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@@ -0,0 +1,927 @@
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+/**
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+ ******************************************************************************
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+ * @file stm32h7xx_hal_dac_ex.c
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+ * @author MCD Application Team
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+ * @brief Extended DAC HAL module driver.
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+ * This file provides firmware functions to manage the extended
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+ * functionalities of the DAC peripheral.
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+ *
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+ *
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+ ******************************************************************************
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+ * @attention
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+ *
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+ * Copyright (c) 2017 STMicroelectronics.
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+ * All rights reserved.
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+ *
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+ * This software is licensed under terms that can be found in the LICENSE file
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+ * in the root directory of this software component.
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+ * If no LICENSE file comes with this software, it is provided AS-IS.
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+ *
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+ ******************************************************************************
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+ @verbatim
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+ ==============================================================================
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+ ##### How to use this driver #####
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+ ==============================================================================
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+ [..]
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+ *** Dual mode IO operation ***
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+ ==============================
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+ [..]
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+ (+) Use HAL_DACEx_DualStart() to enable both channel and start conversion
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+ for dual mode operation.
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+ If software trigger is selected, using HAL_DACEx_DualStart() will start
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+ the conversion of the value previously set by HAL_DACEx_DualSetValue().
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+ (+) Use HAL_DACEx_DualStop() to disable both channel and stop conversion
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+ for dual mode operation.
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+ (+) Use HAL_DACEx_DualStart_DMA() to enable both channel and start conversion
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+ for dual mode operation using DMA to feed DAC converters.
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+ First issued trigger will start the conversion of the value previously
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+ set by HAL_DACEx_DualSetValue().
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+ The same callbacks that are used in single mode are called in dual mode to notify
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+ transfer completion (half complete or complete), errors or underrun.
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+ (+) Use HAL_DACEx_DualStop_DMA() to disable both channel and stop conversion
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+ for dual mode operation using DMA to feed DAC converters.
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+ (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
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+ Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
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+ HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
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+ Channel 1 and Channel 2.
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+ *** Signal generation operation ***
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+ ===================================
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+ [..]
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+ (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
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+ (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
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+
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+ (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
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+ (+) HAL_DACEx_SetUserTrimming to set user trimming value.
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+ (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
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+ after reset, user setting if HAL_DACEx_SetUserTrimming have been used
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+ at least one time after reset).
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+
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+ @endverbatim
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+ ******************************************************************************
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+ */
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+
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+
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+/* Includes ------------------------------------------------------------------*/
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+#include "stm32h7xx_hal.h"
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+
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+/** @addtogroup STM32H7xx_HAL_Driver
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+ * @{
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+ */
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+
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+#ifdef HAL_DAC_MODULE_ENABLED
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+
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+#if defined(DAC1) || defined(DAC2)
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+
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+/** @defgroup DACEx DACEx
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+ * @brief DAC Extended HAL module driver
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+ * @{
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+ */
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+
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+/* Private typedef -----------------------------------------------------------*/
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+/* Private define ------------------------------------------------------------*/
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+
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+/* Delay for DAC minimum trimming time. */
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+/* Note: minimum time needed between two calibration steps */
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+/* The delay below is specified under conditions: */
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+/* - DAC channel output buffer enabled */
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+/* Literal set to maximum value (refer to device datasheet, */
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+/* electrical characteristics, parameter "tTRIM"). */
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+/* Unit: us */
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+#define DAC_DELAY_TRIM_US (50UL) /*!< Delay for DAC minimum trimming time */
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+
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+/* Private macro -------------------------------------------------------------*/
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+/* Private variables ---------------------------------------------------------*/
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+/* Private function prototypes -----------------------------------------------*/
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+/* Exported functions --------------------------------------------------------*/
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+
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+/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
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+ * @{
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+ */
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+
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+/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
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+ * @brief Extended IO operation functions
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+ *
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+@verbatim
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+ ==============================================================================
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+ ##### Extended features functions #####
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+ ==============================================================================
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+ [..] This section provides functions allowing to:
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+ (+) Start conversion.
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+ (+) Stop conversion.
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+ (+) Start conversion and enable DMA transfer.
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+ (+) Stop conversion and disable DMA transfer.
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+ (+) Get result of conversion.
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+ (+) Get result of dual mode conversion.
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+
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+@endverbatim
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+ * @{
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+ */
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+
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+
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+/**
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+ * @brief Enables DAC and starts conversion of both channels.
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+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
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+ * the configuration information for the specified DAC.
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+ * @retval HAL status
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+ */
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+HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
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+{
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+ uint32_t tmp_swtrig = 0UL;
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+
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+ /* Check the DAC peripheral handle */
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+ if (hdac == NULL)
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+ {
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+ return HAL_ERROR;
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+ }
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+
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+
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+ /* Process locked */
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+ __HAL_LOCK(hdac);
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+
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+ /* Change DAC state */
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+ hdac->State = HAL_DAC_STATE_BUSY;
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+
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+ /* Enable the Peripheral */
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+ __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
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+ __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
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+
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+ /* Check if software trigger enabled */
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+ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
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+ {
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+ tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
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+ }
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+ if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)))
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+ {
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+ tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
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+ }
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+ /* Enable the selected DAC software conversion*/
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+ SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig);
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+
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+ /* Change DAC state */
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+ hdac->State = HAL_DAC_STATE_READY;
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+
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+ /* Process unlocked */
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+ __HAL_UNLOCK(hdac);
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+
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+ /* Return function status */
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+ return HAL_OK;
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+}
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+
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+/**
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+ * @brief Disables DAC and stop conversion of both channels.
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+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
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+ * the configuration information for the specified DAC.
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+ * @retval HAL status
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+ */
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+HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
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+{
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+ /* Check the DAC peripheral handle */
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+ if (hdac == NULL)
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+ {
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+ return HAL_ERROR;
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+ }
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+
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+
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+ /* Disable the Peripheral */
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+ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
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+ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
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+
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+ /* Change DAC state */
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+ hdac->State = HAL_DAC_STATE_READY;
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+
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+ /* Return function status */
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+ return HAL_OK;
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+}
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+
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+/**
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+ * @brief Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.
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+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
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+ * the configuration information for the specified DAC.
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+ * @param Channel The DAC channel that will request data from DMA.
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+ * This parameter can be one of the following values:
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+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
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+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
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+ * @param pData The destination peripheral Buffer address.
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+ * @param Length The length of data to be transferred from memory to DAC peripheral
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+ * @param Alignment Specifies the data alignment for DAC channel.
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+ * This parameter can be one of the following values:
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+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
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+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
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+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
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+ * @retval HAL status
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+ */
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+HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
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+ const uint32_t *pData, uint32_t Length, uint32_t Alignment)
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+{
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+ HAL_StatusTypeDef status;
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+ uint32_t tmpreg = 0UL;
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+
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+ /* Check the DAC peripheral handle */
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+ if (hdac == NULL)
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+ {
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+ return HAL_ERROR;
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+ }
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+
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+ /* Check the parameters */
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+ assert_param(IS_DAC_CHANNEL(Channel));
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+ assert_param(IS_DAC_ALIGN(Alignment));
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+
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+ /* Process locked */
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+ __HAL_LOCK(hdac);
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+
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+ /* Change DAC state */
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+ hdac->State = HAL_DAC_STATE_BUSY;
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+
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+ if (Channel == DAC_CHANNEL_1)
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+ {
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+ /* Set the DMA transfer complete callback for channel1 */
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+ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
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+
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+ /* Set the DMA half transfer complete callback for channel1 */
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+ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
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+
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+ /* Set the DMA error callback for channel1 */
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+ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
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+
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+ /* Enable the selected DAC channel1 DMA request */
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+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
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+ }
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+ else
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+ {
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+ /* Set the DMA transfer complete callback for channel2 */
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+ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
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+
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+ /* Set the DMA half transfer complete callback for channel2 */
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+ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
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+
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+ /* Set the DMA error callback for channel2 */
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+ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
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+
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+ /* Enable the selected DAC channel2 DMA request */
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+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
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+ }
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+
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+ switch (Alignment)
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+ {
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+ case DAC_ALIGN_12B_R:
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+ /* Get DHR12R1 address */
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+ tmpreg = (uint32_t)&hdac->Instance->DHR12RD;
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+ break;
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+ case DAC_ALIGN_12B_L:
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+ /* Get DHR12L1 address */
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+ tmpreg = (uint32_t)&hdac->Instance->DHR12LD;
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+ break;
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+ case DAC_ALIGN_8B_R:
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+ /* Get DHR8R1 address */
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+ tmpreg = (uint32_t)&hdac->Instance->DHR8RD;
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ /* Enable the DMA channel */
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+ if (Channel == DAC_CHANNEL_1)
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+ {
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+ /* Enable the DAC DMA underrun interrupt */
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+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
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+
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+ /* Enable the DMA channel */
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+ status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
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+ }
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+ else
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+ {
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+ /* Enable the DAC DMA underrun interrupt */
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+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
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+
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+ /* Enable the DMA channel */
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+ status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
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+ }
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+
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+ /* Process Unlocked */
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+ __HAL_UNLOCK(hdac);
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+
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+ if (status == HAL_OK)
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+ {
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+ /* Enable the Peripheral */
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+ __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
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+ __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
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+ }
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+ else
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+ {
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+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
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+ }
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+
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+ /* Return function status */
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+ return status;
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+}
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+
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+/**
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+ * @brief Disables DAC and stop conversion both channel.
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+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
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+ * the configuration information for the specified DAC.
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+ * @param Channel The DAC channel that requests data from DMA.
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+ * This parameter can be one of the following values:
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+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
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+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
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+ * @retval HAL status
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+ */
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+HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
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+{
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+ HAL_StatusTypeDef status;
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+
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+ /* Check the DAC peripheral handle */
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+ if (hdac == NULL)
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+ {
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+ return HAL_ERROR;
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+ }
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+
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+
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+ /* Disable the selected DAC channel DMA request */
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+ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2 | DAC_CR_DMAEN1);
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+
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+ /* Disable the Peripheral */
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+ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
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+ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
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+
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+ /* Disable the DMA channel */
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+
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+ /* Channel1 is used */
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+ if (Channel == DAC_CHANNEL_1)
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+ {
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+ /* Disable the DMA channel */
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+ status = HAL_DMA_Abort(hdac->DMA_Handle1);
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+
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+ /* Disable the DAC DMA underrun interrupt */
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+ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
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+ }
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+ else
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+ {
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+ /* Disable the DMA channel */
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+ status = HAL_DMA_Abort(hdac->DMA_Handle2);
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+
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+ /* Disable the DAC DMA underrun interrupt */
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+ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
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+ }
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+
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+ /* Check if DMA Channel effectively disabled */
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+ if (status != HAL_OK)
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+ {
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+ /* Update DAC state machine to error */
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+ hdac->State = HAL_DAC_STATE_ERROR;
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+ }
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+ else
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+ {
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+ /* Change DAC state */
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+ hdac->State = HAL_DAC_STATE_READY;
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+ }
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+
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+ /* Return function status */
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+ return status;
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+}
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+
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+
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+/**
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+ * @brief Enable or disable the selected DAC channel wave generation.
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+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
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+ * the configuration information for the specified DAC.
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+ * @param Channel The selected DAC channel.
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+ * This parameter can be one of the following values:
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+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
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+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
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+ * @param Amplitude Select max triangle amplitude.
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+ * This parameter can be one of the following values:
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+ * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
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+ * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
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+ * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
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+ * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
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+ * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
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+ * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
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+ * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
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+ * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
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+ * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
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+ * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
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+ * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
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+ * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
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+ * @retval HAL status
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+ */
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|
|
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
|
|
|
+{
|
|
|
+ /* Check the DAC peripheral handle */
|
|
|
+ if (hdac == NULL)
|
|
|
+ {
|
|
|
+ return HAL_ERROR;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Check the parameters */
|
|
|
+ assert_param(IS_DAC_CHANNEL(Channel));
|
|
|
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
|
|
|
+
|
|
|
+ /* Process locked */
|
|
|
+ __HAL_LOCK(hdac);
|
|
|
+
|
|
|
+ /* Change DAC state */
|
|
|
+ hdac->State = HAL_DAC_STATE_BUSY;
|
|
|
+
|
|
|
+ /* Enable the triangle wave generation for the selected DAC channel */
|
|
|
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
|
|
|
+ (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
|
|
|
+
|
|
|
+ /* Change DAC state */
|
|
|
+ hdac->State = HAL_DAC_STATE_READY;
|
|
|
+
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hdac);
|
|
|
+
|
|
|
+ /* Return function status */
|
|
|
+ return HAL_OK;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Enable or disable the selected DAC channel wave generation.
|
|
|
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified DAC.
|
|
|
+ * @param Channel The selected DAC channel.
|
|
|
+ * This parameter can be one of the following values:
|
|
|
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
|
|
|
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
|
|
|
+ * @param Amplitude Unmask DAC channel LFSR for noise wave generation.
|
|
|
+ * This parameter can be one of the following values:
|
|
|
+ * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
|
|
|
+ * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
|
|
|
+ * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
|
|
|
+ * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
|
|
|
+ * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
|
|
|
+ * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
|
|
|
+ * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
|
|
|
+ * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
|
|
|
+ * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
|
|
|
+ * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
|
|
|
+ * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
|
|
|
+ * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
|
|
|
+ * @retval HAL status
|
|
|
+ */
|
|
|
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
|
|
|
+{
|
|
|
+ /* Check the DAC peripheral handle */
|
|
|
+ if (hdac == NULL)
|
|
|
+ {
|
|
|
+ return HAL_ERROR;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Check the parameters */
|
|
|
+ assert_param(IS_DAC_CHANNEL(Channel));
|
|
|
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
|
|
|
+
|
|
|
+ /* Process locked */
|
|
|
+ __HAL_LOCK(hdac);
|
|
|
+
|
|
|
+ /* Change DAC state */
|
|
|
+ hdac->State = HAL_DAC_STATE_BUSY;
|
|
|
+
|
|
|
+ /* Enable the noise wave generation for the selected DAC channel */
|
|
|
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
|
|
|
+ (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
|
|
|
+
|
|
|
+ /* Change DAC state */
|
|
|
+ hdac->State = HAL_DAC_STATE_READY;
|
|
|
+
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hdac);
|
|
|
+
|
|
|
+ /* Return function status */
|
|
|
+ return HAL_OK;
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Set the specified data holding register value for dual DAC channel.
|
|
|
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified DAC.
|
|
|
+ * @param Alignment Specifies the data alignment for dual channel DAC.
|
|
|
+ * This parameter can be one of the following values:
|
|
|
+ * DAC_ALIGN_8B_R: 8bit right data alignment selected
|
|
|
+ * DAC_ALIGN_12B_L: 12bit left data alignment selected
|
|
|
+ * DAC_ALIGN_12B_R: 12bit right data alignment selected
|
|
|
+ * @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
|
|
|
+ * @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register.
|
|
|
+ * @note In dual mode, a unique register access is required to write in both
|
|
|
+ * DAC channels at the same time.
|
|
|
+ * @retval HAL status
|
|
|
+ */
|
|
|
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
|
|
|
+{
|
|
|
+ uint32_t data;
|
|
|
+ uint32_t tmp;
|
|
|
+
|
|
|
+ /* Check the DAC peripheral handle */
|
|
|
+ if (hdac == NULL)
|
|
|
+ {
|
|
|
+ return HAL_ERROR;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Check the parameters */
|
|
|
+ assert_param(IS_DAC_ALIGN(Alignment));
|
|
|
+ assert_param(IS_DAC_DATA(Data1));
|
|
|
+ assert_param(IS_DAC_DATA(Data2));
|
|
|
+
|
|
|
+ /* Calculate and set dual DAC data holding register value */
|
|
|
+ if (Alignment == DAC_ALIGN_8B_R)
|
|
|
+ {
|
|
|
+ data = ((uint32_t)Data2 << 8U) | Data1;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ data = ((uint32_t)Data2 << 16U) | Data1;
|
|
|
+ }
|
|
|
+
|
|
|
+ tmp = (uint32_t)hdac->Instance;
|
|
|
+ tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
|
|
|
+
|
|
|
+ /* Set the dual DAC selected data holding register */
|
|
|
+ *(__IO uint32_t *)tmp = data;
|
|
|
+
|
|
|
+ /* Return function status */
|
|
|
+ return HAL_OK;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Conversion complete callback in non-blocking mode for Channel2.
|
|
|
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified DAC.
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
|
|
|
+{
|
|
|
+ /* Prevent unused argument(s) compilation warning */
|
|
|
+ UNUSED(hdac);
|
|
|
+
|
|
|
+ /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
+ the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
|
|
|
+ */
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2.
|
|
|
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified DAC.
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
|
|
|
+{
|
|
|
+ /* Prevent unused argument(s) compilation warning */
|
|
|
+ UNUSED(hdac);
|
|
|
+
|
|
|
+ /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
+ the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
|
|
|
+ */
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Error DAC callback for Channel2.
|
|
|
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified DAC.
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
|
|
|
+{
|
|
|
+ /* Prevent unused argument(s) compilation warning */
|
|
|
+ UNUSED(hdac);
|
|
|
+
|
|
|
+ /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
+ the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
|
|
|
+ */
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief DMA underrun DAC callback for Channel2.
|
|
|
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified DAC.
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
|
|
|
+{
|
|
|
+ /* Prevent unused argument(s) compilation warning */
|
|
|
+ UNUSED(hdac);
|
|
|
+
|
|
|
+ /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
+ the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
|
|
|
+ */
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Run the self calibration of one DAC channel.
|
|
|
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified DAC.
|
|
|
+ * @param sConfig DAC channel configuration structure.
|
|
|
+ * @param Channel The selected DAC channel.
|
|
|
+ * This parameter can be one of the following values:
|
|
|
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
|
|
|
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
|
|
|
+ * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
|
|
|
+ * @retval HAL status
|
|
|
+ * @note Calibration runs about 7 ms.
|
|
|
+ */
|
|
|
+HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
|
|
|
+{
|
|
|
+ HAL_StatusTypeDef status = HAL_OK;
|
|
|
+
|
|
|
+ uint32_t trimmingvalue;
|
|
|
+ uint32_t delta;
|
|
|
+ __IO uint32_t wait_loop_index;
|
|
|
+
|
|
|
+ /* store/restore channel configuration structure purpose */
|
|
|
+ uint32_t oldmodeconfiguration;
|
|
|
+
|
|
|
+ /* Check the parameters */
|
|
|
+ assert_param(IS_DAC_CHANNEL(Channel));
|
|
|
+
|
|
|
+ /* Check the DAC handle allocation */
|
|
|
+ /* Check if DAC running */
|
|
|
+ if ((hdac == NULL) || (sConfig == NULL))
|
|
|
+ {
|
|
|
+ status = HAL_ERROR;
|
|
|
+ }
|
|
|
+ else if (hdac->State == HAL_DAC_STATE_BUSY)
|
|
|
+ {
|
|
|
+ status = HAL_ERROR;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ /* Process locked */
|
|
|
+ __HAL_LOCK(hdac);
|
|
|
+
|
|
|
+ /* Store configuration */
|
|
|
+ oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << (Channel & 0x10UL)));
|
|
|
+
|
|
|
+ /* Disable the selected DAC channel */
|
|
|
+ CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL)));
|
|
|
+
|
|
|
+ /* Set mode in MCR for calibration */
|
|
|
+ MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U);
|
|
|
+
|
|
|
+ /* Enable the selected DAC channel calibration */
|
|
|
+ /* i.e. set DAC_CR_CENx bit */
|
|
|
+ SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
|
|
|
+
|
|
|
+ /* Init trimming counter */
|
|
|
+ /* Medium value */
|
|
|
+ trimmingvalue = 16UL;
|
|
|
+ delta = 8UL;
|
|
|
+ while (delta != 0UL)
|
|
|
+ {
|
|
|
+ /* Set candidate trimming */
|
|
|
+ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
|
|
|
+
|
|
|
+ /* Wait minimum time needed between two calibration steps (OTRIM) */
|
|
|
+ /* Wait loop initialization and execution */
|
|
|
+ /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
|
|
|
+ /* 32 bits register capacity and handle low frequency. */
|
|
|
+ wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
|
|
|
+ while (wait_loop_index != 0UL)
|
|
|
+ {
|
|
|
+ wait_loop_index--;
|
|
|
+ }
|
|
|
+
|
|
|
+ if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
|
|
|
+ {
|
|
|
+ /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
|
|
|
+ trimmingvalue -= delta;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ /* DAC_SR_CAL_FLAGx is LOW try lower trimming */
|
|
|
+ trimmingvalue += delta;
|
|
|
+ }
|
|
|
+ delta >>= 1UL;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Still need to check if right calibration is current value or one step below */
|
|
|
+ /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1 */
|
|
|
+ /* Set candidate trimming */
|
|
|
+ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
|
|
|
+
|
|
|
+ /* Wait minimum time needed between two calibration steps (OTRIM) */
|
|
|
+ /* Wait loop initialization and execution */
|
|
|
+ /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
|
|
|
+ /* 32 bits register capacity and handle low frequency. */
|
|
|
+ wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
|
|
|
+ while (wait_loop_index != 0UL)
|
|
|
+ {
|
|
|
+ wait_loop_index--;
|
|
|
+ }
|
|
|
+
|
|
|
+ if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
|
|
|
+ {
|
|
|
+ /* Trimming is actually one value more */
|
|
|
+ trimmingvalue++;
|
|
|
+ /* Set right trimming */
|
|
|
+ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Disable the selected DAC channel calibration */
|
|
|
+ /* i.e. clear DAC_CR_CENx bit */
|
|
|
+ CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
|
|
|
+
|
|
|
+ sConfig->DAC_TrimmingValue = trimmingvalue;
|
|
|
+ sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
|
|
|
+
|
|
|
+ /* Restore configuration */
|
|
|
+ MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration);
|
|
|
+
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hdac);
|
|
|
+ }
|
|
|
+
|
|
|
+ return status;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Set the trimming mode and trimming value (user trimming mode applied).
|
|
|
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified DAC.
|
|
|
+ * @param sConfig DAC configuration structure updated with new DAC trimming value.
|
|
|
+ * @param Channel The selected DAC channel.
|
|
|
+ * This parameter can be one of the following values:
|
|
|
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
|
|
|
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
|
|
|
+ * @param NewTrimmingValue DAC new trimming value
|
|
|
+ * @retval HAL status
|
|
|
+ */
|
|
|
+HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
|
|
|
+ uint32_t NewTrimmingValue)
|
|
|
+{
|
|
|
+ HAL_StatusTypeDef status = HAL_OK;
|
|
|
+
|
|
|
+ /* Check the parameters */
|
|
|
+ assert_param(IS_DAC_CHANNEL(Channel));
|
|
|
+ assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
|
|
|
+
|
|
|
+ /* Check the DAC handle and channel configuration struct allocation */
|
|
|
+ if ((hdac == NULL) || (sConfig == NULL))
|
|
|
+ {
|
|
|
+ status = HAL_ERROR;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ /* Process locked */
|
|
|
+ __HAL_LOCK(hdac);
|
|
|
+
|
|
|
+ /* Set new trimming */
|
|
|
+ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL)));
|
|
|
+
|
|
|
+ /* Update trimming mode */
|
|
|
+ sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
|
|
|
+ sConfig->DAC_TrimmingValue = NewTrimmingValue;
|
|
|
+
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hdac);
|
|
|
+ }
|
|
|
+ return status;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Return the DAC trimming value.
|
|
|
+ * @param hdac DAC handle
|
|
|
+ * @param Channel The selected DAC channel.
|
|
|
+ * This parameter can be one of the following values:
|
|
|
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
|
|
|
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
|
|
|
+ * @retval Trimming value : range: 0->31
|
|
|
+ *
|
|
|
+ */
|
|
|
+uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel)
|
|
|
+{
|
|
|
+ /* Check the parameter */
|
|
|
+ assert_param(IS_DAC_CHANNEL(Channel));
|
|
|
+
|
|
|
+ /* Retrieve trimming */
|
|
|
+ return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL));
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
|
|
|
+ * @brief Extended Peripheral Control functions
|
|
|
+ *
|
|
|
+@verbatim
|
|
|
+ ==============================================================================
|
|
|
+ ##### Peripheral Control functions #####
|
|
|
+ ==============================================================================
|
|
|
+ [..] This section provides functions allowing to:
|
|
|
+ (+) Set the specified data holding register value for DAC channel.
|
|
|
+
|
|
|
+@endverbatim
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Return the last data output value of the selected DAC channel.
|
|
|
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified DAC.
|
|
|
+ * @retval The selected DAC channel data output value.
|
|
|
+ */
|
|
|
+uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac)
|
|
|
+{
|
|
|
+ uint32_t tmp = 0UL;
|
|
|
+
|
|
|
+ tmp |= hdac->Instance->DOR1;
|
|
|
+
|
|
|
+ tmp |= hdac->Instance->DOR2 << 16UL;
|
|
|
+
|
|
|
+ /* Returns the DAC channel data output register value */
|
|
|
+ return tmp;
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/* Private functions ---------------------------------------------------------*/
|
|
|
+/** @defgroup DACEx_Private_Functions DACEx private functions
|
|
|
+ * @brief Extended private functions
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief DMA conversion complete callback.
|
|
|
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified DMA module.
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
|
|
|
+{
|
|
|
+ DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
|
+
|
|
|
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
|
|
+ hdac->ConvCpltCallbackCh2(hdac);
|
|
|
+#else
|
|
|
+ HAL_DACEx_ConvCpltCallbackCh2(hdac);
|
|
|
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
|
|
+
|
|
|
+ hdac->State = HAL_DAC_STATE_READY;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief DMA half transfer complete callback.
|
|
|
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified DMA module.
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
|
|
|
+{
|
|
|
+ DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
|
+ /* Conversion complete callback */
|
|
|
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
|
|
+ hdac->ConvHalfCpltCallbackCh2(hdac);
|
|
|
+#else
|
|
|
+ HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
|
|
|
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief DMA error callback.
|
|
|
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified DMA module.
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
|
|
|
+{
|
|
|
+ DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
|
+
|
|
|
+ /* Set DAC error code to DMA error */
|
|
|
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
|
|
|
+
|
|
|
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
|
|
+ hdac->ErrorCallbackCh2(hdac);
|
|
|
+#else
|
|
|
+ HAL_DACEx_ErrorCallbackCh2(hdac);
|
|
|
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
|
|
+
|
|
|
+ hdac->State = HAL_DAC_STATE_READY;
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+#endif /* DAC1 || DAC2 */
|
|
|
+
|
|
|
+#endif /* HAL_DAC_MODULE_ENABLED */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
Bartosz Jakubski