OZE_Sensor.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000298 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00018718 080002a0 080002a0 000012a0 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000220 080189b8 080189b8 000199b8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM 00000008 08018bd8 08018bd8 00019bd8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .init_array 00000004 08018be0 08018be0 00019be0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .fini_array 00000004 08018be4 08018be4 00019be4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 6 .data 000000a4 24000000 08018be8 0001a000 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .bss 000130f4 240000c0 08018c8c 0001a0c0 2**5 ALLOC 8 ._user_heap_stack 00000604 240131b4 08018c8c 0001a1b4 2**0 ALLOC 9 .ARM.attributes 0000002e 00000000 00000000 0001a0a4 2**0 CONTENTS, READONLY 10 .debug_info 000353b3 00000000 00000000 0001a0d2 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_abbrev 000065d9 00000000 00000000 0004f485 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_aranges 000024e8 00000000 00000000 00055a60 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_macro 0003fa94 00000000 00000000 00057f48 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_line 000318af 00000000 00000000 000979dc 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_str 0018879d 00000000 00000000 000c928b 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .comment 00000043 00000000 00000000 00251a28 2**0 CONTENTS, READONLY 17 .debug_rnglists 00001c67 00000000 00000000 00251a6b 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_frame 0000a3a8 00000000 00000000 002536d4 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_line_str 00000066 00000000 00000000 0025da7c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080002a0 <__do_global_dtors_aux>: 80002a0: b510 push {r4, lr} 80002a2: 4c05 ldr r4, [pc, #20] @ (80002b8 <__do_global_dtors_aux+0x18>) 80002a4: 7823 ldrb r3, [r4, #0] 80002a6: b933 cbnz r3, 80002b6 <__do_global_dtors_aux+0x16> 80002a8: 4b04 ldr r3, [pc, #16] @ (80002bc <__do_global_dtors_aux+0x1c>) 80002aa: b113 cbz r3, 80002b2 <__do_global_dtors_aux+0x12> 80002ac: 4804 ldr r0, [pc, #16] @ (80002c0 <__do_global_dtors_aux+0x20>) 80002ae: f3af 8000 nop.w 80002b2: 2301 movs r3, #1 80002b4: 7023 strb r3, [r4, #0] 80002b6: bd10 pop {r4, pc} 80002b8: 240000c0 .word 0x240000c0 80002bc: 00000000 .word 0x00000000 80002c0: 080189a0 .word 0x080189a0 080002c4 : 80002c4: b508 push {r3, lr} 80002c6: 4b03 ldr r3, [pc, #12] @ (80002d4 ) 80002c8: b11b cbz r3, 80002d2 80002ca: 4903 ldr r1, [pc, #12] @ (80002d8 ) 80002cc: 4803 ldr r0, [pc, #12] @ (80002dc ) 80002ce: f3af 8000 nop.w 80002d2: bd08 pop {r3, pc} 80002d4: 00000000 .word 0x00000000 80002d8: 240000c4 .word 0x240000c4 80002dc: 080189a0 .word 0x080189a0 080002e0 : 80002e0: f001 01ff and.w r1, r1, #255 @ 0xff 80002e4: 2a10 cmp r2, #16 80002e6: db2b blt.n 8000340 80002e8: f010 0f07 tst.w r0, #7 80002ec: d008 beq.n 8000300 80002ee: f810 3b01 ldrb.w r3, [r0], #1 80002f2: 3a01 subs r2, #1 80002f4: 428b cmp r3, r1 80002f6: d02d beq.n 8000354 80002f8: f010 0f07 tst.w r0, #7 80002fc: b342 cbz r2, 8000350 80002fe: d1f6 bne.n 80002ee 8000300: b4f0 push {r4, r5, r6, r7} 8000302: ea41 2101 orr.w r1, r1, r1, lsl #8 8000306: ea41 4101 orr.w r1, r1, r1, lsl #16 800030a: f022 0407 bic.w r4, r2, #7 800030e: f07f 0700 mvns.w r7, #0 8000312: 2300 movs r3, #0 8000314: e8f0 5602 ldrd r5, r6, [r0], #8 8000318: 3c08 subs r4, #8 800031a: ea85 0501 eor.w r5, r5, r1 800031e: ea86 0601 eor.w r6, r6, r1 8000322: fa85 f547 uadd8 r5, r5, r7 8000326: faa3 f587 sel r5, r3, r7 800032a: fa86 f647 uadd8 r6, r6, r7 800032e: faa5 f687 sel r6, r5, r7 8000332: b98e cbnz r6, 8000358 8000334: d1ee bne.n 8000314 8000336: bcf0 pop {r4, r5, r6, r7} 8000338: f001 01ff and.w r1, r1, #255 @ 0xff 800033c: f002 0207 and.w r2, r2, #7 8000340: b132 cbz r2, 8000350 8000342: f810 3b01 ldrb.w r3, [r0], #1 8000346: 3a01 subs r2, #1 8000348: ea83 0301 eor.w r3, r3, r1 800034c: b113 cbz r3, 8000354 800034e: d1f8 bne.n 8000342 8000350: 2000 movs r0, #0 8000352: 4770 bx lr 8000354: 3801 subs r0, #1 8000356: 4770 bx lr 8000358: 2d00 cmp r5, #0 800035a: bf06 itte eq 800035c: 4635 moveq r5, r6 800035e: 3803 subeq r0, #3 8000360: 3807 subne r0, #7 8000362: f015 0f01 tst.w r5, #1 8000366: d107 bne.n 8000378 8000368: 3001 adds r0, #1 800036a: f415 7f80 tst.w r5, #256 @ 0x100 800036e: bf02 ittt eq 8000370: 3001 addeq r0, #1 8000372: f415 3fc0 tsteq.w r5, #98304 @ 0x18000 8000376: 3001 addeq r0, #1 8000378: bcf0 pop {r4, r5, r6, r7} 800037a: 3801 subs r0, #1 800037c: 4770 bx lr 800037e: bf00 nop 08000380 <__aeabi_uldivmod>: 8000380: b953 cbnz r3, 8000398 <__aeabi_uldivmod+0x18> 8000382: b94a cbnz r2, 8000398 <__aeabi_uldivmod+0x18> 8000384: 2900 cmp r1, #0 8000386: bf08 it eq 8000388: 2800 cmpeq r0, #0 800038a: bf1c itt ne 800038c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8000390: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8000394: f000 b96a b.w 800066c <__aeabi_idiv0> 8000398: f1ad 0c08 sub.w ip, sp, #8 800039c: e96d ce04 strd ip, lr, [sp, #-16]! 80003a0: f000 f806 bl 80003b0 <__udivmoddi4> 80003a4: f8dd e004 ldr.w lr, [sp, #4] 80003a8: e9dd 2302 ldrd r2, r3, [sp, #8] 80003ac: b004 add sp, #16 80003ae: 4770 bx lr 080003b0 <__udivmoddi4>: 80003b0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80003b4: 9d08 ldr r5, [sp, #32] 80003b6: 460c mov r4, r1 80003b8: 2b00 cmp r3, #0 80003ba: d14e bne.n 800045a <__udivmoddi4+0xaa> 80003bc: 4694 mov ip, r2 80003be: 458c cmp ip, r1 80003c0: 4686 mov lr, r0 80003c2: fab2 f282 clz r2, r2 80003c6: d962 bls.n 800048e <__udivmoddi4+0xde> 80003c8: b14a cbz r2, 80003de <__udivmoddi4+0x2e> 80003ca: f1c2 0320 rsb r3, r2, #32 80003ce: 4091 lsls r1, r2 80003d0: fa20 f303 lsr.w r3, r0, r3 80003d4: fa0c fc02 lsl.w ip, ip, r2 80003d8: 4319 orrs r1, r3 80003da: fa00 fe02 lsl.w lr, r0, r2 80003de: ea4f 471c mov.w r7, ip, lsr #16 80003e2: fa1f f68c uxth.w r6, ip 80003e6: fbb1 f4f7 udiv r4, r1, r7 80003ea: ea4f 431e mov.w r3, lr, lsr #16 80003ee: fb07 1114 mls r1, r7, r4, r1 80003f2: ea43 4301 orr.w r3, r3, r1, lsl #16 80003f6: fb04 f106 mul.w r1, r4, r6 80003fa: 4299 cmp r1, r3 80003fc: d90a bls.n 8000414 <__udivmoddi4+0x64> 80003fe: eb1c 0303 adds.w r3, ip, r3 8000402: f104 30ff add.w r0, r4, #4294967295 @ 0xffffffff 8000406: f080 8112 bcs.w 800062e <__udivmoddi4+0x27e> 800040a: 4299 cmp r1, r3 800040c: f240 810f bls.w 800062e <__udivmoddi4+0x27e> 8000410: 3c02 subs r4, #2 8000412: 4463 add r3, ip 8000414: 1a59 subs r1, r3, r1 8000416: fa1f f38e uxth.w r3, lr 800041a: fbb1 f0f7 udiv r0, r1, r7 800041e: fb07 1110 mls r1, r7, r0, r1 8000422: ea43 4301 orr.w r3, r3, r1, lsl #16 8000426: fb00 f606 mul.w r6, r0, r6 800042a: 429e cmp r6, r3 800042c: d90a bls.n 8000444 <__udivmoddi4+0x94> 800042e: eb1c 0303 adds.w r3, ip, r3 8000432: f100 31ff add.w r1, r0, #4294967295 @ 0xffffffff 8000436: f080 80fc bcs.w 8000632 <__udivmoddi4+0x282> 800043a: 429e cmp r6, r3 800043c: f240 80f9 bls.w 8000632 <__udivmoddi4+0x282> 8000440: 4463 add r3, ip 8000442: 3802 subs r0, #2 8000444: 1b9b subs r3, r3, r6 8000446: ea40 4004 orr.w r0, r0, r4, lsl #16 800044a: 2100 movs r1, #0 800044c: b11d cbz r5, 8000456 <__udivmoddi4+0xa6> 800044e: 40d3 lsrs r3, r2 8000450: 2200 movs r2, #0 8000452: e9c5 3200 strd r3, r2, [r5] 8000456: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800045a: 428b cmp r3, r1 800045c: d905 bls.n 800046a <__udivmoddi4+0xba> 800045e: b10d cbz r5, 8000464 <__udivmoddi4+0xb4> 8000460: e9c5 0100 strd r0, r1, [r5] 8000464: 2100 movs r1, #0 8000466: 4608 mov r0, r1 8000468: e7f5 b.n 8000456 <__udivmoddi4+0xa6> 800046a: fab3 f183 clz r1, r3 800046e: 2900 cmp r1, #0 8000470: d146 bne.n 8000500 <__udivmoddi4+0x150> 8000472: 42a3 cmp r3, r4 8000474: d302 bcc.n 800047c <__udivmoddi4+0xcc> 8000476: 4290 cmp r0, r2 8000478: f0c0 80f0 bcc.w 800065c <__udivmoddi4+0x2ac> 800047c: 1a86 subs r6, r0, r2 800047e: eb64 0303 sbc.w r3, r4, r3 8000482: 2001 movs r0, #1 8000484: 2d00 cmp r5, #0 8000486: d0e6 beq.n 8000456 <__udivmoddi4+0xa6> 8000488: e9c5 6300 strd r6, r3, [r5] 800048c: e7e3 b.n 8000456 <__udivmoddi4+0xa6> 800048e: 2a00 cmp r2, #0 8000490: f040 8090 bne.w 80005b4 <__udivmoddi4+0x204> 8000494: eba1 040c sub.w r4, r1, ip 8000498: ea4f 481c mov.w r8, ip, lsr #16 800049c: fa1f f78c uxth.w r7, ip 80004a0: 2101 movs r1, #1 80004a2: fbb4 f6f8 udiv r6, r4, r8 80004a6: ea4f 431e mov.w r3, lr, lsr #16 80004aa: fb08 4416 mls r4, r8, r6, r4 80004ae: ea43 4304 orr.w r3, r3, r4, lsl #16 80004b2: fb07 f006 mul.w r0, r7, r6 80004b6: 4298 cmp r0, r3 80004b8: d908 bls.n 80004cc <__udivmoddi4+0x11c> 80004ba: eb1c 0303 adds.w r3, ip, r3 80004be: f106 34ff add.w r4, r6, #4294967295 @ 0xffffffff 80004c2: d202 bcs.n 80004ca <__udivmoddi4+0x11a> 80004c4: 4298 cmp r0, r3 80004c6: f200 80cd bhi.w 8000664 <__udivmoddi4+0x2b4> 80004ca: 4626 mov r6, r4 80004cc: 1a1c subs r4, r3, r0 80004ce: fa1f f38e uxth.w r3, lr 80004d2: fbb4 f0f8 udiv r0, r4, r8 80004d6: fb08 4410 mls r4, r8, r0, r4 80004da: ea43 4304 orr.w r3, r3, r4, lsl #16 80004de: fb00 f707 mul.w r7, r0, r7 80004e2: 429f cmp r7, r3 80004e4: d908 bls.n 80004f8 <__udivmoddi4+0x148> 80004e6: eb1c 0303 adds.w r3, ip, r3 80004ea: f100 34ff add.w r4, r0, #4294967295 @ 0xffffffff 80004ee: d202 bcs.n 80004f6 <__udivmoddi4+0x146> 80004f0: 429f cmp r7, r3 80004f2: f200 80b0 bhi.w 8000656 <__udivmoddi4+0x2a6> 80004f6: 4620 mov r0, r4 80004f8: 1bdb subs r3, r3, r7 80004fa: ea40 4006 orr.w r0, r0, r6, lsl #16 80004fe: e7a5 b.n 800044c <__udivmoddi4+0x9c> 8000500: f1c1 0620 rsb r6, r1, #32 8000504: 408b lsls r3, r1 8000506: fa22 f706 lsr.w r7, r2, r6 800050a: 431f orrs r7, r3 800050c: fa20 fc06 lsr.w ip, r0, r6 8000510: fa04 f301 lsl.w r3, r4, r1 8000514: ea43 030c orr.w r3, r3, ip 8000518: 40f4 lsrs r4, r6 800051a: fa00 f801 lsl.w r8, r0, r1 800051e: 0c38 lsrs r0, r7, #16 8000520: ea4f 4913 mov.w r9, r3, lsr #16 8000524: fbb4 fef0 udiv lr, r4, r0 8000528: fa1f fc87 uxth.w ip, r7 800052c: fb00 441e mls r4, r0, lr, r4 8000530: ea49 4404 orr.w r4, r9, r4, lsl #16 8000534: fb0e f90c mul.w r9, lr, ip 8000538: 45a1 cmp r9, r4 800053a: fa02 f201 lsl.w r2, r2, r1 800053e: d90a bls.n 8000556 <__udivmoddi4+0x1a6> 8000540: 193c adds r4, r7, r4 8000542: f10e 3aff add.w sl, lr, #4294967295 @ 0xffffffff 8000546: f080 8084 bcs.w 8000652 <__udivmoddi4+0x2a2> 800054a: 45a1 cmp r9, r4 800054c: f240 8081 bls.w 8000652 <__udivmoddi4+0x2a2> 8000550: f1ae 0e02 sub.w lr, lr, #2 8000554: 443c add r4, r7 8000556: eba4 0409 sub.w r4, r4, r9 800055a: fa1f f983 uxth.w r9, r3 800055e: fbb4 f3f0 udiv r3, r4, r0 8000562: fb00 4413 mls r4, r0, r3, r4 8000566: ea49 4404 orr.w r4, r9, r4, lsl #16 800056a: fb03 fc0c mul.w ip, r3, ip 800056e: 45a4 cmp ip, r4 8000570: d907 bls.n 8000582 <__udivmoddi4+0x1d2> 8000572: 193c adds r4, r7, r4 8000574: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 8000578: d267 bcs.n 800064a <__udivmoddi4+0x29a> 800057a: 45a4 cmp ip, r4 800057c: d965 bls.n 800064a <__udivmoddi4+0x29a> 800057e: 3b02 subs r3, #2 8000580: 443c add r4, r7 8000582: ea43 400e orr.w r0, r3, lr, lsl #16 8000586: fba0 9302 umull r9, r3, r0, r2 800058a: eba4 040c sub.w r4, r4, ip 800058e: 429c cmp r4, r3 8000590: 46ce mov lr, r9 8000592: 469c mov ip, r3 8000594: d351 bcc.n 800063a <__udivmoddi4+0x28a> 8000596: d04e beq.n 8000636 <__udivmoddi4+0x286> 8000598: b155 cbz r5, 80005b0 <__udivmoddi4+0x200> 800059a: ebb8 030e subs.w r3, r8, lr 800059e: eb64 040c sbc.w r4, r4, ip 80005a2: fa04 f606 lsl.w r6, r4, r6 80005a6: 40cb lsrs r3, r1 80005a8: 431e orrs r6, r3 80005aa: 40cc lsrs r4, r1 80005ac: e9c5 6400 strd r6, r4, [r5] 80005b0: 2100 movs r1, #0 80005b2: e750 b.n 8000456 <__udivmoddi4+0xa6> 80005b4: f1c2 0320 rsb r3, r2, #32 80005b8: fa20 f103 lsr.w r1, r0, r3 80005bc: fa0c fc02 lsl.w ip, ip, r2 80005c0: fa24 f303 lsr.w r3, r4, r3 80005c4: 4094 lsls r4, r2 80005c6: 430c orrs r4, r1 80005c8: ea4f 481c mov.w r8, ip, lsr #16 80005cc: fa00 fe02 lsl.w lr, r0, r2 80005d0: fa1f f78c uxth.w r7, ip 80005d4: fbb3 f0f8 udiv r0, r3, r8 80005d8: fb08 3110 mls r1, r8, r0, r3 80005dc: 0c23 lsrs r3, r4, #16 80005de: ea43 4301 orr.w r3, r3, r1, lsl #16 80005e2: fb00 f107 mul.w r1, r0, r7 80005e6: 4299 cmp r1, r3 80005e8: d908 bls.n 80005fc <__udivmoddi4+0x24c> 80005ea: eb1c 0303 adds.w r3, ip, r3 80005ee: f100 36ff add.w r6, r0, #4294967295 @ 0xffffffff 80005f2: d22c bcs.n 800064e <__udivmoddi4+0x29e> 80005f4: 4299 cmp r1, r3 80005f6: d92a bls.n 800064e <__udivmoddi4+0x29e> 80005f8: 3802 subs r0, #2 80005fa: 4463 add r3, ip 80005fc: 1a5b subs r3, r3, r1 80005fe: b2a4 uxth r4, r4 8000600: fbb3 f1f8 udiv r1, r3, r8 8000604: fb08 3311 mls r3, r8, r1, r3 8000608: ea44 4403 orr.w r4, r4, r3, lsl #16 800060c: fb01 f307 mul.w r3, r1, r7 8000610: 42a3 cmp r3, r4 8000612: d908 bls.n 8000626 <__udivmoddi4+0x276> 8000614: eb1c 0404 adds.w r4, ip, r4 8000618: f101 36ff add.w r6, r1, #4294967295 @ 0xffffffff 800061c: d213 bcs.n 8000646 <__udivmoddi4+0x296> 800061e: 42a3 cmp r3, r4 8000620: d911 bls.n 8000646 <__udivmoddi4+0x296> 8000622: 3902 subs r1, #2 8000624: 4464 add r4, ip 8000626: 1ae4 subs r4, r4, r3 8000628: ea41 4100 orr.w r1, r1, r0, lsl #16 800062c: e739 b.n 80004a2 <__udivmoddi4+0xf2> 800062e: 4604 mov r4, r0 8000630: e6f0 b.n 8000414 <__udivmoddi4+0x64> 8000632: 4608 mov r0, r1 8000634: e706 b.n 8000444 <__udivmoddi4+0x94> 8000636: 45c8 cmp r8, r9 8000638: d2ae bcs.n 8000598 <__udivmoddi4+0x1e8> 800063a: ebb9 0e02 subs.w lr, r9, r2 800063e: eb63 0c07 sbc.w ip, r3, r7 8000642: 3801 subs r0, #1 8000644: e7a8 b.n 8000598 <__udivmoddi4+0x1e8> 8000646: 4631 mov r1, r6 8000648: e7ed b.n 8000626 <__udivmoddi4+0x276> 800064a: 4603 mov r3, r0 800064c: e799 b.n 8000582 <__udivmoddi4+0x1d2> 800064e: 4630 mov r0, r6 8000650: e7d4 b.n 80005fc <__udivmoddi4+0x24c> 8000652: 46d6 mov lr, sl 8000654: e77f b.n 8000556 <__udivmoddi4+0x1a6> 8000656: 4463 add r3, ip 8000658: 3802 subs r0, #2 800065a: e74d b.n 80004f8 <__udivmoddi4+0x148> 800065c: 4606 mov r6, r0 800065e: 4623 mov r3, r4 8000660: 4608 mov r0, r1 8000662: e70f b.n 8000484 <__udivmoddi4+0xd4> 8000664: 3e02 subs r6, #2 8000666: 4463 add r3, ip 8000668: e730 b.n 80004cc <__udivmoddi4+0x11c> 800066a: bf00 nop 0800066c <__aeabi_idiv0>: 800066c: 4770 bx lr 800066e: bf00 nop 08000670 : /* Hook prototypes */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName); /* USER CODE BEGIN 4 */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName) { 8000670: b480 push {r7} 8000672: b083 sub sp, #12 8000674: af00 add r7, sp, #0 8000676: 6078 str r0, [r7, #4] 8000678: 6039 str r1, [r7, #0] /* Run time stack overflow checking is performed if configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is called if a stack overflow is detected. */ } 800067a: bf00 nop 800067c: 370c adds r7, #12 800067e: 46bd mov sp, r7 8000680: f85d 7b04 ldr.w r7, [sp], #4 8000684: 4770 bx lr ... 08000688 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 8000688: b480 push {r7} 800068a: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 800068c: f3bf 8f4f dsb sy } 8000690: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 8000692: 4b06 ldr r3, [pc, #24] @ (80006ac <__NVIC_SystemReset+0x24>) 8000694: 68db ldr r3, [r3, #12] 8000696: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800069a: 4904 ldr r1, [pc, #16] @ (80006ac <__NVIC_SystemReset+0x24>) 800069c: 4b04 ldr r3, [pc, #16] @ (80006b0 <__NVIC_SystemReset+0x28>) 800069e: 4313 orrs r3, r2 80006a0: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 80006a2: f3bf 8f4f dsb sy } 80006a6: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 80006a8: bf00 nop 80006aa: e7fd b.n 80006a8 <__NVIC_SystemReset+0x20> 80006ac: e000ed00 .word 0xe000ed00 80006b0: 05fa0004 .word 0x05fa0004 080006b4 : \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { 80006b4: b480 push {r7} 80006b6: b083 sub sp, #12 80006b8: af00 add r7, sp, #0 80006ba: 6078 str r0, [r7, #4] if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 80006bc: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000 80006c0: f8d3 3e80 ldr.w r3, [r3, #3712] @ 0xe80 80006c4: f003 0301 and.w r3, r3, #1 80006c8: 2b00 cmp r3, #0 80006ca: d013 beq.n 80006f4 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 80006cc: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000 80006d0: f8d3 3e00 ldr.w r3, [r3, #3584] @ 0xe00 80006d4: f003 0301 and.w r3, r3, #1 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 80006d8: 2b00 cmp r3, #0 80006da: d00b beq.n 80006f4 { while (ITM->PORT[0U].u32 == 0UL) 80006dc: e000 b.n 80006e0 { __NOP(); 80006de: bf00 nop while (ITM->PORT[0U].u32 == 0UL) 80006e0: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000 80006e4: 681b ldr r3, [r3, #0] 80006e6: 2b00 cmp r3, #0 80006e8: d0f9 beq.n 80006de } ITM->PORT[0U].u8 = (uint8_t)ch; 80006ea: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000 80006ee: 687a ldr r2, [r7, #4] 80006f0: b2d2 uxtb r2, r2 80006f2: 701a strb r2, [r3, #0] } return (ch); 80006f4: 687b ldr r3, [r7, #4] } 80006f6: 4618 mov r0, r3 80006f8: 370c adds r7, #12 80006fa: 46bd mov sp, r7 80006fc: f85d 7b04 ldr.w r7, [sp], #4 8000700: 4770 bx lr 08000702 <__io_putchar>: /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ int __io_putchar(int ch) { 8000702: b580 push {r7, lr} 8000704: b082 sub sp, #8 8000706: af00 add r7, sp, #0 8000708: 6078 str r0, [r7, #4] #if UART_TASK_LOGS // HAL_UART_Transmit(&huart8, (uint8_t *)&ch, 1, 0xFFFF); // Use UART8 as debug interface ITM_SendChar(ch); // Use SWV as debug interface 800070a: 687b ldr r3, [r7, #4] 800070c: 4618 mov r0, r3 800070e: f7ff ffd1 bl 80006b4 #endif return ch; 8000712: 687b ldr r3, [r7, #4] } 8000714: 4618 mov r0, r3 8000716: 3708 adds r7, #8 8000718: 46bd mov sp, r7 800071a: bd80 pop {r7, pc} 0800071c : void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 800071c: b590 push {r4, r7, lr} 800071e: b085 sub sp, #20 8000720: af00 add r7, sp, #0 8000722: 4603 mov r3, r0 8000724: 80fb strh r3, [r7, #6] if((GPIO_Pin == GPIO_PIN_14) || (GPIO_Pin == GPIO_PIN_15)) 8000726: 88fb ldrh r3, [r7, #6] 8000728: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800072c: d003 beq.n 8000736 800072e: 88fb ldrh r3, [r7, #6] 8000730: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8000734: d11a bne.n 800076c { uint32_t pinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3; 8000736: f44f 4100 mov.w r1, #32768 @ 0x8000 800073a: 481f ldr r0, [pc, #124] @ (80007b8 ) 800073c: f00a fdc0 bl 800b2c0 8000740: 4603 mov r3, r0 8000742: 005c lsls r4, r3, #1 8000744: f44f 4180 mov.w r1, #16384 @ 0x4000 8000748: 481b ldr r0, [pc, #108] @ (80007b8 ) 800074a: f00a fdb9 bl 800b2c0 800074e: 4603 mov r3, r0 8000750: 4323 orrs r3, r4 8000752: f003 0303 and.w r3, r3, #3 8000756: 60fb str r3, [r7, #12] osMessageQueuePut(encoderXTaskArg.dataQueue, &pinStates, 0, 0); 8000758: 4b18 ldr r3, [pc, #96] @ (80007bc ) 800075a: 6918 ldr r0, [r3, #16] 800075c: f107 010c add.w r1, r7, #12 8000760: 2300 movs r3, #0 8000762: 2200 movs r2, #0 8000764: f013 fa5c bl 8013c20 { 8000768: bf00 nop else if ((GPIO_Pin == GPIO_PIN_10) || (GPIO_Pin == GPIO_PIN_11)) { uint32_t pinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3; osMessageQueuePut(encoderYTaskArg.dataQueue, &pinStates, 0, 0); } } 800076a: e020 b.n 80007ae else if ((GPIO_Pin == GPIO_PIN_10) || (GPIO_Pin == GPIO_PIN_11)) 800076c: 88fb ldrh r3, [r7, #6] 800076e: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8000772: d003 beq.n 800077c 8000774: 88fb ldrh r3, [r7, #6] 8000776: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800077a: d118 bne.n 80007ae uint32_t pinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3; 800077c: f44f 6100 mov.w r1, #2048 @ 0x800 8000780: 480f ldr r0, [pc, #60] @ (80007c0 ) 8000782: f00a fd9d bl 800b2c0 8000786: 4603 mov r3, r0 8000788: 005c lsls r4, r3, #1 800078a: f44f 6180 mov.w r1, #1024 @ 0x400 800078e: 480c ldr r0, [pc, #48] @ (80007c0 ) 8000790: f00a fd96 bl 800b2c0 8000794: 4603 mov r3, r0 8000796: 4323 orrs r3, r4 8000798: f003 0303 and.w r3, r3, #3 800079c: 60bb str r3, [r7, #8] osMessageQueuePut(encoderYTaskArg.dataQueue, &pinStates, 0, 0); 800079e: 4b09 ldr r3, [pc, #36] @ (80007c4 ) 80007a0: 6918 ldr r0, [r3, #16] 80007a2: f107 0108 add.w r1, r7, #8 80007a6: 2300 movs r3, #0 80007a8: 2200 movs r2, #0 80007aa: f013 fa39 bl 8013c20 } 80007ae: bf00 nop 80007b0: 3714 adds r7, #20 80007b2: 46bd mov sp, r7 80007b4: bd90 pop {r4, r7, pc} 80007b6: bf00 nop 80007b8: 58020c00 .word 0x58020c00 80007bc: 24000840 .word 0x24000840 80007c0: 58020400 .word 0x58020400 80007c4: 24000860 .word 0x24000860 080007c8
: /** * @brief The application entry point. * @retval int */ int main(void) { 80007c8: b580 push {r7, lr} 80007ca: b084 sub sp, #16 80007cc: af00 add r7, sp, #0 /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MPU Configuration--------------------------------------------------------*/ MPU_Config(); 80007ce: f001 f977 bl 8001ac0 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 80007d2: 4b5e ldr r3, [pc, #376] @ (800094c ) 80007d4: 695b ldr r3, [r3, #20] 80007d6: f403 3300 and.w r3, r3, #131072 @ 0x20000 80007da: 2b00 cmp r3, #0 80007dc: d11b bne.n 8000816 __ASM volatile ("dsb 0xF":::"memory"); 80007de: f3bf 8f4f dsb sy } 80007e2: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80007e4: f3bf 8f6f isb sy } 80007e8: bf00 nop SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 80007ea: 4b58 ldr r3, [pc, #352] @ (800094c ) 80007ec: 2200 movs r2, #0 80007ee: f8c3 2250 str.w r2, [r3, #592] @ 0x250 __ASM volatile ("dsb 0xF":::"memory"); 80007f2: f3bf 8f4f dsb sy } 80007f6: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80007f8: f3bf 8f6f isb sy } 80007fc: bf00 nop SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 80007fe: 4b53 ldr r3, [pc, #332] @ (800094c ) 8000800: 695b ldr r3, [r3, #20] 8000802: 4a52 ldr r2, [pc, #328] @ (800094c ) 8000804: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8000808: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 800080a: f3bf 8f4f dsb sy } 800080e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000810: f3bf 8f6f isb sy } 8000814: e000 b.n 8000818 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 8000816: bf00 nop if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 8000818: 4b4c ldr r3, [pc, #304] @ (800094c ) 800081a: 695b ldr r3, [r3, #20] 800081c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8000820: 2b00 cmp r3, #0 8000822: d138 bne.n 8000896 SCB->CSSELR = 0U; /* select Level 1 data cache */ 8000824: 4b49 ldr r3, [pc, #292] @ (800094c ) 8000826: 2200 movs r2, #0 8000828: f8c3 2084 str.w r2, [r3, #132] @ 0x84 __ASM volatile ("dsb 0xF":::"memory"); 800082c: f3bf 8f4f dsb sy } 8000830: bf00 nop ccsidr = SCB->CCSIDR; 8000832: 4b46 ldr r3, [pc, #280] @ (800094c ) 8000834: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8000838: 60fb str r3, [r7, #12] sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 800083a: 68fb ldr r3, [r7, #12] 800083c: 0b5b lsrs r3, r3, #13 800083e: f3c3 030e ubfx r3, r3, #0, #15 8000842: 60bb str r3, [r7, #8] ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 8000844: 68fb ldr r3, [r7, #12] 8000846: 08db lsrs r3, r3, #3 8000848: f3c3 0309 ubfx r3, r3, #0, #10 800084c: 607b str r3, [r7, #4] SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 800084e: 68bb ldr r3, [r7, #8] 8000850: 015a lsls r2, r3, #5 8000852: f643 73e0 movw r3, #16352 @ 0x3fe0 8000856: 4013 ands r3, r2 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 8000858: 687a ldr r2, [r7, #4] 800085a: 0792 lsls r2, r2, #30 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 800085c: 493b ldr r1, [pc, #236] @ (800094c ) 800085e: 4313 orrs r3, r2 8000860: f8c1 3260 str.w r3, [r1, #608] @ 0x260 } while (ways-- != 0U); 8000864: 687b ldr r3, [r7, #4] 8000866: 1e5a subs r2, r3, #1 8000868: 607a str r2, [r7, #4] 800086a: 2b00 cmp r3, #0 800086c: d1ef bne.n 800084e } while(sets-- != 0U); 800086e: 68bb ldr r3, [r7, #8] 8000870: 1e5a subs r2, r3, #1 8000872: 60ba str r2, [r7, #8] 8000874: 2b00 cmp r3, #0 8000876: d1e5 bne.n 8000844 __ASM volatile ("dsb 0xF":::"memory"); 8000878: f3bf 8f4f dsb sy } 800087c: bf00 nop SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 800087e: 4b33 ldr r3, [pc, #204] @ (800094c ) 8000880: 695b ldr r3, [r3, #20] 8000882: 4a32 ldr r2, [pc, #200] @ (800094c ) 8000884: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8000888: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 800088a: f3bf 8f4f dsb sy } 800088e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000890: f3bf 8f6f isb sy } 8000894: e000 b.n 8000898 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 8000896: bf00 nop SCB_EnableDCache(); /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000898: f005 f93a bl 8005b10 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800089c: f000 f876 bl 800098c /* Configure the peripherals common clocks */ PeriphCommonClock_Config(); 80008a0: f000 f8f2 bl 8000a88 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80008a4: f000 fe62 bl 800156c MX_DMA_Init(); 80008a8: f000 fe30 bl 800150c MX_RNG_Init(); 80008ac: f000 fbde bl 800106c MX_USART1_UART_Init(); 80008b0: f000 fddc bl 800146c MX_ADC1_Init(); 80008b4: f000 f918 bl 8000ae8 MX_UART8_Init(); 80008b8: f000 fd8c bl 80013d4 MX_CRC_Init(); 80008bc: f000 fb70 bl 8000fa0 MX_ADC2_Init(); 80008c0: f000 f9fc bl 8000cbc MX_ADC3_Init(); 80008c4: f000 fa8e bl 8000de4 MX_TIM1_Init(); 80008c8: f000 fbe6 bl 8001098 MX_TIM3_Init(); 80008cc: f000 fc80 bl 80011d0 MX_DAC1_Init(); 80008d0: f000 fb90 bl 8000ff4 MX_COMP1_Init(); 80008d4: f000 fb36 bl 8000f44 MX_TIM8_Init(); 80008d8: f000 fd26 bl 8001328 HAL_IWDG_Refresh(&hiwdg1); #endif /* USER CODE END 2 */ /* Init scheduler */ osKernelInitialize(); 80008dc: f012 fe30 bl 8013540 /* add semaphores, ... */ /* USER CODE END RTOS_SEMAPHORES */ /* Create the timer(s) */ /* creation of debugLedTimer */ debugLedTimerHandle = osTimerNew(debugLedTimerCallback, osTimerOnce, NULL, &debugLedTimer_attributes); 80008e0: 4b1b ldr r3, [pc, #108] @ (8000950 ) 80008e2: 2200 movs r2, #0 80008e4: 2100 movs r1, #0 80008e6: 481b ldr r0, [pc, #108] @ (8000954 ) 80008e8: f012 ff38 bl 801375c 80008ec: 4603 mov r3, r0 80008ee: 4a1a ldr r2, [pc, #104] @ (8000958 ) 80008f0: 6013 str r3, [r2, #0] /* creation of fanTimer */ fanTimerHandle = osTimerNew(fanTimerCallback, osTimerOnce, NULL, &fanTimer_attributes); 80008f2: 4b1a ldr r3, [pc, #104] @ (800095c ) 80008f4: 2200 movs r2, #0 80008f6: 2100 movs r1, #0 80008f8: 4819 ldr r0, [pc, #100] @ (8000960 ) 80008fa: f012 ff2f bl 801375c 80008fe: 4603 mov r3, r0 8000900: 4a18 ldr r2, [pc, #96] @ (8000964 ) 8000902: 6013 str r3, [r2, #0] /* creation of motorXTimer */ motorXTimerHandle = osTimerNew(motorXTimerCallback, osTimerPeriodic, NULL, &motorXTimer_attributes); 8000904: 4b18 ldr r3, [pc, #96] @ (8000968 ) 8000906: 2200 movs r2, #0 8000908: 2101 movs r1, #1 800090a: 4818 ldr r0, [pc, #96] @ (800096c ) 800090c: f012 ff26 bl 801375c 8000910: 4603 mov r3, r0 8000912: 4a17 ldr r2, [pc, #92] @ (8000970 ) 8000914: 6013 str r3, [r2, #0] /* creation of motorYTimer */ motorYTimerHandle = osTimerNew(motorYTimerCallback, osTimerPeriodic, NULL, &motorYTimer_attributes); 8000916: 4b17 ldr r3, [pc, #92] @ (8000974 ) 8000918: 2200 movs r2, #0 800091a: 2101 movs r1, #1 800091c: 4816 ldr r0, [pc, #88] @ (8000978 ) 800091e: f012 ff1d bl 801375c 8000922: 4603 mov r3, r0 8000924: 4a15 ldr r2, [pc, #84] @ (800097c ) 8000926: 6013 str r3, [r2, #0] /* add queues, ... */ /* USER CODE END RTOS_QUEUES */ /* Create the thread(s) */ /* creation of defaultTask */ defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); 8000928: 4a15 ldr r2, [pc, #84] @ (8000980 ) 800092a: 2100 movs r1, #0 800092c: 4815 ldr r0, [pc, #84] @ (8000984 ) 800092e: f012 fe51 bl 80135d4 8000932: 4603 mov r3, r0 8000934: 4a14 ldr r2, [pc, #80] @ (8000988 ) 8000936: 6013 str r3, [r2, #0] /* USER CODE BEGIN RTOS_THREADS */ /* add threads, ... */ #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); #endif UartTasksInit(); 8000938: f003 ffae bl 8004898 #ifdef USER_MOCKS MockMeasurmetsTaskInit(); #else MeasTasksInit(); 800093c: f001 f94c bl 8001bd8 #endif PositionControlTaskInit(); 8000940: f002 fc20 bl 8003184 /* USER CODE BEGIN RTOS_EVENTS */ /* add events, ... */ /* USER CODE END RTOS_EVENTS */ /* Start scheduler */ osKernelStart(); 8000944: f012 fe20 bl 8013588 /* We should never get here as control is now taken by the scheduler */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8000948: bf00 nop 800094a: e7fd b.n 8000948 800094c: e000ed00 .word 0xe000ed00 8000950: 08018b1c .word 0x08018b1c 8000954: 08001a15 .word 0x08001a15 8000958: 2400065c .word 0x2400065c 800095c: 08018b2c .word 0x08018b2c 8000960: 08001a2d .word 0x08001a2d 8000964: 2400068c .word 0x2400068c 8000968: 08018b3c .word 0x08018b3c 800096c: 08001a49 .word 0x08001a49 8000970: 240006bc .word 0x240006bc 8000974: 08018b4c .word 0x08018b4c 8000978: 08001a85 .word 0x08001a85 800097c: 240006ec .word 0x240006ec 8000980: 08018af8 .word 0x08018af8 8000984: 080018e5 .word 0x080018e5 8000988: 24000658 .word 0x24000658 0800098c : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800098c: b580 push {r7, lr} 800098e: b09c sub sp, #112 @ 0x70 8000990: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000992: f107 0324 add.w r3, r7, #36 @ 0x24 8000996: 224c movs r2, #76 @ 0x4c 8000998: 2100 movs r1, #0 800099a: 4618 mov r0, r3 800099c: f017 f976 bl 8017c8c RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 80009a0: 1d3b adds r3, r7, #4 80009a2: 2220 movs r2, #32 80009a4: 2100 movs r1, #0 80009a6: 4618 mov r0, r3 80009a8: f017 f970 bl 8017c8c /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 80009ac: 2002 movs r0, #2 80009ae: f00a fd77 bl 800b4a0 /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 80009b2: 2300 movs r3, #0 80009b4: 603b str r3, [r7, #0] 80009b6: 4b32 ldr r3, [pc, #200] @ (8000a80 ) 80009b8: 6adb ldr r3, [r3, #44] @ 0x2c 80009ba: 4a31 ldr r2, [pc, #196] @ (8000a80 ) 80009bc: f023 0301 bic.w r3, r3, #1 80009c0: 62d3 str r3, [r2, #44] @ 0x2c 80009c2: 4b2f ldr r3, [pc, #188] @ (8000a80 ) 80009c4: 6adb ldr r3, [r3, #44] @ 0x2c 80009c6: f003 0301 and.w r3, r3, #1 80009ca: 603b str r3, [r7, #0] 80009cc: 4b2d ldr r3, [pc, #180] @ (8000a84 ) 80009ce: 699b ldr r3, [r3, #24] 80009d0: 4a2c ldr r2, [pc, #176] @ (8000a84 ) 80009d2: f443 4340 orr.w r3, r3, #49152 @ 0xc000 80009d6: 6193 str r3, [r2, #24] 80009d8: 4b2a ldr r3, [pc, #168] @ (8000a84 ) 80009da: 699b ldr r3, [r3, #24] 80009dc: f403 4340 and.w r3, r3, #49152 @ 0xc000 80009e0: 603b str r3, [r7, #0] 80009e2: 683b ldr r3, [r7, #0] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 80009e4: bf00 nop 80009e6: 4b27 ldr r3, [pc, #156] @ (8000a84 ) 80009e8: 699b ldr r3, [r3, #24] 80009ea: f403 5300 and.w r3, r3, #8192 @ 0x2000 80009ee: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80009f2: d1f8 bne.n 80009e6 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_LSI 80009f4: 2329 movs r3, #41 @ 0x29 80009f6: 627b str r3, [r7, #36] @ 0x24 |RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; 80009f8: f44f 3380 mov.w r3, #65536 @ 0x10000 80009fc: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.LSIState = RCC_LSI_ON; 80009fe: 2301 movs r3, #1 8000a00: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; 8000a02: 2301 movs r3, #1 8000a04: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000a06: 2302 movs r3, #2 8000a08: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000a0a: 2302 movs r3, #2 8000a0c: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.PLL.PLLM = 5; 8000a0e: 2305 movs r3, #5 8000a10: 653b str r3, [r7, #80] @ 0x50 RCC_OscInitStruct.PLL.PLLN = 160; 8000a12: 23a0 movs r3, #160 @ 0xa0 8000a14: 657b str r3, [r7, #84] @ 0x54 RCC_OscInitStruct.PLL.PLLP = 2; 8000a16: 2302 movs r3, #2 8000a18: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLQ = 2; 8000a1a: 2302 movs r3, #2 8000a1c: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLR = 2; 8000a1e: 2302 movs r3, #2 8000a20: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 8000a22: 2308 movs r3, #8 8000a24: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 8000a26: 2300 movs r3, #0 8000a28: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL.PLLFRACN = 0; 8000a2a: 2300 movs r3, #0 8000a2c: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000a2e: f107 0324 add.w r3, r7, #36 @ 0x24 8000a32: 4618 mov r0, r3 8000a34: f00a fdf4 bl 800b620 8000a38: 4603 mov r3, r0 8000a3a: 2b00 cmp r3, #0 8000a3c: d001 beq.n 8000a42 { Error_Handler(); 8000a3e: f001 f8c5 bl 8001bcc } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000a42: 233f movs r3, #63 @ 0x3f 8000a44: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000a46: 2303 movs r3, #3 8000a48: 60bb str r3, [r7, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 8000a4a: 2300 movs r3, #0 8000a4c: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 8000a4e: 2308 movs r3, #8 8000a50: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 8000a52: 2340 movs r3, #64 @ 0x40 8000a54: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 8000a56: 2340 movs r3, #64 @ 0x40 8000a58: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 8000a5a: f44f 6380 mov.w r3, #1024 @ 0x400 8000a5e: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 8000a60: 2340 movs r3, #64 @ 0x40 8000a62: 623b str r3, [r7, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8000a64: 1d3b adds r3, r7, #4 8000a66: 2102 movs r1, #2 8000a68: 4618 mov r0, r3 8000a6a: f00b fa33 bl 800bed4 8000a6e: 4603 mov r3, r0 8000a70: 2b00 cmp r3, #0 8000a72: d001 beq.n 8000a78 { Error_Handler(); 8000a74: f001 f8aa bl 8001bcc } } 8000a78: bf00 nop 8000a7a: 3770 adds r7, #112 @ 0x70 8000a7c: 46bd mov sp, r7 8000a7e: bd80 pop {r7, pc} 8000a80: 58000400 .word 0x58000400 8000a84: 58024800 .word 0x58024800 08000a88 : /** * @brief Peripherals Common Clock Configuration * @retval None */ void PeriphCommonClock_Config(void) { 8000a88: b580 push {r7, lr} 8000a8a: b0b0 sub sp, #192 @ 0xc0 8000a8c: af00 add r7, sp, #0 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8000a8e: 463b mov r3, r7 8000a90: 22c0 movs r2, #192 @ 0xc0 8000a92: 2100 movs r1, #0 8000a94: 4618 mov r0, r3 8000a96: f017 f8f9 bl 8017c8c /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC; 8000a9a: f44f 2200 mov.w r2, #524288 @ 0x80000 8000a9e: f04f 0300 mov.w r3, #0 8000aa2: e9c7 2300 strd r2, r3, [r7] PeriphClkInitStruct.PLL2.PLL2M = 5; 8000aa6: 2305 movs r3, #5 8000aa8: 60bb str r3, [r7, #8] PeriphClkInitStruct.PLL2.PLL2N = 52; 8000aaa: 2334 movs r3, #52 @ 0x34 8000aac: 60fb str r3, [r7, #12] PeriphClkInitStruct.PLL2.PLL2P = 26; 8000aae: 231a movs r3, #26 8000ab0: 613b str r3, [r7, #16] PeriphClkInitStruct.PLL2.PLL2Q = 2; 8000ab2: 2302 movs r3, #2 8000ab4: 617b str r3, [r7, #20] PeriphClkInitStruct.PLL2.PLL2R = 2; 8000ab6: 2302 movs r3, #2 8000ab8: 61bb str r3, [r7, #24] PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2; 8000aba: 2380 movs r3, #128 @ 0x80 8000abc: 61fb str r3, [r7, #28] PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; 8000abe: 2300 movs r3, #0 8000ac0: 623b str r3, [r7, #32] PeriphClkInitStruct.PLL2.PLL2FRACN = 0; 8000ac2: 2300 movs r3, #0 8000ac4: 627b str r3, [r7, #36] @ 0x24 PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; 8000ac6: 2300 movs r3, #0 8000ac8: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8000acc: 463b mov r3, r7 8000ace: 4618 mov r0, r3 8000ad0: f00b fdce bl 800c670 8000ad4: 4603 mov r3, r0 8000ad6: 2b00 cmp r3, #0 8000ad8: d001 beq.n 8000ade { Error_Handler(); 8000ada: f001 f877 bl 8001bcc } } 8000ade: bf00 nop 8000ae0: 37c0 adds r7, #192 @ 0xc0 8000ae2: 46bd mov sp, r7 8000ae4: bd80 pop {r7, pc} ... 08000ae8 : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 8000ae8: b580 push {r7, lr} 8000aea: b08a sub sp, #40 @ 0x28 8000aec: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_MultiModeTypeDef multimode = {0}; 8000aee: f107 031c add.w r3, r7, #28 8000af2: 2200 movs r2, #0 8000af4: 601a str r2, [r3, #0] 8000af6: 605a str r2, [r3, #4] 8000af8: 609a str r2, [r3, #8] ADC_ChannelConfTypeDef sConfig = {0}; 8000afa: 463b mov r3, r7 8000afc: 2200 movs r2, #0 8000afe: 601a str r2, [r3, #0] 8000b00: 605a str r2, [r3, #4] 8000b02: 609a str r2, [r3, #8] 8000b04: 60da str r2, [r3, #12] 8000b06: 611a str r2, [r3, #16] 8000b08: 615a str r2, [r3, #20] 8000b0a: 619a str r2, [r3, #24] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 8000b0c: 4b62 ldr r3, [pc, #392] @ (8000c98 ) 8000b0e: 4a63 ldr r2, [pc, #396] @ (8000c9c ) 8000b10: 601a str r2, [r3, #0] hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 8000b12: 4b61 ldr r3, [pc, #388] @ (8000c98 ) 8000b14: 2200 movs r2, #0 8000b16: 605a str r2, [r3, #4] hadc1.Init.Resolution = ADC_RESOLUTION_16B; 8000b18: 4b5f ldr r3, [pc, #380] @ (8000c98 ) 8000b1a: 2200 movs r2, #0 8000b1c: 609a str r2, [r3, #8] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000b1e: 4b5e ldr r3, [pc, #376] @ (8000c98 ) 8000b20: 2201 movs r2, #1 8000b22: 60da str r2, [r3, #12] hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000b24: 4b5c ldr r3, [pc, #368] @ (8000c98 ) 8000b26: 2208 movs r2, #8 8000b28: 611a str r2, [r3, #16] hadc1.Init.LowPowerAutoWait = DISABLE; 8000b2a: 4b5b ldr r3, [pc, #364] @ (8000c98 ) 8000b2c: 2200 movs r2, #0 8000b2e: 751a strb r2, [r3, #20] hadc1.Init.ContinuousConvMode = ENABLE; 8000b30: 4b59 ldr r3, [pc, #356] @ (8000c98 ) 8000b32: 2201 movs r2, #1 8000b34: 755a strb r2, [r3, #21] hadc1.Init.NbrOfConversion = 7; 8000b36: 4b58 ldr r3, [pc, #352] @ (8000c98 ) 8000b38: 2207 movs r2, #7 8000b3a: 619a str r2, [r3, #24] hadc1.Init.DiscontinuousConvMode = DISABLE; 8000b3c: 4b56 ldr r3, [pc, #344] @ (8000c98 ) 8000b3e: 2200 movs r2, #0 8000b40: 771a strb r2, [r3, #28] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T8_TRGO; 8000b42: 4b55 ldr r3, [pc, #340] @ (8000c98 ) 8000b44: f44f 629c mov.w r2, #1248 @ 0x4e0 8000b48: 625a str r2, [r3, #36] @ 0x24 hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000b4a: 4b53 ldr r3, [pc, #332] @ (8000c98 ) 8000b4c: f44f 6280 mov.w r2, #1024 @ 0x400 8000b50: 629a str r2, [r3, #40] @ 0x28 hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000b52: 4b51 ldr r3, [pc, #324] @ (8000c98 ) 8000b54: 2201 movs r2, #1 8000b56: 62da str r2, [r3, #44] @ 0x2c hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000b58: 4b4f ldr r3, [pc, #316] @ (8000c98 ) 8000b5a: 2200 movs r2, #0 8000b5c: 631a str r2, [r3, #48] @ 0x30 hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000b5e: 4b4e ldr r3, [pc, #312] @ (8000c98 ) 8000b60: 2200 movs r2, #0 8000b62: 635a str r2, [r3, #52] @ 0x34 hadc1.Init.OversamplingMode = DISABLE; 8000b64: 4b4c ldr r3, [pc, #304] @ (8000c98 ) 8000b66: 2200 movs r2, #0 8000b68: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc1) != HAL_OK) 8000b6c: 484a ldr r0, [pc, #296] @ (8000c98 ) 8000b6e: f005 fa7f bl 8006070 8000b72: 4603 mov r3, r0 8000b74: 2b00 cmp r3, #0 8000b76: d001 beq.n 8000b7c { Error_Handler(); 8000b78: f001 f828 bl 8001bcc } /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; 8000b7c: 2300 movs r3, #0 8000b7e: 61fb str r3, [r7, #28] if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 8000b80: f107 031c add.w r3, r7, #28 8000b84: 4619 mov r1, r3 8000b86: 4844 ldr r0, [pc, #272] @ (8000c98 ) 8000b88: f006 fb90 bl 80072ac 8000b8c: 4603 mov r3, r0 8000b8e: 2b00 cmp r3, #0 8000b90: d001 beq.n 8000b96 { Error_Handler(); 8000b92: f001 f81b bl 8001bcc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8000b96: 4b42 ldr r3, [pc, #264] @ (8000ca0 ) 8000b98: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_1; 8000b9a: 2306 movs r3, #6 8000b9c: 607b str r3, [r7, #4] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000b9e: 2306 movs r3, #6 8000ba0: 60bb str r3, [r7, #8] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000ba2: f240 73ff movw r3, #2047 @ 0x7ff 8000ba6: 60fb str r3, [r7, #12] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000ba8: 2304 movs r3, #4 8000baa: 613b str r3, [r7, #16] sConfig.Offset = 0; 8000bac: 2300 movs r3, #0 8000bae: 617b str r3, [r7, #20] sConfig.OffsetSignedSaturation = DISABLE; 8000bb0: 2300 movs r3, #0 8000bb2: 767b strb r3, [r7, #25] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000bb4: 463b mov r3, r7 8000bb6: 4619 mov r1, r3 8000bb8: 4837 ldr r0, [pc, #220] @ (8000c98 ) 8000bba: f005 fcd3 bl 8006564 8000bbe: 4603 mov r3, r0 8000bc0: 2b00 cmp r3, #0 8000bc2: d001 beq.n 8000bc8 { Error_Handler(); 8000bc4: f001 f802 bl 8001bcc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_7; 8000bc8: 4b36 ldr r3, [pc, #216] @ (8000ca4 ) 8000bca: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_2; 8000bcc: 230c movs r3, #12 8000bce: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000bd0: 463b mov r3, r7 8000bd2: 4619 mov r1, r3 8000bd4: 4830 ldr r0, [pc, #192] @ (8000c98 ) 8000bd6: f005 fcc5 bl 8006564 8000bda: 4603 mov r3, r0 8000bdc: 2b00 cmp r3, #0 8000bde: d001 beq.n 8000be4 { Error_Handler(); 8000be0: f000 fff4 bl 8001bcc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_9; 8000be4: 4b30 ldr r3, [pc, #192] @ (8000ca8 ) 8000be6: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_3; 8000be8: 2312 movs r3, #18 8000bea: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000bec: 463b mov r3, r7 8000bee: 4619 mov r1, r3 8000bf0: 4829 ldr r0, [pc, #164] @ (8000c98 ) 8000bf2: f005 fcb7 bl 8006564 8000bf6: 4603 mov r3, r0 8000bf8: 2b00 cmp r3, #0 8000bfa: d001 beq.n 8000c00 { Error_Handler(); 8000bfc: f000 ffe6 bl 8001bcc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_16; 8000c00: 4b2a ldr r3, [pc, #168] @ (8000cac ) 8000c02: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_4; 8000c04: 2318 movs r3, #24 8000c06: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c08: 463b mov r3, r7 8000c0a: 4619 mov r1, r3 8000c0c: 4822 ldr r0, [pc, #136] @ (8000c98 ) 8000c0e: f005 fca9 bl 8006564 8000c12: 4603 mov r3, r0 8000c14: 2b00 cmp r3, #0 8000c16: d001 beq.n 8000c1c { Error_Handler(); 8000c18: f000 ffd8 bl 8001bcc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_17; 8000c1c: 4b24 ldr r3, [pc, #144] @ (8000cb0 ) 8000c1e: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_5; 8000c20: f44f 7380 mov.w r3, #256 @ 0x100 8000c24: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c26: 463b mov r3, r7 8000c28: 4619 mov r1, r3 8000c2a: 481b ldr r0, [pc, #108] @ (8000c98 ) 8000c2c: f005 fc9a bl 8006564 8000c30: 4603 mov r3, r0 8000c32: 2b00 cmp r3, #0 8000c34: d001 beq.n 8000c3a { Error_Handler(); 8000c36: f000 ffc9 bl 8001bcc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_14; 8000c3a: 4b1e ldr r3, [pc, #120] @ (8000cb4 ) 8000c3c: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_6; 8000c3e: f44f 7383 mov.w r3, #262 @ 0x106 8000c42: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c44: 463b mov r3, r7 8000c46: 4619 mov r1, r3 8000c48: 4813 ldr r0, [pc, #76] @ (8000c98 ) 8000c4a: f005 fc8b bl 8006564 8000c4e: 4603 mov r3, r0 8000c50: 2b00 cmp r3, #0 8000c52: d001 beq.n 8000c58 { Error_Handler(); 8000c54: f000 ffba bl 8001bcc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_15; 8000c58: 4b17 ldr r3, [pc, #92] @ (8000cb8 ) 8000c5a: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_7; 8000c5c: f44f 7386 mov.w r3, #268 @ 0x10c 8000c60: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c62: 463b mov r3, r7 8000c64: 4619 mov r1, r3 8000c66: 480c ldr r0, [pc, #48] @ (8000c98 ) 8000c68: f005 fc7c bl 8006564 8000c6c: 4603 mov r3, r0 8000c6e: 2b00 cmp r3, #0 8000c70: d001 beq.n 8000c76 { Error_Handler(); 8000c72: f000 ffab bl 8001bcc } /* USER CODE BEGIN ADC1_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000c76: f240 72ff movw r2, #2047 @ 0x7ff 8000c7a: f04f 1101 mov.w r1, #65537 @ 0x10001 8000c7e: 4806 ldr r0, [pc, #24] @ (8000c98 ) 8000c80: f006 fab0 bl 80071e4 8000c84: 4603 mov r3, r0 8000c86: 2b00 cmp r3, #0 8000c88: d001 beq.n 8000c8e { Error_Handler(); 8000c8a: f000 ff9f bl 8001bcc } /* USER CODE END ADC1_Init 2 */ } 8000c8e: bf00 nop 8000c90: 3728 adds r7, #40 @ 0x28 8000c92: 46bd mov sp, r7 8000c94: bd80 pop {r7, pc} 8000c96: bf00 nop 8000c98: 24000140 .word 0x24000140 8000c9c: 40022000 .word 0x40022000 8000ca0: 21800100 .word 0x21800100 8000ca4: 1d500080 .word 0x1d500080 8000ca8: 25b00200 .word 0x25b00200 8000cac: 43210000 .word 0x43210000 8000cb0: 47520000 .word 0x47520000 8000cb4: 3ac04000 .word 0x3ac04000 8000cb8: 3ef08000 .word 0x3ef08000 08000cbc : * @brief ADC2 Initialization Function * @param None * @retval None */ static void MX_ADC2_Init(void) { 8000cbc: b580 push {r7, lr} 8000cbe: b088 sub sp, #32 8000cc0: af00 add r7, sp, #0 /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000cc2: 1d3b adds r3, r7, #4 8000cc4: 2200 movs r2, #0 8000cc6: 601a str r2, [r3, #0] 8000cc8: 605a str r2, [r3, #4] 8000cca: 609a str r2, [r3, #8] 8000ccc: 60da str r2, [r3, #12] 8000cce: 611a str r2, [r3, #16] 8000cd0: 615a str r2, [r3, #20] 8000cd2: 619a str r2, [r3, #24] /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; 8000cd4: 4b3e ldr r3, [pc, #248] @ (8000dd0 ) 8000cd6: 4a3f ldr r2, [pc, #252] @ (8000dd4 ) 8000cd8: 601a str r2, [r3, #0] hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 8000cda: 4b3d ldr r3, [pc, #244] @ (8000dd0 ) 8000cdc: 2200 movs r2, #0 8000cde: 605a str r2, [r3, #4] hadc2.Init.Resolution = ADC_RESOLUTION_16B; 8000ce0: 4b3b ldr r3, [pc, #236] @ (8000dd0 ) 8000ce2: 2200 movs r2, #0 8000ce4: 609a str r2, [r3, #8] hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000ce6: 4b3a ldr r3, [pc, #232] @ (8000dd0 ) 8000ce8: 2201 movs r2, #1 8000cea: 60da str r2, [r3, #12] hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000cec: 4b38 ldr r3, [pc, #224] @ (8000dd0 ) 8000cee: 2208 movs r2, #8 8000cf0: 611a str r2, [r3, #16] hadc2.Init.LowPowerAutoWait = DISABLE; 8000cf2: 4b37 ldr r3, [pc, #220] @ (8000dd0 ) 8000cf4: 2200 movs r2, #0 8000cf6: 751a strb r2, [r3, #20] hadc2.Init.ContinuousConvMode = ENABLE; 8000cf8: 4b35 ldr r3, [pc, #212] @ (8000dd0 ) 8000cfa: 2201 movs r2, #1 8000cfc: 755a strb r2, [r3, #21] hadc2.Init.NbrOfConversion = 3; 8000cfe: 4b34 ldr r3, [pc, #208] @ (8000dd0 ) 8000d00: 2203 movs r2, #3 8000d02: 619a str r2, [r3, #24] hadc2.Init.DiscontinuousConvMode = DISABLE; 8000d04: 4b32 ldr r3, [pc, #200] @ (8000dd0 ) 8000d06: 2200 movs r2, #0 8000d08: 771a strb r2, [r3, #28] hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T8_TRGO; 8000d0a: 4b31 ldr r3, [pc, #196] @ (8000dd0 ) 8000d0c: f44f 629c mov.w r2, #1248 @ 0x4e0 8000d10: 625a str r2, [r3, #36] @ 0x24 hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000d12: 4b2f ldr r3, [pc, #188] @ (8000dd0 ) 8000d14: f44f 6280 mov.w r2, #1024 @ 0x400 8000d18: 629a str r2, [r3, #40] @ 0x28 hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000d1a: 4b2d ldr r3, [pc, #180] @ (8000dd0 ) 8000d1c: 2201 movs r2, #1 8000d1e: 62da str r2, [r3, #44] @ 0x2c hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000d20: 4b2b ldr r3, [pc, #172] @ (8000dd0 ) 8000d22: 2200 movs r2, #0 8000d24: 631a str r2, [r3, #48] @ 0x30 hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000d26: 4b2a ldr r3, [pc, #168] @ (8000dd0 ) 8000d28: 2200 movs r2, #0 8000d2a: 635a str r2, [r3, #52] @ 0x34 hadc2.Init.OversamplingMode = DISABLE; 8000d2c: 4b28 ldr r3, [pc, #160] @ (8000dd0 ) 8000d2e: 2200 movs r2, #0 8000d30: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc2) != HAL_OK) 8000d34: 4826 ldr r0, [pc, #152] @ (8000dd0 ) 8000d36: f005 f99b bl 8006070 8000d3a: 4603 mov r3, r0 8000d3c: 2b00 cmp r3, #0 8000d3e: d001 beq.n 8000d44 { Error_Handler(); 8000d40: f000 ff44 bl 8001bcc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 8000d44: 4b24 ldr r3, [pc, #144] @ (8000dd8 ) 8000d46: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8000d48: 2306 movs r3, #6 8000d4a: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000d4c: 2306 movs r3, #6 8000d4e: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000d50: f240 73ff movw r3, #2047 @ 0x7ff 8000d54: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000d56: 2304 movs r3, #4 8000d58: 617b str r3, [r7, #20] sConfig.Offset = 0; 8000d5a: 2300 movs r3, #0 8000d5c: 61bb str r3, [r7, #24] sConfig.OffsetSignedSaturation = DISABLE; 8000d5e: 2300 movs r3, #0 8000d60: 777b strb r3, [r7, #29] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000d62: 1d3b adds r3, r7, #4 8000d64: 4619 mov r1, r3 8000d66: 481a ldr r0, [pc, #104] @ (8000dd0 ) 8000d68: f005 fbfc bl 8006564 8000d6c: 4603 mov r3, r0 8000d6e: 2b00 cmp r3, #0 8000d70: d001 beq.n 8000d76 { Error_Handler(); 8000d72: f000 ff2b bl 8001bcc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8000d76: 4b19 ldr r3, [pc, #100] @ (8000ddc ) 8000d78: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 8000d7a: 230c movs r3, #12 8000d7c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000d7e: 1d3b adds r3, r7, #4 8000d80: 4619 mov r1, r3 8000d82: 4813 ldr r0, [pc, #76] @ (8000dd0 ) 8000d84: f005 fbee bl 8006564 8000d88: 4603 mov r3, r0 8000d8a: 2b00 cmp r3, #0 8000d8c: d001 beq.n 8000d92 { Error_Handler(); 8000d8e: f000 ff1d bl 8001bcc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_5; 8000d92: 4b13 ldr r3, [pc, #76] @ (8000de0 ) 8000d94: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8000d96: 2312 movs r3, #18 8000d98: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000d9a: 1d3b adds r3, r7, #4 8000d9c: 4619 mov r1, r3 8000d9e: 480c ldr r0, [pc, #48] @ (8000dd0 ) 8000da0: f005 fbe0 bl 8006564 8000da4: 4603 mov r3, r0 8000da6: 2b00 cmp r3, #0 8000da8: d001 beq.n 8000dae { Error_Handler(); 8000daa: f000 ff0f bl 8001bcc } /* USER CODE BEGIN ADC2_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc2, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000dae: f240 72ff movw r2, #2047 @ 0x7ff 8000db2: f04f 1101 mov.w r1, #65537 @ 0x10001 8000db6: 4806 ldr r0, [pc, #24] @ (8000dd0 ) 8000db8: f006 fa14 bl 80071e4 8000dbc: 4603 mov r3, r0 8000dbe: 2b00 cmp r3, #0 8000dc0: d001 beq.n 8000dc6 { Error_Handler(); 8000dc2: f000 ff03 bl 8001bcc } /* USER CODE END ADC2_Init 2 */ } 8000dc6: bf00 nop 8000dc8: 3720 adds r7, #32 8000dca: 46bd mov sp, r7 8000dcc: bd80 pop {r7, pc} 8000dce: bf00 nop 8000dd0: 240001a4 .word 0x240001a4 8000dd4: 40022100 .word 0x40022100 8000dd8: 0c900008 .word 0x0c900008 8000ddc: 10c00010 .word 0x10c00010 8000de0: 14f00020 .word 0x14f00020 08000de4 : * @brief ADC3 Initialization Function * @param None * @retval None */ static void MX_ADC3_Init(void) { 8000de4: b580 push {r7, lr} 8000de6: b088 sub sp, #32 8000de8: af00 add r7, sp, #0 /* USER CODE BEGIN ADC3_Init 0 */ /* USER CODE END ADC3_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000dea: 1d3b adds r3, r7, #4 8000dec: 2200 movs r2, #0 8000dee: 601a str r2, [r3, #0] 8000df0: 605a str r2, [r3, #4] 8000df2: 609a str r2, [r3, #8] 8000df4: 60da str r2, [r3, #12] 8000df6: 611a str r2, [r3, #16] 8000df8: 615a str r2, [r3, #20] 8000dfa: 619a str r2, [r3, #24] /* USER CODE END ADC3_Init 1 */ /** Common config */ hadc3.Instance = ADC3; 8000dfc: 4b4b ldr r3, [pc, #300] @ (8000f2c ) 8000dfe: 4a4c ldr r2, [pc, #304] @ (8000f30 ) 8000e00: 601a str r2, [r3, #0] hadc3.Init.Resolution = ADC_RESOLUTION_16B; 8000e02: 4b4a ldr r3, [pc, #296] @ (8000f2c ) 8000e04: 2200 movs r2, #0 8000e06: 609a str r2, [r3, #8] hadc3.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000e08: 4b48 ldr r3, [pc, #288] @ (8000f2c ) 8000e0a: 2201 movs r2, #1 8000e0c: 60da str r2, [r3, #12] hadc3.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000e0e: 4b47 ldr r3, [pc, #284] @ (8000f2c ) 8000e10: 2208 movs r2, #8 8000e12: 611a str r2, [r3, #16] hadc3.Init.LowPowerAutoWait = DISABLE; 8000e14: 4b45 ldr r3, [pc, #276] @ (8000f2c ) 8000e16: 2200 movs r2, #0 8000e18: 751a strb r2, [r3, #20] hadc3.Init.ContinuousConvMode = ENABLE; 8000e1a: 4b44 ldr r3, [pc, #272] @ (8000f2c ) 8000e1c: 2201 movs r2, #1 8000e1e: 755a strb r2, [r3, #21] hadc3.Init.NbrOfConversion = 5; 8000e20: 4b42 ldr r3, [pc, #264] @ (8000f2c ) 8000e22: 2205 movs r2, #5 8000e24: 619a str r2, [r3, #24] hadc3.Init.DiscontinuousConvMode = DISABLE; 8000e26: 4b41 ldr r3, [pc, #260] @ (8000f2c ) 8000e28: 2200 movs r2, #0 8000e2a: 771a strb r2, [r3, #28] hadc3.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T8_TRGO; 8000e2c: 4b3f ldr r3, [pc, #252] @ (8000f2c ) 8000e2e: f44f 629c mov.w r2, #1248 @ 0x4e0 8000e32: 625a str r2, [r3, #36] @ 0x24 hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000e34: 4b3d ldr r3, [pc, #244] @ (8000f2c ) 8000e36: f44f 6280 mov.w r2, #1024 @ 0x400 8000e3a: 629a str r2, [r3, #40] @ 0x28 hadc3.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000e3c: 4b3b ldr r3, [pc, #236] @ (8000f2c ) 8000e3e: 2201 movs r2, #1 8000e40: 62da str r2, [r3, #44] @ 0x2c hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000e42: 4b3a ldr r3, [pc, #232] @ (8000f2c ) 8000e44: 2200 movs r2, #0 8000e46: 631a str r2, [r3, #48] @ 0x30 hadc3.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000e48: 4b38 ldr r3, [pc, #224] @ (8000f2c ) 8000e4a: 2200 movs r2, #0 8000e4c: 635a str r2, [r3, #52] @ 0x34 hadc3.Init.OversamplingMode = DISABLE; 8000e4e: 4b37 ldr r3, [pc, #220] @ (8000f2c ) 8000e50: 2200 movs r2, #0 8000e52: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc3) != HAL_OK) 8000e56: 4835 ldr r0, [pc, #212] @ (8000f2c ) 8000e58: f005 f90a bl 8006070 8000e5c: 4603 mov r3, r0 8000e5e: 2b00 cmp r3, #0 8000e60: d001 beq.n 8000e66 { Error_Handler(); 8000e62: f000 feb3 bl 8001bcc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_0; 8000e66: 2301 movs r3, #1 8000e68: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8000e6a: 2306 movs r3, #6 8000e6c: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000e6e: 2306 movs r3, #6 8000e70: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000e72: f240 73ff movw r3, #2047 @ 0x7ff 8000e76: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000e78: 2304 movs r3, #4 8000e7a: 617b str r3, [r7, #20] sConfig.Offset = 0; 8000e7c: 2300 movs r3, #0 8000e7e: 61bb str r3, [r7, #24] sConfig.OffsetSignedSaturation = DISABLE; 8000e80: 2300 movs r3, #0 8000e82: 777b strb r3, [r7, #29] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000e84: 1d3b adds r3, r7, #4 8000e86: 4619 mov r1, r3 8000e88: 4828 ldr r0, [pc, #160] @ (8000f2c ) 8000e8a: f005 fb6b bl 8006564 8000e8e: 4603 mov r3, r0 8000e90: 2b00 cmp r3, #0 8000e92: d001 beq.n 8000e98 { Error_Handler(); 8000e94: f000 fe9a bl 8001bcc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 8000e98: 4b26 ldr r3, [pc, #152] @ (8000f34 ) 8000e9a: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 8000e9c: 230c movs r3, #12 8000e9e: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000ea0: 1d3b adds r3, r7, #4 8000ea2: 4619 mov r1, r3 8000ea4: 4821 ldr r0, [pc, #132] @ (8000f2c ) 8000ea6: f005 fb5d bl 8006564 8000eaa: 4603 mov r3, r0 8000eac: 2b00 cmp r3, #0 8000eae: d001 beq.n 8000eb4 { Error_Handler(); 8000eb0: f000 fe8c bl 8001bcc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_10; 8000eb4: 4b20 ldr r3, [pc, #128] @ (8000f38 ) 8000eb6: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8000eb8: 2312 movs r3, #18 8000eba: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000ebc: 1d3b adds r3, r7, #4 8000ebe: 4619 mov r1, r3 8000ec0: 481a ldr r0, [pc, #104] @ (8000f2c ) 8000ec2: f005 fb4f bl 8006564 8000ec6: 4603 mov r3, r0 8000ec8: 2b00 cmp r3, #0 8000eca: d001 beq.n 8000ed0 { Error_Handler(); 8000ecc: f000 fe7e bl 8001bcc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_11; 8000ed0: 4b1a ldr r3, [pc, #104] @ (8000f3c ) 8000ed2: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_4; 8000ed4: 2318 movs r3, #24 8000ed6: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000ed8: 1d3b adds r3, r7, #4 8000eda: 4619 mov r1, r3 8000edc: 4813 ldr r0, [pc, #76] @ (8000f2c ) 8000ede: f005 fb41 bl 8006564 8000ee2: 4603 mov r3, r0 8000ee4: 2b00 cmp r3, #0 8000ee6: d001 beq.n 8000eec { Error_Handler(); 8000ee8: f000 fe70 bl 8001bcc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; 8000eec: 4b14 ldr r3, [pc, #80] @ (8000f40 ) 8000eee: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_5; 8000ef0: f44f 7380 mov.w r3, #256 @ 0x100 8000ef4: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000ef6: 1d3b adds r3, r7, #4 8000ef8: 4619 mov r1, r3 8000efa: 480c ldr r0, [pc, #48] @ (8000f2c ) 8000efc: f005 fb32 bl 8006564 8000f00: 4603 mov r3, r0 8000f02: 2b00 cmp r3, #0 8000f04: d001 beq.n 8000f0a { Error_Handler(); 8000f06: f000 fe61 bl 8001bcc } /* USER CODE BEGIN ADC3_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc3, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000f0a: f240 72ff movw r2, #2047 @ 0x7ff 8000f0e: f04f 1101 mov.w r1, #65537 @ 0x10001 8000f12: 4806 ldr r0, [pc, #24] @ (8000f2c ) 8000f14: f006 f966 bl 80071e4 8000f18: 4603 mov r3, r0 8000f1a: 2b00 cmp r3, #0 8000f1c: d001 beq.n 8000f22 { Error_Handler(); 8000f1e: f000 fe55 bl 8001bcc } /* USER CODE END ADC3_Init 2 */ } 8000f22: bf00 nop 8000f24: 3720 adds r7, #32 8000f26: 46bd mov sp, r7 8000f28: bd80 pop {r7, pc} 8000f2a: bf00 nop 8000f2c: 24000208 .word 0x24000208 8000f30: 58026000 .word 0x58026000 8000f34: 04300002 .word 0x04300002 8000f38: 2a000400 .word 0x2a000400 8000f3c: 2e300800 .word 0x2e300800 8000f40: cfb80000 .word 0xcfb80000 08000f44 : * @brief COMP1 Initialization Function * @param None * @retval None */ static void MX_COMP1_Init(void) { 8000f44: b580 push {r7, lr} 8000f46: af00 add r7, sp, #0 /* USER CODE END COMP1_Init 0 */ /* USER CODE BEGIN COMP1_Init 1 */ /* USER CODE END COMP1_Init 1 */ hcomp1.Instance = COMP1; 8000f48: 4b12 ldr r3, [pc, #72] @ (8000f94 ) 8000f4a: 4a13 ldr r2, [pc, #76] @ (8000f98 ) 8000f4c: 601a str r2, [r3, #0] hcomp1.Init.InvertingInput = COMP_INPUT_MINUS_3_4VREFINT; 8000f4e: 4b11 ldr r3, [pc, #68] @ (8000f94 ) 8000f50: 4a12 ldr r2, [pc, #72] @ (8000f9c ) 8000f52: 611a str r2, [r3, #16] hcomp1.Init.NonInvertingInput = COMP_INPUT_PLUS_IO2; 8000f54: 4b0f ldr r3, [pc, #60] @ (8000f94 ) 8000f56: f44f 1280 mov.w r2, #1048576 @ 0x100000 8000f5a: 60da str r2, [r3, #12] hcomp1.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED; 8000f5c: 4b0d ldr r3, [pc, #52] @ (8000f94 ) 8000f5e: 2200 movs r2, #0 8000f60: 619a str r2, [r3, #24] hcomp1.Init.Hysteresis = COMP_HYSTERESIS_NONE; 8000f62: 4b0c ldr r3, [pc, #48] @ (8000f94 ) 8000f64: 2200 movs r2, #0 8000f66: 615a str r2, [r3, #20] hcomp1.Init.BlankingSrce = COMP_BLANKINGSRC_NONE; 8000f68: 4b0a ldr r3, [pc, #40] @ (8000f94 ) 8000f6a: 2200 movs r2, #0 8000f6c: 61da str r2, [r3, #28] hcomp1.Init.Mode = COMP_POWERMODE_HIGHSPEED; 8000f6e: 4b09 ldr r3, [pc, #36] @ (8000f94 ) 8000f70: 2200 movs r2, #0 8000f72: 609a str r2, [r3, #8] hcomp1.Init.WindowMode = COMP_WINDOWMODE_DISABLE; 8000f74: 4b07 ldr r3, [pc, #28] @ (8000f94 ) 8000f76: 2200 movs r2, #0 8000f78: 605a str r2, [r3, #4] hcomp1.Init.TriggerMode = COMP_TRIGGERMODE_NONE; 8000f7a: 4b06 ldr r3, [pc, #24] @ (8000f94 ) 8000f7c: 2200 movs r2, #0 8000f7e: 621a str r2, [r3, #32] if (HAL_COMP_Init(&hcomp1) != HAL_OK) 8000f80: 4804 ldr r0, [pc, #16] @ (8000f94 ) 8000f82: f006 fa71 bl 8007468 8000f86: 4603 mov r3, r0 8000f88: 2b00 cmp r3, #0 8000f8a: d001 beq.n 8000f90 { Error_Handler(); 8000f8c: f000 fe1e bl 8001bcc } /* USER CODE BEGIN COMP1_Init 2 */ /* USER CODE END COMP1_Init 2 */ } 8000f90: bf00 nop 8000f92: bd80 pop {r7, pc} 8000f94: 240003d4 .word 0x240003d4 8000f98: 5800380c .word 0x5800380c 8000f9c: 00020006 .word 0x00020006 08000fa0 : * @brief CRC Initialization Function * @param None * @retval None */ static void MX_CRC_Init(void) { 8000fa0: b580 push {r7, lr} 8000fa2: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 8000fa4: 4b11 ldr r3, [pc, #68] @ (8000fec ) 8000fa6: 4a12 ldr r2, [pc, #72] @ (8000ff0 ) 8000fa8: 601a str r2, [r3, #0] hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_DISABLE; 8000faa: 4b10 ldr r3, [pc, #64] @ (8000fec ) 8000fac: 2201 movs r2, #1 8000fae: 711a strb r2, [r3, #4] hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE; 8000fb0: 4b0e ldr r3, [pc, #56] @ (8000fec ) 8000fb2: 2200 movs r2, #0 8000fb4: 715a strb r2, [r3, #5] hcrc.Init.GeneratingPolynomial = 4129; 8000fb6: 4b0d ldr r3, [pc, #52] @ (8000fec ) 8000fb8: f241 0221 movw r2, #4129 @ 0x1021 8000fbc: 609a str r2, [r3, #8] hcrc.Init.CRCLength = CRC_POLYLENGTH_16B; 8000fbe: 4b0b ldr r3, [pc, #44] @ (8000fec ) 8000fc0: 2208 movs r2, #8 8000fc2: 60da str r2, [r3, #12] hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE; 8000fc4: 4b09 ldr r3, [pc, #36] @ (8000fec ) 8000fc6: 2200 movs r2, #0 8000fc8: 615a str r2, [r3, #20] hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE; 8000fca: 4b08 ldr r3, [pc, #32] @ (8000fec ) 8000fcc: 2200 movs r2, #0 8000fce: 619a str r2, [r3, #24] hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; 8000fd0: 4b06 ldr r3, [pc, #24] @ (8000fec ) 8000fd2: 2201 movs r2, #1 8000fd4: 621a str r2, [r3, #32] if (HAL_CRC_Init(&hcrc) != HAL_OK) 8000fd6: 4805 ldr r0, [pc, #20] @ (8000fec ) 8000fd8: f006 fd30 bl 8007a3c 8000fdc: 4603 mov r3, r0 8000fde: 2b00 cmp r3, #0 8000fe0: d001 beq.n 8000fe6 { Error_Handler(); 8000fe2: f000 fdf3 bl 8001bcc } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 8000fe6: bf00 nop 8000fe8: bd80 pop {r7, pc} 8000fea: bf00 nop 8000fec: 24000400 .word 0x24000400 8000ff0: 58024c00 .word 0x58024c00 08000ff4 : * @brief DAC1 Initialization Function * @param None * @retval None */ static void MX_DAC1_Init(void) { 8000ff4: b580 push {r7, lr} 8000ff6: b08a sub sp, #40 @ 0x28 8000ff8: af00 add r7, sp, #0 /* USER CODE BEGIN DAC1_Init 0 */ /* USER CODE END DAC1_Init 0 */ DAC_ChannelConfTypeDef sConfig = {0}; 8000ffa: 1d3b adds r3, r7, #4 8000ffc: 2224 movs r2, #36 @ 0x24 8000ffe: 2100 movs r1, #0 8001000: 4618 mov r0, r3 8001002: f016 fe43 bl 8017c8c /* USER CODE END DAC1_Init 1 */ /** DAC Initialization */ hdac1.Instance = DAC1; 8001006: 4b17 ldr r3, [pc, #92] @ (8001064 ) 8001008: 4a17 ldr r2, [pc, #92] @ (8001068 ) 800100a: 601a str r2, [r3, #0] if (HAL_DAC_Init(&hdac1) != HAL_OK) 800100c: 4815 ldr r0, [pc, #84] @ (8001064 ) 800100e: f006 ff1b bl 8007e48 8001012: 4603 mov r3, r0 8001014: 2b00 cmp r3, #0 8001016: d001 beq.n 800101c { Error_Handler(); 8001018: f000 fdd8 bl 8001bcc } /** DAC channel OUT1 config */ sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; 800101c: 2300 movs r3, #0 800101e: 607b str r3, [r7, #4] sConfig.DAC_Trigger = DAC_TRIGGER_NONE; 8001020: 2300 movs r3, #0 8001022: 60bb str r3, [r7, #8] sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; 8001024: 2300 movs r3, #0 8001026: 60fb str r3, [r7, #12] sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE; 8001028: 2301 movs r3, #1 800102a: 613b str r3, [r7, #16] sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; 800102c: 2300 movs r3, #0 800102e: 617b str r3, [r7, #20] if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) 8001030: 1d3b adds r3, r7, #4 8001032: 2200 movs r2, #0 8001034: 4619 mov r1, r3 8001036: 480b ldr r0, [pc, #44] @ (8001064 ) 8001038: f007 f80a bl 8008050 800103c: 4603 mov r3, r0 800103e: 2b00 cmp r3, #0 8001040: d001 beq.n 8001046 { Error_Handler(); 8001042: f000 fdc3 bl 8001bcc } /** DAC channel OUT2 config */ if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK) 8001046: 1d3b adds r3, r7, #4 8001048: 2210 movs r2, #16 800104a: 4619 mov r1, r3 800104c: 4805 ldr r0, [pc, #20] @ (8001064 ) 800104e: f006 ffff bl 8008050 8001052: 4603 mov r3, r0 8001054: 2b00 cmp r3, #0 8001056: d001 beq.n 800105c { Error_Handler(); 8001058: f000 fdb8 bl 8001bcc } /* USER CODE BEGIN DAC1_Init 2 */ /* USER CODE END DAC1_Init 2 */ } 800105c: bf00 nop 800105e: 3728 adds r7, #40 @ 0x28 8001060: 46bd mov sp, r7 8001062: bd80 pop {r7, pc} 8001064: 24000424 .word 0x24000424 8001068: 40007400 .word 0x40007400 0800106c : * @brief RNG Initialization Function * @param None * @retval None */ static void MX_RNG_Init(void) { 800106c: b580 push {r7, lr} 800106e: af00 add r7, sp, #0 /* USER CODE END RNG_Init 0 */ /* USER CODE BEGIN RNG_Init 1 */ /* USER CODE END RNG_Init 1 */ hrng.Instance = RNG; 8001070: 4b07 ldr r3, [pc, #28] @ (8001090 ) 8001072: 4a08 ldr r2, [pc, #32] @ (8001094 ) 8001074: 601a str r2, [r3, #0] hrng.Init.ClockErrorDetection = RNG_CED_ENABLE; 8001076: 4b06 ldr r3, [pc, #24] @ (8001090 ) 8001078: 2200 movs r2, #0 800107a: 605a str r2, [r3, #4] if (HAL_RNG_Init(&hrng) != HAL_OK) 800107c: 4804 ldr r0, [pc, #16] @ (8001090 ) 800107e: f00d ffd9 bl 800f034 8001082: 4603 mov r3, r0 8001084: 2b00 cmp r3, #0 8001086: d001 beq.n 800108c { Error_Handler(); 8001088: f000 fda0 bl 8001bcc } /* USER CODE BEGIN RNG_Init 2 */ /* USER CODE END RNG_Init 2 */ } 800108c: bf00 nop 800108e: bd80 pop {r7, pc} 8001090: 24000438 .word 0x24000438 8001094: 48021800 .word 0x48021800 08001098 : * @brief TIM1 Initialization Function * @param None * @retval None */ static void MX_TIM1_Init(void) { 8001098: b5b0 push {r4, r5, r7, lr} 800109a: b096 sub sp, #88 @ 0x58 800109c: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 800109e: f107 034c add.w r3, r7, #76 @ 0x4c 80010a2: 2200 movs r2, #0 80010a4: 601a str r2, [r3, #0] 80010a6: 605a str r2, [r3, #4] 80010a8: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 80010aa: f107 0330 add.w r3, r7, #48 @ 0x30 80010ae: 2200 movs r2, #0 80010b0: 601a str r2, [r3, #0] 80010b2: 605a str r2, [r3, #4] 80010b4: 609a str r2, [r3, #8] 80010b6: 60da str r2, [r3, #12] 80010b8: 611a str r2, [r3, #16] 80010ba: 615a str r2, [r3, #20] 80010bc: 619a str r2, [r3, #24] TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 80010be: 1d3b adds r3, r7, #4 80010c0: 222c movs r2, #44 @ 0x2c 80010c2: 2100 movs r1, #0 80010c4: 4618 mov r0, r3 80010c6: f016 fde1 bl 8017c8c /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; 80010ca: 4b3e ldr r3, [pc, #248] @ (80011c4 ) 80010cc: 4a3e ldr r2, [pc, #248] @ (80011c8 ) 80010ce: 601a str r2, [r3, #0] htim1.Init.Prescaler = 199; 80010d0: 4b3c ldr r3, [pc, #240] @ (80011c4 ) 80010d2: 22c7 movs r2, #199 @ 0xc7 80010d4: 605a str r2, [r3, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 80010d6: 4b3b ldr r3, [pc, #236] @ (80011c4 ) 80010d8: 2200 movs r2, #0 80010da: 609a str r2, [r3, #8] htim1.Init.Period = 999; 80010dc: 4b39 ldr r3, [pc, #228] @ (80011c4 ) 80010de: f240 32e7 movw r2, #999 @ 0x3e7 80010e2: 60da str r2, [r3, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80010e4: 4b37 ldr r3, [pc, #220] @ (80011c4 ) 80010e6: 2200 movs r2, #0 80010e8: 611a str r2, [r3, #16] htim1.Init.RepetitionCounter = 0; 80010ea: 4b36 ldr r3, [pc, #216] @ (80011c4 ) 80010ec: 2200 movs r2, #0 80010ee: 615a str r2, [r3, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 80010f0: 4b34 ldr r3, [pc, #208] @ (80011c4 ) 80010f2: 2280 movs r2, #128 @ 0x80 80010f4: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 80010f6: 4833 ldr r0, [pc, #204] @ (80011c4 ) 80010f8: f00e f93e bl 800f378 80010fc: 4603 mov r3, r0 80010fe: 2b00 cmp r3, #0 8001100: d001 beq.n 8001106 { Error_Handler(); 8001102: f000 fd63 bl 8001bcc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001106: 2300 movs r3, #0 8001108: 64fb str r3, [r7, #76] @ 0x4c sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 800110a: 2300 movs r3, #0 800110c: 653b str r3, [r7, #80] @ 0x50 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800110e: 2300 movs r3, #0 8001110: 657b str r3, [r7, #84] @ 0x54 if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 8001112: f107 034c add.w r3, r7, #76 @ 0x4c 8001116: 4619 mov r1, r3 8001118: 482a ldr r0, [pc, #168] @ (80011c4 ) 800111a: f00f fadf bl 80106dc 800111e: 4603 mov r3, r0 8001120: 2b00 cmp r3, #0 8001122: d001 beq.n 8001128 { Error_Handler(); 8001124: f000 fd52 bl 8001bcc } sConfigOC.OCMode = TIM_OCMODE_PWM1; 8001128: 2360 movs r3, #96 @ 0x60 800112a: 633b str r3, [r7, #48] @ 0x30 sConfigOC.Pulse = 99; 800112c: 2363 movs r3, #99 @ 0x63 800112e: 637b str r3, [r7, #52] @ 0x34 sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8001130: 2300 movs r3, #0 8001132: 63bb str r3, [r7, #56] @ 0x38 sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 8001134: 2300 movs r3, #0 8001136: 63fb str r3, [r7, #60] @ 0x3c sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001138: 2300 movs r3, #0 800113a: 643b str r3, [r7, #64] @ 0x40 sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 800113c: 2300 movs r3, #0 800113e: 647b str r3, [r7, #68] @ 0x44 sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 8001140: 2300 movs r3, #0 8001142: 64bb str r3, [r7, #72] @ 0x48 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8001144: f107 0330 add.w r3, r7, #48 @ 0x30 8001148: 2204 movs r2, #4 800114a: 4619 mov r1, r3 800114c: 481d ldr r0, [pc, #116] @ (80011c4 ) 800114e: f00e fc17 bl 800f980 8001152: 4603 mov r3, r0 8001154: 2b00 cmp r3, #0 8001156: d001 beq.n 800115c { Error_Handler(); 8001158: f000 fd38 bl 8001bcc } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 800115c: 2300 movs r3, #0 800115e: 607b str r3, [r7, #4] sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 8001160: 2300 movs r3, #0 8001162: 60bb str r3, [r7, #8] sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 8001164: 2300 movs r3, #0 8001166: 60fb str r3, [r7, #12] sBreakDeadTimeConfig.DeadTime = 0; 8001168: 2300 movs r3, #0 800116a: 613b str r3, [r7, #16] sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 800116c: 2300 movs r3, #0 800116e: 617b str r3, [r7, #20] sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 8001170: f44f 5300 mov.w r3, #8192 @ 0x2000 8001174: 61bb str r3, [r7, #24] sBreakDeadTimeConfig.BreakFilter = 0; 8001176: 2300 movs r3, #0 8001178: 61fb str r3, [r7, #28] sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 800117a: 2300 movs r3, #0 800117c: 623b str r3, [r7, #32] sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 800117e: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8001182: 627b str r3, [r7, #36] @ 0x24 sBreakDeadTimeConfig.Break2Filter = 0; 8001184: 2300 movs r3, #0 8001186: 62bb str r3, [r7, #40] @ 0x28 sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 8001188: 2300 movs r3, #0 800118a: 62fb str r3, [r7, #44] @ 0x2c if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 800118c: 1d3b adds r3, r7, #4 800118e: 4619 mov r1, r3 8001190: 480c ldr r0, [pc, #48] @ (80011c4 ) 8001192: f00f fb31 bl 80107f8 8001196: 4603 mov r3, r0 8001198: 2b00 cmp r3, #0 800119a: d001 beq.n 80011a0 { Error_Handler(); 800119c: f000 fd16 bl 8001bcc } /* USER CODE BEGIN TIM1_Init 2 */ memcpy(&fanTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 80011a0: 4b0a ldr r3, [pc, #40] @ (80011cc ) 80011a2: 461d mov r5, r3 80011a4: f107 0430 add.w r4, r7, #48 @ 0x30 80011a8: cc0f ldmia r4!, {r0, r1, r2, r3} 80011aa: c50f stmia r5!, {r0, r1, r2, r3} 80011ac: e894 0007 ldmia.w r4, {r0, r1, r2} 80011b0: e885 0007 stmia.w r5, {r0, r1, r2} /* USER CODE END TIM1_Init 2 */ HAL_TIM_MspPostInit(&htim1); 80011b4: 4803 ldr r0, [pc, #12] @ (80011c4 ) 80011b6: f003 f815 bl 80041e4 } 80011ba: bf00 nop 80011bc: 3758 adds r7, #88 @ 0x58 80011be: 46bd mov sp, r7 80011c0: bdb0 pop {r4, r5, r7, pc} 80011c2: bf00 nop 80011c4: 2400044c .word 0x2400044c 80011c8: 40010000 .word 0x40010000 80011cc: 2400071c .word 0x2400071c 080011d0 : * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { 80011d0: b5b0 push {r4, r5, r7, lr} 80011d2: b08a sub sp, #40 @ 0x28 80011d4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 80011d6: f107 031c add.w r3, r7, #28 80011da: 2200 movs r2, #0 80011dc: 601a str r2, [r3, #0] 80011de: 605a str r2, [r3, #4] 80011e0: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 80011e2: 463b mov r3, r7 80011e4: 2200 movs r2, #0 80011e6: 601a str r2, [r3, #0] 80011e8: 605a str r2, [r3, #4] 80011ea: 609a str r2, [r3, #8] 80011ec: 60da str r2, [r3, #12] 80011ee: 611a str r2, [r3, #16] 80011f0: 615a str r2, [r3, #20] 80011f2: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 80011f4: 4b48 ldr r3, [pc, #288] @ (8001318 ) 80011f6: 4a49 ldr r2, [pc, #292] @ (800131c ) 80011f8: 601a str r2, [r3, #0] htim3.Init.Prescaler = 199; 80011fa: 4b47 ldr r3, [pc, #284] @ (8001318 ) 80011fc: 22c7 movs r2, #199 @ 0xc7 80011fe: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8001200: 4b45 ldr r3, [pc, #276] @ (8001318 ) 8001202: 2200 movs r2, #0 8001204: 609a str r2, [r3, #8] htim3.Init.Period = 999; 8001206: 4b44 ldr r3, [pc, #272] @ (8001318 ) 8001208: f240 32e7 movw r2, #999 @ 0x3e7 800120c: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800120e: 4b42 ldr r3, [pc, #264] @ (8001318 ) 8001210: 2200 movs r2, #0 8001212: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001214: 4b40 ldr r3, [pc, #256] @ (8001318 ) 8001216: 2280 movs r2, #128 @ 0x80 8001218: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 800121a: 483f ldr r0, [pc, #252] @ (8001318 ) 800121c: f00e f8ac bl 800f378 8001220: 4603 mov r3, r0 8001222: 2b00 cmp r3, #0 8001224: d001 beq.n 800122a { Error_Handler(); 8001226: f000 fcd1 bl 8001bcc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800122a: 2300 movs r3, #0 800122c: 61fb str r3, [r7, #28] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800122e: 2300 movs r3, #0 8001230: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 8001232: f107 031c add.w r3, r7, #28 8001236: 4619 mov r1, r3 8001238: 4837 ldr r0, [pc, #220] @ (8001318 ) 800123a: f00f fa4f bl 80106dc 800123e: 4603 mov r3, r0 8001240: 2b00 cmp r3, #0 8001242: d001 beq.n 8001248 { Error_Handler(); 8001244: f000 fcc2 bl 8001bcc } sConfigOC.OCMode = TIM_OCMODE_COMBINED_PWM1; 8001248: 4b35 ldr r3, [pc, #212] @ (8001320 ) 800124a: 603b str r3, [r7, #0] sConfigOC.Pulse = 500; 800124c: f44f 73fa mov.w r3, #500 @ 0x1f4 8001250: 607b str r3, [r7, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8001252: 2300 movs r3, #0 8001254: 60bb str r3, [r7, #8] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001256: 2300 movs r3, #0 8001258: 613b str r3, [r7, #16] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 800125a: 463b mov r3, r7 800125c: 2200 movs r2, #0 800125e: 4619 mov r1, r3 8001260: 482d ldr r0, [pc, #180] @ (8001318 ) 8001262: f00e fb8d bl 800f980 8001266: 4603 mov r3, r0 8001268: 2b00 cmp r3, #0 800126a: d001 beq.n 8001270 { Error_Handler(); 800126c: f000 fcae bl 8001bcc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_1); 8001270: 4b29 ldr r3, [pc, #164] @ (8001318 ) 8001272: 681b ldr r3, [r3, #0] 8001274: 699a ldr r2, [r3, #24] 8001276: 4b28 ldr r3, [pc, #160] @ (8001318 ) 8001278: 681b ldr r3, [r3, #0] 800127a: f022 0208 bic.w r2, r2, #8 800127e: 619a str r2, [r3, #24] sConfigOC.OCMode = TIM_OCMODE_PWM1; 8001280: 2360 movs r3, #96 @ 0x60 8001282: 603b str r3, [r7, #0] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8001284: 463b mov r3, r7 8001286: 2204 movs r2, #4 8001288: 4619 mov r1, r3 800128a: 4823 ldr r0, [pc, #140] @ (8001318 ) 800128c: f00e fb78 bl 800f980 8001290: 4603 mov r3, r0 8001292: 2b00 cmp r3, #0 8001294: d001 beq.n 800129a { Error_Handler(); 8001296: f000 fc99 bl 8001bcc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_2); 800129a: 4b1f ldr r3, [pc, #124] @ (8001318 ) 800129c: 681b ldr r3, [r3, #0] 800129e: 699a ldr r2, [r3, #24] 80012a0: 4b1d ldr r3, [pc, #116] @ (8001318 ) 80012a2: 681b ldr r3, [r3, #0] 80012a4: f422 6200 bic.w r2, r2, #2048 @ 0x800 80012a8: 619a str r2, [r3, #24] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 80012aa: 463b mov r3, r7 80012ac: 2208 movs r2, #8 80012ae: 4619 mov r1, r3 80012b0: 4819 ldr r0, [pc, #100] @ (8001318 ) 80012b2: f00e fb65 bl 800f980 80012b6: 4603 mov r3, r0 80012b8: 2b00 cmp r3, #0 80012ba: d001 beq.n 80012c0 { Error_Handler(); 80012bc: f000 fc86 bl 8001bcc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_3); 80012c0: 4b15 ldr r3, [pc, #84] @ (8001318 ) 80012c2: 681b ldr r3, [r3, #0] 80012c4: 69da ldr r2, [r3, #28] 80012c6: 4b14 ldr r3, [pc, #80] @ (8001318 ) 80012c8: 681b ldr r3, [r3, #0] 80012ca: f022 0208 bic.w r2, r2, #8 80012ce: 61da str r2, [r3, #28] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 80012d0: 463b mov r3, r7 80012d2: 220c movs r2, #12 80012d4: 4619 mov r1, r3 80012d6: 4810 ldr r0, [pc, #64] @ (8001318 ) 80012d8: f00e fb52 bl 800f980 80012dc: 4603 mov r3, r0 80012de: 2b00 cmp r3, #0 80012e0: d001 beq.n 80012e6 { Error_Handler(); 80012e2: f000 fc73 bl 8001bcc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_4); 80012e6: 4b0c ldr r3, [pc, #48] @ (8001318 ) 80012e8: 681b ldr r3, [r3, #0] 80012ea: 69da ldr r2, [r3, #28] 80012ec: 4b0a ldr r3, [pc, #40] @ (8001318 ) 80012ee: 681b ldr r3, [r3, #0] 80012f0: f422 6200 bic.w r2, r2, #2048 @ 0x800 80012f4: 61da str r2, [r3, #28] /* USER CODE BEGIN TIM3_Init 2 */ memcpy(&motorXYTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 80012f6: 4b0b ldr r3, [pc, #44] @ (8001324 ) 80012f8: 461d mov r5, r3 80012fa: 463c mov r4, r7 80012fc: cc0f ldmia r4!, {r0, r1, r2, r3} 80012fe: c50f stmia r5!, {r0, r1, r2, r3} 8001300: e894 0007 ldmia.w r4, {r0, r1, r2} 8001304: e885 0007 stmia.w r5, {r0, r1, r2} /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 8001308: 4803 ldr r0, [pc, #12] @ (8001318 ) 800130a: f002 ff6b bl 80041e4 } 800130e: bf00 nop 8001310: 3728 adds r7, #40 @ 0x28 8001312: 46bd mov sp, r7 8001314: bdb0 pop {r4, r5, r7, pc} 8001316: bf00 nop 8001318: 24000498 .word 0x24000498 800131c: 40000400 .word 0x40000400 8001320: 00010040 .word 0x00010040 8001324: 24000738 .word 0x24000738 08001328 : * @brief TIM8 Initialization Function * @param None * @retval None */ static void MX_TIM8_Init(void) { 8001328: b580 push {r7, lr} 800132a: b088 sub sp, #32 800132c: af00 add r7, sp, #0 /* USER CODE BEGIN TIM8_Init 0 */ /* USER CODE END TIM8_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800132e: f107 0310 add.w r3, r7, #16 8001332: 2200 movs r2, #0 8001334: 601a str r2, [r3, #0] 8001336: 605a str r2, [r3, #4] 8001338: 609a str r2, [r3, #8] 800133a: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800133c: 1d3b adds r3, r7, #4 800133e: 2200 movs r2, #0 8001340: 601a str r2, [r3, #0] 8001342: 605a str r2, [r3, #4] 8001344: 609a str r2, [r3, #8] /* USER CODE BEGIN TIM8_Init 1 */ /* USER CODE END TIM8_Init 1 */ htim8.Instance = TIM8; 8001346: 4b21 ldr r3, [pc, #132] @ (80013cc ) 8001348: 4a21 ldr r2, [pc, #132] @ (80013d0 ) 800134a: 601a str r2, [r3, #0] htim8.Init.Prescaler = 9999; 800134c: 4b1f ldr r3, [pc, #124] @ (80013cc ) 800134e: f242 720f movw r2, #9999 @ 0x270f 8001352: 605a str r2, [r3, #4] htim8.Init.CounterMode = TIM_COUNTERMODE_UP; 8001354: 4b1d ldr r3, [pc, #116] @ (80013cc ) 8001356: 2200 movs r2, #0 8001358: 609a str r2, [r3, #8] htim8.Init.Period = 999; 800135a: 4b1c ldr r3, [pc, #112] @ (80013cc ) 800135c: f240 32e7 movw r2, #999 @ 0x3e7 8001360: 60da str r2, [r3, #12] htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2; 8001362: 4b1a ldr r3, [pc, #104] @ (80013cc ) 8001364: f44f 7280 mov.w r2, #256 @ 0x100 8001368: 611a str r2, [r3, #16] htim8.Init.RepetitionCounter = 0; 800136a: 4b18 ldr r3, [pc, #96] @ (80013cc ) 800136c: 2200 movs r2, #0 800136e: 615a str r2, [r3, #20] htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001370: 4b16 ldr r3, [pc, #88] @ (80013cc ) 8001372: 2280 movs r2, #128 @ 0x80 8001374: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim8) != HAL_OK) 8001376: 4815 ldr r0, [pc, #84] @ (80013cc ) 8001378: f00d febe bl 800f0f8 800137c: 4603 mov r3, r0 800137e: 2b00 cmp r3, #0 8001380: d001 beq.n 8001386 { Error_Handler(); 8001382: f000 fc23 bl 8001bcc } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8001386: f44f 5380 mov.w r3, #4096 @ 0x1000 800138a: 613b str r3, [r7, #16] if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) 800138c: f107 0310 add.w r3, r7, #16 8001390: 4619 mov r1, r3 8001392: 480e ldr r0, [pc, #56] @ (80013cc ) 8001394: f00e fc08 bl 800fba8 8001398: 4603 mov r3, r0 800139a: 2b00 cmp r3, #0 800139c: d001 beq.n 80013a2 { Error_Handler(); 800139e: f000 fc15 bl 8001bcc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 80013a2: 2320 movs r3, #32 80013a4: 607b str r3, [r7, #4] sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 80013a6: 2300 movs r3, #0 80013a8: 60bb str r3, [r7, #8] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; 80013aa: 2380 movs r3, #128 @ 0x80 80013ac: 60fb str r3, [r7, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 80013ae: 1d3b adds r3, r7, #4 80013b0: 4619 mov r1, r3 80013b2: 4806 ldr r0, [pc, #24] @ (80013cc ) 80013b4: f00f f992 bl 80106dc 80013b8: 4603 mov r3, r0 80013ba: 2b00 cmp r3, #0 80013bc: d001 beq.n 80013c2 { Error_Handler(); 80013be: f000 fc05 bl 8001bcc } /* USER CODE BEGIN TIM8_Init 2 */ /* USER CODE END TIM8_Init 2 */ } 80013c2: bf00 nop 80013c4: 3720 adds r7, #32 80013c6: 46bd mov sp, r7 80013c8: bd80 pop {r7, pc} 80013ca: bf00 nop 80013cc: 240004e4 .word 0x240004e4 80013d0: 40010400 .word 0x40010400 080013d4 : * @brief UART8 Initialization Function * @param None * @retval None */ static void MX_UART8_Init(void) { 80013d4: b580 push {r7, lr} 80013d6: af00 add r7, sp, #0 /* USER CODE END UART8_Init 0 */ /* USER CODE BEGIN UART8_Init 1 */ /* USER CODE END UART8_Init 1 */ huart8.Instance = UART8; 80013d8: 4b22 ldr r3, [pc, #136] @ (8001464 ) 80013da: 4a23 ldr r2, [pc, #140] @ (8001468 ) 80013dc: 601a str r2, [r3, #0] huart8.Init.BaudRate = 115200; 80013de: 4b21 ldr r3, [pc, #132] @ (8001464 ) 80013e0: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80013e4: 605a str r2, [r3, #4] huart8.Init.WordLength = UART_WORDLENGTH_8B; 80013e6: 4b1f ldr r3, [pc, #124] @ (8001464 ) 80013e8: 2200 movs r2, #0 80013ea: 609a str r2, [r3, #8] huart8.Init.StopBits = UART_STOPBITS_1; 80013ec: 4b1d ldr r3, [pc, #116] @ (8001464 ) 80013ee: 2200 movs r2, #0 80013f0: 60da str r2, [r3, #12] huart8.Init.Parity = UART_PARITY_NONE; 80013f2: 4b1c ldr r3, [pc, #112] @ (8001464 ) 80013f4: 2200 movs r2, #0 80013f6: 611a str r2, [r3, #16] huart8.Init.Mode = UART_MODE_TX_RX; 80013f8: 4b1a ldr r3, [pc, #104] @ (8001464 ) 80013fa: 220c movs r2, #12 80013fc: 615a str r2, [r3, #20] huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80013fe: 4b19 ldr r3, [pc, #100] @ (8001464 ) 8001400: 2200 movs r2, #0 8001402: 619a str r2, [r3, #24] huart8.Init.OverSampling = UART_OVERSAMPLING_16; 8001404: 4b17 ldr r3, [pc, #92] @ (8001464 ) 8001406: 2200 movs r2, #0 8001408: 61da str r2, [r3, #28] huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 800140a: 4b16 ldr r3, [pc, #88] @ (8001464 ) 800140c: 2200 movs r2, #0 800140e: 621a str r2, [r3, #32] huart8.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8001410: 4b14 ldr r3, [pc, #80] @ (8001464 ) 8001412: 2200 movs r2, #0 8001414: 625a str r2, [r3, #36] @ 0x24 huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8001416: 4b13 ldr r3, [pc, #76] @ (8001464 ) 8001418: 2200 movs r2, #0 800141a: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart8) != HAL_OK) 800141c: 4811 ldr r0, [pc, #68] @ (8001464 ) 800141e: f00f fa87 bl 8010930 8001422: 4603 mov r3, r0 8001424: 2b00 cmp r3, #0 8001426: d001 beq.n 800142c { Error_Handler(); 8001428: f000 fbd0 bl 8001bcc } if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 800142c: 2100 movs r1, #0 800142e: 480d ldr r0, [pc, #52] @ (8001464 ) 8001430: f011 ff27 bl 8013282 8001434: 4603 mov r3, r0 8001436: 2b00 cmp r3, #0 8001438: d001 beq.n 800143e { Error_Handler(); 800143a: f000 fbc7 bl 8001bcc } if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 800143e: 2100 movs r1, #0 8001440: 4808 ldr r0, [pc, #32] @ (8001464 ) 8001442: f011 ff5c bl 80132fe 8001446: 4603 mov r3, r0 8001448: 2b00 cmp r3, #0 800144a: d001 beq.n 8001450 { Error_Handler(); 800144c: f000 fbbe bl 8001bcc } if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK) 8001450: 4804 ldr r0, [pc, #16] @ (8001464 ) 8001452: f011 fedd bl 8013210 8001456: 4603 mov r3, r0 8001458: 2b00 cmp r3, #0 800145a: d001 beq.n 8001460 { Error_Handler(); 800145c: f000 fbb6 bl 8001bcc } /* USER CODE BEGIN UART8_Init 2 */ /* USER CODE END UART8_Init 2 */ } 8001460: bf00 nop 8001462: bd80 pop {r7, pc} 8001464: 24000530 .word 0x24000530 8001468: 40007c00 .word 0x40007c00 0800146c : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 800146c: b580 push {r7, lr} 800146e: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8001470: 4b24 ldr r3, [pc, #144] @ (8001504 ) 8001472: 4a25 ldr r2, [pc, #148] @ (8001508 ) 8001474: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 8001476: 4b23 ldr r3, [pc, #140] @ (8001504 ) 8001478: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800147c: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800147e: 4b21 ldr r3, [pc, #132] @ (8001504 ) 8001480: 2200 movs r2, #0 8001482: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8001484: 4b1f ldr r3, [pc, #124] @ (8001504 ) 8001486: 2200 movs r2, #0 8001488: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800148a: 4b1e ldr r3, [pc, #120] @ (8001504 ) 800148c: 2200 movs r2, #0 800148e: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8001490: 4b1c ldr r3, [pc, #112] @ (8001504 ) 8001492: 220c movs r2, #12 8001494: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001496: 4b1b ldr r3, [pc, #108] @ (8001504 ) 8001498: 2200 movs r2, #0 800149a: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800149c: 4b19 ldr r3, [pc, #100] @ (8001504 ) 800149e: 2200 movs r2, #0 80014a0: 61da str r2, [r3, #28] huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 80014a2: 4b18 ldr r3, [pc, #96] @ (8001504 ) 80014a4: 2200 movs r2, #0 80014a6: 621a str r2, [r3, #32] huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 80014a8: 4b16 ldr r3, [pc, #88] @ (8001504 ) 80014aa: 2200 movs r2, #0 80014ac: 625a str r2, [r3, #36] @ 0x24 huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_TXINVERT_INIT; 80014ae: 4b15 ldr r3, [pc, #84] @ (8001504 ) 80014b0: 2201 movs r2, #1 80014b2: 629a str r2, [r3, #40] @ 0x28 huart1.AdvancedInit.TxPinLevelInvert = UART_ADVFEATURE_TXINV_ENABLE; 80014b4: 4b13 ldr r3, [pc, #76] @ (8001504 ) 80014b6: f44f 3200 mov.w r2, #131072 @ 0x20000 80014ba: 62da str r2, [r3, #44] @ 0x2c if (HAL_UART_Init(&huart1) != HAL_OK) 80014bc: 4811 ldr r0, [pc, #68] @ (8001504 ) 80014be: f00f fa37 bl 8010930 80014c2: 4603 mov r3, r0 80014c4: 2b00 cmp r3, #0 80014c6: d001 beq.n 80014cc { Error_Handler(); 80014c8: f000 fb80 bl 8001bcc } if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 80014cc: 2100 movs r1, #0 80014ce: 480d ldr r0, [pc, #52] @ (8001504 ) 80014d0: f011 fed7 bl 8013282 80014d4: 4603 mov r3, r0 80014d6: 2b00 cmp r3, #0 80014d8: d001 beq.n 80014de { Error_Handler(); 80014da: f000 fb77 bl 8001bcc } if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 80014de: 2100 movs r1, #0 80014e0: 4808 ldr r0, [pc, #32] @ (8001504 ) 80014e2: f011 ff0c bl 80132fe 80014e6: 4603 mov r3, r0 80014e8: 2b00 cmp r3, #0 80014ea: d001 beq.n 80014f0 { Error_Handler(); 80014ec: f000 fb6e bl 8001bcc } if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) 80014f0: 4804 ldr r0, [pc, #16] @ (8001504 ) 80014f2: f011 fe8d bl 8013210 80014f6: 4603 mov r3, r0 80014f8: 2b00 cmp r3, #0 80014fa: d001 beq.n 8001500 { Error_Handler(); 80014fc: f000 fb66 bl 8001bcc } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8001500: bf00 nop 8001502: bd80 pop {r7, pc} 8001504: 240005c4 .word 0x240005c4 8001508: 40011000 .word 0x40011000 0800150c : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 800150c: b580 push {r7, lr} 800150e: b082 sub sp, #8 8001510: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 8001512: 4b15 ldr r3, [pc, #84] @ (8001568 ) 8001514: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8001518: 4a13 ldr r2, [pc, #76] @ (8001568 ) 800151a: f043 0301 orr.w r3, r3, #1 800151e: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8001522: 4b11 ldr r3, [pc, #68] @ (8001568 ) 8001524: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8001528: f003 0301 and.w r3, r3, #1 800152c: 607b str r3, [r7, #4] 800152e: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0); 8001530: 2200 movs r2, #0 8001532: 2105 movs r1, #5 8001534: 200b movs r0, #11 8001536: f006 f9e1 bl 80078fc HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 800153a: 200b movs r0, #11 800153c: f006 f9f8 bl 8007930 /* DMA1_Stream1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0); 8001540: 2200 movs r2, #0 8001542: 2105 movs r1, #5 8001544: 200c movs r0, #12 8001546: f006 f9d9 bl 80078fc HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn); 800154a: 200c movs r0, #12 800154c: f006 f9f0 bl 8007930 /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0); 8001550: 2200 movs r2, #0 8001552: 2105 movs r1, #5 8001554: 200d movs r0, #13 8001556: f006 f9d1 bl 80078fc HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 800155a: 200d movs r0, #13 800155c: f006 f9e8 bl 8007930 } 8001560: bf00 nop 8001562: 3708 adds r7, #8 8001564: 46bd mov sp, r7 8001566: bd80 pop {r7, pc} 8001568: 58024400 .word 0x58024400 0800156c : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 800156c: b580 push {r7, lr} 800156e: b08c sub sp, #48 @ 0x30 8001570: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001572: f107 031c add.w r3, r7, #28 8001576: 2200 movs r2, #0 8001578: 601a str r2, [r3, #0] 800157a: 605a str r2, [r3, #4] 800157c: 609a str r2, [r3, #8] 800157e: 60da str r2, [r3, #12] 8001580: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 8001582: 4b5b ldr r3, [pc, #364] @ (80016f0 ) 8001584: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001588: 4a59 ldr r2, [pc, #356] @ (80016f0 ) 800158a: f043 0380 orr.w r3, r3, #128 @ 0x80 800158e: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001592: 4b57 ldr r3, [pc, #348] @ (80016f0 ) 8001594: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001598: f003 0380 and.w r3, r3, #128 @ 0x80 800159c: 61bb str r3, [r7, #24] 800159e: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOC_CLK_ENABLE(); 80015a0: 4b53 ldr r3, [pc, #332] @ (80016f0 ) 80015a2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80015a6: 4a52 ldr r2, [pc, #328] @ (80016f0 ) 80015a8: f043 0304 orr.w r3, r3, #4 80015ac: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80015b0: 4b4f ldr r3, [pc, #316] @ (80016f0 ) 80015b2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80015b6: f003 0304 and.w r3, r3, #4 80015ba: 617b str r3, [r7, #20] 80015bc: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 80015be: 4b4c ldr r3, [pc, #304] @ (80016f0 ) 80015c0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80015c4: 4a4a ldr r2, [pc, #296] @ (80016f0 ) 80015c6: f043 0301 orr.w r3, r3, #1 80015ca: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80015ce: 4b48 ldr r3, [pc, #288] @ (80016f0 ) 80015d0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80015d4: f003 0301 and.w r3, r3, #1 80015d8: 613b str r3, [r7, #16] 80015da: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80015dc: 4b44 ldr r3, [pc, #272] @ (80016f0 ) 80015de: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80015e2: 4a43 ldr r2, [pc, #268] @ (80016f0 ) 80015e4: f043 0302 orr.w r3, r3, #2 80015e8: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80015ec: 4b40 ldr r3, [pc, #256] @ (80016f0 ) 80015ee: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80015f2: f003 0302 and.w r3, r3, #2 80015f6: 60fb str r3, [r7, #12] 80015f8: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 80015fa: 4b3d ldr r3, [pc, #244] @ (80016f0 ) 80015fc: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001600: 4a3b ldr r2, [pc, #236] @ (80016f0 ) 8001602: f043 0310 orr.w r3, r3, #16 8001606: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800160a: 4b39 ldr r3, [pc, #228] @ (80016f0 ) 800160c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001610: f003 0310 and.w r3, r3, #16 8001614: 60bb str r3, [r7, #8] 8001616: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 8001618: 4b35 ldr r3, [pc, #212] @ (80016f0 ) 800161a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800161e: 4a34 ldr r2, [pc, #208] @ (80016f0 ) 8001620: f043 0308 orr.w r3, r3, #8 8001624: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001628: 4b31 ldr r3, [pc, #196] @ (80016f0 ) 800162a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800162e: f003 0308 and.w r3, r3, #8 8001632: 607b str r3, [r7, #4] 8001634: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 8001636: 2200 movs r2, #0 8001638: f24e 7180 movw r1, #59264 @ 0xe780 800163c: 482d ldr r0, [pc, #180] @ (80016f4 ) 800163e: f009 fe57 bl 800b2f0 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET); 8001642: 2200 movs r2, #0 8001644: 21f0 movs r1, #240 @ 0xf0 8001646: 482c ldr r0, [pc, #176] @ (80016f8 ) 8001648: f009 fe52 bl 800b2f0 /*Configure GPIO pins : PE7 PE8 PE9 PE10 PE13 PE14 PE15 */ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 800164c: f24e 7380 movw r3, #59264 @ 0xe780 8001650: 61fb str r3, [r7, #28] |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001652: 2301 movs r3, #1 8001654: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001656: 2300 movs r3, #0 8001658: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800165a: 2300 movs r3, #0 800165c: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800165e: f107 031c add.w r3, r7, #28 8001662: 4619 mov r1, r3 8001664: 4823 ldr r0, [pc, #140] @ (80016f4 ) 8001666: f009 fc7b bl 800af60 /*Configure GPIO pins : PB10 PB11 */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; 800166a: f44f 6340 mov.w r3, #3072 @ 0xc00 800166e: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 8001670: f44f 1344 mov.w r3, #3211264 @ 0x310000 8001674: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001676: 2300 movs r3, #0 8001678: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800167a: f107 031c add.w r3, r7, #28 800167e: 4619 mov r1, r3 8001680: 481e ldr r0, [pc, #120] @ (80016fc ) 8001682: f009 fc6d bl 800af60 /*Configure GPIO pins : PD8 PD9 PD10 PD11 PD12 PD13 PD3 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 8001686: f643 7308 movw r3, #16136 @ 0x3f08 800168a: 61fb str r3, [r7, #28] |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800168c: 2300 movs r3, #0 800168e: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001690: 2300 movs r3, #0 8001692: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001694: f107 031c add.w r3, r7, #28 8001698: 4619 mov r1, r3 800169a: 4817 ldr r0, [pc, #92] @ (80016f8 ) 800169c: f009 fc60 bl 800af60 /*Configure GPIO pins : PD14 PD15 */ GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 80016a0: f44f 4340 mov.w r3, #49152 @ 0xc000 80016a4: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 80016a6: f44f 1344 mov.w r3, #3211264 @ 0x310000 80016aa: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 80016ac: 2300 movs r3, #0 80016ae: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80016b0: f107 031c add.w r3, r7, #28 80016b4: 4619 mov r1, r3 80016b6: 4810 ldr r0, [pc, #64] @ (80016f8 ) 80016b8: f009 fc52 bl 800af60 /*Configure GPIO pins : PD4 PD5 PD6 PD7 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; 80016bc: 23f0 movs r3, #240 @ 0xf0 80016be: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80016c0: 2301 movs r3, #1 80016c2: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 80016c4: 2300 movs r3, #0 80016c6: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80016c8: 2300 movs r3, #0 80016ca: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80016cc: f107 031c add.w r3, r7, #28 80016d0: 4619 mov r1, r3 80016d2: 4809 ldr r0, [pc, #36] @ (80016f8 ) 80016d4: f009 fc44 bl 800af60 /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0); 80016d8: 2200 movs r2, #0 80016da: 2105 movs r1, #5 80016dc: 2028 movs r0, #40 @ 0x28 80016de: f006 f90d bl 80078fc HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); 80016e2: 2028 movs r0, #40 @ 0x28 80016e4: f006 f924 bl 8007930 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 80016e8: bf00 nop 80016ea: 3730 adds r7, #48 @ 0x30 80016ec: 46bd mov sp, r7 80016ee: bd80 pop {r7, pc} 80016f0: 58024400 .word 0x58024400 80016f4: 58021000 .word 0x58021000 80016f8: 58020c00 .word 0x58020c00 80016fc: 58020400 .word 0x58020400 08001700 : /* USER CODE BEGIN 4 */ void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { 8001700: b580 push {r7, lr} 8001702: b08e sub sp, #56 @ 0x38 8001704: af00 add r7, sp, #0 8001706: 6078 str r0, [r7, #4] if(hadc->Instance == ADC1) 8001708: 687b ldr r3, [r7, #4] 800170a: 681b ldr r3, [r3, #0] 800170c: 4a67 ldr r2, [pc, #412] @ (80018ac ) 800170e: 4293 cmp r3, r2 8001710: d13f bne.n 8001792 { DbgLEDToggle(DBG_LED4); 8001712: 2080 movs r0, #128 @ 0x80 8001714: f001 fb26 bl 8002d64 SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc1Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 8001718: 4b65 ldr r3, [pc, #404] @ (80018b0 ) 800171a: f023 031f bic.w r3, r3, #31 800171e: 637b str r3, [r7, #52] @ 0x34 8001720: 2320 movs r3, #32 8001722: 633b str r3, [r7, #48] @ 0x30 if ( dsize > 0 ) { 8001724: 6b3b ldr r3, [r7, #48] @ 0x30 8001726: 2b00 cmp r3, #0 8001728: dd1d ble.n 8001766 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 800172a: 6b7b ldr r3, [r7, #52] @ 0x34 800172c: f003 021f and.w r2, r3, #31 8001730: 6b3b ldr r3, [r7, #48] @ 0x30 8001732: 4413 add r3, r2 8001734: 62fb str r3, [r7, #44] @ 0x2c uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 8001736: 6b7b ldr r3, [r7, #52] @ 0x34 8001738: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("dsb 0xF":::"memory"); 800173a: f3bf 8f4f dsb sy } 800173e: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 8001740: 4a5c ldr r2, [pc, #368] @ (80018b4 ) 8001742: 6abb ldr r3, [r7, #40] @ 0x28 8001744: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 8001748: 6abb ldr r3, [r7, #40] @ 0x28 800174a: 3320 adds r3, #32 800174c: 62bb str r3, [r7, #40] @ 0x28 op_size -= __SCB_DCACHE_LINE_SIZE; 800174e: 6afb ldr r3, [r7, #44] @ 0x2c 8001750: 3b20 subs r3, #32 8001752: 62fb str r3, [r7, #44] @ 0x2c } while ( op_size > 0 ); 8001754: 6afb ldr r3, [r7, #44] @ 0x2c 8001756: 2b00 cmp r3, #0 8001758: dcf2 bgt.n 8001740 __ASM volatile ("dsb 0xF":::"memory"); 800175a: f3bf 8f4f dsb sy } 800175e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8001760: f3bf 8f6f isb sy } 8001764: bf00 nop } 8001766: bf00 nop if(adc1MeasDataQueue != NULL) 8001768: 4b53 ldr r3, [pc, #332] @ (80018b8 ) 800176a: 681b ldr r3, [r3, #0] 800176c: 2b00 cmp r3, #0 800176e: d006 beq.n 800177e { osMessageQueuePut(adc1MeasDataQueue, &adc1Data, 0, 0); 8001770: 4b51 ldr r3, [pc, #324] @ (80018b8 ) 8001772: 6818 ldr r0, [r3, #0] 8001774: 2300 movs r3, #0 8001776: 2200 movs r2, #0 8001778: 494d ldr r1, [pc, #308] @ (80018b0 ) 800177a: f012 fa51 bl 8013c20 } if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK) 800177e: 2207 movs r2, #7 8001780: 494b ldr r1, [pc, #300] @ (80018b0 ) 8001782: 484e ldr r0, [pc, #312] @ (80018bc ) 8001784: f004 fe16 bl 80063b4 8001788: 4603 mov r3, r0 800178a: 2b00 cmp r3, #0 800178c: d001 beq.n 8001792 { Error_Handler(); 800178e: f000 fa1d bl 8001bcc } } if(hadc->Instance == ADC2) 8001792: 687b ldr r3, [r7, #4] 8001794: 681b ldr r3, [r3, #0] 8001796: 4a4a ldr r2, [pc, #296] @ (80018c0 ) 8001798: 4293 cmp r3, r2 800179a: d13c bne.n 8001816 { SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc2Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 800179c: 4b49 ldr r3, [pc, #292] @ (80018c4 ) 800179e: f023 031f bic.w r3, r3, #31 80017a2: 627b str r3, [r7, #36] @ 0x24 80017a4: 2320 movs r3, #32 80017a6: 623b str r3, [r7, #32] if ( dsize > 0 ) { 80017a8: 6a3b ldr r3, [r7, #32] 80017aa: 2b00 cmp r3, #0 80017ac: dd1d ble.n 80017ea int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 80017ae: 6a7b ldr r3, [r7, #36] @ 0x24 80017b0: f003 021f and.w r2, r3, #31 80017b4: 6a3b ldr r3, [r7, #32] 80017b6: 4413 add r3, r2 80017b8: 61fb str r3, [r7, #28] uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 80017ba: 6a7b ldr r3, [r7, #36] @ 0x24 80017bc: 61bb str r3, [r7, #24] __ASM volatile ("dsb 0xF":::"memory"); 80017be: f3bf 8f4f dsb sy } 80017c2: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 80017c4: 4a3b ldr r2, [pc, #236] @ (80018b4 ) 80017c6: 69bb ldr r3, [r7, #24] 80017c8: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 80017cc: 69bb ldr r3, [r7, #24] 80017ce: 3320 adds r3, #32 80017d0: 61bb str r3, [r7, #24] op_size -= __SCB_DCACHE_LINE_SIZE; 80017d2: 69fb ldr r3, [r7, #28] 80017d4: 3b20 subs r3, #32 80017d6: 61fb str r3, [r7, #28] } while ( op_size > 0 ); 80017d8: 69fb ldr r3, [r7, #28] 80017da: 2b00 cmp r3, #0 80017dc: dcf2 bgt.n 80017c4 __ASM volatile ("dsb 0xF":::"memory"); 80017de: f3bf 8f4f dsb sy } 80017e2: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80017e4: f3bf 8f6f isb sy } 80017e8: bf00 nop } 80017ea: bf00 nop if(adc2MeasDataQueue != NULL) 80017ec: 4b36 ldr r3, [pc, #216] @ (80018c8 ) 80017ee: 681b ldr r3, [r3, #0] 80017f0: 2b00 cmp r3, #0 80017f2: d006 beq.n 8001802 { osMessageQueuePut(adc2MeasDataQueue, &adc2Data, 0, 0); 80017f4: 4b34 ldr r3, [pc, #208] @ (80018c8 ) 80017f6: 6818 ldr r0, [r3, #0] 80017f8: 2300 movs r3, #0 80017fa: 2200 movs r2, #0 80017fc: 4931 ldr r1, [pc, #196] @ (80018c4 ) 80017fe: f012 fa0f bl 8013c20 } if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK) 8001802: 2203 movs r2, #3 8001804: 492f ldr r1, [pc, #188] @ (80018c4 ) 8001806: 4831 ldr r0, [pc, #196] @ (80018cc ) 8001808: f004 fdd4 bl 80063b4 800180c: 4603 mov r3, r0 800180e: 2b00 cmp r3, #0 8001810: d001 beq.n 8001816 { Error_Handler(); 8001812: f000 f9db bl 8001bcc } } if(hadc->Instance == ADC3) 8001816: 687b ldr r3, [r7, #4] 8001818: 681b ldr r3, [r3, #0] 800181a: 4a2d ldr r2, [pc, #180] @ (80018d0 ) 800181c: 4293 cmp r3, r2 800181e: d13c bne.n 800189a { SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc3Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 8001820: 4b2c ldr r3, [pc, #176] @ (80018d4 ) 8001822: f023 031f bic.w r3, r3, #31 8001826: 617b str r3, [r7, #20] 8001828: 2320 movs r3, #32 800182a: 613b str r3, [r7, #16] if ( dsize > 0 ) { 800182c: 693b ldr r3, [r7, #16] 800182e: 2b00 cmp r3, #0 8001830: dd1d ble.n 800186e int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 8001832: 697b ldr r3, [r7, #20] 8001834: f003 021f and.w r2, r3, #31 8001838: 693b ldr r3, [r7, #16] 800183a: 4413 add r3, r2 800183c: 60fb str r3, [r7, #12] uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 800183e: 697b ldr r3, [r7, #20] 8001840: 60bb str r3, [r7, #8] __ASM volatile ("dsb 0xF":::"memory"); 8001842: f3bf 8f4f dsb sy } 8001846: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 8001848: 4a1a ldr r2, [pc, #104] @ (80018b4 ) 800184a: 68bb ldr r3, [r7, #8] 800184c: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 8001850: 68bb ldr r3, [r7, #8] 8001852: 3320 adds r3, #32 8001854: 60bb str r3, [r7, #8] op_size -= __SCB_DCACHE_LINE_SIZE; 8001856: 68fb ldr r3, [r7, #12] 8001858: 3b20 subs r3, #32 800185a: 60fb str r3, [r7, #12] } while ( op_size > 0 ); 800185c: 68fb ldr r3, [r7, #12] 800185e: 2b00 cmp r3, #0 8001860: dcf2 bgt.n 8001848 __ASM volatile ("dsb 0xF":::"memory"); 8001862: f3bf 8f4f dsb sy } 8001866: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8001868: f3bf 8f6f isb sy } 800186c: bf00 nop } 800186e: bf00 nop if(adc3MeasDataQueue != NULL) 8001870: 4b19 ldr r3, [pc, #100] @ (80018d8 ) 8001872: 681b ldr r3, [r3, #0] 8001874: 2b00 cmp r3, #0 8001876: d006 beq.n 8001886 { osMessageQueuePut(adc3MeasDataQueue, &adc3Data, 0, 0); 8001878: 4b17 ldr r3, [pc, #92] @ (80018d8 ) 800187a: 6818 ldr r0, [r3, #0] 800187c: 2300 movs r3, #0 800187e: 2200 movs r2, #0 8001880: 4914 ldr r1, [pc, #80] @ (80018d4 ) 8001882: f012 f9cd bl 8013c20 } if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK) 8001886: 2205 movs r2, #5 8001888: 4912 ldr r1, [pc, #72] @ (80018d4 ) 800188a: 4814 ldr r0, [pc, #80] @ (80018dc ) 800188c: f004 fd92 bl 80063b4 8001890: 4603 mov r3, r0 8001892: 2b00 cmp r3, #0 8001894: d001 beq.n 800189a { Error_Handler(); 8001896: f000 f999 bl 8001bcc } }osTimerStop (debugLedTimerHandle); 800189a: 4b11 ldr r3, [pc, #68] @ (80018e0 ) 800189c: 681b ldr r3, [r3, #0] 800189e: 4618 mov r0, r3 80018a0: f012 f806 bl 80138b0 } 80018a4: bf00 nop 80018a6: 3738 adds r7, #56 @ 0x38 80018a8: 46bd mov sp, r7 80018aa: bd80 pop {r7, pc} 80018ac: 40022000 .word 0x40022000 80018b0: 240000e0 .word 0x240000e0 80018b4: e000ed00 .word 0xe000ed00 80018b8: 2400077c .word 0x2400077c 80018bc: 24000140 .word 0x24000140 80018c0: 40022100 .word 0x40022100 80018c4: 24000100 .word 0x24000100 80018c8: 24000780 .word 0x24000780 80018cc: 240001a4 .word 0x240001a4 80018d0: 58026000 .word 0x58026000 80018d4: 24000120 .word 0x24000120 80018d8: 24000784 .word 0x24000784 80018dc: 24000208 .word 0x24000208 80018e0: 2400065c .word 0x2400065c 080018e4 : * @param argument: Not used * @retval None */ /* USER CODE END Header_StartDefaultTask */ void StartDefaultTask(void *argument) { 80018e4: b580 push {r7, lr} 80018e6: b082 sub sp, #8 80018e8: af00 add r7, sp, #0 80018ea: 6078 str r0, [r7, #4] /* USER CODE BEGIN 5 */ #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); #endif SelectCurrentSensorGain(CurrentSensorL1, csGain3); 80018ec: 2102 movs r1, #2 80018ee: 2000 movs r0, #0 80018f0: f001 fa56 bl 8002da0 SelectCurrentSensorGain(CurrentSensorL2, csGain3); 80018f4: 2102 movs r1, #2 80018f6: 2001 movs r0, #1 80018f8: f001 fa52 bl 8002da0 SelectCurrentSensorGain(CurrentSensorL3, csGain3); 80018fc: 2102 movs r1, #2 80018fe: 2002 movs r0, #2 8001900: f001 fa4e bl 8002da0 EnableCurrentSensors(); 8001904: f001 fa40 bl 8002d88 osDelay(pdMS_TO_TICKS(100)); 8001908: 2064 movs r0, #100 @ 0x64 800190a: f011 fef6 bl 80136fa #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); #endif if(HAL_TIM_Base_Start(&htim8) != HAL_OK) 800190e: 4836 ldr r0, [pc, #216] @ (80019e8 ) 8001910: f00d fc4a bl 800f1a8 8001914: 4603 mov r3, r0 8001916: 2b00 cmp r3, #0 8001918: d001 beq.n 800191e { Error_Handler(); 800191a: f000 f957 bl 8001bcc } if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK) 800191e: 2207 movs r2, #7 8001920: 4932 ldr r1, [pc, #200] @ (80019ec ) 8001922: 4833 ldr r0, [pc, #204] @ (80019f0 ) 8001924: f004 fd46 bl 80063b4 8001928: 4603 mov r3, r0 800192a: 2b00 cmp r3, #0 800192c: d001 beq.n 8001932 { Error_Handler(); 800192e: f000 f94d bl 8001bcc } if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK) 8001932: 2203 movs r2, #3 8001934: 492f ldr r1, [pc, #188] @ (80019f4 ) 8001936: 4830 ldr r0, [pc, #192] @ (80019f8 ) 8001938: f004 fd3c bl 80063b4 800193c: 4603 mov r3, r0 800193e: 2b00 cmp r3, #0 8001940: d001 beq.n 8001946 { Error_Handler(); 8001942: f000 f943 bl 8001bcc } if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK) 8001946: 2205 movs r2, #5 8001948: 492c ldr r1, [pc, #176] @ (80019fc ) 800194a: 482d ldr r0, [pc, #180] @ (8001a00 ) 800194c: f004 fd32 bl 80063b4 8001950: 4603 mov r3, r0 8001952: 2b00 cmp r3, #0 8001954: d001 beq.n 800195a { Error_Handler(); 8001956: f000 f939 bl 8001bcc } HAL_COMP_Start(&hcomp1); 800195a: 482a ldr r0, [pc, #168] @ (8001a04 ) 800195c: f005 feae bl 80076bc HAL_IWDG_Refresh(&hiwdg1); #endif /* Infinite loop */ for(;;) { osDelay(pdMS_TO_TICKS(100)); 8001960: 2064 movs r0, #100 @ 0x64 8001962: f011 feca bl 80136fa #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); #endif if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 8001966: 2100 movs r1, #0 8001968: 4827 ldr r0, [pc, #156] @ (8001a08 ) 800196a: f00e fa3d bl 800fde8 800196e: 4603 mov r3, r0 8001970: 2b01 cmp r3, #1 8001972: d118 bne.n 80019a6 HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_2) == HAL_TIM_CHANNEL_STATE_READY) 8001974: 2104 movs r1, #4 8001976: 4824 ldr r0, [pc, #144] @ (8001a08 ) 8001978: f00e fa36 bl 800fde8 800197c: 4603 mov r3, r0 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 800197e: 2b01 cmp r3, #1 8001980: d111 bne.n 80019a6 { if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 8001982: 4b22 ldr r3, [pc, #136] @ (8001a0c ) 8001984: 681b ldr r3, [r3, #0] 8001986: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800198a: 4618 mov r0, r3 800198c: f012 f84d bl 8013a2a 8001990: 4603 mov r3, r0 8001992: 2b00 cmp r3, #0 8001994: d107 bne.n 80019a6 { sensorsInfo.motorXStatus = 0; 8001996: 4b1e ldr r3, [pc, #120] @ (8001a10 ) 8001998: 2200 movs r2, #0 800199a: 751a strb r2, [r3, #20] osMutexRelease(sensorsInfoMutex); 800199c: 4b1b ldr r3, [pc, #108] @ (8001a0c ) 800199e: 681b ldr r3, [r3, #0] 80019a0: 4618 mov r0, r3 80019a2: f012 f88d bl 8013ac0 } } if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 80019a6: 2108 movs r1, #8 80019a8: 4817 ldr r0, [pc, #92] @ (8001a08 ) 80019aa: f00e fa1d bl 800fde8 80019ae: 4603 mov r3, r0 80019b0: 2b01 cmp r3, #1 80019b2: d1d5 bne.n 8001960 HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_4) == HAL_TIM_CHANNEL_STATE_READY) 80019b4: 210c movs r1, #12 80019b6: 4814 ldr r0, [pc, #80] @ (8001a08 ) 80019b8: f00e fa16 bl 800fde8 80019bc: 4603 mov r3, r0 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 80019be: 2b01 cmp r3, #1 80019c0: d1ce bne.n 8001960 { if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 80019c2: 4b12 ldr r3, [pc, #72] @ (8001a0c ) 80019c4: 681b ldr r3, [r3, #0] 80019c6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80019ca: 4618 mov r0, r3 80019cc: f012 f82d bl 8013a2a 80019d0: 4603 mov r3, r0 80019d2: 2b00 cmp r3, #0 80019d4: d1c4 bne.n 8001960 { sensorsInfo.motorYStatus = 0; 80019d6: 4b0e ldr r3, [pc, #56] @ (8001a10 ) 80019d8: 2200 movs r2, #0 80019da: 755a strb r2, [r3, #21] osMutexRelease(sensorsInfoMutex); 80019dc: 4b0b ldr r3, [pc, #44] @ (8001a0c ) 80019de: 681b ldr r3, [r3, #0] 80019e0: 4618 mov r0, r3 80019e2: f012 f86d bl 8013ac0 osDelay(pdMS_TO_TICKS(100)); 80019e6: e7bb b.n 8001960 80019e8: 240004e4 .word 0x240004e4 80019ec: 240000e0 .word 0x240000e0 80019f0: 24000140 .word 0x24000140 80019f4: 24000100 .word 0x24000100 80019f8: 240001a4 .word 0x240001a4 80019fc: 24000120 .word 0x24000120 8001a00: 24000208 .word 0x24000208 8001a04: 240003d4 .word 0x240003d4 8001a08: 24000498 .word 0x24000498 8001a0c: 24000790 .word 0x24000790 8001a10: 240007e0 .word 0x240007e0 08001a14 : /* USER CODE END 5 */ } /* debugLedTimerCallback function */ void debugLedTimerCallback(void *argument) { 8001a14: b580 push {r7, lr} 8001a16: b082 sub sp, #8 8001a18: af00 add r7, sp, #0 8001a1a: 6078 str r0, [r7, #4] /* USER CODE BEGIN debugLedTimerCallback */ DbgLEDOff (DBG_LED1); 8001a1c: 2010 movs r0, #16 8001a1e: f001 f98f bl 8002d40 /* USER CODE END debugLedTimerCallback */ } 8001a22: bf00 nop 8001a24: 3708 adds r7, #8 8001a26: 46bd mov sp, r7 8001a28: bd80 pop {r7, pc} ... 08001a2c : /* fanTimerCallback function */ void fanTimerCallback(void *argument) { 8001a2c: b580 push {r7, lr} 8001a2e: b082 sub sp, #8 8001a30: af00 add r7, sp, #0 8001a32: 6078 str r0, [r7, #4] /* USER CODE BEGIN fanTimerCallback */ HAL_TIM_PWM_Stop(&htim1, TIM_CHANNEL_2); 8001a34: 2104 movs r1, #4 8001a36: 4803 ldr r0, [pc, #12] @ (8001a44 ) 8001a38: f00d fe04 bl 800f644 /* USER CODE END fanTimerCallback */ } 8001a3c: bf00 nop 8001a3e: 3708 adds r7, #8 8001a40: 46bd mov sp, r7 8001a42: bd80 pop {r7, pc} 8001a44: 2400044c .word 0x2400044c 08001a48 : /* motorXTimerCallback function */ void motorXTimerCallback(void *argument) { 8001a48: b580 push {r7, lr} 8001a4a: b084 sub sp, #16 8001a4c: af02 add r7, sp, #8 8001a4e: 6078 str r0, [r7, #4] /* USER CODE BEGIN motorXTimerCallback */ MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, HiZ, 0); 8001a50: 2300 movs r3, #0 8001a52: 9301 str r3, [sp, #4] 8001a54: 2300 movs r3, #0 8001a56: 9300 str r3, [sp, #0] 8001a58: 2304 movs r3, #4 8001a5a: 2200 movs r2, #0 8001a5c: 4907 ldr r1, [pc, #28] @ (8001a7c ) 8001a5e: 4808 ldr r0, [pc, #32] @ (8001a80 ) 8001a60: f001 fb23 bl 80030aa HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_1); 8001a64: 2100 movs r1, #0 8001a66: 4806 ldr r0, [pc, #24] @ (8001a80 ) 8001a68: f00d fdec bl 800f644 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_2); 8001a6c: 2104 movs r1, #4 8001a6e: 4804 ldr r0, [pc, #16] @ (8001a80 ) 8001a70: f00d fde8 bl 800f644 /* USER CODE END motorXTimerCallback */ } 8001a74: bf00 nop 8001a76: 3708 adds r7, #8 8001a78: 46bd mov sp, r7 8001a7a: bd80 pop {r7, pc} 8001a7c: 24000738 .word 0x24000738 8001a80: 24000498 .word 0x24000498 08001a84 : /* motorYTimerCallback function */ void motorYTimerCallback(void *argument) { 8001a84: b580 push {r7, lr} 8001a86: b084 sub sp, #16 8001a88: af02 add r7, sp, #8 8001a8a: 6078 str r0, [r7, #4] /* USER CODE BEGIN motorYTimerCallback */ MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, HiZ, 0); 8001a8c: 2300 movs r3, #0 8001a8e: 9301 str r3, [sp, #4] 8001a90: 2300 movs r3, #0 8001a92: 9300 str r3, [sp, #0] 8001a94: 230c movs r3, #12 8001a96: 2208 movs r2, #8 8001a98: 4907 ldr r1, [pc, #28] @ (8001ab8 ) 8001a9a: 4808 ldr r0, [pc, #32] @ (8001abc ) 8001a9c: f001 fb05 bl 80030aa HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_3); 8001aa0: 2108 movs r1, #8 8001aa2: 4806 ldr r0, [pc, #24] @ (8001abc ) 8001aa4: f00d fdce bl 800f644 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_4); 8001aa8: 210c movs r1, #12 8001aaa: 4804 ldr r0, [pc, #16] @ (8001abc ) 8001aac: f00d fdca bl 800f644 /* USER CODE END motorYTimerCallback */ } 8001ab0: bf00 nop 8001ab2: 3708 adds r7, #8 8001ab4: 46bd mov sp, r7 8001ab6: bd80 pop {r7, pc} 8001ab8: 24000738 .word 0x24000738 8001abc: 24000498 .word 0x24000498 08001ac0 : /* MPU Configuration */ void MPU_Config(void) { 8001ac0: b580 push {r7, lr} 8001ac2: b084 sub sp, #16 8001ac4: af00 add r7, sp, #0 MPU_Region_InitTypeDef MPU_InitStruct = {0}; 8001ac6: 463b mov r3, r7 8001ac8: 2200 movs r2, #0 8001aca: 601a str r2, [r3, #0] 8001acc: 605a str r2, [r3, #4] 8001ace: 609a str r2, [r3, #8] 8001ad0: 60da str r2, [r3, #12] /* Disables the MPU */ HAL_MPU_Disable(); 8001ad2: f005 ff3b bl 800794c /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; 8001ad6: 2301 movs r3, #1 8001ad8: 703b strb r3, [r7, #0] MPU_InitStruct.Number = MPU_REGION_NUMBER0; 8001ada: 2300 movs r3, #0 8001adc: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x0; 8001ade: 2300 movs r3, #0 8001ae0: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; 8001ae2: 231f movs r3, #31 8001ae4: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x87; 8001ae6: 2387 movs r3, #135 @ 0x87 8001ae8: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8001aea: 2300 movs r3, #0 8001aec: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; 8001aee: 2300 movs r3, #0 8001af0: 72fb strb r3, [r7, #11] MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; 8001af2: 2301 movs r3, #1 8001af4: 733b strb r3, [r7, #12] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8001af6: 2301 movs r3, #1 8001af8: 737b strb r3, [r7, #13] MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; 8001afa: 2300 movs r3, #0 8001afc: 73bb strb r3, [r7, #14] MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; 8001afe: 2300 movs r3, #0 8001b00: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001b02: 463b mov r3, r7 8001b04: 4618 mov r0, r3 8001b06: f005 ff59 bl 80079bc /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER1; 8001b0a: 2301 movs r3, #1 8001b0c: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24020000; 8001b0e: 4b13 ldr r3, [pc, #76] @ (8001b5c ) 8001b10: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_128KB; 8001b12: 2310 movs r3, #16 8001b14: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x0; 8001b16: 2300 movs r3, #0 8001b18: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; 8001b1a: 2301 movs r3, #1 8001b1c: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; 8001b1e: 2303 movs r3, #3 8001b20: 72fb strb r3, [r7, #11] MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 8001b22: 2300 movs r3, #0 8001b24: 737b strb r3, [r7, #13] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001b26: 463b mov r3, r7 8001b28: 4618 mov r0, r3 8001b2a: f005 ff47 bl 80079bc /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER2; 8001b2e: 2302 movs r3, #2 8001b30: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24040000; 8001b32: 4b0b ldr r3, [pc, #44] @ (8001b60 ) 8001b34: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_512B; 8001b36: 2308 movs r3, #8 8001b38: 723b strb r3, [r7, #8] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8001b3a: 2300 movs r3, #0 8001b3c: 72bb strb r3, [r7, #10] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8001b3e: 2301 movs r3, #1 8001b40: 737b strb r3, [r7, #13] MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; 8001b42: 2301 movs r3, #1 8001b44: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001b46: 463b mov r3, r7 8001b48: 4618 mov r0, r3 8001b4a: f005 ff37 bl 80079bc /* Enables the MPU */ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); 8001b4e: 2004 movs r0, #4 8001b50: f005 ff14 bl 800797c } 8001b54: bf00 nop 8001b56: 3710 adds r7, #16 8001b58: 46bd mov sp, r7 8001b5a: bd80 pop {r7, pc} 8001b5c: 24020000 .word 0x24020000 8001b60: 24040000 .word 0x24040000 08001b64 : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8001b64: b580 push {r7, lr} 8001b66: b082 sub sp, #8 8001b68: af00 add r7, sp, #0 8001b6a: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM6) { 8001b6c: 687b ldr r3, [r7, #4] 8001b6e: 681b ldr r3, [r3, #0] 8001b70: 4a10 ldr r2, [pc, #64] @ (8001bb4 ) 8001b72: 4293 cmp r3, r2 8001b74: d102 bne.n 8001b7c HAL_IncTick(); 8001b76: f004 f807 bl 8005b88 { encoderYChannelA = 0; encoderYChannelB = 0; } /* USER CODE END Callback 1 */ } 8001b7a: e016 b.n 8001baa else if (htim->Instance == TIM4) 8001b7c: 687b ldr r3, [r7, #4] 8001b7e: 681b ldr r3, [r3, #0] 8001b80: 4a0d ldr r2, [pc, #52] @ (8001bb8 ) 8001b82: 4293 cmp r3, r2 8001b84: d106 bne.n 8001b94 encoderXChannelA = 0; 8001b86: 4b0d ldr r3, [pc, #52] @ (8001bbc ) 8001b88: 2200 movs r2, #0 8001b8a: 601a str r2, [r3, #0] encoderXChannelB = 0; 8001b8c: 4b0c ldr r3, [pc, #48] @ (8001bc0 ) 8001b8e: 2200 movs r2, #0 8001b90: 601a str r2, [r3, #0] } 8001b92: e00a b.n 8001baa else if (htim->Instance == TIM2) 8001b94: 687b ldr r3, [r7, #4] 8001b96: 681b ldr r3, [r3, #0] 8001b98: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001b9c: d105 bne.n 8001baa encoderYChannelA = 0; 8001b9e: 4b09 ldr r3, [pc, #36] @ (8001bc4 ) 8001ba0: 2200 movs r2, #0 8001ba2: 601a str r2, [r3, #0] encoderYChannelB = 0; 8001ba4: 4b08 ldr r3, [pc, #32] @ (8001bc8 ) 8001ba6: 2200 movs r2, #0 8001ba8: 601a str r2, [r3, #0] } 8001baa: bf00 nop 8001bac: 3708 adds r7, #8 8001bae: 46bd mov sp, r7 8001bb0: bd80 pop {r7, pc} 8001bb2: bf00 nop 8001bb4: 40001000 .word 0x40001000 8001bb8: 40000800 .word 0x40000800 8001bbc: 24000754 .word 0x24000754 8001bc0: 24000758 .word 0x24000758 8001bc4: 2400075c .word 0x2400075c 8001bc8: 24000760 .word 0x24000760 08001bcc : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001bcc: b580 push {r7, lr} 8001bce: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 8001bd0: b672 cpsid i } 8001bd2: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); NVIC_SystemReset(); 8001bd4: f7fe fd58 bl 8000688 <__NVIC_SystemReset> 08001bd8 : extern TIM_OC_InitTypeDef motorXYTimerConfigOC; extern osTimerId_t motorXTimerHandle; extern osTimerId_t motorYTimerHandle; void MeasTasksInit (void) { 8001bd8: b590 push {r4, r7, lr} 8001bda: b0b5 sub sp, #212 @ 0xd4 8001bdc: af00 add r7, sp, #0 vRefmVMutex = osMutexNew (NULL); 8001bde: 2000 movs r0, #0 8001be0: f011 fe9d bl 801391e 8001be4: 4603 mov r3, r0 8001be6: 4a7e ldr r2, [pc, #504] @ (8001de0 ) 8001be8: 6013 str r3, [r2, #0] resMeasurementsMutex = osMutexNew (NULL); 8001bea: 2000 movs r0, #0 8001bec: f011 fe97 bl 801391e 8001bf0: 4603 mov r3, r0 8001bf2: 4a7c ldr r2, [pc, #496] @ (8001de4 ) 8001bf4: 6013 str r3, [r2, #0] sensorsInfoMutex = osMutexNew (NULL); 8001bf6: 2000 movs r0, #0 8001bf8: f011 fe91 bl 801391e 8001bfc: 4603 mov r3, r0 8001bfe: 4a7a ldr r2, [pc, #488] @ (8001de8 ) 8001c00: 6013 str r3, [r2, #0] ILxRefMutex = osMutexNew (NULL); 8001c02: 2000 movs r0, #0 8001c04: f011 fe8b bl 801391e 8001c08: 4603 mov r3, r0 8001c0a: 4a78 ldr r2, [pc, #480] @ (8001dec ) 8001c0c: 6013 str r3, [r2, #0] adc1MeasDataQueue = osMessageQueueNew (8, sizeof (ADC1_Data), NULL); 8001c0e: 2200 movs r2, #0 8001c10: 2120 movs r1, #32 8001c12: 2008 movs r0, #8 8001c14: f011 ff91 bl 8013b3a 8001c18: 4603 mov r3, r0 8001c1a: 4a75 ldr r2, [pc, #468] @ (8001df0 ) 8001c1c: 6013 str r3, [r2, #0] adc2MeasDataQueue = osMessageQueueNew (8, sizeof (ADC2_Data), NULL); 8001c1e: 2200 movs r2, #0 8001c20: 2120 movs r1, #32 8001c22: 2008 movs r0, #8 8001c24: f011 ff89 bl 8013b3a 8001c28: 4603 mov r3, r0 8001c2a: 4a72 ldr r2, [pc, #456] @ (8001df4 ) 8001c2c: 6013 str r3, [r2, #0] adc3MeasDataQueue = osMessageQueueNew (8, sizeof (ADC3_Data), NULL); 8001c2e: 2200 movs r2, #0 8001c30: 2120 movs r1, #32 8001c32: 2008 movs r0, #8 8001c34: f011 ff81 bl 8013b3a 8001c38: 4603 mov r3, r0 8001c3a: 4a6f ldr r2, [pc, #444] @ (8001df8 ) 8001c3c: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttradc1MeasTask = { 0 }; 8001c3e: f107 03ac add.w r3, r7, #172 @ 0xac 8001c42: 2224 movs r2, #36 @ 0x24 8001c44: 2100 movs r1, #0 8001c46: 4618 mov r0, r3 8001c48: f016 f820 bl 8017c8c osThreadAttr_t osThreadAttradc2MeasTask = { 0 }; 8001c4c: f107 0388 add.w r3, r7, #136 @ 0x88 8001c50: 2224 movs r2, #36 @ 0x24 8001c52: 2100 movs r1, #0 8001c54: 4618 mov r0, r3 8001c56: f016 f819 bl 8017c8c osThreadAttr_t osThreadAttradc3MeasTask = { 0 }; 8001c5a: f107 0364 add.w r3, r7, #100 @ 0x64 8001c5e: 2224 movs r2, #36 @ 0x24 8001c60: 2100 movs r1, #0 8001c62: 4618 mov r0, r3 8001c64: f016 f812 bl 8017c8c osThreadAttradc1MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001c68: f44f 6380 mov.w r3, #1024 @ 0x400 8001c6c: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 osThreadAttradc1MeasTask.priority = (osPriority_t)osPriorityRealtime; 8001c70: 2330 movs r3, #48 @ 0x30 8001c72: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 osThreadAttradc2MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001c76: f44f 6380 mov.w r3, #1024 @ 0x400 8001c7a: f8c7 309c str.w r3, [r7, #156] @ 0x9c osThreadAttradc2MeasTask.priority = (osPriority_t)osPriorityRealtime; 8001c7e: 2330 movs r3, #48 @ 0x30 8001c80: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 osThreadAttradc3MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001c84: f44f 6380 mov.w r3, #1024 @ 0x400 8001c88: 67bb str r3, [r7, #120] @ 0x78 osThreadAttradc3MeasTask.priority = (osPriority_t)osPriorityNormal; 8001c8a: 2318 movs r3, #24 8001c8c: 67fb str r3, [r7, #124] @ 0x7c adc1MeasTaskHandle = osThreadNew (ADC1MeasTask, NULL, &osThreadAttradc1MeasTask); 8001c8e: f107 03ac add.w r3, r7, #172 @ 0xac 8001c92: 461a mov r2, r3 8001c94: 2100 movs r1, #0 8001c96: 4859 ldr r0, [pc, #356] @ (8001dfc ) 8001c98: f011 fc9c bl 80135d4 8001c9c: 4603 mov r3, r0 8001c9e: 4a58 ldr r2, [pc, #352] @ (8001e00 ) 8001ca0: 6013 str r3, [r2, #0] adc2MeasTaskHandle = osThreadNew (ADC2MeasTask, NULL, &osThreadAttradc2MeasTask); 8001ca2: f107 0388 add.w r3, r7, #136 @ 0x88 8001ca6: 461a mov r2, r3 8001ca8: 2100 movs r1, #0 8001caa: 4856 ldr r0, [pc, #344] @ (8001e04 ) 8001cac: f011 fc92 bl 80135d4 8001cb0: 4603 mov r3, r0 8001cb2: 4a55 ldr r2, [pc, #340] @ (8001e08 ) 8001cb4: 6013 str r3, [r2, #0] adc3MeasTaskHandle = osThreadNew (ADC3MeasTask, NULL, &osThreadAttradc3MeasTask); 8001cb6: f107 0364 add.w r3, r7, #100 @ 0x64 8001cba: 461a mov r2, r3 8001cbc: 2100 movs r1, #0 8001cbe: 4853 ldr r0, [pc, #332] @ (8001e0c ) 8001cc0: f011 fc88 bl 80135d4 8001cc4: 4603 mov r3, r0 8001cc6: 4a52 ldr r2, [pc, #328] @ (8001e10 ) 8001cc8: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttradc1LimiterSwitchTask = { 0 }; 8001cca: f107 0340 add.w r3, r7, #64 @ 0x40 8001cce: 2224 movs r2, #36 @ 0x24 8001cd0: 2100 movs r1, #0 8001cd2: 4618 mov r0, r3 8001cd4: f015 ffda bl 8017c8c osThreadAttradc1LimiterSwitchTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001cd8: f44f 6380 mov.w r3, #1024 @ 0x400 8001cdc: 657b str r3, [r7, #84] @ 0x54 osThreadAttradc1LimiterSwitchTask.priority = (osPriority_t)osPriorityNormal; 8001cde: 2318 movs r3, #24 8001ce0: 65bb str r3, [r7, #88] @ 0x58 limiterSwitchTaskHandle = osThreadNew (LimiterSwitchTask, NULL, &osThreadAttradc1LimiterSwitchTask); 8001ce2: f107 0340 add.w r3, r7, #64 @ 0x40 8001ce6: 461a mov r2, r3 8001ce8: 2100 movs r1, #0 8001cea: 484a ldr r0, [pc, #296] @ (8001e14 ) 8001cec: f011 fc72 bl 80135d4 8001cf0: 4603 mov r3, r0 8001cf2: 4a49 ldr r2, [pc, #292] @ (8001e18 ) 8001cf4: 6013 str r3, [r2, #0] encoderXTaskArg.dbgLed = DBG_LED2; 8001cf6: 4b49 ldr r3, [pc, #292] @ (8001e1c ) 8001cf8: 2220 movs r2, #32 8001cfa: 801a strh r2, [r3, #0] encoderXTaskArg.pvEncoder = &(sensorsInfo.pvEncoderX); 8001cfc: 4b47 ldr r3, [pc, #284] @ (8001e1c ) 8001cfe: 4a48 ldr r2, [pc, #288] @ (8001e20 ) 8001d00: 609a str r2, [r3, #8] encoderXTaskArg.currentPosition = &(sensorsInfo.currentXPosition); 8001d02: 4b46 ldr r3, [pc, #280] @ (8001e1c ) 8001d04: 4a47 ldr r2, [pc, #284] @ (8001e24 ) 8001d06: 605a str r2, [r3, #4] osMessageQueueAttr_t encoderMsgQueueAttr = { 0 }; 8001d08: f107 0328 add.w r3, r7, #40 @ 0x28 8001d0c: 2200 movs r2, #0 8001d0e: 601a str r2, [r3, #0] 8001d10: 605a str r2, [r3, #4] 8001d12: 609a str r2, [r3, #8] 8001d14: 60da str r2, [r3, #12] 8001d16: 611a str r2, [r3, #16] 8001d18: 615a str r2, [r3, #20] encoderXTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr); 8001d1a: f107 0328 add.w r3, r7, #40 @ 0x28 8001d1e: 461a mov r2, r3 8001d20: 2104 movs r1, #4 8001d22: 2010 movs r0, #16 8001d24: f011 ff09 bl 8013b3a 8001d28: 4603 mov r3, r0 8001d2a: 4a3c ldr r2, [pc, #240] @ (8001e1c ) 8001d2c: 6113 str r3, [r2, #16] encoderXTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3; 8001d2e: f44f 4100 mov.w r1, #32768 @ 0x8000 8001d32: 483d ldr r0, [pc, #244] @ (8001e28 ) 8001d34: f009 fac4 bl 800b2c0 8001d38: 4603 mov r3, r0 8001d3a: 005c lsls r4, r3, #1 8001d3c: f44f 4180 mov.w r1, #16384 @ 0x4000 8001d40: 4839 ldr r0, [pc, #228] @ (8001e28 ) 8001d42: f009 fabd bl 800b2c0 8001d46: 4603 mov r3, r0 8001d48: 4323 orrs r3, r4 8001d4a: f003 0303 and.w r3, r3, #3 8001d4e: 4a33 ldr r2, [pc, #204] @ (8001e1c ) 8001d50: 60d3 str r3, [r2, #12] encoderYTaskArg.dbgLed = DBG_LED3; 8001d52: 4b36 ldr r3, [pc, #216] @ (8001e2c ) 8001d54: 2240 movs r2, #64 @ 0x40 8001d56: 801a strh r2, [r3, #0] encoderYTaskArg.pvEncoder = &(sensorsInfo.pvEncoderY); 8001d58: 4b34 ldr r3, [pc, #208] @ (8001e2c ) 8001d5a: 4a35 ldr r2, [pc, #212] @ (8001e30 ) 8001d5c: 609a str r2, [r3, #8] encoderYTaskArg.currentPosition = &(sensorsInfo.currentYPosition); 8001d5e: 4b33 ldr r3, [pc, #204] @ (8001e2c ) 8001d60: 4a34 ldr r2, [pc, #208] @ (8001e34 ) 8001d62: 605a str r2, [r3, #4] encoderYTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr); 8001d64: f107 0328 add.w r3, r7, #40 @ 0x28 8001d68: 461a mov r2, r3 8001d6a: 2104 movs r1, #4 8001d6c: 2010 movs r0, #16 8001d6e: f011 fee4 bl 8013b3a 8001d72: 4603 mov r3, r0 8001d74: 4a2d ldr r2, [pc, #180] @ (8001e2c ) 8001d76: 6113 str r3, [r2, #16] encoderYTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3; 8001d78: f44f 6100 mov.w r1, #2048 @ 0x800 8001d7c: 482e ldr r0, [pc, #184] @ (8001e38 ) 8001d7e: f009 fa9f bl 800b2c0 8001d82: 4603 mov r3, r0 8001d84: 005c lsls r4, r3, #1 8001d86: f44f 6180 mov.w r1, #1024 @ 0x400 8001d8a: 482b ldr r0, [pc, #172] @ (8001e38 ) 8001d8c: f009 fa98 bl 800b2c0 8001d90: 4603 mov r3, r0 8001d92: 4323 orrs r3, r4 8001d94: f003 0303 and.w r3, r3, #3 8001d98: 4a24 ldr r2, [pc, #144] @ (8001e2c ) 8001d9a: 60d3 str r3, [r2, #12] osThreadAttr_t osThreadAttrEncoderTask = { 0 }; 8001d9c: 1d3b adds r3, r7, #4 8001d9e: 2224 movs r2, #36 @ 0x24 8001da0: 2100 movs r1, #0 8001da2: 4618 mov r0, r3 8001da4: f015 ff72 bl 8017c8c osThreadAttrEncoderTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001da8: f44f 6380 mov.w r3, #1024 @ 0x400 8001dac: 61bb str r3, [r7, #24] osThreadAttrEncoderTask.priority = (osPriority_t)osPriorityRealtime; 8001dae: 2330 movs r3, #48 @ 0x30 8001db0: 61fb str r3, [r7, #28] encoderXTaskHandle = osThreadNew (EncoderTask, &encoderXTaskArg, &osThreadAttrEncoderTask); 8001db2: 1d3b adds r3, r7, #4 8001db4: 461a mov r2, r3 8001db6: 4919 ldr r1, [pc, #100] @ (8001e1c ) 8001db8: 4820 ldr r0, [pc, #128] @ (8001e3c ) 8001dba: f011 fc0b bl 80135d4 8001dbe: 4603 mov r3, r0 8001dc0: 4a1f ldr r2, [pc, #124] @ (8001e40 ) 8001dc2: 6013 str r3, [r2, #0] encoderYTaskHandle = osThreadNew (EncoderTask, &encoderYTaskArg, &osThreadAttrEncoderTask); 8001dc4: 1d3b adds r3, r7, #4 8001dc6: 461a mov r2, r3 8001dc8: 4918 ldr r1, [pc, #96] @ (8001e2c ) 8001dca: 481c ldr r0, [pc, #112] @ (8001e3c ) 8001dcc: f011 fc02 bl 80135d4 8001dd0: 4603 mov r3, r0 8001dd2: 4a1c ldr r2, [pc, #112] @ (8001e44 ) 8001dd4: 6013 str r3, [r2, #0] } 8001dd6: bf00 nop 8001dd8: 37d4 adds r7, #212 @ 0xd4 8001dda: 46bd mov sp, r7 8001ddc: bd90 pop {r4, r7, pc} 8001dde: bf00 nop 8001de0: 24000788 .word 0x24000788 8001de4: 2400078c .word 0x2400078c 8001de8: 24000790 .word 0x24000790 8001dec: 24000794 .word 0x24000794 8001df0: 2400077c .word 0x2400077c 8001df4: 24000780 .word 0x24000780 8001df8: 24000784 .word 0x24000784 8001dfc: 08001e49 .word 0x08001e49 8001e00: 24000764 .word 0x24000764 8001e04: 080021d1 .word 0x080021d1 8001e08: 24000768 .word 0x24000768 8001e0c: 080024d9 .word 0x080024d9 8001e10: 2400076c .word 0x2400076c 8001e14: 08002855 .word 0x08002855 8001e18: 24000770 .word 0x24000770 8001e1c: 24000840 .word 0x24000840 8001e20: 240007ec .word 0x240007ec 8001e24: 24000810 .word 0x24000810 8001e28: 58020c00 .word 0x58020c00 8001e2c: 24000860 .word 0x24000860 8001e30: 240007f0 .word 0x240007f0 8001e34: 24000814 .word 0x24000814 8001e38: 58020400 .word 0x58020400 8001e3c: 08002b61 .word 0x08002b61 8001e40: 24000774 .word 0x24000774 8001e44: 24000778 .word 0x24000778 08001e48 : void ADC1MeasTask (void* arg) { 8001e48: b580 push {r7, lr} 8001e4a: b09a sub sp, #104 @ 0x68 8001e4c: af00 add r7, sp, #0 8001e4e: 6078 str r0, [r7, #4] float circBuffer[VOLTAGES_COUNT][CIRC_BUFF_LEN] = { 0 }; 8001e50: f107 032c add.w r3, r7, #44 @ 0x2c 8001e54: 2228 movs r2, #40 @ 0x28 8001e56: 2100 movs r1, #0 8001e58: 4618 mov r0, r3 8001e5a: f015 ff17 bl 8017c8c float rms[VOLTAGES_COUNT] = { 0 }; 8001e5e: f04f 0300 mov.w r3, #0 8001e62: 62bb str r3, [r7, #40] @ 0x28 ; ADC1_Data adcData = { 0 }; 8001e64: f107 0308 add.w r3, r7, #8 8001e68: 2220 movs r2, #32 8001e6a: 2100 movs r1, #0 8001e6c: 4618 mov r0, r3 8001e6e: f015 ff0d bl 8017c8c uint32_t circBuffPos = 0; 8001e72: 2300 movs r3, #0 8001e74: 667b str r3, [r7, #100] @ 0x64 float gainCorrection = 1.0; 8001e76: f04f 537e mov.w r3, #1065353216 @ 0x3f800000 8001e7a: 663b str r3, [r7, #96] @ 0x60 while (pdTRUE) { osMessageQueueGet (adc1MeasDataQueue, &adcData, 0, osWaitForever); 8001e7c: 4bc8 ldr r3, [pc, #800] @ (80021a0 ) 8001e7e: 6818 ldr r0, [r3, #0] 8001e80: f107 0108 add.w r1, r7, #8 8001e84: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8001e88: 2200 movs r2, #0 8001e8a: f011 ff29 bl 8013ce0 #ifdef GAIN_AUTO_CORRECTION if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 8001e8e: 4bc5 ldr r3, [pc, #788] @ (80021a4 ) 8001e90: 681b ldr r3, [r3, #0] 8001e92: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001e96: 4618 mov r0, r3 8001e98: f011 fdc7 bl 8013a2a 8001e9c: 4603 mov r3, r0 8001e9e: 2b00 cmp r3, #0 8001ea0: d10c bne.n 8001ebc gainCorrection = (float)vRefmV; 8001ea2: 4bc1 ldr r3, [pc, #772] @ (80021a8 ) 8001ea4: 681b ldr r3, [r3, #0] 8001ea6: ee07 3a90 vmov s15, r3 8001eaa: eef8 7a67 vcvt.f32.u32 s15, s15 8001eae: edc7 7a18 vstr s15, [r7, #96] @ 0x60 osMutexRelease (vRefmVMutex); 8001eb2: 4bbc ldr r3, [pc, #752] @ (80021a4 ) 8001eb4: 681b ldr r3, [r3, #0] 8001eb6: 4618 mov r0, r3 8001eb8: f011 fe02 bl 8013ac0 } gainCorrection = gainCorrection / EXT_VREF_mV; 8001ebc: ed97 7a18 vldr s14, [r7, #96] @ 0x60 8001ec0: eddf 6aba vldr s13, [pc, #744] @ 80021ac 8001ec4: eec7 7a26 vdiv.f32 s15, s14, s13 8001ec8: edc7 7a18 vstr s15, [r7, #96] @ 0x60 #endif for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) { 8001ecc: 2300 movs r3, #0 8001ece: f887 305f strb.w r3, [r7, #95] @ 0x5f 8001ed2: e0e7 b.n 80020a4 float val = adcData.adcDataBuffer[i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 8001ed4: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001ed8: 005b lsls r3, r3, #1 8001eda: 3368 adds r3, #104 @ 0x68 8001edc: 443b add r3, r7 8001ede: f833 3c60 ldrh.w r3, [r3, #-96] 8001ee2: ee07 3a90 vmov s15, r3 8001ee6: eeb8 7be7 vcvt.f64.s32 d7, s15 8001eea: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8001eee: ee27 6b06 vmul.f64 d6, d7, d6 8001ef2: ed9f 5ba5 vldr d5, [pc, #660] @ 8002188 8001ef6: ee86 7b05 vdiv.f64 d7, d6, d5 8001efa: ed9f 6ba5 vldr d6, [pc, #660] @ 8002190 8001efe: ee27 6b06 vmul.f64 d6, d7, d6 8001f02: edd7 7a18 vldr s15, [r7, #96] @ 0x60 8001f06: eeb7 7ae7 vcvt.f64.f32 d7, s15 8001f0a: ee26 6b07 vmul.f64 d6, d6, d7 8001f0e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001f12: 4aa7 ldr r2, [pc, #668] @ (80021b0 ) 8001f14: 00db lsls r3, r3, #3 8001f16: 4413 add r3, r2 8001f18: edd3 7a00 vldr s15, [r3] 8001f1c: eeb7 7ae7 vcvt.f64.f32 d7, s15 8001f20: ee26 6b07 vmul.f64 d6, d6, d7 8001f24: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001f28: 4aa1 ldr r2, [pc, #644] @ (80021b0 ) 8001f2a: 00db lsls r3, r3, #3 8001f2c: 4413 add r3, r2 8001f2e: 3304 adds r3, #4 8001f30: edd3 7a00 vldr s15, [r3] 8001f34: eeb7 7ae7 vcvt.f64.f32 d7, s15 8001f38: ee36 7b07 vadd.f64 d7, d6, d7 8001f3c: eef7 7bc7 vcvt.f32.f64 s15, d7 8001f40: edc7 7a15 vstr s15, [r7, #84] @ 0x54 circBuffer[i][circBuffPos] = val; 8001f44: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 8001f48: 4613 mov r3, r2 8001f4a: 009b lsls r3, r3, #2 8001f4c: 4413 add r3, r2 8001f4e: 005b lsls r3, r3, #1 8001f50: 6e7a ldr r2, [r7, #100] @ 0x64 8001f52: 4413 add r3, r2 8001f54: 009b lsls r3, r3, #2 8001f56: 3368 adds r3, #104 @ 0x68 8001f58: 443b add r3, r7 8001f5a: 3b3c subs r3, #60 @ 0x3c 8001f5c: 6d7a ldr r2, [r7, #84] @ 0x54 8001f5e: 601a str r2, [r3, #0] rms[i] = 0.0; 8001f60: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001f64: 009b lsls r3, r3, #2 8001f66: 3368 adds r3, #104 @ 0x68 8001f68: 443b add r3, r7 8001f6a: 3b40 subs r3, #64 @ 0x40 8001f6c: f04f 0200 mov.w r2, #0 8001f70: 601a str r2, [r3, #0] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 8001f72: 2300 movs r3, #0 8001f74: f887 305e strb.w r3, [r7, #94] @ 0x5e 8001f78: e025 b.n 8001fc6 rms[i] += circBuffer[i][c]; 8001f7a: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001f7e: 009b lsls r3, r3, #2 8001f80: 3368 adds r3, #104 @ 0x68 8001f82: 443b add r3, r7 8001f84: 3b40 subs r3, #64 @ 0x40 8001f86: ed93 7a00 vldr s14, [r3] 8001f8a: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 8001f8e: f897 105e ldrb.w r1, [r7, #94] @ 0x5e 8001f92: 4613 mov r3, r2 8001f94: 009b lsls r3, r3, #2 8001f96: 4413 add r3, r2 8001f98: 005b lsls r3, r3, #1 8001f9a: 440b add r3, r1 8001f9c: 009b lsls r3, r3, #2 8001f9e: 3368 adds r3, #104 @ 0x68 8001fa0: 443b add r3, r7 8001fa2: 3b3c subs r3, #60 @ 0x3c 8001fa4: edd3 7a00 vldr s15, [r3] 8001fa8: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001fac: ee77 7a27 vadd.f32 s15, s14, s15 8001fb0: 009b lsls r3, r3, #2 8001fb2: 3368 adds r3, #104 @ 0x68 8001fb4: 443b add r3, r7 8001fb6: 3b40 subs r3, #64 @ 0x40 8001fb8: edc3 7a00 vstr s15, [r3] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 8001fbc: f897 305e ldrb.w r3, [r7, #94] @ 0x5e 8001fc0: 3301 adds r3, #1 8001fc2: f887 305e strb.w r3, [r7, #94] @ 0x5e 8001fc6: f897 305e ldrb.w r3, [r7, #94] @ 0x5e 8001fca: 2b09 cmp r3, #9 8001fcc: d9d5 bls.n 8001f7a } rms[i] = rms[i] / CIRC_BUFF_LEN; 8001fce: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001fd2: 009b lsls r3, r3, #2 8001fd4: 3368 adds r3, #104 @ 0x68 8001fd6: 443b add r3, r7 8001fd8: 3b40 subs r3, #64 @ 0x40 8001fda: ed93 7a00 vldr s14, [r3] 8001fde: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001fe2: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8001fe6: eec7 7a26 vdiv.f32 s15, s14, s13 8001fea: 009b lsls r3, r3, #2 8001fec: 3368 adds r3, #104 @ 0x68 8001fee: 443b add r3, r7 8001ff0: 3b40 subs r3, #64 @ 0x40 8001ff2: edc3 7a00 vstr s15, [r3] if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8001ff6: 4b6f ldr r3, [pc, #444] @ (80021b4 ) 8001ff8: 681b ldr r3, [r3, #0] 8001ffa: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001ffe: 4618 mov r0, r3 8002000: f011 fd13 bl 8013a2a 8002004: 4603 mov r3, r0 8002006: 2b00 cmp r3, #0 8002008: d147 bne.n 800209a if (fabs (resMeasurements.voltagePeak[i]) < fabs (val)) { 800200a: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800200e: 4a6a ldr r2, [pc, #424] @ (80021b8 ) 8002010: 3302 adds r3, #2 8002012: 009b lsls r3, r3, #2 8002014: 4413 add r3, r2 8002016: 3304 adds r3, #4 8002018: edd3 7a00 vldr s15, [r3] 800201c: eeb0 7ae7 vabs.f32 s14, s15 8002020: edd7 7a15 vldr s15, [r7, #84] @ 0x54 8002024: eef0 7ae7 vabs.f32 s15, s15 8002028: eeb4 7ae7 vcmpe.f32 s14, s15 800202c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002030: d508 bpl.n 8002044 resMeasurements.voltagePeak[i] = val; 8002032: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002036: 4a60 ldr r2, [pc, #384] @ (80021b8 ) 8002038: 3302 adds r3, #2 800203a: 009b lsls r3, r3, #2 800203c: 4413 add r3, r2 800203e: 3304 adds r3, #4 8002040: 6d7a ldr r2, [r7, #84] @ 0x54 8002042: 601a str r2, [r3, #0] } resMeasurements.voltageRMS[i] = rms[i]; 8002044: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 8002048: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800204c: 0092 lsls r2, r2, #2 800204e: 3268 adds r2, #104 @ 0x68 8002050: 443a add r2, r7 8002052: 3a40 subs r2, #64 @ 0x40 8002054: 6812 ldr r2, [r2, #0] 8002056: 4958 ldr r1, [pc, #352] @ (80021b8 ) 8002058: 009b lsls r3, r3, #2 800205a: 440b add r3, r1 800205c: 601a str r2, [r3, #0] resMeasurements.power[i] = resMeasurements.voltageRMS[i] * resMeasurements.currentRMS[i]; 800205e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002062: 4a55 ldr r2, [pc, #340] @ (80021b8 ) 8002064: 009b lsls r3, r3, #2 8002066: 4413 add r3, r2 8002068: ed93 7a00 vldr s14, [r3] 800206c: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002070: 4a51 ldr r2, [pc, #324] @ (80021b8 ) 8002072: 3306 adds r3, #6 8002074: 009b lsls r3, r3, #2 8002076: 4413 add r3, r2 8002078: edd3 7a00 vldr s15, [r3] 800207c: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002080: ee67 7a27 vmul.f32 s15, s14, s15 8002084: 4a4c ldr r2, [pc, #304] @ (80021b8 ) 8002086: 330c adds r3, #12 8002088: 009b lsls r3, r3, #2 800208a: 4413 add r3, r2 800208c: edc3 7a00 vstr s15, [r3] osMutexRelease (resMeasurementsMutex); 8002090: 4b48 ldr r3, [pc, #288] @ (80021b4 ) 8002092: 681b ldr r3, [r3, #0] 8002094: 4618 mov r0, r3 8002096: f011 fd13 bl 8013ac0 for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) { 800209a: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800209e: 3301 adds r3, #1 80020a0: f887 305f strb.w r3, [r7, #95] @ 0x5f 80020a4: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80020a8: 2b00 cmp r3, #0 80020aa: f43f af13 beq.w 8001ed4 } } ++circBuffPos; 80020ae: 6e7b ldr r3, [r7, #100] @ 0x64 80020b0: 3301 adds r3, #1 80020b2: 667b str r3, [r7, #100] @ 0x64 circBuffPos = circBuffPos % CIRC_BUFF_LEN; 80020b4: 6e7a ldr r2, [r7, #100] @ 0x64 80020b6: 4b41 ldr r3, [pc, #260] @ (80021bc ) 80020b8: fba3 1302 umull r1, r3, r3, r2 80020bc: 08d9 lsrs r1, r3, #3 80020be: 460b mov r3, r1 80020c0: 009b lsls r3, r3, #2 80020c2: 440b add r3, r1 80020c4: 005b lsls r3, r3, #1 80020c6: 1ad3 subs r3, r2, r3 80020c8: 667b str r3, [r7, #100] @ 0x64 if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) { 80020ca: 4b3d ldr r3, [pc, #244] @ (80021c0 ) 80020cc: 681b ldr r3, [r3, #0] 80020ce: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80020d2: 4618 mov r0, r3 80020d4: f011 fca9 bl 8013a2a 80020d8: 4603 mov r3, r0 80020da: 2b00 cmp r3, #0 80020dc: d124 bne.n 8002128 uint8_t refIdx = 0; 80020de: 2300 movs r3, #0 80020e0: f887 305d strb.w r3, [r7, #93] @ 0x5d for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) { 80020e4: 2303 movs r3, #3 80020e6: f887 305c strb.w r3, [r7, #92] @ 0x5c 80020ea: e014 b.n 8002116 ILxRef[refIdx++] = adcData.adcDataBuffer[i]; 80020ec: f897 205c ldrb.w r2, [r7, #92] @ 0x5c 80020f0: f897 305d ldrb.w r3, [r7, #93] @ 0x5d 80020f4: 1c59 adds r1, r3, #1 80020f6: f887 105d strb.w r1, [r7, #93] @ 0x5d 80020fa: 4619 mov r1, r3 80020fc: 0053 lsls r3, r2, #1 80020fe: 3368 adds r3, #104 @ 0x68 8002100: 443b add r3, r7 8002102: f833 2c60 ldrh.w r2, [r3, #-96] 8002106: 4b2f ldr r3, [pc, #188] @ (80021c4 ) 8002108: f823 2011 strh.w r2, [r3, r1, lsl #1] for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) { 800210c: f897 305c ldrb.w r3, [r7, #92] @ 0x5c 8002110: 3301 adds r3, #1 8002112: f887 305c strb.w r3, [r7, #92] @ 0x5c 8002116: f897 305c ldrb.w r3, [r7, #92] @ 0x5c 800211a: 2b05 cmp r3, #5 800211c: d9e6 bls.n 80020ec } osMutexRelease (ILxRefMutex); 800211e: 4b28 ldr r3, [pc, #160] @ (80021c0 ) 8002120: 681b ldr r3, [r3, #0] 8002122: 4618 mov r0, r3 8002124: f011 fccc bl 8013ac0 } float fanFBVoltage = adcData.adcDataBuffer[FanFB] * deltaADC * -4.35 + 12; 8002128: 8abb ldrh r3, [r7, #20] 800212a: ee07 3a90 vmov s15, r3 800212e: eeb8 7be7 vcvt.f64.s32 d7, s15 8002132: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002136: ee27 6b06 vmul.f64 d6, d7, d6 800213a: ed9f 5b13 vldr d5, [pc, #76] @ 8002188 800213e: ee86 7b05 vdiv.f64 d7, d6, d5 8002142: ed9f 6b15 vldr d6, [pc, #84] @ 8002198 8002146: ee27 7b06 vmul.f64 d7, d7, d6 800214a: eeb2 6b08 vmov.f64 d6, #40 @ 0x41400000 12.0 800214e: ee37 7b06 vadd.f64 d7, d7, d6 8002152: eef7 7bc7 vcvt.f32.f64 s15, d7 8002156: edc7 7a16 vstr s15, [r7, #88] @ 0x58 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800215a: 4b1b ldr r3, [pc, #108] @ (80021c8 ) 800215c: 681b ldr r3, [r3, #0] 800215e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002162: 4618 mov r0, r3 8002164: f011 fc61 bl 8013a2a 8002168: 4603 mov r3, r0 800216a: 2b00 cmp r3, #0 800216c: f47f ae86 bne.w 8001e7c sensorsInfo.fanVoltage = fanFBVoltage; 8002170: 4a16 ldr r2, [pc, #88] @ (80021cc ) 8002172: 6dbb ldr r3, [r7, #88] @ 0x58 8002174: 6093 str r3, [r2, #8] osMutexRelease (sensorsInfoMutex); 8002176: 4b14 ldr r3, [pc, #80] @ (80021c8 ) 8002178: 681b ldr r3, [r3, #0] 800217a: 4618 mov r0, r3 800217c: f011 fca0 bl 8013ac0 while (pdTRUE) { 8002180: e67c b.n 8001e7c 8002182: bf00 nop 8002184: f3af 8000 nop.w 8002188: 00000000 .word 0x00000000 800218c: 40efffe0 .word 0x40efffe0 8002190: f5c28f5c .word 0xf5c28f5c 8002194: 401e5c28 .word 0x401e5c28 8002198: 66666666 .word 0x66666666 800219c: c0116666 .word 0xc0116666 80021a0: 2400077c .word 0x2400077c 80021a4: 24000788 .word 0x24000788 80021a8: 24000030 .word 0x24000030 80021ac: 453b8000 .word 0x453b8000 80021b0: 24000000 .word 0x24000000 80021b4: 2400078c .word 0x2400078c 80021b8: 240007a0 .word 0x240007a0 80021bc: cccccccd .word 0xcccccccd 80021c0: 24000794 .word 0x24000794 80021c4: 24000820 .word 0x24000820 80021c8: 24000790 .word 0x24000790 80021cc: 240007e0 .word 0x240007e0 080021d0 : } } } void ADC2MeasTask (void* arg) { 80021d0: b580 push {r7, lr} 80021d2: b09c sub sp, #112 @ 0x70 80021d4: af00 add r7, sp, #0 80021d6: 6078 str r0, [r7, #4] float circBuffer[CURRENTS_COUNT][CIRC_BUFF_LEN] = { 0 }; 80021d8: f107 0334 add.w r3, r7, #52 @ 0x34 80021dc: 2228 movs r2, #40 @ 0x28 80021de: 2100 movs r1, #0 80021e0: 4618 mov r0, r3 80021e2: f015 fd53 bl 8017c8c float rms[CURRENTS_COUNT] = { 0 }; 80021e6: f04f 0300 mov.w r3, #0 80021ea: 633b str r3, [r7, #48] @ 0x30 ADC2_Data adcData = { 0 }; 80021ec: f107 0310 add.w r3, r7, #16 80021f0: 2220 movs r2, #32 80021f2: 2100 movs r1, #0 80021f4: 4618 mov r0, r3 80021f6: f015 fd49 bl 8017c8c uint32_t circBuffPos = 0; 80021fa: 2300 movs r3, #0 80021fc: 66fb str r3, [r7, #108] @ 0x6c float gainCorrection = 1.0; 80021fe: f04f 537e mov.w r3, #1065353216 @ 0x3f800000 8002202: 66bb str r3, [r7, #104] @ 0x68 while (pdTRUE) { osMessageQueueGet (adc2MeasDataQueue, &adcData, 0, osWaitForever); 8002204: 4baa ldr r3, [pc, #680] @ (80024b0 ) 8002206: 6818 ldr r0, [r3, #0] 8002208: f107 0110 add.w r1, r7, #16 800220c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002210: 2200 movs r2, #0 8002212: f011 fd65 bl 8013ce0 if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 8002216: 4ba7 ldr r3, [pc, #668] @ (80024b4 ) 8002218: 681b ldr r3, [r3, #0] 800221a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800221e: 4618 mov r0, r3 8002220: f011 fc03 bl 8013a2a 8002224: 4603 mov r3, r0 8002226: 2b00 cmp r3, #0 8002228: d10c bne.n 8002244 gainCorrection = (float)vRefmV; 800222a: 4ba3 ldr r3, [pc, #652] @ (80024b8 ) 800222c: 681b ldr r3, [r3, #0] 800222e: ee07 3a90 vmov s15, r3 8002232: eef8 7a67 vcvt.f32.u32 s15, s15 8002236: edc7 7a1a vstr s15, [r7, #104] @ 0x68 osMutexRelease (vRefmVMutex); 800223a: 4b9e ldr r3, [pc, #632] @ (80024b4 ) 800223c: 681b ldr r3, [r3, #0] 800223e: 4618 mov r0, r3 8002240: f011 fc3e bl 8013ac0 } gainCorrection = gainCorrection / EXT_VREF_mV; 8002244: ed97 7a1a vldr s14, [r7, #104] @ 0x68 8002248: eddf 6a9c vldr s13, [pc, #624] @ 80024bc 800224c: eec7 7a26 vdiv.f32 s15, s14, s13 8002250: edc7 7a1a vstr s15, [r7, #104] @ 0x68 float ref[CURRENTS_COUNT] = { 0 }; 8002254: f04f 0300 mov.w r3, #0 8002258: 60fb str r3, [r7, #12] if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) { 800225a: 4b99 ldr r3, [pc, #612] @ (80024c0 ) 800225c: 681b ldr r3, [r3, #0] 800225e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002262: 4618 mov r0, r3 8002264: f011 fbe1 bl 8013a2a 8002268: 4603 mov r3, r0 800226a: 2b00 cmp r3, #0 800226c: d122 bne.n 80022b4 for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 800226e: 2300 movs r3, #0 8002270: f887 3067 strb.w r3, [r7, #103] @ 0x67 8002274: e015 b.n 80022a2 ref[i] = (float)ILxRef[i]; 8002276: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 800227a: 4a92 ldr r2, [pc, #584] @ (80024c4 ) 800227c: f832 2013 ldrh.w r2, [r2, r3, lsl #1] 8002280: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 8002284: ee07 2a90 vmov s15, r2 8002288: eef8 7a67 vcvt.f32.u32 s15, s15 800228c: 009b lsls r3, r3, #2 800228e: 3370 adds r3, #112 @ 0x70 8002290: 443b add r3, r7 8002292: 3b64 subs r3, #100 @ 0x64 8002294: edc3 7a00 vstr s15, [r3] for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 8002298: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 800229c: 3301 adds r3, #1 800229e: f887 3067 strb.w r3, [r7, #103] @ 0x67 80022a2: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80022a6: 2b00 cmp r3, #0 80022a8: d0e5 beq.n 8002276 } osMutexRelease (ILxRefMutex); 80022aa: 4b85 ldr r3, [pc, #532] @ (80024c0 ) 80022ac: 681b ldr r3, [r3, #0] 80022ae: 4618 mov r0, r3 80022b0: f011 fc06 bl 8013ac0 } for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 80022b4: 2300 movs r3, #0 80022b6: f887 3066 strb.w r3, [r7, #102] @ 0x66 80022ba: e0db b.n 8002474 float adcVal = (float)adcData.adcDataBuffer[i]; 80022bc: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80022c0: 005b lsls r3, r3, #1 80022c2: 3370 adds r3, #112 @ 0x70 80022c4: 443b add r3, r7 80022c6: f833 3c60 ldrh.w r3, [r3, #-96] 80022ca: ee07 3a90 vmov s15, r3 80022ce: eef8 7a67 vcvt.f32.u32 s15, s15 80022d2: edc7 7a18 vstr s15, [r7, #96] @ 0x60 float val = (adcVal - ref[i]) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset; 80022d6: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80022da: 009b lsls r3, r3, #2 80022dc: 3370 adds r3, #112 @ 0x70 80022de: 443b add r3, r7 80022e0: 3b64 subs r3, #100 @ 0x64 80022e2: edd3 7a00 vldr s15, [r3] 80022e6: ed97 7a18 vldr s14, [r7, #96] @ 0x60 80022ea: ee77 7a67 vsub.f32 s15, s14, s15 80022ee: eeb7 7ae7 vcvt.f64.f32 d7, s15 80022f2: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80022f6: ee27 6b06 vmul.f64 d6, d7, d6 80022fa: ed9f 5b69 vldr d5, [pc, #420] @ 80024a0 80022fe: ee86 7b05 vdiv.f64 d7, d6, d5 8002302: ed9f 6b69 vldr d6, [pc, #420] @ 80024a8 8002306: ee27 6b06 vmul.f64 d6, d7, d6 800230a: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800230e: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002312: ee26 6b07 vmul.f64 d6, d6, d7 8002316: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800231a: 4a6b ldr r2, [pc, #428] @ (80024c8 ) 800231c: 00db lsls r3, r3, #3 800231e: 4413 add r3, r2 8002320: edd3 7a00 vldr s15, [r3] 8002324: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002328: ee26 6b07 vmul.f64 d6, d6, d7 800232c: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002330: 4a65 ldr r2, [pc, #404] @ (80024c8 ) 8002332: 00db lsls r3, r3, #3 8002334: 4413 add r3, r2 8002336: 3304 adds r3, #4 8002338: edd3 7a00 vldr s15, [r3] 800233c: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002340: ee36 7b07 vadd.f64 d7, d6, d7 8002344: eef7 7bc7 vcvt.f32.f64 s15, d7 8002348: edc7 7a17 vstr s15, [r7, #92] @ 0x5c circBuffer[i][circBuffPos] = val; 800234c: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 8002350: 4613 mov r3, r2 8002352: 009b lsls r3, r3, #2 8002354: 4413 add r3, r2 8002356: 005b lsls r3, r3, #1 8002358: 6efa ldr r2, [r7, #108] @ 0x6c 800235a: 4413 add r3, r2 800235c: 009b lsls r3, r3, #2 800235e: 3370 adds r3, #112 @ 0x70 8002360: 443b add r3, r7 8002362: 3b3c subs r3, #60 @ 0x3c 8002364: 6dfa ldr r2, [r7, #92] @ 0x5c 8002366: 601a str r2, [r3, #0] rms[i] = 0.0; 8002368: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800236c: 009b lsls r3, r3, #2 800236e: 3370 adds r3, #112 @ 0x70 8002370: 443b add r3, r7 8002372: 3b40 subs r3, #64 @ 0x40 8002374: f04f 0200 mov.w r2, #0 8002378: 601a str r2, [r3, #0] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 800237a: 2300 movs r3, #0 800237c: f887 3065 strb.w r3, [r7, #101] @ 0x65 8002380: e025 b.n 80023ce rms[i] += circBuffer[i][c]; 8002382: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002386: 009b lsls r3, r3, #2 8002388: 3370 adds r3, #112 @ 0x70 800238a: 443b add r3, r7 800238c: 3b40 subs r3, #64 @ 0x40 800238e: ed93 7a00 vldr s14, [r3] 8002392: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 8002396: f897 1065 ldrb.w r1, [r7, #101] @ 0x65 800239a: 4613 mov r3, r2 800239c: 009b lsls r3, r3, #2 800239e: 4413 add r3, r2 80023a0: 005b lsls r3, r3, #1 80023a2: 440b add r3, r1 80023a4: 009b lsls r3, r3, #2 80023a6: 3370 adds r3, #112 @ 0x70 80023a8: 443b add r3, r7 80023aa: 3b3c subs r3, #60 @ 0x3c 80023ac: edd3 7a00 vldr s15, [r3] 80023b0: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80023b4: ee77 7a27 vadd.f32 s15, s14, s15 80023b8: 009b lsls r3, r3, #2 80023ba: 3370 adds r3, #112 @ 0x70 80023bc: 443b add r3, r7 80023be: 3b40 subs r3, #64 @ 0x40 80023c0: edc3 7a00 vstr s15, [r3] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 80023c4: f897 3065 ldrb.w r3, [r7, #101] @ 0x65 80023c8: 3301 adds r3, #1 80023ca: f887 3065 strb.w r3, [r7, #101] @ 0x65 80023ce: f897 3065 ldrb.w r3, [r7, #101] @ 0x65 80023d2: 2b09 cmp r3, #9 80023d4: d9d5 bls.n 8002382 } rms[i] = rms[i] / CIRC_BUFF_LEN; 80023d6: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80023da: 009b lsls r3, r3, #2 80023dc: 3370 adds r3, #112 @ 0x70 80023de: 443b add r3, r7 80023e0: 3b40 subs r3, #64 @ 0x40 80023e2: ed93 7a00 vldr s14, [r3] 80023e6: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80023ea: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 80023ee: eec7 7a26 vdiv.f32 s15, s14, s13 80023f2: 009b lsls r3, r3, #2 80023f4: 3370 adds r3, #112 @ 0x70 80023f6: 443b add r3, r7 80023f8: 3b40 subs r3, #64 @ 0x40 80023fa: edc3 7a00 vstr s15, [r3] if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 80023fe: 4b33 ldr r3, [pc, #204] @ (80024cc ) 8002400: 681b ldr r3, [r3, #0] 8002402: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002406: 4618 mov r0, r3 8002408: f011 fb0f bl 8013a2a 800240c: 4603 mov r3, r0 800240e: 2b00 cmp r3, #0 8002410: d12b bne.n 800246a if (resMeasurements.currentPeak[i] < val) { 8002412: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002416: 4a2e ldr r2, [pc, #184] @ (80024d0 ) 8002418: 3308 adds r3, #8 800241a: 009b lsls r3, r3, #2 800241c: 4413 add r3, r2 800241e: 3304 adds r3, #4 8002420: edd3 7a00 vldr s15, [r3] 8002424: ed97 7a17 vldr s14, [r7, #92] @ 0x5c 8002428: eeb4 7ae7 vcmpe.f32 s14, s15 800242c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002430: dd08 ble.n 8002444 resMeasurements.currentPeak[i] = val; 8002432: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002436: 4a26 ldr r2, [pc, #152] @ (80024d0 ) 8002438: 3308 adds r3, #8 800243a: 009b lsls r3, r3, #2 800243c: 4413 add r3, r2 800243e: 3304 adds r3, #4 8002440: 6dfa ldr r2, [r7, #92] @ 0x5c 8002442: 601a str r2, [r3, #0] } resMeasurements.currentRMS[i] = rms[i]; 8002444: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 8002448: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800244c: 0092 lsls r2, r2, #2 800244e: 3270 adds r2, #112 @ 0x70 8002450: 443a add r2, r7 8002452: 3a40 subs r2, #64 @ 0x40 8002454: 6812 ldr r2, [r2, #0] 8002456: 491e ldr r1, [pc, #120] @ (80024d0 ) 8002458: 3306 adds r3, #6 800245a: 009b lsls r3, r3, #2 800245c: 440b add r3, r1 800245e: 601a str r2, [r3, #0] osMutexRelease (resMeasurementsMutex); 8002460: 4b1a ldr r3, [pc, #104] @ (80024cc ) 8002462: 681b ldr r3, [r3, #0] 8002464: 4618 mov r0, r3 8002466: f011 fb2b bl 8013ac0 for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 800246a: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800246e: 3301 adds r3, #1 8002470: f887 3066 strb.w r3, [r7, #102] @ 0x66 8002474: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002478: 2b00 cmp r3, #0 800247a: f43f af1f beq.w 80022bc } } ++circBuffPos; 800247e: 6efb ldr r3, [r7, #108] @ 0x6c 8002480: 3301 adds r3, #1 8002482: 66fb str r3, [r7, #108] @ 0x6c circBuffPos = circBuffPos % CIRC_BUFF_LEN; 8002484: 6efa ldr r2, [r7, #108] @ 0x6c 8002486: 4b13 ldr r3, [pc, #76] @ (80024d4 ) 8002488: fba3 1302 umull r1, r3, r3, r2 800248c: 08d9 lsrs r1, r3, #3 800248e: 460b mov r3, r1 8002490: 009b lsls r3, r3, #2 8002492: 440b add r3, r1 8002494: 005b lsls r3, r3, #1 8002496: 1ad3 subs r3, r2, r3 8002498: 66fb str r3, [r7, #108] @ 0x6c while (pdTRUE) { 800249a: e6b3 b.n 8002204 800249c: f3af 8000 nop.w 80024a0: 00000000 .word 0x00000000 80024a4: 40efffe0 .word 0x40efffe0 80024a8: 83e425af .word 0x83e425af 80024ac: 401e4d9e .word 0x401e4d9e 80024b0: 24000780 .word 0x24000780 80024b4: 24000788 .word 0x24000788 80024b8: 24000030 .word 0x24000030 80024bc: 453b8000 .word 0x453b8000 80024c0: 24000794 .word 0x24000794 80024c4: 24000820 .word 0x24000820 80024c8: 24000018 .word 0x24000018 80024cc: 2400078c .word 0x2400078c 80024d0: 240007a0 .word 0x240007a0 80024d4: cccccccd .word 0xcccccccd 080024d8 : } } void ADC3MeasTask (void* arg) { 80024d8: b580 push {r7, lr} 80024da: b0bc sub sp, #240 @ 0xf0 80024dc: af00 add r7, sp, #0 80024de: 6078 str r0, [r7, #4] float motorXSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 80024e0: f107 03a4 add.w r3, r7, #164 @ 0xa4 80024e4: 2228 movs r2, #40 @ 0x28 80024e6: 2100 movs r1, #0 80024e8: 4618 mov r0, r3 80024ea: f015 fbcf bl 8017c8c float motorYSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 80024ee: f107 037c add.w r3, r7, #124 @ 0x7c 80024f2: 2228 movs r2, #40 @ 0x28 80024f4: 2100 movs r1, #0 80024f6: 4618 mov r0, r3 80024f8: f015 fbc8 bl 8017c8c float pvT1CircBuffer[CIRC_BUFF_LEN] = { 0 }; 80024fc: f107 0354 add.w r3, r7, #84 @ 0x54 8002500: 2228 movs r2, #40 @ 0x28 8002502: 2100 movs r1, #0 8002504: 4618 mov r0, r3 8002506: f015 fbc1 bl 8017c8c float pvT2CircBuffer[CIRC_BUFF_LEN] = { 0 }; 800250a: f107 032c add.w r3, r7, #44 @ 0x2c 800250e: 2228 movs r2, #40 @ 0x28 8002510: 2100 movs r1, #0 8002512: 4618 mov r0, r3 8002514: f015 fbba bl 8017c8c uint32_t circBuffPos = 0; 8002518: 2300 movs r3, #0 800251a: f8c7 30ec str.w r3, [r7, #236] @ 0xec ADC3_Data adcData = { 0 }; 800251e: f107 030c add.w r3, r7, #12 8002522: 2220 movs r2, #32 8002524: 2100 movs r1, #0 8002526: 4618 mov r0, r3 8002528: f015 fbb0 bl 8017c8c while (pdTRUE) { osMessageQueueGet (adc3MeasDataQueue, &adcData, 0, osWaitForever); 800252c: 4bc2 ldr r3, [pc, #776] @ (8002838 ) 800252e: 6818 ldr r0, [r3, #0] 8002530: f107 010c add.w r1, r7, #12 8002534: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002538: 2200 movs r2, #0 800253a: f011 fbd1 bl 8013ce0 uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B); 800253e: 4bbf ldr r3, [pc, #764] @ (800283c ) 8002540: 881b ldrh r3, [r3, #0] 8002542: 461a mov r2, r3 8002544: f640 43e4 movw r3, #3300 @ 0xce4 8002548: fb02 f303 mul.w r3, r2, r3 800254c: 8aba ldrh r2, [r7, #20] 800254e: fbb3 f3f2 udiv r3, r3, r2 8002552: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 8002556: 4bba ldr r3, [pc, #744] @ (8002840 ) 8002558: 681b ldr r3, [r3, #0] 800255a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800255e: 4618 mov r0, r3 8002560: f011 fa63 bl 8013a2a 8002564: 4603 mov r3, r0 8002566: 2b00 cmp r3, #0 8002568: d108 bne.n 800257c vRefmV = vRef; 800256a: 4ab6 ldr r2, [pc, #728] @ (8002844 ) 800256c: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8002570: 6013 str r3, [r2, #0] osMutexRelease (vRefmVMutex); 8002572: 4bb3 ldr r3, [pc, #716] @ (8002840 ) 8002574: 681b ldr r3, [r3, #0] 8002576: 4618 mov r0, r3 8002578: f011 faa2 bl 8013ac0 } float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333; 800257c: 8a3b ldrh r3, [r7, #16] 800257e: ee07 3a90 vmov s15, r3 8002582: eeb8 7be7 vcvt.f64.s32 d7, s15 8002586: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 800258a: ee27 6b06 vmul.f64 d6, d7, d6 800258e: ed9f 5ba2 vldr d5, [pc, #648] @ 8002818 8002592: ee86 7b05 vdiv.f64 d7, d6, d5 8002596: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 800259a: ee27 6b06 vmul.f64 d6, d7, d6 800259e: ed9f 5ba0 vldr d5, [pc, #640] @ 8002820 80025a2: ee86 7b05 vdiv.f64 d7, d6, d5 80025a6: eef7 7bc7 vcvt.f32.f64 s15, d7 80025aa: edc7 7a34 vstr s15, [r7, #208] @ 0xd0 float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333; 80025ae: 8a7b ldrh r3, [r7, #18] 80025b0: ee07 3a90 vmov s15, r3 80025b4: eeb8 7be7 vcvt.f64.s32 d7, s15 80025b8: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80025bc: ee27 6b06 vmul.f64 d6, d7, d6 80025c0: ed9f 5b95 vldr d5, [pc, #596] @ 8002818 80025c4: ee86 7b05 vdiv.f64 d7, d6, d5 80025c8: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 80025cc: ee27 6b06 vmul.f64 d6, d7, d6 80025d0: ed9f 5b93 vldr d5, [pc, #588] @ 8002820 80025d4: ee86 7b05 vdiv.f64 d7, d6, d5 80025d8: eef7 7bc7 vcvt.f32.f64 s15, d7 80025dc: edc7 7a33 vstr s15, [r7, #204] @ 0xcc motorXSensCircBuffer[circBuffPos] = motorXCurrentSense; 80025e0: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 80025e4: 009b lsls r3, r3, #2 80025e6: 33f0 adds r3, #240 @ 0xf0 80025e8: 443b add r3, r7 80025ea: 3b4c subs r3, #76 @ 0x4c 80025ec: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 80025f0: 601a str r2, [r3, #0] motorYSensCircBuffer[circBuffPos] = motorYCurrentSense; 80025f2: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 80025f6: 009b lsls r3, r3, #2 80025f8: 33f0 adds r3, #240 @ 0xf0 80025fa: 443b add r3, r7 80025fc: 3b74 subs r3, #116 @ 0x74 80025fe: f8d7 20cc ldr.w r2, [r7, #204] @ 0xcc 8002602: 601a str r2, [r3, #0] pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63; 8002604: 89bb ldrh r3, [r7, #12] 8002606: ee07 3a90 vmov s15, r3 800260a: eeb8 7be7 vcvt.f64.s32 d7, s15 800260e: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002612: ee27 6b06 vmul.f64 d6, d7, d6 8002616: ed9f 5b80 vldr d5, [pc, #512] @ 8002818 800261a: ee86 7b05 vdiv.f64 d7, d6, d5 800261e: ed9f 6b82 vldr d6, [pc, #520] @ 8002828 8002622: ee27 7b06 vmul.f64 d7, d7, d6 8002626: ed9f 6b82 vldr d6, [pc, #520] @ 8002830 800262a: ee37 7b46 vsub.f64 d7, d7, d6 800262e: eef7 7bc7 vcvt.f32.f64 s15, d7 8002632: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002636: 009b lsls r3, r3, #2 8002638: 33f0 adds r3, #240 @ 0xf0 800263a: 443b add r3, r7 800263c: 3b9c subs r3, #156 @ 0x9c 800263e: edc3 7a00 vstr s15, [r3] pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63; 8002642: 89fb ldrh r3, [r7, #14] 8002644: ee07 3a90 vmov s15, r3 8002648: eeb8 7be7 vcvt.f64.s32 d7, s15 800264c: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002650: ee27 6b06 vmul.f64 d6, d7, d6 8002654: ed9f 5b70 vldr d5, [pc, #448] @ 8002818 8002658: ee86 7b05 vdiv.f64 d7, d6, d5 800265c: ed9f 6b72 vldr d6, [pc, #456] @ 8002828 8002660: ee27 7b06 vmul.f64 d7, d7, d6 8002664: ed9f 6b72 vldr d6, [pc, #456] @ 8002830 8002668: ee37 7b46 vsub.f64 d7, d7, d6 800266c: eef7 7bc7 vcvt.f32.f64 s15, d7 8002670: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002674: 009b lsls r3, r3, #2 8002676: 33f0 adds r3, #240 @ 0xf0 8002678: 443b add r3, r7 800267a: 3bc4 subs r3, #196 @ 0xc4 800267c: edc3 7a00 vstr s15, [r3] float motorXAveCurrent = 0; 8002680: f04f 0300 mov.w r3, #0 8002684: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 float motorYAveCurrent = 0; 8002688: f04f 0300 mov.w r3, #0 800268c: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 float pvT1AveTemp = 0; 8002690: f04f 0300 mov.w r3, #0 8002694: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 float pvT2AveTemp = 0; 8002698: f04f 0300 mov.w r3, #0 800269c: f8c7 30dc str.w r3, [r7, #220] @ 0xdc for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) { 80026a0: 2300 movs r3, #0 80026a2: f887 30db strb.w r3, [r7, #219] @ 0xdb 80026a6: e03c b.n 8002722 motorXAveCurrent += motorXSensCircBuffer[i]; 80026a8: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 80026ac: 009b lsls r3, r3, #2 80026ae: 33f0 adds r3, #240 @ 0xf0 80026b0: 443b add r3, r7 80026b2: 3b4c subs r3, #76 @ 0x4c 80026b4: edd3 7a00 vldr s15, [r3] 80026b8: ed97 7a3a vldr s14, [r7, #232] @ 0xe8 80026bc: ee77 7a27 vadd.f32 s15, s14, s15 80026c0: edc7 7a3a vstr s15, [r7, #232] @ 0xe8 motorYAveCurrent += motorYSensCircBuffer[i]; 80026c4: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 80026c8: 009b lsls r3, r3, #2 80026ca: 33f0 adds r3, #240 @ 0xf0 80026cc: 443b add r3, r7 80026ce: 3b74 subs r3, #116 @ 0x74 80026d0: edd3 7a00 vldr s15, [r3] 80026d4: ed97 7a39 vldr s14, [r7, #228] @ 0xe4 80026d8: ee77 7a27 vadd.f32 s15, s14, s15 80026dc: edc7 7a39 vstr s15, [r7, #228] @ 0xe4 #ifdef PV_BOARD pvT1AveTemp += pvT1CircBuffer[i]; 80026e0: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 80026e4: 009b lsls r3, r3, #2 80026e6: 33f0 adds r3, #240 @ 0xf0 80026e8: 443b add r3, r7 80026ea: 3b9c subs r3, #156 @ 0x9c 80026ec: edd3 7a00 vldr s15, [r3] 80026f0: ed97 7a38 vldr s14, [r7, #224] @ 0xe0 80026f4: ee77 7a27 vadd.f32 s15, s14, s15 80026f8: edc7 7a38 vstr s15, [r7, #224] @ 0xe0 pvT2AveTemp += pvT2CircBuffer[i]; 80026fc: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002700: 009b lsls r3, r3, #2 8002702: 33f0 adds r3, #240 @ 0xf0 8002704: 443b add r3, r7 8002706: 3bc4 subs r3, #196 @ 0xc4 8002708: edd3 7a00 vldr s15, [r3] 800270c: ed97 7a37 vldr s14, [r7, #220] @ 0xdc 8002710: ee77 7a27 vadd.f32 s15, s14, s15 8002714: edc7 7a37 vstr s15, [r7, #220] @ 0xdc for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) { 8002718: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 800271c: 3301 adds r3, #1 800271e: f887 30db strb.w r3, [r7, #219] @ 0xdb 8002722: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002726: 2b09 cmp r3, #9 8002728: d9be bls.n 80026a8 #endif } motorXAveCurrent /= CIRC_BUFF_LEN; 800272a: ed97 7a3a vldr s14, [r7, #232] @ 0xe8 800272e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002732: eec7 7a26 vdiv.f32 s15, s14, s13 8002736: edc7 7a3a vstr s15, [r7, #232] @ 0xe8 motorYAveCurrent /= CIRC_BUFF_LEN; 800273a: ed97 7a39 vldr s14, [r7, #228] @ 0xe4 800273e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002742: eec7 7a26 vdiv.f32 s15, s14, s13 8002746: edc7 7a39 vstr s15, [r7, #228] @ 0xe4 pvT1AveTemp /= CIRC_BUFF_LEN; 800274a: ed97 7a38 vldr s14, [r7, #224] @ 0xe0 800274e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002752: eec7 7a26 vdiv.f32 s15, s14, s13 8002756: edc7 7a38 vstr s15, [r7, #224] @ 0xe0 pvT2AveTemp /= CIRC_BUFF_LEN; 800275a: ed97 7a37 vldr s14, [r7, #220] @ 0xdc 800275e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002762: eec7 7a26 vdiv.f32 s15, s14, s13 8002766: edc7 7a37 vstr s15, [r7, #220] @ 0xdc if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800276a: 4b37 ldr r3, [pc, #220] @ (8002848 ) 800276c: 681b ldr r3, [r3, #0] 800276e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002772: 4618 mov r0, r3 8002774: f011 f959 bl 8013a2a 8002778: 4603 mov r3, r0 800277a: 2b00 cmp r3, #0 800277c: d138 bne.n 80027f0 if (sensorsInfo.motorXStatus == 1) { 800277e: 4b33 ldr r3, [pc, #204] @ (800284c ) 8002780: 7d1b ldrb r3, [r3, #20] 8002782: 2b01 cmp r3, #1 8002784: d111 bne.n 80027aa sensorsInfo.motorXAveCurrent = motorXAveCurrent; 8002786: 4a31 ldr r2, [pc, #196] @ (800284c ) 8002788: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8 800278c: 6193 str r3, [r2, #24] if (sensorsInfo.motorXPeakCurrent < motorXCurrentSense) { 800278e: 4b2f ldr r3, [pc, #188] @ (800284c ) 8002790: edd3 7a08 vldr s15, [r3, #32] 8002794: ed97 7a34 vldr s14, [r7, #208] @ 0xd0 8002798: eeb4 7ae7 vcmpe.f32 s14, s15 800279c: eef1 fa10 vmrs APSR_nzcv, fpscr 80027a0: dd03 ble.n 80027aa sensorsInfo.motorXPeakCurrent = motorXCurrentSense; 80027a2: 4a2a ldr r2, [pc, #168] @ (800284c ) 80027a4: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0 80027a8: 6213 str r3, [r2, #32] } } if (sensorsInfo.motorYStatus == 1) { 80027aa: 4b28 ldr r3, [pc, #160] @ (800284c ) 80027ac: 7d5b ldrb r3, [r3, #21] 80027ae: 2b01 cmp r3, #1 80027b0: d111 bne.n 80027d6 sensorsInfo.motorYAveCurrent = motorYAveCurrent; 80027b2: 4a26 ldr r2, [pc, #152] @ (800284c ) 80027b4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80027b8: 61d3 str r3, [r2, #28] if (sensorsInfo.motorYPeakCurrent < motorYCurrentSense) { 80027ba: 4b24 ldr r3, [pc, #144] @ (800284c ) 80027bc: edd3 7a09 vldr s15, [r3, #36] @ 0x24 80027c0: ed97 7a33 vldr s14, [r7, #204] @ 0xcc 80027c4: eeb4 7ae7 vcmpe.f32 s14, s15 80027c8: eef1 fa10 vmrs APSR_nzcv, fpscr 80027cc: dd03 ble.n 80027d6 sensorsInfo.motorYPeakCurrent = motorYCurrentSense; 80027ce: 4a1f ldr r2, [pc, #124] @ (800284c ) 80027d0: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc 80027d4: 6253 str r3, [r2, #36] @ 0x24 } } sensorsInfo.pvTemperature[0] = pvT1AveTemp; 80027d6: 4a1d ldr r2, [pc, #116] @ (800284c ) 80027d8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80027dc: 6013 str r3, [r2, #0] sensorsInfo.pvTemperature[1] = pvT2AveTemp; 80027de: 4a1b ldr r2, [pc, #108] @ (800284c ) 80027e0: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80027e4: 6053 str r3, [r2, #4] osMutexRelease (sensorsInfoMutex); 80027e6: 4b18 ldr r3, [pc, #96] @ (8002848 ) 80027e8: 681b ldr r3, [r3, #0] 80027ea: 4618 mov r0, r3 80027ec: f011 f968 bl 8013ac0 } ++circBuffPos; 80027f0: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 80027f4: 3301 adds r3, #1 80027f6: f8c7 30ec str.w r3, [r7, #236] @ 0xec circBuffPos = circBuffPos % CIRC_BUFF_LEN; 80027fa: f8d7 20ec ldr.w r2, [r7, #236] @ 0xec 80027fe: 4b14 ldr r3, [pc, #80] @ (8002850 ) 8002800: fba3 1302 umull r1, r3, r3, r2 8002804: 08d9 lsrs r1, r3, #3 8002806: 460b mov r3, r1 8002808: 009b lsls r3, r3, #2 800280a: 440b add r3, r1 800280c: 005b lsls r3, r3, #1 800280e: 1ad3 subs r3, r2, r3 8002810: f8c7 30ec str.w r3, [r7, #236] @ 0xec while (pdTRUE) { 8002814: e68a b.n 800252c 8002816: bf00 nop 8002818: 00000000 .word 0x00000000 800281c: 40efffe0 .word 0x40efffe0 8002820: 3ad18d26 .word 0x3ad18d26 8002824: 4020aaaa .word 0x4020aaaa 8002828: aaa38226 .word 0xaaa38226 800282c: 4046aaaa .word 0x4046aaaa 8002830: 00000000 .word 0x00000000 8002834: 404f8000 .word 0x404f8000 8002838: 24000784 .word 0x24000784 800283c: 1ff1e860 .word 0x1ff1e860 8002840: 24000788 .word 0x24000788 8002844: 24000030 .word 0x24000030 8002848: 24000790 .word 0x24000790 800284c: 240007e0 .word 0x240007e0 8002850: cccccccd .word 0xcccccccd 08002854 : } } void LimiterSwitchTask (void* arg) { 8002854: b580 push {r7, lr} 8002856: b08c sub sp, #48 @ 0x30 8002858: af06 add r7, sp, #24 800285a: 6078 str r0, [r7, #4] uint8_t limitXSwitchDownPrevState = 0; 800285c: 2300 movs r3, #0 800285e: 75fb strb r3, [r7, #23] uint8_t limitXSwitchCenterPrevState = 0; 8002860: 2300 movs r3, #0 8002862: 75bb strb r3, [r7, #22] uint8_t limitXSwitchUpPrevState = 0; 8002864: 2300 movs r3, #0 8002866: 757b strb r3, [r7, #21] uint8_t limitYSwitchDownPrevState = 0; 8002868: 2300 movs r3, #0 800286a: 753b strb r3, [r7, #20] uint8_t limitYSwitchCenterPrevState = 0; 800286c: 2300 movs r3, #0 800286e: 74fb strb r3, [r7, #19] uint8_t limitYSwitchUpPrevState = 0; 8002870: 2300 movs r3, #0 8002872: 74bb strb r3, [r7, #18] uint8_t pinStates = 0; 8002874: 2300 movs r3, #0 8002876: 73fb strb r3, [r7, #15] uint8_t limiterXTriggered = 0; 8002878: 2300 movs r3, #0 800287a: 747b strb r3, [r7, #17] uint8_t limiterYTriggered = 0; 800287c: 2300 movs r3, #0 800287e: 743b strb r3, [r7, #16] if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8002880: 4bad ldr r3, [pc, #692] @ (8002b38 ) 8002882: 681b ldr r3, [r3, #0] 8002884: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002888: 4618 mov r0, r3 800288a: f011 f8ce bl 8013a2a 800288e: 4603 mov r3, r0 8002890: 2b00 cmp r3, #0 8002892: d10c bne.n 80028ae sensorsInfo.positionXWeak = 1; 8002894: 4ba9 ldr r3, [pc, #676] @ (8002b3c ) 8002896: 2201 movs r2, #1 8002898: f883 2038 strb.w r2, [r3, #56] @ 0x38 sensorsInfo.positionYWeak = 1; 800289c: 4ba7 ldr r3, [pc, #668] @ (8002b3c ) 800289e: 2201 movs r2, #1 80028a0: f883 2039 strb.w r2, [r3, #57] @ 0x39 osMutexRelease (sensorsInfoMutex); 80028a4: 4ba4 ldr r3, [pc, #656] @ (8002b38 ) 80028a6: 681b ldr r3, [r3, #0] 80028a8: 4618 mov r0, r3 80028aa: f011 f909 bl 8013ac0 } while (pdTRUE) { osDelay (pdMS_TO_TICKS (100)); 80028ae: 2064 movs r0, #100 @ 0x64 80028b0: f010 ff23 bl 80136fa if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80028b4: 4ba0 ldr r3, [pc, #640] @ (8002b38 ) 80028b6: 681b ldr r3, [r3, #0] 80028b8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80028bc: 4618 mov r0, r3 80028be: f011 f8b4 bl 8013a2a 80028c2: 4603 mov r3, r0 80028c4: 2b00 cmp r3, #0 80028c6: d1f2 bne.n 80028ae sensorsInfo.limitXSwitchDown = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_13); 80028c8: f44f 5100 mov.w r1, #8192 @ 0x2000 80028cc: 489c ldr r0, [pc, #624] @ (8002b40 ) 80028ce: f008 fcf7 bl 800b2c0 80028d2: 4603 mov r3, r0 80028d4: 461a mov r2, r3 80028d6: 4b99 ldr r3, [pc, #612] @ (8002b3c ) 80028d8: f883 2029 strb.w r2, [r3, #41] @ 0x29 pinStates = (limitXSwitchDownPrevState << 1) | sensorsInfo.limitXSwitchDown; 80028dc: 7dfb ldrb r3, [r7, #23] 80028de: 005b lsls r3, r3, #1 80028e0: b25a sxtb r2, r3 80028e2: 4b96 ldr r3, [pc, #600] @ (8002b3c ) 80028e4: f893 3029 ldrb.w r3, [r3, #41] @ 0x29 80028e8: b25b sxtb r3, r3 80028ea: 4313 orrs r3, r2 80028ec: b25b sxtb r3, r3 80028ee: 73fb strb r3, [r7, #15] if ((pinStates & 0x3) == 0x1) { 80028f0: 7bfb ldrb r3, [r7, #15] 80028f2: f003 0303 and.w r3, r3, #3 80028f6: 2b01 cmp r3, #1 80028f8: d109 bne.n 800290e limiterXTriggered = 1; 80028fa: 2301 movs r3, #1 80028fc: 747b strb r3, [r7, #17] sensorsInfo.currentXPosition = 0; 80028fe: 4b8f ldr r3, [pc, #572] @ (8002b3c ) 8002900: f04f 0200 mov.w r2, #0 8002904: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8002906: 4b8d ldr r3, [pc, #564] @ (8002b3c ) 8002908: 2200 movs r2, #0 800290a: f883 2038 strb.w r2, [r3, #56] @ 0x38 } limitXSwitchDownPrevState = sensorsInfo.limitXSwitchDown; 800290e: 4b8b ldr r3, [pc, #556] @ (8002b3c ) 8002910: f893 3029 ldrb.w r3, [r3, #41] @ 0x29 8002914: 75fb strb r3, [r7, #23] sensorsInfo.limitXSwitchUp = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_12); 8002916: f44f 5180 mov.w r1, #4096 @ 0x1000 800291a: 4889 ldr r0, [pc, #548] @ (8002b40 ) 800291c: f008 fcd0 bl 800b2c0 8002920: 4603 mov r3, r0 8002922: 461a mov r2, r3 8002924: 4b85 ldr r3, [pc, #532] @ (8002b3c ) 8002926: f883 2028 strb.w r2, [r3, #40] @ 0x28 pinStates = (limitXSwitchUpPrevState << 1) | sensorsInfo.limitXSwitchUp; 800292a: 7d7b ldrb r3, [r7, #21] 800292c: 005b lsls r3, r3, #1 800292e: b25a sxtb r2, r3 8002930: 4b82 ldr r3, [pc, #520] @ (8002b3c ) 8002932: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8002936: b25b sxtb r3, r3 8002938: 4313 orrs r3, r2 800293a: b25b sxtb r3, r3 800293c: 73fb strb r3, [r7, #15] if ((pinStates & 0x3) == 0x1) { 800293e: 7bfb ldrb r3, [r7, #15] 8002940: f003 0303 and.w r3, r3, #3 8002944: 2b01 cmp r3, #1 8002946: d108 bne.n 800295a limiterXTriggered = 1; 8002948: 2301 movs r3, #1 800294a: 747b strb r3, [r7, #17] sensorsInfo.currentXPosition = 100; 800294c: 4b7b ldr r3, [pc, #492] @ (8002b3c ) 800294e: 4a7d ldr r2, [pc, #500] @ (8002b44 ) 8002950: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8002952: 4b7a ldr r3, [pc, #488] @ (8002b3c ) 8002954: 2200 movs r2, #0 8002956: f883 2038 strb.w r2, [r3, #56] @ 0x38 } limitXSwitchUpPrevState = sensorsInfo.limitXSwitchUp; 800295a: 4b78 ldr r3, [pc, #480] @ (8002b3c ) 800295c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8002960: 757b strb r3, [r7, #21] sensorsInfo.limitXSwitchCenter = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_10); 8002962: f44f 6180 mov.w r1, #1024 @ 0x400 8002966: 4876 ldr r0, [pc, #472] @ (8002b40 ) 8002968: f008 fcaa bl 800b2c0 800296c: 4603 mov r3, r0 800296e: 461a mov r2, r3 8002970: 4b72 ldr r3, [pc, #456] @ (8002b3c ) 8002972: f883 202a strb.w r2, [r3, #42] @ 0x2a pinStates = (limitXSwitchCenterPrevState << 1) | sensorsInfo.limitXSwitchCenter; 8002976: 7dbb ldrb r3, [r7, #22] 8002978: 005b lsls r3, r3, #1 800297a: b25a sxtb r2, r3 800297c: 4b6f ldr r3, [pc, #444] @ (8002b3c ) 800297e: f893 302a ldrb.w r3, [r3, #42] @ 0x2a 8002982: b25b sxtb r3, r3 8002984: 4313 orrs r3, r2 8002986: b25b sxtb r3, r3 8002988: 73fb strb r3, [r7, #15] if ((pinStates & 0x3) == 0x1) { 800298a: 7bfb ldrb r3, [r7, #15] 800298c: f003 0303 and.w r3, r3, #3 8002990: 2b01 cmp r3, #1 8002992: d106 bne.n 80029a2 sensorsInfo.currentXPosition = AXE_X_MIDDLE_VALUE; 8002994: 4b69 ldr r3, [pc, #420] @ (8002b3c ) 8002996: 4a6c ldr r2, [pc, #432] @ (8002b48 ) 8002998: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 800299a: 4b68 ldr r3, [pc, #416] @ (8002b3c ) 800299c: 2200 movs r2, #0 800299e: f883 2038 strb.w r2, [r3, #56] @ 0x38 } limitXSwitchCenterPrevState = sensorsInfo.limitXSwitchCenter; 80029a2: 4b66 ldr r3, [pc, #408] @ (8002b3c ) 80029a4: f893 302a ldrb.w r3, [r3, #42] @ 0x2a 80029a8: 75bb strb r3, [r7, #22] sensorsInfo.limitYSwitchDown = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_9); 80029aa: f44f 7100 mov.w r1, #512 @ 0x200 80029ae: 4864 ldr r0, [pc, #400] @ (8002b40 ) 80029b0: f008 fc86 bl 800b2c0 80029b4: 4603 mov r3, r0 80029b6: 461a mov r2, r3 80029b8: 4b60 ldr r3, [pc, #384] @ (8002b3c ) 80029ba: f883 202c strb.w r2, [r3, #44] @ 0x2c pinStates = (limitYSwitchDownPrevState << 1) | sensorsInfo.limitYSwitchDown; 80029be: 7d3b ldrb r3, [r7, #20] 80029c0: 005b lsls r3, r3, #1 80029c2: b25a sxtb r2, r3 80029c4: 4b5d ldr r3, [pc, #372] @ (8002b3c ) 80029c6: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 80029ca: b25b sxtb r3, r3 80029cc: 4313 orrs r3, r2 80029ce: b25b sxtb r3, r3 80029d0: 73fb strb r3, [r7, #15] if ((pinStates & 0x3) == 0x1) { 80029d2: 7bfb ldrb r3, [r7, #15] 80029d4: f003 0303 and.w r3, r3, #3 80029d8: 2b01 cmp r3, #1 80029da: d109 bne.n 80029f0 limiterYTriggered = 1; 80029dc: 2301 movs r3, #1 80029de: 743b strb r3, [r7, #16] sensorsInfo.currentYPosition = 0; 80029e0: 4b56 ldr r3, [pc, #344] @ (8002b3c ) 80029e2: f04f 0200 mov.w r2, #0 80029e6: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 80029e8: 4b54 ldr r3, [pc, #336] @ (8002b3c ) 80029ea: 2200 movs r2, #0 80029ec: f883 2039 strb.w r2, [r3, #57] @ 0x39 } limitYSwitchDownPrevState = sensorsInfo.limitYSwitchDown; 80029f0: 4b52 ldr r3, [pc, #328] @ (8002b3c ) 80029f2: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 80029f6: 753b strb r3, [r7, #20] sensorsInfo.limitYSwitchUp = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_11); 80029f8: f44f 6100 mov.w r1, #2048 @ 0x800 80029fc: 4850 ldr r0, [pc, #320] @ (8002b40 ) 80029fe: f008 fc5f bl 800b2c0 8002a02: 4603 mov r3, r0 8002a04: 461a mov r2, r3 8002a06: 4b4d ldr r3, [pc, #308] @ (8002b3c ) 8002a08: f883 202b strb.w r2, [r3, #43] @ 0x2b pinStates = (limitYSwitchUpPrevState << 1) | sensorsInfo.limitYSwitchUp; 8002a0c: 7cbb ldrb r3, [r7, #18] 8002a0e: 005b lsls r3, r3, #1 8002a10: b25a sxtb r2, r3 8002a12: 4b4a ldr r3, [pc, #296] @ (8002b3c ) 8002a14: f893 302b ldrb.w r3, [r3, #43] @ 0x2b 8002a18: b25b sxtb r3, r3 8002a1a: 4313 orrs r3, r2 8002a1c: b25b sxtb r3, r3 8002a1e: 73fb strb r3, [r7, #15] if ((pinStates & 0x3) == 0x1) { 8002a20: 7bfb ldrb r3, [r7, #15] 8002a22: f003 0303 and.w r3, r3, #3 8002a26: 2b01 cmp r3, #1 8002a28: d108 bne.n 8002a3c limiterYTriggered = 1; 8002a2a: 2301 movs r3, #1 8002a2c: 743b strb r3, [r7, #16] sensorsInfo.currentYPosition = 100; 8002a2e: 4b43 ldr r3, [pc, #268] @ (8002b3c ) 8002a30: 4a44 ldr r2, [pc, #272] @ (8002b44 ) 8002a32: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8002a34: 4b41 ldr r3, [pc, #260] @ (8002b3c ) 8002a36: 2200 movs r2, #0 8002a38: f883 2039 strb.w r2, [r3, #57] @ 0x39 } limitYSwitchUpPrevState = sensorsInfo.limitYSwitchUp; 8002a3c: 4b3f ldr r3, [pc, #252] @ (8002b3c ) 8002a3e: f893 302b ldrb.w r3, [r3, #43] @ 0x2b 8002a42: 74bb strb r3, [r7, #18] sensorsInfo.limitYSwitchCenter = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_8); 8002a44: f44f 7180 mov.w r1, #256 @ 0x100 8002a48: 483d ldr r0, [pc, #244] @ (8002b40 ) 8002a4a: f008 fc39 bl 800b2c0 8002a4e: 4603 mov r3, r0 8002a50: 461a mov r2, r3 8002a52: 4b3a ldr r3, [pc, #232] @ (8002b3c ) 8002a54: f883 202d strb.w r2, [r3, #45] @ 0x2d pinStates = (limitYSwitchCenterPrevState << 1) | sensorsInfo.limitYSwitchCenter; 8002a58: 7cfb ldrb r3, [r7, #19] 8002a5a: 005b lsls r3, r3, #1 8002a5c: b25a sxtb r2, r3 8002a5e: 4b37 ldr r3, [pc, #220] @ (8002b3c ) 8002a60: f893 302d ldrb.w r3, [r3, #45] @ 0x2d 8002a64: b25b sxtb r3, r3 8002a66: 4313 orrs r3, r2 8002a68: b25b sxtb r3, r3 8002a6a: 73fb strb r3, [r7, #15] if ((pinStates & 0x3) == 0x1) { 8002a6c: 7bfb ldrb r3, [r7, #15] 8002a6e: f003 0303 and.w r3, r3, #3 8002a72: 2b01 cmp r3, #1 8002a74: d106 bne.n 8002a84 sensorsInfo.currentYPosition = AXE_Y_MIDDLE_VALUE; 8002a76: 4b31 ldr r3, [pc, #196] @ (8002b3c ) 8002a78: 4a33 ldr r2, [pc, #204] @ (8002b48 ) 8002a7a: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8002a7c: 4b2f ldr r3, [pc, #188] @ (8002b3c ) 8002a7e: 2200 movs r2, #0 8002a80: f883 2039 strb.w r2, [r3, #57] @ 0x39 } limitYSwitchCenterPrevState = sensorsInfo.limitYSwitchCenter; 8002a84: 4b2d ldr r3, [pc, #180] @ (8002b3c ) 8002a86: f893 302d ldrb.w r3, [r3, #45] @ 0x2d 8002a8a: 74fb strb r3, [r7, #19] if (((sensorsInfo.limitXSwitchDown == 1) || (sensorsInfo.limitXSwitchUp == 1)) && (limiterXTriggered == 1)) { 8002a8c: 4b2b ldr r3, [pc, #172] @ (8002b3c ) 8002a8e: f893 3029 ldrb.w r3, [r3, #41] @ 0x29 8002a92: 2b01 cmp r3, #1 8002a94: d004 beq.n 8002aa0 8002a96: 4b29 ldr r3, [pc, #164] @ (8002b3c ) 8002a98: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8002a9c: 2b01 cmp r3, #1 8002a9e: d11b bne.n 8002ad8 8002aa0: 7c7b ldrb r3, [r7, #17] 8002aa2: 2b01 cmp r3, #1 8002aa4: d118 bne.n 8002ad8 sensorsInfo.motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, 0, 0, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 8002aa6: 4b29 ldr r3, [pc, #164] @ (8002b4c ) 8002aa8: 681b ldr r3, [r3, #0] 8002aaa: 4a24 ldr r2, [pc, #144] @ (8002b3c ) 8002aac: f892 2028 ldrb.w r2, [r2, #40] @ 0x28 8002ab0: 4922 ldr r1, [pc, #136] @ (8002b3c ) 8002ab2: f891 1029 ldrb.w r1, [r1, #41] @ 0x29 8002ab6: 9104 str r1, [sp, #16] 8002ab8: 9203 str r2, [sp, #12] 8002aba: 2200 movs r2, #0 8002abc: 9202 str r2, [sp, #8] 8002abe: 2200 movs r2, #0 8002ac0: 9201 str r2, [sp, #4] 8002ac2: 9300 str r3, [sp, #0] 8002ac4: 2304 movs r3, #4 8002ac6: 2200 movs r2, #0 8002ac8: 4921 ldr r1, [pc, #132] @ (8002b50 ) 8002aca: 4822 ldr r0, [pc, #136] @ (8002b54 ) 8002acc: f000 f9b4 bl 8002e38 8002ad0: 4603 mov r3, r0 8002ad2: 461a mov r2, r3 8002ad4: 4b19 ldr r3, [pc, #100] @ (8002b3c ) 8002ad6: 751a strb r2, [r3, #20] } if (((sensorsInfo.limitYSwitchDown == 1) || (sensorsInfo.limitYSwitchUp == 1)) && (limiterYTriggered == 1)) { 8002ad8: 4b18 ldr r3, [pc, #96] @ (8002b3c ) 8002ada: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 8002ade: 2b01 cmp r3, #1 8002ae0: d004 beq.n 8002aec 8002ae2: 4b16 ldr r3, [pc, #88] @ (8002b3c ) 8002ae4: f893 302b ldrb.w r3, [r3, #43] @ 0x2b 8002ae8: 2b01 cmp r3, #1 8002aea: d11b bne.n 8002b24 8002aec: 7c3b ldrb r3, [r7, #16] 8002aee: 2b01 cmp r3, #1 8002af0: d118 bne.n 8002b24 sensorsInfo.motorYStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, 0, 0, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 8002af2: 4b19 ldr r3, [pc, #100] @ (8002b58 ) 8002af4: 681b ldr r3, [r3, #0] 8002af6: 4a11 ldr r2, [pc, #68] @ (8002b3c ) 8002af8: f892 202b ldrb.w r2, [r2, #43] @ 0x2b 8002afc: 490f ldr r1, [pc, #60] @ (8002b3c ) 8002afe: f891 102c ldrb.w r1, [r1, #44] @ 0x2c 8002b02: 9104 str r1, [sp, #16] 8002b04: 9203 str r2, [sp, #12] 8002b06: 2200 movs r2, #0 8002b08: 9202 str r2, [sp, #8] 8002b0a: 2200 movs r2, #0 8002b0c: 9201 str r2, [sp, #4] 8002b0e: 9300 str r3, [sp, #0] 8002b10: 230c movs r3, #12 8002b12: 2208 movs r2, #8 8002b14: 490e ldr r1, [pc, #56] @ (8002b50 ) 8002b16: 480f ldr r0, [pc, #60] @ (8002b54 ) 8002b18: f000 f98e bl 8002e38 8002b1c: 4603 mov r3, r0 8002b1e: 461a mov r2, r3 8002b20: 4b06 ldr r3, [pc, #24] @ (8002b3c ) 8002b22: 755a strb r2, [r3, #21] } limiterXTriggered = 0; 8002b24: 2300 movs r3, #0 8002b26: 747b strb r3, [r7, #17] limiterYTriggered = 0; 8002b28: 2300 movs r3, #0 8002b2a: 743b strb r3, [r7, #16] osMutexRelease (sensorsInfoMutex); 8002b2c: 4b02 ldr r3, [pc, #8] @ (8002b38 ) 8002b2e: 681b ldr r3, [r3, #0] 8002b30: 4618 mov r0, r3 8002b32: f010 ffc5 bl 8013ac0 osDelay (pdMS_TO_TICKS (100)); 8002b36: e6ba b.n 80028ae 8002b38: 24000790 .word 0x24000790 8002b3c: 240007e0 .word 0x240007e0 8002b40: 58020c00 .word 0x58020c00 8002b44: 42c80000 .word 0x42c80000 8002b48: 42480000 .word 0x42480000 8002b4c: 240006bc .word 0x240006bc 8002b50: 24000738 .word 0x24000738 8002b54: 24000498 .word 0x24000498 8002b58: 240006ec .word 0x240006ec 8002b5c: 00000000 .word 0x00000000 08002b60 : } } } void EncoderTask (void* arg) { 8002b60: b590 push {r4, r7, lr} 8002b62: b08b sub sp, #44 @ 0x2c 8002b64: af00 add r7, sp, #0 8002b66: 6078 str r0, [r7, #4] // 01 11 10 00 const uint32_t encoderStates[4] = { 0x00, 0x01, 0x03, 0x02 }; 8002b68: 4b67 ldr r3, [pc, #412] @ (8002d08 ) 8002b6a: f107 040c add.w r4, r7, #12 8002b6e: cb0f ldmia r3, {r0, r1, r2, r3} 8002b70: e884 000f stmia.w r4, {r0, r1, r2, r3} uint8_t step = 0; 8002b74: 2300 movs r3, #0 8002b76: f887 3027 strb.w r3, [r7, #39] @ 0x27 EncoderTaskArg* encoderTaskArg = (EncoderTaskArg*)arg; 8002b7a: 687b ldr r3, [r7, #4] 8002b7c: 61fb str r3, [r7, #28] uint32_t pinStates = encoderTaskArg->initPinStates; 8002b7e: 69fb ldr r3, [r7, #28] 8002b80: 68db ldr r3, [r3, #12] 8002b82: 60bb str r3, [r7, #8] for (uint8_t i = 0; i < 4; i++) { 8002b84: 2300 movs r3, #0 8002b86: f887 3026 strb.w r3, [r7, #38] @ 0x26 8002b8a: e014 b.n 8002bb6 if (pinStates == encoderStates[i]) { 8002b8c: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 8002b90: 009b lsls r3, r3, #2 8002b92: 3328 adds r3, #40 @ 0x28 8002b94: 443b add r3, r7 8002b96: f853 2c1c ldr.w r2, [r3, #-28] 8002b9a: 68bb ldr r3, [r7, #8] 8002b9c: 429a cmp r2, r3 8002b9e: d105 bne.n 8002bac step = i; 8002ba0: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 8002ba4: f887 3027 strb.w r3, [r7, #39] @ 0x27 break; 8002ba8: bf00 nop 8002baa: e008 b.n 8002bbe for (uint8_t i = 0; i < 4; i++) { 8002bac: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 8002bb0: 3301 adds r3, #1 8002bb2: f887 3026 strb.w r3, [r7, #38] @ 0x26 8002bb6: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 8002bba: 2b03 cmp r3, #3 8002bbc: d9e6 bls.n 8002b8c } } while (pdTRUE) { float encoderValue = *encoderTaskArg->pvEncoder; 8002bbe: 69fb ldr r3, [r7, #28] 8002bc0: 689b ldr r3, [r3, #8] 8002bc2: 681b ldr r3, [r3, #0] 8002bc4: 623b str r3, [r7, #32] osMessageQueueGet (encoderTaskArg->dataQueue, &pinStates, 0, osWaitForever); 8002bc6: 69fb ldr r3, [r7, #28] 8002bc8: 6918 ldr r0, [r3, #16] 8002bca: f107 0108 add.w r1, r7, #8 8002bce: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002bd2: 2200 movs r2, #0 8002bd4: f011 f884 bl 8013ce0 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8002bd8: 4b4c ldr r3, [pc, #304] @ (8002d0c ) 8002bda: 681b ldr r3, [r3, #0] 8002bdc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002be0: 4618 mov r0, r3 8002be2: f010 ff22 bl 8013a2a 8002be6: 4603 mov r3, r0 8002be8: 2b00 cmp r3, #0 8002bea: f040 8081 bne.w 8002cf0 if (encoderStates[(step + 1) % 4] == pinStates) { 8002bee: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8002bf2: 3301 adds r3, #1 8002bf4: 425a negs r2, r3 8002bf6: f003 0303 and.w r3, r3, #3 8002bfa: f002 0203 and.w r2, r2, #3 8002bfe: bf58 it pl 8002c00: 4253 negpl r3, r2 8002c02: 009b lsls r3, r3, #2 8002c04: 3328 adds r3, #40 @ 0x28 8002c06: 443b add r3, r7 8002c08: f853 2c1c ldr.w r2, [r3, #-28] 8002c0c: 68bb ldr r3, [r7, #8] 8002c0e: 429a cmp r2, r3 8002c10: d111 bne.n 8002c36 step++; 8002c12: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8002c16: 3301 adds r3, #1 8002c18: f887 3027 strb.w r3, [r7, #39] @ 0x27 encoderValue += 360.0 / ENCODER_X_IMP_PER_TURN; 8002c1c: edd7 7a08 vldr s15, [r7, #32] 8002c20: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002c24: ed9f 6b36 vldr d6, [pc, #216] @ 8002d00 8002c28: ee37 7b06 vadd.f64 d7, d7, d6 8002c2c: eef7 7bc7 vcvt.f32.f64 s15, d7 8002c30: edc7 7a08 vstr s15, [r7, #32] 8002c34: e035 b.n 8002ca2 // printf ("Forward\n"); } else if (encoderStates[(step - 1) % 4] == pinStates) { 8002c36: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8002c3a: 3b01 subs r3, #1 8002c3c: 425a negs r2, r3 8002c3e: f003 0303 and.w r3, r3, #3 8002c42: f002 0203 and.w r2, r2, #3 8002c46: bf58 it pl 8002c48: 4253 negpl r3, r2 8002c4a: 009b lsls r3, r3, #2 8002c4c: 3328 adds r3, #40 @ 0x28 8002c4e: 443b add r3, r7 8002c50: f853 2c1c ldr.w r2, [r3, #-28] 8002c54: 68bb ldr r3, [r7, #8] 8002c56: 429a cmp r2, r3 8002c58: d120 bne.n 8002c9c encoderValue -= 360.0 / ENCODER_X_IMP_PER_TURN; 8002c5a: edd7 7a08 vldr s15, [r7, #32] 8002c5e: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002c62: ed9f 6b27 vldr d6, [pc, #156] @ 8002d00 8002c66: ee37 7b46 vsub.f64 d7, d7, d6 8002c6a: eef7 7bc7 vcvt.f32.f64 s15, d7 8002c6e: edc7 7a08 vstr s15, [r7, #32] if (encoderValue < 0) { 8002c72: edd7 7a08 vldr s15, [r7, #32] 8002c76: eef5 7ac0 vcmpe.f32 s15, #0.0 8002c7a: eef1 fa10 vmrs APSR_nzcv, fpscr 8002c7e: d507 bpl.n 8002c90 encoderValue = 360.0 + encoderValue; 8002c80: edd7 7a08 vldr s15, [r7, #32] 8002c84: ed9f 7a22 vldr s14, [pc, #136] @ 8002d10 8002c88: ee77 7a87 vadd.f32 s15, s15, s14 8002c8c: edc7 7a08 vstr s15, [r7, #32] } // printf ("Reverse\n"); step--; 8002c90: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8002c94: 3b01 subs r3, #1 8002c96: f887 3027 strb.w r3, [r7, #39] @ 0x27 8002c9a: e002 b.n 8002ca2 } else { printf ("Forbidden\n"); 8002c9c: 481d ldr r0, [pc, #116] @ (8002d14 ) 8002c9e: f014 ff15 bl 8017acc } step = step % 4; 8002ca2: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8002ca6: f003 0303 and.w r3, r3, #3 8002caa: f887 3027 strb.w r3, [r7, #39] @ 0x27 *encoderTaskArg->pvEncoder = fmodf (encoderValue, 360.0); 8002cae: 69fb ldr r3, [r7, #28] 8002cb0: 689c ldr r4, [r3, #8] 8002cb2: eddf 0a17 vldr s1, [pc, #92] @ 8002d10 8002cb6: ed97 0a08 vldr s0, [r7, #32] 8002cba: f015 fdcf bl 801885c 8002cbe: eef0 7a40 vmov.f32 s15, s0 8002cc2: edc4 7a00 vstr s15, [r4] *encoderTaskArg->currentPosition = 100 * (*encoderTaskArg->pvEncoder) / MAX_X_AXE_ANGLE; 8002cc6: 69fb ldr r3, [r7, #28] 8002cc8: 689b ldr r3, [r3, #8] 8002cca: edd3 7a00 vldr s15, [r3] 8002cce: ed9f 7a12 vldr s14, [pc, #72] @ 8002d18 8002cd2: ee27 7a87 vmul.f32 s14, s15, s14 8002cd6: 69fb ldr r3, [r7, #28] 8002cd8: 685b ldr r3, [r3, #4] 8002cda: eddf 6a0d vldr s13, [pc, #52] @ 8002d10 8002cde: eec7 7a26 vdiv.f32 s15, s14, s13 8002ce2: edc3 7a00 vstr s15, [r3] osMutexRelease (sensorsInfoMutex); 8002ce6: 4b09 ldr r3, [pc, #36] @ (8002d0c ) 8002ce8: 681b ldr r3, [r3, #0] 8002cea: 4618 mov r0, r3 8002cec: f010 fee8 bl 8013ac0 } DbgLEDToggle (encoderTaskArg->dbgLed); 8002cf0: 69fb ldr r3, [r7, #28] 8002cf2: 881b ldrh r3, [r3, #0] 8002cf4: b2db uxtb r3, r3 8002cf6: 4618 mov r0, r3 8002cf8: f000 f834 bl 8002d64 while (pdTRUE) { 8002cfc: e75f b.n 8002bbe 8002cfe: bf00 nop 8002d00: cccccccd .word 0xcccccccd 8002d04: 3fdccccc .word 0x3fdccccc 8002d08: 08018a04 .word 0x08018a04 8002d0c: 24000790 .word 0x24000790 8002d10: 43b40000 .word 0x43b40000 8002d14: 080189f8 .word 0x080189f8 8002d18: 42c80000 .word 0x42c80000 08002d1c : #include #include "peripherial.h" void DbgLEDOn (uint8_t ledNumber) { 8002d1c: b580 push {r7, lr} 8002d1e: b082 sub sp, #8 8002d20: af00 add r7, sp, #0 8002d22: 4603 mov r3, r0 8002d24: 71fb strb r3, [r7, #7] HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_SET); 8002d26: 79fb ldrb r3, [r7, #7] 8002d28: b29b uxth r3, r3 8002d2a: 2201 movs r2, #1 8002d2c: 4619 mov r1, r3 8002d2e: 4803 ldr r0, [pc, #12] @ (8002d3c ) 8002d30: f008 fade bl 800b2f0 } 8002d34: bf00 nop 8002d36: 3708 adds r7, #8 8002d38: 46bd mov sp, r7 8002d3a: bd80 pop {r7, pc} 8002d3c: 58020c00 .word 0x58020c00 08002d40 : void DbgLEDOff (uint8_t ledNumber) { 8002d40: b580 push {r7, lr} 8002d42: b082 sub sp, #8 8002d44: af00 add r7, sp, #0 8002d46: 4603 mov r3, r0 8002d48: 71fb strb r3, [r7, #7] HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_RESET); 8002d4a: 79fb ldrb r3, [r7, #7] 8002d4c: b29b uxth r3, r3 8002d4e: 2200 movs r2, #0 8002d50: 4619 mov r1, r3 8002d52: 4803 ldr r0, [pc, #12] @ (8002d60 ) 8002d54: f008 facc bl 800b2f0 } 8002d58: bf00 nop 8002d5a: 3708 adds r7, #8 8002d5c: 46bd mov sp, r7 8002d5e: bd80 pop {r7, pc} 8002d60: 58020c00 .word 0x58020c00 08002d64 : void DbgLEDToggle (uint8_t ledNumber) { 8002d64: b580 push {r7, lr} 8002d66: b082 sub sp, #8 8002d68: af00 add r7, sp, #0 8002d6a: 4603 mov r3, r0 8002d6c: 71fb strb r3, [r7, #7] HAL_GPIO_TogglePin (GPIOD, ledNumber); 8002d6e: 79fb ldrb r3, [r7, #7] 8002d70: b29b uxth r3, r3 8002d72: 4619 mov r1, r3 8002d74: 4803 ldr r0, [pc, #12] @ (8002d84 ) 8002d76: f008 fad4 bl 800b322 } 8002d7a: bf00 nop 8002d7c: 3708 adds r7, #8 8002d7e: 46bd mov sp, r7 8002d80: bd80 pop {r7, pc} 8002d82: bf00 nop 8002d84: 58020c00 .word 0x58020c00 08002d88 : void EnableCurrentSensors (void) { 8002d88: b580 push {r7, lr} 8002d8a: af00 add r7, sp, #0 HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_SET); 8002d8c: 2201 movs r2, #1 8002d8e: f44f 4100 mov.w r1, #32768 @ 0x8000 8002d92: 4802 ldr r0, [pc, #8] @ (8002d9c ) 8002d94: f008 faac bl 800b2f0 } 8002d98: bf00 nop 8002d9a: bd80 pop {r7, pc} 8002d9c: 58021000 .word 0x58021000 08002da0 : void DisableCurrentSensors (void) { HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_RESET); } void SelectCurrentSensorGain (CurrentSensor sensor, CurrentSensorGain gain) { 8002da0: b580 push {r7, lr} 8002da2: b084 sub sp, #16 8002da4: af00 add r7, sp, #0 8002da6: 4603 mov r3, r0 8002da8: 460a mov r2, r1 8002daa: 71fb strb r3, [r7, #7] 8002dac: 4613 mov r3, r2 8002dae: 71bb strb r3, [r7, #6] uint8_t gpioOffset = 0; 8002db0: 2300 movs r3, #0 8002db2: 73fb strb r3, [r7, #15] switch (sensor) { 8002db4: 79fb ldrb r3, [r7, #7] 8002db6: 2b02 cmp r3, #2 8002db8: d00c beq.n 8002dd4 8002dba: 2b02 cmp r3, #2 8002dbc: dc0d bgt.n 8002dda 8002dbe: 2b00 cmp r3, #0 8002dc0: d002 beq.n 8002dc8 8002dc2: 2b01 cmp r3, #1 8002dc4: d003 beq.n 8002dce case CurrentSensorL1: gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET; break; case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break; case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break; default: break; 8002dc6: e008 b.n 8002dda case CurrentSensorL1: gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET; break; 8002dc8: 2307 movs r3, #7 8002dca: 73fb strb r3, [r7, #15] 8002dcc: e006 b.n 8002ddc case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break; 8002dce: 2309 movs r3, #9 8002dd0: 73fb strb r3, [r7, #15] 8002dd2: e003 b.n 8002ddc case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break; 8002dd4: 230d movs r3, #13 8002dd6: 73fb strb r3, [r7, #15] 8002dd8: e000 b.n 8002ddc default: break; 8002dda: bf00 nop } if (gpioOffset > 0) { 8002ddc: 7bfb ldrb r3, [r7, #15] 8002dde: 2b00 cmp r3, #0 8002de0: d023 beq.n 8002e2a uint16_t gain0Gpio = 1 << gpioOffset; 8002de2: 7bfb ldrb r3, [r7, #15] 8002de4: 2201 movs r2, #1 8002de6: fa02 f303 lsl.w r3, r2, r3 8002dea: 81bb strh r3, [r7, #12] uint16_t gain1Gpio = 1 << (gpioOffset + 1); 8002dec: 7bfb ldrb r3, [r7, #15] 8002dee: 3301 adds r3, #1 8002df0: 2201 movs r2, #1 8002df2: fa02 f303 lsl.w r3, r2, r3 8002df6: 817b strh r3, [r7, #10] uint16_t gpioState = ((uint16_t)gain) & 0x0001; 8002df8: 79bb ldrb r3, [r7, #6] 8002dfa: b29b uxth r3, r3 8002dfc: f003 0301 and.w r3, r3, #1 8002e00: 813b strh r3, [r7, #8] HAL_GPIO_WritePin (GPIOE, gain0Gpio, gpioState); 8002e02: 893b ldrh r3, [r7, #8] 8002e04: b2da uxtb r2, r3 8002e06: 89bb ldrh r3, [r7, #12] 8002e08: 4619 mov r1, r3 8002e0a: 480a ldr r0, [pc, #40] @ (8002e34 ) 8002e0c: f008 fa70 bl 800b2f0 gpioState = (((uint16_t)gain) >> 1) & 0x0001; 8002e10: 79bb ldrb r3, [r7, #6] 8002e12: 085b lsrs r3, r3, #1 8002e14: b2db uxtb r3, r3 8002e16: f003 0301 and.w r3, r3, #1 8002e1a: 813b strh r3, [r7, #8] HAL_GPIO_WritePin (GPIOE, gain1Gpio, gpioState); 8002e1c: 893b ldrh r3, [r7, #8] 8002e1e: b2da uxtb r2, r3 8002e20: 897b ldrh r3, [r7, #10] 8002e22: 4619 mov r1, r3 8002e24: 4803 ldr r0, [pc, #12] @ (8002e34 ) 8002e26: f008 fa63 bl 800b2f0 } } 8002e2a: bf00 nop 8002e2c: 3710 adds r7, #16 8002e2e: 46bd mov sp, r7 8002e30: bd80 pop {r7, pc} 8002e32: bf00 nop 8002e34: 58021000 .word 0x58021000 08002e38 : uint8_t MotorControl (TIM_HandleTypeDef* htim, TIM_OC_InitTypeDef* motorTimerConfigOC, uint8_t channel1, uint8_t channel2, osTimerId_t motorTimerHandle, int32_t motorPWMPulse, int32_t motorTimerPeriod, uint8_t switchLimiterUpStat, uint8_t switchLimiterDownStat) { 8002e38: b580 push {r7, lr} 8002e3a: b088 sub sp, #32 8002e3c: af02 add r7, sp, #8 8002e3e: 60f8 str r0, [r7, #12] 8002e40: 60b9 str r1, [r7, #8] 8002e42: 4611 mov r1, r2 8002e44: 461a mov r2, r3 8002e46: 460b mov r3, r1 8002e48: 71fb strb r3, [r7, #7] 8002e4a: 4613 mov r3, r2 8002e4c: 71bb strb r3, [r7, #6] uint32_t motorStatus = 0; 8002e4e: 2300 movs r3, #0 8002e50: 617b str r3, [r7, #20] MotorDriverState setMotorState = HiZ; 8002e52: 2300 movs r3, #0 8002e54: 74fb strb r3, [r7, #19] HAL_TIM_PWM_Stop (htim, channel1); 8002e56: 79fb ldrb r3, [r7, #7] 8002e58: 4619 mov r1, r3 8002e5a: 68f8 ldr r0, [r7, #12] 8002e5c: f00c fbf2 bl 800f644 HAL_TIM_PWM_Stop (htim, channel2); 8002e60: 79bb ldrb r3, [r7, #6] 8002e62: 4619 mov r1, r3 8002e64: 68f8 ldr r0, [r7, #12] 8002e66: f00c fbed bl 800f644 if (motorTimerPeriod > 0) { 8002e6a: 6abb ldr r3, [r7, #40] @ 0x28 8002e6c: 2b00 cmp r3, #0 8002e6e: f340 808c ble.w 8002f8a if (motorPWMPulse > 0) { 8002e72: 6a7b ldr r3, [r7, #36] @ 0x24 8002e74: 2b00 cmp r3, #0 8002e76: dd2c ble.n 8002ed2 // Forward if (switchLimiterUpStat == 0) { 8002e78: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 8002e7c: 2b00 cmp r3, #0 8002e7e: d11d bne.n 8002ebc setMotorState = Forward; 8002e80: 2301 movs r3, #1 8002e82: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 8002e84: 79f9 ldrb r1, [r7, #7] 8002e86: 79b8 ldrb r0, [r7, #6] 8002e88: 6a7b ldr r3, [r7, #36] @ 0x24 8002e8a: ea83 72e3 eor.w r2, r3, r3, asr #31 8002e8e: eba2 72e3 sub.w r2, r2, r3, asr #31 8002e92: 4613 mov r3, r2 8002e94: 009b lsls r3, r3, #2 8002e96: 4413 add r3, r2 8002e98: 005b lsls r3, r3, #1 8002e9a: 9301 str r3, [sp, #4] 8002e9c: 7cfb ldrb r3, [r7, #19] 8002e9e: 9300 str r3, [sp, #0] 8002ea0: 4603 mov r3, r0 8002ea2: 460a mov r2, r1 8002ea4: 68b9 ldr r1, [r7, #8] 8002ea6: 68f8 ldr r0, [r7, #12] 8002ea8: f000 f8ff bl 80030aa HAL_TIM_PWM_Start (htim, channel1); 8002eac: 79fb ldrb r3, [r7, #7] 8002eae: 4619 mov r1, r3 8002eb0: 68f8 ldr r0, [r7, #12] 8002eb2: f00c fab9 bl 800f428 motorStatus = 1; 8002eb6: 2301 movs r3, #1 8002eb8: 617b str r3, [r7, #20] 8002eba: e004 b.n 8002ec6 } else { HAL_TIM_PWM_Stop (htim, channel1); 8002ebc: 79fb ldrb r3, [r7, #7] 8002ebe: 4619 mov r1, r3 8002ec0: 68f8 ldr r0, [r7, #12] 8002ec2: f00c fbbf bl 800f644 } HAL_TIM_PWM_Stop (htim, channel2); 8002ec6: 79bb ldrb r3, [r7, #6] 8002ec8: 4619 mov r1, r3 8002eca: 68f8 ldr r0, [r7, #12] 8002ecc: f00c fbba bl 800f644 8002ed0: e051 b.n 8002f76 } else if (motorPWMPulse < 0) { 8002ed2: 6a7b ldr r3, [r7, #36] @ 0x24 8002ed4: 2b00 cmp r3, #0 8002ed6: da2c bge.n 8002f32 // Reverse if (switchLimiterDownStat == 0) { 8002ed8: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 8002edc: 2b00 cmp r3, #0 8002ede: d11d bne.n 8002f1c setMotorState = Reverse; 8002ee0: 2302 movs r3, #2 8002ee2: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 8002ee4: 79f9 ldrb r1, [r7, #7] 8002ee6: 79b8 ldrb r0, [r7, #6] 8002ee8: 6a7b ldr r3, [r7, #36] @ 0x24 8002eea: ea83 72e3 eor.w r2, r3, r3, asr #31 8002eee: eba2 72e3 sub.w r2, r2, r3, asr #31 8002ef2: 4613 mov r3, r2 8002ef4: 009b lsls r3, r3, #2 8002ef6: 4413 add r3, r2 8002ef8: 005b lsls r3, r3, #1 8002efa: 9301 str r3, [sp, #4] 8002efc: 7cfb ldrb r3, [r7, #19] 8002efe: 9300 str r3, [sp, #0] 8002f00: 4603 mov r3, r0 8002f02: 460a mov r2, r1 8002f04: 68b9 ldr r1, [r7, #8] 8002f06: 68f8 ldr r0, [r7, #12] 8002f08: f000 f8cf bl 80030aa HAL_TIM_PWM_Start (htim, channel2); 8002f0c: 79bb ldrb r3, [r7, #6] 8002f0e: 4619 mov r1, r3 8002f10: 68f8 ldr r0, [r7, #12] 8002f12: f00c fa89 bl 800f428 motorStatus = 1; 8002f16: 2301 movs r3, #1 8002f18: 617b str r3, [r7, #20] 8002f1a: e004 b.n 8002f26 } else { HAL_TIM_PWM_Stop (htim, channel2); 8002f1c: 79bb ldrb r3, [r7, #6] 8002f1e: 4619 mov r1, r3 8002f20: 68f8 ldr r0, [r7, #12] 8002f22: f00c fb8f bl 800f644 } HAL_TIM_PWM_Stop (htim, channel1); 8002f26: 79fb ldrb r3, [r7, #7] 8002f28: 4619 mov r1, r3 8002f2a: 68f8 ldr r0, [r7, #12] 8002f2c: f00c fb8a bl 800f644 8002f30: e021 b.n 8002f76 } else { // Brake setMotorState = Brake; 8002f32: 2303 movs r3, #3 8002f34: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 8002f36: 79f9 ldrb r1, [r7, #7] 8002f38: 79b8 ldrb r0, [r7, #6] 8002f3a: 6a7b ldr r3, [r7, #36] @ 0x24 8002f3c: ea83 72e3 eor.w r2, r3, r3, asr #31 8002f40: eba2 72e3 sub.w r2, r2, r3, asr #31 8002f44: 4613 mov r3, r2 8002f46: 009b lsls r3, r3, #2 8002f48: 4413 add r3, r2 8002f4a: 005b lsls r3, r3, #1 8002f4c: 9301 str r3, [sp, #4] 8002f4e: 7cfb ldrb r3, [r7, #19] 8002f50: 9300 str r3, [sp, #0] 8002f52: 4603 mov r3, r0 8002f54: 460a mov r2, r1 8002f56: 68b9 ldr r1, [r7, #8] 8002f58: 68f8 ldr r0, [r7, #12] 8002f5a: f000 f8a6 bl 80030aa HAL_TIM_PWM_Start (htim, channel1); 8002f5e: 79fb ldrb r3, [r7, #7] 8002f60: 4619 mov r1, r3 8002f62: 68f8 ldr r0, [r7, #12] 8002f64: f00c fa60 bl 800f428 HAL_TIM_PWM_Start (htim, channel2); 8002f68: 79bb ldrb r3, [r7, #6] 8002f6a: 4619 mov r1, r3 8002f6c: 68f8 ldr r0, [r7, #12] 8002f6e: f00c fa5b bl 800f428 motorStatus = 0; 8002f72: 2300 movs r3, #0 8002f74: 617b str r3, [r7, #20] } osTimerStart (motorTimerHandle, motorTimerPeriod * 1000); 8002f76: 6abb ldr r3, [r7, #40] @ 0x28 8002f78: f44f 727a mov.w r2, #1000 @ 0x3e8 8002f7c: fb02 f303 mul.w r3, r2, r3 8002f80: 4619 mov r1, r3 8002f82: 6a38 ldr r0, [r7, #32] 8002f84: f010 fc66 bl 8013854 8002f88: e089 b.n 800309e } else if ((motorTimerPeriod == 0) && (motorPWMPulse == 0)) { 8002f8a: 6abb ldr r3, [r7, #40] @ 0x28 8002f8c: 2b00 cmp r3, #0 8002f8e: d126 bne.n 8002fde 8002f90: 6a7b ldr r3, [r7, #36] @ 0x24 8002f92: 2b00 cmp r3, #0 8002f94: d123 bne.n 8002fde MotorAction (htim, motorTimerConfigOC, channel1, channel2, HiZ, abs (motorPWMPulse) * 10); 8002f96: 79f9 ldrb r1, [r7, #7] 8002f98: 79b8 ldrb r0, [r7, #6] 8002f9a: 6a7b ldr r3, [r7, #36] @ 0x24 8002f9c: ea83 72e3 eor.w r2, r3, r3, asr #31 8002fa0: eba2 72e3 sub.w r2, r2, r3, asr #31 8002fa4: 4613 mov r3, r2 8002fa6: 009b lsls r3, r3, #2 8002fa8: 4413 add r3, r2 8002faa: 005b lsls r3, r3, #1 8002fac: 9301 str r3, [sp, #4] 8002fae: 2300 movs r3, #0 8002fb0: 9300 str r3, [sp, #0] 8002fb2: 4603 mov r3, r0 8002fb4: 460a mov r2, r1 8002fb6: 68b9 ldr r1, [r7, #8] 8002fb8: 68f8 ldr r0, [r7, #12] 8002fba: f000 f876 bl 80030aa HAL_TIM_PWM_Stop (htim, channel1); 8002fbe: 79fb ldrb r3, [r7, #7] 8002fc0: 4619 mov r1, r3 8002fc2: 68f8 ldr r0, [r7, #12] 8002fc4: f00c fb3e bl 800f644 HAL_TIM_PWM_Stop (htim, channel2); 8002fc8: 79bb ldrb r3, [r7, #6] 8002fca: 4619 mov r1, r3 8002fcc: 68f8 ldr r0, [r7, #12] 8002fce: f00c fb39 bl 800f644 osTimerStop (motorTimerHandle); 8002fd2: 6a38 ldr r0, [r7, #32] 8002fd4: f010 fc6c bl 80138b0 motorStatus = 0; 8002fd8: 2300 movs r3, #0 8002fda: 617b str r3, [r7, #20] 8002fdc: e05f b.n 800309e } else if (motorTimerPeriod == -1) { 8002fde: 6abb ldr r3, [r7, #40] @ 0x28 8002fe0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8002fe4: d15b bne.n 800309e if (motorPWMPulse > 0) { 8002fe6: 6a7b ldr r3, [r7, #36] @ 0x24 8002fe8: 2b00 cmp r3, #0 8002fea: dd2c ble.n 8003046 // Forward if (switchLimiterUpStat == 0) { 8002fec: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 8002ff0: 2b00 cmp r3, #0 8002ff2: d11d bne.n 8003030 setMotorState = Forward; 8002ff4: 2301 movs r3, #1 8002ff6: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 8002ff8: 79f9 ldrb r1, [r7, #7] 8002ffa: 79b8 ldrb r0, [r7, #6] 8002ffc: 6a7b ldr r3, [r7, #36] @ 0x24 8002ffe: ea83 72e3 eor.w r2, r3, r3, asr #31 8003002: eba2 72e3 sub.w r2, r2, r3, asr #31 8003006: 4613 mov r3, r2 8003008: 009b lsls r3, r3, #2 800300a: 4413 add r3, r2 800300c: 005b lsls r3, r3, #1 800300e: 9301 str r3, [sp, #4] 8003010: 7cfb ldrb r3, [r7, #19] 8003012: 9300 str r3, [sp, #0] 8003014: 4603 mov r3, r0 8003016: 460a mov r2, r1 8003018: 68b9 ldr r1, [r7, #8] 800301a: 68f8 ldr r0, [r7, #12] 800301c: f000 f845 bl 80030aa HAL_TIM_PWM_Start (htim, channel1); 8003020: 79fb ldrb r3, [r7, #7] 8003022: 4619 mov r1, r3 8003024: 68f8 ldr r0, [r7, #12] 8003026: f00c f9ff bl 800f428 motorStatus = 1; 800302a: 2301 movs r3, #1 800302c: 617b str r3, [r7, #20] 800302e: e004 b.n 800303a } else { HAL_TIM_PWM_Stop (htim, channel1); 8003030: 79fb ldrb r3, [r7, #7] 8003032: 4619 mov r1, r3 8003034: 68f8 ldr r0, [r7, #12] 8003036: f00c fb05 bl 800f644 } HAL_TIM_PWM_Stop (htim, channel2); 800303a: 79bb ldrb r3, [r7, #6] 800303c: 4619 mov r1, r3 800303e: 68f8 ldr r0, [r7, #12] 8003040: f00c fb00 bl 800f644 8003044: e02b b.n 800309e } else { // Reverse if (switchLimiterDownStat == 0) { 8003046: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 800304a: 2b00 cmp r3, #0 800304c: d11d bne.n 800308a setMotorState = Reverse; 800304e: 2302 movs r3, #2 8003050: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 8003052: 79f9 ldrb r1, [r7, #7] 8003054: 79b8 ldrb r0, [r7, #6] 8003056: 6a7b ldr r3, [r7, #36] @ 0x24 8003058: ea83 72e3 eor.w r2, r3, r3, asr #31 800305c: eba2 72e3 sub.w r2, r2, r3, asr #31 8003060: 4613 mov r3, r2 8003062: 009b lsls r3, r3, #2 8003064: 4413 add r3, r2 8003066: 005b lsls r3, r3, #1 8003068: 9301 str r3, [sp, #4] 800306a: 7cfb ldrb r3, [r7, #19] 800306c: 9300 str r3, [sp, #0] 800306e: 4603 mov r3, r0 8003070: 460a mov r2, r1 8003072: 68b9 ldr r1, [r7, #8] 8003074: 68f8 ldr r0, [r7, #12] 8003076: f000 f818 bl 80030aa HAL_TIM_PWM_Start (htim, channel2); 800307a: 79bb ldrb r3, [r7, #6] 800307c: 4619 mov r1, r3 800307e: 68f8 ldr r0, [r7, #12] 8003080: f00c f9d2 bl 800f428 motorStatus = 1; 8003084: 2301 movs r3, #1 8003086: 617b str r3, [r7, #20] 8003088: e004 b.n 8003094 } else { HAL_TIM_PWM_Stop (htim, channel2); 800308a: 79bb ldrb r3, [r7, #6] 800308c: 4619 mov r1, r3 800308e: 68f8 ldr r0, [r7, #12] 8003090: f00c fad8 bl 800f644 } HAL_TIM_PWM_Stop (htim, channel1); 8003094: 79fb ldrb r3, [r7, #7] 8003096: 4619 mov r1, r3 8003098: 68f8 ldr r0, [r7, #12] 800309a: f00c fad3 bl 800f644 } } return motorStatus; 800309e: 697b ldr r3, [r7, #20] 80030a0: b2db uxtb r3, r3 } 80030a2: 4618 mov r0, r3 80030a4: 3718 adds r7, #24 80030a6: 46bd mov sp, r7 80030a8: bd80 pop {r7, pc} 080030aa : void MotorAction (TIM_HandleTypeDef* tim, TIM_OC_InitTypeDef* timerConf, uint32_t channel1, uint32_t channel2, MotorDriverState setState, uint32_t pulse) { 80030aa: b580 push {r7, lr} 80030ac: b084 sub sp, #16 80030ae: af00 add r7, sp, #0 80030b0: 60f8 str r0, [r7, #12] 80030b2: 60b9 str r1, [r7, #8] 80030b4: 607a str r2, [r7, #4] 80030b6: 603b str r3, [r7, #0] timerConf->Pulse = pulse; 80030b8: 68bb ldr r3, [r7, #8] 80030ba: 69fa ldr r2, [r7, #28] 80030bc: 605a str r2, [r3, #4] switch (setState) { 80030be: 7e3b ldrb r3, [r7, #24] 80030c0: 2b02 cmp r3, #2 80030c2: dc02 bgt.n 80030ca 80030c4: 2b00 cmp r3, #0 80030c6: da03 bge.n 80030d0 80030c8: e038 b.n 800313c 80030ca: 2b03 cmp r3, #3 80030cc: d01b beq.n 8003106 80030ce: e035 b.n 800313c case Forward: case Reverse: case HiZ: timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 80030d0: 68bb ldr r3, [r7, #8] 80030d2: 2200 movs r2, #0 80030d4: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 80030d6: 687a ldr r2, [r7, #4] 80030d8: 68b9 ldr r1, [r7, #8] 80030da: 68f8 ldr r0, [r7, #12] 80030dc: f00c fc50 bl 800f980 80030e0: 4603 mov r3, r0 80030e2: 2b00 cmp r3, #0 80030e4: d001 beq.n 80030ea Error_Handler (); 80030e6: f7fe fd71 bl 8001bcc } timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 80030ea: 68bb ldr r3, [r7, #8] 80030ec: 2200 movs r2, #0 80030ee: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80030f0: 683a ldr r2, [r7, #0] 80030f2: 68b9 ldr r1, [r7, #8] 80030f4: 68f8 ldr r0, [r7, #12] 80030f6: f00c fc43 bl 800f980 80030fa: 4603 mov r3, r0 80030fc: 2b00 cmp r3, #0 80030fe: d038 beq.n 8003172 Error_Handler (); 8003100: f7fe fd64 bl 8001bcc } break; 8003104: e035 b.n 8003172 case Brake: timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 8003106: 68bb ldr r3, [r7, #8] 8003108: 2202 movs r2, #2 800310a: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 800310c: 687a ldr r2, [r7, #4] 800310e: 68b9 ldr r1, [r7, #8] 8003110: 68f8 ldr r0, [r7, #12] 8003112: f00c fc35 bl 800f980 8003116: 4603 mov r3, r0 8003118: 2b00 cmp r3, #0 800311a: d001 beq.n 8003120 Error_Handler (); 800311c: f7fe fd56 bl 8001bcc } timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 8003120: 68bb ldr r3, [r7, #8] 8003122: 2202 movs r2, #2 8003124: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 8003126: 683a ldr r2, [r7, #0] 8003128: 68b9 ldr r1, [r7, #8] 800312a: 68f8 ldr r0, [r7, #12] 800312c: f00c fc28 bl 800f980 8003130: 4603 mov r3, r0 8003132: 2b00 cmp r3, #0 8003134: d01f beq.n 8003176 Error_Handler (); 8003136: f7fe fd49 bl 8001bcc } break; 800313a: e01c b.n 8003176 default: timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 800313c: 68bb ldr r3, [r7, #8] 800313e: 2200 movs r2, #0 8003140: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 8003142: 687a ldr r2, [r7, #4] 8003144: 68b9 ldr r1, [r7, #8] 8003146: 68f8 ldr r0, [r7, #12] 8003148: f00c fc1a bl 800f980 800314c: 4603 mov r3, r0 800314e: 2b00 cmp r3, #0 8003150: d001 beq.n 8003156 Error_Handler (); 8003152: f7fe fd3b bl 8001bcc } timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8003156: 68bb ldr r3, [r7, #8] 8003158: 2200 movs r2, #0 800315a: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 800315c: 683a ldr r2, [r7, #0] 800315e: 68b9 ldr r1, [r7, #8] 8003160: 68f8 ldr r0, [r7, #12] 8003162: f00c fc0d bl 800f980 8003166: 4603 mov r3, r0 8003168: 2b00 cmp r3, #0 800316a: d006 beq.n 800317a Error_Handler (); 800316c: f7fe fd2e bl 8001bcc } break; 8003170: e003 b.n 800317a break; 8003172: bf00 nop 8003174: e002 b.n 800317c break; 8003176: bf00 nop 8003178: e000 b.n 800317c break; 800317a: bf00 nop } } 800317c: bf00 nop 800317e: 3710 adds r7, #16 8003180: 46bd mov sp, r7 8003182: bd80 pop {r7, pc} 08003184 : extern osTimerId_t motorXTimerHandle; extern osTimerId_t motorYTimerHandle; extern TIM_HandleTypeDef htim3; extern TIM_OC_InitTypeDef motorXYTimerConfigOC; void PositionControlTaskInit (void) { 8003184: b580 push {r7, lr} 8003186: b08a sub sp, #40 @ 0x28 8003188: af00 add r7, sp, #0 // positionSettingMutex = osMutexNew (NULL); osThreadAttr_t osThreadAttrPositionControlTask = { 0 }; 800318a: 1d3b adds r3, r7, #4 800318c: 2224 movs r2, #36 @ 0x24 800318e: 2100 movs r1, #0 8003190: 4618 mov r0, r3 8003192: f014 fd7b bl 8017c8c osThreadAttrPositionControlTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8003196: f44f 6380 mov.w r3, #1024 @ 0x400 800319a: 61bb str r3, [r7, #24] osThreadAttrPositionControlTask.priority = (osPriority_t)osPriorityNormal; 800319c: 2318 movs r3, #24 800319e: 61fb str r3, [r7, #28] positionXControlTaskInitArg.channel1 = TIM_CHANNEL_1; 80031a0: 4b3b ldr r3, [pc, #236] @ (8003290 ) 80031a2: 2200 movs r2, #0 80031a4: 721a strb r2, [r3, #8] positionXControlTaskInitArg.channel2 = TIM_CHANNEL_2; 80031a6: 4b3a ldr r3, [pc, #232] @ (8003290 ) 80031a8: 2204 movs r2, #4 80031aa: 725a strb r2, [r3, #9] positionXControlTaskInitArg.htim = &htim3; 80031ac: 4b38 ldr r3, [pc, #224] @ (8003290 ) 80031ae: 4a39 ldr r2, [pc, #228] @ (8003294 ) 80031b0: 601a str r2, [r3, #0] positionXControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC; 80031b2: 4b37 ldr r3, [pc, #220] @ (8003290 ) 80031b4: 4a38 ldr r2, [pc, #224] @ (8003298 ) 80031b6: 605a str r2, [r3, #4] positionXControlTaskInitArg.motorTimerHandle = motorXTimerHandle; 80031b8: 4b38 ldr r3, [pc, #224] @ (800329c ) 80031ba: 681b ldr r3, [r3, #0] 80031bc: 4a34 ldr r2, [pc, #208] @ (8003290 ) 80031be: 60d3 str r3, [r2, #12] positionXControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 80031c0: 2200 movs r2, #0 80031c2: 2104 movs r1, #4 80031c4: 2010 movs r0, #16 80031c6: f010 fcb8 bl 8013b3a 80031ca: 4603 mov r3, r0 80031cc: 4a30 ldr r2, [pc, #192] @ (8003290 ) 80031ce: 6113 str r3, [r2, #16] positionXControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitXSwitchCenter); 80031d0: 4b2f ldr r3, [pc, #188] @ (8003290 ) 80031d2: 4a33 ldr r2, [pc, #204] @ (80032a0 ) 80031d4: 61da str r2, [r3, #28] positionXControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitXSwitchUp); 80031d6: 4b2e ldr r3, [pc, #184] @ (8003290 ) 80031d8: 4a32 ldr r2, [pc, #200] @ (80032a4 ) 80031da: 615a str r2, [r3, #20] positionXControlTaskInitArg.switchLimiterDownStat = &(sensorsInfo.limitXSwitchDown); 80031dc: 4b2c ldr r3, [pc, #176] @ (8003290 ) 80031de: 4a32 ldr r2, [pc, #200] @ (80032a8 ) 80031e0: 619a str r2, [r3, #24] positionXControlTaskInitArg.currentPosition = &(sensorsInfo.currentXPosition); 80031e2: 4b2b ldr r3, [pc, #172] @ (8003290 ) 80031e4: 4a31 ldr r2, [pc, #196] @ (80032ac ) 80031e6: 621a str r2, [r3, #32] positionXControlTaskInitArg.motorStatus = &(sensorsInfo.motorXStatus); 80031e8: 4b29 ldr r3, [pc, #164] @ (8003290 ) 80031ea: 4a31 ldr r2, [pc, #196] @ (80032b0 ) 80031ec: 629a str r2, [r3, #40] @ 0x28 positionXControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorXPeakCurrent); 80031ee: 4b28 ldr r3, [pc, #160] @ (8003290 ) 80031f0: 4a30 ldr r2, [pc, #192] @ (80032b4 ) 80031f2: 62da str r2, [r3, #44] @ 0x2c positionXControlTaskInitArg.positionSetting = &positionXSetting; 80031f4: 4b26 ldr r3, [pc, #152] @ (8003290 ) 80031f6: 4a30 ldr r2, [pc, #192] @ (80032b8 ) 80031f8: 625a str r2, [r3, #36] @ 0x24 positionXControlTaskInitArg.axe = 'X'; 80031fa: 4b25 ldr r3, [pc, #148] @ (8003290 ) 80031fc: 2258 movs r2, #88 @ 0x58 80031fe: f883 2030 strb.w r2, [r3, #48] @ 0x30 positionYControlTaskInitArg.channel1 = TIM_CHANNEL_3; 8003202: 4b2e ldr r3, [pc, #184] @ (80032bc ) 8003204: 2208 movs r2, #8 8003206: 721a strb r2, [r3, #8] positionYControlTaskInitArg.channel2 = TIM_CHANNEL_4; 8003208: 4b2c ldr r3, [pc, #176] @ (80032bc ) 800320a: 220c movs r2, #12 800320c: 725a strb r2, [r3, #9] positionYControlTaskInitArg.htim = &htim3; 800320e: 4b2b ldr r3, [pc, #172] @ (80032bc ) 8003210: 4a20 ldr r2, [pc, #128] @ (8003294 ) 8003212: 601a str r2, [r3, #0] positionYControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC; 8003214: 4b29 ldr r3, [pc, #164] @ (80032bc ) 8003216: 4a20 ldr r2, [pc, #128] @ (8003298 ) 8003218: 605a str r2, [r3, #4] positionYControlTaskInitArg.motorTimerHandle = motorYTimerHandle; 800321a: 4b29 ldr r3, [pc, #164] @ (80032c0 ) 800321c: 681b ldr r3, [r3, #0] 800321e: 4a27 ldr r2, [pc, #156] @ (80032bc ) 8003220: 60d3 str r3, [r2, #12] positionYControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 8003222: 2200 movs r2, #0 8003224: 2104 movs r1, #4 8003226: 2010 movs r0, #16 8003228: f010 fc87 bl 8013b3a 800322c: 4603 mov r3, r0 800322e: 4a23 ldr r2, [pc, #140] @ (80032bc ) 8003230: 6113 str r3, [r2, #16] positionYControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitYSwitchCenter); 8003232: 4b22 ldr r3, [pc, #136] @ (80032bc ) 8003234: 4a23 ldr r2, [pc, #140] @ (80032c4 ) 8003236: 61da str r2, [r3, #28] positionYControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitYSwitchUp); 8003238: 4b20 ldr r3, [pc, #128] @ (80032bc ) 800323a: 4a23 ldr r2, [pc, #140] @ (80032c8 ) 800323c: 615a str r2, [r3, #20] positionYControlTaskInitArg.switchLimiterDownStat = &(sensorsInfo.limitYSwitchDown); 800323e: 4b1f ldr r3, [pc, #124] @ (80032bc ) 8003240: 4a22 ldr r2, [pc, #136] @ (80032cc ) 8003242: 619a str r2, [r3, #24] positionYControlTaskInitArg.currentPosition = &(sensorsInfo.currentYPosition); 8003244: 4b1d ldr r3, [pc, #116] @ (80032bc ) 8003246: 4a22 ldr r2, [pc, #136] @ (80032d0 ) 8003248: 621a str r2, [r3, #32] positionYControlTaskInitArg.motorStatus = &(sensorsInfo.motorYStatus); 800324a: 4b1c ldr r3, [pc, #112] @ (80032bc ) 800324c: 4a21 ldr r2, [pc, #132] @ (80032d4 ) 800324e: 629a str r2, [r3, #40] @ 0x28 positionYControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorYPeakCurrent); 8003250: 4b1a ldr r3, [pc, #104] @ (80032bc ) 8003252: 4a21 ldr r2, [pc, #132] @ (80032d8 ) 8003254: 62da str r2, [r3, #44] @ 0x2c positionXControlTaskInitArg.positionSetting = &positionYSetting; 8003256: 4b0e ldr r3, [pc, #56] @ (8003290 ) 8003258: 4a20 ldr r2, [pc, #128] @ (80032dc ) 800325a: 625a str r2, [r3, #36] @ 0x24 positionYControlTaskInitArg.axe = 'Y'; 800325c: 4b17 ldr r3, [pc, #92] @ (80032bc ) 800325e: 2259 movs r2, #89 @ 0x59 8003260: f883 2030 strb.w r2, [r3, #48] @ 0x30 positionXControlTaskHandle = osThreadNew (PositionControlTask, &positionXControlTaskInitArg, &osThreadAttrPositionControlTask); 8003264: 1d3b adds r3, r7, #4 8003266: 461a mov r2, r3 8003268: 4909 ldr r1, [pc, #36] @ (8003290 ) 800326a: 481d ldr r0, [pc, #116] @ (80032e0 ) 800326c: f010 f9b2 bl 80135d4 8003270: 4603 mov r3, r0 8003272: 4a1c ldr r2, [pc, #112] @ (80032e4 ) 8003274: 6013 str r3, [r2, #0] positionYControlTaskHandle = osThreadNew (PositionControlTask, &positionYControlTaskInitArg, &osThreadAttrPositionControlTask); 8003276: 1d3b adds r3, r7, #4 8003278: 461a mov r2, r3 800327a: 4910 ldr r1, [pc, #64] @ (80032bc ) 800327c: 4818 ldr r0, [pc, #96] @ (80032e0 ) 800327e: f010 f9a9 bl 80135d4 8003282: 4603 mov r3, r0 8003284: 4a18 ldr r2, [pc, #96] @ (80032e8 ) 8003286: 6013 str r3, [r2, #0] } 8003288: bf00 nop 800328a: 3728 adds r7, #40 @ 0x28 800328c: 46bd mov sp, r7 800328e: bd80 pop {r7, pc} 8003290: 240008c0 .word 0x240008c0 8003294: 24000498 .word 0x24000498 8003298: 24000738 .word 0x24000738 800329c: 240006bc .word 0x240006bc 80032a0: 2400080a .word 0x2400080a 80032a4: 24000808 .word 0x24000808 80032a8: 24000809 .word 0x24000809 80032ac: 24000810 .word 0x24000810 80032b0: 240007f4 .word 0x240007f4 80032b4: 24000800 .word 0x24000800 80032b8: 24000880 .word 0x24000880 80032bc: 24000900 .word 0x24000900 80032c0: 240006ec .word 0x240006ec 80032c4: 2400080d .word 0x2400080d 80032c8: 2400080b .word 0x2400080b 80032cc: 2400080c .word 0x2400080c 80032d0: 24000814 .word 0x24000814 80032d4: 240007f5 .word 0x240007f5 80032d8: 24000804 .word 0x24000804 80032dc: 240008a0 .word 0x240008a0 80032e0: 080032ed .word 0x080032ed 80032e4: 240008a4 .word 0x240008a4 80032e8: 240008a8 .word 0x240008a8 080032ec : void PositionControlTask (void* argument) { 80032ec: b5f0 push {r4, r5, r6, r7, lr} 80032ee: b09f sub sp, #124 @ 0x7c 80032f0: af06 add r7, sp, #24 80032f2: 6078 str r0, [r7, #4] 80032f4: f107 0360 add.w r3, r7, #96 @ 0x60 80032f8: 3b58 subs r3, #88 @ 0x58 80032fa: 331f adds r3, #31 80032fc: 095b lsrs r3, r3, #5 80032fe: 015c lsls r4, r3, #5 const int32_t PositionControlTaskTimeOut = 100; 8003300: 2364 movs r3, #100 @ 0x64 8003302: 643b str r3, [r7, #64] @ 0x40 PositionControlTaskInitArg* posCtrlTaskArg = (PositionControlTaskInitArg*)argument; 8003304: 687b ldr r3, [r7, #4] 8003306: 63fb str r3, [r7, #60] @ 0x3c PositionControlTaskData posCtrlData __attribute__ ((aligned (32))) = { 0 }; 8003308: f04f 0300 mov.w r3, #0 800330c: 6023 str r3, [r4, #0] uint32_t motorStatus = 0; 800330e: 2300 movs r3, #0 8003310: 63bb str r3, [r7, #56] @ 0x38 osStatus_t queueSatus; int32_t pwmValue = MOTOR_START_STOP_PWM_VALUE; 8003312: 233c movs r3, #60 @ 0x3c 8003314: 65fb str r3, [r7, #92] @ 0x5c int32_t sign = 0; 8003316: 2300 movs r3, #0 8003318: 65bb str r3, [r7, #88] @ 0x58 MovementPhases movementPhase = idlePhase; 800331a: 2300 movs r3, #0 800331c: f887 3057 strb.w r3, [r7, #87] @ 0x57 float startPosition = 0; 8003320: f04f 0300 mov.w r3, #0 8003324: 653b str r3, [r7, #80] @ 0x50 float prevPosition = 0; 8003326: f04f 0300 mov.w r3, #0 800332a: 64fb str r3, [r7, #76] @ 0x4c int32_t timeLeftMS = 0; 800332c: 2300 movs r3, #0 800332e: 64bb str r3, [r7, #72] @ 0x48 int32_t moveCmdTimeoutCounter = 0; 8003330: 2300 movs r3, #0 8003332: 647b str r3, [r7, #68] @ 0x44 while (pdTRUE) { queueSatus = osMessageQueueGet (posCtrlTaskArg->positionSettingQueue, &posCtrlData, 0, pdMS_TO_TICKS (PositionControlTaskTimeOut)); 8003334: 6bfb ldr r3, [r7, #60] @ 0x3c 8003336: 6918 ldr r0, [r3, #16] 8003338: 6c3b ldr r3, [r7, #64] @ 0x40 800333a: f44f 727a mov.w r2, #1000 @ 0x3e8 800333e: fb02 f303 mul.w r3, r2, r3 8003342: 4a86 ldr r2, [pc, #536] @ (800355c ) 8003344: fba2 2303 umull r2, r3, r2, r3 8003348: 099b lsrs r3, r3, #6 800334a: 2200 movs r2, #0 800334c: 4621 mov r1, r4 800334e: f010 fcc7 bl 8013ce0 8003352: 6378 str r0, [r7, #52] @ 0x34 if (queueSatus == osOK) { 8003354: 6b7b ldr r3, [r7, #52] @ 0x34 8003356: 2b00 cmp r3, #0 8003358: d142 bne.n 80033e0 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800335a: 4b81 ldr r3, [pc, #516] @ (8003560 ) 800335c: 681b ldr r3, [r3, #0] 800335e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003362: 4618 mov r0, r3 8003364: f010 fb61 bl 8013a2a 8003368: 4603 mov r3, r0 800336a: 2b00 cmp r3, #0 800336c: d1e2 bne.n 8003334 float posDiff = posCtrlData.positionSettingValue - *posCtrlTaskArg->currentPosition; 800336e: ed94 7a00 vldr s14, [r4] 8003372: 6bfb ldr r3, [r7, #60] @ 0x3c 8003374: 6a1b ldr r3, [r3, #32] 8003376: edd3 7a00 vldr s15, [r3] 800337a: ee77 7a67 vsub.f32 s15, s14, s15 800337e: edc7 7a0b vstr s15, [r7, #44] @ 0x2c if (posDiff != 0) { 8003382: edd7 7a0b vldr s15, [r7, #44] @ 0x2c 8003386: eef5 7a40 vcmp.f32 s15, #0.0 800338a: eef1 fa10 vmrs APSR_nzcv, fpscr 800338e: d01d beq.n 80033cc sign = posDiff > 0 ? 1 : -1; 8003390: edd7 7a0b vldr s15, [r7, #44] @ 0x2c 8003394: eef5 7ac0 vcmpe.f32 s15, #0.0 8003398: eef1 fa10 vmrs APSR_nzcv, fpscr 800339c: dd01 ble.n 80033a2 800339e: 2301 movs r3, #1 80033a0: e001 b.n 80033a6 80033a2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80033a6: 65bb str r3, [r7, #88] @ 0x58 startPosition = *posCtrlTaskArg->currentPosition; 80033a8: 6bfb ldr r3, [r7, #60] @ 0x3c 80033aa: 6a1b ldr r3, [r3, #32] 80033ac: 681b ldr r3, [r3, #0] 80033ae: 653b str r3, [r7, #80] @ 0x50 movementPhase = startPhase; 80033b0: 2301 movs r3, #1 80033b2: f887 3057 strb.w r3, [r7, #87] @ 0x57 moveCmdTimeoutCounter = 0; 80033b6: 2300 movs r3, #0 80033b8: 647b str r3, [r7, #68] @ 0x44 timeLeftMS = 0; 80033ba: 2300 movs r3, #0 80033bc: 64bb str r3, [r7, #72] @ 0x48 #ifdef DBG_POSITION printf ("Axe %c start phase\n", posCtrlTaskArg->axe); 80033be: 6bfb ldr r3, [r7, #60] @ 0x3c 80033c0: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 80033c4: 4619 mov r1, r3 80033c6: 4867 ldr r0, [pc, #412] @ (8003564 ) 80033c8: f014 fb18 bl 80179fc #endif } osMutexRelease (sensorsInfoMutex); 80033cc: 4b64 ldr r3, [pc, #400] @ (8003560 ) 80033ce: 681b ldr r3, [r3, #0] 80033d0: 4618 mov r0, r3 80033d2: f010 fb75 bl 8013ac0 // if (osMutexAcquire (positionSettingMutex, osWaitForever) == osOK) { *positionXControlTaskInitArg.positionSetting = posCtrlData.positionSettingValue; 80033d6: 4b64 ldr r3, [pc, #400] @ (8003568 ) 80033d8: 6a5b ldr r3, [r3, #36] @ 0x24 80033da: 6822 ldr r2, [r4, #0] 80033dc: 601a str r2, [r3, #0] 80033de: e7a9 b.n 8003334 // osMutexRelease (positionSettingMutex); // } } } else if (queueSatus == osErrorTimeout) { 80033e0: 6b7b ldr r3, [r7, #52] @ 0x34 80033e2: f113 0f02 cmn.w r3, #2 80033e6: d1a5 bne.n 8003334 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80033e8: 4b5d ldr r3, [pc, #372] @ (8003560 ) 80033ea: 681b ldr r3, [r3, #0] 80033ec: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80033f0: 4618 mov r0, r3 80033f2: f010 fb1a bl 8013a2a 80033f6: 4603 mov r3, r0 80033f8: 2b00 cmp r3, #0 80033fa: d19b bne.n 8003334 if (((*posCtrlTaskArg->motorStatus != 0) && (movementPhase != idlePhase)) || (movementPhase == startPhase) ) { 80033fc: 6bfb ldr r3, [r7, #60] @ 0x3c 80033fe: 6a9b ldr r3, [r3, #40] @ 0x28 8003400: 781b ldrb r3, [r3, #0] 8003402: 2b00 cmp r3, #0 8003404: d003 beq.n 800340e 8003406: f897 3057 ldrb.w r3, [r7, #87] @ 0x57 800340a: 2b00 cmp r3, #0 800340c: d104 bne.n 8003418 800340e: f897 3057 ldrb.w r3, [r7, #87] @ 0x57 8003412: 2b01 cmp r3, #1 8003414: f040 8208 bne.w 8003828 if (((*posCtrlTaskArg->switchLimiterDownStat == 1) && (*posCtrlTaskArg->switchLimiterUpStat == 1)) || 8003418: 6bfb ldr r3, [r7, #60] @ 0x3c 800341a: 699b ldr r3, [r3, #24] 800341c: 781b ldrb r3, [r3, #0] 800341e: 2b01 cmp r3, #1 8003420: d104 bne.n 800342c 8003422: 6bfb ldr r3, [r7, #60] @ 0x3c 8003424: 695b ldr r3, [r3, #20] 8003426: 781b ldrb r3, [r3, #0] 8003428: 2b01 cmp r3, #1 800342a: d009 beq.n 8003440 ((*posCtrlTaskArg->switchLimiterUpStat == 1) && (*posCtrlTaskArg->switchLimiterCenterStat == 1))) { 800342c: 6bfb ldr r3, [r7, #60] @ 0x3c 800342e: 695b ldr r3, [r3, #20] 8003430: 781b ldrb r3, [r3, #0] if (((*posCtrlTaskArg->switchLimiterDownStat == 1) && (*posCtrlTaskArg->switchLimiterUpStat == 1)) || 8003432: 2b01 cmp r3, #1 8003434: d132 bne.n 800349c ((*posCtrlTaskArg->switchLimiterUpStat == 1) && (*posCtrlTaskArg->switchLimiterCenterStat == 1))) { 8003436: 6bfb ldr r3, [r7, #60] @ 0x3c 8003438: 69db ldr r3, [r3, #28] 800343a: 781b ldrb r3, [r3, #0] 800343c: 2b01 cmp r3, #1 800343e: d12d bne.n 800349c movementPhase = idlePhase; 8003440: 2300 movs r3, #0 8003442: f887 3057 strb.w r3, [r7, #87] @ 0x57 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 8003446: 6bfb ldr r3, [r7, #60] @ 0x3c 8003448: 6818 ldr r0, [r3, #0] 800344a: 6bfb ldr r3, [r7, #60] @ 0x3c 800344c: 685d ldr r5, [r3, #4] 800344e: 6bfb ldr r3, [r7, #60] @ 0x3c 8003450: 7a1e ldrb r6, [r3, #8] 8003452: 6bfb ldr r3, [r7, #60] @ 0x3c 8003454: f893 c009 ldrb.w ip, [r3, #9] 8003458: 6bfb ldr r3, [r7, #60] @ 0x3c 800345a: 68db ldr r3, [r3, #12] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 800345c: 6bfa ldr r2, [r7, #60] @ 0x3c 800345e: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 8003460: 7812 ldrb r2, [r2, #0] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003462: 6bf9 ldr r1, [r7, #60] @ 0x3c 8003464: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 8003466: 7809 ldrb r1, [r1, #0] 8003468: 9104 str r1, [sp, #16] 800346a: 9203 str r2, [sp, #12] 800346c: 2200 movs r2, #0 800346e: 9202 str r2, [sp, #8] 8003470: 2200 movs r2, #0 8003472: 9201 str r2, [sp, #4] 8003474: 9300 str r3, [sp, #0] 8003476: 4663 mov r3, ip 8003478: 4632 mov r2, r6 800347a: 4629 mov r1, r5 800347c: f7ff fcdc bl 8002e38 8003480: 4603 mov r3, r0 8003482: 63bb str r3, [r7, #56] @ 0x38 *posCtrlTaskArg->motorStatus = motorStatus; 8003484: 6bfb ldr r3, [r7, #60] @ 0x3c 8003486: 6a9b ldr r3, [r3, #40] @ 0x28 8003488: 6bba ldr r2, [r7, #56] @ 0x38 800348a: b2d2 uxtb r2, r2 800348c: 701a strb r2, [r3, #0] #ifdef DBG_POSITION printf ("Axe %c limiters wrong state - idle phase\n", posCtrlTaskArg->axe); 800348e: 6bfb ldr r3, [r7, #60] @ 0x3c 8003490: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 8003494: 4619 mov r1, r3 8003496: 4835 ldr r0, [pc, #212] @ (800356c ) 8003498: f014 fab0 bl 80179fc #endif } timeLeftMS += PositionControlTaskTimeOut; 800349c: 6cba ldr r2, [r7, #72] @ 0x48 800349e: 6c3b ldr r3, [r7, #64] @ 0x40 80034a0: 4413 add r3, r2 80034a2: 64bb str r3, [r7, #72] @ 0x48 if (prevPosition == *posCtrlTaskArg->currentPosition) { 80034a4: 6bfb ldr r3, [r7, #60] @ 0x3c 80034a6: 6a1b ldr r3, [r3, #32] 80034a8: edd3 7a00 vldr s15, [r3] 80034ac: ed97 7a13 vldr s14, [r7, #76] @ 0x4c 80034b0: eeb4 7a67 vcmp.f32 s14, s15 80034b4: eef1 fa10 vmrs APSR_nzcv, fpscr 80034b8: d104 bne.n 80034c4 moveCmdTimeoutCounter += PositionControlTaskTimeOut; 80034ba: 6c7a ldr r2, [r7, #68] @ 0x44 80034bc: 6c3b ldr r3, [r7, #64] @ 0x40 80034be: 4413 add r3, r2 80034c0: 647b str r3, [r7, #68] @ 0x44 80034c2: e001 b.n 80034c8 } else { moveCmdTimeoutCounter = 0; 80034c4: 2300 movs r3, #0 80034c6: 647b str r3, [r7, #68] @ 0x44 } prevPosition = *posCtrlTaskArg->currentPosition; 80034c8: 6bfb ldr r3, [r7, #60] @ 0x3c 80034ca: 6a1b ldr r3, [r3, #32] 80034cc: 681b ldr r3, [r3, #0] 80034ce: 64fb str r3, [r7, #76] @ 0x4c if (moveCmdTimeoutCounter > NO_MOVE_TIMEOUT_MS) { 80034d0: 6c7b ldr r3, [r7, #68] @ 0x44 80034d2: f241 3288 movw r2, #5000 @ 0x1388 80034d6: 4293 cmp r3, r2 80034d8: dd2d ble.n 8003536 movementPhase = idlePhase; 80034da: 2300 movs r3, #0 80034dc: f887 3057 strb.w r3, [r7, #87] @ 0x57 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 80034e0: 6bfb ldr r3, [r7, #60] @ 0x3c 80034e2: 6818 ldr r0, [r3, #0] 80034e4: 6bfb ldr r3, [r7, #60] @ 0x3c 80034e6: 685d ldr r5, [r3, #4] 80034e8: 6bfb ldr r3, [r7, #60] @ 0x3c 80034ea: 7a1e ldrb r6, [r3, #8] 80034ec: 6bfb ldr r3, [r7, #60] @ 0x3c 80034ee: f893 c009 ldrb.w ip, [r3, #9] 80034f2: 6bfb ldr r3, [r7, #60] @ 0x3c 80034f4: 68db ldr r3, [r3, #12] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80034f6: 6bfa ldr r2, [r7, #60] @ 0x3c 80034f8: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 80034fa: 7812 ldrb r2, [r2, #0] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80034fc: 6bf9 ldr r1, [r7, #60] @ 0x3c 80034fe: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 8003500: 7809 ldrb r1, [r1, #0] 8003502: 9104 str r1, [sp, #16] 8003504: 9203 str r2, [sp, #12] 8003506: 2200 movs r2, #0 8003508: 9202 str r2, [sp, #8] 800350a: 2200 movs r2, #0 800350c: 9201 str r2, [sp, #4] 800350e: 9300 str r3, [sp, #0] 8003510: 4663 mov r3, ip 8003512: 4632 mov r2, r6 8003514: 4629 mov r1, r5 8003516: f7ff fc8f bl 8002e38 800351a: 4603 mov r3, r0 800351c: 63bb str r3, [r7, #56] @ 0x38 *posCtrlTaskArg->motorStatus = motorStatus; 800351e: 6bfb ldr r3, [r7, #60] @ 0x3c 8003520: 6a9b ldr r3, [r3, #40] @ 0x28 8003522: 6bba ldr r2, [r7, #56] @ 0x38 8003524: b2d2 uxtb r2, r2 8003526: 701a strb r2, [r3, #0] #ifdef DBG_POSITION printf ("Axe %c no movement idle phase\n", posCtrlTaskArg->axe); 8003528: 6bfb ldr r3, [r7, #60] @ 0x3c 800352a: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 800352e: 4619 mov r1, r3 8003530: 480f ldr r0, [pc, #60] @ (8003570 ) 8003532: f014 fa63 bl 80179fc #endif } switch (movementPhase) { 8003536: f897 3057 ldrb.w r3, [r7, #87] @ 0x57 800353a: 3b01 subs r3, #1 800353c: 2b04 cmp r3, #4 800353e: f200 816b bhi.w 8003818 8003542: a201 add r2, pc, #4 @ (adr r2, 8003548 ) 8003544: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003548: 08003575 .word 0x08003575 800354c: 0800360d .word 0x0800360d 8003550: 080036a9 .word 0x080036a9 8003554: 08003705 .word 0x08003705 8003558: 08003777 .word 0x08003777 800355c: 10624dd3 .word 0x10624dd3 8003560: 24000790 .word 0x24000790 8003564: 08018a14 .word 0x08018a14 8003568: 240008c0 .word 0x240008c0 800356c: 08018a28 .word 0x08018a28 8003570: 08018a54 .word 0x08018a54 case startPhase: motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003574: 6bfb ldr r3, [r7, #60] @ 0x3c 8003576: 681d ldr r5, [r3, #0] 8003578: 6bfb ldr r3, [r7, #60] @ 0x3c 800357a: 685e ldr r6, [r3, #4] 800357c: 6bfb ldr r3, [r7, #60] @ 0x3c 800357e: f893 c008 ldrb.w ip, [r3, #8] 8003582: 6bfb ldr r3, [r7, #60] @ 0x3c 8003584: f893 e009 ldrb.w lr, [r3, #9] 8003588: 6bfb ldr r3, [r7, #60] @ 0x3c 800358a: 68db ldr r3, [r3, #12] 800358c: 6dba ldr r2, [r7, #88] @ 0x58 800358e: 6df9 ldr r1, [r7, #92] @ 0x5c 8003590: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003594: 6bf9 ldr r1, [r7, #60] @ 0x3c 8003596: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003598: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 800359a: 6bf8 ldr r0, [r7, #60] @ 0x3c 800359c: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 800359e: 7800 ldrb r0, [r0, #0] 80035a0: 9004 str r0, [sp, #16] 80035a2: 9103 str r1, [sp, #12] 80035a4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80035a8: 9102 str r1, [sp, #8] 80035aa: 9201 str r2, [sp, #4] 80035ac: 9300 str r3, [sp, #0] 80035ae: 4673 mov r3, lr 80035b0: 4662 mov r2, ip 80035b2: 4631 mov r1, r6 80035b4: 4628 mov r0, r5 80035b6: f7ff fc3f bl 8002e38 80035ba: 4603 mov r3, r0 80035bc: 63bb str r3, [r7, #56] @ 0x38 *posCtrlTaskArg->motorStatus = motorStatus; 80035be: 6bfb ldr r3, [r7, #60] @ 0x3c 80035c0: 6a9b ldr r3, [r3, #40] @ 0x28 80035c2: 6bba ldr r2, [r7, #56] @ 0x38 80035c4: b2d2 uxtb r2, r2 80035c6: 701a strb r2, [r3, #0] if (motorStatus == 1) { 80035c8: 6bbb ldr r3, [r7, #56] @ 0x38 80035ca: 2b01 cmp r3, #1 80035cc: d113 bne.n 80035f6 *posCtrlTaskArg->motorPeakCurrent = 0.0; 80035ce: 6bfb ldr r3, [r7, #60] @ 0x3c 80035d0: 6adb ldr r3, [r3, #44] @ 0x2c 80035d2: f04f 0200 mov.w r2, #0 80035d6: 601a str r2, [r3, #0] #ifdef DBG_POSITION printf ("Axe %c speed up phase\n", posCtrlTaskArg->axe); 80035d8: 6bfb ldr r3, [r7, #60] @ 0x3c 80035da: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 80035de: 4619 mov r1, r3 80035e0: 489e ldr r0, [pc, #632] @ (800385c ) 80035e2: f014 fa0b bl 80179fc #endif movementPhase = speedUpPhase; 80035e6: 2302 movs r3, #2 80035e8: f887 3057 strb.w r3, [r7, #87] @ 0x57 timeLeftMS = 0; 80035ec: 2300 movs r3, #0 80035ee: 64bb str r3, [r7, #72] @ 0x48 moveCmdTimeoutCounter = 0; 80035f0: 2300 movs r3, #0 80035f2: 647b str r3, [r7, #68] @ 0x44 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); #endif } break; 80035f4: e117 b.n 8003826 movementPhase = idlePhase; 80035f6: 2300 movs r3, #0 80035f8: f887 3057 strb.w r3, [r7, #87] @ 0x57 printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); 80035fc: 6bfb ldr r3, [r7, #60] @ 0x3c 80035fe: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 8003602: 4619 mov r1, r3 8003604: 4896 ldr r0, [pc, #600] @ (8003860 ) 8003606: f014 f9f9 bl 80179fc break; 800360a: e10c b.n 8003826 case speedUpPhase: if ((abs (*posCtrlTaskArg->currentPosition - startPosition) >= ANGLE_RANGE_FOR_MOTOR_SPEED_LIMIT) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) { 800360c: 6bfb ldr r3, [r7, #60] @ 0x3c 800360e: 6a1b ldr r3, [r3, #32] 8003610: ed93 7a00 vldr s14, [r3] 8003614: edd7 7a14 vldr s15, [r7, #80] @ 0x50 8003618: ee77 7a67 vsub.f32 s15, s14, s15 800361c: eefd 7ae7 vcvt.s32.f32 s15, s15 8003620: ee17 3a90 vmov r3, s15 8003624: 2b00 cmp r3, #0 8003626: bfb8 it lt 8003628: 425b neglt r3, r3 800362a: 2b04 cmp r3, #4 800362c: dc05 bgt.n 800363a 800362e: 6cbb ldr r3, [r7, #72] @ 0x48 8003630: f241 3287 movw r2, #4999 @ 0x1387 8003634: 4293 cmp r3, r2 8003636: f340 80f1 ble.w 800381c pwmValue = MOTOR_HIGH_SPEED_PWM_VALUE; 800363a: 2364 movs r3, #100 @ 0x64 800363c: 65fb str r3, [r7, #92] @ 0x5c motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 800363e: 6bfb ldr r3, [r7, #60] @ 0x3c 8003640: 681d ldr r5, [r3, #0] 8003642: 6bfb ldr r3, [r7, #60] @ 0x3c 8003644: 685e ldr r6, [r3, #4] 8003646: 6bfb ldr r3, [r7, #60] @ 0x3c 8003648: f893 c008 ldrb.w ip, [r3, #8] 800364c: 6bfb ldr r3, [r7, #60] @ 0x3c 800364e: f893 e009 ldrb.w lr, [r3, #9] 8003652: 6bfb ldr r3, [r7, #60] @ 0x3c 8003654: 68db ldr r3, [r3, #12] 8003656: 6dba ldr r2, [r7, #88] @ 0x58 8003658: 6df9 ldr r1, [r7, #92] @ 0x5c 800365a: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 800365e: 6bf9 ldr r1, [r7, #60] @ 0x3c 8003660: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003662: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003664: 6bf8 ldr r0, [r7, #60] @ 0x3c 8003666: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003668: 7800 ldrb r0, [r0, #0] 800366a: 9004 str r0, [sp, #16] 800366c: 9103 str r1, [sp, #12] 800366e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003672: 9102 str r1, [sp, #8] 8003674: 9201 str r2, [sp, #4] 8003676: 9300 str r3, [sp, #0] 8003678: 4673 mov r3, lr 800367a: 4662 mov r2, ip 800367c: 4631 mov r1, r6 800367e: 4628 mov r0, r5 8003680: f7ff fbda bl 8002e38 8003684: 4603 mov r3, r0 8003686: 63bb str r3, [r7, #56] @ 0x38 *posCtrlTaskArg->motorStatus = motorStatus; 8003688: 6bfb ldr r3, [r7, #60] @ 0x3c 800368a: 6a9b ldr r3, [r3, #40] @ 0x28 800368c: 6bba ldr r2, [r7, #56] @ 0x38 800368e: b2d2 uxtb r2, r2 8003690: 701a strb r2, [r3, #0] movementPhase = movePhase; 8003692: 2303 movs r3, #3 8003694: f887 3057 strb.w r3, [r7, #87] @ 0x57 #ifdef DBG_POSITION printf ("Axe %c move phase\n", posCtrlTaskArg->axe); 8003698: 6bfb ldr r3, [r7, #60] @ 0x3c 800369a: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 800369e: 4619 mov r1, r3 80036a0: 4870 ldr r0, [pc, #448] @ (8003864 ) 80036a2: f014 f9ab bl 80179fc #endif } break; 80036a6: e0b9 b.n 800381c case movePhase: if (abs (*posCtrlTaskArg->currentPosition - *posCtrlTaskArg->positionSetting) <= ANGLE_RANGE_FOR_MOTOR_SPEED_LIMIT) { 80036a8: 6bfb ldr r3, [r7, #60] @ 0x3c 80036aa: 6a1b ldr r3, [r3, #32] 80036ac: ed93 7a00 vldr s14, [r3] 80036b0: 6bfb ldr r3, [r7, #60] @ 0x3c 80036b2: 6a5b ldr r3, [r3, #36] @ 0x24 80036b4: edd3 7a00 vldr s15, [r3] 80036b8: ee77 7a67 vsub.f32 s15, s14, s15 80036bc: eefd 7ae7 vcvt.s32.f32 s15, s15 80036c0: ee17 3a90 vmov r3, s15 80036c4: f113 0f05 cmn.w r3, #5 80036c8: f2c0 80aa blt.w 8003820 80036cc: 6bfb ldr r3, [r7, #60] @ 0x3c 80036ce: 6a1b ldr r3, [r3, #32] 80036d0: ed93 7a00 vldr s14, [r3] 80036d4: 6bfb ldr r3, [r7, #60] @ 0x3c 80036d6: 6a5b ldr r3, [r3, #36] @ 0x24 80036d8: edd3 7a00 vldr s15, [r3] 80036dc: ee77 7a67 vsub.f32 s15, s14, s15 80036e0: eefd 7ae7 vcvt.s32.f32 s15, s15 80036e4: ee17 3a90 vmov r3, s15 80036e8: 2b05 cmp r3, #5 80036ea: f300 8099 bgt.w 8003820 movementPhase = slowDownPhase; 80036ee: 2304 movs r3, #4 80036f0: f887 3057 strb.w r3, [r7, #87] @ 0x57 #ifdef DBG_POSITION printf ("Axe %c slow down phase\n", posCtrlTaskArg->axe); 80036f4: 6bfb ldr r3, [r7, #60] @ 0x3c 80036f6: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 80036fa: 4619 mov r1, r3 80036fc: 485a ldr r0, [pc, #360] @ (8003868 ) 80036fe: f014 f97d bl 80179fc #endif } break; 8003702: e08d b.n 8003820 case slowDownPhase: pwmValue = MOTOR_START_STOP_PWM_VALUE; 8003704: 233c movs r3, #60 @ 0x3c 8003706: 65fb str r3, [r7, #92] @ 0x5c motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003708: 6bfb ldr r3, [r7, #60] @ 0x3c 800370a: 681d ldr r5, [r3, #0] 800370c: 6bfb ldr r3, [r7, #60] @ 0x3c 800370e: 685e ldr r6, [r3, #4] 8003710: 6bfb ldr r3, [r7, #60] @ 0x3c 8003712: f893 c008 ldrb.w ip, [r3, #8] 8003716: 6bfb ldr r3, [r7, #60] @ 0x3c 8003718: f893 e009 ldrb.w lr, [r3, #9] 800371c: 6bfb ldr r3, [r7, #60] @ 0x3c 800371e: 68db ldr r3, [r3, #12] 8003720: 6dba ldr r2, [r7, #88] @ 0x58 8003722: 6df9 ldr r1, [r7, #92] @ 0x5c 8003724: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003728: 6bf9 ldr r1, [r7, #60] @ 0x3c 800372a: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 800372c: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 800372e: 6bf8 ldr r0, [r7, #60] @ 0x3c 8003730: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003732: 7800 ldrb r0, [r0, #0] 8003734: 9004 str r0, [sp, #16] 8003736: 9103 str r1, [sp, #12] 8003738: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800373c: 9102 str r1, [sp, #8] 800373e: 9201 str r2, [sp, #4] 8003740: 9300 str r3, [sp, #0] 8003742: 4673 mov r3, lr 8003744: 4662 mov r2, ip 8003746: 4631 mov r1, r6 8003748: 4628 mov r0, r5 800374a: f7ff fb75 bl 8002e38 800374e: 4603 mov r3, r0 8003750: 63bb str r3, [r7, #56] @ 0x38 *posCtrlTaskArg->motorStatus = motorStatus; 8003752: 6bfb ldr r3, [r7, #60] @ 0x3c 8003754: 6a9b ldr r3, [r3, #40] @ 0x28 8003756: 6bba ldr r2, [r7, #56] @ 0x38 8003758: b2d2 uxtb r2, r2 800375a: 701a strb r2, [r3, #0] movementPhase = stopPhase; 800375c: 2305 movs r3, #5 800375e: f887 3057 strb.w r3, [r7, #87] @ 0x57 timeLeftMS = 0; 8003762: 2300 movs r3, #0 8003764: 64bb str r3, [r7, #72] @ 0x48 #ifdef DBG_POSITION printf ("Axe %c stop phase\n", posCtrlTaskArg->axe); 8003766: 6bfb ldr r3, [r7, #60] @ 0x3c 8003768: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 800376c: 4619 mov r1, r3 800376e: 483f ldr r0, [pc, #252] @ (800386c ) 8003770: f014 f944 bl 80179fc #endif break; 8003774: e057 b.n 8003826 case stopPhase: float posDiff = sign > 0 ? posCtrlData.positionSettingValue - *posCtrlTaskArg->currentPosition : *posCtrlTaskArg->currentPosition - posCtrlData.positionSettingValue; 8003776: 6dbb ldr r3, [r7, #88] @ 0x58 8003778: 2b00 cmp r3, #0 800377a: dd08 ble.n 800378e 800377c: ed94 7a00 vldr s14, [r4] 8003780: 6bfb ldr r3, [r7, #60] @ 0x3c 8003782: 6a1b ldr r3, [r3, #32] 8003784: edd3 7a00 vldr s15, [r3] 8003788: ee77 7a67 vsub.f32 s15, s14, s15 800378c: e007 b.n 800379e 800378e: 6bfb ldr r3, [r7, #60] @ 0x3c 8003790: 6a1b ldr r3, [r3, #32] 8003792: ed93 7a00 vldr s14, [r3] 8003796: edd4 7a00 vldr s15, [r4] 800379a: ee77 7a67 vsub.f32 s15, s14, s15 800379e: edc7 7a0c vstr s15, [r7, #48] @ 0x30 if ((posDiff <= 0) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) { 80037a2: edd7 7a0c vldr s15, [r7, #48] @ 0x30 80037a6: eef5 7ac0 vcmpe.f32 s15, #0.0 80037aa: eef1 fa10 vmrs APSR_nzcv, fpscr 80037ae: d904 bls.n 80037ba 80037b0: 6cbb ldr r3, [r7, #72] @ 0x48 80037b2: f241 3287 movw r2, #4999 @ 0x1387 80037b6: 4293 cmp r3, r2 80037b8: dd34 ble.n 8003824 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80037ba: 6bfb ldr r3, [r7, #60] @ 0x3c 80037bc: 6818 ldr r0, [r3, #0] 80037be: 6bfb ldr r3, [r7, #60] @ 0x3c 80037c0: 685d ldr r5, [r3, #4] 80037c2: 6bfb ldr r3, [r7, #60] @ 0x3c 80037c4: 7a1e ldrb r6, [r3, #8] 80037c6: 6bfb ldr r3, [r7, #60] @ 0x3c 80037c8: f893 c009 ldrb.w ip, [r3, #9] 80037cc: 6bfb ldr r3, [r7, #60] @ 0x3c 80037ce: 68db ldr r3, [r3, #12] 0, 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80037d0: 6bfa ldr r2, [r7, #60] @ 0x3c 80037d2: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80037d4: 7812 ldrb r2, [r2, #0] 0, 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80037d6: 6bf9 ldr r1, [r7, #60] @ 0x3c 80037d8: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80037da: 7809 ldrb r1, [r1, #0] 80037dc: 9104 str r1, [sp, #16] 80037de: 9203 str r2, [sp, #12] 80037e0: 2200 movs r2, #0 80037e2: 9202 str r2, [sp, #8] 80037e4: 2200 movs r2, #0 80037e6: 9201 str r2, [sp, #4] 80037e8: 9300 str r3, [sp, #0] 80037ea: 4663 mov r3, ip 80037ec: 4632 mov r2, r6 80037ee: 4629 mov r1, r5 80037f0: f7ff fb22 bl 8002e38 80037f4: 4603 mov r3, r0 80037f6: 63bb str r3, [r7, #56] @ 0x38 *posCtrlTaskArg->motorStatus = motorStatus; 80037f8: 6bfb ldr r3, [r7, #60] @ 0x3c 80037fa: 6a9b ldr r3, [r3, #40] @ 0x28 80037fc: 6bba ldr r2, [r7, #56] @ 0x38 80037fe: b2d2 uxtb r2, r2 8003800: 701a strb r2, [r3, #0] movementPhase = idlePhase; 8003802: 2300 movs r3, #0 8003804: f887 3057 strb.w r3, [r7, #87] @ 0x57 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); 8003808: 6bfb ldr r3, [r7, #60] @ 0x3c 800380a: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 800380e: 4619 mov r1, r3 8003810: 4813 ldr r0, [pc, #76] @ (8003860 ) 8003812: f014 f8f3 bl 80179fc #endif } break; 8003816: e005 b.n 8003824 default: break; 8003818: bf00 nop 800381a: e018 b.n 800384e break; 800381c: bf00 nop 800381e: e016 b.n 800384e break; 8003820: bf00 nop 8003822: e014 b.n 800384e break; 8003824: bf00 nop switch (movementPhase) { 8003826: e012 b.n 800384e } } else { if ((*posCtrlTaskArg->motorStatus == 0) && (movementPhase != idlePhase)) { 8003828: 6bfb ldr r3, [r7, #60] @ 0x3c 800382a: 6a9b ldr r3, [r3, #40] @ 0x28 800382c: 781b ldrb r3, [r3, #0] 800382e: 2b00 cmp r3, #0 8003830: d10d bne.n 800384e 8003832: f897 3057 ldrb.w r3, [r7, #87] @ 0x57 8003836: 2b00 cmp r3, #0 8003838: d009 beq.n 800384e movementPhase = idlePhase; 800383a: 2300 movs r3, #0 800383c: f887 3057 strb.w r3, [r7, #87] @ 0x57 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); 8003840: 6bfb ldr r3, [r7, #60] @ 0x3c 8003842: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 8003846: 4619 mov r1, r3 8003848: 4805 ldr r0, [pc, #20] @ (8003860 ) 800384a: f014 f8d7 bl 80179fc #endif } } osMutexRelease (sensorsInfoMutex); 800384e: 4b08 ldr r3, [pc, #32] @ (8003870 ) 8003850: 681b ldr r3, [r3, #0] 8003852: 4618 mov r0, r3 8003854: f010 f934 bl 8013ac0 queueSatus = osMessageQueueGet (posCtrlTaskArg->positionSettingQueue, &posCtrlData, 0, pdMS_TO_TICKS (PositionControlTaskTimeOut)); 8003858: e56c b.n 8003334 800385a: bf00 nop 800385c: 08018a74 .word 0x08018a74 8003860: 08018a8c .word 0x08018a8c 8003864: 08018aa0 .word 0x08018aa0 8003868: 08018ab4 .word 0x08018ab4 800386c: 08018acc .word 0x08018acc 8003870: 24000790 .word 0x24000790 08003874 : buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); } *buffPos = newBuffPos; } void WriteDataToBuffer (uint8_t* buff, uint16_t* buffPos, void* data, uint8_t dataSize) { 8003874: b480 push {r7} 8003876: b089 sub sp, #36 @ 0x24 8003878: af00 add r7, sp, #0 800387a: 60f8 str r0, [r7, #12] 800387c: 60b9 str r1, [r7, #8] 800387e: 607a str r2, [r7, #4] 8003880: 70fb strb r3, [r7, #3] uint32_t* uDataPtr = data; 8003882: 687b ldr r3, [r7, #4] 8003884: 61bb str r3, [r7, #24] uint32_t uData = *uDataPtr; 8003886: 69bb ldr r3, [r7, #24] 8003888: 681b ldr r3, [r3, #0] 800388a: 617b str r3, [r7, #20] uint8_t i = 0; 800388c: 2300 movs r3, #0 800388e: 77fb strb r3, [r7, #31] uint8_t newBuffPos = *buffPos; 8003890: 68bb ldr r3, [r7, #8] 8003892: 881b ldrh r3, [r3, #0] 8003894: 77bb strb r3, [r7, #30] for (i = 0; i < dataSize; i++) { 8003896: 2300 movs r3, #0 8003898: 77fb strb r3, [r7, #31] 800389a: e00e b.n 80038ba buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); 800389c: 7ffb ldrb r3, [r7, #31] 800389e: 00db lsls r3, r3, #3 80038a0: 697a ldr r2, [r7, #20] 80038a2: 40da lsrs r2, r3 80038a4: 7fbb ldrb r3, [r7, #30] 80038a6: 1c59 adds r1, r3, #1 80038a8: 77b9 strb r1, [r7, #30] 80038aa: 4619 mov r1, r3 80038ac: 68fb ldr r3, [r7, #12] 80038ae: 440b add r3, r1 80038b0: b2d2 uxtb r2, r2 80038b2: 701a strb r2, [r3, #0] for (i = 0; i < dataSize; i++) { 80038b4: 7ffb ldrb r3, [r7, #31] 80038b6: 3301 adds r3, #1 80038b8: 77fb strb r3, [r7, #31] 80038ba: 7ffa ldrb r2, [r7, #31] 80038bc: 78fb ldrb r3, [r7, #3] 80038be: 429a cmp r2, r3 80038c0: d3ec bcc.n 800389c } *buffPos = newBuffPos; 80038c2: 7fbb ldrb r3, [r7, #30] 80038c4: b29a uxth r2, r3 80038c6: 68bb ldr r3, [r7, #8] 80038c8: 801a strh r2, [r3, #0] } 80038ca: bf00 nop 80038cc: 3724 adds r7, #36 @ 0x24 80038ce: 46bd mov sp, r7 80038d0: f85d 7b04 ldr.w r7, [sp], #4 80038d4: 4770 bx lr 080038d6 : void ReadFloatFromBuffer(uint8_t* buff, uint16_t* buffPos, float* data) { 80038d6: b480 push {r7} 80038d8: b087 sub sp, #28 80038da: af00 add r7, sp, #0 80038dc: 60f8 str r0, [r7, #12] 80038de: 60b9 str r1, [r7, #8] 80038e0: 607a str r2, [r7, #4] uint32_t* word = (uint32_t *)data; 80038e2: 687b ldr r3, [r7, #4] 80038e4: 617b str r3, [r7, #20] *word = CONVERT_BYTES_TO_WORD(&buff[*buffPos]); 80038e6: 68bb ldr r3, [r7, #8] 80038e8: 881b ldrh r3, [r3, #0] 80038ea: 3303 adds r3, #3 80038ec: 68fa ldr r2, [r7, #12] 80038ee: 4413 add r3, r2 80038f0: 781b ldrb r3, [r3, #0] 80038f2: 061a lsls r2, r3, #24 80038f4: 68bb ldr r3, [r7, #8] 80038f6: 881b ldrh r3, [r3, #0] 80038f8: 3302 adds r3, #2 80038fa: 68f9 ldr r1, [r7, #12] 80038fc: 440b add r3, r1 80038fe: 781b ldrb r3, [r3, #0] 8003900: 041b lsls r3, r3, #16 8003902: 431a orrs r2, r3 8003904: 68bb ldr r3, [r7, #8] 8003906: 881b ldrh r3, [r3, #0] 8003908: 3301 adds r3, #1 800390a: 68f9 ldr r1, [r7, #12] 800390c: 440b add r3, r1 800390e: 781b ldrb r3, [r3, #0] 8003910: 021b lsls r3, r3, #8 8003912: 4313 orrs r3, r2 8003914: 68ba ldr r2, [r7, #8] 8003916: 8812 ldrh r2, [r2, #0] 8003918: 4611 mov r1, r2 800391a: 68fa ldr r2, [r7, #12] 800391c: 440a add r2, r1 800391e: 7812 ldrb r2, [r2, #0] 8003920: 4313 orrs r3, r2 8003922: 461a mov r2, r3 8003924: 697b ldr r3, [r7, #20] 8003926: 601a str r2, [r3, #0] *buffPos += sizeof(float); 8003928: 68bb ldr r3, [r7, #8] 800392a: 881b ldrh r3, [r3, #0] 800392c: 3304 adds r3, #4 800392e: b29a uxth r2, r3 8003930: 68bb ldr r3, [r7, #8] 8003932: 801a strh r2, [r3, #0] } 8003934: bf00 nop 8003936: 371c adds r7, #28 8003938: 46bd mov sp, r7 800393a: f85d 7b04 ldr.w r7, [sp], #4 800393e: 4770 bx lr 08003940 : *data = CONVERT_BYTES_TO_SHORT_WORD(&buff[*buffPos]); *buffPos += sizeof(uint16_t); } void ReadWordFromBufer(uint8_t* buff, uint16_t* buffPos, uint32_t* data) { 8003940: b480 push {r7} 8003942: b085 sub sp, #20 8003944: af00 add r7, sp, #0 8003946: 60f8 str r0, [r7, #12] 8003948: 60b9 str r1, [r7, #8] 800394a: 607a str r2, [r7, #4] *data = CONVERT_BYTES_TO_WORD(&buff[*buffPos]); 800394c: 68bb ldr r3, [r7, #8] 800394e: 881b ldrh r3, [r3, #0] 8003950: 3303 adds r3, #3 8003952: 68fa ldr r2, [r7, #12] 8003954: 4413 add r3, r2 8003956: 781b ldrb r3, [r3, #0] 8003958: 061a lsls r2, r3, #24 800395a: 68bb ldr r3, [r7, #8] 800395c: 881b ldrh r3, [r3, #0] 800395e: 3302 adds r3, #2 8003960: 68f9 ldr r1, [r7, #12] 8003962: 440b add r3, r1 8003964: 781b ldrb r3, [r3, #0] 8003966: 041b lsls r3, r3, #16 8003968: 431a orrs r2, r3 800396a: 68bb ldr r3, [r7, #8] 800396c: 881b ldrh r3, [r3, #0] 800396e: 3301 adds r3, #1 8003970: 68f9 ldr r1, [r7, #12] 8003972: 440b add r3, r1 8003974: 781b ldrb r3, [r3, #0] 8003976: 021b lsls r3, r3, #8 8003978: 4313 orrs r3, r2 800397a: 68ba ldr r2, [r7, #8] 800397c: 8812 ldrh r2, [r2, #0] 800397e: 4611 mov r1, r2 8003980: 68fa ldr r2, [r7, #12] 8003982: 440a add r2, r1 8003984: 7812 ldrb r2, [r2, #0] 8003986: 4313 orrs r3, r2 8003988: 461a mov r2, r3 800398a: 687b ldr r3, [r7, #4] 800398c: 601a str r2, [r3, #0] *buffPos += sizeof(uint32_t); 800398e: 68bb ldr r3, [r7, #8] 8003990: 881b ldrh r3, [r3, #0] 8003992: 3304 adds r3, #4 8003994: b29a uxth r2, r3 8003996: 68bb ldr r3, [r7, #8] 8003998: 801a strh r2, [r3, #0] } 800399a: bf00 nop 800399c: 3714 adds r7, #20 800399e: 46bd mov sp, r7 80039a0: f85d 7b04 ldr.w r7, [sp], #4 80039a4: 4770 bx lr ... 080039a8 : txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); return txBufferPos; } uint16_t PrepareRespFrame (uint8_t* txBuffer, uint16_t frameId, SerialProtocolCommands frameCommand, SerialProtocolRespStatus respStatus, uint8_t* dataBuffer, uint16_t dataLength) { 80039a8: b580 push {r7, lr} 80039aa: b084 sub sp, #16 80039ac: af00 add r7, sp, #0 80039ae: 6078 str r0, [r7, #4] 80039b0: 4608 mov r0, r1 80039b2: 4611 mov r1, r2 80039b4: 461a mov r2, r3 80039b6: 4603 mov r3, r0 80039b8: 807b strh r3, [r7, #2] 80039ba: 460b mov r3, r1 80039bc: 707b strb r3, [r7, #1] 80039be: 4613 mov r3, r2 80039c0: 703b strb r3, [r7, #0] uint16_t crc = 0; 80039c2: 2300 movs r3, #0 80039c4: 81bb strh r3, [r7, #12] uint16_t txBufferPos = 0; 80039c6: 2300 movs r3, #0 80039c8: 81fb strh r3, [r7, #14] uint16_t frameCmd = ((uint16_t)frameCommand) | 0x8000; // MSB set means response 80039ca: 787b ldrb r3, [r7, #1] 80039cc: b21a sxth r2, r3 80039ce: 4b43 ldr r3, [pc, #268] @ (8003adc ) 80039d0: 4313 orrs r3, r2 80039d2: b21b sxth r3, r3 80039d4: 817b strh r3, [r7, #10] memset (txBuffer, 0x00, dataLength); 80039d6: 8bbb ldrh r3, [r7, #28] 80039d8: 461a mov r2, r3 80039da: 2100 movs r1, #0 80039dc: 6878 ldr r0, [r7, #4] 80039de: f014 f955 bl 8017c8c txBuffer[txBufferPos++] = FRAME_INDICATOR; 80039e2: 89fb ldrh r3, [r7, #14] 80039e4: 1c5a adds r2, r3, #1 80039e6: 81fa strh r2, [r7, #14] 80039e8: 461a mov r2, r3 80039ea: 687b ldr r3, [r7, #4] 80039ec: 4413 add r3, r2 80039ee: 22aa movs r2, #170 @ 0xaa 80039f0: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameId); 80039f2: 89fb ldrh r3, [r7, #14] 80039f4: 1c5a adds r2, r3, #1 80039f6: 81fa strh r2, [r7, #14] 80039f8: 461a mov r2, r3 80039fa: 687b ldr r3, [r7, #4] 80039fc: 4413 add r3, r2 80039fe: 887a ldrh r2, [r7, #2] 8003a00: b2d2 uxtb r2, r2 8003a02: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameId); 8003a04: 887b ldrh r3, [r7, #2] 8003a06: 0a1b lsrs r3, r3, #8 8003a08: b29a uxth r2, r3 8003a0a: 89fb ldrh r3, [r7, #14] 8003a0c: 1c59 adds r1, r3, #1 8003a0e: 81f9 strh r1, [r7, #14] 8003a10: 4619 mov r1, r3 8003a12: 687b ldr r3, [r7, #4] 8003a14: 440b add r3, r1 8003a16: b2d2 uxtb r2, r2 8003a18: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameCmd); 8003a1a: 89fb ldrh r3, [r7, #14] 8003a1c: 1c5a adds r2, r3, #1 8003a1e: 81fa strh r2, [r7, #14] 8003a20: 461a mov r2, r3 8003a22: 687b ldr r3, [r7, #4] 8003a24: 4413 add r3, r2 8003a26: 897a ldrh r2, [r7, #10] 8003a28: b2d2 uxtb r2, r2 8003a2a: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameCmd); 8003a2c: 897b ldrh r3, [r7, #10] 8003a2e: 0a1b lsrs r3, r3, #8 8003a30: b29a uxth r2, r3 8003a32: 89fb ldrh r3, [r7, #14] 8003a34: 1c59 adds r1, r3, #1 8003a36: 81f9 strh r1, [r7, #14] 8003a38: 4619 mov r1, r3 8003a3a: 687b ldr r3, [r7, #4] 8003a3c: 440b add r3, r1 8003a3e: b2d2 uxtb r2, r2 8003a40: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (dataLength); 8003a42: 89fb ldrh r3, [r7, #14] 8003a44: 1c5a adds r2, r3, #1 8003a46: 81fa strh r2, [r7, #14] 8003a48: 461a mov r2, r3 8003a4a: 687b ldr r3, [r7, #4] 8003a4c: 4413 add r3, r2 8003a4e: 8bba ldrh r2, [r7, #28] 8003a50: b2d2 uxtb r2, r2 8003a52: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (dataLength); 8003a54: 8bbb ldrh r3, [r7, #28] 8003a56: 0a1b lsrs r3, r3, #8 8003a58: b29a uxth r2, r3 8003a5a: 89fb ldrh r3, [r7, #14] 8003a5c: 1c59 adds r1, r3, #1 8003a5e: 81f9 strh r1, [r7, #14] 8003a60: 4619 mov r1, r3 8003a62: 687b ldr r3, [r7, #4] 8003a64: 440b add r3, r1 8003a66: b2d2 uxtb r2, r2 8003a68: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = (uint8_t)respStatus; 8003a6a: 89fb ldrh r3, [r7, #14] 8003a6c: 1c5a adds r2, r3, #1 8003a6e: 81fa strh r2, [r7, #14] 8003a70: 461a mov r2, r3 8003a72: 687b ldr r3, [r7, #4] 8003a74: 4413 add r3, r2 8003a76: 783a ldrb r2, [r7, #0] 8003a78: 701a strb r2, [r3, #0] if (dataLength > 0) { 8003a7a: 8bbb ldrh r3, [r7, #28] 8003a7c: 2b00 cmp r3, #0 8003a7e: d00b beq.n 8003a98 memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength); 8003a80: 89fb ldrh r3, [r7, #14] 8003a82: 687a ldr r2, [r7, #4] 8003a84: 4413 add r3, r2 8003a86: 8bba ldrh r2, [r7, #28] 8003a88: 69b9 ldr r1, [r7, #24] 8003a8a: 4618 mov r0, r3 8003a8c: f014 f9cf bl 8017e2e txBufferPos += dataLength; 8003a90: 89fa ldrh r2, [r7, #14] 8003a92: 8bbb ldrh r3, [r7, #28] 8003a94: 4413 add r3, r2 8003a96: 81fb strh r3, [r7, #14] } crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)txBuffer, txBufferPos); 8003a98: 89fb ldrh r3, [r7, #14] 8003a9a: 461a mov r2, r3 8003a9c: 6879 ldr r1, [r7, #4] 8003a9e: 4810 ldr r0, [pc, #64] @ (8003ae0 ) 8003aa0: f004 f830 bl 8007b04 8003aa4: 4603 mov r3, r0 8003aa6: 81bb strh r3, [r7, #12] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (crc); 8003aa8: 89fb ldrh r3, [r7, #14] 8003aaa: 1c5a adds r2, r3, #1 8003aac: 81fa strh r2, [r7, #14] 8003aae: 461a mov r2, r3 8003ab0: 687b ldr r3, [r7, #4] 8003ab2: 4413 add r3, r2 8003ab4: 89ba ldrh r2, [r7, #12] 8003ab6: b2d2 uxtb r2, r2 8003ab8: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); 8003aba: 89bb ldrh r3, [r7, #12] 8003abc: 0a1b lsrs r3, r3, #8 8003abe: b29a uxth r2, r3 8003ac0: 89fb ldrh r3, [r7, #14] 8003ac2: 1c59 adds r1, r3, #1 8003ac4: 81f9 strh r1, [r7, #14] 8003ac6: 4619 mov r1, r3 8003ac8: 687b ldr r3, [r7, #4] 8003aca: 440b add r3, r1 8003acc: b2d2 uxtb r2, r2 8003ace: 701a strb r2, [r3, #0] return txBufferPos; 8003ad0: 89fb ldrh r3, [r7, #14] } 8003ad2: 4618 mov r0, r3 8003ad4: 3710 adds r7, #16 8003ad6: 46bd mov sp, r7 8003ad8: bd80 pop {r7, pc} 8003ada: bf00 nop 8003adc: ffff8000 .word 0xffff8000 8003ae0: 24000400 .word 0x24000400 08003ae4 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8003ae4: b580 push {r7, lr} 8003ae6: b086 sub sp, #24 8003ae8: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ PWREx_AVDTypeDef sConfigAVD = {0}; 8003aea: f107 0310 add.w r3, r7, #16 8003aee: 2200 movs r2, #0 8003af0: 601a str r2, [r3, #0] 8003af2: 605a str r2, [r3, #4] PWR_PVDTypeDef sConfigPVD = {0}; 8003af4: f107 0308 add.w r3, r7, #8 8003af8: 2200 movs r2, #0 8003afa: 601a str r2, [r3, #0] 8003afc: 605a str r2, [r3, #4] __HAL_RCC_SYSCFG_CLK_ENABLE(); 8003afe: 4b26 ldr r3, [pc, #152] @ (8003b98 ) 8003b00: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003b04: 4a24 ldr r2, [pc, #144] @ (8003b98 ) 8003b06: f043 0302 orr.w r3, r3, #2 8003b0a: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8003b0e: 4b22 ldr r3, [pc, #136] @ (8003b98 ) 8003b10: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003b14: f003 0302 and.w r3, r3, #2 8003b18: 607b str r3, [r7, #4] 8003b1a: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 8003b1c: 2200 movs r2, #0 8003b1e: 210f movs r1, #15 8003b20: f06f 0001 mvn.w r0, #1 8003b24: f003 feea bl 80078fc /* Peripheral interrupt init */ /* RCC_IRQn interrupt configuration */ HAL_NVIC_SetPriority(RCC_IRQn, 5, 0); 8003b28: 2200 movs r2, #0 8003b2a: 2105 movs r1, #5 8003b2c: 2005 movs r0, #5 8003b2e: f003 fee5 bl 80078fc HAL_NVIC_EnableIRQ(RCC_IRQn); 8003b32: 2005 movs r0, #5 8003b34: f003 fefc bl 8007930 /** AVD Configuration */ sConfigAVD.AVDLevel = PWR_AVDLEVEL_3; 8003b38: f44f 23c0 mov.w r3, #393216 @ 0x60000 8003b3c: 613b str r3, [r7, #16] sConfigAVD.Mode = PWR_AVD_MODE_NORMAL; 8003b3e: 2300 movs r3, #0 8003b40: 617b str r3, [r7, #20] HAL_PWREx_ConfigAVD(&sConfigAVD); 8003b42: f107 0310 add.w r3, r7, #16 8003b46: 4618 mov r0, r3 8003b48: f007 fce4 bl 800b514 /** Enable the AVD Output */ HAL_PWREx_EnableAVD(); 8003b4c: f007 fd58 bl 800b600 /** PVD Configuration */ sConfigPVD.PVDLevel = PWR_PVDLEVEL_6; 8003b50: 23c0 movs r3, #192 @ 0xc0 8003b52: 60bb str r3, [r7, #8] sConfigPVD.Mode = PWR_PVD_MODE_NORMAL; 8003b54: 2300 movs r3, #0 8003b56: 60fb str r3, [r7, #12] HAL_PWR_ConfigPVD(&sConfigPVD); 8003b58: f107 0308 add.w r3, r7, #8 8003b5c: 4618 mov r0, r3 8003b5e: f007 fc15 bl 800b38c /** Enable the PVD Output */ HAL_PWR_EnablePVD(); 8003b62: f007 fc8d bl 800b480 /** Enable the VREF clock */ __HAL_RCC_VREF_CLK_ENABLE(); 8003b66: 4b0c ldr r3, [pc, #48] @ (8003b98 ) 8003b68: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003b6c: 4a0a ldr r2, [pc, #40] @ (8003b98 ) 8003b6e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8003b72: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8003b76: 4b08 ldr r3, [pc, #32] @ (8003b98 ) 8003b78: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003b7c: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003b80: 603b str r3, [r7, #0] 8003b82: 683b ldr r3, [r7, #0] /** Disable the Internal Voltage Reference buffer */ HAL_SYSCFG_DisableVREFBUF(); 8003b84: f002 f840 bl 8005c08 /** Configure the internal voltage reference buffer high impedance mode */ HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE); 8003b88: 2002 movs r0, #2 8003b8a: f002 f829 bl 8005be0 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8003b8e: bf00 nop 8003b90: 3718 adds r7, #24 8003b92: 46bd mov sp, r7 8003b94: bd80 pop {r7, pc} 8003b96: bf00 nop 8003b98: 58024400 .word 0x58024400 08003b9c : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8003b9c: b580 push {r7, lr} 8003b9e: b092 sub sp, #72 @ 0x48 8003ba0: af00 add r7, sp, #0 8003ba2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003ba4: f107 0334 add.w r3, r7, #52 @ 0x34 8003ba8: 2200 movs r2, #0 8003baa: 601a str r2, [r3, #0] 8003bac: 605a str r2, [r3, #4] 8003bae: 609a str r2, [r3, #8] 8003bb0: 60da str r2, [r3, #12] 8003bb2: 611a str r2, [r3, #16] if(hadc->Instance==ADC1) 8003bb4: 687b ldr r3, [r7, #4] 8003bb6: 681b ldr r3, [r3, #0] 8003bb8: 4a9d ldr r2, [pc, #628] @ (8003e30 ) 8003bba: 4293 cmp r3, r2 8003bbc: f040 8099 bne.w 8003cf2 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; 8003bc0: 4b9c ldr r3, [pc, #624] @ (8003e34 ) 8003bc2: 681b ldr r3, [r3, #0] 8003bc4: 3301 adds r3, #1 8003bc6: 4a9b ldr r2, [pc, #620] @ (8003e34 ) 8003bc8: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8003bca: 4b9a ldr r3, [pc, #616] @ (8003e34 ) 8003bcc: 681b ldr r3, [r3, #0] 8003bce: 2b01 cmp r3, #1 8003bd0: d10e bne.n 8003bf0 __HAL_RCC_ADC12_CLK_ENABLE(); 8003bd2: 4b99 ldr r3, [pc, #612] @ (8003e38 ) 8003bd4: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003bd8: 4a97 ldr r2, [pc, #604] @ (8003e38 ) 8003bda: f043 0320 orr.w r3, r3, #32 8003bde: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8003be2: 4b95 ldr r3, [pc, #596] @ (8003e38 ) 8003be4: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003be8: f003 0320 and.w r3, r3, #32 8003bec: 633b str r3, [r7, #48] @ 0x30 8003bee: 6b3b ldr r3, [r7, #48] @ 0x30 } __HAL_RCC_GPIOA_CLK_ENABLE(); 8003bf0: 4b91 ldr r3, [pc, #580] @ (8003e38 ) 8003bf2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003bf6: 4a90 ldr r2, [pc, #576] @ (8003e38 ) 8003bf8: f043 0301 orr.w r3, r3, #1 8003bfc: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003c00: 4b8d ldr r3, [pc, #564] @ (8003e38 ) 8003c02: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003c06: f003 0301 and.w r3, r3, #1 8003c0a: 62fb str r3, [r7, #44] @ 0x2c 8003c0c: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 8003c0e: 4b8a ldr r3, [pc, #552] @ (8003e38 ) 8003c10: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003c14: 4a88 ldr r2, [pc, #544] @ (8003e38 ) 8003c16: f043 0304 orr.w r3, r3, #4 8003c1a: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003c1e: 4b86 ldr r3, [pc, #536] @ (8003e38 ) 8003c20: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003c24: f003 0304 and.w r3, r3, #4 8003c28: 62bb str r3, [r7, #40] @ 0x28 8003c2a: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOB_CLK_ENABLE(); 8003c2c: 4b82 ldr r3, [pc, #520] @ (8003e38 ) 8003c2e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003c32: 4a81 ldr r2, [pc, #516] @ (8003e38 ) 8003c34: f043 0302 orr.w r3, r3, #2 8003c38: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003c3c: 4b7e ldr r3, [pc, #504] @ (8003e38 ) 8003c3e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003c42: f003 0302 and.w r3, r3, #2 8003c46: 627b str r3, [r7, #36] @ 0x24 8003c48: 6a7b ldr r3, [r7, #36] @ 0x24 PA3 ------> ADC1_INP15 PA7 ------> ADC1_INP7 PC5 ------> ADC1_INP8 PB0 ------> ADC1_INP9 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 8003c4a: 238f movs r3, #143 @ 0x8f 8003c4c: 637b str r3, [r7, #52] @ 0x34 |GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003c4e: 2303 movs r3, #3 8003c50: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003c52: 2300 movs r3, #0 8003c54: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003c56: f107 0334 add.w r3, r7, #52 @ 0x34 8003c5a: 4619 mov r1, r3 8003c5c: 4877 ldr r0, [pc, #476] @ (8003e3c ) 8003c5e: f007 f97f bl 800af60 GPIO_InitStruct.Pin = GPIO_PIN_5; 8003c62: 2320 movs r3, #32 8003c64: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003c66: 2303 movs r3, #3 8003c68: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003c6a: 2300 movs r3, #0 8003c6c: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003c6e: f107 0334 add.w r3, r7, #52 @ 0x34 8003c72: 4619 mov r1, r3 8003c74: 4872 ldr r0, [pc, #456] @ (8003e40 ) 8003c76: f007 f973 bl 800af60 GPIO_InitStruct.Pin = GPIO_PIN_0; 8003c7a: 2301 movs r3, #1 8003c7c: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003c7e: 2303 movs r3, #3 8003c80: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003c82: 2300 movs r3, #0 8003c84: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003c86: f107 0334 add.w r3, r7, #52 @ 0x34 8003c8a: 4619 mov r1, r3 8003c8c: 486d ldr r0, [pc, #436] @ (8003e44 ) 8003c8e: f007 f967 bl 800af60 /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Stream0; 8003c92: 4b6d ldr r3, [pc, #436] @ (8003e48 ) 8003c94: 4a6d ldr r2, [pc, #436] @ (8003e4c ) 8003c96: 601a str r2, [r3, #0] hdma_adc1.Init.Request = DMA_REQUEST_ADC1; 8003c98: 4b6b ldr r3, [pc, #428] @ (8003e48 ) 8003c9a: 2209 movs r2, #9 8003c9c: 605a str r2, [r3, #4] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003c9e: 4b6a ldr r3, [pc, #424] @ (8003e48 ) 8003ca0: 2200 movs r2, #0 8003ca2: 609a str r2, [r3, #8] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8003ca4: 4b68 ldr r3, [pc, #416] @ (8003e48 ) 8003ca6: 2200 movs r2, #0 8003ca8: 60da str r2, [r3, #12] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8003caa: 4b67 ldr r3, [pc, #412] @ (8003e48 ) 8003cac: f44f 6280 mov.w r2, #1024 @ 0x400 8003cb0: 611a str r2, [r3, #16] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8003cb2: 4b65 ldr r3, [pc, #404] @ (8003e48 ) 8003cb4: f44f 6200 mov.w r2, #2048 @ 0x800 8003cb8: 615a str r2, [r3, #20] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8003cba: 4b63 ldr r3, [pc, #396] @ (8003e48 ) 8003cbc: f44f 5200 mov.w r2, #8192 @ 0x2000 8003cc0: 619a str r2, [r3, #24] hdma_adc1.Init.Mode = DMA_NORMAL; 8003cc2: 4b61 ldr r3, [pc, #388] @ (8003e48 ) 8003cc4: 2200 movs r2, #0 8003cc6: 61da str r2, [r3, #28] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; 8003cc8: 4b5f ldr r3, [pc, #380] @ (8003e48 ) 8003cca: 2200 movs r2, #0 8003ccc: 621a str r2, [r3, #32] hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003cce: 4b5e ldr r3, [pc, #376] @ (8003e48 ) 8003cd0: 2200 movs r2, #0 8003cd2: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 8003cd4: 485c ldr r0, [pc, #368] @ (8003e48 ) 8003cd6: f004 fb07 bl 80082e8 8003cda: 4603 mov r3, r0 8003cdc: 2b00 cmp r3, #0 8003cde: d001 beq.n 8003ce4 { Error_Handler(); 8003ce0: f7fd ff74 bl 8001bcc } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); 8003ce4: 687b ldr r3, [r7, #4] 8003ce6: 4a58 ldr r2, [pc, #352] @ (8003e48 ) 8003ce8: 64da str r2, [r3, #76] @ 0x4c 8003cea: 4a57 ldr r2, [pc, #348] @ (8003e48 ) 8003cec: 687b ldr r3, [r7, #4] 8003cee: 6393 str r3, [r2, #56] @ 0x38 /* USER CODE BEGIN ADC3_MspInit 1 */ /* USER CODE END ADC3_MspInit 1 */ } } 8003cf0: e11e b.n 8003f30 else if(hadc->Instance==ADC2) 8003cf2: 687b ldr r3, [r7, #4] 8003cf4: 681b ldr r3, [r3, #0] 8003cf6: 4a56 ldr r2, [pc, #344] @ (8003e50 ) 8003cf8: 4293 cmp r3, r2 8003cfa: f040 80af bne.w 8003e5c HAL_RCC_ADC12_CLK_ENABLED++; 8003cfe: 4b4d ldr r3, [pc, #308] @ (8003e34 ) 8003d00: 681b ldr r3, [r3, #0] 8003d02: 3301 adds r3, #1 8003d04: 4a4b ldr r2, [pc, #300] @ (8003e34 ) 8003d06: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8003d08: 4b4a ldr r3, [pc, #296] @ (8003e34 ) 8003d0a: 681b ldr r3, [r3, #0] 8003d0c: 2b01 cmp r3, #1 8003d0e: d10e bne.n 8003d2e __HAL_RCC_ADC12_CLK_ENABLE(); 8003d10: 4b49 ldr r3, [pc, #292] @ (8003e38 ) 8003d12: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003d16: 4a48 ldr r2, [pc, #288] @ (8003e38 ) 8003d18: f043 0320 orr.w r3, r3, #32 8003d1c: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8003d20: 4b45 ldr r3, [pc, #276] @ (8003e38 ) 8003d22: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003d26: f003 0320 and.w r3, r3, #32 8003d2a: 623b str r3, [r7, #32] 8003d2c: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 8003d2e: 4b42 ldr r3, [pc, #264] @ (8003e38 ) 8003d30: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d34: 4a40 ldr r2, [pc, #256] @ (8003e38 ) 8003d36: f043 0301 orr.w r3, r3, #1 8003d3a: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003d3e: 4b3e ldr r3, [pc, #248] @ (8003e38 ) 8003d40: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d44: f003 0301 and.w r3, r3, #1 8003d48: 61fb str r3, [r7, #28] 8003d4a: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOC_CLK_ENABLE(); 8003d4c: 4b3a ldr r3, [pc, #232] @ (8003e38 ) 8003d4e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d52: 4a39 ldr r2, [pc, #228] @ (8003e38 ) 8003d54: f043 0304 orr.w r3, r3, #4 8003d58: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003d5c: 4b36 ldr r3, [pc, #216] @ (8003e38 ) 8003d5e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d62: f003 0304 and.w r3, r3, #4 8003d66: 61bb str r3, [r7, #24] 8003d68: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 8003d6a: 4b33 ldr r3, [pc, #204] @ (8003e38 ) 8003d6c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d70: 4a31 ldr r2, [pc, #196] @ (8003e38 ) 8003d72: f043 0302 orr.w r3, r3, #2 8003d76: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003d7a: 4b2f ldr r3, [pc, #188] @ (8003e38 ) 8003d7c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d80: f003 0302 and.w r3, r3, #2 8003d84: 617b str r3, [r7, #20] 8003d86: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_6; 8003d88: 2340 movs r3, #64 @ 0x40 8003d8a: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003d8c: 2303 movs r3, #3 8003d8e: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003d90: 2300 movs r3, #0 8003d92: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003d94: f107 0334 add.w r3, r7, #52 @ 0x34 8003d98: 4619 mov r1, r3 8003d9a: 4828 ldr r0, [pc, #160] @ (8003e3c ) 8003d9c: f007 f8e0 bl 800af60 GPIO_InitStruct.Pin = GPIO_PIN_4; 8003da0: 2310 movs r3, #16 8003da2: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003da4: 2303 movs r3, #3 8003da6: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003da8: 2300 movs r3, #0 8003daa: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003dac: f107 0334 add.w r3, r7, #52 @ 0x34 8003db0: 4619 mov r1, r3 8003db2: 4823 ldr r0, [pc, #140] @ (8003e40 ) 8003db4: f007 f8d4 bl 800af60 GPIO_InitStruct.Pin = GPIO_PIN_1; 8003db8: 2302 movs r3, #2 8003dba: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003dbc: 2303 movs r3, #3 8003dbe: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003dc0: 2300 movs r3, #0 8003dc2: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003dc4: f107 0334 add.w r3, r7, #52 @ 0x34 8003dc8: 4619 mov r1, r3 8003dca: 481e ldr r0, [pc, #120] @ (8003e44 ) 8003dcc: f007 f8c8 bl 800af60 hdma_adc2.Instance = DMA1_Stream1; 8003dd0: 4b20 ldr r3, [pc, #128] @ (8003e54 ) 8003dd2: 4a21 ldr r2, [pc, #132] @ (8003e58 ) 8003dd4: 601a str r2, [r3, #0] hdma_adc2.Init.Request = DMA_REQUEST_ADC2; 8003dd6: 4b1f ldr r3, [pc, #124] @ (8003e54 ) 8003dd8: 220a movs r2, #10 8003dda: 605a str r2, [r3, #4] hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003ddc: 4b1d ldr r3, [pc, #116] @ (8003e54 ) 8003dde: 2200 movs r2, #0 8003de0: 609a str r2, [r3, #8] hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; 8003de2: 4b1c ldr r3, [pc, #112] @ (8003e54 ) 8003de4: 2200 movs r2, #0 8003de6: 60da str r2, [r3, #12] hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; 8003de8: 4b1a ldr r3, [pc, #104] @ (8003e54 ) 8003dea: f44f 6280 mov.w r2, #1024 @ 0x400 8003dee: 611a str r2, [r3, #16] hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8003df0: 4b18 ldr r3, [pc, #96] @ (8003e54 ) 8003df2: f44f 6200 mov.w r2, #2048 @ 0x800 8003df6: 615a str r2, [r3, #20] hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8003df8: 4b16 ldr r3, [pc, #88] @ (8003e54 ) 8003dfa: f44f 5200 mov.w r2, #8192 @ 0x2000 8003dfe: 619a str r2, [r3, #24] hdma_adc2.Init.Mode = DMA_NORMAL; 8003e00: 4b14 ldr r3, [pc, #80] @ (8003e54 ) 8003e02: 2200 movs r2, #0 8003e04: 61da str r2, [r3, #28] hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; 8003e06: 4b13 ldr r3, [pc, #76] @ (8003e54 ) 8003e08: 2200 movs r2, #0 8003e0a: 621a str r2, [r3, #32] hdma_adc2.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003e0c: 4b11 ldr r3, [pc, #68] @ (8003e54 ) 8003e0e: 2200 movs r2, #0 8003e10: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) 8003e12: 4810 ldr r0, [pc, #64] @ (8003e54 ) 8003e14: f004 fa68 bl 80082e8 8003e18: 4603 mov r3, r0 8003e1a: 2b00 cmp r3, #0 8003e1c: d001 beq.n 8003e22 Error_Handler(); 8003e1e: f7fd fed5 bl 8001bcc __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2); 8003e22: 687b ldr r3, [r7, #4] 8003e24: 4a0b ldr r2, [pc, #44] @ (8003e54 ) 8003e26: 64da str r2, [r3, #76] @ 0x4c 8003e28: 4a0a ldr r2, [pc, #40] @ (8003e54 ) 8003e2a: 687b ldr r3, [r7, #4] 8003e2c: 6393 str r3, [r2, #56] @ 0x38 } 8003e2e: e07f b.n 8003f30 8003e30: 40022000 .word 0x40022000 8003e34: 24000934 .word 0x24000934 8003e38: 58024400 .word 0x58024400 8003e3c: 58020000 .word 0x58020000 8003e40: 58020800 .word 0x58020800 8003e44: 58020400 .word 0x58020400 8003e48: 2400026c .word 0x2400026c 8003e4c: 40020010 .word 0x40020010 8003e50: 40022100 .word 0x40022100 8003e54: 240002e4 .word 0x240002e4 8003e58: 40020028 .word 0x40020028 else if(hadc->Instance==ADC3) 8003e5c: 687b ldr r3, [r7, #4] 8003e5e: 681b ldr r3, [r3, #0] 8003e60: 4a35 ldr r2, [pc, #212] @ (8003f38 ) 8003e62: 4293 cmp r3, r2 8003e64: d164 bne.n 8003f30 __HAL_RCC_ADC3_CLK_ENABLE(); 8003e66: 4b35 ldr r3, [pc, #212] @ (8003f3c ) 8003e68: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e6c: 4a33 ldr r2, [pc, #204] @ (8003f3c ) 8003e6e: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8003e72: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003e76: 4b31 ldr r3, [pc, #196] @ (8003f3c ) 8003e78: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e7c: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8003e80: 613b str r3, [r7, #16] 8003e82: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 8003e84: 4b2d ldr r3, [pc, #180] @ (8003f3c ) 8003e86: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e8a: 4a2c ldr r2, [pc, #176] @ (8003f3c ) 8003e8c: f043 0304 orr.w r3, r3, #4 8003e90: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003e94: 4b29 ldr r3, [pc, #164] @ (8003f3c ) 8003e96: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e9a: f003 0304 and.w r3, r3, #4 8003e9e: 60fb str r3, [r7, #12] 8003ea0: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8003ea2: 2303 movs r3, #3 8003ea4: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003ea6: 2303 movs r3, #3 8003ea8: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003eaa: 2300 movs r3, #0 8003eac: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003eae: f107 0334 add.w r3, r7, #52 @ 0x34 8003eb2: 4619 mov r1, r3 8003eb4: 4822 ldr r0, [pc, #136] @ (8003f40 ) 8003eb6: f007 f853 bl 800af60 HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC2, SYSCFG_SWITCH_PC2_OPEN); 8003eba: f04f 6180 mov.w r1, #67108864 @ 0x4000000 8003ebe: f04f 6080 mov.w r0, #67108864 @ 0x4000000 8003ec2: f001 feb1 bl 8005c28 HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC3, SYSCFG_SWITCH_PC3_OPEN); 8003ec6: f04f 6100 mov.w r1, #134217728 @ 0x8000000 8003eca: f04f 6000 mov.w r0, #134217728 @ 0x8000000 8003ece: f001 feab bl 8005c28 hdma_adc3.Instance = DMA1_Stream2; 8003ed2: 4b1c ldr r3, [pc, #112] @ (8003f44 ) 8003ed4: 4a1c ldr r2, [pc, #112] @ (8003f48 ) 8003ed6: 601a str r2, [r3, #0] hdma_adc3.Init.Request = DMA_REQUEST_ADC3; 8003ed8: 4b1a ldr r3, [pc, #104] @ (8003f44 ) 8003eda: 2273 movs r2, #115 @ 0x73 8003edc: 605a str r2, [r3, #4] hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003ede: 4b19 ldr r3, [pc, #100] @ (8003f44 ) 8003ee0: 2200 movs r2, #0 8003ee2: 609a str r2, [r3, #8] hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE; 8003ee4: 4b17 ldr r3, [pc, #92] @ (8003f44 ) 8003ee6: 2200 movs r2, #0 8003ee8: 60da str r2, [r3, #12] hdma_adc3.Init.MemInc = DMA_MINC_ENABLE; 8003eea: 4b16 ldr r3, [pc, #88] @ (8003f44 ) 8003eec: f44f 6280 mov.w r2, #1024 @ 0x400 8003ef0: 611a str r2, [r3, #16] hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8003ef2: 4b14 ldr r3, [pc, #80] @ (8003f44 ) 8003ef4: f44f 6200 mov.w r2, #2048 @ 0x800 8003ef8: 615a str r2, [r3, #20] hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8003efa: 4b12 ldr r3, [pc, #72] @ (8003f44 ) 8003efc: f44f 5200 mov.w r2, #8192 @ 0x2000 8003f00: 619a str r2, [r3, #24] hdma_adc3.Init.Mode = DMA_NORMAL; 8003f02: 4b10 ldr r3, [pc, #64] @ (8003f44 ) 8003f04: 2200 movs r2, #0 8003f06: 61da str r2, [r3, #28] hdma_adc3.Init.Priority = DMA_PRIORITY_LOW; 8003f08: 4b0e ldr r3, [pc, #56] @ (8003f44 ) 8003f0a: 2200 movs r2, #0 8003f0c: 621a str r2, [r3, #32] hdma_adc3.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003f0e: 4b0d ldr r3, [pc, #52] @ (8003f44 ) 8003f10: 2200 movs r2, #0 8003f12: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc3) != HAL_OK) 8003f14: 480b ldr r0, [pc, #44] @ (8003f44 ) 8003f16: f004 f9e7 bl 80082e8 8003f1a: 4603 mov r3, r0 8003f1c: 2b00 cmp r3, #0 8003f1e: d001 beq.n 8003f24 Error_Handler(); 8003f20: f7fd fe54 bl 8001bcc __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc3); 8003f24: 687b ldr r3, [r7, #4] 8003f26: 4a07 ldr r2, [pc, #28] @ (8003f44 ) 8003f28: 64da str r2, [r3, #76] @ 0x4c 8003f2a: 4a06 ldr r2, [pc, #24] @ (8003f44 ) 8003f2c: 687b ldr r3, [r7, #4] 8003f2e: 6393 str r3, [r2, #56] @ 0x38 } 8003f30: bf00 nop 8003f32: 3748 adds r7, #72 @ 0x48 8003f34: 46bd mov sp, r7 8003f36: bd80 pop {r7, pc} 8003f38: 58026000 .word 0x58026000 8003f3c: 58024400 .word 0x58024400 8003f40: 58020800 .word 0x58020800 8003f44: 2400035c .word 0x2400035c 8003f48: 40020040 .word 0x40020040 08003f4c : * This function configures the hardware resources used in this example * @param hcomp: COMP handle pointer * @retval None */ void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp) { 8003f4c: b580 push {r7, lr} 8003f4e: b08a sub sp, #40 @ 0x28 8003f50: af00 add r7, sp, #0 8003f52: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003f54: f107 0314 add.w r3, r7, #20 8003f58: 2200 movs r2, #0 8003f5a: 601a str r2, [r3, #0] 8003f5c: 605a str r2, [r3, #4] 8003f5e: 609a str r2, [r3, #8] 8003f60: 60da str r2, [r3, #12] 8003f62: 611a str r2, [r3, #16] if(hcomp->Instance==COMP1) 8003f64: 687b ldr r3, [r7, #4] 8003f66: 681b ldr r3, [r3, #0] 8003f68: 4a18 ldr r2, [pc, #96] @ (8003fcc ) 8003f6a: 4293 cmp r3, r2 8003f6c: d129 bne.n 8003fc2 { /* USER CODE BEGIN COMP1_MspInit 0 */ /* USER CODE END COMP1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_COMP12_CLK_ENABLE(); 8003f6e: 4b18 ldr r3, [pc, #96] @ (8003fd0 ) 8003f70: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003f74: 4a16 ldr r2, [pc, #88] @ (8003fd0 ) 8003f76: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8003f7a: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8003f7e: 4b14 ldr r3, [pc, #80] @ (8003fd0 ) 8003f80: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003f84: f403 4380 and.w r3, r3, #16384 @ 0x4000 8003f88: 613b str r3, [r7, #16] 8003f8a: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8003f8c: 4b10 ldr r3, [pc, #64] @ (8003fd0 ) 8003f8e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003f92: 4a0f ldr r2, [pc, #60] @ (8003fd0 ) 8003f94: f043 0302 orr.w r3, r3, #2 8003f98: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003f9c: 4b0c ldr r3, [pc, #48] @ (8003fd0 ) 8003f9e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003fa2: f003 0302 and.w r3, r3, #2 8003fa6: 60fb str r3, [r7, #12] 8003fa8: 68fb ldr r3, [r7, #12] /**COMP1 GPIO Configuration PB2 ------> COMP1_INP */ GPIO_InitStruct.Pin = GPIO_PIN_2; 8003faa: 2304 movs r3, #4 8003fac: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003fae: 2303 movs r3, #3 8003fb0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003fb2: 2300 movs r3, #0 8003fb4: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003fb6: f107 0314 add.w r3, r7, #20 8003fba: 4619 mov r1, r3 8003fbc: 4805 ldr r0, [pc, #20] @ (8003fd4 ) 8003fbe: f006 ffcf bl 800af60 /* USER CODE BEGIN COMP1_MspInit 1 */ /* USER CODE END COMP1_MspInit 1 */ } } 8003fc2: bf00 nop 8003fc4: 3728 adds r7, #40 @ 0x28 8003fc6: 46bd mov sp, r7 8003fc8: bd80 pop {r7, pc} 8003fca: bf00 nop 8003fcc: 5800380c .word 0x5800380c 8003fd0: 58024400 .word 0x58024400 8003fd4: 58020400 .word 0x58020400 08003fd8 : * This function configures the hardware resources used in this example * @param hcrc: CRC handle pointer * @retval None */ void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) { 8003fd8: b480 push {r7} 8003fda: b085 sub sp, #20 8003fdc: af00 add r7, sp, #0 8003fde: 6078 str r0, [r7, #4] if(hcrc->Instance==CRC) 8003fe0: 687b ldr r3, [r7, #4] 8003fe2: 681b ldr r3, [r3, #0] 8003fe4: 4a0b ldr r2, [pc, #44] @ (8004014 ) 8003fe6: 4293 cmp r3, r2 8003fe8: d10e bne.n 8004008 { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 8003fea: 4b0b ldr r3, [pc, #44] @ (8004018 ) 8003fec: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003ff0: 4a09 ldr r2, [pc, #36] @ (8004018 ) 8003ff2: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8003ff6: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003ffa: 4b07 ldr r3, [pc, #28] @ (8004018 ) 8003ffc: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004000: f403 2300 and.w r3, r3, #524288 @ 0x80000 8004004: 60fb str r3, [r7, #12] 8004006: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 8004008: bf00 nop 800400a: 3714 adds r7, #20 800400c: 46bd mov sp, r7 800400e: f85d 7b04 ldr.w r7, [sp], #4 8004012: 4770 bx lr 8004014: 58024c00 .word 0x58024c00 8004018: 58024400 .word 0x58024400 0800401c : * This function configures the hardware resources used in this example * @param hdac: DAC handle pointer * @retval None */ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) { 800401c: b580 push {r7, lr} 800401e: b08a sub sp, #40 @ 0x28 8004020: af00 add r7, sp, #0 8004022: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004024: f107 0314 add.w r3, r7, #20 8004028: 2200 movs r2, #0 800402a: 601a str r2, [r3, #0] 800402c: 605a str r2, [r3, #4] 800402e: 609a str r2, [r3, #8] 8004030: 60da str r2, [r3, #12] 8004032: 611a str r2, [r3, #16] if(hdac->Instance==DAC1) 8004034: 687b ldr r3, [r7, #4] 8004036: 681b ldr r3, [r3, #0] 8004038: 4a1c ldr r2, [pc, #112] @ (80040ac ) 800403a: 4293 cmp r3, r2 800403c: d131 bne.n 80040a2 { /* USER CODE BEGIN DAC1_MspInit 0 */ /* USER CODE END DAC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DAC12_CLK_ENABLE(); 800403e: 4b1c ldr r3, [pc, #112] @ (80040b0 ) 8004040: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004044: 4a1a ldr r2, [pc, #104] @ (80040b0 ) 8004046: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 800404a: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 800404e: 4b18 ldr r3, [pc, #96] @ (80040b0 ) 8004050: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004054: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004058: 613b str r3, [r7, #16] 800405a: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800405c: 4b14 ldr r3, [pc, #80] @ (80040b0 ) 800405e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004062: 4a13 ldr r2, [pc, #76] @ (80040b0 ) 8004064: f043 0301 orr.w r3, r3, #1 8004068: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800406c: 4b10 ldr r3, [pc, #64] @ (80040b0 ) 800406e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004072: f003 0301 and.w r3, r3, #1 8004076: 60fb str r3, [r7, #12] 8004078: 68fb ldr r3, [r7, #12] /**DAC1 GPIO Configuration PA4 ------> DAC1_OUT1 PA5 ------> DAC1_OUT2 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 800407a: 2330 movs r3, #48 @ 0x30 800407c: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 800407e: 2303 movs r3, #3 8004080: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004082: 2300 movs r3, #0 8004084: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8004086: f107 0314 add.w r3, r7, #20 800408a: 4619 mov r1, r3 800408c: 4809 ldr r0, [pc, #36] @ (80040b4 ) 800408e: f006 ff67 bl 800af60 /* DAC1 interrupt Init */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 5, 0); 8004092: 2200 movs r2, #0 8004094: 2105 movs r1, #5 8004096: 2036 movs r0, #54 @ 0x36 8004098: f003 fc30 bl 80078fc HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 800409c: 2036 movs r0, #54 @ 0x36 800409e: f003 fc47 bl 8007930 /* USER CODE BEGIN DAC1_MspInit 1 */ /* USER CODE END DAC1_MspInit 1 */ } } 80040a2: bf00 nop 80040a4: 3728 adds r7, #40 @ 0x28 80040a6: 46bd mov sp, r7 80040a8: bd80 pop {r7, pc} 80040aa: bf00 nop 80040ac: 40007400 .word 0x40007400 80040b0: 58024400 .word 0x58024400 80040b4: 58020000 .word 0x58020000 080040b8 : * This function configures the hardware resources used in this example * @param hrng: RNG handle pointer * @retval None */ void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) { 80040b8: b580 push {r7, lr} 80040ba: b0b4 sub sp, #208 @ 0xd0 80040bc: af00 add r7, sp, #0 80040be: 6078 str r0, [r7, #4] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 80040c0: f107 0310 add.w r3, r7, #16 80040c4: 22c0 movs r2, #192 @ 0xc0 80040c6: 2100 movs r1, #0 80040c8: 4618 mov r0, r3 80040ca: f013 fddf bl 8017c8c if(hrng->Instance==RNG) 80040ce: 687b ldr r3, [r7, #4] 80040d0: 681b ldr r3, [r3, #0] 80040d2: 4a14 ldr r2, [pc, #80] @ (8004124 ) 80040d4: 4293 cmp r3, r2 80040d6: d121 bne.n 800411c /* USER CODE END RNG_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG; 80040d8: f44f 3200 mov.w r2, #131072 @ 0x20000 80040dc: f04f 0300 mov.w r3, #0 80040e0: e9c7 2304 strd r2, r3, [r7, #16] PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48; 80040e4: 2300 movs r3, #0 80040e6: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80040ea: f107 0310 add.w r3, r7, #16 80040ee: 4618 mov r0, r3 80040f0: f008 fabe bl 800c670 80040f4: 4603 mov r3, r0 80040f6: 2b00 cmp r3, #0 80040f8: d001 beq.n 80040fe { Error_Handler(); 80040fa: f7fd fd67 bl 8001bcc } /* Peripheral clock enable */ __HAL_RCC_RNG_CLK_ENABLE(); 80040fe: 4b0a ldr r3, [pc, #40] @ (8004128 ) 8004100: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 8004104: 4a08 ldr r2, [pc, #32] @ (8004128 ) 8004106: f043 0340 orr.w r3, r3, #64 @ 0x40 800410a: f8c2 30dc str.w r3, [r2, #220] @ 0xdc 800410e: 4b06 ldr r3, [pc, #24] @ (8004128 ) 8004110: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 8004114: f003 0340 and.w r3, r3, #64 @ 0x40 8004118: 60fb str r3, [r7, #12] 800411a: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN RNG_MspInit 1 */ /* USER CODE END RNG_MspInit 1 */ } } 800411c: bf00 nop 800411e: 37d0 adds r7, #208 @ 0xd0 8004120: 46bd mov sp, r7 8004122: bd80 pop {r7, pc} 8004124: 48021800 .word 0x48021800 8004128: 58024400 .word 0x58024400 0800412c : * This function configures the hardware resources used in this example * @param htim_pwm: TIM_PWM handle pointer * @retval None */ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) { 800412c: b480 push {r7} 800412e: b085 sub sp, #20 8004130: af00 add r7, sp, #0 8004132: 6078 str r0, [r7, #4] if(htim_pwm->Instance==TIM1) 8004134: 687b ldr r3, [r7, #4] 8004136: 681b ldr r3, [r3, #0] 8004138: 4a16 ldr r2, [pc, #88] @ (8004194 ) 800413a: 4293 cmp r3, r2 800413c: d10f bne.n 800415e { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 800413e: 4b16 ldr r3, [pc, #88] @ (8004198 ) 8004140: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8004144: 4a14 ldr r2, [pc, #80] @ (8004198 ) 8004146: f043 0301 orr.w r3, r3, #1 800414a: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 800414e: 4b12 ldr r3, [pc, #72] @ (8004198 ) 8004150: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8004154: f003 0301 and.w r3, r3, #1 8004158: 60fb str r3, [r7, #12] 800415a: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 800415c: e013 b.n 8004186 else if(htim_pwm->Instance==TIM3) 800415e: 687b ldr r3, [r7, #4] 8004160: 681b ldr r3, [r3, #0] 8004162: 4a0e ldr r2, [pc, #56] @ (800419c ) 8004164: 4293 cmp r3, r2 8004166: d10e bne.n 8004186 __HAL_RCC_TIM3_CLK_ENABLE(); 8004168: 4b0b ldr r3, [pc, #44] @ (8004198 ) 800416a: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800416e: 4a0a ldr r2, [pc, #40] @ (8004198 ) 8004170: f043 0302 orr.w r3, r3, #2 8004174: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8004178: 4b07 ldr r3, [pc, #28] @ (8004198 ) 800417a: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800417e: f003 0302 and.w r3, r3, #2 8004182: 60bb str r3, [r7, #8] 8004184: 68bb ldr r3, [r7, #8] } 8004186: bf00 nop 8004188: 3714 adds r7, #20 800418a: 46bd mov sp, r7 800418c: f85d 7b04 ldr.w r7, [sp], #4 8004190: 4770 bx lr 8004192: bf00 nop 8004194: 40010000 .word 0x40010000 8004198: 58024400 .word 0x58024400 800419c: 40000400 .word 0x40000400 080041a0 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 80041a0: b480 push {r7} 80041a2: b085 sub sp, #20 80041a4: af00 add r7, sp, #0 80041a6: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM8) 80041a8: 687b ldr r3, [r7, #4] 80041aa: 681b ldr r3, [r3, #0] 80041ac: 4a0b ldr r2, [pc, #44] @ (80041dc ) 80041ae: 4293 cmp r3, r2 80041b0: d10e bne.n 80041d0 { /* USER CODE BEGIN TIM8_MspInit 0 */ /* USER CODE END TIM8_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM8_CLK_ENABLE(); 80041b2: 4b0b ldr r3, [pc, #44] @ (80041e0 ) 80041b4: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80041b8: 4a09 ldr r2, [pc, #36] @ (80041e0 ) 80041ba: f043 0302 orr.w r3, r3, #2 80041be: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 80041c2: 4b07 ldr r3, [pc, #28] @ (80041e0 ) 80041c4: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80041c8: f003 0302 and.w r3, r3, #2 80041cc: 60fb str r3, [r7, #12] 80041ce: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM8_MspInit 1 */ /* USER CODE END TIM8_MspInit 1 */ } } 80041d0: bf00 nop 80041d2: 3714 adds r7, #20 80041d4: 46bd mov sp, r7 80041d6: f85d 7b04 ldr.w r7, [sp], #4 80041da: 4770 bx lr 80041dc: 40010400 .word 0x40010400 80041e0: 58024400 .word 0x58024400 080041e4 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 80041e4: b580 push {r7, lr} 80041e6: b08a sub sp, #40 @ 0x28 80041e8: af00 add r7, sp, #0 80041ea: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80041ec: f107 0314 add.w r3, r7, #20 80041f0: 2200 movs r2, #0 80041f2: 601a str r2, [r3, #0] 80041f4: 605a str r2, [r3, #4] 80041f6: 609a str r2, [r3, #8] 80041f8: 60da str r2, [r3, #12] 80041fa: 611a str r2, [r3, #16] if(htim->Instance==TIM1) 80041fc: 687b ldr r3, [r7, #4] 80041fe: 681b ldr r3, [r3, #0] 8004200: 4a26 ldr r2, [pc, #152] @ (800429c ) 8004202: 4293 cmp r3, r2 8004204: d120 bne.n 8004248 { /* USER CODE BEGIN TIM1_MspPostInit 0 */ /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8004206: 4b26 ldr r3, [pc, #152] @ (80042a0 ) 8004208: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800420c: 4a24 ldr r2, [pc, #144] @ (80042a0 ) 800420e: f043 0301 orr.w r3, r3, #1 8004212: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004216: 4b22 ldr r3, [pc, #136] @ (80042a0 ) 8004218: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800421c: f003 0301 and.w r3, r3, #1 8004220: 613b str r3, [r7, #16] 8004222: 693b ldr r3, [r7, #16] /**TIM1 GPIO Configuration PA9 ------> TIM1_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_9; 8004224: f44f 7300 mov.w r3, #512 @ 0x200 8004228: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800422a: 2302 movs r3, #2 800422c: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800422e: 2300 movs r3, #0 8004230: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8004232: 2300 movs r3, #0 8004234: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; 8004236: 2301 movs r3, #1 8004238: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800423a: f107 0314 add.w r3, r7, #20 800423e: 4619 mov r1, r3 8004240: 4818 ldr r0, [pc, #96] @ (80042a4 ) 8004242: f006 fe8d bl 800af60 /* USER CODE BEGIN TIM3_MspPostInit 1 */ /* USER CODE END TIM3_MspPostInit 1 */ } } 8004246: e024 b.n 8004292 else if(htim->Instance==TIM3) 8004248: 687b ldr r3, [r7, #4] 800424a: 681b ldr r3, [r3, #0] 800424c: 4a16 ldr r2, [pc, #88] @ (80042a8 ) 800424e: 4293 cmp r3, r2 8004250: d11f bne.n 8004292 __HAL_RCC_GPIOC_CLK_ENABLE(); 8004252: 4b13 ldr r3, [pc, #76] @ (80042a0 ) 8004254: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004258: 4a11 ldr r2, [pc, #68] @ (80042a0 ) 800425a: f043 0304 orr.w r3, r3, #4 800425e: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004262: 4b0f ldr r3, [pc, #60] @ (80042a0 ) 8004264: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004268: f003 0304 and.w r3, r3, #4 800426c: 60fb str r3, [r7, #12] 800426e: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 8004270: f44f 7370 mov.w r3, #960 @ 0x3c0 8004274: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004276: 2302 movs r3, #2 8004278: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800427a: 2300 movs r3, #0 800427c: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 800427e: 2301 movs r3, #1 8004280: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 8004282: 2302 movs r3, #2 8004284: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8004286: f107 0314 add.w r3, r7, #20 800428a: 4619 mov r1, r3 800428c: 4807 ldr r0, [pc, #28] @ (80042ac ) 800428e: f006 fe67 bl 800af60 } 8004292: bf00 nop 8004294: 3728 adds r7, #40 @ 0x28 8004296: 46bd mov sp, r7 8004298: bd80 pop {r7, pc} 800429a: bf00 nop 800429c: 40010000 .word 0x40010000 80042a0: 58024400 .word 0x58024400 80042a4: 58020000 .word 0x58020000 80042a8: 40000400 .word 0x40000400 80042ac: 58020800 .word 0x58020800 080042b0 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 80042b0: b580 push {r7, lr} 80042b2: b0bc sub sp, #240 @ 0xf0 80042b4: af00 add r7, sp, #0 80042b6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80042b8: f107 03dc add.w r3, r7, #220 @ 0xdc 80042bc: 2200 movs r2, #0 80042be: 601a str r2, [r3, #0] 80042c0: 605a str r2, [r3, #4] 80042c2: 609a str r2, [r3, #8] 80042c4: 60da str r2, [r3, #12] 80042c6: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 80042c8: f107 0318 add.w r3, r7, #24 80042cc: 22c0 movs r2, #192 @ 0xc0 80042ce: 2100 movs r1, #0 80042d0: 4618 mov r0, r3 80042d2: f013 fcdb bl 8017c8c if(huart->Instance==UART8) 80042d6: 687b ldr r3, [r7, #4] 80042d8: 681b ldr r3, [r3, #0] 80042da: 4a55 ldr r2, [pc, #340] @ (8004430 ) 80042dc: 4293 cmp r3, r2 80042de: d14e bne.n 800437e /* USER CODE END UART8_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8; 80042e0: f04f 0202 mov.w r2, #2 80042e4: f04f 0300 mov.w r3, #0 80042e8: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 80042ec: 2300 movs r3, #0 80042ee: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80042f2: f107 0318 add.w r3, r7, #24 80042f6: 4618 mov r0, r3 80042f8: f008 f9ba bl 800c670 80042fc: 4603 mov r3, r0 80042fe: 2b00 cmp r3, #0 8004300: d001 beq.n 8004306 { Error_Handler(); 8004302: f7fd fc63 bl 8001bcc } /* Peripheral clock enable */ __HAL_RCC_UART8_CLK_ENABLE(); 8004306: 4b4b ldr r3, [pc, #300] @ (8004434 ) 8004308: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800430c: 4a49 ldr r2, [pc, #292] @ (8004434 ) 800430e: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8004312: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8004316: 4b47 ldr r3, [pc, #284] @ (8004434 ) 8004318: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800431c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8004320: 617b str r3, [r7, #20] 8004322: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOE_CLK_ENABLE(); 8004324: 4b43 ldr r3, [pc, #268] @ (8004434 ) 8004326: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800432a: 4a42 ldr r2, [pc, #264] @ (8004434 ) 800432c: f043 0310 orr.w r3, r3, #16 8004330: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004334: 4b3f ldr r3, [pc, #252] @ (8004434 ) 8004336: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800433a: f003 0310 and.w r3, r3, #16 800433e: 613b str r3, [r7, #16] 8004340: 693b ldr r3, [r7, #16] /**UART8 GPIO Configuration PE0 ------> UART8_RX PE1 ------> UART8_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8004342: 2303 movs r3, #3 8004344: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004348: 2302 movs r3, #2 800434a: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 800434e: 2300 movs r3, #0 8004350: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8004354: 2300 movs r3, #0 8004356: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF8_UART8; 800435a: 2308 movs r3, #8 800435c: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8004360: f107 03dc add.w r3, r7, #220 @ 0xdc 8004364: 4619 mov r1, r3 8004366: 4834 ldr r0, [pc, #208] @ (8004438 ) 8004368: f006 fdfa bl 800af60 /* UART8 interrupt Init */ HAL_NVIC_SetPriority(UART8_IRQn, 5, 0); 800436c: 2200 movs r2, #0 800436e: 2105 movs r1, #5 8004370: 2053 movs r0, #83 @ 0x53 8004372: f003 fac3 bl 80078fc HAL_NVIC_EnableIRQ(UART8_IRQn); 8004376: 2053 movs r0, #83 @ 0x53 8004378: f003 fada bl 8007930 /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 800437c: e053 b.n 8004426 else if(huart->Instance==USART1) 800437e: 687b ldr r3, [r7, #4] 8004380: 681b ldr r3, [r3, #0] 8004382: 4a2e ldr r2, [pc, #184] @ (800443c ) 8004384: 4293 cmp r3, r2 8004386: d14e bne.n 8004426 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; 8004388: f04f 0201 mov.w r2, #1 800438c: f04f 0300 mov.w r3, #0 8004390: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; 8004394: 2300 movs r3, #0 8004396: f8c7 3094 str.w r3, [r7, #148] @ 0x94 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800439a: f107 0318 add.w r3, r7, #24 800439e: 4618 mov r0, r3 80043a0: f008 f966 bl 800c670 80043a4: 4603 mov r3, r0 80043a6: 2b00 cmp r3, #0 80043a8: d001 beq.n 80043ae Error_Handler(); 80043aa: f7fd fc0f bl 8001bcc __HAL_RCC_USART1_CLK_ENABLE(); 80043ae: 4b21 ldr r3, [pc, #132] @ (8004434 ) 80043b0: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80043b4: 4a1f ldr r2, [pc, #124] @ (8004434 ) 80043b6: f043 0310 orr.w r3, r3, #16 80043ba: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 80043be: 4b1d ldr r3, [pc, #116] @ (8004434 ) 80043c0: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80043c4: f003 0310 and.w r3, r3, #16 80043c8: 60fb str r3, [r7, #12] 80043ca: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 80043cc: 4b19 ldr r3, [pc, #100] @ (8004434 ) 80043ce: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80043d2: 4a18 ldr r2, [pc, #96] @ (8004434 ) 80043d4: f043 0302 orr.w r3, r3, #2 80043d8: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80043dc: 4b15 ldr r3, [pc, #84] @ (8004434 ) 80043de: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80043e2: f003 0302 and.w r3, r3, #2 80043e6: 60bb str r3, [r7, #8] 80043e8: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 80043ea: f44f 4340 mov.w r3, #49152 @ 0xc000 80043ee: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80043f2: 2302 movs r3, #2 80043f4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 80043f8: 2300 movs r3, #0 80043fa: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80043fe: 2300 movs r3, #0 8004400: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF4_USART1; 8004404: 2304 movs r3, #4 8004406: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800440a: f107 03dc add.w r3, r7, #220 @ 0xdc 800440e: 4619 mov r1, r3 8004410: 480b ldr r0, [pc, #44] @ (8004440 ) 8004412: f006 fda5 bl 800af60 HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 8004416: 2200 movs r2, #0 8004418: 2105 movs r1, #5 800441a: 2025 movs r0, #37 @ 0x25 800441c: f003 fa6e bl 80078fc HAL_NVIC_EnableIRQ(USART1_IRQn); 8004420: 2025 movs r0, #37 @ 0x25 8004422: f003 fa85 bl 8007930 } 8004426: bf00 nop 8004428: 37f0 adds r7, #240 @ 0xf0 800442a: 46bd mov sp, r7 800442c: bd80 pop {r7, pc} 800442e: bf00 nop 8004430: 40007c00 .word 0x40007c00 8004434: 58024400 .word 0x58024400 8004438: 58021000 .word 0x58021000 800443c: 40011000 .word 0x40011000 8004440: 58020400 .word 0x58020400 08004444 : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8004444: b580 push {r7, lr} 8004446: b090 sub sp, #64 @ 0x40 8004448: af00 add r7, sp, #0 800444a: 6078 str r0, [r7, #4] uint32_t uwTimclock, uwAPB1Prescaler; uint32_t uwPrescalerValue; uint32_t pFLatency; /*Configure the TIM6 IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800444c: 687b ldr r3, [r7, #4] 800444e: 2b0f cmp r3, #15 8004450: d827 bhi.n 80044a2 { HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U); 8004452: 2200 movs r2, #0 8004454: 6879 ldr r1, [r7, #4] 8004456: 2036 movs r0, #54 @ 0x36 8004458: f003 fa50 bl 80078fc /* Enable the TIM6 global Interrupt */ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 800445c: 2036 movs r0, #54 @ 0x36 800445e: f003 fa67 bl 8007930 uwTickPrio = TickPriority; 8004462: 4a29 ldr r2, [pc, #164] @ (8004508 ) 8004464: 687b ldr r3, [r7, #4] 8004466: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Enable TIM6 clock */ __HAL_RCC_TIM6_CLK_ENABLE(); 8004468: 4b28 ldr r3, [pc, #160] @ (800450c ) 800446a: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800446e: 4a27 ldr r2, [pc, #156] @ (800450c ) 8004470: f043 0310 orr.w r3, r3, #16 8004474: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8004478: 4b24 ldr r3, [pc, #144] @ (800450c ) 800447a: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800447e: f003 0310 and.w r3, r3, #16 8004482: 60fb str r3, [r7, #12] 8004484: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 8004486: f107 0210 add.w r2, r7, #16 800448a: f107 0314 add.w r3, r7, #20 800448e: 4611 mov r1, r2 8004490: 4618 mov r0, r3 8004492: f008 f8ab bl 800c5ec /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; 8004496: 6abb ldr r3, [r7, #40] @ 0x28 8004498: 63bb str r3, [r7, #56] @ 0x38 /* Compute TIM6 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) 800449a: 6bbb ldr r3, [r7, #56] @ 0x38 800449c: 2b00 cmp r3, #0 800449e: d106 bne.n 80044ae 80044a0: e001 b.n 80044a6 return HAL_ERROR; 80044a2: 2301 movs r3, #1 80044a4: e02b b.n 80044fe { uwTimclock = HAL_RCC_GetPCLK1Freq(); 80044a6: f008 f875 bl 800c594 80044aa: 63f8 str r0, [r7, #60] @ 0x3c 80044ac: e004 b.n 80044b8 } else { uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); 80044ae: f008 f871 bl 800c594 80044b2: 4603 mov r3, r0 80044b4: 005b lsls r3, r3, #1 80044b6: 63fb str r3, [r7, #60] @ 0x3c } /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 80044b8: 6bfb ldr r3, [r7, #60] @ 0x3c 80044ba: 4a15 ldr r2, [pc, #84] @ (8004510 ) 80044bc: fba2 2303 umull r2, r3, r2, r3 80044c0: 0c9b lsrs r3, r3, #18 80044c2: 3b01 subs r3, #1 80044c4: 637b str r3, [r7, #52] @ 0x34 /* Initialize TIM6 */ htim6.Instance = TIM6; 80044c6: 4b13 ldr r3, [pc, #76] @ (8004514 ) 80044c8: 4a13 ldr r2, [pc, #76] @ (8004518 ) 80044ca: 601a str r2, [r3, #0] + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up */ htim6.Init.Period = (1000000U / 1000U) - 1U; 80044cc: 4b11 ldr r3, [pc, #68] @ (8004514 ) 80044ce: f240 32e7 movw r2, #999 @ 0x3e7 80044d2: 60da str r2, [r3, #12] htim6.Init.Prescaler = uwPrescalerValue; 80044d4: 4a0f ldr r2, [pc, #60] @ (8004514 ) 80044d6: 6b7b ldr r3, [r7, #52] @ 0x34 80044d8: 6053 str r3, [r2, #4] htim6.Init.ClockDivision = 0; 80044da: 4b0e ldr r3, [pc, #56] @ (8004514 ) 80044dc: 2200 movs r2, #0 80044de: 611a str r2, [r3, #16] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 80044e0: 4b0c ldr r3, [pc, #48] @ (8004514 ) 80044e2: 2200 movs r2, #0 80044e4: 609a str r2, [r3, #8] if(HAL_TIM_Base_Init(&htim6) == HAL_OK) 80044e6: 480b ldr r0, [pc, #44] @ (8004514 ) 80044e8: f00a fe06 bl 800f0f8 80044ec: 4603 mov r3, r0 80044ee: 2b00 cmp r3, #0 80044f0: d104 bne.n 80044fc { /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&htim6); 80044f2: 4808 ldr r0, [pc, #32] @ (8004514 ) 80044f4: f00a fec8 bl 800f288 80044f8: 4603 mov r3, r0 80044fa: e000 b.n 80044fe } /* Return function status */ return HAL_ERROR; 80044fc: 2301 movs r3, #1 } 80044fe: 4618 mov r0, r3 8004500: 3740 adds r7, #64 @ 0x40 8004502: 46bd mov sp, r7 8004504: bd80 pop {r7, pc} 8004506: bf00 nop 8004508: 2400003c .word 0x2400003c 800450c: 58024400 .word 0x58024400 8004510: 431bde83 .word 0x431bde83 8004514: 24000938 .word 0x24000938 8004518: 40001000 .word 0x40001000 0800451c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 800451c: b480 push {r7} 800451e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8004520: bf00 nop 8004522: e7fd b.n 8004520 08004524 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8004524: b480 push {r7} 8004526: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8004528: bf00 nop 800452a: e7fd b.n 8004528 0800452c : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 800452c: b480 push {r7} 800452e: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8004530: bf00 nop 8004532: e7fd b.n 8004530 08004534 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8004534: b480 push {r7} 8004536: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8004538: bf00 nop 800453a: e7fd b.n 8004538 0800453c : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 800453c: b480 push {r7} 800453e: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8004540: bf00 nop 8004542: e7fd b.n 8004540 08004544 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8004544: b480 push {r7} 8004546: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8004548: bf00 nop 800454a: 46bd mov sp, r7 800454c: f85d 7b04 ldr.w r7, [sp], #4 8004550: 4770 bx lr 08004552 : /** * @brief This function handles RCC global interrupt. */ void RCC_IRQHandler(void) { 8004552: b480 push {r7} 8004554: af00 add r7, sp, #0 /* USER CODE END RCC_IRQn 0 */ /* USER CODE BEGIN RCC_IRQn 1 */ /* USER CODE END RCC_IRQn 1 */ } 8004556: bf00 nop 8004558: 46bd mov sp, r7 800455a: f85d 7b04 ldr.w r7, [sp], #4 800455e: 4770 bx lr 08004560 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 8004560: b580 push {r7, lr} 8004562: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 8004564: 4802 ldr r0, [pc, #8] @ (8004570 ) 8004566: f005 f9e9 bl 800993c /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 800456a: bf00 nop 800456c: bd80 pop {r7, pc} 800456e: bf00 nop 8004570: 2400026c .word 0x2400026c 08004574 : /** * @brief This function handles DMA1 stream1 global interrupt. */ void DMA1_Stream1_IRQHandler(void) { 8004574: b580 push {r7, lr} 8004576: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */ /* USER CODE END DMA1_Stream1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc2); 8004578: 4802 ldr r0, [pc, #8] @ (8004584 ) 800457a: f005 f9df bl 800993c /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */ /* USER CODE END DMA1_Stream1_IRQn 1 */ } 800457e: bf00 nop 8004580: bd80 pop {r7, pc} 8004582: bf00 nop 8004584: 240002e4 .word 0x240002e4 08004588 : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 8004588: b580 push {r7, lr} 800458a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc3); 800458c: 4802 ldr r0, [pc, #8] @ (8004598 ) 800458e: f005 f9d5 bl 800993c /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 8004592: bf00 nop 8004594: bd80 pop {r7, pc} 8004596: bf00 nop 8004598: 2400035c .word 0x2400035c 0800459c : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 800459c: b580 push {r7, lr} 800459e: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 80045a0: 4802 ldr r0, [pc, #8] @ (80045ac ) 80045a2: f00c faa9 bl 8010af8 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 80045a6: bf00 nop 80045a8: bd80 pop {r7, pc} 80045aa: bf00 nop 80045ac: 240005c4 .word 0x240005c4 080045b0 : /** * @brief This function handles EXTI line[15:10] interrupts. */ void EXTI15_10_IRQHandler(void) { 80045b0: b580 push {r7, lr} 80045b2: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI15_10_IRQn 0 */ /* USER CODE END EXTI15_10_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10); 80045b4: f44f 6080 mov.w r0, #1024 @ 0x400 80045b8: f006 fecd bl 800b356 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); 80045bc: f44f 6000 mov.w r0, #2048 @ 0x800 80045c0: f006 fec9 bl 800b356 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14); 80045c4: f44f 4080 mov.w r0, #16384 @ 0x4000 80045c8: f006 fec5 bl 800b356 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15); 80045cc: f44f 4000 mov.w r0, #32768 @ 0x8000 80045d0: f006 fec1 bl 800b356 /* USER CODE BEGIN EXTI15_10_IRQn 1 */ /* USER CODE END EXTI15_10_IRQn 1 */ } 80045d4: bf00 nop 80045d6: bd80 pop {r7, pc} 080045d8 : /** * @brief This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 80045d8: b580 push {r7, lr} 80045da: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ if (hdac1.State != HAL_DAC_STATE_RESET) { 80045dc: 4b06 ldr r3, [pc, #24] @ (80045f8 ) 80045de: 791b ldrb r3, [r3, #4] 80045e0: b2db uxtb r3, r3 80045e2: 2b00 cmp r3, #0 80045e4: d002 beq.n 80045ec HAL_DAC_IRQHandler(&hdac1); 80045e6: 4804 ldr r0, [pc, #16] @ (80045f8 ) 80045e8: f003 fca7 bl 8007f3a } HAL_TIM_IRQHandler(&htim6); 80045ec: 4803 ldr r0, [pc, #12] @ (80045fc ) 80045ee: f00b f8bf bl 800f770 /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 80045f2: bf00 nop 80045f4: bd80 pop {r7, pc} 80045f6: bf00 nop 80045f8: 24000424 .word 0x24000424 80045fc: 24000938 .word 0x24000938 08004600 : /** * @brief This function handles UART8 global interrupt. */ void UART8_IRQHandler(void) { 8004600: b580 push {r7, lr} 8004602: af00 add r7, sp, #0 /* USER CODE BEGIN UART8_IRQn 0 */ /* USER CODE END UART8_IRQn 0 */ HAL_UART_IRQHandler(&huart8); 8004604: 4802 ldr r0, [pc, #8] @ (8004610 ) 8004606: f00c fa77 bl 8010af8 /* USER CODE BEGIN UART8_IRQn 1 */ /* USER CODE END UART8_IRQn 1 */ } 800460a: bf00 nop 800460c: bd80 pop {r7, pc} 800460e: bf00 nop 8004610: 24000530 .word 0x24000530 08004614 <_read>: _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8004614: b580 push {r7, lr} 8004616: b086 sub sp, #24 8004618: af00 add r7, sp, #0 800461a: 60f8 str r0, [r7, #12] 800461c: 60b9 str r1, [r7, #8] 800461e: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8004620: 2300 movs r3, #0 8004622: 617b str r3, [r7, #20] 8004624: e00a b.n 800463c <_read+0x28> { *ptr++ = __io_getchar(); 8004626: f3af 8000 nop.w 800462a: 4601 mov r1, r0 800462c: 68bb ldr r3, [r7, #8] 800462e: 1c5a adds r2, r3, #1 8004630: 60ba str r2, [r7, #8] 8004632: b2ca uxtb r2, r1 8004634: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 8004636: 697b ldr r3, [r7, #20] 8004638: 3301 adds r3, #1 800463a: 617b str r3, [r7, #20] 800463c: 697a ldr r2, [r7, #20] 800463e: 687b ldr r3, [r7, #4] 8004640: 429a cmp r2, r3 8004642: dbf0 blt.n 8004626 <_read+0x12> } return len; 8004644: 687b ldr r3, [r7, #4] } 8004646: 4618 mov r0, r3 8004648: 3718 adds r7, #24 800464a: 46bd mov sp, r7 800464c: bd80 pop {r7, pc} 0800464e <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 800464e: b580 push {r7, lr} 8004650: b086 sub sp, #24 8004652: af00 add r7, sp, #0 8004654: 60f8 str r0, [r7, #12] 8004656: 60b9 str r1, [r7, #8] 8004658: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800465a: 2300 movs r3, #0 800465c: 617b str r3, [r7, #20] 800465e: e009 b.n 8004674 <_write+0x26> { __io_putchar(*ptr++); 8004660: 68bb ldr r3, [r7, #8] 8004662: 1c5a adds r2, r3, #1 8004664: 60ba str r2, [r7, #8] 8004666: 781b ldrb r3, [r3, #0] 8004668: 4618 mov r0, r3 800466a: f7fc f84a bl 8000702 <__io_putchar> for (DataIdx = 0; DataIdx < len; DataIdx++) 800466e: 697b ldr r3, [r7, #20] 8004670: 3301 adds r3, #1 8004672: 617b str r3, [r7, #20] 8004674: 697a ldr r2, [r7, #20] 8004676: 687b ldr r3, [r7, #4] 8004678: 429a cmp r2, r3 800467a: dbf1 blt.n 8004660 <_write+0x12> } return len; 800467c: 687b ldr r3, [r7, #4] } 800467e: 4618 mov r0, r3 8004680: 3718 adds r7, #24 8004682: 46bd mov sp, r7 8004684: bd80 pop {r7, pc} 08004686 <_close>: int _close(int file) { 8004686: b480 push {r7} 8004688: b083 sub sp, #12 800468a: af00 add r7, sp, #0 800468c: 6078 str r0, [r7, #4] (void)file; return -1; 800468e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 8004692: 4618 mov r0, r3 8004694: 370c adds r7, #12 8004696: 46bd mov sp, r7 8004698: f85d 7b04 ldr.w r7, [sp], #4 800469c: 4770 bx lr 0800469e <_fstat>: int _fstat(int file, struct stat *st) { 800469e: b480 push {r7} 80046a0: b083 sub sp, #12 80046a2: af00 add r7, sp, #0 80046a4: 6078 str r0, [r7, #4] 80046a6: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 80046a8: 683b ldr r3, [r7, #0] 80046aa: f44f 5200 mov.w r2, #8192 @ 0x2000 80046ae: 605a str r2, [r3, #4] return 0; 80046b0: 2300 movs r3, #0 } 80046b2: 4618 mov r0, r3 80046b4: 370c adds r7, #12 80046b6: 46bd mov sp, r7 80046b8: f85d 7b04 ldr.w r7, [sp], #4 80046bc: 4770 bx lr 080046be <_isatty>: int _isatty(int file) { 80046be: b480 push {r7} 80046c0: b083 sub sp, #12 80046c2: af00 add r7, sp, #0 80046c4: 6078 str r0, [r7, #4] (void)file; return 1; 80046c6: 2301 movs r3, #1 } 80046c8: 4618 mov r0, r3 80046ca: 370c adds r7, #12 80046cc: 46bd mov sp, r7 80046ce: f85d 7b04 ldr.w r7, [sp], #4 80046d2: 4770 bx lr 080046d4 <_lseek>: int _lseek(int file, int ptr, int dir) { 80046d4: b480 push {r7} 80046d6: b085 sub sp, #20 80046d8: af00 add r7, sp, #0 80046da: 60f8 str r0, [r7, #12] 80046dc: 60b9 str r1, [r7, #8] 80046de: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 80046e0: 2300 movs r3, #0 } 80046e2: 4618 mov r0, r3 80046e4: 3714 adds r7, #20 80046e6: 46bd mov sp, r7 80046e8: f85d 7b04 ldr.w r7, [sp], #4 80046ec: 4770 bx lr ... 080046f0 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 80046f0: b580 push {r7, lr} 80046f2: b086 sub sp, #24 80046f4: af00 add r7, sp, #0 80046f6: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 80046f8: 4a14 ldr r2, [pc, #80] @ (800474c <_sbrk+0x5c>) 80046fa: 4b15 ldr r3, [pc, #84] @ (8004750 <_sbrk+0x60>) 80046fc: 1ad3 subs r3, r2, r3 80046fe: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8004700: 697b ldr r3, [r7, #20] 8004702: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 8004704: 4b13 ldr r3, [pc, #76] @ (8004754 <_sbrk+0x64>) 8004706: 681b ldr r3, [r3, #0] 8004708: 2b00 cmp r3, #0 800470a: d102 bne.n 8004712 <_sbrk+0x22> { __sbrk_heap_end = &_end; 800470c: 4b11 ldr r3, [pc, #68] @ (8004754 <_sbrk+0x64>) 800470e: 4a12 ldr r2, [pc, #72] @ (8004758 <_sbrk+0x68>) 8004710: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 8004712: 4b10 ldr r3, [pc, #64] @ (8004754 <_sbrk+0x64>) 8004714: 681a ldr r2, [r3, #0] 8004716: 687b ldr r3, [r7, #4] 8004718: 4413 add r3, r2 800471a: 693a ldr r2, [r7, #16] 800471c: 429a cmp r2, r3 800471e: d207 bcs.n 8004730 <_sbrk+0x40> { errno = ENOMEM; 8004720: f013 fb58 bl 8017dd4 <__errno> 8004724: 4603 mov r3, r0 8004726: 220c movs r2, #12 8004728: 601a str r2, [r3, #0] return (void *)-1; 800472a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800472e: e009 b.n 8004744 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 8004730: 4b08 ldr r3, [pc, #32] @ (8004754 <_sbrk+0x64>) 8004732: 681b ldr r3, [r3, #0] 8004734: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 8004736: 4b07 ldr r3, [pc, #28] @ (8004754 <_sbrk+0x64>) 8004738: 681a ldr r2, [r3, #0] 800473a: 687b ldr r3, [r7, #4] 800473c: 4413 add r3, r2 800473e: 4a05 ldr r2, [pc, #20] @ (8004754 <_sbrk+0x64>) 8004740: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 8004742: 68fb ldr r3, [r7, #12] } 8004744: 4618 mov r0, r3 8004746: 3718 adds r7, #24 8004748: 46bd mov sp, r7 800474a: bd80 pop {r7, pc} 800474c: 24060000 .word 0x24060000 8004750: 00000400 .word 0x00000400 8004754: 24000984 .word 0x24000984 8004758: 240131b8 .word 0x240131b8 0800475c : * configuration. * @param None * @retval None */ void SystemInit (void) { 800475c: b480 push {r7} 800475e: af00 add r7, sp, #0 __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8004760: 4b37 ldr r3, [pc, #220] @ (8004840 ) 8004762: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004766: 4a36 ldr r2, [pc, #216] @ (8004840 ) 8004768: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 800476c: f8c2 3088 str.w r3, [r2, #136] @ 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8004770: 4b34 ldr r3, [pc, #208] @ (8004844 ) 8004772: 681b ldr r3, [r3, #0] 8004774: f003 030f and.w r3, r3, #15 8004778: 2b06 cmp r3, #6 800477a: d807 bhi.n 800478c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 800477c: 4b31 ldr r3, [pc, #196] @ (8004844 ) 800477e: 681b ldr r3, [r3, #0] 8004780: f023 030f bic.w r3, r3, #15 8004784: 4a2f ldr r2, [pc, #188] @ (8004844 ) 8004786: f043 0307 orr.w r3, r3, #7 800478a: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 800478c: 4b2e ldr r3, [pc, #184] @ (8004848 ) 800478e: 681b ldr r3, [r3, #0] 8004790: 4a2d ldr r2, [pc, #180] @ (8004848 ) 8004792: f043 0301 orr.w r3, r3, #1 8004796: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 8004798: 4b2b ldr r3, [pc, #172] @ (8004848 ) 800479a: 2200 movs r2, #0 800479c: 611a str r2, [r3, #16] /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 800479e: 4b2a ldr r3, [pc, #168] @ (8004848 ) 80047a0: 681a ldr r2, [r3, #0] 80047a2: 4929 ldr r1, [pc, #164] @ (8004848 ) 80047a4: 4b29 ldr r3, [pc, #164] @ (800484c ) 80047a6: 4013 ands r3, r2 80047a8: 600b str r3, [r1, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 80047aa: 4b26 ldr r3, [pc, #152] @ (8004844 ) 80047ac: 681b ldr r3, [r3, #0] 80047ae: f003 0308 and.w r3, r3, #8 80047b2: 2b00 cmp r3, #0 80047b4: d007 beq.n 80047c6 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 80047b6: 4b23 ldr r3, [pc, #140] @ (8004844 ) 80047b8: 681b ldr r3, [r3, #0] 80047ba: f023 030f bic.w r3, r3, #15 80047be: 4a21 ldr r2, [pc, #132] @ (8004844 ) 80047c0: f043 0307 orr.w r3, r3, #7 80047c4: 6013 str r3, [r2, #0] } #if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; 80047c6: 4b20 ldr r3, [pc, #128] @ (8004848 ) 80047c8: 2200 movs r2, #0 80047ca: 619a str r2, [r3, #24] /* Reset D2CFGR register */ RCC->D2CFGR = 0x00000000; 80047cc: 4b1e ldr r3, [pc, #120] @ (8004848 ) 80047ce: 2200 movs r2, #0 80047d0: 61da str r2, [r3, #28] /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; 80047d2: 4b1d ldr r3, [pc, #116] @ (8004848 ) 80047d4: 2200 movs r2, #0 80047d6: 621a str r2, [r3, #32] /* Reset SRDCFGR register */ RCC->SRDCFGR = 0x00000000; #endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; 80047d8: 4b1b ldr r3, [pc, #108] @ (8004848 ) 80047da: 4a1d ldr r2, [pc, #116] @ (8004850 ) 80047dc: 629a str r2, [r3, #40] @ 0x28 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; 80047de: 4b1a ldr r3, [pc, #104] @ (8004848 ) 80047e0: 4a1c ldr r2, [pc, #112] @ (8004854 ) 80047e2: 62da str r2, [r3, #44] @ 0x2c /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 80047e4: 4b18 ldr r3, [pc, #96] @ (8004848 ) 80047e6: 4a1c ldr r2, [pc, #112] @ (8004858 ) 80047e8: 631a str r2, [r3, #48] @ 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 80047ea: 4b17 ldr r3, [pc, #92] @ (8004848 ) 80047ec: 2200 movs r2, #0 80047ee: 635a str r2, [r3, #52] @ 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 80047f0: 4b15 ldr r3, [pc, #84] @ (8004848 ) 80047f2: 4a19 ldr r2, [pc, #100] @ (8004858 ) 80047f4: 639a str r2, [r3, #56] @ 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 80047f6: 4b14 ldr r3, [pc, #80] @ (8004848 ) 80047f8: 2200 movs r2, #0 80047fa: 63da str r2, [r3, #60] @ 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 80047fc: 4b12 ldr r3, [pc, #72] @ (8004848 ) 80047fe: 4a16 ldr r2, [pc, #88] @ (8004858 ) 8004800: 641a str r2, [r3, #64] @ 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 8004802: 4b11 ldr r3, [pc, #68] @ (8004848 ) 8004804: 2200 movs r2, #0 8004806: 645a str r2, [r3, #68] @ 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8004808: 4b0f ldr r3, [pc, #60] @ (8004848 ) 800480a: 681b ldr r3, [r3, #0] 800480c: 4a0e ldr r2, [pc, #56] @ (8004848 ) 800480e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8004812: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 8004814: 4b0c ldr r3, [pc, #48] @ (8004848 ) 8004816: 2200 movs r2, #0 8004818: 661a str r2, [r3, #96] @ 0x60 #if (STM32H7_DEV_ID == 0x450UL) /* dual core CM7 or single core line */ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) 800481a: 4b10 ldr r3, [pc, #64] @ (800485c ) 800481c: 681a ldr r2, [r3, #0] 800481e: 4b10 ldr r3, [pc, #64] @ (8004860 ) 8004820: 4013 ands r3, r2 8004822: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004826: d202 bcs.n 800482e { /* if stm32h7 revY*/ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; 8004828: 4b0e ldr r3, [pc, #56] @ (8004864 ) 800482a: 2201 movs r2, #1 800482c: 601a str r2, [r3, #0] /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 800482e: 4b0e ldr r3, [pc, #56] @ (8004868 ) 8004830: f243 02d2 movw r2, #12498 @ 0x30d2 8004834: 601a str r2, [r3, #0] #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ } 8004836: bf00 nop 8004838: 46bd mov sp, r7 800483a: f85d 7b04 ldr.w r7, [sp], #4 800483e: 4770 bx lr 8004840: e000ed00 .word 0xe000ed00 8004844: 52002000 .word 0x52002000 8004848: 58024400 .word 0x58024400 800484c: eaf6ed7f .word 0xeaf6ed7f 8004850: 02020200 .word 0x02020200 8004854: 01ff0000 .word 0x01ff0000 8004858: 01010280 .word 0x01010280 800485c: 5c001000 .word 0x5c001000 8004860: ffff0000 .word 0xffff0000 8004864: 51008108 .word 0x51008108 8004868: 52004000 .word 0x52004000 0800486c <__NVIC_SystemReset>: { 800486c: b480 push {r7} 800486e: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 8004870: f3bf 8f4f dsb sy } 8004874: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 8004876: 4b06 ldr r3, [pc, #24] @ (8004890 <__NVIC_SystemReset+0x24>) 8004878: 68db ldr r3, [r3, #12] 800487a: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800487e: 4904 ldr r1, [pc, #16] @ (8004890 <__NVIC_SystemReset+0x24>) 8004880: 4b04 ldr r3, [pc, #16] @ (8004894 <__NVIC_SystemReset+0x28>) 8004882: 4313 orrs r3, r2 8004884: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 8004886: f3bf 8f4f dsb sy } 800488a: bf00 nop __NOP(); 800488c: bf00 nop 800488e: e7fd b.n 800488c <__NVIC_SystemReset+0x20> 8004890: e000ed00 .word 0xe000ed00 8004894: 05fa0004 .word 0x05fa0004 08004898 : uint8_t outputDataBuffer[OUTPUT_DATA_BUFF_SIZE]; uint16_t outputDataBufferPos = 0; extern RNG_HandleTypeDef hrng; void UartTasksInit (void) { 8004898: b580 push {r7, lr} 800489a: af00 add r7, sp, #0 uart1TaskData.uartRxBuffer = uart1RxBuffer; 800489c: 4b24 ldr r3, [pc, #144] @ (8004930 ) 800489e: 4a25 ldr r2, [pc, #148] @ (8004934 ) 80048a0: 601a str r2, [r3, #0] uart1TaskData.uartRxBufferLen = UART1_RX_BUFF_SIZE; 80048a2: 4b23 ldr r3, [pc, #140] @ (8004930 ) 80048a4: f44f 7280 mov.w r2, #256 @ 0x100 80048a8: 809a strh r2, [r3, #4] uart1TaskData.uartTxBuffer = uart1TxBuffer; 80048aa: 4b21 ldr r3, [pc, #132] @ (8004930 ) 80048ac: 4a22 ldr r2, [pc, #136] @ (8004938 ) 80048ae: 609a str r2, [r3, #8] uart1TaskData.uartRxBufferLen = UART1_TX_BUFF_SIZE; 80048b0: 4b1f ldr r3, [pc, #124] @ (8004930 ) 80048b2: f44f 7280 mov.w r2, #256 @ 0x100 80048b6: 809a strh r2, [r3, #4] uart1TaskData.frameData = uart1TaskFrameData; 80048b8: 4b1d ldr r3, [pc, #116] @ (8004930 ) 80048ba: 4a20 ldr r2, [pc, #128] @ (800493c ) 80048bc: 611a str r2, [r3, #16] uart1TaskData.frameDataLen = UART1_RX_BUFF_SIZE; 80048be: 4b1c ldr r3, [pc, #112] @ (8004930 ) 80048c0: f44f 7280 mov.w r2, #256 @ 0x100 80048c4: 829a strh r2, [r3, #20] uart1TaskData.huart = &huart1; 80048c6: 4b1a ldr r3, [pc, #104] @ (8004930 ) 80048c8: 4a1d ldr r2, [pc, #116] @ (8004940 ) 80048ca: 631a str r2, [r3, #48] @ 0x30 uart1TaskData.uartNumber = 1; 80048cc: 4b18 ldr r3, [pc, #96] @ (8004930 ) 80048ce: 2201 movs r2, #1 80048d0: f883 2034 strb.w r2, [r3, #52] @ 0x34 uart1TaskData.processDataCb = Uart1ReceivedDataProcessCallback; 80048d4: 4b16 ldr r3, [pc, #88] @ (8004930 ) 80048d6: 4a1b ldr r2, [pc, #108] @ (8004944 ) 80048d8: 629a str r2, [r3, #40] @ 0x28 uart1TaskData.processRxDataMsgBuffer = NULL; 80048da: 4b15 ldr r3, [pc, #84] @ (8004930 ) 80048dc: 2200 movs r2, #0 80048de: 625a str r2, [r3, #36] @ 0x24 uart8TaskData.uartRxBuffer = uart8RxBuffer; 80048e0: 4b19 ldr r3, [pc, #100] @ (8004948 ) 80048e2: 4a1a ldr r2, [pc, #104] @ (800494c ) 80048e4: 601a str r2, [r3, #0] uart8TaskData.uartRxBufferLen = UART8_RX_BUFF_SIZE; 80048e6: 4b18 ldr r3, [pc, #96] @ (8004948 ) 80048e8: f44f 7280 mov.w r2, #256 @ 0x100 80048ec: 809a strh r2, [r3, #4] uart8TaskData.uartTxBuffer = uart8TxBuffer; 80048ee: 4b16 ldr r3, [pc, #88] @ (8004948 ) 80048f0: 4a17 ldr r2, [pc, #92] @ (8004950 ) 80048f2: 609a str r2, [r3, #8] uart8TaskData.uartRxBufferLen = UART8_TX_BUFF_SIZE; 80048f4: 4b14 ldr r3, [pc, #80] @ (8004948 ) 80048f6: f44f 7280 mov.w r2, #256 @ 0x100 80048fa: 809a strh r2, [r3, #4] uart8TaskData.frameData = uart8TaskFrameData; 80048fc: 4b12 ldr r3, [pc, #72] @ (8004948 ) 80048fe: 4a15 ldr r2, [pc, #84] @ (8004954 ) 8004900: 611a str r2, [r3, #16] uart8TaskData.frameDataLen = UART8_RX_BUFF_SIZE; 8004902: 4b11 ldr r3, [pc, #68] @ (8004948 ) 8004904: f44f 7280 mov.w r2, #256 @ 0x100 8004908: 829a strh r2, [r3, #20] uart8TaskData.huart = &huart8; 800490a: 4b0f ldr r3, [pc, #60] @ (8004948 ) 800490c: 4a12 ldr r2, [pc, #72] @ (8004958 ) 800490e: 631a str r2, [r3, #48] @ 0x30 uart8TaskData.uartNumber = 8; 8004910: 4b0d ldr r3, [pc, #52] @ (8004948 ) 8004912: 2208 movs r2, #8 8004914: f883 2034 strb.w r2, [r3, #52] @ 0x34 uart8TaskData.processDataCb = Uart8ReceivedDataProcessCallback; 8004918: 4b0b ldr r3, [pc, #44] @ (8004948 ) 800491a: 4a10 ldr r2, [pc, #64] @ (800495c ) 800491c: 629a str r2, [r3, #40] @ 0x28 uart8TaskData.processRxDataMsgBuffer = NULL; 800491e: 4b0a ldr r3, [pc, #40] @ (8004948 ) 8004920: 2200 movs r2, #0 8004922: 625a str r2, [r3, #36] @ 0x24 #ifdef USE_UART8_INSTEAD_UART1 UartTaskCreate (&uart8TaskData); 8004924: 4808 ldr r0, [pc, #32] @ (8004948 ) 8004926: f000 f81b bl 8004960 #else UartTaskCreate (&uart1TaskData); #endif } 800492a: bf00 nop 800492c: bd80 pop {r7, pc} 800492e: bf00 nop 8004930: 24000f88 .word 0x24000f88 8004934: 24000988 .word 0x24000988 8004938: 24000a88 .word 0x24000a88 800493c: 24000b88 .word 0x24000b88 8004940: 240005c4 .word 0x240005c4 8004944: 08005009 .word 0x08005009 8004948: 24000fc0 .word 0x24000fc0 800494c: 24000c88 .word 0x24000c88 8004950: 24000d88 .word 0x24000d88 8004954: 24000e88 .word 0x24000e88 8004958: 24000530 .word 0x24000530 800495c: 08004fed .word 0x08004fed 08004960 : void UartTaskCreate (UartTaskData* uartTaskData) { 8004960: b580 push {r7, lr} 8004962: b08c sub sp, #48 @ 0x30 8004964: af00 add r7, sp, #0 8004966: 6078 str r0, [r7, #4] osThreadAttr_t osThreadAttrRxUart = { 0 }; 8004968: f107 030c add.w r3, r7, #12 800496c: 2224 movs r2, #36 @ 0x24 800496e: 2100 movs r1, #0 8004970: 4618 mov r0, r3 8004972: f013 f98b bl 8017c8c osThreadAttrRxUart.stack_size = configMINIMAL_STACK_SIZE * 2; 8004976: f44f 6380 mov.w r3, #1024 @ 0x400 800497a: 623b str r3, [r7, #32] osThreadAttrRxUart.priority = (osPriority_t)osPriorityHigh; 800497c: 2328 movs r3, #40 @ 0x28 800497e: 627b str r3, [r7, #36] @ 0x24 uartTaskData->uartRecieveTaskHandle = osThreadNew (UartRxTask, uartTaskData, &osThreadAttrRxUart); 8004980: f107 030c add.w r3, r7, #12 8004984: 461a mov r2, r3 8004986: 6879 ldr r1, [r7, #4] 8004988: 4804 ldr r0, [pc, #16] @ (800499c ) 800498a: f00e fe23 bl 80135d4 800498e: 4602 mov r2, r0 8004990: 687b ldr r3, [r7, #4] 8004992: 619a str r2, [r3, #24] } 8004994: bf00 nop 8004996: 3730 adds r7, #48 @ 0x30 8004998: 46bd mov sp, r7 800499a: bd80 pop {r7, pc} 800499c: 08004ab5 .word 0x08004ab5 080049a0 : void HAL_UART_RxCpltCallback (UART_HandleTypeDef* huart) { 80049a0: b480 push {r7} 80049a2: b083 sub sp, #12 80049a4: af00 add r7, sp, #0 80049a6: 6078 str r0, [r7, #4] } 80049a8: bf00 nop 80049aa: 370c adds r7, #12 80049ac: 46bd mov sp, r7 80049ae: f85d 7b04 ldr.w r7, [sp], #4 80049b2: 4770 bx lr 080049b4 : void HAL_UARTEx_RxEventCallback (UART_HandleTypeDef* huart, uint16_t Size) { 80049b4: b580 push {r7, lr} 80049b6: b082 sub sp, #8 80049b8: af00 add r7, sp, #0 80049ba: 6078 str r0, [r7, #4] 80049bc: 460b mov r3, r1 80049be: 807b strh r3, [r7, #2] if (huart->Instance == USART1) { 80049c0: 687b ldr r3, [r7, #4] 80049c2: 681b ldr r3, [r3, #0] 80049c4: 4a0c ldr r2, [pc, #48] @ (80049f8 ) 80049c6: 4293 cmp r3, r2 80049c8: d106 bne.n 80049d8 HandleUartRxCallback (&uart1TaskData, huart, Size); 80049ca: 887b ldrh r3, [r7, #2] 80049cc: 461a mov r2, r3 80049ce: 6879 ldr r1, [r7, #4] 80049d0: 480a ldr r0, [pc, #40] @ (80049fc ) 80049d2: f000 f823 bl 8004a1c } else if (huart->Instance == UART8) { HandleUartRxCallback (&uart8TaskData, huart, Size); } } 80049d6: e00a b.n 80049ee } else if (huart->Instance == UART8) { 80049d8: 687b ldr r3, [r7, #4] 80049da: 681b ldr r3, [r3, #0] 80049dc: 4a08 ldr r2, [pc, #32] @ (8004a00 ) 80049de: 4293 cmp r3, r2 80049e0: d105 bne.n 80049ee HandleUartRxCallback (&uart8TaskData, huart, Size); 80049e2: 887b ldrh r3, [r7, #2] 80049e4: 461a mov r2, r3 80049e6: 6879 ldr r1, [r7, #4] 80049e8: 4806 ldr r0, [pc, #24] @ (8004a04 ) 80049ea: f000 f817 bl 8004a1c } 80049ee: bf00 nop 80049f0: 3708 adds r7, #8 80049f2: 46bd mov sp, r7 80049f4: bd80 pop {r7, pc} 80049f6: bf00 nop 80049f8: 40011000 .word 0x40011000 80049fc: 24000f88 .word 0x24000f88 8004a00: 40007c00 .word 0x40007c00 8004a04: 24000fc0 .word 0x24000fc0 08004a08 : void HAL_UART_TxCpltCallback (UART_HandleTypeDef* huart) { 8004a08: b480 push {r7} 8004a0a: b083 sub sp, #12 8004a0c: af00 add r7, sp, #0 8004a0e: 6078 str r0, [r7, #4] if (huart->Instance == UART8) { } } 8004a10: bf00 nop 8004a12: 370c adds r7, #12 8004a14: 46bd mov sp, r7 8004a16: f85d 7b04 ldr.w r7, [sp], #4 8004a1a: 4770 bx lr 08004a1c : void HandleUartRxCallback (UartTaskData* uartTaskData, UART_HandleTypeDef* huart, uint16_t Size) { 8004a1c: b580 push {r7, lr} 8004a1e: b088 sub sp, #32 8004a20: af02 add r7, sp, #8 8004a22: 60f8 str r0, [r7, #12] 8004a24: 60b9 str r1, [r7, #8] 8004a26: 4613 mov r3, r2 8004a28: 80fb strh r3, [r7, #6] BaseType_t pxHigherPriorityTaskWoken = pdFALSE; 8004a2a: 2300 movs r3, #0 8004a2c: 617b str r3, [r7, #20] osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004a2e: 68fb ldr r3, [r7, #12] 8004a30: 6a1b ldr r3, [r3, #32] 8004a32: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004a36: 4618 mov r0, r3 8004a38: f00e fff7 bl 8013a2a memcpy (&(uartTaskData->frameData[uartTaskData->frameBytesCount]), uartTaskData->uartRxBuffer, Size); 8004a3c: 68fb ldr r3, [r7, #12] 8004a3e: 691b ldr r3, [r3, #16] 8004a40: 68fa ldr r2, [r7, #12] 8004a42: 8ad2 ldrh r2, [r2, #22] 8004a44: 1898 adds r0, r3, r2 8004a46: 68fb ldr r3, [r7, #12] 8004a48: 681b ldr r3, [r3, #0] 8004a4a: 88fa ldrh r2, [r7, #6] 8004a4c: 4619 mov r1, r3 8004a4e: f013 f9ee bl 8017e2e uartTaskData->frameBytesCount += Size; 8004a52: 68fb ldr r3, [r7, #12] 8004a54: 8ada ldrh r2, [r3, #22] 8004a56: 88fb ldrh r3, [r7, #6] 8004a58: 4413 add r3, r2 8004a5a: b29a uxth r2, r3 8004a5c: 68fb ldr r3, [r7, #12] 8004a5e: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 8004a60: 68fb ldr r3, [r7, #12] 8004a62: 6a1b ldr r3, [r3, #32] 8004a64: 4618 mov r0, r3 8004a66: f00f f82b bl 8013ac0 xTaskNotifyFromISR (uartTaskData->uartRecieveTaskHandle, Size, eSetValueWithOverwrite, &pxHigherPriorityTaskWoken); 8004a6a: 68fb ldr r3, [r7, #12] 8004a6c: 6998 ldr r0, [r3, #24] 8004a6e: 88f9 ldrh r1, [r7, #6] 8004a70: f107 0314 add.w r3, r7, #20 8004a74: 9300 str r3, [sp, #0] 8004a76: 2300 movs r3, #0 8004a78: 2203 movs r2, #3 8004a7a: f011 fd1b bl 80164b4 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8004a7e: 68fb ldr r3, [r7, #12] 8004a80: 6b18 ldr r0, [r3, #48] @ 0x30 8004a82: 68fb ldr r3, [r7, #12] 8004a84: 6819 ldr r1, [r3, #0] 8004a86: 68fb ldr r3, [r7, #12] 8004a88: 889b ldrh r3, [r3, #4] 8004a8a: 461a mov r2, r3 8004a8c: f00e fc75 bl 801337a portEND_SWITCHING_ISR (pxHigherPriorityTaskWoken); 8004a90: 697b ldr r3, [r7, #20] 8004a92: 2b00 cmp r3, #0 8004a94: d007 beq.n 8004aa6 8004a96: 4b06 ldr r3, [pc, #24] @ (8004ab0 ) 8004a98: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8004a9c: 601a str r2, [r3, #0] 8004a9e: f3bf 8f4f dsb sy 8004aa2: f3bf 8f6f isb sy } 8004aa6: bf00 nop 8004aa8: 3718 adds r7, #24 8004aaa: 46bd mov sp, r7 8004aac: bd80 pop {r7, pc} 8004aae: bf00 nop 8004ab0: e000ed04 .word 0xe000ed04 08004ab4 : void UartRxTask (void* argument) { 8004ab4: b580 push {r7, lr} 8004ab6: b0d2 sub sp, #328 @ 0x148 8004ab8: af02 add r7, sp, #8 8004aba: f507 73a0 add.w r3, r7, #320 @ 0x140 8004abe: f5a3 739e sub.w r3, r3, #316 @ 0x13c 8004ac2: 6018 str r0, [r3, #0] UartTaskData* uartTaskData = (UartTaskData*)argument; 8004ac4: f507 73a0 add.w r3, r7, #320 @ 0x140 8004ac8: f5a3 739e sub.w r3, r3, #316 @ 0x13c 8004acc: 681b ldr r3, [r3, #0] 8004ace: f8c7 312c str.w r3, [r7, #300] @ 0x12c SerialProtocolFrameData spFrameData = { 0 }; 8004ad2: f507 73a0 add.w r3, r7, #320 @ 0x140 8004ad6: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004ada: 4618 mov r0, r3 8004adc: f44f 7386 mov.w r3, #268 @ 0x10c 8004ae0: 461a mov r2, r3 8004ae2: 2100 movs r1, #0 8004ae4: f013 f8d2 bl 8017c8c uint32_t bytesRec = 0; 8004ae8: f507 73a0 add.w r3, r7, #320 @ 0x140 8004aec: f5a3 739a sub.w r3, r3, #308 @ 0x134 8004af0: 2200 movs r2, #0 8004af2: 601a str r2, [r3, #0] uint32_t crc = 0; 8004af4: 2300 movs r3, #0 8004af6: f8c7 3128 str.w r3, [r7, #296] @ 0x128 uint16_t frameCommandRaw = 0x0000; 8004afa: 2300 movs r3, #0 8004afc: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 uint16_t frameBytesCount = 0; 8004b00: 2300 movs r3, #0 8004b02: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 uint16_t frameCrc = 0; 8004b06: 2300 movs r3, #0 8004b08: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 uint16_t frameTotalLength = 0; 8004b0c: 2300 movs r3, #0 8004b0e: f8a7 313e strh.w r3, [r7, #318] @ 0x13e uint16_t dataToSend = 0; 8004b12: 2300 movs r3, #0 8004b14: f8a7 313c strh.w r3, [r7, #316] @ 0x13c portBASE_TYPE crcPass = pdFAIL; 8004b18: 2300 movs r3, #0 8004b1a: f8c7 3138 str.w r3, [r7, #312] @ 0x138 portBASE_TYPE proceed = pdFALSE; 8004b1e: 2300 movs r3, #0 8004b20: f8c7 3134 str.w r3, [r7, #308] @ 0x134 portBASE_TYPE frameTimeout = pdFAIL; 8004b24: 2300 movs r3, #0 8004b26: f8c7 311c str.w r3, [r7, #284] @ 0x11c enum SerialReceiverStates receverState = srWaitForHeader; 8004b2a: 2300 movs r3, #0 8004b2c: f887 3133 strb.w r3, [r7, #307] @ 0x133 uartTaskData->rxDataBufferMutex = osMutexNew (NULL); 8004b30: 2000 movs r0, #0 8004b32: f00e fef4 bl 801391e 8004b36: 4602 mov r2, r0 8004b38: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004b3c: 621a str r2, [r3, #32] HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8004b3e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004b42: 6b18 ldr r0, [r3, #48] @ 0x30 8004b44: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004b48: 6819 ldr r1, [r3, #0] 8004b4a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004b4e: 889b ldrh r3, [r3, #4] 8004b50: 461a mov r2, r3 8004b52: f00e fc12 bl 801337a while (pdTRUE) { frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8004b56: f107 020c add.w r2, r7, #12 8004b5a: f44f 63fa mov.w r3, #2000 @ 0x7d0 8004b5e: 2100 movs r1, #0 8004b60: 2000 movs r0, #0 8004b62: f011 fb85 bl 8016270 8004b66: 4603 mov r3, r0 8004b68: 2b00 cmp r3, #0 8004b6a: bf0c ite eq 8004b6c: 2301 moveq r3, #1 8004b6e: 2300 movne r3, #0 8004b70: b2db uxtb r3, r3 8004b72: f8c7 311c str.w r3, [r7, #284] @ 0x11c osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004b76: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004b7a: 6a1b ldr r3, [r3, #32] 8004b7c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004b80: 4618 mov r0, r3 8004b82: f00e ff52 bl 8013a2a frameBytesCount = uartTaskData->frameBytesCount; 8004b86: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004b8a: 8adb ldrh r3, [r3, #22] 8004b8c: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 osMutexRelease (uartTaskData->rxDataBufferMutex); 8004b90: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004b94: 6a1b ldr r3, [r3, #32] 8004b96: 4618 mov r0, r3 8004b98: f00e ff92 bl 8013ac0 if ((frameTimeout == pdTRUE) && (frameBytesCount > 0)) { 8004b9c: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8004ba0: 2b01 cmp r3, #1 8004ba2: d10a bne.n 8004bba 8004ba4: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004ba8: 2b00 cmp r3, #0 8004baa: d006 beq.n 8004bba receverState = srFail; 8004bac: 2304 movs r3, #4 8004bae: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdTRUE; 8004bb2: 2301 movs r3, #1 8004bb4: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004bb8: e01b b.n 8004bf2 } else { if (frameTimeout == pdFALSE) { 8004bba: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8004bbe: 2b00 cmp r3, #0 8004bc0: d103 bne.n 8004bca proceed = pdTRUE; 8004bc2: 2301 movs r3, #1 8004bc4: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004bc8: e206 b.n 8004fd8 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: RX bytes received: %ld\n", uartTaskData->uartNumber, bytesRec); #endif } else { if (uartTaskData->huart->RxState == HAL_UART_STATE_READY) { 8004bca: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004bce: 6b1b ldr r3, [r3, #48] @ 0x30 8004bd0: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004bd4: 2b20 cmp r3, #32 8004bd6: f040 81ff bne.w 8004fd8 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8004bda: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004bde: 6b18 ldr r0, [r3, #48] @ 0x30 8004be0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004be4: 6819 ldr r1, [r3, #0] 8004be6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004bea: 889b ldrh r3, [r3, #4] 8004bec: 461a mov r2, r3 8004bee: f00e fbc4 bl 801337a } } } while (proceed) { 8004bf2: e1f1 b.n 8004fd8 switch (receverState) { 8004bf4: f897 3133 ldrb.w r3, [r7, #307] @ 0x133 8004bf8: 2b04 cmp r3, #4 8004bfa: f200 81c8 bhi.w 8004f8e 8004bfe: a201 add r2, pc, #4 @ (adr r2, 8004c04 ) 8004c00: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004c04: 08004c19 .word 0x08004c19 8004c08: 08004d7b .word 0x08004d7b 8004c0c: 08004d5f .word 0x08004d5f 8004c10: 08004e0b .word 0x08004e0b 8004c14: 08004eb7 .word 0x08004eb7 case srWaitForHeader: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004c18: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c1c: 6a1b ldr r3, [r3, #32] 8004c1e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004c22: 4618 mov r0, r3 8004c24: f00e ff01 bl 8013a2a if (uartTaskData->frameData[0] == FRAME_INDICATOR) { 8004c28: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c2c: 691b ldr r3, [r3, #16] 8004c2e: 781b ldrb r3, [r3, #0] 8004c30: 2baa cmp r3, #170 @ 0xaa 8004c32: f040 8082 bne.w 8004d3a if (frameBytesCount > FRAME_ID_LENGTH) { 8004c36: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004c3a: 2b02 cmp r3, #2 8004c3c: d914 bls.n 8004c68 spFrameData.frameHeader.frameId = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_ID_LENGTH - FRAME_COMMAND_LENGTH])); 8004c3e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c42: 691b ldr r3, [r3, #16] 8004c44: 3302 adds r3, #2 8004c46: 781b ldrb r3, [r3, #0] 8004c48: 021b lsls r3, r3, #8 8004c4a: b21a sxth r2, r3 8004c4c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c50: 691b ldr r3, [r3, #16] 8004c52: 3301 adds r3, #1 8004c54: 781b ldrb r3, [r3, #0] 8004c56: b21b sxth r3, r3 8004c58: 4313 orrs r3, r2 8004c5a: b21b sxth r3, r3 8004c5c: b29a uxth r2, r3 spFrameData.frameHeader.frameId = 8004c5e: f507 73a0 add.w r3, r7, #320 @ 0x140 8004c62: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004c66: 801a strh r2, [r3, #0] } if (frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH) { 8004c68: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004c6c: 2b04 cmp r3, #4 8004c6e: d923 bls.n 8004cb8 frameCommandRaw = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_COMMAND_LENGTH])); 8004c70: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c74: 691b ldr r3, [r3, #16] 8004c76: 3304 adds r3, #4 8004c78: 781b ldrb r3, [r3, #0] 8004c7a: 021b lsls r3, r3, #8 8004c7c: b21a sxth r2, r3 8004c7e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c82: 691b ldr r3, [r3, #16] 8004c84: 3303 adds r3, #3 8004c86: 781b ldrb r3, [r3, #0] 8004c88: b21b sxth r3, r3 8004c8a: 4313 orrs r3, r2 8004c8c: b21b sxth r3, r3 8004c8e: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 spFrameData.frameHeader.frameCommand = (SerialProtocolCommands)(frameCommandRaw & 0x7FFF); 8004c92: f8b7 3126 ldrh.w r3, [r7, #294] @ 0x126 8004c96: b2da uxtb r2, r3 8004c98: f507 73a0 add.w r3, r7, #320 @ 0x140 8004c9c: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004ca0: 709a strb r2, [r3, #2] spFrameData.frameHeader.isResponseFrame = (frameCommandRaw & 0x8000) != 0 ? pdTRUE : pdFALSE; 8004ca2: f9b7 3126 ldrsh.w r3, [r7, #294] @ 0x126 8004ca6: 13db asrs r3, r3, #15 8004ca8: b21b sxth r3, r3 8004caa: f003 0201 and.w r2, r3, #1 8004cae: f507 73a0 add.w r3, r7, #320 @ 0x140 8004cb2: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004cb6: 609a str r2, [r3, #8] } if ((frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH) && ((spFrameData.frameHeader.frameCommand & 0x8000) != 0)) { 8004cb8: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004cbc: 2b05 cmp r3, #5 8004cbe: d913 bls.n 8004ce8 8004cc0: f507 73a0 add.w r3, r7, #320 @ 0x140 8004cc4: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004cc8: 789b ldrb r3, [r3, #2] 8004cca: f403 4300 and.w r3, r3, #32768 @ 0x8000 8004cce: 2b00 cmp r3, #0 8004cd0: d00a beq.n 8004ce8 spFrameData.frameHeader.respStatus = (SerialProtocolRespStatus)(uartTaskData->frameData[FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH]); 8004cd2: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004cd6: 691b ldr r3, [r3, #16] 8004cd8: 3305 adds r3, #5 8004cda: 781b ldrb r3, [r3, #0] 8004cdc: b25a sxtb r2, r3 8004cde: f507 73a0 add.w r3, r7, #320 @ 0x140 8004ce2: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004ce6: 70da strb r2, [r3, #3] } if (frameBytesCount >= FRAME_HEADER_LENGTH) { 8004ce8: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004cec: 2b07 cmp r3, #7 8004cee: d920 bls.n 8004d32 spFrameData.frameHeader.frameDataLength = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH])); 8004cf0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004cf4: 691b ldr r3, [r3, #16] 8004cf6: 3306 adds r3, #6 8004cf8: 781b ldrb r3, [r3, #0] 8004cfa: 021b lsls r3, r3, #8 8004cfc: b21a sxth r2, r3 8004cfe: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d02: 691b ldr r3, [r3, #16] 8004d04: 3305 adds r3, #5 8004d06: 781b ldrb r3, [r3, #0] 8004d08: b21b sxth r3, r3 8004d0a: 4313 orrs r3, r2 8004d0c: b21b sxth r3, r3 8004d0e: b29a uxth r2, r3 8004d10: f507 73a0 add.w r3, r7, #320 @ 0x140 8004d14: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004d18: 809a strh r2, [r3, #4] frameTotalLength = FRAME_HEADER_LENGTH + spFrameData.frameHeader.frameDataLength + FRAME_CRC_LENGTH; 8004d1a: f507 73a0 add.w r3, r7, #320 @ 0x140 8004d1e: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004d22: 889b ldrh r3, [r3, #4] 8004d24: 330a adds r3, #10 8004d26: f8a7 313e strh.w r3, [r7, #318] @ 0x13e receverState = srRecieveData; 8004d2a: 2302 movs r3, #2 8004d2c: f887 3133 strb.w r3, [r7, #307] @ 0x133 8004d30: e00e b.n 8004d50 } else { proceed = pdFALSE; 8004d32: 2300 movs r3, #0 8004d34: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004d38: e00a b.n 8004d50 } } else { if (frameBytesCount > 0) { 8004d3a: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004d3e: 2b00 cmp r3, #0 8004d40: d003 beq.n 8004d4a receverState = srFail; 8004d42: 2304 movs r3, #4 8004d44: f887 3133 strb.w r3, [r7, #307] @ 0x133 8004d48: e002 b.n 8004d50 } else { proceed = pdFALSE; 8004d4a: 2300 movs r3, #0 8004d4c: f8c7 3134 str.w r3, [r7, #308] @ 0x134 } } osMutexRelease (uartTaskData->rxDataBufferMutex); 8004d50: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d54: 6a1b ldr r3, [r3, #32] 8004d56: 4618 mov r0, r3 8004d58: f00e feb2 bl 8013ac0 break; 8004d5c: e13c b.n 8004fd8 case srRecieveData: if (frameBytesCount >= frameTotalLength) { 8004d5e: f8b7 2124 ldrh.w r2, [r7, #292] @ 0x124 8004d62: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004d66: 429a cmp r2, r3 8004d68: d303 bcc.n 8004d72 receverState = srCheckCrc; 8004d6a: 2301 movs r3, #1 8004d6c: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { proceed = pdFALSE; } break; 8004d70: e132 b.n 8004fd8 proceed = pdFALSE; 8004d72: 2300 movs r3, #0 8004d74: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 8004d78: e12e b.n 8004fd8 case srCheckCrc: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004d7a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d7e: 6a1b ldr r3, [r3, #32] 8004d80: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004d84: 4618 mov r0, r3 8004d86: f00e fe50 bl 8013a2a frameCrc = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[frameTotalLength - FRAME_CRC_LENGTH])); 8004d8a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d8e: 691a ldr r2, [r3, #16] 8004d90: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004d94: 3b01 subs r3, #1 8004d96: 4413 add r3, r2 8004d98: 781b ldrb r3, [r3, #0] 8004d9a: 021b lsls r3, r3, #8 8004d9c: b21a sxth r2, r3 8004d9e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004da2: 6919 ldr r1, [r3, #16] 8004da4: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004da8: 3b02 subs r3, #2 8004daa: 440b add r3, r1 8004dac: 781b ldrb r3, [r3, #0] 8004dae: b21b sxth r3, r3 8004db0: 4313 orrs r3, r2 8004db2: b21b sxth r3, r3 8004db4: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)(uartTaskData->frameData), frameTotalLength - FRAME_CRC_LENGTH); 8004db8: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004dbc: 6919 ldr r1, [r3, #16] 8004dbe: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004dc2: 3b02 subs r3, #2 8004dc4: 461a mov r2, r3 8004dc6: 4887 ldr r0, [pc, #540] @ (8004fe4 ) 8004dc8: f002 fe9c bl 8007b04 8004dcc: f8c7 0128 str.w r0, [r7, #296] @ 0x128 osMutexRelease (uartTaskData->rxDataBufferMutex); 8004dd0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004dd4: 6a1b ldr r3, [r3, #32] 8004dd6: 4618 mov r0, r3 8004dd8: f00e fe72 bl 8013ac0 crcPass = frameCrc == crc; 8004ddc: f8b7 3122 ldrh.w r3, [r7, #290] @ 0x122 8004de0: f8d7 2128 ldr.w r2, [r7, #296] @ 0x128 8004de4: 429a cmp r2, r3 8004de6: bf0c ite eq 8004de8: 2301 moveq r3, #1 8004dea: 2300 movne r3, #0 8004dec: b2db uxtb r3, r3 8004dee: f8c7 3138 str.w r3, [r7, #312] @ 0x138 if (crcPass) { 8004df2: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 8004df6: 2b00 cmp r3, #0 8004df8: d003 beq.n 8004e02 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: Frame CRC PASS\n", uartTaskData->uartNumber); #endif receverState = srExecuteCmd; 8004dfa: 2303 movs r3, #3 8004dfc: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { receverState = srFail; } break; 8004e00: e0ea b.n 8004fd8 receverState = srFail; 8004e02: 2304 movs r3, #4 8004e04: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004e08: e0e6 b.n 8004fd8 case srExecuteCmd: if ((uartTaskData->processDataCb != NULL) || (uartTaskData->processRxDataMsgBuffer != NULL)) { 8004e0a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e0e: 6a9b ldr r3, [r3, #40] @ 0x28 8004e10: 2b00 cmp r3, #0 8004e12: d104 bne.n 8004e1e 8004e14: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e18: 6a5b ldr r3, [r3, #36] @ 0x24 8004e1a: 2b00 cmp r3, #0 8004e1c: d01e beq.n 8004e5c osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004e1e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e22: 6a1b ldr r3, [r3, #32] 8004e24: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004e28: 4618 mov r0, r3 8004e2a: f00e fdfe bl 8013a2a memcpy (spFrameData.dataBuffer, &(uartTaskData->frameData[FRAME_HEADER_LENGTH]), spFrameData.frameHeader.frameDataLength); 8004e2e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e32: 691b ldr r3, [r3, #16] 8004e34: f103 0108 add.w r1, r3, #8 8004e38: f507 73a0 add.w r3, r7, #320 @ 0x140 8004e3c: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004e40: 889b ldrh r3, [r3, #4] 8004e42: 461a mov r2, r3 8004e44: f107 0310 add.w r3, r7, #16 8004e48: 330c adds r3, #12 8004e4a: 4618 mov r0, r3 8004e4c: f012 ffef bl 8017e2e osMutexRelease (uartTaskData->rxDataBufferMutex); 8004e50: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e54: 6a1b ldr r3, [r3, #32] 8004e56: 4618 mov r0, r3 8004e58: f00e fe32 bl 8013ac0 } if (uartTaskData->processRxDataMsgBuffer != NULL) { 8004e5c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e60: 6a5b ldr r3, [r3, #36] @ 0x24 8004e62: 2b00 cmp r3, #0 8004e64: d015 beq.n 8004e92 if (xMessageBufferSend (uartTaskData->processRxDataMsgBuffer, &spFrameData, sizeof (SerialProtocolFrameHeader) + spFrameData.frameHeader.frameDataLength, pdMS_TO_TICKS (200)) == pdFALSE) { 8004e66: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e6a: 6a58 ldr r0, [r3, #36] @ 0x24 8004e6c: f507 73a0 add.w r3, r7, #320 @ 0x140 8004e70: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004e74: 889b ldrh r3, [r3, #4] 8004e76: f103 020c add.w r2, r3, #12 8004e7a: f107 0110 add.w r1, r7, #16 8004e7e: 23c8 movs r3, #200 @ 0xc8 8004e80: f010 f840 bl 8014f04 8004e84: 4603 mov r3, r0 8004e86: 2b00 cmp r3, #0 8004e88: d103 bne.n 8004e92 receverState = srFail; 8004e8a: 2304 movs r3, #4 8004e8c: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004e90: e0a2 b.n 8004fd8 } } if (uartTaskData->processDataCb != NULL) { 8004e92: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e96: 6a9b ldr r3, [r3, #40] @ 0x28 8004e98: 2b00 cmp r3, #0 8004e9a: d008 beq.n 8004eae uartTaskData->processDataCb (uartTaskData, &spFrameData); 8004e9c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004ea0: 6a9b ldr r3, [r3, #40] @ 0x28 8004ea2: f107 0210 add.w r2, r7, #16 8004ea6: 4611 mov r1, r2 8004ea8: f8d7 012c ldr.w r0, [r7, #300] @ 0x12c 8004eac: 4798 blx r3 } receverState = srFinish; 8004eae: 2305 movs r3, #5 8004eb0: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004eb4: e090 b.n 8004fd8 case srFail: dataToSend = 0; 8004eb6: 2300 movs r3, #0 8004eb8: f8a7 313c strh.w r3, [r7, #316] @ 0x13c if ((frameTimeout == pdTRUE) && (frameBytesCount > 2)) { 8004ebc: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8004ec0: 2b01 cmp r3, #1 8004ec2: d11c bne.n 8004efe 8004ec4: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004ec8: 2b02 cmp r3, #2 8004eca: d918 bls.n 8004efe dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0); 8004ecc: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004ed0: 6898 ldr r0, [r3, #8] 8004ed2: f507 73a0 add.w r3, r7, #320 @ 0x140 8004ed6: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004eda: 8819 ldrh r1, [r3, #0] 8004edc: f507 73a0 add.w r3, r7, #320 @ 0x140 8004ee0: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004ee4: 789a ldrb r2, [r3, #2] 8004ee6: 2300 movs r3, #0 8004ee8: 9301 str r3, [sp, #4] 8004eea: 2300 movs r3, #0 8004eec: 9300 str r3, [sp, #0] 8004eee: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8004ef2: f7fe fd59 bl 80039a8 8004ef6: 4603 mov r3, r0 8004ef8: f8a7 313c strh.w r3, [r7, #316] @ 0x13c 8004efc: e034 b.n 8004f68 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: RX data receiver timeout!\n", uartTaskData->uartNumber); #endif } else if (!crcPass) { 8004efe: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 8004f02: 2b00 cmp r3, #0 8004f04: d118 bne.n 8004f38 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spCrcFail, NULL, 0); 8004f06: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f0a: 6898 ldr r0, [r3, #8] 8004f0c: f507 73a0 add.w r3, r7, #320 @ 0x140 8004f10: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004f14: 8819 ldrh r1, [r3, #0] 8004f16: f507 73a0 add.w r3, r7, #320 @ 0x140 8004f1a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004f1e: 789a ldrb r2, [r3, #2] 8004f20: 2300 movs r3, #0 8004f22: 9301 str r3, [sp, #4] 8004f24: 2300 movs r3, #0 8004f26: 9300 str r3, [sp, #0] 8004f28: f06f 0301 mvn.w r3, #1 8004f2c: f7fe fd3c bl 80039a8 8004f30: 4603 mov r3, r0 8004f32: f8a7 313c strh.w r3, [r7, #316] @ 0x13c 8004f36: e017 b.n 8004f68 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: Frame CRC FAIL\n", uartTaskData->uartNumber); #endif } else { dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spInternalError, NULL, 0); 8004f38: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f3c: 6898 ldr r0, [r3, #8] 8004f3e: f507 73a0 add.w r3, r7, #320 @ 0x140 8004f42: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004f46: 8819 ldrh r1, [r3, #0] 8004f48: f507 73a0 add.w r3, r7, #320 @ 0x140 8004f4c: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004f50: 789a ldrb r2, [r3, #2] 8004f52: 2300 movs r3, #0 8004f54: 9301 str r3, [sp, #4] 8004f56: 2300 movs r3, #0 8004f58: 9300 str r3, [sp, #0] 8004f5a: f06f 0303 mvn.w r3, #3 8004f5e: f7fe fd23 bl 80039a8 8004f62: 4603 mov r3, r0 8004f64: f8a7 313c strh.w r3, [r7, #316] @ 0x13c } if (dataToSend > 0) { 8004f68: f8b7 313c ldrh.w r3, [r7, #316] @ 0x13c 8004f6c: 2b00 cmp r3, #0 8004f6e: d00a beq.n 8004f86 HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 8004f70: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f74: 6b18 ldr r0, [r3, #48] @ 0x30 8004f76: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f7a: 689b ldr r3, [r3, #8] 8004f7c: f8b7 213c ldrh.w r2, [r7, #316] @ 0x13c 8004f80: 4619 mov r1, r3 8004f82: f00b fd25 bl 80109d0 } #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: TX bytes sent: %d\n", dataToSend, uartTaskData->uartNumber); #endif receverState = srFinish; 8004f86: 2305 movs r3, #5 8004f88: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004f8c: e024 b.n 8004fd8 case srFinish: default: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004f8e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f92: 6a1b ldr r3, [r3, #32] 8004f94: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004f98: 4618 mov r0, r3 8004f9a: f00e fd46 bl 8013a2a uartTaskData->frameBytesCount = 0; 8004f9e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004fa2: 2200 movs r2, #0 8004fa4: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 8004fa6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004faa: 6a1b ldr r3, [r3, #32] 8004fac: 4618 mov r0, r3 8004fae: f00e fd87 bl 8013ac0 spFrameData.frameHeader.frameCommand = spUnknown; 8004fb2: f507 73a0 add.w r3, r7, #320 @ 0x140 8004fb6: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004fba: 2212 movs r2, #18 8004fbc: 709a strb r2, [r3, #2] frameTotalLength = 0; 8004fbe: 2300 movs r3, #0 8004fc0: f8a7 313e strh.w r3, [r7, #318] @ 0x13e outputDataBufferPos = 0; 8004fc4: 4b08 ldr r3, [pc, #32] @ (8004fe8 ) 8004fc6: 2200 movs r2, #0 8004fc8: 801a strh r2, [r3, #0] receverState = srWaitForHeader; 8004fca: 2300 movs r3, #0 8004fcc: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdFALSE; 8004fd0: 2300 movs r3, #0 8004fd2: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 8004fd6: bf00 nop while (proceed) { 8004fd8: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 8004fdc: 2b00 cmp r3, #0 8004fde: f47f ae09 bne.w 8004bf4 frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8004fe2: e5b8 b.n 8004b56 8004fe4: 24000400 .word 0x24000400 8004fe8: 24001078 .word 0x24001078 08004fec : } } } } void Uart8ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 8004fec: b580 push {r7, lr} 8004fee: b082 sub sp, #8 8004ff0: af00 add r7, sp, #0 8004ff2: 6078 str r0, [r7, #4] 8004ff4: 6039 str r1, [r7, #0] Uart1ReceivedDataProcessCallback (arg, spFrameData); 8004ff6: 6839 ldr r1, [r7, #0] 8004ff8: 6878 ldr r0, [r7, #4] 8004ffa: f000 f805 bl 8005008 } 8004ffe: bf00 nop 8005000: 3708 adds r7, #8 8005002: 46bd mov sp, r7 8005004: bd80 pop {r7, pc} ... 08005008 : void Uart1ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 8005008: b590 push {r4, r7, lr} 800500a: b0ab sub sp, #172 @ 0xac 800500c: af06 add r7, sp, #24 800500e: 6078 str r0, [r7, #4] 8005010: 6039 str r1, [r7, #0] 8005012: f107 0390 add.w r3, r7, #144 @ 0x90 8005016: 3b88 subs r3, #136 @ 0x88 8005018: 331f adds r3, #31 800501a: 095b lsrs r3, r3, #5 800501c: 015c lsls r4, r3, #5 UartTaskData* uartTaskData = (UartTaskData*)arg; 800501e: 687b ldr r3, [r7, #4] 8005020: 66fb str r3, [r7, #108] @ 0x6c uint16_t dataToSend = 0; 8005022: 2300 movs r3, #0 8005024: f8a7 306a strh.w r3, [r7, #106] @ 0x6a outputDataBufferPos = 0; 8005028: 4bba ldr r3, [pc, #744] @ (8005314 ) 800502a: 2200 movs r2, #0 800502c: 801a strh r2, [r3, #0] uint16_t inputDataBufferPos = 0; 800502e: 2300 movs r3, #0 8005030: f8a7 3054 strh.w r3, [r7, #84] @ 0x54 SerialProtocolRespStatus respStatus = spUnknownCommand; 8005034: 23fd movs r3, #253 @ 0xfd 8005036: f887 308f strb.w r3, [r7, #143] @ 0x8f switch (spFrameData->frameHeader.frameCommand) { 800503a: 683b ldr r3, [r7, #0] 800503c: 789b ldrb r3, [r3, #2] 800503e: 2b11 cmp r3, #17 8005040: f200 8504 bhi.w 8005a4c 8005044: a201 add r2, pc, #4 @ (adr r2, 800504c ) 8005046: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800504a: bf00 nop 800504c: 08005095 .word 0x08005095 8005050: 080051a5 .word 0x080051a5 8005054: 08005391 .word 0x08005391 8005058: 0800544d .word 0x0800544d 800505c: 080054ef .word 0x080054ef 8005060: 0800560d .word 0x0800560d 8005064: 08005695 .word 0x08005695 8005068: 08005591 .word 0x08005591 800506c: 080056eb .word 0x080056eb 8005070: 0800575d .word 0x0800575d 8005074: 080057a9 .word 0x080057a9 8005078: 080057f5 .word 0x080057f5 800507c: 08005857 .word 0x08005857 8005080: 080058bb .word 0x080058bb 8005084: 0800591d .word 0x0800591d 8005088: 08005981 .word 0x08005981 800508c: 080059a5 .word 0x080059a5 8005090: 080059f9 .word 0x080059f9 case spGetElectricalMeasurments: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005094: 4ba0 ldr r3, [pc, #640] @ (8005318 ) 8005096: 681b ldr r3, [r3, #0] 8005098: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800509c: 4618 mov r0, r3 800509e: f00e fcc4 bl 8013a2a 80050a2: 4603 mov r3, r0 80050a4: 2b00 cmp r3, #0 80050a6: d178 bne.n 800519a for (int i = 0; i < 3; i++) { 80050a8: 2300 movs r3, #0 80050aa: f8c7 3088 str.w r3, [r7, #136] @ 0x88 80050ae: e00e b.n 80050ce WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltageRMS[i], sizeof (float)); 80050b0: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 80050b4: 009b lsls r3, r3, #2 80050b6: 4a99 ldr r2, [pc, #612] @ (800531c ) 80050b8: 441a add r2, r3 80050ba: 2304 movs r3, #4 80050bc: 4995 ldr r1, [pc, #596] @ (8005314 ) 80050be: 4898 ldr r0, [pc, #608] @ (8005320 ) 80050c0: f7fe fbd8 bl 8003874 for (int i = 0; i < 3; i++) { 80050c4: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 80050c8: 3301 adds r3, #1 80050ca: f8c7 3088 str.w r3, [r7, #136] @ 0x88 80050ce: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 80050d2: 2b02 cmp r3, #2 80050d4: ddec ble.n 80050b0 } for (int i = 0; i < 3; i++) { 80050d6: 2300 movs r3, #0 80050d8: f8c7 3084 str.w r3, [r7, #132] @ 0x84 80050dc: e010 b.n 8005100 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltagePeak[i], sizeof (float)); 80050de: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 80050e2: 3302 adds r3, #2 80050e4: 009b lsls r3, r3, #2 80050e6: 4a8d ldr r2, [pc, #564] @ (800531c ) 80050e8: 4413 add r3, r2 80050ea: 1d1a adds r2, r3, #4 80050ec: 2304 movs r3, #4 80050ee: 4989 ldr r1, [pc, #548] @ (8005314 ) 80050f0: 488b ldr r0, [pc, #556] @ (8005320 ) 80050f2: f7fe fbbf bl 8003874 for (int i = 0; i < 3; i++) { 80050f6: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 80050fa: 3301 adds r3, #1 80050fc: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8005100: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8005104: 2b02 cmp r3, #2 8005106: ddea ble.n 80050de } for (int i = 0; i < 3; i++) { 8005108: 2300 movs r3, #0 800510a: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800510e: e00f b.n 8005130 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentRMS[i], sizeof (float)); 8005110: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8005114: 3306 adds r3, #6 8005116: 009b lsls r3, r3, #2 8005118: 4a80 ldr r2, [pc, #512] @ (800531c ) 800511a: 441a add r2, r3 800511c: 2304 movs r3, #4 800511e: 497d ldr r1, [pc, #500] @ (8005314 ) 8005120: 487f ldr r0, [pc, #508] @ (8005320 ) 8005122: f7fe fba7 bl 8003874 for (int i = 0; i < 3; i++) { 8005126: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 800512a: 3301 adds r3, #1 800512c: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8005130: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8005134: 2b02 cmp r3, #2 8005136: ddeb ble.n 8005110 } for (int i = 0; i < 3; i++) { 8005138: 2300 movs r3, #0 800513a: 67fb str r3, [r7, #124] @ 0x7c 800513c: e00d b.n 800515a WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentPeak[i], sizeof (float)); 800513e: 6ffb ldr r3, [r7, #124] @ 0x7c 8005140: 3308 adds r3, #8 8005142: 009b lsls r3, r3, #2 8005144: 4a75 ldr r2, [pc, #468] @ (800531c ) 8005146: 4413 add r3, r2 8005148: 1d1a adds r2, r3, #4 800514a: 2304 movs r3, #4 800514c: 4971 ldr r1, [pc, #452] @ (8005314 ) 800514e: 4874 ldr r0, [pc, #464] @ (8005320 ) 8005150: f7fe fb90 bl 8003874 for (int i = 0; i < 3; i++) { 8005154: 6ffb ldr r3, [r7, #124] @ 0x7c 8005156: 3301 adds r3, #1 8005158: 67fb str r3, [r7, #124] @ 0x7c 800515a: 6ffb ldr r3, [r7, #124] @ 0x7c 800515c: 2b02 cmp r3, #2 800515e: ddee ble.n 800513e } for (int i = 0; i < 3; i++) { 8005160: 2300 movs r3, #0 8005162: 67bb str r3, [r7, #120] @ 0x78 8005164: e00c b.n 8005180 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.power[i], sizeof (float)); 8005166: 6fbb ldr r3, [r7, #120] @ 0x78 8005168: 330c adds r3, #12 800516a: 009b lsls r3, r3, #2 800516c: 4a6b ldr r2, [pc, #428] @ (800531c ) 800516e: 441a add r2, r3 8005170: 2304 movs r3, #4 8005172: 4968 ldr r1, [pc, #416] @ (8005314 ) 8005174: 486a ldr r0, [pc, #424] @ (8005320 ) 8005176: f7fe fb7d bl 8003874 for (int i = 0; i < 3; i++) { 800517a: 6fbb ldr r3, [r7, #120] @ 0x78 800517c: 3301 adds r3, #1 800517e: 67bb str r3, [r7, #120] @ 0x78 8005180: 6fbb ldr r3, [r7, #120] @ 0x78 8005182: 2b02 cmp r3, #2 8005184: ddef ble.n 8005166 } osMutexRelease (resMeasurementsMutex); 8005186: 4b64 ldr r3, [pc, #400] @ (8005318 ) 8005188: 681b ldr r3, [r3, #0] 800518a: 4618 mov r0, r3 800518c: f00e fc98 bl 8013ac0 respStatus = spOK; 8005190: 2300 movs r3, #0 8005192: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 8005196: f000 bc60 b.w 8005a5a respStatus = spInternalError; 800519a: 23fc movs r3, #252 @ 0xfc 800519c: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 80051a0: f000 bc5b b.w 8005a5a case spGetSensorMeasurments: if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80051a4: 4b5f ldr r3, [pc, #380] @ (8005324 ) 80051a6: 681b ldr r3, [r3, #0] 80051a8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80051ac: 4618 mov r0, r3 80051ae: f00e fc3c bl 8013a2a 80051b2: 4603 mov r3, r0 80051b4: 2b00 cmp r3, #0 80051b6: f040 80e7 bne.w 8005388 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[0], sizeof (float)); 80051ba: 2304 movs r3, #4 80051bc: 4a5a ldr r2, [pc, #360] @ (8005328 ) 80051be: 4955 ldr r1, [pc, #340] @ (8005314 ) 80051c0: 4857 ldr r0, [pc, #348] @ (8005320 ) 80051c2: f7fe fb57 bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[1], sizeof (float)); 80051c6: 2304 movs r3, #4 80051c8: 4a58 ldr r2, [pc, #352] @ (800532c ) 80051ca: 4952 ldr r1, [pc, #328] @ (8005314 ) 80051cc: 4854 ldr r0, [pc, #336] @ (8005320 ) 80051ce: f7fe fb51 bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.fanVoltage, sizeof (float)); 80051d2: 2304 movs r3, #4 80051d4: 4a56 ldr r2, [pc, #344] @ (8005330 ) 80051d6: 494f ldr r1, [pc, #316] @ (8005314 ) 80051d8: 4851 ldr r0, [pc, #324] @ (8005320 ) 80051da: f7fe fb4b bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderX, sizeof (float)); 80051de: 2304 movs r3, #4 80051e0: 4a54 ldr r2, [pc, #336] @ (8005334 ) 80051e2: 494c ldr r1, [pc, #304] @ (8005314 ) 80051e4: 484e ldr r0, [pc, #312] @ (8005320 ) 80051e6: f7fe fb45 bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderY, sizeof (float)); 80051ea: 2304 movs r3, #4 80051ec: 4a52 ldr r2, [pc, #328] @ (8005338 ) 80051ee: 4949 ldr r1, [pc, #292] @ (8005314 ) 80051f0: 484b ldr r0, [pc, #300] @ (8005320 ) 80051f2: f7fe fb3f bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXStatus, sizeof (uint8_t)); 80051f6: 2301 movs r3, #1 80051f8: 4a50 ldr r2, [pc, #320] @ (800533c ) 80051fa: 4946 ldr r1, [pc, #280] @ (8005314 ) 80051fc: 4848 ldr r0, [pc, #288] @ (8005320 ) 80051fe: f7fe fb39 bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYStatus, sizeof (uint8_t)); 8005202: 2301 movs r3, #1 8005204: 4a4e ldr r2, [pc, #312] @ (8005340 ) 8005206: 4943 ldr r1, [pc, #268] @ (8005314 ) 8005208: 4845 ldr r0, [pc, #276] @ (8005320 ) 800520a: f7fe fb33 bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXAveCurrent, sizeof (float)); 800520e: 2304 movs r3, #4 8005210: 4a4c ldr r2, [pc, #304] @ (8005344 ) 8005212: 4940 ldr r1, [pc, #256] @ (8005314 ) 8005214: 4842 ldr r0, [pc, #264] @ (8005320 ) 8005216: f7fe fb2d bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYAveCurrent, sizeof (float)); 800521a: 2304 movs r3, #4 800521c: 4a4a ldr r2, [pc, #296] @ (8005348 ) 800521e: 493d ldr r1, [pc, #244] @ (8005314 ) 8005220: 483f ldr r0, [pc, #252] @ (8005320 ) 8005222: f7fe fb27 bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXPeakCurrent, sizeof (float)); 8005226: 2304 movs r3, #4 8005228: 4a48 ldr r2, [pc, #288] @ (800534c ) 800522a: 493a ldr r1, [pc, #232] @ (8005314 ) 800522c: 483c ldr r0, [pc, #240] @ (8005320 ) 800522e: f7fe fb21 bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYPeakCurrent, sizeof (float)); 8005232: 2304 movs r3, #4 8005234: 4a46 ldr r2, [pc, #280] @ (8005350 ) 8005236: 4937 ldr r1, [pc, #220] @ (8005314 ) 8005238: 4839 ldr r0, [pc, #228] @ (8005320 ) 800523a: f7fe fb1b bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchUp, sizeof (uint8_t)); 800523e: 2301 movs r3, #1 8005240: 4a44 ldr r2, [pc, #272] @ (8005354 ) 8005242: 4934 ldr r1, [pc, #208] @ (8005314 ) 8005244: 4836 ldr r0, [pc, #216] @ (8005320 ) 8005246: f7fe fb15 bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchDown, sizeof (uint8_t)); 800524a: 2301 movs r3, #1 800524c: 4a42 ldr r2, [pc, #264] @ (8005358 ) 800524e: 4931 ldr r1, [pc, #196] @ (8005314 ) 8005250: 4833 ldr r0, [pc, #204] @ (8005320 ) 8005252: f7fe fb0f bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchCenter, sizeof (uint8_t)); 8005256: 2301 movs r3, #1 8005258: 4a40 ldr r2, [pc, #256] @ (800535c ) 800525a: 492e ldr r1, [pc, #184] @ (8005314 ) 800525c: 4830 ldr r0, [pc, #192] @ (8005320 ) 800525e: f7fe fb09 bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchUp, sizeof (uint8_t)); 8005262: 2301 movs r3, #1 8005264: 4a3e ldr r2, [pc, #248] @ (8005360 ) 8005266: 492b ldr r1, [pc, #172] @ (8005314 ) 8005268: 482d ldr r0, [pc, #180] @ (8005320 ) 800526a: f7fe fb03 bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchDown, sizeof (uint8_t)); 800526e: 2301 movs r3, #1 8005270: 4a3c ldr r2, [pc, #240] @ (8005364 ) 8005272: 4928 ldr r1, [pc, #160] @ (8005314 ) 8005274: 482a ldr r0, [pc, #168] @ (8005320 ) 8005276: f7fe fafd bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchCenter, sizeof (uint8_t)); 800527a: 2301 movs r3, #1 800527c: 4a3a ldr r2, [pc, #232] @ (8005368 ) 800527e: 4925 ldr r1, [pc, #148] @ (8005314 ) 8005280: 4827 ldr r0, [pc, #156] @ (8005320 ) 8005282: f7fe faf7 bl 8003874 uint8_t comparatorOutput = HAL_COMP_GetOutputLevel (&hcomp1) == COMP_OUTPUT_LEVEL_HIGH ? 1 : 0; 8005286: 4839 ldr r0, [pc, #228] @ (800536c ) 8005288: f002 fa62 bl 8007750 800528c: 4603 mov r3, r0 800528e: 2b01 cmp r3, #1 8005290: bf0c ite eq 8005292: 2301 moveq r3, #1 8005294: 2300 movne r3, #0 8005296: b2db uxtb r3, r3 8005298: f887 3057 strb.w r3, [r7, #87] @ 0x57 sensorsInfo.powerSupplyFailMask = ~((comparatorOutput << 1) | HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_3)) & 0x01; 800529c: f897 3057 ldrb.w r3, [r7, #87] @ 0x57 80052a0: 005c lsls r4, r3, #1 80052a2: 2108 movs r1, #8 80052a4: 4832 ldr r0, [pc, #200] @ (8005370 ) 80052a6: f006 f80b bl 800b2c0 80052aa: 4603 mov r3, r0 80052ac: 4323 orrs r3, r4 80052ae: f003 0301 and.w r3, r3, #1 80052b2: 2b00 cmp r3, #0 80052b4: bf0c ite eq 80052b6: 2301 moveq r3, #1 80052b8: 2300 movne r3, #0 80052ba: b2db uxtb r3, r3 80052bc: 461a mov r2, r3 80052be: 4b1a ldr r3, [pc, #104] @ (8005328 ) 80052c0: f883 202e strb.w r2, [r3, #46] @ 0x2e WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.powerSupplyFailMask, sizeof (uint8_t)); 80052c4: 2301 movs r3, #1 80052c6: 4a2b ldr r2, [pc, #172] @ (8005374 ) 80052c8: 4912 ldr r1, [pc, #72] @ (8005314 ) 80052ca: 4815 ldr r0, [pc, #84] @ (8005320 ) 80052cc: f7fe fad2 bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.currentXPosition, sizeof (float)); 80052d0: 2304 movs r3, #4 80052d2: 4a29 ldr r2, [pc, #164] @ (8005378 ) 80052d4: 490f ldr r1, [pc, #60] @ (8005314 ) 80052d6: 4812 ldr r0, [pc, #72] @ (8005320 ) 80052d8: f7fe facc bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.currentYPosition, sizeof (float)); 80052dc: 2304 movs r3, #4 80052de: 4a27 ldr r2, [pc, #156] @ (800537c ) 80052e0: 490c ldr r1, [pc, #48] @ (8005314 ) 80052e2: 480f ldr r0, [pc, #60] @ (8005320 ) 80052e4: f7fe fac6 bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.positionXWeak, sizeof (uint8_t)); 80052e8: 2301 movs r3, #1 80052ea: 4a25 ldr r2, [pc, #148] @ (8005380 ) 80052ec: 4909 ldr r1, [pc, #36] @ (8005314 ) 80052ee: 480c ldr r0, [pc, #48] @ (8005320 ) 80052f0: f7fe fac0 bl 8003874 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.positionYWeak, sizeof (uint8_t)); 80052f4: 2301 movs r3, #1 80052f6: 4a23 ldr r2, [pc, #140] @ (8005384 ) 80052f8: 4906 ldr r1, [pc, #24] @ (8005314 ) 80052fa: 4809 ldr r0, [pc, #36] @ (8005320 ) 80052fc: f7fe faba bl 8003874 osMutexRelease (sensorsInfoMutex); 8005300: 4b08 ldr r3, [pc, #32] @ (8005324 ) 8005302: 681b ldr r3, [r3, #0] 8005304: 4618 mov r0, r3 8005306: f00e fbdb bl 8013ac0 respStatus = spOK; 800530a: 2300 movs r3, #0 800530c: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 8005310: e3a3 b.n 8005a5a 8005312: bf00 nop 8005314: 24001078 .word 0x24001078 8005318: 2400078c .word 0x2400078c 800531c: 240007a0 .word 0x240007a0 8005320: 24000ff8 .word 0x24000ff8 8005324: 24000790 .word 0x24000790 8005328: 240007e0 .word 0x240007e0 800532c: 240007e4 .word 0x240007e4 8005330: 240007e8 .word 0x240007e8 8005334: 240007ec .word 0x240007ec 8005338: 240007f0 .word 0x240007f0 800533c: 240007f4 .word 0x240007f4 8005340: 240007f5 .word 0x240007f5 8005344: 240007f8 .word 0x240007f8 8005348: 240007fc .word 0x240007fc 800534c: 24000800 .word 0x24000800 8005350: 24000804 .word 0x24000804 8005354: 24000808 .word 0x24000808 8005358: 24000809 .word 0x24000809 800535c: 2400080a .word 0x2400080a 8005360: 2400080b .word 0x2400080b 8005364: 2400080c .word 0x2400080c 8005368: 2400080d .word 0x2400080d 800536c: 240003d4 .word 0x240003d4 8005370: 58020c00 .word 0x58020c00 8005374: 2400080e .word 0x2400080e 8005378: 24000810 .word 0x24000810 800537c: 24000814 .word 0x24000814 8005380: 24000818 .word 0x24000818 8005384: 24000819 .word 0x24000819 respStatus = spInternalError; 8005388: 23fc movs r3, #252 @ 0xfc 800538a: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 800538e: e364 b.n 8005a5a case spSetFanSpeed: osTimerStop (fanTimerHandle); 8005390: 4bb4 ldr r3, [pc, #720] @ (8005664 ) 8005392: 681b ldr r3, [r3, #0] 8005394: 4618 mov r0, r3 8005396: f00e fa8b bl 80138b0 int32_t fanTimerPeriod = 0; 800539a: 2300 movs r3, #0 800539c: 653b str r3, [r7, #80] @ 0x50 uint32_t pulse = 0; 800539e: 2300 movs r3, #0 80053a0: 64fb str r3, [r7, #76] @ 0x4c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse); 80053a2: 683b ldr r3, [r7, #0] 80053a4: 330c adds r3, #12 80053a6: f107 024c add.w r2, r7, #76 @ 0x4c 80053aa: f107 0154 add.w r1, r7, #84 @ 0x54 80053ae: 4618 mov r0, r3 80053b0: f7fe fac6 bl 8003940 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&fanTimerPeriod); 80053b4: 683b ldr r3, [r7, #0] 80053b6: 330c adds r3, #12 80053b8: f107 0250 add.w r2, r7, #80 @ 0x50 80053bc: f107 0154 add.w r1, r7, #84 @ 0x54 80053c0: 4618 mov r0, r3 80053c2: f7fe fabd bl 8003940 fanTimerConfigOC.Pulse = pulse * 10; 80053c6: 6cfa ldr r2, [r7, #76] @ 0x4c 80053c8: 4613 mov r3, r2 80053ca: 009b lsls r3, r3, #2 80053cc: 4413 add r3, r2 80053ce: 005b lsls r3, r3, #1 80053d0: 461a mov r2, r3 80053d2: 4ba5 ldr r3, [pc, #660] @ (8005668 ) 80053d4: 605a str r2, [r3, #4] if (HAL_TIM_PWM_ConfigChannel (&htim1, &fanTimerConfigOC, TIM_CHANNEL_2) != HAL_OK) { 80053d6: 2204 movs r2, #4 80053d8: 49a3 ldr r1, [pc, #652] @ (8005668 ) 80053da: 48a4 ldr r0, [pc, #656] @ (800566c ) 80053dc: f00a fad0 bl 800f980 80053e0: 4603 mov r3, r0 80053e2: 2b00 cmp r3, #0 80053e4: d001 beq.n 80053ea Error_Handler (); 80053e6: f7fc fbf1 bl 8001bcc } if (fanTimerPeriod > 0) { 80053ea: 6d3b ldr r3, [r7, #80] @ 0x50 80053ec: 2b00 cmp r3, #0 80053ee: dd0f ble.n 8005410 osTimerStart (fanTimerHandle, fanTimerPeriod * 1000); 80053f0: 4b9c ldr r3, [pc, #624] @ (8005664 ) 80053f2: 681a ldr r2, [r3, #0] 80053f4: 6d3b ldr r3, [r7, #80] @ 0x50 80053f6: f44f 717a mov.w r1, #1000 @ 0x3e8 80053fa: fb01 f303 mul.w r3, r1, r3 80053fe: 4619 mov r1, r3 8005400: 4610 mov r0, r2 8005402: f00e fa27 bl 8013854 HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 8005406: 2104 movs r1, #4 8005408: 4898 ldr r0, [pc, #608] @ (800566c ) 800540a: f00a f80d bl 800f428 800540e: e019 b.n 8005444 } else if (fanTimerPeriod == 0) { 8005410: 6d3b ldr r3, [r7, #80] @ 0x50 8005412: 2b00 cmp r3, #0 8005414: d109 bne.n 800542a osTimerStop (fanTimerHandle); 8005416: 4b93 ldr r3, [pc, #588] @ (8005664 ) 8005418: 681b ldr r3, [r3, #0] 800541a: 4618 mov r0, r3 800541c: f00e fa48 bl 80138b0 HAL_TIM_PWM_Stop (&htim1, TIM_CHANNEL_2); 8005420: 2104 movs r1, #4 8005422: 4892 ldr r0, [pc, #584] @ (800566c ) 8005424: f00a f90e bl 800f644 8005428: e00c b.n 8005444 } else if (fanTimerPeriod == -1) { 800542a: 6d3b ldr r3, [r7, #80] @ 0x50 800542c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8005430: d108 bne.n 8005444 osTimerStop (fanTimerHandle); 8005432: 4b8c ldr r3, [pc, #560] @ (8005664 ) 8005434: 681b ldr r3, [r3, #0] 8005436: 4618 mov r0, r3 8005438: f00e fa3a bl 80138b0 HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 800543c: 2104 movs r1, #4 800543e: 488b ldr r0, [pc, #556] @ (800566c ) 8005440: f009 fff2 bl 800f428 } respStatus = spOK; 8005444: 2300 movs r3, #0 8005446: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 800544a: e306 b.n 8005a5a case spSetMotorXOn: int32_t motorXPWMPulse = 0; 800544c: 2300 movs r3, #0 800544e: 64bb str r3, [r7, #72] @ 0x48 int32_t motorXTimerPeriod = 0; 8005450: 2300 movs r3, #0 8005452: 647b str r3, [r7, #68] @ 0x44 uint32_t motorXStatus = 0; 8005454: 2300 movs r3, #0 8005456: 65bb str r3, [r7, #88] @ 0x58 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXPWMPulse); 8005458: 683b ldr r3, [r7, #0] 800545a: 330c adds r3, #12 800545c: f107 0248 add.w r2, r7, #72 @ 0x48 8005460: f107 0154 add.w r1, r7, #84 @ 0x54 8005464: 4618 mov r0, r3 8005466: f7fe fa6b bl 8003940 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXTimerPeriod); 800546a: 683b ldr r3, [r7, #0] 800546c: 330c adds r3, #12 800546e: f107 0244 add.w r2, r7, #68 @ 0x44 8005472: f107 0154 add.w r1, r7, #84 @ 0x54 8005476: 4618 mov r0, r3 8005478: f7fe fa62 bl 8003940 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800547c: 4b7c ldr r3, [pc, #496] @ (8005670 ) 800547e: 681b ldr r3, [r3, #0] 8005480: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005484: 4618 mov r0, r3 8005486: f00e fad0 bl 8013a2a 800548a: 4603 mov r3, r0 800548c: 2b00 cmp r3, #0 800548e: d12a bne.n 80054e6 motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, motorXPWMPulse, motorXTimerPeriod, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 8005490: 4b78 ldr r3, [pc, #480] @ (8005674 ) 8005492: 681b ldr r3, [r3, #0] 8005494: 6cba ldr r2, [r7, #72] @ 0x48 8005496: 6c79 ldr r1, [r7, #68] @ 0x44 8005498: 4877 ldr r0, [pc, #476] @ (8005678 ) 800549a: f890 0028 ldrb.w r0, [r0, #40] @ 0x28 800549e: 4c76 ldr r4, [pc, #472] @ (8005678 ) 80054a0: f894 4029 ldrb.w r4, [r4, #41] @ 0x29 80054a4: 9404 str r4, [sp, #16] 80054a6: 9003 str r0, [sp, #12] 80054a8: 9102 str r1, [sp, #8] 80054aa: 9201 str r2, [sp, #4] 80054ac: 9300 str r3, [sp, #0] 80054ae: 2304 movs r3, #4 80054b0: 2200 movs r2, #0 80054b2: 4972 ldr r1, [pc, #456] @ (800567c ) 80054b4: 4872 ldr r0, [pc, #456] @ (8005680 ) 80054b6: f7fd fcbf bl 8002e38 80054ba: 4603 mov r3, r0 motorXStatus = 80054bc: 65bb str r3, [r7, #88] @ 0x58 sensorsInfo.motorXStatus = motorXStatus; 80054be: 6dbb ldr r3, [r7, #88] @ 0x58 80054c0: b2da uxtb r2, r3 80054c2: 4b6d ldr r3, [pc, #436] @ (8005678 ) 80054c4: 751a strb r2, [r3, #20] if (motorXStatus == 1) { 80054c6: 6dbb ldr r3, [r7, #88] @ 0x58 80054c8: 2b01 cmp r3, #1 80054ca: d103 bne.n 80054d4 sensorsInfo.motorXPeakCurrent = 0.0; 80054cc: 4b6a ldr r3, [pc, #424] @ (8005678 ) 80054ce: f04f 0200 mov.w r2, #0 80054d2: 621a str r2, [r3, #32] } osMutexRelease (sensorsInfoMutex); 80054d4: 4b66 ldr r3, [pc, #408] @ (8005670 ) 80054d6: 681b ldr r3, [r3, #0] 80054d8: 4618 mov r0, r3 80054da: f00e faf1 bl 8013ac0 respStatus = spOK; 80054de: 2300 movs r3, #0 80054e0: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 80054e4: e2b9 b.n 8005a5a respStatus = spInternalError; 80054e6: 23fc movs r3, #252 @ 0xfc 80054e8: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 80054ec: e2b5 b.n 8005a5a case spSetMotorYOn: int32_t motorYPWMPulse = 0; 80054ee: 2300 movs r3, #0 80054f0: 643b str r3, [r7, #64] @ 0x40 int32_t motorYTimerPeriod = 0; 80054f2: 2300 movs r3, #0 80054f4: 63fb str r3, [r7, #60] @ 0x3c uint32_t motorYStatus = 0; 80054f6: 2300 movs r3, #0 80054f8: 65fb str r3, [r7, #92] @ 0x5c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYPWMPulse); 80054fa: 683b ldr r3, [r7, #0] 80054fc: 330c adds r3, #12 80054fe: f107 0240 add.w r2, r7, #64 @ 0x40 8005502: f107 0154 add.w r1, r7, #84 @ 0x54 8005506: 4618 mov r0, r3 8005508: f7fe fa1a bl 8003940 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYTimerPeriod); 800550c: 683b ldr r3, [r7, #0] 800550e: 330c adds r3, #12 8005510: f107 023c add.w r2, r7, #60 @ 0x3c 8005514: f107 0154 add.w r1, r7, #84 @ 0x54 8005518: 4618 mov r0, r3 800551a: f7fe fa11 bl 8003940 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800551e: 4b54 ldr r3, [pc, #336] @ (8005670 ) 8005520: 681b ldr r3, [r3, #0] 8005522: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005526: 4618 mov r0, r3 8005528: f00e fa7f bl 8013a2a 800552c: 4603 mov r3, r0 800552e: 2b00 cmp r3, #0 8005530: d12a bne.n 8005588 motorYStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, motorYPWMPulse, motorYTimerPeriod, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 8005532: 4b54 ldr r3, [pc, #336] @ (8005684 ) 8005534: 681b ldr r3, [r3, #0] 8005536: 6c3a ldr r2, [r7, #64] @ 0x40 8005538: 6bf9 ldr r1, [r7, #60] @ 0x3c 800553a: 484f ldr r0, [pc, #316] @ (8005678 ) 800553c: f890 002b ldrb.w r0, [r0, #43] @ 0x2b 8005540: 4c4d ldr r4, [pc, #308] @ (8005678 ) 8005542: f894 402c ldrb.w r4, [r4, #44] @ 0x2c 8005546: 9404 str r4, [sp, #16] 8005548: 9003 str r0, [sp, #12] 800554a: 9102 str r1, [sp, #8] 800554c: 9201 str r2, [sp, #4] 800554e: 9300 str r3, [sp, #0] 8005550: 230c movs r3, #12 8005552: 2208 movs r2, #8 8005554: 4949 ldr r1, [pc, #292] @ (800567c ) 8005556: 484a ldr r0, [pc, #296] @ (8005680 ) 8005558: f7fd fc6e bl 8002e38 800555c: 4603 mov r3, r0 motorYStatus = 800555e: 65fb str r3, [r7, #92] @ 0x5c sensorsInfo.motorYStatus = motorYStatus; 8005560: 6dfb ldr r3, [r7, #92] @ 0x5c 8005562: b2da uxtb r2, r3 8005564: 4b44 ldr r3, [pc, #272] @ (8005678 ) 8005566: 755a strb r2, [r3, #21] if (motorYStatus == 1) { 8005568: 6dfb ldr r3, [r7, #92] @ 0x5c 800556a: 2b01 cmp r3, #1 800556c: d103 bne.n 8005576 sensorsInfo.motorYPeakCurrent = 0.0; 800556e: 4b42 ldr r3, [pc, #264] @ (8005678 ) 8005570: f04f 0200 mov.w r2, #0 8005574: 625a str r2, [r3, #36] @ 0x24 } osMutexRelease (sensorsInfoMutex); 8005576: 4b3e ldr r3, [pc, #248] @ (8005670 ) 8005578: 681b ldr r3, [r3, #0] 800557a: 4618 mov r0, r3 800557c: f00e faa0 bl 8013ac0 respStatus = spOK; 8005580: 2300 movs r3, #0 8005582: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 8005586: e268 b.n 8005a5a respStatus = spInternalError; 8005588: 23fc movs r3, #252 @ 0xfc 800558a: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 800558e: e264 b.n 8005a5a case spSetDiodeOn: osTimerStop (debugLedTimerHandle); 8005590: 4b3d ldr r3, [pc, #244] @ (8005688 ) 8005592: 681b ldr r3, [r3, #0] 8005594: 4618 mov r0, r3 8005596: f00e f98b bl 80138b0 int32_t dbgLedTimerPeriod = 0; 800559a: 2300 movs r3, #0 800559c: 63bb str r3, [r7, #56] @ 0x38 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&dbgLedTimerPeriod); 800559e: 683b ldr r3, [r7, #0] 80055a0: 330c adds r3, #12 80055a2: f107 0238 add.w r2, r7, #56 @ 0x38 80055a6: f107 0154 add.w r1, r7, #84 @ 0x54 80055aa: 4618 mov r0, r3 80055ac: f7fe f9c8 bl 8003940 if (dbgLedTimerPeriod > 0) { 80055b0: 6bbb ldr r3, [r7, #56] @ 0x38 80055b2: 2b00 cmp r3, #0 80055b4: dd0e ble.n 80055d4 osTimerStart (debugLedTimerHandle, dbgLedTimerPeriod * 1000); 80055b6: 4b34 ldr r3, [pc, #208] @ (8005688 ) 80055b8: 681a ldr r2, [r3, #0] 80055ba: 6bbb ldr r3, [r7, #56] @ 0x38 80055bc: f44f 717a mov.w r1, #1000 @ 0x3e8 80055c0: fb01 f303 mul.w r3, r1, r3 80055c4: 4619 mov r1, r3 80055c6: 4610 mov r0, r2 80055c8: f00e f944 bl 8013854 DbgLEDOn (DBG_LED1); 80055cc: 2010 movs r0, #16 80055ce: f7fd fba5 bl 8002d1c 80055d2: e017 b.n 8005604 } else if (dbgLedTimerPeriod == 0) { 80055d4: 6bbb ldr r3, [r7, #56] @ 0x38 80055d6: 2b00 cmp r3, #0 80055d8: d108 bne.n 80055ec osTimerStop (debugLedTimerHandle); 80055da: 4b2b ldr r3, [pc, #172] @ (8005688 ) 80055dc: 681b ldr r3, [r3, #0] 80055de: 4618 mov r0, r3 80055e0: f00e f966 bl 80138b0 DbgLEDOff (DBG_LED1); 80055e4: 2010 movs r0, #16 80055e6: f7fd fbab bl 8002d40 80055ea: e00b b.n 8005604 } else if (dbgLedTimerPeriod == -1) { 80055ec: 6bbb ldr r3, [r7, #56] @ 0x38 80055ee: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80055f2: d107 bne.n 8005604 osTimerStop (debugLedTimerHandle); 80055f4: 4b24 ldr r3, [pc, #144] @ (8005688 ) 80055f6: 681b ldr r3, [r3, #0] 80055f8: 4618 mov r0, r3 80055fa: f00e f959 bl 80138b0 DbgLEDOn (DBG_LED1); 80055fe: 2010 movs r0, #16 8005600: f7fd fb8c bl 8002d1c } respStatus = spOK; 8005604: 2300 movs r3, #0 8005606: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 800560a: e226 b.n 8005a5a case spSetmotorXMaxCurrent: float motorXMaxCurrent = 0; 800560c: f04f 0300 mov.w r3, #0 8005610: 637b str r3, [r7, #52] @ 0x34 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXMaxCurrent); 8005612: 683b ldr r3, [r7, #0] 8005614: 330c adds r3, #12 8005616: f107 0234 add.w r2, r7, #52 @ 0x34 800561a: f107 0154 add.w r1, r7, #84 @ 0x54 800561e: 4618 mov r0, r3 8005620: f7fe f98e bl 8003940 uint32_t dacDataCh1 = (uint32_t)(4095 * motorXMaxCurrent / (EXT_VREF_mV * 0.001)); 8005624: edd7 7a0d vldr s15, [r7, #52] @ 0x34 8005628: ed9f 7a19 vldr s14, [pc, #100] @ 8005690 800562c: ee67 7a87 vmul.f32 s15, s15, s14 8005630: eeb7 6ae7 vcvt.f64.f32 d6, s15 8005634: eeb0 5b08 vmov.f64 d5, #8 @ 0x40400000 3.0 8005638: ee86 7b05 vdiv.f64 d7, d6, d5 800563c: eefc 7bc7 vcvt.u32.f64 s15, d7 8005640: ee17 3a90 vmov r3, s15 8005644: 663b str r3, [r7, #96] @ 0x60 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, dacDataCh1); 8005646: 6e3b ldr r3, [r7, #96] @ 0x60 8005648: 2200 movs r2, #0 800564a: 2100 movs r1, #0 800564c: 480f ldr r0, [pc, #60] @ (800568c ) 800564e: f002 fcca bl 8007fe6 HAL_DAC_Start (&hdac1, DAC_CHANNEL_1); 8005652: 2100 movs r1, #0 8005654: 480d ldr r0, [pc, #52] @ (800568c ) 8005656: f002 fc19 bl 8007e8c respStatus = spOK; 800565a: 2300 movs r3, #0 800565c: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 8005660: e1fb b.n 8005a5a 8005662: bf00 nop 8005664: 2400068c .word 0x2400068c 8005668: 2400071c .word 0x2400071c 800566c: 2400044c .word 0x2400044c 8005670: 24000790 .word 0x24000790 8005674: 240006bc .word 0x240006bc 8005678: 240007e0 .word 0x240007e0 800567c: 24000738 .word 0x24000738 8005680: 24000498 .word 0x24000498 8005684: 240006ec .word 0x240006ec 8005688: 2400065c .word 0x2400065c 800568c: 24000424 .word 0x24000424 8005690: 457ff000 .word 0x457ff000 case spSetmotorYMaxCurrent: float motorYMaxCurrent = 0; 8005694: f04f 0300 mov.w r3, #0 8005698: 633b str r3, [r7, #48] @ 0x30 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYMaxCurrent); 800569a: 683b ldr r3, [r7, #0] 800569c: 330c adds r3, #12 800569e: f107 0230 add.w r2, r7, #48 @ 0x30 80056a2: f107 0154 add.w r1, r7, #84 @ 0x54 80056a6: 4618 mov r0, r3 80056a8: f7fe f94a bl 8003940 uint32_t dacDataCh2 = (uint32_t)(4095 * motorYMaxCurrent / (EXT_VREF_mV * 0.001)); 80056ac: edd7 7a0c vldr s15, [r7, #48] @ 0x30 80056b0: ed1f 7a09 vldr s14, [pc, #-36] @ 8005690 80056b4: ee67 7a87 vmul.f32 s15, s15, s14 80056b8: eeb7 6ae7 vcvt.f64.f32 d6, s15 80056bc: eeb0 5b08 vmov.f64 d5, #8 @ 0x40400000 3.0 80056c0: ee86 7b05 vdiv.f64 d7, d6, d5 80056c4: eefc 7bc7 vcvt.u32.f64 s15, d7 80056c8: ee17 3a90 vmov r3, s15 80056cc: 667b str r3, [r7, #100] @ 0x64 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, dacDataCh2); 80056ce: 6e7b ldr r3, [r7, #100] @ 0x64 80056d0: 2200 movs r2, #0 80056d2: 2110 movs r1, #16 80056d4: 48ac ldr r0, [pc, #688] @ (8005988 ) 80056d6: f002 fc86 bl 8007fe6 HAL_DAC_Start (&hdac1, DAC_CHANNEL_2); 80056da: 2110 movs r1, #16 80056dc: 48aa ldr r0, [pc, #680] @ (8005988 ) 80056de: f002 fbd5 bl 8007e8c respStatus = spOK; 80056e2: 2300 movs r3, #0 80056e4: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 80056e8: e1b7 b.n 8005a5a case spClearPeakMeasurments: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 80056ea: 4ba8 ldr r3, [pc, #672] @ (800598c ) 80056ec: 681b ldr r3, [r3, #0] 80056ee: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80056f2: 4618 mov r0, r3 80056f4: f00e f999 bl 8013a2a 80056f8: 4603 mov r3, r0 80056fa: 2b00 cmp r3, #0 80056fc: d12a bne.n 8005754 for (int i = 0; i < 3; i++) { 80056fe: 2300 movs r3, #0 8005700: 677b str r3, [r7, #116] @ 0x74 8005702: e01b b.n 800573c resMeasurements.voltagePeak[i] = resMeasurements.voltageRMS[i]; 8005704: 4aa2 ldr r2, [pc, #648] @ (8005990 ) 8005706: 6f7b ldr r3, [r7, #116] @ 0x74 8005708: 009b lsls r3, r3, #2 800570a: 4413 add r3, r2 800570c: 681a ldr r2, [r3, #0] 800570e: 49a0 ldr r1, [pc, #640] @ (8005990 ) 8005710: 6f7b ldr r3, [r7, #116] @ 0x74 8005712: 3302 adds r3, #2 8005714: 009b lsls r3, r3, #2 8005716: 440b add r3, r1 8005718: 3304 adds r3, #4 800571a: 601a str r2, [r3, #0] resMeasurements.currentPeak[i] = resMeasurements.currentRMS[i]; 800571c: 4a9c ldr r2, [pc, #624] @ (8005990 ) 800571e: 6f7b ldr r3, [r7, #116] @ 0x74 8005720: 3306 adds r3, #6 8005722: 009b lsls r3, r3, #2 8005724: 4413 add r3, r2 8005726: 681a ldr r2, [r3, #0] 8005728: 4999 ldr r1, [pc, #612] @ (8005990 ) 800572a: 6f7b ldr r3, [r7, #116] @ 0x74 800572c: 3308 adds r3, #8 800572e: 009b lsls r3, r3, #2 8005730: 440b add r3, r1 8005732: 3304 adds r3, #4 8005734: 601a str r2, [r3, #0] for (int i = 0; i < 3; i++) { 8005736: 6f7b ldr r3, [r7, #116] @ 0x74 8005738: 3301 adds r3, #1 800573a: 677b str r3, [r7, #116] @ 0x74 800573c: 6f7b ldr r3, [r7, #116] @ 0x74 800573e: 2b02 cmp r3, #2 8005740: dde0 ble.n 8005704 } osMutexRelease (resMeasurementsMutex); 8005742: 4b92 ldr r3, [pc, #584] @ (800598c ) 8005744: 681b ldr r3, [r3, #0] 8005746: 4618 mov r0, r3 8005748: f00e f9ba bl 8013ac0 respStatus = spOK; 800574c: 2300 movs r3, #0 800574e: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 8005752: e182 b.n 8005a5a respStatus = spInternalError; 8005754: 23fc movs r3, #252 @ 0xfc 8005756: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 800575a: e17e b.n 8005a5a case spSetEncoderXValue: float enocoderXValue = 0; 800575c: f04f 0300 mov.w r3, #0 8005760: 62fb str r3, [r7, #44] @ 0x2c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderXValue); 8005762: 683b ldr r3, [r7, #0] 8005764: 330c adds r3, #12 8005766: f107 022c add.w r2, r7, #44 @ 0x2c 800576a: f107 0154 add.w r1, r7, #84 @ 0x54 800576e: 4618 mov r0, r3 8005770: f7fe f8e6 bl 8003940 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8005774: 4b87 ldr r3, [pc, #540] @ (8005994 ) 8005776: 681b ldr r3, [r3, #0] 8005778: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800577c: 4618 mov r0, r3 800577e: f00e f954 bl 8013a2a 8005782: 4603 mov r3, r0 8005784: 2b00 cmp r3, #0 8005786: d10b bne.n 80057a0 sensorsInfo.pvEncoderX = enocoderXValue; 8005788: 6afb ldr r3, [r7, #44] @ 0x2c 800578a: 4a83 ldr r2, [pc, #524] @ (8005998 ) 800578c: 60d3 str r3, [r2, #12] osMutexRelease (sensorsInfoMutex); 800578e: 4b81 ldr r3, [pc, #516] @ (8005994 ) 8005790: 681b ldr r3, [r3, #0] 8005792: 4618 mov r0, r3 8005794: f00e f994 bl 8013ac0 respStatus = spOK; 8005798: 2300 movs r3, #0 800579a: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 800579e: e15c b.n 8005a5a respStatus = spInternalError; 80057a0: 23fc movs r3, #252 @ 0xfc 80057a2: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 80057a6: e158 b.n 8005a5a case spSetEncoderYValue: float enocoderYValue = 0; 80057a8: f04f 0300 mov.w r3, #0 80057ac: 62bb str r3, [r7, #40] @ 0x28 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderYValue); 80057ae: 683b ldr r3, [r7, #0] 80057b0: 330c adds r3, #12 80057b2: f107 0228 add.w r2, r7, #40 @ 0x28 80057b6: f107 0154 add.w r1, r7, #84 @ 0x54 80057ba: 4618 mov r0, r3 80057bc: f7fe f8c0 bl 8003940 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80057c0: 4b74 ldr r3, [pc, #464] @ (8005994 ) 80057c2: 681b ldr r3, [r3, #0] 80057c4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80057c8: 4618 mov r0, r3 80057ca: f00e f92e bl 8013a2a 80057ce: 4603 mov r3, r0 80057d0: 2b00 cmp r3, #0 80057d2: d10b bne.n 80057ec sensorsInfo.pvEncoderY = enocoderYValue; 80057d4: 6abb ldr r3, [r7, #40] @ 0x28 80057d6: 4a70 ldr r2, [pc, #448] @ (8005998 ) 80057d8: 6113 str r3, [r2, #16] osMutexRelease (sensorsInfoMutex); 80057da: 4b6e ldr r3, [pc, #440] @ (8005994 ) 80057dc: 681b ldr r3, [r3, #0] 80057de: 4618 mov r0, r3 80057e0: f00e f96e bl 8013ac0 respStatus = spOK; 80057e4: 2300 movs r3, #0 80057e6: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 80057ea: e136 b.n 8005a5a respStatus = spInternalError; 80057ec: 23fc movs r3, #252 @ 0xfc 80057ee: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 80057f2: e132 b.n 8005a5a case spSetVoltageMeasGains: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 80057f4: 4b65 ldr r3, [pc, #404] @ (800598c ) 80057f6: 681b ldr r3, [r3, #0] 80057f8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80057fc: 4618 mov r0, r3 80057fe: f00e f914 bl 8013a2a 8005802: 4603 mov r3, r0 8005804: 2b00 cmp r3, #0 8005806: d122 bne.n 800584e for (uint8_t i = 0; i < 3; i++) { 8005808: 2300 movs r3, #0 800580a: f887 3073 strb.w r3, [r7, #115] @ 0x73 800580e: e011 b.n 8005834 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].gain); 8005810: 683b ldr r3, [r7, #0] 8005812: f103 000c add.w r0, r3, #12 8005816: f897 3073 ldrb.w r3, [r7, #115] @ 0x73 800581a: 00db lsls r3, r3, #3 800581c: 4a5f ldr r2, [pc, #380] @ (800599c ) 800581e: 441a add r2, r3 8005820: f107 0354 add.w r3, r7, #84 @ 0x54 8005824: 4619 mov r1, r3 8005826: f7fe f88b bl 8003940 for (uint8_t i = 0; i < 3; i++) { 800582a: f897 3073 ldrb.w r3, [r7, #115] @ 0x73 800582e: 3301 adds r3, #1 8005830: f887 3073 strb.w r3, [r7, #115] @ 0x73 8005834: f897 3073 ldrb.w r3, [r7, #115] @ 0x73 8005838: 2b02 cmp r3, #2 800583a: d9e9 bls.n 8005810 } osMutexRelease (resMeasurementsMutex); 800583c: 4b53 ldr r3, [pc, #332] @ (800598c ) 800583e: 681b ldr r3, [r3, #0] 8005840: 4618 mov r0, r3 8005842: f00e f93d bl 8013ac0 respStatus = spOK; 8005846: 2300 movs r3, #0 8005848: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 800584c: e105 b.n 8005a5a respStatus = spInternalError; 800584e: 23fc movs r3, #252 @ 0xfc 8005850: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 8005854: e101 b.n 8005a5a case spSetVoltageMeasOffsets: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005856: 4b4d ldr r3, [pc, #308] @ (800598c ) 8005858: 681b ldr r3, [r3, #0] 800585a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800585e: 4618 mov r0, r3 8005860: f00e f8e3 bl 8013a2a 8005864: 4603 mov r3, r0 8005866: 2b00 cmp r3, #0 8005868: d123 bne.n 80058b2 for (uint8_t i = 0; i < 3; i++) { 800586a: 2300 movs r3, #0 800586c: f887 3072 strb.w r3, [r7, #114] @ 0x72 8005870: e012 b.n 8005898 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].offset); 8005872: 683b ldr r3, [r7, #0] 8005874: f103 000c add.w r0, r3, #12 8005878: f897 3072 ldrb.w r3, [r7, #114] @ 0x72 800587c: 00db lsls r3, r3, #3 800587e: 4a47 ldr r2, [pc, #284] @ (800599c ) 8005880: 4413 add r3, r2 8005882: 1d1a adds r2, r3, #4 8005884: f107 0354 add.w r3, r7, #84 @ 0x54 8005888: 4619 mov r1, r3 800588a: f7fe f859 bl 8003940 for (uint8_t i = 0; i < 3; i++) { 800588e: f897 3072 ldrb.w r3, [r7, #114] @ 0x72 8005892: 3301 adds r3, #1 8005894: f887 3072 strb.w r3, [r7, #114] @ 0x72 8005898: f897 3072 ldrb.w r3, [r7, #114] @ 0x72 800589c: 2b02 cmp r3, #2 800589e: d9e8 bls.n 8005872 } osMutexRelease (resMeasurementsMutex); 80058a0: 4b3a ldr r3, [pc, #232] @ (800598c ) 80058a2: 681b ldr r3, [r3, #0] 80058a4: 4618 mov r0, r3 80058a6: f00e f90b bl 8013ac0 respStatus = spOK; 80058aa: 2300 movs r3, #0 80058ac: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 80058b0: e0d3 b.n 8005a5a respStatus = spInternalError; 80058b2: 23fc movs r3, #252 @ 0xfc 80058b4: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 80058b8: e0cf b.n 8005a5a case spSetCurrentMeasGains: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 80058ba: 4b34 ldr r3, [pc, #208] @ (800598c ) 80058bc: 681b ldr r3, [r3, #0] 80058be: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80058c2: 4618 mov r0, r3 80058c4: f00e f8b1 bl 8013a2a 80058c8: 4603 mov r3, r0 80058ca: 2b00 cmp r3, #0 80058cc: d122 bne.n 8005914 for (uint8_t i = 0; i < 3; i++) { 80058ce: 2300 movs r3, #0 80058d0: f887 3071 strb.w r3, [r7, #113] @ 0x71 80058d4: e011 b.n 80058fa ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].gain); 80058d6: 683b ldr r3, [r7, #0] 80058d8: f103 000c add.w r0, r3, #12 80058dc: f897 3071 ldrb.w r3, [r7, #113] @ 0x71 80058e0: 00db lsls r3, r3, #3 80058e2: 4a2f ldr r2, [pc, #188] @ (80059a0 ) 80058e4: 441a add r2, r3 80058e6: f107 0354 add.w r3, r7, #84 @ 0x54 80058ea: 4619 mov r1, r3 80058ec: f7fe f828 bl 8003940 for (uint8_t i = 0; i < 3; i++) { 80058f0: f897 3071 ldrb.w r3, [r7, #113] @ 0x71 80058f4: 3301 adds r3, #1 80058f6: f887 3071 strb.w r3, [r7, #113] @ 0x71 80058fa: f897 3071 ldrb.w r3, [r7, #113] @ 0x71 80058fe: 2b02 cmp r3, #2 8005900: d9e9 bls.n 80058d6 } osMutexRelease (resMeasurementsMutex); 8005902: 4b22 ldr r3, [pc, #136] @ (800598c ) 8005904: 681b ldr r3, [r3, #0] 8005906: 4618 mov r0, r3 8005908: f00e f8da bl 8013ac0 respStatus = spOK; 800590c: 2300 movs r3, #0 800590e: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 8005912: e0a2 b.n 8005a5a respStatus = spInternalError; 8005914: 23fc movs r3, #252 @ 0xfc 8005916: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 800591a: e09e b.n 8005a5a case spSetCurrentMeasOffsets: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 800591c: 4b1b ldr r3, [pc, #108] @ (800598c ) 800591e: 681b ldr r3, [r3, #0] 8005920: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005924: 4618 mov r0, r3 8005926: f00e f880 bl 8013a2a 800592a: 4603 mov r3, r0 800592c: 2b00 cmp r3, #0 800592e: d123 bne.n 8005978 for (uint8_t i = 0; i < 3; i++) { 8005930: 2300 movs r3, #0 8005932: f887 3070 strb.w r3, [r7, #112] @ 0x70 8005936: e012 b.n 800595e ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].offset); 8005938: 683b ldr r3, [r7, #0] 800593a: f103 000c add.w r0, r3, #12 800593e: f897 3070 ldrb.w r3, [r7, #112] @ 0x70 8005942: 00db lsls r3, r3, #3 8005944: 4a16 ldr r2, [pc, #88] @ (80059a0 ) 8005946: 4413 add r3, r2 8005948: 1d1a adds r2, r3, #4 800594a: f107 0354 add.w r3, r7, #84 @ 0x54 800594e: 4619 mov r1, r3 8005950: f7fd fff6 bl 8003940 for (uint8_t i = 0; i < 3; i++) { 8005954: f897 3070 ldrb.w r3, [r7, #112] @ 0x70 8005958: 3301 adds r3, #1 800595a: f887 3070 strb.w r3, [r7, #112] @ 0x70 800595e: f897 3070 ldrb.w r3, [r7, #112] @ 0x70 8005962: 2b02 cmp r3, #2 8005964: d9e8 bls.n 8005938 } osMutexRelease (resMeasurementsMutex); 8005966: 4b09 ldr r3, [pc, #36] @ (800598c ) 8005968: 681b ldr r3, [r3, #0] 800596a: 4618 mov r0, r3 800596c: f00e f8a8 bl 8013ac0 respStatus = spOK; 8005970: 2300 movs r3, #0 8005972: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 8005976: e070 b.n 8005a5a respStatus = spInternalError; 8005978: 23fc movs r3, #252 @ 0xfc 800597a: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 800597e: e06c b.n 8005a5a __ASM volatile ("cpsid i" : : : "memory"); 8005980: b672 cpsid i } 8005982: bf00 nop case spResetSystem: __disable_irq(); NVIC_SystemReset(); 8005984: f7fe ff72 bl 800486c <__NVIC_SystemReset> 8005988: 24000424 .word 0x24000424 800598c: 2400078c .word 0x2400078c 8005990: 240007a0 .word 0x240007a0 8005994: 24000790 .word 0x24000790 8005998: 240007e0 .word 0x240007e0 800599c: 24000000 .word 0x24000000 80059a0: 24000018 .word 0x24000018 break; case spSetPositonX: PositionControlTaskData posXData __attribute__ ((aligned (32))) = { 0 }; 80059a4: f04f 0300 mov.w r3, #0 80059a8: 6023 str r3, [r4, #0] if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80059aa: 4b3e ldr r3, [pc, #248] @ (8005aa4 ) 80059ac: 681b ldr r3, [r3, #0] 80059ae: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80059b2: 4618 mov r0, r3 80059b4: f00e f839 bl 8013a2a 80059b8: 4603 mov r3, r0 80059ba: 2b00 cmp r3, #0 80059bc: d108 bne.n 80059d0 sensorsInfo.positionXWeak = 1; 80059be: 4b3a ldr r3, [pc, #232] @ (8005aa8 ) 80059c0: 2201 movs r2, #1 80059c2: f883 2038 strb.w r2, [r3, #56] @ 0x38 osMutexRelease (sensorsInfoMutex); 80059c6: 4b37 ldr r3, [pc, #220] @ (8005aa4 ) 80059c8: 681b ldr r3, [r3, #0] 80059ca: 4618 mov r0, r3 80059cc: f00e f878 bl 8013ac0 } if (positionXControlTaskInitArg.positionSettingQueue != NULL) 80059d0: 4b36 ldr r3, [pc, #216] @ (8005aac ) 80059d2: 691b ldr r3, [r3, #16] 80059d4: 2b00 cmp r3, #0 80059d6: d03d beq.n 8005a54 { ReadFloatFromBuffer(spFrameData->dataBuffer, &inputDataBufferPos, &posXData.positionSettingValue); 80059d8: 683b ldr r3, [r7, #0] 80059da: 330c adds r3, #12 80059dc: f107 0154 add.w r1, r7, #84 @ 0x54 80059e0: 4622 mov r2, r4 80059e2: 4618 mov r0, r3 80059e4: f7fd ff77 bl 80038d6 osMessageQueuePut(positionXControlTaskInitArg.positionSettingQueue, &posXData, 0, 0); 80059e8: 4b30 ldr r3, [pc, #192] @ (8005aac ) 80059ea: 6918 ldr r0, [r3, #16] 80059ec: 2300 movs r3, #0 80059ee: 2200 movs r2, #0 80059f0: 4621 mov r1, r4 80059f2: f00e f915 bl 8013c20 } break; 80059f6: e02d b.n 8005a54 case spSetPositonY: if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80059f8: 4b2a ldr r3, [pc, #168] @ (8005aa4 ) 80059fa: 681b ldr r3, [r3, #0] 80059fc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005a00: 4618 mov r0, r3 8005a02: f00e f812 bl 8013a2a 8005a06: 4603 mov r3, r0 8005a08: 2b00 cmp r3, #0 8005a0a: d108 bne.n 8005a1e sensorsInfo.positionYWeak = 1; 8005a0c: 4b26 ldr r3, [pc, #152] @ (8005aa8 ) 8005a0e: 2201 movs r2, #1 8005a10: f883 2039 strb.w r2, [r3, #57] @ 0x39 osMutexRelease (sensorsInfoMutex); 8005a14: 4b23 ldr r3, [pc, #140] @ (8005aa4 ) 8005a16: 681b ldr r3, [r3, #0] 8005a18: 4618 mov r0, r3 8005a1a: f00e f851 bl 8013ac0 } PositionControlTaskData posYData __attribute__ ((aligned (32))) = { 0 }; 8005a1e: f04f 0300 mov.w r3, #0 8005a22: 6023 str r3, [r4, #0] if (positionYControlTaskInitArg.positionSettingQueue != NULL) 8005a24: 4b22 ldr r3, [pc, #136] @ (8005ab0 ) 8005a26: 691b ldr r3, [r3, #16] 8005a28: 2b00 cmp r3, #0 8005a2a: d015 beq.n 8005a58 { ReadFloatFromBuffer(spFrameData->dataBuffer, &inputDataBufferPos, &posYData.positionSettingValue); 8005a2c: 683b ldr r3, [r7, #0] 8005a2e: 330c adds r3, #12 8005a30: f107 0154 add.w r1, r7, #84 @ 0x54 8005a34: 4622 mov r2, r4 8005a36: 4618 mov r0, r3 8005a38: f7fd ff4d bl 80038d6 osMessageQueuePut(positionYControlTaskInitArg.positionSettingQueue, &posYData, 0, 0); 8005a3c: 4b1c ldr r3, [pc, #112] @ (8005ab0 ) 8005a3e: 6918 ldr r0, [r3, #16] 8005a40: 2300 movs r3, #0 8005a42: 2200 movs r2, #0 8005a44: 4621 mov r1, r4 8005a46: f00e f8eb bl 8013c20 } break; 8005a4a: e005 b.n 8005a58 default: respStatus = spUnknownCommand; break; 8005a4c: 23fd movs r3, #253 @ 0xfd 8005a4e: f887 308f strb.w r3, [r7, #143] @ 0x8f 8005a52: e002 b.n 8005a5a break; 8005a54: bf00 nop 8005a56: e000 b.n 8005a5a break; 8005a58: bf00 nop } dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8005a5a: 6efb ldr r3, [r7, #108] @ 0x6c 8005a5c: 6898 ldr r0, [r3, #8] 8005a5e: 683b ldr r3, [r7, #0] 8005a60: 8819 ldrh r1, [r3, #0] 8005a62: 683b ldr r3, [r7, #0] 8005a64: 789a ldrb r2, [r3, #2] 8005a66: 4b13 ldr r3, [pc, #76] @ (8005ab4 ) 8005a68: 881b ldrh r3, [r3, #0] 8005a6a: f997 408f ldrsb.w r4, [r7, #143] @ 0x8f 8005a6e: 9301 str r3, [sp, #4] 8005a70: 4b11 ldr r3, [pc, #68] @ (8005ab8 ) 8005a72: 9300 str r3, [sp, #0] 8005a74: 4623 mov r3, r4 8005a76: f7fd ff97 bl 80039a8 8005a7a: 4603 mov r3, r0 8005a7c: f8a7 306a strh.w r3, [r7, #106] @ 0x6a if (dataToSend > 0) { 8005a80: f8b7 306a ldrh.w r3, [r7, #106] @ 0x6a 8005a84: 2b00 cmp r3, #0 8005a86: d008 beq.n 8005a9a HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 8005a88: 6efb ldr r3, [r7, #108] @ 0x6c 8005a8a: 6b18 ldr r0, [r3, #48] @ 0x30 8005a8c: 6efb ldr r3, [r7, #108] @ 0x6c 8005a8e: 689b ldr r3, [r3, #8] 8005a90: f8b7 206a ldrh.w r2, [r7, #106] @ 0x6a 8005a94: 4619 mov r1, r3 8005a96: f00a ff9b bl 80109d0 } #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: TX bytes sent: %d\n", uartTaskData->uartNumber, dataToSend); #endif } 8005a9a: bf00 nop 8005a9c: 3794 adds r7, #148 @ 0x94 8005a9e: 46bd mov sp, r7 8005aa0: bd90 pop {r4, r7, pc} 8005aa2: bf00 nop 8005aa4: 24000790 .word 0x24000790 8005aa8: 240007e0 .word 0x240007e0 8005aac: 240008c0 .word 0x240008c0 8005ab0: 24000900 .word 0x24000900 8005ab4: 24001078 .word 0x24001078 8005ab8: 24000ff8 .word 0x24000ff8 08005abc : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8005abc: f8df d034 ldr.w sp, [pc, #52] @ 8005af4 /* Call the clock system initialization function.*/ bl SystemInit 8005ac0: f7fe fe4c bl 800475c /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8005ac4: 480c ldr r0, [pc, #48] @ (8005af8 ) ldr r1, =_edata 8005ac6: 490d ldr r1, [pc, #52] @ (8005afc ) ldr r2, =_sidata 8005ac8: 4a0d ldr r2, [pc, #52] @ (8005b00 ) movs r3, #0 8005aca: 2300 movs r3, #0 b LoopCopyDataInit 8005acc: e002 b.n 8005ad4 08005ace : CopyDataInit: ldr r4, [r2, r3] 8005ace: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8005ad0: 50c4 str r4, [r0, r3] adds r3, r3, #4 8005ad2: 3304 adds r3, #4 08005ad4 : LoopCopyDataInit: adds r4, r0, r3 8005ad4: 18c4 adds r4, r0, r3 cmp r4, r1 8005ad6: 428c cmp r4, r1 bcc CopyDataInit 8005ad8: d3f9 bcc.n 8005ace /* Zero fill the bss segment. */ ldr r2, =_sbss 8005ada: 4a0a ldr r2, [pc, #40] @ (8005b04 ) ldr r4, =_ebss 8005adc: 4c0a ldr r4, [pc, #40] @ (8005b08 ) movs r3, #0 8005ade: 2300 movs r3, #0 b LoopFillZerobss 8005ae0: e001 b.n 8005ae6 08005ae2 : FillZerobss: str r3, [r2] 8005ae2: 6013 str r3, [r2, #0] adds r2, r2, #4 8005ae4: 3204 adds r2, #4 08005ae6 : LoopFillZerobss: cmp r2, r4 8005ae6: 42a2 cmp r2, r4 bcc FillZerobss 8005ae8: d3fb bcc.n 8005ae2 /* Call static constructors */ bl __libc_init_array 8005aea: f012 f979 bl 8017de0 <__libc_init_array> /* Call the application's entry point.*/ bl main 8005aee: f7fa fe6b bl 80007c8
bx lr 8005af2: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8005af4: 24060000 .word 0x24060000 ldr r0, =_sdata 8005af8: 24000000 .word 0x24000000 ldr r1, =_edata 8005afc: 240000a4 .word 0x240000a4 ldr r2, =_sidata 8005b00: 08018be8 .word 0x08018be8 ldr r2, =_sbss 8005b04: 240000c0 .word 0x240000c0 ldr r4, =_ebss 8005b08: 240131b4 .word 0x240131b4 08005b0c : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8005b0c: e7fe b.n 8005b0c ... 08005b10 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8005b10: b580 push {r7, lr} 8005b12: b082 sub sp, #8 8005b14: af00 add r7, sp, #0 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ #endif /* DUAL_CORE && CORE_CM4 */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8005b16: 2003 movs r0, #3 8005b18: f001 fee5 bl 80078e6 /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8005b1c: f006 fb90 bl 800c240 8005b20: 4602 mov r2, r0 8005b22: 4b15 ldr r3, [pc, #84] @ (8005b78 ) 8005b24: 699b ldr r3, [r3, #24] 8005b26: 0a1b lsrs r3, r3, #8 8005b28: f003 030f and.w r3, r3, #15 8005b2c: 4913 ldr r1, [pc, #76] @ (8005b7c ) 8005b2e: 5ccb ldrb r3, [r1, r3] 8005b30: f003 031f and.w r3, r3, #31 8005b34: fa22 f303 lsr.w r3, r2, r3 8005b38: 607b str r3, [r7, #4] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8005b3a: 4b0f ldr r3, [pc, #60] @ (8005b78 ) 8005b3c: 699b ldr r3, [r3, #24] 8005b3e: f003 030f and.w r3, r3, #15 8005b42: 4a0e ldr r2, [pc, #56] @ (8005b7c ) 8005b44: 5cd3 ldrb r3, [r2, r3] 8005b46: f003 031f and.w r3, r3, #31 8005b4a: 687a ldr r2, [r7, #4] 8005b4c: fa22 f303 lsr.w r3, r2, r3 8005b50: 4a0b ldr r2, [pc, #44] @ (8005b80 ) 8005b52: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8005b54: 4a0b ldr r2, [pc, #44] @ (8005b84 ) 8005b56: 687b ldr r3, [r7, #4] 8005b58: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8005b5a: 2005 movs r0, #5 8005b5c: f7fe fc72 bl 8004444 8005b60: 4603 mov r3, r0 8005b62: 2b00 cmp r3, #0 8005b64: d001 beq.n 8005b6a { return HAL_ERROR; 8005b66: 2301 movs r3, #1 8005b68: e002 b.n 8005b70 } /* Init the low level hardware */ HAL_MspInit(); 8005b6a: f7fd ffbb bl 8003ae4 /* Return function status */ return HAL_OK; 8005b6e: 2300 movs r3, #0 } 8005b70: 4618 mov r0, r3 8005b72: 3708 adds r7, #8 8005b74: 46bd mov sp, r7 8005b76: bd80 pop {r7, pc} 8005b78: 58024400 .word 0x58024400 8005b7c: 08018b5c .word 0x08018b5c 8005b80: 24000038 .word 0x24000038 8005b84: 24000034 .word 0x24000034 08005b88 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8005b88: b480 push {r7} 8005b8a: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 8005b8c: 4b06 ldr r3, [pc, #24] @ (8005ba8 ) 8005b8e: 781b ldrb r3, [r3, #0] 8005b90: 461a mov r2, r3 8005b92: 4b06 ldr r3, [pc, #24] @ (8005bac ) 8005b94: 681b ldr r3, [r3, #0] 8005b96: 4413 add r3, r2 8005b98: 4a04 ldr r2, [pc, #16] @ (8005bac ) 8005b9a: 6013 str r3, [r2, #0] } 8005b9c: bf00 nop 8005b9e: 46bd mov sp, r7 8005ba0: f85d 7b04 ldr.w r7, [sp], #4 8005ba4: 4770 bx lr 8005ba6: bf00 nop 8005ba8: 24000040 .word 0x24000040 8005bac: 2400107c .word 0x2400107c 08005bb0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8005bb0: b480 push {r7} 8005bb2: af00 add r7, sp, #0 return uwTick; 8005bb4: 4b03 ldr r3, [pc, #12] @ (8005bc4 ) 8005bb6: 681b ldr r3, [r3, #0] } 8005bb8: 4618 mov r0, r3 8005bba: 46bd mov sp, r7 8005bbc: f85d 7b04 ldr.w r7, [sp], #4 8005bc0: 4770 bx lr 8005bc2: bf00 nop 8005bc4: 2400107c .word 0x2400107c 08005bc8 : /** * @brief Returns the device revision identifier. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { 8005bc8: b480 push {r7} 8005bca: af00 add r7, sp, #0 return((DBGMCU->IDCODE) >> 16); 8005bcc: 4b03 ldr r3, [pc, #12] @ (8005bdc ) 8005bce: 681b ldr r3, [r3, #0] 8005bd0: 0c1b lsrs r3, r3, #16 } 8005bd2: 4618 mov r0, r3 8005bd4: 46bd mov sp, r7 8005bd6: f85d 7b04 ldr.w r7, [sp], #4 8005bda: 4770 bx lr 8005bdc: 5c001000 .word 0x5c001000 08005be0 : * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. * @retval None */ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) { 8005be0: b480 push {r7} 8005be2: b083 sub sp, #12 8005be4: af00 add r7, sp, #0 8005be6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); 8005be8: 4b06 ldr r3, [pc, #24] @ (8005c04 ) 8005bea: 681b ldr r3, [r3, #0] 8005bec: f023 0202 bic.w r2, r3, #2 8005bf0: 4904 ldr r1, [pc, #16] @ (8005c04 ) 8005bf2: 687b ldr r3, [r7, #4] 8005bf4: 4313 orrs r3, r2 8005bf6: 600b str r3, [r1, #0] } 8005bf8: bf00 nop 8005bfa: 370c adds r7, #12 8005bfc: 46bd mov sp, r7 8005bfe: f85d 7b04 ldr.w r7, [sp], #4 8005c02: 4770 bx lr 8005c04: 58003c00 .word 0x58003c00 08005c08 : * @brief Disable the Internal Voltage Reference buffer (VREFBUF). * * @retval None */ void HAL_SYSCFG_DisableVREFBUF(void) { 8005c08: b480 push {r7} 8005c0a: af00 add r7, sp, #0 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); 8005c0c: 4b05 ldr r3, [pc, #20] @ (8005c24 ) 8005c0e: 681b ldr r3, [r3, #0] 8005c10: 4a04 ldr r2, [pc, #16] @ (8005c24 ) 8005c12: f023 0301 bic.w r3, r3, #1 8005c16: 6013 str r3, [r2, #0] } 8005c18: bf00 nop 8005c1a: 46bd mov sp, r7 8005c1c: f85d 7b04 ldr.w r7, [sp], #4 8005c20: 4770 bx lr 8005c22: bf00 nop 8005c24: 58003c00 .word 0x58003c00 08005c28 : * @arg SYSCFG_SWITCH_PC3_CLOSE * @retval None */ void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ) { 8005c28: b480 push {r7} 8005c2a: b083 sub sp, #12 8005c2c: af00 add r7, sp, #0 8005c2e: 6078 str r0, [r7, #4] 8005c30: 6039 str r1, [r7, #0] /* Check the parameter */ assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch)); assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState)); MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState)); 8005c32: 4b07 ldr r3, [pc, #28] @ (8005c50 ) 8005c34: 685a ldr r2, [r3, #4] 8005c36: 687b ldr r3, [r7, #4] 8005c38: 43db mvns r3, r3 8005c3a: 401a ands r2, r3 8005c3c: 4904 ldr r1, [pc, #16] @ (8005c50 ) 8005c3e: 683b ldr r3, [r7, #0] 8005c40: 4313 orrs r3, r2 8005c42: 604b str r3, [r1, #4] } 8005c44: bf00 nop 8005c46: 370c adds r7, #12 8005c48: 46bd mov sp, r7 8005c4a: f85d 7b04 ldr.w r7, [sp], #4 8005c4e: 4770 bx lr 8005c50: 58000400 .word 0x58000400 08005c54 : * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) { 8005c54: b480 push {r7} 8005c56: b083 sub sp, #12 8005c58: af00 add r7, sp, #0 8005c5a: 6078 str r0, [r7, #4] 8005c5c: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); 8005c5e: 687b ldr r3, [r7, #4] 8005c60: 689b ldr r3, [r3, #8] 8005c62: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000 8005c66: 683b ldr r3, [r7, #0] 8005c68: 431a orrs r2, r3 8005c6a: 687b ldr r3, [r7, #4] 8005c6c: 609a str r2, [r3, #8] } 8005c6e: bf00 nop 8005c70: 370c adds r7, #12 8005c72: 46bd mov sp, r7 8005c74: f85d 7b04 ldr.w r7, [sp], #4 8005c78: 4770 bx lr 08005c7a : * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { 8005c7a: b480 push {r7} 8005c7c: b083 sub sp, #12 8005c7e: af00 add r7, sp, #0 8005c80: 6078 str r0, [r7, #4] 8005c82: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); 8005c84: 687b ldr r3, [r7, #4] 8005c86: 689b ldr r3, [r3, #8] 8005c88: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000 8005c8c: 683b ldr r3, [r7, #0] 8005c8e: 431a orrs r2, r3 8005c90: 687b ldr r3, [r7, #4] 8005c92: 609a str r2, [r3, #8] } 8005c94: bf00 nop 8005c96: 370c adds r7, #12 8005c98: 46bd mov sp, r7 8005c9a: f85d 7b04 ldr.w r7, [sp], #4 8005c9e: 4770 bx lr 08005ca0 : * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) { 8005ca0: b480 push {r7} 8005ca2: b083 sub sp, #12 8005ca4: af00 add r7, sp, #0 8005ca6: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 8005ca8: 687b ldr r3, [r7, #4] 8005caa: 689b ldr r3, [r3, #8] 8005cac: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000 } 8005cb0: 4618 mov r0, r3 8005cb2: 370c adds r7, #12 8005cb4: 46bd mov sp, r7 8005cb6: f85d 7b04 ldr.w r7, [sp], #4 8005cba: 4770 bx lr 08005cbc : * Other channels are slow channels (conversion rate: refer to reference manual). * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x3FFFFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { 8005cbc: b480 push {r7} 8005cbe: b087 sub sp, #28 8005cc0: af00 add r7, sp, #0 8005cc2: 60f8 str r0, [r7, #12] 8005cc4: 60b9 str r1, [r7, #8] 8005cc6: 607a str r2, [r7, #4] 8005cc8: 603b str r3, [r7, #0] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8005cca: 68fb ldr r3, [r7, #12] 8005ccc: 3360 adds r3, #96 @ 0x60 8005cce: 461a mov r2, r3 8005cd0: 68bb ldr r3, [r7, #8] 8005cd2: 009b lsls r3, r3, #2 8005cd4: 4413 add r3, r2 8005cd6: 617b str r3, [r7, #20] ADC3_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } else #endif /* ADC_VER_V5_V90 */ { MODIFY_REG(*preg, 8005cd8: 697b ldr r3, [r7, #20] 8005cda: 681b ldr r3, [r3, #0] 8005cdc: f003 4200 and.w r2, r3, #2147483648 @ 0x80000000 8005ce0: 687b ldr r3, [r7, #4] 8005ce2: f003 41f8 and.w r1, r3, #2080374784 @ 0x7c000000 8005ce6: 683b ldr r3, [r7, #0] 8005ce8: 430b orrs r3, r1 8005cea: 431a orrs r2, r3 8005cec: 697b ldr r3, [r7, #20] 8005cee: 601a str r2, [r3, #0] ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } } 8005cf0: bf00 nop 8005cf2: 371c adds r7, #28 8005cf4: 46bd mov sp, r7 8005cf6: f85d 7b04 ldr.w r7, [sp], #4 8005cfa: 4770 bx lr 08005cfc : * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift) { 8005cfc: b480 push {r7} 8005cfe: b085 sub sp, #20 8005d00: af00 add r7, sp, #0 8005d02: 60f8 str r0, [r7, #12] 8005d04: 60b9 str r1, [r7, #8] 8005d06: 607a str r2, [r7, #4] MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL)); 8005d08: 68fb ldr r3, [r7, #12] 8005d0a: 691b ldr r3, [r3, #16] 8005d0c: f423 42f0 bic.w r2, r3, #30720 @ 0x7800 8005d10: 68bb ldr r3, [r7, #8] 8005d12: f003 031f and.w r3, r3, #31 8005d16: 6879 ldr r1, [r7, #4] 8005d18: fa01 f303 lsl.w r3, r1, r3 8005d1c: 431a orrs r2, r3 8005d1e: 68fb ldr r3, [r7, #12] 8005d20: 611a str r2, [r3, #16] } 8005d22: bf00 nop 8005d24: 3714 adds r7, #20 8005d26: 46bd mov sp, r7 8005d28: f85d 7b04 ldr.w r7, [sp], #4 8005d2c: 4770 bx lr 08005d2e : * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation) { 8005d2e: b480 push {r7} 8005d30: b087 sub sp, #28 8005d32: af00 add r7, sp, #0 8005d34: 60f8 str r0, [r7, #12] 8005d36: 60b9 str r1, [r7, #8] 8005d38: 607a str r2, [r7, #4] /* Function not available on this instance */ } else #endif /* ADC_VER_V5_V90 */ { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8005d3a: 68fb ldr r3, [r7, #12] 8005d3c: 3360 adds r3, #96 @ 0x60 8005d3e: 461a mov r2, r3 8005d40: 68bb ldr r3, [r7, #8] 8005d42: 009b lsls r3, r3, #2 8005d44: 4413 add r3, r2 8005d46: 617b str r3, [r7, #20] MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation); 8005d48: 697b ldr r3, [r7, #20] 8005d4a: 681b ldr r3, [r3, #0] 8005d4c: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 8005d50: 687b ldr r3, [r7, #4] 8005d52: 431a orrs r2, r3 8005d54: 697b ldr r3, [r7, #20] 8005d56: 601a str r2, [r3, #0] } } 8005d58: bf00 nop 8005d5a: 371c adds r7, #28 8005d5c: 46bd mov sp, r7 8005d5e: f85d 7b04 ldr.w r7, [sp], #4 8005d62: 4770 bx lr 08005d64 : * @param ADCx ADC instance * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { 8005d64: b480 push {r7} 8005d66: b083 sub sp, #12 8005d68: af00 add r7, sp, #0 8005d6a: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); 8005d6c: 687b ldr r3, [r7, #4] 8005d6e: 68db ldr r3, [r3, #12] 8005d70: f403 6340 and.w r3, r3, #3072 @ 0xc00 8005d74: 2b00 cmp r3, #0 8005d76: d101 bne.n 8005d7c 8005d78: 2301 movs r3, #1 8005d7a: e000 b.n 8005d7e 8005d7c: 2300 movs r3, #0 } 8005d7e: 4618 mov r0, r3 8005d80: 370c adds r7, #12 8005d82: 46bd mov sp, r7 8005d84: f85d 7b04 ldr.w r7, [sp], #4 8005d88: 4770 bx lr 08005d8a : * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { 8005d8a: b480 push {r7} 8005d8c: b087 sub sp, #28 8005d8e: af00 add r7, sp, #0 8005d90: 60f8 str r0, [r7, #12] 8005d92: 60b9 str r1, [r7, #8] 8005d94: 607a str r2, [r7, #4] /* Set bits with content of parameter "Channel" with bits position */ /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); 8005d96: 68fb ldr r3, [r7, #12] 8005d98: 3330 adds r3, #48 @ 0x30 8005d9a: 461a mov r2, r3 8005d9c: 68bb ldr r3, [r7, #8] 8005d9e: 0a1b lsrs r3, r3, #8 8005da0: 009b lsls r3, r3, #2 8005da2: f003 030c and.w r3, r3, #12 8005da6: 4413 add r3, r2 8005da8: 617b str r3, [r7, #20] MODIFY_REG(*preg, 8005daa: 697b ldr r3, [r7, #20] 8005dac: 681a ldr r2, [r3, #0] 8005dae: 68bb ldr r3, [r7, #8] 8005db0: f003 031f and.w r3, r3, #31 8005db4: 211f movs r1, #31 8005db6: fa01 f303 lsl.w r3, r1, r3 8005dba: 43db mvns r3, r3 8005dbc: 401a ands r2, r3 8005dbe: 687b ldr r3, [r7, #4] 8005dc0: 0e9b lsrs r3, r3, #26 8005dc2: f003 011f and.w r1, r3, #31 8005dc6: 68bb ldr r3, [r7, #8] 8005dc8: f003 031f and.w r3, r3, #31 8005dcc: fa01 f303 lsl.w r3, r1, r3 8005dd0: 431a orrs r2, r3 8005dd2: 697b ldr r3, [r7, #20] 8005dd4: 601a str r2, [r3, #0] ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } 8005dd6: bf00 nop 8005dd8: 371c adds r7, #28 8005dda: 46bd mov sp, r7 8005ddc: f85d 7b04 ldr.w r7, [sp], #4 8005de0: 4770 bx lr 08005de2 : * @param ADCx ADC instance * @param DataTransferMode Select Data Management configuration * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode) { 8005de2: b480 push {r7} 8005de4: b083 sub sp, #12 8005de6: af00 add r7, sp, #0 8005de8: 6078 str r0, [r7, #4] 8005dea: 6039 str r1, [r7, #0] MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode); 8005dec: 687b ldr r3, [r7, #4] 8005dee: 68db ldr r3, [r3, #12] 8005df0: f023 0203 bic.w r2, r3, #3 8005df4: 683b ldr r3, [r7, #0] 8005df6: 431a orrs r2, r3 8005df8: 687b ldr r3, [r7, #4] 8005dfa: 60da str r2, [r3, #12] } 8005dfc: bf00 nop 8005dfe: 370c adds r7, #12 8005e00: 46bd mov sp, r7 8005e02: f85d 7b04 ldr.w r7, [sp], #4 8005e06: 4770 bx lr 08005e08 : * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5 * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) { 8005e08: b480 push {r7} 8005e0a: b087 sub sp, #28 8005e0c: af00 add r7, sp, #0 8005e0e: 60f8 str r0, [r7, #12] 8005e10: 60b9 str r1, [r7, #8] 8005e12: 607a str r2, [r7, #4] /* Set bits with content of parameter "SamplingTime" with bits position */ /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 8005e14: 68fb ldr r3, [r7, #12] 8005e16: 3314 adds r3, #20 8005e18: 461a mov r2, r3 8005e1a: 68bb ldr r3, [r7, #8] 8005e1c: 0e5b lsrs r3, r3, #25 8005e1e: 009b lsls r3, r3, #2 8005e20: f003 0304 and.w r3, r3, #4 8005e24: 4413 add r3, r2 8005e26: 617b str r3, [r7, #20] MODIFY_REG(*preg, 8005e28: 697b ldr r3, [r7, #20] 8005e2a: 681a ldr r2, [r3, #0] 8005e2c: 68bb ldr r3, [r7, #8] 8005e2e: 0d1b lsrs r3, r3, #20 8005e30: f003 031f and.w r3, r3, #31 8005e34: 2107 movs r1, #7 8005e36: fa01 f303 lsl.w r3, r1, r3 8005e3a: 43db mvns r3, r3 8005e3c: 401a ands r2, r3 8005e3e: 68bb ldr r3, [r7, #8] 8005e40: 0d1b lsrs r3, r3, #20 8005e42: f003 031f and.w r3, r3, #31 8005e46: 6879 ldr r1, [r7, #4] 8005e48: fa01 f303 lsl.w r3, r1, r3 8005e4c: 431a orrs r2, r3 8005e4e: 697b ldr r3, [r7, #20] 8005e50: 601a str r2, [r3, #0] ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); } 8005e52: bf00 nop 8005e54: 371c adds r7, #28 8005e56: 46bd mov sp, r7 8005e58: f85d 7b04 ldr.w r7, [sp], #4 8005e5c: 4770 bx lr ... 08005e60 : * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) { 8005e60: b480 push {r7} 8005e62: b085 sub sp, #20 8005e64: af00 add r7, sp, #0 8005e66: 60f8 str r0, [r7, #12] 8005e68: 60b9 str r1, [r7, #8] 8005e6a: 607a str r2, [r7, #4] } #else /* ADC_VER_V5_V90 */ /* Bits of channels in single or differential mode are set only for */ /* differential mode (for single mode, mask of bits allowed to be set is */ /* shifted out of range of bits of channels in single or differential mode. */ MODIFY_REG(ADCx->DIFSEL, 8005e6c: 68fb ldr r3, [r7, #12] 8005e6e: f8d3 20c0 ldr.w r2, [r3, #192] @ 0xc0 8005e72: 68bb ldr r3, [r7, #8] 8005e74: f3c3 0313 ubfx r3, r3, #0, #20 8005e78: 43db mvns r3, r3 8005e7a: 401a ands r2, r3 8005e7c: 687b ldr r3, [r7, #4] 8005e7e: f003 0318 and.w r3, r3, #24 8005e82: 4908 ldr r1, [pc, #32] @ (8005ea4 ) 8005e84: 40d9 lsrs r1, r3 8005e86: 68bb ldr r3, [r7, #8] 8005e88: 400b ands r3, r1 8005e8a: f3c3 0313 ubfx r3, r3, #0, #20 8005e8e: 431a orrs r2, r3 8005e90: 68fb ldr r3, [r7, #12] 8005e92: f8c3 20c0 str.w r2, [r3, #192] @ 0xc0 Channel & ADC_SINGLEDIFF_CHANNEL_MASK, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); #endif /* ADC_VER_V5_V90 */ } 8005e96: bf00 nop 8005e98: 3714 adds r7, #20 8005e9a: 46bd mov sp, r7 8005e9c: f85d 7b04 ldr.w r7, [sp], #4 8005ea0: 4770 bx lr 8005ea2: bf00 nop 8005ea4: 000fffff .word 0x000fffff 08005ea8 : * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) { 8005ea8: b480 push {r7} 8005eaa: b083 sub sp, #12 8005eac: af00 add r7, sp, #0 8005eae: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 8005eb0: 687b ldr r3, [r7, #4] 8005eb2: 689b ldr r3, [r3, #8] 8005eb4: f003 031f and.w r3, r3, #31 } 8005eb8: 4618 mov r0, r3 8005eba: 370c adds r7, #12 8005ebc: 46bd mov sp, r7 8005ebe: f85d 7b04 ldr.w r7, [sp], #4 8005ec2: 4770 bx lr 08005ec4 : * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) { 8005ec4: b480 push {r7} 8005ec6: b083 sub sp, #12 8005ec8: af00 add r7, sp, #0 8005eca: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); 8005ecc: 687b ldr r3, [r7, #4] 8005ece: 689a ldr r2, [r3, #8] 8005ed0: 4b04 ldr r3, [pc, #16] @ (8005ee4 ) 8005ed2: 4013 ands r3, r2 8005ed4: 687a ldr r2, [r7, #4] 8005ed6: 6093 str r3, [r2, #8] } 8005ed8: bf00 nop 8005eda: 370c adds r7, #12 8005edc: 46bd mov sp, r7 8005ede: f85d 7b04 ldr.w r7, [sp], #4 8005ee2: 4770 bx lr 8005ee4: 5fffffc0 .word 0x5fffffc0 08005ee8 : * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) { 8005ee8: b480 push {r7} 8005eea: b083 sub sp, #12 8005eec: af00 add r7, sp, #0 8005eee: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); 8005ef0: 687b ldr r3, [r7, #4] 8005ef2: 689b ldr r3, [r3, #8] 8005ef4: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8005ef8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8005efc: d101 bne.n 8005f02 8005efe: 2301 movs r3, #1 8005f00: e000 b.n 8005f04 8005f02: 2300 movs r3, #0 } 8005f04: 4618 mov r0, r3 8005f06: 370c adds r7, #12 8005f08: 46bd mov sp, r7 8005f0a: f85d 7b04 ldr.w r7, [sp], #4 8005f0e: 4770 bx lr 08005f10 : * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) { 8005f10: b480 push {r7} 8005f12: b083 sub sp, #12 8005f14: af00 add r7, sp, #0 8005f16: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8005f18: 687b ldr r3, [r7, #4] 8005f1a: 689a ldr r2, [r3, #8] 8005f1c: 4b05 ldr r3, [pc, #20] @ (8005f34 ) 8005f1e: 4013 ands r3, r2 8005f20: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000 8005f24: 687b ldr r3, [r7, #4] 8005f26: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); } 8005f28: bf00 nop 8005f2a: 370c adds r7, #12 8005f2c: 46bd mov sp, r7 8005f2e: f85d 7b04 ldr.w r7, [sp], #4 8005f32: 4770 bx lr 8005f34: 6fffffc0 .word 0x6fffffc0 08005f38 : * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) { 8005f38: b480 push {r7} 8005f3a: b083 sub sp, #12 8005f3c: af00 add r7, sp, #0 8005f3e: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 8005f40: 687b ldr r3, [r7, #4] 8005f42: 689b ldr r3, [r3, #8] 8005f44: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8005f48: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8005f4c: d101 bne.n 8005f52 8005f4e: 2301 movs r3, #1 8005f50: e000 b.n 8005f54 8005f52: 2300 movs r3, #0 } 8005f54: 4618 mov r0, r3 8005f56: 370c adds r7, #12 8005f58: 46bd mov sp, r7 8005f5a: f85d 7b04 ldr.w r7, [sp], #4 8005f5e: 4770 bx lr 08005f60 : * @rmtoll CR ADEN LL_ADC_Enable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) { 8005f60: b480 push {r7} 8005f62: b083 sub sp, #12 8005f64: af00 add r7, sp, #0 8005f66: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8005f68: 687b ldr r3, [r7, #4] 8005f6a: 689a ldr r2, [r3, #8] 8005f6c: 4b05 ldr r3, [pc, #20] @ (8005f84 ) 8005f6e: 4013 ands r3, r2 8005f70: f043 0201 orr.w r2, r3, #1 8005f74: 687b ldr r3, [r7, #4] 8005f76: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN); } 8005f78: bf00 nop 8005f7a: 370c adds r7, #12 8005f7c: 46bd mov sp, r7 8005f7e: f85d 7b04 ldr.w r7, [sp], #4 8005f82: 4770 bx lr 8005f84: 7fffffc0 .word 0x7fffffc0 08005f88 : * @rmtoll CR ADDIS LL_ADC_Disable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) { 8005f88: b480 push {r7} 8005f8a: b083 sub sp, #12 8005f8c: af00 add r7, sp, #0 8005f8e: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8005f90: 687b ldr r3, [r7, #4] 8005f92: 689a ldr r2, [r3, #8] 8005f94: 4b05 ldr r3, [pc, #20] @ (8005fac ) 8005f96: 4013 ands r3, r2 8005f98: f043 0202 orr.w r2, r3, #2 8005f9c: 687b ldr r3, [r7, #4] 8005f9e: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS); } 8005fa0: bf00 nop 8005fa2: 370c adds r7, #12 8005fa4: 46bd mov sp, r7 8005fa6: f85d 7b04 ldr.w r7, [sp], #4 8005faa: 4770 bx lr 8005fac: 7fffffc0 .word 0x7fffffc0 08005fb0 : * @rmtoll CR ADEN LL_ADC_IsEnabled * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) { 8005fb0: b480 push {r7} 8005fb2: b083 sub sp, #12 8005fb4: af00 add r7, sp, #0 8005fb6: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8005fb8: 687b ldr r3, [r7, #4] 8005fba: 689b ldr r3, [r3, #8] 8005fbc: f003 0301 and.w r3, r3, #1 8005fc0: 2b01 cmp r3, #1 8005fc2: d101 bne.n 8005fc8 8005fc4: 2301 movs r3, #1 8005fc6: e000 b.n 8005fca 8005fc8: 2300 movs r3, #0 } 8005fca: 4618 mov r0, r3 8005fcc: 370c adds r7, #12 8005fce: 46bd mov sp, r7 8005fd0: f85d 7b04 ldr.w r7, [sp], #4 8005fd4: 4770 bx lr 08005fd6 : * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) { 8005fd6: b480 push {r7} 8005fd8: b083 sub sp, #12 8005fda: af00 add r7, sp, #0 8005fdc: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); 8005fde: 687b ldr r3, [r7, #4] 8005fe0: 689b ldr r3, [r3, #8] 8005fe2: f003 0302 and.w r3, r3, #2 8005fe6: 2b02 cmp r3, #2 8005fe8: d101 bne.n 8005fee 8005fea: 2301 movs r3, #1 8005fec: e000 b.n 8005ff0 8005fee: 2300 movs r3, #0 } 8005ff0: 4618 mov r0, r3 8005ff2: 370c adds r7, #12 8005ff4: 46bd mov sp, r7 8005ff6: f85d 7b04 ldr.w r7, [sp], #4 8005ffa: 4770 bx lr 08005ffc : * @rmtoll CR ADSTART LL_ADC_REG_StartConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) { 8005ffc: b480 push {r7} 8005ffe: b083 sub sp, #12 8006000: af00 add r7, sp, #0 8006002: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8006004: 687b ldr r3, [r7, #4] 8006006: 689a ldr r2, [r3, #8] 8006008: 4b05 ldr r3, [pc, #20] @ (8006020 ) 800600a: 4013 ands r3, r2 800600c: f043 0204 orr.w r2, r3, #4 8006010: 687b ldr r3, [r7, #4] 8006012: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART); } 8006014: bf00 nop 8006016: 370c adds r7, #12 8006018: 46bd mov sp, r7 800601a: f85d 7b04 ldr.w r7, [sp], #4 800601e: 4770 bx lr 8006020: 7fffffc0 .word 0x7fffffc0 08006024 : * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) { 8006024: b480 push {r7} 8006026: b083 sub sp, #12 8006028: af00 add r7, sp, #0 800602a: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 800602c: 687b ldr r3, [r7, #4] 800602e: 689b ldr r3, [r3, #8] 8006030: f003 0304 and.w r3, r3, #4 8006034: 2b04 cmp r3, #4 8006036: d101 bne.n 800603c 8006038: 2301 movs r3, #1 800603a: e000 b.n 800603e 800603c: 2300 movs r3, #0 } 800603e: 4618 mov r0, r3 8006040: 370c adds r7, #12 8006042: 46bd mov sp, r7 8006044: f85d 7b04 ldr.w r7, [sp], #4 8006048: 4770 bx lr 0800604a : * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) { 800604a: b480 push {r7} 800604c: b083 sub sp, #12 800604e: af00 add r7, sp, #0 8006050: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 8006052: 687b ldr r3, [r7, #4] 8006054: 689b ldr r3, [r3, #8] 8006056: f003 0308 and.w r3, r3, #8 800605a: 2b08 cmp r3, #8 800605c: d101 bne.n 8006062 800605e: 2301 movs r3, #1 8006060: e000 b.n 8006064 8006062: 2300 movs r3, #0 } 8006064: 4618 mov r0, r3 8006066: 370c adds r7, #12 8006068: 46bd mov sp, r7 800606a: f85d 7b04 ldr.w r7, [sp], #4 800606e: 4770 bx lr 08006070 : * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { 8006070: b590 push {r4, r7, lr} 8006072: b089 sub sp, #36 @ 0x24 8006074: af00 add r7, sp, #0 8006076: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8006078: 2300 movs r3, #0 800607a: 77fb strb r3, [r7, #31] uint32_t tmpCFGR; uint32_t tmp_adc_reg_is_conversion_on_going; __IO uint32_t wait_loop_index = 0UL; 800607c: 2300 movs r3, #0 800607e: 60bb str r3, [r7, #8] uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check ADC handle */ if (hadc == NULL) 8006080: 687b ldr r3, [r7, #4] 8006082: 2b00 cmp r3, #0 8006084: d101 bne.n 800608a { return HAL_ERROR; 8006086: 2301 movs r3, #1 8006088: e18f b.n 80063aa assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 800608a: 687b ldr r3, [r7, #4] 800608c: 68db ldr r3, [r3, #12] 800608e: 2b00 cmp r3, #0 /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8006090: 687b ldr r3, [r7, #4] 8006092: 6d5b ldr r3, [r3, #84] @ 0x54 8006094: 2b00 cmp r3, #0 8006096: d109 bne.n 80060ac /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8006098: 6878 ldr r0, [r7, #4] 800609a: f7fd fd7f bl 8003b9c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 800609e: 687b ldr r3, [r7, #4] 80060a0: 2200 movs r2, #0 80060a2: 659a str r2, [r3, #88] @ 0x58 /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; 80060a4: 687b ldr r3, [r7, #4] 80060a6: 2200 movs r2, #0 80060a8: f883 2050 strb.w r2, [r3, #80] @ 0x50 } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) 80060ac: 687b ldr r3, [r7, #4] 80060ae: 681b ldr r3, [r3, #0] 80060b0: 4618 mov r0, r3 80060b2: f7ff ff19 bl 8005ee8 80060b6: 4603 mov r3, r0 80060b8: 2b00 cmp r3, #0 80060ba: d004 beq.n 80060c6 { /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); 80060bc: 687b ldr r3, [r7, #4] 80060be: 681b ldr r3, [r3, #0] 80060c0: 4618 mov r0, r3 80060c2: f7ff feff bl 8005ec4 /* System was in deep power down mode, calibration must be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 80060c6: 687b ldr r3, [r7, #4] 80060c8: 681b ldr r3, [r3, #0] 80060ca: 4618 mov r0, r3 80060cc: f7ff ff34 bl 8005f38 80060d0: 4603 mov r3, r0 80060d2: 2b00 cmp r3, #0 80060d4: d114 bne.n 8006100 { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); 80060d6: 687b ldr r3, [r7, #4] 80060d8: 681b ldr r3, [r3, #0] 80060da: 4618 mov r0, r3 80060dc: f7ff ff18 bl 8005f10 /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 80060e0: 4b87 ldr r3, [pc, #540] @ (8006300 ) 80060e2: 681b ldr r3, [r3, #0] 80060e4: 099b lsrs r3, r3, #6 80060e6: 4a87 ldr r2, [pc, #540] @ (8006304 ) 80060e8: fba2 2303 umull r2, r3, r2, r3 80060ec: 099b lsrs r3, r3, #6 80060ee: 3301 adds r3, #1 80060f0: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 80060f2: e002 b.n 80060fa { wait_loop_index--; 80060f4: 68bb ldr r3, [r7, #8] 80060f6: 3b01 subs r3, #1 80060f8: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 80060fa: 68bb ldr r3, [r7, #8] 80060fc: 2b00 cmp r3, #0 80060fe: d1f9 bne.n 80060f4 } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 8006100: 687b ldr r3, [r7, #4] 8006102: 681b ldr r3, [r3, #0] 8006104: 4618 mov r0, r3 8006106: f7ff ff17 bl 8005f38 800610a: 4603 mov r3, r0 800610c: 2b00 cmp r3, #0 800610e: d10d bne.n 800612c { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006110: 687b ldr r3, [r7, #4] 8006112: 6d5b ldr r3, [r3, #84] @ 0x54 8006114: f043 0210 orr.w r2, r3, #16 8006118: 687b ldr r3, [r7, #4] 800611a: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800611c: 687b ldr r3, [r7, #4] 800611e: 6d9b ldr r3, [r3, #88] @ 0x58 8006120: f043 0201 orr.w r2, r3, #1 8006124: 687b ldr r3, [r7, #4] 8006126: 659a str r2, [r3, #88] @ 0x58 tmp_hal_status = HAL_ERROR; 8006128: 2301 movs r3, #1 800612a: 77fb strb r3, [r7, #31] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 800612c: 687b ldr r3, [r7, #4] 800612e: 681b ldr r3, [r3, #0] 8006130: 4618 mov r0, r3 8006132: f7ff ff77 bl 8006024 8006136: 6178 str r0, [r7, #20] if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 8006138: 687b ldr r3, [r7, #4] 800613a: 6d5b ldr r3, [r3, #84] @ 0x54 800613c: f003 0310 and.w r3, r3, #16 8006140: 2b00 cmp r3, #0 8006142: f040 8129 bne.w 8006398 && (tmp_adc_reg_is_conversion_on_going == 0UL) 8006146: 697b ldr r3, [r7, #20] 8006148: 2b00 cmp r3, #0 800614a: f040 8125 bne.w 8006398 ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800614e: 687b ldr r3, [r7, #4] 8006150: 6d5b ldr r3, [r3, #84] @ 0x54 8006152: f423 7381 bic.w r3, r3, #258 @ 0x102 8006156: f043 0202 orr.w r2, r3, #2 800615a: 687b ldr r3, [r7, #4] 800615c: 655a str r2, [r3, #84] @ 0x54 /* Configuration of common ADC parameters */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 800615e: 687b ldr r3, [r7, #4] 8006160: 681b ldr r3, [r3, #0] 8006162: 4618 mov r0, r3 8006164: f7ff ff24 bl 8005fb0 8006168: 4603 mov r3, r0 800616a: 2b00 cmp r3, #0 800616c: d136 bne.n 80061dc { if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 800616e: 687b ldr r3, [r7, #4] 8006170: 681b ldr r3, [r3, #0] 8006172: 4a65 ldr r2, [pc, #404] @ (8006308 ) 8006174: 4293 cmp r3, r2 8006176: d004 beq.n 8006182 8006178: 687b ldr r3, [r7, #4] 800617a: 681b ldr r3, [r3, #0] 800617c: 4a63 ldr r2, [pc, #396] @ (800630c ) 800617e: 4293 cmp r3, r2 8006180: d10e bne.n 80061a0 8006182: 4861 ldr r0, [pc, #388] @ (8006308 ) 8006184: f7ff ff14 bl 8005fb0 8006188: 4604 mov r4, r0 800618a: 4860 ldr r0, [pc, #384] @ (800630c ) 800618c: f7ff ff10 bl 8005fb0 8006190: 4603 mov r3, r0 8006192: 4323 orrs r3, r4 8006194: 2b00 cmp r3, #0 8006196: bf0c ite eq 8006198: 2301 moveq r3, #1 800619a: 2300 movne r3, #0 800619c: b2db uxtb r3, r3 800619e: e008 b.n 80061b2 80061a0: 485b ldr r0, [pc, #364] @ (8006310 ) 80061a2: f7ff ff05 bl 8005fb0 80061a6: 4603 mov r3, r0 80061a8: 2b00 cmp r3, #0 80061aa: bf0c ite eq 80061ac: 2301 moveq r3, #1 80061ae: 2300 movne r3, #0 80061b0: b2db uxtb r3, r3 80061b2: 2b00 cmp r3, #0 80061b4: d012 beq.n 80061dc /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ /* HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); 80061b6: 687b ldr r3, [r7, #4] 80061b8: 681b ldr r3, [r3, #0] 80061ba: 4a53 ldr r2, [pc, #332] @ (8006308 ) 80061bc: 4293 cmp r3, r2 80061be: d004 beq.n 80061ca 80061c0: 687b ldr r3, [r7, #4] 80061c2: 681b ldr r3, [r3, #0] 80061c4: 4a51 ldr r2, [pc, #324] @ (800630c ) 80061c6: 4293 cmp r3, r2 80061c8: d101 bne.n 80061ce 80061ca: 4a52 ldr r2, [pc, #328] @ (8006314 ) 80061cc: e000 b.n 80061d0 80061ce: 4a52 ldr r2, [pc, #328] @ (8006318 ) 80061d0: 687b ldr r3, [r7, #4] 80061d2: 685b ldr r3, [r3, #4] 80061d4: 4619 mov r1, r3 80061d6: 4610 mov r0, r2 80061d8: f7ff fd3c bl 8005c54 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); } #else if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution)) 80061dc: f7ff fcf4 bl 8005bc8 80061e0: 4603 mov r3, r0 80061e2: f241 0203 movw r2, #4099 @ 0x1003 80061e6: 4293 cmp r3, r2 80061e8: d914 bls.n 8006214 80061ea: 687b ldr r3, [r7, #4] 80061ec: 689b ldr r3, [r3, #8] 80061ee: 2b10 cmp r3, #16 80061f0: d110 bne.n 8006214 { /* for STM32H7 silicon rev.B and above , ADC_CFGR_RES value for 8bits resolution is : b111 */ tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 80061f2: 687b ldr r3, [r7, #4] 80061f4: 7d5b ldrb r3, [r3, #21] 80061f6: 035a lsls r2, r3, #13 hadc->Init.Overrun | 80061f8: 687b ldr r3, [r7, #4] 80061fa: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 80061fc: 431a orrs r2, r3 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 80061fe: 687b ldr r3, [r7, #4] 8006200: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 8006202: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8006204: 687b ldr r3, [r7, #4] 8006206: 7f1b ldrb r3, [r3, #28] 8006208: 041b lsls r3, r3, #16 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 800620a: 4313 orrs r3, r2 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 800620c: f043 030c orr.w r3, r3, #12 8006210: 61bb str r3, [r7, #24] 8006212: e00d b.n 8006230 } else { tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006214: 687b ldr r3, [r7, #4] 8006216: 7d5b ldrb r3, [r3, #21] 8006218: 035a lsls r2, r3, #13 hadc->Init.Overrun | 800621a: 687b ldr r3, [r7, #4] 800621c: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 800621e: 431a orrs r2, r3 hadc->Init.Resolution | 8006220: 687b ldr r3, [r7, #4] 8006222: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 8006224: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8006226: 687b ldr r3, [r7, #4] 8006228: 7f1b ldrb r3, [r3, #28] 800622a: 041b lsls r3, r3, #16 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 800622c: 4313 orrs r3, r2 800622e: 61bb str r3, [r7, #24] } #endif /* ADC_VER_V5_3 */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8006230: 687b ldr r3, [r7, #4] 8006232: 7f1b ldrb r3, [r3, #28] 8006234: 2b01 cmp r3, #1 8006236: d106 bne.n 8006246 { tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); 8006238: 687b ldr r3, [r7, #4] 800623a: 6a1b ldr r3, [r3, #32] 800623c: 3b01 subs r3, #1 800623e: 045b lsls r3, r3, #17 8006240: 69ba ldr r2, [r7, #24] 8006242: 4313 orrs r3, r2 8006244: 61bb str r3, [r7, #24] /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 8006246: 687b ldr r3, [r7, #4] 8006248: 6a5b ldr r3, [r3, #36] @ 0x24 800624a: 2b00 cmp r3, #0 800624c: d009 beq.n 8006262 { tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 800624e: 687b ldr r3, [r7, #4] 8006250: 6a5b ldr r3, [r3, #36] @ 0x24 8006252: f403 7278 and.w r2, r3, #992 @ 0x3e0 | hadc->Init.ExternalTrigConvEdge 8006256: 687b ldr r3, [r7, #4] 8006258: 6a9b ldr r3, [r3, #40] @ 0x28 800625a: 4313 orrs r3, r2 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 800625c: 69ba ldr r2, [r7, #24] 800625e: 4313 orrs r3, r2 8006260: 61bb str r3, [r7, #24] /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); } #else /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); 8006262: 687b ldr r3, [r7, #4] 8006264: 681b ldr r3, [r3, #0] 8006266: 68da ldr r2, [r3, #12] 8006268: 4b2c ldr r3, [pc, #176] @ (800631c ) 800626a: 4013 ands r3, r2 800626c: 687a ldr r2, [r7, #4] 800626e: 6812 ldr r2, [r2, #0] 8006270: 69b9 ldr r1, [r7, #24] 8006272: 430b orrs r3, r1 8006274: 60d3 str r3, [r2, #12] /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - Conversion data management Init.ConversionDataManagement */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8006276: 687b ldr r3, [r7, #4] 8006278: 681b ldr r3, [r3, #0] 800627a: 4618 mov r0, r3 800627c: f7ff fed2 bl 8006024 8006280: 6138 str r0, [r7, #16] tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 8006282: 687b ldr r3, [r7, #4] 8006284: 681b ldr r3, [r3, #0] 8006286: 4618 mov r0, r3 8006288: f7ff fedf bl 800604a 800628c: 60f8 str r0, [r7, #12] if ((tmp_adc_is_conversion_on_going_regular == 0UL) 800628e: 693b ldr r3, [r7, #16] 8006290: 2b00 cmp r3, #0 8006292: d15f bne.n 8006354 && (tmp_adc_is_conversion_on_going_injected == 0UL) 8006294: 68fb ldr r3, [r7, #12] 8006296: 2b00 cmp r3, #0 8006298: d15c bne.n 8006354 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); } #else tmpCFGR = ( ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 800629a: 687b ldr r3, [r7, #4] 800629c: 7d1b ldrb r3, [r3, #20] 800629e: 039a lsls r2, r3, #14 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); 80062a0: 687b ldr r3, [r7, #4] 80062a2: 6adb ldr r3, [r3, #44] @ 0x2c tmpCFGR = ( 80062a4: 4313 orrs r3, r2 80062a6: 61bb str r3, [r7, #24] #endif MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 80062a8: 687b ldr r3, [r7, #4] 80062aa: 681b ldr r3, [r3, #0] 80062ac: 68da ldr r2, [r3, #12] 80062ae: 4b1c ldr r3, [pc, #112] @ (8006320 ) 80062b0: 4013 ands r3, r2 80062b2: 687a ldr r2, [r7, #4] 80062b4: 6812 ldr r2, [r2, #0] 80062b6: 69b9 ldr r1, [r7, #24] 80062b8: 430b orrs r3, r1 80062ba: 60d3 str r3, [r2, #12] if (hadc->Init.OversamplingMode == ENABLE) 80062bc: 687b ldr r3, [r7, #4] 80062be: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 80062c2: 2b01 cmp r3, #1 80062c4: d130 bne.n 8006328 #endif assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START) 80062c6: 687b ldr r3, [r7, #4] 80062c8: 6a5b ldr r3, [r3, #36] @ 0x24 80062ca: 2b00 cmp r3, #0 /* - Oversampling Ratio */ /* - Right bit shift */ /* - Left bit shift */ /* - Triggered mode */ /* - Oversampling mode (continued/resumed) */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, 80062cc: 687b ldr r3, [r7, #4] 80062ce: 681b ldr r3, [r3, #0] 80062d0: 691a ldr r2, [r3, #16] 80062d2: 4b14 ldr r3, [pc, #80] @ (8006324 ) 80062d4: 4013 ands r3, r2 80062d6: 687a ldr r2, [r7, #4] 80062d8: 6bd2 ldr r2, [r2, #60] @ 0x3c 80062da: 3a01 subs r2, #1 80062dc: 0411 lsls r1, r2, #16 80062de: 687a ldr r2, [r7, #4] 80062e0: 6c12 ldr r2, [r2, #64] @ 0x40 80062e2: 4311 orrs r1, r2 80062e4: 687a ldr r2, [r7, #4] 80062e6: 6c52 ldr r2, [r2, #68] @ 0x44 80062e8: 4311 orrs r1, r2 80062ea: 687a ldr r2, [r7, #4] 80062ec: 6c92 ldr r2, [r2, #72] @ 0x48 80062ee: 430a orrs r2, r1 80062f0: 431a orrs r2, r3 80062f2: 687b ldr r3, [r7, #4] 80062f4: 681b ldr r3, [r3, #0] 80062f6: f042 0201 orr.w r2, r2, #1 80062fa: 611a str r2, [r3, #16] 80062fc: e01c b.n 8006338 80062fe: bf00 nop 8006300: 24000034 .word 0x24000034 8006304: 053e2d63 .word 0x053e2d63 8006308: 40022000 .word 0x40022000 800630c: 40022100 .word 0x40022100 8006310: 58026000 .word 0x58026000 8006314: 40022300 .word 0x40022300 8006318: 58026300 .word 0x58026300 800631c: fff0c003 .word 0xfff0c003 8006320: ffffbffc .word 0xffffbffc 8006324: fc00f81e .word 0xfc00f81e } else { /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); 8006328: 687b ldr r3, [r7, #4] 800632a: 681b ldr r3, [r3, #0] 800632c: 691a ldr r2, [r3, #16] 800632e: 687b ldr r3, [r7, #4] 8006330: 681b ldr r3, [r3, #0] 8006332: f022 0201 bic.w r2, r2, #1 8006336: 611a str r2, [r3, #16] } /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift); 8006338: 687b ldr r3, [r7, #4] 800633a: 681b ldr r3, [r3, #0] 800633c: 691b ldr r3, [r3, #16] 800633e: f023 4170 bic.w r1, r3, #4026531840 @ 0xf0000000 8006342: 687b ldr r3, [r7, #4] 8006344: 6b5a ldr r2, [r3, #52] @ 0x34 8006346: 687b ldr r3, [r7, #4] 8006348: 681b ldr r3, [r3, #0] 800634a: 430a orrs r2, r1 800634c: 611a str r2, [r3, #16] /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); } #else /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); 800634e: 6878 ldr r0, [r7, #4] 8006350: f000 fde2 bl 8006f18 /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 8006354: 687b ldr r3, [r7, #4] 8006356: 68db ldr r3, [r3, #12] 8006358: 2b01 cmp r3, #1 800635a: d10c bne.n 8006376 { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); 800635c: 687b ldr r3, [r7, #4] 800635e: 681b ldr r3, [r3, #0] 8006360: 6b1b ldr r3, [r3, #48] @ 0x30 8006362: f023 010f bic.w r1, r3, #15 8006366: 687b ldr r3, [r7, #4] 8006368: 699b ldr r3, [r3, #24] 800636a: 1e5a subs r2, r3, #1 800636c: 687b ldr r3, [r7, #4] 800636e: 681b ldr r3, [r3, #0] 8006370: 430a orrs r2, r1 8006372: 631a str r2, [r3, #48] @ 0x30 8006374: e007 b.n 8006386 } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 8006376: 687b ldr r3, [r7, #4] 8006378: 681b ldr r3, [r3, #0] 800637a: 6b1a ldr r2, [r3, #48] @ 0x30 800637c: 687b ldr r3, [r7, #4] 800637e: 681b ldr r3, [r3, #0] 8006380: f022 020f bic.w r2, r2, #15 8006384: 631a str r2, [r3, #48] @ 0x30 } /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); 8006386: 687b ldr r3, [r7, #4] 8006388: 6d5b ldr r3, [r3, #84] @ 0x54 800638a: f023 0303 bic.w r3, r3, #3 800638e: f043 0201 orr.w r2, r3, #1 8006392: 687b ldr r3, [r7, #4] 8006394: 655a str r2, [r3, #84] @ 0x54 8006396: e007 b.n 80063a8 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006398: 687b ldr r3, [r7, #4] 800639a: 6d5b ldr r3, [r3, #84] @ 0x54 800639c: f043 0210 orr.w r2, r3, #16 80063a0: 687b ldr r3, [r7, #4] 80063a2: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 80063a4: 2301 movs r3, #1 80063a6: 77fb strb r3, [r7, #31] } /* Return function status */ return tmp_hal_status; 80063a8: 7ffb ldrb r3, [r7, #31] } 80063aa: 4618 mov r0, r3 80063ac: 3724 adds r7, #36 @ 0x24 80063ae: 46bd mov sp, r7 80063b0: bd90 pop {r4, r7, pc} 80063b2: bf00 nop 080063b4 : * @param pData Destination Buffer address. * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { 80063b4: b580 push {r7, lr} 80063b6: b086 sub sp, #24 80063b8: af00 add r7, sp, #0 80063ba: 60f8 str r0, [r7, #12] 80063bc: 60b9 str r1, [r7, #8] 80063be: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 80063c0: 68fb ldr r3, [r7, #12] 80063c2: 681b ldr r3, [r3, #0] 80063c4: 4a55 ldr r2, [pc, #340] @ (800651c ) 80063c6: 4293 cmp r3, r2 80063c8: d004 beq.n 80063d4 80063ca: 68fb ldr r3, [r7, #12] 80063cc: 681b ldr r3, [r3, #0] 80063ce: 4a54 ldr r2, [pc, #336] @ (8006520 ) 80063d0: 4293 cmp r3, r2 80063d2: d101 bne.n 80063d8 80063d4: 4b53 ldr r3, [pc, #332] @ (8006524 ) 80063d6: e000 b.n 80063da 80063d8: 4b53 ldr r3, [pc, #332] @ (8006528 ) 80063da: 4618 mov r0, r3 80063dc: f7ff fd64 bl 8005ea8 80063e0: 6138 str r0, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 80063e2: 68fb ldr r3, [r7, #12] 80063e4: 681b ldr r3, [r3, #0] 80063e6: 4618 mov r0, r3 80063e8: f7ff fe1c bl 8006024 80063ec: 4603 mov r3, r0 80063ee: 2b00 cmp r3, #0 80063f0: f040 808c bne.w 800650c { /* Process locked */ __HAL_LOCK(hadc); 80063f4: 68fb ldr r3, [r7, #12] 80063f6: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 80063fa: 2b01 cmp r3, #1 80063fc: d101 bne.n 8006402 80063fe: 2302 movs r3, #2 8006400: e087 b.n 8006512 8006402: 68fb ldr r3, [r7, #12] 8006404: 2201 movs r2, #1 8006406: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Ensure that multimode regular conversions are not enabled. */ /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 800640a: 693b ldr r3, [r7, #16] 800640c: 2b00 cmp r3, #0 800640e: d005 beq.n 800641c || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) 8006410: 693b ldr r3, [r7, #16] 8006412: 2b05 cmp r3, #5 8006414: d002 beq.n 800641c || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) 8006416: 693b ldr r3, [r7, #16] 8006418: 2b09 cmp r3, #9 800641a: d170 bne.n 80064fe ) { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 800641c: 68f8 ldr r0, [r7, #12] 800641e: f000 fbfd bl 8006c1c 8006422: 4603 mov r3, r0 8006424: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8006426: 7dfb ldrb r3, [r7, #23] 8006428: 2b00 cmp r3, #0 800642a: d163 bne.n 80064f4 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 800642c: 68fb ldr r3, [r7, #12] 800642e: 6d5a ldr r2, [r3, #84] @ 0x54 8006430: 4b3e ldr r3, [pc, #248] @ (800652c ) 8006432: 4013 ands r3, r2 8006434: f443 7280 orr.w r2, r3, #256 @ 0x100 8006438: 68fb ldr r3, [r7, #12] 800643a: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_REG_BUSY); /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 800643c: 68fb ldr r3, [r7, #12] 800643e: 681b ldr r3, [r3, #0] 8006440: 4a37 ldr r2, [pc, #220] @ (8006520 ) 8006442: 4293 cmp r3, r2 8006444: d002 beq.n 800644c 8006446: 68fb ldr r3, [r7, #12] 8006448: 681b ldr r3, [r3, #0] 800644a: e000 b.n 800644e 800644c: 4b33 ldr r3, [pc, #204] @ (800651c ) 800644e: 68fa ldr r2, [r7, #12] 8006450: 6812 ldr r2, [r2, #0] 8006452: 4293 cmp r3, r2 8006454: d002 beq.n 800645c || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8006456: 693b ldr r3, [r7, #16] 8006458: 2b00 cmp r3, #0 800645a: d105 bne.n 8006468 ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800645c: 68fb ldr r3, [r7, #12] 800645e: 6d5b ldr r3, [r3, #84] @ 0x54 8006460: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 8006464: 68fb ldr r3, [r7, #12] 8006466: 655a str r2, [r3, #84] @ 0x54 } /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) 8006468: 68fb ldr r3, [r7, #12] 800646a: 6d5b ldr r3, [r3, #84] @ 0x54 800646c: f403 5380 and.w r3, r3, #4096 @ 0x1000 8006470: 2b00 cmp r3, #0 8006472: d006 beq.n 8006482 { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8006474: 68fb ldr r3, [r7, #12] 8006476: 6d9b ldr r3, [r3, #88] @ 0x58 8006478: f023 0206 bic.w r2, r3, #6 800647c: 68fb ldr r3, [r7, #12] 800647e: 659a str r2, [r3, #88] @ 0x58 8006480: e002 b.n 8006488 } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8006482: 68fb ldr r3, [r7, #12] 8006484: 2200 movs r2, #0 8006486: 659a str r2, [r3, #88] @ 0x58 } /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 8006488: 68fb ldr r3, [r7, #12] 800648a: 6cdb ldr r3, [r3, #76] @ 0x4c 800648c: 4a28 ldr r2, [pc, #160] @ (8006530 ) 800648e: 63da str r2, [r3, #60] @ 0x3c /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 8006490: 68fb ldr r3, [r7, #12] 8006492: 6cdb ldr r3, [r3, #76] @ 0x4c 8006494: 4a27 ldr r2, [pc, #156] @ (8006534 ) 8006496: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 8006498: 68fb ldr r3, [r7, #12] 800649a: 6cdb ldr r3, [r3, #76] @ 0x4c 800649c: 4a26 ldr r2, [pc, #152] @ (8006538 ) 800649e: 64da str r2, [r3, #76] @ 0x4c /* ADC start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 80064a0: 68fb ldr r3, [r7, #12] 80064a2: 681b ldr r3, [r3, #0] 80064a4: 221c movs r2, #28 80064a6: 601a str r2, [r3, #0] /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 80064a8: 68fb ldr r3, [r7, #12] 80064aa: 2200 movs r2, #0 80064ac: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* With DMA, overrun event is always considered as an error even if hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, ADC_IT_OVR is enabled. */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 80064b0: 68fb ldr r3, [r7, #12] 80064b2: 681b ldr r3, [r3, #0] 80064b4: 685a ldr r2, [r3, #4] 80064b6: 68fb ldr r3, [r7, #12] 80064b8: 681b ldr r3, [r3, #0] 80064ba: f042 0210 orr.w r2, r2, #16 80064be: 605a str r2, [r3, #4] { LL_ADC_REG_SetDataTransferMode(hadc->Instance, ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); } #else LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement); 80064c0: 68fb ldr r3, [r7, #12] 80064c2: 681a ldr r2, [r3, #0] 80064c4: 68fb ldr r3, [r7, #12] 80064c6: 6adb ldr r3, [r3, #44] @ 0x2c 80064c8: 4619 mov r1, r3 80064ca: 4610 mov r0, r2 80064cc: f7ff fc89 bl 8005de2 #endif /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 80064d0: 68fb ldr r3, [r7, #12] 80064d2: 6cd8 ldr r0, [r3, #76] @ 0x4c 80064d4: 68fb ldr r3, [r7, #12] 80064d6: 681b ldr r3, [r3, #0] 80064d8: 3340 adds r3, #64 @ 0x40 80064da: 4619 mov r1, r3 80064dc: 68ba ldr r2, [r7, #8] 80064de: 687b ldr r3, [r7, #4] 80064e0: f002 fa5e bl 80089a0 80064e4: 4603 mov r3, r0 80064e6: 75fb strb r3, [r7, #23] /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); 80064e8: 68fb ldr r3, [r7, #12] 80064ea: 681b ldr r3, [r3, #0] 80064ec: 4618 mov r0, r3 80064ee: f7ff fd85 bl 8005ffc if (tmp_hal_status == HAL_OK) 80064f2: e00d b.n 8006510 } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 80064f4: 68fb ldr r3, [r7, #12] 80064f6: 2200 movs r2, #0 80064f8: f883 2050 strb.w r2, [r3, #80] @ 0x50 if (tmp_hal_status == HAL_OK) 80064fc: e008 b.n 8006510 } } else { tmp_hal_status = HAL_ERROR; 80064fe: 2301 movs r3, #1 8006500: 75fb strb r3, [r7, #23] /* Process unlocked */ __HAL_UNLOCK(hadc); 8006502: 68fb ldr r3, [r7, #12] 8006504: 2200 movs r2, #0 8006506: f883 2050 strb.w r2, [r3, #80] @ 0x50 800650a: e001 b.n 8006510 } } else { tmp_hal_status = HAL_BUSY; 800650c: 2302 movs r3, #2 800650e: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 8006510: 7dfb ldrb r3, [r7, #23] } 8006512: 4618 mov r0, r3 8006514: 3718 adds r7, #24 8006516: 46bd mov sp, r7 8006518: bd80 pop {r7, pc} 800651a: bf00 nop 800651c: 40022000 .word 0x40022000 8006520: 40022100 .word 0x40022100 8006524: 40022300 .word 0x40022300 8006528: 58026300 .word 0x58026300 800652c: fffff0fe .word 0xfffff0fe 8006530: 08006def .word 0x08006def 8006534: 08006ec7 .word 0x08006ec7 8006538: 08006ee3 .word 0x08006ee3 0800653c : * @brief Conversion DMA half-transfer callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { 800653c: b480 push {r7} 800653e: b083 sub sp, #12 8006540: af00 add r7, sp, #0 8006542: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 8006544: bf00 nop 8006546: 370c adds r7, #12 8006548: 46bd mov sp, r7 800654a: f85d 7b04 ldr.w r7, [sp], #4 800654e: 4770 bx lr 08006550 : * (this function is also clearing overrun flag) * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 8006550: b480 push {r7} 8006552: b083 sub sp, #12 8006554: af00 add r7, sp, #0 8006556: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 8006558: bf00 nop 800655a: 370c adds r7, #12 800655c: 46bd mov sp, r7 800655e: f85d 7b04 ldr.w r7, [sp], #4 8006562: 4770 bx lr 08006564 : * @param hadc ADC handle * @param sConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { 8006564: b590 push {r4, r7, lr} 8006566: b0a1 sub sp, #132 @ 0x84 8006568: af00 add r7, sp, #0 800656a: 6078 str r0, [r7, #4] 800656c: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800656e: 2300 movs r3, #0 8006570: f887 307f strb.w r3, [r7, #127] @ 0x7f uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0; 8006574: 2300 movs r3, #0 8006576: 60bb str r3, [r7, #8] /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); /* Verification of channel number */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) 8006578: 683b ldr r3, [r7, #0] 800657a: 68db ldr r3, [r3, #12] 800657c: 4a65 ldr r2, [pc, #404] @ (8006714 ) 800657e: 4293 cmp r3, r2 } #endif } /* Process locked */ __HAL_LOCK(hadc); 8006580: 687b ldr r3, [r7, #4] 8006582: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8006586: 2b01 cmp r3, #1 8006588: d101 bne.n 800658e 800658a: 2302 movs r3, #2 800658c: e32e b.n 8006bec 800658e: 687b ldr r3, [r7, #4] 8006590: 2201 movs r2, #1 8006592: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8006596: 687b ldr r3, [r7, #4] 8006598: 681b ldr r3, [r3, #0] 800659a: 4618 mov r0, r3 800659c: f7ff fd42 bl 8006024 80065a0: 4603 mov r3, r0 80065a2: 2b00 cmp r3, #0 80065a4: f040 8313 bne.w 8006bce { if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))) 80065a8: 683b ldr r3, [r7, #0] 80065aa: 681b ldr r3, [r3, #0] 80065ac: 2b00 cmp r3, #0 80065ae: db2c blt.n 800660a /* ADC channels preselection */ hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); } #else /* ADC channels preselection */ hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); 80065b0: 683b ldr r3, [r7, #0] 80065b2: 681b ldr r3, [r3, #0] 80065b4: f3c3 0313 ubfx r3, r3, #0, #20 80065b8: 2b00 cmp r3, #0 80065ba: d108 bne.n 80065ce 80065bc: 683b ldr r3, [r7, #0] 80065be: 681b ldr r3, [r3, #0] 80065c0: 0e9b lsrs r3, r3, #26 80065c2: f003 031f and.w r3, r3, #31 80065c6: 2201 movs r2, #1 80065c8: fa02 f303 lsl.w r3, r2, r3 80065cc: e016 b.n 80065fc 80065ce: 683b ldr r3, [r7, #0] 80065d0: 681b ldr r3, [r3, #0] 80065d2: 667b str r3, [r7, #100] @ 0x64 uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80065d4: 6e7b ldr r3, [r7, #100] @ 0x64 80065d6: fa93 f3a3 rbit r3, r3 80065da: 663b str r3, [r7, #96] @ 0x60 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 80065dc: 6e3b ldr r3, [r7, #96] @ 0x60 80065de: 66bb str r3, [r7, #104] @ 0x68 optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 80065e0: 6ebb ldr r3, [r7, #104] @ 0x68 80065e2: 2b00 cmp r3, #0 80065e4: d101 bne.n 80065ea { return 32U; 80065e6: 2320 movs r3, #32 80065e8: e003 b.n 80065f2 } return __builtin_clz(value); 80065ea: 6ebb ldr r3, [r7, #104] @ 0x68 80065ec: fab3 f383 clz r3, r3 80065f0: b2db uxtb r3, r3 80065f2: f003 031f and.w r3, r3, #31 80065f6: 2201 movs r2, #1 80065f8: fa02 f303 lsl.w r3, r2, r3 80065fc: 687a ldr r2, [r7, #4] 80065fe: 6812 ldr r2, [r2, #0] 8006600: 69d1 ldr r1, [r2, #28] 8006602: 687a ldr r2, [r7, #4] 8006604: 6812 ldr r2, [r2, #0] 8006606: 430b orrs r3, r1 8006608: 61d3 str r3, [r2, #28] #endif /* ADC_VER_V5_V90 */ } /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); 800660a: 687b ldr r3, [r7, #4] 800660c: 6818 ldr r0, [r3, #0] 800660e: 683b ldr r3, [r7, #0] 8006610: 6859 ldr r1, [r3, #4] 8006612: 683b ldr r3, [r7, #0] 8006614: 681b ldr r3, [r3, #0] 8006616: 461a mov r2, r3 8006618: f7ff fbb7 bl 8005d8a /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 800661c: 687b ldr r3, [r7, #4] 800661e: 681b ldr r3, [r3, #0] 8006620: 4618 mov r0, r3 8006622: f7ff fcff bl 8006024 8006626: 67b8 str r0, [r7, #120] @ 0x78 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 8006628: 687b ldr r3, [r7, #4] 800662a: 681b ldr r3, [r3, #0] 800662c: 4618 mov r0, r3 800662e: f7ff fd0c bl 800604a 8006632: 6778 str r0, [r7, #116] @ 0x74 if ((tmp_adc_is_conversion_on_going_regular == 0UL) 8006634: 6fbb ldr r3, [r7, #120] @ 0x78 8006636: 2b00 cmp r3, #0 8006638: f040 80b8 bne.w 80067ac && (tmp_adc_is_conversion_on_going_injected == 0UL) 800663c: 6f7b ldr r3, [r7, #116] @ 0x74 800663e: 2b00 cmp r3, #0 8006640: f040 80b4 bne.w 80067ac ) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); 8006644: 687b ldr r3, [r7, #4] 8006646: 6818 ldr r0, [r3, #0] 8006648: 683b ldr r3, [r7, #0] 800664a: 6819 ldr r1, [r3, #0] 800664c: 683b ldr r3, [r7, #0] 800664e: 689b ldr r3, [r3, #8] 8006650: 461a mov r2, r3 8006652: f7ff fbd9 bl 8005e08 tmpOffsetShifted = ADC3_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); } else #endif /* ADC_VER_V5_V90 */ { tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); 8006656: 4b30 ldr r3, [pc, #192] @ (8006718 ) 8006658: 681b ldr r3, [r3, #0] 800665a: f003 4370 and.w r3, r3, #4026531840 @ 0xf0000000 800665e: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8006662: d10b bne.n 800667c 8006664: 683b ldr r3, [r7, #0] 8006666: 695a ldr r2, [r3, #20] 8006668: 687b ldr r3, [r7, #4] 800666a: 681b ldr r3, [r3, #0] 800666c: 68db ldr r3, [r3, #12] 800666e: 089b lsrs r3, r3, #2 8006670: f003 0307 and.w r3, r3, #7 8006674: 005b lsls r3, r3, #1 8006676: fa02 f303 lsl.w r3, r2, r3 800667a: e01d b.n 80066b8 800667c: 687b ldr r3, [r7, #4] 800667e: 681b ldr r3, [r3, #0] 8006680: 68db ldr r3, [r3, #12] 8006682: f003 0310 and.w r3, r3, #16 8006686: 2b00 cmp r3, #0 8006688: d10b bne.n 80066a2 800668a: 683b ldr r3, [r7, #0] 800668c: 695a ldr r2, [r3, #20] 800668e: 687b ldr r3, [r7, #4] 8006690: 681b ldr r3, [r3, #0] 8006692: 68db ldr r3, [r3, #12] 8006694: 089b lsrs r3, r3, #2 8006696: f003 0307 and.w r3, r3, #7 800669a: 005b lsls r3, r3, #1 800669c: fa02 f303 lsl.w r3, r2, r3 80066a0: e00a b.n 80066b8 80066a2: 683b ldr r3, [r7, #0] 80066a4: 695a ldr r2, [r3, #20] 80066a6: 687b ldr r3, [r7, #4] 80066a8: 681b ldr r3, [r3, #0] 80066aa: 68db ldr r3, [r3, #12] 80066ac: 089b lsrs r3, r3, #2 80066ae: f003 0304 and.w r3, r3, #4 80066b2: 005b lsls r3, r3, #1 80066b4: fa02 f303 lsl.w r3, r2, r3 80066b8: 673b str r3, [r7, #112] @ 0x70 } if (sConfig->OffsetNumber != ADC_OFFSET_NONE) 80066ba: 683b ldr r3, [r7, #0] 80066bc: 691b ldr r3, [r3, #16] 80066be: 2b04 cmp r3, #4 80066c0: d02c beq.n 800671c { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); 80066c2: 687b ldr r3, [r7, #4] 80066c4: 6818 ldr r0, [r3, #0] 80066c6: 683b ldr r3, [r7, #0] 80066c8: 6919 ldr r1, [r3, #16] 80066ca: 683b ldr r3, [r7, #0] 80066cc: 681a ldr r2, [r3, #0] 80066ce: 6f3b ldr r3, [r7, #112] @ 0x70 80066d0: f7ff faf4 bl 8005cbc else #endif /* ADC_VER_V5_V90 */ { assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation)); /* Set ADC selected offset signed saturation */ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); 80066d4: 687b ldr r3, [r7, #4] 80066d6: 6818 ldr r0, [r3, #0] 80066d8: 683b ldr r3, [r7, #0] 80066da: 6919 ldr r1, [r3, #16] 80066dc: 683b ldr r3, [r7, #0] 80066de: 7e5b ldrb r3, [r3, #25] 80066e0: 2b01 cmp r3, #1 80066e2: d102 bne.n 80066ea 80066e4: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 80066e8: e000 b.n 80066ec 80066ea: 2300 movs r3, #0 80066ec: 461a mov r2, r3 80066ee: f7ff fb1e bl 8005d2e assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift)); /* Set ADC selected offset right shift */ LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); 80066f2: 687b ldr r3, [r7, #4] 80066f4: 6818 ldr r0, [r3, #0] 80066f6: 683b ldr r3, [r7, #0] 80066f8: 6919 ldr r1, [r3, #16] 80066fa: 683b ldr r3, [r7, #0] 80066fc: 7e1b ldrb r3, [r3, #24] 80066fe: 2b01 cmp r3, #1 8006700: d102 bne.n 8006708 8006702: f44f 6300 mov.w r3, #2048 @ 0x800 8006706: e000 b.n 800670a 8006708: 2300 movs r3, #0 800670a: 461a mov r2, r3 800670c: f7ff faf6 bl 8005cfc 8006710: e04c b.n 80067ac 8006712: bf00 nop 8006714: 47ff0000 .word 0x47ff0000 8006718: 5c001000 .word 0x5c001000 } } else #endif /* ADC_VER_V5_V90 */ { if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 800671c: 687b ldr r3, [r7, #4] 800671e: 681b ldr r3, [r3, #0] 8006720: 6e1b ldr r3, [r3, #96] @ 0x60 8006722: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006726: 683b ldr r3, [r7, #0] 8006728: 681b ldr r3, [r3, #0] 800672a: 069b lsls r3, r3, #26 800672c: 429a cmp r2, r3 800672e: d107 bne.n 8006740 { CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE); 8006730: 687b ldr r3, [r7, #4] 8006732: 681b ldr r3, [r3, #0] 8006734: 6e1a ldr r2, [r3, #96] @ 0x60 8006736: 687b ldr r3, [r7, #4] 8006738: 681b ldr r3, [r3, #0] 800673a: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 800673e: 661a str r2, [r3, #96] @ 0x60 } if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8006740: 687b ldr r3, [r7, #4] 8006742: 681b ldr r3, [r3, #0] 8006744: 6e5b ldr r3, [r3, #100] @ 0x64 8006746: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 800674a: 683b ldr r3, [r7, #0] 800674c: 681b ldr r3, [r3, #0] 800674e: 069b lsls r3, r3, #26 8006750: 429a cmp r2, r3 8006752: d107 bne.n 8006764 { CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE); 8006754: 687b ldr r3, [r7, #4] 8006756: 681b ldr r3, [r3, #0] 8006758: 6e5a ldr r2, [r3, #100] @ 0x64 800675a: 687b ldr r3, [r7, #4] 800675c: 681b ldr r3, [r3, #0] 800675e: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8006762: 665a str r2, [r3, #100] @ 0x64 } if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8006764: 687b ldr r3, [r7, #4] 8006766: 681b ldr r3, [r3, #0] 8006768: 6e9b ldr r3, [r3, #104] @ 0x68 800676a: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 800676e: 683b ldr r3, [r7, #0] 8006770: 681b ldr r3, [r3, #0] 8006772: 069b lsls r3, r3, #26 8006774: 429a cmp r2, r3 8006776: d107 bne.n 8006788 { CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE); 8006778: 687b ldr r3, [r7, #4] 800677a: 681b ldr r3, [r3, #0] 800677c: 6e9a ldr r2, [r3, #104] @ 0x68 800677e: 687b ldr r3, [r7, #4] 8006780: 681b ldr r3, [r3, #0] 8006782: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8006786: 669a str r2, [r3, #104] @ 0x68 } if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8006788: 687b ldr r3, [r7, #4] 800678a: 681b ldr r3, [r3, #0] 800678c: 6edb ldr r3, [r3, #108] @ 0x6c 800678e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006792: 683b ldr r3, [r7, #0] 8006794: 681b ldr r3, [r3, #0] 8006796: 069b lsls r3, r3, #26 8006798: 429a cmp r2, r3 800679a: d107 bne.n 80067ac { CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE); 800679c: 687b ldr r3, [r7, #4] 800679e: 681b ldr r3, [r3, #0] 80067a0: 6eda ldr r2, [r3, #108] @ 0x6c 80067a2: 687b ldr r3, [r7, #4] 80067a4: 681b ldr r3, [r3, #0] 80067a6: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 80067aa: 66da str r2, [r3, #108] @ 0x6c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 80067ac: 687b ldr r3, [r7, #4] 80067ae: 681b ldr r3, [r3, #0] 80067b0: 4618 mov r0, r3 80067b2: f7ff fbfd bl 8005fb0 80067b6: 4603 mov r3, r0 80067b8: 2b00 cmp r3, #0 80067ba: f040 8211 bne.w 8006be0 { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); 80067be: 687b ldr r3, [r7, #4] 80067c0: 6818 ldr r0, [r3, #0] 80067c2: 683b ldr r3, [r7, #0] 80067c4: 6819 ldr r1, [r3, #0] 80067c6: 683b ldr r3, [r7, #0] 80067c8: 68db ldr r3, [r3, #12] 80067ca: 461a mov r2, r3 80067cc: f7ff fb48 bl 8005e60 /* Configuration of differential mode */ if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) 80067d0: 683b ldr r3, [r7, #0] 80067d2: 68db ldr r3, [r3, #12] 80067d4: 4aa1 ldr r2, [pc, #644] @ (8006a5c ) 80067d6: 4293 cmp r3, r2 80067d8: f040 812e bne.w 8006a38 { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ LL_ADC_SetChannelSamplingTime(hadc->Instance, 80067dc: 687b ldr r3, [r7, #4] 80067de: 6818 ldr r0, [r3, #0] (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 80067e0: 683b ldr r3, [r7, #0] 80067e2: 681b ldr r3, [r3, #0] 80067e4: f3c3 0313 ubfx r3, r3, #0, #20 80067e8: 2b00 cmp r3, #0 80067ea: d10b bne.n 8006804 80067ec: 683b ldr r3, [r7, #0] 80067ee: 681b ldr r3, [r3, #0] 80067f0: 0e9b lsrs r3, r3, #26 80067f2: 3301 adds r3, #1 80067f4: f003 031f and.w r3, r3, #31 80067f8: 2b09 cmp r3, #9 80067fa: bf94 ite ls 80067fc: 2301 movls r3, #1 80067fe: 2300 movhi r3, #0 8006800: b2db uxtb r3, r3 8006802: e019 b.n 8006838 8006804: 683b ldr r3, [r7, #0] 8006806: 681b ldr r3, [r3, #0] 8006808: 65bb str r3, [r7, #88] @ 0x58 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800680a: 6dbb ldr r3, [r7, #88] @ 0x58 800680c: fa93 f3a3 rbit r3, r3 8006810: 657b str r3, [r7, #84] @ 0x54 return result; 8006812: 6d7b ldr r3, [r7, #84] @ 0x54 8006814: 65fb str r3, [r7, #92] @ 0x5c if (value == 0U) 8006816: 6dfb ldr r3, [r7, #92] @ 0x5c 8006818: 2b00 cmp r3, #0 800681a: d101 bne.n 8006820 return 32U; 800681c: 2320 movs r3, #32 800681e: e003 b.n 8006828 return __builtin_clz(value); 8006820: 6dfb ldr r3, [r7, #92] @ 0x5c 8006822: fab3 f383 clz r3, r3 8006826: b2db uxtb r3, r3 8006828: 3301 adds r3, #1 800682a: f003 031f and.w r3, r3, #31 800682e: 2b09 cmp r3, #9 8006830: bf94 ite ls 8006832: 2301 movls r3, #1 8006834: 2300 movhi r3, #0 8006836: b2db uxtb r3, r3 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006838: 2b00 cmp r3, #0 800683a: d079 beq.n 8006930 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 800683c: 683b ldr r3, [r7, #0] 800683e: 681b ldr r3, [r3, #0] 8006840: f3c3 0313 ubfx r3, r3, #0, #20 8006844: 2b00 cmp r3, #0 8006846: d107 bne.n 8006858 8006848: 683b ldr r3, [r7, #0] 800684a: 681b ldr r3, [r3, #0] 800684c: 0e9b lsrs r3, r3, #26 800684e: 3301 adds r3, #1 8006850: 069b lsls r3, r3, #26 8006852: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006856: e015 b.n 8006884 8006858: 683b ldr r3, [r7, #0] 800685a: 681b ldr r3, [r3, #0] 800685c: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800685e: 6cfb ldr r3, [r7, #76] @ 0x4c 8006860: fa93 f3a3 rbit r3, r3 8006864: 64bb str r3, [r7, #72] @ 0x48 return result; 8006866: 6cbb ldr r3, [r7, #72] @ 0x48 8006868: 653b str r3, [r7, #80] @ 0x50 if (value == 0U) 800686a: 6d3b ldr r3, [r7, #80] @ 0x50 800686c: 2b00 cmp r3, #0 800686e: d101 bne.n 8006874 return 32U; 8006870: 2320 movs r3, #32 8006872: e003 b.n 800687c return __builtin_clz(value); 8006874: 6d3b ldr r3, [r7, #80] @ 0x50 8006876: fab3 f383 clz r3, r3 800687a: b2db uxtb r3, r3 800687c: 3301 adds r3, #1 800687e: 069b lsls r3, r3, #26 8006880: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006884: 683b ldr r3, [r7, #0] 8006886: 681b ldr r3, [r3, #0] 8006888: f3c3 0313 ubfx r3, r3, #0, #20 800688c: 2b00 cmp r3, #0 800688e: d109 bne.n 80068a4 8006890: 683b ldr r3, [r7, #0] 8006892: 681b ldr r3, [r3, #0] 8006894: 0e9b lsrs r3, r3, #26 8006896: 3301 adds r3, #1 8006898: f003 031f and.w r3, r3, #31 800689c: 2101 movs r1, #1 800689e: fa01 f303 lsl.w r3, r1, r3 80068a2: e017 b.n 80068d4 80068a4: 683b ldr r3, [r7, #0] 80068a6: 681b ldr r3, [r3, #0] 80068a8: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80068aa: 6c3b ldr r3, [r7, #64] @ 0x40 80068ac: fa93 f3a3 rbit r3, r3 80068b0: 63fb str r3, [r7, #60] @ 0x3c return result; 80068b2: 6bfb ldr r3, [r7, #60] @ 0x3c 80068b4: 647b str r3, [r7, #68] @ 0x44 if (value == 0U) 80068b6: 6c7b ldr r3, [r7, #68] @ 0x44 80068b8: 2b00 cmp r3, #0 80068ba: d101 bne.n 80068c0 return 32U; 80068bc: 2320 movs r3, #32 80068be: e003 b.n 80068c8 return __builtin_clz(value); 80068c0: 6c7b ldr r3, [r7, #68] @ 0x44 80068c2: fab3 f383 clz r3, r3 80068c6: b2db uxtb r3, r3 80068c8: 3301 adds r3, #1 80068ca: f003 031f and.w r3, r3, #31 80068ce: 2101 movs r1, #1 80068d0: fa01 f303 lsl.w r3, r1, r3 80068d4: ea42 0103 orr.w r1, r2, r3 80068d8: 683b ldr r3, [r7, #0] 80068da: 681b ldr r3, [r3, #0] 80068dc: f3c3 0313 ubfx r3, r3, #0, #20 80068e0: 2b00 cmp r3, #0 80068e2: d10a bne.n 80068fa 80068e4: 683b ldr r3, [r7, #0] 80068e6: 681b ldr r3, [r3, #0] 80068e8: 0e9b lsrs r3, r3, #26 80068ea: 3301 adds r3, #1 80068ec: f003 021f and.w r2, r3, #31 80068f0: 4613 mov r3, r2 80068f2: 005b lsls r3, r3, #1 80068f4: 4413 add r3, r2 80068f6: 051b lsls r3, r3, #20 80068f8: e018 b.n 800692c 80068fa: 683b ldr r3, [r7, #0] 80068fc: 681b ldr r3, [r3, #0] 80068fe: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006900: 6b7b ldr r3, [r7, #52] @ 0x34 8006902: fa93 f3a3 rbit r3, r3 8006906: 633b str r3, [r7, #48] @ 0x30 return result; 8006908: 6b3b ldr r3, [r7, #48] @ 0x30 800690a: 63bb str r3, [r7, #56] @ 0x38 if (value == 0U) 800690c: 6bbb ldr r3, [r7, #56] @ 0x38 800690e: 2b00 cmp r3, #0 8006910: d101 bne.n 8006916 return 32U; 8006912: 2320 movs r3, #32 8006914: e003 b.n 800691e return __builtin_clz(value); 8006916: 6bbb ldr r3, [r7, #56] @ 0x38 8006918: fab3 f383 clz r3, r3 800691c: b2db uxtb r3, r3 800691e: 3301 adds r3, #1 8006920: f003 021f and.w r2, r3, #31 8006924: 4613 mov r3, r2 8006926: 005b lsls r3, r3, #1 8006928: 4413 add r3, r2 800692a: 051b lsls r3, r3, #20 LL_ADC_SetChannelSamplingTime(hadc->Instance, 800692c: 430b orrs r3, r1 800692e: e07e b.n 8006a2e (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8006930: 683b ldr r3, [r7, #0] 8006932: 681b ldr r3, [r3, #0] 8006934: f3c3 0313 ubfx r3, r3, #0, #20 8006938: 2b00 cmp r3, #0 800693a: d107 bne.n 800694c 800693c: 683b ldr r3, [r7, #0] 800693e: 681b ldr r3, [r3, #0] 8006940: 0e9b lsrs r3, r3, #26 8006942: 3301 adds r3, #1 8006944: 069b lsls r3, r3, #26 8006946: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 800694a: e015 b.n 8006978 800694c: 683b ldr r3, [r7, #0] 800694e: 681b ldr r3, [r3, #0] 8006950: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006952: 6abb ldr r3, [r7, #40] @ 0x28 8006954: fa93 f3a3 rbit r3, r3 8006958: 627b str r3, [r7, #36] @ 0x24 return result; 800695a: 6a7b ldr r3, [r7, #36] @ 0x24 800695c: 62fb str r3, [r7, #44] @ 0x2c if (value == 0U) 800695e: 6afb ldr r3, [r7, #44] @ 0x2c 8006960: 2b00 cmp r3, #0 8006962: d101 bne.n 8006968 return 32U; 8006964: 2320 movs r3, #32 8006966: e003 b.n 8006970 return __builtin_clz(value); 8006968: 6afb ldr r3, [r7, #44] @ 0x2c 800696a: fab3 f383 clz r3, r3 800696e: b2db uxtb r3, r3 8006970: 3301 adds r3, #1 8006972: 069b lsls r3, r3, #26 8006974: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006978: 683b ldr r3, [r7, #0] 800697a: 681b ldr r3, [r3, #0] 800697c: f3c3 0313 ubfx r3, r3, #0, #20 8006980: 2b00 cmp r3, #0 8006982: d109 bne.n 8006998 8006984: 683b ldr r3, [r7, #0] 8006986: 681b ldr r3, [r3, #0] 8006988: 0e9b lsrs r3, r3, #26 800698a: 3301 adds r3, #1 800698c: f003 031f and.w r3, r3, #31 8006990: 2101 movs r1, #1 8006992: fa01 f303 lsl.w r3, r1, r3 8006996: e017 b.n 80069c8 8006998: 683b ldr r3, [r7, #0] 800699a: 681b ldr r3, [r3, #0] 800699c: 61fb str r3, [r7, #28] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800699e: 69fb ldr r3, [r7, #28] 80069a0: fa93 f3a3 rbit r3, r3 80069a4: 61bb str r3, [r7, #24] return result; 80069a6: 69bb ldr r3, [r7, #24] 80069a8: 623b str r3, [r7, #32] if (value == 0U) 80069aa: 6a3b ldr r3, [r7, #32] 80069ac: 2b00 cmp r3, #0 80069ae: d101 bne.n 80069b4 return 32U; 80069b0: 2320 movs r3, #32 80069b2: e003 b.n 80069bc return __builtin_clz(value); 80069b4: 6a3b ldr r3, [r7, #32] 80069b6: fab3 f383 clz r3, r3 80069ba: b2db uxtb r3, r3 80069bc: 3301 adds r3, #1 80069be: f003 031f and.w r3, r3, #31 80069c2: 2101 movs r1, #1 80069c4: fa01 f303 lsl.w r3, r1, r3 80069c8: ea42 0103 orr.w r1, r2, r3 80069cc: 683b ldr r3, [r7, #0] 80069ce: 681b ldr r3, [r3, #0] 80069d0: f3c3 0313 ubfx r3, r3, #0, #20 80069d4: 2b00 cmp r3, #0 80069d6: d10d bne.n 80069f4 80069d8: 683b ldr r3, [r7, #0] 80069da: 681b ldr r3, [r3, #0] 80069dc: 0e9b lsrs r3, r3, #26 80069de: 3301 adds r3, #1 80069e0: f003 021f and.w r2, r3, #31 80069e4: 4613 mov r3, r2 80069e6: 005b lsls r3, r3, #1 80069e8: 4413 add r3, r2 80069ea: 3b1e subs r3, #30 80069ec: 051b lsls r3, r3, #20 80069ee: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 80069f2: e01b b.n 8006a2c 80069f4: 683b ldr r3, [r7, #0] 80069f6: 681b ldr r3, [r3, #0] 80069f8: 613b str r3, [r7, #16] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80069fa: 693b ldr r3, [r7, #16] 80069fc: fa93 f3a3 rbit r3, r3 8006a00: 60fb str r3, [r7, #12] return result; 8006a02: 68fb ldr r3, [r7, #12] 8006a04: 617b str r3, [r7, #20] if (value == 0U) 8006a06: 697b ldr r3, [r7, #20] 8006a08: 2b00 cmp r3, #0 8006a0a: d101 bne.n 8006a10 return 32U; 8006a0c: 2320 movs r3, #32 8006a0e: e003 b.n 8006a18 return __builtin_clz(value); 8006a10: 697b ldr r3, [r7, #20] 8006a12: fab3 f383 clz r3, r3 8006a16: b2db uxtb r3, r3 8006a18: 3301 adds r3, #1 8006a1a: f003 021f and.w r2, r3, #31 8006a1e: 4613 mov r3, r2 8006a20: 005b lsls r3, r3, #1 8006a22: 4413 add r3, r2 8006a24: 3b1e subs r3, #30 8006a26: 051b lsls r3, r3, #20 8006a28: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006a2c: 430b orrs r3, r1 8006a2e: 683a ldr r2, [r7, #0] 8006a30: 6892 ldr r2, [r2, #8] 8006a32: 4619 mov r1, r3 8006a34: f7ff f9e8 bl 8005e08 /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 8006a38: 683b ldr r3, [r7, #0] 8006a3a: 681b ldr r3, [r3, #0] 8006a3c: 2b00 cmp r3, #0 8006a3e: f280 80cf bge.w 8006be0 { /* Configuration of common ADC parameters */ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8006a42: 687b ldr r3, [r7, #4] 8006a44: 681b ldr r3, [r3, #0] 8006a46: 4a06 ldr r2, [pc, #24] @ (8006a60 ) 8006a48: 4293 cmp r3, r2 8006a4a: d004 beq.n 8006a56 8006a4c: 687b ldr r3, [r7, #4] 8006a4e: 681b ldr r3, [r3, #0] 8006a50: 4a04 ldr r2, [pc, #16] @ (8006a64 ) 8006a52: 4293 cmp r3, r2 8006a54: d10a bne.n 8006a6c 8006a56: 4b04 ldr r3, [pc, #16] @ (8006a68 ) 8006a58: e009 b.n 8006a6e 8006a5a: bf00 nop 8006a5c: 47ff0000 .word 0x47ff0000 8006a60: 40022000 .word 0x40022000 8006a64: 40022100 .word 0x40022100 8006a68: 40022300 .word 0x40022300 8006a6c: 4b61 ldr r3, [pc, #388] @ (8006bf4 ) 8006a6e: 4618 mov r0, r3 8006a70: f7ff f916 bl 8005ca0 8006a74: 66f8 str r0, [r7, #108] @ 0x6c /* Software is allowed to change common parameters only when all ADCs */ /* of the common group are disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8006a76: 687b ldr r3, [r7, #4] 8006a78: 681b ldr r3, [r3, #0] 8006a7a: 4a5f ldr r2, [pc, #380] @ (8006bf8 ) 8006a7c: 4293 cmp r3, r2 8006a7e: d004 beq.n 8006a8a 8006a80: 687b ldr r3, [r7, #4] 8006a82: 681b ldr r3, [r3, #0] 8006a84: 4a5d ldr r2, [pc, #372] @ (8006bfc ) 8006a86: 4293 cmp r3, r2 8006a88: d10e bne.n 8006aa8 8006a8a: 485b ldr r0, [pc, #364] @ (8006bf8 ) 8006a8c: f7ff fa90 bl 8005fb0 8006a90: 4604 mov r4, r0 8006a92: 485a ldr r0, [pc, #360] @ (8006bfc ) 8006a94: f7ff fa8c bl 8005fb0 8006a98: 4603 mov r3, r0 8006a9a: 4323 orrs r3, r4 8006a9c: 2b00 cmp r3, #0 8006a9e: bf0c ite eq 8006aa0: 2301 moveq r3, #1 8006aa2: 2300 movne r3, #0 8006aa4: b2db uxtb r3, r3 8006aa6: e008 b.n 8006aba 8006aa8: 4855 ldr r0, [pc, #340] @ (8006c00 ) 8006aaa: f7ff fa81 bl 8005fb0 8006aae: 4603 mov r3, r0 8006ab0: 2b00 cmp r3, #0 8006ab2: bf0c ite eq 8006ab4: 2301 moveq r3, #1 8006ab6: 2300 movne r3, #0 8006ab8: b2db uxtb r3, r3 8006aba: 2b00 cmp r3, #0 8006abc: d07d beq.n 8006bba { /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 8006abe: 683b ldr r3, [r7, #0] 8006ac0: 681b ldr r3, [r3, #0] 8006ac2: 4a50 ldr r2, [pc, #320] @ (8006c04 ) 8006ac4: 4293 cmp r3, r2 8006ac6: d130 bne.n 8006b2a 8006ac8: 6efb ldr r3, [r7, #108] @ 0x6c 8006aca: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8006ace: 2b00 cmp r3, #0 8006ad0: d12b bne.n 8006b2a { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8006ad2: 687b ldr r3, [r7, #4] 8006ad4: 681b ldr r3, [r3, #0] 8006ad6: 4a4a ldr r2, [pc, #296] @ (8006c00 ) 8006ad8: 4293 cmp r3, r2 8006ada: f040 8081 bne.w 8006be0 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); 8006ade: 687b ldr r3, [r7, #4] 8006ae0: 681b ldr r3, [r3, #0] 8006ae2: 4a45 ldr r2, [pc, #276] @ (8006bf8 ) 8006ae4: 4293 cmp r3, r2 8006ae6: d004 beq.n 8006af2 8006ae8: 687b ldr r3, [r7, #4] 8006aea: 681b ldr r3, [r3, #0] 8006aec: 4a43 ldr r2, [pc, #268] @ (8006bfc ) 8006aee: 4293 cmp r3, r2 8006af0: d101 bne.n 8006af6 8006af2: 4a45 ldr r2, [pc, #276] @ (8006c08 ) 8006af4: e000 b.n 8006af8 8006af6: 4a3f ldr r2, [pc, #252] @ (8006bf4 ) 8006af8: 6efb ldr r3, [r7, #108] @ 0x6c 8006afa: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 8006afe: 4619 mov r1, r3 8006b00: 4610 mov r0, r2 8006b02: f7ff f8ba bl 8005c7a /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8006b06: 4b41 ldr r3, [pc, #260] @ (8006c0c ) 8006b08: 681b ldr r3, [r3, #0] 8006b0a: 099b lsrs r3, r3, #6 8006b0c: 4a40 ldr r2, [pc, #256] @ (8006c10 ) 8006b0e: fba2 2303 umull r2, r3, r2, r3 8006b12: 099b lsrs r3, r3, #6 8006b14: 3301 adds r3, #1 8006b16: 005b lsls r3, r3, #1 8006b18: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8006b1a: e002 b.n 8006b22 { wait_loop_index--; 8006b1c: 68bb ldr r3, [r7, #8] 8006b1e: 3b01 subs r3, #1 8006b20: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8006b22: 68bb ldr r3, [r7, #8] 8006b24: 2b00 cmp r3, #0 8006b26: d1f9 bne.n 8006b1c if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8006b28: e05a b.n 8006be0 } } } else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 8006b2a: 683b ldr r3, [r7, #0] 8006b2c: 681b ldr r3, [r3, #0] 8006b2e: 4a39 ldr r2, [pc, #228] @ (8006c14 ) 8006b30: 4293 cmp r3, r2 8006b32: d11e bne.n 8006b72 8006b34: 6efb ldr r3, [r7, #108] @ 0x6c 8006b36: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8006b3a: 2b00 cmp r3, #0 8006b3c: d119 bne.n 8006b72 { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 8006b3e: 687b ldr r3, [r7, #4] 8006b40: 681b ldr r3, [r3, #0] 8006b42: 4a2f ldr r2, [pc, #188] @ (8006c00 ) 8006b44: 4293 cmp r3, r2 8006b46: d14b bne.n 8006be0 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); 8006b48: 687b ldr r3, [r7, #4] 8006b4a: 681b ldr r3, [r3, #0] 8006b4c: 4a2a ldr r2, [pc, #168] @ (8006bf8 ) 8006b4e: 4293 cmp r3, r2 8006b50: d004 beq.n 8006b5c 8006b52: 687b ldr r3, [r7, #4] 8006b54: 681b ldr r3, [r3, #0] 8006b56: 4a29 ldr r2, [pc, #164] @ (8006bfc ) 8006b58: 4293 cmp r3, r2 8006b5a: d101 bne.n 8006b60 8006b5c: 4a2a ldr r2, [pc, #168] @ (8006c08 ) 8006b5e: e000 b.n 8006b62 8006b60: 4a24 ldr r2, [pc, #144] @ (8006bf4 ) 8006b62: 6efb ldr r3, [r7, #108] @ 0x6c 8006b64: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8006b68: 4619 mov r1, r3 8006b6a: 4610 mov r0, r2 8006b6c: f7ff f885 bl 8005c7a if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 8006b70: e036 b.n 8006be0 } } else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) 8006b72: 683b ldr r3, [r7, #0] 8006b74: 681b ldr r3, [r3, #0] 8006b76: 4a28 ldr r2, [pc, #160] @ (8006c18 ) 8006b78: 4293 cmp r3, r2 8006b7a: d131 bne.n 8006be0 8006b7c: 6efb ldr r3, [r7, #108] @ 0x6c 8006b7e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8006b82: 2b00 cmp r3, #0 8006b84: d12c bne.n 8006be0 { if (ADC_VREFINT_INSTANCE(hadc)) 8006b86: 687b ldr r3, [r7, #4] 8006b88: 681b ldr r3, [r3, #0] 8006b8a: 4a1d ldr r2, [pc, #116] @ (8006c00 ) 8006b8c: 4293 cmp r3, r2 8006b8e: d127 bne.n 8006be0 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); 8006b90: 687b ldr r3, [r7, #4] 8006b92: 681b ldr r3, [r3, #0] 8006b94: 4a18 ldr r2, [pc, #96] @ (8006bf8 ) 8006b96: 4293 cmp r3, r2 8006b98: d004 beq.n 8006ba4 8006b9a: 687b ldr r3, [r7, #4] 8006b9c: 681b ldr r3, [r3, #0] 8006b9e: 4a17 ldr r2, [pc, #92] @ (8006bfc ) 8006ba0: 4293 cmp r3, r2 8006ba2: d101 bne.n 8006ba8 8006ba4: 4a18 ldr r2, [pc, #96] @ (8006c08 ) 8006ba6: e000 b.n 8006baa 8006ba8: 4a12 ldr r2, [pc, #72] @ (8006bf4 ) 8006baa: 6efb ldr r3, [r7, #108] @ 0x6c 8006bac: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8006bb0: 4619 mov r1, r3 8006bb2: 4610 mov r0, r2 8006bb4: f7ff f861 bl 8005c7a 8006bb8: e012 b.n 8006be0 /* enabled and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8006bba: 687b ldr r3, [r7, #4] 8006bbc: 6d5b ldr r3, [r3, #84] @ 0x54 8006bbe: f043 0220 orr.w r2, r3, #32 8006bc2: 687b ldr r3, [r7, #4] 8006bc4: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8006bc6: 2301 movs r3, #1 8006bc8: f887 307f strb.w r3, [r7, #127] @ 0x7f 8006bcc: e008 b.n 8006be0 /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8006bce: 687b ldr r3, [r7, #4] 8006bd0: 6d5b ldr r3, [r3, #84] @ 0x54 8006bd2: f043 0220 orr.w r2, r3, #32 8006bd6: 687b ldr r3, [r7, #4] 8006bd8: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8006bda: 2301 movs r3, #1 8006bdc: f887 307f strb.w r3, [r7, #127] @ 0x7f } /* Process unlocked */ __HAL_UNLOCK(hadc); 8006be0: 687b ldr r3, [r7, #4] 8006be2: 2200 movs r2, #0 8006be4: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 8006be8: f897 307f ldrb.w r3, [r7, #127] @ 0x7f } 8006bec: 4618 mov r0, r3 8006bee: 3784 adds r7, #132 @ 0x84 8006bf0: 46bd mov sp, r7 8006bf2: bd90 pop {r4, r7, pc} 8006bf4: 58026300 .word 0x58026300 8006bf8: 40022000 .word 0x40022000 8006bfc: 40022100 .word 0x40022100 8006c00: 58026000 .word 0x58026000 8006c04: cb840000 .word 0xcb840000 8006c08: 40022300 .word 0x40022300 8006c0c: 24000034 .word 0x24000034 8006c10: 053e2d63 .word 0x053e2d63 8006c14: c7520000 .word 0xc7520000 8006c18: cfb80000 .word 0xcfb80000 08006c1c : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { 8006c1c: b580 push {r7, lr} 8006c1e: b084 sub sp, #16 8006c20: af00 add r7, sp, #0 8006c22: 6078 str r0, [r7, #4] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8006c24: 687b ldr r3, [r7, #4] 8006c26: 681b ldr r3, [r3, #0] 8006c28: 4618 mov r0, r3 8006c2a: f7ff f9c1 bl 8005fb0 8006c2e: 4603 mov r3, r0 8006c30: 2b00 cmp r3, #0 8006c32: d16e bne.n 8006d12 { /* Check if conditions to enable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) 8006c34: 687b ldr r3, [r7, #4] 8006c36: 681b ldr r3, [r3, #0] 8006c38: 689a ldr r2, [r3, #8] 8006c3a: 4b38 ldr r3, [pc, #224] @ (8006d1c ) 8006c3c: 4013 ands r3, r2 8006c3e: 2b00 cmp r3, #0 8006c40: d00d beq.n 8006c5e { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006c42: 687b ldr r3, [r7, #4] 8006c44: 6d5b ldr r3, [r3, #84] @ 0x54 8006c46: f043 0210 orr.w r2, r3, #16 8006c4a: 687b ldr r3, [r7, #4] 8006c4c: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006c4e: 687b ldr r3, [r7, #4] 8006c50: 6d9b ldr r3, [r3, #88] @ 0x58 8006c52: f043 0201 orr.w r2, r3, #1 8006c56: 687b ldr r3, [r7, #4] 8006c58: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006c5a: 2301 movs r3, #1 8006c5c: e05a b.n 8006d14 } /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); 8006c5e: 687b ldr r3, [r7, #4] 8006c60: 681b ldr r3, [r3, #0] 8006c62: 4618 mov r0, r3 8006c64: f7ff f97c bl 8005f60 /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); 8006c68: f7fe ffa2 bl 8005bb0 8006c6c: 60f8 str r0, [r7, #12] /* Poll for ADC ready flag raised except case of multimode enabled and ADC slave selected. */ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8006c6e: 687b ldr r3, [r7, #4] 8006c70: 681b ldr r3, [r3, #0] 8006c72: 4a2b ldr r2, [pc, #172] @ (8006d20 ) 8006c74: 4293 cmp r3, r2 8006c76: d004 beq.n 8006c82 8006c78: 687b ldr r3, [r7, #4] 8006c7a: 681b ldr r3, [r3, #0] 8006c7c: 4a29 ldr r2, [pc, #164] @ (8006d24 ) 8006c7e: 4293 cmp r3, r2 8006c80: d101 bne.n 8006c86 8006c82: 4b29 ldr r3, [pc, #164] @ (8006d28 ) 8006c84: e000 b.n 8006c88 8006c86: 4b29 ldr r3, [pc, #164] @ (8006d2c ) 8006c88: 4618 mov r0, r3 8006c8a: f7ff f90d bl 8005ea8 8006c8e: 60b8 str r0, [r7, #8] if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8006c90: 687b ldr r3, [r7, #4] 8006c92: 681b ldr r3, [r3, #0] 8006c94: 4a23 ldr r2, [pc, #140] @ (8006d24 ) 8006c96: 4293 cmp r3, r2 8006c98: d002 beq.n 8006ca0 8006c9a: 687b ldr r3, [r7, #4] 8006c9c: 681b ldr r3, [r3, #0] 8006c9e: e000 b.n 8006ca2 8006ca0: 4b1f ldr r3, [pc, #124] @ (8006d20 ) 8006ca2: 687a ldr r2, [r7, #4] 8006ca4: 6812 ldr r2, [r2, #0] 8006ca6: 4293 cmp r3, r2 8006ca8: d02c beq.n 8006d04 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8006caa: 68bb ldr r3, [r7, #8] 8006cac: 2b00 cmp r3, #0 8006cae: d130 bne.n 8006d12 ) { while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8006cb0: e028 b.n 8006d04 The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ /* Note: Test of ADC enabled required due to hardware constraint to */ /* not enable ADC if already enabled. */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8006cb2: 687b ldr r3, [r7, #4] 8006cb4: 681b ldr r3, [r3, #0] 8006cb6: 4618 mov r0, r3 8006cb8: f7ff f97a bl 8005fb0 8006cbc: 4603 mov r3, r0 8006cbe: 2b00 cmp r3, #0 8006cc0: d104 bne.n 8006ccc { LL_ADC_Enable(hadc->Instance); 8006cc2: 687b ldr r3, [r7, #4] 8006cc4: 681b ldr r3, [r3, #0] 8006cc6: 4618 mov r0, r3 8006cc8: f7ff f94a bl 8005f60 } if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8006ccc: f7fe ff70 bl 8005bb0 8006cd0: 4602 mov r2, r0 8006cd2: 68fb ldr r3, [r7, #12] 8006cd4: 1ad3 subs r3, r2, r3 8006cd6: 2b02 cmp r3, #2 8006cd8: d914 bls.n 8006d04 { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8006cda: 687b ldr r3, [r7, #4] 8006cdc: 681b ldr r3, [r3, #0] 8006cde: 681b ldr r3, [r3, #0] 8006ce0: f003 0301 and.w r3, r3, #1 8006ce4: 2b01 cmp r3, #1 8006ce6: d00d beq.n 8006d04 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006ce8: 687b ldr r3, [r7, #4] 8006cea: 6d5b ldr r3, [r3, #84] @ 0x54 8006cec: f043 0210 orr.w r2, r3, #16 8006cf0: 687b ldr r3, [r7, #4] 8006cf2: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006cf4: 687b ldr r3, [r7, #4] 8006cf6: 6d9b ldr r3, [r3, #88] @ 0x58 8006cf8: f043 0201 orr.w r2, r3, #1 8006cfc: 687b ldr r3, [r7, #4] 8006cfe: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006d00: 2301 movs r3, #1 8006d02: e007 b.n 8006d14 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8006d04: 687b ldr r3, [r7, #4] 8006d06: 681b ldr r3, [r3, #0] 8006d08: 681b ldr r3, [r3, #0] 8006d0a: f003 0301 and.w r3, r3, #1 8006d0e: 2b01 cmp r3, #1 8006d10: d1cf bne.n 8006cb2 } } } /* Return HAL status */ return HAL_OK; 8006d12: 2300 movs r3, #0 } 8006d14: 4618 mov r0, r3 8006d16: 3710 adds r7, #16 8006d18: 46bd mov sp, r7 8006d1a: bd80 pop {r7, pc} 8006d1c: 8000003f .word 0x8000003f 8006d20: 40022000 .word 0x40022000 8006d24: 40022100 .word 0x40022100 8006d28: 40022300 .word 0x40022300 8006d2c: 58026300 .word 0x58026300 08006d30 : * stopped. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { 8006d30: b580 push {r7, lr} 8006d32: b084 sub sp, #16 8006d34: af00 add r7, sp, #0 8006d36: 6078 str r0, [r7, #4] uint32_t tickstart; const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); 8006d38: 687b ldr r3, [r7, #4] 8006d3a: 681b ldr r3, [r3, #0] 8006d3c: 4618 mov r0, r3 8006d3e: f7ff f94a bl 8005fd6 8006d42: 60f8 str r0, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) 8006d44: 687b ldr r3, [r7, #4] 8006d46: 681b ldr r3, [r3, #0] 8006d48: 4618 mov r0, r3 8006d4a: f7ff f931 bl 8005fb0 8006d4e: 4603 mov r3, r0 8006d50: 2b00 cmp r3, #0 8006d52: d047 beq.n 8006de4 && (tmp_adc_is_disable_on_going == 0UL) 8006d54: 68fb ldr r3, [r7, #12] 8006d56: 2b00 cmp r3, #0 8006d58: d144 bne.n 8006de4 ) { /* Check if conditions to disable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) 8006d5a: 687b ldr r3, [r7, #4] 8006d5c: 681b ldr r3, [r3, #0] 8006d5e: 689b ldr r3, [r3, #8] 8006d60: f003 030d and.w r3, r3, #13 8006d64: 2b01 cmp r3, #1 8006d66: d10c bne.n 8006d82 { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); 8006d68: 687b ldr r3, [r7, #4] 8006d6a: 681b ldr r3, [r3, #0] 8006d6c: 4618 mov r0, r3 8006d6e: f7ff f90b bl 8005f88 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); 8006d72: 687b ldr r3, [r7, #4] 8006d74: 681b ldr r3, [r3, #0] 8006d76: 2203 movs r2, #3 8006d78: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); 8006d7a: f7fe ff19 bl 8005bb0 8006d7e: 60b8 str r0, [r7, #8] while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8006d80: e029 b.n 8006dd6 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006d82: 687b ldr r3, [r7, #4] 8006d84: 6d5b ldr r3, [r3, #84] @ 0x54 8006d86: f043 0210 orr.w r2, r3, #16 8006d8a: 687b ldr r3, [r7, #4] 8006d8c: 655a str r2, [r3, #84] @ 0x54 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006d8e: 687b ldr r3, [r7, #4] 8006d90: 6d9b ldr r3, [r3, #88] @ 0x58 8006d92: f043 0201 orr.w r2, r3, #1 8006d96: 687b ldr r3, [r7, #4] 8006d98: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006d9a: 2301 movs r3, #1 8006d9c: e023 b.n 8006de6 { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8006d9e: f7fe ff07 bl 8005bb0 8006da2: 4602 mov r2, r0 8006da4: 68bb ldr r3, [r7, #8] 8006da6: 1ad3 subs r3, r2, r3 8006da8: 2b02 cmp r3, #2 8006daa: d914 bls.n 8006dd6 { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8006dac: 687b ldr r3, [r7, #4] 8006dae: 681b ldr r3, [r3, #0] 8006db0: 689b ldr r3, [r3, #8] 8006db2: f003 0301 and.w r3, r3, #1 8006db6: 2b00 cmp r3, #0 8006db8: d00d beq.n 8006dd6 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006dba: 687b ldr r3, [r7, #4] 8006dbc: 6d5b ldr r3, [r3, #84] @ 0x54 8006dbe: f043 0210 orr.w r2, r3, #16 8006dc2: 687b ldr r3, [r7, #4] 8006dc4: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006dc6: 687b ldr r3, [r7, #4] 8006dc8: 6d9b ldr r3, [r3, #88] @ 0x58 8006dca: f043 0201 orr.w r2, r3, #1 8006dce: 687b ldr r3, [r7, #4] 8006dd0: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006dd2: 2301 movs r3, #1 8006dd4: e007 b.n 8006de6 while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8006dd6: 687b ldr r3, [r7, #4] 8006dd8: 681b ldr r3, [r3, #0] 8006dda: 689b ldr r3, [r3, #8] 8006ddc: f003 0301 and.w r3, r3, #1 8006de0: 2b00 cmp r3, #0 8006de2: d1dc bne.n 8006d9e } } } /* Return HAL status */ return HAL_OK; 8006de4: 2300 movs r3, #0 } 8006de6: 4618 mov r0, r3 8006de8: 3710 adds r7, #16 8006dea: 46bd mov sp, r7 8006dec: bd80 pop {r7, pc} 08006dee : * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 8006dee: b580 push {r7, lr} 8006df0: b084 sub sp, #16 8006df2: af00 add r7, sp, #0 8006df4: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006df6: 687b ldr r3, [r7, #4] 8006df8: 6b9b ldr r3, [r3, #56] @ 0x38 8006dfa: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) 8006dfc: 68fb ldr r3, [r7, #12] 8006dfe: 6d5b ldr r3, [r3, #84] @ 0x54 8006e00: f003 0350 and.w r3, r3, #80 @ 0x50 8006e04: 2b00 cmp r3, #0 8006e06: d14b bne.n 8006ea0 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8006e08: 68fb ldr r3, [r7, #12] 8006e0a: 6d5b ldr r3, [r3, #84] @ 0x54 8006e0c: f443 7200 orr.w r2, r3, #512 @ 0x200 8006e10: 68fb ldr r3, [r7, #12] 8006e12: 655a str r2, [r3, #84] @ 0x54 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ /* Is it the end of the regular sequence ? */ if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) 8006e14: 68fb ldr r3, [r7, #12] 8006e16: 681b ldr r3, [r3, #0] 8006e18: 681b ldr r3, [r3, #0] 8006e1a: f003 0308 and.w r3, r3, #8 8006e1e: 2b00 cmp r3, #0 8006e20: d021 beq.n 8006e66 { /* Are conversions software-triggered ? */ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) 8006e22: 68fb ldr r3, [r7, #12] 8006e24: 681b ldr r3, [r3, #0] 8006e26: 4618 mov r0, r3 8006e28: f7fe ff9c bl 8005d64 8006e2c: 4603 mov r3, r0 8006e2e: 2b00 cmp r3, #0 8006e30: d032 beq.n 8006e98 { /* Is CONT bit set ? */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) 8006e32: 68fb ldr r3, [r7, #12] 8006e34: 681b ldr r3, [r3, #0] 8006e36: 68db ldr r3, [r3, #12] 8006e38: f403 5300 and.w r3, r3, #8192 @ 0x2000 8006e3c: 2b00 cmp r3, #0 8006e3e: d12b bne.n 8006e98 { /* CONT bit is not set, no more conversions expected */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8006e40: 68fb ldr r3, [r7, #12] 8006e42: 6d5b ldr r3, [r3, #84] @ 0x54 8006e44: f423 7280 bic.w r2, r3, #256 @ 0x100 8006e48: 68fb ldr r3, [r7, #12] 8006e4a: 655a str r2, [r3, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 8006e4c: 68fb ldr r3, [r7, #12] 8006e4e: 6d5b ldr r3, [r3, #84] @ 0x54 8006e50: f403 5380 and.w r3, r3, #4096 @ 0x1000 8006e54: 2b00 cmp r3, #0 8006e56: d11f bne.n 8006e98 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8006e58: 68fb ldr r3, [r7, #12] 8006e5a: 6d5b ldr r3, [r3, #84] @ 0x54 8006e5c: f043 0201 orr.w r2, r3, #1 8006e60: 68fb ldr r3, [r7, #12] 8006e62: 655a str r2, [r3, #84] @ 0x54 8006e64: e018 b.n 8006e98 } else { /* DMA End of Transfer interrupt was triggered but conversions sequence is not over. If DMACFG is set to 0, conversions are stopped. */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL) 8006e66: 68fb ldr r3, [r7, #12] 8006e68: 681b ldr r3, [r3, #0] 8006e6a: 68db ldr r3, [r3, #12] 8006e6c: f003 0303 and.w r3, r3, #3 8006e70: 2b00 cmp r3, #0 8006e72: d111 bne.n 8006e98 { /* DMACFG bit is not set, conversions are stopped. */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8006e74: 68fb ldr r3, [r7, #12] 8006e76: 6d5b ldr r3, [r3, #84] @ 0x54 8006e78: f423 7280 bic.w r2, r3, #256 @ 0x100 8006e7c: 68fb ldr r3, [r7, #12] 8006e7e: 655a str r2, [r3, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 8006e80: 68fb ldr r3, [r7, #12] 8006e82: 6d5b ldr r3, [r3, #84] @ 0x54 8006e84: f403 5380 and.w r3, r3, #4096 @ 0x1000 8006e88: 2b00 cmp r3, #0 8006e8a: d105 bne.n 8006e98 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8006e8c: 68fb ldr r3, [r7, #12] 8006e8e: 6d5b ldr r3, [r3, #84] @ 0x54 8006e90: f043 0201 orr.w r2, r3, #1 8006e94: 68fb ldr r3, [r7, #12] 8006e96: 655a str r2, [r3, #84] @ 0x54 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 8006e98: 68f8 ldr r0, [r7, #12] 8006e9a: f7fa fc31 bl 8001700 { /* Call ADC DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } } 8006e9e: e00e b.n 8006ebe if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) 8006ea0: 68fb ldr r3, [r7, #12] 8006ea2: 6d5b ldr r3, [r3, #84] @ 0x54 8006ea4: f003 0310 and.w r3, r3, #16 8006ea8: 2b00 cmp r3, #0 8006eaa: d003 beq.n 8006eb4 HAL_ADC_ErrorCallback(hadc); 8006eac: 68f8 ldr r0, [r7, #12] 8006eae: f7ff fb4f bl 8006550 } 8006eb2: e004 b.n 8006ebe hadc->DMA_Handle->XferErrorCallback(hdma); 8006eb4: 68fb ldr r3, [r7, #12] 8006eb6: 6cdb ldr r3, [r3, #76] @ 0x4c 8006eb8: 6cdb ldr r3, [r3, #76] @ 0x4c 8006eba: 6878 ldr r0, [r7, #4] 8006ebc: 4798 blx r3 } 8006ebe: bf00 nop 8006ec0: 3710 adds r7, #16 8006ec2: 46bd mov sp, r7 8006ec4: bd80 pop {r7, pc} 08006ec6 : * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 8006ec6: b580 push {r7, lr} 8006ec8: b084 sub sp, #16 8006eca: af00 add r7, sp, #0 8006ecc: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006ece: 687b ldr r3, [r7, #4] 8006ed0: 6b9b ldr r3, [r3, #56] @ 0x38 8006ed2: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 8006ed4: 68f8 ldr r0, [r7, #12] 8006ed6: f7ff fb31 bl 800653c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8006eda: bf00 nop 8006edc: 3710 adds r7, #16 8006ede: 46bd mov sp, r7 8006ee0: bd80 pop {r7, pc} 08006ee2 : * @brief DMA error callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 8006ee2: b580 push {r7, lr} 8006ee4: b084 sub sp, #16 8006ee6: af00 add r7, sp, #0 8006ee8: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006eea: 687b ldr r3, [r7, #4] 8006eec: 6b9b ldr r3, [r3, #56] @ 0x38 8006eee: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 8006ef0: 68fb ldr r3, [r7, #12] 8006ef2: 6d5b ldr r3, [r3, #84] @ 0x54 8006ef4: f043 0240 orr.w r2, r3, #64 @ 0x40 8006ef8: 68fb ldr r3, [r7, #12] 8006efa: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 8006efc: 68fb ldr r3, [r7, #12] 8006efe: 6d9b ldr r3, [r3, #88] @ 0x58 8006f00: f043 0204 orr.w r2, r3, #4 8006f04: 68fb ldr r3, [r7, #12] 8006f06: 659a str r2, [r3, #88] @ 0x58 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 8006f08: 68f8 ldr r0, [r7, #12] 8006f0a: f7ff fb21 bl 8006550 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8006f0e: bf00 nop 8006f10: 3710 adds r7, #16 8006f12: 46bd mov sp, r7 8006f14: bd80 pop {r7, pc} ... 08006f18 : * stopped. * @param hadc ADC handle * @retval None. */ void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc) { 8006f18: b580 push {r7, lr} 8006f1a: b084 sub sp, #16 8006f1c: af00 add r7, sp, #0 8006f1e: 6078 str r0, [r7, #4] uint32_t freq; if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc)) 8006f20: 687b ldr r3, [r7, #4] 8006f22: 681b ldr r3, [r3, #0] 8006f24: 4a7a ldr r2, [pc, #488] @ (8007110 ) 8006f26: 4293 cmp r3, r2 8006f28: d004 beq.n 8006f34 8006f2a: 687b ldr r3, [r7, #4] 8006f2c: 681b ldr r3, [r3, #0] 8006f2e: 4a79 ldr r2, [pc, #484] @ (8007114 ) 8006f30: 4293 cmp r3, r2 8006f32: d109 bne.n 8006f48 8006f34: 4b78 ldr r3, [pc, #480] @ (8007118 ) 8006f36: 689b ldr r3, [r3, #8] 8006f38: f403 3340 and.w r3, r3, #196608 @ 0x30000 8006f3c: 2b00 cmp r3, #0 8006f3e: bf14 ite ne 8006f40: 2301 movne r3, #1 8006f42: 2300 moveq r3, #0 8006f44: b2db uxtb r3, r3 8006f46: e008 b.n 8006f5a 8006f48: 4b74 ldr r3, [pc, #464] @ (800711c ) 8006f4a: 689b ldr r3, [r3, #8] 8006f4c: f403 3340 and.w r3, r3, #196608 @ 0x30000 8006f50: 2b00 cmp r3, #0 8006f52: bf14 ite ne 8006f54: 2301 movne r3, #1 8006f56: 2300 moveq r3, #0 8006f58: b2db uxtb r3, r3 8006f5a: 2b00 cmp r3, #0 8006f5c: d01c beq.n 8006f98 { freq = HAL_RCC_GetHCLKFreq(); 8006f5e: f005 fae9 bl 800c534 8006f62: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 8006f64: 687b ldr r3, [r7, #4] 8006f66: 685b ldr r3, [r3, #4] 8006f68: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8006f6c: d010 beq.n 8006f90 8006f6e: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8006f72: d873 bhi.n 800705c 8006f74: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8006f78: d002 beq.n 8006f80 8006f7a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8006f7e: d16d bne.n 800705c { case ADC_CLOCK_SYNC_PCLK_DIV1: case ADC_CLOCK_SYNC_PCLK_DIV2: freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos); 8006f80: 687b ldr r3, [r7, #4] 8006f82: 685b ldr r3, [r3, #4] 8006f84: 0c1b lsrs r3, r3, #16 8006f86: 68fa ldr r2, [r7, #12] 8006f88: fbb2 f3f3 udiv r3, r2, r3 8006f8c: 60fb str r3, [r7, #12] break; 8006f8e: e068 b.n 8007062 case ADC_CLOCK_SYNC_PCLK_DIV4: freq /= 4UL; 8006f90: 68fb ldr r3, [r7, #12] 8006f92: 089b lsrs r3, r3, #2 8006f94: 60fb str r3, [r7, #12] break; 8006f96: e064 b.n 8007062 break; } } else { freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC); 8006f98: f44f 2000 mov.w r0, #524288 @ 0x80000 8006f9c: f04f 0100 mov.w r1, #0 8006fa0: f006 fd54 bl 800da4c 8006fa4: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 8006fa6: 687b ldr r3, [r7, #4] 8006fa8: 685b ldr r3, [r3, #4] 8006faa: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 8006fae: d051 beq.n 8007054 8006fb0: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 8006fb4: d854 bhi.n 8007060 8006fb6: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 8006fba: d047 beq.n 800704c 8006fbc: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 8006fc0: d84e bhi.n 8007060 8006fc2: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 8006fc6: d03d beq.n 8007044 8006fc8: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 8006fcc: d848 bhi.n 8007060 8006fce: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8006fd2: d033 beq.n 800703c 8006fd4: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8006fd8: d842 bhi.n 8007060 8006fda: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 8006fde: d029 beq.n 8007034 8006fe0: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 8006fe4: d83c bhi.n 8007060 8006fe6: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 8006fea: d01a beq.n 8007022 8006fec: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 8006ff0: d836 bhi.n 8007060 8006ff2: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 8006ff6: d014 beq.n 8007022 8006ff8: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 8006ffc: d830 bhi.n 8007060 8006ffe: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8007002: d00e beq.n 8007022 8007004: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8007008: d82a bhi.n 8007060 800700a: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 800700e: d008 beq.n 8007022 8007010: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8007014: d824 bhi.n 8007060 8007016: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800701a: d002 beq.n 8007022 800701c: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 8007020: d11e bne.n 8007060 case ADC_CLOCK_ASYNC_DIV4: case ADC_CLOCK_ASYNC_DIV6: case ADC_CLOCK_ASYNC_DIV8: case ADC_CLOCK_ASYNC_DIV10: case ADC_CLOCK_ASYNC_DIV12: freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL); 8007022: 687b ldr r3, [r7, #4] 8007024: 685b ldr r3, [r3, #4] 8007026: 0c9b lsrs r3, r3, #18 8007028: 005b lsls r3, r3, #1 800702a: 68fa ldr r2, [r7, #12] 800702c: fbb2 f3f3 udiv r3, r2, r3 8007030: 60fb str r3, [r7, #12] break; 8007032: e016 b.n 8007062 case ADC_CLOCK_ASYNC_DIV16: freq /= 16UL; 8007034: 68fb ldr r3, [r7, #12] 8007036: 091b lsrs r3, r3, #4 8007038: 60fb str r3, [r7, #12] break; 800703a: e012 b.n 8007062 case ADC_CLOCK_ASYNC_DIV32: freq /= 32UL; 800703c: 68fb ldr r3, [r7, #12] 800703e: 095b lsrs r3, r3, #5 8007040: 60fb str r3, [r7, #12] break; 8007042: e00e b.n 8007062 case ADC_CLOCK_ASYNC_DIV64: freq /= 64UL; 8007044: 68fb ldr r3, [r7, #12] 8007046: 099b lsrs r3, r3, #6 8007048: 60fb str r3, [r7, #12] break; 800704a: e00a b.n 8007062 case ADC_CLOCK_ASYNC_DIV128: freq /= 128UL; 800704c: 68fb ldr r3, [r7, #12] 800704e: 09db lsrs r3, r3, #7 8007050: 60fb str r3, [r7, #12] break; 8007052: e006 b.n 8007062 case ADC_CLOCK_ASYNC_DIV256: freq /= 256UL; 8007054: 68fb ldr r3, [r7, #12] 8007056: 0a1b lsrs r3, r3, #8 8007058: 60fb str r3, [r7, #12] break; 800705a: e002 b.n 8007062 break; 800705c: bf00 nop 800705e: e000 b.n 8007062 default: break; 8007060: bf00 nop else /* if(freq > 25000000UL) */ { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } #else if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */ 8007062: f7fe fdb1 bl 8005bc8 8007066: 4603 mov r3, r0 8007068: f241 0203 movw r2, #4099 @ 0x1003 800706c: 4293 cmp r3, r2 800706e: d815 bhi.n 800709c { if (freq > 20000000UL) 8007070: 68fb ldr r3, [r7, #12] 8007072: 4a2b ldr r2, [pc, #172] @ (8007120 ) 8007074: 4293 cmp r3, r2 8007076: d908 bls.n 800708a { SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 8007078: 687b ldr r3, [r7, #4] 800707a: 681b ldr r3, [r3, #0] 800707c: 689a ldr r2, [r3, #8] 800707e: 687b ldr r3, [r7, #4] 8007080: 681b ldr r3, [r3, #0] 8007082: f442 7280 orr.w r2, r2, #256 @ 0x100 8007086: 609a str r2, [r3, #8] { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } } #endif /* ADC_VER_V5_3 */ } 8007088: e03e b.n 8007108 CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 800708a: 687b ldr r3, [r7, #4] 800708c: 681b ldr r3, [r3, #0] 800708e: 689a ldr r2, [r3, #8] 8007090: 687b ldr r3, [r7, #4] 8007092: 681b ldr r3, [r3, #0] 8007094: f422 7280 bic.w r2, r2, #256 @ 0x100 8007098: 609a str r2, [r3, #8] } 800709a: e035 b.n 8007108 freq /= 2U; /* divider by 2 for Rev.V */ 800709c: 68fb ldr r3, [r7, #12] 800709e: 085b lsrs r3, r3, #1 80070a0: 60fb str r3, [r7, #12] if (freq <= 6250000UL) 80070a2: 68fb ldr r3, [r7, #12] 80070a4: 4a1f ldr r2, [pc, #124] @ (8007124 ) 80070a6: 4293 cmp r3, r2 80070a8: d808 bhi.n 80070bc MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL); 80070aa: 687b ldr r3, [r7, #4] 80070ac: 681b ldr r3, [r3, #0] 80070ae: 689a ldr r2, [r3, #8] 80070b0: 687b ldr r3, [r7, #4] 80070b2: 681b ldr r3, [r3, #0] 80070b4: f422 7240 bic.w r2, r2, #768 @ 0x300 80070b8: 609a str r2, [r3, #8] } 80070ba: e025 b.n 8007108 else if (freq <= 12500000UL) 80070bc: 68fb ldr r3, [r7, #12] 80070be: 4a1a ldr r2, [pc, #104] @ (8007128 ) 80070c0: 4293 cmp r3, r2 80070c2: d80a bhi.n 80070da MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0); 80070c4: 687b ldr r3, [r7, #4] 80070c6: 681b ldr r3, [r3, #0] 80070c8: 689b ldr r3, [r3, #8] 80070ca: f423 7240 bic.w r2, r3, #768 @ 0x300 80070ce: 687b ldr r3, [r7, #4] 80070d0: 681b ldr r3, [r3, #0] 80070d2: f442 7280 orr.w r2, r2, #256 @ 0x100 80070d6: 609a str r2, [r3, #8] } 80070d8: e016 b.n 8007108 else if (freq <= 25000000UL) 80070da: 68fb ldr r3, [r7, #12] 80070dc: 4a13 ldr r2, [pc, #76] @ (800712c ) 80070de: 4293 cmp r3, r2 80070e0: d80a bhi.n 80070f8 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1); 80070e2: 687b ldr r3, [r7, #4] 80070e4: 681b ldr r3, [r3, #0] 80070e6: 689b ldr r3, [r3, #8] 80070e8: f423 7240 bic.w r2, r3, #768 @ 0x300 80070ec: 687b ldr r3, [r7, #4] 80070ee: 681b ldr r3, [r3, #0] 80070f0: f442 7200 orr.w r2, r2, #512 @ 0x200 80070f4: 609a str r2, [r3, #8] } 80070f6: e007 b.n 8007108 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); 80070f8: 687b ldr r3, [r7, #4] 80070fa: 681b ldr r3, [r3, #0] 80070fc: 689a ldr r2, [r3, #8] 80070fe: 687b ldr r3, [r7, #4] 8007100: 681b ldr r3, [r3, #0] 8007102: f442 7240 orr.w r2, r2, #768 @ 0x300 8007106: 609a str r2, [r3, #8] } 8007108: bf00 nop 800710a: 3710 adds r7, #16 800710c: 46bd mov sp, r7 800710e: bd80 pop {r7, pc} 8007110: 40022000 .word 0x40022000 8007114: 40022100 .word 0x40022100 8007118: 40022300 .word 0x40022300 800711c: 58026300 .word 0x58026300 8007120: 01312d00 .word 0x01312d00 8007124: 005f5e10 .word 0x005f5e10 8007128: 00bebc20 .word 0x00bebc20 800712c: 017d7840 .word 0x017d7840 08007130 : { 8007130: b480 push {r7} 8007132: b083 sub sp, #12 8007134: af00 add r7, sp, #0 8007136: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8007138: 687b ldr r3, [r7, #4] 800713a: 689b ldr r3, [r3, #8] 800713c: f003 0301 and.w r3, r3, #1 8007140: 2b01 cmp r3, #1 8007142: d101 bne.n 8007148 8007144: 2301 movs r3, #1 8007146: e000 b.n 800714a 8007148: 2300 movs r3, #0 } 800714a: 4618 mov r0, r3 800714c: 370c adds r7, #12 800714e: 46bd mov sp, r7 8007150: f85d 7b04 ldr.w r7, [sp], #4 8007154: 4770 bx lr ... 08007158 : { 8007158: b480 push {r7} 800715a: b085 sub sp, #20 800715c: af00 add r7, sp, #0 800715e: 60f8 str r0, [r7, #12] 8007160: 60b9 str r1, [r7, #8] 8007162: 607a str r2, [r7, #4] MODIFY_REG(ADCx->CR, 8007164: 68fb ldr r3, [r7, #12] 8007166: 689a ldr r2, [r3, #8] 8007168: 4b09 ldr r3, [pc, #36] @ (8007190 ) 800716a: 4013 ands r3, r2 800716c: 68ba ldr r2, [r7, #8] 800716e: f402 3180 and.w r1, r2, #65536 @ 0x10000 8007172: 687a ldr r2, [r7, #4] 8007174: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 8007178: 430a orrs r2, r1 800717a: 4313 orrs r3, r2 800717c: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 8007180: 68fb ldr r3, [r7, #12] 8007182: 609a str r2, [r3, #8] } 8007184: bf00 nop 8007186: 3714 adds r7, #20 8007188: 46bd mov sp, r7 800718a: f85d 7b04 ldr.w r7, [sp], #4 800718e: 4770 bx lr 8007190: 3ffeffc0 .word 0x3ffeffc0 08007194 : { 8007194: b480 push {r7} 8007196: b083 sub sp, #12 8007198: af00 add r7, sp, #0 800719a: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); 800719c: 687b ldr r3, [r7, #4] 800719e: 689b ldr r3, [r3, #8] 80071a0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80071a4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80071a8: d101 bne.n 80071ae 80071aa: 2301 movs r3, #1 80071ac: e000 b.n 80071b0 80071ae: 2300 movs r3, #0 } 80071b0: 4618 mov r0, r3 80071b2: 370c adds r7, #12 80071b4: 46bd mov sp, r7 80071b6: f85d 7b04 ldr.w r7, [sp], #4 80071ba: 4770 bx lr 080071bc : { 80071bc: b480 push {r7} 80071be: b083 sub sp, #12 80071c0: af00 add r7, sp, #0 80071c2: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 80071c4: 687b ldr r3, [r7, #4] 80071c6: 689b ldr r3, [r3, #8] 80071c8: f003 0304 and.w r3, r3, #4 80071cc: 2b04 cmp r3, #4 80071ce: d101 bne.n 80071d4 80071d0: 2301 movs r3, #1 80071d2: e000 b.n 80071d6 80071d4: 2300 movs r3, #0 } 80071d6: 4618 mov r0, r3 80071d8: 370c adds r7, #12 80071da: 46bd mov sp, r7 80071dc: f85d 7b04 ldr.w r7, [sp], #4 80071e0: 4770 bx lr ... 080071e4 : * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff) { 80071e4: b580 push {r7, lr} 80071e6: b086 sub sp, #24 80071e8: af00 add r7, sp, #0 80071ea: 60f8 str r0, [r7, #12] 80071ec: 60b9 str r1, [r7, #8] 80071ee: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; 80071f0: 2300 movs r3, #0 80071f2: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Process locked */ __HAL_LOCK(hadc); 80071f4: 68fb ldr r3, [r7, #12] 80071f6: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 80071fa: 2b01 cmp r3, #1 80071fc: d101 bne.n 8007202 80071fe: 2302 movs r3, #2 8007200: e04c b.n 800729c 8007202: 68fb ldr r3, [r7, #12] 8007204: 2201 movs r2, #1 8007206: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Calibration prerequisite: ADC must be disabled. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); 800720a: 68f8 ldr r0, [r7, #12] 800720c: f7ff fd90 bl 8006d30 8007210: 4603 mov r3, r0 8007212: 75fb strb r3, [r7, #23] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8007214: 7dfb ldrb r3, [r7, #23] 8007216: 2b00 cmp r3, #0 8007218: d135 bne.n 8007286 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800721a: 68fb ldr r3, [r7, #12] 800721c: 6d5a ldr r2, [r3, #84] @ 0x54 800721e: 4b21 ldr r3, [pc, #132] @ (80072a4 ) 8007220: 4013 ands r3, r2 8007222: f043 0202 orr.w r2, r3, #2 8007226: 68fb ldr r3, [r7, #12] 8007228: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Start ADC calibration in mode single-ended or differential */ LL_ADC_StartCalibration(hadc->Instance, CalibrationMode, SingleDiff); 800722a: 68fb ldr r3, [r7, #12] 800722c: 681b ldr r3, [r3, #0] 800722e: 687a ldr r2, [r7, #4] 8007230: 68b9 ldr r1, [r7, #8] 8007232: 4618 mov r0, r3 8007234: f7ff ff90 bl 8007158 /* Wait for calibration completion */ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 8007238: e014 b.n 8007264 { wait_loop_index++; 800723a: 693b ldr r3, [r7, #16] 800723c: 3301 adds r3, #1 800723e: 613b str r3, [r7, #16] if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) 8007240: 693b ldr r3, [r7, #16] 8007242: 4a19 ldr r2, [pc, #100] @ (80072a8 ) 8007244: 4293 cmp r3, r2 8007246: d30d bcc.n 8007264 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8007248: 68fb ldr r3, [r7, #12] 800724a: 6d5b ldr r3, [r3, #84] @ 0x54 800724c: f023 0312 bic.w r3, r3, #18 8007250: f043 0210 orr.w r2, r3, #16 8007254: 68fb ldr r3, [r7, #12] 8007256: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 8007258: 68fb ldr r3, [r7, #12] 800725a: 2200 movs r2, #0 800725c: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 8007260: 2301 movs r3, #1 8007262: e01b b.n 800729c while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 8007264: 68fb ldr r3, [r7, #12] 8007266: 681b ldr r3, [r3, #0] 8007268: 4618 mov r0, r3 800726a: f7ff ff93 bl 8007194 800726e: 4603 mov r3, r0 8007270: 2b00 cmp r3, #0 8007272: d1e2 bne.n 800723a } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8007274: 68fb ldr r3, [r7, #12] 8007276: 6d5b ldr r3, [r3, #84] @ 0x54 8007278: f023 0303 bic.w r3, r3, #3 800727c: f043 0201 orr.w r2, r3, #1 8007280: 68fb ldr r3, [r7, #12] 8007282: 655a str r2, [r3, #84] @ 0x54 8007284: e005 b.n 8007292 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8007286: 68fb ldr r3, [r7, #12] 8007288: 6d5b ldr r3, [r3, #84] @ 0x54 800728a: f043 0210 orr.w r2, r3, #16 800728e: 68fb ldr r3, [r7, #12] 8007290: 655a str r2, [r3, #84] @ 0x54 /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } /* Process unlocked */ __HAL_UNLOCK(hadc); 8007292: 68fb ldr r3, [r7, #12] 8007294: 2200 movs r2, #0 8007296: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 800729a: 7dfb ldrb r3, [r7, #23] } 800729c: 4618 mov r0, r3 800729e: 3718 adds r7, #24 80072a0: 46bd mov sp, r7 80072a2: bd80 pop {r7, pc} 80072a4: ffffeefd .word 0xffffeefd 80072a8: 25c3f800 .word 0x25c3f800 080072ac : * @param hadc Master ADC handle * @param multimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { 80072ac: b590 push {r4, r7, lr} 80072ae: b09f sub sp, #124 @ 0x7c 80072b0: af00 add r7, sp, #0 80072b2: 6078 str r0, [r7, #4] 80072b4: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80072b6: 2300 movs r3, #0 80072b8: f887 3077 strb.w r3, [r7, #119] @ 0x77 assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); 80072bc: 687b ldr r3, [r7, #4] 80072be: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 80072c2: 2b01 cmp r3, #1 80072c4: d101 bne.n 80072ca 80072c6: 2302 movs r3, #2 80072c8: e0be b.n 8007448 80072ca: 687b ldr r3, [r7, #4] 80072cc: 2201 movs r2, #1 80072ce: f883 2050 strb.w r2, [r3, #80] @ 0x50 tmphadcSlave.State = HAL_ADC_STATE_RESET; 80072d2: 2300 movs r3, #0 80072d4: 65fb str r3, [r7, #92] @ 0x5c tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; 80072d6: 2300 movs r3, #0 80072d8: 663b str r3, [r7, #96] @ 0x60 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 80072da: 687b ldr r3, [r7, #4] 80072dc: 681b ldr r3, [r3, #0] 80072de: 4a5c ldr r2, [pc, #368] @ (8007450 ) 80072e0: 4293 cmp r3, r2 80072e2: d102 bne.n 80072ea 80072e4: 4b5b ldr r3, [pc, #364] @ (8007454 ) 80072e6: 60bb str r3, [r7, #8] 80072e8: e001 b.n 80072ee 80072ea: 2300 movs r3, #0 80072ec: 60bb str r3, [r7, #8] if (tmphadcSlave.Instance == NULL) 80072ee: 68bb ldr r3, [r7, #8] 80072f0: 2b00 cmp r3, #0 80072f2: d10b bne.n 800730c { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80072f4: 687b ldr r3, [r7, #4] 80072f6: 6d5b ldr r3, [r3, #84] @ 0x54 80072f8: f043 0220 orr.w r2, r3, #32 80072fc: 687b ldr r3, [r7, #4] 80072fe: 655a str r2, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hadc); 8007300: 687b ldr r3, [r7, #4] 8007302: 2200 movs r2, #0 8007304: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 8007308: 2301 movs r3, #1 800730a: e09d b.n 8007448 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DATA Format configuration */ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); 800730c: 68bb ldr r3, [r7, #8] 800730e: 4618 mov r0, r3 8007310: f7ff ff54 bl 80071bc 8007314: 6738 str r0, [r7, #112] @ 0x70 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8007316: 687b ldr r3, [r7, #4] 8007318: 681b ldr r3, [r3, #0] 800731a: 4618 mov r0, r3 800731c: f7ff ff4e bl 80071bc 8007320: 4603 mov r3, r0 8007322: 2b00 cmp r3, #0 8007324: d17f bne.n 8007426 && (tmphadcSlave_conversion_on_going == 0UL)) 8007326: 6f3b ldr r3, [r7, #112] @ 0x70 8007328: 2b00 cmp r3, #0 800732a: d17c bne.n 8007426 { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); 800732c: 687b ldr r3, [r7, #4] 800732e: 681b ldr r3, [r3, #0] 8007330: 4a47 ldr r2, [pc, #284] @ (8007450 ) 8007332: 4293 cmp r3, r2 8007334: d004 beq.n 8007340 8007336: 687b ldr r3, [r7, #4] 8007338: 681b ldr r3, [r3, #0] 800733a: 4a46 ldr r2, [pc, #280] @ (8007454 ) 800733c: 4293 cmp r3, r2 800733e: d101 bne.n 8007344 8007340: 4b45 ldr r3, [pc, #276] @ (8007458 ) 8007342: e000 b.n 8007346 8007344: 4b45 ldr r3, [pc, #276] @ (800745c ) 8007346: 66fb str r3, [r7, #108] @ 0x6c /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if (multimode->Mode != ADC_MODE_INDEPENDENT) 8007348: 683b ldr r3, [r7, #0] 800734a: 681b ldr r3, [r3, #0] 800734c: 2b00 cmp r3, #0 800734e: d039 beq.n 80073c4 { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData); 8007350: 6efb ldr r3, [r7, #108] @ 0x6c 8007352: 689b ldr r3, [r3, #8] 8007354: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8007358: 683b ldr r3, [r7, #0] 800735a: 685b ldr r3, [r3, #4] 800735c: 431a orrs r2, r3 800735e: 6efb ldr r3, [r7, #108] @ 0x6c 8007360: 609a str r2, [r3, #8] /* from 1 to 8 clock cycles for 12 bits */ /* from 1 to 6 clock cycles for 10 and 8 bits */ /* If a higher delay is selected, it will be clipped to maximum delay */ /* range */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8007362: 687b ldr r3, [r7, #4] 8007364: 681b ldr r3, [r3, #0] 8007366: 4a3a ldr r2, [pc, #232] @ (8007450 ) 8007368: 4293 cmp r3, r2 800736a: d004 beq.n 8007376 800736c: 687b ldr r3, [r7, #4] 800736e: 681b ldr r3, [r3, #0] 8007370: 4a38 ldr r2, [pc, #224] @ (8007454 ) 8007372: 4293 cmp r3, r2 8007374: d10e bne.n 8007394 8007376: 4836 ldr r0, [pc, #216] @ (8007450 ) 8007378: f7ff feda bl 8007130 800737c: 4604 mov r4, r0 800737e: 4835 ldr r0, [pc, #212] @ (8007454 ) 8007380: f7ff fed6 bl 8007130 8007384: 4603 mov r3, r0 8007386: 4323 orrs r3, r4 8007388: 2b00 cmp r3, #0 800738a: bf0c ite eq 800738c: 2301 moveq r3, #1 800738e: 2300 movne r3, #0 8007390: b2db uxtb r3, r3 8007392: e008 b.n 80073a6 8007394: 4832 ldr r0, [pc, #200] @ (8007460 ) 8007396: f7ff fecb bl 8007130 800739a: 4603 mov r3, r0 800739c: 2b00 cmp r3, #0 800739e: bf0c ite eq 80073a0: 2301 moveq r3, #1 80073a2: 2300 movne r3, #0 80073a4: b2db uxtb r3, r3 80073a6: 2b00 cmp r3, #0 80073a8: d047 beq.n 800743a { MODIFY_REG(tmpADC_Common->CCR, 80073aa: 6efb ldr r3, [r7, #108] @ 0x6c 80073ac: 689a ldr r2, [r3, #8] 80073ae: 4b2d ldr r3, [pc, #180] @ (8007464 ) 80073b0: 4013 ands r3, r2 80073b2: 683a ldr r2, [r7, #0] 80073b4: 6811 ldr r1, [r2, #0] 80073b6: 683a ldr r2, [r7, #0] 80073b8: 6892 ldr r2, [r2, #8] 80073ba: 430a orrs r2, r1 80073bc: 431a orrs r2, r3 80073be: 6efb ldr r3, [r7, #108] @ 0x6c 80073c0: 609a str r2, [r3, #8] if (multimode->Mode != ADC_MODE_INDEPENDENT) 80073c2: e03a b.n 800743a ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF); 80073c4: 6efb ldr r3, [r7, #108] @ 0x6c 80073c6: 689b ldr r3, [r3, #8] 80073c8: f423 4240 bic.w r2, r3, #49152 @ 0xc000 80073cc: 6efb ldr r3, [r7, #108] @ 0x6c 80073ce: 609a str r2, [r3, #8] /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 80073d0: 687b ldr r3, [r7, #4] 80073d2: 681b ldr r3, [r3, #0] 80073d4: 4a1e ldr r2, [pc, #120] @ (8007450 ) 80073d6: 4293 cmp r3, r2 80073d8: d004 beq.n 80073e4 80073da: 687b ldr r3, [r7, #4] 80073dc: 681b ldr r3, [r3, #0] 80073de: 4a1d ldr r2, [pc, #116] @ (8007454 ) 80073e0: 4293 cmp r3, r2 80073e2: d10e bne.n 8007402 80073e4: 481a ldr r0, [pc, #104] @ (8007450 ) 80073e6: f7ff fea3 bl 8007130 80073ea: 4604 mov r4, r0 80073ec: 4819 ldr r0, [pc, #100] @ (8007454 ) 80073ee: f7ff fe9f bl 8007130 80073f2: 4603 mov r3, r0 80073f4: 4323 orrs r3, r4 80073f6: 2b00 cmp r3, #0 80073f8: bf0c ite eq 80073fa: 2301 moveq r3, #1 80073fc: 2300 movne r3, #0 80073fe: b2db uxtb r3, r3 8007400: e008 b.n 8007414 8007402: 4817 ldr r0, [pc, #92] @ (8007460 ) 8007404: f7ff fe94 bl 8007130 8007408: 4603 mov r3, r0 800740a: 2b00 cmp r3, #0 800740c: bf0c ite eq 800740e: 2301 moveq r3, #1 8007410: 2300 movne r3, #0 8007412: b2db uxtb r3, r3 8007414: 2b00 cmp r3, #0 8007416: d010 beq.n 800743a { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); 8007418: 6efb ldr r3, [r7, #108] @ 0x6c 800741a: 689a ldr r2, [r3, #8] 800741c: 4b11 ldr r3, [pc, #68] @ (8007464 ) 800741e: 4013 ands r3, r2 8007420: 6efa ldr r2, [r7, #108] @ 0x6c 8007422: 6093 str r3, [r2, #8] if (multimode->Mode != ADC_MODE_INDEPENDENT) 8007424: e009 b.n 800743a /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8007426: 687b ldr r3, [r7, #4] 8007428: 6d5b ldr r3, [r3, #84] @ 0x54 800742a: f043 0220 orr.w r2, r3, #32 800742e: 687b ldr r3, [r7, #4] 8007430: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8007432: 2301 movs r3, #1 8007434: f887 3077 strb.w r3, [r7, #119] @ 0x77 8007438: e000 b.n 800743c if (multimode->Mode != ADC_MODE_INDEPENDENT) 800743a: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); 800743c: 687b ldr r3, [r7, #4] 800743e: 2200 movs r2, #0 8007440: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 8007444: f897 3077 ldrb.w r3, [r7, #119] @ 0x77 } 8007448: 4618 mov r0, r3 800744a: 377c adds r7, #124 @ 0x7c 800744c: 46bd mov sp, r7 800744e: bd90 pop {r4, r7, pc} 8007450: 40022000 .word 0x40022000 8007454: 40022100 .word 0x40022100 8007458: 40022300 .word 0x40022300 800745c: 58026300 .word 0x58026300 8007460: 58026000 .word 0x58026000 8007464: fffff0e0 .word 0xfffff0e0 08007468 : * To unlock the configuration, perform a system reset. * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { 8007468: b580 push {r7, lr} 800746a: b088 sub sp, #32 800746c: af00 add r7, sp, #0 800746e: 6078 str r0, [r7, #4] uint32_t tmp_csr ; uint32_t exti_line ; uint32_t comp_voltage_scaler_initialized; /* Value "0" is comparator voltage scaler is not initialized */ __IO uint32_t wait_loop_index = 0UL; 8007470: 2300 movs r3, #0 8007472: 60fb str r3, [r7, #12] HAL_StatusTypeDef status = HAL_OK; 8007474: 2300 movs r3, #0 8007476: 77fb strb r3, [r7, #31] /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) 8007478: 687b ldr r3, [r7, #4] 800747a: 2b00 cmp r3, #0 800747c: d102 bne.n 8007484 { status = HAL_ERROR; 800747e: 2301 movs r3, #1 8007480: 77fb strb r3, [r7, #31] 8007482: e10e b.n 80076a2 } else if(__HAL_COMP_IS_LOCKED(hcomp)) 8007484: 687b ldr r3, [r7, #4] 8007486: 681b ldr r3, [r3, #0] 8007488: 681b ldr r3, [r3, #0] 800748a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 800748e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007492: d102 bne.n 800749a { status = HAL_ERROR; 8007494: 2301 movs r3, #1 8007496: 77fb strb r3, [r7, #31] 8007498: e103 b.n 80076a2 assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); if(hcomp->State == HAL_COMP_STATE_RESET) 800749a: 687b ldr r3, [r7, #4] 800749c: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 80074a0: b2db uxtb r3, r3 80074a2: 2b00 cmp r3, #0 80074a4: d109 bne.n 80074ba { /* Allocate lock resource and initialize it */ hcomp->Lock = HAL_UNLOCKED; 80074a6: 687b ldr r3, [r7, #4] 80074a8: 2200 movs r2, #0 80074aa: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Set COMP error code to none */ COMP_CLEAR_ERRORCODE(hcomp); 80074ae: 687b ldr r3, [r7, #4] 80074b0: 2200 movs r2, #0 80074b2: 629a str r2, [r3, #40] @ 0x28 /* Init the low level hardware */ hcomp->MspInitCallback(hcomp); #else /* Init the low level hardware */ HAL_COMP_MspInit(hcomp); 80074b4: 6878 ldr r0, [r7, #4] 80074b6: f7fc fd49 bl 8003f4c #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } /* Memorize voltage scaler state before initialization */ comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN); 80074ba: 687b ldr r3, [r7, #4] 80074bc: 681b ldr r3, [r3, #0] 80074be: 681b ldr r3, [r3, #0] 80074c0: f003 0304 and.w r3, r3, #4 80074c4: 61bb str r3, [r7, #24] /* Set BLANKING bits according to hcomp->Init.BlankingSrce value */ /* Set HYST bits according to hcomp->Init.Hysteresis value */ /* Set POLARITY bit according to hcomp->Init.OutputPol value */ /* Set POWERMODE bits according to hcomp->Init.Mode value */ tmp_csr = (hcomp->Init.InvertingInput | \ 80074c6: 687b ldr r3, [r7, #4] 80074c8: 691a ldr r2, [r3, #16] hcomp->Init.NonInvertingInput | \ 80074ca: 687b ldr r3, [r7, #4] 80074cc: 68db ldr r3, [r3, #12] tmp_csr = (hcomp->Init.InvertingInput | \ 80074ce: 431a orrs r2, r3 hcomp->Init.BlankingSrce | \ 80074d0: 687b ldr r3, [r7, #4] 80074d2: 69db ldr r3, [r3, #28] hcomp->Init.NonInvertingInput | \ 80074d4: 431a orrs r2, r3 hcomp->Init.Hysteresis | \ 80074d6: 687b ldr r3, [r7, #4] 80074d8: 695b ldr r3, [r3, #20] hcomp->Init.BlankingSrce | \ 80074da: 431a orrs r2, r3 hcomp->Init.OutputPol | \ 80074dc: 687b ldr r3, [r7, #4] 80074de: 699b ldr r3, [r3, #24] hcomp->Init.Hysteresis | \ 80074e0: 431a orrs r2, r3 hcomp->Init.Mode ); 80074e2: 687b ldr r3, [r7, #4] 80074e4: 689b ldr r3, [r3, #8] tmp_csr = (hcomp->Init.InvertingInput | \ 80074e6: 4313 orrs r3, r2 80074e8: 617b str r3, [r7, #20] COMP_CFGRx_INP2SEL | COMP_CFGRx_WINMODE | COMP_CFGRx_POLARITY | COMP_CFGRx_HYST | COMP_CFGRx_BLANKING | COMP_CFGRx_BRGEN | COMP_CFGRx_SCALEN, tmp_csr ); #else MODIFY_REG(hcomp->Instance->CFGR, 80074ea: 687b ldr r3, [r7, #4] 80074ec: 681b ldr r3, [r3, #0] 80074ee: 681a ldr r2, [r3, #0] 80074f0: 4b6e ldr r3, [pc, #440] @ (80076ac ) 80074f2: 4013 ands r3, r2 80074f4: 687a ldr r2, [r7, #4] 80074f6: 6812 ldr r2, [r2, #0] 80074f8: 6979 ldr r1, [r7, #20] 80074fa: 430b orrs r3, r1 80074fc: 6013 str r3, [r2, #0] #endif /* Set window mode */ /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ /* instances. Therefore, this function can update another COMP */ /* instance that the one currently selected. */ if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) 80074fe: 687b ldr r3, [r7, #4] 8007500: 685b ldr r3, [r3, #4] 8007502: 2b10 cmp r3, #16 8007504: d108 bne.n 8007518 { SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE); 8007506: 687b ldr r3, [r7, #4] 8007508: 681b ldr r3, [r3, #0] 800750a: 681a ldr r2, [r3, #0] 800750c: 687b ldr r3, [r7, #4] 800750e: 681b ldr r3, [r3, #0] 8007510: f042 0210 orr.w r2, r2, #16 8007514: 601a str r2, [r3, #0] 8007516: e007 b.n 8007528 } else { CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE); 8007518: 687b ldr r3, [r7, #4] 800751a: 681b ldr r3, [r3, #0] 800751c: 681a ldr r2, [r3, #0] 800751e: 687b ldr r3, [r7, #4] 8007520: 681b ldr r3, [r3, #0] 8007522: f022 0210 bic.w r2, r2, #16 8007526: 601a str r2, [r3, #0] } /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is enabled for the first time */ if ((READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN) != 0UL) && 8007528: 687b ldr r3, [r7, #4] 800752a: 681b ldr r3, [r3, #0] 800752c: 681b ldr r3, [r3, #0] 800752e: f003 0304 and.w r3, r3, #4 8007532: 2b00 cmp r3, #0 8007534: d016 beq.n 8007564 8007536: 69bb ldr r3, [r7, #24] 8007538: 2b00 cmp r3, #0 800753a: d013 beq.n 8007564 { /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles.*/ wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 800753c: 4b5c ldr r3, [pc, #368] @ (80076b0 ) 800753e: 681b ldr r3, [r3, #0] 8007540: 099b lsrs r3, r3, #6 8007542: 4a5c ldr r2, [pc, #368] @ (80076b4 ) 8007544: fba2 2303 umull r2, r3, r2, r3 8007548: 099b lsrs r3, r3, #6 800754a: 1c5a adds r2, r3, #1 800754c: 4613 mov r3, r2 800754e: 009b lsls r3, r3, #2 8007550: 4413 add r3, r2 8007552: 009b lsls r3, r3, #2 8007554: 60fb str r3, [r7, #12] while(wait_loop_index != 0UL) 8007556: e002 b.n 800755e { wait_loop_index --; 8007558: 68fb ldr r3, [r7, #12] 800755a: 3b01 subs r3, #1 800755c: 60fb str r3, [r7, #12] while(wait_loop_index != 0UL) 800755e: 68fb ldr r3, [r7, #12] 8007560: 2b00 cmp r3, #0 8007562: d1f9 bne.n 8007558 } } /* Get the EXTI line corresponding to the selected COMP instance */ exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); 8007564: 687b ldr r3, [r7, #4] 8007566: 681b ldr r3, [r3, #0] 8007568: 4a53 ldr r2, [pc, #332] @ (80076b8 ) 800756a: 4293 cmp r3, r2 800756c: d102 bne.n 8007574 800756e: f44f 1380 mov.w r3, #1048576 @ 0x100000 8007572: e001 b.n 8007578 8007574: f44f 1300 mov.w r3, #2097152 @ 0x200000 8007578: 613b str r3, [r7, #16] /* Manage EXTI settings */ if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) 800757a: 687b ldr r3, [r7, #4] 800757c: 6a1b ldr r3, [r3, #32] 800757e: f003 0303 and.w r3, r3, #3 8007582: 2b00 cmp r3, #0 8007584: d06d beq.n 8007662 { /* Configure EXTI rising edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) 8007586: 687b ldr r3, [r7, #4] 8007588: 6a1b ldr r3, [r3, #32] 800758a: f003 0310 and.w r3, r3, #16 800758e: 2b00 cmp r3, #0 8007590: d008 beq.n 80075a4 { SET_BIT(EXTI->RTSR1, exti_line); 8007592: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007596: 681a ldr r2, [r3, #0] 8007598: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800759c: 693b ldr r3, [r7, #16] 800759e: 4313 orrs r3, r2 80075a0: 600b str r3, [r1, #0] 80075a2: e008 b.n 80075b6 } else { CLEAR_BIT(EXTI->RTSR1, exti_line); 80075a4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80075a8: 681a ldr r2, [r3, #0] 80075aa: 693b ldr r3, [r7, #16] 80075ac: 43db mvns r3, r3 80075ae: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80075b2: 4013 ands r3, r2 80075b4: 600b str r3, [r1, #0] } /* Configure EXTI falling edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) 80075b6: 687b ldr r3, [r7, #4] 80075b8: 6a1b ldr r3, [r3, #32] 80075ba: f003 0320 and.w r3, r3, #32 80075be: 2b00 cmp r3, #0 80075c0: d008 beq.n 80075d4 { SET_BIT(EXTI->FTSR1, exti_line); 80075c2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80075c6: 685a ldr r2, [r3, #4] 80075c8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80075cc: 693b ldr r3, [r7, #16] 80075ce: 4313 orrs r3, r2 80075d0: 604b str r3, [r1, #4] 80075d2: e008 b.n 80075e6 } else { CLEAR_BIT(EXTI->FTSR1, exti_line); 80075d4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80075d8: 685a ldr r2, [r3, #4] 80075da: 693b ldr r3, [r7, #16] 80075dc: 43db mvns r3, r3 80075de: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80075e2: 4013 ands r3, r2 80075e4: 604b str r3, [r1, #4] } #if !defined (CORE_CM4) /* Clear COMP EXTI pending bit (if any) */ WRITE_REG(EXTI->PR1, exti_line); 80075e6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 80075ea: 693b ldr r3, [r7, #16] 80075ec: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure EXTI event mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) 80075f0: 687b ldr r3, [r7, #4] 80075f2: 6a1b ldr r3, [r3, #32] 80075f4: f003 0302 and.w r3, r3, #2 80075f8: 2b00 cmp r3, #0 80075fa: d00a beq.n 8007612 { SET_BIT(EXTI->EMR1, exti_line); 80075fc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007600: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 8007604: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007608: 693b ldr r3, [r7, #16] 800760a: 4313 orrs r3, r2 800760c: f8c1 3084 str.w r3, [r1, #132] @ 0x84 8007610: e00a b.n 8007628 } else { CLEAR_BIT(EXTI->EMR1, exti_line); 8007612: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007616: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 800761a: 693b ldr r3, [r7, #16] 800761c: 43db mvns r3, r3 800761e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007622: 4013 ands r3, r2 8007624: f8c1 3084 str.w r3, [r1, #132] @ 0x84 } /* Configure EXTI interrupt mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) 8007628: 687b ldr r3, [r7, #4] 800762a: 6a1b ldr r3, [r3, #32] 800762c: f003 0301 and.w r3, r3, #1 8007630: 2b00 cmp r3, #0 8007632: d00a beq.n 800764a { SET_BIT(EXTI->IMR1, exti_line); 8007634: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007638: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 800763c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007640: 693b ldr r3, [r7, #16] 8007642: 4313 orrs r3, r2 8007644: f8c1 3080 str.w r3, [r1, #128] @ 0x80 8007648: e021 b.n 800768e } else { CLEAR_BIT(EXTI->IMR1, exti_line); 800764a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800764e: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 8007652: 693b ldr r3, [r7, #16] 8007654: 43db mvns r3, r3 8007656: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800765a: 4013 ands r3, r2 800765c: f8c1 3080 str.w r3, [r1, #128] @ 0x80 8007660: e015 b.n 800768e } } else { /* Disable EXTI event mode */ CLEAR_BIT(EXTI->EMR1, exti_line); 8007662: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007666: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 800766a: 693b ldr r3, [r7, #16] 800766c: 43db mvns r3, r3 800766e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007672: 4013 ands r3, r2 8007674: f8c1 3084 str.w r3, [r1, #132] @ 0x84 /* Disable EXTI interrupt mode */ CLEAR_BIT(EXTI->IMR1, exti_line); 8007678: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800767c: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 8007680: 693b ldr r3, [r7, #16] 8007682: 43db mvns r3, r3 8007684: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007688: 4013 ands r3, r2 800768a: f8c1 3080 str.w r3, [r1, #128] @ 0x80 } #endif /* Set HAL COMP handle state */ /* Note: Transition from state reset to state ready, */ /* otherwise (coming from state ready or busy) no state update. */ if (hcomp->State == HAL_COMP_STATE_RESET) 800768e: 687b ldr r3, [r7, #4] 8007690: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8007694: b2db uxtb r3, r3 8007696: 2b00 cmp r3, #0 8007698: d103 bne.n 80076a2 { hcomp->State = HAL_COMP_STATE_READY; 800769a: 687b ldr r3, [r7, #4] 800769c: 2201 movs r2, #1 800769e: f883 2025 strb.w r2, [r3, #37] @ 0x25 } } return status; 80076a2: 7ffb ldrb r3, [r7, #31] } 80076a4: 4618 mov r0, r3 80076a6: 3720 adds r7, #32 80076a8: 46bd mov sp, r7 80076aa: bd80 pop {r7, pc} 80076ac: f0e8cce1 .word 0xf0e8cce1 80076b0: 24000034 .word 0x24000034 80076b4: 053e2d63 .word 0x053e2d63 80076b8: 5800380c .word 0x5800380c 080076bc : * @brief Start the comparator. * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { 80076bc: b480 push {r7} 80076be: b085 sub sp, #20 80076c0: af00 add r7, sp, #0 80076c2: 6078 str r0, [r7, #4] __IO uint32_t wait_loop_index = 0UL; 80076c4: 2300 movs r3, #0 80076c6: 60bb str r3, [r7, #8] HAL_StatusTypeDef status = HAL_OK; 80076c8: 2300 movs r3, #0 80076ca: 73fb strb r3, [r7, #15] /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) 80076cc: 687b ldr r3, [r7, #4] 80076ce: 2b00 cmp r3, #0 80076d0: d102 bne.n 80076d8 { status = HAL_ERROR; 80076d2: 2301 movs r3, #1 80076d4: 73fb strb r3, [r7, #15] 80076d6: e030 b.n 800773a } else if(__HAL_COMP_IS_LOCKED(hcomp)) 80076d8: 687b ldr r3, [r7, #4] 80076da: 681b ldr r3, [r3, #0] 80076dc: 681b ldr r3, [r3, #0] 80076de: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80076e2: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80076e6: d102 bne.n 80076ee { status = HAL_ERROR; 80076e8: 2301 movs r3, #1 80076ea: 73fb strb r3, [r7, #15] 80076ec: e025 b.n 800773a else { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); if(hcomp->State == HAL_COMP_STATE_READY) 80076ee: 687b ldr r3, [r7, #4] 80076f0: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 80076f4: b2db uxtb r3, r3 80076f6: 2b01 cmp r3, #1 80076f8: d11d bne.n 8007736 { /* Enable the selected comparator */ SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN); 80076fa: 687b ldr r3, [r7, #4] 80076fc: 681b ldr r3, [r3, #0] 80076fe: 681a ldr r2, [r3, #0] 8007700: 687b ldr r3, [r7, #4] 8007702: 681b ldr r3, [r3, #0] 8007704: f042 0201 orr.w r2, r2, #1 8007708: 601a str r2, [r3, #0] /* Set HAL COMP handle state */ hcomp->State = HAL_COMP_STATE_BUSY; 800770a: 687b ldr r3, [r7, #4] 800770c: 2202 movs r2, #2 800770e: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Delay for COMP startup time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8007712: 4b0d ldr r3, [pc, #52] @ (8007748 ) 8007714: 681b ldr r3, [r3, #0] 8007716: 099b lsrs r3, r3, #6 8007718: 4a0c ldr r2, [pc, #48] @ (800774c ) 800771a: fba2 2303 umull r2, r3, r2, r3 800771e: 099b lsrs r3, r3, #6 8007720: 3301 adds r3, #1 8007722: 00db lsls r3, r3, #3 8007724: 60bb str r3, [r7, #8] while(wait_loop_index != 0UL) 8007726: e002 b.n 800772e { wait_loop_index--; 8007728: 68bb ldr r3, [r7, #8] 800772a: 3b01 subs r3, #1 800772c: 60bb str r3, [r7, #8] while(wait_loop_index != 0UL) 800772e: 68bb ldr r3, [r7, #8] 8007730: 2b00 cmp r3, #0 8007732: d1f9 bne.n 8007728 8007734: e001 b.n 800773a } } else { status = HAL_ERROR; 8007736: 2301 movs r3, #1 8007738: 73fb strb r3, [r7, #15] } } return status; 800773a: 7bfb ldrb r3, [r7, #15] } 800773c: 4618 mov r0, r3 800773e: 3714 adds r7, #20 8007740: 46bd mov sp, r7 8007742: f85d 7b04 ldr.w r7, [sp], #4 8007746: 4770 bx lr 8007748: 24000034 .word 0x24000034 800774c: 053e2d63 .word 0x053e2d63 08007750 : * @arg @ref COMP_OUTPUT_LEVEL_LOW * @arg @ref COMP_OUTPUT_LEVEL_HIGH * */ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) { 8007750: b480 push {r7} 8007752: b083 sub sp, #12 8007754: af00 add r7, sp, #0 8007756: 6078 str r0, [r7, #4] /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); if (hcomp->Instance == COMP1) 8007758: 687b ldr r3, [r7, #4] 800775a: 681b ldr r3, [r3, #0] 800775c: 4a09 ldr r2, [pc, #36] @ (8007784 ) 800775e: 4293 cmp r3, r2 8007760: d104 bne.n 800776c { return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL)); 8007762: 4b09 ldr r3, [pc, #36] @ (8007788 ) 8007764: 681b ldr r3, [r3, #0] 8007766: f003 0301 and.w r3, r3, #1 800776a: e004 b.n 8007776 } else { return (uint32_t)((READ_BIT(COMP12->SR, COMP_SR_C2VAL))>> 1UL); 800776c: 4b06 ldr r3, [pc, #24] @ (8007788 ) 800776e: 681b ldr r3, [r3, #0] 8007770: 085b lsrs r3, r3, #1 8007772: f003 0301 and.w r3, r3, #1 } } 8007776: 4618 mov r0, r3 8007778: 370c adds r7, #12 800777a: 46bd mov sp, r7 800777c: f85d 7b04 ldr.w r7, [sp], #4 8007780: 4770 bx lr 8007782: bf00 nop 8007784: 5800380c .word 0x5800380c 8007788: 58003800 .word 0x58003800 0800778c <__NVIC_SetPriorityGrouping>: { 800778c: b480 push {r7} 800778e: b085 sub sp, #20 8007790: af00 add r7, sp, #0 8007792: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8007794: 687b ldr r3, [r7, #4] 8007796: f003 0307 and.w r3, r3, #7 800779a: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 800779c: 4b0b ldr r3, [pc, #44] @ (80077cc <__NVIC_SetPriorityGrouping+0x40>) 800779e: 68db ldr r3, [r3, #12] 80077a0: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80077a2: 68ba ldr r2, [r7, #8] 80077a4: f64f 03ff movw r3, #63743 @ 0xf8ff 80077a8: 4013 ands r3, r2 80077aa: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80077ac: 68fb ldr r3, [r7, #12] 80077ae: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80077b0: 68bb ldr r3, [r7, #8] 80077b2: 431a orrs r2, r3 reg_value = (reg_value | 80077b4: 4b06 ldr r3, [pc, #24] @ (80077d0 <__NVIC_SetPriorityGrouping+0x44>) 80077b6: 4313 orrs r3, r2 80077b8: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80077ba: 4a04 ldr r2, [pc, #16] @ (80077cc <__NVIC_SetPriorityGrouping+0x40>) 80077bc: 68bb ldr r3, [r7, #8] 80077be: 60d3 str r3, [r2, #12] } 80077c0: bf00 nop 80077c2: 3714 adds r7, #20 80077c4: 46bd mov sp, r7 80077c6: f85d 7b04 ldr.w r7, [sp], #4 80077ca: 4770 bx lr 80077cc: e000ed00 .word 0xe000ed00 80077d0: 05fa0000 .word 0x05fa0000 080077d4 <__NVIC_GetPriorityGrouping>: { 80077d4: b480 push {r7} 80077d6: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80077d8: 4b04 ldr r3, [pc, #16] @ (80077ec <__NVIC_GetPriorityGrouping+0x18>) 80077da: 68db ldr r3, [r3, #12] 80077dc: 0a1b lsrs r3, r3, #8 80077de: f003 0307 and.w r3, r3, #7 } 80077e2: 4618 mov r0, r3 80077e4: 46bd mov sp, r7 80077e6: f85d 7b04 ldr.w r7, [sp], #4 80077ea: 4770 bx lr 80077ec: e000ed00 .word 0xe000ed00 080077f0 <__NVIC_EnableIRQ>: { 80077f0: b480 push {r7} 80077f2: b083 sub sp, #12 80077f4: af00 add r7, sp, #0 80077f6: 4603 mov r3, r0 80077f8: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 80077fa: f9b7 3006 ldrsh.w r3, [r7, #6] 80077fe: 2b00 cmp r3, #0 8007800: db0b blt.n 800781a <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8007802: 88fb ldrh r3, [r7, #6] 8007804: f003 021f and.w r2, r3, #31 8007808: 4907 ldr r1, [pc, #28] @ (8007828 <__NVIC_EnableIRQ+0x38>) 800780a: f9b7 3006 ldrsh.w r3, [r7, #6] 800780e: 095b lsrs r3, r3, #5 8007810: 2001 movs r0, #1 8007812: fa00 f202 lsl.w r2, r0, r2 8007816: f841 2023 str.w r2, [r1, r3, lsl #2] } 800781a: bf00 nop 800781c: 370c adds r7, #12 800781e: 46bd mov sp, r7 8007820: f85d 7b04 ldr.w r7, [sp], #4 8007824: 4770 bx lr 8007826: bf00 nop 8007828: e000e100 .word 0xe000e100 0800782c <__NVIC_SetPriority>: { 800782c: b480 push {r7} 800782e: b083 sub sp, #12 8007830: af00 add r7, sp, #0 8007832: 4603 mov r3, r0 8007834: 6039 str r1, [r7, #0] 8007836: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8007838: f9b7 3006 ldrsh.w r3, [r7, #6] 800783c: 2b00 cmp r3, #0 800783e: db0a blt.n 8007856 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8007840: 683b ldr r3, [r7, #0] 8007842: b2da uxtb r2, r3 8007844: 490c ldr r1, [pc, #48] @ (8007878 <__NVIC_SetPriority+0x4c>) 8007846: f9b7 3006 ldrsh.w r3, [r7, #6] 800784a: 0112 lsls r2, r2, #4 800784c: b2d2 uxtb r2, r2 800784e: 440b add r3, r1 8007850: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 8007854: e00a b.n 800786c <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8007856: 683b ldr r3, [r7, #0] 8007858: b2da uxtb r2, r3 800785a: 4908 ldr r1, [pc, #32] @ (800787c <__NVIC_SetPriority+0x50>) 800785c: 88fb ldrh r3, [r7, #6] 800785e: f003 030f and.w r3, r3, #15 8007862: 3b04 subs r3, #4 8007864: 0112 lsls r2, r2, #4 8007866: b2d2 uxtb r2, r2 8007868: 440b add r3, r1 800786a: 761a strb r2, [r3, #24] } 800786c: bf00 nop 800786e: 370c adds r7, #12 8007870: 46bd mov sp, r7 8007872: f85d 7b04 ldr.w r7, [sp], #4 8007876: 4770 bx lr 8007878: e000e100 .word 0xe000e100 800787c: e000ed00 .word 0xe000ed00 08007880 : { 8007880: b480 push {r7} 8007882: b089 sub sp, #36 @ 0x24 8007884: af00 add r7, sp, #0 8007886: 60f8 str r0, [r7, #12] 8007888: 60b9 str r1, [r7, #8] 800788a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800788c: 68fb ldr r3, [r7, #12] 800788e: f003 0307 and.w r3, r3, #7 8007892: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8007894: 69fb ldr r3, [r7, #28] 8007896: f1c3 0307 rsb r3, r3, #7 800789a: 2b04 cmp r3, #4 800789c: bf28 it cs 800789e: 2304 movcs r3, #4 80078a0: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80078a2: 69fb ldr r3, [r7, #28] 80078a4: 3304 adds r3, #4 80078a6: 2b06 cmp r3, #6 80078a8: d902 bls.n 80078b0 80078aa: 69fb ldr r3, [r7, #28] 80078ac: 3b03 subs r3, #3 80078ae: e000 b.n 80078b2 80078b0: 2300 movs r3, #0 80078b2: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80078b4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80078b8: 69bb ldr r3, [r7, #24] 80078ba: fa02 f303 lsl.w r3, r2, r3 80078be: 43da mvns r2, r3 80078c0: 68bb ldr r3, [r7, #8] 80078c2: 401a ands r2, r3 80078c4: 697b ldr r3, [r7, #20] 80078c6: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80078c8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80078cc: 697b ldr r3, [r7, #20] 80078ce: fa01 f303 lsl.w r3, r1, r3 80078d2: 43d9 mvns r1, r3 80078d4: 687b ldr r3, [r7, #4] 80078d6: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80078d8: 4313 orrs r3, r2 } 80078da: 4618 mov r0, r3 80078dc: 3724 adds r7, #36 @ 0x24 80078de: 46bd mov sp, r7 80078e0: f85d 7b04 ldr.w r7, [sp], #4 80078e4: 4770 bx lr 080078e6 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80078e6: b580 push {r7, lr} 80078e8: b082 sub sp, #8 80078ea: af00 add r7, sp, #0 80078ec: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80078ee: 6878 ldr r0, [r7, #4] 80078f0: f7ff ff4c bl 800778c <__NVIC_SetPriorityGrouping> } 80078f4: bf00 nop 80078f6: 3708 adds r7, #8 80078f8: 46bd mov sp, r7 80078fa: bd80 pop {r7, pc} 080078fc : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80078fc: b580 push {r7, lr} 80078fe: b086 sub sp, #24 8007900: af00 add r7, sp, #0 8007902: 4603 mov r3, r0 8007904: 60b9 str r1, [r7, #8] 8007906: 607a str r2, [r7, #4] 8007908: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800790a: f7ff ff63 bl 80077d4 <__NVIC_GetPriorityGrouping> 800790e: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8007910: 687a ldr r2, [r7, #4] 8007912: 68b9 ldr r1, [r7, #8] 8007914: 6978 ldr r0, [r7, #20] 8007916: f7ff ffb3 bl 8007880 800791a: 4602 mov r2, r0 800791c: f9b7 300e ldrsh.w r3, [r7, #14] 8007920: 4611 mov r1, r2 8007922: 4618 mov r0, r3 8007924: f7ff ff82 bl 800782c <__NVIC_SetPriority> } 8007928: bf00 nop 800792a: 3718 adds r7, #24 800792c: 46bd mov sp, r7 800792e: bd80 pop {r7, pc} 08007930 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8007930: b580 push {r7, lr} 8007932: b082 sub sp, #8 8007934: af00 add r7, sp, #0 8007936: 4603 mov r3, r0 8007938: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800793a: f9b7 3006 ldrsh.w r3, [r7, #6] 800793e: 4618 mov r0, r3 8007940: f7ff ff56 bl 80077f0 <__NVIC_EnableIRQ> } 8007944: bf00 nop 8007946: 3708 adds r7, #8 8007948: 46bd mov sp, r7 800794a: bd80 pop {r7, pc} 0800794c : /** * @brief Disables the MPU * @retval None */ void HAL_MPU_Disable(void) { 800794c: b480 push {r7} 800794e: af00 add r7, sp, #0 __ASM volatile ("dmb 0xF":::"memory"); 8007950: f3bf 8f5f dmb sy } 8007954: bf00 nop /* Make sure outstanding transfers are done */ __DMB(); /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 8007956: 4b07 ldr r3, [pc, #28] @ (8007974 ) 8007958: 6a5b ldr r3, [r3, #36] @ 0x24 800795a: 4a06 ldr r2, [pc, #24] @ (8007974 ) 800795c: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8007960: 6253 str r3, [r2, #36] @ 0x24 /* Disable the MPU and clear the control register*/ MPU->CTRL = 0; 8007962: 4b05 ldr r3, [pc, #20] @ (8007978 ) 8007964: 2200 movs r2, #0 8007966: 605a str r2, [r3, #4] } 8007968: bf00 nop 800796a: 46bd mov sp, r7 800796c: f85d 7b04 ldr.w r7, [sp], #4 8007970: 4770 bx lr 8007972: bf00 nop 8007974: e000ed00 .word 0xe000ed00 8007978: e000ed90 .word 0xe000ed90 0800797c : * @arg MPU_PRIVILEGED_DEFAULT * @arg MPU_HFNMI_PRIVDEF * @retval None */ void HAL_MPU_Enable(uint32_t MPU_Control) { 800797c: b480 push {r7} 800797e: b083 sub sp, #12 8007980: af00 add r7, sp, #0 8007982: 6078 str r0, [r7, #4] /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 8007984: 4a0b ldr r2, [pc, #44] @ (80079b4 ) 8007986: 687b ldr r3, [r7, #4] 8007988: f043 0301 orr.w r3, r3, #1 800798c: 6053 str r3, [r2, #4] /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 800798e: 4b0a ldr r3, [pc, #40] @ (80079b8 ) 8007990: 6a5b ldr r3, [r3, #36] @ 0x24 8007992: 4a09 ldr r2, [pc, #36] @ (80079b8 ) 8007994: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8007998: 6253 str r3, [r2, #36] @ 0x24 __ASM volatile ("dsb 0xF":::"memory"); 800799a: f3bf 8f4f dsb sy } 800799e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80079a0: f3bf 8f6f isb sy } 80079a4: bf00 nop /* Ensure MPU setting take effects */ __DSB(); __ISB(); } 80079a6: bf00 nop 80079a8: 370c adds r7, #12 80079aa: 46bd mov sp, r7 80079ac: f85d 7b04 ldr.w r7, [sp], #4 80079b0: 4770 bx lr 80079b2: bf00 nop 80079b4: e000ed90 .word 0xe000ed90 80079b8: e000ed00 .word 0xe000ed00 080079bc : * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) { 80079bc: b480 push {r7} 80079be: b083 sub sp, #12 80079c0: af00 add r7, sp, #0 80079c2: 6078 str r0, [r7, #4] assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; 80079c4: 687b ldr r3, [r7, #4] 80079c6: 785a ldrb r2, [r3, #1] 80079c8: 4b1b ldr r3, [pc, #108] @ (8007a38 ) 80079ca: 609a str r2, [r3, #8] /* Disable the Region */ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 80079cc: 4b1a ldr r3, [pc, #104] @ (8007a38 ) 80079ce: 691b ldr r3, [r3, #16] 80079d0: 4a19 ldr r2, [pc, #100] @ (8007a38 ) 80079d2: f023 0301 bic.w r3, r3, #1 80079d6: 6113 str r3, [r2, #16] /* Apply configuration */ MPU->RBAR = MPU_Init->BaseAddress; 80079d8: 4a17 ldr r2, [pc, #92] @ (8007a38 ) 80079da: 687b ldr r3, [r7, #4] 80079dc: 685b ldr r3, [r3, #4] 80079de: 60d3 str r3, [r2, #12] MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 80079e0: 687b ldr r3, [r7, #4] 80079e2: 7b1b ldrb r3, [r3, #12] 80079e4: 071a lsls r2, r3, #28 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 80079e6: 687b ldr r3, [r7, #4] 80079e8: 7adb ldrb r3, [r3, #11] 80079ea: 061b lsls r3, r3, #24 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 80079ec: 431a orrs r2, r3 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 80079ee: 687b ldr r3, [r7, #4] 80079f0: 7a9b ldrb r3, [r3, #10] 80079f2: 04db lsls r3, r3, #19 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 80079f4: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 80079f6: 687b ldr r3, [r7, #4] 80079f8: 7b5b ldrb r3, [r3, #13] 80079fa: 049b lsls r3, r3, #18 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 80079fc: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 80079fe: 687b ldr r3, [r7, #4] 8007a00: 7b9b ldrb r3, [r3, #14] 8007a02: 045b lsls r3, r3, #17 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8007a04: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8007a06: 687b ldr r3, [r7, #4] 8007a08: 7bdb ldrb r3, [r3, #15] 8007a0a: 041b lsls r3, r3, #16 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 8007a0c: 431a orrs r2, r3 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 8007a0e: 687b ldr r3, [r7, #4] 8007a10: 7a5b ldrb r3, [r3, #9] 8007a12: 021b lsls r3, r3, #8 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8007a14: 431a orrs r2, r3 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8007a16: 687b ldr r3, [r7, #4] 8007a18: 7a1b ldrb r3, [r3, #8] 8007a1a: 005b lsls r3, r3, #1 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 8007a1c: 4313 orrs r3, r2 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); 8007a1e: 687a ldr r2, [r7, #4] 8007a20: 7812 ldrb r2, [r2, #0] 8007a22: 4611 mov r1, r2 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007a24: 4a04 ldr r2, [pc, #16] @ (8007a38 ) ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8007a26: 430b orrs r3, r1 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007a28: 6113 str r3, [r2, #16] } 8007a2a: bf00 nop 8007a2c: 370c adds r7, #12 8007a2e: 46bd mov sp, r7 8007a30: f85d 7b04 ldr.w r7, [sp], #4 8007a34: 4770 bx lr 8007a36: bf00 nop 8007a38: e000ed90 .word 0xe000ed90 08007a3c : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 8007a3c: b580 push {r7, lr} 8007a3e: b082 sub sp, #8 8007a40: af00 add r7, sp, #0 8007a42: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 8007a44: 687b ldr r3, [r7, #4] 8007a46: 2b00 cmp r3, #0 8007a48: d101 bne.n 8007a4e { return HAL_ERROR; 8007a4a: 2301 movs r3, #1 8007a4c: e054 b.n 8007af8 } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 8007a4e: 687b ldr r3, [r7, #4] 8007a50: 7f5b ldrb r3, [r3, #29] 8007a52: b2db uxtb r3, r3 8007a54: 2b00 cmp r3, #0 8007a56: d105 bne.n 8007a64 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 8007a58: 687b ldr r3, [r7, #4] 8007a5a: 2200 movs r2, #0 8007a5c: 771a strb r2, [r3, #28] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 8007a5e: 6878 ldr r0, [r7, #4] 8007a60: f7fc faba bl 8003fd8 } hcrc->State = HAL_CRC_STATE_BUSY; 8007a64: 687b ldr r3, [r7, #4] 8007a66: 2202 movs r2, #2 8007a68: 775a strb r2, [r3, #29] /* check whether or not non-default generating polynomial has been * picked up by user */ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) 8007a6a: 687b ldr r3, [r7, #4] 8007a6c: 791b ldrb r3, [r3, #4] 8007a6e: 2b00 cmp r3, #0 8007a70: d10c bne.n 8007a8c { /* initialize peripheral with default generating polynomial */ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); 8007a72: 687b ldr r3, [r7, #4] 8007a74: 681b ldr r3, [r3, #0] 8007a76: 4a22 ldr r2, [pc, #136] @ (8007b00 ) 8007a78: 615a str r2, [r3, #20] MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); 8007a7a: 687b ldr r3, [r7, #4] 8007a7c: 681b ldr r3, [r3, #0] 8007a7e: 689a ldr r2, [r3, #8] 8007a80: 687b ldr r3, [r7, #4] 8007a82: 681b ldr r3, [r3, #0] 8007a84: f022 0218 bic.w r2, r2, #24 8007a88: 609a str r2, [r3, #8] 8007a8a: e00c b.n 8007aa6 } else { /* initialize CRC peripheral with generating polynomial defined by user */ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) 8007a8c: 687b ldr r3, [r7, #4] 8007a8e: 6899 ldr r1, [r3, #8] 8007a90: 687b ldr r3, [r7, #4] 8007a92: 68db ldr r3, [r3, #12] 8007a94: 461a mov r2, r3 8007a96: 6878 ldr r0, [r7, #4] 8007a98: f000 f948 bl 8007d2c 8007a9c: 4603 mov r3, r0 8007a9e: 2b00 cmp r3, #0 8007aa0: d001 beq.n 8007aa6 { return HAL_ERROR; 8007aa2: 2301 movs r3, #1 8007aa4: e028 b.n 8007af8 } /* check whether or not non-default CRC initial value has been * picked up by user */ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) 8007aa6: 687b ldr r3, [r7, #4] 8007aa8: 795b ldrb r3, [r3, #5] 8007aaa: 2b00 cmp r3, #0 8007aac: d105 bne.n 8007aba { WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); 8007aae: 687b ldr r3, [r7, #4] 8007ab0: 681b ldr r3, [r3, #0] 8007ab2: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007ab6: 611a str r2, [r3, #16] 8007ab8: e004 b.n 8007ac4 } else { WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); 8007aba: 687b ldr r3, [r7, #4] 8007abc: 681b ldr r3, [r3, #0] 8007abe: 687a ldr r2, [r7, #4] 8007ac0: 6912 ldr r2, [r2, #16] 8007ac2: 611a str r2, [r3, #16] } /* set input data inversion mode */ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); 8007ac4: 687b ldr r3, [r7, #4] 8007ac6: 681b ldr r3, [r3, #0] 8007ac8: 689b ldr r3, [r3, #8] 8007aca: f023 0160 bic.w r1, r3, #96 @ 0x60 8007ace: 687b ldr r3, [r7, #4] 8007ad0: 695a ldr r2, [r3, #20] 8007ad2: 687b ldr r3, [r7, #4] 8007ad4: 681b ldr r3, [r3, #0] 8007ad6: 430a orrs r2, r1 8007ad8: 609a str r2, [r3, #8] /* set output data inversion mode */ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); 8007ada: 687b ldr r3, [r7, #4] 8007adc: 681b ldr r3, [r3, #0] 8007ade: 689b ldr r3, [r3, #8] 8007ae0: f023 0180 bic.w r1, r3, #128 @ 0x80 8007ae4: 687b ldr r3, [r7, #4] 8007ae6: 699a ldr r2, [r3, #24] 8007ae8: 687b ldr r3, [r7, #4] 8007aea: 681b ldr r3, [r3, #0] 8007aec: 430a orrs r2, r1 8007aee: 609a str r2, [r3, #8] /* makes sure the input data format (bytes, halfwords or words stream) * is properly specified by user */ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 8007af0: 687b ldr r3, [r7, #4] 8007af2: 2201 movs r2, #1 8007af4: 775a strb r2, [r3, #29] /* Return function status */ return HAL_OK; 8007af6: 2300 movs r3, #0 } 8007af8: 4618 mov r0, r3 8007afa: 3708 adds r7, #8 8007afc: 46bd mov sp, r7 8007afe: bd80 pop {r7, pc} 8007b00: 04c11db7 .word 0x04c11db7 08007b04 : * and the API will internally adjust its input data processing based on the * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { 8007b04: b580 push {r7, lr} 8007b06: b086 sub sp, #24 8007b08: af00 add r7, sp, #0 8007b0a: 60f8 str r0, [r7, #12] 8007b0c: 60b9 str r1, [r7, #8] 8007b0e: 607a str r2, [r7, #4] uint32_t index; /* CRC input data buffer index */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ 8007b10: 2300 movs r3, #0 8007b12: 613b str r3, [r7, #16] /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; 8007b14: 68fb ldr r3, [r7, #12] 8007b16: 2202 movs r2, #2 8007b18: 775a strb r2, [r3, #29] /* Reset CRC Calculation Unit (hcrc->Instance->INIT is * written in hcrc->Instance->DR) */ __HAL_CRC_DR_RESET(hcrc); 8007b1a: 68fb ldr r3, [r7, #12] 8007b1c: 681b ldr r3, [r3, #0] 8007b1e: 689a ldr r2, [r3, #8] 8007b20: 68fb ldr r3, [r7, #12] 8007b22: 681b ldr r3, [r3, #0] 8007b24: f042 0201 orr.w r2, r2, #1 8007b28: 609a str r2, [r3, #8] switch (hcrc->InputDataFormat) 8007b2a: 68fb ldr r3, [r7, #12] 8007b2c: 6a1b ldr r3, [r3, #32] 8007b2e: 2b03 cmp r3, #3 8007b30: d006 beq.n 8007b40 8007b32: 2b03 cmp r3, #3 8007b34: d829 bhi.n 8007b8a 8007b36: 2b01 cmp r3, #1 8007b38: d019 beq.n 8007b6e 8007b3a: 2b02 cmp r3, #2 8007b3c: d01e beq.n 8007b7c /* Specific 16-bit input data handling */ temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: break; 8007b3e: e024 b.n 8007b8a for (index = 0U; index < BufferLength; index++) 8007b40: 2300 movs r3, #0 8007b42: 617b str r3, [r7, #20] 8007b44: e00a b.n 8007b5c hcrc->Instance->DR = pBuffer[index]; 8007b46: 697b ldr r3, [r7, #20] 8007b48: 009b lsls r3, r3, #2 8007b4a: 68ba ldr r2, [r7, #8] 8007b4c: 441a add r2, r3 8007b4e: 68fb ldr r3, [r7, #12] 8007b50: 681b ldr r3, [r3, #0] 8007b52: 6812 ldr r2, [r2, #0] 8007b54: 601a str r2, [r3, #0] for (index = 0U; index < BufferLength; index++) 8007b56: 697b ldr r3, [r7, #20] 8007b58: 3301 adds r3, #1 8007b5a: 617b str r3, [r7, #20] 8007b5c: 697a ldr r2, [r7, #20] 8007b5e: 687b ldr r3, [r7, #4] 8007b60: 429a cmp r2, r3 8007b62: d3f0 bcc.n 8007b46 temp = hcrc->Instance->DR; 8007b64: 68fb ldr r3, [r7, #12] 8007b66: 681b ldr r3, [r3, #0] 8007b68: 681b ldr r3, [r3, #0] 8007b6a: 613b str r3, [r7, #16] break; 8007b6c: e00e b.n 8007b8c temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); 8007b6e: 687a ldr r2, [r7, #4] 8007b70: 68b9 ldr r1, [r7, #8] 8007b72: 68f8 ldr r0, [r7, #12] 8007b74: f000 f812 bl 8007b9c 8007b78: 6138 str r0, [r7, #16] break; 8007b7a: e007 b.n 8007b8c temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ 8007b7c: 687a ldr r2, [r7, #4] 8007b7e: 68b9 ldr r1, [r7, #8] 8007b80: 68f8 ldr r0, [r7, #12] 8007b82: f000 f899 bl 8007cb8 8007b86: 6138 str r0, [r7, #16] break; 8007b88: e000 b.n 8007b8c break; 8007b8a: bf00 nop } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 8007b8c: 68fb ldr r3, [r7, #12] 8007b8e: 2201 movs r2, #1 8007b90: 775a strb r2, [r3, #29] /* Return the CRC computed value */ return temp; 8007b92: 693b ldr r3, [r7, #16] } 8007b94: 4618 mov r0, r3 8007b96: 3718 adds r7, #24 8007b98: 46bd mov sp, r7 8007b9a: bd80 pop {r7, pc} 08007b9c : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { 8007b9c: b480 push {r7} 8007b9e: b089 sub sp, #36 @ 0x24 8007ba0: af00 add r7, sp, #0 8007ba2: 60f8 str r0, [r7, #12] 8007ba4: 60b9 str r1, [r7, #8] 8007ba6: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 4 bytes are entered in a row with a single word write, * last bytes must be carefully fed to the CRC calculator to ensure a correct type * handling by the peripheral */ for (i = 0U; i < (BufferLength / 4U); i++) 8007ba8: 2300 movs r3, #0 8007baa: 61fb str r3, [r7, #28] 8007bac: e023 b.n 8007bf6 { hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007bae: 69fb ldr r3, [r7, #28] 8007bb0: 009b lsls r3, r3, #2 8007bb2: 68ba ldr r2, [r7, #8] 8007bb4: 4413 add r3, r2 8007bb6: 781b ldrb r3, [r3, #0] 8007bb8: 061a lsls r2, r3, #24 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8007bba: 69fb ldr r3, [r7, #28] 8007bbc: 009b lsls r3, r3, #2 8007bbe: 3301 adds r3, #1 8007bc0: 68b9 ldr r1, [r7, #8] 8007bc2: 440b add r3, r1 8007bc4: 781b ldrb r3, [r3, #0] 8007bc6: 041b lsls r3, r3, #16 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007bc8: 431a orrs r2, r3 ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 8007bca: 69fb ldr r3, [r7, #28] 8007bcc: 009b lsls r3, r3, #2 8007bce: 3302 adds r3, #2 8007bd0: 68b9 ldr r1, [r7, #8] 8007bd2: 440b add r3, r1 8007bd4: 781b ldrb r3, [r3, #0] 8007bd6: 021b lsls r3, r3, #8 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8007bd8: 431a orrs r2, r3 (uint32_t)pBuffer[(4U * i) + 3U]; 8007bda: 69fb ldr r3, [r7, #28] 8007bdc: 009b lsls r3, r3, #2 8007bde: 3303 adds r3, #3 8007be0: 68b9 ldr r1, [r7, #8] 8007be2: 440b add r3, r1 8007be4: 781b ldrb r3, [r3, #0] 8007be6: 4619 mov r1, r3 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007be8: 68fb ldr r3, [r7, #12] 8007bea: 681b ldr r3, [r3, #0] ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 8007bec: 430a orrs r2, r1 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007bee: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 4U); i++) 8007bf0: 69fb ldr r3, [r7, #28] 8007bf2: 3301 adds r3, #1 8007bf4: 61fb str r3, [r7, #28] 8007bf6: 687b ldr r3, [r7, #4] 8007bf8: 089b lsrs r3, r3, #2 8007bfa: 69fa ldr r2, [r7, #28] 8007bfc: 429a cmp r2, r3 8007bfe: d3d6 bcc.n 8007bae } /* last bytes specific handling */ if ((BufferLength % 4U) != 0U) 8007c00: 687b ldr r3, [r7, #4] 8007c02: f003 0303 and.w r3, r3, #3 8007c06: 2b00 cmp r3, #0 8007c08: d04d beq.n 8007ca6 { if ((BufferLength % 4U) == 1U) 8007c0a: 687b ldr r3, [r7, #4] 8007c0c: f003 0303 and.w r3, r3, #3 8007c10: 2b01 cmp r3, #1 8007c12: d107 bne.n 8007c24 { *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ 8007c14: 69fb ldr r3, [r7, #28] 8007c16: 009b lsls r3, r3, #2 8007c18: 68ba ldr r2, [r7, #8] 8007c1a: 4413 add r3, r2 8007c1c: 68fa ldr r2, [r7, #12] 8007c1e: 6812 ldr r2, [r2, #0] 8007c20: 781b ldrb r3, [r3, #0] 8007c22: 7013 strb r3, [r2, #0] } if ((BufferLength % 4U) == 2U) 8007c24: 687b ldr r3, [r7, #4] 8007c26: f003 0303 and.w r3, r3, #3 8007c2a: 2b02 cmp r3, #2 8007c2c: d116 bne.n 8007c5c { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 8007c2e: 69fb ldr r3, [r7, #28] 8007c30: 009b lsls r3, r3, #2 8007c32: 68ba ldr r2, [r7, #8] 8007c34: 4413 add r3, r2 8007c36: 781b ldrb r3, [r3, #0] 8007c38: 021b lsls r3, r3, #8 8007c3a: b21a sxth r2, r3 8007c3c: 69fb ldr r3, [r7, #28] 8007c3e: 009b lsls r3, r3, #2 8007c40: 3301 adds r3, #1 8007c42: 68b9 ldr r1, [r7, #8] 8007c44: 440b add r3, r1 8007c46: 781b ldrb r3, [r3, #0] 8007c48: b21b sxth r3, r3 8007c4a: 4313 orrs r3, r2 8007c4c: b21b sxth r3, r3 8007c4e: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007c50: 68fb ldr r3, [r7, #12] 8007c52: 681b ldr r3, [r3, #0] 8007c54: 617b str r3, [r7, #20] *pReg = data; 8007c56: 697b ldr r3, [r7, #20] 8007c58: 8b7a ldrh r2, [r7, #26] 8007c5a: 801a strh r2, [r3, #0] } if ((BufferLength % 4U) == 3U) 8007c5c: 687b ldr r3, [r7, #4] 8007c5e: f003 0303 and.w r3, r3, #3 8007c62: 2b03 cmp r3, #3 8007c64: d11f bne.n 8007ca6 { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 8007c66: 69fb ldr r3, [r7, #28] 8007c68: 009b lsls r3, r3, #2 8007c6a: 68ba ldr r2, [r7, #8] 8007c6c: 4413 add r3, r2 8007c6e: 781b ldrb r3, [r3, #0] 8007c70: 021b lsls r3, r3, #8 8007c72: b21a sxth r2, r3 8007c74: 69fb ldr r3, [r7, #28] 8007c76: 009b lsls r3, r3, #2 8007c78: 3301 adds r3, #1 8007c7a: 68b9 ldr r1, [r7, #8] 8007c7c: 440b add r3, r1 8007c7e: 781b ldrb r3, [r3, #0] 8007c80: b21b sxth r3, r3 8007c82: 4313 orrs r3, r2 8007c84: b21b sxth r3, r3 8007c86: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007c88: 68fb ldr r3, [r7, #12] 8007c8a: 681b ldr r3, [r3, #0] 8007c8c: 617b str r3, [r7, #20] *pReg = data; 8007c8e: 697b ldr r3, [r7, #20] 8007c90: 8b7a ldrh r2, [r7, #26] 8007c92: 801a strh r2, [r3, #0] *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ 8007c94: 69fb ldr r3, [r7, #28] 8007c96: 009b lsls r3, r3, #2 8007c98: 3302 adds r3, #2 8007c9a: 68ba ldr r2, [r7, #8] 8007c9c: 4413 add r3, r2 8007c9e: 68fa ldr r2, [r7, #12] 8007ca0: 6812 ldr r2, [r2, #0] 8007ca2: 781b ldrb r3, [r3, #0] 8007ca4: 7013 strb r3, [r2, #0] } } /* Return the CRC computed value */ return hcrc->Instance->DR; 8007ca6: 68fb ldr r3, [r7, #12] 8007ca8: 681b ldr r3, [r3, #0] 8007caa: 681b ldr r3, [r3, #0] } 8007cac: 4618 mov r0, r3 8007cae: 3724 adds r7, #36 @ 0x24 8007cb0: 46bd mov sp, r7 8007cb2: f85d 7b04 ldr.w r7, [sp], #4 8007cb6: 4770 bx lr 08007cb8 : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { 8007cb8: b480 push {r7} 8007cba: b087 sub sp, #28 8007cbc: af00 add r7, sp, #0 8007cbe: 60f8 str r0, [r7, #12] 8007cc0: 60b9 str r1, [r7, #8] 8007cc2: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the peripheral */ for (i = 0U; i < (BufferLength / 2U); i++) 8007cc4: 2300 movs r3, #0 8007cc6: 617b str r3, [r7, #20] 8007cc8: e013 b.n 8007cf2 { hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; 8007cca: 697b ldr r3, [r7, #20] 8007ccc: 009b lsls r3, r3, #2 8007cce: 68ba ldr r2, [r7, #8] 8007cd0: 4413 add r3, r2 8007cd2: 881b ldrh r3, [r3, #0] 8007cd4: 041a lsls r2, r3, #16 8007cd6: 697b ldr r3, [r7, #20] 8007cd8: 009b lsls r3, r3, #2 8007cda: 3302 adds r3, #2 8007cdc: 68b9 ldr r1, [r7, #8] 8007cde: 440b add r3, r1 8007ce0: 881b ldrh r3, [r3, #0] 8007ce2: 4619 mov r1, r3 8007ce4: 68fb ldr r3, [r7, #12] 8007ce6: 681b ldr r3, [r3, #0] 8007ce8: 430a orrs r2, r1 8007cea: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 2U); i++) 8007cec: 697b ldr r3, [r7, #20] 8007cee: 3301 adds r3, #1 8007cf0: 617b str r3, [r7, #20] 8007cf2: 687b ldr r3, [r7, #4] 8007cf4: 085b lsrs r3, r3, #1 8007cf6: 697a ldr r2, [r7, #20] 8007cf8: 429a cmp r2, r3 8007cfa: d3e6 bcc.n 8007cca } if ((BufferLength % 2U) != 0U) 8007cfc: 687b ldr r3, [r7, #4] 8007cfe: f003 0301 and.w r3, r3, #1 8007d02: 2b00 cmp r3, #0 8007d04: d009 beq.n 8007d1a { pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007d06: 68fb ldr r3, [r7, #12] 8007d08: 681b ldr r3, [r3, #0] 8007d0a: 613b str r3, [r7, #16] *pReg = pBuffer[2U * i]; 8007d0c: 697b ldr r3, [r7, #20] 8007d0e: 009b lsls r3, r3, #2 8007d10: 68ba ldr r2, [r7, #8] 8007d12: 4413 add r3, r2 8007d14: 881a ldrh r2, [r3, #0] 8007d16: 693b ldr r3, [r7, #16] 8007d18: 801a strh r2, [r3, #0] } /* Return the CRC computed value */ return hcrc->Instance->DR; 8007d1a: 68fb ldr r3, [r7, #12] 8007d1c: 681b ldr r3, [r3, #0] 8007d1e: 681b ldr r3, [r3, #0] } 8007d20: 4618 mov r0, r3 8007d22: 371c adds r7, #28 8007d24: 46bd mov sp, r7 8007d26: f85d 7b04 ldr.w r7, [sp], #4 8007d2a: 4770 bx lr 08007d2c : * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) { 8007d2c: b480 push {r7} 8007d2e: b087 sub sp, #28 8007d30: af00 add r7, sp, #0 8007d32: 60f8 str r0, [r7, #12] 8007d34: 60b9 str r1, [r7, #8] 8007d36: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8007d38: 2300 movs r3, #0 8007d3a: 75fb strb r3, [r7, #23] uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ 8007d3c: 231f movs r3, #31 8007d3e: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); /* Ensure that the generating polynomial is odd */ if ((Pol & (uint32_t)(0x1U)) == 0U) 8007d40: 68bb ldr r3, [r7, #8] 8007d42: f003 0301 and.w r3, r3, #1 8007d46: 2b00 cmp r3, #0 8007d48: d102 bne.n 8007d50 { status = HAL_ERROR; 8007d4a: 2301 movs r3, #1 8007d4c: 75fb strb r3, [r7, #23] 8007d4e: e063 b.n 8007e18 * definition. HAL_ERROR is reported if Pol degree is * larger than that indicated by PolyLength. * Look for MSB position: msb will contain the degree of * the second to the largest polynomial member. E.g., for * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) 8007d50: bf00 nop 8007d52: 693b ldr r3, [r7, #16] 8007d54: 1e5a subs r2, r3, #1 8007d56: 613a str r2, [r7, #16] 8007d58: 2b00 cmp r3, #0 8007d5a: d009 beq.n 8007d70 8007d5c: 693b ldr r3, [r7, #16] 8007d5e: f003 031f and.w r3, r3, #31 8007d62: 68ba ldr r2, [r7, #8] 8007d64: fa22 f303 lsr.w r3, r2, r3 8007d68: f003 0301 and.w r3, r3, #1 8007d6c: 2b00 cmp r3, #0 8007d6e: d0f0 beq.n 8007d52 { } switch (PolyLength) 8007d70: 687b ldr r3, [r7, #4] 8007d72: 2b18 cmp r3, #24 8007d74: d846 bhi.n 8007e04 8007d76: a201 add r2, pc, #4 @ (adr r2, 8007d7c ) 8007d78: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007d7c: 08007e0b .word 0x08007e0b 8007d80: 08007e05 .word 0x08007e05 8007d84: 08007e05 .word 0x08007e05 8007d88: 08007e05 .word 0x08007e05 8007d8c: 08007e05 .word 0x08007e05 8007d90: 08007e05 .word 0x08007e05 8007d94: 08007e05 .word 0x08007e05 8007d98: 08007e05 .word 0x08007e05 8007d9c: 08007df9 .word 0x08007df9 8007da0: 08007e05 .word 0x08007e05 8007da4: 08007e05 .word 0x08007e05 8007da8: 08007e05 .word 0x08007e05 8007dac: 08007e05 .word 0x08007e05 8007db0: 08007e05 .word 0x08007e05 8007db4: 08007e05 .word 0x08007e05 8007db8: 08007e05 .word 0x08007e05 8007dbc: 08007ded .word 0x08007ded 8007dc0: 08007e05 .word 0x08007e05 8007dc4: 08007e05 .word 0x08007e05 8007dc8: 08007e05 .word 0x08007e05 8007dcc: 08007e05 .word 0x08007e05 8007dd0: 08007e05 .word 0x08007e05 8007dd4: 08007e05 .word 0x08007e05 8007dd8: 08007e05 .word 0x08007e05 8007ddc: 08007de1 .word 0x08007de1 { case CRC_POLYLENGTH_7B: if (msb >= HAL_CRC_LENGTH_7B) 8007de0: 693b ldr r3, [r7, #16] 8007de2: 2b06 cmp r3, #6 8007de4: d913 bls.n 8007e0e { status = HAL_ERROR; 8007de6: 2301 movs r3, #1 8007de8: 75fb strb r3, [r7, #23] } break; 8007dea: e010 b.n 8007e0e case CRC_POLYLENGTH_8B: if (msb >= HAL_CRC_LENGTH_8B) 8007dec: 693b ldr r3, [r7, #16] 8007dee: 2b07 cmp r3, #7 8007df0: d90f bls.n 8007e12 { status = HAL_ERROR; 8007df2: 2301 movs r3, #1 8007df4: 75fb strb r3, [r7, #23] } break; 8007df6: e00c b.n 8007e12 case CRC_POLYLENGTH_16B: if (msb >= HAL_CRC_LENGTH_16B) 8007df8: 693b ldr r3, [r7, #16] 8007dfa: 2b0f cmp r3, #15 8007dfc: d90b bls.n 8007e16 { status = HAL_ERROR; 8007dfe: 2301 movs r3, #1 8007e00: 75fb strb r3, [r7, #23] } break; 8007e02: e008 b.n 8007e16 case CRC_POLYLENGTH_32B: /* no polynomial definition vs. polynomial length issue possible */ break; default: status = HAL_ERROR; 8007e04: 2301 movs r3, #1 8007e06: 75fb strb r3, [r7, #23] break; 8007e08: e006 b.n 8007e18 break; 8007e0a: bf00 nop 8007e0c: e004 b.n 8007e18 break; 8007e0e: bf00 nop 8007e10: e002 b.n 8007e18 break; 8007e12: bf00 nop 8007e14: e000 b.n 8007e18 break; 8007e16: bf00 nop } } if (status == HAL_OK) 8007e18: 7dfb ldrb r3, [r7, #23] 8007e1a: 2b00 cmp r3, #0 8007e1c: d10d bne.n 8007e3a { /* set generating polynomial */ WRITE_REG(hcrc->Instance->POL, Pol); 8007e1e: 68fb ldr r3, [r7, #12] 8007e20: 681b ldr r3, [r3, #0] 8007e22: 68ba ldr r2, [r7, #8] 8007e24: 615a str r2, [r3, #20] /* set generating polynomial size */ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); 8007e26: 68fb ldr r3, [r7, #12] 8007e28: 681b ldr r3, [r3, #0] 8007e2a: 689b ldr r3, [r3, #8] 8007e2c: f023 0118 bic.w r1, r3, #24 8007e30: 68fb ldr r3, [r7, #12] 8007e32: 681b ldr r3, [r3, #0] 8007e34: 687a ldr r2, [r7, #4] 8007e36: 430a orrs r2, r1 8007e38: 609a str r2, [r3, #8] } /* Return function status */ return status; 8007e3a: 7dfb ldrb r3, [r7, #23] } 8007e3c: 4618 mov r0, r3 8007e3e: 371c adds r7, #28 8007e40: 46bd mov sp, r7 8007e42: f85d 7b04 ldr.w r7, [sp], #4 8007e46: 4770 bx lr 08007e48 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { 8007e48: b580 push {r7, lr} 8007e4a: b082 sub sp, #8 8007e4c: af00 add r7, sp, #0 8007e4e: 6078 str r0, [r7, #4] /* Check the DAC peripheral handle */ if (hdac == NULL) 8007e50: 687b ldr r3, [r7, #4] 8007e52: 2b00 cmp r3, #0 8007e54: d101 bne.n 8007e5a { return HAL_ERROR; 8007e56: 2301 movs r3, #1 8007e58: e014 b.n 8007e84 } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); if (hdac->State == HAL_DAC_STATE_RESET) 8007e5a: 687b ldr r3, [r7, #4] 8007e5c: 791b ldrb r3, [r3, #4] 8007e5e: b2db uxtb r3, r3 8007e60: 2b00 cmp r3, #0 8007e62: d105 bne.n 8007e70 hdac->MspInitCallback = HAL_DAC_MspInit; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /* Allocate lock resource and initialize it */ hdac->Lock = HAL_UNLOCKED; 8007e64: 687b ldr r3, [r7, #4] 8007e66: 2200 movs r2, #0 8007e68: 715a strb r2, [r3, #5] #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* Init the low level hardware */ hdac->MspInitCallback(hdac); #else /* Init the low level hardware */ HAL_DAC_MspInit(hdac); 8007e6a: 6878 ldr r0, [r7, #4] 8007e6c: f7fc f8d6 bl 800401c #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; 8007e70: 687b ldr r3, [r7, #4] 8007e72: 2202 movs r2, #2 8007e74: 711a strb r2, [r3, #4] /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; 8007e76: 687b ldr r3, [r7, #4] 8007e78: 2200 movs r2, #0 8007e7a: 611a str r2, [r3, #16] /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; 8007e7c: 687b ldr r3, [r7, #4] 8007e7e: 2201 movs r2, #1 8007e80: 711a strb r2, [r3, #4] /* Return function status */ return HAL_OK; 8007e82: 2300 movs r3, #0 } 8007e84: 4618 mov r0, r3 8007e86: 3708 adds r7, #8 8007e88: 46bd mov sp, r7 8007e8a: bd80 pop {r7, pc} 08007e8c : * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { 8007e8c: b480 push {r7} 8007e8e: b083 sub sp, #12 8007e90: af00 add r7, sp, #0 8007e92: 6078 str r0, [r7, #4] 8007e94: 6039 str r1, [r7, #0] /* Check the DAC peripheral handle */ if (hdac == NULL) 8007e96: 687b ldr r3, [r7, #4] 8007e98: 2b00 cmp r3, #0 8007e9a: d101 bne.n 8007ea0 { return HAL_ERROR; 8007e9c: 2301 movs r3, #1 8007e9e: e046 b.n 8007f2e /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 8007ea0: 687b ldr r3, [r7, #4] 8007ea2: 795b ldrb r3, [r3, #5] 8007ea4: 2b01 cmp r3, #1 8007ea6: d101 bne.n 8007eac 8007ea8: 2302 movs r3, #2 8007eaa: e040 b.n 8007f2e 8007eac: 687b ldr r3, [r7, #4] 8007eae: 2201 movs r2, #1 8007eb0: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 8007eb2: 687b ldr r3, [r7, #4] 8007eb4: 2202 movs r2, #2 8007eb6: 711a strb r2, [r3, #4] /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); 8007eb8: 687b ldr r3, [r7, #4] 8007eba: 681b ldr r3, [r3, #0] 8007ebc: 6819 ldr r1, [r3, #0] 8007ebe: 683b ldr r3, [r7, #0] 8007ec0: f003 0310 and.w r3, r3, #16 8007ec4: 2201 movs r2, #1 8007ec6: 409a lsls r2, r3 8007ec8: 687b ldr r3, [r7, #4] 8007eca: 681b ldr r3, [r3, #0] 8007ecc: 430a orrs r2, r1 8007ece: 601a str r2, [r3, #0] if (Channel == DAC_CHANNEL_1) 8007ed0: 683b ldr r3, [r7, #0] 8007ed2: 2b00 cmp r3, #0 8007ed4: d10f bne.n 8007ef6 { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) 8007ed6: 687b ldr r3, [r7, #4] 8007ed8: 681b ldr r3, [r3, #0] 8007eda: 681b ldr r3, [r3, #0] 8007edc: f003 033e and.w r3, r3, #62 @ 0x3e 8007ee0: 2b02 cmp r3, #2 8007ee2: d11d bne.n 8007f20 { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); 8007ee4: 687b ldr r3, [r7, #4] 8007ee6: 681b ldr r3, [r3, #0] 8007ee8: 685a ldr r2, [r3, #4] 8007eea: 687b ldr r3, [r7, #4] 8007eec: 681b ldr r3, [r3, #0] 8007eee: f042 0201 orr.w r2, r2, #1 8007ef2: 605a str r2, [r3, #4] 8007ef4: e014 b.n 8007f20 } else { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) 8007ef6: 687b ldr r3, [r7, #4] 8007ef8: 681b ldr r3, [r3, #0] 8007efa: 681b ldr r3, [r3, #0] 8007efc: f403 1278 and.w r2, r3, #4063232 @ 0x3e0000 8007f00: 683b ldr r3, [r7, #0] 8007f02: f003 0310 and.w r3, r3, #16 8007f06: 2102 movs r1, #2 8007f08: fa01 f303 lsl.w r3, r1, r3 8007f0c: 429a cmp r2, r3 8007f0e: d107 bne.n 8007f20 { /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); 8007f10: 687b ldr r3, [r7, #4] 8007f12: 681b ldr r3, [r3, #0] 8007f14: 685a ldr r2, [r3, #4] 8007f16: 687b ldr r3, [r7, #4] 8007f18: 681b ldr r3, [r3, #0] 8007f1a: f042 0202 orr.w r2, r2, #2 8007f1e: 605a str r2, [r3, #4] } } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 8007f20: 687b ldr r3, [r7, #4] 8007f22: 2201 movs r2, #1 8007f24: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 8007f26: 687b ldr r3, [r7, #4] 8007f28: 2200 movs r2, #0 8007f2a: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 8007f2c: 2300 movs r3, #0 } 8007f2e: 4618 mov r0, r3 8007f30: 370c adds r7, #12 8007f32: 46bd mov sp, r7 8007f34: f85d 7b04 ldr.w r7, [sp], #4 8007f38: 4770 bx lr 08007f3a : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { 8007f3a: b580 push {r7, lr} 8007f3c: b084 sub sp, #16 8007f3e: af00 add r7, sp, #0 8007f40: 6078 str r0, [r7, #4] uint32_t itsource = hdac->Instance->CR; 8007f42: 687b ldr r3, [r7, #4] 8007f44: 681b ldr r3, [r3, #0] 8007f46: 681b ldr r3, [r3, #0] 8007f48: 60fb str r3, [r7, #12] uint32_t itflag = hdac->Instance->SR; 8007f4a: 687b ldr r3, [r7, #4] 8007f4c: 681b ldr r3, [r3, #0] 8007f4e: 6b5b ldr r3, [r3, #52] @ 0x34 8007f50: 60bb str r3, [r7, #8] if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1) 8007f52: 68fb ldr r3, [r7, #12] 8007f54: f403 5300 and.w r3, r3, #8192 @ 0x2000 8007f58: 2b00 cmp r3, #0 8007f5a: d01d beq.n 8007f98 { /* Check underrun flag of DAC channel 1 */ if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1) 8007f5c: 68bb ldr r3, [r7, #8] 8007f5e: f403 5300 and.w r3, r3, #8192 @ 0x2000 8007f62: 2b00 cmp r3, #0 8007f64: d018 beq.n 8007f98 { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; 8007f66: 687b ldr r3, [r7, #4] 8007f68: 2204 movs r2, #4 8007f6a: 711a strb r2, [r3, #4] /* Set DAC error code to channel1 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); 8007f6c: 687b ldr r3, [r7, #4] 8007f6e: 691b ldr r3, [r3, #16] 8007f70: f043 0201 orr.w r2, r3, #1 8007f74: 687b ldr r3, [r7, #4] 8007f76: 611a str r2, [r3, #16] /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); 8007f78: 687b ldr r3, [r7, #4] 8007f7a: 681b ldr r3, [r3, #0] 8007f7c: f44f 5200 mov.w r2, #8192 @ 0x2000 8007f80: 635a str r2, [r3, #52] @ 0x34 /* Disable the selected DAC channel1 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1); 8007f82: 687b ldr r3, [r7, #4] 8007f84: 681b ldr r3, [r3, #0] 8007f86: 681a ldr r2, [r3, #0] 8007f88: 687b ldr r3, [r7, #4] 8007f8a: 681b ldr r3, [r3, #0] 8007f8c: f422 5280 bic.w r2, r2, #4096 @ 0x1000 8007f90: 601a str r2, [r3, #0] /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh1(hdac); #else HAL_DAC_DMAUnderrunCallbackCh1(hdac); 8007f92: 6878 ldr r0, [r7, #4] 8007f94: f000 f851 bl 800803a #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2) 8007f98: 68fb ldr r3, [r7, #12] 8007f9a: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8007f9e: 2b00 cmp r3, #0 8007fa0: d01d beq.n 8007fde { /* Check underrun flag of DAC channel 2 */ if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2) 8007fa2: 68bb ldr r3, [r7, #8] 8007fa4: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8007fa8: 2b00 cmp r3, #0 8007faa: d018 beq.n 8007fde { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; 8007fac: 687b ldr r3, [r7, #4] 8007fae: 2204 movs r2, #4 8007fb0: 711a strb r2, [r3, #4] /* Set DAC error code to channel2 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); 8007fb2: 687b ldr r3, [r7, #4] 8007fb4: 691b ldr r3, [r3, #16] 8007fb6: f043 0202 orr.w r2, r3, #2 8007fba: 687b ldr r3, [r7, #4] 8007fbc: 611a str r2, [r3, #16] /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); 8007fbe: 687b ldr r3, [r7, #4] 8007fc0: 681b ldr r3, [r3, #0] 8007fc2: f04f 5200 mov.w r2, #536870912 @ 0x20000000 8007fc6: 635a str r2, [r3, #52] @ 0x34 /* Disable the selected DAC channel2 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2); 8007fc8: 687b ldr r3, [r7, #4] 8007fca: 681b ldr r3, [r3, #0] 8007fcc: 681a ldr r2, [r3, #0] 8007fce: 687b ldr r3, [r7, #4] 8007fd0: 681b ldr r3, [r3, #0] 8007fd2: f022 5280 bic.w r2, r2, #268435456 @ 0x10000000 8007fd6: 601a str r2, [r3, #0] /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh2(hdac); #else HAL_DACEx_DMAUnderrunCallbackCh2(hdac); 8007fd8: 6878 ldr r0, [r7, #4] 8007fda: f000 f97b bl 80082d4 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } } 8007fde: bf00 nop 8007fe0: 3710 adds r7, #16 8007fe2: 46bd mov sp, r7 8007fe4: bd80 pop {r7, pc} 08007fe6 : * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { 8007fe6: b480 push {r7} 8007fe8: b087 sub sp, #28 8007fea: af00 add r7, sp, #0 8007fec: 60f8 str r0, [r7, #12] 8007fee: 60b9 str r1, [r7, #8] 8007ff0: 607a str r2, [r7, #4] 8007ff2: 603b str r3, [r7, #0] __IO uint32_t tmp = 0UL; 8007ff4: 2300 movs r3, #0 8007ff6: 617b str r3, [r7, #20] /* Check the DAC peripheral handle */ if (hdac == NULL) 8007ff8: 68fb ldr r3, [r7, #12] 8007ffa: 2b00 cmp r3, #0 8007ffc: d101 bne.n 8008002 { return HAL_ERROR; 8007ffe: 2301 movs r3, #1 8008000: e015 b.n 800802e /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)hdac->Instance; 8008002: 68fb ldr r3, [r7, #12] 8008004: 681b ldr r3, [r3, #0] 8008006: 617b str r3, [r7, #20] if (Channel == DAC_CHANNEL_1) 8008008: 68bb ldr r3, [r7, #8] 800800a: 2b00 cmp r3, #0 800800c: d105 bne.n 800801a { tmp += DAC_DHR12R1_ALIGNMENT(Alignment); 800800e: 697a ldr r2, [r7, #20] 8008010: 687b ldr r3, [r7, #4] 8008012: 4413 add r3, r2 8008014: 3308 adds r3, #8 8008016: 617b str r3, [r7, #20] 8008018: e004 b.n 8008024 } else { tmp += DAC_DHR12R2_ALIGNMENT(Alignment); 800801a: 697a ldr r2, [r7, #20] 800801c: 687b ldr r3, [r7, #4] 800801e: 4413 add r3, r2 8008020: 3314 adds r3, #20 8008022: 617b str r3, [r7, #20] } /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; 8008024: 697b ldr r3, [r7, #20] 8008026: 461a mov r2, r3 8008028: 683b ldr r3, [r7, #0] 800802a: 6013 str r3, [r2, #0] /* Return function status */ return HAL_OK; 800802c: 2300 movs r3, #0 } 800802e: 4618 mov r0, r3 8008030: 371c adds r7, #28 8008032: 46bd mov sp, r7 8008034: f85d 7b04 ldr.w r7, [sp], #4 8008038: 4770 bx lr 0800803a : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) { 800803a: b480 push {r7} 800803c: b083 sub sp, #12 800803e: af00 add r7, sp, #0 8008040: 6078 str r0, [r7, #4] UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file */ } 8008042: bf00 nop 8008044: 370c adds r7, #12 8008046: 46bd mov sp, r7 8008048: f85d 7b04 ldr.w r7, [sp], #4 800804c: 4770 bx lr ... 08008050 : * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { 8008050: b580 push {r7, lr} 8008052: b08a sub sp, #40 @ 0x28 8008054: af00 add r7, sp, #0 8008056: 60f8 str r0, [r7, #12] 8008058: 60b9 str r1, [r7, #8] 800805a: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800805c: 2300 movs r3, #0 800805e: f887 3023 strb.w r3, [r7, #35] @ 0x23 uint32_t tmpreg2; uint32_t tickstart; uint32_t connectOnChip; /* Check the DAC peripheral handle and channel configuration struct */ if ((hdac == NULL) || (sConfig == NULL)) 8008062: 68fb ldr r3, [r7, #12] 8008064: 2b00 cmp r3, #0 8008066: d002 beq.n 800806e 8008068: 68bb ldr r3, [r7, #8] 800806a: 2b00 cmp r3, #0 800806c: d101 bne.n 8008072 { return HAL_ERROR; 800806e: 2301 movs r3, #1 8008070: e12a b.n 80082c8 assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 8008072: 68fb ldr r3, [r7, #12] 8008074: 795b ldrb r3, [r3, #5] 8008076: 2b01 cmp r3, #1 8008078: d101 bne.n 800807e 800807a: 2302 movs r3, #2 800807c: e124 b.n 80082c8 800807e: 68fb ldr r3, [r7, #12] 8008080: 2201 movs r2, #1 8008082: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 8008084: 68fb ldr r3, [r7, #12] 8008086: 2202 movs r2, #2 8008088: 711a strb r2, [r3, #4] /* Sample and hold configuration */ if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) 800808a: 68bb ldr r3, [r7, #8] 800808c: 681b ldr r3, [r3, #0] 800808e: 2b04 cmp r3, #4 8008090: d17a bne.n 8008188 { /* Get timeout */ tickstart = HAL_GetTick(); 8008092: f7fd fd8d bl 8005bb0 8008096: 61f8 str r0, [r7, #28] if (Channel == DAC_CHANNEL_1) 8008098: 687b ldr r3, [r7, #4] 800809a: 2b00 cmp r3, #0 800809c: d13d bne.n 800811a { /* SHSR1 can be written when BWST1 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 800809e: e018 b.n 80080d2 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 80080a0: f7fd fd86 bl 8005bb0 80080a4: 4602 mov r2, r0 80080a6: 69fb ldr r3, [r7, #28] 80080a8: 1ad3 subs r3, r2, r3 80080aa: 2b01 cmp r3, #1 80080ac: d911 bls.n 80080d2 { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 80080ae: 68fb ldr r3, [r7, #12] 80080b0: 681b ldr r3, [r3, #0] 80080b2: 6b5a ldr r2, [r3, #52] @ 0x34 80080b4: 4b86 ldr r3, [pc, #536] @ (80082d0 ) 80080b6: 4013 ands r3, r2 80080b8: 2b00 cmp r3, #0 80080ba: d00a beq.n 80080d2 { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 80080bc: 68fb ldr r3, [r7, #12] 80080be: 691b ldr r3, [r3, #16] 80080c0: f043 0208 orr.w r2, r3, #8 80080c4: 68fb ldr r3, [r7, #12] 80080c6: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 80080c8: 68fb ldr r3, [r7, #12] 80080ca: 2203 movs r2, #3 80080cc: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 80080ce: 2303 movs r3, #3 80080d0: e0fa b.n 80082c8 while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 80080d2: 68fb ldr r3, [r7, #12] 80080d4: 681b ldr r3, [r3, #0] 80080d6: 6b5a ldr r2, [r3, #52] @ 0x34 80080d8: 4b7d ldr r3, [pc, #500] @ (80082d0 ) 80080da: 4013 ands r3, r2 80080dc: 2b00 cmp r3, #0 80080de: d1df bne.n 80080a0 } } } hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 80080e0: 68fb ldr r3, [r7, #12] 80080e2: 681b ldr r3, [r3, #0] 80080e4: 68ba ldr r2, [r7, #8] 80080e6: 6992 ldr r2, [r2, #24] 80080e8: 641a str r2, [r3, #64] @ 0x40 80080ea: e020 b.n 800812e { /* SHSR2 can be written when BWST2 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 80080ec: f7fd fd60 bl 8005bb0 80080f0: 4602 mov r2, r0 80080f2: 69fb ldr r3, [r7, #28] 80080f4: 1ad3 subs r3, r2, r3 80080f6: 2b01 cmp r3, #1 80080f8: d90f bls.n 800811a { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 80080fa: 68fb ldr r3, [r7, #12] 80080fc: 681b ldr r3, [r3, #0] 80080fe: 6b5b ldr r3, [r3, #52] @ 0x34 8008100: 2b00 cmp r3, #0 8008102: da0a bge.n 800811a { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 8008104: 68fb ldr r3, [r7, #12] 8008106: 691b ldr r3, [r3, #16] 8008108: f043 0208 orr.w r2, r3, #8 800810c: 68fb ldr r3, [r7, #12] 800810e: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 8008110: 68fb ldr r3, [r7, #12] 8008112: 2203 movs r2, #3 8008114: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 8008116: 2303 movs r3, #3 8008118: e0d6 b.n 80082c8 while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 800811a: 68fb ldr r3, [r7, #12] 800811c: 681b ldr r3, [r3, #0] 800811e: 6b5b ldr r3, [r3, #52] @ 0x34 8008120: 2b00 cmp r3, #0 8008122: dbe3 blt.n 80080ec } } } hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 8008124: 68fb ldr r3, [r7, #12] 8008126: 681b ldr r3, [r3, #0] 8008128: 68ba ldr r2, [r7, #8] 800812a: 6992 ldr r2, [r2, #24] 800812c: 645a str r2, [r3, #68] @ 0x44 } /* HoldTime */ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), 800812e: 68fb ldr r3, [r7, #12] 8008130: 681b ldr r3, [r3, #0] 8008132: 6c9a ldr r2, [r3, #72] @ 0x48 8008134: 687b ldr r3, [r7, #4] 8008136: f003 0310 and.w r3, r3, #16 800813a: f240 31ff movw r1, #1023 @ 0x3ff 800813e: fa01 f303 lsl.w r3, r1, r3 8008142: 43db mvns r3, r3 8008144: ea02 0103 and.w r1, r2, r3 8008148: 68bb ldr r3, [r7, #8] 800814a: 69da ldr r2, [r3, #28] 800814c: 687b ldr r3, [r7, #4] 800814e: f003 0310 and.w r3, r3, #16 8008152: 409a lsls r2, r3 8008154: 68fb ldr r3, [r7, #12] 8008156: 681b ldr r3, [r3, #0] 8008158: 430a orrs r2, r1 800815a: 649a str r2, [r3, #72] @ 0x48 (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); /* RefreshTime */ MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), 800815c: 68fb ldr r3, [r7, #12] 800815e: 681b ldr r3, [r3, #0] 8008160: 6cda ldr r2, [r3, #76] @ 0x4c 8008162: 687b ldr r3, [r7, #4] 8008164: f003 0310 and.w r3, r3, #16 8008168: 21ff movs r1, #255 @ 0xff 800816a: fa01 f303 lsl.w r3, r1, r3 800816e: 43db mvns r3, r3 8008170: ea02 0103 and.w r1, r2, r3 8008174: 68bb ldr r3, [r7, #8] 8008176: 6a1a ldr r2, [r3, #32] 8008178: 687b ldr r3, [r7, #4] 800817a: f003 0310 and.w r3, r3, #16 800817e: 409a lsls r2, r3 8008180: 68fb ldr r3, [r7, #12] 8008182: 681b ldr r3, [r3, #0] 8008184: 430a orrs r2, r1 8008186: 64da str r2, [r3, #76] @ 0x4c (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); } if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) 8008188: 68bb ldr r3, [r7, #8] 800818a: 691b ldr r3, [r3, #16] 800818c: 2b01 cmp r3, #1 800818e: d11d bne.n 80081cc /* USER TRIMMING */ { /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; 8008190: 68fb ldr r3, [r7, #12] 8008192: 681b ldr r3, [r3, #0] 8008194: 6b9b ldr r3, [r3, #56] @ 0x38 8008196: 61bb str r3, [r7, #24] /* Clear trimming value */ tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); 8008198: 687b ldr r3, [r7, #4] 800819a: f003 0310 and.w r3, r3, #16 800819e: 221f movs r2, #31 80081a0: fa02 f303 lsl.w r3, r2, r3 80081a4: 43db mvns r3, r3 80081a6: 69ba ldr r2, [r7, #24] 80081a8: 4013 ands r3, r2 80081aa: 61bb str r3, [r7, #24] /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; 80081ac: 68bb ldr r3, [r7, #8] 80081ae: 695b ldr r3, [r3, #20] 80081b0: 617b str r3, [r7, #20] /* Calculate CCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 80081b2: 687b ldr r3, [r7, #4] 80081b4: f003 0310 and.w r3, r3, #16 80081b8: 697a ldr r2, [r7, #20] 80081ba: fa02 f303 lsl.w r3, r2, r3 80081be: 69ba ldr r2, [r7, #24] 80081c0: 4313 orrs r3, r2 80081c2: 61bb str r3, [r7, #24] /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; 80081c4: 68fb ldr r3, [r7, #12] 80081c6: 681b ldr r3, [r3, #0] 80081c8: 69ba ldr r2, [r7, #24] 80081ca: 639a str r2, [r3, #56] @ 0x38 } /* else factory trimming is used (factory setting are available at reset)*/ /* SW Nothing has nothing to do */ /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; 80081cc: 68fb ldr r3, [r7, #12] 80081ce: 681b ldr r3, [r3, #0] 80081d0: 6bdb ldr r3, [r3, #60] @ 0x3c 80081d2: 61bb str r3, [r7, #24] /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); 80081d4: 687b ldr r3, [r7, #4] 80081d6: f003 0310 and.w r3, r3, #16 80081da: 2207 movs r2, #7 80081dc: fa02 f303 lsl.w r3, r2, r3 80081e0: 43db mvns r3, r3 80081e2: 69ba ldr r2, [r7, #24] 80081e4: 4013 ands r3, r2 80081e6: 61bb str r3, [r7, #24] /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) 80081e8: 68bb ldr r3, [r7, #8] 80081ea: 68db ldr r3, [r3, #12] 80081ec: 2b01 cmp r3, #1 80081ee: d102 bne.n 80081f6 { connectOnChip = 0x00000000UL; 80081f0: 2300 movs r3, #0 80081f2: 627b str r3, [r7, #36] @ 0x24 80081f4: e00f b.n 8008216 } else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL) 80081f6: 68bb ldr r3, [r7, #8] 80081f8: 68db ldr r3, [r3, #12] 80081fa: 2b02 cmp r3, #2 80081fc: d102 bne.n 8008204 { connectOnChip = DAC_MCR_MODE1_0; 80081fe: 2301 movs r3, #1 8008200: 627b str r3, [r7, #36] @ 0x24 8008202: e008 b.n 8008216 } else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */ { if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) 8008204: 68bb ldr r3, [r7, #8] 8008206: 689b ldr r3, [r3, #8] 8008208: 2b00 cmp r3, #0 800820a: d102 bne.n 8008212 { connectOnChip = DAC_MCR_MODE1_0; 800820c: 2301 movs r3, #1 800820e: 627b str r3, [r7, #36] @ 0x24 8008210: e001 b.n 8008216 } else { connectOnChip = 0x00000000UL; 8008212: 2300 movs r3, #0 8008214: 627b str r3, [r7, #36] @ 0x24 } } tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); 8008216: 68bb ldr r3, [r7, #8] 8008218: 681a ldr r2, [r3, #0] 800821a: 68bb ldr r3, [r7, #8] 800821c: 689b ldr r3, [r3, #8] 800821e: 4313 orrs r3, r2 8008220: 6a7a ldr r2, [r7, #36] @ 0x24 8008222: 4313 orrs r3, r2 8008224: 617b str r3, [r7, #20] /* Calculate MCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8008226: 687b ldr r3, [r7, #4] 8008228: f003 0310 and.w r3, r3, #16 800822c: 697a ldr r2, [r7, #20] 800822e: fa02 f303 lsl.w r3, r2, r3 8008232: 69ba ldr r2, [r7, #24] 8008234: 4313 orrs r3, r2 8008236: 61bb str r3, [r7, #24] /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; 8008238: 68fb ldr r3, [r7, #12] 800823a: 681b ldr r3, [r3, #0] 800823c: 69ba ldr r2, [r7, #24] 800823e: 63da str r2, [r3, #60] @ 0x3c /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); 8008240: 68fb ldr r3, [r7, #12] 8008242: 681b ldr r3, [r3, #0] 8008244: 6819 ldr r1, [r3, #0] 8008246: 687b ldr r3, [r7, #4] 8008248: f003 0310 and.w r3, r3, #16 800824c: f44f 4280 mov.w r2, #16384 @ 0x4000 8008250: fa02 f303 lsl.w r3, r2, r3 8008254: 43da mvns r2, r3 8008256: 68fb ldr r3, [r7, #12] 8008258: 681b ldr r3, [r3, #0] 800825a: 400a ands r2, r1 800825c: 601a str r2, [r3, #0] /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; 800825e: 68fb ldr r3, [r7, #12] 8008260: 681b ldr r3, [r3, #0] 8008262: 681b ldr r3, [r3, #0] 8008264: 61bb str r3, [r7, #24] /* Clear TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); 8008266: 687b ldr r3, [r7, #4] 8008268: f003 0310 and.w r3, r3, #16 800826c: f640 72fe movw r2, #4094 @ 0xffe 8008270: fa02 f303 lsl.w r3, r2, r3 8008274: 43db mvns r3, r3 8008276: 69ba ldr r2, [r7, #24] 8008278: 4013 ands r3, r2 800827a: 61bb str r3, [r7, #24] /* Configure for the selected DAC channel: trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ tmpreg2 = sConfig->DAC_Trigger; 800827c: 68bb ldr r3, [r7, #8] 800827e: 685b ldr r3, [r3, #4] 8008280: 617b str r3, [r7, #20] /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8008282: 687b ldr r3, [r7, #4] 8008284: f003 0310 and.w r3, r3, #16 8008288: 697a ldr r2, [r7, #20] 800828a: fa02 f303 lsl.w r3, r2, r3 800828e: 69ba ldr r2, [r7, #24] 8008290: 4313 orrs r3, r2 8008292: 61bb str r3, [r7, #24] /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; 8008294: 68fb ldr r3, [r7, #12] 8008296: 681b ldr r3, [r3, #0] 8008298: 69ba ldr r2, [r7, #24] 800829a: 601a str r2, [r3, #0] /* Disable wave generation */ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); 800829c: 68fb ldr r3, [r7, #12] 800829e: 681b ldr r3, [r3, #0] 80082a0: 6819 ldr r1, [r3, #0] 80082a2: 687b ldr r3, [r7, #4] 80082a4: f003 0310 and.w r3, r3, #16 80082a8: 22c0 movs r2, #192 @ 0xc0 80082aa: fa02 f303 lsl.w r3, r2, r3 80082ae: 43da mvns r2, r3 80082b0: 68fb ldr r3, [r7, #12] 80082b2: 681b ldr r3, [r3, #0] 80082b4: 400a ands r2, r1 80082b6: 601a str r2, [r3, #0] /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 80082b8: 68fb ldr r3, [r7, #12] 80082ba: 2201 movs r2, #1 80082bc: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 80082be: 68fb ldr r3, [r7, #12] 80082c0: 2200 movs r2, #0 80082c2: 715a strb r2, [r3, #5] /* Return function status */ return status; 80082c4: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 } 80082c8: 4618 mov r0, r3 80082ca: 3728 adds r7, #40 @ 0x28 80082cc: 46bd mov sp, r7 80082ce: bd80 pop {r7, pc} 80082d0: 20008000 .word 0x20008000 080082d4 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) { 80082d4: b480 push {r7} 80082d6: b083 sub sp, #12 80082d8: af00 add r7, sp, #0 80082da: 6078 str r0, [r7, #4] UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file */ } 80082dc: bf00 nop 80082de: 370c adds r7, #12 80082e0: 46bd mov sp, r7 80082e2: f85d 7b04 ldr.w r7, [sp], #4 80082e6: 4770 bx lr 080082e8 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 80082e8: b580 push {r7, lr} 80082ea: b086 sub sp, #24 80082ec: af00 add r7, sp, #0 80082ee: 6078 str r0, [r7, #4] uint32_t registerValue; uint32_t tickstart = HAL_GetTick(); 80082f0: f7fd fc5e bl 8005bb0 80082f4: 6138 str r0, [r7, #16] DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 80082f6: 687b ldr r3, [r7, #4] 80082f8: 2b00 cmp r3, #0 80082fa: d101 bne.n 8008300 { return HAL_ERROR; 80082fc: 2301 movs r3, #1 80082fe: e316 b.n 800892e assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8008300: 687b ldr r3, [r7, #4] 8008302: 681b ldr r3, [r3, #0] 8008304: 4a66 ldr r2, [pc, #408] @ (80084a0 ) 8008306: 4293 cmp r3, r2 8008308: d04a beq.n 80083a0 800830a: 687b ldr r3, [r7, #4] 800830c: 681b ldr r3, [r3, #0] 800830e: 4a65 ldr r2, [pc, #404] @ (80084a4 ) 8008310: 4293 cmp r3, r2 8008312: d045 beq.n 80083a0 8008314: 687b ldr r3, [r7, #4] 8008316: 681b ldr r3, [r3, #0] 8008318: 4a63 ldr r2, [pc, #396] @ (80084a8 ) 800831a: 4293 cmp r3, r2 800831c: d040 beq.n 80083a0 800831e: 687b ldr r3, [r7, #4] 8008320: 681b ldr r3, [r3, #0] 8008322: 4a62 ldr r2, [pc, #392] @ (80084ac ) 8008324: 4293 cmp r3, r2 8008326: d03b beq.n 80083a0 8008328: 687b ldr r3, [r7, #4] 800832a: 681b ldr r3, [r3, #0] 800832c: 4a60 ldr r2, [pc, #384] @ (80084b0 ) 800832e: 4293 cmp r3, r2 8008330: d036 beq.n 80083a0 8008332: 687b ldr r3, [r7, #4] 8008334: 681b ldr r3, [r3, #0] 8008336: 4a5f ldr r2, [pc, #380] @ (80084b4 ) 8008338: 4293 cmp r3, r2 800833a: d031 beq.n 80083a0 800833c: 687b ldr r3, [r7, #4] 800833e: 681b ldr r3, [r3, #0] 8008340: 4a5d ldr r2, [pc, #372] @ (80084b8 ) 8008342: 4293 cmp r3, r2 8008344: d02c beq.n 80083a0 8008346: 687b ldr r3, [r7, #4] 8008348: 681b ldr r3, [r3, #0] 800834a: 4a5c ldr r2, [pc, #368] @ (80084bc ) 800834c: 4293 cmp r3, r2 800834e: d027 beq.n 80083a0 8008350: 687b ldr r3, [r7, #4] 8008352: 681b ldr r3, [r3, #0] 8008354: 4a5a ldr r2, [pc, #360] @ (80084c0 ) 8008356: 4293 cmp r3, r2 8008358: d022 beq.n 80083a0 800835a: 687b ldr r3, [r7, #4] 800835c: 681b ldr r3, [r3, #0] 800835e: 4a59 ldr r2, [pc, #356] @ (80084c4 ) 8008360: 4293 cmp r3, r2 8008362: d01d beq.n 80083a0 8008364: 687b ldr r3, [r7, #4] 8008366: 681b ldr r3, [r3, #0] 8008368: 4a57 ldr r2, [pc, #348] @ (80084c8 ) 800836a: 4293 cmp r3, r2 800836c: d018 beq.n 80083a0 800836e: 687b ldr r3, [r7, #4] 8008370: 681b ldr r3, [r3, #0] 8008372: 4a56 ldr r2, [pc, #344] @ (80084cc ) 8008374: 4293 cmp r3, r2 8008376: d013 beq.n 80083a0 8008378: 687b ldr r3, [r7, #4] 800837a: 681b ldr r3, [r3, #0] 800837c: 4a54 ldr r2, [pc, #336] @ (80084d0 ) 800837e: 4293 cmp r3, r2 8008380: d00e beq.n 80083a0 8008382: 687b ldr r3, [r7, #4] 8008384: 681b ldr r3, [r3, #0] 8008386: 4a53 ldr r2, [pc, #332] @ (80084d4 ) 8008388: 4293 cmp r3, r2 800838a: d009 beq.n 80083a0 800838c: 687b ldr r3, [r7, #4] 800838e: 681b ldr r3, [r3, #0] 8008390: 4a51 ldr r2, [pc, #324] @ (80084d8 ) 8008392: 4293 cmp r3, r2 8008394: d004 beq.n 80083a0 8008396: 687b ldr r3, [r7, #4] 8008398: 681b ldr r3, [r3, #0] 800839a: 4a50 ldr r2, [pc, #320] @ (80084dc ) 800839c: 4293 cmp r3, r2 800839e: d101 bne.n 80083a4 80083a0: 2301 movs r3, #1 80083a2: e000 b.n 80083a6 80083a4: 2300 movs r3, #0 80083a6: 2b00 cmp r3, #0 80083a8: f000 813b beq.w 8008622 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80083ac: 687b ldr r3, [r7, #4] 80083ae: 2202 movs r2, #2 80083b0: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 80083b4: 687b ldr r3, [r7, #4] 80083b6: 2200 movs r2, #0 80083b8: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 80083bc: 687b ldr r3, [r7, #4] 80083be: 681b ldr r3, [r3, #0] 80083c0: 4a37 ldr r2, [pc, #220] @ (80084a0 ) 80083c2: 4293 cmp r3, r2 80083c4: d04a beq.n 800845c 80083c6: 687b ldr r3, [r7, #4] 80083c8: 681b ldr r3, [r3, #0] 80083ca: 4a36 ldr r2, [pc, #216] @ (80084a4 ) 80083cc: 4293 cmp r3, r2 80083ce: d045 beq.n 800845c 80083d0: 687b ldr r3, [r7, #4] 80083d2: 681b ldr r3, [r3, #0] 80083d4: 4a34 ldr r2, [pc, #208] @ (80084a8 ) 80083d6: 4293 cmp r3, r2 80083d8: d040 beq.n 800845c 80083da: 687b ldr r3, [r7, #4] 80083dc: 681b ldr r3, [r3, #0] 80083de: 4a33 ldr r2, [pc, #204] @ (80084ac ) 80083e0: 4293 cmp r3, r2 80083e2: d03b beq.n 800845c 80083e4: 687b ldr r3, [r7, #4] 80083e6: 681b ldr r3, [r3, #0] 80083e8: 4a31 ldr r2, [pc, #196] @ (80084b0 ) 80083ea: 4293 cmp r3, r2 80083ec: d036 beq.n 800845c 80083ee: 687b ldr r3, [r7, #4] 80083f0: 681b ldr r3, [r3, #0] 80083f2: 4a30 ldr r2, [pc, #192] @ (80084b4 ) 80083f4: 4293 cmp r3, r2 80083f6: d031 beq.n 800845c 80083f8: 687b ldr r3, [r7, #4] 80083fa: 681b ldr r3, [r3, #0] 80083fc: 4a2e ldr r2, [pc, #184] @ (80084b8 ) 80083fe: 4293 cmp r3, r2 8008400: d02c beq.n 800845c 8008402: 687b ldr r3, [r7, #4] 8008404: 681b ldr r3, [r3, #0] 8008406: 4a2d ldr r2, [pc, #180] @ (80084bc ) 8008408: 4293 cmp r3, r2 800840a: d027 beq.n 800845c 800840c: 687b ldr r3, [r7, #4] 800840e: 681b ldr r3, [r3, #0] 8008410: 4a2b ldr r2, [pc, #172] @ (80084c0 ) 8008412: 4293 cmp r3, r2 8008414: d022 beq.n 800845c 8008416: 687b ldr r3, [r7, #4] 8008418: 681b ldr r3, [r3, #0] 800841a: 4a2a ldr r2, [pc, #168] @ (80084c4 ) 800841c: 4293 cmp r3, r2 800841e: d01d beq.n 800845c 8008420: 687b ldr r3, [r7, #4] 8008422: 681b ldr r3, [r3, #0] 8008424: 4a28 ldr r2, [pc, #160] @ (80084c8 ) 8008426: 4293 cmp r3, r2 8008428: d018 beq.n 800845c 800842a: 687b ldr r3, [r7, #4] 800842c: 681b ldr r3, [r3, #0] 800842e: 4a27 ldr r2, [pc, #156] @ (80084cc ) 8008430: 4293 cmp r3, r2 8008432: d013 beq.n 800845c 8008434: 687b ldr r3, [r7, #4] 8008436: 681b ldr r3, [r3, #0] 8008438: 4a25 ldr r2, [pc, #148] @ (80084d0 ) 800843a: 4293 cmp r3, r2 800843c: d00e beq.n 800845c 800843e: 687b ldr r3, [r7, #4] 8008440: 681b ldr r3, [r3, #0] 8008442: 4a24 ldr r2, [pc, #144] @ (80084d4 ) 8008444: 4293 cmp r3, r2 8008446: d009 beq.n 800845c 8008448: 687b ldr r3, [r7, #4] 800844a: 681b ldr r3, [r3, #0] 800844c: 4a22 ldr r2, [pc, #136] @ (80084d8 ) 800844e: 4293 cmp r3, r2 8008450: d004 beq.n 800845c 8008452: 687b ldr r3, [r7, #4] 8008454: 681b ldr r3, [r3, #0] 8008456: 4a21 ldr r2, [pc, #132] @ (80084dc ) 8008458: 4293 cmp r3, r2 800845a: d108 bne.n 800846e 800845c: 687b ldr r3, [r7, #4] 800845e: 681b ldr r3, [r3, #0] 8008460: 681a ldr r2, [r3, #0] 8008462: 687b ldr r3, [r7, #4] 8008464: 681b ldr r3, [r3, #0] 8008466: f022 0201 bic.w r2, r2, #1 800846a: 601a str r2, [r3, #0] 800846c: e007 b.n 800847e 800846e: 687b ldr r3, [r7, #4] 8008470: 681b ldr r3, [r3, #0] 8008472: 681a ldr r2, [r3, #0] 8008474: 687b ldr r3, [r7, #4] 8008476: 681b ldr r3, [r3, #0] 8008478: f022 0201 bic.w r2, r2, #1 800847c: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 800847e: e02f b.n 80084e0 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8008480: f7fd fb96 bl 8005bb0 8008484: 4602 mov r2, r0 8008486: 693b ldr r3, [r7, #16] 8008488: 1ad3 subs r3, r2, r3 800848a: 2b05 cmp r3, #5 800848c: d928 bls.n 80084e0 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 800848e: 687b ldr r3, [r7, #4] 8008490: 2220 movs r2, #32 8008492: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 8008494: 687b ldr r3, [r7, #4] 8008496: 2203 movs r2, #3 8008498: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 800849c: 2301 movs r3, #1 800849e: e246 b.n 800892e 80084a0: 40020010 .word 0x40020010 80084a4: 40020028 .word 0x40020028 80084a8: 40020040 .word 0x40020040 80084ac: 40020058 .word 0x40020058 80084b0: 40020070 .word 0x40020070 80084b4: 40020088 .word 0x40020088 80084b8: 400200a0 .word 0x400200a0 80084bc: 400200b8 .word 0x400200b8 80084c0: 40020410 .word 0x40020410 80084c4: 40020428 .word 0x40020428 80084c8: 40020440 .word 0x40020440 80084cc: 40020458 .word 0x40020458 80084d0: 40020470 .word 0x40020470 80084d4: 40020488 .word 0x40020488 80084d8: 400204a0 .word 0x400204a0 80084dc: 400204b8 .word 0x400204b8 while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 80084e0: 687b ldr r3, [r7, #4] 80084e2: 681b ldr r3, [r3, #0] 80084e4: 681b ldr r3, [r3, #0] 80084e6: f003 0301 and.w r3, r3, #1 80084ea: 2b00 cmp r3, #0 80084ec: d1c8 bne.n 8008480 } } /* Get the CR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; 80084ee: 687b ldr r3, [r7, #4] 80084f0: 681b ldr r3, [r3, #0] 80084f2: 681b ldr r3, [r3, #0] 80084f4: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 80084f6: 697a ldr r2, [r7, #20] 80084f8: 4b83 ldr r3, [pc, #524] @ (8008708 ) 80084fa: 4013 ands r3, r2 80084fc: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ registerValue |= hdma->Init.Direction | 80084fe: 687b ldr r3, [r7, #4] 8008500: 689a ldr r2, [r3, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 8008502: 687b ldr r3, [r7, #4] 8008504: 68db ldr r3, [r3, #12] registerValue |= hdma->Init.Direction | 8008506: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8008508: 687b ldr r3, [r7, #4] 800850a: 691b ldr r3, [r3, #16] 800850c: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800850e: 687b ldr r3, [r7, #4] 8008510: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8008512: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8008514: 687b ldr r3, [r7, #4] 8008516: 699b ldr r3, [r3, #24] 8008518: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800851a: 687b ldr r3, [r7, #4] 800851c: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800851e: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8008520: 687b ldr r3, [r7, #4] 8008522: 6a1b ldr r3, [r3, #32] 8008524: 4313 orrs r3, r2 registerValue |= hdma->Init.Direction | 8008526: 697a ldr r2, [r7, #20] 8008528: 4313 orrs r3, r2 800852a: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 800852c: 687b ldr r3, [r7, #4] 800852e: 6a5b ldr r3, [r3, #36] @ 0x24 8008530: 2b04 cmp r3, #4 8008532: d107 bne.n 8008544 { /* Get memory burst and peripheral burst */ registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 8008534: 687b ldr r3, [r7, #4] 8008536: 6ada ldr r2, [r3, #44] @ 0x2c 8008538: 687b ldr r3, [r7, #4] 800853a: 6b1b ldr r3, [r3, #48] @ 0x30 800853c: 4313 orrs r3, r2 800853e: 697a ldr r2, [r7, #20] 8008540: 4313 orrs r3, r2 8008542: 617b str r3, [r7, #20] } /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be lock when transferring data to/from USART/UART */ #if (STM32H7_DEV_ID == 0x450UL) if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) 8008544: 4b71 ldr r3, [pc, #452] @ (800870c ) 8008546: 681a ldr r2, [r3, #0] 8008548: 4b71 ldr r3, [pc, #452] @ (8008710 ) 800854a: 4013 ands r3, r2 800854c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8008550: d328 bcc.n 80085a4 { #endif /* STM32H7_DEV_ID == 0x450UL */ if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) 8008552: 687b ldr r3, [r7, #4] 8008554: 685b ldr r3, [r3, #4] 8008556: 2b28 cmp r3, #40 @ 0x28 8008558: d903 bls.n 8008562 800855a: 687b ldr r3, [r7, #4] 800855c: 685b ldr r3, [r3, #4] 800855e: 2b2e cmp r3, #46 @ 0x2e 8008560: d917 bls.n 8008592 8008562: 687b ldr r3, [r7, #4] 8008564: 685b ldr r3, [r3, #4] 8008566: 2b3e cmp r3, #62 @ 0x3e 8008568: d903 bls.n 8008572 800856a: 687b ldr r3, [r7, #4] 800856c: 685b ldr r3, [r3, #4] 800856e: 2b42 cmp r3, #66 @ 0x42 8008570: d90f bls.n 8008592 8008572: 687b ldr r3, [r7, #4] 8008574: 685b ldr r3, [r3, #4] 8008576: 2b46 cmp r3, #70 @ 0x46 8008578: d903 bls.n 8008582 800857a: 687b ldr r3, [r7, #4] 800857c: 685b ldr r3, [r3, #4] 800857e: 2b48 cmp r3, #72 @ 0x48 8008580: d907 bls.n 8008592 8008582: 687b ldr r3, [r7, #4] 8008584: 685b ldr r3, [r3, #4] 8008586: 2b4e cmp r3, #78 @ 0x4e 8008588: d905 bls.n 8008596 800858a: 687b ldr r3, [r7, #4] 800858c: 685b ldr r3, [r3, #4] 800858e: 2b52 cmp r3, #82 @ 0x52 8008590: d801 bhi.n 8008596 8008592: 2301 movs r3, #1 8008594: e000 b.n 8008598 8008596: 2300 movs r3, #0 8008598: 2b00 cmp r3, #0 800859a: d003 beq.n 80085a4 { registerValue |= DMA_SxCR_TRBUFF; 800859c: 697b ldr r3, [r7, #20] 800859e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80085a2: 617b str r3, [r7, #20] #if (STM32H7_DEV_ID == 0x450UL) } #endif /* STM32H7_DEV_ID == 0x450UL */ /* Write to DMA Stream CR register */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; 80085a4: 687b ldr r3, [r7, #4] 80085a6: 681b ldr r3, [r3, #0] 80085a8: 697a ldr r2, [r7, #20] 80085aa: 601a str r2, [r3, #0] /* Get the FCR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; 80085ac: 687b ldr r3, [r7, #4] 80085ae: 681b ldr r3, [r3, #0] 80085b0: 695b ldr r3, [r3, #20] 80085b2: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 80085b4: 697b ldr r3, [r7, #20] 80085b6: f023 0307 bic.w r3, r3, #7 80085ba: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ registerValue |= hdma->Init.FIFOMode; 80085bc: 687b ldr r3, [r7, #4] 80085be: 6a5b ldr r3, [r3, #36] @ 0x24 80085c0: 697a ldr r2, [r7, #20] 80085c2: 4313 orrs r3, r2 80085c4: 617b str r3, [r7, #20] /* the FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 80085c6: 687b ldr r3, [r7, #4] 80085c8: 6a5b ldr r3, [r3, #36] @ 0x24 80085ca: 2b04 cmp r3, #4 80085cc: d117 bne.n 80085fe { /* Get the FIFO threshold */ registerValue |= hdma->Init.FIFOThreshold; 80085ce: 687b ldr r3, [r7, #4] 80085d0: 6a9b ldr r3, [r3, #40] @ 0x28 80085d2: 697a ldr r2, [r7, #20] 80085d4: 4313 orrs r3, r2 80085d6: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 */ if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) 80085d8: 687b ldr r3, [r7, #4] 80085da: 6adb ldr r3, [r3, #44] @ 0x2c 80085dc: 2b00 cmp r3, #0 80085de: d00e beq.n 80085fe { if (DMA_CheckFifoParam(hdma) != HAL_OK) 80085e0: 6878 ldr r0, [r7, #4] 80085e2: f002 fb33 bl 800ac4c 80085e6: 4603 mov r3, r0 80085e8: 2b00 cmp r3, #0 80085ea: d008 beq.n 80085fe { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 80085ec: 687b ldr r3, [r7, #4] 80085ee: 2240 movs r2, #64 @ 0x40 80085f0: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80085f2: 687b ldr r3, [r7, #4] 80085f4: 2201 movs r2, #1 80085f6: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 80085fa: 2301 movs r3, #1 80085fc: e197 b.n 800892e } } } /* Write to DMA Stream FCR */ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; 80085fe: 687b ldr r3, [r7, #4] 8008600: 681b ldr r3, [r3, #0] 8008602: 697a ldr r2, [r7, #20] 8008604: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8008606: 6878 ldr r0, [r7, #4] 8008608: f002 fa6e bl 800aae8 800860c: 4603 mov r3, r0 800860e: 60bb str r3, [r7, #8] /* Clear all interrupt flags */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8008610: 687b ldr r3, [r7, #4] 8008612: 6ddb ldr r3, [r3, #92] @ 0x5c 8008614: f003 031f and.w r3, r3, #31 8008618: 223f movs r2, #63 @ 0x3f 800861a: 409a lsls r2, r3 800861c: 68bb ldr r3, [r7, #8] 800861e: 609a str r2, [r3, #8] 8008620: e0cd b.n 80087be } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 8008622: 687b ldr r3, [r7, #4] 8008624: 681b ldr r3, [r3, #0] 8008626: 4a3b ldr r2, [pc, #236] @ (8008714 ) 8008628: 4293 cmp r3, r2 800862a: d022 beq.n 8008672 800862c: 687b ldr r3, [r7, #4] 800862e: 681b ldr r3, [r3, #0] 8008630: 4a39 ldr r2, [pc, #228] @ (8008718 ) 8008632: 4293 cmp r3, r2 8008634: d01d beq.n 8008672 8008636: 687b ldr r3, [r7, #4] 8008638: 681b ldr r3, [r3, #0] 800863a: 4a38 ldr r2, [pc, #224] @ (800871c ) 800863c: 4293 cmp r3, r2 800863e: d018 beq.n 8008672 8008640: 687b ldr r3, [r7, #4] 8008642: 681b ldr r3, [r3, #0] 8008644: 4a36 ldr r2, [pc, #216] @ (8008720 ) 8008646: 4293 cmp r3, r2 8008648: d013 beq.n 8008672 800864a: 687b ldr r3, [r7, #4] 800864c: 681b ldr r3, [r3, #0] 800864e: 4a35 ldr r2, [pc, #212] @ (8008724 ) 8008650: 4293 cmp r3, r2 8008652: d00e beq.n 8008672 8008654: 687b ldr r3, [r7, #4] 8008656: 681b ldr r3, [r3, #0] 8008658: 4a33 ldr r2, [pc, #204] @ (8008728 ) 800865a: 4293 cmp r3, r2 800865c: d009 beq.n 8008672 800865e: 687b ldr r3, [r7, #4] 8008660: 681b ldr r3, [r3, #0] 8008662: 4a32 ldr r2, [pc, #200] @ (800872c ) 8008664: 4293 cmp r3, r2 8008666: d004 beq.n 8008672 8008668: 687b ldr r3, [r7, #4] 800866a: 681b ldr r3, [r3, #0] 800866c: 4a30 ldr r2, [pc, #192] @ (8008730 ) 800866e: 4293 cmp r3, r2 8008670: d101 bne.n 8008676 8008672: 2301 movs r3, #1 8008674: e000 b.n 8008678 8008676: 2300 movs r3, #0 8008678: 2b00 cmp r3, #0 800867a: f000 8097 beq.w 80087ac { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 800867e: 687b ldr r3, [r7, #4] 8008680: 681b ldr r3, [r3, #0] 8008682: 4a24 ldr r2, [pc, #144] @ (8008714 ) 8008684: 4293 cmp r3, r2 8008686: d021 beq.n 80086cc 8008688: 687b ldr r3, [r7, #4] 800868a: 681b ldr r3, [r3, #0] 800868c: 4a22 ldr r2, [pc, #136] @ (8008718 ) 800868e: 4293 cmp r3, r2 8008690: d01c beq.n 80086cc 8008692: 687b ldr r3, [r7, #4] 8008694: 681b ldr r3, [r3, #0] 8008696: 4a21 ldr r2, [pc, #132] @ (800871c ) 8008698: 4293 cmp r3, r2 800869a: d017 beq.n 80086cc 800869c: 687b ldr r3, [r7, #4] 800869e: 681b ldr r3, [r3, #0] 80086a0: 4a1f ldr r2, [pc, #124] @ (8008720 ) 80086a2: 4293 cmp r3, r2 80086a4: d012 beq.n 80086cc 80086a6: 687b ldr r3, [r7, #4] 80086a8: 681b ldr r3, [r3, #0] 80086aa: 4a1e ldr r2, [pc, #120] @ (8008724 ) 80086ac: 4293 cmp r3, r2 80086ae: d00d beq.n 80086cc 80086b0: 687b ldr r3, [r7, #4] 80086b2: 681b ldr r3, [r3, #0] 80086b4: 4a1c ldr r2, [pc, #112] @ (8008728 ) 80086b6: 4293 cmp r3, r2 80086b8: d008 beq.n 80086cc 80086ba: 687b ldr r3, [r7, #4] 80086bc: 681b ldr r3, [r3, #0] 80086be: 4a1b ldr r2, [pc, #108] @ (800872c ) 80086c0: 4293 cmp r3, r2 80086c2: d003 beq.n 80086cc 80086c4: 687b ldr r3, [r7, #4] 80086c6: 681b ldr r3, [r3, #0] 80086c8: 4a19 ldr r2, [pc, #100] @ (8008730 ) 80086ca: 4293 cmp r3, r2 /* Check the request parameter */ assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80086cc: 687b ldr r3, [r7, #4] 80086ce: 2202 movs r2, #2 80086d0: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 80086d4: 687b ldr r3, [r7, #4] 80086d6: 2200 movs r2, #0 80086d8: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Get the CR register value */ registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; 80086dc: 687b ldr r3, [r7, #4] 80086de: 681b ldr r3, [r3, #0] 80086e0: 681b ldr r3, [r3, #0] 80086e2: 617b str r3, [r7, #20] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */ registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ 80086e4: 697a ldr r2, [r7, #20] 80086e6: 4b13 ldr r3, [pc, #76] @ (8008734 ) 80086e8: 4013 ands r3, r2 80086ea: 617b str r3, [r7, #20] BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \ BDMA_CCR_CT)); /* Prepare the DMA Channel configuration */ registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 80086ec: 687b ldr r3, [r7, #4] 80086ee: 689b ldr r3, [r3, #8] 80086f0: 2b40 cmp r3, #64 @ 0x40 80086f2: d021 beq.n 8008738 80086f4: 687b ldr r3, [r7, #4] 80086f6: 689b ldr r3, [r3, #8] 80086f8: 2b80 cmp r3, #128 @ 0x80 80086fa: d102 bne.n 8008702 80086fc: f44f 4380 mov.w r3, #16384 @ 0x4000 8008700: e01b b.n 800873a 8008702: 2300 movs r3, #0 8008704: e019 b.n 800873a 8008706: bf00 nop 8008708: fe10803f .word 0xfe10803f 800870c: 5c001000 .word 0x5c001000 8008710: ffff0000 .word 0xffff0000 8008714: 58025408 .word 0x58025408 8008718: 5802541c .word 0x5802541c 800871c: 58025430 .word 0x58025430 8008720: 58025444 .word 0x58025444 8008724: 58025458 .word 0x58025458 8008728: 5802546c .word 0x5802546c 800872c: 58025480 .word 0x58025480 8008730: 58025494 .word 0x58025494 8008734: fffe000f .word 0xfffe000f 8008738: 2310 movs r3, #16 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 800873a: 687a ldr r2, [r7, #4] 800873c: 68d2 ldr r2, [r2, #12] 800873e: 08d2 lsrs r2, r2, #3 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8008740: 431a orrs r2, r3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 8008742: 687b ldr r3, [r7, #4] 8008744: 691b ldr r3, [r3, #16] 8008746: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 8008748: 431a orrs r2, r3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 800874a: 687b ldr r3, [r7, #4] 800874c: 695b ldr r3, [r3, #20] 800874e: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 8008750: 431a orrs r2, r3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 8008752: 687b ldr r3, [r7, #4] 8008754: 699b ldr r3, [r3, #24] 8008756: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 8008758: 431a orrs r2, r3 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 800875a: 687b ldr r3, [r7, #4] 800875c: 69db ldr r3, [r3, #28] 800875e: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 8008760: 431a orrs r2, r3 DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); 8008762: 687b ldr r3, [r7, #4] 8008764: 6a1b ldr r3, [r3, #32] 8008766: 091b lsrs r3, r3, #4 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 8008768: 4313 orrs r3, r2 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 800876a: 697a ldr r2, [r7, #20] 800876c: 4313 orrs r3, r2 800876e: 617b str r3, [r7, #20] /* Write to DMA Channel CR register */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; 8008770: 687b ldr r3, [r7, #4] 8008772: 681b ldr r3, [r3, #0] 8008774: 697a ldr r2, [r7, #20] 8008776: 601a str r2, [r3, #0] /* calculation of the channel index */ hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; 8008778: 687b ldr r3, [r7, #4] 800877a: 681b ldr r3, [r3, #0] 800877c: 461a mov r2, r3 800877e: 4b6e ldr r3, [pc, #440] @ (8008938 ) 8008780: 4413 add r3, r2 8008782: 4a6e ldr r2, [pc, #440] @ (800893c ) 8008784: fba2 2303 umull r2, r3, r2, r3 8008788: 091b lsrs r3, r3, #4 800878a: 009a lsls r2, r3, #2 800878c: 687b ldr r3, [r7, #4] 800878e: 65da str r2, [r3, #92] @ 0x5c /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8008790: 6878 ldr r0, [r7, #4] 8008792: f002 f9a9 bl 800aae8 8008796: 4603 mov r3, r0 8008798: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 800879a: 687b ldr r3, [r7, #4] 800879c: 6ddb ldr r3, [r3, #92] @ 0x5c 800879e: f003 031f and.w r3, r3, #31 80087a2: 2201 movs r2, #1 80087a4: 409a lsls r2, r3 80087a6: 68fb ldr r3, [r7, #12] 80087a8: 605a str r2, [r3, #4] 80087aa: e008 b.n 80087be } else { hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 80087ac: 687b ldr r3, [r7, #4] 80087ae: 2240 movs r2, #64 @ 0x40 80087b0: 655a str r2, [r3, #84] @ 0x54 hdma->State = HAL_DMA_STATE_ERROR; 80087b2: 687b ldr r3, [r7, #4] 80087b4: 2203 movs r2, #3 80087b6: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 80087ba: 2301 movs r3, #1 80087bc: e0b7 b.n 800892e } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80087be: 687b ldr r3, [r7, #4] 80087c0: 681b ldr r3, [r3, #0] 80087c2: 4a5f ldr r2, [pc, #380] @ (8008940 ) 80087c4: 4293 cmp r3, r2 80087c6: d072 beq.n 80088ae 80087c8: 687b ldr r3, [r7, #4] 80087ca: 681b ldr r3, [r3, #0] 80087cc: 4a5d ldr r2, [pc, #372] @ (8008944 ) 80087ce: 4293 cmp r3, r2 80087d0: d06d beq.n 80088ae 80087d2: 687b ldr r3, [r7, #4] 80087d4: 681b ldr r3, [r3, #0] 80087d6: 4a5c ldr r2, [pc, #368] @ (8008948 ) 80087d8: 4293 cmp r3, r2 80087da: d068 beq.n 80088ae 80087dc: 687b ldr r3, [r7, #4] 80087de: 681b ldr r3, [r3, #0] 80087e0: 4a5a ldr r2, [pc, #360] @ (800894c ) 80087e2: 4293 cmp r3, r2 80087e4: d063 beq.n 80088ae 80087e6: 687b ldr r3, [r7, #4] 80087e8: 681b ldr r3, [r3, #0] 80087ea: 4a59 ldr r2, [pc, #356] @ (8008950 ) 80087ec: 4293 cmp r3, r2 80087ee: d05e beq.n 80088ae 80087f0: 687b ldr r3, [r7, #4] 80087f2: 681b ldr r3, [r3, #0] 80087f4: 4a57 ldr r2, [pc, #348] @ (8008954 ) 80087f6: 4293 cmp r3, r2 80087f8: d059 beq.n 80088ae 80087fa: 687b ldr r3, [r7, #4] 80087fc: 681b ldr r3, [r3, #0] 80087fe: 4a56 ldr r2, [pc, #344] @ (8008958 ) 8008800: 4293 cmp r3, r2 8008802: d054 beq.n 80088ae 8008804: 687b ldr r3, [r7, #4] 8008806: 681b ldr r3, [r3, #0] 8008808: 4a54 ldr r2, [pc, #336] @ (800895c ) 800880a: 4293 cmp r3, r2 800880c: d04f beq.n 80088ae 800880e: 687b ldr r3, [r7, #4] 8008810: 681b ldr r3, [r3, #0] 8008812: 4a53 ldr r2, [pc, #332] @ (8008960 ) 8008814: 4293 cmp r3, r2 8008816: d04a beq.n 80088ae 8008818: 687b ldr r3, [r7, #4] 800881a: 681b ldr r3, [r3, #0] 800881c: 4a51 ldr r2, [pc, #324] @ (8008964 ) 800881e: 4293 cmp r3, r2 8008820: d045 beq.n 80088ae 8008822: 687b ldr r3, [r7, #4] 8008824: 681b ldr r3, [r3, #0] 8008826: 4a50 ldr r2, [pc, #320] @ (8008968 ) 8008828: 4293 cmp r3, r2 800882a: d040 beq.n 80088ae 800882c: 687b ldr r3, [r7, #4] 800882e: 681b ldr r3, [r3, #0] 8008830: 4a4e ldr r2, [pc, #312] @ (800896c ) 8008832: 4293 cmp r3, r2 8008834: d03b beq.n 80088ae 8008836: 687b ldr r3, [r7, #4] 8008838: 681b ldr r3, [r3, #0] 800883a: 4a4d ldr r2, [pc, #308] @ (8008970 ) 800883c: 4293 cmp r3, r2 800883e: d036 beq.n 80088ae 8008840: 687b ldr r3, [r7, #4] 8008842: 681b ldr r3, [r3, #0] 8008844: 4a4b ldr r2, [pc, #300] @ (8008974 ) 8008846: 4293 cmp r3, r2 8008848: d031 beq.n 80088ae 800884a: 687b ldr r3, [r7, #4] 800884c: 681b ldr r3, [r3, #0] 800884e: 4a4a ldr r2, [pc, #296] @ (8008978 ) 8008850: 4293 cmp r3, r2 8008852: d02c beq.n 80088ae 8008854: 687b ldr r3, [r7, #4] 8008856: 681b ldr r3, [r3, #0] 8008858: 4a48 ldr r2, [pc, #288] @ (800897c ) 800885a: 4293 cmp r3, r2 800885c: d027 beq.n 80088ae 800885e: 687b ldr r3, [r7, #4] 8008860: 681b ldr r3, [r3, #0] 8008862: 4a47 ldr r2, [pc, #284] @ (8008980 ) 8008864: 4293 cmp r3, r2 8008866: d022 beq.n 80088ae 8008868: 687b ldr r3, [r7, #4] 800886a: 681b ldr r3, [r3, #0] 800886c: 4a45 ldr r2, [pc, #276] @ (8008984 ) 800886e: 4293 cmp r3, r2 8008870: d01d beq.n 80088ae 8008872: 687b ldr r3, [r7, #4] 8008874: 681b ldr r3, [r3, #0] 8008876: 4a44 ldr r2, [pc, #272] @ (8008988 ) 8008878: 4293 cmp r3, r2 800887a: d018 beq.n 80088ae 800887c: 687b ldr r3, [r7, #4] 800887e: 681b ldr r3, [r3, #0] 8008880: 4a42 ldr r2, [pc, #264] @ (800898c ) 8008882: 4293 cmp r3, r2 8008884: d013 beq.n 80088ae 8008886: 687b ldr r3, [r7, #4] 8008888: 681b ldr r3, [r3, #0] 800888a: 4a41 ldr r2, [pc, #260] @ (8008990 ) 800888c: 4293 cmp r3, r2 800888e: d00e beq.n 80088ae 8008890: 687b ldr r3, [r7, #4] 8008892: 681b ldr r3, [r3, #0] 8008894: 4a3f ldr r2, [pc, #252] @ (8008994 ) 8008896: 4293 cmp r3, r2 8008898: d009 beq.n 80088ae 800889a: 687b ldr r3, [r7, #4] 800889c: 681b ldr r3, [r3, #0] 800889e: 4a3e ldr r2, [pc, #248] @ (8008998 ) 80088a0: 4293 cmp r3, r2 80088a2: d004 beq.n 80088ae 80088a4: 687b ldr r3, [r7, #4] 80088a6: 681b ldr r3, [r3, #0] 80088a8: 4a3c ldr r2, [pc, #240] @ (800899c ) 80088aa: 4293 cmp r3, r2 80088ac: d101 bne.n 80088b2 80088ae: 2301 movs r3, #1 80088b0: e000 b.n 80088b4 80088b2: 2300 movs r3, #0 80088b4: 2b00 cmp r3, #0 80088b6: d032 beq.n 800891e { /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 80088b8: 6878 ldr r0, [r7, #4] 80088ba: f002 fa43 bl 800ad44 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 80088be: 687b ldr r3, [r7, #4] 80088c0: 689b ldr r3, [r3, #8] 80088c2: 2b80 cmp r3, #128 @ 0x80 80088c4: d102 bne.n 80088cc { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 80088c6: 687b ldr r3, [r7, #4] 80088c8: 2200 movs r2, #0 80088ca: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 80088cc: 687b ldr r3, [r7, #4] 80088ce: 685a ldr r2, [r3, #4] 80088d0: 687b ldr r3, [r7, #4] 80088d2: 6e1b ldr r3, [r3, #96] @ 0x60 80088d4: b2d2 uxtb r2, r2 80088d6: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 80088d8: 687b ldr r3, [r7, #4] 80088da: 6e5b ldr r3, [r3, #100] @ 0x64 80088dc: 687a ldr r2, [r7, #4] 80088de: 6e92 ldr r2, [r2, #104] @ 0x68 80088e0: 605a str r2, [r3, #4] /* Initialize parameters for DMAMUX request generator : if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 */ if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) 80088e2: 687b ldr r3, [r7, #4] 80088e4: 685b ldr r3, [r3, #4] 80088e6: 2b00 cmp r3, #0 80088e8: d010 beq.n 800890c 80088ea: 687b ldr r3, [r7, #4] 80088ec: 685b ldr r3, [r3, #4] 80088ee: 2b08 cmp r3, #8 80088f0: d80c bhi.n 800890c { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 80088f2: 6878 ldr r0, [r7, #4] 80088f4: f002 fac0 bl 800ae78 /* Reset the DMAMUX request generator register */ hdma->DMAmuxRequestGen->RGCR = 0U; 80088f8: 687b ldr r3, [r7, #4] 80088fa: 6edb ldr r3, [r3, #108] @ 0x6c 80088fc: 2200 movs r2, #0 80088fe: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8008900: 687b ldr r3, [r7, #4] 8008902: 6f1b ldr r3, [r3, #112] @ 0x70 8008904: 687a ldr r2, [r7, #4] 8008906: 6f52 ldr r2, [r2, #116] @ 0x74 8008908: 605a str r2, [r3, #4] 800890a: e008 b.n 800891e } else { hdma->DMAmuxRequestGen = 0U; 800890c: 687b ldr r3, [r7, #4] 800890e: 2200 movs r2, #0 8008910: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = 0U; 8008912: 687b ldr r3, [r7, #4] 8008914: 2200 movs r2, #0 8008916: 671a str r2, [r3, #112] @ 0x70 hdma->DMAmuxRequestGenStatusMask = 0U; 8008918: 687b ldr r3, [r7, #4] 800891a: 2200 movs r2, #0 800891c: 675a str r2, [r3, #116] @ 0x74 } } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800891e: 687b ldr r3, [r7, #4] 8008920: 2200 movs r2, #0 8008922: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8008924: 687b ldr r3, [r7, #4] 8008926: 2201 movs r2, #1 8008928: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 800892c: 2300 movs r3, #0 } 800892e: 4618 mov r0, r3 8008930: 3718 adds r7, #24 8008932: 46bd mov sp, r7 8008934: bd80 pop {r7, pc} 8008936: bf00 nop 8008938: a7fdabf8 .word 0xa7fdabf8 800893c: cccccccd .word 0xcccccccd 8008940: 40020010 .word 0x40020010 8008944: 40020028 .word 0x40020028 8008948: 40020040 .word 0x40020040 800894c: 40020058 .word 0x40020058 8008950: 40020070 .word 0x40020070 8008954: 40020088 .word 0x40020088 8008958: 400200a0 .word 0x400200a0 800895c: 400200b8 .word 0x400200b8 8008960: 40020410 .word 0x40020410 8008964: 40020428 .word 0x40020428 8008968: 40020440 .word 0x40020440 800896c: 40020458 .word 0x40020458 8008970: 40020470 .word 0x40020470 8008974: 40020488 .word 0x40020488 8008978: 400204a0 .word 0x400204a0 800897c: 400204b8 .word 0x400204b8 8008980: 58025408 .word 0x58025408 8008984: 5802541c .word 0x5802541c 8008988: 58025430 .word 0x58025430 800898c: 58025444 .word 0x58025444 8008990: 58025458 .word 0x58025458 8008994: 5802546c .word 0x5802546c 8008998: 58025480 .word 0x58025480 800899c: 58025494 .word 0x58025494 080089a0 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 80089a0: b580 push {r7, lr} 80089a2: b086 sub sp, #24 80089a4: af00 add r7, sp, #0 80089a6: 60f8 str r0, [r7, #12] 80089a8: 60b9 str r1, [r7, #8] 80089aa: 607a str r2, [r7, #4] 80089ac: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 80089ae: 2300 movs r3, #0 80089b0: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Check the DMA peripheral handle */ if(hdma == NULL) 80089b2: 68fb ldr r3, [r7, #12] 80089b4: 2b00 cmp r3, #0 80089b6: d101 bne.n 80089bc { return HAL_ERROR; 80089b8: 2301 movs r3, #1 80089ba: e226 b.n 8008e0a } /* Process locked */ __HAL_LOCK(hdma); 80089bc: 68fb ldr r3, [r7, #12] 80089be: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 80089c2: 2b01 cmp r3, #1 80089c4: d101 bne.n 80089ca 80089c6: 2302 movs r3, #2 80089c8: e21f b.n 8008e0a 80089ca: 68fb ldr r3, [r7, #12] 80089cc: 2201 movs r2, #1 80089ce: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 80089d2: 68fb ldr r3, [r7, #12] 80089d4: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 80089d8: b2db uxtb r3, r3 80089da: 2b01 cmp r3, #1 80089dc: f040 820a bne.w 8008df4 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80089e0: 68fb ldr r3, [r7, #12] 80089e2: 2202 movs r2, #2 80089e4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 80089e8: 68fb ldr r3, [r7, #12] 80089ea: 2200 movs r2, #0 80089ec: 655a str r2, [r3, #84] @ 0x54 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 80089ee: 68fb ldr r3, [r7, #12] 80089f0: 681b ldr r3, [r3, #0] 80089f2: 4a68 ldr r2, [pc, #416] @ (8008b94 ) 80089f4: 4293 cmp r3, r2 80089f6: d04a beq.n 8008a8e 80089f8: 68fb ldr r3, [r7, #12] 80089fa: 681b ldr r3, [r3, #0] 80089fc: 4a66 ldr r2, [pc, #408] @ (8008b98 ) 80089fe: 4293 cmp r3, r2 8008a00: d045 beq.n 8008a8e 8008a02: 68fb ldr r3, [r7, #12] 8008a04: 681b ldr r3, [r3, #0] 8008a06: 4a65 ldr r2, [pc, #404] @ (8008b9c ) 8008a08: 4293 cmp r3, r2 8008a0a: d040 beq.n 8008a8e 8008a0c: 68fb ldr r3, [r7, #12] 8008a0e: 681b ldr r3, [r3, #0] 8008a10: 4a63 ldr r2, [pc, #396] @ (8008ba0 ) 8008a12: 4293 cmp r3, r2 8008a14: d03b beq.n 8008a8e 8008a16: 68fb ldr r3, [r7, #12] 8008a18: 681b ldr r3, [r3, #0] 8008a1a: 4a62 ldr r2, [pc, #392] @ (8008ba4 ) 8008a1c: 4293 cmp r3, r2 8008a1e: d036 beq.n 8008a8e 8008a20: 68fb ldr r3, [r7, #12] 8008a22: 681b ldr r3, [r3, #0] 8008a24: 4a60 ldr r2, [pc, #384] @ (8008ba8 ) 8008a26: 4293 cmp r3, r2 8008a28: d031 beq.n 8008a8e 8008a2a: 68fb ldr r3, [r7, #12] 8008a2c: 681b ldr r3, [r3, #0] 8008a2e: 4a5f ldr r2, [pc, #380] @ (8008bac ) 8008a30: 4293 cmp r3, r2 8008a32: d02c beq.n 8008a8e 8008a34: 68fb ldr r3, [r7, #12] 8008a36: 681b ldr r3, [r3, #0] 8008a38: 4a5d ldr r2, [pc, #372] @ (8008bb0 ) 8008a3a: 4293 cmp r3, r2 8008a3c: d027 beq.n 8008a8e 8008a3e: 68fb ldr r3, [r7, #12] 8008a40: 681b ldr r3, [r3, #0] 8008a42: 4a5c ldr r2, [pc, #368] @ (8008bb4 ) 8008a44: 4293 cmp r3, r2 8008a46: d022 beq.n 8008a8e 8008a48: 68fb ldr r3, [r7, #12] 8008a4a: 681b ldr r3, [r3, #0] 8008a4c: 4a5a ldr r2, [pc, #360] @ (8008bb8 ) 8008a4e: 4293 cmp r3, r2 8008a50: d01d beq.n 8008a8e 8008a52: 68fb ldr r3, [r7, #12] 8008a54: 681b ldr r3, [r3, #0] 8008a56: 4a59 ldr r2, [pc, #356] @ (8008bbc ) 8008a58: 4293 cmp r3, r2 8008a5a: d018 beq.n 8008a8e 8008a5c: 68fb ldr r3, [r7, #12] 8008a5e: 681b ldr r3, [r3, #0] 8008a60: 4a57 ldr r2, [pc, #348] @ (8008bc0 ) 8008a62: 4293 cmp r3, r2 8008a64: d013 beq.n 8008a8e 8008a66: 68fb ldr r3, [r7, #12] 8008a68: 681b ldr r3, [r3, #0] 8008a6a: 4a56 ldr r2, [pc, #344] @ (8008bc4 ) 8008a6c: 4293 cmp r3, r2 8008a6e: d00e beq.n 8008a8e 8008a70: 68fb ldr r3, [r7, #12] 8008a72: 681b ldr r3, [r3, #0] 8008a74: 4a54 ldr r2, [pc, #336] @ (8008bc8 ) 8008a76: 4293 cmp r3, r2 8008a78: d009 beq.n 8008a8e 8008a7a: 68fb ldr r3, [r7, #12] 8008a7c: 681b ldr r3, [r3, #0] 8008a7e: 4a53 ldr r2, [pc, #332] @ (8008bcc ) 8008a80: 4293 cmp r3, r2 8008a82: d004 beq.n 8008a8e 8008a84: 68fb ldr r3, [r7, #12] 8008a86: 681b ldr r3, [r3, #0] 8008a88: 4a51 ldr r2, [pc, #324] @ (8008bd0 ) 8008a8a: 4293 cmp r3, r2 8008a8c: d108 bne.n 8008aa0 8008a8e: 68fb ldr r3, [r7, #12] 8008a90: 681b ldr r3, [r3, #0] 8008a92: 681a ldr r2, [r3, #0] 8008a94: 68fb ldr r3, [r7, #12] 8008a96: 681b ldr r3, [r3, #0] 8008a98: f022 0201 bic.w r2, r2, #1 8008a9c: 601a str r2, [r3, #0] 8008a9e: e007 b.n 8008ab0 8008aa0: 68fb ldr r3, [r7, #12] 8008aa2: 681b ldr r3, [r3, #0] 8008aa4: 681a ldr r2, [r3, #0] 8008aa6: 68fb ldr r3, [r7, #12] 8008aa8: 681b ldr r3, [r3, #0] 8008aaa: f022 0201 bic.w r2, r2, #1 8008aae: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8008ab0: 683b ldr r3, [r7, #0] 8008ab2: 687a ldr r2, [r7, #4] 8008ab4: 68b9 ldr r1, [r7, #8] 8008ab6: 68f8 ldr r0, [r7, #12] 8008ab8: f001 fe6a bl 800a790 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8008abc: 68fb ldr r3, [r7, #12] 8008abe: 681b ldr r3, [r3, #0] 8008ac0: 4a34 ldr r2, [pc, #208] @ (8008b94 ) 8008ac2: 4293 cmp r3, r2 8008ac4: d04a beq.n 8008b5c 8008ac6: 68fb ldr r3, [r7, #12] 8008ac8: 681b ldr r3, [r3, #0] 8008aca: 4a33 ldr r2, [pc, #204] @ (8008b98 ) 8008acc: 4293 cmp r3, r2 8008ace: d045 beq.n 8008b5c 8008ad0: 68fb ldr r3, [r7, #12] 8008ad2: 681b ldr r3, [r3, #0] 8008ad4: 4a31 ldr r2, [pc, #196] @ (8008b9c ) 8008ad6: 4293 cmp r3, r2 8008ad8: d040 beq.n 8008b5c 8008ada: 68fb ldr r3, [r7, #12] 8008adc: 681b ldr r3, [r3, #0] 8008ade: 4a30 ldr r2, [pc, #192] @ (8008ba0 ) 8008ae0: 4293 cmp r3, r2 8008ae2: d03b beq.n 8008b5c 8008ae4: 68fb ldr r3, [r7, #12] 8008ae6: 681b ldr r3, [r3, #0] 8008ae8: 4a2e ldr r2, [pc, #184] @ (8008ba4 ) 8008aea: 4293 cmp r3, r2 8008aec: d036 beq.n 8008b5c 8008aee: 68fb ldr r3, [r7, #12] 8008af0: 681b ldr r3, [r3, #0] 8008af2: 4a2d ldr r2, [pc, #180] @ (8008ba8 ) 8008af4: 4293 cmp r3, r2 8008af6: d031 beq.n 8008b5c 8008af8: 68fb ldr r3, [r7, #12] 8008afa: 681b ldr r3, [r3, #0] 8008afc: 4a2b ldr r2, [pc, #172] @ (8008bac ) 8008afe: 4293 cmp r3, r2 8008b00: d02c beq.n 8008b5c 8008b02: 68fb ldr r3, [r7, #12] 8008b04: 681b ldr r3, [r3, #0] 8008b06: 4a2a ldr r2, [pc, #168] @ (8008bb0 ) 8008b08: 4293 cmp r3, r2 8008b0a: d027 beq.n 8008b5c 8008b0c: 68fb ldr r3, [r7, #12] 8008b0e: 681b ldr r3, [r3, #0] 8008b10: 4a28 ldr r2, [pc, #160] @ (8008bb4 ) 8008b12: 4293 cmp r3, r2 8008b14: d022 beq.n 8008b5c 8008b16: 68fb ldr r3, [r7, #12] 8008b18: 681b ldr r3, [r3, #0] 8008b1a: 4a27 ldr r2, [pc, #156] @ (8008bb8 ) 8008b1c: 4293 cmp r3, r2 8008b1e: d01d beq.n 8008b5c 8008b20: 68fb ldr r3, [r7, #12] 8008b22: 681b ldr r3, [r3, #0] 8008b24: 4a25 ldr r2, [pc, #148] @ (8008bbc ) 8008b26: 4293 cmp r3, r2 8008b28: d018 beq.n 8008b5c 8008b2a: 68fb ldr r3, [r7, #12] 8008b2c: 681b ldr r3, [r3, #0] 8008b2e: 4a24 ldr r2, [pc, #144] @ (8008bc0 ) 8008b30: 4293 cmp r3, r2 8008b32: d013 beq.n 8008b5c 8008b34: 68fb ldr r3, [r7, #12] 8008b36: 681b ldr r3, [r3, #0] 8008b38: 4a22 ldr r2, [pc, #136] @ (8008bc4 ) 8008b3a: 4293 cmp r3, r2 8008b3c: d00e beq.n 8008b5c 8008b3e: 68fb ldr r3, [r7, #12] 8008b40: 681b ldr r3, [r3, #0] 8008b42: 4a21 ldr r2, [pc, #132] @ (8008bc8 ) 8008b44: 4293 cmp r3, r2 8008b46: d009 beq.n 8008b5c 8008b48: 68fb ldr r3, [r7, #12] 8008b4a: 681b ldr r3, [r3, #0] 8008b4c: 4a1f ldr r2, [pc, #124] @ (8008bcc ) 8008b4e: 4293 cmp r3, r2 8008b50: d004 beq.n 8008b5c 8008b52: 68fb ldr r3, [r7, #12] 8008b54: 681b ldr r3, [r3, #0] 8008b56: 4a1e ldr r2, [pc, #120] @ (8008bd0 ) 8008b58: 4293 cmp r3, r2 8008b5a: d101 bne.n 8008b60 8008b5c: 2301 movs r3, #1 8008b5e: e000 b.n 8008b62 8008b60: 2300 movs r3, #0 8008b62: 2b00 cmp r3, #0 8008b64: d036 beq.n 8008bd4 { /* Enable Common interrupts*/ MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 8008b66: 68fb ldr r3, [r7, #12] 8008b68: 681b ldr r3, [r3, #0] 8008b6a: 681b ldr r3, [r3, #0] 8008b6c: f023 021e bic.w r2, r3, #30 8008b70: 68fb ldr r3, [r7, #12] 8008b72: 681b ldr r3, [r3, #0] 8008b74: f042 0216 orr.w r2, r2, #22 8008b78: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8008b7a: 68fb ldr r3, [r7, #12] 8008b7c: 6c1b ldr r3, [r3, #64] @ 0x40 8008b7e: 2b00 cmp r3, #0 8008b80: d03e beq.n 8008c00 { /* Enable Half Transfer IT if corresponding Callback is set */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; 8008b82: 68fb ldr r3, [r7, #12] 8008b84: 681b ldr r3, [r3, #0] 8008b86: 681a ldr r2, [r3, #0] 8008b88: 68fb ldr r3, [r7, #12] 8008b8a: 681b ldr r3, [r3, #0] 8008b8c: f042 0208 orr.w r2, r2, #8 8008b90: 601a str r2, [r3, #0] 8008b92: e035 b.n 8008c00 8008b94: 40020010 .word 0x40020010 8008b98: 40020028 .word 0x40020028 8008b9c: 40020040 .word 0x40020040 8008ba0: 40020058 .word 0x40020058 8008ba4: 40020070 .word 0x40020070 8008ba8: 40020088 .word 0x40020088 8008bac: 400200a0 .word 0x400200a0 8008bb0: 400200b8 .word 0x400200b8 8008bb4: 40020410 .word 0x40020410 8008bb8: 40020428 .word 0x40020428 8008bbc: 40020440 .word 0x40020440 8008bc0: 40020458 .word 0x40020458 8008bc4: 40020470 .word 0x40020470 8008bc8: 40020488 .word 0x40020488 8008bcc: 400204a0 .word 0x400204a0 8008bd0: 400204b8 .word 0x400204b8 } } else /* BDMA channel */ { /* Enable Common interrupts */ MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE)); 8008bd4: 68fb ldr r3, [r7, #12] 8008bd6: 681b ldr r3, [r3, #0] 8008bd8: 681b ldr r3, [r3, #0] 8008bda: f023 020e bic.w r2, r3, #14 8008bde: 68fb ldr r3, [r7, #12] 8008be0: 681b ldr r3, [r3, #0] 8008be2: f042 020a orr.w r2, r2, #10 8008be6: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8008be8: 68fb ldr r3, [r7, #12] 8008bea: 6c1b ldr r3, [r3, #64] @ 0x40 8008bec: 2b00 cmp r3, #0 8008bee: d007 beq.n 8008c00 { /*Enable Half Transfer IT if corresponding Callback is set */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; 8008bf0: 68fb ldr r3, [r7, #12] 8008bf2: 681b ldr r3, [r3, #0] 8008bf4: 681a ldr r2, [r3, #0] 8008bf6: 68fb ldr r3, [r7, #12] 8008bf8: 681b ldr r3, [r3, #0] 8008bfa: f042 0204 orr.w r2, r2, #4 8008bfe: 601a str r2, [r3, #0] } } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8008c00: 68fb ldr r3, [r7, #12] 8008c02: 681b ldr r3, [r3, #0] 8008c04: 4a83 ldr r2, [pc, #524] @ (8008e14 ) 8008c06: 4293 cmp r3, r2 8008c08: d072 beq.n 8008cf0 8008c0a: 68fb ldr r3, [r7, #12] 8008c0c: 681b ldr r3, [r3, #0] 8008c0e: 4a82 ldr r2, [pc, #520] @ (8008e18 ) 8008c10: 4293 cmp r3, r2 8008c12: d06d beq.n 8008cf0 8008c14: 68fb ldr r3, [r7, #12] 8008c16: 681b ldr r3, [r3, #0] 8008c18: 4a80 ldr r2, [pc, #512] @ (8008e1c ) 8008c1a: 4293 cmp r3, r2 8008c1c: d068 beq.n 8008cf0 8008c1e: 68fb ldr r3, [r7, #12] 8008c20: 681b ldr r3, [r3, #0] 8008c22: 4a7f ldr r2, [pc, #508] @ (8008e20 ) 8008c24: 4293 cmp r3, r2 8008c26: d063 beq.n 8008cf0 8008c28: 68fb ldr r3, [r7, #12] 8008c2a: 681b ldr r3, [r3, #0] 8008c2c: 4a7d ldr r2, [pc, #500] @ (8008e24 ) 8008c2e: 4293 cmp r3, r2 8008c30: d05e beq.n 8008cf0 8008c32: 68fb ldr r3, [r7, #12] 8008c34: 681b ldr r3, [r3, #0] 8008c36: 4a7c ldr r2, [pc, #496] @ (8008e28 ) 8008c38: 4293 cmp r3, r2 8008c3a: d059 beq.n 8008cf0 8008c3c: 68fb ldr r3, [r7, #12] 8008c3e: 681b ldr r3, [r3, #0] 8008c40: 4a7a ldr r2, [pc, #488] @ (8008e2c ) 8008c42: 4293 cmp r3, r2 8008c44: d054 beq.n 8008cf0 8008c46: 68fb ldr r3, [r7, #12] 8008c48: 681b ldr r3, [r3, #0] 8008c4a: 4a79 ldr r2, [pc, #484] @ (8008e30 ) 8008c4c: 4293 cmp r3, r2 8008c4e: d04f beq.n 8008cf0 8008c50: 68fb ldr r3, [r7, #12] 8008c52: 681b ldr r3, [r3, #0] 8008c54: 4a77 ldr r2, [pc, #476] @ (8008e34 ) 8008c56: 4293 cmp r3, r2 8008c58: d04a beq.n 8008cf0 8008c5a: 68fb ldr r3, [r7, #12] 8008c5c: 681b ldr r3, [r3, #0] 8008c5e: 4a76 ldr r2, [pc, #472] @ (8008e38 ) 8008c60: 4293 cmp r3, r2 8008c62: d045 beq.n 8008cf0 8008c64: 68fb ldr r3, [r7, #12] 8008c66: 681b ldr r3, [r3, #0] 8008c68: 4a74 ldr r2, [pc, #464] @ (8008e3c ) 8008c6a: 4293 cmp r3, r2 8008c6c: d040 beq.n 8008cf0 8008c6e: 68fb ldr r3, [r7, #12] 8008c70: 681b ldr r3, [r3, #0] 8008c72: 4a73 ldr r2, [pc, #460] @ (8008e40 ) 8008c74: 4293 cmp r3, r2 8008c76: d03b beq.n 8008cf0 8008c78: 68fb ldr r3, [r7, #12] 8008c7a: 681b ldr r3, [r3, #0] 8008c7c: 4a71 ldr r2, [pc, #452] @ (8008e44 ) 8008c7e: 4293 cmp r3, r2 8008c80: d036 beq.n 8008cf0 8008c82: 68fb ldr r3, [r7, #12] 8008c84: 681b ldr r3, [r3, #0] 8008c86: 4a70 ldr r2, [pc, #448] @ (8008e48 ) 8008c88: 4293 cmp r3, r2 8008c8a: d031 beq.n 8008cf0 8008c8c: 68fb ldr r3, [r7, #12] 8008c8e: 681b ldr r3, [r3, #0] 8008c90: 4a6e ldr r2, [pc, #440] @ (8008e4c ) 8008c92: 4293 cmp r3, r2 8008c94: d02c beq.n 8008cf0 8008c96: 68fb ldr r3, [r7, #12] 8008c98: 681b ldr r3, [r3, #0] 8008c9a: 4a6d ldr r2, [pc, #436] @ (8008e50 ) 8008c9c: 4293 cmp r3, r2 8008c9e: d027 beq.n 8008cf0 8008ca0: 68fb ldr r3, [r7, #12] 8008ca2: 681b ldr r3, [r3, #0] 8008ca4: 4a6b ldr r2, [pc, #428] @ (8008e54 ) 8008ca6: 4293 cmp r3, r2 8008ca8: d022 beq.n 8008cf0 8008caa: 68fb ldr r3, [r7, #12] 8008cac: 681b ldr r3, [r3, #0] 8008cae: 4a6a ldr r2, [pc, #424] @ (8008e58 ) 8008cb0: 4293 cmp r3, r2 8008cb2: d01d beq.n 8008cf0 8008cb4: 68fb ldr r3, [r7, #12] 8008cb6: 681b ldr r3, [r3, #0] 8008cb8: 4a68 ldr r2, [pc, #416] @ (8008e5c ) 8008cba: 4293 cmp r3, r2 8008cbc: d018 beq.n 8008cf0 8008cbe: 68fb ldr r3, [r7, #12] 8008cc0: 681b ldr r3, [r3, #0] 8008cc2: 4a67 ldr r2, [pc, #412] @ (8008e60 ) 8008cc4: 4293 cmp r3, r2 8008cc6: d013 beq.n 8008cf0 8008cc8: 68fb ldr r3, [r7, #12] 8008cca: 681b ldr r3, [r3, #0] 8008ccc: 4a65 ldr r2, [pc, #404] @ (8008e64 ) 8008cce: 4293 cmp r3, r2 8008cd0: d00e beq.n 8008cf0 8008cd2: 68fb ldr r3, [r7, #12] 8008cd4: 681b ldr r3, [r3, #0] 8008cd6: 4a64 ldr r2, [pc, #400] @ (8008e68 ) 8008cd8: 4293 cmp r3, r2 8008cda: d009 beq.n 8008cf0 8008cdc: 68fb ldr r3, [r7, #12] 8008cde: 681b ldr r3, [r3, #0] 8008ce0: 4a62 ldr r2, [pc, #392] @ (8008e6c ) 8008ce2: 4293 cmp r3, r2 8008ce4: d004 beq.n 8008cf0 8008ce6: 68fb ldr r3, [r7, #12] 8008ce8: 681b ldr r3, [r3, #0] 8008cea: 4a61 ldr r2, [pc, #388] @ (8008e70 ) 8008cec: 4293 cmp r3, r2 8008cee: d101 bne.n 8008cf4 8008cf0: 2301 movs r3, #1 8008cf2: e000 b.n 8008cf6 8008cf4: 2300 movs r3, #0 8008cf6: 2b00 cmp r3, #0 8008cf8: d01a beq.n 8008d30 { /* Check if DMAMUX Synchronization is enabled */ if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) 8008cfa: 68fb ldr r3, [r7, #12] 8008cfc: 6e1b ldr r3, [r3, #96] @ 0x60 8008cfe: 681b ldr r3, [r3, #0] 8008d00: f403 3380 and.w r3, r3, #65536 @ 0x10000 8008d04: 2b00 cmp r3, #0 8008d06: d007 beq.n 8008d18 { /* Enable DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; 8008d08: 68fb ldr r3, [r7, #12] 8008d0a: 6e1b ldr r3, [r3, #96] @ 0x60 8008d0c: 681a ldr r2, [r3, #0] 8008d0e: 68fb ldr r3, [r7, #12] 8008d10: 6e1b ldr r3, [r3, #96] @ 0x60 8008d12: f442 7280 orr.w r2, r2, #256 @ 0x100 8008d16: 601a str r2, [r3, #0] } if(hdma->DMAmuxRequestGen != 0U) 8008d18: 68fb ldr r3, [r7, #12] 8008d1a: 6edb ldr r3, [r3, #108] @ 0x6c 8008d1c: 2b00 cmp r3, #0 8008d1e: d007 beq.n 8008d30 { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 8008d20: 68fb ldr r3, [r7, #12] 8008d22: 6edb ldr r3, [r3, #108] @ 0x6c 8008d24: 681a ldr r2, [r3, #0] 8008d26: 68fb ldr r3, [r7, #12] 8008d28: 6edb ldr r3, [r3, #108] @ 0x6c 8008d2a: f442 7280 orr.w r2, r2, #256 @ 0x100 8008d2e: 601a str r2, [r3, #0] } } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8008d30: 68fb ldr r3, [r7, #12] 8008d32: 681b ldr r3, [r3, #0] 8008d34: 4a37 ldr r2, [pc, #220] @ (8008e14 ) 8008d36: 4293 cmp r3, r2 8008d38: d04a beq.n 8008dd0 8008d3a: 68fb ldr r3, [r7, #12] 8008d3c: 681b ldr r3, [r3, #0] 8008d3e: 4a36 ldr r2, [pc, #216] @ (8008e18 ) 8008d40: 4293 cmp r3, r2 8008d42: d045 beq.n 8008dd0 8008d44: 68fb ldr r3, [r7, #12] 8008d46: 681b ldr r3, [r3, #0] 8008d48: 4a34 ldr r2, [pc, #208] @ (8008e1c ) 8008d4a: 4293 cmp r3, r2 8008d4c: d040 beq.n 8008dd0 8008d4e: 68fb ldr r3, [r7, #12] 8008d50: 681b ldr r3, [r3, #0] 8008d52: 4a33 ldr r2, [pc, #204] @ (8008e20 ) 8008d54: 4293 cmp r3, r2 8008d56: d03b beq.n 8008dd0 8008d58: 68fb ldr r3, [r7, #12] 8008d5a: 681b ldr r3, [r3, #0] 8008d5c: 4a31 ldr r2, [pc, #196] @ (8008e24 ) 8008d5e: 4293 cmp r3, r2 8008d60: d036 beq.n 8008dd0 8008d62: 68fb ldr r3, [r7, #12] 8008d64: 681b ldr r3, [r3, #0] 8008d66: 4a30 ldr r2, [pc, #192] @ (8008e28 ) 8008d68: 4293 cmp r3, r2 8008d6a: d031 beq.n 8008dd0 8008d6c: 68fb ldr r3, [r7, #12] 8008d6e: 681b ldr r3, [r3, #0] 8008d70: 4a2e ldr r2, [pc, #184] @ (8008e2c ) 8008d72: 4293 cmp r3, r2 8008d74: d02c beq.n 8008dd0 8008d76: 68fb ldr r3, [r7, #12] 8008d78: 681b ldr r3, [r3, #0] 8008d7a: 4a2d ldr r2, [pc, #180] @ (8008e30 ) 8008d7c: 4293 cmp r3, r2 8008d7e: d027 beq.n 8008dd0 8008d80: 68fb ldr r3, [r7, #12] 8008d82: 681b ldr r3, [r3, #0] 8008d84: 4a2b ldr r2, [pc, #172] @ (8008e34 ) 8008d86: 4293 cmp r3, r2 8008d88: d022 beq.n 8008dd0 8008d8a: 68fb ldr r3, [r7, #12] 8008d8c: 681b ldr r3, [r3, #0] 8008d8e: 4a2a ldr r2, [pc, #168] @ (8008e38 ) 8008d90: 4293 cmp r3, r2 8008d92: d01d beq.n 8008dd0 8008d94: 68fb ldr r3, [r7, #12] 8008d96: 681b ldr r3, [r3, #0] 8008d98: 4a28 ldr r2, [pc, #160] @ (8008e3c ) 8008d9a: 4293 cmp r3, r2 8008d9c: d018 beq.n 8008dd0 8008d9e: 68fb ldr r3, [r7, #12] 8008da0: 681b ldr r3, [r3, #0] 8008da2: 4a27 ldr r2, [pc, #156] @ (8008e40 ) 8008da4: 4293 cmp r3, r2 8008da6: d013 beq.n 8008dd0 8008da8: 68fb ldr r3, [r7, #12] 8008daa: 681b ldr r3, [r3, #0] 8008dac: 4a25 ldr r2, [pc, #148] @ (8008e44 ) 8008dae: 4293 cmp r3, r2 8008db0: d00e beq.n 8008dd0 8008db2: 68fb ldr r3, [r7, #12] 8008db4: 681b ldr r3, [r3, #0] 8008db6: 4a24 ldr r2, [pc, #144] @ (8008e48 ) 8008db8: 4293 cmp r3, r2 8008dba: d009 beq.n 8008dd0 8008dbc: 68fb ldr r3, [r7, #12] 8008dbe: 681b ldr r3, [r3, #0] 8008dc0: 4a22 ldr r2, [pc, #136] @ (8008e4c ) 8008dc2: 4293 cmp r3, r2 8008dc4: d004 beq.n 8008dd0 8008dc6: 68fb ldr r3, [r7, #12] 8008dc8: 681b ldr r3, [r3, #0] 8008dca: 4a21 ldr r2, [pc, #132] @ (8008e50 ) 8008dcc: 4293 cmp r3, r2 8008dce: d108 bne.n 8008de2 8008dd0: 68fb ldr r3, [r7, #12] 8008dd2: 681b ldr r3, [r3, #0] 8008dd4: 681a ldr r2, [r3, #0] 8008dd6: 68fb ldr r3, [r7, #12] 8008dd8: 681b ldr r3, [r3, #0] 8008dda: f042 0201 orr.w r2, r2, #1 8008dde: 601a str r2, [r3, #0] 8008de0: e012 b.n 8008e08 8008de2: 68fb ldr r3, [r7, #12] 8008de4: 681b ldr r3, [r3, #0] 8008de6: 681a ldr r2, [r3, #0] 8008de8: 68fb ldr r3, [r7, #12] 8008dea: 681b ldr r3, [r3, #0] 8008dec: f042 0201 orr.w r2, r2, #1 8008df0: 601a str r2, [r3, #0] 8008df2: e009 b.n 8008e08 } else { /* Set the error code to busy */ hdma->ErrorCode = HAL_DMA_ERROR_BUSY; 8008df4: 68fb ldr r3, [r7, #12] 8008df6: f44f 6200 mov.w r2, #2048 @ 0x800 8008dfa: 655a str r2, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hdma); 8008dfc: 68fb ldr r3, [r7, #12] 8008dfe: 2200 movs r2, #0 8008e00: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Return error status */ status = HAL_ERROR; 8008e04: 2301 movs r3, #1 8008e06: 75fb strb r3, [r7, #23] } return status; 8008e08: 7dfb ldrb r3, [r7, #23] } 8008e0a: 4618 mov r0, r3 8008e0c: 3718 adds r7, #24 8008e0e: 46bd mov sp, r7 8008e10: bd80 pop {r7, pc} 8008e12: bf00 nop 8008e14: 40020010 .word 0x40020010 8008e18: 40020028 .word 0x40020028 8008e1c: 40020040 .word 0x40020040 8008e20: 40020058 .word 0x40020058 8008e24: 40020070 .word 0x40020070 8008e28: 40020088 .word 0x40020088 8008e2c: 400200a0 .word 0x400200a0 8008e30: 400200b8 .word 0x400200b8 8008e34: 40020410 .word 0x40020410 8008e38: 40020428 .word 0x40020428 8008e3c: 40020440 .word 0x40020440 8008e40: 40020458 .word 0x40020458 8008e44: 40020470 .word 0x40020470 8008e48: 40020488 .word 0x40020488 8008e4c: 400204a0 .word 0x400204a0 8008e50: 400204b8 .word 0x400204b8 8008e54: 58025408 .word 0x58025408 8008e58: 5802541c .word 0x5802541c 8008e5c: 58025430 .word 0x58025430 8008e60: 58025444 .word 0x58025444 8008e64: 58025458 .word 0x58025458 8008e68: 5802546c .word 0x5802546c 8008e6c: 58025480 .word 0x58025480 8008e70: 58025494 .word 0x58025494 08008e74 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8008e74: b580 push {r7, lr} 8008e76: b086 sub sp, #24 8008e78: af00 add r7, sp, #0 8008e7a: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; const __IO uint32_t *enableRegister; uint32_t tickstart = HAL_GetTick(); 8008e7c: f7fc fe98 bl 8005bb0 8008e80: 6138 str r0, [r7, #16] /* Check the DMA peripheral handle */ if(hdma == NULL) 8008e82: 687b ldr r3, [r7, #4] 8008e84: 2b00 cmp r3, #0 8008e86: d101 bne.n 8008e8c { return HAL_ERROR; 8008e88: 2301 movs r3, #1 8008e8a: e2dc b.n 8009446 } /* Check the DMA peripheral state */ if(hdma->State != HAL_DMA_STATE_BUSY) 8008e8c: 687b ldr r3, [r7, #4] 8008e8e: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8008e92: b2db uxtb r3, r3 8008e94: 2b02 cmp r3, #2 8008e96: d008 beq.n 8008eaa { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8008e98: 687b ldr r3, [r7, #4] 8008e9a: 2280 movs r2, #128 @ 0x80 8008e9c: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8008e9e: 687b ldr r3, [r7, #4] 8008ea0: 2200 movs r2, #0 8008ea2: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8008ea6: 2301 movs r3, #1 8008ea8: e2cd b.n 8009446 } else { /* Disable all the transfer interrupts */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8008eaa: 687b ldr r3, [r7, #4] 8008eac: 681b ldr r3, [r3, #0] 8008eae: 4a76 ldr r2, [pc, #472] @ (8009088 ) 8008eb0: 4293 cmp r3, r2 8008eb2: d04a beq.n 8008f4a 8008eb4: 687b ldr r3, [r7, #4] 8008eb6: 681b ldr r3, [r3, #0] 8008eb8: 4a74 ldr r2, [pc, #464] @ (800908c ) 8008eba: 4293 cmp r3, r2 8008ebc: d045 beq.n 8008f4a 8008ebe: 687b ldr r3, [r7, #4] 8008ec0: 681b ldr r3, [r3, #0] 8008ec2: 4a73 ldr r2, [pc, #460] @ (8009090 ) 8008ec4: 4293 cmp r3, r2 8008ec6: d040 beq.n 8008f4a 8008ec8: 687b ldr r3, [r7, #4] 8008eca: 681b ldr r3, [r3, #0] 8008ecc: 4a71 ldr r2, [pc, #452] @ (8009094 ) 8008ece: 4293 cmp r3, r2 8008ed0: d03b beq.n 8008f4a 8008ed2: 687b ldr r3, [r7, #4] 8008ed4: 681b ldr r3, [r3, #0] 8008ed6: 4a70 ldr r2, [pc, #448] @ (8009098 ) 8008ed8: 4293 cmp r3, r2 8008eda: d036 beq.n 8008f4a 8008edc: 687b ldr r3, [r7, #4] 8008ede: 681b ldr r3, [r3, #0] 8008ee0: 4a6e ldr r2, [pc, #440] @ (800909c ) 8008ee2: 4293 cmp r3, r2 8008ee4: d031 beq.n 8008f4a 8008ee6: 687b ldr r3, [r7, #4] 8008ee8: 681b ldr r3, [r3, #0] 8008eea: 4a6d ldr r2, [pc, #436] @ (80090a0 ) 8008eec: 4293 cmp r3, r2 8008eee: d02c beq.n 8008f4a 8008ef0: 687b ldr r3, [r7, #4] 8008ef2: 681b ldr r3, [r3, #0] 8008ef4: 4a6b ldr r2, [pc, #428] @ (80090a4 ) 8008ef6: 4293 cmp r3, r2 8008ef8: d027 beq.n 8008f4a 8008efa: 687b ldr r3, [r7, #4] 8008efc: 681b ldr r3, [r3, #0] 8008efe: 4a6a ldr r2, [pc, #424] @ (80090a8 ) 8008f00: 4293 cmp r3, r2 8008f02: d022 beq.n 8008f4a 8008f04: 687b ldr r3, [r7, #4] 8008f06: 681b ldr r3, [r3, #0] 8008f08: 4a68 ldr r2, [pc, #416] @ (80090ac ) 8008f0a: 4293 cmp r3, r2 8008f0c: d01d beq.n 8008f4a 8008f0e: 687b ldr r3, [r7, #4] 8008f10: 681b ldr r3, [r3, #0] 8008f12: 4a67 ldr r2, [pc, #412] @ (80090b0 ) 8008f14: 4293 cmp r3, r2 8008f16: d018 beq.n 8008f4a 8008f18: 687b ldr r3, [r7, #4] 8008f1a: 681b ldr r3, [r3, #0] 8008f1c: 4a65 ldr r2, [pc, #404] @ (80090b4 ) 8008f1e: 4293 cmp r3, r2 8008f20: d013 beq.n 8008f4a 8008f22: 687b ldr r3, [r7, #4] 8008f24: 681b ldr r3, [r3, #0] 8008f26: 4a64 ldr r2, [pc, #400] @ (80090b8 ) 8008f28: 4293 cmp r3, r2 8008f2a: d00e beq.n 8008f4a 8008f2c: 687b ldr r3, [r7, #4] 8008f2e: 681b ldr r3, [r3, #0] 8008f30: 4a62 ldr r2, [pc, #392] @ (80090bc ) 8008f32: 4293 cmp r3, r2 8008f34: d009 beq.n 8008f4a 8008f36: 687b ldr r3, [r7, #4] 8008f38: 681b ldr r3, [r3, #0] 8008f3a: 4a61 ldr r2, [pc, #388] @ (80090c0 ) 8008f3c: 4293 cmp r3, r2 8008f3e: d004 beq.n 8008f4a 8008f40: 687b ldr r3, [r7, #4] 8008f42: 681b ldr r3, [r3, #0] 8008f44: 4a5f ldr r2, [pc, #380] @ (80090c4 ) 8008f46: 4293 cmp r3, r2 8008f48: d101 bne.n 8008f4e 8008f4a: 2301 movs r3, #1 8008f4c: e000 b.n 8008f50 8008f4e: 2300 movs r3, #0 8008f50: 2b00 cmp r3, #0 8008f52: d013 beq.n 8008f7c { /* Disable DMA All Interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 8008f54: 687b ldr r3, [r7, #4] 8008f56: 681b ldr r3, [r3, #0] 8008f58: 681a ldr r2, [r3, #0] 8008f5a: 687b ldr r3, [r7, #4] 8008f5c: 681b ldr r3, [r3, #0] 8008f5e: f022 021e bic.w r2, r2, #30 8008f62: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 8008f64: 687b ldr r3, [r7, #4] 8008f66: 681b ldr r3, [r3, #0] 8008f68: 695a ldr r2, [r3, #20] 8008f6a: 687b ldr r3, [r7, #4] 8008f6c: 681b ldr r3, [r3, #0] 8008f6e: f022 0280 bic.w r2, r2, #128 @ 0x80 8008f72: 615a str r2, [r3, #20] enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); 8008f74: 687b ldr r3, [r7, #4] 8008f76: 681b ldr r3, [r3, #0] 8008f78: 617b str r3, [r7, #20] 8008f7a: e00a b.n 8008f92 } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 8008f7c: 687b ldr r3, [r7, #4] 8008f7e: 681b ldr r3, [r3, #0] 8008f80: 681a ldr r2, [r3, #0] 8008f82: 687b ldr r3, [r7, #4] 8008f84: 681b ldr r3, [r3, #0] 8008f86: f022 020e bic.w r2, r2, #14 8008f8a: 601a str r2, [r3, #0] enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); 8008f8c: 687b ldr r3, [r7, #4] 8008f8e: 681b ldr r3, [r3, #0] 8008f90: 617b str r3, [r7, #20] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8008f92: 687b ldr r3, [r7, #4] 8008f94: 681b ldr r3, [r3, #0] 8008f96: 4a3c ldr r2, [pc, #240] @ (8009088 ) 8008f98: 4293 cmp r3, r2 8008f9a: d072 beq.n 8009082 8008f9c: 687b ldr r3, [r7, #4] 8008f9e: 681b ldr r3, [r3, #0] 8008fa0: 4a3a ldr r2, [pc, #232] @ (800908c ) 8008fa2: 4293 cmp r3, r2 8008fa4: d06d beq.n 8009082 8008fa6: 687b ldr r3, [r7, #4] 8008fa8: 681b ldr r3, [r3, #0] 8008faa: 4a39 ldr r2, [pc, #228] @ (8009090 ) 8008fac: 4293 cmp r3, r2 8008fae: d068 beq.n 8009082 8008fb0: 687b ldr r3, [r7, #4] 8008fb2: 681b ldr r3, [r3, #0] 8008fb4: 4a37 ldr r2, [pc, #220] @ (8009094 ) 8008fb6: 4293 cmp r3, r2 8008fb8: d063 beq.n 8009082 8008fba: 687b ldr r3, [r7, #4] 8008fbc: 681b ldr r3, [r3, #0] 8008fbe: 4a36 ldr r2, [pc, #216] @ (8009098 ) 8008fc0: 4293 cmp r3, r2 8008fc2: d05e beq.n 8009082 8008fc4: 687b ldr r3, [r7, #4] 8008fc6: 681b ldr r3, [r3, #0] 8008fc8: 4a34 ldr r2, [pc, #208] @ (800909c ) 8008fca: 4293 cmp r3, r2 8008fcc: d059 beq.n 8009082 8008fce: 687b ldr r3, [r7, #4] 8008fd0: 681b ldr r3, [r3, #0] 8008fd2: 4a33 ldr r2, [pc, #204] @ (80090a0 ) 8008fd4: 4293 cmp r3, r2 8008fd6: d054 beq.n 8009082 8008fd8: 687b ldr r3, [r7, #4] 8008fda: 681b ldr r3, [r3, #0] 8008fdc: 4a31 ldr r2, [pc, #196] @ (80090a4 ) 8008fde: 4293 cmp r3, r2 8008fe0: d04f beq.n 8009082 8008fe2: 687b ldr r3, [r7, #4] 8008fe4: 681b ldr r3, [r3, #0] 8008fe6: 4a30 ldr r2, [pc, #192] @ (80090a8 ) 8008fe8: 4293 cmp r3, r2 8008fea: d04a beq.n 8009082 8008fec: 687b ldr r3, [r7, #4] 8008fee: 681b ldr r3, [r3, #0] 8008ff0: 4a2e ldr r2, [pc, #184] @ (80090ac ) 8008ff2: 4293 cmp r3, r2 8008ff4: d045 beq.n 8009082 8008ff6: 687b ldr r3, [r7, #4] 8008ff8: 681b ldr r3, [r3, #0] 8008ffa: 4a2d ldr r2, [pc, #180] @ (80090b0 ) 8008ffc: 4293 cmp r3, r2 8008ffe: d040 beq.n 8009082 8009000: 687b ldr r3, [r7, #4] 8009002: 681b ldr r3, [r3, #0] 8009004: 4a2b ldr r2, [pc, #172] @ (80090b4 ) 8009006: 4293 cmp r3, r2 8009008: d03b beq.n 8009082 800900a: 687b ldr r3, [r7, #4] 800900c: 681b ldr r3, [r3, #0] 800900e: 4a2a ldr r2, [pc, #168] @ (80090b8 ) 8009010: 4293 cmp r3, r2 8009012: d036 beq.n 8009082 8009014: 687b ldr r3, [r7, #4] 8009016: 681b ldr r3, [r3, #0] 8009018: 4a28 ldr r2, [pc, #160] @ (80090bc ) 800901a: 4293 cmp r3, r2 800901c: d031 beq.n 8009082 800901e: 687b ldr r3, [r7, #4] 8009020: 681b ldr r3, [r3, #0] 8009022: 4a27 ldr r2, [pc, #156] @ (80090c0 ) 8009024: 4293 cmp r3, r2 8009026: d02c beq.n 8009082 8009028: 687b ldr r3, [r7, #4] 800902a: 681b ldr r3, [r3, #0] 800902c: 4a25 ldr r2, [pc, #148] @ (80090c4 ) 800902e: 4293 cmp r3, r2 8009030: d027 beq.n 8009082 8009032: 687b ldr r3, [r7, #4] 8009034: 681b ldr r3, [r3, #0] 8009036: 4a24 ldr r2, [pc, #144] @ (80090c8 ) 8009038: 4293 cmp r3, r2 800903a: d022 beq.n 8009082 800903c: 687b ldr r3, [r7, #4] 800903e: 681b ldr r3, [r3, #0] 8009040: 4a22 ldr r2, [pc, #136] @ (80090cc ) 8009042: 4293 cmp r3, r2 8009044: d01d beq.n 8009082 8009046: 687b ldr r3, [r7, #4] 8009048: 681b ldr r3, [r3, #0] 800904a: 4a21 ldr r2, [pc, #132] @ (80090d0 ) 800904c: 4293 cmp r3, r2 800904e: d018 beq.n 8009082 8009050: 687b ldr r3, [r7, #4] 8009052: 681b ldr r3, [r3, #0] 8009054: 4a1f ldr r2, [pc, #124] @ (80090d4 ) 8009056: 4293 cmp r3, r2 8009058: d013 beq.n 8009082 800905a: 687b ldr r3, [r7, #4] 800905c: 681b ldr r3, [r3, #0] 800905e: 4a1e ldr r2, [pc, #120] @ (80090d8 ) 8009060: 4293 cmp r3, r2 8009062: d00e beq.n 8009082 8009064: 687b ldr r3, [r7, #4] 8009066: 681b ldr r3, [r3, #0] 8009068: 4a1c ldr r2, [pc, #112] @ (80090dc ) 800906a: 4293 cmp r3, r2 800906c: d009 beq.n 8009082 800906e: 687b ldr r3, [r7, #4] 8009070: 681b ldr r3, [r3, #0] 8009072: 4a1b ldr r2, [pc, #108] @ (80090e0 ) 8009074: 4293 cmp r3, r2 8009076: d004 beq.n 8009082 8009078: 687b ldr r3, [r7, #4] 800907a: 681b ldr r3, [r3, #0] 800907c: 4a19 ldr r2, [pc, #100] @ (80090e4 ) 800907e: 4293 cmp r3, r2 8009080: d132 bne.n 80090e8 8009082: 2301 movs r3, #1 8009084: e031 b.n 80090ea 8009086: bf00 nop 8009088: 40020010 .word 0x40020010 800908c: 40020028 .word 0x40020028 8009090: 40020040 .word 0x40020040 8009094: 40020058 .word 0x40020058 8009098: 40020070 .word 0x40020070 800909c: 40020088 .word 0x40020088 80090a0: 400200a0 .word 0x400200a0 80090a4: 400200b8 .word 0x400200b8 80090a8: 40020410 .word 0x40020410 80090ac: 40020428 .word 0x40020428 80090b0: 40020440 .word 0x40020440 80090b4: 40020458 .word 0x40020458 80090b8: 40020470 .word 0x40020470 80090bc: 40020488 .word 0x40020488 80090c0: 400204a0 .word 0x400204a0 80090c4: 400204b8 .word 0x400204b8 80090c8: 58025408 .word 0x58025408 80090cc: 5802541c .word 0x5802541c 80090d0: 58025430 .word 0x58025430 80090d4: 58025444 .word 0x58025444 80090d8: 58025458 .word 0x58025458 80090dc: 5802546c .word 0x5802546c 80090e0: 58025480 .word 0x58025480 80090e4: 58025494 .word 0x58025494 80090e8: 2300 movs r3, #0 80090ea: 2b00 cmp r3, #0 80090ec: d007 beq.n 80090fe { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 80090ee: 687b ldr r3, [r7, #4] 80090f0: 6e1b ldr r3, [r3, #96] @ 0x60 80090f2: 681a ldr r2, [r3, #0] 80090f4: 687b ldr r3, [r7, #4] 80090f6: 6e1b ldr r3, [r3, #96] @ 0x60 80090f8: f422 7280 bic.w r2, r2, #256 @ 0x100 80090fc: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80090fe: 687b ldr r3, [r7, #4] 8009100: 681b ldr r3, [r3, #0] 8009102: 4a6d ldr r2, [pc, #436] @ (80092b8 ) 8009104: 4293 cmp r3, r2 8009106: d04a beq.n 800919e 8009108: 687b ldr r3, [r7, #4] 800910a: 681b ldr r3, [r3, #0] 800910c: 4a6b ldr r2, [pc, #428] @ (80092bc ) 800910e: 4293 cmp r3, r2 8009110: d045 beq.n 800919e 8009112: 687b ldr r3, [r7, #4] 8009114: 681b ldr r3, [r3, #0] 8009116: 4a6a ldr r2, [pc, #424] @ (80092c0 ) 8009118: 4293 cmp r3, r2 800911a: d040 beq.n 800919e 800911c: 687b ldr r3, [r7, #4] 800911e: 681b ldr r3, [r3, #0] 8009120: 4a68 ldr r2, [pc, #416] @ (80092c4 ) 8009122: 4293 cmp r3, r2 8009124: d03b beq.n 800919e 8009126: 687b ldr r3, [r7, #4] 8009128: 681b ldr r3, [r3, #0] 800912a: 4a67 ldr r2, [pc, #412] @ (80092c8 ) 800912c: 4293 cmp r3, r2 800912e: d036 beq.n 800919e 8009130: 687b ldr r3, [r7, #4] 8009132: 681b ldr r3, [r3, #0] 8009134: 4a65 ldr r2, [pc, #404] @ (80092cc ) 8009136: 4293 cmp r3, r2 8009138: d031 beq.n 800919e 800913a: 687b ldr r3, [r7, #4] 800913c: 681b ldr r3, [r3, #0] 800913e: 4a64 ldr r2, [pc, #400] @ (80092d0 ) 8009140: 4293 cmp r3, r2 8009142: d02c beq.n 800919e 8009144: 687b ldr r3, [r7, #4] 8009146: 681b ldr r3, [r3, #0] 8009148: 4a62 ldr r2, [pc, #392] @ (80092d4 ) 800914a: 4293 cmp r3, r2 800914c: d027 beq.n 800919e 800914e: 687b ldr r3, [r7, #4] 8009150: 681b ldr r3, [r3, #0] 8009152: 4a61 ldr r2, [pc, #388] @ (80092d8 ) 8009154: 4293 cmp r3, r2 8009156: d022 beq.n 800919e 8009158: 687b ldr r3, [r7, #4] 800915a: 681b ldr r3, [r3, #0] 800915c: 4a5f ldr r2, [pc, #380] @ (80092dc ) 800915e: 4293 cmp r3, r2 8009160: d01d beq.n 800919e 8009162: 687b ldr r3, [r7, #4] 8009164: 681b ldr r3, [r3, #0] 8009166: 4a5e ldr r2, [pc, #376] @ (80092e0 ) 8009168: 4293 cmp r3, r2 800916a: d018 beq.n 800919e 800916c: 687b ldr r3, [r7, #4] 800916e: 681b ldr r3, [r3, #0] 8009170: 4a5c ldr r2, [pc, #368] @ (80092e4 ) 8009172: 4293 cmp r3, r2 8009174: d013 beq.n 800919e 8009176: 687b ldr r3, [r7, #4] 8009178: 681b ldr r3, [r3, #0] 800917a: 4a5b ldr r2, [pc, #364] @ (80092e8 ) 800917c: 4293 cmp r3, r2 800917e: d00e beq.n 800919e 8009180: 687b ldr r3, [r7, #4] 8009182: 681b ldr r3, [r3, #0] 8009184: 4a59 ldr r2, [pc, #356] @ (80092ec ) 8009186: 4293 cmp r3, r2 8009188: d009 beq.n 800919e 800918a: 687b ldr r3, [r7, #4] 800918c: 681b ldr r3, [r3, #0] 800918e: 4a58 ldr r2, [pc, #352] @ (80092f0 ) 8009190: 4293 cmp r3, r2 8009192: d004 beq.n 800919e 8009194: 687b ldr r3, [r7, #4] 8009196: 681b ldr r3, [r3, #0] 8009198: 4a56 ldr r2, [pc, #344] @ (80092f4 ) 800919a: 4293 cmp r3, r2 800919c: d108 bne.n 80091b0 800919e: 687b ldr r3, [r7, #4] 80091a0: 681b ldr r3, [r3, #0] 80091a2: 681a ldr r2, [r3, #0] 80091a4: 687b ldr r3, [r7, #4] 80091a6: 681b ldr r3, [r3, #0] 80091a8: f022 0201 bic.w r2, r2, #1 80091ac: 601a str r2, [r3, #0] 80091ae: e007 b.n 80091c0 80091b0: 687b ldr r3, [r7, #4] 80091b2: 681b ldr r3, [r3, #0] 80091b4: 681a ldr r2, [r3, #0] 80091b6: 687b ldr r3, [r7, #4] 80091b8: 681b ldr r3, [r3, #0] 80091ba: f022 0201 bic.w r2, r2, #1 80091be: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while(((*enableRegister) & DMA_SxCR_EN) != 0U) 80091c0: e013 b.n 80091ea { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 80091c2: f7fc fcf5 bl 8005bb0 80091c6: 4602 mov r2, r0 80091c8: 693b ldr r3, [r7, #16] 80091ca: 1ad3 subs r3, r2, r3 80091cc: 2b05 cmp r3, #5 80091ce: d90c bls.n 80091ea { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 80091d0: 687b ldr r3, [r7, #4] 80091d2: 2220 movs r2, #32 80091d4: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 80091d6: 687b ldr r3, [r7, #4] 80091d8: 2203 movs r2, #3 80091da: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80091de: 687b ldr r3, [r7, #4] 80091e0: 2200 movs r2, #0 80091e2: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 80091e6: 2301 movs r3, #1 80091e8: e12d b.n 8009446 while(((*enableRegister) & DMA_SxCR_EN) != 0U) 80091ea: 697b ldr r3, [r7, #20] 80091ec: 681b ldr r3, [r3, #0] 80091ee: f003 0301 and.w r3, r3, #1 80091f2: 2b00 cmp r3, #0 80091f4: d1e5 bne.n 80091c2 } } /* Clear all interrupt flags at correct offset within the register */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80091f6: 687b ldr r3, [r7, #4] 80091f8: 681b ldr r3, [r3, #0] 80091fa: 4a2f ldr r2, [pc, #188] @ (80092b8 ) 80091fc: 4293 cmp r3, r2 80091fe: d04a beq.n 8009296 8009200: 687b ldr r3, [r7, #4] 8009202: 681b ldr r3, [r3, #0] 8009204: 4a2d ldr r2, [pc, #180] @ (80092bc ) 8009206: 4293 cmp r3, r2 8009208: d045 beq.n 8009296 800920a: 687b ldr r3, [r7, #4] 800920c: 681b ldr r3, [r3, #0] 800920e: 4a2c ldr r2, [pc, #176] @ (80092c0 ) 8009210: 4293 cmp r3, r2 8009212: d040 beq.n 8009296 8009214: 687b ldr r3, [r7, #4] 8009216: 681b ldr r3, [r3, #0] 8009218: 4a2a ldr r2, [pc, #168] @ (80092c4 ) 800921a: 4293 cmp r3, r2 800921c: d03b beq.n 8009296 800921e: 687b ldr r3, [r7, #4] 8009220: 681b ldr r3, [r3, #0] 8009222: 4a29 ldr r2, [pc, #164] @ (80092c8 ) 8009224: 4293 cmp r3, r2 8009226: d036 beq.n 8009296 8009228: 687b ldr r3, [r7, #4] 800922a: 681b ldr r3, [r3, #0] 800922c: 4a27 ldr r2, [pc, #156] @ (80092cc ) 800922e: 4293 cmp r3, r2 8009230: d031 beq.n 8009296 8009232: 687b ldr r3, [r7, #4] 8009234: 681b ldr r3, [r3, #0] 8009236: 4a26 ldr r2, [pc, #152] @ (80092d0 ) 8009238: 4293 cmp r3, r2 800923a: d02c beq.n 8009296 800923c: 687b ldr r3, [r7, #4] 800923e: 681b ldr r3, [r3, #0] 8009240: 4a24 ldr r2, [pc, #144] @ (80092d4 ) 8009242: 4293 cmp r3, r2 8009244: d027 beq.n 8009296 8009246: 687b ldr r3, [r7, #4] 8009248: 681b ldr r3, [r3, #0] 800924a: 4a23 ldr r2, [pc, #140] @ (80092d8 ) 800924c: 4293 cmp r3, r2 800924e: d022 beq.n 8009296 8009250: 687b ldr r3, [r7, #4] 8009252: 681b ldr r3, [r3, #0] 8009254: 4a21 ldr r2, [pc, #132] @ (80092dc ) 8009256: 4293 cmp r3, r2 8009258: d01d beq.n 8009296 800925a: 687b ldr r3, [r7, #4] 800925c: 681b ldr r3, [r3, #0] 800925e: 4a20 ldr r2, [pc, #128] @ (80092e0 ) 8009260: 4293 cmp r3, r2 8009262: d018 beq.n 8009296 8009264: 687b ldr r3, [r7, #4] 8009266: 681b ldr r3, [r3, #0] 8009268: 4a1e ldr r2, [pc, #120] @ (80092e4 ) 800926a: 4293 cmp r3, r2 800926c: d013 beq.n 8009296 800926e: 687b ldr r3, [r7, #4] 8009270: 681b ldr r3, [r3, #0] 8009272: 4a1d ldr r2, [pc, #116] @ (80092e8 ) 8009274: 4293 cmp r3, r2 8009276: d00e beq.n 8009296 8009278: 687b ldr r3, [r7, #4] 800927a: 681b ldr r3, [r3, #0] 800927c: 4a1b ldr r2, [pc, #108] @ (80092ec ) 800927e: 4293 cmp r3, r2 8009280: d009 beq.n 8009296 8009282: 687b ldr r3, [r7, #4] 8009284: 681b ldr r3, [r3, #0] 8009286: 4a1a ldr r2, [pc, #104] @ (80092f0 ) 8009288: 4293 cmp r3, r2 800928a: d004 beq.n 8009296 800928c: 687b ldr r3, [r7, #4] 800928e: 681b ldr r3, [r3, #0] 8009290: 4a18 ldr r2, [pc, #96] @ (80092f4 ) 8009292: 4293 cmp r3, r2 8009294: d101 bne.n 800929a 8009296: 2301 movs r3, #1 8009298: e000 b.n 800929c 800929a: 2300 movs r3, #0 800929c: 2b00 cmp r3, #0 800929e: d02b beq.n 80092f8 { regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 80092a0: 687b ldr r3, [r7, #4] 80092a2: 6d9b ldr r3, [r3, #88] @ 0x58 80092a4: 60bb str r3, [r7, #8] regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 80092a6: 687b ldr r3, [r7, #4] 80092a8: 6ddb ldr r3, [r3, #92] @ 0x5c 80092aa: f003 031f and.w r3, r3, #31 80092ae: 223f movs r2, #63 @ 0x3f 80092b0: 409a lsls r2, r3 80092b2: 68bb ldr r3, [r7, #8] 80092b4: 609a str r2, [r3, #8] 80092b6: e02a b.n 800930e 80092b8: 40020010 .word 0x40020010 80092bc: 40020028 .word 0x40020028 80092c0: 40020040 .word 0x40020040 80092c4: 40020058 .word 0x40020058 80092c8: 40020070 .word 0x40020070 80092cc: 40020088 .word 0x40020088 80092d0: 400200a0 .word 0x400200a0 80092d4: 400200b8 .word 0x400200b8 80092d8: 40020410 .word 0x40020410 80092dc: 40020428 .word 0x40020428 80092e0: 40020440 .word 0x40020440 80092e4: 40020458 .word 0x40020458 80092e8: 40020470 .word 0x40020470 80092ec: 40020488 .word 0x40020488 80092f0: 400204a0 .word 0x400204a0 80092f4: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 80092f8: 687b ldr r3, [r7, #4] 80092fa: 6d9b ldr r3, [r3, #88] @ 0x58 80092fc: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 80092fe: 687b ldr r3, [r7, #4] 8009300: 6ddb ldr r3, [r3, #92] @ 0x5c 8009302: f003 031f and.w r3, r3, #31 8009306: 2201 movs r2, #1 8009308: 409a lsls r2, r3 800930a: 68fb ldr r3, [r7, #12] 800930c: 605a str r2, [r3, #4] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800930e: 687b ldr r3, [r7, #4] 8009310: 681b ldr r3, [r3, #0] 8009312: 4a4f ldr r2, [pc, #316] @ (8009450 ) 8009314: 4293 cmp r3, r2 8009316: d072 beq.n 80093fe 8009318: 687b ldr r3, [r7, #4] 800931a: 681b ldr r3, [r3, #0] 800931c: 4a4d ldr r2, [pc, #308] @ (8009454 ) 800931e: 4293 cmp r3, r2 8009320: d06d beq.n 80093fe 8009322: 687b ldr r3, [r7, #4] 8009324: 681b ldr r3, [r3, #0] 8009326: 4a4c ldr r2, [pc, #304] @ (8009458 ) 8009328: 4293 cmp r3, r2 800932a: d068 beq.n 80093fe 800932c: 687b ldr r3, [r7, #4] 800932e: 681b ldr r3, [r3, #0] 8009330: 4a4a ldr r2, [pc, #296] @ (800945c ) 8009332: 4293 cmp r3, r2 8009334: d063 beq.n 80093fe 8009336: 687b ldr r3, [r7, #4] 8009338: 681b ldr r3, [r3, #0] 800933a: 4a49 ldr r2, [pc, #292] @ (8009460 ) 800933c: 4293 cmp r3, r2 800933e: d05e beq.n 80093fe 8009340: 687b ldr r3, [r7, #4] 8009342: 681b ldr r3, [r3, #0] 8009344: 4a47 ldr r2, [pc, #284] @ (8009464 ) 8009346: 4293 cmp r3, r2 8009348: d059 beq.n 80093fe 800934a: 687b ldr r3, [r7, #4] 800934c: 681b ldr r3, [r3, #0] 800934e: 4a46 ldr r2, [pc, #280] @ (8009468 ) 8009350: 4293 cmp r3, r2 8009352: d054 beq.n 80093fe 8009354: 687b ldr r3, [r7, #4] 8009356: 681b ldr r3, [r3, #0] 8009358: 4a44 ldr r2, [pc, #272] @ (800946c ) 800935a: 4293 cmp r3, r2 800935c: d04f beq.n 80093fe 800935e: 687b ldr r3, [r7, #4] 8009360: 681b ldr r3, [r3, #0] 8009362: 4a43 ldr r2, [pc, #268] @ (8009470 ) 8009364: 4293 cmp r3, r2 8009366: d04a beq.n 80093fe 8009368: 687b ldr r3, [r7, #4] 800936a: 681b ldr r3, [r3, #0] 800936c: 4a41 ldr r2, [pc, #260] @ (8009474 ) 800936e: 4293 cmp r3, r2 8009370: d045 beq.n 80093fe 8009372: 687b ldr r3, [r7, #4] 8009374: 681b ldr r3, [r3, #0] 8009376: 4a40 ldr r2, [pc, #256] @ (8009478 ) 8009378: 4293 cmp r3, r2 800937a: d040 beq.n 80093fe 800937c: 687b ldr r3, [r7, #4] 800937e: 681b ldr r3, [r3, #0] 8009380: 4a3e ldr r2, [pc, #248] @ (800947c ) 8009382: 4293 cmp r3, r2 8009384: d03b beq.n 80093fe 8009386: 687b ldr r3, [r7, #4] 8009388: 681b ldr r3, [r3, #0] 800938a: 4a3d ldr r2, [pc, #244] @ (8009480 ) 800938c: 4293 cmp r3, r2 800938e: d036 beq.n 80093fe 8009390: 687b ldr r3, [r7, #4] 8009392: 681b ldr r3, [r3, #0] 8009394: 4a3b ldr r2, [pc, #236] @ (8009484 ) 8009396: 4293 cmp r3, r2 8009398: d031 beq.n 80093fe 800939a: 687b ldr r3, [r7, #4] 800939c: 681b ldr r3, [r3, #0] 800939e: 4a3a ldr r2, [pc, #232] @ (8009488 ) 80093a0: 4293 cmp r3, r2 80093a2: d02c beq.n 80093fe 80093a4: 687b ldr r3, [r7, #4] 80093a6: 681b ldr r3, [r3, #0] 80093a8: 4a38 ldr r2, [pc, #224] @ (800948c ) 80093aa: 4293 cmp r3, r2 80093ac: d027 beq.n 80093fe 80093ae: 687b ldr r3, [r7, #4] 80093b0: 681b ldr r3, [r3, #0] 80093b2: 4a37 ldr r2, [pc, #220] @ (8009490 ) 80093b4: 4293 cmp r3, r2 80093b6: d022 beq.n 80093fe 80093b8: 687b ldr r3, [r7, #4] 80093ba: 681b ldr r3, [r3, #0] 80093bc: 4a35 ldr r2, [pc, #212] @ (8009494 ) 80093be: 4293 cmp r3, r2 80093c0: d01d beq.n 80093fe 80093c2: 687b ldr r3, [r7, #4] 80093c4: 681b ldr r3, [r3, #0] 80093c6: 4a34 ldr r2, [pc, #208] @ (8009498 ) 80093c8: 4293 cmp r3, r2 80093ca: d018 beq.n 80093fe 80093cc: 687b ldr r3, [r7, #4] 80093ce: 681b ldr r3, [r3, #0] 80093d0: 4a32 ldr r2, [pc, #200] @ (800949c ) 80093d2: 4293 cmp r3, r2 80093d4: d013 beq.n 80093fe 80093d6: 687b ldr r3, [r7, #4] 80093d8: 681b ldr r3, [r3, #0] 80093da: 4a31 ldr r2, [pc, #196] @ (80094a0 ) 80093dc: 4293 cmp r3, r2 80093de: d00e beq.n 80093fe 80093e0: 687b ldr r3, [r7, #4] 80093e2: 681b ldr r3, [r3, #0] 80093e4: 4a2f ldr r2, [pc, #188] @ (80094a4 ) 80093e6: 4293 cmp r3, r2 80093e8: d009 beq.n 80093fe 80093ea: 687b ldr r3, [r7, #4] 80093ec: 681b ldr r3, [r3, #0] 80093ee: 4a2e ldr r2, [pc, #184] @ (80094a8 ) 80093f0: 4293 cmp r3, r2 80093f2: d004 beq.n 80093fe 80093f4: 687b ldr r3, [r7, #4] 80093f6: 681b ldr r3, [r3, #0] 80093f8: 4a2c ldr r2, [pc, #176] @ (80094ac ) 80093fa: 4293 cmp r3, r2 80093fc: d101 bne.n 8009402 80093fe: 2301 movs r3, #1 8009400: e000 b.n 8009404 8009402: 2300 movs r3, #0 8009404: 2b00 cmp r3, #0 8009406: d015 beq.n 8009434 { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8009408: 687b ldr r3, [r7, #4] 800940a: 6e5b ldr r3, [r3, #100] @ 0x64 800940c: 687a ldr r2, [r7, #4] 800940e: 6e92 ldr r2, [r2, #104] @ 0x68 8009410: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 8009412: 687b ldr r3, [r7, #4] 8009414: 6edb ldr r3, [r3, #108] @ 0x6c 8009416: 2b00 cmp r3, #0 8009418: d00c beq.n 8009434 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 800941a: 687b ldr r3, [r7, #4] 800941c: 6edb ldr r3, [r3, #108] @ 0x6c 800941e: 681a ldr r2, [r3, #0] 8009420: 687b ldr r3, [r7, #4] 8009422: 6edb ldr r3, [r3, #108] @ 0x6c 8009424: f422 7280 bic.w r2, r2, #256 @ 0x100 8009428: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 800942a: 687b ldr r3, [r7, #4] 800942c: 6f1b ldr r3, [r3, #112] @ 0x70 800942e: 687a ldr r2, [r7, #4] 8009430: 6f52 ldr r2, [r2, #116] @ 0x74 8009432: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8009434: 687b ldr r3, [r7, #4] 8009436: 2201 movs r2, #1 8009438: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800943c: 687b ldr r3, [r7, #4] 800943e: 2200 movs r2, #0 8009440: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 8009444: 2300 movs r3, #0 } 8009446: 4618 mov r0, r3 8009448: 3718 adds r7, #24 800944a: 46bd mov sp, r7 800944c: bd80 pop {r7, pc} 800944e: bf00 nop 8009450: 40020010 .word 0x40020010 8009454: 40020028 .word 0x40020028 8009458: 40020040 .word 0x40020040 800945c: 40020058 .word 0x40020058 8009460: 40020070 .word 0x40020070 8009464: 40020088 .word 0x40020088 8009468: 400200a0 .word 0x400200a0 800946c: 400200b8 .word 0x400200b8 8009470: 40020410 .word 0x40020410 8009474: 40020428 .word 0x40020428 8009478: 40020440 .word 0x40020440 800947c: 40020458 .word 0x40020458 8009480: 40020470 .word 0x40020470 8009484: 40020488 .word 0x40020488 8009488: 400204a0 .word 0x400204a0 800948c: 400204b8 .word 0x400204b8 8009490: 58025408 .word 0x58025408 8009494: 5802541c .word 0x5802541c 8009498: 58025430 .word 0x58025430 800949c: 58025444 .word 0x58025444 80094a0: 58025458 .word 0x58025458 80094a4: 5802546c .word 0x5802546c 80094a8: 58025480 .word 0x58025480 80094ac: 58025494 .word 0x58025494 080094b0 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 80094b0: b580 push {r7, lr} 80094b2: b084 sub sp, #16 80094b4: af00 add r7, sp, #0 80094b6: 6078 str r0, [r7, #4] BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 80094b8: 687b ldr r3, [r7, #4] 80094ba: 2b00 cmp r3, #0 80094bc: d101 bne.n 80094c2 { return HAL_ERROR; 80094be: 2301 movs r3, #1 80094c0: e237 b.n 8009932 } if(hdma->State != HAL_DMA_STATE_BUSY) 80094c2: 687b ldr r3, [r7, #4] 80094c4: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 80094c8: b2db uxtb r3, r3 80094ca: 2b02 cmp r3, #2 80094cc: d004 beq.n 80094d8 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80094ce: 687b ldr r3, [r7, #4] 80094d0: 2280 movs r2, #128 @ 0x80 80094d2: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 80094d4: 2301 movs r3, #1 80094d6: e22c b.n 8009932 } else { if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80094d8: 687b ldr r3, [r7, #4] 80094da: 681b ldr r3, [r3, #0] 80094dc: 4a5c ldr r2, [pc, #368] @ (8009650 ) 80094de: 4293 cmp r3, r2 80094e0: d04a beq.n 8009578 80094e2: 687b ldr r3, [r7, #4] 80094e4: 681b ldr r3, [r3, #0] 80094e6: 4a5b ldr r2, [pc, #364] @ (8009654 ) 80094e8: 4293 cmp r3, r2 80094ea: d045 beq.n 8009578 80094ec: 687b ldr r3, [r7, #4] 80094ee: 681b ldr r3, [r3, #0] 80094f0: 4a59 ldr r2, [pc, #356] @ (8009658 ) 80094f2: 4293 cmp r3, r2 80094f4: d040 beq.n 8009578 80094f6: 687b ldr r3, [r7, #4] 80094f8: 681b ldr r3, [r3, #0] 80094fa: 4a58 ldr r2, [pc, #352] @ (800965c ) 80094fc: 4293 cmp r3, r2 80094fe: d03b beq.n 8009578 8009500: 687b ldr r3, [r7, #4] 8009502: 681b ldr r3, [r3, #0] 8009504: 4a56 ldr r2, [pc, #344] @ (8009660 ) 8009506: 4293 cmp r3, r2 8009508: d036 beq.n 8009578 800950a: 687b ldr r3, [r7, #4] 800950c: 681b ldr r3, [r3, #0] 800950e: 4a55 ldr r2, [pc, #340] @ (8009664 ) 8009510: 4293 cmp r3, r2 8009512: d031 beq.n 8009578 8009514: 687b ldr r3, [r7, #4] 8009516: 681b ldr r3, [r3, #0] 8009518: 4a53 ldr r2, [pc, #332] @ (8009668 ) 800951a: 4293 cmp r3, r2 800951c: d02c beq.n 8009578 800951e: 687b ldr r3, [r7, #4] 8009520: 681b ldr r3, [r3, #0] 8009522: 4a52 ldr r2, [pc, #328] @ (800966c ) 8009524: 4293 cmp r3, r2 8009526: d027 beq.n 8009578 8009528: 687b ldr r3, [r7, #4] 800952a: 681b ldr r3, [r3, #0] 800952c: 4a50 ldr r2, [pc, #320] @ (8009670 ) 800952e: 4293 cmp r3, r2 8009530: d022 beq.n 8009578 8009532: 687b ldr r3, [r7, #4] 8009534: 681b ldr r3, [r3, #0] 8009536: 4a4f ldr r2, [pc, #316] @ (8009674 ) 8009538: 4293 cmp r3, r2 800953a: d01d beq.n 8009578 800953c: 687b ldr r3, [r7, #4] 800953e: 681b ldr r3, [r3, #0] 8009540: 4a4d ldr r2, [pc, #308] @ (8009678 ) 8009542: 4293 cmp r3, r2 8009544: d018 beq.n 8009578 8009546: 687b ldr r3, [r7, #4] 8009548: 681b ldr r3, [r3, #0] 800954a: 4a4c ldr r2, [pc, #304] @ (800967c ) 800954c: 4293 cmp r3, r2 800954e: d013 beq.n 8009578 8009550: 687b ldr r3, [r7, #4] 8009552: 681b ldr r3, [r3, #0] 8009554: 4a4a ldr r2, [pc, #296] @ (8009680 ) 8009556: 4293 cmp r3, r2 8009558: d00e beq.n 8009578 800955a: 687b ldr r3, [r7, #4] 800955c: 681b ldr r3, [r3, #0] 800955e: 4a49 ldr r2, [pc, #292] @ (8009684 ) 8009560: 4293 cmp r3, r2 8009562: d009 beq.n 8009578 8009564: 687b ldr r3, [r7, #4] 8009566: 681b ldr r3, [r3, #0] 8009568: 4a47 ldr r2, [pc, #284] @ (8009688 ) 800956a: 4293 cmp r3, r2 800956c: d004 beq.n 8009578 800956e: 687b ldr r3, [r7, #4] 8009570: 681b ldr r3, [r3, #0] 8009572: 4a46 ldr r2, [pc, #280] @ (800968c ) 8009574: 4293 cmp r3, r2 8009576: d101 bne.n 800957c 8009578: 2301 movs r3, #1 800957a: e000 b.n 800957e 800957c: 2300 movs r3, #0 800957e: 2b00 cmp r3, #0 8009580: f000 8086 beq.w 8009690 { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 8009584: 687b ldr r3, [r7, #4] 8009586: 2204 movs r2, #4 8009588: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800958c: 687b ldr r3, [r7, #4] 800958e: 681b ldr r3, [r3, #0] 8009590: 4a2f ldr r2, [pc, #188] @ (8009650 ) 8009592: 4293 cmp r3, r2 8009594: d04a beq.n 800962c 8009596: 687b ldr r3, [r7, #4] 8009598: 681b ldr r3, [r3, #0] 800959a: 4a2e ldr r2, [pc, #184] @ (8009654 ) 800959c: 4293 cmp r3, r2 800959e: d045 beq.n 800962c 80095a0: 687b ldr r3, [r7, #4] 80095a2: 681b ldr r3, [r3, #0] 80095a4: 4a2c ldr r2, [pc, #176] @ (8009658 ) 80095a6: 4293 cmp r3, r2 80095a8: d040 beq.n 800962c 80095aa: 687b ldr r3, [r7, #4] 80095ac: 681b ldr r3, [r3, #0] 80095ae: 4a2b ldr r2, [pc, #172] @ (800965c ) 80095b0: 4293 cmp r3, r2 80095b2: d03b beq.n 800962c 80095b4: 687b ldr r3, [r7, #4] 80095b6: 681b ldr r3, [r3, #0] 80095b8: 4a29 ldr r2, [pc, #164] @ (8009660 ) 80095ba: 4293 cmp r3, r2 80095bc: d036 beq.n 800962c 80095be: 687b ldr r3, [r7, #4] 80095c0: 681b ldr r3, [r3, #0] 80095c2: 4a28 ldr r2, [pc, #160] @ (8009664 ) 80095c4: 4293 cmp r3, r2 80095c6: d031 beq.n 800962c 80095c8: 687b ldr r3, [r7, #4] 80095ca: 681b ldr r3, [r3, #0] 80095cc: 4a26 ldr r2, [pc, #152] @ (8009668 ) 80095ce: 4293 cmp r3, r2 80095d0: d02c beq.n 800962c 80095d2: 687b ldr r3, [r7, #4] 80095d4: 681b ldr r3, [r3, #0] 80095d6: 4a25 ldr r2, [pc, #148] @ (800966c ) 80095d8: 4293 cmp r3, r2 80095da: d027 beq.n 800962c 80095dc: 687b ldr r3, [r7, #4] 80095de: 681b ldr r3, [r3, #0] 80095e0: 4a23 ldr r2, [pc, #140] @ (8009670 ) 80095e2: 4293 cmp r3, r2 80095e4: d022 beq.n 800962c 80095e6: 687b ldr r3, [r7, #4] 80095e8: 681b ldr r3, [r3, #0] 80095ea: 4a22 ldr r2, [pc, #136] @ (8009674 ) 80095ec: 4293 cmp r3, r2 80095ee: d01d beq.n 800962c 80095f0: 687b ldr r3, [r7, #4] 80095f2: 681b ldr r3, [r3, #0] 80095f4: 4a20 ldr r2, [pc, #128] @ (8009678 ) 80095f6: 4293 cmp r3, r2 80095f8: d018 beq.n 800962c 80095fa: 687b ldr r3, [r7, #4] 80095fc: 681b ldr r3, [r3, #0] 80095fe: 4a1f ldr r2, [pc, #124] @ (800967c ) 8009600: 4293 cmp r3, r2 8009602: d013 beq.n 800962c 8009604: 687b ldr r3, [r7, #4] 8009606: 681b ldr r3, [r3, #0] 8009608: 4a1d ldr r2, [pc, #116] @ (8009680 ) 800960a: 4293 cmp r3, r2 800960c: d00e beq.n 800962c 800960e: 687b ldr r3, [r7, #4] 8009610: 681b ldr r3, [r3, #0] 8009612: 4a1c ldr r2, [pc, #112] @ (8009684 ) 8009614: 4293 cmp r3, r2 8009616: d009 beq.n 800962c 8009618: 687b ldr r3, [r7, #4] 800961a: 681b ldr r3, [r3, #0] 800961c: 4a1a ldr r2, [pc, #104] @ (8009688 ) 800961e: 4293 cmp r3, r2 8009620: d004 beq.n 800962c 8009622: 687b ldr r3, [r7, #4] 8009624: 681b ldr r3, [r3, #0] 8009626: 4a19 ldr r2, [pc, #100] @ (800968c ) 8009628: 4293 cmp r3, r2 800962a: d108 bne.n 800963e 800962c: 687b ldr r3, [r7, #4] 800962e: 681b ldr r3, [r3, #0] 8009630: 681a ldr r2, [r3, #0] 8009632: 687b ldr r3, [r7, #4] 8009634: 681b ldr r3, [r3, #0] 8009636: f022 0201 bic.w r2, r2, #1 800963a: 601a str r2, [r3, #0] 800963c: e178 b.n 8009930 800963e: 687b ldr r3, [r7, #4] 8009640: 681b ldr r3, [r3, #0] 8009642: 681a ldr r2, [r3, #0] 8009644: 687b ldr r3, [r7, #4] 8009646: 681b ldr r3, [r3, #0] 8009648: f022 0201 bic.w r2, r2, #1 800964c: 601a str r2, [r3, #0] 800964e: e16f b.n 8009930 8009650: 40020010 .word 0x40020010 8009654: 40020028 .word 0x40020028 8009658: 40020040 .word 0x40020040 800965c: 40020058 .word 0x40020058 8009660: 40020070 .word 0x40020070 8009664: 40020088 .word 0x40020088 8009668: 400200a0 .word 0x400200a0 800966c: 400200b8 .word 0x400200b8 8009670: 40020410 .word 0x40020410 8009674: 40020428 .word 0x40020428 8009678: 40020440 .word 0x40020440 800967c: 40020458 .word 0x40020458 8009680: 40020470 .word 0x40020470 8009684: 40020488 .word 0x40020488 8009688: 400204a0 .word 0x400204a0 800968c: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 8009690: 687b ldr r3, [r7, #4] 8009692: 681b ldr r3, [r3, #0] 8009694: 681a ldr r2, [r3, #0] 8009696: 687b ldr r3, [r7, #4] 8009698: 681b ldr r3, [r3, #0] 800969a: f022 020e bic.w r2, r2, #14 800969e: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 80096a0: 687b ldr r3, [r7, #4] 80096a2: 681b ldr r3, [r3, #0] 80096a4: 4a6c ldr r2, [pc, #432] @ (8009858 ) 80096a6: 4293 cmp r3, r2 80096a8: d04a beq.n 8009740 80096aa: 687b ldr r3, [r7, #4] 80096ac: 681b ldr r3, [r3, #0] 80096ae: 4a6b ldr r2, [pc, #428] @ (800985c ) 80096b0: 4293 cmp r3, r2 80096b2: d045 beq.n 8009740 80096b4: 687b ldr r3, [r7, #4] 80096b6: 681b ldr r3, [r3, #0] 80096b8: 4a69 ldr r2, [pc, #420] @ (8009860 ) 80096ba: 4293 cmp r3, r2 80096bc: d040 beq.n 8009740 80096be: 687b ldr r3, [r7, #4] 80096c0: 681b ldr r3, [r3, #0] 80096c2: 4a68 ldr r2, [pc, #416] @ (8009864 ) 80096c4: 4293 cmp r3, r2 80096c6: d03b beq.n 8009740 80096c8: 687b ldr r3, [r7, #4] 80096ca: 681b ldr r3, [r3, #0] 80096cc: 4a66 ldr r2, [pc, #408] @ (8009868 ) 80096ce: 4293 cmp r3, r2 80096d0: d036 beq.n 8009740 80096d2: 687b ldr r3, [r7, #4] 80096d4: 681b ldr r3, [r3, #0] 80096d6: 4a65 ldr r2, [pc, #404] @ (800986c ) 80096d8: 4293 cmp r3, r2 80096da: d031 beq.n 8009740 80096dc: 687b ldr r3, [r7, #4] 80096de: 681b ldr r3, [r3, #0] 80096e0: 4a63 ldr r2, [pc, #396] @ (8009870 ) 80096e2: 4293 cmp r3, r2 80096e4: d02c beq.n 8009740 80096e6: 687b ldr r3, [r7, #4] 80096e8: 681b ldr r3, [r3, #0] 80096ea: 4a62 ldr r2, [pc, #392] @ (8009874 ) 80096ec: 4293 cmp r3, r2 80096ee: d027 beq.n 8009740 80096f0: 687b ldr r3, [r7, #4] 80096f2: 681b ldr r3, [r3, #0] 80096f4: 4a60 ldr r2, [pc, #384] @ (8009878 ) 80096f6: 4293 cmp r3, r2 80096f8: d022 beq.n 8009740 80096fa: 687b ldr r3, [r7, #4] 80096fc: 681b ldr r3, [r3, #0] 80096fe: 4a5f ldr r2, [pc, #380] @ (800987c ) 8009700: 4293 cmp r3, r2 8009702: d01d beq.n 8009740 8009704: 687b ldr r3, [r7, #4] 8009706: 681b ldr r3, [r3, #0] 8009708: 4a5d ldr r2, [pc, #372] @ (8009880 ) 800970a: 4293 cmp r3, r2 800970c: d018 beq.n 8009740 800970e: 687b ldr r3, [r7, #4] 8009710: 681b ldr r3, [r3, #0] 8009712: 4a5c ldr r2, [pc, #368] @ (8009884 ) 8009714: 4293 cmp r3, r2 8009716: d013 beq.n 8009740 8009718: 687b ldr r3, [r7, #4] 800971a: 681b ldr r3, [r3, #0] 800971c: 4a5a ldr r2, [pc, #360] @ (8009888 ) 800971e: 4293 cmp r3, r2 8009720: d00e beq.n 8009740 8009722: 687b ldr r3, [r7, #4] 8009724: 681b ldr r3, [r3, #0] 8009726: 4a59 ldr r2, [pc, #356] @ (800988c ) 8009728: 4293 cmp r3, r2 800972a: d009 beq.n 8009740 800972c: 687b ldr r3, [r7, #4] 800972e: 681b ldr r3, [r3, #0] 8009730: 4a57 ldr r2, [pc, #348] @ (8009890 ) 8009732: 4293 cmp r3, r2 8009734: d004 beq.n 8009740 8009736: 687b ldr r3, [r7, #4] 8009738: 681b ldr r3, [r3, #0] 800973a: 4a56 ldr r2, [pc, #344] @ (8009894 ) 800973c: 4293 cmp r3, r2 800973e: d108 bne.n 8009752 8009740: 687b ldr r3, [r7, #4] 8009742: 681b ldr r3, [r3, #0] 8009744: 681a ldr r2, [r3, #0] 8009746: 687b ldr r3, [r7, #4] 8009748: 681b ldr r3, [r3, #0] 800974a: f022 0201 bic.w r2, r2, #1 800974e: 601a str r2, [r3, #0] 8009750: e007 b.n 8009762 8009752: 687b ldr r3, [r7, #4] 8009754: 681b ldr r3, [r3, #0] 8009756: 681a ldr r2, [r3, #0] 8009758: 687b ldr r3, [r7, #4] 800975a: 681b ldr r3, [r3, #0] 800975c: f022 0201 bic.w r2, r2, #1 8009760: 601a str r2, [r3, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8009762: 687b ldr r3, [r7, #4] 8009764: 681b ldr r3, [r3, #0] 8009766: 4a3c ldr r2, [pc, #240] @ (8009858 ) 8009768: 4293 cmp r3, r2 800976a: d072 beq.n 8009852 800976c: 687b ldr r3, [r7, #4] 800976e: 681b ldr r3, [r3, #0] 8009770: 4a3a ldr r2, [pc, #232] @ (800985c ) 8009772: 4293 cmp r3, r2 8009774: d06d beq.n 8009852 8009776: 687b ldr r3, [r7, #4] 8009778: 681b ldr r3, [r3, #0] 800977a: 4a39 ldr r2, [pc, #228] @ (8009860 ) 800977c: 4293 cmp r3, r2 800977e: d068 beq.n 8009852 8009780: 687b ldr r3, [r7, #4] 8009782: 681b ldr r3, [r3, #0] 8009784: 4a37 ldr r2, [pc, #220] @ (8009864 ) 8009786: 4293 cmp r3, r2 8009788: d063 beq.n 8009852 800978a: 687b ldr r3, [r7, #4] 800978c: 681b ldr r3, [r3, #0] 800978e: 4a36 ldr r2, [pc, #216] @ (8009868 ) 8009790: 4293 cmp r3, r2 8009792: d05e beq.n 8009852 8009794: 687b ldr r3, [r7, #4] 8009796: 681b ldr r3, [r3, #0] 8009798: 4a34 ldr r2, [pc, #208] @ (800986c ) 800979a: 4293 cmp r3, r2 800979c: d059 beq.n 8009852 800979e: 687b ldr r3, [r7, #4] 80097a0: 681b ldr r3, [r3, #0] 80097a2: 4a33 ldr r2, [pc, #204] @ (8009870 ) 80097a4: 4293 cmp r3, r2 80097a6: d054 beq.n 8009852 80097a8: 687b ldr r3, [r7, #4] 80097aa: 681b ldr r3, [r3, #0] 80097ac: 4a31 ldr r2, [pc, #196] @ (8009874 ) 80097ae: 4293 cmp r3, r2 80097b0: d04f beq.n 8009852 80097b2: 687b ldr r3, [r7, #4] 80097b4: 681b ldr r3, [r3, #0] 80097b6: 4a30 ldr r2, [pc, #192] @ (8009878 ) 80097b8: 4293 cmp r3, r2 80097ba: d04a beq.n 8009852 80097bc: 687b ldr r3, [r7, #4] 80097be: 681b ldr r3, [r3, #0] 80097c0: 4a2e ldr r2, [pc, #184] @ (800987c ) 80097c2: 4293 cmp r3, r2 80097c4: d045 beq.n 8009852 80097c6: 687b ldr r3, [r7, #4] 80097c8: 681b ldr r3, [r3, #0] 80097ca: 4a2d ldr r2, [pc, #180] @ (8009880 ) 80097cc: 4293 cmp r3, r2 80097ce: d040 beq.n 8009852 80097d0: 687b ldr r3, [r7, #4] 80097d2: 681b ldr r3, [r3, #0] 80097d4: 4a2b ldr r2, [pc, #172] @ (8009884 ) 80097d6: 4293 cmp r3, r2 80097d8: d03b beq.n 8009852 80097da: 687b ldr r3, [r7, #4] 80097dc: 681b ldr r3, [r3, #0] 80097de: 4a2a ldr r2, [pc, #168] @ (8009888 ) 80097e0: 4293 cmp r3, r2 80097e2: d036 beq.n 8009852 80097e4: 687b ldr r3, [r7, #4] 80097e6: 681b ldr r3, [r3, #0] 80097e8: 4a28 ldr r2, [pc, #160] @ (800988c ) 80097ea: 4293 cmp r3, r2 80097ec: d031 beq.n 8009852 80097ee: 687b ldr r3, [r7, #4] 80097f0: 681b ldr r3, [r3, #0] 80097f2: 4a27 ldr r2, [pc, #156] @ (8009890 ) 80097f4: 4293 cmp r3, r2 80097f6: d02c beq.n 8009852 80097f8: 687b ldr r3, [r7, #4] 80097fa: 681b ldr r3, [r3, #0] 80097fc: 4a25 ldr r2, [pc, #148] @ (8009894 ) 80097fe: 4293 cmp r3, r2 8009800: d027 beq.n 8009852 8009802: 687b ldr r3, [r7, #4] 8009804: 681b ldr r3, [r3, #0] 8009806: 4a24 ldr r2, [pc, #144] @ (8009898 ) 8009808: 4293 cmp r3, r2 800980a: d022 beq.n 8009852 800980c: 687b ldr r3, [r7, #4] 800980e: 681b ldr r3, [r3, #0] 8009810: 4a22 ldr r2, [pc, #136] @ (800989c ) 8009812: 4293 cmp r3, r2 8009814: d01d beq.n 8009852 8009816: 687b ldr r3, [r7, #4] 8009818: 681b ldr r3, [r3, #0] 800981a: 4a21 ldr r2, [pc, #132] @ (80098a0 ) 800981c: 4293 cmp r3, r2 800981e: d018 beq.n 8009852 8009820: 687b ldr r3, [r7, #4] 8009822: 681b ldr r3, [r3, #0] 8009824: 4a1f ldr r2, [pc, #124] @ (80098a4 ) 8009826: 4293 cmp r3, r2 8009828: d013 beq.n 8009852 800982a: 687b ldr r3, [r7, #4] 800982c: 681b ldr r3, [r3, #0] 800982e: 4a1e ldr r2, [pc, #120] @ (80098a8 ) 8009830: 4293 cmp r3, r2 8009832: d00e beq.n 8009852 8009834: 687b ldr r3, [r7, #4] 8009836: 681b ldr r3, [r3, #0] 8009838: 4a1c ldr r2, [pc, #112] @ (80098ac ) 800983a: 4293 cmp r3, r2 800983c: d009 beq.n 8009852 800983e: 687b ldr r3, [r7, #4] 8009840: 681b ldr r3, [r3, #0] 8009842: 4a1b ldr r2, [pc, #108] @ (80098b0 ) 8009844: 4293 cmp r3, r2 8009846: d004 beq.n 8009852 8009848: 687b ldr r3, [r7, #4] 800984a: 681b ldr r3, [r3, #0] 800984c: 4a19 ldr r2, [pc, #100] @ (80098b4 ) 800984e: 4293 cmp r3, r2 8009850: d132 bne.n 80098b8 8009852: 2301 movs r3, #1 8009854: e031 b.n 80098ba 8009856: bf00 nop 8009858: 40020010 .word 0x40020010 800985c: 40020028 .word 0x40020028 8009860: 40020040 .word 0x40020040 8009864: 40020058 .word 0x40020058 8009868: 40020070 .word 0x40020070 800986c: 40020088 .word 0x40020088 8009870: 400200a0 .word 0x400200a0 8009874: 400200b8 .word 0x400200b8 8009878: 40020410 .word 0x40020410 800987c: 40020428 .word 0x40020428 8009880: 40020440 .word 0x40020440 8009884: 40020458 .word 0x40020458 8009888: 40020470 .word 0x40020470 800988c: 40020488 .word 0x40020488 8009890: 400204a0 .word 0x400204a0 8009894: 400204b8 .word 0x400204b8 8009898: 58025408 .word 0x58025408 800989c: 5802541c .word 0x5802541c 80098a0: 58025430 .word 0x58025430 80098a4: 58025444 .word 0x58025444 80098a8: 58025458 .word 0x58025458 80098ac: 5802546c .word 0x5802546c 80098b0: 58025480 .word 0x58025480 80098b4: 58025494 .word 0x58025494 80098b8: 2300 movs r3, #0 80098ba: 2b00 cmp r3, #0 80098bc: d028 beq.n 8009910 { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 80098be: 687b ldr r3, [r7, #4] 80098c0: 6e1b ldr r3, [r3, #96] @ 0x60 80098c2: 681a ldr r2, [r3, #0] 80098c4: 687b ldr r3, [r7, #4] 80098c6: 6e1b ldr r3, [r3, #96] @ 0x60 80098c8: f422 7280 bic.w r2, r2, #256 @ 0x100 80098cc: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 80098ce: 687b ldr r3, [r7, #4] 80098d0: 6d9b ldr r3, [r3, #88] @ 0x58 80098d2: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 80098d4: 687b ldr r3, [r7, #4] 80098d6: 6ddb ldr r3, [r3, #92] @ 0x5c 80098d8: f003 031f and.w r3, r3, #31 80098dc: 2201 movs r2, #1 80098de: 409a lsls r2, r3 80098e0: 68fb ldr r3, [r7, #12] 80098e2: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 80098e4: 687b ldr r3, [r7, #4] 80098e6: 6e5b ldr r3, [r3, #100] @ 0x64 80098e8: 687a ldr r2, [r7, #4] 80098ea: 6e92 ldr r2, [r2, #104] @ 0x68 80098ec: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 80098ee: 687b ldr r3, [r7, #4] 80098f0: 6edb ldr r3, [r3, #108] @ 0x6c 80098f2: 2b00 cmp r3, #0 80098f4: d00c beq.n 8009910 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 80098f6: 687b ldr r3, [r7, #4] 80098f8: 6edb ldr r3, [r3, #108] @ 0x6c 80098fa: 681a ldr r2, [r3, #0] 80098fc: 687b ldr r3, [r7, #4] 80098fe: 6edb ldr r3, [r3, #108] @ 0x6c 8009900: f422 7280 bic.w r2, r2, #256 @ 0x100 8009904: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8009906: 687b ldr r3, [r7, #4] 8009908: 6f1b ldr r3, [r3, #112] @ 0x70 800990a: 687a ldr r2, [r7, #4] 800990c: 6f52 ldr r2, [r2, #116] @ 0x74 800990e: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8009910: 687b ldr r3, [r7, #4] 8009912: 2201 movs r2, #1 8009914: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009918: 687b ldr r3, [r7, #4] 800991a: 2200 movs r2, #0 800991c: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8009920: 687b ldr r3, [r7, #4] 8009922: 6d1b ldr r3, [r3, #80] @ 0x50 8009924: 2b00 cmp r3, #0 8009926: d003 beq.n 8009930 { hdma->XferAbortCallback(hdma); 8009928: 687b ldr r3, [r7, #4] 800992a: 6d1b ldr r3, [r3, #80] @ 0x50 800992c: 6878 ldr r0, [r7, #4] 800992e: 4798 blx r3 } } } return HAL_OK; 8009930: 2300 movs r3, #0 } 8009932: 4618 mov r0, r3 8009934: 3710 adds r7, #16 8009936: 46bd mov sp, r7 8009938: bd80 pop {r7, pc} 800993a: bf00 nop 0800993c : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 800993c: b580 push {r7, lr} 800993e: b08a sub sp, #40 @ 0x28 8009940: af00 add r7, sp, #0 8009942: 6078 str r0, [r7, #4] uint32_t tmpisr_dma, tmpisr_bdma; uint32_t ccr_reg; __IO uint32_t count = 0U; 8009944: 2300 movs r3, #0 8009946: 60fb str r3, [r7, #12] uint32_t timeout = SystemCoreClock / 9600U; 8009948: 4b67 ldr r3, [pc, #412] @ (8009ae8 ) 800994a: 681b ldr r3, [r3, #0] 800994c: 4a67 ldr r2, [pc, #412] @ (8009aec ) 800994e: fba2 2303 umull r2, r3, r2, r3 8009952: 0a9b lsrs r3, r3, #10 8009954: 627b str r3, [r7, #36] @ 0x24 /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8009956: 687b ldr r3, [r7, #4] 8009958: 6d9b ldr r3, [r3, #88] @ 0x58 800995a: 623b str r3, [r7, #32] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 800995c: 687b ldr r3, [r7, #4] 800995e: 6d9b ldr r3, [r3, #88] @ 0x58 8009960: 61fb str r3, [r7, #28] tmpisr_dma = regs_dma->ISR; 8009962: 6a3b ldr r3, [r7, #32] 8009964: 681b ldr r3, [r3, #0] 8009966: 61bb str r3, [r7, #24] tmpisr_bdma = regs_bdma->ISR; 8009968: 69fb ldr r3, [r7, #28] 800996a: 681b ldr r3, [r3, #0] 800996c: 617b str r3, [r7, #20] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800996e: 687b ldr r3, [r7, #4] 8009970: 681b ldr r3, [r3, #0] 8009972: 4a5f ldr r2, [pc, #380] @ (8009af0 ) 8009974: 4293 cmp r3, r2 8009976: d04a beq.n 8009a0e 8009978: 687b ldr r3, [r7, #4] 800997a: 681b ldr r3, [r3, #0] 800997c: 4a5d ldr r2, [pc, #372] @ (8009af4 ) 800997e: 4293 cmp r3, r2 8009980: d045 beq.n 8009a0e 8009982: 687b ldr r3, [r7, #4] 8009984: 681b ldr r3, [r3, #0] 8009986: 4a5c ldr r2, [pc, #368] @ (8009af8 ) 8009988: 4293 cmp r3, r2 800998a: d040 beq.n 8009a0e 800998c: 687b ldr r3, [r7, #4] 800998e: 681b ldr r3, [r3, #0] 8009990: 4a5a ldr r2, [pc, #360] @ (8009afc ) 8009992: 4293 cmp r3, r2 8009994: d03b beq.n 8009a0e 8009996: 687b ldr r3, [r7, #4] 8009998: 681b ldr r3, [r3, #0] 800999a: 4a59 ldr r2, [pc, #356] @ (8009b00 ) 800999c: 4293 cmp r3, r2 800999e: d036 beq.n 8009a0e 80099a0: 687b ldr r3, [r7, #4] 80099a2: 681b ldr r3, [r3, #0] 80099a4: 4a57 ldr r2, [pc, #348] @ (8009b04 ) 80099a6: 4293 cmp r3, r2 80099a8: d031 beq.n 8009a0e 80099aa: 687b ldr r3, [r7, #4] 80099ac: 681b ldr r3, [r3, #0] 80099ae: 4a56 ldr r2, [pc, #344] @ (8009b08 ) 80099b0: 4293 cmp r3, r2 80099b2: d02c beq.n 8009a0e 80099b4: 687b ldr r3, [r7, #4] 80099b6: 681b ldr r3, [r3, #0] 80099b8: 4a54 ldr r2, [pc, #336] @ (8009b0c ) 80099ba: 4293 cmp r3, r2 80099bc: d027 beq.n 8009a0e 80099be: 687b ldr r3, [r7, #4] 80099c0: 681b ldr r3, [r3, #0] 80099c2: 4a53 ldr r2, [pc, #332] @ (8009b10 ) 80099c4: 4293 cmp r3, r2 80099c6: d022 beq.n 8009a0e 80099c8: 687b ldr r3, [r7, #4] 80099ca: 681b ldr r3, [r3, #0] 80099cc: 4a51 ldr r2, [pc, #324] @ (8009b14 ) 80099ce: 4293 cmp r3, r2 80099d0: d01d beq.n 8009a0e 80099d2: 687b ldr r3, [r7, #4] 80099d4: 681b ldr r3, [r3, #0] 80099d6: 4a50 ldr r2, [pc, #320] @ (8009b18 ) 80099d8: 4293 cmp r3, r2 80099da: d018 beq.n 8009a0e 80099dc: 687b ldr r3, [r7, #4] 80099de: 681b ldr r3, [r3, #0] 80099e0: 4a4e ldr r2, [pc, #312] @ (8009b1c ) 80099e2: 4293 cmp r3, r2 80099e4: d013 beq.n 8009a0e 80099e6: 687b ldr r3, [r7, #4] 80099e8: 681b ldr r3, [r3, #0] 80099ea: 4a4d ldr r2, [pc, #308] @ (8009b20 ) 80099ec: 4293 cmp r3, r2 80099ee: d00e beq.n 8009a0e 80099f0: 687b ldr r3, [r7, #4] 80099f2: 681b ldr r3, [r3, #0] 80099f4: 4a4b ldr r2, [pc, #300] @ (8009b24 ) 80099f6: 4293 cmp r3, r2 80099f8: d009 beq.n 8009a0e 80099fa: 687b ldr r3, [r7, #4] 80099fc: 681b ldr r3, [r3, #0] 80099fe: 4a4a ldr r2, [pc, #296] @ (8009b28 ) 8009a00: 4293 cmp r3, r2 8009a02: d004 beq.n 8009a0e 8009a04: 687b ldr r3, [r7, #4] 8009a06: 681b ldr r3, [r3, #0] 8009a08: 4a48 ldr r2, [pc, #288] @ (8009b2c ) 8009a0a: 4293 cmp r3, r2 8009a0c: d101 bne.n 8009a12 8009a0e: 2301 movs r3, #1 8009a10: e000 b.n 8009a14 8009a12: 2300 movs r3, #0 8009a14: 2b00 cmp r3, #0 8009a16: f000 842b beq.w 800a270 { /* Transfer Error Interrupt management ***************************************/ if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009a1a: 687b ldr r3, [r7, #4] 8009a1c: 6ddb ldr r3, [r3, #92] @ 0x5c 8009a1e: f003 031f and.w r3, r3, #31 8009a22: 2208 movs r2, #8 8009a24: 409a lsls r2, r3 8009a26: 69bb ldr r3, [r7, #24] 8009a28: 4013 ands r3, r2 8009a2a: 2b00 cmp r3, #0 8009a2c: f000 80a2 beq.w 8009b74 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) 8009a30: 687b ldr r3, [r7, #4] 8009a32: 681b ldr r3, [r3, #0] 8009a34: 4a2e ldr r2, [pc, #184] @ (8009af0 ) 8009a36: 4293 cmp r3, r2 8009a38: d04a beq.n 8009ad0 8009a3a: 687b ldr r3, [r7, #4] 8009a3c: 681b ldr r3, [r3, #0] 8009a3e: 4a2d ldr r2, [pc, #180] @ (8009af4 ) 8009a40: 4293 cmp r3, r2 8009a42: d045 beq.n 8009ad0 8009a44: 687b ldr r3, [r7, #4] 8009a46: 681b ldr r3, [r3, #0] 8009a48: 4a2b ldr r2, [pc, #172] @ (8009af8 ) 8009a4a: 4293 cmp r3, r2 8009a4c: d040 beq.n 8009ad0 8009a4e: 687b ldr r3, [r7, #4] 8009a50: 681b ldr r3, [r3, #0] 8009a52: 4a2a ldr r2, [pc, #168] @ (8009afc ) 8009a54: 4293 cmp r3, r2 8009a56: d03b beq.n 8009ad0 8009a58: 687b ldr r3, [r7, #4] 8009a5a: 681b ldr r3, [r3, #0] 8009a5c: 4a28 ldr r2, [pc, #160] @ (8009b00 ) 8009a5e: 4293 cmp r3, r2 8009a60: d036 beq.n 8009ad0 8009a62: 687b ldr r3, [r7, #4] 8009a64: 681b ldr r3, [r3, #0] 8009a66: 4a27 ldr r2, [pc, #156] @ (8009b04 ) 8009a68: 4293 cmp r3, r2 8009a6a: d031 beq.n 8009ad0 8009a6c: 687b ldr r3, [r7, #4] 8009a6e: 681b ldr r3, [r3, #0] 8009a70: 4a25 ldr r2, [pc, #148] @ (8009b08 ) 8009a72: 4293 cmp r3, r2 8009a74: d02c beq.n 8009ad0 8009a76: 687b ldr r3, [r7, #4] 8009a78: 681b ldr r3, [r3, #0] 8009a7a: 4a24 ldr r2, [pc, #144] @ (8009b0c ) 8009a7c: 4293 cmp r3, r2 8009a7e: d027 beq.n 8009ad0 8009a80: 687b ldr r3, [r7, #4] 8009a82: 681b ldr r3, [r3, #0] 8009a84: 4a22 ldr r2, [pc, #136] @ (8009b10 ) 8009a86: 4293 cmp r3, r2 8009a88: d022 beq.n 8009ad0 8009a8a: 687b ldr r3, [r7, #4] 8009a8c: 681b ldr r3, [r3, #0] 8009a8e: 4a21 ldr r2, [pc, #132] @ (8009b14 ) 8009a90: 4293 cmp r3, r2 8009a92: d01d beq.n 8009ad0 8009a94: 687b ldr r3, [r7, #4] 8009a96: 681b ldr r3, [r3, #0] 8009a98: 4a1f ldr r2, [pc, #124] @ (8009b18 ) 8009a9a: 4293 cmp r3, r2 8009a9c: d018 beq.n 8009ad0 8009a9e: 687b ldr r3, [r7, #4] 8009aa0: 681b ldr r3, [r3, #0] 8009aa2: 4a1e ldr r2, [pc, #120] @ (8009b1c ) 8009aa4: 4293 cmp r3, r2 8009aa6: d013 beq.n 8009ad0 8009aa8: 687b ldr r3, [r7, #4] 8009aaa: 681b ldr r3, [r3, #0] 8009aac: 4a1c ldr r2, [pc, #112] @ (8009b20 ) 8009aae: 4293 cmp r3, r2 8009ab0: d00e beq.n 8009ad0 8009ab2: 687b ldr r3, [r7, #4] 8009ab4: 681b ldr r3, [r3, #0] 8009ab6: 4a1b ldr r2, [pc, #108] @ (8009b24 ) 8009ab8: 4293 cmp r3, r2 8009aba: d009 beq.n 8009ad0 8009abc: 687b ldr r3, [r7, #4] 8009abe: 681b ldr r3, [r3, #0] 8009ac0: 4a19 ldr r2, [pc, #100] @ (8009b28 ) 8009ac2: 4293 cmp r3, r2 8009ac4: d004 beq.n 8009ad0 8009ac6: 687b ldr r3, [r7, #4] 8009ac8: 681b ldr r3, [r3, #0] 8009aca: 4a18 ldr r2, [pc, #96] @ (8009b2c ) 8009acc: 4293 cmp r3, r2 8009ace: d12f bne.n 8009b30 8009ad0: 687b ldr r3, [r7, #4] 8009ad2: 681b ldr r3, [r3, #0] 8009ad4: 681b ldr r3, [r3, #0] 8009ad6: f003 0304 and.w r3, r3, #4 8009ada: 2b00 cmp r3, #0 8009adc: bf14 ite ne 8009ade: 2301 movne r3, #1 8009ae0: 2300 moveq r3, #0 8009ae2: b2db uxtb r3, r3 8009ae4: e02e b.n 8009b44 8009ae6: bf00 nop 8009ae8: 24000034 .word 0x24000034 8009aec: 1b4e81b5 .word 0x1b4e81b5 8009af0: 40020010 .word 0x40020010 8009af4: 40020028 .word 0x40020028 8009af8: 40020040 .word 0x40020040 8009afc: 40020058 .word 0x40020058 8009b00: 40020070 .word 0x40020070 8009b04: 40020088 .word 0x40020088 8009b08: 400200a0 .word 0x400200a0 8009b0c: 400200b8 .word 0x400200b8 8009b10: 40020410 .word 0x40020410 8009b14: 40020428 .word 0x40020428 8009b18: 40020440 .word 0x40020440 8009b1c: 40020458 .word 0x40020458 8009b20: 40020470 .word 0x40020470 8009b24: 40020488 .word 0x40020488 8009b28: 400204a0 .word 0x400204a0 8009b2c: 400204b8 .word 0x400204b8 8009b30: 687b ldr r3, [r7, #4] 8009b32: 681b ldr r3, [r3, #0] 8009b34: 681b ldr r3, [r3, #0] 8009b36: f003 0308 and.w r3, r3, #8 8009b3a: 2b00 cmp r3, #0 8009b3c: bf14 ite ne 8009b3e: 2301 movne r3, #1 8009b40: 2300 moveq r3, #0 8009b42: b2db uxtb r3, r3 8009b44: 2b00 cmp r3, #0 8009b46: d015 beq.n 8009b74 { /* Disable the transfer error interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); 8009b48: 687b ldr r3, [r7, #4] 8009b4a: 681b ldr r3, [r3, #0] 8009b4c: 681a ldr r2, [r3, #0] 8009b4e: 687b ldr r3, [r7, #4] 8009b50: 681b ldr r3, [r3, #0] 8009b52: f022 0204 bic.w r2, r2, #4 8009b56: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009b58: 687b ldr r3, [r7, #4] 8009b5a: 6ddb ldr r3, [r3, #92] @ 0x5c 8009b5c: f003 031f and.w r3, r3, #31 8009b60: 2208 movs r2, #8 8009b62: 409a lsls r2, r3 8009b64: 6a3b ldr r3, [r7, #32] 8009b66: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 8009b68: 687b ldr r3, [r7, #4] 8009b6a: 6d5b ldr r3, [r3, #84] @ 0x54 8009b6c: f043 0201 orr.w r2, r3, #1 8009b70: 687b ldr r3, [r7, #4] 8009b72: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009b74: 687b ldr r3, [r7, #4] 8009b76: 6ddb ldr r3, [r3, #92] @ 0x5c 8009b78: f003 031f and.w r3, r3, #31 8009b7c: 69ba ldr r2, [r7, #24] 8009b7e: fa22 f303 lsr.w r3, r2, r3 8009b82: f003 0301 and.w r3, r3, #1 8009b86: 2b00 cmp r3, #0 8009b88: d06e beq.n 8009c68 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) 8009b8a: 687b ldr r3, [r7, #4] 8009b8c: 681b ldr r3, [r3, #0] 8009b8e: 4a69 ldr r2, [pc, #420] @ (8009d34 ) 8009b90: 4293 cmp r3, r2 8009b92: d04a beq.n 8009c2a 8009b94: 687b ldr r3, [r7, #4] 8009b96: 681b ldr r3, [r3, #0] 8009b98: 4a67 ldr r2, [pc, #412] @ (8009d38 ) 8009b9a: 4293 cmp r3, r2 8009b9c: d045 beq.n 8009c2a 8009b9e: 687b ldr r3, [r7, #4] 8009ba0: 681b ldr r3, [r3, #0] 8009ba2: 4a66 ldr r2, [pc, #408] @ (8009d3c ) 8009ba4: 4293 cmp r3, r2 8009ba6: d040 beq.n 8009c2a 8009ba8: 687b ldr r3, [r7, #4] 8009baa: 681b ldr r3, [r3, #0] 8009bac: 4a64 ldr r2, [pc, #400] @ (8009d40 ) 8009bae: 4293 cmp r3, r2 8009bb0: d03b beq.n 8009c2a 8009bb2: 687b ldr r3, [r7, #4] 8009bb4: 681b ldr r3, [r3, #0] 8009bb6: 4a63 ldr r2, [pc, #396] @ (8009d44 ) 8009bb8: 4293 cmp r3, r2 8009bba: d036 beq.n 8009c2a 8009bbc: 687b ldr r3, [r7, #4] 8009bbe: 681b ldr r3, [r3, #0] 8009bc0: 4a61 ldr r2, [pc, #388] @ (8009d48 ) 8009bc2: 4293 cmp r3, r2 8009bc4: d031 beq.n 8009c2a 8009bc6: 687b ldr r3, [r7, #4] 8009bc8: 681b ldr r3, [r3, #0] 8009bca: 4a60 ldr r2, [pc, #384] @ (8009d4c ) 8009bcc: 4293 cmp r3, r2 8009bce: d02c beq.n 8009c2a 8009bd0: 687b ldr r3, [r7, #4] 8009bd2: 681b ldr r3, [r3, #0] 8009bd4: 4a5e ldr r2, [pc, #376] @ (8009d50 ) 8009bd6: 4293 cmp r3, r2 8009bd8: d027 beq.n 8009c2a 8009bda: 687b ldr r3, [r7, #4] 8009bdc: 681b ldr r3, [r3, #0] 8009bde: 4a5d ldr r2, [pc, #372] @ (8009d54 ) 8009be0: 4293 cmp r3, r2 8009be2: d022 beq.n 8009c2a 8009be4: 687b ldr r3, [r7, #4] 8009be6: 681b ldr r3, [r3, #0] 8009be8: 4a5b ldr r2, [pc, #364] @ (8009d58 ) 8009bea: 4293 cmp r3, r2 8009bec: d01d beq.n 8009c2a 8009bee: 687b ldr r3, [r7, #4] 8009bf0: 681b ldr r3, [r3, #0] 8009bf2: 4a5a ldr r2, [pc, #360] @ (8009d5c ) 8009bf4: 4293 cmp r3, r2 8009bf6: d018 beq.n 8009c2a 8009bf8: 687b ldr r3, [r7, #4] 8009bfa: 681b ldr r3, [r3, #0] 8009bfc: 4a58 ldr r2, [pc, #352] @ (8009d60 ) 8009bfe: 4293 cmp r3, r2 8009c00: d013 beq.n 8009c2a 8009c02: 687b ldr r3, [r7, #4] 8009c04: 681b ldr r3, [r3, #0] 8009c06: 4a57 ldr r2, [pc, #348] @ (8009d64 ) 8009c08: 4293 cmp r3, r2 8009c0a: d00e beq.n 8009c2a 8009c0c: 687b ldr r3, [r7, #4] 8009c0e: 681b ldr r3, [r3, #0] 8009c10: 4a55 ldr r2, [pc, #340] @ (8009d68 ) 8009c12: 4293 cmp r3, r2 8009c14: d009 beq.n 8009c2a 8009c16: 687b ldr r3, [r7, #4] 8009c18: 681b ldr r3, [r3, #0] 8009c1a: 4a54 ldr r2, [pc, #336] @ (8009d6c ) 8009c1c: 4293 cmp r3, r2 8009c1e: d004 beq.n 8009c2a 8009c20: 687b ldr r3, [r7, #4] 8009c22: 681b ldr r3, [r3, #0] 8009c24: 4a52 ldr r2, [pc, #328] @ (8009d70 ) 8009c26: 4293 cmp r3, r2 8009c28: d10a bne.n 8009c40 8009c2a: 687b ldr r3, [r7, #4] 8009c2c: 681b ldr r3, [r3, #0] 8009c2e: 695b ldr r3, [r3, #20] 8009c30: f003 0380 and.w r3, r3, #128 @ 0x80 8009c34: 2b00 cmp r3, #0 8009c36: bf14 ite ne 8009c38: 2301 movne r3, #1 8009c3a: 2300 moveq r3, #0 8009c3c: b2db uxtb r3, r3 8009c3e: e003 b.n 8009c48 8009c40: 687b ldr r3, [r7, #4] 8009c42: 681b ldr r3, [r3, #0] 8009c44: 681b ldr r3, [r3, #0] 8009c46: 2300 movs r3, #0 8009c48: 2b00 cmp r3, #0 8009c4a: d00d beq.n 8009c68 { /* Clear the FIFO error flag */ regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009c4c: 687b ldr r3, [r7, #4] 8009c4e: 6ddb ldr r3, [r3, #92] @ 0x5c 8009c50: f003 031f and.w r3, r3, #31 8009c54: 2201 movs r2, #1 8009c56: 409a lsls r2, r3 8009c58: 6a3b ldr r3, [r7, #32] 8009c5a: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 8009c5c: 687b ldr r3, [r7, #4] 8009c5e: 6d5b ldr r3, [r3, #84] @ 0x54 8009c60: f043 0202 orr.w r2, r3, #2 8009c64: 687b ldr r3, [r7, #4] 8009c66: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009c68: 687b ldr r3, [r7, #4] 8009c6a: 6ddb ldr r3, [r3, #92] @ 0x5c 8009c6c: f003 031f and.w r3, r3, #31 8009c70: 2204 movs r2, #4 8009c72: 409a lsls r2, r3 8009c74: 69bb ldr r3, [r7, #24] 8009c76: 4013 ands r3, r2 8009c78: 2b00 cmp r3, #0 8009c7a: f000 808f beq.w 8009d9c { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) 8009c7e: 687b ldr r3, [r7, #4] 8009c80: 681b ldr r3, [r3, #0] 8009c82: 4a2c ldr r2, [pc, #176] @ (8009d34 ) 8009c84: 4293 cmp r3, r2 8009c86: d04a beq.n 8009d1e 8009c88: 687b ldr r3, [r7, #4] 8009c8a: 681b ldr r3, [r3, #0] 8009c8c: 4a2a ldr r2, [pc, #168] @ (8009d38 ) 8009c8e: 4293 cmp r3, r2 8009c90: d045 beq.n 8009d1e 8009c92: 687b ldr r3, [r7, #4] 8009c94: 681b ldr r3, [r3, #0] 8009c96: 4a29 ldr r2, [pc, #164] @ (8009d3c ) 8009c98: 4293 cmp r3, r2 8009c9a: d040 beq.n 8009d1e 8009c9c: 687b ldr r3, [r7, #4] 8009c9e: 681b ldr r3, [r3, #0] 8009ca0: 4a27 ldr r2, [pc, #156] @ (8009d40 ) 8009ca2: 4293 cmp r3, r2 8009ca4: d03b beq.n 8009d1e 8009ca6: 687b ldr r3, [r7, #4] 8009ca8: 681b ldr r3, [r3, #0] 8009caa: 4a26 ldr r2, [pc, #152] @ (8009d44 ) 8009cac: 4293 cmp r3, r2 8009cae: d036 beq.n 8009d1e 8009cb0: 687b ldr r3, [r7, #4] 8009cb2: 681b ldr r3, [r3, #0] 8009cb4: 4a24 ldr r2, [pc, #144] @ (8009d48 ) 8009cb6: 4293 cmp r3, r2 8009cb8: d031 beq.n 8009d1e 8009cba: 687b ldr r3, [r7, #4] 8009cbc: 681b ldr r3, [r3, #0] 8009cbe: 4a23 ldr r2, [pc, #140] @ (8009d4c ) 8009cc0: 4293 cmp r3, r2 8009cc2: d02c beq.n 8009d1e 8009cc4: 687b ldr r3, [r7, #4] 8009cc6: 681b ldr r3, [r3, #0] 8009cc8: 4a21 ldr r2, [pc, #132] @ (8009d50 ) 8009cca: 4293 cmp r3, r2 8009ccc: d027 beq.n 8009d1e 8009cce: 687b ldr r3, [r7, #4] 8009cd0: 681b ldr r3, [r3, #0] 8009cd2: 4a20 ldr r2, [pc, #128] @ (8009d54 ) 8009cd4: 4293 cmp r3, r2 8009cd6: d022 beq.n 8009d1e 8009cd8: 687b ldr r3, [r7, #4] 8009cda: 681b ldr r3, [r3, #0] 8009cdc: 4a1e ldr r2, [pc, #120] @ (8009d58 ) 8009cde: 4293 cmp r3, r2 8009ce0: d01d beq.n 8009d1e 8009ce2: 687b ldr r3, [r7, #4] 8009ce4: 681b ldr r3, [r3, #0] 8009ce6: 4a1d ldr r2, [pc, #116] @ (8009d5c ) 8009ce8: 4293 cmp r3, r2 8009cea: d018 beq.n 8009d1e 8009cec: 687b ldr r3, [r7, #4] 8009cee: 681b ldr r3, [r3, #0] 8009cf0: 4a1b ldr r2, [pc, #108] @ (8009d60 ) 8009cf2: 4293 cmp r3, r2 8009cf4: d013 beq.n 8009d1e 8009cf6: 687b ldr r3, [r7, #4] 8009cf8: 681b ldr r3, [r3, #0] 8009cfa: 4a1a ldr r2, [pc, #104] @ (8009d64 ) 8009cfc: 4293 cmp r3, r2 8009cfe: d00e beq.n 8009d1e 8009d00: 687b ldr r3, [r7, #4] 8009d02: 681b ldr r3, [r3, #0] 8009d04: 4a18 ldr r2, [pc, #96] @ (8009d68 ) 8009d06: 4293 cmp r3, r2 8009d08: d009 beq.n 8009d1e 8009d0a: 687b ldr r3, [r7, #4] 8009d0c: 681b ldr r3, [r3, #0] 8009d0e: 4a17 ldr r2, [pc, #92] @ (8009d6c ) 8009d10: 4293 cmp r3, r2 8009d12: d004 beq.n 8009d1e 8009d14: 687b ldr r3, [r7, #4] 8009d16: 681b ldr r3, [r3, #0] 8009d18: 4a15 ldr r2, [pc, #84] @ (8009d70 ) 8009d1a: 4293 cmp r3, r2 8009d1c: d12a bne.n 8009d74 8009d1e: 687b ldr r3, [r7, #4] 8009d20: 681b ldr r3, [r3, #0] 8009d22: 681b ldr r3, [r3, #0] 8009d24: f003 0302 and.w r3, r3, #2 8009d28: 2b00 cmp r3, #0 8009d2a: bf14 ite ne 8009d2c: 2301 movne r3, #1 8009d2e: 2300 moveq r3, #0 8009d30: b2db uxtb r3, r3 8009d32: e023 b.n 8009d7c 8009d34: 40020010 .word 0x40020010 8009d38: 40020028 .word 0x40020028 8009d3c: 40020040 .word 0x40020040 8009d40: 40020058 .word 0x40020058 8009d44: 40020070 .word 0x40020070 8009d48: 40020088 .word 0x40020088 8009d4c: 400200a0 .word 0x400200a0 8009d50: 400200b8 .word 0x400200b8 8009d54: 40020410 .word 0x40020410 8009d58: 40020428 .word 0x40020428 8009d5c: 40020440 .word 0x40020440 8009d60: 40020458 .word 0x40020458 8009d64: 40020470 .word 0x40020470 8009d68: 40020488 .word 0x40020488 8009d6c: 400204a0 .word 0x400204a0 8009d70: 400204b8 .word 0x400204b8 8009d74: 687b ldr r3, [r7, #4] 8009d76: 681b ldr r3, [r3, #0] 8009d78: 681b ldr r3, [r3, #0] 8009d7a: 2300 movs r3, #0 8009d7c: 2b00 cmp r3, #0 8009d7e: d00d beq.n 8009d9c { /* Clear the direct mode error flag */ regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009d80: 687b ldr r3, [r7, #4] 8009d82: 6ddb ldr r3, [r3, #92] @ 0x5c 8009d84: f003 031f and.w r3, r3, #31 8009d88: 2204 movs r2, #4 8009d8a: 409a lsls r2, r3 8009d8c: 6a3b ldr r3, [r7, #32] 8009d8e: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 8009d90: 687b ldr r3, [r7, #4] 8009d92: 6d5b ldr r3, [r3, #84] @ 0x54 8009d94: f043 0204 orr.w r2, r3, #4 8009d98: 687b ldr r3, [r7, #4] 8009d9a: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009d9c: 687b ldr r3, [r7, #4] 8009d9e: 6ddb ldr r3, [r3, #92] @ 0x5c 8009da0: f003 031f and.w r3, r3, #31 8009da4: 2210 movs r2, #16 8009da6: 409a lsls r2, r3 8009da8: 69bb ldr r3, [r7, #24] 8009daa: 4013 ands r3, r2 8009dac: 2b00 cmp r3, #0 8009dae: f000 80a6 beq.w 8009efe { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) 8009db2: 687b ldr r3, [r7, #4] 8009db4: 681b ldr r3, [r3, #0] 8009db6: 4a85 ldr r2, [pc, #532] @ (8009fcc ) 8009db8: 4293 cmp r3, r2 8009dba: d04a beq.n 8009e52 8009dbc: 687b ldr r3, [r7, #4] 8009dbe: 681b ldr r3, [r3, #0] 8009dc0: 4a83 ldr r2, [pc, #524] @ (8009fd0 ) 8009dc2: 4293 cmp r3, r2 8009dc4: d045 beq.n 8009e52 8009dc6: 687b ldr r3, [r7, #4] 8009dc8: 681b ldr r3, [r3, #0] 8009dca: 4a82 ldr r2, [pc, #520] @ (8009fd4 ) 8009dcc: 4293 cmp r3, r2 8009dce: d040 beq.n 8009e52 8009dd0: 687b ldr r3, [r7, #4] 8009dd2: 681b ldr r3, [r3, #0] 8009dd4: 4a80 ldr r2, [pc, #512] @ (8009fd8 ) 8009dd6: 4293 cmp r3, r2 8009dd8: d03b beq.n 8009e52 8009dda: 687b ldr r3, [r7, #4] 8009ddc: 681b ldr r3, [r3, #0] 8009dde: 4a7f ldr r2, [pc, #508] @ (8009fdc ) 8009de0: 4293 cmp r3, r2 8009de2: d036 beq.n 8009e52 8009de4: 687b ldr r3, [r7, #4] 8009de6: 681b ldr r3, [r3, #0] 8009de8: 4a7d ldr r2, [pc, #500] @ (8009fe0 ) 8009dea: 4293 cmp r3, r2 8009dec: d031 beq.n 8009e52 8009dee: 687b ldr r3, [r7, #4] 8009df0: 681b ldr r3, [r3, #0] 8009df2: 4a7c ldr r2, [pc, #496] @ (8009fe4 ) 8009df4: 4293 cmp r3, r2 8009df6: d02c beq.n 8009e52 8009df8: 687b ldr r3, [r7, #4] 8009dfa: 681b ldr r3, [r3, #0] 8009dfc: 4a7a ldr r2, [pc, #488] @ (8009fe8 ) 8009dfe: 4293 cmp r3, r2 8009e00: d027 beq.n 8009e52 8009e02: 687b ldr r3, [r7, #4] 8009e04: 681b ldr r3, [r3, #0] 8009e06: 4a79 ldr r2, [pc, #484] @ (8009fec ) 8009e08: 4293 cmp r3, r2 8009e0a: d022 beq.n 8009e52 8009e0c: 687b ldr r3, [r7, #4] 8009e0e: 681b ldr r3, [r3, #0] 8009e10: 4a77 ldr r2, [pc, #476] @ (8009ff0 ) 8009e12: 4293 cmp r3, r2 8009e14: d01d beq.n 8009e52 8009e16: 687b ldr r3, [r7, #4] 8009e18: 681b ldr r3, [r3, #0] 8009e1a: 4a76 ldr r2, [pc, #472] @ (8009ff4 ) 8009e1c: 4293 cmp r3, r2 8009e1e: d018 beq.n 8009e52 8009e20: 687b ldr r3, [r7, #4] 8009e22: 681b ldr r3, [r3, #0] 8009e24: 4a74 ldr r2, [pc, #464] @ (8009ff8 ) 8009e26: 4293 cmp r3, r2 8009e28: d013 beq.n 8009e52 8009e2a: 687b ldr r3, [r7, #4] 8009e2c: 681b ldr r3, [r3, #0] 8009e2e: 4a73 ldr r2, [pc, #460] @ (8009ffc ) 8009e30: 4293 cmp r3, r2 8009e32: d00e beq.n 8009e52 8009e34: 687b ldr r3, [r7, #4] 8009e36: 681b ldr r3, [r3, #0] 8009e38: 4a71 ldr r2, [pc, #452] @ (800a000 ) 8009e3a: 4293 cmp r3, r2 8009e3c: d009 beq.n 8009e52 8009e3e: 687b ldr r3, [r7, #4] 8009e40: 681b ldr r3, [r3, #0] 8009e42: 4a70 ldr r2, [pc, #448] @ (800a004 ) 8009e44: 4293 cmp r3, r2 8009e46: d004 beq.n 8009e52 8009e48: 687b ldr r3, [r7, #4] 8009e4a: 681b ldr r3, [r3, #0] 8009e4c: 4a6e ldr r2, [pc, #440] @ (800a008 ) 8009e4e: 4293 cmp r3, r2 8009e50: d10a bne.n 8009e68 8009e52: 687b ldr r3, [r7, #4] 8009e54: 681b ldr r3, [r3, #0] 8009e56: 681b ldr r3, [r3, #0] 8009e58: f003 0308 and.w r3, r3, #8 8009e5c: 2b00 cmp r3, #0 8009e5e: bf14 ite ne 8009e60: 2301 movne r3, #1 8009e62: 2300 moveq r3, #0 8009e64: b2db uxtb r3, r3 8009e66: e009 b.n 8009e7c 8009e68: 687b ldr r3, [r7, #4] 8009e6a: 681b ldr r3, [r3, #0] 8009e6c: 681b ldr r3, [r3, #0] 8009e6e: f003 0304 and.w r3, r3, #4 8009e72: 2b00 cmp r3, #0 8009e74: bf14 ite ne 8009e76: 2301 movne r3, #1 8009e78: 2300 moveq r3, #0 8009e7a: b2db uxtb r3, r3 8009e7c: 2b00 cmp r3, #0 8009e7e: d03e beq.n 8009efe { /* Clear the half transfer complete flag */ regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); 8009e80: 687b ldr r3, [r7, #4] 8009e82: 6ddb ldr r3, [r3, #92] @ 0x5c 8009e84: f003 031f and.w r3, r3, #31 8009e88: 2210 movs r2, #16 8009e8a: 409a lsls r2, r3 8009e8c: 6a3b ldr r3, [r7, #32] 8009e8e: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 8009e90: 687b ldr r3, [r7, #4] 8009e92: 681b ldr r3, [r3, #0] 8009e94: 681b ldr r3, [r3, #0] 8009e96: f403 2380 and.w r3, r3, #262144 @ 0x40000 8009e9a: 2b00 cmp r3, #0 8009e9c: d018 beq.n 8009ed0 { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 8009e9e: 687b ldr r3, [r7, #4] 8009ea0: 681b ldr r3, [r3, #0] 8009ea2: 681b ldr r3, [r3, #0] 8009ea4: f403 2300 and.w r3, r3, #524288 @ 0x80000 8009ea8: 2b00 cmp r3, #0 8009eaa: d108 bne.n 8009ebe { if(hdma->XferHalfCpltCallback != NULL) 8009eac: 687b ldr r3, [r7, #4] 8009eae: 6c1b ldr r3, [r3, #64] @ 0x40 8009eb0: 2b00 cmp r3, #0 8009eb2: d024 beq.n 8009efe { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8009eb4: 687b ldr r3, [r7, #4] 8009eb6: 6c1b ldr r3, [r3, #64] @ 0x40 8009eb8: 6878 ldr r0, [r7, #4] 8009eba: 4798 blx r3 8009ebc: e01f b.n 8009efe } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 8009ebe: 687b ldr r3, [r7, #4] 8009ec0: 6c9b ldr r3, [r3, #72] @ 0x48 8009ec2: 2b00 cmp r3, #0 8009ec4: d01b beq.n 8009efe { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 8009ec6: 687b ldr r3, [r7, #4] 8009ec8: 6c9b ldr r3, [r3, #72] @ 0x48 8009eca: 6878 ldr r0, [r7, #4] 8009ecc: 4798 blx r3 8009ece: e016 b.n 8009efe } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 8009ed0: 687b ldr r3, [r7, #4] 8009ed2: 681b ldr r3, [r3, #0] 8009ed4: 681b ldr r3, [r3, #0] 8009ed6: f403 7380 and.w r3, r3, #256 @ 0x100 8009eda: 2b00 cmp r3, #0 8009edc: d107 bne.n 8009eee { /* Disable the half transfer interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 8009ede: 687b ldr r3, [r7, #4] 8009ee0: 681b ldr r3, [r3, #0] 8009ee2: 681a ldr r2, [r3, #0] 8009ee4: 687b ldr r3, [r7, #4] 8009ee6: 681b ldr r3, [r3, #0] 8009ee8: f022 0208 bic.w r2, r2, #8 8009eec: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 8009eee: 687b ldr r3, [r7, #4] 8009ef0: 6c1b ldr r3, [r3, #64] @ 0x40 8009ef2: 2b00 cmp r3, #0 8009ef4: d003 beq.n 8009efe { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8009ef6: 687b ldr r3, [r7, #4] 8009ef8: 6c1b ldr r3, [r3, #64] @ 0x40 8009efa: 6878 ldr r0, [r7, #4] 8009efc: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009efe: 687b ldr r3, [r7, #4] 8009f00: 6ddb ldr r3, [r3, #92] @ 0x5c 8009f02: f003 031f and.w r3, r3, #31 8009f06: 2220 movs r2, #32 8009f08: 409a lsls r2, r3 8009f0a: 69bb ldr r3, [r7, #24] 8009f0c: 4013 ands r3, r2 8009f0e: 2b00 cmp r3, #0 8009f10: f000 8110 beq.w 800a134 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) 8009f14: 687b ldr r3, [r7, #4] 8009f16: 681b ldr r3, [r3, #0] 8009f18: 4a2c ldr r2, [pc, #176] @ (8009fcc ) 8009f1a: 4293 cmp r3, r2 8009f1c: d04a beq.n 8009fb4 8009f1e: 687b ldr r3, [r7, #4] 8009f20: 681b ldr r3, [r3, #0] 8009f22: 4a2b ldr r2, [pc, #172] @ (8009fd0 ) 8009f24: 4293 cmp r3, r2 8009f26: d045 beq.n 8009fb4 8009f28: 687b ldr r3, [r7, #4] 8009f2a: 681b ldr r3, [r3, #0] 8009f2c: 4a29 ldr r2, [pc, #164] @ (8009fd4 ) 8009f2e: 4293 cmp r3, r2 8009f30: d040 beq.n 8009fb4 8009f32: 687b ldr r3, [r7, #4] 8009f34: 681b ldr r3, [r3, #0] 8009f36: 4a28 ldr r2, [pc, #160] @ (8009fd8 ) 8009f38: 4293 cmp r3, r2 8009f3a: d03b beq.n 8009fb4 8009f3c: 687b ldr r3, [r7, #4] 8009f3e: 681b ldr r3, [r3, #0] 8009f40: 4a26 ldr r2, [pc, #152] @ (8009fdc ) 8009f42: 4293 cmp r3, r2 8009f44: d036 beq.n 8009fb4 8009f46: 687b ldr r3, [r7, #4] 8009f48: 681b ldr r3, [r3, #0] 8009f4a: 4a25 ldr r2, [pc, #148] @ (8009fe0 ) 8009f4c: 4293 cmp r3, r2 8009f4e: d031 beq.n 8009fb4 8009f50: 687b ldr r3, [r7, #4] 8009f52: 681b ldr r3, [r3, #0] 8009f54: 4a23 ldr r2, [pc, #140] @ (8009fe4 ) 8009f56: 4293 cmp r3, r2 8009f58: d02c beq.n 8009fb4 8009f5a: 687b ldr r3, [r7, #4] 8009f5c: 681b ldr r3, [r3, #0] 8009f5e: 4a22 ldr r2, [pc, #136] @ (8009fe8 ) 8009f60: 4293 cmp r3, r2 8009f62: d027 beq.n 8009fb4 8009f64: 687b ldr r3, [r7, #4] 8009f66: 681b ldr r3, [r3, #0] 8009f68: 4a20 ldr r2, [pc, #128] @ (8009fec ) 8009f6a: 4293 cmp r3, r2 8009f6c: d022 beq.n 8009fb4 8009f6e: 687b ldr r3, [r7, #4] 8009f70: 681b ldr r3, [r3, #0] 8009f72: 4a1f ldr r2, [pc, #124] @ (8009ff0 ) 8009f74: 4293 cmp r3, r2 8009f76: d01d beq.n 8009fb4 8009f78: 687b ldr r3, [r7, #4] 8009f7a: 681b ldr r3, [r3, #0] 8009f7c: 4a1d ldr r2, [pc, #116] @ (8009ff4 ) 8009f7e: 4293 cmp r3, r2 8009f80: d018 beq.n 8009fb4 8009f82: 687b ldr r3, [r7, #4] 8009f84: 681b ldr r3, [r3, #0] 8009f86: 4a1c ldr r2, [pc, #112] @ (8009ff8 ) 8009f88: 4293 cmp r3, r2 8009f8a: d013 beq.n 8009fb4 8009f8c: 687b ldr r3, [r7, #4] 8009f8e: 681b ldr r3, [r3, #0] 8009f90: 4a1a ldr r2, [pc, #104] @ (8009ffc ) 8009f92: 4293 cmp r3, r2 8009f94: d00e beq.n 8009fb4 8009f96: 687b ldr r3, [r7, #4] 8009f98: 681b ldr r3, [r3, #0] 8009f9a: 4a19 ldr r2, [pc, #100] @ (800a000 ) 8009f9c: 4293 cmp r3, r2 8009f9e: d009 beq.n 8009fb4 8009fa0: 687b ldr r3, [r7, #4] 8009fa2: 681b ldr r3, [r3, #0] 8009fa4: 4a17 ldr r2, [pc, #92] @ (800a004 ) 8009fa6: 4293 cmp r3, r2 8009fa8: d004 beq.n 8009fb4 8009faa: 687b ldr r3, [r7, #4] 8009fac: 681b ldr r3, [r3, #0] 8009fae: 4a16 ldr r2, [pc, #88] @ (800a008 ) 8009fb0: 4293 cmp r3, r2 8009fb2: d12b bne.n 800a00c 8009fb4: 687b ldr r3, [r7, #4] 8009fb6: 681b ldr r3, [r3, #0] 8009fb8: 681b ldr r3, [r3, #0] 8009fba: f003 0310 and.w r3, r3, #16 8009fbe: 2b00 cmp r3, #0 8009fc0: bf14 ite ne 8009fc2: 2301 movne r3, #1 8009fc4: 2300 moveq r3, #0 8009fc6: b2db uxtb r3, r3 8009fc8: e02a b.n 800a020 8009fca: bf00 nop 8009fcc: 40020010 .word 0x40020010 8009fd0: 40020028 .word 0x40020028 8009fd4: 40020040 .word 0x40020040 8009fd8: 40020058 .word 0x40020058 8009fdc: 40020070 .word 0x40020070 8009fe0: 40020088 .word 0x40020088 8009fe4: 400200a0 .word 0x400200a0 8009fe8: 400200b8 .word 0x400200b8 8009fec: 40020410 .word 0x40020410 8009ff0: 40020428 .word 0x40020428 8009ff4: 40020440 .word 0x40020440 8009ff8: 40020458 .word 0x40020458 8009ffc: 40020470 .word 0x40020470 800a000: 40020488 .word 0x40020488 800a004: 400204a0 .word 0x400204a0 800a008: 400204b8 .word 0x400204b8 800a00c: 687b ldr r3, [r7, #4] 800a00e: 681b ldr r3, [r3, #0] 800a010: 681b ldr r3, [r3, #0] 800a012: f003 0302 and.w r3, r3, #2 800a016: 2b00 cmp r3, #0 800a018: bf14 ite ne 800a01a: 2301 movne r3, #1 800a01c: 2300 moveq r3, #0 800a01e: b2db uxtb r3, r3 800a020: 2b00 cmp r3, #0 800a022: f000 8087 beq.w 800a134 { /* Clear the transfer complete flag */ regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); 800a026: 687b ldr r3, [r7, #4] 800a028: 6ddb ldr r3, [r3, #92] @ 0x5c 800a02a: f003 031f and.w r3, r3, #31 800a02e: 2220 movs r2, #32 800a030: 409a lsls r2, r3 800a032: 6a3b ldr r3, [r7, #32] 800a034: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 800a036: 687b ldr r3, [r7, #4] 800a038: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 800a03c: b2db uxtb r3, r3 800a03e: 2b04 cmp r3, #4 800a040: d139 bne.n 800a0b6 { /* Disable all the transfer interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 800a042: 687b ldr r3, [r7, #4] 800a044: 681b ldr r3, [r3, #0] 800a046: 681a ldr r2, [r3, #0] 800a048: 687b ldr r3, [r7, #4] 800a04a: 681b ldr r3, [r3, #0] 800a04c: f022 0216 bic.w r2, r2, #22 800a050: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 800a052: 687b ldr r3, [r7, #4] 800a054: 681b ldr r3, [r3, #0] 800a056: 695a ldr r2, [r3, #20] 800a058: 687b ldr r3, [r7, #4] 800a05a: 681b ldr r3, [r3, #0] 800a05c: f022 0280 bic.w r2, r2, #128 @ 0x80 800a060: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 800a062: 687b ldr r3, [r7, #4] 800a064: 6c1b ldr r3, [r3, #64] @ 0x40 800a066: 2b00 cmp r3, #0 800a068: d103 bne.n 800a072 800a06a: 687b ldr r3, [r7, #4] 800a06c: 6c9b ldr r3, [r3, #72] @ 0x48 800a06e: 2b00 cmp r3, #0 800a070: d007 beq.n 800a082 { ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 800a072: 687b ldr r3, [r7, #4] 800a074: 681b ldr r3, [r3, #0] 800a076: 681a ldr r2, [r3, #0] 800a078: 687b ldr r3, [r7, #4] 800a07a: 681b ldr r3, [r3, #0] 800a07c: f022 0208 bic.w r2, r2, #8 800a080: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800a082: 687b ldr r3, [r7, #4] 800a084: 6ddb ldr r3, [r3, #92] @ 0x5c 800a086: f003 031f and.w r3, r3, #31 800a08a: 223f movs r2, #63 @ 0x3f 800a08c: 409a lsls r2, r3 800a08e: 6a3b ldr r3, [r7, #32] 800a090: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a092: 687b ldr r3, [r7, #4] 800a094: 2201 movs r2, #1 800a096: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a09a: 687b ldr r3, [r7, #4] 800a09c: 2200 movs r2, #0 800a09e: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 800a0a2: 687b ldr r3, [r7, #4] 800a0a4: 6d1b ldr r3, [r3, #80] @ 0x50 800a0a6: 2b00 cmp r3, #0 800a0a8: f000 834a beq.w 800a740 { hdma->XferAbortCallback(hdma); 800a0ac: 687b ldr r3, [r7, #4] 800a0ae: 6d1b ldr r3, [r3, #80] @ 0x50 800a0b0: 6878 ldr r0, [r7, #4] 800a0b2: 4798 blx r3 } return; 800a0b4: e344 b.n 800a740 } if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 800a0b6: 687b ldr r3, [r7, #4] 800a0b8: 681b ldr r3, [r3, #0] 800a0ba: 681b ldr r3, [r3, #0] 800a0bc: f403 2380 and.w r3, r3, #262144 @ 0x40000 800a0c0: 2b00 cmp r3, #0 800a0c2: d018 beq.n 800a0f6 { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 800a0c4: 687b ldr r3, [r7, #4] 800a0c6: 681b ldr r3, [r3, #0] 800a0c8: 681b ldr r3, [r3, #0] 800a0ca: f403 2300 and.w r3, r3, #524288 @ 0x80000 800a0ce: 2b00 cmp r3, #0 800a0d0: d108 bne.n 800a0e4 { if(hdma->XferM1CpltCallback != NULL) 800a0d2: 687b ldr r3, [r7, #4] 800a0d4: 6c5b ldr r3, [r3, #68] @ 0x44 800a0d6: 2b00 cmp r3, #0 800a0d8: d02c beq.n 800a134 { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 800a0da: 687b ldr r3, [r7, #4] 800a0dc: 6c5b ldr r3, [r3, #68] @ 0x44 800a0de: 6878 ldr r0, [r7, #4] 800a0e0: 4798 blx r3 800a0e2: e027 b.n 800a134 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800a0e4: 687b ldr r3, [r7, #4] 800a0e6: 6bdb ldr r3, [r3, #60] @ 0x3c 800a0e8: 2b00 cmp r3, #0 800a0ea: d023 beq.n 800a134 { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 800a0ec: 687b ldr r3, [r7, #4] 800a0ee: 6bdb ldr r3, [r3, #60] @ 0x3c 800a0f0: 6878 ldr r0, [r7, #4] 800a0f2: 4798 blx r3 800a0f4: e01e b.n 800a134 } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 800a0f6: 687b ldr r3, [r7, #4] 800a0f8: 681b ldr r3, [r3, #0] 800a0fa: 681b ldr r3, [r3, #0] 800a0fc: f403 7380 and.w r3, r3, #256 @ 0x100 800a100: 2b00 cmp r3, #0 800a102: d10f bne.n 800a124 { /* Disable the transfer complete interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); 800a104: 687b ldr r3, [r7, #4] 800a106: 681b ldr r3, [r3, #0] 800a108: 681a ldr r2, [r3, #0] 800a10a: 687b ldr r3, [r7, #4] 800a10c: 681b ldr r3, [r3, #0] 800a10e: f022 0210 bic.w r2, r2, #16 800a112: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a114: 687b ldr r3, [r7, #4] 800a116: 2201 movs r2, #1 800a118: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a11c: 687b ldr r3, [r7, #4] 800a11e: 2200 movs r2, #0 800a120: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 800a124: 687b ldr r3, [r7, #4] 800a126: 6bdb ldr r3, [r3, #60] @ 0x3c 800a128: 2b00 cmp r3, #0 800a12a: d003 beq.n 800a134 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 800a12c: 687b ldr r3, [r7, #4] 800a12e: 6bdb ldr r3, [r3, #60] @ 0x3c 800a130: 6878 ldr r0, [r7, #4] 800a132: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 800a134: 687b ldr r3, [r7, #4] 800a136: 6d5b ldr r3, [r3, #84] @ 0x54 800a138: 2b00 cmp r3, #0 800a13a: f000 8306 beq.w 800a74a { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) 800a13e: 687b ldr r3, [r7, #4] 800a140: 6d5b ldr r3, [r3, #84] @ 0x54 800a142: f003 0301 and.w r3, r3, #1 800a146: 2b00 cmp r3, #0 800a148: f000 8088 beq.w 800a25c { hdma->State = HAL_DMA_STATE_ABORT; 800a14c: 687b ldr r3, [r7, #4] 800a14e: 2204 movs r2, #4 800a150: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800a154: 687b ldr r3, [r7, #4] 800a156: 681b ldr r3, [r3, #0] 800a158: 4a7a ldr r2, [pc, #488] @ (800a344 ) 800a15a: 4293 cmp r3, r2 800a15c: d04a beq.n 800a1f4 800a15e: 687b ldr r3, [r7, #4] 800a160: 681b ldr r3, [r3, #0] 800a162: 4a79 ldr r2, [pc, #484] @ (800a348 ) 800a164: 4293 cmp r3, r2 800a166: d045 beq.n 800a1f4 800a168: 687b ldr r3, [r7, #4] 800a16a: 681b ldr r3, [r3, #0] 800a16c: 4a77 ldr r2, [pc, #476] @ (800a34c ) 800a16e: 4293 cmp r3, r2 800a170: d040 beq.n 800a1f4 800a172: 687b ldr r3, [r7, #4] 800a174: 681b ldr r3, [r3, #0] 800a176: 4a76 ldr r2, [pc, #472] @ (800a350 ) 800a178: 4293 cmp r3, r2 800a17a: d03b beq.n 800a1f4 800a17c: 687b ldr r3, [r7, #4] 800a17e: 681b ldr r3, [r3, #0] 800a180: 4a74 ldr r2, [pc, #464] @ (800a354 ) 800a182: 4293 cmp r3, r2 800a184: d036 beq.n 800a1f4 800a186: 687b ldr r3, [r7, #4] 800a188: 681b ldr r3, [r3, #0] 800a18a: 4a73 ldr r2, [pc, #460] @ (800a358 ) 800a18c: 4293 cmp r3, r2 800a18e: d031 beq.n 800a1f4 800a190: 687b ldr r3, [r7, #4] 800a192: 681b ldr r3, [r3, #0] 800a194: 4a71 ldr r2, [pc, #452] @ (800a35c ) 800a196: 4293 cmp r3, r2 800a198: d02c beq.n 800a1f4 800a19a: 687b ldr r3, [r7, #4] 800a19c: 681b ldr r3, [r3, #0] 800a19e: 4a70 ldr r2, [pc, #448] @ (800a360 ) 800a1a0: 4293 cmp r3, r2 800a1a2: d027 beq.n 800a1f4 800a1a4: 687b ldr r3, [r7, #4] 800a1a6: 681b ldr r3, [r3, #0] 800a1a8: 4a6e ldr r2, [pc, #440] @ (800a364 ) 800a1aa: 4293 cmp r3, r2 800a1ac: d022 beq.n 800a1f4 800a1ae: 687b ldr r3, [r7, #4] 800a1b0: 681b ldr r3, [r3, #0] 800a1b2: 4a6d ldr r2, [pc, #436] @ (800a368 ) 800a1b4: 4293 cmp r3, r2 800a1b6: d01d beq.n 800a1f4 800a1b8: 687b ldr r3, [r7, #4] 800a1ba: 681b ldr r3, [r3, #0] 800a1bc: 4a6b ldr r2, [pc, #428] @ (800a36c ) 800a1be: 4293 cmp r3, r2 800a1c0: d018 beq.n 800a1f4 800a1c2: 687b ldr r3, [r7, #4] 800a1c4: 681b ldr r3, [r3, #0] 800a1c6: 4a6a ldr r2, [pc, #424] @ (800a370 ) 800a1c8: 4293 cmp r3, r2 800a1ca: d013 beq.n 800a1f4 800a1cc: 687b ldr r3, [r7, #4] 800a1ce: 681b ldr r3, [r3, #0] 800a1d0: 4a68 ldr r2, [pc, #416] @ (800a374 ) 800a1d2: 4293 cmp r3, r2 800a1d4: d00e beq.n 800a1f4 800a1d6: 687b ldr r3, [r7, #4] 800a1d8: 681b ldr r3, [r3, #0] 800a1da: 4a67 ldr r2, [pc, #412] @ (800a378 ) 800a1dc: 4293 cmp r3, r2 800a1de: d009 beq.n 800a1f4 800a1e0: 687b ldr r3, [r7, #4] 800a1e2: 681b ldr r3, [r3, #0] 800a1e4: 4a65 ldr r2, [pc, #404] @ (800a37c ) 800a1e6: 4293 cmp r3, r2 800a1e8: d004 beq.n 800a1f4 800a1ea: 687b ldr r3, [r7, #4] 800a1ec: 681b ldr r3, [r3, #0] 800a1ee: 4a64 ldr r2, [pc, #400] @ (800a380 ) 800a1f0: 4293 cmp r3, r2 800a1f2: d108 bne.n 800a206 800a1f4: 687b ldr r3, [r7, #4] 800a1f6: 681b ldr r3, [r3, #0] 800a1f8: 681a ldr r2, [r3, #0] 800a1fa: 687b ldr r3, [r7, #4] 800a1fc: 681b ldr r3, [r3, #0] 800a1fe: f022 0201 bic.w r2, r2, #1 800a202: 601a str r2, [r3, #0] 800a204: e007 b.n 800a216 800a206: 687b ldr r3, [r7, #4] 800a208: 681b ldr r3, [r3, #0] 800a20a: 681a ldr r2, [r3, #0] 800a20c: 687b ldr r3, [r7, #4] 800a20e: 681b ldr r3, [r3, #0] 800a210: f022 0201 bic.w r2, r2, #1 800a214: 601a str r2, [r3, #0] do { if (++count > timeout) 800a216: 68fb ldr r3, [r7, #12] 800a218: 3301 adds r3, #1 800a21a: 60fb str r3, [r7, #12] 800a21c: 6a7a ldr r2, [r7, #36] @ 0x24 800a21e: 429a cmp r2, r3 800a220: d307 bcc.n 800a232 { break; } } while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); 800a222: 687b ldr r3, [r7, #4] 800a224: 681b ldr r3, [r3, #0] 800a226: 681b ldr r3, [r3, #0] 800a228: f003 0301 and.w r3, r3, #1 800a22c: 2b00 cmp r3, #0 800a22e: d1f2 bne.n 800a216 800a230: e000 b.n 800a234 break; 800a232: bf00 nop if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 800a234: 687b ldr r3, [r7, #4] 800a236: 681b ldr r3, [r3, #0] 800a238: 681b ldr r3, [r3, #0] 800a23a: f003 0301 and.w r3, r3, #1 800a23e: 2b00 cmp r3, #0 800a240: d004 beq.n 800a24c { /* Change the DMA state to error if DMA disable fails */ hdma->State = HAL_DMA_STATE_ERROR; 800a242: 687b ldr r3, [r7, #4] 800a244: 2203 movs r2, #3 800a246: f883 2035 strb.w r2, [r3, #53] @ 0x35 800a24a: e003 b.n 800a254 } else { /* Change the DMA state to Ready if DMA disable success */ hdma->State = HAL_DMA_STATE_READY; 800a24c: 687b ldr r3, [r7, #4] 800a24e: 2201 movs r2, #1 800a250: f883 2035 strb.w r2, [r3, #53] @ 0x35 } /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a254: 687b ldr r3, [r7, #4] 800a256: 2200 movs r2, #0 800a258: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 800a25c: 687b ldr r3, [r7, #4] 800a25e: 6cdb ldr r3, [r3, #76] @ 0x4c 800a260: 2b00 cmp r3, #0 800a262: f000 8272 beq.w 800a74a { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800a266: 687b ldr r3, [r7, #4] 800a268: 6cdb ldr r3, [r3, #76] @ 0x4c 800a26a: 6878 ldr r0, [r7, #4] 800a26c: 4798 blx r3 800a26e: e26c b.n 800a74a } } } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 800a270: 687b ldr r3, [r7, #4] 800a272: 681b ldr r3, [r3, #0] 800a274: 4a43 ldr r2, [pc, #268] @ (800a384 ) 800a276: 4293 cmp r3, r2 800a278: d022 beq.n 800a2c0 800a27a: 687b ldr r3, [r7, #4] 800a27c: 681b ldr r3, [r3, #0] 800a27e: 4a42 ldr r2, [pc, #264] @ (800a388 ) 800a280: 4293 cmp r3, r2 800a282: d01d beq.n 800a2c0 800a284: 687b ldr r3, [r7, #4] 800a286: 681b ldr r3, [r3, #0] 800a288: 4a40 ldr r2, [pc, #256] @ (800a38c ) 800a28a: 4293 cmp r3, r2 800a28c: d018 beq.n 800a2c0 800a28e: 687b ldr r3, [r7, #4] 800a290: 681b ldr r3, [r3, #0] 800a292: 4a3f ldr r2, [pc, #252] @ (800a390 ) 800a294: 4293 cmp r3, r2 800a296: d013 beq.n 800a2c0 800a298: 687b ldr r3, [r7, #4] 800a29a: 681b ldr r3, [r3, #0] 800a29c: 4a3d ldr r2, [pc, #244] @ (800a394 ) 800a29e: 4293 cmp r3, r2 800a2a0: d00e beq.n 800a2c0 800a2a2: 687b ldr r3, [r7, #4] 800a2a4: 681b ldr r3, [r3, #0] 800a2a6: 4a3c ldr r2, [pc, #240] @ (800a398 ) 800a2a8: 4293 cmp r3, r2 800a2aa: d009 beq.n 800a2c0 800a2ac: 687b ldr r3, [r7, #4] 800a2ae: 681b ldr r3, [r3, #0] 800a2b0: 4a3a ldr r2, [pc, #232] @ (800a39c ) 800a2b2: 4293 cmp r3, r2 800a2b4: d004 beq.n 800a2c0 800a2b6: 687b ldr r3, [r7, #4] 800a2b8: 681b ldr r3, [r3, #0] 800a2ba: 4a39 ldr r2, [pc, #228] @ (800a3a0 ) 800a2bc: 4293 cmp r3, r2 800a2be: d101 bne.n 800a2c4 800a2c0: 2301 movs r3, #1 800a2c2: e000 b.n 800a2c6 800a2c4: 2300 movs r3, #0 800a2c6: 2b00 cmp r3, #0 800a2c8: f000 823f beq.w 800a74a { ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); 800a2cc: 687b ldr r3, [r7, #4] 800a2ce: 681b ldr r3, [r3, #0] 800a2d0: 681b ldr r3, [r3, #0] 800a2d2: 613b str r3, [r7, #16] /* Half Transfer Complete Interrupt management ******************************/ if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) 800a2d4: 687b ldr r3, [r7, #4] 800a2d6: 6ddb ldr r3, [r3, #92] @ 0x5c 800a2d8: f003 031f and.w r3, r3, #31 800a2dc: 2204 movs r2, #4 800a2de: 409a lsls r2, r3 800a2e0: 697b ldr r3, [r7, #20] 800a2e2: 4013 ands r3, r2 800a2e4: 2b00 cmp r3, #0 800a2e6: f000 80cd beq.w 800a484 800a2ea: 693b ldr r3, [r7, #16] 800a2ec: f003 0304 and.w r3, r3, #4 800a2f0: 2b00 cmp r3, #0 800a2f2: f000 80c7 beq.w 800a484 { /* Clear the half transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); 800a2f6: 687b ldr r3, [r7, #4] 800a2f8: 6ddb ldr r3, [r3, #92] @ 0x5c 800a2fa: f003 031f and.w r3, r3, #31 800a2fe: 2204 movs r2, #4 800a300: 409a lsls r2, r3 800a302: 69fb ldr r3, [r7, #28] 800a304: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a306: 693b ldr r3, [r7, #16] 800a308: f403 4300 and.w r3, r3, #32768 @ 0x8000 800a30c: 2b00 cmp r3, #0 800a30e: d049 beq.n 800a3a4 { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 800a310: 693b ldr r3, [r7, #16] 800a312: f403 3380 and.w r3, r3, #65536 @ 0x10000 800a316: 2b00 cmp r3, #0 800a318: d109 bne.n 800a32e { if(hdma->XferM1HalfCpltCallback != NULL) 800a31a: 687b ldr r3, [r7, #4] 800a31c: 6c9b ldr r3, [r3, #72] @ 0x48 800a31e: 2b00 cmp r3, #0 800a320: f000 8210 beq.w 800a744 { /* Half transfer Callback for Memory 1 */ hdma->XferM1HalfCpltCallback(hdma); 800a324: 687b ldr r3, [r7, #4] 800a326: 6c9b ldr r3, [r3, #72] @ 0x48 800a328: 6878 ldr r0, [r7, #4] 800a32a: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a32c: e20a b.n 800a744 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferHalfCpltCallback != NULL) 800a32e: 687b ldr r3, [r7, #4] 800a330: 6c1b ldr r3, [r3, #64] @ 0x40 800a332: 2b00 cmp r3, #0 800a334: f000 8206 beq.w 800a744 { /* Half transfer Callback for Memory 0 */ hdma->XferHalfCpltCallback(hdma); 800a338: 687b ldr r3, [r7, #4] 800a33a: 6c1b ldr r3, [r3, #64] @ 0x40 800a33c: 6878 ldr r0, [r7, #4] 800a33e: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a340: e200 b.n 800a744 800a342: bf00 nop 800a344: 40020010 .word 0x40020010 800a348: 40020028 .word 0x40020028 800a34c: 40020040 .word 0x40020040 800a350: 40020058 .word 0x40020058 800a354: 40020070 .word 0x40020070 800a358: 40020088 .word 0x40020088 800a35c: 400200a0 .word 0x400200a0 800a360: 400200b8 .word 0x400200b8 800a364: 40020410 .word 0x40020410 800a368: 40020428 .word 0x40020428 800a36c: 40020440 .word 0x40020440 800a370: 40020458 .word 0x40020458 800a374: 40020470 .word 0x40020470 800a378: 40020488 .word 0x40020488 800a37c: 400204a0 .word 0x400204a0 800a380: 400204b8 .word 0x400204b8 800a384: 58025408 .word 0x58025408 800a388: 5802541c .word 0x5802541c 800a38c: 58025430 .word 0x58025430 800a390: 58025444 .word 0x58025444 800a394: 58025458 .word 0x58025458 800a398: 5802546c .word 0x5802546c 800a39c: 58025480 .word 0x58025480 800a3a0: 58025494 .word 0x58025494 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 800a3a4: 693b ldr r3, [r7, #16] 800a3a6: f003 0320 and.w r3, r3, #32 800a3aa: 2b00 cmp r3, #0 800a3ac: d160 bne.n 800a470 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800a3ae: 687b ldr r3, [r7, #4] 800a3b0: 681b ldr r3, [r3, #0] 800a3b2: 4a7f ldr r2, [pc, #508] @ (800a5b0 ) 800a3b4: 4293 cmp r3, r2 800a3b6: d04a beq.n 800a44e 800a3b8: 687b ldr r3, [r7, #4] 800a3ba: 681b ldr r3, [r3, #0] 800a3bc: 4a7d ldr r2, [pc, #500] @ (800a5b4 ) 800a3be: 4293 cmp r3, r2 800a3c0: d045 beq.n 800a44e 800a3c2: 687b ldr r3, [r7, #4] 800a3c4: 681b ldr r3, [r3, #0] 800a3c6: 4a7c ldr r2, [pc, #496] @ (800a5b8 ) 800a3c8: 4293 cmp r3, r2 800a3ca: d040 beq.n 800a44e 800a3cc: 687b ldr r3, [r7, #4] 800a3ce: 681b ldr r3, [r3, #0] 800a3d0: 4a7a ldr r2, [pc, #488] @ (800a5bc ) 800a3d2: 4293 cmp r3, r2 800a3d4: d03b beq.n 800a44e 800a3d6: 687b ldr r3, [r7, #4] 800a3d8: 681b ldr r3, [r3, #0] 800a3da: 4a79 ldr r2, [pc, #484] @ (800a5c0 ) 800a3dc: 4293 cmp r3, r2 800a3de: d036 beq.n 800a44e 800a3e0: 687b ldr r3, [r7, #4] 800a3e2: 681b ldr r3, [r3, #0] 800a3e4: 4a77 ldr r2, [pc, #476] @ (800a5c4 ) 800a3e6: 4293 cmp r3, r2 800a3e8: d031 beq.n 800a44e 800a3ea: 687b ldr r3, [r7, #4] 800a3ec: 681b ldr r3, [r3, #0] 800a3ee: 4a76 ldr r2, [pc, #472] @ (800a5c8 ) 800a3f0: 4293 cmp r3, r2 800a3f2: d02c beq.n 800a44e 800a3f4: 687b ldr r3, [r7, #4] 800a3f6: 681b ldr r3, [r3, #0] 800a3f8: 4a74 ldr r2, [pc, #464] @ (800a5cc ) 800a3fa: 4293 cmp r3, r2 800a3fc: d027 beq.n 800a44e 800a3fe: 687b ldr r3, [r7, #4] 800a400: 681b ldr r3, [r3, #0] 800a402: 4a73 ldr r2, [pc, #460] @ (800a5d0 ) 800a404: 4293 cmp r3, r2 800a406: d022 beq.n 800a44e 800a408: 687b ldr r3, [r7, #4] 800a40a: 681b ldr r3, [r3, #0] 800a40c: 4a71 ldr r2, [pc, #452] @ (800a5d4 ) 800a40e: 4293 cmp r3, r2 800a410: d01d beq.n 800a44e 800a412: 687b ldr r3, [r7, #4] 800a414: 681b ldr r3, [r3, #0] 800a416: 4a70 ldr r2, [pc, #448] @ (800a5d8 ) 800a418: 4293 cmp r3, r2 800a41a: d018 beq.n 800a44e 800a41c: 687b ldr r3, [r7, #4] 800a41e: 681b ldr r3, [r3, #0] 800a420: 4a6e ldr r2, [pc, #440] @ (800a5dc ) 800a422: 4293 cmp r3, r2 800a424: d013 beq.n 800a44e 800a426: 687b ldr r3, [r7, #4] 800a428: 681b ldr r3, [r3, #0] 800a42a: 4a6d ldr r2, [pc, #436] @ (800a5e0 ) 800a42c: 4293 cmp r3, r2 800a42e: d00e beq.n 800a44e 800a430: 687b ldr r3, [r7, #4] 800a432: 681b ldr r3, [r3, #0] 800a434: 4a6b ldr r2, [pc, #428] @ (800a5e4 ) 800a436: 4293 cmp r3, r2 800a438: d009 beq.n 800a44e 800a43a: 687b ldr r3, [r7, #4] 800a43c: 681b ldr r3, [r3, #0] 800a43e: 4a6a ldr r2, [pc, #424] @ (800a5e8 ) 800a440: 4293 cmp r3, r2 800a442: d004 beq.n 800a44e 800a444: 687b ldr r3, [r7, #4] 800a446: 681b ldr r3, [r3, #0] 800a448: 4a68 ldr r2, [pc, #416] @ (800a5ec ) 800a44a: 4293 cmp r3, r2 800a44c: d108 bne.n 800a460 800a44e: 687b ldr r3, [r7, #4] 800a450: 681b ldr r3, [r3, #0] 800a452: 681a ldr r2, [r3, #0] 800a454: 687b ldr r3, [r7, #4] 800a456: 681b ldr r3, [r3, #0] 800a458: f022 0208 bic.w r2, r2, #8 800a45c: 601a str r2, [r3, #0] 800a45e: e007 b.n 800a470 800a460: 687b ldr r3, [r7, #4] 800a462: 681b ldr r3, [r3, #0] 800a464: 681a ldr r2, [r3, #0] 800a466: 687b ldr r3, [r7, #4] 800a468: 681b ldr r3, [r3, #0] 800a46a: f022 0204 bic.w r2, r2, #4 800a46e: 601a str r2, [r3, #0] } /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 800a470: 687b ldr r3, [r7, #4] 800a472: 6c1b ldr r3, [r3, #64] @ 0x40 800a474: 2b00 cmp r3, #0 800a476: f000 8165 beq.w 800a744 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800a47a: 687b ldr r3, [r7, #4] 800a47c: 6c1b ldr r3, [r3, #64] @ 0x40 800a47e: 6878 ldr r0, [r7, #4] 800a480: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a482: e15f b.n 800a744 } } } /* Transfer Complete Interrupt management ***********************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) 800a484: 687b ldr r3, [r7, #4] 800a486: 6ddb ldr r3, [r3, #92] @ 0x5c 800a488: f003 031f and.w r3, r3, #31 800a48c: 2202 movs r2, #2 800a48e: 409a lsls r2, r3 800a490: 697b ldr r3, [r7, #20] 800a492: 4013 ands r3, r2 800a494: 2b00 cmp r3, #0 800a496: f000 80c5 beq.w 800a624 800a49a: 693b ldr r3, [r7, #16] 800a49c: f003 0302 and.w r3, r3, #2 800a4a0: 2b00 cmp r3, #0 800a4a2: f000 80bf beq.w 800a624 { /* Clear the transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); 800a4a6: 687b ldr r3, [r7, #4] 800a4a8: 6ddb ldr r3, [r3, #92] @ 0x5c 800a4aa: f003 031f and.w r3, r3, #31 800a4ae: 2202 movs r2, #2 800a4b0: 409a lsls r2, r3 800a4b2: 69fb ldr r3, [r7, #28] 800a4b4: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a4b6: 693b ldr r3, [r7, #16] 800a4b8: f403 4300 and.w r3, r3, #32768 @ 0x8000 800a4bc: 2b00 cmp r3, #0 800a4be: d018 beq.n 800a4f2 { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 800a4c0: 693b ldr r3, [r7, #16] 800a4c2: f403 3380 and.w r3, r3, #65536 @ 0x10000 800a4c6: 2b00 cmp r3, #0 800a4c8: d109 bne.n 800a4de { if(hdma->XferM1CpltCallback != NULL) 800a4ca: 687b ldr r3, [r7, #4] 800a4cc: 6c5b ldr r3, [r3, #68] @ 0x44 800a4ce: 2b00 cmp r3, #0 800a4d0: f000 813a beq.w 800a748 { /* Transfer complete Callback for Memory 1 */ hdma->XferM1CpltCallback(hdma); 800a4d4: 687b ldr r3, [r7, #4] 800a4d6: 6c5b ldr r3, [r3, #68] @ 0x44 800a4d8: 6878 ldr r0, [r7, #4] 800a4da: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a4dc: e134 b.n 800a748 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800a4de: 687b ldr r3, [r7, #4] 800a4e0: 6bdb ldr r3, [r3, #60] @ 0x3c 800a4e2: 2b00 cmp r3, #0 800a4e4: f000 8130 beq.w 800a748 { /* Transfer complete Callback for Memory 0 */ hdma->XferCpltCallback(hdma); 800a4e8: 687b ldr r3, [r7, #4] 800a4ea: 6bdb ldr r3, [r3, #60] @ 0x3c 800a4ec: 6878 ldr r0, [r7, #4] 800a4ee: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a4f0: e12a b.n 800a748 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 800a4f2: 693b ldr r3, [r7, #16] 800a4f4: f003 0320 and.w r3, r3, #32 800a4f8: 2b00 cmp r3, #0 800a4fa: f040 8089 bne.w 800a610 { /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 800a4fe: 687b ldr r3, [r7, #4] 800a500: 681b ldr r3, [r3, #0] 800a502: 4a2b ldr r2, [pc, #172] @ (800a5b0 ) 800a504: 4293 cmp r3, r2 800a506: d04a beq.n 800a59e 800a508: 687b ldr r3, [r7, #4] 800a50a: 681b ldr r3, [r3, #0] 800a50c: 4a29 ldr r2, [pc, #164] @ (800a5b4 ) 800a50e: 4293 cmp r3, r2 800a510: d045 beq.n 800a59e 800a512: 687b ldr r3, [r7, #4] 800a514: 681b ldr r3, [r3, #0] 800a516: 4a28 ldr r2, [pc, #160] @ (800a5b8 ) 800a518: 4293 cmp r3, r2 800a51a: d040 beq.n 800a59e 800a51c: 687b ldr r3, [r7, #4] 800a51e: 681b ldr r3, [r3, #0] 800a520: 4a26 ldr r2, [pc, #152] @ (800a5bc ) 800a522: 4293 cmp r3, r2 800a524: d03b beq.n 800a59e 800a526: 687b ldr r3, [r7, #4] 800a528: 681b ldr r3, [r3, #0] 800a52a: 4a25 ldr r2, [pc, #148] @ (800a5c0 ) 800a52c: 4293 cmp r3, r2 800a52e: d036 beq.n 800a59e 800a530: 687b ldr r3, [r7, #4] 800a532: 681b ldr r3, [r3, #0] 800a534: 4a23 ldr r2, [pc, #140] @ (800a5c4 ) 800a536: 4293 cmp r3, r2 800a538: d031 beq.n 800a59e 800a53a: 687b ldr r3, [r7, #4] 800a53c: 681b ldr r3, [r3, #0] 800a53e: 4a22 ldr r2, [pc, #136] @ (800a5c8 ) 800a540: 4293 cmp r3, r2 800a542: d02c beq.n 800a59e 800a544: 687b ldr r3, [r7, #4] 800a546: 681b ldr r3, [r3, #0] 800a548: 4a20 ldr r2, [pc, #128] @ (800a5cc ) 800a54a: 4293 cmp r3, r2 800a54c: d027 beq.n 800a59e 800a54e: 687b ldr r3, [r7, #4] 800a550: 681b ldr r3, [r3, #0] 800a552: 4a1f ldr r2, [pc, #124] @ (800a5d0 ) 800a554: 4293 cmp r3, r2 800a556: d022 beq.n 800a59e 800a558: 687b ldr r3, [r7, #4] 800a55a: 681b ldr r3, [r3, #0] 800a55c: 4a1d ldr r2, [pc, #116] @ (800a5d4 ) 800a55e: 4293 cmp r3, r2 800a560: d01d beq.n 800a59e 800a562: 687b ldr r3, [r7, #4] 800a564: 681b ldr r3, [r3, #0] 800a566: 4a1c ldr r2, [pc, #112] @ (800a5d8 ) 800a568: 4293 cmp r3, r2 800a56a: d018 beq.n 800a59e 800a56c: 687b ldr r3, [r7, #4] 800a56e: 681b ldr r3, [r3, #0] 800a570: 4a1a ldr r2, [pc, #104] @ (800a5dc ) 800a572: 4293 cmp r3, r2 800a574: d013 beq.n 800a59e 800a576: 687b ldr r3, [r7, #4] 800a578: 681b ldr r3, [r3, #0] 800a57a: 4a19 ldr r2, [pc, #100] @ (800a5e0 ) 800a57c: 4293 cmp r3, r2 800a57e: d00e beq.n 800a59e 800a580: 687b ldr r3, [r7, #4] 800a582: 681b ldr r3, [r3, #0] 800a584: 4a17 ldr r2, [pc, #92] @ (800a5e4 ) 800a586: 4293 cmp r3, r2 800a588: d009 beq.n 800a59e 800a58a: 687b ldr r3, [r7, #4] 800a58c: 681b ldr r3, [r3, #0] 800a58e: 4a16 ldr r2, [pc, #88] @ (800a5e8 ) 800a590: 4293 cmp r3, r2 800a592: d004 beq.n 800a59e 800a594: 687b ldr r3, [r7, #4] 800a596: 681b ldr r3, [r3, #0] 800a598: 4a14 ldr r2, [pc, #80] @ (800a5ec ) 800a59a: 4293 cmp r3, r2 800a59c: d128 bne.n 800a5f0 800a59e: 687b ldr r3, [r7, #4] 800a5a0: 681b ldr r3, [r3, #0] 800a5a2: 681a ldr r2, [r3, #0] 800a5a4: 687b ldr r3, [r7, #4] 800a5a6: 681b ldr r3, [r3, #0] 800a5a8: f022 0214 bic.w r2, r2, #20 800a5ac: 601a str r2, [r3, #0] 800a5ae: e027 b.n 800a600 800a5b0: 40020010 .word 0x40020010 800a5b4: 40020028 .word 0x40020028 800a5b8: 40020040 .word 0x40020040 800a5bc: 40020058 .word 0x40020058 800a5c0: 40020070 .word 0x40020070 800a5c4: 40020088 .word 0x40020088 800a5c8: 400200a0 .word 0x400200a0 800a5cc: 400200b8 .word 0x400200b8 800a5d0: 40020410 .word 0x40020410 800a5d4: 40020428 .word 0x40020428 800a5d8: 40020440 .word 0x40020440 800a5dc: 40020458 .word 0x40020458 800a5e0: 40020470 .word 0x40020470 800a5e4: 40020488 .word 0x40020488 800a5e8: 400204a0 .word 0x400204a0 800a5ec: 400204b8 .word 0x400204b8 800a5f0: 687b ldr r3, [r7, #4] 800a5f2: 681b ldr r3, [r3, #0] 800a5f4: 681a ldr r2, [r3, #0] 800a5f6: 687b ldr r3, [r7, #4] 800a5f8: 681b ldr r3, [r3, #0] 800a5fa: f022 020a bic.w r2, r2, #10 800a5fe: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a600: 687b ldr r3, [r7, #4] 800a602: 2201 movs r2, #1 800a604: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a608: 687b ldr r3, [r7, #4] 800a60a: 2200 movs r2, #0 800a60c: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 800a610: 687b ldr r3, [r7, #4] 800a612: 6bdb ldr r3, [r3, #60] @ 0x3c 800a614: 2b00 cmp r3, #0 800a616: f000 8097 beq.w 800a748 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 800a61a: 687b ldr r3, [r7, #4] 800a61c: 6bdb ldr r3, [r3, #60] @ 0x3c 800a61e: 6878 ldr r0, [r7, #4] 800a620: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a622: e091 b.n 800a748 } } } /* Transfer Error Interrupt management **************************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) 800a624: 687b ldr r3, [r7, #4] 800a626: 6ddb ldr r3, [r3, #92] @ 0x5c 800a628: f003 031f and.w r3, r3, #31 800a62c: 2208 movs r2, #8 800a62e: 409a lsls r2, r3 800a630: 697b ldr r3, [r7, #20] 800a632: 4013 ands r3, r2 800a634: 2b00 cmp r3, #0 800a636: f000 8088 beq.w 800a74a 800a63a: 693b ldr r3, [r7, #16] 800a63c: f003 0308 and.w r3, r3, #8 800a640: 2b00 cmp r3, #0 800a642: f000 8082 beq.w 800a74a { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800a646: 687b ldr r3, [r7, #4] 800a648: 681b ldr r3, [r3, #0] 800a64a: 4a41 ldr r2, [pc, #260] @ (800a750 ) 800a64c: 4293 cmp r3, r2 800a64e: d04a beq.n 800a6e6 800a650: 687b ldr r3, [r7, #4] 800a652: 681b ldr r3, [r3, #0] 800a654: 4a3f ldr r2, [pc, #252] @ (800a754 ) 800a656: 4293 cmp r3, r2 800a658: d045 beq.n 800a6e6 800a65a: 687b ldr r3, [r7, #4] 800a65c: 681b ldr r3, [r3, #0] 800a65e: 4a3e ldr r2, [pc, #248] @ (800a758 ) 800a660: 4293 cmp r3, r2 800a662: d040 beq.n 800a6e6 800a664: 687b ldr r3, [r7, #4] 800a666: 681b ldr r3, [r3, #0] 800a668: 4a3c ldr r2, [pc, #240] @ (800a75c ) 800a66a: 4293 cmp r3, r2 800a66c: d03b beq.n 800a6e6 800a66e: 687b ldr r3, [r7, #4] 800a670: 681b ldr r3, [r3, #0] 800a672: 4a3b ldr r2, [pc, #236] @ (800a760 ) 800a674: 4293 cmp r3, r2 800a676: d036 beq.n 800a6e6 800a678: 687b ldr r3, [r7, #4] 800a67a: 681b ldr r3, [r3, #0] 800a67c: 4a39 ldr r2, [pc, #228] @ (800a764 ) 800a67e: 4293 cmp r3, r2 800a680: d031 beq.n 800a6e6 800a682: 687b ldr r3, [r7, #4] 800a684: 681b ldr r3, [r3, #0] 800a686: 4a38 ldr r2, [pc, #224] @ (800a768 ) 800a688: 4293 cmp r3, r2 800a68a: d02c beq.n 800a6e6 800a68c: 687b ldr r3, [r7, #4] 800a68e: 681b ldr r3, [r3, #0] 800a690: 4a36 ldr r2, [pc, #216] @ (800a76c ) 800a692: 4293 cmp r3, r2 800a694: d027 beq.n 800a6e6 800a696: 687b ldr r3, [r7, #4] 800a698: 681b ldr r3, [r3, #0] 800a69a: 4a35 ldr r2, [pc, #212] @ (800a770 ) 800a69c: 4293 cmp r3, r2 800a69e: d022 beq.n 800a6e6 800a6a0: 687b ldr r3, [r7, #4] 800a6a2: 681b ldr r3, [r3, #0] 800a6a4: 4a33 ldr r2, [pc, #204] @ (800a774 ) 800a6a6: 4293 cmp r3, r2 800a6a8: d01d beq.n 800a6e6 800a6aa: 687b ldr r3, [r7, #4] 800a6ac: 681b ldr r3, [r3, #0] 800a6ae: 4a32 ldr r2, [pc, #200] @ (800a778 ) 800a6b0: 4293 cmp r3, r2 800a6b2: d018 beq.n 800a6e6 800a6b4: 687b ldr r3, [r7, #4] 800a6b6: 681b ldr r3, [r3, #0] 800a6b8: 4a30 ldr r2, [pc, #192] @ (800a77c ) 800a6ba: 4293 cmp r3, r2 800a6bc: d013 beq.n 800a6e6 800a6be: 687b ldr r3, [r7, #4] 800a6c0: 681b ldr r3, [r3, #0] 800a6c2: 4a2f ldr r2, [pc, #188] @ (800a780 ) 800a6c4: 4293 cmp r3, r2 800a6c6: d00e beq.n 800a6e6 800a6c8: 687b ldr r3, [r7, #4] 800a6ca: 681b ldr r3, [r3, #0] 800a6cc: 4a2d ldr r2, [pc, #180] @ (800a784 ) 800a6ce: 4293 cmp r3, r2 800a6d0: d009 beq.n 800a6e6 800a6d2: 687b ldr r3, [r7, #4] 800a6d4: 681b ldr r3, [r3, #0] 800a6d6: 4a2c ldr r2, [pc, #176] @ (800a788 ) 800a6d8: 4293 cmp r3, r2 800a6da: d004 beq.n 800a6e6 800a6dc: 687b ldr r3, [r7, #4] 800a6de: 681b ldr r3, [r3, #0] 800a6e0: 4a2a ldr r2, [pc, #168] @ (800a78c ) 800a6e2: 4293 cmp r3, r2 800a6e4: d108 bne.n 800a6f8 800a6e6: 687b ldr r3, [r7, #4] 800a6e8: 681b ldr r3, [r3, #0] 800a6ea: 681a ldr r2, [r3, #0] 800a6ec: 687b ldr r3, [r7, #4] 800a6ee: 681b ldr r3, [r3, #0] 800a6f0: f022 021c bic.w r2, r2, #28 800a6f4: 601a str r2, [r3, #0] 800a6f6: e007 b.n 800a708 800a6f8: 687b ldr r3, [r7, #4] 800a6fa: 681b ldr r3, [r3, #0] 800a6fc: 681a ldr r2, [r3, #0] 800a6fe: 687b ldr r3, [r7, #4] 800a700: 681b ldr r3, [r3, #0] 800a702: f022 020e bic.w r2, r2, #14 800a706: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 800a708: 687b ldr r3, [r7, #4] 800a70a: 6ddb ldr r3, [r3, #92] @ 0x5c 800a70c: f003 031f and.w r3, r3, #31 800a710: 2201 movs r2, #1 800a712: 409a lsls r2, r3 800a714: 69fb ldr r3, [r7, #28] 800a716: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 800a718: 687b ldr r3, [r7, #4] 800a71a: 2201 movs r2, #1 800a71c: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a71e: 687b ldr r3, [r7, #4] 800a720: 2201 movs r2, #1 800a722: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a726: 687b ldr r3, [r7, #4] 800a728: 2200 movs r2, #0 800a72a: f883 2034 strb.w r2, [r3, #52] @ 0x34 if (hdma->XferErrorCallback != NULL) 800a72e: 687b ldr r3, [r7, #4] 800a730: 6cdb ldr r3, [r3, #76] @ 0x4c 800a732: 2b00 cmp r3, #0 800a734: d009 beq.n 800a74a { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800a736: 687b ldr r3, [r7, #4] 800a738: 6cdb ldr r3, [r3, #76] @ 0x4c 800a73a: 6878 ldr r0, [r7, #4] 800a73c: 4798 blx r3 800a73e: e004 b.n 800a74a return; 800a740: bf00 nop 800a742: e002 b.n 800a74a if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a744: bf00 nop 800a746: e000 b.n 800a74a if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a748: bf00 nop } else { /* Nothing To Do */ } } 800a74a: 3728 adds r7, #40 @ 0x28 800a74c: 46bd mov sp, r7 800a74e: bd80 pop {r7, pc} 800a750: 40020010 .word 0x40020010 800a754: 40020028 .word 0x40020028 800a758: 40020040 .word 0x40020040 800a75c: 40020058 .word 0x40020058 800a760: 40020070 .word 0x40020070 800a764: 40020088 .word 0x40020088 800a768: 400200a0 .word 0x400200a0 800a76c: 400200b8 .word 0x400200b8 800a770: 40020410 .word 0x40020410 800a774: 40020428 .word 0x40020428 800a778: 40020440 .word 0x40020440 800a77c: 40020458 .word 0x40020458 800a780: 40020470 .word 0x40020470 800a784: 40020488 .word 0x40020488 800a788: 400204a0 .word 0x400204a0 800a78c: 400204b8 .word 0x400204b8 0800a790 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval None */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 800a790: b480 push {r7} 800a792: b087 sub sp, #28 800a794: af00 add r7, sp, #0 800a796: 60f8 str r0, [r7, #12] 800a798: 60b9 str r1, [r7, #8] 800a79a: 607a str r2, [r7, #4] 800a79c: 603b str r3, [r7, #0] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 800a79e: 68fb ldr r3, [r7, #12] 800a7a0: 6d9b ldr r3, [r3, #88] @ 0x58 800a7a2: 617b str r3, [r7, #20] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 800a7a4: 68fb ldr r3, [r7, #12] 800a7a6: 6d9b ldr r3, [r3, #88] @ 0x58 800a7a8: 613b str r3, [r7, #16] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800a7aa: 68fb ldr r3, [r7, #12] 800a7ac: 681b ldr r3, [r3, #0] 800a7ae: 4a7f ldr r2, [pc, #508] @ (800a9ac ) 800a7b0: 4293 cmp r3, r2 800a7b2: d072 beq.n 800a89a 800a7b4: 68fb ldr r3, [r7, #12] 800a7b6: 681b ldr r3, [r3, #0] 800a7b8: 4a7d ldr r2, [pc, #500] @ (800a9b0 ) 800a7ba: 4293 cmp r3, r2 800a7bc: d06d beq.n 800a89a 800a7be: 68fb ldr r3, [r7, #12] 800a7c0: 681b ldr r3, [r3, #0] 800a7c2: 4a7c ldr r2, [pc, #496] @ (800a9b4 ) 800a7c4: 4293 cmp r3, r2 800a7c6: d068 beq.n 800a89a 800a7c8: 68fb ldr r3, [r7, #12] 800a7ca: 681b ldr r3, [r3, #0] 800a7cc: 4a7a ldr r2, [pc, #488] @ (800a9b8 ) 800a7ce: 4293 cmp r3, r2 800a7d0: d063 beq.n 800a89a 800a7d2: 68fb ldr r3, [r7, #12] 800a7d4: 681b ldr r3, [r3, #0] 800a7d6: 4a79 ldr r2, [pc, #484] @ (800a9bc ) 800a7d8: 4293 cmp r3, r2 800a7da: d05e beq.n 800a89a 800a7dc: 68fb ldr r3, [r7, #12] 800a7de: 681b ldr r3, [r3, #0] 800a7e0: 4a77 ldr r2, [pc, #476] @ (800a9c0 ) 800a7e2: 4293 cmp r3, r2 800a7e4: d059 beq.n 800a89a 800a7e6: 68fb ldr r3, [r7, #12] 800a7e8: 681b ldr r3, [r3, #0] 800a7ea: 4a76 ldr r2, [pc, #472] @ (800a9c4 ) 800a7ec: 4293 cmp r3, r2 800a7ee: d054 beq.n 800a89a 800a7f0: 68fb ldr r3, [r7, #12] 800a7f2: 681b ldr r3, [r3, #0] 800a7f4: 4a74 ldr r2, [pc, #464] @ (800a9c8 ) 800a7f6: 4293 cmp r3, r2 800a7f8: d04f beq.n 800a89a 800a7fa: 68fb ldr r3, [r7, #12] 800a7fc: 681b ldr r3, [r3, #0] 800a7fe: 4a73 ldr r2, [pc, #460] @ (800a9cc ) 800a800: 4293 cmp r3, r2 800a802: d04a beq.n 800a89a 800a804: 68fb ldr r3, [r7, #12] 800a806: 681b ldr r3, [r3, #0] 800a808: 4a71 ldr r2, [pc, #452] @ (800a9d0 ) 800a80a: 4293 cmp r3, r2 800a80c: d045 beq.n 800a89a 800a80e: 68fb ldr r3, [r7, #12] 800a810: 681b ldr r3, [r3, #0] 800a812: 4a70 ldr r2, [pc, #448] @ (800a9d4 ) 800a814: 4293 cmp r3, r2 800a816: d040 beq.n 800a89a 800a818: 68fb ldr r3, [r7, #12] 800a81a: 681b ldr r3, [r3, #0] 800a81c: 4a6e ldr r2, [pc, #440] @ (800a9d8 ) 800a81e: 4293 cmp r3, r2 800a820: d03b beq.n 800a89a 800a822: 68fb ldr r3, [r7, #12] 800a824: 681b ldr r3, [r3, #0] 800a826: 4a6d ldr r2, [pc, #436] @ (800a9dc ) 800a828: 4293 cmp r3, r2 800a82a: d036 beq.n 800a89a 800a82c: 68fb ldr r3, [r7, #12] 800a82e: 681b ldr r3, [r3, #0] 800a830: 4a6b ldr r2, [pc, #428] @ (800a9e0 ) 800a832: 4293 cmp r3, r2 800a834: d031 beq.n 800a89a 800a836: 68fb ldr r3, [r7, #12] 800a838: 681b ldr r3, [r3, #0] 800a83a: 4a6a ldr r2, [pc, #424] @ (800a9e4 ) 800a83c: 4293 cmp r3, r2 800a83e: d02c beq.n 800a89a 800a840: 68fb ldr r3, [r7, #12] 800a842: 681b ldr r3, [r3, #0] 800a844: 4a68 ldr r2, [pc, #416] @ (800a9e8 ) 800a846: 4293 cmp r3, r2 800a848: d027 beq.n 800a89a 800a84a: 68fb ldr r3, [r7, #12] 800a84c: 681b ldr r3, [r3, #0] 800a84e: 4a67 ldr r2, [pc, #412] @ (800a9ec ) 800a850: 4293 cmp r3, r2 800a852: d022 beq.n 800a89a 800a854: 68fb ldr r3, [r7, #12] 800a856: 681b ldr r3, [r3, #0] 800a858: 4a65 ldr r2, [pc, #404] @ (800a9f0 ) 800a85a: 4293 cmp r3, r2 800a85c: d01d beq.n 800a89a 800a85e: 68fb ldr r3, [r7, #12] 800a860: 681b ldr r3, [r3, #0] 800a862: 4a64 ldr r2, [pc, #400] @ (800a9f4 ) 800a864: 4293 cmp r3, r2 800a866: d018 beq.n 800a89a 800a868: 68fb ldr r3, [r7, #12] 800a86a: 681b ldr r3, [r3, #0] 800a86c: 4a62 ldr r2, [pc, #392] @ (800a9f8 ) 800a86e: 4293 cmp r3, r2 800a870: d013 beq.n 800a89a 800a872: 68fb ldr r3, [r7, #12] 800a874: 681b ldr r3, [r3, #0] 800a876: 4a61 ldr r2, [pc, #388] @ (800a9fc ) 800a878: 4293 cmp r3, r2 800a87a: d00e beq.n 800a89a 800a87c: 68fb ldr r3, [r7, #12] 800a87e: 681b ldr r3, [r3, #0] 800a880: 4a5f ldr r2, [pc, #380] @ (800aa00 ) 800a882: 4293 cmp r3, r2 800a884: d009 beq.n 800a89a 800a886: 68fb ldr r3, [r7, #12] 800a888: 681b ldr r3, [r3, #0] 800a88a: 4a5e ldr r2, [pc, #376] @ (800aa04 ) 800a88c: 4293 cmp r3, r2 800a88e: d004 beq.n 800a89a 800a890: 68fb ldr r3, [r7, #12] 800a892: 681b ldr r3, [r3, #0] 800a894: 4a5c ldr r2, [pc, #368] @ (800aa08 ) 800a896: 4293 cmp r3, r2 800a898: d101 bne.n 800a89e 800a89a: 2301 movs r3, #1 800a89c: e000 b.n 800a8a0 800a89e: 2300 movs r3, #0 800a8a0: 2b00 cmp r3, #0 800a8a2: d00d beq.n 800a8c0 { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 800a8a4: 68fb ldr r3, [r7, #12] 800a8a6: 6e5b ldr r3, [r3, #100] @ 0x64 800a8a8: 68fa ldr r2, [r7, #12] 800a8aa: 6e92 ldr r2, [r2, #104] @ 0x68 800a8ac: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 800a8ae: 68fb ldr r3, [r7, #12] 800a8b0: 6edb ldr r3, [r3, #108] @ 0x6c 800a8b2: 2b00 cmp r3, #0 800a8b4: d004 beq.n 800a8c0 { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 800a8b6: 68fb ldr r3, [r7, #12] 800a8b8: 6f1b ldr r3, [r3, #112] @ 0x70 800a8ba: 68fa ldr r2, [r7, #12] 800a8bc: 6f52 ldr r2, [r2, #116] @ 0x74 800a8be: 605a str r2, [r3, #4] } } if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800a8c0: 68fb ldr r3, [r7, #12] 800a8c2: 681b ldr r3, [r3, #0] 800a8c4: 4a39 ldr r2, [pc, #228] @ (800a9ac ) 800a8c6: 4293 cmp r3, r2 800a8c8: d04a beq.n 800a960 800a8ca: 68fb ldr r3, [r7, #12] 800a8cc: 681b ldr r3, [r3, #0] 800a8ce: 4a38 ldr r2, [pc, #224] @ (800a9b0 ) 800a8d0: 4293 cmp r3, r2 800a8d2: d045 beq.n 800a960 800a8d4: 68fb ldr r3, [r7, #12] 800a8d6: 681b ldr r3, [r3, #0] 800a8d8: 4a36 ldr r2, [pc, #216] @ (800a9b4 ) 800a8da: 4293 cmp r3, r2 800a8dc: d040 beq.n 800a960 800a8de: 68fb ldr r3, [r7, #12] 800a8e0: 681b ldr r3, [r3, #0] 800a8e2: 4a35 ldr r2, [pc, #212] @ (800a9b8 ) 800a8e4: 4293 cmp r3, r2 800a8e6: d03b beq.n 800a960 800a8e8: 68fb ldr r3, [r7, #12] 800a8ea: 681b ldr r3, [r3, #0] 800a8ec: 4a33 ldr r2, [pc, #204] @ (800a9bc ) 800a8ee: 4293 cmp r3, r2 800a8f0: d036 beq.n 800a960 800a8f2: 68fb ldr r3, [r7, #12] 800a8f4: 681b ldr r3, [r3, #0] 800a8f6: 4a32 ldr r2, [pc, #200] @ (800a9c0 ) 800a8f8: 4293 cmp r3, r2 800a8fa: d031 beq.n 800a960 800a8fc: 68fb ldr r3, [r7, #12] 800a8fe: 681b ldr r3, [r3, #0] 800a900: 4a30 ldr r2, [pc, #192] @ (800a9c4 ) 800a902: 4293 cmp r3, r2 800a904: d02c beq.n 800a960 800a906: 68fb ldr r3, [r7, #12] 800a908: 681b ldr r3, [r3, #0] 800a90a: 4a2f ldr r2, [pc, #188] @ (800a9c8 ) 800a90c: 4293 cmp r3, r2 800a90e: d027 beq.n 800a960 800a910: 68fb ldr r3, [r7, #12] 800a912: 681b ldr r3, [r3, #0] 800a914: 4a2d ldr r2, [pc, #180] @ (800a9cc ) 800a916: 4293 cmp r3, r2 800a918: d022 beq.n 800a960 800a91a: 68fb ldr r3, [r7, #12] 800a91c: 681b ldr r3, [r3, #0] 800a91e: 4a2c ldr r2, [pc, #176] @ (800a9d0 ) 800a920: 4293 cmp r3, r2 800a922: d01d beq.n 800a960 800a924: 68fb ldr r3, [r7, #12] 800a926: 681b ldr r3, [r3, #0] 800a928: 4a2a ldr r2, [pc, #168] @ (800a9d4 ) 800a92a: 4293 cmp r3, r2 800a92c: d018 beq.n 800a960 800a92e: 68fb ldr r3, [r7, #12] 800a930: 681b ldr r3, [r3, #0] 800a932: 4a29 ldr r2, [pc, #164] @ (800a9d8 ) 800a934: 4293 cmp r3, r2 800a936: d013 beq.n 800a960 800a938: 68fb ldr r3, [r7, #12] 800a93a: 681b ldr r3, [r3, #0] 800a93c: 4a27 ldr r2, [pc, #156] @ (800a9dc ) 800a93e: 4293 cmp r3, r2 800a940: d00e beq.n 800a960 800a942: 68fb ldr r3, [r7, #12] 800a944: 681b ldr r3, [r3, #0] 800a946: 4a26 ldr r2, [pc, #152] @ (800a9e0 ) 800a948: 4293 cmp r3, r2 800a94a: d009 beq.n 800a960 800a94c: 68fb ldr r3, [r7, #12] 800a94e: 681b ldr r3, [r3, #0] 800a950: 4a24 ldr r2, [pc, #144] @ (800a9e4 ) 800a952: 4293 cmp r3, r2 800a954: d004 beq.n 800a960 800a956: 68fb ldr r3, [r7, #12] 800a958: 681b ldr r3, [r3, #0] 800a95a: 4a23 ldr r2, [pc, #140] @ (800a9e8 ) 800a95c: 4293 cmp r3, r2 800a95e: d101 bne.n 800a964 800a960: 2301 movs r3, #1 800a962: e000 b.n 800a966 800a964: 2300 movs r3, #0 800a966: 2b00 cmp r3, #0 800a968: d059 beq.n 800aa1e { /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800a96a: 68fb ldr r3, [r7, #12] 800a96c: 6ddb ldr r3, [r3, #92] @ 0x5c 800a96e: f003 031f and.w r3, r3, #31 800a972: 223f movs r2, #63 @ 0x3f 800a974: 409a lsls r2, r3 800a976: 697b ldr r3, [r7, #20] 800a978: 609a str r2, [r3, #8] /* Clear DBM bit */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM); 800a97a: 68fb ldr r3, [r7, #12] 800a97c: 681b ldr r3, [r3, #0] 800a97e: 681a ldr r2, [r3, #0] 800a980: 68fb ldr r3, [r7, #12] 800a982: 681b ldr r3, [r3, #0] 800a984: f422 2280 bic.w r2, r2, #262144 @ 0x40000 800a988: 601a str r2, [r3, #0] /* Configure DMA Stream data length */ ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; 800a98a: 68fb ldr r3, [r7, #12] 800a98c: 681b ldr r3, [r3, #0] 800a98e: 683a ldr r2, [r7, #0] 800a990: 605a str r2, [r3, #4] /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800a992: 68fb ldr r3, [r7, #12] 800a994: 689b ldr r3, [r3, #8] 800a996: 2b40 cmp r3, #64 @ 0x40 800a998: d138 bne.n 800aa0c { /* Configure DMA Stream destination address */ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; 800a99a: 68fb ldr r3, [r7, #12] 800a99c: 681b ldr r3, [r3, #0] 800a99e: 687a ldr r2, [r7, #4] 800a9a0: 609a str r2, [r3, #8] /* Configure DMA Stream source address */ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; 800a9a2: 68fb ldr r3, [r7, #12] 800a9a4: 681b ldr r3, [r3, #0] 800a9a6: 68ba ldr r2, [r7, #8] 800a9a8: 60da str r2, [r3, #12] } else { /* Nothing To Do */ } } 800a9aa: e086 b.n 800aaba 800a9ac: 40020010 .word 0x40020010 800a9b0: 40020028 .word 0x40020028 800a9b4: 40020040 .word 0x40020040 800a9b8: 40020058 .word 0x40020058 800a9bc: 40020070 .word 0x40020070 800a9c0: 40020088 .word 0x40020088 800a9c4: 400200a0 .word 0x400200a0 800a9c8: 400200b8 .word 0x400200b8 800a9cc: 40020410 .word 0x40020410 800a9d0: 40020428 .word 0x40020428 800a9d4: 40020440 .word 0x40020440 800a9d8: 40020458 .word 0x40020458 800a9dc: 40020470 .word 0x40020470 800a9e0: 40020488 .word 0x40020488 800a9e4: 400204a0 .word 0x400204a0 800a9e8: 400204b8 .word 0x400204b8 800a9ec: 58025408 .word 0x58025408 800a9f0: 5802541c .word 0x5802541c 800a9f4: 58025430 .word 0x58025430 800a9f8: 58025444 .word 0x58025444 800a9fc: 58025458 .word 0x58025458 800aa00: 5802546c .word 0x5802546c 800aa04: 58025480 .word 0x58025480 800aa08: 58025494 .word 0x58025494 ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; 800aa0c: 68fb ldr r3, [r7, #12] 800aa0e: 681b ldr r3, [r3, #0] 800aa10: 68ba ldr r2, [r7, #8] 800aa12: 609a str r2, [r3, #8] ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; 800aa14: 68fb ldr r3, [r7, #12] 800aa16: 681b ldr r3, [r3, #0] 800aa18: 687a ldr r2, [r7, #4] 800aa1a: 60da str r2, [r3, #12] } 800aa1c: e04d b.n 800aaba else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 800aa1e: 68fb ldr r3, [r7, #12] 800aa20: 681b ldr r3, [r3, #0] 800aa22: 4a29 ldr r2, [pc, #164] @ (800aac8 ) 800aa24: 4293 cmp r3, r2 800aa26: d022 beq.n 800aa6e 800aa28: 68fb ldr r3, [r7, #12] 800aa2a: 681b ldr r3, [r3, #0] 800aa2c: 4a27 ldr r2, [pc, #156] @ (800aacc ) 800aa2e: 4293 cmp r3, r2 800aa30: d01d beq.n 800aa6e 800aa32: 68fb ldr r3, [r7, #12] 800aa34: 681b ldr r3, [r3, #0] 800aa36: 4a26 ldr r2, [pc, #152] @ (800aad0 ) 800aa38: 4293 cmp r3, r2 800aa3a: d018 beq.n 800aa6e 800aa3c: 68fb ldr r3, [r7, #12] 800aa3e: 681b ldr r3, [r3, #0] 800aa40: 4a24 ldr r2, [pc, #144] @ (800aad4 ) 800aa42: 4293 cmp r3, r2 800aa44: d013 beq.n 800aa6e 800aa46: 68fb ldr r3, [r7, #12] 800aa48: 681b ldr r3, [r3, #0] 800aa4a: 4a23 ldr r2, [pc, #140] @ (800aad8 ) 800aa4c: 4293 cmp r3, r2 800aa4e: d00e beq.n 800aa6e 800aa50: 68fb ldr r3, [r7, #12] 800aa52: 681b ldr r3, [r3, #0] 800aa54: 4a21 ldr r2, [pc, #132] @ (800aadc ) 800aa56: 4293 cmp r3, r2 800aa58: d009 beq.n 800aa6e 800aa5a: 68fb ldr r3, [r7, #12] 800aa5c: 681b ldr r3, [r3, #0] 800aa5e: 4a20 ldr r2, [pc, #128] @ (800aae0 ) 800aa60: 4293 cmp r3, r2 800aa62: d004 beq.n 800aa6e 800aa64: 68fb ldr r3, [r7, #12] 800aa66: 681b ldr r3, [r3, #0] 800aa68: 4a1e ldr r2, [pc, #120] @ (800aae4 ) 800aa6a: 4293 cmp r3, r2 800aa6c: d101 bne.n 800aa72 800aa6e: 2301 movs r3, #1 800aa70: e000 b.n 800aa74 800aa72: 2300 movs r3, #0 800aa74: 2b00 cmp r3, #0 800aa76: d020 beq.n 800aaba regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 800aa78: 68fb ldr r3, [r7, #12] 800aa7a: 6ddb ldr r3, [r3, #92] @ 0x5c 800aa7c: f003 031f and.w r3, r3, #31 800aa80: 2201 movs r2, #1 800aa82: 409a lsls r2, r3 800aa84: 693b ldr r3, [r7, #16] 800aa86: 605a str r2, [r3, #4] ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; 800aa88: 68fb ldr r3, [r7, #12] 800aa8a: 681b ldr r3, [r3, #0] 800aa8c: 683a ldr r2, [r7, #0] 800aa8e: 605a str r2, [r3, #4] if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800aa90: 68fb ldr r3, [r7, #12] 800aa92: 689b ldr r3, [r3, #8] 800aa94: 2b40 cmp r3, #64 @ 0x40 800aa96: d108 bne.n 800aaaa ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; 800aa98: 68fb ldr r3, [r7, #12] 800aa9a: 681b ldr r3, [r3, #0] 800aa9c: 687a ldr r2, [r7, #4] 800aa9e: 609a str r2, [r3, #8] ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; 800aaa0: 68fb ldr r3, [r7, #12] 800aaa2: 681b ldr r3, [r3, #0] 800aaa4: 68ba ldr r2, [r7, #8] 800aaa6: 60da str r2, [r3, #12] } 800aaa8: e007 b.n 800aaba ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; 800aaaa: 68fb ldr r3, [r7, #12] 800aaac: 681b ldr r3, [r3, #0] 800aaae: 68ba ldr r2, [r7, #8] 800aab0: 609a str r2, [r3, #8] ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; 800aab2: 68fb ldr r3, [r7, #12] 800aab4: 681b ldr r3, [r3, #0] 800aab6: 687a ldr r2, [r7, #4] 800aab8: 60da str r2, [r3, #12] } 800aaba: bf00 nop 800aabc: 371c adds r7, #28 800aabe: 46bd mov sp, r7 800aac0: f85d 7b04 ldr.w r7, [sp], #4 800aac4: 4770 bx lr 800aac6: bf00 nop 800aac8: 58025408 .word 0x58025408 800aacc: 5802541c .word 0x5802541c 800aad0: 58025430 .word 0x58025430 800aad4: 58025444 .word 0x58025444 800aad8: 58025458 .word 0x58025458 800aadc: 5802546c .word 0x5802546c 800aae0: 58025480 .word 0x58025480 800aae4: 58025494 .word 0x58025494 0800aae8 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 800aae8: b480 push {r7} 800aaea: b085 sub sp, #20 800aaec: af00 add r7, sp, #0 800aaee: 6078 str r0, [r7, #4] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800aaf0: 687b ldr r3, [r7, #4] 800aaf2: 681b ldr r3, [r3, #0] 800aaf4: 4a42 ldr r2, [pc, #264] @ (800ac00 ) 800aaf6: 4293 cmp r3, r2 800aaf8: d04a beq.n 800ab90 800aafa: 687b ldr r3, [r7, #4] 800aafc: 681b ldr r3, [r3, #0] 800aafe: 4a41 ldr r2, [pc, #260] @ (800ac04 ) 800ab00: 4293 cmp r3, r2 800ab02: d045 beq.n 800ab90 800ab04: 687b ldr r3, [r7, #4] 800ab06: 681b ldr r3, [r3, #0] 800ab08: 4a3f ldr r2, [pc, #252] @ (800ac08 ) 800ab0a: 4293 cmp r3, r2 800ab0c: d040 beq.n 800ab90 800ab0e: 687b ldr r3, [r7, #4] 800ab10: 681b ldr r3, [r3, #0] 800ab12: 4a3e ldr r2, [pc, #248] @ (800ac0c ) 800ab14: 4293 cmp r3, r2 800ab16: d03b beq.n 800ab90 800ab18: 687b ldr r3, [r7, #4] 800ab1a: 681b ldr r3, [r3, #0] 800ab1c: 4a3c ldr r2, [pc, #240] @ (800ac10 ) 800ab1e: 4293 cmp r3, r2 800ab20: d036 beq.n 800ab90 800ab22: 687b ldr r3, [r7, #4] 800ab24: 681b ldr r3, [r3, #0] 800ab26: 4a3b ldr r2, [pc, #236] @ (800ac14 ) 800ab28: 4293 cmp r3, r2 800ab2a: d031 beq.n 800ab90 800ab2c: 687b ldr r3, [r7, #4] 800ab2e: 681b ldr r3, [r3, #0] 800ab30: 4a39 ldr r2, [pc, #228] @ (800ac18 ) 800ab32: 4293 cmp r3, r2 800ab34: d02c beq.n 800ab90 800ab36: 687b ldr r3, [r7, #4] 800ab38: 681b ldr r3, [r3, #0] 800ab3a: 4a38 ldr r2, [pc, #224] @ (800ac1c ) 800ab3c: 4293 cmp r3, r2 800ab3e: d027 beq.n 800ab90 800ab40: 687b ldr r3, [r7, #4] 800ab42: 681b ldr r3, [r3, #0] 800ab44: 4a36 ldr r2, [pc, #216] @ (800ac20 ) 800ab46: 4293 cmp r3, r2 800ab48: d022 beq.n 800ab90 800ab4a: 687b ldr r3, [r7, #4] 800ab4c: 681b ldr r3, [r3, #0] 800ab4e: 4a35 ldr r2, [pc, #212] @ (800ac24 ) 800ab50: 4293 cmp r3, r2 800ab52: d01d beq.n 800ab90 800ab54: 687b ldr r3, [r7, #4] 800ab56: 681b ldr r3, [r3, #0] 800ab58: 4a33 ldr r2, [pc, #204] @ (800ac28 ) 800ab5a: 4293 cmp r3, r2 800ab5c: d018 beq.n 800ab90 800ab5e: 687b ldr r3, [r7, #4] 800ab60: 681b ldr r3, [r3, #0] 800ab62: 4a32 ldr r2, [pc, #200] @ (800ac2c ) 800ab64: 4293 cmp r3, r2 800ab66: d013 beq.n 800ab90 800ab68: 687b ldr r3, [r7, #4] 800ab6a: 681b ldr r3, [r3, #0] 800ab6c: 4a30 ldr r2, [pc, #192] @ (800ac30 ) 800ab6e: 4293 cmp r3, r2 800ab70: d00e beq.n 800ab90 800ab72: 687b ldr r3, [r7, #4] 800ab74: 681b ldr r3, [r3, #0] 800ab76: 4a2f ldr r2, [pc, #188] @ (800ac34 ) 800ab78: 4293 cmp r3, r2 800ab7a: d009 beq.n 800ab90 800ab7c: 687b ldr r3, [r7, #4] 800ab7e: 681b ldr r3, [r3, #0] 800ab80: 4a2d ldr r2, [pc, #180] @ (800ac38 ) 800ab82: 4293 cmp r3, r2 800ab84: d004 beq.n 800ab90 800ab86: 687b ldr r3, [r7, #4] 800ab88: 681b ldr r3, [r3, #0] 800ab8a: 4a2c ldr r2, [pc, #176] @ (800ac3c ) 800ab8c: 4293 cmp r3, r2 800ab8e: d101 bne.n 800ab94 800ab90: 2301 movs r3, #1 800ab92: e000 b.n 800ab96 800ab94: 2300 movs r3, #0 800ab96: 2b00 cmp r3, #0 800ab98: d024 beq.n 800abe4 { uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800ab9a: 687b ldr r3, [r7, #4] 800ab9c: 681b ldr r3, [r3, #0] 800ab9e: b2db uxtb r3, r3 800aba0: 3b10 subs r3, #16 800aba2: 4a27 ldr r2, [pc, #156] @ (800ac40 ) 800aba4: fba2 2303 umull r2, r3, r2, r3 800aba8: 091b lsrs r3, r3, #4 800abaa: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; 800abac: 68fb ldr r3, [r7, #12] 800abae: f003 0307 and.w r3, r3, #7 800abb2: 4a24 ldr r2, [pc, #144] @ (800ac44 ) 800abb4: 5cd3 ldrb r3, [r2, r3] 800abb6: 461a mov r2, r3 800abb8: 687b ldr r3, [r7, #4] 800abba: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 800abbc: 68fb ldr r3, [r7, #12] 800abbe: 2b03 cmp r3, #3 800abc0: d908 bls.n 800abd4 { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); 800abc2: 687b ldr r3, [r7, #4] 800abc4: 681b ldr r3, [r3, #0] 800abc6: 461a mov r2, r3 800abc8: 4b1f ldr r3, [pc, #124] @ (800ac48 ) 800abca: 4013 ands r3, r2 800abcc: 1d1a adds r2, r3, #4 800abce: 687b ldr r3, [r7, #4] 800abd0: 659a str r2, [r3, #88] @ 0x58 800abd2: e00d b.n 800abf0 } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); 800abd4: 687b ldr r3, [r7, #4] 800abd6: 681b ldr r3, [r3, #0] 800abd8: 461a mov r2, r3 800abda: 4b1b ldr r3, [pc, #108] @ (800ac48 ) 800abdc: 4013 ands r3, r2 800abde: 687a ldr r2, [r7, #4] 800abe0: 6593 str r3, [r2, #88] @ 0x58 800abe2: e005 b.n 800abf0 } } else /* BDMA instance(s) */ { /* return pointer to ISR and IFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); 800abe4: 687b ldr r3, [r7, #4] 800abe6: 681b ldr r3, [r3, #0] 800abe8: f023 02ff bic.w r2, r3, #255 @ 0xff 800abec: 687b ldr r3, [r7, #4] 800abee: 659a str r2, [r3, #88] @ 0x58 } return hdma->StreamBaseAddress; 800abf0: 687b ldr r3, [r7, #4] 800abf2: 6d9b ldr r3, [r3, #88] @ 0x58 } 800abf4: 4618 mov r0, r3 800abf6: 3714 adds r7, #20 800abf8: 46bd mov sp, r7 800abfa: f85d 7b04 ldr.w r7, [sp], #4 800abfe: 4770 bx lr 800ac00: 40020010 .word 0x40020010 800ac04: 40020028 .word 0x40020028 800ac08: 40020040 .word 0x40020040 800ac0c: 40020058 .word 0x40020058 800ac10: 40020070 .word 0x40020070 800ac14: 40020088 .word 0x40020088 800ac18: 400200a0 .word 0x400200a0 800ac1c: 400200b8 .word 0x400200b8 800ac20: 40020410 .word 0x40020410 800ac24: 40020428 .word 0x40020428 800ac28: 40020440 .word 0x40020440 800ac2c: 40020458 .word 0x40020458 800ac30: 40020470 .word 0x40020470 800ac34: 40020488 .word 0x40020488 800ac38: 400204a0 .word 0x400204a0 800ac3c: 400204b8 .word 0x400204b8 800ac40: aaaaaaab .word 0xaaaaaaab 800ac44: 08018b6c .word 0x08018b6c 800ac48: fffffc00 .word 0xfffffc00 0800ac4c : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 800ac4c: b480 push {r7} 800ac4e: b085 sub sp, #20 800ac50: af00 add r7, sp, #0 800ac52: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800ac54: 2300 movs r3, #0 800ac56: 73fb strb r3, [r7, #15] /* Memory Data size equal to Byte */ if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 800ac58: 687b ldr r3, [r7, #4] 800ac5a: 699b ldr r3, [r3, #24] 800ac5c: 2b00 cmp r3, #0 800ac5e: d120 bne.n 800aca2 { switch (hdma->Init.FIFOThreshold) 800ac60: 687b ldr r3, [r7, #4] 800ac62: 6a9b ldr r3, [r3, #40] @ 0x28 800ac64: 2b03 cmp r3, #3 800ac66: d858 bhi.n 800ad1a 800ac68: a201 add r2, pc, #4 @ (adr r2, 800ac70 ) 800ac6a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ac6e: bf00 nop 800ac70: 0800ac81 .word 0x0800ac81 800ac74: 0800ac93 .word 0x0800ac93 800ac78: 0800ac81 .word 0x0800ac81 800ac7c: 0800ad1b .word 0x0800ad1b { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800ac80: 687b ldr r3, [r7, #4] 800ac82: 6adb ldr r3, [r3, #44] @ 0x2c 800ac84: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800ac88: 2b00 cmp r3, #0 800ac8a: d048 beq.n 800ad1e { status = HAL_ERROR; 800ac8c: 2301 movs r3, #1 800ac8e: 73fb strb r3, [r7, #15] } break; 800ac90: e045 b.n 800ad1e case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 800ac92: 687b ldr r3, [r7, #4] 800ac94: 6adb ldr r3, [r3, #44] @ 0x2c 800ac96: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800ac9a: d142 bne.n 800ad22 { status = HAL_ERROR; 800ac9c: 2301 movs r3, #1 800ac9e: 73fb strb r3, [r7, #15] } break; 800aca0: e03f b.n 800ad22 break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 800aca2: 687b ldr r3, [r7, #4] 800aca4: 699b ldr r3, [r3, #24] 800aca6: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800acaa: d123 bne.n 800acf4 { switch (hdma->Init.FIFOThreshold) 800acac: 687b ldr r3, [r7, #4] 800acae: 6a9b ldr r3, [r3, #40] @ 0x28 800acb0: 2b03 cmp r3, #3 800acb2: d838 bhi.n 800ad26 800acb4: a201 add r2, pc, #4 @ (adr r2, 800acbc ) 800acb6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800acba: bf00 nop 800acbc: 0800accd .word 0x0800accd 800acc0: 0800acd3 .word 0x0800acd3 800acc4: 0800accd .word 0x0800accd 800acc8: 0800ace5 .word 0x0800ace5 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 800accc: 2301 movs r3, #1 800acce: 73fb strb r3, [r7, #15] break; 800acd0: e030 b.n 800ad34 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800acd2: 687b ldr r3, [r7, #4] 800acd4: 6adb ldr r3, [r3, #44] @ 0x2c 800acd6: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800acda: 2b00 cmp r3, #0 800acdc: d025 beq.n 800ad2a { status = HAL_ERROR; 800acde: 2301 movs r3, #1 800ace0: 73fb strb r3, [r7, #15] } break; 800ace2: e022 b.n 800ad2a case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 800ace4: 687b ldr r3, [r7, #4] 800ace6: 6adb ldr r3, [r3, #44] @ 0x2c 800ace8: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800acec: d11f bne.n 800ad2e { status = HAL_ERROR; 800acee: 2301 movs r3, #1 800acf0: 73fb strb r3, [r7, #15] } break; 800acf2: e01c b.n 800ad2e } /* Memory Data size equal to Word */ else { switch (hdma->Init.FIFOThreshold) 800acf4: 687b ldr r3, [r7, #4] 800acf6: 6a9b ldr r3, [r3, #40] @ 0x28 800acf8: 2b02 cmp r3, #2 800acfa: d902 bls.n 800ad02 800acfc: 2b03 cmp r3, #3 800acfe: d003 beq.n 800ad08 status = HAL_ERROR; } break; default: break; 800ad00: e018 b.n 800ad34 status = HAL_ERROR; 800ad02: 2301 movs r3, #1 800ad04: 73fb strb r3, [r7, #15] break; 800ad06: e015 b.n 800ad34 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800ad08: 687b ldr r3, [r7, #4] 800ad0a: 6adb ldr r3, [r3, #44] @ 0x2c 800ad0c: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800ad10: 2b00 cmp r3, #0 800ad12: d00e beq.n 800ad32 status = HAL_ERROR; 800ad14: 2301 movs r3, #1 800ad16: 73fb strb r3, [r7, #15] break; 800ad18: e00b b.n 800ad32 break; 800ad1a: bf00 nop 800ad1c: e00a b.n 800ad34 break; 800ad1e: bf00 nop 800ad20: e008 b.n 800ad34 break; 800ad22: bf00 nop 800ad24: e006 b.n 800ad34 break; 800ad26: bf00 nop 800ad28: e004 b.n 800ad34 break; 800ad2a: bf00 nop 800ad2c: e002 b.n 800ad34 break; 800ad2e: bf00 nop 800ad30: e000 b.n 800ad34 break; 800ad32: bf00 nop } } return status; 800ad34: 7bfb ldrb r3, [r7, #15] } 800ad36: 4618 mov r0, r3 800ad38: 3714 adds r7, #20 800ad3a: 46bd mov sp, r7 800ad3c: f85d 7b04 ldr.w r7, [sp], #4 800ad40: 4770 bx lr 800ad42: bf00 nop 0800ad44 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 800ad44: b480 push {r7} 800ad46: b085 sub sp, #20 800ad48: af00 add r7, sp, #0 800ad4a: 6078 str r0, [r7, #4] uint32_t stream_number; uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); 800ad4c: 687b ldr r3, [r7, #4] 800ad4e: 681b ldr r3, [r3, #0] 800ad50: 60bb str r3, [r7, #8] if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 800ad52: 687b ldr r3, [r7, #4] 800ad54: 681b ldr r3, [r3, #0] 800ad56: 4a38 ldr r2, [pc, #224] @ (800ae38 ) 800ad58: 4293 cmp r3, r2 800ad5a: d022 beq.n 800ada2 800ad5c: 687b ldr r3, [r7, #4] 800ad5e: 681b ldr r3, [r3, #0] 800ad60: 4a36 ldr r2, [pc, #216] @ (800ae3c ) 800ad62: 4293 cmp r3, r2 800ad64: d01d beq.n 800ada2 800ad66: 687b ldr r3, [r7, #4] 800ad68: 681b ldr r3, [r3, #0] 800ad6a: 4a35 ldr r2, [pc, #212] @ (800ae40 ) 800ad6c: 4293 cmp r3, r2 800ad6e: d018 beq.n 800ada2 800ad70: 687b ldr r3, [r7, #4] 800ad72: 681b ldr r3, [r3, #0] 800ad74: 4a33 ldr r2, [pc, #204] @ (800ae44 ) 800ad76: 4293 cmp r3, r2 800ad78: d013 beq.n 800ada2 800ad7a: 687b ldr r3, [r7, #4] 800ad7c: 681b ldr r3, [r3, #0] 800ad7e: 4a32 ldr r2, [pc, #200] @ (800ae48 ) 800ad80: 4293 cmp r3, r2 800ad82: d00e beq.n 800ada2 800ad84: 687b ldr r3, [r7, #4] 800ad86: 681b ldr r3, [r3, #0] 800ad88: 4a30 ldr r2, [pc, #192] @ (800ae4c ) 800ad8a: 4293 cmp r3, r2 800ad8c: d009 beq.n 800ada2 800ad8e: 687b ldr r3, [r7, #4] 800ad90: 681b ldr r3, [r3, #0] 800ad92: 4a2f ldr r2, [pc, #188] @ (800ae50 ) 800ad94: 4293 cmp r3, r2 800ad96: d004 beq.n 800ada2 800ad98: 687b ldr r3, [r7, #4] 800ad9a: 681b ldr r3, [r3, #0] 800ad9c: 4a2d ldr r2, [pc, #180] @ (800ae54 ) 800ad9e: 4293 cmp r3, r2 800ada0: d101 bne.n 800ada6 800ada2: 2301 movs r3, #1 800ada4: e000 b.n 800ada8 800ada6: 2300 movs r3, #0 800ada8: 2b00 cmp r3, #0 800adaa: d01a beq.n 800ade2 { /* BDMA Channels are connected to DMAMUX2 channels */ stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; 800adac: 687b ldr r3, [r7, #4] 800adae: 681b ldr r3, [r3, #0] 800adb0: b2db uxtb r3, r3 800adb2: 3b08 subs r3, #8 800adb4: 4a28 ldr r2, [pc, #160] @ (800ae58 ) 800adb6: fba2 2303 umull r2, r3, r2, r3 800adba: 091b lsrs r3, r3, #4 800adbc: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); 800adbe: 68fa ldr r2, [r7, #12] 800adc0: 4b26 ldr r3, [pc, #152] @ (800ae5c ) 800adc2: 4413 add r3, r2 800adc4: 009b lsls r3, r3, #2 800adc6: 461a mov r2, r3 800adc8: 687b ldr r3, [r7, #4] 800adca: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; 800adcc: 687b ldr r3, [r7, #4] 800adce: 4a24 ldr r2, [pc, #144] @ (800ae60 ) 800add0: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800add2: 68fb ldr r3, [r7, #12] 800add4: f003 031f and.w r3, r3, #31 800add8: 2201 movs r2, #1 800adda: 409a lsls r2, r3 800addc: 687b ldr r3, [r7, #4] 800adde: 669a str r2, [r3, #104] @ 0x68 } hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); } } 800ade0: e024 b.n 800ae2c stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800ade2: 687b ldr r3, [r7, #4] 800ade4: 681b ldr r3, [r3, #0] 800ade6: b2db uxtb r3, r3 800ade8: 3b10 subs r3, #16 800adea: 4a1e ldr r2, [pc, #120] @ (800ae64 ) 800adec: fba2 2303 umull r2, r3, r2, r3 800adf0: 091b lsrs r3, r3, #4 800adf2: 60fb str r3, [r7, #12] if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ 800adf4: 68bb ldr r3, [r7, #8] 800adf6: 4a1c ldr r2, [pc, #112] @ (800ae68 ) 800adf8: 4293 cmp r3, r2 800adfa: d806 bhi.n 800ae0a 800adfc: 68bb ldr r3, [r7, #8] 800adfe: 4a1b ldr r2, [pc, #108] @ (800ae6c ) 800ae00: 4293 cmp r3, r2 800ae02: d902 bls.n 800ae0a stream_number += 8U; 800ae04: 68fb ldr r3, [r7, #12] 800ae06: 3308 adds r3, #8 800ae08: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); 800ae0a: 68fa ldr r2, [r7, #12] 800ae0c: 4b18 ldr r3, [pc, #96] @ (800ae70 ) 800ae0e: 4413 add r3, r2 800ae10: 009b lsls r3, r3, #2 800ae12: 461a mov r2, r3 800ae14: 687b ldr r3, [r7, #4] 800ae16: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 800ae18: 687b ldr r3, [r7, #4] 800ae1a: 4a16 ldr r2, [pc, #88] @ (800ae74 ) 800ae1c: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800ae1e: 68fb ldr r3, [r7, #12] 800ae20: f003 031f and.w r3, r3, #31 800ae24: 2201 movs r2, #1 800ae26: 409a lsls r2, r3 800ae28: 687b ldr r3, [r7, #4] 800ae2a: 669a str r2, [r3, #104] @ 0x68 } 800ae2c: bf00 nop 800ae2e: 3714 adds r7, #20 800ae30: 46bd mov sp, r7 800ae32: f85d 7b04 ldr.w r7, [sp], #4 800ae36: 4770 bx lr 800ae38: 58025408 .word 0x58025408 800ae3c: 5802541c .word 0x5802541c 800ae40: 58025430 .word 0x58025430 800ae44: 58025444 .word 0x58025444 800ae48: 58025458 .word 0x58025458 800ae4c: 5802546c .word 0x5802546c 800ae50: 58025480 .word 0x58025480 800ae54: 58025494 .word 0x58025494 800ae58: cccccccd .word 0xcccccccd 800ae5c: 16009600 .word 0x16009600 800ae60: 58025880 .word 0x58025880 800ae64: aaaaaaab .word 0xaaaaaaab 800ae68: 400204b8 .word 0x400204b8 800ae6c: 4002040f .word 0x4002040f 800ae70: 10008200 .word 0x10008200 800ae74: 40020880 .word 0x40020880 0800ae78 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 800ae78: b480 push {r7} 800ae7a: b085 sub sp, #20 800ae7c: af00 add r7, sp, #0 800ae7e: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 800ae80: 687b ldr r3, [r7, #4] 800ae82: 685b ldr r3, [r3, #4] 800ae84: b2db uxtb r3, r3 800ae86: 60fb str r3, [r7, #12] if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) 800ae88: 68fb ldr r3, [r7, #12] 800ae8a: 2b00 cmp r3, #0 800ae8c: d04a beq.n 800af24 800ae8e: 68fb ldr r3, [r7, #12] 800ae90: 2b08 cmp r3, #8 800ae92: d847 bhi.n 800af24 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 800ae94: 687b ldr r3, [r7, #4] 800ae96: 681b ldr r3, [r3, #0] 800ae98: 4a25 ldr r2, [pc, #148] @ (800af30 ) 800ae9a: 4293 cmp r3, r2 800ae9c: d022 beq.n 800aee4 800ae9e: 687b ldr r3, [r7, #4] 800aea0: 681b ldr r3, [r3, #0] 800aea2: 4a24 ldr r2, [pc, #144] @ (800af34 ) 800aea4: 4293 cmp r3, r2 800aea6: d01d beq.n 800aee4 800aea8: 687b ldr r3, [r7, #4] 800aeaa: 681b ldr r3, [r3, #0] 800aeac: 4a22 ldr r2, [pc, #136] @ (800af38 ) 800aeae: 4293 cmp r3, r2 800aeb0: d018 beq.n 800aee4 800aeb2: 687b ldr r3, [r7, #4] 800aeb4: 681b ldr r3, [r3, #0] 800aeb6: 4a21 ldr r2, [pc, #132] @ (800af3c ) 800aeb8: 4293 cmp r3, r2 800aeba: d013 beq.n 800aee4 800aebc: 687b ldr r3, [r7, #4] 800aebe: 681b ldr r3, [r3, #0] 800aec0: 4a1f ldr r2, [pc, #124] @ (800af40 ) 800aec2: 4293 cmp r3, r2 800aec4: d00e beq.n 800aee4 800aec6: 687b ldr r3, [r7, #4] 800aec8: 681b ldr r3, [r3, #0] 800aeca: 4a1e ldr r2, [pc, #120] @ (800af44 ) 800aecc: 4293 cmp r3, r2 800aece: d009 beq.n 800aee4 800aed0: 687b ldr r3, [r7, #4] 800aed2: 681b ldr r3, [r3, #0] 800aed4: 4a1c ldr r2, [pc, #112] @ (800af48 ) 800aed6: 4293 cmp r3, r2 800aed8: d004 beq.n 800aee4 800aeda: 687b ldr r3, [r7, #4] 800aedc: 681b ldr r3, [r3, #0] 800aede: 4a1b ldr r2, [pc, #108] @ (800af4c ) 800aee0: 4293 cmp r3, r2 800aee2: d101 bne.n 800aee8 800aee4: 2301 movs r3, #1 800aee6: e000 b.n 800aeea 800aee8: 2300 movs r3, #0 800aeea: 2b00 cmp r3, #0 800aeec: d00a beq.n 800af04 { /* BDMA Channels are connected to DMAMUX2 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); 800aeee: 68fa ldr r2, [r7, #12] 800aef0: 4b17 ldr r3, [pc, #92] @ (800af50 ) 800aef2: 4413 add r3, r2 800aef4: 009b lsls r3, r3, #2 800aef6: 461a mov r2, r3 800aef8: 687b ldr r3, [r7, #4] 800aefa: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; 800aefc: 687b ldr r3, [r7, #4] 800aefe: 4a15 ldr r2, [pc, #84] @ (800af54 ) 800af00: 671a str r2, [r3, #112] @ 0x70 800af02: e009 b.n 800af18 } else { /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 800af04: 68fa ldr r2, [r7, #12] 800af06: 4b14 ldr r3, [pc, #80] @ (800af58 ) 800af08: 4413 add r3, r2 800af0a: 009b lsls r3, r3, #2 800af0c: 461a mov r2, r3 800af0e: 687b ldr r3, [r7, #4] 800af10: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 800af12: 687b ldr r3, [r7, #4] 800af14: 4a11 ldr r2, [pc, #68] @ (800af5c ) 800af16: 671a str r2, [r3, #112] @ 0x70 } hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); 800af18: 68fb ldr r3, [r7, #12] 800af1a: 3b01 subs r3, #1 800af1c: 2201 movs r2, #1 800af1e: 409a lsls r2, r3 800af20: 687b ldr r3, [r7, #4] 800af22: 675a str r2, [r3, #116] @ 0x74 } } 800af24: bf00 nop 800af26: 3714 adds r7, #20 800af28: 46bd mov sp, r7 800af2a: f85d 7b04 ldr.w r7, [sp], #4 800af2e: 4770 bx lr 800af30: 58025408 .word 0x58025408 800af34: 5802541c .word 0x5802541c 800af38: 58025430 .word 0x58025430 800af3c: 58025444 .word 0x58025444 800af40: 58025458 .word 0x58025458 800af44: 5802546c .word 0x5802546c 800af48: 58025480 .word 0x58025480 800af4c: 58025494 .word 0x58025494 800af50: 1600963f .word 0x1600963f 800af54: 58025940 .word 0x58025940 800af58: 1000823f .word 0x1000823f 800af5c: 40020940 .word 0x40020940 0800af60 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800af60: b480 push {r7} 800af62: b089 sub sp, #36 @ 0x24 800af64: af00 add r7, sp, #0 800af66: 6078 str r0, [r7, #4] 800af68: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 800af6a: 2300 movs r3, #0 800af6c: 61fb str r3, [r7, #28] EXTI_Core_TypeDef *EXTI_CurrentCPU; #if defined(DUAL_CORE) && defined(CORE_CM4) EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ #else EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ 800af6e: 4b89 ldr r3, [pc, #548] @ (800b194 ) 800af70: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 800af72: e194 b.n 800b29e { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 800af74: 683b ldr r3, [r7, #0] 800af76: 681a ldr r2, [r3, #0] 800af78: 2101 movs r1, #1 800af7a: 69fb ldr r3, [r7, #28] 800af7c: fa01 f303 lsl.w r3, r1, r3 800af80: 4013 ands r3, r2 800af82: 613b str r3, [r7, #16] if (iocurrent != 0x00U) 800af84: 693b ldr r3, [r7, #16] 800af86: 2b00 cmp r3, #0 800af88: f000 8186 beq.w 800b298 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 800af8c: 683b ldr r3, [r7, #0] 800af8e: 685b ldr r3, [r3, #4] 800af90: f003 0303 and.w r3, r3, #3 800af94: 2b01 cmp r3, #1 800af96: d005 beq.n 800afa4 800af98: 683b ldr r3, [r7, #0] 800af9a: 685b ldr r3, [r3, #4] 800af9c: f003 0303 and.w r3, r3, #3 800afa0: 2b02 cmp r3, #2 800afa2: d130 bne.n 800b006 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 800afa4: 687b ldr r3, [r7, #4] 800afa6: 689b ldr r3, [r3, #8] 800afa8: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 800afaa: 69fb ldr r3, [r7, #28] 800afac: 005b lsls r3, r3, #1 800afae: 2203 movs r2, #3 800afb0: fa02 f303 lsl.w r3, r2, r3 800afb4: 43db mvns r3, r3 800afb6: 69ba ldr r2, [r7, #24] 800afb8: 4013 ands r3, r2 800afba: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 800afbc: 683b ldr r3, [r7, #0] 800afbe: 68da ldr r2, [r3, #12] 800afc0: 69fb ldr r3, [r7, #28] 800afc2: 005b lsls r3, r3, #1 800afc4: fa02 f303 lsl.w r3, r2, r3 800afc8: 69ba ldr r2, [r7, #24] 800afca: 4313 orrs r3, r2 800afcc: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 800afce: 687b ldr r3, [r7, #4] 800afd0: 69ba ldr r2, [r7, #24] 800afd2: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 800afd4: 687b ldr r3, [r7, #4] 800afd6: 685b ldr r3, [r3, #4] 800afd8: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT0 << position) ; 800afda: 2201 movs r2, #1 800afdc: 69fb ldr r3, [r7, #28] 800afde: fa02 f303 lsl.w r3, r2, r3 800afe2: 43db mvns r3, r3 800afe4: 69ba ldr r2, [r7, #24] 800afe6: 4013 ands r3, r2 800afe8: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 800afea: 683b ldr r3, [r7, #0] 800afec: 685b ldr r3, [r3, #4] 800afee: 091b lsrs r3, r3, #4 800aff0: f003 0201 and.w r2, r3, #1 800aff4: 69fb ldr r3, [r7, #28] 800aff6: fa02 f303 lsl.w r3, r2, r3 800affa: 69ba ldr r2, [r7, #24] 800affc: 4313 orrs r3, r2 800affe: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 800b000: 687b ldr r3, [r7, #4] 800b002: 69ba ldr r2, [r7, #24] 800b004: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 800b006: 683b ldr r3, [r7, #0] 800b008: 685b ldr r3, [r3, #4] 800b00a: f003 0303 and.w r3, r3, #3 800b00e: 2b03 cmp r3, #3 800b010: d017 beq.n 800b042 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 800b012: 687b ldr r3, [r7, #4] 800b014: 68db ldr r3, [r3, #12] 800b016: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 800b018: 69fb ldr r3, [r7, #28] 800b01a: 005b lsls r3, r3, #1 800b01c: 2203 movs r2, #3 800b01e: fa02 f303 lsl.w r3, r2, r3 800b022: 43db mvns r3, r3 800b024: 69ba ldr r2, [r7, #24] 800b026: 4013 ands r3, r2 800b028: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 800b02a: 683b ldr r3, [r7, #0] 800b02c: 689a ldr r2, [r3, #8] 800b02e: 69fb ldr r3, [r7, #28] 800b030: 005b lsls r3, r3, #1 800b032: fa02 f303 lsl.w r3, r2, r3 800b036: 69ba ldr r2, [r7, #24] 800b038: 4313 orrs r3, r2 800b03a: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 800b03c: 687b ldr r3, [r7, #4] 800b03e: 69ba ldr r2, [r7, #24] 800b040: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 800b042: 683b ldr r3, [r7, #0] 800b044: 685b ldr r3, [r3, #4] 800b046: f003 0303 and.w r3, r3, #3 800b04a: 2b02 cmp r3, #2 800b04c: d123 bne.n 800b096 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 800b04e: 69fb ldr r3, [r7, #28] 800b050: 08da lsrs r2, r3, #3 800b052: 687b ldr r3, [r7, #4] 800b054: 3208 adds r2, #8 800b056: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800b05a: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 800b05c: 69fb ldr r3, [r7, #28] 800b05e: f003 0307 and.w r3, r3, #7 800b062: 009b lsls r3, r3, #2 800b064: 220f movs r2, #15 800b066: fa02 f303 lsl.w r3, r2, r3 800b06a: 43db mvns r3, r3 800b06c: 69ba ldr r2, [r7, #24] 800b06e: 4013 ands r3, r2 800b070: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 800b072: 683b ldr r3, [r7, #0] 800b074: 691a ldr r2, [r3, #16] 800b076: 69fb ldr r3, [r7, #28] 800b078: f003 0307 and.w r3, r3, #7 800b07c: 009b lsls r3, r3, #2 800b07e: fa02 f303 lsl.w r3, r2, r3 800b082: 69ba ldr r2, [r7, #24] 800b084: 4313 orrs r3, r2 800b086: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 800b088: 69fb ldr r3, [r7, #28] 800b08a: 08da lsrs r2, r3, #3 800b08c: 687b ldr r3, [r7, #4] 800b08e: 3208 adds r2, #8 800b090: 69b9 ldr r1, [r7, #24] 800b092: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 800b096: 687b ldr r3, [r7, #4] 800b098: 681b ldr r3, [r3, #0] 800b09a: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 800b09c: 69fb ldr r3, [r7, #28] 800b09e: 005b lsls r3, r3, #1 800b0a0: 2203 movs r2, #3 800b0a2: fa02 f303 lsl.w r3, r2, r3 800b0a6: 43db mvns r3, r3 800b0a8: 69ba ldr r2, [r7, #24] 800b0aa: 4013 ands r3, r2 800b0ac: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 800b0ae: 683b ldr r3, [r7, #0] 800b0b0: 685b ldr r3, [r3, #4] 800b0b2: f003 0203 and.w r2, r3, #3 800b0b6: 69fb ldr r3, [r7, #28] 800b0b8: 005b lsls r3, r3, #1 800b0ba: fa02 f303 lsl.w r3, r2, r3 800b0be: 69ba ldr r2, [r7, #24] 800b0c0: 4313 orrs r3, r2 800b0c2: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 800b0c4: 687b ldr r3, [r7, #4] 800b0c6: 69ba ldr r2, [r7, #24] 800b0c8: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 800b0ca: 683b ldr r3, [r7, #0] 800b0cc: 685b ldr r3, [r3, #4] 800b0ce: f403 3340 and.w r3, r3, #196608 @ 0x30000 800b0d2: 2b00 cmp r3, #0 800b0d4: f000 80e0 beq.w 800b298 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800b0d8: 4b2f ldr r3, [pc, #188] @ (800b198 ) 800b0da: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 800b0de: 4a2e ldr r2, [pc, #184] @ (800b198 ) 800b0e0: f043 0302 orr.w r3, r3, #2 800b0e4: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 800b0e8: 4b2b ldr r3, [pc, #172] @ (800b198 ) 800b0ea: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 800b0ee: f003 0302 and.w r3, r3, #2 800b0f2: 60fb str r3, [r7, #12] 800b0f4: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 800b0f6: 4a29 ldr r2, [pc, #164] @ (800b19c ) 800b0f8: 69fb ldr r3, [r7, #28] 800b0fa: 089b lsrs r3, r3, #2 800b0fc: 3302 adds r3, #2 800b0fe: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800b102: 61bb str r3, [r7, #24] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 800b104: 69fb ldr r3, [r7, #28] 800b106: f003 0303 and.w r3, r3, #3 800b10a: 009b lsls r3, r3, #2 800b10c: 220f movs r2, #15 800b10e: fa02 f303 lsl.w r3, r2, r3 800b112: 43db mvns r3, r3 800b114: 69ba ldr r2, [r7, #24] 800b116: 4013 ands r3, r2 800b118: 61bb str r3, [r7, #24] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 800b11a: 687b ldr r3, [r7, #4] 800b11c: 4a20 ldr r2, [pc, #128] @ (800b1a0 ) 800b11e: 4293 cmp r3, r2 800b120: d052 beq.n 800b1c8 800b122: 687b ldr r3, [r7, #4] 800b124: 4a1f ldr r2, [pc, #124] @ (800b1a4 ) 800b126: 4293 cmp r3, r2 800b128: d031 beq.n 800b18e 800b12a: 687b ldr r3, [r7, #4] 800b12c: 4a1e ldr r2, [pc, #120] @ (800b1a8 ) 800b12e: 4293 cmp r3, r2 800b130: d02b beq.n 800b18a 800b132: 687b ldr r3, [r7, #4] 800b134: 4a1d ldr r2, [pc, #116] @ (800b1ac ) 800b136: 4293 cmp r3, r2 800b138: d025 beq.n 800b186 800b13a: 687b ldr r3, [r7, #4] 800b13c: 4a1c ldr r2, [pc, #112] @ (800b1b0 ) 800b13e: 4293 cmp r3, r2 800b140: d01f beq.n 800b182 800b142: 687b ldr r3, [r7, #4] 800b144: 4a1b ldr r2, [pc, #108] @ (800b1b4 ) 800b146: 4293 cmp r3, r2 800b148: d019 beq.n 800b17e 800b14a: 687b ldr r3, [r7, #4] 800b14c: 4a1a ldr r2, [pc, #104] @ (800b1b8 ) 800b14e: 4293 cmp r3, r2 800b150: d013 beq.n 800b17a 800b152: 687b ldr r3, [r7, #4] 800b154: 4a19 ldr r2, [pc, #100] @ (800b1bc ) 800b156: 4293 cmp r3, r2 800b158: d00d beq.n 800b176 800b15a: 687b ldr r3, [r7, #4] 800b15c: 4a18 ldr r2, [pc, #96] @ (800b1c0 ) 800b15e: 4293 cmp r3, r2 800b160: d007 beq.n 800b172 800b162: 687b ldr r3, [r7, #4] 800b164: 4a17 ldr r2, [pc, #92] @ (800b1c4 ) 800b166: 4293 cmp r3, r2 800b168: d101 bne.n 800b16e 800b16a: 2309 movs r3, #9 800b16c: e02d b.n 800b1ca 800b16e: 230a movs r3, #10 800b170: e02b b.n 800b1ca 800b172: 2308 movs r3, #8 800b174: e029 b.n 800b1ca 800b176: 2307 movs r3, #7 800b178: e027 b.n 800b1ca 800b17a: 2306 movs r3, #6 800b17c: e025 b.n 800b1ca 800b17e: 2305 movs r3, #5 800b180: e023 b.n 800b1ca 800b182: 2304 movs r3, #4 800b184: e021 b.n 800b1ca 800b186: 2303 movs r3, #3 800b188: e01f b.n 800b1ca 800b18a: 2302 movs r3, #2 800b18c: e01d b.n 800b1ca 800b18e: 2301 movs r3, #1 800b190: e01b b.n 800b1ca 800b192: bf00 nop 800b194: 58000080 .word 0x58000080 800b198: 58024400 .word 0x58024400 800b19c: 58000400 .word 0x58000400 800b1a0: 58020000 .word 0x58020000 800b1a4: 58020400 .word 0x58020400 800b1a8: 58020800 .word 0x58020800 800b1ac: 58020c00 .word 0x58020c00 800b1b0: 58021000 .word 0x58021000 800b1b4: 58021400 .word 0x58021400 800b1b8: 58021800 .word 0x58021800 800b1bc: 58021c00 .word 0x58021c00 800b1c0: 58022000 .word 0x58022000 800b1c4: 58022400 .word 0x58022400 800b1c8: 2300 movs r3, #0 800b1ca: 69fa ldr r2, [r7, #28] 800b1cc: f002 0203 and.w r2, r2, #3 800b1d0: 0092 lsls r2, r2, #2 800b1d2: 4093 lsls r3, r2 800b1d4: 69ba ldr r2, [r7, #24] 800b1d6: 4313 orrs r3, r2 800b1d8: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 800b1da: 4938 ldr r1, [pc, #224] @ (800b2bc ) 800b1dc: 69fb ldr r3, [r7, #28] 800b1de: 089b lsrs r3, r3, #2 800b1e0: 3302 adds r3, #2 800b1e2: 69ba ldr r2, [r7, #24] 800b1e4: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 800b1e8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b1ec: 681b ldr r3, [r3, #0] 800b1ee: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b1f0: 693b ldr r3, [r7, #16] 800b1f2: 43db mvns r3, r3 800b1f4: 69ba ldr r2, [r7, #24] 800b1f6: 4013 ands r3, r2 800b1f8: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 800b1fa: 683b ldr r3, [r7, #0] 800b1fc: 685b ldr r3, [r3, #4] 800b1fe: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800b202: 2b00 cmp r3, #0 800b204: d003 beq.n 800b20e { temp |= iocurrent; 800b206: 69ba ldr r2, [r7, #24] 800b208: 693b ldr r3, [r7, #16] 800b20a: 4313 orrs r3, r2 800b20c: 61bb str r3, [r7, #24] } EXTI->RTSR1 = temp; 800b20e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b212: 69bb ldr r3, [r7, #24] 800b214: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 800b216: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b21a: 685b ldr r3, [r3, #4] 800b21c: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b21e: 693b ldr r3, [r7, #16] 800b220: 43db mvns r3, r3 800b222: 69ba ldr r2, [r7, #24] 800b224: 4013 ands r3, r2 800b226: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 800b228: 683b ldr r3, [r7, #0] 800b22a: 685b ldr r3, [r3, #4] 800b22c: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800b230: 2b00 cmp r3, #0 800b232: d003 beq.n 800b23c { temp |= iocurrent; 800b234: 69ba ldr r2, [r7, #24] 800b236: 693b ldr r3, [r7, #16] 800b238: 4313 orrs r3, r2 800b23a: 61bb str r3, [r7, #24] } EXTI->FTSR1 = temp; 800b23c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b240: 69bb ldr r3, [r7, #24] 800b242: 6053 str r3, [r2, #4] temp = EXTI_CurrentCPU->EMR1; 800b244: 697b ldr r3, [r7, #20] 800b246: 685b ldr r3, [r3, #4] 800b248: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b24a: 693b ldr r3, [r7, #16] 800b24c: 43db mvns r3, r3 800b24e: 69ba ldr r2, [r7, #24] 800b250: 4013 ands r3, r2 800b252: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 800b254: 683b ldr r3, [r7, #0] 800b256: 685b ldr r3, [r3, #4] 800b258: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b25c: 2b00 cmp r3, #0 800b25e: d003 beq.n 800b268 { temp |= iocurrent; 800b260: 69ba ldr r2, [r7, #24] 800b262: 693b ldr r3, [r7, #16] 800b264: 4313 orrs r3, r2 800b266: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->EMR1 = temp; 800b268: 697b ldr r3, [r7, #20] 800b26a: 69ba ldr r2, [r7, #24] 800b26c: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 800b26e: 697b ldr r3, [r7, #20] 800b270: 681b ldr r3, [r3, #0] 800b272: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b274: 693b ldr r3, [r7, #16] 800b276: 43db mvns r3, r3 800b278: 69ba ldr r2, [r7, #24] 800b27a: 4013 ands r3, r2 800b27c: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 800b27e: 683b ldr r3, [r7, #0] 800b280: 685b ldr r3, [r3, #4] 800b282: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b286: 2b00 cmp r3, #0 800b288: d003 beq.n 800b292 { temp |= iocurrent; 800b28a: 69ba ldr r2, [r7, #24] 800b28c: 693b ldr r3, [r7, #16] 800b28e: 4313 orrs r3, r2 800b290: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->IMR1 = temp; 800b292: 697b ldr r3, [r7, #20] 800b294: 69ba ldr r2, [r7, #24] 800b296: 601a str r2, [r3, #0] } } position++; 800b298: 69fb ldr r3, [r7, #28] 800b29a: 3301 adds r3, #1 800b29c: 61fb str r3, [r7, #28] while (((GPIO_Init->Pin) >> position) != 0x00U) 800b29e: 683b ldr r3, [r7, #0] 800b2a0: 681a ldr r2, [r3, #0] 800b2a2: 69fb ldr r3, [r7, #28] 800b2a4: fa22 f303 lsr.w r3, r2, r3 800b2a8: 2b00 cmp r3, #0 800b2aa: f47f ae63 bne.w 800af74 } } 800b2ae: bf00 nop 800b2b0: bf00 nop 800b2b2: 3724 adds r7, #36 @ 0x24 800b2b4: 46bd mov sp, r7 800b2b6: f85d 7b04 ldr.w r7, [sp], #4 800b2ba: 4770 bx lr 800b2bc: 58000400 .word 0x58000400 0800b2c0 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800b2c0: b480 push {r7} 800b2c2: b085 sub sp, #20 800b2c4: af00 add r7, sp, #0 800b2c6: 6078 str r0, [r7, #4] 800b2c8: 460b mov r3, r1 800b2ca: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0x00U) 800b2cc: 687b ldr r3, [r7, #4] 800b2ce: 691a ldr r2, [r3, #16] 800b2d0: 887b ldrh r3, [r7, #2] 800b2d2: 4013 ands r3, r2 800b2d4: 2b00 cmp r3, #0 800b2d6: d002 beq.n 800b2de { bitstatus = GPIO_PIN_SET; 800b2d8: 2301 movs r3, #1 800b2da: 73fb strb r3, [r7, #15] 800b2dc: e001 b.n 800b2e2 } else { bitstatus = GPIO_PIN_RESET; 800b2de: 2300 movs r3, #0 800b2e0: 73fb strb r3, [r7, #15] } return bitstatus; 800b2e2: 7bfb ldrb r3, [r7, #15] } 800b2e4: 4618 mov r0, r3 800b2e6: 3714 adds r7, #20 800b2e8: 46bd mov sp, r7 800b2ea: f85d 7b04 ldr.w r7, [sp], #4 800b2ee: 4770 bx lr 0800b2f0 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800b2f0: b480 push {r7} 800b2f2: b083 sub sp, #12 800b2f4: af00 add r7, sp, #0 800b2f6: 6078 str r0, [r7, #4] 800b2f8: 460b mov r3, r1 800b2fa: 807b strh r3, [r7, #2] 800b2fc: 4613 mov r3, r2 800b2fe: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800b300: 787b ldrb r3, [r7, #1] 800b302: 2b00 cmp r3, #0 800b304: d003 beq.n 800b30e { GPIOx->BSRR = GPIO_Pin; 800b306: 887a ldrh r2, [r7, #2] 800b308: 687b ldr r3, [r7, #4] 800b30a: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; } } 800b30c: e003 b.n 800b316 GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 800b30e: 887b ldrh r3, [r7, #2] 800b310: 041a lsls r2, r3, #16 800b312: 687b ldr r3, [r7, #4] 800b314: 619a str r2, [r3, #24] } 800b316: bf00 nop 800b318: 370c adds r7, #12 800b31a: 46bd mov sp, r7 800b31c: f85d 7b04 ldr.w r7, [sp], #4 800b320: 4770 bx lr 0800b322 : * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral. * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800b322: b480 push {r7} 800b324: b085 sub sp, #20 800b326: af00 add r7, sp, #0 800b328: 6078 str r0, [r7, #4] 800b32a: 460b mov r3, r1 800b32c: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; 800b32e: 687b ldr r3, [r7, #4] 800b330: 695b ldr r3, [r3, #20] 800b332: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 800b334: 887a ldrh r2, [r7, #2] 800b336: 68fb ldr r3, [r7, #12] 800b338: 4013 ands r3, r2 800b33a: 041a lsls r2, r3, #16 800b33c: 68fb ldr r3, [r7, #12] 800b33e: 43d9 mvns r1, r3 800b340: 887b ldrh r3, [r7, #2] 800b342: 400b ands r3, r1 800b344: 431a orrs r2, r3 800b346: 687b ldr r3, [r7, #4] 800b348: 619a str r2, [r3, #24] } 800b34a: bf00 nop 800b34c: 3714 adds r7, #20 800b34e: 46bd mov sp, r7 800b350: f85d 7b04 ldr.w r7, [sp], #4 800b354: 4770 bx lr 0800b356 : * @brief Handle EXTI interrupt request. * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 800b356: b580 push {r7, lr} 800b358: b082 sub sp, #8 800b35a: af00 add r7, sp, #0 800b35c: 4603 mov r3, r0 800b35e: 80fb strh r3, [r7, #6] __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); } #else /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U) 800b360: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b364: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 800b368: 88fb ldrh r3, [r7, #6] 800b36a: 4013 ands r3, r2 800b36c: 2b00 cmp r3, #0 800b36e: d008 beq.n 800b382 { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 800b370: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b374: 88fb ldrh r3, [r7, #6] 800b376: f8c2 3088 str.w r3, [r2, #136] @ 0x88 HAL_GPIO_EXTI_Callback(GPIO_Pin); 800b37a: 88fb ldrh r3, [r7, #6] 800b37c: 4618 mov r0, r3 800b37e: f7f5 f9cd bl 800071c } #endif } 800b382: bf00 nop 800b384: 3708 adds r7, #8 800b386: 46bd mov sp, r7 800b388: bd80 pop {r7, pc} ... 0800b38c : * driver. All combination are allowed: wake up only Cortex-M7, wake up * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4. * @retval None. */ void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD) { 800b38c: b480 push {r7} 800b38e: b083 sub sp, #12 800b390: af00 add r7, sp, #0 800b392: 6078 str r0, [r7, #4] /* Check the PVD configuration parameter */ if (sConfigPVD == NULL) 800b394: 687b ldr r3, [r7, #4] 800b396: 2b00 cmp r3, #0 800b398: d069 beq.n 800b46e /* Check the parameters */ assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel)); assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode)); /* Set PLS[7:5] bits according to PVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); 800b39a: 4b38 ldr r3, [pc, #224] @ (800b47c ) 800b39c: 681b ldr r3, [r3, #0] 800b39e: f023 02e0 bic.w r2, r3, #224 @ 0xe0 800b3a2: 687b ldr r3, [r7, #4] 800b3a4: 681b ldr r3, [r3, #0] 800b3a6: 4935 ldr r1, [pc, #212] @ (800b47c ) 800b3a8: 4313 orrs r3, r2 800b3aa: 600b str r3, [r1, #0] /* Clear previous config */ #if !defined (DUAL_CORE) __HAL_PWR_PVD_EXTI_DISABLE_EVENT (); 800b3ac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b3b0: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b3b4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b3b8: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b3bc: f8c2 3084 str.w r3, [r2, #132] @ 0x84 __HAL_PWR_PVD_EXTI_DISABLE_IT (); 800b3c0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b3c4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b3c8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b3cc: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b3d0: f8c2 3080 str.w r3, [r2, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE (); 800b3d4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b3d8: 681b ldr r3, [r3, #0] 800b3da: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b3de: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b3e2: 6013 str r3, [r2, #0] __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE (); 800b3e4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b3e8: 685b ldr r3, [r3, #4] 800b3ea: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b3ee: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b3f2: 6053 str r3, [r2, #4] #if !defined (DUAL_CORE) /* Interrupt mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 800b3f4: 687b ldr r3, [r7, #4] 800b3f6: 685b ldr r3, [r3, #4] 800b3f8: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b3fc: 2b00 cmp r3, #0 800b3fe: d009 beq.n 800b414 { __HAL_PWR_PVD_EXTI_ENABLE_IT (); 800b400: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b404: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b408: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b40c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b410: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } /* Event mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 800b414: 687b ldr r3, [r7, #4] 800b416: 685b ldr r3, [r3, #4] 800b418: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b41c: 2b00 cmp r3, #0 800b41e: d009 beq.n 800b434 { __HAL_PWR_PVD_EXTI_ENABLE_EVENT (); 800b420: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b424: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b428: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b42c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b430: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 800b434: 687b ldr r3, [r7, #4] 800b436: 685b ldr r3, [r3, #4] 800b438: f003 0301 and.w r3, r3, #1 800b43c: 2b00 cmp r3, #0 800b43e: d007 beq.n 800b450 { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE (); 800b440: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b444: 681b ldr r3, [r3, #0] 800b446: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b44a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b44e: 6013 str r3, [r2, #0] } /* Falling edge configuration */ if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 800b450: 687b ldr r3, [r7, #4] 800b452: 685b ldr r3, [r3, #4] 800b454: f003 0302 and.w r3, r3, #2 800b458: 2b00 cmp r3, #0 800b45a: d009 beq.n 800b470 { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE (); 800b45c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b460: 685b ldr r3, [r3, #4] 800b462: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b466: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b46a: 6053 str r3, [r2, #4] 800b46c: e000 b.n 800b470 return; 800b46e: bf00 nop } } 800b470: 370c adds r7, #12 800b472: 46bd mov sp, r7 800b474: f85d 7b04 ldr.w r7, [sp], #4 800b478: 4770 bx lr 800b47a: bf00 nop 800b47c: 58024800 .word 0x58024800 0800b480 : /** * @brief Enable the Programmable Voltage Detector (PVD). * @retval None. */ void HAL_PWR_EnablePVD (void) { 800b480: b480 push {r7} 800b482: af00 add r7, sp, #0 /* Enable the power voltage detector */ SET_BIT (PWR->CR1, PWR_CR1_PVDEN); 800b484: 4b05 ldr r3, [pc, #20] @ (800b49c ) 800b486: 681b ldr r3, [r3, #0] 800b488: 4a04 ldr r2, [pc, #16] @ (800b49c ) 800b48a: f043 0310 orr.w r3, r3, #16 800b48e: 6013 str r3, [r2, #0] } 800b490: bf00 nop 800b492: 46bd mov sp, r7 800b494: f85d 7b04 ldr.w r7, [sp], #4 800b498: 4770 bx lr 800b49a: bf00 nop 800b49c: 58024800 .word 0x58024800 0800b4a0 : * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { 800b4a0: b580 push {r7, lr} 800b4a2: b084 sub sp, #16 800b4a4: af00 add r7, sp, #0 800b4a6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_SUPPLY (SupplySource)); /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) 800b4a8: 4b19 ldr r3, [pc, #100] @ (800b510 ) 800b4aa: 68db ldr r3, [r3, #12] 800b4ac: f003 0304 and.w r3, r3, #4 800b4b0: 2b04 cmp r3, #4 800b4b2: d00a beq.n 800b4ca #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 800b4b4: 4b16 ldr r3, [pc, #88] @ (800b510 ) 800b4b6: 68db ldr r3, [r3, #12] 800b4b8: f003 0307 and.w r3, r3, #7 800b4bc: 687a ldr r2, [r7, #4] 800b4be: 429a cmp r2, r3 800b4c0: d001 beq.n 800b4c6 { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 800b4c2: 2301 movs r3, #1 800b4c4: e01f b.n 800b506 else { /* Supply configuration update locked, but new supply configuration matches with old supply configuration : nothing to do */ return HAL_OK; 800b4c6: 2300 movs r3, #0 800b4c8: e01d b.n 800b506 } } /* Set the power supply configuration */ MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 800b4ca: 4b11 ldr r3, [pc, #68] @ (800b510 ) 800b4cc: 68db ldr r3, [r3, #12] 800b4ce: f023 0207 bic.w r2, r3, #7 800b4d2: 490f ldr r1, [pc, #60] @ (800b510 ) 800b4d4: 687b ldr r3, [r7, #4] 800b4d6: 4313 orrs r3, r2 800b4d8: 60cb str r3, [r1, #12] /* Get tick */ tickstart = HAL_GetTick (); 800b4da: f7fa fb69 bl 8005bb0 800b4de: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800b4e0: e009 b.n 800b4f6 { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 800b4e2: f7fa fb65 bl 8005bb0 800b4e6: 4602 mov r2, r0 800b4e8: 68fb ldr r3, [r7, #12] 800b4ea: 1ad3 subs r3, r2, r3 800b4ec: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b4f0: d901 bls.n 800b4f6 { return HAL_ERROR; 800b4f2: 2301 movs r3, #1 800b4f4: e007 b.n 800b506 while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800b4f6: 4b06 ldr r3, [pc, #24] @ (800b510 ) 800b4f8: 685b ldr r3, [r3, #4] 800b4fa: f403 5300 and.w r3, r3, #8192 @ 0x2000 800b4fe: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800b502: d1ee bne.n 800b4e2 } } } #endif /* defined (SMPS) */ return HAL_OK; 800b504: 2300 movs r3, #0 } 800b506: 4618 mov r0, r3 800b508: 3710 adds r7, #16 800b50a: 46bd mov sp, r7 800b50c: bd80 pop {r7, pc} 800b50e: bf00 nop 800b510: 58024800 .word 0x58024800 0800b514 : * driver. All combination are allowed: wake up only Cortex-M7, wake up * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4. * @retval None. */ void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD) { 800b514: b480 push {r7} 800b516: b083 sub sp, #12 800b518: af00 add r7, sp, #0 800b51a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode)); /* Set the ALS[18:17] bits according to AVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); 800b51c: 4b37 ldr r3, [pc, #220] @ (800b5fc ) 800b51e: 681b ldr r3, [r3, #0] 800b520: f423 22c0 bic.w r2, r3, #393216 @ 0x60000 800b524: 687b ldr r3, [r7, #4] 800b526: 681b ldr r3, [r3, #0] 800b528: 4934 ldr r1, [pc, #208] @ (800b5fc ) 800b52a: 4313 orrs r3, r2 800b52c: 600b str r3, [r1, #0] /* Clear any previous config */ #if !defined (DUAL_CORE) __HAL_PWR_AVD_EXTI_DISABLE_EVENT (); 800b52e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b532: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b536: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b53a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b53e: f8c2 3084 str.w r3, [r2, #132] @ 0x84 __HAL_PWR_AVD_EXTI_DISABLE_IT (); 800b542: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b546: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b54a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b54e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b552: f8c2 3080 str.w r3, [r2, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE (); 800b556: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b55a: 681b ldr r3, [r3, #0] 800b55c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b560: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b564: 6013 str r3, [r2, #0] __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE (); 800b566: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b56a: 685b ldr r3, [r3, #4] 800b56c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b570: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b574: 6053 str r3, [r2, #4] #if !defined (DUAL_CORE) /* Configure the interrupt mode */ if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT) 800b576: 687b ldr r3, [r7, #4] 800b578: 685b ldr r3, [r3, #4] 800b57a: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b57e: 2b00 cmp r3, #0 800b580: d009 beq.n 800b596 { __HAL_PWR_AVD_EXTI_ENABLE_IT (); 800b582: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b586: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b58a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b58e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b592: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } /* Configure the event mode */ if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT) 800b596: 687b ldr r3, [r7, #4] 800b598: 685b ldr r3, [r3, #4] 800b59a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b59e: 2b00 cmp r3, #0 800b5a0: d009 beq.n 800b5b6 { __HAL_PWR_AVD_EXTI_ENABLE_EVENT (); 800b5a2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b5a6: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b5aa: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b5ae: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b5b2: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE) 800b5b6: 687b ldr r3, [r7, #4] 800b5b8: 685b ldr r3, [r3, #4] 800b5ba: f003 0301 and.w r3, r3, #1 800b5be: 2b00 cmp r3, #0 800b5c0: d007 beq.n 800b5d2 { __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE (); 800b5c2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b5c6: 681b ldr r3, [r3, #0] 800b5c8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b5cc: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b5d0: 6013 str r3, [r2, #0] } /* Falling edge configuration */ if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE) 800b5d2: 687b ldr r3, [r7, #4] 800b5d4: 685b ldr r3, [r3, #4] 800b5d6: f003 0302 and.w r3, r3, #2 800b5da: 2b00 cmp r3, #0 800b5dc: d007 beq.n 800b5ee { __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE (); 800b5de: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b5e2: 685b ldr r3, [r3, #4] 800b5e4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b5e8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b5ec: 6053 str r3, [r2, #4] } } 800b5ee: bf00 nop 800b5f0: 370c adds r7, #12 800b5f2: 46bd mov sp, r7 800b5f4: f85d 7b04 ldr.w r7, [sp], #4 800b5f8: 4770 bx lr 800b5fa: bf00 nop 800b5fc: 58024800 .word 0x58024800 0800b600 : /** * @brief Enable the Analog Voltage Detector (AVD). * @retval None. */ void HAL_PWREx_EnableAVD (void) { 800b600: b480 push {r7} 800b602: af00 add r7, sp, #0 /* Enable the Analog Voltage Detector */ SET_BIT (PWR->CR1, PWR_CR1_AVDEN); 800b604: 4b05 ldr r3, [pc, #20] @ (800b61c ) 800b606: 681b ldr r3, [r3, #0] 800b608: 4a04 ldr r2, [pc, #16] @ (800b61c ) 800b60a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b60e: 6013 str r3, [r2, #0] } 800b610: bf00 nop 800b612: 46bd mov sp, r7 800b614: f85d 7b04 ldr.w r7, [sp], #4 800b618: 4770 bx lr 800b61a: bf00 nop 800b61c: 58024800 .word 0x58024800 0800b620 : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800b620: b580 push {r7, lr} 800b622: b08c sub sp, #48 @ 0x30 800b624: af00 add r7, sp, #0 800b626: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 800b628: 687b ldr r3, [r7, #4] 800b62a: 2b00 cmp r3, #0 800b62c: d102 bne.n 800b634 { return HAL_ERROR; 800b62e: 2301 movs r3, #1 800b630: f000 bc48 b.w 800bec4 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800b634: 687b ldr r3, [r7, #4] 800b636: 681b ldr r3, [r3, #0] 800b638: f003 0301 and.w r3, r3, #1 800b63c: 2b00 cmp r3, #0 800b63e: f000 8088 beq.w 800b752 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b642: 4b99 ldr r3, [pc, #612] @ (800b8a8 ) 800b644: 691b ldr r3, [r3, #16] 800b646: f003 0338 and.w r3, r3, #56 @ 0x38 800b64a: 62fb str r3, [r7, #44] @ 0x2c const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800b64c: 4b96 ldr r3, [pc, #600] @ (800b8a8 ) 800b64e: 6a9b ldr r3, [r3, #40] @ 0x28 800b650: 62bb str r3, [r7, #40] @ 0x28 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 800b652: 6afb ldr r3, [r7, #44] @ 0x2c 800b654: 2b10 cmp r3, #16 800b656: d007 beq.n 800b668 800b658: 6afb ldr r3, [r7, #44] @ 0x2c 800b65a: 2b18 cmp r3, #24 800b65c: d111 bne.n 800b682 800b65e: 6abb ldr r3, [r7, #40] @ 0x28 800b660: f003 0303 and.w r3, r3, #3 800b664: 2b02 cmp r3, #2 800b666: d10c bne.n 800b682 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800b668: 4b8f ldr r3, [pc, #572] @ (800b8a8 ) 800b66a: 681b ldr r3, [r3, #0] 800b66c: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b670: 2b00 cmp r3, #0 800b672: d06d beq.n 800b750 800b674: 687b ldr r3, [r7, #4] 800b676: 685b ldr r3, [r3, #4] 800b678: 2b00 cmp r3, #0 800b67a: d169 bne.n 800b750 { return HAL_ERROR; 800b67c: 2301 movs r3, #1 800b67e: f000 bc21 b.w 800bec4 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800b682: 687b ldr r3, [r7, #4] 800b684: 685b ldr r3, [r3, #4] 800b686: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800b68a: d106 bne.n 800b69a 800b68c: 4b86 ldr r3, [pc, #536] @ (800b8a8 ) 800b68e: 681b ldr r3, [r3, #0] 800b690: 4a85 ldr r2, [pc, #532] @ (800b8a8 ) 800b692: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b696: 6013 str r3, [r2, #0] 800b698: e02e b.n 800b6f8 800b69a: 687b ldr r3, [r7, #4] 800b69c: 685b ldr r3, [r3, #4] 800b69e: 2b00 cmp r3, #0 800b6a0: d10c bne.n 800b6bc 800b6a2: 4b81 ldr r3, [pc, #516] @ (800b8a8 ) 800b6a4: 681b ldr r3, [r3, #0] 800b6a6: 4a80 ldr r2, [pc, #512] @ (800b8a8 ) 800b6a8: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b6ac: 6013 str r3, [r2, #0] 800b6ae: 4b7e ldr r3, [pc, #504] @ (800b8a8 ) 800b6b0: 681b ldr r3, [r3, #0] 800b6b2: 4a7d ldr r2, [pc, #500] @ (800b8a8 ) 800b6b4: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800b6b8: 6013 str r3, [r2, #0] 800b6ba: e01d b.n 800b6f8 800b6bc: 687b ldr r3, [r7, #4] 800b6be: 685b ldr r3, [r3, #4] 800b6c0: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800b6c4: d10c bne.n 800b6e0 800b6c6: 4b78 ldr r3, [pc, #480] @ (800b8a8 ) 800b6c8: 681b ldr r3, [r3, #0] 800b6ca: 4a77 ldr r2, [pc, #476] @ (800b8a8 ) 800b6cc: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800b6d0: 6013 str r3, [r2, #0] 800b6d2: 4b75 ldr r3, [pc, #468] @ (800b8a8 ) 800b6d4: 681b ldr r3, [r3, #0] 800b6d6: 4a74 ldr r2, [pc, #464] @ (800b8a8 ) 800b6d8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b6dc: 6013 str r3, [r2, #0] 800b6de: e00b b.n 800b6f8 800b6e0: 4b71 ldr r3, [pc, #452] @ (800b8a8 ) 800b6e2: 681b ldr r3, [r3, #0] 800b6e4: 4a70 ldr r2, [pc, #448] @ (800b8a8 ) 800b6e6: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b6ea: 6013 str r3, [r2, #0] 800b6ec: 4b6e ldr r3, [pc, #440] @ (800b8a8 ) 800b6ee: 681b ldr r3, [r3, #0] 800b6f0: 4a6d ldr r2, [pc, #436] @ (800b8a8 ) 800b6f2: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800b6f6: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 800b6f8: 687b ldr r3, [r7, #4] 800b6fa: 685b ldr r3, [r3, #4] 800b6fc: 2b00 cmp r3, #0 800b6fe: d013 beq.n 800b728 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b700: f7fa fa56 bl 8005bb0 800b704: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800b706: e008 b.n 800b71a { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800b708: f7fa fa52 bl 8005bb0 800b70c: 4602 mov r2, r0 800b70e: 6a7b ldr r3, [r7, #36] @ 0x24 800b710: 1ad3 subs r3, r2, r3 800b712: 2b64 cmp r3, #100 @ 0x64 800b714: d901 bls.n 800b71a { return HAL_TIMEOUT; 800b716: 2303 movs r3, #3 800b718: e3d4 b.n 800bec4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800b71a: 4b63 ldr r3, [pc, #396] @ (800b8a8 ) 800b71c: 681b ldr r3, [r3, #0] 800b71e: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b722: 2b00 cmp r3, #0 800b724: d0f0 beq.n 800b708 800b726: e014 b.n 800b752 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b728: f7fa fa42 bl 8005bb0 800b72c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800b72e: e008 b.n 800b742 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800b730: f7fa fa3e bl 8005bb0 800b734: 4602 mov r2, r0 800b736: 6a7b ldr r3, [r7, #36] @ 0x24 800b738: 1ad3 subs r3, r2, r3 800b73a: 2b64 cmp r3, #100 @ 0x64 800b73c: d901 bls.n 800b742 { return HAL_TIMEOUT; 800b73e: 2303 movs r3, #3 800b740: e3c0 b.n 800bec4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800b742: 4b59 ldr r3, [pc, #356] @ (800b8a8 ) 800b744: 681b ldr r3, [r3, #0] 800b746: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b74a: 2b00 cmp r3, #0 800b74c: d1f0 bne.n 800b730 800b74e: e000 b.n 800b752 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800b750: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800b752: 687b ldr r3, [r7, #4] 800b754: 681b ldr r3, [r3, #0] 800b756: f003 0302 and.w r3, r3, #2 800b75a: 2b00 cmp r3, #0 800b75c: f000 80ca beq.w 800b8f4 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b760: 4b51 ldr r3, [pc, #324] @ (800b8a8 ) 800b762: 691b ldr r3, [r3, #16] 800b764: f003 0338 and.w r3, r3, #56 @ 0x38 800b768: 623b str r3, [r7, #32] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800b76a: 4b4f ldr r3, [pc, #316] @ (800b8a8 ) 800b76c: 6a9b ldr r3, [r3, #40] @ 0x28 800b76e: 61fb str r3, [r7, #28] if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 800b770: 6a3b ldr r3, [r7, #32] 800b772: 2b00 cmp r3, #0 800b774: d007 beq.n 800b786 800b776: 6a3b ldr r3, [r7, #32] 800b778: 2b18 cmp r3, #24 800b77a: d156 bne.n 800b82a 800b77c: 69fb ldr r3, [r7, #28] 800b77e: f003 0303 and.w r3, r3, #3 800b782: 2b00 cmp r3, #0 800b784: d151 bne.n 800b82a { /* When HSI is used as system clock it will not be disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800b786: 4b48 ldr r3, [pc, #288] @ (800b8a8 ) 800b788: 681b ldr r3, [r3, #0] 800b78a: f003 0304 and.w r3, r3, #4 800b78e: 2b00 cmp r3, #0 800b790: d005 beq.n 800b79e 800b792: 687b ldr r3, [r7, #4] 800b794: 68db ldr r3, [r3, #12] 800b796: 2b00 cmp r3, #0 800b798: d101 bne.n 800b79e { return HAL_ERROR; 800b79a: 2301 movs r3, #1 800b79c: e392 b.n 800bec4 } /* Otherwise, only HSI division and calibration are allowed */ else { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800b79e: 4b42 ldr r3, [pc, #264] @ (800b8a8 ) 800b7a0: 681b ldr r3, [r3, #0] 800b7a2: f023 0219 bic.w r2, r3, #25 800b7a6: 687b ldr r3, [r7, #4] 800b7a8: 68db ldr r3, [r3, #12] 800b7aa: 493f ldr r1, [pc, #252] @ (800b8a8 ) 800b7ac: 4313 orrs r3, r2 800b7ae: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b7b0: f7fa f9fe bl 8005bb0 800b7b4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800b7b6: e008 b.n 800b7ca { if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800b7b8: f7fa f9fa bl 8005bb0 800b7bc: 4602 mov r2, r0 800b7be: 6a7b ldr r3, [r7, #36] @ 0x24 800b7c0: 1ad3 subs r3, r2, r3 800b7c2: 2b02 cmp r3, #2 800b7c4: d901 bls.n 800b7ca { return HAL_TIMEOUT; 800b7c6: 2303 movs r3, #3 800b7c8: e37c b.n 800bec4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800b7ca: 4b37 ldr r3, [pc, #220] @ (800b8a8 ) 800b7cc: 681b ldr r3, [r3, #0] 800b7ce: f003 0304 and.w r3, r3, #4 800b7d2: 2b00 cmp r3, #0 800b7d4: d0f0 beq.n 800b7b8 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800b7d6: f7fa f9f7 bl 8005bc8 800b7da: 4603 mov r3, r0 800b7dc: f241 0203 movw r2, #4099 @ 0x1003 800b7e0: 4293 cmp r3, r2 800b7e2: d817 bhi.n 800b814 800b7e4: 687b ldr r3, [r7, #4] 800b7e6: 691b ldr r3, [r3, #16] 800b7e8: 2b40 cmp r3, #64 @ 0x40 800b7ea: d108 bne.n 800b7fe 800b7ec: 4b2e ldr r3, [pc, #184] @ (800b8a8 ) 800b7ee: 685b ldr r3, [r3, #4] 800b7f0: f423 337c bic.w r3, r3, #258048 @ 0x3f000 800b7f4: 4a2c ldr r2, [pc, #176] @ (800b8a8 ) 800b7f6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800b7fa: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800b7fc: e07a b.n 800b8f4 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800b7fe: 4b2a ldr r3, [pc, #168] @ (800b8a8 ) 800b800: 685b ldr r3, [r3, #4] 800b802: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800b806: 687b ldr r3, [r7, #4] 800b808: 691b ldr r3, [r3, #16] 800b80a: 031b lsls r3, r3, #12 800b80c: 4926 ldr r1, [pc, #152] @ (800b8a8 ) 800b80e: 4313 orrs r3, r2 800b810: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800b812: e06f b.n 800b8f4 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800b814: 4b24 ldr r3, [pc, #144] @ (800b8a8 ) 800b816: 685b ldr r3, [r3, #4] 800b818: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800b81c: 687b ldr r3, [r7, #4] 800b81e: 691b ldr r3, [r3, #16] 800b820: 061b lsls r3, r3, #24 800b822: 4921 ldr r1, [pc, #132] @ (800b8a8 ) 800b824: 4313 orrs r3, r2 800b826: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800b828: e064 b.n 800b8f4 } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 800b82a: 687b ldr r3, [r7, #4] 800b82c: 68db ldr r3, [r3, #12] 800b82e: 2b00 cmp r3, #0 800b830: d047 beq.n 800b8c2 { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800b832: 4b1d ldr r3, [pc, #116] @ (800b8a8 ) 800b834: 681b ldr r3, [r3, #0] 800b836: f023 0219 bic.w r2, r3, #25 800b83a: 687b ldr r3, [r7, #4] 800b83c: 68db ldr r3, [r3, #12] 800b83e: 491a ldr r1, [pc, #104] @ (800b8a8 ) 800b840: 4313 orrs r3, r2 800b842: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b844: f7fa f9b4 bl 8005bb0 800b848: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800b84a: e008 b.n 800b85e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800b84c: f7fa f9b0 bl 8005bb0 800b850: 4602 mov r2, r0 800b852: 6a7b ldr r3, [r7, #36] @ 0x24 800b854: 1ad3 subs r3, r2, r3 800b856: 2b02 cmp r3, #2 800b858: d901 bls.n 800b85e { return HAL_TIMEOUT; 800b85a: 2303 movs r3, #3 800b85c: e332 b.n 800bec4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800b85e: 4b12 ldr r3, [pc, #72] @ (800b8a8 ) 800b860: 681b ldr r3, [r3, #0] 800b862: f003 0304 and.w r3, r3, #4 800b866: 2b00 cmp r3, #0 800b868: d0f0 beq.n 800b84c } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800b86a: f7fa f9ad bl 8005bc8 800b86e: 4603 mov r3, r0 800b870: f241 0203 movw r2, #4099 @ 0x1003 800b874: 4293 cmp r3, r2 800b876: d819 bhi.n 800b8ac 800b878: 687b ldr r3, [r7, #4] 800b87a: 691b ldr r3, [r3, #16] 800b87c: 2b40 cmp r3, #64 @ 0x40 800b87e: d108 bne.n 800b892 800b880: 4b09 ldr r3, [pc, #36] @ (800b8a8 ) 800b882: 685b ldr r3, [r3, #4] 800b884: f423 337c bic.w r3, r3, #258048 @ 0x3f000 800b888: 4a07 ldr r2, [pc, #28] @ (800b8a8 ) 800b88a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800b88e: 6053 str r3, [r2, #4] 800b890: e030 b.n 800b8f4 800b892: 4b05 ldr r3, [pc, #20] @ (800b8a8 ) 800b894: 685b ldr r3, [r3, #4] 800b896: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800b89a: 687b ldr r3, [r7, #4] 800b89c: 691b ldr r3, [r3, #16] 800b89e: 031b lsls r3, r3, #12 800b8a0: 4901 ldr r1, [pc, #4] @ (800b8a8 ) 800b8a2: 4313 orrs r3, r2 800b8a4: 604b str r3, [r1, #4] 800b8a6: e025 b.n 800b8f4 800b8a8: 58024400 .word 0x58024400 800b8ac: 4b9a ldr r3, [pc, #616] @ (800bb18 ) 800b8ae: 685b ldr r3, [r3, #4] 800b8b0: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800b8b4: 687b ldr r3, [r7, #4] 800b8b6: 691b ldr r3, [r3, #16] 800b8b8: 061b lsls r3, r3, #24 800b8ba: 4997 ldr r1, [pc, #604] @ (800bb18 ) 800b8bc: 4313 orrs r3, r2 800b8be: 604b str r3, [r1, #4] 800b8c0: e018 b.n 800b8f4 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800b8c2: 4b95 ldr r3, [pc, #596] @ (800bb18 ) 800b8c4: 681b ldr r3, [r3, #0] 800b8c6: 4a94 ldr r2, [pc, #592] @ (800bb18 ) 800b8c8: f023 0301 bic.w r3, r3, #1 800b8cc: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b8ce: f7fa f96f bl 8005bb0 800b8d2: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800b8d4: e008 b.n 800b8e8 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800b8d6: f7fa f96b bl 8005bb0 800b8da: 4602 mov r2, r0 800b8dc: 6a7b ldr r3, [r7, #36] @ 0x24 800b8de: 1ad3 subs r3, r2, r3 800b8e0: 2b02 cmp r3, #2 800b8e2: d901 bls.n 800b8e8 { return HAL_TIMEOUT; 800b8e4: 2303 movs r3, #3 800b8e6: e2ed b.n 800bec4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800b8e8: 4b8b ldr r3, [pc, #556] @ (800bb18 ) 800b8ea: 681b ldr r3, [r3, #0] 800b8ec: f003 0304 and.w r3, r3, #4 800b8f0: 2b00 cmp r3, #0 800b8f2: d1f0 bne.n 800b8d6 } } } } /*----------------------------- CSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 800b8f4: 687b ldr r3, [r7, #4] 800b8f6: 681b ldr r3, [r3, #0] 800b8f8: f003 0310 and.w r3, r3, #16 800b8fc: 2b00 cmp r3, #0 800b8fe: f000 80a9 beq.w 800ba54 /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b902: 4b85 ldr r3, [pc, #532] @ (800bb18 ) 800b904: 691b ldr r3, [r3, #16] 800b906: f003 0338 and.w r3, r3, #56 @ 0x38 800b90a: 61bb str r3, [r7, #24] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800b90c: 4b82 ldr r3, [pc, #520] @ (800bb18 ) 800b90e: 6a9b ldr r3, [r3, #40] @ 0x28 800b910: 617b str r3, [r7, #20] if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 800b912: 69bb ldr r3, [r7, #24] 800b914: 2b08 cmp r3, #8 800b916: d007 beq.n 800b928 800b918: 69bb ldr r3, [r7, #24] 800b91a: 2b18 cmp r3, #24 800b91c: d13a bne.n 800b994 800b91e: 697b ldr r3, [r7, #20] 800b920: f003 0303 and.w r3, r3, #3 800b924: 2b01 cmp r3, #1 800b926: d135 bne.n 800b994 { /* When CSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800b928: 4b7b ldr r3, [pc, #492] @ (800bb18 ) 800b92a: 681b ldr r3, [r3, #0] 800b92c: f403 7380 and.w r3, r3, #256 @ 0x100 800b930: 2b00 cmp r3, #0 800b932: d005 beq.n 800b940 800b934: 687b ldr r3, [r7, #4] 800b936: 69db ldr r3, [r3, #28] 800b938: 2b80 cmp r3, #128 @ 0x80 800b93a: d001 beq.n 800b940 { return HAL_ERROR; 800b93c: 2301 movs r3, #1 800b93e: e2c1 b.n 800bec4 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800b940: f7fa f942 bl 8005bc8 800b944: 4603 mov r3, r0 800b946: f241 0203 movw r2, #4099 @ 0x1003 800b94a: 4293 cmp r3, r2 800b94c: d817 bhi.n 800b97e 800b94e: 687b ldr r3, [r7, #4] 800b950: 6a1b ldr r3, [r3, #32] 800b952: 2b20 cmp r3, #32 800b954: d108 bne.n 800b968 800b956: 4b70 ldr r3, [pc, #448] @ (800bb18 ) 800b958: 685b ldr r3, [r3, #4] 800b95a: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 800b95e: 4a6e ldr r2, [pc, #440] @ (800bb18 ) 800b960: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800b964: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800b966: e075 b.n 800ba54 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800b968: 4b6b ldr r3, [pc, #428] @ (800bb18 ) 800b96a: 685b ldr r3, [r3, #4] 800b96c: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800b970: 687b ldr r3, [r7, #4] 800b972: 6a1b ldr r3, [r3, #32] 800b974: 069b lsls r3, r3, #26 800b976: 4968 ldr r1, [pc, #416] @ (800bb18 ) 800b978: 4313 orrs r3, r2 800b97a: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800b97c: e06a b.n 800ba54 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800b97e: 4b66 ldr r3, [pc, #408] @ (800bb18 ) 800b980: 68db ldr r3, [r3, #12] 800b982: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 800b986: 687b ldr r3, [r7, #4] 800b988: 6a1b ldr r3, [r3, #32] 800b98a: 061b lsls r3, r3, #24 800b98c: 4962 ldr r1, [pc, #392] @ (800bb18 ) 800b98e: 4313 orrs r3, r2 800b990: 60cb str r3, [r1, #12] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800b992: e05f b.n 800ba54 } } else { /* Check the CSI State */ if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) 800b994: 687b ldr r3, [r7, #4] 800b996: 69db ldr r3, [r3, #28] 800b998: 2b00 cmp r3, #0 800b99a: d042 beq.n 800ba22 { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 800b99c: 4b5e ldr r3, [pc, #376] @ (800bb18 ) 800b99e: 681b ldr r3, [r3, #0] 800b9a0: 4a5d ldr r2, [pc, #372] @ (800bb18 ) 800b9a2: f043 0380 orr.w r3, r3, #128 @ 0x80 800b9a6: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b9a8: f7fa f902 bl 8005bb0 800b9ac: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800b9ae: e008 b.n 800b9c2 { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 800b9b0: f7fa f8fe bl 8005bb0 800b9b4: 4602 mov r2, r0 800b9b6: 6a7b ldr r3, [r7, #36] @ 0x24 800b9b8: 1ad3 subs r3, r2, r3 800b9ba: 2b02 cmp r3, #2 800b9bc: d901 bls.n 800b9c2 { return HAL_TIMEOUT; 800b9be: 2303 movs r3, #3 800b9c0: e280 b.n 800bec4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800b9c2: 4b55 ldr r3, [pc, #340] @ (800bb18 ) 800b9c4: 681b ldr r3, [r3, #0] 800b9c6: f403 7380 and.w r3, r3, #256 @ 0x100 800b9ca: 2b00 cmp r3, #0 800b9cc: d0f0 beq.n 800b9b0 } } /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800b9ce: f7fa f8fb bl 8005bc8 800b9d2: 4603 mov r3, r0 800b9d4: f241 0203 movw r2, #4099 @ 0x1003 800b9d8: 4293 cmp r3, r2 800b9da: d817 bhi.n 800ba0c 800b9dc: 687b ldr r3, [r7, #4] 800b9de: 6a1b ldr r3, [r3, #32] 800b9e0: 2b20 cmp r3, #32 800b9e2: d108 bne.n 800b9f6 800b9e4: 4b4c ldr r3, [pc, #304] @ (800bb18 ) 800b9e6: 685b ldr r3, [r3, #4] 800b9e8: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 800b9ec: 4a4a ldr r2, [pc, #296] @ (800bb18 ) 800b9ee: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800b9f2: 6053 str r3, [r2, #4] 800b9f4: e02e b.n 800ba54 800b9f6: 4b48 ldr r3, [pc, #288] @ (800bb18 ) 800b9f8: 685b ldr r3, [r3, #4] 800b9fa: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800b9fe: 687b ldr r3, [r7, #4] 800ba00: 6a1b ldr r3, [r3, #32] 800ba02: 069b lsls r3, r3, #26 800ba04: 4944 ldr r1, [pc, #272] @ (800bb18 ) 800ba06: 4313 orrs r3, r2 800ba08: 604b str r3, [r1, #4] 800ba0a: e023 b.n 800ba54 800ba0c: 4b42 ldr r3, [pc, #264] @ (800bb18 ) 800ba0e: 68db ldr r3, [r3, #12] 800ba10: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 800ba14: 687b ldr r3, [r7, #4] 800ba16: 6a1b ldr r3, [r3, #32] 800ba18: 061b lsls r3, r3, #24 800ba1a: 493f ldr r1, [pc, #252] @ (800bb18 ) 800ba1c: 4313 orrs r3, r2 800ba1e: 60cb str r3, [r1, #12] 800ba20: e018 b.n 800ba54 } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 800ba22: 4b3d ldr r3, [pc, #244] @ (800bb18 ) 800ba24: 681b ldr r3, [r3, #0] 800ba26: 4a3c ldr r2, [pc, #240] @ (800bb18 ) 800ba28: f023 0380 bic.w r3, r3, #128 @ 0x80 800ba2c: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ba2e: f7fa f8bf bl 8005bb0 800ba32: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800ba34: e008 b.n 800ba48 { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 800ba36: f7fa f8bb bl 8005bb0 800ba3a: 4602 mov r2, r0 800ba3c: 6a7b ldr r3, [r7, #36] @ 0x24 800ba3e: 1ad3 subs r3, r2, r3 800ba40: 2b02 cmp r3, #2 800ba42: d901 bls.n 800ba48 { return HAL_TIMEOUT; 800ba44: 2303 movs r3, #3 800ba46: e23d b.n 800bec4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800ba48: 4b33 ldr r3, [pc, #204] @ (800bb18 ) 800ba4a: 681b ldr r3, [r3, #0] 800ba4c: f403 7380 and.w r3, r3, #256 @ 0x100 800ba50: 2b00 cmp r3, #0 800ba52: d1f0 bne.n 800ba36 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800ba54: 687b ldr r3, [r7, #4] 800ba56: 681b ldr r3, [r3, #0] 800ba58: f003 0308 and.w r3, r3, #8 800ba5c: 2b00 cmp r3, #0 800ba5e: d036 beq.n 800bace { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 800ba60: 687b ldr r3, [r7, #4] 800ba62: 695b ldr r3, [r3, #20] 800ba64: 2b00 cmp r3, #0 800ba66: d019 beq.n 800ba9c { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800ba68: 4b2b ldr r3, [pc, #172] @ (800bb18 ) 800ba6a: 6f5b ldr r3, [r3, #116] @ 0x74 800ba6c: 4a2a ldr r2, [pc, #168] @ (800bb18 ) 800ba6e: f043 0301 orr.w r3, r3, #1 800ba72: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ba74: f7fa f89c bl 8005bb0 800ba78: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800ba7a: e008 b.n 800ba8e { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800ba7c: f7fa f898 bl 8005bb0 800ba80: 4602 mov r2, r0 800ba82: 6a7b ldr r3, [r7, #36] @ 0x24 800ba84: 1ad3 subs r3, r2, r3 800ba86: 2b02 cmp r3, #2 800ba88: d901 bls.n 800ba8e { return HAL_TIMEOUT; 800ba8a: 2303 movs r3, #3 800ba8c: e21a b.n 800bec4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800ba8e: 4b22 ldr r3, [pc, #136] @ (800bb18 ) 800ba90: 6f5b ldr r3, [r3, #116] @ 0x74 800ba92: f003 0302 and.w r3, r3, #2 800ba96: 2b00 cmp r3, #0 800ba98: d0f0 beq.n 800ba7c 800ba9a: e018 b.n 800bace } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800ba9c: 4b1e ldr r3, [pc, #120] @ (800bb18 ) 800ba9e: 6f5b ldr r3, [r3, #116] @ 0x74 800baa0: 4a1d ldr r2, [pc, #116] @ (800bb18 ) 800baa2: f023 0301 bic.w r3, r3, #1 800baa6: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800baa8: f7fa f882 bl 8005bb0 800baac: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800baae: e008 b.n 800bac2 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800bab0: f7fa f87e bl 8005bb0 800bab4: 4602 mov r2, r0 800bab6: 6a7b ldr r3, [r7, #36] @ 0x24 800bab8: 1ad3 subs r3, r2, r3 800baba: 2b02 cmp r3, #2 800babc: d901 bls.n 800bac2 { return HAL_TIMEOUT; 800babe: 2303 movs r3, #3 800bac0: e200 b.n 800bec4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800bac2: 4b15 ldr r3, [pc, #84] @ (800bb18 ) 800bac4: 6f5b ldr r3, [r3, #116] @ 0x74 800bac6: f003 0302 and.w r3, r3, #2 800baca: 2b00 cmp r3, #0 800bacc: d1f0 bne.n 800bab0 } } } /*------------------------------ HSI48 Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 800bace: 687b ldr r3, [r7, #4] 800bad0: 681b ldr r3, [r3, #0] 800bad2: f003 0320 and.w r3, r3, #32 800bad6: 2b00 cmp r3, #0 800bad8: d039 beq.n 800bb4e { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) 800bada: 687b ldr r3, [r7, #4] 800badc: 699b ldr r3, [r3, #24] 800bade: 2b00 cmp r3, #0 800bae0: d01c beq.n 800bb1c { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 800bae2: 4b0d ldr r3, [pc, #52] @ (800bb18 ) 800bae4: 681b ldr r3, [r3, #0] 800bae6: 4a0c ldr r2, [pc, #48] @ (800bb18 ) 800bae8: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800baec: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800baee: f7fa f85f bl 8005bb0 800baf2: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 800baf4: e008 b.n 800bb08 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800baf6: f7fa f85b bl 8005bb0 800bafa: 4602 mov r2, r0 800bafc: 6a7b ldr r3, [r7, #36] @ 0x24 800bafe: 1ad3 subs r3, r2, r3 800bb00: 2b02 cmp r3, #2 800bb02: d901 bls.n 800bb08 { return HAL_TIMEOUT; 800bb04: 2303 movs r3, #3 800bb06: e1dd b.n 800bec4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 800bb08: 4b03 ldr r3, [pc, #12] @ (800bb18 ) 800bb0a: 681b ldr r3, [r3, #0] 800bb0c: f403 5300 and.w r3, r3, #8192 @ 0x2000 800bb10: 2b00 cmp r3, #0 800bb12: d0f0 beq.n 800baf6 800bb14: e01b b.n 800bb4e 800bb16: bf00 nop 800bb18: 58024400 .word 0x58024400 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 800bb1c: 4b9b ldr r3, [pc, #620] @ (800bd8c ) 800bb1e: 681b ldr r3, [r3, #0] 800bb20: 4a9a ldr r2, [pc, #616] @ (800bd8c ) 800bb22: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800bb26: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800bb28: f7fa f842 bl 8005bb0 800bb2c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800bb2e: e008 b.n 800bb42 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800bb30: f7fa f83e bl 8005bb0 800bb34: 4602 mov r2, r0 800bb36: 6a7b ldr r3, [r7, #36] @ 0x24 800bb38: 1ad3 subs r3, r2, r3 800bb3a: 2b02 cmp r3, #2 800bb3c: d901 bls.n 800bb42 { return HAL_TIMEOUT; 800bb3e: 2303 movs r3, #3 800bb40: e1c0 b.n 800bec4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800bb42: 4b92 ldr r3, [pc, #584] @ (800bd8c ) 800bb44: 681b ldr r3, [r3, #0] 800bb46: f403 5300 and.w r3, r3, #8192 @ 0x2000 800bb4a: 2b00 cmp r3, #0 800bb4c: d1f0 bne.n 800bb30 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800bb4e: 687b ldr r3, [r7, #4] 800bb50: 681b ldr r3, [r3, #0] 800bb52: f003 0304 and.w r3, r3, #4 800bb56: 2b00 cmp r3, #0 800bb58: f000 8081 beq.w 800bc5e { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 800bb5c: 4b8c ldr r3, [pc, #560] @ (800bd90 ) 800bb5e: 681b ldr r3, [r3, #0] 800bb60: 4a8b ldr r2, [pc, #556] @ (800bd90 ) 800bb62: f443 7380 orr.w r3, r3, #256 @ 0x100 800bb66: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800bb68: f7fa f822 bl 8005bb0 800bb6c: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800bb6e: e008 b.n 800bb82 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800bb70: f7fa f81e bl 8005bb0 800bb74: 4602 mov r2, r0 800bb76: 6a7b ldr r3, [r7, #36] @ 0x24 800bb78: 1ad3 subs r3, r2, r3 800bb7a: 2b64 cmp r3, #100 @ 0x64 800bb7c: d901 bls.n 800bb82 { return HAL_TIMEOUT; 800bb7e: 2303 movs r3, #3 800bb80: e1a0 b.n 800bec4 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800bb82: 4b83 ldr r3, [pc, #524] @ (800bd90 ) 800bb84: 681b ldr r3, [r3, #0] 800bb86: f403 7380 and.w r3, r3, #256 @ 0x100 800bb8a: 2b00 cmp r3, #0 800bb8c: d0f0 beq.n 800bb70 } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800bb8e: 687b ldr r3, [r7, #4] 800bb90: 689b ldr r3, [r3, #8] 800bb92: 2b01 cmp r3, #1 800bb94: d106 bne.n 800bba4 800bb96: 4b7d ldr r3, [pc, #500] @ (800bd8c ) 800bb98: 6f1b ldr r3, [r3, #112] @ 0x70 800bb9a: 4a7c ldr r2, [pc, #496] @ (800bd8c ) 800bb9c: f043 0301 orr.w r3, r3, #1 800bba0: 6713 str r3, [r2, #112] @ 0x70 800bba2: e02d b.n 800bc00 800bba4: 687b ldr r3, [r7, #4] 800bba6: 689b ldr r3, [r3, #8] 800bba8: 2b00 cmp r3, #0 800bbaa: d10c bne.n 800bbc6 800bbac: 4b77 ldr r3, [pc, #476] @ (800bd8c ) 800bbae: 6f1b ldr r3, [r3, #112] @ 0x70 800bbb0: 4a76 ldr r2, [pc, #472] @ (800bd8c ) 800bbb2: f023 0301 bic.w r3, r3, #1 800bbb6: 6713 str r3, [r2, #112] @ 0x70 800bbb8: 4b74 ldr r3, [pc, #464] @ (800bd8c ) 800bbba: 6f1b ldr r3, [r3, #112] @ 0x70 800bbbc: 4a73 ldr r2, [pc, #460] @ (800bd8c ) 800bbbe: f023 0304 bic.w r3, r3, #4 800bbc2: 6713 str r3, [r2, #112] @ 0x70 800bbc4: e01c b.n 800bc00 800bbc6: 687b ldr r3, [r7, #4] 800bbc8: 689b ldr r3, [r3, #8] 800bbca: 2b05 cmp r3, #5 800bbcc: d10c bne.n 800bbe8 800bbce: 4b6f ldr r3, [pc, #444] @ (800bd8c ) 800bbd0: 6f1b ldr r3, [r3, #112] @ 0x70 800bbd2: 4a6e ldr r2, [pc, #440] @ (800bd8c ) 800bbd4: f043 0304 orr.w r3, r3, #4 800bbd8: 6713 str r3, [r2, #112] @ 0x70 800bbda: 4b6c ldr r3, [pc, #432] @ (800bd8c ) 800bbdc: 6f1b ldr r3, [r3, #112] @ 0x70 800bbde: 4a6b ldr r2, [pc, #428] @ (800bd8c ) 800bbe0: f043 0301 orr.w r3, r3, #1 800bbe4: 6713 str r3, [r2, #112] @ 0x70 800bbe6: e00b b.n 800bc00 800bbe8: 4b68 ldr r3, [pc, #416] @ (800bd8c ) 800bbea: 6f1b ldr r3, [r3, #112] @ 0x70 800bbec: 4a67 ldr r2, [pc, #412] @ (800bd8c ) 800bbee: f023 0301 bic.w r3, r3, #1 800bbf2: 6713 str r3, [r2, #112] @ 0x70 800bbf4: 4b65 ldr r3, [pc, #404] @ (800bd8c ) 800bbf6: 6f1b ldr r3, [r3, #112] @ 0x70 800bbf8: 4a64 ldr r2, [pc, #400] @ (800bd8c ) 800bbfa: f023 0304 bic.w r3, r3, #4 800bbfe: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 800bc00: 687b ldr r3, [r7, #4] 800bc02: 689b ldr r3, [r3, #8] 800bc04: 2b00 cmp r3, #0 800bc06: d015 beq.n 800bc34 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bc08: f7f9 ffd2 bl 8005bb0 800bc0c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800bc0e: e00a b.n 800bc26 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800bc10: f7f9 ffce bl 8005bb0 800bc14: 4602 mov r2, r0 800bc16: 6a7b ldr r3, [r7, #36] @ 0x24 800bc18: 1ad3 subs r3, r2, r3 800bc1a: f241 3288 movw r2, #5000 @ 0x1388 800bc1e: 4293 cmp r3, r2 800bc20: d901 bls.n 800bc26 { return HAL_TIMEOUT; 800bc22: 2303 movs r3, #3 800bc24: e14e b.n 800bec4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800bc26: 4b59 ldr r3, [pc, #356] @ (800bd8c ) 800bc28: 6f1b ldr r3, [r3, #112] @ 0x70 800bc2a: f003 0302 and.w r3, r3, #2 800bc2e: 2b00 cmp r3, #0 800bc30: d0ee beq.n 800bc10 800bc32: e014 b.n 800bc5e } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bc34: f7f9 ffbc bl 8005bb0 800bc38: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800bc3a: e00a b.n 800bc52 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800bc3c: f7f9 ffb8 bl 8005bb0 800bc40: 4602 mov r2, r0 800bc42: 6a7b ldr r3, [r7, #36] @ 0x24 800bc44: 1ad3 subs r3, r2, r3 800bc46: f241 3288 movw r2, #5000 @ 0x1388 800bc4a: 4293 cmp r3, r2 800bc4c: d901 bls.n 800bc52 { return HAL_TIMEOUT; 800bc4e: 2303 movs r3, #3 800bc50: e138 b.n 800bec4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800bc52: 4b4e ldr r3, [pc, #312] @ (800bd8c ) 800bc54: 6f1b ldr r3, [r3, #112] @ 0x70 800bc56: f003 0302 and.w r3, r3, #2 800bc5a: 2b00 cmp r3, #0 800bc5c: d1ee bne.n 800bc3c } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800bc5e: 687b ldr r3, [r7, #4] 800bc60: 6a5b ldr r3, [r3, #36] @ 0x24 800bc62: 2b00 cmp r3, #0 800bc64: f000 812d beq.w 800bec2 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 800bc68: 4b48 ldr r3, [pc, #288] @ (800bd8c ) 800bc6a: 691b ldr r3, [r3, #16] 800bc6c: f003 0338 and.w r3, r3, #56 @ 0x38 800bc70: 2b18 cmp r3, #24 800bc72: f000 80bd beq.w 800bdf0 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 800bc76: 687b ldr r3, [r7, #4] 800bc78: 6a5b ldr r3, [r3, #36] @ 0x24 800bc7a: 2b02 cmp r3, #2 800bc7c: f040 809e bne.w 800bdbc assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800bc80: 4b42 ldr r3, [pc, #264] @ (800bd8c ) 800bc82: 681b ldr r3, [r3, #0] 800bc84: 4a41 ldr r2, [pc, #260] @ (800bd8c ) 800bc86: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800bc8a: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bc8c: f7f9 ff90 bl 8005bb0 800bc90: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800bc92: e008 b.n 800bca6 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800bc94: f7f9 ff8c bl 8005bb0 800bc98: 4602 mov r2, r0 800bc9a: 6a7b ldr r3, [r7, #36] @ 0x24 800bc9c: 1ad3 subs r3, r2, r3 800bc9e: 2b02 cmp r3, #2 800bca0: d901 bls.n 800bca6 { return HAL_TIMEOUT; 800bca2: 2303 movs r3, #3 800bca4: e10e b.n 800bec4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800bca6: 4b39 ldr r3, [pc, #228] @ (800bd8c ) 800bca8: 681b ldr r3, [r3, #0] 800bcaa: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800bcae: 2b00 cmp r3, #0 800bcb0: d1f0 bne.n 800bc94 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 800bcb2: 4b36 ldr r3, [pc, #216] @ (800bd8c ) 800bcb4: 6a9a ldr r2, [r3, #40] @ 0x28 800bcb6: 4b37 ldr r3, [pc, #220] @ (800bd94 ) 800bcb8: 4013 ands r3, r2 800bcba: 687a ldr r2, [r7, #4] 800bcbc: 6a91 ldr r1, [r2, #40] @ 0x28 800bcbe: 687a ldr r2, [r7, #4] 800bcc0: 6ad2 ldr r2, [r2, #44] @ 0x2c 800bcc2: 0112 lsls r2, r2, #4 800bcc4: 430a orrs r2, r1 800bcc6: 4931 ldr r1, [pc, #196] @ (800bd8c ) 800bcc8: 4313 orrs r3, r2 800bcca: 628b str r3, [r1, #40] @ 0x28 800bccc: 687b ldr r3, [r7, #4] 800bcce: 6b1b ldr r3, [r3, #48] @ 0x30 800bcd0: 3b01 subs r3, #1 800bcd2: f3c3 0208 ubfx r2, r3, #0, #9 800bcd6: 687b ldr r3, [r7, #4] 800bcd8: 6b5b ldr r3, [r3, #52] @ 0x34 800bcda: 3b01 subs r3, #1 800bcdc: 025b lsls r3, r3, #9 800bcde: b29b uxth r3, r3 800bce0: 431a orrs r2, r3 800bce2: 687b ldr r3, [r7, #4] 800bce4: 6b9b ldr r3, [r3, #56] @ 0x38 800bce6: 3b01 subs r3, #1 800bce8: 041b lsls r3, r3, #16 800bcea: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800bcee: 431a orrs r2, r3 800bcf0: 687b ldr r3, [r7, #4] 800bcf2: 6bdb ldr r3, [r3, #60] @ 0x3c 800bcf4: 3b01 subs r3, #1 800bcf6: 061b lsls r3, r3, #24 800bcf8: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800bcfc: 4923 ldr r1, [pc, #140] @ (800bd8c ) 800bcfe: 4313 orrs r3, r2 800bd00: 630b str r3, [r1, #48] @ 0x30 RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Disable PLLFRACN . */ __HAL_RCC_PLLFRACN_DISABLE(); 800bd02: 4b22 ldr r3, [pc, #136] @ (800bd8c ) 800bd04: 6adb ldr r3, [r3, #44] @ 0x2c 800bd06: 4a21 ldr r2, [pc, #132] @ (800bd8c ) 800bd08: f023 0301 bic.w r3, r3, #1 800bd0c: 62d3 str r3, [r2, #44] @ 0x2c /* Configure PLL PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800bd0e: 4b1f ldr r3, [pc, #124] @ (800bd8c ) 800bd10: 6b5a ldr r2, [r3, #52] @ 0x34 800bd12: 4b21 ldr r3, [pc, #132] @ (800bd98 ) 800bd14: 4013 ands r3, r2 800bd16: 687a ldr r2, [r7, #4] 800bd18: 6c92 ldr r2, [r2, #72] @ 0x48 800bd1a: 00d2 lsls r2, r2, #3 800bd1c: 491b ldr r1, [pc, #108] @ (800bd8c ) 800bd1e: 4313 orrs r3, r2 800bd20: 634b str r3, [r1, #52] @ 0x34 /* Select PLL1 input reference frequency range: VCI */ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 800bd22: 4b1a ldr r3, [pc, #104] @ (800bd8c ) 800bd24: 6adb ldr r3, [r3, #44] @ 0x2c 800bd26: f023 020c bic.w r2, r3, #12 800bd2a: 687b ldr r3, [r7, #4] 800bd2c: 6c1b ldr r3, [r3, #64] @ 0x40 800bd2e: 4917 ldr r1, [pc, #92] @ (800bd8c ) 800bd30: 4313 orrs r3, r2 800bd32: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL1 output frequency range : VCO */ __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 800bd34: 4b15 ldr r3, [pc, #84] @ (800bd8c ) 800bd36: 6adb ldr r3, [r3, #44] @ 0x2c 800bd38: f023 0202 bic.w r2, r3, #2 800bd3c: 687b ldr r3, [r7, #4] 800bd3e: 6c5b ldr r3, [r3, #68] @ 0x44 800bd40: 4912 ldr r1, [pc, #72] @ (800bd8c ) 800bd42: 4313 orrs r3, r2 800bd44: 62cb str r3, [r1, #44] @ 0x2c /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 800bd46: 4b11 ldr r3, [pc, #68] @ (800bd8c ) 800bd48: 6adb ldr r3, [r3, #44] @ 0x2c 800bd4a: 4a10 ldr r2, [pc, #64] @ (800bd8c ) 800bd4c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800bd50: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1Q Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800bd52: 4b0e ldr r3, [pc, #56] @ (800bd8c ) 800bd54: 6adb ldr r3, [r3, #44] @ 0x2c 800bd56: 4a0d ldr r2, [pc, #52] @ (800bd8c ) 800bd58: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800bd5c: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1R Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 800bd5e: 4b0b ldr r3, [pc, #44] @ (800bd8c ) 800bd60: 6adb ldr r3, [r3, #44] @ 0x2c 800bd62: 4a0a ldr r2, [pc, #40] @ (800bd8c ) 800bd64: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800bd68: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1FRACN . */ __HAL_RCC_PLLFRACN_ENABLE(); 800bd6a: 4b08 ldr r3, [pc, #32] @ (800bd8c ) 800bd6c: 6adb ldr r3, [r3, #44] @ 0x2c 800bd6e: 4a07 ldr r2, [pc, #28] @ (800bd8c ) 800bd70: f043 0301 orr.w r3, r3, #1 800bd74: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800bd76: 4b05 ldr r3, [pc, #20] @ (800bd8c ) 800bd78: 681b ldr r3, [r3, #0] 800bd7a: 4a04 ldr r2, [pc, #16] @ (800bd8c ) 800bd7c: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800bd80: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bd82: f7f9 ff15 bl 8005bb0 800bd86: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800bd88: e011 b.n 800bdae 800bd8a: bf00 nop 800bd8c: 58024400 .word 0x58024400 800bd90: 58024800 .word 0x58024800 800bd94: fffffc0c .word 0xfffffc0c 800bd98: ffff0007 .word 0xffff0007 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800bd9c: f7f9 ff08 bl 8005bb0 800bda0: 4602 mov r2, r0 800bda2: 6a7b ldr r3, [r7, #36] @ 0x24 800bda4: 1ad3 subs r3, r2, r3 800bda6: 2b02 cmp r3, #2 800bda8: d901 bls.n 800bdae { return HAL_TIMEOUT; 800bdaa: 2303 movs r3, #3 800bdac: e08a b.n 800bec4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800bdae: 4b47 ldr r3, [pc, #284] @ (800becc ) 800bdb0: 681b ldr r3, [r3, #0] 800bdb2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800bdb6: 2b00 cmp r3, #0 800bdb8: d0f0 beq.n 800bd9c 800bdba: e082 b.n 800bec2 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800bdbc: 4b43 ldr r3, [pc, #268] @ (800becc ) 800bdbe: 681b ldr r3, [r3, #0] 800bdc0: 4a42 ldr r2, [pc, #264] @ (800becc ) 800bdc2: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800bdc6: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bdc8: f7f9 fef2 bl 8005bb0 800bdcc: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800bdce: e008 b.n 800bde2 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800bdd0: f7f9 feee bl 8005bb0 800bdd4: 4602 mov r2, r0 800bdd6: 6a7b ldr r3, [r7, #36] @ 0x24 800bdd8: 1ad3 subs r3, r2, r3 800bdda: 2b02 cmp r3, #2 800bddc: d901 bls.n 800bde2 { return HAL_TIMEOUT; 800bdde: 2303 movs r3, #3 800bde0: e070 b.n 800bec4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800bde2: 4b3a ldr r3, [pc, #232] @ (800becc ) 800bde4: 681b ldr r3, [r3, #0] 800bde6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800bdea: 2b00 cmp r3, #0 800bdec: d1f0 bne.n 800bdd0 800bdee: e068 b.n 800bec2 } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp1_pllckcfg = RCC->PLLCKSELR; 800bdf0: 4b36 ldr r3, [pc, #216] @ (800becc ) 800bdf2: 6a9b ldr r3, [r3, #40] @ 0x28 800bdf4: 613b str r3, [r7, #16] temp2_pllckcfg = RCC->PLL1DIVR; 800bdf6: 4b35 ldr r3, [pc, #212] @ (800becc ) 800bdf8: 6b1b ldr r3, [r3, #48] @ 0x30 800bdfa: 60fb str r3, [r7, #12] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800bdfc: 687b ldr r3, [r7, #4] 800bdfe: 6a5b ldr r3, [r3, #36] @ 0x24 800be00: 2b01 cmp r3, #1 800be02: d031 beq.n 800be68 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800be04: 693b ldr r3, [r7, #16] 800be06: f003 0203 and.w r2, r3, #3 800be0a: 687b ldr r3, [r7, #4] 800be0c: 6a9b ldr r3, [r3, #40] @ 0x28 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800be0e: 429a cmp r2, r3 800be10: d12a bne.n 800be68 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800be12: 693b ldr r3, [r7, #16] 800be14: 091b lsrs r3, r3, #4 800be16: f003 023f and.w r2, r3, #63 @ 0x3f 800be1a: 687b ldr r3, [r7, #4] 800be1c: 6adb ldr r3, [r3, #44] @ 0x2c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800be1e: 429a cmp r2, r3 800be20: d122 bne.n 800be68 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800be22: 68fb ldr r3, [r7, #12] 800be24: f3c3 0208 ubfx r2, r3, #0, #9 800be28: 687b ldr r3, [r7, #4] 800be2a: 6b1b ldr r3, [r3, #48] @ 0x30 800be2c: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800be2e: 429a cmp r2, r3 800be30: d11a bne.n 800be68 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800be32: 68fb ldr r3, [r7, #12] 800be34: 0a5b lsrs r3, r3, #9 800be36: f003 027f and.w r2, r3, #127 @ 0x7f 800be3a: 687b ldr r3, [r7, #4] 800be3c: 6b5b ldr r3, [r3, #52] @ 0x34 800be3e: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800be40: 429a cmp r2, r3 800be42: d111 bne.n 800be68 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 800be44: 68fb ldr r3, [r7, #12] 800be46: 0c1b lsrs r3, r3, #16 800be48: f003 027f and.w r2, r3, #127 @ 0x7f 800be4c: 687b ldr r3, [r7, #4] 800be4e: 6b9b ldr r3, [r3, #56] @ 0x38 800be50: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800be52: 429a cmp r2, r3 800be54: d108 bne.n 800be68 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 800be56: 68fb ldr r3, [r7, #12] 800be58: 0e1b lsrs r3, r3, #24 800be5a: f003 027f and.w r2, r3, #127 @ 0x7f 800be5e: 687b ldr r3, [r7, #4] 800be60: 6bdb ldr r3, [r3, #60] @ 0x3c 800be62: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 800be64: 429a cmp r2, r3 800be66: d001 beq.n 800be6c { return HAL_ERROR; 800be68: 2301 movs r3, #1 800be6a: e02b b.n 800bec4 } else { /* Check if only fractional part needs to be updated */ temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); 800be6c: 4b17 ldr r3, [pc, #92] @ (800becc ) 800be6e: 6b5b ldr r3, [r3, #52] @ 0x34 800be70: 08db lsrs r3, r3, #3 800be72: f3c3 030c ubfx r3, r3, #0, #13 800be76: 613b str r3, [r7, #16] if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) 800be78: 687b ldr r3, [r7, #4] 800be7a: 6c9b ldr r3, [r3, #72] @ 0x48 800be7c: 693a ldr r2, [r7, #16] 800be7e: 429a cmp r2, r3 800be80: d01f beq.n 800bec2 { assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable PLL1FRACEN */ __HAL_RCC_PLLFRACN_DISABLE(); 800be82: 4b12 ldr r3, [pc, #72] @ (800becc ) 800be84: 6adb ldr r3, [r3, #44] @ 0x2c 800be86: 4a11 ldr r2, [pc, #68] @ (800becc ) 800be88: f023 0301 bic.w r3, r3, #1 800be8c: 62d3 str r3, [r2, #44] @ 0x2c /* Get Start Tick*/ tickstart = HAL_GetTick(); 800be8e: f7f9 fe8f bl 8005bb0 800be92: 6278 str r0, [r7, #36] @ 0x24 /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) 800be94: bf00 nop 800be96: f7f9 fe8b bl 8005bb0 800be9a: 4602 mov r2, r0 800be9c: 6a7b ldr r3, [r7, #36] @ 0x24 800be9e: 4293 cmp r3, r2 800bea0: d0f9 beq.n 800be96 { } /* Configure PLL1 PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800bea2: 4b0a ldr r3, [pc, #40] @ (800becc ) 800bea4: 6b5a ldr r2, [r3, #52] @ 0x34 800bea6: 4b0a ldr r3, [pc, #40] @ (800bed0 ) 800bea8: 4013 ands r3, r2 800beaa: 687a ldr r2, [r7, #4] 800beac: 6c92 ldr r2, [r2, #72] @ 0x48 800beae: 00d2 lsls r2, r2, #3 800beb0: 4906 ldr r1, [pc, #24] @ (800becc ) 800beb2: 4313 orrs r3, r2 800beb4: 634b str r3, [r1, #52] @ 0x34 /* Enable PLL1FRACEN to latch new value. */ __HAL_RCC_PLLFRACN_ENABLE(); 800beb6: 4b05 ldr r3, [pc, #20] @ (800becc ) 800beb8: 6adb ldr r3, [r3, #44] @ 0x2c 800beba: 4a04 ldr r2, [pc, #16] @ (800becc ) 800bebc: f043 0301 orr.w r3, r3, #1 800bec0: 62d3 str r3, [r2, #44] @ 0x2c } } } } return HAL_OK; 800bec2: 2300 movs r3, #0 } 800bec4: 4618 mov r0, r3 800bec6: 3730 adds r7, #48 @ 0x30 800bec8: 46bd mov sp, r7 800beca: bd80 pop {r7, pc} 800becc: 58024400 .word 0x58024400 800bed0: ffff0007 .word 0xffff0007 0800bed4 : * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800bed4: b580 push {r7, lr} 800bed6: b086 sub sp, #24 800bed8: af00 add r7, sp, #0 800beda: 6078 str r0, [r7, #4] 800bedc: 6039 str r1, [r7, #0] HAL_StatusTypeDef halstatus; uint32_t tickstart; uint32_t common_system_clock; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800bede: 687b ldr r3, [r7, #4] 800bee0: 2b00 cmp r3, #0 800bee2: d101 bne.n 800bee8 { return HAL_ERROR; 800bee4: 2301 movs r3, #1 800bee6: e19c b.n 800c222 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 800bee8: 4b8a ldr r3, [pc, #552] @ (800c114 ) 800beea: 681b ldr r3, [r3, #0] 800beec: f003 030f and.w r3, r3, #15 800bef0: 683a ldr r2, [r7, #0] 800bef2: 429a cmp r2, r3 800bef4: d910 bls.n 800bf18 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800bef6: 4b87 ldr r3, [pc, #540] @ (800c114 ) 800bef8: 681b ldr r3, [r3, #0] 800befa: f023 020f bic.w r2, r3, #15 800befe: 4985 ldr r1, [pc, #532] @ (800c114 ) 800bf00: 683b ldr r3, [r7, #0] 800bf02: 4313 orrs r3, r2 800bf04: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800bf06: 4b83 ldr r3, [pc, #524] @ (800c114 ) 800bf08: 681b ldr r3, [r3, #0] 800bf0a: f003 030f and.w r3, r3, #15 800bf0e: 683a ldr r2, [r7, #0] 800bf10: 429a cmp r2, r3 800bf12: d001 beq.n 800bf18 { return HAL_ERROR; 800bf14: 2301 movs r3, #1 800bf16: e184 b.n 800c222 } /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 800bf18: 687b ldr r3, [r7, #4] 800bf1a: 681b ldr r3, [r3, #0] 800bf1c: f003 0304 and.w r3, r3, #4 800bf20: 2b00 cmp r3, #0 800bf22: d010 beq.n 800bf46 { #if defined (RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 800bf24: 687b ldr r3, [r7, #4] 800bf26: 691a ldr r2, [r3, #16] 800bf28: 4b7b ldr r3, [pc, #492] @ (800c118 ) 800bf2a: 699b ldr r3, [r3, #24] 800bf2c: f003 0370 and.w r3, r3, #112 @ 0x70 800bf30: 429a cmp r2, r3 800bf32: d908 bls.n 800bf46 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 800bf34: 4b78 ldr r3, [pc, #480] @ (800c118 ) 800bf36: 699b ldr r3, [r3, #24] 800bf38: f023 0270 bic.w r2, r3, #112 @ 0x70 800bf3c: 687b ldr r3, [r7, #4] 800bf3e: 691b ldr r3, [r3, #16] 800bf40: 4975 ldr r1, [pc, #468] @ (800c118 ) 800bf42: 4313 orrs r3, r2 800bf44: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800bf46: 687b ldr r3, [r7, #4] 800bf48: 681b ldr r3, [r3, #0] 800bf4a: f003 0308 and.w r3, r3, #8 800bf4e: 2b00 cmp r3, #0 800bf50: d010 beq.n 800bf74 { #if defined (RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800bf52: 687b ldr r3, [r7, #4] 800bf54: 695a ldr r2, [r3, #20] 800bf56: 4b70 ldr r3, [pc, #448] @ (800c118 ) 800bf58: 69db ldr r3, [r3, #28] 800bf5a: f003 0370 and.w r3, r3, #112 @ 0x70 800bf5e: 429a cmp r2, r3 800bf60: d908 bls.n 800bf74 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800bf62: 4b6d ldr r3, [pc, #436] @ (800c118 ) 800bf64: 69db ldr r3, [r3, #28] 800bf66: f023 0270 bic.w r2, r3, #112 @ 0x70 800bf6a: 687b ldr r3, [r7, #4] 800bf6c: 695b ldr r3, [r3, #20] 800bf6e: 496a ldr r1, [pc, #424] @ (800c118 ) 800bf70: 4313 orrs r3, r2 800bf72: 61cb str r3, [r1, #28] MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800bf74: 687b ldr r3, [r7, #4] 800bf76: 681b ldr r3, [r3, #0] 800bf78: f003 0310 and.w r3, r3, #16 800bf7c: 2b00 cmp r3, #0 800bf7e: d010 beq.n 800bfa2 { #if defined(RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800bf80: 687b ldr r3, [r7, #4] 800bf82: 699a ldr r2, [r3, #24] 800bf84: 4b64 ldr r3, [pc, #400] @ (800c118 ) 800bf86: 69db ldr r3, [r3, #28] 800bf88: f403 63e0 and.w r3, r3, #1792 @ 0x700 800bf8c: 429a cmp r2, r3 800bf8e: d908 bls.n 800bfa2 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800bf90: 4b61 ldr r3, [pc, #388] @ (800c118 ) 800bf92: 69db ldr r3, [r3, #28] 800bf94: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800bf98: 687b ldr r3, [r7, #4] 800bf9a: 699b ldr r3, [r3, #24] 800bf9c: 495e ldr r1, [pc, #376] @ (800c118 ) 800bf9e: 4313 orrs r3, r2 800bfa0: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800bfa2: 687b ldr r3, [r7, #4] 800bfa4: 681b ldr r3, [r3, #0] 800bfa6: f003 0320 and.w r3, r3, #32 800bfaa: 2b00 cmp r3, #0 800bfac: d010 beq.n 800bfd0 { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800bfae: 687b ldr r3, [r7, #4] 800bfb0: 69da ldr r2, [r3, #28] 800bfb2: 4b59 ldr r3, [pc, #356] @ (800c118 ) 800bfb4: 6a1b ldr r3, [r3, #32] 800bfb6: f003 0370 and.w r3, r3, #112 @ 0x70 800bfba: 429a cmp r2, r3 800bfbc: d908 bls.n 800bfd0 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800bfbe: 4b56 ldr r3, [pc, #344] @ (800c118 ) 800bfc0: 6a1b ldr r3, [r3, #32] 800bfc2: f023 0270 bic.w r2, r3, #112 @ 0x70 800bfc6: 687b ldr r3, [r7, #4] 800bfc8: 69db ldr r3, [r3, #28] 800bfca: 4953 ldr r1, [pc, #332] @ (800c118 ) 800bfcc: 4313 orrs r3, r2 800bfce: 620b str r3, [r1, #32] } #endif } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800bfd0: 687b ldr r3, [r7, #4] 800bfd2: 681b ldr r3, [r3, #0] 800bfd4: f003 0302 and.w r3, r3, #2 800bfd8: 2b00 cmp r3, #0 800bfda: d010 beq.n 800bffe { #if defined (RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800bfdc: 687b ldr r3, [r7, #4] 800bfde: 68da ldr r2, [r3, #12] 800bfe0: 4b4d ldr r3, [pc, #308] @ (800c118 ) 800bfe2: 699b ldr r3, [r3, #24] 800bfe4: f003 030f and.w r3, r3, #15 800bfe8: 429a cmp r2, r3 800bfea: d908 bls.n 800bffe { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800bfec: 4b4a ldr r3, [pc, #296] @ (800c118 ) 800bfee: 699b ldr r3, [r3, #24] 800bff0: f023 020f bic.w r2, r3, #15 800bff4: 687b ldr r3, [r7, #4] 800bff6: 68db ldr r3, [r3, #12] 800bff8: 4947 ldr r1, [pc, #284] @ (800c118 ) 800bffa: 4313 orrs r3, r2 800bffc: 618b str r3, [r1, #24] } #endif } /*------------------------- SYSCLK Configuration -------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800bffe: 687b ldr r3, [r7, #4] 800c000: 681b ldr r3, [r3, #0] 800c002: f003 0301 and.w r3, r3, #1 800c006: 2b00 cmp r3, #0 800c008: d055 beq.n 800c0b6 { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_D1CFGR_D1CPRE) MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); 800c00a: 4b43 ldr r3, [pc, #268] @ (800c118 ) 800c00c: 699b ldr r3, [r3, #24] 800c00e: f423 6270 bic.w r2, r3, #3840 @ 0xf00 800c012: 687b ldr r3, [r7, #4] 800c014: 689b ldr r3, [r3, #8] 800c016: 4940 ldr r1, [pc, #256] @ (800c118 ) 800c018: 4313 orrs r3, r2 800c01a: 618b str r3, [r1, #24] #else MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); #endif /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800c01c: 687b ldr r3, [r7, #4] 800c01e: 685b ldr r3, [r3, #4] 800c020: 2b02 cmp r3, #2 800c022: d107 bne.n 800c034 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800c024: 4b3c ldr r3, [pc, #240] @ (800c118 ) 800c026: 681b ldr r3, [r3, #0] 800c028: f403 3300 and.w r3, r3, #131072 @ 0x20000 800c02c: 2b00 cmp r3, #0 800c02e: d121 bne.n 800c074 { return HAL_ERROR; 800c030: 2301 movs r3, #1 800c032: e0f6 b.n 800c222 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800c034: 687b ldr r3, [r7, #4] 800c036: 685b ldr r3, [r3, #4] 800c038: 2b03 cmp r3, #3 800c03a: d107 bne.n 800c04c { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800c03c: 4b36 ldr r3, [pc, #216] @ (800c118 ) 800c03e: 681b ldr r3, [r3, #0] 800c040: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800c044: 2b00 cmp r3, #0 800c046: d115 bne.n 800c074 { return HAL_ERROR; 800c048: 2301 movs r3, #1 800c04a: e0ea b.n 800c222 } } /* CSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 800c04c: 687b ldr r3, [r7, #4] 800c04e: 685b ldr r3, [r3, #4] 800c050: 2b01 cmp r3, #1 800c052: d107 bne.n 800c064 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800c054: 4b30 ldr r3, [pc, #192] @ (800c118 ) 800c056: 681b ldr r3, [r3, #0] 800c058: f403 7380 and.w r3, r3, #256 @ 0x100 800c05c: 2b00 cmp r3, #0 800c05e: d109 bne.n 800c074 { return HAL_ERROR; 800c060: 2301 movs r3, #1 800c062: e0de b.n 800c222 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800c064: 4b2c ldr r3, [pc, #176] @ (800c118 ) 800c066: 681b ldr r3, [r3, #0] 800c068: f003 0304 and.w r3, r3, #4 800c06c: 2b00 cmp r3, #0 800c06e: d101 bne.n 800c074 { return HAL_ERROR; 800c070: 2301 movs r3, #1 800c072: e0d6 b.n 800c222 } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 800c074: 4b28 ldr r3, [pc, #160] @ (800c118 ) 800c076: 691b ldr r3, [r3, #16] 800c078: f023 0207 bic.w r2, r3, #7 800c07c: 687b ldr r3, [r7, #4] 800c07e: 685b ldr r3, [r3, #4] 800c080: 4925 ldr r1, [pc, #148] @ (800c118 ) 800c082: 4313 orrs r3, r2 800c084: 610b str r3, [r1, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c086: f7f9 fd93 bl 8005bb0 800c08a: 6178 str r0, [r7, #20] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800c08c: e00a b.n 800c0a4 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800c08e: f7f9 fd8f bl 8005bb0 800c092: 4602 mov r2, r0 800c094: 697b ldr r3, [r7, #20] 800c096: 1ad3 subs r3, r2, r3 800c098: f241 3288 movw r2, #5000 @ 0x1388 800c09c: 4293 cmp r3, r2 800c09e: d901 bls.n 800c0a4 { return HAL_TIMEOUT; 800c0a0: 2303 movs r3, #3 800c0a2: e0be b.n 800c222 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800c0a4: 4b1c ldr r3, [pc, #112] @ (800c118 ) 800c0a6: 691b ldr r3, [r3, #16] 800c0a8: f003 0238 and.w r2, r3, #56 @ 0x38 800c0ac: 687b ldr r3, [r7, #4] 800c0ae: 685b ldr r3, [r3, #4] 800c0b0: 00db lsls r3, r3, #3 800c0b2: 429a cmp r2, r3 800c0b4: d1eb bne.n 800c08e } /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800c0b6: 687b ldr r3, [r7, #4] 800c0b8: 681b ldr r3, [r3, #0] 800c0ba: f003 0302 and.w r3, r3, #2 800c0be: 2b00 cmp r3, #0 800c0c0: d010 beq.n 800c0e4 { #if defined(RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800c0c2: 687b ldr r3, [r7, #4] 800c0c4: 68da ldr r2, [r3, #12] 800c0c6: 4b14 ldr r3, [pc, #80] @ (800c118 ) 800c0c8: 699b ldr r3, [r3, #24] 800c0ca: f003 030f and.w r3, r3, #15 800c0ce: 429a cmp r2, r3 800c0d0: d208 bcs.n 800c0e4 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800c0d2: 4b11 ldr r3, [pc, #68] @ (800c118 ) 800c0d4: 699b ldr r3, [r3, #24] 800c0d6: f023 020f bic.w r2, r3, #15 800c0da: 687b ldr r3, [r7, #4] 800c0dc: 68db ldr r3, [r3, #12] 800c0de: 490e ldr r1, [pc, #56] @ (800c118 ) 800c0e0: 4313 orrs r3, r2 800c0e2: 618b str r3, [r1, #24] } #endif } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 800c0e4: 4b0b ldr r3, [pc, #44] @ (800c114 ) 800c0e6: 681b ldr r3, [r3, #0] 800c0e8: f003 030f and.w r3, r3, #15 800c0ec: 683a ldr r2, [r7, #0] 800c0ee: 429a cmp r2, r3 800c0f0: d214 bcs.n 800c11c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800c0f2: 4b08 ldr r3, [pc, #32] @ (800c114 ) 800c0f4: 681b ldr r3, [r3, #0] 800c0f6: f023 020f bic.w r2, r3, #15 800c0fa: 4906 ldr r1, [pc, #24] @ (800c114 ) 800c0fc: 683b ldr r3, [r7, #0] 800c0fe: 4313 orrs r3, r2 800c100: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800c102: 4b04 ldr r3, [pc, #16] @ (800c114 ) 800c104: 681b ldr r3, [r3, #0] 800c106: f003 030f and.w r3, r3, #15 800c10a: 683a ldr r2, [r7, #0] 800c10c: 429a cmp r2, r3 800c10e: d005 beq.n 800c11c { return HAL_ERROR; 800c110: 2301 movs r3, #1 800c112: e086 b.n 800c222 800c114: 52002000 .word 0x52002000 800c118: 58024400 .word 0x58024400 } } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 800c11c: 687b ldr r3, [r7, #4] 800c11e: 681b ldr r3, [r3, #0] 800c120: f003 0304 and.w r3, r3, #4 800c124: 2b00 cmp r3, #0 800c126: d010 beq.n 800c14a { #if defined(RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 800c128: 687b ldr r3, [r7, #4] 800c12a: 691a ldr r2, [r3, #16] 800c12c: 4b3f ldr r3, [pc, #252] @ (800c22c ) 800c12e: 699b ldr r3, [r3, #24] 800c130: f003 0370 and.w r3, r3, #112 @ 0x70 800c134: 429a cmp r2, r3 800c136: d208 bcs.n 800c14a { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 800c138: 4b3c ldr r3, [pc, #240] @ (800c22c ) 800c13a: 699b ldr r3, [r3, #24] 800c13c: f023 0270 bic.w r2, r3, #112 @ 0x70 800c140: 687b ldr r3, [r7, #4] 800c142: 691b ldr r3, [r3, #16] 800c144: 4939 ldr r1, [pc, #228] @ (800c22c ) 800c146: 4313 orrs r3, r2 800c148: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800c14a: 687b ldr r3, [r7, #4] 800c14c: 681b ldr r3, [r3, #0] 800c14e: f003 0308 and.w r3, r3, #8 800c152: 2b00 cmp r3, #0 800c154: d010 beq.n 800c178 { #if defined(RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800c156: 687b ldr r3, [r7, #4] 800c158: 695a ldr r2, [r3, #20] 800c15a: 4b34 ldr r3, [pc, #208] @ (800c22c ) 800c15c: 69db ldr r3, [r3, #28] 800c15e: f003 0370 and.w r3, r3, #112 @ 0x70 800c162: 429a cmp r2, r3 800c164: d208 bcs.n 800c178 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800c166: 4b31 ldr r3, [pc, #196] @ (800c22c ) 800c168: 69db ldr r3, [r3, #28] 800c16a: f023 0270 bic.w r2, r3, #112 @ 0x70 800c16e: 687b ldr r3, [r7, #4] 800c170: 695b ldr r3, [r3, #20] 800c172: 492e ldr r1, [pc, #184] @ (800c22c ) 800c174: 4313 orrs r3, r2 800c176: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800c178: 687b ldr r3, [r7, #4] 800c17a: 681b ldr r3, [r3, #0] 800c17c: f003 0310 and.w r3, r3, #16 800c180: 2b00 cmp r3, #0 800c182: d010 beq.n 800c1a6 { #if defined (RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800c184: 687b ldr r3, [r7, #4] 800c186: 699a ldr r2, [r3, #24] 800c188: 4b28 ldr r3, [pc, #160] @ (800c22c ) 800c18a: 69db ldr r3, [r3, #28] 800c18c: f403 63e0 and.w r3, r3, #1792 @ 0x700 800c190: 429a cmp r2, r3 800c192: d208 bcs.n 800c1a6 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800c194: 4b25 ldr r3, [pc, #148] @ (800c22c ) 800c196: 69db ldr r3, [r3, #28] 800c198: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800c19c: 687b ldr r3, [r7, #4] 800c19e: 699b ldr r3, [r3, #24] 800c1a0: 4922 ldr r1, [pc, #136] @ (800c22c ) 800c1a2: 4313 orrs r3, r2 800c1a4: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800c1a6: 687b ldr r3, [r7, #4] 800c1a8: 681b ldr r3, [r3, #0] 800c1aa: f003 0320 and.w r3, r3, #32 800c1ae: 2b00 cmp r3, #0 800c1b0: d010 beq.n 800c1d4 { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800c1b2: 687b ldr r3, [r7, #4] 800c1b4: 69da ldr r2, [r3, #28] 800c1b6: 4b1d ldr r3, [pc, #116] @ (800c22c ) 800c1b8: 6a1b ldr r3, [r3, #32] 800c1ba: f003 0370 and.w r3, r3, #112 @ 0x70 800c1be: 429a cmp r2, r3 800c1c0: d208 bcs.n 800c1d4 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800c1c2: 4b1a ldr r3, [pc, #104] @ (800c22c ) 800c1c4: 6a1b ldr r3, [r3, #32] 800c1c6: f023 0270 bic.w r2, r3, #112 @ 0x70 800c1ca: 687b ldr r3, [r7, #4] 800c1cc: 69db ldr r3, [r3, #28] 800c1ce: 4917 ldr r1, [pc, #92] @ (800c22c ) 800c1d0: 4313 orrs r3, r2 800c1d2: 620b str r3, [r1, #32] #endif } /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 800c1d4: f000 f834 bl 800c240 800c1d8: 4602 mov r2, r0 800c1da: 4b14 ldr r3, [pc, #80] @ (800c22c ) 800c1dc: 699b ldr r3, [r3, #24] 800c1de: 0a1b lsrs r3, r3, #8 800c1e0: f003 030f and.w r3, r3, #15 800c1e4: 4912 ldr r1, [pc, #72] @ (800c230 ) 800c1e6: 5ccb ldrb r3, [r1, r3] 800c1e8: f003 031f and.w r3, r3, #31 800c1ec: fa22 f303 lsr.w r3, r2, r3 800c1f0: 613b str r3, [r7, #16] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800c1f2: 4b0e ldr r3, [pc, #56] @ (800c22c ) 800c1f4: 699b ldr r3, [r3, #24] 800c1f6: f003 030f and.w r3, r3, #15 800c1fa: 4a0d ldr r2, [pc, #52] @ (800c230 ) 800c1fc: 5cd3 ldrb r3, [r2, r3] 800c1fe: f003 031f and.w r3, r3, #31 800c202: 693a ldr r2, [r7, #16] 800c204: fa22 f303 lsr.w r3, r2, r3 800c208: 4a0a ldr r2, [pc, #40] @ (800c234 ) 800c20a: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 800c20c: 4a0a ldr r2, [pc, #40] @ (800c238 ) 800c20e: 693b ldr r3, [r7, #16] 800c210: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick(uwTickPrio); 800c212: 4b0a ldr r3, [pc, #40] @ (800c23c ) 800c214: 681b ldr r3, [r3, #0] 800c216: 4618 mov r0, r3 800c218: f7f8 f914 bl 8004444 800c21c: 4603 mov r3, r0 800c21e: 73fb strb r3, [r7, #15] return halstatus; 800c220: 7bfb ldrb r3, [r7, #15] } 800c222: 4618 mov r0, r3 800c224: 3718 adds r7, #24 800c226: 46bd mov sp, r7 800c228: bd80 pop {r7, pc} 800c22a: bf00 nop 800c22c: 58024400 .word 0x58024400 800c230: 08018b5c .word 0x08018b5c 800c234: 24000038 .word 0x24000038 800c238: 24000034 .word 0x24000034 800c23c: 2400003c .word 0x2400003c 0800c240 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800c240: b480 push {r7} 800c242: b089 sub sp, #36 @ 0x24 800c244: af00 add r7, sp, #0 float_t fracn1, pllvco; uint32_t sysclockfreq; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 800c246: 4bb3 ldr r3, [pc, #716] @ (800c514 ) 800c248: 691b ldr r3, [r3, #16] 800c24a: f003 0338 and.w r3, r3, #56 @ 0x38 800c24e: 2b18 cmp r3, #24 800c250: f200 8155 bhi.w 800c4fe 800c254: a201 add r2, pc, #4 @ (adr r2, 800c25c ) 800c256: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c25a: bf00 nop 800c25c: 0800c2c1 .word 0x0800c2c1 800c260: 0800c4ff .word 0x0800c4ff 800c264: 0800c4ff .word 0x0800c4ff 800c268: 0800c4ff .word 0x0800c4ff 800c26c: 0800c4ff .word 0x0800c4ff 800c270: 0800c4ff .word 0x0800c4ff 800c274: 0800c4ff .word 0x0800c4ff 800c278: 0800c4ff .word 0x0800c4ff 800c27c: 0800c2e7 .word 0x0800c2e7 800c280: 0800c4ff .word 0x0800c4ff 800c284: 0800c4ff .word 0x0800c4ff 800c288: 0800c4ff .word 0x0800c4ff 800c28c: 0800c4ff .word 0x0800c4ff 800c290: 0800c4ff .word 0x0800c4ff 800c294: 0800c4ff .word 0x0800c4ff 800c298: 0800c4ff .word 0x0800c4ff 800c29c: 0800c2ed .word 0x0800c2ed 800c2a0: 0800c4ff .word 0x0800c4ff 800c2a4: 0800c4ff .word 0x0800c4ff 800c2a8: 0800c4ff .word 0x0800c4ff 800c2ac: 0800c4ff .word 0x0800c4ff 800c2b0: 0800c4ff .word 0x0800c4ff 800c2b4: 0800c4ff .word 0x0800c4ff 800c2b8: 0800c4ff .word 0x0800c4ff 800c2bc: 0800c2f3 .word 0x0800c2f3 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800c2c0: 4b94 ldr r3, [pc, #592] @ (800c514 ) 800c2c2: 681b ldr r3, [r3, #0] 800c2c4: f003 0320 and.w r3, r3, #32 800c2c8: 2b00 cmp r3, #0 800c2ca: d009 beq.n 800c2e0 { sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800c2cc: 4b91 ldr r3, [pc, #580] @ (800c514 ) 800c2ce: 681b ldr r3, [r3, #0] 800c2d0: 08db lsrs r3, r3, #3 800c2d2: f003 0303 and.w r3, r3, #3 800c2d6: 4a90 ldr r2, [pc, #576] @ (800c518 ) 800c2d8: fa22 f303 lsr.w r3, r2, r3 800c2dc: 61bb str r3, [r7, #24] else { sysclockfreq = (uint32_t) HSI_VALUE; } break; 800c2de: e111 b.n 800c504 sysclockfreq = (uint32_t) HSI_VALUE; 800c2e0: 4b8d ldr r3, [pc, #564] @ (800c518 ) 800c2e2: 61bb str r3, [r7, #24] break; 800c2e4: e10e b.n 800c504 case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ sysclockfreq = CSI_VALUE; 800c2e6: 4b8d ldr r3, [pc, #564] @ (800c51c ) 800c2e8: 61bb str r3, [r7, #24] break; 800c2ea: e10b b.n 800c504 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 800c2ec: 4b8c ldr r3, [pc, #560] @ (800c520 ) 800c2ee: 61bb str r3, [r7, #24] break; 800c2f0: e108 b.n 800c504 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800c2f2: 4b88 ldr r3, [pc, #544] @ (800c514 ) 800c2f4: 6a9b ldr r3, [r3, #40] @ 0x28 800c2f6: f003 0303 and.w r3, r3, #3 800c2fa: 617b str r3, [r7, #20] pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; 800c2fc: 4b85 ldr r3, [pc, #532] @ (800c514 ) 800c2fe: 6a9b ldr r3, [r3, #40] @ 0x28 800c300: 091b lsrs r3, r3, #4 800c302: f003 033f and.w r3, r3, #63 @ 0x3f 800c306: 613b str r3, [r7, #16] pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); 800c308: 4b82 ldr r3, [pc, #520] @ (800c514 ) 800c30a: 6adb ldr r3, [r3, #44] @ 0x2c 800c30c: f003 0301 and.w r3, r3, #1 800c310: 60fb str r3, [r7, #12] fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800c312: 4b80 ldr r3, [pc, #512] @ (800c514 ) 800c314: 6b5b ldr r3, [r3, #52] @ 0x34 800c316: 08db lsrs r3, r3, #3 800c318: f3c3 030c ubfx r3, r3, #0, #13 800c31c: 68fa ldr r2, [r7, #12] 800c31e: fb02 f303 mul.w r3, r2, r3 800c322: ee07 3a90 vmov s15, r3 800c326: eef8 7a67 vcvt.f32.u32 s15, s15 800c32a: edc7 7a02 vstr s15, [r7, #8] if (pllm != 0U) 800c32e: 693b ldr r3, [r7, #16] 800c330: 2b00 cmp r3, #0 800c332: f000 80e1 beq.w 800c4f8 800c336: 697b ldr r3, [r7, #20] 800c338: 2b02 cmp r3, #2 800c33a: f000 8083 beq.w 800c444 800c33e: 697b ldr r3, [r7, #20] 800c340: 2b02 cmp r3, #2 800c342: f200 80a1 bhi.w 800c488 800c346: 697b ldr r3, [r7, #20] 800c348: 2b00 cmp r3, #0 800c34a: d003 beq.n 800c354 800c34c: 697b ldr r3, [r7, #20] 800c34e: 2b01 cmp r3, #1 800c350: d056 beq.n 800c400 800c352: e099 b.n 800c488 { switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800c354: 4b6f ldr r3, [pc, #444] @ (800c514 ) 800c356: 681b ldr r3, [r3, #0] 800c358: f003 0320 and.w r3, r3, #32 800c35c: 2b00 cmp r3, #0 800c35e: d02d beq.n 800c3bc { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800c360: 4b6c ldr r3, [pc, #432] @ (800c514 ) 800c362: 681b ldr r3, [r3, #0] 800c364: 08db lsrs r3, r3, #3 800c366: f003 0303 and.w r3, r3, #3 800c36a: 4a6b ldr r2, [pc, #428] @ (800c518 ) 800c36c: fa22 f303 lsr.w r3, r2, r3 800c370: 607b str r3, [r7, #4] pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c372: 687b ldr r3, [r7, #4] 800c374: ee07 3a90 vmov s15, r3 800c378: eef8 6a67 vcvt.f32.u32 s13, s15 800c37c: 693b ldr r3, [r7, #16] 800c37e: ee07 3a90 vmov s15, r3 800c382: eef8 7a67 vcvt.f32.u32 s15, s15 800c386: ee86 7aa7 vdiv.f32 s14, s13, s15 800c38a: 4b62 ldr r3, [pc, #392] @ (800c514 ) 800c38c: 6b1b ldr r3, [r3, #48] @ 0x30 800c38e: f3c3 0308 ubfx r3, r3, #0, #9 800c392: ee07 3a90 vmov s15, r3 800c396: eef8 6a67 vcvt.f32.u32 s13, s15 800c39a: ed97 6a02 vldr s12, [r7, #8] 800c39e: eddf 5a61 vldr s11, [pc, #388] @ 800c524 800c3a2: eec6 7a25 vdiv.f32 s15, s12, s11 800c3a6: ee76 7aa7 vadd.f32 s15, s13, s15 800c3aa: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c3ae: ee77 7aa6 vadd.f32 s15, s15, s13 800c3b2: ee67 7a27 vmul.f32 s15, s14, s15 800c3b6: edc7 7a07 vstr s15, [r7, #28] } else { pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 800c3ba: e087 b.n 800c4cc pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c3bc: 693b ldr r3, [r7, #16] 800c3be: ee07 3a90 vmov s15, r3 800c3c2: eef8 7a67 vcvt.f32.u32 s15, s15 800c3c6: eddf 6a58 vldr s13, [pc, #352] @ 800c528 800c3ca: ee86 7aa7 vdiv.f32 s14, s13, s15 800c3ce: 4b51 ldr r3, [pc, #324] @ (800c514 ) 800c3d0: 6b1b ldr r3, [r3, #48] @ 0x30 800c3d2: f3c3 0308 ubfx r3, r3, #0, #9 800c3d6: ee07 3a90 vmov s15, r3 800c3da: eef8 6a67 vcvt.f32.u32 s13, s15 800c3de: ed97 6a02 vldr s12, [r7, #8] 800c3e2: eddf 5a50 vldr s11, [pc, #320] @ 800c524 800c3e6: eec6 7a25 vdiv.f32 s15, s12, s11 800c3ea: ee76 7aa7 vadd.f32 s15, s13, s15 800c3ee: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c3f2: ee77 7aa6 vadd.f32 s15, s15, s13 800c3f6: ee67 7a27 vmul.f32 s15, s14, s15 800c3fa: edc7 7a07 vstr s15, [r7, #28] break; 800c3fe: e065 b.n 800c4cc case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c400: 693b ldr r3, [r7, #16] 800c402: ee07 3a90 vmov s15, r3 800c406: eef8 7a67 vcvt.f32.u32 s15, s15 800c40a: eddf 6a48 vldr s13, [pc, #288] @ 800c52c 800c40e: ee86 7aa7 vdiv.f32 s14, s13, s15 800c412: 4b40 ldr r3, [pc, #256] @ (800c514 ) 800c414: 6b1b ldr r3, [r3, #48] @ 0x30 800c416: f3c3 0308 ubfx r3, r3, #0, #9 800c41a: ee07 3a90 vmov s15, r3 800c41e: eef8 6a67 vcvt.f32.u32 s13, s15 800c422: ed97 6a02 vldr s12, [r7, #8] 800c426: eddf 5a3f vldr s11, [pc, #252] @ 800c524 800c42a: eec6 7a25 vdiv.f32 s15, s12, s11 800c42e: ee76 7aa7 vadd.f32 s15, s13, s15 800c432: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c436: ee77 7aa6 vadd.f32 s15, s15, s13 800c43a: ee67 7a27 vmul.f32 s15, s14, s15 800c43e: edc7 7a07 vstr s15, [r7, #28] break; 800c442: e043 b.n 800c4cc case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c444: 693b ldr r3, [r7, #16] 800c446: ee07 3a90 vmov s15, r3 800c44a: eef8 7a67 vcvt.f32.u32 s15, s15 800c44e: eddf 6a38 vldr s13, [pc, #224] @ 800c530 800c452: ee86 7aa7 vdiv.f32 s14, s13, s15 800c456: 4b2f ldr r3, [pc, #188] @ (800c514 ) 800c458: 6b1b ldr r3, [r3, #48] @ 0x30 800c45a: f3c3 0308 ubfx r3, r3, #0, #9 800c45e: ee07 3a90 vmov s15, r3 800c462: eef8 6a67 vcvt.f32.u32 s13, s15 800c466: ed97 6a02 vldr s12, [r7, #8] 800c46a: eddf 5a2e vldr s11, [pc, #184] @ 800c524 800c46e: eec6 7a25 vdiv.f32 s15, s12, s11 800c472: ee76 7aa7 vadd.f32 s15, s13, s15 800c476: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c47a: ee77 7aa6 vadd.f32 s15, s15, s13 800c47e: ee67 7a27 vmul.f32 s15, s14, s15 800c482: edc7 7a07 vstr s15, [r7, #28] break; 800c486: e021 b.n 800c4cc default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c488: 693b ldr r3, [r7, #16] 800c48a: ee07 3a90 vmov s15, r3 800c48e: eef8 7a67 vcvt.f32.u32 s15, s15 800c492: eddf 6a26 vldr s13, [pc, #152] @ 800c52c 800c496: ee86 7aa7 vdiv.f32 s14, s13, s15 800c49a: 4b1e ldr r3, [pc, #120] @ (800c514 ) 800c49c: 6b1b ldr r3, [r3, #48] @ 0x30 800c49e: f3c3 0308 ubfx r3, r3, #0, #9 800c4a2: ee07 3a90 vmov s15, r3 800c4a6: eef8 6a67 vcvt.f32.u32 s13, s15 800c4aa: ed97 6a02 vldr s12, [r7, #8] 800c4ae: eddf 5a1d vldr s11, [pc, #116] @ 800c524 800c4b2: eec6 7a25 vdiv.f32 s15, s12, s11 800c4b6: ee76 7aa7 vadd.f32 s15, s13, s15 800c4ba: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c4be: ee77 7aa6 vadd.f32 s15, s15, s13 800c4c2: ee67 7a27 vmul.f32 s15, s14, s15 800c4c6: edc7 7a07 vstr s15, [r7, #28] break; 800c4ca: bf00 nop } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; 800c4cc: 4b11 ldr r3, [pc, #68] @ (800c514 ) 800c4ce: 6b1b ldr r3, [r3, #48] @ 0x30 800c4d0: 0a5b lsrs r3, r3, #9 800c4d2: f003 037f and.w r3, r3, #127 @ 0x7f 800c4d6: 3301 adds r3, #1 800c4d8: 603b str r3, [r7, #0] sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); 800c4da: 683b ldr r3, [r7, #0] 800c4dc: ee07 3a90 vmov s15, r3 800c4e0: eeb8 7a67 vcvt.f32.u32 s14, s15 800c4e4: edd7 6a07 vldr s13, [r7, #28] 800c4e8: eec6 7a87 vdiv.f32 s15, s13, s14 800c4ec: eefc 7ae7 vcvt.u32.f32 s15, s15 800c4f0: ee17 3a90 vmov r3, s15 800c4f4: 61bb str r3, [r7, #24] } else { sysclockfreq = 0U; } break; 800c4f6: e005 b.n 800c504 sysclockfreq = 0U; 800c4f8: 2300 movs r3, #0 800c4fa: 61bb str r3, [r7, #24] break; 800c4fc: e002 b.n 800c504 default: sysclockfreq = CSI_VALUE; 800c4fe: 4b07 ldr r3, [pc, #28] @ (800c51c ) 800c500: 61bb str r3, [r7, #24] break; 800c502: bf00 nop } return sysclockfreq; 800c504: 69bb ldr r3, [r7, #24] } 800c506: 4618 mov r0, r3 800c508: 3724 adds r7, #36 @ 0x24 800c50a: 46bd mov sp, r7 800c50c: f85d 7b04 ldr.w r7, [sp], #4 800c510: 4770 bx lr 800c512: bf00 nop 800c514: 58024400 .word 0x58024400 800c518: 03d09000 .word 0x03d09000 800c51c: 003d0900 .word 0x003d0900 800c520: 017d7840 .word 0x017d7840 800c524: 46000000 .word 0x46000000 800c528: 4c742400 .word 0x4c742400 800c52c: 4a742400 .word 0x4a742400 800c530: 4bbebc20 .word 0x4bbebc20 0800c534 : * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 800c534: b580 push {r7, lr} 800c536: b082 sub sp, #8 800c538: af00 add r7, sp, #0 uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 800c53a: f7ff fe81 bl 800c240 800c53e: 4602 mov r2, r0 800c540: 4b10 ldr r3, [pc, #64] @ (800c584 ) 800c542: 699b ldr r3, [r3, #24] 800c544: 0a1b lsrs r3, r3, #8 800c546: f003 030f and.w r3, r3, #15 800c54a: 490f ldr r1, [pc, #60] @ (800c588 ) 800c54c: 5ccb ldrb r3, [r1, r3] 800c54e: f003 031f and.w r3, r3, #31 800c552: fa22 f303 lsr.w r3, r2, r3 800c556: 607b str r3, [r7, #4] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800c558: 4b0a ldr r3, [pc, #40] @ (800c584 ) 800c55a: 699b ldr r3, [r3, #24] 800c55c: f003 030f and.w r3, r3, #15 800c560: 4a09 ldr r2, [pc, #36] @ (800c588 ) 800c562: 5cd3 ldrb r3, [r2, r3] 800c564: f003 031f and.w r3, r3, #31 800c568: 687a ldr r2, [r7, #4] 800c56a: fa22 f303 lsr.w r3, r2, r3 800c56e: 4a07 ldr r2, [pc, #28] @ (800c58c ) 800c570: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 800c572: 4a07 ldr r2, [pc, #28] @ (800c590 ) 800c574: 687b ldr r3, [r7, #4] 800c576: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ return SystemD2Clock; 800c578: 4b04 ldr r3, [pc, #16] @ (800c58c ) 800c57a: 681b ldr r3, [r3, #0] } 800c57c: 4618 mov r0, r3 800c57e: 3708 adds r7, #8 800c580: 46bd mov sp, r7 800c582: bd80 pop {r7, pc} 800c584: 58024400 .word 0x58024400 800c588: 08018b5c .word 0x08018b5c 800c58c: 24000038 .word 0x24000038 800c590: 24000034 .word 0x24000034 0800c594 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 800c594: b580 push {r7, lr} 800c596: af00 add r7, sp, #0 #if defined (RCC_D2CFGR_D2PPRE1) /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); 800c598: f7ff ffcc bl 800c534 800c59c: 4602 mov r2, r0 800c59e: 4b06 ldr r3, [pc, #24] @ (800c5b8 ) 800c5a0: 69db ldr r3, [r3, #28] 800c5a2: 091b lsrs r3, r3, #4 800c5a4: f003 0307 and.w r3, r3, #7 800c5a8: 4904 ldr r1, [pc, #16] @ (800c5bc ) 800c5aa: 5ccb ldrb r3, [r1, r3] 800c5ac: f003 031f and.w r3, r3, #31 800c5b0: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); #endif } 800c5b4: 4618 mov r0, r3 800c5b6: bd80 pop {r7, pc} 800c5b8: 58024400 .word 0x58024400 800c5bc: 08018b5c .word 0x08018b5c 0800c5c0 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 800c5c0: b580 push {r7, lr} 800c5c2: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ #if defined(RCC_D2CFGR_D2PPRE2) return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); 800c5c4: f7ff ffb6 bl 800c534 800c5c8: 4602 mov r2, r0 800c5ca: 4b06 ldr r3, [pc, #24] @ (800c5e4 ) 800c5cc: 69db ldr r3, [r3, #28] 800c5ce: 0a1b lsrs r3, r3, #8 800c5d0: f003 0307 and.w r3, r3, #7 800c5d4: 4904 ldr r1, [pc, #16] @ (800c5e8 ) 800c5d6: 5ccb ldrb r3, [r1, r3] 800c5d8: f003 031f and.w r3, r3, #31 800c5dc: fa22 f303 lsr.w r3, r2, r3 #else return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); #endif } 800c5e0: 4618 mov r0, r3 800c5e2: bd80 pop {r7, pc} 800c5e4: 58024400 .word 0x58024400 800c5e8: 08018b5c .word 0x08018b5c 0800c5ec : * will be configured. * @param pFLatency: Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 800c5ec: b480 push {r7} 800c5ee: b083 sub sp, #12 800c5f0: af00 add r7, sp, #0 800c5f2: 6078 str r0, [r7, #4] 800c5f4: 6039 str r1, [r7, #0] /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | 800c5f6: 687b ldr r3, [r7, #4] 800c5f8: 223f movs r2, #63 @ 0x3f 800c5fa: 601a str r2, [r3, #0] RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ; /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 800c5fc: 4b1a ldr r3, [pc, #104] @ (800c668 ) 800c5fe: 691b ldr r3, [r3, #16] 800c600: f003 0207 and.w r2, r3, #7 800c604: 687b ldr r3, [r7, #4] 800c606: 605a str r2, [r3, #4] #if defined(RCC_D1CFGR_D1CPRE) /* Get the SYSCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE); 800c608: 4b17 ldr r3, [pc, #92] @ (800c668 ) 800c60a: 699b ldr r3, [r3, #24] 800c60c: f403 6270 and.w r2, r3, #3840 @ 0xf00 800c610: 687b ldr r3, [r7, #4] 800c612: 609a str r2, [r3, #8] /* Get the D1HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE); 800c614: 4b14 ldr r3, [pc, #80] @ (800c668 ) 800c616: 699b ldr r3, [r3, #24] 800c618: f003 020f and.w r2, r3, #15 800c61c: 687b ldr r3, [r7, #4] 800c61e: 60da str r2, [r3, #12] /* Get the APB3 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE); 800c620: 4b11 ldr r3, [pc, #68] @ (800c668 ) 800c622: 699b ldr r3, [r3, #24] 800c624: f003 0270 and.w r2, r3, #112 @ 0x70 800c628: 687b ldr r3, [r7, #4] 800c62a: 611a str r2, [r3, #16] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1); 800c62c: 4b0e ldr r3, [pc, #56] @ (800c668 ) 800c62e: 69db ldr r3, [r3, #28] 800c630: f003 0270 and.w r2, r3, #112 @ 0x70 800c634: 687b ldr r3, [r7, #4] 800c636: 615a str r2, [r3, #20] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2); 800c638: 4b0b ldr r3, [pc, #44] @ (800c668 ) 800c63a: 69db ldr r3, [r3, #28] 800c63c: f403 62e0 and.w r2, r3, #1792 @ 0x700 800c640: 687b ldr r3, [r7, #4] 800c642: 619a str r2, [r3, #24] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); 800c644: 4b08 ldr r3, [pc, #32] @ (800c668 ) 800c646: 6a1b ldr r3, [r3, #32] 800c648: f003 0270 and.w r2, r3, #112 @ 0x70 800c64c: 687b ldr r3, [r7, #4] 800c64e: 61da str r2, [r3, #28] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE); #endif /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 800c650: 4b06 ldr r3, [pc, #24] @ (800c66c ) 800c652: 681b ldr r3, [r3, #0] 800c654: f003 020f and.w r2, r3, #15 800c658: 683b ldr r3, [r7, #0] 800c65a: 601a str r2, [r3, #0] } 800c65c: bf00 nop 800c65e: 370c adds r7, #12 800c660: 46bd mov sp, r7 800c662: f85d 7b04 ldr.w r7, [sp], #4 800c666: 4770 bx lr 800c668: 58024400 .word 0x58024400 800c66c: 52002000 .word 0x52002000 0800c670 : * (*) : Available on some STM32H7 lines only. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 800c670: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 800c674: b0c8 sub sp, #288 @ 0x120 800c676: af00 add r7, sp, #0 800c678: f8c7 010c str.w r0, [r7, #268] @ 0x10c uint32_t tmpreg; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 800c67c: 2300 movs r3, #0 800c67e: f887 311f strb.w r3, [r7, #287] @ 0x11f HAL_StatusTypeDef status = HAL_OK; /* Final status */ 800c682: 2300 movs r3, #0 800c684: f887 311e strb.w r3, [r7, #286] @ 0x11e /*---------------------------- SPDIFRX configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 800c688: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c68c: e9d3 2300 ldrd r2, r3, [r3] 800c690: f002 6400 and.w r4, r2, #134217728 @ 0x8000000 800c694: 2500 movs r5, #0 800c696: ea54 0305 orrs.w r3, r4, r5 800c69a: d049 beq.n 800c730 { switch (PeriphClkInit->SpdifrxClockSelection) 800c69c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c6a0: 6e9b ldr r3, [r3, #104] @ 0x68 800c6a2: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800c6a6: d02f beq.n 800c708 800c6a8: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800c6ac: d828 bhi.n 800c700 800c6ae: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800c6b2: d01a beq.n 800c6ea 800c6b4: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800c6b8: d822 bhi.n 800c700 800c6ba: 2b00 cmp r3, #0 800c6bc: d003 beq.n 800c6c6 800c6be: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800c6c2: d007 beq.n 800c6d4 800c6c4: e01c b.n 800c700 { case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c6c6: 4bb8 ldr r3, [pc, #736] @ (800c9a8 ) 800c6c8: 6adb ldr r3, [r3, #44] @ 0x2c 800c6ca: 4ab7 ldr r2, [pc, #732] @ (800c9a8 ) 800c6cc: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c6d0: 62d3 str r3, [r2, #44] @ 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 800c6d2: e01a b.n 800c70a case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800c6d4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c6d8: 3308 adds r3, #8 800c6da: 2102 movs r1, #2 800c6dc: 4618 mov r0, r3 800c6de: f002 fb45 bl 800ed6c 800c6e2: 4603 mov r3, r0 800c6e4: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 800c6e8: e00f b.n 800c70a case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800c6ea: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c6ee: 3328 adds r3, #40 @ 0x28 800c6f0: 2102 movs r1, #2 800c6f2: 4618 mov r0, r3 800c6f4: f002 fbec bl 800eed0 800c6f8: 4603 mov r3, r0 800c6fa: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 800c6fe: e004 b.n 800c70a /* Internal OSC clock is used as source of SPDIFRX clock*/ /* SPDIFRX clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800c700: 2301 movs r3, #1 800c702: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c706: e000 b.n 800c70a break; 800c708: bf00 nop } if (ret == HAL_OK) 800c70a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c70e: 2b00 cmp r3, #0 800c710: d10a bne.n 800c728 { /* Set the source of SPDIFRX clock*/ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 800c712: 4ba5 ldr r3, [pc, #660] @ (800c9a8 ) 800c714: 6d1b ldr r3, [r3, #80] @ 0x50 800c716: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800c71a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c71e: 6e9b ldr r3, [r3, #104] @ 0x68 800c720: 4aa1 ldr r2, [pc, #644] @ (800c9a8 ) 800c722: 430b orrs r3, r1 800c724: 6513 str r3, [r2, #80] @ 0x50 800c726: e003 b.n 800c730 } else { /* set overall return value */ status = ret; 800c728: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c72c: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 800c730: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c734: e9d3 2300 ldrd r2, r3, [r3] 800c738: f402 7880 and.w r8, r2, #256 @ 0x100 800c73c: f04f 0900 mov.w r9, #0 800c740: ea58 0309 orrs.w r3, r8, r9 800c744: d047 beq.n 800c7d6 { switch (PeriphClkInit->Sai1ClockSelection) 800c746: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c74a: 6d9b ldr r3, [r3, #88] @ 0x58 800c74c: 2b04 cmp r3, #4 800c74e: d82a bhi.n 800c7a6 800c750: a201 add r2, pc, #4 @ (adr r2, 800c758 ) 800c752: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c756: bf00 nop 800c758: 0800c76d .word 0x0800c76d 800c75c: 0800c77b .word 0x0800c77b 800c760: 0800c791 .word 0x0800c791 800c764: 0800c7af .word 0x0800c7af 800c768: 0800c7af .word 0x0800c7af { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c76c: 4b8e ldr r3, [pc, #568] @ (800c9a8 ) 800c76e: 6adb ldr r3, [r3, #44] @ 0x2c 800c770: 4a8d ldr r2, [pc, #564] @ (800c9a8 ) 800c772: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c776: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800c778: e01a b.n 800c7b0 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800c77a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c77e: 3308 adds r3, #8 800c780: 2100 movs r1, #0 800c782: 4618 mov r0, r3 800c784: f002 faf2 bl 800ed6c 800c788: 4603 mov r3, r0 800c78a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800c78e: e00f b.n 800c7b0 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800c790: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c794: 3328 adds r3, #40 @ 0x28 800c796: 2100 movs r1, #0 800c798: 4618 mov r0, r3 800c79a: f002 fb99 bl 800eed0 800c79e: 4603 mov r3, r0 800c7a0: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800c7a4: e004 b.n 800c7b0 /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800c7a6: 2301 movs r3, #1 800c7a8: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c7ac: e000 b.n 800c7b0 break; 800c7ae: bf00 nop } if (ret == HAL_OK) 800c7b0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c7b4: 2b00 cmp r3, #0 800c7b6: d10a bne.n 800c7ce { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 800c7b8: 4b7b ldr r3, [pc, #492] @ (800c9a8 ) 800c7ba: 6d1b ldr r3, [r3, #80] @ 0x50 800c7bc: f023 0107 bic.w r1, r3, #7 800c7c0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c7c4: 6d9b ldr r3, [r3, #88] @ 0x58 800c7c6: 4a78 ldr r2, [pc, #480] @ (800c9a8 ) 800c7c8: 430b orrs r3, r1 800c7ca: 6513 str r3, [r2, #80] @ 0x50 800c7cc: e003 b.n 800c7d6 } else { /* set overall return value */ status = ret; 800c7ce: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c7d2: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #if defined(SAI3) /*---------------------------- SAI2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) 800c7d6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c7da: e9d3 2300 ldrd r2, r3, [r3] 800c7de: f402 7a00 and.w sl, r2, #512 @ 0x200 800c7e2: f04f 0b00 mov.w fp, #0 800c7e6: ea5a 030b orrs.w r3, sl, fp 800c7ea: d04c beq.n 800c886 { switch (PeriphClkInit->Sai23ClockSelection) 800c7ec: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c7f0: 6ddb ldr r3, [r3, #92] @ 0x5c 800c7f2: f5b3 7f80 cmp.w r3, #256 @ 0x100 800c7f6: d030 beq.n 800c85a 800c7f8: f5b3 7f80 cmp.w r3, #256 @ 0x100 800c7fc: d829 bhi.n 800c852 800c7fe: 2bc0 cmp r3, #192 @ 0xc0 800c800: d02d beq.n 800c85e 800c802: 2bc0 cmp r3, #192 @ 0xc0 800c804: d825 bhi.n 800c852 800c806: 2b80 cmp r3, #128 @ 0x80 800c808: d018 beq.n 800c83c 800c80a: 2b80 cmp r3, #128 @ 0x80 800c80c: d821 bhi.n 800c852 800c80e: 2b00 cmp r3, #0 800c810: d002 beq.n 800c818 800c812: 2b40 cmp r3, #64 @ 0x40 800c814: d007 beq.n 800c826 800c816: e01c b.n 800c852 { case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c818: 4b63 ldr r3, [pc, #396] @ (800c9a8 ) 800c81a: 6adb ldr r3, [r3, #44] @ 0x2c 800c81c: 4a62 ldr r2, [pc, #392] @ (800c9a8 ) 800c81e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c822: 62d3 str r3, [r2, #44] @ 0x2c /* SAI2/3 clock source configuration done later after clock selection check */ break; 800c824: e01c b.n 800c860 case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800c826: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c82a: 3308 adds r3, #8 800c82c: 2100 movs r1, #0 800c82e: 4618 mov r0, r3 800c830: f002 fa9c bl 800ed6c 800c834: 4603 mov r3, r0 800c836: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 800c83a: e011 b.n 800c860 case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800c83c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c840: 3328 adds r3, #40 @ 0x28 800c842: 2100 movs r1, #0 800c844: 4618 mov r0, r3 800c846: f002 fb43 bl 800eed0 800c84a: 4603 mov r3, r0 800c84c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 800c850: e006 b.n 800c860 /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ /* SAI2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800c852: 2301 movs r3, #1 800c854: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c858: e002 b.n 800c860 break; 800c85a: bf00 nop 800c85c: e000 b.n 800c860 break; 800c85e: bf00 nop } if (ret == HAL_OK) 800c860: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c864: 2b00 cmp r3, #0 800c866: d10a bne.n 800c87e { /* Set the source of SAI2/3 clock*/ __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); 800c868: 4b4f ldr r3, [pc, #316] @ (800c9a8 ) 800c86a: 6d1b ldr r3, [r3, #80] @ 0x50 800c86c: f423 71e0 bic.w r1, r3, #448 @ 0x1c0 800c870: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c874: 6ddb ldr r3, [r3, #92] @ 0x5c 800c876: 4a4c ldr r2, [pc, #304] @ (800c9a8 ) 800c878: 430b orrs r3, r1 800c87a: 6513 str r3, [r2, #80] @ 0x50 800c87c: e003 b.n 800c886 } else { /* set overall return value */ status = ret; 800c87e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c882: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI2B*/ #if defined(SAI4) /*---------------------------- SAI4A configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 800c886: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c88a: e9d3 2300 ldrd r2, r3, [r3] 800c88e: f402 6380 and.w r3, r2, #1024 @ 0x400 800c892: f8c7 3100 str.w r3, [r7, #256] @ 0x100 800c896: 2300 movs r3, #0 800c898: f8c7 3104 str.w r3, [r7, #260] @ 0x104 800c89c: e9d7 1240 ldrd r1, r2, [r7, #256] @ 0x100 800c8a0: 460b mov r3, r1 800c8a2: 4313 orrs r3, r2 800c8a4: d053 beq.n 800c94e { switch (PeriphClkInit->Sai4AClockSelection) 800c8a6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c8aa: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 800c8ae: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800c8b2: d035 beq.n 800c920 800c8b4: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800c8b8: d82e bhi.n 800c918 800c8ba: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800c8be: d031 beq.n 800c924 800c8c0: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800c8c4: d828 bhi.n 800c918 800c8c6: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800c8ca: d01a beq.n 800c902 800c8cc: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800c8d0: d822 bhi.n 800c918 800c8d2: 2b00 cmp r3, #0 800c8d4: d003 beq.n 800c8de 800c8d6: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800c8da: d007 beq.n 800c8ec 800c8dc: e01c b.n 800c918 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c8de: 4b32 ldr r3, [pc, #200] @ (800c9a8 ) 800c8e0: 6adb ldr r3, [r3, #44] @ 0x2c 800c8e2: 4a31 ldr r2, [pc, #196] @ (800c9a8 ) 800c8e4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c8e8: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800c8ea: e01c b.n 800c926 case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800c8ec: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c8f0: 3308 adds r3, #8 800c8f2: 2100 movs r1, #0 800c8f4: 4618 mov r0, r3 800c8f6: f002 fa39 bl 800ed6c 800c8fa: 4603 mov r3, r0 800c8fc: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800c900: e011 b.n 800c926 case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800c902: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c906: 3328 adds r3, #40 @ 0x28 800c908: 2100 movs r1, #0 800c90a: 4618 mov r0, r3 800c90c: f002 fae0 bl 800eed0 800c910: 4603 mov r3, r0 800c912: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800c916: e006 b.n 800c926 /* SAI4A clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800c918: 2301 movs r3, #1 800c91a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c91e: e002 b.n 800c926 break; 800c920: bf00 nop 800c922: e000 b.n 800c926 break; 800c924: bf00 nop } if (ret == HAL_OK) 800c926: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c92a: 2b00 cmp r3, #0 800c92c: d10b bne.n 800c946 { /* Set the source of SAI4A clock*/ __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); 800c92e: 4b1e ldr r3, [pc, #120] @ (800c9a8 ) 800c930: 6d9b ldr r3, [r3, #88] @ 0x58 800c932: f423 0160 bic.w r1, r3, #14680064 @ 0xe00000 800c936: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c93a: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 800c93e: 4a1a ldr r2, [pc, #104] @ (800c9a8 ) 800c940: 430b orrs r3, r1 800c942: 6593 str r3, [r2, #88] @ 0x58 800c944: e003 b.n 800c94e } else { /* set overall return value */ status = ret; 800c946: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c94a: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI4B configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 800c94e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c952: e9d3 2300 ldrd r2, r3, [r3] 800c956: f402 6300 and.w r3, r2, #2048 @ 0x800 800c95a: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 800c95e: 2300 movs r3, #0 800c960: f8c7 30fc str.w r3, [r7, #252] @ 0xfc 800c964: e9d7 123e ldrd r1, r2, [r7, #248] @ 0xf8 800c968: 460b mov r3, r1 800c96a: 4313 orrs r3, r2 800c96c: d056 beq.n 800ca1c { switch (PeriphClkInit->Sai4BClockSelection) 800c96e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c972: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 800c976: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800c97a: d038 beq.n 800c9ee 800c97c: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800c980: d831 bhi.n 800c9e6 800c982: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800c986: d034 beq.n 800c9f2 800c988: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800c98c: d82b bhi.n 800c9e6 800c98e: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800c992: d01d beq.n 800c9d0 800c994: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800c998: d825 bhi.n 800c9e6 800c99a: 2b00 cmp r3, #0 800c99c: d006 beq.n 800c9ac 800c99e: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800c9a2: d00a beq.n 800c9ba 800c9a4: e01f b.n 800c9e6 800c9a6: bf00 nop 800c9a8: 58024400 .word 0x58024400 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c9ac: 4ba2 ldr r3, [pc, #648] @ (800cc38 ) 800c9ae: 6adb ldr r3, [r3, #44] @ 0x2c 800c9b0: 4aa1 ldr r2, [pc, #644] @ (800cc38 ) 800c9b2: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c9b6: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800c9b8: e01c b.n 800c9f4 case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800c9ba: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c9be: 3308 adds r3, #8 800c9c0: 2100 movs r1, #0 800c9c2: 4618 mov r0, r3 800c9c4: f002 f9d2 bl 800ed6c 800c9c8: 4603 mov r3, r0 800c9ca: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800c9ce: e011 b.n 800c9f4 case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800c9d0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c9d4: 3328 adds r3, #40 @ 0x28 800c9d6: 2100 movs r1, #0 800c9d8: 4618 mov r0, r3 800c9da: f002 fa79 bl 800eed0 800c9de: 4603 mov r3, r0 800c9e0: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800c9e4: e006 b.n 800c9f4 /* SAI4B clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800c9e6: 2301 movs r3, #1 800c9e8: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c9ec: e002 b.n 800c9f4 break; 800c9ee: bf00 nop 800c9f0: e000 b.n 800c9f4 break; 800c9f2: bf00 nop } if (ret == HAL_OK) 800c9f4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c9f8: 2b00 cmp r3, #0 800c9fa: d10b bne.n 800ca14 { /* Set the source of SAI4B clock*/ __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); 800c9fc: 4b8e ldr r3, [pc, #568] @ (800cc38 ) 800c9fe: 6d9b ldr r3, [r3, #88] @ 0x58 800ca00: f023 61e0 bic.w r1, r3, #117440512 @ 0x7000000 800ca04: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca08: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 800ca0c: 4a8a ldr r2, [pc, #552] @ (800cc38 ) 800ca0e: 430b orrs r3, r1 800ca10: 6593 str r3, [r2, #88] @ 0x58 800ca12: e003 b.n 800ca1c } else { /* set overall return value */ status = ret; 800ca14: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ca18: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI4*/ #if defined(QUADSPI) /*---------------------------- QSPI configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) 800ca1c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca20: e9d3 2300 ldrd r2, r3, [r3] 800ca24: f002 7300 and.w r3, r2, #33554432 @ 0x2000000 800ca28: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0 800ca2c: 2300 movs r3, #0 800ca2e: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4 800ca32: e9d7 123c ldrd r1, r2, [r7, #240] @ 0xf0 800ca36: 460b mov r3, r1 800ca38: 4313 orrs r3, r2 800ca3a: d03a beq.n 800cab2 { switch (PeriphClkInit->QspiClockSelection) 800ca3c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca40: 6cdb ldr r3, [r3, #76] @ 0x4c 800ca42: 2b30 cmp r3, #48 @ 0x30 800ca44: d01f beq.n 800ca86 800ca46: 2b30 cmp r3, #48 @ 0x30 800ca48: d819 bhi.n 800ca7e 800ca4a: 2b20 cmp r3, #32 800ca4c: d00c beq.n 800ca68 800ca4e: 2b20 cmp r3, #32 800ca50: d815 bhi.n 800ca7e 800ca52: 2b00 cmp r3, #0 800ca54: d019 beq.n 800ca8a 800ca56: 2b10 cmp r3, #16 800ca58: d111 bne.n 800ca7e { case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ /* Enable QSPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800ca5a: 4b77 ldr r3, [pc, #476] @ (800cc38 ) 800ca5c: 6adb ldr r3, [r3, #44] @ 0x2c 800ca5e: 4a76 ldr r2, [pc, #472] @ (800cc38 ) 800ca60: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800ca64: 62d3 str r3, [r2, #44] @ 0x2c /* QSPI clock source configuration done later after clock selection check */ break; 800ca66: e011 b.n 800ca8c case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800ca68: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca6c: 3308 adds r3, #8 800ca6e: 2102 movs r1, #2 800ca70: 4618 mov r0, r3 800ca72: f002 f97b bl 800ed6c 800ca76: 4603 mov r3, r0 800ca78: f887 311f strb.w r3, [r7, #287] @ 0x11f /* QSPI clock source configuration done later after clock selection check */ break; 800ca7c: e006 b.n 800ca8c case RCC_QSPICLKSOURCE_D1HCLK: /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ break; default: ret = HAL_ERROR; 800ca7e: 2301 movs r3, #1 800ca80: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ca84: e002 b.n 800ca8c break; 800ca86: bf00 nop 800ca88: e000 b.n 800ca8c break; 800ca8a: bf00 nop } if (ret == HAL_OK) 800ca8c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ca90: 2b00 cmp r3, #0 800ca92: d10a bne.n 800caaa { /* Set the source of QSPI clock*/ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); 800ca94: 4b68 ldr r3, [pc, #416] @ (800cc38 ) 800ca96: 6cdb ldr r3, [r3, #76] @ 0x4c 800ca98: f023 0130 bic.w r1, r3, #48 @ 0x30 800ca9c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800caa0: 6cdb ldr r3, [r3, #76] @ 0x4c 800caa2: 4a65 ldr r2, [pc, #404] @ (800cc38 ) 800caa4: 430b orrs r3, r1 800caa6: 64d3 str r3, [r2, #76] @ 0x4c 800caa8: e003 b.n 800cab2 } else { /* set overall return value */ status = ret; 800caaa: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800caae: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 800cab2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cab6: e9d3 2300 ldrd r2, r3, [r3] 800caba: f402 5380 and.w r3, r2, #4096 @ 0x1000 800cabe: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 800cac2: 2300 movs r3, #0 800cac4: f8c7 30ec str.w r3, [r7, #236] @ 0xec 800cac8: e9d7 123a ldrd r1, r2, [r7, #232] @ 0xe8 800cacc: 460b mov r3, r1 800cace: 4313 orrs r3, r2 800cad0: d051 beq.n 800cb76 { switch (PeriphClkInit->Spi123ClockSelection) 800cad2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cad6: 6e1b ldr r3, [r3, #96] @ 0x60 800cad8: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800cadc: d035 beq.n 800cb4a 800cade: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800cae2: d82e bhi.n 800cb42 800cae4: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800cae8: d031 beq.n 800cb4e 800caea: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800caee: d828 bhi.n 800cb42 800caf0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800caf4: d01a beq.n 800cb2c 800caf6: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800cafa: d822 bhi.n 800cb42 800cafc: 2b00 cmp r3, #0 800cafe: d003 beq.n 800cb08 800cb00: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800cb04: d007 beq.n 800cb16 800cb06: e01c b.n 800cb42 { case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cb08: 4b4b ldr r3, [pc, #300] @ (800cc38 ) 800cb0a: 6adb ldr r3, [r3, #44] @ 0x2c 800cb0c: 4a4a ldr r2, [pc, #296] @ (800cc38 ) 800cb0e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cb12: 62d3 str r3, [r2, #44] @ 0x2c /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800cb14: e01c b.n 800cb50 case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800cb16: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb1a: 3308 adds r3, #8 800cb1c: 2100 movs r1, #0 800cb1e: 4618 mov r0, r3 800cb20: f002 f924 bl 800ed6c 800cb24: 4603 mov r3, r0 800cb26: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800cb2a: e011 b.n 800cb50 case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800cb2c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb30: 3328 adds r3, #40 @ 0x28 800cb32: 2100 movs r1, #0 800cb34: 4618 mov r0, r3 800cb36: f002 f9cb bl 800eed0 800cb3a: 4603 mov r3, r0 800cb3c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800cb40: e006 b.n 800cb50 /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ /* SPI1/2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cb42: 2301 movs r3, #1 800cb44: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cb48: e002 b.n 800cb50 break; 800cb4a: bf00 nop 800cb4c: e000 b.n 800cb50 break; 800cb4e: bf00 nop } if (ret == HAL_OK) 800cb50: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cb54: 2b00 cmp r3, #0 800cb56: d10a bne.n 800cb6e { /* Set the source of SPI1/2/3 clock*/ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 800cb58: 4b37 ldr r3, [pc, #220] @ (800cc38 ) 800cb5a: 6d1b ldr r3, [r3, #80] @ 0x50 800cb5c: f423 41e0 bic.w r1, r3, #28672 @ 0x7000 800cb60: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb64: 6e1b ldr r3, [r3, #96] @ 0x60 800cb66: 4a34 ldr r2, [pc, #208] @ (800cc38 ) 800cb68: 430b orrs r3, r1 800cb6a: 6513 str r3, [r2, #80] @ 0x50 800cb6c: e003 b.n 800cb76 } else { /* set overall return value */ status = ret; 800cb6e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cb72: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI4/5 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 800cb76: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb7a: e9d3 2300 ldrd r2, r3, [r3] 800cb7e: f402 5300 and.w r3, r2, #8192 @ 0x2000 800cb82: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 800cb86: 2300 movs r3, #0 800cb88: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 800cb8c: e9d7 1238 ldrd r1, r2, [r7, #224] @ 0xe0 800cb90: 460b mov r3, r1 800cb92: 4313 orrs r3, r2 800cb94: d056 beq.n 800cc44 { switch (PeriphClkInit->Spi45ClockSelection) 800cb96: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb9a: 6e5b ldr r3, [r3, #100] @ 0x64 800cb9c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800cba0: d033 beq.n 800cc0a 800cba2: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800cba6: d82c bhi.n 800cc02 800cba8: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800cbac: d02f beq.n 800cc0e 800cbae: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800cbb2: d826 bhi.n 800cc02 800cbb4: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800cbb8: d02b beq.n 800cc12 800cbba: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800cbbe: d820 bhi.n 800cc02 800cbc0: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800cbc4: d012 beq.n 800cbec 800cbc6: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800cbca: d81a bhi.n 800cc02 800cbcc: 2b00 cmp r3, #0 800cbce: d022 beq.n 800cc16 800cbd0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800cbd4: d115 bne.n 800cc02 /* SPI4/5 clock source configuration done later after clock selection check */ break; case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800cbd6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cbda: 3308 adds r3, #8 800cbdc: 2101 movs r1, #1 800cbde: 4618 mov r0, r3 800cbe0: f002 f8c4 bl 800ed6c 800cbe4: 4603 mov r3, r0 800cbe6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 800cbea: e015 b.n 800cc18 case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800cbec: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cbf0: 3328 adds r3, #40 @ 0x28 800cbf2: 2101 movs r1, #1 800cbf4: 4618 mov r0, r3 800cbf6: f002 f96b bl 800eed0 800cbfa: 4603 mov r3, r0 800cbfc: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 800cc00: e00a b.n 800cc18 /* HSE, oscillator is used as source of SPI4/5 clock */ /* SPI4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cc02: 2301 movs r3, #1 800cc04: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cc08: e006 b.n 800cc18 break; 800cc0a: bf00 nop 800cc0c: e004 b.n 800cc18 break; 800cc0e: bf00 nop 800cc10: e002 b.n 800cc18 break; 800cc12: bf00 nop 800cc14: e000 b.n 800cc18 break; 800cc16: bf00 nop } if (ret == HAL_OK) 800cc18: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cc1c: 2b00 cmp r3, #0 800cc1e: d10d bne.n 800cc3c { /* Set the source of SPI4/5 clock*/ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 800cc20: 4b05 ldr r3, [pc, #20] @ (800cc38 ) 800cc22: 6d1b ldr r3, [r3, #80] @ 0x50 800cc24: f423 21e0 bic.w r1, r3, #458752 @ 0x70000 800cc28: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc2c: 6e5b ldr r3, [r3, #100] @ 0x64 800cc2e: 4a02 ldr r2, [pc, #8] @ (800cc38 ) 800cc30: 430b orrs r3, r1 800cc32: 6513 str r3, [r2, #80] @ 0x50 800cc34: e006 b.n 800cc44 800cc36: bf00 nop 800cc38: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800cc3c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cc40: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI6 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 800cc44: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc48: e9d3 2300 ldrd r2, r3, [r3] 800cc4c: f402 4380 and.w r3, r2, #16384 @ 0x4000 800cc50: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 800cc54: 2300 movs r3, #0 800cc56: f8c7 30dc str.w r3, [r7, #220] @ 0xdc 800cc5a: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 800cc5e: 460b mov r3, r1 800cc60: 4313 orrs r3, r2 800cc62: d055 beq.n 800cd10 { switch (PeriphClkInit->Spi6ClockSelection) 800cc64: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc68: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 800cc6c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800cc70: d033 beq.n 800ccda 800cc72: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800cc76: d82c bhi.n 800ccd2 800cc78: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800cc7c: d02f beq.n 800ccde 800cc7e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800cc82: d826 bhi.n 800ccd2 800cc84: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800cc88: d02b beq.n 800cce2 800cc8a: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800cc8e: d820 bhi.n 800ccd2 800cc90: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cc94: d012 beq.n 800ccbc 800cc96: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cc9a: d81a bhi.n 800ccd2 800cc9c: 2b00 cmp r3, #0 800cc9e: d022 beq.n 800cce6 800cca0: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800cca4: d115 bne.n 800ccd2 /* SPI6 clock source configuration done later after clock selection check */ break; case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800cca6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ccaa: 3308 adds r3, #8 800ccac: 2101 movs r1, #1 800ccae: 4618 mov r0, r3 800ccb0: f002 f85c bl 800ed6c 800ccb4: 4603 mov r3, r0 800ccb6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 800ccba: e015 b.n 800cce8 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800ccbc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ccc0: 3328 adds r3, #40 @ 0x28 800ccc2: 2101 movs r1, #1 800ccc4: 4618 mov r0, r3 800ccc6: f002 f903 bl 800eed0 800ccca: 4603 mov r3, r0 800cccc: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 800ccd0: e00a b.n 800cce8 /* SPI6 clock source configuration done later after clock selection check */ break; #endif default: ret = HAL_ERROR; 800ccd2: 2301 movs r3, #1 800ccd4: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ccd8: e006 b.n 800cce8 break; 800ccda: bf00 nop 800ccdc: e004 b.n 800cce8 break; 800ccde: bf00 nop 800cce0: e002 b.n 800cce8 break; 800cce2: bf00 nop 800cce4: e000 b.n 800cce8 break; 800cce6: bf00 nop } if (ret == HAL_OK) 800cce8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ccec: 2b00 cmp r3, #0 800ccee: d10b bne.n 800cd08 { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 800ccf0: 4ba3 ldr r3, [pc, #652] @ (800cf80 ) 800ccf2: 6d9b ldr r3, [r3, #88] @ 0x58 800ccf4: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 800ccf8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ccfc: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 800cd00: 4a9f ldr r2, [pc, #636] @ (800cf80 ) 800cd02: 430b orrs r3, r1 800cd04: 6593 str r3, [r2, #88] @ 0x58 800cd06: e003 b.n 800cd10 } else { /* set overall return value */ status = ret; 800cd08: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cd0c: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*DSI*/ #if defined(FDCAN1) || defined(FDCAN2) /*---------------------------- FDCAN configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 800cd10: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd14: e9d3 2300 ldrd r2, r3, [r3] 800cd18: f402 4300 and.w r3, r2, #32768 @ 0x8000 800cd1c: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 800cd20: 2300 movs r3, #0 800cd22: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 800cd26: e9d7 1234 ldrd r1, r2, [r7, #208] @ 0xd0 800cd2a: 460b mov r3, r1 800cd2c: 4313 orrs r3, r2 800cd2e: d037 beq.n 800cda0 { switch (PeriphClkInit->FdcanClockSelection) 800cd30: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd34: 6f1b ldr r3, [r3, #112] @ 0x70 800cd36: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cd3a: d00e beq.n 800cd5a 800cd3c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cd40: d816 bhi.n 800cd70 800cd42: 2b00 cmp r3, #0 800cd44: d018 beq.n 800cd78 800cd46: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800cd4a: d111 bne.n 800cd70 { case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ /* Enable FDCAN Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cd4c: 4b8c ldr r3, [pc, #560] @ (800cf80 ) 800cd4e: 6adb ldr r3, [r3, #44] @ 0x2c 800cd50: 4a8b ldr r2, [pc, #556] @ (800cf80 ) 800cd52: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cd56: 62d3 str r3, [r2, #44] @ 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 800cd58: e00f b.n 800cd7a case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800cd5a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd5e: 3308 adds r3, #8 800cd60: 2101 movs r1, #1 800cd62: 4618 mov r0, r3 800cd64: f002 f802 bl 800ed6c 800cd68: 4603 mov r3, r0 800cd6a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FDCAN clock source configuration done later after clock selection check */ break; 800cd6e: e004 b.n 800cd7a /* HSE is used as clock source for FDCAN*/ /* FDCAN clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cd70: 2301 movs r3, #1 800cd72: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cd76: e000 b.n 800cd7a break; 800cd78: bf00 nop } if (ret == HAL_OK) 800cd7a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cd7e: 2b00 cmp r3, #0 800cd80: d10a bne.n 800cd98 { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 800cd82: 4b7f ldr r3, [pc, #508] @ (800cf80 ) 800cd84: 6d1b ldr r3, [r3, #80] @ 0x50 800cd86: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 800cd8a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd8e: 6f1b ldr r3, [r3, #112] @ 0x70 800cd90: 4a7b ldr r2, [pc, #492] @ (800cf80 ) 800cd92: 430b orrs r3, r1 800cd94: 6513 str r3, [r2, #80] @ 0x50 800cd96: e003 b.n 800cda0 } else { /* set overall return value */ status = ret; 800cd98: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cd9c: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*FDCAN1 || FDCAN2*/ /*---------------------------- FMC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 800cda0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cda4: e9d3 2300 ldrd r2, r3, [r3] 800cda8: f002 7380 and.w r3, r2, #16777216 @ 0x1000000 800cdac: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 800cdb0: 2300 movs r3, #0 800cdb2: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 800cdb6: e9d7 1232 ldrd r1, r2, [r7, #200] @ 0xc8 800cdba: 460b mov r3, r1 800cdbc: 4313 orrs r3, r2 800cdbe: d039 beq.n 800ce34 { switch (PeriphClkInit->FmcClockSelection) 800cdc0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cdc4: 6c9b ldr r3, [r3, #72] @ 0x48 800cdc6: 2b03 cmp r3, #3 800cdc8: d81c bhi.n 800ce04 800cdca: a201 add r2, pc, #4 @ (adr r2, 800cdd0 ) 800cdcc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800cdd0: 0800ce0d .word 0x0800ce0d 800cdd4: 0800cde1 .word 0x0800cde1 800cdd8: 0800cdef .word 0x0800cdef 800cddc: 0800ce0d .word 0x0800ce0d { case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ /* Enable FMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cde0: 4b67 ldr r3, [pc, #412] @ (800cf80 ) 800cde2: 6adb ldr r3, [r3, #44] @ 0x2c 800cde4: 4a66 ldr r2, [pc, #408] @ (800cf80 ) 800cde6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cdea: 62d3 str r3, [r2, #44] @ 0x2c /* FMC clock source configuration done later after clock selection check */ break; 800cdec: e00f b.n 800ce0e case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800cdee: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cdf2: 3308 adds r3, #8 800cdf4: 2102 movs r1, #2 800cdf6: 4618 mov r0, r3 800cdf8: f001 ffb8 bl 800ed6c 800cdfc: 4603 mov r3, r0 800cdfe: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FMC clock source configuration done later after clock selection check */ break; 800ce02: e004 b.n 800ce0e case RCC_FMCCLKSOURCE_HCLK: /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ break; default: ret = HAL_ERROR; 800ce04: 2301 movs r3, #1 800ce06: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ce0a: e000 b.n 800ce0e break; 800ce0c: bf00 nop } if (ret == HAL_OK) 800ce0e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ce12: 2b00 cmp r3, #0 800ce14: d10a bne.n 800ce2c { /* Set the source of FMC clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 800ce16: 4b5a ldr r3, [pc, #360] @ (800cf80 ) 800ce18: 6cdb ldr r3, [r3, #76] @ 0x4c 800ce1a: f023 0103 bic.w r1, r3, #3 800ce1e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce22: 6c9b ldr r3, [r3, #72] @ 0x48 800ce24: 4a56 ldr r2, [pc, #344] @ (800cf80 ) 800ce26: 430b orrs r3, r1 800ce28: 64d3 str r3, [r2, #76] @ 0x4c 800ce2a: e003 b.n 800ce34 } else { /* set overall return value */ status = ret; 800ce2c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ce30: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- RTC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 800ce34: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce38: e9d3 2300 ldrd r2, r3, [r3] 800ce3c: f402 0380 and.w r3, r2, #4194304 @ 0x400000 800ce40: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 800ce44: 2300 movs r3, #0 800ce46: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 800ce4a: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 800ce4e: 460b mov r3, r1 800ce50: 4313 orrs r3, r2 800ce52: f000 809f beq.w 800cf94 { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 800ce56: 4b4b ldr r3, [pc, #300] @ (800cf84 ) 800ce58: 681b ldr r3, [r3, #0] 800ce5a: 4a4a ldr r2, [pc, #296] @ (800cf84 ) 800ce5c: f443 7380 orr.w r3, r3, #256 @ 0x100 800ce60: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800ce62: f7f8 fea5 bl 8005bb0 800ce66: f8c7 0118 str.w r0, [r7, #280] @ 0x118 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800ce6a: e00b b.n 800ce84 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800ce6c: f7f8 fea0 bl 8005bb0 800ce70: 4602 mov r2, r0 800ce72: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 800ce76: 1ad3 subs r3, r2, r3 800ce78: 2b64 cmp r3, #100 @ 0x64 800ce7a: d903 bls.n 800ce84 { ret = HAL_TIMEOUT; 800ce7c: 2303 movs r3, #3 800ce7e: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ce82: e005 b.n 800ce90 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800ce84: 4b3f ldr r3, [pc, #252] @ (800cf84 ) 800ce86: 681b ldr r3, [r3, #0] 800ce88: f403 7380 and.w r3, r3, #256 @ 0x100 800ce8c: 2b00 cmp r3, #0 800ce8e: d0ed beq.n 800ce6c } } if (ret == HAL_OK) 800ce90: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ce94: 2b00 cmp r3, #0 800ce96: d179 bne.n 800cf8c { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 800ce98: 4b39 ldr r3, [pc, #228] @ (800cf80 ) 800ce9a: 6f1a ldr r2, [r3, #112] @ 0x70 800ce9c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cea0: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800cea4: 4053 eors r3, r2 800cea6: f403 7340 and.w r3, r3, #768 @ 0x300 800ceaa: 2b00 cmp r3, #0 800ceac: d015 beq.n 800ceda { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800ceae: 4b34 ldr r3, [pc, #208] @ (800cf80 ) 800ceb0: 6f1b ldr r3, [r3, #112] @ 0x70 800ceb2: f423 7340 bic.w r3, r3, #768 @ 0x300 800ceb6: f8c7 3114 str.w r3, [r7, #276] @ 0x114 /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 800ceba: 4b31 ldr r3, [pc, #196] @ (800cf80 ) 800cebc: 6f1b ldr r3, [r3, #112] @ 0x70 800cebe: 4a30 ldr r2, [pc, #192] @ (800cf80 ) 800cec0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800cec4: 6713 str r3, [r2, #112] @ 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 800cec6: 4b2e ldr r3, [pc, #184] @ (800cf80 ) 800cec8: 6f1b ldr r3, [r3, #112] @ 0x70 800ceca: 4a2d ldr r2, [pc, #180] @ (800cf80 ) 800cecc: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ced0: 6713 str r3, [r2, #112] @ 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg; 800ced2: 4a2b ldr r2, [pc, #172] @ (800cf80 ) 800ced4: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800ced8: 6713 str r3, [r2, #112] @ 0x70 } /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 800ceda: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cede: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800cee2: f5b3 7f80 cmp.w r3, #256 @ 0x100 800cee6: d118 bne.n 800cf1a { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800cee8: f7f8 fe62 bl 8005bb0 800ceec: f8c7 0118 str.w r0, [r7, #280] @ 0x118 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800cef0: e00d b.n 800cf0e { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800cef2: f7f8 fe5d bl 8005bb0 800cef6: 4602 mov r2, r0 800cef8: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 800cefc: 1ad2 subs r2, r2, r3 800cefe: f241 3388 movw r3, #5000 @ 0x1388 800cf02: 429a cmp r2, r3 800cf04: d903 bls.n 800cf0e { ret = HAL_TIMEOUT; 800cf06: 2303 movs r3, #3 800cf08: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cf0c: e005 b.n 800cf1a while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800cf0e: 4b1c ldr r3, [pc, #112] @ (800cf80 ) 800cf10: 6f1b ldr r3, [r3, #112] @ 0x70 800cf12: f003 0302 and.w r3, r3, #2 800cf16: 2b00 cmp r3, #0 800cf18: d0eb beq.n 800cef2 } } } if (ret == HAL_OK) 800cf1a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cf1e: 2b00 cmp r3, #0 800cf20: d129 bne.n 800cf76 { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 800cf22: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf26: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800cf2a: f403 7340 and.w r3, r3, #768 @ 0x300 800cf2e: f5b3 7f40 cmp.w r3, #768 @ 0x300 800cf32: d10e bne.n 800cf52 800cf34: 4b12 ldr r3, [pc, #72] @ (800cf80 ) 800cf36: 691b ldr r3, [r3, #16] 800cf38: f423 517c bic.w r1, r3, #16128 @ 0x3f00 800cf3c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf40: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800cf44: 091a lsrs r2, r3, #4 800cf46: 4b10 ldr r3, [pc, #64] @ (800cf88 ) 800cf48: 4013 ands r3, r2 800cf4a: 4a0d ldr r2, [pc, #52] @ (800cf80 ) 800cf4c: 430b orrs r3, r1 800cf4e: 6113 str r3, [r2, #16] 800cf50: e005 b.n 800cf5e 800cf52: 4b0b ldr r3, [pc, #44] @ (800cf80 ) 800cf54: 691b ldr r3, [r3, #16] 800cf56: 4a0a ldr r2, [pc, #40] @ (800cf80 ) 800cf58: f423 537c bic.w r3, r3, #16128 @ 0x3f00 800cf5c: 6113 str r3, [r2, #16] 800cf5e: 4b08 ldr r3, [pc, #32] @ (800cf80 ) 800cf60: 6f19 ldr r1, [r3, #112] @ 0x70 800cf62: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf66: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800cf6a: f3c3 030b ubfx r3, r3, #0, #12 800cf6e: 4a04 ldr r2, [pc, #16] @ (800cf80 ) 800cf70: 430b orrs r3, r1 800cf72: 6713 str r3, [r2, #112] @ 0x70 800cf74: e00e b.n 800cf94 } else { /* set overall return value */ status = ret; 800cf76: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cf7a: f887 311e strb.w r3, [r7, #286] @ 0x11e 800cf7e: e009 b.n 800cf94 800cf80: 58024400 .word 0x58024400 800cf84: 58024800 .word 0x58024800 800cf88: 00ffffcf .word 0x00ffffcf } } else { /* set overall return value */ status = ret; 800cf8c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cf90: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART1/6 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 800cf94: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf98: e9d3 2300 ldrd r2, r3, [r3] 800cf9c: f002 0301 and.w r3, r2, #1 800cfa0: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 800cfa4: 2300 movs r3, #0 800cfa6: f8c7 30bc str.w r3, [r7, #188] @ 0xbc 800cfaa: e9d7 122e ldrd r1, r2, [r7, #184] @ 0xb8 800cfae: 460b mov r3, r1 800cfb0: 4313 orrs r3, r2 800cfb2: f000 8089 beq.w 800d0c8 { switch (PeriphClkInit->Usart16ClockSelection) 800cfb6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cfba: 6fdb ldr r3, [r3, #124] @ 0x7c 800cfbc: 2b28 cmp r3, #40 @ 0x28 800cfbe: d86b bhi.n 800d098 800cfc0: a201 add r2, pc, #4 @ (adr r2, 800cfc8 ) 800cfc2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800cfc6: bf00 nop 800cfc8: 0800d0a1 .word 0x0800d0a1 800cfcc: 0800d099 .word 0x0800d099 800cfd0: 0800d099 .word 0x0800d099 800cfd4: 0800d099 .word 0x0800d099 800cfd8: 0800d099 .word 0x0800d099 800cfdc: 0800d099 .word 0x0800d099 800cfe0: 0800d099 .word 0x0800d099 800cfe4: 0800d099 .word 0x0800d099 800cfe8: 0800d06d .word 0x0800d06d 800cfec: 0800d099 .word 0x0800d099 800cff0: 0800d099 .word 0x0800d099 800cff4: 0800d099 .word 0x0800d099 800cff8: 0800d099 .word 0x0800d099 800cffc: 0800d099 .word 0x0800d099 800d000: 0800d099 .word 0x0800d099 800d004: 0800d099 .word 0x0800d099 800d008: 0800d083 .word 0x0800d083 800d00c: 0800d099 .word 0x0800d099 800d010: 0800d099 .word 0x0800d099 800d014: 0800d099 .word 0x0800d099 800d018: 0800d099 .word 0x0800d099 800d01c: 0800d099 .word 0x0800d099 800d020: 0800d099 .word 0x0800d099 800d024: 0800d099 .word 0x0800d099 800d028: 0800d0a1 .word 0x0800d0a1 800d02c: 0800d099 .word 0x0800d099 800d030: 0800d099 .word 0x0800d099 800d034: 0800d099 .word 0x0800d099 800d038: 0800d099 .word 0x0800d099 800d03c: 0800d099 .word 0x0800d099 800d040: 0800d099 .word 0x0800d099 800d044: 0800d099 .word 0x0800d099 800d048: 0800d0a1 .word 0x0800d0a1 800d04c: 0800d099 .word 0x0800d099 800d050: 0800d099 .word 0x0800d099 800d054: 0800d099 .word 0x0800d099 800d058: 0800d099 .word 0x0800d099 800d05c: 0800d099 .word 0x0800d099 800d060: 0800d099 .word 0x0800d099 800d064: 0800d099 .word 0x0800d099 800d068: 0800d0a1 .word 0x0800d0a1 case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ /* USART1/6 clock source configuration done later after clock selection check */ break; case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d06c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d070: 3308 adds r3, #8 800d072: 2101 movs r1, #1 800d074: 4618 mov r0, r3 800d076: f001 fe79 bl 800ed6c 800d07a: 4603 mov r3, r0 800d07c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 800d080: e00f b.n 800d0a2 case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d082: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d086: 3328 adds r3, #40 @ 0x28 800d088: 2101 movs r1, #1 800d08a: 4618 mov r0, r3 800d08c: f001 ff20 bl 800eed0 800d090: 4603 mov r3, r0 800d092: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 800d096: e004 b.n 800d0a2 /* LSE, oscillator is used as source of USART1/6 clock */ /* USART1/6 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d098: 2301 movs r3, #1 800d09a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d09e: e000 b.n 800d0a2 break; 800d0a0: bf00 nop } if (ret == HAL_OK) 800d0a2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d0a6: 2b00 cmp r3, #0 800d0a8: d10a bne.n 800d0c0 { /* Set the source of USART1/6 clock */ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 800d0aa: 4bbf ldr r3, [pc, #764] @ (800d3a8 ) 800d0ac: 6d5b ldr r3, [r3, #84] @ 0x54 800d0ae: f023 0138 bic.w r1, r3, #56 @ 0x38 800d0b2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0b6: 6fdb ldr r3, [r3, #124] @ 0x7c 800d0b8: 4abb ldr r2, [pc, #748] @ (800d3a8 ) 800d0ba: 430b orrs r3, r1 800d0bc: 6553 str r3, [r2, #84] @ 0x54 800d0be: e003 b.n 800d0c8 } else { /* set overall return value */ status = ret; 800d0c0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d0c4: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 800d0c8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0cc: e9d3 2300 ldrd r2, r3, [r3] 800d0d0: f002 0302 and.w r3, r2, #2 800d0d4: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 800d0d8: 2300 movs r3, #0 800d0da: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 800d0de: e9d7 122c ldrd r1, r2, [r7, #176] @ 0xb0 800d0e2: 460b mov r3, r1 800d0e4: 4313 orrs r3, r2 800d0e6: d041 beq.n 800d16c { switch (PeriphClkInit->Usart234578ClockSelection) 800d0e8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0ec: 6f9b ldr r3, [r3, #120] @ 0x78 800d0ee: 2b05 cmp r3, #5 800d0f0: d824 bhi.n 800d13c 800d0f2: a201 add r2, pc, #4 @ (adr r2, 800d0f8 ) 800d0f4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d0f8: 0800d145 .word 0x0800d145 800d0fc: 0800d111 .word 0x0800d111 800d100: 0800d127 .word 0x0800d127 800d104: 0800d145 .word 0x0800d145 800d108: 0800d145 .word 0x0800d145 800d10c: 0800d145 .word 0x0800d145 case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d110: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d114: 3308 adds r3, #8 800d116: 2101 movs r1, #1 800d118: 4618 mov r0, r3 800d11a: f001 fe27 bl 800ed6c 800d11e: 4603 mov r3, r0 800d120: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 800d124: e00f b.n 800d146 case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d126: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d12a: 3328 adds r3, #40 @ 0x28 800d12c: 2101 movs r1, #1 800d12e: 4618 mov r0, r3 800d130: f001 fece bl 800eed0 800d134: 4603 mov r3, r0 800d136: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 800d13a: e004 b.n 800d146 /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d13c: 2301 movs r3, #1 800d13e: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d142: e000 b.n 800d146 break; 800d144: bf00 nop } if (ret == HAL_OK) 800d146: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d14a: 2b00 cmp r3, #0 800d14c: d10a bne.n 800d164 { /* Set the source of USART2/3/4/5/7/8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 800d14e: 4b96 ldr r3, [pc, #600] @ (800d3a8 ) 800d150: 6d5b ldr r3, [r3, #84] @ 0x54 800d152: f023 0107 bic.w r1, r3, #7 800d156: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d15a: 6f9b ldr r3, [r3, #120] @ 0x78 800d15c: 4a92 ldr r2, [pc, #584] @ (800d3a8 ) 800d15e: 430b orrs r3, r1 800d160: 6553 str r3, [r2, #84] @ 0x54 800d162: e003 b.n 800d16c } else { /* set overall return value */ status = ret; 800d164: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d168: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- LPUART1 Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 800d16c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d170: e9d3 2300 ldrd r2, r3, [r3] 800d174: f002 0304 and.w r3, r2, #4 800d178: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 800d17c: 2300 movs r3, #0 800d17e: f8c7 30ac str.w r3, [r7, #172] @ 0xac 800d182: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 800d186: 460b mov r3, r1 800d188: 4313 orrs r3, r2 800d18a: d044 beq.n 800d216 { switch (PeriphClkInit->Lpuart1ClockSelection) 800d18c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d190: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800d194: 2b05 cmp r3, #5 800d196: d825 bhi.n 800d1e4 800d198: a201 add r2, pc, #4 @ (adr r2, 800d1a0 ) 800d19a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d19e: bf00 nop 800d1a0: 0800d1ed .word 0x0800d1ed 800d1a4: 0800d1b9 .word 0x0800d1b9 800d1a8: 0800d1cf .word 0x0800d1cf 800d1ac: 0800d1ed .word 0x0800d1ed 800d1b0: 0800d1ed .word 0x0800d1ed 800d1b4: 0800d1ed .word 0x0800d1ed case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d1b8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d1bc: 3308 adds r3, #8 800d1be: 2101 movs r1, #1 800d1c0: 4618 mov r0, r3 800d1c2: f001 fdd3 bl 800ed6c 800d1c6: 4603 mov r3, r0 800d1c8: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 800d1cc: e00f b.n 800d1ee case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d1ce: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d1d2: 3328 adds r3, #40 @ 0x28 800d1d4: 2101 movs r1, #1 800d1d6: 4618 mov r0, r3 800d1d8: f001 fe7a bl 800eed0 800d1dc: 4603 mov r3, r0 800d1de: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 800d1e2: e004 b.n 800d1ee /* LSE, oscillator is used as source of LPUART1 clock */ /* LPUART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d1e4: 2301 movs r3, #1 800d1e6: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d1ea: e000 b.n 800d1ee break; 800d1ec: bf00 nop } if (ret == HAL_OK) 800d1ee: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d1f2: 2b00 cmp r3, #0 800d1f4: d10b bne.n 800d20e { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 800d1f6: 4b6c ldr r3, [pc, #432] @ (800d3a8 ) 800d1f8: 6d9b ldr r3, [r3, #88] @ 0x58 800d1fa: f023 0107 bic.w r1, r3, #7 800d1fe: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d202: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800d206: 4a68 ldr r2, [pc, #416] @ (800d3a8 ) 800d208: 430b orrs r3, r1 800d20a: 6593 str r3, [r2, #88] @ 0x58 800d20c: e003 b.n 800d216 } else { /* set overall return value */ status = ret; 800d20e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d212: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 800d216: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d21a: e9d3 2300 ldrd r2, r3, [r3] 800d21e: f002 0320 and.w r3, r2, #32 800d222: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 800d226: 2300 movs r3, #0 800d228: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 800d22c: e9d7 1228 ldrd r1, r2, [r7, #160] @ 0xa0 800d230: 460b mov r3, r1 800d232: 4313 orrs r3, r2 800d234: d055 beq.n 800d2e2 { switch (PeriphClkInit->Lptim1ClockSelection) 800d236: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d23a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800d23e: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800d242: d033 beq.n 800d2ac 800d244: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800d248: d82c bhi.n 800d2a4 800d24a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800d24e: d02f beq.n 800d2b0 800d250: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800d254: d826 bhi.n 800d2a4 800d256: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800d25a: d02b beq.n 800d2b4 800d25c: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800d260: d820 bhi.n 800d2a4 800d262: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d266: d012 beq.n 800d28e 800d268: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d26c: d81a bhi.n 800d2a4 800d26e: 2b00 cmp r3, #0 800d270: d022 beq.n 800d2b8 800d272: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800d276: d115 bne.n 800d2a4 /* LPTIM1 clock source configuration done later after clock selection check */ break; case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d278: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d27c: 3308 adds r3, #8 800d27e: 2100 movs r1, #0 800d280: 4618 mov r0, r3 800d282: f001 fd73 bl 800ed6c 800d286: 4603 mov r3, r0 800d288: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 800d28c: e015 b.n 800d2ba case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d28e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d292: 3328 adds r3, #40 @ 0x28 800d294: 2102 movs r1, #2 800d296: 4618 mov r0, r3 800d298: f001 fe1a bl 800eed0 800d29c: 4603 mov r3, r0 800d29e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 800d2a2: e00a b.n 800d2ba /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ /* LPTIM1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d2a4: 2301 movs r3, #1 800d2a6: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d2aa: e006 b.n 800d2ba break; 800d2ac: bf00 nop 800d2ae: e004 b.n 800d2ba break; 800d2b0: bf00 nop 800d2b2: e002 b.n 800d2ba break; 800d2b4: bf00 nop 800d2b6: e000 b.n 800d2ba break; 800d2b8: bf00 nop } if (ret == HAL_OK) 800d2ba: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d2be: 2b00 cmp r3, #0 800d2c0: d10b bne.n 800d2da { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 800d2c2: 4b39 ldr r3, [pc, #228] @ (800d3a8 ) 800d2c4: 6d5b ldr r3, [r3, #84] @ 0x54 800d2c6: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 800d2ca: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d2ce: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800d2d2: 4a35 ldr r2, [pc, #212] @ (800d3a8 ) 800d2d4: 430b orrs r3, r1 800d2d6: 6553 str r3, [r2, #84] @ 0x54 800d2d8: e003 b.n 800d2e2 } else { /* set overall return value */ status = ret; 800d2da: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d2de: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 800d2e2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d2e6: e9d3 2300 ldrd r2, r3, [r3] 800d2ea: f002 0340 and.w r3, r2, #64 @ 0x40 800d2ee: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800d2f2: 2300 movs r3, #0 800d2f4: f8c7 309c str.w r3, [r7, #156] @ 0x9c 800d2f8: e9d7 1226 ldrd r1, r2, [r7, #152] @ 0x98 800d2fc: 460b mov r3, r1 800d2fe: 4313 orrs r3, r2 800d300: d058 beq.n 800d3b4 { switch (PeriphClkInit->Lptim2ClockSelection) 800d302: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d306: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800d30a: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800d30e: d033 beq.n 800d378 800d310: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800d314: d82c bhi.n 800d370 800d316: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d31a: d02f beq.n 800d37c 800d31c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d320: d826 bhi.n 800d370 800d322: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 800d326: d02b beq.n 800d380 800d328: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 800d32c: d820 bhi.n 800d370 800d32e: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800d332: d012 beq.n 800d35a 800d334: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800d338: d81a bhi.n 800d370 800d33a: 2b00 cmp r3, #0 800d33c: d022 beq.n 800d384 800d33e: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800d342: d115 bne.n 800d370 /* LPTIM2 clock source configuration done later after clock selection check */ break; case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d344: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d348: 3308 adds r3, #8 800d34a: 2100 movs r1, #0 800d34c: 4618 mov r0, r3 800d34e: f001 fd0d bl 800ed6c 800d352: 4603 mov r3, r0 800d354: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 800d358: e015 b.n 800d386 case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d35a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d35e: 3328 adds r3, #40 @ 0x28 800d360: 2102 movs r1, #2 800d362: 4618 mov r0, r3 800d364: f001 fdb4 bl 800eed0 800d368: 4603 mov r3, r0 800d36a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 800d36e: e00a b.n 800d386 /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ /* LPTIM2 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d370: 2301 movs r3, #1 800d372: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d376: e006 b.n 800d386 break; 800d378: bf00 nop 800d37a: e004 b.n 800d386 break; 800d37c: bf00 nop 800d37e: e002 b.n 800d386 break; 800d380: bf00 nop 800d382: e000 b.n 800d386 break; 800d384: bf00 nop } if (ret == HAL_OK) 800d386: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d38a: 2b00 cmp r3, #0 800d38c: d10e bne.n 800d3ac { /* Set the source of LPTIM2 clock*/ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 800d38e: 4b06 ldr r3, [pc, #24] @ (800d3a8 ) 800d390: 6d9b ldr r3, [r3, #88] @ 0x58 800d392: f423 51e0 bic.w r1, r3, #7168 @ 0x1c00 800d396: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d39a: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800d39e: 4a02 ldr r2, [pc, #8] @ (800d3a8 ) 800d3a0: 430b orrs r3, r1 800d3a2: 6593 str r3, [r2, #88] @ 0x58 800d3a4: e006 b.n 800d3b4 800d3a6: bf00 nop 800d3a8: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800d3ac: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d3b0: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM345 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 800d3b4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d3b8: e9d3 2300 ldrd r2, r3, [r3] 800d3bc: f002 0380 and.w r3, r2, #128 @ 0x80 800d3c0: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800d3c4: 2300 movs r3, #0 800d3c6: f8c7 3094 str.w r3, [r7, #148] @ 0x94 800d3ca: e9d7 1224 ldrd r1, r2, [r7, #144] @ 0x90 800d3ce: 460b mov r3, r1 800d3d0: 4313 orrs r3, r2 800d3d2: d055 beq.n 800d480 { switch (PeriphClkInit->Lptim345ClockSelection) 800d3d4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d3d8: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800d3dc: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 800d3e0: d033 beq.n 800d44a 800d3e2: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 800d3e6: d82c bhi.n 800d442 800d3e8: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800d3ec: d02f beq.n 800d44e 800d3ee: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800d3f2: d826 bhi.n 800d442 800d3f4: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800d3f8: d02b beq.n 800d452 800d3fa: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800d3fe: d820 bhi.n 800d442 800d400: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800d404: d012 beq.n 800d42c 800d406: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800d40a: d81a bhi.n 800d442 800d40c: 2b00 cmp r3, #0 800d40e: d022 beq.n 800d456 800d410: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800d414: d115 bne.n 800d442 case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d416: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d41a: 3308 adds r3, #8 800d41c: 2100 movs r1, #0 800d41e: 4618 mov r0, r3 800d420: f001 fca4 bl 800ed6c 800d424: 4603 mov r3, r0 800d426: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800d42a: e015 b.n 800d458 case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d42c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d430: 3328 adds r3, #40 @ 0x28 800d432: 2102 movs r1, #2 800d434: 4618 mov r0, r3 800d436: f001 fd4b bl 800eed0 800d43a: 4603 mov r3, r0 800d43c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800d440: e00a b.n 800d458 /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d442: 2301 movs r3, #1 800d444: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d448: e006 b.n 800d458 break; 800d44a: bf00 nop 800d44c: e004 b.n 800d458 break; 800d44e: bf00 nop 800d450: e002 b.n 800d458 break; 800d452: bf00 nop 800d454: e000 b.n 800d458 break; 800d456: bf00 nop } if (ret == HAL_OK) 800d458: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d45c: 2b00 cmp r3, #0 800d45e: d10b bne.n 800d478 { /* Set the source of LPTIM3/4/5 clock */ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 800d460: 4bbb ldr r3, [pc, #748] @ (800d750 ) 800d462: 6d9b ldr r3, [r3, #88] @ 0x58 800d464: f423 4160 bic.w r1, r3, #57344 @ 0xe000 800d468: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d46c: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800d470: 4ab7 ldr r2, [pc, #732] @ (800d750 ) 800d472: 430b orrs r3, r1 800d474: 6593 str r3, [r2, #88] @ 0x58 800d476: e003 b.n 800d480 } else { /* set overall return value */ status = ret; 800d478: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d47c: f887 311e strb.w r3, [r7, #286] @ 0x11e __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); } #else if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 800d480: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d484: e9d3 2300 ldrd r2, r3, [r3] 800d488: f002 0308 and.w r3, r2, #8 800d48c: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800d490: 2300 movs r3, #0 800d492: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800d496: e9d7 1222 ldrd r1, r2, [r7, #136] @ 0x88 800d49a: 460b mov r3, r1 800d49c: 4313 orrs r3, r2 800d49e: d01e beq.n 800d4de { /* Check the parameters */ assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3) 800d4a0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d4a4: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800d4a8: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d4ac: d10c bne.n 800d4c8 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800d4ae: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d4b2: 3328 adds r3, #40 @ 0x28 800d4b4: 2102 movs r1, #2 800d4b6: 4618 mov r0, r3 800d4b8: f001 fd0a bl 800eed0 800d4bc: 4603 mov r3, r0 800d4be: 2b00 cmp r3, #0 800d4c0: d002 beq.n 800d4c8 { status = HAL_ERROR; 800d4c2: 2301 movs r3, #1 800d4c4: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 800d4c8: 4ba1 ldr r3, [pc, #644] @ (800d750 ) 800d4ca: 6d5b ldr r3, [r3, #84] @ 0x54 800d4cc: f423 5140 bic.w r1, r3, #12288 @ 0x3000 800d4d0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d4d4: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800d4d8: 4a9d ldr r2, [pc, #628] @ (800d750 ) 800d4da: 430b orrs r3, r1 800d4dc: 6553 str r3, [r2, #84] @ 0x54 } #endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 800d4de: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d4e2: e9d3 2300 ldrd r2, r3, [r3] 800d4e6: f002 0310 and.w r3, r2, #16 800d4ea: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800d4ee: 2300 movs r3, #0 800d4f0: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800d4f4: e9d7 1220 ldrd r1, r2, [r7, #128] @ 0x80 800d4f8: 460b mov r3, r1 800d4fa: 4313 orrs r3, r2 800d4fc: d01e beq.n 800d53c { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) 800d4fe: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d502: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800d506: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d50a: d10c bne.n 800d526 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800d50c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d510: 3328 adds r3, #40 @ 0x28 800d512: 2102 movs r1, #2 800d514: 4618 mov r0, r3 800d516: f001 fcdb bl 800eed0 800d51a: 4603 mov r3, r0 800d51c: 2b00 cmp r3, #0 800d51e: d002 beq.n 800d526 { status = HAL_ERROR; 800d520: 2301 movs r3, #1 800d522: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 800d526: 4b8a ldr r3, [pc, #552] @ (800d750 ) 800d528: 6d9b ldr r3, [r3, #88] @ 0x58 800d52a: f423 7140 bic.w r1, r3, #768 @ 0x300 800d52e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d532: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800d536: 4a86 ldr r2, [pc, #536] @ (800d750 ) 800d538: 430b orrs r3, r1 800d53a: 6593 str r3, [r2, #88] @ 0x58 } /*---------------------------- ADC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 800d53c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d540: e9d3 2300 ldrd r2, r3, [r3] 800d544: f402 2300 and.w r3, r2, #524288 @ 0x80000 800d548: 67bb str r3, [r7, #120] @ 0x78 800d54a: 2300 movs r3, #0 800d54c: 67fb str r3, [r7, #124] @ 0x7c 800d54e: e9d7 121e ldrd r1, r2, [r7, #120] @ 0x78 800d552: 460b mov r3, r1 800d554: 4313 orrs r3, r2 800d556: d03e beq.n 800d5d6 { switch (PeriphClkInit->AdcClockSelection) 800d558: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d55c: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 800d560: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d564: d022 beq.n 800d5ac 800d566: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d56a: d81b bhi.n 800d5a4 800d56c: 2b00 cmp r3, #0 800d56e: d003 beq.n 800d578 800d570: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800d574: d00b beq.n 800d58e 800d576: e015 b.n 800d5a4 { case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d578: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d57c: 3308 adds r3, #8 800d57e: 2100 movs r1, #0 800d580: 4618 mov r0, r3 800d582: f001 fbf3 bl 800ed6c 800d586: 4603 mov r3, r0 800d588: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 800d58c: e00f b.n 800d5ae case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d58e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d592: 3328 adds r3, #40 @ 0x28 800d594: 2102 movs r1, #2 800d596: 4618 mov r0, r3 800d598: f001 fc9a bl 800eed0 800d59c: 4603 mov r3, r0 800d59e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 800d5a2: e004 b.n 800d5ae /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ /* ADC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d5a4: 2301 movs r3, #1 800d5a6: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d5aa: e000 b.n 800d5ae break; 800d5ac: bf00 nop } if (ret == HAL_OK) 800d5ae: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d5b2: 2b00 cmp r3, #0 800d5b4: d10b bne.n 800d5ce { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 800d5b6: 4b66 ldr r3, [pc, #408] @ (800d750 ) 800d5b8: 6d9b ldr r3, [r3, #88] @ 0x58 800d5ba: f423 3140 bic.w r1, r3, #196608 @ 0x30000 800d5be: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d5c2: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 800d5c6: 4a62 ldr r2, [pc, #392] @ (800d750 ) 800d5c8: 430b orrs r3, r1 800d5ca: 6593 str r3, [r2, #88] @ 0x58 800d5cc: e003 b.n 800d5d6 } else { /* set overall return value */ status = ret; 800d5ce: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d5d2: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ USB Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 800d5d6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d5da: e9d3 2300 ldrd r2, r3, [r3] 800d5de: f402 2380 and.w r3, r2, #262144 @ 0x40000 800d5e2: 673b str r3, [r7, #112] @ 0x70 800d5e4: 2300 movs r3, #0 800d5e6: 677b str r3, [r7, #116] @ 0x74 800d5e8: e9d7 121c ldrd r1, r2, [r7, #112] @ 0x70 800d5ec: 460b mov r3, r1 800d5ee: 4313 orrs r3, r2 800d5f0: d03b beq.n 800d66a { switch (PeriphClkInit->UsbClockSelection) 800d5f2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d5f6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800d5fa: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800d5fe: d01f beq.n 800d640 800d600: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800d604: d818 bhi.n 800d638 800d606: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800d60a: d003 beq.n 800d614 800d60c: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800d610: d007 beq.n 800d622 800d612: e011 b.n 800d638 { case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ /* Enable USB Clock output generated form System USB . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d614: 4b4e ldr r3, [pc, #312] @ (800d750 ) 800d616: 6adb ldr r3, [r3, #44] @ 0x2c 800d618: 4a4d ldr r2, [pc, #308] @ (800d750 ) 800d61a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d61e: 62d3 str r3, [r2, #44] @ 0x2c /* USB clock source configuration done later after clock selection check */ break; 800d620: e00f b.n 800d642 case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d622: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d626: 3328 adds r3, #40 @ 0x28 800d628: 2101 movs r1, #1 800d62a: 4618 mov r0, r3 800d62c: f001 fc50 bl 800eed0 800d630: 4603 mov r3, r0 800d632: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USB clock source configuration done later after clock selection check */ break; 800d636: e004 b.n 800d642 /* HSI48 oscillator is used as source of USB clock */ /* USB clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d638: 2301 movs r3, #1 800d63a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d63e: e000 b.n 800d642 break; 800d640: bf00 nop } if (ret == HAL_OK) 800d642: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d646: 2b00 cmp r3, #0 800d648: d10b bne.n 800d662 { /* Set the source of USB clock*/ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 800d64a: 4b41 ldr r3, [pc, #260] @ (800d750 ) 800d64c: 6d5b ldr r3, [r3, #84] @ 0x54 800d64e: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800d652: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d656: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800d65a: 4a3d ldr r2, [pc, #244] @ (800d750 ) 800d65c: 430b orrs r3, r1 800d65e: 6553 str r3, [r2, #84] @ 0x54 800d660: e003 b.n 800d66a } else { /* set overall return value */ status = ret; 800d662: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d666: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------------- SDMMC Configuration ------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 800d66a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d66e: e9d3 2300 ldrd r2, r3, [r3] 800d672: f402 3380 and.w r3, r2, #65536 @ 0x10000 800d676: 66bb str r3, [r7, #104] @ 0x68 800d678: 2300 movs r3, #0 800d67a: 66fb str r3, [r7, #108] @ 0x6c 800d67c: e9d7 121a ldrd r1, r2, [r7, #104] @ 0x68 800d680: 460b mov r3, r1 800d682: 4313 orrs r3, r2 800d684: d031 beq.n 800d6ea { /* Check the parameters */ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); switch (PeriphClkInit->SdmmcClockSelection) 800d686: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d68a: 6d1b ldr r3, [r3, #80] @ 0x50 800d68c: 2b00 cmp r3, #0 800d68e: d003 beq.n 800d698 800d690: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800d694: d007 beq.n 800d6a6 800d696: e011 b.n 800d6bc { case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ /* Enable SDMMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d698: 4b2d ldr r3, [pc, #180] @ (800d750 ) 800d69a: 6adb ldr r3, [r3, #44] @ 0x2c 800d69c: 4a2c ldr r2, [pc, #176] @ (800d750 ) 800d69e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d6a2: 62d3 str r3, [r2, #44] @ 0x2c /* SDMMC clock source configuration done later after clock selection check */ break; 800d6a4: e00e b.n 800d6c4 case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800d6a6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d6aa: 3308 adds r3, #8 800d6ac: 2102 movs r1, #2 800d6ae: 4618 mov r0, r3 800d6b0: f001 fb5c bl 800ed6c 800d6b4: 4603 mov r3, r0 800d6b6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SDMMC clock source configuration done later after clock selection check */ break; 800d6ba: e003 b.n 800d6c4 default: ret = HAL_ERROR; 800d6bc: 2301 movs r3, #1 800d6be: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d6c2: bf00 nop } if (ret == HAL_OK) 800d6c4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d6c8: 2b00 cmp r3, #0 800d6ca: d10a bne.n 800d6e2 { /* Set the source of SDMMC clock*/ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 800d6cc: 4b20 ldr r3, [pc, #128] @ (800d750 ) 800d6ce: 6cdb ldr r3, [r3, #76] @ 0x4c 800d6d0: f423 3180 bic.w r1, r3, #65536 @ 0x10000 800d6d4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d6d8: 6d1b ldr r3, [r3, #80] @ 0x50 800d6da: 4a1d ldr r2, [pc, #116] @ (800d750 ) 800d6dc: 430b orrs r3, r1 800d6de: 64d3 str r3, [r2, #76] @ 0x4c 800d6e0: e003 b.n 800d6ea } else { /* set overall return value */ status = ret; 800d6e2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d6e6: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /* LTDC */ /*------------------------------ RNG Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 800d6ea: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d6ee: e9d3 2300 ldrd r2, r3, [r3] 800d6f2: f402 3300 and.w r3, r2, #131072 @ 0x20000 800d6f6: 663b str r3, [r7, #96] @ 0x60 800d6f8: 2300 movs r3, #0 800d6fa: 667b str r3, [r7, #100] @ 0x64 800d6fc: e9d7 1218 ldrd r1, r2, [r7, #96] @ 0x60 800d700: 460b mov r3, r1 800d702: 4313 orrs r3, r2 800d704: d03b beq.n 800d77e { switch (PeriphClkInit->RngClockSelection) 800d706: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d70a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800d70e: f5b3 7f40 cmp.w r3, #768 @ 0x300 800d712: d018 beq.n 800d746 800d714: f5b3 7f40 cmp.w r3, #768 @ 0x300 800d718: d811 bhi.n 800d73e 800d71a: f5b3 7f00 cmp.w r3, #512 @ 0x200 800d71e: d014 beq.n 800d74a 800d720: f5b3 7f00 cmp.w r3, #512 @ 0x200 800d724: d80b bhi.n 800d73e 800d726: 2b00 cmp r3, #0 800d728: d014 beq.n 800d754 800d72a: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d72e: d106 bne.n 800d73e { case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ /* Enable RNG Clock output generated form System RNG . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d730: 4b07 ldr r3, [pc, #28] @ (800d750 ) 800d732: 6adb ldr r3, [r3, #44] @ 0x2c 800d734: 4a06 ldr r2, [pc, #24] @ (800d750 ) 800d736: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d73a: 62d3 str r3, [r2, #44] @ 0x2c /* RNG clock source configuration done later after clock selection check */ break; 800d73c: e00b b.n 800d756 /* HSI48 oscillator is used as source of RNG clock */ /* RNG clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d73e: 2301 movs r3, #1 800d740: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d744: e007 b.n 800d756 break; 800d746: bf00 nop 800d748: e005 b.n 800d756 break; 800d74a: bf00 nop 800d74c: e003 b.n 800d756 800d74e: bf00 nop 800d750: 58024400 .word 0x58024400 break; 800d754: bf00 nop } if (ret == HAL_OK) 800d756: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d75a: 2b00 cmp r3, #0 800d75c: d10b bne.n 800d776 { /* Set the source of RNG clock*/ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 800d75e: 4bba ldr r3, [pc, #744] @ (800da48 ) 800d760: 6d5b ldr r3, [r3, #84] @ 0x54 800d762: f423 7140 bic.w r1, r3, #768 @ 0x300 800d766: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d76a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800d76e: 4ab6 ldr r2, [pc, #728] @ (800da48 ) 800d770: 430b orrs r3, r1 800d772: 6553 str r3, [r2, #84] @ 0x54 800d774: e003 b.n 800d77e } else { /* set overall return value */ status = ret; 800d776: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d77a: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ SWPMI1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 800d77e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d782: e9d3 2300 ldrd r2, r3, [r3] 800d786: f402 1380 and.w r3, r2, #1048576 @ 0x100000 800d78a: 65bb str r3, [r7, #88] @ 0x58 800d78c: 2300 movs r3, #0 800d78e: 65fb str r3, [r7, #92] @ 0x5c 800d790: e9d7 1216 ldrd r1, r2, [r7, #88] @ 0x58 800d794: 460b mov r3, r1 800d796: 4313 orrs r3, r2 800d798: d009 beq.n 800d7ae { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 800d79a: 4bab ldr r3, [pc, #684] @ (800da48 ) 800d79c: 6d1b ldr r3, [r3, #80] @ 0x50 800d79e: f023 4100 bic.w r1, r3, #2147483648 @ 0x80000000 800d7a2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7a6: 6f5b ldr r3, [r3, #116] @ 0x74 800d7a8: 4aa7 ldr r2, [pc, #668] @ (800da48 ) 800d7aa: 430b orrs r3, r1 800d7ac: 6513 str r3, [r2, #80] @ 0x50 } #if defined(HRTIM1) /*------------------------------ HRTIM1 clock Configuration ----------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) 800d7ae: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7b2: e9d3 2300 ldrd r2, r3, [r3] 800d7b6: f002 5380 and.w r3, r2, #268435456 @ 0x10000000 800d7ba: 653b str r3, [r7, #80] @ 0x50 800d7bc: 2300 movs r3, #0 800d7be: 657b str r3, [r7, #84] @ 0x54 800d7c0: e9d7 1214 ldrd r1, r2, [r7, #80] @ 0x50 800d7c4: 460b mov r3, r1 800d7c6: 4313 orrs r3, r2 800d7c8: d00a beq.n 800d7e0 { /* Check the parameters */ assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); 800d7ca: 4b9f ldr r3, [pc, #636] @ (800da48 ) 800d7cc: 691b ldr r3, [r3, #16] 800d7ce: f423 4180 bic.w r1, r3, #16384 @ 0x4000 800d7d2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7d6: f8d3 30b8 ldr.w r3, [r3, #184] @ 0xb8 800d7da: 4a9b ldr r2, [pc, #620] @ (800da48 ) 800d7dc: 430b orrs r3, r1 800d7de: 6113 str r3, [r2, #16] } #endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 800d7e0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7e4: e9d3 2300 ldrd r2, r3, [r3] 800d7e8: f402 1300 and.w r3, r2, #2097152 @ 0x200000 800d7ec: 64bb str r3, [r7, #72] @ 0x48 800d7ee: 2300 movs r3, #0 800d7f0: 64fb str r3, [r7, #76] @ 0x4c 800d7f2: e9d7 1212 ldrd r1, r2, [r7, #72] @ 0x48 800d7f6: 460b mov r3, r1 800d7f8: 4313 orrs r3, r2 800d7fa: d009 beq.n 800d810 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 800d7fc: 4b92 ldr r3, [pc, #584] @ (800da48 ) 800d7fe: 6d1b ldr r3, [r3, #80] @ 0x50 800d800: f023 7180 bic.w r1, r3, #16777216 @ 0x1000000 800d804: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d808: 6edb ldr r3, [r3, #108] @ 0x6c 800d80a: 4a8f ldr r2, [pc, #572] @ (800da48 ) 800d80c: 430b orrs r3, r1 800d80e: 6513 str r3, [r2, #80] @ 0x50 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); } #endif /* DFSDM2 */ /*------------------------------------ TIM configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 800d810: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d814: e9d3 2300 ldrd r2, r3, [r3] 800d818: f002 4380 and.w r3, r2, #1073741824 @ 0x40000000 800d81c: 643b str r3, [r7, #64] @ 0x40 800d81e: 2300 movs r3, #0 800d820: 647b str r3, [r7, #68] @ 0x44 800d822: e9d7 1210 ldrd r1, r2, [r7, #64] @ 0x40 800d826: 460b mov r3, r1 800d828: 4313 orrs r3, r2 800d82a: d00e beq.n 800d84a { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 800d82c: 4b86 ldr r3, [pc, #536] @ (800da48 ) 800d82e: 691b ldr r3, [r3, #16] 800d830: 4a85 ldr r2, [pc, #532] @ (800da48 ) 800d832: f423 4300 bic.w r3, r3, #32768 @ 0x8000 800d836: 6113 str r3, [r2, #16] 800d838: 4b83 ldr r3, [pc, #524] @ (800da48 ) 800d83a: 6919 ldr r1, [r3, #16] 800d83c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d840: f8d3 30bc ldr.w r3, [r3, #188] @ 0xbc 800d844: 4a80 ldr r2, [pc, #512] @ (800da48 ) 800d846: 430b orrs r3, r1 800d848: 6113 str r3, [r2, #16] } /*------------------------------------ CKPER configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 800d84a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d84e: e9d3 2300 ldrd r2, r3, [r3] 800d852: f002 4300 and.w r3, r2, #2147483648 @ 0x80000000 800d856: 63bb str r3, [r7, #56] @ 0x38 800d858: 2300 movs r3, #0 800d85a: 63fb str r3, [r7, #60] @ 0x3c 800d85c: e9d7 120e ldrd r1, r2, [r7, #56] @ 0x38 800d860: 460b mov r3, r1 800d862: 4313 orrs r3, r2 800d864: d009 beq.n 800d87a { /* Check the parameters */ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); /* Configure the CKPER clock source */ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 800d866: 4b78 ldr r3, [pc, #480] @ (800da48 ) 800d868: 6cdb ldr r3, [r3, #76] @ 0x4c 800d86a: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 800d86e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d872: 6d5b ldr r3, [r3, #84] @ 0x54 800d874: 4a74 ldr r2, [pc, #464] @ (800da48 ) 800d876: 430b orrs r3, r1 800d878: 64d3 str r3, [r2, #76] @ 0x4c } /*------------------------------ CEC Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 800d87a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d87e: e9d3 2300 ldrd r2, r3, [r3] 800d882: f402 0300 and.w r3, r2, #8388608 @ 0x800000 800d886: 633b str r3, [r7, #48] @ 0x30 800d888: 2300 movs r3, #0 800d88a: 637b str r3, [r7, #52] @ 0x34 800d88c: e9d7 120c ldrd r1, r2, [r7, #48] @ 0x30 800d890: 460b mov r3, r1 800d892: 4313 orrs r3, r2 800d894: d00a beq.n 800d8ac { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC interface clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 800d896: 4b6c ldr r3, [pc, #432] @ (800da48 ) 800d898: 6d5b ldr r3, [r3, #84] @ 0x54 800d89a: f423 0140 bic.w r1, r3, #12582912 @ 0xc00000 800d89e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8a2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800d8a6: 4a68 ldr r2, [pc, #416] @ (800da48 ) 800d8a8: 430b orrs r3, r1 800d8aa: 6553 str r3, [r2, #84] @ 0x54 } /*---------------------------- PLL2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) 800d8ac: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8b0: e9d3 2300 ldrd r2, r3, [r3] 800d8b4: 2100 movs r1, #0 800d8b6: 62b9 str r1, [r7, #40] @ 0x28 800d8b8: f003 0301 and.w r3, r3, #1 800d8bc: 62fb str r3, [r7, #44] @ 0x2c 800d8be: e9d7 120a ldrd r1, r2, [r7, #40] @ 0x28 800d8c2: 460b mov r3, r1 800d8c4: 4313 orrs r3, r2 800d8c6: d011 beq.n 800d8ec { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d8c8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8cc: 3308 adds r3, #8 800d8ce: 2100 movs r1, #0 800d8d0: 4618 mov r0, r3 800d8d2: f001 fa4b bl 800ed6c 800d8d6: 4603 mov r3, r0 800d8d8: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800d8dc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d8e0: 2b00 cmp r3, #0 800d8e2: d003 beq.n 800d8ec /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800d8e4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d8e8: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) 800d8ec: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8f0: e9d3 2300 ldrd r2, r3, [r3] 800d8f4: 2100 movs r1, #0 800d8f6: 6239 str r1, [r7, #32] 800d8f8: f003 0302 and.w r3, r3, #2 800d8fc: 627b str r3, [r7, #36] @ 0x24 800d8fe: e9d7 1208 ldrd r1, r2, [r7, #32] 800d902: 460b mov r3, r1 800d904: 4313 orrs r3, r2 800d906: d011 beq.n 800d92c { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d908: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d90c: 3308 adds r3, #8 800d90e: 2101 movs r1, #1 800d910: 4618 mov r0, r3 800d912: f001 fa2b bl 800ed6c 800d916: 4603 mov r3, r0 800d918: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800d91c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d920: 2b00 cmp r3, #0 800d922: d003 beq.n 800d92c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800d924: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d928: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) 800d92c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d930: e9d3 2300 ldrd r2, r3, [r3] 800d934: 2100 movs r1, #0 800d936: 61b9 str r1, [r7, #24] 800d938: f003 0304 and.w r3, r3, #4 800d93c: 61fb str r3, [r7, #28] 800d93e: e9d7 1206 ldrd r1, r2, [r7, #24] 800d942: 460b mov r3, r1 800d944: 4313 orrs r3, r2 800d946: d011 beq.n 800d96c { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800d948: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d94c: 3308 adds r3, #8 800d94e: 2102 movs r1, #2 800d950: 4618 mov r0, r3 800d952: f001 fa0b bl 800ed6c 800d956: 4603 mov r3, r0 800d958: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800d95c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d960: 2b00 cmp r3, #0 800d962: d003 beq.n 800d96c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800d964: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d968: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- PLL3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) 800d96c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d970: e9d3 2300 ldrd r2, r3, [r3] 800d974: 2100 movs r1, #0 800d976: 6139 str r1, [r7, #16] 800d978: f003 0308 and.w r3, r3, #8 800d97c: 617b str r3, [r7, #20] 800d97e: e9d7 1204 ldrd r1, r2, [r7, #16] 800d982: 460b mov r3, r1 800d984: 4313 orrs r3, r2 800d986: d011 beq.n 800d9ac { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800d988: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d98c: 3328 adds r3, #40 @ 0x28 800d98e: 2100 movs r1, #0 800d990: 4618 mov r0, r3 800d992: f001 fa9d bl 800eed0 800d996: 4603 mov r3, r0 800d998: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800d99c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d9a0: 2b00 cmp r3, #0 800d9a2: d003 beq.n 800d9ac /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800d9a4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d9a8: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) 800d9ac: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d9b0: e9d3 2300 ldrd r2, r3, [r3] 800d9b4: 2100 movs r1, #0 800d9b6: 60b9 str r1, [r7, #8] 800d9b8: f003 0310 and.w r3, r3, #16 800d9bc: 60fb str r3, [r7, #12] 800d9be: e9d7 1202 ldrd r1, r2, [r7, #8] 800d9c2: 460b mov r3, r1 800d9c4: 4313 orrs r3, r2 800d9c6: d011 beq.n 800d9ec { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d9c8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d9cc: 3328 adds r3, #40 @ 0x28 800d9ce: 2101 movs r1, #1 800d9d0: 4618 mov r0, r3 800d9d2: f001 fa7d bl 800eed0 800d9d6: 4603 mov r3, r0 800d9d8: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800d9dc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d9e0: 2b00 cmp r3, #0 800d9e2: d003 beq.n 800d9ec /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800d9e4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d9e8: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) 800d9ec: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d9f0: e9d3 2300 ldrd r2, r3, [r3] 800d9f4: 2100 movs r1, #0 800d9f6: 6039 str r1, [r7, #0] 800d9f8: f003 0320 and.w r3, r3, #32 800d9fc: 607b str r3, [r7, #4] 800d9fe: e9d7 1200 ldrd r1, r2, [r7] 800da02: 460b mov r3, r1 800da04: 4313 orrs r3, r2 800da06: d011 beq.n 800da2c { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800da08: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da0c: 3328 adds r3, #40 @ 0x28 800da0e: 2102 movs r1, #2 800da10: 4618 mov r0, r3 800da12: f001 fa5d bl 800eed0 800da16: 4603 mov r3, r0 800da18: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800da1c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800da20: 2b00 cmp r3, #0 800da22: d003 beq.n 800da2c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800da24: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800da28: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (status == HAL_OK) 800da2c: f897 311e ldrb.w r3, [r7, #286] @ 0x11e 800da30: 2b00 cmp r3, #0 800da32: d101 bne.n 800da38 { return HAL_OK; 800da34: 2300 movs r3, #0 800da36: e000 b.n 800da3a } return HAL_ERROR; 800da38: 2301 movs r3, #1 } 800da3a: 4618 mov r0, r3 800da3c: f507 7790 add.w r7, r7, #288 @ 0x120 800da40: 46bd mov sp, r7 800da42: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 800da46: bf00 nop 800da48: 58024400 .word 0x58024400 0800da4c : * @retval Frequency in KHz * * (*) : Available on some STM32H7 lines only. */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) { 800da4c: b580 push {r7, lr} 800da4e: b090 sub sp, #64 @ 0x40 800da50: af00 add r7, sp, #0 800da52: e9c7 0100 strd r0, r1, [r7] /* This variable is used to store the SAI and CKP clock source */ uint32_t saiclocksource; uint32_t ckpclocksource; uint32_t srcclk; if (PeriphClk == RCC_PERIPHCLK_SAI1) 800da56: e9d7 2300 ldrd r2, r3, [r7] 800da5a: f5a2 7180 sub.w r1, r2, #256 @ 0x100 800da5e: 430b orrs r3, r1 800da60: f040 8094 bne.w 800db8c { saiclocksource = __HAL_RCC_GET_SAI1_SOURCE(); 800da64: 4b9e ldr r3, [pc, #632] @ (800dce0 ) 800da66: 6d1b ldr r3, [r3, #80] @ 0x50 800da68: f003 0307 and.w r3, r3, #7 800da6c: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800da6e: 6b3b ldr r3, [r7, #48] @ 0x30 800da70: 2b04 cmp r3, #4 800da72: f200 8087 bhi.w 800db84 800da76: a201 add r2, pc, #4 @ (adr r2, 800da7c ) 800da78: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800da7c: 0800da91 .word 0x0800da91 800da80: 0800dab9 .word 0x0800dab9 800da84: 0800dae1 .word 0x0800dae1 800da88: 0800db7d .word 0x0800db7d 800da8c: 0800db09 .word 0x0800db09 { case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800da90: 4b93 ldr r3, [pc, #588] @ (800dce0 ) 800da92: 681b ldr r3, [r3, #0] 800da94: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800da98: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800da9c: d108 bne.n 800dab0 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800da9e: f107 0324 add.w r3, r7, #36 @ 0x24 800daa2: 4618 mov r0, r3 800daa4: f001 f810 bl 800eac8 frequency = pll1_clocks.PLL1_Q_Frequency; 800daa8: 6abb ldr r3, [r7, #40] @ 0x28 800daaa: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800daac: f000 bd45 b.w 800e53a frequency = 0; 800dab0: 2300 movs r3, #0 800dab2: 63fb str r3, [r7, #60] @ 0x3c break; 800dab4: f000 bd41 b.w 800e53a } case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800dab8: 4b89 ldr r3, [pc, #548] @ (800dce0 ) 800daba: 681b ldr r3, [r3, #0] 800dabc: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800dac0: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800dac4: d108 bne.n 800dad8 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800dac6: f107 0318 add.w r3, r7, #24 800daca: 4618 mov r0, r3 800dacc: f000 fd54 bl 800e578 frequency = pll2_clocks.PLL2_P_Frequency; 800dad0: 69bb ldr r3, [r7, #24] 800dad2: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dad4: f000 bd31 b.w 800e53a frequency = 0; 800dad8: 2300 movs r3, #0 800dada: 63fb str r3, [r7, #60] @ 0x3c break; 800dadc: f000 bd2d b.w 800e53a } case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800dae0: 4b7f ldr r3, [pc, #508] @ (800dce0 ) 800dae2: 681b ldr r3, [r3, #0] 800dae4: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800dae8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800daec: d108 bne.n 800db00 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800daee: f107 030c add.w r3, r7, #12 800daf2: 4618 mov r0, r3 800daf4: f000 fe94 bl 800e820 frequency = pll3_clocks.PLL3_P_Frequency; 800daf8: 68fb ldr r3, [r7, #12] 800dafa: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dafc: f000 bd1d b.w 800e53a frequency = 0; 800db00: 2300 movs r3, #0 800db02: 63fb str r3, [r7, #60] @ 0x3c break; 800db04: f000 bd19 b.w 800e53a } case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800db08: 4b75 ldr r3, [pc, #468] @ (800dce0 ) 800db0a: 6cdb ldr r3, [r3, #76] @ 0x4c 800db0c: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800db10: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800db12: 4b73 ldr r3, [pc, #460] @ (800dce0 ) 800db14: 681b ldr r3, [r3, #0] 800db16: f003 0304 and.w r3, r3, #4 800db1a: 2b04 cmp r3, #4 800db1c: d10c bne.n 800db38 800db1e: 6b7b ldr r3, [r7, #52] @ 0x34 800db20: 2b00 cmp r3, #0 800db22: d109 bne.n 800db38 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800db24: 4b6e ldr r3, [pc, #440] @ (800dce0 ) 800db26: 681b ldr r3, [r3, #0] 800db28: 08db lsrs r3, r3, #3 800db2a: f003 0303 and.w r3, r3, #3 800db2e: 4a6d ldr r2, [pc, #436] @ (800dce4 ) 800db30: fa22 f303 lsr.w r3, r2, r3 800db34: 63fb str r3, [r7, #60] @ 0x3c 800db36: e01f b.n 800db78 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800db38: 4b69 ldr r3, [pc, #420] @ (800dce0 ) 800db3a: 681b ldr r3, [r3, #0] 800db3c: f403 7380 and.w r3, r3, #256 @ 0x100 800db40: f5b3 7f80 cmp.w r3, #256 @ 0x100 800db44: d106 bne.n 800db54 800db46: 6b7b ldr r3, [r7, #52] @ 0x34 800db48: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800db4c: d102 bne.n 800db54 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800db4e: 4b66 ldr r3, [pc, #408] @ (800dce8 ) 800db50: 63fb str r3, [r7, #60] @ 0x3c 800db52: e011 b.n 800db78 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800db54: 4b62 ldr r3, [pc, #392] @ (800dce0 ) 800db56: 681b ldr r3, [r3, #0] 800db58: f403 3300 and.w r3, r3, #131072 @ 0x20000 800db5c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800db60: d106 bne.n 800db70 800db62: 6b7b ldr r3, [r7, #52] @ 0x34 800db64: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800db68: d102 bne.n 800db70 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800db6a: 4b60 ldr r3, [pc, #384] @ (800dcec ) 800db6c: 63fb str r3, [r7, #60] @ 0x3c 800db6e: e003 b.n 800db78 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800db70: 2300 movs r3, #0 800db72: 63fb str r3, [r7, #60] @ 0x3c } break; 800db74: f000 bce1 b.w 800e53a 800db78: f000 bcdf b.w 800e53a } case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ { frequency = EXTERNAL_CLOCK_VALUE; 800db7c: 4b5c ldr r3, [pc, #368] @ (800dcf0 ) 800db7e: 63fb str r3, [r7, #60] @ 0x3c break; 800db80: f000 bcdb b.w 800e53a } default : { frequency = 0; 800db84: 2300 movs r3, #0 800db86: 63fb str r3, [r7, #60] @ 0x3c break; 800db88: f000 bcd7 b.w 800e53a } } } #if defined(SAI3) else if (PeriphClk == RCC_PERIPHCLK_SAI23) 800db8c: e9d7 2300 ldrd r2, r3, [r7] 800db90: f5a2 7100 sub.w r1, r2, #512 @ 0x200 800db94: 430b orrs r3, r1 800db96: f040 80ad bne.w 800dcf4 { saiclocksource = __HAL_RCC_GET_SAI23_SOURCE(); 800db9a: 4b51 ldr r3, [pc, #324] @ (800dce0 ) 800db9c: 6d1b ldr r3, [r3, #80] @ 0x50 800db9e: f403 73e0 and.w r3, r3, #448 @ 0x1c0 800dba2: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800dba4: 6b3b ldr r3, [r7, #48] @ 0x30 800dba6: f5b3 7f80 cmp.w r3, #256 @ 0x100 800dbaa: d056 beq.n 800dc5a 800dbac: 6b3b ldr r3, [r7, #48] @ 0x30 800dbae: f5b3 7f80 cmp.w r3, #256 @ 0x100 800dbb2: f200 8090 bhi.w 800dcd6 800dbb6: 6b3b ldr r3, [r7, #48] @ 0x30 800dbb8: 2bc0 cmp r3, #192 @ 0xc0 800dbba: f000 8088 beq.w 800dcce 800dbbe: 6b3b ldr r3, [r7, #48] @ 0x30 800dbc0: 2bc0 cmp r3, #192 @ 0xc0 800dbc2: f200 8088 bhi.w 800dcd6 800dbc6: 6b3b ldr r3, [r7, #48] @ 0x30 800dbc8: 2b80 cmp r3, #128 @ 0x80 800dbca: d032 beq.n 800dc32 800dbcc: 6b3b ldr r3, [r7, #48] @ 0x30 800dbce: 2b80 cmp r3, #128 @ 0x80 800dbd0: f200 8081 bhi.w 800dcd6 800dbd4: 6b3b ldr r3, [r7, #48] @ 0x30 800dbd6: 2b00 cmp r3, #0 800dbd8: d003 beq.n 800dbe2 800dbda: 6b3b ldr r3, [r7, #48] @ 0x30 800dbdc: 2b40 cmp r3, #64 @ 0x40 800dbde: d014 beq.n 800dc0a 800dbe0: e079 b.n 800dcd6 { case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800dbe2: 4b3f ldr r3, [pc, #252] @ (800dce0 ) 800dbe4: 681b ldr r3, [r3, #0] 800dbe6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800dbea: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800dbee: d108 bne.n 800dc02 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800dbf0: f107 0324 add.w r3, r7, #36 @ 0x24 800dbf4: 4618 mov r0, r3 800dbf6: f000 ff67 bl 800eac8 frequency = pll1_clocks.PLL1_Q_Frequency; 800dbfa: 6abb ldr r3, [r7, #40] @ 0x28 800dbfc: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dbfe: f000 bc9c b.w 800e53a frequency = 0; 800dc02: 2300 movs r3, #0 800dc04: 63fb str r3, [r7, #60] @ 0x3c break; 800dc06: f000 bc98 b.w 800e53a } case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800dc0a: 4b35 ldr r3, [pc, #212] @ (800dce0 ) 800dc0c: 681b ldr r3, [r3, #0] 800dc0e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800dc12: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800dc16: d108 bne.n 800dc2a { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800dc18: f107 0318 add.w r3, r7, #24 800dc1c: 4618 mov r0, r3 800dc1e: f000 fcab bl 800e578 frequency = pll2_clocks.PLL2_P_Frequency; 800dc22: 69bb ldr r3, [r7, #24] 800dc24: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dc26: f000 bc88 b.w 800e53a frequency = 0; 800dc2a: 2300 movs r3, #0 800dc2c: 63fb str r3, [r7, #60] @ 0x3c break; 800dc2e: f000 bc84 b.w 800e53a } case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800dc32: 4b2b ldr r3, [pc, #172] @ (800dce0 ) 800dc34: 681b ldr r3, [r3, #0] 800dc36: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800dc3a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800dc3e: d108 bne.n 800dc52 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800dc40: f107 030c add.w r3, r7, #12 800dc44: 4618 mov r0, r3 800dc46: f000 fdeb bl 800e820 frequency = pll3_clocks.PLL3_P_Frequency; 800dc4a: 68fb ldr r3, [r7, #12] 800dc4c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dc4e: f000 bc74 b.w 800e53a frequency = 0; 800dc52: 2300 movs r3, #0 800dc54: 63fb str r3, [r7, #60] @ 0x3c break; 800dc56: f000 bc70 b.w 800e53a } case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800dc5a: 4b21 ldr r3, [pc, #132] @ (800dce0 ) 800dc5c: 6cdb ldr r3, [r3, #76] @ 0x4c 800dc5e: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800dc62: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800dc64: 4b1e ldr r3, [pc, #120] @ (800dce0 ) 800dc66: 681b ldr r3, [r3, #0] 800dc68: f003 0304 and.w r3, r3, #4 800dc6c: 2b04 cmp r3, #4 800dc6e: d10c bne.n 800dc8a 800dc70: 6b7b ldr r3, [r7, #52] @ 0x34 800dc72: 2b00 cmp r3, #0 800dc74: d109 bne.n 800dc8a { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800dc76: 4b1a ldr r3, [pc, #104] @ (800dce0 ) 800dc78: 681b ldr r3, [r3, #0] 800dc7a: 08db lsrs r3, r3, #3 800dc7c: f003 0303 and.w r3, r3, #3 800dc80: 4a18 ldr r2, [pc, #96] @ (800dce4 ) 800dc82: fa22 f303 lsr.w r3, r2, r3 800dc86: 63fb str r3, [r7, #60] @ 0x3c 800dc88: e01f b.n 800dcca } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800dc8a: 4b15 ldr r3, [pc, #84] @ (800dce0 ) 800dc8c: 681b ldr r3, [r3, #0] 800dc8e: f403 7380 and.w r3, r3, #256 @ 0x100 800dc92: f5b3 7f80 cmp.w r3, #256 @ 0x100 800dc96: d106 bne.n 800dca6 800dc98: 6b7b ldr r3, [r7, #52] @ 0x34 800dc9a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800dc9e: d102 bne.n 800dca6 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800dca0: 4b11 ldr r3, [pc, #68] @ (800dce8 ) 800dca2: 63fb str r3, [r7, #60] @ 0x3c 800dca4: e011 b.n 800dcca } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800dca6: 4b0e ldr r3, [pc, #56] @ (800dce0 ) 800dca8: 681b ldr r3, [r3, #0] 800dcaa: f403 3300 and.w r3, r3, #131072 @ 0x20000 800dcae: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800dcb2: d106 bne.n 800dcc2 800dcb4: 6b7b ldr r3, [r7, #52] @ 0x34 800dcb6: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800dcba: d102 bne.n 800dcc2 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800dcbc: 4b0b ldr r3, [pc, #44] @ (800dcec ) 800dcbe: 63fb str r3, [r7, #60] @ 0x3c 800dcc0: e003 b.n 800dcca } else { /* In Case the CKPER is disabled*/ frequency = 0; 800dcc2: 2300 movs r3, #0 800dcc4: 63fb str r3, [r7, #60] @ 0x3c } break; 800dcc6: f000 bc38 b.w 800e53a 800dcca: f000 bc36 b.w 800e53a } case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ { frequency = EXTERNAL_CLOCK_VALUE; 800dcce: 4b08 ldr r3, [pc, #32] @ (800dcf0 ) 800dcd0: 63fb str r3, [r7, #60] @ 0x3c break; 800dcd2: f000 bc32 b.w 800e53a } default : { frequency = 0; 800dcd6: 2300 movs r3, #0 800dcd8: 63fb str r3, [r7, #60] @ 0x3c break; 800dcda: f000 bc2e b.w 800e53a 800dcde: bf00 nop 800dce0: 58024400 .word 0x58024400 800dce4: 03d09000 .word 0x03d09000 800dce8: 003d0900 .word 0x003d0900 800dcec: 017d7840 .word 0x017d7840 800dcf0: 00bb8000 .word 0x00bb8000 } } #endif #if defined(SAI4) else if (PeriphClk == RCC_PERIPHCLK_SAI4A) 800dcf4: e9d7 2300 ldrd r2, r3, [r7] 800dcf8: f5a2 6180 sub.w r1, r2, #1024 @ 0x400 800dcfc: 430b orrs r3, r1 800dcfe: f040 809c bne.w 800de3a { saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE(); 800dd02: 4b9e ldr r3, [pc, #632] @ (800df7c ) 800dd04: 6d9b ldr r3, [r3, #88] @ 0x58 800dd06: f403 0360 and.w r3, r3, #14680064 @ 0xe00000 800dd0a: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800dd0c: 6b3b ldr r3, [r7, #48] @ 0x30 800dd0e: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800dd12: d054 beq.n 800ddbe 800dd14: 6b3b ldr r3, [r7, #48] @ 0x30 800dd16: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800dd1a: f200 808b bhi.w 800de34 800dd1e: 6b3b ldr r3, [r7, #48] @ 0x30 800dd20: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800dd24: f000 8083 beq.w 800de2e 800dd28: 6b3b ldr r3, [r7, #48] @ 0x30 800dd2a: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800dd2e: f200 8081 bhi.w 800de34 800dd32: 6b3b ldr r3, [r7, #48] @ 0x30 800dd34: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800dd38: d02f beq.n 800dd9a 800dd3a: 6b3b ldr r3, [r7, #48] @ 0x30 800dd3c: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800dd40: d878 bhi.n 800de34 800dd42: 6b3b ldr r3, [r7, #48] @ 0x30 800dd44: 2b00 cmp r3, #0 800dd46: d004 beq.n 800dd52 800dd48: 6b3b ldr r3, [r7, #48] @ 0x30 800dd4a: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800dd4e: d012 beq.n 800dd76 800dd50: e070 b.n 800de34 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800dd52: 4b8a ldr r3, [pc, #552] @ (800df7c ) 800dd54: 681b ldr r3, [r3, #0] 800dd56: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800dd5a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800dd5e: d107 bne.n 800dd70 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800dd60: f107 0324 add.w r3, r7, #36 @ 0x24 800dd64: 4618 mov r0, r3 800dd66: f000 feaf bl 800eac8 frequency = pll1_clocks.PLL1_Q_Frequency; 800dd6a: 6abb ldr r3, [r7, #40] @ 0x28 800dd6c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dd6e: e3e4 b.n 800e53a frequency = 0; 800dd70: 2300 movs r3, #0 800dd72: 63fb str r3, [r7, #60] @ 0x3c break; 800dd74: e3e1 b.n 800e53a } case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800dd76: 4b81 ldr r3, [pc, #516] @ (800df7c ) 800dd78: 681b ldr r3, [r3, #0] 800dd7a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800dd7e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800dd82: d107 bne.n 800dd94 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800dd84: f107 0318 add.w r3, r7, #24 800dd88: 4618 mov r0, r3 800dd8a: f000 fbf5 bl 800e578 frequency = pll2_clocks.PLL2_P_Frequency; 800dd8e: 69bb ldr r3, [r7, #24] 800dd90: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dd92: e3d2 b.n 800e53a frequency = 0; 800dd94: 2300 movs r3, #0 800dd96: 63fb str r3, [r7, #60] @ 0x3c break; 800dd98: e3cf b.n 800e53a } case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800dd9a: 4b78 ldr r3, [pc, #480] @ (800df7c ) 800dd9c: 681b ldr r3, [r3, #0] 800dd9e: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800dda2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800dda6: d107 bne.n 800ddb8 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800dda8: f107 030c add.w r3, r7, #12 800ddac: 4618 mov r0, r3 800ddae: f000 fd37 bl 800e820 frequency = pll3_clocks.PLL3_P_Frequency; 800ddb2: 68fb ldr r3, [r7, #12] 800ddb4: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800ddb6: e3c0 b.n 800e53a frequency = 0; 800ddb8: 2300 movs r3, #0 800ddba: 63fb str r3, [r7, #60] @ 0x3c break; 800ddbc: e3bd b.n 800e53a } case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800ddbe: 4b6f ldr r3, [pc, #444] @ (800df7c ) 800ddc0: 6cdb ldr r3, [r3, #76] @ 0x4c 800ddc2: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800ddc6: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800ddc8: 4b6c ldr r3, [pc, #432] @ (800df7c ) 800ddca: 681b ldr r3, [r3, #0] 800ddcc: f003 0304 and.w r3, r3, #4 800ddd0: 2b04 cmp r3, #4 800ddd2: d10c bne.n 800ddee 800ddd4: 6b7b ldr r3, [r7, #52] @ 0x34 800ddd6: 2b00 cmp r3, #0 800ddd8: d109 bne.n 800ddee { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800ddda: 4b68 ldr r3, [pc, #416] @ (800df7c ) 800dddc: 681b ldr r3, [r3, #0] 800ddde: 08db lsrs r3, r3, #3 800dde0: f003 0303 and.w r3, r3, #3 800dde4: 4a66 ldr r2, [pc, #408] @ (800df80 ) 800dde6: fa22 f303 lsr.w r3, r2, r3 800ddea: 63fb str r3, [r7, #60] @ 0x3c 800ddec: e01e b.n 800de2c } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800ddee: 4b63 ldr r3, [pc, #396] @ (800df7c ) 800ddf0: 681b ldr r3, [r3, #0] 800ddf2: f403 7380 and.w r3, r3, #256 @ 0x100 800ddf6: f5b3 7f80 cmp.w r3, #256 @ 0x100 800ddfa: d106 bne.n 800de0a 800ddfc: 6b7b ldr r3, [r7, #52] @ 0x34 800ddfe: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800de02: d102 bne.n 800de0a { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800de04: 4b5f ldr r3, [pc, #380] @ (800df84 ) 800de06: 63fb str r3, [r7, #60] @ 0x3c 800de08: e010 b.n 800de2c } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800de0a: 4b5c ldr r3, [pc, #368] @ (800df7c ) 800de0c: 681b ldr r3, [r3, #0] 800de0e: f403 3300 and.w r3, r3, #131072 @ 0x20000 800de12: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800de16: d106 bne.n 800de26 800de18: 6b7b ldr r3, [r7, #52] @ 0x34 800de1a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800de1e: d102 bne.n 800de26 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800de20: 4b59 ldr r3, [pc, #356] @ (800df88 ) 800de22: 63fb str r3, [r7, #60] @ 0x3c 800de24: e002 b.n 800de2c } else { /* In Case the CKPER is disabled*/ frequency = 0; 800de26: 2300 movs r3, #0 800de28: 63fb str r3, [r7, #60] @ 0x3c } break; 800de2a: e386 b.n 800e53a 800de2c: e385 b.n 800e53a } case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ { frequency = EXTERNAL_CLOCK_VALUE; 800de2e: 4b57 ldr r3, [pc, #348] @ (800df8c ) 800de30: 63fb str r3, [r7, #60] @ 0x3c break; 800de32: e382 b.n 800e53a } default : { frequency = 0; 800de34: 2300 movs r3, #0 800de36: 63fb str r3, [r7, #60] @ 0x3c break; 800de38: e37f b.n 800e53a } } } else if (PeriphClk == RCC_PERIPHCLK_SAI4B) 800de3a: e9d7 2300 ldrd r2, r3, [r7] 800de3e: f5a2 6100 sub.w r1, r2, #2048 @ 0x800 800de42: 430b orrs r3, r1 800de44: f040 80a7 bne.w 800df96 { saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE(); 800de48: 4b4c ldr r3, [pc, #304] @ (800df7c ) 800de4a: 6d9b ldr r3, [r3, #88] @ 0x58 800de4c: f003 63e0 and.w r3, r3, #117440512 @ 0x7000000 800de50: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800de52: 6b3b ldr r3, [r7, #48] @ 0x30 800de54: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800de58: d055 beq.n 800df06 800de5a: 6b3b ldr r3, [r7, #48] @ 0x30 800de5c: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800de60: f200 8096 bhi.w 800df90 800de64: 6b3b ldr r3, [r7, #48] @ 0x30 800de66: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800de6a: f000 8084 beq.w 800df76 800de6e: 6b3b ldr r3, [r7, #48] @ 0x30 800de70: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800de74: f200 808c bhi.w 800df90 800de78: 6b3b ldr r3, [r7, #48] @ 0x30 800de7a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800de7e: d030 beq.n 800dee2 800de80: 6b3b ldr r3, [r7, #48] @ 0x30 800de82: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800de86: f200 8083 bhi.w 800df90 800de8a: 6b3b ldr r3, [r7, #48] @ 0x30 800de8c: 2b00 cmp r3, #0 800de8e: d004 beq.n 800de9a 800de90: 6b3b ldr r3, [r7, #48] @ 0x30 800de92: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800de96: d012 beq.n 800debe 800de98: e07a b.n 800df90 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800de9a: 4b38 ldr r3, [pc, #224] @ (800df7c ) 800de9c: 681b ldr r3, [r3, #0] 800de9e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800dea2: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800dea6: d107 bne.n 800deb8 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800dea8: f107 0324 add.w r3, r7, #36 @ 0x24 800deac: 4618 mov r0, r3 800deae: f000 fe0b bl 800eac8 frequency = pll1_clocks.PLL1_Q_Frequency; 800deb2: 6abb ldr r3, [r7, #40] @ 0x28 800deb4: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800deb6: e340 b.n 800e53a frequency = 0; 800deb8: 2300 movs r3, #0 800deba: 63fb str r3, [r7, #60] @ 0x3c break; 800debc: e33d b.n 800e53a } case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800debe: 4b2f ldr r3, [pc, #188] @ (800df7c ) 800dec0: 681b ldr r3, [r3, #0] 800dec2: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800dec6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800deca: d107 bne.n 800dedc { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800decc: f107 0318 add.w r3, r7, #24 800ded0: 4618 mov r0, r3 800ded2: f000 fb51 bl 800e578 frequency = pll2_clocks.PLL2_P_Frequency; 800ded6: 69bb ldr r3, [r7, #24] 800ded8: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800deda: e32e b.n 800e53a frequency = 0; 800dedc: 2300 movs r3, #0 800dede: 63fb str r3, [r7, #60] @ 0x3c break; 800dee0: e32b b.n 800e53a } case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800dee2: 4b26 ldr r3, [pc, #152] @ (800df7c ) 800dee4: 681b ldr r3, [r3, #0] 800dee6: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800deea: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800deee: d107 bne.n 800df00 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800def0: f107 030c add.w r3, r7, #12 800def4: 4618 mov r0, r3 800def6: f000 fc93 bl 800e820 frequency = pll3_clocks.PLL3_P_Frequency; 800defa: 68fb ldr r3, [r7, #12] 800defc: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800defe: e31c b.n 800e53a frequency = 0; 800df00: 2300 movs r3, #0 800df02: 63fb str r3, [r7, #60] @ 0x3c break; 800df04: e319 b.n 800e53a } case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800df06: 4b1d ldr r3, [pc, #116] @ (800df7c ) 800df08: 6cdb ldr r3, [r3, #76] @ 0x4c 800df0a: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800df0e: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800df10: 4b1a ldr r3, [pc, #104] @ (800df7c ) 800df12: 681b ldr r3, [r3, #0] 800df14: f003 0304 and.w r3, r3, #4 800df18: 2b04 cmp r3, #4 800df1a: d10c bne.n 800df36 800df1c: 6b7b ldr r3, [r7, #52] @ 0x34 800df1e: 2b00 cmp r3, #0 800df20: d109 bne.n 800df36 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800df22: 4b16 ldr r3, [pc, #88] @ (800df7c ) 800df24: 681b ldr r3, [r3, #0] 800df26: 08db lsrs r3, r3, #3 800df28: f003 0303 and.w r3, r3, #3 800df2c: 4a14 ldr r2, [pc, #80] @ (800df80 ) 800df2e: fa22 f303 lsr.w r3, r2, r3 800df32: 63fb str r3, [r7, #60] @ 0x3c 800df34: e01e b.n 800df74 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800df36: 4b11 ldr r3, [pc, #68] @ (800df7c ) 800df38: 681b ldr r3, [r3, #0] 800df3a: f403 7380 and.w r3, r3, #256 @ 0x100 800df3e: f5b3 7f80 cmp.w r3, #256 @ 0x100 800df42: d106 bne.n 800df52 800df44: 6b7b ldr r3, [r7, #52] @ 0x34 800df46: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800df4a: d102 bne.n 800df52 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800df4c: 4b0d ldr r3, [pc, #52] @ (800df84 ) 800df4e: 63fb str r3, [r7, #60] @ 0x3c 800df50: e010 b.n 800df74 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800df52: 4b0a ldr r3, [pc, #40] @ (800df7c ) 800df54: 681b ldr r3, [r3, #0] 800df56: f403 3300 and.w r3, r3, #131072 @ 0x20000 800df5a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800df5e: d106 bne.n 800df6e 800df60: 6b7b ldr r3, [r7, #52] @ 0x34 800df62: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800df66: d102 bne.n 800df6e { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800df68: 4b07 ldr r3, [pc, #28] @ (800df88 ) 800df6a: 63fb str r3, [r7, #60] @ 0x3c 800df6c: e002 b.n 800df74 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800df6e: 2300 movs r3, #0 800df70: 63fb str r3, [r7, #60] @ 0x3c } break; 800df72: e2e2 b.n 800e53a 800df74: e2e1 b.n 800e53a } case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ { frequency = EXTERNAL_CLOCK_VALUE; 800df76: 4b05 ldr r3, [pc, #20] @ (800df8c ) 800df78: 63fb str r3, [r7, #60] @ 0x3c break; 800df7a: e2de b.n 800e53a 800df7c: 58024400 .word 0x58024400 800df80: 03d09000 .word 0x03d09000 800df84: 003d0900 .word 0x003d0900 800df88: 017d7840 .word 0x017d7840 800df8c: 00bb8000 .word 0x00bb8000 } default : { frequency = 0; 800df90: 2300 movs r3, #0 800df92: 63fb str r3, [r7, #60] @ 0x3c break; 800df94: e2d1 b.n 800e53a } } } #endif /*SAI4*/ else if (PeriphClk == RCC_PERIPHCLK_SPI123) 800df96: e9d7 2300 ldrd r2, r3, [r7] 800df9a: f5a2 5180 sub.w r1, r2, #4096 @ 0x1000 800df9e: 430b orrs r3, r1 800dfa0: f040 809c bne.w 800e0dc { /* Get SPI1/2/3 clock source */ srcclk = __HAL_RCC_GET_SPI123_SOURCE(); 800dfa4: 4b93 ldr r3, [pc, #588] @ (800e1f4 ) 800dfa6: 6d1b ldr r3, [r3, #80] @ 0x50 800dfa8: f403 43e0 and.w r3, r3, #28672 @ 0x7000 800dfac: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800dfae: 6bbb ldr r3, [r7, #56] @ 0x38 800dfb0: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800dfb4: d054 beq.n 800e060 800dfb6: 6bbb ldr r3, [r7, #56] @ 0x38 800dfb8: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800dfbc: f200 808b bhi.w 800e0d6 800dfc0: 6bbb ldr r3, [r7, #56] @ 0x38 800dfc2: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800dfc6: f000 8083 beq.w 800e0d0 800dfca: 6bbb ldr r3, [r7, #56] @ 0x38 800dfcc: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800dfd0: f200 8081 bhi.w 800e0d6 800dfd4: 6bbb ldr r3, [r7, #56] @ 0x38 800dfd6: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800dfda: d02f beq.n 800e03c 800dfdc: 6bbb ldr r3, [r7, #56] @ 0x38 800dfde: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800dfe2: d878 bhi.n 800e0d6 800dfe4: 6bbb ldr r3, [r7, #56] @ 0x38 800dfe6: 2b00 cmp r3, #0 800dfe8: d004 beq.n 800dff4 800dfea: 6bbb ldr r3, [r7, #56] @ 0x38 800dfec: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800dff0: d012 beq.n 800e018 800dff2: e070 b.n 800e0d6 { case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800dff4: 4b7f ldr r3, [pc, #508] @ (800e1f4 ) 800dff6: 681b ldr r3, [r3, #0] 800dff8: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800dffc: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e000: d107 bne.n 800e012 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e002: f107 0324 add.w r3, r7, #36 @ 0x24 800e006: 4618 mov r0, r3 800e008: f000 fd5e bl 800eac8 frequency = pll1_clocks.PLL1_Q_Frequency; 800e00c: 6abb ldr r3, [r7, #40] @ 0x28 800e00e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e010: e293 b.n 800e53a frequency = 0; 800e012: 2300 movs r3, #0 800e014: 63fb str r3, [r7, #60] @ 0x3c break; 800e016: e290 b.n 800e53a } case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e018: 4b76 ldr r3, [pc, #472] @ (800e1f4 ) 800e01a: 681b ldr r3, [r3, #0] 800e01c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e020: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e024: d107 bne.n 800e036 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e026: f107 0318 add.w r3, r7, #24 800e02a: 4618 mov r0, r3 800e02c: f000 faa4 bl 800e578 frequency = pll2_clocks.PLL2_P_Frequency; 800e030: 69bb ldr r3, [r7, #24] 800e032: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e034: e281 b.n 800e53a frequency = 0; 800e036: 2300 movs r3, #0 800e038: 63fb str r3, [r7, #60] @ 0x3c break; 800e03a: e27e b.n 800e53a } case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e03c: 4b6d ldr r3, [pc, #436] @ (800e1f4 ) 800e03e: 681b ldr r3, [r3, #0] 800e040: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e044: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e048: d107 bne.n 800e05a { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e04a: f107 030c add.w r3, r7, #12 800e04e: 4618 mov r0, r3 800e050: f000 fbe6 bl 800e820 frequency = pll3_clocks.PLL3_P_Frequency; 800e054: 68fb ldr r3, [r7, #12] 800e056: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e058: e26f b.n 800e53a frequency = 0; 800e05a: 2300 movs r3, #0 800e05c: 63fb str r3, [r7, #60] @ 0x3c break; 800e05e: e26c b.n 800e53a } case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e060: 4b64 ldr r3, [pc, #400] @ (800e1f4 ) 800e062: 6cdb ldr r3, [r3, #76] @ 0x4c 800e064: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e068: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e06a: 4b62 ldr r3, [pc, #392] @ (800e1f4 ) 800e06c: 681b ldr r3, [r3, #0] 800e06e: f003 0304 and.w r3, r3, #4 800e072: 2b04 cmp r3, #4 800e074: d10c bne.n 800e090 800e076: 6b7b ldr r3, [r7, #52] @ 0x34 800e078: 2b00 cmp r3, #0 800e07a: d109 bne.n 800e090 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e07c: 4b5d ldr r3, [pc, #372] @ (800e1f4 ) 800e07e: 681b ldr r3, [r3, #0] 800e080: 08db lsrs r3, r3, #3 800e082: f003 0303 and.w r3, r3, #3 800e086: 4a5c ldr r2, [pc, #368] @ (800e1f8 ) 800e088: fa22 f303 lsr.w r3, r2, r3 800e08c: 63fb str r3, [r7, #60] @ 0x3c 800e08e: e01e b.n 800e0ce } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e090: 4b58 ldr r3, [pc, #352] @ (800e1f4 ) 800e092: 681b ldr r3, [r3, #0] 800e094: f403 7380 and.w r3, r3, #256 @ 0x100 800e098: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e09c: d106 bne.n 800e0ac 800e09e: 6b7b ldr r3, [r7, #52] @ 0x34 800e0a0: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e0a4: d102 bne.n 800e0ac { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e0a6: 4b55 ldr r3, [pc, #340] @ (800e1fc ) 800e0a8: 63fb str r3, [r7, #60] @ 0x3c 800e0aa: e010 b.n 800e0ce } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e0ac: 4b51 ldr r3, [pc, #324] @ (800e1f4 ) 800e0ae: 681b ldr r3, [r3, #0] 800e0b0: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e0b4: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e0b8: d106 bne.n 800e0c8 800e0ba: 6b7b ldr r3, [r7, #52] @ 0x34 800e0bc: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e0c0: d102 bne.n 800e0c8 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e0c2: 4b4f ldr r3, [pc, #316] @ (800e200 ) 800e0c4: 63fb str r3, [r7, #60] @ 0x3c 800e0c6: e002 b.n 800e0ce } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e0c8: 2300 movs r3, #0 800e0ca: 63fb str r3, [r7, #60] @ 0x3c } break; 800e0cc: e235 b.n 800e53a 800e0ce: e234 b.n 800e53a } case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ { frequency = EXTERNAL_CLOCK_VALUE; 800e0d0: 4b4c ldr r3, [pc, #304] @ (800e204 ) 800e0d2: 63fb str r3, [r7, #60] @ 0x3c break; 800e0d4: e231 b.n 800e53a } default : { frequency = 0; 800e0d6: 2300 movs r3, #0 800e0d8: 63fb str r3, [r7, #60] @ 0x3c break; 800e0da: e22e b.n 800e53a } } } else if (PeriphClk == RCC_PERIPHCLK_SPI45) 800e0dc: e9d7 2300 ldrd r2, r3, [r7] 800e0e0: f5a2 5100 sub.w r1, r2, #8192 @ 0x2000 800e0e4: 430b orrs r3, r1 800e0e6: f040 808f bne.w 800e208 { /* Get SPI45 clock source */ srcclk = __HAL_RCC_GET_SPI45_SOURCE(); 800e0ea: 4b42 ldr r3, [pc, #264] @ (800e1f4 ) 800e0ec: 6d1b ldr r3, [r3, #80] @ 0x50 800e0ee: f403 23e0 and.w r3, r3, #458752 @ 0x70000 800e0f2: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e0f4: 6bbb ldr r3, [r7, #56] @ 0x38 800e0f6: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800e0fa: d06b beq.n 800e1d4 800e0fc: 6bbb ldr r3, [r7, #56] @ 0x38 800e0fe: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800e102: d874 bhi.n 800e1ee 800e104: 6bbb ldr r3, [r7, #56] @ 0x38 800e106: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800e10a: d056 beq.n 800e1ba 800e10c: 6bbb ldr r3, [r7, #56] @ 0x38 800e10e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800e112: d86c bhi.n 800e1ee 800e114: 6bbb ldr r3, [r7, #56] @ 0x38 800e116: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800e11a: d03b beq.n 800e194 800e11c: 6bbb ldr r3, [r7, #56] @ 0x38 800e11e: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800e122: d864 bhi.n 800e1ee 800e124: 6bbb ldr r3, [r7, #56] @ 0x38 800e126: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e12a: d021 beq.n 800e170 800e12c: 6bbb ldr r3, [r7, #56] @ 0x38 800e12e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e132: d85c bhi.n 800e1ee 800e134: 6bbb ldr r3, [r7, #56] @ 0x38 800e136: 2b00 cmp r3, #0 800e138: d004 beq.n 800e144 800e13a: 6bbb ldr r3, [r7, #56] @ 0x38 800e13c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e140: d004 beq.n 800e14c 800e142: e054 b.n 800e1ee { case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */ { frequency = HAL_RCC_GetPCLK1Freq(); 800e144: f7fe fa26 bl 800c594 800e148: 63f8 str r0, [r7, #60] @ 0x3c break; 800e14a: e1f6 b.n 800e53a } case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e14c: 4b29 ldr r3, [pc, #164] @ (800e1f4 ) 800e14e: 681b ldr r3, [r3, #0] 800e150: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e154: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e158: d107 bne.n 800e16a { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e15a: f107 0318 add.w r3, r7, #24 800e15e: 4618 mov r0, r3 800e160: f000 fa0a bl 800e578 frequency = pll2_clocks.PLL2_Q_Frequency; 800e164: 69fb ldr r3, [r7, #28] 800e166: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e168: e1e7 b.n 800e53a frequency = 0; 800e16a: 2300 movs r3, #0 800e16c: 63fb str r3, [r7, #60] @ 0x3c break; 800e16e: e1e4 b.n 800e53a } case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e170: 4b20 ldr r3, [pc, #128] @ (800e1f4 ) 800e172: 681b ldr r3, [r3, #0] 800e174: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e178: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e17c: d107 bne.n 800e18e { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e17e: f107 030c add.w r3, r7, #12 800e182: 4618 mov r0, r3 800e184: f000 fb4c bl 800e820 frequency = pll3_clocks.PLL3_Q_Frequency; 800e188: 693b ldr r3, [r7, #16] 800e18a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e18c: e1d5 b.n 800e53a frequency = 0; 800e18e: 2300 movs r3, #0 800e190: 63fb str r3, [r7, #60] @ 0x3c break; 800e192: e1d2 b.n 800e53a } case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800e194: 4b17 ldr r3, [pc, #92] @ (800e1f4 ) 800e196: 681b ldr r3, [r3, #0] 800e198: f003 0304 and.w r3, r3, #4 800e19c: 2b04 cmp r3, #4 800e19e: d109 bne.n 800e1b4 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e1a0: 4b14 ldr r3, [pc, #80] @ (800e1f4 ) 800e1a2: 681b ldr r3, [r3, #0] 800e1a4: 08db lsrs r3, r3, #3 800e1a6: f003 0303 and.w r3, r3, #3 800e1aa: 4a13 ldr r2, [pc, #76] @ (800e1f8 ) 800e1ac: fa22 f303 lsr.w r3, r2, r3 800e1b0: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e1b2: e1c2 b.n 800e53a frequency = 0; 800e1b4: 2300 movs r3, #0 800e1b6: 63fb str r3, [r7, #60] @ 0x3c break; 800e1b8: e1bf b.n 800e53a } case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 800e1ba: 4b0e ldr r3, [pc, #56] @ (800e1f4 ) 800e1bc: 681b ldr r3, [r3, #0] 800e1be: f403 7380 and.w r3, r3, #256 @ 0x100 800e1c2: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e1c6: d102 bne.n 800e1ce { frequency = CSI_VALUE; 800e1c8: 4b0c ldr r3, [pc, #48] @ (800e1fc ) 800e1ca: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e1cc: e1b5 b.n 800e53a frequency = 0; 800e1ce: 2300 movs r3, #0 800e1d0: 63fb str r3, [r7, #60] @ 0x3c break; 800e1d2: e1b2 b.n 800e53a } case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e1d4: 4b07 ldr r3, [pc, #28] @ (800e1f4 ) 800e1d6: 681b ldr r3, [r3, #0] 800e1d8: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e1dc: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e1e0: d102 bne.n 800e1e8 { frequency = HSE_VALUE; 800e1e2: 4b07 ldr r3, [pc, #28] @ (800e200 ) 800e1e4: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e1e6: e1a8 b.n 800e53a frequency = 0; 800e1e8: 2300 movs r3, #0 800e1ea: 63fb str r3, [r7, #60] @ 0x3c break; 800e1ec: e1a5 b.n 800e53a } default : { frequency = 0; 800e1ee: 2300 movs r3, #0 800e1f0: 63fb str r3, [r7, #60] @ 0x3c break; 800e1f2: e1a2 b.n 800e53a 800e1f4: 58024400 .word 0x58024400 800e1f8: 03d09000 .word 0x03d09000 800e1fc: 003d0900 .word 0x003d0900 800e200: 017d7840 .word 0x017d7840 800e204: 00bb8000 .word 0x00bb8000 } } } else if (PeriphClk == RCC_PERIPHCLK_ADC) 800e208: e9d7 2300 ldrd r2, r3, [r7] 800e20c: f5a2 2100 sub.w r1, r2, #524288 @ 0x80000 800e210: 430b orrs r3, r1 800e212: d173 bne.n 800e2fc { /* Get ADC clock source */ srcclk = __HAL_RCC_GET_ADC_SOURCE(); 800e214: 4b9c ldr r3, [pc, #624] @ (800e488 ) 800e216: 6d9b ldr r3, [r3, #88] @ 0x58 800e218: f403 3340 and.w r3, r3, #196608 @ 0x30000 800e21c: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e21e: 6bbb ldr r3, [r7, #56] @ 0x38 800e220: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e224: d02f beq.n 800e286 800e226: 6bbb ldr r3, [r7, #56] @ 0x38 800e228: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e22c: d863 bhi.n 800e2f6 800e22e: 6bbb ldr r3, [r7, #56] @ 0x38 800e230: 2b00 cmp r3, #0 800e232: d004 beq.n 800e23e 800e234: 6bbb ldr r3, [r7, #56] @ 0x38 800e236: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e23a: d012 beq.n 800e262 800e23c: e05b b.n 800e2f6 { case RCC_ADCCLKSOURCE_PLL2: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e23e: 4b92 ldr r3, [pc, #584] @ (800e488 ) 800e240: 681b ldr r3, [r3, #0] 800e242: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e246: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e24a: d107 bne.n 800e25c { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e24c: f107 0318 add.w r3, r7, #24 800e250: 4618 mov r0, r3 800e252: f000 f991 bl 800e578 frequency = pll2_clocks.PLL2_P_Frequency; 800e256: 69bb ldr r3, [r7, #24] 800e258: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e25a: e16e b.n 800e53a frequency = 0; 800e25c: 2300 movs r3, #0 800e25e: 63fb str r3, [r7, #60] @ 0x3c break; 800e260: e16b b.n 800e53a } case RCC_ADCCLKSOURCE_PLL3: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e262: 4b89 ldr r3, [pc, #548] @ (800e488 ) 800e264: 681b ldr r3, [r3, #0] 800e266: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e26a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e26e: d107 bne.n 800e280 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e270: f107 030c add.w r3, r7, #12 800e274: 4618 mov r0, r3 800e276: f000 fad3 bl 800e820 frequency = pll3_clocks.PLL3_R_Frequency; 800e27a: 697b ldr r3, [r7, #20] 800e27c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e27e: e15c b.n 800e53a frequency = 0; 800e280: 2300 movs r3, #0 800e282: 63fb str r3, [r7, #60] @ 0x3c break; 800e284: e159 b.n 800e53a } case RCC_ADCCLKSOURCE_CLKP: { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e286: 4b80 ldr r3, [pc, #512] @ (800e488 ) 800e288: 6cdb ldr r3, [r3, #76] @ 0x4c 800e28a: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e28e: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e290: 4b7d ldr r3, [pc, #500] @ (800e488 ) 800e292: 681b ldr r3, [r3, #0] 800e294: f003 0304 and.w r3, r3, #4 800e298: 2b04 cmp r3, #4 800e29a: d10c bne.n 800e2b6 800e29c: 6b7b ldr r3, [r7, #52] @ 0x34 800e29e: 2b00 cmp r3, #0 800e2a0: d109 bne.n 800e2b6 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e2a2: 4b79 ldr r3, [pc, #484] @ (800e488 ) 800e2a4: 681b ldr r3, [r3, #0] 800e2a6: 08db lsrs r3, r3, #3 800e2a8: f003 0303 and.w r3, r3, #3 800e2ac: 4a77 ldr r2, [pc, #476] @ (800e48c ) 800e2ae: fa22 f303 lsr.w r3, r2, r3 800e2b2: 63fb str r3, [r7, #60] @ 0x3c 800e2b4: e01e b.n 800e2f4 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e2b6: 4b74 ldr r3, [pc, #464] @ (800e488 ) 800e2b8: 681b ldr r3, [r3, #0] 800e2ba: f403 7380 and.w r3, r3, #256 @ 0x100 800e2be: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e2c2: d106 bne.n 800e2d2 800e2c4: 6b7b ldr r3, [r7, #52] @ 0x34 800e2c6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e2ca: d102 bne.n 800e2d2 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e2cc: 4b70 ldr r3, [pc, #448] @ (800e490 ) 800e2ce: 63fb str r3, [r7, #60] @ 0x3c 800e2d0: e010 b.n 800e2f4 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e2d2: 4b6d ldr r3, [pc, #436] @ (800e488 ) 800e2d4: 681b ldr r3, [r3, #0] 800e2d6: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e2da: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e2de: d106 bne.n 800e2ee 800e2e0: 6b7b ldr r3, [r7, #52] @ 0x34 800e2e2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e2e6: d102 bne.n 800e2ee { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e2e8: 4b6a ldr r3, [pc, #424] @ (800e494 ) 800e2ea: 63fb str r3, [r7, #60] @ 0x3c 800e2ec: e002 b.n 800e2f4 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e2ee: 2300 movs r3, #0 800e2f0: 63fb str r3, [r7, #60] @ 0x3c } break; 800e2f2: e122 b.n 800e53a 800e2f4: e121 b.n 800e53a } default : { frequency = 0; 800e2f6: 2300 movs r3, #0 800e2f8: 63fb str r3, [r7, #60] @ 0x3c break; 800e2fa: e11e b.n 800e53a } } } else if (PeriphClk == RCC_PERIPHCLK_SDMMC) 800e2fc: e9d7 2300 ldrd r2, r3, [r7] 800e300: f5a2 3180 sub.w r1, r2, #65536 @ 0x10000 800e304: 430b orrs r3, r1 800e306: d133 bne.n 800e370 { /* Get SDMMC clock source */ srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); 800e308: 4b5f ldr r3, [pc, #380] @ (800e488 ) 800e30a: 6cdb ldr r3, [r3, #76] @ 0x4c 800e30c: f403 3380 and.w r3, r3, #65536 @ 0x10000 800e310: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e312: 6bbb ldr r3, [r7, #56] @ 0x38 800e314: 2b00 cmp r3, #0 800e316: d004 beq.n 800e322 800e318: 6bbb ldr r3, [r7, #56] @ 0x38 800e31a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e31e: d012 beq.n 800e346 800e320: e023 b.n 800e36a { case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e322: 4b59 ldr r3, [pc, #356] @ (800e488 ) 800e324: 681b ldr r3, [r3, #0] 800e326: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e32a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e32e: d107 bne.n 800e340 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e330: f107 0324 add.w r3, r7, #36 @ 0x24 800e334: 4618 mov r0, r3 800e336: f000 fbc7 bl 800eac8 frequency = pll1_clocks.PLL1_Q_Frequency; 800e33a: 6abb ldr r3, [r7, #40] @ 0x28 800e33c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e33e: e0fc b.n 800e53a frequency = 0; 800e340: 2300 movs r3, #0 800e342: 63fb str r3, [r7, #60] @ 0x3c break; 800e344: e0f9 b.n 800e53a } case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e346: 4b50 ldr r3, [pc, #320] @ (800e488 ) 800e348: 681b ldr r3, [r3, #0] 800e34a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e34e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e352: d107 bne.n 800e364 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e354: f107 0318 add.w r3, r7, #24 800e358: 4618 mov r0, r3 800e35a: f000 f90d bl 800e578 frequency = pll2_clocks.PLL2_R_Frequency; 800e35e: 6a3b ldr r3, [r7, #32] 800e360: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e362: e0ea b.n 800e53a frequency = 0; 800e364: 2300 movs r3, #0 800e366: 63fb str r3, [r7, #60] @ 0x3c break; 800e368: e0e7 b.n 800e53a } default : { frequency = 0; 800e36a: 2300 movs r3, #0 800e36c: 63fb str r3, [r7, #60] @ 0x3c break; 800e36e: e0e4 b.n 800e53a } } } else if (PeriphClk == RCC_PERIPHCLK_SPI6) 800e370: e9d7 2300 ldrd r2, r3, [r7] 800e374: f5a2 4180 sub.w r1, r2, #16384 @ 0x4000 800e378: 430b orrs r3, r1 800e37a: f040 808d bne.w 800e498 { /* Get SPI6 clock source */ srcclk = __HAL_RCC_GET_SPI6_SOURCE(); 800e37e: 4b42 ldr r3, [pc, #264] @ (800e488 ) 800e380: 6d9b ldr r3, [r3, #88] @ 0x58 800e382: f003 43e0 and.w r3, r3, #1879048192 @ 0x70000000 800e386: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e388: 6bbb ldr r3, [r7, #56] @ 0x38 800e38a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800e38e: d06b beq.n 800e468 800e390: 6bbb ldr r3, [r7, #56] @ 0x38 800e392: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800e396: d874 bhi.n 800e482 800e398: 6bbb ldr r3, [r7, #56] @ 0x38 800e39a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800e39e: d056 beq.n 800e44e 800e3a0: 6bbb ldr r3, [r7, #56] @ 0x38 800e3a2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800e3a6: d86c bhi.n 800e482 800e3a8: 6bbb ldr r3, [r7, #56] @ 0x38 800e3aa: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800e3ae: d03b beq.n 800e428 800e3b0: 6bbb ldr r3, [r7, #56] @ 0x38 800e3b2: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800e3b6: d864 bhi.n 800e482 800e3b8: 6bbb ldr r3, [r7, #56] @ 0x38 800e3ba: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e3be: d021 beq.n 800e404 800e3c0: 6bbb ldr r3, [r7, #56] @ 0x38 800e3c2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e3c6: d85c bhi.n 800e482 800e3c8: 6bbb ldr r3, [r7, #56] @ 0x38 800e3ca: 2b00 cmp r3, #0 800e3cc: d004 beq.n 800e3d8 800e3ce: 6bbb ldr r3, [r7, #56] @ 0x38 800e3d0: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e3d4: d004 beq.n 800e3e0 800e3d6: e054 b.n 800e482 { case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ { frequency = HAL_RCCEx_GetD3PCLK1Freq(); 800e3d8: f000 f8b8 bl 800e54c 800e3dc: 63f8 str r0, [r7, #60] @ 0x3c break; 800e3de: e0ac b.n 800e53a } case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e3e0: 4b29 ldr r3, [pc, #164] @ (800e488 ) 800e3e2: 681b ldr r3, [r3, #0] 800e3e4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e3e8: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e3ec: d107 bne.n 800e3fe { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e3ee: f107 0318 add.w r3, r7, #24 800e3f2: 4618 mov r0, r3 800e3f4: f000 f8c0 bl 800e578 frequency = pll2_clocks.PLL2_Q_Frequency; 800e3f8: 69fb ldr r3, [r7, #28] 800e3fa: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e3fc: e09d b.n 800e53a frequency = 0; 800e3fe: 2300 movs r3, #0 800e400: 63fb str r3, [r7, #60] @ 0x3c break; 800e402: e09a b.n 800e53a } case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e404: 4b20 ldr r3, [pc, #128] @ (800e488 ) 800e406: 681b ldr r3, [r3, #0] 800e408: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e40c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e410: d107 bne.n 800e422 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e412: f107 030c add.w r3, r7, #12 800e416: 4618 mov r0, r3 800e418: f000 fa02 bl 800e820 frequency = pll3_clocks.PLL3_Q_Frequency; 800e41c: 693b ldr r3, [r7, #16] 800e41e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e420: e08b b.n 800e53a frequency = 0; 800e422: 2300 movs r3, #0 800e424: 63fb str r3, [r7, #60] @ 0x3c break; 800e426: e088 b.n 800e53a } case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800e428: 4b17 ldr r3, [pc, #92] @ (800e488 ) 800e42a: 681b ldr r3, [r3, #0] 800e42c: f003 0304 and.w r3, r3, #4 800e430: 2b04 cmp r3, #4 800e432: d109 bne.n 800e448 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e434: 4b14 ldr r3, [pc, #80] @ (800e488 ) 800e436: 681b ldr r3, [r3, #0] 800e438: 08db lsrs r3, r3, #3 800e43a: f003 0303 and.w r3, r3, #3 800e43e: 4a13 ldr r2, [pc, #76] @ (800e48c ) 800e440: fa22 f303 lsr.w r3, r2, r3 800e444: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e446: e078 b.n 800e53a frequency = 0; 800e448: 2300 movs r3, #0 800e44a: 63fb str r3, [r7, #60] @ 0x3c break; 800e44c: e075 b.n 800e53a } case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 800e44e: 4b0e ldr r3, [pc, #56] @ (800e488 ) 800e450: 681b ldr r3, [r3, #0] 800e452: f403 7380 and.w r3, r3, #256 @ 0x100 800e456: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e45a: d102 bne.n 800e462 { frequency = CSI_VALUE; 800e45c: 4b0c ldr r3, [pc, #48] @ (800e490 ) 800e45e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e460: e06b b.n 800e53a frequency = 0; 800e462: 2300 movs r3, #0 800e464: 63fb str r3, [r7, #60] @ 0x3c break; 800e466: e068 b.n 800e53a } case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e468: 4b07 ldr r3, [pc, #28] @ (800e488 ) 800e46a: 681b ldr r3, [r3, #0] 800e46c: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e470: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e474: d102 bne.n 800e47c { frequency = HSE_VALUE; 800e476: 4b07 ldr r3, [pc, #28] @ (800e494 ) 800e478: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e47a: e05e b.n 800e53a frequency = 0; 800e47c: 2300 movs r3, #0 800e47e: 63fb str r3, [r7, #60] @ 0x3c break; 800e480: e05b b.n 800e53a break; } #endif /* RCC_SPI6CLKSOURCE_PIN */ default : { frequency = 0; 800e482: 2300 movs r3, #0 800e484: 63fb str r3, [r7, #60] @ 0x3c break; 800e486: e058 b.n 800e53a 800e488: 58024400 .word 0x58024400 800e48c: 03d09000 .word 0x03d09000 800e490: 003d0900 .word 0x003d0900 800e494: 017d7840 .word 0x017d7840 } } } else if (PeriphClk == RCC_PERIPHCLK_FDCAN) 800e498: e9d7 2300 ldrd r2, r3, [r7] 800e49c: f5a2 4100 sub.w r1, r2, #32768 @ 0x8000 800e4a0: 430b orrs r3, r1 800e4a2: d148 bne.n 800e536 { /* Get FDCAN clock source */ srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); 800e4a4: 4b27 ldr r3, [pc, #156] @ (800e544 ) 800e4a6: 6d1b ldr r3, [r3, #80] @ 0x50 800e4a8: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e4ac: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e4ae: 6bbb ldr r3, [r7, #56] @ 0x38 800e4b0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e4b4: d02a beq.n 800e50c 800e4b6: 6bbb ldr r3, [r7, #56] @ 0x38 800e4b8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e4bc: d838 bhi.n 800e530 800e4be: 6bbb ldr r3, [r7, #56] @ 0x38 800e4c0: 2b00 cmp r3, #0 800e4c2: d004 beq.n 800e4ce 800e4c4: 6bbb ldr r3, [r7, #56] @ 0x38 800e4c6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e4ca: d00d beq.n 800e4e8 800e4cc: e030 b.n 800e530 { case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e4ce: 4b1d ldr r3, [pc, #116] @ (800e544 ) 800e4d0: 681b ldr r3, [r3, #0] 800e4d2: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e4d6: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e4da: d102 bne.n 800e4e2 { frequency = HSE_VALUE; 800e4dc: 4b1a ldr r3, [pc, #104] @ (800e548 ) 800e4de: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e4e0: e02b b.n 800e53a frequency = 0; 800e4e2: 2300 movs r3, #0 800e4e4: 63fb str r3, [r7, #60] @ 0x3c break; 800e4e6: e028 b.n 800e53a } case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e4e8: 4b16 ldr r3, [pc, #88] @ (800e544 ) 800e4ea: 681b ldr r3, [r3, #0] 800e4ec: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e4f0: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e4f4: d107 bne.n 800e506 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e4f6: f107 0324 add.w r3, r7, #36 @ 0x24 800e4fa: 4618 mov r0, r3 800e4fc: f000 fae4 bl 800eac8 frequency = pll1_clocks.PLL1_Q_Frequency; 800e500: 6abb ldr r3, [r7, #40] @ 0x28 800e502: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e504: e019 b.n 800e53a frequency = 0; 800e506: 2300 movs r3, #0 800e508: 63fb str r3, [r7, #60] @ 0x3c break; 800e50a: e016 b.n 800e53a } case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e50c: 4b0d ldr r3, [pc, #52] @ (800e544 ) 800e50e: 681b ldr r3, [r3, #0] 800e510: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e514: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e518: d107 bne.n 800e52a { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e51a: f107 0318 add.w r3, r7, #24 800e51e: 4618 mov r0, r3 800e520: f000 f82a bl 800e578 frequency = pll2_clocks.PLL2_Q_Frequency; 800e524: 69fb ldr r3, [r7, #28] 800e526: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e528: e007 b.n 800e53a frequency = 0; 800e52a: 2300 movs r3, #0 800e52c: 63fb str r3, [r7, #60] @ 0x3c break; 800e52e: e004 b.n 800e53a } default : { frequency = 0; 800e530: 2300 movs r3, #0 800e532: 63fb str r3, [r7, #60] @ 0x3c break; 800e534: e001 b.n 800e53a } } } else { frequency = 0; 800e536: 2300 movs r3, #0 800e538: 63fb str r3, [r7, #60] @ 0x3c } return frequency; 800e53a: 6bfb ldr r3, [r7, #60] @ 0x3c } 800e53c: 4618 mov r0, r3 800e53e: 3740 adds r7, #64 @ 0x40 800e540: 46bd mov sp, r7 800e542: bd80 pop {r7, pc} 800e544: 58024400 .word 0x58024400 800e548: 017d7840 .word 0x017d7840 0800e54c : * @note Each time D3PCLK1 changes, this function must be called to update the * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval D3PCLK1 frequency */ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) { 800e54c: b580 push {r7, lr} 800e54e: af00 add r7, sp, #0 #if defined(RCC_D3CFGR_D3PPRE) /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); 800e550: f7fd fff0 bl 800c534 800e554: 4602 mov r2, r0 800e556: 4b06 ldr r3, [pc, #24] @ (800e570 ) 800e558: 6a1b ldr r3, [r3, #32] 800e55a: 091b lsrs r3, r3, #4 800e55c: f003 0307 and.w r3, r3, #7 800e560: 4904 ldr r1, [pc, #16] @ (800e574 ) 800e562: 5ccb ldrb r3, [r1, r3] 800e564: f003 031f and.w r3, r3, #31 800e568: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); #endif } 800e56c: 4618 mov r0, r3 800e56e: bd80 pop {r7, pc} 800e570: 58024400 .word 0x58024400 800e574: 08018b5c .word 0x08018b5c 0800e578 : * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL2_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) { 800e578: b480 push {r7} 800e57a: b089 sub sp, #36 @ 0x24 800e57c: af00 add r7, sp, #0 800e57e: 6078 str r0, [r7, #4] float_t fracn2, pll2vco; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N PLL2xCLK = PLL2_VCO / PLL2x */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800e580: 4ba1 ldr r3, [pc, #644] @ (800e808 ) 800e582: 6a9b ldr r3, [r3, #40] @ 0x28 800e584: f003 0303 and.w r3, r3, #3 800e588: 61bb str r3, [r7, #24] pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); 800e58a: 4b9f ldr r3, [pc, #636] @ (800e808 ) 800e58c: 6a9b ldr r3, [r3, #40] @ 0x28 800e58e: 0b1b lsrs r3, r3, #12 800e590: f003 033f and.w r3, r3, #63 @ 0x3f 800e594: 617b str r3, [r7, #20] pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; 800e596: 4b9c ldr r3, [pc, #624] @ (800e808 ) 800e598: 6adb ldr r3, [r3, #44] @ 0x2c 800e59a: 091b lsrs r3, r3, #4 800e59c: f003 0301 and.w r3, r3, #1 800e5a0: 613b str r3, [r7, #16] fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); 800e5a2: 4b99 ldr r3, [pc, #612] @ (800e808 ) 800e5a4: 6bdb ldr r3, [r3, #60] @ 0x3c 800e5a6: 08db lsrs r3, r3, #3 800e5a8: f3c3 030c ubfx r3, r3, #0, #13 800e5ac: 693a ldr r2, [r7, #16] 800e5ae: fb02 f303 mul.w r3, r2, r3 800e5b2: ee07 3a90 vmov s15, r3 800e5b6: eef8 7a67 vcvt.f32.u32 s15, s15 800e5ba: edc7 7a03 vstr s15, [r7, #12] if (pll2m != 0U) 800e5be: 697b ldr r3, [r7, #20] 800e5c0: 2b00 cmp r3, #0 800e5c2: f000 8111 beq.w 800e7e8 { switch (pllsource) 800e5c6: 69bb ldr r3, [r7, #24] 800e5c8: 2b02 cmp r3, #2 800e5ca: f000 8083 beq.w 800e6d4 800e5ce: 69bb ldr r3, [r7, #24] 800e5d0: 2b02 cmp r3, #2 800e5d2: f200 80a1 bhi.w 800e718 800e5d6: 69bb ldr r3, [r7, #24] 800e5d8: 2b00 cmp r3, #0 800e5da: d003 beq.n 800e5e4 800e5dc: 69bb ldr r3, [r7, #24] 800e5de: 2b01 cmp r3, #1 800e5e0: d056 beq.n 800e690 800e5e2: e099 b.n 800e718 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800e5e4: 4b88 ldr r3, [pc, #544] @ (800e808 ) 800e5e6: 681b ldr r3, [r3, #0] 800e5e8: f003 0320 and.w r3, r3, #32 800e5ec: 2b00 cmp r3, #0 800e5ee: d02d beq.n 800e64c { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e5f0: 4b85 ldr r3, [pc, #532] @ (800e808 ) 800e5f2: 681b ldr r3, [r3, #0] 800e5f4: 08db lsrs r3, r3, #3 800e5f6: f003 0303 and.w r3, r3, #3 800e5fa: 4a84 ldr r2, [pc, #528] @ (800e80c ) 800e5fc: fa22 f303 lsr.w r3, r2, r3 800e600: 60bb str r3, [r7, #8] pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e602: 68bb ldr r3, [r7, #8] 800e604: ee07 3a90 vmov s15, r3 800e608: eef8 6a67 vcvt.f32.u32 s13, s15 800e60c: 697b ldr r3, [r7, #20] 800e60e: ee07 3a90 vmov s15, r3 800e612: eef8 7a67 vcvt.f32.u32 s15, s15 800e616: ee86 7aa7 vdiv.f32 s14, s13, s15 800e61a: 4b7b ldr r3, [pc, #492] @ (800e808 ) 800e61c: 6b9b ldr r3, [r3, #56] @ 0x38 800e61e: f3c3 0308 ubfx r3, r3, #0, #9 800e622: ee07 3a90 vmov s15, r3 800e626: eef8 6a67 vcvt.f32.u32 s13, s15 800e62a: ed97 6a03 vldr s12, [r7, #12] 800e62e: eddf 5a78 vldr s11, [pc, #480] @ 800e810 800e632: eec6 7a25 vdiv.f32 s15, s12, s11 800e636: ee76 7aa7 vadd.f32 s15, s13, s15 800e63a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e63e: ee77 7aa6 vadd.f32 s15, s15, s13 800e642: ee67 7a27 vmul.f32 s15, s14, s15 800e646: edc7 7a07 vstr s15, [r7, #28] } else { pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); } break; 800e64a: e087 b.n 800e75c pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e64c: 697b ldr r3, [r7, #20] 800e64e: ee07 3a90 vmov s15, r3 800e652: eef8 7a67 vcvt.f32.u32 s15, s15 800e656: eddf 6a6f vldr s13, [pc, #444] @ 800e814 800e65a: ee86 7aa7 vdiv.f32 s14, s13, s15 800e65e: 4b6a ldr r3, [pc, #424] @ (800e808 ) 800e660: 6b9b ldr r3, [r3, #56] @ 0x38 800e662: f3c3 0308 ubfx r3, r3, #0, #9 800e666: ee07 3a90 vmov s15, r3 800e66a: eef8 6a67 vcvt.f32.u32 s13, s15 800e66e: ed97 6a03 vldr s12, [r7, #12] 800e672: eddf 5a67 vldr s11, [pc, #412] @ 800e810 800e676: eec6 7a25 vdiv.f32 s15, s12, s11 800e67a: ee76 7aa7 vadd.f32 s15, s13, s15 800e67e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e682: ee77 7aa6 vadd.f32 s15, s15, s13 800e686: ee67 7a27 vmul.f32 s15, s14, s15 800e68a: edc7 7a07 vstr s15, [r7, #28] break; 800e68e: e065 b.n 800e75c case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e690: 697b ldr r3, [r7, #20] 800e692: ee07 3a90 vmov s15, r3 800e696: eef8 7a67 vcvt.f32.u32 s15, s15 800e69a: eddf 6a5f vldr s13, [pc, #380] @ 800e818 800e69e: ee86 7aa7 vdiv.f32 s14, s13, s15 800e6a2: 4b59 ldr r3, [pc, #356] @ (800e808 ) 800e6a4: 6b9b ldr r3, [r3, #56] @ 0x38 800e6a6: f3c3 0308 ubfx r3, r3, #0, #9 800e6aa: ee07 3a90 vmov s15, r3 800e6ae: eef8 6a67 vcvt.f32.u32 s13, s15 800e6b2: ed97 6a03 vldr s12, [r7, #12] 800e6b6: eddf 5a56 vldr s11, [pc, #344] @ 800e810 800e6ba: eec6 7a25 vdiv.f32 s15, s12, s11 800e6be: ee76 7aa7 vadd.f32 s15, s13, s15 800e6c2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e6c6: ee77 7aa6 vadd.f32 s15, s15, s13 800e6ca: ee67 7a27 vmul.f32 s15, s14, s15 800e6ce: edc7 7a07 vstr s15, [r7, #28] break; 800e6d2: e043 b.n 800e75c case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e6d4: 697b ldr r3, [r7, #20] 800e6d6: ee07 3a90 vmov s15, r3 800e6da: eef8 7a67 vcvt.f32.u32 s15, s15 800e6de: eddf 6a4f vldr s13, [pc, #316] @ 800e81c 800e6e2: ee86 7aa7 vdiv.f32 s14, s13, s15 800e6e6: 4b48 ldr r3, [pc, #288] @ (800e808 ) 800e6e8: 6b9b ldr r3, [r3, #56] @ 0x38 800e6ea: f3c3 0308 ubfx r3, r3, #0, #9 800e6ee: ee07 3a90 vmov s15, r3 800e6f2: eef8 6a67 vcvt.f32.u32 s13, s15 800e6f6: ed97 6a03 vldr s12, [r7, #12] 800e6fa: eddf 5a45 vldr s11, [pc, #276] @ 800e810 800e6fe: eec6 7a25 vdiv.f32 s15, s12, s11 800e702: ee76 7aa7 vadd.f32 s15, s13, s15 800e706: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e70a: ee77 7aa6 vadd.f32 s15, s15, s13 800e70e: ee67 7a27 vmul.f32 s15, s14, s15 800e712: edc7 7a07 vstr s15, [r7, #28] break; 800e716: e021 b.n 800e75c default: pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e718: 697b ldr r3, [r7, #20] 800e71a: ee07 3a90 vmov s15, r3 800e71e: eef8 7a67 vcvt.f32.u32 s15, s15 800e722: eddf 6a3d vldr s13, [pc, #244] @ 800e818 800e726: ee86 7aa7 vdiv.f32 s14, s13, s15 800e72a: 4b37 ldr r3, [pc, #220] @ (800e808 ) 800e72c: 6b9b ldr r3, [r3, #56] @ 0x38 800e72e: f3c3 0308 ubfx r3, r3, #0, #9 800e732: ee07 3a90 vmov s15, r3 800e736: eef8 6a67 vcvt.f32.u32 s13, s15 800e73a: ed97 6a03 vldr s12, [r7, #12] 800e73e: eddf 5a34 vldr s11, [pc, #208] @ 800e810 800e742: eec6 7a25 vdiv.f32 s15, s12, s11 800e746: ee76 7aa7 vadd.f32 s15, s13, s15 800e74a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e74e: ee77 7aa6 vadd.f32 s15, s15, s13 800e752: ee67 7a27 vmul.f32 s15, s14, s15 800e756: edc7 7a07 vstr s15, [r7, #28] break; 800e75a: bf00 nop } PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; 800e75c: 4b2a ldr r3, [pc, #168] @ (800e808 ) 800e75e: 6b9b ldr r3, [r3, #56] @ 0x38 800e760: 0a5b lsrs r3, r3, #9 800e762: f003 037f and.w r3, r3, #127 @ 0x7f 800e766: ee07 3a90 vmov s15, r3 800e76a: eef8 7a67 vcvt.f32.u32 s15, s15 800e76e: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800e772: ee37 7a87 vadd.f32 s14, s15, s14 800e776: edd7 6a07 vldr s13, [r7, #28] 800e77a: eec6 7a87 vdiv.f32 s15, s13, s14 800e77e: eefc 7ae7 vcvt.u32.f32 s15, s15 800e782: ee17 2a90 vmov r2, s15 800e786: 687b ldr r3, [r7, #4] 800e788: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; 800e78a: 4b1f ldr r3, [pc, #124] @ (800e808 ) 800e78c: 6b9b ldr r3, [r3, #56] @ 0x38 800e78e: 0c1b lsrs r3, r3, #16 800e790: f003 037f and.w r3, r3, #127 @ 0x7f 800e794: ee07 3a90 vmov s15, r3 800e798: eef8 7a67 vcvt.f32.u32 s15, s15 800e79c: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800e7a0: ee37 7a87 vadd.f32 s14, s15, s14 800e7a4: edd7 6a07 vldr s13, [r7, #28] 800e7a8: eec6 7a87 vdiv.f32 s15, s13, s14 800e7ac: eefc 7ae7 vcvt.u32.f32 s15, s15 800e7b0: ee17 2a90 vmov r2, s15 800e7b4: 687b ldr r3, [r7, #4] 800e7b6: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; 800e7b8: 4b13 ldr r3, [pc, #76] @ (800e808 ) 800e7ba: 6b9b ldr r3, [r3, #56] @ 0x38 800e7bc: 0e1b lsrs r3, r3, #24 800e7be: f003 037f and.w r3, r3, #127 @ 0x7f 800e7c2: ee07 3a90 vmov s15, r3 800e7c6: eef8 7a67 vcvt.f32.u32 s15, s15 800e7ca: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800e7ce: ee37 7a87 vadd.f32 s14, s15, s14 800e7d2: edd7 6a07 vldr s13, [r7, #28] 800e7d6: eec6 7a87 vdiv.f32 s15, s13, s14 800e7da: eefc 7ae7 vcvt.u32.f32 s15, s15 800e7de: ee17 2a90 vmov r2, s15 800e7e2: 687b ldr r3, [r7, #4] 800e7e4: 609a str r2, [r3, #8] { PLL2_Clocks->PLL2_P_Frequency = 0U; PLL2_Clocks->PLL2_Q_Frequency = 0U; PLL2_Clocks->PLL2_R_Frequency = 0U; } } 800e7e6: e008 b.n 800e7fa PLL2_Clocks->PLL2_P_Frequency = 0U; 800e7e8: 687b ldr r3, [r7, #4] 800e7ea: 2200 movs r2, #0 800e7ec: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = 0U; 800e7ee: 687b ldr r3, [r7, #4] 800e7f0: 2200 movs r2, #0 800e7f2: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = 0U; 800e7f4: 687b ldr r3, [r7, #4] 800e7f6: 2200 movs r2, #0 800e7f8: 609a str r2, [r3, #8] } 800e7fa: bf00 nop 800e7fc: 3724 adds r7, #36 @ 0x24 800e7fe: 46bd mov sp, r7 800e800: f85d 7b04 ldr.w r7, [sp], #4 800e804: 4770 bx lr 800e806: bf00 nop 800e808: 58024400 .word 0x58024400 800e80c: 03d09000 .word 0x03d09000 800e810: 46000000 .word 0x46000000 800e814: 4c742400 .word 0x4c742400 800e818: 4a742400 .word 0x4a742400 800e81c: 4bbebc20 .word 0x4bbebc20 0800e820 : * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL3_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) { 800e820: b480 push {r7} 800e822: b089 sub sp, #36 @ 0x24 800e824: af00 add r7, sp, #0 800e826: 6078 str r0, [r7, #4] float_t fracn3, pll3vco; /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N PLL3xCLK = PLL3_VCO / PLLxR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800e828: 4ba1 ldr r3, [pc, #644] @ (800eab0 ) 800e82a: 6a9b ldr r3, [r3, #40] @ 0x28 800e82c: f003 0303 and.w r3, r3, #3 800e830: 61bb str r3, [r7, #24] pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; 800e832: 4b9f ldr r3, [pc, #636] @ (800eab0 ) 800e834: 6a9b ldr r3, [r3, #40] @ 0x28 800e836: 0d1b lsrs r3, r3, #20 800e838: f003 033f and.w r3, r3, #63 @ 0x3f 800e83c: 617b str r3, [r7, #20] pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; 800e83e: 4b9c ldr r3, [pc, #624] @ (800eab0 ) 800e840: 6adb ldr r3, [r3, #44] @ 0x2c 800e842: 0a1b lsrs r3, r3, #8 800e844: f003 0301 and.w r3, r3, #1 800e848: 613b str r3, [r7, #16] fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); 800e84a: 4b99 ldr r3, [pc, #612] @ (800eab0 ) 800e84c: 6c5b ldr r3, [r3, #68] @ 0x44 800e84e: 08db lsrs r3, r3, #3 800e850: f3c3 030c ubfx r3, r3, #0, #13 800e854: 693a ldr r2, [r7, #16] 800e856: fb02 f303 mul.w r3, r2, r3 800e85a: ee07 3a90 vmov s15, r3 800e85e: eef8 7a67 vcvt.f32.u32 s15, s15 800e862: edc7 7a03 vstr s15, [r7, #12] if (pll3m != 0U) 800e866: 697b ldr r3, [r7, #20] 800e868: 2b00 cmp r3, #0 800e86a: f000 8111 beq.w 800ea90 { switch (pllsource) 800e86e: 69bb ldr r3, [r7, #24] 800e870: 2b02 cmp r3, #2 800e872: f000 8083 beq.w 800e97c 800e876: 69bb ldr r3, [r7, #24] 800e878: 2b02 cmp r3, #2 800e87a: f200 80a1 bhi.w 800e9c0 800e87e: 69bb ldr r3, [r7, #24] 800e880: 2b00 cmp r3, #0 800e882: d003 beq.n 800e88c 800e884: 69bb ldr r3, [r7, #24] 800e886: 2b01 cmp r3, #1 800e888: d056 beq.n 800e938 800e88a: e099 b.n 800e9c0 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800e88c: 4b88 ldr r3, [pc, #544] @ (800eab0 ) 800e88e: 681b ldr r3, [r3, #0] 800e890: f003 0320 and.w r3, r3, #32 800e894: 2b00 cmp r3, #0 800e896: d02d beq.n 800e8f4 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e898: 4b85 ldr r3, [pc, #532] @ (800eab0 ) 800e89a: 681b ldr r3, [r3, #0] 800e89c: 08db lsrs r3, r3, #3 800e89e: f003 0303 and.w r3, r3, #3 800e8a2: 4a84 ldr r2, [pc, #528] @ (800eab4 ) 800e8a4: fa22 f303 lsr.w r3, r2, r3 800e8a8: 60bb str r3, [r7, #8] pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800e8aa: 68bb ldr r3, [r7, #8] 800e8ac: ee07 3a90 vmov s15, r3 800e8b0: eef8 6a67 vcvt.f32.u32 s13, s15 800e8b4: 697b ldr r3, [r7, #20] 800e8b6: ee07 3a90 vmov s15, r3 800e8ba: eef8 7a67 vcvt.f32.u32 s15, s15 800e8be: ee86 7aa7 vdiv.f32 s14, s13, s15 800e8c2: 4b7b ldr r3, [pc, #492] @ (800eab0 ) 800e8c4: 6c1b ldr r3, [r3, #64] @ 0x40 800e8c6: f3c3 0308 ubfx r3, r3, #0, #9 800e8ca: ee07 3a90 vmov s15, r3 800e8ce: eef8 6a67 vcvt.f32.u32 s13, s15 800e8d2: ed97 6a03 vldr s12, [r7, #12] 800e8d6: eddf 5a78 vldr s11, [pc, #480] @ 800eab8 800e8da: eec6 7a25 vdiv.f32 s15, s12, s11 800e8de: ee76 7aa7 vadd.f32 s15, s13, s15 800e8e2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e8e6: ee77 7aa6 vadd.f32 s15, s15, s13 800e8ea: ee67 7a27 vmul.f32 s15, s14, s15 800e8ee: edc7 7a07 vstr s15, [r7, #28] } else { pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); } break; 800e8f2: e087 b.n 800ea04 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800e8f4: 697b ldr r3, [r7, #20] 800e8f6: ee07 3a90 vmov s15, r3 800e8fa: eef8 7a67 vcvt.f32.u32 s15, s15 800e8fe: eddf 6a6f vldr s13, [pc, #444] @ 800eabc 800e902: ee86 7aa7 vdiv.f32 s14, s13, s15 800e906: 4b6a ldr r3, [pc, #424] @ (800eab0 ) 800e908: 6c1b ldr r3, [r3, #64] @ 0x40 800e90a: f3c3 0308 ubfx r3, r3, #0, #9 800e90e: ee07 3a90 vmov s15, r3 800e912: eef8 6a67 vcvt.f32.u32 s13, s15 800e916: ed97 6a03 vldr s12, [r7, #12] 800e91a: eddf 5a67 vldr s11, [pc, #412] @ 800eab8 800e91e: eec6 7a25 vdiv.f32 s15, s12, s11 800e922: ee76 7aa7 vadd.f32 s15, s13, s15 800e926: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e92a: ee77 7aa6 vadd.f32 s15, s15, s13 800e92e: ee67 7a27 vmul.f32 s15, s14, s15 800e932: edc7 7a07 vstr s15, [r7, #28] break; 800e936: e065 b.n 800ea04 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800e938: 697b ldr r3, [r7, #20] 800e93a: ee07 3a90 vmov s15, r3 800e93e: eef8 7a67 vcvt.f32.u32 s15, s15 800e942: eddf 6a5f vldr s13, [pc, #380] @ 800eac0 800e946: ee86 7aa7 vdiv.f32 s14, s13, s15 800e94a: 4b59 ldr r3, [pc, #356] @ (800eab0 ) 800e94c: 6c1b ldr r3, [r3, #64] @ 0x40 800e94e: f3c3 0308 ubfx r3, r3, #0, #9 800e952: ee07 3a90 vmov s15, r3 800e956: eef8 6a67 vcvt.f32.u32 s13, s15 800e95a: ed97 6a03 vldr s12, [r7, #12] 800e95e: eddf 5a56 vldr s11, [pc, #344] @ 800eab8 800e962: eec6 7a25 vdiv.f32 s15, s12, s11 800e966: ee76 7aa7 vadd.f32 s15, s13, s15 800e96a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e96e: ee77 7aa6 vadd.f32 s15, s15, s13 800e972: ee67 7a27 vmul.f32 s15, s14, s15 800e976: edc7 7a07 vstr s15, [r7, #28] break; 800e97a: e043 b.n 800ea04 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800e97c: 697b ldr r3, [r7, #20] 800e97e: ee07 3a90 vmov s15, r3 800e982: eef8 7a67 vcvt.f32.u32 s15, s15 800e986: eddf 6a4f vldr s13, [pc, #316] @ 800eac4 800e98a: ee86 7aa7 vdiv.f32 s14, s13, s15 800e98e: 4b48 ldr r3, [pc, #288] @ (800eab0 ) 800e990: 6c1b ldr r3, [r3, #64] @ 0x40 800e992: f3c3 0308 ubfx r3, r3, #0, #9 800e996: ee07 3a90 vmov s15, r3 800e99a: eef8 6a67 vcvt.f32.u32 s13, s15 800e99e: ed97 6a03 vldr s12, [r7, #12] 800e9a2: eddf 5a45 vldr s11, [pc, #276] @ 800eab8 800e9a6: eec6 7a25 vdiv.f32 s15, s12, s11 800e9aa: ee76 7aa7 vadd.f32 s15, s13, s15 800e9ae: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e9b2: ee77 7aa6 vadd.f32 s15, s15, s13 800e9b6: ee67 7a27 vmul.f32 s15, s14, s15 800e9ba: edc7 7a07 vstr s15, [r7, #28] break; 800e9be: e021 b.n 800ea04 default: pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800e9c0: 697b ldr r3, [r7, #20] 800e9c2: ee07 3a90 vmov s15, r3 800e9c6: eef8 7a67 vcvt.f32.u32 s15, s15 800e9ca: eddf 6a3d vldr s13, [pc, #244] @ 800eac0 800e9ce: ee86 7aa7 vdiv.f32 s14, s13, s15 800e9d2: 4b37 ldr r3, [pc, #220] @ (800eab0 ) 800e9d4: 6c1b ldr r3, [r3, #64] @ 0x40 800e9d6: f3c3 0308 ubfx r3, r3, #0, #9 800e9da: ee07 3a90 vmov s15, r3 800e9de: eef8 6a67 vcvt.f32.u32 s13, s15 800e9e2: ed97 6a03 vldr s12, [r7, #12] 800e9e6: eddf 5a34 vldr s11, [pc, #208] @ 800eab8 800e9ea: eec6 7a25 vdiv.f32 s15, s12, s11 800e9ee: ee76 7aa7 vadd.f32 s15, s13, s15 800e9f2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e9f6: ee77 7aa6 vadd.f32 s15, s15, s13 800e9fa: ee67 7a27 vmul.f32 s15, s14, s15 800e9fe: edc7 7a07 vstr s15, [r7, #28] break; 800ea02: bf00 nop } PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; 800ea04: 4b2a ldr r3, [pc, #168] @ (800eab0 ) 800ea06: 6c1b ldr r3, [r3, #64] @ 0x40 800ea08: 0a5b lsrs r3, r3, #9 800ea0a: f003 037f and.w r3, r3, #127 @ 0x7f 800ea0e: ee07 3a90 vmov s15, r3 800ea12: eef8 7a67 vcvt.f32.u32 s15, s15 800ea16: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ea1a: ee37 7a87 vadd.f32 s14, s15, s14 800ea1e: edd7 6a07 vldr s13, [r7, #28] 800ea22: eec6 7a87 vdiv.f32 s15, s13, s14 800ea26: eefc 7ae7 vcvt.u32.f32 s15, s15 800ea2a: ee17 2a90 vmov r2, s15 800ea2e: 687b ldr r3, [r7, #4] 800ea30: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; 800ea32: 4b1f ldr r3, [pc, #124] @ (800eab0 ) 800ea34: 6c1b ldr r3, [r3, #64] @ 0x40 800ea36: 0c1b lsrs r3, r3, #16 800ea38: f003 037f and.w r3, r3, #127 @ 0x7f 800ea3c: ee07 3a90 vmov s15, r3 800ea40: eef8 7a67 vcvt.f32.u32 s15, s15 800ea44: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ea48: ee37 7a87 vadd.f32 s14, s15, s14 800ea4c: edd7 6a07 vldr s13, [r7, #28] 800ea50: eec6 7a87 vdiv.f32 s15, s13, s14 800ea54: eefc 7ae7 vcvt.u32.f32 s15, s15 800ea58: ee17 2a90 vmov r2, s15 800ea5c: 687b ldr r3, [r7, #4] 800ea5e: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; 800ea60: 4b13 ldr r3, [pc, #76] @ (800eab0 ) 800ea62: 6c1b ldr r3, [r3, #64] @ 0x40 800ea64: 0e1b lsrs r3, r3, #24 800ea66: f003 037f and.w r3, r3, #127 @ 0x7f 800ea6a: ee07 3a90 vmov s15, r3 800ea6e: eef8 7a67 vcvt.f32.u32 s15, s15 800ea72: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ea76: ee37 7a87 vadd.f32 s14, s15, s14 800ea7a: edd7 6a07 vldr s13, [r7, #28] 800ea7e: eec6 7a87 vdiv.f32 s15, s13, s14 800ea82: eefc 7ae7 vcvt.u32.f32 s15, s15 800ea86: ee17 2a90 vmov r2, s15 800ea8a: 687b ldr r3, [r7, #4] 800ea8c: 609a str r2, [r3, #8] PLL3_Clocks->PLL3_P_Frequency = 0U; PLL3_Clocks->PLL3_Q_Frequency = 0U; PLL3_Clocks->PLL3_R_Frequency = 0U; } } 800ea8e: e008 b.n 800eaa2 PLL3_Clocks->PLL3_P_Frequency = 0U; 800ea90: 687b ldr r3, [r7, #4] 800ea92: 2200 movs r2, #0 800ea94: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = 0U; 800ea96: 687b ldr r3, [r7, #4] 800ea98: 2200 movs r2, #0 800ea9a: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = 0U; 800ea9c: 687b ldr r3, [r7, #4] 800ea9e: 2200 movs r2, #0 800eaa0: 609a str r2, [r3, #8] } 800eaa2: bf00 nop 800eaa4: 3724 adds r7, #36 @ 0x24 800eaa6: 46bd mov sp, r7 800eaa8: f85d 7b04 ldr.w r7, [sp], #4 800eaac: 4770 bx lr 800eaae: bf00 nop 800eab0: 58024400 .word 0x58024400 800eab4: 03d09000 .word 0x03d09000 800eab8: 46000000 .word 0x46000000 800eabc: 4c742400 .word 0x4c742400 800eac0: 4a742400 .word 0x4a742400 800eac4: 4bbebc20 .word 0x4bbebc20 0800eac8 : * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL1_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) { 800eac8: b480 push {r7} 800eaca: b089 sub sp, #36 @ 0x24 800eacc: af00 add r7, sp, #0 800eace: 6078 str r0, [r7, #4] uint32_t pllsource, pll1m, pll1fracen, hsivalue; float_t fracn1, pll1vco; pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800ead0: 4ba0 ldr r3, [pc, #640] @ (800ed54 ) 800ead2: 6a9b ldr r3, [r3, #40] @ 0x28 800ead4: f003 0303 and.w r3, r3, #3 800ead8: 61bb str r3, [r7, #24] pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); 800eada: 4b9e ldr r3, [pc, #632] @ (800ed54 ) 800eadc: 6a9b ldr r3, [r3, #40] @ 0x28 800eade: 091b lsrs r3, r3, #4 800eae0: f003 033f and.w r3, r3, #63 @ 0x3f 800eae4: 617b str r3, [r7, #20] pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; 800eae6: 4b9b ldr r3, [pc, #620] @ (800ed54 ) 800eae8: 6adb ldr r3, [r3, #44] @ 0x2c 800eaea: f003 0301 and.w r3, r3, #1 800eaee: 613b str r3, [r7, #16] fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800eaf0: 4b98 ldr r3, [pc, #608] @ (800ed54 ) 800eaf2: 6b5b ldr r3, [r3, #52] @ 0x34 800eaf4: 08db lsrs r3, r3, #3 800eaf6: f3c3 030c ubfx r3, r3, #0, #13 800eafa: 693a ldr r2, [r7, #16] 800eafc: fb02 f303 mul.w r3, r2, r3 800eb00: ee07 3a90 vmov s15, r3 800eb04: eef8 7a67 vcvt.f32.u32 s15, s15 800eb08: edc7 7a03 vstr s15, [r7, #12] if (pll1m != 0U) 800eb0c: 697b ldr r3, [r7, #20] 800eb0e: 2b00 cmp r3, #0 800eb10: f000 8111 beq.w 800ed36 { switch (pllsource) 800eb14: 69bb ldr r3, [r7, #24] 800eb16: 2b02 cmp r3, #2 800eb18: f000 8083 beq.w 800ec22 800eb1c: 69bb ldr r3, [r7, #24] 800eb1e: 2b02 cmp r3, #2 800eb20: f200 80a1 bhi.w 800ec66 800eb24: 69bb ldr r3, [r7, #24] 800eb26: 2b00 cmp r3, #0 800eb28: d003 beq.n 800eb32 800eb2a: 69bb ldr r3, [r7, #24] 800eb2c: 2b01 cmp r3, #1 800eb2e: d056 beq.n 800ebde 800eb30: e099 b.n 800ec66 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800eb32: 4b88 ldr r3, [pc, #544] @ (800ed54 ) 800eb34: 681b ldr r3, [r3, #0] 800eb36: f003 0320 and.w r3, r3, #32 800eb3a: 2b00 cmp r3, #0 800eb3c: d02d beq.n 800eb9a { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800eb3e: 4b85 ldr r3, [pc, #532] @ (800ed54 ) 800eb40: 681b ldr r3, [r3, #0] 800eb42: 08db lsrs r3, r3, #3 800eb44: f003 0303 and.w r3, r3, #3 800eb48: 4a83 ldr r2, [pc, #524] @ (800ed58 ) 800eb4a: fa22 f303 lsr.w r3, r2, r3 800eb4e: 60bb str r3, [r7, #8] pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800eb50: 68bb ldr r3, [r7, #8] 800eb52: ee07 3a90 vmov s15, r3 800eb56: eef8 6a67 vcvt.f32.u32 s13, s15 800eb5a: 697b ldr r3, [r7, #20] 800eb5c: ee07 3a90 vmov s15, r3 800eb60: eef8 7a67 vcvt.f32.u32 s15, s15 800eb64: ee86 7aa7 vdiv.f32 s14, s13, s15 800eb68: 4b7a ldr r3, [pc, #488] @ (800ed54 ) 800eb6a: 6b1b ldr r3, [r3, #48] @ 0x30 800eb6c: f3c3 0308 ubfx r3, r3, #0, #9 800eb70: ee07 3a90 vmov s15, r3 800eb74: eef8 6a67 vcvt.f32.u32 s13, s15 800eb78: ed97 6a03 vldr s12, [r7, #12] 800eb7c: eddf 5a77 vldr s11, [pc, #476] @ 800ed5c 800eb80: eec6 7a25 vdiv.f32 s15, s12, s11 800eb84: ee76 7aa7 vadd.f32 s15, s13, s15 800eb88: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800eb8c: ee77 7aa6 vadd.f32 s15, s15, s13 800eb90: ee67 7a27 vmul.f32 s15, s14, s15 800eb94: edc7 7a07 vstr s15, [r7, #28] } else { pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 800eb98: e087 b.n 800ecaa pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800eb9a: 697b ldr r3, [r7, #20] 800eb9c: ee07 3a90 vmov s15, r3 800eba0: eef8 7a67 vcvt.f32.u32 s15, s15 800eba4: eddf 6a6e vldr s13, [pc, #440] @ 800ed60 800eba8: ee86 7aa7 vdiv.f32 s14, s13, s15 800ebac: 4b69 ldr r3, [pc, #420] @ (800ed54 ) 800ebae: 6b1b ldr r3, [r3, #48] @ 0x30 800ebb0: f3c3 0308 ubfx r3, r3, #0, #9 800ebb4: ee07 3a90 vmov s15, r3 800ebb8: eef8 6a67 vcvt.f32.u32 s13, s15 800ebbc: ed97 6a03 vldr s12, [r7, #12] 800ebc0: eddf 5a66 vldr s11, [pc, #408] @ 800ed5c 800ebc4: eec6 7a25 vdiv.f32 s15, s12, s11 800ebc8: ee76 7aa7 vadd.f32 s15, s13, s15 800ebcc: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ebd0: ee77 7aa6 vadd.f32 s15, s15, s13 800ebd4: ee67 7a27 vmul.f32 s15, s14, s15 800ebd8: edc7 7a07 vstr s15, [r7, #28] break; 800ebdc: e065 b.n 800ecaa case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ebde: 697b ldr r3, [r7, #20] 800ebe0: ee07 3a90 vmov s15, r3 800ebe4: eef8 7a67 vcvt.f32.u32 s15, s15 800ebe8: eddf 6a5e vldr s13, [pc, #376] @ 800ed64 800ebec: ee86 7aa7 vdiv.f32 s14, s13, s15 800ebf0: 4b58 ldr r3, [pc, #352] @ (800ed54 ) 800ebf2: 6b1b ldr r3, [r3, #48] @ 0x30 800ebf4: f3c3 0308 ubfx r3, r3, #0, #9 800ebf8: ee07 3a90 vmov s15, r3 800ebfc: eef8 6a67 vcvt.f32.u32 s13, s15 800ec00: ed97 6a03 vldr s12, [r7, #12] 800ec04: eddf 5a55 vldr s11, [pc, #340] @ 800ed5c 800ec08: eec6 7a25 vdiv.f32 s15, s12, s11 800ec0c: ee76 7aa7 vadd.f32 s15, s13, s15 800ec10: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ec14: ee77 7aa6 vadd.f32 s15, s15, s13 800ec18: ee67 7a27 vmul.f32 s15, s14, s15 800ec1c: edc7 7a07 vstr s15, [r7, #28] break; 800ec20: e043 b.n 800ecaa case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ec22: 697b ldr r3, [r7, #20] 800ec24: ee07 3a90 vmov s15, r3 800ec28: eef8 7a67 vcvt.f32.u32 s15, s15 800ec2c: eddf 6a4e vldr s13, [pc, #312] @ 800ed68 800ec30: ee86 7aa7 vdiv.f32 s14, s13, s15 800ec34: 4b47 ldr r3, [pc, #284] @ (800ed54 ) 800ec36: 6b1b ldr r3, [r3, #48] @ 0x30 800ec38: f3c3 0308 ubfx r3, r3, #0, #9 800ec3c: ee07 3a90 vmov s15, r3 800ec40: eef8 6a67 vcvt.f32.u32 s13, s15 800ec44: ed97 6a03 vldr s12, [r7, #12] 800ec48: eddf 5a44 vldr s11, [pc, #272] @ 800ed5c 800ec4c: eec6 7a25 vdiv.f32 s15, s12, s11 800ec50: ee76 7aa7 vadd.f32 s15, s13, s15 800ec54: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ec58: ee77 7aa6 vadd.f32 s15, s15, s13 800ec5c: ee67 7a27 vmul.f32 s15, s14, s15 800ec60: edc7 7a07 vstr s15, [r7, #28] break; 800ec64: e021 b.n 800ecaa default: pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ec66: 697b ldr r3, [r7, #20] 800ec68: ee07 3a90 vmov s15, r3 800ec6c: eef8 7a67 vcvt.f32.u32 s15, s15 800ec70: eddf 6a3b vldr s13, [pc, #236] @ 800ed60 800ec74: ee86 7aa7 vdiv.f32 s14, s13, s15 800ec78: 4b36 ldr r3, [pc, #216] @ (800ed54 ) 800ec7a: 6b1b ldr r3, [r3, #48] @ 0x30 800ec7c: f3c3 0308 ubfx r3, r3, #0, #9 800ec80: ee07 3a90 vmov s15, r3 800ec84: eef8 6a67 vcvt.f32.u32 s13, s15 800ec88: ed97 6a03 vldr s12, [r7, #12] 800ec8c: eddf 5a33 vldr s11, [pc, #204] @ 800ed5c 800ec90: eec6 7a25 vdiv.f32 s15, s12, s11 800ec94: ee76 7aa7 vadd.f32 s15, s13, s15 800ec98: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ec9c: ee77 7aa6 vadd.f32 s15, s15, s13 800eca0: ee67 7a27 vmul.f32 s15, s14, s15 800eca4: edc7 7a07 vstr s15, [r7, #28] break; 800eca8: bf00 nop } PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; 800ecaa: 4b2a ldr r3, [pc, #168] @ (800ed54 ) 800ecac: 6b1b ldr r3, [r3, #48] @ 0x30 800ecae: 0a5b lsrs r3, r3, #9 800ecb0: f003 037f and.w r3, r3, #127 @ 0x7f 800ecb4: ee07 3a90 vmov s15, r3 800ecb8: eef8 7a67 vcvt.f32.u32 s15, s15 800ecbc: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ecc0: ee37 7a87 vadd.f32 s14, s15, s14 800ecc4: edd7 6a07 vldr s13, [r7, #28] 800ecc8: eec6 7a87 vdiv.f32 s15, s13, s14 800eccc: eefc 7ae7 vcvt.u32.f32 s15, s15 800ecd0: ee17 2a90 vmov r2, s15 800ecd4: 687b ldr r3, [r7, #4] 800ecd6: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ; 800ecd8: 4b1e ldr r3, [pc, #120] @ (800ed54 ) 800ecda: 6b1b ldr r3, [r3, #48] @ 0x30 800ecdc: 0c1b lsrs r3, r3, #16 800ecde: f003 037f and.w r3, r3, #127 @ 0x7f 800ece2: ee07 3a90 vmov s15, r3 800ece6: eef8 7a67 vcvt.f32.u32 s15, s15 800ecea: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ecee: ee37 7a87 vadd.f32 s14, s15, s14 800ecf2: edd7 6a07 vldr s13, [r7, #28] 800ecf6: eec6 7a87 vdiv.f32 s15, s13, s14 800ecfa: eefc 7ae7 vcvt.u32.f32 s15, s15 800ecfe: ee17 2a90 vmov r2, s15 800ed02: 687b ldr r3, [r7, #4] 800ed04: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; 800ed06: 4b13 ldr r3, [pc, #76] @ (800ed54 ) 800ed08: 6b1b ldr r3, [r3, #48] @ 0x30 800ed0a: 0e1b lsrs r3, r3, #24 800ed0c: f003 037f and.w r3, r3, #127 @ 0x7f 800ed10: ee07 3a90 vmov s15, r3 800ed14: eef8 7a67 vcvt.f32.u32 s15, s15 800ed18: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ed1c: ee37 7a87 vadd.f32 s14, s15, s14 800ed20: edd7 6a07 vldr s13, [r7, #28] 800ed24: eec6 7a87 vdiv.f32 s15, s13, s14 800ed28: eefc 7ae7 vcvt.u32.f32 s15, s15 800ed2c: ee17 2a90 vmov r2, s15 800ed30: 687b ldr r3, [r7, #4] 800ed32: 609a str r2, [r3, #8] PLL1_Clocks->PLL1_P_Frequency = 0U; PLL1_Clocks->PLL1_Q_Frequency = 0U; PLL1_Clocks->PLL1_R_Frequency = 0U; } } 800ed34: e008 b.n 800ed48 PLL1_Clocks->PLL1_P_Frequency = 0U; 800ed36: 687b ldr r3, [r7, #4] 800ed38: 2200 movs r2, #0 800ed3a: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = 0U; 800ed3c: 687b ldr r3, [r7, #4] 800ed3e: 2200 movs r2, #0 800ed40: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = 0U; 800ed42: 687b ldr r3, [r7, #4] 800ed44: 2200 movs r2, #0 800ed46: 609a str r2, [r3, #8] } 800ed48: bf00 nop 800ed4a: 3724 adds r7, #36 @ 0x24 800ed4c: 46bd mov sp, r7 800ed4e: f85d 7b04 ldr.w r7, [sp], #4 800ed52: 4770 bx lr 800ed54: 58024400 .word 0x58024400 800ed58: 03d09000 .word 0x03d09000 800ed5c: 46000000 .word 0x46000000 800ed60: 4c742400 .word 0x4c742400 800ed64: 4a742400 .word 0x4a742400 800ed68: 4bbebc20 .word 0x4bbebc20 0800ed6c : * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { 800ed6c: b580 push {r7, lr} 800ed6e: b084 sub sp, #16 800ed70: af00 add r7, sp, #0 800ed72: 6078 str r0, [r7, #4] 800ed74: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800ed76: 2300 movs r3, #0 800ed78: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800ed7a: 4b53 ldr r3, [pc, #332] @ (800eec8 ) 800ed7c: 6a9b ldr r3, [r3, #40] @ 0x28 800ed7e: f003 0303 and.w r3, r3, #3 800ed82: 2b03 cmp r3, #3 800ed84: d101 bne.n 800ed8a { return HAL_ERROR; 800ed86: 2301 movs r3, #1 800ed88: e099 b.n 800eebe else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 800ed8a: 4b4f ldr r3, [pc, #316] @ (800eec8 ) 800ed8c: 681b ldr r3, [r3, #0] 800ed8e: 4a4e ldr r2, [pc, #312] @ (800eec8 ) 800ed90: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800ed94: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ed96: f7f6 ff0b bl 8005bb0 800ed9a: 60b8 str r0, [r7, #8] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800ed9c: e008 b.n 800edb0 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800ed9e: f7f6 ff07 bl 8005bb0 800eda2: 4602 mov r2, r0 800eda4: 68bb ldr r3, [r7, #8] 800eda6: 1ad3 subs r3, r2, r3 800eda8: 2b02 cmp r3, #2 800edaa: d901 bls.n 800edb0 { return HAL_TIMEOUT; 800edac: 2303 movs r3, #3 800edae: e086 b.n 800eebe while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800edb0: 4b45 ldr r3, [pc, #276] @ (800eec8 ) 800edb2: 681b ldr r3, [r3, #0] 800edb4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800edb8: 2b00 cmp r3, #0 800edba: d1f0 bne.n 800ed9e } } /* Configure PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 800edbc: 4b42 ldr r3, [pc, #264] @ (800eec8 ) 800edbe: 6a9b ldr r3, [r3, #40] @ 0x28 800edc0: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800edc4: 687b ldr r3, [r7, #4] 800edc6: 681b ldr r3, [r3, #0] 800edc8: 031b lsls r3, r3, #12 800edca: 493f ldr r1, [pc, #252] @ (800eec8 ) 800edcc: 4313 orrs r3, r2 800edce: 628b str r3, [r1, #40] @ 0x28 800edd0: 687b ldr r3, [r7, #4] 800edd2: 685b ldr r3, [r3, #4] 800edd4: 3b01 subs r3, #1 800edd6: f3c3 0208 ubfx r2, r3, #0, #9 800edda: 687b ldr r3, [r7, #4] 800eddc: 689b ldr r3, [r3, #8] 800edde: 3b01 subs r3, #1 800ede0: 025b lsls r3, r3, #9 800ede2: b29b uxth r3, r3 800ede4: 431a orrs r2, r3 800ede6: 687b ldr r3, [r7, #4] 800ede8: 68db ldr r3, [r3, #12] 800edea: 3b01 subs r3, #1 800edec: 041b lsls r3, r3, #16 800edee: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800edf2: 431a orrs r2, r3 800edf4: 687b ldr r3, [r7, #4] 800edf6: 691b ldr r3, [r3, #16] 800edf8: 3b01 subs r3, #1 800edfa: 061b lsls r3, r3, #24 800edfc: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800ee00: 4931 ldr r1, [pc, #196] @ (800eec8 ) 800ee02: 4313 orrs r3, r2 800ee04: 638b str r3, [r1, #56] @ 0x38 pll2->PLL2P, pll2->PLL2Q, pll2->PLL2R); /* Select PLL2 input reference frequency range: VCI */ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 800ee06: 4b30 ldr r3, [pc, #192] @ (800eec8 ) 800ee08: 6adb ldr r3, [r3, #44] @ 0x2c 800ee0a: f023 02c0 bic.w r2, r3, #192 @ 0xc0 800ee0e: 687b ldr r3, [r7, #4] 800ee10: 695b ldr r3, [r3, #20] 800ee12: 492d ldr r1, [pc, #180] @ (800eec8 ) 800ee14: 4313 orrs r3, r2 800ee16: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL2 output frequency range : VCO */ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 800ee18: 4b2b ldr r3, [pc, #172] @ (800eec8 ) 800ee1a: 6adb ldr r3, [r3, #44] @ 0x2c 800ee1c: f023 0220 bic.w r2, r3, #32 800ee20: 687b ldr r3, [r7, #4] 800ee22: 699b ldr r3, [r3, #24] 800ee24: 4928 ldr r1, [pc, #160] @ (800eec8 ) 800ee26: 4313 orrs r3, r2 800ee28: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_DISABLE(); 800ee2a: 4b27 ldr r3, [pc, #156] @ (800eec8 ) 800ee2c: 6adb ldr r3, [r3, #44] @ 0x2c 800ee2e: 4a26 ldr r2, [pc, #152] @ (800eec8 ) 800ee30: f023 0310 bic.w r3, r3, #16 800ee34: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 800ee36: 4b24 ldr r3, [pc, #144] @ (800eec8 ) 800ee38: 6bda ldr r2, [r3, #60] @ 0x3c 800ee3a: 4b24 ldr r3, [pc, #144] @ (800eecc ) 800ee3c: 4013 ands r3, r2 800ee3e: 687a ldr r2, [r7, #4] 800ee40: 69d2 ldr r2, [r2, #28] 800ee42: 00d2 lsls r2, r2, #3 800ee44: 4920 ldr r1, [pc, #128] @ (800eec8 ) 800ee46: 4313 orrs r3, r2 800ee48: 63cb str r3, [r1, #60] @ 0x3c /* Enable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_ENABLE(); 800ee4a: 4b1f ldr r3, [pc, #124] @ (800eec8 ) 800ee4c: 6adb ldr r3, [r3, #44] @ 0x2c 800ee4e: 4a1e ldr r2, [pc, #120] @ (800eec8 ) 800ee50: f043 0310 orr.w r3, r3, #16 800ee54: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL2 clock output */ if (Divider == DIVIDER_P_UPDATE) 800ee56: 683b ldr r3, [r7, #0] 800ee58: 2b00 cmp r3, #0 800ee5a: d106 bne.n 800ee6a { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 800ee5c: 4b1a ldr r3, [pc, #104] @ (800eec8 ) 800ee5e: 6adb ldr r3, [r3, #44] @ 0x2c 800ee60: 4a19 ldr r2, [pc, #100] @ (800eec8 ) 800ee62: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800ee66: 62d3 str r3, [r2, #44] @ 0x2c 800ee68: e00f b.n 800ee8a } else if (Divider == DIVIDER_Q_UPDATE) 800ee6a: 683b ldr r3, [r7, #0] 800ee6c: 2b01 cmp r3, #1 800ee6e: d106 bne.n 800ee7e { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 800ee70: 4b15 ldr r3, [pc, #84] @ (800eec8 ) 800ee72: 6adb ldr r3, [r3, #44] @ 0x2c 800ee74: 4a14 ldr r2, [pc, #80] @ (800eec8 ) 800ee76: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800ee7a: 62d3 str r3, [r2, #44] @ 0x2c 800ee7c: e005 b.n 800ee8a } else { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 800ee7e: 4b12 ldr r3, [pc, #72] @ (800eec8 ) 800ee80: 6adb ldr r3, [r3, #44] @ 0x2c 800ee82: 4a11 ldr r2, [pc, #68] @ (800eec8 ) 800ee84: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 800ee88: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL2. */ __HAL_RCC_PLL2_ENABLE(); 800ee8a: 4b0f ldr r3, [pc, #60] @ (800eec8 ) 800ee8c: 681b ldr r3, [r3, #0] 800ee8e: 4a0e ldr r2, [pc, #56] @ (800eec8 ) 800ee90: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 800ee94: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ee96: f7f6 fe8b bl 8005bb0 800ee9a: 60b8 str r0, [r7, #8] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800ee9c: e008 b.n 800eeb0 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800ee9e: f7f6 fe87 bl 8005bb0 800eea2: 4602 mov r2, r0 800eea4: 68bb ldr r3, [r7, #8] 800eea6: 1ad3 subs r3, r2, r3 800eea8: 2b02 cmp r3, #2 800eeaa: d901 bls.n 800eeb0 { return HAL_TIMEOUT; 800eeac: 2303 movs r3, #3 800eeae: e006 b.n 800eebe while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800eeb0: 4b05 ldr r3, [pc, #20] @ (800eec8 ) 800eeb2: 681b ldr r3, [r3, #0] 800eeb4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800eeb8: 2b00 cmp r3, #0 800eeba: d0f0 beq.n 800ee9e } } return status; 800eebc: 7bfb ldrb r3, [r7, #15] } 800eebe: 4618 mov r0, r3 800eec0: 3710 adds r7, #16 800eec2: 46bd mov sp, r7 800eec4: bd80 pop {r7, pc} 800eec6: bf00 nop 800eec8: 58024400 .word 0x58024400 800eecc: ffff0007 .word 0xffff0007 0800eed0 : * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { 800eed0: b580 push {r7, lr} 800eed2: b084 sub sp, #16 800eed4: af00 add r7, sp, #0 800eed6: 6078 str r0, [r7, #4] 800eed8: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800eeda: 2300 movs r3, #0 800eedc: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800eede: 4b53 ldr r3, [pc, #332] @ (800f02c ) 800eee0: 6a9b ldr r3, [r3, #40] @ 0x28 800eee2: f003 0303 and.w r3, r3, #3 800eee6: 2b03 cmp r3, #3 800eee8: d101 bne.n 800eeee { return HAL_ERROR; 800eeea: 2301 movs r3, #1 800eeec: e099 b.n 800f022 else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 800eeee: 4b4f ldr r3, [pc, #316] @ (800f02c ) 800eef0: 681b ldr r3, [r3, #0] 800eef2: 4a4e ldr r2, [pc, #312] @ (800f02c ) 800eef4: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800eef8: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800eefa: f7f6 fe59 bl 8005bb0 800eefe: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800ef00: e008 b.n 800ef14 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800ef02: f7f6 fe55 bl 8005bb0 800ef06: 4602 mov r2, r0 800ef08: 68bb ldr r3, [r7, #8] 800ef0a: 1ad3 subs r3, r2, r3 800ef0c: 2b02 cmp r3, #2 800ef0e: d901 bls.n 800ef14 { return HAL_TIMEOUT; 800ef10: 2303 movs r3, #3 800ef12: e086 b.n 800f022 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800ef14: 4b45 ldr r3, [pc, #276] @ (800f02c ) 800ef16: 681b ldr r3, [r3, #0] 800ef18: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800ef1c: 2b00 cmp r3, #0 800ef1e: d1f0 bne.n 800ef02 } } /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 800ef20: 4b42 ldr r3, [pc, #264] @ (800f02c ) 800ef22: 6a9b ldr r3, [r3, #40] @ 0x28 800ef24: f023 727c bic.w r2, r3, #66060288 @ 0x3f00000 800ef28: 687b ldr r3, [r7, #4] 800ef2a: 681b ldr r3, [r3, #0] 800ef2c: 051b lsls r3, r3, #20 800ef2e: 493f ldr r1, [pc, #252] @ (800f02c ) 800ef30: 4313 orrs r3, r2 800ef32: 628b str r3, [r1, #40] @ 0x28 800ef34: 687b ldr r3, [r7, #4] 800ef36: 685b ldr r3, [r3, #4] 800ef38: 3b01 subs r3, #1 800ef3a: f3c3 0208 ubfx r2, r3, #0, #9 800ef3e: 687b ldr r3, [r7, #4] 800ef40: 689b ldr r3, [r3, #8] 800ef42: 3b01 subs r3, #1 800ef44: 025b lsls r3, r3, #9 800ef46: b29b uxth r3, r3 800ef48: 431a orrs r2, r3 800ef4a: 687b ldr r3, [r7, #4] 800ef4c: 68db ldr r3, [r3, #12] 800ef4e: 3b01 subs r3, #1 800ef50: 041b lsls r3, r3, #16 800ef52: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800ef56: 431a orrs r2, r3 800ef58: 687b ldr r3, [r7, #4] 800ef5a: 691b ldr r3, [r3, #16] 800ef5c: 3b01 subs r3, #1 800ef5e: 061b lsls r3, r3, #24 800ef60: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800ef64: 4931 ldr r1, [pc, #196] @ (800f02c ) 800ef66: 4313 orrs r3, r2 800ef68: 640b str r3, [r1, #64] @ 0x40 pll3->PLL3P, pll3->PLL3Q, pll3->PLL3R); /* Select PLL3 input reference frequency range: VCI */ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 800ef6a: 4b30 ldr r3, [pc, #192] @ (800f02c ) 800ef6c: 6adb ldr r3, [r3, #44] @ 0x2c 800ef6e: f423 6240 bic.w r2, r3, #3072 @ 0xc00 800ef72: 687b ldr r3, [r7, #4] 800ef74: 695b ldr r3, [r3, #20] 800ef76: 492d ldr r1, [pc, #180] @ (800f02c ) 800ef78: 4313 orrs r3, r2 800ef7a: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL3 output frequency range : VCO */ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 800ef7c: 4b2b ldr r3, [pc, #172] @ (800f02c ) 800ef7e: 6adb ldr r3, [r3, #44] @ 0x2c 800ef80: f423 7200 bic.w r2, r3, #512 @ 0x200 800ef84: 687b ldr r3, [r7, #4] 800ef86: 699b ldr r3, [r3, #24] 800ef88: 4928 ldr r1, [pc, #160] @ (800f02c ) 800ef8a: 4313 orrs r3, r2 800ef8c: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_DISABLE(); 800ef8e: 4b27 ldr r3, [pc, #156] @ (800f02c ) 800ef90: 6adb ldr r3, [r3, #44] @ 0x2c 800ef92: 4a26 ldr r2, [pc, #152] @ (800f02c ) 800ef94: f423 7380 bic.w r3, r3, #256 @ 0x100 800ef98: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 800ef9a: 4b24 ldr r3, [pc, #144] @ (800f02c ) 800ef9c: 6c5a ldr r2, [r3, #68] @ 0x44 800ef9e: 4b24 ldr r3, [pc, #144] @ (800f030 ) 800efa0: 4013 ands r3, r2 800efa2: 687a ldr r2, [r7, #4] 800efa4: 69d2 ldr r2, [r2, #28] 800efa6: 00d2 lsls r2, r2, #3 800efa8: 4920 ldr r1, [pc, #128] @ (800f02c ) 800efaa: 4313 orrs r3, r2 800efac: 644b str r3, [r1, #68] @ 0x44 /* Enable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_ENABLE(); 800efae: 4b1f ldr r3, [pc, #124] @ (800f02c ) 800efb0: 6adb ldr r3, [r3, #44] @ 0x2c 800efb2: 4a1e ldr r2, [pc, #120] @ (800f02c ) 800efb4: f443 7380 orr.w r3, r3, #256 @ 0x100 800efb8: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL3 clock output */ if (Divider == DIVIDER_P_UPDATE) 800efba: 683b ldr r3, [r7, #0] 800efbc: 2b00 cmp r3, #0 800efbe: d106 bne.n 800efce { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 800efc0: 4b1a ldr r3, [pc, #104] @ (800f02c ) 800efc2: 6adb ldr r3, [r3, #44] @ 0x2c 800efc4: 4a19 ldr r2, [pc, #100] @ (800f02c ) 800efc6: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 800efca: 62d3 str r3, [r2, #44] @ 0x2c 800efcc: e00f b.n 800efee } else if (Divider == DIVIDER_Q_UPDATE) 800efce: 683b ldr r3, [r7, #0] 800efd0: 2b01 cmp r3, #1 800efd2: d106 bne.n 800efe2 { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 800efd4: 4b15 ldr r3, [pc, #84] @ (800f02c ) 800efd6: 6adb ldr r3, [r3, #44] @ 0x2c 800efd8: 4a14 ldr r2, [pc, #80] @ (800f02c ) 800efda: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 800efde: 62d3 str r3, [r2, #44] @ 0x2c 800efe0: e005 b.n 800efee } else { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 800efe2: 4b12 ldr r3, [pc, #72] @ (800f02c ) 800efe4: 6adb ldr r3, [r3, #44] @ 0x2c 800efe6: 4a11 ldr r2, [pc, #68] @ (800f02c ) 800efe8: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800efec: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL3. */ __HAL_RCC_PLL3_ENABLE(); 800efee: 4b0f ldr r3, [pc, #60] @ (800f02c ) 800eff0: 681b ldr r3, [r3, #0] 800eff2: 4a0e ldr r2, [pc, #56] @ (800f02c ) 800eff4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800eff8: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800effa: f7f6 fdd9 bl 8005bb0 800effe: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800f000: e008 b.n 800f014 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800f002: f7f6 fdd5 bl 8005bb0 800f006: 4602 mov r2, r0 800f008: 68bb ldr r3, [r7, #8] 800f00a: 1ad3 subs r3, r2, r3 800f00c: 2b02 cmp r3, #2 800f00e: d901 bls.n 800f014 { return HAL_TIMEOUT; 800f010: 2303 movs r3, #3 800f012: e006 b.n 800f022 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800f014: 4b05 ldr r3, [pc, #20] @ (800f02c ) 800f016: 681b ldr r3, [r3, #0] 800f018: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800f01c: 2b00 cmp r3, #0 800f01e: d0f0 beq.n 800f002 } } return status; 800f020: 7bfb ldrb r3, [r7, #15] } 800f022: 4618 mov r0, r3 800f024: 3710 adds r7, #16 800f026: 46bd mov sp, r7 800f028: bd80 pop {r7, pc} 800f02a: bf00 nop 800f02c: 58024400 .word 0x58024400 800f030: ffff0007 .word 0xffff0007 0800f034 : * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL status */ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { 800f034: b580 push {r7, lr} 800f036: b084 sub sp, #16 800f038: af00 add r7, sp, #0 800f03a: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the RNG handle allocation */ if (hrng == NULL) 800f03c: 687b ldr r3, [r7, #4] 800f03e: 2b00 cmp r3, #0 800f040: d101 bne.n 800f046 { return HAL_ERROR; 800f042: 2301 movs r3, #1 800f044: e054 b.n 800f0f0 /* Init the low level hardware */ hrng->MspInitCallback(hrng); } #else if (hrng->State == HAL_RNG_STATE_RESET) 800f046: 687b ldr r3, [r7, #4] 800f048: 7a5b ldrb r3, [r3, #9] 800f04a: b2db uxtb r3, r3 800f04c: 2b00 cmp r3, #0 800f04e: d105 bne.n 800f05c { /* Allocate lock resource and initialize it */ hrng->Lock = HAL_UNLOCKED; 800f050: 687b ldr r3, [r7, #4] 800f052: 2200 movs r2, #0 800f054: 721a strb r2, [r3, #8] /* Init the low level hardware */ HAL_RNG_MspInit(hrng); 800f056: 6878 ldr r0, [r7, #4] 800f058: f7f5 f82e bl 80040b8 } #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; 800f05c: 687b ldr r3, [r7, #4] 800f05e: 2202 movs r2, #2 800f060: 725a strb r2, [r3, #9] } } } #else /* Clock Error Detection Configuration */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection); 800f062: 687b ldr r3, [r7, #4] 800f064: 681b ldr r3, [r3, #0] 800f066: 681b ldr r3, [r3, #0] 800f068: f023 0120 bic.w r1, r3, #32 800f06c: 687b ldr r3, [r7, #4] 800f06e: 685a ldr r2, [r3, #4] 800f070: 687b ldr r3, [r7, #4] 800f072: 681b ldr r3, [r3, #0] 800f074: 430a orrs r2, r1 800f076: 601a str r2, [r3, #0] #endif /* RNG_CR_CONDRST */ /* Enable the RNG Peripheral */ __HAL_RNG_ENABLE(hrng); 800f078: 687b ldr r3, [r7, #4] 800f07a: 681b ldr r3, [r3, #0] 800f07c: 681a ldr r2, [r3, #0] 800f07e: 687b ldr r3, [r7, #4] 800f080: 681b ldr r3, [r3, #0] 800f082: f042 0204 orr.w r2, r2, #4 800f086: 601a str r2, [r3, #0] /* verify that no seed error */ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) 800f088: 687b ldr r3, [r7, #4] 800f08a: 681b ldr r3, [r3, #0] 800f08c: 685b ldr r3, [r3, #4] 800f08e: f003 0340 and.w r3, r3, #64 @ 0x40 800f092: 2b40 cmp r3, #64 @ 0x40 800f094: d104 bne.n 800f0a0 { hrng->State = HAL_RNG_STATE_ERROR; 800f096: 687b ldr r3, [r7, #4] 800f098: 2204 movs r2, #4 800f09a: 725a strb r2, [r3, #9] return HAL_ERROR; 800f09c: 2301 movs r3, #1 800f09e: e027 b.n 800f0f0 } /* Get tick */ tickstart = HAL_GetTick(); 800f0a0: f7f6 fd86 bl 8005bb0 800f0a4: 60f8 str r0, [r7, #12] /* Check if data register contains valid random data */ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f0a6: e015 b.n 800f0d4 { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) 800f0a8: f7f6 fd82 bl 8005bb0 800f0ac: 4602 mov r2, r0 800f0ae: 68fb ldr r3, [r7, #12] 800f0b0: 1ad3 subs r3, r2, r3 800f0b2: 2b02 cmp r3, #2 800f0b4: d90e bls.n 800f0d4 { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f0b6: 687b ldr r3, [r7, #4] 800f0b8: 681b ldr r3, [r3, #0] 800f0ba: 685b ldr r3, [r3, #4] 800f0bc: f003 0304 and.w r3, r3, #4 800f0c0: 2b04 cmp r3, #4 800f0c2: d107 bne.n 800f0d4 { hrng->State = HAL_RNG_STATE_ERROR; 800f0c4: 687b ldr r3, [r7, #4] 800f0c6: 2204 movs r2, #4 800f0c8: 725a strb r2, [r3, #9] hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; 800f0ca: 687b ldr r3, [r7, #4] 800f0cc: 2202 movs r2, #2 800f0ce: 60da str r2, [r3, #12] return HAL_ERROR; 800f0d0: 2301 movs r3, #1 800f0d2: e00d b.n 800f0f0 while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f0d4: 687b ldr r3, [r7, #4] 800f0d6: 681b ldr r3, [r3, #0] 800f0d8: 685b ldr r3, [r3, #4] 800f0da: f003 0304 and.w r3, r3, #4 800f0de: 2b04 cmp r3, #4 800f0e0: d0e2 beq.n 800f0a8 } } } /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; 800f0e2: 687b ldr r3, [r7, #4] 800f0e4: 2201 movs r2, #1 800f0e6: 725a strb r2, [r3, #9] /* Initialise the error code */ hrng->ErrorCode = HAL_RNG_ERROR_NONE; 800f0e8: 687b ldr r3, [r7, #4] 800f0ea: 2200 movs r2, #0 800f0ec: 60da str r2, [r3, #12] /* Return function status */ return HAL_OK; 800f0ee: 2300 movs r3, #0 } 800f0f0: 4618 mov r0, r3 800f0f2: 3710 adds r7, #16 800f0f4: 46bd mov sp, r7 800f0f6: bd80 pop {r7, pc} 0800f0f8 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 800f0f8: b580 push {r7, lr} 800f0fa: b082 sub sp, #8 800f0fc: af00 add r7, sp, #0 800f0fe: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800f100: 687b ldr r3, [r7, #4] 800f102: 2b00 cmp r3, #0 800f104: d101 bne.n 800f10a { return HAL_ERROR; 800f106: 2301 movs r3, #1 800f108: e049 b.n 800f19e assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800f10a: 687b ldr r3, [r7, #4] 800f10c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f110: b2db uxtb r3, r3 800f112: 2b00 cmp r3, #0 800f114: d106 bne.n 800f124 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800f116: 687b ldr r3, [r7, #4] 800f118: 2200 movs r2, #0 800f11a: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800f11e: 6878 ldr r0, [r7, #4] 800f120: f7f5 f83e bl 80041a0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f124: 687b ldr r3, [r7, #4] 800f126: 2202 movs r2, #2 800f128: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800f12c: 687b ldr r3, [r7, #4] 800f12e: 681a ldr r2, [r3, #0] 800f130: 687b ldr r3, [r7, #4] 800f132: 3304 adds r3, #4 800f134: 4619 mov r1, r3 800f136: 4610 mov r0, r2 800f138: f000 fe90 bl 800fe5c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800f13c: 687b ldr r3, [r7, #4] 800f13e: 2201 movs r2, #1 800f140: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f144: 687b ldr r3, [r7, #4] 800f146: 2201 movs r2, #1 800f148: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f14c: 687b ldr r3, [r7, #4] 800f14e: 2201 movs r2, #1 800f150: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f154: 687b ldr r3, [r7, #4] 800f156: 2201 movs r2, #1 800f158: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f15c: 687b ldr r3, [r7, #4] 800f15e: 2201 movs r2, #1 800f160: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f164: 687b ldr r3, [r7, #4] 800f166: 2201 movs r2, #1 800f168: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f16c: 687b ldr r3, [r7, #4] 800f16e: 2201 movs r2, #1 800f170: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f174: 687b ldr r3, [r7, #4] 800f176: 2201 movs r2, #1 800f178: f883 2044 strb.w r2, [r3, #68] @ 0x44 800f17c: 687b ldr r3, [r7, #4] 800f17e: 2201 movs r2, #1 800f180: f883 2045 strb.w r2, [r3, #69] @ 0x45 800f184: 687b ldr r3, [r7, #4] 800f186: 2201 movs r2, #1 800f188: f883 2046 strb.w r2, [r3, #70] @ 0x46 800f18c: 687b ldr r3, [r7, #4] 800f18e: 2201 movs r2, #1 800f190: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800f194: 687b ldr r3, [r7, #4] 800f196: 2201 movs r2, #1 800f198: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800f19c: 2300 movs r3, #0 } 800f19e: 4618 mov r0, r3 800f1a0: 3708 adds r7, #8 800f1a2: 46bd mov sp, r7 800f1a4: bd80 pop {r7, pc} ... 0800f1a8 : * @brief Starts the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { 800f1a8: b480 push {r7} 800f1aa: b085 sub sp, #20 800f1ac: af00 add r7, sp, #0 800f1ae: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800f1b0: 687b ldr r3, [r7, #4] 800f1b2: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f1b6: b2db uxtb r3, r3 800f1b8: 2b01 cmp r3, #1 800f1ba: d001 beq.n 800f1c0 { return HAL_ERROR; 800f1bc: 2301 movs r3, #1 800f1be: e04c b.n 800f25a } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f1c0: 687b ldr r3, [r7, #4] 800f1c2: 2202 movs r2, #2 800f1c4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f1c8: 687b ldr r3, [r7, #4] 800f1ca: 681b ldr r3, [r3, #0] 800f1cc: 4a26 ldr r2, [pc, #152] @ (800f268 ) 800f1ce: 4293 cmp r3, r2 800f1d0: d022 beq.n 800f218 800f1d2: 687b ldr r3, [r7, #4] 800f1d4: 681b ldr r3, [r3, #0] 800f1d6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f1da: d01d beq.n 800f218 800f1dc: 687b ldr r3, [r7, #4] 800f1de: 681b ldr r3, [r3, #0] 800f1e0: 4a22 ldr r2, [pc, #136] @ (800f26c ) 800f1e2: 4293 cmp r3, r2 800f1e4: d018 beq.n 800f218 800f1e6: 687b ldr r3, [r7, #4] 800f1e8: 681b ldr r3, [r3, #0] 800f1ea: 4a21 ldr r2, [pc, #132] @ (800f270 ) 800f1ec: 4293 cmp r3, r2 800f1ee: d013 beq.n 800f218 800f1f0: 687b ldr r3, [r7, #4] 800f1f2: 681b ldr r3, [r3, #0] 800f1f4: 4a1f ldr r2, [pc, #124] @ (800f274 ) 800f1f6: 4293 cmp r3, r2 800f1f8: d00e beq.n 800f218 800f1fa: 687b ldr r3, [r7, #4] 800f1fc: 681b ldr r3, [r3, #0] 800f1fe: 4a1e ldr r2, [pc, #120] @ (800f278 ) 800f200: 4293 cmp r3, r2 800f202: d009 beq.n 800f218 800f204: 687b ldr r3, [r7, #4] 800f206: 681b ldr r3, [r3, #0] 800f208: 4a1c ldr r2, [pc, #112] @ (800f27c ) 800f20a: 4293 cmp r3, r2 800f20c: d004 beq.n 800f218 800f20e: 687b ldr r3, [r7, #4] 800f210: 681b ldr r3, [r3, #0] 800f212: 4a1b ldr r2, [pc, #108] @ (800f280 ) 800f214: 4293 cmp r3, r2 800f216: d115 bne.n 800f244 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f218: 687b ldr r3, [r7, #4] 800f21a: 681b ldr r3, [r3, #0] 800f21c: 689a ldr r2, [r3, #8] 800f21e: 4b19 ldr r3, [pc, #100] @ (800f284 ) 800f220: 4013 ands r3, r2 800f222: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f224: 68fb ldr r3, [r7, #12] 800f226: 2b06 cmp r3, #6 800f228: d015 beq.n 800f256 800f22a: 68fb ldr r3, [r7, #12] 800f22c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f230: d011 beq.n 800f256 { __HAL_TIM_ENABLE(htim); 800f232: 687b ldr r3, [r7, #4] 800f234: 681b ldr r3, [r3, #0] 800f236: 681a ldr r2, [r3, #0] 800f238: 687b ldr r3, [r7, #4] 800f23a: 681b ldr r3, [r3, #0] 800f23c: f042 0201 orr.w r2, r2, #1 800f240: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f242: e008 b.n 800f256 } } else { __HAL_TIM_ENABLE(htim); 800f244: 687b ldr r3, [r7, #4] 800f246: 681b ldr r3, [r3, #0] 800f248: 681a ldr r2, [r3, #0] 800f24a: 687b ldr r3, [r7, #4] 800f24c: 681b ldr r3, [r3, #0] 800f24e: f042 0201 orr.w r2, r2, #1 800f252: 601a str r2, [r3, #0] 800f254: e000 b.n 800f258 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f256: bf00 nop } /* Return function status */ return HAL_OK; 800f258: 2300 movs r3, #0 } 800f25a: 4618 mov r0, r3 800f25c: 3714 adds r7, #20 800f25e: 46bd mov sp, r7 800f260: f85d 7b04 ldr.w r7, [sp], #4 800f264: 4770 bx lr 800f266: bf00 nop 800f268: 40010000 .word 0x40010000 800f26c: 40000400 .word 0x40000400 800f270: 40000800 .word 0x40000800 800f274: 40000c00 .word 0x40000c00 800f278: 40010400 .word 0x40010400 800f27c: 40001800 .word 0x40001800 800f280: 40014000 .word 0x40014000 800f284: 00010007 .word 0x00010007 0800f288 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 800f288: b480 push {r7} 800f28a: b085 sub sp, #20 800f28c: af00 add r7, sp, #0 800f28e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800f290: 687b ldr r3, [r7, #4] 800f292: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f296: b2db uxtb r3, r3 800f298: 2b01 cmp r3, #1 800f29a: d001 beq.n 800f2a0 { return HAL_ERROR; 800f29c: 2301 movs r3, #1 800f29e: e054 b.n 800f34a } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f2a0: 687b ldr r3, [r7, #4] 800f2a2: 2202 movs r2, #2 800f2a4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 800f2a8: 687b ldr r3, [r7, #4] 800f2aa: 681b ldr r3, [r3, #0] 800f2ac: 68da ldr r2, [r3, #12] 800f2ae: 687b ldr r3, [r7, #4] 800f2b0: 681b ldr r3, [r3, #0] 800f2b2: f042 0201 orr.w r2, r2, #1 800f2b6: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f2b8: 687b ldr r3, [r7, #4] 800f2ba: 681b ldr r3, [r3, #0] 800f2bc: 4a26 ldr r2, [pc, #152] @ (800f358 ) 800f2be: 4293 cmp r3, r2 800f2c0: d022 beq.n 800f308 800f2c2: 687b ldr r3, [r7, #4] 800f2c4: 681b ldr r3, [r3, #0] 800f2c6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f2ca: d01d beq.n 800f308 800f2cc: 687b ldr r3, [r7, #4] 800f2ce: 681b ldr r3, [r3, #0] 800f2d0: 4a22 ldr r2, [pc, #136] @ (800f35c ) 800f2d2: 4293 cmp r3, r2 800f2d4: d018 beq.n 800f308 800f2d6: 687b ldr r3, [r7, #4] 800f2d8: 681b ldr r3, [r3, #0] 800f2da: 4a21 ldr r2, [pc, #132] @ (800f360 ) 800f2dc: 4293 cmp r3, r2 800f2de: d013 beq.n 800f308 800f2e0: 687b ldr r3, [r7, #4] 800f2e2: 681b ldr r3, [r3, #0] 800f2e4: 4a1f ldr r2, [pc, #124] @ (800f364 ) 800f2e6: 4293 cmp r3, r2 800f2e8: d00e beq.n 800f308 800f2ea: 687b ldr r3, [r7, #4] 800f2ec: 681b ldr r3, [r3, #0] 800f2ee: 4a1e ldr r2, [pc, #120] @ (800f368 ) 800f2f0: 4293 cmp r3, r2 800f2f2: d009 beq.n 800f308 800f2f4: 687b ldr r3, [r7, #4] 800f2f6: 681b ldr r3, [r3, #0] 800f2f8: 4a1c ldr r2, [pc, #112] @ (800f36c ) 800f2fa: 4293 cmp r3, r2 800f2fc: d004 beq.n 800f308 800f2fe: 687b ldr r3, [r7, #4] 800f300: 681b ldr r3, [r3, #0] 800f302: 4a1b ldr r2, [pc, #108] @ (800f370 ) 800f304: 4293 cmp r3, r2 800f306: d115 bne.n 800f334 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f308: 687b ldr r3, [r7, #4] 800f30a: 681b ldr r3, [r3, #0] 800f30c: 689a ldr r2, [r3, #8] 800f30e: 4b19 ldr r3, [pc, #100] @ (800f374 ) 800f310: 4013 ands r3, r2 800f312: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f314: 68fb ldr r3, [r7, #12] 800f316: 2b06 cmp r3, #6 800f318: d015 beq.n 800f346 800f31a: 68fb ldr r3, [r7, #12] 800f31c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f320: d011 beq.n 800f346 { __HAL_TIM_ENABLE(htim); 800f322: 687b ldr r3, [r7, #4] 800f324: 681b ldr r3, [r3, #0] 800f326: 681a ldr r2, [r3, #0] 800f328: 687b ldr r3, [r7, #4] 800f32a: 681b ldr r3, [r3, #0] 800f32c: f042 0201 orr.w r2, r2, #1 800f330: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f332: e008 b.n 800f346 } } else { __HAL_TIM_ENABLE(htim); 800f334: 687b ldr r3, [r7, #4] 800f336: 681b ldr r3, [r3, #0] 800f338: 681a ldr r2, [r3, #0] 800f33a: 687b ldr r3, [r7, #4] 800f33c: 681b ldr r3, [r3, #0] 800f33e: f042 0201 orr.w r2, r2, #1 800f342: 601a str r2, [r3, #0] 800f344: e000 b.n 800f348 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f346: bf00 nop } /* Return function status */ return HAL_OK; 800f348: 2300 movs r3, #0 } 800f34a: 4618 mov r0, r3 800f34c: 3714 adds r7, #20 800f34e: 46bd mov sp, r7 800f350: f85d 7b04 ldr.w r7, [sp], #4 800f354: 4770 bx lr 800f356: bf00 nop 800f358: 40010000 .word 0x40010000 800f35c: 40000400 .word 0x40000400 800f360: 40000800 .word 0x40000800 800f364: 40000c00 .word 0x40000c00 800f368: 40010400 .word 0x40010400 800f36c: 40001800 .word 0x40001800 800f370: 40014000 .word 0x40014000 800f374: 00010007 .word 0x00010007 0800f378 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 800f378: b580 push {r7, lr} 800f37a: b082 sub sp, #8 800f37c: af00 add r7, sp, #0 800f37e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800f380: 687b ldr r3, [r7, #4] 800f382: 2b00 cmp r3, #0 800f384: d101 bne.n 800f38a { return HAL_ERROR; 800f386: 2301 movs r3, #1 800f388: e049 b.n 800f41e assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800f38a: 687b ldr r3, [r7, #4] 800f38c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f390: b2db uxtb r3, r3 800f392: 2b00 cmp r3, #0 800f394: d106 bne.n 800f3a4 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800f396: 687b ldr r3, [r7, #4] 800f398: 2200 movs r2, #0 800f39a: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 800f39e: 6878 ldr r0, [r7, #4] 800f3a0: f7f4 fec4 bl 800412c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f3a4: 687b ldr r3, [r7, #4] 800f3a6: 2202 movs r2, #2 800f3a8: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800f3ac: 687b ldr r3, [r7, #4] 800f3ae: 681a ldr r2, [r3, #0] 800f3b0: 687b ldr r3, [r7, #4] 800f3b2: 3304 adds r3, #4 800f3b4: 4619 mov r1, r3 800f3b6: 4610 mov r0, r2 800f3b8: f000 fd50 bl 800fe5c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800f3bc: 687b ldr r3, [r7, #4] 800f3be: 2201 movs r2, #1 800f3c0: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f3c4: 687b ldr r3, [r7, #4] 800f3c6: 2201 movs r2, #1 800f3c8: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f3cc: 687b ldr r3, [r7, #4] 800f3ce: 2201 movs r2, #1 800f3d0: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f3d4: 687b ldr r3, [r7, #4] 800f3d6: 2201 movs r2, #1 800f3d8: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f3dc: 687b ldr r3, [r7, #4] 800f3de: 2201 movs r2, #1 800f3e0: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f3e4: 687b ldr r3, [r7, #4] 800f3e6: 2201 movs r2, #1 800f3e8: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f3ec: 687b ldr r3, [r7, #4] 800f3ee: 2201 movs r2, #1 800f3f0: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f3f4: 687b ldr r3, [r7, #4] 800f3f6: 2201 movs r2, #1 800f3f8: f883 2044 strb.w r2, [r3, #68] @ 0x44 800f3fc: 687b ldr r3, [r7, #4] 800f3fe: 2201 movs r2, #1 800f400: f883 2045 strb.w r2, [r3, #69] @ 0x45 800f404: 687b ldr r3, [r7, #4] 800f406: 2201 movs r2, #1 800f408: f883 2046 strb.w r2, [r3, #70] @ 0x46 800f40c: 687b ldr r3, [r7, #4] 800f40e: 2201 movs r2, #1 800f410: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800f414: 687b ldr r3, [r7, #4] 800f416: 2201 movs r2, #1 800f418: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800f41c: 2300 movs r3, #0 } 800f41e: 4618 mov r0, r3 800f420: 3708 adds r7, #8 800f422: 46bd mov sp, r7 800f424: bd80 pop {r7, pc} ... 0800f428 : * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 800f428: b580 push {r7, lr} 800f42a: b084 sub sp, #16 800f42c: af00 add r7, sp, #0 800f42e: 6078 str r0, [r7, #4] 800f430: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 800f432: 683b ldr r3, [r7, #0] 800f434: 2b00 cmp r3, #0 800f436: d109 bne.n 800f44c 800f438: 687b ldr r3, [r7, #4] 800f43a: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800f43e: b2db uxtb r3, r3 800f440: 2b01 cmp r3, #1 800f442: bf14 ite ne 800f444: 2301 movne r3, #1 800f446: 2300 moveq r3, #0 800f448: b2db uxtb r3, r3 800f44a: e03c b.n 800f4c6 800f44c: 683b ldr r3, [r7, #0] 800f44e: 2b04 cmp r3, #4 800f450: d109 bne.n 800f466 800f452: 687b ldr r3, [r7, #4] 800f454: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800f458: b2db uxtb r3, r3 800f45a: 2b01 cmp r3, #1 800f45c: bf14 ite ne 800f45e: 2301 movne r3, #1 800f460: 2300 moveq r3, #0 800f462: b2db uxtb r3, r3 800f464: e02f b.n 800f4c6 800f466: 683b ldr r3, [r7, #0] 800f468: 2b08 cmp r3, #8 800f46a: d109 bne.n 800f480 800f46c: 687b ldr r3, [r7, #4] 800f46e: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800f472: b2db uxtb r3, r3 800f474: 2b01 cmp r3, #1 800f476: bf14 ite ne 800f478: 2301 movne r3, #1 800f47a: 2300 moveq r3, #0 800f47c: b2db uxtb r3, r3 800f47e: e022 b.n 800f4c6 800f480: 683b ldr r3, [r7, #0] 800f482: 2b0c cmp r3, #12 800f484: d109 bne.n 800f49a 800f486: 687b ldr r3, [r7, #4] 800f488: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800f48c: b2db uxtb r3, r3 800f48e: 2b01 cmp r3, #1 800f490: bf14 ite ne 800f492: 2301 movne r3, #1 800f494: 2300 moveq r3, #0 800f496: b2db uxtb r3, r3 800f498: e015 b.n 800f4c6 800f49a: 683b ldr r3, [r7, #0] 800f49c: 2b10 cmp r3, #16 800f49e: d109 bne.n 800f4b4 800f4a0: 687b ldr r3, [r7, #4] 800f4a2: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800f4a6: b2db uxtb r3, r3 800f4a8: 2b01 cmp r3, #1 800f4aa: bf14 ite ne 800f4ac: 2301 movne r3, #1 800f4ae: 2300 moveq r3, #0 800f4b0: b2db uxtb r3, r3 800f4b2: e008 b.n 800f4c6 800f4b4: 687b ldr r3, [r7, #4] 800f4b6: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800f4ba: b2db uxtb r3, r3 800f4bc: 2b01 cmp r3, #1 800f4be: bf14 ite ne 800f4c0: 2301 movne r3, #1 800f4c2: 2300 moveq r3, #0 800f4c4: b2db uxtb r3, r3 800f4c6: 2b00 cmp r3, #0 800f4c8: d001 beq.n 800f4ce { return HAL_ERROR; 800f4ca: 2301 movs r3, #1 800f4cc: e0a1 b.n 800f612 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800f4ce: 683b ldr r3, [r7, #0] 800f4d0: 2b00 cmp r3, #0 800f4d2: d104 bne.n 800f4de 800f4d4: 687b ldr r3, [r7, #4] 800f4d6: 2202 movs r2, #2 800f4d8: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f4dc: e023 b.n 800f526 800f4de: 683b ldr r3, [r7, #0] 800f4e0: 2b04 cmp r3, #4 800f4e2: d104 bne.n 800f4ee 800f4e4: 687b ldr r3, [r7, #4] 800f4e6: 2202 movs r2, #2 800f4e8: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f4ec: e01b b.n 800f526 800f4ee: 683b ldr r3, [r7, #0] 800f4f0: 2b08 cmp r3, #8 800f4f2: d104 bne.n 800f4fe 800f4f4: 687b ldr r3, [r7, #4] 800f4f6: 2202 movs r2, #2 800f4f8: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f4fc: e013 b.n 800f526 800f4fe: 683b ldr r3, [r7, #0] 800f500: 2b0c cmp r3, #12 800f502: d104 bne.n 800f50e 800f504: 687b ldr r3, [r7, #4] 800f506: 2202 movs r2, #2 800f508: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f50c: e00b b.n 800f526 800f50e: 683b ldr r3, [r7, #0] 800f510: 2b10 cmp r3, #16 800f512: d104 bne.n 800f51e 800f514: 687b ldr r3, [r7, #4] 800f516: 2202 movs r2, #2 800f518: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f51c: e003 b.n 800f526 800f51e: 687b ldr r3, [r7, #4] 800f520: 2202 movs r2, #2 800f522: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 800f526: 687b ldr r3, [r7, #4] 800f528: 681b ldr r3, [r3, #0] 800f52a: 2201 movs r2, #1 800f52c: 6839 ldr r1, [r7, #0] 800f52e: 4618 mov r0, r3 800f530: f001 f8ae bl 8010690 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800f534: 687b ldr r3, [r7, #4] 800f536: 681b ldr r3, [r3, #0] 800f538: 4a38 ldr r2, [pc, #224] @ (800f61c ) 800f53a: 4293 cmp r3, r2 800f53c: d013 beq.n 800f566 800f53e: 687b ldr r3, [r7, #4] 800f540: 681b ldr r3, [r3, #0] 800f542: 4a37 ldr r2, [pc, #220] @ (800f620 ) 800f544: 4293 cmp r3, r2 800f546: d00e beq.n 800f566 800f548: 687b ldr r3, [r7, #4] 800f54a: 681b ldr r3, [r3, #0] 800f54c: 4a35 ldr r2, [pc, #212] @ (800f624 ) 800f54e: 4293 cmp r3, r2 800f550: d009 beq.n 800f566 800f552: 687b ldr r3, [r7, #4] 800f554: 681b ldr r3, [r3, #0] 800f556: 4a34 ldr r2, [pc, #208] @ (800f628 ) 800f558: 4293 cmp r3, r2 800f55a: d004 beq.n 800f566 800f55c: 687b ldr r3, [r7, #4] 800f55e: 681b ldr r3, [r3, #0] 800f560: 4a32 ldr r2, [pc, #200] @ (800f62c ) 800f562: 4293 cmp r3, r2 800f564: d101 bne.n 800f56a 800f566: 2301 movs r3, #1 800f568: e000 b.n 800f56c 800f56a: 2300 movs r3, #0 800f56c: 2b00 cmp r3, #0 800f56e: d007 beq.n 800f580 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 800f570: 687b ldr r3, [r7, #4] 800f572: 681b ldr r3, [r3, #0] 800f574: 6c5a ldr r2, [r3, #68] @ 0x44 800f576: 687b ldr r3, [r7, #4] 800f578: 681b ldr r3, [r3, #0] 800f57a: f442 4200 orr.w r2, r2, #32768 @ 0x8000 800f57e: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f580: 687b ldr r3, [r7, #4] 800f582: 681b ldr r3, [r3, #0] 800f584: 4a25 ldr r2, [pc, #148] @ (800f61c ) 800f586: 4293 cmp r3, r2 800f588: d022 beq.n 800f5d0 800f58a: 687b ldr r3, [r7, #4] 800f58c: 681b ldr r3, [r3, #0] 800f58e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f592: d01d beq.n 800f5d0 800f594: 687b ldr r3, [r7, #4] 800f596: 681b ldr r3, [r3, #0] 800f598: 4a25 ldr r2, [pc, #148] @ (800f630 ) 800f59a: 4293 cmp r3, r2 800f59c: d018 beq.n 800f5d0 800f59e: 687b ldr r3, [r7, #4] 800f5a0: 681b ldr r3, [r3, #0] 800f5a2: 4a24 ldr r2, [pc, #144] @ (800f634 ) 800f5a4: 4293 cmp r3, r2 800f5a6: d013 beq.n 800f5d0 800f5a8: 687b ldr r3, [r7, #4] 800f5aa: 681b ldr r3, [r3, #0] 800f5ac: 4a22 ldr r2, [pc, #136] @ (800f638 ) 800f5ae: 4293 cmp r3, r2 800f5b0: d00e beq.n 800f5d0 800f5b2: 687b ldr r3, [r7, #4] 800f5b4: 681b ldr r3, [r3, #0] 800f5b6: 4a1a ldr r2, [pc, #104] @ (800f620 ) 800f5b8: 4293 cmp r3, r2 800f5ba: d009 beq.n 800f5d0 800f5bc: 687b ldr r3, [r7, #4] 800f5be: 681b ldr r3, [r3, #0] 800f5c0: 4a1e ldr r2, [pc, #120] @ (800f63c ) 800f5c2: 4293 cmp r3, r2 800f5c4: d004 beq.n 800f5d0 800f5c6: 687b ldr r3, [r7, #4] 800f5c8: 681b ldr r3, [r3, #0] 800f5ca: 4a16 ldr r2, [pc, #88] @ (800f624 ) 800f5cc: 4293 cmp r3, r2 800f5ce: d115 bne.n 800f5fc { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f5d0: 687b ldr r3, [r7, #4] 800f5d2: 681b ldr r3, [r3, #0] 800f5d4: 689a ldr r2, [r3, #8] 800f5d6: 4b1a ldr r3, [pc, #104] @ (800f640 ) 800f5d8: 4013 ands r3, r2 800f5da: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f5dc: 68fb ldr r3, [r7, #12] 800f5de: 2b06 cmp r3, #6 800f5e0: d015 beq.n 800f60e 800f5e2: 68fb ldr r3, [r7, #12] 800f5e4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f5e8: d011 beq.n 800f60e { __HAL_TIM_ENABLE(htim); 800f5ea: 687b ldr r3, [r7, #4] 800f5ec: 681b ldr r3, [r3, #0] 800f5ee: 681a ldr r2, [r3, #0] 800f5f0: 687b ldr r3, [r7, #4] 800f5f2: 681b ldr r3, [r3, #0] 800f5f4: f042 0201 orr.w r2, r2, #1 800f5f8: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f5fa: e008 b.n 800f60e } } else { __HAL_TIM_ENABLE(htim); 800f5fc: 687b ldr r3, [r7, #4] 800f5fe: 681b ldr r3, [r3, #0] 800f600: 681a ldr r2, [r3, #0] 800f602: 687b ldr r3, [r7, #4] 800f604: 681b ldr r3, [r3, #0] 800f606: f042 0201 orr.w r2, r2, #1 800f60a: 601a str r2, [r3, #0] 800f60c: e000 b.n 800f610 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f60e: bf00 nop } /* Return function status */ return HAL_OK; 800f610: 2300 movs r3, #0 } 800f612: 4618 mov r0, r3 800f614: 3710 adds r7, #16 800f616: 46bd mov sp, r7 800f618: bd80 pop {r7, pc} 800f61a: bf00 nop 800f61c: 40010000 .word 0x40010000 800f620: 40010400 .word 0x40010400 800f624: 40014000 .word 0x40014000 800f628: 40014400 .word 0x40014400 800f62c: 40014800 .word 0x40014800 800f630: 40000400 .word 0x40000400 800f634: 40000800 .word 0x40000800 800f638: 40000c00 .word 0x40000c00 800f63c: 40001800 .word 0x40001800 800f640: 00010007 .word 0x00010007 0800f644 : * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { 800f644: b580 push {r7, lr} 800f646: b082 sub sp, #8 800f648: af00 add r7, sp, #0 800f64a: 6078 str r0, [r7, #4] 800f64c: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 800f64e: 687b ldr r3, [r7, #4] 800f650: 681b ldr r3, [r3, #0] 800f652: 2200 movs r2, #0 800f654: 6839 ldr r1, [r7, #0] 800f656: 4618 mov r0, r3 800f658: f001 f81a bl 8010690 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800f65c: 687b ldr r3, [r7, #4] 800f65e: 681b ldr r3, [r3, #0] 800f660: 4a3e ldr r2, [pc, #248] @ (800f75c ) 800f662: 4293 cmp r3, r2 800f664: d013 beq.n 800f68e 800f666: 687b ldr r3, [r7, #4] 800f668: 681b ldr r3, [r3, #0] 800f66a: 4a3d ldr r2, [pc, #244] @ (800f760 ) 800f66c: 4293 cmp r3, r2 800f66e: d00e beq.n 800f68e 800f670: 687b ldr r3, [r7, #4] 800f672: 681b ldr r3, [r3, #0] 800f674: 4a3b ldr r2, [pc, #236] @ (800f764 ) 800f676: 4293 cmp r3, r2 800f678: d009 beq.n 800f68e 800f67a: 687b ldr r3, [r7, #4] 800f67c: 681b ldr r3, [r3, #0] 800f67e: 4a3a ldr r2, [pc, #232] @ (800f768 ) 800f680: 4293 cmp r3, r2 800f682: d004 beq.n 800f68e 800f684: 687b ldr r3, [r7, #4] 800f686: 681b ldr r3, [r3, #0] 800f688: 4a38 ldr r2, [pc, #224] @ (800f76c ) 800f68a: 4293 cmp r3, r2 800f68c: d101 bne.n 800f692 800f68e: 2301 movs r3, #1 800f690: e000 b.n 800f694 800f692: 2300 movs r3, #0 800f694: 2b00 cmp r3, #0 800f696: d017 beq.n 800f6c8 { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); 800f698: 687b ldr r3, [r7, #4] 800f69a: 681b ldr r3, [r3, #0] 800f69c: 6a1a ldr r2, [r3, #32] 800f69e: f241 1311 movw r3, #4369 @ 0x1111 800f6a2: 4013 ands r3, r2 800f6a4: 2b00 cmp r3, #0 800f6a6: d10f bne.n 800f6c8 800f6a8: 687b ldr r3, [r7, #4] 800f6aa: 681b ldr r3, [r3, #0] 800f6ac: 6a1a ldr r2, [r3, #32] 800f6ae: f240 4344 movw r3, #1092 @ 0x444 800f6b2: 4013 ands r3, r2 800f6b4: 2b00 cmp r3, #0 800f6b6: d107 bne.n 800f6c8 800f6b8: 687b ldr r3, [r7, #4] 800f6ba: 681b ldr r3, [r3, #0] 800f6bc: 6c5a ldr r2, [r3, #68] @ 0x44 800f6be: 687b ldr r3, [r7, #4] 800f6c0: 681b ldr r3, [r3, #0] 800f6c2: f422 4200 bic.w r2, r2, #32768 @ 0x8000 800f6c6: 645a str r2, [r3, #68] @ 0x44 } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); 800f6c8: 687b ldr r3, [r7, #4] 800f6ca: 681b ldr r3, [r3, #0] 800f6cc: 6a1a ldr r2, [r3, #32] 800f6ce: f241 1311 movw r3, #4369 @ 0x1111 800f6d2: 4013 ands r3, r2 800f6d4: 2b00 cmp r3, #0 800f6d6: d10f bne.n 800f6f8 800f6d8: 687b ldr r3, [r7, #4] 800f6da: 681b ldr r3, [r3, #0] 800f6dc: 6a1a ldr r2, [r3, #32] 800f6de: f240 4344 movw r3, #1092 @ 0x444 800f6e2: 4013 ands r3, r2 800f6e4: 2b00 cmp r3, #0 800f6e6: d107 bne.n 800f6f8 800f6e8: 687b ldr r3, [r7, #4] 800f6ea: 681b ldr r3, [r3, #0] 800f6ec: 681a ldr r2, [r3, #0] 800f6ee: 687b ldr r3, [r7, #4] 800f6f0: 681b ldr r3, [r3, #0] 800f6f2: f022 0201 bic.w r2, r2, #1 800f6f6: 601a str r2, [r3, #0] /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); 800f6f8: 683b ldr r3, [r7, #0] 800f6fa: 2b00 cmp r3, #0 800f6fc: d104 bne.n 800f708 800f6fe: 687b ldr r3, [r7, #4] 800f700: 2201 movs r2, #1 800f702: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f706: e023 b.n 800f750 800f708: 683b ldr r3, [r7, #0] 800f70a: 2b04 cmp r3, #4 800f70c: d104 bne.n 800f718 800f70e: 687b ldr r3, [r7, #4] 800f710: 2201 movs r2, #1 800f712: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f716: e01b b.n 800f750 800f718: 683b ldr r3, [r7, #0] 800f71a: 2b08 cmp r3, #8 800f71c: d104 bne.n 800f728 800f71e: 687b ldr r3, [r7, #4] 800f720: 2201 movs r2, #1 800f722: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f726: e013 b.n 800f750 800f728: 683b ldr r3, [r7, #0] 800f72a: 2b0c cmp r3, #12 800f72c: d104 bne.n 800f738 800f72e: 687b ldr r3, [r7, #4] 800f730: 2201 movs r2, #1 800f732: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f736: e00b b.n 800f750 800f738: 683b ldr r3, [r7, #0] 800f73a: 2b10 cmp r3, #16 800f73c: d104 bne.n 800f748 800f73e: 687b ldr r3, [r7, #4] 800f740: 2201 movs r2, #1 800f742: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f746: e003 b.n 800f750 800f748: 687b ldr r3, [r7, #4] 800f74a: 2201 movs r2, #1 800f74c: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Return function status */ return HAL_OK; 800f750: 2300 movs r3, #0 } 800f752: 4618 mov r0, r3 800f754: 3708 adds r7, #8 800f756: 46bd mov sp, r7 800f758: bd80 pop {r7, pc} 800f75a: bf00 nop 800f75c: 40010000 .word 0x40010000 800f760: 40010400 .word 0x40010400 800f764: 40014000 .word 0x40014000 800f768: 40014400 .word 0x40014400 800f76c: 40014800 .word 0x40014800 0800f770 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 800f770: b580 push {r7, lr} 800f772: b084 sub sp, #16 800f774: af00 add r7, sp, #0 800f776: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 800f778: 687b ldr r3, [r7, #4] 800f77a: 681b ldr r3, [r3, #0] 800f77c: 68db ldr r3, [r3, #12] 800f77e: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 800f780: 687b ldr r3, [r7, #4] 800f782: 681b ldr r3, [r3, #0] 800f784: 691b ldr r3, [r3, #16] 800f786: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 800f788: 68bb ldr r3, [r7, #8] 800f78a: f003 0302 and.w r3, r3, #2 800f78e: 2b00 cmp r3, #0 800f790: d020 beq.n 800f7d4 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 800f792: 68fb ldr r3, [r7, #12] 800f794: f003 0302 and.w r3, r3, #2 800f798: 2b00 cmp r3, #0 800f79a: d01b beq.n 800f7d4 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 800f79c: 687b ldr r3, [r7, #4] 800f79e: 681b ldr r3, [r3, #0] 800f7a0: f06f 0202 mvn.w r2, #2 800f7a4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800f7a6: 687b ldr r3, [r7, #4] 800f7a8: 2201 movs r2, #1 800f7aa: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 800f7ac: 687b ldr r3, [r7, #4] 800f7ae: 681b ldr r3, [r3, #0] 800f7b0: 699b ldr r3, [r3, #24] 800f7b2: f003 0303 and.w r3, r3, #3 800f7b6: 2b00 cmp r3, #0 800f7b8: d003 beq.n 800f7c2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800f7ba: 6878 ldr r0, [r7, #4] 800f7bc: f000 faf6 bl 800fdac 800f7c0: e005 b.n 800f7ce { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800f7c2: 6878 ldr r0, [r7, #4] 800f7c4: f000 fae8 bl 800fd98 HAL_TIM_PWM_PulseFinishedCallback(htim); 800f7c8: 6878 ldr r0, [r7, #4] 800f7ca: f000 faf9 bl 800fdc0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800f7ce: 687b ldr r3, [r7, #4] 800f7d0: 2200 movs r2, #0 800f7d2: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 800f7d4: 68bb ldr r3, [r7, #8] 800f7d6: f003 0304 and.w r3, r3, #4 800f7da: 2b00 cmp r3, #0 800f7dc: d020 beq.n 800f820 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 800f7de: 68fb ldr r3, [r7, #12] 800f7e0: f003 0304 and.w r3, r3, #4 800f7e4: 2b00 cmp r3, #0 800f7e6: d01b beq.n 800f820 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 800f7e8: 687b ldr r3, [r7, #4] 800f7ea: 681b ldr r3, [r3, #0] 800f7ec: f06f 0204 mvn.w r2, #4 800f7f0: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800f7f2: 687b ldr r3, [r7, #4] 800f7f4: 2202 movs r2, #2 800f7f6: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 800f7f8: 687b ldr r3, [r7, #4] 800f7fa: 681b ldr r3, [r3, #0] 800f7fc: 699b ldr r3, [r3, #24] 800f7fe: f403 7340 and.w r3, r3, #768 @ 0x300 800f802: 2b00 cmp r3, #0 800f804: d003 beq.n 800f80e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800f806: 6878 ldr r0, [r7, #4] 800f808: f000 fad0 bl 800fdac 800f80c: e005 b.n 800f81a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800f80e: 6878 ldr r0, [r7, #4] 800f810: f000 fac2 bl 800fd98 HAL_TIM_PWM_PulseFinishedCallback(htim); 800f814: 6878 ldr r0, [r7, #4] 800f816: f000 fad3 bl 800fdc0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800f81a: 687b ldr r3, [r7, #4] 800f81c: 2200 movs r2, #0 800f81e: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 800f820: 68bb ldr r3, [r7, #8] 800f822: f003 0308 and.w r3, r3, #8 800f826: 2b00 cmp r3, #0 800f828: d020 beq.n 800f86c { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 800f82a: 68fb ldr r3, [r7, #12] 800f82c: f003 0308 and.w r3, r3, #8 800f830: 2b00 cmp r3, #0 800f832: d01b beq.n 800f86c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 800f834: 687b ldr r3, [r7, #4] 800f836: 681b ldr r3, [r3, #0] 800f838: f06f 0208 mvn.w r2, #8 800f83c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800f83e: 687b ldr r3, [r7, #4] 800f840: 2204 movs r2, #4 800f842: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800f844: 687b ldr r3, [r7, #4] 800f846: 681b ldr r3, [r3, #0] 800f848: 69db ldr r3, [r3, #28] 800f84a: f003 0303 and.w r3, r3, #3 800f84e: 2b00 cmp r3, #0 800f850: d003 beq.n 800f85a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800f852: 6878 ldr r0, [r7, #4] 800f854: f000 faaa bl 800fdac 800f858: e005 b.n 800f866 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800f85a: 6878 ldr r0, [r7, #4] 800f85c: f000 fa9c bl 800fd98 HAL_TIM_PWM_PulseFinishedCallback(htim); 800f860: 6878 ldr r0, [r7, #4] 800f862: f000 faad bl 800fdc0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800f866: 687b ldr r3, [r7, #4] 800f868: 2200 movs r2, #0 800f86a: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 800f86c: 68bb ldr r3, [r7, #8] 800f86e: f003 0310 and.w r3, r3, #16 800f872: 2b00 cmp r3, #0 800f874: d020 beq.n 800f8b8 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 800f876: 68fb ldr r3, [r7, #12] 800f878: f003 0310 and.w r3, r3, #16 800f87c: 2b00 cmp r3, #0 800f87e: d01b beq.n 800f8b8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 800f880: 687b ldr r3, [r7, #4] 800f882: 681b ldr r3, [r3, #0] 800f884: f06f 0210 mvn.w r2, #16 800f888: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800f88a: 687b ldr r3, [r7, #4] 800f88c: 2208 movs r2, #8 800f88e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 800f890: 687b ldr r3, [r7, #4] 800f892: 681b ldr r3, [r3, #0] 800f894: 69db ldr r3, [r3, #28] 800f896: f403 7340 and.w r3, r3, #768 @ 0x300 800f89a: 2b00 cmp r3, #0 800f89c: d003 beq.n 800f8a6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800f89e: 6878 ldr r0, [r7, #4] 800f8a0: f000 fa84 bl 800fdac 800f8a4: e005 b.n 800f8b2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800f8a6: 6878 ldr r0, [r7, #4] 800f8a8: f000 fa76 bl 800fd98 HAL_TIM_PWM_PulseFinishedCallback(htim); 800f8ac: 6878 ldr r0, [r7, #4] 800f8ae: f000 fa87 bl 800fdc0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800f8b2: 687b ldr r3, [r7, #4] 800f8b4: 2200 movs r2, #0 800f8b6: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 800f8b8: 68bb ldr r3, [r7, #8] 800f8ba: f003 0301 and.w r3, r3, #1 800f8be: 2b00 cmp r3, #0 800f8c0: d00c beq.n 800f8dc { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 800f8c2: 68fb ldr r3, [r7, #12] 800f8c4: f003 0301 and.w r3, r3, #1 800f8c8: 2b00 cmp r3, #0 800f8ca: d007 beq.n 800f8dc { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 800f8cc: 687b ldr r3, [r7, #4] 800f8ce: 681b ldr r3, [r3, #0] 800f8d0: f06f 0201 mvn.w r2, #1 800f8d4: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 800f8d6: 6878 ldr r0, [r7, #4] 800f8d8: f7f2 f944 bl 8001b64 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800f8dc: 68bb ldr r3, [r7, #8] 800f8de: f003 0380 and.w r3, r3, #128 @ 0x80 800f8e2: 2b00 cmp r3, #0 800f8e4: d104 bne.n 800f8f0 ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) 800f8e6: 68bb ldr r3, [r7, #8] 800f8e8: f403 5300 and.w r3, r3, #8192 @ 0x2000 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800f8ec: 2b00 cmp r3, #0 800f8ee: d00c beq.n 800f90a { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800f8f0: 68fb ldr r3, [r7, #12] 800f8f2: f003 0380 and.w r3, r3, #128 @ 0x80 800f8f6: 2b00 cmp r3, #0 800f8f8: d007 beq.n 800f90a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 800f8fa: 687b ldr r3, [r7, #4] 800f8fc: 681b ldr r3, [r3, #0] 800f8fe: f46f 5202 mvn.w r2, #8320 @ 0x2080 800f902: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 800f904: 6878 ldr r0, [r7, #4] 800f906: f000 ffff bl 8010908 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 800f90a: 68bb ldr r3, [r7, #8] 800f90c: f403 7380 and.w r3, r3, #256 @ 0x100 800f910: 2b00 cmp r3, #0 800f912: d00c beq.n 800f92e { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800f914: 68fb ldr r3, [r7, #12] 800f916: f003 0380 and.w r3, r3, #128 @ 0x80 800f91a: 2b00 cmp r3, #0 800f91c: d007 beq.n 800f92e { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 800f91e: 687b ldr r3, [r7, #4] 800f920: 681b ldr r3, [r3, #0] 800f922: f46f 7280 mvn.w r2, #256 @ 0x100 800f926: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 800f928: 6878 ldr r0, [r7, #4] 800f92a: f000 fff7 bl 801091c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 800f92e: 68bb ldr r3, [r7, #8] 800f930: f003 0340 and.w r3, r3, #64 @ 0x40 800f934: 2b00 cmp r3, #0 800f936: d00c beq.n 800f952 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 800f938: 68fb ldr r3, [r7, #12] 800f93a: f003 0340 and.w r3, r3, #64 @ 0x40 800f93e: 2b00 cmp r3, #0 800f940: d007 beq.n 800f952 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 800f942: 687b ldr r3, [r7, #4] 800f944: 681b ldr r3, [r3, #0] 800f946: f06f 0240 mvn.w r2, #64 @ 0x40 800f94a: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 800f94c: 6878 ldr r0, [r7, #4] 800f94e: f000 fa41 bl 800fdd4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 800f952: 68bb ldr r3, [r7, #8] 800f954: f003 0320 and.w r3, r3, #32 800f958: 2b00 cmp r3, #0 800f95a: d00c beq.n 800f976 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 800f95c: 68fb ldr r3, [r7, #12] 800f95e: f003 0320 and.w r3, r3, #32 800f962: 2b00 cmp r3, #0 800f964: d007 beq.n 800f976 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 800f966: 687b ldr r3, [r7, #4] 800f968: 681b ldr r3, [r3, #0] 800f96a: f06f 0220 mvn.w r2, #32 800f96e: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 800f970: 6878 ldr r0, [r7, #4] 800f972: f000 ffbf bl 80108f4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 800f976: bf00 nop 800f978: 3710 adds r7, #16 800f97a: 46bd mov sp, r7 800f97c: bd80 pop {r7, pc} ... 0800f980 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 800f980: b580 push {r7, lr} 800f982: b086 sub sp, #24 800f984: af00 add r7, sp, #0 800f986: 60f8 str r0, [r7, #12] 800f988: 60b9 str r1, [r7, #8] 800f98a: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800f98c: 2300 movs r3, #0 800f98e: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 800f990: 68fb ldr r3, [r7, #12] 800f992: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800f996: 2b01 cmp r3, #1 800f998: d101 bne.n 800f99e 800f99a: 2302 movs r3, #2 800f99c: e0ff b.n 800fb9e 800f99e: 68fb ldr r3, [r7, #12] 800f9a0: 2201 movs r2, #1 800f9a2: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 800f9a6: 687b ldr r3, [r7, #4] 800f9a8: 2b14 cmp r3, #20 800f9aa: f200 80f0 bhi.w 800fb8e 800f9ae: a201 add r2, pc, #4 @ (adr r2, 800f9b4 ) 800f9b0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800f9b4: 0800fa09 .word 0x0800fa09 800f9b8: 0800fb8f .word 0x0800fb8f 800f9bc: 0800fb8f .word 0x0800fb8f 800f9c0: 0800fb8f .word 0x0800fb8f 800f9c4: 0800fa49 .word 0x0800fa49 800f9c8: 0800fb8f .word 0x0800fb8f 800f9cc: 0800fb8f .word 0x0800fb8f 800f9d0: 0800fb8f .word 0x0800fb8f 800f9d4: 0800fa8b .word 0x0800fa8b 800f9d8: 0800fb8f .word 0x0800fb8f 800f9dc: 0800fb8f .word 0x0800fb8f 800f9e0: 0800fb8f .word 0x0800fb8f 800f9e4: 0800facb .word 0x0800facb 800f9e8: 0800fb8f .word 0x0800fb8f 800f9ec: 0800fb8f .word 0x0800fb8f 800f9f0: 0800fb8f .word 0x0800fb8f 800f9f4: 0800fb0d .word 0x0800fb0d 800f9f8: 0800fb8f .word 0x0800fb8f 800f9fc: 0800fb8f .word 0x0800fb8f 800fa00: 0800fb8f .word 0x0800fb8f 800fa04: 0800fb4d .word 0x0800fb4d { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 800fa08: 68fb ldr r3, [r7, #12] 800fa0a: 681b ldr r3, [r3, #0] 800fa0c: 68b9 ldr r1, [r7, #8] 800fa0e: 4618 mov r0, r3 800fa10: f000 faca bl 800ffa8 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 800fa14: 68fb ldr r3, [r7, #12] 800fa16: 681b ldr r3, [r3, #0] 800fa18: 699a ldr r2, [r3, #24] 800fa1a: 68fb ldr r3, [r7, #12] 800fa1c: 681b ldr r3, [r3, #0] 800fa1e: f042 0208 orr.w r2, r2, #8 800fa22: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 800fa24: 68fb ldr r3, [r7, #12] 800fa26: 681b ldr r3, [r3, #0] 800fa28: 699a ldr r2, [r3, #24] 800fa2a: 68fb ldr r3, [r7, #12] 800fa2c: 681b ldr r3, [r3, #0] 800fa2e: f022 0204 bic.w r2, r2, #4 800fa32: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 800fa34: 68fb ldr r3, [r7, #12] 800fa36: 681b ldr r3, [r3, #0] 800fa38: 6999 ldr r1, [r3, #24] 800fa3a: 68bb ldr r3, [r7, #8] 800fa3c: 691a ldr r2, [r3, #16] 800fa3e: 68fb ldr r3, [r7, #12] 800fa40: 681b ldr r3, [r3, #0] 800fa42: 430a orrs r2, r1 800fa44: 619a str r2, [r3, #24] break; 800fa46: e0a5 b.n 800fb94 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 800fa48: 68fb ldr r3, [r7, #12] 800fa4a: 681b ldr r3, [r3, #0] 800fa4c: 68b9 ldr r1, [r7, #8] 800fa4e: 4618 mov r0, r3 800fa50: f000 fb3a bl 80100c8 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 800fa54: 68fb ldr r3, [r7, #12] 800fa56: 681b ldr r3, [r3, #0] 800fa58: 699a ldr r2, [r3, #24] 800fa5a: 68fb ldr r3, [r7, #12] 800fa5c: 681b ldr r3, [r3, #0] 800fa5e: f442 6200 orr.w r2, r2, #2048 @ 0x800 800fa62: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 800fa64: 68fb ldr r3, [r7, #12] 800fa66: 681b ldr r3, [r3, #0] 800fa68: 699a ldr r2, [r3, #24] 800fa6a: 68fb ldr r3, [r7, #12] 800fa6c: 681b ldr r3, [r3, #0] 800fa6e: f422 6280 bic.w r2, r2, #1024 @ 0x400 800fa72: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 800fa74: 68fb ldr r3, [r7, #12] 800fa76: 681b ldr r3, [r3, #0] 800fa78: 6999 ldr r1, [r3, #24] 800fa7a: 68bb ldr r3, [r7, #8] 800fa7c: 691b ldr r3, [r3, #16] 800fa7e: 021a lsls r2, r3, #8 800fa80: 68fb ldr r3, [r7, #12] 800fa82: 681b ldr r3, [r3, #0] 800fa84: 430a orrs r2, r1 800fa86: 619a str r2, [r3, #24] break; 800fa88: e084 b.n 800fb94 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 800fa8a: 68fb ldr r3, [r7, #12] 800fa8c: 681b ldr r3, [r3, #0] 800fa8e: 68b9 ldr r1, [r7, #8] 800fa90: 4618 mov r0, r3 800fa92: f000 fba3 bl 80101dc /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 800fa96: 68fb ldr r3, [r7, #12] 800fa98: 681b ldr r3, [r3, #0] 800fa9a: 69da ldr r2, [r3, #28] 800fa9c: 68fb ldr r3, [r7, #12] 800fa9e: 681b ldr r3, [r3, #0] 800faa0: f042 0208 orr.w r2, r2, #8 800faa4: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 800faa6: 68fb ldr r3, [r7, #12] 800faa8: 681b ldr r3, [r3, #0] 800faaa: 69da ldr r2, [r3, #28] 800faac: 68fb ldr r3, [r7, #12] 800faae: 681b ldr r3, [r3, #0] 800fab0: f022 0204 bic.w r2, r2, #4 800fab4: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 800fab6: 68fb ldr r3, [r7, #12] 800fab8: 681b ldr r3, [r3, #0] 800faba: 69d9 ldr r1, [r3, #28] 800fabc: 68bb ldr r3, [r7, #8] 800fabe: 691a ldr r2, [r3, #16] 800fac0: 68fb ldr r3, [r7, #12] 800fac2: 681b ldr r3, [r3, #0] 800fac4: 430a orrs r2, r1 800fac6: 61da str r2, [r3, #28] break; 800fac8: e064 b.n 800fb94 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 800faca: 68fb ldr r3, [r7, #12] 800facc: 681b ldr r3, [r3, #0] 800face: 68b9 ldr r1, [r7, #8] 800fad0: 4618 mov r0, r3 800fad2: f000 fc0b bl 80102ec /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 800fad6: 68fb ldr r3, [r7, #12] 800fad8: 681b ldr r3, [r3, #0] 800fada: 69da ldr r2, [r3, #28] 800fadc: 68fb ldr r3, [r7, #12] 800fade: 681b ldr r3, [r3, #0] 800fae0: f442 6200 orr.w r2, r2, #2048 @ 0x800 800fae4: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 800fae6: 68fb ldr r3, [r7, #12] 800fae8: 681b ldr r3, [r3, #0] 800faea: 69da ldr r2, [r3, #28] 800faec: 68fb ldr r3, [r7, #12] 800faee: 681b ldr r3, [r3, #0] 800faf0: f422 6280 bic.w r2, r2, #1024 @ 0x400 800faf4: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 800faf6: 68fb ldr r3, [r7, #12] 800faf8: 681b ldr r3, [r3, #0] 800fafa: 69d9 ldr r1, [r3, #28] 800fafc: 68bb ldr r3, [r7, #8] 800fafe: 691b ldr r3, [r3, #16] 800fb00: 021a lsls r2, r3, #8 800fb02: 68fb ldr r3, [r7, #12] 800fb04: 681b ldr r3, [r3, #0] 800fb06: 430a orrs r2, r1 800fb08: 61da str r2, [r3, #28] break; 800fb0a: e043 b.n 800fb94 { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); 800fb0c: 68fb ldr r3, [r7, #12] 800fb0e: 681b ldr r3, [r3, #0] 800fb10: 68b9 ldr r1, [r7, #8] 800fb12: 4618 mov r0, r3 800fb14: f000 fc54 bl 80103c0 /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 800fb18: 68fb ldr r3, [r7, #12] 800fb1a: 681b ldr r3, [r3, #0] 800fb1c: 6d5a ldr r2, [r3, #84] @ 0x54 800fb1e: 68fb ldr r3, [r7, #12] 800fb20: 681b ldr r3, [r3, #0] 800fb22: f042 0208 orr.w r2, r2, #8 800fb26: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 800fb28: 68fb ldr r3, [r7, #12] 800fb2a: 681b ldr r3, [r3, #0] 800fb2c: 6d5a ldr r2, [r3, #84] @ 0x54 800fb2e: 68fb ldr r3, [r7, #12] 800fb30: 681b ldr r3, [r3, #0] 800fb32: f022 0204 bic.w r2, r2, #4 800fb36: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; 800fb38: 68fb ldr r3, [r7, #12] 800fb3a: 681b ldr r3, [r3, #0] 800fb3c: 6d59 ldr r1, [r3, #84] @ 0x54 800fb3e: 68bb ldr r3, [r7, #8] 800fb40: 691a ldr r2, [r3, #16] 800fb42: 68fb ldr r3, [r7, #12] 800fb44: 681b ldr r3, [r3, #0] 800fb46: 430a orrs r2, r1 800fb48: 655a str r2, [r3, #84] @ 0x54 break; 800fb4a: e023 b.n 800fb94 { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); 800fb4c: 68fb ldr r3, [r7, #12] 800fb4e: 681b ldr r3, [r3, #0] 800fb50: 68b9 ldr r1, [r7, #8] 800fb52: 4618 mov r0, r3 800fb54: f000 fc98 bl 8010488 /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 800fb58: 68fb ldr r3, [r7, #12] 800fb5a: 681b ldr r3, [r3, #0] 800fb5c: 6d5a ldr r2, [r3, #84] @ 0x54 800fb5e: 68fb ldr r3, [r7, #12] 800fb60: 681b ldr r3, [r3, #0] 800fb62: f442 6200 orr.w r2, r2, #2048 @ 0x800 800fb66: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 800fb68: 68fb ldr r3, [r7, #12] 800fb6a: 681b ldr r3, [r3, #0] 800fb6c: 6d5a ldr r2, [r3, #84] @ 0x54 800fb6e: 68fb ldr r3, [r7, #12] 800fb70: 681b ldr r3, [r3, #0] 800fb72: f422 6280 bic.w r2, r2, #1024 @ 0x400 800fb76: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 800fb78: 68fb ldr r3, [r7, #12] 800fb7a: 681b ldr r3, [r3, #0] 800fb7c: 6d59 ldr r1, [r3, #84] @ 0x54 800fb7e: 68bb ldr r3, [r7, #8] 800fb80: 691b ldr r3, [r3, #16] 800fb82: 021a lsls r2, r3, #8 800fb84: 68fb ldr r3, [r7, #12] 800fb86: 681b ldr r3, [r3, #0] 800fb88: 430a orrs r2, r1 800fb8a: 655a str r2, [r3, #84] @ 0x54 break; 800fb8c: e002 b.n 800fb94 } default: status = HAL_ERROR; 800fb8e: 2301 movs r3, #1 800fb90: 75fb strb r3, [r7, #23] break; 800fb92: bf00 nop } __HAL_UNLOCK(htim); 800fb94: 68fb ldr r3, [r7, #12] 800fb96: 2200 movs r2, #0 800fb98: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 800fb9c: 7dfb ldrb r3, [r7, #23] } 800fb9e: 4618 mov r0, r3 800fba0: 3718 adds r7, #24 800fba2: 46bd mov sp, r7 800fba4: bd80 pop {r7, pc} 800fba6: bf00 nop 0800fba8 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 800fba8: b580 push {r7, lr} 800fbaa: b084 sub sp, #16 800fbac: af00 add r7, sp, #0 800fbae: 6078 str r0, [r7, #4] 800fbb0: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800fbb2: 2300 movs r3, #0 800fbb4: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 800fbb6: 687b ldr r3, [r7, #4] 800fbb8: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800fbbc: 2b01 cmp r3, #1 800fbbe: d101 bne.n 800fbc4 800fbc0: 2302 movs r3, #2 800fbc2: e0dc b.n 800fd7e 800fbc4: 687b ldr r3, [r7, #4] 800fbc6: 2201 movs r2, #1 800fbc8: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 800fbcc: 687b ldr r3, [r7, #4] 800fbce: 2202 movs r2, #2 800fbd0: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 800fbd4: 687b ldr r3, [r7, #4] 800fbd6: 681b ldr r3, [r3, #0] 800fbd8: 689b ldr r3, [r3, #8] 800fbda: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 800fbdc: 68ba ldr r2, [r7, #8] 800fbde: 4b6a ldr r3, [pc, #424] @ (800fd88 ) 800fbe0: 4013 ands r3, r2 800fbe2: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 800fbe4: 68bb ldr r3, [r7, #8] 800fbe6: f423 437f bic.w r3, r3, #65280 @ 0xff00 800fbea: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 800fbec: 687b ldr r3, [r7, #4] 800fbee: 681b ldr r3, [r3, #0] 800fbf0: 68ba ldr r2, [r7, #8] 800fbf2: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 800fbf4: 683b ldr r3, [r7, #0] 800fbf6: 681b ldr r3, [r3, #0] 800fbf8: 4a64 ldr r2, [pc, #400] @ (800fd8c ) 800fbfa: 4293 cmp r3, r2 800fbfc: f000 80a9 beq.w 800fd52 800fc00: 4a62 ldr r2, [pc, #392] @ (800fd8c ) 800fc02: 4293 cmp r3, r2 800fc04: f200 80ae bhi.w 800fd64 800fc08: 4a61 ldr r2, [pc, #388] @ (800fd90 ) 800fc0a: 4293 cmp r3, r2 800fc0c: f000 80a1 beq.w 800fd52 800fc10: 4a5f ldr r2, [pc, #380] @ (800fd90 ) 800fc12: 4293 cmp r3, r2 800fc14: f200 80a6 bhi.w 800fd64 800fc18: 4a5e ldr r2, [pc, #376] @ (800fd94 ) 800fc1a: 4293 cmp r3, r2 800fc1c: f000 8099 beq.w 800fd52 800fc20: 4a5c ldr r2, [pc, #368] @ (800fd94 ) 800fc22: 4293 cmp r3, r2 800fc24: f200 809e bhi.w 800fd64 800fc28: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 800fc2c: f000 8091 beq.w 800fd52 800fc30: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 800fc34: f200 8096 bhi.w 800fd64 800fc38: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800fc3c: f000 8089 beq.w 800fd52 800fc40: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800fc44: f200 808e bhi.w 800fd64 800fc48: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800fc4c: d03e beq.n 800fccc 800fc4e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800fc52: f200 8087 bhi.w 800fd64 800fc56: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800fc5a: f000 8086 beq.w 800fd6a 800fc5e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800fc62: d87f bhi.n 800fd64 800fc64: 2b70 cmp r3, #112 @ 0x70 800fc66: d01a beq.n 800fc9e 800fc68: 2b70 cmp r3, #112 @ 0x70 800fc6a: d87b bhi.n 800fd64 800fc6c: 2b60 cmp r3, #96 @ 0x60 800fc6e: d050 beq.n 800fd12 800fc70: 2b60 cmp r3, #96 @ 0x60 800fc72: d877 bhi.n 800fd64 800fc74: 2b50 cmp r3, #80 @ 0x50 800fc76: d03c beq.n 800fcf2 800fc78: 2b50 cmp r3, #80 @ 0x50 800fc7a: d873 bhi.n 800fd64 800fc7c: 2b40 cmp r3, #64 @ 0x40 800fc7e: d058 beq.n 800fd32 800fc80: 2b40 cmp r3, #64 @ 0x40 800fc82: d86f bhi.n 800fd64 800fc84: 2b30 cmp r3, #48 @ 0x30 800fc86: d064 beq.n 800fd52 800fc88: 2b30 cmp r3, #48 @ 0x30 800fc8a: d86b bhi.n 800fd64 800fc8c: 2b20 cmp r3, #32 800fc8e: d060 beq.n 800fd52 800fc90: 2b20 cmp r3, #32 800fc92: d867 bhi.n 800fd64 800fc94: 2b00 cmp r3, #0 800fc96: d05c beq.n 800fd52 800fc98: 2b10 cmp r3, #16 800fc9a: d05a beq.n 800fd52 800fc9c: e062 b.n 800fd64 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 800fc9e: 687b ldr r3, [r7, #4] 800fca0: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 800fca2: 683b ldr r3, [r7, #0] 800fca4: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 800fca6: 683b ldr r3, [r7, #0] 800fca8: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 800fcaa: 683b ldr r3, [r7, #0] 800fcac: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 800fcae: f000 fccf bl 8010650 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 800fcb2: 687b ldr r3, [r7, #4] 800fcb4: 681b ldr r3, [r3, #0] 800fcb6: 689b ldr r3, [r3, #8] 800fcb8: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 800fcba: 68bb ldr r3, [r7, #8] 800fcbc: f043 0377 orr.w r3, r3, #119 @ 0x77 800fcc0: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800fcc2: 687b ldr r3, [r7, #4] 800fcc4: 681b ldr r3, [r3, #0] 800fcc6: 68ba ldr r2, [r7, #8] 800fcc8: 609a str r2, [r3, #8] break; 800fcca: e04f b.n 800fd6c assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 800fccc: 687b ldr r3, [r7, #4] 800fcce: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 800fcd0: 683b ldr r3, [r7, #0] 800fcd2: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 800fcd4: 683b ldr r3, [r7, #0] 800fcd6: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 800fcd8: 683b ldr r3, [r7, #0] 800fcda: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 800fcdc: f000 fcb8 bl 8010650 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 800fce0: 687b ldr r3, [r7, #4] 800fce2: 681b ldr r3, [r3, #0] 800fce4: 689a ldr r2, [r3, #8] 800fce6: 687b ldr r3, [r7, #4] 800fce8: 681b ldr r3, [r3, #0] 800fcea: f442 4280 orr.w r2, r2, #16384 @ 0x4000 800fcee: 609a str r2, [r3, #8] break; 800fcf0: e03c b.n 800fd6c /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 800fcf2: 687b ldr r3, [r7, #4] 800fcf4: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800fcf6: 683b ldr r3, [r7, #0] 800fcf8: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800fcfa: 683b ldr r3, [r7, #0] 800fcfc: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 800fcfe: 461a mov r2, r3 800fd00: f000 fc28 bl 8010554 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 800fd04: 687b ldr r3, [r7, #4] 800fd06: 681b ldr r3, [r3, #0] 800fd08: 2150 movs r1, #80 @ 0x50 800fd0a: 4618 mov r0, r3 800fd0c: f000 fc82 bl 8010614 break; 800fd10: e02c b.n 800fd6c /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 800fd12: 687b ldr r3, [r7, #4] 800fd14: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800fd16: 683b ldr r3, [r7, #0] 800fd18: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800fd1a: 683b ldr r3, [r7, #0] 800fd1c: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 800fd1e: 461a mov r2, r3 800fd20: f000 fc47 bl 80105b2 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 800fd24: 687b ldr r3, [r7, #4] 800fd26: 681b ldr r3, [r3, #0] 800fd28: 2160 movs r1, #96 @ 0x60 800fd2a: 4618 mov r0, r3 800fd2c: f000 fc72 bl 8010614 break; 800fd30: e01c b.n 800fd6c /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 800fd32: 687b ldr r3, [r7, #4] 800fd34: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800fd36: 683b ldr r3, [r7, #0] 800fd38: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800fd3a: 683b ldr r3, [r7, #0] 800fd3c: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 800fd3e: 461a mov r2, r3 800fd40: f000 fc08 bl 8010554 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 800fd44: 687b ldr r3, [r7, #4] 800fd46: 681b ldr r3, [r3, #0] 800fd48: 2140 movs r1, #64 @ 0x40 800fd4a: 4618 mov r0, r3 800fd4c: f000 fc62 bl 8010614 break; 800fd50: e00c b.n 800fd6c case TIM_CLOCKSOURCE_ITR8: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 800fd52: 687b ldr r3, [r7, #4] 800fd54: 681a ldr r2, [r3, #0] 800fd56: 683b ldr r3, [r7, #0] 800fd58: 681b ldr r3, [r3, #0] 800fd5a: 4619 mov r1, r3 800fd5c: 4610 mov r0, r2 800fd5e: f000 fc59 bl 8010614 break; 800fd62: e003 b.n 800fd6c } default: status = HAL_ERROR; 800fd64: 2301 movs r3, #1 800fd66: 73fb strb r3, [r7, #15] break; 800fd68: e000 b.n 800fd6c break; 800fd6a: bf00 nop } htim->State = HAL_TIM_STATE_READY; 800fd6c: 687b ldr r3, [r7, #4] 800fd6e: 2201 movs r2, #1 800fd70: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 800fd74: 687b ldr r3, [r7, #4] 800fd76: 2200 movs r2, #0 800fd78: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 800fd7c: 7bfb ldrb r3, [r7, #15] } 800fd7e: 4618 mov r0, r3 800fd80: 3710 adds r7, #16 800fd82: 46bd mov sp, r7 800fd84: bd80 pop {r7, pc} 800fd86: bf00 nop 800fd88: ffceff88 .word 0xffceff88 800fd8c: 00100040 .word 0x00100040 800fd90: 00100030 .word 0x00100030 800fd94: 00100020 .word 0x00100020 0800fd98 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 800fd98: b480 push {r7} 800fd9a: b083 sub sp, #12 800fd9c: af00 add r7, sp, #0 800fd9e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 800fda0: bf00 nop 800fda2: 370c adds r7, #12 800fda4: 46bd mov sp, r7 800fda6: f85d 7b04 ldr.w r7, [sp], #4 800fdaa: 4770 bx lr 0800fdac : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 800fdac: b480 push {r7} 800fdae: b083 sub sp, #12 800fdb0: af00 add r7, sp, #0 800fdb2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 800fdb4: bf00 nop 800fdb6: 370c adds r7, #12 800fdb8: 46bd mov sp, r7 800fdba: f85d 7b04 ldr.w r7, [sp], #4 800fdbe: 4770 bx lr 0800fdc0 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 800fdc0: b480 push {r7} 800fdc2: b083 sub sp, #12 800fdc4: af00 add r7, sp, #0 800fdc6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 800fdc8: bf00 nop 800fdca: 370c adds r7, #12 800fdcc: 46bd mov sp, r7 800fdce: f85d 7b04 ldr.w r7, [sp], #4 800fdd2: 4770 bx lr 0800fdd4 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 800fdd4: b480 push {r7} 800fdd6: b083 sub sp, #12 800fdd8: af00 add r7, sp, #0 800fdda: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 800fddc: bf00 nop 800fdde: 370c adds r7, #12 800fde0: 46bd mov sp, r7 800fde2: f85d 7b04 ldr.w r7, [sp], #4 800fde6: 4770 bx lr 0800fde8 : * @arg TIM_CHANNEL_5: TIM Channel 5 * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) { 800fde8: b480 push {r7} 800fdea: b085 sub sp, #20 800fdec: af00 add r7, sp, #0 800fdee: 6078 str r0, [r7, #4] 800fdf0: 6039 str r1, [r7, #0] HAL_TIM_ChannelStateTypeDef channel_state; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); 800fdf2: 683b ldr r3, [r7, #0] 800fdf4: 2b00 cmp r3, #0 800fdf6: d104 bne.n 800fe02 800fdf8: 687b ldr r3, [r7, #4] 800fdfa: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800fdfe: b2db uxtb r3, r3 800fe00: e023 b.n 800fe4a 800fe02: 683b ldr r3, [r7, #0] 800fe04: 2b04 cmp r3, #4 800fe06: d104 bne.n 800fe12 800fe08: 687b ldr r3, [r7, #4] 800fe0a: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800fe0e: b2db uxtb r3, r3 800fe10: e01b b.n 800fe4a 800fe12: 683b ldr r3, [r7, #0] 800fe14: 2b08 cmp r3, #8 800fe16: d104 bne.n 800fe22 800fe18: 687b ldr r3, [r7, #4] 800fe1a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800fe1e: b2db uxtb r3, r3 800fe20: e013 b.n 800fe4a 800fe22: 683b ldr r3, [r7, #0] 800fe24: 2b0c cmp r3, #12 800fe26: d104 bne.n 800fe32 800fe28: 687b ldr r3, [r7, #4] 800fe2a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800fe2e: b2db uxtb r3, r3 800fe30: e00b b.n 800fe4a 800fe32: 683b ldr r3, [r7, #0] 800fe34: 2b10 cmp r3, #16 800fe36: d104 bne.n 800fe42 800fe38: 687b ldr r3, [r7, #4] 800fe3a: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800fe3e: b2db uxtb r3, r3 800fe40: e003 b.n 800fe4a 800fe42: 687b ldr r3, [r7, #4] 800fe44: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800fe48: b2db uxtb r3, r3 800fe4a: 73fb strb r3, [r7, #15] return channel_state; 800fe4c: 7bfb ldrb r3, [r7, #15] } 800fe4e: 4618 mov r0, r3 800fe50: 3714 adds r7, #20 800fe52: 46bd mov sp, r7 800fe54: f85d 7b04 ldr.w r7, [sp], #4 800fe58: 4770 bx lr ... 0800fe5c : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 800fe5c: b480 push {r7} 800fe5e: b085 sub sp, #20 800fe60: af00 add r7, sp, #0 800fe62: 6078 str r0, [r7, #4] 800fe64: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 800fe66: 687b ldr r3, [r7, #4] 800fe68: 681b ldr r3, [r3, #0] 800fe6a: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 800fe6c: 687b ldr r3, [r7, #4] 800fe6e: 4a46 ldr r2, [pc, #280] @ (800ff88 ) 800fe70: 4293 cmp r3, r2 800fe72: d013 beq.n 800fe9c 800fe74: 687b ldr r3, [r7, #4] 800fe76: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800fe7a: d00f beq.n 800fe9c 800fe7c: 687b ldr r3, [r7, #4] 800fe7e: 4a43 ldr r2, [pc, #268] @ (800ff8c ) 800fe80: 4293 cmp r3, r2 800fe82: d00b beq.n 800fe9c 800fe84: 687b ldr r3, [r7, #4] 800fe86: 4a42 ldr r2, [pc, #264] @ (800ff90 ) 800fe88: 4293 cmp r3, r2 800fe8a: d007 beq.n 800fe9c 800fe8c: 687b ldr r3, [r7, #4] 800fe8e: 4a41 ldr r2, [pc, #260] @ (800ff94 ) 800fe90: 4293 cmp r3, r2 800fe92: d003 beq.n 800fe9c 800fe94: 687b ldr r3, [r7, #4] 800fe96: 4a40 ldr r2, [pc, #256] @ (800ff98 ) 800fe98: 4293 cmp r3, r2 800fe9a: d108 bne.n 800feae { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 800fe9c: 68fb ldr r3, [r7, #12] 800fe9e: f023 0370 bic.w r3, r3, #112 @ 0x70 800fea2: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 800fea4: 683b ldr r3, [r7, #0] 800fea6: 685b ldr r3, [r3, #4] 800fea8: 68fa ldr r2, [r7, #12] 800feaa: 4313 orrs r3, r2 800feac: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800feae: 687b ldr r3, [r7, #4] 800feb0: 4a35 ldr r2, [pc, #212] @ (800ff88 ) 800feb2: 4293 cmp r3, r2 800feb4: d01f beq.n 800fef6 800feb6: 687b ldr r3, [r7, #4] 800feb8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800febc: d01b beq.n 800fef6 800febe: 687b ldr r3, [r7, #4] 800fec0: 4a32 ldr r2, [pc, #200] @ (800ff8c ) 800fec2: 4293 cmp r3, r2 800fec4: d017 beq.n 800fef6 800fec6: 687b ldr r3, [r7, #4] 800fec8: 4a31 ldr r2, [pc, #196] @ (800ff90 ) 800feca: 4293 cmp r3, r2 800fecc: d013 beq.n 800fef6 800fece: 687b ldr r3, [r7, #4] 800fed0: 4a30 ldr r2, [pc, #192] @ (800ff94 ) 800fed2: 4293 cmp r3, r2 800fed4: d00f beq.n 800fef6 800fed6: 687b ldr r3, [r7, #4] 800fed8: 4a2f ldr r2, [pc, #188] @ (800ff98 ) 800feda: 4293 cmp r3, r2 800fedc: d00b beq.n 800fef6 800fede: 687b ldr r3, [r7, #4] 800fee0: 4a2e ldr r2, [pc, #184] @ (800ff9c ) 800fee2: 4293 cmp r3, r2 800fee4: d007 beq.n 800fef6 800fee6: 687b ldr r3, [r7, #4] 800fee8: 4a2d ldr r2, [pc, #180] @ (800ffa0 ) 800feea: 4293 cmp r3, r2 800feec: d003 beq.n 800fef6 800feee: 687b ldr r3, [r7, #4] 800fef0: 4a2c ldr r2, [pc, #176] @ (800ffa4 ) 800fef2: 4293 cmp r3, r2 800fef4: d108 bne.n 800ff08 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800fef6: 68fb ldr r3, [r7, #12] 800fef8: f423 7340 bic.w r3, r3, #768 @ 0x300 800fefc: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 800fefe: 683b ldr r3, [r7, #0] 800ff00: 68db ldr r3, [r3, #12] 800ff02: 68fa ldr r2, [r7, #12] 800ff04: 4313 orrs r3, r2 800ff06: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 800ff08: 68fb ldr r3, [r7, #12] 800ff0a: f023 0280 bic.w r2, r3, #128 @ 0x80 800ff0e: 683b ldr r3, [r7, #0] 800ff10: 695b ldr r3, [r3, #20] 800ff12: 4313 orrs r3, r2 800ff14: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 800ff16: 687b ldr r3, [r7, #4] 800ff18: 68fa ldr r2, [r7, #12] 800ff1a: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 800ff1c: 683b ldr r3, [r7, #0] 800ff1e: 689a ldr r2, [r3, #8] 800ff20: 687b ldr r3, [r7, #4] 800ff22: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 800ff24: 683b ldr r3, [r7, #0] 800ff26: 681a ldr r2, [r3, #0] 800ff28: 687b ldr r3, [r7, #4] 800ff2a: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800ff2c: 687b ldr r3, [r7, #4] 800ff2e: 4a16 ldr r2, [pc, #88] @ (800ff88 ) 800ff30: 4293 cmp r3, r2 800ff32: d00f beq.n 800ff54 800ff34: 687b ldr r3, [r7, #4] 800ff36: 4a18 ldr r2, [pc, #96] @ (800ff98 ) 800ff38: 4293 cmp r3, r2 800ff3a: d00b beq.n 800ff54 800ff3c: 687b ldr r3, [r7, #4] 800ff3e: 4a17 ldr r2, [pc, #92] @ (800ff9c ) 800ff40: 4293 cmp r3, r2 800ff42: d007 beq.n 800ff54 800ff44: 687b ldr r3, [r7, #4] 800ff46: 4a16 ldr r2, [pc, #88] @ (800ffa0 ) 800ff48: 4293 cmp r3, r2 800ff4a: d003 beq.n 800ff54 800ff4c: 687b ldr r3, [r7, #4] 800ff4e: 4a15 ldr r2, [pc, #84] @ (800ffa4 ) 800ff50: 4293 cmp r3, r2 800ff52: d103 bne.n 800ff5c { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 800ff54: 683b ldr r3, [r7, #0] 800ff56: 691a ldr r2, [r3, #16] 800ff58: 687b ldr r3, [r7, #4] 800ff5a: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 800ff5c: 687b ldr r3, [r7, #4] 800ff5e: 2201 movs r2, #1 800ff60: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 800ff62: 687b ldr r3, [r7, #4] 800ff64: 691b ldr r3, [r3, #16] 800ff66: f003 0301 and.w r3, r3, #1 800ff6a: 2b01 cmp r3, #1 800ff6c: d105 bne.n 800ff7a { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 800ff6e: 687b ldr r3, [r7, #4] 800ff70: 691b ldr r3, [r3, #16] 800ff72: f023 0201 bic.w r2, r3, #1 800ff76: 687b ldr r3, [r7, #4] 800ff78: 611a str r2, [r3, #16] } } 800ff7a: bf00 nop 800ff7c: 3714 adds r7, #20 800ff7e: 46bd mov sp, r7 800ff80: f85d 7b04 ldr.w r7, [sp], #4 800ff84: 4770 bx lr 800ff86: bf00 nop 800ff88: 40010000 .word 0x40010000 800ff8c: 40000400 .word 0x40000400 800ff90: 40000800 .word 0x40000800 800ff94: 40000c00 .word 0x40000c00 800ff98: 40010400 .word 0x40010400 800ff9c: 40014000 .word 0x40014000 800ffa0: 40014400 .word 0x40014400 800ffa4: 40014800 .word 0x40014800 0800ffa8 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800ffa8: b480 push {r7} 800ffaa: b087 sub sp, #28 800ffac: af00 add r7, sp, #0 800ffae: 6078 str r0, [r7, #4] 800ffb0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800ffb2: 687b ldr r3, [r7, #4] 800ffb4: 6a1b ldr r3, [r3, #32] 800ffb6: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 800ffb8: 687b ldr r3, [r7, #4] 800ffba: 6a1b ldr r3, [r3, #32] 800ffbc: f023 0201 bic.w r2, r3, #1 800ffc0: 687b ldr r3, [r7, #4] 800ffc2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800ffc4: 687b ldr r3, [r7, #4] 800ffc6: 685b ldr r3, [r3, #4] 800ffc8: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 800ffca: 687b ldr r3, [r7, #4] 800ffcc: 699b ldr r3, [r3, #24] 800ffce: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 800ffd0: 68fa ldr r2, [r7, #12] 800ffd2: 4b37 ldr r3, [pc, #220] @ (80100b0 ) 800ffd4: 4013 ands r3, r2 800ffd6: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 800ffd8: 68fb ldr r3, [r7, #12] 800ffda: f023 0303 bic.w r3, r3, #3 800ffde: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800ffe0: 683b ldr r3, [r7, #0] 800ffe2: 681b ldr r3, [r3, #0] 800ffe4: 68fa ldr r2, [r7, #12] 800ffe6: 4313 orrs r3, r2 800ffe8: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 800ffea: 697b ldr r3, [r7, #20] 800ffec: f023 0302 bic.w r3, r3, #2 800fff0: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 800fff2: 683b ldr r3, [r7, #0] 800fff4: 689b ldr r3, [r3, #8] 800fff6: 697a ldr r2, [r7, #20] 800fff8: 4313 orrs r3, r2 800fffa: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 800fffc: 687b ldr r3, [r7, #4] 800fffe: 4a2d ldr r2, [pc, #180] @ (80100b4 ) 8010000: 4293 cmp r3, r2 8010002: d00f beq.n 8010024 8010004: 687b ldr r3, [r7, #4] 8010006: 4a2c ldr r2, [pc, #176] @ (80100b8 ) 8010008: 4293 cmp r3, r2 801000a: d00b beq.n 8010024 801000c: 687b ldr r3, [r7, #4] 801000e: 4a2b ldr r2, [pc, #172] @ (80100bc ) 8010010: 4293 cmp r3, r2 8010012: d007 beq.n 8010024 8010014: 687b ldr r3, [r7, #4] 8010016: 4a2a ldr r2, [pc, #168] @ (80100c0 ) 8010018: 4293 cmp r3, r2 801001a: d003 beq.n 8010024 801001c: 687b ldr r3, [r7, #4] 801001e: 4a29 ldr r2, [pc, #164] @ (80100c4 ) 8010020: 4293 cmp r3, r2 8010022: d10c bne.n 801003e { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8010024: 697b ldr r3, [r7, #20] 8010026: f023 0308 bic.w r3, r3, #8 801002a: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 801002c: 683b ldr r3, [r7, #0] 801002e: 68db ldr r3, [r3, #12] 8010030: 697a ldr r2, [r7, #20] 8010032: 4313 orrs r3, r2 8010034: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 8010036: 697b ldr r3, [r7, #20] 8010038: f023 0304 bic.w r3, r3, #4 801003c: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 801003e: 687b ldr r3, [r7, #4] 8010040: 4a1c ldr r2, [pc, #112] @ (80100b4 ) 8010042: 4293 cmp r3, r2 8010044: d00f beq.n 8010066 8010046: 687b ldr r3, [r7, #4] 8010048: 4a1b ldr r2, [pc, #108] @ (80100b8 ) 801004a: 4293 cmp r3, r2 801004c: d00b beq.n 8010066 801004e: 687b ldr r3, [r7, #4] 8010050: 4a1a ldr r2, [pc, #104] @ (80100bc ) 8010052: 4293 cmp r3, r2 8010054: d007 beq.n 8010066 8010056: 687b ldr r3, [r7, #4] 8010058: 4a19 ldr r2, [pc, #100] @ (80100c0 ) 801005a: 4293 cmp r3, r2 801005c: d003 beq.n 8010066 801005e: 687b ldr r3, [r7, #4] 8010060: 4a18 ldr r2, [pc, #96] @ (80100c4 ) 8010062: 4293 cmp r3, r2 8010064: d111 bne.n 801008a /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 8010066: 693b ldr r3, [r7, #16] 8010068: f423 7380 bic.w r3, r3, #256 @ 0x100 801006c: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 801006e: 693b ldr r3, [r7, #16] 8010070: f423 7300 bic.w r3, r3, #512 @ 0x200 8010074: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8010076: 683b ldr r3, [r7, #0] 8010078: 695b ldr r3, [r3, #20] 801007a: 693a ldr r2, [r7, #16] 801007c: 4313 orrs r3, r2 801007e: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8010080: 683b ldr r3, [r7, #0] 8010082: 699b ldr r3, [r3, #24] 8010084: 693a ldr r2, [r7, #16] 8010086: 4313 orrs r3, r2 8010088: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 801008a: 687b ldr r3, [r7, #4] 801008c: 693a ldr r2, [r7, #16] 801008e: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8010090: 687b ldr r3, [r7, #4] 8010092: 68fa ldr r2, [r7, #12] 8010094: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 8010096: 683b ldr r3, [r7, #0] 8010098: 685a ldr r2, [r3, #4] 801009a: 687b ldr r3, [r7, #4] 801009c: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 801009e: 687b ldr r3, [r7, #4] 80100a0: 697a ldr r2, [r7, #20] 80100a2: 621a str r2, [r3, #32] } 80100a4: bf00 nop 80100a6: 371c adds r7, #28 80100a8: 46bd mov sp, r7 80100aa: f85d 7b04 ldr.w r7, [sp], #4 80100ae: 4770 bx lr 80100b0: fffeff8f .word 0xfffeff8f 80100b4: 40010000 .word 0x40010000 80100b8: 40010400 .word 0x40010400 80100bc: 40014000 .word 0x40014000 80100c0: 40014400 .word 0x40014400 80100c4: 40014800 .word 0x40014800 080100c8 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80100c8: b480 push {r7} 80100ca: b087 sub sp, #28 80100cc: af00 add r7, sp, #0 80100ce: 6078 str r0, [r7, #4] 80100d0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80100d2: 687b ldr r3, [r7, #4] 80100d4: 6a1b ldr r3, [r3, #32] 80100d6: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 80100d8: 687b ldr r3, [r7, #4] 80100da: 6a1b ldr r3, [r3, #32] 80100dc: f023 0210 bic.w r2, r3, #16 80100e0: 687b ldr r3, [r7, #4] 80100e2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80100e4: 687b ldr r3, [r7, #4] 80100e6: 685b ldr r3, [r3, #4] 80100e8: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80100ea: 687b ldr r3, [r7, #4] 80100ec: 699b ldr r3, [r3, #24] 80100ee: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 80100f0: 68fa ldr r2, [r7, #12] 80100f2: 4b34 ldr r3, [pc, #208] @ (80101c4 ) 80100f4: 4013 ands r3, r2 80100f6: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 80100f8: 68fb ldr r3, [r7, #12] 80100fa: f423 7340 bic.w r3, r3, #768 @ 0x300 80100fe: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8010100: 683b ldr r3, [r7, #0] 8010102: 681b ldr r3, [r3, #0] 8010104: 021b lsls r3, r3, #8 8010106: 68fa ldr r2, [r7, #12] 8010108: 4313 orrs r3, r2 801010a: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 801010c: 697b ldr r3, [r7, #20] 801010e: f023 0320 bic.w r3, r3, #32 8010112: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 8010114: 683b ldr r3, [r7, #0] 8010116: 689b ldr r3, [r3, #8] 8010118: 011b lsls r3, r3, #4 801011a: 697a ldr r2, [r7, #20] 801011c: 4313 orrs r3, r2 801011e: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 8010120: 687b ldr r3, [r7, #4] 8010122: 4a29 ldr r2, [pc, #164] @ (80101c8 ) 8010124: 4293 cmp r3, r2 8010126: d003 beq.n 8010130 8010128: 687b ldr r3, [r7, #4] 801012a: 4a28 ldr r2, [pc, #160] @ (80101cc ) 801012c: 4293 cmp r3, r2 801012e: d10d bne.n 801014c { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 8010130: 697b ldr r3, [r7, #20] 8010132: f023 0380 bic.w r3, r3, #128 @ 0x80 8010136: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8010138: 683b ldr r3, [r7, #0] 801013a: 68db ldr r3, [r3, #12] 801013c: 011b lsls r3, r3, #4 801013e: 697a ldr r2, [r7, #20] 8010140: 4313 orrs r3, r2 8010142: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8010144: 697b ldr r3, [r7, #20] 8010146: f023 0340 bic.w r3, r3, #64 @ 0x40 801014a: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 801014c: 687b ldr r3, [r7, #4] 801014e: 4a1e ldr r2, [pc, #120] @ (80101c8 ) 8010150: 4293 cmp r3, r2 8010152: d00f beq.n 8010174 8010154: 687b ldr r3, [r7, #4] 8010156: 4a1d ldr r2, [pc, #116] @ (80101cc ) 8010158: 4293 cmp r3, r2 801015a: d00b beq.n 8010174 801015c: 687b ldr r3, [r7, #4] 801015e: 4a1c ldr r2, [pc, #112] @ (80101d0 ) 8010160: 4293 cmp r3, r2 8010162: d007 beq.n 8010174 8010164: 687b ldr r3, [r7, #4] 8010166: 4a1b ldr r2, [pc, #108] @ (80101d4 ) 8010168: 4293 cmp r3, r2 801016a: d003 beq.n 8010174 801016c: 687b ldr r3, [r7, #4] 801016e: 4a1a ldr r2, [pc, #104] @ (80101d8 ) 8010170: 4293 cmp r3, r2 8010172: d113 bne.n 801019c /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8010174: 693b ldr r3, [r7, #16] 8010176: f423 6380 bic.w r3, r3, #1024 @ 0x400 801017a: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 801017c: 693b ldr r3, [r7, #16] 801017e: f423 6300 bic.w r3, r3, #2048 @ 0x800 8010182: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8010184: 683b ldr r3, [r7, #0] 8010186: 695b ldr r3, [r3, #20] 8010188: 009b lsls r3, r3, #2 801018a: 693a ldr r2, [r7, #16] 801018c: 4313 orrs r3, r2 801018e: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8010190: 683b ldr r3, [r7, #0] 8010192: 699b ldr r3, [r3, #24] 8010194: 009b lsls r3, r3, #2 8010196: 693a ldr r2, [r7, #16] 8010198: 4313 orrs r3, r2 801019a: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 801019c: 687b ldr r3, [r7, #4] 801019e: 693a ldr r2, [r7, #16] 80101a0: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80101a2: 687b ldr r3, [r7, #4] 80101a4: 68fa ldr r2, [r7, #12] 80101a6: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 80101a8: 683b ldr r3, [r7, #0] 80101aa: 685a ldr r2, [r3, #4] 80101ac: 687b ldr r3, [r7, #4] 80101ae: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80101b0: 687b ldr r3, [r7, #4] 80101b2: 697a ldr r2, [r7, #20] 80101b4: 621a str r2, [r3, #32] } 80101b6: bf00 nop 80101b8: 371c adds r7, #28 80101ba: 46bd mov sp, r7 80101bc: f85d 7b04 ldr.w r7, [sp], #4 80101c0: 4770 bx lr 80101c2: bf00 nop 80101c4: feff8fff .word 0xfeff8fff 80101c8: 40010000 .word 0x40010000 80101cc: 40010400 .word 0x40010400 80101d0: 40014000 .word 0x40014000 80101d4: 40014400 .word 0x40014400 80101d8: 40014800 .word 0x40014800 080101dc : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80101dc: b480 push {r7} 80101de: b087 sub sp, #28 80101e0: af00 add r7, sp, #0 80101e2: 6078 str r0, [r7, #4] 80101e4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80101e6: 687b ldr r3, [r7, #4] 80101e8: 6a1b ldr r3, [r3, #32] 80101ea: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 80101ec: 687b ldr r3, [r7, #4] 80101ee: 6a1b ldr r3, [r3, #32] 80101f0: f423 7280 bic.w r2, r3, #256 @ 0x100 80101f4: 687b ldr r3, [r7, #4] 80101f6: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80101f8: 687b ldr r3, [r7, #4] 80101fa: 685b ldr r3, [r3, #4] 80101fc: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 80101fe: 687b ldr r3, [r7, #4] 8010200: 69db ldr r3, [r3, #28] 8010202: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8010204: 68fa ldr r2, [r7, #12] 8010206: 4b33 ldr r3, [pc, #204] @ (80102d4 ) 8010208: 4013 ands r3, r2 801020a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 801020c: 68fb ldr r3, [r7, #12] 801020e: f023 0303 bic.w r3, r3, #3 8010212: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8010214: 683b ldr r3, [r7, #0] 8010216: 681b ldr r3, [r3, #0] 8010218: 68fa ldr r2, [r7, #12] 801021a: 4313 orrs r3, r2 801021c: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 801021e: 697b ldr r3, [r7, #20] 8010220: f423 7300 bic.w r3, r3, #512 @ 0x200 8010224: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 8010226: 683b ldr r3, [r7, #0] 8010228: 689b ldr r3, [r3, #8] 801022a: 021b lsls r3, r3, #8 801022c: 697a ldr r2, [r7, #20] 801022e: 4313 orrs r3, r2 8010230: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8010232: 687b ldr r3, [r7, #4] 8010234: 4a28 ldr r2, [pc, #160] @ (80102d8 ) 8010236: 4293 cmp r3, r2 8010238: d003 beq.n 8010242 801023a: 687b ldr r3, [r7, #4] 801023c: 4a27 ldr r2, [pc, #156] @ (80102dc ) 801023e: 4293 cmp r3, r2 8010240: d10d bne.n 801025e { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8010242: 697b ldr r3, [r7, #20] 8010244: f423 6300 bic.w r3, r3, #2048 @ 0x800 8010248: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 801024a: 683b ldr r3, [r7, #0] 801024c: 68db ldr r3, [r3, #12] 801024e: 021b lsls r3, r3, #8 8010250: 697a ldr r2, [r7, #20] 8010252: 4313 orrs r3, r2 8010254: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8010256: 697b ldr r3, [r7, #20] 8010258: f423 6380 bic.w r3, r3, #1024 @ 0x400 801025c: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 801025e: 687b ldr r3, [r7, #4] 8010260: 4a1d ldr r2, [pc, #116] @ (80102d8 ) 8010262: 4293 cmp r3, r2 8010264: d00f beq.n 8010286 8010266: 687b ldr r3, [r7, #4] 8010268: 4a1c ldr r2, [pc, #112] @ (80102dc ) 801026a: 4293 cmp r3, r2 801026c: d00b beq.n 8010286 801026e: 687b ldr r3, [r7, #4] 8010270: 4a1b ldr r2, [pc, #108] @ (80102e0 ) 8010272: 4293 cmp r3, r2 8010274: d007 beq.n 8010286 8010276: 687b ldr r3, [r7, #4] 8010278: 4a1a ldr r2, [pc, #104] @ (80102e4 ) 801027a: 4293 cmp r3, r2 801027c: d003 beq.n 8010286 801027e: 687b ldr r3, [r7, #4] 8010280: 4a19 ldr r2, [pc, #100] @ (80102e8 ) 8010282: 4293 cmp r3, r2 8010284: d113 bne.n 80102ae /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8010286: 693b ldr r3, [r7, #16] 8010288: f423 5380 bic.w r3, r3, #4096 @ 0x1000 801028c: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 801028e: 693b ldr r3, [r7, #16] 8010290: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8010294: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8010296: 683b ldr r3, [r7, #0] 8010298: 695b ldr r3, [r3, #20] 801029a: 011b lsls r3, r3, #4 801029c: 693a ldr r2, [r7, #16] 801029e: 4313 orrs r3, r2 80102a0: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 80102a2: 683b ldr r3, [r7, #0] 80102a4: 699b ldr r3, [r3, #24] 80102a6: 011b lsls r3, r3, #4 80102a8: 693a ldr r2, [r7, #16] 80102aa: 4313 orrs r3, r2 80102ac: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80102ae: 687b ldr r3, [r7, #4] 80102b0: 693a ldr r2, [r7, #16] 80102b2: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 80102b4: 687b ldr r3, [r7, #4] 80102b6: 68fa ldr r2, [r7, #12] 80102b8: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 80102ba: 683b ldr r3, [r7, #0] 80102bc: 685a ldr r2, [r3, #4] 80102be: 687b ldr r3, [r7, #4] 80102c0: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80102c2: 687b ldr r3, [r7, #4] 80102c4: 697a ldr r2, [r7, #20] 80102c6: 621a str r2, [r3, #32] } 80102c8: bf00 nop 80102ca: 371c adds r7, #28 80102cc: 46bd mov sp, r7 80102ce: f85d 7b04 ldr.w r7, [sp], #4 80102d2: 4770 bx lr 80102d4: fffeff8f .word 0xfffeff8f 80102d8: 40010000 .word 0x40010000 80102dc: 40010400 .word 0x40010400 80102e0: 40014000 .word 0x40014000 80102e4: 40014400 .word 0x40014400 80102e8: 40014800 .word 0x40014800 080102ec : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80102ec: b480 push {r7} 80102ee: b087 sub sp, #28 80102f0: af00 add r7, sp, #0 80102f2: 6078 str r0, [r7, #4] 80102f4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80102f6: 687b ldr r3, [r7, #4] 80102f8: 6a1b ldr r3, [r3, #32] 80102fa: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 80102fc: 687b ldr r3, [r7, #4] 80102fe: 6a1b ldr r3, [r3, #32] 8010300: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8010304: 687b ldr r3, [r7, #4] 8010306: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010308: 687b ldr r3, [r7, #4] 801030a: 685b ldr r3, [r3, #4] 801030c: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 801030e: 687b ldr r3, [r7, #4] 8010310: 69db ldr r3, [r3, #28] 8010312: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8010314: 68fa ldr r2, [r7, #12] 8010316: 4b24 ldr r3, [pc, #144] @ (80103a8 ) 8010318: 4013 ands r3, r2 801031a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 801031c: 68fb ldr r3, [r7, #12] 801031e: f423 7340 bic.w r3, r3, #768 @ 0x300 8010322: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8010324: 683b ldr r3, [r7, #0] 8010326: 681b ldr r3, [r3, #0] 8010328: 021b lsls r3, r3, #8 801032a: 68fa ldr r2, [r7, #12] 801032c: 4313 orrs r3, r2 801032e: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8010330: 693b ldr r3, [r7, #16] 8010332: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8010336: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8010338: 683b ldr r3, [r7, #0] 801033a: 689b ldr r3, [r3, #8] 801033c: 031b lsls r3, r3, #12 801033e: 693a ldr r2, [r7, #16] 8010340: 4313 orrs r3, r2 8010342: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010344: 687b ldr r3, [r7, #4] 8010346: 4a19 ldr r2, [pc, #100] @ (80103ac ) 8010348: 4293 cmp r3, r2 801034a: d00f beq.n 801036c 801034c: 687b ldr r3, [r7, #4] 801034e: 4a18 ldr r2, [pc, #96] @ (80103b0 ) 8010350: 4293 cmp r3, r2 8010352: d00b beq.n 801036c 8010354: 687b ldr r3, [r7, #4] 8010356: 4a17 ldr r2, [pc, #92] @ (80103b4 ) 8010358: 4293 cmp r3, r2 801035a: d007 beq.n 801036c 801035c: 687b ldr r3, [r7, #4] 801035e: 4a16 ldr r2, [pc, #88] @ (80103b8 ) 8010360: 4293 cmp r3, r2 8010362: d003 beq.n 801036c 8010364: 687b ldr r3, [r7, #4] 8010366: 4a15 ldr r2, [pc, #84] @ (80103bc ) 8010368: 4293 cmp r3, r2 801036a: d109 bne.n 8010380 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 801036c: 697b ldr r3, [r7, #20] 801036e: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8010372: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8010374: 683b ldr r3, [r7, #0] 8010376: 695b ldr r3, [r3, #20] 8010378: 019b lsls r3, r3, #6 801037a: 697a ldr r2, [r7, #20] 801037c: 4313 orrs r3, r2 801037e: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010380: 687b ldr r3, [r7, #4] 8010382: 697a ldr r2, [r7, #20] 8010384: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8010386: 687b ldr r3, [r7, #4] 8010388: 68fa ldr r2, [r7, #12] 801038a: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 801038c: 683b ldr r3, [r7, #0] 801038e: 685a ldr r2, [r3, #4] 8010390: 687b ldr r3, [r7, #4] 8010392: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010394: 687b ldr r3, [r7, #4] 8010396: 693a ldr r2, [r7, #16] 8010398: 621a str r2, [r3, #32] } 801039a: bf00 nop 801039c: 371c adds r7, #28 801039e: 46bd mov sp, r7 80103a0: f85d 7b04 ldr.w r7, [sp], #4 80103a4: 4770 bx lr 80103a6: bf00 nop 80103a8: feff8fff .word 0xfeff8fff 80103ac: 40010000 .word 0x40010000 80103b0: 40010400 .word 0x40010400 80103b4: 40014000 .word 0x40014000 80103b8: 40014400 .word 0x40014400 80103bc: 40014800 .word 0x40014800 080103c0 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80103c0: b480 push {r7} 80103c2: b087 sub sp, #28 80103c4: af00 add r7, sp, #0 80103c6: 6078 str r0, [r7, #4] 80103c8: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80103ca: 687b ldr r3, [r7, #4] 80103cc: 6a1b ldr r3, [r3, #32] 80103ce: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; 80103d0: 687b ldr r3, [r7, #4] 80103d2: 6a1b ldr r3, [r3, #32] 80103d4: f423 3280 bic.w r2, r3, #65536 @ 0x10000 80103d8: 687b ldr r3, [r7, #4] 80103da: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80103dc: 687b ldr r3, [r7, #4] 80103de: 685b ldr r3, [r3, #4] 80103e0: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 80103e2: 687b ldr r3, [r7, #4] 80103e4: 6d5b ldr r3, [r3, #84] @ 0x54 80103e6: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); 80103e8: 68fa ldr r2, [r7, #12] 80103ea: 4b21 ldr r3, [pc, #132] @ (8010470 ) 80103ec: 4013 ands r3, r2 80103ee: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80103f0: 683b ldr r3, [r7, #0] 80103f2: 681b ldr r3, [r3, #0] 80103f4: 68fa ldr r2, [r7, #12] 80103f6: 4313 orrs r3, r2 80103f8: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; 80103fa: 693b ldr r3, [r7, #16] 80103fc: f423 3300 bic.w r3, r3, #131072 @ 0x20000 8010400: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); 8010402: 683b ldr r3, [r7, #0] 8010404: 689b ldr r3, [r3, #8] 8010406: 041b lsls r3, r3, #16 8010408: 693a ldr r2, [r7, #16] 801040a: 4313 orrs r3, r2 801040c: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 801040e: 687b ldr r3, [r7, #4] 8010410: 4a18 ldr r2, [pc, #96] @ (8010474 ) 8010412: 4293 cmp r3, r2 8010414: d00f beq.n 8010436 8010416: 687b ldr r3, [r7, #4] 8010418: 4a17 ldr r2, [pc, #92] @ (8010478 ) 801041a: 4293 cmp r3, r2 801041c: d00b beq.n 8010436 801041e: 687b ldr r3, [r7, #4] 8010420: 4a16 ldr r2, [pc, #88] @ (801047c ) 8010422: 4293 cmp r3, r2 8010424: d007 beq.n 8010436 8010426: 687b ldr r3, [r7, #4] 8010428: 4a15 ldr r2, [pc, #84] @ (8010480 ) 801042a: 4293 cmp r3, r2 801042c: d003 beq.n 8010436 801042e: 687b ldr r3, [r7, #4] 8010430: 4a14 ldr r2, [pc, #80] @ (8010484 ) 8010432: 4293 cmp r3, r2 8010434: d109 bne.n 801044a { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; 8010436: 697b ldr r3, [r7, #20] 8010438: f423 3380 bic.w r3, r3, #65536 @ 0x10000 801043c: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); 801043e: 683b ldr r3, [r7, #0] 8010440: 695b ldr r3, [r3, #20] 8010442: 021b lsls r3, r3, #8 8010444: 697a ldr r2, [r7, #20] 8010446: 4313 orrs r3, r2 8010448: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 801044a: 687b ldr r3, [r7, #4] 801044c: 697a ldr r2, [r7, #20] 801044e: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 8010450: 687b ldr r3, [r7, #4] 8010452: 68fa ldr r2, [r7, #12] 8010454: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; 8010456: 683b ldr r3, [r7, #0] 8010458: 685a ldr r2, [r3, #4] 801045a: 687b ldr r3, [r7, #4] 801045c: 659a str r2, [r3, #88] @ 0x58 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 801045e: 687b ldr r3, [r7, #4] 8010460: 693a ldr r2, [r7, #16] 8010462: 621a str r2, [r3, #32] } 8010464: bf00 nop 8010466: 371c adds r7, #28 8010468: 46bd mov sp, r7 801046a: f85d 7b04 ldr.w r7, [sp], #4 801046e: 4770 bx lr 8010470: fffeff8f .word 0xfffeff8f 8010474: 40010000 .word 0x40010000 8010478: 40010400 .word 0x40010400 801047c: 40014000 .word 0x40014000 8010480: 40014400 .word 0x40014400 8010484: 40014800 .word 0x40014800 08010488 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010488: b480 push {r7} 801048a: b087 sub sp, #28 801048c: af00 add r7, sp, #0 801048e: 6078 str r0, [r7, #4] 8010490: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010492: 687b ldr r3, [r7, #4] 8010494: 6a1b ldr r3, [r3, #32] 8010496: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; 8010498: 687b ldr r3, [r7, #4] 801049a: 6a1b ldr r3, [r3, #32] 801049c: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 80104a0: 687b ldr r3, [r7, #4] 80104a2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80104a4: 687b ldr r3, [r7, #4] 80104a6: 685b ldr r3, [r3, #4] 80104a8: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 80104aa: 687b ldr r3, [r7, #4] 80104ac: 6d5b ldr r3, [r3, #84] @ 0x54 80104ae: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); 80104b0: 68fa ldr r2, [r7, #12] 80104b2: 4b22 ldr r3, [pc, #136] @ (801053c ) 80104b4: 4013 ands r3, r2 80104b6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80104b8: 683b ldr r3, [r7, #0] 80104ba: 681b ldr r3, [r3, #0] 80104bc: 021b lsls r3, r3, #8 80104be: 68fa ldr r2, [r7, #12] 80104c0: 4313 orrs r3, r2 80104c2: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; 80104c4: 693b ldr r3, [r7, #16] 80104c6: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 80104ca: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); 80104cc: 683b ldr r3, [r7, #0] 80104ce: 689b ldr r3, [r3, #8] 80104d0: 051b lsls r3, r3, #20 80104d2: 693a ldr r2, [r7, #16] 80104d4: 4313 orrs r3, r2 80104d6: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 80104d8: 687b ldr r3, [r7, #4] 80104da: 4a19 ldr r2, [pc, #100] @ (8010540 ) 80104dc: 4293 cmp r3, r2 80104de: d00f beq.n 8010500 80104e0: 687b ldr r3, [r7, #4] 80104e2: 4a18 ldr r2, [pc, #96] @ (8010544 ) 80104e4: 4293 cmp r3, r2 80104e6: d00b beq.n 8010500 80104e8: 687b ldr r3, [r7, #4] 80104ea: 4a17 ldr r2, [pc, #92] @ (8010548 ) 80104ec: 4293 cmp r3, r2 80104ee: d007 beq.n 8010500 80104f0: 687b ldr r3, [r7, #4] 80104f2: 4a16 ldr r2, [pc, #88] @ (801054c ) 80104f4: 4293 cmp r3, r2 80104f6: d003 beq.n 8010500 80104f8: 687b ldr r3, [r7, #4] 80104fa: 4a15 ldr r2, [pc, #84] @ (8010550 ) 80104fc: 4293 cmp r3, r2 80104fe: d109 bne.n 8010514 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; 8010500: 697b ldr r3, [r7, #20] 8010502: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010506: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); 8010508: 683b ldr r3, [r7, #0] 801050a: 695b ldr r3, [r3, #20] 801050c: 029b lsls r3, r3, #10 801050e: 697a ldr r2, [r7, #20] 8010510: 4313 orrs r3, r2 8010512: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010514: 687b ldr r3, [r7, #4] 8010516: 697a ldr r2, [r7, #20] 8010518: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 801051a: 687b ldr r3, [r7, #4] 801051c: 68fa ldr r2, [r7, #12] 801051e: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; 8010520: 683b ldr r3, [r7, #0] 8010522: 685a ldr r2, [r3, #4] 8010524: 687b ldr r3, [r7, #4] 8010526: 65da str r2, [r3, #92] @ 0x5c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010528: 687b ldr r3, [r7, #4] 801052a: 693a ldr r2, [r7, #16] 801052c: 621a str r2, [r3, #32] } 801052e: bf00 nop 8010530: 371c adds r7, #28 8010532: 46bd mov sp, r7 8010534: f85d 7b04 ldr.w r7, [sp], #4 8010538: 4770 bx lr 801053a: bf00 nop 801053c: feff8fff .word 0xfeff8fff 8010540: 40010000 .word 0x40010000 8010544: 40010400 .word 0x40010400 8010548: 40014000 .word 0x40014000 801054c: 40014400 .word 0x40014400 8010550: 40014800 .word 0x40014800 08010554 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8010554: b480 push {r7} 8010556: b087 sub sp, #28 8010558: af00 add r7, sp, #0 801055a: 60f8 str r0, [r7, #12] 801055c: 60b9 str r1, [r7, #8] 801055e: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8010560: 68fb ldr r3, [r7, #12] 8010562: 6a1b ldr r3, [r3, #32] 8010564: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8010566: 68fb ldr r3, [r7, #12] 8010568: 6a1b ldr r3, [r3, #32] 801056a: f023 0201 bic.w r2, r3, #1 801056e: 68fb ldr r3, [r7, #12] 8010570: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010572: 68fb ldr r3, [r7, #12] 8010574: 699b ldr r3, [r3, #24] 8010576: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8010578: 693b ldr r3, [r7, #16] 801057a: f023 03f0 bic.w r3, r3, #240 @ 0xf0 801057e: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8010580: 687b ldr r3, [r7, #4] 8010582: 011b lsls r3, r3, #4 8010584: 693a ldr r2, [r7, #16] 8010586: 4313 orrs r3, r2 8010588: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 801058a: 697b ldr r3, [r7, #20] 801058c: f023 030a bic.w r3, r3, #10 8010590: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8010592: 697a ldr r2, [r7, #20] 8010594: 68bb ldr r3, [r7, #8] 8010596: 4313 orrs r3, r2 8010598: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 801059a: 68fb ldr r3, [r7, #12] 801059c: 693a ldr r2, [r7, #16] 801059e: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 80105a0: 68fb ldr r3, [r7, #12] 80105a2: 697a ldr r2, [r7, #20] 80105a4: 621a str r2, [r3, #32] } 80105a6: bf00 nop 80105a8: 371c adds r7, #28 80105aa: 46bd mov sp, r7 80105ac: f85d 7b04 ldr.w r7, [sp], #4 80105b0: 4770 bx lr 080105b2 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 80105b2: b480 push {r7} 80105b4: b087 sub sp, #28 80105b6: af00 add r7, sp, #0 80105b8: 60f8 str r0, [r7, #12] 80105ba: 60b9 str r1, [r7, #8] 80105bc: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 80105be: 68fb ldr r3, [r7, #12] 80105c0: 6a1b ldr r3, [r3, #32] 80105c2: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 80105c4: 68fb ldr r3, [r7, #12] 80105c6: 6a1b ldr r3, [r3, #32] 80105c8: f023 0210 bic.w r2, r3, #16 80105cc: 68fb ldr r3, [r7, #12] 80105ce: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 80105d0: 68fb ldr r3, [r7, #12] 80105d2: 699b ldr r3, [r3, #24] 80105d4: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 80105d6: 693b ldr r3, [r7, #16] 80105d8: f423 4370 bic.w r3, r3, #61440 @ 0xf000 80105dc: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 80105de: 687b ldr r3, [r7, #4] 80105e0: 031b lsls r3, r3, #12 80105e2: 693a ldr r2, [r7, #16] 80105e4: 4313 orrs r3, r2 80105e6: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 80105e8: 697b ldr r3, [r7, #20] 80105ea: f023 03a0 bic.w r3, r3, #160 @ 0xa0 80105ee: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 80105f0: 68bb ldr r3, [r7, #8] 80105f2: 011b lsls r3, r3, #4 80105f4: 697a ldr r2, [r7, #20] 80105f6: 4313 orrs r3, r2 80105f8: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 80105fa: 68fb ldr r3, [r7, #12] 80105fc: 693a ldr r2, [r7, #16] 80105fe: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8010600: 68fb ldr r3, [r7, #12] 8010602: 697a ldr r2, [r7, #20] 8010604: 621a str r2, [r3, #32] } 8010606: bf00 nop 8010608: 371c adds r7, #28 801060a: 46bd mov sp, r7 801060c: f85d 7b04 ldr.w r7, [sp], #4 8010610: 4770 bx lr ... 08010614 : * (*) Value not defined in all devices. * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8010614: b480 push {r7} 8010616: b085 sub sp, #20 8010618: af00 add r7, sp, #0 801061a: 6078 str r0, [r7, #4] 801061c: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 801061e: 687b ldr r3, [r7, #4] 8010620: 689b ldr r3, [r3, #8] 8010622: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8010624: 68fa ldr r2, [r7, #12] 8010626: 4b09 ldr r3, [pc, #36] @ (801064c ) 8010628: 4013 ands r3, r2 801062a: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 801062c: 683a ldr r2, [r7, #0] 801062e: 68fb ldr r3, [r7, #12] 8010630: 4313 orrs r3, r2 8010632: f043 0307 orr.w r3, r3, #7 8010636: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8010638: 687b ldr r3, [r7, #4] 801063a: 68fa ldr r2, [r7, #12] 801063c: 609a str r2, [r3, #8] } 801063e: bf00 nop 8010640: 3714 adds r7, #20 8010642: 46bd mov sp, r7 8010644: f85d 7b04 ldr.w r7, [sp], #4 8010648: 4770 bx lr 801064a: bf00 nop 801064c: ffcfff8f .word 0xffcfff8f 08010650 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8010650: b480 push {r7} 8010652: b087 sub sp, #28 8010654: af00 add r7, sp, #0 8010656: 60f8 str r0, [r7, #12] 8010658: 60b9 str r1, [r7, #8] 801065a: 607a str r2, [r7, #4] 801065c: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 801065e: 68fb ldr r3, [r7, #12] 8010660: 689b ldr r3, [r3, #8] 8010662: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8010664: 697b ldr r3, [r7, #20] 8010666: f423 437f bic.w r3, r3, #65280 @ 0xff00 801066a: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 801066c: 683b ldr r3, [r7, #0] 801066e: 021a lsls r2, r3, #8 8010670: 687b ldr r3, [r7, #4] 8010672: 431a orrs r2, r3 8010674: 68bb ldr r3, [r7, #8] 8010676: 4313 orrs r3, r2 8010678: 697a ldr r2, [r7, #20] 801067a: 4313 orrs r3, r2 801067c: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 801067e: 68fb ldr r3, [r7, #12] 8010680: 697a ldr r2, [r7, #20] 8010682: 609a str r2, [r3, #8] } 8010684: bf00 nop 8010686: 371c adds r7, #28 8010688: 46bd mov sp, r7 801068a: f85d 7b04 ldr.w r7, [sp], #4 801068e: 4770 bx lr 08010690 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8010690: b480 push {r7} 8010692: b087 sub sp, #28 8010694: af00 add r7, sp, #0 8010696: 60f8 str r0, [r7, #12] 8010698: 60b9 str r1, [r7, #8] 801069a: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 801069c: 68bb ldr r3, [r7, #8] 801069e: f003 031f and.w r3, r3, #31 80106a2: 2201 movs r2, #1 80106a4: fa02 f303 lsl.w r3, r2, r3 80106a8: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 80106aa: 68fb ldr r3, [r7, #12] 80106ac: 6a1a ldr r2, [r3, #32] 80106ae: 697b ldr r3, [r7, #20] 80106b0: 43db mvns r3, r3 80106b2: 401a ands r2, r3 80106b4: 68fb ldr r3, [r7, #12] 80106b6: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 80106b8: 68fb ldr r3, [r7, #12] 80106ba: 6a1a ldr r2, [r3, #32] 80106bc: 68bb ldr r3, [r7, #8] 80106be: f003 031f and.w r3, r3, #31 80106c2: 6879 ldr r1, [r7, #4] 80106c4: fa01 f303 lsl.w r3, r1, r3 80106c8: 431a orrs r2, r3 80106ca: 68fb ldr r3, [r7, #12] 80106cc: 621a str r2, [r3, #32] } 80106ce: bf00 nop 80106d0: 371c adds r7, #28 80106d2: 46bd mov sp, r7 80106d4: f85d 7b04 ldr.w r7, [sp], #4 80106d8: 4770 bx lr ... 080106dc : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 80106dc: b480 push {r7} 80106de: b085 sub sp, #20 80106e0: af00 add r7, sp, #0 80106e2: 6078 str r0, [r7, #4] 80106e4: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 80106e6: 687b ldr r3, [r7, #4] 80106e8: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80106ec: 2b01 cmp r3, #1 80106ee: d101 bne.n 80106f4 80106f0: 2302 movs r3, #2 80106f2: e06d b.n 80107d0 80106f4: 687b ldr r3, [r7, #4] 80106f6: 2201 movs r2, #1 80106f8: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 80106fc: 687b ldr r3, [r7, #4] 80106fe: 2202 movs r2, #2 8010700: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8010704: 687b ldr r3, [r7, #4] 8010706: 681b ldr r3, [r3, #0] 8010708: 685b ldr r3, [r3, #4] 801070a: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 801070c: 687b ldr r3, [r7, #4] 801070e: 681b ldr r3, [r3, #0] 8010710: 689b ldr r3, [r3, #8] 8010712: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 8010714: 687b ldr r3, [r7, #4] 8010716: 681b ldr r3, [r3, #0] 8010718: 4a30 ldr r2, [pc, #192] @ (80107dc ) 801071a: 4293 cmp r3, r2 801071c: d004 beq.n 8010728 801071e: 687b ldr r3, [r7, #4] 8010720: 681b ldr r3, [r3, #0] 8010722: 4a2f ldr r2, [pc, #188] @ (80107e0 ) 8010724: 4293 cmp r3, r2 8010726: d108 bne.n 801073a { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 8010728: 68fb ldr r3, [r7, #12] 801072a: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 801072e: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 8010730: 683b ldr r3, [r7, #0] 8010732: 685b ldr r3, [r3, #4] 8010734: 68fa ldr r2, [r7, #12] 8010736: 4313 orrs r3, r2 8010738: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 801073a: 68fb ldr r3, [r7, #12] 801073c: f023 0370 bic.w r3, r3, #112 @ 0x70 8010740: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8010742: 683b ldr r3, [r7, #0] 8010744: 681b ldr r3, [r3, #0] 8010746: 68fa ldr r2, [r7, #12] 8010748: 4313 orrs r3, r2 801074a: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 801074c: 687b ldr r3, [r7, #4] 801074e: 681b ldr r3, [r3, #0] 8010750: 68fa ldr r2, [r7, #12] 8010752: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8010754: 687b ldr r3, [r7, #4] 8010756: 681b ldr r3, [r3, #0] 8010758: 4a20 ldr r2, [pc, #128] @ (80107dc ) 801075a: 4293 cmp r3, r2 801075c: d022 beq.n 80107a4 801075e: 687b ldr r3, [r7, #4] 8010760: 681b ldr r3, [r3, #0] 8010762: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8010766: d01d beq.n 80107a4 8010768: 687b ldr r3, [r7, #4] 801076a: 681b ldr r3, [r3, #0] 801076c: 4a1d ldr r2, [pc, #116] @ (80107e4 ) 801076e: 4293 cmp r3, r2 8010770: d018 beq.n 80107a4 8010772: 687b ldr r3, [r7, #4] 8010774: 681b ldr r3, [r3, #0] 8010776: 4a1c ldr r2, [pc, #112] @ (80107e8 ) 8010778: 4293 cmp r3, r2 801077a: d013 beq.n 80107a4 801077c: 687b ldr r3, [r7, #4] 801077e: 681b ldr r3, [r3, #0] 8010780: 4a1a ldr r2, [pc, #104] @ (80107ec ) 8010782: 4293 cmp r3, r2 8010784: d00e beq.n 80107a4 8010786: 687b ldr r3, [r7, #4] 8010788: 681b ldr r3, [r3, #0] 801078a: 4a15 ldr r2, [pc, #84] @ (80107e0 ) 801078c: 4293 cmp r3, r2 801078e: d009 beq.n 80107a4 8010790: 687b ldr r3, [r7, #4] 8010792: 681b ldr r3, [r3, #0] 8010794: 4a16 ldr r2, [pc, #88] @ (80107f0 ) 8010796: 4293 cmp r3, r2 8010798: d004 beq.n 80107a4 801079a: 687b ldr r3, [r7, #4] 801079c: 681b ldr r3, [r3, #0] 801079e: 4a15 ldr r2, [pc, #84] @ (80107f4 ) 80107a0: 4293 cmp r3, r2 80107a2: d10c bne.n 80107be { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 80107a4: 68bb ldr r3, [r7, #8] 80107a6: f023 0380 bic.w r3, r3, #128 @ 0x80 80107aa: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 80107ac: 683b ldr r3, [r7, #0] 80107ae: 689b ldr r3, [r3, #8] 80107b0: 68ba ldr r2, [r7, #8] 80107b2: 4313 orrs r3, r2 80107b4: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80107b6: 687b ldr r3, [r7, #4] 80107b8: 681b ldr r3, [r3, #0] 80107ba: 68ba ldr r2, [r7, #8] 80107bc: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 80107be: 687b ldr r3, [r7, #4] 80107c0: 2201 movs r2, #1 80107c2: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 80107c6: 687b ldr r3, [r7, #4] 80107c8: 2200 movs r2, #0 80107ca: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 80107ce: 2300 movs r3, #0 } 80107d0: 4618 mov r0, r3 80107d2: 3714 adds r7, #20 80107d4: 46bd mov sp, r7 80107d6: f85d 7b04 ldr.w r7, [sp], #4 80107da: 4770 bx lr 80107dc: 40010000 .word 0x40010000 80107e0: 40010400 .word 0x40010400 80107e4: 40000400 .word 0x40000400 80107e8: 40000800 .word 0x40000800 80107ec: 40000c00 .word 0x40000c00 80107f0: 40001800 .word 0x40001800 80107f4: 40014000 .word 0x40014000 080107f8 : * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { 80107f8: b480 push {r7} 80107fa: b085 sub sp, #20 80107fc: af00 add r7, sp, #0 80107fe: 6078 str r0, [r7, #4] 8010800: 6039 str r1, [r7, #0] /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; 8010802: 2300 movs r3, #0 8010804: 60fb str r3, [r7, #12] #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); #endif /* TIM_BDTR_BKBID */ /* Check input state */ __HAL_LOCK(htim); 8010806: 687b ldr r3, [r7, #4] 8010808: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 801080c: 2b01 cmp r3, #1 801080e: d101 bne.n 8010814 8010810: 2302 movs r3, #2 8010812: e065 b.n 80108e0 8010814: 687b ldr r3, [r7, #4] 8010816: 2201 movs r2, #1 8010818: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); 801081c: 68fb ldr r3, [r7, #12] 801081e: f023 02ff bic.w r2, r3, #255 @ 0xff 8010822: 683b ldr r3, [r7, #0] 8010824: 68db ldr r3, [r3, #12] 8010826: 4313 orrs r3, r2 8010828: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); 801082a: 68fb ldr r3, [r7, #12] 801082c: f423 7240 bic.w r2, r3, #768 @ 0x300 8010830: 683b ldr r3, [r7, #0] 8010832: 689b ldr r3, [r3, #8] 8010834: 4313 orrs r3, r2 8010836: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 8010838: 68fb ldr r3, [r7, #12] 801083a: f423 6280 bic.w r2, r3, #1024 @ 0x400 801083e: 683b ldr r3, [r7, #0] 8010840: 685b ldr r3, [r3, #4] 8010842: 4313 orrs r3, r2 8010844: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 8010846: 68fb ldr r3, [r7, #12] 8010848: f423 6200 bic.w r2, r3, #2048 @ 0x800 801084c: 683b ldr r3, [r7, #0] 801084e: 681b ldr r3, [r3, #0] 8010850: 4313 orrs r3, r2 8010852: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 8010854: 68fb ldr r3, [r7, #12] 8010856: f423 5280 bic.w r2, r3, #4096 @ 0x1000 801085a: 683b ldr r3, [r7, #0] 801085c: 691b ldr r3, [r3, #16] 801085e: 4313 orrs r3, r2 8010860: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 8010862: 68fb ldr r3, [r7, #12] 8010864: f423 5200 bic.w r2, r3, #8192 @ 0x2000 8010868: 683b ldr r3, [r7, #0] 801086a: 695b ldr r3, [r3, #20] 801086c: 4313 orrs r3, r2 801086e: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 8010870: 68fb ldr r3, [r7, #12] 8010872: f423 4280 bic.w r2, r3, #16384 @ 0x4000 8010876: 683b ldr r3, [r7, #0] 8010878: 6a9b ldr r3, [r3, #40] @ 0x28 801087a: 4313 orrs r3, r2 801087c: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 801087e: 68fb ldr r3, [r7, #12] 8010880: f423 2270 bic.w r2, r3, #983040 @ 0xf0000 8010884: 683b ldr r3, [r7, #0] 8010886: 699b ldr r3, [r3, #24] 8010888: 041b lsls r3, r3, #16 801088a: 4313 orrs r3, r2 801088c: 60fb str r3, [r7, #12] #if defined(TIM_BDTR_BKBID) MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); #endif /* TIM_BDTR_BKBID */ if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) 801088e: 687b ldr r3, [r7, #4] 8010890: 681b ldr r3, [r3, #0] 8010892: 4a16 ldr r2, [pc, #88] @ (80108ec ) 8010894: 4293 cmp r3, r2 8010896: d004 beq.n 80108a2 8010898: 687b ldr r3, [r7, #4] 801089a: 681b ldr r3, [r3, #0] 801089c: 4a14 ldr r2, [pc, #80] @ (80108f0 ) 801089e: 4293 cmp r3, r2 80108a0: d115 bne.n 80108ce #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); #endif /* TIM_BDTR_BKBID */ /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); 80108a2: 68fb ldr r3, [r7, #12] 80108a4: f423 0270 bic.w r2, r3, #15728640 @ 0xf00000 80108a8: 683b ldr r3, [r7, #0] 80108aa: 6a5b ldr r3, [r3, #36] @ 0x24 80108ac: 051b lsls r3, r3, #20 80108ae: 4313 orrs r3, r2 80108b0: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); 80108b2: 68fb ldr r3, [r7, #12] 80108b4: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000 80108b8: 683b ldr r3, [r7, #0] 80108ba: 69db ldr r3, [r3, #28] 80108bc: 4313 orrs r3, r2 80108be: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); 80108c0: 68fb ldr r3, [r7, #12] 80108c2: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000 80108c6: 683b ldr r3, [r7, #0] 80108c8: 6a1b ldr r3, [r3, #32] 80108ca: 4313 orrs r3, r2 80108cc: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); #endif /* TIM_BDTR_BKBID */ } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; 80108ce: 687b ldr r3, [r7, #4] 80108d0: 681b ldr r3, [r3, #0] 80108d2: 68fa ldr r2, [r7, #12] 80108d4: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(htim); 80108d6: 687b ldr r3, [r7, #4] 80108d8: 2200 movs r2, #0 80108da: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 80108de: 2300 movs r3, #0 } 80108e0: 4618 mov r0, r3 80108e2: 3714 adds r7, #20 80108e4: 46bd mov sp, r7 80108e6: f85d 7b04 ldr.w r7, [sp], #4 80108ea: 4770 bx lr 80108ec: 40010000 .word 0x40010000 80108f0: 40010400 .word 0x40010400 080108f4 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 80108f4: b480 push {r7} 80108f6: b083 sub sp, #12 80108f8: af00 add r7, sp, #0 80108fa: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 80108fc: bf00 nop 80108fe: 370c adds r7, #12 8010900: 46bd mov sp, r7 8010902: f85d 7b04 ldr.w r7, [sp], #4 8010906: 4770 bx lr 08010908 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8010908: b480 push {r7} 801090a: b083 sub sp, #12 801090c: af00 add r7, sp, #0 801090e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8010910: bf00 nop 8010912: 370c adds r7, #12 8010914: 46bd mov sp, r7 8010916: f85d 7b04 ldr.w r7, [sp], #4 801091a: 4770 bx lr 0801091c : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 801091c: b480 push {r7} 801091e: b083 sub sp, #12 8010920: af00 add r7, sp, #0 8010922: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 8010924: bf00 nop 8010926: 370c adds r7, #12 8010928: 46bd mov sp, r7 801092a: f85d 7b04 ldr.w r7, [sp], #4 801092e: 4770 bx lr 08010930 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8010930: b580 push {r7, lr} 8010932: b082 sub sp, #8 8010934: af00 add r7, sp, #0 8010936: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8010938: 687b ldr r3, [r7, #4] 801093a: 2b00 cmp r3, #0 801093c: d101 bne.n 8010942 { return HAL_ERROR; 801093e: 2301 movs r3, #1 8010940: e042 b.n 80109c8 { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 8010942: 687b ldr r3, [r7, #4] 8010944: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8010948: 2b00 cmp r3, #0 801094a: d106 bne.n 801095a { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 801094c: 687b ldr r3, [r7, #4] 801094e: 2200 movs r2, #0 8010950: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8010954: 6878 ldr r0, [r7, #4] 8010956: f7f3 fcab bl 80042b0 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 801095a: 687b ldr r3, [r7, #4] 801095c: 2224 movs r2, #36 @ 0x24 801095e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UART_DISABLE(huart); 8010962: 687b ldr r3, [r7, #4] 8010964: 681b ldr r3, [r3, #0] 8010966: 681a ldr r2, [r3, #0] 8010968: 687b ldr r3, [r7, #4] 801096a: 681b ldr r3, [r3, #0] 801096c: f022 0201 bic.w r2, r2, #1 8010970: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 8010972: 687b ldr r3, [r7, #4] 8010974: 6a9b ldr r3, [r3, #40] @ 0x28 8010976: 2b00 cmp r3, #0 8010978: d002 beq.n 8010980 { UART_AdvFeatureConfig(huart); 801097a: 6878 ldr r0, [r7, #4] 801097c: f001 f9e8 bl 8011d50 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 8010980: 6878 ldr r0, [r7, #4] 8010982: f000 fc7d bl 8011280 8010986: 4603 mov r3, r0 8010988: 2b01 cmp r3, #1 801098a: d101 bne.n 8010990 { return HAL_ERROR; 801098c: 2301 movs r3, #1 801098e: e01b b.n 80109c8 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8010990: 687b ldr r3, [r7, #4] 8010992: 681b ldr r3, [r3, #0] 8010994: 685a ldr r2, [r3, #4] 8010996: 687b ldr r3, [r7, #4] 8010998: 681b ldr r3, [r3, #0] 801099a: f422 4290 bic.w r2, r2, #18432 @ 0x4800 801099e: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 80109a0: 687b ldr r3, [r7, #4] 80109a2: 681b ldr r3, [r3, #0] 80109a4: 689a ldr r2, [r3, #8] 80109a6: 687b ldr r3, [r7, #4] 80109a8: 681b ldr r3, [r3, #0] 80109aa: f022 022a bic.w r2, r2, #42 @ 0x2a 80109ae: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 80109b0: 687b ldr r3, [r7, #4] 80109b2: 681b ldr r3, [r3, #0] 80109b4: 681a ldr r2, [r3, #0] 80109b6: 687b ldr r3, [r7, #4] 80109b8: 681b ldr r3, [r3, #0] 80109ba: f042 0201 orr.w r2, r2, #1 80109be: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 80109c0: 6878 ldr r0, [r7, #4] 80109c2: f001 fa67 bl 8011e94 80109c6: 4603 mov r3, r0 } 80109c8: 4618 mov r0, r3 80109ca: 3708 adds r7, #8 80109cc: 46bd mov sp, r7 80109ce: bd80 pop {r7, pc} 080109d0 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 80109d0: b480 push {r7} 80109d2: b091 sub sp, #68 @ 0x44 80109d4: af00 add r7, sp, #0 80109d6: 60f8 str r0, [r7, #12] 80109d8: 60b9 str r1, [r7, #8] 80109da: 4613 mov r3, r2 80109dc: 80fb strh r3, [r7, #6] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 80109de: 68fb ldr r3, [r7, #12] 80109e0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80109e4: 2b20 cmp r3, #32 80109e6: d178 bne.n 8010ada { if ((pData == NULL) || (Size == 0U)) 80109e8: 68bb ldr r3, [r7, #8] 80109ea: 2b00 cmp r3, #0 80109ec: d002 beq.n 80109f4 80109ee: 88fb ldrh r3, [r7, #6] 80109f0: 2b00 cmp r3, #0 80109f2: d101 bne.n 80109f8 { return HAL_ERROR; 80109f4: 2301 movs r3, #1 80109f6: e071 b.n 8010adc } huart->pTxBuffPtr = pData; 80109f8: 68fb ldr r3, [r7, #12] 80109fa: 68ba ldr r2, [r7, #8] 80109fc: 651a str r2, [r3, #80] @ 0x50 huart->TxXferSize = Size; 80109fe: 68fb ldr r3, [r7, #12] 8010a00: 88fa ldrh r2, [r7, #6] 8010a02: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 huart->TxXferCount = Size; 8010a06: 68fb ldr r3, [r7, #12] 8010a08: 88fa ldrh r2, [r7, #6] 8010a0a: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 huart->TxISR = NULL; 8010a0e: 68fb ldr r3, [r7, #12] 8010a10: 2200 movs r2, #0 8010a12: 679a str r2, [r3, #120] @ 0x78 huart->ErrorCode = HAL_UART_ERROR_NONE; 8010a14: 68fb ldr r3, [r7, #12] 8010a16: 2200 movs r2, #0 8010a18: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->gState = HAL_UART_STATE_BUSY_TX; 8010a1c: 68fb ldr r3, [r7, #12] 8010a1e: 2221 movs r2, #33 @ 0x21 8010a20: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Configure Tx interrupt processing */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) 8010a24: 68fb ldr r3, [r7, #12] 8010a26: 6e5b ldr r3, [r3, #100] @ 0x64 8010a28: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8010a2c: d12a bne.n 8010a84 { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8010a2e: 68fb ldr r3, [r7, #12] 8010a30: 689b ldr r3, [r3, #8] 8010a32: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8010a36: d107 bne.n 8010a48 8010a38: 68fb ldr r3, [r7, #12] 8010a3a: 691b ldr r3, [r3, #16] 8010a3c: 2b00 cmp r3, #0 8010a3e: d103 bne.n 8010a48 { huart->TxISR = UART_TxISR_16BIT_FIFOEN; 8010a40: 68fb ldr r3, [r7, #12] 8010a42: 4a29 ldr r2, [pc, #164] @ (8010ae8 ) 8010a44: 679a str r2, [r3, #120] @ 0x78 8010a46: e002 b.n 8010a4e } else { huart->TxISR = UART_TxISR_8BIT_FIFOEN; 8010a48: 68fb ldr r3, [r7, #12] 8010a4a: 4a28 ldr r2, [pc, #160] @ (8010aec ) 8010a4c: 679a str r2, [r3, #120] @ 0x78 } /* Enable the TX FIFO threshold interrupt */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 8010a4e: 68fb ldr r3, [r7, #12] 8010a50: 681b ldr r3, [r3, #0] 8010a52: 3308 adds r3, #8 8010a54: 62bb str r3, [r7, #40] @ 0x28 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010a56: 6abb ldr r3, [r7, #40] @ 0x28 8010a58: e853 3f00 ldrex r3, [r3] 8010a5c: 627b str r3, [r7, #36] @ 0x24 return(result); 8010a5e: 6a7b ldr r3, [r7, #36] @ 0x24 8010a60: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 8010a64: 63bb str r3, [r7, #56] @ 0x38 8010a66: 68fb ldr r3, [r7, #12] 8010a68: 681b ldr r3, [r3, #0] 8010a6a: 3308 adds r3, #8 8010a6c: 6bba ldr r2, [r7, #56] @ 0x38 8010a6e: 637a str r2, [r7, #52] @ 0x34 8010a70: 633b str r3, [r7, #48] @ 0x30 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010a72: 6b39 ldr r1, [r7, #48] @ 0x30 8010a74: 6b7a ldr r2, [r7, #52] @ 0x34 8010a76: e841 2300 strex r3, r2, [r1] 8010a7a: 62fb str r3, [r7, #44] @ 0x2c return(result); 8010a7c: 6afb ldr r3, [r7, #44] @ 0x2c 8010a7e: 2b00 cmp r3, #0 8010a80: d1e5 bne.n 8010a4e 8010a82: e028 b.n 8010ad6 } else { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8010a84: 68fb ldr r3, [r7, #12] 8010a86: 689b ldr r3, [r3, #8] 8010a88: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8010a8c: d107 bne.n 8010a9e 8010a8e: 68fb ldr r3, [r7, #12] 8010a90: 691b ldr r3, [r3, #16] 8010a92: 2b00 cmp r3, #0 8010a94: d103 bne.n 8010a9e { huart->TxISR = UART_TxISR_16BIT; 8010a96: 68fb ldr r3, [r7, #12] 8010a98: 4a15 ldr r2, [pc, #84] @ (8010af0 ) 8010a9a: 679a str r2, [r3, #120] @ 0x78 8010a9c: e002 b.n 8010aa4 } else { huart->TxISR = UART_TxISR_8BIT; 8010a9e: 68fb ldr r3, [r7, #12] 8010aa0: 4a14 ldr r2, [pc, #80] @ (8010af4 ) 8010aa2: 679a str r2, [r3, #120] @ 0x78 } /* Enable the Transmit Data Register Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8010aa4: 68fb ldr r3, [r7, #12] 8010aa6: 681b ldr r3, [r3, #0] 8010aa8: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010aaa: 697b ldr r3, [r7, #20] 8010aac: e853 3f00 ldrex r3, [r3] 8010ab0: 613b str r3, [r7, #16] return(result); 8010ab2: 693b ldr r3, [r7, #16] 8010ab4: f043 0380 orr.w r3, r3, #128 @ 0x80 8010ab8: 63fb str r3, [r7, #60] @ 0x3c 8010aba: 68fb ldr r3, [r7, #12] 8010abc: 681b ldr r3, [r3, #0] 8010abe: 461a mov r2, r3 8010ac0: 6bfb ldr r3, [r7, #60] @ 0x3c 8010ac2: 623b str r3, [r7, #32] 8010ac4: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010ac6: 69f9 ldr r1, [r7, #28] 8010ac8: 6a3a ldr r2, [r7, #32] 8010aca: e841 2300 strex r3, r2, [r1] 8010ace: 61bb str r3, [r7, #24] return(result); 8010ad0: 69bb ldr r3, [r7, #24] 8010ad2: 2b00 cmp r3, #0 8010ad4: d1e6 bne.n 8010aa4 } return HAL_OK; 8010ad6: 2300 movs r3, #0 8010ad8: e000 b.n 8010adc } else { return HAL_BUSY; 8010ada: 2302 movs r3, #2 } } 8010adc: 4618 mov r0, r3 8010ade: 3744 adds r7, #68 @ 0x44 8010ae0: 46bd mov sp, r7 8010ae2: f85d 7b04 ldr.w r7, [sp], #4 8010ae6: 4770 bx lr 8010ae8: 0801265b .word 0x0801265b 8010aec: 0801257b .word 0x0801257b 8010af0: 080124b9 .word 0x080124b9 8010af4: 08012401 .word 0x08012401 08010af8 : * @brief Handle UART interrupt request. * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8010af8: b580 push {r7, lr} 8010afa: b0ba sub sp, #232 @ 0xe8 8010afc: af00 add r7, sp, #0 8010afe: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->ISR); 8010b00: 687b ldr r3, [r7, #4] 8010b02: 681b ldr r3, [r3, #0] 8010b04: 69db ldr r3, [r3, #28] 8010b06: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8010b0a: 687b ldr r3, [r7, #4] 8010b0c: 681b ldr r3, [r3, #0] 8010b0e: 681b ldr r3, [r3, #0] 8010b10: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8010b14: 687b ldr r3, [r7, #4] 8010b16: 681b ldr r3, [r3, #0] 8010b18: 689b ldr r3, [r3, #8] 8010b1a: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags; uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); 8010b1e: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4 8010b22: f640 030f movw r3, #2063 @ 0x80f 8010b26: 4013 ands r3, r2 8010b28: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == 0U) 8010b2c: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8010b30: 2b00 cmp r3, #0 8010b32: d11b bne.n 8010b6c { /* UART in mode Receiver ---------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 8010b34: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010b38: f003 0320 and.w r3, r3, #32 8010b3c: 2b00 cmp r3, #0 8010b3e: d015 beq.n 8010b6c && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 8010b40: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010b44: f003 0320 and.w r3, r3, #32 8010b48: 2b00 cmp r3, #0 8010b4a: d105 bne.n 8010b58 || ((cr3its & USART_CR3_RXFTIE) != 0U))) 8010b4c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8010b50: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010b54: 2b00 cmp r3, #0 8010b56: d009 beq.n 8010b6c { if (huart->RxISR != NULL) 8010b58: 687b ldr r3, [r7, #4] 8010b5a: 6f5b ldr r3, [r3, #116] @ 0x74 8010b5c: 2b00 cmp r3, #0 8010b5e: f000 8377 beq.w 8011250 { huart->RxISR(huart); 8010b62: 687b ldr r3, [r7, #4] 8010b64: 6f5b ldr r3, [r3, #116] @ 0x74 8010b66: 6878 ldr r0, [r7, #4] 8010b68: 4798 blx r3 } return; 8010b6a: e371 b.n 8011250 } } /* If some errors occur */ if ((errorflags != 0U) 8010b6c: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8010b70: 2b00 cmp r3, #0 8010b72: f000 8123 beq.w 8010dbc && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) 8010b76: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 8010b7a: 4b8d ldr r3, [pc, #564] @ (8010db0 ) 8010b7c: 4013 ands r3, r2 8010b7e: 2b00 cmp r3, #0 8010b80: d106 bne.n 8010b90 || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) 8010b82: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0 8010b86: 4b8b ldr r3, [pc, #556] @ (8010db4 ) 8010b88: 4013 ands r3, r2 8010b8a: 2b00 cmp r3, #0 8010b8c: f000 8116 beq.w 8010dbc { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8010b90: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010b94: f003 0301 and.w r3, r3, #1 8010b98: 2b00 cmp r3, #0 8010b9a: d011 beq.n 8010bc0 8010b9c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010ba0: f403 7380 and.w r3, r3, #256 @ 0x100 8010ba4: 2b00 cmp r3, #0 8010ba6: d00b beq.n 8010bc0 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8010ba8: 687b ldr r3, [r7, #4] 8010baa: 681b ldr r3, [r3, #0] 8010bac: 2201 movs r2, #1 8010bae: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8010bb0: 687b ldr r3, [r7, #4] 8010bb2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010bb6: f043 0201 orr.w r2, r3, #1 8010bba: 687b ldr r3, [r7, #4] 8010bbc: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8010bc0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010bc4: f003 0302 and.w r3, r3, #2 8010bc8: 2b00 cmp r3, #0 8010bca: d011 beq.n 8010bf0 8010bcc: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8010bd0: f003 0301 and.w r3, r3, #1 8010bd4: 2b00 cmp r3, #0 8010bd6: d00b beq.n 8010bf0 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8010bd8: 687b ldr r3, [r7, #4] 8010bda: 681b ldr r3, [r3, #0] 8010bdc: 2202 movs r2, #2 8010bde: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8010be0: 687b ldr r3, [r7, #4] 8010be2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010be6: f043 0204 orr.w r2, r3, #4 8010bea: 687b ldr r3, [r7, #4] 8010bec: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8010bf0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010bf4: f003 0304 and.w r3, r3, #4 8010bf8: 2b00 cmp r3, #0 8010bfa: d011 beq.n 8010c20 8010bfc: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8010c00: f003 0301 and.w r3, r3, #1 8010c04: 2b00 cmp r3, #0 8010c06: d00b beq.n 8010c20 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8010c08: 687b ldr r3, [r7, #4] 8010c0a: 681b ldr r3, [r3, #0] 8010c0c: 2204 movs r2, #4 8010c0e: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8010c10: 687b ldr r3, [r7, #4] 8010c12: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010c16: f043 0202 orr.w r2, r3, #2 8010c1a: 687b ldr r3, [r7, #4] 8010c1c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Over-Run interrupt occurred -----------------------------------------*/ if (((isrflags & USART_ISR_ORE) != 0U) 8010c20: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010c24: f003 0308 and.w r3, r3, #8 8010c28: 2b00 cmp r3, #0 8010c2a: d017 beq.n 8010c5c && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 8010c2c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010c30: f003 0320 and.w r3, r3, #32 8010c34: 2b00 cmp r3, #0 8010c36: d105 bne.n 8010c44 ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) 8010c38: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 8010c3c: 4b5c ldr r3, [pc, #368] @ (8010db0 ) 8010c3e: 4013 ands r3, r2 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 8010c40: 2b00 cmp r3, #0 8010c42: d00b beq.n 8010c5c { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8010c44: 687b ldr r3, [r7, #4] 8010c46: 681b ldr r3, [r3, #0] 8010c48: 2208 movs r2, #8 8010c4a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_ORE; 8010c4c: 687b ldr r3, [r7, #4] 8010c4e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010c52: f043 0208 orr.w r2, r3, #8 8010c56: 687b ldr r3, [r7, #4] 8010c58: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Receiver Timeout interrupt occurred ---------------------------------*/ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) 8010c5c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010c60: f403 6300 and.w r3, r3, #2048 @ 0x800 8010c64: 2b00 cmp r3, #0 8010c66: d012 beq.n 8010c8e 8010c68: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010c6c: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8010c70: 2b00 cmp r3, #0 8010c72: d00c beq.n 8010c8e { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8010c74: 687b ldr r3, [r7, #4] 8010c76: 681b ldr r3, [r3, #0] 8010c78: f44f 6200 mov.w r2, #2048 @ 0x800 8010c7c: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_RTO; 8010c7e: 687b ldr r3, [r7, #4] 8010c80: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010c84: f043 0220 orr.w r2, r3, #32 8010c88: 687b ldr r3, [r7, #4] 8010c8a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8010c8e: 687b ldr r3, [r7, #4] 8010c90: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010c94: 2b00 cmp r3, #0 8010c96: f000 82dd beq.w 8011254 { /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 8010c9a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010c9e: f003 0320 and.w r3, r3, #32 8010ca2: 2b00 cmp r3, #0 8010ca4: d013 beq.n 8010cce && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 8010ca6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010caa: f003 0320 and.w r3, r3, #32 8010cae: 2b00 cmp r3, #0 8010cb0: d105 bne.n 8010cbe || ((cr3its & USART_CR3_RXFTIE) != 0U))) 8010cb2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8010cb6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010cba: 2b00 cmp r3, #0 8010cbc: d007 beq.n 8010cce { if (huart->RxISR != NULL) 8010cbe: 687b ldr r3, [r7, #4] 8010cc0: 6f5b ldr r3, [r3, #116] @ 0x74 8010cc2: 2b00 cmp r3, #0 8010cc4: d003 beq.n 8010cce { huart->RxISR(huart); 8010cc6: 687b ldr r3, [r7, #4] 8010cc8: 6f5b ldr r3, [r3, #116] @ 0x74 8010cca: 6878 ldr r0, [r7, #4] 8010ccc: 4798 blx r3 /* If Error is to be considered as blocking : - Receiver Timeout error in Reception - Overrun error in Reception - any error occurs in DMA mode reception */ errorcode = huart->ErrorCode; 8010cce: 687b ldr r3, [r7, #4] 8010cd0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010cd4: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8010cd8: 687b ldr r3, [r7, #4] 8010cda: 681b ldr r3, [r3, #0] 8010cdc: 689b ldr r3, [r3, #8] 8010cde: f003 0340 and.w r3, r3, #64 @ 0x40 8010ce2: 2b40 cmp r3, #64 @ 0x40 8010ce4: d005 beq.n 8010cf2 ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) 8010ce6: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8010cea: f003 0328 and.w r3, r3, #40 @ 0x28 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8010cee: 2b00 cmp r3, #0 8010cf0: d054 beq.n 8010d9c { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8010cf2: 6878 ldr r0, [r7, #4] 8010cf4: f001 fb08 bl 8012308 /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010cf8: 687b ldr r3, [r7, #4] 8010cfa: 681b ldr r3, [r3, #0] 8010cfc: 689b ldr r3, [r3, #8] 8010cfe: f003 0340 and.w r3, r3, #64 @ 0x40 8010d02: 2b40 cmp r3, #64 @ 0x40 8010d04: d146 bne.n 8010d94 { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8010d06: 687b ldr r3, [r7, #4] 8010d08: 681b ldr r3, [r3, #0] 8010d0a: 3308 adds r3, #8 8010d0c: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010d10: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8010d14: e853 3f00 ldrex r3, [r3] 8010d18: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8010d1c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8010d20: f023 0340 bic.w r3, r3, #64 @ 0x40 8010d24: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8010d28: 687b ldr r3, [r7, #4] 8010d2a: 681b ldr r3, [r3, #0] 8010d2c: 3308 adds r3, #8 8010d2e: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8010d32: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8010d36: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010d3a: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8010d3e: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8010d42: e841 2300 strex r3, r2, [r1] 8010d46: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8010d4a: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8010d4e: 2b00 cmp r3, #0 8010d50: d1d9 bne.n 8010d06 /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 8010d52: 687b ldr r3, [r7, #4] 8010d54: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010d58: 2b00 cmp r3, #0 8010d5a: d017 beq.n 8010d8c { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8010d5c: 687b ldr r3, [r7, #4] 8010d5e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010d62: 4a15 ldr r2, [pc, #84] @ (8010db8 ) 8010d64: 651a str r2, [r3, #80] @ 0x50 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8010d66: 687b ldr r3, [r7, #4] 8010d68: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010d6c: 4618 mov r0, r3 8010d6e: f7f8 fb9f bl 80094b0 8010d72: 4603 mov r3, r0 8010d74: 2b00 cmp r3, #0 8010d76: d019 beq.n 8010dac { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8010d78: 687b ldr r3, [r7, #4] 8010d7a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010d7e: 6d1b ldr r3, [r3, #80] @ 0x50 8010d80: 687a ldr r2, [r7, #4] 8010d82: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80 8010d86: 4610 mov r0, r2 8010d88: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010d8a: e00f b.n 8010dac #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8010d8c: 6878 ldr r0, [r7, #4] 8010d8e: f000 fa6d bl 801126c if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010d92: e00b b.n 8010dac #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8010d94: 6878 ldr r0, [r7, #4] 8010d96: f000 fa69 bl 801126c if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010d9a: e007 b.n 8010dac #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8010d9c: 6878 ldr r0, [r7, #4] 8010d9e: f000 fa65 bl 801126c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8010da2: 687b ldr r3, [r7, #4] 8010da4: 2200 movs r2, #0 8010da6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } return; 8010daa: e253 b.n 8011254 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010dac: bf00 nop return; 8010dae: e251 b.n 8011254 8010db0: 10000001 .word 0x10000001 8010db4: 04000120 .word 0x04000120 8010db8: 080123d5 .word 0x080123d5 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8010dbc: 687b ldr r3, [r7, #4] 8010dbe: 6edb ldr r3, [r3, #108] @ 0x6c 8010dc0: 2b01 cmp r3, #1 8010dc2: f040 81e7 bne.w 8011194 && ((isrflags & USART_ISR_IDLE) != 0U) 8010dc6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010dca: f003 0310 and.w r3, r3, #16 8010dce: 2b00 cmp r3, #0 8010dd0: f000 81e0 beq.w 8011194 && ((cr1its & USART_ISR_IDLE) != 0U)) 8010dd4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010dd8: f003 0310 and.w r3, r3, #16 8010ddc: 2b00 cmp r3, #0 8010dde: f000 81d9 beq.w 8011194 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8010de2: 687b ldr r3, [r7, #4] 8010de4: 681b ldr r3, [r3, #0] 8010de6: 2210 movs r2, #16 8010de8: 621a str r2, [r3, #32] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010dea: 687b ldr r3, [r7, #4] 8010dec: 681b ldr r3, [r3, #0] 8010dee: 689b ldr r3, [r3, #8] 8010df0: f003 0340 and.w r3, r3, #64 @ 0x40 8010df4: 2b40 cmp r3, #64 @ 0x40 8010df6: f040 8151 bne.w 801109c { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8010dfa: 687b ldr r3, [r7, #4] 8010dfc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e00: 681b ldr r3, [r3, #0] 8010e02: 4a96 ldr r2, [pc, #600] @ (801105c ) 8010e04: 4293 cmp r3, r2 8010e06: d068 beq.n 8010eda 8010e08: 687b ldr r3, [r7, #4] 8010e0a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e0e: 681b ldr r3, [r3, #0] 8010e10: 4a93 ldr r2, [pc, #588] @ (8011060 ) 8010e12: 4293 cmp r3, r2 8010e14: d061 beq.n 8010eda 8010e16: 687b ldr r3, [r7, #4] 8010e18: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e1c: 681b ldr r3, [r3, #0] 8010e1e: 4a91 ldr r2, [pc, #580] @ (8011064 ) 8010e20: 4293 cmp r3, r2 8010e22: d05a beq.n 8010eda 8010e24: 687b ldr r3, [r7, #4] 8010e26: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e2a: 681b ldr r3, [r3, #0] 8010e2c: 4a8e ldr r2, [pc, #568] @ (8011068 ) 8010e2e: 4293 cmp r3, r2 8010e30: d053 beq.n 8010eda 8010e32: 687b ldr r3, [r7, #4] 8010e34: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e38: 681b ldr r3, [r3, #0] 8010e3a: 4a8c ldr r2, [pc, #560] @ (801106c ) 8010e3c: 4293 cmp r3, r2 8010e3e: d04c beq.n 8010eda 8010e40: 687b ldr r3, [r7, #4] 8010e42: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e46: 681b ldr r3, [r3, #0] 8010e48: 4a89 ldr r2, [pc, #548] @ (8011070 ) 8010e4a: 4293 cmp r3, r2 8010e4c: d045 beq.n 8010eda 8010e4e: 687b ldr r3, [r7, #4] 8010e50: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e54: 681b ldr r3, [r3, #0] 8010e56: 4a87 ldr r2, [pc, #540] @ (8011074 ) 8010e58: 4293 cmp r3, r2 8010e5a: d03e beq.n 8010eda 8010e5c: 687b ldr r3, [r7, #4] 8010e5e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e62: 681b ldr r3, [r3, #0] 8010e64: 4a84 ldr r2, [pc, #528] @ (8011078 ) 8010e66: 4293 cmp r3, r2 8010e68: d037 beq.n 8010eda 8010e6a: 687b ldr r3, [r7, #4] 8010e6c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e70: 681b ldr r3, [r3, #0] 8010e72: 4a82 ldr r2, [pc, #520] @ (801107c ) 8010e74: 4293 cmp r3, r2 8010e76: d030 beq.n 8010eda 8010e78: 687b ldr r3, [r7, #4] 8010e7a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e7e: 681b ldr r3, [r3, #0] 8010e80: 4a7f ldr r2, [pc, #508] @ (8011080 ) 8010e82: 4293 cmp r3, r2 8010e84: d029 beq.n 8010eda 8010e86: 687b ldr r3, [r7, #4] 8010e88: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e8c: 681b ldr r3, [r3, #0] 8010e8e: 4a7d ldr r2, [pc, #500] @ (8011084 ) 8010e90: 4293 cmp r3, r2 8010e92: d022 beq.n 8010eda 8010e94: 687b ldr r3, [r7, #4] 8010e96: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e9a: 681b ldr r3, [r3, #0] 8010e9c: 4a7a ldr r2, [pc, #488] @ (8011088 ) 8010e9e: 4293 cmp r3, r2 8010ea0: d01b beq.n 8010eda 8010ea2: 687b ldr r3, [r7, #4] 8010ea4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010ea8: 681b ldr r3, [r3, #0] 8010eaa: 4a78 ldr r2, [pc, #480] @ (801108c ) 8010eac: 4293 cmp r3, r2 8010eae: d014 beq.n 8010eda 8010eb0: 687b ldr r3, [r7, #4] 8010eb2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010eb6: 681b ldr r3, [r3, #0] 8010eb8: 4a75 ldr r2, [pc, #468] @ (8011090 ) 8010eba: 4293 cmp r3, r2 8010ebc: d00d beq.n 8010eda 8010ebe: 687b ldr r3, [r7, #4] 8010ec0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010ec4: 681b ldr r3, [r3, #0] 8010ec6: 4a73 ldr r2, [pc, #460] @ (8011094 ) 8010ec8: 4293 cmp r3, r2 8010eca: d006 beq.n 8010eda 8010ecc: 687b ldr r3, [r7, #4] 8010ece: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010ed2: 681b ldr r3, [r3, #0] 8010ed4: 4a70 ldr r2, [pc, #448] @ (8011098 ) 8010ed6: 4293 cmp r3, r2 8010ed8: d106 bne.n 8010ee8 8010eda: 687b ldr r3, [r7, #4] 8010edc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010ee0: 681b ldr r3, [r3, #0] 8010ee2: 685b ldr r3, [r3, #4] 8010ee4: b29b uxth r3, r3 8010ee6: e005 b.n 8010ef4 8010ee8: 687b ldr r3, [r7, #4] 8010eea: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010eee: 681b ldr r3, [r3, #0] 8010ef0: 685b ldr r3, [r3, #4] 8010ef2: b29b uxth r3, r3 8010ef4: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8010ef8: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8010efc: 2b00 cmp r3, #0 8010efe: f000 81ab beq.w 8011258 && (nb_remaining_rx_data < huart->RxXferSize)) 8010f02: 687b ldr r3, [r7, #4] 8010f04: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8010f08: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8010f0c: 429a cmp r2, r3 8010f0e: f080 81a3 bcs.w 8011258 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8010f12: 687b ldr r3, [r7, #4] 8010f14: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8010f18: f8a3 205e strh.w r2, [r3, #94] @ 0x5e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8010f1c: 687b ldr r3, [r7, #4] 8010f1e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010f22: 69db ldr r3, [r3, #28] 8010f24: f5b3 7f80 cmp.w r3, #256 @ 0x100 8010f28: f000 8087 beq.w 801103a { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8010f2c: 687b ldr r3, [r7, #4] 8010f2e: 681b ldr r3, [r3, #0] 8010f30: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010f34: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8010f38: e853 3f00 ldrex r3, [r3] 8010f3c: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8010f40: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8010f44: f423 7380 bic.w r3, r3, #256 @ 0x100 8010f48: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8010f4c: 687b ldr r3, [r7, #4] 8010f4e: 681b ldr r3, [r3, #0] 8010f50: 461a mov r2, r3 8010f52: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 8010f56: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8010f5a: f8c7 2090 str.w r2, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010f5e: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8010f62: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8010f66: e841 2300 strex r3, r2, [r1] 8010f6a: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8010f6e: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8010f72: 2b00 cmp r3, #0 8010f74: d1da bne.n 8010f2c ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8010f76: 687b ldr r3, [r7, #4] 8010f78: 681b ldr r3, [r3, #0] 8010f7a: 3308 adds r3, #8 8010f7c: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010f7e: 6f7b ldr r3, [r7, #116] @ 0x74 8010f80: e853 3f00 ldrex r3, [r3] 8010f84: 673b str r3, [r7, #112] @ 0x70 return(result); 8010f86: 6f3b ldr r3, [r7, #112] @ 0x70 8010f88: f023 0301 bic.w r3, r3, #1 8010f8c: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8010f90: 687b ldr r3, [r7, #4] 8010f92: 681b ldr r3, [r3, #0] 8010f94: 3308 adds r3, #8 8010f96: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8010f9a: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8010f9e: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010fa0: 6ff9 ldr r1, [r7, #124] @ 0x7c 8010fa2: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8010fa6: e841 2300 strex r3, r2, [r1] 8010faa: 67bb str r3, [r7, #120] @ 0x78 return(result); 8010fac: 6fbb ldr r3, [r7, #120] @ 0x78 8010fae: 2b00 cmp r3, #0 8010fb0: d1e1 bne.n 8010f76 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8010fb2: 687b ldr r3, [r7, #4] 8010fb4: 681b ldr r3, [r3, #0] 8010fb6: 3308 adds r3, #8 8010fb8: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010fba: 6e3b ldr r3, [r7, #96] @ 0x60 8010fbc: e853 3f00 ldrex r3, [r3] 8010fc0: 65fb str r3, [r7, #92] @ 0x5c return(result); 8010fc2: 6dfb ldr r3, [r7, #92] @ 0x5c 8010fc4: f023 0340 bic.w r3, r3, #64 @ 0x40 8010fc8: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8010fcc: 687b ldr r3, [r7, #4] 8010fce: 681b ldr r3, [r3, #0] 8010fd0: 3308 adds r3, #8 8010fd2: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8010fd6: 66fa str r2, [r7, #108] @ 0x6c 8010fd8: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010fda: 6eb9 ldr r1, [r7, #104] @ 0x68 8010fdc: 6efa ldr r2, [r7, #108] @ 0x6c 8010fde: e841 2300 strex r3, r2, [r1] 8010fe2: 667b str r3, [r7, #100] @ 0x64 return(result); 8010fe4: 6e7b ldr r3, [r7, #100] @ 0x64 8010fe6: 2b00 cmp r3, #0 8010fe8: d1e3 bne.n 8010fb2 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8010fea: 687b ldr r3, [r7, #4] 8010fec: 2220 movs r2, #32 8010fee: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8010ff2: 687b ldr r3, [r7, #4] 8010ff4: 2200 movs r2, #0 8010ff6: 66da str r2, [r3, #108] @ 0x6c ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8010ff8: 687b ldr r3, [r7, #4] 8010ffa: 681b ldr r3, [r3, #0] 8010ffc: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010ffe: 6cfb ldr r3, [r7, #76] @ 0x4c 8011000: e853 3f00 ldrex r3, [r3] 8011004: 64bb str r3, [r7, #72] @ 0x48 return(result); 8011006: 6cbb ldr r3, [r7, #72] @ 0x48 8011008: f023 0310 bic.w r3, r3, #16 801100c: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8011010: 687b ldr r3, [r7, #4] 8011012: 681b ldr r3, [r3, #0] 8011014: 461a mov r2, r3 8011016: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801101a: 65bb str r3, [r7, #88] @ 0x58 801101c: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801101e: 6d79 ldr r1, [r7, #84] @ 0x54 8011020: 6dba ldr r2, [r7, #88] @ 0x58 8011022: e841 2300 strex r3, r2, [r1] 8011026: 653b str r3, [r7, #80] @ 0x50 return(result); 8011028: 6d3b ldr r3, [r7, #80] @ 0x50 801102a: 2b00 cmp r3, #0 801102c: d1e4 bne.n 8010ff8 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 801102e: 687b ldr r3, [r7, #4] 8011030: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011034: 4618 mov r0, r3 8011036: f7f7 ff1d bl 8008e74 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 801103a: 687b ldr r3, [r7, #4] 801103c: 2202 movs r2, #2 801103e: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8011040: 687b ldr r3, [r7, #4] 8011042: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 8011046: 687b ldr r3, [r7, #4] 8011048: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 801104c: b29b uxth r3, r3 801104e: 1ad3 subs r3, r2, r3 8011050: b29b uxth r3, r3 8011052: 4619 mov r1, r3 8011054: 6878 ldr r0, [r7, #4] 8011056: f7f3 fcad bl 80049b4 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 801105a: e0fd b.n 8011258 801105c: 40020010 .word 0x40020010 8011060: 40020028 .word 0x40020028 8011064: 40020040 .word 0x40020040 8011068: 40020058 .word 0x40020058 801106c: 40020070 .word 0x40020070 8011070: 40020088 .word 0x40020088 8011074: 400200a0 .word 0x400200a0 8011078: 400200b8 .word 0x400200b8 801107c: 40020410 .word 0x40020410 8011080: 40020428 .word 0x40020428 8011084: 40020440 .word 0x40020440 8011088: 40020458 .word 0x40020458 801108c: 40020470 .word 0x40020470 8011090: 40020488 .word 0x40020488 8011094: 400204a0 .word 0x400204a0 8011098: 400204b8 .word 0x400204b8 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 801109c: 687b ldr r3, [r7, #4] 801109e: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 80110a2: 687b ldr r3, [r7, #4] 80110a4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80110a8: b29b uxth r3, r3 80110aa: 1ad3 subs r3, r2, r3 80110ac: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 80110b0: 687b ldr r3, [r7, #4] 80110b2: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80110b6: b29b uxth r3, r3 80110b8: 2b00 cmp r3, #0 80110ba: f000 80cf beq.w 801125c && (nb_rx_data > 0U)) 80110be: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 80110c2: 2b00 cmp r3, #0 80110c4: f000 80ca beq.w 801125c { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 80110c8: 687b ldr r3, [r7, #4] 80110ca: 681b ldr r3, [r3, #0] 80110cc: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80110ce: 6bbb ldr r3, [r7, #56] @ 0x38 80110d0: e853 3f00 ldrex r3, [r3] 80110d4: 637b str r3, [r7, #52] @ 0x34 return(result); 80110d6: 6b7b ldr r3, [r7, #52] @ 0x34 80110d8: f423 7390 bic.w r3, r3, #288 @ 0x120 80110dc: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 80110e0: 687b ldr r3, [r7, #4] 80110e2: 681b ldr r3, [r3, #0] 80110e4: 461a mov r2, r3 80110e6: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 80110ea: 647b str r3, [r7, #68] @ 0x44 80110ec: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80110ee: 6c39 ldr r1, [r7, #64] @ 0x40 80110f0: 6c7a ldr r2, [r7, #68] @ 0x44 80110f2: e841 2300 strex r3, r2, [r1] 80110f6: 63fb str r3, [r7, #60] @ 0x3c return(result); 80110f8: 6bfb ldr r3, [r7, #60] @ 0x3c 80110fa: 2b00 cmp r3, #0 80110fc: d1e4 bne.n 80110c8 /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 80110fe: 687b ldr r3, [r7, #4] 8011100: 681b ldr r3, [r3, #0] 8011102: 3308 adds r3, #8 8011104: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011106: 6a7b ldr r3, [r7, #36] @ 0x24 8011108: e853 3f00 ldrex r3, [r3] 801110c: 623b str r3, [r7, #32] return(result); 801110e: 6a3a ldr r2, [r7, #32] 8011110: 4b55 ldr r3, [pc, #340] @ (8011268 ) 8011112: 4013 ands r3, r2 8011114: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8011118: 687b ldr r3, [r7, #4] 801111a: 681b ldr r3, [r3, #0] 801111c: 3308 adds r3, #8 801111e: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8011122: 633a str r2, [r7, #48] @ 0x30 8011124: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011126: 6af9 ldr r1, [r7, #44] @ 0x2c 8011128: 6b3a ldr r2, [r7, #48] @ 0x30 801112a: e841 2300 strex r3, r2, [r1] 801112e: 62bb str r3, [r7, #40] @ 0x28 return(result); 8011130: 6abb ldr r3, [r7, #40] @ 0x28 8011132: 2b00 cmp r3, #0 8011134: d1e3 bne.n 80110fe /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8011136: 687b ldr r3, [r7, #4] 8011138: 2220 movs r2, #32 801113a: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801113e: 687b ldr r3, [r7, #4] 8011140: 2200 movs r2, #0 8011142: 66da str r2, [r3, #108] @ 0x6c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8011144: 687b ldr r3, [r7, #4] 8011146: 2200 movs r2, #0 8011148: 675a str r2, [r3, #116] @ 0x74 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801114a: 687b ldr r3, [r7, #4] 801114c: 681b ldr r3, [r3, #0] 801114e: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011150: 693b ldr r3, [r7, #16] 8011152: e853 3f00 ldrex r3, [r3] 8011156: 60fb str r3, [r7, #12] return(result); 8011158: 68fb ldr r3, [r7, #12] 801115a: f023 0310 bic.w r3, r3, #16 801115e: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8011162: 687b ldr r3, [r7, #4] 8011164: 681b ldr r3, [r3, #0] 8011166: 461a mov r2, r3 8011168: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 801116c: 61fb str r3, [r7, #28] 801116e: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011170: 69b9 ldr r1, [r7, #24] 8011172: 69fa ldr r2, [r7, #28] 8011174: e841 2300 strex r3, r2, [r1] 8011178: 617b str r3, [r7, #20] return(result); 801117a: 697b ldr r3, [r7, #20] 801117c: 2b00 cmp r3, #0 801117e: d1e4 bne.n 801114a /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8011180: 687b ldr r3, [r7, #4] 8011182: 2202 movs r2, #2 8011184: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8011186: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 801118a: 4619 mov r1, r3 801118c: 6878 ldr r0, [r7, #4] 801118e: f7f3 fc11 bl 80049b4 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 8011192: e063 b.n 801125c } } /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) 8011194: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011198: f403 1380 and.w r3, r3, #1048576 @ 0x100000 801119c: 2b00 cmp r3, #0 801119e: d00e beq.n 80111be 80111a0: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80111a4: f403 0380 and.w r3, r3, #4194304 @ 0x400000 80111a8: 2b00 cmp r3, #0 80111aa: d008 beq.n 80111be { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); 80111ac: 687b ldr r3, [r7, #4] 80111ae: 681b ldr r3, [r3, #0] 80111b0: f44f 1280 mov.w r2, #1048576 @ 0x100000 80111b4: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Wakeup Callback */ huart->WakeupCallback(huart); #else /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); 80111b6: 6878 ldr r0, [r7, #4] 80111b8: f002 f80c bl 80131d4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 80111bc: e051 b.n 8011262 } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) 80111be: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80111c2: f003 0380 and.w r3, r3, #128 @ 0x80 80111c6: 2b00 cmp r3, #0 80111c8: d014 beq.n 80111f4 && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) 80111ca: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80111ce: f003 0380 and.w r3, r3, #128 @ 0x80 80111d2: 2b00 cmp r3, #0 80111d4: d105 bne.n 80111e2 || ((cr3its & USART_CR3_TXFTIE) != 0U))) 80111d6: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80111da: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80111de: 2b00 cmp r3, #0 80111e0: d008 beq.n 80111f4 { if (huart->TxISR != NULL) 80111e2: 687b ldr r3, [r7, #4] 80111e4: 6f9b ldr r3, [r3, #120] @ 0x78 80111e6: 2b00 cmp r3, #0 80111e8: d03a beq.n 8011260 { huart->TxISR(huart); 80111ea: 687b ldr r3, [r7, #4] 80111ec: 6f9b ldr r3, [r3, #120] @ 0x78 80111ee: 6878 ldr r0, [r7, #4] 80111f0: 4798 blx r3 } return; 80111f2: e035 b.n 8011260 } /* UART in mode Transmitter (transmission end) -----------------------------*/ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) 80111f4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80111f8: f003 0340 and.w r3, r3, #64 @ 0x40 80111fc: 2b00 cmp r3, #0 80111fe: d009 beq.n 8011214 8011200: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011204: f003 0340 and.w r3, r3, #64 @ 0x40 8011208: 2b00 cmp r3, #0 801120a: d003 beq.n 8011214 { UART_EndTransmit_IT(huart); 801120c: 6878 ldr r0, [r7, #4] 801120e: f001 fa99 bl 8012744 return; 8011212: e026 b.n 8011262 } /* UART TX Fifo Empty occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) 8011214: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011218: f403 0300 and.w r3, r3, #8388608 @ 0x800000 801121c: 2b00 cmp r3, #0 801121e: d009 beq.n 8011234 8011220: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011224: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 8011228: 2b00 cmp r3, #0 801122a: d003 beq.n 8011234 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ huart->TxFifoEmptyCallback(huart); #else /* Call legacy weak Tx Fifo Empty Callback */ HAL_UARTEx_TxFifoEmptyCallback(huart); 801122c: 6878 ldr r0, [r7, #4] 801122e: f001 ffe5 bl 80131fc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8011232: e016 b.n 8011262 } /* UART RX Fifo Full occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) 8011234: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011238: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 801123c: 2b00 cmp r3, #0 801123e: d010 beq.n 8011262 8011240: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011244: 2b00 cmp r3, #0 8011246: da0c bge.n 8011262 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ huart->RxFifoFullCallback(huart); #else /* Call legacy weak Rx Fifo Full Callback */ HAL_UARTEx_RxFifoFullCallback(huart); 8011248: 6878 ldr r0, [r7, #4] 801124a: f001 ffcd bl 80131e8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 801124e: e008 b.n 8011262 return; 8011250: bf00 nop 8011252: e006 b.n 8011262 return; 8011254: bf00 nop 8011256: e004 b.n 8011262 return; 8011258: bf00 nop 801125a: e002 b.n 8011262 return; 801125c: bf00 nop 801125e: e000 b.n 8011262 return; 8011260: bf00 nop } } 8011262: 37e8 adds r7, #232 @ 0xe8 8011264: 46bd mov sp, r7 8011266: bd80 pop {r7, pc} 8011268: effffffe .word 0xeffffffe 0801126c : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 801126c: b480 push {r7} 801126e: b083 sub sp, #12 8011270: af00 add r7, sp, #0 8011272: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } 8011274: bf00 nop 8011276: 370c adds r7, #12 8011278: 46bd mov sp, r7 801127a: f85d 7b04 ldr.w r7, [sp], #4 801127e: 4770 bx lr 08011280 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 8011280: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8011284: b092 sub sp, #72 @ 0x48 8011286: af00 add r7, sp, #0 8011288: 6178 str r0, [r7, #20] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 801128a: 2300 movs r3, #0 801128c: f887 3042 strb.w r3, [r7, #66] @ 0x42 * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 8011290: 697b ldr r3, [r7, #20] 8011292: 689a ldr r2, [r3, #8] 8011294: 697b ldr r3, [r7, #20] 8011296: 691b ldr r3, [r3, #16] 8011298: 431a orrs r2, r3 801129a: 697b ldr r3, [r7, #20] 801129c: 695b ldr r3, [r3, #20] 801129e: 431a orrs r2, r3 80112a0: 697b ldr r3, [r7, #20] 80112a2: 69db ldr r3, [r3, #28] 80112a4: 4313 orrs r3, r2 80112a6: 647b str r3, [r7, #68] @ 0x44 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 80112a8: 697b ldr r3, [r7, #20] 80112aa: 681b ldr r3, [r3, #0] 80112ac: 681a ldr r2, [r3, #0] 80112ae: 4bbe ldr r3, [pc, #760] @ (80115a8 ) 80112b0: 4013 ands r3, r2 80112b2: 697a ldr r2, [r7, #20] 80112b4: 6812 ldr r2, [r2, #0] 80112b6: 6c79 ldr r1, [r7, #68] @ 0x44 80112b8: 430b orrs r3, r1 80112ba: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 80112bc: 697b ldr r3, [r7, #20] 80112be: 681b ldr r3, [r3, #0] 80112c0: 685b ldr r3, [r3, #4] 80112c2: f423 5140 bic.w r1, r3, #12288 @ 0x3000 80112c6: 697b ldr r3, [r7, #20] 80112c8: 68da ldr r2, [r3, #12] 80112ca: 697b ldr r3, [r7, #20] 80112cc: 681b ldr r3, [r3, #0] 80112ce: 430a orrs r2, r1 80112d0: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 80112d2: 697b ldr r3, [r7, #20] 80112d4: 699b ldr r3, [r3, #24] 80112d6: 647b str r3, [r7, #68] @ 0x44 if (!(UART_INSTANCE_LOWPOWER(huart))) 80112d8: 697b ldr r3, [r7, #20] 80112da: 681b ldr r3, [r3, #0] 80112dc: 4ab3 ldr r2, [pc, #716] @ (80115ac ) 80112de: 4293 cmp r3, r2 80112e0: d004 beq.n 80112ec { tmpreg |= huart->Init.OneBitSampling; 80112e2: 697b ldr r3, [r7, #20] 80112e4: 6a1b ldr r3, [r3, #32] 80112e6: 6c7a ldr r2, [r7, #68] @ 0x44 80112e8: 4313 orrs r3, r2 80112ea: 647b str r3, [r7, #68] @ 0x44 } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 80112ec: 697b ldr r3, [r7, #20] 80112ee: 681b ldr r3, [r3, #0] 80112f0: 689a ldr r2, [r3, #8] 80112f2: 4baf ldr r3, [pc, #700] @ (80115b0 ) 80112f4: 4013 ands r3, r2 80112f6: 697a ldr r2, [r7, #20] 80112f8: 6812 ldr r2, [r2, #0] 80112fa: 6c79 ldr r1, [r7, #68] @ 0x44 80112fc: 430b orrs r3, r1 80112fe: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 8011300: 697b ldr r3, [r7, #20] 8011302: 681b ldr r3, [r3, #0] 8011304: 6adb ldr r3, [r3, #44] @ 0x2c 8011306: f023 010f bic.w r1, r3, #15 801130a: 697b ldr r3, [r7, #20] 801130c: 6a5a ldr r2, [r3, #36] @ 0x24 801130e: 697b ldr r3, [r7, #20] 8011310: 681b ldr r3, [r3, #0] 8011312: 430a orrs r2, r1 8011314: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 8011316: 697b ldr r3, [r7, #20] 8011318: 681b ldr r3, [r3, #0] 801131a: 4aa6 ldr r2, [pc, #664] @ (80115b4 ) 801131c: 4293 cmp r3, r2 801131e: d177 bne.n 8011410 8011320: 4ba5 ldr r3, [pc, #660] @ (80115b8 ) 8011322: 6d5b ldr r3, [r3, #84] @ 0x54 8011324: f003 0338 and.w r3, r3, #56 @ 0x38 8011328: 2b28 cmp r3, #40 @ 0x28 801132a: d86d bhi.n 8011408 801132c: a201 add r2, pc, #4 @ (adr r2, 8011334 ) 801132e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011332: bf00 nop 8011334: 080113d9 .word 0x080113d9 8011338: 08011409 .word 0x08011409 801133c: 08011409 .word 0x08011409 8011340: 08011409 .word 0x08011409 8011344: 08011409 .word 0x08011409 8011348: 08011409 .word 0x08011409 801134c: 08011409 .word 0x08011409 8011350: 08011409 .word 0x08011409 8011354: 080113e1 .word 0x080113e1 8011358: 08011409 .word 0x08011409 801135c: 08011409 .word 0x08011409 8011360: 08011409 .word 0x08011409 8011364: 08011409 .word 0x08011409 8011368: 08011409 .word 0x08011409 801136c: 08011409 .word 0x08011409 8011370: 08011409 .word 0x08011409 8011374: 080113e9 .word 0x080113e9 8011378: 08011409 .word 0x08011409 801137c: 08011409 .word 0x08011409 8011380: 08011409 .word 0x08011409 8011384: 08011409 .word 0x08011409 8011388: 08011409 .word 0x08011409 801138c: 08011409 .word 0x08011409 8011390: 08011409 .word 0x08011409 8011394: 080113f1 .word 0x080113f1 8011398: 08011409 .word 0x08011409 801139c: 08011409 .word 0x08011409 80113a0: 08011409 .word 0x08011409 80113a4: 08011409 .word 0x08011409 80113a8: 08011409 .word 0x08011409 80113ac: 08011409 .word 0x08011409 80113b0: 08011409 .word 0x08011409 80113b4: 080113f9 .word 0x080113f9 80113b8: 08011409 .word 0x08011409 80113bc: 08011409 .word 0x08011409 80113c0: 08011409 .word 0x08011409 80113c4: 08011409 .word 0x08011409 80113c8: 08011409 .word 0x08011409 80113cc: 08011409 .word 0x08011409 80113d0: 08011409 .word 0x08011409 80113d4: 08011401 .word 0x08011401 80113d8: 2301 movs r3, #1 80113da: f887 3043 strb.w r3, [r7, #67] @ 0x43 80113de: e222 b.n 8011826 80113e0: 2304 movs r3, #4 80113e2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80113e6: e21e b.n 8011826 80113e8: 2308 movs r3, #8 80113ea: f887 3043 strb.w r3, [r7, #67] @ 0x43 80113ee: e21a b.n 8011826 80113f0: 2310 movs r3, #16 80113f2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80113f6: e216 b.n 8011826 80113f8: 2320 movs r3, #32 80113fa: f887 3043 strb.w r3, [r7, #67] @ 0x43 80113fe: e212 b.n 8011826 8011400: 2340 movs r3, #64 @ 0x40 8011402: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011406: e20e b.n 8011826 8011408: 2380 movs r3, #128 @ 0x80 801140a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801140e: e20a b.n 8011826 8011410: 697b ldr r3, [r7, #20] 8011412: 681b ldr r3, [r3, #0] 8011414: 4a69 ldr r2, [pc, #420] @ (80115bc ) 8011416: 4293 cmp r3, r2 8011418: d130 bne.n 801147c 801141a: 4b67 ldr r3, [pc, #412] @ (80115b8 ) 801141c: 6d5b ldr r3, [r3, #84] @ 0x54 801141e: f003 0307 and.w r3, r3, #7 8011422: 2b05 cmp r3, #5 8011424: d826 bhi.n 8011474 8011426: a201 add r2, pc, #4 @ (adr r2, 801142c ) 8011428: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801142c: 08011445 .word 0x08011445 8011430: 0801144d .word 0x0801144d 8011434: 08011455 .word 0x08011455 8011438: 0801145d .word 0x0801145d 801143c: 08011465 .word 0x08011465 8011440: 0801146d .word 0x0801146d 8011444: 2300 movs r3, #0 8011446: f887 3043 strb.w r3, [r7, #67] @ 0x43 801144a: e1ec b.n 8011826 801144c: 2304 movs r3, #4 801144e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011452: e1e8 b.n 8011826 8011454: 2308 movs r3, #8 8011456: f887 3043 strb.w r3, [r7, #67] @ 0x43 801145a: e1e4 b.n 8011826 801145c: 2310 movs r3, #16 801145e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011462: e1e0 b.n 8011826 8011464: 2320 movs r3, #32 8011466: f887 3043 strb.w r3, [r7, #67] @ 0x43 801146a: e1dc b.n 8011826 801146c: 2340 movs r3, #64 @ 0x40 801146e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011472: e1d8 b.n 8011826 8011474: 2380 movs r3, #128 @ 0x80 8011476: f887 3043 strb.w r3, [r7, #67] @ 0x43 801147a: e1d4 b.n 8011826 801147c: 697b ldr r3, [r7, #20] 801147e: 681b ldr r3, [r3, #0] 8011480: 4a4f ldr r2, [pc, #316] @ (80115c0 ) 8011482: 4293 cmp r3, r2 8011484: d130 bne.n 80114e8 8011486: 4b4c ldr r3, [pc, #304] @ (80115b8 ) 8011488: 6d5b ldr r3, [r3, #84] @ 0x54 801148a: f003 0307 and.w r3, r3, #7 801148e: 2b05 cmp r3, #5 8011490: d826 bhi.n 80114e0 8011492: a201 add r2, pc, #4 @ (adr r2, 8011498 ) 8011494: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011498: 080114b1 .word 0x080114b1 801149c: 080114b9 .word 0x080114b9 80114a0: 080114c1 .word 0x080114c1 80114a4: 080114c9 .word 0x080114c9 80114a8: 080114d1 .word 0x080114d1 80114ac: 080114d9 .word 0x080114d9 80114b0: 2300 movs r3, #0 80114b2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114b6: e1b6 b.n 8011826 80114b8: 2304 movs r3, #4 80114ba: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114be: e1b2 b.n 8011826 80114c0: 2308 movs r3, #8 80114c2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114c6: e1ae b.n 8011826 80114c8: 2310 movs r3, #16 80114ca: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114ce: e1aa b.n 8011826 80114d0: 2320 movs r3, #32 80114d2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114d6: e1a6 b.n 8011826 80114d8: 2340 movs r3, #64 @ 0x40 80114da: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114de: e1a2 b.n 8011826 80114e0: 2380 movs r3, #128 @ 0x80 80114e2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114e6: e19e b.n 8011826 80114e8: 697b ldr r3, [r7, #20] 80114ea: 681b ldr r3, [r3, #0] 80114ec: 4a35 ldr r2, [pc, #212] @ (80115c4 ) 80114ee: 4293 cmp r3, r2 80114f0: d130 bne.n 8011554 80114f2: 4b31 ldr r3, [pc, #196] @ (80115b8 ) 80114f4: 6d5b ldr r3, [r3, #84] @ 0x54 80114f6: f003 0307 and.w r3, r3, #7 80114fa: 2b05 cmp r3, #5 80114fc: d826 bhi.n 801154c 80114fe: a201 add r2, pc, #4 @ (adr r2, 8011504 ) 8011500: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011504: 0801151d .word 0x0801151d 8011508: 08011525 .word 0x08011525 801150c: 0801152d .word 0x0801152d 8011510: 08011535 .word 0x08011535 8011514: 0801153d .word 0x0801153d 8011518: 08011545 .word 0x08011545 801151c: 2300 movs r3, #0 801151e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011522: e180 b.n 8011826 8011524: 2304 movs r3, #4 8011526: f887 3043 strb.w r3, [r7, #67] @ 0x43 801152a: e17c b.n 8011826 801152c: 2308 movs r3, #8 801152e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011532: e178 b.n 8011826 8011534: 2310 movs r3, #16 8011536: f887 3043 strb.w r3, [r7, #67] @ 0x43 801153a: e174 b.n 8011826 801153c: 2320 movs r3, #32 801153e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011542: e170 b.n 8011826 8011544: 2340 movs r3, #64 @ 0x40 8011546: f887 3043 strb.w r3, [r7, #67] @ 0x43 801154a: e16c b.n 8011826 801154c: 2380 movs r3, #128 @ 0x80 801154e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011552: e168 b.n 8011826 8011554: 697b ldr r3, [r7, #20] 8011556: 681b ldr r3, [r3, #0] 8011558: 4a1b ldr r2, [pc, #108] @ (80115c8 ) 801155a: 4293 cmp r3, r2 801155c: d142 bne.n 80115e4 801155e: 4b16 ldr r3, [pc, #88] @ (80115b8 ) 8011560: 6d5b ldr r3, [r3, #84] @ 0x54 8011562: f003 0307 and.w r3, r3, #7 8011566: 2b05 cmp r3, #5 8011568: d838 bhi.n 80115dc 801156a: a201 add r2, pc, #4 @ (adr r2, 8011570 ) 801156c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011570: 08011589 .word 0x08011589 8011574: 08011591 .word 0x08011591 8011578: 08011599 .word 0x08011599 801157c: 080115a1 .word 0x080115a1 8011580: 080115cd .word 0x080115cd 8011584: 080115d5 .word 0x080115d5 8011588: 2300 movs r3, #0 801158a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801158e: e14a b.n 8011826 8011590: 2304 movs r3, #4 8011592: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011596: e146 b.n 8011826 8011598: 2308 movs r3, #8 801159a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801159e: e142 b.n 8011826 80115a0: 2310 movs r3, #16 80115a2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80115a6: e13e b.n 8011826 80115a8: cfff69f3 .word 0xcfff69f3 80115ac: 58000c00 .word 0x58000c00 80115b0: 11fff4ff .word 0x11fff4ff 80115b4: 40011000 .word 0x40011000 80115b8: 58024400 .word 0x58024400 80115bc: 40004400 .word 0x40004400 80115c0: 40004800 .word 0x40004800 80115c4: 40004c00 .word 0x40004c00 80115c8: 40005000 .word 0x40005000 80115cc: 2320 movs r3, #32 80115ce: f887 3043 strb.w r3, [r7, #67] @ 0x43 80115d2: e128 b.n 8011826 80115d4: 2340 movs r3, #64 @ 0x40 80115d6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80115da: e124 b.n 8011826 80115dc: 2380 movs r3, #128 @ 0x80 80115de: f887 3043 strb.w r3, [r7, #67] @ 0x43 80115e2: e120 b.n 8011826 80115e4: 697b ldr r3, [r7, #20] 80115e6: 681b ldr r3, [r3, #0] 80115e8: 4acb ldr r2, [pc, #812] @ (8011918 ) 80115ea: 4293 cmp r3, r2 80115ec: d176 bne.n 80116dc 80115ee: 4bcb ldr r3, [pc, #812] @ (801191c ) 80115f0: 6d5b ldr r3, [r3, #84] @ 0x54 80115f2: f003 0338 and.w r3, r3, #56 @ 0x38 80115f6: 2b28 cmp r3, #40 @ 0x28 80115f8: d86c bhi.n 80116d4 80115fa: a201 add r2, pc, #4 @ (adr r2, 8011600 ) 80115fc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011600: 080116a5 .word 0x080116a5 8011604: 080116d5 .word 0x080116d5 8011608: 080116d5 .word 0x080116d5 801160c: 080116d5 .word 0x080116d5 8011610: 080116d5 .word 0x080116d5 8011614: 080116d5 .word 0x080116d5 8011618: 080116d5 .word 0x080116d5 801161c: 080116d5 .word 0x080116d5 8011620: 080116ad .word 0x080116ad 8011624: 080116d5 .word 0x080116d5 8011628: 080116d5 .word 0x080116d5 801162c: 080116d5 .word 0x080116d5 8011630: 080116d5 .word 0x080116d5 8011634: 080116d5 .word 0x080116d5 8011638: 080116d5 .word 0x080116d5 801163c: 080116d5 .word 0x080116d5 8011640: 080116b5 .word 0x080116b5 8011644: 080116d5 .word 0x080116d5 8011648: 080116d5 .word 0x080116d5 801164c: 080116d5 .word 0x080116d5 8011650: 080116d5 .word 0x080116d5 8011654: 080116d5 .word 0x080116d5 8011658: 080116d5 .word 0x080116d5 801165c: 080116d5 .word 0x080116d5 8011660: 080116bd .word 0x080116bd 8011664: 080116d5 .word 0x080116d5 8011668: 080116d5 .word 0x080116d5 801166c: 080116d5 .word 0x080116d5 8011670: 080116d5 .word 0x080116d5 8011674: 080116d5 .word 0x080116d5 8011678: 080116d5 .word 0x080116d5 801167c: 080116d5 .word 0x080116d5 8011680: 080116c5 .word 0x080116c5 8011684: 080116d5 .word 0x080116d5 8011688: 080116d5 .word 0x080116d5 801168c: 080116d5 .word 0x080116d5 8011690: 080116d5 .word 0x080116d5 8011694: 080116d5 .word 0x080116d5 8011698: 080116d5 .word 0x080116d5 801169c: 080116d5 .word 0x080116d5 80116a0: 080116cd .word 0x080116cd 80116a4: 2301 movs r3, #1 80116a6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80116aa: e0bc b.n 8011826 80116ac: 2304 movs r3, #4 80116ae: f887 3043 strb.w r3, [r7, #67] @ 0x43 80116b2: e0b8 b.n 8011826 80116b4: 2308 movs r3, #8 80116b6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80116ba: e0b4 b.n 8011826 80116bc: 2310 movs r3, #16 80116be: f887 3043 strb.w r3, [r7, #67] @ 0x43 80116c2: e0b0 b.n 8011826 80116c4: 2320 movs r3, #32 80116c6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80116ca: e0ac b.n 8011826 80116cc: 2340 movs r3, #64 @ 0x40 80116ce: f887 3043 strb.w r3, [r7, #67] @ 0x43 80116d2: e0a8 b.n 8011826 80116d4: 2380 movs r3, #128 @ 0x80 80116d6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80116da: e0a4 b.n 8011826 80116dc: 697b ldr r3, [r7, #20] 80116de: 681b ldr r3, [r3, #0] 80116e0: 4a8f ldr r2, [pc, #572] @ (8011920 ) 80116e2: 4293 cmp r3, r2 80116e4: d130 bne.n 8011748 80116e6: 4b8d ldr r3, [pc, #564] @ (801191c ) 80116e8: 6d5b ldr r3, [r3, #84] @ 0x54 80116ea: f003 0307 and.w r3, r3, #7 80116ee: 2b05 cmp r3, #5 80116f0: d826 bhi.n 8011740 80116f2: a201 add r2, pc, #4 @ (adr r2, 80116f8 ) 80116f4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80116f8: 08011711 .word 0x08011711 80116fc: 08011719 .word 0x08011719 8011700: 08011721 .word 0x08011721 8011704: 08011729 .word 0x08011729 8011708: 08011731 .word 0x08011731 801170c: 08011739 .word 0x08011739 8011710: 2300 movs r3, #0 8011712: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011716: e086 b.n 8011826 8011718: 2304 movs r3, #4 801171a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801171e: e082 b.n 8011826 8011720: 2308 movs r3, #8 8011722: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011726: e07e b.n 8011826 8011728: 2310 movs r3, #16 801172a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801172e: e07a b.n 8011826 8011730: 2320 movs r3, #32 8011732: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011736: e076 b.n 8011826 8011738: 2340 movs r3, #64 @ 0x40 801173a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801173e: e072 b.n 8011826 8011740: 2380 movs r3, #128 @ 0x80 8011742: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011746: e06e b.n 8011826 8011748: 697b ldr r3, [r7, #20] 801174a: 681b ldr r3, [r3, #0] 801174c: 4a75 ldr r2, [pc, #468] @ (8011924 ) 801174e: 4293 cmp r3, r2 8011750: d130 bne.n 80117b4 8011752: 4b72 ldr r3, [pc, #456] @ (801191c ) 8011754: 6d5b ldr r3, [r3, #84] @ 0x54 8011756: f003 0307 and.w r3, r3, #7 801175a: 2b05 cmp r3, #5 801175c: d826 bhi.n 80117ac 801175e: a201 add r2, pc, #4 @ (adr r2, 8011764 ) 8011760: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011764: 0801177d .word 0x0801177d 8011768: 08011785 .word 0x08011785 801176c: 0801178d .word 0x0801178d 8011770: 08011795 .word 0x08011795 8011774: 0801179d .word 0x0801179d 8011778: 080117a5 .word 0x080117a5 801177c: 2300 movs r3, #0 801177e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011782: e050 b.n 8011826 8011784: 2304 movs r3, #4 8011786: f887 3043 strb.w r3, [r7, #67] @ 0x43 801178a: e04c b.n 8011826 801178c: 2308 movs r3, #8 801178e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011792: e048 b.n 8011826 8011794: 2310 movs r3, #16 8011796: f887 3043 strb.w r3, [r7, #67] @ 0x43 801179a: e044 b.n 8011826 801179c: 2320 movs r3, #32 801179e: f887 3043 strb.w r3, [r7, #67] @ 0x43 80117a2: e040 b.n 8011826 80117a4: 2340 movs r3, #64 @ 0x40 80117a6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80117aa: e03c b.n 8011826 80117ac: 2380 movs r3, #128 @ 0x80 80117ae: f887 3043 strb.w r3, [r7, #67] @ 0x43 80117b2: e038 b.n 8011826 80117b4: 697b ldr r3, [r7, #20] 80117b6: 681b ldr r3, [r3, #0] 80117b8: 4a5b ldr r2, [pc, #364] @ (8011928 ) 80117ba: 4293 cmp r3, r2 80117bc: d130 bne.n 8011820 80117be: 4b57 ldr r3, [pc, #348] @ (801191c ) 80117c0: 6d9b ldr r3, [r3, #88] @ 0x58 80117c2: f003 0307 and.w r3, r3, #7 80117c6: 2b05 cmp r3, #5 80117c8: d826 bhi.n 8011818 80117ca: a201 add r2, pc, #4 @ (adr r2, 80117d0 ) 80117cc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80117d0: 080117e9 .word 0x080117e9 80117d4: 080117f1 .word 0x080117f1 80117d8: 080117f9 .word 0x080117f9 80117dc: 08011801 .word 0x08011801 80117e0: 08011809 .word 0x08011809 80117e4: 08011811 .word 0x08011811 80117e8: 2302 movs r3, #2 80117ea: f887 3043 strb.w r3, [r7, #67] @ 0x43 80117ee: e01a b.n 8011826 80117f0: 2304 movs r3, #4 80117f2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80117f6: e016 b.n 8011826 80117f8: 2308 movs r3, #8 80117fa: f887 3043 strb.w r3, [r7, #67] @ 0x43 80117fe: e012 b.n 8011826 8011800: 2310 movs r3, #16 8011802: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011806: e00e b.n 8011826 8011808: 2320 movs r3, #32 801180a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801180e: e00a b.n 8011826 8011810: 2340 movs r3, #64 @ 0x40 8011812: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011816: e006 b.n 8011826 8011818: 2380 movs r3, #128 @ 0x80 801181a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801181e: e002 b.n 8011826 8011820: 2380 movs r3, #128 @ 0x80 8011822: f887 3043 strb.w r3, [r7, #67] @ 0x43 /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 8011826: 697b ldr r3, [r7, #20] 8011828: 681b ldr r3, [r3, #0] 801182a: 4a3f ldr r2, [pc, #252] @ (8011928 ) 801182c: 4293 cmp r3, r2 801182e: f040 80f8 bne.w 8011a22 { /* Retrieve frequency clock */ switch (clocksource) 8011832: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 8011836: 2b20 cmp r3, #32 8011838: dc46 bgt.n 80118c8 801183a: 2b02 cmp r3, #2 801183c: f2c0 8082 blt.w 8011944 8011840: 3b02 subs r3, #2 8011842: 2b1e cmp r3, #30 8011844: d87e bhi.n 8011944 8011846: a201 add r2, pc, #4 @ (adr r2, 801184c ) 8011848: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801184c: 080118cf .word 0x080118cf 8011850: 08011945 .word 0x08011945 8011854: 080118d7 .word 0x080118d7 8011858: 08011945 .word 0x08011945 801185c: 08011945 .word 0x08011945 8011860: 08011945 .word 0x08011945 8011864: 080118e7 .word 0x080118e7 8011868: 08011945 .word 0x08011945 801186c: 08011945 .word 0x08011945 8011870: 08011945 .word 0x08011945 8011874: 08011945 .word 0x08011945 8011878: 08011945 .word 0x08011945 801187c: 08011945 .word 0x08011945 8011880: 08011945 .word 0x08011945 8011884: 080118f7 .word 0x080118f7 8011888: 08011945 .word 0x08011945 801188c: 08011945 .word 0x08011945 8011890: 08011945 .word 0x08011945 8011894: 08011945 .word 0x08011945 8011898: 08011945 .word 0x08011945 801189c: 08011945 .word 0x08011945 80118a0: 08011945 .word 0x08011945 80118a4: 08011945 .word 0x08011945 80118a8: 08011945 .word 0x08011945 80118ac: 08011945 .word 0x08011945 80118b0: 08011945 .word 0x08011945 80118b4: 08011945 .word 0x08011945 80118b8: 08011945 .word 0x08011945 80118bc: 08011945 .word 0x08011945 80118c0: 08011945 .word 0x08011945 80118c4: 08011937 .word 0x08011937 80118c8: 2b40 cmp r3, #64 @ 0x40 80118ca: d037 beq.n 801193c 80118cc: e03a b.n 8011944 { case UART_CLOCKSOURCE_D3PCLK1: pclk = HAL_RCCEx_GetD3PCLK1Freq(); 80118ce: f7fc fe3d bl 800e54c 80118d2: 63f8 str r0, [r7, #60] @ 0x3c break; 80118d4: e03c b.n 8011950 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80118d6: f107 0324 add.w r3, r7, #36 @ 0x24 80118da: 4618 mov r0, r3 80118dc: f7fc fe4c bl 800e578 pclk = pll2_clocks.PLL2_Q_Frequency; 80118e0: 6abb ldr r3, [r7, #40] @ 0x28 80118e2: 63fb str r3, [r7, #60] @ 0x3c break; 80118e4: e034 b.n 8011950 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 80118e6: f107 0318 add.w r3, r7, #24 80118ea: 4618 mov r0, r3 80118ec: f7fc ff98 bl 800e820 pclk = pll3_clocks.PLL3_Q_Frequency; 80118f0: 69fb ldr r3, [r7, #28] 80118f2: 63fb str r3, [r7, #60] @ 0x3c break; 80118f4: e02c b.n 8011950 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 80118f6: 4b09 ldr r3, [pc, #36] @ (801191c ) 80118f8: 681b ldr r3, [r3, #0] 80118fa: f003 0320 and.w r3, r3, #32 80118fe: 2b00 cmp r3, #0 8011900: d016 beq.n 8011930 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8011902: 4b06 ldr r3, [pc, #24] @ (801191c ) 8011904: 681b ldr r3, [r3, #0] 8011906: 08db lsrs r3, r3, #3 8011908: f003 0303 and.w r3, r3, #3 801190c: 4a07 ldr r2, [pc, #28] @ (801192c ) 801190e: fa22 f303 lsr.w r3, r2, r3 8011912: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8011914: e01c b.n 8011950 8011916: bf00 nop 8011918: 40011400 .word 0x40011400 801191c: 58024400 .word 0x58024400 8011920: 40007800 .word 0x40007800 8011924: 40007c00 .word 0x40007c00 8011928: 58000c00 .word 0x58000c00 801192c: 03d09000 .word 0x03d09000 pclk = (uint32_t) HSI_VALUE; 8011930: 4b9d ldr r3, [pc, #628] @ (8011ba8 ) 8011932: 63fb str r3, [r7, #60] @ 0x3c break; 8011934: e00c b.n 8011950 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 8011936: 4b9d ldr r3, [pc, #628] @ (8011bac ) 8011938: 63fb str r3, [r7, #60] @ 0x3c break; 801193a: e009 b.n 8011950 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 801193c: f44f 4300 mov.w r3, #32768 @ 0x8000 8011940: 63fb str r3, [r7, #60] @ 0x3c break; 8011942: e005 b.n 8011950 default: pclk = 0U; 8011944: 2300 movs r3, #0 8011946: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 8011948: 2301 movs r3, #1 801194a: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 801194e: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 8011950: 6bfb ldr r3, [r7, #60] @ 0x3c 8011952: 2b00 cmp r3, #0 8011954: f000 81de beq.w 8011d14 { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 8011958: 697b ldr r3, [r7, #20] 801195a: 6a5b ldr r3, [r3, #36] @ 0x24 801195c: 4a94 ldr r2, [pc, #592] @ (8011bb0 ) 801195e: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8011962: 461a mov r2, r3 8011964: 6bfb ldr r3, [r7, #60] @ 0x3c 8011966: fbb3 f3f2 udiv r3, r3, r2 801196a: 633b str r3, [r7, #48] @ 0x30 /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 801196c: 697b ldr r3, [r7, #20] 801196e: 685a ldr r2, [r3, #4] 8011970: 4613 mov r3, r2 8011972: 005b lsls r3, r3, #1 8011974: 4413 add r3, r2 8011976: 6b3a ldr r2, [r7, #48] @ 0x30 8011978: 429a cmp r2, r3 801197a: d305 bcc.n 8011988 (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) 801197c: 697b ldr r3, [r7, #20] 801197e: 685b ldr r3, [r3, #4] 8011980: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 8011982: 6b3a ldr r2, [r7, #48] @ 0x30 8011984: 429a cmp r2, r3 8011986: d903 bls.n 8011990 { ret = HAL_ERROR; 8011988: 2301 movs r3, #1 801198a: f887 3042 strb.w r3, [r7, #66] @ 0x42 801198e: e1c1 b.n 8011d14 } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8011990: 6bfb ldr r3, [r7, #60] @ 0x3c 8011992: 2200 movs r2, #0 8011994: 60bb str r3, [r7, #8] 8011996: 60fa str r2, [r7, #12] 8011998: 697b ldr r3, [r7, #20] 801199a: 6a5b ldr r3, [r3, #36] @ 0x24 801199c: 4a84 ldr r2, [pc, #528] @ (8011bb0 ) 801199e: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80119a2: b29b uxth r3, r3 80119a4: 2200 movs r2, #0 80119a6: 603b str r3, [r7, #0] 80119a8: 607a str r2, [r7, #4] 80119aa: e9d7 2300 ldrd r2, r3, [r7] 80119ae: e9d7 0102 ldrd r0, r1, [r7, #8] 80119b2: f7ee fce5 bl 8000380 <__aeabi_uldivmod> 80119b6: 4602 mov r2, r0 80119b8: 460b mov r3, r1 80119ba: 4610 mov r0, r2 80119bc: 4619 mov r1, r3 80119be: f04f 0200 mov.w r2, #0 80119c2: f04f 0300 mov.w r3, #0 80119c6: 020b lsls r3, r1, #8 80119c8: ea43 6310 orr.w r3, r3, r0, lsr #24 80119cc: 0202 lsls r2, r0, #8 80119ce: 6979 ldr r1, [r7, #20] 80119d0: 6849 ldr r1, [r1, #4] 80119d2: 0849 lsrs r1, r1, #1 80119d4: 2000 movs r0, #0 80119d6: 460c mov r4, r1 80119d8: 4605 mov r5, r0 80119da: eb12 0804 adds.w r8, r2, r4 80119de: eb43 0905 adc.w r9, r3, r5 80119e2: 697b ldr r3, [r7, #20] 80119e4: 685b ldr r3, [r3, #4] 80119e6: 2200 movs r2, #0 80119e8: 469a mov sl, r3 80119ea: 4693 mov fp, r2 80119ec: 4652 mov r2, sl 80119ee: 465b mov r3, fp 80119f0: 4640 mov r0, r8 80119f2: 4649 mov r1, r9 80119f4: f7ee fcc4 bl 8000380 <__aeabi_uldivmod> 80119f8: 4602 mov r2, r0 80119fa: 460b mov r3, r1 80119fc: 4613 mov r3, r2 80119fe: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 8011a00: 6bbb ldr r3, [r7, #56] @ 0x38 8011a02: f5b3 7f40 cmp.w r3, #768 @ 0x300 8011a06: d308 bcc.n 8011a1a 8011a08: 6bbb ldr r3, [r7, #56] @ 0x38 8011a0a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8011a0e: d204 bcs.n 8011a1a { huart->Instance->BRR = usartdiv; 8011a10: 697b ldr r3, [r7, #20] 8011a12: 681b ldr r3, [r3, #0] 8011a14: 6bba ldr r2, [r7, #56] @ 0x38 8011a16: 60da str r2, [r3, #12] 8011a18: e17c b.n 8011d14 } else { ret = HAL_ERROR; 8011a1a: 2301 movs r3, #1 8011a1c: f887 3042 strb.w r3, [r7, #66] @ 0x42 8011a20: e178 b.n 8011d14 } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8011a22: 697b ldr r3, [r7, #20] 8011a24: 69db ldr r3, [r3, #28] 8011a26: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8011a2a: f040 80c5 bne.w 8011bb8 { switch (clocksource) 8011a2e: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 8011a32: 2b20 cmp r3, #32 8011a34: dc48 bgt.n 8011ac8 8011a36: 2b00 cmp r3, #0 8011a38: db7b blt.n 8011b32 8011a3a: 2b20 cmp r3, #32 8011a3c: d879 bhi.n 8011b32 8011a3e: a201 add r2, pc, #4 @ (adr r2, 8011a44 ) 8011a40: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011a44: 08011acf .word 0x08011acf 8011a48: 08011ad7 .word 0x08011ad7 8011a4c: 08011b33 .word 0x08011b33 8011a50: 08011b33 .word 0x08011b33 8011a54: 08011adf .word 0x08011adf 8011a58: 08011b33 .word 0x08011b33 8011a5c: 08011b33 .word 0x08011b33 8011a60: 08011b33 .word 0x08011b33 8011a64: 08011aef .word 0x08011aef 8011a68: 08011b33 .word 0x08011b33 8011a6c: 08011b33 .word 0x08011b33 8011a70: 08011b33 .word 0x08011b33 8011a74: 08011b33 .word 0x08011b33 8011a78: 08011b33 .word 0x08011b33 8011a7c: 08011b33 .word 0x08011b33 8011a80: 08011b33 .word 0x08011b33 8011a84: 08011aff .word 0x08011aff 8011a88: 08011b33 .word 0x08011b33 8011a8c: 08011b33 .word 0x08011b33 8011a90: 08011b33 .word 0x08011b33 8011a94: 08011b33 .word 0x08011b33 8011a98: 08011b33 .word 0x08011b33 8011a9c: 08011b33 .word 0x08011b33 8011aa0: 08011b33 .word 0x08011b33 8011aa4: 08011b33 .word 0x08011b33 8011aa8: 08011b33 .word 0x08011b33 8011aac: 08011b33 .word 0x08011b33 8011ab0: 08011b33 .word 0x08011b33 8011ab4: 08011b33 .word 0x08011b33 8011ab8: 08011b33 .word 0x08011b33 8011abc: 08011b33 .word 0x08011b33 8011ac0: 08011b33 .word 0x08011b33 8011ac4: 08011b25 .word 0x08011b25 8011ac8: 2b40 cmp r3, #64 @ 0x40 8011aca: d02e beq.n 8011b2a 8011acc: e031 b.n 8011b32 { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8011ace: f7fa fd61 bl 800c594 8011ad2: 63f8 str r0, [r7, #60] @ 0x3c break; 8011ad4: e033 b.n 8011b3e case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8011ad6: f7fa fd73 bl 800c5c0 8011ada: 63f8 str r0, [r7, #60] @ 0x3c break; 8011adc: e02f b.n 8011b3e case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8011ade: f107 0324 add.w r3, r7, #36 @ 0x24 8011ae2: 4618 mov r0, r3 8011ae4: f7fc fd48 bl 800e578 pclk = pll2_clocks.PLL2_Q_Frequency; 8011ae8: 6abb ldr r3, [r7, #40] @ 0x28 8011aea: 63fb str r3, [r7, #60] @ 0x3c break; 8011aec: e027 b.n 8011b3e case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8011aee: f107 0318 add.w r3, r7, #24 8011af2: 4618 mov r0, r3 8011af4: f7fc fe94 bl 800e820 pclk = pll3_clocks.PLL3_Q_Frequency; 8011af8: 69fb ldr r3, [r7, #28] 8011afa: 63fb str r3, [r7, #60] @ 0x3c break; 8011afc: e01f b.n 8011b3e case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8011afe: 4b2d ldr r3, [pc, #180] @ (8011bb4 ) 8011b00: 681b ldr r3, [r3, #0] 8011b02: f003 0320 and.w r3, r3, #32 8011b06: 2b00 cmp r3, #0 8011b08: d009 beq.n 8011b1e { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8011b0a: 4b2a ldr r3, [pc, #168] @ (8011bb4 ) 8011b0c: 681b ldr r3, [r3, #0] 8011b0e: 08db lsrs r3, r3, #3 8011b10: f003 0303 and.w r3, r3, #3 8011b14: 4a24 ldr r2, [pc, #144] @ (8011ba8 ) 8011b16: fa22 f303 lsr.w r3, r2, r3 8011b1a: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8011b1c: e00f b.n 8011b3e pclk = (uint32_t) HSI_VALUE; 8011b1e: 4b22 ldr r3, [pc, #136] @ (8011ba8 ) 8011b20: 63fb str r3, [r7, #60] @ 0x3c break; 8011b22: e00c b.n 8011b3e case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 8011b24: 4b21 ldr r3, [pc, #132] @ (8011bac ) 8011b26: 63fb str r3, [r7, #60] @ 0x3c break; 8011b28: e009 b.n 8011b3e case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8011b2a: f44f 4300 mov.w r3, #32768 @ 0x8000 8011b2e: 63fb str r3, [r7, #60] @ 0x3c break; 8011b30: e005 b.n 8011b3e default: pclk = 0U; 8011b32: 2300 movs r3, #0 8011b34: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 8011b36: 2301 movs r3, #1 8011b38: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 8011b3c: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 8011b3e: 6bfb ldr r3, [r7, #60] @ 0x3c 8011b40: 2b00 cmp r3, #0 8011b42: f000 80e7 beq.w 8011d14 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8011b46: 697b ldr r3, [r7, #20] 8011b48: 6a5b ldr r3, [r3, #36] @ 0x24 8011b4a: 4a19 ldr r2, [pc, #100] @ (8011bb0 ) 8011b4c: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8011b50: 461a mov r2, r3 8011b52: 6bfb ldr r3, [r7, #60] @ 0x3c 8011b54: fbb3 f3f2 udiv r3, r3, r2 8011b58: 005a lsls r2, r3, #1 8011b5a: 697b ldr r3, [r7, #20] 8011b5c: 685b ldr r3, [r3, #4] 8011b5e: 085b lsrs r3, r3, #1 8011b60: 441a add r2, r3 8011b62: 697b ldr r3, [r7, #20] 8011b64: 685b ldr r3, [r3, #4] 8011b66: fbb2 f3f3 udiv r3, r2, r3 8011b6a: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8011b6c: 6bbb ldr r3, [r7, #56] @ 0x38 8011b6e: 2b0f cmp r3, #15 8011b70: d916 bls.n 8011ba0 8011b72: 6bbb ldr r3, [r7, #56] @ 0x38 8011b74: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8011b78: d212 bcs.n 8011ba0 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 8011b7a: 6bbb ldr r3, [r7, #56] @ 0x38 8011b7c: b29b uxth r3, r3 8011b7e: f023 030f bic.w r3, r3, #15 8011b82: 86fb strh r3, [r7, #54] @ 0x36 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8011b84: 6bbb ldr r3, [r7, #56] @ 0x38 8011b86: 085b lsrs r3, r3, #1 8011b88: b29b uxth r3, r3 8011b8a: f003 0307 and.w r3, r3, #7 8011b8e: b29a uxth r2, r3 8011b90: 8efb ldrh r3, [r7, #54] @ 0x36 8011b92: 4313 orrs r3, r2 8011b94: 86fb strh r3, [r7, #54] @ 0x36 huart->Instance->BRR = brrtemp; 8011b96: 697b ldr r3, [r7, #20] 8011b98: 681b ldr r3, [r3, #0] 8011b9a: 8efa ldrh r2, [r7, #54] @ 0x36 8011b9c: 60da str r2, [r3, #12] 8011b9e: e0b9 b.n 8011d14 } else { ret = HAL_ERROR; 8011ba0: 2301 movs r3, #1 8011ba2: f887 3042 strb.w r3, [r7, #66] @ 0x42 8011ba6: e0b5 b.n 8011d14 8011ba8: 03d09000 .word 0x03d09000 8011bac: 003d0900 .word 0x003d0900 8011bb0: 08018b74 .word 0x08018b74 8011bb4: 58024400 .word 0x58024400 } } } else { switch (clocksource) 8011bb8: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 8011bbc: 2b20 cmp r3, #32 8011bbe: dc49 bgt.n 8011c54 8011bc0: 2b00 cmp r3, #0 8011bc2: db7c blt.n 8011cbe 8011bc4: 2b20 cmp r3, #32 8011bc6: d87a bhi.n 8011cbe 8011bc8: a201 add r2, pc, #4 @ (adr r2, 8011bd0 ) 8011bca: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011bce: bf00 nop 8011bd0: 08011c5b .word 0x08011c5b 8011bd4: 08011c63 .word 0x08011c63 8011bd8: 08011cbf .word 0x08011cbf 8011bdc: 08011cbf .word 0x08011cbf 8011be0: 08011c6b .word 0x08011c6b 8011be4: 08011cbf .word 0x08011cbf 8011be8: 08011cbf .word 0x08011cbf 8011bec: 08011cbf .word 0x08011cbf 8011bf0: 08011c7b .word 0x08011c7b 8011bf4: 08011cbf .word 0x08011cbf 8011bf8: 08011cbf .word 0x08011cbf 8011bfc: 08011cbf .word 0x08011cbf 8011c00: 08011cbf .word 0x08011cbf 8011c04: 08011cbf .word 0x08011cbf 8011c08: 08011cbf .word 0x08011cbf 8011c0c: 08011cbf .word 0x08011cbf 8011c10: 08011c8b .word 0x08011c8b 8011c14: 08011cbf .word 0x08011cbf 8011c18: 08011cbf .word 0x08011cbf 8011c1c: 08011cbf .word 0x08011cbf 8011c20: 08011cbf .word 0x08011cbf 8011c24: 08011cbf .word 0x08011cbf 8011c28: 08011cbf .word 0x08011cbf 8011c2c: 08011cbf .word 0x08011cbf 8011c30: 08011cbf .word 0x08011cbf 8011c34: 08011cbf .word 0x08011cbf 8011c38: 08011cbf .word 0x08011cbf 8011c3c: 08011cbf .word 0x08011cbf 8011c40: 08011cbf .word 0x08011cbf 8011c44: 08011cbf .word 0x08011cbf 8011c48: 08011cbf .word 0x08011cbf 8011c4c: 08011cbf .word 0x08011cbf 8011c50: 08011cb1 .word 0x08011cb1 8011c54: 2b40 cmp r3, #64 @ 0x40 8011c56: d02e beq.n 8011cb6 8011c58: e031 b.n 8011cbe { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8011c5a: f7fa fc9b bl 800c594 8011c5e: 63f8 str r0, [r7, #60] @ 0x3c break; 8011c60: e033 b.n 8011cca case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8011c62: f7fa fcad bl 800c5c0 8011c66: 63f8 str r0, [r7, #60] @ 0x3c break; 8011c68: e02f b.n 8011cca case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8011c6a: f107 0324 add.w r3, r7, #36 @ 0x24 8011c6e: 4618 mov r0, r3 8011c70: f7fc fc82 bl 800e578 pclk = pll2_clocks.PLL2_Q_Frequency; 8011c74: 6abb ldr r3, [r7, #40] @ 0x28 8011c76: 63fb str r3, [r7, #60] @ 0x3c break; 8011c78: e027 b.n 8011cca case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8011c7a: f107 0318 add.w r3, r7, #24 8011c7e: 4618 mov r0, r3 8011c80: f7fc fdce bl 800e820 pclk = pll3_clocks.PLL3_Q_Frequency; 8011c84: 69fb ldr r3, [r7, #28] 8011c86: 63fb str r3, [r7, #60] @ 0x3c break; 8011c88: e01f b.n 8011cca case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8011c8a: 4b2d ldr r3, [pc, #180] @ (8011d40 ) 8011c8c: 681b ldr r3, [r3, #0] 8011c8e: f003 0320 and.w r3, r3, #32 8011c92: 2b00 cmp r3, #0 8011c94: d009 beq.n 8011caa { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8011c96: 4b2a ldr r3, [pc, #168] @ (8011d40 ) 8011c98: 681b ldr r3, [r3, #0] 8011c9a: 08db lsrs r3, r3, #3 8011c9c: f003 0303 and.w r3, r3, #3 8011ca0: 4a28 ldr r2, [pc, #160] @ (8011d44 ) 8011ca2: fa22 f303 lsr.w r3, r2, r3 8011ca6: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8011ca8: e00f b.n 8011cca pclk = (uint32_t) HSI_VALUE; 8011caa: 4b26 ldr r3, [pc, #152] @ (8011d44 ) 8011cac: 63fb str r3, [r7, #60] @ 0x3c break; 8011cae: e00c b.n 8011cca case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 8011cb0: 4b25 ldr r3, [pc, #148] @ (8011d48 ) 8011cb2: 63fb str r3, [r7, #60] @ 0x3c break; 8011cb4: e009 b.n 8011cca case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8011cb6: f44f 4300 mov.w r3, #32768 @ 0x8000 8011cba: 63fb str r3, [r7, #60] @ 0x3c break; 8011cbc: e005 b.n 8011cca default: pclk = 0U; 8011cbe: 2300 movs r3, #0 8011cc0: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 8011cc2: 2301 movs r3, #1 8011cc4: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 8011cc8: bf00 nop } if (pclk != 0U) 8011cca: 6bfb ldr r3, [r7, #60] @ 0x3c 8011ccc: 2b00 cmp r3, #0 8011cce: d021 beq.n 8011d14 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8011cd0: 697b ldr r3, [r7, #20] 8011cd2: 6a5b ldr r3, [r3, #36] @ 0x24 8011cd4: 4a1d ldr r2, [pc, #116] @ (8011d4c ) 8011cd6: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8011cda: 461a mov r2, r3 8011cdc: 6bfb ldr r3, [r7, #60] @ 0x3c 8011cde: fbb3 f2f2 udiv r2, r3, r2 8011ce2: 697b ldr r3, [r7, #20] 8011ce4: 685b ldr r3, [r3, #4] 8011ce6: 085b lsrs r3, r3, #1 8011ce8: 441a add r2, r3 8011cea: 697b ldr r3, [r7, #20] 8011cec: 685b ldr r3, [r3, #4] 8011cee: fbb2 f3f3 udiv r3, r2, r3 8011cf2: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8011cf4: 6bbb ldr r3, [r7, #56] @ 0x38 8011cf6: 2b0f cmp r3, #15 8011cf8: d909 bls.n 8011d0e 8011cfa: 6bbb ldr r3, [r7, #56] @ 0x38 8011cfc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8011d00: d205 bcs.n 8011d0e { huart->Instance->BRR = (uint16_t)usartdiv; 8011d02: 6bbb ldr r3, [r7, #56] @ 0x38 8011d04: b29a uxth r2, r3 8011d06: 697b ldr r3, [r7, #20] 8011d08: 681b ldr r3, [r3, #0] 8011d0a: 60da str r2, [r3, #12] 8011d0c: e002 b.n 8011d14 } else { ret = HAL_ERROR; 8011d0e: 2301 movs r3, #1 8011d10: f887 3042 strb.w r3, [r7, #66] @ 0x42 } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 8011d14: 697b ldr r3, [r7, #20] 8011d16: 2201 movs r2, #1 8011d18: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1; 8011d1c: 697b ldr r3, [r7, #20] 8011d1e: 2201 movs r2, #1 8011d20: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; 8011d24: 697b ldr r3, [r7, #20] 8011d26: 2200 movs r2, #0 8011d28: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 8011d2a: 697b ldr r3, [r7, #20] 8011d2c: 2200 movs r2, #0 8011d2e: 679a str r2, [r3, #120] @ 0x78 return ret; 8011d30: f897 3042 ldrb.w r3, [r7, #66] @ 0x42 } 8011d34: 4618 mov r0, r3 8011d36: 3748 adds r7, #72 @ 0x48 8011d38: 46bd mov sp, r7 8011d3a: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8011d3e: bf00 nop 8011d40: 58024400 .word 0x58024400 8011d44: 03d09000 .word 0x03d09000 8011d48: 003d0900 .word 0x003d0900 8011d4c: 08018b74 .word 0x08018b74 08011d50 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 8011d50: b480 push {r7} 8011d52: b083 sub sp, #12 8011d54: af00 add r7, sp, #0 8011d56: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 8011d58: 687b ldr r3, [r7, #4] 8011d5a: 6a9b ldr r3, [r3, #40] @ 0x28 8011d5c: f003 0308 and.w r3, r3, #8 8011d60: 2b00 cmp r3, #0 8011d62: d00a beq.n 8011d7a { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 8011d64: 687b ldr r3, [r7, #4] 8011d66: 681b ldr r3, [r3, #0] 8011d68: 685b ldr r3, [r3, #4] 8011d6a: f423 4100 bic.w r1, r3, #32768 @ 0x8000 8011d6e: 687b ldr r3, [r7, #4] 8011d70: 6b9a ldr r2, [r3, #56] @ 0x38 8011d72: 687b ldr r3, [r7, #4] 8011d74: 681b ldr r3, [r3, #0] 8011d76: 430a orrs r2, r1 8011d78: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 8011d7a: 687b ldr r3, [r7, #4] 8011d7c: 6a9b ldr r3, [r3, #40] @ 0x28 8011d7e: f003 0301 and.w r3, r3, #1 8011d82: 2b00 cmp r3, #0 8011d84: d00a beq.n 8011d9c { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 8011d86: 687b ldr r3, [r7, #4] 8011d88: 681b ldr r3, [r3, #0] 8011d8a: 685b ldr r3, [r3, #4] 8011d8c: f423 3100 bic.w r1, r3, #131072 @ 0x20000 8011d90: 687b ldr r3, [r7, #4] 8011d92: 6ada ldr r2, [r3, #44] @ 0x2c 8011d94: 687b ldr r3, [r7, #4] 8011d96: 681b ldr r3, [r3, #0] 8011d98: 430a orrs r2, r1 8011d9a: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 8011d9c: 687b ldr r3, [r7, #4] 8011d9e: 6a9b ldr r3, [r3, #40] @ 0x28 8011da0: f003 0302 and.w r3, r3, #2 8011da4: 2b00 cmp r3, #0 8011da6: d00a beq.n 8011dbe { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 8011da8: 687b ldr r3, [r7, #4] 8011daa: 681b ldr r3, [r3, #0] 8011dac: 685b ldr r3, [r3, #4] 8011dae: f423 3180 bic.w r1, r3, #65536 @ 0x10000 8011db2: 687b ldr r3, [r7, #4] 8011db4: 6b1a ldr r2, [r3, #48] @ 0x30 8011db6: 687b ldr r3, [r7, #4] 8011db8: 681b ldr r3, [r3, #0] 8011dba: 430a orrs r2, r1 8011dbc: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 8011dbe: 687b ldr r3, [r7, #4] 8011dc0: 6a9b ldr r3, [r3, #40] @ 0x28 8011dc2: f003 0304 and.w r3, r3, #4 8011dc6: 2b00 cmp r3, #0 8011dc8: d00a beq.n 8011de0 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 8011dca: 687b ldr r3, [r7, #4] 8011dcc: 681b ldr r3, [r3, #0] 8011dce: 685b ldr r3, [r3, #4] 8011dd0: f423 2180 bic.w r1, r3, #262144 @ 0x40000 8011dd4: 687b ldr r3, [r7, #4] 8011dd6: 6b5a ldr r2, [r3, #52] @ 0x34 8011dd8: 687b ldr r3, [r7, #4] 8011dda: 681b ldr r3, [r3, #0] 8011ddc: 430a orrs r2, r1 8011dde: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 8011de0: 687b ldr r3, [r7, #4] 8011de2: 6a9b ldr r3, [r3, #40] @ 0x28 8011de4: f003 0310 and.w r3, r3, #16 8011de8: 2b00 cmp r3, #0 8011dea: d00a beq.n 8011e02 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 8011dec: 687b ldr r3, [r7, #4] 8011dee: 681b ldr r3, [r3, #0] 8011df0: 689b ldr r3, [r3, #8] 8011df2: f423 5180 bic.w r1, r3, #4096 @ 0x1000 8011df6: 687b ldr r3, [r7, #4] 8011df8: 6bda ldr r2, [r3, #60] @ 0x3c 8011dfa: 687b ldr r3, [r7, #4] 8011dfc: 681b ldr r3, [r3, #0] 8011dfe: 430a orrs r2, r1 8011e00: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 8011e02: 687b ldr r3, [r7, #4] 8011e04: 6a9b ldr r3, [r3, #40] @ 0x28 8011e06: f003 0320 and.w r3, r3, #32 8011e0a: 2b00 cmp r3, #0 8011e0c: d00a beq.n 8011e24 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 8011e0e: 687b ldr r3, [r7, #4] 8011e10: 681b ldr r3, [r3, #0] 8011e12: 689b ldr r3, [r3, #8] 8011e14: f423 5100 bic.w r1, r3, #8192 @ 0x2000 8011e18: 687b ldr r3, [r7, #4] 8011e1a: 6c1a ldr r2, [r3, #64] @ 0x40 8011e1c: 687b ldr r3, [r7, #4] 8011e1e: 681b ldr r3, [r3, #0] 8011e20: 430a orrs r2, r1 8011e22: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 8011e24: 687b ldr r3, [r7, #4] 8011e26: 6a9b ldr r3, [r3, #40] @ 0x28 8011e28: f003 0340 and.w r3, r3, #64 @ 0x40 8011e2c: 2b00 cmp r3, #0 8011e2e: d01a beq.n 8011e66 { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 8011e30: 687b ldr r3, [r7, #4] 8011e32: 681b ldr r3, [r3, #0] 8011e34: 685b ldr r3, [r3, #4] 8011e36: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 8011e3a: 687b ldr r3, [r7, #4] 8011e3c: 6c5a ldr r2, [r3, #68] @ 0x44 8011e3e: 687b ldr r3, [r7, #4] 8011e40: 681b ldr r3, [r3, #0] 8011e42: 430a orrs r2, r1 8011e44: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 8011e46: 687b ldr r3, [r7, #4] 8011e48: 6c5b ldr r3, [r3, #68] @ 0x44 8011e4a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8011e4e: d10a bne.n 8011e66 { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 8011e50: 687b ldr r3, [r7, #4] 8011e52: 681b ldr r3, [r3, #0] 8011e54: 685b ldr r3, [r3, #4] 8011e56: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 8011e5a: 687b ldr r3, [r7, #4] 8011e5c: 6c9a ldr r2, [r3, #72] @ 0x48 8011e5e: 687b ldr r3, [r7, #4] 8011e60: 681b ldr r3, [r3, #0] 8011e62: 430a orrs r2, r1 8011e64: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 8011e66: 687b ldr r3, [r7, #4] 8011e68: 6a9b ldr r3, [r3, #40] @ 0x28 8011e6a: f003 0380 and.w r3, r3, #128 @ 0x80 8011e6e: 2b00 cmp r3, #0 8011e70: d00a beq.n 8011e88 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 8011e72: 687b ldr r3, [r7, #4] 8011e74: 681b ldr r3, [r3, #0] 8011e76: 685b ldr r3, [r3, #4] 8011e78: f423 2100 bic.w r1, r3, #524288 @ 0x80000 8011e7c: 687b ldr r3, [r7, #4] 8011e7e: 6cda ldr r2, [r3, #76] @ 0x4c 8011e80: 687b ldr r3, [r7, #4] 8011e82: 681b ldr r3, [r3, #0] 8011e84: 430a orrs r2, r1 8011e86: 605a str r2, [r3, #4] } } 8011e88: bf00 nop 8011e8a: 370c adds r7, #12 8011e8c: 46bd mov sp, r7 8011e8e: f85d 7b04 ldr.w r7, [sp], #4 8011e92: 4770 bx lr 08011e94 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 8011e94: b580 push {r7, lr} 8011e96: b098 sub sp, #96 @ 0x60 8011e98: af02 add r7, sp, #8 8011e9a: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8011e9c: 687b ldr r3, [r7, #4] 8011e9e: 2200 movs r2, #0 8011ea0: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8011ea4: f7f3 fe84 bl 8005bb0 8011ea8: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 8011eaa: 687b ldr r3, [r7, #4] 8011eac: 681b ldr r3, [r3, #0] 8011eae: 681b ldr r3, [r3, #0] 8011eb0: f003 0308 and.w r3, r3, #8 8011eb4: 2b08 cmp r3, #8 8011eb6: d12f bne.n 8011f18 { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8011eb8: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8011ebc: 9300 str r3, [sp, #0] 8011ebe: 6d7b ldr r3, [r7, #84] @ 0x54 8011ec0: 2200 movs r2, #0 8011ec2: f44f 1100 mov.w r1, #2097152 @ 0x200000 8011ec6: 6878 ldr r0, [r7, #4] 8011ec8: f000 f88e bl 8011fe8 8011ecc: 4603 mov r3, r0 8011ece: 2b00 cmp r3, #0 8011ed0: d022 beq.n 8011f18 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 8011ed2: 687b ldr r3, [r7, #4] 8011ed4: 681b ldr r3, [r3, #0] 8011ed6: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011ed8: 6bbb ldr r3, [r7, #56] @ 0x38 8011eda: e853 3f00 ldrex r3, [r3] 8011ede: 637b str r3, [r7, #52] @ 0x34 return(result); 8011ee0: 6b7b ldr r3, [r7, #52] @ 0x34 8011ee2: f023 0380 bic.w r3, r3, #128 @ 0x80 8011ee6: 653b str r3, [r7, #80] @ 0x50 8011ee8: 687b ldr r3, [r7, #4] 8011eea: 681b ldr r3, [r3, #0] 8011eec: 461a mov r2, r3 8011eee: 6d3b ldr r3, [r7, #80] @ 0x50 8011ef0: 647b str r3, [r7, #68] @ 0x44 8011ef2: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011ef4: 6c39 ldr r1, [r7, #64] @ 0x40 8011ef6: 6c7a ldr r2, [r7, #68] @ 0x44 8011ef8: e841 2300 strex r3, r2, [r1] 8011efc: 63fb str r3, [r7, #60] @ 0x3c return(result); 8011efe: 6bfb ldr r3, [r7, #60] @ 0x3c 8011f00: 2b00 cmp r3, #0 8011f02: d1e6 bne.n 8011ed2 huart->gState = HAL_UART_STATE_READY; 8011f04: 687b ldr r3, [r7, #4] 8011f06: 2220 movs r2, #32 8011f08: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); 8011f0c: 687b ldr r3, [r7, #4] 8011f0e: 2200 movs r2, #0 8011f10: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8011f14: 2303 movs r3, #3 8011f16: e063 b.n 8011fe0 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 8011f18: 687b ldr r3, [r7, #4] 8011f1a: 681b ldr r3, [r3, #0] 8011f1c: 681b ldr r3, [r3, #0] 8011f1e: f003 0304 and.w r3, r3, #4 8011f22: 2b04 cmp r3, #4 8011f24: d149 bne.n 8011fba { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8011f26: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8011f2a: 9300 str r3, [sp, #0] 8011f2c: 6d7b ldr r3, [r7, #84] @ 0x54 8011f2e: 2200 movs r2, #0 8011f30: f44f 0180 mov.w r1, #4194304 @ 0x400000 8011f34: 6878 ldr r0, [r7, #4] 8011f36: f000 f857 bl 8011fe8 8011f3a: 4603 mov r3, r0 8011f3c: 2b00 cmp r3, #0 8011f3e: d03c beq.n 8011fba { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8011f40: 687b ldr r3, [r7, #4] 8011f42: 681b ldr r3, [r3, #0] 8011f44: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011f46: 6a7b ldr r3, [r7, #36] @ 0x24 8011f48: e853 3f00 ldrex r3, [r3] 8011f4c: 623b str r3, [r7, #32] return(result); 8011f4e: 6a3b ldr r3, [r7, #32] 8011f50: f423 7390 bic.w r3, r3, #288 @ 0x120 8011f54: 64fb str r3, [r7, #76] @ 0x4c 8011f56: 687b ldr r3, [r7, #4] 8011f58: 681b ldr r3, [r3, #0] 8011f5a: 461a mov r2, r3 8011f5c: 6cfb ldr r3, [r7, #76] @ 0x4c 8011f5e: 633b str r3, [r7, #48] @ 0x30 8011f60: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011f62: 6af9 ldr r1, [r7, #44] @ 0x2c 8011f64: 6b3a ldr r2, [r7, #48] @ 0x30 8011f66: e841 2300 strex r3, r2, [r1] 8011f6a: 62bb str r3, [r7, #40] @ 0x28 return(result); 8011f6c: 6abb ldr r3, [r7, #40] @ 0x28 8011f6e: 2b00 cmp r3, #0 8011f70: d1e6 bne.n 8011f40 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8011f72: 687b ldr r3, [r7, #4] 8011f74: 681b ldr r3, [r3, #0] 8011f76: 3308 adds r3, #8 8011f78: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011f7a: 693b ldr r3, [r7, #16] 8011f7c: e853 3f00 ldrex r3, [r3] 8011f80: 60fb str r3, [r7, #12] return(result); 8011f82: 68fb ldr r3, [r7, #12] 8011f84: f023 0301 bic.w r3, r3, #1 8011f88: 64bb str r3, [r7, #72] @ 0x48 8011f8a: 687b ldr r3, [r7, #4] 8011f8c: 681b ldr r3, [r3, #0] 8011f8e: 3308 adds r3, #8 8011f90: 6cba ldr r2, [r7, #72] @ 0x48 8011f92: 61fa str r2, [r7, #28] 8011f94: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011f96: 69b9 ldr r1, [r7, #24] 8011f98: 69fa ldr r2, [r7, #28] 8011f9a: e841 2300 strex r3, r2, [r1] 8011f9e: 617b str r3, [r7, #20] return(result); 8011fa0: 697b ldr r3, [r7, #20] 8011fa2: 2b00 cmp r3, #0 8011fa4: d1e5 bne.n 8011f72 huart->RxState = HAL_UART_STATE_READY; 8011fa6: 687b ldr r3, [r7, #4] 8011fa8: 2220 movs r2, #32 8011faa: f8c3 208c str.w r2, [r3, #140] @ 0x8c __HAL_UNLOCK(huart); 8011fae: 687b ldr r3, [r7, #4] 8011fb0: 2200 movs r2, #0 8011fb2: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8011fb6: 2303 movs r3, #3 8011fb8: e012 b.n 8011fe0 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 8011fba: 687b ldr r3, [r7, #4] 8011fbc: 2220 movs r2, #32 8011fbe: f8c3 2088 str.w r2, [r3, #136] @ 0x88 huart->RxState = HAL_UART_STATE_READY; 8011fc2: 687b ldr r3, [r7, #4] 8011fc4: 2220 movs r2, #32 8011fc6: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8011fca: 687b ldr r3, [r7, #4] 8011fcc: 2200 movs r2, #0 8011fce: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8011fd0: 687b ldr r3, [r7, #4] 8011fd2: 2200 movs r2, #0 8011fd4: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 8011fd6: 687b ldr r3, [r7, #4] 8011fd8: 2200 movs r2, #0 8011fda: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8011fde: 2300 movs r3, #0 } 8011fe0: 4618 mov r0, r3 8011fe2: 3758 adds r7, #88 @ 0x58 8011fe4: 46bd mov sp, r7 8011fe6: bd80 pop {r7, pc} 08011fe8 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8011fe8: b580 push {r7, lr} 8011fea: b084 sub sp, #16 8011fec: af00 add r7, sp, #0 8011fee: 60f8 str r0, [r7, #12] 8011ff0: 60b9 str r1, [r7, #8] 8011ff2: 603b str r3, [r7, #0] 8011ff4: 4613 mov r3, r2 8011ff6: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8011ff8: e04f b.n 801209a { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8011ffa: 69bb ldr r3, [r7, #24] 8011ffc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8012000: d04b beq.n 801209a { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8012002: f7f3 fdd5 bl 8005bb0 8012006: 4602 mov r2, r0 8012008: 683b ldr r3, [r7, #0] 801200a: 1ad3 subs r3, r2, r3 801200c: 69ba ldr r2, [r7, #24] 801200e: 429a cmp r2, r3 8012010: d302 bcc.n 8012018 8012012: 69bb ldr r3, [r7, #24] 8012014: 2b00 cmp r3, #0 8012016: d101 bne.n 801201c { return HAL_TIMEOUT; 8012018: 2303 movs r3, #3 801201a: e04e b.n 80120ba } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 801201c: 68fb ldr r3, [r7, #12] 801201e: 681b ldr r3, [r3, #0] 8012020: 681b ldr r3, [r3, #0] 8012022: f003 0304 and.w r3, r3, #4 8012026: 2b00 cmp r3, #0 8012028: d037 beq.n 801209a 801202a: 68bb ldr r3, [r7, #8] 801202c: 2b80 cmp r3, #128 @ 0x80 801202e: d034 beq.n 801209a 8012030: 68bb ldr r3, [r7, #8] 8012032: 2b40 cmp r3, #64 @ 0x40 8012034: d031 beq.n 801209a { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8012036: 68fb ldr r3, [r7, #12] 8012038: 681b ldr r3, [r3, #0] 801203a: 69db ldr r3, [r3, #28] 801203c: f003 0308 and.w r3, r3, #8 8012040: 2b08 cmp r3, #8 8012042: d110 bne.n 8012066 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8012044: 68fb ldr r3, [r7, #12] 8012046: 681b ldr r3, [r3, #0] 8012048: 2208 movs r2, #8 801204a: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 801204c: 68f8 ldr r0, [r7, #12] 801204e: f000 f95b bl 8012308 huart->ErrorCode = HAL_UART_ERROR_ORE; 8012052: 68fb ldr r3, [r7, #12] 8012054: 2208 movs r2, #8 8012056: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 801205a: 68fb ldr r3, [r7, #12] 801205c: 2200 movs r2, #0 801205e: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_ERROR; 8012062: 2301 movs r3, #1 8012064: e029 b.n 80120ba } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8012066: 68fb ldr r3, [r7, #12] 8012068: 681b ldr r3, [r3, #0] 801206a: 69db ldr r3, [r3, #28] 801206c: f403 6300 and.w r3, r3, #2048 @ 0x800 8012070: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8012074: d111 bne.n 801209a { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8012076: 68fb ldr r3, [r7, #12] 8012078: 681b ldr r3, [r3, #0] 801207a: f44f 6200 mov.w r2, #2048 @ 0x800 801207e: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8012080: 68f8 ldr r0, [r7, #12] 8012082: f000 f941 bl 8012308 huart->ErrorCode = HAL_UART_ERROR_RTO; 8012086: 68fb ldr r3, [r7, #12] 8012088: 2220 movs r2, #32 801208a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 801208e: 68fb ldr r3, [r7, #12] 8012090: 2200 movs r2, #0 8012092: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_TIMEOUT; 8012096: 2303 movs r3, #3 8012098: e00f b.n 80120ba while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 801209a: 68fb ldr r3, [r7, #12] 801209c: 681b ldr r3, [r3, #0] 801209e: 69da ldr r2, [r3, #28] 80120a0: 68bb ldr r3, [r7, #8] 80120a2: 4013 ands r3, r2 80120a4: 68ba ldr r2, [r7, #8] 80120a6: 429a cmp r2, r3 80120a8: bf0c ite eq 80120aa: 2301 moveq r3, #1 80120ac: 2300 movne r3, #0 80120ae: b2db uxtb r3, r3 80120b0: 461a mov r2, r3 80120b2: 79fb ldrb r3, [r7, #7] 80120b4: 429a cmp r2, r3 80120b6: d0a0 beq.n 8011ffa } } } } return HAL_OK; 80120b8: 2300 movs r3, #0 } 80120ba: 4618 mov r0, r3 80120bc: 3710 adds r7, #16 80120be: 46bd mov sp, r7 80120c0: bd80 pop {r7, pc} ... 080120c4 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80120c4: b480 push {r7} 80120c6: b0a3 sub sp, #140 @ 0x8c 80120c8: af00 add r7, sp, #0 80120ca: 60f8 str r0, [r7, #12] 80120cc: 60b9 str r1, [r7, #8] 80120ce: 4613 mov r3, r2 80120d0: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 80120d2: 68fb ldr r3, [r7, #12] 80120d4: 68ba ldr r2, [r7, #8] 80120d6: 659a str r2, [r3, #88] @ 0x58 huart->RxXferSize = Size; 80120d8: 68fb ldr r3, [r7, #12] 80120da: 88fa ldrh r2, [r7, #6] 80120dc: f8a3 205c strh.w r2, [r3, #92] @ 0x5c huart->RxXferCount = Size; 80120e0: 68fb ldr r3, [r7, #12] 80120e2: 88fa ldrh r2, [r7, #6] 80120e4: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->RxISR = NULL; 80120e8: 68fb ldr r3, [r7, #12] 80120ea: 2200 movs r2, #0 80120ec: 675a str r2, [r3, #116] @ 0x74 /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); 80120ee: 68fb ldr r3, [r7, #12] 80120f0: 689b ldr r3, [r3, #8] 80120f2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80120f6: d10e bne.n 8012116 80120f8: 68fb ldr r3, [r7, #12] 80120fa: 691b ldr r3, [r3, #16] 80120fc: 2b00 cmp r3, #0 80120fe: d105 bne.n 801210c 8012100: 68fb ldr r3, [r7, #12] 8012102: f240 12ff movw r2, #511 @ 0x1ff 8012106: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 801210a: e02d b.n 8012168 801210c: 68fb ldr r3, [r7, #12] 801210e: 22ff movs r2, #255 @ 0xff 8012110: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012114: e028 b.n 8012168 8012116: 68fb ldr r3, [r7, #12] 8012118: 689b ldr r3, [r3, #8] 801211a: 2b00 cmp r3, #0 801211c: d10d bne.n 801213a 801211e: 68fb ldr r3, [r7, #12] 8012120: 691b ldr r3, [r3, #16] 8012122: 2b00 cmp r3, #0 8012124: d104 bne.n 8012130 8012126: 68fb ldr r3, [r7, #12] 8012128: 22ff movs r2, #255 @ 0xff 801212a: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 801212e: e01b b.n 8012168 8012130: 68fb ldr r3, [r7, #12] 8012132: 227f movs r2, #127 @ 0x7f 8012134: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012138: e016 b.n 8012168 801213a: 68fb ldr r3, [r7, #12] 801213c: 689b ldr r3, [r3, #8] 801213e: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8012142: d10d bne.n 8012160 8012144: 68fb ldr r3, [r7, #12] 8012146: 691b ldr r3, [r3, #16] 8012148: 2b00 cmp r3, #0 801214a: d104 bne.n 8012156 801214c: 68fb ldr r3, [r7, #12] 801214e: 227f movs r2, #127 @ 0x7f 8012150: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012154: e008 b.n 8012168 8012156: 68fb ldr r3, [r7, #12] 8012158: 223f movs r2, #63 @ 0x3f 801215a: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 801215e: e003 b.n 8012168 8012160: 68fb ldr r3, [r7, #12] 8012162: 2200 movs r2, #0 8012164: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 huart->ErrorCode = HAL_UART_ERROR_NONE; 8012168: 68fb ldr r3, [r7, #12] 801216a: 2200 movs r2, #0 801216c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->RxState = HAL_UART_STATE_BUSY_RX; 8012170: 68fb ldr r3, [r7, #12] 8012172: 2222 movs r2, #34 @ 0x22 8012174: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012178: 68fb ldr r3, [r7, #12] 801217a: 681b ldr r3, [r3, #0] 801217c: 3308 adds r3, #8 801217e: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012180: 6e7b ldr r3, [r7, #100] @ 0x64 8012182: e853 3f00 ldrex r3, [r3] 8012186: 663b str r3, [r7, #96] @ 0x60 return(result); 8012188: 6e3b ldr r3, [r7, #96] @ 0x60 801218a: f043 0301 orr.w r3, r3, #1 801218e: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8012192: 68fb ldr r3, [r7, #12] 8012194: 681b ldr r3, [r3, #0] 8012196: 3308 adds r3, #8 8012198: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 801219c: 673a str r2, [r7, #112] @ 0x70 801219e: 66fb str r3, [r7, #108] @ 0x6c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80121a0: 6ef9 ldr r1, [r7, #108] @ 0x6c 80121a2: 6f3a ldr r2, [r7, #112] @ 0x70 80121a4: e841 2300 strex r3, r2, [r1] 80121a8: 66bb str r3, [r7, #104] @ 0x68 return(result); 80121aa: 6ebb ldr r3, [r7, #104] @ 0x68 80121ac: 2b00 cmp r3, #0 80121ae: d1e3 bne.n 8012178 /* Configure Rx interrupt processing */ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) 80121b0: 68fb ldr r3, [r7, #12] 80121b2: 6e5b ldr r3, [r3, #100] @ 0x64 80121b4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80121b8: d14f bne.n 801225a 80121ba: 68fb ldr r3, [r7, #12] 80121bc: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 80121c0: 88fa ldrh r2, [r7, #6] 80121c2: 429a cmp r2, r3 80121c4: d349 bcc.n 801225a { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80121c6: 68fb ldr r3, [r7, #12] 80121c8: 689b ldr r3, [r3, #8] 80121ca: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80121ce: d107 bne.n 80121e0 80121d0: 68fb ldr r3, [r7, #12] 80121d2: 691b ldr r3, [r3, #16] 80121d4: 2b00 cmp r3, #0 80121d6: d103 bne.n 80121e0 { huart->RxISR = UART_RxISR_16BIT_FIFOEN; 80121d8: 68fb ldr r3, [r7, #12] 80121da: 4a47 ldr r2, [pc, #284] @ (80122f8 ) 80121dc: 675a str r2, [r3, #116] @ 0x74 80121de: e002 b.n 80121e6 } else { huart->RxISR = UART_RxISR_8BIT_FIFOEN; 80121e0: 68fb ldr r3, [r7, #12] 80121e2: 4a46 ldr r2, [pc, #280] @ (80122fc ) 80121e4: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 80121e6: 68fb ldr r3, [r7, #12] 80121e8: 691b ldr r3, [r3, #16] 80121ea: 2b00 cmp r3, #0 80121ec: d01a beq.n 8012224 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80121ee: 68fb ldr r3, [r7, #12] 80121f0: 681b ldr r3, [r3, #0] 80121f2: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80121f4: 6d3b ldr r3, [r7, #80] @ 0x50 80121f6: e853 3f00 ldrex r3, [r3] 80121fa: 64fb str r3, [r7, #76] @ 0x4c return(result); 80121fc: 6cfb ldr r3, [r7, #76] @ 0x4c 80121fe: f443 7380 orr.w r3, r3, #256 @ 0x100 8012202: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8012206: 68fb ldr r3, [r7, #12] 8012208: 681b ldr r3, [r3, #0] 801220a: 461a mov r2, r3 801220c: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8012210: 65fb str r3, [r7, #92] @ 0x5c 8012212: 65ba str r2, [r7, #88] @ 0x58 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012214: 6db9 ldr r1, [r7, #88] @ 0x58 8012216: 6dfa ldr r2, [r7, #92] @ 0x5c 8012218: e841 2300 strex r3, r2, [r1] 801221c: 657b str r3, [r7, #84] @ 0x54 return(result); 801221e: 6d7b ldr r3, [r7, #84] @ 0x54 8012220: 2b00 cmp r3, #0 8012222: d1e4 bne.n 80121ee } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8012224: 68fb ldr r3, [r7, #12] 8012226: 681b ldr r3, [r3, #0] 8012228: 3308 adds r3, #8 801222a: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801222c: 6bfb ldr r3, [r7, #60] @ 0x3c 801222e: e853 3f00 ldrex r3, [r3] 8012232: 63bb str r3, [r7, #56] @ 0x38 return(result); 8012234: 6bbb ldr r3, [r7, #56] @ 0x38 8012236: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 801223a: 67fb str r3, [r7, #124] @ 0x7c 801223c: 68fb ldr r3, [r7, #12] 801223e: 681b ldr r3, [r3, #0] 8012240: 3308 adds r3, #8 8012242: 6ffa ldr r2, [r7, #124] @ 0x7c 8012244: 64ba str r2, [r7, #72] @ 0x48 8012246: 647b str r3, [r7, #68] @ 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012248: 6c79 ldr r1, [r7, #68] @ 0x44 801224a: 6cba ldr r2, [r7, #72] @ 0x48 801224c: e841 2300 strex r3, r2, [r1] 8012250: 643b str r3, [r7, #64] @ 0x40 return(result); 8012252: 6c3b ldr r3, [r7, #64] @ 0x40 8012254: 2b00 cmp r3, #0 8012256: d1e5 bne.n 8012224 8012258: e046 b.n 80122e8 } else { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 801225a: 68fb ldr r3, [r7, #12] 801225c: 689b ldr r3, [r3, #8] 801225e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012262: d107 bne.n 8012274 8012264: 68fb ldr r3, [r7, #12] 8012266: 691b ldr r3, [r3, #16] 8012268: 2b00 cmp r3, #0 801226a: d103 bne.n 8012274 { huart->RxISR = UART_RxISR_16BIT; 801226c: 68fb ldr r3, [r7, #12] 801226e: 4a24 ldr r2, [pc, #144] @ (8012300 ) 8012270: 675a str r2, [r3, #116] @ 0x74 8012272: e002 b.n 801227a } else { huart->RxISR = UART_RxISR_8BIT; 8012274: 68fb ldr r3, [r7, #12] 8012276: 4a23 ldr r2, [pc, #140] @ (8012304 ) 8012278: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 801227a: 68fb ldr r3, [r7, #12] 801227c: 691b ldr r3, [r3, #16] 801227e: 2b00 cmp r3, #0 8012280: d019 beq.n 80122b6 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); 8012282: 68fb ldr r3, [r7, #12] 8012284: 681b ldr r3, [r3, #0] 8012286: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012288: 6abb ldr r3, [r7, #40] @ 0x28 801228a: e853 3f00 ldrex r3, [r3] 801228e: 627b str r3, [r7, #36] @ 0x24 return(result); 8012290: 6a7b ldr r3, [r7, #36] @ 0x24 8012292: f443 7390 orr.w r3, r3, #288 @ 0x120 8012296: 677b str r3, [r7, #116] @ 0x74 8012298: 68fb ldr r3, [r7, #12] 801229a: 681b ldr r3, [r3, #0] 801229c: 461a mov r2, r3 801229e: 6f7b ldr r3, [r7, #116] @ 0x74 80122a0: 637b str r3, [r7, #52] @ 0x34 80122a2: 633a str r2, [r7, #48] @ 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80122a4: 6b39 ldr r1, [r7, #48] @ 0x30 80122a6: 6b7a ldr r2, [r7, #52] @ 0x34 80122a8: e841 2300 strex r3, r2, [r1] 80122ac: 62fb str r3, [r7, #44] @ 0x2c return(result); 80122ae: 6afb ldr r3, [r7, #44] @ 0x2c 80122b0: 2b00 cmp r3, #0 80122b2: d1e6 bne.n 8012282 80122b4: e018 b.n 80122e8 } else { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 80122b6: 68fb ldr r3, [r7, #12] 80122b8: 681b ldr r3, [r3, #0] 80122ba: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80122bc: 697b ldr r3, [r7, #20] 80122be: e853 3f00 ldrex r3, [r3] 80122c2: 613b str r3, [r7, #16] return(result); 80122c4: 693b ldr r3, [r7, #16] 80122c6: f043 0320 orr.w r3, r3, #32 80122ca: 67bb str r3, [r7, #120] @ 0x78 80122cc: 68fb ldr r3, [r7, #12] 80122ce: 681b ldr r3, [r3, #0] 80122d0: 461a mov r2, r3 80122d2: 6fbb ldr r3, [r7, #120] @ 0x78 80122d4: 623b str r3, [r7, #32] 80122d6: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80122d8: 69f9 ldr r1, [r7, #28] 80122da: 6a3a ldr r2, [r7, #32] 80122dc: e841 2300 strex r3, r2, [r1] 80122e0: 61bb str r3, [r7, #24] return(result); 80122e2: 69bb ldr r3, [r7, #24] 80122e4: 2b00 cmp r3, #0 80122e6: d1e6 bne.n 80122b6 } } return HAL_OK; 80122e8: 2300 movs r3, #0 } 80122ea: 4618 mov r0, r3 80122ec: 378c adds r7, #140 @ 0x8c 80122ee: 46bd mov sp, r7 80122f0: f85d 7b04 ldr.w r7, [sp], #4 80122f4: 4770 bx lr 80122f6: bf00 nop 80122f8: 08012e6d .word 0x08012e6d 80122fc: 08012b0d .word 0x08012b0d 8012300: 08012955 .word 0x08012955 8012304: 0801279d .word 0x0801279d 08012308 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8012308: b480 push {r7} 801230a: b095 sub sp, #84 @ 0x54 801230c: af00 add r7, sp, #0 801230e: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8012310: 687b ldr r3, [r7, #4] 8012312: 681b ldr r3, [r3, #0] 8012314: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012316: 6b7b ldr r3, [r7, #52] @ 0x34 8012318: e853 3f00 ldrex r3, [r3] 801231c: 633b str r3, [r7, #48] @ 0x30 return(result); 801231e: 6b3b ldr r3, [r7, #48] @ 0x30 8012320: f423 7390 bic.w r3, r3, #288 @ 0x120 8012324: 64fb str r3, [r7, #76] @ 0x4c 8012326: 687b ldr r3, [r7, #4] 8012328: 681b ldr r3, [r3, #0] 801232a: 461a mov r2, r3 801232c: 6cfb ldr r3, [r7, #76] @ 0x4c 801232e: 643b str r3, [r7, #64] @ 0x40 8012330: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012332: 6bf9 ldr r1, [r7, #60] @ 0x3c 8012334: 6c3a ldr r2, [r7, #64] @ 0x40 8012336: e841 2300 strex r3, r2, [r1] 801233a: 63bb str r3, [r7, #56] @ 0x38 return(result); 801233c: 6bbb ldr r3, [r7, #56] @ 0x38 801233e: 2b00 cmp r3, #0 8012340: d1e6 bne.n 8012310 ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8012342: 687b ldr r3, [r7, #4] 8012344: 681b ldr r3, [r3, #0] 8012346: 3308 adds r3, #8 8012348: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801234a: 6a3b ldr r3, [r7, #32] 801234c: e853 3f00 ldrex r3, [r3] 8012350: 61fb str r3, [r7, #28] return(result); 8012352: 69fa ldr r2, [r7, #28] 8012354: 4b1e ldr r3, [pc, #120] @ (80123d0 ) 8012356: 4013 ands r3, r2 8012358: 64bb str r3, [r7, #72] @ 0x48 801235a: 687b ldr r3, [r7, #4] 801235c: 681b ldr r3, [r3, #0] 801235e: 3308 adds r3, #8 8012360: 6cba ldr r2, [r7, #72] @ 0x48 8012362: 62fa str r2, [r7, #44] @ 0x2c 8012364: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012366: 6ab9 ldr r1, [r7, #40] @ 0x28 8012368: 6afa ldr r2, [r7, #44] @ 0x2c 801236a: e841 2300 strex r3, r2, [r1] 801236e: 627b str r3, [r7, #36] @ 0x24 return(result); 8012370: 6a7b ldr r3, [r7, #36] @ 0x24 8012372: 2b00 cmp r3, #0 8012374: d1e5 bne.n 8012342 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012376: 687b ldr r3, [r7, #4] 8012378: 6edb ldr r3, [r3, #108] @ 0x6c 801237a: 2b01 cmp r3, #1 801237c: d118 bne.n 80123b0 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801237e: 687b ldr r3, [r7, #4] 8012380: 681b ldr r3, [r3, #0] 8012382: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012384: 68fb ldr r3, [r7, #12] 8012386: e853 3f00 ldrex r3, [r3] 801238a: 60bb str r3, [r7, #8] return(result); 801238c: 68bb ldr r3, [r7, #8] 801238e: f023 0310 bic.w r3, r3, #16 8012392: 647b str r3, [r7, #68] @ 0x44 8012394: 687b ldr r3, [r7, #4] 8012396: 681b ldr r3, [r3, #0] 8012398: 461a mov r2, r3 801239a: 6c7b ldr r3, [r7, #68] @ 0x44 801239c: 61bb str r3, [r7, #24] 801239e: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80123a0: 6979 ldr r1, [r7, #20] 80123a2: 69ba ldr r2, [r7, #24] 80123a4: e841 2300 strex r3, r2, [r1] 80123a8: 613b str r3, [r7, #16] return(result); 80123aa: 693b ldr r3, [r7, #16] 80123ac: 2b00 cmp r3, #0 80123ae: d1e6 bne.n 801237e } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80123b0: 687b ldr r3, [r7, #4] 80123b2: 2220 movs r2, #32 80123b4: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80123b8: 687b ldr r3, [r7, #4] 80123ba: 2200 movs r2, #0 80123bc: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 80123be: 687b ldr r3, [r7, #4] 80123c0: 2200 movs r2, #0 80123c2: 675a str r2, [r3, #116] @ 0x74 } 80123c4: bf00 nop 80123c6: 3754 adds r7, #84 @ 0x54 80123c8: 46bd mov sp, r7 80123ca: f85d 7b04 ldr.w r7, [sp], #4 80123ce: 4770 bx lr 80123d0: effffffe .word 0xeffffffe 080123d4 : * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 80123d4: b580 push {r7, lr} 80123d6: b084 sub sp, #16 80123d8: af00 add r7, sp, #0 80123da: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 80123dc: 687b ldr r3, [r7, #4] 80123de: 6b9b ldr r3, [r3, #56] @ 0x38 80123e0: 60fb str r3, [r7, #12] huart->RxXferCount = 0U; 80123e2: 68fb ldr r3, [r7, #12] 80123e4: 2200 movs r2, #0 80123e6: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->TxXferCount = 0U; 80123ea: 68fb ldr r3, [r7, #12] 80123ec: 2200 movs r2, #0 80123ee: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80123f2: 68f8 ldr r0, [r7, #12] 80123f4: f7fe ff3a bl 801126c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80123f8: bf00 nop 80123fa: 3710 adds r7, #16 80123fc: 46bd mov sp, r7 80123fe: bd80 pop {r7, pc} 08012400 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) { 8012400: b480 push {r7} 8012402: b08f sub sp, #60 @ 0x3c 8012404: af00 add r7, sp, #0 8012406: 6078 str r0, [r7, #4] /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8012408: 687b ldr r3, [r7, #4] 801240a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 801240e: 2b21 cmp r3, #33 @ 0x21 8012410: d14c bne.n 80124ac { if (huart->TxXferCount == 0U) 8012412: 687b ldr r3, [r7, #4] 8012414: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012418: b29b uxth r3, r3 801241a: 2b00 cmp r3, #0 801241c: d132 bne.n 8012484 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 801241e: 687b ldr r3, [r7, #4] 8012420: 681b ldr r3, [r3, #0] 8012422: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012424: 6a3b ldr r3, [r7, #32] 8012426: e853 3f00 ldrex r3, [r3] 801242a: 61fb str r3, [r7, #28] return(result); 801242c: 69fb ldr r3, [r7, #28] 801242e: f023 0380 bic.w r3, r3, #128 @ 0x80 8012432: 637b str r3, [r7, #52] @ 0x34 8012434: 687b ldr r3, [r7, #4] 8012436: 681b ldr r3, [r3, #0] 8012438: 461a mov r2, r3 801243a: 6b7b ldr r3, [r7, #52] @ 0x34 801243c: 62fb str r3, [r7, #44] @ 0x2c 801243e: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012440: 6ab9 ldr r1, [r7, #40] @ 0x28 8012442: 6afa ldr r2, [r7, #44] @ 0x2c 8012444: e841 2300 strex r3, r2, [r1] 8012448: 627b str r3, [r7, #36] @ 0x24 return(result); 801244a: 6a7b ldr r3, [r7, #36] @ 0x24 801244c: 2b00 cmp r3, #0 801244e: d1e6 bne.n 801241e /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8012450: 687b ldr r3, [r7, #4] 8012452: 681b ldr r3, [r3, #0] 8012454: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012456: 68fb ldr r3, [r7, #12] 8012458: e853 3f00 ldrex r3, [r3] 801245c: 60bb str r3, [r7, #8] return(result); 801245e: 68bb ldr r3, [r7, #8] 8012460: f043 0340 orr.w r3, r3, #64 @ 0x40 8012464: 633b str r3, [r7, #48] @ 0x30 8012466: 687b ldr r3, [r7, #4] 8012468: 681b ldr r3, [r3, #0] 801246a: 461a mov r2, r3 801246c: 6b3b ldr r3, [r7, #48] @ 0x30 801246e: 61bb str r3, [r7, #24] 8012470: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012472: 6979 ldr r1, [r7, #20] 8012474: 69ba ldr r2, [r7, #24] 8012476: e841 2300 strex r3, r2, [r1] 801247a: 613b str r3, [r7, #16] return(result); 801247c: 693b ldr r3, [r7, #16] 801247e: 2b00 cmp r3, #0 8012480: d1e6 bne.n 8012450 huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); huart->pTxBuffPtr++; huart->TxXferCount--; } } } 8012482: e013 b.n 80124ac huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 8012484: 687b ldr r3, [r7, #4] 8012486: 6d1b ldr r3, [r3, #80] @ 0x50 8012488: 781a ldrb r2, [r3, #0] 801248a: 687b ldr r3, [r7, #4] 801248c: 681b ldr r3, [r3, #0] 801248e: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 8012490: 687b ldr r3, [r7, #4] 8012492: 6d1b ldr r3, [r3, #80] @ 0x50 8012494: 1c5a adds r2, r3, #1 8012496: 687b ldr r3, [r7, #4] 8012498: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 801249a: 687b ldr r3, [r7, #4] 801249c: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80124a0: b29b uxth r3, r3 80124a2: 3b01 subs r3, #1 80124a4: b29a uxth r2, r3 80124a6: 687b ldr r3, [r7, #4] 80124a8: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 80124ac: bf00 nop 80124ae: 373c adds r7, #60 @ 0x3c 80124b0: 46bd mov sp, r7 80124b2: f85d 7b04 ldr.w r7, [sp], #4 80124b6: 4770 bx lr 080124b8 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { 80124b8: b480 push {r7} 80124ba: b091 sub sp, #68 @ 0x44 80124bc: af00 add r7, sp, #0 80124be: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 80124c0: 687b ldr r3, [r7, #4] 80124c2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80124c6: 2b21 cmp r3, #33 @ 0x21 80124c8: d151 bne.n 801256e { if (huart->TxXferCount == 0U) 80124ca: 687b ldr r3, [r7, #4] 80124cc: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80124d0: b29b uxth r3, r3 80124d2: 2b00 cmp r3, #0 80124d4: d132 bne.n 801253c { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 80124d6: 687b ldr r3, [r7, #4] 80124d8: 681b ldr r3, [r3, #0] 80124da: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80124dc: 6a7b ldr r3, [r7, #36] @ 0x24 80124de: e853 3f00 ldrex r3, [r3] 80124e2: 623b str r3, [r7, #32] return(result); 80124e4: 6a3b ldr r3, [r7, #32] 80124e6: f023 0380 bic.w r3, r3, #128 @ 0x80 80124ea: 63bb str r3, [r7, #56] @ 0x38 80124ec: 687b ldr r3, [r7, #4] 80124ee: 681b ldr r3, [r3, #0] 80124f0: 461a mov r2, r3 80124f2: 6bbb ldr r3, [r7, #56] @ 0x38 80124f4: 633b str r3, [r7, #48] @ 0x30 80124f6: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80124f8: 6af9 ldr r1, [r7, #44] @ 0x2c 80124fa: 6b3a ldr r2, [r7, #48] @ 0x30 80124fc: e841 2300 strex r3, r2, [r1] 8012500: 62bb str r3, [r7, #40] @ 0x28 return(result); 8012502: 6abb ldr r3, [r7, #40] @ 0x28 8012504: 2b00 cmp r3, #0 8012506: d1e6 bne.n 80124d6 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8012508: 687b ldr r3, [r7, #4] 801250a: 681b ldr r3, [r3, #0] 801250c: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801250e: 693b ldr r3, [r7, #16] 8012510: e853 3f00 ldrex r3, [r3] 8012514: 60fb str r3, [r7, #12] return(result); 8012516: 68fb ldr r3, [r7, #12] 8012518: f043 0340 orr.w r3, r3, #64 @ 0x40 801251c: 637b str r3, [r7, #52] @ 0x34 801251e: 687b ldr r3, [r7, #4] 8012520: 681b ldr r3, [r3, #0] 8012522: 461a mov r2, r3 8012524: 6b7b ldr r3, [r7, #52] @ 0x34 8012526: 61fb str r3, [r7, #28] 8012528: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801252a: 69b9 ldr r1, [r7, #24] 801252c: 69fa ldr r2, [r7, #28] 801252e: e841 2300 strex r3, r2, [r1] 8012532: 617b str r3, [r7, #20] return(result); 8012534: 697b ldr r3, [r7, #20] 8012536: 2b00 cmp r3, #0 8012538: d1e6 bne.n 8012508 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; } } } 801253a: e018 b.n 801256e tmp = (const uint16_t *) huart->pTxBuffPtr; 801253c: 687b ldr r3, [r7, #4] 801253e: 6d1b ldr r3, [r3, #80] @ 0x50 8012540: 63fb str r3, [r7, #60] @ 0x3c huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 8012542: 6bfb ldr r3, [r7, #60] @ 0x3c 8012544: 881b ldrh r3, [r3, #0] 8012546: 461a mov r2, r3 8012548: 687b ldr r3, [r7, #4] 801254a: 681b ldr r3, [r3, #0] 801254c: f3c2 0208 ubfx r2, r2, #0, #9 8012550: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 8012552: 687b ldr r3, [r7, #4] 8012554: 6d1b ldr r3, [r3, #80] @ 0x50 8012556: 1c9a adds r2, r3, #2 8012558: 687b ldr r3, [r7, #4] 801255a: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 801255c: 687b ldr r3, [r7, #4] 801255e: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012562: b29b uxth r3, r3 8012564: 3b01 subs r3, #1 8012566: b29a uxth r2, r3 8012568: 687b ldr r3, [r7, #4] 801256a: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 801256e: bf00 nop 8012570: 3744 adds r7, #68 @ 0x44 8012572: 46bd mov sp, r7 8012574: f85d 7b04 ldr.w r7, [sp], #4 8012578: 4770 bx lr 0801257a : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 801257a: b480 push {r7} 801257c: b091 sub sp, #68 @ 0x44 801257e: af00 add r7, sp, #0 8012580: 6078 str r0, [r7, #4] uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8012582: 687b ldr r3, [r7, #4] 8012584: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8012588: 2b21 cmp r3, #33 @ 0x21 801258a: d160 bne.n 801264e { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 801258c: 687b ldr r3, [r7, #4] 801258e: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 8012592: 87fb strh r3, [r7, #62] @ 0x3e 8012594: e057 b.n 8012646 { if (huart->TxXferCount == 0U) 8012596: 687b ldr r3, [r7, #4] 8012598: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 801259c: b29b uxth r3, r3 801259e: 2b00 cmp r3, #0 80125a0: d133 bne.n 801260a { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 80125a2: 687b ldr r3, [r7, #4] 80125a4: 681b ldr r3, [r3, #0] 80125a6: 3308 adds r3, #8 80125a8: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80125aa: 6a7b ldr r3, [r7, #36] @ 0x24 80125ac: e853 3f00 ldrex r3, [r3] 80125b0: 623b str r3, [r7, #32] return(result); 80125b2: 6a3b ldr r3, [r7, #32] 80125b4: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 80125b8: 63bb str r3, [r7, #56] @ 0x38 80125ba: 687b ldr r3, [r7, #4] 80125bc: 681b ldr r3, [r3, #0] 80125be: 3308 adds r3, #8 80125c0: 6bba ldr r2, [r7, #56] @ 0x38 80125c2: 633a str r2, [r7, #48] @ 0x30 80125c4: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80125c6: 6af9 ldr r1, [r7, #44] @ 0x2c 80125c8: 6b3a ldr r2, [r7, #48] @ 0x30 80125ca: e841 2300 strex r3, r2, [r1] 80125ce: 62bb str r3, [r7, #40] @ 0x28 return(result); 80125d0: 6abb ldr r3, [r7, #40] @ 0x28 80125d2: 2b00 cmp r3, #0 80125d4: d1e5 bne.n 80125a2 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80125d6: 687b ldr r3, [r7, #4] 80125d8: 681b ldr r3, [r3, #0] 80125da: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80125dc: 693b ldr r3, [r7, #16] 80125de: e853 3f00 ldrex r3, [r3] 80125e2: 60fb str r3, [r7, #12] return(result); 80125e4: 68fb ldr r3, [r7, #12] 80125e6: f043 0340 orr.w r3, r3, #64 @ 0x40 80125ea: 637b str r3, [r7, #52] @ 0x34 80125ec: 687b ldr r3, [r7, #4] 80125ee: 681b ldr r3, [r3, #0] 80125f0: 461a mov r2, r3 80125f2: 6b7b ldr r3, [r7, #52] @ 0x34 80125f4: 61fb str r3, [r7, #28] 80125f6: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80125f8: 69b9 ldr r1, [r7, #24] 80125fa: 69fa ldr r2, [r7, #28] 80125fc: e841 2300 strex r3, r2, [r1] 8012600: 617b str r3, [r7, #20] return(result); 8012602: 697b ldr r3, [r7, #20] 8012604: 2b00 cmp r3, #0 8012606: d1e6 bne.n 80125d6 break; /* force exit loop */ 8012608: e021 b.n 801264e } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 801260a: 687b ldr r3, [r7, #4] 801260c: 681b ldr r3, [r3, #0] 801260e: 69db ldr r3, [r3, #28] 8012610: f003 0380 and.w r3, r3, #128 @ 0x80 8012614: 2b00 cmp r3, #0 8012616: d013 beq.n 8012640 { huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 8012618: 687b ldr r3, [r7, #4] 801261a: 6d1b ldr r3, [r3, #80] @ 0x50 801261c: 781a ldrb r2, [r3, #0] 801261e: 687b ldr r3, [r7, #4] 8012620: 681b ldr r3, [r3, #0] 8012622: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 8012624: 687b ldr r3, [r7, #4] 8012626: 6d1b ldr r3, [r3, #80] @ 0x50 8012628: 1c5a adds r2, r3, #1 801262a: 687b ldr r3, [r7, #4] 801262c: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 801262e: 687b ldr r3, [r7, #4] 8012630: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012634: b29b uxth r3, r3 8012636: 3b01 subs r3, #1 8012638: b29a uxth r2, r3 801263a: 687b ldr r3, [r7, #4] 801263c: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 8012640: 8ffb ldrh r3, [r7, #62] @ 0x3e 8012642: 3b01 subs r3, #1 8012644: 87fb strh r3, [r7, #62] @ 0x3e 8012646: 8ffb ldrh r3, [r7, #62] @ 0x3e 8012648: 2b00 cmp r3, #0 801264a: d1a4 bne.n 8012596 { /* Nothing to do */ } } } } 801264c: e7ff b.n 801264e 801264e: bf00 nop 8012650: 3744 adds r7, #68 @ 0x44 8012652: 46bd mov sp, r7 8012654: f85d 7b04 ldr.w r7, [sp], #4 8012658: 4770 bx lr 0801265a : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 801265a: b480 push {r7} 801265c: b091 sub sp, #68 @ 0x44 801265e: af00 add r7, sp, #0 8012660: 6078 str r0, [r7, #4] const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8012662: 687b ldr r3, [r7, #4] 8012664: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8012668: 2b21 cmp r3, #33 @ 0x21 801266a: d165 bne.n 8012738 { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 801266c: 687b ldr r3, [r7, #4] 801266e: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 8012672: 87fb strh r3, [r7, #62] @ 0x3e 8012674: e05c b.n 8012730 { if (huart->TxXferCount == 0U) 8012676: 687b ldr r3, [r7, #4] 8012678: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 801267c: b29b uxth r3, r3 801267e: 2b00 cmp r3, #0 8012680: d133 bne.n 80126ea { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 8012682: 687b ldr r3, [r7, #4] 8012684: 681b ldr r3, [r3, #0] 8012686: 3308 adds r3, #8 8012688: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801268a: 6a3b ldr r3, [r7, #32] 801268c: e853 3f00 ldrex r3, [r3] 8012690: 61fb str r3, [r7, #28] return(result); 8012692: 69fb ldr r3, [r7, #28] 8012694: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 8012698: 637b str r3, [r7, #52] @ 0x34 801269a: 687b ldr r3, [r7, #4] 801269c: 681b ldr r3, [r3, #0] 801269e: 3308 adds r3, #8 80126a0: 6b7a ldr r2, [r7, #52] @ 0x34 80126a2: 62fa str r2, [r7, #44] @ 0x2c 80126a4: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80126a6: 6ab9 ldr r1, [r7, #40] @ 0x28 80126a8: 6afa ldr r2, [r7, #44] @ 0x2c 80126aa: e841 2300 strex r3, r2, [r1] 80126ae: 627b str r3, [r7, #36] @ 0x24 return(result); 80126b0: 6a7b ldr r3, [r7, #36] @ 0x24 80126b2: 2b00 cmp r3, #0 80126b4: d1e5 bne.n 8012682 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80126b6: 687b ldr r3, [r7, #4] 80126b8: 681b ldr r3, [r3, #0] 80126ba: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80126bc: 68fb ldr r3, [r7, #12] 80126be: e853 3f00 ldrex r3, [r3] 80126c2: 60bb str r3, [r7, #8] return(result); 80126c4: 68bb ldr r3, [r7, #8] 80126c6: f043 0340 orr.w r3, r3, #64 @ 0x40 80126ca: 633b str r3, [r7, #48] @ 0x30 80126cc: 687b ldr r3, [r7, #4] 80126ce: 681b ldr r3, [r3, #0] 80126d0: 461a mov r2, r3 80126d2: 6b3b ldr r3, [r7, #48] @ 0x30 80126d4: 61bb str r3, [r7, #24] 80126d6: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80126d8: 6979 ldr r1, [r7, #20] 80126da: 69ba ldr r2, [r7, #24] 80126dc: e841 2300 strex r3, r2, [r1] 80126e0: 613b str r3, [r7, #16] return(result); 80126e2: 693b ldr r3, [r7, #16] 80126e4: 2b00 cmp r3, #0 80126e6: d1e6 bne.n 80126b6 break; /* force exit loop */ 80126e8: e026 b.n 8012738 } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 80126ea: 687b ldr r3, [r7, #4] 80126ec: 681b ldr r3, [r3, #0] 80126ee: 69db ldr r3, [r3, #28] 80126f0: f003 0380 and.w r3, r3, #128 @ 0x80 80126f4: 2b00 cmp r3, #0 80126f6: d018 beq.n 801272a { tmp = (const uint16_t *) huart->pTxBuffPtr; 80126f8: 687b ldr r3, [r7, #4] 80126fa: 6d1b ldr r3, [r3, #80] @ 0x50 80126fc: 63bb str r3, [r7, #56] @ 0x38 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 80126fe: 6bbb ldr r3, [r7, #56] @ 0x38 8012700: 881b ldrh r3, [r3, #0] 8012702: 461a mov r2, r3 8012704: 687b ldr r3, [r7, #4] 8012706: 681b ldr r3, [r3, #0] 8012708: f3c2 0208 ubfx r2, r2, #0, #9 801270c: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 801270e: 687b ldr r3, [r7, #4] 8012710: 6d1b ldr r3, [r3, #80] @ 0x50 8012712: 1c9a adds r2, r3, #2 8012714: 687b ldr r3, [r7, #4] 8012716: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 8012718: 687b ldr r3, [r7, #4] 801271a: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 801271e: b29b uxth r3, r3 8012720: 3b01 subs r3, #1 8012722: b29a uxth r2, r3 8012724: 687b ldr r3, [r7, #4] 8012726: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 801272a: 8ffb ldrh r3, [r7, #62] @ 0x3e 801272c: 3b01 subs r3, #1 801272e: 87fb strh r3, [r7, #62] @ 0x3e 8012730: 8ffb ldrh r3, [r7, #62] @ 0x3e 8012732: 2b00 cmp r3, #0 8012734: d19f bne.n 8012676 { /* Nothing to do */ } } } } 8012736: e7ff b.n 8012738 8012738: bf00 nop 801273a: 3744 adds r7, #68 @ 0x44 801273c: 46bd mov sp, r7 801273e: f85d 7b04 ldr.w r7, [sp], #4 8012742: 4770 bx lr 08012744 : * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8012744: b580 push {r7, lr} 8012746: b088 sub sp, #32 8012748: af00 add r7, sp, #0 801274a: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); 801274c: 687b ldr r3, [r7, #4] 801274e: 681b ldr r3, [r3, #0] 8012750: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012752: 68fb ldr r3, [r7, #12] 8012754: e853 3f00 ldrex r3, [r3] 8012758: 60bb str r3, [r7, #8] return(result); 801275a: 68bb ldr r3, [r7, #8] 801275c: f023 0340 bic.w r3, r3, #64 @ 0x40 8012760: 61fb str r3, [r7, #28] 8012762: 687b ldr r3, [r7, #4] 8012764: 681b ldr r3, [r3, #0] 8012766: 461a mov r2, r3 8012768: 69fb ldr r3, [r7, #28] 801276a: 61bb str r3, [r7, #24] 801276c: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801276e: 6979 ldr r1, [r7, #20] 8012770: 69ba ldr r2, [r7, #24] 8012772: e841 2300 strex r3, r2, [r1] 8012776: 613b str r3, [r7, #16] return(result); 8012778: 693b ldr r3, [r7, #16] 801277a: 2b00 cmp r3, #0 801277c: d1e6 bne.n 801274c /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 801277e: 687b ldr r3, [r7, #4] 8012780: 2220 movs r2, #32 8012782: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Cleat TxISR function pointer */ huart->TxISR = NULL; 8012786: 687b ldr r3, [r7, #4] 8012788: 2200 movs r2, #0 801278a: 679a str r2, [r3, #120] @ 0x78 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 801278c: 6878 ldr r0, [r7, #4] 801278e: f7f2 f93b bl 8004a08 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8012792: bf00 nop 8012794: 3720 adds r7, #32 8012796: 46bd mov sp, r7 8012798: bd80 pop {r7, pc} ... 0801279c : * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) { 801279c: b580 push {r7, lr} 801279e: b09c sub sp, #112 @ 0x70 80127a0: af00 add r7, sp, #0 80127a2: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 80127a4: 687b ldr r3, [r7, #4] 80127a6: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 80127aa: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80127ae: 687b ldr r3, [r7, #4] 80127b0: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80127b4: 2b22 cmp r3, #34 @ 0x22 80127b6: f040 80be bne.w 8012936 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 80127ba: 687b ldr r3, [r7, #4] 80127bc: 681b ldr r3, [r3, #0] 80127be: 6a5b ldr r3, [r3, #36] @ 0x24 80127c0: f8a7 306c strh.w r3, [r7, #108] @ 0x6c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 80127c4: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 80127c8: b2d9 uxtb r1, r3 80127ca: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 80127ce: b2da uxtb r2, r3 80127d0: 687b ldr r3, [r7, #4] 80127d2: 6d9b ldr r3, [r3, #88] @ 0x58 80127d4: 400a ands r2, r1 80127d6: b2d2 uxtb r2, r2 80127d8: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 80127da: 687b ldr r3, [r7, #4] 80127dc: 6d9b ldr r3, [r3, #88] @ 0x58 80127de: 1c5a adds r2, r3, #1 80127e0: 687b ldr r3, [r7, #4] 80127e2: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 80127e4: 687b ldr r3, [r7, #4] 80127e6: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80127ea: b29b uxth r3, r3 80127ec: 3b01 subs r3, #1 80127ee: b29a uxth r2, r3 80127f0: 687b ldr r3, [r7, #4] 80127f2: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 80127f6: 687b ldr r3, [r7, #4] 80127f8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80127fc: b29b uxth r3, r3 80127fe: 2b00 cmp r3, #0 8012800: f040 80a1 bne.w 8012946 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8012804: 687b ldr r3, [r7, #4] 8012806: 681b ldr r3, [r3, #0] 8012808: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801280a: 6cfb ldr r3, [r7, #76] @ 0x4c 801280c: e853 3f00 ldrex r3, [r3] 8012810: 64bb str r3, [r7, #72] @ 0x48 return(result); 8012812: 6cbb ldr r3, [r7, #72] @ 0x48 8012814: f423 7390 bic.w r3, r3, #288 @ 0x120 8012818: 66bb str r3, [r7, #104] @ 0x68 801281a: 687b ldr r3, [r7, #4] 801281c: 681b ldr r3, [r3, #0] 801281e: 461a mov r2, r3 8012820: 6ebb ldr r3, [r7, #104] @ 0x68 8012822: 65bb str r3, [r7, #88] @ 0x58 8012824: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012826: 6d79 ldr r1, [r7, #84] @ 0x54 8012828: 6dba ldr r2, [r7, #88] @ 0x58 801282a: e841 2300 strex r3, r2, [r1] 801282e: 653b str r3, [r7, #80] @ 0x50 return(result); 8012830: 6d3b ldr r3, [r7, #80] @ 0x50 8012832: 2b00 cmp r3, #0 8012834: d1e6 bne.n 8012804 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012836: 687b ldr r3, [r7, #4] 8012838: 681b ldr r3, [r3, #0] 801283a: 3308 adds r3, #8 801283c: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801283e: 6bbb ldr r3, [r7, #56] @ 0x38 8012840: e853 3f00 ldrex r3, [r3] 8012844: 637b str r3, [r7, #52] @ 0x34 return(result); 8012846: 6b7b ldr r3, [r7, #52] @ 0x34 8012848: f023 0301 bic.w r3, r3, #1 801284c: 667b str r3, [r7, #100] @ 0x64 801284e: 687b ldr r3, [r7, #4] 8012850: 681b ldr r3, [r3, #0] 8012852: 3308 adds r3, #8 8012854: 6e7a ldr r2, [r7, #100] @ 0x64 8012856: 647a str r2, [r7, #68] @ 0x44 8012858: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801285a: 6c39 ldr r1, [r7, #64] @ 0x40 801285c: 6c7a ldr r2, [r7, #68] @ 0x44 801285e: e841 2300 strex r3, r2, [r1] 8012862: 63fb str r3, [r7, #60] @ 0x3c return(result); 8012864: 6bfb ldr r3, [r7, #60] @ 0x3c 8012866: 2b00 cmp r3, #0 8012868: d1e5 bne.n 8012836 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 801286a: 687b ldr r3, [r7, #4] 801286c: 2220 movs r2, #32 801286e: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8012872: 687b ldr r3, [r7, #4] 8012874: 2200 movs r2, #0 8012876: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8012878: 687b ldr r3, [r7, #4] 801287a: 2200 movs r2, #0 801287c: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 801287e: 687b ldr r3, [r7, #4] 8012880: 681b ldr r3, [r3, #0] 8012882: 4a33 ldr r2, [pc, #204] @ (8012950 ) 8012884: 4293 cmp r3, r2 8012886: d01f beq.n 80128c8 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8012888: 687b ldr r3, [r7, #4] 801288a: 681b ldr r3, [r3, #0] 801288c: 685b ldr r3, [r3, #4] 801288e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8012892: 2b00 cmp r3, #0 8012894: d018 beq.n 80128c8 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8012896: 687b ldr r3, [r7, #4] 8012898: 681b ldr r3, [r3, #0] 801289a: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801289c: 6a7b ldr r3, [r7, #36] @ 0x24 801289e: e853 3f00 ldrex r3, [r3] 80128a2: 623b str r3, [r7, #32] return(result); 80128a4: 6a3b ldr r3, [r7, #32] 80128a6: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 80128aa: 663b str r3, [r7, #96] @ 0x60 80128ac: 687b ldr r3, [r7, #4] 80128ae: 681b ldr r3, [r3, #0] 80128b0: 461a mov r2, r3 80128b2: 6e3b ldr r3, [r7, #96] @ 0x60 80128b4: 633b str r3, [r7, #48] @ 0x30 80128b6: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80128b8: 6af9 ldr r1, [r7, #44] @ 0x2c 80128ba: 6b3a ldr r2, [r7, #48] @ 0x30 80128bc: e841 2300 strex r3, r2, [r1] 80128c0: 62bb str r3, [r7, #40] @ 0x28 return(result); 80128c2: 6abb ldr r3, [r7, #40] @ 0x28 80128c4: 2b00 cmp r3, #0 80128c6: d1e6 bne.n 8012896 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80128c8: 687b ldr r3, [r7, #4] 80128ca: 6edb ldr r3, [r3, #108] @ 0x6c 80128cc: 2b01 cmp r3, #1 80128ce: d12e bne.n 801292e { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80128d0: 687b ldr r3, [r7, #4] 80128d2: 2200 movs r2, #0 80128d4: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80128d6: 687b ldr r3, [r7, #4] 80128d8: 681b ldr r3, [r3, #0] 80128da: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80128dc: 693b ldr r3, [r7, #16] 80128de: e853 3f00 ldrex r3, [r3] 80128e2: 60fb str r3, [r7, #12] return(result); 80128e4: 68fb ldr r3, [r7, #12] 80128e6: f023 0310 bic.w r3, r3, #16 80128ea: 65fb str r3, [r7, #92] @ 0x5c 80128ec: 687b ldr r3, [r7, #4] 80128ee: 681b ldr r3, [r3, #0] 80128f0: 461a mov r2, r3 80128f2: 6dfb ldr r3, [r7, #92] @ 0x5c 80128f4: 61fb str r3, [r7, #28] 80128f6: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80128f8: 69b9 ldr r1, [r7, #24] 80128fa: 69fa ldr r2, [r7, #28] 80128fc: e841 2300 strex r3, r2, [r1] 8012900: 617b str r3, [r7, #20] return(result); 8012902: 697b ldr r3, [r7, #20] 8012904: 2b00 cmp r3, #0 8012906: d1e6 bne.n 80128d6 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8012908: 687b ldr r3, [r7, #4] 801290a: 681b ldr r3, [r3, #0] 801290c: 69db ldr r3, [r3, #28] 801290e: f003 0310 and.w r3, r3, #16 8012912: 2b10 cmp r3, #16 8012914: d103 bne.n 801291e { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8012916: 687b ldr r3, [r7, #4] 8012918: 681b ldr r3, [r3, #0] 801291a: 2210 movs r2, #16 801291c: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 801291e: 687b ldr r3, [r7, #4] 8012920: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8012924: 4619 mov r1, r3 8012926: 6878 ldr r0, [r7, #4] 8012928: f7f2 f844 bl 80049b4 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 801292c: e00b b.n 8012946 HAL_UART_RxCpltCallback(huart); 801292e: 6878 ldr r0, [r7, #4] 8012930: f7f2 f836 bl 80049a0 } 8012934: e007 b.n 8012946 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8012936: 687b ldr r3, [r7, #4] 8012938: 681b ldr r3, [r3, #0] 801293a: 699a ldr r2, [r3, #24] 801293c: 687b ldr r3, [r7, #4] 801293e: 681b ldr r3, [r3, #0] 8012940: f042 0208 orr.w r2, r2, #8 8012944: 619a str r2, [r3, #24] } 8012946: bf00 nop 8012948: 3770 adds r7, #112 @ 0x70 801294a: 46bd mov sp, r7 801294c: bd80 pop {r7, pc} 801294e: bf00 nop 8012950: 58000c00 .word 0x58000c00 08012954 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { 8012954: b580 push {r7, lr} 8012956: b09c sub sp, #112 @ 0x70 8012958: af00 add r7, sp, #0 801295a: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 801295c: 687b ldr r3, [r7, #4] 801295e: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8012962: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8012966: 687b ldr r3, [r7, #4] 8012968: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 801296c: 2b22 cmp r3, #34 @ 0x22 801296e: f040 80be bne.w 8012aee { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8012972: 687b ldr r3, [r7, #4] 8012974: 681b ldr r3, [r3, #0] 8012976: 6a5b ldr r3, [r3, #36] @ 0x24 8012978: f8a7 306c strh.w r3, [r7, #108] @ 0x6c tmp = (uint16_t *) huart->pRxBuffPtr ; 801297c: 687b ldr r3, [r7, #4] 801297e: 6d9b ldr r3, [r3, #88] @ 0x58 8012980: 66bb str r3, [r7, #104] @ 0x68 *tmp = (uint16_t)(uhdata & uhMask); 8012982: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c 8012986: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 801298a: 4013 ands r3, r2 801298c: b29a uxth r2, r3 801298e: 6ebb ldr r3, [r7, #104] @ 0x68 8012990: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8012992: 687b ldr r3, [r7, #4] 8012994: 6d9b ldr r3, [r3, #88] @ 0x58 8012996: 1c9a adds r2, r3, #2 8012998: 687b ldr r3, [r7, #4] 801299a: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 801299c: 687b ldr r3, [r7, #4] 801299e: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80129a2: b29b uxth r3, r3 80129a4: 3b01 subs r3, #1 80129a6: b29a uxth r2, r3 80129a8: 687b ldr r3, [r7, #4] 80129aa: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 80129ae: 687b ldr r3, [r7, #4] 80129b0: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80129b4: b29b uxth r3, r3 80129b6: 2b00 cmp r3, #0 80129b8: f040 80a1 bne.w 8012afe { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 80129bc: 687b ldr r3, [r7, #4] 80129be: 681b ldr r3, [r3, #0] 80129c0: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80129c2: 6cbb ldr r3, [r7, #72] @ 0x48 80129c4: e853 3f00 ldrex r3, [r3] 80129c8: 647b str r3, [r7, #68] @ 0x44 return(result); 80129ca: 6c7b ldr r3, [r7, #68] @ 0x44 80129cc: f423 7390 bic.w r3, r3, #288 @ 0x120 80129d0: 667b str r3, [r7, #100] @ 0x64 80129d2: 687b ldr r3, [r7, #4] 80129d4: 681b ldr r3, [r3, #0] 80129d6: 461a mov r2, r3 80129d8: 6e7b ldr r3, [r7, #100] @ 0x64 80129da: 657b str r3, [r7, #84] @ 0x54 80129dc: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80129de: 6d39 ldr r1, [r7, #80] @ 0x50 80129e0: 6d7a ldr r2, [r7, #84] @ 0x54 80129e2: e841 2300 strex r3, r2, [r1] 80129e6: 64fb str r3, [r7, #76] @ 0x4c return(result); 80129e8: 6cfb ldr r3, [r7, #76] @ 0x4c 80129ea: 2b00 cmp r3, #0 80129ec: d1e6 bne.n 80129bc /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80129ee: 687b ldr r3, [r7, #4] 80129f0: 681b ldr r3, [r3, #0] 80129f2: 3308 adds r3, #8 80129f4: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80129f6: 6b7b ldr r3, [r7, #52] @ 0x34 80129f8: e853 3f00 ldrex r3, [r3] 80129fc: 633b str r3, [r7, #48] @ 0x30 return(result); 80129fe: 6b3b ldr r3, [r7, #48] @ 0x30 8012a00: f023 0301 bic.w r3, r3, #1 8012a04: 663b str r3, [r7, #96] @ 0x60 8012a06: 687b ldr r3, [r7, #4] 8012a08: 681b ldr r3, [r3, #0] 8012a0a: 3308 adds r3, #8 8012a0c: 6e3a ldr r2, [r7, #96] @ 0x60 8012a0e: 643a str r2, [r7, #64] @ 0x40 8012a10: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012a12: 6bf9 ldr r1, [r7, #60] @ 0x3c 8012a14: 6c3a ldr r2, [r7, #64] @ 0x40 8012a16: e841 2300 strex r3, r2, [r1] 8012a1a: 63bb str r3, [r7, #56] @ 0x38 return(result); 8012a1c: 6bbb ldr r3, [r7, #56] @ 0x38 8012a1e: 2b00 cmp r3, #0 8012a20: d1e5 bne.n 80129ee /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012a22: 687b ldr r3, [r7, #4] 8012a24: 2220 movs r2, #32 8012a26: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8012a2a: 687b ldr r3, [r7, #4] 8012a2c: 2200 movs r2, #0 8012a2e: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8012a30: 687b ldr r3, [r7, #4] 8012a32: 2200 movs r2, #0 8012a34: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8012a36: 687b ldr r3, [r7, #4] 8012a38: 681b ldr r3, [r3, #0] 8012a3a: 4a33 ldr r2, [pc, #204] @ (8012b08 ) 8012a3c: 4293 cmp r3, r2 8012a3e: d01f beq.n 8012a80 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8012a40: 687b ldr r3, [r7, #4] 8012a42: 681b ldr r3, [r3, #0] 8012a44: 685b ldr r3, [r3, #4] 8012a46: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8012a4a: 2b00 cmp r3, #0 8012a4c: d018 beq.n 8012a80 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8012a4e: 687b ldr r3, [r7, #4] 8012a50: 681b ldr r3, [r3, #0] 8012a52: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012a54: 6a3b ldr r3, [r7, #32] 8012a56: e853 3f00 ldrex r3, [r3] 8012a5a: 61fb str r3, [r7, #28] return(result); 8012a5c: 69fb ldr r3, [r7, #28] 8012a5e: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8012a62: 65fb str r3, [r7, #92] @ 0x5c 8012a64: 687b ldr r3, [r7, #4] 8012a66: 681b ldr r3, [r3, #0] 8012a68: 461a mov r2, r3 8012a6a: 6dfb ldr r3, [r7, #92] @ 0x5c 8012a6c: 62fb str r3, [r7, #44] @ 0x2c 8012a6e: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012a70: 6ab9 ldr r1, [r7, #40] @ 0x28 8012a72: 6afa ldr r2, [r7, #44] @ 0x2c 8012a74: e841 2300 strex r3, r2, [r1] 8012a78: 627b str r3, [r7, #36] @ 0x24 return(result); 8012a7a: 6a7b ldr r3, [r7, #36] @ 0x24 8012a7c: 2b00 cmp r3, #0 8012a7e: d1e6 bne.n 8012a4e } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012a80: 687b ldr r3, [r7, #4] 8012a82: 6edb ldr r3, [r3, #108] @ 0x6c 8012a84: 2b01 cmp r3, #1 8012a86: d12e bne.n 8012ae6 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012a88: 687b ldr r3, [r7, #4] 8012a8a: 2200 movs r2, #0 8012a8c: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012a8e: 687b ldr r3, [r7, #4] 8012a90: 681b ldr r3, [r3, #0] 8012a92: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012a94: 68fb ldr r3, [r7, #12] 8012a96: e853 3f00 ldrex r3, [r3] 8012a9a: 60bb str r3, [r7, #8] return(result); 8012a9c: 68bb ldr r3, [r7, #8] 8012a9e: f023 0310 bic.w r3, r3, #16 8012aa2: 65bb str r3, [r7, #88] @ 0x58 8012aa4: 687b ldr r3, [r7, #4] 8012aa6: 681b ldr r3, [r3, #0] 8012aa8: 461a mov r2, r3 8012aaa: 6dbb ldr r3, [r7, #88] @ 0x58 8012aac: 61bb str r3, [r7, #24] 8012aae: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012ab0: 6979 ldr r1, [r7, #20] 8012ab2: 69ba ldr r2, [r7, #24] 8012ab4: e841 2300 strex r3, r2, [r1] 8012ab8: 613b str r3, [r7, #16] return(result); 8012aba: 693b ldr r3, [r7, #16] 8012abc: 2b00 cmp r3, #0 8012abe: d1e6 bne.n 8012a8e if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8012ac0: 687b ldr r3, [r7, #4] 8012ac2: 681b ldr r3, [r3, #0] 8012ac4: 69db ldr r3, [r3, #28] 8012ac6: f003 0310 and.w r3, r3, #16 8012aca: 2b10 cmp r3, #16 8012acc: d103 bne.n 8012ad6 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8012ace: 687b ldr r3, [r7, #4] 8012ad0: 681b ldr r3, [r3, #0] 8012ad2: 2210 movs r2, #16 8012ad4: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8012ad6: 687b ldr r3, [r7, #4] 8012ad8: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8012adc: 4619 mov r1, r3 8012ade: 6878 ldr r0, [r7, #4] 8012ae0: f7f1 ff68 bl 80049b4 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8012ae4: e00b b.n 8012afe HAL_UART_RxCpltCallback(huart); 8012ae6: 6878 ldr r0, [r7, #4] 8012ae8: f7f1 ff5a bl 80049a0 } 8012aec: e007 b.n 8012afe __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8012aee: 687b ldr r3, [r7, #4] 8012af0: 681b ldr r3, [r3, #0] 8012af2: 699a ldr r2, [r3, #24] 8012af4: 687b ldr r3, [r7, #4] 8012af6: 681b ldr r3, [r3, #0] 8012af8: f042 0208 orr.w r2, r2, #8 8012afc: 619a str r2, [r3, #24] } 8012afe: bf00 nop 8012b00: 3770 adds r7, #112 @ 0x70 8012b02: 46bd mov sp, r7 8012b04: bd80 pop {r7, pc} 8012b06: bf00 nop 8012b08: 58000c00 .word 0x58000c00 08012b0c : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 8012b0c: b580 push {r7, lr} 8012b0e: b0ac sub sp, #176 @ 0xb0 8012b10: af00 add r7, sp, #0 8012b12: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 8012b14: 687b ldr r3, [r7, #4] 8012b16: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8012b1a: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 8012b1e: 687b ldr r3, [r7, #4] 8012b20: 681b ldr r3, [r3, #0] 8012b22: 69db ldr r3, [r3, #28] 8012b24: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr1its = READ_REG(huart->Instance->CR1); 8012b28: 687b ldr r3, [r7, #4] 8012b2a: 681b ldr r3, [r3, #0] 8012b2c: 681b ldr r3, [r3, #0] 8012b2e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8012b32: 687b ldr r3, [r7, #4] 8012b34: 681b ldr r3, [r3, #0] 8012b36: 689b ldr r3, [r3, #8] 8012b38: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8012b3c: 687b ldr r3, [r7, #4] 8012b3e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8012b42: 2b22 cmp r3, #34 @ 0x22 8012b44: f040 8180 bne.w 8012e48 { nb_rx_data = huart->NbRxDataToProcess; 8012b48: 687b ldr r3, [r7, #4] 8012b4a: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8012b4e: f8a7 309e strh.w r3, [r7, #158] @ 0x9e while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8012b52: e123 b.n 8012d9c { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8012b54: 687b ldr r3, [r7, #4] 8012b56: 681b ldr r3, [r3, #0] 8012b58: 6a5b ldr r3, [r3, #36] @ 0x24 8012b5a: f8a7 309c strh.w r3, [r7, #156] @ 0x9c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 8012b5e: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c 8012b62: b2d9 uxtb r1, r3 8012b64: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa 8012b68: b2da uxtb r2, r3 8012b6a: 687b ldr r3, [r7, #4] 8012b6c: 6d9b ldr r3, [r3, #88] @ 0x58 8012b6e: 400a ands r2, r1 8012b70: b2d2 uxtb r2, r2 8012b72: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8012b74: 687b ldr r3, [r7, #4] 8012b76: 6d9b ldr r3, [r3, #88] @ 0x58 8012b78: 1c5a adds r2, r3, #1 8012b7a: 687b ldr r3, [r7, #4] 8012b7c: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8012b7e: 687b ldr r3, [r7, #4] 8012b80: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012b84: b29b uxth r3, r3 8012b86: 3b01 subs r3, #1 8012b88: b29a uxth r2, r3 8012b8a: 687b ldr r3, [r7, #4] 8012b8c: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 8012b90: 687b ldr r3, [r7, #4] 8012b92: 681b ldr r3, [r3, #0] 8012b94: 69db ldr r3, [r3, #28] 8012b96: f8c7 30ac str.w r3, [r7, #172] @ 0xac /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8012b9a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012b9e: f003 0307 and.w r3, r3, #7 8012ba2: 2b00 cmp r3, #0 8012ba4: d053 beq.n 8012c4e { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8012ba6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012baa: f003 0301 and.w r3, r3, #1 8012bae: 2b00 cmp r3, #0 8012bb0: d011 beq.n 8012bd6 8012bb2: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 8012bb6: f403 7380 and.w r3, r3, #256 @ 0x100 8012bba: 2b00 cmp r3, #0 8012bbc: d00b beq.n 8012bd6 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8012bbe: 687b ldr r3, [r7, #4] 8012bc0: 681b ldr r3, [r3, #0] 8012bc2: 2201 movs r2, #1 8012bc4: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8012bc6: 687b ldr r3, [r7, #4] 8012bc8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012bcc: f043 0201 orr.w r2, r3, #1 8012bd0: 687b ldr r3, [r7, #4] 8012bd2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8012bd6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012bda: f003 0302 and.w r3, r3, #2 8012bde: 2b00 cmp r3, #0 8012be0: d011 beq.n 8012c06 8012be2: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8012be6: f003 0301 and.w r3, r3, #1 8012bea: 2b00 cmp r3, #0 8012bec: d00b beq.n 8012c06 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8012bee: 687b ldr r3, [r7, #4] 8012bf0: 681b ldr r3, [r3, #0] 8012bf2: 2202 movs r2, #2 8012bf4: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8012bf6: 687b ldr r3, [r7, #4] 8012bf8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012bfc: f043 0204 orr.w r2, r3, #4 8012c00: 687b ldr r3, [r7, #4] 8012c02: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8012c06: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012c0a: f003 0304 and.w r3, r3, #4 8012c0e: 2b00 cmp r3, #0 8012c10: d011 beq.n 8012c36 8012c12: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8012c16: f003 0301 and.w r3, r3, #1 8012c1a: 2b00 cmp r3, #0 8012c1c: d00b beq.n 8012c36 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8012c1e: 687b ldr r3, [r7, #4] 8012c20: 681b ldr r3, [r3, #0] 8012c22: 2204 movs r2, #4 8012c24: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8012c26: 687b ldr r3, [r7, #4] 8012c28: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012c2c: f043 0202 orr.w r2, r3, #2 8012c30: 687b ldr r3, [r7, #4] 8012c32: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8012c36: 687b ldr r3, [r7, #4] 8012c38: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012c3c: 2b00 cmp r3, #0 8012c3e: d006 beq.n 8012c4e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8012c40: 6878 ldr r0, [r7, #4] 8012c42: f7fe fb13 bl 801126c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012c46: 687b ldr r3, [r7, #4] 8012c48: 2200 movs r2, #0 8012c4a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 8012c4e: 687b ldr r3, [r7, #4] 8012c50: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012c54: b29b uxth r3, r3 8012c56: 2b00 cmp r3, #0 8012c58: f040 80a0 bne.w 8012d9c { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8012c5c: 687b ldr r3, [r7, #4] 8012c5e: 681b ldr r3, [r3, #0] 8012c60: 673b str r3, [r7, #112] @ 0x70 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012c62: 6f3b ldr r3, [r7, #112] @ 0x70 8012c64: e853 3f00 ldrex r3, [r3] 8012c68: 66fb str r3, [r7, #108] @ 0x6c return(result); 8012c6a: 6efb ldr r3, [r7, #108] @ 0x6c 8012c6c: f423 7380 bic.w r3, r3, #256 @ 0x100 8012c70: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8012c74: 687b ldr r3, [r7, #4] 8012c76: 681b ldr r3, [r3, #0] 8012c78: 461a mov r2, r3 8012c7a: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8012c7e: 67fb str r3, [r7, #124] @ 0x7c 8012c80: 67ba str r2, [r7, #120] @ 0x78 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012c82: 6fb9 ldr r1, [r7, #120] @ 0x78 8012c84: 6ffa ldr r2, [r7, #124] @ 0x7c 8012c86: e841 2300 strex r3, r2, [r1] 8012c8a: 677b str r3, [r7, #116] @ 0x74 return(result); 8012c8c: 6f7b ldr r3, [r7, #116] @ 0x74 8012c8e: 2b00 cmp r3, #0 8012c90: d1e4 bne.n 8012c5c /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8012c92: 687b ldr r3, [r7, #4] 8012c94: 681b ldr r3, [r3, #0] 8012c96: 3308 adds r3, #8 8012c98: 65fb str r3, [r7, #92] @ 0x5c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012c9a: 6dfb ldr r3, [r7, #92] @ 0x5c 8012c9c: e853 3f00 ldrex r3, [r3] 8012ca0: 65bb str r3, [r7, #88] @ 0x58 return(result); 8012ca2: 6dba ldr r2, [r7, #88] @ 0x58 8012ca4: 4b6e ldr r3, [pc, #440] @ (8012e60 ) 8012ca6: 4013 ands r3, r2 8012ca8: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8012cac: 687b ldr r3, [r7, #4] 8012cae: 681b ldr r3, [r3, #0] 8012cb0: 3308 adds r3, #8 8012cb2: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8012cb6: 66ba str r2, [r7, #104] @ 0x68 8012cb8: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012cba: 6e79 ldr r1, [r7, #100] @ 0x64 8012cbc: 6eba ldr r2, [r7, #104] @ 0x68 8012cbe: e841 2300 strex r3, r2, [r1] 8012cc2: 663b str r3, [r7, #96] @ 0x60 return(result); 8012cc4: 6e3b ldr r3, [r7, #96] @ 0x60 8012cc6: 2b00 cmp r3, #0 8012cc8: d1e3 bne.n 8012c92 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012cca: 687b ldr r3, [r7, #4] 8012ccc: 2220 movs r2, #32 8012cce: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8012cd2: 687b ldr r3, [r7, #4] 8012cd4: 2200 movs r2, #0 8012cd6: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8012cd8: 687b ldr r3, [r7, #4] 8012cda: 2200 movs r2, #0 8012cdc: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8012cde: 687b ldr r3, [r7, #4] 8012ce0: 681b ldr r3, [r3, #0] 8012ce2: 4a60 ldr r2, [pc, #384] @ (8012e64 ) 8012ce4: 4293 cmp r3, r2 8012ce6: d021 beq.n 8012d2c { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8012ce8: 687b ldr r3, [r7, #4] 8012cea: 681b ldr r3, [r3, #0] 8012cec: 685b ldr r3, [r3, #4] 8012cee: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8012cf2: 2b00 cmp r3, #0 8012cf4: d01a beq.n 8012d2c { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8012cf6: 687b ldr r3, [r7, #4] 8012cf8: 681b ldr r3, [r3, #0] 8012cfa: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012cfc: 6cbb ldr r3, [r7, #72] @ 0x48 8012cfe: e853 3f00 ldrex r3, [r3] 8012d02: 647b str r3, [r7, #68] @ 0x44 return(result); 8012d04: 6c7b ldr r3, [r7, #68] @ 0x44 8012d06: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8012d0a: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8012d0e: 687b ldr r3, [r7, #4] 8012d10: 681b ldr r3, [r3, #0] 8012d12: 461a mov r2, r3 8012d14: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8012d18: 657b str r3, [r7, #84] @ 0x54 8012d1a: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d1c: 6d39 ldr r1, [r7, #80] @ 0x50 8012d1e: 6d7a ldr r2, [r7, #84] @ 0x54 8012d20: e841 2300 strex r3, r2, [r1] 8012d24: 64fb str r3, [r7, #76] @ 0x4c return(result); 8012d26: 6cfb ldr r3, [r7, #76] @ 0x4c 8012d28: 2b00 cmp r3, #0 8012d2a: d1e4 bne.n 8012cf6 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012d2c: 687b ldr r3, [r7, #4] 8012d2e: 6edb ldr r3, [r3, #108] @ 0x6c 8012d30: 2b01 cmp r3, #1 8012d32: d130 bne.n 8012d96 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012d34: 687b ldr r3, [r7, #4] 8012d36: 2200 movs r2, #0 8012d38: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012d3a: 687b ldr r3, [r7, #4] 8012d3c: 681b ldr r3, [r3, #0] 8012d3e: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012d40: 6b7b ldr r3, [r7, #52] @ 0x34 8012d42: e853 3f00 ldrex r3, [r3] 8012d46: 633b str r3, [r7, #48] @ 0x30 return(result); 8012d48: 6b3b ldr r3, [r7, #48] @ 0x30 8012d4a: f023 0310 bic.w r3, r3, #16 8012d4e: f8c7 308c str.w r3, [r7, #140] @ 0x8c 8012d52: 687b ldr r3, [r7, #4] 8012d54: 681b ldr r3, [r3, #0] 8012d56: 461a mov r2, r3 8012d58: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8012d5c: 643b str r3, [r7, #64] @ 0x40 8012d5e: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d60: 6bf9 ldr r1, [r7, #60] @ 0x3c 8012d62: 6c3a ldr r2, [r7, #64] @ 0x40 8012d64: e841 2300 strex r3, r2, [r1] 8012d68: 63bb str r3, [r7, #56] @ 0x38 return(result); 8012d6a: 6bbb ldr r3, [r7, #56] @ 0x38 8012d6c: 2b00 cmp r3, #0 8012d6e: d1e4 bne.n 8012d3a if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8012d70: 687b ldr r3, [r7, #4] 8012d72: 681b ldr r3, [r3, #0] 8012d74: 69db ldr r3, [r3, #28] 8012d76: f003 0310 and.w r3, r3, #16 8012d7a: 2b10 cmp r3, #16 8012d7c: d103 bne.n 8012d86 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8012d7e: 687b ldr r3, [r7, #4] 8012d80: 681b ldr r3, [r3, #0] 8012d82: 2210 movs r2, #16 8012d84: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8012d86: 687b ldr r3, [r7, #4] 8012d88: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8012d8c: 4619 mov r1, r3 8012d8e: 6878 ldr r0, [r7, #4] 8012d90: f7f1 fe10 bl 80049b4 8012d94: e002 b.n 8012d9c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8012d96: 6878 ldr r0, [r7, #4] 8012d98: f7f1 fe02 bl 80049a0 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8012d9c: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e 8012da0: 2b00 cmp r3, #0 8012da2: d006 beq.n 8012db2 8012da4: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012da8: f003 0320 and.w r3, r3, #32 8012dac: 2b00 cmp r3, #0 8012dae: f47f aed1 bne.w 8012b54 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 8012db2: 687b ldr r3, [r7, #4] 8012db4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012db8: f8a7 308a strh.w r3, [r7, #138] @ 0x8a if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 8012dbc: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 8012dc0: 2b00 cmp r3, #0 8012dc2: d049 beq.n 8012e58 8012dc4: 687b ldr r3, [r7, #4] 8012dc6: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8012dca: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a 8012dce: 429a cmp r2, r3 8012dd0: d242 bcs.n 8012e58 { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8012dd2: 687b ldr r3, [r7, #4] 8012dd4: 681b ldr r3, [r3, #0] 8012dd6: 3308 adds r3, #8 8012dd8: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012dda: 6a3b ldr r3, [r7, #32] 8012ddc: e853 3f00 ldrex r3, [r3] 8012de0: 61fb str r3, [r7, #28] return(result); 8012de2: 69fb ldr r3, [r7, #28] 8012de4: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8012de8: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8012dec: 687b ldr r3, [r7, #4] 8012dee: 681b ldr r3, [r3, #0] 8012df0: 3308 adds r3, #8 8012df2: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 8012df6: 62fa str r2, [r7, #44] @ 0x2c 8012df8: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012dfa: 6ab9 ldr r1, [r7, #40] @ 0x28 8012dfc: 6afa ldr r2, [r7, #44] @ 0x2c 8012dfe: e841 2300 strex r3, r2, [r1] 8012e02: 627b str r3, [r7, #36] @ 0x24 return(result); 8012e04: 6a7b ldr r3, [r7, #36] @ 0x24 8012e06: 2b00 cmp r3, #0 8012e08: d1e3 bne.n 8012dd2 /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; 8012e0a: 687b ldr r3, [r7, #4] 8012e0c: 4a16 ldr r2, [pc, #88] @ (8012e68 ) 8012e0e: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8012e10: 687b ldr r3, [r7, #4] 8012e12: 681b ldr r3, [r3, #0] 8012e14: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012e16: 68fb ldr r3, [r7, #12] 8012e18: e853 3f00 ldrex r3, [r3] 8012e1c: 60bb str r3, [r7, #8] return(result); 8012e1e: 68bb ldr r3, [r7, #8] 8012e20: f043 0320 orr.w r3, r3, #32 8012e24: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8012e28: 687b ldr r3, [r7, #4] 8012e2a: 681b ldr r3, [r3, #0] 8012e2c: 461a mov r2, r3 8012e2e: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8012e32: 61bb str r3, [r7, #24] 8012e34: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012e36: 6979 ldr r1, [r7, #20] 8012e38: 69ba ldr r2, [r7, #24] 8012e3a: e841 2300 strex r3, r2, [r1] 8012e3e: 613b str r3, [r7, #16] return(result); 8012e40: 693b ldr r3, [r7, #16] 8012e42: 2b00 cmp r3, #0 8012e44: d1e4 bne.n 8012e10 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8012e46: e007 b.n 8012e58 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8012e48: 687b ldr r3, [r7, #4] 8012e4a: 681b ldr r3, [r3, #0] 8012e4c: 699a ldr r2, [r3, #24] 8012e4e: 687b ldr r3, [r7, #4] 8012e50: 681b ldr r3, [r3, #0] 8012e52: f042 0208 orr.w r2, r2, #8 8012e56: 619a str r2, [r3, #24] } 8012e58: bf00 nop 8012e5a: 37b0 adds r7, #176 @ 0xb0 8012e5c: 46bd mov sp, r7 8012e5e: bd80 pop {r7, pc} 8012e60: effffffe .word 0xeffffffe 8012e64: 58000c00 .word 0x58000c00 8012e68: 0801279d .word 0x0801279d 08012e6c : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 8012e6c: b580 push {r7, lr} 8012e6e: b0ae sub sp, #184 @ 0xb8 8012e70: af00 add r7, sp, #0 8012e72: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 8012e74: 687b ldr r3, [r7, #4] 8012e76: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8012e7a: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2 uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 8012e7e: 687b ldr r3, [r7, #4] 8012e80: 681b ldr r3, [r3, #0] 8012e82: 69db ldr r3, [r3, #28] 8012e84: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8012e88: 687b ldr r3, [r7, #4] 8012e8a: 681b ldr r3, [r3, #0] 8012e8c: 681b ldr r3, [r3, #0] 8012e8e: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr3its = READ_REG(huart->Instance->CR3); 8012e92: 687b ldr r3, [r7, #4] 8012e94: 681b ldr r3, [r3, #0] 8012e96: 689b ldr r3, [r3, #8] 8012e98: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8012e9c: 687b ldr r3, [r7, #4] 8012e9e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8012ea2: 2b22 cmp r3, #34 @ 0x22 8012ea4: f040 8184 bne.w 80131b0 { nb_rx_data = huart->NbRxDataToProcess; 8012ea8: 687b ldr r3, [r7, #4] 8012eaa: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8012eae: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8012eb2: e127 b.n 8013104 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8012eb4: 687b ldr r3, [r7, #4] 8012eb6: 681b ldr r3, [r3, #0] 8012eb8: 6a5b ldr r3, [r3, #36] @ 0x24 8012eba: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4 tmp = (uint16_t *) huart->pRxBuffPtr ; 8012ebe: 687b ldr r3, [r7, #4] 8012ec0: 6d9b ldr r3, [r3, #88] @ 0x58 8012ec2: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 *tmp = (uint16_t)(uhdata & uhMask); 8012ec6: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4 8012eca: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2 8012ece: 4013 ands r3, r2 8012ed0: b29a uxth r2, r3 8012ed2: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8012ed6: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8012ed8: 687b ldr r3, [r7, #4] 8012eda: 6d9b ldr r3, [r3, #88] @ 0x58 8012edc: 1c9a adds r2, r3, #2 8012ede: 687b ldr r3, [r7, #4] 8012ee0: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8012ee2: 687b ldr r3, [r7, #4] 8012ee4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012ee8: b29b uxth r3, r3 8012eea: 3b01 subs r3, #1 8012eec: b29a uxth r2, r3 8012eee: 687b ldr r3, [r7, #4] 8012ef0: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 8012ef4: 687b ldr r3, [r7, #4] 8012ef6: 681b ldr r3, [r3, #0] 8012ef8: 69db ldr r3, [r3, #28] 8012efa: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8012efe: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8012f02: f003 0307 and.w r3, r3, #7 8012f06: 2b00 cmp r3, #0 8012f08: d053 beq.n 8012fb2 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8012f0a: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8012f0e: f003 0301 and.w r3, r3, #1 8012f12: 2b00 cmp r3, #0 8012f14: d011 beq.n 8012f3a 8012f16: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012f1a: f403 7380 and.w r3, r3, #256 @ 0x100 8012f1e: 2b00 cmp r3, #0 8012f20: d00b beq.n 8012f3a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8012f22: 687b ldr r3, [r7, #4] 8012f24: 681b ldr r3, [r3, #0] 8012f26: 2201 movs r2, #1 8012f28: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8012f2a: 687b ldr r3, [r7, #4] 8012f2c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012f30: f043 0201 orr.w r2, r3, #1 8012f34: 687b ldr r3, [r7, #4] 8012f36: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8012f3a: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8012f3e: f003 0302 and.w r3, r3, #2 8012f42: 2b00 cmp r3, #0 8012f44: d011 beq.n 8012f6a 8012f46: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8012f4a: f003 0301 and.w r3, r3, #1 8012f4e: 2b00 cmp r3, #0 8012f50: d00b beq.n 8012f6a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8012f52: 687b ldr r3, [r7, #4] 8012f54: 681b ldr r3, [r3, #0] 8012f56: 2202 movs r2, #2 8012f58: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8012f5a: 687b ldr r3, [r7, #4] 8012f5c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012f60: f043 0204 orr.w r2, r3, #4 8012f64: 687b ldr r3, [r7, #4] 8012f66: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8012f6a: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8012f6e: f003 0304 and.w r3, r3, #4 8012f72: 2b00 cmp r3, #0 8012f74: d011 beq.n 8012f9a 8012f76: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8012f7a: f003 0301 and.w r3, r3, #1 8012f7e: 2b00 cmp r3, #0 8012f80: d00b beq.n 8012f9a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8012f82: 687b ldr r3, [r7, #4] 8012f84: 681b ldr r3, [r3, #0] 8012f86: 2204 movs r2, #4 8012f88: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8012f8a: 687b ldr r3, [r7, #4] 8012f8c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012f90: f043 0202 orr.w r2, r3, #2 8012f94: 687b ldr r3, [r7, #4] 8012f96: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8012f9a: 687b ldr r3, [r7, #4] 8012f9c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012fa0: 2b00 cmp r3, #0 8012fa2: d006 beq.n 8012fb2 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8012fa4: 6878 ldr r0, [r7, #4] 8012fa6: f7fe f961 bl 801126c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012faa: 687b ldr r3, [r7, #4] 8012fac: 2200 movs r2, #0 8012fae: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 8012fb2: 687b ldr r3, [r7, #4] 8012fb4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012fb8: b29b uxth r3, r3 8012fba: 2b00 cmp r3, #0 8012fbc: f040 80a2 bne.w 8013104 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8012fc0: 687b ldr r3, [r7, #4] 8012fc2: 681b ldr r3, [r3, #0] 8012fc4: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012fc6: 6f7b ldr r3, [r7, #116] @ 0x74 8012fc8: e853 3f00 ldrex r3, [r3] 8012fcc: 673b str r3, [r7, #112] @ 0x70 return(result); 8012fce: 6f3b ldr r3, [r7, #112] @ 0x70 8012fd0: f423 7380 bic.w r3, r3, #256 @ 0x100 8012fd4: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8012fd8: 687b ldr r3, [r7, #4] 8012fda: 681b ldr r3, [r3, #0] 8012fdc: 461a mov r2, r3 8012fde: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8012fe2: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8012fe6: 67fa str r2, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012fe8: 6ff9 ldr r1, [r7, #124] @ 0x7c 8012fea: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8012fee: e841 2300 strex r3, r2, [r1] 8012ff2: 67bb str r3, [r7, #120] @ 0x78 return(result); 8012ff4: 6fbb ldr r3, [r7, #120] @ 0x78 8012ff6: 2b00 cmp r3, #0 8012ff8: d1e2 bne.n 8012fc0 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8012ffa: 687b ldr r3, [r7, #4] 8012ffc: 681b ldr r3, [r3, #0] 8012ffe: 3308 adds r3, #8 8013000: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013002: 6e3b ldr r3, [r7, #96] @ 0x60 8013004: e853 3f00 ldrex r3, [r3] 8013008: 65fb str r3, [r7, #92] @ 0x5c return(result); 801300a: 6dfa ldr r2, [r7, #92] @ 0x5c 801300c: 4b6e ldr r3, [pc, #440] @ (80131c8 ) 801300e: 4013 ands r3, r2 8013010: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8013014: 687b ldr r3, [r7, #4] 8013016: 681b ldr r3, [r3, #0] 8013018: 3308 adds r3, #8 801301a: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98 801301e: 66fa str r2, [r7, #108] @ 0x6c 8013020: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013022: 6eb9 ldr r1, [r7, #104] @ 0x68 8013024: 6efa ldr r2, [r7, #108] @ 0x6c 8013026: e841 2300 strex r3, r2, [r1] 801302a: 667b str r3, [r7, #100] @ 0x64 return(result); 801302c: 6e7b ldr r3, [r7, #100] @ 0x64 801302e: 2b00 cmp r3, #0 8013030: d1e3 bne.n 8012ffa /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013032: 687b ldr r3, [r7, #4] 8013034: 2220 movs r2, #32 8013036: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 801303a: 687b ldr r3, [r7, #4] 801303c: 2200 movs r2, #0 801303e: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8013040: 687b ldr r3, [r7, #4] 8013042: 2200 movs r2, #0 8013044: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8013046: 687b ldr r3, [r7, #4] 8013048: 681b ldr r3, [r3, #0] 801304a: 4a60 ldr r2, [pc, #384] @ (80131cc ) 801304c: 4293 cmp r3, r2 801304e: d021 beq.n 8013094 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8013050: 687b ldr r3, [r7, #4] 8013052: 681b ldr r3, [r3, #0] 8013054: 685b ldr r3, [r3, #4] 8013056: f403 0300 and.w r3, r3, #8388608 @ 0x800000 801305a: 2b00 cmp r3, #0 801305c: d01a beq.n 8013094 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 801305e: 687b ldr r3, [r7, #4] 8013060: 681b ldr r3, [r3, #0] 8013062: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013064: 6cfb ldr r3, [r7, #76] @ 0x4c 8013066: e853 3f00 ldrex r3, [r3] 801306a: 64bb str r3, [r7, #72] @ 0x48 return(result); 801306c: 6cbb ldr r3, [r7, #72] @ 0x48 801306e: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8013072: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8013076: 687b ldr r3, [r7, #4] 8013078: 681b ldr r3, [r3, #0] 801307a: 461a mov r2, r3 801307c: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 8013080: 65bb str r3, [r7, #88] @ 0x58 8013082: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013084: 6d79 ldr r1, [r7, #84] @ 0x54 8013086: 6dba ldr r2, [r7, #88] @ 0x58 8013088: e841 2300 strex r3, r2, [r1] 801308c: 653b str r3, [r7, #80] @ 0x50 return(result); 801308e: 6d3b ldr r3, [r7, #80] @ 0x50 8013090: 2b00 cmp r3, #0 8013092: d1e4 bne.n 801305e } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013094: 687b ldr r3, [r7, #4] 8013096: 6edb ldr r3, [r3, #108] @ 0x6c 8013098: 2b01 cmp r3, #1 801309a: d130 bne.n 80130fe { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801309c: 687b ldr r3, [r7, #4] 801309e: 2200 movs r2, #0 80130a0: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80130a2: 687b ldr r3, [r7, #4] 80130a4: 681b ldr r3, [r3, #0] 80130a6: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80130a8: 6bbb ldr r3, [r7, #56] @ 0x38 80130aa: e853 3f00 ldrex r3, [r3] 80130ae: 637b str r3, [r7, #52] @ 0x34 return(result); 80130b0: 6b7b ldr r3, [r7, #52] @ 0x34 80130b2: f023 0310 bic.w r3, r3, #16 80130b6: f8c7 3090 str.w r3, [r7, #144] @ 0x90 80130ba: 687b ldr r3, [r7, #4] 80130bc: 681b ldr r3, [r3, #0] 80130be: 461a mov r2, r3 80130c0: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 80130c4: 647b str r3, [r7, #68] @ 0x44 80130c6: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80130c8: 6c39 ldr r1, [r7, #64] @ 0x40 80130ca: 6c7a ldr r2, [r7, #68] @ 0x44 80130cc: e841 2300 strex r3, r2, [r1] 80130d0: 63fb str r3, [r7, #60] @ 0x3c return(result); 80130d2: 6bfb ldr r3, [r7, #60] @ 0x3c 80130d4: 2b00 cmp r3, #0 80130d6: d1e4 bne.n 80130a2 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 80130d8: 687b ldr r3, [r7, #4] 80130da: 681b ldr r3, [r3, #0] 80130dc: 69db ldr r3, [r3, #28] 80130de: f003 0310 and.w r3, r3, #16 80130e2: 2b10 cmp r3, #16 80130e4: d103 bne.n 80130ee { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 80130e6: 687b ldr r3, [r7, #4] 80130e8: 681b ldr r3, [r3, #0] 80130ea: 2210 movs r2, #16 80130ec: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 80130ee: 687b ldr r3, [r7, #4] 80130f0: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 80130f4: 4619 mov r1, r3 80130f6: 6878 ldr r0, [r7, #4] 80130f8: f7f1 fc5c bl 80049b4 80130fc: e002 b.n 8013104 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 80130fe: 6878 ldr r0, [r7, #4] 8013100: f7f1 fc4e bl 80049a0 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8013104: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6 8013108: 2b00 cmp r3, #0 801310a: d006 beq.n 801311a 801310c: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8013110: f003 0320 and.w r3, r3, #32 8013114: 2b00 cmp r3, #0 8013116: f47f aecd bne.w 8012eb4 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 801311a: 687b ldr r3, [r7, #4] 801311c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013120: f8a7 308e strh.w r3, [r7, #142] @ 0x8e if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 8013124: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e 8013128: 2b00 cmp r3, #0 801312a: d049 beq.n 80131c0 801312c: 687b ldr r3, [r7, #4] 801312e: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8013132: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e 8013136: 429a cmp r2, r3 8013138: d242 bcs.n 80131c0 { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 801313a: 687b ldr r3, [r7, #4] 801313c: 681b ldr r3, [r3, #0] 801313e: 3308 adds r3, #8 8013140: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013142: 6a7b ldr r3, [r7, #36] @ 0x24 8013144: e853 3f00 ldrex r3, [r3] 8013148: 623b str r3, [r7, #32] return(result); 801314a: 6a3b ldr r3, [r7, #32] 801314c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8013150: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8013154: 687b ldr r3, [r7, #4] 8013156: 681b ldr r3, [r3, #0] 8013158: 3308 adds r3, #8 801315a: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88 801315e: 633a str r2, [r7, #48] @ 0x30 8013160: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013162: 6af9 ldr r1, [r7, #44] @ 0x2c 8013164: 6b3a ldr r2, [r7, #48] @ 0x30 8013166: e841 2300 strex r3, r2, [r1] 801316a: 62bb str r3, [r7, #40] @ 0x28 return(result); 801316c: 6abb ldr r3, [r7, #40] @ 0x28 801316e: 2b00 cmp r3, #0 8013170: d1e3 bne.n 801313a /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; 8013172: 687b ldr r3, [r7, #4] 8013174: 4a16 ldr r2, [pc, #88] @ (80131d0 ) 8013176: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8013178: 687b ldr r3, [r7, #4] 801317a: 681b ldr r3, [r3, #0] 801317c: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801317e: 693b ldr r3, [r7, #16] 8013180: e853 3f00 ldrex r3, [r3] 8013184: 60fb str r3, [r7, #12] return(result); 8013186: 68fb ldr r3, [r7, #12] 8013188: f043 0320 orr.w r3, r3, #32 801318c: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8013190: 687b ldr r3, [r7, #4] 8013192: 681b ldr r3, [r3, #0] 8013194: 461a mov r2, r3 8013196: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 801319a: 61fb str r3, [r7, #28] 801319c: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801319e: 69b9 ldr r1, [r7, #24] 80131a0: 69fa ldr r2, [r7, #28] 80131a2: e841 2300 strex r3, r2, [r1] 80131a6: 617b str r3, [r7, #20] return(result); 80131a8: 697b ldr r3, [r7, #20] 80131aa: 2b00 cmp r3, #0 80131ac: d1e4 bne.n 8013178 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 80131ae: e007 b.n 80131c0 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 80131b0: 687b ldr r3, [r7, #4] 80131b2: 681b ldr r3, [r3, #0] 80131b4: 699a ldr r2, [r3, #24] 80131b6: 687b ldr r3, [r7, #4] 80131b8: 681b ldr r3, [r3, #0] 80131ba: f042 0208 orr.w r2, r2, #8 80131be: 619a str r2, [r3, #24] } 80131c0: bf00 nop 80131c2: 37b8 adds r7, #184 @ 0xb8 80131c4: 46bd mov sp, r7 80131c6: bd80 pop {r7, pc} 80131c8: effffffe .word 0xeffffffe 80131cc: 58000c00 .word 0x58000c00 80131d0: 08012955 .word 0x08012955 080131d4 : * @brief UART wakeup from Stop mode callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { 80131d4: b480 push {r7} 80131d6: b083 sub sp, #12 80131d8: af00 add r7, sp, #0 80131da: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } 80131dc: bf00 nop 80131de: 370c adds r7, #12 80131e0: 46bd mov sp, r7 80131e2: f85d 7b04 ldr.w r7, [sp], #4 80131e6: 4770 bx lr 080131e8 : * @brief UART RX Fifo full callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { 80131e8: b480 push {r7} 80131ea: b083 sub sp, #12 80131ec: af00 add r7, sp, #0 80131ee: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. */ } 80131f0: bf00 nop 80131f2: 370c adds r7, #12 80131f4: 46bd mov sp, r7 80131f6: f85d 7b04 ldr.w r7, [sp], #4 80131fa: 4770 bx lr 080131fc : * @brief UART TX Fifo empty callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { 80131fc: b480 push {r7} 80131fe: b083 sub sp, #12 8013200: af00 add r7, sp, #0 8013202: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } 8013204: bf00 nop 8013206: 370c adds r7, #12 8013208: 46bd mov sp, r7 801320a: f85d 7b04 ldr.w r7, [sp], #4 801320e: 4770 bx lr 08013210 : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 8013210: b480 push {r7} 8013212: b085 sub sp, #20 8013214: af00 add r7, sp, #0 8013216: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 8013218: 687b ldr r3, [r7, #4] 801321a: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 801321e: 2b01 cmp r3, #1 8013220: d101 bne.n 8013226 8013222: 2302 movs r3, #2 8013224: e027 b.n 8013276 8013226: 687b ldr r3, [r7, #4] 8013228: 2201 movs r2, #1 801322a: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 801322e: 687b ldr r3, [r7, #4] 8013230: 2224 movs r2, #36 @ 0x24 8013232: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8013236: 687b ldr r3, [r7, #4] 8013238: 681b ldr r3, [r3, #0] 801323a: 681b ldr r3, [r3, #0] 801323c: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 801323e: 687b ldr r3, [r7, #4] 8013240: 681b ldr r3, [r3, #0] 8013242: 681a ldr r2, [r3, #0] 8013244: 687b ldr r3, [r7, #4] 8013246: 681b ldr r3, [r3, #0] 8013248: f022 0201 bic.w r2, r2, #1 801324c: 601a str r2, [r3, #0] /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 801324e: 68fb ldr r3, [r7, #12] 8013250: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000 8013254: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 8013256: 687b ldr r3, [r7, #4] 8013258: 2200 movs r2, #0 801325a: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 801325c: 687b ldr r3, [r7, #4] 801325e: 681b ldr r3, [r3, #0] 8013260: 68fa ldr r2, [r7, #12] 8013262: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8013264: 687b ldr r3, [r7, #4] 8013266: 2220 movs r2, #32 8013268: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 801326c: 687b ldr r3, [r7, #4] 801326e: 2200 movs r2, #0 8013270: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8013274: 2300 movs r3, #0 } 8013276: 4618 mov r0, r3 8013278: 3714 adds r7, #20 801327a: 46bd mov sp, r7 801327c: f85d 7b04 ldr.w r7, [sp], #4 8013280: 4770 bx lr 08013282 : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8013282: b580 push {r7, lr} 8013284: b084 sub sp, #16 8013286: af00 add r7, sp, #0 8013288: 6078 str r0, [r7, #4] 801328a: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 801328c: 687b ldr r3, [r7, #4] 801328e: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8013292: 2b01 cmp r3, #1 8013294: d101 bne.n 801329a 8013296: 2302 movs r3, #2 8013298: e02d b.n 80132f6 801329a: 687b ldr r3, [r7, #4] 801329c: 2201 movs r2, #1 801329e: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 80132a2: 687b ldr r3, [r7, #4] 80132a4: 2224 movs r2, #36 @ 0x24 80132a6: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 80132aa: 687b ldr r3, [r7, #4] 80132ac: 681b ldr r3, [r3, #0] 80132ae: 681b ldr r3, [r3, #0] 80132b0: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 80132b2: 687b ldr r3, [r7, #4] 80132b4: 681b ldr r3, [r3, #0] 80132b6: 681a ldr r2, [r3, #0] 80132b8: 687b ldr r3, [r7, #4] 80132ba: 681b ldr r3, [r3, #0] 80132bc: f022 0201 bic.w r2, r2, #1 80132c0: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 80132c2: 687b ldr r3, [r7, #4] 80132c4: 681b ldr r3, [r3, #0] 80132c6: 689b ldr r3, [r3, #8] 80132c8: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 80132cc: 687b ldr r3, [r7, #4] 80132ce: 681b ldr r3, [r3, #0] 80132d0: 683a ldr r2, [r7, #0] 80132d2: 430a orrs r2, r1 80132d4: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 80132d6: 6878 ldr r0, [r7, #4] 80132d8: f000 f8a0 bl 801341c /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 80132dc: 687b ldr r3, [r7, #4] 80132de: 681b ldr r3, [r3, #0] 80132e0: 68fa ldr r2, [r7, #12] 80132e2: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 80132e4: 687b ldr r3, [r7, #4] 80132e6: 2220 movs r2, #32 80132e8: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 80132ec: 687b ldr r3, [r7, #4] 80132ee: 2200 movs r2, #0 80132f0: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 80132f4: 2300 movs r3, #0 } 80132f6: 4618 mov r0, r3 80132f8: 3710 adds r7, #16 80132fa: 46bd mov sp, r7 80132fc: bd80 pop {r7, pc} 080132fe : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 80132fe: b580 push {r7, lr} 8013300: b084 sub sp, #16 8013302: af00 add r7, sp, #0 8013304: 6078 str r0, [r7, #4] 8013306: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8013308: 687b ldr r3, [r7, #4] 801330a: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 801330e: 2b01 cmp r3, #1 8013310: d101 bne.n 8013316 8013312: 2302 movs r3, #2 8013314: e02d b.n 8013372 8013316: 687b ldr r3, [r7, #4] 8013318: 2201 movs r2, #1 801331a: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 801331e: 687b ldr r3, [r7, #4] 8013320: 2224 movs r2, #36 @ 0x24 8013322: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8013326: 687b ldr r3, [r7, #4] 8013328: 681b ldr r3, [r3, #0] 801332a: 681b ldr r3, [r3, #0] 801332c: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 801332e: 687b ldr r3, [r7, #4] 8013330: 681b ldr r3, [r3, #0] 8013332: 681a ldr r2, [r3, #0] 8013334: 687b ldr r3, [r7, #4] 8013336: 681b ldr r3, [r3, #0] 8013338: f022 0201 bic.w r2, r2, #1 801333c: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 801333e: 687b ldr r3, [r7, #4] 8013340: 681b ldr r3, [r3, #0] 8013342: 689b ldr r3, [r3, #8] 8013344: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 8013348: 687b ldr r3, [r7, #4] 801334a: 681b ldr r3, [r3, #0] 801334c: 683a ldr r2, [r7, #0] 801334e: 430a orrs r2, r1 8013350: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8013352: 6878 ldr r0, [r7, #4] 8013354: f000 f862 bl 801341c /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8013358: 687b ldr r3, [r7, #4] 801335a: 681b ldr r3, [r3, #0] 801335c: 68fa ldr r2, [r7, #12] 801335e: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8013360: 687b ldr r3, [r7, #4] 8013362: 2220 movs r2, #32 8013364: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8013368: 687b ldr r3, [r7, #4] 801336a: 2200 movs r2, #0 801336c: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8013370: 2300 movs r3, #0 } 8013372: 4618 mov r0, r3 8013374: 3710 adds r7, #16 8013376: 46bd mov sp, r7 8013378: bd80 pop {r7, pc} 0801337a : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 801337a: b580 push {r7, lr} 801337c: b08c sub sp, #48 @ 0x30 801337e: af00 add r7, sp, #0 8013380: 60f8 str r0, [r7, #12] 8013382: 60b9 str r1, [r7, #8] 8013384: 4613 mov r3, r2 8013386: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status = HAL_OK; 8013388: 2300 movs r3, #0 801338a: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 801338e: 68fb ldr r3, [r7, #12] 8013390: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8013394: 2b20 cmp r3, #32 8013396: d13b bne.n 8013410 { if ((pData == NULL) || (Size == 0U)) 8013398: 68bb ldr r3, [r7, #8] 801339a: 2b00 cmp r3, #0 801339c: d002 beq.n 80133a4 801339e: 88fb ldrh r3, [r7, #6] 80133a0: 2b00 cmp r3, #0 80133a2: d101 bne.n 80133a8 { return HAL_ERROR; 80133a4: 2301 movs r3, #1 80133a6: e034 b.n 8013412 } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 80133a8: 68fb ldr r3, [r7, #12] 80133aa: 2201 movs r2, #1 80133ac: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 80133ae: 68fb ldr r3, [r7, #12] 80133b0: 2200 movs r2, #0 80133b2: 671a str r2, [r3, #112] @ 0x70 (void)UART_Start_Receive_IT(huart, pData, Size); 80133b4: 88fb ldrh r3, [r7, #6] 80133b6: 461a mov r2, r3 80133b8: 68b9 ldr r1, [r7, #8] 80133ba: 68f8 ldr r0, [r7, #12] 80133bc: f7fe fe82 bl 80120c4 if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80133c0: 68fb ldr r3, [r7, #12] 80133c2: 6edb ldr r3, [r3, #108] @ 0x6c 80133c4: 2b01 cmp r3, #1 80133c6: d11d bne.n 8013404 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 80133c8: 68fb ldr r3, [r7, #12] 80133ca: 681b ldr r3, [r3, #0] 80133cc: 2210 movs r2, #16 80133ce: 621a str r2, [r3, #32] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80133d0: 68fb ldr r3, [r7, #12] 80133d2: 681b ldr r3, [r3, #0] 80133d4: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80133d6: 69bb ldr r3, [r7, #24] 80133d8: e853 3f00 ldrex r3, [r3] 80133dc: 617b str r3, [r7, #20] return(result); 80133de: 697b ldr r3, [r7, #20] 80133e0: f043 0310 orr.w r3, r3, #16 80133e4: 62bb str r3, [r7, #40] @ 0x28 80133e6: 68fb ldr r3, [r7, #12] 80133e8: 681b ldr r3, [r3, #0] 80133ea: 461a mov r2, r3 80133ec: 6abb ldr r3, [r7, #40] @ 0x28 80133ee: 627b str r3, [r7, #36] @ 0x24 80133f0: 623a str r2, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80133f2: 6a39 ldr r1, [r7, #32] 80133f4: 6a7a ldr r2, [r7, #36] @ 0x24 80133f6: e841 2300 strex r3, r2, [r1] 80133fa: 61fb str r3, [r7, #28] return(result); 80133fc: 69fb ldr r3, [r7, #28] 80133fe: 2b00 cmp r3, #0 8013400: d1e6 bne.n 80133d0 8013402: e002 b.n 801340a { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8013404: 2301 movs r3, #1 8013406: f887 302f strb.w r3, [r7, #47] @ 0x2f } return status; 801340a: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 801340e: e000 b.n 8013412 } else { return HAL_BUSY; 8013410: 2302 movs r3, #2 } } 8013412: 4618 mov r0, r3 8013414: 3730 adds r7, #48 @ 0x30 8013416: 46bd mov sp, r7 8013418: bd80 pop {r7, pc} ... 0801341c : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 801341c: b480 push {r7} 801341e: b085 sub sp, #20 8013420: af00 add r7, sp, #0 8013422: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 8013424: 687b ldr r3, [r7, #4] 8013426: 6e5b ldr r3, [r3, #100] @ 0x64 8013428: 2b00 cmp r3, #0 801342a: d108 bne.n 801343e { huart->NbTxDataToProcess = 1U; 801342c: 687b ldr r3, [r7, #4] 801342e: 2201 movs r2, #1 8013430: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1U; 8013434: 687b ldr r3, [r7, #4] 8013436: 2201 movs r2, #1 8013438: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 801343c: e031 b.n 80134a2 rx_fifo_depth = RX_FIFO_DEPTH; 801343e: 2310 movs r3, #16 8013440: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 8013442: 2310 movs r3, #16 8013444: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 8013446: 687b ldr r3, [r7, #4] 8013448: 681b ldr r3, [r3, #0] 801344a: 689b ldr r3, [r3, #8] 801344c: 0e5b lsrs r3, r3, #25 801344e: b2db uxtb r3, r3 8013450: f003 0307 and.w r3, r3, #7 8013454: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 8013456: 687b ldr r3, [r7, #4] 8013458: 681b ldr r3, [r3, #0] 801345a: 689b ldr r3, [r3, #8] 801345c: 0f5b lsrs r3, r3, #29 801345e: b2db uxtb r3, r3 8013460: f003 0307 and.w r3, r3, #7 8013464: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8013466: 7bbb ldrb r3, [r7, #14] 8013468: 7b3a ldrb r2, [r7, #12] 801346a: 4911 ldr r1, [pc, #68] @ (80134b0 ) 801346c: 5c8a ldrb r2, [r1, r2] 801346e: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 8013472: 7b3a ldrb r2, [r7, #12] 8013474: 490f ldr r1, [pc, #60] @ (80134b4 ) 8013476: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8013478: fb93 f3f2 sdiv r3, r3, r2 801347c: b29a uxth r2, r3 801347e: 687b ldr r3, [r7, #4] 8013480: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8013484: 7bfb ldrb r3, [r7, #15] 8013486: 7b7a ldrb r2, [r7, #13] 8013488: 4909 ldr r1, [pc, #36] @ (80134b0 ) 801348a: 5c8a ldrb r2, [r1, r2] 801348c: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 8013490: 7b7a ldrb r2, [r7, #13] 8013492: 4908 ldr r1, [pc, #32] @ (80134b4 ) 8013494: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8013496: fb93 f3f2 sdiv r3, r3, r2 801349a: b29a uxth r2, r3 801349c: 687b ldr r3, [r7, #4] 801349e: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 } 80134a2: bf00 nop 80134a4: 3714 adds r7, #20 80134a6: 46bd mov sp, r7 80134a8: f85d 7b04 ldr.w r7, [sp], #4 80134ac: 4770 bx lr 80134ae: bf00 nop 80134b0: 08018b8c .word 0x08018b8c 80134b4: 08018b94 .word 0x08018b94 080134b8 <__NVIC_SetPriority>: { 80134b8: b480 push {r7} 80134ba: b083 sub sp, #12 80134bc: af00 add r7, sp, #0 80134be: 4603 mov r3, r0 80134c0: 6039 str r1, [r7, #0] 80134c2: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 80134c4: f9b7 3006 ldrsh.w r3, [r7, #6] 80134c8: 2b00 cmp r3, #0 80134ca: db0a blt.n 80134e2 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80134cc: 683b ldr r3, [r7, #0] 80134ce: b2da uxtb r2, r3 80134d0: 490c ldr r1, [pc, #48] @ (8013504 <__NVIC_SetPriority+0x4c>) 80134d2: f9b7 3006 ldrsh.w r3, [r7, #6] 80134d6: 0112 lsls r2, r2, #4 80134d8: b2d2 uxtb r2, r2 80134da: 440b add r3, r1 80134dc: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 80134e0: e00a b.n 80134f8 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80134e2: 683b ldr r3, [r7, #0] 80134e4: b2da uxtb r2, r3 80134e6: 4908 ldr r1, [pc, #32] @ (8013508 <__NVIC_SetPriority+0x50>) 80134e8: 88fb ldrh r3, [r7, #6] 80134ea: f003 030f and.w r3, r3, #15 80134ee: 3b04 subs r3, #4 80134f0: 0112 lsls r2, r2, #4 80134f2: b2d2 uxtb r2, r2 80134f4: 440b add r3, r1 80134f6: 761a strb r2, [r3, #24] } 80134f8: bf00 nop 80134fa: 370c adds r7, #12 80134fc: 46bd mov sp, r7 80134fe: f85d 7b04 ldr.w r7, [sp], #4 8013502: 4770 bx lr 8013504: e000e100 .word 0xe000e100 8013508: e000ed00 .word 0xe000ed00 0801350c : /* SysTick handler implementation that also clears overflow flag. */ #if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) void SysTick_Handler (void) { 801350c: b580 push {r7, lr} 801350e: af00 add r7, sp, #0 /* Clear overflow flag */ SysTick->CTRL; 8013510: 4b05 ldr r3, [pc, #20] @ (8013528 ) 8013512: 681b ldr r3, [r3, #0] if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { 8013514: f002 fd1e bl 8015f54 8013518: 4603 mov r3, r0 801351a: 2b01 cmp r3, #1 801351c: d001 beq.n 8013522 /* Call tick handler */ xPortSysTickHandler(); 801351e: f003 ff2b bl 8017378 } } 8013522: bf00 nop 8013524: bd80 pop {r7, pc} 8013526: bf00 nop 8013528: e000e010 .word 0xe000e010 0801352c : #endif /* SysTick */ /* Setup SVC to reset value. */ __STATIC_INLINE void SVC_Setup (void) { 801352c: b580 push {r7, lr} 801352e: af00 add r7, sp, #0 #if (__ARM_ARCH_7A__ == 0U) /* Service Call interrupt might be configured before kernel start */ /* and when its priority is lower or equal to BASEPRI, svc intruction */ /* causes a Hard Fault. */ NVIC_SetPriority (SVCall_IRQ_NBR, 0U); 8013530: 2100 movs r1, #0 8013532: f06f 0004 mvn.w r0, #4 8013536: f7ff ffbf bl 80134b8 <__NVIC_SetPriority> #endif } 801353a: bf00 nop 801353c: bd80 pop {r7, pc} ... 08013540 : static uint32_t OS_Tick_GetOverflow (void); /* Get OS Tick interval */ static uint32_t OS_Tick_GetInterval (void); /*---------------------------------------------------------------------------*/ osStatus_t osKernelInitialize (void) { 8013540: b480 push {r7} 8013542: b083 sub sp, #12 8013544: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013546: f3ef 8305 mrs r3, IPSR 801354a: 603b str r3, [r7, #0] return(result); 801354c: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 801354e: 2b00 cmp r3, #0 8013550: d003 beq.n 801355a stat = osErrorISR; 8013552: f06f 0305 mvn.w r3, #5 8013556: 607b str r3, [r7, #4] 8013558: e00c b.n 8013574 } else { if (KernelState == osKernelInactive) { 801355a: 4b0a ldr r3, [pc, #40] @ (8013584 ) 801355c: 681b ldr r3, [r3, #0] 801355e: 2b00 cmp r3, #0 8013560: d105 bne.n 801356e EvrFreeRTOSSetup(0U); #endif #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) vPortDefineHeapRegions (configHEAP_5_REGIONS); #endif KernelState = osKernelReady; 8013562: 4b08 ldr r3, [pc, #32] @ (8013584 ) 8013564: 2201 movs r2, #1 8013566: 601a str r2, [r3, #0] stat = osOK; 8013568: 2300 movs r3, #0 801356a: 607b str r3, [r7, #4] 801356c: e002 b.n 8013574 } else { stat = osError; 801356e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8013572: 607b str r3, [r7, #4] } } return (stat); 8013574: 687b ldr r3, [r7, #4] } 8013576: 4618 mov r0, r3 8013578: 370c adds r7, #12 801357a: 46bd mov sp, r7 801357c: f85d 7b04 ldr.w r7, [sp], #4 8013580: 4770 bx lr 8013582: bf00 nop 8013584: 24001080 .word 0x24001080 08013588 : } return (state); } osStatus_t osKernelStart (void) { 8013588: b580 push {r7, lr} 801358a: b082 sub sp, #8 801358c: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801358e: f3ef 8305 mrs r3, IPSR 8013592: 603b str r3, [r7, #0] return(result); 8013594: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 8013596: 2b00 cmp r3, #0 8013598: d003 beq.n 80135a2 stat = osErrorISR; 801359a: f06f 0305 mvn.w r3, #5 801359e: 607b str r3, [r7, #4] 80135a0: e010 b.n 80135c4 } else { if (KernelState == osKernelReady) { 80135a2: 4b0b ldr r3, [pc, #44] @ (80135d0 ) 80135a4: 681b ldr r3, [r3, #0] 80135a6: 2b01 cmp r3, #1 80135a8: d109 bne.n 80135be /* Ensure SVC priority is at the reset value */ SVC_Setup(); 80135aa: f7ff ffbf bl 801352c /* Change state to enable IRQ masking check */ KernelState = osKernelRunning; 80135ae: 4b08 ldr r3, [pc, #32] @ (80135d0 ) 80135b0: 2202 movs r2, #2 80135b2: 601a str r2, [r3, #0] /* Start the kernel scheduler */ vTaskStartScheduler(); 80135b4: f002 f824 bl 8015600 stat = osOK; 80135b8: 2300 movs r3, #0 80135ba: 607b str r3, [r7, #4] 80135bc: e002 b.n 80135c4 } else { stat = osError; 80135be: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80135c2: 607b str r3, [r7, #4] } } return (stat); 80135c4: 687b ldr r3, [r7, #4] } 80135c6: 4618 mov r0, r3 80135c8: 3708 adds r7, #8 80135ca: 46bd mov sp, r7 80135cc: bd80 pop {r7, pc} 80135ce: bf00 nop 80135d0: 24001080 .word 0x24001080 080135d4 : return (configCPU_CLOCK_HZ); } /*---------------------------------------------------------------------------*/ osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { 80135d4: b580 push {r7, lr} 80135d6: b08e sub sp, #56 @ 0x38 80135d8: af04 add r7, sp, #16 80135da: 60f8 str r0, [r7, #12] 80135dc: 60b9 str r1, [r7, #8] 80135de: 607a str r2, [r7, #4] uint32_t stack; TaskHandle_t hTask; UBaseType_t prio; int32_t mem; hTask = NULL; 80135e0: 2300 movs r3, #0 80135e2: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80135e4: f3ef 8305 mrs r3, IPSR 80135e8: 617b str r3, [r7, #20] return(result); 80135ea: 697b ldr r3, [r7, #20] if (!IS_IRQ() && (func != NULL)) { 80135ec: 2b00 cmp r3, #0 80135ee: d17f bne.n 80136f0 80135f0: 68fb ldr r3, [r7, #12] 80135f2: 2b00 cmp r3, #0 80135f4: d07c beq.n 80136f0 stack = configMINIMAL_STACK_SIZE; 80135f6: f44f 7300 mov.w r3, #512 @ 0x200 80135fa: 623b str r3, [r7, #32] prio = (UBaseType_t)osPriorityNormal; 80135fc: 2318 movs r3, #24 80135fe: 61fb str r3, [r7, #28] name = NULL; 8013600: 2300 movs r3, #0 8013602: 627b str r3, [r7, #36] @ 0x24 mem = -1; 8013604: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8013608: 61bb str r3, [r7, #24] if (attr != NULL) { 801360a: 687b ldr r3, [r7, #4] 801360c: 2b00 cmp r3, #0 801360e: d045 beq.n 801369c if (attr->name != NULL) { 8013610: 687b ldr r3, [r7, #4] 8013612: 681b ldr r3, [r3, #0] 8013614: 2b00 cmp r3, #0 8013616: d002 beq.n 801361e name = attr->name; 8013618: 687b ldr r3, [r7, #4] 801361a: 681b ldr r3, [r3, #0] 801361c: 627b str r3, [r7, #36] @ 0x24 } if (attr->priority != osPriorityNone) { 801361e: 687b ldr r3, [r7, #4] 8013620: 699b ldr r3, [r3, #24] 8013622: 2b00 cmp r3, #0 8013624: d002 beq.n 801362c prio = (UBaseType_t)attr->priority; 8013626: 687b ldr r3, [r7, #4] 8013628: 699b ldr r3, [r3, #24] 801362a: 61fb str r3, [r7, #28] } if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { 801362c: 69fb ldr r3, [r7, #28] 801362e: 2b00 cmp r3, #0 8013630: d008 beq.n 8013644 8013632: 69fb ldr r3, [r7, #28] 8013634: 2b38 cmp r3, #56 @ 0x38 8013636: d805 bhi.n 8013644 8013638: 687b ldr r3, [r7, #4] 801363a: 685b ldr r3, [r3, #4] 801363c: f003 0301 and.w r3, r3, #1 8013640: 2b00 cmp r3, #0 8013642: d001 beq.n 8013648 return (NULL); 8013644: 2300 movs r3, #0 8013646: e054 b.n 80136f2 } if (attr->stack_size > 0U) { 8013648: 687b ldr r3, [r7, #4] 801364a: 695b ldr r3, [r3, #20] 801364c: 2b00 cmp r3, #0 801364e: d003 beq.n 8013658 /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ stack = attr->stack_size / sizeof(StackType_t); 8013650: 687b ldr r3, [r7, #4] 8013652: 695b ldr r3, [r3, #20] 8013654: 089b lsrs r3, r3, #2 8013656: 623b str r3, [r7, #32] } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 8013658: 687b ldr r3, [r7, #4] 801365a: 689b ldr r3, [r3, #8] 801365c: 2b00 cmp r3, #0 801365e: d00e beq.n 801367e 8013660: 687b ldr r3, [r7, #4] 8013662: 68db ldr r3, [r3, #12] 8013664: 2ba7 cmp r3, #167 @ 0xa7 8013666: d90a bls.n 801367e (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 8013668: 687b ldr r3, [r7, #4] 801366a: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 801366c: 2b00 cmp r3, #0 801366e: d006 beq.n 801367e (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 8013670: 687b ldr r3, [r7, #4] 8013672: 695b ldr r3, [r3, #20] 8013674: 2b00 cmp r3, #0 8013676: d002 beq.n 801367e mem = 1; 8013678: 2301 movs r3, #1 801367a: 61bb str r3, [r7, #24] 801367c: e010 b.n 80136a0 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { 801367e: 687b ldr r3, [r7, #4] 8013680: 689b ldr r3, [r3, #8] 8013682: 2b00 cmp r3, #0 8013684: d10c bne.n 80136a0 8013686: 687b ldr r3, [r7, #4] 8013688: 68db ldr r3, [r3, #12] 801368a: 2b00 cmp r3, #0 801368c: d108 bne.n 80136a0 801368e: 687b ldr r3, [r7, #4] 8013690: 691b ldr r3, [r3, #16] 8013692: 2b00 cmp r3, #0 8013694: d104 bne.n 80136a0 mem = 0; 8013696: 2300 movs r3, #0 8013698: 61bb str r3, [r7, #24] 801369a: e001 b.n 80136a0 } } } else { mem = 0; 801369c: 2300 movs r3, #0 801369e: 61bb str r3, [r7, #24] } if (mem == 1) { 80136a0: 69bb ldr r3, [r7, #24] 80136a2: 2b01 cmp r3, #1 80136a4: d110 bne.n 80136c8 #if (configSUPPORT_STATIC_ALLOCATION == 1) hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 80136a6: 687b ldr r3, [r7, #4] 80136a8: 691b ldr r3, [r3, #16] (StaticTask_t *)attr->cb_mem); 80136aa: 687a ldr r2, [r7, #4] 80136ac: 6892 ldr r2, [r2, #8] hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 80136ae: 9202 str r2, [sp, #8] 80136b0: 9301 str r3, [sp, #4] 80136b2: 69fb ldr r3, [r7, #28] 80136b4: 9300 str r3, [sp, #0] 80136b6: 68bb ldr r3, [r7, #8] 80136b8: 6a3a ldr r2, [r7, #32] 80136ba: 6a79 ldr r1, [r7, #36] @ 0x24 80136bc: 68f8 ldr r0, [r7, #12] 80136be: f001 fdac bl 801521a 80136c2: 4603 mov r3, r0 80136c4: 613b str r3, [r7, #16] 80136c6: e013 b.n 80136f0 #endif } else { if (mem == 0) { 80136c8: 69bb ldr r3, [r7, #24] 80136ca: 2b00 cmp r3, #0 80136cc: d110 bne.n 80136f0 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { 80136ce: 6a3b ldr r3, [r7, #32] 80136d0: b29a uxth r2, r3 80136d2: f107 0310 add.w r3, r7, #16 80136d6: 9301 str r3, [sp, #4] 80136d8: 69fb ldr r3, [r7, #28] 80136da: 9300 str r3, [sp, #0] 80136dc: 68bb ldr r3, [r7, #8] 80136de: 6a79 ldr r1, [r7, #36] @ 0x24 80136e0: 68f8 ldr r0, [r7, #12] 80136e2: f001 fdfa bl 80152da 80136e6: 4603 mov r3, r0 80136e8: 2b01 cmp r3, #1 80136ea: d001 beq.n 80136f0 hTask = NULL; 80136ec: 2300 movs r3, #0 80136ee: 613b str r3, [r7, #16] #endif } } } return ((osThreadId_t)hTask); 80136f0: 693b ldr r3, [r7, #16] } 80136f2: 4618 mov r0, r3 80136f4: 3728 adds r7, #40 @ 0x28 80136f6: 46bd mov sp, r7 80136f8: bd80 pop {r7, pc} 080136fa : /* Return flags before clearing */ return (rflags); } #endif /* (configUSE_OS2_THREAD_FLAGS == 1) */ osStatus_t osDelay (uint32_t ticks) { 80136fa: b580 push {r7, lr} 80136fc: b084 sub sp, #16 80136fe: af00 add r7, sp, #0 8013700: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013702: f3ef 8305 mrs r3, IPSR 8013706: 60bb str r3, [r7, #8] return(result); 8013708: 68bb ldr r3, [r7, #8] osStatus_t stat; if (IS_IRQ()) { 801370a: 2b00 cmp r3, #0 801370c: d003 beq.n 8013716 stat = osErrorISR; 801370e: f06f 0305 mvn.w r3, #5 8013712: 60fb str r3, [r7, #12] 8013714: e007 b.n 8013726 } else { stat = osOK; 8013716: 2300 movs r3, #0 8013718: 60fb str r3, [r7, #12] if (ticks != 0U) { 801371a: 687b ldr r3, [r7, #4] 801371c: 2b00 cmp r3, #0 801371e: d002 beq.n 8013726 vTaskDelay(ticks); 8013720: 6878 ldr r0, [r7, #4] 8013722: f001 ff37 bl 8015594 } } return (stat); 8013726: 68fb ldr r3, [r7, #12] } 8013728: 4618 mov r0, r3 801372a: 3710 adds r7, #16 801372c: 46bd mov sp, r7 801372e: bd80 pop {r7, pc} 08013730 : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_TIMER == 1) static void TimerCallback (TimerHandle_t hTimer) { 8013730: b580 push {r7, lr} 8013732: b084 sub sp, #16 8013734: af00 add r7, sp, #0 8013736: 6078 str r0, [r7, #4] TimerCallback_t *callb; callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); 8013738: 6878 ldr r0, [r7, #4] 801373a: f003 fc3d bl 8016fb8 801373e: 60f8 str r0, [r7, #12] if (callb != NULL) { 8013740: 68fb ldr r3, [r7, #12] 8013742: 2b00 cmp r3, #0 8013744: d005 beq.n 8013752 callb->func (callb->arg); 8013746: 68fb ldr r3, [r7, #12] 8013748: 681b ldr r3, [r3, #0] 801374a: 68fa ldr r2, [r7, #12] 801374c: 6852 ldr r2, [r2, #4] 801374e: 4610 mov r0, r2 8013750: 4798 blx r3 } } 8013752: bf00 nop 8013754: 3710 adds r7, #16 8013756: 46bd mov sp, r7 8013758: bd80 pop {r7, pc} ... 0801375c : osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { 801375c: b580 push {r7, lr} 801375e: b08c sub sp, #48 @ 0x30 8013760: af02 add r7, sp, #8 8013762: 60f8 str r0, [r7, #12] 8013764: 607a str r2, [r7, #4] 8013766: 603b str r3, [r7, #0] 8013768: 460b mov r3, r1 801376a: 72fb strb r3, [r7, #11] TimerHandle_t hTimer; TimerCallback_t *callb; UBaseType_t reload; int32_t mem; hTimer = NULL; 801376c: 2300 movs r3, #0 801376e: 623b str r3, [r7, #32] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013770: f3ef 8305 mrs r3, IPSR 8013774: 613b str r3, [r7, #16] return(result); 8013776: 693b ldr r3, [r7, #16] if (!IS_IRQ() && (func != NULL)) { 8013778: 2b00 cmp r3, #0 801377a: d163 bne.n 8013844 801377c: 68fb ldr r3, [r7, #12] 801377e: 2b00 cmp r3, #0 8013780: d060 beq.n 8013844 /* Allocate memory to store callback function and argument */ callb = pvPortMalloc (sizeof(TimerCallback_t)); 8013782: 2008 movs r0, #8 8013784: f003 fe8a bl 801749c 8013788: 6178 str r0, [r7, #20] if (callb != NULL) { 801378a: 697b ldr r3, [r7, #20] 801378c: 2b00 cmp r3, #0 801378e: d059 beq.n 8013844 callb->func = func; 8013790: 697b ldr r3, [r7, #20] 8013792: 68fa ldr r2, [r7, #12] 8013794: 601a str r2, [r3, #0] callb->arg = argument; 8013796: 697b ldr r3, [r7, #20] 8013798: 687a ldr r2, [r7, #4] 801379a: 605a str r2, [r3, #4] if (type == osTimerOnce) { 801379c: 7afb ldrb r3, [r7, #11] 801379e: 2b00 cmp r3, #0 80137a0: d102 bne.n 80137a8 reload = pdFALSE; 80137a2: 2300 movs r3, #0 80137a4: 61fb str r3, [r7, #28] 80137a6: e001 b.n 80137ac } else { reload = pdTRUE; 80137a8: 2301 movs r3, #1 80137aa: 61fb str r3, [r7, #28] } mem = -1; 80137ac: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80137b0: 61bb str r3, [r7, #24] name = NULL; 80137b2: 2300 movs r3, #0 80137b4: 627b str r3, [r7, #36] @ 0x24 if (attr != NULL) { 80137b6: 683b ldr r3, [r7, #0] 80137b8: 2b00 cmp r3, #0 80137ba: d01c beq.n 80137f6 if (attr->name != NULL) { 80137bc: 683b ldr r3, [r7, #0] 80137be: 681b ldr r3, [r3, #0] 80137c0: 2b00 cmp r3, #0 80137c2: d002 beq.n 80137ca name = attr->name; 80137c4: 683b ldr r3, [r7, #0] 80137c6: 681b ldr r3, [r3, #0] 80137c8: 627b str r3, [r7, #36] @ 0x24 } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) { 80137ca: 683b ldr r3, [r7, #0] 80137cc: 689b ldr r3, [r3, #8] 80137ce: 2b00 cmp r3, #0 80137d0: d006 beq.n 80137e0 80137d2: 683b ldr r3, [r7, #0] 80137d4: 68db ldr r3, [r3, #12] 80137d6: 2b2b cmp r3, #43 @ 0x2b 80137d8: d902 bls.n 80137e0 mem = 1; 80137da: 2301 movs r3, #1 80137dc: 61bb str r3, [r7, #24] 80137de: e00c b.n 80137fa } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 80137e0: 683b ldr r3, [r7, #0] 80137e2: 689b ldr r3, [r3, #8] 80137e4: 2b00 cmp r3, #0 80137e6: d108 bne.n 80137fa 80137e8: 683b ldr r3, [r7, #0] 80137ea: 68db ldr r3, [r3, #12] 80137ec: 2b00 cmp r3, #0 80137ee: d104 bne.n 80137fa mem = 0; 80137f0: 2300 movs r3, #0 80137f2: 61bb str r3, [r7, #24] 80137f4: e001 b.n 80137fa } } } else { mem = 0; 80137f6: 2300 movs r3, #0 80137f8: 61bb str r3, [r7, #24] } if (mem == 1) { 80137fa: 69bb ldr r3, [r7, #24] 80137fc: 2b01 cmp r3, #1 80137fe: d10c bne.n 801381a #if (configSUPPORT_STATIC_ALLOCATION == 1) hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem); 8013800: 683b ldr r3, [r7, #0] 8013802: 689b ldr r3, [r3, #8] 8013804: 9301 str r3, [sp, #4] 8013806: 4b12 ldr r3, [pc, #72] @ (8013850 ) 8013808: 9300 str r3, [sp, #0] 801380a: 697b ldr r3, [r7, #20] 801380c: 69fa ldr r2, [r7, #28] 801380e: 2101 movs r1, #1 8013810: 6a78 ldr r0, [r7, #36] @ 0x24 8013812: f003 f81a bl 801684a 8013816: 6238 str r0, [r7, #32] 8013818: e00b b.n 8013832 #endif } else { if (mem == 0) { 801381a: 69bb ldr r3, [r7, #24] 801381c: 2b00 cmp r3, #0 801381e: d108 bne.n 8013832 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback); 8013820: 4b0b ldr r3, [pc, #44] @ (8013850 ) 8013822: 9300 str r3, [sp, #0] 8013824: 697b ldr r3, [r7, #20] 8013826: 69fa ldr r2, [r7, #28] 8013828: 2101 movs r1, #1 801382a: 6a78 ldr r0, [r7, #36] @ 0x24 801382c: f002 ffec bl 8016808 8013830: 6238 str r0, [r7, #32] #endif } } if ((hTimer == NULL) && (callb != NULL)) { 8013832: 6a3b ldr r3, [r7, #32] 8013834: 2b00 cmp r3, #0 8013836: d105 bne.n 8013844 8013838: 697b ldr r3, [r7, #20] 801383a: 2b00 cmp r3, #0 801383c: d002 beq.n 8013844 vPortFree (callb); 801383e: 6978 ldr r0, [r7, #20] 8013840: f003 fefa bl 8017638 } } } return ((osTimerId_t)hTimer); 8013844: 6a3b ldr r3, [r7, #32] } 8013846: 4618 mov r0, r3 8013848: 3728 adds r7, #40 @ 0x28 801384a: 46bd mov sp, r7 801384c: bd80 pop {r7, pc} 801384e: bf00 nop 8013850: 08013731 .word 0x08013731 08013854 : } return (p); } osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) { 8013854: b580 push {r7, lr} 8013856: b088 sub sp, #32 8013858: af02 add r7, sp, #8 801385a: 6078 str r0, [r7, #4] 801385c: 6039 str r1, [r7, #0] TimerHandle_t hTimer = (TimerHandle_t)timer_id; 801385e: 687b ldr r3, [r7, #4] 8013860: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013862: f3ef 8305 mrs r3, IPSR 8013866: 60fb str r3, [r7, #12] return(result); 8013868: 68fb ldr r3, [r7, #12] osStatus_t stat; if (IS_IRQ()) { 801386a: 2b00 cmp r3, #0 801386c: d003 beq.n 8013876 stat = osErrorISR; 801386e: f06f 0305 mvn.w r3, #5 8013872: 617b str r3, [r7, #20] 8013874: e017 b.n 80138a6 } else if (hTimer == NULL) { 8013876: 693b ldr r3, [r7, #16] 8013878: 2b00 cmp r3, #0 801387a: d103 bne.n 8013884 stat = osErrorParameter; 801387c: f06f 0303 mvn.w r3, #3 8013880: 617b str r3, [r7, #20] 8013882: e010 b.n 80138a6 } else { if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) { 8013884: 2300 movs r3, #0 8013886: 9300 str r3, [sp, #0] 8013888: 2300 movs r3, #0 801388a: 683a ldr r2, [r7, #0] 801388c: 2104 movs r1, #4 801388e: 6938 ldr r0, [r7, #16] 8013890: f003 f858 bl 8016944 8013894: 4603 mov r3, r0 8013896: 2b01 cmp r3, #1 8013898: d102 bne.n 80138a0 stat = osOK; 801389a: 2300 movs r3, #0 801389c: 617b str r3, [r7, #20] 801389e: e002 b.n 80138a6 } else { stat = osErrorResource; 80138a0: f06f 0302 mvn.w r3, #2 80138a4: 617b str r3, [r7, #20] } } return (stat); 80138a6: 697b ldr r3, [r7, #20] } 80138a8: 4618 mov r0, r3 80138aa: 3718 adds r7, #24 80138ac: 46bd mov sp, r7 80138ae: bd80 pop {r7, pc} 080138b0 : osStatus_t osTimerStop (osTimerId_t timer_id) { 80138b0: b580 push {r7, lr} 80138b2: b088 sub sp, #32 80138b4: af02 add r7, sp, #8 80138b6: 6078 str r0, [r7, #4] TimerHandle_t hTimer = (TimerHandle_t)timer_id; 80138b8: 687b ldr r3, [r7, #4] 80138ba: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80138bc: f3ef 8305 mrs r3, IPSR 80138c0: 60fb str r3, [r7, #12] return(result); 80138c2: 68fb ldr r3, [r7, #12] osStatus_t stat; if (IS_IRQ()) { 80138c4: 2b00 cmp r3, #0 80138c6: d003 beq.n 80138d0 stat = osErrorISR; 80138c8: f06f 0305 mvn.w r3, #5 80138cc: 617b str r3, [r7, #20] 80138ce: e021 b.n 8013914 } else if (hTimer == NULL) { 80138d0: 693b ldr r3, [r7, #16] 80138d2: 2b00 cmp r3, #0 80138d4: d103 bne.n 80138de stat = osErrorParameter; 80138d6: f06f 0303 mvn.w r3, #3 80138da: 617b str r3, [r7, #20] 80138dc: e01a b.n 8013914 } else { if (xTimerIsTimerActive (hTimer) == pdFALSE) { 80138de: 6938 ldr r0, [r7, #16] 80138e0: f003 fb40 bl 8016f64 80138e4: 4603 mov r3, r0 80138e6: 2b00 cmp r3, #0 80138e8: d103 bne.n 80138f2 stat = osErrorResource; 80138ea: f06f 0302 mvn.w r3, #2 80138ee: 617b str r3, [r7, #20] 80138f0: e010 b.n 8013914 } else { if (xTimerStop (hTimer, 0) == pdPASS) { 80138f2: 2300 movs r3, #0 80138f4: 9300 str r3, [sp, #0] 80138f6: 2300 movs r3, #0 80138f8: 2200 movs r2, #0 80138fa: 2103 movs r1, #3 80138fc: 6938 ldr r0, [r7, #16] 80138fe: f003 f821 bl 8016944 8013902: 4603 mov r3, r0 8013904: 2b01 cmp r3, #1 8013906: d102 bne.n 801390e stat = osOK; 8013908: 2300 movs r3, #0 801390a: 617b str r3, [r7, #20] 801390c: e002 b.n 8013914 } else { stat = osError; 801390e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8013912: 617b str r3, [r7, #20] } } } return (stat); 8013914: 697b ldr r3, [r7, #20] } 8013916: 4618 mov r0, r3 8013918: 3718 adds r7, #24 801391a: 46bd mov sp, r7 801391c: bd80 pop {r7, pc} 0801391e : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_MUTEX == 1) osMutexId_t osMutexNew (const osMutexAttr_t *attr) { 801391e: b580 push {r7, lr} 8013920: b088 sub sp, #32 8013922: af00 add r7, sp, #0 8013924: 6078 str r0, [r7, #4] int32_t mem; #if (configQUEUE_REGISTRY_SIZE > 0) const char *name; #endif hMutex = NULL; 8013926: 2300 movs r3, #0 8013928: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801392a: f3ef 8305 mrs r3, IPSR 801392e: 60bb str r3, [r7, #8] return(result); 8013930: 68bb ldr r3, [r7, #8] if (!IS_IRQ()) { 8013932: 2b00 cmp r3, #0 8013934: d174 bne.n 8013a20 if (attr != NULL) { 8013936: 687b ldr r3, [r7, #4] 8013938: 2b00 cmp r3, #0 801393a: d003 beq.n 8013944 type = attr->attr_bits; 801393c: 687b ldr r3, [r7, #4] 801393e: 685b ldr r3, [r3, #4] 8013940: 61bb str r3, [r7, #24] 8013942: e001 b.n 8013948 } else { type = 0U; 8013944: 2300 movs r3, #0 8013946: 61bb str r3, [r7, #24] } if ((type & osMutexRecursive) == osMutexRecursive) { 8013948: 69bb ldr r3, [r7, #24] 801394a: f003 0301 and.w r3, r3, #1 801394e: 2b00 cmp r3, #0 8013950: d002 beq.n 8013958 rmtx = 1U; 8013952: 2301 movs r3, #1 8013954: 617b str r3, [r7, #20] 8013956: e001 b.n 801395c } else { rmtx = 0U; 8013958: 2300 movs r3, #0 801395a: 617b str r3, [r7, #20] } if ((type & osMutexRobust) != osMutexRobust) { 801395c: 69bb ldr r3, [r7, #24] 801395e: f003 0308 and.w r3, r3, #8 8013962: 2b00 cmp r3, #0 8013964: d15c bne.n 8013a20 mem = -1; 8013966: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801396a: 613b str r3, [r7, #16] if (attr != NULL) { 801396c: 687b ldr r3, [r7, #4] 801396e: 2b00 cmp r3, #0 8013970: d015 beq.n 801399e if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { 8013972: 687b ldr r3, [r7, #4] 8013974: 689b ldr r3, [r3, #8] 8013976: 2b00 cmp r3, #0 8013978: d006 beq.n 8013988 801397a: 687b ldr r3, [r7, #4] 801397c: 68db ldr r3, [r3, #12] 801397e: 2b4f cmp r3, #79 @ 0x4f 8013980: d902 bls.n 8013988 mem = 1; 8013982: 2301 movs r3, #1 8013984: 613b str r3, [r7, #16] 8013986: e00c b.n 80139a2 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 8013988: 687b ldr r3, [r7, #4] 801398a: 689b ldr r3, [r3, #8] 801398c: 2b00 cmp r3, #0 801398e: d108 bne.n 80139a2 8013990: 687b ldr r3, [r7, #4] 8013992: 68db ldr r3, [r3, #12] 8013994: 2b00 cmp r3, #0 8013996: d104 bne.n 80139a2 mem = 0; 8013998: 2300 movs r3, #0 801399a: 613b str r3, [r7, #16] 801399c: e001 b.n 80139a2 } } } else { mem = 0; 801399e: 2300 movs r3, #0 80139a0: 613b str r3, [r7, #16] } if (mem == 1) { 80139a2: 693b ldr r3, [r7, #16] 80139a4: 2b01 cmp r3, #1 80139a6: d112 bne.n 80139ce #if (configSUPPORT_STATIC_ALLOCATION == 1) if (rmtx != 0U) { 80139a8: 697b ldr r3, [r7, #20] 80139aa: 2b00 cmp r3, #0 80139ac: d007 beq.n 80139be #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem); 80139ae: 687b ldr r3, [r7, #4] 80139b0: 689b ldr r3, [r3, #8] 80139b2: 4619 mov r1, r3 80139b4: 2004 movs r0, #4 80139b6: f000 fc50 bl 801425a 80139ba: 61f8 str r0, [r7, #28] 80139bc: e016 b.n 80139ec #endif } else { hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem); 80139be: 687b ldr r3, [r7, #4] 80139c0: 689b ldr r3, [r3, #8] 80139c2: 4619 mov r1, r3 80139c4: 2001 movs r0, #1 80139c6: f000 fc48 bl 801425a 80139ca: 61f8 str r0, [r7, #28] 80139cc: e00e b.n 80139ec } #endif } else { if (mem == 0) { 80139ce: 693b ldr r3, [r7, #16] 80139d0: 2b00 cmp r3, #0 80139d2: d10b bne.n 80139ec #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (rmtx != 0U) { 80139d4: 697b ldr r3, [r7, #20] 80139d6: 2b00 cmp r3, #0 80139d8: d004 beq.n 80139e4 #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutex (); 80139da: 2004 movs r0, #4 80139dc: f000 fc25 bl 801422a 80139e0: 61f8 str r0, [r7, #28] 80139e2: e003 b.n 80139ec #endif } else { hMutex = xSemaphoreCreateMutex (); 80139e4: 2001 movs r0, #1 80139e6: f000 fc20 bl 801422a 80139ea: 61f8 str r0, [r7, #28] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hMutex != NULL) { 80139ec: 69fb ldr r3, [r7, #28] 80139ee: 2b00 cmp r3, #0 80139f0: d00c beq.n 8013a0c if (attr != NULL) { 80139f2: 687b ldr r3, [r7, #4] 80139f4: 2b00 cmp r3, #0 80139f6: d003 beq.n 8013a00 name = attr->name; 80139f8: 687b ldr r3, [r7, #4] 80139fa: 681b ldr r3, [r3, #0] 80139fc: 60fb str r3, [r7, #12] 80139fe: e001 b.n 8013a04 } else { name = NULL; 8013a00: 2300 movs r3, #0 8013a02: 60fb str r3, [r7, #12] } vQueueAddToRegistry (hMutex, name); 8013a04: 68f9 ldr r1, [r7, #12] 8013a06: 69f8 ldr r0, [r7, #28] 8013a08: f001 f9ea bl 8014de0 } #endif if ((hMutex != NULL) && (rmtx != 0U)) { 8013a0c: 69fb ldr r3, [r7, #28] 8013a0e: 2b00 cmp r3, #0 8013a10: d006 beq.n 8013a20 8013a12: 697b ldr r3, [r7, #20] 8013a14: 2b00 cmp r3, #0 8013a16: d003 beq.n 8013a20 hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U); 8013a18: 69fb ldr r3, [r7, #28] 8013a1a: f043 0301 orr.w r3, r3, #1 8013a1e: 61fb str r3, [r7, #28] } } } return ((osMutexId_t)hMutex); 8013a20: 69fb ldr r3, [r7, #28] } 8013a22: 4618 mov r0, r3 8013a24: 3720 adds r7, #32 8013a26: 46bd mov sp, r7 8013a28: bd80 pop {r7, pc} 08013a2a : osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { 8013a2a: b580 push {r7, lr} 8013a2c: b086 sub sp, #24 8013a2e: af00 add r7, sp, #0 8013a30: 6078 str r0, [r7, #4] 8013a32: 6039 str r1, [r7, #0] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 8013a34: 687b ldr r3, [r7, #4] 8013a36: f023 0301 bic.w r3, r3, #1 8013a3a: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 8013a3c: 687b ldr r3, [r7, #4] 8013a3e: f003 0301 and.w r3, r3, #1 8013a42: 60fb str r3, [r7, #12] stat = osOK; 8013a44: 2300 movs r3, #0 8013a46: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013a48: f3ef 8305 mrs r3, IPSR 8013a4c: 60bb str r3, [r7, #8] return(result); 8013a4e: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 8013a50: 2b00 cmp r3, #0 8013a52: d003 beq.n 8013a5c stat = osErrorISR; 8013a54: f06f 0305 mvn.w r3, #5 8013a58: 617b str r3, [r7, #20] 8013a5a: e02c b.n 8013ab6 } else if (hMutex == NULL) { 8013a5c: 693b ldr r3, [r7, #16] 8013a5e: 2b00 cmp r3, #0 8013a60: d103 bne.n 8013a6a stat = osErrorParameter; 8013a62: f06f 0303 mvn.w r3, #3 8013a66: 617b str r3, [r7, #20] 8013a68: e025 b.n 8013ab6 } else { if (rmtx != 0U) { 8013a6a: 68fb ldr r3, [r7, #12] 8013a6c: 2b00 cmp r3, #0 8013a6e: d011 beq.n 8013a94 #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) { 8013a70: 6839 ldr r1, [r7, #0] 8013a72: 6938 ldr r0, [r7, #16] 8013a74: f000 fc41 bl 80142fa 8013a78: 4603 mov r3, r0 8013a7a: 2b01 cmp r3, #1 8013a7c: d01b beq.n 8013ab6 if (timeout != 0U) { 8013a7e: 683b ldr r3, [r7, #0] 8013a80: 2b00 cmp r3, #0 8013a82: d003 beq.n 8013a8c stat = osErrorTimeout; 8013a84: f06f 0301 mvn.w r3, #1 8013a88: 617b str r3, [r7, #20] 8013a8a: e014 b.n 8013ab6 } else { stat = osErrorResource; 8013a8c: f06f 0302 mvn.w r3, #2 8013a90: 617b str r3, [r7, #20] 8013a92: e010 b.n 8013ab6 } } #endif } else { if (xSemaphoreTake (hMutex, timeout) != pdPASS) { 8013a94: 6839 ldr r1, [r7, #0] 8013a96: 6938 ldr r0, [r7, #16] 8013a98: f000 fee8 bl 801486c 8013a9c: 4603 mov r3, r0 8013a9e: 2b01 cmp r3, #1 8013aa0: d009 beq.n 8013ab6 if (timeout != 0U) { 8013aa2: 683b ldr r3, [r7, #0] 8013aa4: 2b00 cmp r3, #0 8013aa6: d003 beq.n 8013ab0 stat = osErrorTimeout; 8013aa8: f06f 0301 mvn.w r3, #1 8013aac: 617b str r3, [r7, #20] 8013aae: e002 b.n 8013ab6 } else { stat = osErrorResource; 8013ab0: f06f 0302 mvn.w r3, #2 8013ab4: 617b str r3, [r7, #20] } } } } return (stat); 8013ab6: 697b ldr r3, [r7, #20] } 8013ab8: 4618 mov r0, r3 8013aba: 3718 adds r7, #24 8013abc: 46bd mov sp, r7 8013abe: bd80 pop {r7, pc} 08013ac0 : osStatus_t osMutexRelease (osMutexId_t mutex_id) { 8013ac0: b580 push {r7, lr} 8013ac2: b086 sub sp, #24 8013ac4: af00 add r7, sp, #0 8013ac6: 6078 str r0, [r7, #4] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 8013ac8: 687b ldr r3, [r7, #4] 8013aca: f023 0301 bic.w r3, r3, #1 8013ace: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 8013ad0: 687b ldr r3, [r7, #4] 8013ad2: f003 0301 and.w r3, r3, #1 8013ad6: 60fb str r3, [r7, #12] stat = osOK; 8013ad8: 2300 movs r3, #0 8013ada: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013adc: f3ef 8305 mrs r3, IPSR 8013ae0: 60bb str r3, [r7, #8] return(result); 8013ae2: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 8013ae4: 2b00 cmp r3, #0 8013ae6: d003 beq.n 8013af0 stat = osErrorISR; 8013ae8: f06f 0305 mvn.w r3, #5 8013aec: 617b str r3, [r7, #20] 8013aee: e01f b.n 8013b30 } else if (hMutex == NULL) { 8013af0: 693b ldr r3, [r7, #16] 8013af2: 2b00 cmp r3, #0 8013af4: d103 bne.n 8013afe stat = osErrorParameter; 8013af6: f06f 0303 mvn.w r3, #3 8013afa: 617b str r3, [r7, #20] 8013afc: e018 b.n 8013b30 } else { if (rmtx != 0U) { 8013afe: 68fb ldr r3, [r7, #12] 8013b00: 2b00 cmp r3, #0 8013b02: d009 beq.n 8013b18 #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreGiveRecursive (hMutex) != pdPASS) { 8013b04: 6938 ldr r0, [r7, #16] 8013b06: f000 fbc3 bl 8014290 8013b0a: 4603 mov r3, r0 8013b0c: 2b01 cmp r3, #1 8013b0e: d00f beq.n 8013b30 stat = osErrorResource; 8013b10: f06f 0302 mvn.w r3, #2 8013b14: 617b str r3, [r7, #20] 8013b16: e00b b.n 8013b30 } #endif } else { if (xSemaphoreGive (hMutex) != pdPASS) { 8013b18: 2300 movs r3, #0 8013b1a: 2200 movs r2, #0 8013b1c: 2100 movs r1, #0 8013b1e: 6938 ldr r0, [r7, #16] 8013b20: f000 fc22 bl 8014368 8013b24: 4603 mov r3, r0 8013b26: 2b01 cmp r3, #1 8013b28: d002 beq.n 8013b30 stat = osErrorResource; 8013b2a: f06f 0302 mvn.w r3, #2 8013b2e: 617b str r3, [r7, #20] } } } return (stat); 8013b30: 697b ldr r3, [r7, #20] } 8013b32: 4618 mov r0, r3 8013b34: 3718 adds r7, #24 8013b36: 46bd mov sp, r7 8013b38: bd80 pop {r7, pc} 08013b3a : return (stat); } /*---------------------------------------------------------------------------*/ osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { 8013b3a: b580 push {r7, lr} 8013b3c: b08a sub sp, #40 @ 0x28 8013b3e: af02 add r7, sp, #8 8013b40: 60f8 str r0, [r7, #12] 8013b42: 60b9 str r1, [r7, #8] 8013b44: 607a str r2, [r7, #4] int32_t mem; #if (configQUEUE_REGISTRY_SIZE > 0) const char *name; #endif hQueue = NULL; 8013b46: 2300 movs r3, #0 8013b48: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013b4a: f3ef 8305 mrs r3, IPSR 8013b4e: 613b str r3, [r7, #16] return(result); 8013b50: 693b ldr r3, [r7, #16] if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) { 8013b52: 2b00 cmp r3, #0 8013b54: d15f bne.n 8013c16 8013b56: 68fb ldr r3, [r7, #12] 8013b58: 2b00 cmp r3, #0 8013b5a: d05c beq.n 8013c16 8013b5c: 68bb ldr r3, [r7, #8] 8013b5e: 2b00 cmp r3, #0 8013b60: d059 beq.n 8013c16 mem = -1; 8013b62: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8013b66: 61bb str r3, [r7, #24] if (attr != NULL) { 8013b68: 687b ldr r3, [r7, #4] 8013b6a: 2b00 cmp r3, #0 8013b6c: d029 beq.n 8013bc2 if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 8013b6e: 687b ldr r3, [r7, #4] 8013b70: 689b ldr r3, [r3, #8] 8013b72: 2b00 cmp r3, #0 8013b74: d012 beq.n 8013b9c 8013b76: 687b ldr r3, [r7, #4] 8013b78: 68db ldr r3, [r3, #12] 8013b7a: 2b4f cmp r3, #79 @ 0x4f 8013b7c: d90e bls.n 8013b9c (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 8013b7e: 687b ldr r3, [r7, #4] 8013b80: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 8013b82: 2b00 cmp r3, #0 8013b84: d00a beq.n 8013b9c (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 8013b86: 687b ldr r3, [r7, #4] 8013b88: 695a ldr r2, [r3, #20] 8013b8a: 68fb ldr r3, [r7, #12] 8013b8c: 68b9 ldr r1, [r7, #8] 8013b8e: fb01 f303 mul.w r3, r1, r3 8013b92: 429a cmp r2, r3 8013b94: d302 bcc.n 8013b9c mem = 1; 8013b96: 2301 movs r3, #1 8013b98: 61bb str r3, [r7, #24] 8013b9a: e014 b.n 8013bc6 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 8013b9c: 687b ldr r3, [r7, #4] 8013b9e: 689b ldr r3, [r3, #8] 8013ba0: 2b00 cmp r3, #0 8013ba2: d110 bne.n 8013bc6 8013ba4: 687b ldr r3, [r7, #4] 8013ba6: 68db ldr r3, [r3, #12] 8013ba8: 2b00 cmp r3, #0 8013baa: d10c bne.n 8013bc6 (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 8013bac: 687b ldr r3, [r7, #4] 8013bae: 691b ldr r3, [r3, #16] if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 8013bb0: 2b00 cmp r3, #0 8013bb2: d108 bne.n 8013bc6 (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 8013bb4: 687b ldr r3, [r7, #4] 8013bb6: 695b ldr r3, [r3, #20] 8013bb8: 2b00 cmp r3, #0 8013bba: d104 bne.n 8013bc6 mem = 0; 8013bbc: 2300 movs r3, #0 8013bbe: 61bb str r3, [r7, #24] 8013bc0: e001 b.n 8013bc6 } } } else { mem = 0; 8013bc2: 2300 movs r3, #0 8013bc4: 61bb str r3, [r7, #24] } if (mem == 1) { 8013bc6: 69bb ldr r3, [r7, #24] 8013bc8: 2b01 cmp r3, #1 8013bca: d10b bne.n 8013be4 #if (configSUPPORT_STATIC_ALLOCATION == 1) hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem); 8013bcc: 687b ldr r3, [r7, #4] 8013bce: 691a ldr r2, [r3, #16] 8013bd0: 687b ldr r3, [r7, #4] 8013bd2: 689b ldr r3, [r3, #8] 8013bd4: 2100 movs r1, #0 8013bd6: 9100 str r1, [sp, #0] 8013bd8: 68b9 ldr r1, [r7, #8] 8013bda: 68f8 ldr r0, [r7, #12] 8013bdc: f000 fa30 bl 8014040 8013be0: 61f8 str r0, [r7, #28] 8013be2: e008 b.n 8013bf6 #endif } else { if (mem == 0) { 8013be4: 69bb ldr r3, [r7, #24] 8013be6: 2b00 cmp r3, #0 8013be8: d105 bne.n 8013bf6 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hQueue = xQueueCreate (msg_count, msg_size); 8013bea: 2200 movs r2, #0 8013bec: 68b9 ldr r1, [r7, #8] 8013bee: 68f8 ldr r0, [r7, #12] 8013bf0: f000 faa3 bl 801413a 8013bf4: 61f8 str r0, [r7, #28] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hQueue != NULL) { 8013bf6: 69fb ldr r3, [r7, #28] 8013bf8: 2b00 cmp r3, #0 8013bfa: d00c beq.n 8013c16 if (attr != NULL) { 8013bfc: 687b ldr r3, [r7, #4] 8013bfe: 2b00 cmp r3, #0 8013c00: d003 beq.n 8013c0a name = attr->name; 8013c02: 687b ldr r3, [r7, #4] 8013c04: 681b ldr r3, [r3, #0] 8013c06: 617b str r3, [r7, #20] 8013c08: e001 b.n 8013c0e } else { name = NULL; 8013c0a: 2300 movs r3, #0 8013c0c: 617b str r3, [r7, #20] } vQueueAddToRegistry (hQueue, name); 8013c0e: 6979 ldr r1, [r7, #20] 8013c10: 69f8 ldr r0, [r7, #28] 8013c12: f001 f8e5 bl 8014de0 } #endif } return ((osMessageQueueId_t)hQueue); 8013c16: 69fb ldr r3, [r7, #28] } 8013c18: 4618 mov r0, r3 8013c1a: 3720 adds r7, #32 8013c1c: 46bd mov sp, r7 8013c1e: bd80 pop {r7, pc} 08013c20 : osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { 8013c20: b580 push {r7, lr} 8013c22: b088 sub sp, #32 8013c24: af00 add r7, sp, #0 8013c26: 60f8 str r0, [r7, #12] 8013c28: 60b9 str r1, [r7, #8] 8013c2a: 603b str r3, [r7, #0] 8013c2c: 4613 mov r3, r2 8013c2e: 71fb strb r3, [r7, #7] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 8013c30: 68fb ldr r3, [r7, #12] 8013c32: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 8013c34: 2300 movs r3, #0 8013c36: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013c38: f3ef 8305 mrs r3, IPSR 8013c3c: 617b str r3, [r7, #20] return(result); 8013c3e: 697b ldr r3, [r7, #20] if (IS_IRQ()) { 8013c40: 2b00 cmp r3, #0 8013c42: d028 beq.n 8013c96 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 8013c44: 69bb ldr r3, [r7, #24] 8013c46: 2b00 cmp r3, #0 8013c48: d005 beq.n 8013c56 8013c4a: 68bb ldr r3, [r7, #8] 8013c4c: 2b00 cmp r3, #0 8013c4e: d002 beq.n 8013c56 8013c50: 683b ldr r3, [r7, #0] 8013c52: 2b00 cmp r3, #0 8013c54: d003 beq.n 8013c5e stat = osErrorParameter; 8013c56: f06f 0303 mvn.w r3, #3 8013c5a: 61fb str r3, [r7, #28] 8013c5c: e038 b.n 8013cd0 } else { yield = pdFALSE; 8013c5e: 2300 movs r3, #0 8013c60: 613b str r3, [r7, #16] if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { 8013c62: f107 0210 add.w r2, r7, #16 8013c66: 2300 movs r3, #0 8013c68: 68b9 ldr r1, [r7, #8] 8013c6a: 69b8 ldr r0, [r7, #24] 8013c6c: f000 fc7e bl 801456c 8013c70: 4603 mov r3, r0 8013c72: 2b01 cmp r3, #1 8013c74: d003 beq.n 8013c7e stat = osErrorResource; 8013c76: f06f 0302 mvn.w r3, #2 8013c7a: 61fb str r3, [r7, #28] 8013c7c: e028 b.n 8013cd0 } else { portYIELD_FROM_ISR (yield); 8013c7e: 693b ldr r3, [r7, #16] 8013c80: 2b00 cmp r3, #0 8013c82: d025 beq.n 8013cd0 8013c84: 4b15 ldr r3, [pc, #84] @ (8013cdc ) 8013c86: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8013c8a: 601a str r2, [r3, #0] 8013c8c: f3bf 8f4f dsb sy 8013c90: f3bf 8f6f isb sy 8013c94: e01c b.n 8013cd0 } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 8013c96: 69bb ldr r3, [r7, #24] 8013c98: 2b00 cmp r3, #0 8013c9a: d002 beq.n 8013ca2 8013c9c: 68bb ldr r3, [r7, #8] 8013c9e: 2b00 cmp r3, #0 8013ca0: d103 bne.n 8013caa stat = osErrorParameter; 8013ca2: f06f 0303 mvn.w r3, #3 8013ca6: 61fb str r3, [r7, #28] 8013ca8: e012 b.n 8013cd0 } else { if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 8013caa: 2300 movs r3, #0 8013cac: 683a ldr r2, [r7, #0] 8013cae: 68b9 ldr r1, [r7, #8] 8013cb0: 69b8 ldr r0, [r7, #24] 8013cb2: f000 fb59 bl 8014368 8013cb6: 4603 mov r3, r0 8013cb8: 2b01 cmp r3, #1 8013cba: d009 beq.n 8013cd0 if (timeout != 0U) { 8013cbc: 683b ldr r3, [r7, #0] 8013cbe: 2b00 cmp r3, #0 8013cc0: d003 beq.n 8013cca stat = osErrorTimeout; 8013cc2: f06f 0301 mvn.w r3, #1 8013cc6: 61fb str r3, [r7, #28] 8013cc8: e002 b.n 8013cd0 } else { stat = osErrorResource; 8013cca: f06f 0302 mvn.w r3, #2 8013cce: 61fb str r3, [r7, #28] } } } } return (stat); 8013cd0: 69fb ldr r3, [r7, #28] } 8013cd2: 4618 mov r0, r3 8013cd4: 3720 adds r7, #32 8013cd6: 46bd mov sp, r7 8013cd8: bd80 pop {r7, pc} 8013cda: bf00 nop 8013cdc: e000ed04 .word 0xe000ed04 08013ce0 : osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { 8013ce0: b580 push {r7, lr} 8013ce2: b088 sub sp, #32 8013ce4: af00 add r7, sp, #0 8013ce6: 60f8 str r0, [r7, #12] 8013ce8: 60b9 str r1, [r7, #8] 8013cea: 607a str r2, [r7, #4] 8013cec: 603b str r3, [r7, #0] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 8013cee: 68fb ldr r3, [r7, #12] 8013cf0: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 8013cf2: 2300 movs r3, #0 8013cf4: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013cf6: f3ef 8305 mrs r3, IPSR 8013cfa: 617b str r3, [r7, #20] return(result); 8013cfc: 697b ldr r3, [r7, #20] if (IS_IRQ()) { 8013cfe: 2b00 cmp r3, #0 8013d00: d028 beq.n 8013d54 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 8013d02: 69bb ldr r3, [r7, #24] 8013d04: 2b00 cmp r3, #0 8013d06: d005 beq.n 8013d14 8013d08: 68bb ldr r3, [r7, #8] 8013d0a: 2b00 cmp r3, #0 8013d0c: d002 beq.n 8013d14 8013d0e: 683b ldr r3, [r7, #0] 8013d10: 2b00 cmp r3, #0 8013d12: d003 beq.n 8013d1c stat = osErrorParameter; 8013d14: f06f 0303 mvn.w r3, #3 8013d18: 61fb str r3, [r7, #28] 8013d1a: e037 b.n 8013d8c } else { yield = pdFALSE; 8013d1c: 2300 movs r3, #0 8013d1e: 613b str r3, [r7, #16] if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) { 8013d20: f107 0310 add.w r3, r7, #16 8013d24: 461a mov r2, r3 8013d26: 68b9 ldr r1, [r7, #8] 8013d28: 69b8 ldr r0, [r7, #24] 8013d2a: f000 feaf bl 8014a8c 8013d2e: 4603 mov r3, r0 8013d30: 2b01 cmp r3, #1 8013d32: d003 beq.n 8013d3c stat = osErrorResource; 8013d34: f06f 0302 mvn.w r3, #2 8013d38: 61fb str r3, [r7, #28] 8013d3a: e027 b.n 8013d8c } else { portYIELD_FROM_ISR (yield); 8013d3c: 693b ldr r3, [r7, #16] 8013d3e: 2b00 cmp r3, #0 8013d40: d024 beq.n 8013d8c 8013d42: 4b15 ldr r3, [pc, #84] @ (8013d98 ) 8013d44: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8013d48: 601a str r2, [r3, #0] 8013d4a: f3bf 8f4f dsb sy 8013d4e: f3bf 8f6f isb sy 8013d52: e01b b.n 8013d8c } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 8013d54: 69bb ldr r3, [r7, #24] 8013d56: 2b00 cmp r3, #0 8013d58: d002 beq.n 8013d60 8013d5a: 68bb ldr r3, [r7, #8] 8013d5c: 2b00 cmp r3, #0 8013d5e: d103 bne.n 8013d68 stat = osErrorParameter; 8013d60: f06f 0303 mvn.w r3, #3 8013d64: 61fb str r3, [r7, #28] 8013d66: e011 b.n 8013d8c } else { if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 8013d68: 683a ldr r2, [r7, #0] 8013d6a: 68b9 ldr r1, [r7, #8] 8013d6c: 69b8 ldr r0, [r7, #24] 8013d6e: f000 fc9b bl 80146a8 8013d72: 4603 mov r3, r0 8013d74: 2b01 cmp r3, #1 8013d76: d009 beq.n 8013d8c if (timeout != 0U) { 8013d78: 683b ldr r3, [r7, #0] 8013d7a: 2b00 cmp r3, #0 8013d7c: d003 beq.n 8013d86 stat = osErrorTimeout; 8013d7e: f06f 0301 mvn.w r3, #1 8013d82: 61fb str r3, [r7, #28] 8013d84: e002 b.n 8013d8c } else { stat = osErrorResource; 8013d86: f06f 0302 mvn.w r3, #2 8013d8a: 61fb str r3, [r7, #28] } } } } return (stat); 8013d8c: 69fb ldr r3, [r7, #28] } 8013d8e: 4618 mov r0, r3 8013d90: 3720 adds r7, #32 8013d92: 46bd mov sp, r7 8013d94: bd80 pop {r7, pc} 8013d96: bf00 nop 8013d98: e000ed04 .word 0xe000ed04 08013d9c : /* vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { 8013d9c: b480 push {r7} 8013d9e: b085 sub sp, #20 8013da0: af00 add r7, sp, #0 8013da2: 60f8 str r0, [r7, #12] 8013da4: 60b9 str r1, [r7, #8] 8013da6: 607a str r2, [r7, #4] /* Idle task control block and stack */ static StaticTask_t Idle_TCB; static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; *ppxIdleTaskTCBBuffer = &Idle_TCB; 8013da8: 68fb ldr r3, [r7, #12] 8013daa: 4a07 ldr r2, [pc, #28] @ (8013dc8 ) 8013dac: 601a str r2, [r3, #0] *ppxIdleTaskStackBuffer = &Idle_Stack[0]; 8013dae: 68bb ldr r3, [r7, #8] 8013db0: 4a06 ldr r2, [pc, #24] @ (8013dcc ) 8013db2: 601a str r2, [r3, #0] *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; 8013db4: 687b ldr r3, [r7, #4] 8013db6: f44f 7200 mov.w r2, #512 @ 0x200 8013dba: 601a str r2, [r3, #0] } 8013dbc: bf00 nop 8013dbe: 3714 adds r7, #20 8013dc0: 46bd mov sp, r7 8013dc2: f85d 7b04 ldr.w r7, [sp], #4 8013dc6: 4770 bx lr 8013dc8: 24001084 .word 0x24001084 8013dcc: 2400112c .word 0x2400112c 08013dd0 : /* vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { 8013dd0: b480 push {r7} 8013dd2: b085 sub sp, #20 8013dd4: af00 add r7, sp, #0 8013dd6: 60f8 str r0, [r7, #12] 8013dd8: 60b9 str r1, [r7, #8] 8013dda: 607a str r2, [r7, #4] /* Timer task control block and stack */ static StaticTask_t Timer_TCB; static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; *ppxTimerTaskTCBBuffer = &Timer_TCB; 8013ddc: 68fb ldr r3, [r7, #12] 8013dde: 4a07 ldr r2, [pc, #28] @ (8013dfc ) 8013de0: 601a str r2, [r3, #0] *ppxTimerTaskStackBuffer = &Timer_Stack[0]; 8013de2: 68bb ldr r3, [r7, #8] 8013de4: 4a06 ldr r2, [pc, #24] @ (8013e00 ) 8013de6: 601a str r2, [r3, #0] *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; 8013de8: 687b ldr r3, [r7, #4] 8013dea: f44f 6280 mov.w r2, #1024 @ 0x400 8013dee: 601a str r2, [r3, #0] } 8013df0: bf00 nop 8013df2: 3714 adds r7, #20 8013df4: 46bd mov sp, r7 8013df6: f85d 7b04 ldr.w r7, [sp], #4 8013dfa: 4770 bx lr 8013dfc: 2400192c .word 0x2400192c 8013e00: 240019d4 .word 0x240019d4 08013e04 : /*----------------------------------------------------------- * PUBLIC LIST API documented in list.h *----------------------------------------------------------*/ void vListInitialise( List_t * const pxList ) { 8013e04: b480 push {r7} 8013e06: b083 sub sp, #12 8013e08: af00 add r7, sp, #0 8013e0a: 6078 str r0, [r7, #4] /* The list structure contains a list item which is used to mark the end of the list. To initialise the list the list end is inserted as the only list entry. */ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8013e0c: 687b ldr r3, [r7, #4] 8013e0e: f103 0208 add.w r2, r3, #8 8013e12: 687b ldr r3, [r7, #4] 8013e14: 605a str r2, [r3, #4] /* The list end value is the highest possible value in the list to ensure it remains at the end of the list. */ pxList->xListEnd.xItemValue = portMAX_DELAY; 8013e16: 687b ldr r3, [r7, #4] 8013e18: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8013e1c: 609a str r2, [r3, #8] /* The list end next and previous pointers point to itself so we know when the list is empty. */ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8013e1e: 687b ldr r3, [r7, #4] 8013e20: f103 0208 add.w r2, r3, #8 8013e24: 687b ldr r3, [r7, #4] 8013e26: 60da str r2, [r3, #12] pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8013e28: 687b ldr r3, [r7, #4] 8013e2a: f103 0208 add.w r2, r3, #8 8013e2e: 687b ldr r3, [r7, #4] 8013e30: 611a str r2, [r3, #16] pxList->uxNumberOfItems = ( UBaseType_t ) 0U; 8013e32: 687b ldr r3, [r7, #4] 8013e34: 2200 movs r2, #0 8013e36: 601a str r2, [r3, #0] /* Write known values into the list if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); } 8013e38: bf00 nop 8013e3a: 370c adds r7, #12 8013e3c: 46bd mov sp, r7 8013e3e: f85d 7b04 ldr.w r7, [sp], #4 8013e42: 4770 bx lr 08013e44 : /*-----------------------------------------------------------*/ void vListInitialiseItem( ListItem_t * const pxItem ) { 8013e44: b480 push {r7} 8013e46: b083 sub sp, #12 8013e48: af00 add r7, sp, #0 8013e4a: 6078 str r0, [r7, #4] /* Make sure the list item is not recorded as being on a list. */ pxItem->pxContainer = NULL; 8013e4c: 687b ldr r3, [r7, #4] 8013e4e: 2200 movs r2, #0 8013e50: 611a str r2, [r3, #16] /* Write known values into the list item if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } 8013e52: bf00 nop 8013e54: 370c adds r7, #12 8013e56: 46bd mov sp, r7 8013e58: f85d 7b04 ldr.w r7, [sp], #4 8013e5c: 4770 bx lr 08013e5e : /*-----------------------------------------------------------*/ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8013e5e: b480 push {r7} 8013e60: b085 sub sp, #20 8013e62: af00 add r7, sp, #0 8013e64: 6078 str r0, [r7, #4] 8013e66: 6039 str r1, [r7, #0] ListItem_t * const pxIndex = pxList->pxIndex; 8013e68: 687b ldr r3, [r7, #4] 8013e6a: 685b ldr r3, [r3, #4] 8013e6c: 60fb str r3, [r7, #12] listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); /* Insert a new list item into pxList, but rather than sort the list, makes the new list item the last item to be removed by a call to listGET_OWNER_OF_NEXT_ENTRY(). */ pxNewListItem->pxNext = pxIndex; 8013e6e: 683b ldr r3, [r7, #0] 8013e70: 68fa ldr r2, [r7, #12] 8013e72: 605a str r2, [r3, #4] pxNewListItem->pxPrevious = pxIndex->pxPrevious; 8013e74: 68fb ldr r3, [r7, #12] 8013e76: 689a ldr r2, [r3, #8] 8013e78: 683b ldr r3, [r7, #0] 8013e7a: 609a str r2, [r3, #8] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); pxIndex->pxPrevious->pxNext = pxNewListItem; 8013e7c: 68fb ldr r3, [r7, #12] 8013e7e: 689b ldr r3, [r3, #8] 8013e80: 683a ldr r2, [r7, #0] 8013e82: 605a str r2, [r3, #4] pxIndex->pxPrevious = pxNewListItem; 8013e84: 68fb ldr r3, [r7, #12] 8013e86: 683a ldr r2, [r7, #0] 8013e88: 609a str r2, [r3, #8] /* Remember which list the item is in. */ pxNewListItem->pxContainer = pxList; 8013e8a: 683b ldr r3, [r7, #0] 8013e8c: 687a ldr r2, [r7, #4] 8013e8e: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8013e90: 687b ldr r3, [r7, #4] 8013e92: 681b ldr r3, [r3, #0] 8013e94: 1c5a adds r2, r3, #1 8013e96: 687b ldr r3, [r7, #4] 8013e98: 601a str r2, [r3, #0] } 8013e9a: bf00 nop 8013e9c: 3714 adds r7, #20 8013e9e: 46bd mov sp, r7 8013ea0: f85d 7b04 ldr.w r7, [sp], #4 8013ea4: 4770 bx lr 08013ea6 : /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8013ea6: b480 push {r7} 8013ea8: b085 sub sp, #20 8013eaa: af00 add r7, sp, #0 8013eac: 6078 str r0, [r7, #4] 8013eae: 6039 str r1, [r7, #0] ListItem_t *pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; 8013eb0: 683b ldr r3, [r7, #0] 8013eb2: 681b ldr r3, [r3, #0] 8013eb4: 60bb str r3, [r7, #8] new list item should be placed after it. This ensures that TCBs which are stored in ready lists (all of which have the same xItemValue value) get a share of the CPU. However, if the xItemValue is the same as the back marker the iteration loop below will not end. Therefore the value is checked first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) 8013eb6: 68bb ldr r3, [r7, #8] 8013eb8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8013ebc: d103 bne.n 8013ec6 { pxIterator = pxList->xListEnd.pxPrevious; 8013ebe: 687b ldr r3, [r7, #4] 8013ec0: 691b ldr r3, [r3, #16] 8013ec2: 60fb str r3, [r7, #12] 8013ec4: e00c b.n 8013ee0 4) Using a queue or semaphore before it has been initialised or before the scheduler has been started (are interrupts firing before vTaskStartScheduler() has been called?). **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ 8013ec6: 687b ldr r3, [r7, #4] 8013ec8: 3308 adds r3, #8 8013eca: 60fb str r3, [r7, #12] 8013ecc: e002 b.n 8013ed4 8013ece: 68fb ldr r3, [r7, #12] 8013ed0: 685b ldr r3, [r3, #4] 8013ed2: 60fb str r3, [r7, #12] 8013ed4: 68fb ldr r3, [r7, #12] 8013ed6: 685b ldr r3, [r3, #4] 8013ed8: 681b ldr r3, [r3, #0] 8013eda: 68ba ldr r2, [r7, #8] 8013edc: 429a cmp r2, r3 8013ede: d2f6 bcs.n 8013ece /* There is nothing to do here, just iterating to the wanted insertion position. */ } } pxNewListItem->pxNext = pxIterator->pxNext; 8013ee0: 68fb ldr r3, [r7, #12] 8013ee2: 685a ldr r2, [r3, #4] 8013ee4: 683b ldr r3, [r7, #0] 8013ee6: 605a str r2, [r3, #4] pxNewListItem->pxNext->pxPrevious = pxNewListItem; 8013ee8: 683b ldr r3, [r7, #0] 8013eea: 685b ldr r3, [r3, #4] 8013eec: 683a ldr r2, [r7, #0] 8013eee: 609a str r2, [r3, #8] pxNewListItem->pxPrevious = pxIterator; 8013ef0: 683b ldr r3, [r7, #0] 8013ef2: 68fa ldr r2, [r7, #12] 8013ef4: 609a str r2, [r3, #8] pxIterator->pxNext = pxNewListItem; 8013ef6: 68fb ldr r3, [r7, #12] 8013ef8: 683a ldr r2, [r7, #0] 8013efa: 605a str r2, [r3, #4] /* Remember which list the item is in. This allows fast removal of the item later. */ pxNewListItem->pxContainer = pxList; 8013efc: 683b ldr r3, [r7, #0] 8013efe: 687a ldr r2, [r7, #4] 8013f00: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8013f02: 687b ldr r3, [r7, #4] 8013f04: 681b ldr r3, [r3, #0] 8013f06: 1c5a adds r2, r3, #1 8013f08: 687b ldr r3, [r7, #4] 8013f0a: 601a str r2, [r3, #0] } 8013f0c: bf00 nop 8013f0e: 3714 adds r7, #20 8013f10: 46bd mov sp, r7 8013f12: f85d 7b04 ldr.w r7, [sp], #4 8013f16: 4770 bx lr 08013f18 : /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { 8013f18: b480 push {r7} 8013f1a: b085 sub sp, #20 8013f1c: af00 add r7, sp, #0 8013f1e: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list item. */ List_t * const pxList = pxItemToRemove->pxContainer; 8013f20: 687b ldr r3, [r7, #4] 8013f22: 691b ldr r3, [r3, #16] 8013f24: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 8013f26: 687b ldr r3, [r7, #4] 8013f28: 685b ldr r3, [r3, #4] 8013f2a: 687a ldr r2, [r7, #4] 8013f2c: 6892 ldr r2, [r2, #8] 8013f2e: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; 8013f30: 687b ldr r3, [r7, #4] 8013f32: 689b ldr r3, [r3, #8] 8013f34: 687a ldr r2, [r7, #4] 8013f36: 6852 ldr r2, [r2, #4] 8013f38: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) 8013f3a: 68fb ldr r3, [r7, #12] 8013f3c: 685b ldr r3, [r3, #4] 8013f3e: 687a ldr r2, [r7, #4] 8013f40: 429a cmp r2, r3 8013f42: d103 bne.n 8013f4c { pxList->pxIndex = pxItemToRemove->pxPrevious; 8013f44: 687b ldr r3, [r7, #4] 8013f46: 689a ldr r2, [r3, #8] 8013f48: 68fb ldr r3, [r7, #12] 8013f4a: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; 8013f4c: 687b ldr r3, [r7, #4] 8013f4e: 2200 movs r2, #0 8013f50: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; 8013f52: 68fb ldr r3, [r7, #12] 8013f54: 681b ldr r3, [r3, #0] 8013f56: 1e5a subs r2, r3, #1 8013f58: 68fb ldr r3, [r7, #12] 8013f5a: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; 8013f5c: 68fb ldr r3, [r7, #12] 8013f5e: 681b ldr r3, [r3, #0] } 8013f60: 4618 mov r0, r3 8013f62: 3714 adds r7, #20 8013f64: 46bd mov sp, r7 8013f66: f85d 7b04 ldr.w r7, [sp], #4 8013f6a: 4770 bx lr 08013f6c : } \ taskEXIT_CRITICAL() /*-----------------------------------------------------------*/ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) { 8013f6c: b580 push {r7, lr} 8013f6e: b084 sub sp, #16 8013f70: af00 add r7, sp, #0 8013f72: 6078 str r0, [r7, #4] 8013f74: 6039 str r1, [r7, #0] Queue_t * const pxQueue = xQueue; 8013f76: 687b ldr r3, [r7, #4] 8013f78: 60fb str r3, [r7, #12] configASSERT( pxQueue ); 8013f7a: 68fb ldr r3, [r7, #12] 8013f7c: 2b00 cmp r3, #0 8013f7e: d10b bne.n 8013f98 portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile 8013f80: f04f 0350 mov.w r3, #80 @ 0x50 8013f84: f383 8811 msr BASEPRI, r3 8013f88: f3bf 8f6f isb sy 8013f8c: f3bf 8f4f dsb sy 8013f90: 60bb str r3, [r7, #8] " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } 8013f92: bf00 nop 8013f94: bf00 nop 8013f96: e7fd b.n 8013f94 taskENTER_CRITICAL(); 8013f98: f003 f95e bl 8017258 { pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8013f9c: 68fb ldr r3, [r7, #12] 8013f9e: 681a ldr r2, [r3, #0] 8013fa0: 68fb ldr r3, [r7, #12] 8013fa2: 6bdb ldr r3, [r3, #60] @ 0x3c 8013fa4: 68f9 ldr r1, [r7, #12] 8013fa6: 6c09 ldr r1, [r1, #64] @ 0x40 8013fa8: fb01 f303 mul.w r3, r1, r3 8013fac: 441a add r2, r3 8013fae: 68fb ldr r3, [r7, #12] 8013fb0: 609a str r2, [r3, #8] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 8013fb2: 68fb ldr r3, [r7, #12] 8013fb4: 2200 movs r2, #0 8013fb6: 639a str r2, [r3, #56] @ 0x38 pxQueue->pcWriteTo = pxQueue->pcHead; 8013fb8: 68fb ldr r3, [r7, #12] 8013fba: 681a ldr r2, [r3, #0] 8013fbc: 68fb ldr r3, [r7, #12] 8013fbe: 605a str r2, [r3, #4] pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8013fc0: 68fb ldr r3, [r7, #12] 8013fc2: 681a ldr r2, [r3, #0] 8013fc4: 68fb ldr r3, [r7, #12] 8013fc6: 6bdb ldr r3, [r3, #60] @ 0x3c 8013fc8: 3b01 subs r3, #1 8013fca: 68f9 ldr r1, [r7, #12] 8013fcc: 6c09 ldr r1, [r1, #64] @ 0x40 8013fce: fb01 f303 mul.w r3, r1, r3 8013fd2: 441a add r2, r3 8013fd4: 68fb ldr r3, [r7, #12] 8013fd6: 60da str r2, [r3, #12] pxQueue->cRxLock = queueUNLOCKED; 8013fd8: 68fb ldr r3, [r7, #12] 8013fda: 22ff movs r2, #255 @ 0xff 8013fdc: f883 2044 strb.w r2, [r3, #68] @ 0x44 pxQueue->cTxLock = queueUNLOCKED; 8013fe0: 68fb ldr r3, [r7, #12] 8013fe2: 22ff movs r2, #255 @ 0xff 8013fe4: f883 2045 strb.w r2, [r3, #69] @ 0x45 if( xNewQueue == pdFALSE ) 8013fe8: 683b ldr r3, [r7, #0] 8013fea: 2b00 cmp r3, #0 8013fec: d114 bne.n 8014018 /* If there are tasks blocked waiting to read from the queue, then the tasks will remain blocked as after this function exits the queue will still be empty. If there are tasks blocked waiting to write to the queue, then one should be unblocked as after this function exits it will be possible to write to it. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8013fee: 68fb ldr r3, [r7, #12] 8013ff0: 691b ldr r3, [r3, #16] 8013ff2: 2b00 cmp r3, #0 8013ff4: d01a beq.n 801402c { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8013ff6: 68fb ldr r3, [r7, #12] 8013ff8: 3310 adds r3, #16 8013ffa: 4618 mov r0, r3 8013ffc: f001 fdac bl 8015b58 8014000: 4603 mov r3, r0 8014002: 2b00 cmp r3, #0 8014004: d012 beq.n 801402c { queueYIELD_IF_USING_PREEMPTION(); 8014006: 4b0d ldr r3, [pc, #52] @ (801403c ) 8014008: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801400c: 601a str r2, [r3, #0] 801400e: f3bf 8f4f dsb sy 8014012: f3bf 8f6f isb sy 8014016: e009 b.n 801402c } } else { /* Ensure the event queues start in the correct state. */ vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 8014018: 68fb ldr r3, [r7, #12] 801401a: 3310 adds r3, #16 801401c: 4618 mov r0, r3 801401e: f7ff fef1 bl 8013e04 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); 8014022: 68fb ldr r3, [r7, #12] 8014024: 3324 adds r3, #36 @ 0x24 8014026: 4618 mov r0, r3 8014028: f7ff feec bl 8013e04 } } taskEXIT_CRITICAL(); 801402c: f003 f946 bl 80172bc /* A value is returned for calling semantic consistency with previous versions. */ return pdPASS; 8014030: 2301 movs r3, #1 } 8014032: 4618 mov r0, r3 8014034: 3710 adds r7, #16 8014036: 46bd mov sp, r7 8014038: bd80 pop {r7, pc} 801403a: bf00 nop 801403c: e000ed04 .word 0xe000ed04 08014040 : /*-----------------------------------------------------------*/ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) { 8014040: b580 push {r7, lr} 8014042: b08e sub sp, #56 @ 0x38 8014044: af02 add r7, sp, #8 8014046: 60f8 str r0, [r7, #12] 8014048: 60b9 str r1, [r7, #8] 801404a: 607a str r2, [r7, #4] 801404c: 603b str r3, [r7, #0] Queue_t *pxNewQueue; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 801404e: 68fb ldr r3, [r7, #12] 8014050: 2b00 cmp r3, #0 8014052: d10b bne.n 801406c __asm volatile 8014054: f04f 0350 mov.w r3, #80 @ 0x50 8014058: f383 8811 msr BASEPRI, r3 801405c: f3bf 8f6f isb sy 8014060: f3bf 8f4f dsb sy 8014064: 62bb str r3, [r7, #40] @ 0x28 } 8014066: bf00 nop 8014068: bf00 nop 801406a: e7fd b.n 8014068 /* The StaticQueue_t structure and the queue storage area must be supplied. */ configASSERT( pxStaticQueue != NULL ); 801406c: 683b ldr r3, [r7, #0] 801406e: 2b00 cmp r3, #0 8014070: d10b bne.n 801408a __asm volatile 8014072: f04f 0350 mov.w r3, #80 @ 0x50 8014076: f383 8811 msr BASEPRI, r3 801407a: f3bf 8f6f isb sy 801407e: f3bf 8f4f dsb sy 8014082: 627b str r3, [r7, #36] @ 0x24 } 8014084: bf00 nop 8014086: bf00 nop 8014088: e7fd b.n 8014086 /* A queue storage area should be provided if the item size is not 0, and should not be provided if the item size is 0. */ configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); 801408a: 687b ldr r3, [r7, #4] 801408c: 2b00 cmp r3, #0 801408e: d002 beq.n 8014096 8014090: 68bb ldr r3, [r7, #8] 8014092: 2b00 cmp r3, #0 8014094: d001 beq.n 801409a 8014096: 2301 movs r3, #1 8014098: e000 b.n 801409c 801409a: 2300 movs r3, #0 801409c: 2b00 cmp r3, #0 801409e: d10b bne.n 80140b8 __asm volatile 80140a0: f04f 0350 mov.w r3, #80 @ 0x50 80140a4: f383 8811 msr BASEPRI, r3 80140a8: f3bf 8f6f isb sy 80140ac: f3bf 8f4f dsb sy 80140b0: 623b str r3, [r7, #32] } 80140b2: bf00 nop 80140b4: bf00 nop 80140b6: e7fd b.n 80140b4 configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); 80140b8: 687b ldr r3, [r7, #4] 80140ba: 2b00 cmp r3, #0 80140bc: d102 bne.n 80140c4 80140be: 68bb ldr r3, [r7, #8] 80140c0: 2b00 cmp r3, #0 80140c2: d101 bne.n 80140c8 80140c4: 2301 movs r3, #1 80140c6: e000 b.n 80140ca 80140c8: 2300 movs r3, #0 80140ca: 2b00 cmp r3, #0 80140cc: d10b bne.n 80140e6 __asm volatile 80140ce: f04f 0350 mov.w r3, #80 @ 0x50 80140d2: f383 8811 msr BASEPRI, r3 80140d6: f3bf 8f6f isb sy 80140da: f3bf 8f4f dsb sy 80140de: 61fb str r3, [r7, #28] } 80140e0: bf00 nop 80140e2: bf00 nop 80140e4: e7fd b.n 80140e2 #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticQueue_t or StaticSemaphore_t equals the size of the real queue and semaphore structures. */ volatile size_t xSize = sizeof( StaticQueue_t ); 80140e6: 2350 movs r3, #80 @ 0x50 80140e8: 617b str r3, [r7, #20] configASSERT( xSize == sizeof( Queue_t ) ); 80140ea: 697b ldr r3, [r7, #20] 80140ec: 2b50 cmp r3, #80 @ 0x50 80140ee: d00b beq.n 8014108 __asm volatile 80140f0: f04f 0350 mov.w r3, #80 @ 0x50 80140f4: f383 8811 msr BASEPRI, r3 80140f8: f3bf 8f6f isb sy 80140fc: f3bf 8f4f dsb sy 8014100: 61bb str r3, [r7, #24] } 8014102: bf00 nop 8014104: bf00 nop 8014106: e7fd b.n 8014104 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 8014108: 697b ldr r3, [r7, #20] #endif /* configASSERT_DEFINED */ /* The address of a statically allocated queue was passed in, use it. The address of a statically allocated storage area was also passed in but is already set. */ pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 801410a: 683b ldr r3, [r7, #0] 801410c: 62fb str r3, [r7, #44] @ 0x2c if( pxNewQueue != NULL ) 801410e: 6afb ldr r3, [r7, #44] @ 0x2c 8014110: 2b00 cmp r3, #0 8014112: d00d beq.n 8014130 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* Queues can be allocated wither statically or dynamically, so note this queue was allocated statically in case the queue is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdTRUE; 8014114: 6afb ldr r3, [r7, #44] @ 0x2c 8014116: 2201 movs r2, #1 8014118: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 801411c: f897 2038 ldrb.w r2, [r7, #56] @ 0x38 8014120: 6afb ldr r3, [r7, #44] @ 0x2c 8014122: 9300 str r3, [sp, #0] 8014124: 4613 mov r3, r2 8014126: 687a ldr r2, [r7, #4] 8014128: 68b9 ldr r1, [r7, #8] 801412a: 68f8 ldr r0, [r7, #12] 801412c: f000 f840 bl 80141b0 { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 8014130: 6afb ldr r3, [r7, #44] @ 0x2c } 8014132: 4618 mov r0, r3 8014134: 3730 adds r7, #48 @ 0x30 8014136: 46bd mov sp, r7 8014138: bd80 pop {r7, pc} 0801413a : /*-----------------------------------------------------------*/ #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) { 801413a: b580 push {r7, lr} 801413c: b08a sub sp, #40 @ 0x28 801413e: af02 add r7, sp, #8 8014140: 60f8 str r0, [r7, #12] 8014142: 60b9 str r1, [r7, #8] 8014144: 4613 mov r3, r2 8014146: 71fb strb r3, [r7, #7] Queue_t *pxNewQueue; size_t xQueueSizeInBytes; uint8_t *pucQueueStorage; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 8014148: 68fb ldr r3, [r7, #12] 801414a: 2b00 cmp r3, #0 801414c: d10b bne.n 8014166 __asm volatile 801414e: f04f 0350 mov.w r3, #80 @ 0x50 8014152: f383 8811 msr BASEPRI, r3 8014156: f3bf 8f6f isb sy 801415a: f3bf 8f4f dsb sy 801415e: 613b str r3, [r7, #16] } 8014160: bf00 nop 8014162: bf00 nop 8014164: e7fd b.n 8014162 /* Allocate enough space to hold the maximum number of items that can be in the queue at any time. It is valid for uxItemSize to be zero in the case the queue is used as a semaphore. */ xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8014166: 68fb ldr r3, [r7, #12] 8014168: 68ba ldr r2, [r7, #8] 801416a: fb02 f303 mul.w r3, r2, r3 801416e: 61fb str r3, [r7, #28] alignment requirements of the Queue_t structure - which in this case is an int8_t *. Therefore, whenever the stack alignment requirements are greater than or equal to the pointer to char requirements the cast is safe. In other cases alignment requirements are not strict (one or two bytes). */ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ 8014170: 69fb ldr r3, [r7, #28] 8014172: 3350 adds r3, #80 @ 0x50 8014174: 4618 mov r0, r3 8014176: f003 f991 bl 801749c 801417a: 61b8 str r0, [r7, #24] if( pxNewQueue != NULL ) 801417c: 69bb ldr r3, [r7, #24] 801417e: 2b00 cmp r3, #0 8014180: d011 beq.n 80141a6 { /* Jump past the queue structure to find the location of the queue storage area. */ pucQueueStorage = ( uint8_t * ) pxNewQueue; 8014182: 69bb ldr r3, [r7, #24] 8014184: 617b str r3, [r7, #20] pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8014186: 697b ldr r3, [r7, #20] 8014188: 3350 adds r3, #80 @ 0x50 801418a: 617b str r3, [r7, #20] #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { /* Queues can be created either statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdFALSE; 801418c: 69bb ldr r3, [r7, #24] 801418e: 2200 movs r2, #0 8014190: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_STATIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8014194: 79fa ldrb r2, [r7, #7] 8014196: 69bb ldr r3, [r7, #24] 8014198: 9300 str r3, [sp, #0] 801419a: 4613 mov r3, r2 801419c: 697a ldr r2, [r7, #20] 801419e: 68b9 ldr r1, [r7, #8] 80141a0: 68f8 ldr r0, [r7, #12] 80141a2: f000 f805 bl 80141b0 { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 80141a6: 69bb ldr r3, [r7, #24] } 80141a8: 4618 mov r0, r3 80141aa: 3720 adds r7, #32 80141ac: 46bd mov sp, r7 80141ae: bd80 pop {r7, pc} 080141b0 : #endif /* configSUPPORT_STATIC_ALLOCATION */ /*-----------------------------------------------------------*/ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) { 80141b0: b580 push {r7, lr} 80141b2: b084 sub sp, #16 80141b4: af00 add r7, sp, #0 80141b6: 60f8 str r0, [r7, #12] 80141b8: 60b9 str r1, [r7, #8] 80141ba: 607a str r2, [r7, #4] 80141bc: 70fb strb r3, [r7, #3] /* Remove compiler warnings about unused parameters should configUSE_TRACE_FACILITY not be set to 1. */ ( void ) ucQueueType; if( uxItemSize == ( UBaseType_t ) 0 ) 80141be: 68bb ldr r3, [r7, #8] 80141c0: 2b00 cmp r3, #0 80141c2: d103 bne.n 80141cc { /* No RAM was allocated for the queue storage area, but PC head cannot be set to NULL because NULL is used as a key to say the queue is used as a mutex. Therefore just set pcHead to point to the queue as a benign value that is known to be within the memory map. */ pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; 80141c4: 69bb ldr r3, [r7, #24] 80141c6: 69ba ldr r2, [r7, #24] 80141c8: 601a str r2, [r3, #0] 80141ca: e002 b.n 80141d2 } else { /* Set the head to the start of the queue storage area. */ pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; 80141cc: 69bb ldr r3, [r7, #24] 80141ce: 687a ldr r2, [r7, #4] 80141d0: 601a str r2, [r3, #0] } /* Initialise the queue members as described where the queue type is defined. */ pxNewQueue->uxLength = uxQueueLength; 80141d2: 69bb ldr r3, [r7, #24] 80141d4: 68fa ldr r2, [r7, #12] 80141d6: 63da str r2, [r3, #60] @ 0x3c pxNewQueue->uxItemSize = uxItemSize; 80141d8: 69bb ldr r3, [r7, #24] 80141da: 68ba ldr r2, [r7, #8] 80141dc: 641a str r2, [r3, #64] @ 0x40 ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); 80141de: 2101 movs r1, #1 80141e0: 69b8 ldr r0, [r7, #24] 80141e2: f7ff fec3 bl 8013f6c #if ( configUSE_TRACE_FACILITY == 1 ) { pxNewQueue->ucQueueType = ucQueueType; 80141e6: 69bb ldr r3, [r7, #24] 80141e8: 78fa ldrb r2, [r7, #3] 80141ea: f883 204c strb.w r2, [r3, #76] @ 0x4c pxNewQueue->pxQueueSetContainer = NULL; } #endif /* configUSE_QUEUE_SETS */ traceQUEUE_CREATE( pxNewQueue ); } 80141ee: bf00 nop 80141f0: 3710 adds r7, #16 80141f2: 46bd mov sp, r7 80141f4: bd80 pop {r7, pc} 080141f6 : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static void prvInitialiseMutex( Queue_t *pxNewQueue ) { 80141f6: b580 push {r7, lr} 80141f8: b082 sub sp, #8 80141fa: af00 add r7, sp, #0 80141fc: 6078 str r0, [r7, #4] if( pxNewQueue != NULL ) 80141fe: 687b ldr r3, [r7, #4] 8014200: 2b00 cmp r3, #0 8014202: d00e beq.n 8014222 { /* The queue create function will set all the queue structure members correctly for a generic queue, but this function is creating a mutex. Overwrite those members that need to be set differently - in particular the information required for priority inheritance. */ pxNewQueue->u.xSemaphore.xMutexHolder = NULL; 8014204: 687b ldr r3, [r7, #4] 8014206: 2200 movs r2, #0 8014208: 609a str r2, [r3, #8] pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; 801420a: 687b ldr r3, [r7, #4] 801420c: 2200 movs r2, #0 801420e: 601a str r2, [r3, #0] /* In case this is a recursive mutex. */ pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; 8014210: 687b ldr r3, [r7, #4] 8014212: 2200 movs r2, #0 8014214: 60da str r2, [r3, #12] traceCREATE_MUTEX( pxNewQueue ); /* Start with the semaphore in the expected state. */ ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); 8014216: 2300 movs r3, #0 8014218: 2200 movs r2, #0 801421a: 2100 movs r1, #0 801421c: 6878 ldr r0, [r7, #4] 801421e: f000 f8a3 bl 8014368 } else { traceCREATE_MUTEX_FAILED(); } } 8014222: bf00 nop 8014224: 3708 adds r7, #8 8014226: 46bd mov sp, r7 8014228: bd80 pop {r7, pc} 0801422a : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) { 801422a: b580 push {r7, lr} 801422c: b086 sub sp, #24 801422e: af00 add r7, sp, #0 8014230: 4603 mov r3, r0 8014232: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8014234: 2301 movs r3, #1 8014236: 617b str r3, [r7, #20] 8014238: 2300 movs r3, #0 801423a: 613b str r3, [r7, #16] xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); 801423c: 79fb ldrb r3, [r7, #7] 801423e: 461a mov r2, r3 8014240: 6939 ldr r1, [r7, #16] 8014242: 6978 ldr r0, [r7, #20] 8014244: f7ff ff79 bl 801413a 8014248: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 801424a: 68f8 ldr r0, [r7, #12] 801424c: f7ff ffd3 bl 80141f6 return xNewQueue; 8014250: 68fb ldr r3, [r7, #12] } 8014252: 4618 mov r0, r3 8014254: 3718 adds r7, #24 8014256: 46bd mov sp, r7 8014258: bd80 pop {r7, pc} 0801425a : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) { 801425a: b580 push {r7, lr} 801425c: b088 sub sp, #32 801425e: af02 add r7, sp, #8 8014260: 4603 mov r3, r0 8014262: 6039 str r1, [r7, #0] 8014264: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8014266: 2301 movs r3, #1 8014268: 617b str r3, [r7, #20] 801426a: 2300 movs r3, #0 801426c: 613b str r3, [r7, #16] /* Prevent compiler warnings about unused parameters if configUSE_TRACE_FACILITY does not equal 1. */ ( void ) ucQueueType; xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); 801426e: 79fb ldrb r3, [r7, #7] 8014270: 9300 str r3, [sp, #0] 8014272: 683b ldr r3, [r7, #0] 8014274: 2200 movs r2, #0 8014276: 6939 ldr r1, [r7, #16] 8014278: 6978 ldr r0, [r7, #20] 801427a: f7ff fee1 bl 8014040 801427e: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 8014280: 68f8 ldr r0, [r7, #12] 8014282: f7ff ffb8 bl 80141f6 return xNewQueue; 8014286: 68fb ldr r3, [r7, #12] } 8014288: 4618 mov r0, r3 801428a: 3718 adds r7, #24 801428c: 46bd mov sp, r7 801428e: bd80 pop {r7, pc} 08014290 : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) { 8014290: b590 push {r4, r7, lr} 8014292: b087 sub sp, #28 8014294: af00 add r7, sp, #0 8014296: 6078 str r0, [r7, #4] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8014298: 687b ldr r3, [r7, #4] 801429a: 613b str r3, [r7, #16] configASSERT( pxMutex ); 801429c: 693b ldr r3, [r7, #16] 801429e: 2b00 cmp r3, #0 80142a0: d10b bne.n 80142ba __asm volatile 80142a2: f04f 0350 mov.w r3, #80 @ 0x50 80142a6: f383 8811 msr BASEPRI, r3 80142aa: f3bf 8f6f isb sy 80142ae: f3bf 8f4f dsb sy 80142b2: 60fb str r3, [r7, #12] } 80142b4: bf00 nop 80142b6: bf00 nop 80142b8: e7fd b.n 80142b6 change outside of this task. If this task does not hold the mutex then pxMutexHolder can never coincidentally equal the tasks handle, and as this is the only condition we are interested in it does not matter if pxMutexHolder is accessed simultaneously by another task. Therefore no mutual exclusion is required to test the pxMutexHolder variable. */ if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 80142ba: 693b ldr r3, [r7, #16] 80142bc: 689c ldr r4, [r3, #8] 80142be: f001 fe39 bl 8015f34 80142c2: 4603 mov r3, r0 80142c4: 429c cmp r4, r3 80142c6: d111 bne.n 80142ec /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to the task handle, therefore no underflow check is required. Also, uxRecursiveCallCount is only modified by the mutex holder, and as there can only be one, no mutual exclusion is required to modify the uxRecursiveCallCount member. */ ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; 80142c8: 693b ldr r3, [r7, #16] 80142ca: 68db ldr r3, [r3, #12] 80142cc: 1e5a subs r2, r3, #1 80142ce: 693b ldr r3, [r7, #16] 80142d0: 60da str r2, [r3, #12] /* Has the recursive call count unwound to 0? */ if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) 80142d2: 693b ldr r3, [r7, #16] 80142d4: 68db ldr r3, [r3, #12] 80142d6: 2b00 cmp r3, #0 80142d8: d105 bne.n 80142e6 { /* Return the mutex. This will automatically unblock any other task that might be waiting to access the mutex. */ ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); 80142da: 2300 movs r3, #0 80142dc: 2200 movs r2, #0 80142de: 2100 movs r1, #0 80142e0: 6938 ldr r0, [r7, #16] 80142e2: f000 f841 bl 8014368 else { mtCOVERAGE_TEST_MARKER(); } xReturn = pdPASS; 80142e6: 2301 movs r3, #1 80142e8: 617b str r3, [r7, #20] 80142ea: e001 b.n 80142f0 } else { /* The mutex cannot be given because the calling task is not the holder. */ xReturn = pdFAIL; 80142ec: 2300 movs r3, #0 80142ee: 617b str r3, [r7, #20] traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); } return xReturn; 80142f0: 697b ldr r3, [r7, #20] } 80142f2: 4618 mov r0, r3 80142f4: 371c adds r7, #28 80142f6: 46bd mov sp, r7 80142f8: bd90 pop {r4, r7, pc} 080142fa : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) { 80142fa: b590 push {r4, r7, lr} 80142fc: b087 sub sp, #28 80142fe: af00 add r7, sp, #0 8014300: 6078 str r0, [r7, #4] 8014302: 6039 str r1, [r7, #0] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8014304: 687b ldr r3, [r7, #4] 8014306: 613b str r3, [r7, #16] configASSERT( pxMutex ); 8014308: 693b ldr r3, [r7, #16] 801430a: 2b00 cmp r3, #0 801430c: d10b bne.n 8014326 __asm volatile 801430e: f04f 0350 mov.w r3, #80 @ 0x50 8014312: f383 8811 msr BASEPRI, r3 8014316: f3bf 8f6f isb sy 801431a: f3bf 8f4f dsb sy 801431e: 60fb str r3, [r7, #12] } 8014320: bf00 nop 8014322: bf00 nop 8014324: e7fd b.n 8014322 /* Comments regarding mutual exclusion as per those within xQueueGiveMutexRecursive(). */ traceTAKE_MUTEX_RECURSIVE( pxMutex ); if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 8014326: 693b ldr r3, [r7, #16] 8014328: 689c ldr r4, [r3, #8] 801432a: f001 fe03 bl 8015f34 801432e: 4603 mov r3, r0 8014330: 429c cmp r4, r3 8014332: d107 bne.n 8014344 { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 8014334: 693b ldr r3, [r7, #16] 8014336: 68db ldr r3, [r3, #12] 8014338: 1c5a adds r2, r3, #1 801433a: 693b ldr r3, [r7, #16] 801433c: 60da str r2, [r3, #12] xReturn = pdPASS; 801433e: 2301 movs r3, #1 8014340: 617b str r3, [r7, #20] 8014342: e00c b.n 801435e } else { xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait ); 8014344: 6839 ldr r1, [r7, #0] 8014346: 6938 ldr r0, [r7, #16] 8014348: f000 fa90 bl 801486c 801434c: 6178 str r0, [r7, #20] /* pdPASS will only be returned if the mutex was successfully obtained. The calling task may have entered the Blocked state before reaching here. */ if( xReturn != pdFAIL ) 801434e: 697b ldr r3, [r7, #20] 8014350: 2b00 cmp r3, #0 8014352: d004 beq.n 801435e { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 8014354: 693b ldr r3, [r7, #16] 8014356: 68db ldr r3, [r3, #12] 8014358: 1c5a adds r2, r3, #1 801435a: 693b ldr r3, [r7, #16] 801435c: 60da str r2, [r3, #12] { traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ); } } return xReturn; 801435e: 697b ldr r3, [r7, #20] } 8014360: 4618 mov r0, r3 8014362: 371c adds r7, #28 8014364: 46bd mov sp, r7 8014366: bd90 pop {r4, r7, pc} 08014368 : #endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) { 8014368: b580 push {r7, lr} 801436a: b08e sub sp, #56 @ 0x38 801436c: af00 add r7, sp, #0 801436e: 60f8 str r0, [r7, #12] 8014370: 60b9 str r1, [r7, #8] 8014372: 607a str r2, [r7, #4] 8014374: 603b str r3, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; 8014376: 2300 movs r3, #0 8014378: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 801437a: 68fb ldr r3, [r7, #12] 801437c: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 801437e: 6b3b ldr r3, [r7, #48] @ 0x30 8014380: 2b00 cmp r3, #0 8014382: d10b bne.n 801439c __asm volatile 8014384: f04f 0350 mov.w r3, #80 @ 0x50 8014388: f383 8811 msr BASEPRI, r3 801438c: f3bf 8f6f isb sy 8014390: f3bf 8f4f dsb sy 8014394: 62bb str r3, [r7, #40] @ 0x28 } 8014396: bf00 nop 8014398: bf00 nop 801439a: e7fd b.n 8014398 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 801439c: 68bb ldr r3, [r7, #8] 801439e: 2b00 cmp r3, #0 80143a0: d103 bne.n 80143aa 80143a2: 6b3b ldr r3, [r7, #48] @ 0x30 80143a4: 6c1b ldr r3, [r3, #64] @ 0x40 80143a6: 2b00 cmp r3, #0 80143a8: d101 bne.n 80143ae 80143aa: 2301 movs r3, #1 80143ac: e000 b.n 80143b0 80143ae: 2300 movs r3, #0 80143b0: 2b00 cmp r3, #0 80143b2: d10b bne.n 80143cc __asm volatile 80143b4: f04f 0350 mov.w r3, #80 @ 0x50 80143b8: f383 8811 msr BASEPRI, r3 80143bc: f3bf 8f6f isb sy 80143c0: f3bf 8f4f dsb sy 80143c4: 627b str r3, [r7, #36] @ 0x24 } 80143c6: bf00 nop 80143c8: bf00 nop 80143ca: e7fd b.n 80143c8 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 80143cc: 683b ldr r3, [r7, #0] 80143ce: 2b02 cmp r3, #2 80143d0: d103 bne.n 80143da 80143d2: 6b3b ldr r3, [r7, #48] @ 0x30 80143d4: 6bdb ldr r3, [r3, #60] @ 0x3c 80143d6: 2b01 cmp r3, #1 80143d8: d101 bne.n 80143de 80143da: 2301 movs r3, #1 80143dc: e000 b.n 80143e0 80143de: 2300 movs r3, #0 80143e0: 2b00 cmp r3, #0 80143e2: d10b bne.n 80143fc __asm volatile 80143e4: f04f 0350 mov.w r3, #80 @ 0x50 80143e8: f383 8811 msr BASEPRI, r3 80143ec: f3bf 8f6f isb sy 80143f0: f3bf 8f4f dsb sy 80143f4: 623b str r3, [r7, #32] } 80143f6: bf00 nop 80143f8: bf00 nop 80143fa: e7fd b.n 80143f8 #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 80143fc: f001 fdaa bl 8015f54 8014400: 4603 mov r3, r0 8014402: 2b00 cmp r3, #0 8014404: d102 bne.n 801440c 8014406: 687b ldr r3, [r7, #4] 8014408: 2b00 cmp r3, #0 801440a: d101 bne.n 8014410 801440c: 2301 movs r3, #1 801440e: e000 b.n 8014412 8014410: 2300 movs r3, #0 8014412: 2b00 cmp r3, #0 8014414: d10b bne.n 801442e __asm volatile 8014416: f04f 0350 mov.w r3, #80 @ 0x50 801441a: f383 8811 msr BASEPRI, r3 801441e: f3bf 8f6f isb sy 8014422: f3bf 8f4f dsb sy 8014426: 61fb str r3, [r7, #28] } 8014428: bf00 nop 801442a: bf00 nop 801442c: e7fd b.n 801442a /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 801442e: f002 ff13 bl 8017258 { /* Is there room on the queue now? The running task must be the highest priority task wanting to access the queue. If the head item in the queue is to be overwritten then it does not matter if the queue is full. */ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 8014432: 6b3b ldr r3, [r7, #48] @ 0x30 8014434: 6b9a ldr r2, [r3, #56] @ 0x38 8014436: 6b3b ldr r3, [r7, #48] @ 0x30 8014438: 6bdb ldr r3, [r3, #60] @ 0x3c 801443a: 429a cmp r2, r3 801443c: d302 bcc.n 8014444 801443e: 683b ldr r3, [r7, #0] 8014440: 2b02 cmp r3, #2 8014442: d129 bne.n 8014498 } } } #else /* configUSE_QUEUE_SETS */ { xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 8014444: 683a ldr r2, [r7, #0] 8014446: 68b9 ldr r1, [r7, #8] 8014448: 6b38 ldr r0, [r7, #48] @ 0x30 801444a: f000 fbb9 bl 8014bc0 801444e: 62f8 str r0, [r7, #44] @ 0x2c /* If there was a task waiting for data to arrive on the queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8014450: 6b3b ldr r3, [r7, #48] @ 0x30 8014452: 6a5b ldr r3, [r3, #36] @ 0x24 8014454: 2b00 cmp r3, #0 8014456: d010 beq.n 801447a { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8014458: 6b3b ldr r3, [r7, #48] @ 0x30 801445a: 3324 adds r3, #36 @ 0x24 801445c: 4618 mov r0, r3 801445e: f001 fb7b bl 8015b58 8014462: 4603 mov r3, r0 8014464: 2b00 cmp r3, #0 8014466: d013 beq.n 8014490 { /* The unblocked task has a priority higher than our own so yield immediately. Yes it is ok to do this from within the critical section - the kernel takes care of that. */ queueYIELD_IF_USING_PREEMPTION(); 8014468: 4b3f ldr r3, [pc, #252] @ (8014568 ) 801446a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801446e: 601a str r2, [r3, #0] 8014470: f3bf 8f4f dsb sy 8014474: f3bf 8f6f isb sy 8014478: e00a b.n 8014490 else { mtCOVERAGE_TEST_MARKER(); } } else if( xYieldRequired != pdFALSE ) 801447a: 6afb ldr r3, [r7, #44] @ 0x2c 801447c: 2b00 cmp r3, #0 801447e: d007 beq.n 8014490 { /* This path is a special case that will only get executed if the task was holding multiple mutexes and the mutexes were given back in an order that is different to that in which they were taken. */ queueYIELD_IF_USING_PREEMPTION(); 8014480: 4b39 ldr r3, [pc, #228] @ (8014568 ) 8014482: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014486: 601a str r2, [r3, #0] 8014488: f3bf 8f4f dsb sy 801448c: f3bf 8f6f isb sy mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); 8014490: f002 ff14 bl 80172bc return pdPASS; 8014494: 2301 movs r3, #1 8014496: e063 b.n 8014560 } else { if( xTicksToWait == ( TickType_t ) 0 ) 8014498: 687b ldr r3, [r7, #4] 801449a: 2b00 cmp r3, #0 801449c: d103 bne.n 80144a6 { /* The queue was full and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 801449e: f002 ff0d bl 80172bc /* Return to the original privilege level before exiting the function. */ traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 80144a2: 2300 movs r3, #0 80144a4: e05c b.n 8014560 } else if( xEntryTimeSet == pdFALSE ) 80144a6: 6b7b ldr r3, [r7, #52] @ 0x34 80144a8: 2b00 cmp r3, #0 80144aa: d106 bne.n 80144ba { /* The queue was full and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 80144ac: f107 0314 add.w r3, r7, #20 80144b0: 4618 mov r0, r3 80144b2: f001 fbdd bl 8015c70 xEntryTimeSet = pdTRUE; 80144b6: 2301 movs r3, #1 80144b8: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 80144ba: f002 feff bl 80172bc /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 80144be: f001 f90f bl 80156e0 prvLockQueue( pxQueue ); 80144c2: f002 fec9 bl 8017258 80144c6: 6b3b ldr r3, [r7, #48] @ 0x30 80144c8: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80144cc: b25b sxtb r3, r3 80144ce: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80144d2: d103 bne.n 80144dc 80144d4: 6b3b ldr r3, [r7, #48] @ 0x30 80144d6: 2200 movs r2, #0 80144d8: f883 2044 strb.w r2, [r3, #68] @ 0x44 80144dc: 6b3b ldr r3, [r7, #48] @ 0x30 80144de: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80144e2: b25b sxtb r3, r3 80144e4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80144e8: d103 bne.n 80144f2 80144ea: 6b3b ldr r3, [r7, #48] @ 0x30 80144ec: 2200 movs r2, #0 80144ee: f883 2045 strb.w r2, [r3, #69] @ 0x45 80144f2: f002 fee3 bl 80172bc /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 80144f6: 1d3a adds r2, r7, #4 80144f8: f107 0314 add.w r3, r7, #20 80144fc: 4611 mov r1, r2 80144fe: 4618 mov r0, r3 8014500: f001 fbcc bl 8015c9c 8014504: 4603 mov r3, r0 8014506: 2b00 cmp r3, #0 8014508: d124 bne.n 8014554 { if( prvIsQueueFull( pxQueue ) != pdFALSE ) 801450a: 6b38 ldr r0, [r7, #48] @ 0x30 801450c: f000 fc50 bl 8014db0 8014510: 4603 mov r3, r0 8014512: 2b00 cmp r3, #0 8014514: d018 beq.n 8014548 { traceBLOCKING_ON_QUEUE_SEND( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); 8014516: 6b3b ldr r3, [r7, #48] @ 0x30 8014518: 3310 adds r3, #16 801451a: 687a ldr r2, [r7, #4] 801451c: 4611 mov r1, r2 801451e: 4618 mov r0, r3 8014520: f001 fac8 bl 8015ab4 /* Unlocking the queue means queue events can effect the event list. It is possible that interrupts occurring now remove this task from the event list again - but as the scheduler is suspended the task will go onto the pending ready last instead of the actual ready list. */ prvUnlockQueue( pxQueue ); 8014524: 6b38 ldr r0, [r7, #48] @ 0x30 8014526: f000 fbdb bl 8014ce0 /* Resuming the scheduler will move tasks from the pending ready list into the ready list - so it is feasible that this task is already in a ready list before it yields - in which case the yield will not cause a context switch unless there is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) 801452a: f001 f8e7 bl 80156fc 801452e: 4603 mov r3, r0 8014530: 2b00 cmp r3, #0 8014532: f47f af7c bne.w 801442e { portYIELD_WITHIN_API(); 8014536: 4b0c ldr r3, [pc, #48] @ (8014568 ) 8014538: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801453c: 601a str r2, [r3, #0] 801453e: f3bf 8f4f dsb sy 8014542: f3bf 8f6f isb sy 8014546: e772 b.n 801442e } } else { /* Try again. */ prvUnlockQueue( pxQueue ); 8014548: 6b38 ldr r0, [r7, #48] @ 0x30 801454a: f000 fbc9 bl 8014ce0 ( void ) xTaskResumeAll(); 801454e: f001 f8d5 bl 80156fc 8014552: e76c b.n 801442e } } else { /* The timeout has expired. */ prvUnlockQueue( pxQueue ); 8014554: 6b38 ldr r0, [r7, #48] @ 0x30 8014556: f000 fbc3 bl 8014ce0 ( void ) xTaskResumeAll(); 801455a: f001 f8cf bl 80156fc traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 801455e: 2300 movs r3, #0 } } /*lint -restore */ } 8014560: 4618 mov r0, r3 8014562: 3738 adds r7, #56 @ 0x38 8014564: 46bd mov sp, r7 8014566: bd80 pop {r7, pc} 8014568: e000ed04 .word 0xe000ed04 0801456c : /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) { 801456c: b580 push {r7, lr} 801456e: b090 sub sp, #64 @ 0x40 8014570: af00 add r7, sp, #0 8014572: 60f8 str r0, [r7, #12] 8014574: 60b9 str r1, [r7, #8] 8014576: 607a str r2, [r7, #4] 8014578: 603b str r3, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 801457a: 68fb ldr r3, [r7, #12] 801457c: 63bb str r3, [r7, #56] @ 0x38 configASSERT( pxQueue ); 801457e: 6bbb ldr r3, [r7, #56] @ 0x38 8014580: 2b00 cmp r3, #0 8014582: d10b bne.n 801459c __asm volatile 8014584: f04f 0350 mov.w r3, #80 @ 0x50 8014588: f383 8811 msr BASEPRI, r3 801458c: f3bf 8f6f isb sy 8014590: f3bf 8f4f dsb sy 8014594: 62bb str r3, [r7, #40] @ 0x28 } 8014596: bf00 nop 8014598: bf00 nop 801459a: e7fd b.n 8014598 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 801459c: 68bb ldr r3, [r7, #8] 801459e: 2b00 cmp r3, #0 80145a0: d103 bne.n 80145aa 80145a2: 6bbb ldr r3, [r7, #56] @ 0x38 80145a4: 6c1b ldr r3, [r3, #64] @ 0x40 80145a6: 2b00 cmp r3, #0 80145a8: d101 bne.n 80145ae 80145aa: 2301 movs r3, #1 80145ac: e000 b.n 80145b0 80145ae: 2300 movs r3, #0 80145b0: 2b00 cmp r3, #0 80145b2: d10b bne.n 80145cc __asm volatile 80145b4: f04f 0350 mov.w r3, #80 @ 0x50 80145b8: f383 8811 msr BASEPRI, r3 80145bc: f3bf 8f6f isb sy 80145c0: f3bf 8f4f dsb sy 80145c4: 627b str r3, [r7, #36] @ 0x24 } 80145c6: bf00 nop 80145c8: bf00 nop 80145ca: e7fd b.n 80145c8 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 80145cc: 683b ldr r3, [r7, #0] 80145ce: 2b02 cmp r3, #2 80145d0: d103 bne.n 80145da 80145d2: 6bbb ldr r3, [r7, #56] @ 0x38 80145d4: 6bdb ldr r3, [r3, #60] @ 0x3c 80145d6: 2b01 cmp r3, #1 80145d8: d101 bne.n 80145de 80145da: 2301 movs r3, #1 80145dc: e000 b.n 80145e0 80145de: 2300 movs r3, #0 80145e0: 2b00 cmp r3, #0 80145e2: d10b bne.n 80145fc __asm volatile 80145e4: f04f 0350 mov.w r3, #80 @ 0x50 80145e8: f383 8811 msr BASEPRI, r3 80145ec: f3bf 8f6f isb sy 80145f0: f3bf 8f4f dsb sy 80145f4: 623b str r3, [r7, #32] } 80145f6: bf00 nop 80145f8: bf00 nop 80145fa: e7fd b.n 80145f8 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 80145fc: f002 ff0c bl 8017418 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile 8014600: f3ef 8211 mrs r2, BASEPRI 8014604: f04f 0350 mov.w r3, #80 @ 0x50 8014608: f383 8811 msr BASEPRI, r3 801460c: f3bf 8f6f isb sy 8014610: f3bf 8f4f dsb sy 8014614: 61fa str r2, [r7, #28] 8014616: 61bb str r3, [r7, #24] :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; 8014618: 69fb ldr r3, [r7, #28] /* Similar to xQueueGenericSend, except without blocking if there is no room in the queue. Also don't directly wake a task that was blocked on a queue read, instead return a flag to say whether a context switch is required or not (i.e. has a task with a higher priority than us been woken by this post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 801461a: 637b str r3, [r7, #52] @ 0x34 { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 801461c: 6bbb ldr r3, [r7, #56] @ 0x38 801461e: 6b9a ldr r2, [r3, #56] @ 0x38 8014620: 6bbb ldr r3, [r7, #56] @ 0x38 8014622: 6bdb ldr r3, [r3, #60] @ 0x3c 8014624: 429a cmp r2, r3 8014626: d302 bcc.n 801462e 8014628: 683b ldr r3, [r7, #0] 801462a: 2b02 cmp r3, #2 801462c: d12f bne.n 801468e { const int8_t cTxLock = pxQueue->cTxLock; 801462e: 6bbb ldr r3, [r7, #56] @ 0x38 8014630: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014634: f887 3033 strb.w r3, [r7, #51] @ 0x33 const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; 8014638: 6bbb ldr r3, [r7, #56] @ 0x38 801463a: 6b9b ldr r3, [r3, #56] @ 0x38 801463c: 62fb str r3, [r7, #44] @ 0x2c /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a semaphore or mutex. That means prvCopyDataToQueue() cannot result in a task disinheriting a priority and prvCopyDataToQueue() can be called here even though the disinherit function does not check if the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 801463e: 683a ldr r2, [r7, #0] 8014640: 68b9 ldr r1, [r7, #8] 8014642: 6bb8 ldr r0, [r7, #56] @ 0x38 8014644: f000 fabc bl 8014bc0 /* The event list is not altered if the queue is locked. This will be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 8014648: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33 801464c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014650: d112 bne.n 8014678 } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8014652: 6bbb ldr r3, [r7, #56] @ 0x38 8014654: 6a5b ldr r3, [r3, #36] @ 0x24 8014656: 2b00 cmp r3, #0 8014658: d016 beq.n 8014688 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 801465a: 6bbb ldr r3, [r7, #56] @ 0x38 801465c: 3324 adds r3, #36 @ 0x24 801465e: 4618 mov r0, r3 8014660: f001 fa7a bl 8015b58 8014664: 4603 mov r3, r0 8014666: 2b00 cmp r3, #0 8014668: d00e beq.n 8014688 { /* The task waiting has a higher priority so record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 801466a: 687b ldr r3, [r7, #4] 801466c: 2b00 cmp r3, #0 801466e: d00b beq.n 8014688 { *pxHigherPriorityTaskWoken = pdTRUE; 8014670: 687b ldr r3, [r7, #4] 8014672: 2201 movs r2, #1 8014674: 601a str r2, [r3, #0] 8014676: e007 b.n 8014688 } else { /* Increment the lock count so the task that unlocks the queue knows that data was posted while it was locked. */ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); 8014678: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 801467c: 3301 adds r3, #1 801467e: b2db uxtb r3, r3 8014680: b25a sxtb r2, r3 8014682: 6bbb ldr r3, [r7, #56] @ 0x38 8014684: f883 2045 strb.w r2, [r3, #69] @ 0x45 } xReturn = pdPASS; 8014688: 2301 movs r3, #1 801468a: 63fb str r3, [r7, #60] @ 0x3c { 801468c: e001 b.n 8014692 } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 801468e: 2300 movs r3, #0 8014690: 63fb str r3, [r7, #60] @ 0x3c 8014692: 6b7b ldr r3, [r7, #52] @ 0x34 8014694: 617b str r3, [r7, #20] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile 8014696: 697b ldr r3, [r7, #20] 8014698: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } 801469c: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 801469e: 6bfb ldr r3, [r7, #60] @ 0x3c } 80146a0: 4618 mov r0, r3 80146a2: 3740 adds r7, #64 @ 0x40 80146a4: 46bd mov sp, r7 80146a6: bd80 pop {r7, pc} 080146a8 : return xReturn; } /*-----------------------------------------------------------*/ BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) { 80146a8: b580 push {r7, lr} 80146aa: b08c sub sp, #48 @ 0x30 80146ac: af00 add r7, sp, #0 80146ae: 60f8 str r0, [r7, #12] 80146b0: 60b9 str r1, [r7, #8] 80146b2: 607a str r2, [r7, #4] BaseType_t xEntryTimeSet = pdFALSE; 80146b4: 2300 movs r3, #0 80146b6: 62fb str r3, [r7, #44] @ 0x2c TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 80146b8: 68fb ldr r3, [r7, #12] 80146ba: 62bb str r3, [r7, #40] @ 0x28 /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); 80146bc: 6abb ldr r3, [r7, #40] @ 0x28 80146be: 2b00 cmp r3, #0 80146c0: d10b bne.n 80146da __asm volatile 80146c2: f04f 0350 mov.w r3, #80 @ 0x50 80146c6: f383 8811 msr BASEPRI, r3 80146ca: f3bf 8f6f isb sy 80146ce: f3bf 8f4f dsb sy 80146d2: 623b str r3, [r7, #32] } 80146d4: bf00 nop 80146d6: bf00 nop 80146d8: e7fd b.n 80146d6 /* The buffer into which data is received can only be NULL if the data size is zero (so no data is copied into the buffer. */ configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); 80146da: 68bb ldr r3, [r7, #8] 80146dc: 2b00 cmp r3, #0 80146de: d103 bne.n 80146e8 80146e0: 6abb ldr r3, [r7, #40] @ 0x28 80146e2: 6c1b ldr r3, [r3, #64] @ 0x40 80146e4: 2b00 cmp r3, #0 80146e6: d101 bne.n 80146ec 80146e8: 2301 movs r3, #1 80146ea: e000 b.n 80146ee 80146ec: 2300 movs r3, #0 80146ee: 2b00 cmp r3, #0 80146f0: d10b bne.n 801470a __asm volatile 80146f2: f04f 0350 mov.w r3, #80 @ 0x50 80146f6: f383 8811 msr BASEPRI, r3 80146fa: f3bf 8f6f isb sy 80146fe: f3bf 8f4f dsb sy 8014702: 61fb str r3, [r7, #28] } 8014704: bf00 nop 8014706: bf00 nop 8014708: e7fd b.n 8014706 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 801470a: f001 fc23 bl 8015f54 801470e: 4603 mov r3, r0 8014710: 2b00 cmp r3, #0 8014712: d102 bne.n 801471a 8014714: 687b ldr r3, [r7, #4] 8014716: 2b00 cmp r3, #0 8014718: d101 bne.n 801471e 801471a: 2301 movs r3, #1 801471c: e000 b.n 8014720 801471e: 2300 movs r3, #0 8014720: 2b00 cmp r3, #0 8014722: d10b bne.n 801473c __asm volatile 8014724: f04f 0350 mov.w r3, #80 @ 0x50 8014728: f383 8811 msr BASEPRI, r3 801472c: f3bf 8f6f isb sy 8014730: f3bf 8f4f dsb sy 8014734: 61bb str r3, [r7, #24] } 8014736: bf00 nop 8014738: bf00 nop 801473a: e7fd b.n 8014738 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 801473c: f002 fd8c bl 8017258 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8014740: 6abb ldr r3, [r7, #40] @ 0x28 8014742: 6b9b ldr r3, [r3, #56] @ 0x38 8014744: 627b str r3, [r7, #36] @ 0x24 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 8014746: 6a7b ldr r3, [r7, #36] @ 0x24 8014748: 2b00 cmp r3, #0 801474a: d01f beq.n 801478c { /* Data available, remove one item. */ prvCopyDataFromQueue( pxQueue, pvBuffer ); 801474c: 68b9 ldr r1, [r7, #8] 801474e: 6ab8 ldr r0, [r7, #40] @ 0x28 8014750: f000 faa0 bl 8014c94 traceQUEUE_RECEIVE( pxQueue ); pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 8014754: 6a7b ldr r3, [r7, #36] @ 0x24 8014756: 1e5a subs r2, r3, #1 8014758: 6abb ldr r3, [r7, #40] @ 0x28 801475a: 639a str r2, [r3, #56] @ 0x38 /* There is now space in the queue, were any tasks waiting to post to the queue? If so, unblock the highest priority waiting task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 801475c: 6abb ldr r3, [r7, #40] @ 0x28 801475e: 691b ldr r3, [r3, #16] 8014760: 2b00 cmp r3, #0 8014762: d00f beq.n 8014784 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014764: 6abb ldr r3, [r7, #40] @ 0x28 8014766: 3310 adds r3, #16 8014768: 4618 mov r0, r3 801476a: f001 f9f5 bl 8015b58 801476e: 4603 mov r3, r0 8014770: 2b00 cmp r3, #0 8014772: d007 beq.n 8014784 { queueYIELD_IF_USING_PREEMPTION(); 8014774: 4b3c ldr r3, [pc, #240] @ (8014868 ) 8014776: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801477a: 601a str r2, [r3, #0] 801477c: f3bf 8f4f dsb sy 8014780: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 8014784: f002 fd9a bl 80172bc return pdPASS; 8014788: 2301 movs r3, #1 801478a: e069 b.n 8014860 } else { if( xTicksToWait == ( TickType_t ) 0 ) 801478c: 687b ldr r3, [r7, #4] 801478e: 2b00 cmp r3, #0 8014790: d103 bne.n 801479a { /* The queue was empty and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 8014792: f002 fd93 bl 80172bc traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8014796: 2300 movs r3, #0 8014798: e062 b.n 8014860 } else if( xEntryTimeSet == pdFALSE ) 801479a: 6afb ldr r3, [r7, #44] @ 0x2c 801479c: 2b00 cmp r3, #0 801479e: d106 bne.n 80147ae { /* The queue was empty and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 80147a0: f107 0310 add.w r3, r7, #16 80147a4: 4618 mov r0, r3 80147a6: f001 fa63 bl 8015c70 xEntryTimeSet = pdTRUE; 80147aa: 2301 movs r3, #1 80147ac: 62fb str r3, [r7, #44] @ 0x2c /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 80147ae: f002 fd85 bl 80172bc /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 80147b2: f000 ff95 bl 80156e0 prvLockQueue( pxQueue ); 80147b6: f002 fd4f bl 8017258 80147ba: 6abb ldr r3, [r7, #40] @ 0x28 80147bc: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80147c0: b25b sxtb r3, r3 80147c2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80147c6: d103 bne.n 80147d0 80147c8: 6abb ldr r3, [r7, #40] @ 0x28 80147ca: 2200 movs r2, #0 80147cc: f883 2044 strb.w r2, [r3, #68] @ 0x44 80147d0: 6abb ldr r3, [r7, #40] @ 0x28 80147d2: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80147d6: b25b sxtb r3, r3 80147d8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80147dc: d103 bne.n 80147e6 80147de: 6abb ldr r3, [r7, #40] @ 0x28 80147e0: 2200 movs r2, #0 80147e2: f883 2045 strb.w r2, [r3, #69] @ 0x45 80147e6: f002 fd69 bl 80172bc /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 80147ea: 1d3a adds r2, r7, #4 80147ec: f107 0310 add.w r3, r7, #16 80147f0: 4611 mov r1, r2 80147f2: 4618 mov r0, r3 80147f4: f001 fa52 bl 8015c9c 80147f8: 4603 mov r3, r0 80147fa: 2b00 cmp r3, #0 80147fc: d123 bne.n 8014846 { /* The timeout has not expired. If the queue is still empty place the task on the list of tasks waiting to receive from the queue. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80147fe: 6ab8 ldr r0, [r7, #40] @ 0x28 8014800: f000 fac0 bl 8014d84 8014804: 4603 mov r3, r0 8014806: 2b00 cmp r3, #0 8014808: d017 beq.n 801483a { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 801480a: 6abb ldr r3, [r7, #40] @ 0x28 801480c: 3324 adds r3, #36 @ 0x24 801480e: 687a ldr r2, [r7, #4] 8014810: 4611 mov r1, r2 8014812: 4618 mov r0, r3 8014814: f001 f94e bl 8015ab4 prvUnlockQueue( pxQueue ); 8014818: 6ab8 ldr r0, [r7, #40] @ 0x28 801481a: f000 fa61 bl 8014ce0 if( xTaskResumeAll() == pdFALSE ) 801481e: f000 ff6d bl 80156fc 8014822: 4603 mov r3, r0 8014824: 2b00 cmp r3, #0 8014826: d189 bne.n 801473c { portYIELD_WITHIN_API(); 8014828: 4b0f ldr r3, [pc, #60] @ (8014868 ) 801482a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801482e: 601a str r2, [r3, #0] 8014830: f3bf 8f4f dsb sy 8014834: f3bf 8f6f isb sy 8014838: e780 b.n 801473c } else { /* The queue contains data again. Loop back to try and read the data. */ prvUnlockQueue( pxQueue ); 801483a: 6ab8 ldr r0, [r7, #40] @ 0x28 801483c: f000 fa50 bl 8014ce0 ( void ) xTaskResumeAll(); 8014840: f000 ff5c bl 80156fc 8014844: e77a b.n 801473c } else { /* Timed out. If there is no data in the queue exit, otherwise loop back and attempt to read the data. */ prvUnlockQueue( pxQueue ); 8014846: 6ab8 ldr r0, [r7, #40] @ 0x28 8014848: f000 fa4a bl 8014ce0 ( void ) xTaskResumeAll(); 801484c: f000 ff56 bl 80156fc if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8014850: 6ab8 ldr r0, [r7, #40] @ 0x28 8014852: f000 fa97 bl 8014d84 8014856: 4603 mov r3, r0 8014858: 2b00 cmp r3, #0 801485a: f43f af6f beq.w 801473c { traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 801485e: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 8014860: 4618 mov r0, r3 8014862: 3730 adds r7, #48 @ 0x30 8014864: 46bd mov sp, r7 8014866: bd80 pop {r7, pc} 8014868: e000ed04 .word 0xe000ed04 0801486c : /*-----------------------------------------------------------*/ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) { 801486c: b580 push {r7, lr} 801486e: b08e sub sp, #56 @ 0x38 8014870: af00 add r7, sp, #0 8014872: 6078 str r0, [r7, #4] 8014874: 6039 str r1, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE; 8014876: 2300 movs r3, #0 8014878: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 801487a: 687b ldr r3, [r7, #4] 801487c: 62fb str r3, [r7, #44] @ 0x2c #if( configUSE_MUTEXES == 1 ) BaseType_t xInheritanceOccurred = pdFALSE; 801487e: 2300 movs r3, #0 8014880: 633b str r3, [r7, #48] @ 0x30 #endif /* Check the queue pointer is not NULL. */ configASSERT( ( pxQueue ) ); 8014882: 6afb ldr r3, [r7, #44] @ 0x2c 8014884: 2b00 cmp r3, #0 8014886: d10b bne.n 80148a0 __asm volatile 8014888: f04f 0350 mov.w r3, #80 @ 0x50 801488c: f383 8811 msr BASEPRI, r3 8014890: f3bf 8f6f isb sy 8014894: f3bf 8f4f dsb sy 8014898: 623b str r3, [r7, #32] } 801489a: bf00 nop 801489c: bf00 nop 801489e: e7fd b.n 801489c /* Check this really is a semaphore, in which case the item size will be 0. */ configASSERT( pxQueue->uxItemSize == 0 ); 80148a0: 6afb ldr r3, [r7, #44] @ 0x2c 80148a2: 6c1b ldr r3, [r3, #64] @ 0x40 80148a4: 2b00 cmp r3, #0 80148a6: d00b beq.n 80148c0 __asm volatile 80148a8: f04f 0350 mov.w r3, #80 @ 0x50 80148ac: f383 8811 msr BASEPRI, r3 80148b0: f3bf 8f6f isb sy 80148b4: f3bf 8f4f dsb sy 80148b8: 61fb str r3, [r7, #28] } 80148ba: bf00 nop 80148bc: bf00 nop 80148be: e7fd b.n 80148bc /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 80148c0: f001 fb48 bl 8015f54 80148c4: 4603 mov r3, r0 80148c6: 2b00 cmp r3, #0 80148c8: d102 bne.n 80148d0 80148ca: 683b ldr r3, [r7, #0] 80148cc: 2b00 cmp r3, #0 80148ce: d101 bne.n 80148d4 80148d0: 2301 movs r3, #1 80148d2: e000 b.n 80148d6 80148d4: 2300 movs r3, #0 80148d6: 2b00 cmp r3, #0 80148d8: d10b bne.n 80148f2 __asm volatile 80148da: f04f 0350 mov.w r3, #80 @ 0x50 80148de: f383 8811 msr BASEPRI, r3 80148e2: f3bf 8f6f isb sy 80148e6: f3bf 8f4f dsb sy 80148ea: 61bb str r3, [r7, #24] } 80148ec: bf00 nop 80148ee: bf00 nop 80148f0: e7fd b.n 80148ee /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 80148f2: f002 fcb1 bl 8017258 { /* Semaphores are queues with an item size of 0, and where the number of messages in the queue is the semaphore's count value. */ const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; 80148f6: 6afb ldr r3, [r7, #44] @ 0x2c 80148f8: 6b9b ldr r3, [r3, #56] @ 0x38 80148fa: 62bb str r3, [r7, #40] @ 0x28 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxSemaphoreCount > ( UBaseType_t ) 0 ) 80148fc: 6abb ldr r3, [r7, #40] @ 0x28 80148fe: 2b00 cmp r3, #0 8014900: d024 beq.n 801494c { traceQUEUE_RECEIVE( pxQueue ); /* Semaphores are queues with a data size of zero and where the messages waiting is the semaphore's count. Reduce the count. */ pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; 8014902: 6abb ldr r3, [r7, #40] @ 0x28 8014904: 1e5a subs r2, r3, #1 8014906: 6afb ldr r3, [r7, #44] @ 0x2c 8014908: 639a str r2, [r3, #56] @ 0x38 #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 801490a: 6afb ldr r3, [r7, #44] @ 0x2c 801490c: 681b ldr r3, [r3, #0] 801490e: 2b00 cmp r3, #0 8014910: d104 bne.n 801491c { /* Record the information required to implement priority inheritance should it become necessary. */ pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); 8014912: f001 fc99 bl 8016248 8014916: 4602 mov r2, r0 8014918: 6afb ldr r3, [r7, #44] @ 0x2c 801491a: 609a str r2, [r3, #8] } #endif /* configUSE_MUTEXES */ /* Check to see if other tasks are blocked waiting to give the semaphore, and if so, unblock the highest priority such task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 801491c: 6afb ldr r3, [r7, #44] @ 0x2c 801491e: 691b ldr r3, [r3, #16] 8014920: 2b00 cmp r3, #0 8014922: d00f beq.n 8014944 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014924: 6afb ldr r3, [r7, #44] @ 0x2c 8014926: 3310 adds r3, #16 8014928: 4618 mov r0, r3 801492a: f001 f915 bl 8015b58 801492e: 4603 mov r3, r0 8014930: 2b00 cmp r3, #0 8014932: d007 beq.n 8014944 { queueYIELD_IF_USING_PREEMPTION(); 8014934: 4b54 ldr r3, [pc, #336] @ (8014a88 ) 8014936: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801493a: 601a str r2, [r3, #0] 801493c: f3bf 8f4f dsb sy 8014940: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 8014944: f002 fcba bl 80172bc return pdPASS; 8014948: 2301 movs r3, #1 801494a: e098 b.n 8014a7e } else { if( xTicksToWait == ( TickType_t ) 0 ) 801494c: 683b ldr r3, [r7, #0] 801494e: 2b00 cmp r3, #0 8014950: d112 bne.n 8014978 /* For inheritance to have occurred there must have been an initial timeout, and an adjusted timeout cannot become 0, as if it were 0 the function would have exited. */ #if( configUSE_MUTEXES == 1 ) { configASSERT( xInheritanceOccurred == pdFALSE ); 8014952: 6b3b ldr r3, [r7, #48] @ 0x30 8014954: 2b00 cmp r3, #0 8014956: d00b beq.n 8014970 __asm volatile 8014958: f04f 0350 mov.w r3, #80 @ 0x50 801495c: f383 8811 msr BASEPRI, r3 8014960: f3bf 8f6f isb sy 8014964: f3bf 8f4f dsb sy 8014968: 617b str r3, [r7, #20] } 801496a: bf00 nop 801496c: bf00 nop 801496e: e7fd b.n 801496c } #endif /* configUSE_MUTEXES */ /* The semaphore count was 0 and no block time is specified (or the block time has expired) so exit now. */ taskEXIT_CRITICAL(); 8014970: f002 fca4 bl 80172bc traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8014974: 2300 movs r3, #0 8014976: e082 b.n 8014a7e } else if( xEntryTimeSet == pdFALSE ) 8014978: 6b7b ldr r3, [r7, #52] @ 0x34 801497a: 2b00 cmp r3, #0 801497c: d106 bne.n 801498c { /* The semaphore count was 0 and a block time was specified so configure the timeout structure ready to block. */ vTaskInternalSetTimeOutState( &xTimeOut ); 801497e: f107 030c add.w r3, r7, #12 8014982: 4618 mov r0, r3 8014984: f001 f974 bl 8015c70 xEntryTimeSet = pdTRUE; 8014988: 2301 movs r3, #1 801498a: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 801498c: f002 fc96 bl 80172bc /* Interrupts and other tasks can give to and take from the semaphore now the critical section has been exited. */ vTaskSuspendAll(); 8014990: f000 fea6 bl 80156e0 prvLockQueue( pxQueue ); 8014994: f002 fc60 bl 8017258 8014998: 6afb ldr r3, [r7, #44] @ 0x2c 801499a: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 801499e: b25b sxtb r3, r3 80149a0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80149a4: d103 bne.n 80149ae 80149a6: 6afb ldr r3, [r7, #44] @ 0x2c 80149a8: 2200 movs r2, #0 80149aa: f883 2044 strb.w r2, [r3, #68] @ 0x44 80149ae: 6afb ldr r3, [r7, #44] @ 0x2c 80149b0: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80149b4: b25b sxtb r3, r3 80149b6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80149ba: d103 bne.n 80149c4 80149bc: 6afb ldr r3, [r7, #44] @ 0x2c 80149be: 2200 movs r2, #0 80149c0: f883 2045 strb.w r2, [r3, #69] @ 0x45 80149c4: f002 fc7a bl 80172bc /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 80149c8: 463a mov r2, r7 80149ca: f107 030c add.w r3, r7, #12 80149ce: 4611 mov r1, r2 80149d0: 4618 mov r0, r3 80149d2: f001 f963 bl 8015c9c 80149d6: 4603 mov r3, r0 80149d8: 2b00 cmp r3, #0 80149da: d132 bne.n 8014a42 { /* A block time is specified and not expired. If the semaphore count is 0 then enter the Blocked state to wait for a semaphore to become available. As semaphores are implemented with queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80149dc: 6af8 ldr r0, [r7, #44] @ 0x2c 80149de: f000 f9d1 bl 8014d84 80149e2: 4603 mov r3, r0 80149e4: 2b00 cmp r3, #0 80149e6: d026 beq.n 8014a36 { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 80149e8: 6afb ldr r3, [r7, #44] @ 0x2c 80149ea: 681b ldr r3, [r3, #0] 80149ec: 2b00 cmp r3, #0 80149ee: d109 bne.n 8014a04 { taskENTER_CRITICAL(); 80149f0: f002 fc32 bl 8017258 { xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); 80149f4: 6afb ldr r3, [r7, #44] @ 0x2c 80149f6: 689b ldr r3, [r3, #8] 80149f8: 4618 mov r0, r3 80149fa: f001 fac9 bl 8015f90 80149fe: 6338 str r0, [r7, #48] @ 0x30 } taskEXIT_CRITICAL(); 8014a00: f002 fc5c bl 80172bc mtCOVERAGE_TEST_MARKER(); } } #endif vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 8014a04: 6afb ldr r3, [r7, #44] @ 0x2c 8014a06: 3324 adds r3, #36 @ 0x24 8014a08: 683a ldr r2, [r7, #0] 8014a0a: 4611 mov r1, r2 8014a0c: 4618 mov r0, r3 8014a0e: f001 f851 bl 8015ab4 prvUnlockQueue( pxQueue ); 8014a12: 6af8 ldr r0, [r7, #44] @ 0x2c 8014a14: f000 f964 bl 8014ce0 if( xTaskResumeAll() == pdFALSE ) 8014a18: f000 fe70 bl 80156fc 8014a1c: 4603 mov r3, r0 8014a1e: 2b00 cmp r3, #0 8014a20: f47f af67 bne.w 80148f2 { portYIELD_WITHIN_API(); 8014a24: 4b18 ldr r3, [pc, #96] @ (8014a88 ) 8014a26: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014a2a: 601a str r2, [r3, #0] 8014a2c: f3bf 8f4f dsb sy 8014a30: f3bf 8f6f isb sy 8014a34: e75d b.n 80148f2 } else { /* There was no timeout and the semaphore count was not 0, so attempt to take the semaphore again. */ prvUnlockQueue( pxQueue ); 8014a36: 6af8 ldr r0, [r7, #44] @ 0x2c 8014a38: f000 f952 bl 8014ce0 ( void ) xTaskResumeAll(); 8014a3c: f000 fe5e bl 80156fc 8014a40: e757 b.n 80148f2 } } else { /* Timed out. */ prvUnlockQueue( pxQueue ); 8014a42: 6af8 ldr r0, [r7, #44] @ 0x2c 8014a44: f000 f94c bl 8014ce0 ( void ) xTaskResumeAll(); 8014a48: f000 fe58 bl 80156fc /* If the semaphore count is 0 exit now as the timeout has expired. Otherwise return to attempt to take the semaphore that is known to be available. As semaphores are implemented by queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8014a4c: 6af8 ldr r0, [r7, #44] @ 0x2c 8014a4e: f000 f999 bl 8014d84 8014a52: 4603 mov r3, r0 8014a54: 2b00 cmp r3, #0 8014a56: f43f af4c beq.w 80148f2 #if ( configUSE_MUTEXES == 1 ) { /* xInheritanceOccurred could only have be set if pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to test the mutex type again to check it is actually a mutex. */ if( xInheritanceOccurred != pdFALSE ) 8014a5a: 6b3b ldr r3, [r7, #48] @ 0x30 8014a5c: 2b00 cmp r3, #0 8014a5e: d00d beq.n 8014a7c { taskENTER_CRITICAL(); 8014a60: f002 fbfa bl 8017258 /* This task blocking on the mutex caused another task to inherit this task's priority. Now this task has timed out the priority should be disinherited again, but only as low as the next highest priority task that is waiting for the same mutex. */ uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); 8014a64: 6af8 ldr r0, [r7, #44] @ 0x2c 8014a66: f000 f893 bl 8014b90 8014a6a: 6278 str r0, [r7, #36] @ 0x24 vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); 8014a6c: 6afb ldr r3, [r7, #44] @ 0x2c 8014a6e: 689b ldr r3, [r3, #8] 8014a70: 6a79 ldr r1, [r7, #36] @ 0x24 8014a72: 4618 mov r0, r3 8014a74: f001 fb64 bl 8016140 } taskEXIT_CRITICAL(); 8014a78: f002 fc20 bl 80172bc } } #endif /* configUSE_MUTEXES */ traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8014a7c: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 8014a7e: 4618 mov r0, r3 8014a80: 3738 adds r7, #56 @ 0x38 8014a82: 46bd mov sp, r7 8014a84: bd80 pop {r7, pc} 8014a86: bf00 nop 8014a88: e000ed04 .word 0xe000ed04 08014a8c : } /*lint -restore */ } /*-----------------------------------------------------------*/ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) { 8014a8c: b580 push {r7, lr} 8014a8e: b08e sub sp, #56 @ 0x38 8014a90: af00 add r7, sp, #0 8014a92: 60f8 str r0, [r7, #12] 8014a94: 60b9 str r1, [r7, #8] 8014a96: 607a str r2, [r7, #4] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8014a98: 68fb ldr r3, [r7, #12] 8014a9a: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 8014a9c: 6b3b ldr r3, [r7, #48] @ 0x30 8014a9e: 2b00 cmp r3, #0 8014aa0: d10b bne.n 8014aba __asm volatile 8014aa2: f04f 0350 mov.w r3, #80 @ 0x50 8014aa6: f383 8811 msr BASEPRI, r3 8014aaa: f3bf 8f6f isb sy 8014aae: f3bf 8f4f dsb sy 8014ab2: 623b str r3, [r7, #32] } 8014ab4: bf00 nop 8014ab6: bf00 nop 8014ab8: e7fd b.n 8014ab6 configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8014aba: 68bb ldr r3, [r7, #8] 8014abc: 2b00 cmp r3, #0 8014abe: d103 bne.n 8014ac8 8014ac0: 6b3b ldr r3, [r7, #48] @ 0x30 8014ac2: 6c1b ldr r3, [r3, #64] @ 0x40 8014ac4: 2b00 cmp r3, #0 8014ac6: d101 bne.n 8014acc 8014ac8: 2301 movs r3, #1 8014aca: e000 b.n 8014ace 8014acc: 2300 movs r3, #0 8014ace: 2b00 cmp r3, #0 8014ad0: d10b bne.n 8014aea __asm volatile 8014ad2: f04f 0350 mov.w r3, #80 @ 0x50 8014ad6: f383 8811 msr BASEPRI, r3 8014ada: f3bf 8f6f isb sy 8014ade: f3bf 8f4f dsb sy 8014ae2: 61fb str r3, [r7, #28] } 8014ae4: bf00 nop 8014ae6: bf00 nop 8014ae8: e7fd b.n 8014ae6 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8014aea: f002 fc95 bl 8017418 __asm volatile 8014aee: f3ef 8211 mrs r2, BASEPRI 8014af2: f04f 0350 mov.w r3, #80 @ 0x50 8014af6: f383 8811 msr BASEPRI, r3 8014afa: f3bf 8f6f isb sy 8014afe: f3bf 8f4f dsb sy 8014b02: 61ba str r2, [r7, #24] 8014b04: 617b str r3, [r7, #20] return ulOriginalBASEPRI; 8014b06: 69bb ldr r3, [r7, #24] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8014b08: 62fb str r3, [r7, #44] @ 0x2c { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8014b0a: 6b3b ldr r3, [r7, #48] @ 0x30 8014b0c: 6b9b ldr r3, [r3, #56] @ 0x38 8014b0e: 62bb str r3, [r7, #40] @ 0x28 /* Cannot block in an ISR, so check there is data available. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 8014b10: 6abb ldr r3, [r7, #40] @ 0x28 8014b12: 2b00 cmp r3, #0 8014b14: d02f beq.n 8014b76 { const int8_t cRxLock = pxQueue->cRxLock; 8014b16: 6b3b ldr r3, [r7, #48] @ 0x30 8014b18: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014b1c: f887 3027 strb.w r3, [r7, #39] @ 0x27 traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); prvCopyDataFromQueue( pxQueue, pvBuffer ); 8014b20: 68b9 ldr r1, [r7, #8] 8014b22: 6b38 ldr r0, [r7, #48] @ 0x30 8014b24: f000 f8b6 bl 8014c94 pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 8014b28: 6abb ldr r3, [r7, #40] @ 0x28 8014b2a: 1e5a subs r2, r3, #1 8014b2c: 6b3b ldr r3, [r7, #48] @ 0x30 8014b2e: 639a str r2, [r3, #56] @ 0x38 /* If the queue is locked the event list will not be modified. Instead update the lock count so the task that unlocks the queue will know that an ISR has removed data while the queue was locked. */ if( cRxLock == queueUNLOCKED ) 8014b30: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27 8014b34: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014b38: d112 bne.n 8014b60 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8014b3a: 6b3b ldr r3, [r7, #48] @ 0x30 8014b3c: 691b ldr r3, [r3, #16] 8014b3e: 2b00 cmp r3, #0 8014b40: d016 beq.n 8014b70 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014b42: 6b3b ldr r3, [r7, #48] @ 0x30 8014b44: 3310 adds r3, #16 8014b46: 4618 mov r0, r3 8014b48: f001 f806 bl 8015b58 8014b4c: 4603 mov r3, r0 8014b4e: 2b00 cmp r3, #0 8014b50: d00e beq.n 8014b70 { /* The task waiting has a higher priority than us so force a context switch. */ if( pxHigherPriorityTaskWoken != NULL ) 8014b52: 687b ldr r3, [r7, #4] 8014b54: 2b00 cmp r3, #0 8014b56: d00b beq.n 8014b70 { *pxHigherPriorityTaskWoken = pdTRUE; 8014b58: 687b ldr r3, [r7, #4] 8014b5a: 2201 movs r2, #1 8014b5c: 601a str r2, [r3, #0] 8014b5e: e007 b.n 8014b70 } else { /* Increment the lock count so the task that unlocks the queue knows that data was removed while it was locked. */ pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 ); 8014b60: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8014b64: 3301 adds r3, #1 8014b66: b2db uxtb r3, r3 8014b68: b25a sxtb r2, r3 8014b6a: 6b3b ldr r3, [r7, #48] @ 0x30 8014b6c: f883 2044 strb.w r2, [r3, #68] @ 0x44 } xReturn = pdPASS; 8014b70: 2301 movs r3, #1 8014b72: 637b str r3, [r7, #52] @ 0x34 8014b74: e001 b.n 8014b7a } else { xReturn = pdFAIL; 8014b76: 2300 movs r3, #0 8014b78: 637b str r3, [r7, #52] @ 0x34 8014b7a: 6afb ldr r3, [r7, #44] @ 0x2c 8014b7c: 613b str r3, [r7, #16] __asm volatile 8014b7e: 693b ldr r3, [r7, #16] 8014b80: f383 8811 msr BASEPRI, r3 } 8014b84: bf00 nop traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 8014b86: 6b7b ldr r3, [r7, #52] @ 0x34 } 8014b88: 4618 mov r0, r3 8014b8a: 3738 adds r7, #56 @ 0x38 8014b8c: 46bd mov sp, r7 8014b8e: bd80 pop {r7, pc} 08014b90 : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) { 8014b90: b480 push {r7} 8014b92: b085 sub sp, #20 8014b94: af00 add r7, sp, #0 8014b96: 6078 str r0, [r7, #4] priority, but the waiting task times out, then the holder should disinherit the priority - but only down to the highest priority of any other tasks that are waiting for the same mutex. For this purpose, return the priority of the highest priority task that is waiting for the mutex. */ if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) 8014b98: 687b ldr r3, [r7, #4] 8014b9a: 6a5b ldr r3, [r3, #36] @ 0x24 8014b9c: 2b00 cmp r3, #0 8014b9e: d006 beq.n 8014bae { uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); 8014ba0: 687b ldr r3, [r7, #4] 8014ba2: 6b1b ldr r3, [r3, #48] @ 0x30 8014ba4: 681b ldr r3, [r3, #0] 8014ba6: f1c3 0338 rsb r3, r3, #56 @ 0x38 8014baa: 60fb str r3, [r7, #12] 8014bac: e001 b.n 8014bb2 } else { uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; 8014bae: 2300 movs r3, #0 8014bb0: 60fb str r3, [r7, #12] } return uxHighestPriorityOfWaitingTasks; 8014bb2: 68fb ldr r3, [r7, #12] } 8014bb4: 4618 mov r0, r3 8014bb6: 3714 adds r7, #20 8014bb8: 46bd mov sp, r7 8014bba: f85d 7b04 ldr.w r7, [sp], #4 8014bbe: 4770 bx lr 08014bc0 : #endif /* configUSE_MUTEXES */ /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) { 8014bc0: b580 push {r7, lr} 8014bc2: b086 sub sp, #24 8014bc4: af00 add r7, sp, #0 8014bc6: 60f8 str r0, [r7, #12] 8014bc8: 60b9 str r1, [r7, #8] 8014bca: 607a str r2, [r7, #4] BaseType_t xReturn = pdFALSE; 8014bcc: 2300 movs r3, #0 8014bce: 617b str r3, [r7, #20] UBaseType_t uxMessagesWaiting; /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8014bd0: 68fb ldr r3, [r7, #12] 8014bd2: 6b9b ldr r3, [r3, #56] @ 0x38 8014bd4: 613b str r3, [r7, #16] if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) 8014bd6: 68fb ldr r3, [r7, #12] 8014bd8: 6c1b ldr r3, [r3, #64] @ 0x40 8014bda: 2b00 cmp r3, #0 8014bdc: d10d bne.n 8014bfa { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8014bde: 68fb ldr r3, [r7, #12] 8014be0: 681b ldr r3, [r3, #0] 8014be2: 2b00 cmp r3, #0 8014be4: d14d bne.n 8014c82 { /* The mutex is no longer being held. */ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); 8014be6: 68fb ldr r3, [r7, #12] 8014be8: 689b ldr r3, [r3, #8] 8014bea: 4618 mov r0, r3 8014bec: f001 fa38 bl 8016060 8014bf0: 6178 str r0, [r7, #20] pxQueue->u.xSemaphore.xMutexHolder = NULL; 8014bf2: 68fb ldr r3, [r7, #12] 8014bf4: 2200 movs r2, #0 8014bf6: 609a str r2, [r3, #8] 8014bf8: e043 b.n 8014c82 mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_MUTEXES */ } else if( xPosition == queueSEND_TO_BACK ) 8014bfa: 687b ldr r3, [r7, #4] 8014bfc: 2b00 cmp r3, #0 8014bfe: d119 bne.n 8014c34 { ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 8014c00: 68fb ldr r3, [r7, #12] 8014c02: 6858 ldr r0, [r3, #4] 8014c04: 68fb ldr r3, [r7, #12] 8014c06: 6c1b ldr r3, [r3, #64] @ 0x40 8014c08: 461a mov r2, r3 8014c0a: 68b9 ldr r1, [r7, #8] 8014c0c: f003 f90f bl 8017e2e pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 8014c10: 68fb ldr r3, [r7, #12] 8014c12: 685a ldr r2, [r3, #4] 8014c14: 68fb ldr r3, [r7, #12] 8014c16: 6c1b ldr r3, [r3, #64] @ 0x40 8014c18: 441a add r2, r3 8014c1a: 68fb ldr r3, [r7, #12] 8014c1c: 605a str r2, [r3, #4] if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 8014c1e: 68fb ldr r3, [r7, #12] 8014c20: 685a ldr r2, [r3, #4] 8014c22: 68fb ldr r3, [r7, #12] 8014c24: 689b ldr r3, [r3, #8] 8014c26: 429a cmp r2, r3 8014c28: d32b bcc.n 8014c82 { pxQueue->pcWriteTo = pxQueue->pcHead; 8014c2a: 68fb ldr r3, [r7, #12] 8014c2c: 681a ldr r2, [r3, #0] 8014c2e: 68fb ldr r3, [r7, #12] 8014c30: 605a str r2, [r3, #4] 8014c32: e026 b.n 8014c82 mtCOVERAGE_TEST_MARKER(); } } else { ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ 8014c34: 68fb ldr r3, [r7, #12] 8014c36: 68d8 ldr r0, [r3, #12] 8014c38: 68fb ldr r3, [r7, #12] 8014c3a: 6c1b ldr r3, [r3, #64] @ 0x40 8014c3c: 461a mov r2, r3 8014c3e: 68b9 ldr r1, [r7, #8] 8014c40: f003 f8f5 bl 8017e2e pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; 8014c44: 68fb ldr r3, [r7, #12] 8014c46: 68da ldr r2, [r3, #12] 8014c48: 68fb ldr r3, [r7, #12] 8014c4a: 6c1b ldr r3, [r3, #64] @ 0x40 8014c4c: 425b negs r3, r3 8014c4e: 441a add r2, r3 8014c50: 68fb ldr r3, [r7, #12] 8014c52: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 8014c54: 68fb ldr r3, [r7, #12] 8014c56: 68da ldr r2, [r3, #12] 8014c58: 68fb ldr r3, [r7, #12] 8014c5a: 681b ldr r3, [r3, #0] 8014c5c: 429a cmp r2, r3 8014c5e: d207 bcs.n 8014c70 { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); 8014c60: 68fb ldr r3, [r7, #12] 8014c62: 689a ldr r2, [r3, #8] 8014c64: 68fb ldr r3, [r7, #12] 8014c66: 6c1b ldr r3, [r3, #64] @ 0x40 8014c68: 425b negs r3, r3 8014c6a: 441a add r2, r3 8014c6c: 68fb ldr r3, [r7, #12] 8014c6e: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } if( xPosition == queueOVERWRITE ) 8014c70: 687b ldr r3, [r7, #4] 8014c72: 2b02 cmp r3, #2 8014c74: d105 bne.n 8014c82 { if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 8014c76: 693b ldr r3, [r7, #16] 8014c78: 2b00 cmp r3, #0 8014c7a: d002 beq.n 8014c82 { /* An item is not being added but overwritten, so subtract one from the recorded number of items in the queue so when one is added again below the number of recorded items remains correct. */ --uxMessagesWaiting; 8014c7c: 693b ldr r3, [r7, #16] 8014c7e: 3b01 subs r3, #1 8014c80: 613b str r3, [r7, #16] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 8014c82: 693b ldr r3, [r7, #16] 8014c84: 1c5a adds r2, r3, #1 8014c86: 68fb ldr r3, [r7, #12] 8014c88: 639a str r2, [r3, #56] @ 0x38 return xReturn; 8014c8a: 697b ldr r3, [r7, #20] } 8014c8c: 4618 mov r0, r3 8014c8e: 3718 adds r7, #24 8014c90: 46bd mov sp, r7 8014c92: bd80 pop {r7, pc} 08014c94 : /*-----------------------------------------------------------*/ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) { 8014c94: b580 push {r7, lr} 8014c96: b082 sub sp, #8 8014c98: af00 add r7, sp, #0 8014c9a: 6078 str r0, [r7, #4] 8014c9c: 6039 str r1, [r7, #0] if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) 8014c9e: 687b ldr r3, [r7, #4] 8014ca0: 6c1b ldr r3, [r3, #64] @ 0x40 8014ca2: 2b00 cmp r3, #0 8014ca4: d018 beq.n 8014cd8 { pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 8014ca6: 687b ldr r3, [r7, #4] 8014ca8: 68da ldr r2, [r3, #12] 8014caa: 687b ldr r3, [r7, #4] 8014cac: 6c1b ldr r3, [r3, #64] @ 0x40 8014cae: 441a add r2, r3 8014cb0: 687b ldr r3, [r7, #4] 8014cb2: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 8014cb4: 687b ldr r3, [r7, #4] 8014cb6: 68da ldr r2, [r3, #12] 8014cb8: 687b ldr r3, [r7, #4] 8014cba: 689b ldr r3, [r3, #8] 8014cbc: 429a cmp r2, r3 8014cbe: d303 bcc.n 8014cc8 { pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; 8014cc0: 687b ldr r3, [r7, #4] 8014cc2: 681a ldr r2, [r3, #0] 8014cc4: 687b ldr r3, [r7, #4] 8014cc6: 60da str r2, [r3, #12] } else { mtCOVERAGE_TEST_MARKER(); } ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 8014cc8: 687b ldr r3, [r7, #4] 8014cca: 68d9 ldr r1, [r3, #12] 8014ccc: 687b ldr r3, [r7, #4] 8014cce: 6c1b ldr r3, [r3, #64] @ 0x40 8014cd0: 461a mov r2, r3 8014cd2: 6838 ldr r0, [r7, #0] 8014cd4: f003 f8ab bl 8017e2e } } 8014cd8: bf00 nop 8014cda: 3708 adds r7, #8 8014cdc: 46bd mov sp, r7 8014cde: bd80 pop {r7, pc} 08014ce0 : /*-----------------------------------------------------------*/ static void prvUnlockQueue( Queue_t * const pxQueue ) { 8014ce0: b580 push {r7, lr} 8014ce2: b084 sub sp, #16 8014ce4: af00 add r7, sp, #0 8014ce6: 6078 str r0, [r7, #4] /* The lock counts contains the number of extra data items placed or removed from the queue while the queue was locked. When a queue is locked items can be added or removed, but the event lists cannot be updated. */ taskENTER_CRITICAL(); 8014ce8: f002 fab6 bl 8017258 { int8_t cTxLock = pxQueue->cTxLock; 8014cec: 687b ldr r3, [r7, #4] 8014cee: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014cf2: 73fb strb r3, [r7, #15] /* See if data was added to the queue while it was locked. */ while( cTxLock > queueLOCKED_UNMODIFIED ) 8014cf4: e011 b.n 8014d1a } #else /* configUSE_QUEUE_SETS */ { /* Tasks that are removed from the event list will get added to the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8014cf6: 687b ldr r3, [r7, #4] 8014cf8: 6a5b ldr r3, [r3, #36] @ 0x24 8014cfa: 2b00 cmp r3, #0 8014cfc: d012 beq.n 8014d24 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8014cfe: 687b ldr r3, [r7, #4] 8014d00: 3324 adds r3, #36 @ 0x24 8014d02: 4618 mov r0, r3 8014d04: f000 ff28 bl 8015b58 8014d08: 4603 mov r3, r0 8014d0a: 2b00 cmp r3, #0 8014d0c: d001 beq.n 8014d12 { /* The task waiting has a higher priority so record that a context switch is required. */ vTaskMissedYield(); 8014d0e: f001 f829 bl 8015d64 break; } } #endif /* configUSE_QUEUE_SETS */ --cTxLock; 8014d12: 7bfb ldrb r3, [r7, #15] 8014d14: 3b01 subs r3, #1 8014d16: b2db uxtb r3, r3 8014d18: 73fb strb r3, [r7, #15] while( cTxLock > queueLOCKED_UNMODIFIED ) 8014d1a: f997 300f ldrsb.w r3, [r7, #15] 8014d1e: 2b00 cmp r3, #0 8014d20: dce9 bgt.n 8014cf6 8014d22: e000 b.n 8014d26 break; 8014d24: bf00 nop } pxQueue->cTxLock = queueUNLOCKED; 8014d26: 687b ldr r3, [r7, #4] 8014d28: 22ff movs r2, #255 @ 0xff 8014d2a: f883 2045 strb.w r2, [r3, #69] @ 0x45 } taskEXIT_CRITICAL(); 8014d2e: f002 fac5 bl 80172bc /* Do the same for the Rx lock. */ taskENTER_CRITICAL(); 8014d32: f002 fa91 bl 8017258 { int8_t cRxLock = pxQueue->cRxLock; 8014d36: 687b ldr r3, [r7, #4] 8014d38: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014d3c: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 8014d3e: e011 b.n 8014d64 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8014d40: 687b ldr r3, [r7, #4] 8014d42: 691b ldr r3, [r3, #16] 8014d44: 2b00 cmp r3, #0 8014d46: d012 beq.n 8014d6e { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014d48: 687b ldr r3, [r7, #4] 8014d4a: 3310 adds r3, #16 8014d4c: 4618 mov r0, r3 8014d4e: f000 ff03 bl 8015b58 8014d52: 4603 mov r3, r0 8014d54: 2b00 cmp r3, #0 8014d56: d001 beq.n 8014d5c { vTaskMissedYield(); 8014d58: f001 f804 bl 8015d64 else { mtCOVERAGE_TEST_MARKER(); } --cRxLock; 8014d5c: 7bbb ldrb r3, [r7, #14] 8014d5e: 3b01 subs r3, #1 8014d60: b2db uxtb r3, r3 8014d62: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 8014d64: f997 300e ldrsb.w r3, [r7, #14] 8014d68: 2b00 cmp r3, #0 8014d6a: dce9 bgt.n 8014d40 8014d6c: e000 b.n 8014d70 } else { break; 8014d6e: bf00 nop } } pxQueue->cRxLock = queueUNLOCKED; 8014d70: 687b ldr r3, [r7, #4] 8014d72: 22ff movs r2, #255 @ 0xff 8014d74: f883 2044 strb.w r2, [r3, #68] @ 0x44 } taskEXIT_CRITICAL(); 8014d78: f002 faa0 bl 80172bc } 8014d7c: bf00 nop 8014d7e: 3710 adds r7, #16 8014d80: 46bd mov sp, r7 8014d82: bd80 pop {r7, pc} 08014d84 : /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) { 8014d84: b580 push {r7, lr} 8014d86: b084 sub sp, #16 8014d88: af00 add r7, sp, #0 8014d8a: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8014d8c: f002 fa64 bl 8017258 { if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) 8014d90: 687b ldr r3, [r7, #4] 8014d92: 6b9b ldr r3, [r3, #56] @ 0x38 8014d94: 2b00 cmp r3, #0 8014d96: d102 bne.n 8014d9e { xReturn = pdTRUE; 8014d98: 2301 movs r3, #1 8014d9a: 60fb str r3, [r7, #12] 8014d9c: e001 b.n 8014da2 } else { xReturn = pdFALSE; 8014d9e: 2300 movs r3, #0 8014da0: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8014da2: f002 fa8b bl 80172bc return xReturn; 8014da6: 68fb ldr r3, [r7, #12] } 8014da8: 4618 mov r0, r3 8014daa: 3710 adds r7, #16 8014dac: 46bd mov sp, r7 8014dae: bd80 pop {r7, pc} 08014db0 : return xReturn; } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) { 8014db0: b580 push {r7, lr} 8014db2: b084 sub sp, #16 8014db4: af00 add r7, sp, #0 8014db6: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8014db8: f002 fa4e bl 8017258 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) 8014dbc: 687b ldr r3, [r7, #4] 8014dbe: 6b9a ldr r2, [r3, #56] @ 0x38 8014dc0: 687b ldr r3, [r7, #4] 8014dc2: 6bdb ldr r3, [r3, #60] @ 0x3c 8014dc4: 429a cmp r2, r3 8014dc6: d102 bne.n 8014dce { xReturn = pdTRUE; 8014dc8: 2301 movs r3, #1 8014dca: 60fb str r3, [r7, #12] 8014dcc: e001 b.n 8014dd2 } else { xReturn = pdFALSE; 8014dce: 2300 movs r3, #0 8014dd0: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8014dd2: f002 fa73 bl 80172bc return xReturn; 8014dd6: 68fb ldr r3, [r7, #12] } 8014dd8: 4618 mov r0, r3 8014dda: 3710 adds r7, #16 8014ddc: 46bd mov sp, r7 8014dde: bd80 pop {r7, pc} 08014de0 : /*-----------------------------------------------------------*/ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ { 8014de0: b480 push {r7} 8014de2: b085 sub sp, #20 8014de4: af00 add r7, sp, #0 8014de6: 6078 str r0, [r7, #4] 8014de8: 6039 str r1, [r7, #0] UBaseType_t ux; /* See if there is an empty space in the registry. A NULL name denotes a free slot. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8014dea: 2300 movs r3, #0 8014dec: 60fb str r3, [r7, #12] 8014dee: e014 b.n 8014e1a { if( xQueueRegistry[ ux ].pcQueueName == NULL ) 8014df0: 4a0f ldr r2, [pc, #60] @ (8014e30 ) 8014df2: 68fb ldr r3, [r7, #12] 8014df4: f852 3033 ldr.w r3, [r2, r3, lsl #3] 8014df8: 2b00 cmp r3, #0 8014dfa: d10b bne.n 8014e14 { /* Store the information on this queue. */ xQueueRegistry[ ux ].pcQueueName = pcQueueName; 8014dfc: 490c ldr r1, [pc, #48] @ (8014e30 ) 8014dfe: 68fb ldr r3, [r7, #12] 8014e00: 683a ldr r2, [r7, #0] 8014e02: f841 2033 str.w r2, [r1, r3, lsl #3] xQueueRegistry[ ux ].xHandle = xQueue; 8014e06: 4a0a ldr r2, [pc, #40] @ (8014e30 ) 8014e08: 68fb ldr r3, [r7, #12] 8014e0a: 00db lsls r3, r3, #3 8014e0c: 4413 add r3, r2 8014e0e: 687a ldr r2, [r7, #4] 8014e10: 605a str r2, [r3, #4] traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); break; 8014e12: e006 b.n 8014e22 for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8014e14: 68fb ldr r3, [r7, #12] 8014e16: 3301 adds r3, #1 8014e18: 60fb str r3, [r7, #12] 8014e1a: 68fb ldr r3, [r7, #12] 8014e1c: 2b07 cmp r3, #7 8014e1e: d9e7 bls.n 8014df0 else { mtCOVERAGE_TEST_MARKER(); } } } 8014e20: bf00 nop 8014e22: bf00 nop 8014e24: 3714 adds r7, #20 8014e26: 46bd mov sp, r7 8014e28: f85d 7b04 ldr.w r7, [sp], #4 8014e2c: 4770 bx lr 8014e2e: bf00 nop 8014e30: 240029d4 .word 0x240029d4 08014e34 : /*-----------------------------------------------------------*/ #if ( configUSE_TIMERS == 1 ) void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 8014e34: b580 push {r7, lr} 8014e36: b086 sub sp, #24 8014e38: af00 add r7, sp, #0 8014e3a: 60f8 str r0, [r7, #12] 8014e3c: 60b9 str r1, [r7, #8] 8014e3e: 607a str r2, [r7, #4] Queue_t * const pxQueue = xQueue; 8014e40: 68fb ldr r3, [r7, #12] 8014e42: 617b str r3, [r7, #20] will not actually cause the task to block, just place it on a blocked list. It will not block until the scheduler is unlocked - at which time a yield will be performed. If an item is added to the queue while the queue is locked, and the calling task blocks on the queue, then the calling task will be immediately unblocked when the queue is unlocked. */ prvLockQueue( pxQueue ); 8014e44: f002 fa08 bl 8017258 8014e48: 697b ldr r3, [r7, #20] 8014e4a: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014e4e: b25b sxtb r3, r3 8014e50: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014e54: d103 bne.n 8014e5e 8014e56: 697b ldr r3, [r7, #20] 8014e58: 2200 movs r2, #0 8014e5a: f883 2044 strb.w r2, [r3, #68] @ 0x44 8014e5e: 697b ldr r3, [r7, #20] 8014e60: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014e64: b25b sxtb r3, r3 8014e66: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014e6a: d103 bne.n 8014e74 8014e6c: 697b ldr r3, [r7, #20] 8014e6e: 2200 movs r2, #0 8014e70: f883 2045 strb.w r2, [r3, #69] @ 0x45 8014e74: f002 fa22 bl 80172bc if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) 8014e78: 697b ldr r3, [r7, #20] 8014e7a: 6b9b ldr r3, [r3, #56] @ 0x38 8014e7c: 2b00 cmp r3, #0 8014e7e: d106 bne.n 8014e8e { /* There is nothing in the queue, block for the specified period. */ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); 8014e80: 697b ldr r3, [r7, #20] 8014e82: 3324 adds r3, #36 @ 0x24 8014e84: 687a ldr r2, [r7, #4] 8014e86: 68b9 ldr r1, [r7, #8] 8014e88: 4618 mov r0, r3 8014e8a: f000 fe39 bl 8015b00 } else { mtCOVERAGE_TEST_MARKER(); } prvUnlockQueue( pxQueue ); 8014e8e: 6978 ldr r0, [r7, #20] 8014e90: f7ff ff26 bl 8014ce0 } 8014e94: bf00 nop 8014e96: 3718 adds r7, #24 8014e98: 46bd mov sp, r7 8014e9a: bd80 pop {r7, pc} 08014e9c : return xReturn; } /*-----------------------------------------------------------*/ size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) { 8014e9c: b480 push {r7} 8014e9e: b087 sub sp, #28 8014ea0: af00 add r7, sp, #0 8014ea2: 6078 str r0, [r7, #4] const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 8014ea4: 687b ldr r3, [r7, #4] 8014ea6: 613b str r3, [r7, #16] size_t xSpace; configASSERT( pxStreamBuffer ); 8014ea8: 693b ldr r3, [r7, #16] 8014eaa: 2b00 cmp r3, #0 8014eac: d10b bne.n 8014ec6 __asm volatile 8014eae: f04f 0350 mov.w r3, #80 @ 0x50 8014eb2: f383 8811 msr BASEPRI, r3 8014eb6: f3bf 8f6f isb sy 8014eba: f3bf 8f4f dsb sy 8014ebe: 60fb str r3, [r7, #12] } 8014ec0: bf00 nop 8014ec2: bf00 nop 8014ec4: e7fd b.n 8014ec2 xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; 8014ec6: 693b ldr r3, [r7, #16] 8014ec8: 689a ldr r2, [r3, #8] 8014eca: 693b ldr r3, [r7, #16] 8014ecc: 681b ldr r3, [r3, #0] 8014ece: 4413 add r3, r2 8014ed0: 617b str r3, [r7, #20] xSpace -= pxStreamBuffer->xHead; 8014ed2: 693b ldr r3, [r7, #16] 8014ed4: 685b ldr r3, [r3, #4] 8014ed6: 697a ldr r2, [r7, #20] 8014ed8: 1ad3 subs r3, r2, r3 8014eda: 617b str r3, [r7, #20] xSpace -= ( size_t ) 1; 8014edc: 697b ldr r3, [r7, #20] 8014ede: 3b01 subs r3, #1 8014ee0: 617b str r3, [r7, #20] if( xSpace >= pxStreamBuffer->xLength ) 8014ee2: 693b ldr r3, [r7, #16] 8014ee4: 689b ldr r3, [r3, #8] 8014ee6: 697a ldr r2, [r7, #20] 8014ee8: 429a cmp r2, r3 8014eea: d304 bcc.n 8014ef6 { xSpace -= pxStreamBuffer->xLength; 8014eec: 693b ldr r3, [r7, #16] 8014eee: 689b ldr r3, [r3, #8] 8014ef0: 697a ldr r2, [r7, #20] 8014ef2: 1ad3 subs r3, r2, r3 8014ef4: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xSpace; 8014ef6: 697b ldr r3, [r7, #20] } 8014ef8: 4618 mov r0, r3 8014efa: 371c adds r7, #28 8014efc: 46bd mov sp, r7 8014efe: f85d 7b04 ldr.w r7, [sp], #4 8014f02: 4770 bx lr 08014f04 : size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) { 8014f04: b580 push {r7, lr} 8014f06: b090 sub sp, #64 @ 0x40 8014f08: af02 add r7, sp, #8 8014f0a: 60f8 str r0, [r7, #12] 8014f0c: 60b9 str r1, [r7, #8] 8014f0e: 607a str r2, [r7, #4] 8014f10: 603b str r3, [r7, #0] StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 8014f12: 68fb ldr r3, [r7, #12] 8014f14: 62fb str r3, [r7, #44] @ 0x2c size_t xReturn, xSpace = 0; 8014f16: 2300 movs r3, #0 8014f18: 637b str r3, [r7, #52] @ 0x34 size_t xRequiredSpace = xDataLengthBytes; 8014f1a: 687b ldr r3, [r7, #4] 8014f1c: 633b str r3, [r7, #48] @ 0x30 TimeOut_t xTimeOut; configASSERT( pvTxData ); 8014f1e: 68bb ldr r3, [r7, #8] 8014f20: 2b00 cmp r3, #0 8014f22: d10b bne.n 8014f3c __asm volatile 8014f24: f04f 0350 mov.w r3, #80 @ 0x50 8014f28: f383 8811 msr BASEPRI, r3 8014f2c: f3bf 8f6f isb sy 8014f30: f3bf 8f4f dsb sy 8014f34: 627b str r3, [r7, #36] @ 0x24 } 8014f36: bf00 nop 8014f38: bf00 nop 8014f3a: e7fd b.n 8014f38 configASSERT( pxStreamBuffer ); 8014f3c: 6afb ldr r3, [r7, #44] @ 0x2c 8014f3e: 2b00 cmp r3, #0 8014f40: d10b bne.n 8014f5a __asm volatile 8014f42: f04f 0350 mov.w r3, #80 @ 0x50 8014f46: f383 8811 msr BASEPRI, r3 8014f4a: f3bf 8f6f isb sy 8014f4e: f3bf 8f4f dsb sy 8014f52: 623b str r3, [r7, #32] } 8014f54: bf00 nop 8014f56: bf00 nop 8014f58: e7fd b.n 8014f56 /* This send function is used to write to both message buffers and stream buffers. If this is a message buffer then the space needed must be increased by the amount of bytes needed to store the length of the message. */ if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) 8014f5a: 6afb ldr r3, [r7, #44] @ 0x2c 8014f5c: 7f1b ldrb r3, [r3, #28] 8014f5e: f003 0301 and.w r3, r3, #1 8014f62: 2b00 cmp r3, #0 8014f64: d012 beq.n 8014f8c { xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; 8014f66: 6b3b ldr r3, [r7, #48] @ 0x30 8014f68: 3304 adds r3, #4 8014f6a: 633b str r3, [r7, #48] @ 0x30 /* Overflow? */ configASSERT( xRequiredSpace > xDataLengthBytes ); 8014f6c: 6b3a ldr r2, [r7, #48] @ 0x30 8014f6e: 687b ldr r3, [r7, #4] 8014f70: 429a cmp r2, r3 8014f72: d80b bhi.n 8014f8c __asm volatile 8014f74: f04f 0350 mov.w r3, #80 @ 0x50 8014f78: f383 8811 msr BASEPRI, r3 8014f7c: f3bf 8f6f isb sy 8014f80: f3bf 8f4f dsb sy 8014f84: 61fb str r3, [r7, #28] } 8014f86: bf00 nop 8014f88: bf00 nop 8014f8a: e7fd b.n 8014f88 else { mtCOVERAGE_TEST_MARKER(); } if( xTicksToWait != ( TickType_t ) 0 ) 8014f8c: 683b ldr r3, [r7, #0] 8014f8e: 2b00 cmp r3, #0 8014f90: d03f beq.n 8015012 { vTaskSetTimeOutState( &xTimeOut ); 8014f92: f107 0310 add.w r3, r7, #16 8014f96: 4618 mov r0, r3 8014f98: f000 fe42 bl 8015c20 do { /* Wait until the required number of bytes are free in the message buffer. */ taskENTER_CRITICAL(); 8014f9c: f002 f95c bl 8017258 { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 8014fa0: 6af8 ldr r0, [r7, #44] @ 0x2c 8014fa2: f7ff ff7b bl 8014e9c 8014fa6: 6378 str r0, [r7, #52] @ 0x34 if( xSpace < xRequiredSpace ) 8014fa8: 6b7a ldr r2, [r7, #52] @ 0x34 8014faa: 6b3b ldr r3, [r7, #48] @ 0x30 8014fac: 429a cmp r2, r3 8014fae: d218 bcs.n 8014fe2 { /* Clear notification state as going to wait for space. */ ( void ) xTaskNotifyStateClear( NULL ); 8014fb0: 2000 movs r0, #0 8014fb2: f001 fb65 bl 8016680 /* Should only be one writer. */ configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL ); 8014fb6: 6afb ldr r3, [r7, #44] @ 0x2c 8014fb8: 695b ldr r3, [r3, #20] 8014fba: 2b00 cmp r3, #0 8014fbc: d00b beq.n 8014fd6 __asm volatile 8014fbe: f04f 0350 mov.w r3, #80 @ 0x50 8014fc2: f383 8811 msr BASEPRI, r3 8014fc6: f3bf 8f6f isb sy 8014fca: f3bf 8f4f dsb sy 8014fce: 61bb str r3, [r7, #24] } 8014fd0: bf00 nop 8014fd2: bf00 nop 8014fd4: e7fd b.n 8014fd2 pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle(); 8014fd6: f000 ffad bl 8015f34 8014fda: 4602 mov r2, r0 8014fdc: 6afb ldr r3, [r7, #44] @ 0x2c 8014fde: 615a str r2, [r3, #20] 8014fe0: e002 b.n 8014fe8 } else { taskEXIT_CRITICAL(); 8014fe2: f002 f96b bl 80172bc break; 8014fe6: e014 b.n 8015012 } } taskEXIT_CRITICAL(); 8014fe8: f002 f968 bl 80172bc traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ); ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); 8014fec: 683b ldr r3, [r7, #0] 8014fee: 2200 movs r2, #0 8014ff0: 2100 movs r1, #0 8014ff2: 2000 movs r0, #0 8014ff4: f001 f93c bl 8016270 pxStreamBuffer->xTaskWaitingToSend = NULL; 8014ff8: 6afb ldr r3, [r7, #44] @ 0x2c 8014ffa: 2200 movs r2, #0 8014ffc: 615a str r2, [r3, #20] } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); 8014ffe: 463a mov r2, r7 8015000: f107 0310 add.w r3, r7, #16 8015004: 4611 mov r1, r2 8015006: 4618 mov r0, r3 8015008: f000 fe48 bl 8015c9c 801500c: 4603 mov r3, r0 801500e: 2b00 cmp r3, #0 8015010: d0c4 beq.n 8014f9c else { mtCOVERAGE_TEST_MARKER(); } if( xSpace == ( size_t ) 0 ) 8015012: 6b7b ldr r3, [r7, #52] @ 0x34 8015014: 2b00 cmp r3, #0 8015016: d103 bne.n 8015020 { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 8015018: 6af8 ldr r0, [r7, #44] @ 0x2c 801501a: f7ff ff3f bl 8014e9c 801501e: 6378 str r0, [r7, #52] @ 0x34 else { mtCOVERAGE_TEST_MARKER(); } xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); 8015020: 6b3b ldr r3, [r7, #48] @ 0x30 8015022: 9300 str r3, [sp, #0] 8015024: 6b7b ldr r3, [r7, #52] @ 0x34 8015026: 687a ldr r2, [r7, #4] 8015028: 68b9 ldr r1, [r7, #8] 801502a: 6af8 ldr r0, [r7, #44] @ 0x2c 801502c: f000 f823 bl 8015076 8015030: 62b8 str r0, [r7, #40] @ 0x28 if( xReturn > ( size_t ) 0 ) 8015032: 6abb ldr r3, [r7, #40] @ 0x28 8015034: 2b00 cmp r3, #0 8015036: d019 beq.n 801506c { traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn ); /* Was a task waiting for the data? */ if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) 8015038: 6af8 ldr r0, [r7, #44] @ 0x2c 801503a: f000 f8ce bl 80151da 801503e: 4602 mov r2, r0 8015040: 6afb ldr r3, [r7, #44] @ 0x2c 8015042: 68db ldr r3, [r3, #12] 8015044: 429a cmp r2, r3 8015046: d311 bcc.n 801506c { sbSEND_COMPLETED( pxStreamBuffer ); 8015048: f000 fb4a bl 80156e0 801504c: 6afb ldr r3, [r7, #44] @ 0x2c 801504e: 691b ldr r3, [r3, #16] 8015050: 2b00 cmp r3, #0 8015052: d009 beq.n 8015068 8015054: 6afb ldr r3, [r7, #44] @ 0x2c 8015056: 6918 ldr r0, [r3, #16] 8015058: 2300 movs r3, #0 801505a: 2200 movs r2, #0 801505c: 2100 movs r1, #0 801505e: f001 f967 bl 8016330 8015062: 6afb ldr r3, [r7, #44] @ 0x2c 8015064: 2200 movs r2, #0 8015066: 611a str r2, [r3, #16] 8015068: f000 fb48 bl 80156fc { mtCOVERAGE_TEST_MARKER(); traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ); } return xReturn; 801506c: 6abb ldr r3, [r7, #40] @ 0x28 } 801506e: 4618 mov r0, r3 8015070: 3738 adds r7, #56 @ 0x38 8015072: 46bd mov sp, r7 8015074: bd80 pop {r7, pc} 08015076 : static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, const void * pvTxData, size_t xDataLengthBytes, size_t xSpace, size_t xRequiredSpace ) { 8015076: b580 push {r7, lr} 8015078: b086 sub sp, #24 801507a: af00 add r7, sp, #0 801507c: 60f8 str r0, [r7, #12] 801507e: 60b9 str r1, [r7, #8] 8015080: 607a str r2, [r7, #4] 8015082: 603b str r3, [r7, #0] BaseType_t xShouldWrite; size_t xReturn; if( xSpace == ( size_t ) 0 ) 8015084: 683b ldr r3, [r7, #0] 8015086: 2b00 cmp r3, #0 8015088: d102 bne.n 8015090 { /* Doesn't matter if this is a stream buffer or a message buffer, there is no space to write. */ xShouldWrite = pdFALSE; 801508a: 2300 movs r3, #0 801508c: 617b str r3, [r7, #20] 801508e: e01d b.n 80150cc } else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 ) 8015090: 68fb ldr r3, [r7, #12] 8015092: 7f1b ldrb r3, [r3, #28] 8015094: f003 0301 and.w r3, r3, #1 8015098: 2b00 cmp r3, #0 801509a: d108 bne.n 80150ae { /* This is a stream buffer, as opposed to a message buffer, so writing a stream of bytes rather than discrete messages. Write as many bytes as possible. */ xShouldWrite = pdTRUE; 801509c: 2301 movs r3, #1 801509e: 617b str r3, [r7, #20] xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); 80150a0: 687a ldr r2, [r7, #4] 80150a2: 683b ldr r3, [r7, #0] 80150a4: 4293 cmp r3, r2 80150a6: bf28 it cs 80150a8: 4613 movcs r3, r2 80150aa: 607b str r3, [r7, #4] 80150ac: e00e b.n 80150cc } else if( xSpace >= xRequiredSpace ) 80150ae: 683a ldr r2, [r7, #0] 80150b0: 6a3b ldr r3, [r7, #32] 80150b2: 429a cmp r2, r3 80150b4: d308 bcc.n 80150c8 { /* This is a message buffer, as opposed to a stream buffer, and there is enough space to write both the message length and the message itself into the buffer. Start by writing the length of the data, the data itself will be written later in this function. */ xShouldWrite = pdTRUE; 80150b6: 2301 movs r3, #1 80150b8: 617b str r3, [r7, #20] ( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH ); 80150ba: 1d3b adds r3, r7, #4 80150bc: 2204 movs r2, #4 80150be: 4619 mov r1, r3 80150c0: 68f8 ldr r0, [r7, #12] 80150c2: f000 f815 bl 80150f0 80150c6: e001 b.n 80150cc } else { /* There is space available, but not enough space. */ xShouldWrite = pdFALSE; 80150c8: 2300 movs r3, #0 80150ca: 617b str r3, [r7, #20] } if( xShouldWrite != pdFALSE ) 80150cc: 697b ldr r3, [r7, #20] 80150ce: 2b00 cmp r3, #0 80150d0: d007 beq.n 80150e2 { /* Writes the data itself. */ xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */ 80150d2: 687b ldr r3, [r7, #4] 80150d4: 461a mov r2, r3 80150d6: 68b9 ldr r1, [r7, #8] 80150d8: 68f8 ldr r0, [r7, #12] 80150da: f000 f809 bl 80150f0 80150de: 6138 str r0, [r7, #16] 80150e0: e001 b.n 80150e6 } else { xReturn = 0; 80150e2: 2300 movs r3, #0 80150e4: 613b str r3, [r7, #16] } return xReturn; 80150e6: 693b ldr r3, [r7, #16] } 80150e8: 4618 mov r0, r3 80150ea: 3718 adds r7, #24 80150ec: 46bd mov sp, r7 80150ee: bd80 pop {r7, pc} 080150f0 : return xReturn; } /*-----------------------------------------------------------*/ static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) { 80150f0: b580 push {r7, lr} 80150f2: b08a sub sp, #40 @ 0x28 80150f4: af00 add r7, sp, #0 80150f6: 60f8 str r0, [r7, #12] 80150f8: 60b9 str r1, [r7, #8] 80150fa: 607a str r2, [r7, #4] size_t xNextHead, xFirstLength; configASSERT( xCount > ( size_t ) 0 ); 80150fc: 687b ldr r3, [r7, #4] 80150fe: 2b00 cmp r3, #0 8015100: d10b bne.n 801511a __asm volatile 8015102: f04f 0350 mov.w r3, #80 @ 0x50 8015106: f383 8811 msr BASEPRI, r3 801510a: f3bf 8f6f isb sy 801510e: f3bf 8f4f dsb sy 8015112: 61fb str r3, [r7, #28] } 8015114: bf00 nop 8015116: bf00 nop 8015118: e7fd b.n 8015116 xNextHead = pxStreamBuffer->xHead; 801511a: 68fb ldr r3, [r7, #12] 801511c: 685b ldr r3, [r3, #4] 801511e: 627b str r3, [r7, #36] @ 0x24 /* Calculate the number of bytes that can be added in the first write - which may be less than the total number of bytes that need to be added if the buffer will wrap back to the beginning. */ xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount ); 8015120: 68fb ldr r3, [r7, #12] 8015122: 689a ldr r2, [r3, #8] 8015124: 6a7b ldr r3, [r7, #36] @ 0x24 8015126: 1ad3 subs r3, r2, r3 8015128: 687a ldr r2, [r7, #4] 801512a: 4293 cmp r3, r2 801512c: bf28 it cs 801512e: 4613 movcs r3, r2 8015130: 623b str r3, [r7, #32] /* Write as many bytes as can be written in the first write. */ configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength ); 8015132: 6a7a ldr r2, [r7, #36] @ 0x24 8015134: 6a3b ldr r3, [r7, #32] 8015136: 441a add r2, r3 8015138: 68fb ldr r3, [r7, #12] 801513a: 689b ldr r3, [r3, #8] 801513c: 429a cmp r2, r3 801513e: d90b bls.n 8015158 __asm volatile 8015140: f04f 0350 mov.w r3, #80 @ 0x50 8015144: f383 8811 msr BASEPRI, r3 8015148: f3bf 8f6f isb sy 801514c: f3bf 8f4f dsb sy 8015150: 61bb str r3, [r7, #24] } 8015152: bf00 nop 8015154: bf00 nop 8015156: e7fd b.n 8015154 ( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 8015158: 68fb ldr r3, [r7, #12] 801515a: 699a ldr r2, [r3, #24] 801515c: 6a7b ldr r3, [r7, #36] @ 0x24 801515e: 4413 add r3, r2 8015160: 6a3a ldr r2, [r7, #32] 8015162: 68b9 ldr r1, [r7, #8] 8015164: 4618 mov r0, r3 8015166: f002 fe62 bl 8017e2e /* If the number of bytes written was less than the number that could be written in the first write... */ if( xCount > xFirstLength ) 801516a: 687a ldr r2, [r7, #4] 801516c: 6a3b ldr r3, [r7, #32] 801516e: 429a cmp r2, r3 8015170: d91d bls.n 80151ae { /* ...then write the remaining bytes to the start of the buffer. */ configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength ); 8015172: 687a ldr r2, [r7, #4] 8015174: 6a3b ldr r3, [r7, #32] 8015176: 1ad2 subs r2, r2, r3 8015178: 68fb ldr r3, [r7, #12] 801517a: 689b ldr r3, [r3, #8] 801517c: 429a cmp r2, r3 801517e: d90b bls.n 8015198 __asm volatile 8015180: f04f 0350 mov.w r3, #80 @ 0x50 8015184: f383 8811 msr BASEPRI, r3 8015188: f3bf 8f6f isb sy 801518c: f3bf 8f4f dsb sy 8015190: 617b str r3, [r7, #20] } 8015192: bf00 nop 8015194: bf00 nop 8015196: e7fd b.n 8015194 ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 8015198: 68fb ldr r3, [r7, #12] 801519a: 6998 ldr r0, [r3, #24] 801519c: 68ba ldr r2, [r7, #8] 801519e: 6a3b ldr r3, [r7, #32] 80151a0: 18d1 adds r1, r2, r3 80151a2: 687a ldr r2, [r7, #4] 80151a4: 6a3b ldr r3, [r7, #32] 80151a6: 1ad3 subs r3, r2, r3 80151a8: 461a mov r2, r3 80151aa: f002 fe40 bl 8017e2e else { mtCOVERAGE_TEST_MARKER(); } xNextHead += xCount; 80151ae: 6a7a ldr r2, [r7, #36] @ 0x24 80151b0: 687b ldr r3, [r7, #4] 80151b2: 4413 add r3, r2 80151b4: 627b str r3, [r7, #36] @ 0x24 if( xNextHead >= pxStreamBuffer->xLength ) 80151b6: 68fb ldr r3, [r7, #12] 80151b8: 689b ldr r3, [r3, #8] 80151ba: 6a7a ldr r2, [r7, #36] @ 0x24 80151bc: 429a cmp r2, r3 80151be: d304 bcc.n 80151ca { xNextHead -= pxStreamBuffer->xLength; 80151c0: 68fb ldr r3, [r7, #12] 80151c2: 689b ldr r3, [r3, #8] 80151c4: 6a7a ldr r2, [r7, #36] @ 0x24 80151c6: 1ad3 subs r3, r2, r3 80151c8: 627b str r3, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } pxStreamBuffer->xHead = xNextHead; 80151ca: 68fb ldr r3, [r7, #12] 80151cc: 6a7a ldr r2, [r7, #36] @ 0x24 80151ce: 605a str r2, [r3, #4] return xCount; 80151d0: 687b ldr r3, [r7, #4] } 80151d2: 4618 mov r0, r3 80151d4: 3728 adds r7, #40 @ 0x28 80151d6: 46bd mov sp, r7 80151d8: bd80 pop {r7, pc} 080151da : return xCount; } /*-----------------------------------------------------------*/ static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) { 80151da: b480 push {r7} 80151dc: b085 sub sp, #20 80151de: af00 add r7, sp, #0 80151e0: 6078 str r0, [r7, #4] /* Returns the distance between xTail and xHead. */ size_t xCount; xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead; 80151e2: 687b ldr r3, [r7, #4] 80151e4: 689a ldr r2, [r3, #8] 80151e6: 687b ldr r3, [r7, #4] 80151e8: 685b ldr r3, [r3, #4] 80151ea: 4413 add r3, r2 80151ec: 60fb str r3, [r7, #12] xCount -= pxStreamBuffer->xTail; 80151ee: 687b ldr r3, [r7, #4] 80151f0: 681b ldr r3, [r3, #0] 80151f2: 68fa ldr r2, [r7, #12] 80151f4: 1ad3 subs r3, r2, r3 80151f6: 60fb str r3, [r7, #12] if ( xCount >= pxStreamBuffer->xLength ) 80151f8: 687b ldr r3, [r7, #4] 80151fa: 689b ldr r3, [r3, #8] 80151fc: 68fa ldr r2, [r7, #12] 80151fe: 429a cmp r2, r3 8015200: d304 bcc.n 801520c { xCount -= pxStreamBuffer->xLength; 8015202: 687b ldr r3, [r7, #4] 8015204: 689b ldr r3, [r3, #8] 8015206: 68fa ldr r2, [r7, #12] 8015208: 1ad3 subs r3, r2, r3 801520a: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xCount; 801520c: 68fb ldr r3, [r7, #12] } 801520e: 4618 mov r0, r3 8015210: 3714 adds r7, #20 8015212: 46bd mov sp, r7 8015214: f85d 7b04 ldr.w r7, [sp], #4 8015218: 4770 bx lr 0801521a : const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) { 801521a: b580 push {r7, lr} 801521c: b08e sub sp, #56 @ 0x38 801521e: af04 add r7, sp, #16 8015220: 60f8 str r0, [r7, #12] 8015222: 60b9 str r1, [r7, #8] 8015224: 607a str r2, [r7, #4] 8015226: 603b str r3, [r7, #0] TCB_t *pxNewTCB; TaskHandle_t xReturn; configASSERT( puxStackBuffer != NULL ); 8015228: 6b7b ldr r3, [r7, #52] @ 0x34 801522a: 2b00 cmp r3, #0 801522c: d10b bne.n 8015246 __asm volatile 801522e: f04f 0350 mov.w r3, #80 @ 0x50 8015232: f383 8811 msr BASEPRI, r3 8015236: f3bf 8f6f isb sy 801523a: f3bf 8f4f dsb sy 801523e: 623b str r3, [r7, #32] } 8015240: bf00 nop 8015242: bf00 nop 8015244: e7fd b.n 8015242 configASSERT( pxTaskBuffer != NULL ); 8015246: 6bbb ldr r3, [r7, #56] @ 0x38 8015248: 2b00 cmp r3, #0 801524a: d10b bne.n 8015264 __asm volatile 801524c: f04f 0350 mov.w r3, #80 @ 0x50 8015250: f383 8811 msr BASEPRI, r3 8015254: f3bf 8f6f isb sy 8015258: f3bf 8f4f dsb sy 801525c: 61fb str r3, [r7, #28] } 801525e: bf00 nop 8015260: bf00 nop 8015262: e7fd b.n 8015260 #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTask_t equals the size of the real task structure. */ volatile size_t xSize = sizeof( StaticTask_t ); 8015264: 23a8 movs r3, #168 @ 0xa8 8015266: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( TCB_t ) ); 8015268: 693b ldr r3, [r7, #16] 801526a: 2ba8 cmp r3, #168 @ 0xa8 801526c: d00b beq.n 8015286 __asm volatile 801526e: f04f 0350 mov.w r3, #80 @ 0x50 8015272: f383 8811 msr BASEPRI, r3 8015276: f3bf 8f6f isb sy 801527a: f3bf 8f4f dsb sy 801527e: 61bb str r3, [r7, #24] } 8015280: bf00 nop 8015282: bf00 nop 8015284: e7fd b.n 8015282 ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ 8015286: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) 8015288: 6bbb ldr r3, [r7, #56] @ 0x38 801528a: 2b00 cmp r3, #0 801528c: d01e beq.n 80152cc 801528e: 6b7b ldr r3, [r7, #52] @ 0x34 8015290: 2b00 cmp r3, #0 8015292: d01b beq.n 80152cc { /* The memory used for the task's TCB and stack are passed into this function - use them. */ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8015294: 6bbb ldr r3, [r7, #56] @ 0x38 8015296: 627b str r3, [r7, #36] @ 0x24 pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; 8015298: 6a7b ldr r3, [r7, #36] @ 0x24 801529a: 6b7a ldr r2, [r7, #52] @ 0x34 801529c: 631a str r2, [r3, #48] @ 0x30 #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created statically in case the task is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; 801529e: 6a7b ldr r3, [r7, #36] @ 0x24 80152a0: 2202 movs r2, #2 80152a2: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 80152a6: 2300 movs r3, #0 80152a8: 9303 str r3, [sp, #12] 80152aa: 6a7b ldr r3, [r7, #36] @ 0x24 80152ac: 9302 str r3, [sp, #8] 80152ae: f107 0314 add.w r3, r7, #20 80152b2: 9301 str r3, [sp, #4] 80152b4: 6b3b ldr r3, [r7, #48] @ 0x30 80152b6: 9300 str r3, [sp, #0] 80152b8: 683b ldr r3, [r7, #0] 80152ba: 687a ldr r2, [r7, #4] 80152bc: 68b9 ldr r1, [r7, #8] 80152be: 68f8 ldr r0, [r7, #12] 80152c0: f000 f850 bl 8015364 prvAddNewTaskToReadyList( pxNewTCB ); 80152c4: 6a78 ldr r0, [r7, #36] @ 0x24 80152c6: f000 f8f5 bl 80154b4 80152ca: e001 b.n 80152d0 } else { xReturn = NULL; 80152cc: 2300 movs r3, #0 80152ce: 617b str r3, [r7, #20] } return xReturn; 80152d0: 697b ldr r3, [r7, #20] } 80152d2: 4618 mov r0, r3 80152d4: 3728 adds r7, #40 @ 0x28 80152d6: 46bd mov sp, r7 80152d8: bd80 pop {r7, pc} 080152da : const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const configSTACK_DEPTH_TYPE usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) { 80152da: b580 push {r7, lr} 80152dc: b08c sub sp, #48 @ 0x30 80152de: af04 add r7, sp, #16 80152e0: 60f8 str r0, [r7, #12] 80152e2: 60b9 str r1, [r7, #8] 80152e4: 603b str r3, [r7, #0] 80152e6: 4613 mov r3, r2 80152e8: 80fb strh r3, [r7, #6] #else /* portSTACK_GROWTH */ { StackType_t *pxStack; /* Allocate space for the stack used by the task being created. */ pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ 80152ea: 88fb ldrh r3, [r7, #6] 80152ec: 009b lsls r3, r3, #2 80152ee: 4618 mov r0, r3 80152f0: f002 f8d4 bl 801749c 80152f4: 6178 str r0, [r7, #20] if( pxStack != NULL ) 80152f6: 697b ldr r3, [r7, #20] 80152f8: 2b00 cmp r3, #0 80152fa: d00e beq.n 801531a { /* Allocate space for the TCB. */ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ 80152fc: 20a8 movs r0, #168 @ 0xa8 80152fe: f002 f8cd bl 801749c 8015302: 61f8 str r0, [r7, #28] if( pxNewTCB != NULL ) 8015304: 69fb ldr r3, [r7, #28] 8015306: 2b00 cmp r3, #0 8015308: d003 beq.n 8015312 { /* Store the stack location in the TCB. */ pxNewTCB->pxStack = pxStack; 801530a: 69fb ldr r3, [r7, #28] 801530c: 697a ldr r2, [r7, #20] 801530e: 631a str r2, [r3, #48] @ 0x30 8015310: e005 b.n 801531e } else { /* The stack cannot be used as the TCB was not created. Free it again. */ vPortFree( pxStack ); 8015312: 6978 ldr r0, [r7, #20] 8015314: f002 f990 bl 8017638 8015318: e001 b.n 801531e } } else { pxNewTCB = NULL; 801531a: 2300 movs r3, #0 801531c: 61fb str r3, [r7, #28] } } #endif /* portSTACK_GROWTH */ if( pxNewTCB != NULL ) 801531e: 69fb ldr r3, [r7, #28] 8015320: 2b00 cmp r3, #0 8015322: d017 beq.n 8015354 { #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; 8015324: 69fb ldr r3, [r7, #28] 8015326: 2200 movs r2, #0 8015328: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); 801532c: 88fa ldrh r2, [r7, #6] 801532e: 2300 movs r3, #0 8015330: 9303 str r3, [sp, #12] 8015332: 69fb ldr r3, [r7, #28] 8015334: 9302 str r3, [sp, #8] 8015336: 6afb ldr r3, [r7, #44] @ 0x2c 8015338: 9301 str r3, [sp, #4] 801533a: 6abb ldr r3, [r7, #40] @ 0x28 801533c: 9300 str r3, [sp, #0] 801533e: 683b ldr r3, [r7, #0] 8015340: 68b9 ldr r1, [r7, #8] 8015342: 68f8 ldr r0, [r7, #12] 8015344: f000 f80e bl 8015364 prvAddNewTaskToReadyList( pxNewTCB ); 8015348: 69f8 ldr r0, [r7, #28] 801534a: f000 f8b3 bl 80154b4 xReturn = pdPASS; 801534e: 2301 movs r3, #1 8015350: 61bb str r3, [r7, #24] 8015352: e002 b.n 801535a } else { xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; 8015354: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8015358: 61bb str r3, [r7, #24] } return xReturn; 801535a: 69bb ldr r3, [r7, #24] } 801535c: 4618 mov r0, r3 801535e: 3720 adds r7, #32 8015360: 46bd mov sp, r7 8015362: bd80 pop {r7, pc} 08015364 : void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, TCB_t *pxNewTCB, const MemoryRegion_t * const xRegions ) { 8015364: b580 push {r7, lr} 8015366: b088 sub sp, #32 8015368: af00 add r7, sp, #0 801536a: 60f8 str r0, [r7, #12] 801536c: 60b9 str r1, [r7, #8] 801536e: 607a str r2, [r7, #4] 8015370: 603b str r3, [r7, #0] /* Avoid dependency on memset() if it is not required. */ #if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) { /* Fill the stack with a known value to assist debugging. */ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); 8015372: 6b3b ldr r3, [r7, #48] @ 0x30 8015374: 6b18 ldr r0, [r3, #48] @ 0x30 8015376: 687b ldr r3, [r7, #4] 8015378: 009b lsls r3, r3, #2 801537a: 461a mov r2, r3 801537c: 21a5 movs r1, #165 @ 0xa5 801537e: f002 fc85 bl 8017c8c grows from high memory to low (as per the 80x86) or vice versa. portSTACK_GROWTH is used to make the result positive or negative as required by the port. */ #if( portSTACK_GROWTH < 0 ) { pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); 8015382: 6b3b ldr r3, [r7, #48] @ 0x30 8015384: 6b1a ldr r2, [r3, #48] @ 0x30 8015386: 6879 ldr r1, [r7, #4] 8015388: f06f 4340 mvn.w r3, #3221225472 @ 0xc0000000 801538c: 440b add r3, r1 801538e: 009b lsls r3, r3, #2 8015390: 4413 add r3, r2 8015392: 61bb str r3, [r7, #24] pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ 8015394: 69bb ldr r3, [r7, #24] 8015396: f023 0307 bic.w r3, r3, #7 801539a: 61bb str r3, [r7, #24] /* Check the alignment of the calculated top of stack is correct. */ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); 801539c: 69bb ldr r3, [r7, #24] 801539e: f003 0307 and.w r3, r3, #7 80153a2: 2b00 cmp r3, #0 80153a4: d00b beq.n 80153be __asm volatile 80153a6: f04f 0350 mov.w r3, #80 @ 0x50 80153aa: f383 8811 msr BASEPRI, r3 80153ae: f3bf 8f6f isb sy 80153b2: f3bf 8f4f dsb sy 80153b6: 617b str r3, [r7, #20] } 80153b8: bf00 nop 80153ba: bf00 nop 80153bc: e7fd b.n 80153ba pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); } #endif /* portSTACK_GROWTH */ /* Store the task name in the TCB. */ if( pcName != NULL ) 80153be: 68bb ldr r3, [r7, #8] 80153c0: 2b00 cmp r3, #0 80153c2: d01f beq.n 8015404 { for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 80153c4: 2300 movs r3, #0 80153c6: 61fb str r3, [r7, #28] 80153c8: e012 b.n 80153f0 { pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 80153ca: 68ba ldr r2, [r7, #8] 80153cc: 69fb ldr r3, [r7, #28] 80153ce: 4413 add r3, r2 80153d0: 7819 ldrb r1, [r3, #0] 80153d2: 6b3a ldr r2, [r7, #48] @ 0x30 80153d4: 69fb ldr r3, [r7, #28] 80153d6: 4413 add r3, r2 80153d8: 3334 adds r3, #52 @ 0x34 80153da: 460a mov r2, r1 80153dc: 701a strb r2, [r3, #0] /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than configMAX_TASK_NAME_LEN characters just in case the memory after the string is not accessible (extremely unlikely). */ if( pcName[ x ] == ( char ) 0x00 ) 80153de: 68ba ldr r2, [r7, #8] 80153e0: 69fb ldr r3, [r7, #28] 80153e2: 4413 add r3, r2 80153e4: 781b ldrb r3, [r3, #0] 80153e6: 2b00 cmp r3, #0 80153e8: d006 beq.n 80153f8 for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 80153ea: 69fb ldr r3, [r7, #28] 80153ec: 3301 adds r3, #1 80153ee: 61fb str r3, [r7, #28] 80153f0: 69fb ldr r3, [r7, #28] 80153f2: 2b0f cmp r3, #15 80153f4: d9e9 bls.n 80153ca 80153f6: e000 b.n 80153fa { break; 80153f8: bf00 nop } } /* Ensure the name string is terminated in the case that the string length was greater or equal to configMAX_TASK_NAME_LEN. */ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; 80153fa: 6b3b ldr r3, [r7, #48] @ 0x30 80153fc: 2200 movs r2, #0 80153fe: f883 2043 strb.w r2, [r3, #67] @ 0x43 8015402: e003 b.n 801540c } else { /* The task has not been given a name, so just ensure there is a NULL terminator when it is read out. */ pxNewTCB->pcTaskName[ 0 ] = 0x00; 8015404: 6b3b ldr r3, [r7, #48] @ 0x30 8015406: 2200 movs r2, #0 8015408: f883 2034 strb.w r2, [r3, #52] @ 0x34 } /* This is used as an array index so must ensure it's not too large. First remove the privilege bit if one is present. */ if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) 801540c: 6abb ldr r3, [r7, #40] @ 0x28 801540e: 2b37 cmp r3, #55 @ 0x37 8015410: d901 bls.n 8015416 { uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; 8015412: 2337 movs r3, #55 @ 0x37 8015414: 62bb str r3, [r7, #40] @ 0x28 else { mtCOVERAGE_TEST_MARKER(); } pxNewTCB->uxPriority = uxPriority; 8015416: 6b3b ldr r3, [r7, #48] @ 0x30 8015418: 6aba ldr r2, [r7, #40] @ 0x28 801541a: 62da str r2, [r3, #44] @ 0x2c #if ( configUSE_MUTEXES == 1 ) { pxNewTCB->uxBasePriority = uxPriority; 801541c: 6b3b ldr r3, [r7, #48] @ 0x30 801541e: 6aba ldr r2, [r7, #40] @ 0x28 8015420: 64da str r2, [r3, #76] @ 0x4c pxNewTCB->uxMutexesHeld = 0; 8015422: 6b3b ldr r3, [r7, #48] @ 0x30 8015424: 2200 movs r2, #0 8015426: 651a str r2, [r3, #80] @ 0x50 } #endif /* configUSE_MUTEXES */ vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); 8015428: 6b3b ldr r3, [r7, #48] @ 0x30 801542a: 3304 adds r3, #4 801542c: 4618 mov r0, r3 801542e: f7fe fd09 bl 8013e44 vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); 8015432: 6b3b ldr r3, [r7, #48] @ 0x30 8015434: 3318 adds r3, #24 8015436: 4618 mov r0, r3 8015438: f7fe fd04 bl 8013e44 /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get back to the containing TCB from a generic item in a list. */ listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); 801543c: 6b3b ldr r3, [r7, #48] @ 0x30 801543e: 6b3a ldr r2, [r7, #48] @ 0x30 8015440: 611a str r2, [r3, #16] /* Event lists are always in priority order. */ listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8015442: 6abb ldr r3, [r7, #40] @ 0x28 8015444: f1c3 0238 rsb r2, r3, #56 @ 0x38 8015448: 6b3b ldr r3, [r7, #48] @ 0x30 801544a: 619a str r2, [r3, #24] listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); 801544c: 6b3b ldr r3, [r7, #48] @ 0x30 801544e: 6b3a ldr r2, [r7, #48] @ 0x30 8015450: 625a str r2, [r3, #36] @ 0x24 } #endif #if ( configUSE_TASK_NOTIFICATIONS == 1 ) { pxNewTCB->ulNotifiedValue = 0; 8015452: 6b3b ldr r3, [r7, #48] @ 0x30 8015454: 2200 movs r2, #0 8015456: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 801545a: 6b3b ldr r3, [r7, #48] @ 0x30 801545c: 2200 movs r2, #0 801545e: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 #if ( configUSE_NEWLIB_REENTRANT == 1 ) { /* Initialise this task's Newlib reent structure. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); 8015462: 6b3b ldr r3, [r7, #48] @ 0x30 8015464: 3354 adds r3, #84 @ 0x54 8015466: 224c movs r2, #76 @ 0x4c 8015468: 2100 movs r1, #0 801546a: 4618 mov r0, r3 801546c: f002 fc0e bl 8017c8c 8015470: 6b3b ldr r3, [r7, #48] @ 0x30 8015472: 4a0d ldr r2, [pc, #52] @ (80154a8 ) 8015474: 659a str r2, [r3, #88] @ 0x58 8015476: 6b3b ldr r3, [r7, #48] @ 0x30 8015478: 4a0c ldr r2, [pc, #48] @ (80154ac ) 801547a: 65da str r2, [r3, #92] @ 0x5c 801547c: 6b3b ldr r3, [r7, #48] @ 0x30 801547e: 4a0c ldr r2, [pc, #48] @ (80154b0 ) 8015480: 661a str r2, [r3, #96] @ 0x60 } #endif /* portSTACK_GROWTH */ } #else /* portHAS_STACK_OVERFLOW_CHECKING */ { pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); 8015482: 683a ldr r2, [r7, #0] 8015484: 68f9 ldr r1, [r7, #12] 8015486: 69b8 ldr r0, [r7, #24] 8015488: f001 fdb8 bl 8016ffc 801548c: 4602 mov r2, r0 801548e: 6b3b ldr r3, [r7, #48] @ 0x30 8015490: 601a str r2, [r3, #0] } #endif /* portHAS_STACK_OVERFLOW_CHECKING */ } #endif /* portUSING_MPU_WRAPPERS */ if( pxCreatedTask != NULL ) 8015492: 6afb ldr r3, [r7, #44] @ 0x2c 8015494: 2b00 cmp r3, #0 8015496: d002 beq.n 801549e { /* Pass the handle out in an anonymous way. The handle can be used to change the created task's priority, delete the created task, etc.*/ *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; 8015498: 6afb ldr r3, [r7, #44] @ 0x2c 801549a: 6b3a ldr r2, [r7, #48] @ 0x30 801549c: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 801549e: bf00 nop 80154a0: 3720 adds r7, #32 80154a2: 46bd mov sp, r7 80154a4: bd80 pop {r7, pc} 80154a6: bf00 nop 80154a8: 24013068 .word 0x24013068 80154ac: 240130d0 .word 0x240130d0 80154b0: 24013138 .word 0x24013138 080154b4 : /*-----------------------------------------------------------*/ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) { 80154b4: b580 push {r7, lr} 80154b6: b082 sub sp, #8 80154b8: af00 add r7, sp, #0 80154ba: 6078 str r0, [r7, #4] /* Ensure interrupts don't access the task lists while the lists are being updated. */ taskENTER_CRITICAL(); 80154bc: f001 fecc bl 8017258 { uxCurrentNumberOfTasks++; 80154c0: 4b2d ldr r3, [pc, #180] @ (8015578 ) 80154c2: 681b ldr r3, [r3, #0] 80154c4: 3301 adds r3, #1 80154c6: 4a2c ldr r2, [pc, #176] @ (8015578 ) 80154c8: 6013 str r3, [r2, #0] if( pxCurrentTCB == NULL ) 80154ca: 4b2c ldr r3, [pc, #176] @ (801557c ) 80154cc: 681b ldr r3, [r3, #0] 80154ce: 2b00 cmp r3, #0 80154d0: d109 bne.n 80154e6 { /* There are no other tasks, or all the other tasks are in the suspended state - make this the current task. */ pxCurrentTCB = pxNewTCB; 80154d2: 4a2a ldr r2, [pc, #168] @ (801557c ) 80154d4: 687b ldr r3, [r7, #4] 80154d6: 6013 str r3, [r2, #0] if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) 80154d8: 4b27 ldr r3, [pc, #156] @ (8015578 ) 80154da: 681b ldr r3, [r3, #0] 80154dc: 2b01 cmp r3, #1 80154de: d110 bne.n 8015502 { /* This is the first task to be created so do the preliminary initialisation required. We will not recover if this call fails, but we will report the failure. */ prvInitialiseTaskLists(); 80154e0: f000 fc64 bl 8015dac 80154e4: e00d b.n 8015502 else { /* If the scheduler is not already running, make this task the current task if it is the highest priority task to be created so far. */ if( xSchedulerRunning == pdFALSE ) 80154e6: 4b26 ldr r3, [pc, #152] @ (8015580 ) 80154e8: 681b ldr r3, [r3, #0] 80154ea: 2b00 cmp r3, #0 80154ec: d109 bne.n 8015502 { if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) 80154ee: 4b23 ldr r3, [pc, #140] @ (801557c ) 80154f0: 681b ldr r3, [r3, #0] 80154f2: 6ada ldr r2, [r3, #44] @ 0x2c 80154f4: 687b ldr r3, [r7, #4] 80154f6: 6adb ldr r3, [r3, #44] @ 0x2c 80154f8: 429a cmp r2, r3 80154fa: d802 bhi.n 8015502 { pxCurrentTCB = pxNewTCB; 80154fc: 4a1f ldr r2, [pc, #124] @ (801557c ) 80154fe: 687b ldr r3, [r7, #4] 8015500: 6013 str r3, [r2, #0] { mtCOVERAGE_TEST_MARKER(); } } uxTaskNumber++; 8015502: 4b20 ldr r3, [pc, #128] @ (8015584 ) 8015504: 681b ldr r3, [r3, #0] 8015506: 3301 adds r3, #1 8015508: 4a1e ldr r2, [pc, #120] @ (8015584 ) 801550a: 6013 str r3, [r2, #0] #if ( configUSE_TRACE_FACILITY == 1 ) { /* Add a counter into the TCB for tracing only. */ pxNewTCB->uxTCBNumber = uxTaskNumber; 801550c: 4b1d ldr r3, [pc, #116] @ (8015584 ) 801550e: 681a ldr r2, [r3, #0] 8015510: 687b ldr r3, [r7, #4] 8015512: 645a str r2, [r3, #68] @ 0x44 } #endif /* configUSE_TRACE_FACILITY */ traceTASK_CREATE( pxNewTCB ); prvAddTaskToReadyList( pxNewTCB ); 8015514: 687b ldr r3, [r7, #4] 8015516: 6ada ldr r2, [r3, #44] @ 0x2c 8015518: 4b1b ldr r3, [pc, #108] @ (8015588 ) 801551a: 681b ldr r3, [r3, #0] 801551c: 429a cmp r2, r3 801551e: d903 bls.n 8015528 8015520: 687b ldr r3, [r7, #4] 8015522: 6adb ldr r3, [r3, #44] @ 0x2c 8015524: 4a18 ldr r2, [pc, #96] @ (8015588 ) 8015526: 6013 str r3, [r2, #0] 8015528: 687b ldr r3, [r7, #4] 801552a: 6ada ldr r2, [r3, #44] @ 0x2c 801552c: 4613 mov r3, r2 801552e: 009b lsls r3, r3, #2 8015530: 4413 add r3, r2 8015532: 009b lsls r3, r3, #2 8015534: 4a15 ldr r2, [pc, #84] @ (801558c ) 8015536: 441a add r2, r3 8015538: 687b ldr r3, [r7, #4] 801553a: 3304 adds r3, #4 801553c: 4619 mov r1, r3 801553e: 4610 mov r0, r2 8015540: f7fe fc8d bl 8013e5e portSETUP_TCB( pxNewTCB ); } taskEXIT_CRITICAL(); 8015544: f001 feba bl 80172bc if( xSchedulerRunning != pdFALSE ) 8015548: 4b0d ldr r3, [pc, #52] @ (8015580 ) 801554a: 681b ldr r3, [r3, #0] 801554c: 2b00 cmp r3, #0 801554e: d00e beq.n 801556e { /* If the created task is of a higher priority than the current task then it should run now. */ if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) 8015550: 4b0a ldr r3, [pc, #40] @ (801557c ) 8015552: 681b ldr r3, [r3, #0] 8015554: 6ada ldr r2, [r3, #44] @ 0x2c 8015556: 687b ldr r3, [r7, #4] 8015558: 6adb ldr r3, [r3, #44] @ 0x2c 801555a: 429a cmp r2, r3 801555c: d207 bcs.n 801556e { taskYIELD_IF_USING_PREEMPTION(); 801555e: 4b0c ldr r3, [pc, #48] @ (8015590 ) 8015560: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015564: 601a str r2, [r3, #0] 8015566: f3bf 8f4f dsb sy 801556a: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 801556e: bf00 nop 8015570: 3708 adds r7, #8 8015572: 46bd mov sp, r7 8015574: bd80 pop {r7, pc} 8015576: bf00 nop 8015578: 24002ee8 .word 0x24002ee8 801557c: 24002a14 .word 0x24002a14 8015580: 24002ef4 .word 0x24002ef4 8015584: 24002f04 .word 0x24002f04 8015588: 24002ef0 .word 0x24002ef0 801558c: 24002a18 .word 0x24002a18 8015590: e000ed04 .word 0xe000ed04 08015594 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelay == 1 ) void vTaskDelay( const TickType_t xTicksToDelay ) { 8015594: b580 push {r7, lr} 8015596: b084 sub sp, #16 8015598: af00 add r7, sp, #0 801559a: 6078 str r0, [r7, #4] BaseType_t xAlreadyYielded = pdFALSE; 801559c: 2300 movs r3, #0 801559e: 60fb str r3, [r7, #12] /* A delay time of zero just forces a reschedule. */ if( xTicksToDelay > ( TickType_t ) 0U ) 80155a0: 687b ldr r3, [r7, #4] 80155a2: 2b00 cmp r3, #0 80155a4: d018 beq.n 80155d8 { configASSERT( uxSchedulerSuspended == 0 ); 80155a6: 4b14 ldr r3, [pc, #80] @ (80155f8 ) 80155a8: 681b ldr r3, [r3, #0] 80155aa: 2b00 cmp r3, #0 80155ac: d00b beq.n 80155c6 __asm volatile 80155ae: f04f 0350 mov.w r3, #80 @ 0x50 80155b2: f383 8811 msr BASEPRI, r3 80155b6: f3bf 8f6f isb sy 80155ba: f3bf 8f4f dsb sy 80155be: 60bb str r3, [r7, #8] } 80155c0: bf00 nop 80155c2: bf00 nop 80155c4: e7fd b.n 80155c2 vTaskSuspendAll(); 80155c6: f000 f88b bl 80156e0 list or removed from the blocked list until the scheduler is resumed. This task cannot be in an event list as it is the currently executing task. */ prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); 80155ca: 2100 movs r1, #0 80155cc: 6878 ldr r0, [r7, #4] 80155ce: f001 f87d bl 80166cc } xAlreadyYielded = xTaskResumeAll(); 80155d2: f000 f893 bl 80156fc 80155d6: 60f8 str r0, [r7, #12] mtCOVERAGE_TEST_MARKER(); } /* Force a reschedule if xTaskResumeAll has not already done so, we may have put ourselves to sleep. */ if( xAlreadyYielded == pdFALSE ) 80155d8: 68fb ldr r3, [r7, #12] 80155da: 2b00 cmp r3, #0 80155dc: d107 bne.n 80155ee { portYIELD_WITHIN_API(); 80155de: 4b07 ldr r3, [pc, #28] @ (80155fc ) 80155e0: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80155e4: 601a str r2, [r3, #0] 80155e6: f3bf 8f4f dsb sy 80155ea: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 80155ee: bf00 nop 80155f0: 3710 adds r7, #16 80155f2: 46bd mov sp, r7 80155f4: bd80 pop {r7, pc} 80155f6: bf00 nop 80155f8: 24002f10 .word 0x24002f10 80155fc: e000ed04 .word 0xe000ed04 08015600 : #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ /*-----------------------------------------------------------*/ void vTaskStartScheduler( void ) { 8015600: b580 push {r7, lr} 8015602: b08a sub sp, #40 @ 0x28 8015604: af04 add r7, sp, #16 BaseType_t xReturn; /* Add the idle task at the lowest priority. */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxIdleTaskTCBBuffer = NULL; 8015606: 2300 movs r3, #0 8015608: 60bb str r3, [r7, #8] StackType_t *pxIdleTaskStackBuffer = NULL; 801560a: 2300 movs r3, #0 801560c: 607b str r3, [r7, #4] uint32_t ulIdleTaskStackSize; /* The Idle task is created using user provided RAM - obtain the address of the RAM then create the idle task. */ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); 801560e: 463a mov r2, r7 8015610: 1d39 adds r1, r7, #4 8015612: f107 0308 add.w r3, r7, #8 8015616: 4618 mov r0, r3 8015618: f7fe fbc0 bl 8013d9c xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, 801561c: 6839 ldr r1, [r7, #0] 801561e: 687b ldr r3, [r7, #4] 8015620: 68ba ldr r2, [r7, #8] 8015622: 9202 str r2, [sp, #8] 8015624: 9301 str r3, [sp, #4] 8015626: 2300 movs r3, #0 8015628: 9300 str r3, [sp, #0] 801562a: 2300 movs r3, #0 801562c: 460a mov r2, r1 801562e: 4924 ldr r1, [pc, #144] @ (80156c0 ) 8015630: 4824 ldr r0, [pc, #144] @ (80156c4 ) 8015632: f7ff fdf2 bl 801521a 8015636: 4603 mov r3, r0 8015638: 4a23 ldr r2, [pc, #140] @ (80156c8 ) 801563a: 6013 str r3, [r2, #0] ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ pxIdleTaskStackBuffer, pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ if( xIdleTaskHandle != NULL ) 801563c: 4b22 ldr r3, [pc, #136] @ (80156c8 ) 801563e: 681b ldr r3, [r3, #0] 8015640: 2b00 cmp r3, #0 8015642: d002 beq.n 801564a { xReturn = pdPASS; 8015644: 2301 movs r3, #1 8015646: 617b str r3, [r7, #20] 8015648: e001 b.n 801564e } else { xReturn = pdFAIL; 801564a: 2300 movs r3, #0 801564c: 617b str r3, [r7, #20] } #endif /* configSUPPORT_STATIC_ALLOCATION */ #if ( configUSE_TIMERS == 1 ) { if( xReturn == pdPASS ) 801564e: 697b ldr r3, [r7, #20] 8015650: 2b01 cmp r3, #1 8015652: d102 bne.n 801565a { xReturn = xTimerCreateTimerTask(); 8015654: f001 f88e bl 8016774 8015658: 6178 str r0, [r7, #20] mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_TIMERS */ if( xReturn == pdPASS ) 801565a: 697b ldr r3, [r7, #20] 801565c: 2b01 cmp r3, #1 801565e: d11b bne.n 8015698 __asm volatile 8015660: f04f 0350 mov.w r3, #80 @ 0x50 8015664: f383 8811 msr BASEPRI, r3 8015668: f3bf 8f6f isb sy 801566c: f3bf 8f4f dsb sy 8015670: 613b str r3, [r7, #16] } 8015672: bf00 nop { /* Switch Newlib's _impure_ptr variable to point to the _reent structure specific to the task that will run first. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 8015674: 4b15 ldr r3, [pc, #84] @ (80156cc ) 8015676: 681b ldr r3, [r3, #0] 8015678: 3354 adds r3, #84 @ 0x54 801567a: 4a15 ldr r2, [pc, #84] @ (80156d0 ) 801567c: 6013 str r3, [r2, #0] } #endif /* configUSE_NEWLIB_REENTRANT */ xNextTaskUnblockTime = portMAX_DELAY; 801567e: 4b15 ldr r3, [pc, #84] @ (80156d4 ) 8015680: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8015684: 601a str r2, [r3, #0] xSchedulerRunning = pdTRUE; 8015686: 4b14 ldr r3, [pc, #80] @ (80156d8 ) 8015688: 2201 movs r2, #1 801568a: 601a str r2, [r3, #0] xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; 801568c: 4b13 ldr r3, [pc, #76] @ (80156dc ) 801568e: 2200 movs r2, #0 8015690: 601a str r2, [r3, #0] traceTASK_SWITCHED_IN(); /* Setting up the timer tick is hardware specific and thus in the portable interface. */ if( xPortStartScheduler() != pdFALSE ) 8015692: f001 fd3d bl 8017110 } /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, meaning xIdleTaskHandle is not used anywhere else. */ ( void ) xIdleTaskHandle; } 8015696: e00f b.n 80156b8 configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); 8015698: 697b ldr r3, [r7, #20] 801569a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801569e: d10b bne.n 80156b8 __asm volatile 80156a0: f04f 0350 mov.w r3, #80 @ 0x50 80156a4: f383 8811 msr BASEPRI, r3 80156a8: f3bf 8f6f isb sy 80156ac: f3bf 8f4f dsb sy 80156b0: 60fb str r3, [r7, #12] } 80156b2: bf00 nop 80156b4: bf00 nop 80156b6: e7fd b.n 80156b4 } 80156b8: bf00 nop 80156ba: 3718 adds r7, #24 80156bc: 46bd mov sp, r7 80156be: bd80 pop {r7, pc} 80156c0: 08018ae0 .word 0x08018ae0 80156c4: 08015d7d .word 0x08015d7d 80156c8: 24002f0c .word 0x24002f0c 80156cc: 24002a14 .word 0x24002a14 80156d0: 24000054 .word 0x24000054 80156d4: 24002f08 .word 0x24002f08 80156d8: 24002ef4 .word 0x24002ef4 80156dc: 24002eec .word 0x24002eec 080156e0 : vPortEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { 80156e0: b480 push {r7} 80156e2: af00 add r7, sp, #0 do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER(); /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; 80156e4: 4b04 ldr r3, [pc, #16] @ (80156f8 ) 80156e6: 681b ldr r3, [r3, #0] 80156e8: 3301 adds r3, #1 80156ea: 4a03 ldr r2, [pc, #12] @ (80156f8 ) 80156ec: 6013 str r3, [r2, #0] /* Enforces ordering for ports and optimised compilers that may otherwise place the above increment elsewhere. */ portMEMORY_BARRIER(); } 80156ee: bf00 nop 80156f0: 46bd mov sp, r7 80156f2: f85d 7b04 ldr.w r7, [sp], #4 80156f6: 4770 bx lr 80156f8: 24002f10 .word 0x24002f10 080156fc : #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ BaseType_t xTaskResumeAll( void ) { 80156fc: b580 push {r7, lr} 80156fe: b084 sub sp, #16 8015700: af00 add r7, sp, #0 TCB_t *pxTCB = NULL; 8015702: 2300 movs r3, #0 8015704: 60fb str r3, [r7, #12] BaseType_t xAlreadyYielded = pdFALSE; 8015706: 2300 movs r3, #0 8015708: 60bb str r3, [r7, #8] /* If uxSchedulerSuspended is zero then this function does not match a previous call to vTaskSuspendAll(). */ configASSERT( uxSchedulerSuspended ); 801570a: 4b42 ldr r3, [pc, #264] @ (8015814 ) 801570c: 681b ldr r3, [r3, #0] 801570e: 2b00 cmp r3, #0 8015710: d10b bne.n 801572a __asm volatile 8015712: f04f 0350 mov.w r3, #80 @ 0x50 8015716: f383 8811 msr BASEPRI, r3 801571a: f3bf 8f6f isb sy 801571e: f3bf 8f4f dsb sy 8015722: 603b str r3, [r7, #0] } 8015724: bf00 nop 8015726: bf00 nop 8015728: e7fd b.n 8015726 /* It is possible that an ISR caused a task to be removed from an event list while the scheduler was suspended. If this was the case then the removed task will have been added to the xPendingReadyList. Once the scheduler has been resumed it is safe to move all the pending ready tasks from this list into their appropriate ready list. */ taskENTER_CRITICAL(); 801572a: f001 fd95 bl 8017258 { --uxSchedulerSuspended; 801572e: 4b39 ldr r3, [pc, #228] @ (8015814 ) 8015730: 681b ldr r3, [r3, #0] 8015732: 3b01 subs r3, #1 8015734: 4a37 ldr r2, [pc, #220] @ (8015814 ) 8015736: 6013 str r3, [r2, #0] if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8015738: 4b36 ldr r3, [pc, #216] @ (8015814 ) 801573a: 681b ldr r3, [r3, #0] 801573c: 2b00 cmp r3, #0 801573e: d162 bne.n 8015806 { if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) 8015740: 4b35 ldr r3, [pc, #212] @ (8015818 ) 8015742: 681b ldr r3, [r3, #0] 8015744: 2b00 cmp r3, #0 8015746: d05e beq.n 8015806 { /* Move any readied tasks from the pending list into the appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 8015748: e02f b.n 80157aa { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 801574a: 4b34 ldr r3, [pc, #208] @ (801581c ) 801574c: 68db ldr r3, [r3, #12] 801574e: 68db ldr r3, [r3, #12] 8015750: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 8015752: 68fb ldr r3, [r7, #12] 8015754: 3318 adds r3, #24 8015756: 4618 mov r0, r3 8015758: f7fe fbde bl 8013f18 ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 801575c: 68fb ldr r3, [r7, #12] 801575e: 3304 adds r3, #4 8015760: 4618 mov r0, r3 8015762: f7fe fbd9 bl 8013f18 prvAddTaskToReadyList( pxTCB ); 8015766: 68fb ldr r3, [r7, #12] 8015768: 6ada ldr r2, [r3, #44] @ 0x2c 801576a: 4b2d ldr r3, [pc, #180] @ (8015820 ) 801576c: 681b ldr r3, [r3, #0] 801576e: 429a cmp r2, r3 8015770: d903 bls.n 801577a 8015772: 68fb ldr r3, [r7, #12] 8015774: 6adb ldr r3, [r3, #44] @ 0x2c 8015776: 4a2a ldr r2, [pc, #168] @ (8015820 ) 8015778: 6013 str r3, [r2, #0] 801577a: 68fb ldr r3, [r7, #12] 801577c: 6ada ldr r2, [r3, #44] @ 0x2c 801577e: 4613 mov r3, r2 8015780: 009b lsls r3, r3, #2 8015782: 4413 add r3, r2 8015784: 009b lsls r3, r3, #2 8015786: 4a27 ldr r2, [pc, #156] @ (8015824 ) 8015788: 441a add r2, r3 801578a: 68fb ldr r3, [r7, #12] 801578c: 3304 adds r3, #4 801578e: 4619 mov r1, r3 8015790: 4610 mov r0, r2 8015792: f7fe fb64 bl 8013e5e /* If the moved task has a priority higher than the current task then a yield must be performed. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 8015796: 68fb ldr r3, [r7, #12] 8015798: 6ada ldr r2, [r3, #44] @ 0x2c 801579a: 4b23 ldr r3, [pc, #140] @ (8015828 ) 801579c: 681b ldr r3, [r3, #0] 801579e: 6adb ldr r3, [r3, #44] @ 0x2c 80157a0: 429a cmp r2, r3 80157a2: d302 bcc.n 80157aa { xYieldPending = pdTRUE; 80157a4: 4b21 ldr r3, [pc, #132] @ (801582c ) 80157a6: 2201 movs r2, #1 80157a8: 601a str r2, [r3, #0] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 80157aa: 4b1c ldr r3, [pc, #112] @ (801581c ) 80157ac: 681b ldr r3, [r3, #0] 80157ae: 2b00 cmp r3, #0 80157b0: d1cb bne.n 801574a { mtCOVERAGE_TEST_MARKER(); } } if( pxTCB != NULL ) 80157b2: 68fb ldr r3, [r7, #12] 80157b4: 2b00 cmp r3, #0 80157b6: d001 beq.n 80157bc which may have prevented the next unblock time from being re-calculated, in which case re-calculate it now. Mainly important for low power tickless implementations, where this can prevent an unnecessary exit from low power state. */ prvResetNextTaskUnblockTime(); 80157b8: f000 fb9c bl 8015ef4 /* If any ticks occurred while the scheduler was suspended then they should be processed now. This ensures the tick count does not slip, and that any delayed tasks are resumed at the correct time. */ { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ 80157bc: 4b1c ldr r3, [pc, #112] @ (8015830 ) 80157be: 681b ldr r3, [r3, #0] 80157c0: 607b str r3, [r7, #4] if( xPendedCounts > ( TickType_t ) 0U ) 80157c2: 687b ldr r3, [r7, #4] 80157c4: 2b00 cmp r3, #0 80157c6: d010 beq.n 80157ea { do { if( xTaskIncrementTick() != pdFALSE ) 80157c8: f000 f846 bl 8015858 80157cc: 4603 mov r3, r0 80157ce: 2b00 cmp r3, #0 80157d0: d002 beq.n 80157d8 { xYieldPending = pdTRUE; 80157d2: 4b16 ldr r3, [pc, #88] @ (801582c ) 80157d4: 2201 movs r2, #1 80157d6: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } --xPendedCounts; 80157d8: 687b ldr r3, [r7, #4] 80157da: 3b01 subs r3, #1 80157dc: 607b str r3, [r7, #4] } while( xPendedCounts > ( TickType_t ) 0U ); 80157de: 687b ldr r3, [r7, #4] 80157e0: 2b00 cmp r3, #0 80157e2: d1f1 bne.n 80157c8 xPendedTicks = 0; 80157e4: 4b12 ldr r3, [pc, #72] @ (8015830 ) 80157e6: 2200 movs r2, #0 80157e8: 601a str r2, [r3, #0] { mtCOVERAGE_TEST_MARKER(); } } if( xYieldPending != pdFALSE ) 80157ea: 4b10 ldr r3, [pc, #64] @ (801582c ) 80157ec: 681b ldr r3, [r3, #0] 80157ee: 2b00 cmp r3, #0 80157f0: d009 beq.n 8015806 { #if( configUSE_PREEMPTION != 0 ) { xAlreadyYielded = pdTRUE; 80157f2: 2301 movs r3, #1 80157f4: 60bb str r3, [r7, #8] } #endif taskYIELD_IF_USING_PREEMPTION(); 80157f6: 4b0f ldr r3, [pc, #60] @ (8015834 ) 80157f8: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80157fc: 601a str r2, [r3, #0] 80157fe: f3bf 8f4f dsb sy 8015802: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8015806: f001 fd59 bl 80172bc return xAlreadyYielded; 801580a: 68bb ldr r3, [r7, #8] } 801580c: 4618 mov r0, r3 801580e: 3710 adds r7, #16 8015810: 46bd mov sp, r7 8015812: bd80 pop {r7, pc} 8015814: 24002f10 .word 0x24002f10 8015818: 24002ee8 .word 0x24002ee8 801581c: 24002ea8 .word 0x24002ea8 8015820: 24002ef0 .word 0x24002ef0 8015824: 24002a18 .word 0x24002a18 8015828: 24002a14 .word 0x24002a14 801582c: 24002efc .word 0x24002efc 8015830: 24002ef8 .word 0x24002ef8 8015834: e000ed04 .word 0xe000ed04 08015838 : /*-----------------------------------------------------------*/ TickType_t xTaskGetTickCount( void ) { 8015838: b480 push {r7} 801583a: b083 sub sp, #12 801583c: af00 add r7, sp, #0 TickType_t xTicks; /* Critical section required if running on a 16 bit processor. */ portTICK_TYPE_ENTER_CRITICAL(); { xTicks = xTickCount; 801583e: 4b05 ldr r3, [pc, #20] @ (8015854 ) 8015840: 681b ldr r3, [r3, #0] 8015842: 607b str r3, [r7, #4] } portTICK_TYPE_EXIT_CRITICAL(); return xTicks; 8015844: 687b ldr r3, [r7, #4] } 8015846: 4618 mov r0, r3 8015848: 370c adds r7, #12 801584a: 46bd mov sp, r7 801584c: f85d 7b04 ldr.w r7, [sp], #4 8015850: 4770 bx lr 8015852: bf00 nop 8015854: 24002eec .word 0x24002eec 08015858 : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { 8015858: b580 push {r7, lr} 801585a: b086 sub sp, #24 801585c: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; 801585e: 2300 movs r3, #0 8015860: 617b str r3, [r7, #20] /* Called by the portable layer each time a tick interrupt occurs. Increments the tick then checks to see if the new tick value will cause any tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8015862: 4b4f ldr r3, [pc, #316] @ (80159a0 ) 8015864: 681b ldr r3, [r3, #0] 8015866: 2b00 cmp r3, #0 8015868: f040 8090 bne.w 801598c { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 801586c: 4b4d ldr r3, [pc, #308] @ (80159a4 ) 801586e: 681b ldr r3, [r3, #0] 8015870: 3301 adds r3, #1 8015872: 613b str r3, [r7, #16] /* Increment the RTOS tick, switching the delayed and overflowed delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; 8015874: 4a4b ldr r2, [pc, #300] @ (80159a4 ) 8015876: 693b ldr r3, [r7, #16] 8015878: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ 801587a: 693b ldr r3, [r7, #16] 801587c: 2b00 cmp r3, #0 801587e: d121 bne.n 80158c4 { taskSWITCH_DELAYED_LISTS(); 8015880: 4b49 ldr r3, [pc, #292] @ (80159a8 ) 8015882: 681b ldr r3, [r3, #0] 8015884: 681b ldr r3, [r3, #0] 8015886: 2b00 cmp r3, #0 8015888: d00b beq.n 80158a2 __asm volatile 801588a: f04f 0350 mov.w r3, #80 @ 0x50 801588e: f383 8811 msr BASEPRI, r3 8015892: f3bf 8f6f isb sy 8015896: f3bf 8f4f dsb sy 801589a: 603b str r3, [r7, #0] } 801589c: bf00 nop 801589e: bf00 nop 80158a0: e7fd b.n 801589e 80158a2: 4b41 ldr r3, [pc, #260] @ (80159a8 ) 80158a4: 681b ldr r3, [r3, #0] 80158a6: 60fb str r3, [r7, #12] 80158a8: 4b40 ldr r3, [pc, #256] @ (80159ac ) 80158aa: 681b ldr r3, [r3, #0] 80158ac: 4a3e ldr r2, [pc, #248] @ (80159a8 ) 80158ae: 6013 str r3, [r2, #0] 80158b0: 4a3e ldr r2, [pc, #248] @ (80159ac ) 80158b2: 68fb ldr r3, [r7, #12] 80158b4: 6013 str r3, [r2, #0] 80158b6: 4b3e ldr r3, [pc, #248] @ (80159b0 ) 80158b8: 681b ldr r3, [r3, #0] 80158ba: 3301 adds r3, #1 80158bc: 4a3c ldr r2, [pc, #240] @ (80159b0 ) 80158be: 6013 str r3, [r2, #0] 80158c0: f000 fb18 bl 8015ef4 /* See if this tick has made a timeout expire. Tasks are stored in the queue in the order of their wake time - meaning once one task has been found whose block time has not expired there is no need to look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) 80158c4: 4b3b ldr r3, [pc, #236] @ (80159b4 ) 80158c6: 681b ldr r3, [r3, #0] 80158c8: 693a ldr r2, [r7, #16] 80158ca: 429a cmp r2, r3 80158cc: d349 bcc.n 8015962 { for( ;; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 80158ce: 4b36 ldr r3, [pc, #216] @ (80159a8 ) 80158d0: 681b ldr r3, [r3, #0] 80158d2: 681b ldr r3, [r3, #0] 80158d4: 2b00 cmp r3, #0 80158d6: d104 bne.n 80158e2 /* The delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 80158d8: 4b36 ldr r3, [pc, #216] @ (80159b4 ) 80158da: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80158de: 601a str r2, [r3, #0] break; 80158e0: e03f b.n 8015962 { /* The delayed list is not empty, get the value of the item at the head of the delayed list. This is the time at which the task at the head of the delayed list must be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80158e2: 4b31 ldr r3, [pc, #196] @ (80159a8 ) 80158e4: 681b ldr r3, [r3, #0] 80158e6: 68db ldr r3, [r3, #12] 80158e8: 68db ldr r3, [r3, #12] 80158ea: 60bb str r3, [r7, #8] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); 80158ec: 68bb ldr r3, [r7, #8] 80158ee: 685b ldr r3, [r3, #4] 80158f0: 607b str r3, [r7, #4] if( xConstTickCount < xItemValue ) 80158f2: 693a ldr r2, [r7, #16] 80158f4: 687b ldr r3, [r7, #4] 80158f6: 429a cmp r2, r3 80158f8: d203 bcs.n 8015902 /* It is not time to unblock this item yet, but the item value is the time at which the task at the head of the blocked list must be removed from the Blocked state - so record the item value in xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; 80158fa: 4a2e ldr r2, [pc, #184] @ (80159b4 ) 80158fc: 687b ldr r3, [r7, #4] 80158fe: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ 8015900: e02f b.n 8015962 { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8015902: 68bb ldr r3, [r7, #8] 8015904: 3304 adds r3, #4 8015906: 4618 mov r0, r3 8015908: f7fe fb06 bl 8013f18 /* Is the task waiting on an event also? If so remove it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 801590c: 68bb ldr r3, [r7, #8] 801590e: 6a9b ldr r3, [r3, #40] @ 0x28 8015910: 2b00 cmp r3, #0 8015912: d004 beq.n 801591e { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 8015914: 68bb ldr r3, [r7, #8] 8015916: 3318 adds r3, #24 8015918: 4618 mov r0, r3 801591a: f7fe fafd bl 8013f18 mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready list. */ prvAddTaskToReadyList( pxTCB ); 801591e: 68bb ldr r3, [r7, #8] 8015920: 6ada ldr r2, [r3, #44] @ 0x2c 8015922: 4b25 ldr r3, [pc, #148] @ (80159b8 ) 8015924: 681b ldr r3, [r3, #0] 8015926: 429a cmp r2, r3 8015928: d903 bls.n 8015932 801592a: 68bb ldr r3, [r7, #8] 801592c: 6adb ldr r3, [r3, #44] @ 0x2c 801592e: 4a22 ldr r2, [pc, #136] @ (80159b8 ) 8015930: 6013 str r3, [r2, #0] 8015932: 68bb ldr r3, [r7, #8] 8015934: 6ada ldr r2, [r3, #44] @ 0x2c 8015936: 4613 mov r3, r2 8015938: 009b lsls r3, r3, #2 801593a: 4413 add r3, r2 801593c: 009b lsls r3, r3, #2 801593e: 4a1f ldr r2, [pc, #124] @ (80159bc ) 8015940: 441a add r2, r3 8015942: 68bb ldr r3, [r7, #8] 8015944: 3304 adds r3, #4 8015946: 4619 mov r1, r3 8015948: 4610 mov r0, r2 801594a: f7fe fa88 bl 8013e5e { /* Preemption is on, but a context switch should only be performed if the unblocked task has a priority that is equal to or higher than the currently executing task. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 801594e: 68bb ldr r3, [r7, #8] 8015950: 6ada ldr r2, [r3, #44] @ 0x2c 8015952: 4b1b ldr r3, [pc, #108] @ (80159c0 ) 8015954: 681b ldr r3, [r3, #0] 8015956: 6adb ldr r3, [r3, #44] @ 0x2c 8015958: 429a cmp r2, r3 801595a: d3b8 bcc.n 80158ce { xSwitchRequired = pdTRUE; 801595c: 2301 movs r3, #1 801595e: 617b str r3, [r7, #20] if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8015960: e7b5 b.n 80158ce /* Tasks of equal priority to the currently running task will share processing time (time slice) if preemption is on, and the application writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 8015962: 4b17 ldr r3, [pc, #92] @ (80159c0 ) 8015964: 681b ldr r3, [r3, #0] 8015966: 6ada ldr r2, [r3, #44] @ 0x2c 8015968: 4914 ldr r1, [pc, #80] @ (80159bc ) 801596a: 4613 mov r3, r2 801596c: 009b lsls r3, r3, #2 801596e: 4413 add r3, r2 8015970: 009b lsls r3, r3, #2 8015972: 440b add r3, r1 8015974: 681b ldr r3, [r3, #0] 8015976: 2b01 cmp r3, #1 8015978: d901 bls.n 801597e { xSwitchRequired = pdTRUE; 801597a: 2301 movs r3, #1 801597c: 617b str r3, [r7, #20] } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) 801597e: 4b11 ldr r3, [pc, #68] @ (80159c4 ) 8015980: 681b ldr r3, [r3, #0] 8015982: 2b00 cmp r3, #0 8015984: d007 beq.n 8015996 { xSwitchRequired = pdTRUE; 8015986: 2301 movs r3, #1 8015988: 617b str r3, [r7, #20] 801598a: e004 b.n 8015996 } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; 801598c: 4b0e ldr r3, [pc, #56] @ (80159c8 ) 801598e: 681b ldr r3, [r3, #0] 8015990: 3301 adds r3, #1 8015992: 4a0d ldr r2, [pc, #52] @ (80159c8 ) 8015994: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; 8015996: 697b ldr r3, [r7, #20] } 8015998: 4618 mov r0, r3 801599a: 3718 adds r7, #24 801599c: 46bd mov sp, r7 801599e: bd80 pop {r7, pc} 80159a0: 24002f10 .word 0x24002f10 80159a4: 24002eec .word 0x24002eec 80159a8: 24002ea0 .word 0x24002ea0 80159ac: 24002ea4 .word 0x24002ea4 80159b0: 24002f00 .word 0x24002f00 80159b4: 24002f08 .word 0x24002f08 80159b8: 24002ef0 .word 0x24002ef0 80159bc: 24002a18 .word 0x24002a18 80159c0: 24002a14 .word 0x24002a14 80159c4: 24002efc .word 0x24002efc 80159c8: 24002ef8 .word 0x24002ef8 080159cc : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { 80159cc: b580 push {r7, lr} 80159ce: b084 sub sp, #16 80159d0: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) 80159d2: 4b32 ldr r3, [pc, #200] @ (8015a9c ) 80159d4: 681b ldr r3, [r3, #0] 80159d6: 2b00 cmp r3, #0 80159d8: d003 beq.n 80159e2 { /* The scheduler is currently suspended - do not allow a context switch. */ xYieldPending = pdTRUE; 80159da: 4b31 ldr r3, [pc, #196] @ (8015aa0 ) 80159dc: 2201 movs r2, #1 80159de: 601a str r2, [r3, #0] for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ } } 80159e0: e058 b.n 8015a94 xYieldPending = pdFALSE; 80159e2: 4b2f ldr r3, [pc, #188] @ (8015aa0 ) 80159e4: 2200 movs r2, #0 80159e6: 601a str r2, [r3, #0] taskCHECK_FOR_STACK_OVERFLOW(); 80159e8: 4b2e ldr r3, [pc, #184] @ (8015aa4 ) 80159ea: 681b ldr r3, [r3, #0] 80159ec: 681a ldr r2, [r3, #0] 80159ee: 4b2d ldr r3, [pc, #180] @ (8015aa4 ) 80159f0: 681b ldr r3, [r3, #0] 80159f2: 6b1b ldr r3, [r3, #48] @ 0x30 80159f4: 429a cmp r2, r3 80159f6: d808 bhi.n 8015a0a 80159f8: 4b2a ldr r3, [pc, #168] @ (8015aa4 ) 80159fa: 681a ldr r2, [r3, #0] 80159fc: 4b29 ldr r3, [pc, #164] @ (8015aa4 ) 80159fe: 681b ldr r3, [r3, #0] 8015a00: 3334 adds r3, #52 @ 0x34 8015a02: 4619 mov r1, r3 8015a04: 4610 mov r0, r2 8015a06: f7ea fe33 bl 8000670 taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015a0a: 4b27 ldr r3, [pc, #156] @ (8015aa8 ) 8015a0c: 681b ldr r3, [r3, #0] 8015a0e: 60fb str r3, [r7, #12] 8015a10: e011 b.n 8015a36 8015a12: 68fb ldr r3, [r7, #12] 8015a14: 2b00 cmp r3, #0 8015a16: d10b bne.n 8015a30 __asm volatile 8015a18: f04f 0350 mov.w r3, #80 @ 0x50 8015a1c: f383 8811 msr BASEPRI, r3 8015a20: f3bf 8f6f isb sy 8015a24: f3bf 8f4f dsb sy 8015a28: 607b str r3, [r7, #4] } 8015a2a: bf00 nop 8015a2c: bf00 nop 8015a2e: e7fd b.n 8015a2c 8015a30: 68fb ldr r3, [r7, #12] 8015a32: 3b01 subs r3, #1 8015a34: 60fb str r3, [r7, #12] 8015a36: 491d ldr r1, [pc, #116] @ (8015aac ) 8015a38: 68fa ldr r2, [r7, #12] 8015a3a: 4613 mov r3, r2 8015a3c: 009b lsls r3, r3, #2 8015a3e: 4413 add r3, r2 8015a40: 009b lsls r3, r3, #2 8015a42: 440b add r3, r1 8015a44: 681b ldr r3, [r3, #0] 8015a46: 2b00 cmp r3, #0 8015a48: d0e3 beq.n 8015a12 8015a4a: 68fa ldr r2, [r7, #12] 8015a4c: 4613 mov r3, r2 8015a4e: 009b lsls r3, r3, #2 8015a50: 4413 add r3, r2 8015a52: 009b lsls r3, r3, #2 8015a54: 4a15 ldr r2, [pc, #84] @ (8015aac ) 8015a56: 4413 add r3, r2 8015a58: 60bb str r3, [r7, #8] 8015a5a: 68bb ldr r3, [r7, #8] 8015a5c: 685b ldr r3, [r3, #4] 8015a5e: 685a ldr r2, [r3, #4] 8015a60: 68bb ldr r3, [r7, #8] 8015a62: 605a str r2, [r3, #4] 8015a64: 68bb ldr r3, [r7, #8] 8015a66: 685a ldr r2, [r3, #4] 8015a68: 68bb ldr r3, [r7, #8] 8015a6a: 3308 adds r3, #8 8015a6c: 429a cmp r2, r3 8015a6e: d104 bne.n 8015a7a 8015a70: 68bb ldr r3, [r7, #8] 8015a72: 685b ldr r3, [r3, #4] 8015a74: 685a ldr r2, [r3, #4] 8015a76: 68bb ldr r3, [r7, #8] 8015a78: 605a str r2, [r3, #4] 8015a7a: 68bb ldr r3, [r7, #8] 8015a7c: 685b ldr r3, [r3, #4] 8015a7e: 68db ldr r3, [r3, #12] 8015a80: 4a08 ldr r2, [pc, #32] @ (8015aa4 ) 8015a82: 6013 str r3, [r2, #0] 8015a84: 4a08 ldr r2, [pc, #32] @ (8015aa8 ) 8015a86: 68fb ldr r3, [r7, #12] 8015a88: 6013 str r3, [r2, #0] _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 8015a8a: 4b06 ldr r3, [pc, #24] @ (8015aa4 ) 8015a8c: 681b ldr r3, [r3, #0] 8015a8e: 3354 adds r3, #84 @ 0x54 8015a90: 4a07 ldr r2, [pc, #28] @ (8015ab0 ) 8015a92: 6013 str r3, [r2, #0] } 8015a94: bf00 nop 8015a96: 3710 adds r7, #16 8015a98: 46bd mov sp, r7 8015a9a: bd80 pop {r7, pc} 8015a9c: 24002f10 .word 0x24002f10 8015aa0: 24002efc .word 0x24002efc 8015aa4: 24002a14 .word 0x24002a14 8015aa8: 24002ef0 .word 0x24002ef0 8015aac: 24002a18 .word 0x24002a18 8015ab0: 24000054 .word 0x24000054 08015ab4 : /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { 8015ab4: b580 push {r7, lr} 8015ab6: b084 sub sp, #16 8015ab8: af00 add r7, sp, #0 8015aba: 6078 str r0, [r7, #4] 8015abc: 6039 str r1, [r7, #0] configASSERT( pxEventList ); 8015abe: 687b ldr r3, [r7, #4] 8015ac0: 2b00 cmp r3, #0 8015ac2: d10b bne.n 8015adc __asm volatile 8015ac4: f04f 0350 mov.w r3, #80 @ 0x50 8015ac8: f383 8811 msr BASEPRI, r3 8015acc: f3bf 8f6f isb sy 8015ad0: f3bf 8f4f dsb sy 8015ad4: 60fb str r3, [r7, #12] } 8015ad6: bf00 nop 8015ad8: bf00 nop 8015ada: e7fd b.n 8015ad8 /* Place the event list item of the TCB in the appropriate event list. This is placed in the list in priority order so the highest priority task is the first to be woken by the event. The queue that contains the event list is locked, preventing simultaneous access from interrupts. */ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 8015adc: 4b07 ldr r3, [pc, #28] @ (8015afc ) 8015ade: 681b ldr r3, [r3, #0] 8015ae0: 3318 adds r3, #24 8015ae2: 4619 mov r1, r3 8015ae4: 6878 ldr r0, [r7, #4] 8015ae6: f7fe f9de bl 8013ea6 prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 8015aea: 2101 movs r1, #1 8015aec: 6838 ldr r0, [r7, #0] 8015aee: f000 fded bl 80166cc } 8015af2: bf00 nop 8015af4: 3710 adds r7, #16 8015af6: 46bd mov sp, r7 8015af8: bd80 pop {r7, pc} 8015afa: bf00 nop 8015afc: 24002a14 .word 0x24002a14 08015b00 : /*-----------------------------------------------------------*/ #if( configUSE_TIMERS == 1 ) void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 8015b00: b580 push {r7, lr} 8015b02: b086 sub sp, #24 8015b04: af00 add r7, sp, #0 8015b06: 60f8 str r0, [r7, #12] 8015b08: 60b9 str r1, [r7, #8] 8015b0a: 607a str r2, [r7, #4] configASSERT( pxEventList ); 8015b0c: 68fb ldr r3, [r7, #12] 8015b0e: 2b00 cmp r3, #0 8015b10: d10b bne.n 8015b2a __asm volatile 8015b12: f04f 0350 mov.w r3, #80 @ 0x50 8015b16: f383 8811 msr BASEPRI, r3 8015b1a: f3bf 8f6f isb sy 8015b1e: f3bf 8f4f dsb sy 8015b22: 617b str r3, [r7, #20] } 8015b24: bf00 nop 8015b26: bf00 nop 8015b28: e7fd b.n 8015b26 /* Place the event list item of the TCB in the appropriate event list. In this case it is assume that this is the only task that is going to be waiting on this event list, so the faster vListInsertEnd() function can be used in place of vListInsert. */ vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 8015b2a: 4b0a ldr r3, [pc, #40] @ (8015b54 ) 8015b2c: 681b ldr r3, [r3, #0] 8015b2e: 3318 adds r3, #24 8015b30: 4619 mov r1, r3 8015b32: 68f8 ldr r0, [r7, #12] 8015b34: f7fe f993 bl 8013e5e /* If the task should block indefinitely then set the block time to a value that will be recognised as an indefinite delay inside the prvAddCurrentTaskToDelayedList() function. */ if( xWaitIndefinitely != pdFALSE ) 8015b38: 687b ldr r3, [r7, #4] 8015b3a: 2b00 cmp r3, #0 8015b3c: d002 beq.n 8015b44 { xTicksToWait = portMAX_DELAY; 8015b3e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8015b42: 60bb str r3, [r7, #8] } traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); 8015b44: 6879 ldr r1, [r7, #4] 8015b46: 68b8 ldr r0, [r7, #8] 8015b48: f000 fdc0 bl 80166cc } 8015b4c: bf00 nop 8015b4e: 3718 adds r7, #24 8015b50: 46bd mov sp, r7 8015b52: bd80 pop {r7, pc} 8015b54: 24002a14 .word 0x24002a14 08015b58 : #endif /* configUSE_TIMERS */ /*-----------------------------------------------------------*/ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { 8015b58: b580 push {r7, lr} 8015b5a: b086 sub sp, #24 8015b5c: af00 add r7, sp, #0 8015b5e: 6078 str r0, [r7, #4] get called - the lock count on the queue will get modified instead. This means exclusive access to the event list is guaranteed here. This function assumes that a check has already been made to ensure that pxEventList is not empty. */ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015b60: 687b ldr r3, [r7, #4] 8015b62: 68db ldr r3, [r3, #12] 8015b64: 68db ldr r3, [r3, #12] 8015b66: 613b str r3, [r7, #16] configASSERT( pxUnblockedTCB ); 8015b68: 693b ldr r3, [r7, #16] 8015b6a: 2b00 cmp r3, #0 8015b6c: d10b bne.n 8015b86 __asm volatile 8015b6e: f04f 0350 mov.w r3, #80 @ 0x50 8015b72: f383 8811 msr BASEPRI, r3 8015b76: f3bf 8f6f isb sy 8015b7a: f3bf 8f4f dsb sy 8015b7e: 60fb str r3, [r7, #12] } 8015b80: bf00 nop 8015b82: bf00 nop 8015b84: e7fd b.n 8015b82 ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); 8015b86: 693b ldr r3, [r7, #16] 8015b88: 3318 adds r3, #24 8015b8a: 4618 mov r0, r3 8015b8c: f7fe f9c4 bl 8013f18 if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8015b90: 4b1d ldr r3, [pc, #116] @ (8015c08 ) 8015b92: 681b ldr r3, [r3, #0] 8015b94: 2b00 cmp r3, #0 8015b96: d11d bne.n 8015bd4 { ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); 8015b98: 693b ldr r3, [r7, #16] 8015b9a: 3304 adds r3, #4 8015b9c: 4618 mov r0, r3 8015b9e: f7fe f9bb bl 8013f18 prvAddTaskToReadyList( pxUnblockedTCB ); 8015ba2: 693b ldr r3, [r7, #16] 8015ba4: 6ada ldr r2, [r3, #44] @ 0x2c 8015ba6: 4b19 ldr r3, [pc, #100] @ (8015c0c ) 8015ba8: 681b ldr r3, [r3, #0] 8015baa: 429a cmp r2, r3 8015bac: d903 bls.n 8015bb6 8015bae: 693b ldr r3, [r7, #16] 8015bb0: 6adb ldr r3, [r3, #44] @ 0x2c 8015bb2: 4a16 ldr r2, [pc, #88] @ (8015c0c ) 8015bb4: 6013 str r3, [r2, #0] 8015bb6: 693b ldr r3, [r7, #16] 8015bb8: 6ada ldr r2, [r3, #44] @ 0x2c 8015bba: 4613 mov r3, r2 8015bbc: 009b lsls r3, r3, #2 8015bbe: 4413 add r3, r2 8015bc0: 009b lsls r3, r3, #2 8015bc2: 4a13 ldr r2, [pc, #76] @ (8015c10 ) 8015bc4: 441a add r2, r3 8015bc6: 693b ldr r3, [r7, #16] 8015bc8: 3304 adds r3, #4 8015bca: 4619 mov r1, r3 8015bcc: 4610 mov r0, r2 8015bce: f7fe f946 bl 8013e5e 8015bd2: e005 b.n 8015be0 } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); 8015bd4: 693b ldr r3, [r7, #16] 8015bd6: 3318 adds r3, #24 8015bd8: 4619 mov r1, r3 8015bda: 480e ldr r0, [pc, #56] @ (8015c14 ) 8015bdc: f7fe f93f bl 8013e5e } if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) 8015be0: 693b ldr r3, [r7, #16] 8015be2: 6ada ldr r2, [r3, #44] @ 0x2c 8015be4: 4b0c ldr r3, [pc, #48] @ (8015c18 ) 8015be6: 681b ldr r3, [r3, #0] 8015be8: 6adb ldr r3, [r3, #44] @ 0x2c 8015bea: 429a cmp r2, r3 8015bec: d905 bls.n 8015bfa { /* Return true if the task removed from the event list has a higher priority than the calling task. This allows the calling task to know if it should force a context switch now. */ xReturn = pdTRUE; 8015bee: 2301 movs r3, #1 8015bf0: 617b str r3, [r7, #20] /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 8015bf2: 4b0a ldr r3, [pc, #40] @ (8015c1c ) 8015bf4: 2201 movs r2, #1 8015bf6: 601a str r2, [r3, #0] 8015bf8: e001 b.n 8015bfe } else { xReturn = pdFALSE; 8015bfa: 2300 movs r3, #0 8015bfc: 617b str r3, [r7, #20] } return xReturn; 8015bfe: 697b ldr r3, [r7, #20] } 8015c00: 4618 mov r0, r3 8015c02: 3718 adds r7, #24 8015c04: 46bd mov sp, r7 8015c06: bd80 pop {r7, pc} 8015c08: 24002f10 .word 0x24002f10 8015c0c: 24002ef0 .word 0x24002ef0 8015c10: 24002a18 .word 0x24002a18 8015c14: 24002ea8 .word 0x24002ea8 8015c18: 24002a14 .word 0x24002a14 8015c1c: 24002efc .word 0x24002efc 08015c20 : } } /*-----------------------------------------------------------*/ void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) { 8015c20: b580 push {r7, lr} 8015c22: b084 sub sp, #16 8015c24: af00 add r7, sp, #0 8015c26: 6078 str r0, [r7, #4] configASSERT( pxTimeOut ); 8015c28: 687b ldr r3, [r7, #4] 8015c2a: 2b00 cmp r3, #0 8015c2c: d10b bne.n 8015c46 __asm volatile 8015c2e: f04f 0350 mov.w r3, #80 @ 0x50 8015c32: f383 8811 msr BASEPRI, r3 8015c36: f3bf 8f6f isb sy 8015c3a: f3bf 8f4f dsb sy 8015c3e: 60fb str r3, [r7, #12] } 8015c40: bf00 nop 8015c42: bf00 nop 8015c44: e7fd b.n 8015c42 taskENTER_CRITICAL(); 8015c46: f001 fb07 bl 8017258 { pxTimeOut->xOverflowCount = xNumOfOverflows; 8015c4a: 4b07 ldr r3, [pc, #28] @ (8015c68 ) 8015c4c: 681a ldr r2, [r3, #0] 8015c4e: 687b ldr r3, [r7, #4] 8015c50: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 8015c52: 4b06 ldr r3, [pc, #24] @ (8015c6c ) 8015c54: 681a ldr r2, [r3, #0] 8015c56: 687b ldr r3, [r7, #4] 8015c58: 605a str r2, [r3, #4] } taskEXIT_CRITICAL(); 8015c5a: f001 fb2f bl 80172bc } 8015c5e: bf00 nop 8015c60: 3710 adds r7, #16 8015c62: 46bd mov sp, r7 8015c64: bd80 pop {r7, pc} 8015c66: bf00 nop 8015c68: 24002f00 .word 0x24002f00 8015c6c: 24002eec .word 0x24002eec 08015c70 : /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { 8015c70: b480 push {r7} 8015c72: b083 sub sp, #12 8015c74: af00 add r7, sp, #0 8015c76: 6078 str r0, [r7, #4] /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; 8015c78: 4b06 ldr r3, [pc, #24] @ (8015c94 ) 8015c7a: 681a ldr r2, [r3, #0] 8015c7c: 687b ldr r3, [r7, #4] 8015c7e: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 8015c80: 4b05 ldr r3, [pc, #20] @ (8015c98 ) 8015c82: 681a ldr r2, [r3, #0] 8015c84: 687b ldr r3, [r7, #4] 8015c86: 605a str r2, [r3, #4] } 8015c88: bf00 nop 8015c8a: 370c adds r7, #12 8015c8c: 46bd mov sp, r7 8015c8e: f85d 7b04 ldr.w r7, [sp], #4 8015c92: 4770 bx lr 8015c94: 24002f00 .word 0x24002f00 8015c98: 24002eec .word 0x24002eec 08015c9c : /*-----------------------------------------------------------*/ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) { 8015c9c: b580 push {r7, lr} 8015c9e: b088 sub sp, #32 8015ca0: af00 add r7, sp, #0 8015ca2: 6078 str r0, [r7, #4] 8015ca4: 6039 str r1, [r7, #0] BaseType_t xReturn; configASSERT( pxTimeOut ); 8015ca6: 687b ldr r3, [r7, #4] 8015ca8: 2b00 cmp r3, #0 8015caa: d10b bne.n 8015cc4 __asm volatile 8015cac: f04f 0350 mov.w r3, #80 @ 0x50 8015cb0: f383 8811 msr BASEPRI, r3 8015cb4: f3bf 8f6f isb sy 8015cb8: f3bf 8f4f dsb sy 8015cbc: 613b str r3, [r7, #16] } 8015cbe: bf00 nop 8015cc0: bf00 nop 8015cc2: e7fd b.n 8015cc0 configASSERT( pxTicksToWait ); 8015cc4: 683b ldr r3, [r7, #0] 8015cc6: 2b00 cmp r3, #0 8015cc8: d10b bne.n 8015ce2 __asm volatile 8015cca: f04f 0350 mov.w r3, #80 @ 0x50 8015cce: f383 8811 msr BASEPRI, r3 8015cd2: f3bf 8f6f isb sy 8015cd6: f3bf 8f4f dsb sy 8015cda: 60fb str r3, [r7, #12] } 8015cdc: bf00 nop 8015cde: bf00 nop 8015ce0: e7fd b.n 8015cde taskENTER_CRITICAL(); 8015ce2: f001 fab9 bl 8017258 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; 8015ce6: 4b1d ldr r3, [pc, #116] @ (8015d5c ) 8015ce8: 681b ldr r3, [r3, #0] 8015cea: 61bb str r3, [r7, #24] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; 8015cec: 687b ldr r3, [r7, #4] 8015cee: 685b ldr r3, [r3, #4] 8015cf0: 69ba ldr r2, [r7, #24] 8015cf2: 1ad3 subs r3, r2, r3 8015cf4: 617b str r3, [r7, #20] } else #endif #if ( INCLUDE_vTaskSuspend == 1 ) if( *pxTicksToWait == portMAX_DELAY ) 8015cf6: 683b ldr r3, [r7, #0] 8015cf8: 681b ldr r3, [r3, #0] 8015cfa: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015cfe: d102 bne.n 8015d06 { /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is the maximum block time then the task should block indefinitely, and therefore never time out. */ xReturn = pdFALSE; 8015d00: 2300 movs r3, #0 8015d02: 61fb str r3, [r7, #28] 8015d04: e023 b.n 8015d4e } else #endif if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ 8015d06: 687b ldr r3, [r7, #4] 8015d08: 681a ldr r2, [r3, #0] 8015d0a: 4b15 ldr r3, [pc, #84] @ (8015d60 ) 8015d0c: 681b ldr r3, [r3, #0] 8015d0e: 429a cmp r2, r3 8015d10: d007 beq.n 8015d22 8015d12: 687b ldr r3, [r7, #4] 8015d14: 685b ldr r3, [r3, #4] 8015d16: 69ba ldr r2, [r7, #24] 8015d18: 429a cmp r2, r3 8015d1a: d302 bcc.n 8015d22 /* The tick count is greater than the time at which vTaskSetTimeout() was called, but has also overflowed since vTaskSetTimeOut() was called. It must have wrapped all the way around and gone past again. This passed since vTaskSetTimeout() was called. */ xReturn = pdTRUE; 8015d1c: 2301 movs r3, #1 8015d1e: 61fb str r3, [r7, #28] 8015d20: e015 b.n 8015d4e } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ 8015d22: 683b ldr r3, [r7, #0] 8015d24: 681b ldr r3, [r3, #0] 8015d26: 697a ldr r2, [r7, #20] 8015d28: 429a cmp r2, r3 8015d2a: d20b bcs.n 8015d44 { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; 8015d2c: 683b ldr r3, [r7, #0] 8015d2e: 681a ldr r2, [r3, #0] 8015d30: 697b ldr r3, [r7, #20] 8015d32: 1ad2 subs r2, r2, r3 8015d34: 683b ldr r3, [r7, #0] 8015d36: 601a str r2, [r3, #0] vTaskInternalSetTimeOutState( pxTimeOut ); 8015d38: 6878 ldr r0, [r7, #4] 8015d3a: f7ff ff99 bl 8015c70 xReturn = pdFALSE; 8015d3e: 2300 movs r3, #0 8015d40: 61fb str r3, [r7, #28] 8015d42: e004 b.n 8015d4e } else { *pxTicksToWait = 0; 8015d44: 683b ldr r3, [r7, #0] 8015d46: 2200 movs r2, #0 8015d48: 601a str r2, [r3, #0] xReturn = pdTRUE; 8015d4a: 2301 movs r3, #1 8015d4c: 61fb str r3, [r7, #28] } } taskEXIT_CRITICAL(); 8015d4e: f001 fab5 bl 80172bc return xReturn; 8015d52: 69fb ldr r3, [r7, #28] } 8015d54: 4618 mov r0, r3 8015d56: 3720 adds r7, #32 8015d58: 46bd mov sp, r7 8015d5a: bd80 pop {r7, pc} 8015d5c: 24002eec .word 0x24002eec 8015d60: 24002f00 .word 0x24002f00 08015d64 : /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { 8015d64: b480 push {r7} 8015d66: af00 add r7, sp, #0 xYieldPending = pdTRUE; 8015d68: 4b03 ldr r3, [pc, #12] @ (8015d78 ) 8015d6a: 2201 movs r2, #1 8015d6c: 601a str r2, [r3, #0] } 8015d6e: bf00 nop 8015d70: 46bd mov sp, r7 8015d72: f85d 7b04 ldr.w r7, [sp], #4 8015d76: 4770 bx lr 8015d78: 24002efc .word 0x24002efc 08015d7c : * * void prvIdleTask( void *pvParameters ); * */ static portTASK_FUNCTION( prvIdleTask, pvParameters ) { 8015d7c: b580 push {r7, lr} 8015d7e: b082 sub sp, #8 8015d80: af00 add r7, sp, #0 8015d82: 6078 str r0, [r7, #4] for( ;; ) { /* See if any tasks have deleted themselves - if so then the idle task is responsible for freeing the deleted task's TCB and stack. */ prvCheckTasksWaitingTermination(); 8015d84: f000 f852 bl 8015e2c A critical region is not required here as we are just reading from the list, and an occasional incorrect value will not matter. If the ready list at the idle priority contains more than one task then a task other than the idle task is ready to execute. */ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) 8015d88: 4b06 ldr r3, [pc, #24] @ (8015da4 ) 8015d8a: 681b ldr r3, [r3, #0] 8015d8c: 2b01 cmp r3, #1 8015d8e: d9f9 bls.n 8015d84 { taskYIELD(); 8015d90: 4b05 ldr r3, [pc, #20] @ (8015da8 ) 8015d92: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015d96: 601a str r2, [r3, #0] 8015d98: f3bf 8f4f dsb sy 8015d9c: f3bf 8f6f isb sy prvCheckTasksWaitingTermination(); 8015da0: e7f0 b.n 8015d84 8015da2: bf00 nop 8015da4: 24002a18 .word 0x24002a18 8015da8: e000ed04 .word 0xe000ed04 08015dac : #endif /* portUSING_MPU_WRAPPERS */ /*-----------------------------------------------------------*/ static void prvInitialiseTaskLists( void ) { 8015dac: b580 push {r7, lr} 8015dae: b082 sub sp, #8 8015db0: af00 add r7, sp, #0 UBaseType_t uxPriority; for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 8015db2: 2300 movs r3, #0 8015db4: 607b str r3, [r7, #4] 8015db6: e00c b.n 8015dd2 { vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); 8015db8: 687a ldr r2, [r7, #4] 8015dba: 4613 mov r3, r2 8015dbc: 009b lsls r3, r3, #2 8015dbe: 4413 add r3, r2 8015dc0: 009b lsls r3, r3, #2 8015dc2: 4a12 ldr r2, [pc, #72] @ (8015e0c ) 8015dc4: 4413 add r3, r2 8015dc6: 4618 mov r0, r3 8015dc8: f7fe f81c bl 8013e04 for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 8015dcc: 687b ldr r3, [r7, #4] 8015dce: 3301 adds r3, #1 8015dd0: 607b str r3, [r7, #4] 8015dd2: 687b ldr r3, [r7, #4] 8015dd4: 2b37 cmp r3, #55 @ 0x37 8015dd6: d9ef bls.n 8015db8 } vListInitialise( &xDelayedTaskList1 ); 8015dd8: 480d ldr r0, [pc, #52] @ (8015e10 ) 8015dda: f7fe f813 bl 8013e04 vListInitialise( &xDelayedTaskList2 ); 8015dde: 480d ldr r0, [pc, #52] @ (8015e14 ) 8015de0: f7fe f810 bl 8013e04 vListInitialise( &xPendingReadyList ); 8015de4: 480c ldr r0, [pc, #48] @ (8015e18 ) 8015de6: f7fe f80d bl 8013e04 #if ( INCLUDE_vTaskDelete == 1 ) { vListInitialise( &xTasksWaitingTermination ); 8015dea: 480c ldr r0, [pc, #48] @ (8015e1c ) 8015dec: f7fe f80a bl 8013e04 } #endif /* INCLUDE_vTaskDelete */ #if ( INCLUDE_vTaskSuspend == 1 ) { vListInitialise( &xSuspendedTaskList ); 8015df0: 480b ldr r0, [pc, #44] @ (8015e20 ) 8015df2: f7fe f807 bl 8013e04 } #endif /* INCLUDE_vTaskSuspend */ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList using list2. */ pxDelayedTaskList = &xDelayedTaskList1; 8015df6: 4b0b ldr r3, [pc, #44] @ (8015e24 ) 8015df8: 4a05 ldr r2, [pc, #20] @ (8015e10 ) 8015dfa: 601a str r2, [r3, #0] pxOverflowDelayedTaskList = &xDelayedTaskList2; 8015dfc: 4b0a ldr r3, [pc, #40] @ (8015e28 ) 8015dfe: 4a05 ldr r2, [pc, #20] @ (8015e14 ) 8015e00: 601a str r2, [r3, #0] } 8015e02: bf00 nop 8015e04: 3708 adds r7, #8 8015e06: 46bd mov sp, r7 8015e08: bd80 pop {r7, pc} 8015e0a: bf00 nop 8015e0c: 24002a18 .word 0x24002a18 8015e10: 24002e78 .word 0x24002e78 8015e14: 24002e8c .word 0x24002e8c 8015e18: 24002ea8 .word 0x24002ea8 8015e1c: 24002ebc .word 0x24002ebc 8015e20: 24002ed4 .word 0x24002ed4 8015e24: 24002ea0 .word 0x24002ea0 8015e28: 24002ea4 .word 0x24002ea4 08015e2c : /*-----------------------------------------------------------*/ static void prvCheckTasksWaitingTermination( void ) { 8015e2c: b580 push {r7, lr} 8015e2e: b082 sub sp, #8 8015e30: af00 add r7, sp, #0 { TCB_t *pxTCB; /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 8015e32: e019 b.n 8015e68 { taskENTER_CRITICAL(); 8015e34: f001 fa10 bl 8017258 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015e38: 4b10 ldr r3, [pc, #64] @ (8015e7c ) 8015e3a: 68db ldr r3, [r3, #12] 8015e3c: 68db ldr r3, [r3, #12] 8015e3e: 607b str r3, [r7, #4] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8015e40: 687b ldr r3, [r7, #4] 8015e42: 3304 adds r3, #4 8015e44: 4618 mov r0, r3 8015e46: f7fe f867 bl 8013f18 --uxCurrentNumberOfTasks; 8015e4a: 4b0d ldr r3, [pc, #52] @ (8015e80 ) 8015e4c: 681b ldr r3, [r3, #0] 8015e4e: 3b01 subs r3, #1 8015e50: 4a0b ldr r2, [pc, #44] @ (8015e80 ) 8015e52: 6013 str r3, [r2, #0] --uxDeletedTasksWaitingCleanUp; 8015e54: 4b0b ldr r3, [pc, #44] @ (8015e84 ) 8015e56: 681b ldr r3, [r3, #0] 8015e58: 3b01 subs r3, #1 8015e5a: 4a0a ldr r2, [pc, #40] @ (8015e84 ) 8015e5c: 6013 str r3, [r2, #0] } taskEXIT_CRITICAL(); 8015e5e: f001 fa2d bl 80172bc prvDeleteTCB( pxTCB ); 8015e62: 6878 ldr r0, [r7, #4] 8015e64: f000 f810 bl 8015e88 while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 8015e68: 4b06 ldr r3, [pc, #24] @ (8015e84 ) 8015e6a: 681b ldr r3, [r3, #0] 8015e6c: 2b00 cmp r3, #0 8015e6e: d1e1 bne.n 8015e34 } } #endif /* INCLUDE_vTaskDelete */ } 8015e70: bf00 nop 8015e72: bf00 nop 8015e74: 3708 adds r7, #8 8015e76: 46bd mov sp, r7 8015e78: bd80 pop {r7, pc} 8015e7a: bf00 nop 8015e7c: 24002ebc .word 0x24002ebc 8015e80: 24002ee8 .word 0x24002ee8 8015e84: 24002ed0 .word 0x24002ed0 08015e88 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelete == 1 ) static void prvDeleteTCB( TCB_t *pxTCB ) { 8015e88: b580 push {r7, lr} 8015e8a: b084 sub sp, #16 8015e8c: af00 add r7, sp, #0 8015e8e: 6078 str r0, [r7, #4] to the task to free any memory allocated at the application level. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ #if ( configUSE_NEWLIB_REENTRANT == 1 ) { _reclaim_reent( &( pxTCB->xNewLib_reent ) ); 8015e90: 687b ldr r3, [r7, #4] 8015e92: 3354 adds r3, #84 @ 0x54 8015e94: 4618 mov r0, r3 8015e96: f001 ff11 bl 8017cbc <_reclaim_reent> #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* The task could have been allocated statically or dynamically, so check what was statically allocated before trying to free the memory. */ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) 8015e9a: 687b ldr r3, [r7, #4] 8015e9c: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8015ea0: 2b00 cmp r3, #0 8015ea2: d108 bne.n 8015eb6 { /* Both the stack and TCB were allocated dynamically, so both must be freed. */ vPortFree( pxTCB->pxStack ); 8015ea4: 687b ldr r3, [r7, #4] 8015ea6: 6b1b ldr r3, [r3, #48] @ 0x30 8015ea8: 4618 mov r0, r3 8015eaa: f001 fbc5 bl 8017638 vPortFree( pxTCB ); 8015eae: 6878 ldr r0, [r7, #4] 8015eb0: f001 fbc2 bl 8017638 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); mtCOVERAGE_TEST_MARKER(); } } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } 8015eb4: e019 b.n 8015eea else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) 8015eb6: 687b ldr r3, [r7, #4] 8015eb8: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8015ebc: 2b01 cmp r3, #1 8015ebe: d103 bne.n 8015ec8 vPortFree( pxTCB ); 8015ec0: 6878 ldr r0, [r7, #4] 8015ec2: f001 fbb9 bl 8017638 } 8015ec6: e010 b.n 8015eea configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); 8015ec8: 687b ldr r3, [r7, #4] 8015eca: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8015ece: 2b02 cmp r3, #2 8015ed0: d00b beq.n 8015eea __asm volatile 8015ed2: f04f 0350 mov.w r3, #80 @ 0x50 8015ed6: f383 8811 msr BASEPRI, r3 8015eda: f3bf 8f6f isb sy 8015ede: f3bf 8f4f dsb sy 8015ee2: 60fb str r3, [r7, #12] } 8015ee4: bf00 nop 8015ee6: bf00 nop 8015ee8: e7fd b.n 8015ee6 } 8015eea: bf00 nop 8015eec: 3710 adds r7, #16 8015eee: 46bd mov sp, r7 8015ef0: bd80 pop {r7, pc} ... 08015ef4 : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { 8015ef4: b480 push {r7} 8015ef6: b083 sub sp, #12 8015ef8: af00 add r7, sp, #0 TCB_t *pxTCB; if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8015efa: 4b0c ldr r3, [pc, #48] @ (8015f2c ) 8015efc: 681b ldr r3, [r3, #0] 8015efe: 681b ldr r3, [r3, #0] 8015f00: 2b00 cmp r3, #0 8015f02: d104 bne.n 8015f0e { /* The new current delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass until there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; 8015f04: 4b0a ldr r3, [pc, #40] @ (8015f30 ) 8015f06: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8015f0a: 601a str r2, [r3, #0] which the task at the head of the delayed list should be removed from the Blocked state. */ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); } } 8015f0c: e008 b.n 8015f20 ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015f0e: 4b07 ldr r3, [pc, #28] @ (8015f2c ) 8015f10: 681b ldr r3, [r3, #0] 8015f12: 68db ldr r3, [r3, #12] 8015f14: 68db ldr r3, [r3, #12] 8015f16: 607b str r3, [r7, #4] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 8015f18: 687b ldr r3, [r7, #4] 8015f1a: 685b ldr r3, [r3, #4] 8015f1c: 4a04 ldr r2, [pc, #16] @ (8015f30 ) 8015f1e: 6013 str r3, [r2, #0] } 8015f20: bf00 nop 8015f22: 370c adds r7, #12 8015f24: 46bd mov sp, r7 8015f26: f85d 7b04 ldr.w r7, [sp], #4 8015f2a: 4770 bx lr 8015f2c: 24002ea0 .word 0x24002ea0 8015f30: 24002f08 .word 0x24002f08 08015f34 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) TaskHandle_t xTaskGetCurrentTaskHandle( void ) { 8015f34: b480 push {r7} 8015f36: b083 sub sp, #12 8015f38: af00 add r7, sp, #0 TaskHandle_t xReturn; /* A critical section is not required as this is not called from an interrupt and the current TCB will always be the same for any individual execution thread. */ xReturn = pxCurrentTCB; 8015f3a: 4b05 ldr r3, [pc, #20] @ (8015f50 ) 8015f3c: 681b ldr r3, [r3, #0] 8015f3e: 607b str r3, [r7, #4] return xReturn; 8015f40: 687b ldr r3, [r7, #4] } 8015f42: 4618 mov r0, r3 8015f44: 370c adds r7, #12 8015f46: 46bd mov sp, r7 8015f48: f85d 7b04 ldr.w r7, [sp], #4 8015f4c: 4770 bx lr 8015f4e: bf00 nop 8015f50: 24002a14 .word 0x24002a14 08015f54 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) BaseType_t xTaskGetSchedulerState( void ) { 8015f54: b480 push {r7} 8015f56: b083 sub sp, #12 8015f58: af00 add r7, sp, #0 BaseType_t xReturn; if( xSchedulerRunning == pdFALSE ) 8015f5a: 4b0b ldr r3, [pc, #44] @ (8015f88 ) 8015f5c: 681b ldr r3, [r3, #0] 8015f5e: 2b00 cmp r3, #0 8015f60: d102 bne.n 8015f68 { xReturn = taskSCHEDULER_NOT_STARTED; 8015f62: 2301 movs r3, #1 8015f64: 607b str r3, [r7, #4] 8015f66: e008 b.n 8015f7a } else { if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8015f68: 4b08 ldr r3, [pc, #32] @ (8015f8c ) 8015f6a: 681b ldr r3, [r3, #0] 8015f6c: 2b00 cmp r3, #0 8015f6e: d102 bne.n 8015f76 { xReturn = taskSCHEDULER_RUNNING; 8015f70: 2302 movs r3, #2 8015f72: 607b str r3, [r7, #4] 8015f74: e001 b.n 8015f7a } else { xReturn = taskSCHEDULER_SUSPENDED; 8015f76: 2300 movs r3, #0 8015f78: 607b str r3, [r7, #4] } } return xReturn; 8015f7a: 687b ldr r3, [r7, #4] } 8015f7c: 4618 mov r0, r3 8015f7e: 370c adds r7, #12 8015f80: 46bd mov sp, r7 8015f82: f85d 7b04 ldr.w r7, [sp], #4 8015f86: 4770 bx lr 8015f88: 24002ef4 .word 0x24002ef4 8015f8c: 24002f10 .word 0x24002f10 08015f90 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) { 8015f90: b580 push {r7, lr} 8015f92: b084 sub sp, #16 8015f94: af00 add r7, sp, #0 8015f96: 6078 str r0, [r7, #4] TCB_t * const pxMutexHolderTCB = pxMutexHolder; 8015f98: 687b ldr r3, [r7, #4] 8015f9a: 60bb str r3, [r7, #8] BaseType_t xReturn = pdFALSE; 8015f9c: 2300 movs r3, #0 8015f9e: 60fb str r3, [r7, #12] /* If the mutex was given back by an interrupt while the queue was locked then the mutex holder might now be NULL. _RB_ Is this still needed as interrupts can no longer use mutexes? */ if( pxMutexHolder != NULL ) 8015fa0: 687b ldr r3, [r7, #4] 8015fa2: 2b00 cmp r3, #0 8015fa4: d051 beq.n 801604a { /* If the holder of the mutex has a priority below the priority of the task attempting to obtain the mutex then it will temporarily inherit the priority of the task attempting to obtain the mutex. */ if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) 8015fa6: 68bb ldr r3, [r7, #8] 8015fa8: 6ada ldr r2, [r3, #44] @ 0x2c 8015faa: 4b2a ldr r3, [pc, #168] @ (8016054 ) 8015fac: 681b ldr r3, [r3, #0] 8015fae: 6adb ldr r3, [r3, #44] @ 0x2c 8015fb0: 429a cmp r2, r3 8015fb2: d241 bcs.n 8016038 { /* Adjust the mutex holder state to account for its new priority. Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 8015fb4: 68bb ldr r3, [r7, #8] 8015fb6: 699b ldr r3, [r3, #24] 8015fb8: 2b00 cmp r3, #0 8015fba: db06 blt.n 8015fca { listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8015fbc: 4b25 ldr r3, [pc, #148] @ (8016054 ) 8015fbe: 681b ldr r3, [r3, #0] 8015fc0: 6adb ldr r3, [r3, #44] @ 0x2c 8015fc2: f1c3 0238 rsb r2, r3, #56 @ 0x38 8015fc6: 68bb ldr r3, [r7, #8] 8015fc8: 619a str r2, [r3, #24] mtCOVERAGE_TEST_MARKER(); } /* If the task being modified is in the ready state it will need to be moved into a new list. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) 8015fca: 68bb ldr r3, [r7, #8] 8015fcc: 6959 ldr r1, [r3, #20] 8015fce: 68bb ldr r3, [r7, #8] 8015fd0: 6ada ldr r2, [r3, #44] @ 0x2c 8015fd2: 4613 mov r3, r2 8015fd4: 009b lsls r3, r3, #2 8015fd6: 4413 add r3, r2 8015fd8: 009b lsls r3, r3, #2 8015fda: 4a1f ldr r2, [pc, #124] @ (8016058 ) 8015fdc: 4413 add r3, r2 8015fde: 4299 cmp r1, r3 8015fe0: d122 bne.n 8016028 { if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8015fe2: 68bb ldr r3, [r7, #8] 8015fe4: 3304 adds r3, #4 8015fe6: 4618 mov r0, r3 8015fe8: f7fd ff96 bl 8013f18 { mtCOVERAGE_TEST_MARKER(); } /* Inherit the priority before being moved into the new list. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8015fec: 4b19 ldr r3, [pc, #100] @ (8016054 ) 8015fee: 681b ldr r3, [r3, #0] 8015ff0: 6ada ldr r2, [r3, #44] @ 0x2c 8015ff2: 68bb ldr r3, [r7, #8] 8015ff4: 62da str r2, [r3, #44] @ 0x2c prvAddTaskToReadyList( pxMutexHolderTCB ); 8015ff6: 68bb ldr r3, [r7, #8] 8015ff8: 6ada ldr r2, [r3, #44] @ 0x2c 8015ffa: 4b18 ldr r3, [pc, #96] @ (801605c ) 8015ffc: 681b ldr r3, [r3, #0] 8015ffe: 429a cmp r2, r3 8016000: d903 bls.n 801600a 8016002: 68bb ldr r3, [r7, #8] 8016004: 6adb ldr r3, [r3, #44] @ 0x2c 8016006: 4a15 ldr r2, [pc, #84] @ (801605c ) 8016008: 6013 str r3, [r2, #0] 801600a: 68bb ldr r3, [r7, #8] 801600c: 6ada ldr r2, [r3, #44] @ 0x2c 801600e: 4613 mov r3, r2 8016010: 009b lsls r3, r3, #2 8016012: 4413 add r3, r2 8016014: 009b lsls r3, r3, #2 8016016: 4a10 ldr r2, [pc, #64] @ (8016058 ) 8016018: 441a add r2, r3 801601a: 68bb ldr r3, [r7, #8] 801601c: 3304 adds r3, #4 801601e: 4619 mov r1, r3 8016020: 4610 mov r0, r2 8016022: f7fd ff1c bl 8013e5e 8016026: e004 b.n 8016032 } else { /* Just inherit the priority. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8016028: 4b0a ldr r3, [pc, #40] @ (8016054 ) 801602a: 681b ldr r3, [r3, #0] 801602c: 6ada ldr r2, [r3, #44] @ 0x2c 801602e: 68bb ldr r3, [r7, #8] 8016030: 62da str r2, [r3, #44] @ 0x2c } traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); /* Inheritance occurred. */ xReturn = pdTRUE; 8016032: 2301 movs r3, #1 8016034: 60fb str r3, [r7, #12] 8016036: e008 b.n 801604a } else { if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) 8016038: 68bb ldr r3, [r7, #8] 801603a: 6cda ldr r2, [r3, #76] @ 0x4c 801603c: 4b05 ldr r3, [pc, #20] @ (8016054 ) 801603e: 681b ldr r3, [r3, #0] 8016040: 6adb ldr r3, [r3, #44] @ 0x2c 8016042: 429a cmp r2, r3 8016044: d201 bcs.n 801604a current priority of the mutex holder is not lower than the priority of the task attempting to take the mutex. Therefore the mutex holder must have already inherited a priority, but inheritance would have occurred if that had not been the case. */ xReturn = pdTRUE; 8016046: 2301 movs r3, #1 8016048: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 801604a: 68fb ldr r3, [r7, #12] } 801604c: 4618 mov r0, r3 801604e: 3710 adds r7, #16 8016050: 46bd mov sp, r7 8016052: bd80 pop {r7, pc} 8016054: 24002a14 .word 0x24002a14 8016058: 24002a18 .word 0x24002a18 801605c: 24002ef0 .word 0x24002ef0 08016060 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { 8016060: b580 push {r7, lr} 8016062: b086 sub sp, #24 8016064: af00 add r7, sp, #0 8016066: 6078 str r0, [r7, #4] TCB_t * const pxTCB = pxMutexHolder; 8016068: 687b ldr r3, [r7, #4] 801606a: 613b str r3, [r7, #16] BaseType_t xReturn = pdFALSE; 801606c: 2300 movs r3, #0 801606e: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 8016070: 687b ldr r3, [r7, #4] 8016072: 2b00 cmp r3, #0 8016074: d058 beq.n 8016128 { /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. */ configASSERT( pxTCB == pxCurrentTCB ); 8016076: 4b2f ldr r3, [pc, #188] @ (8016134 ) 8016078: 681b ldr r3, [r3, #0] 801607a: 693a ldr r2, [r7, #16] 801607c: 429a cmp r2, r3 801607e: d00b beq.n 8016098 __asm volatile 8016080: f04f 0350 mov.w r3, #80 @ 0x50 8016084: f383 8811 msr BASEPRI, r3 8016088: f3bf 8f6f isb sy 801608c: f3bf 8f4f dsb sy 8016090: 60fb str r3, [r7, #12] } 8016092: bf00 nop 8016094: bf00 nop 8016096: e7fd b.n 8016094 configASSERT( pxTCB->uxMutexesHeld ); 8016098: 693b ldr r3, [r7, #16] 801609a: 6d1b ldr r3, [r3, #80] @ 0x50 801609c: 2b00 cmp r3, #0 801609e: d10b bne.n 80160b8 __asm volatile 80160a0: f04f 0350 mov.w r3, #80 @ 0x50 80160a4: f383 8811 msr BASEPRI, r3 80160a8: f3bf 8f6f isb sy 80160ac: f3bf 8f4f dsb sy 80160b0: 60bb str r3, [r7, #8] } 80160b2: bf00 nop 80160b4: bf00 nop 80160b6: e7fd b.n 80160b4 ( pxTCB->uxMutexesHeld )--; 80160b8: 693b ldr r3, [r7, #16] 80160ba: 6d1b ldr r3, [r3, #80] @ 0x50 80160bc: 1e5a subs r2, r3, #1 80160be: 693b ldr r3, [r7, #16] 80160c0: 651a str r2, [r3, #80] @ 0x50 /* Has the holder of the mutex inherited the priority of another task? */ if( pxTCB->uxPriority != pxTCB->uxBasePriority ) 80160c2: 693b ldr r3, [r7, #16] 80160c4: 6ada ldr r2, [r3, #44] @ 0x2c 80160c6: 693b ldr r3, [r7, #16] 80160c8: 6cdb ldr r3, [r3, #76] @ 0x4c 80160ca: 429a cmp r2, r3 80160cc: d02c beq.n 8016128 { /* Only disinherit if no other mutexes are held. */ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) 80160ce: 693b ldr r3, [r7, #16] 80160d0: 6d1b ldr r3, [r3, #80] @ 0x50 80160d2: 2b00 cmp r3, #0 80160d4: d128 bne.n 8016128 /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. Remove the holding task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 80160d6: 693b ldr r3, [r7, #16] 80160d8: 3304 adds r3, #4 80160da: 4618 mov r0, r3 80160dc: f7fd ff1c bl 8013f18 } /* Disinherit the priority before adding the task into the new ready list. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); pxTCB->uxPriority = pxTCB->uxBasePriority; 80160e0: 693b ldr r3, [r7, #16] 80160e2: 6cda ldr r2, [r3, #76] @ 0x4c 80160e4: 693b ldr r3, [r7, #16] 80160e6: 62da str r2, [r3, #44] @ 0x2c /* Reset the event list item value. It cannot be in use for any other purpose if this task is running, and it must be running to give back the mutex. */ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 80160e8: 693b ldr r3, [r7, #16] 80160ea: 6adb ldr r3, [r3, #44] @ 0x2c 80160ec: f1c3 0238 rsb r2, r3, #56 @ 0x38 80160f0: 693b ldr r3, [r7, #16] 80160f2: 619a str r2, [r3, #24] prvAddTaskToReadyList( pxTCB ); 80160f4: 693b ldr r3, [r7, #16] 80160f6: 6ada ldr r2, [r3, #44] @ 0x2c 80160f8: 4b0f ldr r3, [pc, #60] @ (8016138 ) 80160fa: 681b ldr r3, [r3, #0] 80160fc: 429a cmp r2, r3 80160fe: d903 bls.n 8016108 8016100: 693b ldr r3, [r7, #16] 8016102: 6adb ldr r3, [r3, #44] @ 0x2c 8016104: 4a0c ldr r2, [pc, #48] @ (8016138 ) 8016106: 6013 str r3, [r2, #0] 8016108: 693b ldr r3, [r7, #16] 801610a: 6ada ldr r2, [r3, #44] @ 0x2c 801610c: 4613 mov r3, r2 801610e: 009b lsls r3, r3, #2 8016110: 4413 add r3, r2 8016112: 009b lsls r3, r3, #2 8016114: 4a09 ldr r2, [pc, #36] @ (801613c ) 8016116: 441a add r2, r3 8016118: 693b ldr r3, [r7, #16] 801611a: 3304 adds r3, #4 801611c: 4619 mov r1, r3 801611e: 4610 mov r0, r2 8016120: f7fd fe9d bl 8013e5e in an order different to that in which they were taken. If a context switch did not occur when the first mutex was returned, even if a task was waiting on it, then a context switch should occur when the last mutex is returned whether a task is waiting on it or not. */ xReturn = pdTRUE; 8016124: 2301 movs r3, #1 8016126: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8016128: 697b ldr r3, [r7, #20] } 801612a: 4618 mov r0, r3 801612c: 3718 adds r7, #24 801612e: 46bd mov sp, r7 8016130: bd80 pop {r7, pc} 8016132: bf00 nop 8016134: 24002a14 .word 0x24002a14 8016138: 24002ef0 .word 0x24002ef0 801613c: 24002a18 .word 0x24002a18 08016140 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) { 8016140: b580 push {r7, lr} 8016142: b088 sub sp, #32 8016144: af00 add r7, sp, #0 8016146: 6078 str r0, [r7, #4] 8016148: 6039 str r1, [r7, #0] TCB_t * const pxTCB = pxMutexHolder; 801614a: 687b ldr r3, [r7, #4] 801614c: 61bb str r3, [r7, #24] UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; 801614e: 2301 movs r3, #1 8016150: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 8016152: 687b ldr r3, [r7, #4] 8016154: 2b00 cmp r3, #0 8016156: d06c beq.n 8016232 { /* If pxMutexHolder is not NULL then the holder must hold at least one mutex. */ configASSERT( pxTCB->uxMutexesHeld ); 8016158: 69bb ldr r3, [r7, #24] 801615a: 6d1b ldr r3, [r3, #80] @ 0x50 801615c: 2b00 cmp r3, #0 801615e: d10b bne.n 8016178 __asm volatile 8016160: f04f 0350 mov.w r3, #80 @ 0x50 8016164: f383 8811 msr BASEPRI, r3 8016168: f3bf 8f6f isb sy 801616c: f3bf 8f4f dsb sy 8016170: 60fb str r3, [r7, #12] } 8016172: bf00 nop 8016174: bf00 nop 8016176: e7fd b.n 8016174 /* Determine the priority to which the priority of the task that holds the mutex should be set. This will be the greater of the holding task's base priority and the priority of the highest priority task that is waiting to obtain the mutex. */ if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) 8016178: 69bb ldr r3, [r7, #24] 801617a: 6cdb ldr r3, [r3, #76] @ 0x4c 801617c: 683a ldr r2, [r7, #0] 801617e: 429a cmp r2, r3 8016180: d902 bls.n 8016188 { uxPriorityToUse = uxHighestPriorityWaitingTask; 8016182: 683b ldr r3, [r7, #0] 8016184: 61fb str r3, [r7, #28] 8016186: e002 b.n 801618e } else { uxPriorityToUse = pxTCB->uxBasePriority; 8016188: 69bb ldr r3, [r7, #24] 801618a: 6cdb ldr r3, [r3, #76] @ 0x4c 801618c: 61fb str r3, [r7, #28] } /* Does the priority need to change? */ if( pxTCB->uxPriority != uxPriorityToUse ) 801618e: 69bb ldr r3, [r7, #24] 8016190: 6adb ldr r3, [r3, #44] @ 0x2c 8016192: 69fa ldr r2, [r7, #28] 8016194: 429a cmp r2, r3 8016196: d04c beq.n 8016232 { /* Only disinherit if no other mutexes are held. This is a simplification in the priority inheritance implementation. If the task that holds the mutex is also holding other mutexes then the other mutexes may have caused the priority inheritance. */ if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) 8016198: 69bb ldr r3, [r7, #24] 801619a: 6d1b ldr r3, [r3, #80] @ 0x50 801619c: 697a ldr r2, [r7, #20] 801619e: 429a cmp r2, r3 80161a0: d147 bne.n 8016232 { /* If a task has timed out because it already holds the mutex it was trying to obtain then it cannot of inherited its own priority. */ configASSERT( pxTCB != pxCurrentTCB ); 80161a2: 4b26 ldr r3, [pc, #152] @ (801623c ) 80161a4: 681b ldr r3, [r3, #0] 80161a6: 69ba ldr r2, [r7, #24] 80161a8: 429a cmp r2, r3 80161aa: d10b bne.n 80161c4 __asm volatile 80161ac: f04f 0350 mov.w r3, #80 @ 0x50 80161b0: f383 8811 msr BASEPRI, r3 80161b4: f3bf 8f6f isb sy 80161b8: f3bf 8f4f dsb sy 80161bc: 60bb str r3, [r7, #8] } 80161be: bf00 nop 80161c0: bf00 nop 80161c2: e7fd b.n 80161c0 /* Disinherit the priority, remembering the previous priority to facilitate determining the subject task's state. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); uxPriorityUsedOnEntry = pxTCB->uxPriority; 80161c4: 69bb ldr r3, [r7, #24] 80161c6: 6adb ldr r3, [r3, #44] @ 0x2c 80161c8: 613b str r3, [r7, #16] pxTCB->uxPriority = uxPriorityToUse; 80161ca: 69bb ldr r3, [r7, #24] 80161cc: 69fa ldr r2, [r7, #28] 80161ce: 62da str r2, [r3, #44] @ 0x2c /* Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 80161d0: 69bb ldr r3, [r7, #24] 80161d2: 699b ldr r3, [r3, #24] 80161d4: 2b00 cmp r3, #0 80161d6: db04 blt.n 80161e2 { listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 80161d8: 69fb ldr r3, [r7, #28] 80161da: f1c3 0238 rsb r2, r3, #56 @ 0x38 80161de: 69bb ldr r3, [r7, #24] 80161e0: 619a str r2, [r3, #24] then the task that holds the mutex could be in either the Ready, Blocked or Suspended states. Only remove the task from its current state list if it is in the Ready state as the task's priority is going to change and there is one Ready list per priority. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) 80161e2: 69bb ldr r3, [r7, #24] 80161e4: 6959 ldr r1, [r3, #20] 80161e6: 693a ldr r2, [r7, #16] 80161e8: 4613 mov r3, r2 80161ea: 009b lsls r3, r3, #2 80161ec: 4413 add r3, r2 80161ee: 009b lsls r3, r3, #2 80161f0: 4a13 ldr r2, [pc, #76] @ (8016240 ) 80161f2: 4413 add r3, r2 80161f4: 4299 cmp r1, r3 80161f6: d11c bne.n 8016232 { if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 80161f8: 69bb ldr r3, [r7, #24] 80161fa: 3304 adds r3, #4 80161fc: 4618 mov r0, r3 80161fe: f7fd fe8b bl 8013f18 else { mtCOVERAGE_TEST_MARKER(); } prvAddTaskToReadyList( pxTCB ); 8016202: 69bb ldr r3, [r7, #24] 8016204: 6ada ldr r2, [r3, #44] @ 0x2c 8016206: 4b0f ldr r3, [pc, #60] @ (8016244 ) 8016208: 681b ldr r3, [r3, #0] 801620a: 429a cmp r2, r3 801620c: d903 bls.n 8016216 801620e: 69bb ldr r3, [r7, #24] 8016210: 6adb ldr r3, [r3, #44] @ 0x2c 8016212: 4a0c ldr r2, [pc, #48] @ (8016244 ) 8016214: 6013 str r3, [r2, #0] 8016216: 69bb ldr r3, [r7, #24] 8016218: 6ada ldr r2, [r3, #44] @ 0x2c 801621a: 4613 mov r3, r2 801621c: 009b lsls r3, r3, #2 801621e: 4413 add r3, r2 8016220: 009b lsls r3, r3, #2 8016222: 4a07 ldr r2, [pc, #28] @ (8016240 ) 8016224: 441a add r2, r3 8016226: 69bb ldr r3, [r7, #24] 8016228: 3304 adds r3, #4 801622a: 4619 mov r1, r3 801622c: 4610 mov r0, r2 801622e: f7fd fe16 bl 8013e5e } else { mtCOVERAGE_TEST_MARKER(); } } 8016232: bf00 nop 8016234: 3720 adds r7, #32 8016236: 46bd mov sp, r7 8016238: bd80 pop {r7, pc} 801623a: bf00 nop 801623c: 24002a14 .word 0x24002a14 8016240: 24002a18 .word 0x24002a18 8016244: 24002ef0 .word 0x24002ef0 08016248 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) TaskHandle_t pvTaskIncrementMutexHeldCount( void ) { 8016248: b480 push {r7} 801624a: af00 add r7, sp, #0 /* If xSemaphoreCreateMutex() is called before any tasks have been created then pxCurrentTCB will be NULL. */ if( pxCurrentTCB != NULL ) 801624c: 4b07 ldr r3, [pc, #28] @ (801626c ) 801624e: 681b ldr r3, [r3, #0] 8016250: 2b00 cmp r3, #0 8016252: d004 beq.n 801625e { ( pxCurrentTCB->uxMutexesHeld )++; 8016254: 4b05 ldr r3, [pc, #20] @ (801626c ) 8016256: 681b ldr r3, [r3, #0] 8016258: 6d1a ldr r2, [r3, #80] @ 0x50 801625a: 3201 adds r2, #1 801625c: 651a str r2, [r3, #80] @ 0x50 } return pxCurrentTCB; 801625e: 4b03 ldr r3, [pc, #12] @ (801626c ) 8016260: 681b ldr r3, [r3, #0] } 8016262: 4618 mov r0, r3 8016264: 46bd mov sp, r7 8016266: f85d 7b04 ldr.w r7, [sp], #4 801626a: 4770 bx lr 801626c: 24002a14 .word 0x24002a14 08016270 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) { 8016270: b580 push {r7, lr} 8016272: b086 sub sp, #24 8016274: af00 add r7, sp, #0 8016276: 60f8 str r0, [r7, #12] 8016278: 60b9 str r1, [r7, #8] 801627a: 607a str r2, [r7, #4] 801627c: 603b str r3, [r7, #0] BaseType_t xReturn; taskENTER_CRITICAL(); 801627e: f000 ffeb bl 8017258 { /* Only block if a notification is not already pending. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 8016282: 4b29 ldr r3, [pc, #164] @ (8016328 ) 8016284: 681b ldr r3, [r3, #0] 8016286: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 801628a: b2db uxtb r3, r3 801628c: 2b02 cmp r3, #2 801628e: d01c beq.n 80162ca { /* Clear bits in the task's notification value as bits may get set by the notifying task or interrupt. This can be used to clear the value to zero. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry; 8016290: 4b25 ldr r3, [pc, #148] @ (8016328 ) 8016292: 681b ldr r3, [r3, #0] 8016294: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 8016298: 68fa ldr r2, [r7, #12] 801629a: 43d2 mvns r2, r2 801629c: 400a ands r2, r1 801629e: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 /* Mark this task as waiting for a notification. */ pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION; 80162a2: 4b21 ldr r3, [pc, #132] @ (8016328 ) 80162a4: 681b ldr r3, [r3, #0] 80162a6: 2201 movs r2, #1 80162a8: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 if( xTicksToWait > ( TickType_t ) 0 ) 80162ac: 683b ldr r3, [r7, #0] 80162ae: 2b00 cmp r3, #0 80162b0: d00b beq.n 80162ca { prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 80162b2: 2101 movs r1, #1 80162b4: 6838 ldr r0, [r7, #0] 80162b6: f000 fa09 bl 80166cc /* All ports are written to allow a yield in a critical section (some will yield immediately, others wait until the critical section exits) - but it is not something that application code should ever do. */ portYIELD_WITHIN_API(); 80162ba: 4b1c ldr r3, [pc, #112] @ (801632c ) 80162bc: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80162c0: 601a str r2, [r3, #0] 80162c2: f3bf 8f4f dsb sy 80162c6: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 80162ca: f000 fff7 bl 80172bc taskENTER_CRITICAL(); 80162ce: f000 ffc3 bl 8017258 { traceTASK_NOTIFY_WAIT(); if( pulNotificationValue != NULL ) 80162d2: 687b ldr r3, [r7, #4] 80162d4: 2b00 cmp r3, #0 80162d6: d005 beq.n 80162e4 { /* Output the current notification value, which may or may not have changed. */ *pulNotificationValue = pxCurrentTCB->ulNotifiedValue; 80162d8: 4b13 ldr r3, [pc, #76] @ (8016328 ) 80162da: 681b ldr r3, [r3, #0] 80162dc: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 80162e0: 687b ldr r3, [r7, #4] 80162e2: 601a str r2, [r3, #0] /* If ucNotifyValue is set then either the task never entered the blocked state (because a notification was already pending) or the task unblocked because of a notification. Otherwise the task unblocked because of a timeout. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 80162e4: 4b10 ldr r3, [pc, #64] @ (8016328 ) 80162e6: 681b ldr r3, [r3, #0] 80162e8: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 80162ec: b2db uxtb r3, r3 80162ee: 2b02 cmp r3, #2 80162f0: d002 beq.n 80162f8 { /* A notification was not received. */ xReturn = pdFALSE; 80162f2: 2300 movs r3, #0 80162f4: 617b str r3, [r7, #20] 80162f6: e00a b.n 801630e } else { /* A notification was already pending or a notification was received while the task was waiting. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit; 80162f8: 4b0b ldr r3, [pc, #44] @ (8016328 ) 80162fa: 681b ldr r3, [r3, #0] 80162fc: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 8016300: 68ba ldr r2, [r7, #8] 8016302: 43d2 mvns r2, r2 8016304: 400a ands r2, r1 8016306: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 xReturn = pdTRUE; 801630a: 2301 movs r3, #1 801630c: 617b str r3, [r7, #20] } pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 801630e: 4b06 ldr r3, [pc, #24] @ (8016328 ) 8016310: 681b ldr r3, [r3, #0] 8016312: 2200 movs r2, #0 8016314: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 } taskEXIT_CRITICAL(); 8016318: f000 ffd0 bl 80172bc return xReturn; 801631c: 697b ldr r3, [r7, #20] } 801631e: 4618 mov r0, r3 8016320: 3718 adds r7, #24 8016322: 46bd mov sp, r7 8016324: bd80 pop {r7, pc} 8016326: bf00 nop 8016328: 24002a14 .word 0x24002a14 801632c: e000ed04 .word 0xe000ed04 08016330 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) { 8016330: b580 push {r7, lr} 8016332: b08a sub sp, #40 @ 0x28 8016334: af00 add r7, sp, #0 8016336: 60f8 str r0, [r7, #12] 8016338: 60b9 str r1, [r7, #8] 801633a: 603b str r3, [r7, #0] 801633c: 4613 mov r3, r2 801633e: 71fb strb r3, [r7, #7] TCB_t * pxTCB; BaseType_t xReturn = pdPASS; 8016340: 2301 movs r3, #1 8016342: 627b str r3, [r7, #36] @ 0x24 uint8_t ucOriginalNotifyState; configASSERT( xTaskToNotify ); 8016344: 68fb ldr r3, [r7, #12] 8016346: 2b00 cmp r3, #0 8016348: d10b bne.n 8016362 __asm volatile 801634a: f04f 0350 mov.w r3, #80 @ 0x50 801634e: f383 8811 msr BASEPRI, r3 8016352: f3bf 8f6f isb sy 8016356: f3bf 8f4f dsb sy 801635a: 61bb str r3, [r7, #24] } 801635c: bf00 nop 801635e: bf00 nop 8016360: e7fd b.n 801635e pxTCB = xTaskToNotify; 8016362: 68fb ldr r3, [r7, #12] 8016364: 623b str r3, [r7, #32] taskENTER_CRITICAL(); 8016366: f000 ff77 bl 8017258 { if( pulPreviousNotificationValue != NULL ) 801636a: 683b ldr r3, [r7, #0] 801636c: 2b00 cmp r3, #0 801636e: d004 beq.n 801637a { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 8016370: 6a3b ldr r3, [r7, #32] 8016372: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016376: 683b ldr r3, [r7, #0] 8016378: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 801637a: 6a3b ldr r3, [r7, #32] 801637c: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016380: 77fb strb r3, [r7, #31] pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 8016382: 6a3b ldr r3, [r7, #32] 8016384: 2202 movs r2, #2 8016386: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 801638a: 79fb ldrb r3, [r7, #7] 801638c: 2b04 cmp r3, #4 801638e: d82e bhi.n 80163ee 8016390: a201 add r2, pc, #4 @ (adr r2, 8016398 ) 8016392: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016396: bf00 nop 8016398: 08016413 .word 0x08016413 801639c: 080163ad .word 0x080163ad 80163a0: 080163bf .word 0x080163bf 80163a4: 080163cf .word 0x080163cf 80163a8: 080163d9 .word 0x080163d9 { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 80163ac: 6a3b ldr r3, [r7, #32] 80163ae: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 80163b2: 68bb ldr r3, [r7, #8] 80163b4: 431a orrs r2, r3 80163b6: 6a3b ldr r3, [r7, #32] 80163b8: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 80163bc: e02c b.n 8016418 case eIncrement : ( pxTCB->ulNotifiedValue )++; 80163be: 6a3b ldr r3, [r7, #32] 80163c0: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 80163c4: 1c5a adds r2, r3, #1 80163c6: 6a3b ldr r3, [r7, #32] 80163c8: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 80163cc: e024 b.n 8016418 case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 80163ce: 6a3b ldr r3, [r7, #32] 80163d0: 68ba ldr r2, [r7, #8] 80163d2: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 80163d6: e01f b.n 8016418 case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 80163d8: 7ffb ldrb r3, [r7, #31] 80163da: 2b02 cmp r3, #2 80163dc: d004 beq.n 80163e8 { pxTCB->ulNotifiedValue = ulValue; 80163de: 6a3b ldr r3, [r7, #32] 80163e0: 68ba ldr r2, [r7, #8] 80163e2: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 80163e6: e017 b.n 8016418 xReturn = pdFAIL; 80163e8: 2300 movs r3, #0 80163ea: 627b str r3, [r7, #36] @ 0x24 break; 80163ec: e014 b.n 8016418 default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 80163ee: 6a3b ldr r3, [r7, #32] 80163f0: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 80163f4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80163f8: d00d beq.n 8016416 __asm volatile 80163fa: f04f 0350 mov.w r3, #80 @ 0x50 80163fe: f383 8811 msr BASEPRI, r3 8016402: f3bf 8f6f isb sy 8016406: f3bf 8f4f dsb sy 801640a: 617b str r3, [r7, #20] } 801640c: bf00 nop 801640e: bf00 nop 8016410: e7fd b.n 801640e break; 8016412: bf00 nop 8016414: e000 b.n 8016418 break; 8016416: bf00 nop traceTASK_NOTIFY(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 8016418: 7ffb ldrb r3, [r7, #31] 801641a: 2b01 cmp r3, #1 801641c: d13b bne.n 8016496 { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 801641e: 6a3b ldr r3, [r7, #32] 8016420: 3304 adds r3, #4 8016422: 4618 mov r0, r3 8016424: f7fd fd78 bl 8013f18 prvAddTaskToReadyList( pxTCB ); 8016428: 6a3b ldr r3, [r7, #32] 801642a: 6ada ldr r2, [r3, #44] @ 0x2c 801642c: 4b1d ldr r3, [pc, #116] @ (80164a4 ) 801642e: 681b ldr r3, [r3, #0] 8016430: 429a cmp r2, r3 8016432: d903 bls.n 801643c 8016434: 6a3b ldr r3, [r7, #32] 8016436: 6adb ldr r3, [r3, #44] @ 0x2c 8016438: 4a1a ldr r2, [pc, #104] @ (80164a4 ) 801643a: 6013 str r3, [r2, #0] 801643c: 6a3b ldr r3, [r7, #32] 801643e: 6ada ldr r2, [r3, #44] @ 0x2c 8016440: 4613 mov r3, r2 8016442: 009b lsls r3, r3, #2 8016444: 4413 add r3, r2 8016446: 009b lsls r3, r3, #2 8016448: 4a17 ldr r2, [pc, #92] @ (80164a8 ) 801644a: 441a add r2, r3 801644c: 6a3b ldr r3, [r7, #32] 801644e: 3304 adds r3, #4 8016450: 4619 mov r1, r3 8016452: 4610 mov r0, r2 8016454: f7fd fd03 bl 8013e5e /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 8016458: 6a3b ldr r3, [r7, #32] 801645a: 6a9b ldr r3, [r3, #40] @ 0x28 801645c: 2b00 cmp r3, #0 801645e: d00b beq.n 8016478 __asm volatile 8016460: f04f 0350 mov.w r3, #80 @ 0x50 8016464: f383 8811 msr BASEPRI, r3 8016468: f3bf 8f6f isb sy 801646c: f3bf 8f4f dsb sy 8016470: 613b str r3, [r7, #16] } 8016472: bf00 nop 8016474: bf00 nop 8016476: e7fd b.n 8016474 earliest possible time. */ prvResetNextTaskUnblockTime(); } #endif if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 8016478: 6a3b ldr r3, [r7, #32] 801647a: 6ada ldr r2, [r3, #44] @ 0x2c 801647c: 4b0b ldr r3, [pc, #44] @ (80164ac ) 801647e: 681b ldr r3, [r3, #0] 8016480: 6adb ldr r3, [r3, #44] @ 0x2c 8016482: 429a cmp r2, r3 8016484: d907 bls.n 8016496 { /* The notified task has a priority above the currently executing task so a yield is required. */ taskYIELD_IF_USING_PREEMPTION(); 8016486: 4b0a ldr r3, [pc, #40] @ (80164b0 ) 8016488: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801648c: 601a str r2, [r3, #0] 801648e: f3bf 8f4f dsb sy 8016492: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016496: f000 ff11 bl 80172bc return xReturn; 801649a: 6a7b ldr r3, [r7, #36] @ 0x24 } 801649c: 4618 mov r0, r3 801649e: 3728 adds r7, #40 @ 0x28 80164a0: 46bd mov sp, r7 80164a2: bd80 pop {r7, pc} 80164a4: 24002ef0 .word 0x24002ef0 80164a8: 24002a18 .word 0x24002a18 80164ac: 24002a14 .word 0x24002a14 80164b0: e000ed04 .word 0xe000ed04 080164b4 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) { 80164b4: b580 push {r7, lr} 80164b6: b08e sub sp, #56 @ 0x38 80164b8: af00 add r7, sp, #0 80164ba: 60f8 str r0, [r7, #12] 80164bc: 60b9 str r1, [r7, #8] 80164be: 603b str r3, [r7, #0] 80164c0: 4613 mov r3, r2 80164c2: 71fb strb r3, [r7, #7] TCB_t * pxTCB; uint8_t ucOriginalNotifyState; BaseType_t xReturn = pdPASS; 80164c4: 2301 movs r3, #1 80164c6: 637b str r3, [r7, #52] @ 0x34 UBaseType_t uxSavedInterruptStatus; configASSERT( xTaskToNotify ); 80164c8: 68fb ldr r3, [r7, #12] 80164ca: 2b00 cmp r3, #0 80164cc: d10b bne.n 80164e6 __asm volatile 80164ce: f04f 0350 mov.w r3, #80 @ 0x50 80164d2: f383 8811 msr BASEPRI, r3 80164d6: f3bf 8f6f isb sy 80164da: f3bf 8f4f dsb sy 80164de: 627b str r3, [r7, #36] @ 0x24 } 80164e0: bf00 nop 80164e2: bf00 nop 80164e4: e7fd b.n 80164e2 below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 80164e6: f000 ff97 bl 8017418 pxTCB = xTaskToNotify; 80164ea: 68fb ldr r3, [r7, #12] 80164ec: 633b str r3, [r7, #48] @ 0x30 __asm volatile 80164ee: f3ef 8211 mrs r2, BASEPRI 80164f2: f04f 0350 mov.w r3, #80 @ 0x50 80164f6: f383 8811 msr BASEPRI, r3 80164fa: f3bf 8f6f isb sy 80164fe: f3bf 8f4f dsb sy 8016502: 623a str r2, [r7, #32] 8016504: 61fb str r3, [r7, #28] return ulOriginalBASEPRI; 8016506: 6a3b ldr r3, [r7, #32] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8016508: 62fb str r3, [r7, #44] @ 0x2c { if( pulPreviousNotificationValue != NULL ) 801650a: 683b ldr r3, [r7, #0] 801650c: 2b00 cmp r3, #0 801650e: d004 beq.n 801651a { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 8016510: 6b3b ldr r3, [r7, #48] @ 0x30 8016512: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016516: 683b ldr r3, [r7, #0] 8016518: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 801651a: 6b3b ldr r3, [r7, #48] @ 0x30 801651c: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016520: f887 302b strb.w r3, [r7, #43] @ 0x2b pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 8016524: 6b3b ldr r3, [r7, #48] @ 0x30 8016526: 2202 movs r2, #2 8016528: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 801652c: 79fb ldrb r3, [r7, #7] 801652e: 2b04 cmp r3, #4 8016530: d82e bhi.n 8016590 8016532: a201 add r2, pc, #4 @ (adr r2, 8016538 ) 8016534: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016538: 080165b5 .word 0x080165b5 801653c: 0801654d .word 0x0801654d 8016540: 0801655f .word 0x0801655f 8016544: 0801656f .word 0x0801656f 8016548: 08016579 .word 0x08016579 { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 801654c: 6b3b ldr r3, [r7, #48] @ 0x30 801654e: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016552: 68bb ldr r3, [r7, #8] 8016554: 431a orrs r2, r3 8016556: 6b3b ldr r3, [r7, #48] @ 0x30 8016558: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 801655c: e02d b.n 80165ba case eIncrement : ( pxTCB->ulNotifiedValue )++; 801655e: 6b3b ldr r3, [r7, #48] @ 0x30 8016560: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016564: 1c5a adds r2, r3, #1 8016566: 6b3b ldr r3, [r7, #48] @ 0x30 8016568: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 801656c: e025 b.n 80165ba case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 801656e: 6b3b ldr r3, [r7, #48] @ 0x30 8016570: 68ba ldr r2, [r7, #8] 8016572: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016576: e020 b.n 80165ba case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 8016578: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 801657c: 2b02 cmp r3, #2 801657e: d004 beq.n 801658a { pxTCB->ulNotifiedValue = ulValue; 8016580: 6b3b ldr r3, [r7, #48] @ 0x30 8016582: 68ba ldr r2, [r7, #8] 8016584: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 8016588: e017 b.n 80165ba xReturn = pdFAIL; 801658a: 2300 movs r3, #0 801658c: 637b str r3, [r7, #52] @ 0x34 break; 801658e: e014 b.n 80165ba default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 8016590: 6b3b ldr r3, [r7, #48] @ 0x30 8016592: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016596: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801659a: d00d beq.n 80165b8 __asm volatile 801659c: f04f 0350 mov.w r3, #80 @ 0x50 80165a0: f383 8811 msr BASEPRI, r3 80165a4: f3bf 8f6f isb sy 80165a8: f3bf 8f4f dsb sy 80165ac: 61bb str r3, [r7, #24] } 80165ae: bf00 nop 80165b0: bf00 nop 80165b2: e7fd b.n 80165b0 break; 80165b4: bf00 nop 80165b6: e000 b.n 80165ba break; 80165b8: bf00 nop traceTASK_NOTIFY_FROM_ISR(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 80165ba: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 80165be: 2b01 cmp r3, #1 80165c0: d147 bne.n 8016652 { /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 80165c2: 6b3b ldr r3, [r7, #48] @ 0x30 80165c4: 6a9b ldr r3, [r3, #40] @ 0x28 80165c6: 2b00 cmp r3, #0 80165c8: d00b beq.n 80165e2 __asm volatile 80165ca: f04f 0350 mov.w r3, #80 @ 0x50 80165ce: f383 8811 msr BASEPRI, r3 80165d2: f3bf 8f6f isb sy 80165d6: f3bf 8f4f dsb sy 80165da: 617b str r3, [r7, #20] } 80165dc: bf00 nop 80165de: bf00 nop 80165e0: e7fd b.n 80165de if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80165e2: 4b21 ldr r3, [pc, #132] @ (8016668 ) 80165e4: 681b ldr r3, [r3, #0] 80165e6: 2b00 cmp r3, #0 80165e8: d11d bne.n 8016626 { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80165ea: 6b3b ldr r3, [r7, #48] @ 0x30 80165ec: 3304 adds r3, #4 80165ee: 4618 mov r0, r3 80165f0: f7fd fc92 bl 8013f18 prvAddTaskToReadyList( pxTCB ); 80165f4: 6b3b ldr r3, [r7, #48] @ 0x30 80165f6: 6ada ldr r2, [r3, #44] @ 0x2c 80165f8: 4b1c ldr r3, [pc, #112] @ (801666c ) 80165fa: 681b ldr r3, [r3, #0] 80165fc: 429a cmp r2, r3 80165fe: d903 bls.n 8016608 8016600: 6b3b ldr r3, [r7, #48] @ 0x30 8016602: 6adb ldr r3, [r3, #44] @ 0x2c 8016604: 4a19 ldr r2, [pc, #100] @ (801666c ) 8016606: 6013 str r3, [r2, #0] 8016608: 6b3b ldr r3, [r7, #48] @ 0x30 801660a: 6ada ldr r2, [r3, #44] @ 0x2c 801660c: 4613 mov r3, r2 801660e: 009b lsls r3, r3, #2 8016610: 4413 add r3, r2 8016612: 009b lsls r3, r3, #2 8016614: 4a16 ldr r2, [pc, #88] @ (8016670 ) 8016616: 441a add r2, r3 8016618: 6b3b ldr r3, [r7, #48] @ 0x30 801661a: 3304 adds r3, #4 801661c: 4619 mov r1, r3 801661e: 4610 mov r0, r2 8016620: f7fd fc1d bl 8013e5e 8016624: e005 b.n 8016632 } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); 8016626: 6b3b ldr r3, [r7, #48] @ 0x30 8016628: 3318 adds r3, #24 801662a: 4619 mov r1, r3 801662c: 4811 ldr r0, [pc, #68] @ (8016674 ) 801662e: f7fd fc16 bl 8013e5e } if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 8016632: 6b3b ldr r3, [r7, #48] @ 0x30 8016634: 6ada ldr r2, [r3, #44] @ 0x2c 8016636: 4b10 ldr r3, [pc, #64] @ (8016678 ) 8016638: 681b ldr r3, [r3, #0] 801663a: 6adb ldr r3, [r3, #44] @ 0x2c 801663c: 429a cmp r2, r3 801663e: d908 bls.n 8016652 { /* The notified task has a priority above the currently executing task so a yield is required. */ if( pxHigherPriorityTaskWoken != NULL ) 8016640: 6c3b ldr r3, [r7, #64] @ 0x40 8016642: 2b00 cmp r3, #0 8016644: d002 beq.n 801664c { *pxHigherPriorityTaskWoken = pdTRUE; 8016646: 6c3b ldr r3, [r7, #64] @ 0x40 8016648: 2201 movs r2, #1 801664a: 601a str r2, [r3, #0] } /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 801664c: 4b0b ldr r3, [pc, #44] @ (801667c ) 801664e: 2201 movs r2, #1 8016650: 601a str r2, [r3, #0] 8016652: 6afb ldr r3, [r7, #44] @ 0x2c 8016654: 613b str r3, [r7, #16] __asm volatile 8016656: 693b ldr r3, [r7, #16] 8016658: f383 8811 msr BASEPRI, r3 } 801665c: bf00 nop } } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 801665e: 6b7b ldr r3, [r7, #52] @ 0x34 } 8016660: 4618 mov r0, r3 8016662: 3738 adds r7, #56 @ 0x38 8016664: 46bd mov sp, r7 8016666: bd80 pop {r7, pc} 8016668: 24002f10 .word 0x24002f10 801666c: 24002ef0 .word 0x24002ef0 8016670: 24002a18 .word 0x24002a18 8016674: 24002ea8 .word 0x24002ea8 8016678: 24002a14 .word 0x24002a14 801667c: 24002efc .word 0x24002efc 08016680 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask ) { 8016680: b580 push {r7, lr} 8016682: b084 sub sp, #16 8016684: af00 add r7, sp, #0 8016686: 6078 str r0, [r7, #4] TCB_t *pxTCB; BaseType_t xReturn; /* If null is passed in here then it is the calling task that is having its notification state cleared. */ pxTCB = prvGetTCBFromHandle( xTask ); 8016688: 687b ldr r3, [r7, #4] 801668a: 2b00 cmp r3, #0 801668c: d102 bne.n 8016694 801668e: 4b0e ldr r3, [pc, #56] @ (80166c8 ) 8016690: 681b ldr r3, [r3, #0] 8016692: e000 b.n 8016696 8016694: 687b ldr r3, [r7, #4] 8016696: 60bb str r3, [r7, #8] taskENTER_CRITICAL(); 8016698: f000 fdde bl 8017258 { if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED ) 801669c: 68bb ldr r3, [r7, #8] 801669e: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 80166a2: b2db uxtb r3, r3 80166a4: 2b02 cmp r3, #2 80166a6: d106 bne.n 80166b6 { pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 80166a8: 68bb ldr r3, [r7, #8] 80166aa: 2200 movs r2, #0 80166ac: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 xReturn = pdPASS; 80166b0: 2301 movs r3, #1 80166b2: 60fb str r3, [r7, #12] 80166b4: e001 b.n 80166ba } else { xReturn = pdFAIL; 80166b6: 2300 movs r3, #0 80166b8: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 80166ba: f000 fdff bl 80172bc return xReturn; 80166be: 68fb ldr r3, [r7, #12] } 80166c0: 4618 mov r0, r3 80166c2: 3710 adds r7, #16 80166c4: 46bd mov sp, r7 80166c6: bd80 pop {r7, pc} 80166c8: 24002a14 .word 0x24002a14 080166cc : #endif /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { 80166cc: b580 push {r7, lr} 80166ce: b084 sub sp, #16 80166d0: af00 add r7, sp, #0 80166d2: 6078 str r0, [r7, #4] 80166d4: 6039 str r1, [r7, #0] TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; 80166d6: 4b21 ldr r3, [pc, #132] @ (801675c ) 80166d8: 681b ldr r3, [r3, #0] 80166da: 60fb str r3, [r7, #12] } #endif /* Remove the task from the ready list before adding it to the blocked list as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 80166dc: 4b20 ldr r3, [pc, #128] @ (8016760 ) 80166de: 681b ldr r3, [r3, #0] 80166e0: 3304 adds r3, #4 80166e2: 4618 mov r0, r3 80166e4: f7fd fc18 bl 8013f18 mtCOVERAGE_TEST_MARKER(); } #if ( INCLUDE_vTaskSuspend == 1 ) { if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) 80166e8: 687b ldr r3, [r7, #4] 80166ea: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80166ee: d10a bne.n 8016706 80166f0: 683b ldr r3, [r7, #0] 80166f2: 2b00 cmp r3, #0 80166f4: d007 beq.n 8016706 { /* Add the task to the suspended task list instead of a delayed task list to ensure it is not woken by a timing event. It will block indefinitely. */ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 80166f6: 4b1a ldr r3, [pc, #104] @ (8016760 ) 80166f8: 681b ldr r3, [r3, #0] 80166fa: 3304 adds r3, #4 80166fc: 4619 mov r1, r3 80166fe: 4819 ldr r0, [pc, #100] @ (8016764 ) 8016700: f7fd fbad bl 8013e5e /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } 8016704: e026 b.n 8016754 xTimeToWake = xConstTickCount + xTicksToWait; 8016706: 68fa ldr r2, [r7, #12] 8016708: 687b ldr r3, [r7, #4] 801670a: 4413 add r3, r2 801670c: 60bb str r3, [r7, #8] listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 801670e: 4b14 ldr r3, [pc, #80] @ (8016760 ) 8016710: 681b ldr r3, [r3, #0] 8016712: 68ba ldr r2, [r7, #8] 8016714: 605a str r2, [r3, #4] if( xTimeToWake < xConstTickCount ) 8016716: 68ba ldr r2, [r7, #8] 8016718: 68fb ldr r3, [r7, #12] 801671a: 429a cmp r2, r3 801671c: d209 bcs.n 8016732 vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 801671e: 4b12 ldr r3, [pc, #72] @ (8016768 ) 8016720: 681a ldr r2, [r3, #0] 8016722: 4b0f ldr r3, [pc, #60] @ (8016760 ) 8016724: 681b ldr r3, [r3, #0] 8016726: 3304 adds r3, #4 8016728: 4619 mov r1, r3 801672a: 4610 mov r0, r2 801672c: f7fd fbbb bl 8013ea6 } 8016730: e010 b.n 8016754 vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8016732: 4b0e ldr r3, [pc, #56] @ (801676c ) 8016734: 681a ldr r2, [r3, #0] 8016736: 4b0a ldr r3, [pc, #40] @ (8016760 ) 8016738: 681b ldr r3, [r3, #0] 801673a: 3304 adds r3, #4 801673c: 4619 mov r1, r3 801673e: 4610 mov r0, r2 8016740: f7fd fbb1 bl 8013ea6 if( xTimeToWake < xNextTaskUnblockTime ) 8016744: 4b0a ldr r3, [pc, #40] @ (8016770 ) 8016746: 681b ldr r3, [r3, #0] 8016748: 68ba ldr r2, [r7, #8] 801674a: 429a cmp r2, r3 801674c: d202 bcs.n 8016754 xNextTaskUnblockTime = xTimeToWake; 801674e: 4a08 ldr r2, [pc, #32] @ (8016770 ) 8016750: 68bb ldr r3, [r7, #8] 8016752: 6013 str r3, [r2, #0] } 8016754: bf00 nop 8016756: 3710 adds r7, #16 8016758: 46bd mov sp, r7 801675a: bd80 pop {r7, pc} 801675c: 24002eec .word 0x24002eec 8016760: 24002a14 .word 0x24002a14 8016764: 24002ed4 .word 0x24002ed4 8016768: 24002ea4 .word 0x24002ea4 801676c: 24002ea0 .word 0x24002ea0 8016770: 24002f08 .word 0x24002f08 08016774 : TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ BaseType_t xTimerCreateTimerTask( void ) { 8016774: b580 push {r7, lr} 8016776: b08a sub sp, #40 @ 0x28 8016778: af04 add r7, sp, #16 BaseType_t xReturn = pdFAIL; 801677a: 2300 movs r3, #0 801677c: 617b str r3, [r7, #20] /* This function is called when the scheduler is started if configUSE_TIMERS is set to 1. Check that the infrastructure used by the timer service task has been created/initialised. If timers have already been created then the initialisation will already have been performed. */ prvCheckForValidListAndQueue(); 801677e: f000 fbb1 bl 8016ee4 if( xTimerQueue != NULL ) 8016782: 4b1d ldr r3, [pc, #116] @ (80167f8 ) 8016784: 681b ldr r3, [r3, #0] 8016786: 2b00 cmp r3, #0 8016788: d021 beq.n 80167ce { #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxTimerTaskTCBBuffer = NULL; 801678a: 2300 movs r3, #0 801678c: 60fb str r3, [r7, #12] StackType_t *pxTimerTaskStackBuffer = NULL; 801678e: 2300 movs r3, #0 8016790: 60bb str r3, [r7, #8] uint32_t ulTimerTaskStackSize; vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); 8016792: 1d3a adds r2, r7, #4 8016794: f107 0108 add.w r1, r7, #8 8016798: f107 030c add.w r3, r7, #12 801679c: 4618 mov r0, r3 801679e: f7fd fb17 bl 8013dd0 xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, 80167a2: 6879 ldr r1, [r7, #4] 80167a4: 68bb ldr r3, [r7, #8] 80167a6: 68fa ldr r2, [r7, #12] 80167a8: 9202 str r2, [sp, #8] 80167aa: 9301 str r3, [sp, #4] 80167ac: 2302 movs r3, #2 80167ae: 9300 str r3, [sp, #0] 80167b0: 2300 movs r3, #0 80167b2: 460a mov r2, r1 80167b4: 4911 ldr r1, [pc, #68] @ (80167fc ) 80167b6: 4812 ldr r0, [pc, #72] @ (8016800 ) 80167b8: f7fe fd2f bl 801521a 80167bc: 4603 mov r3, r0 80167be: 4a11 ldr r2, [pc, #68] @ (8016804 ) 80167c0: 6013 str r3, [r2, #0] NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, pxTimerTaskStackBuffer, pxTimerTaskTCBBuffer ); if( xTimerTaskHandle != NULL ) 80167c2: 4b10 ldr r3, [pc, #64] @ (8016804 ) 80167c4: 681b ldr r3, [r3, #0] 80167c6: 2b00 cmp r3, #0 80167c8: d001 beq.n 80167ce { xReturn = pdPASS; 80167ca: 2301 movs r3, #1 80167cc: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } configASSERT( xReturn ); 80167ce: 697b ldr r3, [r7, #20] 80167d0: 2b00 cmp r3, #0 80167d2: d10b bne.n 80167ec __asm volatile 80167d4: f04f 0350 mov.w r3, #80 @ 0x50 80167d8: f383 8811 msr BASEPRI, r3 80167dc: f3bf 8f6f isb sy 80167e0: f3bf 8f4f dsb sy 80167e4: 613b str r3, [r7, #16] } 80167e6: bf00 nop 80167e8: bf00 nop 80167ea: e7fd b.n 80167e8 return xReturn; 80167ec: 697b ldr r3, [r7, #20] } 80167ee: 4618 mov r0, r3 80167f0: 3718 adds r7, #24 80167f2: 46bd mov sp, r7 80167f4: bd80 pop {r7, pc} 80167f6: bf00 nop 80167f8: 24002f44 .word 0x24002f44 80167fc: 08018ae8 .word 0x08018ae8 8016800: 08016a7d .word 0x08016a7d 8016804: 24002f48 .word 0x24002f48 08016808 : TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) { 8016808: b580 push {r7, lr} 801680a: b088 sub sp, #32 801680c: af02 add r7, sp, #8 801680e: 60f8 str r0, [r7, #12] 8016810: 60b9 str r1, [r7, #8] 8016812: 607a str r2, [r7, #4] 8016814: 603b str r3, [r7, #0] Timer_t *pxNewTimer; pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */ 8016816: 202c movs r0, #44 @ 0x2c 8016818: f000 fe40 bl 801749c 801681c: 6178 str r0, [r7, #20] if( pxNewTimer != NULL ) 801681e: 697b ldr r3, [r7, #20] 8016820: 2b00 cmp r3, #0 8016822: d00d beq.n 8016840 { /* Status is thus far zero as the timer is not created statically and has not been started. The auto-reload bit may get set in prvInitialiseNewTimer. */ pxNewTimer->ucStatus = 0x00; 8016824: 697b ldr r3, [r7, #20] 8016826: 2200 movs r2, #0 8016828: f883 2028 strb.w r2, [r3, #40] @ 0x28 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); 801682c: 697b ldr r3, [r7, #20] 801682e: 9301 str r3, [sp, #4] 8016830: 6a3b ldr r3, [r7, #32] 8016832: 9300 str r3, [sp, #0] 8016834: 683b ldr r3, [r7, #0] 8016836: 687a ldr r2, [r7, #4] 8016838: 68b9 ldr r1, [r7, #8] 801683a: 68f8 ldr r0, [r7, #12] 801683c: f000 f845 bl 80168ca } return pxNewTimer; 8016840: 697b ldr r3, [r7, #20] } 8016842: 4618 mov r0, r3 8016844: 3718 adds r7, #24 8016846: 46bd mov sp, r7 8016848: bd80 pop {r7, pc} 0801684a : const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) { 801684a: b580 push {r7, lr} 801684c: b08a sub sp, #40 @ 0x28 801684e: af02 add r7, sp, #8 8016850: 60f8 str r0, [r7, #12] 8016852: 60b9 str r1, [r7, #8] 8016854: 607a str r2, [r7, #4] 8016856: 603b str r3, [r7, #0] #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTimer_t equals the size of the real timer structure. */ volatile size_t xSize = sizeof( StaticTimer_t ); 8016858: 232c movs r3, #44 @ 0x2c 801685a: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( Timer_t ) ); 801685c: 693b ldr r3, [r7, #16] 801685e: 2b2c cmp r3, #44 @ 0x2c 8016860: d00b beq.n 801687a __asm volatile 8016862: f04f 0350 mov.w r3, #80 @ 0x50 8016866: f383 8811 msr BASEPRI, r3 801686a: f3bf 8f6f isb sy 801686e: f3bf 8f4f dsb sy 8016872: 61bb str r3, [r7, #24] } 8016874: bf00 nop 8016876: bf00 nop 8016878: e7fd b.n 8016876 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 801687a: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ /* A pointer to a StaticTimer_t structure MUST be provided, use it. */ configASSERT( pxTimerBuffer ); 801687c: 6afb ldr r3, [r7, #44] @ 0x2c 801687e: 2b00 cmp r3, #0 8016880: d10b bne.n 801689a __asm volatile 8016882: f04f 0350 mov.w r3, #80 @ 0x50 8016886: f383 8811 msr BASEPRI, r3 801688a: f3bf 8f6f isb sy 801688e: f3bf 8f4f dsb sy 8016892: 617b str r3, [r7, #20] } 8016894: bf00 nop 8016896: bf00 nop 8016898: e7fd b.n 8016896 pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */ 801689a: 6afb ldr r3, [r7, #44] @ 0x2c 801689c: 61fb str r3, [r7, #28] if( pxNewTimer != NULL ) 801689e: 69fb ldr r3, [r7, #28] 80168a0: 2b00 cmp r3, #0 80168a2: d00d beq.n 80168c0 { /* Timers can be created statically or dynamically so note this timer was created statically in case it is later deleted. The auto-reload bit may get set in prvInitialiseNewTimer(). */ pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED; 80168a4: 69fb ldr r3, [r7, #28] 80168a6: 2202 movs r2, #2 80168a8: f883 2028 strb.w r2, [r3, #40] @ 0x28 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); 80168ac: 69fb ldr r3, [r7, #28] 80168ae: 9301 str r3, [sp, #4] 80168b0: 6abb ldr r3, [r7, #40] @ 0x28 80168b2: 9300 str r3, [sp, #0] 80168b4: 683b ldr r3, [r7, #0] 80168b6: 687a ldr r2, [r7, #4] 80168b8: 68b9 ldr r1, [r7, #8] 80168ba: 68f8 ldr r0, [r7, #12] 80168bc: f000 f805 bl 80168ca } return pxNewTimer; 80168c0: 69fb ldr r3, [r7, #28] } 80168c2: 4618 mov r0, r3 80168c4: 3720 adds r7, #32 80168c6: 46bd mov sp, r7 80168c8: bd80 pop {r7, pc} 080168ca : const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) { 80168ca: b580 push {r7, lr} 80168cc: b086 sub sp, #24 80168ce: af00 add r7, sp, #0 80168d0: 60f8 str r0, [r7, #12] 80168d2: 60b9 str r1, [r7, #8] 80168d4: 607a str r2, [r7, #4] 80168d6: 603b str r3, [r7, #0] /* 0 is not a valid value for xTimerPeriodInTicks. */ configASSERT( ( xTimerPeriodInTicks > 0 ) ); 80168d8: 68bb ldr r3, [r7, #8] 80168da: 2b00 cmp r3, #0 80168dc: d10b bne.n 80168f6 __asm volatile 80168de: f04f 0350 mov.w r3, #80 @ 0x50 80168e2: f383 8811 msr BASEPRI, r3 80168e6: f3bf 8f6f isb sy 80168ea: f3bf 8f4f dsb sy 80168ee: 617b str r3, [r7, #20] } 80168f0: bf00 nop 80168f2: bf00 nop 80168f4: e7fd b.n 80168f2 if( pxNewTimer != NULL ) 80168f6: 6a7b ldr r3, [r7, #36] @ 0x24 80168f8: 2b00 cmp r3, #0 80168fa: d01e beq.n 801693a { /* Ensure the infrastructure used by the timer service task has been created/initialised. */ prvCheckForValidListAndQueue(); 80168fc: f000 faf2 bl 8016ee4 /* Initialise the timer structure members using the function parameters. */ pxNewTimer->pcTimerName = pcTimerName; 8016900: 6a7b ldr r3, [r7, #36] @ 0x24 8016902: 68fa ldr r2, [r7, #12] 8016904: 601a str r2, [r3, #0] pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks; 8016906: 6a7b ldr r3, [r7, #36] @ 0x24 8016908: 68ba ldr r2, [r7, #8] 801690a: 619a str r2, [r3, #24] pxNewTimer->pvTimerID = pvTimerID; 801690c: 6a7b ldr r3, [r7, #36] @ 0x24 801690e: 683a ldr r2, [r7, #0] 8016910: 61da str r2, [r3, #28] pxNewTimer->pxCallbackFunction = pxCallbackFunction; 8016912: 6a7b ldr r3, [r7, #36] @ 0x24 8016914: 6a3a ldr r2, [r7, #32] 8016916: 621a str r2, [r3, #32] vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); 8016918: 6a7b ldr r3, [r7, #36] @ 0x24 801691a: 3304 adds r3, #4 801691c: 4618 mov r0, r3 801691e: f7fd fa91 bl 8013e44 if( uxAutoReload != pdFALSE ) 8016922: 687b ldr r3, [r7, #4] 8016924: 2b00 cmp r3, #0 8016926: d008 beq.n 801693a { pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; 8016928: 6a7b ldr r3, [r7, #36] @ 0x24 801692a: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 801692e: f043 0304 orr.w r3, r3, #4 8016932: b2da uxtb r2, r3 8016934: 6a7b ldr r3, [r7, #36] @ 0x24 8016936: f883 2028 strb.w r2, [r3, #40] @ 0x28 } traceTIMER_CREATE( pxNewTimer ); } } 801693a: bf00 nop 801693c: 3718 adds r7, #24 801693e: 46bd mov sp, r7 8016940: bd80 pop {r7, pc} ... 08016944 : /*-----------------------------------------------------------*/ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) { 8016944: b580 push {r7, lr} 8016946: b08a sub sp, #40 @ 0x28 8016948: af00 add r7, sp, #0 801694a: 60f8 str r0, [r7, #12] 801694c: 60b9 str r1, [r7, #8] 801694e: 607a str r2, [r7, #4] 8016950: 603b str r3, [r7, #0] BaseType_t xReturn = pdFAIL; 8016952: 2300 movs r3, #0 8016954: 627b str r3, [r7, #36] @ 0x24 DaemonTaskMessage_t xMessage; configASSERT( xTimer ); 8016956: 68fb ldr r3, [r7, #12] 8016958: 2b00 cmp r3, #0 801695a: d10b bne.n 8016974 __asm volatile 801695c: f04f 0350 mov.w r3, #80 @ 0x50 8016960: f383 8811 msr BASEPRI, r3 8016964: f3bf 8f6f isb sy 8016968: f3bf 8f4f dsb sy 801696c: 623b str r3, [r7, #32] } 801696e: bf00 nop 8016970: bf00 nop 8016972: e7fd b.n 8016970 /* Send a message to the timer service task to perform a particular action on a particular timer definition. */ if( xTimerQueue != NULL ) 8016974: 4b19 ldr r3, [pc, #100] @ (80169dc ) 8016976: 681b ldr r3, [r3, #0] 8016978: 2b00 cmp r3, #0 801697a: d02a beq.n 80169d2 { /* Send a command to the timer service task to start the xTimer timer. */ xMessage.xMessageID = xCommandID; 801697c: 68bb ldr r3, [r7, #8] 801697e: 613b str r3, [r7, #16] xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; 8016980: 687b ldr r3, [r7, #4] 8016982: 617b str r3, [r7, #20] xMessage.u.xTimerParameters.pxTimer = xTimer; 8016984: 68fb ldr r3, [r7, #12] 8016986: 61bb str r3, [r7, #24] if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) 8016988: 68bb ldr r3, [r7, #8] 801698a: 2b05 cmp r3, #5 801698c: dc18 bgt.n 80169c0 { if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) 801698e: f7ff fae1 bl 8015f54 8016992: 4603 mov r3, r0 8016994: 2b02 cmp r3, #2 8016996: d109 bne.n 80169ac { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); 8016998: 4b10 ldr r3, [pc, #64] @ (80169dc ) 801699a: 6818 ldr r0, [r3, #0] 801699c: f107 0110 add.w r1, r7, #16 80169a0: 2300 movs r3, #0 80169a2: 6b3a ldr r2, [r7, #48] @ 0x30 80169a4: f7fd fce0 bl 8014368 80169a8: 6278 str r0, [r7, #36] @ 0x24 80169aa: e012 b.n 80169d2 } else { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); 80169ac: 4b0b ldr r3, [pc, #44] @ (80169dc ) 80169ae: 6818 ldr r0, [r3, #0] 80169b0: f107 0110 add.w r1, r7, #16 80169b4: 2300 movs r3, #0 80169b6: 2200 movs r2, #0 80169b8: f7fd fcd6 bl 8014368 80169bc: 6278 str r0, [r7, #36] @ 0x24 80169be: e008 b.n 80169d2 } } else { xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); 80169c0: 4b06 ldr r3, [pc, #24] @ (80169dc ) 80169c2: 6818 ldr r0, [r3, #0] 80169c4: f107 0110 add.w r1, r7, #16 80169c8: 2300 movs r3, #0 80169ca: 683a ldr r2, [r7, #0] 80169cc: f7fd fdce bl 801456c 80169d0: 6278 str r0, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 80169d2: 6a7b ldr r3, [r7, #36] @ 0x24 } 80169d4: 4618 mov r0, r3 80169d6: 3728 adds r7, #40 @ 0x28 80169d8: 46bd mov sp, r7 80169da: bd80 pop {r7, pc} 80169dc: 24002f44 .word 0x24002f44 080169e0 : return pxTimer->pcTimerName; } /*-----------------------------------------------------------*/ static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) { 80169e0: b580 push {r7, lr} 80169e2: b088 sub sp, #32 80169e4: af02 add r7, sp, #8 80169e6: 6078 str r0, [r7, #4] 80169e8: 6039 str r1, [r7, #0] BaseType_t xResult; Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80169ea: 4b23 ldr r3, [pc, #140] @ (8016a78 ) 80169ec: 681b ldr r3, [r3, #0] 80169ee: 68db ldr r3, [r3, #12] 80169f0: 68db ldr r3, [r3, #12] 80169f2: 617b str r3, [r7, #20] /* Remove the timer from the list of active timers. A check has already been performed to ensure the list is not empty. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 80169f4: 697b ldr r3, [r7, #20] 80169f6: 3304 adds r3, #4 80169f8: 4618 mov r0, r3 80169fa: f7fd fa8d bl 8013f18 traceTIMER_EXPIRED( pxTimer ); /* If the timer is an auto-reload timer then calculate the next expiry time and re-insert the timer in the list of active timers. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 80169fe: 697b ldr r3, [r7, #20] 8016a00: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016a04: f003 0304 and.w r3, r3, #4 8016a08: 2b00 cmp r3, #0 8016a0a: d023 beq.n 8016a54 { /* The timer is inserted into a list using a time relative to anything other than the current time. It will therefore be inserted into the correct list relative to the time this task thinks it is now. */ if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) 8016a0c: 697b ldr r3, [r7, #20] 8016a0e: 699a ldr r2, [r3, #24] 8016a10: 687b ldr r3, [r7, #4] 8016a12: 18d1 adds r1, r2, r3 8016a14: 687b ldr r3, [r7, #4] 8016a16: 683a ldr r2, [r7, #0] 8016a18: 6978 ldr r0, [r7, #20] 8016a1a: f000 f8d5 bl 8016bc8 8016a1e: 4603 mov r3, r0 8016a20: 2b00 cmp r3, #0 8016a22: d020 beq.n 8016a66 { /* The timer expired before it was added to the active timer list. Reload it now. */ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 8016a24: 2300 movs r3, #0 8016a26: 9300 str r3, [sp, #0] 8016a28: 2300 movs r3, #0 8016a2a: 687a ldr r2, [r7, #4] 8016a2c: 2100 movs r1, #0 8016a2e: 6978 ldr r0, [r7, #20] 8016a30: f7ff ff88 bl 8016944 8016a34: 6138 str r0, [r7, #16] configASSERT( xResult ); 8016a36: 693b ldr r3, [r7, #16] 8016a38: 2b00 cmp r3, #0 8016a3a: d114 bne.n 8016a66 __asm volatile 8016a3c: f04f 0350 mov.w r3, #80 @ 0x50 8016a40: f383 8811 msr BASEPRI, r3 8016a44: f3bf 8f6f isb sy 8016a48: f3bf 8f4f dsb sy 8016a4c: 60fb str r3, [r7, #12] } 8016a4e: bf00 nop 8016a50: bf00 nop 8016a52: e7fd b.n 8016a50 mtCOVERAGE_TEST_MARKER(); } } else { pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8016a54: 697b ldr r3, [r7, #20] 8016a56: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016a5a: f023 0301 bic.w r3, r3, #1 8016a5e: b2da uxtb r2, r3 8016a60: 697b ldr r3, [r7, #20] 8016a62: f883 2028 strb.w r2, [r3, #40] @ 0x28 mtCOVERAGE_TEST_MARKER(); } /* Call the timer callback. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8016a66: 697b ldr r3, [r7, #20] 8016a68: 6a1b ldr r3, [r3, #32] 8016a6a: 6978 ldr r0, [r7, #20] 8016a6c: 4798 blx r3 } 8016a6e: bf00 nop 8016a70: 3718 adds r7, #24 8016a72: 46bd mov sp, r7 8016a74: bd80 pop {r7, pc} 8016a76: bf00 nop 8016a78: 24002f3c .word 0x24002f3c 08016a7c : /*-----------------------------------------------------------*/ static portTASK_FUNCTION( prvTimerTask, pvParameters ) { 8016a7c: b580 push {r7, lr} 8016a7e: b084 sub sp, #16 8016a80: af00 add r7, sp, #0 8016a82: 6078 str r0, [r7, #4] for( ;; ) { /* Query the timers list to see if it contains any timers, and if so, obtain the time at which the next timer will expire. */ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8016a84: f107 0308 add.w r3, r7, #8 8016a88: 4618 mov r0, r3 8016a8a: f000 f859 bl 8016b40 8016a8e: 60f8 str r0, [r7, #12] /* If a timer has expired, process it. Otherwise, block this task until either a timer does expire, or a command is received. */ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); 8016a90: 68bb ldr r3, [r7, #8] 8016a92: 4619 mov r1, r3 8016a94: 68f8 ldr r0, [r7, #12] 8016a96: f000 f805 bl 8016aa4 /* Empty the command queue. */ prvProcessReceivedCommands(); 8016a9a: f000 f8d7 bl 8016c4c xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8016a9e: bf00 nop 8016aa0: e7f0 b.n 8016a84 ... 08016aa4 : } } /*-----------------------------------------------------------*/ static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) { 8016aa4: b580 push {r7, lr} 8016aa6: b084 sub sp, #16 8016aa8: af00 add r7, sp, #0 8016aaa: 6078 str r0, [r7, #4] 8016aac: 6039 str r1, [r7, #0] TickType_t xTimeNow; BaseType_t xTimerListsWereSwitched; vTaskSuspendAll(); 8016aae: f7fe fe17 bl 80156e0 /* Obtain the time now to make an assessment as to whether the timer has expired or not. If obtaining the time causes the lists to switch then don't process this timer as any timers that remained in the list when the lists were switched will have been processed within the prvSampleTimeNow() function. */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8016ab2: f107 0308 add.w r3, r7, #8 8016ab6: 4618 mov r0, r3 8016ab8: f000 f866 bl 8016b88 8016abc: 60f8 str r0, [r7, #12] if( xTimerListsWereSwitched == pdFALSE ) 8016abe: 68bb ldr r3, [r7, #8] 8016ac0: 2b00 cmp r3, #0 8016ac2: d130 bne.n 8016b26 { /* The tick count has not overflowed, has the timer expired? */ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) 8016ac4: 683b ldr r3, [r7, #0] 8016ac6: 2b00 cmp r3, #0 8016ac8: d10a bne.n 8016ae0 8016aca: 687a ldr r2, [r7, #4] 8016acc: 68fb ldr r3, [r7, #12] 8016ace: 429a cmp r2, r3 8016ad0: d806 bhi.n 8016ae0 { ( void ) xTaskResumeAll(); 8016ad2: f7fe fe13 bl 80156fc prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); 8016ad6: 68f9 ldr r1, [r7, #12] 8016ad8: 6878 ldr r0, [r7, #4] 8016ada: f7ff ff81 bl 80169e0 else { ( void ) xTaskResumeAll(); } } } 8016ade: e024 b.n 8016b2a if( xListWasEmpty != pdFALSE ) 8016ae0: 683b ldr r3, [r7, #0] 8016ae2: 2b00 cmp r3, #0 8016ae4: d008 beq.n 8016af8 xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); 8016ae6: 4b13 ldr r3, [pc, #76] @ (8016b34 ) 8016ae8: 681b ldr r3, [r3, #0] 8016aea: 681b ldr r3, [r3, #0] 8016aec: 2b00 cmp r3, #0 8016aee: d101 bne.n 8016af4 8016af0: 2301 movs r3, #1 8016af2: e000 b.n 8016af6 8016af4: 2300 movs r3, #0 8016af6: 603b str r3, [r7, #0] vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); 8016af8: 4b0f ldr r3, [pc, #60] @ (8016b38 ) 8016afa: 6818 ldr r0, [r3, #0] 8016afc: 687a ldr r2, [r7, #4] 8016afe: 68fb ldr r3, [r7, #12] 8016b00: 1ad3 subs r3, r2, r3 8016b02: 683a ldr r2, [r7, #0] 8016b04: 4619 mov r1, r3 8016b06: f7fe f995 bl 8014e34 if( xTaskResumeAll() == pdFALSE ) 8016b0a: f7fe fdf7 bl 80156fc 8016b0e: 4603 mov r3, r0 8016b10: 2b00 cmp r3, #0 8016b12: d10a bne.n 8016b2a portYIELD_WITHIN_API(); 8016b14: 4b09 ldr r3, [pc, #36] @ (8016b3c ) 8016b16: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016b1a: 601a str r2, [r3, #0] 8016b1c: f3bf 8f4f dsb sy 8016b20: f3bf 8f6f isb sy } 8016b24: e001 b.n 8016b2a ( void ) xTaskResumeAll(); 8016b26: f7fe fde9 bl 80156fc } 8016b2a: bf00 nop 8016b2c: 3710 adds r7, #16 8016b2e: 46bd mov sp, r7 8016b30: bd80 pop {r7, pc} 8016b32: bf00 nop 8016b34: 24002f40 .word 0x24002f40 8016b38: 24002f44 .word 0x24002f44 8016b3c: e000ed04 .word 0xe000ed04 08016b40 : /*-----------------------------------------------------------*/ static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) { 8016b40: b480 push {r7} 8016b42: b085 sub sp, #20 8016b44: af00 add r7, sp, #0 8016b46: 6078 str r0, [r7, #4] the timer with the nearest expiry time will expire. If there are no active timers then just set the next expire time to 0. That will cause this task to unblock when the tick count overflows, at which point the timer lists will be switched and the next expiry time can be re-assessed. */ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); 8016b48: 4b0e ldr r3, [pc, #56] @ (8016b84 ) 8016b4a: 681b ldr r3, [r3, #0] 8016b4c: 681b ldr r3, [r3, #0] 8016b4e: 2b00 cmp r3, #0 8016b50: d101 bne.n 8016b56 8016b52: 2201 movs r2, #1 8016b54: e000 b.n 8016b58 8016b56: 2200 movs r2, #0 8016b58: 687b ldr r3, [r7, #4] 8016b5a: 601a str r2, [r3, #0] if( *pxListWasEmpty == pdFALSE ) 8016b5c: 687b ldr r3, [r7, #4] 8016b5e: 681b ldr r3, [r3, #0] 8016b60: 2b00 cmp r3, #0 8016b62: d105 bne.n 8016b70 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 8016b64: 4b07 ldr r3, [pc, #28] @ (8016b84 ) 8016b66: 681b ldr r3, [r3, #0] 8016b68: 68db ldr r3, [r3, #12] 8016b6a: 681b ldr r3, [r3, #0] 8016b6c: 60fb str r3, [r7, #12] 8016b6e: e001 b.n 8016b74 } else { /* Ensure the task unblocks when the tick count rolls over. */ xNextExpireTime = ( TickType_t ) 0U; 8016b70: 2300 movs r3, #0 8016b72: 60fb str r3, [r7, #12] } return xNextExpireTime; 8016b74: 68fb ldr r3, [r7, #12] } 8016b76: 4618 mov r0, r3 8016b78: 3714 adds r7, #20 8016b7a: 46bd mov sp, r7 8016b7c: f85d 7b04 ldr.w r7, [sp], #4 8016b80: 4770 bx lr 8016b82: bf00 nop 8016b84: 24002f3c .word 0x24002f3c 08016b88 : /*-----------------------------------------------------------*/ static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) { 8016b88: b580 push {r7, lr} 8016b8a: b084 sub sp, #16 8016b8c: af00 add r7, sp, #0 8016b8e: 6078 str r0, [r7, #4] TickType_t xTimeNow; PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ xTimeNow = xTaskGetTickCount(); 8016b90: f7fe fe52 bl 8015838 8016b94: 60f8 str r0, [r7, #12] if( xTimeNow < xLastTime ) 8016b96: 4b0b ldr r3, [pc, #44] @ (8016bc4 ) 8016b98: 681b ldr r3, [r3, #0] 8016b9a: 68fa ldr r2, [r7, #12] 8016b9c: 429a cmp r2, r3 8016b9e: d205 bcs.n 8016bac { prvSwitchTimerLists(); 8016ba0: f000 f93a bl 8016e18 *pxTimerListsWereSwitched = pdTRUE; 8016ba4: 687b ldr r3, [r7, #4] 8016ba6: 2201 movs r2, #1 8016ba8: 601a str r2, [r3, #0] 8016baa: e002 b.n 8016bb2 } else { *pxTimerListsWereSwitched = pdFALSE; 8016bac: 687b ldr r3, [r7, #4] 8016bae: 2200 movs r2, #0 8016bb0: 601a str r2, [r3, #0] } xLastTime = xTimeNow; 8016bb2: 4a04 ldr r2, [pc, #16] @ (8016bc4 ) 8016bb4: 68fb ldr r3, [r7, #12] 8016bb6: 6013 str r3, [r2, #0] return xTimeNow; 8016bb8: 68fb ldr r3, [r7, #12] } 8016bba: 4618 mov r0, r3 8016bbc: 3710 adds r7, #16 8016bbe: 46bd mov sp, r7 8016bc0: bd80 pop {r7, pc} 8016bc2: bf00 nop 8016bc4: 24002f4c .word 0x24002f4c 08016bc8 : /*-----------------------------------------------------------*/ static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) { 8016bc8: b580 push {r7, lr} 8016bca: b086 sub sp, #24 8016bcc: af00 add r7, sp, #0 8016bce: 60f8 str r0, [r7, #12] 8016bd0: 60b9 str r1, [r7, #8] 8016bd2: 607a str r2, [r7, #4] 8016bd4: 603b str r3, [r7, #0] BaseType_t xProcessTimerNow = pdFALSE; 8016bd6: 2300 movs r3, #0 8016bd8: 617b str r3, [r7, #20] listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); 8016bda: 68fb ldr r3, [r7, #12] 8016bdc: 68ba ldr r2, [r7, #8] 8016bde: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 8016be0: 68fb ldr r3, [r7, #12] 8016be2: 68fa ldr r2, [r7, #12] 8016be4: 611a str r2, [r3, #16] if( xNextExpiryTime <= xTimeNow ) 8016be6: 68ba ldr r2, [r7, #8] 8016be8: 687b ldr r3, [r7, #4] 8016bea: 429a cmp r2, r3 8016bec: d812 bhi.n 8016c14 { /* Has the expiry time elapsed between the command to start/reset a timer was issued, and the time the command was processed? */ if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016bee: 687a ldr r2, [r7, #4] 8016bf0: 683b ldr r3, [r7, #0] 8016bf2: 1ad2 subs r2, r2, r3 8016bf4: 68fb ldr r3, [r7, #12] 8016bf6: 699b ldr r3, [r3, #24] 8016bf8: 429a cmp r2, r3 8016bfa: d302 bcc.n 8016c02 { /* The time between a command being issued and the command being processed actually exceeds the timers period. */ xProcessTimerNow = pdTRUE; 8016bfc: 2301 movs r3, #1 8016bfe: 617b str r3, [r7, #20] 8016c00: e01b b.n 8016c3a } else { vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); 8016c02: 4b10 ldr r3, [pc, #64] @ (8016c44 ) 8016c04: 681a ldr r2, [r3, #0] 8016c06: 68fb ldr r3, [r7, #12] 8016c08: 3304 adds r3, #4 8016c0a: 4619 mov r1, r3 8016c0c: 4610 mov r0, r2 8016c0e: f7fd f94a bl 8013ea6 8016c12: e012 b.n 8016c3a } } else { if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) 8016c14: 687a ldr r2, [r7, #4] 8016c16: 683b ldr r3, [r7, #0] 8016c18: 429a cmp r2, r3 8016c1a: d206 bcs.n 8016c2a 8016c1c: 68ba ldr r2, [r7, #8] 8016c1e: 683b ldr r3, [r7, #0] 8016c20: 429a cmp r2, r3 8016c22: d302 bcc.n 8016c2a { /* If, since the command was issued, the tick count has overflowed but the expiry time has not, then the timer must have already passed its expiry time and should be processed immediately. */ xProcessTimerNow = pdTRUE; 8016c24: 2301 movs r3, #1 8016c26: 617b str r3, [r7, #20] 8016c28: e007 b.n 8016c3a } else { vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 8016c2a: 4b07 ldr r3, [pc, #28] @ (8016c48 ) 8016c2c: 681a ldr r2, [r3, #0] 8016c2e: 68fb ldr r3, [r7, #12] 8016c30: 3304 adds r3, #4 8016c32: 4619 mov r1, r3 8016c34: 4610 mov r0, r2 8016c36: f7fd f936 bl 8013ea6 } } return xProcessTimerNow; 8016c3a: 697b ldr r3, [r7, #20] } 8016c3c: 4618 mov r0, r3 8016c3e: 3718 adds r7, #24 8016c40: 46bd mov sp, r7 8016c42: bd80 pop {r7, pc} 8016c44: 24002f40 .word 0x24002f40 8016c48: 24002f3c .word 0x24002f3c 08016c4c : /*-----------------------------------------------------------*/ static void prvProcessReceivedCommands( void ) { 8016c4c: b580 push {r7, lr} 8016c4e: b08e sub sp, #56 @ 0x38 8016c50: af02 add r7, sp, #8 DaemonTaskMessage_t xMessage; Timer_t *pxTimer; BaseType_t xTimerListsWereSwitched, xResult; TickType_t xTimeNow; while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 8016c52: e0ce b.n 8016df2 { #if ( INCLUDE_xTimerPendFunctionCall == 1 ) { /* Negative commands are pended function calls rather than timer commands. */ if( xMessage.xMessageID < ( BaseType_t ) 0 ) 8016c54: 687b ldr r3, [r7, #4] 8016c56: 2b00 cmp r3, #0 8016c58: da19 bge.n 8016c8e { const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); 8016c5a: 1d3b adds r3, r7, #4 8016c5c: 3304 adds r3, #4 8016c5e: 62fb str r3, [r7, #44] @ 0x2c /* The timer uses the xCallbackParameters member to request a callback be executed. Check the callback is not NULL. */ configASSERT( pxCallback ); 8016c60: 6afb ldr r3, [r7, #44] @ 0x2c 8016c62: 2b00 cmp r3, #0 8016c64: d10b bne.n 8016c7e __asm volatile 8016c66: f04f 0350 mov.w r3, #80 @ 0x50 8016c6a: f383 8811 msr BASEPRI, r3 8016c6e: f3bf 8f6f isb sy 8016c72: f3bf 8f4f dsb sy 8016c76: 61fb str r3, [r7, #28] } 8016c78: bf00 nop 8016c7a: bf00 nop 8016c7c: e7fd b.n 8016c7a /* Call the function. */ pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); 8016c7e: 6afb ldr r3, [r7, #44] @ 0x2c 8016c80: 681b ldr r3, [r3, #0] 8016c82: 6afa ldr r2, [r7, #44] @ 0x2c 8016c84: 6850 ldr r0, [r2, #4] 8016c86: 6afa ldr r2, [r7, #44] @ 0x2c 8016c88: 6892 ldr r2, [r2, #8] 8016c8a: 4611 mov r1, r2 8016c8c: 4798 blx r3 } #endif /* INCLUDE_xTimerPendFunctionCall */ /* Commands that are positive are timer commands rather than pended function calls. */ if( xMessage.xMessageID >= ( BaseType_t ) 0 ) 8016c8e: 687b ldr r3, [r7, #4] 8016c90: 2b00 cmp r3, #0 8016c92: f2c0 80ae blt.w 8016df2 { /* The messages uses the xTimerParameters member to work on a software timer. */ pxTimer = xMessage.u.xTimerParameters.pxTimer; 8016c96: 68fb ldr r3, [r7, #12] 8016c98: 62bb str r3, [r7, #40] @ 0x28 if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ 8016c9a: 6abb ldr r3, [r7, #40] @ 0x28 8016c9c: 695b ldr r3, [r3, #20] 8016c9e: 2b00 cmp r3, #0 8016ca0: d004 beq.n 8016cac { /* The timer is in a list, remove it. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8016ca2: 6abb ldr r3, [r7, #40] @ 0x28 8016ca4: 3304 adds r3, #4 8016ca6: 4618 mov r0, r3 8016ca8: f7fd f936 bl 8013f18 it must be present in the function call. prvSampleTimeNow() must be called after the message is received from xTimerQueue so there is no possibility of a higher priority task adding a message to the message queue with a time that is ahead of the timer daemon task (because it pre-empted the timer daemon task after the xTimeNow value was set). */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8016cac: 463b mov r3, r7 8016cae: 4618 mov r0, r3 8016cb0: f7ff ff6a bl 8016b88 8016cb4: 6278 str r0, [r7, #36] @ 0x24 switch( xMessage.xMessageID ) 8016cb6: 687b ldr r3, [r7, #4] 8016cb8: 2b09 cmp r3, #9 8016cba: f200 8097 bhi.w 8016dec 8016cbe: a201 add r2, pc, #4 @ (adr r2, 8016cc4 ) 8016cc0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016cc4: 08016ced .word 0x08016ced 8016cc8: 08016ced .word 0x08016ced 8016ccc: 08016ced .word 0x08016ced 8016cd0: 08016d63 .word 0x08016d63 8016cd4: 08016d77 .word 0x08016d77 8016cd8: 08016dc3 .word 0x08016dc3 8016cdc: 08016ced .word 0x08016ced 8016ce0: 08016ced .word 0x08016ced 8016ce4: 08016d63 .word 0x08016d63 8016ce8: 08016d77 .word 0x08016d77 case tmrCOMMAND_START_FROM_ISR : case tmrCOMMAND_RESET : case tmrCOMMAND_RESET_FROM_ISR : case tmrCOMMAND_START_DONT_TRACE : /* Start or restart a timer. */ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8016cec: 6abb ldr r3, [r7, #40] @ 0x28 8016cee: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016cf2: f043 0301 orr.w r3, r3, #1 8016cf6: b2da uxtb r2, r3 8016cf8: 6abb ldr r3, [r7, #40] @ 0x28 8016cfa: f883 2028 strb.w r2, [r3, #40] @ 0x28 if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) 8016cfe: 68ba ldr r2, [r7, #8] 8016d00: 6abb ldr r3, [r7, #40] @ 0x28 8016d02: 699b ldr r3, [r3, #24] 8016d04: 18d1 adds r1, r2, r3 8016d06: 68bb ldr r3, [r7, #8] 8016d08: 6a7a ldr r2, [r7, #36] @ 0x24 8016d0a: 6ab8 ldr r0, [r7, #40] @ 0x28 8016d0c: f7ff ff5c bl 8016bc8 8016d10: 4603 mov r3, r0 8016d12: 2b00 cmp r3, #0 8016d14: d06c beq.n 8016df0 { /* The timer expired before it was added to the active timer list. Process it now. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8016d16: 6abb ldr r3, [r7, #40] @ 0x28 8016d18: 6a1b ldr r3, [r3, #32] 8016d1a: 6ab8 ldr r0, [r7, #40] @ 0x28 8016d1c: 4798 blx r3 traceTIMER_EXPIRED( pxTimer ); if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 8016d1e: 6abb ldr r3, [r7, #40] @ 0x28 8016d20: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016d24: f003 0304 and.w r3, r3, #4 8016d28: 2b00 cmp r3, #0 8016d2a: d061 beq.n 8016df0 { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); 8016d2c: 68ba ldr r2, [r7, #8] 8016d2e: 6abb ldr r3, [r7, #40] @ 0x28 8016d30: 699b ldr r3, [r3, #24] 8016d32: 441a add r2, r3 8016d34: 2300 movs r3, #0 8016d36: 9300 str r3, [sp, #0] 8016d38: 2300 movs r3, #0 8016d3a: 2100 movs r1, #0 8016d3c: 6ab8 ldr r0, [r7, #40] @ 0x28 8016d3e: f7ff fe01 bl 8016944 8016d42: 6238 str r0, [r7, #32] configASSERT( xResult ); 8016d44: 6a3b ldr r3, [r7, #32] 8016d46: 2b00 cmp r3, #0 8016d48: d152 bne.n 8016df0 __asm volatile 8016d4a: f04f 0350 mov.w r3, #80 @ 0x50 8016d4e: f383 8811 msr BASEPRI, r3 8016d52: f3bf 8f6f isb sy 8016d56: f3bf 8f4f dsb sy 8016d5a: 61bb str r3, [r7, #24] } 8016d5c: bf00 nop 8016d5e: bf00 nop 8016d60: e7fd b.n 8016d5e break; case tmrCOMMAND_STOP : case tmrCOMMAND_STOP_FROM_ISR : /* The timer has already been removed from the active list. */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8016d62: 6abb ldr r3, [r7, #40] @ 0x28 8016d64: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016d68: f023 0301 bic.w r3, r3, #1 8016d6c: b2da uxtb r2, r3 8016d6e: 6abb ldr r3, [r7, #40] @ 0x28 8016d70: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8016d74: e03d b.n 8016df2 case tmrCOMMAND_CHANGE_PERIOD : case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR : pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8016d76: 6abb ldr r3, [r7, #40] @ 0x28 8016d78: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016d7c: f043 0301 orr.w r3, r3, #1 8016d80: b2da uxtb r2, r3 8016d82: 6abb ldr r3, [r7, #40] @ 0x28 8016d84: f883 2028 strb.w r2, [r3, #40] @ 0x28 pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; 8016d88: 68ba ldr r2, [r7, #8] 8016d8a: 6abb ldr r3, [r7, #40] @ 0x28 8016d8c: 619a str r2, [r3, #24] configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); 8016d8e: 6abb ldr r3, [r7, #40] @ 0x28 8016d90: 699b ldr r3, [r3, #24] 8016d92: 2b00 cmp r3, #0 8016d94: d10b bne.n 8016dae __asm volatile 8016d96: f04f 0350 mov.w r3, #80 @ 0x50 8016d9a: f383 8811 msr BASEPRI, r3 8016d9e: f3bf 8f6f isb sy 8016da2: f3bf 8f4f dsb sy 8016da6: 617b str r3, [r7, #20] } 8016da8: bf00 nop 8016daa: bf00 nop 8016dac: e7fd b.n 8016daa be longer or shorter than the old one. The command time is therefore set to the current time, and as the period cannot be zero the next expiry time can only be in the future, meaning (unlike for the xTimerStart() case above) there is no fail case that needs to be handled here. */ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); 8016dae: 6abb ldr r3, [r7, #40] @ 0x28 8016db0: 699a ldr r2, [r3, #24] 8016db2: 6a7b ldr r3, [r7, #36] @ 0x24 8016db4: 18d1 adds r1, r2, r3 8016db6: 6a7b ldr r3, [r7, #36] @ 0x24 8016db8: 6a7a ldr r2, [r7, #36] @ 0x24 8016dba: 6ab8 ldr r0, [r7, #40] @ 0x28 8016dbc: f7ff ff04 bl 8016bc8 break; 8016dc0: e017 b.n 8016df2 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* The timer has already been removed from the active list, just free up the memory if the memory was dynamically allocated. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) 8016dc2: 6abb ldr r3, [r7, #40] @ 0x28 8016dc4: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016dc8: f003 0302 and.w r3, r3, #2 8016dcc: 2b00 cmp r3, #0 8016dce: d103 bne.n 8016dd8 { vPortFree( pxTimer ); 8016dd0: 6ab8 ldr r0, [r7, #40] @ 0x28 8016dd2: f000 fc31 bl 8017638 no need to free the memory - just mark the timer as "not active". */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ break; 8016dd6: e00c b.n 8016df2 pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8016dd8: 6abb ldr r3, [r7, #40] @ 0x28 8016dda: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016dde: f023 0301 bic.w r3, r3, #1 8016de2: b2da uxtb r2, r3 8016de4: 6abb ldr r3, [r7, #40] @ 0x28 8016de6: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8016dea: e002 b.n 8016df2 default : /* Don't expect to get here. */ break; 8016dec: bf00 nop 8016dee: e000 b.n 8016df2 break; 8016df0: bf00 nop while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 8016df2: 4b08 ldr r3, [pc, #32] @ (8016e14 ) 8016df4: 681b ldr r3, [r3, #0] 8016df6: 1d39 adds r1, r7, #4 8016df8: 2200 movs r2, #0 8016dfa: 4618 mov r0, r3 8016dfc: f7fd fc54 bl 80146a8 8016e00: 4603 mov r3, r0 8016e02: 2b00 cmp r3, #0 8016e04: f47f af26 bne.w 8016c54 } } } } 8016e08: bf00 nop 8016e0a: bf00 nop 8016e0c: 3730 adds r7, #48 @ 0x30 8016e0e: 46bd mov sp, r7 8016e10: bd80 pop {r7, pc} 8016e12: bf00 nop 8016e14: 24002f44 .word 0x24002f44 08016e18 : /*-----------------------------------------------------------*/ static void prvSwitchTimerLists( void ) { 8016e18: b580 push {r7, lr} 8016e1a: b088 sub sp, #32 8016e1c: af02 add r7, sp, #8 /* The tick count has overflowed. The timer lists must be switched. If there are any timers still referenced from the current timer list then they must have expired and should be processed before the lists are switched. */ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 8016e1e: e049 b.n 8016eb4 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 8016e20: 4b2e ldr r3, [pc, #184] @ (8016edc ) 8016e22: 681b ldr r3, [r3, #0] 8016e24: 68db ldr r3, [r3, #12] 8016e26: 681b ldr r3, [r3, #0] 8016e28: 613b str r3, [r7, #16] /* Remove the timer from the list. */ pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8016e2a: 4b2c ldr r3, [pc, #176] @ (8016edc ) 8016e2c: 681b ldr r3, [r3, #0] 8016e2e: 68db ldr r3, [r3, #12] 8016e30: 68db ldr r3, [r3, #12] 8016e32: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8016e34: 68fb ldr r3, [r7, #12] 8016e36: 3304 adds r3, #4 8016e38: 4618 mov r0, r3 8016e3a: f7fd f86d bl 8013f18 traceTIMER_EXPIRED( pxTimer ); /* Execute its callback, then send a command to restart the timer if it is an auto-reload timer. It cannot be restarted here as the lists have not yet been switched. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8016e3e: 68fb ldr r3, [r7, #12] 8016e40: 6a1b ldr r3, [r3, #32] 8016e42: 68f8 ldr r0, [r7, #12] 8016e44: 4798 blx r3 if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 8016e46: 68fb ldr r3, [r7, #12] 8016e48: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016e4c: f003 0304 and.w r3, r3, #4 8016e50: 2b00 cmp r3, #0 8016e52: d02f beq.n 8016eb4 the timer going into the same timer list then it has already expired and the timer should be re-inserted into the current list so it is processed again within this loop. Otherwise a command should be sent to restart the timer to ensure it is only inserted into a list after the lists have been swapped. */ xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); 8016e54: 68fb ldr r3, [r7, #12] 8016e56: 699b ldr r3, [r3, #24] 8016e58: 693a ldr r2, [r7, #16] 8016e5a: 4413 add r3, r2 8016e5c: 60bb str r3, [r7, #8] if( xReloadTime > xNextExpireTime ) 8016e5e: 68ba ldr r2, [r7, #8] 8016e60: 693b ldr r3, [r7, #16] 8016e62: 429a cmp r2, r3 8016e64: d90e bls.n 8016e84 { listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); 8016e66: 68fb ldr r3, [r7, #12] 8016e68: 68ba ldr r2, [r7, #8] 8016e6a: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 8016e6c: 68fb ldr r3, [r7, #12] 8016e6e: 68fa ldr r2, [r7, #12] 8016e70: 611a str r2, [r3, #16] vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 8016e72: 4b1a ldr r3, [pc, #104] @ (8016edc ) 8016e74: 681a ldr r2, [r3, #0] 8016e76: 68fb ldr r3, [r7, #12] 8016e78: 3304 adds r3, #4 8016e7a: 4619 mov r1, r3 8016e7c: 4610 mov r0, r2 8016e7e: f7fd f812 bl 8013ea6 8016e82: e017 b.n 8016eb4 } else { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 8016e84: 2300 movs r3, #0 8016e86: 9300 str r3, [sp, #0] 8016e88: 2300 movs r3, #0 8016e8a: 693a ldr r2, [r7, #16] 8016e8c: 2100 movs r1, #0 8016e8e: 68f8 ldr r0, [r7, #12] 8016e90: f7ff fd58 bl 8016944 8016e94: 6078 str r0, [r7, #4] configASSERT( xResult ); 8016e96: 687b ldr r3, [r7, #4] 8016e98: 2b00 cmp r3, #0 8016e9a: d10b bne.n 8016eb4 __asm volatile 8016e9c: f04f 0350 mov.w r3, #80 @ 0x50 8016ea0: f383 8811 msr BASEPRI, r3 8016ea4: f3bf 8f6f isb sy 8016ea8: f3bf 8f4f dsb sy 8016eac: 603b str r3, [r7, #0] } 8016eae: bf00 nop 8016eb0: bf00 nop 8016eb2: e7fd b.n 8016eb0 while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 8016eb4: 4b09 ldr r3, [pc, #36] @ (8016edc ) 8016eb6: 681b ldr r3, [r3, #0] 8016eb8: 681b ldr r3, [r3, #0] 8016eba: 2b00 cmp r3, #0 8016ebc: d1b0 bne.n 8016e20 { mtCOVERAGE_TEST_MARKER(); } } pxTemp = pxCurrentTimerList; 8016ebe: 4b07 ldr r3, [pc, #28] @ (8016edc ) 8016ec0: 681b ldr r3, [r3, #0] 8016ec2: 617b str r3, [r7, #20] pxCurrentTimerList = pxOverflowTimerList; 8016ec4: 4b06 ldr r3, [pc, #24] @ (8016ee0 ) 8016ec6: 681b ldr r3, [r3, #0] 8016ec8: 4a04 ldr r2, [pc, #16] @ (8016edc ) 8016eca: 6013 str r3, [r2, #0] pxOverflowTimerList = pxTemp; 8016ecc: 4a04 ldr r2, [pc, #16] @ (8016ee0 ) 8016ece: 697b ldr r3, [r7, #20] 8016ed0: 6013 str r3, [r2, #0] } 8016ed2: bf00 nop 8016ed4: 3718 adds r7, #24 8016ed6: 46bd mov sp, r7 8016ed8: bd80 pop {r7, pc} 8016eda: bf00 nop 8016edc: 24002f3c .word 0x24002f3c 8016ee0: 24002f40 .word 0x24002f40 08016ee4 : /*-----------------------------------------------------------*/ static void prvCheckForValidListAndQueue( void ) { 8016ee4: b580 push {r7, lr} 8016ee6: b082 sub sp, #8 8016ee8: af02 add r7, sp, #8 /* Check that the list from which active timers are referenced, and the queue used to communicate with the timer service, have been initialised. */ taskENTER_CRITICAL(); 8016eea: f000 f9b5 bl 8017258 { if( xTimerQueue == NULL ) 8016eee: 4b15 ldr r3, [pc, #84] @ (8016f44 ) 8016ef0: 681b ldr r3, [r3, #0] 8016ef2: 2b00 cmp r3, #0 8016ef4: d120 bne.n 8016f38 { vListInitialise( &xActiveTimerList1 ); 8016ef6: 4814 ldr r0, [pc, #80] @ (8016f48 ) 8016ef8: f7fc ff84 bl 8013e04 vListInitialise( &xActiveTimerList2 ); 8016efc: 4813 ldr r0, [pc, #76] @ (8016f4c ) 8016efe: f7fc ff81 bl 8013e04 pxCurrentTimerList = &xActiveTimerList1; 8016f02: 4b13 ldr r3, [pc, #76] @ (8016f50 ) 8016f04: 4a10 ldr r2, [pc, #64] @ (8016f48 ) 8016f06: 601a str r2, [r3, #0] pxOverflowTimerList = &xActiveTimerList2; 8016f08: 4b12 ldr r3, [pc, #72] @ (8016f54 ) 8016f0a: 4a10 ldr r2, [pc, #64] @ (8016f4c ) 8016f0c: 601a str r2, [r3, #0] /* The timer queue is allocated statically in case configSUPPORT_DYNAMIC_ALLOCATION is 0. */ static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 8016f0e: 2300 movs r3, #0 8016f10: 9300 str r3, [sp, #0] 8016f12: 4b11 ldr r3, [pc, #68] @ (8016f58 ) 8016f14: 4a11 ldr r2, [pc, #68] @ (8016f5c ) 8016f16: 2110 movs r1, #16 8016f18: 200a movs r0, #10 8016f1a: f7fd f891 bl 8014040 8016f1e: 4603 mov r3, r0 8016f20: 4a08 ldr r2, [pc, #32] @ (8016f44 ) 8016f22: 6013 str r3, [r2, #0] } #endif #if ( configQUEUE_REGISTRY_SIZE > 0 ) { if( xTimerQueue != NULL ) 8016f24: 4b07 ldr r3, [pc, #28] @ (8016f44 ) 8016f26: 681b ldr r3, [r3, #0] 8016f28: 2b00 cmp r3, #0 8016f2a: d005 beq.n 8016f38 { vQueueAddToRegistry( xTimerQueue, "TmrQ" ); 8016f2c: 4b05 ldr r3, [pc, #20] @ (8016f44 ) 8016f2e: 681b ldr r3, [r3, #0] 8016f30: 490b ldr r1, [pc, #44] @ (8016f60 ) 8016f32: 4618 mov r0, r3 8016f34: f7fd ff54 bl 8014de0 else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016f38: f000 f9c0 bl 80172bc } 8016f3c: bf00 nop 8016f3e: 46bd mov sp, r7 8016f40: bd80 pop {r7, pc} 8016f42: bf00 nop 8016f44: 24002f44 .word 0x24002f44 8016f48: 24002f14 .word 0x24002f14 8016f4c: 24002f28 .word 0x24002f28 8016f50: 24002f3c .word 0x24002f3c 8016f54: 24002f40 .word 0x24002f40 8016f58: 24002ff0 .word 0x24002ff0 8016f5c: 24002f50 .word 0x24002f50 8016f60: 08018af0 .word 0x08018af0 08016f64 : /*-----------------------------------------------------------*/ BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) { 8016f64: b580 push {r7, lr} 8016f66: b086 sub sp, #24 8016f68: af00 add r7, sp, #0 8016f6a: 6078 str r0, [r7, #4] BaseType_t xReturn; Timer_t *pxTimer = xTimer; 8016f6c: 687b ldr r3, [r7, #4] 8016f6e: 613b str r3, [r7, #16] configASSERT( xTimer ); 8016f70: 687b ldr r3, [r7, #4] 8016f72: 2b00 cmp r3, #0 8016f74: d10b bne.n 8016f8e __asm volatile 8016f76: f04f 0350 mov.w r3, #80 @ 0x50 8016f7a: f383 8811 msr BASEPRI, r3 8016f7e: f3bf 8f6f isb sy 8016f82: f3bf 8f4f dsb sy 8016f86: 60fb str r3, [r7, #12] } 8016f88: bf00 nop 8016f8a: bf00 nop 8016f8c: e7fd b.n 8016f8a /* Is the timer in the list of active timers? */ taskENTER_CRITICAL(); 8016f8e: f000 f963 bl 8017258 { if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 ) 8016f92: 693b ldr r3, [r7, #16] 8016f94: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016f98: f003 0301 and.w r3, r3, #1 8016f9c: 2b00 cmp r3, #0 8016f9e: d102 bne.n 8016fa6 { xReturn = pdFALSE; 8016fa0: 2300 movs r3, #0 8016fa2: 617b str r3, [r7, #20] 8016fa4: e001 b.n 8016faa } else { xReturn = pdTRUE; 8016fa6: 2301 movs r3, #1 8016fa8: 617b str r3, [r7, #20] } } taskEXIT_CRITICAL(); 8016faa: f000 f987 bl 80172bc return xReturn; 8016fae: 697b ldr r3, [r7, #20] } /*lint !e818 Can't be pointer to const due to the typedef. */ 8016fb0: 4618 mov r0, r3 8016fb2: 3718 adds r7, #24 8016fb4: 46bd mov sp, r7 8016fb6: bd80 pop {r7, pc} 08016fb8 : /*-----------------------------------------------------------*/ void *pvTimerGetTimerID( const TimerHandle_t xTimer ) { 8016fb8: b580 push {r7, lr} 8016fba: b086 sub sp, #24 8016fbc: af00 add r7, sp, #0 8016fbe: 6078 str r0, [r7, #4] Timer_t * const pxTimer = xTimer; 8016fc0: 687b ldr r3, [r7, #4] 8016fc2: 617b str r3, [r7, #20] void *pvReturn; configASSERT( xTimer ); 8016fc4: 687b ldr r3, [r7, #4] 8016fc6: 2b00 cmp r3, #0 8016fc8: d10b bne.n 8016fe2 __asm volatile 8016fca: f04f 0350 mov.w r3, #80 @ 0x50 8016fce: f383 8811 msr BASEPRI, r3 8016fd2: f3bf 8f6f isb sy 8016fd6: f3bf 8f4f dsb sy 8016fda: 60fb str r3, [r7, #12] } 8016fdc: bf00 nop 8016fde: bf00 nop 8016fe0: e7fd b.n 8016fde taskENTER_CRITICAL(); 8016fe2: f000 f939 bl 8017258 { pvReturn = pxTimer->pvTimerID; 8016fe6: 697b ldr r3, [r7, #20] 8016fe8: 69db ldr r3, [r3, #28] 8016fea: 613b str r3, [r7, #16] } taskEXIT_CRITICAL(); 8016fec: f000 f966 bl 80172bc return pvReturn; 8016ff0: 693b ldr r3, [r7, #16] } 8016ff2: 4618 mov r0, r3 8016ff4: 3718 adds r7, #24 8016ff6: 46bd mov sp, r7 8016ff8: bd80 pop {r7, pc} ... 08016ffc : /* * See header file for description. */ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) { 8016ffc: b480 push {r7} 8016ffe: b085 sub sp, #20 8017000: af00 add r7, sp, #0 8017002: 60f8 str r0, [r7, #12] 8017004: 60b9 str r1, [r7, #8] 8017006: 607a str r2, [r7, #4] /* Simulate the stack frame as it would be created by a context switch interrupt. */ /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts, and to ensure alignment. */ pxTopOfStack--; 8017008: 68fb ldr r3, [r7, #12] 801700a: 3b04 subs r3, #4 801700c: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ 801700e: 68fb ldr r3, [r7, #12] 8017010: f04f 7280 mov.w r2, #16777216 @ 0x1000000 8017014: 601a str r2, [r3, #0] pxTopOfStack--; 8017016: 68fb ldr r3, [r7, #12] 8017018: 3b04 subs r3, #4 801701a: 60fb str r3, [r7, #12] *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ 801701c: 68bb ldr r3, [r7, #8] 801701e: f023 0201 bic.w r2, r3, #1 8017022: 68fb ldr r3, [r7, #12] 8017024: 601a str r2, [r3, #0] pxTopOfStack--; 8017026: 68fb ldr r3, [r7, #12] 8017028: 3b04 subs r3, #4 801702a: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ 801702c: 4a0c ldr r2, [pc, #48] @ (8017060 ) 801702e: 68fb ldr r3, [r7, #12] 8017030: 601a str r2, [r3, #0] /* Save code space by skipping register initialisation. */ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ 8017032: 68fb ldr r3, [r7, #12] 8017034: 3b14 subs r3, #20 8017036: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ 8017038: 687a ldr r2, [r7, #4] 801703a: 68fb ldr r3, [r7, #12] 801703c: 601a str r2, [r3, #0] /* A save method is being used that requires each task to maintain its own exec return value. */ pxTopOfStack--; 801703e: 68fb ldr r3, [r7, #12] 8017040: 3b04 subs r3, #4 8017042: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_EXC_RETURN; 8017044: 68fb ldr r3, [r7, #12] 8017046: f06f 0202 mvn.w r2, #2 801704a: 601a str r2, [r3, #0] pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ 801704c: 68fb ldr r3, [r7, #12] 801704e: 3b20 subs r3, #32 8017050: 60fb str r3, [r7, #12] return pxTopOfStack; 8017052: 68fb ldr r3, [r7, #12] } 8017054: 4618 mov r0, r3 8017056: 3714 adds r7, #20 8017058: 46bd mov sp, r7 801705a: f85d 7b04 ldr.w r7, [sp], #4 801705e: 4770 bx lr 8017060: 08017065 .word 0x08017065 08017064 : /*-----------------------------------------------------------*/ static void prvTaskExitError( void ) { 8017064: b480 push {r7} 8017066: b085 sub sp, #20 8017068: af00 add r7, sp, #0 volatile uint32_t ulDummy = 0; 801706a: 2300 movs r3, #0 801706c: 607b str r3, [r7, #4] its caller as there is nothing to return to. If a task wants to exit it should instead call vTaskDelete( NULL ). Artificially force an assert() to be triggered if configASSERT() is defined, then stop here so application writers can catch the error. */ configASSERT( uxCriticalNesting == ~0UL ); 801706e: 4b13 ldr r3, [pc, #76] @ (80170bc ) 8017070: 681b ldr r3, [r3, #0] 8017072: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8017076: d00b beq.n 8017090 __asm volatile 8017078: f04f 0350 mov.w r3, #80 @ 0x50 801707c: f383 8811 msr BASEPRI, r3 8017080: f3bf 8f6f isb sy 8017084: f3bf 8f4f dsb sy 8017088: 60fb str r3, [r7, #12] } 801708a: bf00 nop 801708c: bf00 nop 801708e: e7fd b.n 801708c __asm volatile 8017090: f04f 0350 mov.w r3, #80 @ 0x50 8017094: f383 8811 msr BASEPRI, r3 8017098: f3bf 8f6f isb sy 801709c: f3bf 8f4f dsb sy 80170a0: 60bb str r3, [r7, #8] } 80170a2: bf00 nop portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) 80170a4: bf00 nop 80170a6: 687b ldr r3, [r7, #4] 80170a8: 2b00 cmp r3, #0 80170aa: d0fc beq.n 80170a6 about code appearing after this function is called - making ulDummy volatile makes the compiler think the function could return and therefore not output an 'unreachable code' warning for code that appears after it. */ } } 80170ac: bf00 nop 80170ae: bf00 nop 80170b0: 3714 adds r7, #20 80170b2: 46bd mov sp, r7 80170b4: f85d 7b04 ldr.w r7, [sp], #4 80170b8: 4770 bx lr 80170ba: bf00 nop 80170bc: 24000044 .word 0x24000044 080170c0 : /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( 80170c0: 4b07 ldr r3, [pc, #28] @ (80170e0 ) 80170c2: 6819 ldr r1, [r3, #0] 80170c4: 6808 ldr r0, [r1, #0] 80170c6: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80170ca: f380 8809 msr PSP, r0 80170ce: f3bf 8f6f isb sy 80170d2: f04f 0000 mov.w r0, #0 80170d6: f380 8811 msr BASEPRI, r0 80170da: 4770 bx lr 80170dc: f3af 8000 nop.w 080170e0 : 80170e0: 24002a14 .word 0x24002a14 " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } 80170e4: bf00 nop 80170e6: bf00 nop 080170e8 : { /* Start the first task. This also clears the bit that indicates the FPU is in use in case the FPU was used before the scheduler was started - which would otherwise result in the unnecessary leaving of space in the SVC stack for lazy saving of FPU registers. */ __asm volatile( 80170e8: 4808 ldr r0, [pc, #32] @ (801710c ) 80170ea: 6800 ldr r0, [r0, #0] 80170ec: 6800 ldr r0, [r0, #0] 80170ee: f380 8808 msr MSP, r0 80170f2: f04f 0000 mov.w r0, #0 80170f6: f380 8814 msr CONTROL, r0 80170fa: b662 cpsie i 80170fc: b661 cpsie f 80170fe: f3bf 8f4f dsb sy 8017102: f3bf 8f6f isb sy 8017106: df00 svc 0 8017108: bf00 nop " dsb \n" " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n" ); } 801710a: bf00 nop 801710c: e000ed08 .word 0xe000ed08 08017110 : /* * See header file for description. */ BaseType_t xPortStartScheduler( void ) { 8017110: b580 push {r7, lr} 8017112: b086 sub sp, #24 8017114: af00 add r7, sp, #0 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); /* This port can be used on all revisions of the Cortex-M7 core other than the r0p1 parts. r0p1 parts should use the port from the /source/portable/GCC/ARM_CM7/r0p1 directory. */ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); 8017116: 4b47 ldr r3, [pc, #284] @ (8017234 ) 8017118: 681b ldr r3, [r3, #0] 801711a: 4a47 ldr r2, [pc, #284] @ (8017238 ) 801711c: 4293 cmp r3, r2 801711e: d10b bne.n 8017138 __asm volatile 8017120: f04f 0350 mov.w r3, #80 @ 0x50 8017124: f383 8811 msr BASEPRI, r3 8017128: f3bf 8f6f isb sy 801712c: f3bf 8f4f dsb sy 8017130: 613b str r3, [r7, #16] } 8017132: bf00 nop 8017134: bf00 nop 8017136: e7fd b.n 8017134 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); 8017138: 4b3e ldr r3, [pc, #248] @ (8017234 ) 801713a: 681b ldr r3, [r3, #0] 801713c: 4a3f ldr r2, [pc, #252] @ (801723c ) 801713e: 4293 cmp r3, r2 8017140: d10b bne.n 801715a __asm volatile 8017142: f04f 0350 mov.w r3, #80 @ 0x50 8017146: f383 8811 msr BASEPRI, r3 801714a: f3bf 8f6f isb sy 801714e: f3bf 8f4f dsb sy 8017152: 60fb str r3, [r7, #12] } 8017154: bf00 nop 8017156: bf00 nop 8017158: e7fd b.n 8017156 #if( configASSERT_DEFINED == 1 ) { volatile uint32_t ulOriginalPriority; volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); 801715a: 4b39 ldr r3, [pc, #228] @ (8017240 ) 801715c: 617b str r3, [r7, #20] functions can be called. ISR safe functions are those that end in "FromISR". FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. Save the interrupt priority value that is about to be clobbered. */ ulOriginalPriority = *pucFirstUserPriorityRegister; 801715e: 697b ldr r3, [r7, #20] 8017160: 781b ldrb r3, [r3, #0] 8017162: b2db uxtb r3, r3 8017164: 607b str r3, [r7, #4] /* Determine the number of priority bits available. First write to all possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; 8017166: 697b ldr r3, [r7, #20] 8017168: 22ff movs r2, #255 @ 0xff 801716a: 701a strb r2, [r3, #0] /* Read the value back to see how many bits stuck. */ ucMaxPriorityValue = *pucFirstUserPriorityRegister; 801716c: 697b ldr r3, [r7, #20] 801716e: 781b ldrb r3, [r3, #0] 8017170: b2db uxtb r3, r3 8017172: 70fb strb r3, [r7, #3] /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; 8017174: 78fb ldrb r3, [r7, #3] 8017176: b2db uxtb r3, r3 8017178: f003 0350 and.w r3, r3, #80 @ 0x50 801717c: b2da uxtb r2, r3 801717e: 4b31 ldr r3, [pc, #196] @ (8017244 ) 8017180: 701a strb r2, [r3, #0] /* Calculate the maximum acceptable priority group value for the number of bits read back. */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; 8017182: 4b31 ldr r3, [pc, #196] @ (8017248 ) 8017184: 2207 movs r2, #7 8017186: 601a str r2, [r3, #0] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 8017188: e009 b.n 801719e { ulMaxPRIGROUPValue--; 801718a: 4b2f ldr r3, [pc, #188] @ (8017248 ) 801718c: 681b ldr r3, [r3, #0] 801718e: 3b01 subs r3, #1 8017190: 4a2d ldr r2, [pc, #180] @ (8017248 ) 8017192: 6013 str r3, [r2, #0] ucMaxPriorityValue <<= ( uint8_t ) 0x01; 8017194: 78fb ldrb r3, [r7, #3] 8017196: b2db uxtb r3, r3 8017198: 005b lsls r3, r3, #1 801719a: b2db uxtb r3, r3 801719c: 70fb strb r3, [r7, #3] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 801719e: 78fb ldrb r3, [r7, #3] 80171a0: b2db uxtb r3, r3 80171a2: f003 0380 and.w r3, r3, #128 @ 0x80 80171a6: 2b80 cmp r3, #128 @ 0x80 80171a8: d0ef beq.n 801718a #ifdef configPRIO_BITS { /* Check the FreeRTOS configuration that defines the number of priority bits matches the number of priority bits actually queried from the hardware. */ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); 80171aa: 4b27 ldr r3, [pc, #156] @ (8017248 ) 80171ac: 681b ldr r3, [r3, #0] 80171ae: f1c3 0307 rsb r3, r3, #7 80171b2: 2b04 cmp r3, #4 80171b4: d00b beq.n 80171ce __asm volatile 80171b6: f04f 0350 mov.w r3, #80 @ 0x50 80171ba: f383 8811 msr BASEPRI, r3 80171be: f3bf 8f6f isb sy 80171c2: f3bf 8f4f dsb sy 80171c6: 60bb str r3, [r7, #8] } 80171c8: bf00 nop 80171ca: bf00 nop 80171cc: e7fd b.n 80171ca } #endif /* Shift the priority group value back to its position within the AIRCR register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; 80171ce: 4b1e ldr r3, [pc, #120] @ (8017248 ) 80171d0: 681b ldr r3, [r3, #0] 80171d2: 021b lsls r3, r3, #8 80171d4: 4a1c ldr r2, [pc, #112] @ (8017248 ) 80171d6: 6013 str r3, [r2, #0] ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; 80171d8: 4b1b ldr r3, [pc, #108] @ (8017248 ) 80171da: 681b ldr r3, [r3, #0] 80171dc: f403 63e0 and.w r3, r3, #1792 @ 0x700 80171e0: 4a19 ldr r2, [pc, #100] @ (8017248 ) 80171e2: 6013 str r3, [r2, #0] /* Restore the clobbered interrupt priority register to its original value. */ *pucFirstUserPriorityRegister = ulOriginalPriority; 80171e4: 687b ldr r3, [r7, #4] 80171e6: b2da uxtb r2, r3 80171e8: 697b ldr r3, [r7, #20] 80171ea: 701a strb r2, [r3, #0] } #endif /* conifgASSERT_DEFINED */ /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; 80171ec: 4b17 ldr r3, [pc, #92] @ (801724c ) 80171ee: 681b ldr r3, [r3, #0] 80171f0: 4a16 ldr r2, [pc, #88] @ (801724c ) 80171f2: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 80171f6: 6013 str r3, [r2, #0] portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; 80171f8: 4b14 ldr r3, [pc, #80] @ (801724c ) 80171fa: 681b ldr r3, [r3, #0] 80171fc: 4a13 ldr r2, [pc, #76] @ (801724c ) 80171fe: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000 8017202: 6013 str r3, [r2, #0] /* Start the timer that generates the tick ISR. Interrupts are disabled here already. */ vPortSetupTimerInterrupt(); 8017204: f000 f8da bl 80173bc /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; 8017208: 4b11 ldr r3, [pc, #68] @ (8017250 ) 801720a: 2200 movs r2, #0 801720c: 601a str r2, [r3, #0] /* Ensure the VFP is enabled - it should be anyway. */ vPortEnableVFP(); 801720e: f000 f8f9 bl 8017404 /* Lazy save always. */ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; 8017212: 4b10 ldr r3, [pc, #64] @ (8017254 ) 8017214: 681b ldr r3, [r3, #0] 8017216: 4a0f ldr r2, [pc, #60] @ (8017254 ) 8017218: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000 801721c: 6013 str r3, [r2, #0] /* Start the first task. */ prvPortStartFirstTask(); 801721e: f7ff ff63 bl 80170e8 exit error function to prevent compiler warnings about a static function not being called in the case that the application writer overrides this functionality by defining configTASK_RETURN_ADDRESS. Call vTaskSwitchContext() so link time optimisation does not remove the symbol. */ vTaskSwitchContext(); 8017222: f7fe fbd3 bl 80159cc prvTaskExitError(); 8017226: f7ff ff1d bl 8017064 /* Should not get here! */ return 0; 801722a: 2300 movs r3, #0 } 801722c: 4618 mov r0, r3 801722e: 3718 adds r7, #24 8017230: 46bd mov sp, r7 8017232: bd80 pop {r7, pc} 8017234: e000ed00 .word 0xe000ed00 8017238: 410fc271 .word 0x410fc271 801723c: 410fc270 .word 0x410fc270 8017240: e000e400 .word 0xe000e400 8017244: 24003040 .word 0x24003040 8017248: 24003044 .word 0x24003044 801724c: e000ed20 .word 0xe000ed20 8017250: 24000044 .word 0x24000044 8017254: e000ef34 .word 0xe000ef34 08017258 : configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) { 8017258: b480 push {r7} 801725a: b083 sub sp, #12 801725c: af00 add r7, sp, #0 __asm volatile 801725e: f04f 0350 mov.w r3, #80 @ 0x50 8017262: f383 8811 msr BASEPRI, r3 8017266: f3bf 8f6f isb sy 801726a: f3bf 8f4f dsb sy 801726e: 607b str r3, [r7, #4] } 8017270: bf00 nop portDISABLE_INTERRUPTS(); uxCriticalNesting++; 8017272: 4b10 ldr r3, [pc, #64] @ (80172b4 ) 8017274: 681b ldr r3, [r3, #0] 8017276: 3301 adds r3, #1 8017278: 4a0e ldr r2, [pc, #56] @ (80172b4 ) 801727a: 6013 str r3, [r2, #0] /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if( uxCriticalNesting == 1 ) 801727c: 4b0d ldr r3, [pc, #52] @ (80172b4 ) 801727e: 681b ldr r3, [r3, #0] 8017280: 2b01 cmp r3, #1 8017282: d110 bne.n 80172a6 { configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); 8017284: 4b0c ldr r3, [pc, #48] @ (80172b8 ) 8017286: 681b ldr r3, [r3, #0] 8017288: b2db uxtb r3, r3 801728a: 2b00 cmp r3, #0 801728c: d00b beq.n 80172a6 __asm volatile 801728e: f04f 0350 mov.w r3, #80 @ 0x50 8017292: f383 8811 msr BASEPRI, r3 8017296: f3bf 8f6f isb sy 801729a: f3bf 8f4f dsb sy 801729e: 603b str r3, [r7, #0] } 80172a0: bf00 nop 80172a2: bf00 nop 80172a4: e7fd b.n 80172a2 } } 80172a6: bf00 nop 80172a8: 370c adds r7, #12 80172aa: 46bd mov sp, r7 80172ac: f85d 7b04 ldr.w r7, [sp], #4 80172b0: 4770 bx lr 80172b2: bf00 nop 80172b4: 24000044 .word 0x24000044 80172b8: e000ed04 .word 0xe000ed04 080172bc : /*-----------------------------------------------------------*/ void vPortExitCritical( void ) { 80172bc: b480 push {r7} 80172be: b083 sub sp, #12 80172c0: af00 add r7, sp, #0 configASSERT( uxCriticalNesting ); 80172c2: 4b12 ldr r3, [pc, #72] @ (801730c ) 80172c4: 681b ldr r3, [r3, #0] 80172c6: 2b00 cmp r3, #0 80172c8: d10b bne.n 80172e2 __asm volatile 80172ca: f04f 0350 mov.w r3, #80 @ 0x50 80172ce: f383 8811 msr BASEPRI, r3 80172d2: f3bf 8f6f isb sy 80172d6: f3bf 8f4f dsb sy 80172da: 607b str r3, [r7, #4] } 80172dc: bf00 nop 80172de: bf00 nop 80172e0: e7fd b.n 80172de uxCriticalNesting--; 80172e2: 4b0a ldr r3, [pc, #40] @ (801730c ) 80172e4: 681b ldr r3, [r3, #0] 80172e6: 3b01 subs r3, #1 80172e8: 4a08 ldr r2, [pc, #32] @ (801730c ) 80172ea: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) 80172ec: 4b07 ldr r3, [pc, #28] @ (801730c ) 80172ee: 681b ldr r3, [r3, #0] 80172f0: 2b00 cmp r3, #0 80172f2: d105 bne.n 8017300 80172f4: 2300 movs r3, #0 80172f6: 603b str r3, [r7, #0] __asm volatile 80172f8: 683b ldr r3, [r7, #0] 80172fa: f383 8811 msr BASEPRI, r3 } 80172fe: bf00 nop { portENABLE_INTERRUPTS(); } } 8017300: bf00 nop 8017302: 370c adds r7, #12 8017304: 46bd mov sp, r7 8017306: f85d 7b04 ldr.w r7, [sp], #4 801730a: 4770 bx lr 801730c: 24000044 .word 0x24000044 08017310 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile 8017310: f3ef 8009 mrs r0, PSP 8017314: f3bf 8f6f isb sy 8017318: 4b15 ldr r3, [pc, #84] @ (8017370 ) 801731a: 681a ldr r2, [r3, #0] 801731c: f01e 0f10 tst.w lr, #16 8017320: bf08 it eq 8017322: ed20 8a10 vstmdbeq r0!, {s16-s31} 8017326: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801732a: 6010 str r0, [r2, #0] 801732c: e92d 0009 stmdb sp!, {r0, r3} 8017330: f04f 0050 mov.w r0, #80 @ 0x50 8017334: f380 8811 msr BASEPRI, r0 8017338: f3bf 8f4f dsb sy 801733c: f3bf 8f6f isb sy 8017340: f7fe fb44 bl 80159cc 8017344: f04f 0000 mov.w r0, #0 8017348: f380 8811 msr BASEPRI, r0 801734c: bc09 pop {r0, r3} 801734e: 6819 ldr r1, [r3, #0] 8017350: 6808 ldr r0, [r1, #0] 8017352: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017356: f01e 0f10 tst.w lr, #16 801735a: bf08 it eq 801735c: ecb0 8a10 vldmiaeq r0!, {s16-s31} 8017360: f380 8809 msr PSP, r0 8017364: f3bf 8f6f isb sy 8017368: 4770 bx lr 801736a: bf00 nop 801736c: f3af 8000 nop.w 08017370 : 8017370: 24002a14 .word 0x24002a14 " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ); } 8017374: bf00 nop 8017376: bf00 nop 08017378 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { 8017378: b580 push {r7, lr} 801737a: b082 sub sp, #8 801737c: af00 add r7, sp, #0 __asm volatile 801737e: f04f 0350 mov.w r3, #80 @ 0x50 8017382: f383 8811 msr BASEPRI, r3 8017386: f3bf 8f6f isb sy 801738a: f3bf 8f4f dsb sy 801738e: 607b str r3, [r7, #4] } 8017390: bf00 nop save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) 8017392: f7fe fa61 bl 8015858 8017396: 4603 mov r3, r0 8017398: 2b00 cmp r3, #0 801739a: d003 beq.n 80173a4 { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; 801739c: 4b06 ldr r3, [pc, #24] @ (80173b8 ) 801739e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80173a2: 601a str r2, [r3, #0] 80173a4: 2300 movs r3, #0 80173a6: 603b str r3, [r7, #0] __asm volatile 80173a8: 683b ldr r3, [r7, #0] 80173aa: f383 8811 msr BASEPRI, r3 } 80173ae: bf00 nop } } portENABLE_INTERRUPTS(); } 80173b0: bf00 nop 80173b2: 3708 adds r7, #8 80173b4: 46bd mov sp, r7 80173b6: bd80 pop {r7, pc} 80173b8: e000ed04 .word 0xe000ed04 080173bc : /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) { 80173bc: b480 push {r7} 80173be: af00 add r7, sp, #0 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and clear the SysTick. */ portNVIC_SYSTICK_CTRL_REG = 0UL; 80173c0: 4b0b ldr r3, [pc, #44] @ (80173f0 ) 80173c2: 2200 movs r2, #0 80173c4: 601a str r2, [r3, #0] portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; 80173c6: 4b0b ldr r3, [pc, #44] @ (80173f4 ) 80173c8: 2200 movs r2, #0 80173ca: 601a str r2, [r3, #0] /* Configure SysTick to interrupt at the requested rate. */ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; 80173cc: 4b0a ldr r3, [pc, #40] @ (80173f8 ) 80173ce: 681b ldr r3, [r3, #0] 80173d0: 4a0a ldr r2, [pc, #40] @ (80173fc ) 80173d2: fba2 2303 umull r2, r3, r2, r3 80173d6: 099b lsrs r3, r3, #6 80173d8: 4a09 ldr r2, [pc, #36] @ (8017400 ) 80173da: 3b01 subs r3, #1 80173dc: 6013 str r3, [r2, #0] portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); 80173de: 4b04 ldr r3, [pc, #16] @ (80173f0 ) 80173e0: 2207 movs r2, #7 80173e2: 601a str r2, [r3, #0] } 80173e4: bf00 nop 80173e6: 46bd mov sp, r7 80173e8: f85d 7b04 ldr.w r7, [sp], #4 80173ec: 4770 bx lr 80173ee: bf00 nop 80173f0: e000e010 .word 0xe000e010 80173f4: e000e018 .word 0xe000e018 80173f8: 24000034 .word 0x24000034 80173fc: 10624dd3 .word 0x10624dd3 8017400: e000e014 .word 0xe000e014 08017404 : /*-----------------------------------------------------------*/ /* This is a naked function. */ static void vPortEnableVFP( void ) { __asm volatile 8017404: f8df 000c ldr.w r0, [pc, #12] @ 8017414 8017408: 6801 ldr r1, [r0, #0] 801740a: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 801740e: 6001 str r1, [r0, #0] 8017410: 4770 bx lr " \n" " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ " str r1, [r0] \n" " bx r14 " ); } 8017412: bf00 nop 8017414: e000ed88 .word 0xe000ed88 08017418 : /*-----------------------------------------------------------*/ #if( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { 8017418: b480 push {r7} 801741a: b085 sub sp, #20 801741c: af00 add r7, sp, #0 uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); 801741e: f3ef 8305 mrs r3, IPSR 8017422: 60fb str r3, [r7, #12] /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) 8017424: 68fb ldr r3, [r7, #12] 8017426: 2b0f cmp r3, #15 8017428: d915 bls.n 8017456 { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; 801742a: 4a18 ldr r2, [pc, #96] @ (801748c ) 801742c: 68fb ldr r3, [r7, #12] 801742e: 4413 add r3, r2 8017430: 781b ldrb r3, [r3, #0] 8017432: 72fb strb r3, [r7, #11] interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); 8017434: 4b16 ldr r3, [pc, #88] @ (8017490 ) 8017436: 781b ldrb r3, [r3, #0] 8017438: 7afa ldrb r2, [r7, #11] 801743a: 429a cmp r2, r3 801743c: d20b bcs.n 8017456 __asm volatile 801743e: f04f 0350 mov.w r3, #80 @ 0x50 8017442: f383 8811 msr BASEPRI, r3 8017446: f3bf 8f6f isb sy 801744a: f3bf 8f4f dsb sy 801744e: 607b str r3, [r7, #4] } 8017450: bf00 nop 8017452: bf00 nop 8017454: e7fd b.n 8017452 configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); 8017456: 4b0f ldr r3, [pc, #60] @ (8017494 ) 8017458: 681b ldr r3, [r3, #0] 801745a: f403 62e0 and.w r2, r3, #1792 @ 0x700 801745e: 4b0e ldr r3, [pc, #56] @ (8017498 ) 8017460: 681b ldr r3, [r3, #0] 8017462: 429a cmp r2, r3 8017464: d90b bls.n 801747e __asm volatile 8017466: f04f 0350 mov.w r3, #80 @ 0x50 801746a: f383 8811 msr BASEPRI, r3 801746e: f3bf 8f6f isb sy 8017472: f3bf 8f4f dsb sy 8017476: 603b str r3, [r7, #0] } 8017478: bf00 nop 801747a: bf00 nop 801747c: e7fd b.n 801747a } 801747e: bf00 nop 8017480: 3714 adds r7, #20 8017482: 46bd mov sp, r7 8017484: f85d 7b04 ldr.w r7, [sp], #4 8017488: 4770 bx lr 801748a: bf00 nop 801748c: e000e3f0 .word 0xe000e3f0 8017490: 24003040 .word 0x24003040 8017494: e000ed0c .word 0xe000ed0c 8017498: 24003044 .word 0x24003044 0801749c : static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ void *pvPortMalloc( size_t xWantedSize ) { 801749c: b580 push {r7, lr} 801749e: b08a sub sp, #40 @ 0x28 80174a0: af00 add r7, sp, #0 80174a2: 6078 str r0, [r7, #4] BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; void *pvReturn = NULL; 80174a4: 2300 movs r3, #0 80174a6: 61fb str r3, [r7, #28] vTaskSuspendAll(); 80174a8: f7fe f91a bl 80156e0 { /* If this is the first call to malloc then the heap will require initialisation to setup the list of free blocks. */ if( pxEnd == NULL ) 80174ac: 4b5c ldr r3, [pc, #368] @ (8017620 ) 80174ae: 681b ldr r3, [r3, #0] 80174b0: 2b00 cmp r3, #0 80174b2: d101 bne.n 80174b8 { prvHeapInit(); 80174b4: f000 f924 bl 8017700 /* Check the requested block size is not so large that the top bit is set. The top bit of the block size member of the BlockLink_t structure is used to determine who owns the block - the application or the kernel, so it must be free. */ if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) 80174b8: 4b5a ldr r3, [pc, #360] @ (8017624 ) 80174ba: 681a ldr r2, [r3, #0] 80174bc: 687b ldr r3, [r7, #4] 80174be: 4013 ands r3, r2 80174c0: 2b00 cmp r3, #0 80174c2: f040 8095 bne.w 80175f0 { /* The wanted size is increased so it can contain a BlockLink_t structure in addition to the requested amount of bytes. */ if( xWantedSize > 0 ) 80174c6: 687b ldr r3, [r7, #4] 80174c8: 2b00 cmp r3, #0 80174ca: d01e beq.n 801750a { xWantedSize += xHeapStructSize; 80174cc: 2208 movs r2, #8 80174ce: 687b ldr r3, [r7, #4] 80174d0: 4413 add r3, r2 80174d2: 607b str r3, [r7, #4] /* Ensure that blocks are always aligned to the required number of bytes. */ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) 80174d4: 687b ldr r3, [r7, #4] 80174d6: f003 0307 and.w r3, r3, #7 80174da: 2b00 cmp r3, #0 80174dc: d015 beq.n 801750a { /* Byte alignment required. */ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); 80174de: 687b ldr r3, [r7, #4] 80174e0: f023 0307 bic.w r3, r3, #7 80174e4: 3308 adds r3, #8 80174e6: 607b str r3, [r7, #4] configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); 80174e8: 687b ldr r3, [r7, #4] 80174ea: f003 0307 and.w r3, r3, #7 80174ee: 2b00 cmp r3, #0 80174f0: d00b beq.n 801750a __asm volatile 80174f2: f04f 0350 mov.w r3, #80 @ 0x50 80174f6: f383 8811 msr BASEPRI, r3 80174fa: f3bf 8f6f isb sy 80174fe: f3bf 8f4f dsb sy 8017502: 617b str r3, [r7, #20] } 8017504: bf00 nop 8017506: bf00 nop 8017508: e7fd b.n 8017506 else { mtCOVERAGE_TEST_MARKER(); } if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) 801750a: 687b ldr r3, [r7, #4] 801750c: 2b00 cmp r3, #0 801750e: d06f beq.n 80175f0 8017510: 4b45 ldr r3, [pc, #276] @ (8017628 ) 8017512: 681b ldr r3, [r3, #0] 8017514: 687a ldr r2, [r7, #4] 8017516: 429a cmp r2, r3 8017518: d86a bhi.n 80175f0 { /* Traverse the list from the start (lowest address) block until one of adequate size is found. */ pxPreviousBlock = &xStart; 801751a: 4b44 ldr r3, [pc, #272] @ (801762c ) 801751c: 623b str r3, [r7, #32] pxBlock = xStart.pxNextFreeBlock; 801751e: 4b43 ldr r3, [pc, #268] @ (801762c ) 8017520: 681b ldr r3, [r3, #0] 8017522: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 8017524: e004 b.n 8017530 { pxPreviousBlock = pxBlock; 8017526: 6a7b ldr r3, [r7, #36] @ 0x24 8017528: 623b str r3, [r7, #32] pxBlock = pxBlock->pxNextFreeBlock; 801752a: 6a7b ldr r3, [r7, #36] @ 0x24 801752c: 681b ldr r3, [r3, #0] 801752e: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 8017530: 6a7b ldr r3, [r7, #36] @ 0x24 8017532: 685b ldr r3, [r3, #4] 8017534: 687a ldr r2, [r7, #4] 8017536: 429a cmp r2, r3 8017538: d903 bls.n 8017542 801753a: 6a7b ldr r3, [r7, #36] @ 0x24 801753c: 681b ldr r3, [r3, #0] 801753e: 2b00 cmp r3, #0 8017540: d1f1 bne.n 8017526 } /* If the end marker was reached then a block of adequate size was not found. */ if( pxBlock != pxEnd ) 8017542: 4b37 ldr r3, [pc, #220] @ (8017620 ) 8017544: 681b ldr r3, [r3, #0] 8017546: 6a7a ldr r2, [r7, #36] @ 0x24 8017548: 429a cmp r2, r3 801754a: d051 beq.n 80175f0 { /* Return the memory space pointed to - jumping over the BlockLink_t structure at its start. */ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); 801754c: 6a3b ldr r3, [r7, #32] 801754e: 681b ldr r3, [r3, #0] 8017550: 2208 movs r2, #8 8017552: 4413 add r3, r2 8017554: 61fb str r3, [r7, #28] /* This block is being returned for use so must be taken out of the list of free blocks. */ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; 8017556: 6a7b ldr r3, [r7, #36] @ 0x24 8017558: 681a ldr r2, [r3, #0] 801755a: 6a3b ldr r3, [r7, #32] 801755c: 601a str r2, [r3, #0] /* If the block is larger than required it can be split into two. */ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) 801755e: 6a7b ldr r3, [r7, #36] @ 0x24 8017560: 685a ldr r2, [r3, #4] 8017562: 687b ldr r3, [r7, #4] 8017564: 1ad2 subs r2, r2, r3 8017566: 2308 movs r3, #8 8017568: 005b lsls r3, r3, #1 801756a: 429a cmp r2, r3 801756c: d920 bls.n 80175b0 { /* This block is to be split into two. Create a new block following the number of bytes requested. The void cast is used to prevent byte alignment warnings from the compiler. */ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); 801756e: 6a7a ldr r2, [r7, #36] @ 0x24 8017570: 687b ldr r3, [r7, #4] 8017572: 4413 add r3, r2 8017574: 61bb str r3, [r7, #24] configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); 8017576: 69bb ldr r3, [r7, #24] 8017578: f003 0307 and.w r3, r3, #7 801757c: 2b00 cmp r3, #0 801757e: d00b beq.n 8017598 __asm volatile 8017580: f04f 0350 mov.w r3, #80 @ 0x50 8017584: f383 8811 msr BASEPRI, r3 8017588: f3bf 8f6f isb sy 801758c: f3bf 8f4f dsb sy 8017590: 613b str r3, [r7, #16] } 8017592: bf00 nop 8017594: bf00 nop 8017596: e7fd b.n 8017594 /* Calculate the sizes of two blocks split from the single block. */ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; 8017598: 6a7b ldr r3, [r7, #36] @ 0x24 801759a: 685a ldr r2, [r3, #4] 801759c: 687b ldr r3, [r7, #4] 801759e: 1ad2 subs r2, r2, r3 80175a0: 69bb ldr r3, [r7, #24] 80175a2: 605a str r2, [r3, #4] pxBlock->xBlockSize = xWantedSize; 80175a4: 6a7b ldr r3, [r7, #36] @ 0x24 80175a6: 687a ldr r2, [r7, #4] 80175a8: 605a str r2, [r3, #4] /* Insert the new block into the list of free blocks. */ prvInsertBlockIntoFreeList( pxNewBlockLink ); 80175aa: 69b8 ldr r0, [r7, #24] 80175ac: f000 f90a bl 80177c4 else { mtCOVERAGE_TEST_MARKER(); } xFreeBytesRemaining -= pxBlock->xBlockSize; 80175b0: 4b1d ldr r3, [pc, #116] @ (8017628 ) 80175b2: 681a ldr r2, [r3, #0] 80175b4: 6a7b ldr r3, [r7, #36] @ 0x24 80175b6: 685b ldr r3, [r3, #4] 80175b8: 1ad3 subs r3, r2, r3 80175ba: 4a1b ldr r2, [pc, #108] @ (8017628 ) 80175bc: 6013 str r3, [r2, #0] if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) 80175be: 4b1a ldr r3, [pc, #104] @ (8017628 ) 80175c0: 681a ldr r2, [r3, #0] 80175c2: 4b1b ldr r3, [pc, #108] @ (8017630 ) 80175c4: 681b ldr r3, [r3, #0] 80175c6: 429a cmp r2, r3 80175c8: d203 bcs.n 80175d2 { xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; 80175ca: 4b17 ldr r3, [pc, #92] @ (8017628 ) 80175cc: 681b ldr r3, [r3, #0] 80175ce: 4a18 ldr r2, [pc, #96] @ (8017630 ) 80175d0: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } /* The block is being returned - it is allocated and owned by the application and has no "next" block. */ pxBlock->xBlockSize |= xBlockAllocatedBit; 80175d2: 6a7b ldr r3, [r7, #36] @ 0x24 80175d4: 685a ldr r2, [r3, #4] 80175d6: 4b13 ldr r3, [pc, #76] @ (8017624 ) 80175d8: 681b ldr r3, [r3, #0] 80175da: 431a orrs r2, r3 80175dc: 6a7b ldr r3, [r7, #36] @ 0x24 80175de: 605a str r2, [r3, #4] pxBlock->pxNextFreeBlock = NULL; 80175e0: 6a7b ldr r3, [r7, #36] @ 0x24 80175e2: 2200 movs r2, #0 80175e4: 601a str r2, [r3, #0] xNumberOfSuccessfulAllocations++; 80175e6: 4b13 ldr r3, [pc, #76] @ (8017634 ) 80175e8: 681b ldr r3, [r3, #0] 80175ea: 3301 adds r3, #1 80175ec: 4a11 ldr r2, [pc, #68] @ (8017634 ) 80175ee: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } traceMALLOC( pvReturn, xWantedSize ); } ( void ) xTaskResumeAll(); 80175f0: f7fe f884 bl 80156fc mtCOVERAGE_TEST_MARKER(); } } #endif configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); 80175f4: 69fb ldr r3, [r7, #28] 80175f6: f003 0307 and.w r3, r3, #7 80175fa: 2b00 cmp r3, #0 80175fc: d00b beq.n 8017616 __asm volatile 80175fe: f04f 0350 mov.w r3, #80 @ 0x50 8017602: f383 8811 msr BASEPRI, r3 8017606: f3bf 8f6f isb sy 801760a: f3bf 8f4f dsb sy 801760e: 60fb str r3, [r7, #12] } 8017610: bf00 nop 8017612: bf00 nop 8017614: e7fd b.n 8017612 return pvReturn; 8017616: 69fb ldr r3, [r7, #28] } 8017618: 4618 mov r0, r3 801761a: 3728 adds r7, #40 @ 0x28 801761c: 46bd mov sp, r7 801761e: bd80 pop {r7, pc} 8017620: 24013050 .word 0x24013050 8017624: 24013064 .word 0x24013064 8017628: 24013054 .word 0x24013054 801762c: 24013048 .word 0x24013048 8017630: 24013058 .word 0x24013058 8017634: 2401305c .word 0x2401305c 08017638 : /*-----------------------------------------------------------*/ void vPortFree( void *pv ) { 8017638: b580 push {r7, lr} 801763a: b086 sub sp, #24 801763c: af00 add r7, sp, #0 801763e: 6078 str r0, [r7, #4] uint8_t *puc = ( uint8_t * ) pv; 8017640: 687b ldr r3, [r7, #4] 8017642: 617b str r3, [r7, #20] BlockLink_t *pxLink; if( pv != NULL ) 8017644: 687b ldr r3, [r7, #4] 8017646: 2b00 cmp r3, #0 8017648: d04f beq.n 80176ea { /* The memory being freed will have an BlockLink_t structure immediately before it. */ puc -= xHeapStructSize; 801764a: 2308 movs r3, #8 801764c: 425b negs r3, r3 801764e: 697a ldr r2, [r7, #20] 8017650: 4413 add r3, r2 8017652: 617b str r3, [r7, #20] /* This casting is to keep the compiler from issuing warnings. */ pxLink = ( void * ) puc; 8017654: 697b ldr r3, [r7, #20] 8017656: 613b str r3, [r7, #16] /* Check the block is actually allocated. */ configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); 8017658: 693b ldr r3, [r7, #16] 801765a: 685a ldr r2, [r3, #4] 801765c: 4b25 ldr r3, [pc, #148] @ (80176f4 ) 801765e: 681b ldr r3, [r3, #0] 8017660: 4013 ands r3, r2 8017662: 2b00 cmp r3, #0 8017664: d10b bne.n 801767e __asm volatile 8017666: f04f 0350 mov.w r3, #80 @ 0x50 801766a: f383 8811 msr BASEPRI, r3 801766e: f3bf 8f6f isb sy 8017672: f3bf 8f4f dsb sy 8017676: 60fb str r3, [r7, #12] } 8017678: bf00 nop 801767a: bf00 nop 801767c: e7fd b.n 801767a configASSERT( pxLink->pxNextFreeBlock == NULL ); 801767e: 693b ldr r3, [r7, #16] 8017680: 681b ldr r3, [r3, #0] 8017682: 2b00 cmp r3, #0 8017684: d00b beq.n 801769e __asm volatile 8017686: f04f 0350 mov.w r3, #80 @ 0x50 801768a: f383 8811 msr BASEPRI, r3 801768e: f3bf 8f6f isb sy 8017692: f3bf 8f4f dsb sy 8017696: 60bb str r3, [r7, #8] } 8017698: bf00 nop 801769a: bf00 nop 801769c: e7fd b.n 801769a if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) 801769e: 693b ldr r3, [r7, #16] 80176a0: 685a ldr r2, [r3, #4] 80176a2: 4b14 ldr r3, [pc, #80] @ (80176f4 ) 80176a4: 681b ldr r3, [r3, #0] 80176a6: 4013 ands r3, r2 80176a8: 2b00 cmp r3, #0 80176aa: d01e beq.n 80176ea { if( pxLink->pxNextFreeBlock == NULL ) 80176ac: 693b ldr r3, [r7, #16] 80176ae: 681b ldr r3, [r3, #0] 80176b0: 2b00 cmp r3, #0 80176b2: d11a bne.n 80176ea { /* The block is being returned to the heap - it is no longer allocated. */ pxLink->xBlockSize &= ~xBlockAllocatedBit; 80176b4: 693b ldr r3, [r7, #16] 80176b6: 685a ldr r2, [r3, #4] 80176b8: 4b0e ldr r3, [pc, #56] @ (80176f4 ) 80176ba: 681b ldr r3, [r3, #0] 80176bc: 43db mvns r3, r3 80176be: 401a ands r2, r3 80176c0: 693b ldr r3, [r7, #16] 80176c2: 605a str r2, [r3, #4] vTaskSuspendAll(); 80176c4: f7fe f80c bl 80156e0 { /* Add this block to the list of free blocks. */ xFreeBytesRemaining += pxLink->xBlockSize; 80176c8: 693b ldr r3, [r7, #16] 80176ca: 685a ldr r2, [r3, #4] 80176cc: 4b0a ldr r3, [pc, #40] @ (80176f8 ) 80176ce: 681b ldr r3, [r3, #0] 80176d0: 4413 add r3, r2 80176d2: 4a09 ldr r2, [pc, #36] @ (80176f8 ) 80176d4: 6013 str r3, [r2, #0] traceFREE( pv, pxLink->xBlockSize ); prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); 80176d6: 6938 ldr r0, [r7, #16] 80176d8: f000 f874 bl 80177c4 xNumberOfSuccessfulFrees++; 80176dc: 4b07 ldr r3, [pc, #28] @ (80176fc ) 80176de: 681b ldr r3, [r3, #0] 80176e0: 3301 adds r3, #1 80176e2: 4a06 ldr r2, [pc, #24] @ (80176fc ) 80176e4: 6013 str r3, [r2, #0] } ( void ) xTaskResumeAll(); 80176e6: f7fe f809 bl 80156fc else { mtCOVERAGE_TEST_MARKER(); } } } 80176ea: bf00 nop 80176ec: 3718 adds r7, #24 80176ee: 46bd mov sp, r7 80176f0: bd80 pop {r7, pc} 80176f2: bf00 nop 80176f4: 24013064 .word 0x24013064 80176f8: 24013054 .word 0x24013054 80176fc: 24013060 .word 0x24013060 08017700 : /* This just exists to keep the linker quiet. */ } /*-----------------------------------------------------------*/ static void prvHeapInit( void ) { 8017700: b480 push {r7} 8017702: b085 sub sp, #20 8017704: af00 add r7, sp, #0 BlockLink_t *pxFirstFreeBlock; uint8_t *pucAlignedHeap; size_t uxAddress; size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; 8017706: f44f 3380 mov.w r3, #65536 @ 0x10000 801770a: 60bb str r3, [r7, #8] /* Ensure the heap starts on a correctly aligned boundary. */ uxAddress = ( size_t ) ucHeap; 801770c: 4b27 ldr r3, [pc, #156] @ (80177ac ) 801770e: 60fb str r3, [r7, #12] if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) 8017710: 68fb ldr r3, [r7, #12] 8017712: f003 0307 and.w r3, r3, #7 8017716: 2b00 cmp r3, #0 8017718: d00c beq.n 8017734 { uxAddress += ( portBYTE_ALIGNMENT - 1 ); 801771a: 68fb ldr r3, [r7, #12] 801771c: 3307 adds r3, #7 801771e: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 8017720: 68fb ldr r3, [r7, #12] 8017722: f023 0307 bic.w r3, r3, #7 8017726: 60fb str r3, [r7, #12] xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; 8017728: 68ba ldr r2, [r7, #8] 801772a: 68fb ldr r3, [r7, #12] 801772c: 1ad3 subs r3, r2, r3 801772e: 4a1f ldr r2, [pc, #124] @ (80177ac ) 8017730: 4413 add r3, r2 8017732: 60bb str r3, [r7, #8] } pucAlignedHeap = ( uint8_t * ) uxAddress; 8017734: 68fb ldr r3, [r7, #12] 8017736: 607b str r3, [r7, #4] /* xStart is used to hold a pointer to the first item in the list of free blocks. The void cast is used to prevent compiler warnings. */ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; 8017738: 4a1d ldr r2, [pc, #116] @ (80177b0 ) 801773a: 687b ldr r3, [r7, #4] 801773c: 6013 str r3, [r2, #0] xStart.xBlockSize = ( size_t ) 0; 801773e: 4b1c ldr r3, [pc, #112] @ (80177b0 ) 8017740: 2200 movs r2, #0 8017742: 605a str r2, [r3, #4] /* pxEnd is used to mark the end of the list of free blocks and is inserted at the end of the heap space. */ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; 8017744: 687b ldr r3, [r7, #4] 8017746: 68ba ldr r2, [r7, #8] 8017748: 4413 add r3, r2 801774a: 60fb str r3, [r7, #12] uxAddress -= xHeapStructSize; 801774c: 2208 movs r2, #8 801774e: 68fb ldr r3, [r7, #12] 8017750: 1a9b subs r3, r3, r2 8017752: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 8017754: 68fb ldr r3, [r7, #12] 8017756: f023 0307 bic.w r3, r3, #7 801775a: 60fb str r3, [r7, #12] pxEnd = ( void * ) uxAddress; 801775c: 68fb ldr r3, [r7, #12] 801775e: 4a15 ldr r2, [pc, #84] @ (80177b4 ) 8017760: 6013 str r3, [r2, #0] pxEnd->xBlockSize = 0; 8017762: 4b14 ldr r3, [pc, #80] @ (80177b4 ) 8017764: 681b ldr r3, [r3, #0] 8017766: 2200 movs r2, #0 8017768: 605a str r2, [r3, #4] pxEnd->pxNextFreeBlock = NULL; 801776a: 4b12 ldr r3, [pc, #72] @ (80177b4 ) 801776c: 681b ldr r3, [r3, #0] 801776e: 2200 movs r2, #0 8017770: 601a str r2, [r3, #0] /* To start with there is a single free block that is sized to take up the entire heap space, minus the space taken by pxEnd. */ pxFirstFreeBlock = ( void * ) pucAlignedHeap; 8017772: 687b ldr r3, [r7, #4] 8017774: 603b str r3, [r7, #0] pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; 8017776: 683b ldr r3, [r7, #0] 8017778: 68fa ldr r2, [r7, #12] 801777a: 1ad2 subs r2, r2, r3 801777c: 683b ldr r3, [r7, #0] 801777e: 605a str r2, [r3, #4] pxFirstFreeBlock->pxNextFreeBlock = pxEnd; 8017780: 4b0c ldr r3, [pc, #48] @ (80177b4 ) 8017782: 681a ldr r2, [r3, #0] 8017784: 683b ldr r3, [r7, #0] 8017786: 601a str r2, [r3, #0] /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8017788: 683b ldr r3, [r7, #0] 801778a: 685b ldr r3, [r3, #4] 801778c: 4a0a ldr r2, [pc, #40] @ (80177b8 ) 801778e: 6013 str r3, [r2, #0] xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8017790: 683b ldr r3, [r7, #0] 8017792: 685b ldr r3, [r3, #4] 8017794: 4a09 ldr r2, [pc, #36] @ (80177bc ) 8017796: 6013 str r3, [r2, #0] /* Work out the position of the top bit in a size_t variable. */ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); 8017798: 4b09 ldr r3, [pc, #36] @ (80177c0 ) 801779a: f04f 4200 mov.w r2, #2147483648 @ 0x80000000 801779e: 601a str r2, [r3, #0] } 80177a0: bf00 nop 80177a2: 3714 adds r7, #20 80177a4: 46bd mov sp, r7 80177a6: f85d 7b04 ldr.w r7, [sp], #4 80177aa: 4770 bx lr 80177ac: 24003048 .word 0x24003048 80177b0: 24013048 .word 0x24013048 80177b4: 24013050 .word 0x24013050 80177b8: 24013058 .word 0x24013058 80177bc: 24013054 .word 0x24013054 80177c0: 24013064 .word 0x24013064 080177c4 : /*-----------------------------------------------------------*/ static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) { 80177c4: b480 push {r7} 80177c6: b085 sub sp, #20 80177c8: af00 add r7, sp, #0 80177ca: 6078 str r0, [r7, #4] BlockLink_t *pxIterator; uint8_t *puc; /* Iterate through the list until a block is found that has a higher address than the block being inserted. */ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) 80177cc: 4b28 ldr r3, [pc, #160] @ (8017870 ) 80177ce: 60fb str r3, [r7, #12] 80177d0: e002 b.n 80177d8 80177d2: 68fb ldr r3, [r7, #12] 80177d4: 681b ldr r3, [r3, #0] 80177d6: 60fb str r3, [r7, #12] 80177d8: 68fb ldr r3, [r7, #12] 80177da: 681b ldr r3, [r3, #0] 80177dc: 687a ldr r2, [r7, #4] 80177de: 429a cmp r2, r3 80177e0: d8f7 bhi.n 80177d2 /* Nothing to do here, just iterate to the right position. */ } /* Do the block being inserted, and the block it is being inserted after make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; 80177e2: 68fb ldr r3, [r7, #12] 80177e4: 60bb str r3, [r7, #8] if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) 80177e6: 68fb ldr r3, [r7, #12] 80177e8: 685b ldr r3, [r3, #4] 80177ea: 68ba ldr r2, [r7, #8] 80177ec: 4413 add r3, r2 80177ee: 687a ldr r2, [r7, #4] 80177f0: 429a cmp r2, r3 80177f2: d108 bne.n 8017806 { pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 80177f4: 68fb ldr r3, [r7, #12] 80177f6: 685a ldr r2, [r3, #4] 80177f8: 687b ldr r3, [r7, #4] 80177fa: 685b ldr r3, [r3, #4] 80177fc: 441a add r2, r3 80177fe: 68fb ldr r3, [r7, #12] 8017800: 605a str r2, [r3, #4] pxBlockToInsert = pxIterator; 8017802: 68fb ldr r3, [r7, #12] 8017804: 607b str r3, [r7, #4] mtCOVERAGE_TEST_MARKER(); } /* Do the block being inserted, and the block it is being inserted before make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; 8017806: 687b ldr r3, [r7, #4] 8017808: 60bb str r3, [r7, #8] if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 801780a: 687b ldr r3, [r7, #4] 801780c: 685b ldr r3, [r3, #4] 801780e: 68ba ldr r2, [r7, #8] 8017810: 441a add r2, r3 8017812: 68fb ldr r3, [r7, #12] 8017814: 681b ldr r3, [r3, #0] 8017816: 429a cmp r2, r3 8017818: d118 bne.n 801784c { if( pxIterator->pxNextFreeBlock != pxEnd ) 801781a: 68fb ldr r3, [r7, #12] 801781c: 681a ldr r2, [r3, #0] 801781e: 4b15 ldr r3, [pc, #84] @ (8017874 ) 8017820: 681b ldr r3, [r3, #0] 8017822: 429a cmp r2, r3 8017824: d00d beq.n 8017842 { /* Form one big block from the two blocks. */ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; 8017826: 687b ldr r3, [r7, #4] 8017828: 685a ldr r2, [r3, #4] 801782a: 68fb ldr r3, [r7, #12] 801782c: 681b ldr r3, [r3, #0] 801782e: 685b ldr r3, [r3, #4] 8017830: 441a add r2, r3 8017832: 687b ldr r3, [r7, #4] 8017834: 605a str r2, [r3, #4] pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; 8017836: 68fb ldr r3, [r7, #12] 8017838: 681b ldr r3, [r3, #0] 801783a: 681a ldr r2, [r3, #0] 801783c: 687b ldr r3, [r7, #4] 801783e: 601a str r2, [r3, #0] 8017840: e008 b.n 8017854 } else { pxBlockToInsert->pxNextFreeBlock = pxEnd; 8017842: 4b0c ldr r3, [pc, #48] @ (8017874 ) 8017844: 681a ldr r2, [r3, #0] 8017846: 687b ldr r3, [r7, #4] 8017848: 601a str r2, [r3, #0] 801784a: e003 b.n 8017854 } } else { pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; 801784c: 68fb ldr r3, [r7, #12] 801784e: 681a ldr r2, [r3, #0] 8017850: 687b ldr r3, [r7, #4] 8017852: 601a str r2, [r3, #0] /* If the block being inserted plugged a gab, so was merged with the block before and the block after, then it's pxNextFreeBlock pointer will have already been set, and should not be set here as that would make it point to itself. */ if( pxIterator != pxBlockToInsert ) 8017854: 68fa ldr r2, [r7, #12] 8017856: 687b ldr r3, [r7, #4] 8017858: 429a cmp r2, r3 801785a: d002 beq.n 8017862 { pxIterator->pxNextFreeBlock = pxBlockToInsert; 801785c: 68fb ldr r3, [r7, #12] 801785e: 687a ldr r2, [r7, #4] 8017860: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 8017862: bf00 nop 8017864: 3714 adds r7, #20 8017866: 46bd mov sp, r7 8017868: f85d 7b04 ldr.w r7, [sp], #4 801786c: 4770 bx lr 801786e: bf00 nop 8017870: 24013048 .word 0x24013048 8017874: 24013050 .word 0x24013050 08017878 : 8017878: 2300 movs r3, #0 801787a: b510 push {r4, lr} 801787c: 4604 mov r4, r0 801787e: e9c0 3300 strd r3, r3, [r0] 8017882: e9c0 3304 strd r3, r3, [r0, #16] 8017886: 6083 str r3, [r0, #8] 8017888: 8181 strh r1, [r0, #12] 801788a: 6643 str r3, [r0, #100] @ 0x64 801788c: 81c2 strh r2, [r0, #14] 801788e: 6183 str r3, [r0, #24] 8017890: 4619 mov r1, r3 8017892: 2208 movs r2, #8 8017894: 305c adds r0, #92 @ 0x5c 8017896: f000 f9f9 bl 8017c8c 801789a: 4b0d ldr r3, [pc, #52] @ (80178d0 ) 801789c: 6263 str r3, [r4, #36] @ 0x24 801789e: 4b0d ldr r3, [pc, #52] @ (80178d4 ) 80178a0: 62a3 str r3, [r4, #40] @ 0x28 80178a2: 4b0d ldr r3, [pc, #52] @ (80178d8 ) 80178a4: 62e3 str r3, [r4, #44] @ 0x2c 80178a6: 4b0d ldr r3, [pc, #52] @ (80178dc ) 80178a8: 6323 str r3, [r4, #48] @ 0x30 80178aa: 4b0d ldr r3, [pc, #52] @ (80178e0 ) 80178ac: 6224 str r4, [r4, #32] 80178ae: 429c cmp r4, r3 80178b0: d006 beq.n 80178c0 80178b2: f103 0268 add.w r2, r3, #104 @ 0x68 80178b6: 4294 cmp r4, r2 80178b8: d002 beq.n 80178c0 80178ba: 33d0 adds r3, #208 @ 0xd0 80178bc: 429c cmp r4, r3 80178be: d105 bne.n 80178cc 80178c0: f104 0058 add.w r0, r4, #88 @ 0x58 80178c4: e8bd 4010 ldmia.w sp!, {r4, lr} 80178c8: f000 baae b.w 8017e28 <__retarget_lock_init_recursive> 80178cc: bd10 pop {r4, pc} 80178ce: bf00 nop 80178d0: 08017add .word 0x08017add 80178d4: 08017aff .word 0x08017aff 80178d8: 08017b37 .word 0x08017b37 80178dc: 08017b5b .word 0x08017b5b 80178e0: 24013068 .word 0x24013068 080178e4 : 80178e4: 4a02 ldr r2, [pc, #8] @ (80178f0 ) 80178e6: 4903 ldr r1, [pc, #12] @ (80178f4 ) 80178e8: 4803 ldr r0, [pc, #12] @ (80178f8 ) 80178ea: f000 b869 b.w 80179c0 <_fwalk_sglue> 80178ee: bf00 nop 80178f0: 24000048 .word 0x24000048 80178f4: 080186e5 .word 0x080186e5 80178f8: 24000058 .word 0x24000058 080178fc : 80178fc: 6841 ldr r1, [r0, #4] 80178fe: 4b0c ldr r3, [pc, #48] @ (8017930 ) 8017900: 4299 cmp r1, r3 8017902: b510 push {r4, lr} 8017904: 4604 mov r4, r0 8017906: d001 beq.n 801790c 8017908: f000 feec bl 80186e4 <_fflush_r> 801790c: 68a1 ldr r1, [r4, #8] 801790e: 4b09 ldr r3, [pc, #36] @ (8017934 ) 8017910: 4299 cmp r1, r3 8017912: d002 beq.n 801791a 8017914: 4620 mov r0, r4 8017916: f000 fee5 bl 80186e4 <_fflush_r> 801791a: 68e1 ldr r1, [r4, #12] 801791c: 4b06 ldr r3, [pc, #24] @ (8017938 ) 801791e: 4299 cmp r1, r3 8017920: d004 beq.n 801792c 8017922: 4620 mov r0, r4 8017924: e8bd 4010 ldmia.w sp!, {r4, lr} 8017928: f000 bedc b.w 80186e4 <_fflush_r> 801792c: bd10 pop {r4, pc} 801792e: bf00 nop 8017930: 24013068 .word 0x24013068 8017934: 240130d0 .word 0x240130d0 8017938: 24013138 .word 0x24013138 0801793c : 801793c: b510 push {r4, lr} 801793e: 4b0b ldr r3, [pc, #44] @ (801796c ) 8017940: 4c0b ldr r4, [pc, #44] @ (8017970 ) 8017942: 4a0c ldr r2, [pc, #48] @ (8017974 ) 8017944: 601a str r2, [r3, #0] 8017946: 4620 mov r0, r4 8017948: 2200 movs r2, #0 801794a: 2104 movs r1, #4 801794c: f7ff ff94 bl 8017878 8017950: f104 0068 add.w r0, r4, #104 @ 0x68 8017954: 2201 movs r2, #1 8017956: 2109 movs r1, #9 8017958: f7ff ff8e bl 8017878 801795c: f104 00d0 add.w r0, r4, #208 @ 0xd0 8017960: 2202 movs r2, #2 8017962: e8bd 4010 ldmia.w sp!, {r4, lr} 8017966: 2112 movs r1, #18 8017968: f7ff bf86 b.w 8017878 801796c: 240131a0 .word 0x240131a0 8017970: 24013068 .word 0x24013068 8017974: 080178e5 .word 0x080178e5 08017978 <__sfp_lock_acquire>: 8017978: 4801 ldr r0, [pc, #4] @ (8017980 <__sfp_lock_acquire+0x8>) 801797a: f000 ba56 b.w 8017e2a <__retarget_lock_acquire_recursive> 801797e: bf00 nop 8017980: 240131a9 .word 0x240131a9 08017984 <__sfp_lock_release>: 8017984: 4801 ldr r0, [pc, #4] @ (801798c <__sfp_lock_release+0x8>) 8017986: f000 ba51 b.w 8017e2c <__retarget_lock_release_recursive> 801798a: bf00 nop 801798c: 240131a9 .word 0x240131a9 08017990 <__sinit>: 8017990: b510 push {r4, lr} 8017992: 4604 mov r4, r0 8017994: f7ff fff0 bl 8017978 <__sfp_lock_acquire> 8017998: 6a23 ldr r3, [r4, #32] 801799a: b11b cbz r3, 80179a4 <__sinit+0x14> 801799c: e8bd 4010 ldmia.w sp!, {r4, lr} 80179a0: f7ff bff0 b.w 8017984 <__sfp_lock_release> 80179a4: 4b04 ldr r3, [pc, #16] @ (80179b8 <__sinit+0x28>) 80179a6: 6223 str r3, [r4, #32] 80179a8: 4b04 ldr r3, [pc, #16] @ (80179bc <__sinit+0x2c>) 80179aa: 681b ldr r3, [r3, #0] 80179ac: 2b00 cmp r3, #0 80179ae: d1f5 bne.n 801799c <__sinit+0xc> 80179b0: f7ff ffc4 bl 801793c 80179b4: e7f2 b.n 801799c <__sinit+0xc> 80179b6: bf00 nop 80179b8: 080178fd .word 0x080178fd 80179bc: 240131a0 .word 0x240131a0 080179c0 <_fwalk_sglue>: 80179c0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 80179c4: 4607 mov r7, r0 80179c6: 4688 mov r8, r1 80179c8: 4614 mov r4, r2 80179ca: 2600 movs r6, #0 80179cc: e9d4 9501 ldrd r9, r5, [r4, #4] 80179d0: f1b9 0901 subs.w r9, r9, #1 80179d4: d505 bpl.n 80179e2 <_fwalk_sglue+0x22> 80179d6: 6824 ldr r4, [r4, #0] 80179d8: 2c00 cmp r4, #0 80179da: d1f7 bne.n 80179cc <_fwalk_sglue+0xc> 80179dc: 4630 mov r0, r6 80179de: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 80179e2: 89ab ldrh r3, [r5, #12] 80179e4: 2b01 cmp r3, #1 80179e6: d907 bls.n 80179f8 <_fwalk_sglue+0x38> 80179e8: f9b5 300e ldrsh.w r3, [r5, #14] 80179ec: 3301 adds r3, #1 80179ee: d003 beq.n 80179f8 <_fwalk_sglue+0x38> 80179f0: 4629 mov r1, r5 80179f2: 4638 mov r0, r7 80179f4: 47c0 blx r8 80179f6: 4306 orrs r6, r0 80179f8: 3568 adds r5, #104 @ 0x68 80179fa: e7e9 b.n 80179d0 <_fwalk_sglue+0x10> 080179fc : 80179fc: b40f push {r0, r1, r2, r3} 80179fe: b507 push {r0, r1, r2, lr} 8017a00: 4906 ldr r1, [pc, #24] @ (8017a1c ) 8017a02: ab04 add r3, sp, #16 8017a04: 6808 ldr r0, [r1, #0] 8017a06: f853 2b04 ldr.w r2, [r3], #4 8017a0a: 6881 ldr r1, [r0, #8] 8017a0c: 9301 str r3, [sp, #4] 8017a0e: f000 fb3f bl 8018090 <_vfiprintf_r> 8017a12: b003 add sp, #12 8017a14: f85d eb04 ldr.w lr, [sp], #4 8017a18: b004 add sp, #16 8017a1a: 4770 bx lr 8017a1c: 24000054 .word 0x24000054 08017a20 <_puts_r>: 8017a20: 6a03 ldr r3, [r0, #32] 8017a22: b570 push {r4, r5, r6, lr} 8017a24: 6884 ldr r4, [r0, #8] 8017a26: 4605 mov r5, r0 8017a28: 460e mov r6, r1 8017a2a: b90b cbnz r3, 8017a30 <_puts_r+0x10> 8017a2c: f7ff ffb0 bl 8017990 <__sinit> 8017a30: 6e63 ldr r3, [r4, #100] @ 0x64 8017a32: 07db lsls r3, r3, #31 8017a34: d405 bmi.n 8017a42 <_puts_r+0x22> 8017a36: 89a3 ldrh r3, [r4, #12] 8017a38: 0598 lsls r0, r3, #22 8017a3a: d402 bmi.n 8017a42 <_puts_r+0x22> 8017a3c: 6da0 ldr r0, [r4, #88] @ 0x58 8017a3e: f000 f9f4 bl 8017e2a <__retarget_lock_acquire_recursive> 8017a42: 89a3 ldrh r3, [r4, #12] 8017a44: 0719 lsls r1, r3, #28 8017a46: d502 bpl.n 8017a4e <_puts_r+0x2e> 8017a48: 6923 ldr r3, [r4, #16] 8017a4a: 2b00 cmp r3, #0 8017a4c: d135 bne.n 8017aba <_puts_r+0x9a> 8017a4e: 4621 mov r1, r4 8017a50: 4628 mov r0, r5 8017a52: f000 f8c5 bl 8017be0 <__swsetup_r> 8017a56: b380 cbz r0, 8017aba <_puts_r+0x9a> 8017a58: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff 8017a5c: 6e63 ldr r3, [r4, #100] @ 0x64 8017a5e: 07da lsls r2, r3, #31 8017a60: d405 bmi.n 8017a6e <_puts_r+0x4e> 8017a62: 89a3 ldrh r3, [r4, #12] 8017a64: 059b lsls r3, r3, #22 8017a66: d402 bmi.n 8017a6e <_puts_r+0x4e> 8017a68: 6da0 ldr r0, [r4, #88] @ 0x58 8017a6a: f000 f9df bl 8017e2c <__retarget_lock_release_recursive> 8017a6e: 4628 mov r0, r5 8017a70: bd70 pop {r4, r5, r6, pc} 8017a72: 2b00 cmp r3, #0 8017a74: da04 bge.n 8017a80 <_puts_r+0x60> 8017a76: 69a2 ldr r2, [r4, #24] 8017a78: 429a cmp r2, r3 8017a7a: dc17 bgt.n 8017aac <_puts_r+0x8c> 8017a7c: 290a cmp r1, #10 8017a7e: d015 beq.n 8017aac <_puts_r+0x8c> 8017a80: 6823 ldr r3, [r4, #0] 8017a82: 1c5a adds r2, r3, #1 8017a84: 6022 str r2, [r4, #0] 8017a86: 7019 strb r1, [r3, #0] 8017a88: 68a3 ldr r3, [r4, #8] 8017a8a: f816 1f01 ldrb.w r1, [r6, #1]! 8017a8e: 3b01 subs r3, #1 8017a90: 60a3 str r3, [r4, #8] 8017a92: 2900 cmp r1, #0 8017a94: d1ed bne.n 8017a72 <_puts_r+0x52> 8017a96: 2b00 cmp r3, #0 8017a98: da11 bge.n 8017abe <_puts_r+0x9e> 8017a9a: 4622 mov r2, r4 8017a9c: 210a movs r1, #10 8017a9e: 4628 mov r0, r5 8017aa0: f000 f85f bl 8017b62 <__swbuf_r> 8017aa4: 3001 adds r0, #1 8017aa6: d0d7 beq.n 8017a58 <_puts_r+0x38> 8017aa8: 250a movs r5, #10 8017aaa: e7d7 b.n 8017a5c <_puts_r+0x3c> 8017aac: 4622 mov r2, r4 8017aae: 4628 mov r0, r5 8017ab0: f000 f857 bl 8017b62 <__swbuf_r> 8017ab4: 3001 adds r0, #1 8017ab6: d1e7 bne.n 8017a88 <_puts_r+0x68> 8017ab8: e7ce b.n 8017a58 <_puts_r+0x38> 8017aba: 3e01 subs r6, #1 8017abc: e7e4 b.n 8017a88 <_puts_r+0x68> 8017abe: 6823 ldr r3, [r4, #0] 8017ac0: 1c5a adds r2, r3, #1 8017ac2: 6022 str r2, [r4, #0] 8017ac4: 220a movs r2, #10 8017ac6: 701a strb r2, [r3, #0] 8017ac8: e7ee b.n 8017aa8 <_puts_r+0x88> ... 08017acc : 8017acc: 4b02 ldr r3, [pc, #8] @ (8017ad8 ) 8017ace: 4601 mov r1, r0 8017ad0: 6818 ldr r0, [r3, #0] 8017ad2: f7ff bfa5 b.w 8017a20 <_puts_r> 8017ad6: bf00 nop 8017ad8: 24000054 .word 0x24000054 08017adc <__sread>: 8017adc: b510 push {r4, lr} 8017ade: 460c mov r4, r1 8017ae0: f9b1 100e ldrsh.w r1, [r1, #14] 8017ae4: f000 f952 bl 8017d8c <_read_r> 8017ae8: 2800 cmp r0, #0 8017aea: bfab itete ge 8017aec: 6d63 ldrge r3, [r4, #84] @ 0x54 8017aee: 89a3 ldrhlt r3, [r4, #12] 8017af0: 181b addge r3, r3, r0 8017af2: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 8017af6: bfac ite ge 8017af8: 6563 strge r3, [r4, #84] @ 0x54 8017afa: 81a3 strhlt r3, [r4, #12] 8017afc: bd10 pop {r4, pc} 08017afe <__swrite>: 8017afe: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8017b02: 461f mov r7, r3 8017b04: 898b ldrh r3, [r1, #12] 8017b06: 05db lsls r3, r3, #23 8017b08: 4605 mov r5, r0 8017b0a: 460c mov r4, r1 8017b0c: 4616 mov r6, r2 8017b0e: d505 bpl.n 8017b1c <__swrite+0x1e> 8017b10: f9b1 100e ldrsh.w r1, [r1, #14] 8017b14: 2302 movs r3, #2 8017b16: 2200 movs r2, #0 8017b18: f000 f926 bl 8017d68 <_lseek_r> 8017b1c: 89a3 ldrh r3, [r4, #12] 8017b1e: f9b4 100e ldrsh.w r1, [r4, #14] 8017b22: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8017b26: 81a3 strh r3, [r4, #12] 8017b28: 4632 mov r2, r6 8017b2a: 463b mov r3, r7 8017b2c: 4628 mov r0, r5 8017b2e: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8017b32: f000 b93d b.w 8017db0 <_write_r> 08017b36 <__sseek>: 8017b36: b510 push {r4, lr} 8017b38: 460c mov r4, r1 8017b3a: f9b1 100e ldrsh.w r1, [r1, #14] 8017b3e: f000 f913 bl 8017d68 <_lseek_r> 8017b42: 1c43 adds r3, r0, #1 8017b44: 89a3 ldrh r3, [r4, #12] 8017b46: bf15 itete ne 8017b48: 6560 strne r0, [r4, #84] @ 0x54 8017b4a: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 8017b4e: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 8017b52: 81a3 strheq r3, [r4, #12] 8017b54: bf18 it ne 8017b56: 81a3 strhne r3, [r4, #12] 8017b58: bd10 pop {r4, pc} 08017b5a <__sclose>: 8017b5a: f9b1 100e ldrsh.w r1, [r1, #14] 8017b5e: f000 b89d b.w 8017c9c <_close_r> 08017b62 <__swbuf_r>: 8017b62: b5f8 push {r3, r4, r5, r6, r7, lr} 8017b64: 460e mov r6, r1 8017b66: 4614 mov r4, r2 8017b68: 4605 mov r5, r0 8017b6a: b118 cbz r0, 8017b74 <__swbuf_r+0x12> 8017b6c: 6a03 ldr r3, [r0, #32] 8017b6e: b90b cbnz r3, 8017b74 <__swbuf_r+0x12> 8017b70: f7ff ff0e bl 8017990 <__sinit> 8017b74: 69a3 ldr r3, [r4, #24] 8017b76: 60a3 str r3, [r4, #8] 8017b78: 89a3 ldrh r3, [r4, #12] 8017b7a: 071a lsls r2, r3, #28 8017b7c: d501 bpl.n 8017b82 <__swbuf_r+0x20> 8017b7e: 6923 ldr r3, [r4, #16] 8017b80: b943 cbnz r3, 8017b94 <__swbuf_r+0x32> 8017b82: 4621 mov r1, r4 8017b84: 4628 mov r0, r5 8017b86: f000 f82b bl 8017be0 <__swsetup_r> 8017b8a: b118 cbz r0, 8017b94 <__swbuf_r+0x32> 8017b8c: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff 8017b90: 4638 mov r0, r7 8017b92: bdf8 pop {r3, r4, r5, r6, r7, pc} 8017b94: 6823 ldr r3, [r4, #0] 8017b96: 6922 ldr r2, [r4, #16] 8017b98: 1a98 subs r0, r3, r2 8017b9a: 6963 ldr r3, [r4, #20] 8017b9c: b2f6 uxtb r6, r6 8017b9e: 4283 cmp r3, r0 8017ba0: 4637 mov r7, r6 8017ba2: dc05 bgt.n 8017bb0 <__swbuf_r+0x4e> 8017ba4: 4621 mov r1, r4 8017ba6: 4628 mov r0, r5 8017ba8: f000 fd9c bl 80186e4 <_fflush_r> 8017bac: 2800 cmp r0, #0 8017bae: d1ed bne.n 8017b8c <__swbuf_r+0x2a> 8017bb0: 68a3 ldr r3, [r4, #8] 8017bb2: 3b01 subs r3, #1 8017bb4: 60a3 str r3, [r4, #8] 8017bb6: 6823 ldr r3, [r4, #0] 8017bb8: 1c5a adds r2, r3, #1 8017bba: 6022 str r2, [r4, #0] 8017bbc: 701e strb r6, [r3, #0] 8017bbe: 6962 ldr r2, [r4, #20] 8017bc0: 1c43 adds r3, r0, #1 8017bc2: 429a cmp r2, r3 8017bc4: d004 beq.n 8017bd0 <__swbuf_r+0x6e> 8017bc6: 89a3 ldrh r3, [r4, #12] 8017bc8: 07db lsls r3, r3, #31 8017bca: d5e1 bpl.n 8017b90 <__swbuf_r+0x2e> 8017bcc: 2e0a cmp r6, #10 8017bce: d1df bne.n 8017b90 <__swbuf_r+0x2e> 8017bd0: 4621 mov r1, r4 8017bd2: 4628 mov r0, r5 8017bd4: f000 fd86 bl 80186e4 <_fflush_r> 8017bd8: 2800 cmp r0, #0 8017bda: d0d9 beq.n 8017b90 <__swbuf_r+0x2e> 8017bdc: e7d6 b.n 8017b8c <__swbuf_r+0x2a> ... 08017be0 <__swsetup_r>: 8017be0: b538 push {r3, r4, r5, lr} 8017be2: 4b29 ldr r3, [pc, #164] @ (8017c88 <__swsetup_r+0xa8>) 8017be4: 4605 mov r5, r0 8017be6: 6818 ldr r0, [r3, #0] 8017be8: 460c mov r4, r1 8017bea: b118 cbz r0, 8017bf4 <__swsetup_r+0x14> 8017bec: 6a03 ldr r3, [r0, #32] 8017bee: b90b cbnz r3, 8017bf4 <__swsetup_r+0x14> 8017bf0: f7ff fece bl 8017990 <__sinit> 8017bf4: f9b4 300c ldrsh.w r3, [r4, #12] 8017bf8: 0719 lsls r1, r3, #28 8017bfa: d422 bmi.n 8017c42 <__swsetup_r+0x62> 8017bfc: 06da lsls r2, r3, #27 8017bfe: d407 bmi.n 8017c10 <__swsetup_r+0x30> 8017c00: 2209 movs r2, #9 8017c02: 602a str r2, [r5, #0] 8017c04: f043 0340 orr.w r3, r3, #64 @ 0x40 8017c08: 81a3 strh r3, [r4, #12] 8017c0a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8017c0e: e033 b.n 8017c78 <__swsetup_r+0x98> 8017c10: 0758 lsls r0, r3, #29 8017c12: d512 bpl.n 8017c3a <__swsetup_r+0x5a> 8017c14: 6b61 ldr r1, [r4, #52] @ 0x34 8017c16: b141 cbz r1, 8017c2a <__swsetup_r+0x4a> 8017c18: f104 0344 add.w r3, r4, #68 @ 0x44 8017c1c: 4299 cmp r1, r3 8017c1e: d002 beq.n 8017c26 <__swsetup_r+0x46> 8017c20: 4628 mov r0, r5 8017c22: f000 f913 bl 8017e4c <_free_r> 8017c26: 2300 movs r3, #0 8017c28: 6363 str r3, [r4, #52] @ 0x34 8017c2a: 89a3 ldrh r3, [r4, #12] 8017c2c: f023 0324 bic.w r3, r3, #36 @ 0x24 8017c30: 81a3 strh r3, [r4, #12] 8017c32: 2300 movs r3, #0 8017c34: 6063 str r3, [r4, #4] 8017c36: 6923 ldr r3, [r4, #16] 8017c38: 6023 str r3, [r4, #0] 8017c3a: 89a3 ldrh r3, [r4, #12] 8017c3c: f043 0308 orr.w r3, r3, #8 8017c40: 81a3 strh r3, [r4, #12] 8017c42: 6923 ldr r3, [r4, #16] 8017c44: b94b cbnz r3, 8017c5a <__swsetup_r+0x7a> 8017c46: 89a3 ldrh r3, [r4, #12] 8017c48: f403 7320 and.w r3, r3, #640 @ 0x280 8017c4c: f5b3 7f00 cmp.w r3, #512 @ 0x200 8017c50: d003 beq.n 8017c5a <__swsetup_r+0x7a> 8017c52: 4621 mov r1, r4 8017c54: 4628 mov r0, r5 8017c56: f000 fd93 bl 8018780 <__smakebuf_r> 8017c5a: f9b4 300c ldrsh.w r3, [r4, #12] 8017c5e: f013 0201 ands.w r2, r3, #1 8017c62: d00a beq.n 8017c7a <__swsetup_r+0x9a> 8017c64: 2200 movs r2, #0 8017c66: 60a2 str r2, [r4, #8] 8017c68: 6962 ldr r2, [r4, #20] 8017c6a: 4252 negs r2, r2 8017c6c: 61a2 str r2, [r4, #24] 8017c6e: 6922 ldr r2, [r4, #16] 8017c70: b942 cbnz r2, 8017c84 <__swsetup_r+0xa4> 8017c72: f013 0080 ands.w r0, r3, #128 @ 0x80 8017c76: d1c5 bne.n 8017c04 <__swsetup_r+0x24> 8017c78: bd38 pop {r3, r4, r5, pc} 8017c7a: 0799 lsls r1, r3, #30 8017c7c: bf58 it pl 8017c7e: 6962 ldrpl r2, [r4, #20] 8017c80: 60a2 str r2, [r4, #8] 8017c82: e7f4 b.n 8017c6e <__swsetup_r+0x8e> 8017c84: 2000 movs r0, #0 8017c86: e7f7 b.n 8017c78 <__swsetup_r+0x98> 8017c88: 24000054 .word 0x24000054 08017c8c : 8017c8c: 4402 add r2, r0 8017c8e: 4603 mov r3, r0 8017c90: 4293 cmp r3, r2 8017c92: d100 bne.n 8017c96 8017c94: 4770 bx lr 8017c96: f803 1b01 strb.w r1, [r3], #1 8017c9a: e7f9 b.n 8017c90 08017c9c <_close_r>: 8017c9c: b538 push {r3, r4, r5, lr} 8017c9e: 4d06 ldr r5, [pc, #24] @ (8017cb8 <_close_r+0x1c>) 8017ca0: 2300 movs r3, #0 8017ca2: 4604 mov r4, r0 8017ca4: 4608 mov r0, r1 8017ca6: 602b str r3, [r5, #0] 8017ca8: f7ec fced bl 8004686 <_close> 8017cac: 1c43 adds r3, r0, #1 8017cae: d102 bne.n 8017cb6 <_close_r+0x1a> 8017cb0: 682b ldr r3, [r5, #0] 8017cb2: b103 cbz r3, 8017cb6 <_close_r+0x1a> 8017cb4: 6023 str r3, [r4, #0] 8017cb6: bd38 pop {r3, r4, r5, pc} 8017cb8: 240131a4 .word 0x240131a4 08017cbc <_reclaim_reent>: 8017cbc: 4b29 ldr r3, [pc, #164] @ (8017d64 <_reclaim_reent+0xa8>) 8017cbe: 681b ldr r3, [r3, #0] 8017cc0: 4283 cmp r3, r0 8017cc2: b570 push {r4, r5, r6, lr} 8017cc4: 4604 mov r4, r0 8017cc6: d04b beq.n 8017d60 <_reclaim_reent+0xa4> 8017cc8: 69c3 ldr r3, [r0, #28] 8017cca: b1ab cbz r3, 8017cf8 <_reclaim_reent+0x3c> 8017ccc: 68db ldr r3, [r3, #12] 8017cce: b16b cbz r3, 8017cec <_reclaim_reent+0x30> 8017cd0: 2500 movs r5, #0 8017cd2: 69e3 ldr r3, [r4, #28] 8017cd4: 68db ldr r3, [r3, #12] 8017cd6: 5959 ldr r1, [r3, r5] 8017cd8: 2900 cmp r1, #0 8017cda: d13b bne.n 8017d54 <_reclaim_reent+0x98> 8017cdc: 3504 adds r5, #4 8017cde: 2d80 cmp r5, #128 @ 0x80 8017ce0: d1f7 bne.n 8017cd2 <_reclaim_reent+0x16> 8017ce2: 69e3 ldr r3, [r4, #28] 8017ce4: 4620 mov r0, r4 8017ce6: 68d9 ldr r1, [r3, #12] 8017ce8: f000 f8b0 bl 8017e4c <_free_r> 8017cec: 69e3 ldr r3, [r4, #28] 8017cee: 6819 ldr r1, [r3, #0] 8017cf0: b111 cbz r1, 8017cf8 <_reclaim_reent+0x3c> 8017cf2: 4620 mov r0, r4 8017cf4: f000 f8aa bl 8017e4c <_free_r> 8017cf8: 6961 ldr r1, [r4, #20] 8017cfa: b111 cbz r1, 8017d02 <_reclaim_reent+0x46> 8017cfc: 4620 mov r0, r4 8017cfe: f000 f8a5 bl 8017e4c <_free_r> 8017d02: 69e1 ldr r1, [r4, #28] 8017d04: b111 cbz r1, 8017d0c <_reclaim_reent+0x50> 8017d06: 4620 mov r0, r4 8017d08: f000 f8a0 bl 8017e4c <_free_r> 8017d0c: 6b21 ldr r1, [r4, #48] @ 0x30 8017d0e: b111 cbz r1, 8017d16 <_reclaim_reent+0x5a> 8017d10: 4620 mov r0, r4 8017d12: f000 f89b bl 8017e4c <_free_r> 8017d16: 6b61 ldr r1, [r4, #52] @ 0x34 8017d18: b111 cbz r1, 8017d20 <_reclaim_reent+0x64> 8017d1a: 4620 mov r0, r4 8017d1c: f000 f896 bl 8017e4c <_free_r> 8017d20: 6ba1 ldr r1, [r4, #56] @ 0x38 8017d22: b111 cbz r1, 8017d2a <_reclaim_reent+0x6e> 8017d24: 4620 mov r0, r4 8017d26: f000 f891 bl 8017e4c <_free_r> 8017d2a: 6ca1 ldr r1, [r4, #72] @ 0x48 8017d2c: b111 cbz r1, 8017d34 <_reclaim_reent+0x78> 8017d2e: 4620 mov r0, r4 8017d30: f000 f88c bl 8017e4c <_free_r> 8017d34: 6c61 ldr r1, [r4, #68] @ 0x44 8017d36: b111 cbz r1, 8017d3e <_reclaim_reent+0x82> 8017d38: 4620 mov r0, r4 8017d3a: f000 f887 bl 8017e4c <_free_r> 8017d3e: 6ae1 ldr r1, [r4, #44] @ 0x2c 8017d40: b111 cbz r1, 8017d48 <_reclaim_reent+0x8c> 8017d42: 4620 mov r0, r4 8017d44: f000 f882 bl 8017e4c <_free_r> 8017d48: 6a23 ldr r3, [r4, #32] 8017d4a: b14b cbz r3, 8017d60 <_reclaim_reent+0xa4> 8017d4c: 4620 mov r0, r4 8017d4e: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} 8017d52: 4718 bx r3 8017d54: 680e ldr r6, [r1, #0] 8017d56: 4620 mov r0, r4 8017d58: f000 f878 bl 8017e4c <_free_r> 8017d5c: 4631 mov r1, r6 8017d5e: e7bb b.n 8017cd8 <_reclaim_reent+0x1c> 8017d60: bd70 pop {r4, r5, r6, pc} 8017d62: bf00 nop 8017d64: 24000054 .word 0x24000054 08017d68 <_lseek_r>: 8017d68: b538 push {r3, r4, r5, lr} 8017d6a: 4d07 ldr r5, [pc, #28] @ (8017d88 <_lseek_r+0x20>) 8017d6c: 4604 mov r4, r0 8017d6e: 4608 mov r0, r1 8017d70: 4611 mov r1, r2 8017d72: 2200 movs r2, #0 8017d74: 602a str r2, [r5, #0] 8017d76: 461a mov r2, r3 8017d78: f7ec fcac bl 80046d4 <_lseek> 8017d7c: 1c43 adds r3, r0, #1 8017d7e: d102 bne.n 8017d86 <_lseek_r+0x1e> 8017d80: 682b ldr r3, [r5, #0] 8017d82: b103 cbz r3, 8017d86 <_lseek_r+0x1e> 8017d84: 6023 str r3, [r4, #0] 8017d86: bd38 pop {r3, r4, r5, pc} 8017d88: 240131a4 .word 0x240131a4 08017d8c <_read_r>: 8017d8c: b538 push {r3, r4, r5, lr} 8017d8e: 4d07 ldr r5, [pc, #28] @ (8017dac <_read_r+0x20>) 8017d90: 4604 mov r4, r0 8017d92: 4608 mov r0, r1 8017d94: 4611 mov r1, r2 8017d96: 2200 movs r2, #0 8017d98: 602a str r2, [r5, #0] 8017d9a: 461a mov r2, r3 8017d9c: f7ec fc3a bl 8004614 <_read> 8017da0: 1c43 adds r3, r0, #1 8017da2: d102 bne.n 8017daa <_read_r+0x1e> 8017da4: 682b ldr r3, [r5, #0] 8017da6: b103 cbz r3, 8017daa <_read_r+0x1e> 8017da8: 6023 str r3, [r4, #0] 8017daa: bd38 pop {r3, r4, r5, pc} 8017dac: 240131a4 .word 0x240131a4 08017db0 <_write_r>: 8017db0: b538 push {r3, r4, r5, lr} 8017db2: 4d07 ldr r5, [pc, #28] @ (8017dd0 <_write_r+0x20>) 8017db4: 4604 mov r4, r0 8017db6: 4608 mov r0, r1 8017db8: 4611 mov r1, r2 8017dba: 2200 movs r2, #0 8017dbc: 602a str r2, [r5, #0] 8017dbe: 461a mov r2, r3 8017dc0: f7ec fc45 bl 800464e <_write> 8017dc4: 1c43 adds r3, r0, #1 8017dc6: d102 bne.n 8017dce <_write_r+0x1e> 8017dc8: 682b ldr r3, [r5, #0] 8017dca: b103 cbz r3, 8017dce <_write_r+0x1e> 8017dcc: 6023 str r3, [r4, #0] 8017dce: bd38 pop {r3, r4, r5, pc} 8017dd0: 240131a4 .word 0x240131a4 08017dd4 <__errno>: 8017dd4: 4b01 ldr r3, [pc, #4] @ (8017ddc <__errno+0x8>) 8017dd6: 6818 ldr r0, [r3, #0] 8017dd8: 4770 bx lr 8017dda: bf00 nop 8017ddc: 24000054 .word 0x24000054 08017de0 <__libc_init_array>: 8017de0: b570 push {r4, r5, r6, lr} 8017de2: 4d0d ldr r5, [pc, #52] @ (8017e18 <__libc_init_array+0x38>) 8017de4: 4c0d ldr r4, [pc, #52] @ (8017e1c <__libc_init_array+0x3c>) 8017de6: 1b64 subs r4, r4, r5 8017de8: 10a4 asrs r4, r4, #2 8017dea: 2600 movs r6, #0 8017dec: 42a6 cmp r6, r4 8017dee: d109 bne.n 8017e04 <__libc_init_array+0x24> 8017df0: 4d0b ldr r5, [pc, #44] @ (8017e20 <__libc_init_array+0x40>) 8017df2: 4c0c ldr r4, [pc, #48] @ (8017e24 <__libc_init_array+0x44>) 8017df4: f000 fdd4 bl 80189a0 <_init> 8017df8: 1b64 subs r4, r4, r5 8017dfa: 10a4 asrs r4, r4, #2 8017dfc: 2600 movs r6, #0 8017dfe: 42a6 cmp r6, r4 8017e00: d105 bne.n 8017e0e <__libc_init_array+0x2e> 8017e02: bd70 pop {r4, r5, r6, pc} 8017e04: f855 3b04 ldr.w r3, [r5], #4 8017e08: 4798 blx r3 8017e0a: 3601 adds r6, #1 8017e0c: e7ee b.n 8017dec <__libc_init_array+0xc> 8017e0e: f855 3b04 ldr.w r3, [r5], #4 8017e12: 4798 blx r3 8017e14: 3601 adds r6, #1 8017e16: e7f2 b.n 8017dfe <__libc_init_array+0x1e> 8017e18: 08018be0 .word 0x08018be0 8017e1c: 08018be0 .word 0x08018be0 8017e20: 08018be0 .word 0x08018be0 8017e24: 08018be4 .word 0x08018be4 08017e28 <__retarget_lock_init_recursive>: 8017e28: 4770 bx lr 08017e2a <__retarget_lock_acquire_recursive>: 8017e2a: 4770 bx lr 08017e2c <__retarget_lock_release_recursive>: 8017e2c: 4770 bx lr 08017e2e : 8017e2e: 440a add r2, r1 8017e30: 4291 cmp r1, r2 8017e32: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8017e36: d100 bne.n 8017e3a 8017e38: 4770 bx lr 8017e3a: b510 push {r4, lr} 8017e3c: f811 4b01 ldrb.w r4, [r1], #1 8017e40: f803 4f01 strb.w r4, [r3, #1]! 8017e44: 4291 cmp r1, r2 8017e46: d1f9 bne.n 8017e3c 8017e48: bd10 pop {r4, pc} ... 08017e4c <_free_r>: 8017e4c: b538 push {r3, r4, r5, lr} 8017e4e: 4605 mov r5, r0 8017e50: 2900 cmp r1, #0 8017e52: d041 beq.n 8017ed8 <_free_r+0x8c> 8017e54: f851 3c04 ldr.w r3, [r1, #-4] 8017e58: 1f0c subs r4, r1, #4 8017e5a: 2b00 cmp r3, #0 8017e5c: bfb8 it lt 8017e5e: 18e4 addlt r4, r4, r3 8017e60: f000 f8e0 bl 8018024 <__malloc_lock> 8017e64: 4a1d ldr r2, [pc, #116] @ (8017edc <_free_r+0x90>) 8017e66: 6813 ldr r3, [r2, #0] 8017e68: b933 cbnz r3, 8017e78 <_free_r+0x2c> 8017e6a: 6063 str r3, [r4, #4] 8017e6c: 6014 str r4, [r2, #0] 8017e6e: 4628 mov r0, r5 8017e70: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8017e74: f000 b8dc b.w 8018030 <__malloc_unlock> 8017e78: 42a3 cmp r3, r4 8017e7a: d908 bls.n 8017e8e <_free_r+0x42> 8017e7c: 6820 ldr r0, [r4, #0] 8017e7e: 1821 adds r1, r4, r0 8017e80: 428b cmp r3, r1 8017e82: bf01 itttt eq 8017e84: 6819 ldreq r1, [r3, #0] 8017e86: 685b ldreq r3, [r3, #4] 8017e88: 1809 addeq r1, r1, r0 8017e8a: 6021 streq r1, [r4, #0] 8017e8c: e7ed b.n 8017e6a <_free_r+0x1e> 8017e8e: 461a mov r2, r3 8017e90: 685b ldr r3, [r3, #4] 8017e92: b10b cbz r3, 8017e98 <_free_r+0x4c> 8017e94: 42a3 cmp r3, r4 8017e96: d9fa bls.n 8017e8e <_free_r+0x42> 8017e98: 6811 ldr r1, [r2, #0] 8017e9a: 1850 adds r0, r2, r1 8017e9c: 42a0 cmp r0, r4 8017e9e: d10b bne.n 8017eb8 <_free_r+0x6c> 8017ea0: 6820 ldr r0, [r4, #0] 8017ea2: 4401 add r1, r0 8017ea4: 1850 adds r0, r2, r1 8017ea6: 4283 cmp r3, r0 8017ea8: 6011 str r1, [r2, #0] 8017eaa: d1e0 bne.n 8017e6e <_free_r+0x22> 8017eac: 6818 ldr r0, [r3, #0] 8017eae: 685b ldr r3, [r3, #4] 8017eb0: 6053 str r3, [r2, #4] 8017eb2: 4408 add r0, r1 8017eb4: 6010 str r0, [r2, #0] 8017eb6: e7da b.n 8017e6e <_free_r+0x22> 8017eb8: d902 bls.n 8017ec0 <_free_r+0x74> 8017eba: 230c movs r3, #12 8017ebc: 602b str r3, [r5, #0] 8017ebe: e7d6 b.n 8017e6e <_free_r+0x22> 8017ec0: 6820 ldr r0, [r4, #0] 8017ec2: 1821 adds r1, r4, r0 8017ec4: 428b cmp r3, r1 8017ec6: bf04 itt eq 8017ec8: 6819 ldreq r1, [r3, #0] 8017eca: 685b ldreq r3, [r3, #4] 8017ecc: 6063 str r3, [r4, #4] 8017ece: bf04 itt eq 8017ed0: 1809 addeq r1, r1, r0 8017ed2: 6021 streq r1, [r4, #0] 8017ed4: 6054 str r4, [r2, #4] 8017ed6: e7ca b.n 8017e6e <_free_r+0x22> 8017ed8: bd38 pop {r3, r4, r5, pc} 8017eda: bf00 nop 8017edc: 240131b0 .word 0x240131b0 08017ee0 : 8017ee0: b570 push {r4, r5, r6, lr} 8017ee2: 4e0f ldr r6, [pc, #60] @ (8017f20 ) 8017ee4: 460c mov r4, r1 8017ee6: 6831 ldr r1, [r6, #0] 8017ee8: 4605 mov r5, r0 8017eea: b911 cbnz r1, 8017ef2 8017eec: f000 fca6 bl 801883c <_sbrk_r> 8017ef0: 6030 str r0, [r6, #0] 8017ef2: 4621 mov r1, r4 8017ef4: 4628 mov r0, r5 8017ef6: f000 fca1 bl 801883c <_sbrk_r> 8017efa: 1c43 adds r3, r0, #1 8017efc: d103 bne.n 8017f06 8017efe: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 8017f02: 4620 mov r0, r4 8017f04: bd70 pop {r4, r5, r6, pc} 8017f06: 1cc4 adds r4, r0, #3 8017f08: f024 0403 bic.w r4, r4, #3 8017f0c: 42a0 cmp r0, r4 8017f0e: d0f8 beq.n 8017f02 8017f10: 1a21 subs r1, r4, r0 8017f12: 4628 mov r0, r5 8017f14: f000 fc92 bl 801883c <_sbrk_r> 8017f18: 3001 adds r0, #1 8017f1a: d1f2 bne.n 8017f02 8017f1c: e7ef b.n 8017efe 8017f1e: bf00 nop 8017f20: 240131ac .word 0x240131ac 08017f24 <_malloc_r>: 8017f24: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8017f28: 1ccd adds r5, r1, #3 8017f2a: f025 0503 bic.w r5, r5, #3 8017f2e: 3508 adds r5, #8 8017f30: 2d0c cmp r5, #12 8017f32: bf38 it cc 8017f34: 250c movcc r5, #12 8017f36: 2d00 cmp r5, #0 8017f38: 4606 mov r6, r0 8017f3a: db01 blt.n 8017f40 <_malloc_r+0x1c> 8017f3c: 42a9 cmp r1, r5 8017f3e: d904 bls.n 8017f4a <_malloc_r+0x26> 8017f40: 230c movs r3, #12 8017f42: 6033 str r3, [r6, #0] 8017f44: 2000 movs r0, #0 8017f46: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8017f4a: f8df 80d4 ldr.w r8, [pc, #212] @ 8018020 <_malloc_r+0xfc> 8017f4e: f000 f869 bl 8018024 <__malloc_lock> 8017f52: f8d8 3000 ldr.w r3, [r8] 8017f56: 461c mov r4, r3 8017f58: bb44 cbnz r4, 8017fac <_malloc_r+0x88> 8017f5a: 4629 mov r1, r5 8017f5c: 4630 mov r0, r6 8017f5e: f7ff ffbf bl 8017ee0 8017f62: 1c43 adds r3, r0, #1 8017f64: 4604 mov r4, r0 8017f66: d158 bne.n 801801a <_malloc_r+0xf6> 8017f68: f8d8 4000 ldr.w r4, [r8] 8017f6c: 4627 mov r7, r4 8017f6e: 2f00 cmp r7, #0 8017f70: d143 bne.n 8017ffa <_malloc_r+0xd6> 8017f72: 2c00 cmp r4, #0 8017f74: d04b beq.n 801800e <_malloc_r+0xea> 8017f76: 6823 ldr r3, [r4, #0] 8017f78: 4639 mov r1, r7 8017f7a: 4630 mov r0, r6 8017f7c: eb04 0903 add.w r9, r4, r3 8017f80: f000 fc5c bl 801883c <_sbrk_r> 8017f84: 4581 cmp r9, r0 8017f86: d142 bne.n 801800e <_malloc_r+0xea> 8017f88: 6821 ldr r1, [r4, #0] 8017f8a: 1a6d subs r5, r5, r1 8017f8c: 4629 mov r1, r5 8017f8e: 4630 mov r0, r6 8017f90: f7ff ffa6 bl 8017ee0 8017f94: 3001 adds r0, #1 8017f96: d03a beq.n 801800e <_malloc_r+0xea> 8017f98: 6823 ldr r3, [r4, #0] 8017f9a: 442b add r3, r5 8017f9c: 6023 str r3, [r4, #0] 8017f9e: f8d8 3000 ldr.w r3, [r8] 8017fa2: 685a ldr r2, [r3, #4] 8017fa4: bb62 cbnz r2, 8018000 <_malloc_r+0xdc> 8017fa6: f8c8 7000 str.w r7, [r8] 8017faa: e00f b.n 8017fcc <_malloc_r+0xa8> 8017fac: 6822 ldr r2, [r4, #0] 8017fae: 1b52 subs r2, r2, r5 8017fb0: d420 bmi.n 8017ff4 <_malloc_r+0xd0> 8017fb2: 2a0b cmp r2, #11 8017fb4: d917 bls.n 8017fe6 <_malloc_r+0xc2> 8017fb6: 1961 adds r1, r4, r5 8017fb8: 42a3 cmp r3, r4 8017fba: 6025 str r5, [r4, #0] 8017fbc: bf18 it ne 8017fbe: 6059 strne r1, [r3, #4] 8017fc0: 6863 ldr r3, [r4, #4] 8017fc2: bf08 it eq 8017fc4: f8c8 1000 streq.w r1, [r8] 8017fc8: 5162 str r2, [r4, r5] 8017fca: 604b str r3, [r1, #4] 8017fcc: 4630 mov r0, r6 8017fce: f000 f82f bl 8018030 <__malloc_unlock> 8017fd2: f104 000b add.w r0, r4, #11 8017fd6: 1d23 adds r3, r4, #4 8017fd8: f020 0007 bic.w r0, r0, #7 8017fdc: 1ac2 subs r2, r0, r3 8017fde: bf1c itt ne 8017fe0: 1a1b subne r3, r3, r0 8017fe2: 50a3 strne r3, [r4, r2] 8017fe4: e7af b.n 8017f46 <_malloc_r+0x22> 8017fe6: 6862 ldr r2, [r4, #4] 8017fe8: 42a3 cmp r3, r4 8017fea: bf0c ite eq 8017fec: f8c8 2000 streq.w r2, [r8] 8017ff0: 605a strne r2, [r3, #4] 8017ff2: e7eb b.n 8017fcc <_malloc_r+0xa8> 8017ff4: 4623 mov r3, r4 8017ff6: 6864 ldr r4, [r4, #4] 8017ff8: e7ae b.n 8017f58 <_malloc_r+0x34> 8017ffa: 463c mov r4, r7 8017ffc: 687f ldr r7, [r7, #4] 8017ffe: e7b6 b.n 8017f6e <_malloc_r+0x4a> 8018000: 461a mov r2, r3 8018002: 685b ldr r3, [r3, #4] 8018004: 42a3 cmp r3, r4 8018006: d1fb bne.n 8018000 <_malloc_r+0xdc> 8018008: 2300 movs r3, #0 801800a: 6053 str r3, [r2, #4] 801800c: e7de b.n 8017fcc <_malloc_r+0xa8> 801800e: 230c movs r3, #12 8018010: 6033 str r3, [r6, #0] 8018012: 4630 mov r0, r6 8018014: f000 f80c bl 8018030 <__malloc_unlock> 8018018: e794 b.n 8017f44 <_malloc_r+0x20> 801801a: 6005 str r5, [r0, #0] 801801c: e7d6 b.n 8017fcc <_malloc_r+0xa8> 801801e: bf00 nop 8018020: 240131b0 .word 0x240131b0 08018024 <__malloc_lock>: 8018024: 4801 ldr r0, [pc, #4] @ (801802c <__malloc_lock+0x8>) 8018026: f7ff bf00 b.w 8017e2a <__retarget_lock_acquire_recursive> 801802a: bf00 nop 801802c: 240131a8 .word 0x240131a8 08018030 <__malloc_unlock>: 8018030: 4801 ldr r0, [pc, #4] @ (8018038 <__malloc_unlock+0x8>) 8018032: f7ff befb b.w 8017e2c <__retarget_lock_release_recursive> 8018036: bf00 nop 8018038: 240131a8 .word 0x240131a8 0801803c <__sfputc_r>: 801803c: 6893 ldr r3, [r2, #8] 801803e: 3b01 subs r3, #1 8018040: 2b00 cmp r3, #0 8018042: b410 push {r4} 8018044: 6093 str r3, [r2, #8] 8018046: da08 bge.n 801805a <__sfputc_r+0x1e> 8018048: 6994 ldr r4, [r2, #24] 801804a: 42a3 cmp r3, r4 801804c: db01 blt.n 8018052 <__sfputc_r+0x16> 801804e: 290a cmp r1, #10 8018050: d103 bne.n 801805a <__sfputc_r+0x1e> 8018052: f85d 4b04 ldr.w r4, [sp], #4 8018056: f7ff bd84 b.w 8017b62 <__swbuf_r> 801805a: 6813 ldr r3, [r2, #0] 801805c: 1c58 adds r0, r3, #1 801805e: 6010 str r0, [r2, #0] 8018060: 7019 strb r1, [r3, #0] 8018062: 4608 mov r0, r1 8018064: f85d 4b04 ldr.w r4, [sp], #4 8018068: 4770 bx lr 0801806a <__sfputs_r>: 801806a: b5f8 push {r3, r4, r5, r6, r7, lr} 801806c: 4606 mov r6, r0 801806e: 460f mov r7, r1 8018070: 4614 mov r4, r2 8018072: 18d5 adds r5, r2, r3 8018074: 42ac cmp r4, r5 8018076: d101 bne.n 801807c <__sfputs_r+0x12> 8018078: 2000 movs r0, #0 801807a: e007 b.n 801808c <__sfputs_r+0x22> 801807c: f814 1b01 ldrb.w r1, [r4], #1 8018080: 463a mov r2, r7 8018082: 4630 mov r0, r6 8018084: f7ff ffda bl 801803c <__sfputc_r> 8018088: 1c43 adds r3, r0, #1 801808a: d1f3 bne.n 8018074 <__sfputs_r+0xa> 801808c: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 08018090 <_vfiprintf_r>: 8018090: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8018094: 460d mov r5, r1 8018096: b09d sub sp, #116 @ 0x74 8018098: 4614 mov r4, r2 801809a: 4698 mov r8, r3 801809c: 4606 mov r6, r0 801809e: b118 cbz r0, 80180a8 <_vfiprintf_r+0x18> 80180a0: 6a03 ldr r3, [r0, #32] 80180a2: b90b cbnz r3, 80180a8 <_vfiprintf_r+0x18> 80180a4: f7ff fc74 bl 8017990 <__sinit> 80180a8: 6e6b ldr r3, [r5, #100] @ 0x64 80180aa: 07d9 lsls r1, r3, #31 80180ac: d405 bmi.n 80180ba <_vfiprintf_r+0x2a> 80180ae: 89ab ldrh r3, [r5, #12] 80180b0: 059a lsls r2, r3, #22 80180b2: d402 bmi.n 80180ba <_vfiprintf_r+0x2a> 80180b4: 6da8 ldr r0, [r5, #88] @ 0x58 80180b6: f7ff feb8 bl 8017e2a <__retarget_lock_acquire_recursive> 80180ba: 89ab ldrh r3, [r5, #12] 80180bc: 071b lsls r3, r3, #28 80180be: d501 bpl.n 80180c4 <_vfiprintf_r+0x34> 80180c0: 692b ldr r3, [r5, #16] 80180c2: b99b cbnz r3, 80180ec <_vfiprintf_r+0x5c> 80180c4: 4629 mov r1, r5 80180c6: 4630 mov r0, r6 80180c8: f7ff fd8a bl 8017be0 <__swsetup_r> 80180cc: b170 cbz r0, 80180ec <_vfiprintf_r+0x5c> 80180ce: 6e6b ldr r3, [r5, #100] @ 0x64 80180d0: 07dc lsls r4, r3, #31 80180d2: d504 bpl.n 80180de <_vfiprintf_r+0x4e> 80180d4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80180d8: b01d add sp, #116 @ 0x74 80180da: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80180de: 89ab ldrh r3, [r5, #12] 80180e0: 0598 lsls r0, r3, #22 80180e2: d4f7 bmi.n 80180d4 <_vfiprintf_r+0x44> 80180e4: 6da8 ldr r0, [r5, #88] @ 0x58 80180e6: f7ff fea1 bl 8017e2c <__retarget_lock_release_recursive> 80180ea: e7f3 b.n 80180d4 <_vfiprintf_r+0x44> 80180ec: 2300 movs r3, #0 80180ee: 9309 str r3, [sp, #36] @ 0x24 80180f0: 2320 movs r3, #32 80180f2: f88d 3029 strb.w r3, [sp, #41] @ 0x29 80180f6: f8cd 800c str.w r8, [sp, #12] 80180fa: 2330 movs r3, #48 @ 0x30 80180fc: f8df 81ac ldr.w r8, [pc, #428] @ 80182ac <_vfiprintf_r+0x21c> 8018100: f88d 302a strb.w r3, [sp, #42] @ 0x2a 8018104: f04f 0901 mov.w r9, #1 8018108: 4623 mov r3, r4 801810a: 469a mov sl, r3 801810c: f813 2b01 ldrb.w r2, [r3], #1 8018110: b10a cbz r2, 8018116 <_vfiprintf_r+0x86> 8018112: 2a25 cmp r2, #37 @ 0x25 8018114: d1f9 bne.n 801810a <_vfiprintf_r+0x7a> 8018116: ebba 0b04 subs.w fp, sl, r4 801811a: d00b beq.n 8018134 <_vfiprintf_r+0xa4> 801811c: 465b mov r3, fp 801811e: 4622 mov r2, r4 8018120: 4629 mov r1, r5 8018122: 4630 mov r0, r6 8018124: f7ff ffa1 bl 801806a <__sfputs_r> 8018128: 3001 adds r0, #1 801812a: f000 80a7 beq.w 801827c <_vfiprintf_r+0x1ec> 801812e: 9a09 ldr r2, [sp, #36] @ 0x24 8018130: 445a add r2, fp 8018132: 9209 str r2, [sp, #36] @ 0x24 8018134: f89a 3000 ldrb.w r3, [sl] 8018138: 2b00 cmp r3, #0 801813a: f000 809f beq.w 801827c <_vfiprintf_r+0x1ec> 801813e: 2300 movs r3, #0 8018140: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8018144: e9cd 2305 strd r2, r3, [sp, #20] 8018148: f10a 0a01 add.w sl, sl, #1 801814c: 9304 str r3, [sp, #16] 801814e: 9307 str r3, [sp, #28] 8018150: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8018154: 931a str r3, [sp, #104] @ 0x68 8018156: 4654 mov r4, sl 8018158: 2205 movs r2, #5 801815a: f814 1b01 ldrb.w r1, [r4], #1 801815e: 4853 ldr r0, [pc, #332] @ (80182ac <_vfiprintf_r+0x21c>) 8018160: f7e8 f8be bl 80002e0 8018164: 9a04 ldr r2, [sp, #16] 8018166: b9d8 cbnz r0, 80181a0 <_vfiprintf_r+0x110> 8018168: 06d1 lsls r1, r2, #27 801816a: bf44 itt mi 801816c: 2320 movmi r3, #32 801816e: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8018172: 0713 lsls r3, r2, #28 8018174: bf44 itt mi 8018176: 232b movmi r3, #43 @ 0x2b 8018178: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 801817c: f89a 3000 ldrb.w r3, [sl] 8018180: 2b2a cmp r3, #42 @ 0x2a 8018182: d015 beq.n 80181b0 <_vfiprintf_r+0x120> 8018184: 9a07 ldr r2, [sp, #28] 8018186: 4654 mov r4, sl 8018188: 2000 movs r0, #0 801818a: f04f 0c0a mov.w ip, #10 801818e: 4621 mov r1, r4 8018190: f811 3b01 ldrb.w r3, [r1], #1 8018194: 3b30 subs r3, #48 @ 0x30 8018196: 2b09 cmp r3, #9 8018198: d94b bls.n 8018232 <_vfiprintf_r+0x1a2> 801819a: b1b0 cbz r0, 80181ca <_vfiprintf_r+0x13a> 801819c: 9207 str r2, [sp, #28] 801819e: e014 b.n 80181ca <_vfiprintf_r+0x13a> 80181a0: eba0 0308 sub.w r3, r0, r8 80181a4: fa09 f303 lsl.w r3, r9, r3 80181a8: 4313 orrs r3, r2 80181aa: 9304 str r3, [sp, #16] 80181ac: 46a2 mov sl, r4 80181ae: e7d2 b.n 8018156 <_vfiprintf_r+0xc6> 80181b0: 9b03 ldr r3, [sp, #12] 80181b2: 1d19 adds r1, r3, #4 80181b4: 681b ldr r3, [r3, #0] 80181b6: 9103 str r1, [sp, #12] 80181b8: 2b00 cmp r3, #0 80181ba: bfbb ittet lt 80181bc: 425b neglt r3, r3 80181be: f042 0202 orrlt.w r2, r2, #2 80181c2: 9307 strge r3, [sp, #28] 80181c4: 9307 strlt r3, [sp, #28] 80181c6: bfb8 it lt 80181c8: 9204 strlt r2, [sp, #16] 80181ca: 7823 ldrb r3, [r4, #0] 80181cc: 2b2e cmp r3, #46 @ 0x2e 80181ce: d10a bne.n 80181e6 <_vfiprintf_r+0x156> 80181d0: 7863 ldrb r3, [r4, #1] 80181d2: 2b2a cmp r3, #42 @ 0x2a 80181d4: d132 bne.n 801823c <_vfiprintf_r+0x1ac> 80181d6: 9b03 ldr r3, [sp, #12] 80181d8: 1d1a adds r2, r3, #4 80181da: 681b ldr r3, [r3, #0] 80181dc: 9203 str r2, [sp, #12] 80181de: ea43 73e3 orr.w r3, r3, r3, asr #31 80181e2: 3402 adds r4, #2 80181e4: 9305 str r3, [sp, #20] 80181e6: f8df a0d4 ldr.w sl, [pc, #212] @ 80182bc <_vfiprintf_r+0x22c> 80181ea: 7821 ldrb r1, [r4, #0] 80181ec: 2203 movs r2, #3 80181ee: 4650 mov r0, sl 80181f0: f7e8 f876 bl 80002e0 80181f4: b138 cbz r0, 8018206 <_vfiprintf_r+0x176> 80181f6: 9b04 ldr r3, [sp, #16] 80181f8: eba0 000a sub.w r0, r0, sl 80181fc: 2240 movs r2, #64 @ 0x40 80181fe: 4082 lsls r2, r0 8018200: 4313 orrs r3, r2 8018202: 3401 adds r4, #1 8018204: 9304 str r3, [sp, #16] 8018206: f814 1b01 ldrb.w r1, [r4], #1 801820a: 4829 ldr r0, [pc, #164] @ (80182b0 <_vfiprintf_r+0x220>) 801820c: f88d 1028 strb.w r1, [sp, #40] @ 0x28 8018210: 2206 movs r2, #6 8018212: f7e8 f865 bl 80002e0 8018216: 2800 cmp r0, #0 8018218: d03f beq.n 801829a <_vfiprintf_r+0x20a> 801821a: 4b26 ldr r3, [pc, #152] @ (80182b4 <_vfiprintf_r+0x224>) 801821c: bb1b cbnz r3, 8018266 <_vfiprintf_r+0x1d6> 801821e: 9b03 ldr r3, [sp, #12] 8018220: 3307 adds r3, #7 8018222: f023 0307 bic.w r3, r3, #7 8018226: 3308 adds r3, #8 8018228: 9303 str r3, [sp, #12] 801822a: 9b09 ldr r3, [sp, #36] @ 0x24 801822c: 443b add r3, r7 801822e: 9309 str r3, [sp, #36] @ 0x24 8018230: e76a b.n 8018108 <_vfiprintf_r+0x78> 8018232: fb0c 3202 mla r2, ip, r2, r3 8018236: 460c mov r4, r1 8018238: 2001 movs r0, #1 801823a: e7a8 b.n 801818e <_vfiprintf_r+0xfe> 801823c: 2300 movs r3, #0 801823e: 3401 adds r4, #1 8018240: 9305 str r3, [sp, #20] 8018242: 4619 mov r1, r3 8018244: f04f 0c0a mov.w ip, #10 8018248: 4620 mov r0, r4 801824a: f810 2b01 ldrb.w r2, [r0], #1 801824e: 3a30 subs r2, #48 @ 0x30 8018250: 2a09 cmp r2, #9 8018252: d903 bls.n 801825c <_vfiprintf_r+0x1cc> 8018254: 2b00 cmp r3, #0 8018256: d0c6 beq.n 80181e6 <_vfiprintf_r+0x156> 8018258: 9105 str r1, [sp, #20] 801825a: e7c4 b.n 80181e6 <_vfiprintf_r+0x156> 801825c: fb0c 2101 mla r1, ip, r1, r2 8018260: 4604 mov r4, r0 8018262: 2301 movs r3, #1 8018264: e7f0 b.n 8018248 <_vfiprintf_r+0x1b8> 8018266: ab03 add r3, sp, #12 8018268: 9300 str r3, [sp, #0] 801826a: 462a mov r2, r5 801826c: 4b12 ldr r3, [pc, #72] @ (80182b8 <_vfiprintf_r+0x228>) 801826e: a904 add r1, sp, #16 8018270: 4630 mov r0, r6 8018272: f3af 8000 nop.w 8018276: 4607 mov r7, r0 8018278: 1c78 adds r0, r7, #1 801827a: d1d6 bne.n 801822a <_vfiprintf_r+0x19a> 801827c: 6e6b ldr r3, [r5, #100] @ 0x64 801827e: 07d9 lsls r1, r3, #31 8018280: d405 bmi.n 801828e <_vfiprintf_r+0x1fe> 8018282: 89ab ldrh r3, [r5, #12] 8018284: 059a lsls r2, r3, #22 8018286: d402 bmi.n 801828e <_vfiprintf_r+0x1fe> 8018288: 6da8 ldr r0, [r5, #88] @ 0x58 801828a: f7ff fdcf bl 8017e2c <__retarget_lock_release_recursive> 801828e: 89ab ldrh r3, [r5, #12] 8018290: 065b lsls r3, r3, #25 8018292: f53f af1f bmi.w 80180d4 <_vfiprintf_r+0x44> 8018296: 9809 ldr r0, [sp, #36] @ 0x24 8018298: e71e b.n 80180d8 <_vfiprintf_r+0x48> 801829a: ab03 add r3, sp, #12 801829c: 9300 str r3, [sp, #0] 801829e: 462a mov r2, r5 80182a0: 4b05 ldr r3, [pc, #20] @ (80182b8 <_vfiprintf_r+0x228>) 80182a2: a904 add r1, sp, #16 80182a4: 4630 mov r0, r6 80182a6: f000 f879 bl 801839c <_printf_i> 80182aa: e7e4 b.n 8018276 <_vfiprintf_r+0x1e6> 80182ac: 08018b9c .word 0x08018b9c 80182b0: 08018ba6 .word 0x08018ba6 80182b4: 00000000 .word 0x00000000 80182b8: 0801806b .word 0x0801806b 80182bc: 08018ba2 .word 0x08018ba2 080182c0 <_printf_common>: 80182c0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80182c4: 4616 mov r6, r2 80182c6: 4698 mov r8, r3 80182c8: 688a ldr r2, [r1, #8] 80182ca: 690b ldr r3, [r1, #16] 80182cc: f8dd 9020 ldr.w r9, [sp, #32] 80182d0: 4293 cmp r3, r2 80182d2: bfb8 it lt 80182d4: 4613 movlt r3, r2 80182d6: 6033 str r3, [r6, #0] 80182d8: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 80182dc: 4607 mov r7, r0 80182de: 460c mov r4, r1 80182e0: b10a cbz r2, 80182e6 <_printf_common+0x26> 80182e2: 3301 adds r3, #1 80182e4: 6033 str r3, [r6, #0] 80182e6: 6823 ldr r3, [r4, #0] 80182e8: 0699 lsls r1, r3, #26 80182ea: bf42 ittt mi 80182ec: 6833 ldrmi r3, [r6, #0] 80182ee: 3302 addmi r3, #2 80182f0: 6033 strmi r3, [r6, #0] 80182f2: 6825 ldr r5, [r4, #0] 80182f4: f015 0506 ands.w r5, r5, #6 80182f8: d106 bne.n 8018308 <_printf_common+0x48> 80182fa: f104 0a19 add.w sl, r4, #25 80182fe: 68e3 ldr r3, [r4, #12] 8018300: 6832 ldr r2, [r6, #0] 8018302: 1a9b subs r3, r3, r2 8018304: 42ab cmp r3, r5 8018306: dc26 bgt.n 8018356 <_printf_common+0x96> 8018308: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 801830c: 6822 ldr r2, [r4, #0] 801830e: 3b00 subs r3, #0 8018310: bf18 it ne 8018312: 2301 movne r3, #1 8018314: 0692 lsls r2, r2, #26 8018316: d42b bmi.n 8018370 <_printf_common+0xb0> 8018318: f104 0243 add.w r2, r4, #67 @ 0x43 801831c: 4641 mov r1, r8 801831e: 4638 mov r0, r7 8018320: 47c8 blx r9 8018322: 3001 adds r0, #1 8018324: d01e beq.n 8018364 <_printf_common+0xa4> 8018326: 6823 ldr r3, [r4, #0] 8018328: 6922 ldr r2, [r4, #16] 801832a: f003 0306 and.w r3, r3, #6 801832e: 2b04 cmp r3, #4 8018330: bf02 ittt eq 8018332: 68e5 ldreq r5, [r4, #12] 8018334: 6833 ldreq r3, [r6, #0] 8018336: 1aed subeq r5, r5, r3 8018338: 68a3 ldr r3, [r4, #8] 801833a: bf0c ite eq 801833c: ea25 75e5 biceq.w r5, r5, r5, asr #31 8018340: 2500 movne r5, #0 8018342: 4293 cmp r3, r2 8018344: bfc4 itt gt 8018346: 1a9b subgt r3, r3, r2 8018348: 18ed addgt r5, r5, r3 801834a: 2600 movs r6, #0 801834c: 341a adds r4, #26 801834e: 42b5 cmp r5, r6 8018350: d11a bne.n 8018388 <_printf_common+0xc8> 8018352: 2000 movs r0, #0 8018354: e008 b.n 8018368 <_printf_common+0xa8> 8018356: 2301 movs r3, #1 8018358: 4652 mov r2, sl 801835a: 4641 mov r1, r8 801835c: 4638 mov r0, r7 801835e: 47c8 blx r9 8018360: 3001 adds r0, #1 8018362: d103 bne.n 801836c <_printf_common+0xac> 8018364: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8018368: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801836c: 3501 adds r5, #1 801836e: e7c6 b.n 80182fe <_printf_common+0x3e> 8018370: 18e1 adds r1, r4, r3 8018372: 1c5a adds r2, r3, #1 8018374: 2030 movs r0, #48 @ 0x30 8018376: f881 0043 strb.w r0, [r1, #67] @ 0x43 801837a: 4422 add r2, r4 801837c: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 8018380: f882 1043 strb.w r1, [r2, #67] @ 0x43 8018384: 3302 adds r3, #2 8018386: e7c7 b.n 8018318 <_printf_common+0x58> 8018388: 2301 movs r3, #1 801838a: 4622 mov r2, r4 801838c: 4641 mov r1, r8 801838e: 4638 mov r0, r7 8018390: 47c8 blx r9 8018392: 3001 adds r0, #1 8018394: d0e6 beq.n 8018364 <_printf_common+0xa4> 8018396: 3601 adds r6, #1 8018398: e7d9 b.n 801834e <_printf_common+0x8e> ... 0801839c <_printf_i>: 801839c: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 80183a0: 7e0f ldrb r7, [r1, #24] 80183a2: 9e0c ldr r6, [sp, #48] @ 0x30 80183a4: 2f78 cmp r7, #120 @ 0x78 80183a6: 4691 mov r9, r2 80183a8: 4680 mov r8, r0 80183aa: 460c mov r4, r1 80183ac: 469a mov sl, r3 80183ae: f101 0243 add.w r2, r1, #67 @ 0x43 80183b2: d807 bhi.n 80183c4 <_printf_i+0x28> 80183b4: 2f62 cmp r7, #98 @ 0x62 80183b6: d80a bhi.n 80183ce <_printf_i+0x32> 80183b8: 2f00 cmp r7, #0 80183ba: f000 80d2 beq.w 8018562 <_printf_i+0x1c6> 80183be: 2f58 cmp r7, #88 @ 0x58 80183c0: f000 80b9 beq.w 8018536 <_printf_i+0x19a> 80183c4: f104 0642 add.w r6, r4, #66 @ 0x42 80183c8: f884 7042 strb.w r7, [r4, #66] @ 0x42 80183cc: e03a b.n 8018444 <_printf_i+0xa8> 80183ce: f1a7 0363 sub.w r3, r7, #99 @ 0x63 80183d2: 2b15 cmp r3, #21 80183d4: d8f6 bhi.n 80183c4 <_printf_i+0x28> 80183d6: a101 add r1, pc, #4 @ (adr r1, 80183dc <_printf_i+0x40>) 80183d8: f851 f023 ldr.w pc, [r1, r3, lsl #2] 80183dc: 08018435 .word 0x08018435 80183e0: 08018449 .word 0x08018449 80183e4: 080183c5 .word 0x080183c5 80183e8: 080183c5 .word 0x080183c5 80183ec: 080183c5 .word 0x080183c5 80183f0: 080183c5 .word 0x080183c5 80183f4: 08018449 .word 0x08018449 80183f8: 080183c5 .word 0x080183c5 80183fc: 080183c5 .word 0x080183c5 8018400: 080183c5 .word 0x080183c5 8018404: 080183c5 .word 0x080183c5 8018408: 08018549 .word 0x08018549 801840c: 08018473 .word 0x08018473 8018410: 08018503 .word 0x08018503 8018414: 080183c5 .word 0x080183c5 8018418: 080183c5 .word 0x080183c5 801841c: 0801856b .word 0x0801856b 8018420: 080183c5 .word 0x080183c5 8018424: 08018473 .word 0x08018473 8018428: 080183c5 .word 0x080183c5 801842c: 080183c5 .word 0x080183c5 8018430: 0801850b .word 0x0801850b 8018434: 6833 ldr r3, [r6, #0] 8018436: 1d1a adds r2, r3, #4 8018438: 681b ldr r3, [r3, #0] 801843a: 6032 str r2, [r6, #0] 801843c: f104 0642 add.w r6, r4, #66 @ 0x42 8018440: f884 3042 strb.w r3, [r4, #66] @ 0x42 8018444: 2301 movs r3, #1 8018446: e09d b.n 8018584 <_printf_i+0x1e8> 8018448: 6833 ldr r3, [r6, #0] 801844a: 6820 ldr r0, [r4, #0] 801844c: 1d19 adds r1, r3, #4 801844e: 6031 str r1, [r6, #0] 8018450: 0606 lsls r6, r0, #24 8018452: d501 bpl.n 8018458 <_printf_i+0xbc> 8018454: 681d ldr r5, [r3, #0] 8018456: e003 b.n 8018460 <_printf_i+0xc4> 8018458: 0645 lsls r5, r0, #25 801845a: d5fb bpl.n 8018454 <_printf_i+0xb8> 801845c: f9b3 5000 ldrsh.w r5, [r3] 8018460: 2d00 cmp r5, #0 8018462: da03 bge.n 801846c <_printf_i+0xd0> 8018464: 232d movs r3, #45 @ 0x2d 8018466: 426d negs r5, r5 8018468: f884 3043 strb.w r3, [r4, #67] @ 0x43 801846c: 4859 ldr r0, [pc, #356] @ (80185d4 <_printf_i+0x238>) 801846e: 230a movs r3, #10 8018470: e011 b.n 8018496 <_printf_i+0xfa> 8018472: 6821 ldr r1, [r4, #0] 8018474: 6833 ldr r3, [r6, #0] 8018476: 0608 lsls r0, r1, #24 8018478: f853 5b04 ldr.w r5, [r3], #4 801847c: d402 bmi.n 8018484 <_printf_i+0xe8> 801847e: 0649 lsls r1, r1, #25 8018480: bf48 it mi 8018482: b2ad uxthmi r5, r5 8018484: 2f6f cmp r7, #111 @ 0x6f 8018486: 4853 ldr r0, [pc, #332] @ (80185d4 <_printf_i+0x238>) 8018488: 6033 str r3, [r6, #0] 801848a: bf14 ite ne 801848c: 230a movne r3, #10 801848e: 2308 moveq r3, #8 8018490: 2100 movs r1, #0 8018492: f884 1043 strb.w r1, [r4, #67] @ 0x43 8018496: 6866 ldr r6, [r4, #4] 8018498: 60a6 str r6, [r4, #8] 801849a: 2e00 cmp r6, #0 801849c: bfa2 ittt ge 801849e: 6821 ldrge r1, [r4, #0] 80184a0: f021 0104 bicge.w r1, r1, #4 80184a4: 6021 strge r1, [r4, #0] 80184a6: b90d cbnz r5, 80184ac <_printf_i+0x110> 80184a8: 2e00 cmp r6, #0 80184aa: d04b beq.n 8018544 <_printf_i+0x1a8> 80184ac: 4616 mov r6, r2 80184ae: fbb5 f1f3 udiv r1, r5, r3 80184b2: fb03 5711 mls r7, r3, r1, r5 80184b6: 5dc7 ldrb r7, [r0, r7] 80184b8: f806 7d01 strb.w r7, [r6, #-1]! 80184bc: 462f mov r7, r5 80184be: 42bb cmp r3, r7 80184c0: 460d mov r5, r1 80184c2: d9f4 bls.n 80184ae <_printf_i+0x112> 80184c4: 2b08 cmp r3, #8 80184c6: d10b bne.n 80184e0 <_printf_i+0x144> 80184c8: 6823 ldr r3, [r4, #0] 80184ca: 07df lsls r7, r3, #31 80184cc: d508 bpl.n 80184e0 <_printf_i+0x144> 80184ce: 6923 ldr r3, [r4, #16] 80184d0: 6861 ldr r1, [r4, #4] 80184d2: 4299 cmp r1, r3 80184d4: bfde ittt le 80184d6: 2330 movle r3, #48 @ 0x30 80184d8: f806 3c01 strble.w r3, [r6, #-1] 80184dc: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 80184e0: 1b92 subs r2, r2, r6 80184e2: 6122 str r2, [r4, #16] 80184e4: f8cd a000 str.w sl, [sp] 80184e8: 464b mov r3, r9 80184ea: aa03 add r2, sp, #12 80184ec: 4621 mov r1, r4 80184ee: 4640 mov r0, r8 80184f0: f7ff fee6 bl 80182c0 <_printf_common> 80184f4: 3001 adds r0, #1 80184f6: d14a bne.n 801858e <_printf_i+0x1f2> 80184f8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80184fc: b004 add sp, #16 80184fe: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8018502: 6823 ldr r3, [r4, #0] 8018504: f043 0320 orr.w r3, r3, #32 8018508: 6023 str r3, [r4, #0] 801850a: 4833 ldr r0, [pc, #204] @ (80185d8 <_printf_i+0x23c>) 801850c: 2778 movs r7, #120 @ 0x78 801850e: f884 7045 strb.w r7, [r4, #69] @ 0x45 8018512: 6823 ldr r3, [r4, #0] 8018514: 6831 ldr r1, [r6, #0] 8018516: 061f lsls r7, r3, #24 8018518: f851 5b04 ldr.w r5, [r1], #4 801851c: d402 bmi.n 8018524 <_printf_i+0x188> 801851e: 065f lsls r7, r3, #25 8018520: bf48 it mi 8018522: b2ad uxthmi r5, r5 8018524: 6031 str r1, [r6, #0] 8018526: 07d9 lsls r1, r3, #31 8018528: bf44 itt mi 801852a: f043 0320 orrmi.w r3, r3, #32 801852e: 6023 strmi r3, [r4, #0] 8018530: b11d cbz r5, 801853a <_printf_i+0x19e> 8018532: 2310 movs r3, #16 8018534: e7ac b.n 8018490 <_printf_i+0xf4> 8018536: 4827 ldr r0, [pc, #156] @ (80185d4 <_printf_i+0x238>) 8018538: e7e9 b.n 801850e <_printf_i+0x172> 801853a: 6823 ldr r3, [r4, #0] 801853c: f023 0320 bic.w r3, r3, #32 8018540: 6023 str r3, [r4, #0] 8018542: e7f6 b.n 8018532 <_printf_i+0x196> 8018544: 4616 mov r6, r2 8018546: e7bd b.n 80184c4 <_printf_i+0x128> 8018548: 6833 ldr r3, [r6, #0] 801854a: 6825 ldr r5, [r4, #0] 801854c: 6961 ldr r1, [r4, #20] 801854e: 1d18 adds r0, r3, #4 8018550: 6030 str r0, [r6, #0] 8018552: 062e lsls r6, r5, #24 8018554: 681b ldr r3, [r3, #0] 8018556: d501 bpl.n 801855c <_printf_i+0x1c0> 8018558: 6019 str r1, [r3, #0] 801855a: e002 b.n 8018562 <_printf_i+0x1c6> 801855c: 0668 lsls r0, r5, #25 801855e: d5fb bpl.n 8018558 <_printf_i+0x1bc> 8018560: 8019 strh r1, [r3, #0] 8018562: 2300 movs r3, #0 8018564: 6123 str r3, [r4, #16] 8018566: 4616 mov r6, r2 8018568: e7bc b.n 80184e4 <_printf_i+0x148> 801856a: 6833 ldr r3, [r6, #0] 801856c: 1d1a adds r2, r3, #4 801856e: 6032 str r2, [r6, #0] 8018570: 681e ldr r6, [r3, #0] 8018572: 6862 ldr r2, [r4, #4] 8018574: 2100 movs r1, #0 8018576: 4630 mov r0, r6 8018578: f7e7 feb2 bl 80002e0 801857c: b108 cbz r0, 8018582 <_printf_i+0x1e6> 801857e: 1b80 subs r0, r0, r6 8018580: 6060 str r0, [r4, #4] 8018582: 6863 ldr r3, [r4, #4] 8018584: 6123 str r3, [r4, #16] 8018586: 2300 movs r3, #0 8018588: f884 3043 strb.w r3, [r4, #67] @ 0x43 801858c: e7aa b.n 80184e4 <_printf_i+0x148> 801858e: 6923 ldr r3, [r4, #16] 8018590: 4632 mov r2, r6 8018592: 4649 mov r1, r9 8018594: 4640 mov r0, r8 8018596: 47d0 blx sl 8018598: 3001 adds r0, #1 801859a: d0ad beq.n 80184f8 <_printf_i+0x15c> 801859c: 6823 ldr r3, [r4, #0] 801859e: 079b lsls r3, r3, #30 80185a0: d413 bmi.n 80185ca <_printf_i+0x22e> 80185a2: 68e0 ldr r0, [r4, #12] 80185a4: 9b03 ldr r3, [sp, #12] 80185a6: 4298 cmp r0, r3 80185a8: bfb8 it lt 80185aa: 4618 movlt r0, r3 80185ac: e7a6 b.n 80184fc <_printf_i+0x160> 80185ae: 2301 movs r3, #1 80185b0: 4632 mov r2, r6 80185b2: 4649 mov r1, r9 80185b4: 4640 mov r0, r8 80185b6: 47d0 blx sl 80185b8: 3001 adds r0, #1 80185ba: d09d beq.n 80184f8 <_printf_i+0x15c> 80185bc: 3501 adds r5, #1 80185be: 68e3 ldr r3, [r4, #12] 80185c0: 9903 ldr r1, [sp, #12] 80185c2: 1a5b subs r3, r3, r1 80185c4: 42ab cmp r3, r5 80185c6: dcf2 bgt.n 80185ae <_printf_i+0x212> 80185c8: e7eb b.n 80185a2 <_printf_i+0x206> 80185ca: 2500 movs r5, #0 80185cc: f104 0619 add.w r6, r4, #25 80185d0: e7f5 b.n 80185be <_printf_i+0x222> 80185d2: bf00 nop 80185d4: 08018bad .word 0x08018bad 80185d8: 08018bbe .word 0x08018bbe 080185dc <__sflush_r>: 80185dc: f9b1 200c ldrsh.w r2, [r1, #12] 80185e0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80185e4: 0716 lsls r6, r2, #28 80185e6: 4605 mov r5, r0 80185e8: 460c mov r4, r1 80185ea: d454 bmi.n 8018696 <__sflush_r+0xba> 80185ec: 684b ldr r3, [r1, #4] 80185ee: 2b00 cmp r3, #0 80185f0: dc02 bgt.n 80185f8 <__sflush_r+0x1c> 80185f2: 6c0b ldr r3, [r1, #64] @ 0x40 80185f4: 2b00 cmp r3, #0 80185f6: dd48 ble.n 801868a <__sflush_r+0xae> 80185f8: 6ae6 ldr r6, [r4, #44] @ 0x2c 80185fa: 2e00 cmp r6, #0 80185fc: d045 beq.n 801868a <__sflush_r+0xae> 80185fe: 2300 movs r3, #0 8018600: f412 5280 ands.w r2, r2, #4096 @ 0x1000 8018604: 682f ldr r7, [r5, #0] 8018606: 6a21 ldr r1, [r4, #32] 8018608: 602b str r3, [r5, #0] 801860a: d030 beq.n 801866e <__sflush_r+0x92> 801860c: 6d62 ldr r2, [r4, #84] @ 0x54 801860e: 89a3 ldrh r3, [r4, #12] 8018610: 0759 lsls r1, r3, #29 8018612: d505 bpl.n 8018620 <__sflush_r+0x44> 8018614: 6863 ldr r3, [r4, #4] 8018616: 1ad2 subs r2, r2, r3 8018618: 6b63 ldr r3, [r4, #52] @ 0x34 801861a: b10b cbz r3, 8018620 <__sflush_r+0x44> 801861c: 6c23 ldr r3, [r4, #64] @ 0x40 801861e: 1ad2 subs r2, r2, r3 8018620: 2300 movs r3, #0 8018622: 6ae6 ldr r6, [r4, #44] @ 0x2c 8018624: 6a21 ldr r1, [r4, #32] 8018626: 4628 mov r0, r5 8018628: 47b0 blx r6 801862a: 1c43 adds r3, r0, #1 801862c: 89a3 ldrh r3, [r4, #12] 801862e: d106 bne.n 801863e <__sflush_r+0x62> 8018630: 6829 ldr r1, [r5, #0] 8018632: 291d cmp r1, #29 8018634: d82b bhi.n 801868e <__sflush_r+0xb2> 8018636: 4a2a ldr r2, [pc, #168] @ (80186e0 <__sflush_r+0x104>) 8018638: 410a asrs r2, r1 801863a: 07d6 lsls r6, r2, #31 801863c: d427 bmi.n 801868e <__sflush_r+0xb2> 801863e: 2200 movs r2, #0 8018640: 6062 str r2, [r4, #4] 8018642: 04d9 lsls r1, r3, #19 8018644: 6922 ldr r2, [r4, #16] 8018646: 6022 str r2, [r4, #0] 8018648: d504 bpl.n 8018654 <__sflush_r+0x78> 801864a: 1c42 adds r2, r0, #1 801864c: d101 bne.n 8018652 <__sflush_r+0x76> 801864e: 682b ldr r3, [r5, #0] 8018650: b903 cbnz r3, 8018654 <__sflush_r+0x78> 8018652: 6560 str r0, [r4, #84] @ 0x54 8018654: 6b61 ldr r1, [r4, #52] @ 0x34 8018656: 602f str r7, [r5, #0] 8018658: b1b9 cbz r1, 801868a <__sflush_r+0xae> 801865a: f104 0344 add.w r3, r4, #68 @ 0x44 801865e: 4299 cmp r1, r3 8018660: d002 beq.n 8018668 <__sflush_r+0x8c> 8018662: 4628 mov r0, r5 8018664: f7ff fbf2 bl 8017e4c <_free_r> 8018668: 2300 movs r3, #0 801866a: 6363 str r3, [r4, #52] @ 0x34 801866c: e00d b.n 801868a <__sflush_r+0xae> 801866e: 2301 movs r3, #1 8018670: 4628 mov r0, r5 8018672: 47b0 blx r6 8018674: 4602 mov r2, r0 8018676: 1c50 adds r0, r2, #1 8018678: d1c9 bne.n 801860e <__sflush_r+0x32> 801867a: 682b ldr r3, [r5, #0] 801867c: 2b00 cmp r3, #0 801867e: d0c6 beq.n 801860e <__sflush_r+0x32> 8018680: 2b1d cmp r3, #29 8018682: d001 beq.n 8018688 <__sflush_r+0xac> 8018684: 2b16 cmp r3, #22 8018686: d11e bne.n 80186c6 <__sflush_r+0xea> 8018688: 602f str r7, [r5, #0] 801868a: 2000 movs r0, #0 801868c: e022 b.n 80186d4 <__sflush_r+0xf8> 801868e: f043 0340 orr.w r3, r3, #64 @ 0x40 8018692: b21b sxth r3, r3 8018694: e01b b.n 80186ce <__sflush_r+0xf2> 8018696: 690f ldr r7, [r1, #16] 8018698: 2f00 cmp r7, #0 801869a: d0f6 beq.n 801868a <__sflush_r+0xae> 801869c: 0793 lsls r3, r2, #30 801869e: 680e ldr r6, [r1, #0] 80186a0: bf08 it eq 80186a2: 694b ldreq r3, [r1, #20] 80186a4: 600f str r7, [r1, #0] 80186a6: bf18 it ne 80186a8: 2300 movne r3, #0 80186aa: eba6 0807 sub.w r8, r6, r7 80186ae: 608b str r3, [r1, #8] 80186b0: f1b8 0f00 cmp.w r8, #0 80186b4: dde9 ble.n 801868a <__sflush_r+0xae> 80186b6: 6a21 ldr r1, [r4, #32] 80186b8: 6aa6 ldr r6, [r4, #40] @ 0x28 80186ba: 4643 mov r3, r8 80186bc: 463a mov r2, r7 80186be: 4628 mov r0, r5 80186c0: 47b0 blx r6 80186c2: 2800 cmp r0, #0 80186c4: dc08 bgt.n 80186d8 <__sflush_r+0xfc> 80186c6: f9b4 300c ldrsh.w r3, [r4, #12] 80186ca: f043 0340 orr.w r3, r3, #64 @ 0x40 80186ce: 81a3 strh r3, [r4, #12] 80186d0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80186d4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80186d8: 4407 add r7, r0 80186da: eba8 0800 sub.w r8, r8, r0 80186de: e7e7 b.n 80186b0 <__sflush_r+0xd4> 80186e0: dfbffffe .word 0xdfbffffe 080186e4 <_fflush_r>: 80186e4: b538 push {r3, r4, r5, lr} 80186e6: 690b ldr r3, [r1, #16] 80186e8: 4605 mov r5, r0 80186ea: 460c mov r4, r1 80186ec: b913 cbnz r3, 80186f4 <_fflush_r+0x10> 80186ee: 2500 movs r5, #0 80186f0: 4628 mov r0, r5 80186f2: bd38 pop {r3, r4, r5, pc} 80186f4: b118 cbz r0, 80186fe <_fflush_r+0x1a> 80186f6: 6a03 ldr r3, [r0, #32] 80186f8: b90b cbnz r3, 80186fe <_fflush_r+0x1a> 80186fa: f7ff f949 bl 8017990 <__sinit> 80186fe: f9b4 300c ldrsh.w r3, [r4, #12] 8018702: 2b00 cmp r3, #0 8018704: d0f3 beq.n 80186ee <_fflush_r+0xa> 8018706: 6e62 ldr r2, [r4, #100] @ 0x64 8018708: 07d0 lsls r0, r2, #31 801870a: d404 bmi.n 8018716 <_fflush_r+0x32> 801870c: 0599 lsls r1, r3, #22 801870e: d402 bmi.n 8018716 <_fflush_r+0x32> 8018710: 6da0 ldr r0, [r4, #88] @ 0x58 8018712: f7ff fb8a bl 8017e2a <__retarget_lock_acquire_recursive> 8018716: 4628 mov r0, r5 8018718: 4621 mov r1, r4 801871a: f7ff ff5f bl 80185dc <__sflush_r> 801871e: 6e63 ldr r3, [r4, #100] @ 0x64 8018720: 07da lsls r2, r3, #31 8018722: 4605 mov r5, r0 8018724: d4e4 bmi.n 80186f0 <_fflush_r+0xc> 8018726: 89a3 ldrh r3, [r4, #12] 8018728: 059b lsls r3, r3, #22 801872a: d4e1 bmi.n 80186f0 <_fflush_r+0xc> 801872c: 6da0 ldr r0, [r4, #88] @ 0x58 801872e: f7ff fb7d bl 8017e2c <__retarget_lock_release_recursive> 8018732: e7dd b.n 80186f0 <_fflush_r+0xc> 08018734 <__swhatbuf_r>: 8018734: b570 push {r4, r5, r6, lr} 8018736: 460c mov r4, r1 8018738: f9b1 100e ldrsh.w r1, [r1, #14] 801873c: 2900 cmp r1, #0 801873e: b096 sub sp, #88 @ 0x58 8018740: 4615 mov r5, r2 8018742: 461e mov r6, r3 8018744: da0d bge.n 8018762 <__swhatbuf_r+0x2e> 8018746: 89a3 ldrh r3, [r4, #12] 8018748: f013 0f80 tst.w r3, #128 @ 0x80 801874c: f04f 0100 mov.w r1, #0 8018750: bf14 ite ne 8018752: 2340 movne r3, #64 @ 0x40 8018754: f44f 6380 moveq.w r3, #1024 @ 0x400 8018758: 2000 movs r0, #0 801875a: 6031 str r1, [r6, #0] 801875c: 602b str r3, [r5, #0] 801875e: b016 add sp, #88 @ 0x58 8018760: bd70 pop {r4, r5, r6, pc} 8018762: 466a mov r2, sp 8018764: f000 f848 bl 80187f8 <_fstat_r> 8018768: 2800 cmp r0, #0 801876a: dbec blt.n 8018746 <__swhatbuf_r+0x12> 801876c: 9901 ldr r1, [sp, #4] 801876e: f401 4170 and.w r1, r1, #61440 @ 0xf000 8018772: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 8018776: 4259 negs r1, r3 8018778: 4159 adcs r1, r3 801877a: f44f 6380 mov.w r3, #1024 @ 0x400 801877e: e7eb b.n 8018758 <__swhatbuf_r+0x24> 08018780 <__smakebuf_r>: 8018780: 898b ldrh r3, [r1, #12] 8018782: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8018784: 079d lsls r5, r3, #30 8018786: 4606 mov r6, r0 8018788: 460c mov r4, r1 801878a: d507 bpl.n 801879c <__smakebuf_r+0x1c> 801878c: f104 0347 add.w r3, r4, #71 @ 0x47 8018790: 6023 str r3, [r4, #0] 8018792: 6123 str r3, [r4, #16] 8018794: 2301 movs r3, #1 8018796: 6163 str r3, [r4, #20] 8018798: b003 add sp, #12 801879a: bdf0 pop {r4, r5, r6, r7, pc} 801879c: ab01 add r3, sp, #4 801879e: 466a mov r2, sp 80187a0: f7ff ffc8 bl 8018734 <__swhatbuf_r> 80187a4: 9f00 ldr r7, [sp, #0] 80187a6: 4605 mov r5, r0 80187a8: 4639 mov r1, r7 80187aa: 4630 mov r0, r6 80187ac: f7ff fbba bl 8017f24 <_malloc_r> 80187b0: b948 cbnz r0, 80187c6 <__smakebuf_r+0x46> 80187b2: f9b4 300c ldrsh.w r3, [r4, #12] 80187b6: 059a lsls r2, r3, #22 80187b8: d4ee bmi.n 8018798 <__smakebuf_r+0x18> 80187ba: f023 0303 bic.w r3, r3, #3 80187be: f043 0302 orr.w r3, r3, #2 80187c2: 81a3 strh r3, [r4, #12] 80187c4: e7e2 b.n 801878c <__smakebuf_r+0xc> 80187c6: 89a3 ldrh r3, [r4, #12] 80187c8: 6020 str r0, [r4, #0] 80187ca: f043 0380 orr.w r3, r3, #128 @ 0x80 80187ce: 81a3 strh r3, [r4, #12] 80187d0: 9b01 ldr r3, [sp, #4] 80187d2: e9c4 0704 strd r0, r7, [r4, #16] 80187d6: b15b cbz r3, 80187f0 <__smakebuf_r+0x70> 80187d8: f9b4 100e ldrsh.w r1, [r4, #14] 80187dc: 4630 mov r0, r6 80187de: f000 f81d bl 801881c <_isatty_r> 80187e2: b128 cbz r0, 80187f0 <__smakebuf_r+0x70> 80187e4: 89a3 ldrh r3, [r4, #12] 80187e6: f023 0303 bic.w r3, r3, #3 80187ea: f043 0301 orr.w r3, r3, #1 80187ee: 81a3 strh r3, [r4, #12] 80187f0: 89a3 ldrh r3, [r4, #12] 80187f2: 431d orrs r5, r3 80187f4: 81a5 strh r5, [r4, #12] 80187f6: e7cf b.n 8018798 <__smakebuf_r+0x18> 080187f8 <_fstat_r>: 80187f8: b538 push {r3, r4, r5, lr} 80187fa: 4d07 ldr r5, [pc, #28] @ (8018818 <_fstat_r+0x20>) 80187fc: 2300 movs r3, #0 80187fe: 4604 mov r4, r0 8018800: 4608 mov r0, r1 8018802: 4611 mov r1, r2 8018804: 602b str r3, [r5, #0] 8018806: f7eb ff4a bl 800469e <_fstat> 801880a: 1c43 adds r3, r0, #1 801880c: d102 bne.n 8018814 <_fstat_r+0x1c> 801880e: 682b ldr r3, [r5, #0] 8018810: b103 cbz r3, 8018814 <_fstat_r+0x1c> 8018812: 6023 str r3, [r4, #0] 8018814: bd38 pop {r3, r4, r5, pc} 8018816: bf00 nop 8018818: 240131a4 .word 0x240131a4 0801881c <_isatty_r>: 801881c: b538 push {r3, r4, r5, lr} 801881e: 4d06 ldr r5, [pc, #24] @ (8018838 <_isatty_r+0x1c>) 8018820: 2300 movs r3, #0 8018822: 4604 mov r4, r0 8018824: 4608 mov r0, r1 8018826: 602b str r3, [r5, #0] 8018828: f7eb ff49 bl 80046be <_isatty> 801882c: 1c43 adds r3, r0, #1 801882e: d102 bne.n 8018836 <_isatty_r+0x1a> 8018830: 682b ldr r3, [r5, #0] 8018832: b103 cbz r3, 8018836 <_isatty_r+0x1a> 8018834: 6023 str r3, [r4, #0] 8018836: bd38 pop {r3, r4, r5, pc} 8018838: 240131a4 .word 0x240131a4 0801883c <_sbrk_r>: 801883c: b538 push {r3, r4, r5, lr} 801883e: 4d06 ldr r5, [pc, #24] @ (8018858 <_sbrk_r+0x1c>) 8018840: 2300 movs r3, #0 8018842: 4604 mov r4, r0 8018844: 4608 mov r0, r1 8018846: 602b str r3, [r5, #0] 8018848: f7eb ff52 bl 80046f0 <_sbrk> 801884c: 1c43 adds r3, r0, #1 801884e: d102 bne.n 8018856 <_sbrk_r+0x1a> 8018850: 682b ldr r3, [r5, #0] 8018852: b103 cbz r3, 8018856 <_sbrk_r+0x1a> 8018854: 6023 str r3, [r4, #0] 8018856: bd38 pop {r3, r4, r5, pc} 8018858: 240131a4 .word 0x240131a4 0801885c : 801885c: b508 push {r3, lr} 801885e: ed2d 8b02 vpush {d8} 8018862: eef0 8a40 vmov.f32 s17, s0 8018866: eeb0 8a60 vmov.f32 s16, s1 801886a: f000 f817 bl 801889c <__ieee754_fmodf> 801886e: eef4 8a48 vcmp.f32 s17, s16 8018872: eef1 fa10 vmrs APSR_nzcv, fpscr 8018876: d60c bvs.n 8018892 8018878: eddf 8a07 vldr s17, [pc, #28] @ 8018898 801887c: eeb4 8a68 vcmp.f32 s16, s17 8018880: eef1 fa10 vmrs APSR_nzcv, fpscr 8018884: d105 bne.n 8018892 8018886: f7ff faa5 bl 8017dd4 <__errno> 801888a: ee88 0aa8 vdiv.f32 s0, s17, s17 801888e: 2321 movs r3, #33 @ 0x21 8018890: 6003 str r3, [r0, #0] 8018892: ecbd 8b02 vpop {d8} 8018896: bd08 pop {r3, pc} 8018898: 00000000 .word 0x00000000 0801889c <__ieee754_fmodf>: 801889c: b5f0 push {r4, r5, r6, r7, lr} 801889e: ee10 5a90 vmov r5, s1 80188a2: f025 4000 bic.w r0, r5, #2147483648 @ 0x80000000 80188a6: 1e43 subs r3, r0, #1 80188a8: f1b3 4fff cmp.w r3, #2139095040 @ 0x7f800000 80188ac: d206 bcs.n 80188bc <__ieee754_fmodf+0x20> 80188ae: ee10 3a10 vmov r3, s0 80188b2: f023 4600 bic.w r6, r3, #2147483648 @ 0x80000000 80188b6: f1b6 4fff cmp.w r6, #2139095040 @ 0x7f800000 80188ba: d304 bcc.n 80188c6 <__ieee754_fmodf+0x2a> 80188bc: ee60 0a20 vmul.f32 s1, s0, s1 80188c0: ee80 0aa0 vdiv.f32 s0, s1, s1 80188c4: bdf0 pop {r4, r5, r6, r7, pc} 80188c6: 4286 cmp r6, r0 80188c8: dbfc blt.n 80188c4 <__ieee754_fmodf+0x28> 80188ca: f003 4400 and.w r4, r3, #2147483648 @ 0x80000000 80188ce: d105 bne.n 80188dc <__ieee754_fmodf+0x40> 80188d0: 4b32 ldr r3, [pc, #200] @ (801899c <__ieee754_fmodf+0x100>) 80188d2: eb03 7354 add.w r3, r3, r4, lsr #29 80188d6: ed93 0a00 vldr s0, [r3] 80188da: e7f3 b.n 80188c4 <__ieee754_fmodf+0x28> 80188dc: f013 4fff tst.w r3, #2139095040 @ 0x7f800000 80188e0: d140 bne.n 8018964 <__ieee754_fmodf+0xc8> 80188e2: 0232 lsls r2, r6, #8 80188e4: f06f 017d mvn.w r1, #125 @ 0x7d 80188e8: 2a00 cmp r2, #0 80188ea: dc38 bgt.n 801895e <__ieee754_fmodf+0xc2> 80188ec: f015 4fff tst.w r5, #2139095040 @ 0x7f800000 80188f0: d13e bne.n 8018970 <__ieee754_fmodf+0xd4> 80188f2: 0207 lsls r7, r0, #8 80188f4: f06f 027d mvn.w r2, #125 @ 0x7d 80188f8: 2f00 cmp r7, #0 80188fa: da36 bge.n 801896a <__ieee754_fmodf+0xce> 80188fc: f111 0f7e cmn.w r1, #126 @ 0x7e 8018900: bfb9 ittee lt 8018902: f06f 037d mvnlt.w r3, #125 @ 0x7d 8018906: 1a5b sublt r3, r3, r1 8018908: f3c3 0316 ubfxge r3, r3, #0, #23 801890c: f443 0300 orrge.w r3, r3, #8388608 @ 0x800000 8018910: bfb8 it lt 8018912: fa06 f303 lsllt.w r3, r6, r3 8018916: f112 0f7e cmn.w r2, #126 @ 0x7e 801891a: bfb5 itete lt 801891c: f06f 057d mvnlt.w r5, #125 @ 0x7d 8018920: f3c5 0516 ubfxge r5, r5, #0, #23 8018924: 1aad sublt r5, r5, r2 8018926: f445 0000 orrge.w r0, r5, #8388608 @ 0x800000 801892a: bfb8 it lt 801892c: 40a8 lsllt r0, r5 801892e: 1a89 subs r1, r1, r2 8018930: 1a1d subs r5, r3, r0 8018932: bb01 cbnz r1, 8018976 <__ieee754_fmodf+0xda> 8018934: ea13 0325 ands.w r3, r3, r5, asr #32 8018938: bf38 it cc 801893a: 462b movcc r3, r5 801893c: 2b00 cmp r3, #0 801893e: d0c7 beq.n 80188d0 <__ieee754_fmodf+0x34> 8018940: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 8018944: db1f blt.n 8018986 <__ieee754_fmodf+0xea> 8018946: f112 0f7e cmn.w r2, #126 @ 0x7e 801894a: db1f blt.n 801898c <__ieee754_fmodf+0xf0> 801894c: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 8018950: 327f adds r2, #127 @ 0x7f 8018952: 4323 orrs r3, r4 8018954: ea43 53c2 orr.w r3, r3, r2, lsl #23 8018958: ee00 3a10 vmov s0, r3 801895c: e7b2 b.n 80188c4 <__ieee754_fmodf+0x28> 801895e: 3901 subs r1, #1 8018960: 0052 lsls r2, r2, #1 8018962: e7c1 b.n 80188e8 <__ieee754_fmodf+0x4c> 8018964: 15f1 asrs r1, r6, #23 8018966: 397f subs r1, #127 @ 0x7f 8018968: e7c0 b.n 80188ec <__ieee754_fmodf+0x50> 801896a: 3a01 subs r2, #1 801896c: 007f lsls r7, r7, #1 801896e: e7c3 b.n 80188f8 <__ieee754_fmodf+0x5c> 8018970: 15c2 asrs r2, r0, #23 8018972: 3a7f subs r2, #127 @ 0x7f 8018974: e7c2 b.n 80188fc <__ieee754_fmodf+0x60> 8018976: 2d00 cmp r5, #0 8018978: da02 bge.n 8018980 <__ieee754_fmodf+0xe4> 801897a: 005b lsls r3, r3, #1 801897c: 3901 subs r1, #1 801897e: e7d7 b.n 8018930 <__ieee754_fmodf+0x94> 8018980: d0a6 beq.n 80188d0 <__ieee754_fmodf+0x34> 8018982: 006b lsls r3, r5, #1 8018984: e7fa b.n 801897c <__ieee754_fmodf+0xe0> 8018986: 005b lsls r3, r3, #1 8018988: 3a01 subs r2, #1 801898a: e7d9 b.n 8018940 <__ieee754_fmodf+0xa4> 801898c: f1c2 22ff rsb r2, r2, #4278255360 @ 0xff00ff00 8018990: f502 027f add.w r2, r2, #16711680 @ 0xff0000 8018994: 3282 adds r2, #130 @ 0x82 8018996: 4113 asrs r3, r2 8018998: 4323 orrs r3, r4 801899a: e7dd b.n 8018958 <__ieee754_fmodf+0xbc> 801899c: 08018bd0 .word 0x08018bd0 080189a0 <_init>: 80189a0: b5f8 push {r3, r4, r5, r6, r7, lr} 80189a2: bf00 nop 80189a4: bcf8 pop {r3, r4, r5, r6, r7} 80189a6: bc08 pop {r3} 80189a8: 469e mov lr, r3 80189aa: 4770 bx lr 080189ac <_fini>: 80189ac: b5f8 push {r3, r4, r5, r6, r7, lr} 80189ae: bf00 nop 80189b0: bcf8 pop {r3, r4, r5, r6, r7} 80189b2: bc08 pop {r3} 80189b4: 469e mov lr, r3 80189b6: 4770 bx lr