OZE_Sensor.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000298 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00019f0c 080002a0 080002a0 000012a0 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000488 0801a1b0 0801a1b0 0001b1b0 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM 00000008 0801a638 0801a638 0001b638 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .init_array 00000004 0801a640 0801a640 0001b640 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .fini_array 00000004 0801a644 0801a644 0001b644 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 6 .data 00000210 24000000 0801a648 0001c000 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .bss 000130d4 24000220 0801a858 0001c220 2**5 ALLOC 8 ._user_heap_stack 00000604 240132f4 0801a858 0001c2f4 2**0 ALLOC 9 .ARM.attributes 0000002e 00000000 00000000 0001c210 2**0 CONTENTS, READONLY 10 .debug_info 00035425 00000000 00000000 0001c23e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_abbrev 0000671d 00000000 00000000 00051663 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_aranges 00002510 00000000 00000000 00057d80 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_macro 0004014f 00000000 00000000 0005a290 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_line 000321e7 00000000 00000000 0009a3df 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_str 001893b6 00000000 00000000 000cc5c6 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .comment 00000043 00000000 00000000 0025597c 2**0 CONTENTS, READONLY 17 .debug_rnglists 00001c81 00000000 00000000 002559bf 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_frame 0000aa30 00000000 00000000 00257640 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_line_str 00000066 00000000 00000000 00262070 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080002a0 <__do_global_dtors_aux>: 80002a0: b510 push {r4, lr} 80002a2: 4c05 ldr r4, [pc, #20] @ (80002b8 <__do_global_dtors_aux+0x18>) 80002a4: 7823 ldrb r3, [r4, #0] 80002a6: b933 cbnz r3, 80002b6 <__do_global_dtors_aux+0x16> 80002a8: 4b04 ldr r3, [pc, #16] @ (80002bc <__do_global_dtors_aux+0x1c>) 80002aa: b113 cbz r3, 80002b2 <__do_global_dtors_aux+0x12> 80002ac: 4804 ldr r0, [pc, #16] @ (80002c0 <__do_global_dtors_aux+0x20>) 80002ae: f3af 8000 nop.w 80002b2: 2301 movs r3, #1 80002b4: 7023 strb r3, [r4, #0] 80002b6: bd10 pop {r4, pc} 80002b8: 24000220 .word 0x24000220 80002bc: 00000000 .word 0x00000000 80002c0: 0801a194 .word 0x0801a194 080002c4 : 80002c4: b508 push {r3, lr} 80002c6: 4b03 ldr r3, [pc, #12] @ (80002d4 ) 80002c8: b11b cbz r3, 80002d2 80002ca: 4903 ldr r1, [pc, #12] @ (80002d8 ) 80002cc: 4803 ldr r0, [pc, #12] @ (80002dc ) 80002ce: f3af 8000 nop.w 80002d2: bd08 pop {r3, pc} 80002d4: 00000000 .word 0x00000000 80002d8: 24000224 .word 0x24000224 80002dc: 0801a194 .word 0x0801a194 080002e0 : 80002e0: f001 01ff and.w r1, r1, #255 @ 0xff 80002e4: 2a10 cmp r2, #16 80002e6: db2b blt.n 8000340 80002e8: f010 0f07 tst.w r0, #7 80002ec: d008 beq.n 8000300 80002ee: f810 3b01 ldrb.w r3, [r0], #1 80002f2: 3a01 subs r2, #1 80002f4: 428b cmp r3, r1 80002f6: d02d beq.n 8000354 80002f8: f010 0f07 tst.w r0, #7 80002fc: b342 cbz r2, 8000350 80002fe: d1f6 bne.n 80002ee 8000300: b4f0 push {r4, r5, r6, r7} 8000302: ea41 2101 orr.w r1, r1, r1, lsl #8 8000306: ea41 4101 orr.w r1, r1, r1, lsl #16 800030a: f022 0407 bic.w r4, r2, #7 800030e: f07f 0700 mvns.w r7, #0 8000312: 2300 movs r3, #0 8000314: e8f0 5602 ldrd r5, r6, [r0], #8 8000318: 3c08 subs r4, #8 800031a: ea85 0501 eor.w r5, r5, r1 800031e: ea86 0601 eor.w r6, r6, r1 8000322: fa85 f547 uadd8 r5, r5, r7 8000326: faa3 f587 sel r5, r3, r7 800032a: fa86 f647 uadd8 r6, r6, r7 800032e: faa5 f687 sel r6, r5, r7 8000332: b98e cbnz r6, 8000358 8000334: d1ee bne.n 8000314 8000336: bcf0 pop {r4, r5, r6, r7} 8000338: f001 01ff and.w r1, r1, #255 @ 0xff 800033c: f002 0207 and.w r2, r2, #7 8000340: b132 cbz r2, 8000350 8000342: f810 3b01 ldrb.w r3, [r0], #1 8000346: 3a01 subs r2, #1 8000348: ea83 0301 eor.w r3, r3, r1 800034c: b113 cbz r3, 8000354 800034e: d1f8 bne.n 8000342 8000350: 2000 movs r0, #0 8000352: 4770 bx lr 8000354: 3801 subs r0, #1 8000356: 4770 bx lr 8000358: 2d00 cmp r5, #0 800035a: bf06 itte eq 800035c: 4635 moveq r5, r6 800035e: 3803 subeq r0, #3 8000360: 3807 subne r0, #7 8000362: f015 0f01 tst.w r5, #1 8000366: d107 bne.n 8000378 8000368: 3001 adds r0, #1 800036a: f415 7f80 tst.w r5, #256 @ 0x100 800036e: bf02 ittt eq 8000370: 3001 addeq r0, #1 8000372: f415 3fc0 tsteq.w r5, #98304 @ 0x18000 8000376: 3001 addeq r0, #1 8000378: bcf0 pop {r4, r5, r6, r7} 800037a: 3801 subs r0, #1 800037c: 4770 bx lr 800037e: bf00 nop 08000380 : 8000380: 4603 mov r3, r0 8000382: f813 2b01 ldrb.w r2, [r3], #1 8000386: 2a00 cmp r2, #0 8000388: d1fb bne.n 8000382 800038a: 1a18 subs r0, r3, r0 800038c: 3801 subs r0, #1 800038e: 4770 bx lr 08000390 <__aeabi_uldivmod>: 8000390: b953 cbnz r3, 80003a8 <__aeabi_uldivmod+0x18> 8000392: b94a cbnz r2, 80003a8 <__aeabi_uldivmod+0x18> 8000394: 2900 cmp r1, #0 8000396: bf08 it eq 8000398: 2800 cmpeq r0, #0 800039a: bf1c itt ne 800039c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 80003a0: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 80003a4: f000 b96a b.w 800067c <__aeabi_idiv0> 80003a8: f1ad 0c08 sub.w ip, sp, #8 80003ac: e96d ce04 strd ip, lr, [sp, #-16]! 80003b0: f000 f806 bl 80003c0 <__udivmoddi4> 80003b4: f8dd e004 ldr.w lr, [sp, #4] 80003b8: e9dd 2302 ldrd r2, r3, [sp, #8] 80003bc: b004 add sp, #16 80003be: 4770 bx lr 080003c0 <__udivmoddi4>: 80003c0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80003c4: 9d08 ldr r5, [sp, #32] 80003c6: 460c mov r4, r1 80003c8: 2b00 cmp r3, #0 80003ca: d14e bne.n 800046a <__udivmoddi4+0xaa> 80003cc: 4694 mov ip, r2 80003ce: 458c cmp ip, r1 80003d0: 4686 mov lr, r0 80003d2: fab2 f282 clz r2, r2 80003d6: d962 bls.n 800049e <__udivmoddi4+0xde> 80003d8: b14a cbz r2, 80003ee <__udivmoddi4+0x2e> 80003da: f1c2 0320 rsb r3, r2, #32 80003de: 4091 lsls r1, r2 80003e0: fa20 f303 lsr.w r3, r0, r3 80003e4: fa0c fc02 lsl.w ip, ip, r2 80003e8: 4319 orrs r1, r3 80003ea: fa00 fe02 lsl.w lr, r0, r2 80003ee: ea4f 471c mov.w r7, ip, lsr #16 80003f2: fa1f f68c uxth.w r6, ip 80003f6: fbb1 f4f7 udiv r4, r1, r7 80003fa: ea4f 431e mov.w r3, lr, lsr #16 80003fe: fb07 1114 mls r1, r7, r4, r1 8000402: ea43 4301 orr.w r3, r3, r1, lsl #16 8000406: fb04 f106 mul.w r1, r4, r6 800040a: 4299 cmp r1, r3 800040c: d90a bls.n 8000424 <__udivmoddi4+0x64> 800040e: eb1c 0303 adds.w r3, ip, r3 8000412: f104 30ff add.w r0, r4, #4294967295 @ 0xffffffff 8000416: f080 8112 bcs.w 800063e <__udivmoddi4+0x27e> 800041a: 4299 cmp r1, r3 800041c: f240 810f bls.w 800063e <__udivmoddi4+0x27e> 8000420: 3c02 subs r4, #2 8000422: 4463 add r3, ip 8000424: 1a59 subs r1, r3, r1 8000426: fa1f f38e uxth.w r3, lr 800042a: fbb1 f0f7 udiv r0, r1, r7 800042e: fb07 1110 mls r1, r7, r0, r1 8000432: ea43 4301 orr.w r3, r3, r1, lsl #16 8000436: fb00 f606 mul.w r6, r0, r6 800043a: 429e cmp r6, r3 800043c: d90a bls.n 8000454 <__udivmoddi4+0x94> 800043e: eb1c 0303 adds.w r3, ip, r3 8000442: f100 31ff add.w r1, r0, #4294967295 @ 0xffffffff 8000446: f080 80fc bcs.w 8000642 <__udivmoddi4+0x282> 800044a: 429e cmp r6, r3 800044c: f240 80f9 bls.w 8000642 <__udivmoddi4+0x282> 8000450: 4463 add r3, ip 8000452: 3802 subs r0, #2 8000454: 1b9b subs r3, r3, r6 8000456: ea40 4004 orr.w r0, r0, r4, lsl #16 800045a: 2100 movs r1, #0 800045c: b11d cbz r5, 8000466 <__udivmoddi4+0xa6> 800045e: 40d3 lsrs r3, r2 8000460: 2200 movs r2, #0 8000462: e9c5 3200 strd r3, r2, [r5] 8000466: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800046a: 428b cmp r3, r1 800046c: d905 bls.n 800047a <__udivmoddi4+0xba> 800046e: b10d cbz r5, 8000474 <__udivmoddi4+0xb4> 8000470: e9c5 0100 strd r0, r1, [r5] 8000474: 2100 movs r1, #0 8000476: 4608 mov r0, r1 8000478: e7f5 b.n 8000466 <__udivmoddi4+0xa6> 800047a: fab3 f183 clz r1, r3 800047e: 2900 cmp r1, #0 8000480: d146 bne.n 8000510 <__udivmoddi4+0x150> 8000482: 42a3 cmp r3, r4 8000484: d302 bcc.n 800048c <__udivmoddi4+0xcc> 8000486: 4290 cmp r0, r2 8000488: f0c0 80f0 bcc.w 800066c <__udivmoddi4+0x2ac> 800048c: 1a86 subs r6, r0, r2 800048e: eb64 0303 sbc.w r3, r4, r3 8000492: 2001 movs r0, #1 8000494: 2d00 cmp r5, #0 8000496: d0e6 beq.n 8000466 <__udivmoddi4+0xa6> 8000498: e9c5 6300 strd r6, r3, [r5] 800049c: e7e3 b.n 8000466 <__udivmoddi4+0xa6> 800049e: 2a00 cmp r2, #0 80004a0: f040 8090 bne.w 80005c4 <__udivmoddi4+0x204> 80004a4: eba1 040c sub.w r4, r1, ip 80004a8: ea4f 481c mov.w r8, ip, lsr #16 80004ac: fa1f f78c uxth.w r7, ip 80004b0: 2101 movs r1, #1 80004b2: fbb4 f6f8 udiv r6, r4, r8 80004b6: ea4f 431e mov.w r3, lr, lsr #16 80004ba: fb08 4416 mls r4, r8, r6, r4 80004be: ea43 4304 orr.w r3, r3, r4, lsl #16 80004c2: fb07 f006 mul.w r0, r7, r6 80004c6: 4298 cmp r0, r3 80004c8: d908 bls.n 80004dc <__udivmoddi4+0x11c> 80004ca: eb1c 0303 adds.w r3, ip, r3 80004ce: f106 34ff add.w r4, r6, #4294967295 @ 0xffffffff 80004d2: d202 bcs.n 80004da <__udivmoddi4+0x11a> 80004d4: 4298 cmp r0, r3 80004d6: f200 80cd bhi.w 8000674 <__udivmoddi4+0x2b4> 80004da: 4626 mov r6, r4 80004dc: 1a1c subs r4, r3, r0 80004de: fa1f f38e uxth.w r3, lr 80004e2: fbb4 f0f8 udiv r0, r4, r8 80004e6: fb08 4410 mls r4, r8, r0, r4 80004ea: ea43 4304 orr.w r3, r3, r4, lsl #16 80004ee: fb00 f707 mul.w r7, r0, r7 80004f2: 429f cmp r7, r3 80004f4: d908 bls.n 8000508 <__udivmoddi4+0x148> 80004f6: eb1c 0303 adds.w r3, ip, r3 80004fa: f100 34ff add.w r4, r0, #4294967295 @ 0xffffffff 80004fe: d202 bcs.n 8000506 <__udivmoddi4+0x146> 8000500: 429f cmp r7, r3 8000502: f200 80b0 bhi.w 8000666 <__udivmoddi4+0x2a6> 8000506: 4620 mov r0, r4 8000508: 1bdb subs r3, r3, r7 800050a: ea40 4006 orr.w r0, r0, r6, lsl #16 800050e: e7a5 b.n 800045c <__udivmoddi4+0x9c> 8000510: f1c1 0620 rsb r6, r1, #32 8000514: 408b lsls r3, r1 8000516: fa22 f706 lsr.w r7, r2, r6 800051a: 431f orrs r7, r3 800051c: fa20 fc06 lsr.w ip, r0, r6 8000520: fa04 f301 lsl.w r3, r4, r1 8000524: ea43 030c orr.w r3, r3, ip 8000528: 40f4 lsrs r4, r6 800052a: fa00 f801 lsl.w r8, r0, r1 800052e: 0c38 lsrs r0, r7, #16 8000530: ea4f 4913 mov.w r9, r3, lsr #16 8000534: fbb4 fef0 udiv lr, r4, r0 8000538: fa1f fc87 uxth.w ip, r7 800053c: fb00 441e mls r4, r0, lr, r4 8000540: ea49 4404 orr.w r4, r9, r4, lsl #16 8000544: fb0e f90c mul.w r9, lr, ip 8000548: 45a1 cmp r9, r4 800054a: fa02 f201 lsl.w r2, r2, r1 800054e: d90a bls.n 8000566 <__udivmoddi4+0x1a6> 8000550: 193c adds r4, r7, r4 8000552: f10e 3aff add.w sl, lr, #4294967295 @ 0xffffffff 8000556: f080 8084 bcs.w 8000662 <__udivmoddi4+0x2a2> 800055a: 45a1 cmp r9, r4 800055c: f240 8081 bls.w 8000662 <__udivmoddi4+0x2a2> 8000560: f1ae 0e02 sub.w lr, lr, #2 8000564: 443c add r4, r7 8000566: eba4 0409 sub.w r4, r4, r9 800056a: fa1f f983 uxth.w r9, r3 800056e: fbb4 f3f0 udiv r3, r4, r0 8000572: fb00 4413 mls r4, r0, r3, r4 8000576: ea49 4404 orr.w r4, r9, r4, lsl #16 800057a: fb03 fc0c mul.w ip, r3, ip 800057e: 45a4 cmp ip, r4 8000580: d907 bls.n 8000592 <__udivmoddi4+0x1d2> 8000582: 193c adds r4, r7, r4 8000584: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 8000588: d267 bcs.n 800065a <__udivmoddi4+0x29a> 800058a: 45a4 cmp ip, r4 800058c: d965 bls.n 800065a <__udivmoddi4+0x29a> 800058e: 3b02 subs r3, #2 8000590: 443c add r4, r7 8000592: ea43 400e orr.w r0, r3, lr, lsl #16 8000596: fba0 9302 umull r9, r3, r0, r2 800059a: eba4 040c sub.w r4, r4, ip 800059e: 429c cmp r4, r3 80005a0: 46ce mov lr, r9 80005a2: 469c mov ip, r3 80005a4: d351 bcc.n 800064a <__udivmoddi4+0x28a> 80005a6: d04e beq.n 8000646 <__udivmoddi4+0x286> 80005a8: b155 cbz r5, 80005c0 <__udivmoddi4+0x200> 80005aa: ebb8 030e subs.w r3, r8, lr 80005ae: eb64 040c sbc.w r4, r4, ip 80005b2: fa04 f606 lsl.w r6, r4, r6 80005b6: 40cb lsrs r3, r1 80005b8: 431e orrs r6, r3 80005ba: 40cc lsrs r4, r1 80005bc: e9c5 6400 strd r6, r4, [r5] 80005c0: 2100 movs r1, #0 80005c2: e750 b.n 8000466 <__udivmoddi4+0xa6> 80005c4: f1c2 0320 rsb r3, r2, #32 80005c8: fa20 f103 lsr.w r1, r0, r3 80005cc: fa0c fc02 lsl.w ip, ip, r2 80005d0: fa24 f303 lsr.w r3, r4, r3 80005d4: 4094 lsls r4, r2 80005d6: 430c orrs r4, r1 80005d8: ea4f 481c mov.w r8, ip, lsr #16 80005dc: fa00 fe02 lsl.w lr, r0, r2 80005e0: fa1f f78c uxth.w r7, ip 80005e4: fbb3 f0f8 udiv r0, r3, r8 80005e8: fb08 3110 mls r1, r8, r0, r3 80005ec: 0c23 lsrs r3, r4, #16 80005ee: ea43 4301 orr.w r3, r3, r1, lsl #16 80005f2: fb00 f107 mul.w r1, r0, r7 80005f6: 4299 cmp r1, r3 80005f8: d908 bls.n 800060c <__udivmoddi4+0x24c> 80005fa: eb1c 0303 adds.w r3, ip, r3 80005fe: f100 36ff add.w r6, r0, #4294967295 @ 0xffffffff 8000602: d22c bcs.n 800065e <__udivmoddi4+0x29e> 8000604: 4299 cmp r1, r3 8000606: d92a bls.n 800065e <__udivmoddi4+0x29e> 8000608: 3802 subs r0, #2 800060a: 4463 add r3, ip 800060c: 1a5b subs r3, r3, r1 800060e: b2a4 uxth r4, r4 8000610: fbb3 f1f8 udiv r1, r3, r8 8000614: fb08 3311 mls r3, r8, r1, r3 8000618: ea44 4403 orr.w r4, r4, r3, lsl #16 800061c: fb01 f307 mul.w r3, r1, r7 8000620: 42a3 cmp r3, r4 8000622: d908 bls.n 8000636 <__udivmoddi4+0x276> 8000624: eb1c 0404 adds.w r4, ip, r4 8000628: f101 36ff add.w r6, r1, #4294967295 @ 0xffffffff 800062c: d213 bcs.n 8000656 <__udivmoddi4+0x296> 800062e: 42a3 cmp r3, r4 8000630: d911 bls.n 8000656 <__udivmoddi4+0x296> 8000632: 3902 subs r1, #2 8000634: 4464 add r4, ip 8000636: 1ae4 subs r4, r4, r3 8000638: ea41 4100 orr.w r1, r1, r0, lsl #16 800063c: e739 b.n 80004b2 <__udivmoddi4+0xf2> 800063e: 4604 mov r4, r0 8000640: e6f0 b.n 8000424 <__udivmoddi4+0x64> 8000642: 4608 mov r0, r1 8000644: e706 b.n 8000454 <__udivmoddi4+0x94> 8000646: 45c8 cmp r8, r9 8000648: d2ae bcs.n 80005a8 <__udivmoddi4+0x1e8> 800064a: ebb9 0e02 subs.w lr, r9, r2 800064e: eb63 0c07 sbc.w ip, r3, r7 8000652: 3801 subs r0, #1 8000654: e7a8 b.n 80005a8 <__udivmoddi4+0x1e8> 8000656: 4631 mov r1, r6 8000658: e7ed b.n 8000636 <__udivmoddi4+0x276> 800065a: 4603 mov r3, r0 800065c: e799 b.n 8000592 <__udivmoddi4+0x1d2> 800065e: 4630 mov r0, r6 8000660: e7d4 b.n 800060c <__udivmoddi4+0x24c> 8000662: 46d6 mov lr, sl 8000664: e77f b.n 8000566 <__udivmoddi4+0x1a6> 8000666: 4463 add r3, ip 8000668: 3802 subs r0, #2 800066a: e74d b.n 8000508 <__udivmoddi4+0x148> 800066c: 4606 mov r6, r0 800066e: 4623 mov r3, r4 8000670: 4608 mov r0, r1 8000672: e70f b.n 8000494 <__udivmoddi4+0xd4> 8000674: 3e02 subs r6, #2 8000676: 4463 add r3, ip 8000678: e730 b.n 80004dc <__udivmoddi4+0x11c> 800067a: bf00 nop 0800067c <__aeabi_idiv0>: 800067c: 4770 bx lr 800067e: bf00 nop 08000680 : /* Hook prototypes */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName); /* USER CODE BEGIN 4 */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName) { 8000680: b480 push {r7} 8000682: b083 sub sp, #12 8000684: af00 add r7, sp, #0 8000686: 6078 str r0, [r7, #4] 8000688: 6039 str r1, [r7, #0] /* Run time stack overflow checking is performed if configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is called if a stack overflow is detected. */ } 800068a: bf00 nop 800068c: 370c adds r7, #12 800068e: 46bd mov sp, r7 8000690: f85d 7b04 ldr.w r7, [sp], #4 8000694: 4770 bx lr ... 08000698 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 8000698: b480 push {r7} 800069a: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 800069c: f3bf 8f4f dsb sy } 80006a0: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 80006a2: 4b06 ldr r3, [pc, #24] @ (80006bc <__NVIC_SystemReset+0x24>) 80006a4: 68db ldr r3, [r3, #12] 80006a6: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80006aa: 4904 ldr r1, [pc, #16] @ (80006bc <__NVIC_SystemReset+0x24>) 80006ac: 4b04 ldr r3, [pc, #16] @ (80006c0 <__NVIC_SystemReset+0x28>) 80006ae: 4313 orrs r3, r2 80006b0: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 80006b2: f3bf 8f4f dsb sy } 80006b6: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 80006b8: bf00 nop 80006ba: e7fd b.n 80006b8 <__NVIC_SystemReset+0x20> 80006bc: e000ed00 .word 0xe000ed00 80006c0: 05fa0004 .word 0x05fa0004 080006c4 : \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { 80006c4: b480 push {r7} 80006c6: b083 sub sp, #12 80006c8: af00 add r7, sp, #0 80006ca: 6078 str r0, [r7, #4] if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 80006cc: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000 80006d0: f8d3 3e80 ldr.w r3, [r3, #3712] @ 0xe80 80006d4: f003 0301 and.w r3, r3, #1 80006d8: 2b00 cmp r3, #0 80006da: d013 beq.n 8000704 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 80006dc: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000 80006e0: f8d3 3e00 ldr.w r3, [r3, #3584] @ 0xe00 80006e4: f003 0301 and.w r3, r3, #1 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 80006e8: 2b00 cmp r3, #0 80006ea: d00b beq.n 8000704 { while (ITM->PORT[0U].u32 == 0UL) 80006ec: e000 b.n 80006f0 { __NOP(); 80006ee: bf00 nop while (ITM->PORT[0U].u32 == 0UL) 80006f0: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000 80006f4: 681b ldr r3, [r3, #0] 80006f6: 2b00 cmp r3, #0 80006f8: d0f9 beq.n 80006ee } ITM->PORT[0U].u8 = (uint8_t)ch; 80006fa: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000 80006fe: 687a ldr r2, [r7, #4] 8000700: b2d2 uxtb r2, r2 8000702: 701a strb r2, [r3, #0] } return (ch); 8000704: 687b ldr r3, [r7, #4] } 8000706: 4618 mov r0, r3 8000708: 370c adds r7, #12 800070a: 46bd mov sp, r7 800070c: f85d 7b04 ldr.w r7, [sp], #4 8000710: 4770 bx lr 08000712 <__io_putchar>: /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ int __io_putchar(int ch) { 8000712: b580 push {r7, lr} 8000714: b082 sub sp, #8 8000716: af00 add r7, sp, #0 8000718: 6078 str r0, [r7, #4] #if UART_TASK_LOGS // HAL_UART_Transmit(&huart8, (uint8_t *)&ch, 1, 0xFFFF); // Use UART8 as debug interface ITM_SendChar(ch); // Use SWV as debug interface 800071a: 687b ldr r3, [r7, #4] 800071c: 4618 mov r0, r3 800071e: f7ff ffd1 bl 80006c4 #endif return ch; 8000722: 687b ldr r3, [r7, #4] } 8000724: 4618 mov r0, r3 8000726: 3708 adds r7, #8 8000728: 46bd mov sp, r7 800072a: bd80 pop {r7, pc} 0800072c : void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 800072c: b590 push {r4, r7, lr} 800072e: b085 sub sp, #20 8000730: af00 add r7, sp, #0 8000732: 4603 mov r3, r0 8000734: 80fb strh r3, [r7, #6] if((GPIO_Pin == GPIO_PIN_14) || (GPIO_Pin == GPIO_PIN_15)) 8000736: 88fb ldrh r3, [r7, #6] 8000738: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800073c: d003 beq.n 8000746 800073e: 88fb ldrh r3, [r7, #6] 8000740: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8000744: d11a bne.n 800077c { uint32_t pinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3; 8000746: f44f 4100 mov.w r1, #32768 @ 0x8000 800074a: 481f ldr r0, [pc, #124] @ (80007c8 ) 800074c: f00a fd20 bl 800b190 8000750: 4603 mov r3, r0 8000752: 005c lsls r4, r3, #1 8000754: f44f 4180 mov.w r1, #16384 @ 0x4000 8000758: 481b ldr r0, [pc, #108] @ (80007c8 ) 800075a: f00a fd19 bl 800b190 800075e: 4603 mov r3, r0 8000760: 4323 orrs r3, r4 8000762: f003 0303 and.w r3, r3, #3 8000766: 60fb str r3, [r7, #12] osMessageQueuePut(encoderXTaskArg.dataQueue, &pinStates, 0, 0); 8000768: 4b18 ldr r3, [pc, #96] @ (80007cc ) 800076a: 6918 ldr r0, [r3, #16] 800076c: f107 010c add.w r1, r7, #12 8000770: 2300 movs r3, #0 8000772: 2200 movs r2, #0 8000774: f013 fa1a bl 8013bac { 8000778: bf00 nop else if ((GPIO_Pin == GPIO_PIN_10) || (GPIO_Pin == GPIO_PIN_11)) { uint32_t pinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3; osMessageQueuePut(encoderYTaskArg.dataQueue, &pinStates, 0, 0); } } 800077a: e020 b.n 80007be else if ((GPIO_Pin == GPIO_PIN_10) || (GPIO_Pin == GPIO_PIN_11)) 800077c: 88fb ldrh r3, [r7, #6] 800077e: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8000782: d003 beq.n 800078c 8000784: 88fb ldrh r3, [r7, #6] 8000786: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800078a: d118 bne.n 80007be uint32_t pinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3; 800078c: f44f 6100 mov.w r1, #2048 @ 0x800 8000790: 480f ldr r0, [pc, #60] @ (80007d0 ) 8000792: f00a fcfd bl 800b190 8000796: 4603 mov r3, r0 8000798: 005c lsls r4, r3, #1 800079a: f44f 6180 mov.w r1, #1024 @ 0x400 800079e: 480c ldr r0, [pc, #48] @ (80007d0 ) 80007a0: f00a fcf6 bl 800b190 80007a4: 4603 mov r3, r0 80007a6: 4323 orrs r3, r4 80007a8: f003 0303 and.w r3, r3, #3 80007ac: 60bb str r3, [r7, #8] osMessageQueuePut(encoderYTaskArg.dataQueue, &pinStates, 0, 0); 80007ae: 4b09 ldr r3, [pc, #36] @ (80007d4 ) 80007b0: 6918 ldr r0, [r3, #16] 80007b2: f107 0108 add.w r1, r7, #8 80007b6: 2300 movs r3, #0 80007b8: 2200 movs r2, #0 80007ba: f013 f9f7 bl 8013bac } 80007be: bf00 nop 80007c0: 3714 adds r7, #20 80007c2: 46bd mov sp, r7 80007c4: bd90 pop {r4, r7, pc} 80007c6: bf00 nop 80007c8: 58020c00 .word 0x58020c00 80007cc: 24000980 .word 0x24000980 80007d0: 58020400 .word 0x58020400 80007d4: 240009a0 .word 0x240009a0 080007d8
: /** * @brief The application entry point. * @retval int */ int main(void) { 80007d8: b580 push {r7, lr} 80007da: b084 sub sp, #16 80007dc: af00 add r7, sp, #0 /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MPU Configuration--------------------------------------------------------*/ MPU_Config(); 80007de: f001 f94f bl 8001a80 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 80007e2: 4b62 ldr r3, [pc, #392] @ (800096c ) 80007e4: 695b ldr r3, [r3, #20] 80007e6: f403 3300 and.w r3, r3, #131072 @ 0x20000 80007ea: 2b00 cmp r3, #0 80007ec: d11b bne.n 8000826 __ASM volatile ("dsb 0xF":::"memory"); 80007ee: f3bf 8f4f dsb sy } 80007f2: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80007f4: f3bf 8f6f isb sy } 80007f8: bf00 nop SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 80007fa: 4b5c ldr r3, [pc, #368] @ (800096c ) 80007fc: 2200 movs r2, #0 80007fe: f8c3 2250 str.w r2, [r3, #592] @ 0x250 __ASM volatile ("dsb 0xF":::"memory"); 8000802: f3bf 8f4f dsb sy } 8000806: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000808: f3bf 8f6f isb sy } 800080c: bf00 nop SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 800080e: 4b57 ldr r3, [pc, #348] @ (800096c ) 8000810: 695b ldr r3, [r3, #20] 8000812: 4a56 ldr r2, [pc, #344] @ (800096c ) 8000814: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8000818: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 800081a: f3bf 8f4f dsb sy } 800081e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000820: f3bf 8f6f isb sy } 8000824: e000 b.n 8000828 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 8000826: bf00 nop if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 8000828: 4b50 ldr r3, [pc, #320] @ (800096c ) 800082a: 695b ldr r3, [r3, #20] 800082c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8000830: 2b00 cmp r3, #0 8000832: d138 bne.n 80008a6 SCB->CSSELR = 0U; /* select Level 1 data cache */ 8000834: 4b4d ldr r3, [pc, #308] @ (800096c ) 8000836: 2200 movs r2, #0 8000838: f8c3 2084 str.w r2, [r3, #132] @ 0x84 __ASM volatile ("dsb 0xF":::"memory"); 800083c: f3bf 8f4f dsb sy } 8000840: bf00 nop ccsidr = SCB->CCSIDR; 8000842: 4b4a ldr r3, [pc, #296] @ (800096c ) 8000844: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8000848: 60fb str r3, [r7, #12] sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 800084a: 68fb ldr r3, [r7, #12] 800084c: 0b5b lsrs r3, r3, #13 800084e: f3c3 030e ubfx r3, r3, #0, #15 8000852: 60bb str r3, [r7, #8] ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 8000854: 68fb ldr r3, [r7, #12] 8000856: 08db lsrs r3, r3, #3 8000858: f3c3 0309 ubfx r3, r3, #0, #10 800085c: 607b str r3, [r7, #4] SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 800085e: 68bb ldr r3, [r7, #8] 8000860: 015a lsls r2, r3, #5 8000862: f643 73e0 movw r3, #16352 @ 0x3fe0 8000866: 4013 ands r3, r2 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 8000868: 687a ldr r2, [r7, #4] 800086a: 0792 lsls r2, r2, #30 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 800086c: 493f ldr r1, [pc, #252] @ (800096c ) 800086e: 4313 orrs r3, r2 8000870: f8c1 3260 str.w r3, [r1, #608] @ 0x260 } while (ways-- != 0U); 8000874: 687b ldr r3, [r7, #4] 8000876: 1e5a subs r2, r3, #1 8000878: 607a str r2, [r7, #4] 800087a: 2b00 cmp r3, #0 800087c: d1ef bne.n 800085e } while(sets-- != 0U); 800087e: 68bb ldr r3, [r7, #8] 8000880: 1e5a subs r2, r3, #1 8000882: 60ba str r2, [r7, #8] 8000884: 2b00 cmp r3, #0 8000886: d1e5 bne.n 8000854 __ASM volatile ("dsb 0xF":::"memory"); 8000888: f3bf 8f4f dsb sy } 800088c: bf00 nop SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 800088e: 4b37 ldr r3, [pc, #220] @ (800096c ) 8000890: 695b ldr r3, [r3, #20] 8000892: 4a36 ldr r2, [pc, #216] @ (800096c ) 8000894: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8000898: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 800089a: f3bf 8f4f dsb sy } 800089e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80008a0: f3bf 8f6f isb sy } 80008a4: e000 b.n 80008a8 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 80008a6: bf00 nop SCB_EnableDCache(); /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80008a8: f004 ffa8 bl 80057fc /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80008ac: f000 f880 bl 80009b0 /* Configure the peripherals common clocks */ PeriphCommonClock_Config(); 80008b0: f000 f8fc bl 8000aac /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80008b4: f000 fe84 bl 80015c0 MX_DMA_Init(); 80008b8: f000 fe52 bl 8001560 MX_RNG_Init(); 80008bc: f000 fc02 bl 80010c4 MX_USART1_UART_Init(); 80008c0: f000 fdfe bl 80014c0 MX_ADC1_Init(); 80008c4: f000 f922 bl 8000b0c MX_UART8_Init(); 80008c8: f000 fdae bl 8001428 MX_CRC_Init(); 80008cc: f000 fb78 bl 8000fc0 MX_ADC2_Init(); 80008d0: f000 fa0a bl 8000ce8 MX_ADC3_Init(); 80008d4: f000 fa94 bl 8000e00 MX_TIM1_Init(); 80008d8: f000 fc0a bl 80010f0 MX_TIM3_Init(); 80008dc: f000 fca4 bl 8001228 MX_DAC1_Init(); 80008e0: f000 fb98 bl 8001014 MX_COMP1_Init(); 80008e4: f000 fb3e bl 8000f64 MX_TIM8_Init(); 80008e8: f000 fd4a bl 8001380 #ifdef WATCHDOG_ENABLED MX_IWDG1_Init(); 80008ec: f000 fbce bl 800108c #endif /* USER CODE BEGIN 2 */ #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 80008f0: 481f ldr r0, [pc, #124] @ (8000970 ) 80008f2: f00a fd01 bl 800b2f8 #endif /* USER CODE END 2 */ /* Init scheduler */ osKernelInitialize(); 80008f6: f012 fde9 bl 80134cc /* add semaphores, ... */ /* USER CODE END RTOS_SEMAPHORES */ /* Create the timer(s) */ /* creation of debugLedTimer */ debugLedTimerHandle = osTimerNew(debugLedTimerCallback, osTimerOnce, NULL, &debugLedTimer_attributes); 80008fa: 4b1e ldr r3, [pc, #120] @ (8000974 ) 80008fc: 2200 movs r2, #0 80008fe: 2100 movs r1, #0 8000900: 481d ldr r0, [pc, #116] @ (8000978 ) 8000902: f012 fef1 bl 80136e8 8000906: 4603 mov r3, r0 8000908: 4a1c ldr r2, [pc, #112] @ (800097c ) 800090a: 6013 str r3, [r2, #0] /* creation of fanTimer */ fanTimerHandle = osTimerNew(fanTimerCallback, osTimerOnce, NULL, &fanTimer_attributes); 800090c: 4b1c ldr r3, [pc, #112] @ (8000980 ) 800090e: 2200 movs r2, #0 8000910: 2100 movs r1, #0 8000912: 481c ldr r0, [pc, #112] @ (8000984 ) 8000914: f012 fee8 bl 80136e8 8000918: 4603 mov r3, r0 800091a: 4a1b ldr r2, [pc, #108] @ (8000988 ) 800091c: 6013 str r3, [r2, #0] /* creation of motorXTimer */ motorXTimerHandle = osTimerNew(motorXTimerCallback, osTimerPeriodic, NULL, &motorXTimer_attributes); 800091e: 4b1b ldr r3, [pc, #108] @ (800098c ) 8000920: 2200 movs r2, #0 8000922: 2101 movs r1, #1 8000924: 481a ldr r0, [pc, #104] @ (8000990 ) 8000926: f012 fedf bl 80136e8 800092a: 4603 mov r3, r0 800092c: 4a19 ldr r2, [pc, #100] @ (8000994 ) 800092e: 6013 str r3, [r2, #0] /* creation of motorYTimer */ motorYTimerHandle = osTimerNew(motorYTimerCallback, osTimerPeriodic, NULL, &motorYTimer_attributes); 8000930: 4b19 ldr r3, [pc, #100] @ (8000998 ) 8000932: 2200 movs r2, #0 8000934: 2101 movs r1, #1 8000936: 4819 ldr r0, [pc, #100] @ (800099c ) 8000938: f012 fed6 bl 80136e8 800093c: 4603 mov r3, r0 800093e: 4a18 ldr r2, [pc, #96] @ (80009a0 ) 8000940: 6013 str r3, [r2, #0] /* add queues, ... */ /* USER CODE END RTOS_QUEUES */ /* Create the thread(s) */ /* creation of defaultTask */ defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); 8000942: 4a18 ldr r2, [pc, #96] @ (80009a4 ) 8000944: 2100 movs r1, #0 8000946: 4818 ldr r0, [pc, #96] @ (80009a8 ) 8000948: f012 fe0a bl 8013560 800094c: 4603 mov r3, r0 800094e: 4a17 ldr r2, [pc, #92] @ (80009ac ) 8000950: 6013 str r3, [r2, #0] /* USER CODE BEGIN RTOS_THREADS */ /* add threads, ... */ #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8000952: 4807 ldr r0, [pc, #28] @ (8000970 ) 8000954: f00a fcd0 bl 800b2f8 #endif UartTasksInit(); 8000958: f003 fdf6 bl 8004548 #ifdef USER_MOCKS MockMeasurmetsTaskInit(); #else MeasTasksInit(); 800095c: f001 f91c bl 8001b98 #endif PositionControlTaskInit(); 8000960: f002 fa9e bl 8002ea0 /* USER CODE BEGIN RTOS_EVENTS */ /* add events, ... */ /* USER CODE END RTOS_EVENTS */ /* Start scheduler */ osKernelStart(); 8000964: f012 fdd6 bl 8013514 /* We should never get here as control is now taken by the scheduler */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8000968: bf00 nop 800096a: e7fd b.n 8000968 800096c: e000ed00 .word 0xe000ed00 8000970: 24000578 .word 0x24000578 8000974: 0801a248 .word 0x0801a248 8000978: 080019d5 .word 0x080019d5 800097c: 240007ac .word 0x240007ac 8000980: 0801a258 .word 0x0801a258 8000984: 080019ed .word 0x080019ed 8000988: 240007dc .word 0x240007dc 800098c: 0801a268 .word 0x0801a268 8000990: 08001a09 .word 0x08001a09 8000994: 2400080c .word 0x2400080c 8000998: 0801a278 .word 0x0801a278 800099c: 08001a45 .word 0x08001a45 80009a0: 2400083c .word 0x2400083c 80009a4: 0801a224 .word 0x0801a224 80009a8: 080018a5 .word 0x080018a5 80009ac: 240007a8 .word 0x240007a8 080009b0 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80009b0: b580 push {r7, lr} 80009b2: b09c sub sp, #112 @ 0x70 80009b4: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80009b6: f107 0324 add.w r3, r7, #36 @ 0x24 80009ba: 224c movs r2, #76 @ 0x4c 80009bc: 2100 movs r1, #0 80009be: 4618 mov r0, r3 80009c0: f017 fd52 bl 8018468 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 80009c4: 1d3b adds r3, r7, #4 80009c6: 2220 movs r2, #32 80009c8: 2100 movs r1, #0 80009ca: 4618 mov r0, r3 80009cc: f017 fd4c bl 8018468 /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 80009d0: 2002 movs r0, #2 80009d2: f00a fd2b bl 800b42c /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 80009d6: 2300 movs r3, #0 80009d8: 603b str r3, [r7, #0] 80009da: 4b32 ldr r3, [pc, #200] @ (8000aa4 ) 80009dc: 6adb ldr r3, [r3, #44] @ 0x2c 80009de: 4a31 ldr r2, [pc, #196] @ (8000aa4 ) 80009e0: f023 0301 bic.w r3, r3, #1 80009e4: 62d3 str r3, [r2, #44] @ 0x2c 80009e6: 4b2f ldr r3, [pc, #188] @ (8000aa4 ) 80009e8: 6adb ldr r3, [r3, #44] @ 0x2c 80009ea: f003 0301 and.w r3, r3, #1 80009ee: 603b str r3, [r7, #0] 80009f0: 4b2d ldr r3, [pc, #180] @ (8000aa8 ) 80009f2: 699b ldr r3, [r3, #24] 80009f4: 4a2c ldr r2, [pc, #176] @ (8000aa8 ) 80009f6: f443 4340 orr.w r3, r3, #49152 @ 0xc000 80009fa: 6193 str r3, [r2, #24] 80009fc: 4b2a ldr r3, [pc, #168] @ (8000aa8 ) 80009fe: 699b ldr r3, [r3, #24] 8000a00: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000a04: 603b str r3, [r7, #0] 8000a06: 683b ldr r3, [r7, #0] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 8000a08: bf00 nop 8000a0a: 4b27 ldr r3, [pc, #156] @ (8000aa8 ) 8000a0c: 699b ldr r3, [r3, #24] 8000a0e: f403 5300 and.w r3, r3, #8192 @ 0x2000 8000a12: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8000a16: d1f8 bne.n 8000a0a /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_LSI 8000a18: 2329 movs r3, #41 @ 0x29 8000a1a: 627b str r3, [r7, #36] @ 0x24 |RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000a1c: f44f 3380 mov.w r3, #65536 @ 0x10000 8000a20: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.LSIState = RCC_LSI_ON; 8000a22: 2301 movs r3, #1 8000a24: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; 8000a26: 2301 movs r3, #1 8000a28: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000a2a: 2302 movs r3, #2 8000a2c: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000a2e: 2302 movs r3, #2 8000a30: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.PLL.PLLM = 5; 8000a32: 2305 movs r3, #5 8000a34: 653b str r3, [r7, #80] @ 0x50 RCC_OscInitStruct.PLL.PLLN = 160; 8000a36: 23a0 movs r3, #160 @ 0xa0 8000a38: 657b str r3, [r7, #84] @ 0x54 RCC_OscInitStruct.PLL.PLLP = 2; 8000a3a: 2302 movs r3, #2 8000a3c: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLQ = 2; 8000a3e: 2302 movs r3, #2 8000a40: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLR = 2; 8000a42: 2302 movs r3, #2 8000a44: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 8000a46: 2308 movs r3, #8 8000a48: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 8000a4a: 2300 movs r3, #0 8000a4c: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL.PLLFRACN = 0; 8000a4e: 2300 movs r3, #0 8000a50: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000a52: f107 0324 add.w r3, r7, #36 @ 0x24 8000a56: 4618 mov r0, r3 8000a58: f00a fda8 bl 800b5ac 8000a5c: 4603 mov r3, r0 8000a5e: 2b00 cmp r3, #0 8000a60: d001 beq.n 8000a66 { Error_Handler(); 8000a62: f001 f893 bl 8001b8c } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000a66: 233f movs r3, #63 @ 0x3f 8000a68: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000a6a: 2303 movs r3, #3 8000a6c: 60bb str r3, [r7, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 8000a6e: 2300 movs r3, #0 8000a70: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 8000a72: 2308 movs r3, #8 8000a74: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 8000a76: 2340 movs r3, #64 @ 0x40 8000a78: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 8000a7a: 2340 movs r3, #64 @ 0x40 8000a7c: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 8000a7e: f44f 6380 mov.w r3, #1024 @ 0x400 8000a82: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 8000a84: 2340 movs r3, #64 @ 0x40 8000a86: 623b str r3, [r7, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8000a88: 1d3b adds r3, r7, #4 8000a8a: 2102 movs r1, #2 8000a8c: 4618 mov r0, r3 8000a8e: f00b f9e7 bl 800be60 8000a92: 4603 mov r3, r0 8000a94: 2b00 cmp r3, #0 8000a96: d001 beq.n 8000a9c { Error_Handler(); 8000a98: f001 f878 bl 8001b8c } } 8000a9c: bf00 nop 8000a9e: 3770 adds r7, #112 @ 0x70 8000aa0: 46bd mov sp, r7 8000aa2: bd80 pop {r7, pc} 8000aa4: 58000400 .word 0x58000400 8000aa8: 58024800 .word 0x58024800 08000aac : /** * @brief Peripherals Common Clock Configuration * @retval None */ void PeriphCommonClock_Config(void) { 8000aac: b580 push {r7, lr} 8000aae: b0b0 sub sp, #192 @ 0xc0 8000ab0: af00 add r7, sp, #0 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8000ab2: 463b mov r3, r7 8000ab4: 22c0 movs r2, #192 @ 0xc0 8000ab6: 2100 movs r1, #0 8000ab8: 4618 mov r0, r3 8000aba: f017 fcd5 bl 8018468 /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC; 8000abe: f44f 2200 mov.w r2, #524288 @ 0x80000 8000ac2: f04f 0300 mov.w r3, #0 8000ac6: e9c7 2300 strd r2, r3, [r7] PeriphClkInitStruct.PLL2.PLL2M = 5; 8000aca: 2305 movs r3, #5 8000acc: 60bb str r3, [r7, #8] PeriphClkInitStruct.PLL2.PLL2N = 90; 8000ace: 235a movs r3, #90 @ 0x5a 8000ad0: 60fb str r3, [r7, #12] PeriphClkInitStruct.PLL2.PLL2P = 25; 8000ad2: 2319 movs r3, #25 8000ad4: 613b str r3, [r7, #16] PeriphClkInitStruct.PLL2.PLL2Q = 3; 8000ad6: 2303 movs r3, #3 8000ad8: 617b str r3, [r7, #20] PeriphClkInitStruct.PLL2.PLL2R = 2; 8000ada: 2302 movs r3, #2 8000adc: 61bb str r3, [r7, #24] PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2; 8000ade: 2380 movs r3, #128 @ 0x80 8000ae0: 61fb str r3, [r7, #28] PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; 8000ae2: 2300 movs r3, #0 8000ae4: 623b str r3, [r7, #32] PeriphClkInitStruct.PLL2.PLL2FRACN = 0; 8000ae6: 2300 movs r3, #0 8000ae8: 627b str r3, [r7, #36] @ 0x24 PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; 8000aea: 2300 movs r3, #0 8000aec: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8000af0: 463b mov r3, r7 8000af2: 4618 mov r0, r3 8000af4: f00b fd82 bl 800c5fc 8000af8: 4603 mov r3, r0 8000afa: 2b00 cmp r3, #0 8000afc: d001 beq.n 8000b02 { Error_Handler(); 8000afe: f001 f845 bl 8001b8c } } 8000b02: bf00 nop 8000b04: 37c0 adds r7, #192 @ 0xc0 8000b06: 46bd mov sp, r7 8000b08: bd80 pop {r7, pc} ... 08000b0c : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 8000b0c: b580 push {r7, lr} 8000b0e: b08a sub sp, #40 @ 0x28 8000b10: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_MultiModeTypeDef multimode = {0}; 8000b12: f107 031c add.w r3, r7, #28 8000b16: 2200 movs r2, #0 8000b18: 601a str r2, [r3, #0] 8000b1a: 605a str r2, [r3, #4] 8000b1c: 609a str r2, [r3, #8] ADC_ChannelConfTypeDef sConfig = {0}; 8000b1e: 463b mov r3, r7 8000b20: 2200 movs r2, #0 8000b22: 601a str r2, [r3, #0] 8000b24: 605a str r2, [r3, #4] 8000b26: 609a str r2, [r3, #8] 8000b28: 60da str r2, [r3, #12] 8000b2a: 611a str r2, [r3, #16] 8000b2c: 615a str r2, [r3, #20] 8000b2e: 619a str r2, [r3, #24] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 8000b30: 4b64 ldr r3, [pc, #400] @ (8000cc4 ) 8000b32: 4a65 ldr r2, [pc, #404] @ (8000cc8 ) 8000b34: 601a str r2, [r3, #0] hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 8000b36: 4b63 ldr r3, [pc, #396] @ (8000cc4 ) 8000b38: 2200 movs r2, #0 8000b3a: 605a str r2, [r3, #4] hadc1.Init.Resolution = ADC_RESOLUTION_16B; 8000b3c: 4b61 ldr r3, [pc, #388] @ (8000cc4 ) 8000b3e: 2200 movs r2, #0 8000b40: 609a str r2, [r3, #8] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000b42: 4b60 ldr r3, [pc, #384] @ (8000cc4 ) 8000b44: 2201 movs r2, #1 8000b46: 60da str r2, [r3, #12] hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 8000b48: 4b5e ldr r3, [pc, #376] @ (8000cc4 ) 8000b4a: 2204 movs r2, #4 8000b4c: 611a str r2, [r3, #16] hadc1.Init.LowPowerAutoWait = DISABLE; 8000b4e: 4b5d ldr r3, [pc, #372] @ (8000cc4 ) 8000b50: 2200 movs r2, #0 8000b52: 751a strb r2, [r3, #20] hadc1.Init.ContinuousConvMode = ENABLE; 8000b54: 4b5b ldr r3, [pc, #364] @ (8000cc4 ) 8000b56: 2201 movs r2, #1 8000b58: 755a strb r2, [r3, #21] hadc1.Init.NbrOfConversion = 7; 8000b5a: 4b5a ldr r3, [pc, #360] @ (8000cc4 ) 8000b5c: 2207 movs r2, #7 8000b5e: 619a str r2, [r3, #24] hadc1.Init.DiscontinuousConvMode = DISABLE; 8000b60: 4b58 ldr r3, [pc, #352] @ (8000cc4 ) 8000b62: 2200 movs r2, #0 8000b64: 771a strb r2, [r3, #28] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T8_TRGO; 8000b66: 4b57 ldr r3, [pc, #348] @ (8000cc4 ) 8000b68: f44f 629c mov.w r2, #1248 @ 0x4e0 8000b6c: 625a str r2, [r3, #36] @ 0x24 hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000b6e: 4b55 ldr r3, [pc, #340] @ (8000cc4 ) 8000b70: f44f 6280 mov.w r2, #1024 @ 0x400 8000b74: 629a str r2, [r3, #40] @ 0x28 hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000b76: 4b53 ldr r3, [pc, #332] @ (8000cc4 ) 8000b78: 2201 movs r2, #1 8000b7a: 62da str r2, [r3, #44] @ 0x2c hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000b7c: 4b51 ldr r3, [pc, #324] @ (8000cc4 ) 8000b7e: 2200 movs r2, #0 8000b80: 631a str r2, [r3, #48] @ 0x30 hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000b82: 4b50 ldr r3, [pc, #320] @ (8000cc4 ) 8000b84: 2200 movs r2, #0 8000b86: 635a str r2, [r3, #52] @ 0x34 hadc1.Init.OversamplingMode = DISABLE; 8000b88: 4b4e ldr r3, [pc, #312] @ (8000cc4 ) 8000b8a: 2200 movs r2, #0 8000b8c: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc1) != HAL_OK) 8000b90: 484c ldr r0, [pc, #304] @ (8000cc4 ) 8000b92: f005 f8e3 bl 8005d5c 8000b96: 4603 mov r3, r0 8000b98: 2b00 cmp r3, #0 8000b9a: d001 beq.n 8000ba0 { Error_Handler(); 8000b9c: f000 fff6 bl 8001b8c } /** Configure the ADC multi-mode */ multimode.Mode = ADC_DUALMODE_REGSIMULT; 8000ba0: 2306 movs r3, #6 8000ba2: 61fb str r3, [r7, #28] multimode.DualModeData = ADC_DUALMODEDATAFORMAT_32_10_BITS; 8000ba4: f44f 4300 mov.w r3, #32768 @ 0x8000 8000ba8: 623b str r3, [r7, #32] multimode.TwoSamplingDelay = ADC_TWOSAMPLINGDELAY_1CYCLE; 8000baa: 2300 movs r3, #0 8000bac: 627b str r3, [r7, #36] @ 0x24 if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 8000bae: f107 031c add.w r3, r7, #28 8000bb2: 4619 mov r1, r3 8000bb4: 4843 ldr r0, [pc, #268] @ (8000cc4 ) 8000bb6: f006 fae1 bl 800717c 8000bba: 4603 mov r3, r0 8000bbc: 2b00 cmp r3, #0 8000bbe: d001 beq.n 8000bc4 { Error_Handler(); 8000bc0: f000 ffe4 bl 8001b8c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8000bc4: 4b41 ldr r3, [pc, #260] @ (8000ccc ) 8000bc6: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_1; 8000bc8: 2306 movs r3, #6 8000bca: 607b str r3, [r7, #4] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 8000bcc: 2300 movs r3, #0 8000bce: 60bb str r3, [r7, #8] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000bd0: f240 73ff movw r3, #2047 @ 0x7ff 8000bd4: 60fb str r3, [r7, #12] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000bd6: 2304 movs r3, #4 8000bd8: 613b str r3, [r7, #16] sConfig.Offset = 0; 8000bda: 2300 movs r3, #0 8000bdc: 617b str r3, [r7, #20] sConfig.OffsetSignedSaturation = DISABLE; 8000bde: 2300 movs r3, #0 8000be0: 767b strb r3, [r7, #25] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000be2: 463b mov r3, r7 8000be4: 4619 mov r1, r3 8000be6: 4837 ldr r0, [pc, #220] @ (8000cc4 ) 8000be8: f005 fb32 bl 8006250 8000bec: 4603 mov r3, r0 8000bee: 2b00 cmp r3, #0 8000bf0: d001 beq.n 8000bf6 { Error_Handler(); 8000bf2: f000 ffcb bl 8001b8c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_9; 8000bf6: 4b36 ldr r3, [pc, #216] @ (8000cd0 ) 8000bf8: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_2; 8000bfa: 230c movs r3, #12 8000bfc: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000bfe: 463b mov r3, r7 8000c00: 4619 mov r1, r3 8000c02: 4830 ldr r0, [pc, #192] @ (8000cc4 ) 8000c04: f005 fb24 bl 8006250 8000c08: 4603 mov r3, r0 8000c0a: 2b00 cmp r3, #0 8000c0c: d001 beq.n 8000c12 { Error_Handler(); 8000c0e: f000 ffbd bl 8001b8c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_7; 8000c12: 4b30 ldr r3, [pc, #192] @ (8000cd4 ) 8000c14: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_3; 8000c16: 2312 movs r3, #18 8000c18: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c1a: 463b mov r3, r7 8000c1c: 4619 mov r1, r3 8000c1e: 4829 ldr r0, [pc, #164] @ (8000cc4 ) 8000c20: f005 fb16 bl 8006250 8000c24: 4603 mov r3, r0 8000c26: 2b00 cmp r3, #0 8000c28: d001 beq.n 8000c2e { Error_Handler(); 8000c2a: f000 ffaf bl 8001b8c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_16; 8000c2e: 4b2a ldr r3, [pc, #168] @ (8000cd8 ) 8000c30: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_4; 8000c32: 2318 movs r3, #24 8000c34: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c36: 463b mov r3, r7 8000c38: 4619 mov r1, r3 8000c3a: 4822 ldr r0, [pc, #136] @ (8000cc4 ) 8000c3c: f005 fb08 bl 8006250 8000c40: 4603 mov r3, r0 8000c42: 2b00 cmp r3, #0 8000c44: d001 beq.n 8000c4a { Error_Handler(); 8000c46: f000 ffa1 bl 8001b8c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_17; 8000c4a: 4b24 ldr r3, [pc, #144] @ (8000cdc ) 8000c4c: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_5; 8000c4e: f44f 7380 mov.w r3, #256 @ 0x100 8000c52: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c54: 463b mov r3, r7 8000c56: 4619 mov r1, r3 8000c58: 481a ldr r0, [pc, #104] @ (8000cc4 ) 8000c5a: f005 faf9 bl 8006250 8000c5e: 4603 mov r3, r0 8000c60: 2b00 cmp r3, #0 8000c62: d001 beq.n 8000c68 { Error_Handler(); 8000c64: f000 ff92 bl 8001b8c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_14; 8000c68: 4b1d ldr r3, [pc, #116] @ (8000ce0 ) 8000c6a: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_6; 8000c6c: f44f 7383 mov.w r3, #262 @ 0x106 8000c70: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c72: 463b mov r3, r7 8000c74: 4619 mov r1, r3 8000c76: 4813 ldr r0, [pc, #76] @ (8000cc4 ) 8000c78: f005 faea bl 8006250 8000c7c: 4603 mov r3, r0 8000c7e: 2b00 cmp r3, #0 8000c80: d001 beq.n 8000c86 { Error_Handler(); 8000c82: f000 ff83 bl 8001b8c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_15; 8000c86: 4b17 ldr r3, [pc, #92] @ (8000ce4 ) 8000c88: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_7; 8000c8a: f44f 7386 mov.w r3, #268 @ 0x10c 8000c8e: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c90: 463b mov r3, r7 8000c92: 4619 mov r1, r3 8000c94: 480b ldr r0, [pc, #44] @ (8000cc4 ) 8000c96: f005 fadb bl 8006250 8000c9a: 4603 mov r3, r0 8000c9c: 2b00 cmp r3, #0 8000c9e: d001 beq.n 8000ca4 { Error_Handler(); 8000ca0: f000 ff74 bl 8001b8c } /* USER CODE BEGIN ADC1_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000ca4: f240 72ff movw r2, #2047 @ 0x7ff 8000ca8: f04f 1101 mov.w r1, #65537 @ 0x10001 8000cac: 4805 ldr r0, [pc, #20] @ (8000cc4 ) 8000cae: f006 f923 bl 8006ef8 8000cb2: 4603 mov r3, r0 8000cb4: 2b00 cmp r3, #0 8000cb6: d001 beq.n 8000cbc { Error_Handler(); 8000cb8: f000 ff68 bl 8001b8c } /* USER CODE END ADC1_Init 2 */ } 8000cbc: bf00 nop 8000cbe: 3728 adds r7, #40 @ 0x28 8000cc0: 46bd mov sp, r7 8000cc2: bd80 pop {r7, pc} 8000cc4: 24000280 .word 0x24000280 8000cc8: 40022000 .word 0x40022000 8000ccc: 21800100 .word 0x21800100 8000cd0: 25b00200 .word 0x25b00200 8000cd4: 1d500080 .word 0x1d500080 8000cd8: 43210000 .word 0x43210000 8000cdc: 47520000 .word 0x47520000 8000ce0: 3ac04000 .word 0x3ac04000 8000ce4: 3ef08000 .word 0x3ef08000 08000ce8 : * @brief ADC2 Initialization Function * @param None * @retval None */ static void MX_ADC2_Init(void) { 8000ce8: b580 push {r7, lr} 8000cea: b088 sub sp, #32 8000cec: af00 add r7, sp, #0 /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000cee: 1d3b adds r3, r7, #4 8000cf0: 2200 movs r2, #0 8000cf2: 601a str r2, [r3, #0] 8000cf4: 605a str r2, [r3, #4] 8000cf6: 609a str r2, [r3, #8] 8000cf8: 60da str r2, [r3, #12] 8000cfa: 611a str r2, [r3, #16] 8000cfc: 615a str r2, [r3, #20] 8000cfe: 619a str r2, [r3, #24] /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; 8000d00: 4b3a ldr r3, [pc, #232] @ (8000dec ) 8000d02: 4a3b ldr r2, [pc, #236] @ (8000df0 ) 8000d04: 601a str r2, [r3, #0] hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 8000d06: 4b39 ldr r3, [pc, #228] @ (8000dec ) 8000d08: 2200 movs r2, #0 8000d0a: 605a str r2, [r3, #4] hadc2.Init.Resolution = ADC_RESOLUTION_16B; 8000d0c: 4b37 ldr r3, [pc, #220] @ (8000dec ) 8000d0e: 2200 movs r2, #0 8000d10: 609a str r2, [r3, #8] hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000d12: 4b36 ldr r3, [pc, #216] @ (8000dec ) 8000d14: 2201 movs r2, #1 8000d16: 60da str r2, [r3, #12] hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 8000d18: 4b34 ldr r3, [pc, #208] @ (8000dec ) 8000d1a: 2204 movs r2, #4 8000d1c: 611a str r2, [r3, #16] hadc2.Init.LowPowerAutoWait = DISABLE; 8000d1e: 4b33 ldr r3, [pc, #204] @ (8000dec ) 8000d20: 2200 movs r2, #0 8000d22: 751a strb r2, [r3, #20] hadc2.Init.ContinuousConvMode = ENABLE; 8000d24: 4b31 ldr r3, [pc, #196] @ (8000dec ) 8000d26: 2201 movs r2, #1 8000d28: 755a strb r2, [r3, #21] hadc2.Init.NbrOfConversion = 3; 8000d2a: 4b30 ldr r3, [pc, #192] @ (8000dec ) 8000d2c: 2203 movs r2, #3 8000d2e: 619a str r2, [r3, #24] hadc2.Init.DiscontinuousConvMode = DISABLE; 8000d30: 4b2e ldr r3, [pc, #184] @ (8000dec ) 8000d32: 2200 movs r2, #0 8000d34: 771a strb r2, [r3, #28] hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000d36: 4b2d ldr r3, [pc, #180] @ (8000dec ) 8000d38: 2201 movs r2, #1 8000d3a: 62da str r2, [r3, #44] @ 0x2c hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000d3c: 4b2b ldr r3, [pc, #172] @ (8000dec ) 8000d3e: 2200 movs r2, #0 8000d40: 631a str r2, [r3, #48] @ 0x30 hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000d42: 4b2a ldr r3, [pc, #168] @ (8000dec ) 8000d44: 2200 movs r2, #0 8000d46: 635a str r2, [r3, #52] @ 0x34 hadc2.Init.OversamplingMode = DISABLE; 8000d48: 4b28 ldr r3, [pc, #160] @ (8000dec ) 8000d4a: 2200 movs r2, #0 8000d4c: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc2) != HAL_OK) 8000d50: 4826 ldr r0, [pc, #152] @ (8000dec ) 8000d52: f005 f803 bl 8005d5c 8000d56: 4603 mov r3, r0 8000d58: 2b00 cmp r3, #0 8000d5a: d001 beq.n 8000d60 { Error_Handler(); 8000d5c: f000 ff16 bl 8001b8c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 8000d60: 4b24 ldr r3, [pc, #144] @ (8000df4 ) 8000d62: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8000d64: 2306 movs r3, #6 8000d66: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 8000d68: 2300 movs r3, #0 8000d6a: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000d6c: f240 73ff movw r3, #2047 @ 0x7ff 8000d70: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000d72: 2304 movs r3, #4 8000d74: 617b str r3, [r7, #20] sConfig.Offset = 0; 8000d76: 2300 movs r3, #0 8000d78: 61bb str r3, [r7, #24] sConfig.OffsetSignedSaturation = DISABLE; 8000d7a: 2300 movs r3, #0 8000d7c: 777b strb r3, [r7, #29] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000d7e: 1d3b adds r3, r7, #4 8000d80: 4619 mov r1, r3 8000d82: 481a ldr r0, [pc, #104] @ (8000dec ) 8000d84: f005 fa64 bl 8006250 8000d88: 4603 mov r3, r0 8000d8a: 2b00 cmp r3, #0 8000d8c: d001 beq.n 8000d92 { Error_Handler(); 8000d8e: f000 fefd bl 8001b8c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8000d92: 4b19 ldr r3, [pc, #100] @ (8000df8 ) 8000d94: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 8000d96: 230c movs r3, #12 8000d98: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000d9a: 1d3b adds r3, r7, #4 8000d9c: 4619 mov r1, r3 8000d9e: 4813 ldr r0, [pc, #76] @ (8000dec ) 8000da0: f005 fa56 bl 8006250 8000da4: 4603 mov r3, r0 8000da6: 2b00 cmp r3, #0 8000da8: d001 beq.n 8000dae { Error_Handler(); 8000daa: f000 feef bl 8001b8c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_5; 8000dae: 4b13 ldr r3, [pc, #76] @ (8000dfc ) 8000db0: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8000db2: 2312 movs r3, #18 8000db4: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000db6: 1d3b adds r3, r7, #4 8000db8: 4619 mov r1, r3 8000dba: 480c ldr r0, [pc, #48] @ (8000dec ) 8000dbc: f005 fa48 bl 8006250 8000dc0: 4603 mov r3, r0 8000dc2: 2b00 cmp r3, #0 8000dc4: d001 beq.n 8000dca { Error_Handler(); 8000dc6: f000 fee1 bl 8001b8c } /* USER CODE BEGIN ADC2_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc2, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000dca: f240 72ff movw r2, #2047 @ 0x7ff 8000dce: f04f 1101 mov.w r1, #65537 @ 0x10001 8000dd2: 4806 ldr r0, [pc, #24] @ (8000dec ) 8000dd4: f006 f890 bl 8006ef8 8000dd8: 4603 mov r3, r0 8000dda: 2b00 cmp r3, #0 8000ddc: d001 beq.n 8000de2 { Error_Handler(); 8000dde: f000 fed5 bl 8001b8c } /* USER CODE END ADC2_Init 2 */ } 8000de2: bf00 nop 8000de4: 3720 adds r7, #32 8000de6: 46bd mov sp, r7 8000de8: bd80 pop {r7, pc} 8000dea: bf00 nop 8000dec: 240002e4 .word 0x240002e4 8000df0: 40022100 .word 0x40022100 8000df4: 0c900008 .word 0x0c900008 8000df8: 10c00010 .word 0x10c00010 8000dfc: 14f00020 .word 0x14f00020 08000e00 : * @brief ADC3 Initialization Function * @param None * @retval None */ static void MX_ADC3_Init(void) { 8000e00: b580 push {r7, lr} 8000e02: b088 sub sp, #32 8000e04: af00 add r7, sp, #0 /* USER CODE BEGIN ADC3_Init 0 */ /* USER CODE END ADC3_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000e06: 1d3b adds r3, r7, #4 8000e08: 2200 movs r2, #0 8000e0a: 601a str r2, [r3, #0] 8000e0c: 605a str r2, [r3, #4] 8000e0e: 609a str r2, [r3, #8] 8000e10: 60da str r2, [r3, #12] 8000e12: 611a str r2, [r3, #16] 8000e14: 615a str r2, [r3, #20] 8000e16: 619a str r2, [r3, #24] /* USER CODE END ADC3_Init 1 */ /** Common config */ hadc3.Instance = ADC3; 8000e18: 4b4c ldr r3, [pc, #304] @ (8000f4c ) 8000e1a: 4a4d ldr r2, [pc, #308] @ (8000f50 ) 8000e1c: 601a str r2, [r3, #0] hadc3.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 8000e1e: 4b4b ldr r3, [pc, #300] @ (8000f4c ) 8000e20: 2200 movs r2, #0 8000e22: 605a str r2, [r3, #4] hadc3.Init.Resolution = ADC_RESOLUTION_16B; 8000e24: 4b49 ldr r3, [pc, #292] @ (8000f4c ) 8000e26: 2200 movs r2, #0 8000e28: 609a str r2, [r3, #8] hadc3.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000e2a: 4b48 ldr r3, [pc, #288] @ (8000f4c ) 8000e2c: 2201 movs r2, #1 8000e2e: 60da str r2, [r3, #12] hadc3.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000e30: 4b46 ldr r3, [pc, #280] @ (8000f4c ) 8000e32: 2208 movs r2, #8 8000e34: 611a str r2, [r3, #16] hadc3.Init.LowPowerAutoWait = DISABLE; 8000e36: 4b45 ldr r3, [pc, #276] @ (8000f4c ) 8000e38: 2200 movs r2, #0 8000e3a: 751a strb r2, [r3, #20] hadc3.Init.ContinuousConvMode = ENABLE; 8000e3c: 4b43 ldr r3, [pc, #268] @ (8000f4c ) 8000e3e: 2201 movs r2, #1 8000e40: 755a strb r2, [r3, #21] hadc3.Init.NbrOfConversion = 5; 8000e42: 4b42 ldr r3, [pc, #264] @ (8000f4c ) 8000e44: 2205 movs r2, #5 8000e46: 619a str r2, [r3, #24] hadc3.Init.DiscontinuousConvMode = DISABLE; 8000e48: 4b40 ldr r3, [pc, #256] @ (8000f4c ) 8000e4a: 2200 movs r2, #0 8000e4c: 771a strb r2, [r3, #28] hadc3.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T8_TRGO; 8000e4e: 4b3f ldr r3, [pc, #252] @ (8000f4c ) 8000e50: f44f 629c mov.w r2, #1248 @ 0x4e0 8000e54: 625a str r2, [r3, #36] @ 0x24 hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000e56: 4b3d ldr r3, [pc, #244] @ (8000f4c ) 8000e58: f44f 6280 mov.w r2, #1024 @ 0x400 8000e5c: 629a str r2, [r3, #40] @ 0x28 hadc3.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000e5e: 4b3b ldr r3, [pc, #236] @ (8000f4c ) 8000e60: 2201 movs r2, #1 8000e62: 62da str r2, [r3, #44] @ 0x2c hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000e64: 4b39 ldr r3, [pc, #228] @ (8000f4c ) 8000e66: 2200 movs r2, #0 8000e68: 631a str r2, [r3, #48] @ 0x30 hadc3.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000e6a: 4b38 ldr r3, [pc, #224] @ (8000f4c ) 8000e6c: 2200 movs r2, #0 8000e6e: 635a str r2, [r3, #52] @ 0x34 hadc3.Init.OversamplingMode = DISABLE; 8000e70: 4b36 ldr r3, [pc, #216] @ (8000f4c ) 8000e72: 2200 movs r2, #0 8000e74: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc3) != HAL_OK) 8000e78: 4834 ldr r0, [pc, #208] @ (8000f4c ) 8000e7a: f004 ff6f bl 8005d5c 8000e7e: 4603 mov r3, r0 8000e80: 2b00 cmp r3, #0 8000e82: d001 beq.n 8000e88 { Error_Handler(); 8000e84: f000 fe82 bl 8001b8c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_0; 8000e88: 2301 movs r3, #1 8000e8a: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8000e8c: 2306 movs r3, #6 8000e8e: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000e90: 2306 movs r3, #6 8000e92: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000e94: f240 73ff movw r3, #2047 @ 0x7ff 8000e98: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000e9a: 2304 movs r3, #4 8000e9c: 617b str r3, [r7, #20] sConfig.Offset = 0; 8000e9e: 2300 movs r3, #0 8000ea0: 61bb str r3, [r7, #24] sConfig.OffsetSignedSaturation = DISABLE; 8000ea2: 2300 movs r3, #0 8000ea4: 777b strb r3, [r7, #29] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000ea6: 1d3b adds r3, r7, #4 8000ea8: 4619 mov r1, r3 8000eaa: 4828 ldr r0, [pc, #160] @ (8000f4c ) 8000eac: f005 f9d0 bl 8006250 8000eb0: 4603 mov r3, r0 8000eb2: 2b00 cmp r3, #0 8000eb4: d001 beq.n 8000eba { Error_Handler(); 8000eb6: f000 fe69 bl 8001b8c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 8000eba: 4b26 ldr r3, [pc, #152] @ (8000f54 ) 8000ebc: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 8000ebe: 230c movs r3, #12 8000ec0: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000ec2: 1d3b adds r3, r7, #4 8000ec4: 4619 mov r1, r3 8000ec6: 4821 ldr r0, [pc, #132] @ (8000f4c ) 8000ec8: f005 f9c2 bl 8006250 8000ecc: 4603 mov r3, r0 8000ece: 2b00 cmp r3, #0 8000ed0: d001 beq.n 8000ed6 { Error_Handler(); 8000ed2: f000 fe5b bl 8001b8c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_10; 8000ed6: 4b20 ldr r3, [pc, #128] @ (8000f58 ) 8000ed8: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8000eda: 2312 movs r3, #18 8000edc: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000ede: 1d3b adds r3, r7, #4 8000ee0: 4619 mov r1, r3 8000ee2: 481a ldr r0, [pc, #104] @ (8000f4c ) 8000ee4: f005 f9b4 bl 8006250 8000ee8: 4603 mov r3, r0 8000eea: 2b00 cmp r3, #0 8000eec: d001 beq.n 8000ef2 { Error_Handler(); 8000eee: f000 fe4d bl 8001b8c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_11; 8000ef2: 4b1a ldr r3, [pc, #104] @ (8000f5c ) 8000ef4: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_4; 8000ef6: 2318 movs r3, #24 8000ef8: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000efa: 1d3b adds r3, r7, #4 8000efc: 4619 mov r1, r3 8000efe: 4813 ldr r0, [pc, #76] @ (8000f4c ) 8000f00: f005 f9a6 bl 8006250 8000f04: 4603 mov r3, r0 8000f06: 2b00 cmp r3, #0 8000f08: d001 beq.n 8000f0e { Error_Handler(); 8000f0a: f000 fe3f bl 8001b8c } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; 8000f0e: 4b14 ldr r3, [pc, #80] @ (8000f60 ) 8000f10: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_5; 8000f12: f44f 7380 mov.w r3, #256 @ 0x100 8000f16: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000f18: 1d3b adds r3, r7, #4 8000f1a: 4619 mov r1, r3 8000f1c: 480b ldr r0, [pc, #44] @ (8000f4c ) 8000f1e: f005 f997 bl 8006250 8000f22: 4603 mov r3, r0 8000f24: 2b00 cmp r3, #0 8000f26: d001 beq.n 8000f2c { Error_Handler(); 8000f28: f000 fe30 bl 8001b8c } /* USER CODE BEGIN ADC3_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc3, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000f2c: f240 72ff movw r2, #2047 @ 0x7ff 8000f30: f04f 1101 mov.w r1, #65537 @ 0x10001 8000f34: 4805 ldr r0, [pc, #20] @ (8000f4c ) 8000f36: f005 ffdf bl 8006ef8 8000f3a: 4603 mov r3, r0 8000f3c: 2b00 cmp r3, #0 8000f3e: d001 beq.n 8000f44 { Error_Handler(); 8000f40: f000 fe24 bl 8001b8c } /* USER CODE END ADC3_Init 2 */ } 8000f44: bf00 nop 8000f46: 3720 adds r7, #32 8000f48: 46bd mov sp, r7 8000f4a: bd80 pop {r7, pc} 8000f4c: 24000348 .word 0x24000348 8000f50: 58026000 .word 0x58026000 8000f54: 04300002 .word 0x04300002 8000f58: 2a000400 .word 0x2a000400 8000f5c: 2e300800 .word 0x2e300800 8000f60: cfb80000 .word 0xcfb80000 08000f64 : * @brief COMP1 Initialization Function * @param None * @retval None */ static void MX_COMP1_Init(void) { 8000f64: b580 push {r7, lr} 8000f66: af00 add r7, sp, #0 /* USER CODE END COMP1_Init 0 */ /* USER CODE BEGIN COMP1_Init 1 */ /* USER CODE END COMP1_Init 1 */ hcomp1.Instance = COMP1; 8000f68: 4b12 ldr r3, [pc, #72] @ (8000fb4 ) 8000f6a: 4a13 ldr r2, [pc, #76] @ (8000fb8 ) 8000f6c: 601a str r2, [r3, #0] hcomp1.Init.InvertingInput = COMP_INPUT_MINUS_3_4VREFINT; 8000f6e: 4b11 ldr r3, [pc, #68] @ (8000fb4 ) 8000f70: 4a12 ldr r2, [pc, #72] @ (8000fbc ) 8000f72: 611a str r2, [r3, #16] hcomp1.Init.NonInvertingInput = COMP_INPUT_PLUS_IO2; 8000f74: 4b0f ldr r3, [pc, #60] @ (8000fb4 ) 8000f76: f44f 1280 mov.w r2, #1048576 @ 0x100000 8000f7a: 60da str r2, [r3, #12] hcomp1.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED; 8000f7c: 4b0d ldr r3, [pc, #52] @ (8000fb4 ) 8000f7e: 2200 movs r2, #0 8000f80: 619a str r2, [r3, #24] hcomp1.Init.Hysteresis = COMP_HYSTERESIS_NONE; 8000f82: 4b0c ldr r3, [pc, #48] @ (8000fb4 ) 8000f84: 2200 movs r2, #0 8000f86: 615a str r2, [r3, #20] hcomp1.Init.BlankingSrce = COMP_BLANKINGSRC_NONE; 8000f88: 4b0a ldr r3, [pc, #40] @ (8000fb4 ) 8000f8a: 2200 movs r2, #0 8000f8c: 61da str r2, [r3, #28] hcomp1.Init.Mode = COMP_POWERMODE_HIGHSPEED; 8000f8e: 4b09 ldr r3, [pc, #36] @ (8000fb4 ) 8000f90: 2200 movs r2, #0 8000f92: 609a str r2, [r3, #8] hcomp1.Init.WindowMode = COMP_WINDOWMODE_DISABLE; 8000f94: 4b07 ldr r3, [pc, #28] @ (8000fb4 ) 8000f96: 2200 movs r2, #0 8000f98: 605a str r2, [r3, #4] hcomp1.Init.TriggerMode = COMP_TRIGGERMODE_NONE; 8000f9a: 4b06 ldr r3, [pc, #24] @ (8000fb4 ) 8000f9c: 2200 movs r2, #0 8000f9e: 621a str r2, [r3, #32] if (HAL_COMP_Init(&hcomp1) != HAL_OK) 8000fa0: 4804 ldr r0, [pc, #16] @ (8000fb4 ) 8000fa2: f006 f9c9 bl 8007338 8000fa6: 4603 mov r3, r0 8000fa8: 2b00 cmp r3, #0 8000faa: d001 beq.n 8000fb0 { Error_Handler(); 8000fac: f000 fdee bl 8001b8c } /* USER CODE BEGIN COMP1_Init 2 */ /* USER CODE END COMP1_Init 2 */ } 8000fb0: bf00 nop 8000fb2: bd80 pop {r7, pc} 8000fb4: 24000514 .word 0x24000514 8000fb8: 5800380c .word 0x5800380c 8000fbc: 00020006 .word 0x00020006 08000fc0 : * @brief CRC Initialization Function * @param None * @retval None */ static void MX_CRC_Init(void) { 8000fc0: b580 push {r7, lr} 8000fc2: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 8000fc4: 4b11 ldr r3, [pc, #68] @ (800100c ) 8000fc6: 4a12 ldr r2, [pc, #72] @ (8001010 ) 8000fc8: 601a str r2, [r3, #0] hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_DISABLE; 8000fca: 4b10 ldr r3, [pc, #64] @ (800100c ) 8000fcc: 2201 movs r2, #1 8000fce: 711a strb r2, [r3, #4] hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE; 8000fd0: 4b0e ldr r3, [pc, #56] @ (800100c ) 8000fd2: 2200 movs r2, #0 8000fd4: 715a strb r2, [r3, #5] hcrc.Init.GeneratingPolynomial = 4129; 8000fd6: 4b0d ldr r3, [pc, #52] @ (800100c ) 8000fd8: f241 0221 movw r2, #4129 @ 0x1021 8000fdc: 609a str r2, [r3, #8] hcrc.Init.CRCLength = CRC_POLYLENGTH_16B; 8000fde: 4b0b ldr r3, [pc, #44] @ (800100c ) 8000fe0: 2208 movs r2, #8 8000fe2: 60da str r2, [r3, #12] hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE; 8000fe4: 4b09 ldr r3, [pc, #36] @ (800100c ) 8000fe6: 2200 movs r2, #0 8000fe8: 615a str r2, [r3, #20] hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE; 8000fea: 4b08 ldr r3, [pc, #32] @ (800100c ) 8000fec: 2200 movs r2, #0 8000fee: 619a str r2, [r3, #24] hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; 8000ff0: 4b06 ldr r3, [pc, #24] @ (800100c ) 8000ff2: 2201 movs r2, #1 8000ff4: 621a str r2, [r3, #32] if (HAL_CRC_Init(&hcrc) != HAL_OK) 8000ff6: 4805 ldr r0, [pc, #20] @ (800100c ) 8000ff8: f006 fc88 bl 800790c 8000ffc: 4603 mov r3, r0 8000ffe: 2b00 cmp r3, #0 8001000: d001 beq.n 8001006 { Error_Handler(); 8001002: f000 fdc3 bl 8001b8c } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 8001006: bf00 nop 8001008: bd80 pop {r7, pc} 800100a: bf00 nop 800100c: 24000540 .word 0x24000540 8001010: 58024c00 .word 0x58024c00 08001014 : * @brief DAC1 Initialization Function * @param None * @retval None */ static void MX_DAC1_Init(void) { 8001014: b580 push {r7, lr} 8001016: b08a sub sp, #40 @ 0x28 8001018: af00 add r7, sp, #0 /* USER CODE BEGIN DAC1_Init 0 */ /* USER CODE END DAC1_Init 0 */ DAC_ChannelConfTypeDef sConfig = {0}; 800101a: 1d3b adds r3, r7, #4 800101c: 2224 movs r2, #36 @ 0x24 800101e: 2100 movs r1, #0 8001020: 4618 mov r0, r3 8001022: f017 fa21 bl 8018468 /* USER CODE END DAC1_Init 1 */ /** DAC Initialization */ hdac1.Instance = DAC1; 8001026: 4b17 ldr r3, [pc, #92] @ (8001084 ) 8001028: 4a17 ldr r2, [pc, #92] @ (8001088 ) 800102a: 601a str r2, [r3, #0] if (HAL_DAC_Init(&hdac1) != HAL_OK) 800102c: 4815 ldr r0, [pc, #84] @ (8001084 ) 800102e: f006 fe73 bl 8007d18 8001032: 4603 mov r3, r0 8001034: 2b00 cmp r3, #0 8001036: d001 beq.n 800103c { Error_Handler(); 8001038: f000 fda8 bl 8001b8c } /** DAC channel OUT1 config */ sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; 800103c: 2300 movs r3, #0 800103e: 607b str r3, [r7, #4] sConfig.DAC_Trigger = DAC_TRIGGER_NONE; 8001040: 2300 movs r3, #0 8001042: 60bb str r3, [r7, #8] sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; 8001044: 2300 movs r3, #0 8001046: 60fb str r3, [r7, #12] sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE; 8001048: 2301 movs r3, #1 800104a: 613b str r3, [r7, #16] sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; 800104c: 2300 movs r3, #0 800104e: 617b str r3, [r7, #20] if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) 8001050: 1d3b adds r3, r7, #4 8001052: 2200 movs r2, #0 8001054: 4619 mov r1, r3 8001056: 480b ldr r0, [pc, #44] @ (8001084 ) 8001058: f006 ff62 bl 8007f20 800105c: 4603 mov r3, r0 800105e: 2b00 cmp r3, #0 8001060: d001 beq.n 8001066 { Error_Handler(); 8001062: f000 fd93 bl 8001b8c } /** DAC channel OUT2 config */ if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK) 8001066: 1d3b adds r3, r7, #4 8001068: 2210 movs r2, #16 800106a: 4619 mov r1, r3 800106c: 4805 ldr r0, [pc, #20] @ (8001084 ) 800106e: f006 ff57 bl 8007f20 8001072: 4603 mov r3, r0 8001074: 2b00 cmp r3, #0 8001076: d001 beq.n 800107c { Error_Handler(); 8001078: f000 fd88 bl 8001b8c } /* USER CODE BEGIN DAC1_Init 2 */ /* USER CODE END DAC1_Init 2 */ } 800107c: bf00 nop 800107e: 3728 adds r7, #40 @ 0x28 8001080: 46bd mov sp, r7 8001082: bd80 pop {r7, pc} 8001084: 24000564 .word 0x24000564 8001088: 40007400 .word 0x40007400 0800108c : * @brief IWDG1 Initialization Function * @param None * @retval None */ static void MX_IWDG1_Init(void) { 800108c: b580 push {r7, lr} 800108e: af00 add r7, sp, #0 /* USER CODE END IWDG1_Init 0 */ /* USER CODE BEGIN IWDG1_Init 1 */ /* USER CODE END IWDG1_Init 1 */ hiwdg1.Instance = IWDG1; 8001090: 4b0a ldr r3, [pc, #40] @ (80010bc ) 8001092: 4a0b ldr r2, [pc, #44] @ (80010c0 ) 8001094: 601a str r2, [r3, #0] hiwdg1.Init.Prescaler = IWDG_PRESCALER_64; 8001096: 4b09 ldr r3, [pc, #36] @ (80010bc ) 8001098: 2204 movs r2, #4 800109a: 605a str r2, [r3, #4] hiwdg1.Init.Window = 249; 800109c: 4b07 ldr r3, [pc, #28] @ (80010bc ) 800109e: 22f9 movs r2, #249 @ 0xf9 80010a0: 60da str r2, [r3, #12] hiwdg1.Init.Reload = 249; 80010a2: 4b06 ldr r3, [pc, #24] @ (80010bc ) 80010a4: 22f9 movs r2, #249 @ 0xf9 80010a6: 609a str r2, [r3, #8] if (HAL_IWDG_Init(&hiwdg1) != HAL_OK) 80010a8: 4804 ldr r0, [pc, #16] @ (80010bc ) 80010aa: f00a f8d6 bl 800b25a 80010ae: 4603 mov r3, r0 80010b0: 2b00 cmp r3, #0 80010b2: d001 beq.n 80010b8 { Error_Handler(); 80010b4: f000 fd6a bl 8001b8c } /* USER CODE BEGIN IWDG1_Init 2 */ /* USER CODE END IWDG1_Init 2 */ } 80010b8: bf00 nop 80010ba: bd80 pop {r7, pc} 80010bc: 24000578 .word 0x24000578 80010c0: 58004800 .word 0x58004800 080010c4 : * @brief RNG Initialization Function * @param None * @retval None */ static void MX_RNG_Init(void) { 80010c4: b580 push {r7, lr} 80010c6: af00 add r7, sp, #0 /* USER CODE END RNG_Init 0 */ /* USER CODE BEGIN RNG_Init 1 */ /* USER CODE END RNG_Init 1 */ hrng.Instance = RNG; 80010c8: 4b07 ldr r3, [pc, #28] @ (80010e8 ) 80010ca: 4a08 ldr r2, [pc, #32] @ (80010ec ) 80010cc: 601a str r2, [r3, #0] hrng.Init.ClockErrorDetection = RNG_CED_ENABLE; 80010ce: 4b06 ldr r3, [pc, #24] @ (80010e8 ) 80010d0: 2200 movs r2, #0 80010d2: 605a str r2, [r3, #4] if (HAL_RNG_Init(&hrng) != HAL_OK) 80010d4: 4804 ldr r0, [pc, #16] @ (80010e8 ) 80010d6: f00d ff73 bl 800efc0 80010da: 4603 mov r3, r0 80010dc: 2b00 cmp r3, #0 80010de: d001 beq.n 80010e4 { Error_Handler(); 80010e0: f000 fd54 bl 8001b8c } /* USER CODE BEGIN RNG_Init 2 */ /* USER CODE END RNG_Init 2 */ } 80010e4: bf00 nop 80010e6: bd80 pop {r7, pc} 80010e8: 24000588 .word 0x24000588 80010ec: 48021800 .word 0x48021800 080010f0 : * @brief TIM1 Initialization Function * @param None * @retval None */ static void MX_TIM1_Init(void) { 80010f0: b5b0 push {r4, r5, r7, lr} 80010f2: b096 sub sp, #88 @ 0x58 80010f4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 80010f6: f107 034c add.w r3, r7, #76 @ 0x4c 80010fa: 2200 movs r2, #0 80010fc: 601a str r2, [r3, #0] 80010fe: 605a str r2, [r3, #4] 8001100: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 8001102: f107 0330 add.w r3, r7, #48 @ 0x30 8001106: 2200 movs r2, #0 8001108: 601a str r2, [r3, #0] 800110a: 605a str r2, [r3, #4] 800110c: 609a str r2, [r3, #8] 800110e: 60da str r2, [r3, #12] 8001110: 611a str r2, [r3, #16] 8001112: 615a str r2, [r3, #20] 8001114: 619a str r2, [r3, #24] TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 8001116: 1d3b adds r3, r7, #4 8001118: 222c movs r2, #44 @ 0x2c 800111a: 2100 movs r1, #0 800111c: 4618 mov r0, r3 800111e: f017 f9a3 bl 8018468 /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; 8001122: 4b3e ldr r3, [pc, #248] @ (800121c ) 8001124: 4a3e ldr r2, [pc, #248] @ (8001220 ) 8001126: 601a str r2, [r3, #0] htim1.Init.Prescaler = 199; 8001128: 4b3c ldr r3, [pc, #240] @ (800121c ) 800112a: 22c7 movs r2, #199 @ 0xc7 800112c: 605a str r2, [r3, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 800112e: 4b3b ldr r3, [pc, #236] @ (800121c ) 8001130: 2200 movs r2, #0 8001132: 609a str r2, [r3, #8] htim1.Init.Period = 999; 8001134: 4b39 ldr r3, [pc, #228] @ (800121c ) 8001136: f240 32e7 movw r2, #999 @ 0x3e7 800113a: 60da str r2, [r3, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800113c: 4b37 ldr r3, [pc, #220] @ (800121c ) 800113e: 2200 movs r2, #0 8001140: 611a str r2, [r3, #16] htim1.Init.RepetitionCounter = 0; 8001142: 4b36 ldr r3, [pc, #216] @ (800121c ) 8001144: 2200 movs r2, #0 8001146: 615a str r2, [r3, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001148: 4b34 ldr r3, [pc, #208] @ (800121c ) 800114a: 2280 movs r2, #128 @ 0x80 800114c: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 800114e: 4833 ldr r0, [pc, #204] @ (800121c ) 8001150: f00e f8d8 bl 800f304 8001154: 4603 mov r3, r0 8001156: 2b00 cmp r3, #0 8001158: d001 beq.n 800115e { Error_Handler(); 800115a: f000 fd17 bl 8001b8c } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800115e: 2300 movs r3, #0 8001160: 64fb str r3, [r7, #76] @ 0x4c sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 8001162: 2300 movs r3, #0 8001164: 653b str r3, [r7, #80] @ 0x50 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8001166: 2300 movs r3, #0 8001168: 657b str r3, [r7, #84] @ 0x54 if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 800116a: f107 034c add.w r3, r7, #76 @ 0x4c 800116e: 4619 mov r1, r3 8001170: 482a ldr r0, [pc, #168] @ (800121c ) 8001172: f00f fa79 bl 8010668 8001176: 4603 mov r3, r0 8001178: 2b00 cmp r3, #0 800117a: d001 beq.n 8001180 { Error_Handler(); 800117c: f000 fd06 bl 8001b8c } sConfigOC.OCMode = TIM_OCMODE_PWM1; 8001180: 2360 movs r3, #96 @ 0x60 8001182: 633b str r3, [r7, #48] @ 0x30 sConfigOC.Pulse = 99; 8001184: 2363 movs r3, #99 @ 0x63 8001186: 637b str r3, [r7, #52] @ 0x34 sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8001188: 2300 movs r3, #0 800118a: 63bb str r3, [r7, #56] @ 0x38 sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 800118c: 2300 movs r3, #0 800118e: 63fb str r3, [r7, #60] @ 0x3c sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001190: 2300 movs r3, #0 8001192: 643b str r3, [r7, #64] @ 0x40 sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 8001194: 2300 movs r3, #0 8001196: 647b str r3, [r7, #68] @ 0x44 sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 8001198: 2300 movs r3, #0 800119a: 64bb str r3, [r7, #72] @ 0x48 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800119c: f107 0330 add.w r3, r7, #48 @ 0x30 80011a0: 2204 movs r2, #4 80011a2: 4619 mov r1, r3 80011a4: 481d ldr r0, [pc, #116] @ (800121c ) 80011a6: f00e fbb1 bl 800f90c 80011aa: 4603 mov r3, r0 80011ac: 2b00 cmp r3, #0 80011ae: d001 beq.n 80011b4 { Error_Handler(); 80011b0: f000 fcec bl 8001b8c } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 80011b4: 2300 movs r3, #0 80011b6: 607b str r3, [r7, #4] sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 80011b8: 2300 movs r3, #0 80011ba: 60bb str r3, [r7, #8] sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 80011bc: 2300 movs r3, #0 80011be: 60fb str r3, [r7, #12] sBreakDeadTimeConfig.DeadTime = 0; 80011c0: 2300 movs r3, #0 80011c2: 613b str r3, [r7, #16] sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 80011c4: 2300 movs r3, #0 80011c6: 617b str r3, [r7, #20] sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 80011c8: f44f 5300 mov.w r3, #8192 @ 0x2000 80011cc: 61bb str r3, [r7, #24] sBreakDeadTimeConfig.BreakFilter = 0; 80011ce: 2300 movs r3, #0 80011d0: 61fb str r3, [r7, #28] sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 80011d2: 2300 movs r3, #0 80011d4: 623b str r3, [r7, #32] sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 80011d6: f04f 7300 mov.w r3, #33554432 @ 0x2000000 80011da: 627b str r3, [r7, #36] @ 0x24 sBreakDeadTimeConfig.Break2Filter = 0; 80011dc: 2300 movs r3, #0 80011de: 62bb str r3, [r7, #40] @ 0x28 sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 80011e0: 2300 movs r3, #0 80011e2: 62fb str r3, [r7, #44] @ 0x2c if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 80011e4: 1d3b adds r3, r7, #4 80011e6: 4619 mov r1, r3 80011e8: 480c ldr r0, [pc, #48] @ (800121c ) 80011ea: f00f facb bl 8010784 80011ee: 4603 mov r3, r0 80011f0: 2b00 cmp r3, #0 80011f2: d001 beq.n 80011f8 { Error_Handler(); 80011f4: f000 fcca bl 8001b8c } /* USER CODE BEGIN TIM1_Init 2 */ memcpy(&fanTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 80011f8: 4b0a ldr r3, [pc, #40] @ (8001224 ) 80011fa: 461d mov r5, r3 80011fc: f107 0430 add.w r4, r7, #48 @ 0x30 8001200: cc0f ldmia r4!, {r0, r1, r2, r3} 8001202: c50f stmia r5!, {r0, r1, r2, r3} 8001204: e894 0007 ldmia.w r4, {r0, r1, r2} 8001208: e885 0007 stmia.w r5, {r0, r1, r2} /* USER CODE END TIM1_Init 2 */ HAL_TIM_MspPostInit(&htim1); 800120c: 4803 ldr r0, [pc, #12] @ (800121c ) 800120e: f002 fe1f bl 8003e50 } 8001212: bf00 nop 8001214: 3758 adds r7, #88 @ 0x58 8001216: 46bd mov sp, r7 8001218: bdb0 pop {r4, r5, r7, pc} 800121a: bf00 nop 800121c: 2400059c .word 0x2400059c 8001220: 40010000 .word 0x40010000 8001224: 2400086c .word 0x2400086c 08001228 : * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { 8001228: b5b0 push {r4, r5, r7, lr} 800122a: b08a sub sp, #40 @ 0x28 800122c: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 800122e: f107 031c add.w r3, r7, #28 8001232: 2200 movs r2, #0 8001234: 601a str r2, [r3, #0] 8001236: 605a str r2, [r3, #4] 8001238: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 800123a: 463b mov r3, r7 800123c: 2200 movs r2, #0 800123e: 601a str r2, [r3, #0] 8001240: 605a str r2, [r3, #4] 8001242: 609a str r2, [r3, #8] 8001244: 60da str r2, [r3, #12] 8001246: 611a str r2, [r3, #16] 8001248: 615a str r2, [r3, #20] 800124a: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 800124c: 4b48 ldr r3, [pc, #288] @ (8001370 ) 800124e: 4a49 ldr r2, [pc, #292] @ (8001374 ) 8001250: 601a str r2, [r3, #0] htim3.Init.Prescaler = 199; 8001252: 4b47 ldr r3, [pc, #284] @ (8001370 ) 8001254: 22c7 movs r2, #199 @ 0xc7 8001256: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8001258: 4b45 ldr r3, [pc, #276] @ (8001370 ) 800125a: 2200 movs r2, #0 800125c: 609a str r2, [r3, #8] htim3.Init.Period = 999; 800125e: 4b44 ldr r3, [pc, #272] @ (8001370 ) 8001260: f240 32e7 movw r2, #999 @ 0x3e7 8001264: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8001266: 4b42 ldr r3, [pc, #264] @ (8001370 ) 8001268: 2200 movs r2, #0 800126a: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 800126c: 4b40 ldr r3, [pc, #256] @ (8001370 ) 800126e: 2280 movs r2, #128 @ 0x80 8001270: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 8001272: 483f ldr r0, [pc, #252] @ (8001370 ) 8001274: f00e f846 bl 800f304 8001278: 4603 mov r3, r0 800127a: 2b00 cmp r3, #0 800127c: d001 beq.n 8001282 { Error_Handler(); 800127e: f000 fc85 bl 8001b8c } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001282: 2300 movs r3, #0 8001284: 61fb str r3, [r7, #28] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8001286: 2300 movs r3, #0 8001288: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800128a: f107 031c add.w r3, r7, #28 800128e: 4619 mov r1, r3 8001290: 4837 ldr r0, [pc, #220] @ (8001370 ) 8001292: f00f f9e9 bl 8010668 8001296: 4603 mov r3, r0 8001298: 2b00 cmp r3, #0 800129a: d001 beq.n 80012a0 { Error_Handler(); 800129c: f000 fc76 bl 8001b8c } sConfigOC.OCMode = TIM_OCMODE_COMBINED_PWM1; 80012a0: 4b35 ldr r3, [pc, #212] @ (8001378 ) 80012a2: 603b str r3, [r7, #0] sConfigOC.Pulse = 500; 80012a4: f44f 73fa mov.w r3, #500 @ 0x1f4 80012a8: 607b str r3, [r7, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 80012aa: 2300 movs r3, #0 80012ac: 60bb str r3, [r7, #8] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 80012ae: 2300 movs r3, #0 80012b0: 613b str r3, [r7, #16] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 80012b2: 463b mov r3, r7 80012b4: 2200 movs r2, #0 80012b6: 4619 mov r1, r3 80012b8: 482d ldr r0, [pc, #180] @ (8001370 ) 80012ba: f00e fb27 bl 800f90c 80012be: 4603 mov r3, r0 80012c0: 2b00 cmp r3, #0 80012c2: d001 beq.n 80012c8 { Error_Handler(); 80012c4: f000 fc62 bl 8001b8c } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_1); 80012c8: 4b29 ldr r3, [pc, #164] @ (8001370 ) 80012ca: 681b ldr r3, [r3, #0] 80012cc: 699a ldr r2, [r3, #24] 80012ce: 4b28 ldr r3, [pc, #160] @ (8001370 ) 80012d0: 681b ldr r3, [r3, #0] 80012d2: f022 0208 bic.w r2, r2, #8 80012d6: 619a str r2, [r3, #24] sConfigOC.OCMode = TIM_OCMODE_PWM1; 80012d8: 2360 movs r3, #96 @ 0x60 80012da: 603b str r3, [r7, #0] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 80012dc: 463b mov r3, r7 80012de: 2204 movs r2, #4 80012e0: 4619 mov r1, r3 80012e2: 4823 ldr r0, [pc, #140] @ (8001370 ) 80012e4: f00e fb12 bl 800f90c 80012e8: 4603 mov r3, r0 80012ea: 2b00 cmp r3, #0 80012ec: d001 beq.n 80012f2 { Error_Handler(); 80012ee: f000 fc4d bl 8001b8c } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_2); 80012f2: 4b1f ldr r3, [pc, #124] @ (8001370 ) 80012f4: 681b ldr r3, [r3, #0] 80012f6: 699a ldr r2, [r3, #24] 80012f8: 4b1d ldr r3, [pc, #116] @ (8001370 ) 80012fa: 681b ldr r3, [r3, #0] 80012fc: f422 6200 bic.w r2, r2, #2048 @ 0x800 8001300: 619a str r2, [r3, #24] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 8001302: 463b mov r3, r7 8001304: 2208 movs r2, #8 8001306: 4619 mov r1, r3 8001308: 4819 ldr r0, [pc, #100] @ (8001370 ) 800130a: f00e faff bl 800f90c 800130e: 4603 mov r3, r0 8001310: 2b00 cmp r3, #0 8001312: d001 beq.n 8001318 { Error_Handler(); 8001314: f000 fc3a bl 8001b8c } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_3); 8001318: 4b15 ldr r3, [pc, #84] @ (8001370 ) 800131a: 681b ldr r3, [r3, #0] 800131c: 69da ldr r2, [r3, #28] 800131e: 4b14 ldr r3, [pc, #80] @ (8001370 ) 8001320: 681b ldr r3, [r3, #0] 8001322: f022 0208 bic.w r2, r2, #8 8001326: 61da str r2, [r3, #28] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 8001328: 463b mov r3, r7 800132a: 220c movs r2, #12 800132c: 4619 mov r1, r3 800132e: 4810 ldr r0, [pc, #64] @ (8001370 ) 8001330: f00e faec bl 800f90c 8001334: 4603 mov r3, r0 8001336: 2b00 cmp r3, #0 8001338: d001 beq.n 800133e { Error_Handler(); 800133a: f000 fc27 bl 8001b8c } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_4); 800133e: 4b0c ldr r3, [pc, #48] @ (8001370 ) 8001340: 681b ldr r3, [r3, #0] 8001342: 69da ldr r2, [r3, #28] 8001344: 4b0a ldr r3, [pc, #40] @ (8001370 ) 8001346: 681b ldr r3, [r3, #0] 8001348: f422 6200 bic.w r2, r2, #2048 @ 0x800 800134c: 61da str r2, [r3, #28] /* USER CODE BEGIN TIM3_Init 2 */ memcpy(&motorXYTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 800134e: 4b0b ldr r3, [pc, #44] @ (800137c ) 8001350: 461d mov r5, r3 8001352: 463c mov r4, r7 8001354: cc0f ldmia r4!, {r0, r1, r2, r3} 8001356: c50f stmia r5!, {r0, r1, r2, r3} 8001358: e894 0007 ldmia.w r4, {r0, r1, r2} 800135c: e885 0007 stmia.w r5, {r0, r1, r2} /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 8001360: 4803 ldr r0, [pc, #12] @ (8001370 ) 8001362: f002 fd75 bl 8003e50 } 8001366: bf00 nop 8001368: 3728 adds r7, #40 @ 0x28 800136a: 46bd mov sp, r7 800136c: bdb0 pop {r4, r5, r7, pc} 800136e: bf00 nop 8001370: 240005e8 .word 0x240005e8 8001374: 40000400 .word 0x40000400 8001378: 00010040 .word 0x00010040 800137c: 24000888 .word 0x24000888 08001380 : * @brief TIM8 Initialization Function * @param None * @retval None */ static void MX_TIM8_Init(void) { 8001380: b580 push {r7, lr} 8001382: b088 sub sp, #32 8001384: af00 add r7, sp, #0 /* USER CODE BEGIN TIM8_Init 0 */ /* USER CODE END TIM8_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8001386: f107 0310 add.w r3, r7, #16 800138a: 2200 movs r2, #0 800138c: 601a str r2, [r3, #0] 800138e: 605a str r2, [r3, #4] 8001390: 609a str r2, [r3, #8] 8001392: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001394: 1d3b adds r3, r7, #4 8001396: 2200 movs r2, #0 8001398: 601a str r2, [r3, #0] 800139a: 605a str r2, [r3, #4] 800139c: 609a str r2, [r3, #8] /* USER CODE BEGIN TIM8_Init 1 */ /* USER CODE END TIM8_Init 1 */ htim8.Instance = TIM8; 800139e: 4b20 ldr r3, [pc, #128] @ (8001420 ) 80013a0: 4a20 ldr r2, [pc, #128] @ (8001424 ) 80013a2: 601a str r2, [r3, #0] htim8.Init.Prescaler = 0; 80013a4: 4b1e ldr r3, [pc, #120] @ (8001420 ) 80013a6: 2200 movs r2, #0 80013a8: 605a str r2, [r3, #4] htim8.Init.CounterMode = TIM_COUNTERMODE_UP; 80013aa: 4b1d ldr r3, [pc, #116] @ (8001420 ) 80013ac: 2200 movs r2, #0 80013ae: 609a str r2, [r3, #8] htim8.Init.Period = 1999; 80013b0: 4b1b ldr r3, [pc, #108] @ (8001420 ) 80013b2: f240 72cf movw r2, #1999 @ 0x7cf 80013b6: 60da str r2, [r3, #12] htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80013b8: 4b19 ldr r3, [pc, #100] @ (8001420 ) 80013ba: 2200 movs r2, #0 80013bc: 611a str r2, [r3, #16] htim8.Init.RepetitionCounter = 0; 80013be: 4b18 ldr r3, [pc, #96] @ (8001420 ) 80013c0: 2200 movs r2, #0 80013c2: 615a str r2, [r3, #20] htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 80013c4: 4b16 ldr r3, [pc, #88] @ (8001420 ) 80013c6: 2280 movs r2, #128 @ 0x80 80013c8: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim8) != HAL_OK) 80013ca: 4815 ldr r0, [pc, #84] @ (8001420 ) 80013cc: f00d fe5a bl 800f084 80013d0: 4603 mov r3, r0 80013d2: 2b00 cmp r3, #0 80013d4: d001 beq.n 80013da { Error_Handler(); 80013d6: f000 fbd9 bl 8001b8c } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 80013da: f44f 5380 mov.w r3, #4096 @ 0x1000 80013de: 613b str r3, [r7, #16] if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) 80013e0: f107 0310 add.w r3, r7, #16 80013e4: 4619 mov r1, r3 80013e6: 480e ldr r0, [pc, #56] @ (8001420 ) 80013e8: f00e fba4 bl 800fb34 80013ec: 4603 mov r3, r0 80013ee: 2b00 cmp r3, #0 80013f0: d001 beq.n 80013f6 { Error_Handler(); 80013f2: f000 fbcb bl 8001b8c } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 80013f6: 2320 movs r3, #32 80013f8: 607b str r3, [r7, #4] sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 80013fa: 2300 movs r3, #0 80013fc: 60bb str r3, [r7, #8] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; 80013fe: 2380 movs r3, #128 @ 0x80 8001400: 60fb str r3, [r7, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 8001402: 1d3b adds r3, r7, #4 8001404: 4619 mov r1, r3 8001406: 4806 ldr r0, [pc, #24] @ (8001420 ) 8001408: f00f f92e bl 8010668 800140c: 4603 mov r3, r0 800140e: 2b00 cmp r3, #0 8001410: d001 beq.n 8001416 { Error_Handler(); 8001412: f000 fbbb bl 8001b8c } /* USER CODE BEGIN TIM8_Init 2 */ /* USER CODE END TIM8_Init 2 */ } 8001416: bf00 nop 8001418: 3720 adds r7, #32 800141a: 46bd mov sp, r7 800141c: bd80 pop {r7, pc} 800141e: bf00 nop 8001420: 24000634 .word 0x24000634 8001424: 40010400 .word 0x40010400 08001428 : * @brief UART8 Initialization Function * @param None * @retval None */ static void MX_UART8_Init(void) { 8001428: b580 push {r7, lr} 800142a: af00 add r7, sp, #0 /* USER CODE END UART8_Init 0 */ /* USER CODE BEGIN UART8_Init 1 */ /* USER CODE END UART8_Init 1 */ huart8.Instance = UART8; 800142c: 4b22 ldr r3, [pc, #136] @ (80014b8 ) 800142e: 4a23 ldr r2, [pc, #140] @ (80014bc ) 8001430: 601a str r2, [r3, #0] huart8.Init.BaudRate = 115200; 8001432: 4b21 ldr r3, [pc, #132] @ (80014b8 ) 8001434: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001438: 605a str r2, [r3, #4] huart8.Init.WordLength = UART_WORDLENGTH_8B; 800143a: 4b1f ldr r3, [pc, #124] @ (80014b8 ) 800143c: 2200 movs r2, #0 800143e: 609a str r2, [r3, #8] huart8.Init.StopBits = UART_STOPBITS_1; 8001440: 4b1d ldr r3, [pc, #116] @ (80014b8 ) 8001442: 2200 movs r2, #0 8001444: 60da str r2, [r3, #12] huart8.Init.Parity = UART_PARITY_NONE; 8001446: 4b1c ldr r3, [pc, #112] @ (80014b8 ) 8001448: 2200 movs r2, #0 800144a: 611a str r2, [r3, #16] huart8.Init.Mode = UART_MODE_TX_RX; 800144c: 4b1a ldr r3, [pc, #104] @ (80014b8 ) 800144e: 220c movs r2, #12 8001450: 615a str r2, [r3, #20] huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001452: 4b19 ldr r3, [pc, #100] @ (80014b8 ) 8001454: 2200 movs r2, #0 8001456: 619a str r2, [r3, #24] huart8.Init.OverSampling = UART_OVERSAMPLING_16; 8001458: 4b17 ldr r3, [pc, #92] @ (80014b8 ) 800145a: 2200 movs r2, #0 800145c: 61da str r2, [r3, #28] huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 800145e: 4b16 ldr r3, [pc, #88] @ (80014b8 ) 8001460: 2200 movs r2, #0 8001462: 621a str r2, [r3, #32] huart8.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8001464: 4b14 ldr r3, [pc, #80] @ (80014b8 ) 8001466: 2200 movs r2, #0 8001468: 625a str r2, [r3, #36] @ 0x24 huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 800146a: 4b13 ldr r3, [pc, #76] @ (80014b8 ) 800146c: 2200 movs r2, #0 800146e: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart8) != HAL_OK) 8001470: 4811 ldr r0, [pc, #68] @ (80014b8 ) 8001472: f00f fa23 bl 80108bc 8001476: 4603 mov r3, r0 8001478: 2b00 cmp r3, #0 800147a: d001 beq.n 8001480 { Error_Handler(); 800147c: f000 fb86 bl 8001b8c } if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8001480: 2100 movs r1, #0 8001482: 480d ldr r0, [pc, #52] @ (80014b8 ) 8001484: f011 fec3 bl 801320e 8001488: 4603 mov r3, r0 800148a: 2b00 cmp r3, #0 800148c: d001 beq.n 8001492 { Error_Handler(); 800148e: f000 fb7d bl 8001b8c } if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8001492: 2100 movs r1, #0 8001494: 4808 ldr r0, [pc, #32] @ (80014b8 ) 8001496: f011 fef8 bl 801328a 800149a: 4603 mov r3, r0 800149c: 2b00 cmp r3, #0 800149e: d001 beq.n 80014a4 { Error_Handler(); 80014a0: f000 fb74 bl 8001b8c } if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK) 80014a4: 4804 ldr r0, [pc, #16] @ (80014b8 ) 80014a6: f011 fe79 bl 801319c 80014aa: 4603 mov r3, r0 80014ac: 2b00 cmp r3, #0 80014ae: d001 beq.n 80014b4 { Error_Handler(); 80014b0: f000 fb6c bl 8001b8c } /* USER CODE BEGIN UART8_Init 2 */ /* USER CODE END UART8_Init 2 */ } 80014b4: bf00 nop 80014b6: bd80 pop {r7, pc} 80014b8: 24000680 .word 0x24000680 80014bc: 40007c00 .word 0x40007c00 080014c0 : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 80014c0: b580 push {r7, lr} 80014c2: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 80014c4: 4b24 ldr r3, [pc, #144] @ (8001558 ) 80014c6: 4a25 ldr r2, [pc, #148] @ (800155c ) 80014c8: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 80014ca: 4b23 ldr r3, [pc, #140] @ (8001558 ) 80014cc: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80014d0: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 80014d2: 4b21 ldr r3, [pc, #132] @ (8001558 ) 80014d4: 2200 movs r2, #0 80014d6: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 80014d8: 4b1f ldr r3, [pc, #124] @ (8001558 ) 80014da: 2200 movs r2, #0 80014dc: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 80014de: 4b1e ldr r3, [pc, #120] @ (8001558 ) 80014e0: 2200 movs r2, #0 80014e2: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 80014e4: 4b1c ldr r3, [pc, #112] @ (8001558 ) 80014e6: 220c movs r2, #12 80014e8: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80014ea: 4b1b ldr r3, [pc, #108] @ (8001558 ) 80014ec: 2200 movs r2, #0 80014ee: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 80014f0: 4b19 ldr r3, [pc, #100] @ (8001558 ) 80014f2: 2200 movs r2, #0 80014f4: 61da str r2, [r3, #28] huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 80014f6: 4b18 ldr r3, [pc, #96] @ (8001558 ) 80014f8: 2200 movs r2, #0 80014fa: 621a str r2, [r3, #32] huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 80014fc: 4b16 ldr r3, [pc, #88] @ (8001558 ) 80014fe: 2200 movs r2, #0 8001500: 625a str r2, [r3, #36] @ 0x24 huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_TXINVERT_INIT; 8001502: 4b15 ldr r3, [pc, #84] @ (8001558 ) 8001504: 2201 movs r2, #1 8001506: 629a str r2, [r3, #40] @ 0x28 huart1.AdvancedInit.TxPinLevelInvert = UART_ADVFEATURE_TXINV_ENABLE; 8001508: 4b13 ldr r3, [pc, #76] @ (8001558 ) 800150a: f44f 3200 mov.w r2, #131072 @ 0x20000 800150e: 62da str r2, [r3, #44] @ 0x2c if (HAL_UART_Init(&huart1) != HAL_OK) 8001510: 4811 ldr r0, [pc, #68] @ (8001558 ) 8001512: f00f f9d3 bl 80108bc 8001516: 4603 mov r3, r0 8001518: 2b00 cmp r3, #0 800151a: d001 beq.n 8001520 { Error_Handler(); 800151c: f000 fb36 bl 8001b8c } if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8001520: 2100 movs r1, #0 8001522: 480d ldr r0, [pc, #52] @ (8001558 ) 8001524: f011 fe73 bl 801320e 8001528: 4603 mov r3, r0 800152a: 2b00 cmp r3, #0 800152c: d001 beq.n 8001532 { Error_Handler(); 800152e: f000 fb2d bl 8001b8c } if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8001532: 2100 movs r1, #0 8001534: 4808 ldr r0, [pc, #32] @ (8001558 ) 8001536: f011 fea8 bl 801328a 800153a: 4603 mov r3, r0 800153c: 2b00 cmp r3, #0 800153e: d001 beq.n 8001544 { Error_Handler(); 8001540: f000 fb24 bl 8001b8c } if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) 8001544: 4804 ldr r0, [pc, #16] @ (8001558 ) 8001546: f011 fe29 bl 801319c 800154a: 4603 mov r3, r0 800154c: 2b00 cmp r3, #0 800154e: d001 beq.n 8001554 { Error_Handler(); 8001550: f000 fb1c bl 8001b8c } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8001554: bf00 nop 8001556: bd80 pop {r7, pc} 8001558: 24000714 .word 0x24000714 800155c: 40011000 .word 0x40011000 08001560 : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 8001560: b580 push {r7, lr} 8001562: b082 sub sp, #8 8001564: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 8001566: 4b15 ldr r3, [pc, #84] @ (80015bc ) 8001568: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 800156c: 4a13 ldr r2, [pc, #76] @ (80015bc ) 800156e: f043 0301 orr.w r3, r3, #1 8001572: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8001576: 4b11 ldr r3, [pc, #68] @ (80015bc ) 8001578: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 800157c: f003 0301 and.w r3, r3, #1 8001580: 607b str r3, [r7, #4] 8001582: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0); 8001584: 2200 movs r2, #0 8001586: 2105 movs r1, #5 8001588: 200b movs r0, #11 800158a: f006 f91f bl 80077cc HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 800158e: 200b movs r0, #11 8001590: f006 f936 bl 8007800 /* DMA1_Stream1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0); 8001594: 2200 movs r2, #0 8001596: 2105 movs r1, #5 8001598: 200c movs r0, #12 800159a: f006 f917 bl 80077cc HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn); 800159e: 200c movs r0, #12 80015a0: f006 f92e bl 8007800 /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0); 80015a4: 2200 movs r2, #0 80015a6: 2105 movs r1, #5 80015a8: 200d movs r0, #13 80015aa: f006 f90f bl 80077cc HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 80015ae: 200d movs r0, #13 80015b0: f006 f926 bl 8007800 } 80015b4: bf00 nop 80015b6: 3708 adds r7, #8 80015b8: 46bd mov sp, r7 80015ba: bd80 pop {r7, pc} 80015bc: 58024400 .word 0x58024400 080015c0 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80015c0: b580 push {r7, lr} 80015c2: b08c sub sp, #48 @ 0x30 80015c4: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80015c6: f107 031c add.w r3, r7, #28 80015ca: 2200 movs r2, #0 80015cc: 601a str r2, [r3, #0] 80015ce: 605a str r2, [r3, #4] 80015d0: 609a str r2, [r3, #8] 80015d2: 60da str r2, [r3, #12] 80015d4: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 80015d6: 4b5b ldr r3, [pc, #364] @ (8001744 ) 80015d8: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80015dc: 4a59 ldr r2, [pc, #356] @ (8001744 ) 80015de: f043 0380 orr.w r3, r3, #128 @ 0x80 80015e2: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80015e6: 4b57 ldr r3, [pc, #348] @ (8001744 ) 80015e8: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80015ec: f003 0380 and.w r3, r3, #128 @ 0x80 80015f0: 61bb str r3, [r7, #24] 80015f2: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOC_CLK_ENABLE(); 80015f4: 4b53 ldr r3, [pc, #332] @ (8001744 ) 80015f6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80015fa: 4a52 ldr r2, [pc, #328] @ (8001744 ) 80015fc: f043 0304 orr.w r3, r3, #4 8001600: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001604: 4b4f ldr r3, [pc, #316] @ (8001744 ) 8001606: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800160a: f003 0304 and.w r3, r3, #4 800160e: 617b str r3, [r7, #20] 8001610: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001612: 4b4c ldr r3, [pc, #304] @ (8001744 ) 8001614: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001618: 4a4a ldr r2, [pc, #296] @ (8001744 ) 800161a: f043 0301 orr.w r3, r3, #1 800161e: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001622: 4b48 ldr r3, [pc, #288] @ (8001744 ) 8001624: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001628: f003 0301 and.w r3, r3, #1 800162c: 613b str r3, [r7, #16] 800162e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001630: 4b44 ldr r3, [pc, #272] @ (8001744 ) 8001632: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001636: 4a43 ldr r2, [pc, #268] @ (8001744 ) 8001638: f043 0302 orr.w r3, r3, #2 800163c: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001640: 4b40 ldr r3, [pc, #256] @ (8001744 ) 8001642: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001646: f003 0302 and.w r3, r3, #2 800164a: 60fb str r3, [r7, #12] 800164c: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 800164e: 4b3d ldr r3, [pc, #244] @ (8001744 ) 8001650: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001654: 4a3b ldr r2, [pc, #236] @ (8001744 ) 8001656: f043 0310 orr.w r3, r3, #16 800165a: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800165e: 4b39 ldr r3, [pc, #228] @ (8001744 ) 8001660: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001664: f003 0310 and.w r3, r3, #16 8001668: 60bb str r3, [r7, #8] 800166a: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 800166c: 4b35 ldr r3, [pc, #212] @ (8001744 ) 800166e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001672: 4a34 ldr r2, [pc, #208] @ (8001744 ) 8001674: f043 0308 orr.w r3, r3, #8 8001678: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800167c: 4b31 ldr r3, [pc, #196] @ (8001744 ) 800167e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001682: f003 0308 and.w r3, r3, #8 8001686: 607b str r3, [r7, #4] 8001688: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 800168a: 2200 movs r2, #0 800168c: f24e 7180 movw r1, #59264 @ 0xe780 8001690: 482d ldr r0, [pc, #180] @ (8001748 ) 8001692: f009 fd95 bl 800b1c0 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET); 8001696: 2200 movs r2, #0 8001698: 21f0 movs r1, #240 @ 0xf0 800169a: 482c ldr r0, [pc, #176] @ (800174c ) 800169c: f009 fd90 bl 800b1c0 /*Configure GPIO pins : PE7 PE8 PE9 PE10 PE13 PE14 PE15 */ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 80016a0: f24e 7380 movw r3, #59264 @ 0xe780 80016a4: 61fb str r3, [r7, #28] |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80016a6: 2301 movs r3, #1 80016a8: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 80016aa: 2300 movs r3, #0 80016ac: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80016ae: 2300 movs r3, #0 80016b0: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 80016b2: f107 031c add.w r3, r7, #28 80016b6: 4619 mov r1, r3 80016b8: 4823 ldr r0, [pc, #140] @ (8001748 ) 80016ba: f009 fbb9 bl 800ae30 /*Configure GPIO pins : PB10 PB11 */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; 80016be: f44f 6340 mov.w r3, #3072 @ 0xc00 80016c2: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 80016c4: f44f 1344 mov.w r3, #3211264 @ 0x310000 80016c8: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 80016ca: 2300 movs r3, #0 80016cc: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80016ce: f107 031c add.w r3, r7, #28 80016d2: 4619 mov r1, r3 80016d4: 481e ldr r0, [pc, #120] @ (8001750 ) 80016d6: f009 fbab bl 800ae30 /*Configure GPIO pins : PD8 PD9 PD10 PD11 PD12 PD13 PD3 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 80016da: f643 7308 movw r3, #16136 @ 0x3f08 80016de: 61fb str r3, [r7, #28] |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80016e0: 2300 movs r3, #0 80016e2: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 80016e4: 2300 movs r3, #0 80016e6: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80016e8: f107 031c add.w r3, r7, #28 80016ec: 4619 mov r1, r3 80016ee: 4817 ldr r0, [pc, #92] @ (800174c ) 80016f0: f009 fb9e bl 800ae30 /*Configure GPIO pins : PD14 PD15 */ GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 80016f4: f44f 4340 mov.w r3, #49152 @ 0xc000 80016f8: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 80016fa: f44f 1344 mov.w r3, #3211264 @ 0x310000 80016fe: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001700: 2300 movs r3, #0 8001702: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001704: f107 031c add.w r3, r7, #28 8001708: 4619 mov r1, r3 800170a: 4810 ldr r0, [pc, #64] @ (800174c ) 800170c: f009 fb90 bl 800ae30 /*Configure GPIO pins : PD4 PD5 PD6 PD7 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; 8001710: 23f0 movs r3, #240 @ 0xf0 8001712: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001714: 2301 movs r3, #1 8001716: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001718: 2300 movs r3, #0 800171a: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800171c: 2300 movs r3, #0 800171e: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001720: f107 031c add.w r3, r7, #28 8001724: 4619 mov r1, r3 8001726: 4809 ldr r0, [pc, #36] @ (800174c ) 8001728: f009 fb82 bl 800ae30 /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0); 800172c: 2200 movs r2, #0 800172e: 2105 movs r1, #5 8001730: 2028 movs r0, #40 @ 0x28 8001732: f006 f84b bl 80077cc HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); 8001736: 2028 movs r0, #40 @ 0x28 8001738: f006 f862 bl 8007800 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 800173c: bf00 nop 800173e: 3730 adds r7, #48 @ 0x30 8001740: 46bd mov sp, r7 8001742: bd80 pop {r7, pc} 8001744: 58024400 .word 0x58024400 8001748: 58021000 .word 0x58021000 800174c: 58020c00 .word 0x58020c00 8001750: 58020400 .word 0x58020400 08001754 : /* USER CODE BEGIN 4 */ void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { 8001754: b580 push {r7, lr} 8001756: b08a sub sp, #40 @ 0x28 8001758: af00 add r7, sp, #0 800175a: 6078 str r0, [r7, #4] if(hadc->Instance == ADC1) 800175c: 687b ldr r3, [r7, #4] 800175e: 681b ldr r3, [r3, #0] 8001760: 4a46 ldr r2, [pc, #280] @ (800187c ) 8001762: 4293 cmp r3, r2 8001764: d13f bne.n 80017e6 { DbgLEDToggle(DBG_LED4); 8001766: 2080 movs r0, #128 @ 0x80 8001768: f001 f98a bl 8002a80 SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc1Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 800176c: 4b44 ldr r3, [pc, #272] @ (8001880 ) 800176e: f023 031f bic.w r3, r3, #31 8001772: 627b str r3, [r7, #36] @ 0x24 8001774: 2320 movs r3, #32 8001776: 623b str r3, [r7, #32] if ( dsize > 0 ) { 8001778: 6a3b ldr r3, [r7, #32] 800177a: 2b00 cmp r3, #0 800177c: dd1d ble.n 80017ba int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 800177e: 6a7b ldr r3, [r7, #36] @ 0x24 8001780: f003 021f and.w r2, r3, #31 8001784: 6a3b ldr r3, [r7, #32] 8001786: 4413 add r3, r2 8001788: 61fb str r3, [r7, #28] uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 800178a: 6a7b ldr r3, [r7, #36] @ 0x24 800178c: 61bb str r3, [r7, #24] __ASM volatile ("dsb 0xF":::"memory"); 800178e: f3bf 8f4f dsb sy } 8001792: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 8001794: 4a3b ldr r2, [pc, #236] @ (8001884 ) 8001796: 69bb ldr r3, [r7, #24] 8001798: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 800179c: 69bb ldr r3, [r7, #24] 800179e: 3320 adds r3, #32 80017a0: 61bb str r3, [r7, #24] op_size -= __SCB_DCACHE_LINE_SIZE; 80017a2: 69fb ldr r3, [r7, #28] 80017a4: 3b20 subs r3, #32 80017a6: 61fb str r3, [r7, #28] } while ( op_size > 0 ); 80017a8: 69fb ldr r3, [r7, #28] 80017aa: 2b00 cmp r3, #0 80017ac: dcf2 bgt.n 8001794 __ASM volatile ("dsb 0xF":::"memory"); 80017ae: f3bf 8f4f dsb sy } 80017b2: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80017b4: f3bf 8f6f isb sy } 80017b8: bf00 nop } 80017ba: bf00 nop if(adc1MeasDataQueue != NULL) 80017bc: 4b32 ldr r3, [pc, #200] @ (8001888 ) 80017be: 681b ldr r3, [r3, #0] 80017c0: 2b00 cmp r3, #0 80017c2: d006 beq.n 80017d2 { osMessageQueuePut(adc1MeasDataQueue, &adc1Data, 0, 0); 80017c4: 4b30 ldr r3, [pc, #192] @ (8001888 ) 80017c6: 6818 ldr r0, [r3, #0] 80017c8: 2300 movs r3, #0 80017ca: 2200 movs r2, #0 80017cc: 492c ldr r1, [pc, #176] @ (8001880 ) 80017ce: f012 f9ed bl 8013bac } if(HAL_ADCEx_MultiModeStart_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData*sizeof(uint32_t)) != HAL_OK) 80017d2: 221c movs r2, #28 80017d4: 492a ldr r1, [pc, #168] @ (8001880 ) 80017d6: 482d ldr r0, [pc, #180] @ (800188c ) 80017d8: f005 fbf2 bl 8006fc0 80017dc: 4603 mov r3, r0 80017de: 2b00 cmp r3, #0 80017e0: d001 beq.n 80017e6 { Error_Handler(); 80017e2: f000 f9d3 bl 8001b8c } } if(hadc->Instance == ADC3) 80017e6: 687b ldr r3, [r7, #4] 80017e8: 681b ldr r3, [r3, #0] 80017ea: 4a29 ldr r2, [pc, #164] @ (8001890 ) 80017ec: 4293 cmp r3, r2 80017ee: d13c bne.n 800186a { SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc3Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 80017f0: 4b28 ldr r3, [pc, #160] @ (8001894 ) 80017f2: f023 031f bic.w r3, r3, #31 80017f6: 617b str r3, [r7, #20] 80017f8: 2320 movs r3, #32 80017fa: 613b str r3, [r7, #16] if ( dsize > 0 ) { 80017fc: 693b ldr r3, [r7, #16] 80017fe: 2b00 cmp r3, #0 8001800: dd1d ble.n 800183e int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 8001802: 697b ldr r3, [r7, #20] 8001804: f003 021f and.w r2, r3, #31 8001808: 693b ldr r3, [r7, #16] 800180a: 4413 add r3, r2 800180c: 60fb str r3, [r7, #12] uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 800180e: 697b ldr r3, [r7, #20] 8001810: 60bb str r3, [r7, #8] __ASM volatile ("dsb 0xF":::"memory"); 8001812: f3bf 8f4f dsb sy } 8001816: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 8001818: 4a1a ldr r2, [pc, #104] @ (8001884 ) 800181a: 68bb ldr r3, [r7, #8] 800181c: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 8001820: 68bb ldr r3, [r7, #8] 8001822: 3320 adds r3, #32 8001824: 60bb str r3, [r7, #8] op_size -= __SCB_DCACHE_LINE_SIZE; 8001826: 68fb ldr r3, [r7, #12] 8001828: 3b20 subs r3, #32 800182a: 60fb str r3, [r7, #12] } while ( op_size > 0 ); 800182c: 68fb ldr r3, [r7, #12] 800182e: 2b00 cmp r3, #0 8001830: dcf2 bgt.n 8001818 __ASM volatile ("dsb 0xF":::"memory"); 8001832: f3bf 8f4f dsb sy } 8001836: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8001838: f3bf 8f6f isb sy } 800183c: bf00 nop } 800183e: bf00 nop if(adc3MeasDataQueue != NULL) 8001840: 4b15 ldr r3, [pc, #84] @ (8001898 ) 8001842: 681b ldr r3, [r3, #0] 8001844: 2b00 cmp r3, #0 8001846: d006 beq.n 8001856 { osMessageQueuePut(adc3MeasDataQueue, &adc3Data, 0, 0); 8001848: 4b13 ldr r3, [pc, #76] @ (8001898 ) 800184a: 6818 ldr r0, [r3, #0] 800184c: 2300 movs r3, #0 800184e: 2200 movs r2, #0 8001850: 4910 ldr r1, [pc, #64] @ (8001894 ) 8001852: f012 f9ab bl 8013bac } if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData*sizeof(uint16_t)) != HAL_OK) 8001856: 220a movs r2, #10 8001858: 490e ldr r1, [pc, #56] @ (8001894 ) 800185a: 4810 ldr r0, [pc, #64] @ (800189c ) 800185c: f004 fc20 bl 80060a0 8001860: 4603 mov r3, r0 8001862: 2b00 cmp r3, #0 8001864: d001 beq.n 800186a { Error_Handler(); 8001866: f000 f991 bl 8001b8c } } osTimerStop (debugLedTimerHandle); 800186a: 4b0d ldr r3, [pc, #52] @ (80018a0 ) 800186c: 681b ldr r3, [r3, #0] 800186e: 4618 mov r0, r3 8001870: f011 ffe4 bl 801383c } 8001874: bf00 nop 8001876: 3728 adds r7, #40 @ 0x28 8001878: 46bd mov sp, r7 800187a: bd80 pop {r7, pc} 800187c: 40022000 .word 0x40022000 8001880: 24000240 .word 0x24000240 8001884: e000ed00 .word 0xe000ed00 8001888: 240008c8 .word 0x240008c8 800188c: 24000280 .word 0x24000280 8001890: 58026000 .word 0x58026000 8001894: 24000260 .word 0x24000260 8001898: 240008d0 .word 0x240008d0 800189c: 24000348 .word 0x24000348 80018a0: 240007ac .word 0x240007ac 080018a4 : * @param argument: Not used * @retval None */ /* USER CODE END Header_StartDefaultTask */ void StartDefaultTask(void *argument) { 80018a4: b580 push {r7, lr} 80018a6: b082 sub sp, #8 80018a8: af00 add r7, sp, #0 80018aa: 6078 str r0, [r7, #4] /* USER CODE BEGIN 5 */ #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 80018ac: 483f ldr r0, [pc, #252] @ (80019ac ) 80018ae: f009 fd23 bl 800b2f8 #endif SelectCurrentSensorGain(CurrentSensorL1, csGain3); 80018b2: 2102 movs r1, #2 80018b4: 2000 movs r0, #0 80018b6: f001 f901 bl 8002abc SelectCurrentSensorGain(CurrentSensorL2, csGain3); 80018ba: 2102 movs r1, #2 80018bc: 2001 movs r0, #1 80018be: f001 f8fd bl 8002abc SelectCurrentSensorGain(CurrentSensorL3, csGain3); 80018c2: 2102 movs r1, #2 80018c4: 2002 movs r0, #2 80018c6: f001 f8f9 bl 8002abc EnableCurrentSensors(); 80018ca: f001 f8eb bl 8002aa4 osDelay(pdMS_TO_TICKS(100)); 80018ce: 2064 movs r0, #100 @ 0x64 80018d0: f011 fed9 bl 8013686 #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 80018d4: 4835 ldr r0, [pc, #212] @ (80019ac ) 80018d6: f009 fd0f bl 800b2f8 #endif if(HAL_TIM_Base_Start(&htim8) != HAL_OK) 80018da: 4835 ldr r0, [pc, #212] @ (80019b0 ) 80018dc: f00d fc2a bl 800f134 80018e0: 4603 mov r3, r0 80018e2: 2b00 cmp r3, #0 80018e4: d001 beq.n 80018ea { Error_Handler(); 80018e6: f000 f951 bl 8001b8c } if(HAL_ADCEx_MultiModeStart_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData*sizeof(uint32_t)) != HAL_OK) 80018ea: 221c movs r2, #28 80018ec: 4931 ldr r1, [pc, #196] @ (80019b4 ) 80018ee: 4832 ldr r0, [pc, #200] @ (80019b8 ) 80018f0: f005 fb66 bl 8006fc0 80018f4: 4603 mov r3, r0 80018f6: 2b00 cmp r3, #0 80018f8: d001 beq.n 80018fe { Error_Handler(); 80018fa: f000 f947 bl 8001b8c } if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData*sizeof(uint16_t)) != HAL_OK) 80018fe: 220a movs r2, #10 8001900: 492e ldr r1, [pc, #184] @ (80019bc ) 8001902: 482f ldr r0, [pc, #188] @ (80019c0 ) 8001904: f004 fbcc bl 80060a0 8001908: 4603 mov r3, r0 800190a: 2b00 cmp r3, #0 800190c: d001 beq.n 8001912 { Error_Handler(); 800190e: f000 f93d bl 8001b8c } HAL_COMP_Start(&hcomp1); 8001912: 482c ldr r0, [pc, #176] @ (80019c4 ) 8001914: f005 fe3a bl 800758c #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001918: 4824 ldr r0, [pc, #144] @ (80019ac ) 800191a: f009 fced bl 800b2f8 #endif /* Infinite loop */ for(;;) { osDelay(pdMS_TO_TICKS(100)); 800191e: 2064 movs r0, #100 @ 0x64 8001920: f011 feb1 bl 8013686 #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001924: 4821 ldr r0, [pc, #132] @ (80019ac ) 8001926: f009 fce7 bl 800b2f8 #endif if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 800192a: 2100 movs r1, #0 800192c: 4826 ldr r0, [pc, #152] @ (80019c8 ) 800192e: f00e fa21 bl 800fd74 8001932: 4603 mov r3, r0 8001934: 2b01 cmp r3, #1 8001936: d118 bne.n 800196a HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_2) == HAL_TIM_CHANNEL_STATE_READY) 8001938: 2104 movs r1, #4 800193a: 4823 ldr r0, [pc, #140] @ (80019c8 ) 800193c: f00e fa1a bl 800fd74 8001940: 4603 mov r3, r0 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 8001942: 2b01 cmp r3, #1 8001944: d111 bne.n 800196a { if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 8001946: 4b21 ldr r3, [pc, #132] @ (80019cc ) 8001948: 681b ldr r3, [r3, #0] 800194a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800194e: 4618 mov r0, r3 8001950: f012 f831 bl 80139b6 8001954: 4603 mov r3, r0 8001956: 2b00 cmp r3, #0 8001958: d107 bne.n 800196a { sensorsInfo.motorXStatus = 0; 800195a: 4b1d ldr r3, [pc, #116] @ (80019d0 ) 800195c: 2200 movs r2, #0 800195e: 751a strb r2, [r3, #20] osMutexRelease(sensorsInfoMutex); 8001960: 4b1a ldr r3, [pc, #104] @ (80019cc ) 8001962: 681b ldr r3, [r3, #0] 8001964: 4618 mov r0, r3 8001966: f012 f871 bl 8013a4c } } if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 800196a: 2108 movs r1, #8 800196c: 4816 ldr r0, [pc, #88] @ (80019c8 ) 800196e: f00e fa01 bl 800fd74 8001972: 4603 mov r3, r0 8001974: 2b01 cmp r3, #1 8001976: d1d2 bne.n 800191e HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_4) == HAL_TIM_CHANNEL_STATE_READY) 8001978: 210c movs r1, #12 800197a: 4813 ldr r0, [pc, #76] @ (80019c8 ) 800197c: f00e f9fa bl 800fd74 8001980: 4603 mov r3, r0 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 8001982: 2b01 cmp r3, #1 8001984: d1cb bne.n 800191e { if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 8001986: 4b11 ldr r3, [pc, #68] @ (80019cc ) 8001988: 681b ldr r3, [r3, #0] 800198a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800198e: 4618 mov r0, r3 8001990: f012 f811 bl 80139b6 8001994: 4603 mov r3, r0 8001996: 2b00 cmp r3, #0 8001998: d1c1 bne.n 800191e { sensorsInfo.motorYStatus = 0; 800199a: 4b0d ldr r3, [pc, #52] @ (80019d0 ) 800199c: 2200 movs r2, #0 800199e: 755a strb r2, [r3, #21] osMutexRelease(sensorsInfoMutex); 80019a0: 4b0a ldr r3, [pc, #40] @ (80019cc ) 80019a2: 681b ldr r3, [r3, #0] 80019a4: 4618 mov r0, r3 80019a6: f012 f851 bl 8013a4c osDelay(pdMS_TO_TICKS(100)); 80019aa: e7b8 b.n 800191e 80019ac: 24000578 .word 0x24000578 80019b0: 24000634 .word 0x24000634 80019b4: 24000240 .word 0x24000240 80019b8: 24000280 .word 0x24000280 80019bc: 24000260 .word 0x24000260 80019c0: 24000348 .word 0x24000348 80019c4: 24000514 .word 0x24000514 80019c8: 240005e8 .word 0x240005e8 80019cc: 240008dc .word 0x240008dc 80019d0: 24000940 .word 0x24000940 080019d4 : /* USER CODE END 5 */ } /* debugLedTimerCallback function */ void debugLedTimerCallback(void *argument) { 80019d4: b580 push {r7, lr} 80019d6: b082 sub sp, #8 80019d8: af00 add r7, sp, #0 80019da: 6078 str r0, [r7, #4] /* USER CODE BEGIN debugLedTimerCallback */ DbgLEDOff (DBG_LED1); 80019dc: 2010 movs r0, #16 80019de: f001 f83d bl 8002a5c /* USER CODE END debugLedTimerCallback */ } 80019e2: bf00 nop 80019e4: 3708 adds r7, #8 80019e6: 46bd mov sp, r7 80019e8: bd80 pop {r7, pc} ... 080019ec : /* fanTimerCallback function */ void fanTimerCallback(void *argument) { 80019ec: b580 push {r7, lr} 80019ee: b082 sub sp, #8 80019f0: af00 add r7, sp, #0 80019f2: 6078 str r0, [r7, #4] /* USER CODE BEGIN fanTimerCallback */ HAL_TIM_PWM_Stop(&htim1, TIM_CHANNEL_2); 80019f4: 2104 movs r1, #4 80019f6: 4803 ldr r0, [pc, #12] @ (8001a04 ) 80019f8: f00d fdea bl 800f5d0 /* USER CODE END fanTimerCallback */ } 80019fc: bf00 nop 80019fe: 3708 adds r7, #8 8001a00: 46bd mov sp, r7 8001a02: bd80 pop {r7, pc} 8001a04: 2400059c .word 0x2400059c 08001a08 : /* motorXTimerCallback function */ void motorXTimerCallback(void *argument) { 8001a08: b580 push {r7, lr} 8001a0a: b084 sub sp, #16 8001a0c: af02 add r7, sp, #8 8001a0e: 6078 str r0, [r7, #4] /* USER CODE BEGIN motorXTimerCallback */ MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, HiZ, 0); 8001a10: 2300 movs r3, #0 8001a12: 9301 str r3, [sp, #4] 8001a14: 2300 movs r3, #0 8001a16: 9300 str r3, [sp, #0] 8001a18: 2304 movs r3, #4 8001a1a: 2200 movs r2, #0 8001a1c: 4907 ldr r1, [pc, #28] @ (8001a3c ) 8001a1e: 4808 ldr r0, [pc, #32] @ (8001a40 ) 8001a20: f001 f9d1 bl 8002dc6 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_1); 8001a24: 2100 movs r1, #0 8001a26: 4806 ldr r0, [pc, #24] @ (8001a40 ) 8001a28: f00d fdd2 bl 800f5d0 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_2); 8001a2c: 2104 movs r1, #4 8001a2e: 4804 ldr r0, [pc, #16] @ (8001a40 ) 8001a30: f00d fdce bl 800f5d0 /* USER CODE END motorXTimerCallback */ } 8001a34: bf00 nop 8001a36: 3708 adds r7, #8 8001a38: 46bd mov sp, r7 8001a3a: bd80 pop {r7, pc} 8001a3c: 24000888 .word 0x24000888 8001a40: 240005e8 .word 0x240005e8 08001a44 : /* motorYTimerCallback function */ void motorYTimerCallback(void *argument) { 8001a44: b580 push {r7, lr} 8001a46: b084 sub sp, #16 8001a48: af02 add r7, sp, #8 8001a4a: 6078 str r0, [r7, #4] /* USER CODE BEGIN motorYTimerCallback */ MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, HiZ, 0); 8001a4c: 2300 movs r3, #0 8001a4e: 9301 str r3, [sp, #4] 8001a50: 2300 movs r3, #0 8001a52: 9300 str r3, [sp, #0] 8001a54: 230c movs r3, #12 8001a56: 2208 movs r2, #8 8001a58: 4907 ldr r1, [pc, #28] @ (8001a78 ) 8001a5a: 4808 ldr r0, [pc, #32] @ (8001a7c ) 8001a5c: f001 f9b3 bl 8002dc6 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_3); 8001a60: 2108 movs r1, #8 8001a62: 4806 ldr r0, [pc, #24] @ (8001a7c ) 8001a64: f00d fdb4 bl 800f5d0 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_4); 8001a68: 210c movs r1, #12 8001a6a: 4804 ldr r0, [pc, #16] @ (8001a7c ) 8001a6c: f00d fdb0 bl 800f5d0 /* USER CODE END motorYTimerCallback */ } 8001a70: bf00 nop 8001a72: 3708 adds r7, #8 8001a74: 46bd mov sp, r7 8001a76: bd80 pop {r7, pc} 8001a78: 24000888 .word 0x24000888 8001a7c: 240005e8 .word 0x240005e8 08001a80 : /* MPU Configuration */ void MPU_Config(void) { 8001a80: b580 push {r7, lr} 8001a82: b084 sub sp, #16 8001a84: af00 add r7, sp, #0 MPU_Region_InitTypeDef MPU_InitStruct = {0}; 8001a86: 463b mov r3, r7 8001a88: 2200 movs r2, #0 8001a8a: 601a str r2, [r3, #0] 8001a8c: 605a str r2, [r3, #4] 8001a8e: 609a str r2, [r3, #8] 8001a90: 60da str r2, [r3, #12] /* Disables the MPU */ HAL_MPU_Disable(); 8001a92: f005 fec3 bl 800781c /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; 8001a96: 2301 movs r3, #1 8001a98: 703b strb r3, [r7, #0] MPU_InitStruct.Number = MPU_REGION_NUMBER0; 8001a9a: 2300 movs r3, #0 8001a9c: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x0; 8001a9e: 2300 movs r3, #0 8001aa0: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; 8001aa2: 231f movs r3, #31 8001aa4: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x87; 8001aa6: 2387 movs r3, #135 @ 0x87 8001aa8: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8001aaa: 2300 movs r3, #0 8001aac: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; 8001aae: 2300 movs r3, #0 8001ab0: 72fb strb r3, [r7, #11] MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; 8001ab2: 2301 movs r3, #1 8001ab4: 733b strb r3, [r7, #12] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8001ab6: 2301 movs r3, #1 8001ab8: 737b strb r3, [r7, #13] MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; 8001aba: 2300 movs r3, #0 8001abc: 73bb strb r3, [r7, #14] MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; 8001abe: 2300 movs r3, #0 8001ac0: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001ac2: 463b mov r3, r7 8001ac4: 4618 mov r0, r3 8001ac6: f005 fee1 bl 800788c /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER1; 8001aca: 2301 movs r3, #1 8001acc: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24020000; 8001ace: 4b13 ldr r3, [pc, #76] @ (8001b1c ) 8001ad0: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_128KB; 8001ad2: 2310 movs r3, #16 8001ad4: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x0; 8001ad6: 2300 movs r3, #0 8001ad8: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; 8001ada: 2301 movs r3, #1 8001adc: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; 8001ade: 2303 movs r3, #3 8001ae0: 72fb strb r3, [r7, #11] MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 8001ae2: 2300 movs r3, #0 8001ae4: 737b strb r3, [r7, #13] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001ae6: 463b mov r3, r7 8001ae8: 4618 mov r0, r3 8001aea: f005 fecf bl 800788c /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER2; 8001aee: 2302 movs r3, #2 8001af0: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24040000; 8001af2: 4b0b ldr r3, [pc, #44] @ (8001b20 ) 8001af4: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_512B; 8001af6: 2308 movs r3, #8 8001af8: 723b strb r3, [r7, #8] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8001afa: 2300 movs r3, #0 8001afc: 72bb strb r3, [r7, #10] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8001afe: 2301 movs r3, #1 8001b00: 737b strb r3, [r7, #13] MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; 8001b02: 2301 movs r3, #1 8001b04: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001b06: 463b mov r3, r7 8001b08: 4618 mov r0, r3 8001b0a: f005 febf bl 800788c /* Enables the MPU */ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); 8001b0e: 2004 movs r0, #4 8001b10: f005 fe9c bl 800784c } 8001b14: bf00 nop 8001b16: 3710 adds r7, #16 8001b18: 46bd mov sp, r7 8001b1a: bd80 pop {r7, pc} 8001b1c: 24020000 .word 0x24020000 8001b20: 24040000 .word 0x24040000 08001b24 : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8001b24: b580 push {r7, lr} 8001b26: b082 sub sp, #8 8001b28: af00 add r7, sp, #0 8001b2a: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM6) { 8001b2c: 687b ldr r3, [r7, #4] 8001b2e: 681b ldr r3, [r3, #0] 8001b30: 4a10 ldr r2, [pc, #64] @ (8001b74 ) 8001b32: 4293 cmp r3, r2 8001b34: d102 bne.n 8001b3c HAL_IncTick(); 8001b36: f003 fe9d bl 8005874 { encoderYChannelA = 0; encoderYChannelB = 0; } /* USER CODE END Callback 1 */ } 8001b3a: e016 b.n 8001b6a else if (htim->Instance == TIM4) 8001b3c: 687b ldr r3, [r7, #4] 8001b3e: 681b ldr r3, [r3, #0] 8001b40: 4a0d ldr r2, [pc, #52] @ (8001b78 ) 8001b42: 4293 cmp r3, r2 8001b44: d106 bne.n 8001b54 encoderXChannelA = 0; 8001b46: 4b0d ldr r3, [pc, #52] @ (8001b7c ) 8001b48: 2200 movs r2, #0 8001b4a: 601a str r2, [r3, #0] encoderXChannelB = 0; 8001b4c: 4b0c ldr r3, [pc, #48] @ (8001b80 ) 8001b4e: 2200 movs r2, #0 8001b50: 601a str r2, [r3, #0] } 8001b52: e00a b.n 8001b6a else if (htim->Instance == TIM2) 8001b54: 687b ldr r3, [r7, #4] 8001b56: 681b ldr r3, [r3, #0] 8001b58: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001b5c: d105 bne.n 8001b6a encoderYChannelA = 0; 8001b5e: 4b09 ldr r3, [pc, #36] @ (8001b84 ) 8001b60: 2200 movs r2, #0 8001b62: 601a str r2, [r3, #0] encoderYChannelB = 0; 8001b64: 4b08 ldr r3, [pc, #32] @ (8001b88 ) 8001b66: 2200 movs r2, #0 8001b68: 601a str r2, [r3, #0] } 8001b6a: bf00 nop 8001b6c: 3708 adds r7, #8 8001b6e: 46bd mov sp, r7 8001b70: bd80 pop {r7, pc} 8001b72: bf00 nop 8001b74: 40001000 .word 0x40001000 8001b78: 40000800 .word 0x40000800 8001b7c: 240008a4 .word 0x240008a4 8001b80: 240008a8 .word 0x240008a8 8001b84: 240008ac .word 0x240008ac 8001b88: 240008b0 .word 0x240008b0 08001b8c : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001b8c: b580 push {r7, lr} 8001b8e: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 8001b90: b672 cpsid i } 8001b92: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); NVIC_SystemReset(); 8001b94: f7fe fd80 bl 8000698 <__NVIC_SystemReset> 08001b98 : arg = delta*i + phase; outBuff[i] = amplitude * arm_sin_f32(arg); } } void MeasTasksInit (void) { 8001b98: b590 push {r4, r7, lr} 8001b9a: b0ab sub sp, #172 @ 0xac 8001b9c: af00 add r7, sp, #0 vRefmVMutex = osMutexNew (NULL); 8001b9e: 2000 movs r0, #0 8001ba0: f011 fe83 bl 80138aa 8001ba4: 4603 mov r3, r0 8001ba6: 4a72 ldr r2, [pc, #456] @ (8001d70 ) 8001ba8: 6013 str r3, [r2, #0] resMeasurementsMutex = osMutexNew (NULL); 8001baa: 2000 movs r0, #0 8001bac: f011 fe7d bl 80138aa 8001bb0: 4603 mov r3, r0 8001bb2: 4a70 ldr r2, [pc, #448] @ (8001d74 ) 8001bb4: 6013 str r3, [r2, #0] sensorsInfoMutex = osMutexNew (NULL); 8001bb6: 2000 movs r0, #0 8001bb8: f011 fe77 bl 80138aa 8001bbc: 4603 mov r3, r0 8001bbe: 4a6e ldr r2, [pc, #440] @ (8001d78 ) 8001bc0: 6013 str r3, [r2, #0] ILxRefMutex = osMutexNew (NULL); 8001bc2: 2000 movs r0, #0 8001bc4: f011 fe71 bl 80138aa 8001bc8: 4603 mov r3, r0 8001bca: 4a6c ldr r2, [pc, #432] @ (8001d7c ) 8001bcc: 6013 str r3, [r2, #0] adc1MeasDataQueue = osMessageQueueNew (8, sizeof (ADC1_Data), NULL); 8001bce: 2200 movs r2, #0 8001bd0: 2120 movs r1, #32 8001bd2: 2008 movs r0, #8 8001bd4: f011 ff77 bl 8013ac6 8001bd8: 4603 mov r3, r0 8001bda: 4a69 ldr r2, [pc, #420] @ (8001d80 ) 8001bdc: 6013 str r3, [r2, #0] adc2MeasDataQueue = osMessageQueueNew (8, sizeof (ADC2_Data), NULL); 8001bde: 2200 movs r2, #0 8001be0: 2120 movs r1, #32 8001be2: 2008 movs r0, #8 8001be4: f011 ff6f bl 8013ac6 8001be8: 4603 mov r3, r0 8001bea: 4a66 ldr r2, [pc, #408] @ (8001d84 ) 8001bec: 6013 str r3, [r2, #0] adc3MeasDataQueue = osMessageQueueNew (8, sizeof (ADC3_Data), NULL); 8001bee: 2200 movs r2, #0 8001bf0: 2120 movs r1, #32 8001bf2: 2008 movs r0, #8 8001bf4: f011 ff67 bl 8013ac6 8001bf8: 4603 mov r3, r0 8001bfa: 4a63 ldr r2, [pc, #396] @ (8001d88 ) 8001bfc: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttradc1MeasTask = { 0 }; 8001bfe: f107 0384 add.w r3, r7, #132 @ 0x84 8001c02: 2224 movs r2, #36 @ 0x24 8001c04: 2100 movs r1, #0 8001c06: 4618 mov r0, r3 8001c08: f016 fc2e bl 8018468 osThreadAttr_t osThreadAttradc3MeasTask = { 0 }; 8001c0c: f107 0360 add.w r3, r7, #96 @ 0x60 8001c10: 2224 movs r2, #36 @ 0x24 8001c12: 2100 movs r1, #0 8001c14: 4618 mov r0, r3 8001c16: f016 fc27 bl 8018468 osThreadAttradc1MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001c1a: f44f 6380 mov.w r3, #1024 @ 0x400 8001c1e: f8c7 3098 str.w r3, [r7, #152] @ 0x98 osThreadAttradc1MeasTask.priority = (osPriority_t)osPriorityRealtime; 8001c22: 2330 movs r3, #48 @ 0x30 8001c24: f8c7 309c str.w r3, [r7, #156] @ 0x9c osThreadAttradc3MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001c28: f44f 6380 mov.w r3, #1024 @ 0x400 8001c2c: 677b str r3, [r7, #116] @ 0x74 osThreadAttradc3MeasTask.priority = (osPriority_t)osPriorityNormal; 8001c2e: 2318 movs r3, #24 8001c30: 67bb str r3, [r7, #120] @ 0x78 adc1MeasTaskHandle = osThreadNew (ADC1MeasTask, NULL, &osThreadAttradc1MeasTask); 8001c32: f107 0384 add.w r3, r7, #132 @ 0x84 8001c36: 461a mov r2, r3 8001c38: 2100 movs r1, #0 8001c3a: 4854 ldr r0, [pc, #336] @ (8001d8c ) 8001c3c: f011 fc90 bl 8013560 8001c40: 4603 mov r3, r0 8001c42: 4a53 ldr r2, [pc, #332] @ (8001d90 ) 8001c44: 6013 str r3, [r2, #0] adc3MeasTaskHandle = osThreadNew (ADC3MeasTask, NULL, &osThreadAttradc3MeasTask); 8001c46: f107 0360 add.w r3, r7, #96 @ 0x60 8001c4a: 461a mov r2, r3 8001c4c: 2100 movs r1, #0 8001c4e: 4851 ldr r0, [pc, #324] @ (8001d94 ) 8001c50: f011 fc86 bl 8013560 8001c54: 4603 mov r3, r0 8001c56: 4a50 ldr r2, [pc, #320] @ (8001d98 ) 8001c58: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttradc1LimiterSwitchTask = { 0 }; 8001c5a: f107 033c add.w r3, r7, #60 @ 0x3c 8001c5e: 2224 movs r2, #36 @ 0x24 8001c60: 2100 movs r1, #0 8001c62: 4618 mov r0, r3 8001c64: f016 fc00 bl 8018468 osThreadAttradc1LimiterSwitchTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001c68: f44f 6380 mov.w r3, #1024 @ 0x400 8001c6c: 653b str r3, [r7, #80] @ 0x50 osThreadAttradc1LimiterSwitchTask.priority = (osPriority_t)osPriorityNormal; 8001c6e: 2318 movs r3, #24 8001c70: 657b str r3, [r7, #84] @ 0x54 limiterSwitchTaskHandle = osThreadNew (LimiterSwitchTask, NULL, &osThreadAttradc1LimiterSwitchTask); 8001c72: f107 033c add.w r3, r7, #60 @ 0x3c 8001c76: 461a mov r2, r3 8001c78: 2100 movs r1, #0 8001c7a: 4848 ldr r0, [pc, #288] @ (8001d9c ) 8001c7c: f011 fc70 bl 8013560 8001c80: 4603 mov r3, r0 8001c82: 4a47 ldr r2, [pc, #284] @ (8001da0 ) 8001c84: 6013 str r3, [r2, #0] encoderXTaskArg.dbgLed = DBG_LED2; 8001c86: 4b47 ldr r3, [pc, #284] @ (8001da4 ) 8001c88: 2220 movs r2, #32 8001c8a: 801a strh r2, [r3, #0] encoderXTaskArg.pvEncoder = &(sensorsInfo.pvEncoderX); 8001c8c: 4b45 ldr r3, [pc, #276] @ (8001da4 ) 8001c8e: 4a46 ldr r2, [pc, #280] @ (8001da8 ) 8001c90: 609a str r2, [r3, #8] encoderXTaskArg.currentPosition = &(sensorsInfo.currentXPosition); 8001c92: 4b44 ldr r3, [pc, #272] @ (8001da4 ) 8001c94: 4a45 ldr r2, [pc, #276] @ (8001dac ) 8001c96: 605a str r2, [r3, #4] osMessageQueueAttr_t encoderMsgQueueAttr = { 0 }; 8001c98: f107 0324 add.w r3, r7, #36 @ 0x24 8001c9c: 2200 movs r2, #0 8001c9e: 601a str r2, [r3, #0] 8001ca0: 605a str r2, [r3, #4] 8001ca2: 609a str r2, [r3, #8] 8001ca4: 60da str r2, [r3, #12] 8001ca6: 611a str r2, [r3, #16] 8001ca8: 615a str r2, [r3, #20] encoderXTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr); 8001caa: f107 0324 add.w r3, r7, #36 @ 0x24 8001cae: 461a mov r2, r3 8001cb0: 2104 movs r1, #4 8001cb2: 2010 movs r0, #16 8001cb4: f011 ff07 bl 8013ac6 8001cb8: 4603 mov r3, r0 8001cba: 4a3a ldr r2, [pc, #232] @ (8001da4 ) 8001cbc: 6113 str r3, [r2, #16] encoderXTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3; 8001cbe: f44f 4100 mov.w r1, #32768 @ 0x8000 8001cc2: 483b ldr r0, [pc, #236] @ (8001db0 ) 8001cc4: f009 fa64 bl 800b190 8001cc8: 4603 mov r3, r0 8001cca: 005c lsls r4, r3, #1 8001ccc: f44f 4180 mov.w r1, #16384 @ 0x4000 8001cd0: 4837 ldr r0, [pc, #220] @ (8001db0 ) 8001cd2: f009 fa5d bl 800b190 8001cd6: 4603 mov r3, r0 8001cd8: 4323 orrs r3, r4 8001cda: f003 0303 and.w r3, r3, #3 8001cde: 4a31 ldr r2, [pc, #196] @ (8001da4 ) 8001ce0: 60d3 str r3, [r2, #12] encoderYTaskArg.dbgLed = DBG_LED3; 8001ce2: 4b34 ldr r3, [pc, #208] @ (8001db4 ) 8001ce4: 2240 movs r2, #64 @ 0x40 8001ce6: 801a strh r2, [r3, #0] encoderYTaskArg.pvEncoder = &(sensorsInfo.pvEncoderY); 8001ce8: 4b32 ldr r3, [pc, #200] @ (8001db4 ) 8001cea: 4a33 ldr r2, [pc, #204] @ (8001db8 ) 8001cec: 609a str r2, [r3, #8] encoderYTaskArg.currentPosition = &(sensorsInfo.currentYPosition); 8001cee: 4b31 ldr r3, [pc, #196] @ (8001db4 ) 8001cf0: 4a32 ldr r2, [pc, #200] @ (8001dbc ) 8001cf2: 605a str r2, [r3, #4] encoderYTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr); 8001cf4: f107 0324 add.w r3, r7, #36 @ 0x24 8001cf8: 461a mov r2, r3 8001cfa: 2104 movs r1, #4 8001cfc: 2010 movs r0, #16 8001cfe: f011 fee2 bl 8013ac6 8001d02: 4603 mov r3, r0 8001d04: 4a2b ldr r2, [pc, #172] @ (8001db4 ) 8001d06: 6113 str r3, [r2, #16] encoderYTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3; 8001d08: f44f 6100 mov.w r1, #2048 @ 0x800 8001d0c: 482c ldr r0, [pc, #176] @ (8001dc0 ) 8001d0e: f009 fa3f bl 800b190 8001d12: 4603 mov r3, r0 8001d14: 005c lsls r4, r3, #1 8001d16: f44f 6180 mov.w r1, #1024 @ 0x400 8001d1a: 4829 ldr r0, [pc, #164] @ (8001dc0 ) 8001d1c: f009 fa38 bl 800b190 8001d20: 4603 mov r3, r0 8001d22: 4323 orrs r3, r4 8001d24: f003 0303 and.w r3, r3, #3 8001d28: 4a22 ldr r2, [pc, #136] @ (8001db4 ) 8001d2a: 60d3 str r3, [r2, #12] osThreadAttr_t osThreadAttrEncoderTask = { 0 }; 8001d2c: 463b mov r3, r7 8001d2e: 2224 movs r2, #36 @ 0x24 8001d30: 2100 movs r1, #0 8001d32: 4618 mov r0, r3 8001d34: f016 fb98 bl 8018468 osThreadAttrEncoderTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001d38: f44f 6380 mov.w r3, #1024 @ 0x400 8001d3c: 617b str r3, [r7, #20] osThreadAttrEncoderTask.priority = (osPriority_t)osPriorityRealtime; 8001d3e: 2330 movs r3, #48 @ 0x30 8001d40: 61bb str r3, [r7, #24] encoderXTaskHandle = osThreadNew (EncoderTask, &encoderXTaskArg, &osThreadAttrEncoderTask); 8001d42: 463b mov r3, r7 8001d44: 461a mov r2, r3 8001d46: 4917 ldr r1, [pc, #92] @ (8001da4 ) 8001d48: 481e ldr r0, [pc, #120] @ (8001dc4 ) 8001d4a: f011 fc09 bl 8013560 8001d4e: 4603 mov r3, r0 8001d50: 4a1d ldr r2, [pc, #116] @ (8001dc8 ) 8001d52: 6013 str r3, [r2, #0] encoderYTaskHandle = osThreadNew (EncoderTask, &encoderYTaskArg, &osThreadAttrEncoderTask); 8001d54: 463b mov r3, r7 8001d56: 461a mov r2, r3 8001d58: 4916 ldr r1, [pc, #88] @ (8001db4 ) 8001d5a: 481a ldr r0, [pc, #104] @ (8001dc4 ) 8001d5c: f011 fc00 bl 8013560 8001d60: 4603 mov r3, r0 8001d62: 4a1a ldr r2, [pc, #104] @ (8001dcc ) 8001d64: 6013 str r3, [r2, #0] // arm_scale_f32(fft_power, scale, fft_power_scaled, SAMPLE_BUFFER_LENGTH_HALF); // float32_t maxValue; // uint32_t maxIndex; // arm_max_f32(fft_power_scaled, SAMPLE_BUFFER_LENGTH_HALF, &maxValue, &maxIndex); // printf("maxValue %f, index %ld\n", maxValue, maxIndex); } 8001d66: bf00 nop 8001d68: 37ac adds r7, #172 @ 0xac 8001d6a: 46bd mov sp, r7 8001d6c: bd90 pop {r4, r7, pc} 8001d6e: bf00 nop 8001d70: 240008d4 .word 0x240008d4 8001d74: 240008d8 .word 0x240008d8 8001d78: 240008dc .word 0x240008dc 8001d7c: 240008e0 .word 0x240008e0 8001d80: 240008c8 .word 0x240008c8 8001d84: 240008cc .word 0x240008cc 8001d88: 240008d0 .word 0x240008d0 8001d8c: 08001dd1 .word 0x08001dd1 8001d90: 240008b4 .word 0x240008b4 8001d94: 08002241 .word 0x08002241 8001d98: 240008b8 .word 0x240008b8 8001d9c: 080025bd .word 0x080025bd 8001da0: 240008bc .word 0x240008bc 8001da4: 24000980 .word 0x24000980 8001da8: 2400094c .word 0x2400094c 8001dac: 24000970 .word 0x24000970 8001db0: 58020c00 .word 0x58020c00 8001db4: 240009a0 .word 0x240009a0 8001db8: 24000950 .word 0x24000950 8001dbc: 24000974 .word 0x24000974 8001dc0: 58020400 .word 0x58020400 8001dc4: 080028c5 .word 0x080028c5 8001dc8: 240008c0 .word 0x240008c0 8001dcc: 240008c4 .word 0x240008c4 08001dd0 : void ADC1MeasTask (void* arg) { 8001dd0: b590 push {r4, r7, lr} 8001dd2: b097 sub sp, #92 @ 0x5c 8001dd4: af00 add r7, sp, #0 8001dd6: 6078 str r0, [r7, #4] float voltageAcc[CHANNELS_COUNT] = { 0 }; 8001dd8: f04f 0300 mov.w r3, #0 8001ddc: 637b str r3, [r7, #52] @ 0x34 float currentAcc[CHANNELS_COUNT] = { 0 }; 8001dde: f04f 0300 mov.w r3, #0 8001de2: 633b str r3, [r7, #48] @ 0x30 float powerAcc[CHANNELS_COUNT] = { 0 }; 8001de4: f04f 0300 mov.w r3, #0 8001de8: 62fb str r3, [r7, #44] @ 0x2c uint32_t samplesCounter = 0; 8001dea: 2300 movs r3, #0 8001dec: 657b str r3, [r7, #84] @ 0x54 ADC1_Data adcData = { 0 }; 8001dee: f107 030c add.w r3, r7, #12 8001df2: 2220 movs r2, #32 8001df4: 2100 movs r1, #0 8001df6: 4618 mov r0, r3 8001df8: f016 fb36 bl 8018468 float gainCorrection = 1.0; 8001dfc: f04f 537e mov.w r3, #1065353216 @ 0x3f800000 8001e00: 653b str r3, [r7, #80] @ 0x50 while (pdTRUE) { osMessageQueueGet (adc1MeasDataQueue, &adcData, 0, osWaitForever); 8001e02: 4bb1 ldr r3, [pc, #708] @ (80020c8 ) 8001e04: 6818 ldr r0, [r3, #0] 8001e06: f107 010c add.w r1, r7, #12 8001e0a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8001e0e: 2200 movs r2, #0 8001e10: f011 ff2c bl 8013c6c #ifdef GAIN_AUTO_CORRECTION if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 8001e14: 4bad ldr r3, [pc, #692] @ (80020cc ) 8001e16: 681b ldr r3, [r3, #0] 8001e18: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001e1c: 4618 mov r0, r3 8001e1e: f011 fdca bl 80139b6 8001e22: 4603 mov r3, r0 8001e24: 2b00 cmp r3, #0 8001e26: d10c bne.n 8001e42 gainCorrection = (float)vRefmV; 8001e28: 4ba9 ldr r3, [pc, #676] @ (80020d0 ) 8001e2a: 681b ldr r3, [r3, #0] 8001e2c: ee07 3a90 vmov s15, r3 8001e30: eef8 7a67 vcvt.f32.u32 s15, s15 8001e34: edc7 7a14 vstr s15, [r7, #80] @ 0x50 osMutexRelease (vRefmVMutex); 8001e38: 4ba4 ldr r3, [pc, #656] @ (80020cc ) 8001e3a: 681b ldr r3, [r3, #0] 8001e3c: 4618 mov r0, r3 8001e3e: f011 fe05 bl 8013a4c } gainCorrection = gainCorrection / EXT_VREF_mV; 8001e42: ed97 7a14 vldr s14, [r7, #80] @ 0x50 8001e46: eddf 6aa3 vldr s13, [pc, #652] @ 80020d4 8001e4a: eec7 7a26 vdiv.f32 s15, s14, s13 8001e4e: edc7 7a14 vstr s15, [r7, #80] @ 0x50 #endif if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8001e52: 4ba1 ldr r3, [pc, #644] @ (80020d8 ) 8001e54: 681b ldr r3, [r3, #0] 8001e56: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001e5a: 4618 mov r0, r3 8001e5c: f011 fdab bl 80139b6 8001e60: 4603 mov r3, r0 8001e62: 2b00 cmp r3, #0 8001e64: d1cd bne.n 8001e02 for (uint8_t i = 0; i < CHANNELS_COUNT; i++) { 8001e66: 2300 movs r3, #0 8001e68: f887 304f strb.w r3, [r7, #79] @ 0x4f 8001e6c: e10d b.n 800208a #ifdef MOCK_VOLTAGES_AND_CURRENS float voltage = voltageWave[i][samplesCounter % SAMPLE_BUFFER_LENGTH]; float current = currentWave[i][samplesCounter % SAMPLE_BUFFER_LENGTH]; #else float voltage = (adcData.adcDataBuffer[UL1 + i] & 0xFFFF) * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 8001e6e: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001e72: 009b lsls r3, r3, #2 8001e74: 3358 adds r3, #88 @ 0x58 8001e76: 443b add r3, r7 8001e78: f853 3c4c ldr.w r3, [r3, #-76] 8001e7c: b29b uxth r3, r3 8001e7e: ee07 3a90 vmov s15, r3 8001e82: eeb8 7b67 vcvt.f64.u32 d7, s15 8001e86: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8001e8a: ee27 6b06 vmul.f64 d6, d7, d6 8001e8e: ed9f 5b88 vldr d5, [pc, #544] @ 80020b0 8001e92: ee86 7b05 vdiv.f64 d7, d6, d5 8001e96: ed9f 6b88 vldr d6, [pc, #544] @ 80020b8 8001e9a: ee27 6b06 vmul.f64 d6, d7, d6 8001e9e: edd7 7a14 vldr s15, [r7, #80] @ 0x50 8001ea2: eeb7 7ae7 vcvt.f64.f32 d7, s15 8001ea6: ee26 6b07 vmul.f64 d6, d6, d7 8001eaa: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001eae: 4a8b ldr r2, [pc, #556] @ (80020dc ) 8001eb0: 00db lsls r3, r3, #3 8001eb2: 4413 add r3, r2 8001eb4: edd3 7a00 vldr s15, [r3] 8001eb8: eeb7 7ae7 vcvt.f64.f32 d7, s15 8001ebc: ee26 6b07 vmul.f64 d6, d6, d7 8001ec0: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001ec4: 4a85 ldr r2, [pc, #532] @ (80020dc ) 8001ec6: 00db lsls r3, r3, #3 8001ec8: 4413 add r3, r2 8001eca: 3304 adds r3, #4 8001ecc: edd3 7a00 vldr s15, [r3] 8001ed0: eeb7 7ae7 vcvt.f64.f32 d7, s15 8001ed4: ee36 7b07 vadd.f64 d7, d6, d7 8001ed8: eef7 7bc7 vcvt.f32.f64 s15, d7 8001edc: edc7 7a11 vstr s15, [r7, #68] @ 0x44 float ref = (float)(adcData.adcDataBuffer[IL1Ref + i] & 0xFFFF); 8001ee0: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001ee4: 3303 adds r3, #3 8001ee6: 009b lsls r3, r3, #2 8001ee8: 3358 adds r3, #88 @ 0x58 8001eea: 443b add r3, r7 8001eec: f853 3c4c ldr.w r3, [r3, #-76] 8001ef0: b29b uxth r3, r3 8001ef2: ee07 3a90 vmov s15, r3 8001ef6: eef8 7a67 vcvt.f32.u32 s15, s15 8001efa: edc7 7a10 vstr s15, [r7, #64] @ 0x40 float adcVal = (float)(adcData.adcDataBuffer[UL1 + i] >> 16); 8001efe: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001f02: 009b lsls r3, r3, #2 8001f04: 3358 adds r3, #88 @ 0x58 8001f06: 443b add r3, r7 8001f08: f853 3c4c ldr.w r3, [r3, #-76] 8001f0c: 0c1b lsrs r3, r3, #16 8001f0e: ee07 3a90 vmov s15, r3 8001f12: eef8 7a67 vcvt.f32.u32 s15, s15 8001f16: edc7 7a0f vstr s15, [r7, #60] @ 0x3c float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset; 8001f1a: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8001f1e: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8001f22: ee77 7a67 vsub.f32 s15, s14, s15 8001f26: eeb7 7ae7 vcvt.f64.f32 d7, s15 8001f2a: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8001f2e: ee27 6b06 vmul.f64 d6, d7, d6 8001f32: ed9f 5b5f vldr d5, [pc, #380] @ 80020b0 8001f36: ee86 7b05 vdiv.f64 d7, d6, d5 8001f3a: ed9f 6b61 vldr d6, [pc, #388] @ 80020c0 8001f3e: ee27 6b06 vmul.f64 d6, d7, d6 8001f42: edd7 7a14 vldr s15, [r7, #80] @ 0x50 8001f46: eeb7 7ae7 vcvt.f64.f32 d7, s15 8001f4a: ee26 6b07 vmul.f64 d6, d6, d7 8001f4e: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001f52: 4a63 ldr r2, [pc, #396] @ (80020e0 ) 8001f54: 00db lsls r3, r3, #3 8001f56: 4413 add r3, r2 8001f58: edd3 7a00 vldr s15, [r3] 8001f5c: eeb7 7ae7 vcvt.f64.f32 d7, s15 8001f60: ee26 6b07 vmul.f64 d6, d6, d7 8001f64: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001f68: 4a5d ldr r2, [pc, #372] @ (80020e0 ) 8001f6a: 00db lsls r3, r3, #3 8001f6c: 4413 add r3, r2 8001f6e: 3304 adds r3, #4 8001f70: edd3 7a00 vldr s15, [r3] 8001f74: eeb7 7ae7 vcvt.f64.f32 d7, s15 8001f78: ee36 7b07 vadd.f64 d7, d6, d7 8001f7c: eef7 7bc7 vcvt.f32.f64 s15, d7 8001f80: edc7 7a0e vstr s15, [r7, #56] @ 0x38 #endif voltageAcc[i] += voltage * voltage; 8001f84: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001f88: 009b lsls r3, r3, #2 8001f8a: 3358 adds r3, #88 @ 0x58 8001f8c: 443b add r3, r7 8001f8e: 3b24 subs r3, #36 @ 0x24 8001f90: ed93 7a00 vldr s14, [r3] 8001f94: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8001f98: ee67 7aa7 vmul.f32 s15, s15, s15 8001f9c: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001fa0: ee77 7a27 vadd.f32 s15, s14, s15 8001fa4: 009b lsls r3, r3, #2 8001fa6: 3358 adds r3, #88 @ 0x58 8001fa8: 443b add r3, r7 8001faa: 3b24 subs r3, #36 @ 0x24 8001fac: edc3 7a00 vstr s15, [r3] currentAcc[i] += current * current; 8001fb0: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001fb4: 009b lsls r3, r3, #2 8001fb6: 3358 adds r3, #88 @ 0x58 8001fb8: 443b add r3, r7 8001fba: 3b28 subs r3, #40 @ 0x28 8001fbc: ed93 7a00 vldr s14, [r3] 8001fc0: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8001fc4: ee67 7aa7 vmul.f32 s15, s15, s15 8001fc8: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001fcc: ee77 7a27 vadd.f32 s15, s14, s15 8001fd0: 009b lsls r3, r3, #2 8001fd2: 3358 adds r3, #88 @ 0x58 8001fd4: 443b add r3, r7 8001fd6: 3b28 subs r3, #40 @ 0x28 8001fd8: edc3 7a00 vstr s15, [r3] powerAcc[i] += voltage * current; 8001fdc: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001fe0: 009b lsls r3, r3, #2 8001fe2: 3358 adds r3, #88 @ 0x58 8001fe4: 443b add r3, r7 8001fe6: 3b2c subs r3, #44 @ 0x2c 8001fe8: ed93 7a00 vldr s14, [r3] 8001fec: edd7 6a11 vldr s13, [r7, #68] @ 0x44 8001ff0: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8001ff4: ee66 7aa7 vmul.f32 s15, s13, s15 8001ff8: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8001ffc: ee77 7a27 vadd.f32 s15, s14, s15 8002000: 009b lsls r3, r3, #2 8002002: 3358 adds r3, #88 @ 0x58 8002004: 443b add r3, r7 8002006: 3b2c subs r3, #44 @ 0x2c 8002008: edc3 7a00 vstr s15, [r3] if (fabs (resMeasurements.voltagePeak[i]) < fabs (voltage)) { 800200c: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8002010: 4a34 ldr r2, [pc, #208] @ (80020e4 ) 8002012: 3302 adds r3, #2 8002014: 009b lsls r3, r3, #2 8002016: 4413 add r3, r2 8002018: 3304 adds r3, #4 800201a: edd3 7a00 vldr s15, [r3] 800201e: eeb0 7ae7 vabs.f32 s14, s15 8002022: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8002026: eef0 7ae7 vabs.f32 s15, s15 800202a: eeb4 7ae7 vcmpe.f32 s14, s15 800202e: eef1 fa10 vmrs APSR_nzcv, fpscr 8002032: d508 bpl.n 8002046 resMeasurements.voltagePeak[i] = voltage; 8002034: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8002038: 4a2a ldr r2, [pc, #168] @ (80020e4 ) 800203a: 3302 adds r3, #2 800203c: 009b lsls r3, r3, #2 800203e: 4413 add r3, r2 8002040: 3304 adds r3, #4 8002042: 6c7a ldr r2, [r7, #68] @ 0x44 8002044: 601a str r2, [r3, #0] } if (fabs (resMeasurements.currentPeak[i]) < fabs (current)) { 8002046: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 800204a: 4a26 ldr r2, [pc, #152] @ (80020e4 ) 800204c: 3308 adds r3, #8 800204e: 009b lsls r3, r3, #2 8002050: 4413 add r3, r2 8002052: 3304 adds r3, #4 8002054: edd3 7a00 vldr s15, [r3] 8002058: eeb0 7ae7 vabs.f32 s14, s15 800205c: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8002060: eef0 7ae7 vabs.f32 s15, s15 8002064: eeb4 7ae7 vcmpe.f32 s14, s15 8002068: eef1 fa10 vmrs APSR_nzcv, fpscr 800206c: d508 bpl.n 8002080 resMeasurements.currentPeak[i] = current; 800206e: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8002072: 4a1c ldr r2, [pc, #112] @ (80020e4 ) 8002074: 3308 adds r3, #8 8002076: 009b lsls r3, r3, #2 8002078: 4413 add r3, r2 800207a: 3304 adds r3, #4 800207c: 6bba ldr r2, [r7, #56] @ 0x38 800207e: 601a str r2, [r3, #0] for (uint8_t i = 0; i < CHANNELS_COUNT; i++) { 8002080: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 8002084: 3301 adds r3, #1 8002086: f887 304f strb.w r3, [r7, #79] @ 0x4f 800208a: f897 304f ldrb.w r3, [r7, #79] @ 0x4f 800208e: 2b00 cmp r3, #0 8002090: f43f aeed beq.w 8001e6e } } samplesCounter += 1; 8002094: 6d7b ldr r3, [r7, #84] @ 0x54 8002096: 3301 adds r3, #1 8002098: 657b str r3, [r7, #84] @ 0x54 if (samplesCounter > 33332) 800209a: 6d7b ldr r3, [r7, #84] @ 0x54 800209c: f248 2234 movw r2, #33332 @ 0x8234 80020a0: 4293 cmp r3, r2 80020a2: f240 809a bls.w 80021da { for (uint8_t i = 0; i < CHANNELS_COUNT; i++) { 80020a6: 2300 movs r3, #0 80020a8: f887 304e strb.w r3, [r7, #78] @ 0x4e 80020ac: e08c b.n 80021c8 80020ae: bf00 nop 80020b0: 00000000 .word 0x00000000 80020b4: 40efffe0 .word 0x40efffe0 80020b8: f5c28f5c .word 0xf5c28f5c 80020bc: 401e5c28 .word 0x401e5c28 80020c0: 83e425af .word 0x83e425af 80020c4: 401e4d9e .word 0x401e4d9e 80020c8: 240008c8 .word 0x240008c8 80020cc: 240008d4 .word 0x240008d4 80020d0: 24000030 .word 0x24000030 80020d4: 453b8000 .word 0x453b8000 80020d8: 240008d8 .word 0x240008d8 80020dc: 24000000 .word 0x24000000 80020e0: 24000018 .word 0x24000018 80020e4: 24000900 .word 0x24000900 resMeasurements.voltageRMS[i] = sqrtf(voltageAcc[i] / samplesCounter); 80020e8: f897 304e ldrb.w r3, [r7, #78] @ 0x4e 80020ec: 009b lsls r3, r3, #2 80020ee: 3358 adds r3, #88 @ 0x58 80020f0: 443b add r3, r7 80020f2: 3b24 subs r3, #36 @ 0x24 80020f4: ed93 7a00 vldr s14, [r3] 80020f8: 6d7b ldr r3, [r7, #84] @ 0x54 80020fa: ee07 3a90 vmov s15, r3 80020fe: eef8 7a67 vcvt.f32.u32 s15, s15 8002102: eec7 6a27 vdiv.f32 s13, s14, s15 8002106: f897 404e ldrb.w r4, [r7, #78] @ 0x4e 800210a: eeb0 0a66 vmov.f32 s0, s13 800210e: f018 f81f bl 801a150 8002112: eef0 7a40 vmov.f32 s15, s0 8002116: 4a46 ldr r2, [pc, #280] @ (8002230 ) 8002118: 00a3 lsls r3, r4, #2 800211a: 4413 add r3, r2 800211c: edc3 7a00 vstr s15, [r3] resMeasurements.currentRMS[i] = sqrtf(currentAcc[i] / samplesCounter); 8002120: f897 304e ldrb.w r3, [r7, #78] @ 0x4e 8002124: 009b lsls r3, r3, #2 8002126: 3358 adds r3, #88 @ 0x58 8002128: 443b add r3, r7 800212a: 3b28 subs r3, #40 @ 0x28 800212c: ed93 7a00 vldr s14, [r3] 8002130: 6d7b ldr r3, [r7, #84] @ 0x54 8002132: ee07 3a90 vmov s15, r3 8002136: eef8 7a67 vcvt.f32.u32 s15, s15 800213a: eec7 6a27 vdiv.f32 s13, s14, s15 800213e: f897 404e ldrb.w r4, [r7, #78] @ 0x4e 8002142: eeb0 0a66 vmov.f32 s0, s13 8002146: f018 f803 bl 801a150 800214a: eef0 7a40 vmov.f32 s15, s0 800214e: 4a38 ldr r2, [pc, #224] @ (8002230 ) 8002150: 1da3 adds r3, r4, #6 8002152: 009b lsls r3, r3, #2 8002154: 4413 add r3, r2 8002156: edc3 7a00 vstr s15, [r3] resMeasurements.power[i] = powerAcc[i] / samplesCounter; 800215a: f897 304e ldrb.w r3, [r7, #78] @ 0x4e 800215e: 009b lsls r3, r3, #2 8002160: 3358 adds r3, #88 @ 0x58 8002162: 443b add r3, r7 8002164: 3b2c subs r3, #44 @ 0x2c 8002166: edd3 6a00 vldr s13, [r3] 800216a: 6d7b ldr r3, [r7, #84] @ 0x54 800216c: ee07 3a90 vmov s15, r3 8002170: eeb8 7a67 vcvt.f32.u32 s14, s15 8002174: f897 304e ldrb.w r3, [r7, #78] @ 0x4e 8002178: eec6 7a87 vdiv.f32 s15, s13, s14 800217c: 4a2c ldr r2, [pc, #176] @ (8002230 ) 800217e: 330c adds r3, #12 8002180: 009b lsls r3, r3, #2 8002182: 4413 add r3, r2 8002184: edc3 7a00 vstr s15, [r3] voltageAcc[i] = 0; 8002188: f897 304e ldrb.w r3, [r7, #78] @ 0x4e 800218c: 009b lsls r3, r3, #2 800218e: 3358 adds r3, #88 @ 0x58 8002190: 443b add r3, r7 8002192: 3b24 subs r3, #36 @ 0x24 8002194: f04f 0200 mov.w r2, #0 8002198: 601a str r2, [r3, #0] currentAcc[i] = 0; 800219a: f897 304e ldrb.w r3, [r7, #78] @ 0x4e 800219e: 009b lsls r3, r3, #2 80021a0: 3358 adds r3, #88 @ 0x58 80021a2: 443b add r3, r7 80021a4: 3b28 subs r3, #40 @ 0x28 80021a6: f04f 0200 mov.w r2, #0 80021aa: 601a str r2, [r3, #0] powerAcc[i] = 0; 80021ac: f897 304e ldrb.w r3, [r7, #78] @ 0x4e 80021b0: 009b lsls r3, r3, #2 80021b2: 3358 adds r3, #88 @ 0x58 80021b4: 443b add r3, r7 80021b6: 3b2c subs r3, #44 @ 0x2c 80021b8: f04f 0200 mov.w r2, #0 80021bc: 601a str r2, [r3, #0] for (uint8_t i = 0; i < CHANNELS_COUNT; i++) { 80021be: f897 304e ldrb.w r3, [r7, #78] @ 0x4e 80021c2: 3301 adds r3, #1 80021c4: f887 304e strb.w r3, [r7, #78] @ 0x4e 80021c8: f897 304e ldrb.w r3, [r7, #78] @ 0x4e 80021cc: 2b00 cmp r3, #0 80021ce: d08b beq.n 80020e8 } samplesCounter = 0; 80021d0: 2300 movs r3, #0 80021d2: 657b str r3, [r7, #84] @ 0x54 DbgLEDToggle(DBG_LED3); 80021d4: 2040 movs r0, #64 @ 0x40 80021d6: f000 fc53 bl 8002a80 } float fanFBVoltage = (adcData.adcDataBuffer[FanFB] & 0xFFFF) * deltaADC * -4.35 + 12; 80021da: 6a7b ldr r3, [r7, #36] @ 0x24 80021dc: b29b uxth r3, r3 80021de: ee07 3a90 vmov s15, r3 80021e2: eeb8 7b67 vcvt.f64.u32 d7, s15 80021e6: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80021ea: ee27 6b06 vmul.f64 d6, d7, d6 80021ee: ed9f 5b0c vldr d5, [pc, #48] @ 8002220 80021f2: ee86 7b05 vdiv.f64 d7, d6, d5 80021f6: ed9f 6b0c vldr d6, [pc, #48] @ 8002228 80021fa: ee27 7b06 vmul.f64 d7, d7, d6 80021fe: eeb2 6b08 vmov.f64 d6, #40 @ 0x41400000 12.0 8002202: ee37 7b06 vadd.f64 d7, d7, d6 8002206: eef7 7bc7 vcvt.f32.f64 s15, d7 800220a: edc7 7a12 vstr s15, [r7, #72] @ 0x48 sensorsInfo.fanVoltage = fanFBVoltage; 800220e: 4a09 ldr r2, [pc, #36] @ (8002234 ) 8002210: 6cbb ldr r3, [r7, #72] @ 0x48 8002212: 6093 str r3, [r2, #8] osMutexRelease (resMeasurementsMutex); 8002214: 4b08 ldr r3, [pc, #32] @ (8002238 ) 8002216: 681b ldr r3, [r3, #0] 8002218: 4618 mov r0, r3 800221a: f011 fc17 bl 8013a4c osMessageQueueGet (adc1MeasDataQueue, &adcData, 0, osWaitForever); 800221e: e5f0 b.n 8001e02 8002220: 00000000 .word 0x00000000 8002224: 40efffe0 .word 0x40efffe0 8002228: 66666666 .word 0x66666666 800222c: c0116666 .word 0xc0116666 8002230: 24000900 .word 0x24000900 8002234: 24000940 .word 0x24000940 8002238: 240008d8 .word 0x240008d8 800223c: 00000000 .word 0x00000000 08002240 : } } } void ADC3MeasTask (void* arg) { 8002240: b580 push {r7, lr} 8002242: b0bc sub sp, #240 @ 0xf0 8002244: af00 add r7, sp, #0 8002246: 6078 str r0, [r7, #4] float motorXSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 8002248: f107 03a4 add.w r3, r7, #164 @ 0xa4 800224c: 2228 movs r2, #40 @ 0x28 800224e: 2100 movs r1, #0 8002250: 4618 mov r0, r3 8002252: f016 f909 bl 8018468 float motorYSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 8002256: f107 037c add.w r3, r7, #124 @ 0x7c 800225a: 2228 movs r2, #40 @ 0x28 800225c: 2100 movs r1, #0 800225e: 4618 mov r0, r3 8002260: f016 f902 bl 8018468 #ifdef PV_BOARD float pvT1CircBuffer[CIRC_BUFF_LEN] = { 0 }; 8002264: f107 0354 add.w r3, r7, #84 @ 0x54 8002268: 2228 movs r2, #40 @ 0x28 800226a: 2100 movs r1, #0 800226c: 4618 mov r0, r3 800226e: f016 f8fb bl 8018468 float pvT2CircBuffer[CIRC_BUFF_LEN] = { 0 }; 8002272: f107 032c add.w r3, r7, #44 @ 0x2c 8002276: 2228 movs r2, #40 @ 0x28 8002278: 2100 movs r1, #0 800227a: 4618 mov r0, r3 800227c: f016 f8f4 bl 8018468 #endif uint32_t circBuffPos = 0; 8002280: 2300 movs r3, #0 8002282: f8c7 30ec str.w r3, [r7, #236] @ 0xec ADC3_Data adcData = { 0 }; 8002286: f107 030c add.w r3, r7, #12 800228a: 2220 movs r2, #32 800228c: 2100 movs r1, #0 800228e: 4618 mov r0, r3 8002290: f016 f8ea bl 8018468 while (pdTRUE) { osMessageQueueGet (adc3MeasDataQueue, &adcData, 0, osWaitForever); 8002294: 4bc2 ldr r3, [pc, #776] @ (80025a0 ) 8002296: 6818 ldr r0, [r3, #0] 8002298: f107 010c add.w r1, r7, #12 800229c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80022a0: 2200 movs r2, #0 80022a2: f011 fce3 bl 8013c6c uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B); 80022a6: 4bbf ldr r3, [pc, #764] @ (80025a4 ) 80022a8: 881b ldrh r3, [r3, #0] 80022aa: 461a mov r2, r3 80022ac: f640 43e4 movw r3, #3300 @ 0xce4 80022b0: fb02 f303 mul.w r3, r2, r3 80022b4: 8aba ldrh r2, [r7, #20] 80022b6: fbb3 f3f2 udiv r3, r3, r2 80022ba: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 80022be: 4bba ldr r3, [pc, #744] @ (80025a8 ) 80022c0: 681b ldr r3, [r3, #0] 80022c2: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80022c6: 4618 mov r0, r3 80022c8: f011 fb75 bl 80139b6 80022cc: 4603 mov r3, r0 80022ce: 2b00 cmp r3, #0 80022d0: d108 bne.n 80022e4 vRefmV = vRef; 80022d2: 4ab6 ldr r2, [pc, #728] @ (80025ac ) 80022d4: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 80022d8: 6013 str r3, [r2, #0] osMutexRelease (vRefmVMutex); 80022da: 4bb3 ldr r3, [pc, #716] @ (80025a8 ) 80022dc: 681b ldr r3, [r3, #0] 80022de: 4618 mov r0, r3 80022e0: f011 fbb4 bl 8013a4c } float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333; 80022e4: 8a3b ldrh r3, [r7, #16] 80022e6: ee07 3a90 vmov s15, r3 80022ea: eeb8 7be7 vcvt.f64.s32 d7, s15 80022ee: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80022f2: ee27 6b06 vmul.f64 d6, d7, d6 80022f6: ed9f 5ba2 vldr d5, [pc, #648] @ 8002580 80022fa: ee86 7b05 vdiv.f64 d7, d6, d5 80022fe: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 8002302: ee27 6b06 vmul.f64 d6, d7, d6 8002306: ed9f 5ba0 vldr d5, [pc, #640] @ 8002588 800230a: ee86 7b05 vdiv.f64 d7, d6, d5 800230e: eef7 7bc7 vcvt.f32.f64 s15, d7 8002312: edc7 7a34 vstr s15, [r7, #208] @ 0xd0 float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333; 8002316: 8a7b ldrh r3, [r7, #18] 8002318: ee07 3a90 vmov s15, r3 800231c: eeb8 7be7 vcvt.f64.s32 d7, s15 8002320: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002324: ee27 6b06 vmul.f64 d6, d7, d6 8002328: ed9f 5b95 vldr d5, [pc, #596] @ 8002580 800232c: ee86 7b05 vdiv.f64 d7, d6, d5 8002330: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 8002334: ee27 6b06 vmul.f64 d6, d7, d6 8002338: ed9f 5b93 vldr d5, [pc, #588] @ 8002588 800233c: ee86 7b05 vdiv.f64 d7, d6, d5 8002340: eef7 7bc7 vcvt.f32.f64 s15, d7 8002344: edc7 7a33 vstr s15, [r7, #204] @ 0xcc motorXSensCircBuffer[circBuffPos] = motorXCurrentSense; 8002348: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 800234c: 009b lsls r3, r3, #2 800234e: 33f0 adds r3, #240 @ 0xf0 8002350: 443b add r3, r7 8002352: 3b4c subs r3, #76 @ 0x4c 8002354: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8002358: 601a str r2, [r3, #0] motorYSensCircBuffer[circBuffPos] = motorYCurrentSense; 800235a: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 800235e: 009b lsls r3, r3, #2 8002360: 33f0 adds r3, #240 @ 0xf0 8002362: 443b add r3, r7 8002364: 3b74 subs r3, #116 @ 0x74 8002366: f8d7 20cc ldr.w r2, [r7, #204] @ 0xcc 800236a: 601a str r2, [r3, #0] #ifdef PV_BOARD pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63; 800236c: 89bb ldrh r3, [r7, #12] 800236e: ee07 3a90 vmov s15, r3 8002372: eeb8 7be7 vcvt.f64.s32 d7, s15 8002376: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 800237a: ee27 6b06 vmul.f64 d6, d7, d6 800237e: ed9f 5b80 vldr d5, [pc, #512] @ 8002580 8002382: ee86 7b05 vdiv.f64 d7, d6, d5 8002386: ed9f 6b82 vldr d6, [pc, #520] @ 8002590 800238a: ee27 7b06 vmul.f64 d7, d7, d6 800238e: ed9f 6b82 vldr d6, [pc, #520] @ 8002598 8002392: ee37 7b46 vsub.f64 d7, d7, d6 8002396: eef7 7bc7 vcvt.f32.f64 s15, d7 800239a: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 800239e: 009b lsls r3, r3, #2 80023a0: 33f0 adds r3, #240 @ 0xf0 80023a2: 443b add r3, r7 80023a4: 3b9c subs r3, #156 @ 0x9c 80023a6: edc3 7a00 vstr s15, [r3] pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63; 80023aa: 89fb ldrh r3, [r7, #14] 80023ac: ee07 3a90 vmov s15, r3 80023b0: eeb8 7be7 vcvt.f64.s32 d7, s15 80023b4: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80023b8: ee27 6b06 vmul.f64 d6, d7, d6 80023bc: ed9f 5b70 vldr d5, [pc, #448] @ 8002580 80023c0: ee86 7b05 vdiv.f64 d7, d6, d5 80023c4: ed9f 6b72 vldr d6, [pc, #456] @ 8002590 80023c8: ee27 7b06 vmul.f64 d7, d7, d6 80023cc: ed9f 6b72 vldr d6, [pc, #456] @ 8002598 80023d0: ee37 7b46 vsub.f64 d7, d7, d6 80023d4: eef7 7bc7 vcvt.f32.f64 s15, d7 80023d8: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 80023dc: 009b lsls r3, r3, #2 80023de: 33f0 adds r3, #240 @ 0xf0 80023e0: 443b add r3, r7 80023e2: 3bc4 subs r3, #196 @ 0xc4 80023e4: edc3 7a00 vstr s15, [r3] #endif float motorXAveCurrent = 0; 80023e8: f04f 0300 mov.w r3, #0 80023ec: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 float motorYAveCurrent = 0; 80023f0: f04f 0300 mov.w r3, #0 80023f4: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 float pvT1AveTemp = 0; 80023f8: f04f 0300 mov.w r3, #0 80023fc: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 float pvT2AveTemp = 0; 8002400: f04f 0300 mov.w r3, #0 8002404: f8c7 30dc str.w r3, [r7, #220] @ 0xdc for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) { 8002408: 2300 movs r3, #0 800240a: f887 30db strb.w r3, [r7, #219] @ 0xdb 800240e: e03c b.n 800248a motorXAveCurrent += motorXSensCircBuffer[i]; 8002410: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002414: 009b lsls r3, r3, #2 8002416: 33f0 adds r3, #240 @ 0xf0 8002418: 443b add r3, r7 800241a: 3b4c subs r3, #76 @ 0x4c 800241c: edd3 7a00 vldr s15, [r3] 8002420: ed97 7a3a vldr s14, [r7, #232] @ 0xe8 8002424: ee77 7a27 vadd.f32 s15, s14, s15 8002428: edc7 7a3a vstr s15, [r7, #232] @ 0xe8 motorYAveCurrent += motorYSensCircBuffer[i]; 800242c: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002430: 009b lsls r3, r3, #2 8002432: 33f0 adds r3, #240 @ 0xf0 8002434: 443b add r3, r7 8002436: 3b74 subs r3, #116 @ 0x74 8002438: edd3 7a00 vldr s15, [r3] 800243c: ed97 7a39 vldr s14, [r7, #228] @ 0xe4 8002440: ee77 7a27 vadd.f32 s15, s14, s15 8002444: edc7 7a39 vstr s15, [r7, #228] @ 0xe4 #ifdef PV_BOARD pvT1AveTemp += pvT1CircBuffer[i]; 8002448: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 800244c: 009b lsls r3, r3, #2 800244e: 33f0 adds r3, #240 @ 0xf0 8002450: 443b add r3, r7 8002452: 3b9c subs r3, #156 @ 0x9c 8002454: edd3 7a00 vldr s15, [r3] 8002458: ed97 7a38 vldr s14, [r7, #224] @ 0xe0 800245c: ee77 7a27 vadd.f32 s15, s14, s15 8002460: edc7 7a38 vstr s15, [r7, #224] @ 0xe0 pvT2AveTemp += pvT2CircBuffer[i]; 8002464: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002468: 009b lsls r3, r3, #2 800246a: 33f0 adds r3, #240 @ 0xf0 800246c: 443b add r3, r7 800246e: 3bc4 subs r3, #196 @ 0xc4 8002470: edd3 7a00 vldr s15, [r3] 8002474: ed97 7a37 vldr s14, [r7, #220] @ 0xdc 8002478: ee77 7a27 vadd.f32 s15, s14, s15 800247c: edc7 7a37 vstr s15, [r7, #220] @ 0xdc for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) { 8002480: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002484: 3301 adds r3, #1 8002486: f887 30db strb.w r3, [r7, #219] @ 0xdb 800248a: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 800248e: 2b09 cmp r3, #9 8002490: d9be bls.n 8002410 #endif } motorXAveCurrent /= CIRC_BUFF_LEN; 8002492: ed97 7a3a vldr s14, [r7, #232] @ 0xe8 8002496: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 800249a: eec7 7a26 vdiv.f32 s15, s14, s13 800249e: edc7 7a3a vstr s15, [r7, #232] @ 0xe8 motorYAveCurrent /= CIRC_BUFF_LEN; 80024a2: ed97 7a39 vldr s14, [r7, #228] @ 0xe4 80024a6: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 80024aa: eec7 7a26 vdiv.f32 s15, s14, s13 80024ae: edc7 7a39 vstr s15, [r7, #228] @ 0xe4 pvT1AveTemp /= CIRC_BUFF_LEN; 80024b2: ed97 7a38 vldr s14, [r7, #224] @ 0xe0 80024b6: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 80024ba: eec7 7a26 vdiv.f32 s15, s14, s13 80024be: edc7 7a38 vstr s15, [r7, #224] @ 0xe0 pvT2AveTemp /= CIRC_BUFF_LEN; 80024c2: ed97 7a37 vldr s14, [r7, #220] @ 0xdc 80024c6: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 80024ca: eec7 7a26 vdiv.f32 s15, s14, s13 80024ce: edc7 7a37 vstr s15, [r7, #220] @ 0xdc if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80024d2: 4b37 ldr r3, [pc, #220] @ (80025b0 ) 80024d4: 681b ldr r3, [r3, #0] 80024d6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80024da: 4618 mov r0, r3 80024dc: f011 fa6b bl 80139b6 80024e0: 4603 mov r3, r0 80024e2: 2b00 cmp r3, #0 80024e4: d138 bne.n 8002558 if (sensorsInfo.motorXStatus == 1) { 80024e6: 4b33 ldr r3, [pc, #204] @ (80025b4 ) 80024e8: 7d1b ldrb r3, [r3, #20] 80024ea: 2b01 cmp r3, #1 80024ec: d111 bne.n 8002512 sensorsInfo.motorXAveCurrent = motorXAveCurrent; 80024ee: 4a31 ldr r2, [pc, #196] @ (80025b4 ) 80024f0: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8 80024f4: 6193 str r3, [r2, #24] if (sensorsInfo.motorXPeakCurrent < motorXCurrentSense) { 80024f6: 4b2f ldr r3, [pc, #188] @ (80025b4 ) 80024f8: edd3 7a08 vldr s15, [r3, #32] 80024fc: ed97 7a34 vldr s14, [r7, #208] @ 0xd0 8002500: eeb4 7ae7 vcmpe.f32 s14, s15 8002504: eef1 fa10 vmrs APSR_nzcv, fpscr 8002508: dd03 ble.n 8002512 sensorsInfo.motorXPeakCurrent = motorXCurrentSense; 800250a: 4a2a ldr r2, [pc, #168] @ (80025b4 ) 800250c: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0 8002510: 6213 str r3, [r2, #32] } } if (sensorsInfo.motorYStatus == 1) { 8002512: 4b28 ldr r3, [pc, #160] @ (80025b4 ) 8002514: 7d5b ldrb r3, [r3, #21] 8002516: 2b01 cmp r3, #1 8002518: d111 bne.n 800253e sensorsInfo.motorYAveCurrent = motorYAveCurrent; 800251a: 4a26 ldr r2, [pc, #152] @ (80025b4 ) 800251c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8002520: 61d3 str r3, [r2, #28] if (sensorsInfo.motorYPeakCurrent < motorYCurrentSense) { 8002522: 4b24 ldr r3, [pc, #144] @ (80025b4 ) 8002524: edd3 7a09 vldr s15, [r3, #36] @ 0x24 8002528: ed97 7a33 vldr s14, [r7, #204] @ 0xcc 800252c: eeb4 7ae7 vcmpe.f32 s14, s15 8002530: eef1 fa10 vmrs APSR_nzcv, fpscr 8002534: dd03 ble.n 800253e sensorsInfo.motorYPeakCurrent = motorYCurrentSense; 8002536: 4a1f ldr r2, [pc, #124] @ (80025b4 ) 8002538: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc 800253c: 6253 str r3, [r2, #36] @ 0x24 } } sensorsInfo.pvTemperature[0] = pvT1AveTemp; 800253e: 4a1d ldr r2, [pc, #116] @ (80025b4 ) 8002540: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8002544: 6013 str r3, [r2, #0] sensorsInfo.pvTemperature[1] = pvT2AveTemp; 8002546: 4a1b ldr r2, [pc, #108] @ (80025b4 ) 8002548: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 800254c: 6053 str r3, [r2, #4] osMutexRelease (sensorsInfoMutex); 800254e: 4b18 ldr r3, [pc, #96] @ (80025b0 ) 8002550: 681b ldr r3, [r3, #0] 8002552: 4618 mov r0, r3 8002554: f011 fa7a bl 8013a4c } ++circBuffPos; 8002558: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 800255c: 3301 adds r3, #1 800255e: f8c7 30ec str.w r3, [r7, #236] @ 0xec circBuffPos = circBuffPos % CIRC_BUFF_LEN; 8002562: f8d7 20ec ldr.w r2, [r7, #236] @ 0xec 8002566: 4b14 ldr r3, [pc, #80] @ (80025b8 ) 8002568: fba3 1302 umull r1, r3, r3, r2 800256c: 08d9 lsrs r1, r3, #3 800256e: 460b mov r3, r1 8002570: 009b lsls r3, r3, #2 8002572: 440b add r3, r1 8002574: 005b lsls r3, r3, #1 8002576: 1ad3 subs r3, r2, r3 8002578: f8c7 30ec str.w r3, [r7, #236] @ 0xec while (pdTRUE) { 800257c: e68a b.n 8002294 800257e: bf00 nop 8002580: 00000000 .word 0x00000000 8002584: 40efffe0 .word 0x40efffe0 8002588: 3ad18d26 .word 0x3ad18d26 800258c: 4020aaaa .word 0x4020aaaa 8002590: aaa38226 .word 0xaaa38226 8002594: 4046aaaa .word 0x4046aaaa 8002598: 00000000 .word 0x00000000 800259c: 404f8000 .word 0x404f8000 80025a0: 240008d0 .word 0x240008d0 80025a4: 1ff1e860 .word 0x1ff1e860 80025a8: 240008d4 .word 0x240008d4 80025ac: 24000030 .word 0x24000030 80025b0: 240008dc .word 0x240008dc 80025b4: 24000940 .word 0x24000940 80025b8: cccccccd .word 0xcccccccd 080025bc : } } void LimiterSwitchTask (void* arg) { 80025bc: b580 push {r7, lr} 80025be: b08c sub sp, #48 @ 0x30 80025c0: af06 add r7, sp, #24 80025c2: 6078 str r0, [r7, #4] uint8_t limitXSwitchDownPrevState = 0; 80025c4: 2300 movs r3, #0 80025c6: 75fb strb r3, [r7, #23] uint8_t limitXSwitchCenterPrevState = 0; 80025c8: 2300 movs r3, #0 80025ca: 75bb strb r3, [r7, #22] uint8_t limitXSwitchUpPrevState = 0; 80025cc: 2300 movs r3, #0 80025ce: 757b strb r3, [r7, #21] uint8_t limitYSwitchDownPrevState = 0; 80025d0: 2300 movs r3, #0 80025d2: 753b strb r3, [r7, #20] uint8_t limitYSwitchCenterPrevState = 0; 80025d4: 2300 movs r3, #0 80025d6: 74fb strb r3, [r7, #19] uint8_t limitYSwitchUpPrevState = 0; 80025d8: 2300 movs r3, #0 80025da: 74bb strb r3, [r7, #18] uint8_t pinStates = 0; 80025dc: 2300 movs r3, #0 80025de: 73fb strb r3, [r7, #15] uint8_t limiterXTriggered = 0; 80025e0: 2300 movs r3, #0 80025e2: 747b strb r3, [r7, #17] uint8_t limiterYTriggered = 0; 80025e4: 2300 movs r3, #0 80025e6: 743b strb r3, [r7, #16] if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80025e8: 4bad ldr r3, [pc, #692] @ (80028a0 ) 80025ea: 681b ldr r3, [r3, #0] 80025ec: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80025f0: 4618 mov r0, r3 80025f2: f011 f9e0 bl 80139b6 80025f6: 4603 mov r3, r0 80025f8: 2b00 cmp r3, #0 80025fa: d10c bne.n 8002616 sensorsInfo.positionXWeak = 1; 80025fc: 4ba9 ldr r3, [pc, #676] @ (80028a4 ) 80025fe: 2201 movs r2, #1 8002600: f883 2038 strb.w r2, [r3, #56] @ 0x38 sensorsInfo.positionYWeak = 1; 8002604: 4ba7 ldr r3, [pc, #668] @ (80028a4 ) 8002606: 2201 movs r2, #1 8002608: f883 2039 strb.w r2, [r3, #57] @ 0x39 osMutexRelease (sensorsInfoMutex); 800260c: 4ba4 ldr r3, [pc, #656] @ (80028a0 ) 800260e: 681b ldr r3, [r3, #0] 8002610: 4618 mov r0, r3 8002612: f011 fa1b bl 8013a4c } while (pdTRUE) { osDelay (pdMS_TO_TICKS (100)); 8002616: 2064 movs r0, #100 @ 0x64 8002618: f011 f835 bl 8013686 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800261c: 4ba0 ldr r3, [pc, #640] @ (80028a0 ) 800261e: 681b ldr r3, [r3, #0] 8002620: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002624: 4618 mov r0, r3 8002626: f011 f9c6 bl 80139b6 800262a: 4603 mov r3, r0 800262c: 2b00 cmp r3, #0 800262e: d1f2 bne.n 8002616 sensorsInfo.limitXSwitchDown = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_12); 8002630: f44f 5180 mov.w r1, #4096 @ 0x1000 8002634: 489c ldr r0, [pc, #624] @ (80028a8 ) 8002636: f008 fdab bl 800b190 800263a: 4603 mov r3, r0 800263c: 461a mov r2, r3 800263e: 4b99 ldr r3, [pc, #612] @ (80028a4 ) 8002640: f883 2029 strb.w r2, [r3, #41] @ 0x29 pinStates = (limitXSwitchDownPrevState << 1) | sensorsInfo.limitXSwitchDown; 8002644: 7dfb ldrb r3, [r7, #23] 8002646: 005b lsls r3, r3, #1 8002648: b25a sxtb r2, r3 800264a: 4b96 ldr r3, [pc, #600] @ (80028a4 ) 800264c: f893 3029 ldrb.w r3, [r3, #41] @ 0x29 8002650: b25b sxtb r3, r3 8002652: 4313 orrs r3, r2 8002654: b25b sxtb r3, r3 8002656: 73fb strb r3, [r7, #15] if ((pinStates & 0x3) == 0x1) { 8002658: 7bfb ldrb r3, [r7, #15] 800265a: f003 0303 and.w r3, r3, #3 800265e: 2b01 cmp r3, #1 8002660: d109 bne.n 8002676 limiterXTriggered = 1; 8002662: 2301 movs r3, #1 8002664: 747b strb r3, [r7, #17] sensorsInfo.currentXPosition = 0; 8002666: 4b8f ldr r3, [pc, #572] @ (80028a4 ) 8002668: f04f 0200 mov.w r2, #0 800266c: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 800266e: 4b8d ldr r3, [pc, #564] @ (80028a4 ) 8002670: 2200 movs r2, #0 8002672: f883 2038 strb.w r2, [r3, #56] @ 0x38 } limitXSwitchDownPrevState = sensorsInfo.limitXSwitchDown; 8002676: 4b8b ldr r3, [pc, #556] @ (80028a4 ) 8002678: f893 3029 ldrb.w r3, [r3, #41] @ 0x29 800267c: 75fb strb r3, [r7, #23] sensorsInfo.limitXSwitchUp = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_13); 800267e: f44f 5100 mov.w r1, #8192 @ 0x2000 8002682: 4889 ldr r0, [pc, #548] @ (80028a8 ) 8002684: f008 fd84 bl 800b190 8002688: 4603 mov r3, r0 800268a: 461a mov r2, r3 800268c: 4b85 ldr r3, [pc, #532] @ (80028a4 ) 800268e: f883 2028 strb.w r2, [r3, #40] @ 0x28 pinStates = (limitXSwitchUpPrevState << 1) | sensorsInfo.limitXSwitchUp; 8002692: 7d7b ldrb r3, [r7, #21] 8002694: 005b lsls r3, r3, #1 8002696: b25a sxtb r2, r3 8002698: 4b82 ldr r3, [pc, #520] @ (80028a4 ) 800269a: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 800269e: b25b sxtb r3, r3 80026a0: 4313 orrs r3, r2 80026a2: b25b sxtb r3, r3 80026a4: 73fb strb r3, [r7, #15] if ((pinStates & 0x3) == 0x1) { 80026a6: 7bfb ldrb r3, [r7, #15] 80026a8: f003 0303 and.w r3, r3, #3 80026ac: 2b01 cmp r3, #1 80026ae: d108 bne.n 80026c2 limiterXTriggered = 1; 80026b0: 2301 movs r3, #1 80026b2: 747b strb r3, [r7, #17] sensorsInfo.currentXPosition = 100; 80026b4: 4b7b ldr r3, [pc, #492] @ (80028a4 ) 80026b6: 4a7d ldr r2, [pc, #500] @ (80028ac ) 80026b8: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 80026ba: 4b7a ldr r3, [pc, #488] @ (80028a4 ) 80026bc: 2200 movs r2, #0 80026be: f883 2038 strb.w r2, [r3, #56] @ 0x38 } limitXSwitchUpPrevState = sensorsInfo.limitXSwitchUp; 80026c2: 4b78 ldr r3, [pc, #480] @ (80028a4 ) 80026c4: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80026c8: 757b strb r3, [r7, #21] sensorsInfo.limitXSwitchCenter = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_10); 80026ca: f44f 6180 mov.w r1, #1024 @ 0x400 80026ce: 4876 ldr r0, [pc, #472] @ (80028a8 ) 80026d0: f008 fd5e bl 800b190 80026d4: 4603 mov r3, r0 80026d6: 461a mov r2, r3 80026d8: 4b72 ldr r3, [pc, #456] @ (80028a4 ) 80026da: f883 202a strb.w r2, [r3, #42] @ 0x2a pinStates = (limitXSwitchCenterPrevState << 1) | sensorsInfo.limitXSwitchCenter; 80026de: 7dbb ldrb r3, [r7, #22] 80026e0: 005b lsls r3, r3, #1 80026e2: b25a sxtb r2, r3 80026e4: 4b6f ldr r3, [pc, #444] @ (80028a4 ) 80026e6: f893 302a ldrb.w r3, [r3, #42] @ 0x2a 80026ea: b25b sxtb r3, r3 80026ec: 4313 orrs r3, r2 80026ee: b25b sxtb r3, r3 80026f0: 73fb strb r3, [r7, #15] if ((pinStates & 0x3) == 0x1) { 80026f2: 7bfb ldrb r3, [r7, #15] 80026f4: f003 0303 and.w r3, r3, #3 80026f8: 2b01 cmp r3, #1 80026fa: d106 bne.n 800270a sensorsInfo.currentXPosition = AXE_X_MIDDLE_VALUE; 80026fc: 4b69 ldr r3, [pc, #420] @ (80028a4 ) 80026fe: 4a6c ldr r2, [pc, #432] @ (80028b0 ) 8002700: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8002702: 4b68 ldr r3, [pc, #416] @ (80028a4 ) 8002704: 2200 movs r2, #0 8002706: f883 2038 strb.w r2, [r3, #56] @ 0x38 } limitXSwitchCenterPrevState = sensorsInfo.limitXSwitchCenter; 800270a: 4b66 ldr r3, [pc, #408] @ (80028a4 ) 800270c: f893 302a ldrb.w r3, [r3, #42] @ 0x2a 8002710: 75bb strb r3, [r7, #22] sensorsInfo.limitYSwitchDown = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_11); 8002712: f44f 6100 mov.w r1, #2048 @ 0x800 8002716: 4864 ldr r0, [pc, #400] @ (80028a8 ) 8002718: f008 fd3a bl 800b190 800271c: 4603 mov r3, r0 800271e: 461a mov r2, r3 8002720: 4b60 ldr r3, [pc, #384] @ (80028a4 ) 8002722: f883 202c strb.w r2, [r3, #44] @ 0x2c pinStates = (limitYSwitchDownPrevState << 1) | sensorsInfo.limitYSwitchDown; 8002726: 7d3b ldrb r3, [r7, #20] 8002728: 005b lsls r3, r3, #1 800272a: b25a sxtb r2, r3 800272c: 4b5d ldr r3, [pc, #372] @ (80028a4 ) 800272e: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 8002732: b25b sxtb r3, r3 8002734: 4313 orrs r3, r2 8002736: b25b sxtb r3, r3 8002738: 73fb strb r3, [r7, #15] if ((pinStates & 0x3) == 0x1) { 800273a: 7bfb ldrb r3, [r7, #15] 800273c: f003 0303 and.w r3, r3, #3 8002740: 2b01 cmp r3, #1 8002742: d109 bne.n 8002758 limiterYTriggered = 1; 8002744: 2301 movs r3, #1 8002746: 743b strb r3, [r7, #16] sensorsInfo.currentYPosition = 0; 8002748: 4b56 ldr r3, [pc, #344] @ (80028a4 ) 800274a: f04f 0200 mov.w r2, #0 800274e: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8002750: 4b54 ldr r3, [pc, #336] @ (80028a4 ) 8002752: 2200 movs r2, #0 8002754: f883 2039 strb.w r2, [r3, #57] @ 0x39 } limitYSwitchDownPrevState = sensorsInfo.limitYSwitchDown; 8002758: 4b52 ldr r3, [pc, #328] @ (80028a4 ) 800275a: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 800275e: 753b strb r3, [r7, #20] sensorsInfo.limitYSwitchUp = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_9); 8002760: f44f 7100 mov.w r1, #512 @ 0x200 8002764: 4850 ldr r0, [pc, #320] @ (80028a8 ) 8002766: f008 fd13 bl 800b190 800276a: 4603 mov r3, r0 800276c: 461a mov r2, r3 800276e: 4b4d ldr r3, [pc, #308] @ (80028a4 ) 8002770: f883 202b strb.w r2, [r3, #43] @ 0x2b pinStates = (limitYSwitchUpPrevState << 1) | sensorsInfo.limitYSwitchUp; 8002774: 7cbb ldrb r3, [r7, #18] 8002776: 005b lsls r3, r3, #1 8002778: b25a sxtb r2, r3 800277a: 4b4a ldr r3, [pc, #296] @ (80028a4 ) 800277c: f893 302b ldrb.w r3, [r3, #43] @ 0x2b 8002780: b25b sxtb r3, r3 8002782: 4313 orrs r3, r2 8002784: b25b sxtb r3, r3 8002786: 73fb strb r3, [r7, #15] if ((pinStates & 0x3) == 0x1) { 8002788: 7bfb ldrb r3, [r7, #15] 800278a: f003 0303 and.w r3, r3, #3 800278e: 2b01 cmp r3, #1 8002790: d108 bne.n 80027a4 limiterYTriggered = 1; 8002792: 2301 movs r3, #1 8002794: 743b strb r3, [r7, #16] sensorsInfo.currentYPosition = 100; 8002796: 4b43 ldr r3, [pc, #268] @ (80028a4 ) 8002798: 4a44 ldr r2, [pc, #272] @ (80028ac ) 800279a: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 800279c: 4b41 ldr r3, [pc, #260] @ (80028a4 ) 800279e: 2200 movs r2, #0 80027a0: f883 2039 strb.w r2, [r3, #57] @ 0x39 } limitYSwitchUpPrevState = sensorsInfo.limitYSwitchUp; 80027a4: 4b3f ldr r3, [pc, #252] @ (80028a4 ) 80027a6: f893 302b ldrb.w r3, [r3, #43] @ 0x2b 80027aa: 74bb strb r3, [r7, #18] sensorsInfo.limitYSwitchCenter = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_8); 80027ac: f44f 7180 mov.w r1, #256 @ 0x100 80027b0: 483d ldr r0, [pc, #244] @ (80028a8 ) 80027b2: f008 fced bl 800b190 80027b6: 4603 mov r3, r0 80027b8: 461a mov r2, r3 80027ba: 4b3a ldr r3, [pc, #232] @ (80028a4 ) 80027bc: f883 202d strb.w r2, [r3, #45] @ 0x2d pinStates = (limitYSwitchCenterPrevState << 1) | sensorsInfo.limitYSwitchCenter; 80027c0: 7cfb ldrb r3, [r7, #19] 80027c2: 005b lsls r3, r3, #1 80027c4: b25a sxtb r2, r3 80027c6: 4b37 ldr r3, [pc, #220] @ (80028a4 ) 80027c8: f893 302d ldrb.w r3, [r3, #45] @ 0x2d 80027cc: b25b sxtb r3, r3 80027ce: 4313 orrs r3, r2 80027d0: b25b sxtb r3, r3 80027d2: 73fb strb r3, [r7, #15] if ((pinStates & 0x3) == 0x1) { 80027d4: 7bfb ldrb r3, [r7, #15] 80027d6: f003 0303 and.w r3, r3, #3 80027da: 2b01 cmp r3, #1 80027dc: d106 bne.n 80027ec sensorsInfo.currentYPosition = AXE_Y_MIDDLE_VALUE; 80027de: 4b31 ldr r3, [pc, #196] @ (80028a4 ) 80027e0: 4a33 ldr r2, [pc, #204] @ (80028b0 ) 80027e2: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 80027e4: 4b2f ldr r3, [pc, #188] @ (80028a4 ) 80027e6: 2200 movs r2, #0 80027e8: f883 2039 strb.w r2, [r3, #57] @ 0x39 } limitYSwitchCenterPrevState = sensorsInfo.limitYSwitchCenter; 80027ec: 4b2d ldr r3, [pc, #180] @ (80028a4 ) 80027ee: f893 302d ldrb.w r3, [r3, #45] @ 0x2d 80027f2: 74fb strb r3, [r7, #19] if (((sensorsInfo.limitXSwitchDown == 1) || (sensorsInfo.limitXSwitchUp == 1)) && (limiterXTriggered == 1)) { 80027f4: 4b2b ldr r3, [pc, #172] @ (80028a4 ) 80027f6: f893 3029 ldrb.w r3, [r3, #41] @ 0x29 80027fa: 2b01 cmp r3, #1 80027fc: d004 beq.n 8002808 80027fe: 4b29 ldr r3, [pc, #164] @ (80028a4 ) 8002800: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8002804: 2b01 cmp r3, #1 8002806: d11b bne.n 8002840 8002808: 7c7b ldrb r3, [r7, #17] 800280a: 2b01 cmp r3, #1 800280c: d118 bne.n 8002840 sensorsInfo.motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, 0, 0, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 800280e: 4b29 ldr r3, [pc, #164] @ (80028b4 ) 8002810: 681b ldr r3, [r3, #0] 8002812: 4a24 ldr r2, [pc, #144] @ (80028a4 ) 8002814: f892 2028 ldrb.w r2, [r2, #40] @ 0x28 8002818: 4922 ldr r1, [pc, #136] @ (80028a4 ) 800281a: f891 1029 ldrb.w r1, [r1, #41] @ 0x29 800281e: 9104 str r1, [sp, #16] 8002820: 9203 str r2, [sp, #12] 8002822: 2200 movs r2, #0 8002824: 9202 str r2, [sp, #8] 8002826: 2200 movs r2, #0 8002828: 9201 str r2, [sp, #4] 800282a: 9300 str r3, [sp, #0] 800282c: 2304 movs r3, #4 800282e: 2200 movs r2, #0 8002830: 4921 ldr r1, [pc, #132] @ (80028b8 ) 8002832: 4822 ldr r0, [pc, #136] @ (80028bc ) 8002834: f000 f98e bl 8002b54 8002838: 4603 mov r3, r0 800283a: 461a mov r2, r3 800283c: 4b19 ldr r3, [pc, #100] @ (80028a4 ) 800283e: 751a strb r2, [r3, #20] } if (((sensorsInfo.limitYSwitchDown == 1) || (sensorsInfo.limitYSwitchUp == 1)) && (limiterYTriggered == 1)) { 8002840: 4b18 ldr r3, [pc, #96] @ (80028a4 ) 8002842: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 8002846: 2b01 cmp r3, #1 8002848: d004 beq.n 8002854 800284a: 4b16 ldr r3, [pc, #88] @ (80028a4 ) 800284c: f893 302b ldrb.w r3, [r3, #43] @ 0x2b 8002850: 2b01 cmp r3, #1 8002852: d11b bne.n 800288c 8002854: 7c3b ldrb r3, [r7, #16] 8002856: 2b01 cmp r3, #1 8002858: d118 bne.n 800288c sensorsInfo.motorYStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, 0, 0, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 800285a: 4b19 ldr r3, [pc, #100] @ (80028c0 ) 800285c: 681b ldr r3, [r3, #0] 800285e: 4a11 ldr r2, [pc, #68] @ (80028a4 ) 8002860: f892 202b ldrb.w r2, [r2, #43] @ 0x2b 8002864: 490f ldr r1, [pc, #60] @ (80028a4 ) 8002866: f891 102c ldrb.w r1, [r1, #44] @ 0x2c 800286a: 9104 str r1, [sp, #16] 800286c: 9203 str r2, [sp, #12] 800286e: 2200 movs r2, #0 8002870: 9202 str r2, [sp, #8] 8002872: 2200 movs r2, #0 8002874: 9201 str r2, [sp, #4] 8002876: 9300 str r3, [sp, #0] 8002878: 230c movs r3, #12 800287a: 2208 movs r2, #8 800287c: 490e ldr r1, [pc, #56] @ (80028b8 ) 800287e: 480f ldr r0, [pc, #60] @ (80028bc ) 8002880: f000 f968 bl 8002b54 8002884: 4603 mov r3, r0 8002886: 461a mov r2, r3 8002888: 4b06 ldr r3, [pc, #24] @ (80028a4 ) 800288a: 755a strb r2, [r3, #21] } limiterXTriggered = 0; 800288c: 2300 movs r3, #0 800288e: 747b strb r3, [r7, #17] limiterYTriggered = 0; 8002890: 2300 movs r3, #0 8002892: 743b strb r3, [r7, #16] osMutexRelease (sensorsInfoMutex); 8002894: 4b02 ldr r3, [pc, #8] @ (80028a0 ) 8002896: 681b ldr r3, [r3, #0] 8002898: 4618 mov r0, r3 800289a: f011 f8d7 bl 8013a4c osDelay (pdMS_TO_TICKS (100)); 800289e: e6ba b.n 8002616 80028a0: 240008dc .word 0x240008dc 80028a4: 24000940 .word 0x24000940 80028a8: 58020c00 .word 0x58020c00 80028ac: 42c80000 .word 0x42c80000 80028b0: 42480000 .word 0x42480000 80028b4: 2400080c .word 0x2400080c 80028b8: 24000888 .word 0x24000888 80028bc: 240005e8 .word 0x240005e8 80028c0: 2400083c .word 0x2400083c 080028c4 : } } } void EncoderTask (void* arg) { 80028c4: b590 push {r4, r7, lr} 80028c6: b08b sub sp, #44 @ 0x2c 80028c8: af00 add r7, sp, #0 80028ca: 6078 str r0, [r7, #4] // 01 11 10 00 const uint32_t encoderStates[4] = { 0x00, 0x01, 0x03, 0x02 }; 80028cc: 4b55 ldr r3, [pc, #340] @ (8002a24 ) 80028ce: f107 040c add.w r4, r7, #12 80028d2: cb0f ldmia r3, {r0, r1, r2, r3} 80028d4: e884 000f stmia.w r4, {r0, r1, r2, r3} uint8_t step = 0; 80028d8: 2300 movs r3, #0 80028da: f887 3027 strb.w r3, [r7, #39] @ 0x27 EncoderTaskArg* encoderTaskArg = (EncoderTaskArg*)arg; 80028de: 687b ldr r3, [r7, #4] 80028e0: 61fb str r3, [r7, #28] uint32_t pinStates = encoderTaskArg->initPinStates; 80028e2: 69fb ldr r3, [r7, #28] 80028e4: 68db ldr r3, [r3, #12] 80028e6: 60bb str r3, [r7, #8] for (uint8_t i = 0; i < 4; i++) { 80028e8: 2300 movs r3, #0 80028ea: f887 3026 strb.w r3, [r7, #38] @ 0x26 80028ee: e014 b.n 800291a if (pinStates == encoderStates[i]) { 80028f0: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 80028f4: 009b lsls r3, r3, #2 80028f6: 3328 adds r3, #40 @ 0x28 80028f8: 443b add r3, r7 80028fa: f853 2c1c ldr.w r2, [r3, #-28] 80028fe: 68bb ldr r3, [r7, #8] 8002900: 429a cmp r2, r3 8002902: d105 bne.n 8002910 step = i; 8002904: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 8002908: f887 3027 strb.w r3, [r7, #39] @ 0x27 break; 800290c: bf00 nop 800290e: e008 b.n 8002922 for (uint8_t i = 0; i < 4; i++) { 8002910: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 8002914: 3301 adds r3, #1 8002916: f887 3026 strb.w r3, [r7, #38] @ 0x26 800291a: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 800291e: 2b03 cmp r3, #3 8002920: d9e6 bls.n 80028f0 } } while (pdTRUE) { osMessageQueueGet (encoderTaskArg->dataQueue, &pinStates, 0, osWaitForever); 8002922: 69fb ldr r3, [r7, #28] 8002924: 6918 ldr r0, [r3, #16] 8002926: f107 0108 add.w r1, r7, #8 800292a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800292e: 2200 movs r2, #0 8002930: f011 f99c bl 8013c6c float encoderValue = *encoderTaskArg->pvEncoder; 8002934: 69fb ldr r3, [r7, #28] 8002936: 689b ldr r3, [r3, #8] 8002938: 681b ldr r3, [r3, #0] 800293a: 623b str r3, [r7, #32] if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800293c: 4b3a ldr r3, [pc, #232] @ (8002a28 ) 800293e: 681b ldr r3, [r3, #0] 8002940: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002944: 4618 mov r0, r3 8002946: f011 f836 bl 80139b6 800294a: 4603 mov r3, r0 800294c: 2b00 cmp r3, #0 800294e: d161 bne.n 8002a14 if (encoderStates[(step + 1) % 4] == pinStates) { 8002950: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8002954: 3301 adds r3, #1 8002956: 425a negs r2, r3 8002958: f003 0303 and.w r3, r3, #3 800295c: f002 0203 and.w r2, r2, #3 8002960: bf58 it pl 8002962: 4253 negpl r3, r2 8002964: 009b lsls r3, r3, #2 8002966: 3328 adds r3, #40 @ 0x28 8002968: 443b add r3, r7 800296a: f853 2c1c ldr.w r2, [r3, #-28] 800296e: 68bb ldr r3, [r7, #8] 8002970: 429a cmp r2, r3 8002972: d10d bne.n 8002990 step++; 8002974: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8002978: 3301 adds r3, #1 800297a: f887 3027 strb.w r3, [r7, #39] @ 0x27 encoderValue++; 800297e: edd7 7a08 vldr s15, [r7, #32] 8002982: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8002986: ee77 7a87 vadd.f32 s15, s15, s14 800298a: edc7 7a08 vstr s15, [r7, #32] 800298e: e022 b.n 80029d6 // encoderValue += 360.0 / ENCODER_X_IMP_PER_TURN; // printf ("Forward\n"); } else if (encoderStates[(step - 1) % 4] == pinStates) { 8002990: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8002994: 3b01 subs r3, #1 8002996: 425a negs r2, r3 8002998: f003 0303 and.w r3, r3, #3 800299c: f002 0203 and.w r2, r2, #3 80029a0: bf58 it pl 80029a2: 4253 negpl r3, r2 80029a4: 009b lsls r3, r3, #2 80029a6: 3328 adds r3, #40 @ 0x28 80029a8: 443b add r3, r7 80029aa: f853 2c1c ldr.w r2, [r3, #-28] 80029ae: 68bb ldr r3, [r7, #8] 80029b0: 429a cmp r2, r3 80029b2: d10d bne.n 80029d0 encoderValue--; 80029b4: edd7 7a08 vldr s15, [r7, #32] 80029b8: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 80029bc: ee77 7ac7 vsub.f32 s15, s15, s14 80029c0: edc7 7a08 vstr s15, [r7, #32] // encoderValue -= 360.0 / ENCODER_X_IMP_PER_TURN; // if (encoderValue < 0) { // encoderValue = 360.0 + encoderValue; // } // printf ("Reverse\n"); step--; 80029c4: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 80029c8: 3b01 subs r3, #1 80029ca: f887 3027 strb.w r3, [r7, #39] @ 0x27 80029ce: e002 b.n 80029d6 } else { printf ("Forbidden\n"); 80029d0: 4816 ldr r0, [pc, #88] @ (8002a2c ) 80029d2: f015 fc69 bl 80182a8 } step = step % 4; 80029d6: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 80029da: f003 0303 and.w r3, r3, #3 80029de: f887 3027 strb.w r3, [r7, #39] @ 0x27 // *encoderTaskArg->pvEncoder = fmodf (encoderValue, 360.0); *encoderTaskArg->pvEncoder = encoderValue; 80029e2: 69fb ldr r3, [r7, #28] 80029e4: 689b ldr r3, [r3, #8] 80029e6: 6a3a ldr r2, [r7, #32] 80029e8: 601a str r2, [r3, #0] *encoderTaskArg->currentPosition = 100 * (*encoderTaskArg->pvEncoder) / MAX_X_AXE_ANGLE; 80029ea: 69fb ldr r3, [r7, #28] 80029ec: 689b ldr r3, [r3, #8] 80029ee: edd3 7a00 vldr s15, [r3] 80029f2: ed9f 7a0f vldr s14, [pc, #60] @ 8002a30 80029f6: ee27 7a87 vmul.f32 s14, s15, s14 80029fa: 69fb ldr r3, [r7, #28] 80029fc: 685b ldr r3, [r3, #4] 80029fe: eddf 6a0d vldr s13, [pc, #52] @ 8002a34 8002a02: eec7 7a26 vdiv.f32 s15, s14, s13 8002a06: edc3 7a00 vstr s15, [r3] osMutexRelease (sensorsInfoMutex); 8002a0a: 4b07 ldr r3, [pc, #28] @ (8002a28 ) 8002a0c: 681b ldr r3, [r3, #0] 8002a0e: 4618 mov r0, r3 8002a10: f011 f81c bl 8013a4c } DbgLEDToggle (encoderTaskArg->dbgLed); 8002a14: 69fb ldr r3, [r7, #28] 8002a16: 881b ldrh r3, [r3, #0] 8002a18: b2db uxtb r3, r3 8002a1a: 4618 mov r0, r3 8002a1c: f000 f830 bl 8002a80 while (pdTRUE) { 8002a20: e77f b.n 8002922 8002a22: bf00 nop 8002a24: 0801a1fc .word 0x0801a1fc 8002a28: 240008dc .word 0x240008dc 8002a2c: 0801a1f0 .word 0x0801a1f0 8002a30: 42c80000 .word 0x42c80000 8002a34: 43b40000 .word 0x43b40000 08002a38 : #include #include "peripherial.h" void DbgLEDOn (uint8_t ledNumber) { 8002a38: b580 push {r7, lr} 8002a3a: b082 sub sp, #8 8002a3c: af00 add r7, sp, #0 8002a3e: 4603 mov r3, r0 8002a40: 71fb strb r3, [r7, #7] HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_SET); 8002a42: 79fb ldrb r3, [r7, #7] 8002a44: b29b uxth r3, r3 8002a46: 2201 movs r2, #1 8002a48: 4619 mov r1, r3 8002a4a: 4803 ldr r0, [pc, #12] @ (8002a58 ) 8002a4c: f008 fbb8 bl 800b1c0 } 8002a50: bf00 nop 8002a52: 3708 adds r7, #8 8002a54: 46bd mov sp, r7 8002a56: bd80 pop {r7, pc} 8002a58: 58020c00 .word 0x58020c00 08002a5c : void DbgLEDOff (uint8_t ledNumber) { 8002a5c: b580 push {r7, lr} 8002a5e: b082 sub sp, #8 8002a60: af00 add r7, sp, #0 8002a62: 4603 mov r3, r0 8002a64: 71fb strb r3, [r7, #7] HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_RESET); 8002a66: 79fb ldrb r3, [r7, #7] 8002a68: b29b uxth r3, r3 8002a6a: 2200 movs r2, #0 8002a6c: 4619 mov r1, r3 8002a6e: 4803 ldr r0, [pc, #12] @ (8002a7c ) 8002a70: f008 fba6 bl 800b1c0 } 8002a74: bf00 nop 8002a76: 3708 adds r7, #8 8002a78: 46bd mov sp, r7 8002a7a: bd80 pop {r7, pc} 8002a7c: 58020c00 .word 0x58020c00 08002a80 : void DbgLEDToggle (uint8_t ledNumber) { 8002a80: b580 push {r7, lr} 8002a82: b082 sub sp, #8 8002a84: af00 add r7, sp, #0 8002a86: 4603 mov r3, r0 8002a88: 71fb strb r3, [r7, #7] HAL_GPIO_TogglePin (GPIOD, ledNumber); 8002a8a: 79fb ldrb r3, [r7, #7] 8002a8c: b29b uxth r3, r3 8002a8e: 4619 mov r1, r3 8002a90: 4803 ldr r0, [pc, #12] @ (8002aa0 ) 8002a92: f008 fbae bl 800b1f2 } 8002a96: bf00 nop 8002a98: 3708 adds r7, #8 8002a9a: 46bd mov sp, r7 8002a9c: bd80 pop {r7, pc} 8002a9e: bf00 nop 8002aa0: 58020c00 .word 0x58020c00 08002aa4 : void EnableCurrentSensors (void) { 8002aa4: b580 push {r7, lr} 8002aa6: af00 add r7, sp, #0 HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_SET); 8002aa8: 2201 movs r2, #1 8002aaa: f44f 4100 mov.w r1, #32768 @ 0x8000 8002aae: 4802 ldr r0, [pc, #8] @ (8002ab8 ) 8002ab0: f008 fb86 bl 800b1c0 } 8002ab4: bf00 nop 8002ab6: bd80 pop {r7, pc} 8002ab8: 58021000 .word 0x58021000 08002abc : void DisableCurrentSensors (void) { HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_RESET); } void SelectCurrentSensorGain (CurrentSensor sensor, CurrentSensorGain gain) { 8002abc: b580 push {r7, lr} 8002abe: b084 sub sp, #16 8002ac0: af00 add r7, sp, #0 8002ac2: 4603 mov r3, r0 8002ac4: 460a mov r2, r1 8002ac6: 71fb strb r3, [r7, #7] 8002ac8: 4613 mov r3, r2 8002aca: 71bb strb r3, [r7, #6] uint8_t gpioOffset = 0; 8002acc: 2300 movs r3, #0 8002ace: 73fb strb r3, [r7, #15] switch (sensor) { 8002ad0: 79fb ldrb r3, [r7, #7] 8002ad2: 2b02 cmp r3, #2 8002ad4: d00c beq.n 8002af0 8002ad6: 2b02 cmp r3, #2 8002ad8: dc0d bgt.n 8002af6 8002ada: 2b00 cmp r3, #0 8002adc: d002 beq.n 8002ae4 8002ade: 2b01 cmp r3, #1 8002ae0: d003 beq.n 8002aea case CurrentSensorL1: gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET; break; case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break; case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break; default: break; 8002ae2: e008 b.n 8002af6 case CurrentSensorL1: gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET; break; 8002ae4: 2307 movs r3, #7 8002ae6: 73fb strb r3, [r7, #15] 8002ae8: e006 b.n 8002af8 case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break; 8002aea: 2309 movs r3, #9 8002aec: 73fb strb r3, [r7, #15] 8002aee: e003 b.n 8002af8 case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break; 8002af0: 230d movs r3, #13 8002af2: 73fb strb r3, [r7, #15] 8002af4: e000 b.n 8002af8 default: break; 8002af6: bf00 nop } if (gpioOffset > 0) { 8002af8: 7bfb ldrb r3, [r7, #15] 8002afa: 2b00 cmp r3, #0 8002afc: d023 beq.n 8002b46 uint16_t gain0Gpio = 1 << gpioOffset; 8002afe: 7bfb ldrb r3, [r7, #15] 8002b00: 2201 movs r2, #1 8002b02: fa02 f303 lsl.w r3, r2, r3 8002b06: 81bb strh r3, [r7, #12] uint16_t gain1Gpio = 1 << (gpioOffset + 1); 8002b08: 7bfb ldrb r3, [r7, #15] 8002b0a: 3301 adds r3, #1 8002b0c: 2201 movs r2, #1 8002b0e: fa02 f303 lsl.w r3, r2, r3 8002b12: 817b strh r3, [r7, #10] uint16_t gpioState = ((uint16_t)gain) & 0x0001; 8002b14: 79bb ldrb r3, [r7, #6] 8002b16: b29b uxth r3, r3 8002b18: f003 0301 and.w r3, r3, #1 8002b1c: 813b strh r3, [r7, #8] HAL_GPIO_WritePin (GPIOE, gain0Gpio, gpioState); 8002b1e: 893b ldrh r3, [r7, #8] 8002b20: b2da uxtb r2, r3 8002b22: 89bb ldrh r3, [r7, #12] 8002b24: 4619 mov r1, r3 8002b26: 480a ldr r0, [pc, #40] @ (8002b50 ) 8002b28: f008 fb4a bl 800b1c0 gpioState = (((uint16_t)gain) >> 1) & 0x0001; 8002b2c: 79bb ldrb r3, [r7, #6] 8002b2e: 085b lsrs r3, r3, #1 8002b30: b2db uxtb r3, r3 8002b32: f003 0301 and.w r3, r3, #1 8002b36: 813b strh r3, [r7, #8] HAL_GPIO_WritePin (GPIOE, gain1Gpio, gpioState); 8002b38: 893b ldrh r3, [r7, #8] 8002b3a: b2da uxtb r2, r3 8002b3c: 897b ldrh r3, [r7, #10] 8002b3e: 4619 mov r1, r3 8002b40: 4803 ldr r0, [pc, #12] @ (8002b50 ) 8002b42: f008 fb3d bl 800b1c0 } } 8002b46: bf00 nop 8002b48: 3710 adds r7, #16 8002b4a: 46bd mov sp, r7 8002b4c: bd80 pop {r7, pc} 8002b4e: bf00 nop 8002b50: 58021000 .word 0x58021000 08002b54 : uint8_t MotorControl (TIM_HandleTypeDef* htim, TIM_OC_InitTypeDef* motorTimerConfigOC, uint8_t channel1, uint8_t channel2, osTimerId_t motorTimerHandle, int32_t motorPWMPulse, int32_t motorTimerPeriod, uint8_t switchLimiterUpStat, uint8_t switchLimiterDownStat) { 8002b54: b580 push {r7, lr} 8002b56: b088 sub sp, #32 8002b58: af02 add r7, sp, #8 8002b5a: 60f8 str r0, [r7, #12] 8002b5c: 60b9 str r1, [r7, #8] 8002b5e: 4611 mov r1, r2 8002b60: 461a mov r2, r3 8002b62: 460b mov r3, r1 8002b64: 71fb strb r3, [r7, #7] 8002b66: 4613 mov r3, r2 8002b68: 71bb strb r3, [r7, #6] uint32_t motorStatus = 0; 8002b6a: 2300 movs r3, #0 8002b6c: 617b str r3, [r7, #20] MotorDriverState setMotorState = HiZ; 8002b6e: 2300 movs r3, #0 8002b70: 74fb strb r3, [r7, #19] HAL_TIM_PWM_Stop (htim, channel1); 8002b72: 79fb ldrb r3, [r7, #7] 8002b74: 4619 mov r1, r3 8002b76: 68f8 ldr r0, [r7, #12] 8002b78: f00c fd2a bl 800f5d0 HAL_TIM_PWM_Stop (htim, channel2); 8002b7c: 79bb ldrb r3, [r7, #6] 8002b7e: 4619 mov r1, r3 8002b80: 68f8 ldr r0, [r7, #12] 8002b82: f00c fd25 bl 800f5d0 if (motorTimerPeriod > 0) { 8002b86: 6abb ldr r3, [r7, #40] @ 0x28 8002b88: 2b00 cmp r3, #0 8002b8a: f340 808c ble.w 8002ca6 if (motorPWMPulse > 0) { 8002b8e: 6a7b ldr r3, [r7, #36] @ 0x24 8002b90: 2b00 cmp r3, #0 8002b92: dd2c ble.n 8002bee // Forward if (switchLimiterUpStat == 0) { 8002b94: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 8002b98: 2b00 cmp r3, #0 8002b9a: d11d bne.n 8002bd8 setMotorState = Forward; 8002b9c: 2301 movs r3, #1 8002b9e: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 8002ba0: 79f9 ldrb r1, [r7, #7] 8002ba2: 79b8 ldrb r0, [r7, #6] 8002ba4: 6a7b ldr r3, [r7, #36] @ 0x24 8002ba6: ea83 72e3 eor.w r2, r3, r3, asr #31 8002baa: eba2 72e3 sub.w r2, r2, r3, asr #31 8002bae: 4613 mov r3, r2 8002bb0: 009b lsls r3, r3, #2 8002bb2: 4413 add r3, r2 8002bb4: 005b lsls r3, r3, #1 8002bb6: 9301 str r3, [sp, #4] 8002bb8: 7cfb ldrb r3, [r7, #19] 8002bba: 9300 str r3, [sp, #0] 8002bbc: 4603 mov r3, r0 8002bbe: 460a mov r2, r1 8002bc0: 68b9 ldr r1, [r7, #8] 8002bc2: 68f8 ldr r0, [r7, #12] 8002bc4: f000 f8ff bl 8002dc6 HAL_TIM_PWM_Start (htim, channel1); 8002bc8: 79fb ldrb r3, [r7, #7] 8002bca: 4619 mov r1, r3 8002bcc: 68f8 ldr r0, [r7, #12] 8002bce: f00c fbf1 bl 800f3b4 motorStatus = 1; 8002bd2: 2301 movs r3, #1 8002bd4: 617b str r3, [r7, #20] 8002bd6: e004 b.n 8002be2 } else { HAL_TIM_PWM_Stop (htim, channel1); 8002bd8: 79fb ldrb r3, [r7, #7] 8002bda: 4619 mov r1, r3 8002bdc: 68f8 ldr r0, [r7, #12] 8002bde: f00c fcf7 bl 800f5d0 } HAL_TIM_PWM_Stop (htim, channel2); 8002be2: 79bb ldrb r3, [r7, #6] 8002be4: 4619 mov r1, r3 8002be6: 68f8 ldr r0, [r7, #12] 8002be8: f00c fcf2 bl 800f5d0 8002bec: e051 b.n 8002c92 } else if (motorPWMPulse < 0) { 8002bee: 6a7b ldr r3, [r7, #36] @ 0x24 8002bf0: 2b00 cmp r3, #0 8002bf2: da2c bge.n 8002c4e // Reverse if (switchLimiterDownStat == 0) { 8002bf4: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 8002bf8: 2b00 cmp r3, #0 8002bfa: d11d bne.n 8002c38 setMotorState = Reverse; 8002bfc: 2302 movs r3, #2 8002bfe: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 8002c00: 79f9 ldrb r1, [r7, #7] 8002c02: 79b8 ldrb r0, [r7, #6] 8002c04: 6a7b ldr r3, [r7, #36] @ 0x24 8002c06: ea83 72e3 eor.w r2, r3, r3, asr #31 8002c0a: eba2 72e3 sub.w r2, r2, r3, asr #31 8002c0e: 4613 mov r3, r2 8002c10: 009b lsls r3, r3, #2 8002c12: 4413 add r3, r2 8002c14: 005b lsls r3, r3, #1 8002c16: 9301 str r3, [sp, #4] 8002c18: 7cfb ldrb r3, [r7, #19] 8002c1a: 9300 str r3, [sp, #0] 8002c1c: 4603 mov r3, r0 8002c1e: 460a mov r2, r1 8002c20: 68b9 ldr r1, [r7, #8] 8002c22: 68f8 ldr r0, [r7, #12] 8002c24: f000 f8cf bl 8002dc6 HAL_TIM_PWM_Start (htim, channel2); 8002c28: 79bb ldrb r3, [r7, #6] 8002c2a: 4619 mov r1, r3 8002c2c: 68f8 ldr r0, [r7, #12] 8002c2e: f00c fbc1 bl 800f3b4 motorStatus = 1; 8002c32: 2301 movs r3, #1 8002c34: 617b str r3, [r7, #20] 8002c36: e004 b.n 8002c42 } else { HAL_TIM_PWM_Stop (htim, channel2); 8002c38: 79bb ldrb r3, [r7, #6] 8002c3a: 4619 mov r1, r3 8002c3c: 68f8 ldr r0, [r7, #12] 8002c3e: f00c fcc7 bl 800f5d0 } HAL_TIM_PWM_Stop (htim, channel1); 8002c42: 79fb ldrb r3, [r7, #7] 8002c44: 4619 mov r1, r3 8002c46: 68f8 ldr r0, [r7, #12] 8002c48: f00c fcc2 bl 800f5d0 8002c4c: e021 b.n 8002c92 } else { // Brake setMotorState = Brake; 8002c4e: 2303 movs r3, #3 8002c50: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 8002c52: 79f9 ldrb r1, [r7, #7] 8002c54: 79b8 ldrb r0, [r7, #6] 8002c56: 6a7b ldr r3, [r7, #36] @ 0x24 8002c58: ea83 72e3 eor.w r2, r3, r3, asr #31 8002c5c: eba2 72e3 sub.w r2, r2, r3, asr #31 8002c60: 4613 mov r3, r2 8002c62: 009b lsls r3, r3, #2 8002c64: 4413 add r3, r2 8002c66: 005b lsls r3, r3, #1 8002c68: 9301 str r3, [sp, #4] 8002c6a: 7cfb ldrb r3, [r7, #19] 8002c6c: 9300 str r3, [sp, #0] 8002c6e: 4603 mov r3, r0 8002c70: 460a mov r2, r1 8002c72: 68b9 ldr r1, [r7, #8] 8002c74: 68f8 ldr r0, [r7, #12] 8002c76: f000 f8a6 bl 8002dc6 HAL_TIM_PWM_Start (htim, channel1); 8002c7a: 79fb ldrb r3, [r7, #7] 8002c7c: 4619 mov r1, r3 8002c7e: 68f8 ldr r0, [r7, #12] 8002c80: f00c fb98 bl 800f3b4 HAL_TIM_PWM_Start (htim, channel2); 8002c84: 79bb ldrb r3, [r7, #6] 8002c86: 4619 mov r1, r3 8002c88: 68f8 ldr r0, [r7, #12] 8002c8a: f00c fb93 bl 800f3b4 motorStatus = 0; 8002c8e: 2300 movs r3, #0 8002c90: 617b str r3, [r7, #20] } osTimerStart (motorTimerHandle, motorTimerPeriod * 1000); 8002c92: 6abb ldr r3, [r7, #40] @ 0x28 8002c94: f44f 727a mov.w r2, #1000 @ 0x3e8 8002c98: fb02 f303 mul.w r3, r2, r3 8002c9c: 4619 mov r1, r3 8002c9e: 6a38 ldr r0, [r7, #32] 8002ca0: f010 fd9e bl 80137e0 8002ca4: e089 b.n 8002dba } else if ((motorTimerPeriod == 0) && (motorPWMPulse == 0)) { 8002ca6: 6abb ldr r3, [r7, #40] @ 0x28 8002ca8: 2b00 cmp r3, #0 8002caa: d126 bne.n 8002cfa 8002cac: 6a7b ldr r3, [r7, #36] @ 0x24 8002cae: 2b00 cmp r3, #0 8002cb0: d123 bne.n 8002cfa MotorAction (htim, motorTimerConfigOC, channel1, channel2, HiZ, abs (motorPWMPulse) * 10); 8002cb2: 79f9 ldrb r1, [r7, #7] 8002cb4: 79b8 ldrb r0, [r7, #6] 8002cb6: 6a7b ldr r3, [r7, #36] @ 0x24 8002cb8: ea83 72e3 eor.w r2, r3, r3, asr #31 8002cbc: eba2 72e3 sub.w r2, r2, r3, asr #31 8002cc0: 4613 mov r3, r2 8002cc2: 009b lsls r3, r3, #2 8002cc4: 4413 add r3, r2 8002cc6: 005b lsls r3, r3, #1 8002cc8: 9301 str r3, [sp, #4] 8002cca: 2300 movs r3, #0 8002ccc: 9300 str r3, [sp, #0] 8002cce: 4603 mov r3, r0 8002cd0: 460a mov r2, r1 8002cd2: 68b9 ldr r1, [r7, #8] 8002cd4: 68f8 ldr r0, [r7, #12] 8002cd6: f000 f876 bl 8002dc6 HAL_TIM_PWM_Stop (htim, channel1); 8002cda: 79fb ldrb r3, [r7, #7] 8002cdc: 4619 mov r1, r3 8002cde: 68f8 ldr r0, [r7, #12] 8002ce0: f00c fc76 bl 800f5d0 HAL_TIM_PWM_Stop (htim, channel2); 8002ce4: 79bb ldrb r3, [r7, #6] 8002ce6: 4619 mov r1, r3 8002ce8: 68f8 ldr r0, [r7, #12] 8002cea: f00c fc71 bl 800f5d0 osTimerStop (motorTimerHandle); 8002cee: 6a38 ldr r0, [r7, #32] 8002cf0: f010 fda4 bl 801383c motorStatus = 0; 8002cf4: 2300 movs r3, #0 8002cf6: 617b str r3, [r7, #20] 8002cf8: e05f b.n 8002dba } else if (motorTimerPeriod == -1) { 8002cfa: 6abb ldr r3, [r7, #40] @ 0x28 8002cfc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8002d00: d15b bne.n 8002dba if (motorPWMPulse > 0) { 8002d02: 6a7b ldr r3, [r7, #36] @ 0x24 8002d04: 2b00 cmp r3, #0 8002d06: dd2c ble.n 8002d62 // Forward if (switchLimiterUpStat == 0) { 8002d08: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 8002d0c: 2b00 cmp r3, #0 8002d0e: d11d bne.n 8002d4c setMotorState = Forward; 8002d10: 2301 movs r3, #1 8002d12: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 8002d14: 79f9 ldrb r1, [r7, #7] 8002d16: 79b8 ldrb r0, [r7, #6] 8002d18: 6a7b ldr r3, [r7, #36] @ 0x24 8002d1a: ea83 72e3 eor.w r2, r3, r3, asr #31 8002d1e: eba2 72e3 sub.w r2, r2, r3, asr #31 8002d22: 4613 mov r3, r2 8002d24: 009b lsls r3, r3, #2 8002d26: 4413 add r3, r2 8002d28: 005b lsls r3, r3, #1 8002d2a: 9301 str r3, [sp, #4] 8002d2c: 7cfb ldrb r3, [r7, #19] 8002d2e: 9300 str r3, [sp, #0] 8002d30: 4603 mov r3, r0 8002d32: 460a mov r2, r1 8002d34: 68b9 ldr r1, [r7, #8] 8002d36: 68f8 ldr r0, [r7, #12] 8002d38: f000 f845 bl 8002dc6 HAL_TIM_PWM_Start (htim, channel1); 8002d3c: 79fb ldrb r3, [r7, #7] 8002d3e: 4619 mov r1, r3 8002d40: 68f8 ldr r0, [r7, #12] 8002d42: f00c fb37 bl 800f3b4 motorStatus = 1; 8002d46: 2301 movs r3, #1 8002d48: 617b str r3, [r7, #20] 8002d4a: e004 b.n 8002d56 } else { HAL_TIM_PWM_Stop (htim, channel1); 8002d4c: 79fb ldrb r3, [r7, #7] 8002d4e: 4619 mov r1, r3 8002d50: 68f8 ldr r0, [r7, #12] 8002d52: f00c fc3d bl 800f5d0 } HAL_TIM_PWM_Stop (htim, channel2); 8002d56: 79bb ldrb r3, [r7, #6] 8002d58: 4619 mov r1, r3 8002d5a: 68f8 ldr r0, [r7, #12] 8002d5c: f00c fc38 bl 800f5d0 8002d60: e02b b.n 8002dba } else { // Reverse if (switchLimiterDownStat == 0) { 8002d62: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 8002d66: 2b00 cmp r3, #0 8002d68: d11d bne.n 8002da6 setMotorState = Reverse; 8002d6a: 2302 movs r3, #2 8002d6c: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 8002d6e: 79f9 ldrb r1, [r7, #7] 8002d70: 79b8 ldrb r0, [r7, #6] 8002d72: 6a7b ldr r3, [r7, #36] @ 0x24 8002d74: ea83 72e3 eor.w r2, r3, r3, asr #31 8002d78: eba2 72e3 sub.w r2, r2, r3, asr #31 8002d7c: 4613 mov r3, r2 8002d7e: 009b lsls r3, r3, #2 8002d80: 4413 add r3, r2 8002d82: 005b lsls r3, r3, #1 8002d84: 9301 str r3, [sp, #4] 8002d86: 7cfb ldrb r3, [r7, #19] 8002d88: 9300 str r3, [sp, #0] 8002d8a: 4603 mov r3, r0 8002d8c: 460a mov r2, r1 8002d8e: 68b9 ldr r1, [r7, #8] 8002d90: 68f8 ldr r0, [r7, #12] 8002d92: f000 f818 bl 8002dc6 HAL_TIM_PWM_Start (htim, channel2); 8002d96: 79bb ldrb r3, [r7, #6] 8002d98: 4619 mov r1, r3 8002d9a: 68f8 ldr r0, [r7, #12] 8002d9c: f00c fb0a bl 800f3b4 motorStatus = 1; 8002da0: 2301 movs r3, #1 8002da2: 617b str r3, [r7, #20] 8002da4: e004 b.n 8002db0 } else { HAL_TIM_PWM_Stop (htim, channel2); 8002da6: 79bb ldrb r3, [r7, #6] 8002da8: 4619 mov r1, r3 8002daa: 68f8 ldr r0, [r7, #12] 8002dac: f00c fc10 bl 800f5d0 } HAL_TIM_PWM_Stop (htim, channel1); 8002db0: 79fb ldrb r3, [r7, #7] 8002db2: 4619 mov r1, r3 8002db4: 68f8 ldr r0, [r7, #12] 8002db6: f00c fc0b bl 800f5d0 } } return motorStatus; 8002dba: 697b ldr r3, [r7, #20] 8002dbc: b2db uxtb r3, r3 } 8002dbe: 4618 mov r0, r3 8002dc0: 3718 adds r7, #24 8002dc2: 46bd mov sp, r7 8002dc4: bd80 pop {r7, pc} 08002dc6 : void MotorAction (TIM_HandleTypeDef* tim, TIM_OC_InitTypeDef* timerConf, uint32_t channel1, uint32_t channel2, MotorDriverState setState, uint32_t pulse) { 8002dc6: b580 push {r7, lr} 8002dc8: b084 sub sp, #16 8002dca: af00 add r7, sp, #0 8002dcc: 60f8 str r0, [r7, #12] 8002dce: 60b9 str r1, [r7, #8] 8002dd0: 607a str r2, [r7, #4] 8002dd2: 603b str r3, [r7, #0] timerConf->Pulse = pulse; 8002dd4: 68bb ldr r3, [r7, #8] 8002dd6: 69fa ldr r2, [r7, #28] 8002dd8: 605a str r2, [r3, #4] switch (setState) { 8002dda: 7e3b ldrb r3, [r7, #24] 8002ddc: 2b02 cmp r3, #2 8002dde: dc02 bgt.n 8002de6 8002de0: 2b00 cmp r3, #0 8002de2: da03 bge.n 8002dec 8002de4: e038 b.n 8002e58 8002de6: 2b03 cmp r3, #3 8002de8: d01b beq.n 8002e22 8002dea: e035 b.n 8002e58 case Forward: case Reverse: case HiZ: timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8002dec: 68bb ldr r3, [r7, #8] 8002dee: 2200 movs r2, #0 8002df0: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 8002df2: 687a ldr r2, [r7, #4] 8002df4: 68b9 ldr r1, [r7, #8] 8002df6: 68f8 ldr r0, [r7, #12] 8002df8: f00c fd88 bl 800f90c 8002dfc: 4603 mov r3, r0 8002dfe: 2b00 cmp r3, #0 8002e00: d001 beq.n 8002e06 Error_Handler (); 8002e02: f7fe fec3 bl 8001b8c } timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8002e06: 68bb ldr r3, [r7, #8] 8002e08: 2200 movs r2, #0 8002e0a: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 8002e0c: 683a ldr r2, [r7, #0] 8002e0e: 68b9 ldr r1, [r7, #8] 8002e10: 68f8 ldr r0, [r7, #12] 8002e12: f00c fd7b bl 800f90c 8002e16: 4603 mov r3, r0 8002e18: 2b00 cmp r3, #0 8002e1a: d038 beq.n 8002e8e Error_Handler (); 8002e1c: f7fe feb6 bl 8001b8c } break; 8002e20: e035 b.n 8002e8e case Brake: timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 8002e22: 68bb ldr r3, [r7, #8] 8002e24: 2202 movs r2, #2 8002e26: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 8002e28: 687a ldr r2, [r7, #4] 8002e2a: 68b9 ldr r1, [r7, #8] 8002e2c: 68f8 ldr r0, [r7, #12] 8002e2e: f00c fd6d bl 800f90c 8002e32: 4603 mov r3, r0 8002e34: 2b00 cmp r3, #0 8002e36: d001 beq.n 8002e3c Error_Handler (); 8002e38: f7fe fea8 bl 8001b8c } timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 8002e3c: 68bb ldr r3, [r7, #8] 8002e3e: 2202 movs r2, #2 8002e40: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 8002e42: 683a ldr r2, [r7, #0] 8002e44: 68b9 ldr r1, [r7, #8] 8002e46: 68f8 ldr r0, [r7, #12] 8002e48: f00c fd60 bl 800f90c 8002e4c: 4603 mov r3, r0 8002e4e: 2b00 cmp r3, #0 8002e50: d01f beq.n 8002e92 Error_Handler (); 8002e52: f7fe fe9b bl 8001b8c } break; 8002e56: e01c b.n 8002e92 default: timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8002e58: 68bb ldr r3, [r7, #8] 8002e5a: 2200 movs r2, #0 8002e5c: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 8002e5e: 687a ldr r2, [r7, #4] 8002e60: 68b9 ldr r1, [r7, #8] 8002e62: 68f8 ldr r0, [r7, #12] 8002e64: f00c fd52 bl 800f90c 8002e68: 4603 mov r3, r0 8002e6a: 2b00 cmp r3, #0 8002e6c: d001 beq.n 8002e72 Error_Handler (); 8002e6e: f7fe fe8d bl 8001b8c } timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8002e72: 68bb ldr r3, [r7, #8] 8002e74: 2200 movs r2, #0 8002e76: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 8002e78: 683a ldr r2, [r7, #0] 8002e7a: 68b9 ldr r1, [r7, #8] 8002e7c: 68f8 ldr r0, [r7, #12] 8002e7e: f00c fd45 bl 800f90c 8002e82: 4603 mov r3, r0 8002e84: 2b00 cmp r3, #0 8002e86: d006 beq.n 8002e96 Error_Handler (); 8002e88: f7fe fe80 bl 8001b8c } break; 8002e8c: e003 b.n 8002e96 break; 8002e8e: bf00 nop 8002e90: e002 b.n 8002e98 break; 8002e92: bf00 nop 8002e94: e000 b.n 8002e98 break; 8002e96: bf00 nop } } 8002e98: bf00 nop 8002e9a: 3710 adds r7, #16 8002e9c: 46bd mov sp, r7 8002e9e: bd80 pop {r7, pc} 08002ea0 : extern osTimerId_t motorXTimerHandle; extern osTimerId_t motorYTimerHandle; extern TIM_HandleTypeDef htim3; extern TIM_OC_InitTypeDef motorXYTimerConfigOC; void PositionControlTaskInit (void) { 8002ea0: b580 push {r7, lr} 8002ea2: b08a sub sp, #40 @ 0x28 8002ea4: af00 add r7, sp, #0 // positionSettingMutex = osMutexNew (NULL); osThreadAttr_t osThreadAttrPositionControlTask = { 0 }; 8002ea6: 1d3b adds r3, r7, #4 8002ea8: 2224 movs r2, #36 @ 0x24 8002eaa: 2100 movs r1, #0 8002eac: 4618 mov r0, r3 8002eae: f015 fadb bl 8018468 osThreadAttrPositionControlTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8002eb2: f44f 6380 mov.w r3, #1024 @ 0x400 8002eb6: 61bb str r3, [r7, #24] osThreadAttrPositionControlTask.priority = (osPriority_t)osPriorityNormal; 8002eb8: 2318 movs r3, #24 8002eba: 61fb str r3, [r7, #28] positionXControlTaskInitArg.channel1 = TIM_CHANNEL_1; 8002ebc: 4b3b ldr r3, [pc, #236] @ (8002fac ) 8002ebe: 2200 movs r2, #0 8002ec0: 721a strb r2, [r3, #8] positionXControlTaskInitArg.channel2 = TIM_CHANNEL_2; 8002ec2: 4b3a ldr r3, [pc, #232] @ (8002fac ) 8002ec4: 2204 movs r2, #4 8002ec6: 725a strb r2, [r3, #9] positionXControlTaskInitArg.htim = &htim3; 8002ec8: 4b38 ldr r3, [pc, #224] @ (8002fac ) 8002eca: 4a39 ldr r2, [pc, #228] @ (8002fb0 ) 8002ecc: 601a str r2, [r3, #0] positionXControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC; 8002ece: 4b37 ldr r3, [pc, #220] @ (8002fac ) 8002ed0: 4a38 ldr r2, [pc, #224] @ (8002fb4 ) 8002ed2: 605a str r2, [r3, #4] positionXControlTaskInitArg.motorTimerHandle = motorXTimerHandle; 8002ed4: 4b38 ldr r3, [pc, #224] @ (8002fb8 ) 8002ed6: 681b ldr r3, [r3, #0] 8002ed8: 4a34 ldr r2, [pc, #208] @ (8002fac ) 8002eda: 60d3 str r3, [r2, #12] positionXControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 8002edc: 2200 movs r2, #0 8002ede: 2104 movs r1, #4 8002ee0: 2010 movs r0, #16 8002ee2: f010 fdf0 bl 8013ac6 8002ee6: 4603 mov r3, r0 8002ee8: 4a30 ldr r2, [pc, #192] @ (8002fac ) 8002eea: 6113 str r3, [r2, #16] positionXControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitXSwitchCenter); 8002eec: 4b2f ldr r3, [pc, #188] @ (8002fac ) 8002eee: 4a33 ldr r2, [pc, #204] @ (8002fbc ) 8002ef0: 61da str r2, [r3, #28] positionXControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitXSwitchUp); 8002ef2: 4b2e ldr r3, [pc, #184] @ (8002fac ) 8002ef4: 4a32 ldr r2, [pc, #200] @ (8002fc0 ) 8002ef6: 615a str r2, [r3, #20] positionXControlTaskInitArg.switchLimiterDownStat = &(sensorsInfo.limitXSwitchDown); 8002ef8: 4b2c ldr r3, [pc, #176] @ (8002fac ) 8002efa: 4a32 ldr r2, [pc, #200] @ (8002fc4 ) 8002efc: 619a str r2, [r3, #24] positionXControlTaskInitArg.currentPosition = &(sensorsInfo.currentXPosition); 8002efe: 4b2b ldr r3, [pc, #172] @ (8002fac ) 8002f00: 4a31 ldr r2, [pc, #196] @ (8002fc8 ) 8002f02: 621a str r2, [r3, #32] positionXControlTaskInitArg.motorStatus = &(sensorsInfo.motorXStatus); 8002f04: 4b29 ldr r3, [pc, #164] @ (8002fac ) 8002f06: 4a31 ldr r2, [pc, #196] @ (8002fcc ) 8002f08: 629a str r2, [r3, #40] @ 0x28 positionXControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorXPeakCurrent); 8002f0a: 4b28 ldr r3, [pc, #160] @ (8002fac ) 8002f0c: 4a30 ldr r2, [pc, #192] @ (8002fd0 ) 8002f0e: 62da str r2, [r3, #44] @ 0x2c positionXControlTaskInitArg.positionSetting = &positionXSetting; 8002f10: 4b26 ldr r3, [pc, #152] @ (8002fac ) 8002f12: 4a30 ldr r2, [pc, #192] @ (8002fd4 ) 8002f14: 625a str r2, [r3, #36] @ 0x24 positionXControlTaskInitArg.axe = 'X'; 8002f16: 4b25 ldr r3, [pc, #148] @ (8002fac ) 8002f18: 2258 movs r2, #88 @ 0x58 8002f1a: f883 2030 strb.w r2, [r3, #48] @ 0x30 positionYControlTaskInitArg.channel1 = TIM_CHANNEL_3; 8002f1e: 4b2e ldr r3, [pc, #184] @ (8002fd8 ) 8002f20: 2208 movs r2, #8 8002f22: 721a strb r2, [r3, #8] positionYControlTaskInitArg.channel2 = TIM_CHANNEL_4; 8002f24: 4b2c ldr r3, [pc, #176] @ (8002fd8 ) 8002f26: 220c movs r2, #12 8002f28: 725a strb r2, [r3, #9] positionYControlTaskInitArg.htim = &htim3; 8002f2a: 4b2b ldr r3, [pc, #172] @ (8002fd8 ) 8002f2c: 4a20 ldr r2, [pc, #128] @ (8002fb0 ) 8002f2e: 601a str r2, [r3, #0] positionYControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC; 8002f30: 4b29 ldr r3, [pc, #164] @ (8002fd8 ) 8002f32: 4a20 ldr r2, [pc, #128] @ (8002fb4 ) 8002f34: 605a str r2, [r3, #4] positionYControlTaskInitArg.motorTimerHandle = motorYTimerHandle; 8002f36: 4b29 ldr r3, [pc, #164] @ (8002fdc ) 8002f38: 681b ldr r3, [r3, #0] 8002f3a: 4a27 ldr r2, [pc, #156] @ (8002fd8 ) 8002f3c: 60d3 str r3, [r2, #12] positionYControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 8002f3e: 2200 movs r2, #0 8002f40: 2104 movs r1, #4 8002f42: 2010 movs r0, #16 8002f44: f010 fdbf bl 8013ac6 8002f48: 4603 mov r3, r0 8002f4a: 4a23 ldr r2, [pc, #140] @ (8002fd8 ) 8002f4c: 6113 str r3, [r2, #16] positionYControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitYSwitchCenter); 8002f4e: 4b22 ldr r3, [pc, #136] @ (8002fd8 ) 8002f50: 4a23 ldr r2, [pc, #140] @ (8002fe0 ) 8002f52: 61da str r2, [r3, #28] positionYControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitYSwitchUp); 8002f54: 4b20 ldr r3, [pc, #128] @ (8002fd8 ) 8002f56: 4a23 ldr r2, [pc, #140] @ (8002fe4 ) 8002f58: 615a str r2, [r3, #20] positionYControlTaskInitArg.switchLimiterDownStat = &(sensorsInfo.limitYSwitchDown); 8002f5a: 4b1f ldr r3, [pc, #124] @ (8002fd8 ) 8002f5c: 4a22 ldr r2, [pc, #136] @ (8002fe8 ) 8002f5e: 619a str r2, [r3, #24] positionYControlTaskInitArg.currentPosition = &(sensorsInfo.currentYPosition); 8002f60: 4b1d ldr r3, [pc, #116] @ (8002fd8 ) 8002f62: 4a22 ldr r2, [pc, #136] @ (8002fec ) 8002f64: 621a str r2, [r3, #32] positionYControlTaskInitArg.motorStatus = &(sensorsInfo.motorYStatus); 8002f66: 4b1c ldr r3, [pc, #112] @ (8002fd8 ) 8002f68: 4a21 ldr r2, [pc, #132] @ (8002ff0 ) 8002f6a: 629a str r2, [r3, #40] @ 0x28 positionYControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorYPeakCurrent); 8002f6c: 4b1a ldr r3, [pc, #104] @ (8002fd8 ) 8002f6e: 4a21 ldr r2, [pc, #132] @ (8002ff4 ) 8002f70: 62da str r2, [r3, #44] @ 0x2c positionXControlTaskInitArg.positionSetting = &positionYSetting; 8002f72: 4b0e ldr r3, [pc, #56] @ (8002fac ) 8002f74: 4a20 ldr r2, [pc, #128] @ (8002ff8 ) 8002f76: 625a str r2, [r3, #36] @ 0x24 positionYControlTaskInitArg.axe = 'Y'; 8002f78: 4b17 ldr r3, [pc, #92] @ (8002fd8 ) 8002f7a: 2259 movs r2, #89 @ 0x59 8002f7c: f883 2030 strb.w r2, [r3, #48] @ 0x30 positionXControlTaskHandle = osThreadNew (PositionControlTask, &positionXControlTaskInitArg, &osThreadAttrPositionControlTask); 8002f80: 1d3b adds r3, r7, #4 8002f82: 461a mov r2, r3 8002f84: 4909 ldr r1, [pc, #36] @ (8002fac ) 8002f86: 481d ldr r0, [pc, #116] @ (8002ffc ) 8002f88: f010 faea bl 8013560 8002f8c: 4603 mov r3, r0 8002f8e: 4a1c ldr r2, [pc, #112] @ (8003000 ) 8002f90: 6013 str r3, [r2, #0] positionYControlTaskHandle = osThreadNew (PositionControlTask, &positionYControlTaskInitArg, &osThreadAttrPositionControlTask); 8002f92: 1d3b adds r3, r7, #4 8002f94: 461a mov r2, r3 8002f96: 4910 ldr r1, [pc, #64] @ (8002fd8 ) 8002f98: 4818 ldr r0, [pc, #96] @ (8002ffc ) 8002f9a: f010 fae1 bl 8013560 8002f9e: 4603 mov r3, r0 8002fa0: 4a18 ldr r2, [pc, #96] @ (8003004 ) 8002fa2: 6013 str r3, [r2, #0] } 8002fa4: bf00 nop 8002fa6: 3728 adds r7, #40 @ 0x28 8002fa8: 46bd mov sp, r7 8002faa: bd80 pop {r7, pc} 8002fac: 24000a00 .word 0x24000a00 8002fb0: 240005e8 .word 0x240005e8 8002fb4: 24000888 .word 0x24000888 8002fb8: 2400080c .word 0x2400080c 8002fbc: 2400096a .word 0x2400096a 8002fc0: 24000968 .word 0x24000968 8002fc4: 24000969 .word 0x24000969 8002fc8: 24000970 .word 0x24000970 8002fcc: 24000954 .word 0x24000954 8002fd0: 24000960 .word 0x24000960 8002fd4: 240009c0 .word 0x240009c0 8002fd8: 24000a40 .word 0x24000a40 8002fdc: 2400083c .word 0x2400083c 8002fe0: 2400096d .word 0x2400096d 8002fe4: 2400096b .word 0x2400096b 8002fe8: 2400096c .word 0x2400096c 8002fec: 24000974 .word 0x24000974 8002ff0: 24000955 .word 0x24000955 8002ff4: 24000964 .word 0x24000964 8002ff8: 240009e0 .word 0x240009e0 8002ffc: 08003009 .word 0x08003009 8003000: 240009e4 .word 0x240009e4 8003004: 240009e8 .word 0x240009e8 08003008 : void PositionControlTask (void* argument) { 8003008: b5f0 push {r4, r5, r6, r7, lr} 800300a: b09f sub sp, #124 @ 0x7c 800300c: af06 add r7, sp, #24 800300e: 6078 str r0, [r7, #4] 8003010: f107 0360 add.w r3, r7, #96 @ 0x60 8003014: 3b58 subs r3, #88 @ 0x58 8003016: 331f adds r3, #31 8003018: 095b lsrs r3, r3, #5 800301a: 015c lsls r4, r3, #5 const int32_t PositionControlTaskTimeOut = 100; 800301c: 2364 movs r3, #100 @ 0x64 800301e: 643b str r3, [r7, #64] @ 0x40 PositionControlTaskInitArg* posCtrlTaskArg = (PositionControlTaskInitArg*)argument; 8003020: 687b ldr r3, [r7, #4] 8003022: 63fb str r3, [r7, #60] @ 0x3c PositionControlTaskData posCtrlData __attribute__ ((aligned (32))) = { 0 }; 8003024: f04f 0300 mov.w r3, #0 8003028: 6023 str r3, [r4, #0] uint32_t motorStatus = 0; 800302a: 2300 movs r3, #0 800302c: 63bb str r3, [r7, #56] @ 0x38 osStatus_t queueSatus; int32_t pwmValue = MOTOR_START_STOP_PWM_VALUE; 800302e: 233c movs r3, #60 @ 0x3c 8003030: 65fb str r3, [r7, #92] @ 0x5c int32_t sign = 0; 8003032: 2300 movs r3, #0 8003034: 65bb str r3, [r7, #88] @ 0x58 MovementPhases movementPhase = idlePhase; 8003036: 2300 movs r3, #0 8003038: f887 3057 strb.w r3, [r7, #87] @ 0x57 float startPosition = 0; 800303c: f04f 0300 mov.w r3, #0 8003040: 653b str r3, [r7, #80] @ 0x50 float prevPosition = 0; 8003042: f04f 0300 mov.w r3, #0 8003046: 64fb str r3, [r7, #76] @ 0x4c int32_t timeLeftMS = 0; 8003048: 2300 movs r3, #0 800304a: 64bb str r3, [r7, #72] @ 0x48 int32_t moveCmdTimeoutCounter = 0; 800304c: 2300 movs r3, #0 800304e: 647b str r3, [r7, #68] @ 0x44 while (pdTRUE) { queueSatus = osMessageQueueGet (posCtrlTaskArg->positionSettingQueue, &posCtrlData, 0, pdMS_TO_TICKS (PositionControlTaskTimeOut)); 8003050: 6bfb ldr r3, [r7, #60] @ 0x3c 8003052: 6918 ldr r0, [r3, #16] 8003054: 6c3b ldr r3, [r7, #64] @ 0x40 8003056: f44f 727a mov.w r2, #1000 @ 0x3e8 800305a: fb02 f303 mul.w r3, r2, r3 800305e: 4a9b ldr r2, [pc, #620] @ (80032cc ) 8003060: fba2 2303 umull r2, r3, r2, r3 8003064: 099b lsrs r3, r3, #6 8003066: 2200 movs r2, #0 8003068: 4621 mov r1, r4 800306a: f010 fdff bl 8013c6c 800306e: 6378 str r0, [r7, #52] @ 0x34 if (queueSatus == osOK) { 8003070: 6b7b ldr r3, [r7, #52] @ 0x34 8003072: 2b00 cmp r3, #0 8003074: d13b bne.n 80030ee if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8003076: 4b96 ldr r3, [pc, #600] @ (80032d0 ) 8003078: 681b ldr r3, [r3, #0] 800307a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800307e: 4618 mov r0, r3 8003080: f010 fc99 bl 80139b6 8003084: 4603 mov r3, r0 8003086: 2b00 cmp r3, #0 8003088: d1e2 bne.n 8003050 float posDiff = posCtrlData.positionSettingValue - *posCtrlTaskArg->currentPosition; 800308a: ed94 7a00 vldr s14, [r4] 800308e: 6bfb ldr r3, [r7, #60] @ 0x3c 8003090: 6a1b ldr r3, [r3, #32] 8003092: edd3 7a00 vldr s15, [r3] 8003096: ee77 7a67 vsub.f32 s15, s14, s15 800309a: edc7 7a0b vstr s15, [r7, #44] @ 0x2c if (posDiff != 0) { 800309e: edd7 7a0b vldr s15, [r7, #44] @ 0x2c 80030a2: eef5 7a40 vcmp.f32 s15, #0.0 80030a6: eef1 fa10 vmrs APSR_nzcv, fpscr 80030aa: d016 beq.n 80030da sign = posDiff > 0 ? 1 : -1; 80030ac: edd7 7a0b vldr s15, [r7, #44] @ 0x2c 80030b0: eef5 7ac0 vcmpe.f32 s15, #0.0 80030b4: eef1 fa10 vmrs APSR_nzcv, fpscr 80030b8: dd01 ble.n 80030be 80030ba: 2301 movs r3, #1 80030bc: e001 b.n 80030c2 80030be: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80030c2: 65bb str r3, [r7, #88] @ 0x58 startPosition = *posCtrlTaskArg->currentPosition; 80030c4: 6bfb ldr r3, [r7, #60] @ 0x3c 80030c6: 6a1b ldr r3, [r3, #32] 80030c8: 681b ldr r3, [r3, #0] 80030ca: 653b str r3, [r7, #80] @ 0x50 movementPhase = startPhase; 80030cc: 2301 movs r3, #1 80030ce: f887 3057 strb.w r3, [r7, #87] @ 0x57 moveCmdTimeoutCounter = 0; 80030d2: 2300 movs r3, #0 80030d4: 647b str r3, [r7, #68] @ 0x44 timeLeftMS = 0; 80030d6: 2300 movs r3, #0 80030d8: 64bb str r3, [r7, #72] @ 0x48 #ifdef DBG_POSITION printf ("Axe %c start phase\n", posCtrlTaskArg->axe); #endif } *(posCtrlTaskArg->positionSetting) = posCtrlData.positionSettingValue; 80030da: 6bfb ldr r3, [r7, #60] @ 0x3c 80030dc: 6a5b ldr r3, [r3, #36] @ 0x24 80030de: 6822 ldr r2, [r4, #0] 80030e0: 601a str r2, [r3, #0] osMutexRelease (sensorsInfoMutex); 80030e2: 4b7b ldr r3, [pc, #492] @ (80032d0 ) 80030e4: 681b ldr r3, [r3, #0] 80030e6: 4618 mov r0, r3 80030e8: f010 fcb0 bl 8013a4c 80030ec: e7b0 b.n 8003050 // if (osMutexAcquire (positionSettingMutex, osWaitForever) == osOK) { // osMutexRelease (positionSettingMutex); // } } } else if (queueSatus == osErrorTimeout) { 80030ee: 6b7b ldr r3, [r7, #52] @ 0x34 80030f0: f113 0f02 cmn.w r3, #2 80030f4: d1ac bne.n 8003050 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80030f6: 4b76 ldr r3, [pc, #472] @ (80032d0 ) 80030f8: 681b ldr r3, [r3, #0] 80030fa: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80030fe: 4618 mov r0, r3 8003100: f010 fc59 bl 80139b6 8003104: 4603 mov r3, r0 8003106: 2b00 cmp r3, #0 8003108: d1a2 bne.n 8003050 if (((*posCtrlTaskArg->motorStatus != 0) && (movementPhase != idlePhase)) || (movementPhase == startPhase) ) { 800310a: 6bfb ldr r3, [r7, #60] @ 0x3c 800310c: 6a9b ldr r3, [r3, #40] @ 0x28 800310e: 781b ldrb r3, [r3, #0] 8003110: 2b00 cmp r3, #0 8003112: d003 beq.n 800311c 8003114: f897 3057 ldrb.w r3, [r7, #87] @ 0x57 8003118: 2b00 cmp r3, #0 800311a: d104 bne.n 8003126 800311c: f897 3057 ldrb.w r3, [r7, #87] @ 0x57 8003120: 2b01 cmp r3, #1 8003122: f040 81c9 bne.w 80034b8 if (((*posCtrlTaskArg->switchLimiterDownStat == 1) && (*posCtrlTaskArg->switchLimiterUpStat == 1)) || 8003126: 6bfb ldr r3, [r7, #60] @ 0x3c 8003128: 699b ldr r3, [r3, #24] 800312a: 781b ldrb r3, [r3, #0] 800312c: 2b01 cmp r3, #1 800312e: d104 bne.n 800313a 8003130: 6bfb ldr r3, [r7, #60] @ 0x3c 8003132: 695b ldr r3, [r3, #20] 8003134: 781b ldrb r3, [r3, #0] 8003136: 2b01 cmp r3, #1 8003138: d009 beq.n 800314e ((*posCtrlTaskArg->switchLimiterUpStat == 1) && (*posCtrlTaskArg->switchLimiterCenterStat == 1))) { 800313a: 6bfb ldr r3, [r7, #60] @ 0x3c 800313c: 695b ldr r3, [r3, #20] 800313e: 781b ldrb r3, [r3, #0] if (((*posCtrlTaskArg->switchLimiterDownStat == 1) && (*posCtrlTaskArg->switchLimiterUpStat == 1)) || 8003140: 2b01 cmp r3, #1 8003142: d12b bne.n 800319c ((*posCtrlTaskArg->switchLimiterUpStat == 1) && (*posCtrlTaskArg->switchLimiterCenterStat == 1))) { 8003144: 6bfb ldr r3, [r7, #60] @ 0x3c 8003146: 69db ldr r3, [r3, #28] 8003148: 781b ldrb r3, [r3, #0] 800314a: 2b01 cmp r3, #1 800314c: d126 bne.n 800319c movementPhase = idlePhase; 800314e: 2300 movs r3, #0 8003150: f887 3057 strb.w r3, [r7, #87] @ 0x57 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 8003154: 6bfb ldr r3, [r7, #60] @ 0x3c 8003156: 6818 ldr r0, [r3, #0] 8003158: 6bfb ldr r3, [r7, #60] @ 0x3c 800315a: 685d ldr r5, [r3, #4] 800315c: 6bfb ldr r3, [r7, #60] @ 0x3c 800315e: 7a1e ldrb r6, [r3, #8] 8003160: 6bfb ldr r3, [r7, #60] @ 0x3c 8003162: f893 c009 ldrb.w ip, [r3, #9] 8003166: 6bfb ldr r3, [r7, #60] @ 0x3c 8003168: 68db ldr r3, [r3, #12] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 800316a: 6bfa ldr r2, [r7, #60] @ 0x3c 800316c: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 800316e: 7812 ldrb r2, [r2, #0] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003170: 6bf9 ldr r1, [r7, #60] @ 0x3c 8003172: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 8003174: 7809 ldrb r1, [r1, #0] 8003176: 9104 str r1, [sp, #16] 8003178: 9203 str r2, [sp, #12] 800317a: 2200 movs r2, #0 800317c: 9202 str r2, [sp, #8] 800317e: 2200 movs r2, #0 8003180: 9201 str r2, [sp, #4] 8003182: 9300 str r3, [sp, #0] 8003184: 4663 mov r3, ip 8003186: 4632 mov r2, r6 8003188: 4629 mov r1, r5 800318a: f7ff fce3 bl 8002b54 800318e: 4603 mov r3, r0 8003190: 63bb str r3, [r7, #56] @ 0x38 *posCtrlTaskArg->motorStatus = motorStatus; 8003192: 6bfb ldr r3, [r7, #60] @ 0x3c 8003194: 6a9b ldr r3, [r3, #40] @ 0x28 8003196: 6bba ldr r2, [r7, #56] @ 0x38 8003198: b2d2 uxtb r2, r2 800319a: 701a strb r2, [r3, #0] printf ("Axe %c limiters wrong state - idle phase\n", posCtrlTaskArg->axe); #endif } timeLeftMS += PositionControlTaskTimeOut; 800319c: 6cba ldr r2, [r7, #72] @ 0x48 800319e: 6c3b ldr r3, [r7, #64] @ 0x40 80031a0: 4413 add r3, r2 80031a2: 64bb str r3, [r7, #72] @ 0x48 if (prevPosition == *posCtrlTaskArg->currentPosition) { 80031a4: 6bfb ldr r3, [r7, #60] @ 0x3c 80031a6: 6a1b ldr r3, [r3, #32] 80031a8: edd3 7a00 vldr s15, [r3] 80031ac: ed97 7a13 vldr s14, [r7, #76] @ 0x4c 80031b0: eeb4 7a67 vcmp.f32 s14, s15 80031b4: eef1 fa10 vmrs APSR_nzcv, fpscr 80031b8: d104 bne.n 80031c4 moveCmdTimeoutCounter += PositionControlTaskTimeOut; 80031ba: 6c7a ldr r2, [r7, #68] @ 0x44 80031bc: 6c3b ldr r3, [r7, #64] @ 0x40 80031be: 4413 add r3, r2 80031c0: 647b str r3, [r7, #68] @ 0x44 80031c2: e001 b.n 80031c8 } else { moveCmdTimeoutCounter = 0; 80031c4: 2300 movs r3, #0 80031c6: 647b str r3, [r7, #68] @ 0x44 } prevPosition = *posCtrlTaskArg->currentPosition; 80031c8: 6bfb ldr r3, [r7, #60] @ 0x3c 80031ca: 6a1b ldr r3, [r3, #32] 80031cc: 681b ldr r3, [r3, #0] 80031ce: 64fb str r3, [r7, #76] @ 0x4c if (moveCmdTimeoutCounter > NO_MOVE_TIMEOUT_MS) { 80031d0: 6c7b ldr r3, [r7, #68] @ 0x44 80031d2: f241 3288 movw r2, #5000 @ 0x1388 80031d6: 4293 cmp r3, r2 80031d8: dd26 ble.n 8003228 movementPhase = idlePhase; 80031da: 2300 movs r3, #0 80031dc: f887 3057 strb.w r3, [r7, #87] @ 0x57 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 80031e0: 6bfb ldr r3, [r7, #60] @ 0x3c 80031e2: 6818 ldr r0, [r3, #0] 80031e4: 6bfb ldr r3, [r7, #60] @ 0x3c 80031e6: 685d ldr r5, [r3, #4] 80031e8: 6bfb ldr r3, [r7, #60] @ 0x3c 80031ea: 7a1e ldrb r6, [r3, #8] 80031ec: 6bfb ldr r3, [r7, #60] @ 0x3c 80031ee: f893 c009 ldrb.w ip, [r3, #9] 80031f2: 6bfb ldr r3, [r7, #60] @ 0x3c 80031f4: 68db ldr r3, [r3, #12] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80031f6: 6bfa ldr r2, [r7, #60] @ 0x3c 80031f8: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 80031fa: 7812 ldrb r2, [r2, #0] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80031fc: 6bf9 ldr r1, [r7, #60] @ 0x3c 80031fe: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 8003200: 7809 ldrb r1, [r1, #0] 8003202: 9104 str r1, [sp, #16] 8003204: 9203 str r2, [sp, #12] 8003206: 2200 movs r2, #0 8003208: 9202 str r2, [sp, #8] 800320a: 2200 movs r2, #0 800320c: 9201 str r2, [sp, #4] 800320e: 9300 str r3, [sp, #0] 8003210: 4663 mov r3, ip 8003212: 4632 mov r2, r6 8003214: 4629 mov r1, r5 8003216: f7ff fc9d bl 8002b54 800321a: 4603 mov r3, r0 800321c: 63bb str r3, [r7, #56] @ 0x38 *posCtrlTaskArg->motorStatus = motorStatus; 800321e: 6bfb ldr r3, [r7, #60] @ 0x3c 8003220: 6a9b ldr r3, [r3, #40] @ 0x28 8003222: 6bba ldr r2, [r7, #56] @ 0x38 8003224: b2d2 uxtb r2, r2 8003226: 701a strb r2, [r3, #0] #ifdef DBG_POSITION printf ("Axe %c no movement idle phase\n", posCtrlTaskArg->axe); #endif } switch (movementPhase) { 8003228: f897 3057 ldrb.w r3, [r7, #87] @ 0x57 800322c: 3b01 subs r3, #1 800322e: 2b04 cmp r3, #4 8003230: f200 813a bhi.w 80034a8 8003234: a201 add r2, pc, #4 @ (adr r2, 800323c ) 8003236: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800323a: bf00 nop 800323c: 08003251 .word 0x08003251 8003240: 080032d5 .word 0x080032d5 8003244: 08003363 .word 0x08003363 8003248: 080033b1 .word 0x080033b1 800324c: 08003415 .word 0x08003415 case startPhase: motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003250: 6bfb ldr r3, [r7, #60] @ 0x3c 8003252: 681d ldr r5, [r3, #0] 8003254: 6bfb ldr r3, [r7, #60] @ 0x3c 8003256: 685e ldr r6, [r3, #4] 8003258: 6bfb ldr r3, [r7, #60] @ 0x3c 800325a: f893 c008 ldrb.w ip, [r3, #8] 800325e: 6bfb ldr r3, [r7, #60] @ 0x3c 8003260: f893 e009 ldrb.w lr, [r3, #9] 8003264: 6bfb ldr r3, [r7, #60] @ 0x3c 8003266: 68db ldr r3, [r3, #12] 8003268: 6dba ldr r2, [r7, #88] @ 0x58 800326a: 6df9 ldr r1, [r7, #92] @ 0x5c 800326c: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003270: 6bf9 ldr r1, [r7, #60] @ 0x3c 8003272: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003274: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003276: 6bf8 ldr r0, [r7, #60] @ 0x3c 8003278: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 800327a: 7800 ldrb r0, [r0, #0] 800327c: 9004 str r0, [sp, #16] 800327e: 9103 str r1, [sp, #12] 8003280: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003284: 9102 str r1, [sp, #8] 8003286: 9201 str r2, [sp, #4] 8003288: 9300 str r3, [sp, #0] 800328a: 4673 mov r3, lr 800328c: 4662 mov r2, ip 800328e: 4631 mov r1, r6 8003290: 4628 mov r0, r5 8003292: f7ff fc5f bl 8002b54 8003296: 4603 mov r3, r0 8003298: 63bb str r3, [r7, #56] @ 0x38 *posCtrlTaskArg->motorStatus = motorStatus; 800329a: 6bfb ldr r3, [r7, #60] @ 0x3c 800329c: 6a9b ldr r3, [r3, #40] @ 0x28 800329e: 6bba ldr r2, [r7, #56] @ 0x38 80032a0: b2d2 uxtb r2, r2 80032a2: 701a strb r2, [r3, #0] if (motorStatus == 1) { 80032a4: 6bbb ldr r3, [r7, #56] @ 0x38 80032a6: 2b01 cmp r3, #1 80032a8: d10c bne.n 80032c4 *posCtrlTaskArg->motorPeakCurrent = 0.0; 80032aa: 6bfb ldr r3, [r7, #60] @ 0x3c 80032ac: 6adb ldr r3, [r3, #44] @ 0x2c 80032ae: f04f 0200 mov.w r2, #0 80032b2: 601a str r2, [r3, #0] #ifdef DBG_POSITION printf ("Axe %c speed up phase\n", posCtrlTaskArg->axe); #endif movementPhase = speedUpPhase; 80032b4: 2302 movs r3, #2 80032b6: f887 3057 strb.w r3, [r7, #87] @ 0x57 timeLeftMS = 0; 80032ba: 2300 movs r3, #0 80032bc: 64bb str r3, [r7, #72] @ 0x48 moveCmdTimeoutCounter = 0; 80032be: 2300 movs r3, #0 80032c0: 647b str r3, [r7, #68] @ 0x44 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); #endif } break; 80032c2: e0f8 b.n 80034b6 movementPhase = idlePhase; 80032c4: 2300 movs r3, #0 80032c6: f887 3057 strb.w r3, [r7, #87] @ 0x57 break; 80032ca: e0f4 b.n 80034b6 80032cc: 10624dd3 .word 0x10624dd3 80032d0: 240008dc .word 0x240008dc case speedUpPhase: if ((abs (*posCtrlTaskArg->currentPosition - startPosition) >= ANGLE_RANGE_FOR_MOTOR_SPEED_LIMIT) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) { 80032d4: 6bfb ldr r3, [r7, #60] @ 0x3c 80032d6: 6a1b ldr r3, [r3, #32] 80032d8: ed93 7a00 vldr s14, [r3] 80032dc: edd7 7a14 vldr s15, [r7, #80] @ 0x50 80032e0: ee77 7a67 vsub.f32 s15, s14, s15 80032e4: eefd 7ae7 vcvt.s32.f32 s15, s15 80032e8: ee17 3a90 vmov r3, s15 80032ec: 2b00 cmp r3, #0 80032ee: bfb8 it lt 80032f0: 425b neglt r3, r3 80032f2: 2b04 cmp r3, #4 80032f4: dc05 bgt.n 8003302 80032f6: 6cbb ldr r3, [r7, #72] @ 0x48 80032f8: f241 3287 movw r2, #4999 @ 0x1387 80032fc: 4293 cmp r3, r2 80032fe: f340 80d5 ble.w 80034ac pwmValue = MOTOR_HIGH_SPEED_PWM_VALUE; 8003302: 2364 movs r3, #100 @ 0x64 8003304: 65fb str r3, [r7, #92] @ 0x5c motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003306: 6bfb ldr r3, [r7, #60] @ 0x3c 8003308: 681d ldr r5, [r3, #0] 800330a: 6bfb ldr r3, [r7, #60] @ 0x3c 800330c: 685e ldr r6, [r3, #4] 800330e: 6bfb ldr r3, [r7, #60] @ 0x3c 8003310: f893 c008 ldrb.w ip, [r3, #8] 8003314: 6bfb ldr r3, [r7, #60] @ 0x3c 8003316: f893 e009 ldrb.w lr, [r3, #9] 800331a: 6bfb ldr r3, [r7, #60] @ 0x3c 800331c: 68db ldr r3, [r3, #12] 800331e: 6dba ldr r2, [r7, #88] @ 0x58 8003320: 6df9 ldr r1, [r7, #92] @ 0x5c 8003322: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003326: 6bf9 ldr r1, [r7, #60] @ 0x3c 8003328: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 800332a: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 800332c: 6bf8 ldr r0, [r7, #60] @ 0x3c 800332e: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003330: 7800 ldrb r0, [r0, #0] 8003332: 9004 str r0, [sp, #16] 8003334: 9103 str r1, [sp, #12] 8003336: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800333a: 9102 str r1, [sp, #8] 800333c: 9201 str r2, [sp, #4] 800333e: 9300 str r3, [sp, #0] 8003340: 4673 mov r3, lr 8003342: 4662 mov r2, ip 8003344: 4631 mov r1, r6 8003346: 4628 mov r0, r5 8003348: f7ff fc04 bl 8002b54 800334c: 4603 mov r3, r0 800334e: 63bb str r3, [r7, #56] @ 0x38 *posCtrlTaskArg->motorStatus = motorStatus; 8003350: 6bfb ldr r3, [r7, #60] @ 0x3c 8003352: 6a9b ldr r3, [r3, #40] @ 0x28 8003354: 6bba ldr r2, [r7, #56] @ 0x38 8003356: b2d2 uxtb r2, r2 8003358: 701a strb r2, [r3, #0] movementPhase = movePhase; 800335a: 2303 movs r3, #3 800335c: f887 3057 strb.w r3, [r7, #87] @ 0x57 #ifdef DBG_POSITION printf ("Axe %c move phase\n", posCtrlTaskArg->axe); #endif } break; 8003360: e0a4 b.n 80034ac case movePhase: if (abs (*posCtrlTaskArg->currentPosition - *posCtrlTaskArg->positionSetting) <= ANGLE_RANGE_FOR_MOTOR_SPEED_LIMIT) { 8003362: 6bfb ldr r3, [r7, #60] @ 0x3c 8003364: 6a1b ldr r3, [r3, #32] 8003366: ed93 7a00 vldr s14, [r3] 800336a: 6bfb ldr r3, [r7, #60] @ 0x3c 800336c: 6a5b ldr r3, [r3, #36] @ 0x24 800336e: edd3 7a00 vldr s15, [r3] 8003372: ee77 7a67 vsub.f32 s15, s14, s15 8003376: eefd 7ae7 vcvt.s32.f32 s15, s15 800337a: ee17 3a90 vmov r3, s15 800337e: f113 0f05 cmn.w r3, #5 8003382: f2c0 8095 blt.w 80034b0 8003386: 6bfb ldr r3, [r7, #60] @ 0x3c 8003388: 6a1b ldr r3, [r3, #32] 800338a: ed93 7a00 vldr s14, [r3] 800338e: 6bfb ldr r3, [r7, #60] @ 0x3c 8003390: 6a5b ldr r3, [r3, #36] @ 0x24 8003392: edd3 7a00 vldr s15, [r3] 8003396: ee77 7a67 vsub.f32 s15, s14, s15 800339a: eefd 7ae7 vcvt.s32.f32 s15, s15 800339e: ee17 3a90 vmov r3, s15 80033a2: 2b05 cmp r3, #5 80033a4: f300 8084 bgt.w 80034b0 movementPhase = slowDownPhase; 80033a8: 2304 movs r3, #4 80033aa: f887 3057 strb.w r3, [r7, #87] @ 0x57 #ifdef DBG_POSITION printf ("Axe %c slow down phase\n", posCtrlTaskArg->axe); #endif } break; 80033ae: e07f b.n 80034b0 case slowDownPhase: pwmValue = MOTOR_START_STOP_PWM_VALUE; 80033b0: 233c movs r3, #60 @ 0x3c 80033b2: 65fb str r3, [r7, #92] @ 0x5c motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80033b4: 6bfb ldr r3, [r7, #60] @ 0x3c 80033b6: 681d ldr r5, [r3, #0] 80033b8: 6bfb ldr r3, [r7, #60] @ 0x3c 80033ba: 685e ldr r6, [r3, #4] 80033bc: 6bfb ldr r3, [r7, #60] @ 0x3c 80033be: f893 c008 ldrb.w ip, [r3, #8] 80033c2: 6bfb ldr r3, [r7, #60] @ 0x3c 80033c4: f893 e009 ldrb.w lr, [r3, #9] 80033c8: 6bfb ldr r3, [r7, #60] @ 0x3c 80033ca: 68db ldr r3, [r3, #12] 80033cc: 6dba ldr r2, [r7, #88] @ 0x58 80033ce: 6df9 ldr r1, [r7, #92] @ 0x5c 80033d0: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80033d4: 6bf9 ldr r1, [r7, #60] @ 0x3c 80033d6: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80033d8: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80033da: 6bf8 ldr r0, [r7, #60] @ 0x3c 80033dc: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80033de: 7800 ldrb r0, [r0, #0] 80033e0: 9004 str r0, [sp, #16] 80033e2: 9103 str r1, [sp, #12] 80033e4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80033e8: 9102 str r1, [sp, #8] 80033ea: 9201 str r2, [sp, #4] 80033ec: 9300 str r3, [sp, #0] 80033ee: 4673 mov r3, lr 80033f0: 4662 mov r2, ip 80033f2: 4631 mov r1, r6 80033f4: 4628 mov r0, r5 80033f6: f7ff fbad bl 8002b54 80033fa: 4603 mov r3, r0 80033fc: 63bb str r3, [r7, #56] @ 0x38 *posCtrlTaskArg->motorStatus = motorStatus; 80033fe: 6bfb ldr r3, [r7, #60] @ 0x3c 8003400: 6a9b ldr r3, [r3, #40] @ 0x28 8003402: 6bba ldr r2, [r7, #56] @ 0x38 8003404: b2d2 uxtb r2, r2 8003406: 701a strb r2, [r3, #0] movementPhase = stopPhase; 8003408: 2305 movs r3, #5 800340a: f887 3057 strb.w r3, [r7, #87] @ 0x57 timeLeftMS = 0; 800340e: 2300 movs r3, #0 8003410: 64bb str r3, [r7, #72] @ 0x48 #ifdef DBG_POSITION printf ("Axe %c stop phase\n", posCtrlTaskArg->axe); #endif break; 8003412: e050 b.n 80034b6 case stopPhase: float posDiff = sign > 0 ? posCtrlData.positionSettingValue - *posCtrlTaskArg->currentPosition : *posCtrlTaskArg->currentPosition - posCtrlData.positionSettingValue; 8003414: 6dbb ldr r3, [r7, #88] @ 0x58 8003416: 2b00 cmp r3, #0 8003418: dd08 ble.n 800342c 800341a: ed94 7a00 vldr s14, [r4] 800341e: 6bfb ldr r3, [r7, #60] @ 0x3c 8003420: 6a1b ldr r3, [r3, #32] 8003422: edd3 7a00 vldr s15, [r3] 8003426: ee77 7a67 vsub.f32 s15, s14, s15 800342a: e007 b.n 800343c 800342c: 6bfb ldr r3, [r7, #60] @ 0x3c 800342e: 6a1b ldr r3, [r3, #32] 8003430: ed93 7a00 vldr s14, [r3] 8003434: edd4 7a00 vldr s15, [r4] 8003438: ee77 7a67 vsub.f32 s15, s14, s15 800343c: edc7 7a0c vstr s15, [r7, #48] @ 0x30 if ((posDiff <= 0) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) { 8003440: edd7 7a0c vldr s15, [r7, #48] @ 0x30 8003444: eef5 7ac0 vcmpe.f32 s15, #0.0 8003448: eef1 fa10 vmrs APSR_nzcv, fpscr 800344c: d904 bls.n 8003458 800344e: 6cbb ldr r3, [r7, #72] @ 0x48 8003450: f241 3287 movw r2, #4999 @ 0x1387 8003454: 4293 cmp r3, r2 8003456: dd2d ble.n 80034b4 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003458: 6bfb ldr r3, [r7, #60] @ 0x3c 800345a: 6818 ldr r0, [r3, #0] 800345c: 6bfb ldr r3, [r7, #60] @ 0x3c 800345e: 685d ldr r5, [r3, #4] 8003460: 6bfb ldr r3, [r7, #60] @ 0x3c 8003462: 7a1e ldrb r6, [r3, #8] 8003464: 6bfb ldr r3, [r7, #60] @ 0x3c 8003466: f893 c009 ldrb.w ip, [r3, #9] 800346a: 6bfb ldr r3, [r7, #60] @ 0x3c 800346c: 68db ldr r3, [r3, #12] 0, 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 800346e: 6bfa ldr r2, [r7, #60] @ 0x3c 8003470: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003472: 7812 ldrb r2, [r2, #0] 0, 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003474: 6bf9 ldr r1, [r7, #60] @ 0x3c 8003476: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003478: 7809 ldrb r1, [r1, #0] 800347a: 9104 str r1, [sp, #16] 800347c: 9203 str r2, [sp, #12] 800347e: 2200 movs r2, #0 8003480: 9202 str r2, [sp, #8] 8003482: 2200 movs r2, #0 8003484: 9201 str r2, [sp, #4] 8003486: 9300 str r3, [sp, #0] 8003488: 4663 mov r3, ip 800348a: 4632 mov r2, r6 800348c: 4629 mov r1, r5 800348e: f7ff fb61 bl 8002b54 8003492: 4603 mov r3, r0 8003494: 63bb str r3, [r7, #56] @ 0x38 *posCtrlTaskArg->motorStatus = motorStatus; 8003496: 6bfb ldr r3, [r7, #60] @ 0x3c 8003498: 6a9b ldr r3, [r3, #40] @ 0x28 800349a: 6bba ldr r2, [r7, #56] @ 0x38 800349c: b2d2 uxtb r2, r2 800349e: 701a strb r2, [r3, #0] movementPhase = idlePhase; 80034a0: 2300 movs r3, #0 80034a2: f887 3057 strb.w r3, [r7, #87] @ 0x57 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); #endif } break; 80034a6: e005 b.n 80034b4 default: break; 80034a8: bf00 nop 80034aa: e011 b.n 80034d0 break; 80034ac: bf00 nop 80034ae: e00f b.n 80034d0 break; 80034b0: bf00 nop 80034b2: e00d b.n 80034d0 break; 80034b4: bf00 nop switch (movementPhase) { 80034b6: e00b b.n 80034d0 } } else { if ((*posCtrlTaskArg->motorStatus == 0) && (movementPhase != idlePhase)) { 80034b8: 6bfb ldr r3, [r7, #60] @ 0x3c 80034ba: 6a9b ldr r3, [r3, #40] @ 0x28 80034bc: 781b ldrb r3, [r3, #0] 80034be: 2b00 cmp r3, #0 80034c0: d106 bne.n 80034d0 80034c2: f897 3057 ldrb.w r3, [r7, #87] @ 0x57 80034c6: 2b00 cmp r3, #0 80034c8: d002 beq.n 80034d0 movementPhase = idlePhase; 80034ca: 2300 movs r3, #0 80034cc: f887 3057 strb.w r3, [r7, #87] @ 0x57 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); #endif } } osMutexRelease (sensorsInfoMutex); 80034d0: 4b02 ldr r3, [pc, #8] @ (80034dc ) 80034d2: 681b ldr r3, [r3, #0] 80034d4: 4618 mov r0, r3 80034d6: f010 fab9 bl 8013a4c queueSatus = osMessageQueueGet (posCtrlTaskArg->positionSettingQueue, &posCtrlData, 0, pdMS_TO_TICKS (PositionControlTaskTimeOut)); 80034da: e5b9 b.n 8003050 80034dc: 240008dc .word 0x240008dc 080034e0 : buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); } *buffPos = newBuffPos; } void WriteDataToBuffer (uint8_t* buff, uint16_t* buffPos, void* data, uint8_t dataSize) { 80034e0: b480 push {r7} 80034e2: b089 sub sp, #36 @ 0x24 80034e4: af00 add r7, sp, #0 80034e6: 60f8 str r0, [r7, #12] 80034e8: 60b9 str r1, [r7, #8] 80034ea: 607a str r2, [r7, #4] 80034ec: 70fb strb r3, [r7, #3] uint32_t* uDataPtr = data; 80034ee: 687b ldr r3, [r7, #4] 80034f0: 61bb str r3, [r7, #24] uint32_t uData = *uDataPtr; 80034f2: 69bb ldr r3, [r7, #24] 80034f4: 681b ldr r3, [r3, #0] 80034f6: 617b str r3, [r7, #20] uint8_t i = 0; 80034f8: 2300 movs r3, #0 80034fa: 77fb strb r3, [r7, #31] uint8_t newBuffPos = *buffPos; 80034fc: 68bb ldr r3, [r7, #8] 80034fe: 881b ldrh r3, [r3, #0] 8003500: 77bb strb r3, [r7, #30] for (i = 0; i < dataSize; i++) { 8003502: 2300 movs r3, #0 8003504: 77fb strb r3, [r7, #31] 8003506: e00e b.n 8003526 buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); 8003508: 7ffb ldrb r3, [r7, #31] 800350a: 00db lsls r3, r3, #3 800350c: 697a ldr r2, [r7, #20] 800350e: 40da lsrs r2, r3 8003510: 7fbb ldrb r3, [r7, #30] 8003512: 1c59 adds r1, r3, #1 8003514: 77b9 strb r1, [r7, #30] 8003516: 4619 mov r1, r3 8003518: 68fb ldr r3, [r7, #12] 800351a: 440b add r3, r1 800351c: b2d2 uxtb r2, r2 800351e: 701a strb r2, [r3, #0] for (i = 0; i < dataSize; i++) { 8003520: 7ffb ldrb r3, [r7, #31] 8003522: 3301 adds r3, #1 8003524: 77fb strb r3, [r7, #31] 8003526: 7ffa ldrb r2, [r7, #31] 8003528: 78fb ldrb r3, [r7, #3] 800352a: 429a cmp r2, r3 800352c: d3ec bcc.n 8003508 } *buffPos = newBuffPos; 800352e: 7fbb ldrb r3, [r7, #30] 8003530: b29a uxth r2, r3 8003532: 68bb ldr r3, [r7, #8] 8003534: 801a strh r2, [r3, #0] } 8003536: bf00 nop 8003538: 3724 adds r7, #36 @ 0x24 800353a: 46bd mov sp, r7 800353c: f85d 7b04 ldr.w r7, [sp], #4 8003540: 4770 bx lr 08003542 : void ReadFloatFromBuffer(uint8_t* buff, uint16_t* buffPos, float* data) { 8003542: b480 push {r7} 8003544: b087 sub sp, #28 8003546: af00 add r7, sp, #0 8003548: 60f8 str r0, [r7, #12] 800354a: 60b9 str r1, [r7, #8] 800354c: 607a str r2, [r7, #4] uint32_t* word = (uint32_t *)data; 800354e: 687b ldr r3, [r7, #4] 8003550: 617b str r3, [r7, #20] *word = CONVERT_BYTES_TO_WORD(&buff[*buffPos]); 8003552: 68bb ldr r3, [r7, #8] 8003554: 881b ldrh r3, [r3, #0] 8003556: 3303 adds r3, #3 8003558: 68fa ldr r2, [r7, #12] 800355a: 4413 add r3, r2 800355c: 781b ldrb r3, [r3, #0] 800355e: 061a lsls r2, r3, #24 8003560: 68bb ldr r3, [r7, #8] 8003562: 881b ldrh r3, [r3, #0] 8003564: 3302 adds r3, #2 8003566: 68f9 ldr r1, [r7, #12] 8003568: 440b add r3, r1 800356a: 781b ldrb r3, [r3, #0] 800356c: 041b lsls r3, r3, #16 800356e: 431a orrs r2, r3 8003570: 68bb ldr r3, [r7, #8] 8003572: 881b ldrh r3, [r3, #0] 8003574: 3301 adds r3, #1 8003576: 68f9 ldr r1, [r7, #12] 8003578: 440b add r3, r1 800357a: 781b ldrb r3, [r3, #0] 800357c: 021b lsls r3, r3, #8 800357e: 4313 orrs r3, r2 8003580: 68ba ldr r2, [r7, #8] 8003582: 8812 ldrh r2, [r2, #0] 8003584: 4611 mov r1, r2 8003586: 68fa ldr r2, [r7, #12] 8003588: 440a add r2, r1 800358a: 7812 ldrb r2, [r2, #0] 800358c: 4313 orrs r3, r2 800358e: 461a mov r2, r3 8003590: 697b ldr r3, [r7, #20] 8003592: 601a str r2, [r3, #0] *buffPos += sizeof(float); 8003594: 68bb ldr r3, [r7, #8] 8003596: 881b ldrh r3, [r3, #0] 8003598: 3304 adds r3, #4 800359a: b29a uxth r2, r3 800359c: 68bb ldr r3, [r7, #8] 800359e: 801a strh r2, [r3, #0] } 80035a0: bf00 nop 80035a2: 371c adds r7, #28 80035a4: 46bd mov sp, r7 80035a6: f85d 7b04 ldr.w r7, [sp], #4 80035aa: 4770 bx lr 080035ac : *data = CONVERT_BYTES_TO_SHORT_WORD(&buff[*buffPos]); *buffPos += sizeof(uint16_t); } void ReadWordFromBufer(uint8_t* buff, uint16_t* buffPos, uint32_t* data) { 80035ac: b480 push {r7} 80035ae: b085 sub sp, #20 80035b0: af00 add r7, sp, #0 80035b2: 60f8 str r0, [r7, #12] 80035b4: 60b9 str r1, [r7, #8] 80035b6: 607a str r2, [r7, #4] *data = CONVERT_BYTES_TO_WORD(&buff[*buffPos]); 80035b8: 68bb ldr r3, [r7, #8] 80035ba: 881b ldrh r3, [r3, #0] 80035bc: 3303 adds r3, #3 80035be: 68fa ldr r2, [r7, #12] 80035c0: 4413 add r3, r2 80035c2: 781b ldrb r3, [r3, #0] 80035c4: 061a lsls r2, r3, #24 80035c6: 68bb ldr r3, [r7, #8] 80035c8: 881b ldrh r3, [r3, #0] 80035ca: 3302 adds r3, #2 80035cc: 68f9 ldr r1, [r7, #12] 80035ce: 440b add r3, r1 80035d0: 781b ldrb r3, [r3, #0] 80035d2: 041b lsls r3, r3, #16 80035d4: 431a orrs r2, r3 80035d6: 68bb ldr r3, [r7, #8] 80035d8: 881b ldrh r3, [r3, #0] 80035da: 3301 adds r3, #1 80035dc: 68f9 ldr r1, [r7, #12] 80035de: 440b add r3, r1 80035e0: 781b ldrb r3, [r3, #0] 80035e2: 021b lsls r3, r3, #8 80035e4: 4313 orrs r3, r2 80035e6: 68ba ldr r2, [r7, #8] 80035e8: 8812 ldrh r2, [r2, #0] 80035ea: 4611 mov r1, r2 80035ec: 68fa ldr r2, [r7, #12] 80035ee: 440a add r2, r1 80035f0: 7812 ldrb r2, [r2, #0] 80035f2: 4313 orrs r3, r2 80035f4: 461a mov r2, r3 80035f6: 687b ldr r3, [r7, #4] 80035f8: 601a str r2, [r3, #0] *buffPos += sizeof(uint32_t); 80035fa: 68bb ldr r3, [r7, #8] 80035fc: 881b ldrh r3, [r3, #0] 80035fe: 3304 adds r3, #4 8003600: b29a uxth r2, r3 8003602: 68bb ldr r3, [r7, #8] 8003604: 801a strh r2, [r3, #0] } 8003606: bf00 nop 8003608: 3714 adds r7, #20 800360a: 46bd mov sp, r7 800360c: f85d 7b04 ldr.w r7, [sp], #4 8003610: 4770 bx lr ... 08003614 : txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); return txBufferPos; } uint16_t PrepareRespFrame (uint8_t* txBuffer, uint16_t frameId, SerialProtocolCommands frameCommand, SerialProtocolRespStatus respStatus, uint8_t* dataBuffer, uint16_t dataLength) { 8003614: b580 push {r7, lr} 8003616: b084 sub sp, #16 8003618: af00 add r7, sp, #0 800361a: 6078 str r0, [r7, #4] 800361c: 4608 mov r0, r1 800361e: 4611 mov r1, r2 8003620: 461a mov r2, r3 8003622: 4603 mov r3, r0 8003624: 807b strh r3, [r7, #2] 8003626: 460b mov r3, r1 8003628: 707b strb r3, [r7, #1] 800362a: 4613 mov r3, r2 800362c: 703b strb r3, [r7, #0] uint16_t crc = 0; 800362e: 2300 movs r3, #0 8003630: 81bb strh r3, [r7, #12] uint16_t txBufferPos = 0; 8003632: 2300 movs r3, #0 8003634: 81fb strh r3, [r7, #14] uint16_t frameCmd = ((uint16_t)frameCommand) | 0x8000; // MSB set means response 8003636: 787b ldrb r3, [r7, #1] 8003638: b21a sxth r2, r3 800363a: 4b43 ldr r3, [pc, #268] @ (8003748 ) 800363c: 4313 orrs r3, r2 800363e: b21b sxth r3, r3 8003640: 817b strh r3, [r7, #10] memset (txBuffer, 0x00, dataLength); 8003642: 8bbb ldrh r3, [r7, #28] 8003644: 461a mov r2, r3 8003646: 2100 movs r1, #0 8003648: 6878 ldr r0, [r7, #4] 800364a: f014 ff0d bl 8018468 txBuffer[txBufferPos++] = FRAME_INDICATOR; 800364e: 89fb ldrh r3, [r7, #14] 8003650: 1c5a adds r2, r3, #1 8003652: 81fa strh r2, [r7, #14] 8003654: 461a mov r2, r3 8003656: 687b ldr r3, [r7, #4] 8003658: 4413 add r3, r2 800365a: 22aa movs r2, #170 @ 0xaa 800365c: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameId); 800365e: 89fb ldrh r3, [r7, #14] 8003660: 1c5a adds r2, r3, #1 8003662: 81fa strh r2, [r7, #14] 8003664: 461a mov r2, r3 8003666: 687b ldr r3, [r7, #4] 8003668: 4413 add r3, r2 800366a: 887a ldrh r2, [r7, #2] 800366c: b2d2 uxtb r2, r2 800366e: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameId); 8003670: 887b ldrh r3, [r7, #2] 8003672: 0a1b lsrs r3, r3, #8 8003674: b29a uxth r2, r3 8003676: 89fb ldrh r3, [r7, #14] 8003678: 1c59 adds r1, r3, #1 800367a: 81f9 strh r1, [r7, #14] 800367c: 4619 mov r1, r3 800367e: 687b ldr r3, [r7, #4] 8003680: 440b add r3, r1 8003682: b2d2 uxtb r2, r2 8003684: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameCmd); 8003686: 89fb ldrh r3, [r7, #14] 8003688: 1c5a adds r2, r3, #1 800368a: 81fa strh r2, [r7, #14] 800368c: 461a mov r2, r3 800368e: 687b ldr r3, [r7, #4] 8003690: 4413 add r3, r2 8003692: 897a ldrh r2, [r7, #10] 8003694: b2d2 uxtb r2, r2 8003696: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameCmd); 8003698: 897b ldrh r3, [r7, #10] 800369a: 0a1b lsrs r3, r3, #8 800369c: b29a uxth r2, r3 800369e: 89fb ldrh r3, [r7, #14] 80036a0: 1c59 adds r1, r3, #1 80036a2: 81f9 strh r1, [r7, #14] 80036a4: 4619 mov r1, r3 80036a6: 687b ldr r3, [r7, #4] 80036a8: 440b add r3, r1 80036aa: b2d2 uxtb r2, r2 80036ac: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (dataLength); 80036ae: 89fb ldrh r3, [r7, #14] 80036b0: 1c5a adds r2, r3, #1 80036b2: 81fa strh r2, [r7, #14] 80036b4: 461a mov r2, r3 80036b6: 687b ldr r3, [r7, #4] 80036b8: 4413 add r3, r2 80036ba: 8bba ldrh r2, [r7, #28] 80036bc: b2d2 uxtb r2, r2 80036be: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (dataLength); 80036c0: 8bbb ldrh r3, [r7, #28] 80036c2: 0a1b lsrs r3, r3, #8 80036c4: b29a uxth r2, r3 80036c6: 89fb ldrh r3, [r7, #14] 80036c8: 1c59 adds r1, r3, #1 80036ca: 81f9 strh r1, [r7, #14] 80036cc: 4619 mov r1, r3 80036ce: 687b ldr r3, [r7, #4] 80036d0: 440b add r3, r1 80036d2: b2d2 uxtb r2, r2 80036d4: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = (uint8_t)respStatus; 80036d6: 89fb ldrh r3, [r7, #14] 80036d8: 1c5a adds r2, r3, #1 80036da: 81fa strh r2, [r7, #14] 80036dc: 461a mov r2, r3 80036de: 687b ldr r3, [r7, #4] 80036e0: 4413 add r3, r2 80036e2: 783a ldrb r2, [r7, #0] 80036e4: 701a strb r2, [r3, #0] if (dataLength > 0) { 80036e6: 8bbb ldrh r3, [r7, #28] 80036e8: 2b00 cmp r3, #0 80036ea: d00b beq.n 8003704 memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength); 80036ec: 89fb ldrh r3, [r7, #14] 80036ee: 687a ldr r2, [r7, #4] 80036f0: 4413 add r3, r2 80036f2: 8bba ldrh r2, [r7, #28] 80036f4: 69b9 ldr r1, [r7, #24] 80036f6: 4618 mov r0, r3 80036f8: f014 ff8b bl 8018612 txBufferPos += dataLength; 80036fc: 89fa ldrh r2, [r7, #14] 80036fe: 8bbb ldrh r3, [r7, #28] 8003700: 4413 add r3, r2 8003702: 81fb strh r3, [r7, #14] } crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)txBuffer, txBufferPos); 8003704: 89fb ldrh r3, [r7, #14] 8003706: 461a mov r2, r3 8003708: 6879 ldr r1, [r7, #4] 800370a: 4810 ldr r0, [pc, #64] @ (800374c ) 800370c: f004 f962 bl 80079d4 8003710: 4603 mov r3, r0 8003712: 81bb strh r3, [r7, #12] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (crc); 8003714: 89fb ldrh r3, [r7, #14] 8003716: 1c5a adds r2, r3, #1 8003718: 81fa strh r2, [r7, #14] 800371a: 461a mov r2, r3 800371c: 687b ldr r3, [r7, #4] 800371e: 4413 add r3, r2 8003720: 89ba ldrh r2, [r7, #12] 8003722: b2d2 uxtb r2, r2 8003724: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); 8003726: 89bb ldrh r3, [r7, #12] 8003728: 0a1b lsrs r3, r3, #8 800372a: b29a uxth r2, r3 800372c: 89fb ldrh r3, [r7, #14] 800372e: 1c59 adds r1, r3, #1 8003730: 81f9 strh r1, [r7, #14] 8003732: 4619 mov r1, r3 8003734: 687b ldr r3, [r7, #4] 8003736: 440b add r3, r1 8003738: b2d2 uxtb r2, r2 800373a: 701a strb r2, [r3, #0] return txBufferPos; 800373c: 89fb ldrh r3, [r7, #14] } 800373e: 4618 mov r0, r3 8003740: 3710 adds r7, #16 8003742: 46bd mov sp, r7 8003744: bd80 pop {r7, pc} 8003746: bf00 nop 8003748: ffff8000 .word 0xffff8000 800374c: 24000540 .word 0x24000540 08003750 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8003750: b580 push {r7, lr} 8003752: b086 sub sp, #24 8003754: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ PWREx_AVDTypeDef sConfigAVD = {0}; 8003756: f107 0310 add.w r3, r7, #16 800375a: 2200 movs r2, #0 800375c: 601a str r2, [r3, #0] 800375e: 605a str r2, [r3, #4] PWR_PVDTypeDef sConfigPVD = {0}; 8003760: f107 0308 add.w r3, r7, #8 8003764: 2200 movs r2, #0 8003766: 601a str r2, [r3, #0] 8003768: 605a str r2, [r3, #4] __HAL_RCC_SYSCFG_CLK_ENABLE(); 800376a: 4b26 ldr r3, [pc, #152] @ (8003804 ) 800376c: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003770: 4a24 ldr r2, [pc, #144] @ (8003804 ) 8003772: f043 0302 orr.w r3, r3, #2 8003776: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 800377a: 4b22 ldr r3, [pc, #136] @ (8003804 ) 800377c: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003780: f003 0302 and.w r3, r3, #2 8003784: 607b str r3, [r7, #4] 8003786: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 8003788: 2200 movs r2, #0 800378a: 210f movs r1, #15 800378c: f06f 0001 mvn.w r0, #1 8003790: f004 f81c bl 80077cc /* Peripheral interrupt init */ /* RCC_IRQn interrupt configuration */ HAL_NVIC_SetPriority(RCC_IRQn, 5, 0); 8003794: 2200 movs r2, #0 8003796: 2105 movs r1, #5 8003798: 2005 movs r0, #5 800379a: f004 f817 bl 80077cc HAL_NVIC_EnableIRQ(RCC_IRQn); 800379e: 2005 movs r0, #5 80037a0: f004 f82e bl 8007800 /** AVD Configuration */ sConfigAVD.AVDLevel = PWR_AVDLEVEL_3; 80037a4: f44f 23c0 mov.w r3, #393216 @ 0x60000 80037a8: 613b str r3, [r7, #16] sConfigAVD.Mode = PWR_AVD_MODE_NORMAL; 80037aa: 2300 movs r3, #0 80037ac: 617b str r3, [r7, #20] HAL_PWREx_ConfigAVD(&sConfigAVD); 80037ae: f107 0310 add.w r3, r7, #16 80037b2: 4618 mov r0, r3 80037b4: f007 fe74 bl 800b4a0 /** Enable the AVD Output */ HAL_PWREx_EnableAVD(); 80037b8: f007 fee8 bl 800b58c /** PVD Configuration */ sConfigPVD.PVDLevel = PWR_PVDLEVEL_6; 80037bc: 23c0 movs r3, #192 @ 0xc0 80037be: 60bb str r3, [r7, #8] sConfigPVD.Mode = PWR_PVD_MODE_NORMAL; 80037c0: 2300 movs r3, #0 80037c2: 60fb str r3, [r7, #12] HAL_PWR_ConfigPVD(&sConfigPVD); 80037c4: f107 0308 add.w r3, r7, #8 80037c8: 4618 mov r0, r3 80037ca: f007 fda5 bl 800b318 /** Enable the PVD Output */ HAL_PWR_EnablePVD(); 80037ce: f007 fe1d bl 800b40c /** Enable the VREF clock */ __HAL_RCC_VREF_CLK_ENABLE(); 80037d2: 4b0c ldr r3, [pc, #48] @ (8003804 ) 80037d4: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 80037d8: 4a0a ldr r2, [pc, #40] @ (8003804 ) 80037da: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80037de: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 80037e2: 4b08 ldr r3, [pc, #32] @ (8003804 ) 80037e4: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 80037e8: f403 4300 and.w r3, r3, #32768 @ 0x8000 80037ec: 603b str r3, [r7, #0] 80037ee: 683b ldr r3, [r7, #0] /** Disable the Internal Voltage Reference buffer */ HAL_SYSCFG_DisableVREFBUF(); 80037f0: f002 f880 bl 80058f4 /** Configure the internal voltage reference buffer high impedance mode */ HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE); 80037f4: 2002 movs r0, #2 80037f6: f002 f869 bl 80058cc /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80037fa: bf00 nop 80037fc: 3718 adds r7, #24 80037fe: 46bd mov sp, r7 8003800: bd80 pop {r7, pc} 8003802: bf00 nop 8003804: 58024400 .word 0x58024400 08003808 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8003808: b580 push {r7, lr} 800380a: b092 sub sp, #72 @ 0x48 800380c: af00 add r7, sp, #0 800380e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003810: f107 0334 add.w r3, r7, #52 @ 0x34 8003814: 2200 movs r2, #0 8003816: 601a str r2, [r3, #0] 8003818: 605a str r2, [r3, #4] 800381a: 609a str r2, [r3, #8] 800381c: 60da str r2, [r3, #12] 800381e: 611a str r2, [r3, #16] if(hadc->Instance==ADC1) 8003820: 687b ldr r3, [r7, #4] 8003822: 681b ldr r3, [r3, #0] 8003824: 4a9d ldr r2, [pc, #628] @ (8003a9c ) 8003826: 4293 cmp r3, r2 8003828: f040 8099 bne.w 800395e { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; 800382c: 4b9c ldr r3, [pc, #624] @ (8003aa0 ) 800382e: 681b ldr r3, [r3, #0] 8003830: 3301 adds r3, #1 8003832: 4a9b ldr r2, [pc, #620] @ (8003aa0 ) 8003834: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8003836: 4b9a ldr r3, [pc, #616] @ (8003aa0 ) 8003838: 681b ldr r3, [r3, #0] 800383a: 2b01 cmp r3, #1 800383c: d10e bne.n 800385c __HAL_RCC_ADC12_CLK_ENABLE(); 800383e: 4b99 ldr r3, [pc, #612] @ (8003aa4 ) 8003840: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003844: 4a97 ldr r2, [pc, #604] @ (8003aa4 ) 8003846: f043 0320 orr.w r3, r3, #32 800384a: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 800384e: 4b95 ldr r3, [pc, #596] @ (8003aa4 ) 8003850: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003854: f003 0320 and.w r3, r3, #32 8003858: 633b str r3, [r7, #48] @ 0x30 800385a: 6b3b ldr r3, [r7, #48] @ 0x30 } __HAL_RCC_GPIOA_CLK_ENABLE(); 800385c: 4b91 ldr r3, [pc, #580] @ (8003aa4 ) 800385e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003862: 4a90 ldr r2, [pc, #576] @ (8003aa4 ) 8003864: f043 0301 orr.w r3, r3, #1 8003868: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800386c: 4b8d ldr r3, [pc, #564] @ (8003aa4 ) 800386e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003872: f003 0301 and.w r3, r3, #1 8003876: 62fb str r3, [r7, #44] @ 0x2c 8003878: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 800387a: 4b8a ldr r3, [pc, #552] @ (8003aa4 ) 800387c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003880: 4a88 ldr r2, [pc, #544] @ (8003aa4 ) 8003882: f043 0304 orr.w r3, r3, #4 8003886: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800388a: 4b86 ldr r3, [pc, #536] @ (8003aa4 ) 800388c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003890: f003 0304 and.w r3, r3, #4 8003894: 62bb str r3, [r7, #40] @ 0x28 8003896: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOB_CLK_ENABLE(); 8003898: 4b82 ldr r3, [pc, #520] @ (8003aa4 ) 800389a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800389e: 4a81 ldr r2, [pc, #516] @ (8003aa4 ) 80038a0: f043 0302 orr.w r3, r3, #2 80038a4: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80038a8: 4b7e ldr r3, [pc, #504] @ (8003aa4 ) 80038aa: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80038ae: f003 0302 and.w r3, r3, #2 80038b2: 627b str r3, [r7, #36] @ 0x24 80038b4: 6a7b ldr r3, [r7, #36] @ 0x24 PA3 ------> ADC1_INP15 PA7 ------> ADC1_INP7 PC5 ------> ADC1_INP8 PB0 ------> ADC1_INP9 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 80038b6: 238f movs r3, #143 @ 0x8f 80038b8: 637b str r3, [r7, #52] @ 0x34 |GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80038ba: 2303 movs r3, #3 80038bc: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 80038be: 2300 movs r3, #0 80038c0: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80038c2: f107 0334 add.w r3, r7, #52 @ 0x34 80038c6: 4619 mov r1, r3 80038c8: 4877 ldr r0, [pc, #476] @ (8003aa8 ) 80038ca: f007 fab1 bl 800ae30 GPIO_InitStruct.Pin = GPIO_PIN_5; 80038ce: 2320 movs r3, #32 80038d0: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80038d2: 2303 movs r3, #3 80038d4: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 80038d6: 2300 movs r3, #0 80038d8: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80038da: f107 0334 add.w r3, r7, #52 @ 0x34 80038de: 4619 mov r1, r3 80038e0: 4872 ldr r0, [pc, #456] @ (8003aac ) 80038e2: f007 faa5 bl 800ae30 GPIO_InitStruct.Pin = GPIO_PIN_0; 80038e6: 2301 movs r3, #1 80038e8: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80038ea: 2303 movs r3, #3 80038ec: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 80038ee: 2300 movs r3, #0 80038f0: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80038f2: f107 0334 add.w r3, r7, #52 @ 0x34 80038f6: 4619 mov r1, r3 80038f8: 486d ldr r0, [pc, #436] @ (8003ab0 ) 80038fa: f007 fa99 bl 800ae30 /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Stream0; 80038fe: 4b6d ldr r3, [pc, #436] @ (8003ab4 ) 8003900: 4a6d ldr r2, [pc, #436] @ (8003ab8 ) 8003902: 601a str r2, [r3, #0] hdma_adc1.Init.Request = DMA_REQUEST_ADC1; 8003904: 4b6b ldr r3, [pc, #428] @ (8003ab4 ) 8003906: 2209 movs r2, #9 8003908: 605a str r2, [r3, #4] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 800390a: 4b6a ldr r3, [pc, #424] @ (8003ab4 ) 800390c: 2200 movs r2, #0 800390e: 609a str r2, [r3, #8] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8003910: 4b68 ldr r3, [pc, #416] @ (8003ab4 ) 8003912: 2200 movs r2, #0 8003914: 60da str r2, [r3, #12] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8003916: 4b67 ldr r3, [pc, #412] @ (8003ab4 ) 8003918: f44f 6280 mov.w r2, #1024 @ 0x400 800391c: 611a str r2, [r3, #16] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 800391e: 4b65 ldr r3, [pc, #404] @ (8003ab4 ) 8003920: f44f 6200 mov.w r2, #2048 @ 0x800 8003924: 615a str r2, [r3, #20] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8003926: 4b63 ldr r3, [pc, #396] @ (8003ab4 ) 8003928: f44f 5200 mov.w r2, #8192 @ 0x2000 800392c: 619a str r2, [r3, #24] hdma_adc1.Init.Mode = DMA_NORMAL; 800392e: 4b61 ldr r3, [pc, #388] @ (8003ab4 ) 8003930: 2200 movs r2, #0 8003932: 61da str r2, [r3, #28] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; 8003934: 4b5f ldr r3, [pc, #380] @ (8003ab4 ) 8003936: 2200 movs r2, #0 8003938: 621a str r2, [r3, #32] hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 800393a: 4b5e ldr r3, [pc, #376] @ (8003ab4 ) 800393c: 2200 movs r2, #0 800393e: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 8003940: 485c ldr r0, [pc, #368] @ (8003ab4 ) 8003942: f004 fc39 bl 80081b8 8003946: 4603 mov r3, r0 8003948: 2b00 cmp r3, #0 800394a: d001 beq.n 8003950 { Error_Handler(); 800394c: f7fe f91e bl 8001b8c } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); 8003950: 687b ldr r3, [r7, #4] 8003952: 4a58 ldr r2, [pc, #352] @ (8003ab4 ) 8003954: 64da str r2, [r3, #76] @ 0x4c 8003956: 4a57 ldr r2, [pc, #348] @ (8003ab4 ) 8003958: 687b ldr r3, [r7, #4] 800395a: 6393 str r3, [r2, #56] @ 0x38 /* USER CODE BEGIN ADC3_MspInit 1 */ /* USER CODE END ADC3_MspInit 1 */ } } 800395c: e11e b.n 8003b9c else if(hadc->Instance==ADC2) 800395e: 687b ldr r3, [r7, #4] 8003960: 681b ldr r3, [r3, #0] 8003962: 4a56 ldr r2, [pc, #344] @ (8003abc ) 8003964: 4293 cmp r3, r2 8003966: f040 80af bne.w 8003ac8 HAL_RCC_ADC12_CLK_ENABLED++; 800396a: 4b4d ldr r3, [pc, #308] @ (8003aa0 ) 800396c: 681b ldr r3, [r3, #0] 800396e: 3301 adds r3, #1 8003970: 4a4b ldr r2, [pc, #300] @ (8003aa0 ) 8003972: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8003974: 4b4a ldr r3, [pc, #296] @ (8003aa0 ) 8003976: 681b ldr r3, [r3, #0] 8003978: 2b01 cmp r3, #1 800397a: d10e bne.n 800399a __HAL_RCC_ADC12_CLK_ENABLE(); 800397c: 4b49 ldr r3, [pc, #292] @ (8003aa4 ) 800397e: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003982: 4a48 ldr r2, [pc, #288] @ (8003aa4 ) 8003984: f043 0320 orr.w r3, r3, #32 8003988: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 800398c: 4b45 ldr r3, [pc, #276] @ (8003aa4 ) 800398e: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003992: f003 0320 and.w r3, r3, #32 8003996: 623b str r3, [r7, #32] 8003998: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 800399a: 4b42 ldr r3, [pc, #264] @ (8003aa4 ) 800399c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80039a0: 4a40 ldr r2, [pc, #256] @ (8003aa4 ) 80039a2: f043 0301 orr.w r3, r3, #1 80039a6: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80039aa: 4b3e ldr r3, [pc, #248] @ (8003aa4 ) 80039ac: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80039b0: f003 0301 and.w r3, r3, #1 80039b4: 61fb str r3, [r7, #28] 80039b6: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOC_CLK_ENABLE(); 80039b8: 4b3a ldr r3, [pc, #232] @ (8003aa4 ) 80039ba: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80039be: 4a39 ldr r2, [pc, #228] @ (8003aa4 ) 80039c0: f043 0304 orr.w r3, r3, #4 80039c4: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80039c8: 4b36 ldr r3, [pc, #216] @ (8003aa4 ) 80039ca: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80039ce: f003 0304 and.w r3, r3, #4 80039d2: 61bb str r3, [r7, #24] 80039d4: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 80039d6: 4b33 ldr r3, [pc, #204] @ (8003aa4 ) 80039d8: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80039dc: 4a31 ldr r2, [pc, #196] @ (8003aa4 ) 80039de: f043 0302 orr.w r3, r3, #2 80039e2: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80039e6: 4b2f ldr r3, [pc, #188] @ (8003aa4 ) 80039e8: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80039ec: f003 0302 and.w r3, r3, #2 80039f0: 617b str r3, [r7, #20] 80039f2: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_6; 80039f4: 2340 movs r3, #64 @ 0x40 80039f6: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80039f8: 2303 movs r3, #3 80039fa: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 80039fc: 2300 movs r3, #0 80039fe: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003a00: f107 0334 add.w r3, r7, #52 @ 0x34 8003a04: 4619 mov r1, r3 8003a06: 4828 ldr r0, [pc, #160] @ (8003aa8 ) 8003a08: f007 fa12 bl 800ae30 GPIO_InitStruct.Pin = GPIO_PIN_4; 8003a0c: 2310 movs r3, #16 8003a0e: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003a10: 2303 movs r3, #3 8003a12: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003a14: 2300 movs r3, #0 8003a16: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003a18: f107 0334 add.w r3, r7, #52 @ 0x34 8003a1c: 4619 mov r1, r3 8003a1e: 4823 ldr r0, [pc, #140] @ (8003aac ) 8003a20: f007 fa06 bl 800ae30 GPIO_InitStruct.Pin = GPIO_PIN_1; 8003a24: 2302 movs r3, #2 8003a26: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003a28: 2303 movs r3, #3 8003a2a: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003a2c: 2300 movs r3, #0 8003a2e: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003a30: f107 0334 add.w r3, r7, #52 @ 0x34 8003a34: 4619 mov r1, r3 8003a36: 481e ldr r0, [pc, #120] @ (8003ab0 ) 8003a38: f007 f9fa bl 800ae30 hdma_adc2.Instance = DMA1_Stream1; 8003a3c: 4b20 ldr r3, [pc, #128] @ (8003ac0 ) 8003a3e: 4a21 ldr r2, [pc, #132] @ (8003ac4 ) 8003a40: 601a str r2, [r3, #0] hdma_adc2.Init.Request = DMA_REQUEST_ADC2; 8003a42: 4b1f ldr r3, [pc, #124] @ (8003ac0 ) 8003a44: 220a movs r2, #10 8003a46: 605a str r2, [r3, #4] hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003a48: 4b1d ldr r3, [pc, #116] @ (8003ac0 ) 8003a4a: 2200 movs r2, #0 8003a4c: 609a str r2, [r3, #8] hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; 8003a4e: 4b1c ldr r3, [pc, #112] @ (8003ac0 ) 8003a50: 2200 movs r2, #0 8003a52: 60da str r2, [r3, #12] hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; 8003a54: 4b1a ldr r3, [pc, #104] @ (8003ac0 ) 8003a56: f44f 6280 mov.w r2, #1024 @ 0x400 8003a5a: 611a str r2, [r3, #16] hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8003a5c: 4b18 ldr r3, [pc, #96] @ (8003ac0 ) 8003a5e: f44f 6200 mov.w r2, #2048 @ 0x800 8003a62: 615a str r2, [r3, #20] hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8003a64: 4b16 ldr r3, [pc, #88] @ (8003ac0 ) 8003a66: f44f 5200 mov.w r2, #8192 @ 0x2000 8003a6a: 619a str r2, [r3, #24] hdma_adc2.Init.Mode = DMA_NORMAL; 8003a6c: 4b14 ldr r3, [pc, #80] @ (8003ac0 ) 8003a6e: 2200 movs r2, #0 8003a70: 61da str r2, [r3, #28] hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; 8003a72: 4b13 ldr r3, [pc, #76] @ (8003ac0 ) 8003a74: 2200 movs r2, #0 8003a76: 621a str r2, [r3, #32] hdma_adc2.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003a78: 4b11 ldr r3, [pc, #68] @ (8003ac0 ) 8003a7a: 2200 movs r2, #0 8003a7c: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) 8003a7e: 4810 ldr r0, [pc, #64] @ (8003ac0 ) 8003a80: f004 fb9a bl 80081b8 8003a84: 4603 mov r3, r0 8003a86: 2b00 cmp r3, #0 8003a88: d001 beq.n 8003a8e Error_Handler(); 8003a8a: f7fe f87f bl 8001b8c __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2); 8003a8e: 687b ldr r3, [r7, #4] 8003a90: 4a0b ldr r2, [pc, #44] @ (8003ac0 ) 8003a92: 64da str r2, [r3, #76] @ 0x4c 8003a94: 4a0a ldr r2, [pc, #40] @ (8003ac0 ) 8003a96: 687b ldr r3, [r7, #4] 8003a98: 6393 str r3, [r2, #56] @ 0x38 } 8003a9a: e07f b.n 8003b9c 8003a9c: 40022000 .word 0x40022000 8003aa0: 24000a74 .word 0x24000a74 8003aa4: 58024400 .word 0x58024400 8003aa8: 58020000 .word 0x58020000 8003aac: 58020800 .word 0x58020800 8003ab0: 58020400 .word 0x58020400 8003ab4: 240003ac .word 0x240003ac 8003ab8: 40020010 .word 0x40020010 8003abc: 40022100 .word 0x40022100 8003ac0: 24000424 .word 0x24000424 8003ac4: 40020028 .word 0x40020028 else if(hadc->Instance==ADC3) 8003ac8: 687b ldr r3, [r7, #4] 8003aca: 681b ldr r3, [r3, #0] 8003acc: 4a35 ldr r2, [pc, #212] @ (8003ba4 ) 8003ace: 4293 cmp r3, r2 8003ad0: d164 bne.n 8003b9c __HAL_RCC_ADC3_CLK_ENABLE(); 8003ad2: 4b35 ldr r3, [pc, #212] @ (8003ba8 ) 8003ad4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003ad8: 4a33 ldr r2, [pc, #204] @ (8003ba8 ) 8003ada: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8003ade: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003ae2: 4b31 ldr r3, [pc, #196] @ (8003ba8 ) 8003ae4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003ae8: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8003aec: 613b str r3, [r7, #16] 8003aee: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 8003af0: 4b2d ldr r3, [pc, #180] @ (8003ba8 ) 8003af2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003af6: 4a2c ldr r2, [pc, #176] @ (8003ba8 ) 8003af8: f043 0304 orr.w r3, r3, #4 8003afc: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003b00: 4b29 ldr r3, [pc, #164] @ (8003ba8 ) 8003b02: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003b06: f003 0304 and.w r3, r3, #4 8003b0a: 60fb str r3, [r7, #12] 8003b0c: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8003b0e: 2303 movs r3, #3 8003b10: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003b12: 2303 movs r3, #3 8003b14: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003b16: 2300 movs r3, #0 8003b18: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003b1a: f107 0334 add.w r3, r7, #52 @ 0x34 8003b1e: 4619 mov r1, r3 8003b20: 4822 ldr r0, [pc, #136] @ (8003bac ) 8003b22: f007 f985 bl 800ae30 HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC2, SYSCFG_SWITCH_PC2_OPEN); 8003b26: f04f 6180 mov.w r1, #67108864 @ 0x4000000 8003b2a: f04f 6080 mov.w r0, #67108864 @ 0x4000000 8003b2e: f001 fef1 bl 8005914 HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC3, SYSCFG_SWITCH_PC3_OPEN); 8003b32: f04f 6100 mov.w r1, #134217728 @ 0x8000000 8003b36: f04f 6000 mov.w r0, #134217728 @ 0x8000000 8003b3a: f001 feeb bl 8005914 hdma_adc3.Instance = DMA1_Stream2; 8003b3e: 4b1c ldr r3, [pc, #112] @ (8003bb0 ) 8003b40: 4a1c ldr r2, [pc, #112] @ (8003bb4 ) 8003b42: 601a str r2, [r3, #0] hdma_adc3.Init.Request = DMA_REQUEST_ADC3; 8003b44: 4b1a ldr r3, [pc, #104] @ (8003bb0 ) 8003b46: 2273 movs r2, #115 @ 0x73 8003b48: 605a str r2, [r3, #4] hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003b4a: 4b19 ldr r3, [pc, #100] @ (8003bb0 ) 8003b4c: 2200 movs r2, #0 8003b4e: 609a str r2, [r3, #8] hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE; 8003b50: 4b17 ldr r3, [pc, #92] @ (8003bb0 ) 8003b52: 2200 movs r2, #0 8003b54: 60da str r2, [r3, #12] hdma_adc3.Init.MemInc = DMA_MINC_ENABLE; 8003b56: 4b16 ldr r3, [pc, #88] @ (8003bb0 ) 8003b58: f44f 6280 mov.w r2, #1024 @ 0x400 8003b5c: 611a str r2, [r3, #16] hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8003b5e: 4b14 ldr r3, [pc, #80] @ (8003bb0 ) 8003b60: f44f 6200 mov.w r2, #2048 @ 0x800 8003b64: 615a str r2, [r3, #20] hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8003b66: 4b12 ldr r3, [pc, #72] @ (8003bb0 ) 8003b68: f44f 5200 mov.w r2, #8192 @ 0x2000 8003b6c: 619a str r2, [r3, #24] hdma_adc3.Init.Mode = DMA_NORMAL; 8003b6e: 4b10 ldr r3, [pc, #64] @ (8003bb0 ) 8003b70: 2200 movs r2, #0 8003b72: 61da str r2, [r3, #28] hdma_adc3.Init.Priority = DMA_PRIORITY_LOW; 8003b74: 4b0e ldr r3, [pc, #56] @ (8003bb0 ) 8003b76: 2200 movs r2, #0 8003b78: 621a str r2, [r3, #32] hdma_adc3.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003b7a: 4b0d ldr r3, [pc, #52] @ (8003bb0 ) 8003b7c: 2200 movs r2, #0 8003b7e: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc3) != HAL_OK) 8003b80: 480b ldr r0, [pc, #44] @ (8003bb0 ) 8003b82: f004 fb19 bl 80081b8 8003b86: 4603 mov r3, r0 8003b88: 2b00 cmp r3, #0 8003b8a: d001 beq.n 8003b90 Error_Handler(); 8003b8c: f7fd fffe bl 8001b8c __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc3); 8003b90: 687b ldr r3, [r7, #4] 8003b92: 4a07 ldr r2, [pc, #28] @ (8003bb0 ) 8003b94: 64da str r2, [r3, #76] @ 0x4c 8003b96: 4a06 ldr r2, [pc, #24] @ (8003bb0 ) 8003b98: 687b ldr r3, [r7, #4] 8003b9a: 6393 str r3, [r2, #56] @ 0x38 } 8003b9c: bf00 nop 8003b9e: 3748 adds r7, #72 @ 0x48 8003ba0: 46bd mov sp, r7 8003ba2: bd80 pop {r7, pc} 8003ba4: 58026000 .word 0x58026000 8003ba8: 58024400 .word 0x58024400 8003bac: 58020800 .word 0x58020800 8003bb0: 2400049c .word 0x2400049c 8003bb4: 40020040 .word 0x40020040 08003bb8 : * This function configures the hardware resources used in this example * @param hcomp: COMP handle pointer * @retval None */ void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp) { 8003bb8: b580 push {r7, lr} 8003bba: b08a sub sp, #40 @ 0x28 8003bbc: af00 add r7, sp, #0 8003bbe: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003bc0: f107 0314 add.w r3, r7, #20 8003bc4: 2200 movs r2, #0 8003bc6: 601a str r2, [r3, #0] 8003bc8: 605a str r2, [r3, #4] 8003bca: 609a str r2, [r3, #8] 8003bcc: 60da str r2, [r3, #12] 8003bce: 611a str r2, [r3, #16] if(hcomp->Instance==COMP1) 8003bd0: 687b ldr r3, [r7, #4] 8003bd2: 681b ldr r3, [r3, #0] 8003bd4: 4a18 ldr r2, [pc, #96] @ (8003c38 ) 8003bd6: 4293 cmp r3, r2 8003bd8: d129 bne.n 8003c2e { /* USER CODE BEGIN COMP1_MspInit 0 */ /* USER CODE END COMP1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_COMP12_CLK_ENABLE(); 8003bda: 4b18 ldr r3, [pc, #96] @ (8003c3c ) 8003bdc: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003be0: 4a16 ldr r2, [pc, #88] @ (8003c3c ) 8003be2: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8003be6: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8003bea: 4b14 ldr r3, [pc, #80] @ (8003c3c ) 8003bec: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003bf0: f403 4380 and.w r3, r3, #16384 @ 0x4000 8003bf4: 613b str r3, [r7, #16] 8003bf6: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8003bf8: 4b10 ldr r3, [pc, #64] @ (8003c3c ) 8003bfa: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003bfe: 4a0f ldr r2, [pc, #60] @ (8003c3c ) 8003c00: f043 0302 orr.w r3, r3, #2 8003c04: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003c08: 4b0c ldr r3, [pc, #48] @ (8003c3c ) 8003c0a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003c0e: f003 0302 and.w r3, r3, #2 8003c12: 60fb str r3, [r7, #12] 8003c14: 68fb ldr r3, [r7, #12] /**COMP1 GPIO Configuration PB2 ------> COMP1_INP */ GPIO_InitStruct.Pin = GPIO_PIN_2; 8003c16: 2304 movs r3, #4 8003c18: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003c1a: 2303 movs r3, #3 8003c1c: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003c1e: 2300 movs r3, #0 8003c20: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003c22: f107 0314 add.w r3, r7, #20 8003c26: 4619 mov r1, r3 8003c28: 4805 ldr r0, [pc, #20] @ (8003c40 ) 8003c2a: f007 f901 bl 800ae30 /* USER CODE BEGIN COMP1_MspInit 1 */ /* USER CODE END COMP1_MspInit 1 */ } } 8003c2e: bf00 nop 8003c30: 3728 adds r7, #40 @ 0x28 8003c32: 46bd mov sp, r7 8003c34: bd80 pop {r7, pc} 8003c36: bf00 nop 8003c38: 5800380c .word 0x5800380c 8003c3c: 58024400 .word 0x58024400 8003c40: 58020400 .word 0x58020400 08003c44 : * This function configures the hardware resources used in this example * @param hcrc: CRC handle pointer * @retval None */ void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) { 8003c44: b480 push {r7} 8003c46: b085 sub sp, #20 8003c48: af00 add r7, sp, #0 8003c4a: 6078 str r0, [r7, #4] if(hcrc->Instance==CRC) 8003c4c: 687b ldr r3, [r7, #4] 8003c4e: 681b ldr r3, [r3, #0] 8003c50: 4a0b ldr r2, [pc, #44] @ (8003c80 ) 8003c52: 4293 cmp r3, r2 8003c54: d10e bne.n 8003c74 { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 8003c56: 4b0b ldr r3, [pc, #44] @ (8003c84 ) 8003c58: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003c5c: 4a09 ldr r2, [pc, #36] @ (8003c84 ) 8003c5e: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8003c62: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003c66: 4b07 ldr r3, [pc, #28] @ (8003c84 ) 8003c68: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003c6c: f403 2300 and.w r3, r3, #524288 @ 0x80000 8003c70: 60fb str r3, [r7, #12] 8003c72: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 8003c74: bf00 nop 8003c76: 3714 adds r7, #20 8003c78: 46bd mov sp, r7 8003c7a: f85d 7b04 ldr.w r7, [sp], #4 8003c7e: 4770 bx lr 8003c80: 58024c00 .word 0x58024c00 8003c84: 58024400 .word 0x58024400 08003c88 : * This function configures the hardware resources used in this example * @param hdac: DAC handle pointer * @retval None */ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) { 8003c88: b580 push {r7, lr} 8003c8a: b08a sub sp, #40 @ 0x28 8003c8c: af00 add r7, sp, #0 8003c8e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003c90: f107 0314 add.w r3, r7, #20 8003c94: 2200 movs r2, #0 8003c96: 601a str r2, [r3, #0] 8003c98: 605a str r2, [r3, #4] 8003c9a: 609a str r2, [r3, #8] 8003c9c: 60da str r2, [r3, #12] 8003c9e: 611a str r2, [r3, #16] if(hdac->Instance==DAC1) 8003ca0: 687b ldr r3, [r7, #4] 8003ca2: 681b ldr r3, [r3, #0] 8003ca4: 4a1c ldr r2, [pc, #112] @ (8003d18 ) 8003ca6: 4293 cmp r3, r2 8003ca8: d131 bne.n 8003d0e { /* USER CODE BEGIN DAC1_MspInit 0 */ /* USER CODE END DAC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DAC12_CLK_ENABLE(); 8003caa: 4b1c ldr r3, [pc, #112] @ (8003d1c ) 8003cac: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003cb0: 4a1a ldr r2, [pc, #104] @ (8003d1c ) 8003cb2: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8003cb6: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8003cba: 4b18 ldr r3, [pc, #96] @ (8003d1c ) 8003cbc: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003cc0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8003cc4: 613b str r3, [r7, #16] 8003cc6: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8003cc8: 4b14 ldr r3, [pc, #80] @ (8003d1c ) 8003cca: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003cce: 4a13 ldr r2, [pc, #76] @ (8003d1c ) 8003cd0: f043 0301 orr.w r3, r3, #1 8003cd4: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003cd8: 4b10 ldr r3, [pc, #64] @ (8003d1c ) 8003cda: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003cde: f003 0301 and.w r3, r3, #1 8003ce2: 60fb str r3, [r7, #12] 8003ce4: 68fb ldr r3, [r7, #12] /**DAC1 GPIO Configuration PA4 ------> DAC1_OUT1 PA5 ------> DAC1_OUT2 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 8003ce6: 2330 movs r3, #48 @ 0x30 8003ce8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003cea: 2303 movs r3, #3 8003cec: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003cee: 2300 movs r3, #0 8003cf0: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003cf2: f107 0314 add.w r3, r7, #20 8003cf6: 4619 mov r1, r3 8003cf8: 4809 ldr r0, [pc, #36] @ (8003d20 ) 8003cfa: f007 f899 bl 800ae30 /* DAC1 interrupt Init */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 5, 0); 8003cfe: 2200 movs r2, #0 8003d00: 2105 movs r1, #5 8003d02: 2036 movs r0, #54 @ 0x36 8003d04: f003 fd62 bl 80077cc HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 8003d08: 2036 movs r0, #54 @ 0x36 8003d0a: f003 fd79 bl 8007800 /* USER CODE BEGIN DAC1_MspInit 1 */ /* USER CODE END DAC1_MspInit 1 */ } } 8003d0e: bf00 nop 8003d10: 3728 adds r7, #40 @ 0x28 8003d12: 46bd mov sp, r7 8003d14: bd80 pop {r7, pc} 8003d16: bf00 nop 8003d18: 40007400 .word 0x40007400 8003d1c: 58024400 .word 0x58024400 8003d20: 58020000 .word 0x58020000 08003d24 : * This function configures the hardware resources used in this example * @param hrng: RNG handle pointer * @retval None */ void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) { 8003d24: b580 push {r7, lr} 8003d26: b0b4 sub sp, #208 @ 0xd0 8003d28: af00 add r7, sp, #0 8003d2a: 6078 str r0, [r7, #4] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8003d2c: f107 0310 add.w r3, r7, #16 8003d30: 22c0 movs r2, #192 @ 0xc0 8003d32: 2100 movs r1, #0 8003d34: 4618 mov r0, r3 8003d36: f014 fb97 bl 8018468 if(hrng->Instance==RNG) 8003d3a: 687b ldr r3, [r7, #4] 8003d3c: 681b ldr r3, [r3, #0] 8003d3e: 4a14 ldr r2, [pc, #80] @ (8003d90 ) 8003d40: 4293 cmp r3, r2 8003d42: d121 bne.n 8003d88 /* USER CODE END RNG_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG; 8003d44: f44f 3200 mov.w r2, #131072 @ 0x20000 8003d48: f04f 0300 mov.w r3, #0 8003d4c: e9c7 2304 strd r2, r3, [r7, #16] PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48; 8003d50: 2300 movs r3, #0 8003d52: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8003d56: f107 0310 add.w r3, r7, #16 8003d5a: 4618 mov r0, r3 8003d5c: f008 fc4e bl 800c5fc 8003d60: 4603 mov r3, r0 8003d62: 2b00 cmp r3, #0 8003d64: d001 beq.n 8003d6a { Error_Handler(); 8003d66: f7fd ff11 bl 8001b8c } /* Peripheral clock enable */ __HAL_RCC_RNG_CLK_ENABLE(); 8003d6a: 4b0a ldr r3, [pc, #40] @ (8003d94 ) 8003d6c: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 8003d70: 4a08 ldr r2, [pc, #32] @ (8003d94 ) 8003d72: f043 0340 orr.w r3, r3, #64 @ 0x40 8003d76: f8c2 30dc str.w r3, [r2, #220] @ 0xdc 8003d7a: 4b06 ldr r3, [pc, #24] @ (8003d94 ) 8003d7c: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 8003d80: f003 0340 and.w r3, r3, #64 @ 0x40 8003d84: 60fb str r3, [r7, #12] 8003d86: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN RNG_MspInit 1 */ /* USER CODE END RNG_MspInit 1 */ } } 8003d88: bf00 nop 8003d8a: 37d0 adds r7, #208 @ 0xd0 8003d8c: 46bd mov sp, r7 8003d8e: bd80 pop {r7, pc} 8003d90: 48021800 .word 0x48021800 8003d94: 58024400 .word 0x58024400 08003d98 : * This function configures the hardware resources used in this example * @param htim_pwm: TIM_PWM handle pointer * @retval None */ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) { 8003d98: b480 push {r7} 8003d9a: b085 sub sp, #20 8003d9c: af00 add r7, sp, #0 8003d9e: 6078 str r0, [r7, #4] if(htim_pwm->Instance==TIM1) 8003da0: 687b ldr r3, [r7, #4] 8003da2: 681b ldr r3, [r3, #0] 8003da4: 4a16 ldr r2, [pc, #88] @ (8003e00 ) 8003da6: 4293 cmp r3, r2 8003da8: d10f bne.n 8003dca { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 8003daa: 4b16 ldr r3, [pc, #88] @ (8003e04 ) 8003dac: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8003db0: 4a14 ldr r2, [pc, #80] @ (8003e04 ) 8003db2: f043 0301 orr.w r3, r3, #1 8003db6: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 8003dba: 4b12 ldr r3, [pc, #72] @ (8003e04 ) 8003dbc: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8003dc0: f003 0301 and.w r3, r3, #1 8003dc4: 60fb str r3, [r7, #12] 8003dc6: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 8003dc8: e013 b.n 8003df2 else if(htim_pwm->Instance==TIM3) 8003dca: 687b ldr r3, [r7, #4] 8003dcc: 681b ldr r3, [r3, #0] 8003dce: 4a0e ldr r2, [pc, #56] @ (8003e08 ) 8003dd0: 4293 cmp r3, r2 8003dd2: d10e bne.n 8003df2 __HAL_RCC_TIM3_CLK_ENABLE(); 8003dd4: 4b0b ldr r3, [pc, #44] @ (8003e04 ) 8003dd6: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003dda: 4a0a ldr r2, [pc, #40] @ (8003e04 ) 8003ddc: f043 0302 orr.w r3, r3, #2 8003de0: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8003de4: 4b07 ldr r3, [pc, #28] @ (8003e04 ) 8003de6: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003dea: f003 0302 and.w r3, r3, #2 8003dee: 60bb str r3, [r7, #8] 8003df0: 68bb ldr r3, [r7, #8] } 8003df2: bf00 nop 8003df4: 3714 adds r7, #20 8003df6: 46bd mov sp, r7 8003df8: f85d 7b04 ldr.w r7, [sp], #4 8003dfc: 4770 bx lr 8003dfe: bf00 nop 8003e00: 40010000 .word 0x40010000 8003e04: 58024400 .word 0x58024400 8003e08: 40000400 .word 0x40000400 08003e0c : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8003e0c: b480 push {r7} 8003e0e: b085 sub sp, #20 8003e10: af00 add r7, sp, #0 8003e12: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM8) 8003e14: 687b ldr r3, [r7, #4] 8003e16: 681b ldr r3, [r3, #0] 8003e18: 4a0b ldr r2, [pc, #44] @ (8003e48 ) 8003e1a: 4293 cmp r3, r2 8003e1c: d10e bne.n 8003e3c { /* USER CODE BEGIN TIM8_MspInit 0 */ /* USER CODE END TIM8_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM8_CLK_ENABLE(); 8003e1e: 4b0b ldr r3, [pc, #44] @ (8003e4c ) 8003e20: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8003e24: 4a09 ldr r2, [pc, #36] @ (8003e4c ) 8003e26: f043 0302 orr.w r3, r3, #2 8003e2a: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 8003e2e: 4b07 ldr r3, [pc, #28] @ (8003e4c ) 8003e30: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8003e34: f003 0302 and.w r3, r3, #2 8003e38: 60fb str r3, [r7, #12] 8003e3a: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM8_MspInit 1 */ /* USER CODE END TIM8_MspInit 1 */ } } 8003e3c: bf00 nop 8003e3e: 3714 adds r7, #20 8003e40: 46bd mov sp, r7 8003e42: f85d 7b04 ldr.w r7, [sp], #4 8003e46: 4770 bx lr 8003e48: 40010400 .word 0x40010400 8003e4c: 58024400 .word 0x58024400 08003e50 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 8003e50: b580 push {r7, lr} 8003e52: b08a sub sp, #40 @ 0x28 8003e54: af00 add r7, sp, #0 8003e56: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003e58: f107 0314 add.w r3, r7, #20 8003e5c: 2200 movs r2, #0 8003e5e: 601a str r2, [r3, #0] 8003e60: 605a str r2, [r3, #4] 8003e62: 609a str r2, [r3, #8] 8003e64: 60da str r2, [r3, #12] 8003e66: 611a str r2, [r3, #16] if(htim->Instance==TIM1) 8003e68: 687b ldr r3, [r7, #4] 8003e6a: 681b ldr r3, [r3, #0] 8003e6c: 4a26 ldr r2, [pc, #152] @ (8003f08 ) 8003e6e: 4293 cmp r3, r2 8003e70: d120 bne.n 8003eb4 { /* USER CODE BEGIN TIM1_MspPostInit 0 */ /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8003e72: 4b26 ldr r3, [pc, #152] @ (8003f0c ) 8003e74: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e78: 4a24 ldr r2, [pc, #144] @ (8003f0c ) 8003e7a: f043 0301 orr.w r3, r3, #1 8003e7e: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003e82: 4b22 ldr r3, [pc, #136] @ (8003f0c ) 8003e84: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e88: f003 0301 and.w r3, r3, #1 8003e8c: 613b str r3, [r7, #16] 8003e8e: 693b ldr r3, [r7, #16] /**TIM1 GPIO Configuration PA9 ------> TIM1_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_9; 8003e90: f44f 7300 mov.w r3, #512 @ 0x200 8003e94: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003e96: 2302 movs r3, #2 8003e98: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003e9a: 2300 movs r3, #0 8003e9c: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003e9e: 2300 movs r3, #0 8003ea0: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; 8003ea2: 2301 movs r3, #1 8003ea4: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003ea6: f107 0314 add.w r3, r7, #20 8003eaa: 4619 mov r1, r3 8003eac: 4818 ldr r0, [pc, #96] @ (8003f10 ) 8003eae: f006 ffbf bl 800ae30 /* USER CODE BEGIN TIM3_MspPostInit 1 */ /* USER CODE END TIM3_MspPostInit 1 */ } } 8003eb2: e024 b.n 8003efe else if(htim->Instance==TIM3) 8003eb4: 687b ldr r3, [r7, #4] 8003eb6: 681b ldr r3, [r3, #0] 8003eb8: 4a16 ldr r2, [pc, #88] @ (8003f14 ) 8003eba: 4293 cmp r3, r2 8003ebc: d11f bne.n 8003efe __HAL_RCC_GPIOC_CLK_ENABLE(); 8003ebe: 4b13 ldr r3, [pc, #76] @ (8003f0c ) 8003ec0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003ec4: 4a11 ldr r2, [pc, #68] @ (8003f0c ) 8003ec6: f043 0304 orr.w r3, r3, #4 8003eca: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003ece: 4b0f ldr r3, [pc, #60] @ (8003f0c ) 8003ed0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003ed4: f003 0304 and.w r3, r3, #4 8003ed8: 60fb str r3, [r7, #12] 8003eda: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 8003edc: f44f 7370 mov.w r3, #960 @ 0x3c0 8003ee0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003ee2: 2302 movs r3, #2 8003ee4: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003ee6: 2300 movs r3, #0 8003ee8: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 8003eea: 2301 movs r3, #1 8003eec: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 8003eee: 2302 movs r3, #2 8003ef0: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003ef2: f107 0314 add.w r3, r7, #20 8003ef6: 4619 mov r1, r3 8003ef8: 4807 ldr r0, [pc, #28] @ (8003f18 ) 8003efa: f006 ff99 bl 800ae30 } 8003efe: bf00 nop 8003f00: 3728 adds r7, #40 @ 0x28 8003f02: 46bd mov sp, r7 8003f04: bd80 pop {r7, pc} 8003f06: bf00 nop 8003f08: 40010000 .word 0x40010000 8003f0c: 58024400 .word 0x58024400 8003f10: 58020000 .word 0x58020000 8003f14: 40000400 .word 0x40000400 8003f18: 58020800 .word 0x58020800 08003f1c : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8003f1c: b580 push {r7, lr} 8003f1e: b0bc sub sp, #240 @ 0xf0 8003f20: af00 add r7, sp, #0 8003f22: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003f24: f107 03dc add.w r3, r7, #220 @ 0xdc 8003f28: 2200 movs r2, #0 8003f2a: 601a str r2, [r3, #0] 8003f2c: 605a str r2, [r3, #4] 8003f2e: 609a str r2, [r3, #8] 8003f30: 60da str r2, [r3, #12] 8003f32: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8003f34: f107 0318 add.w r3, r7, #24 8003f38: 22c0 movs r2, #192 @ 0xc0 8003f3a: 2100 movs r1, #0 8003f3c: 4618 mov r0, r3 8003f3e: f014 fa93 bl 8018468 if(huart->Instance==UART8) 8003f42: 687b ldr r3, [r7, #4] 8003f44: 681b ldr r3, [r3, #0] 8003f46: 4a55 ldr r2, [pc, #340] @ (800409c ) 8003f48: 4293 cmp r3, r2 8003f4a: d14e bne.n 8003fea /* USER CODE END UART8_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8; 8003f4c: f04f 0202 mov.w r2, #2 8003f50: f04f 0300 mov.w r3, #0 8003f54: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 8003f58: 2300 movs r3, #0 8003f5a: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8003f5e: f107 0318 add.w r3, r7, #24 8003f62: 4618 mov r0, r3 8003f64: f008 fb4a bl 800c5fc 8003f68: 4603 mov r3, r0 8003f6a: 2b00 cmp r3, #0 8003f6c: d001 beq.n 8003f72 { Error_Handler(); 8003f6e: f7fd fe0d bl 8001b8c } /* Peripheral clock enable */ __HAL_RCC_UART8_CLK_ENABLE(); 8003f72: 4b4b ldr r3, [pc, #300] @ (80040a0 ) 8003f74: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003f78: 4a49 ldr r2, [pc, #292] @ (80040a0 ) 8003f7a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8003f7e: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8003f82: 4b47 ldr r3, [pc, #284] @ (80040a0 ) 8003f84: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003f88: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8003f8c: 617b str r3, [r7, #20] 8003f8e: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOE_CLK_ENABLE(); 8003f90: 4b43 ldr r3, [pc, #268] @ (80040a0 ) 8003f92: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003f96: 4a42 ldr r2, [pc, #264] @ (80040a0 ) 8003f98: f043 0310 orr.w r3, r3, #16 8003f9c: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003fa0: 4b3f ldr r3, [pc, #252] @ (80040a0 ) 8003fa2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003fa6: f003 0310 and.w r3, r3, #16 8003faa: 613b str r3, [r7, #16] 8003fac: 693b ldr r3, [r7, #16] /**UART8 GPIO Configuration PE0 ------> UART8_RX PE1 ------> UART8_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8003fae: 2303 movs r3, #3 8003fb0: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003fb4: 2302 movs r3, #2 8003fb6: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003fba: 2300 movs r3, #0 8003fbc: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003fc0: 2300 movs r3, #0 8003fc2: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF8_UART8; 8003fc6: 2308 movs r3, #8 8003fc8: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8003fcc: f107 03dc add.w r3, r7, #220 @ 0xdc 8003fd0: 4619 mov r1, r3 8003fd2: 4834 ldr r0, [pc, #208] @ (80040a4 ) 8003fd4: f006 ff2c bl 800ae30 /* UART8 interrupt Init */ HAL_NVIC_SetPriority(UART8_IRQn, 5, 0); 8003fd8: 2200 movs r2, #0 8003fda: 2105 movs r1, #5 8003fdc: 2053 movs r0, #83 @ 0x53 8003fde: f003 fbf5 bl 80077cc HAL_NVIC_EnableIRQ(UART8_IRQn); 8003fe2: 2053 movs r0, #83 @ 0x53 8003fe4: f003 fc0c bl 8007800 /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 8003fe8: e053 b.n 8004092 else if(huart->Instance==USART1) 8003fea: 687b ldr r3, [r7, #4] 8003fec: 681b ldr r3, [r3, #0] 8003fee: 4a2e ldr r2, [pc, #184] @ (80040a8 ) 8003ff0: 4293 cmp r3, r2 8003ff2: d14e bne.n 8004092 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; 8003ff4: f04f 0201 mov.w r2, #1 8003ff8: f04f 0300 mov.w r3, #0 8003ffc: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; 8004000: 2300 movs r3, #0 8004002: f8c7 3094 str.w r3, [r7, #148] @ 0x94 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8004006: f107 0318 add.w r3, r7, #24 800400a: 4618 mov r0, r3 800400c: f008 faf6 bl 800c5fc 8004010: 4603 mov r3, r0 8004012: 2b00 cmp r3, #0 8004014: d001 beq.n 800401a Error_Handler(); 8004016: f7fd fdb9 bl 8001b8c __HAL_RCC_USART1_CLK_ENABLE(); 800401a: 4b21 ldr r3, [pc, #132] @ (80040a0 ) 800401c: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8004020: 4a1f ldr r2, [pc, #124] @ (80040a0 ) 8004022: f043 0310 orr.w r3, r3, #16 8004026: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 800402a: 4b1d ldr r3, [pc, #116] @ (80040a0 ) 800402c: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8004030: f003 0310 and.w r3, r3, #16 8004034: 60fb str r3, [r7, #12] 8004036: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 8004038: 4b19 ldr r3, [pc, #100] @ (80040a0 ) 800403a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800403e: 4a18 ldr r2, [pc, #96] @ (80040a0 ) 8004040: f043 0302 orr.w r3, r3, #2 8004044: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004048: 4b15 ldr r3, [pc, #84] @ (80040a0 ) 800404a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800404e: f003 0302 and.w r3, r3, #2 8004052: 60bb str r3, [r7, #8] 8004054: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 8004056: f44f 4340 mov.w r3, #49152 @ 0xc000 800405a: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800405e: 2302 movs r3, #2 8004060: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8004064: 2300 movs r3, #0 8004066: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800406a: 2300 movs r3, #0 800406c: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF4_USART1; 8004070: 2304 movs r3, #4 8004072: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8004076: f107 03dc add.w r3, r7, #220 @ 0xdc 800407a: 4619 mov r1, r3 800407c: 480b ldr r0, [pc, #44] @ (80040ac ) 800407e: f006 fed7 bl 800ae30 HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 8004082: 2200 movs r2, #0 8004084: 2105 movs r1, #5 8004086: 2025 movs r0, #37 @ 0x25 8004088: f003 fba0 bl 80077cc HAL_NVIC_EnableIRQ(USART1_IRQn); 800408c: 2025 movs r0, #37 @ 0x25 800408e: f003 fbb7 bl 8007800 } 8004092: bf00 nop 8004094: 37f0 adds r7, #240 @ 0xf0 8004096: 46bd mov sp, r7 8004098: bd80 pop {r7, pc} 800409a: bf00 nop 800409c: 40007c00 .word 0x40007c00 80040a0: 58024400 .word 0x58024400 80040a4: 58021000 .word 0x58021000 80040a8: 40011000 .word 0x40011000 80040ac: 58020400 .word 0x58020400 080040b0 : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80040b0: b580 push {r7, lr} 80040b2: b090 sub sp, #64 @ 0x40 80040b4: af00 add r7, sp, #0 80040b6: 6078 str r0, [r7, #4] uint32_t uwTimclock, uwAPB1Prescaler; uint32_t uwPrescalerValue; uint32_t pFLatency; /*Configure the TIM6 IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80040b8: 687b ldr r3, [r7, #4] 80040ba: 2b0f cmp r3, #15 80040bc: d827 bhi.n 800410e { HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U); 80040be: 2200 movs r2, #0 80040c0: 6879 ldr r1, [r7, #4] 80040c2: 2036 movs r0, #54 @ 0x36 80040c4: f003 fb82 bl 80077cc /* Enable the TIM6 global Interrupt */ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 80040c8: 2036 movs r0, #54 @ 0x36 80040ca: f003 fb99 bl 8007800 uwTickPrio = TickPriority; 80040ce: 4a29 ldr r2, [pc, #164] @ (8004174 ) 80040d0: 687b ldr r3, [r7, #4] 80040d2: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Enable TIM6 clock */ __HAL_RCC_TIM6_CLK_ENABLE(); 80040d4: 4b28 ldr r3, [pc, #160] @ (8004178 ) 80040d6: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80040da: 4a27 ldr r2, [pc, #156] @ (8004178 ) 80040dc: f043 0310 orr.w r3, r3, #16 80040e0: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 80040e4: 4b24 ldr r3, [pc, #144] @ (8004178 ) 80040e6: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80040ea: f003 0310 and.w r3, r3, #16 80040ee: 60fb str r3, [r7, #12] 80040f0: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 80040f2: f107 0210 add.w r2, r7, #16 80040f6: f107 0314 add.w r3, r7, #20 80040fa: 4611 mov r1, r2 80040fc: 4618 mov r0, r3 80040fe: f008 fa3b bl 800c578 /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; 8004102: 6abb ldr r3, [r7, #40] @ 0x28 8004104: 63bb str r3, [r7, #56] @ 0x38 /* Compute TIM6 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) 8004106: 6bbb ldr r3, [r7, #56] @ 0x38 8004108: 2b00 cmp r3, #0 800410a: d106 bne.n 800411a 800410c: e001 b.n 8004112 return HAL_ERROR; 800410e: 2301 movs r3, #1 8004110: e02b b.n 800416a { uwTimclock = HAL_RCC_GetPCLK1Freq(); 8004112: f008 fa05 bl 800c520 8004116: 63f8 str r0, [r7, #60] @ 0x3c 8004118: e004 b.n 8004124 } else { uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); 800411a: f008 fa01 bl 800c520 800411e: 4603 mov r3, r0 8004120: 005b lsls r3, r3, #1 8004122: 63fb str r3, [r7, #60] @ 0x3c } /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 8004124: 6bfb ldr r3, [r7, #60] @ 0x3c 8004126: 4a15 ldr r2, [pc, #84] @ (800417c ) 8004128: fba2 2303 umull r2, r3, r2, r3 800412c: 0c9b lsrs r3, r3, #18 800412e: 3b01 subs r3, #1 8004130: 637b str r3, [r7, #52] @ 0x34 /* Initialize TIM6 */ htim6.Instance = TIM6; 8004132: 4b13 ldr r3, [pc, #76] @ (8004180 ) 8004134: 4a13 ldr r2, [pc, #76] @ (8004184 ) 8004136: 601a str r2, [r3, #0] + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up */ htim6.Init.Period = (1000000U / 1000U) - 1U; 8004138: 4b11 ldr r3, [pc, #68] @ (8004180 ) 800413a: f240 32e7 movw r2, #999 @ 0x3e7 800413e: 60da str r2, [r3, #12] htim6.Init.Prescaler = uwPrescalerValue; 8004140: 4a0f ldr r2, [pc, #60] @ (8004180 ) 8004142: 6b7b ldr r3, [r7, #52] @ 0x34 8004144: 6053 str r3, [r2, #4] htim6.Init.ClockDivision = 0; 8004146: 4b0e ldr r3, [pc, #56] @ (8004180 ) 8004148: 2200 movs r2, #0 800414a: 611a str r2, [r3, #16] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 800414c: 4b0c ldr r3, [pc, #48] @ (8004180 ) 800414e: 2200 movs r2, #0 8004150: 609a str r2, [r3, #8] if(HAL_TIM_Base_Init(&htim6) == HAL_OK) 8004152: 480b ldr r0, [pc, #44] @ (8004180 ) 8004154: f00a ff96 bl 800f084 8004158: 4603 mov r3, r0 800415a: 2b00 cmp r3, #0 800415c: d104 bne.n 8004168 { /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&htim6); 800415e: 4808 ldr r0, [pc, #32] @ (8004180 ) 8004160: f00b f858 bl 800f214 8004164: 4603 mov r3, r0 8004166: e000 b.n 800416a } /* Return function status */ return HAL_ERROR; 8004168: 2301 movs r3, #1 } 800416a: 4618 mov r0, r3 800416c: 3740 adds r7, #64 @ 0x40 800416e: 46bd mov sp, r7 8004170: bd80 pop {r7, pc} 8004172: bf00 nop 8004174: 2400003c .word 0x2400003c 8004178: 58024400 .word 0x58024400 800417c: 431bde83 .word 0x431bde83 8004180: 24000a78 .word 0x24000a78 8004184: 40001000 .word 0x40001000 08004188 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8004188: b480 push {r7} 800418a: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800418c: bf00 nop 800418e: e7fd b.n 800418c 08004190 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8004190: b480 push {r7} 8004192: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8004194: bf00 nop 8004196: e7fd b.n 8004194 08004198 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8004198: b480 push {r7} 800419a: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800419c: bf00 nop 800419e: e7fd b.n 800419c 080041a0 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 80041a0: b480 push {r7} 80041a2: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80041a4: bf00 nop 80041a6: e7fd b.n 80041a4 080041a8 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80041a8: b480 push {r7} 80041aa: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80041ac: bf00 nop 80041ae: e7fd b.n 80041ac 080041b0 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80041b0: b480 push {r7} 80041b2: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 80041b4: bf00 nop 80041b6: 46bd mov sp, r7 80041b8: f85d 7b04 ldr.w r7, [sp], #4 80041bc: 4770 bx lr 080041be : /** * @brief This function handles RCC global interrupt. */ void RCC_IRQHandler(void) { 80041be: b480 push {r7} 80041c0: af00 add r7, sp, #0 /* USER CODE END RCC_IRQn 0 */ /* USER CODE BEGIN RCC_IRQn 1 */ /* USER CODE END RCC_IRQn 1 */ } 80041c2: bf00 nop 80041c4: 46bd mov sp, r7 80041c6: f85d 7b04 ldr.w r7, [sp], #4 80041ca: 4770 bx lr 080041cc : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 80041cc: b580 push {r7, lr} 80041ce: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 80041d0: 4802 ldr r0, [pc, #8] @ (80041dc ) 80041d2: f005 fb1b bl 800980c /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 80041d6: bf00 nop 80041d8: bd80 pop {r7, pc} 80041da: bf00 nop 80041dc: 240003ac .word 0x240003ac 080041e0 : /** * @brief This function handles DMA1 stream1 global interrupt. */ void DMA1_Stream1_IRQHandler(void) { 80041e0: b580 push {r7, lr} 80041e2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */ /* USER CODE END DMA1_Stream1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc2); 80041e4: 4802 ldr r0, [pc, #8] @ (80041f0 ) 80041e6: f005 fb11 bl 800980c /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */ /* USER CODE END DMA1_Stream1_IRQn 1 */ } 80041ea: bf00 nop 80041ec: bd80 pop {r7, pc} 80041ee: bf00 nop 80041f0: 24000424 .word 0x24000424 080041f4 : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 80041f4: b580 push {r7, lr} 80041f6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc3); 80041f8: 4802 ldr r0, [pc, #8] @ (8004204 ) 80041fa: f005 fb07 bl 800980c /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 80041fe: bf00 nop 8004200: bd80 pop {r7, pc} 8004202: bf00 nop 8004204: 2400049c .word 0x2400049c 08004208 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8004208: b580 push {r7, lr} 800420a: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 800420c: 4802 ldr r0, [pc, #8] @ (8004218 ) 800420e: f00c fc39 bl 8010a84 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8004212: bf00 nop 8004214: bd80 pop {r7, pc} 8004216: bf00 nop 8004218: 24000714 .word 0x24000714 0800421c : /** * @brief This function handles EXTI line[15:10] interrupts. */ void EXTI15_10_IRQHandler(void) { 800421c: b580 push {r7, lr} 800421e: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI15_10_IRQn 0 */ /* USER CODE END EXTI15_10_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10); 8004220: f44f 6080 mov.w r0, #1024 @ 0x400 8004224: f006 ffff bl 800b226 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); 8004228: f44f 6000 mov.w r0, #2048 @ 0x800 800422c: f006 fffb bl 800b226 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14); 8004230: f44f 4080 mov.w r0, #16384 @ 0x4000 8004234: f006 fff7 bl 800b226 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15); 8004238: f44f 4000 mov.w r0, #32768 @ 0x8000 800423c: f006 fff3 bl 800b226 /* USER CODE BEGIN EXTI15_10_IRQn 1 */ /* USER CODE END EXTI15_10_IRQn 1 */ } 8004240: bf00 nop 8004242: bd80 pop {r7, pc} 08004244 : /** * @brief This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 8004244: b580 push {r7, lr} 8004246: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ if (hdac1.State != HAL_DAC_STATE_RESET) { 8004248: 4b06 ldr r3, [pc, #24] @ (8004264 ) 800424a: 791b ldrb r3, [r3, #4] 800424c: b2db uxtb r3, r3 800424e: 2b00 cmp r3, #0 8004250: d002 beq.n 8004258 HAL_DAC_IRQHandler(&hdac1); 8004252: 4804 ldr r0, [pc, #16] @ (8004264 ) 8004254: f003 fdd9 bl 8007e0a } HAL_TIM_IRQHandler(&htim6); 8004258: 4803 ldr r0, [pc, #12] @ (8004268 ) 800425a: f00b fa4f bl 800f6fc /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 800425e: bf00 nop 8004260: bd80 pop {r7, pc} 8004262: bf00 nop 8004264: 24000564 .word 0x24000564 8004268: 24000a78 .word 0x24000a78 0800426c : /** * @brief This function handles UART8 global interrupt. */ void UART8_IRQHandler(void) { 800426c: b580 push {r7, lr} 800426e: af00 add r7, sp, #0 /* USER CODE BEGIN UART8_IRQn 0 */ /* USER CODE END UART8_IRQn 0 */ HAL_UART_IRQHandler(&huart8); 8004270: 4802 ldr r0, [pc, #8] @ (800427c ) 8004272: f00c fc07 bl 8010a84 /* USER CODE BEGIN UART8_IRQn 1 */ /* USER CODE END UART8_IRQn 1 */ } 8004276: bf00 nop 8004278: bd80 pop {r7, pc} 800427a: bf00 nop 800427c: 24000680 .word 0x24000680 08004280 <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 8004280: b480 push {r7} 8004282: af00 add r7, sp, #0 return 1; 8004284: 2301 movs r3, #1 } 8004286: 4618 mov r0, r3 8004288: 46bd mov sp, r7 800428a: f85d 7b04 ldr.w r7, [sp], #4 800428e: 4770 bx lr 08004290 <_kill>: int _kill(int pid, int sig) { 8004290: b580 push {r7, lr} 8004292: b082 sub sp, #8 8004294: af00 add r7, sp, #0 8004296: 6078 str r0, [r7, #4] 8004298: 6039 str r1, [r7, #0] (void)pid; (void)sig; errno = EINVAL; 800429a: f014 f98d bl 80185b8 <__errno> 800429e: 4603 mov r3, r0 80042a0: 2216 movs r2, #22 80042a2: 601a str r2, [r3, #0] return -1; 80042a4: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 80042a8: 4618 mov r0, r3 80042aa: 3708 adds r7, #8 80042ac: 46bd mov sp, r7 80042ae: bd80 pop {r7, pc} 080042b0 <_exit>: void _exit (int status) { 80042b0: b580 push {r7, lr} 80042b2: b082 sub sp, #8 80042b4: af00 add r7, sp, #0 80042b6: 6078 str r0, [r7, #4] _kill(status, -1); 80042b8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80042bc: 6878 ldr r0, [r7, #4] 80042be: f7ff ffe7 bl 8004290 <_kill> while (1) {} /* Make sure we hang here */ 80042c2: bf00 nop 80042c4: e7fd b.n 80042c2 <_exit+0x12> 080042c6 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 80042c6: b580 push {r7, lr} 80042c8: b086 sub sp, #24 80042ca: af00 add r7, sp, #0 80042cc: 60f8 str r0, [r7, #12] 80042ce: 60b9 str r1, [r7, #8] 80042d0: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 80042d2: 2300 movs r3, #0 80042d4: 617b str r3, [r7, #20] 80042d6: e00a b.n 80042ee <_read+0x28> { *ptr++ = __io_getchar(); 80042d8: f3af 8000 nop.w 80042dc: 4601 mov r1, r0 80042de: 68bb ldr r3, [r7, #8] 80042e0: 1c5a adds r2, r3, #1 80042e2: 60ba str r2, [r7, #8] 80042e4: b2ca uxtb r2, r1 80042e6: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 80042e8: 697b ldr r3, [r7, #20] 80042ea: 3301 adds r3, #1 80042ec: 617b str r3, [r7, #20] 80042ee: 697a ldr r2, [r7, #20] 80042f0: 687b ldr r3, [r7, #4] 80042f2: 429a cmp r2, r3 80042f4: dbf0 blt.n 80042d8 <_read+0x12> } return len; 80042f6: 687b ldr r3, [r7, #4] } 80042f8: 4618 mov r0, r3 80042fa: 3718 adds r7, #24 80042fc: 46bd mov sp, r7 80042fe: bd80 pop {r7, pc} 08004300 <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 8004300: b580 push {r7, lr} 8004302: b086 sub sp, #24 8004304: af00 add r7, sp, #0 8004306: 60f8 str r0, [r7, #12] 8004308: 60b9 str r1, [r7, #8] 800430a: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800430c: 2300 movs r3, #0 800430e: 617b str r3, [r7, #20] 8004310: e009 b.n 8004326 <_write+0x26> { __io_putchar(*ptr++); 8004312: 68bb ldr r3, [r7, #8] 8004314: 1c5a adds r2, r3, #1 8004316: 60ba str r2, [r7, #8] 8004318: 781b ldrb r3, [r3, #0] 800431a: 4618 mov r0, r3 800431c: f7fc f9f9 bl 8000712 <__io_putchar> for (DataIdx = 0; DataIdx < len; DataIdx++) 8004320: 697b ldr r3, [r7, #20] 8004322: 3301 adds r3, #1 8004324: 617b str r3, [r7, #20] 8004326: 697a ldr r2, [r7, #20] 8004328: 687b ldr r3, [r7, #4] 800432a: 429a cmp r2, r3 800432c: dbf1 blt.n 8004312 <_write+0x12> } return len; 800432e: 687b ldr r3, [r7, #4] } 8004330: 4618 mov r0, r3 8004332: 3718 adds r7, #24 8004334: 46bd mov sp, r7 8004336: bd80 pop {r7, pc} 08004338 <_close>: int _close(int file) { 8004338: b480 push {r7} 800433a: b083 sub sp, #12 800433c: af00 add r7, sp, #0 800433e: 6078 str r0, [r7, #4] (void)file; return -1; 8004340: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 8004344: 4618 mov r0, r3 8004346: 370c adds r7, #12 8004348: 46bd mov sp, r7 800434a: f85d 7b04 ldr.w r7, [sp], #4 800434e: 4770 bx lr 08004350 <_fstat>: int _fstat(int file, struct stat *st) { 8004350: b480 push {r7} 8004352: b083 sub sp, #12 8004354: af00 add r7, sp, #0 8004356: 6078 str r0, [r7, #4] 8004358: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 800435a: 683b ldr r3, [r7, #0] 800435c: f44f 5200 mov.w r2, #8192 @ 0x2000 8004360: 605a str r2, [r3, #4] return 0; 8004362: 2300 movs r3, #0 } 8004364: 4618 mov r0, r3 8004366: 370c adds r7, #12 8004368: 46bd mov sp, r7 800436a: f85d 7b04 ldr.w r7, [sp], #4 800436e: 4770 bx lr 08004370 <_isatty>: int _isatty(int file) { 8004370: b480 push {r7} 8004372: b083 sub sp, #12 8004374: af00 add r7, sp, #0 8004376: 6078 str r0, [r7, #4] (void)file; return 1; 8004378: 2301 movs r3, #1 } 800437a: 4618 mov r0, r3 800437c: 370c adds r7, #12 800437e: 46bd mov sp, r7 8004380: f85d 7b04 ldr.w r7, [sp], #4 8004384: 4770 bx lr 08004386 <_lseek>: int _lseek(int file, int ptr, int dir) { 8004386: b480 push {r7} 8004388: b085 sub sp, #20 800438a: af00 add r7, sp, #0 800438c: 60f8 str r0, [r7, #12] 800438e: 60b9 str r1, [r7, #8] 8004390: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 8004392: 2300 movs r3, #0 } 8004394: 4618 mov r0, r3 8004396: 3714 adds r7, #20 8004398: 46bd mov sp, r7 800439a: f85d 7b04 ldr.w r7, [sp], #4 800439e: 4770 bx lr 080043a0 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 80043a0: b580 push {r7, lr} 80043a2: b086 sub sp, #24 80043a4: af00 add r7, sp, #0 80043a6: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 80043a8: 4a14 ldr r2, [pc, #80] @ (80043fc <_sbrk+0x5c>) 80043aa: 4b15 ldr r3, [pc, #84] @ (8004400 <_sbrk+0x60>) 80043ac: 1ad3 subs r3, r2, r3 80043ae: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 80043b0: 697b ldr r3, [r7, #20] 80043b2: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 80043b4: 4b13 ldr r3, [pc, #76] @ (8004404 <_sbrk+0x64>) 80043b6: 681b ldr r3, [r3, #0] 80043b8: 2b00 cmp r3, #0 80043ba: d102 bne.n 80043c2 <_sbrk+0x22> { __sbrk_heap_end = &_end; 80043bc: 4b11 ldr r3, [pc, #68] @ (8004404 <_sbrk+0x64>) 80043be: 4a12 ldr r2, [pc, #72] @ (8004408 <_sbrk+0x68>) 80043c0: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 80043c2: 4b10 ldr r3, [pc, #64] @ (8004404 <_sbrk+0x64>) 80043c4: 681a ldr r2, [r3, #0] 80043c6: 687b ldr r3, [r7, #4] 80043c8: 4413 add r3, r2 80043ca: 693a ldr r2, [r7, #16] 80043cc: 429a cmp r2, r3 80043ce: d207 bcs.n 80043e0 <_sbrk+0x40> { errno = ENOMEM; 80043d0: f014 f8f2 bl 80185b8 <__errno> 80043d4: 4603 mov r3, r0 80043d6: 220c movs r2, #12 80043d8: 601a str r2, [r3, #0] return (void *)-1; 80043da: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80043de: e009 b.n 80043f4 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 80043e0: 4b08 ldr r3, [pc, #32] @ (8004404 <_sbrk+0x64>) 80043e2: 681b ldr r3, [r3, #0] 80043e4: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 80043e6: 4b07 ldr r3, [pc, #28] @ (8004404 <_sbrk+0x64>) 80043e8: 681a ldr r2, [r3, #0] 80043ea: 687b ldr r3, [r7, #4] 80043ec: 4413 add r3, r2 80043ee: 4a05 ldr r2, [pc, #20] @ (8004404 <_sbrk+0x64>) 80043f0: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 80043f2: 68fb ldr r3, [r7, #12] } 80043f4: 4618 mov r0, r3 80043f6: 3718 adds r7, #24 80043f8: 46bd mov sp, r7 80043fa: bd80 pop {r7, pc} 80043fc: 24060000 .word 0x24060000 8004400: 00000400 .word 0x00000400 8004404: 24000ac4 .word 0x24000ac4 8004408: 240132f8 .word 0x240132f8 0800440c : * configuration. * @param None * @retval None */ void SystemInit (void) { 800440c: b480 push {r7} 800440e: af00 add r7, sp, #0 __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8004410: 4b37 ldr r3, [pc, #220] @ (80044f0 ) 8004412: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004416: 4a36 ldr r2, [pc, #216] @ (80044f0 ) 8004418: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 800441c: f8c2 3088 str.w r3, [r2, #136] @ 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8004420: 4b34 ldr r3, [pc, #208] @ (80044f4 ) 8004422: 681b ldr r3, [r3, #0] 8004424: f003 030f and.w r3, r3, #15 8004428: 2b06 cmp r3, #6 800442a: d807 bhi.n 800443c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 800442c: 4b31 ldr r3, [pc, #196] @ (80044f4 ) 800442e: 681b ldr r3, [r3, #0] 8004430: f023 030f bic.w r3, r3, #15 8004434: 4a2f ldr r2, [pc, #188] @ (80044f4 ) 8004436: f043 0307 orr.w r3, r3, #7 800443a: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 800443c: 4b2e ldr r3, [pc, #184] @ (80044f8 ) 800443e: 681b ldr r3, [r3, #0] 8004440: 4a2d ldr r2, [pc, #180] @ (80044f8 ) 8004442: f043 0301 orr.w r3, r3, #1 8004446: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 8004448: 4b2b ldr r3, [pc, #172] @ (80044f8 ) 800444a: 2200 movs r2, #0 800444c: 611a str r2, [r3, #16] /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 800444e: 4b2a ldr r3, [pc, #168] @ (80044f8 ) 8004450: 681a ldr r2, [r3, #0] 8004452: 4929 ldr r1, [pc, #164] @ (80044f8 ) 8004454: 4b29 ldr r3, [pc, #164] @ (80044fc ) 8004456: 4013 ands r3, r2 8004458: 600b str r3, [r1, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 800445a: 4b26 ldr r3, [pc, #152] @ (80044f4 ) 800445c: 681b ldr r3, [r3, #0] 800445e: f003 0308 and.w r3, r3, #8 8004462: 2b00 cmp r3, #0 8004464: d007 beq.n 8004476 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8004466: 4b23 ldr r3, [pc, #140] @ (80044f4 ) 8004468: 681b ldr r3, [r3, #0] 800446a: f023 030f bic.w r3, r3, #15 800446e: 4a21 ldr r2, [pc, #132] @ (80044f4 ) 8004470: f043 0307 orr.w r3, r3, #7 8004474: 6013 str r3, [r2, #0] } #if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; 8004476: 4b20 ldr r3, [pc, #128] @ (80044f8 ) 8004478: 2200 movs r2, #0 800447a: 619a str r2, [r3, #24] /* Reset D2CFGR register */ RCC->D2CFGR = 0x00000000; 800447c: 4b1e ldr r3, [pc, #120] @ (80044f8 ) 800447e: 2200 movs r2, #0 8004480: 61da str r2, [r3, #28] /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; 8004482: 4b1d ldr r3, [pc, #116] @ (80044f8 ) 8004484: 2200 movs r2, #0 8004486: 621a str r2, [r3, #32] /* Reset SRDCFGR register */ RCC->SRDCFGR = 0x00000000; #endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; 8004488: 4b1b ldr r3, [pc, #108] @ (80044f8 ) 800448a: 4a1d ldr r2, [pc, #116] @ (8004500 ) 800448c: 629a str r2, [r3, #40] @ 0x28 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; 800448e: 4b1a ldr r3, [pc, #104] @ (80044f8 ) 8004490: 4a1c ldr r2, [pc, #112] @ (8004504 ) 8004492: 62da str r2, [r3, #44] @ 0x2c /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 8004494: 4b18 ldr r3, [pc, #96] @ (80044f8 ) 8004496: 4a1c ldr r2, [pc, #112] @ (8004508 ) 8004498: 631a str r2, [r3, #48] @ 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 800449a: 4b17 ldr r3, [pc, #92] @ (80044f8 ) 800449c: 2200 movs r2, #0 800449e: 635a str r2, [r3, #52] @ 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 80044a0: 4b15 ldr r3, [pc, #84] @ (80044f8 ) 80044a2: 4a19 ldr r2, [pc, #100] @ (8004508 ) 80044a4: 639a str r2, [r3, #56] @ 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 80044a6: 4b14 ldr r3, [pc, #80] @ (80044f8 ) 80044a8: 2200 movs r2, #0 80044aa: 63da str r2, [r3, #60] @ 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 80044ac: 4b12 ldr r3, [pc, #72] @ (80044f8 ) 80044ae: 4a16 ldr r2, [pc, #88] @ (8004508 ) 80044b0: 641a str r2, [r3, #64] @ 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 80044b2: 4b11 ldr r3, [pc, #68] @ (80044f8 ) 80044b4: 2200 movs r2, #0 80044b6: 645a str r2, [r3, #68] @ 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 80044b8: 4b0f ldr r3, [pc, #60] @ (80044f8 ) 80044ba: 681b ldr r3, [r3, #0] 80044bc: 4a0e ldr r2, [pc, #56] @ (80044f8 ) 80044be: f423 2380 bic.w r3, r3, #262144 @ 0x40000 80044c2: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 80044c4: 4b0c ldr r3, [pc, #48] @ (80044f8 ) 80044c6: 2200 movs r2, #0 80044c8: 661a str r2, [r3, #96] @ 0x60 #if (STM32H7_DEV_ID == 0x450UL) /* dual core CM7 or single core line */ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) 80044ca: 4b10 ldr r3, [pc, #64] @ (800450c ) 80044cc: 681a ldr r2, [r3, #0] 80044ce: 4b10 ldr r3, [pc, #64] @ (8004510 ) 80044d0: 4013 ands r3, r2 80044d2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80044d6: d202 bcs.n 80044de { /* if stm32h7 revY*/ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; 80044d8: 4b0e ldr r3, [pc, #56] @ (8004514 ) 80044da: 2201 movs r2, #1 80044dc: 601a str r2, [r3, #0] /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 80044de: 4b0e ldr r3, [pc, #56] @ (8004518 ) 80044e0: f243 02d2 movw r2, #12498 @ 0x30d2 80044e4: 601a str r2, [r3, #0] #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ } 80044e6: bf00 nop 80044e8: 46bd mov sp, r7 80044ea: f85d 7b04 ldr.w r7, [sp], #4 80044ee: 4770 bx lr 80044f0: e000ed00 .word 0xe000ed00 80044f4: 52002000 .word 0x52002000 80044f8: 58024400 .word 0x58024400 80044fc: eaf6ed7f .word 0xeaf6ed7f 8004500: 02020200 .word 0x02020200 8004504: 01ff0000 .word 0x01ff0000 8004508: 01010280 .word 0x01010280 800450c: 5c001000 .word 0x5c001000 8004510: ffff0000 .word 0xffff0000 8004514: 51008108 .word 0x51008108 8004518: 52004000 .word 0x52004000 0800451c <__NVIC_SystemReset>: { 800451c: b480 push {r7} 800451e: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 8004520: f3bf 8f4f dsb sy } 8004524: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 8004526: 4b06 ldr r3, [pc, #24] @ (8004540 <__NVIC_SystemReset+0x24>) 8004528: 68db ldr r3, [r3, #12] 800452a: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800452e: 4904 ldr r1, [pc, #16] @ (8004540 <__NVIC_SystemReset+0x24>) 8004530: 4b04 ldr r3, [pc, #16] @ (8004544 <__NVIC_SystemReset+0x28>) 8004532: 4313 orrs r3, r2 8004534: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 8004536: f3bf 8f4f dsb sy } 800453a: bf00 nop __NOP(); 800453c: bf00 nop 800453e: e7fd b.n 800453c <__NVIC_SystemReset+0x20> 8004540: e000ed00 .word 0xe000ed00 8004544: 05fa0004 .word 0x05fa0004 08004548 : uint8_t outputDataBuffer[OUTPUT_DATA_BUFF_SIZE]; uint16_t outputDataBufferPos = 0; extern RNG_HandleTypeDef hrng; void UartTasksInit (void) { 8004548: b580 push {r7, lr} 800454a: af00 add r7, sp, #0 uart1TaskData.uartRxBuffer = uart1RxBuffer; 800454c: 4b24 ldr r3, [pc, #144] @ (80045e0 ) 800454e: 4a25 ldr r2, [pc, #148] @ (80045e4 ) 8004550: 601a str r2, [r3, #0] uart1TaskData.uartRxBufferLen = UART1_RX_BUFF_SIZE; 8004552: 4b23 ldr r3, [pc, #140] @ (80045e0 ) 8004554: f44f 7280 mov.w r2, #256 @ 0x100 8004558: 809a strh r2, [r3, #4] uart1TaskData.uartTxBuffer = uart1TxBuffer; 800455a: 4b21 ldr r3, [pc, #132] @ (80045e0 ) 800455c: 4a22 ldr r2, [pc, #136] @ (80045e8 ) 800455e: 609a str r2, [r3, #8] uart1TaskData.uartRxBufferLen = UART1_TX_BUFF_SIZE; 8004560: 4b1f ldr r3, [pc, #124] @ (80045e0 ) 8004562: f44f 7280 mov.w r2, #256 @ 0x100 8004566: 809a strh r2, [r3, #4] uart1TaskData.frameData = uart1TaskFrameData; 8004568: 4b1d ldr r3, [pc, #116] @ (80045e0 ) 800456a: 4a20 ldr r2, [pc, #128] @ (80045ec ) 800456c: 611a str r2, [r3, #16] uart1TaskData.frameDataLen = UART1_RX_BUFF_SIZE; 800456e: 4b1c ldr r3, [pc, #112] @ (80045e0 ) 8004570: f44f 7280 mov.w r2, #256 @ 0x100 8004574: 829a strh r2, [r3, #20] uart1TaskData.huart = &huart1; 8004576: 4b1a ldr r3, [pc, #104] @ (80045e0 ) 8004578: 4a1d ldr r2, [pc, #116] @ (80045f0 ) 800457a: 631a str r2, [r3, #48] @ 0x30 uart1TaskData.uartNumber = 1; 800457c: 4b18 ldr r3, [pc, #96] @ (80045e0 ) 800457e: 2201 movs r2, #1 8004580: f883 2034 strb.w r2, [r3, #52] @ 0x34 uart1TaskData.processDataCb = Uart1ReceivedDataProcessCallback; 8004584: 4b16 ldr r3, [pc, #88] @ (80045e0 ) 8004586: 4a1b ldr r2, [pc, #108] @ (80045f4 ) 8004588: 629a str r2, [r3, #40] @ 0x28 uart1TaskData.processRxDataMsgBuffer = NULL; 800458a: 4b15 ldr r3, [pc, #84] @ (80045e0 ) 800458c: 2200 movs r2, #0 800458e: 625a str r2, [r3, #36] @ 0x24 uart8TaskData.uartRxBuffer = uart8RxBuffer; 8004590: 4b19 ldr r3, [pc, #100] @ (80045f8 ) 8004592: 4a1a ldr r2, [pc, #104] @ (80045fc ) 8004594: 601a str r2, [r3, #0] uart8TaskData.uartRxBufferLen = UART8_RX_BUFF_SIZE; 8004596: 4b18 ldr r3, [pc, #96] @ (80045f8 ) 8004598: f44f 7280 mov.w r2, #256 @ 0x100 800459c: 809a strh r2, [r3, #4] uart8TaskData.uartTxBuffer = uart8TxBuffer; 800459e: 4b16 ldr r3, [pc, #88] @ (80045f8 ) 80045a0: 4a17 ldr r2, [pc, #92] @ (8004600 ) 80045a2: 609a str r2, [r3, #8] uart8TaskData.uartRxBufferLen = UART8_TX_BUFF_SIZE; 80045a4: 4b14 ldr r3, [pc, #80] @ (80045f8 ) 80045a6: f44f 7280 mov.w r2, #256 @ 0x100 80045aa: 809a strh r2, [r3, #4] uart8TaskData.frameData = uart8TaskFrameData; 80045ac: 4b12 ldr r3, [pc, #72] @ (80045f8 ) 80045ae: 4a15 ldr r2, [pc, #84] @ (8004604 ) 80045b0: 611a str r2, [r3, #16] uart8TaskData.frameDataLen = UART8_RX_BUFF_SIZE; 80045b2: 4b11 ldr r3, [pc, #68] @ (80045f8 ) 80045b4: f44f 7280 mov.w r2, #256 @ 0x100 80045b8: 829a strh r2, [r3, #20] uart8TaskData.huart = &huart8; 80045ba: 4b0f ldr r3, [pc, #60] @ (80045f8 ) 80045bc: 4a12 ldr r2, [pc, #72] @ (8004608 ) 80045be: 631a str r2, [r3, #48] @ 0x30 uart8TaskData.uartNumber = 8; 80045c0: 4b0d ldr r3, [pc, #52] @ (80045f8 ) 80045c2: 2208 movs r2, #8 80045c4: f883 2034 strb.w r2, [r3, #52] @ 0x34 uart8TaskData.processDataCb = Uart8ReceivedDataProcessCallback; 80045c8: 4b0b ldr r3, [pc, #44] @ (80045f8 ) 80045ca: 4a10 ldr r2, [pc, #64] @ (800460c ) 80045cc: 629a str r2, [r3, #40] @ 0x28 uart8TaskData.processRxDataMsgBuffer = NULL; 80045ce: 4b0a ldr r3, [pc, #40] @ (80045f8 ) 80045d0: 2200 movs r2, #0 80045d2: 625a str r2, [r3, #36] @ 0x24 #ifdef USE_UART8_INSTEAD_UART1 UartTaskCreate (&uart8TaskData); #else UartTaskCreate (&uart1TaskData); 80045d4: 4802 ldr r0, [pc, #8] @ (80045e0 ) 80045d6: f000 f81b bl 8004610 #endif } 80045da: bf00 nop 80045dc: bd80 pop {r7, pc} 80045de: bf00 nop 80045e0: 240010c8 .word 0x240010c8 80045e4: 24000ac8 .word 0x24000ac8 80045e8: 24000bc8 .word 0x24000bc8 80045ec: 24000cc8 .word 0x24000cc8 80045f0: 24000714 .word 0x24000714 80045f4: 08004cb9 .word 0x08004cb9 80045f8: 24001100 .word 0x24001100 80045fc: 24000dc8 .word 0x24000dc8 8004600: 24000ec8 .word 0x24000ec8 8004604: 24000fc8 .word 0x24000fc8 8004608: 24000680 .word 0x24000680 800460c: 08004c9d .word 0x08004c9d 08004610 : void UartTaskCreate (UartTaskData* uartTaskData) { 8004610: b580 push {r7, lr} 8004612: b08c sub sp, #48 @ 0x30 8004614: af00 add r7, sp, #0 8004616: 6078 str r0, [r7, #4] osThreadAttr_t osThreadAttrRxUart = { 0 }; 8004618: f107 030c add.w r3, r7, #12 800461c: 2224 movs r2, #36 @ 0x24 800461e: 2100 movs r1, #0 8004620: 4618 mov r0, r3 8004622: f013 ff21 bl 8018468 osThreadAttrRxUart.stack_size = configMINIMAL_STACK_SIZE * 2; 8004626: f44f 6380 mov.w r3, #1024 @ 0x400 800462a: 623b str r3, [r7, #32] osThreadAttrRxUart.priority = (osPriority_t)osPriorityHigh; 800462c: 2328 movs r3, #40 @ 0x28 800462e: 627b str r3, [r7, #36] @ 0x24 uartTaskData->uartRecieveTaskHandle = osThreadNew (UartRxTask, uartTaskData, &osThreadAttrRxUart); 8004630: f107 030c add.w r3, r7, #12 8004634: 461a mov r2, r3 8004636: 6879 ldr r1, [r7, #4] 8004638: 4804 ldr r0, [pc, #16] @ (800464c ) 800463a: f00e ff91 bl 8013560 800463e: 4602 mov r2, r0 8004640: 687b ldr r3, [r7, #4] 8004642: 619a str r2, [r3, #24] } 8004644: bf00 nop 8004646: 3730 adds r7, #48 @ 0x30 8004648: 46bd mov sp, r7 800464a: bd80 pop {r7, pc} 800464c: 08004765 .word 0x08004765 08004650 : void HAL_UART_RxCpltCallback (UART_HandleTypeDef* huart) { 8004650: b480 push {r7} 8004652: b083 sub sp, #12 8004654: af00 add r7, sp, #0 8004656: 6078 str r0, [r7, #4] } 8004658: bf00 nop 800465a: 370c adds r7, #12 800465c: 46bd mov sp, r7 800465e: f85d 7b04 ldr.w r7, [sp], #4 8004662: 4770 bx lr 08004664 : void HAL_UARTEx_RxEventCallback (UART_HandleTypeDef* huart, uint16_t Size) { 8004664: b580 push {r7, lr} 8004666: b082 sub sp, #8 8004668: af00 add r7, sp, #0 800466a: 6078 str r0, [r7, #4] 800466c: 460b mov r3, r1 800466e: 807b strh r3, [r7, #2] if (huart->Instance == USART1) { 8004670: 687b ldr r3, [r7, #4] 8004672: 681b ldr r3, [r3, #0] 8004674: 4a0c ldr r2, [pc, #48] @ (80046a8 ) 8004676: 4293 cmp r3, r2 8004678: d106 bne.n 8004688 HandleUartRxCallback (&uart1TaskData, huart, Size); 800467a: 887b ldrh r3, [r7, #2] 800467c: 461a mov r2, r3 800467e: 6879 ldr r1, [r7, #4] 8004680: 480a ldr r0, [pc, #40] @ (80046ac ) 8004682: f000 f823 bl 80046cc } else if (huart->Instance == UART8) { HandleUartRxCallback (&uart8TaskData, huart, Size); } } 8004686: e00a b.n 800469e } else if (huart->Instance == UART8) { 8004688: 687b ldr r3, [r7, #4] 800468a: 681b ldr r3, [r3, #0] 800468c: 4a08 ldr r2, [pc, #32] @ (80046b0 ) 800468e: 4293 cmp r3, r2 8004690: d105 bne.n 800469e HandleUartRxCallback (&uart8TaskData, huart, Size); 8004692: 887b ldrh r3, [r7, #2] 8004694: 461a mov r2, r3 8004696: 6879 ldr r1, [r7, #4] 8004698: 4806 ldr r0, [pc, #24] @ (80046b4 ) 800469a: f000 f817 bl 80046cc } 800469e: bf00 nop 80046a0: 3708 adds r7, #8 80046a2: 46bd mov sp, r7 80046a4: bd80 pop {r7, pc} 80046a6: bf00 nop 80046a8: 40011000 .word 0x40011000 80046ac: 240010c8 .word 0x240010c8 80046b0: 40007c00 .word 0x40007c00 80046b4: 24001100 .word 0x24001100 080046b8 : void HAL_UART_TxCpltCallback (UART_HandleTypeDef* huart) { 80046b8: b480 push {r7} 80046ba: b083 sub sp, #12 80046bc: af00 add r7, sp, #0 80046be: 6078 str r0, [r7, #4] if (huart->Instance == UART8) { } } 80046c0: bf00 nop 80046c2: 370c adds r7, #12 80046c4: 46bd mov sp, r7 80046c6: f85d 7b04 ldr.w r7, [sp], #4 80046ca: 4770 bx lr 080046cc : void HandleUartRxCallback (UartTaskData* uartTaskData, UART_HandleTypeDef* huart, uint16_t Size) { 80046cc: b580 push {r7, lr} 80046ce: b088 sub sp, #32 80046d0: af02 add r7, sp, #8 80046d2: 60f8 str r0, [r7, #12] 80046d4: 60b9 str r1, [r7, #8] 80046d6: 4613 mov r3, r2 80046d8: 80fb strh r3, [r7, #6] BaseType_t pxHigherPriorityTaskWoken = pdFALSE; 80046da: 2300 movs r3, #0 80046dc: 617b str r3, [r7, #20] osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 80046de: 68fb ldr r3, [r7, #12] 80046e0: 6a1b ldr r3, [r3, #32] 80046e2: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80046e6: 4618 mov r0, r3 80046e8: f00f f965 bl 80139b6 memcpy (&(uartTaskData->frameData[uartTaskData->frameBytesCount]), uartTaskData->uartRxBuffer, Size); 80046ec: 68fb ldr r3, [r7, #12] 80046ee: 691b ldr r3, [r3, #16] 80046f0: 68fa ldr r2, [r7, #12] 80046f2: 8ad2 ldrh r2, [r2, #22] 80046f4: 1898 adds r0, r3, r2 80046f6: 68fb ldr r3, [r7, #12] 80046f8: 681b ldr r3, [r3, #0] 80046fa: 88fa ldrh r2, [r7, #6] 80046fc: 4619 mov r1, r3 80046fe: f013 ff88 bl 8018612 uartTaskData->frameBytesCount += Size; 8004702: 68fb ldr r3, [r7, #12] 8004704: 8ada ldrh r2, [r3, #22] 8004706: 88fb ldrh r3, [r7, #6] 8004708: 4413 add r3, r2 800470a: b29a uxth r2, r3 800470c: 68fb ldr r3, [r7, #12] 800470e: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 8004710: 68fb ldr r3, [r7, #12] 8004712: 6a1b ldr r3, [r3, #32] 8004714: 4618 mov r0, r3 8004716: f00f f999 bl 8013a4c xTaskNotifyFromISR (uartTaskData->uartRecieveTaskHandle, Size, eSetValueWithOverwrite, &pxHigherPriorityTaskWoken); 800471a: 68fb ldr r3, [r7, #12] 800471c: 6998 ldr r0, [r3, #24] 800471e: 88f9 ldrh r1, [r7, #6] 8004720: f107 0314 add.w r3, r7, #20 8004724: 9300 str r3, [sp, #0] 8004726: 2300 movs r3, #0 8004728: 2203 movs r2, #3 800472a: f011 fe89 bl 8016440 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 800472e: 68fb ldr r3, [r7, #12] 8004730: 6b18 ldr r0, [r3, #48] @ 0x30 8004732: 68fb ldr r3, [r7, #12] 8004734: 6819 ldr r1, [r3, #0] 8004736: 68fb ldr r3, [r7, #12] 8004738: 889b ldrh r3, [r3, #4] 800473a: 461a mov r2, r3 800473c: f00e fde3 bl 8013306 portEND_SWITCHING_ISR (pxHigherPriorityTaskWoken); 8004740: 697b ldr r3, [r7, #20] 8004742: 2b00 cmp r3, #0 8004744: d007 beq.n 8004756 8004746: 4b06 ldr r3, [pc, #24] @ (8004760 ) 8004748: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800474c: 601a str r2, [r3, #0] 800474e: f3bf 8f4f dsb sy 8004752: f3bf 8f6f isb sy } 8004756: bf00 nop 8004758: 3718 adds r7, #24 800475a: 46bd mov sp, r7 800475c: bd80 pop {r7, pc} 800475e: bf00 nop 8004760: e000ed04 .word 0xe000ed04 08004764 : void UartRxTask (void* argument) { 8004764: b580 push {r7, lr} 8004766: b0d2 sub sp, #328 @ 0x148 8004768: af02 add r7, sp, #8 800476a: f507 73a0 add.w r3, r7, #320 @ 0x140 800476e: f5a3 739e sub.w r3, r3, #316 @ 0x13c 8004772: 6018 str r0, [r3, #0] UartTaskData* uartTaskData = (UartTaskData*)argument; 8004774: f507 73a0 add.w r3, r7, #320 @ 0x140 8004778: f5a3 739e sub.w r3, r3, #316 @ 0x13c 800477c: 681b ldr r3, [r3, #0] 800477e: f8c7 312c str.w r3, [r7, #300] @ 0x12c SerialProtocolFrameData spFrameData = { 0 }; 8004782: f507 73a0 add.w r3, r7, #320 @ 0x140 8004786: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800478a: 4618 mov r0, r3 800478c: f44f 7386 mov.w r3, #268 @ 0x10c 8004790: 461a mov r2, r3 8004792: 2100 movs r1, #0 8004794: f013 fe68 bl 8018468 uint32_t bytesRec = 0; 8004798: f507 73a0 add.w r3, r7, #320 @ 0x140 800479c: f5a3 739a sub.w r3, r3, #308 @ 0x134 80047a0: 2200 movs r2, #0 80047a2: 601a str r2, [r3, #0] uint32_t crc = 0; 80047a4: 2300 movs r3, #0 80047a6: f8c7 3128 str.w r3, [r7, #296] @ 0x128 uint16_t frameCommandRaw = 0x0000; 80047aa: 2300 movs r3, #0 80047ac: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 uint16_t frameBytesCount = 0; 80047b0: 2300 movs r3, #0 80047b2: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 uint16_t frameCrc = 0; 80047b6: 2300 movs r3, #0 80047b8: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 uint16_t frameTotalLength = 0; 80047bc: 2300 movs r3, #0 80047be: f8a7 313e strh.w r3, [r7, #318] @ 0x13e uint16_t dataToSend = 0; 80047c2: 2300 movs r3, #0 80047c4: f8a7 313c strh.w r3, [r7, #316] @ 0x13c portBASE_TYPE crcPass = pdFAIL; 80047c8: 2300 movs r3, #0 80047ca: f8c7 3138 str.w r3, [r7, #312] @ 0x138 portBASE_TYPE proceed = pdFALSE; 80047ce: 2300 movs r3, #0 80047d0: f8c7 3134 str.w r3, [r7, #308] @ 0x134 portBASE_TYPE frameTimeout = pdFAIL; 80047d4: 2300 movs r3, #0 80047d6: f8c7 311c str.w r3, [r7, #284] @ 0x11c enum SerialReceiverStates receverState = srWaitForHeader; 80047da: 2300 movs r3, #0 80047dc: f887 3133 strb.w r3, [r7, #307] @ 0x133 uartTaskData->rxDataBufferMutex = osMutexNew (NULL); 80047e0: 2000 movs r0, #0 80047e2: f00f f862 bl 80138aa 80047e6: 4602 mov r2, r0 80047e8: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80047ec: 621a str r2, [r3, #32] HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 80047ee: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80047f2: 6b18 ldr r0, [r3, #48] @ 0x30 80047f4: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80047f8: 6819 ldr r1, [r3, #0] 80047fa: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80047fe: 889b ldrh r3, [r3, #4] 8004800: 461a mov r2, r3 8004802: f00e fd80 bl 8013306 while (pdTRUE) { frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8004806: f107 020c add.w r2, r7, #12 800480a: f44f 63fa mov.w r3, #2000 @ 0x7d0 800480e: 2100 movs r1, #0 8004810: 2000 movs r0, #0 8004812: f011 fcf3 bl 80161fc 8004816: 4603 mov r3, r0 8004818: 2b00 cmp r3, #0 800481a: bf0c ite eq 800481c: 2301 moveq r3, #1 800481e: 2300 movne r3, #0 8004820: b2db uxtb r3, r3 8004822: f8c7 311c str.w r3, [r7, #284] @ 0x11c osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004826: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800482a: 6a1b ldr r3, [r3, #32] 800482c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004830: 4618 mov r0, r3 8004832: f00f f8c0 bl 80139b6 frameBytesCount = uartTaskData->frameBytesCount; 8004836: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800483a: 8adb ldrh r3, [r3, #22] 800483c: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 osMutexRelease (uartTaskData->rxDataBufferMutex); 8004840: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004844: 6a1b ldr r3, [r3, #32] 8004846: 4618 mov r0, r3 8004848: f00f f900 bl 8013a4c if ((frameTimeout == pdTRUE) && (frameBytesCount > 0)) { 800484c: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8004850: 2b01 cmp r3, #1 8004852: d10a bne.n 800486a 8004854: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004858: 2b00 cmp r3, #0 800485a: d006 beq.n 800486a receverState = srFail; 800485c: 2304 movs r3, #4 800485e: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdTRUE; 8004862: 2301 movs r3, #1 8004864: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004868: e01b b.n 80048a2 } else { if (frameTimeout == pdFALSE) { 800486a: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 800486e: 2b00 cmp r3, #0 8004870: d103 bne.n 800487a proceed = pdTRUE; 8004872: 2301 movs r3, #1 8004874: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004878: e206 b.n 8004c88 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: RX bytes received: %ld\n", uartTaskData->uartNumber, bytesRec); #endif } else { if (uartTaskData->huart->RxState == HAL_UART_STATE_READY) { 800487a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800487e: 6b1b ldr r3, [r3, #48] @ 0x30 8004880: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004884: 2b20 cmp r3, #32 8004886: f040 81ff bne.w 8004c88 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 800488a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800488e: 6b18 ldr r0, [r3, #48] @ 0x30 8004890: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004894: 6819 ldr r1, [r3, #0] 8004896: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800489a: 889b ldrh r3, [r3, #4] 800489c: 461a mov r2, r3 800489e: f00e fd32 bl 8013306 } } } while (proceed) { 80048a2: e1f1 b.n 8004c88 switch (receverState) { 80048a4: f897 3133 ldrb.w r3, [r7, #307] @ 0x133 80048a8: 2b04 cmp r3, #4 80048aa: f200 81c8 bhi.w 8004c3e 80048ae: a201 add r2, pc, #4 @ (adr r2, 80048b4 ) 80048b0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80048b4: 080048c9 .word 0x080048c9 80048b8: 08004a2b .word 0x08004a2b 80048bc: 08004a0f .word 0x08004a0f 80048c0: 08004abb .word 0x08004abb 80048c4: 08004b67 .word 0x08004b67 case srWaitForHeader: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 80048c8: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80048cc: 6a1b ldr r3, [r3, #32] 80048ce: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80048d2: 4618 mov r0, r3 80048d4: f00f f86f bl 80139b6 if (uartTaskData->frameData[0] == FRAME_INDICATOR) { 80048d8: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80048dc: 691b ldr r3, [r3, #16] 80048de: 781b ldrb r3, [r3, #0] 80048e0: 2baa cmp r3, #170 @ 0xaa 80048e2: f040 8082 bne.w 80049ea if (frameBytesCount > FRAME_ID_LENGTH) { 80048e6: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 80048ea: 2b02 cmp r3, #2 80048ec: d914 bls.n 8004918 spFrameData.frameHeader.frameId = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_ID_LENGTH - FRAME_COMMAND_LENGTH])); 80048ee: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80048f2: 691b ldr r3, [r3, #16] 80048f4: 3302 adds r3, #2 80048f6: 781b ldrb r3, [r3, #0] 80048f8: 021b lsls r3, r3, #8 80048fa: b21a sxth r2, r3 80048fc: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004900: 691b ldr r3, [r3, #16] 8004902: 3301 adds r3, #1 8004904: 781b ldrb r3, [r3, #0] 8004906: b21b sxth r3, r3 8004908: 4313 orrs r3, r2 800490a: b21b sxth r3, r3 800490c: b29a uxth r2, r3 spFrameData.frameHeader.frameId = 800490e: f507 73a0 add.w r3, r7, #320 @ 0x140 8004912: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004916: 801a strh r2, [r3, #0] } if (frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH) { 8004918: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 800491c: 2b04 cmp r3, #4 800491e: d923 bls.n 8004968 frameCommandRaw = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_COMMAND_LENGTH])); 8004920: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004924: 691b ldr r3, [r3, #16] 8004926: 3304 adds r3, #4 8004928: 781b ldrb r3, [r3, #0] 800492a: 021b lsls r3, r3, #8 800492c: b21a sxth r2, r3 800492e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004932: 691b ldr r3, [r3, #16] 8004934: 3303 adds r3, #3 8004936: 781b ldrb r3, [r3, #0] 8004938: b21b sxth r3, r3 800493a: 4313 orrs r3, r2 800493c: b21b sxth r3, r3 800493e: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 spFrameData.frameHeader.frameCommand = (SerialProtocolCommands)(frameCommandRaw & 0x7FFF); 8004942: f8b7 3126 ldrh.w r3, [r7, #294] @ 0x126 8004946: b2da uxtb r2, r3 8004948: f507 73a0 add.w r3, r7, #320 @ 0x140 800494c: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004950: 709a strb r2, [r3, #2] spFrameData.frameHeader.isResponseFrame = (frameCommandRaw & 0x8000) != 0 ? pdTRUE : pdFALSE; 8004952: f9b7 3126 ldrsh.w r3, [r7, #294] @ 0x126 8004956: 13db asrs r3, r3, #15 8004958: b21b sxth r3, r3 800495a: f003 0201 and.w r2, r3, #1 800495e: f507 73a0 add.w r3, r7, #320 @ 0x140 8004962: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004966: 609a str r2, [r3, #8] } if ((frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH) && ((spFrameData.frameHeader.frameCommand & 0x8000) != 0)) { 8004968: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 800496c: 2b05 cmp r3, #5 800496e: d913 bls.n 8004998 8004970: f507 73a0 add.w r3, r7, #320 @ 0x140 8004974: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004978: 789b ldrb r3, [r3, #2] 800497a: f403 4300 and.w r3, r3, #32768 @ 0x8000 800497e: 2b00 cmp r3, #0 8004980: d00a beq.n 8004998 spFrameData.frameHeader.respStatus = (SerialProtocolRespStatus)(uartTaskData->frameData[FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH]); 8004982: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004986: 691b ldr r3, [r3, #16] 8004988: 3305 adds r3, #5 800498a: 781b ldrb r3, [r3, #0] 800498c: b25a sxtb r2, r3 800498e: f507 73a0 add.w r3, r7, #320 @ 0x140 8004992: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004996: 70da strb r2, [r3, #3] } if (frameBytesCount >= FRAME_HEADER_LENGTH) { 8004998: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 800499c: 2b07 cmp r3, #7 800499e: d920 bls.n 80049e2 spFrameData.frameHeader.frameDataLength = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH])); 80049a0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80049a4: 691b ldr r3, [r3, #16] 80049a6: 3306 adds r3, #6 80049a8: 781b ldrb r3, [r3, #0] 80049aa: 021b lsls r3, r3, #8 80049ac: b21a sxth r2, r3 80049ae: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80049b2: 691b ldr r3, [r3, #16] 80049b4: 3305 adds r3, #5 80049b6: 781b ldrb r3, [r3, #0] 80049b8: b21b sxth r3, r3 80049ba: 4313 orrs r3, r2 80049bc: b21b sxth r3, r3 80049be: b29a uxth r2, r3 80049c0: f507 73a0 add.w r3, r7, #320 @ 0x140 80049c4: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80049c8: 809a strh r2, [r3, #4] frameTotalLength = FRAME_HEADER_LENGTH + spFrameData.frameHeader.frameDataLength + FRAME_CRC_LENGTH; 80049ca: f507 73a0 add.w r3, r7, #320 @ 0x140 80049ce: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80049d2: 889b ldrh r3, [r3, #4] 80049d4: 330a adds r3, #10 80049d6: f8a7 313e strh.w r3, [r7, #318] @ 0x13e receverState = srRecieveData; 80049da: 2302 movs r3, #2 80049dc: f887 3133 strb.w r3, [r7, #307] @ 0x133 80049e0: e00e b.n 8004a00 } else { proceed = pdFALSE; 80049e2: 2300 movs r3, #0 80049e4: f8c7 3134 str.w r3, [r7, #308] @ 0x134 80049e8: e00a b.n 8004a00 } } else { if (frameBytesCount > 0) { 80049ea: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 80049ee: 2b00 cmp r3, #0 80049f0: d003 beq.n 80049fa receverState = srFail; 80049f2: 2304 movs r3, #4 80049f4: f887 3133 strb.w r3, [r7, #307] @ 0x133 80049f8: e002 b.n 8004a00 } else { proceed = pdFALSE; 80049fa: 2300 movs r3, #0 80049fc: f8c7 3134 str.w r3, [r7, #308] @ 0x134 } } osMutexRelease (uartTaskData->rxDataBufferMutex); 8004a00: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004a04: 6a1b ldr r3, [r3, #32] 8004a06: 4618 mov r0, r3 8004a08: f00f f820 bl 8013a4c break; 8004a0c: e13c b.n 8004c88 case srRecieveData: if (frameBytesCount >= frameTotalLength) { 8004a0e: f8b7 2124 ldrh.w r2, [r7, #292] @ 0x124 8004a12: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004a16: 429a cmp r2, r3 8004a18: d303 bcc.n 8004a22 receverState = srCheckCrc; 8004a1a: 2301 movs r3, #1 8004a1c: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { proceed = pdFALSE; } break; 8004a20: e132 b.n 8004c88 proceed = pdFALSE; 8004a22: 2300 movs r3, #0 8004a24: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 8004a28: e12e b.n 8004c88 case srCheckCrc: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004a2a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004a2e: 6a1b ldr r3, [r3, #32] 8004a30: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004a34: 4618 mov r0, r3 8004a36: f00e ffbe bl 80139b6 frameCrc = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[frameTotalLength - FRAME_CRC_LENGTH])); 8004a3a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004a3e: 691a ldr r2, [r3, #16] 8004a40: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004a44: 3b01 subs r3, #1 8004a46: 4413 add r3, r2 8004a48: 781b ldrb r3, [r3, #0] 8004a4a: 021b lsls r3, r3, #8 8004a4c: b21a sxth r2, r3 8004a4e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004a52: 6919 ldr r1, [r3, #16] 8004a54: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004a58: 3b02 subs r3, #2 8004a5a: 440b add r3, r1 8004a5c: 781b ldrb r3, [r3, #0] 8004a5e: b21b sxth r3, r3 8004a60: 4313 orrs r3, r2 8004a62: b21b sxth r3, r3 8004a64: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)(uartTaskData->frameData), frameTotalLength - FRAME_CRC_LENGTH); 8004a68: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004a6c: 6919 ldr r1, [r3, #16] 8004a6e: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004a72: 3b02 subs r3, #2 8004a74: 461a mov r2, r3 8004a76: 4887 ldr r0, [pc, #540] @ (8004c94 ) 8004a78: f002 ffac bl 80079d4 8004a7c: f8c7 0128 str.w r0, [r7, #296] @ 0x128 osMutexRelease (uartTaskData->rxDataBufferMutex); 8004a80: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004a84: 6a1b ldr r3, [r3, #32] 8004a86: 4618 mov r0, r3 8004a88: f00e ffe0 bl 8013a4c crcPass = frameCrc == crc; 8004a8c: f8b7 3122 ldrh.w r3, [r7, #290] @ 0x122 8004a90: f8d7 2128 ldr.w r2, [r7, #296] @ 0x128 8004a94: 429a cmp r2, r3 8004a96: bf0c ite eq 8004a98: 2301 moveq r3, #1 8004a9a: 2300 movne r3, #0 8004a9c: b2db uxtb r3, r3 8004a9e: f8c7 3138 str.w r3, [r7, #312] @ 0x138 if (crcPass) { 8004aa2: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 8004aa6: 2b00 cmp r3, #0 8004aa8: d003 beq.n 8004ab2 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: Frame CRC PASS\n", uartTaskData->uartNumber); #endif receverState = srExecuteCmd; 8004aaa: 2303 movs r3, #3 8004aac: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { receverState = srFail; } break; 8004ab0: e0ea b.n 8004c88 receverState = srFail; 8004ab2: 2304 movs r3, #4 8004ab4: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004ab8: e0e6 b.n 8004c88 case srExecuteCmd: if ((uartTaskData->processDataCb != NULL) || (uartTaskData->processRxDataMsgBuffer != NULL)) { 8004aba: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004abe: 6a9b ldr r3, [r3, #40] @ 0x28 8004ac0: 2b00 cmp r3, #0 8004ac2: d104 bne.n 8004ace 8004ac4: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004ac8: 6a5b ldr r3, [r3, #36] @ 0x24 8004aca: 2b00 cmp r3, #0 8004acc: d01e beq.n 8004b0c osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004ace: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004ad2: 6a1b ldr r3, [r3, #32] 8004ad4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004ad8: 4618 mov r0, r3 8004ada: f00e ff6c bl 80139b6 memcpy (spFrameData.dataBuffer, &(uartTaskData->frameData[FRAME_HEADER_LENGTH]), spFrameData.frameHeader.frameDataLength); 8004ade: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004ae2: 691b ldr r3, [r3, #16] 8004ae4: f103 0108 add.w r1, r3, #8 8004ae8: f507 73a0 add.w r3, r7, #320 @ 0x140 8004aec: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004af0: 889b ldrh r3, [r3, #4] 8004af2: 461a mov r2, r3 8004af4: f107 0310 add.w r3, r7, #16 8004af8: 330c adds r3, #12 8004afa: 4618 mov r0, r3 8004afc: f013 fd89 bl 8018612 osMutexRelease (uartTaskData->rxDataBufferMutex); 8004b00: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004b04: 6a1b ldr r3, [r3, #32] 8004b06: 4618 mov r0, r3 8004b08: f00e ffa0 bl 8013a4c } if (uartTaskData->processRxDataMsgBuffer != NULL) { 8004b0c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004b10: 6a5b ldr r3, [r3, #36] @ 0x24 8004b12: 2b00 cmp r3, #0 8004b14: d015 beq.n 8004b42 if (xMessageBufferSend (uartTaskData->processRxDataMsgBuffer, &spFrameData, sizeof (SerialProtocolFrameHeader) + spFrameData.frameHeader.frameDataLength, pdMS_TO_TICKS (200)) == pdFALSE) { 8004b16: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004b1a: 6a58 ldr r0, [r3, #36] @ 0x24 8004b1c: f507 73a0 add.w r3, r7, #320 @ 0x140 8004b20: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004b24: 889b ldrh r3, [r3, #4] 8004b26: f103 020c add.w r2, r3, #12 8004b2a: f107 0110 add.w r1, r7, #16 8004b2e: 23c8 movs r3, #200 @ 0xc8 8004b30: f010 f9ae bl 8014e90 8004b34: 4603 mov r3, r0 8004b36: 2b00 cmp r3, #0 8004b38: d103 bne.n 8004b42 receverState = srFail; 8004b3a: 2304 movs r3, #4 8004b3c: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004b40: e0a2 b.n 8004c88 } } if (uartTaskData->processDataCb != NULL) { 8004b42: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004b46: 6a9b ldr r3, [r3, #40] @ 0x28 8004b48: 2b00 cmp r3, #0 8004b4a: d008 beq.n 8004b5e uartTaskData->processDataCb (uartTaskData, &spFrameData); 8004b4c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004b50: 6a9b ldr r3, [r3, #40] @ 0x28 8004b52: f107 0210 add.w r2, r7, #16 8004b56: 4611 mov r1, r2 8004b58: f8d7 012c ldr.w r0, [r7, #300] @ 0x12c 8004b5c: 4798 blx r3 } receverState = srFinish; 8004b5e: 2305 movs r3, #5 8004b60: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004b64: e090 b.n 8004c88 case srFail: dataToSend = 0; 8004b66: 2300 movs r3, #0 8004b68: f8a7 313c strh.w r3, [r7, #316] @ 0x13c if ((frameTimeout == pdTRUE) && (frameBytesCount > 2)) { 8004b6c: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8004b70: 2b01 cmp r3, #1 8004b72: d11c bne.n 8004bae 8004b74: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004b78: 2b02 cmp r3, #2 8004b7a: d918 bls.n 8004bae dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0); 8004b7c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004b80: 6898 ldr r0, [r3, #8] 8004b82: f507 73a0 add.w r3, r7, #320 @ 0x140 8004b86: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004b8a: 8819 ldrh r1, [r3, #0] 8004b8c: f507 73a0 add.w r3, r7, #320 @ 0x140 8004b90: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004b94: 789a ldrb r2, [r3, #2] 8004b96: 2300 movs r3, #0 8004b98: 9301 str r3, [sp, #4] 8004b9a: 2300 movs r3, #0 8004b9c: 9300 str r3, [sp, #0] 8004b9e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8004ba2: f7fe fd37 bl 8003614 8004ba6: 4603 mov r3, r0 8004ba8: f8a7 313c strh.w r3, [r7, #316] @ 0x13c 8004bac: e034 b.n 8004c18 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: RX data receiver timeout!\n", uartTaskData->uartNumber); #endif } else if (!crcPass) { 8004bae: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 8004bb2: 2b00 cmp r3, #0 8004bb4: d118 bne.n 8004be8 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spCrcFail, NULL, 0); 8004bb6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004bba: 6898 ldr r0, [r3, #8] 8004bbc: f507 73a0 add.w r3, r7, #320 @ 0x140 8004bc0: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004bc4: 8819 ldrh r1, [r3, #0] 8004bc6: f507 73a0 add.w r3, r7, #320 @ 0x140 8004bca: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004bce: 789a ldrb r2, [r3, #2] 8004bd0: 2300 movs r3, #0 8004bd2: 9301 str r3, [sp, #4] 8004bd4: 2300 movs r3, #0 8004bd6: 9300 str r3, [sp, #0] 8004bd8: f06f 0301 mvn.w r3, #1 8004bdc: f7fe fd1a bl 8003614 8004be0: 4603 mov r3, r0 8004be2: f8a7 313c strh.w r3, [r7, #316] @ 0x13c 8004be6: e017 b.n 8004c18 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: Frame CRC FAIL\n", uartTaskData->uartNumber); #endif } else { dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spInternalError, NULL, 0); 8004be8: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004bec: 6898 ldr r0, [r3, #8] 8004bee: f507 73a0 add.w r3, r7, #320 @ 0x140 8004bf2: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004bf6: 8819 ldrh r1, [r3, #0] 8004bf8: f507 73a0 add.w r3, r7, #320 @ 0x140 8004bfc: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004c00: 789a ldrb r2, [r3, #2] 8004c02: 2300 movs r3, #0 8004c04: 9301 str r3, [sp, #4] 8004c06: 2300 movs r3, #0 8004c08: 9300 str r3, [sp, #0] 8004c0a: f06f 0303 mvn.w r3, #3 8004c0e: f7fe fd01 bl 8003614 8004c12: 4603 mov r3, r0 8004c14: f8a7 313c strh.w r3, [r7, #316] @ 0x13c } if (dataToSend > 0) { 8004c18: f8b7 313c ldrh.w r3, [r7, #316] @ 0x13c 8004c1c: 2b00 cmp r3, #0 8004c1e: d00a beq.n 8004c36 HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 8004c20: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c24: 6b18 ldr r0, [r3, #48] @ 0x30 8004c26: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c2a: 689b ldr r3, [r3, #8] 8004c2c: f8b7 213c ldrh.w r2, [r7, #316] @ 0x13c 8004c30: 4619 mov r1, r3 8004c32: f00b fe93 bl 801095c } #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: TX bytes sent: %d\n", dataToSend, uartTaskData->uartNumber); #endif receverState = srFinish; 8004c36: 2305 movs r3, #5 8004c38: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004c3c: e024 b.n 8004c88 case srFinish: default: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004c3e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c42: 6a1b ldr r3, [r3, #32] 8004c44: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004c48: 4618 mov r0, r3 8004c4a: f00e feb4 bl 80139b6 uartTaskData->frameBytesCount = 0; 8004c4e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c52: 2200 movs r2, #0 8004c54: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 8004c56: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c5a: 6a1b ldr r3, [r3, #32] 8004c5c: 4618 mov r0, r3 8004c5e: f00e fef5 bl 8013a4c spFrameData.frameHeader.frameCommand = spUnknown; 8004c62: f507 73a0 add.w r3, r7, #320 @ 0x140 8004c66: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004c6a: 2212 movs r2, #18 8004c6c: 709a strb r2, [r3, #2] frameTotalLength = 0; 8004c6e: 2300 movs r3, #0 8004c70: f8a7 313e strh.w r3, [r7, #318] @ 0x13e outputDataBufferPos = 0; 8004c74: 4b08 ldr r3, [pc, #32] @ (8004c98 ) 8004c76: 2200 movs r2, #0 8004c78: 801a strh r2, [r3, #0] receverState = srWaitForHeader; 8004c7a: 2300 movs r3, #0 8004c7c: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdFALSE; 8004c80: 2300 movs r3, #0 8004c82: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 8004c86: bf00 nop while (proceed) { 8004c88: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 8004c8c: 2b00 cmp r3, #0 8004c8e: f47f ae09 bne.w 80048a4 frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8004c92: e5b8 b.n 8004806 8004c94: 24000540 .word 0x24000540 8004c98: 240011b8 .word 0x240011b8 08004c9c : } } } } void Uart8ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 8004c9c: b580 push {r7, lr} 8004c9e: b082 sub sp, #8 8004ca0: af00 add r7, sp, #0 8004ca2: 6078 str r0, [r7, #4] 8004ca4: 6039 str r1, [r7, #0] Uart1ReceivedDataProcessCallback (arg, spFrameData); 8004ca6: 6839 ldr r1, [r7, #0] 8004ca8: 6878 ldr r0, [r7, #4] 8004caa: f000 f805 bl 8004cb8 } 8004cae: bf00 nop 8004cb0: 3708 adds r7, #8 8004cb2: 46bd mov sp, r7 8004cb4: bd80 pop {r7, pc} ... 08004cb8 : void Uart1ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 8004cb8: b590 push {r4, r7, lr} 8004cba: b0ab sub sp, #172 @ 0xac 8004cbc: af06 add r7, sp, #24 8004cbe: 6078 str r0, [r7, #4] 8004cc0: 6039 str r1, [r7, #0] 8004cc2: f107 0390 add.w r3, r7, #144 @ 0x90 8004cc6: 3b88 subs r3, #136 @ 0x88 8004cc8: 331f adds r3, #31 8004cca: 095b lsrs r3, r3, #5 8004ccc: 015c lsls r4, r3, #5 UartTaskData* uartTaskData = (UartTaskData*)arg; 8004cce: 687b ldr r3, [r7, #4] 8004cd0: 66fb str r3, [r7, #108] @ 0x6c uint16_t dataToSend = 0; 8004cd2: 2300 movs r3, #0 8004cd4: f8a7 306a strh.w r3, [r7, #106] @ 0x6a outputDataBufferPos = 0; 8004cd8: 4bba ldr r3, [pc, #744] @ (8004fc4 ) 8004cda: 2200 movs r2, #0 8004cdc: 801a strh r2, [r3, #0] uint16_t inputDataBufferPos = 0; 8004cde: 2300 movs r3, #0 8004ce0: f8a7 3054 strh.w r3, [r7, #84] @ 0x54 SerialProtocolRespStatus respStatus = spUnknownCommand; 8004ce4: 23fd movs r3, #253 @ 0xfd 8004ce6: f887 308f strb.w r3, [r7, #143] @ 0x8f switch (spFrameData->frameHeader.frameCommand) { 8004cea: 683b ldr r3, [r7, #0] 8004cec: 789b ldrb r3, [r3, #2] 8004cee: 2b11 cmp r3, #17 8004cf0: f200 8522 bhi.w 8005738 8004cf4: a201 add r2, pc, #4 @ (adr r2, 8004cfc ) 8004cf6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004cfa: bf00 nop 8004cfc: 08004d45 .word 0x08004d45 8004d00: 08004e55 .word 0x08004e55 8004d04: 08005041 .word 0x08005041 8004d08: 080050fd .word 0x080050fd 8004d0c: 0800519f .word 0x0800519f 8004d10: 080052bd .word 0x080052bd 8004d14: 08005345 .word 0x08005345 8004d18: 08005241 .word 0x08005241 8004d1c: 0800539b .word 0x0800539b 8004d20: 0800540d .word 0x0800540d 8004d24: 08005473 .word 0x08005473 8004d28: 080054d9 .word 0x080054d9 8004d2c: 0800553b .word 0x0800553b 8004d30: 0800559f .word 0x0800559f 8004d34: 08005601 .word 0x08005601 8004d38: 08005665 .word 0x08005665 8004d3c: 08005691 .word 0x08005691 8004d40: 080056e5 .word 0x080056e5 case spGetElectricalMeasurments: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8004d44: 4ba0 ldr r3, [pc, #640] @ (8004fc8 ) 8004d46: 681b ldr r3, [r3, #0] 8004d48: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004d4c: 4618 mov r0, r3 8004d4e: f00e fe32 bl 80139b6 8004d52: 4603 mov r3, r0 8004d54: 2b00 cmp r3, #0 8004d56: d178 bne.n 8004e4a for (int i = 0; i < 3; i++) { 8004d58: 2300 movs r3, #0 8004d5a: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8004d5e: e00e b.n 8004d7e WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltageRMS[i], sizeof (float)); 8004d60: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8004d64: 009b lsls r3, r3, #2 8004d66: 4a99 ldr r2, [pc, #612] @ (8004fcc ) 8004d68: 441a add r2, r3 8004d6a: 2304 movs r3, #4 8004d6c: 4995 ldr r1, [pc, #596] @ (8004fc4 ) 8004d6e: 4898 ldr r0, [pc, #608] @ (8004fd0 ) 8004d70: f7fe fbb6 bl 80034e0 for (int i = 0; i < 3; i++) { 8004d74: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8004d78: 3301 adds r3, #1 8004d7a: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8004d7e: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8004d82: 2b02 cmp r3, #2 8004d84: ddec ble.n 8004d60 } for (int i = 0; i < 3; i++) { 8004d86: 2300 movs r3, #0 8004d88: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8004d8c: e010 b.n 8004db0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltagePeak[i], sizeof (float)); 8004d8e: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8004d92: 3302 adds r3, #2 8004d94: 009b lsls r3, r3, #2 8004d96: 4a8d ldr r2, [pc, #564] @ (8004fcc ) 8004d98: 4413 add r3, r2 8004d9a: 1d1a adds r2, r3, #4 8004d9c: 2304 movs r3, #4 8004d9e: 4989 ldr r1, [pc, #548] @ (8004fc4 ) 8004da0: 488b ldr r0, [pc, #556] @ (8004fd0 ) 8004da2: f7fe fb9d bl 80034e0 for (int i = 0; i < 3; i++) { 8004da6: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8004daa: 3301 adds r3, #1 8004dac: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8004db0: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8004db4: 2b02 cmp r3, #2 8004db6: ddea ble.n 8004d8e } for (int i = 0; i < 3; i++) { 8004db8: 2300 movs r3, #0 8004dba: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8004dbe: e00f b.n 8004de0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentRMS[i], sizeof (float)); 8004dc0: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8004dc4: 3306 adds r3, #6 8004dc6: 009b lsls r3, r3, #2 8004dc8: 4a80 ldr r2, [pc, #512] @ (8004fcc ) 8004dca: 441a add r2, r3 8004dcc: 2304 movs r3, #4 8004dce: 497d ldr r1, [pc, #500] @ (8004fc4 ) 8004dd0: 487f ldr r0, [pc, #508] @ (8004fd0 ) 8004dd2: f7fe fb85 bl 80034e0 for (int i = 0; i < 3; i++) { 8004dd6: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8004dda: 3301 adds r3, #1 8004ddc: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8004de0: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8004de4: 2b02 cmp r3, #2 8004de6: ddeb ble.n 8004dc0 } for (int i = 0; i < 3; i++) { 8004de8: 2300 movs r3, #0 8004dea: 67fb str r3, [r7, #124] @ 0x7c 8004dec: e00d b.n 8004e0a WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentPeak[i], sizeof (float)); 8004dee: 6ffb ldr r3, [r7, #124] @ 0x7c 8004df0: 3308 adds r3, #8 8004df2: 009b lsls r3, r3, #2 8004df4: 4a75 ldr r2, [pc, #468] @ (8004fcc ) 8004df6: 4413 add r3, r2 8004df8: 1d1a adds r2, r3, #4 8004dfa: 2304 movs r3, #4 8004dfc: 4971 ldr r1, [pc, #452] @ (8004fc4 ) 8004dfe: 4874 ldr r0, [pc, #464] @ (8004fd0 ) 8004e00: f7fe fb6e bl 80034e0 for (int i = 0; i < 3; i++) { 8004e04: 6ffb ldr r3, [r7, #124] @ 0x7c 8004e06: 3301 adds r3, #1 8004e08: 67fb str r3, [r7, #124] @ 0x7c 8004e0a: 6ffb ldr r3, [r7, #124] @ 0x7c 8004e0c: 2b02 cmp r3, #2 8004e0e: ddee ble.n 8004dee } for (int i = 0; i < 3; i++) { 8004e10: 2300 movs r3, #0 8004e12: 67bb str r3, [r7, #120] @ 0x78 8004e14: e00c b.n 8004e30 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.power[i], sizeof (float)); 8004e16: 6fbb ldr r3, [r7, #120] @ 0x78 8004e18: 330c adds r3, #12 8004e1a: 009b lsls r3, r3, #2 8004e1c: 4a6b ldr r2, [pc, #428] @ (8004fcc ) 8004e1e: 441a add r2, r3 8004e20: 2304 movs r3, #4 8004e22: 4968 ldr r1, [pc, #416] @ (8004fc4 ) 8004e24: 486a ldr r0, [pc, #424] @ (8004fd0 ) 8004e26: f7fe fb5b bl 80034e0 for (int i = 0; i < 3; i++) { 8004e2a: 6fbb ldr r3, [r7, #120] @ 0x78 8004e2c: 3301 adds r3, #1 8004e2e: 67bb str r3, [r7, #120] @ 0x78 8004e30: 6fbb ldr r3, [r7, #120] @ 0x78 8004e32: 2b02 cmp r3, #2 8004e34: ddef ble.n 8004e16 } osMutexRelease (resMeasurementsMutex); 8004e36: 4b64 ldr r3, [pc, #400] @ (8004fc8 ) 8004e38: 681b ldr r3, [r3, #0] 8004e3a: 4618 mov r0, r3 8004e3c: f00e fe06 bl 8013a4c respStatus = spOK; 8004e40: 2300 movs r3, #0 8004e42: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 8004e46: f000 bc7e b.w 8005746 respStatus = spInternalError; 8004e4a: 23fc movs r3, #252 @ 0xfc 8004e4c: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 8004e50: f000 bc79 b.w 8005746 case spGetSensorMeasurments: if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8004e54: 4b5f ldr r3, [pc, #380] @ (8004fd4 ) 8004e56: 681b ldr r3, [r3, #0] 8004e58: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004e5c: 4618 mov r0, r3 8004e5e: f00e fdaa bl 80139b6 8004e62: 4603 mov r3, r0 8004e64: 2b00 cmp r3, #0 8004e66: f040 80e7 bne.w 8005038 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[0], sizeof (float)); 8004e6a: 2304 movs r3, #4 8004e6c: 4a5a ldr r2, [pc, #360] @ (8004fd8 ) 8004e6e: 4955 ldr r1, [pc, #340] @ (8004fc4 ) 8004e70: 4857 ldr r0, [pc, #348] @ (8004fd0 ) 8004e72: f7fe fb35 bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[1], sizeof (float)); 8004e76: 2304 movs r3, #4 8004e78: 4a58 ldr r2, [pc, #352] @ (8004fdc ) 8004e7a: 4952 ldr r1, [pc, #328] @ (8004fc4 ) 8004e7c: 4854 ldr r0, [pc, #336] @ (8004fd0 ) 8004e7e: f7fe fb2f bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.fanVoltage, sizeof (float)); 8004e82: 2304 movs r3, #4 8004e84: 4a56 ldr r2, [pc, #344] @ (8004fe0 ) 8004e86: 494f ldr r1, [pc, #316] @ (8004fc4 ) 8004e88: 4851 ldr r0, [pc, #324] @ (8004fd0 ) 8004e8a: f7fe fb29 bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderX, sizeof (float)); 8004e8e: 2304 movs r3, #4 8004e90: 4a54 ldr r2, [pc, #336] @ (8004fe4 ) 8004e92: 494c ldr r1, [pc, #304] @ (8004fc4 ) 8004e94: 484e ldr r0, [pc, #312] @ (8004fd0 ) 8004e96: f7fe fb23 bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderY, sizeof (float)); 8004e9a: 2304 movs r3, #4 8004e9c: 4a52 ldr r2, [pc, #328] @ (8004fe8 ) 8004e9e: 4949 ldr r1, [pc, #292] @ (8004fc4 ) 8004ea0: 484b ldr r0, [pc, #300] @ (8004fd0 ) 8004ea2: f7fe fb1d bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXStatus, sizeof (uint8_t)); 8004ea6: 2301 movs r3, #1 8004ea8: 4a50 ldr r2, [pc, #320] @ (8004fec ) 8004eaa: 4946 ldr r1, [pc, #280] @ (8004fc4 ) 8004eac: 4848 ldr r0, [pc, #288] @ (8004fd0 ) 8004eae: f7fe fb17 bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYStatus, sizeof (uint8_t)); 8004eb2: 2301 movs r3, #1 8004eb4: 4a4e ldr r2, [pc, #312] @ (8004ff0 ) 8004eb6: 4943 ldr r1, [pc, #268] @ (8004fc4 ) 8004eb8: 4845 ldr r0, [pc, #276] @ (8004fd0 ) 8004eba: f7fe fb11 bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXAveCurrent, sizeof (float)); 8004ebe: 2304 movs r3, #4 8004ec0: 4a4c ldr r2, [pc, #304] @ (8004ff4 ) 8004ec2: 4940 ldr r1, [pc, #256] @ (8004fc4 ) 8004ec4: 4842 ldr r0, [pc, #264] @ (8004fd0 ) 8004ec6: f7fe fb0b bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYAveCurrent, sizeof (float)); 8004eca: 2304 movs r3, #4 8004ecc: 4a4a ldr r2, [pc, #296] @ (8004ff8 ) 8004ece: 493d ldr r1, [pc, #244] @ (8004fc4 ) 8004ed0: 483f ldr r0, [pc, #252] @ (8004fd0 ) 8004ed2: f7fe fb05 bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXPeakCurrent, sizeof (float)); 8004ed6: 2304 movs r3, #4 8004ed8: 4a48 ldr r2, [pc, #288] @ (8004ffc ) 8004eda: 493a ldr r1, [pc, #232] @ (8004fc4 ) 8004edc: 483c ldr r0, [pc, #240] @ (8004fd0 ) 8004ede: f7fe faff bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYPeakCurrent, sizeof (float)); 8004ee2: 2304 movs r3, #4 8004ee4: 4a46 ldr r2, [pc, #280] @ (8005000 ) 8004ee6: 4937 ldr r1, [pc, #220] @ (8004fc4 ) 8004ee8: 4839 ldr r0, [pc, #228] @ (8004fd0 ) 8004eea: f7fe faf9 bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchUp, sizeof (uint8_t)); 8004eee: 2301 movs r3, #1 8004ef0: 4a44 ldr r2, [pc, #272] @ (8005004 ) 8004ef2: 4934 ldr r1, [pc, #208] @ (8004fc4 ) 8004ef4: 4836 ldr r0, [pc, #216] @ (8004fd0 ) 8004ef6: f7fe faf3 bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchDown, sizeof (uint8_t)); 8004efa: 2301 movs r3, #1 8004efc: 4a42 ldr r2, [pc, #264] @ (8005008 ) 8004efe: 4931 ldr r1, [pc, #196] @ (8004fc4 ) 8004f00: 4833 ldr r0, [pc, #204] @ (8004fd0 ) 8004f02: f7fe faed bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchCenter, sizeof (uint8_t)); 8004f06: 2301 movs r3, #1 8004f08: 4a40 ldr r2, [pc, #256] @ (800500c ) 8004f0a: 492e ldr r1, [pc, #184] @ (8004fc4 ) 8004f0c: 4830 ldr r0, [pc, #192] @ (8004fd0 ) 8004f0e: f7fe fae7 bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchUp, sizeof (uint8_t)); 8004f12: 2301 movs r3, #1 8004f14: 4a3e ldr r2, [pc, #248] @ (8005010 ) 8004f16: 492b ldr r1, [pc, #172] @ (8004fc4 ) 8004f18: 482d ldr r0, [pc, #180] @ (8004fd0 ) 8004f1a: f7fe fae1 bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchDown, sizeof (uint8_t)); 8004f1e: 2301 movs r3, #1 8004f20: 4a3c ldr r2, [pc, #240] @ (8005014 ) 8004f22: 4928 ldr r1, [pc, #160] @ (8004fc4 ) 8004f24: 482a ldr r0, [pc, #168] @ (8004fd0 ) 8004f26: f7fe fadb bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchCenter, sizeof (uint8_t)); 8004f2a: 2301 movs r3, #1 8004f2c: 4a3a ldr r2, [pc, #232] @ (8005018 ) 8004f2e: 4925 ldr r1, [pc, #148] @ (8004fc4 ) 8004f30: 4827 ldr r0, [pc, #156] @ (8004fd0 ) 8004f32: f7fe fad5 bl 80034e0 uint8_t comparatorOutput = HAL_COMP_GetOutputLevel (&hcomp1) == COMP_OUTPUT_LEVEL_HIGH ? 1 : 0; 8004f36: 4839 ldr r0, [pc, #228] @ (800501c ) 8004f38: f002 fb72 bl 8007620 8004f3c: 4603 mov r3, r0 8004f3e: 2b01 cmp r3, #1 8004f40: bf0c ite eq 8004f42: 2301 moveq r3, #1 8004f44: 2300 movne r3, #0 8004f46: b2db uxtb r3, r3 8004f48: f887 3057 strb.w r3, [r7, #87] @ 0x57 sensorsInfo.powerSupplyFailMask = ~((comparatorOutput << 1) | HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_3)) & 0x01; 8004f4c: f897 3057 ldrb.w r3, [r7, #87] @ 0x57 8004f50: 005c lsls r4, r3, #1 8004f52: 2108 movs r1, #8 8004f54: 4832 ldr r0, [pc, #200] @ (8005020 ) 8004f56: f006 f91b bl 800b190 8004f5a: 4603 mov r3, r0 8004f5c: 4323 orrs r3, r4 8004f5e: f003 0301 and.w r3, r3, #1 8004f62: 2b00 cmp r3, #0 8004f64: bf0c ite eq 8004f66: 2301 moveq r3, #1 8004f68: 2300 movne r3, #0 8004f6a: b2db uxtb r3, r3 8004f6c: 461a mov r2, r3 8004f6e: 4b1a ldr r3, [pc, #104] @ (8004fd8 ) 8004f70: f883 202e strb.w r2, [r3, #46] @ 0x2e WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.powerSupplyFailMask, sizeof (uint8_t)); 8004f74: 2301 movs r3, #1 8004f76: 4a2b ldr r2, [pc, #172] @ (8005024 ) 8004f78: 4912 ldr r1, [pc, #72] @ (8004fc4 ) 8004f7a: 4815 ldr r0, [pc, #84] @ (8004fd0 ) 8004f7c: f7fe fab0 bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.currentXPosition, sizeof (float)); 8004f80: 2304 movs r3, #4 8004f82: 4a29 ldr r2, [pc, #164] @ (8005028 ) 8004f84: 490f ldr r1, [pc, #60] @ (8004fc4 ) 8004f86: 4812 ldr r0, [pc, #72] @ (8004fd0 ) 8004f88: f7fe faaa bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.currentYPosition, sizeof (float)); 8004f8c: 2304 movs r3, #4 8004f8e: 4a27 ldr r2, [pc, #156] @ (800502c ) 8004f90: 490c ldr r1, [pc, #48] @ (8004fc4 ) 8004f92: 480f ldr r0, [pc, #60] @ (8004fd0 ) 8004f94: f7fe faa4 bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.positionXWeak, sizeof (uint8_t)); 8004f98: 2301 movs r3, #1 8004f9a: 4a25 ldr r2, [pc, #148] @ (8005030 ) 8004f9c: 4909 ldr r1, [pc, #36] @ (8004fc4 ) 8004f9e: 480c ldr r0, [pc, #48] @ (8004fd0 ) 8004fa0: f7fe fa9e bl 80034e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.positionYWeak, sizeof (uint8_t)); 8004fa4: 2301 movs r3, #1 8004fa6: 4a23 ldr r2, [pc, #140] @ (8005034 ) 8004fa8: 4906 ldr r1, [pc, #24] @ (8004fc4 ) 8004faa: 4809 ldr r0, [pc, #36] @ (8004fd0 ) 8004fac: f7fe fa98 bl 80034e0 osMutexRelease (sensorsInfoMutex); 8004fb0: 4b08 ldr r3, [pc, #32] @ (8004fd4 ) 8004fb2: 681b ldr r3, [r3, #0] 8004fb4: 4618 mov r0, r3 8004fb6: f00e fd49 bl 8013a4c respStatus = spOK; 8004fba: 2300 movs r3, #0 8004fbc: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 8004fc0: e3c1 b.n 8005746 8004fc2: bf00 nop 8004fc4: 240011b8 .word 0x240011b8 8004fc8: 240008d8 .word 0x240008d8 8004fcc: 24000900 .word 0x24000900 8004fd0: 24001138 .word 0x24001138 8004fd4: 240008dc .word 0x240008dc 8004fd8: 24000940 .word 0x24000940 8004fdc: 24000944 .word 0x24000944 8004fe0: 24000948 .word 0x24000948 8004fe4: 2400094c .word 0x2400094c 8004fe8: 24000950 .word 0x24000950 8004fec: 24000954 .word 0x24000954 8004ff0: 24000955 .word 0x24000955 8004ff4: 24000958 .word 0x24000958 8004ff8: 2400095c .word 0x2400095c 8004ffc: 24000960 .word 0x24000960 8005000: 24000964 .word 0x24000964 8005004: 24000968 .word 0x24000968 8005008: 24000969 .word 0x24000969 800500c: 2400096a .word 0x2400096a 8005010: 2400096b .word 0x2400096b 8005014: 2400096c .word 0x2400096c 8005018: 2400096d .word 0x2400096d 800501c: 24000514 .word 0x24000514 8005020: 58020c00 .word 0x58020c00 8005024: 2400096e .word 0x2400096e 8005028: 24000970 .word 0x24000970 800502c: 24000974 .word 0x24000974 8005030: 24000978 .word 0x24000978 8005034: 24000979 .word 0x24000979 respStatus = spInternalError; 8005038: 23fc movs r3, #252 @ 0xfc 800503a: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 800503e: e382 b.n 8005746 case spSetFanSpeed: osTimerStop (fanTimerHandle); 8005040: 4bb4 ldr r3, [pc, #720] @ (8005314 ) 8005042: 681b ldr r3, [r3, #0] 8005044: 4618 mov r0, r3 8005046: f00e fbf9 bl 801383c int32_t fanTimerPeriod = 0; 800504a: 2300 movs r3, #0 800504c: 653b str r3, [r7, #80] @ 0x50 uint32_t pulse = 0; 800504e: 2300 movs r3, #0 8005050: 64fb str r3, [r7, #76] @ 0x4c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse); 8005052: 683b ldr r3, [r7, #0] 8005054: 330c adds r3, #12 8005056: f107 024c add.w r2, r7, #76 @ 0x4c 800505a: f107 0154 add.w r1, r7, #84 @ 0x54 800505e: 4618 mov r0, r3 8005060: f7fe faa4 bl 80035ac ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&fanTimerPeriod); 8005064: 683b ldr r3, [r7, #0] 8005066: 330c adds r3, #12 8005068: f107 0250 add.w r2, r7, #80 @ 0x50 800506c: f107 0154 add.w r1, r7, #84 @ 0x54 8005070: 4618 mov r0, r3 8005072: f7fe fa9b bl 80035ac fanTimerConfigOC.Pulse = pulse * 10; 8005076: 6cfa ldr r2, [r7, #76] @ 0x4c 8005078: 4613 mov r3, r2 800507a: 009b lsls r3, r3, #2 800507c: 4413 add r3, r2 800507e: 005b lsls r3, r3, #1 8005080: 461a mov r2, r3 8005082: 4ba5 ldr r3, [pc, #660] @ (8005318 ) 8005084: 605a str r2, [r3, #4] if (HAL_TIM_PWM_ConfigChannel (&htim1, &fanTimerConfigOC, TIM_CHANNEL_2) != HAL_OK) { 8005086: 2204 movs r2, #4 8005088: 49a3 ldr r1, [pc, #652] @ (8005318 ) 800508a: 48a4 ldr r0, [pc, #656] @ (800531c ) 800508c: f00a fc3e bl 800f90c 8005090: 4603 mov r3, r0 8005092: 2b00 cmp r3, #0 8005094: d001 beq.n 800509a Error_Handler (); 8005096: f7fc fd79 bl 8001b8c } if (fanTimerPeriod > 0) { 800509a: 6d3b ldr r3, [r7, #80] @ 0x50 800509c: 2b00 cmp r3, #0 800509e: dd0f ble.n 80050c0 osTimerStart (fanTimerHandle, fanTimerPeriod * 1000); 80050a0: 4b9c ldr r3, [pc, #624] @ (8005314 ) 80050a2: 681a ldr r2, [r3, #0] 80050a4: 6d3b ldr r3, [r7, #80] @ 0x50 80050a6: f44f 717a mov.w r1, #1000 @ 0x3e8 80050aa: fb01 f303 mul.w r3, r1, r3 80050ae: 4619 mov r1, r3 80050b0: 4610 mov r0, r2 80050b2: f00e fb95 bl 80137e0 HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 80050b6: 2104 movs r1, #4 80050b8: 4898 ldr r0, [pc, #608] @ (800531c ) 80050ba: f00a f97b bl 800f3b4 80050be: e019 b.n 80050f4 } else if (fanTimerPeriod == 0) { 80050c0: 6d3b ldr r3, [r7, #80] @ 0x50 80050c2: 2b00 cmp r3, #0 80050c4: d109 bne.n 80050da osTimerStop (fanTimerHandle); 80050c6: 4b93 ldr r3, [pc, #588] @ (8005314 ) 80050c8: 681b ldr r3, [r3, #0] 80050ca: 4618 mov r0, r3 80050cc: f00e fbb6 bl 801383c HAL_TIM_PWM_Stop (&htim1, TIM_CHANNEL_2); 80050d0: 2104 movs r1, #4 80050d2: 4892 ldr r0, [pc, #584] @ (800531c ) 80050d4: f00a fa7c bl 800f5d0 80050d8: e00c b.n 80050f4 } else if (fanTimerPeriod == -1) { 80050da: 6d3b ldr r3, [r7, #80] @ 0x50 80050dc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80050e0: d108 bne.n 80050f4 osTimerStop (fanTimerHandle); 80050e2: 4b8c ldr r3, [pc, #560] @ (8005314 ) 80050e4: 681b ldr r3, [r3, #0] 80050e6: 4618 mov r0, r3 80050e8: f00e fba8 bl 801383c HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 80050ec: 2104 movs r1, #4 80050ee: 488b ldr r0, [pc, #556] @ (800531c ) 80050f0: f00a f960 bl 800f3b4 } respStatus = spOK; 80050f4: 2300 movs r3, #0 80050f6: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 80050fa: e324 b.n 8005746 case spSetMotorXOn: int32_t motorXPWMPulse = 0; 80050fc: 2300 movs r3, #0 80050fe: 64bb str r3, [r7, #72] @ 0x48 int32_t motorXTimerPeriod = 0; 8005100: 2300 movs r3, #0 8005102: 647b str r3, [r7, #68] @ 0x44 uint32_t motorXStatus = 0; 8005104: 2300 movs r3, #0 8005106: 65bb str r3, [r7, #88] @ 0x58 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXPWMPulse); 8005108: 683b ldr r3, [r7, #0] 800510a: 330c adds r3, #12 800510c: f107 0248 add.w r2, r7, #72 @ 0x48 8005110: f107 0154 add.w r1, r7, #84 @ 0x54 8005114: 4618 mov r0, r3 8005116: f7fe fa49 bl 80035ac ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXTimerPeriod); 800511a: 683b ldr r3, [r7, #0] 800511c: 330c adds r3, #12 800511e: f107 0244 add.w r2, r7, #68 @ 0x44 8005122: f107 0154 add.w r1, r7, #84 @ 0x54 8005126: 4618 mov r0, r3 8005128: f7fe fa40 bl 80035ac if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800512c: 4b7c ldr r3, [pc, #496] @ (8005320 ) 800512e: 681b ldr r3, [r3, #0] 8005130: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005134: 4618 mov r0, r3 8005136: f00e fc3e bl 80139b6 800513a: 4603 mov r3, r0 800513c: 2b00 cmp r3, #0 800513e: d12a bne.n 8005196 motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, motorXPWMPulse, motorXTimerPeriod, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 8005140: 4b78 ldr r3, [pc, #480] @ (8005324 ) 8005142: 681b ldr r3, [r3, #0] 8005144: 6cba ldr r2, [r7, #72] @ 0x48 8005146: 6c79 ldr r1, [r7, #68] @ 0x44 8005148: 4877 ldr r0, [pc, #476] @ (8005328 ) 800514a: f890 0028 ldrb.w r0, [r0, #40] @ 0x28 800514e: 4c76 ldr r4, [pc, #472] @ (8005328 ) 8005150: f894 4029 ldrb.w r4, [r4, #41] @ 0x29 8005154: 9404 str r4, [sp, #16] 8005156: 9003 str r0, [sp, #12] 8005158: 9102 str r1, [sp, #8] 800515a: 9201 str r2, [sp, #4] 800515c: 9300 str r3, [sp, #0] 800515e: 2304 movs r3, #4 8005160: 2200 movs r2, #0 8005162: 4972 ldr r1, [pc, #456] @ (800532c ) 8005164: 4872 ldr r0, [pc, #456] @ (8005330 ) 8005166: f7fd fcf5 bl 8002b54 800516a: 4603 mov r3, r0 motorXStatus = 800516c: 65bb str r3, [r7, #88] @ 0x58 sensorsInfo.motorXStatus = motorXStatus; 800516e: 6dbb ldr r3, [r7, #88] @ 0x58 8005170: b2da uxtb r2, r3 8005172: 4b6d ldr r3, [pc, #436] @ (8005328 ) 8005174: 751a strb r2, [r3, #20] if (motorXStatus == 1) { 8005176: 6dbb ldr r3, [r7, #88] @ 0x58 8005178: 2b01 cmp r3, #1 800517a: d103 bne.n 8005184 sensorsInfo.motorXPeakCurrent = 0.0; 800517c: 4b6a ldr r3, [pc, #424] @ (8005328 ) 800517e: f04f 0200 mov.w r2, #0 8005182: 621a str r2, [r3, #32] } osMutexRelease (sensorsInfoMutex); 8005184: 4b66 ldr r3, [pc, #408] @ (8005320 ) 8005186: 681b ldr r3, [r3, #0] 8005188: 4618 mov r0, r3 800518a: f00e fc5f bl 8013a4c respStatus = spOK; 800518e: 2300 movs r3, #0 8005190: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 8005194: e2d7 b.n 8005746 respStatus = spInternalError; 8005196: 23fc movs r3, #252 @ 0xfc 8005198: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 800519c: e2d3 b.n 8005746 case spSetMotorYOn: int32_t motorYPWMPulse = 0; 800519e: 2300 movs r3, #0 80051a0: 643b str r3, [r7, #64] @ 0x40 int32_t motorYTimerPeriod = 0; 80051a2: 2300 movs r3, #0 80051a4: 63fb str r3, [r7, #60] @ 0x3c uint32_t motorYStatus = 0; 80051a6: 2300 movs r3, #0 80051a8: 65fb str r3, [r7, #92] @ 0x5c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYPWMPulse); 80051aa: 683b ldr r3, [r7, #0] 80051ac: 330c adds r3, #12 80051ae: f107 0240 add.w r2, r7, #64 @ 0x40 80051b2: f107 0154 add.w r1, r7, #84 @ 0x54 80051b6: 4618 mov r0, r3 80051b8: f7fe f9f8 bl 80035ac ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYTimerPeriod); 80051bc: 683b ldr r3, [r7, #0] 80051be: 330c adds r3, #12 80051c0: f107 023c add.w r2, r7, #60 @ 0x3c 80051c4: f107 0154 add.w r1, r7, #84 @ 0x54 80051c8: 4618 mov r0, r3 80051ca: f7fe f9ef bl 80035ac if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80051ce: 4b54 ldr r3, [pc, #336] @ (8005320 ) 80051d0: 681b ldr r3, [r3, #0] 80051d2: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80051d6: 4618 mov r0, r3 80051d8: f00e fbed bl 80139b6 80051dc: 4603 mov r3, r0 80051de: 2b00 cmp r3, #0 80051e0: d12a bne.n 8005238 motorYStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, motorYPWMPulse, motorYTimerPeriod, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 80051e2: 4b54 ldr r3, [pc, #336] @ (8005334 ) 80051e4: 681b ldr r3, [r3, #0] 80051e6: 6c3a ldr r2, [r7, #64] @ 0x40 80051e8: 6bf9 ldr r1, [r7, #60] @ 0x3c 80051ea: 484f ldr r0, [pc, #316] @ (8005328 ) 80051ec: f890 002b ldrb.w r0, [r0, #43] @ 0x2b 80051f0: 4c4d ldr r4, [pc, #308] @ (8005328 ) 80051f2: f894 402c ldrb.w r4, [r4, #44] @ 0x2c 80051f6: 9404 str r4, [sp, #16] 80051f8: 9003 str r0, [sp, #12] 80051fa: 9102 str r1, [sp, #8] 80051fc: 9201 str r2, [sp, #4] 80051fe: 9300 str r3, [sp, #0] 8005200: 230c movs r3, #12 8005202: 2208 movs r2, #8 8005204: 4949 ldr r1, [pc, #292] @ (800532c ) 8005206: 484a ldr r0, [pc, #296] @ (8005330 ) 8005208: f7fd fca4 bl 8002b54 800520c: 4603 mov r3, r0 motorYStatus = 800520e: 65fb str r3, [r7, #92] @ 0x5c sensorsInfo.motorYStatus = motorYStatus; 8005210: 6dfb ldr r3, [r7, #92] @ 0x5c 8005212: b2da uxtb r2, r3 8005214: 4b44 ldr r3, [pc, #272] @ (8005328 ) 8005216: 755a strb r2, [r3, #21] if (motorYStatus == 1) { 8005218: 6dfb ldr r3, [r7, #92] @ 0x5c 800521a: 2b01 cmp r3, #1 800521c: d103 bne.n 8005226 sensorsInfo.motorYPeakCurrent = 0.0; 800521e: 4b42 ldr r3, [pc, #264] @ (8005328 ) 8005220: f04f 0200 mov.w r2, #0 8005224: 625a str r2, [r3, #36] @ 0x24 } osMutexRelease (sensorsInfoMutex); 8005226: 4b3e ldr r3, [pc, #248] @ (8005320 ) 8005228: 681b ldr r3, [r3, #0] 800522a: 4618 mov r0, r3 800522c: f00e fc0e bl 8013a4c respStatus = spOK; 8005230: 2300 movs r3, #0 8005232: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 8005236: e286 b.n 8005746 respStatus = spInternalError; 8005238: 23fc movs r3, #252 @ 0xfc 800523a: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 800523e: e282 b.n 8005746 case spSetDiodeOn: osTimerStop (debugLedTimerHandle); 8005240: 4b3d ldr r3, [pc, #244] @ (8005338 ) 8005242: 681b ldr r3, [r3, #0] 8005244: 4618 mov r0, r3 8005246: f00e faf9 bl 801383c int32_t dbgLedTimerPeriod = 0; 800524a: 2300 movs r3, #0 800524c: 63bb str r3, [r7, #56] @ 0x38 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&dbgLedTimerPeriod); 800524e: 683b ldr r3, [r7, #0] 8005250: 330c adds r3, #12 8005252: f107 0238 add.w r2, r7, #56 @ 0x38 8005256: f107 0154 add.w r1, r7, #84 @ 0x54 800525a: 4618 mov r0, r3 800525c: f7fe f9a6 bl 80035ac if (dbgLedTimerPeriod > 0) { 8005260: 6bbb ldr r3, [r7, #56] @ 0x38 8005262: 2b00 cmp r3, #0 8005264: dd0e ble.n 8005284 osTimerStart (debugLedTimerHandle, dbgLedTimerPeriod * 1000); 8005266: 4b34 ldr r3, [pc, #208] @ (8005338 ) 8005268: 681a ldr r2, [r3, #0] 800526a: 6bbb ldr r3, [r7, #56] @ 0x38 800526c: f44f 717a mov.w r1, #1000 @ 0x3e8 8005270: fb01 f303 mul.w r3, r1, r3 8005274: 4619 mov r1, r3 8005276: 4610 mov r0, r2 8005278: f00e fab2 bl 80137e0 DbgLEDOn (DBG_LED1); 800527c: 2010 movs r0, #16 800527e: f7fd fbdb bl 8002a38 8005282: e017 b.n 80052b4 } else if (dbgLedTimerPeriod == 0) { 8005284: 6bbb ldr r3, [r7, #56] @ 0x38 8005286: 2b00 cmp r3, #0 8005288: d108 bne.n 800529c osTimerStop (debugLedTimerHandle); 800528a: 4b2b ldr r3, [pc, #172] @ (8005338 ) 800528c: 681b ldr r3, [r3, #0] 800528e: 4618 mov r0, r3 8005290: f00e fad4 bl 801383c DbgLEDOff (DBG_LED1); 8005294: 2010 movs r0, #16 8005296: f7fd fbe1 bl 8002a5c 800529a: e00b b.n 80052b4 } else if (dbgLedTimerPeriod == -1) { 800529c: 6bbb ldr r3, [r7, #56] @ 0x38 800529e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80052a2: d107 bne.n 80052b4 osTimerStop (debugLedTimerHandle); 80052a4: 4b24 ldr r3, [pc, #144] @ (8005338 ) 80052a6: 681b ldr r3, [r3, #0] 80052a8: 4618 mov r0, r3 80052aa: f00e fac7 bl 801383c DbgLEDOn (DBG_LED1); 80052ae: 2010 movs r0, #16 80052b0: f7fd fbc2 bl 8002a38 } respStatus = spOK; 80052b4: 2300 movs r3, #0 80052b6: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 80052ba: e244 b.n 8005746 case spSetmotorXMaxCurrent: float motorXMaxCurrent = 0; 80052bc: f04f 0300 mov.w r3, #0 80052c0: 637b str r3, [r7, #52] @ 0x34 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXMaxCurrent); 80052c2: 683b ldr r3, [r7, #0] 80052c4: 330c adds r3, #12 80052c6: f107 0234 add.w r2, r7, #52 @ 0x34 80052ca: f107 0154 add.w r1, r7, #84 @ 0x54 80052ce: 4618 mov r0, r3 80052d0: f7fe f96c bl 80035ac uint32_t dacDataCh1 = (uint32_t)(4095 * motorXMaxCurrent / (EXT_VREF_mV * 0.001)); 80052d4: edd7 7a0d vldr s15, [r7, #52] @ 0x34 80052d8: ed9f 7a19 vldr s14, [pc, #100] @ 8005340 80052dc: ee67 7a87 vmul.f32 s15, s15, s14 80052e0: eeb7 6ae7 vcvt.f64.f32 d6, s15 80052e4: eeb0 5b08 vmov.f64 d5, #8 @ 0x40400000 3.0 80052e8: ee86 7b05 vdiv.f64 d7, d6, d5 80052ec: eefc 7bc7 vcvt.u32.f64 s15, d7 80052f0: ee17 3a90 vmov r3, s15 80052f4: 663b str r3, [r7, #96] @ 0x60 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, dacDataCh1); 80052f6: 6e3b ldr r3, [r7, #96] @ 0x60 80052f8: 2200 movs r2, #0 80052fa: 2100 movs r1, #0 80052fc: 480f ldr r0, [pc, #60] @ (800533c ) 80052fe: f002 fdda bl 8007eb6 HAL_DAC_Start (&hdac1, DAC_CHANNEL_1); 8005302: 2100 movs r1, #0 8005304: 480d ldr r0, [pc, #52] @ (800533c ) 8005306: f002 fd29 bl 8007d5c respStatus = spOK; 800530a: 2300 movs r3, #0 800530c: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 8005310: e219 b.n 8005746 8005312: bf00 nop 8005314: 240007dc .word 0x240007dc 8005318: 2400086c .word 0x2400086c 800531c: 2400059c .word 0x2400059c 8005320: 240008dc .word 0x240008dc 8005324: 2400080c .word 0x2400080c 8005328: 24000940 .word 0x24000940 800532c: 24000888 .word 0x24000888 8005330: 240005e8 .word 0x240005e8 8005334: 2400083c .word 0x2400083c 8005338: 240007ac .word 0x240007ac 800533c: 24000564 .word 0x24000564 8005340: 457ff000 .word 0x457ff000 case spSetmotorYMaxCurrent: float motorYMaxCurrent = 0; 8005344: f04f 0300 mov.w r3, #0 8005348: 633b str r3, [r7, #48] @ 0x30 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYMaxCurrent); 800534a: 683b ldr r3, [r7, #0] 800534c: 330c adds r3, #12 800534e: f107 0230 add.w r2, r7, #48 @ 0x30 8005352: f107 0154 add.w r1, r7, #84 @ 0x54 8005356: 4618 mov r0, r3 8005358: f7fe f928 bl 80035ac uint32_t dacDataCh2 = (uint32_t)(4095 * motorYMaxCurrent / (EXT_VREF_mV * 0.001)); 800535c: edd7 7a0c vldr s15, [r7, #48] @ 0x30 8005360: ed1f 7a09 vldr s14, [pc, #-36] @ 8005340 8005364: ee67 7a87 vmul.f32 s15, s15, s14 8005368: eeb7 6ae7 vcvt.f64.f32 d6, s15 800536c: eeb0 5b08 vmov.f64 d5, #8 @ 0x40400000 3.0 8005370: ee86 7b05 vdiv.f64 d7, d6, d5 8005374: eefc 7bc7 vcvt.u32.f64 s15, d7 8005378: ee17 3a90 vmov r3, s15 800537c: 667b str r3, [r7, #100] @ 0x64 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, dacDataCh2); 800537e: 6e7b ldr r3, [r7, #100] @ 0x64 8005380: 2200 movs r2, #0 8005382: 2110 movs r1, #16 8005384: 48b9 ldr r0, [pc, #740] @ (800566c ) 8005386: f002 fd96 bl 8007eb6 HAL_DAC_Start (&hdac1, DAC_CHANNEL_2); 800538a: 2110 movs r1, #16 800538c: 48b7 ldr r0, [pc, #732] @ (800566c ) 800538e: f002 fce5 bl 8007d5c respStatus = spOK; 8005392: 2300 movs r3, #0 8005394: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 8005398: e1d5 b.n 8005746 case spClearPeakMeasurments: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 800539a: 4bb5 ldr r3, [pc, #724] @ (8005670 ) 800539c: 681b ldr r3, [r3, #0] 800539e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80053a2: 4618 mov r0, r3 80053a4: f00e fb07 bl 80139b6 80053a8: 4603 mov r3, r0 80053aa: 2b00 cmp r3, #0 80053ac: d12a bne.n 8005404 for (int i = 0; i < 3; i++) { 80053ae: 2300 movs r3, #0 80053b0: 677b str r3, [r7, #116] @ 0x74 80053b2: e01b b.n 80053ec resMeasurements.voltagePeak[i] = resMeasurements.voltageRMS[i]; 80053b4: 4aaf ldr r2, [pc, #700] @ (8005674 ) 80053b6: 6f7b ldr r3, [r7, #116] @ 0x74 80053b8: 009b lsls r3, r3, #2 80053ba: 4413 add r3, r2 80053bc: 681a ldr r2, [r3, #0] 80053be: 49ad ldr r1, [pc, #692] @ (8005674 ) 80053c0: 6f7b ldr r3, [r7, #116] @ 0x74 80053c2: 3302 adds r3, #2 80053c4: 009b lsls r3, r3, #2 80053c6: 440b add r3, r1 80053c8: 3304 adds r3, #4 80053ca: 601a str r2, [r3, #0] resMeasurements.currentPeak[i] = resMeasurements.currentRMS[i]; 80053cc: 4aa9 ldr r2, [pc, #676] @ (8005674 ) 80053ce: 6f7b ldr r3, [r7, #116] @ 0x74 80053d0: 3306 adds r3, #6 80053d2: 009b lsls r3, r3, #2 80053d4: 4413 add r3, r2 80053d6: 681a ldr r2, [r3, #0] 80053d8: 49a6 ldr r1, [pc, #664] @ (8005674 ) 80053da: 6f7b ldr r3, [r7, #116] @ 0x74 80053dc: 3308 adds r3, #8 80053de: 009b lsls r3, r3, #2 80053e0: 440b add r3, r1 80053e2: 3304 adds r3, #4 80053e4: 601a str r2, [r3, #0] for (int i = 0; i < 3; i++) { 80053e6: 6f7b ldr r3, [r7, #116] @ 0x74 80053e8: 3301 adds r3, #1 80053ea: 677b str r3, [r7, #116] @ 0x74 80053ec: 6f7b ldr r3, [r7, #116] @ 0x74 80053ee: 2b02 cmp r3, #2 80053f0: dde0 ble.n 80053b4 } osMutexRelease (resMeasurementsMutex); 80053f2: 4b9f ldr r3, [pc, #636] @ (8005670 ) 80053f4: 681b ldr r3, [r3, #0] 80053f6: 4618 mov r0, r3 80053f8: f00e fb28 bl 8013a4c respStatus = spOK; 80053fc: 2300 movs r3, #0 80053fe: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 8005402: e1a0 b.n 8005746 respStatus = spInternalError; 8005404: 23fc movs r3, #252 @ 0xfc 8005406: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 800540a: e19c b.n 8005746 case spSetEncoderXValue: float enocoderXValue = 0; 800540c: f04f 0300 mov.w r3, #0 8005410: 62fb str r3, [r7, #44] @ 0x2c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderXValue); 8005412: 683b ldr r3, [r7, #0] 8005414: 330c adds r3, #12 8005416: f107 022c add.w r2, r7, #44 @ 0x2c 800541a: f107 0154 add.w r1, r7, #84 @ 0x54 800541e: 4618 mov r0, r3 8005420: f7fe f8c4 bl 80035ac if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8005424: 4b94 ldr r3, [pc, #592] @ (8005678 ) 8005426: 681b ldr r3, [r3, #0] 8005428: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800542c: 4618 mov r0, r3 800542e: f00e fac2 bl 80139b6 8005432: 4603 mov r3, r0 8005434: 2b00 cmp r3, #0 8005436: d118 bne.n 800546a sensorsInfo.pvEncoderX = enocoderXValue; 8005438: 6afb ldr r3, [r7, #44] @ 0x2c 800543a: 4a90 ldr r2, [pc, #576] @ (800567c ) 800543c: 60d3 str r3, [r2, #12] sensorsInfo.currentXPosition = 100 * enocoderXValue / MAX_X_AXE_ANGLE; 800543e: edd7 7a0b vldr s15, [r7, #44] @ 0x2c 8005442: ed9f 7a8f vldr s14, [pc, #572] @ 8005680 8005446: ee27 7a87 vmul.f32 s14, s15, s14 800544a: eddf 6a8e vldr s13, [pc, #568] @ 8005684 800544e: eec7 7a26 vdiv.f32 s15, s14, s13 8005452: 4b8a ldr r3, [pc, #552] @ (800567c ) 8005454: edc3 7a0c vstr s15, [r3, #48] @ 0x30 osMutexRelease (sensorsInfoMutex); 8005458: 4b87 ldr r3, [pc, #540] @ (8005678 ) 800545a: 681b ldr r3, [r3, #0] 800545c: 4618 mov r0, r3 800545e: f00e faf5 bl 8013a4c respStatus = spOK; 8005462: 2300 movs r3, #0 8005464: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 8005468: e16d b.n 8005746 respStatus = spInternalError; 800546a: 23fc movs r3, #252 @ 0xfc 800546c: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 8005470: e169 b.n 8005746 case spSetEncoderYValue: float enocoderYValue = 0; 8005472: f04f 0300 mov.w r3, #0 8005476: 62bb str r3, [r7, #40] @ 0x28 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderYValue); 8005478: 683b ldr r3, [r7, #0] 800547a: 330c adds r3, #12 800547c: f107 0228 add.w r2, r7, #40 @ 0x28 8005480: f107 0154 add.w r1, r7, #84 @ 0x54 8005484: 4618 mov r0, r3 8005486: f7fe f891 bl 80035ac if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800548a: 4b7b ldr r3, [pc, #492] @ (8005678 ) 800548c: 681b ldr r3, [r3, #0] 800548e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005492: 4618 mov r0, r3 8005494: f00e fa8f bl 80139b6 8005498: 4603 mov r3, r0 800549a: 2b00 cmp r3, #0 800549c: d118 bne.n 80054d0 sensorsInfo.pvEncoderY = enocoderYValue; 800549e: 6abb ldr r3, [r7, #40] @ 0x28 80054a0: 4a76 ldr r2, [pc, #472] @ (800567c ) 80054a2: 6113 str r3, [r2, #16] sensorsInfo.currentYPosition = 100 * enocoderYValue / MAX_X_AXE_ANGLE; 80054a4: edd7 7a0a vldr s15, [r7, #40] @ 0x28 80054a8: ed9f 7a75 vldr s14, [pc, #468] @ 8005680 80054ac: ee27 7a87 vmul.f32 s14, s15, s14 80054b0: eddf 6a74 vldr s13, [pc, #464] @ 8005684 80054b4: eec7 7a26 vdiv.f32 s15, s14, s13 80054b8: 4b70 ldr r3, [pc, #448] @ (800567c ) 80054ba: edc3 7a0d vstr s15, [r3, #52] @ 0x34 osMutexRelease (sensorsInfoMutex); 80054be: 4b6e ldr r3, [pc, #440] @ (8005678 ) 80054c0: 681b ldr r3, [r3, #0] 80054c2: 4618 mov r0, r3 80054c4: f00e fac2 bl 8013a4c respStatus = spOK; 80054c8: 2300 movs r3, #0 80054ca: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 80054ce: e13a b.n 8005746 respStatus = spInternalError; 80054d0: 23fc movs r3, #252 @ 0xfc 80054d2: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 80054d6: e136 b.n 8005746 case spSetVoltageMeasGains: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 80054d8: 4b65 ldr r3, [pc, #404] @ (8005670 ) 80054da: 681b ldr r3, [r3, #0] 80054dc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80054e0: 4618 mov r0, r3 80054e2: f00e fa68 bl 80139b6 80054e6: 4603 mov r3, r0 80054e8: 2b00 cmp r3, #0 80054ea: d122 bne.n 8005532 for (uint8_t i = 0; i < 3; i++) { 80054ec: 2300 movs r3, #0 80054ee: f887 3073 strb.w r3, [r7, #115] @ 0x73 80054f2: e011 b.n 8005518 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].gain); 80054f4: 683b ldr r3, [r7, #0] 80054f6: f103 000c add.w r0, r3, #12 80054fa: f897 3073 ldrb.w r3, [r7, #115] @ 0x73 80054fe: 00db lsls r3, r3, #3 8005500: 4a61 ldr r2, [pc, #388] @ (8005688 ) 8005502: 441a add r2, r3 8005504: f107 0354 add.w r3, r7, #84 @ 0x54 8005508: 4619 mov r1, r3 800550a: f7fe f84f bl 80035ac for (uint8_t i = 0; i < 3; i++) { 800550e: f897 3073 ldrb.w r3, [r7, #115] @ 0x73 8005512: 3301 adds r3, #1 8005514: f887 3073 strb.w r3, [r7, #115] @ 0x73 8005518: f897 3073 ldrb.w r3, [r7, #115] @ 0x73 800551c: 2b02 cmp r3, #2 800551e: d9e9 bls.n 80054f4 } osMutexRelease (resMeasurementsMutex); 8005520: 4b53 ldr r3, [pc, #332] @ (8005670 ) 8005522: 681b ldr r3, [r3, #0] 8005524: 4618 mov r0, r3 8005526: f00e fa91 bl 8013a4c respStatus = spOK; 800552a: 2300 movs r3, #0 800552c: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 8005530: e109 b.n 8005746 respStatus = spInternalError; 8005532: 23fc movs r3, #252 @ 0xfc 8005534: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 8005538: e105 b.n 8005746 case spSetVoltageMeasOffsets: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 800553a: 4b4d ldr r3, [pc, #308] @ (8005670 ) 800553c: 681b ldr r3, [r3, #0] 800553e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005542: 4618 mov r0, r3 8005544: f00e fa37 bl 80139b6 8005548: 4603 mov r3, r0 800554a: 2b00 cmp r3, #0 800554c: d123 bne.n 8005596 for (uint8_t i = 0; i < 3; i++) { 800554e: 2300 movs r3, #0 8005550: f887 3072 strb.w r3, [r7, #114] @ 0x72 8005554: e012 b.n 800557c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].offset); 8005556: 683b ldr r3, [r7, #0] 8005558: f103 000c add.w r0, r3, #12 800555c: f897 3072 ldrb.w r3, [r7, #114] @ 0x72 8005560: 00db lsls r3, r3, #3 8005562: 4a49 ldr r2, [pc, #292] @ (8005688 ) 8005564: 4413 add r3, r2 8005566: 1d1a adds r2, r3, #4 8005568: f107 0354 add.w r3, r7, #84 @ 0x54 800556c: 4619 mov r1, r3 800556e: f7fe f81d bl 80035ac for (uint8_t i = 0; i < 3; i++) { 8005572: f897 3072 ldrb.w r3, [r7, #114] @ 0x72 8005576: 3301 adds r3, #1 8005578: f887 3072 strb.w r3, [r7, #114] @ 0x72 800557c: f897 3072 ldrb.w r3, [r7, #114] @ 0x72 8005580: 2b02 cmp r3, #2 8005582: d9e8 bls.n 8005556 } osMutexRelease (resMeasurementsMutex); 8005584: 4b3a ldr r3, [pc, #232] @ (8005670 ) 8005586: 681b ldr r3, [r3, #0] 8005588: 4618 mov r0, r3 800558a: f00e fa5f bl 8013a4c respStatus = spOK; 800558e: 2300 movs r3, #0 8005590: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 8005594: e0d7 b.n 8005746 respStatus = spInternalError; 8005596: 23fc movs r3, #252 @ 0xfc 8005598: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 800559c: e0d3 b.n 8005746 case spSetCurrentMeasGains: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 800559e: 4b34 ldr r3, [pc, #208] @ (8005670 ) 80055a0: 681b ldr r3, [r3, #0] 80055a2: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80055a6: 4618 mov r0, r3 80055a8: f00e fa05 bl 80139b6 80055ac: 4603 mov r3, r0 80055ae: 2b00 cmp r3, #0 80055b0: d122 bne.n 80055f8 for (uint8_t i = 0; i < 3; i++) { 80055b2: 2300 movs r3, #0 80055b4: f887 3071 strb.w r3, [r7, #113] @ 0x71 80055b8: e011 b.n 80055de ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].gain); 80055ba: 683b ldr r3, [r7, #0] 80055bc: f103 000c add.w r0, r3, #12 80055c0: f897 3071 ldrb.w r3, [r7, #113] @ 0x71 80055c4: 00db lsls r3, r3, #3 80055c6: 4a31 ldr r2, [pc, #196] @ (800568c ) 80055c8: 441a add r2, r3 80055ca: f107 0354 add.w r3, r7, #84 @ 0x54 80055ce: 4619 mov r1, r3 80055d0: f7fd ffec bl 80035ac for (uint8_t i = 0; i < 3; i++) { 80055d4: f897 3071 ldrb.w r3, [r7, #113] @ 0x71 80055d8: 3301 adds r3, #1 80055da: f887 3071 strb.w r3, [r7, #113] @ 0x71 80055de: f897 3071 ldrb.w r3, [r7, #113] @ 0x71 80055e2: 2b02 cmp r3, #2 80055e4: d9e9 bls.n 80055ba } osMutexRelease (resMeasurementsMutex); 80055e6: 4b22 ldr r3, [pc, #136] @ (8005670 ) 80055e8: 681b ldr r3, [r3, #0] 80055ea: 4618 mov r0, r3 80055ec: f00e fa2e bl 8013a4c respStatus = spOK; 80055f0: 2300 movs r3, #0 80055f2: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 80055f6: e0a6 b.n 8005746 respStatus = spInternalError; 80055f8: 23fc movs r3, #252 @ 0xfc 80055fa: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 80055fe: e0a2 b.n 8005746 case spSetCurrentMeasOffsets: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005600: 4b1b ldr r3, [pc, #108] @ (8005670 ) 8005602: 681b ldr r3, [r3, #0] 8005604: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005608: 4618 mov r0, r3 800560a: f00e f9d4 bl 80139b6 800560e: 4603 mov r3, r0 8005610: 2b00 cmp r3, #0 8005612: d123 bne.n 800565c for (uint8_t i = 0; i < 3; i++) { 8005614: 2300 movs r3, #0 8005616: f887 3070 strb.w r3, [r7, #112] @ 0x70 800561a: e012 b.n 8005642 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].offset); 800561c: 683b ldr r3, [r7, #0] 800561e: f103 000c add.w r0, r3, #12 8005622: f897 3070 ldrb.w r3, [r7, #112] @ 0x70 8005626: 00db lsls r3, r3, #3 8005628: 4a18 ldr r2, [pc, #96] @ (800568c ) 800562a: 4413 add r3, r2 800562c: 1d1a adds r2, r3, #4 800562e: f107 0354 add.w r3, r7, #84 @ 0x54 8005632: 4619 mov r1, r3 8005634: f7fd ffba bl 80035ac for (uint8_t i = 0; i < 3; i++) { 8005638: f897 3070 ldrb.w r3, [r7, #112] @ 0x70 800563c: 3301 adds r3, #1 800563e: f887 3070 strb.w r3, [r7, #112] @ 0x70 8005642: f897 3070 ldrb.w r3, [r7, #112] @ 0x70 8005646: 2b02 cmp r3, #2 8005648: d9e8 bls.n 800561c } osMutexRelease (resMeasurementsMutex); 800564a: 4b09 ldr r3, [pc, #36] @ (8005670 ) 800564c: 681b ldr r3, [r3, #0] 800564e: 4618 mov r0, r3 8005650: f00e f9fc bl 8013a4c respStatus = spOK; 8005654: 2300 movs r3, #0 8005656: f887 308f strb.w r3, [r7, #143] @ 0x8f } else { respStatus = spInternalError; } break; 800565a: e074 b.n 8005746 respStatus = spInternalError; 800565c: 23fc movs r3, #252 @ 0xfc 800565e: f887 308f strb.w r3, [r7, #143] @ 0x8f break; 8005662: e070 b.n 8005746 __ASM volatile ("cpsid i" : : : "memory"); 8005664: b672 cpsid i } 8005666: bf00 nop case spResetSystem: __disable_irq(); NVIC_SystemReset(); 8005668: f7fe ff58 bl 800451c <__NVIC_SystemReset> 800566c: 24000564 .word 0x24000564 8005670: 240008d8 .word 0x240008d8 8005674: 24000900 .word 0x24000900 8005678: 240008dc .word 0x240008dc 800567c: 24000940 .word 0x24000940 8005680: 42c80000 .word 0x42c80000 8005684: 43b40000 .word 0x43b40000 8005688: 24000000 .word 0x24000000 800568c: 24000018 .word 0x24000018 break; case spSetPositonX: PositionControlTaskData posXData __attribute__ ((aligned (32))) = { 0 }; 8005690: f04f 0300 mov.w r3, #0 8005694: 6023 str r3, [r4, #0] if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8005696: 4b3e ldr r3, [pc, #248] @ (8005790 ) 8005698: 681b ldr r3, [r3, #0] 800569a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800569e: 4618 mov r0, r3 80056a0: f00e f989 bl 80139b6 80056a4: 4603 mov r3, r0 80056a6: 2b00 cmp r3, #0 80056a8: d108 bne.n 80056bc sensorsInfo.positionXWeak = 1; 80056aa: 4b3a ldr r3, [pc, #232] @ (8005794 ) 80056ac: 2201 movs r2, #1 80056ae: f883 2038 strb.w r2, [r3, #56] @ 0x38 osMutexRelease (sensorsInfoMutex); 80056b2: 4b37 ldr r3, [pc, #220] @ (8005790 ) 80056b4: 681b ldr r3, [r3, #0] 80056b6: 4618 mov r0, r3 80056b8: f00e f9c8 bl 8013a4c } if (positionXControlTaskInitArg.positionSettingQueue != NULL) 80056bc: 4b36 ldr r3, [pc, #216] @ (8005798 ) 80056be: 691b ldr r3, [r3, #16] 80056c0: 2b00 cmp r3, #0 80056c2: d03d beq.n 8005740 { ReadFloatFromBuffer(spFrameData->dataBuffer, &inputDataBufferPos, &posXData.positionSettingValue); 80056c4: 683b ldr r3, [r7, #0] 80056c6: 330c adds r3, #12 80056c8: f107 0154 add.w r1, r7, #84 @ 0x54 80056cc: 4622 mov r2, r4 80056ce: 4618 mov r0, r3 80056d0: f7fd ff37 bl 8003542 osMessageQueuePut(positionXControlTaskInitArg.positionSettingQueue, &posXData, 0, 0); 80056d4: 4b30 ldr r3, [pc, #192] @ (8005798 ) 80056d6: 6918 ldr r0, [r3, #16] 80056d8: 2300 movs r3, #0 80056da: 2200 movs r2, #0 80056dc: 4621 mov r1, r4 80056de: f00e fa65 bl 8013bac } break; 80056e2: e02d b.n 8005740 case spSetPositonY: if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80056e4: 4b2a ldr r3, [pc, #168] @ (8005790 ) 80056e6: 681b ldr r3, [r3, #0] 80056e8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80056ec: 4618 mov r0, r3 80056ee: f00e f962 bl 80139b6 80056f2: 4603 mov r3, r0 80056f4: 2b00 cmp r3, #0 80056f6: d108 bne.n 800570a sensorsInfo.positionYWeak = 1; 80056f8: 4b26 ldr r3, [pc, #152] @ (8005794 ) 80056fa: 2201 movs r2, #1 80056fc: f883 2039 strb.w r2, [r3, #57] @ 0x39 osMutexRelease (sensorsInfoMutex); 8005700: 4b23 ldr r3, [pc, #140] @ (8005790 ) 8005702: 681b ldr r3, [r3, #0] 8005704: 4618 mov r0, r3 8005706: f00e f9a1 bl 8013a4c } PositionControlTaskData posYData __attribute__ ((aligned (32))) = { 0 }; 800570a: f04f 0300 mov.w r3, #0 800570e: 6023 str r3, [r4, #0] if (positionYControlTaskInitArg.positionSettingQueue != NULL) 8005710: 4b22 ldr r3, [pc, #136] @ (800579c ) 8005712: 691b ldr r3, [r3, #16] 8005714: 2b00 cmp r3, #0 8005716: d015 beq.n 8005744 { ReadFloatFromBuffer(spFrameData->dataBuffer, &inputDataBufferPos, &posYData.positionSettingValue); 8005718: 683b ldr r3, [r7, #0] 800571a: 330c adds r3, #12 800571c: f107 0154 add.w r1, r7, #84 @ 0x54 8005720: 4622 mov r2, r4 8005722: 4618 mov r0, r3 8005724: f7fd ff0d bl 8003542 osMessageQueuePut(positionYControlTaskInitArg.positionSettingQueue, &posYData, 0, 0); 8005728: 4b1c ldr r3, [pc, #112] @ (800579c ) 800572a: 6918 ldr r0, [r3, #16] 800572c: 2300 movs r3, #0 800572e: 2200 movs r2, #0 8005730: 4621 mov r1, r4 8005732: f00e fa3b bl 8013bac } break; 8005736: e005 b.n 8005744 default: respStatus = spUnknownCommand; break; 8005738: 23fd movs r3, #253 @ 0xfd 800573a: f887 308f strb.w r3, [r7, #143] @ 0x8f 800573e: e002 b.n 8005746 break; 8005740: bf00 nop 8005742: e000 b.n 8005746 break; 8005744: bf00 nop } dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8005746: 6efb ldr r3, [r7, #108] @ 0x6c 8005748: 6898 ldr r0, [r3, #8] 800574a: 683b ldr r3, [r7, #0] 800574c: 8819 ldrh r1, [r3, #0] 800574e: 683b ldr r3, [r7, #0] 8005750: 789a ldrb r2, [r3, #2] 8005752: 4b13 ldr r3, [pc, #76] @ (80057a0 ) 8005754: 881b ldrh r3, [r3, #0] 8005756: f997 408f ldrsb.w r4, [r7, #143] @ 0x8f 800575a: 9301 str r3, [sp, #4] 800575c: 4b11 ldr r3, [pc, #68] @ (80057a4 ) 800575e: 9300 str r3, [sp, #0] 8005760: 4623 mov r3, r4 8005762: f7fd ff57 bl 8003614 8005766: 4603 mov r3, r0 8005768: f8a7 306a strh.w r3, [r7, #106] @ 0x6a if (dataToSend > 0) { 800576c: f8b7 306a ldrh.w r3, [r7, #106] @ 0x6a 8005770: 2b00 cmp r3, #0 8005772: d008 beq.n 8005786 HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 8005774: 6efb ldr r3, [r7, #108] @ 0x6c 8005776: 6b18 ldr r0, [r3, #48] @ 0x30 8005778: 6efb ldr r3, [r7, #108] @ 0x6c 800577a: 689b ldr r3, [r3, #8] 800577c: f8b7 206a ldrh.w r2, [r7, #106] @ 0x6a 8005780: 4619 mov r1, r3 8005782: f00b f8eb bl 801095c } #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: TX bytes sent: %d\n", uartTaskData->uartNumber, dataToSend); #endif } 8005786: bf00 nop 8005788: 3794 adds r7, #148 @ 0x94 800578a: 46bd mov sp, r7 800578c: bd90 pop {r4, r7, pc} 800578e: bf00 nop 8005790: 240008dc .word 0x240008dc 8005794: 24000940 .word 0x24000940 8005798: 24000a00 .word 0x24000a00 800579c: 24000a40 .word 0x24000a40 80057a0: 240011b8 .word 0x240011b8 80057a4: 24001138 .word 0x24001138 080057a8 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 80057a8: f8df d034 ldr.w sp, [pc, #52] @ 80057e0 /* Call the clock system initialization function.*/ bl SystemInit 80057ac: f7fe fe2e bl 800440c /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80057b0: 480c ldr r0, [pc, #48] @ (80057e4 ) ldr r1, =_edata 80057b2: 490d ldr r1, [pc, #52] @ (80057e8 ) ldr r2, =_sidata 80057b4: 4a0d ldr r2, [pc, #52] @ (80057ec ) movs r3, #0 80057b6: 2300 movs r3, #0 b LoopCopyDataInit 80057b8: e002 b.n 80057c0 080057ba : CopyDataInit: ldr r4, [r2, r3] 80057ba: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80057bc: 50c4 str r4, [r0, r3] adds r3, r3, #4 80057be: 3304 adds r3, #4 080057c0 : LoopCopyDataInit: adds r4, r0, r3 80057c0: 18c4 adds r4, r0, r3 cmp r4, r1 80057c2: 428c cmp r4, r1 bcc CopyDataInit 80057c4: d3f9 bcc.n 80057ba /* Zero fill the bss segment. */ ldr r2, =_sbss 80057c6: 4a0a ldr r2, [pc, #40] @ (80057f0 ) ldr r4, =_ebss 80057c8: 4c0a ldr r4, [pc, #40] @ (80057f4 ) movs r3, #0 80057ca: 2300 movs r3, #0 b LoopFillZerobss 80057cc: e001 b.n 80057d2 080057ce : FillZerobss: str r3, [r2] 80057ce: 6013 str r3, [r2, #0] adds r2, r2, #4 80057d0: 3204 adds r2, #4 080057d2 : LoopFillZerobss: cmp r2, r4 80057d2: 42a2 cmp r2, r4 bcc FillZerobss 80057d4: d3fb bcc.n 80057ce /* Call static constructors */ bl __libc_init_array 80057d6: f012 fef5 bl 80185c4 <__libc_init_array> /* Call the application's entry point.*/ bl main 80057da: f7fa fffd bl 80007d8
bx lr 80057de: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 80057e0: 24060000 .word 0x24060000 ldr r0, =_sdata 80057e4: 24000000 .word 0x24000000 ldr r1, =_edata 80057e8: 24000210 .word 0x24000210 ldr r2, =_sidata 80057ec: 0801a648 .word 0x0801a648 ldr r2, =_sbss 80057f0: 24000220 .word 0x24000220 ldr r4, =_ebss 80057f4: 240132f4 .word 0x240132f4 080057f8 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80057f8: e7fe b.n 80057f8 ... 080057fc : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80057fc: b580 push {r7, lr} 80057fe: b082 sub sp, #8 8005800: af00 add r7, sp, #0 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ #endif /* DUAL_CORE && CORE_CM4 */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8005802: 2003 movs r0, #3 8005804: f001 ffd7 bl 80077b6 /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8005808: f006 fce0 bl 800c1cc 800580c: 4602 mov r2, r0 800580e: 4b15 ldr r3, [pc, #84] @ (8005864 ) 8005810: 699b ldr r3, [r3, #24] 8005812: 0a1b lsrs r3, r3, #8 8005814: f003 030f and.w r3, r3, #15 8005818: 4913 ldr r1, [pc, #76] @ (8005868 ) 800581a: 5ccb ldrb r3, [r1, r3] 800581c: f003 031f and.w r3, r3, #31 8005820: fa22 f303 lsr.w r3, r2, r3 8005824: 607b str r3, [r7, #4] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8005826: 4b0f ldr r3, [pc, #60] @ (8005864 ) 8005828: 699b ldr r3, [r3, #24] 800582a: f003 030f and.w r3, r3, #15 800582e: 4a0e ldr r2, [pc, #56] @ (8005868 ) 8005830: 5cd3 ldrb r3, [r2, r3] 8005832: f003 031f and.w r3, r3, #31 8005836: 687a ldr r2, [r7, #4] 8005838: fa22 f303 lsr.w r3, r2, r3 800583c: 4a0b ldr r2, [pc, #44] @ (800586c ) 800583e: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8005840: 4a0b ldr r2, [pc, #44] @ (8005870 ) 8005842: 687b ldr r3, [r7, #4] 8005844: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8005846: 2005 movs r0, #5 8005848: f7fe fc32 bl 80040b0 800584c: 4603 mov r3, r0 800584e: 2b00 cmp r3, #0 8005850: d001 beq.n 8005856 { return HAL_ERROR; 8005852: 2301 movs r3, #1 8005854: e002 b.n 800585c } /* Init the low level hardware */ HAL_MspInit(); 8005856: f7fd ff7b bl 8003750 /* Return function status */ return HAL_OK; 800585a: 2300 movs r3, #0 } 800585c: 4618 mov r0, r3 800585e: 3708 adds r7, #8 8005860: 46bd mov sp, r7 8005862: bd80 pop {r7, pc} 8005864: 58024400 .word 0x58024400 8005868: 0801a288 .word 0x0801a288 800586c: 24000038 .word 0x24000038 8005870: 24000034 .word 0x24000034 08005874 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8005874: b480 push {r7} 8005876: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 8005878: 4b06 ldr r3, [pc, #24] @ (8005894 ) 800587a: 781b ldrb r3, [r3, #0] 800587c: 461a mov r2, r3 800587e: 4b06 ldr r3, [pc, #24] @ (8005898 ) 8005880: 681b ldr r3, [r3, #0] 8005882: 4413 add r3, r2 8005884: 4a04 ldr r2, [pc, #16] @ (8005898 ) 8005886: 6013 str r3, [r2, #0] } 8005888: bf00 nop 800588a: 46bd mov sp, r7 800588c: f85d 7b04 ldr.w r7, [sp], #4 8005890: 4770 bx lr 8005892: bf00 nop 8005894: 24000040 .word 0x24000040 8005898: 240011bc .word 0x240011bc 0800589c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 800589c: b480 push {r7} 800589e: af00 add r7, sp, #0 return uwTick; 80058a0: 4b03 ldr r3, [pc, #12] @ (80058b0 ) 80058a2: 681b ldr r3, [r3, #0] } 80058a4: 4618 mov r0, r3 80058a6: 46bd mov sp, r7 80058a8: f85d 7b04 ldr.w r7, [sp], #4 80058ac: 4770 bx lr 80058ae: bf00 nop 80058b0: 240011bc .word 0x240011bc 080058b4 : /** * @brief Returns the device revision identifier. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { 80058b4: b480 push {r7} 80058b6: af00 add r7, sp, #0 return((DBGMCU->IDCODE) >> 16); 80058b8: 4b03 ldr r3, [pc, #12] @ (80058c8 ) 80058ba: 681b ldr r3, [r3, #0] 80058bc: 0c1b lsrs r3, r3, #16 } 80058be: 4618 mov r0, r3 80058c0: 46bd mov sp, r7 80058c2: f85d 7b04 ldr.w r7, [sp], #4 80058c6: 4770 bx lr 80058c8: 5c001000 .word 0x5c001000 080058cc : * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. * @retval None */ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) { 80058cc: b480 push {r7} 80058ce: b083 sub sp, #12 80058d0: af00 add r7, sp, #0 80058d2: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); 80058d4: 4b06 ldr r3, [pc, #24] @ (80058f0 ) 80058d6: 681b ldr r3, [r3, #0] 80058d8: f023 0202 bic.w r2, r3, #2 80058dc: 4904 ldr r1, [pc, #16] @ (80058f0 ) 80058de: 687b ldr r3, [r7, #4] 80058e0: 4313 orrs r3, r2 80058e2: 600b str r3, [r1, #0] } 80058e4: bf00 nop 80058e6: 370c adds r7, #12 80058e8: 46bd mov sp, r7 80058ea: f85d 7b04 ldr.w r7, [sp], #4 80058ee: 4770 bx lr 80058f0: 58003c00 .word 0x58003c00 080058f4 : * @brief Disable the Internal Voltage Reference buffer (VREFBUF). * * @retval None */ void HAL_SYSCFG_DisableVREFBUF(void) { 80058f4: b480 push {r7} 80058f6: af00 add r7, sp, #0 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); 80058f8: 4b05 ldr r3, [pc, #20] @ (8005910 ) 80058fa: 681b ldr r3, [r3, #0] 80058fc: 4a04 ldr r2, [pc, #16] @ (8005910 ) 80058fe: f023 0301 bic.w r3, r3, #1 8005902: 6013 str r3, [r2, #0] } 8005904: bf00 nop 8005906: 46bd mov sp, r7 8005908: f85d 7b04 ldr.w r7, [sp], #4 800590c: 4770 bx lr 800590e: bf00 nop 8005910: 58003c00 .word 0x58003c00 08005914 : * @arg SYSCFG_SWITCH_PC3_CLOSE * @retval None */ void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ) { 8005914: b480 push {r7} 8005916: b083 sub sp, #12 8005918: af00 add r7, sp, #0 800591a: 6078 str r0, [r7, #4] 800591c: 6039 str r1, [r7, #0] /* Check the parameter */ assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch)); assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState)); MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState)); 800591e: 4b07 ldr r3, [pc, #28] @ (800593c ) 8005920: 685a ldr r2, [r3, #4] 8005922: 687b ldr r3, [r7, #4] 8005924: 43db mvns r3, r3 8005926: 401a ands r2, r3 8005928: 4904 ldr r1, [pc, #16] @ (800593c ) 800592a: 683b ldr r3, [r7, #0] 800592c: 4313 orrs r3, r2 800592e: 604b str r3, [r1, #4] } 8005930: bf00 nop 8005932: 370c adds r7, #12 8005934: 46bd mov sp, r7 8005936: f85d 7b04 ldr.w r7, [sp], #4 800593a: 4770 bx lr 800593c: 58000400 .word 0x58000400 08005940 : * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) { 8005940: b480 push {r7} 8005942: b083 sub sp, #12 8005944: af00 add r7, sp, #0 8005946: 6078 str r0, [r7, #4] 8005948: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); 800594a: 687b ldr r3, [r7, #4] 800594c: 689b ldr r3, [r3, #8] 800594e: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000 8005952: 683b ldr r3, [r7, #0] 8005954: 431a orrs r2, r3 8005956: 687b ldr r3, [r7, #4] 8005958: 609a str r2, [r3, #8] } 800595a: bf00 nop 800595c: 370c adds r7, #12 800595e: 46bd mov sp, r7 8005960: f85d 7b04 ldr.w r7, [sp], #4 8005964: 4770 bx lr 08005966 : * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { 8005966: b480 push {r7} 8005968: b083 sub sp, #12 800596a: af00 add r7, sp, #0 800596c: 6078 str r0, [r7, #4] 800596e: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); 8005970: 687b ldr r3, [r7, #4] 8005972: 689b ldr r3, [r3, #8] 8005974: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000 8005978: 683b ldr r3, [r7, #0] 800597a: 431a orrs r2, r3 800597c: 687b ldr r3, [r7, #4] 800597e: 609a str r2, [r3, #8] } 8005980: bf00 nop 8005982: 370c adds r7, #12 8005984: 46bd mov sp, r7 8005986: f85d 7b04 ldr.w r7, [sp], #4 800598a: 4770 bx lr 0800598c : * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) { 800598c: b480 push {r7} 800598e: b083 sub sp, #12 8005990: af00 add r7, sp, #0 8005992: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 8005994: 687b ldr r3, [r7, #4] 8005996: 689b ldr r3, [r3, #8] 8005998: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000 } 800599c: 4618 mov r0, r3 800599e: 370c adds r7, #12 80059a0: 46bd mov sp, r7 80059a2: f85d 7b04 ldr.w r7, [sp], #4 80059a6: 4770 bx lr 080059a8 : * Other channels are slow channels (conversion rate: refer to reference manual). * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x3FFFFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { 80059a8: b480 push {r7} 80059aa: b087 sub sp, #28 80059ac: af00 add r7, sp, #0 80059ae: 60f8 str r0, [r7, #12] 80059b0: 60b9 str r1, [r7, #8] 80059b2: 607a str r2, [r7, #4] 80059b4: 603b str r3, [r7, #0] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 80059b6: 68fb ldr r3, [r7, #12] 80059b8: 3360 adds r3, #96 @ 0x60 80059ba: 461a mov r2, r3 80059bc: 68bb ldr r3, [r7, #8] 80059be: 009b lsls r3, r3, #2 80059c0: 4413 add r3, r2 80059c2: 617b str r3, [r7, #20] ADC3_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } else #endif /* ADC_VER_V5_V90 */ { MODIFY_REG(*preg, 80059c4: 697b ldr r3, [r7, #20] 80059c6: 681b ldr r3, [r3, #0] 80059c8: f003 4200 and.w r2, r3, #2147483648 @ 0x80000000 80059cc: 687b ldr r3, [r7, #4] 80059ce: f003 41f8 and.w r1, r3, #2080374784 @ 0x7c000000 80059d2: 683b ldr r3, [r7, #0] 80059d4: 430b orrs r3, r1 80059d6: 431a orrs r2, r3 80059d8: 697b ldr r3, [r7, #20] 80059da: 601a str r2, [r3, #0] ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } } 80059dc: bf00 nop 80059de: 371c adds r7, #28 80059e0: 46bd mov sp, r7 80059e2: f85d 7b04 ldr.w r7, [sp], #4 80059e6: 4770 bx lr 080059e8 : * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift) { 80059e8: b480 push {r7} 80059ea: b085 sub sp, #20 80059ec: af00 add r7, sp, #0 80059ee: 60f8 str r0, [r7, #12] 80059f0: 60b9 str r1, [r7, #8] 80059f2: 607a str r2, [r7, #4] MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL)); 80059f4: 68fb ldr r3, [r7, #12] 80059f6: 691b ldr r3, [r3, #16] 80059f8: f423 42f0 bic.w r2, r3, #30720 @ 0x7800 80059fc: 68bb ldr r3, [r7, #8] 80059fe: f003 031f and.w r3, r3, #31 8005a02: 6879 ldr r1, [r7, #4] 8005a04: fa01 f303 lsl.w r3, r1, r3 8005a08: 431a orrs r2, r3 8005a0a: 68fb ldr r3, [r7, #12] 8005a0c: 611a str r2, [r3, #16] } 8005a0e: bf00 nop 8005a10: 3714 adds r7, #20 8005a12: 46bd mov sp, r7 8005a14: f85d 7b04 ldr.w r7, [sp], #4 8005a18: 4770 bx lr 08005a1a : * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation) { 8005a1a: b480 push {r7} 8005a1c: b087 sub sp, #28 8005a1e: af00 add r7, sp, #0 8005a20: 60f8 str r0, [r7, #12] 8005a22: 60b9 str r1, [r7, #8] 8005a24: 607a str r2, [r7, #4] /* Function not available on this instance */ } else #endif /* ADC_VER_V5_V90 */ { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8005a26: 68fb ldr r3, [r7, #12] 8005a28: 3360 adds r3, #96 @ 0x60 8005a2a: 461a mov r2, r3 8005a2c: 68bb ldr r3, [r7, #8] 8005a2e: 009b lsls r3, r3, #2 8005a30: 4413 add r3, r2 8005a32: 617b str r3, [r7, #20] MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation); 8005a34: 697b ldr r3, [r7, #20] 8005a36: 681b ldr r3, [r3, #0] 8005a38: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 8005a3c: 687b ldr r3, [r7, #4] 8005a3e: 431a orrs r2, r3 8005a40: 697b ldr r3, [r7, #20] 8005a42: 601a str r2, [r3, #0] } } 8005a44: bf00 nop 8005a46: 371c adds r7, #28 8005a48: 46bd mov sp, r7 8005a4a: f85d 7b04 ldr.w r7, [sp], #4 8005a4e: 4770 bx lr 08005a50 : * @param ADCx ADC instance * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { 8005a50: b480 push {r7} 8005a52: b083 sub sp, #12 8005a54: af00 add r7, sp, #0 8005a56: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); 8005a58: 687b ldr r3, [r7, #4] 8005a5a: 68db ldr r3, [r3, #12] 8005a5c: f403 6340 and.w r3, r3, #3072 @ 0xc00 8005a60: 2b00 cmp r3, #0 8005a62: d101 bne.n 8005a68 8005a64: 2301 movs r3, #1 8005a66: e000 b.n 8005a6a 8005a68: 2300 movs r3, #0 } 8005a6a: 4618 mov r0, r3 8005a6c: 370c adds r7, #12 8005a6e: 46bd mov sp, r7 8005a70: f85d 7b04 ldr.w r7, [sp], #4 8005a74: 4770 bx lr 08005a76 : * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { 8005a76: b480 push {r7} 8005a78: b087 sub sp, #28 8005a7a: af00 add r7, sp, #0 8005a7c: 60f8 str r0, [r7, #12] 8005a7e: 60b9 str r1, [r7, #8] 8005a80: 607a str r2, [r7, #4] /* Set bits with content of parameter "Channel" with bits position */ /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); 8005a82: 68fb ldr r3, [r7, #12] 8005a84: 3330 adds r3, #48 @ 0x30 8005a86: 461a mov r2, r3 8005a88: 68bb ldr r3, [r7, #8] 8005a8a: 0a1b lsrs r3, r3, #8 8005a8c: 009b lsls r3, r3, #2 8005a8e: f003 030c and.w r3, r3, #12 8005a92: 4413 add r3, r2 8005a94: 617b str r3, [r7, #20] MODIFY_REG(*preg, 8005a96: 697b ldr r3, [r7, #20] 8005a98: 681a ldr r2, [r3, #0] 8005a9a: 68bb ldr r3, [r7, #8] 8005a9c: f003 031f and.w r3, r3, #31 8005aa0: 211f movs r1, #31 8005aa2: fa01 f303 lsl.w r3, r1, r3 8005aa6: 43db mvns r3, r3 8005aa8: 401a ands r2, r3 8005aaa: 687b ldr r3, [r7, #4] 8005aac: 0e9b lsrs r3, r3, #26 8005aae: f003 011f and.w r1, r3, #31 8005ab2: 68bb ldr r3, [r7, #8] 8005ab4: f003 031f and.w r3, r3, #31 8005ab8: fa01 f303 lsl.w r3, r1, r3 8005abc: 431a orrs r2, r3 8005abe: 697b ldr r3, [r7, #20] 8005ac0: 601a str r2, [r3, #0] ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } 8005ac2: bf00 nop 8005ac4: 371c adds r7, #28 8005ac6: 46bd mov sp, r7 8005ac8: f85d 7b04 ldr.w r7, [sp], #4 8005acc: 4770 bx lr 08005ace : * @param ADCx ADC instance * @param DataTransferMode Select Data Management configuration * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode) { 8005ace: b480 push {r7} 8005ad0: b083 sub sp, #12 8005ad2: af00 add r7, sp, #0 8005ad4: 6078 str r0, [r7, #4] 8005ad6: 6039 str r1, [r7, #0] MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode); 8005ad8: 687b ldr r3, [r7, #4] 8005ada: 68db ldr r3, [r3, #12] 8005adc: f023 0203 bic.w r2, r3, #3 8005ae0: 683b ldr r3, [r7, #0] 8005ae2: 431a orrs r2, r3 8005ae4: 687b ldr r3, [r7, #4] 8005ae6: 60da str r2, [r3, #12] } 8005ae8: bf00 nop 8005aea: 370c adds r7, #12 8005aec: 46bd mov sp, r7 8005aee: f85d 7b04 ldr.w r7, [sp], #4 8005af2: 4770 bx lr 08005af4 : * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5 * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) { 8005af4: b480 push {r7} 8005af6: b087 sub sp, #28 8005af8: af00 add r7, sp, #0 8005afa: 60f8 str r0, [r7, #12] 8005afc: 60b9 str r1, [r7, #8] 8005afe: 607a str r2, [r7, #4] /* Set bits with content of parameter "SamplingTime" with bits position */ /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 8005b00: 68fb ldr r3, [r7, #12] 8005b02: 3314 adds r3, #20 8005b04: 461a mov r2, r3 8005b06: 68bb ldr r3, [r7, #8] 8005b08: 0e5b lsrs r3, r3, #25 8005b0a: 009b lsls r3, r3, #2 8005b0c: f003 0304 and.w r3, r3, #4 8005b10: 4413 add r3, r2 8005b12: 617b str r3, [r7, #20] MODIFY_REG(*preg, 8005b14: 697b ldr r3, [r7, #20] 8005b16: 681a ldr r2, [r3, #0] 8005b18: 68bb ldr r3, [r7, #8] 8005b1a: 0d1b lsrs r3, r3, #20 8005b1c: f003 031f and.w r3, r3, #31 8005b20: 2107 movs r1, #7 8005b22: fa01 f303 lsl.w r3, r1, r3 8005b26: 43db mvns r3, r3 8005b28: 401a ands r2, r3 8005b2a: 68bb ldr r3, [r7, #8] 8005b2c: 0d1b lsrs r3, r3, #20 8005b2e: f003 031f and.w r3, r3, #31 8005b32: 6879 ldr r1, [r7, #4] 8005b34: fa01 f303 lsl.w r3, r1, r3 8005b38: 431a orrs r2, r3 8005b3a: 697b ldr r3, [r7, #20] 8005b3c: 601a str r2, [r3, #0] ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); } 8005b3e: bf00 nop 8005b40: 371c adds r7, #28 8005b42: 46bd mov sp, r7 8005b44: f85d 7b04 ldr.w r7, [sp], #4 8005b48: 4770 bx lr ... 08005b4c : * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) { 8005b4c: b480 push {r7} 8005b4e: b085 sub sp, #20 8005b50: af00 add r7, sp, #0 8005b52: 60f8 str r0, [r7, #12] 8005b54: 60b9 str r1, [r7, #8] 8005b56: 607a str r2, [r7, #4] } #else /* ADC_VER_V5_V90 */ /* Bits of channels in single or differential mode are set only for */ /* differential mode (for single mode, mask of bits allowed to be set is */ /* shifted out of range of bits of channels in single or differential mode. */ MODIFY_REG(ADCx->DIFSEL, 8005b58: 68fb ldr r3, [r7, #12] 8005b5a: f8d3 20c0 ldr.w r2, [r3, #192] @ 0xc0 8005b5e: 68bb ldr r3, [r7, #8] 8005b60: f3c3 0313 ubfx r3, r3, #0, #20 8005b64: 43db mvns r3, r3 8005b66: 401a ands r2, r3 8005b68: 687b ldr r3, [r7, #4] 8005b6a: f003 0318 and.w r3, r3, #24 8005b6e: 4908 ldr r1, [pc, #32] @ (8005b90 ) 8005b70: 40d9 lsrs r1, r3 8005b72: 68bb ldr r3, [r7, #8] 8005b74: 400b ands r3, r1 8005b76: f3c3 0313 ubfx r3, r3, #0, #20 8005b7a: 431a orrs r2, r3 8005b7c: 68fb ldr r3, [r7, #12] 8005b7e: f8c3 20c0 str.w r2, [r3, #192] @ 0xc0 Channel & ADC_SINGLEDIFF_CHANNEL_MASK, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); #endif /* ADC_VER_V5_V90 */ } 8005b82: bf00 nop 8005b84: 3714 adds r7, #20 8005b86: 46bd mov sp, r7 8005b88: f85d 7b04 ldr.w r7, [sp], #4 8005b8c: 4770 bx lr 8005b8e: bf00 nop 8005b90: 000fffff .word 0x000fffff 08005b94 : * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) { 8005b94: b480 push {r7} 8005b96: b083 sub sp, #12 8005b98: af00 add r7, sp, #0 8005b9a: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 8005b9c: 687b ldr r3, [r7, #4] 8005b9e: 689b ldr r3, [r3, #8] 8005ba0: f003 031f and.w r3, r3, #31 } 8005ba4: 4618 mov r0, r3 8005ba6: 370c adds r7, #12 8005ba8: 46bd mov sp, r7 8005baa: f85d 7b04 ldr.w r7, [sp], #4 8005bae: 4770 bx lr 08005bb0 : * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) { 8005bb0: b480 push {r7} 8005bb2: b083 sub sp, #12 8005bb4: af00 add r7, sp, #0 8005bb6: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); 8005bb8: 687b ldr r3, [r7, #4] 8005bba: 689a ldr r2, [r3, #8] 8005bbc: 4b04 ldr r3, [pc, #16] @ (8005bd0 ) 8005bbe: 4013 ands r3, r2 8005bc0: 687a ldr r2, [r7, #4] 8005bc2: 6093 str r3, [r2, #8] } 8005bc4: bf00 nop 8005bc6: 370c adds r7, #12 8005bc8: 46bd mov sp, r7 8005bca: f85d 7b04 ldr.w r7, [sp], #4 8005bce: 4770 bx lr 8005bd0: 5fffffc0 .word 0x5fffffc0 08005bd4 : * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) { 8005bd4: b480 push {r7} 8005bd6: b083 sub sp, #12 8005bd8: af00 add r7, sp, #0 8005bda: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); 8005bdc: 687b ldr r3, [r7, #4] 8005bde: 689b ldr r3, [r3, #8] 8005be0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8005be4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8005be8: d101 bne.n 8005bee 8005bea: 2301 movs r3, #1 8005bec: e000 b.n 8005bf0 8005bee: 2300 movs r3, #0 } 8005bf0: 4618 mov r0, r3 8005bf2: 370c adds r7, #12 8005bf4: 46bd mov sp, r7 8005bf6: f85d 7b04 ldr.w r7, [sp], #4 8005bfa: 4770 bx lr 08005bfc : * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) { 8005bfc: b480 push {r7} 8005bfe: b083 sub sp, #12 8005c00: af00 add r7, sp, #0 8005c02: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8005c04: 687b ldr r3, [r7, #4] 8005c06: 689a ldr r2, [r3, #8] 8005c08: 4b05 ldr r3, [pc, #20] @ (8005c20 ) 8005c0a: 4013 ands r3, r2 8005c0c: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000 8005c10: 687b ldr r3, [r7, #4] 8005c12: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); } 8005c14: bf00 nop 8005c16: 370c adds r7, #12 8005c18: 46bd mov sp, r7 8005c1a: f85d 7b04 ldr.w r7, [sp], #4 8005c1e: 4770 bx lr 8005c20: 6fffffc0 .word 0x6fffffc0 08005c24 : * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) { 8005c24: b480 push {r7} 8005c26: b083 sub sp, #12 8005c28: af00 add r7, sp, #0 8005c2a: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 8005c2c: 687b ldr r3, [r7, #4] 8005c2e: 689b ldr r3, [r3, #8] 8005c30: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8005c34: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8005c38: d101 bne.n 8005c3e 8005c3a: 2301 movs r3, #1 8005c3c: e000 b.n 8005c40 8005c3e: 2300 movs r3, #0 } 8005c40: 4618 mov r0, r3 8005c42: 370c adds r7, #12 8005c44: 46bd mov sp, r7 8005c46: f85d 7b04 ldr.w r7, [sp], #4 8005c4a: 4770 bx lr 08005c4c : * @rmtoll CR ADEN LL_ADC_Enable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) { 8005c4c: b480 push {r7} 8005c4e: b083 sub sp, #12 8005c50: af00 add r7, sp, #0 8005c52: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8005c54: 687b ldr r3, [r7, #4] 8005c56: 689a ldr r2, [r3, #8] 8005c58: 4b05 ldr r3, [pc, #20] @ (8005c70 ) 8005c5a: 4013 ands r3, r2 8005c5c: f043 0201 orr.w r2, r3, #1 8005c60: 687b ldr r3, [r7, #4] 8005c62: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN); } 8005c64: bf00 nop 8005c66: 370c adds r7, #12 8005c68: 46bd mov sp, r7 8005c6a: f85d 7b04 ldr.w r7, [sp], #4 8005c6e: 4770 bx lr 8005c70: 7fffffc0 .word 0x7fffffc0 08005c74 : * @rmtoll CR ADDIS LL_ADC_Disable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) { 8005c74: b480 push {r7} 8005c76: b083 sub sp, #12 8005c78: af00 add r7, sp, #0 8005c7a: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8005c7c: 687b ldr r3, [r7, #4] 8005c7e: 689a ldr r2, [r3, #8] 8005c80: 4b05 ldr r3, [pc, #20] @ (8005c98 ) 8005c82: 4013 ands r3, r2 8005c84: f043 0202 orr.w r2, r3, #2 8005c88: 687b ldr r3, [r7, #4] 8005c8a: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS); } 8005c8c: bf00 nop 8005c8e: 370c adds r7, #12 8005c90: 46bd mov sp, r7 8005c92: f85d 7b04 ldr.w r7, [sp], #4 8005c96: 4770 bx lr 8005c98: 7fffffc0 .word 0x7fffffc0 08005c9c : * @rmtoll CR ADEN LL_ADC_IsEnabled * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) { 8005c9c: b480 push {r7} 8005c9e: b083 sub sp, #12 8005ca0: af00 add r7, sp, #0 8005ca2: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8005ca4: 687b ldr r3, [r7, #4] 8005ca6: 689b ldr r3, [r3, #8] 8005ca8: f003 0301 and.w r3, r3, #1 8005cac: 2b01 cmp r3, #1 8005cae: d101 bne.n 8005cb4 8005cb0: 2301 movs r3, #1 8005cb2: e000 b.n 8005cb6 8005cb4: 2300 movs r3, #0 } 8005cb6: 4618 mov r0, r3 8005cb8: 370c adds r7, #12 8005cba: 46bd mov sp, r7 8005cbc: f85d 7b04 ldr.w r7, [sp], #4 8005cc0: 4770 bx lr 08005cc2 : * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) { 8005cc2: b480 push {r7} 8005cc4: b083 sub sp, #12 8005cc6: af00 add r7, sp, #0 8005cc8: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); 8005cca: 687b ldr r3, [r7, #4] 8005ccc: 689b ldr r3, [r3, #8] 8005cce: f003 0302 and.w r3, r3, #2 8005cd2: 2b02 cmp r3, #2 8005cd4: d101 bne.n 8005cda 8005cd6: 2301 movs r3, #1 8005cd8: e000 b.n 8005cdc 8005cda: 2300 movs r3, #0 } 8005cdc: 4618 mov r0, r3 8005cde: 370c adds r7, #12 8005ce0: 46bd mov sp, r7 8005ce2: f85d 7b04 ldr.w r7, [sp], #4 8005ce6: 4770 bx lr 08005ce8 : * @rmtoll CR ADSTART LL_ADC_REG_StartConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) { 8005ce8: b480 push {r7} 8005cea: b083 sub sp, #12 8005cec: af00 add r7, sp, #0 8005cee: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8005cf0: 687b ldr r3, [r7, #4] 8005cf2: 689a ldr r2, [r3, #8] 8005cf4: 4b05 ldr r3, [pc, #20] @ (8005d0c ) 8005cf6: 4013 ands r3, r2 8005cf8: f043 0204 orr.w r2, r3, #4 8005cfc: 687b ldr r3, [r7, #4] 8005cfe: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART); } 8005d00: bf00 nop 8005d02: 370c adds r7, #12 8005d04: 46bd mov sp, r7 8005d06: f85d 7b04 ldr.w r7, [sp], #4 8005d0a: 4770 bx lr 8005d0c: 7fffffc0 .word 0x7fffffc0 08005d10 : * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) { 8005d10: b480 push {r7} 8005d12: b083 sub sp, #12 8005d14: af00 add r7, sp, #0 8005d16: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8005d18: 687b ldr r3, [r7, #4] 8005d1a: 689b ldr r3, [r3, #8] 8005d1c: f003 0304 and.w r3, r3, #4 8005d20: 2b04 cmp r3, #4 8005d22: d101 bne.n 8005d28 8005d24: 2301 movs r3, #1 8005d26: e000 b.n 8005d2a 8005d28: 2300 movs r3, #0 } 8005d2a: 4618 mov r0, r3 8005d2c: 370c adds r7, #12 8005d2e: 46bd mov sp, r7 8005d30: f85d 7b04 ldr.w r7, [sp], #4 8005d34: 4770 bx lr 08005d36 : * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) { 8005d36: b480 push {r7} 8005d38: b083 sub sp, #12 8005d3a: af00 add r7, sp, #0 8005d3c: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 8005d3e: 687b ldr r3, [r7, #4] 8005d40: 689b ldr r3, [r3, #8] 8005d42: f003 0308 and.w r3, r3, #8 8005d46: 2b08 cmp r3, #8 8005d48: d101 bne.n 8005d4e 8005d4a: 2301 movs r3, #1 8005d4c: e000 b.n 8005d50 8005d4e: 2300 movs r3, #0 } 8005d50: 4618 mov r0, r3 8005d52: 370c adds r7, #12 8005d54: 46bd mov sp, r7 8005d56: f85d 7b04 ldr.w r7, [sp], #4 8005d5a: 4770 bx lr 08005d5c : * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { 8005d5c: b590 push {r4, r7, lr} 8005d5e: b089 sub sp, #36 @ 0x24 8005d60: af00 add r7, sp, #0 8005d62: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8005d64: 2300 movs r3, #0 8005d66: 77fb strb r3, [r7, #31] uint32_t tmpCFGR; uint32_t tmp_adc_reg_is_conversion_on_going; __IO uint32_t wait_loop_index = 0UL; 8005d68: 2300 movs r3, #0 8005d6a: 60bb str r3, [r7, #8] uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check ADC handle */ if (hadc == NULL) 8005d6c: 687b ldr r3, [r7, #4] 8005d6e: 2b00 cmp r3, #0 8005d70: d101 bne.n 8005d76 { return HAL_ERROR; 8005d72: 2301 movs r3, #1 8005d74: e18f b.n 8006096 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 8005d76: 687b ldr r3, [r7, #4] 8005d78: 68db ldr r3, [r3, #12] 8005d7a: 2b00 cmp r3, #0 /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8005d7c: 687b ldr r3, [r7, #4] 8005d7e: 6d5b ldr r3, [r3, #84] @ 0x54 8005d80: 2b00 cmp r3, #0 8005d82: d109 bne.n 8005d98 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8005d84: 6878 ldr r0, [r7, #4] 8005d86: f7fd fd3f bl 8003808 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8005d8a: 687b ldr r3, [r7, #4] 8005d8c: 2200 movs r2, #0 8005d8e: 659a str r2, [r3, #88] @ 0x58 /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; 8005d90: 687b ldr r3, [r7, #4] 8005d92: 2200 movs r2, #0 8005d94: f883 2050 strb.w r2, [r3, #80] @ 0x50 } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) 8005d98: 687b ldr r3, [r7, #4] 8005d9a: 681b ldr r3, [r3, #0] 8005d9c: 4618 mov r0, r3 8005d9e: f7ff ff19 bl 8005bd4 8005da2: 4603 mov r3, r0 8005da4: 2b00 cmp r3, #0 8005da6: d004 beq.n 8005db2 { /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); 8005da8: 687b ldr r3, [r7, #4] 8005daa: 681b ldr r3, [r3, #0] 8005dac: 4618 mov r0, r3 8005dae: f7ff feff bl 8005bb0 /* System was in deep power down mode, calibration must be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 8005db2: 687b ldr r3, [r7, #4] 8005db4: 681b ldr r3, [r3, #0] 8005db6: 4618 mov r0, r3 8005db8: f7ff ff34 bl 8005c24 8005dbc: 4603 mov r3, r0 8005dbe: 2b00 cmp r3, #0 8005dc0: d114 bne.n 8005dec { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); 8005dc2: 687b ldr r3, [r7, #4] 8005dc4: 681b ldr r3, [r3, #0] 8005dc6: 4618 mov r0, r3 8005dc8: f7ff ff18 bl 8005bfc /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8005dcc: 4b87 ldr r3, [pc, #540] @ (8005fec ) 8005dce: 681b ldr r3, [r3, #0] 8005dd0: 099b lsrs r3, r3, #6 8005dd2: 4a87 ldr r2, [pc, #540] @ (8005ff0 ) 8005dd4: fba2 2303 umull r2, r3, r2, r3 8005dd8: 099b lsrs r3, r3, #6 8005dda: 3301 adds r3, #1 8005ddc: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8005dde: e002 b.n 8005de6 { wait_loop_index--; 8005de0: 68bb ldr r3, [r7, #8] 8005de2: 3b01 subs r3, #1 8005de4: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8005de6: 68bb ldr r3, [r7, #8] 8005de8: 2b00 cmp r3, #0 8005dea: d1f9 bne.n 8005de0 } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 8005dec: 687b ldr r3, [r7, #4] 8005dee: 681b ldr r3, [r3, #0] 8005df0: 4618 mov r0, r3 8005df2: f7ff ff17 bl 8005c24 8005df6: 4603 mov r3, r0 8005df8: 2b00 cmp r3, #0 8005dfa: d10d bne.n 8005e18 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8005dfc: 687b ldr r3, [r7, #4] 8005dfe: 6d5b ldr r3, [r3, #84] @ 0x54 8005e00: f043 0210 orr.w r2, r3, #16 8005e04: 687b ldr r3, [r7, #4] 8005e06: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8005e08: 687b ldr r3, [r7, #4] 8005e0a: 6d9b ldr r3, [r3, #88] @ 0x58 8005e0c: f043 0201 orr.w r2, r3, #1 8005e10: 687b ldr r3, [r7, #4] 8005e12: 659a str r2, [r3, #88] @ 0x58 tmp_hal_status = HAL_ERROR; 8005e14: 2301 movs r3, #1 8005e16: 77fb strb r3, [r7, #31] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8005e18: 687b ldr r3, [r7, #4] 8005e1a: 681b ldr r3, [r3, #0] 8005e1c: 4618 mov r0, r3 8005e1e: f7ff ff77 bl 8005d10 8005e22: 6178 str r0, [r7, #20] if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 8005e24: 687b ldr r3, [r7, #4] 8005e26: 6d5b ldr r3, [r3, #84] @ 0x54 8005e28: f003 0310 and.w r3, r3, #16 8005e2c: 2b00 cmp r3, #0 8005e2e: f040 8129 bne.w 8006084 && (tmp_adc_reg_is_conversion_on_going == 0UL) 8005e32: 697b ldr r3, [r7, #20] 8005e34: 2b00 cmp r3, #0 8005e36: f040 8125 bne.w 8006084 ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8005e3a: 687b ldr r3, [r7, #4] 8005e3c: 6d5b ldr r3, [r3, #84] @ 0x54 8005e3e: f423 7381 bic.w r3, r3, #258 @ 0x102 8005e42: f043 0202 orr.w r2, r3, #2 8005e46: 687b ldr r3, [r7, #4] 8005e48: 655a str r2, [r3, #84] @ 0x54 /* Configuration of common ADC parameters */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8005e4a: 687b ldr r3, [r7, #4] 8005e4c: 681b ldr r3, [r3, #0] 8005e4e: 4618 mov r0, r3 8005e50: f7ff ff24 bl 8005c9c 8005e54: 4603 mov r3, r0 8005e56: 2b00 cmp r3, #0 8005e58: d136 bne.n 8005ec8 { if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8005e5a: 687b ldr r3, [r7, #4] 8005e5c: 681b ldr r3, [r3, #0] 8005e5e: 4a65 ldr r2, [pc, #404] @ (8005ff4 ) 8005e60: 4293 cmp r3, r2 8005e62: d004 beq.n 8005e6e 8005e64: 687b ldr r3, [r7, #4] 8005e66: 681b ldr r3, [r3, #0] 8005e68: 4a63 ldr r2, [pc, #396] @ (8005ff8 ) 8005e6a: 4293 cmp r3, r2 8005e6c: d10e bne.n 8005e8c 8005e6e: 4861 ldr r0, [pc, #388] @ (8005ff4 ) 8005e70: f7ff ff14 bl 8005c9c 8005e74: 4604 mov r4, r0 8005e76: 4860 ldr r0, [pc, #384] @ (8005ff8 ) 8005e78: f7ff ff10 bl 8005c9c 8005e7c: 4603 mov r3, r0 8005e7e: 4323 orrs r3, r4 8005e80: 2b00 cmp r3, #0 8005e82: bf0c ite eq 8005e84: 2301 moveq r3, #1 8005e86: 2300 movne r3, #0 8005e88: b2db uxtb r3, r3 8005e8a: e008 b.n 8005e9e 8005e8c: 485b ldr r0, [pc, #364] @ (8005ffc ) 8005e8e: f7ff ff05 bl 8005c9c 8005e92: 4603 mov r3, r0 8005e94: 2b00 cmp r3, #0 8005e96: bf0c ite eq 8005e98: 2301 moveq r3, #1 8005e9a: 2300 movne r3, #0 8005e9c: b2db uxtb r3, r3 8005e9e: 2b00 cmp r3, #0 8005ea0: d012 beq.n 8005ec8 /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ /* HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); 8005ea2: 687b ldr r3, [r7, #4] 8005ea4: 681b ldr r3, [r3, #0] 8005ea6: 4a53 ldr r2, [pc, #332] @ (8005ff4 ) 8005ea8: 4293 cmp r3, r2 8005eaa: d004 beq.n 8005eb6 8005eac: 687b ldr r3, [r7, #4] 8005eae: 681b ldr r3, [r3, #0] 8005eb0: 4a51 ldr r2, [pc, #324] @ (8005ff8 ) 8005eb2: 4293 cmp r3, r2 8005eb4: d101 bne.n 8005eba 8005eb6: 4a52 ldr r2, [pc, #328] @ (8006000 ) 8005eb8: e000 b.n 8005ebc 8005eba: 4a52 ldr r2, [pc, #328] @ (8006004 ) 8005ebc: 687b ldr r3, [r7, #4] 8005ebe: 685b ldr r3, [r3, #4] 8005ec0: 4619 mov r1, r3 8005ec2: 4610 mov r0, r2 8005ec4: f7ff fd3c bl 8005940 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); } #else if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution)) 8005ec8: f7ff fcf4 bl 80058b4 8005ecc: 4603 mov r3, r0 8005ece: f241 0203 movw r2, #4099 @ 0x1003 8005ed2: 4293 cmp r3, r2 8005ed4: d914 bls.n 8005f00 8005ed6: 687b ldr r3, [r7, #4] 8005ed8: 689b ldr r3, [r3, #8] 8005eda: 2b10 cmp r3, #16 8005edc: d110 bne.n 8005f00 { /* for STM32H7 silicon rev.B and above , ADC_CFGR_RES value for 8bits resolution is : b111 */ tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8005ede: 687b ldr r3, [r7, #4] 8005ee0: 7d5b ldrb r3, [r3, #21] 8005ee2: 035a lsls r2, r3, #13 hadc->Init.Overrun | 8005ee4: 687b ldr r3, [r7, #4] 8005ee6: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8005ee8: 431a orrs r2, r3 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 8005eea: 687b ldr r3, [r7, #4] 8005eec: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 8005eee: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8005ef0: 687b ldr r3, [r7, #4] 8005ef2: 7f1b ldrb r3, [r3, #28] 8005ef4: 041b lsls r3, r3, #16 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 8005ef6: 4313 orrs r3, r2 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8005ef8: f043 030c orr.w r3, r3, #12 8005efc: 61bb str r3, [r7, #24] 8005efe: e00d b.n 8005f1c } else { tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8005f00: 687b ldr r3, [r7, #4] 8005f02: 7d5b ldrb r3, [r3, #21] 8005f04: 035a lsls r2, r3, #13 hadc->Init.Overrun | 8005f06: 687b ldr r3, [r7, #4] 8005f08: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8005f0a: 431a orrs r2, r3 hadc->Init.Resolution | 8005f0c: 687b ldr r3, [r7, #4] 8005f0e: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 8005f10: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8005f12: 687b ldr r3, [r7, #4] 8005f14: 7f1b ldrb r3, [r3, #28] 8005f16: 041b lsls r3, r3, #16 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8005f18: 4313 orrs r3, r2 8005f1a: 61bb str r3, [r7, #24] } #endif /* ADC_VER_V5_3 */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8005f1c: 687b ldr r3, [r7, #4] 8005f1e: 7f1b ldrb r3, [r3, #28] 8005f20: 2b01 cmp r3, #1 8005f22: d106 bne.n 8005f32 { tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); 8005f24: 687b ldr r3, [r7, #4] 8005f26: 6a1b ldr r3, [r3, #32] 8005f28: 3b01 subs r3, #1 8005f2a: 045b lsls r3, r3, #17 8005f2c: 69ba ldr r2, [r7, #24] 8005f2e: 4313 orrs r3, r2 8005f30: 61bb str r3, [r7, #24] /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 8005f32: 687b ldr r3, [r7, #4] 8005f34: 6a5b ldr r3, [r3, #36] @ 0x24 8005f36: 2b00 cmp r3, #0 8005f38: d009 beq.n 8005f4e { tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8005f3a: 687b ldr r3, [r7, #4] 8005f3c: 6a5b ldr r3, [r3, #36] @ 0x24 8005f3e: f403 7278 and.w r2, r3, #992 @ 0x3e0 | hadc->Init.ExternalTrigConvEdge 8005f42: 687b ldr r3, [r7, #4] 8005f44: 6a9b ldr r3, [r3, #40] @ 0x28 8005f46: 4313 orrs r3, r2 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8005f48: 69ba ldr r2, [r7, #24] 8005f4a: 4313 orrs r3, r2 8005f4c: 61bb str r3, [r7, #24] /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); } #else /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); 8005f4e: 687b ldr r3, [r7, #4] 8005f50: 681b ldr r3, [r3, #0] 8005f52: 68da ldr r2, [r3, #12] 8005f54: 4b2c ldr r3, [pc, #176] @ (8006008 ) 8005f56: 4013 ands r3, r2 8005f58: 687a ldr r2, [r7, #4] 8005f5a: 6812 ldr r2, [r2, #0] 8005f5c: 69b9 ldr r1, [r7, #24] 8005f5e: 430b orrs r3, r1 8005f60: 60d3 str r3, [r2, #12] /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - Conversion data management Init.ConversionDataManagement */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8005f62: 687b ldr r3, [r7, #4] 8005f64: 681b ldr r3, [r3, #0] 8005f66: 4618 mov r0, r3 8005f68: f7ff fed2 bl 8005d10 8005f6c: 6138 str r0, [r7, #16] tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 8005f6e: 687b ldr r3, [r7, #4] 8005f70: 681b ldr r3, [r3, #0] 8005f72: 4618 mov r0, r3 8005f74: f7ff fedf bl 8005d36 8005f78: 60f8 str r0, [r7, #12] if ((tmp_adc_is_conversion_on_going_regular == 0UL) 8005f7a: 693b ldr r3, [r7, #16] 8005f7c: 2b00 cmp r3, #0 8005f7e: d15f bne.n 8006040 && (tmp_adc_is_conversion_on_going_injected == 0UL) 8005f80: 68fb ldr r3, [r7, #12] 8005f82: 2b00 cmp r3, #0 8005f84: d15c bne.n 8006040 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); } #else tmpCFGR = ( ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8005f86: 687b ldr r3, [r7, #4] 8005f88: 7d1b ldrb r3, [r3, #20] 8005f8a: 039a lsls r2, r3, #14 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); 8005f8c: 687b ldr r3, [r7, #4] 8005f8e: 6adb ldr r3, [r3, #44] @ 0x2c tmpCFGR = ( 8005f90: 4313 orrs r3, r2 8005f92: 61bb str r3, [r7, #24] #endif MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 8005f94: 687b ldr r3, [r7, #4] 8005f96: 681b ldr r3, [r3, #0] 8005f98: 68da ldr r2, [r3, #12] 8005f9a: 4b1c ldr r3, [pc, #112] @ (800600c ) 8005f9c: 4013 ands r3, r2 8005f9e: 687a ldr r2, [r7, #4] 8005fa0: 6812 ldr r2, [r2, #0] 8005fa2: 69b9 ldr r1, [r7, #24] 8005fa4: 430b orrs r3, r1 8005fa6: 60d3 str r3, [r2, #12] if (hadc->Init.OversamplingMode == ENABLE) 8005fa8: 687b ldr r3, [r7, #4] 8005faa: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 8005fae: 2b01 cmp r3, #1 8005fb0: d130 bne.n 8006014 #endif assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START) 8005fb2: 687b ldr r3, [r7, #4] 8005fb4: 6a5b ldr r3, [r3, #36] @ 0x24 8005fb6: 2b00 cmp r3, #0 /* - Oversampling Ratio */ /* - Right bit shift */ /* - Left bit shift */ /* - Triggered mode */ /* - Oversampling mode (continued/resumed) */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, 8005fb8: 687b ldr r3, [r7, #4] 8005fba: 681b ldr r3, [r3, #0] 8005fbc: 691a ldr r2, [r3, #16] 8005fbe: 4b14 ldr r3, [pc, #80] @ (8006010 ) 8005fc0: 4013 ands r3, r2 8005fc2: 687a ldr r2, [r7, #4] 8005fc4: 6bd2 ldr r2, [r2, #60] @ 0x3c 8005fc6: 3a01 subs r2, #1 8005fc8: 0411 lsls r1, r2, #16 8005fca: 687a ldr r2, [r7, #4] 8005fcc: 6c12 ldr r2, [r2, #64] @ 0x40 8005fce: 4311 orrs r1, r2 8005fd0: 687a ldr r2, [r7, #4] 8005fd2: 6c52 ldr r2, [r2, #68] @ 0x44 8005fd4: 4311 orrs r1, r2 8005fd6: 687a ldr r2, [r7, #4] 8005fd8: 6c92 ldr r2, [r2, #72] @ 0x48 8005fda: 430a orrs r2, r1 8005fdc: 431a orrs r2, r3 8005fde: 687b ldr r3, [r7, #4] 8005fe0: 681b ldr r3, [r3, #0] 8005fe2: f042 0201 orr.w r2, r2, #1 8005fe6: 611a str r2, [r3, #16] 8005fe8: e01c b.n 8006024 8005fea: bf00 nop 8005fec: 24000034 .word 0x24000034 8005ff0: 053e2d63 .word 0x053e2d63 8005ff4: 40022000 .word 0x40022000 8005ff8: 40022100 .word 0x40022100 8005ffc: 58026000 .word 0x58026000 8006000: 40022300 .word 0x40022300 8006004: 58026300 .word 0x58026300 8006008: fff0c003 .word 0xfff0c003 800600c: ffffbffc .word 0xffffbffc 8006010: fc00f81e .word 0xfc00f81e } else { /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); 8006014: 687b ldr r3, [r7, #4] 8006016: 681b ldr r3, [r3, #0] 8006018: 691a ldr r2, [r3, #16] 800601a: 687b ldr r3, [r7, #4] 800601c: 681b ldr r3, [r3, #0] 800601e: f022 0201 bic.w r2, r2, #1 8006022: 611a str r2, [r3, #16] } /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift); 8006024: 687b ldr r3, [r7, #4] 8006026: 681b ldr r3, [r3, #0] 8006028: 691b ldr r3, [r3, #16] 800602a: f023 4170 bic.w r1, r3, #4026531840 @ 0xf0000000 800602e: 687b ldr r3, [r7, #4] 8006030: 6b5a ldr r2, [r3, #52] @ 0x34 8006032: 687b ldr r3, [r7, #4] 8006034: 681b ldr r3, [r3, #0] 8006036: 430a orrs r2, r1 8006038: 611a str r2, [r3, #16] /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); } #else /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); 800603a: 6878 ldr r0, [r7, #4] 800603c: f000 fde2 bl 8006c04 /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 8006040: 687b ldr r3, [r7, #4] 8006042: 68db ldr r3, [r3, #12] 8006044: 2b01 cmp r3, #1 8006046: d10c bne.n 8006062 { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); 8006048: 687b ldr r3, [r7, #4] 800604a: 681b ldr r3, [r3, #0] 800604c: 6b1b ldr r3, [r3, #48] @ 0x30 800604e: f023 010f bic.w r1, r3, #15 8006052: 687b ldr r3, [r7, #4] 8006054: 699b ldr r3, [r3, #24] 8006056: 1e5a subs r2, r3, #1 8006058: 687b ldr r3, [r7, #4] 800605a: 681b ldr r3, [r3, #0] 800605c: 430a orrs r2, r1 800605e: 631a str r2, [r3, #48] @ 0x30 8006060: e007 b.n 8006072 } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 8006062: 687b ldr r3, [r7, #4] 8006064: 681b ldr r3, [r3, #0] 8006066: 6b1a ldr r2, [r3, #48] @ 0x30 8006068: 687b ldr r3, [r7, #4] 800606a: 681b ldr r3, [r3, #0] 800606c: f022 020f bic.w r2, r2, #15 8006070: 631a str r2, [r3, #48] @ 0x30 } /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); 8006072: 687b ldr r3, [r7, #4] 8006074: 6d5b ldr r3, [r3, #84] @ 0x54 8006076: f023 0303 bic.w r3, r3, #3 800607a: f043 0201 orr.w r2, r3, #1 800607e: 687b ldr r3, [r7, #4] 8006080: 655a str r2, [r3, #84] @ 0x54 8006082: e007 b.n 8006094 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006084: 687b ldr r3, [r7, #4] 8006086: 6d5b ldr r3, [r3, #84] @ 0x54 8006088: f043 0210 orr.w r2, r3, #16 800608c: 687b ldr r3, [r7, #4] 800608e: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8006090: 2301 movs r3, #1 8006092: 77fb strb r3, [r7, #31] } /* Return function status */ return tmp_hal_status; 8006094: 7ffb ldrb r3, [r7, #31] } 8006096: 4618 mov r0, r3 8006098: 3724 adds r7, #36 @ 0x24 800609a: 46bd mov sp, r7 800609c: bd90 pop {r4, r7, pc} 800609e: bf00 nop 080060a0 : * @param pData Destination Buffer address. * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { 80060a0: b580 push {r7, lr} 80060a2: b086 sub sp, #24 80060a4: af00 add r7, sp, #0 80060a6: 60f8 str r0, [r7, #12] 80060a8: 60b9 str r1, [r7, #8] 80060aa: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 80060ac: 68fb ldr r3, [r7, #12] 80060ae: 681b ldr r3, [r3, #0] 80060b0: 4a55 ldr r2, [pc, #340] @ (8006208 ) 80060b2: 4293 cmp r3, r2 80060b4: d004 beq.n 80060c0 80060b6: 68fb ldr r3, [r7, #12] 80060b8: 681b ldr r3, [r3, #0] 80060ba: 4a54 ldr r2, [pc, #336] @ (800620c ) 80060bc: 4293 cmp r3, r2 80060be: d101 bne.n 80060c4 80060c0: 4b53 ldr r3, [pc, #332] @ (8006210 ) 80060c2: e000 b.n 80060c6 80060c4: 4b53 ldr r3, [pc, #332] @ (8006214 ) 80060c6: 4618 mov r0, r3 80060c8: f7ff fd64 bl 8005b94 80060cc: 6138 str r0, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 80060ce: 68fb ldr r3, [r7, #12] 80060d0: 681b ldr r3, [r3, #0] 80060d2: 4618 mov r0, r3 80060d4: f7ff fe1c bl 8005d10 80060d8: 4603 mov r3, r0 80060da: 2b00 cmp r3, #0 80060dc: f040 808c bne.w 80061f8 { /* Process locked */ __HAL_LOCK(hadc); 80060e0: 68fb ldr r3, [r7, #12] 80060e2: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 80060e6: 2b01 cmp r3, #1 80060e8: d101 bne.n 80060ee 80060ea: 2302 movs r3, #2 80060ec: e087 b.n 80061fe 80060ee: 68fb ldr r3, [r7, #12] 80060f0: 2201 movs r2, #1 80060f2: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Ensure that multimode regular conversions are not enabled. */ /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 80060f6: 693b ldr r3, [r7, #16] 80060f8: 2b00 cmp r3, #0 80060fa: d005 beq.n 8006108 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) 80060fc: 693b ldr r3, [r7, #16] 80060fe: 2b05 cmp r3, #5 8006100: d002 beq.n 8006108 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) 8006102: 693b ldr r3, [r7, #16] 8006104: 2b09 cmp r3, #9 8006106: d170 bne.n 80061ea ) { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8006108: 68f8 ldr r0, [r7, #12] 800610a: f000 fbfd bl 8006908 800610e: 4603 mov r3, r0 8006110: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8006112: 7dfb ldrb r3, [r7, #23] 8006114: 2b00 cmp r3, #0 8006116: d163 bne.n 80061e0 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8006118: 68fb ldr r3, [r7, #12] 800611a: 6d5a ldr r2, [r3, #84] @ 0x54 800611c: 4b3e ldr r3, [pc, #248] @ (8006218 ) 800611e: 4013 ands r3, r2 8006120: f443 7280 orr.w r2, r3, #256 @ 0x100 8006124: 68fb ldr r3, [r7, #12] 8006126: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_REG_BUSY); /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8006128: 68fb ldr r3, [r7, #12] 800612a: 681b ldr r3, [r3, #0] 800612c: 4a37 ldr r2, [pc, #220] @ (800620c ) 800612e: 4293 cmp r3, r2 8006130: d002 beq.n 8006138 8006132: 68fb ldr r3, [r7, #12] 8006134: 681b ldr r3, [r3, #0] 8006136: e000 b.n 800613a 8006138: 4b33 ldr r3, [pc, #204] @ (8006208 ) 800613a: 68fa ldr r2, [r7, #12] 800613c: 6812 ldr r2, [r2, #0] 800613e: 4293 cmp r3, r2 8006140: d002 beq.n 8006148 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8006142: 693b ldr r3, [r7, #16] 8006144: 2b00 cmp r3, #0 8006146: d105 bne.n 8006154 ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8006148: 68fb ldr r3, [r7, #12] 800614a: 6d5b ldr r3, [r3, #84] @ 0x54 800614c: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 8006150: 68fb ldr r3, [r7, #12] 8006152: 655a str r2, [r3, #84] @ 0x54 } /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) 8006154: 68fb ldr r3, [r7, #12] 8006156: 6d5b ldr r3, [r3, #84] @ 0x54 8006158: f403 5380 and.w r3, r3, #4096 @ 0x1000 800615c: 2b00 cmp r3, #0 800615e: d006 beq.n 800616e { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8006160: 68fb ldr r3, [r7, #12] 8006162: 6d9b ldr r3, [r3, #88] @ 0x58 8006164: f023 0206 bic.w r2, r3, #6 8006168: 68fb ldr r3, [r7, #12] 800616a: 659a str r2, [r3, #88] @ 0x58 800616c: e002 b.n 8006174 } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); 800616e: 68fb ldr r3, [r7, #12] 8006170: 2200 movs r2, #0 8006172: 659a str r2, [r3, #88] @ 0x58 } /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 8006174: 68fb ldr r3, [r7, #12] 8006176: 6cdb ldr r3, [r3, #76] @ 0x4c 8006178: 4a28 ldr r2, [pc, #160] @ (800621c ) 800617a: 63da str r2, [r3, #60] @ 0x3c /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 800617c: 68fb ldr r3, [r7, #12] 800617e: 6cdb ldr r3, [r3, #76] @ 0x4c 8006180: 4a27 ldr r2, [pc, #156] @ (8006220 ) 8006182: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 8006184: 68fb ldr r3, [r7, #12] 8006186: 6cdb ldr r3, [r3, #76] @ 0x4c 8006188: 4a26 ldr r2, [pc, #152] @ (8006224 ) 800618a: 64da str r2, [r3, #76] @ 0x4c /* ADC start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 800618c: 68fb ldr r3, [r7, #12] 800618e: 681b ldr r3, [r3, #0] 8006190: 221c movs r2, #28 8006192: 601a str r2, [r3, #0] /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8006194: 68fb ldr r3, [r7, #12] 8006196: 2200 movs r2, #0 8006198: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* With DMA, overrun event is always considered as an error even if hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, ADC_IT_OVR is enabled. */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 800619c: 68fb ldr r3, [r7, #12] 800619e: 681b ldr r3, [r3, #0] 80061a0: 685a ldr r2, [r3, #4] 80061a2: 68fb ldr r3, [r7, #12] 80061a4: 681b ldr r3, [r3, #0] 80061a6: f042 0210 orr.w r2, r2, #16 80061aa: 605a str r2, [r3, #4] { LL_ADC_REG_SetDataTransferMode(hadc->Instance, ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); } #else LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement); 80061ac: 68fb ldr r3, [r7, #12] 80061ae: 681a ldr r2, [r3, #0] 80061b0: 68fb ldr r3, [r7, #12] 80061b2: 6adb ldr r3, [r3, #44] @ 0x2c 80061b4: 4619 mov r1, r3 80061b6: 4610 mov r0, r2 80061b8: f7ff fc89 bl 8005ace #endif /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 80061bc: 68fb ldr r3, [r7, #12] 80061be: 6cd8 ldr r0, [r3, #76] @ 0x4c 80061c0: 68fb ldr r3, [r7, #12] 80061c2: 681b ldr r3, [r3, #0] 80061c4: 3340 adds r3, #64 @ 0x40 80061c6: 4619 mov r1, r3 80061c8: 68ba ldr r2, [r7, #8] 80061ca: 687b ldr r3, [r7, #4] 80061cc: f002 fb50 bl 8008870 80061d0: 4603 mov r3, r0 80061d2: 75fb strb r3, [r7, #23] /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); 80061d4: 68fb ldr r3, [r7, #12] 80061d6: 681b ldr r3, [r3, #0] 80061d8: 4618 mov r0, r3 80061da: f7ff fd85 bl 8005ce8 if (tmp_hal_status == HAL_OK) 80061de: e00d b.n 80061fc } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 80061e0: 68fb ldr r3, [r7, #12] 80061e2: 2200 movs r2, #0 80061e4: f883 2050 strb.w r2, [r3, #80] @ 0x50 if (tmp_hal_status == HAL_OK) 80061e8: e008 b.n 80061fc } } else { tmp_hal_status = HAL_ERROR; 80061ea: 2301 movs r3, #1 80061ec: 75fb strb r3, [r7, #23] /* Process unlocked */ __HAL_UNLOCK(hadc); 80061ee: 68fb ldr r3, [r7, #12] 80061f0: 2200 movs r2, #0 80061f2: f883 2050 strb.w r2, [r3, #80] @ 0x50 80061f6: e001 b.n 80061fc } } else { tmp_hal_status = HAL_BUSY; 80061f8: 2302 movs r3, #2 80061fa: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 80061fc: 7dfb ldrb r3, [r7, #23] } 80061fe: 4618 mov r0, r3 8006200: 3718 adds r7, #24 8006202: 46bd mov sp, r7 8006204: bd80 pop {r7, pc} 8006206: bf00 nop 8006208: 40022000 .word 0x40022000 800620c: 40022100 .word 0x40022100 8006210: 40022300 .word 0x40022300 8006214: 58026300 .word 0x58026300 8006218: fffff0fe .word 0xfffff0fe 800621c: 08006adb .word 0x08006adb 8006220: 08006bb3 .word 0x08006bb3 8006224: 08006bcf .word 0x08006bcf 08006228 : * @brief Conversion DMA half-transfer callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { 8006228: b480 push {r7} 800622a: b083 sub sp, #12 800622c: af00 add r7, sp, #0 800622e: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 8006230: bf00 nop 8006232: 370c adds r7, #12 8006234: 46bd mov sp, r7 8006236: f85d 7b04 ldr.w r7, [sp], #4 800623a: 4770 bx lr 0800623c : * (this function is also clearing overrun flag) * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 800623c: b480 push {r7} 800623e: b083 sub sp, #12 8006240: af00 add r7, sp, #0 8006242: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 8006244: bf00 nop 8006246: 370c adds r7, #12 8006248: 46bd mov sp, r7 800624a: f85d 7b04 ldr.w r7, [sp], #4 800624e: 4770 bx lr 08006250 : * @param hadc ADC handle * @param sConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { 8006250: b590 push {r4, r7, lr} 8006252: b0a1 sub sp, #132 @ 0x84 8006254: af00 add r7, sp, #0 8006256: 6078 str r0, [r7, #4] 8006258: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800625a: 2300 movs r3, #0 800625c: f887 307f strb.w r3, [r7, #127] @ 0x7f uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0; 8006260: 2300 movs r3, #0 8006262: 60bb str r3, [r7, #8] /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); /* Verification of channel number */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) 8006264: 683b ldr r3, [r7, #0] 8006266: 68db ldr r3, [r3, #12] 8006268: 4a65 ldr r2, [pc, #404] @ (8006400 ) 800626a: 4293 cmp r3, r2 } #endif } /* Process locked */ __HAL_LOCK(hadc); 800626c: 687b ldr r3, [r7, #4] 800626e: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8006272: 2b01 cmp r3, #1 8006274: d101 bne.n 800627a 8006276: 2302 movs r3, #2 8006278: e32e b.n 80068d8 800627a: 687b ldr r3, [r7, #4] 800627c: 2201 movs r2, #1 800627e: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8006282: 687b ldr r3, [r7, #4] 8006284: 681b ldr r3, [r3, #0] 8006286: 4618 mov r0, r3 8006288: f7ff fd42 bl 8005d10 800628c: 4603 mov r3, r0 800628e: 2b00 cmp r3, #0 8006290: f040 8313 bne.w 80068ba { if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))) 8006294: 683b ldr r3, [r7, #0] 8006296: 681b ldr r3, [r3, #0] 8006298: 2b00 cmp r3, #0 800629a: db2c blt.n 80062f6 /* ADC channels preselection */ hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); } #else /* ADC channels preselection */ hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); 800629c: 683b ldr r3, [r7, #0] 800629e: 681b ldr r3, [r3, #0] 80062a0: f3c3 0313 ubfx r3, r3, #0, #20 80062a4: 2b00 cmp r3, #0 80062a6: d108 bne.n 80062ba 80062a8: 683b ldr r3, [r7, #0] 80062aa: 681b ldr r3, [r3, #0] 80062ac: 0e9b lsrs r3, r3, #26 80062ae: f003 031f and.w r3, r3, #31 80062b2: 2201 movs r2, #1 80062b4: fa02 f303 lsl.w r3, r2, r3 80062b8: e016 b.n 80062e8 80062ba: 683b ldr r3, [r7, #0] 80062bc: 681b ldr r3, [r3, #0] 80062be: 667b str r3, [r7, #100] @ 0x64 uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80062c0: 6e7b ldr r3, [r7, #100] @ 0x64 80062c2: fa93 f3a3 rbit r3, r3 80062c6: 663b str r3, [r7, #96] @ 0x60 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 80062c8: 6e3b ldr r3, [r7, #96] @ 0x60 80062ca: 66bb str r3, [r7, #104] @ 0x68 optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 80062cc: 6ebb ldr r3, [r7, #104] @ 0x68 80062ce: 2b00 cmp r3, #0 80062d0: d101 bne.n 80062d6 { return 32U; 80062d2: 2320 movs r3, #32 80062d4: e003 b.n 80062de } return __builtin_clz(value); 80062d6: 6ebb ldr r3, [r7, #104] @ 0x68 80062d8: fab3 f383 clz r3, r3 80062dc: b2db uxtb r3, r3 80062de: f003 031f and.w r3, r3, #31 80062e2: 2201 movs r2, #1 80062e4: fa02 f303 lsl.w r3, r2, r3 80062e8: 687a ldr r2, [r7, #4] 80062ea: 6812 ldr r2, [r2, #0] 80062ec: 69d1 ldr r1, [r2, #28] 80062ee: 687a ldr r2, [r7, #4] 80062f0: 6812 ldr r2, [r2, #0] 80062f2: 430b orrs r3, r1 80062f4: 61d3 str r3, [r2, #28] #endif /* ADC_VER_V5_V90 */ } /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); 80062f6: 687b ldr r3, [r7, #4] 80062f8: 6818 ldr r0, [r3, #0] 80062fa: 683b ldr r3, [r7, #0] 80062fc: 6859 ldr r1, [r3, #4] 80062fe: 683b ldr r3, [r7, #0] 8006300: 681b ldr r3, [r3, #0] 8006302: 461a mov r2, r3 8006304: f7ff fbb7 bl 8005a76 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8006308: 687b ldr r3, [r7, #4] 800630a: 681b ldr r3, [r3, #0] 800630c: 4618 mov r0, r3 800630e: f7ff fcff bl 8005d10 8006312: 67b8 str r0, [r7, #120] @ 0x78 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 8006314: 687b ldr r3, [r7, #4] 8006316: 681b ldr r3, [r3, #0] 8006318: 4618 mov r0, r3 800631a: f7ff fd0c bl 8005d36 800631e: 6778 str r0, [r7, #116] @ 0x74 if ((tmp_adc_is_conversion_on_going_regular == 0UL) 8006320: 6fbb ldr r3, [r7, #120] @ 0x78 8006322: 2b00 cmp r3, #0 8006324: f040 80b8 bne.w 8006498 && (tmp_adc_is_conversion_on_going_injected == 0UL) 8006328: 6f7b ldr r3, [r7, #116] @ 0x74 800632a: 2b00 cmp r3, #0 800632c: f040 80b4 bne.w 8006498 ) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); 8006330: 687b ldr r3, [r7, #4] 8006332: 6818 ldr r0, [r3, #0] 8006334: 683b ldr r3, [r7, #0] 8006336: 6819 ldr r1, [r3, #0] 8006338: 683b ldr r3, [r7, #0] 800633a: 689b ldr r3, [r3, #8] 800633c: 461a mov r2, r3 800633e: f7ff fbd9 bl 8005af4 tmpOffsetShifted = ADC3_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); } else #endif /* ADC_VER_V5_V90 */ { tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); 8006342: 4b30 ldr r3, [pc, #192] @ (8006404 ) 8006344: 681b ldr r3, [r3, #0] 8006346: f003 4370 and.w r3, r3, #4026531840 @ 0xf0000000 800634a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800634e: d10b bne.n 8006368 8006350: 683b ldr r3, [r7, #0] 8006352: 695a ldr r2, [r3, #20] 8006354: 687b ldr r3, [r7, #4] 8006356: 681b ldr r3, [r3, #0] 8006358: 68db ldr r3, [r3, #12] 800635a: 089b lsrs r3, r3, #2 800635c: f003 0307 and.w r3, r3, #7 8006360: 005b lsls r3, r3, #1 8006362: fa02 f303 lsl.w r3, r2, r3 8006366: e01d b.n 80063a4 8006368: 687b ldr r3, [r7, #4] 800636a: 681b ldr r3, [r3, #0] 800636c: 68db ldr r3, [r3, #12] 800636e: f003 0310 and.w r3, r3, #16 8006372: 2b00 cmp r3, #0 8006374: d10b bne.n 800638e 8006376: 683b ldr r3, [r7, #0] 8006378: 695a ldr r2, [r3, #20] 800637a: 687b ldr r3, [r7, #4] 800637c: 681b ldr r3, [r3, #0] 800637e: 68db ldr r3, [r3, #12] 8006380: 089b lsrs r3, r3, #2 8006382: f003 0307 and.w r3, r3, #7 8006386: 005b lsls r3, r3, #1 8006388: fa02 f303 lsl.w r3, r2, r3 800638c: e00a b.n 80063a4 800638e: 683b ldr r3, [r7, #0] 8006390: 695a ldr r2, [r3, #20] 8006392: 687b ldr r3, [r7, #4] 8006394: 681b ldr r3, [r3, #0] 8006396: 68db ldr r3, [r3, #12] 8006398: 089b lsrs r3, r3, #2 800639a: f003 0304 and.w r3, r3, #4 800639e: 005b lsls r3, r3, #1 80063a0: fa02 f303 lsl.w r3, r2, r3 80063a4: 673b str r3, [r7, #112] @ 0x70 } if (sConfig->OffsetNumber != ADC_OFFSET_NONE) 80063a6: 683b ldr r3, [r7, #0] 80063a8: 691b ldr r3, [r3, #16] 80063aa: 2b04 cmp r3, #4 80063ac: d02c beq.n 8006408 { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); 80063ae: 687b ldr r3, [r7, #4] 80063b0: 6818 ldr r0, [r3, #0] 80063b2: 683b ldr r3, [r7, #0] 80063b4: 6919 ldr r1, [r3, #16] 80063b6: 683b ldr r3, [r7, #0] 80063b8: 681a ldr r2, [r3, #0] 80063ba: 6f3b ldr r3, [r7, #112] @ 0x70 80063bc: f7ff faf4 bl 80059a8 else #endif /* ADC_VER_V5_V90 */ { assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation)); /* Set ADC selected offset signed saturation */ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); 80063c0: 687b ldr r3, [r7, #4] 80063c2: 6818 ldr r0, [r3, #0] 80063c4: 683b ldr r3, [r7, #0] 80063c6: 6919 ldr r1, [r3, #16] 80063c8: 683b ldr r3, [r7, #0] 80063ca: 7e5b ldrb r3, [r3, #25] 80063cc: 2b01 cmp r3, #1 80063ce: d102 bne.n 80063d6 80063d0: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 80063d4: e000 b.n 80063d8 80063d6: 2300 movs r3, #0 80063d8: 461a mov r2, r3 80063da: f7ff fb1e bl 8005a1a assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift)); /* Set ADC selected offset right shift */ LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); 80063de: 687b ldr r3, [r7, #4] 80063e0: 6818 ldr r0, [r3, #0] 80063e2: 683b ldr r3, [r7, #0] 80063e4: 6919 ldr r1, [r3, #16] 80063e6: 683b ldr r3, [r7, #0] 80063e8: 7e1b ldrb r3, [r3, #24] 80063ea: 2b01 cmp r3, #1 80063ec: d102 bne.n 80063f4 80063ee: f44f 6300 mov.w r3, #2048 @ 0x800 80063f2: e000 b.n 80063f6 80063f4: 2300 movs r3, #0 80063f6: 461a mov r2, r3 80063f8: f7ff faf6 bl 80059e8 80063fc: e04c b.n 8006498 80063fe: bf00 nop 8006400: 47ff0000 .word 0x47ff0000 8006404: 5c001000 .word 0x5c001000 } } else #endif /* ADC_VER_V5_V90 */ { if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8006408: 687b ldr r3, [r7, #4] 800640a: 681b ldr r3, [r3, #0] 800640c: 6e1b ldr r3, [r3, #96] @ 0x60 800640e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006412: 683b ldr r3, [r7, #0] 8006414: 681b ldr r3, [r3, #0] 8006416: 069b lsls r3, r3, #26 8006418: 429a cmp r2, r3 800641a: d107 bne.n 800642c { CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE); 800641c: 687b ldr r3, [r7, #4] 800641e: 681b ldr r3, [r3, #0] 8006420: 6e1a ldr r2, [r3, #96] @ 0x60 8006422: 687b ldr r3, [r7, #4] 8006424: 681b ldr r3, [r3, #0] 8006426: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 800642a: 661a str r2, [r3, #96] @ 0x60 } if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 800642c: 687b ldr r3, [r7, #4] 800642e: 681b ldr r3, [r3, #0] 8006430: 6e5b ldr r3, [r3, #100] @ 0x64 8006432: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006436: 683b ldr r3, [r7, #0] 8006438: 681b ldr r3, [r3, #0] 800643a: 069b lsls r3, r3, #26 800643c: 429a cmp r2, r3 800643e: d107 bne.n 8006450 { CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE); 8006440: 687b ldr r3, [r7, #4] 8006442: 681b ldr r3, [r3, #0] 8006444: 6e5a ldr r2, [r3, #100] @ 0x64 8006446: 687b ldr r3, [r7, #4] 8006448: 681b ldr r3, [r3, #0] 800644a: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 800644e: 665a str r2, [r3, #100] @ 0x64 } if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8006450: 687b ldr r3, [r7, #4] 8006452: 681b ldr r3, [r3, #0] 8006454: 6e9b ldr r3, [r3, #104] @ 0x68 8006456: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 800645a: 683b ldr r3, [r7, #0] 800645c: 681b ldr r3, [r3, #0] 800645e: 069b lsls r3, r3, #26 8006460: 429a cmp r2, r3 8006462: d107 bne.n 8006474 { CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE); 8006464: 687b ldr r3, [r7, #4] 8006466: 681b ldr r3, [r3, #0] 8006468: 6e9a ldr r2, [r3, #104] @ 0x68 800646a: 687b ldr r3, [r7, #4] 800646c: 681b ldr r3, [r3, #0] 800646e: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8006472: 669a str r2, [r3, #104] @ 0x68 } if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8006474: 687b ldr r3, [r7, #4] 8006476: 681b ldr r3, [r3, #0] 8006478: 6edb ldr r3, [r3, #108] @ 0x6c 800647a: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 800647e: 683b ldr r3, [r7, #0] 8006480: 681b ldr r3, [r3, #0] 8006482: 069b lsls r3, r3, #26 8006484: 429a cmp r2, r3 8006486: d107 bne.n 8006498 { CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE); 8006488: 687b ldr r3, [r7, #4] 800648a: 681b ldr r3, [r3, #0] 800648c: 6eda ldr r2, [r3, #108] @ 0x6c 800648e: 687b ldr r3, [r7, #4] 8006490: 681b ldr r3, [r3, #0] 8006492: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8006496: 66da str r2, [r3, #108] @ 0x6c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8006498: 687b ldr r3, [r7, #4] 800649a: 681b ldr r3, [r3, #0] 800649c: 4618 mov r0, r3 800649e: f7ff fbfd bl 8005c9c 80064a2: 4603 mov r3, r0 80064a4: 2b00 cmp r3, #0 80064a6: f040 8211 bne.w 80068cc { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); 80064aa: 687b ldr r3, [r7, #4] 80064ac: 6818 ldr r0, [r3, #0] 80064ae: 683b ldr r3, [r7, #0] 80064b0: 6819 ldr r1, [r3, #0] 80064b2: 683b ldr r3, [r7, #0] 80064b4: 68db ldr r3, [r3, #12] 80064b6: 461a mov r2, r3 80064b8: f7ff fb48 bl 8005b4c /* Configuration of differential mode */ if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) 80064bc: 683b ldr r3, [r7, #0] 80064be: 68db ldr r3, [r3, #12] 80064c0: 4aa1 ldr r2, [pc, #644] @ (8006748 ) 80064c2: 4293 cmp r3, r2 80064c4: f040 812e bne.w 8006724 { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ LL_ADC_SetChannelSamplingTime(hadc->Instance, 80064c8: 687b ldr r3, [r7, #4] 80064ca: 6818 ldr r0, [r3, #0] (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 80064cc: 683b ldr r3, [r7, #0] 80064ce: 681b ldr r3, [r3, #0] 80064d0: f3c3 0313 ubfx r3, r3, #0, #20 80064d4: 2b00 cmp r3, #0 80064d6: d10b bne.n 80064f0 80064d8: 683b ldr r3, [r7, #0] 80064da: 681b ldr r3, [r3, #0] 80064dc: 0e9b lsrs r3, r3, #26 80064de: 3301 adds r3, #1 80064e0: f003 031f and.w r3, r3, #31 80064e4: 2b09 cmp r3, #9 80064e6: bf94 ite ls 80064e8: 2301 movls r3, #1 80064ea: 2300 movhi r3, #0 80064ec: b2db uxtb r3, r3 80064ee: e019 b.n 8006524 80064f0: 683b ldr r3, [r7, #0] 80064f2: 681b ldr r3, [r3, #0] 80064f4: 65bb str r3, [r7, #88] @ 0x58 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80064f6: 6dbb ldr r3, [r7, #88] @ 0x58 80064f8: fa93 f3a3 rbit r3, r3 80064fc: 657b str r3, [r7, #84] @ 0x54 return result; 80064fe: 6d7b ldr r3, [r7, #84] @ 0x54 8006500: 65fb str r3, [r7, #92] @ 0x5c if (value == 0U) 8006502: 6dfb ldr r3, [r7, #92] @ 0x5c 8006504: 2b00 cmp r3, #0 8006506: d101 bne.n 800650c return 32U; 8006508: 2320 movs r3, #32 800650a: e003 b.n 8006514 return __builtin_clz(value); 800650c: 6dfb ldr r3, [r7, #92] @ 0x5c 800650e: fab3 f383 clz r3, r3 8006512: b2db uxtb r3, r3 8006514: 3301 adds r3, #1 8006516: f003 031f and.w r3, r3, #31 800651a: 2b09 cmp r3, #9 800651c: bf94 ite ls 800651e: 2301 movls r3, #1 8006520: 2300 movhi r3, #0 8006522: b2db uxtb r3, r3 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006524: 2b00 cmp r3, #0 8006526: d079 beq.n 800661c (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8006528: 683b ldr r3, [r7, #0] 800652a: 681b ldr r3, [r3, #0] 800652c: f3c3 0313 ubfx r3, r3, #0, #20 8006530: 2b00 cmp r3, #0 8006532: d107 bne.n 8006544 8006534: 683b ldr r3, [r7, #0] 8006536: 681b ldr r3, [r3, #0] 8006538: 0e9b lsrs r3, r3, #26 800653a: 3301 adds r3, #1 800653c: 069b lsls r3, r3, #26 800653e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006542: e015 b.n 8006570 8006544: 683b ldr r3, [r7, #0] 8006546: 681b ldr r3, [r3, #0] 8006548: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800654a: 6cfb ldr r3, [r7, #76] @ 0x4c 800654c: fa93 f3a3 rbit r3, r3 8006550: 64bb str r3, [r7, #72] @ 0x48 return result; 8006552: 6cbb ldr r3, [r7, #72] @ 0x48 8006554: 653b str r3, [r7, #80] @ 0x50 if (value == 0U) 8006556: 6d3b ldr r3, [r7, #80] @ 0x50 8006558: 2b00 cmp r3, #0 800655a: d101 bne.n 8006560 return 32U; 800655c: 2320 movs r3, #32 800655e: e003 b.n 8006568 return __builtin_clz(value); 8006560: 6d3b ldr r3, [r7, #80] @ 0x50 8006562: fab3 f383 clz r3, r3 8006566: b2db uxtb r3, r3 8006568: 3301 adds r3, #1 800656a: 069b lsls r3, r3, #26 800656c: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006570: 683b ldr r3, [r7, #0] 8006572: 681b ldr r3, [r3, #0] 8006574: f3c3 0313 ubfx r3, r3, #0, #20 8006578: 2b00 cmp r3, #0 800657a: d109 bne.n 8006590 800657c: 683b ldr r3, [r7, #0] 800657e: 681b ldr r3, [r3, #0] 8006580: 0e9b lsrs r3, r3, #26 8006582: 3301 adds r3, #1 8006584: f003 031f and.w r3, r3, #31 8006588: 2101 movs r1, #1 800658a: fa01 f303 lsl.w r3, r1, r3 800658e: e017 b.n 80065c0 8006590: 683b ldr r3, [r7, #0] 8006592: 681b ldr r3, [r3, #0] 8006594: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006596: 6c3b ldr r3, [r7, #64] @ 0x40 8006598: fa93 f3a3 rbit r3, r3 800659c: 63fb str r3, [r7, #60] @ 0x3c return result; 800659e: 6bfb ldr r3, [r7, #60] @ 0x3c 80065a0: 647b str r3, [r7, #68] @ 0x44 if (value == 0U) 80065a2: 6c7b ldr r3, [r7, #68] @ 0x44 80065a4: 2b00 cmp r3, #0 80065a6: d101 bne.n 80065ac return 32U; 80065a8: 2320 movs r3, #32 80065aa: e003 b.n 80065b4 return __builtin_clz(value); 80065ac: 6c7b ldr r3, [r7, #68] @ 0x44 80065ae: fab3 f383 clz r3, r3 80065b2: b2db uxtb r3, r3 80065b4: 3301 adds r3, #1 80065b6: f003 031f and.w r3, r3, #31 80065ba: 2101 movs r1, #1 80065bc: fa01 f303 lsl.w r3, r1, r3 80065c0: ea42 0103 orr.w r1, r2, r3 80065c4: 683b ldr r3, [r7, #0] 80065c6: 681b ldr r3, [r3, #0] 80065c8: f3c3 0313 ubfx r3, r3, #0, #20 80065cc: 2b00 cmp r3, #0 80065ce: d10a bne.n 80065e6 80065d0: 683b ldr r3, [r7, #0] 80065d2: 681b ldr r3, [r3, #0] 80065d4: 0e9b lsrs r3, r3, #26 80065d6: 3301 adds r3, #1 80065d8: f003 021f and.w r2, r3, #31 80065dc: 4613 mov r3, r2 80065de: 005b lsls r3, r3, #1 80065e0: 4413 add r3, r2 80065e2: 051b lsls r3, r3, #20 80065e4: e018 b.n 8006618 80065e6: 683b ldr r3, [r7, #0] 80065e8: 681b ldr r3, [r3, #0] 80065ea: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80065ec: 6b7b ldr r3, [r7, #52] @ 0x34 80065ee: fa93 f3a3 rbit r3, r3 80065f2: 633b str r3, [r7, #48] @ 0x30 return result; 80065f4: 6b3b ldr r3, [r7, #48] @ 0x30 80065f6: 63bb str r3, [r7, #56] @ 0x38 if (value == 0U) 80065f8: 6bbb ldr r3, [r7, #56] @ 0x38 80065fa: 2b00 cmp r3, #0 80065fc: d101 bne.n 8006602 return 32U; 80065fe: 2320 movs r3, #32 8006600: e003 b.n 800660a return __builtin_clz(value); 8006602: 6bbb ldr r3, [r7, #56] @ 0x38 8006604: fab3 f383 clz r3, r3 8006608: b2db uxtb r3, r3 800660a: 3301 adds r3, #1 800660c: f003 021f and.w r2, r3, #31 8006610: 4613 mov r3, r2 8006612: 005b lsls r3, r3, #1 8006614: 4413 add r3, r2 8006616: 051b lsls r3, r3, #20 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006618: 430b orrs r3, r1 800661a: e07e b.n 800671a (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 800661c: 683b ldr r3, [r7, #0] 800661e: 681b ldr r3, [r3, #0] 8006620: f3c3 0313 ubfx r3, r3, #0, #20 8006624: 2b00 cmp r3, #0 8006626: d107 bne.n 8006638 8006628: 683b ldr r3, [r7, #0] 800662a: 681b ldr r3, [r3, #0] 800662c: 0e9b lsrs r3, r3, #26 800662e: 3301 adds r3, #1 8006630: 069b lsls r3, r3, #26 8006632: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006636: e015 b.n 8006664 8006638: 683b ldr r3, [r7, #0] 800663a: 681b ldr r3, [r3, #0] 800663c: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800663e: 6abb ldr r3, [r7, #40] @ 0x28 8006640: fa93 f3a3 rbit r3, r3 8006644: 627b str r3, [r7, #36] @ 0x24 return result; 8006646: 6a7b ldr r3, [r7, #36] @ 0x24 8006648: 62fb str r3, [r7, #44] @ 0x2c if (value == 0U) 800664a: 6afb ldr r3, [r7, #44] @ 0x2c 800664c: 2b00 cmp r3, #0 800664e: d101 bne.n 8006654 return 32U; 8006650: 2320 movs r3, #32 8006652: e003 b.n 800665c return __builtin_clz(value); 8006654: 6afb ldr r3, [r7, #44] @ 0x2c 8006656: fab3 f383 clz r3, r3 800665a: b2db uxtb r3, r3 800665c: 3301 adds r3, #1 800665e: 069b lsls r3, r3, #26 8006660: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006664: 683b ldr r3, [r7, #0] 8006666: 681b ldr r3, [r3, #0] 8006668: f3c3 0313 ubfx r3, r3, #0, #20 800666c: 2b00 cmp r3, #0 800666e: d109 bne.n 8006684 8006670: 683b ldr r3, [r7, #0] 8006672: 681b ldr r3, [r3, #0] 8006674: 0e9b lsrs r3, r3, #26 8006676: 3301 adds r3, #1 8006678: f003 031f and.w r3, r3, #31 800667c: 2101 movs r1, #1 800667e: fa01 f303 lsl.w r3, r1, r3 8006682: e017 b.n 80066b4 8006684: 683b ldr r3, [r7, #0] 8006686: 681b ldr r3, [r3, #0] 8006688: 61fb str r3, [r7, #28] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800668a: 69fb ldr r3, [r7, #28] 800668c: fa93 f3a3 rbit r3, r3 8006690: 61bb str r3, [r7, #24] return result; 8006692: 69bb ldr r3, [r7, #24] 8006694: 623b str r3, [r7, #32] if (value == 0U) 8006696: 6a3b ldr r3, [r7, #32] 8006698: 2b00 cmp r3, #0 800669a: d101 bne.n 80066a0 return 32U; 800669c: 2320 movs r3, #32 800669e: e003 b.n 80066a8 return __builtin_clz(value); 80066a0: 6a3b ldr r3, [r7, #32] 80066a2: fab3 f383 clz r3, r3 80066a6: b2db uxtb r3, r3 80066a8: 3301 adds r3, #1 80066aa: f003 031f and.w r3, r3, #31 80066ae: 2101 movs r1, #1 80066b0: fa01 f303 lsl.w r3, r1, r3 80066b4: ea42 0103 orr.w r1, r2, r3 80066b8: 683b ldr r3, [r7, #0] 80066ba: 681b ldr r3, [r3, #0] 80066bc: f3c3 0313 ubfx r3, r3, #0, #20 80066c0: 2b00 cmp r3, #0 80066c2: d10d bne.n 80066e0 80066c4: 683b ldr r3, [r7, #0] 80066c6: 681b ldr r3, [r3, #0] 80066c8: 0e9b lsrs r3, r3, #26 80066ca: 3301 adds r3, #1 80066cc: f003 021f and.w r2, r3, #31 80066d0: 4613 mov r3, r2 80066d2: 005b lsls r3, r3, #1 80066d4: 4413 add r3, r2 80066d6: 3b1e subs r3, #30 80066d8: 051b lsls r3, r3, #20 80066da: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 80066de: e01b b.n 8006718 80066e0: 683b ldr r3, [r7, #0] 80066e2: 681b ldr r3, [r3, #0] 80066e4: 613b str r3, [r7, #16] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80066e6: 693b ldr r3, [r7, #16] 80066e8: fa93 f3a3 rbit r3, r3 80066ec: 60fb str r3, [r7, #12] return result; 80066ee: 68fb ldr r3, [r7, #12] 80066f0: 617b str r3, [r7, #20] if (value == 0U) 80066f2: 697b ldr r3, [r7, #20] 80066f4: 2b00 cmp r3, #0 80066f6: d101 bne.n 80066fc return 32U; 80066f8: 2320 movs r3, #32 80066fa: e003 b.n 8006704 return __builtin_clz(value); 80066fc: 697b ldr r3, [r7, #20] 80066fe: fab3 f383 clz r3, r3 8006702: b2db uxtb r3, r3 8006704: 3301 adds r3, #1 8006706: f003 021f and.w r2, r3, #31 800670a: 4613 mov r3, r2 800670c: 005b lsls r3, r3, #1 800670e: 4413 add r3, r2 8006710: 3b1e subs r3, #30 8006712: 051b lsls r3, r3, #20 8006714: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006718: 430b orrs r3, r1 800671a: 683a ldr r2, [r7, #0] 800671c: 6892 ldr r2, [r2, #8] 800671e: 4619 mov r1, r3 8006720: f7ff f9e8 bl 8005af4 /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 8006724: 683b ldr r3, [r7, #0] 8006726: 681b ldr r3, [r3, #0] 8006728: 2b00 cmp r3, #0 800672a: f280 80cf bge.w 80068cc { /* Configuration of common ADC parameters */ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 800672e: 687b ldr r3, [r7, #4] 8006730: 681b ldr r3, [r3, #0] 8006732: 4a06 ldr r2, [pc, #24] @ (800674c ) 8006734: 4293 cmp r3, r2 8006736: d004 beq.n 8006742 8006738: 687b ldr r3, [r7, #4] 800673a: 681b ldr r3, [r3, #0] 800673c: 4a04 ldr r2, [pc, #16] @ (8006750 ) 800673e: 4293 cmp r3, r2 8006740: d10a bne.n 8006758 8006742: 4b04 ldr r3, [pc, #16] @ (8006754 ) 8006744: e009 b.n 800675a 8006746: bf00 nop 8006748: 47ff0000 .word 0x47ff0000 800674c: 40022000 .word 0x40022000 8006750: 40022100 .word 0x40022100 8006754: 40022300 .word 0x40022300 8006758: 4b61 ldr r3, [pc, #388] @ (80068e0 ) 800675a: 4618 mov r0, r3 800675c: f7ff f916 bl 800598c 8006760: 66f8 str r0, [r7, #108] @ 0x6c /* Software is allowed to change common parameters only when all ADCs */ /* of the common group are disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8006762: 687b ldr r3, [r7, #4] 8006764: 681b ldr r3, [r3, #0] 8006766: 4a5f ldr r2, [pc, #380] @ (80068e4 ) 8006768: 4293 cmp r3, r2 800676a: d004 beq.n 8006776 800676c: 687b ldr r3, [r7, #4] 800676e: 681b ldr r3, [r3, #0] 8006770: 4a5d ldr r2, [pc, #372] @ (80068e8 ) 8006772: 4293 cmp r3, r2 8006774: d10e bne.n 8006794 8006776: 485b ldr r0, [pc, #364] @ (80068e4 ) 8006778: f7ff fa90 bl 8005c9c 800677c: 4604 mov r4, r0 800677e: 485a ldr r0, [pc, #360] @ (80068e8 ) 8006780: f7ff fa8c bl 8005c9c 8006784: 4603 mov r3, r0 8006786: 4323 orrs r3, r4 8006788: 2b00 cmp r3, #0 800678a: bf0c ite eq 800678c: 2301 moveq r3, #1 800678e: 2300 movne r3, #0 8006790: b2db uxtb r3, r3 8006792: e008 b.n 80067a6 8006794: 4855 ldr r0, [pc, #340] @ (80068ec ) 8006796: f7ff fa81 bl 8005c9c 800679a: 4603 mov r3, r0 800679c: 2b00 cmp r3, #0 800679e: bf0c ite eq 80067a0: 2301 moveq r3, #1 80067a2: 2300 movne r3, #0 80067a4: b2db uxtb r3, r3 80067a6: 2b00 cmp r3, #0 80067a8: d07d beq.n 80068a6 { /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 80067aa: 683b ldr r3, [r7, #0] 80067ac: 681b ldr r3, [r3, #0] 80067ae: 4a50 ldr r2, [pc, #320] @ (80068f0 ) 80067b0: 4293 cmp r3, r2 80067b2: d130 bne.n 8006816 80067b4: 6efb ldr r3, [r7, #108] @ 0x6c 80067b6: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80067ba: 2b00 cmp r3, #0 80067bc: d12b bne.n 8006816 { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 80067be: 687b ldr r3, [r7, #4] 80067c0: 681b ldr r3, [r3, #0] 80067c2: 4a4a ldr r2, [pc, #296] @ (80068ec ) 80067c4: 4293 cmp r3, r2 80067c6: f040 8081 bne.w 80068cc { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); 80067ca: 687b ldr r3, [r7, #4] 80067cc: 681b ldr r3, [r3, #0] 80067ce: 4a45 ldr r2, [pc, #276] @ (80068e4 ) 80067d0: 4293 cmp r3, r2 80067d2: d004 beq.n 80067de 80067d4: 687b ldr r3, [r7, #4] 80067d6: 681b ldr r3, [r3, #0] 80067d8: 4a43 ldr r2, [pc, #268] @ (80068e8 ) 80067da: 4293 cmp r3, r2 80067dc: d101 bne.n 80067e2 80067de: 4a45 ldr r2, [pc, #276] @ (80068f4 ) 80067e0: e000 b.n 80067e4 80067e2: 4a3f ldr r2, [pc, #252] @ (80068e0 ) 80067e4: 6efb ldr r3, [r7, #108] @ 0x6c 80067e6: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 80067ea: 4619 mov r1, r3 80067ec: 4610 mov r0, r2 80067ee: f7ff f8ba bl 8005966 /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 80067f2: 4b41 ldr r3, [pc, #260] @ (80068f8 ) 80067f4: 681b ldr r3, [r3, #0] 80067f6: 099b lsrs r3, r3, #6 80067f8: 4a40 ldr r2, [pc, #256] @ (80068fc ) 80067fa: fba2 2303 umull r2, r3, r2, r3 80067fe: 099b lsrs r3, r3, #6 8006800: 3301 adds r3, #1 8006802: 005b lsls r3, r3, #1 8006804: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8006806: e002 b.n 800680e { wait_loop_index--; 8006808: 68bb ldr r3, [r7, #8] 800680a: 3b01 subs r3, #1 800680c: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 800680e: 68bb ldr r3, [r7, #8] 8006810: 2b00 cmp r3, #0 8006812: d1f9 bne.n 8006808 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8006814: e05a b.n 80068cc } } } else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 8006816: 683b ldr r3, [r7, #0] 8006818: 681b ldr r3, [r3, #0] 800681a: 4a39 ldr r2, [pc, #228] @ (8006900 ) 800681c: 4293 cmp r3, r2 800681e: d11e bne.n 800685e 8006820: 6efb ldr r3, [r7, #108] @ 0x6c 8006822: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8006826: 2b00 cmp r3, #0 8006828: d119 bne.n 800685e { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 800682a: 687b ldr r3, [r7, #4] 800682c: 681b ldr r3, [r3, #0] 800682e: 4a2f ldr r2, [pc, #188] @ (80068ec ) 8006830: 4293 cmp r3, r2 8006832: d14b bne.n 80068cc { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); 8006834: 687b ldr r3, [r7, #4] 8006836: 681b ldr r3, [r3, #0] 8006838: 4a2a ldr r2, [pc, #168] @ (80068e4 ) 800683a: 4293 cmp r3, r2 800683c: d004 beq.n 8006848 800683e: 687b ldr r3, [r7, #4] 8006840: 681b ldr r3, [r3, #0] 8006842: 4a29 ldr r2, [pc, #164] @ (80068e8 ) 8006844: 4293 cmp r3, r2 8006846: d101 bne.n 800684c 8006848: 4a2a ldr r2, [pc, #168] @ (80068f4 ) 800684a: e000 b.n 800684e 800684c: 4a24 ldr r2, [pc, #144] @ (80068e0 ) 800684e: 6efb ldr r3, [r7, #108] @ 0x6c 8006850: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8006854: 4619 mov r1, r3 8006856: 4610 mov r0, r2 8006858: f7ff f885 bl 8005966 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 800685c: e036 b.n 80068cc } } else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) 800685e: 683b ldr r3, [r7, #0] 8006860: 681b ldr r3, [r3, #0] 8006862: 4a28 ldr r2, [pc, #160] @ (8006904 ) 8006864: 4293 cmp r3, r2 8006866: d131 bne.n 80068cc 8006868: 6efb ldr r3, [r7, #108] @ 0x6c 800686a: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800686e: 2b00 cmp r3, #0 8006870: d12c bne.n 80068cc { if (ADC_VREFINT_INSTANCE(hadc)) 8006872: 687b ldr r3, [r7, #4] 8006874: 681b ldr r3, [r3, #0] 8006876: 4a1d ldr r2, [pc, #116] @ (80068ec ) 8006878: 4293 cmp r3, r2 800687a: d127 bne.n 80068cc { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); 800687c: 687b ldr r3, [r7, #4] 800687e: 681b ldr r3, [r3, #0] 8006880: 4a18 ldr r2, [pc, #96] @ (80068e4 ) 8006882: 4293 cmp r3, r2 8006884: d004 beq.n 8006890 8006886: 687b ldr r3, [r7, #4] 8006888: 681b ldr r3, [r3, #0] 800688a: 4a17 ldr r2, [pc, #92] @ (80068e8 ) 800688c: 4293 cmp r3, r2 800688e: d101 bne.n 8006894 8006890: 4a18 ldr r2, [pc, #96] @ (80068f4 ) 8006892: e000 b.n 8006896 8006894: 4a12 ldr r2, [pc, #72] @ (80068e0 ) 8006896: 6efb ldr r3, [r7, #108] @ 0x6c 8006898: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 800689c: 4619 mov r1, r3 800689e: 4610 mov r0, r2 80068a0: f7ff f861 bl 8005966 80068a4: e012 b.n 80068cc /* enabled and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80068a6: 687b ldr r3, [r7, #4] 80068a8: 6d5b ldr r3, [r3, #84] @ 0x54 80068aa: f043 0220 orr.w r2, r3, #32 80068ae: 687b ldr r3, [r7, #4] 80068b0: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 80068b2: 2301 movs r3, #1 80068b4: f887 307f strb.w r3, [r7, #127] @ 0x7f 80068b8: e008 b.n 80068cc /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80068ba: 687b ldr r3, [r7, #4] 80068bc: 6d5b ldr r3, [r3, #84] @ 0x54 80068be: f043 0220 orr.w r2, r3, #32 80068c2: 687b ldr r3, [r7, #4] 80068c4: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 80068c6: 2301 movs r3, #1 80068c8: f887 307f strb.w r3, [r7, #127] @ 0x7f } /* Process unlocked */ __HAL_UNLOCK(hadc); 80068cc: 687b ldr r3, [r7, #4] 80068ce: 2200 movs r2, #0 80068d0: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 80068d4: f897 307f ldrb.w r3, [r7, #127] @ 0x7f } 80068d8: 4618 mov r0, r3 80068da: 3784 adds r7, #132 @ 0x84 80068dc: 46bd mov sp, r7 80068de: bd90 pop {r4, r7, pc} 80068e0: 58026300 .word 0x58026300 80068e4: 40022000 .word 0x40022000 80068e8: 40022100 .word 0x40022100 80068ec: 58026000 .word 0x58026000 80068f0: cb840000 .word 0xcb840000 80068f4: 40022300 .word 0x40022300 80068f8: 24000034 .word 0x24000034 80068fc: 053e2d63 .word 0x053e2d63 8006900: c7520000 .word 0xc7520000 8006904: cfb80000 .word 0xcfb80000 08006908 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { 8006908: b580 push {r7, lr} 800690a: b084 sub sp, #16 800690c: af00 add r7, sp, #0 800690e: 6078 str r0, [r7, #4] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8006910: 687b ldr r3, [r7, #4] 8006912: 681b ldr r3, [r3, #0] 8006914: 4618 mov r0, r3 8006916: f7ff f9c1 bl 8005c9c 800691a: 4603 mov r3, r0 800691c: 2b00 cmp r3, #0 800691e: d16e bne.n 80069fe { /* Check if conditions to enable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) 8006920: 687b ldr r3, [r7, #4] 8006922: 681b ldr r3, [r3, #0] 8006924: 689a ldr r2, [r3, #8] 8006926: 4b38 ldr r3, [pc, #224] @ (8006a08 ) 8006928: 4013 ands r3, r2 800692a: 2b00 cmp r3, #0 800692c: d00d beq.n 800694a { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800692e: 687b ldr r3, [r7, #4] 8006930: 6d5b ldr r3, [r3, #84] @ 0x54 8006932: f043 0210 orr.w r2, r3, #16 8006936: 687b ldr r3, [r7, #4] 8006938: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800693a: 687b ldr r3, [r7, #4] 800693c: 6d9b ldr r3, [r3, #88] @ 0x58 800693e: f043 0201 orr.w r2, r3, #1 8006942: 687b ldr r3, [r7, #4] 8006944: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006946: 2301 movs r3, #1 8006948: e05a b.n 8006a00 } /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); 800694a: 687b ldr r3, [r7, #4] 800694c: 681b ldr r3, [r3, #0] 800694e: 4618 mov r0, r3 8006950: f7ff f97c bl 8005c4c /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); 8006954: f7fe ffa2 bl 800589c 8006958: 60f8 str r0, [r7, #12] /* Poll for ADC ready flag raised except case of multimode enabled and ADC slave selected. */ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 800695a: 687b ldr r3, [r7, #4] 800695c: 681b ldr r3, [r3, #0] 800695e: 4a2b ldr r2, [pc, #172] @ (8006a0c ) 8006960: 4293 cmp r3, r2 8006962: d004 beq.n 800696e 8006964: 687b ldr r3, [r7, #4] 8006966: 681b ldr r3, [r3, #0] 8006968: 4a29 ldr r2, [pc, #164] @ (8006a10 ) 800696a: 4293 cmp r3, r2 800696c: d101 bne.n 8006972 800696e: 4b29 ldr r3, [pc, #164] @ (8006a14 ) 8006970: e000 b.n 8006974 8006972: 4b29 ldr r3, [pc, #164] @ (8006a18 ) 8006974: 4618 mov r0, r3 8006976: f7ff f90d bl 8005b94 800697a: 60b8 str r0, [r7, #8] if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 800697c: 687b ldr r3, [r7, #4] 800697e: 681b ldr r3, [r3, #0] 8006980: 4a23 ldr r2, [pc, #140] @ (8006a10 ) 8006982: 4293 cmp r3, r2 8006984: d002 beq.n 800698c 8006986: 687b ldr r3, [r7, #4] 8006988: 681b ldr r3, [r3, #0] 800698a: e000 b.n 800698e 800698c: 4b1f ldr r3, [pc, #124] @ (8006a0c ) 800698e: 687a ldr r2, [r7, #4] 8006990: 6812 ldr r2, [r2, #0] 8006992: 4293 cmp r3, r2 8006994: d02c beq.n 80069f0 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8006996: 68bb ldr r3, [r7, #8] 8006998: 2b00 cmp r3, #0 800699a: d130 bne.n 80069fe ) { while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 800699c: e028 b.n 80069f0 The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ /* Note: Test of ADC enabled required due to hardware constraint to */ /* not enable ADC if already enabled. */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 800699e: 687b ldr r3, [r7, #4] 80069a0: 681b ldr r3, [r3, #0] 80069a2: 4618 mov r0, r3 80069a4: f7ff f97a bl 8005c9c 80069a8: 4603 mov r3, r0 80069aa: 2b00 cmp r3, #0 80069ac: d104 bne.n 80069b8 { LL_ADC_Enable(hadc->Instance); 80069ae: 687b ldr r3, [r7, #4] 80069b0: 681b ldr r3, [r3, #0] 80069b2: 4618 mov r0, r3 80069b4: f7ff f94a bl 8005c4c } if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 80069b8: f7fe ff70 bl 800589c 80069bc: 4602 mov r2, r0 80069be: 68fb ldr r3, [r7, #12] 80069c0: 1ad3 subs r3, r2, r3 80069c2: 2b02 cmp r3, #2 80069c4: d914 bls.n 80069f0 { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 80069c6: 687b ldr r3, [r7, #4] 80069c8: 681b ldr r3, [r3, #0] 80069ca: 681b ldr r3, [r3, #0] 80069cc: f003 0301 and.w r3, r3, #1 80069d0: 2b01 cmp r3, #1 80069d2: d00d beq.n 80069f0 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80069d4: 687b ldr r3, [r7, #4] 80069d6: 6d5b ldr r3, [r3, #84] @ 0x54 80069d8: f043 0210 orr.w r2, r3, #16 80069dc: 687b ldr r3, [r7, #4] 80069de: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80069e0: 687b ldr r3, [r7, #4] 80069e2: 6d9b ldr r3, [r3, #88] @ 0x58 80069e4: f043 0201 orr.w r2, r3, #1 80069e8: 687b ldr r3, [r7, #4] 80069ea: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 80069ec: 2301 movs r3, #1 80069ee: e007 b.n 8006a00 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 80069f0: 687b ldr r3, [r7, #4] 80069f2: 681b ldr r3, [r3, #0] 80069f4: 681b ldr r3, [r3, #0] 80069f6: f003 0301 and.w r3, r3, #1 80069fa: 2b01 cmp r3, #1 80069fc: d1cf bne.n 800699e } } } /* Return HAL status */ return HAL_OK; 80069fe: 2300 movs r3, #0 } 8006a00: 4618 mov r0, r3 8006a02: 3710 adds r7, #16 8006a04: 46bd mov sp, r7 8006a06: bd80 pop {r7, pc} 8006a08: 8000003f .word 0x8000003f 8006a0c: 40022000 .word 0x40022000 8006a10: 40022100 .word 0x40022100 8006a14: 40022300 .word 0x40022300 8006a18: 58026300 .word 0x58026300 08006a1c : * stopped. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { 8006a1c: b580 push {r7, lr} 8006a1e: b084 sub sp, #16 8006a20: af00 add r7, sp, #0 8006a22: 6078 str r0, [r7, #4] uint32_t tickstart; const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); 8006a24: 687b ldr r3, [r7, #4] 8006a26: 681b ldr r3, [r3, #0] 8006a28: 4618 mov r0, r3 8006a2a: f7ff f94a bl 8005cc2 8006a2e: 60f8 str r0, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) 8006a30: 687b ldr r3, [r7, #4] 8006a32: 681b ldr r3, [r3, #0] 8006a34: 4618 mov r0, r3 8006a36: f7ff f931 bl 8005c9c 8006a3a: 4603 mov r3, r0 8006a3c: 2b00 cmp r3, #0 8006a3e: d047 beq.n 8006ad0 && (tmp_adc_is_disable_on_going == 0UL) 8006a40: 68fb ldr r3, [r7, #12] 8006a42: 2b00 cmp r3, #0 8006a44: d144 bne.n 8006ad0 ) { /* Check if conditions to disable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) 8006a46: 687b ldr r3, [r7, #4] 8006a48: 681b ldr r3, [r3, #0] 8006a4a: 689b ldr r3, [r3, #8] 8006a4c: f003 030d and.w r3, r3, #13 8006a50: 2b01 cmp r3, #1 8006a52: d10c bne.n 8006a6e { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); 8006a54: 687b ldr r3, [r7, #4] 8006a56: 681b ldr r3, [r3, #0] 8006a58: 4618 mov r0, r3 8006a5a: f7ff f90b bl 8005c74 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); 8006a5e: 687b ldr r3, [r7, #4] 8006a60: 681b ldr r3, [r3, #0] 8006a62: 2203 movs r2, #3 8006a64: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); 8006a66: f7fe ff19 bl 800589c 8006a6a: 60b8 str r0, [r7, #8] while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8006a6c: e029 b.n 8006ac2 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006a6e: 687b ldr r3, [r7, #4] 8006a70: 6d5b ldr r3, [r3, #84] @ 0x54 8006a72: f043 0210 orr.w r2, r3, #16 8006a76: 687b ldr r3, [r7, #4] 8006a78: 655a str r2, [r3, #84] @ 0x54 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006a7a: 687b ldr r3, [r7, #4] 8006a7c: 6d9b ldr r3, [r3, #88] @ 0x58 8006a7e: f043 0201 orr.w r2, r3, #1 8006a82: 687b ldr r3, [r7, #4] 8006a84: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006a86: 2301 movs r3, #1 8006a88: e023 b.n 8006ad2 { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8006a8a: f7fe ff07 bl 800589c 8006a8e: 4602 mov r2, r0 8006a90: 68bb ldr r3, [r7, #8] 8006a92: 1ad3 subs r3, r2, r3 8006a94: 2b02 cmp r3, #2 8006a96: d914 bls.n 8006ac2 { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8006a98: 687b ldr r3, [r7, #4] 8006a9a: 681b ldr r3, [r3, #0] 8006a9c: 689b ldr r3, [r3, #8] 8006a9e: f003 0301 and.w r3, r3, #1 8006aa2: 2b00 cmp r3, #0 8006aa4: d00d beq.n 8006ac2 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006aa6: 687b ldr r3, [r7, #4] 8006aa8: 6d5b ldr r3, [r3, #84] @ 0x54 8006aaa: f043 0210 orr.w r2, r3, #16 8006aae: 687b ldr r3, [r7, #4] 8006ab0: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006ab2: 687b ldr r3, [r7, #4] 8006ab4: 6d9b ldr r3, [r3, #88] @ 0x58 8006ab6: f043 0201 orr.w r2, r3, #1 8006aba: 687b ldr r3, [r7, #4] 8006abc: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006abe: 2301 movs r3, #1 8006ac0: e007 b.n 8006ad2 while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8006ac2: 687b ldr r3, [r7, #4] 8006ac4: 681b ldr r3, [r3, #0] 8006ac6: 689b ldr r3, [r3, #8] 8006ac8: f003 0301 and.w r3, r3, #1 8006acc: 2b00 cmp r3, #0 8006ace: d1dc bne.n 8006a8a } } } /* Return HAL status */ return HAL_OK; 8006ad0: 2300 movs r3, #0 } 8006ad2: 4618 mov r0, r3 8006ad4: 3710 adds r7, #16 8006ad6: 46bd mov sp, r7 8006ad8: bd80 pop {r7, pc} 08006ada : * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 8006ada: b580 push {r7, lr} 8006adc: b084 sub sp, #16 8006ade: af00 add r7, sp, #0 8006ae0: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006ae2: 687b ldr r3, [r7, #4] 8006ae4: 6b9b ldr r3, [r3, #56] @ 0x38 8006ae6: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) 8006ae8: 68fb ldr r3, [r7, #12] 8006aea: 6d5b ldr r3, [r3, #84] @ 0x54 8006aec: f003 0350 and.w r3, r3, #80 @ 0x50 8006af0: 2b00 cmp r3, #0 8006af2: d14b bne.n 8006b8c { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8006af4: 68fb ldr r3, [r7, #12] 8006af6: 6d5b ldr r3, [r3, #84] @ 0x54 8006af8: f443 7200 orr.w r2, r3, #512 @ 0x200 8006afc: 68fb ldr r3, [r7, #12] 8006afe: 655a str r2, [r3, #84] @ 0x54 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ /* Is it the end of the regular sequence ? */ if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) 8006b00: 68fb ldr r3, [r7, #12] 8006b02: 681b ldr r3, [r3, #0] 8006b04: 681b ldr r3, [r3, #0] 8006b06: f003 0308 and.w r3, r3, #8 8006b0a: 2b00 cmp r3, #0 8006b0c: d021 beq.n 8006b52 { /* Are conversions software-triggered ? */ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) 8006b0e: 68fb ldr r3, [r7, #12] 8006b10: 681b ldr r3, [r3, #0] 8006b12: 4618 mov r0, r3 8006b14: f7fe ff9c bl 8005a50 8006b18: 4603 mov r3, r0 8006b1a: 2b00 cmp r3, #0 8006b1c: d032 beq.n 8006b84 { /* Is CONT bit set ? */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) 8006b1e: 68fb ldr r3, [r7, #12] 8006b20: 681b ldr r3, [r3, #0] 8006b22: 68db ldr r3, [r3, #12] 8006b24: f403 5300 and.w r3, r3, #8192 @ 0x2000 8006b28: 2b00 cmp r3, #0 8006b2a: d12b bne.n 8006b84 { /* CONT bit is not set, no more conversions expected */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8006b2c: 68fb ldr r3, [r7, #12] 8006b2e: 6d5b ldr r3, [r3, #84] @ 0x54 8006b30: f423 7280 bic.w r2, r3, #256 @ 0x100 8006b34: 68fb ldr r3, [r7, #12] 8006b36: 655a str r2, [r3, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 8006b38: 68fb ldr r3, [r7, #12] 8006b3a: 6d5b ldr r3, [r3, #84] @ 0x54 8006b3c: f403 5380 and.w r3, r3, #4096 @ 0x1000 8006b40: 2b00 cmp r3, #0 8006b42: d11f bne.n 8006b84 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8006b44: 68fb ldr r3, [r7, #12] 8006b46: 6d5b ldr r3, [r3, #84] @ 0x54 8006b48: f043 0201 orr.w r2, r3, #1 8006b4c: 68fb ldr r3, [r7, #12] 8006b4e: 655a str r2, [r3, #84] @ 0x54 8006b50: e018 b.n 8006b84 } else { /* DMA End of Transfer interrupt was triggered but conversions sequence is not over. If DMACFG is set to 0, conversions are stopped. */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL) 8006b52: 68fb ldr r3, [r7, #12] 8006b54: 681b ldr r3, [r3, #0] 8006b56: 68db ldr r3, [r3, #12] 8006b58: f003 0303 and.w r3, r3, #3 8006b5c: 2b00 cmp r3, #0 8006b5e: d111 bne.n 8006b84 { /* DMACFG bit is not set, conversions are stopped. */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8006b60: 68fb ldr r3, [r7, #12] 8006b62: 6d5b ldr r3, [r3, #84] @ 0x54 8006b64: f423 7280 bic.w r2, r3, #256 @ 0x100 8006b68: 68fb ldr r3, [r7, #12] 8006b6a: 655a str r2, [r3, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 8006b6c: 68fb ldr r3, [r7, #12] 8006b6e: 6d5b ldr r3, [r3, #84] @ 0x54 8006b70: f403 5380 and.w r3, r3, #4096 @ 0x1000 8006b74: 2b00 cmp r3, #0 8006b76: d105 bne.n 8006b84 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8006b78: 68fb ldr r3, [r7, #12] 8006b7a: 6d5b ldr r3, [r3, #84] @ 0x54 8006b7c: f043 0201 orr.w r2, r3, #1 8006b80: 68fb ldr r3, [r7, #12] 8006b82: 655a str r2, [r3, #84] @ 0x54 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 8006b84: 68f8 ldr r0, [r7, #12] 8006b86: f7fa fde5 bl 8001754 { /* Call ADC DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } } 8006b8a: e00e b.n 8006baa if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) 8006b8c: 68fb ldr r3, [r7, #12] 8006b8e: 6d5b ldr r3, [r3, #84] @ 0x54 8006b90: f003 0310 and.w r3, r3, #16 8006b94: 2b00 cmp r3, #0 8006b96: d003 beq.n 8006ba0 HAL_ADC_ErrorCallback(hadc); 8006b98: 68f8 ldr r0, [r7, #12] 8006b9a: f7ff fb4f bl 800623c } 8006b9e: e004 b.n 8006baa hadc->DMA_Handle->XferErrorCallback(hdma); 8006ba0: 68fb ldr r3, [r7, #12] 8006ba2: 6cdb ldr r3, [r3, #76] @ 0x4c 8006ba4: 6cdb ldr r3, [r3, #76] @ 0x4c 8006ba6: 6878 ldr r0, [r7, #4] 8006ba8: 4798 blx r3 } 8006baa: bf00 nop 8006bac: 3710 adds r7, #16 8006bae: 46bd mov sp, r7 8006bb0: bd80 pop {r7, pc} 08006bb2 : * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 8006bb2: b580 push {r7, lr} 8006bb4: b084 sub sp, #16 8006bb6: af00 add r7, sp, #0 8006bb8: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006bba: 687b ldr r3, [r7, #4] 8006bbc: 6b9b ldr r3, [r3, #56] @ 0x38 8006bbe: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 8006bc0: 68f8 ldr r0, [r7, #12] 8006bc2: f7ff fb31 bl 8006228 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8006bc6: bf00 nop 8006bc8: 3710 adds r7, #16 8006bca: 46bd mov sp, r7 8006bcc: bd80 pop {r7, pc} 08006bce : * @brief DMA error callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 8006bce: b580 push {r7, lr} 8006bd0: b084 sub sp, #16 8006bd2: af00 add r7, sp, #0 8006bd4: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006bd6: 687b ldr r3, [r7, #4] 8006bd8: 6b9b ldr r3, [r3, #56] @ 0x38 8006bda: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 8006bdc: 68fb ldr r3, [r7, #12] 8006bde: 6d5b ldr r3, [r3, #84] @ 0x54 8006be0: f043 0240 orr.w r2, r3, #64 @ 0x40 8006be4: 68fb ldr r3, [r7, #12] 8006be6: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 8006be8: 68fb ldr r3, [r7, #12] 8006bea: 6d9b ldr r3, [r3, #88] @ 0x58 8006bec: f043 0204 orr.w r2, r3, #4 8006bf0: 68fb ldr r3, [r7, #12] 8006bf2: 659a str r2, [r3, #88] @ 0x58 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 8006bf4: 68f8 ldr r0, [r7, #12] 8006bf6: f7ff fb21 bl 800623c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8006bfa: bf00 nop 8006bfc: 3710 adds r7, #16 8006bfe: 46bd mov sp, r7 8006c00: bd80 pop {r7, pc} ... 08006c04 : * stopped. * @param hadc ADC handle * @retval None. */ void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc) { 8006c04: b580 push {r7, lr} 8006c06: b084 sub sp, #16 8006c08: af00 add r7, sp, #0 8006c0a: 6078 str r0, [r7, #4] uint32_t freq; if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc)) 8006c0c: 687b ldr r3, [r7, #4] 8006c0e: 681b ldr r3, [r3, #0] 8006c10: 4a7a ldr r2, [pc, #488] @ (8006dfc ) 8006c12: 4293 cmp r3, r2 8006c14: d004 beq.n 8006c20 8006c16: 687b ldr r3, [r7, #4] 8006c18: 681b ldr r3, [r3, #0] 8006c1a: 4a79 ldr r2, [pc, #484] @ (8006e00 ) 8006c1c: 4293 cmp r3, r2 8006c1e: d109 bne.n 8006c34 8006c20: 4b78 ldr r3, [pc, #480] @ (8006e04 ) 8006c22: 689b ldr r3, [r3, #8] 8006c24: f403 3340 and.w r3, r3, #196608 @ 0x30000 8006c28: 2b00 cmp r3, #0 8006c2a: bf14 ite ne 8006c2c: 2301 movne r3, #1 8006c2e: 2300 moveq r3, #0 8006c30: b2db uxtb r3, r3 8006c32: e008 b.n 8006c46 8006c34: 4b74 ldr r3, [pc, #464] @ (8006e08 ) 8006c36: 689b ldr r3, [r3, #8] 8006c38: f403 3340 and.w r3, r3, #196608 @ 0x30000 8006c3c: 2b00 cmp r3, #0 8006c3e: bf14 ite ne 8006c40: 2301 movne r3, #1 8006c42: 2300 moveq r3, #0 8006c44: b2db uxtb r3, r3 8006c46: 2b00 cmp r3, #0 8006c48: d01c beq.n 8006c84 { freq = HAL_RCC_GetHCLKFreq(); 8006c4a: f005 fc39 bl 800c4c0 8006c4e: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 8006c50: 687b ldr r3, [r7, #4] 8006c52: 685b ldr r3, [r3, #4] 8006c54: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8006c58: d010 beq.n 8006c7c 8006c5a: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8006c5e: d873 bhi.n 8006d48 8006c60: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8006c64: d002 beq.n 8006c6c 8006c66: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8006c6a: d16d bne.n 8006d48 { case ADC_CLOCK_SYNC_PCLK_DIV1: case ADC_CLOCK_SYNC_PCLK_DIV2: freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos); 8006c6c: 687b ldr r3, [r7, #4] 8006c6e: 685b ldr r3, [r3, #4] 8006c70: 0c1b lsrs r3, r3, #16 8006c72: 68fa ldr r2, [r7, #12] 8006c74: fbb2 f3f3 udiv r3, r2, r3 8006c78: 60fb str r3, [r7, #12] break; 8006c7a: e068 b.n 8006d4e case ADC_CLOCK_SYNC_PCLK_DIV4: freq /= 4UL; 8006c7c: 68fb ldr r3, [r7, #12] 8006c7e: 089b lsrs r3, r3, #2 8006c80: 60fb str r3, [r7, #12] break; 8006c82: e064 b.n 8006d4e break; } } else { freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC); 8006c84: f44f 2000 mov.w r0, #524288 @ 0x80000 8006c88: f04f 0100 mov.w r1, #0 8006c8c: f006 fea4 bl 800d9d8 8006c90: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 8006c92: 687b ldr r3, [r7, #4] 8006c94: 685b ldr r3, [r3, #4] 8006c96: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 8006c9a: d051 beq.n 8006d40 8006c9c: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 8006ca0: d854 bhi.n 8006d4c 8006ca2: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 8006ca6: d047 beq.n 8006d38 8006ca8: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 8006cac: d84e bhi.n 8006d4c 8006cae: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 8006cb2: d03d beq.n 8006d30 8006cb4: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 8006cb8: d848 bhi.n 8006d4c 8006cba: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8006cbe: d033 beq.n 8006d28 8006cc0: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8006cc4: d842 bhi.n 8006d4c 8006cc6: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 8006cca: d029 beq.n 8006d20 8006ccc: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 8006cd0: d83c bhi.n 8006d4c 8006cd2: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 8006cd6: d01a beq.n 8006d0e 8006cd8: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 8006cdc: d836 bhi.n 8006d4c 8006cde: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 8006ce2: d014 beq.n 8006d0e 8006ce4: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 8006ce8: d830 bhi.n 8006d4c 8006cea: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8006cee: d00e beq.n 8006d0e 8006cf0: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8006cf4: d82a bhi.n 8006d4c 8006cf6: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8006cfa: d008 beq.n 8006d0e 8006cfc: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8006d00: d824 bhi.n 8006d4c 8006d02: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8006d06: d002 beq.n 8006d0e 8006d08: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 8006d0c: d11e bne.n 8006d4c case ADC_CLOCK_ASYNC_DIV4: case ADC_CLOCK_ASYNC_DIV6: case ADC_CLOCK_ASYNC_DIV8: case ADC_CLOCK_ASYNC_DIV10: case ADC_CLOCK_ASYNC_DIV12: freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL); 8006d0e: 687b ldr r3, [r7, #4] 8006d10: 685b ldr r3, [r3, #4] 8006d12: 0c9b lsrs r3, r3, #18 8006d14: 005b lsls r3, r3, #1 8006d16: 68fa ldr r2, [r7, #12] 8006d18: fbb2 f3f3 udiv r3, r2, r3 8006d1c: 60fb str r3, [r7, #12] break; 8006d1e: e016 b.n 8006d4e case ADC_CLOCK_ASYNC_DIV16: freq /= 16UL; 8006d20: 68fb ldr r3, [r7, #12] 8006d22: 091b lsrs r3, r3, #4 8006d24: 60fb str r3, [r7, #12] break; 8006d26: e012 b.n 8006d4e case ADC_CLOCK_ASYNC_DIV32: freq /= 32UL; 8006d28: 68fb ldr r3, [r7, #12] 8006d2a: 095b lsrs r3, r3, #5 8006d2c: 60fb str r3, [r7, #12] break; 8006d2e: e00e b.n 8006d4e case ADC_CLOCK_ASYNC_DIV64: freq /= 64UL; 8006d30: 68fb ldr r3, [r7, #12] 8006d32: 099b lsrs r3, r3, #6 8006d34: 60fb str r3, [r7, #12] break; 8006d36: e00a b.n 8006d4e case ADC_CLOCK_ASYNC_DIV128: freq /= 128UL; 8006d38: 68fb ldr r3, [r7, #12] 8006d3a: 09db lsrs r3, r3, #7 8006d3c: 60fb str r3, [r7, #12] break; 8006d3e: e006 b.n 8006d4e case ADC_CLOCK_ASYNC_DIV256: freq /= 256UL; 8006d40: 68fb ldr r3, [r7, #12] 8006d42: 0a1b lsrs r3, r3, #8 8006d44: 60fb str r3, [r7, #12] break; 8006d46: e002 b.n 8006d4e break; 8006d48: bf00 nop 8006d4a: e000 b.n 8006d4e default: break; 8006d4c: bf00 nop else /* if(freq > 25000000UL) */ { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } #else if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */ 8006d4e: f7fe fdb1 bl 80058b4 8006d52: 4603 mov r3, r0 8006d54: f241 0203 movw r2, #4099 @ 0x1003 8006d58: 4293 cmp r3, r2 8006d5a: d815 bhi.n 8006d88 { if (freq > 20000000UL) 8006d5c: 68fb ldr r3, [r7, #12] 8006d5e: 4a2b ldr r2, [pc, #172] @ (8006e0c ) 8006d60: 4293 cmp r3, r2 8006d62: d908 bls.n 8006d76 { SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 8006d64: 687b ldr r3, [r7, #4] 8006d66: 681b ldr r3, [r3, #0] 8006d68: 689a ldr r2, [r3, #8] 8006d6a: 687b ldr r3, [r7, #4] 8006d6c: 681b ldr r3, [r3, #0] 8006d6e: f442 7280 orr.w r2, r2, #256 @ 0x100 8006d72: 609a str r2, [r3, #8] { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } } #endif /* ADC_VER_V5_3 */ } 8006d74: e03e b.n 8006df4 CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 8006d76: 687b ldr r3, [r7, #4] 8006d78: 681b ldr r3, [r3, #0] 8006d7a: 689a ldr r2, [r3, #8] 8006d7c: 687b ldr r3, [r7, #4] 8006d7e: 681b ldr r3, [r3, #0] 8006d80: f422 7280 bic.w r2, r2, #256 @ 0x100 8006d84: 609a str r2, [r3, #8] } 8006d86: e035 b.n 8006df4 freq /= 2U; /* divider by 2 for Rev.V */ 8006d88: 68fb ldr r3, [r7, #12] 8006d8a: 085b lsrs r3, r3, #1 8006d8c: 60fb str r3, [r7, #12] if (freq <= 6250000UL) 8006d8e: 68fb ldr r3, [r7, #12] 8006d90: 4a1f ldr r2, [pc, #124] @ (8006e10 ) 8006d92: 4293 cmp r3, r2 8006d94: d808 bhi.n 8006da8 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL); 8006d96: 687b ldr r3, [r7, #4] 8006d98: 681b ldr r3, [r3, #0] 8006d9a: 689a ldr r2, [r3, #8] 8006d9c: 687b ldr r3, [r7, #4] 8006d9e: 681b ldr r3, [r3, #0] 8006da0: f422 7240 bic.w r2, r2, #768 @ 0x300 8006da4: 609a str r2, [r3, #8] } 8006da6: e025 b.n 8006df4 else if (freq <= 12500000UL) 8006da8: 68fb ldr r3, [r7, #12] 8006daa: 4a1a ldr r2, [pc, #104] @ (8006e14 ) 8006dac: 4293 cmp r3, r2 8006dae: d80a bhi.n 8006dc6 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0); 8006db0: 687b ldr r3, [r7, #4] 8006db2: 681b ldr r3, [r3, #0] 8006db4: 689b ldr r3, [r3, #8] 8006db6: f423 7240 bic.w r2, r3, #768 @ 0x300 8006dba: 687b ldr r3, [r7, #4] 8006dbc: 681b ldr r3, [r3, #0] 8006dbe: f442 7280 orr.w r2, r2, #256 @ 0x100 8006dc2: 609a str r2, [r3, #8] } 8006dc4: e016 b.n 8006df4 else if (freq <= 25000000UL) 8006dc6: 68fb ldr r3, [r7, #12] 8006dc8: 4a13 ldr r2, [pc, #76] @ (8006e18 ) 8006dca: 4293 cmp r3, r2 8006dcc: d80a bhi.n 8006de4 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1); 8006dce: 687b ldr r3, [r7, #4] 8006dd0: 681b ldr r3, [r3, #0] 8006dd2: 689b ldr r3, [r3, #8] 8006dd4: f423 7240 bic.w r2, r3, #768 @ 0x300 8006dd8: 687b ldr r3, [r7, #4] 8006dda: 681b ldr r3, [r3, #0] 8006ddc: f442 7200 orr.w r2, r2, #512 @ 0x200 8006de0: 609a str r2, [r3, #8] } 8006de2: e007 b.n 8006df4 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); 8006de4: 687b ldr r3, [r7, #4] 8006de6: 681b ldr r3, [r3, #0] 8006de8: 689a ldr r2, [r3, #8] 8006dea: 687b ldr r3, [r7, #4] 8006dec: 681b ldr r3, [r3, #0] 8006dee: f442 7240 orr.w r2, r2, #768 @ 0x300 8006df2: 609a str r2, [r3, #8] } 8006df4: bf00 nop 8006df6: 3710 adds r7, #16 8006df8: 46bd mov sp, r7 8006dfa: bd80 pop {r7, pc} 8006dfc: 40022000 .word 0x40022000 8006e00: 40022100 .word 0x40022100 8006e04: 40022300 .word 0x40022300 8006e08: 58026300 .word 0x58026300 8006e0c: 01312d00 .word 0x01312d00 8006e10: 005f5e10 .word 0x005f5e10 8006e14: 00bebc20 .word 0x00bebc20 8006e18: 017d7840 .word 0x017d7840 08006e1c : { 8006e1c: b480 push {r7} 8006e1e: b083 sub sp, #12 8006e20: af00 add r7, sp, #0 8006e22: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8006e24: 687b ldr r3, [r7, #4] 8006e26: 689b ldr r3, [r3, #8] 8006e28: f003 0301 and.w r3, r3, #1 8006e2c: 2b01 cmp r3, #1 8006e2e: d101 bne.n 8006e34 8006e30: 2301 movs r3, #1 8006e32: e000 b.n 8006e36 8006e34: 2300 movs r3, #0 } 8006e36: 4618 mov r0, r3 8006e38: 370c adds r7, #12 8006e3a: 46bd mov sp, r7 8006e3c: f85d 7b04 ldr.w r7, [sp], #4 8006e40: 4770 bx lr ... 08006e44 : { 8006e44: b480 push {r7} 8006e46: b085 sub sp, #20 8006e48: af00 add r7, sp, #0 8006e4a: 60f8 str r0, [r7, #12] 8006e4c: 60b9 str r1, [r7, #8] 8006e4e: 607a str r2, [r7, #4] MODIFY_REG(ADCx->CR, 8006e50: 68fb ldr r3, [r7, #12] 8006e52: 689a ldr r2, [r3, #8] 8006e54: 4b09 ldr r3, [pc, #36] @ (8006e7c ) 8006e56: 4013 ands r3, r2 8006e58: 68ba ldr r2, [r7, #8] 8006e5a: f402 3180 and.w r1, r2, #65536 @ 0x10000 8006e5e: 687a ldr r2, [r7, #4] 8006e60: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 8006e64: 430a orrs r2, r1 8006e66: 4313 orrs r3, r2 8006e68: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 8006e6c: 68fb ldr r3, [r7, #12] 8006e6e: 609a str r2, [r3, #8] } 8006e70: bf00 nop 8006e72: 3714 adds r7, #20 8006e74: 46bd mov sp, r7 8006e76: f85d 7b04 ldr.w r7, [sp], #4 8006e7a: 4770 bx lr 8006e7c: 3ffeffc0 .word 0x3ffeffc0 08006e80 : { 8006e80: b480 push {r7} 8006e82: b083 sub sp, #12 8006e84: af00 add r7, sp, #0 8006e86: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); 8006e88: 687b ldr r3, [r7, #4] 8006e8a: 689b ldr r3, [r3, #8] 8006e8c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8006e90: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8006e94: d101 bne.n 8006e9a 8006e96: 2301 movs r3, #1 8006e98: e000 b.n 8006e9c 8006e9a: 2300 movs r3, #0 } 8006e9c: 4618 mov r0, r3 8006e9e: 370c adds r7, #12 8006ea0: 46bd mov sp, r7 8006ea2: f85d 7b04 ldr.w r7, [sp], #4 8006ea6: 4770 bx lr 08006ea8 : { 8006ea8: b480 push {r7} 8006eaa: b083 sub sp, #12 8006eac: af00 add r7, sp, #0 8006eae: 6078 str r0, [r7, #4] MODIFY_REG(ADCx->CR, 8006eb0: 687b ldr r3, [r7, #4] 8006eb2: 689a ldr r2, [r3, #8] 8006eb4: 4b05 ldr r3, [pc, #20] @ (8006ecc ) 8006eb6: 4013 ands r3, r2 8006eb8: f043 0204 orr.w r2, r3, #4 8006ebc: 687b ldr r3, [r7, #4] 8006ebe: 609a str r2, [r3, #8] } 8006ec0: bf00 nop 8006ec2: 370c adds r7, #12 8006ec4: 46bd mov sp, r7 8006ec6: f85d 7b04 ldr.w r7, [sp], #4 8006eca: 4770 bx lr 8006ecc: 7fffffc0 .word 0x7fffffc0 08006ed0 : { 8006ed0: b480 push {r7} 8006ed2: b083 sub sp, #12 8006ed4: af00 add r7, sp, #0 8006ed6: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8006ed8: 687b ldr r3, [r7, #4] 8006eda: 689b ldr r3, [r3, #8] 8006edc: f003 0304 and.w r3, r3, #4 8006ee0: 2b04 cmp r3, #4 8006ee2: d101 bne.n 8006ee8 8006ee4: 2301 movs r3, #1 8006ee6: e000 b.n 8006eea 8006ee8: 2300 movs r3, #0 } 8006eea: 4618 mov r0, r3 8006eec: 370c adds r7, #12 8006eee: 46bd mov sp, r7 8006ef0: f85d 7b04 ldr.w r7, [sp], #4 8006ef4: 4770 bx lr ... 08006ef8 : * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff) { 8006ef8: b580 push {r7, lr} 8006efa: b086 sub sp, #24 8006efc: af00 add r7, sp, #0 8006efe: 60f8 str r0, [r7, #12] 8006f00: 60b9 str r1, [r7, #8] 8006f02: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; 8006f04: 2300 movs r3, #0 8006f06: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Process locked */ __HAL_LOCK(hadc); 8006f08: 68fb ldr r3, [r7, #12] 8006f0a: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8006f0e: 2b01 cmp r3, #1 8006f10: d101 bne.n 8006f16 8006f12: 2302 movs r3, #2 8006f14: e04c b.n 8006fb0 8006f16: 68fb ldr r3, [r7, #12] 8006f18: 2201 movs r2, #1 8006f1a: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Calibration prerequisite: ADC must be disabled. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); 8006f1e: 68f8 ldr r0, [r7, #12] 8006f20: f7ff fd7c bl 8006a1c 8006f24: 4603 mov r3, r0 8006f26: 75fb strb r3, [r7, #23] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8006f28: 7dfb ldrb r3, [r7, #23] 8006f2a: 2b00 cmp r3, #0 8006f2c: d135 bne.n 8006f9a { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8006f2e: 68fb ldr r3, [r7, #12] 8006f30: 6d5a ldr r2, [r3, #84] @ 0x54 8006f32: 4b21 ldr r3, [pc, #132] @ (8006fb8 ) 8006f34: 4013 ands r3, r2 8006f36: f043 0202 orr.w r2, r3, #2 8006f3a: 68fb ldr r3, [r7, #12] 8006f3c: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Start ADC calibration in mode single-ended or differential */ LL_ADC_StartCalibration(hadc->Instance, CalibrationMode, SingleDiff); 8006f3e: 68fb ldr r3, [r7, #12] 8006f40: 681b ldr r3, [r3, #0] 8006f42: 687a ldr r2, [r7, #4] 8006f44: 68b9 ldr r1, [r7, #8] 8006f46: 4618 mov r0, r3 8006f48: f7ff ff7c bl 8006e44 /* Wait for calibration completion */ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 8006f4c: e014 b.n 8006f78 { wait_loop_index++; 8006f4e: 693b ldr r3, [r7, #16] 8006f50: 3301 adds r3, #1 8006f52: 613b str r3, [r7, #16] if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) 8006f54: 693b ldr r3, [r7, #16] 8006f56: 4a19 ldr r2, [pc, #100] @ (8006fbc ) 8006f58: 4293 cmp r3, r2 8006f5a: d30d bcc.n 8006f78 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8006f5c: 68fb ldr r3, [r7, #12] 8006f5e: 6d5b ldr r3, [r3, #84] @ 0x54 8006f60: f023 0312 bic.w r3, r3, #18 8006f64: f043 0210 orr.w r2, r3, #16 8006f68: 68fb ldr r3, [r7, #12] 8006f6a: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 8006f6c: 68fb ldr r3, [r7, #12] 8006f6e: 2200 movs r2, #0 8006f70: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 8006f74: 2301 movs r3, #1 8006f76: e01b b.n 8006fb0 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 8006f78: 68fb ldr r3, [r7, #12] 8006f7a: 681b ldr r3, [r3, #0] 8006f7c: 4618 mov r0, r3 8006f7e: f7ff ff7f bl 8006e80 8006f82: 4603 mov r3, r0 8006f84: 2b00 cmp r3, #0 8006f86: d1e2 bne.n 8006f4e } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8006f88: 68fb ldr r3, [r7, #12] 8006f8a: 6d5b ldr r3, [r3, #84] @ 0x54 8006f8c: f023 0303 bic.w r3, r3, #3 8006f90: f043 0201 orr.w r2, r3, #1 8006f94: 68fb ldr r3, [r7, #12] 8006f96: 655a str r2, [r3, #84] @ 0x54 8006f98: e005 b.n 8006fa6 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006f9a: 68fb ldr r3, [r7, #12] 8006f9c: 6d5b ldr r3, [r3, #84] @ 0x54 8006f9e: f043 0210 orr.w r2, r3, #16 8006fa2: 68fb ldr r3, [r7, #12] 8006fa4: 655a str r2, [r3, #84] @ 0x54 /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } /* Process unlocked */ __HAL_UNLOCK(hadc); 8006fa6: 68fb ldr r3, [r7, #12] 8006fa8: 2200 movs r2, #0 8006faa: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 8006fae: 7dfb ldrb r3, [r7, #23] } 8006fb0: 4618 mov r0, r3 8006fb2: 3718 adds r7, #24 8006fb4: 46bd mov sp, r7 8006fb6: bd80 pop {r7, pc} 8006fb8: ffffeefd .word 0xffffeefd 8006fbc: 25c3f800 .word 0x25c3f800 08006fc0 : * @param pData Destination Buffer address. * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes). * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { 8006fc0: b580 push {r7, lr} 8006fc2: b0a0 sub sp, #128 @ 0x80 8006fc4: af00 add r7, sp, #0 8006fc6: 60f8 str r0, [r7, #12] 8006fc8: 60b9 str r1, [r7, #8] 8006fca: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) 8006fcc: 68fb ldr r3, [r7, #12] 8006fce: 681b ldr r3, [r3, #0] 8006fd0: 4618 mov r0, r3 8006fd2: f7ff ff7d bl 8006ed0 8006fd6: 4603 mov r3, r0 8006fd8: 2b00 cmp r3, #0 8006fda: d001 beq.n 8006fe0 { return HAL_BUSY; 8006fdc: 2302 movs r3, #2 8006fde: e0b9 b.n 8007154 } else { /* Process locked */ __HAL_LOCK(hadc); 8006fe0: 68fb ldr r3, [r7, #12] 8006fe2: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8006fe6: 2b01 cmp r3, #1 8006fe8: d101 bne.n 8006fee 8006fea: 2302 movs r3, #2 8006fec: e0b2 b.n 8007154 8006fee: 68fb ldr r3, [r7, #12] 8006ff0: 2201 movs r2, #1 8006ff2: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Case of ADC slave using its own DMA channel: check whether handle selected corresponds to ADC master or slave instance */ if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance) 8006ff6: 68fb ldr r3, [r7, #12] 8006ff8: 681b ldr r3, [r3, #0] 8006ffa: 4a58 ldr r2, [pc, #352] @ (800715c ) 8006ffc: 4293 cmp r3, r2 8006ffe: d002 beq.n 8007006 8007000: 68fb ldr r3, [r7, #12] 8007002: 681b ldr r3, [r3, #0] 8007004: e000 b.n 8007008 8007006: 4b56 ldr r3, [pc, #344] @ (8007160 ) 8007008: 68fa ldr r2, [r7, #12] 800700a: 6812 ldr r2, [r2, #0] 800700c: 4293 cmp r3, r2 800700e: d006 beq.n 800701e { /* Case of ADC slave selected: enable ADC instance */ tmp_hal_status = ADC_Enable(hadc); 8007010: 68f8 ldr r0, [r7, #12] 8007012: f7ff fc79 bl 8006908 8007016: 4603 mov r3, r0 8007018: f887 307f strb.w r3, [r7, #127] @ 0x7f 800701c: e02e b.n 800707c } else { tmphadcSlave.State = HAL_ADC_STATE_RESET; 800701e: 2300 movs r3, #0 8007020: 66bb str r3, [r7, #104] @ 0x68 tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; 8007022: 2300 movs r3, #0 8007024: 66fb str r3, [r7, #108] @ 0x6c /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 8007026: 68fb ldr r3, [r7, #12] 8007028: 681b ldr r3, [r3, #0] 800702a: 4a4d ldr r2, [pc, #308] @ (8007160 ) 800702c: 4293 cmp r3, r2 800702e: d102 bne.n 8007036 8007030: 4b4a ldr r3, [pc, #296] @ (800715c ) 8007032: 617b str r3, [r7, #20] 8007034: e001 b.n 800703a 8007036: 2300 movs r3, #0 8007038: 617b str r3, [r7, #20] if (tmphadcSlave.Instance == NULL) 800703a: 697b ldr r3, [r7, #20] 800703c: 2b00 cmp r3, #0 800703e: d10b bne.n 8007058 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8007040: 68fb ldr r3, [r7, #12] 8007042: 6d5b ldr r3, [r3, #84] @ 0x54 8007044: f043 0220 orr.w r2, r3, #32 8007048: 68fb ldr r3, [r7, #12] 800704a: 655a str r2, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hadc); 800704c: 68fb ldr r3, [r7, #12] 800704e: 2200 movs r2, #0 8007050: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 8007054: 2301 movs r3, #1 8007056: e07d b.n 8007154 } /* Enable the ADC peripherals: master and slave (in case if not already */ /* enabled previously) */ tmp_hal_status = ADC_Enable(hadc); 8007058: 68f8 ldr r0, [r7, #12] 800705a: f7ff fc55 bl 8006908 800705e: 4603 mov r3, r0 8007060: f887 307f strb.w r3, [r7, #127] @ 0x7f if (tmp_hal_status == HAL_OK) 8007064: f897 307f ldrb.w r3, [r7, #127] @ 0x7f 8007068: 2b00 cmp r3, #0 800706a: d107 bne.n 800707c { tmp_hal_status = ADC_Enable(&tmphadcSlave); 800706c: f107 0314 add.w r3, r7, #20 8007070: 4618 mov r0, r3 8007072: f7ff fc49 bl 8006908 8007076: 4603 mov r3, r0 8007078: f887 307f strb.w r3, [r7, #127] @ 0x7f } } /* Start multimode conversion of ADCs pair */ if (tmp_hal_status == HAL_OK) 800707c: f897 307f ldrb.w r3, [r7, #127] @ 0x7f 8007080: 2b00 cmp r3, #0 8007082: d161 bne.n 8007148 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8007084: 68fb ldr r3, [r7, #12] 8007086: 6d5a ldr r2, [r3, #84] @ 0x54 8007088: 4b36 ldr r3, [pc, #216] @ (8007164 ) 800708a: 4013 ands r3, r2 800708c: f443 7280 orr.w r2, r3, #256 @ 0x100 8007090: 68fb ldr r3, [r7, #12] 8007092: 655a str r2, [r3, #84] @ 0x54 (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY); /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8007094: 68fb ldr r3, [r7, #12] 8007096: 2200 movs r2, #0 8007098: 659a str r2, [r3, #88] @ 0x58 /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 800709a: 68fb ldr r3, [r7, #12] 800709c: 6cdb ldr r3, [r3, #76] @ 0x4c 800709e: 4a32 ldr r2, [pc, #200] @ (8007168 ) 80070a0: 63da str r2, [r3, #60] @ 0x3c /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 80070a2: 68fb ldr r3, [r7, #12] 80070a4: 6cdb ldr r3, [r3, #76] @ 0x4c 80070a6: 4a31 ldr r2, [pc, #196] @ (800716c ) 80070a8: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ; 80070aa: 68fb ldr r3, [r7, #12] 80070ac: 6cdb ldr r3, [r3, #76] @ 0x4c 80070ae: 4a30 ldr r2, [pc, #192] @ (8007170 ) 80070b0: 64da str r2, [r3, #76] @ 0x4c /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 80070b2: 68fb ldr r3, [r7, #12] 80070b4: 681b ldr r3, [r3, #0] 80070b6: 221c movs r2, #28 80070b8: 601a str r2, [r3, #0] /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 80070ba: 68fb ldr r3, [r7, #12] 80070bc: 2200 movs r2, #0 80070be: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 80070c2: 68fb ldr r3, [r7, #12] 80070c4: 681b ldr r3, [r3, #0] 80070c6: 685a ldr r2, [r3, #4] 80070c8: 68fb ldr r3, [r7, #12] 80070ca: 681b ldr r3, [r3, #0] 80070cc: f042 0210 orr.w r2, r2, #16 80070d0: 605a str r2, [r3, #4] /* Case of ADC slave using its own DMA channel: check whether handle selected corresponds to ADC master or slave instance */ if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance) 80070d2: 68fb ldr r3, [r7, #12] 80070d4: 681b ldr r3, [r3, #0] 80070d6: 4a21 ldr r2, [pc, #132] @ (800715c ) 80070d8: 4293 cmp r3, r2 80070da: d002 beq.n 80070e2 80070dc: 68fb ldr r3, [r7, #12] 80070de: 681b ldr r3, [r3, #0] 80070e0: e000 b.n 80070e4 80070e2: 4b1f ldr r3, [pc, #124] @ (8007160 ) 80070e4: 68fa ldr r2, [r7, #12] 80070e6: 6812 ldr r2, [r2, #0] 80070e8: 4293 cmp r3, r2 80070ea: d00d beq.n 8007108 { /* Case of ADC slave selected: Start the DMA channel. */ /* Note: Data transfer will start upon next call of this function using handle of ADC master */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 80070ec: 68fb ldr r3, [r7, #12] 80070ee: 6cd8 ldr r0, [r3, #76] @ 0x4c 80070f0: 68fb ldr r3, [r7, #12] 80070f2: 681b ldr r3, [r3, #0] 80070f4: 3340 adds r3, #64 @ 0x40 80070f6: 4619 mov r1, r3 80070f8: 68ba ldr r2, [r7, #8] 80070fa: 687b ldr r3, [r7, #4] 80070fc: f001 fbb8 bl 8008870 8007100: 4603 mov r3, r0 8007102: f887 307f strb.w r3, [r7, #127] @ 0x7f 8007106: e023 b.n 8007150 } else { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); 8007108: 68fb ldr r3, [r7, #12] 800710a: 681b ldr r3, [r3, #0] 800710c: 4a14 ldr r2, [pc, #80] @ (8007160 ) 800710e: 4293 cmp r3, r2 8007110: d004 beq.n 800711c 8007112: 68fb ldr r3, [r7, #12] 8007114: 681b ldr r3, [r3, #0] 8007116: 4a11 ldr r2, [pc, #68] @ (800715c ) 8007118: 4293 cmp r3, r2 800711a: d101 bne.n 8007120 800711c: 4b15 ldr r3, [pc, #84] @ (8007174 ) 800711e: e000 b.n 8007122 8007120: 4b15 ldr r3, [pc, #84] @ (8007178 ) 8007122: 67bb str r3, [r7, #120] @ 0x78 /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); 8007124: 68fb ldr r3, [r7, #12] 8007126: 6cd8 ldr r0, [r3, #76] @ 0x4c 8007128: 6fbb ldr r3, [r7, #120] @ 0x78 800712a: 330c adds r3, #12 800712c: 4619 mov r1, r3 800712e: 68ba ldr r2, [r7, #8] 8007130: 687b ldr r3, [r7, #4] 8007132: f001 fb9d bl 8008870 8007136: 4603 mov r3, r0 8007138: f887 307f strb.w r3, [r7, #127] @ 0x7f /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); 800713c: 68fb ldr r3, [r7, #12] 800713e: 681b ldr r3, [r3, #0] 8007140: 4618 mov r0, r3 8007142: f7ff feb1 bl 8006ea8 8007146: e003 b.n 8007150 } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 8007148: 68fb ldr r3, [r7, #12] 800714a: 2200 movs r2, #0 800714c: f883 2050 strb.w r2, [r3, #80] @ 0x50 } /* Return function status */ return tmp_hal_status; 8007150: f897 307f ldrb.w r3, [r7, #127] @ 0x7f } } 8007154: 4618 mov r0, r3 8007156: 3780 adds r7, #128 @ 0x80 8007158: 46bd mov sp, r7 800715a: bd80 pop {r7, pc} 800715c: 40022100 .word 0x40022100 8007160: 40022000 .word 0x40022000 8007164: fffff0fe .word 0xfffff0fe 8007168: 08006adb .word 0x08006adb 800716c: 08006bb3 .word 0x08006bb3 8007170: 08006bcf .word 0x08006bcf 8007174: 40022300 .word 0x40022300 8007178: 58026300 .word 0x58026300 0800717c : * @param hadc Master ADC handle * @param multimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { 800717c: b590 push {r4, r7, lr} 800717e: b09f sub sp, #124 @ 0x7c 8007180: af00 add r7, sp, #0 8007182: 6078 str r0, [r7, #4] 8007184: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8007186: 2300 movs r3, #0 8007188: f887 3077 strb.w r3, [r7, #119] @ 0x77 assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); 800718c: 687b ldr r3, [r7, #4] 800718e: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8007192: 2b01 cmp r3, #1 8007194: d101 bne.n 800719a 8007196: 2302 movs r3, #2 8007198: e0be b.n 8007318 800719a: 687b ldr r3, [r7, #4] 800719c: 2201 movs r2, #1 800719e: f883 2050 strb.w r2, [r3, #80] @ 0x50 tmphadcSlave.State = HAL_ADC_STATE_RESET; 80071a2: 2300 movs r3, #0 80071a4: 65fb str r3, [r7, #92] @ 0x5c tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; 80071a6: 2300 movs r3, #0 80071a8: 663b str r3, [r7, #96] @ 0x60 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 80071aa: 687b ldr r3, [r7, #4] 80071ac: 681b ldr r3, [r3, #0] 80071ae: 4a5c ldr r2, [pc, #368] @ (8007320 ) 80071b0: 4293 cmp r3, r2 80071b2: d102 bne.n 80071ba 80071b4: 4b5b ldr r3, [pc, #364] @ (8007324 ) 80071b6: 60bb str r3, [r7, #8] 80071b8: e001 b.n 80071be 80071ba: 2300 movs r3, #0 80071bc: 60bb str r3, [r7, #8] if (tmphadcSlave.Instance == NULL) 80071be: 68bb ldr r3, [r7, #8] 80071c0: 2b00 cmp r3, #0 80071c2: d10b bne.n 80071dc { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80071c4: 687b ldr r3, [r7, #4] 80071c6: 6d5b ldr r3, [r3, #84] @ 0x54 80071c8: f043 0220 orr.w r2, r3, #32 80071cc: 687b ldr r3, [r7, #4] 80071ce: 655a str r2, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hadc); 80071d0: 687b ldr r3, [r7, #4] 80071d2: 2200 movs r2, #0 80071d4: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 80071d8: 2301 movs r3, #1 80071da: e09d b.n 8007318 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DATA Format configuration */ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); 80071dc: 68bb ldr r3, [r7, #8] 80071de: 4618 mov r0, r3 80071e0: f7ff fe76 bl 8006ed0 80071e4: 6738 str r0, [r7, #112] @ 0x70 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 80071e6: 687b ldr r3, [r7, #4] 80071e8: 681b ldr r3, [r3, #0] 80071ea: 4618 mov r0, r3 80071ec: f7ff fe70 bl 8006ed0 80071f0: 4603 mov r3, r0 80071f2: 2b00 cmp r3, #0 80071f4: d17f bne.n 80072f6 && (tmphadcSlave_conversion_on_going == 0UL)) 80071f6: 6f3b ldr r3, [r7, #112] @ 0x70 80071f8: 2b00 cmp r3, #0 80071fa: d17c bne.n 80072f6 { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); 80071fc: 687b ldr r3, [r7, #4] 80071fe: 681b ldr r3, [r3, #0] 8007200: 4a47 ldr r2, [pc, #284] @ (8007320 ) 8007202: 4293 cmp r3, r2 8007204: d004 beq.n 8007210 8007206: 687b ldr r3, [r7, #4] 8007208: 681b ldr r3, [r3, #0] 800720a: 4a46 ldr r2, [pc, #280] @ (8007324 ) 800720c: 4293 cmp r3, r2 800720e: d101 bne.n 8007214 8007210: 4b45 ldr r3, [pc, #276] @ (8007328 ) 8007212: e000 b.n 8007216 8007214: 4b45 ldr r3, [pc, #276] @ (800732c ) 8007216: 66fb str r3, [r7, #108] @ 0x6c /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if (multimode->Mode != ADC_MODE_INDEPENDENT) 8007218: 683b ldr r3, [r7, #0] 800721a: 681b ldr r3, [r3, #0] 800721c: 2b00 cmp r3, #0 800721e: d039 beq.n 8007294 { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData); 8007220: 6efb ldr r3, [r7, #108] @ 0x6c 8007222: 689b ldr r3, [r3, #8] 8007224: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8007228: 683b ldr r3, [r7, #0] 800722a: 685b ldr r3, [r3, #4] 800722c: 431a orrs r2, r3 800722e: 6efb ldr r3, [r7, #108] @ 0x6c 8007230: 609a str r2, [r3, #8] /* from 1 to 8 clock cycles for 12 bits */ /* from 1 to 6 clock cycles for 10 and 8 bits */ /* If a higher delay is selected, it will be clipped to maximum delay */ /* range */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8007232: 687b ldr r3, [r7, #4] 8007234: 681b ldr r3, [r3, #0] 8007236: 4a3a ldr r2, [pc, #232] @ (8007320 ) 8007238: 4293 cmp r3, r2 800723a: d004 beq.n 8007246 800723c: 687b ldr r3, [r7, #4] 800723e: 681b ldr r3, [r3, #0] 8007240: 4a38 ldr r2, [pc, #224] @ (8007324 ) 8007242: 4293 cmp r3, r2 8007244: d10e bne.n 8007264 8007246: 4836 ldr r0, [pc, #216] @ (8007320 ) 8007248: f7ff fde8 bl 8006e1c 800724c: 4604 mov r4, r0 800724e: 4835 ldr r0, [pc, #212] @ (8007324 ) 8007250: f7ff fde4 bl 8006e1c 8007254: 4603 mov r3, r0 8007256: 4323 orrs r3, r4 8007258: 2b00 cmp r3, #0 800725a: bf0c ite eq 800725c: 2301 moveq r3, #1 800725e: 2300 movne r3, #0 8007260: b2db uxtb r3, r3 8007262: e008 b.n 8007276 8007264: 4832 ldr r0, [pc, #200] @ (8007330 ) 8007266: f7ff fdd9 bl 8006e1c 800726a: 4603 mov r3, r0 800726c: 2b00 cmp r3, #0 800726e: bf0c ite eq 8007270: 2301 moveq r3, #1 8007272: 2300 movne r3, #0 8007274: b2db uxtb r3, r3 8007276: 2b00 cmp r3, #0 8007278: d047 beq.n 800730a { MODIFY_REG(tmpADC_Common->CCR, 800727a: 6efb ldr r3, [r7, #108] @ 0x6c 800727c: 689a ldr r2, [r3, #8] 800727e: 4b2d ldr r3, [pc, #180] @ (8007334 ) 8007280: 4013 ands r3, r2 8007282: 683a ldr r2, [r7, #0] 8007284: 6811 ldr r1, [r2, #0] 8007286: 683a ldr r2, [r7, #0] 8007288: 6892 ldr r2, [r2, #8] 800728a: 430a orrs r2, r1 800728c: 431a orrs r2, r3 800728e: 6efb ldr r3, [r7, #108] @ 0x6c 8007290: 609a str r2, [r3, #8] if (multimode->Mode != ADC_MODE_INDEPENDENT) 8007292: e03a b.n 800730a ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF); 8007294: 6efb ldr r3, [r7, #108] @ 0x6c 8007296: 689b ldr r3, [r3, #8] 8007298: f423 4240 bic.w r2, r3, #49152 @ 0xc000 800729c: 6efb ldr r3, [r7, #108] @ 0x6c 800729e: 609a str r2, [r3, #8] /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 80072a0: 687b ldr r3, [r7, #4] 80072a2: 681b ldr r3, [r3, #0] 80072a4: 4a1e ldr r2, [pc, #120] @ (8007320 ) 80072a6: 4293 cmp r3, r2 80072a8: d004 beq.n 80072b4 80072aa: 687b ldr r3, [r7, #4] 80072ac: 681b ldr r3, [r3, #0] 80072ae: 4a1d ldr r2, [pc, #116] @ (8007324 ) 80072b0: 4293 cmp r3, r2 80072b2: d10e bne.n 80072d2 80072b4: 481a ldr r0, [pc, #104] @ (8007320 ) 80072b6: f7ff fdb1 bl 8006e1c 80072ba: 4604 mov r4, r0 80072bc: 4819 ldr r0, [pc, #100] @ (8007324 ) 80072be: f7ff fdad bl 8006e1c 80072c2: 4603 mov r3, r0 80072c4: 4323 orrs r3, r4 80072c6: 2b00 cmp r3, #0 80072c8: bf0c ite eq 80072ca: 2301 moveq r3, #1 80072cc: 2300 movne r3, #0 80072ce: b2db uxtb r3, r3 80072d0: e008 b.n 80072e4 80072d2: 4817 ldr r0, [pc, #92] @ (8007330 ) 80072d4: f7ff fda2 bl 8006e1c 80072d8: 4603 mov r3, r0 80072da: 2b00 cmp r3, #0 80072dc: bf0c ite eq 80072de: 2301 moveq r3, #1 80072e0: 2300 movne r3, #0 80072e2: b2db uxtb r3, r3 80072e4: 2b00 cmp r3, #0 80072e6: d010 beq.n 800730a { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); 80072e8: 6efb ldr r3, [r7, #108] @ 0x6c 80072ea: 689a ldr r2, [r3, #8] 80072ec: 4b11 ldr r3, [pc, #68] @ (8007334 ) 80072ee: 4013 ands r3, r2 80072f0: 6efa ldr r2, [r7, #108] @ 0x6c 80072f2: 6093 str r3, [r2, #8] if (multimode->Mode != ADC_MODE_INDEPENDENT) 80072f4: e009 b.n 800730a /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80072f6: 687b ldr r3, [r7, #4] 80072f8: 6d5b ldr r3, [r3, #84] @ 0x54 80072fa: f043 0220 orr.w r2, r3, #32 80072fe: 687b ldr r3, [r7, #4] 8007300: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8007302: 2301 movs r3, #1 8007304: f887 3077 strb.w r3, [r7, #119] @ 0x77 8007308: e000 b.n 800730c if (multimode->Mode != ADC_MODE_INDEPENDENT) 800730a: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); 800730c: 687b ldr r3, [r7, #4] 800730e: 2200 movs r2, #0 8007310: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 8007314: f897 3077 ldrb.w r3, [r7, #119] @ 0x77 } 8007318: 4618 mov r0, r3 800731a: 377c adds r7, #124 @ 0x7c 800731c: 46bd mov sp, r7 800731e: bd90 pop {r4, r7, pc} 8007320: 40022000 .word 0x40022000 8007324: 40022100 .word 0x40022100 8007328: 40022300 .word 0x40022300 800732c: 58026300 .word 0x58026300 8007330: 58026000 .word 0x58026000 8007334: fffff0e0 .word 0xfffff0e0 08007338 : * To unlock the configuration, perform a system reset. * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { 8007338: b580 push {r7, lr} 800733a: b088 sub sp, #32 800733c: af00 add r7, sp, #0 800733e: 6078 str r0, [r7, #4] uint32_t tmp_csr ; uint32_t exti_line ; uint32_t comp_voltage_scaler_initialized; /* Value "0" is comparator voltage scaler is not initialized */ __IO uint32_t wait_loop_index = 0UL; 8007340: 2300 movs r3, #0 8007342: 60fb str r3, [r7, #12] HAL_StatusTypeDef status = HAL_OK; 8007344: 2300 movs r3, #0 8007346: 77fb strb r3, [r7, #31] /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) 8007348: 687b ldr r3, [r7, #4] 800734a: 2b00 cmp r3, #0 800734c: d102 bne.n 8007354 { status = HAL_ERROR; 800734e: 2301 movs r3, #1 8007350: 77fb strb r3, [r7, #31] 8007352: e10e b.n 8007572 } else if(__HAL_COMP_IS_LOCKED(hcomp)) 8007354: 687b ldr r3, [r7, #4] 8007356: 681b ldr r3, [r3, #0] 8007358: 681b ldr r3, [r3, #0] 800735a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 800735e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007362: d102 bne.n 800736a { status = HAL_ERROR; 8007364: 2301 movs r3, #1 8007366: 77fb strb r3, [r7, #31] 8007368: e103 b.n 8007572 assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); if(hcomp->State == HAL_COMP_STATE_RESET) 800736a: 687b ldr r3, [r7, #4] 800736c: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8007370: b2db uxtb r3, r3 8007372: 2b00 cmp r3, #0 8007374: d109 bne.n 800738a { /* Allocate lock resource and initialize it */ hcomp->Lock = HAL_UNLOCKED; 8007376: 687b ldr r3, [r7, #4] 8007378: 2200 movs r2, #0 800737a: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Set COMP error code to none */ COMP_CLEAR_ERRORCODE(hcomp); 800737e: 687b ldr r3, [r7, #4] 8007380: 2200 movs r2, #0 8007382: 629a str r2, [r3, #40] @ 0x28 /* Init the low level hardware */ hcomp->MspInitCallback(hcomp); #else /* Init the low level hardware */ HAL_COMP_MspInit(hcomp); 8007384: 6878 ldr r0, [r7, #4] 8007386: f7fc fc17 bl 8003bb8 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } /* Memorize voltage scaler state before initialization */ comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN); 800738a: 687b ldr r3, [r7, #4] 800738c: 681b ldr r3, [r3, #0] 800738e: 681b ldr r3, [r3, #0] 8007390: f003 0304 and.w r3, r3, #4 8007394: 61bb str r3, [r7, #24] /* Set BLANKING bits according to hcomp->Init.BlankingSrce value */ /* Set HYST bits according to hcomp->Init.Hysteresis value */ /* Set POLARITY bit according to hcomp->Init.OutputPol value */ /* Set POWERMODE bits according to hcomp->Init.Mode value */ tmp_csr = (hcomp->Init.InvertingInput | \ 8007396: 687b ldr r3, [r7, #4] 8007398: 691a ldr r2, [r3, #16] hcomp->Init.NonInvertingInput | \ 800739a: 687b ldr r3, [r7, #4] 800739c: 68db ldr r3, [r3, #12] tmp_csr = (hcomp->Init.InvertingInput | \ 800739e: 431a orrs r2, r3 hcomp->Init.BlankingSrce | \ 80073a0: 687b ldr r3, [r7, #4] 80073a2: 69db ldr r3, [r3, #28] hcomp->Init.NonInvertingInput | \ 80073a4: 431a orrs r2, r3 hcomp->Init.Hysteresis | \ 80073a6: 687b ldr r3, [r7, #4] 80073a8: 695b ldr r3, [r3, #20] hcomp->Init.BlankingSrce | \ 80073aa: 431a orrs r2, r3 hcomp->Init.OutputPol | \ 80073ac: 687b ldr r3, [r7, #4] 80073ae: 699b ldr r3, [r3, #24] hcomp->Init.Hysteresis | \ 80073b0: 431a orrs r2, r3 hcomp->Init.Mode ); 80073b2: 687b ldr r3, [r7, #4] 80073b4: 689b ldr r3, [r3, #8] tmp_csr = (hcomp->Init.InvertingInput | \ 80073b6: 4313 orrs r3, r2 80073b8: 617b str r3, [r7, #20] COMP_CFGRx_INP2SEL | COMP_CFGRx_WINMODE | COMP_CFGRx_POLARITY | COMP_CFGRx_HYST | COMP_CFGRx_BLANKING | COMP_CFGRx_BRGEN | COMP_CFGRx_SCALEN, tmp_csr ); #else MODIFY_REG(hcomp->Instance->CFGR, 80073ba: 687b ldr r3, [r7, #4] 80073bc: 681b ldr r3, [r3, #0] 80073be: 681a ldr r2, [r3, #0] 80073c0: 4b6e ldr r3, [pc, #440] @ (800757c ) 80073c2: 4013 ands r3, r2 80073c4: 687a ldr r2, [r7, #4] 80073c6: 6812 ldr r2, [r2, #0] 80073c8: 6979 ldr r1, [r7, #20] 80073ca: 430b orrs r3, r1 80073cc: 6013 str r3, [r2, #0] #endif /* Set window mode */ /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ /* instances. Therefore, this function can update another COMP */ /* instance that the one currently selected. */ if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) 80073ce: 687b ldr r3, [r7, #4] 80073d0: 685b ldr r3, [r3, #4] 80073d2: 2b10 cmp r3, #16 80073d4: d108 bne.n 80073e8 { SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE); 80073d6: 687b ldr r3, [r7, #4] 80073d8: 681b ldr r3, [r3, #0] 80073da: 681a ldr r2, [r3, #0] 80073dc: 687b ldr r3, [r7, #4] 80073de: 681b ldr r3, [r3, #0] 80073e0: f042 0210 orr.w r2, r2, #16 80073e4: 601a str r2, [r3, #0] 80073e6: e007 b.n 80073f8 } else { CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE); 80073e8: 687b ldr r3, [r7, #4] 80073ea: 681b ldr r3, [r3, #0] 80073ec: 681a ldr r2, [r3, #0] 80073ee: 687b ldr r3, [r7, #4] 80073f0: 681b ldr r3, [r3, #0] 80073f2: f022 0210 bic.w r2, r2, #16 80073f6: 601a str r2, [r3, #0] } /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is enabled for the first time */ if ((READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN) != 0UL) && 80073f8: 687b ldr r3, [r7, #4] 80073fa: 681b ldr r3, [r3, #0] 80073fc: 681b ldr r3, [r3, #0] 80073fe: f003 0304 and.w r3, r3, #4 8007402: 2b00 cmp r3, #0 8007404: d016 beq.n 8007434 8007406: 69bb ldr r3, [r7, #24] 8007408: 2b00 cmp r3, #0 800740a: d013 beq.n 8007434 { /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles.*/ wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 800740c: 4b5c ldr r3, [pc, #368] @ (8007580 ) 800740e: 681b ldr r3, [r3, #0] 8007410: 099b lsrs r3, r3, #6 8007412: 4a5c ldr r2, [pc, #368] @ (8007584 ) 8007414: fba2 2303 umull r2, r3, r2, r3 8007418: 099b lsrs r3, r3, #6 800741a: 1c5a adds r2, r3, #1 800741c: 4613 mov r3, r2 800741e: 009b lsls r3, r3, #2 8007420: 4413 add r3, r2 8007422: 009b lsls r3, r3, #2 8007424: 60fb str r3, [r7, #12] while(wait_loop_index != 0UL) 8007426: e002 b.n 800742e { wait_loop_index --; 8007428: 68fb ldr r3, [r7, #12] 800742a: 3b01 subs r3, #1 800742c: 60fb str r3, [r7, #12] while(wait_loop_index != 0UL) 800742e: 68fb ldr r3, [r7, #12] 8007430: 2b00 cmp r3, #0 8007432: d1f9 bne.n 8007428 } } /* Get the EXTI line corresponding to the selected COMP instance */ exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); 8007434: 687b ldr r3, [r7, #4] 8007436: 681b ldr r3, [r3, #0] 8007438: 4a53 ldr r2, [pc, #332] @ (8007588 ) 800743a: 4293 cmp r3, r2 800743c: d102 bne.n 8007444 800743e: f44f 1380 mov.w r3, #1048576 @ 0x100000 8007442: e001 b.n 8007448 8007444: f44f 1300 mov.w r3, #2097152 @ 0x200000 8007448: 613b str r3, [r7, #16] /* Manage EXTI settings */ if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) 800744a: 687b ldr r3, [r7, #4] 800744c: 6a1b ldr r3, [r3, #32] 800744e: f003 0303 and.w r3, r3, #3 8007452: 2b00 cmp r3, #0 8007454: d06d beq.n 8007532 { /* Configure EXTI rising edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) 8007456: 687b ldr r3, [r7, #4] 8007458: 6a1b ldr r3, [r3, #32] 800745a: f003 0310 and.w r3, r3, #16 800745e: 2b00 cmp r3, #0 8007460: d008 beq.n 8007474 { SET_BIT(EXTI->RTSR1, exti_line); 8007462: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007466: 681a ldr r2, [r3, #0] 8007468: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800746c: 693b ldr r3, [r7, #16] 800746e: 4313 orrs r3, r2 8007470: 600b str r3, [r1, #0] 8007472: e008 b.n 8007486 } else { CLEAR_BIT(EXTI->RTSR1, exti_line); 8007474: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007478: 681a ldr r2, [r3, #0] 800747a: 693b ldr r3, [r7, #16] 800747c: 43db mvns r3, r3 800747e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007482: 4013 ands r3, r2 8007484: 600b str r3, [r1, #0] } /* Configure EXTI falling edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) 8007486: 687b ldr r3, [r7, #4] 8007488: 6a1b ldr r3, [r3, #32] 800748a: f003 0320 and.w r3, r3, #32 800748e: 2b00 cmp r3, #0 8007490: d008 beq.n 80074a4 { SET_BIT(EXTI->FTSR1, exti_line); 8007492: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007496: 685a ldr r2, [r3, #4] 8007498: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800749c: 693b ldr r3, [r7, #16] 800749e: 4313 orrs r3, r2 80074a0: 604b str r3, [r1, #4] 80074a2: e008 b.n 80074b6 } else { CLEAR_BIT(EXTI->FTSR1, exti_line); 80074a4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80074a8: 685a ldr r2, [r3, #4] 80074aa: 693b ldr r3, [r7, #16] 80074ac: 43db mvns r3, r3 80074ae: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80074b2: 4013 ands r3, r2 80074b4: 604b str r3, [r1, #4] } #if !defined (CORE_CM4) /* Clear COMP EXTI pending bit (if any) */ WRITE_REG(EXTI->PR1, exti_line); 80074b6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 80074ba: 693b ldr r3, [r7, #16] 80074bc: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure EXTI event mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) 80074c0: 687b ldr r3, [r7, #4] 80074c2: 6a1b ldr r3, [r3, #32] 80074c4: f003 0302 and.w r3, r3, #2 80074c8: 2b00 cmp r3, #0 80074ca: d00a beq.n 80074e2 { SET_BIT(EXTI->EMR1, exti_line); 80074cc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80074d0: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 80074d4: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80074d8: 693b ldr r3, [r7, #16] 80074da: 4313 orrs r3, r2 80074dc: f8c1 3084 str.w r3, [r1, #132] @ 0x84 80074e0: e00a b.n 80074f8 } else { CLEAR_BIT(EXTI->EMR1, exti_line); 80074e2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80074e6: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 80074ea: 693b ldr r3, [r7, #16] 80074ec: 43db mvns r3, r3 80074ee: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80074f2: 4013 ands r3, r2 80074f4: f8c1 3084 str.w r3, [r1, #132] @ 0x84 } /* Configure EXTI interrupt mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) 80074f8: 687b ldr r3, [r7, #4] 80074fa: 6a1b ldr r3, [r3, #32] 80074fc: f003 0301 and.w r3, r3, #1 8007500: 2b00 cmp r3, #0 8007502: d00a beq.n 800751a { SET_BIT(EXTI->IMR1, exti_line); 8007504: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007508: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 800750c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007510: 693b ldr r3, [r7, #16] 8007512: 4313 orrs r3, r2 8007514: f8c1 3080 str.w r3, [r1, #128] @ 0x80 8007518: e021 b.n 800755e } else { CLEAR_BIT(EXTI->IMR1, exti_line); 800751a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800751e: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 8007522: 693b ldr r3, [r7, #16] 8007524: 43db mvns r3, r3 8007526: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800752a: 4013 ands r3, r2 800752c: f8c1 3080 str.w r3, [r1, #128] @ 0x80 8007530: e015 b.n 800755e } } else { /* Disable EXTI event mode */ CLEAR_BIT(EXTI->EMR1, exti_line); 8007532: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007536: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 800753a: 693b ldr r3, [r7, #16] 800753c: 43db mvns r3, r3 800753e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007542: 4013 ands r3, r2 8007544: f8c1 3084 str.w r3, [r1, #132] @ 0x84 /* Disable EXTI interrupt mode */ CLEAR_BIT(EXTI->IMR1, exti_line); 8007548: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800754c: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 8007550: 693b ldr r3, [r7, #16] 8007552: 43db mvns r3, r3 8007554: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007558: 4013 ands r3, r2 800755a: f8c1 3080 str.w r3, [r1, #128] @ 0x80 } #endif /* Set HAL COMP handle state */ /* Note: Transition from state reset to state ready, */ /* otherwise (coming from state ready or busy) no state update. */ if (hcomp->State == HAL_COMP_STATE_RESET) 800755e: 687b ldr r3, [r7, #4] 8007560: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8007564: b2db uxtb r3, r3 8007566: 2b00 cmp r3, #0 8007568: d103 bne.n 8007572 { hcomp->State = HAL_COMP_STATE_READY; 800756a: 687b ldr r3, [r7, #4] 800756c: 2201 movs r2, #1 800756e: f883 2025 strb.w r2, [r3, #37] @ 0x25 } } return status; 8007572: 7ffb ldrb r3, [r7, #31] } 8007574: 4618 mov r0, r3 8007576: 3720 adds r7, #32 8007578: 46bd mov sp, r7 800757a: bd80 pop {r7, pc} 800757c: f0e8cce1 .word 0xf0e8cce1 8007580: 24000034 .word 0x24000034 8007584: 053e2d63 .word 0x053e2d63 8007588: 5800380c .word 0x5800380c 0800758c : * @brief Start the comparator. * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { 800758c: b480 push {r7} 800758e: b085 sub sp, #20 8007590: af00 add r7, sp, #0 8007592: 6078 str r0, [r7, #4] __IO uint32_t wait_loop_index = 0UL; 8007594: 2300 movs r3, #0 8007596: 60bb str r3, [r7, #8] HAL_StatusTypeDef status = HAL_OK; 8007598: 2300 movs r3, #0 800759a: 73fb strb r3, [r7, #15] /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) 800759c: 687b ldr r3, [r7, #4] 800759e: 2b00 cmp r3, #0 80075a0: d102 bne.n 80075a8 { status = HAL_ERROR; 80075a2: 2301 movs r3, #1 80075a4: 73fb strb r3, [r7, #15] 80075a6: e030 b.n 800760a } else if(__HAL_COMP_IS_LOCKED(hcomp)) 80075a8: 687b ldr r3, [r7, #4] 80075aa: 681b ldr r3, [r3, #0] 80075ac: 681b ldr r3, [r3, #0] 80075ae: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80075b2: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80075b6: d102 bne.n 80075be { status = HAL_ERROR; 80075b8: 2301 movs r3, #1 80075ba: 73fb strb r3, [r7, #15] 80075bc: e025 b.n 800760a else { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); if(hcomp->State == HAL_COMP_STATE_READY) 80075be: 687b ldr r3, [r7, #4] 80075c0: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 80075c4: b2db uxtb r3, r3 80075c6: 2b01 cmp r3, #1 80075c8: d11d bne.n 8007606 { /* Enable the selected comparator */ SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN); 80075ca: 687b ldr r3, [r7, #4] 80075cc: 681b ldr r3, [r3, #0] 80075ce: 681a ldr r2, [r3, #0] 80075d0: 687b ldr r3, [r7, #4] 80075d2: 681b ldr r3, [r3, #0] 80075d4: f042 0201 orr.w r2, r2, #1 80075d8: 601a str r2, [r3, #0] /* Set HAL COMP handle state */ hcomp->State = HAL_COMP_STATE_BUSY; 80075da: 687b ldr r3, [r7, #4] 80075dc: 2202 movs r2, #2 80075de: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Delay for COMP startup time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 80075e2: 4b0d ldr r3, [pc, #52] @ (8007618 ) 80075e4: 681b ldr r3, [r3, #0] 80075e6: 099b lsrs r3, r3, #6 80075e8: 4a0c ldr r2, [pc, #48] @ (800761c ) 80075ea: fba2 2303 umull r2, r3, r2, r3 80075ee: 099b lsrs r3, r3, #6 80075f0: 3301 adds r3, #1 80075f2: 00db lsls r3, r3, #3 80075f4: 60bb str r3, [r7, #8] while(wait_loop_index != 0UL) 80075f6: e002 b.n 80075fe { wait_loop_index--; 80075f8: 68bb ldr r3, [r7, #8] 80075fa: 3b01 subs r3, #1 80075fc: 60bb str r3, [r7, #8] while(wait_loop_index != 0UL) 80075fe: 68bb ldr r3, [r7, #8] 8007600: 2b00 cmp r3, #0 8007602: d1f9 bne.n 80075f8 8007604: e001 b.n 800760a } } else { status = HAL_ERROR; 8007606: 2301 movs r3, #1 8007608: 73fb strb r3, [r7, #15] } } return status; 800760a: 7bfb ldrb r3, [r7, #15] } 800760c: 4618 mov r0, r3 800760e: 3714 adds r7, #20 8007610: 46bd mov sp, r7 8007612: f85d 7b04 ldr.w r7, [sp], #4 8007616: 4770 bx lr 8007618: 24000034 .word 0x24000034 800761c: 053e2d63 .word 0x053e2d63 08007620 : * @arg @ref COMP_OUTPUT_LEVEL_LOW * @arg @ref COMP_OUTPUT_LEVEL_HIGH * */ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) { 8007620: b480 push {r7} 8007622: b083 sub sp, #12 8007624: af00 add r7, sp, #0 8007626: 6078 str r0, [r7, #4] /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); if (hcomp->Instance == COMP1) 8007628: 687b ldr r3, [r7, #4] 800762a: 681b ldr r3, [r3, #0] 800762c: 4a09 ldr r2, [pc, #36] @ (8007654 ) 800762e: 4293 cmp r3, r2 8007630: d104 bne.n 800763c { return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL)); 8007632: 4b09 ldr r3, [pc, #36] @ (8007658 ) 8007634: 681b ldr r3, [r3, #0] 8007636: f003 0301 and.w r3, r3, #1 800763a: e004 b.n 8007646 } else { return (uint32_t)((READ_BIT(COMP12->SR, COMP_SR_C2VAL))>> 1UL); 800763c: 4b06 ldr r3, [pc, #24] @ (8007658 ) 800763e: 681b ldr r3, [r3, #0] 8007640: 085b lsrs r3, r3, #1 8007642: f003 0301 and.w r3, r3, #1 } } 8007646: 4618 mov r0, r3 8007648: 370c adds r7, #12 800764a: 46bd mov sp, r7 800764c: f85d 7b04 ldr.w r7, [sp], #4 8007650: 4770 bx lr 8007652: bf00 nop 8007654: 5800380c .word 0x5800380c 8007658: 58003800 .word 0x58003800 0800765c <__NVIC_SetPriorityGrouping>: { 800765c: b480 push {r7} 800765e: b085 sub sp, #20 8007660: af00 add r7, sp, #0 8007662: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8007664: 687b ldr r3, [r7, #4] 8007666: f003 0307 and.w r3, r3, #7 800766a: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 800766c: 4b0b ldr r3, [pc, #44] @ (800769c <__NVIC_SetPriorityGrouping+0x40>) 800766e: 68db ldr r3, [r3, #12] 8007670: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8007672: 68ba ldr r2, [r7, #8] 8007674: f64f 03ff movw r3, #63743 @ 0xf8ff 8007678: 4013 ands r3, r2 800767a: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800767c: 68fb ldr r3, [r7, #12] 800767e: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8007680: 68bb ldr r3, [r7, #8] 8007682: 431a orrs r2, r3 reg_value = (reg_value | 8007684: 4b06 ldr r3, [pc, #24] @ (80076a0 <__NVIC_SetPriorityGrouping+0x44>) 8007686: 4313 orrs r3, r2 8007688: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800768a: 4a04 ldr r2, [pc, #16] @ (800769c <__NVIC_SetPriorityGrouping+0x40>) 800768c: 68bb ldr r3, [r7, #8] 800768e: 60d3 str r3, [r2, #12] } 8007690: bf00 nop 8007692: 3714 adds r7, #20 8007694: 46bd mov sp, r7 8007696: f85d 7b04 ldr.w r7, [sp], #4 800769a: 4770 bx lr 800769c: e000ed00 .word 0xe000ed00 80076a0: 05fa0000 .word 0x05fa0000 080076a4 <__NVIC_GetPriorityGrouping>: { 80076a4: b480 push {r7} 80076a6: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80076a8: 4b04 ldr r3, [pc, #16] @ (80076bc <__NVIC_GetPriorityGrouping+0x18>) 80076aa: 68db ldr r3, [r3, #12] 80076ac: 0a1b lsrs r3, r3, #8 80076ae: f003 0307 and.w r3, r3, #7 } 80076b2: 4618 mov r0, r3 80076b4: 46bd mov sp, r7 80076b6: f85d 7b04 ldr.w r7, [sp], #4 80076ba: 4770 bx lr 80076bc: e000ed00 .word 0xe000ed00 080076c0 <__NVIC_EnableIRQ>: { 80076c0: b480 push {r7} 80076c2: b083 sub sp, #12 80076c4: af00 add r7, sp, #0 80076c6: 4603 mov r3, r0 80076c8: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 80076ca: f9b7 3006 ldrsh.w r3, [r7, #6] 80076ce: 2b00 cmp r3, #0 80076d0: db0b blt.n 80076ea <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80076d2: 88fb ldrh r3, [r7, #6] 80076d4: f003 021f and.w r2, r3, #31 80076d8: 4907 ldr r1, [pc, #28] @ (80076f8 <__NVIC_EnableIRQ+0x38>) 80076da: f9b7 3006 ldrsh.w r3, [r7, #6] 80076de: 095b lsrs r3, r3, #5 80076e0: 2001 movs r0, #1 80076e2: fa00 f202 lsl.w r2, r0, r2 80076e6: f841 2023 str.w r2, [r1, r3, lsl #2] } 80076ea: bf00 nop 80076ec: 370c adds r7, #12 80076ee: 46bd mov sp, r7 80076f0: f85d 7b04 ldr.w r7, [sp], #4 80076f4: 4770 bx lr 80076f6: bf00 nop 80076f8: e000e100 .word 0xe000e100 080076fc <__NVIC_SetPriority>: { 80076fc: b480 push {r7} 80076fe: b083 sub sp, #12 8007700: af00 add r7, sp, #0 8007702: 4603 mov r3, r0 8007704: 6039 str r1, [r7, #0] 8007706: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8007708: f9b7 3006 ldrsh.w r3, [r7, #6] 800770c: 2b00 cmp r3, #0 800770e: db0a blt.n 8007726 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8007710: 683b ldr r3, [r7, #0] 8007712: b2da uxtb r2, r3 8007714: 490c ldr r1, [pc, #48] @ (8007748 <__NVIC_SetPriority+0x4c>) 8007716: f9b7 3006 ldrsh.w r3, [r7, #6] 800771a: 0112 lsls r2, r2, #4 800771c: b2d2 uxtb r2, r2 800771e: 440b add r3, r1 8007720: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 8007724: e00a b.n 800773c <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8007726: 683b ldr r3, [r7, #0] 8007728: b2da uxtb r2, r3 800772a: 4908 ldr r1, [pc, #32] @ (800774c <__NVIC_SetPriority+0x50>) 800772c: 88fb ldrh r3, [r7, #6] 800772e: f003 030f and.w r3, r3, #15 8007732: 3b04 subs r3, #4 8007734: 0112 lsls r2, r2, #4 8007736: b2d2 uxtb r2, r2 8007738: 440b add r3, r1 800773a: 761a strb r2, [r3, #24] } 800773c: bf00 nop 800773e: 370c adds r7, #12 8007740: 46bd mov sp, r7 8007742: f85d 7b04 ldr.w r7, [sp], #4 8007746: 4770 bx lr 8007748: e000e100 .word 0xe000e100 800774c: e000ed00 .word 0xe000ed00 08007750 : { 8007750: b480 push {r7} 8007752: b089 sub sp, #36 @ 0x24 8007754: af00 add r7, sp, #0 8007756: 60f8 str r0, [r7, #12] 8007758: 60b9 str r1, [r7, #8] 800775a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800775c: 68fb ldr r3, [r7, #12] 800775e: f003 0307 and.w r3, r3, #7 8007762: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8007764: 69fb ldr r3, [r7, #28] 8007766: f1c3 0307 rsb r3, r3, #7 800776a: 2b04 cmp r3, #4 800776c: bf28 it cs 800776e: 2304 movcs r3, #4 8007770: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8007772: 69fb ldr r3, [r7, #28] 8007774: 3304 adds r3, #4 8007776: 2b06 cmp r3, #6 8007778: d902 bls.n 8007780 800777a: 69fb ldr r3, [r7, #28] 800777c: 3b03 subs r3, #3 800777e: e000 b.n 8007782 8007780: 2300 movs r3, #0 8007782: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8007784: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007788: 69bb ldr r3, [r7, #24] 800778a: fa02 f303 lsl.w r3, r2, r3 800778e: 43da mvns r2, r3 8007790: 68bb ldr r3, [r7, #8] 8007792: 401a ands r2, r3 8007794: 697b ldr r3, [r7, #20] 8007796: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8007798: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800779c: 697b ldr r3, [r7, #20] 800779e: fa01 f303 lsl.w r3, r1, r3 80077a2: 43d9 mvns r1, r3 80077a4: 687b ldr r3, [r7, #4] 80077a6: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80077a8: 4313 orrs r3, r2 } 80077aa: 4618 mov r0, r3 80077ac: 3724 adds r7, #36 @ 0x24 80077ae: 46bd mov sp, r7 80077b0: f85d 7b04 ldr.w r7, [sp], #4 80077b4: 4770 bx lr 080077b6 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80077b6: b580 push {r7, lr} 80077b8: b082 sub sp, #8 80077ba: af00 add r7, sp, #0 80077bc: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80077be: 6878 ldr r0, [r7, #4] 80077c0: f7ff ff4c bl 800765c <__NVIC_SetPriorityGrouping> } 80077c4: bf00 nop 80077c6: 3708 adds r7, #8 80077c8: 46bd mov sp, r7 80077ca: bd80 pop {r7, pc} 080077cc : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80077cc: b580 push {r7, lr} 80077ce: b086 sub sp, #24 80077d0: af00 add r7, sp, #0 80077d2: 4603 mov r3, r0 80077d4: 60b9 str r1, [r7, #8] 80077d6: 607a str r2, [r7, #4] 80077d8: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 80077da: f7ff ff63 bl 80076a4 <__NVIC_GetPriorityGrouping> 80077de: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80077e0: 687a ldr r2, [r7, #4] 80077e2: 68b9 ldr r1, [r7, #8] 80077e4: 6978 ldr r0, [r7, #20] 80077e6: f7ff ffb3 bl 8007750 80077ea: 4602 mov r2, r0 80077ec: f9b7 300e ldrsh.w r3, [r7, #14] 80077f0: 4611 mov r1, r2 80077f2: 4618 mov r0, r3 80077f4: f7ff ff82 bl 80076fc <__NVIC_SetPriority> } 80077f8: bf00 nop 80077fa: 3718 adds r7, #24 80077fc: 46bd mov sp, r7 80077fe: bd80 pop {r7, pc} 08007800 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8007800: b580 push {r7, lr} 8007802: b082 sub sp, #8 8007804: af00 add r7, sp, #0 8007806: 4603 mov r3, r0 8007808: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800780a: f9b7 3006 ldrsh.w r3, [r7, #6] 800780e: 4618 mov r0, r3 8007810: f7ff ff56 bl 80076c0 <__NVIC_EnableIRQ> } 8007814: bf00 nop 8007816: 3708 adds r7, #8 8007818: 46bd mov sp, r7 800781a: bd80 pop {r7, pc} 0800781c : /** * @brief Disables the MPU * @retval None */ void HAL_MPU_Disable(void) { 800781c: b480 push {r7} 800781e: af00 add r7, sp, #0 __ASM volatile ("dmb 0xF":::"memory"); 8007820: f3bf 8f5f dmb sy } 8007824: bf00 nop /* Make sure outstanding transfers are done */ __DMB(); /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 8007826: 4b07 ldr r3, [pc, #28] @ (8007844 ) 8007828: 6a5b ldr r3, [r3, #36] @ 0x24 800782a: 4a06 ldr r2, [pc, #24] @ (8007844 ) 800782c: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8007830: 6253 str r3, [r2, #36] @ 0x24 /* Disable the MPU and clear the control register*/ MPU->CTRL = 0; 8007832: 4b05 ldr r3, [pc, #20] @ (8007848 ) 8007834: 2200 movs r2, #0 8007836: 605a str r2, [r3, #4] } 8007838: bf00 nop 800783a: 46bd mov sp, r7 800783c: f85d 7b04 ldr.w r7, [sp], #4 8007840: 4770 bx lr 8007842: bf00 nop 8007844: e000ed00 .word 0xe000ed00 8007848: e000ed90 .word 0xe000ed90 0800784c : * @arg MPU_PRIVILEGED_DEFAULT * @arg MPU_HFNMI_PRIVDEF * @retval None */ void HAL_MPU_Enable(uint32_t MPU_Control) { 800784c: b480 push {r7} 800784e: b083 sub sp, #12 8007850: af00 add r7, sp, #0 8007852: 6078 str r0, [r7, #4] /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 8007854: 4a0b ldr r2, [pc, #44] @ (8007884 ) 8007856: 687b ldr r3, [r7, #4] 8007858: f043 0301 orr.w r3, r3, #1 800785c: 6053 str r3, [r2, #4] /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 800785e: 4b0a ldr r3, [pc, #40] @ (8007888 ) 8007860: 6a5b ldr r3, [r3, #36] @ 0x24 8007862: 4a09 ldr r2, [pc, #36] @ (8007888 ) 8007864: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8007868: 6253 str r3, [r2, #36] @ 0x24 __ASM volatile ("dsb 0xF":::"memory"); 800786a: f3bf 8f4f dsb sy } 800786e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8007870: f3bf 8f6f isb sy } 8007874: bf00 nop /* Ensure MPU setting take effects */ __DSB(); __ISB(); } 8007876: bf00 nop 8007878: 370c adds r7, #12 800787a: 46bd mov sp, r7 800787c: f85d 7b04 ldr.w r7, [sp], #4 8007880: 4770 bx lr 8007882: bf00 nop 8007884: e000ed90 .word 0xe000ed90 8007888: e000ed00 .word 0xe000ed00 0800788c : * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) { 800788c: b480 push {r7} 800788e: b083 sub sp, #12 8007890: af00 add r7, sp, #0 8007892: 6078 str r0, [r7, #4] assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; 8007894: 687b ldr r3, [r7, #4] 8007896: 785a ldrb r2, [r3, #1] 8007898: 4b1b ldr r3, [pc, #108] @ (8007908 ) 800789a: 609a str r2, [r3, #8] /* Disable the Region */ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 800789c: 4b1a ldr r3, [pc, #104] @ (8007908 ) 800789e: 691b ldr r3, [r3, #16] 80078a0: 4a19 ldr r2, [pc, #100] @ (8007908 ) 80078a2: f023 0301 bic.w r3, r3, #1 80078a6: 6113 str r3, [r2, #16] /* Apply configuration */ MPU->RBAR = MPU_Init->BaseAddress; 80078a8: 4a17 ldr r2, [pc, #92] @ (8007908 ) 80078aa: 687b ldr r3, [r7, #4] 80078ac: 685b ldr r3, [r3, #4] 80078ae: 60d3 str r3, [r2, #12] MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 80078b0: 687b ldr r3, [r7, #4] 80078b2: 7b1b ldrb r3, [r3, #12] 80078b4: 071a lsls r2, r3, #28 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 80078b6: 687b ldr r3, [r7, #4] 80078b8: 7adb ldrb r3, [r3, #11] 80078ba: 061b lsls r3, r3, #24 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 80078bc: 431a orrs r2, r3 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 80078be: 687b ldr r3, [r7, #4] 80078c0: 7a9b ldrb r3, [r3, #10] 80078c2: 04db lsls r3, r3, #19 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 80078c4: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 80078c6: 687b ldr r3, [r7, #4] 80078c8: 7b5b ldrb r3, [r3, #13] 80078ca: 049b lsls r3, r3, #18 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 80078cc: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 80078ce: 687b ldr r3, [r7, #4] 80078d0: 7b9b ldrb r3, [r3, #14] 80078d2: 045b lsls r3, r3, #17 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 80078d4: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 80078d6: 687b ldr r3, [r7, #4] 80078d8: 7bdb ldrb r3, [r3, #15] 80078da: 041b lsls r3, r3, #16 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 80078dc: 431a orrs r2, r3 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 80078de: 687b ldr r3, [r7, #4] 80078e0: 7a5b ldrb r3, [r3, #9] 80078e2: 021b lsls r3, r3, #8 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 80078e4: 431a orrs r2, r3 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 80078e6: 687b ldr r3, [r7, #4] 80078e8: 7a1b ldrb r3, [r3, #8] 80078ea: 005b lsls r3, r3, #1 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 80078ec: 4313 orrs r3, r2 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); 80078ee: 687a ldr r2, [r7, #4] 80078f0: 7812 ldrb r2, [r2, #0] 80078f2: 4611 mov r1, r2 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 80078f4: 4a04 ldr r2, [pc, #16] @ (8007908 ) ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 80078f6: 430b orrs r3, r1 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 80078f8: 6113 str r3, [r2, #16] } 80078fa: bf00 nop 80078fc: 370c adds r7, #12 80078fe: 46bd mov sp, r7 8007900: f85d 7b04 ldr.w r7, [sp], #4 8007904: 4770 bx lr 8007906: bf00 nop 8007908: e000ed90 .word 0xe000ed90 0800790c : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 800790c: b580 push {r7, lr} 800790e: b082 sub sp, #8 8007910: af00 add r7, sp, #0 8007912: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 8007914: 687b ldr r3, [r7, #4] 8007916: 2b00 cmp r3, #0 8007918: d101 bne.n 800791e { return HAL_ERROR; 800791a: 2301 movs r3, #1 800791c: e054 b.n 80079c8 } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 800791e: 687b ldr r3, [r7, #4] 8007920: 7f5b ldrb r3, [r3, #29] 8007922: b2db uxtb r3, r3 8007924: 2b00 cmp r3, #0 8007926: d105 bne.n 8007934 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 8007928: 687b ldr r3, [r7, #4] 800792a: 2200 movs r2, #0 800792c: 771a strb r2, [r3, #28] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 800792e: 6878 ldr r0, [r7, #4] 8007930: f7fc f988 bl 8003c44 } hcrc->State = HAL_CRC_STATE_BUSY; 8007934: 687b ldr r3, [r7, #4] 8007936: 2202 movs r2, #2 8007938: 775a strb r2, [r3, #29] /* check whether or not non-default generating polynomial has been * picked up by user */ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) 800793a: 687b ldr r3, [r7, #4] 800793c: 791b ldrb r3, [r3, #4] 800793e: 2b00 cmp r3, #0 8007940: d10c bne.n 800795c { /* initialize peripheral with default generating polynomial */ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); 8007942: 687b ldr r3, [r7, #4] 8007944: 681b ldr r3, [r3, #0] 8007946: 4a22 ldr r2, [pc, #136] @ (80079d0 ) 8007948: 615a str r2, [r3, #20] MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); 800794a: 687b ldr r3, [r7, #4] 800794c: 681b ldr r3, [r3, #0] 800794e: 689a ldr r2, [r3, #8] 8007950: 687b ldr r3, [r7, #4] 8007952: 681b ldr r3, [r3, #0] 8007954: f022 0218 bic.w r2, r2, #24 8007958: 609a str r2, [r3, #8] 800795a: e00c b.n 8007976 } else { /* initialize CRC peripheral with generating polynomial defined by user */ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) 800795c: 687b ldr r3, [r7, #4] 800795e: 6899 ldr r1, [r3, #8] 8007960: 687b ldr r3, [r7, #4] 8007962: 68db ldr r3, [r3, #12] 8007964: 461a mov r2, r3 8007966: 6878 ldr r0, [r7, #4] 8007968: f000 f948 bl 8007bfc 800796c: 4603 mov r3, r0 800796e: 2b00 cmp r3, #0 8007970: d001 beq.n 8007976 { return HAL_ERROR; 8007972: 2301 movs r3, #1 8007974: e028 b.n 80079c8 } /* check whether or not non-default CRC initial value has been * picked up by user */ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) 8007976: 687b ldr r3, [r7, #4] 8007978: 795b ldrb r3, [r3, #5] 800797a: 2b00 cmp r3, #0 800797c: d105 bne.n 800798a { WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); 800797e: 687b ldr r3, [r7, #4] 8007980: 681b ldr r3, [r3, #0] 8007982: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007986: 611a str r2, [r3, #16] 8007988: e004 b.n 8007994 } else { WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); 800798a: 687b ldr r3, [r7, #4] 800798c: 681b ldr r3, [r3, #0] 800798e: 687a ldr r2, [r7, #4] 8007990: 6912 ldr r2, [r2, #16] 8007992: 611a str r2, [r3, #16] } /* set input data inversion mode */ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); 8007994: 687b ldr r3, [r7, #4] 8007996: 681b ldr r3, [r3, #0] 8007998: 689b ldr r3, [r3, #8] 800799a: f023 0160 bic.w r1, r3, #96 @ 0x60 800799e: 687b ldr r3, [r7, #4] 80079a0: 695a ldr r2, [r3, #20] 80079a2: 687b ldr r3, [r7, #4] 80079a4: 681b ldr r3, [r3, #0] 80079a6: 430a orrs r2, r1 80079a8: 609a str r2, [r3, #8] /* set output data inversion mode */ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); 80079aa: 687b ldr r3, [r7, #4] 80079ac: 681b ldr r3, [r3, #0] 80079ae: 689b ldr r3, [r3, #8] 80079b0: f023 0180 bic.w r1, r3, #128 @ 0x80 80079b4: 687b ldr r3, [r7, #4] 80079b6: 699a ldr r2, [r3, #24] 80079b8: 687b ldr r3, [r7, #4] 80079ba: 681b ldr r3, [r3, #0] 80079bc: 430a orrs r2, r1 80079be: 609a str r2, [r3, #8] /* makes sure the input data format (bytes, halfwords or words stream) * is properly specified by user */ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 80079c0: 687b ldr r3, [r7, #4] 80079c2: 2201 movs r2, #1 80079c4: 775a strb r2, [r3, #29] /* Return function status */ return HAL_OK; 80079c6: 2300 movs r3, #0 } 80079c8: 4618 mov r0, r3 80079ca: 3708 adds r7, #8 80079cc: 46bd mov sp, r7 80079ce: bd80 pop {r7, pc} 80079d0: 04c11db7 .word 0x04c11db7 080079d4 : * and the API will internally adjust its input data processing based on the * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { 80079d4: b580 push {r7, lr} 80079d6: b086 sub sp, #24 80079d8: af00 add r7, sp, #0 80079da: 60f8 str r0, [r7, #12] 80079dc: 60b9 str r1, [r7, #8] 80079de: 607a str r2, [r7, #4] uint32_t index; /* CRC input data buffer index */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ 80079e0: 2300 movs r3, #0 80079e2: 613b str r3, [r7, #16] /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; 80079e4: 68fb ldr r3, [r7, #12] 80079e6: 2202 movs r2, #2 80079e8: 775a strb r2, [r3, #29] /* Reset CRC Calculation Unit (hcrc->Instance->INIT is * written in hcrc->Instance->DR) */ __HAL_CRC_DR_RESET(hcrc); 80079ea: 68fb ldr r3, [r7, #12] 80079ec: 681b ldr r3, [r3, #0] 80079ee: 689a ldr r2, [r3, #8] 80079f0: 68fb ldr r3, [r7, #12] 80079f2: 681b ldr r3, [r3, #0] 80079f4: f042 0201 orr.w r2, r2, #1 80079f8: 609a str r2, [r3, #8] switch (hcrc->InputDataFormat) 80079fa: 68fb ldr r3, [r7, #12] 80079fc: 6a1b ldr r3, [r3, #32] 80079fe: 2b03 cmp r3, #3 8007a00: d006 beq.n 8007a10 8007a02: 2b03 cmp r3, #3 8007a04: d829 bhi.n 8007a5a 8007a06: 2b01 cmp r3, #1 8007a08: d019 beq.n 8007a3e 8007a0a: 2b02 cmp r3, #2 8007a0c: d01e beq.n 8007a4c /* Specific 16-bit input data handling */ temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: break; 8007a0e: e024 b.n 8007a5a for (index = 0U; index < BufferLength; index++) 8007a10: 2300 movs r3, #0 8007a12: 617b str r3, [r7, #20] 8007a14: e00a b.n 8007a2c hcrc->Instance->DR = pBuffer[index]; 8007a16: 697b ldr r3, [r7, #20] 8007a18: 009b lsls r3, r3, #2 8007a1a: 68ba ldr r2, [r7, #8] 8007a1c: 441a add r2, r3 8007a1e: 68fb ldr r3, [r7, #12] 8007a20: 681b ldr r3, [r3, #0] 8007a22: 6812 ldr r2, [r2, #0] 8007a24: 601a str r2, [r3, #0] for (index = 0U; index < BufferLength; index++) 8007a26: 697b ldr r3, [r7, #20] 8007a28: 3301 adds r3, #1 8007a2a: 617b str r3, [r7, #20] 8007a2c: 697a ldr r2, [r7, #20] 8007a2e: 687b ldr r3, [r7, #4] 8007a30: 429a cmp r2, r3 8007a32: d3f0 bcc.n 8007a16 temp = hcrc->Instance->DR; 8007a34: 68fb ldr r3, [r7, #12] 8007a36: 681b ldr r3, [r3, #0] 8007a38: 681b ldr r3, [r3, #0] 8007a3a: 613b str r3, [r7, #16] break; 8007a3c: e00e b.n 8007a5c temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); 8007a3e: 687a ldr r2, [r7, #4] 8007a40: 68b9 ldr r1, [r7, #8] 8007a42: 68f8 ldr r0, [r7, #12] 8007a44: f000 f812 bl 8007a6c 8007a48: 6138 str r0, [r7, #16] break; 8007a4a: e007 b.n 8007a5c temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ 8007a4c: 687a ldr r2, [r7, #4] 8007a4e: 68b9 ldr r1, [r7, #8] 8007a50: 68f8 ldr r0, [r7, #12] 8007a52: f000 f899 bl 8007b88 8007a56: 6138 str r0, [r7, #16] break; 8007a58: e000 b.n 8007a5c break; 8007a5a: bf00 nop } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 8007a5c: 68fb ldr r3, [r7, #12] 8007a5e: 2201 movs r2, #1 8007a60: 775a strb r2, [r3, #29] /* Return the CRC computed value */ return temp; 8007a62: 693b ldr r3, [r7, #16] } 8007a64: 4618 mov r0, r3 8007a66: 3718 adds r7, #24 8007a68: 46bd mov sp, r7 8007a6a: bd80 pop {r7, pc} 08007a6c : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { 8007a6c: b480 push {r7} 8007a6e: b089 sub sp, #36 @ 0x24 8007a70: af00 add r7, sp, #0 8007a72: 60f8 str r0, [r7, #12] 8007a74: 60b9 str r1, [r7, #8] 8007a76: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 4 bytes are entered in a row with a single word write, * last bytes must be carefully fed to the CRC calculator to ensure a correct type * handling by the peripheral */ for (i = 0U; i < (BufferLength / 4U); i++) 8007a78: 2300 movs r3, #0 8007a7a: 61fb str r3, [r7, #28] 8007a7c: e023 b.n 8007ac6 { hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007a7e: 69fb ldr r3, [r7, #28] 8007a80: 009b lsls r3, r3, #2 8007a82: 68ba ldr r2, [r7, #8] 8007a84: 4413 add r3, r2 8007a86: 781b ldrb r3, [r3, #0] 8007a88: 061a lsls r2, r3, #24 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8007a8a: 69fb ldr r3, [r7, #28] 8007a8c: 009b lsls r3, r3, #2 8007a8e: 3301 adds r3, #1 8007a90: 68b9 ldr r1, [r7, #8] 8007a92: 440b add r3, r1 8007a94: 781b ldrb r3, [r3, #0] 8007a96: 041b lsls r3, r3, #16 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007a98: 431a orrs r2, r3 ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 8007a9a: 69fb ldr r3, [r7, #28] 8007a9c: 009b lsls r3, r3, #2 8007a9e: 3302 adds r3, #2 8007aa0: 68b9 ldr r1, [r7, #8] 8007aa2: 440b add r3, r1 8007aa4: 781b ldrb r3, [r3, #0] 8007aa6: 021b lsls r3, r3, #8 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8007aa8: 431a orrs r2, r3 (uint32_t)pBuffer[(4U * i) + 3U]; 8007aaa: 69fb ldr r3, [r7, #28] 8007aac: 009b lsls r3, r3, #2 8007aae: 3303 adds r3, #3 8007ab0: 68b9 ldr r1, [r7, #8] 8007ab2: 440b add r3, r1 8007ab4: 781b ldrb r3, [r3, #0] 8007ab6: 4619 mov r1, r3 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007ab8: 68fb ldr r3, [r7, #12] 8007aba: 681b ldr r3, [r3, #0] ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 8007abc: 430a orrs r2, r1 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007abe: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 4U); i++) 8007ac0: 69fb ldr r3, [r7, #28] 8007ac2: 3301 adds r3, #1 8007ac4: 61fb str r3, [r7, #28] 8007ac6: 687b ldr r3, [r7, #4] 8007ac8: 089b lsrs r3, r3, #2 8007aca: 69fa ldr r2, [r7, #28] 8007acc: 429a cmp r2, r3 8007ace: d3d6 bcc.n 8007a7e } /* last bytes specific handling */ if ((BufferLength % 4U) != 0U) 8007ad0: 687b ldr r3, [r7, #4] 8007ad2: f003 0303 and.w r3, r3, #3 8007ad6: 2b00 cmp r3, #0 8007ad8: d04d beq.n 8007b76 { if ((BufferLength % 4U) == 1U) 8007ada: 687b ldr r3, [r7, #4] 8007adc: f003 0303 and.w r3, r3, #3 8007ae0: 2b01 cmp r3, #1 8007ae2: d107 bne.n 8007af4 { *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ 8007ae4: 69fb ldr r3, [r7, #28] 8007ae6: 009b lsls r3, r3, #2 8007ae8: 68ba ldr r2, [r7, #8] 8007aea: 4413 add r3, r2 8007aec: 68fa ldr r2, [r7, #12] 8007aee: 6812 ldr r2, [r2, #0] 8007af0: 781b ldrb r3, [r3, #0] 8007af2: 7013 strb r3, [r2, #0] } if ((BufferLength % 4U) == 2U) 8007af4: 687b ldr r3, [r7, #4] 8007af6: f003 0303 and.w r3, r3, #3 8007afa: 2b02 cmp r3, #2 8007afc: d116 bne.n 8007b2c { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 8007afe: 69fb ldr r3, [r7, #28] 8007b00: 009b lsls r3, r3, #2 8007b02: 68ba ldr r2, [r7, #8] 8007b04: 4413 add r3, r2 8007b06: 781b ldrb r3, [r3, #0] 8007b08: 021b lsls r3, r3, #8 8007b0a: b21a sxth r2, r3 8007b0c: 69fb ldr r3, [r7, #28] 8007b0e: 009b lsls r3, r3, #2 8007b10: 3301 adds r3, #1 8007b12: 68b9 ldr r1, [r7, #8] 8007b14: 440b add r3, r1 8007b16: 781b ldrb r3, [r3, #0] 8007b18: b21b sxth r3, r3 8007b1a: 4313 orrs r3, r2 8007b1c: b21b sxth r3, r3 8007b1e: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007b20: 68fb ldr r3, [r7, #12] 8007b22: 681b ldr r3, [r3, #0] 8007b24: 617b str r3, [r7, #20] *pReg = data; 8007b26: 697b ldr r3, [r7, #20] 8007b28: 8b7a ldrh r2, [r7, #26] 8007b2a: 801a strh r2, [r3, #0] } if ((BufferLength % 4U) == 3U) 8007b2c: 687b ldr r3, [r7, #4] 8007b2e: f003 0303 and.w r3, r3, #3 8007b32: 2b03 cmp r3, #3 8007b34: d11f bne.n 8007b76 { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 8007b36: 69fb ldr r3, [r7, #28] 8007b38: 009b lsls r3, r3, #2 8007b3a: 68ba ldr r2, [r7, #8] 8007b3c: 4413 add r3, r2 8007b3e: 781b ldrb r3, [r3, #0] 8007b40: 021b lsls r3, r3, #8 8007b42: b21a sxth r2, r3 8007b44: 69fb ldr r3, [r7, #28] 8007b46: 009b lsls r3, r3, #2 8007b48: 3301 adds r3, #1 8007b4a: 68b9 ldr r1, [r7, #8] 8007b4c: 440b add r3, r1 8007b4e: 781b ldrb r3, [r3, #0] 8007b50: b21b sxth r3, r3 8007b52: 4313 orrs r3, r2 8007b54: b21b sxth r3, r3 8007b56: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007b58: 68fb ldr r3, [r7, #12] 8007b5a: 681b ldr r3, [r3, #0] 8007b5c: 617b str r3, [r7, #20] *pReg = data; 8007b5e: 697b ldr r3, [r7, #20] 8007b60: 8b7a ldrh r2, [r7, #26] 8007b62: 801a strh r2, [r3, #0] *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ 8007b64: 69fb ldr r3, [r7, #28] 8007b66: 009b lsls r3, r3, #2 8007b68: 3302 adds r3, #2 8007b6a: 68ba ldr r2, [r7, #8] 8007b6c: 4413 add r3, r2 8007b6e: 68fa ldr r2, [r7, #12] 8007b70: 6812 ldr r2, [r2, #0] 8007b72: 781b ldrb r3, [r3, #0] 8007b74: 7013 strb r3, [r2, #0] } } /* Return the CRC computed value */ return hcrc->Instance->DR; 8007b76: 68fb ldr r3, [r7, #12] 8007b78: 681b ldr r3, [r3, #0] 8007b7a: 681b ldr r3, [r3, #0] } 8007b7c: 4618 mov r0, r3 8007b7e: 3724 adds r7, #36 @ 0x24 8007b80: 46bd mov sp, r7 8007b82: f85d 7b04 ldr.w r7, [sp], #4 8007b86: 4770 bx lr 08007b88 : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { 8007b88: b480 push {r7} 8007b8a: b087 sub sp, #28 8007b8c: af00 add r7, sp, #0 8007b8e: 60f8 str r0, [r7, #12] 8007b90: 60b9 str r1, [r7, #8] 8007b92: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the peripheral */ for (i = 0U; i < (BufferLength / 2U); i++) 8007b94: 2300 movs r3, #0 8007b96: 617b str r3, [r7, #20] 8007b98: e013 b.n 8007bc2 { hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; 8007b9a: 697b ldr r3, [r7, #20] 8007b9c: 009b lsls r3, r3, #2 8007b9e: 68ba ldr r2, [r7, #8] 8007ba0: 4413 add r3, r2 8007ba2: 881b ldrh r3, [r3, #0] 8007ba4: 041a lsls r2, r3, #16 8007ba6: 697b ldr r3, [r7, #20] 8007ba8: 009b lsls r3, r3, #2 8007baa: 3302 adds r3, #2 8007bac: 68b9 ldr r1, [r7, #8] 8007bae: 440b add r3, r1 8007bb0: 881b ldrh r3, [r3, #0] 8007bb2: 4619 mov r1, r3 8007bb4: 68fb ldr r3, [r7, #12] 8007bb6: 681b ldr r3, [r3, #0] 8007bb8: 430a orrs r2, r1 8007bba: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 2U); i++) 8007bbc: 697b ldr r3, [r7, #20] 8007bbe: 3301 adds r3, #1 8007bc0: 617b str r3, [r7, #20] 8007bc2: 687b ldr r3, [r7, #4] 8007bc4: 085b lsrs r3, r3, #1 8007bc6: 697a ldr r2, [r7, #20] 8007bc8: 429a cmp r2, r3 8007bca: d3e6 bcc.n 8007b9a } if ((BufferLength % 2U) != 0U) 8007bcc: 687b ldr r3, [r7, #4] 8007bce: f003 0301 and.w r3, r3, #1 8007bd2: 2b00 cmp r3, #0 8007bd4: d009 beq.n 8007bea { pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007bd6: 68fb ldr r3, [r7, #12] 8007bd8: 681b ldr r3, [r3, #0] 8007bda: 613b str r3, [r7, #16] *pReg = pBuffer[2U * i]; 8007bdc: 697b ldr r3, [r7, #20] 8007bde: 009b lsls r3, r3, #2 8007be0: 68ba ldr r2, [r7, #8] 8007be2: 4413 add r3, r2 8007be4: 881a ldrh r2, [r3, #0] 8007be6: 693b ldr r3, [r7, #16] 8007be8: 801a strh r2, [r3, #0] } /* Return the CRC computed value */ return hcrc->Instance->DR; 8007bea: 68fb ldr r3, [r7, #12] 8007bec: 681b ldr r3, [r3, #0] 8007bee: 681b ldr r3, [r3, #0] } 8007bf0: 4618 mov r0, r3 8007bf2: 371c adds r7, #28 8007bf4: 46bd mov sp, r7 8007bf6: f85d 7b04 ldr.w r7, [sp], #4 8007bfa: 4770 bx lr 08007bfc : * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) { 8007bfc: b480 push {r7} 8007bfe: b087 sub sp, #28 8007c00: af00 add r7, sp, #0 8007c02: 60f8 str r0, [r7, #12] 8007c04: 60b9 str r1, [r7, #8] 8007c06: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8007c08: 2300 movs r3, #0 8007c0a: 75fb strb r3, [r7, #23] uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ 8007c0c: 231f movs r3, #31 8007c0e: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); /* Ensure that the generating polynomial is odd */ if ((Pol & (uint32_t)(0x1U)) == 0U) 8007c10: 68bb ldr r3, [r7, #8] 8007c12: f003 0301 and.w r3, r3, #1 8007c16: 2b00 cmp r3, #0 8007c18: d102 bne.n 8007c20 { status = HAL_ERROR; 8007c1a: 2301 movs r3, #1 8007c1c: 75fb strb r3, [r7, #23] 8007c1e: e063 b.n 8007ce8 * definition. HAL_ERROR is reported if Pol degree is * larger than that indicated by PolyLength. * Look for MSB position: msb will contain the degree of * the second to the largest polynomial member. E.g., for * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) 8007c20: bf00 nop 8007c22: 693b ldr r3, [r7, #16] 8007c24: 1e5a subs r2, r3, #1 8007c26: 613a str r2, [r7, #16] 8007c28: 2b00 cmp r3, #0 8007c2a: d009 beq.n 8007c40 8007c2c: 693b ldr r3, [r7, #16] 8007c2e: f003 031f and.w r3, r3, #31 8007c32: 68ba ldr r2, [r7, #8] 8007c34: fa22 f303 lsr.w r3, r2, r3 8007c38: f003 0301 and.w r3, r3, #1 8007c3c: 2b00 cmp r3, #0 8007c3e: d0f0 beq.n 8007c22 { } switch (PolyLength) 8007c40: 687b ldr r3, [r7, #4] 8007c42: 2b18 cmp r3, #24 8007c44: d846 bhi.n 8007cd4 8007c46: a201 add r2, pc, #4 @ (adr r2, 8007c4c ) 8007c48: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007c4c: 08007cdb .word 0x08007cdb 8007c50: 08007cd5 .word 0x08007cd5 8007c54: 08007cd5 .word 0x08007cd5 8007c58: 08007cd5 .word 0x08007cd5 8007c5c: 08007cd5 .word 0x08007cd5 8007c60: 08007cd5 .word 0x08007cd5 8007c64: 08007cd5 .word 0x08007cd5 8007c68: 08007cd5 .word 0x08007cd5 8007c6c: 08007cc9 .word 0x08007cc9 8007c70: 08007cd5 .word 0x08007cd5 8007c74: 08007cd5 .word 0x08007cd5 8007c78: 08007cd5 .word 0x08007cd5 8007c7c: 08007cd5 .word 0x08007cd5 8007c80: 08007cd5 .word 0x08007cd5 8007c84: 08007cd5 .word 0x08007cd5 8007c88: 08007cd5 .word 0x08007cd5 8007c8c: 08007cbd .word 0x08007cbd 8007c90: 08007cd5 .word 0x08007cd5 8007c94: 08007cd5 .word 0x08007cd5 8007c98: 08007cd5 .word 0x08007cd5 8007c9c: 08007cd5 .word 0x08007cd5 8007ca0: 08007cd5 .word 0x08007cd5 8007ca4: 08007cd5 .word 0x08007cd5 8007ca8: 08007cd5 .word 0x08007cd5 8007cac: 08007cb1 .word 0x08007cb1 { case CRC_POLYLENGTH_7B: if (msb >= HAL_CRC_LENGTH_7B) 8007cb0: 693b ldr r3, [r7, #16] 8007cb2: 2b06 cmp r3, #6 8007cb4: d913 bls.n 8007cde { status = HAL_ERROR; 8007cb6: 2301 movs r3, #1 8007cb8: 75fb strb r3, [r7, #23] } break; 8007cba: e010 b.n 8007cde case CRC_POLYLENGTH_8B: if (msb >= HAL_CRC_LENGTH_8B) 8007cbc: 693b ldr r3, [r7, #16] 8007cbe: 2b07 cmp r3, #7 8007cc0: d90f bls.n 8007ce2 { status = HAL_ERROR; 8007cc2: 2301 movs r3, #1 8007cc4: 75fb strb r3, [r7, #23] } break; 8007cc6: e00c b.n 8007ce2 case CRC_POLYLENGTH_16B: if (msb >= HAL_CRC_LENGTH_16B) 8007cc8: 693b ldr r3, [r7, #16] 8007cca: 2b0f cmp r3, #15 8007ccc: d90b bls.n 8007ce6 { status = HAL_ERROR; 8007cce: 2301 movs r3, #1 8007cd0: 75fb strb r3, [r7, #23] } break; 8007cd2: e008 b.n 8007ce6 case CRC_POLYLENGTH_32B: /* no polynomial definition vs. polynomial length issue possible */ break; default: status = HAL_ERROR; 8007cd4: 2301 movs r3, #1 8007cd6: 75fb strb r3, [r7, #23] break; 8007cd8: e006 b.n 8007ce8 break; 8007cda: bf00 nop 8007cdc: e004 b.n 8007ce8 break; 8007cde: bf00 nop 8007ce0: e002 b.n 8007ce8 break; 8007ce2: bf00 nop 8007ce4: e000 b.n 8007ce8 break; 8007ce6: bf00 nop } } if (status == HAL_OK) 8007ce8: 7dfb ldrb r3, [r7, #23] 8007cea: 2b00 cmp r3, #0 8007cec: d10d bne.n 8007d0a { /* set generating polynomial */ WRITE_REG(hcrc->Instance->POL, Pol); 8007cee: 68fb ldr r3, [r7, #12] 8007cf0: 681b ldr r3, [r3, #0] 8007cf2: 68ba ldr r2, [r7, #8] 8007cf4: 615a str r2, [r3, #20] /* set generating polynomial size */ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); 8007cf6: 68fb ldr r3, [r7, #12] 8007cf8: 681b ldr r3, [r3, #0] 8007cfa: 689b ldr r3, [r3, #8] 8007cfc: f023 0118 bic.w r1, r3, #24 8007d00: 68fb ldr r3, [r7, #12] 8007d02: 681b ldr r3, [r3, #0] 8007d04: 687a ldr r2, [r7, #4] 8007d06: 430a orrs r2, r1 8007d08: 609a str r2, [r3, #8] } /* Return function status */ return status; 8007d0a: 7dfb ldrb r3, [r7, #23] } 8007d0c: 4618 mov r0, r3 8007d0e: 371c adds r7, #28 8007d10: 46bd mov sp, r7 8007d12: f85d 7b04 ldr.w r7, [sp], #4 8007d16: 4770 bx lr 08007d18 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { 8007d18: b580 push {r7, lr} 8007d1a: b082 sub sp, #8 8007d1c: af00 add r7, sp, #0 8007d1e: 6078 str r0, [r7, #4] /* Check the DAC peripheral handle */ if (hdac == NULL) 8007d20: 687b ldr r3, [r7, #4] 8007d22: 2b00 cmp r3, #0 8007d24: d101 bne.n 8007d2a { return HAL_ERROR; 8007d26: 2301 movs r3, #1 8007d28: e014 b.n 8007d54 } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); if (hdac->State == HAL_DAC_STATE_RESET) 8007d2a: 687b ldr r3, [r7, #4] 8007d2c: 791b ldrb r3, [r3, #4] 8007d2e: b2db uxtb r3, r3 8007d30: 2b00 cmp r3, #0 8007d32: d105 bne.n 8007d40 hdac->MspInitCallback = HAL_DAC_MspInit; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /* Allocate lock resource and initialize it */ hdac->Lock = HAL_UNLOCKED; 8007d34: 687b ldr r3, [r7, #4] 8007d36: 2200 movs r2, #0 8007d38: 715a strb r2, [r3, #5] #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* Init the low level hardware */ hdac->MspInitCallback(hdac); #else /* Init the low level hardware */ HAL_DAC_MspInit(hdac); 8007d3a: 6878 ldr r0, [r7, #4] 8007d3c: f7fb ffa4 bl 8003c88 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; 8007d40: 687b ldr r3, [r7, #4] 8007d42: 2202 movs r2, #2 8007d44: 711a strb r2, [r3, #4] /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; 8007d46: 687b ldr r3, [r7, #4] 8007d48: 2200 movs r2, #0 8007d4a: 611a str r2, [r3, #16] /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; 8007d4c: 687b ldr r3, [r7, #4] 8007d4e: 2201 movs r2, #1 8007d50: 711a strb r2, [r3, #4] /* Return function status */ return HAL_OK; 8007d52: 2300 movs r3, #0 } 8007d54: 4618 mov r0, r3 8007d56: 3708 adds r7, #8 8007d58: 46bd mov sp, r7 8007d5a: bd80 pop {r7, pc} 08007d5c : * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { 8007d5c: b480 push {r7} 8007d5e: b083 sub sp, #12 8007d60: af00 add r7, sp, #0 8007d62: 6078 str r0, [r7, #4] 8007d64: 6039 str r1, [r7, #0] /* Check the DAC peripheral handle */ if (hdac == NULL) 8007d66: 687b ldr r3, [r7, #4] 8007d68: 2b00 cmp r3, #0 8007d6a: d101 bne.n 8007d70 { return HAL_ERROR; 8007d6c: 2301 movs r3, #1 8007d6e: e046 b.n 8007dfe /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 8007d70: 687b ldr r3, [r7, #4] 8007d72: 795b ldrb r3, [r3, #5] 8007d74: 2b01 cmp r3, #1 8007d76: d101 bne.n 8007d7c 8007d78: 2302 movs r3, #2 8007d7a: e040 b.n 8007dfe 8007d7c: 687b ldr r3, [r7, #4] 8007d7e: 2201 movs r2, #1 8007d80: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 8007d82: 687b ldr r3, [r7, #4] 8007d84: 2202 movs r2, #2 8007d86: 711a strb r2, [r3, #4] /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); 8007d88: 687b ldr r3, [r7, #4] 8007d8a: 681b ldr r3, [r3, #0] 8007d8c: 6819 ldr r1, [r3, #0] 8007d8e: 683b ldr r3, [r7, #0] 8007d90: f003 0310 and.w r3, r3, #16 8007d94: 2201 movs r2, #1 8007d96: 409a lsls r2, r3 8007d98: 687b ldr r3, [r7, #4] 8007d9a: 681b ldr r3, [r3, #0] 8007d9c: 430a orrs r2, r1 8007d9e: 601a str r2, [r3, #0] if (Channel == DAC_CHANNEL_1) 8007da0: 683b ldr r3, [r7, #0] 8007da2: 2b00 cmp r3, #0 8007da4: d10f bne.n 8007dc6 { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) 8007da6: 687b ldr r3, [r7, #4] 8007da8: 681b ldr r3, [r3, #0] 8007daa: 681b ldr r3, [r3, #0] 8007dac: f003 033e and.w r3, r3, #62 @ 0x3e 8007db0: 2b02 cmp r3, #2 8007db2: d11d bne.n 8007df0 { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); 8007db4: 687b ldr r3, [r7, #4] 8007db6: 681b ldr r3, [r3, #0] 8007db8: 685a ldr r2, [r3, #4] 8007dba: 687b ldr r3, [r7, #4] 8007dbc: 681b ldr r3, [r3, #0] 8007dbe: f042 0201 orr.w r2, r2, #1 8007dc2: 605a str r2, [r3, #4] 8007dc4: e014 b.n 8007df0 } else { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) 8007dc6: 687b ldr r3, [r7, #4] 8007dc8: 681b ldr r3, [r3, #0] 8007dca: 681b ldr r3, [r3, #0] 8007dcc: f403 1278 and.w r2, r3, #4063232 @ 0x3e0000 8007dd0: 683b ldr r3, [r7, #0] 8007dd2: f003 0310 and.w r3, r3, #16 8007dd6: 2102 movs r1, #2 8007dd8: fa01 f303 lsl.w r3, r1, r3 8007ddc: 429a cmp r2, r3 8007dde: d107 bne.n 8007df0 { /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); 8007de0: 687b ldr r3, [r7, #4] 8007de2: 681b ldr r3, [r3, #0] 8007de4: 685a ldr r2, [r3, #4] 8007de6: 687b ldr r3, [r7, #4] 8007de8: 681b ldr r3, [r3, #0] 8007dea: f042 0202 orr.w r2, r2, #2 8007dee: 605a str r2, [r3, #4] } } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 8007df0: 687b ldr r3, [r7, #4] 8007df2: 2201 movs r2, #1 8007df4: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 8007df6: 687b ldr r3, [r7, #4] 8007df8: 2200 movs r2, #0 8007dfa: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 8007dfc: 2300 movs r3, #0 } 8007dfe: 4618 mov r0, r3 8007e00: 370c adds r7, #12 8007e02: 46bd mov sp, r7 8007e04: f85d 7b04 ldr.w r7, [sp], #4 8007e08: 4770 bx lr 08007e0a : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { 8007e0a: b580 push {r7, lr} 8007e0c: b084 sub sp, #16 8007e0e: af00 add r7, sp, #0 8007e10: 6078 str r0, [r7, #4] uint32_t itsource = hdac->Instance->CR; 8007e12: 687b ldr r3, [r7, #4] 8007e14: 681b ldr r3, [r3, #0] 8007e16: 681b ldr r3, [r3, #0] 8007e18: 60fb str r3, [r7, #12] uint32_t itflag = hdac->Instance->SR; 8007e1a: 687b ldr r3, [r7, #4] 8007e1c: 681b ldr r3, [r3, #0] 8007e1e: 6b5b ldr r3, [r3, #52] @ 0x34 8007e20: 60bb str r3, [r7, #8] if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1) 8007e22: 68fb ldr r3, [r7, #12] 8007e24: f403 5300 and.w r3, r3, #8192 @ 0x2000 8007e28: 2b00 cmp r3, #0 8007e2a: d01d beq.n 8007e68 { /* Check underrun flag of DAC channel 1 */ if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1) 8007e2c: 68bb ldr r3, [r7, #8] 8007e2e: f403 5300 and.w r3, r3, #8192 @ 0x2000 8007e32: 2b00 cmp r3, #0 8007e34: d018 beq.n 8007e68 { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; 8007e36: 687b ldr r3, [r7, #4] 8007e38: 2204 movs r2, #4 8007e3a: 711a strb r2, [r3, #4] /* Set DAC error code to channel1 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); 8007e3c: 687b ldr r3, [r7, #4] 8007e3e: 691b ldr r3, [r3, #16] 8007e40: f043 0201 orr.w r2, r3, #1 8007e44: 687b ldr r3, [r7, #4] 8007e46: 611a str r2, [r3, #16] /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); 8007e48: 687b ldr r3, [r7, #4] 8007e4a: 681b ldr r3, [r3, #0] 8007e4c: f44f 5200 mov.w r2, #8192 @ 0x2000 8007e50: 635a str r2, [r3, #52] @ 0x34 /* Disable the selected DAC channel1 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1); 8007e52: 687b ldr r3, [r7, #4] 8007e54: 681b ldr r3, [r3, #0] 8007e56: 681a ldr r2, [r3, #0] 8007e58: 687b ldr r3, [r7, #4] 8007e5a: 681b ldr r3, [r3, #0] 8007e5c: f422 5280 bic.w r2, r2, #4096 @ 0x1000 8007e60: 601a str r2, [r3, #0] /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh1(hdac); #else HAL_DAC_DMAUnderrunCallbackCh1(hdac); 8007e62: 6878 ldr r0, [r7, #4] 8007e64: f000 f851 bl 8007f0a #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2) 8007e68: 68fb ldr r3, [r7, #12] 8007e6a: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8007e6e: 2b00 cmp r3, #0 8007e70: d01d beq.n 8007eae { /* Check underrun flag of DAC channel 2 */ if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2) 8007e72: 68bb ldr r3, [r7, #8] 8007e74: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8007e78: 2b00 cmp r3, #0 8007e7a: d018 beq.n 8007eae { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; 8007e7c: 687b ldr r3, [r7, #4] 8007e7e: 2204 movs r2, #4 8007e80: 711a strb r2, [r3, #4] /* Set DAC error code to channel2 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); 8007e82: 687b ldr r3, [r7, #4] 8007e84: 691b ldr r3, [r3, #16] 8007e86: f043 0202 orr.w r2, r3, #2 8007e8a: 687b ldr r3, [r7, #4] 8007e8c: 611a str r2, [r3, #16] /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); 8007e8e: 687b ldr r3, [r7, #4] 8007e90: 681b ldr r3, [r3, #0] 8007e92: f04f 5200 mov.w r2, #536870912 @ 0x20000000 8007e96: 635a str r2, [r3, #52] @ 0x34 /* Disable the selected DAC channel2 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2); 8007e98: 687b ldr r3, [r7, #4] 8007e9a: 681b ldr r3, [r3, #0] 8007e9c: 681a ldr r2, [r3, #0] 8007e9e: 687b ldr r3, [r7, #4] 8007ea0: 681b ldr r3, [r3, #0] 8007ea2: f022 5280 bic.w r2, r2, #268435456 @ 0x10000000 8007ea6: 601a str r2, [r3, #0] /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh2(hdac); #else HAL_DACEx_DMAUnderrunCallbackCh2(hdac); 8007ea8: 6878 ldr r0, [r7, #4] 8007eaa: f000 f97b bl 80081a4 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } } 8007eae: bf00 nop 8007eb0: 3710 adds r7, #16 8007eb2: 46bd mov sp, r7 8007eb4: bd80 pop {r7, pc} 08007eb6 : * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { 8007eb6: b480 push {r7} 8007eb8: b087 sub sp, #28 8007eba: af00 add r7, sp, #0 8007ebc: 60f8 str r0, [r7, #12] 8007ebe: 60b9 str r1, [r7, #8] 8007ec0: 607a str r2, [r7, #4] 8007ec2: 603b str r3, [r7, #0] __IO uint32_t tmp = 0UL; 8007ec4: 2300 movs r3, #0 8007ec6: 617b str r3, [r7, #20] /* Check the DAC peripheral handle */ if (hdac == NULL) 8007ec8: 68fb ldr r3, [r7, #12] 8007eca: 2b00 cmp r3, #0 8007ecc: d101 bne.n 8007ed2 { return HAL_ERROR; 8007ece: 2301 movs r3, #1 8007ed0: e015 b.n 8007efe /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)hdac->Instance; 8007ed2: 68fb ldr r3, [r7, #12] 8007ed4: 681b ldr r3, [r3, #0] 8007ed6: 617b str r3, [r7, #20] if (Channel == DAC_CHANNEL_1) 8007ed8: 68bb ldr r3, [r7, #8] 8007eda: 2b00 cmp r3, #0 8007edc: d105 bne.n 8007eea { tmp += DAC_DHR12R1_ALIGNMENT(Alignment); 8007ede: 697a ldr r2, [r7, #20] 8007ee0: 687b ldr r3, [r7, #4] 8007ee2: 4413 add r3, r2 8007ee4: 3308 adds r3, #8 8007ee6: 617b str r3, [r7, #20] 8007ee8: e004 b.n 8007ef4 } else { tmp += DAC_DHR12R2_ALIGNMENT(Alignment); 8007eea: 697a ldr r2, [r7, #20] 8007eec: 687b ldr r3, [r7, #4] 8007eee: 4413 add r3, r2 8007ef0: 3314 adds r3, #20 8007ef2: 617b str r3, [r7, #20] } /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; 8007ef4: 697b ldr r3, [r7, #20] 8007ef6: 461a mov r2, r3 8007ef8: 683b ldr r3, [r7, #0] 8007efa: 6013 str r3, [r2, #0] /* Return function status */ return HAL_OK; 8007efc: 2300 movs r3, #0 } 8007efe: 4618 mov r0, r3 8007f00: 371c adds r7, #28 8007f02: 46bd mov sp, r7 8007f04: f85d 7b04 ldr.w r7, [sp], #4 8007f08: 4770 bx lr 08007f0a : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) { 8007f0a: b480 push {r7} 8007f0c: b083 sub sp, #12 8007f0e: af00 add r7, sp, #0 8007f10: 6078 str r0, [r7, #4] UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file */ } 8007f12: bf00 nop 8007f14: 370c adds r7, #12 8007f16: 46bd mov sp, r7 8007f18: f85d 7b04 ldr.w r7, [sp], #4 8007f1c: 4770 bx lr ... 08007f20 : * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { 8007f20: b580 push {r7, lr} 8007f22: b08a sub sp, #40 @ 0x28 8007f24: af00 add r7, sp, #0 8007f26: 60f8 str r0, [r7, #12] 8007f28: 60b9 str r1, [r7, #8] 8007f2a: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8007f2c: 2300 movs r3, #0 8007f2e: f887 3023 strb.w r3, [r7, #35] @ 0x23 uint32_t tmpreg2; uint32_t tickstart; uint32_t connectOnChip; /* Check the DAC peripheral handle and channel configuration struct */ if ((hdac == NULL) || (sConfig == NULL)) 8007f32: 68fb ldr r3, [r7, #12] 8007f34: 2b00 cmp r3, #0 8007f36: d002 beq.n 8007f3e 8007f38: 68bb ldr r3, [r7, #8] 8007f3a: 2b00 cmp r3, #0 8007f3c: d101 bne.n 8007f42 { return HAL_ERROR; 8007f3e: 2301 movs r3, #1 8007f40: e12a b.n 8008198 assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 8007f42: 68fb ldr r3, [r7, #12] 8007f44: 795b ldrb r3, [r3, #5] 8007f46: 2b01 cmp r3, #1 8007f48: d101 bne.n 8007f4e 8007f4a: 2302 movs r3, #2 8007f4c: e124 b.n 8008198 8007f4e: 68fb ldr r3, [r7, #12] 8007f50: 2201 movs r2, #1 8007f52: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 8007f54: 68fb ldr r3, [r7, #12] 8007f56: 2202 movs r2, #2 8007f58: 711a strb r2, [r3, #4] /* Sample and hold configuration */ if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) 8007f5a: 68bb ldr r3, [r7, #8] 8007f5c: 681b ldr r3, [r3, #0] 8007f5e: 2b04 cmp r3, #4 8007f60: d17a bne.n 8008058 { /* Get timeout */ tickstart = HAL_GetTick(); 8007f62: f7fd fc9b bl 800589c 8007f66: 61f8 str r0, [r7, #28] if (Channel == DAC_CHANNEL_1) 8007f68: 687b ldr r3, [r7, #4] 8007f6a: 2b00 cmp r3, #0 8007f6c: d13d bne.n 8007fea { /* SHSR1 can be written when BWST1 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 8007f6e: e018 b.n 8007fa2 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8007f70: f7fd fc94 bl 800589c 8007f74: 4602 mov r2, r0 8007f76: 69fb ldr r3, [r7, #28] 8007f78: 1ad3 subs r3, r2, r3 8007f7a: 2b01 cmp r3, #1 8007f7c: d911 bls.n 8007fa2 { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 8007f7e: 68fb ldr r3, [r7, #12] 8007f80: 681b ldr r3, [r3, #0] 8007f82: 6b5a ldr r2, [r3, #52] @ 0x34 8007f84: 4b86 ldr r3, [pc, #536] @ (80081a0 ) 8007f86: 4013 ands r3, r2 8007f88: 2b00 cmp r3, #0 8007f8a: d00a beq.n 8007fa2 { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 8007f8c: 68fb ldr r3, [r7, #12] 8007f8e: 691b ldr r3, [r3, #16] 8007f90: f043 0208 orr.w r2, r3, #8 8007f94: 68fb ldr r3, [r7, #12] 8007f96: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 8007f98: 68fb ldr r3, [r7, #12] 8007f9a: 2203 movs r2, #3 8007f9c: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 8007f9e: 2303 movs r3, #3 8007fa0: e0fa b.n 8008198 while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 8007fa2: 68fb ldr r3, [r7, #12] 8007fa4: 681b ldr r3, [r3, #0] 8007fa6: 6b5a ldr r2, [r3, #52] @ 0x34 8007fa8: 4b7d ldr r3, [pc, #500] @ (80081a0 ) 8007faa: 4013 ands r3, r2 8007fac: 2b00 cmp r3, #0 8007fae: d1df bne.n 8007f70 } } } hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 8007fb0: 68fb ldr r3, [r7, #12] 8007fb2: 681b ldr r3, [r3, #0] 8007fb4: 68ba ldr r2, [r7, #8] 8007fb6: 6992 ldr r2, [r2, #24] 8007fb8: 641a str r2, [r3, #64] @ 0x40 8007fba: e020 b.n 8007ffe { /* SHSR2 can be written when BWST2 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8007fbc: f7fd fc6e bl 800589c 8007fc0: 4602 mov r2, r0 8007fc2: 69fb ldr r3, [r7, #28] 8007fc4: 1ad3 subs r3, r2, r3 8007fc6: 2b01 cmp r3, #1 8007fc8: d90f bls.n 8007fea { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 8007fca: 68fb ldr r3, [r7, #12] 8007fcc: 681b ldr r3, [r3, #0] 8007fce: 6b5b ldr r3, [r3, #52] @ 0x34 8007fd0: 2b00 cmp r3, #0 8007fd2: da0a bge.n 8007fea { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 8007fd4: 68fb ldr r3, [r7, #12] 8007fd6: 691b ldr r3, [r3, #16] 8007fd8: f043 0208 orr.w r2, r3, #8 8007fdc: 68fb ldr r3, [r7, #12] 8007fde: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 8007fe0: 68fb ldr r3, [r7, #12] 8007fe2: 2203 movs r2, #3 8007fe4: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 8007fe6: 2303 movs r3, #3 8007fe8: e0d6 b.n 8008198 while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 8007fea: 68fb ldr r3, [r7, #12] 8007fec: 681b ldr r3, [r3, #0] 8007fee: 6b5b ldr r3, [r3, #52] @ 0x34 8007ff0: 2b00 cmp r3, #0 8007ff2: dbe3 blt.n 8007fbc } } } hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 8007ff4: 68fb ldr r3, [r7, #12] 8007ff6: 681b ldr r3, [r3, #0] 8007ff8: 68ba ldr r2, [r7, #8] 8007ffa: 6992 ldr r2, [r2, #24] 8007ffc: 645a str r2, [r3, #68] @ 0x44 } /* HoldTime */ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), 8007ffe: 68fb ldr r3, [r7, #12] 8008000: 681b ldr r3, [r3, #0] 8008002: 6c9a ldr r2, [r3, #72] @ 0x48 8008004: 687b ldr r3, [r7, #4] 8008006: f003 0310 and.w r3, r3, #16 800800a: f240 31ff movw r1, #1023 @ 0x3ff 800800e: fa01 f303 lsl.w r3, r1, r3 8008012: 43db mvns r3, r3 8008014: ea02 0103 and.w r1, r2, r3 8008018: 68bb ldr r3, [r7, #8] 800801a: 69da ldr r2, [r3, #28] 800801c: 687b ldr r3, [r7, #4] 800801e: f003 0310 and.w r3, r3, #16 8008022: 409a lsls r2, r3 8008024: 68fb ldr r3, [r7, #12] 8008026: 681b ldr r3, [r3, #0] 8008028: 430a orrs r2, r1 800802a: 649a str r2, [r3, #72] @ 0x48 (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); /* RefreshTime */ MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), 800802c: 68fb ldr r3, [r7, #12] 800802e: 681b ldr r3, [r3, #0] 8008030: 6cda ldr r2, [r3, #76] @ 0x4c 8008032: 687b ldr r3, [r7, #4] 8008034: f003 0310 and.w r3, r3, #16 8008038: 21ff movs r1, #255 @ 0xff 800803a: fa01 f303 lsl.w r3, r1, r3 800803e: 43db mvns r3, r3 8008040: ea02 0103 and.w r1, r2, r3 8008044: 68bb ldr r3, [r7, #8] 8008046: 6a1a ldr r2, [r3, #32] 8008048: 687b ldr r3, [r7, #4] 800804a: f003 0310 and.w r3, r3, #16 800804e: 409a lsls r2, r3 8008050: 68fb ldr r3, [r7, #12] 8008052: 681b ldr r3, [r3, #0] 8008054: 430a orrs r2, r1 8008056: 64da str r2, [r3, #76] @ 0x4c (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); } if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) 8008058: 68bb ldr r3, [r7, #8] 800805a: 691b ldr r3, [r3, #16] 800805c: 2b01 cmp r3, #1 800805e: d11d bne.n 800809c /* USER TRIMMING */ { /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; 8008060: 68fb ldr r3, [r7, #12] 8008062: 681b ldr r3, [r3, #0] 8008064: 6b9b ldr r3, [r3, #56] @ 0x38 8008066: 61bb str r3, [r7, #24] /* Clear trimming value */ tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); 8008068: 687b ldr r3, [r7, #4] 800806a: f003 0310 and.w r3, r3, #16 800806e: 221f movs r2, #31 8008070: fa02 f303 lsl.w r3, r2, r3 8008074: 43db mvns r3, r3 8008076: 69ba ldr r2, [r7, #24] 8008078: 4013 ands r3, r2 800807a: 61bb str r3, [r7, #24] /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; 800807c: 68bb ldr r3, [r7, #8] 800807e: 695b ldr r3, [r3, #20] 8008080: 617b str r3, [r7, #20] /* Calculate CCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8008082: 687b ldr r3, [r7, #4] 8008084: f003 0310 and.w r3, r3, #16 8008088: 697a ldr r2, [r7, #20] 800808a: fa02 f303 lsl.w r3, r2, r3 800808e: 69ba ldr r2, [r7, #24] 8008090: 4313 orrs r3, r2 8008092: 61bb str r3, [r7, #24] /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; 8008094: 68fb ldr r3, [r7, #12] 8008096: 681b ldr r3, [r3, #0] 8008098: 69ba ldr r2, [r7, #24] 800809a: 639a str r2, [r3, #56] @ 0x38 } /* else factory trimming is used (factory setting are available at reset)*/ /* SW Nothing has nothing to do */ /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; 800809c: 68fb ldr r3, [r7, #12] 800809e: 681b ldr r3, [r3, #0] 80080a0: 6bdb ldr r3, [r3, #60] @ 0x3c 80080a2: 61bb str r3, [r7, #24] /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); 80080a4: 687b ldr r3, [r7, #4] 80080a6: f003 0310 and.w r3, r3, #16 80080aa: 2207 movs r2, #7 80080ac: fa02 f303 lsl.w r3, r2, r3 80080b0: 43db mvns r3, r3 80080b2: 69ba ldr r2, [r7, #24] 80080b4: 4013 ands r3, r2 80080b6: 61bb str r3, [r7, #24] /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) 80080b8: 68bb ldr r3, [r7, #8] 80080ba: 68db ldr r3, [r3, #12] 80080bc: 2b01 cmp r3, #1 80080be: d102 bne.n 80080c6 { connectOnChip = 0x00000000UL; 80080c0: 2300 movs r3, #0 80080c2: 627b str r3, [r7, #36] @ 0x24 80080c4: e00f b.n 80080e6 } else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL) 80080c6: 68bb ldr r3, [r7, #8] 80080c8: 68db ldr r3, [r3, #12] 80080ca: 2b02 cmp r3, #2 80080cc: d102 bne.n 80080d4 { connectOnChip = DAC_MCR_MODE1_0; 80080ce: 2301 movs r3, #1 80080d0: 627b str r3, [r7, #36] @ 0x24 80080d2: e008 b.n 80080e6 } else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */ { if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) 80080d4: 68bb ldr r3, [r7, #8] 80080d6: 689b ldr r3, [r3, #8] 80080d8: 2b00 cmp r3, #0 80080da: d102 bne.n 80080e2 { connectOnChip = DAC_MCR_MODE1_0; 80080dc: 2301 movs r3, #1 80080de: 627b str r3, [r7, #36] @ 0x24 80080e0: e001 b.n 80080e6 } else { connectOnChip = 0x00000000UL; 80080e2: 2300 movs r3, #0 80080e4: 627b str r3, [r7, #36] @ 0x24 } } tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); 80080e6: 68bb ldr r3, [r7, #8] 80080e8: 681a ldr r2, [r3, #0] 80080ea: 68bb ldr r3, [r7, #8] 80080ec: 689b ldr r3, [r3, #8] 80080ee: 4313 orrs r3, r2 80080f0: 6a7a ldr r2, [r7, #36] @ 0x24 80080f2: 4313 orrs r3, r2 80080f4: 617b str r3, [r7, #20] /* Calculate MCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 80080f6: 687b ldr r3, [r7, #4] 80080f8: f003 0310 and.w r3, r3, #16 80080fc: 697a ldr r2, [r7, #20] 80080fe: fa02 f303 lsl.w r3, r2, r3 8008102: 69ba ldr r2, [r7, #24] 8008104: 4313 orrs r3, r2 8008106: 61bb str r3, [r7, #24] /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; 8008108: 68fb ldr r3, [r7, #12] 800810a: 681b ldr r3, [r3, #0] 800810c: 69ba ldr r2, [r7, #24] 800810e: 63da str r2, [r3, #60] @ 0x3c /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); 8008110: 68fb ldr r3, [r7, #12] 8008112: 681b ldr r3, [r3, #0] 8008114: 6819 ldr r1, [r3, #0] 8008116: 687b ldr r3, [r7, #4] 8008118: f003 0310 and.w r3, r3, #16 800811c: f44f 4280 mov.w r2, #16384 @ 0x4000 8008120: fa02 f303 lsl.w r3, r2, r3 8008124: 43da mvns r2, r3 8008126: 68fb ldr r3, [r7, #12] 8008128: 681b ldr r3, [r3, #0] 800812a: 400a ands r2, r1 800812c: 601a str r2, [r3, #0] /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; 800812e: 68fb ldr r3, [r7, #12] 8008130: 681b ldr r3, [r3, #0] 8008132: 681b ldr r3, [r3, #0] 8008134: 61bb str r3, [r7, #24] /* Clear TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); 8008136: 687b ldr r3, [r7, #4] 8008138: f003 0310 and.w r3, r3, #16 800813c: f640 72fe movw r2, #4094 @ 0xffe 8008140: fa02 f303 lsl.w r3, r2, r3 8008144: 43db mvns r3, r3 8008146: 69ba ldr r2, [r7, #24] 8008148: 4013 ands r3, r2 800814a: 61bb str r3, [r7, #24] /* Configure for the selected DAC channel: trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ tmpreg2 = sConfig->DAC_Trigger; 800814c: 68bb ldr r3, [r7, #8] 800814e: 685b ldr r3, [r3, #4] 8008150: 617b str r3, [r7, #20] /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8008152: 687b ldr r3, [r7, #4] 8008154: f003 0310 and.w r3, r3, #16 8008158: 697a ldr r2, [r7, #20] 800815a: fa02 f303 lsl.w r3, r2, r3 800815e: 69ba ldr r2, [r7, #24] 8008160: 4313 orrs r3, r2 8008162: 61bb str r3, [r7, #24] /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; 8008164: 68fb ldr r3, [r7, #12] 8008166: 681b ldr r3, [r3, #0] 8008168: 69ba ldr r2, [r7, #24] 800816a: 601a str r2, [r3, #0] /* Disable wave generation */ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); 800816c: 68fb ldr r3, [r7, #12] 800816e: 681b ldr r3, [r3, #0] 8008170: 6819 ldr r1, [r3, #0] 8008172: 687b ldr r3, [r7, #4] 8008174: f003 0310 and.w r3, r3, #16 8008178: 22c0 movs r2, #192 @ 0xc0 800817a: fa02 f303 lsl.w r3, r2, r3 800817e: 43da mvns r2, r3 8008180: 68fb ldr r3, [r7, #12] 8008182: 681b ldr r3, [r3, #0] 8008184: 400a ands r2, r1 8008186: 601a str r2, [r3, #0] /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 8008188: 68fb ldr r3, [r7, #12] 800818a: 2201 movs r2, #1 800818c: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 800818e: 68fb ldr r3, [r7, #12] 8008190: 2200 movs r2, #0 8008192: 715a strb r2, [r3, #5] /* Return function status */ return status; 8008194: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 } 8008198: 4618 mov r0, r3 800819a: 3728 adds r7, #40 @ 0x28 800819c: 46bd mov sp, r7 800819e: bd80 pop {r7, pc} 80081a0: 20008000 .word 0x20008000 080081a4 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) { 80081a4: b480 push {r7} 80081a6: b083 sub sp, #12 80081a8: af00 add r7, sp, #0 80081aa: 6078 str r0, [r7, #4] UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file */ } 80081ac: bf00 nop 80081ae: 370c adds r7, #12 80081b0: 46bd mov sp, r7 80081b2: f85d 7b04 ldr.w r7, [sp], #4 80081b6: 4770 bx lr 080081b8 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 80081b8: b580 push {r7, lr} 80081ba: b086 sub sp, #24 80081bc: af00 add r7, sp, #0 80081be: 6078 str r0, [r7, #4] uint32_t registerValue; uint32_t tickstart = HAL_GetTick(); 80081c0: f7fd fb6c bl 800589c 80081c4: 6138 str r0, [r7, #16] DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 80081c6: 687b ldr r3, [r7, #4] 80081c8: 2b00 cmp r3, #0 80081ca: d101 bne.n 80081d0 { return HAL_ERROR; 80081cc: 2301 movs r3, #1 80081ce: e316 b.n 80087fe assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80081d0: 687b ldr r3, [r7, #4] 80081d2: 681b ldr r3, [r3, #0] 80081d4: 4a66 ldr r2, [pc, #408] @ (8008370 ) 80081d6: 4293 cmp r3, r2 80081d8: d04a beq.n 8008270 80081da: 687b ldr r3, [r7, #4] 80081dc: 681b ldr r3, [r3, #0] 80081de: 4a65 ldr r2, [pc, #404] @ (8008374 ) 80081e0: 4293 cmp r3, r2 80081e2: d045 beq.n 8008270 80081e4: 687b ldr r3, [r7, #4] 80081e6: 681b ldr r3, [r3, #0] 80081e8: 4a63 ldr r2, [pc, #396] @ (8008378 ) 80081ea: 4293 cmp r3, r2 80081ec: d040 beq.n 8008270 80081ee: 687b ldr r3, [r7, #4] 80081f0: 681b ldr r3, [r3, #0] 80081f2: 4a62 ldr r2, [pc, #392] @ (800837c ) 80081f4: 4293 cmp r3, r2 80081f6: d03b beq.n 8008270 80081f8: 687b ldr r3, [r7, #4] 80081fa: 681b ldr r3, [r3, #0] 80081fc: 4a60 ldr r2, [pc, #384] @ (8008380 ) 80081fe: 4293 cmp r3, r2 8008200: d036 beq.n 8008270 8008202: 687b ldr r3, [r7, #4] 8008204: 681b ldr r3, [r3, #0] 8008206: 4a5f ldr r2, [pc, #380] @ (8008384 ) 8008208: 4293 cmp r3, r2 800820a: d031 beq.n 8008270 800820c: 687b ldr r3, [r7, #4] 800820e: 681b ldr r3, [r3, #0] 8008210: 4a5d ldr r2, [pc, #372] @ (8008388 ) 8008212: 4293 cmp r3, r2 8008214: d02c beq.n 8008270 8008216: 687b ldr r3, [r7, #4] 8008218: 681b ldr r3, [r3, #0] 800821a: 4a5c ldr r2, [pc, #368] @ (800838c ) 800821c: 4293 cmp r3, r2 800821e: d027 beq.n 8008270 8008220: 687b ldr r3, [r7, #4] 8008222: 681b ldr r3, [r3, #0] 8008224: 4a5a ldr r2, [pc, #360] @ (8008390 ) 8008226: 4293 cmp r3, r2 8008228: d022 beq.n 8008270 800822a: 687b ldr r3, [r7, #4] 800822c: 681b ldr r3, [r3, #0] 800822e: 4a59 ldr r2, [pc, #356] @ (8008394 ) 8008230: 4293 cmp r3, r2 8008232: d01d beq.n 8008270 8008234: 687b ldr r3, [r7, #4] 8008236: 681b ldr r3, [r3, #0] 8008238: 4a57 ldr r2, [pc, #348] @ (8008398 ) 800823a: 4293 cmp r3, r2 800823c: d018 beq.n 8008270 800823e: 687b ldr r3, [r7, #4] 8008240: 681b ldr r3, [r3, #0] 8008242: 4a56 ldr r2, [pc, #344] @ (800839c ) 8008244: 4293 cmp r3, r2 8008246: d013 beq.n 8008270 8008248: 687b ldr r3, [r7, #4] 800824a: 681b ldr r3, [r3, #0] 800824c: 4a54 ldr r2, [pc, #336] @ (80083a0 ) 800824e: 4293 cmp r3, r2 8008250: d00e beq.n 8008270 8008252: 687b ldr r3, [r7, #4] 8008254: 681b ldr r3, [r3, #0] 8008256: 4a53 ldr r2, [pc, #332] @ (80083a4 ) 8008258: 4293 cmp r3, r2 800825a: d009 beq.n 8008270 800825c: 687b ldr r3, [r7, #4] 800825e: 681b ldr r3, [r3, #0] 8008260: 4a51 ldr r2, [pc, #324] @ (80083a8 ) 8008262: 4293 cmp r3, r2 8008264: d004 beq.n 8008270 8008266: 687b ldr r3, [r7, #4] 8008268: 681b ldr r3, [r3, #0] 800826a: 4a50 ldr r2, [pc, #320] @ (80083ac ) 800826c: 4293 cmp r3, r2 800826e: d101 bne.n 8008274 8008270: 2301 movs r3, #1 8008272: e000 b.n 8008276 8008274: 2300 movs r3, #0 8008276: 2b00 cmp r3, #0 8008278: f000 813b beq.w 80084f2 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 800827c: 687b ldr r3, [r7, #4] 800827e: 2202 movs r2, #2 8008280: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8008284: 687b ldr r3, [r7, #4] 8008286: 2200 movs r2, #0 8008288: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 800828c: 687b ldr r3, [r7, #4] 800828e: 681b ldr r3, [r3, #0] 8008290: 4a37 ldr r2, [pc, #220] @ (8008370 ) 8008292: 4293 cmp r3, r2 8008294: d04a beq.n 800832c 8008296: 687b ldr r3, [r7, #4] 8008298: 681b ldr r3, [r3, #0] 800829a: 4a36 ldr r2, [pc, #216] @ (8008374 ) 800829c: 4293 cmp r3, r2 800829e: d045 beq.n 800832c 80082a0: 687b ldr r3, [r7, #4] 80082a2: 681b ldr r3, [r3, #0] 80082a4: 4a34 ldr r2, [pc, #208] @ (8008378 ) 80082a6: 4293 cmp r3, r2 80082a8: d040 beq.n 800832c 80082aa: 687b ldr r3, [r7, #4] 80082ac: 681b ldr r3, [r3, #0] 80082ae: 4a33 ldr r2, [pc, #204] @ (800837c ) 80082b0: 4293 cmp r3, r2 80082b2: d03b beq.n 800832c 80082b4: 687b ldr r3, [r7, #4] 80082b6: 681b ldr r3, [r3, #0] 80082b8: 4a31 ldr r2, [pc, #196] @ (8008380 ) 80082ba: 4293 cmp r3, r2 80082bc: d036 beq.n 800832c 80082be: 687b ldr r3, [r7, #4] 80082c0: 681b ldr r3, [r3, #0] 80082c2: 4a30 ldr r2, [pc, #192] @ (8008384 ) 80082c4: 4293 cmp r3, r2 80082c6: d031 beq.n 800832c 80082c8: 687b ldr r3, [r7, #4] 80082ca: 681b ldr r3, [r3, #0] 80082cc: 4a2e ldr r2, [pc, #184] @ (8008388 ) 80082ce: 4293 cmp r3, r2 80082d0: d02c beq.n 800832c 80082d2: 687b ldr r3, [r7, #4] 80082d4: 681b ldr r3, [r3, #0] 80082d6: 4a2d ldr r2, [pc, #180] @ (800838c ) 80082d8: 4293 cmp r3, r2 80082da: d027 beq.n 800832c 80082dc: 687b ldr r3, [r7, #4] 80082de: 681b ldr r3, [r3, #0] 80082e0: 4a2b ldr r2, [pc, #172] @ (8008390 ) 80082e2: 4293 cmp r3, r2 80082e4: d022 beq.n 800832c 80082e6: 687b ldr r3, [r7, #4] 80082e8: 681b ldr r3, [r3, #0] 80082ea: 4a2a ldr r2, [pc, #168] @ (8008394 ) 80082ec: 4293 cmp r3, r2 80082ee: d01d beq.n 800832c 80082f0: 687b ldr r3, [r7, #4] 80082f2: 681b ldr r3, [r3, #0] 80082f4: 4a28 ldr r2, [pc, #160] @ (8008398 ) 80082f6: 4293 cmp r3, r2 80082f8: d018 beq.n 800832c 80082fa: 687b ldr r3, [r7, #4] 80082fc: 681b ldr r3, [r3, #0] 80082fe: 4a27 ldr r2, [pc, #156] @ (800839c ) 8008300: 4293 cmp r3, r2 8008302: d013 beq.n 800832c 8008304: 687b ldr r3, [r7, #4] 8008306: 681b ldr r3, [r3, #0] 8008308: 4a25 ldr r2, [pc, #148] @ (80083a0 ) 800830a: 4293 cmp r3, r2 800830c: d00e beq.n 800832c 800830e: 687b ldr r3, [r7, #4] 8008310: 681b ldr r3, [r3, #0] 8008312: 4a24 ldr r2, [pc, #144] @ (80083a4 ) 8008314: 4293 cmp r3, r2 8008316: d009 beq.n 800832c 8008318: 687b ldr r3, [r7, #4] 800831a: 681b ldr r3, [r3, #0] 800831c: 4a22 ldr r2, [pc, #136] @ (80083a8 ) 800831e: 4293 cmp r3, r2 8008320: d004 beq.n 800832c 8008322: 687b ldr r3, [r7, #4] 8008324: 681b ldr r3, [r3, #0] 8008326: 4a21 ldr r2, [pc, #132] @ (80083ac ) 8008328: 4293 cmp r3, r2 800832a: d108 bne.n 800833e 800832c: 687b ldr r3, [r7, #4] 800832e: 681b ldr r3, [r3, #0] 8008330: 681a ldr r2, [r3, #0] 8008332: 687b ldr r3, [r7, #4] 8008334: 681b ldr r3, [r3, #0] 8008336: f022 0201 bic.w r2, r2, #1 800833a: 601a str r2, [r3, #0] 800833c: e007 b.n 800834e 800833e: 687b ldr r3, [r7, #4] 8008340: 681b ldr r3, [r3, #0] 8008342: 681a ldr r2, [r3, #0] 8008344: 687b ldr r3, [r7, #4] 8008346: 681b ldr r3, [r3, #0] 8008348: f022 0201 bic.w r2, r2, #1 800834c: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 800834e: e02f b.n 80083b0 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8008350: f7fd faa4 bl 800589c 8008354: 4602 mov r2, r0 8008356: 693b ldr r3, [r7, #16] 8008358: 1ad3 subs r3, r2, r3 800835a: 2b05 cmp r3, #5 800835c: d928 bls.n 80083b0 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 800835e: 687b ldr r3, [r7, #4] 8008360: 2220 movs r2, #32 8008362: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 8008364: 687b ldr r3, [r7, #4] 8008366: 2203 movs r2, #3 8008368: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 800836c: 2301 movs r3, #1 800836e: e246 b.n 80087fe 8008370: 40020010 .word 0x40020010 8008374: 40020028 .word 0x40020028 8008378: 40020040 .word 0x40020040 800837c: 40020058 .word 0x40020058 8008380: 40020070 .word 0x40020070 8008384: 40020088 .word 0x40020088 8008388: 400200a0 .word 0x400200a0 800838c: 400200b8 .word 0x400200b8 8008390: 40020410 .word 0x40020410 8008394: 40020428 .word 0x40020428 8008398: 40020440 .word 0x40020440 800839c: 40020458 .word 0x40020458 80083a0: 40020470 .word 0x40020470 80083a4: 40020488 .word 0x40020488 80083a8: 400204a0 .word 0x400204a0 80083ac: 400204b8 .word 0x400204b8 while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 80083b0: 687b ldr r3, [r7, #4] 80083b2: 681b ldr r3, [r3, #0] 80083b4: 681b ldr r3, [r3, #0] 80083b6: f003 0301 and.w r3, r3, #1 80083ba: 2b00 cmp r3, #0 80083bc: d1c8 bne.n 8008350 } } /* Get the CR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; 80083be: 687b ldr r3, [r7, #4] 80083c0: 681b ldr r3, [r3, #0] 80083c2: 681b ldr r3, [r3, #0] 80083c4: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 80083c6: 697a ldr r2, [r7, #20] 80083c8: 4b83 ldr r3, [pc, #524] @ (80085d8 ) 80083ca: 4013 ands r3, r2 80083cc: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ registerValue |= hdma->Init.Direction | 80083ce: 687b ldr r3, [r7, #4] 80083d0: 689a ldr r2, [r3, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 80083d2: 687b ldr r3, [r7, #4] 80083d4: 68db ldr r3, [r3, #12] registerValue |= hdma->Init.Direction | 80083d6: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 80083d8: 687b ldr r3, [r7, #4] 80083da: 691b ldr r3, [r3, #16] 80083dc: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80083de: 687b ldr r3, [r7, #4] 80083e0: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 80083e2: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80083e4: 687b ldr r3, [r7, #4] 80083e6: 699b ldr r3, [r3, #24] 80083e8: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 80083ea: 687b ldr r3, [r7, #4] 80083ec: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80083ee: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 80083f0: 687b ldr r3, [r7, #4] 80083f2: 6a1b ldr r3, [r3, #32] 80083f4: 4313 orrs r3, r2 registerValue |= hdma->Init.Direction | 80083f6: 697a ldr r2, [r7, #20] 80083f8: 4313 orrs r3, r2 80083fa: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 80083fc: 687b ldr r3, [r7, #4] 80083fe: 6a5b ldr r3, [r3, #36] @ 0x24 8008400: 2b04 cmp r3, #4 8008402: d107 bne.n 8008414 { /* Get memory burst and peripheral burst */ registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 8008404: 687b ldr r3, [r7, #4] 8008406: 6ada ldr r2, [r3, #44] @ 0x2c 8008408: 687b ldr r3, [r7, #4] 800840a: 6b1b ldr r3, [r3, #48] @ 0x30 800840c: 4313 orrs r3, r2 800840e: 697a ldr r2, [r7, #20] 8008410: 4313 orrs r3, r2 8008412: 617b str r3, [r7, #20] } /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be lock when transferring data to/from USART/UART */ #if (STM32H7_DEV_ID == 0x450UL) if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) 8008414: 4b71 ldr r3, [pc, #452] @ (80085dc ) 8008416: 681a ldr r2, [r3, #0] 8008418: 4b71 ldr r3, [pc, #452] @ (80085e0 ) 800841a: 4013 ands r3, r2 800841c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8008420: d328 bcc.n 8008474 { #endif /* STM32H7_DEV_ID == 0x450UL */ if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) 8008422: 687b ldr r3, [r7, #4] 8008424: 685b ldr r3, [r3, #4] 8008426: 2b28 cmp r3, #40 @ 0x28 8008428: d903 bls.n 8008432 800842a: 687b ldr r3, [r7, #4] 800842c: 685b ldr r3, [r3, #4] 800842e: 2b2e cmp r3, #46 @ 0x2e 8008430: d917 bls.n 8008462 8008432: 687b ldr r3, [r7, #4] 8008434: 685b ldr r3, [r3, #4] 8008436: 2b3e cmp r3, #62 @ 0x3e 8008438: d903 bls.n 8008442 800843a: 687b ldr r3, [r7, #4] 800843c: 685b ldr r3, [r3, #4] 800843e: 2b42 cmp r3, #66 @ 0x42 8008440: d90f bls.n 8008462 8008442: 687b ldr r3, [r7, #4] 8008444: 685b ldr r3, [r3, #4] 8008446: 2b46 cmp r3, #70 @ 0x46 8008448: d903 bls.n 8008452 800844a: 687b ldr r3, [r7, #4] 800844c: 685b ldr r3, [r3, #4] 800844e: 2b48 cmp r3, #72 @ 0x48 8008450: d907 bls.n 8008462 8008452: 687b ldr r3, [r7, #4] 8008454: 685b ldr r3, [r3, #4] 8008456: 2b4e cmp r3, #78 @ 0x4e 8008458: d905 bls.n 8008466 800845a: 687b ldr r3, [r7, #4] 800845c: 685b ldr r3, [r3, #4] 800845e: 2b52 cmp r3, #82 @ 0x52 8008460: d801 bhi.n 8008466 8008462: 2301 movs r3, #1 8008464: e000 b.n 8008468 8008466: 2300 movs r3, #0 8008468: 2b00 cmp r3, #0 800846a: d003 beq.n 8008474 { registerValue |= DMA_SxCR_TRBUFF; 800846c: 697b ldr r3, [r7, #20] 800846e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8008472: 617b str r3, [r7, #20] #if (STM32H7_DEV_ID == 0x450UL) } #endif /* STM32H7_DEV_ID == 0x450UL */ /* Write to DMA Stream CR register */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; 8008474: 687b ldr r3, [r7, #4] 8008476: 681b ldr r3, [r3, #0] 8008478: 697a ldr r2, [r7, #20] 800847a: 601a str r2, [r3, #0] /* Get the FCR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; 800847c: 687b ldr r3, [r7, #4] 800847e: 681b ldr r3, [r3, #0] 8008480: 695b ldr r3, [r3, #20] 8008482: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8008484: 697b ldr r3, [r7, #20] 8008486: f023 0307 bic.w r3, r3, #7 800848a: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ registerValue |= hdma->Init.FIFOMode; 800848c: 687b ldr r3, [r7, #4] 800848e: 6a5b ldr r3, [r3, #36] @ 0x24 8008490: 697a ldr r2, [r7, #20] 8008492: 4313 orrs r3, r2 8008494: 617b str r3, [r7, #20] /* the FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8008496: 687b ldr r3, [r7, #4] 8008498: 6a5b ldr r3, [r3, #36] @ 0x24 800849a: 2b04 cmp r3, #4 800849c: d117 bne.n 80084ce { /* Get the FIFO threshold */ registerValue |= hdma->Init.FIFOThreshold; 800849e: 687b ldr r3, [r7, #4] 80084a0: 6a9b ldr r3, [r3, #40] @ 0x28 80084a2: 697a ldr r2, [r7, #20] 80084a4: 4313 orrs r3, r2 80084a6: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 */ if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) 80084a8: 687b ldr r3, [r7, #4] 80084aa: 6adb ldr r3, [r3, #44] @ 0x2c 80084ac: 2b00 cmp r3, #0 80084ae: d00e beq.n 80084ce { if (DMA_CheckFifoParam(hdma) != HAL_OK) 80084b0: 6878 ldr r0, [r7, #4] 80084b2: f002 fb33 bl 800ab1c 80084b6: 4603 mov r3, r0 80084b8: 2b00 cmp r3, #0 80084ba: d008 beq.n 80084ce { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 80084bc: 687b ldr r3, [r7, #4] 80084be: 2240 movs r2, #64 @ 0x40 80084c0: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80084c2: 687b ldr r3, [r7, #4] 80084c4: 2201 movs r2, #1 80084c6: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 80084ca: 2301 movs r3, #1 80084cc: e197 b.n 80087fe } } } /* Write to DMA Stream FCR */ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; 80084ce: 687b ldr r3, [r7, #4] 80084d0: 681b ldr r3, [r3, #0] 80084d2: 697a ldr r2, [r7, #20] 80084d4: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 80084d6: 6878 ldr r0, [r7, #4] 80084d8: f002 fa6e bl 800a9b8 80084dc: 4603 mov r3, r0 80084de: 60bb str r3, [r7, #8] /* Clear all interrupt flags */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 80084e0: 687b ldr r3, [r7, #4] 80084e2: 6ddb ldr r3, [r3, #92] @ 0x5c 80084e4: f003 031f and.w r3, r3, #31 80084e8: 223f movs r2, #63 @ 0x3f 80084ea: 409a lsls r2, r3 80084ec: 68bb ldr r3, [r7, #8] 80084ee: 609a str r2, [r3, #8] 80084f0: e0cd b.n 800868e } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 80084f2: 687b ldr r3, [r7, #4] 80084f4: 681b ldr r3, [r3, #0] 80084f6: 4a3b ldr r2, [pc, #236] @ (80085e4 ) 80084f8: 4293 cmp r3, r2 80084fa: d022 beq.n 8008542 80084fc: 687b ldr r3, [r7, #4] 80084fe: 681b ldr r3, [r3, #0] 8008500: 4a39 ldr r2, [pc, #228] @ (80085e8 ) 8008502: 4293 cmp r3, r2 8008504: d01d beq.n 8008542 8008506: 687b ldr r3, [r7, #4] 8008508: 681b ldr r3, [r3, #0] 800850a: 4a38 ldr r2, [pc, #224] @ (80085ec ) 800850c: 4293 cmp r3, r2 800850e: d018 beq.n 8008542 8008510: 687b ldr r3, [r7, #4] 8008512: 681b ldr r3, [r3, #0] 8008514: 4a36 ldr r2, [pc, #216] @ (80085f0 ) 8008516: 4293 cmp r3, r2 8008518: d013 beq.n 8008542 800851a: 687b ldr r3, [r7, #4] 800851c: 681b ldr r3, [r3, #0] 800851e: 4a35 ldr r2, [pc, #212] @ (80085f4 ) 8008520: 4293 cmp r3, r2 8008522: d00e beq.n 8008542 8008524: 687b ldr r3, [r7, #4] 8008526: 681b ldr r3, [r3, #0] 8008528: 4a33 ldr r2, [pc, #204] @ (80085f8 ) 800852a: 4293 cmp r3, r2 800852c: d009 beq.n 8008542 800852e: 687b ldr r3, [r7, #4] 8008530: 681b ldr r3, [r3, #0] 8008532: 4a32 ldr r2, [pc, #200] @ (80085fc ) 8008534: 4293 cmp r3, r2 8008536: d004 beq.n 8008542 8008538: 687b ldr r3, [r7, #4] 800853a: 681b ldr r3, [r3, #0] 800853c: 4a30 ldr r2, [pc, #192] @ (8008600 ) 800853e: 4293 cmp r3, r2 8008540: d101 bne.n 8008546 8008542: 2301 movs r3, #1 8008544: e000 b.n 8008548 8008546: 2300 movs r3, #0 8008548: 2b00 cmp r3, #0 800854a: f000 8097 beq.w 800867c { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 800854e: 687b ldr r3, [r7, #4] 8008550: 681b ldr r3, [r3, #0] 8008552: 4a24 ldr r2, [pc, #144] @ (80085e4 ) 8008554: 4293 cmp r3, r2 8008556: d021 beq.n 800859c 8008558: 687b ldr r3, [r7, #4] 800855a: 681b ldr r3, [r3, #0] 800855c: 4a22 ldr r2, [pc, #136] @ (80085e8 ) 800855e: 4293 cmp r3, r2 8008560: d01c beq.n 800859c 8008562: 687b ldr r3, [r7, #4] 8008564: 681b ldr r3, [r3, #0] 8008566: 4a21 ldr r2, [pc, #132] @ (80085ec ) 8008568: 4293 cmp r3, r2 800856a: d017 beq.n 800859c 800856c: 687b ldr r3, [r7, #4] 800856e: 681b ldr r3, [r3, #0] 8008570: 4a1f ldr r2, [pc, #124] @ (80085f0 ) 8008572: 4293 cmp r3, r2 8008574: d012 beq.n 800859c 8008576: 687b ldr r3, [r7, #4] 8008578: 681b ldr r3, [r3, #0] 800857a: 4a1e ldr r2, [pc, #120] @ (80085f4 ) 800857c: 4293 cmp r3, r2 800857e: d00d beq.n 800859c 8008580: 687b ldr r3, [r7, #4] 8008582: 681b ldr r3, [r3, #0] 8008584: 4a1c ldr r2, [pc, #112] @ (80085f8 ) 8008586: 4293 cmp r3, r2 8008588: d008 beq.n 800859c 800858a: 687b ldr r3, [r7, #4] 800858c: 681b ldr r3, [r3, #0] 800858e: 4a1b ldr r2, [pc, #108] @ (80085fc ) 8008590: 4293 cmp r3, r2 8008592: d003 beq.n 800859c 8008594: 687b ldr r3, [r7, #4] 8008596: 681b ldr r3, [r3, #0] 8008598: 4a19 ldr r2, [pc, #100] @ (8008600 ) 800859a: 4293 cmp r3, r2 /* Check the request parameter */ assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 800859c: 687b ldr r3, [r7, #4] 800859e: 2202 movs r2, #2 80085a0: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 80085a4: 687b ldr r3, [r7, #4] 80085a6: 2200 movs r2, #0 80085a8: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Get the CR register value */ registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; 80085ac: 687b ldr r3, [r7, #4] 80085ae: 681b ldr r3, [r3, #0] 80085b0: 681b ldr r3, [r3, #0] 80085b2: 617b str r3, [r7, #20] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */ registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ 80085b4: 697a ldr r2, [r7, #20] 80085b6: 4b13 ldr r3, [pc, #76] @ (8008604 ) 80085b8: 4013 ands r3, r2 80085ba: 617b str r3, [r7, #20] BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \ BDMA_CCR_CT)); /* Prepare the DMA Channel configuration */ registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 80085bc: 687b ldr r3, [r7, #4] 80085be: 689b ldr r3, [r3, #8] 80085c0: 2b40 cmp r3, #64 @ 0x40 80085c2: d021 beq.n 8008608 80085c4: 687b ldr r3, [r7, #4] 80085c6: 689b ldr r3, [r3, #8] 80085c8: 2b80 cmp r3, #128 @ 0x80 80085ca: d102 bne.n 80085d2 80085cc: f44f 4380 mov.w r3, #16384 @ 0x4000 80085d0: e01b b.n 800860a 80085d2: 2300 movs r3, #0 80085d4: e019 b.n 800860a 80085d6: bf00 nop 80085d8: fe10803f .word 0xfe10803f 80085dc: 5c001000 .word 0x5c001000 80085e0: ffff0000 .word 0xffff0000 80085e4: 58025408 .word 0x58025408 80085e8: 5802541c .word 0x5802541c 80085ec: 58025430 .word 0x58025430 80085f0: 58025444 .word 0x58025444 80085f4: 58025458 .word 0x58025458 80085f8: 5802546c .word 0x5802546c 80085fc: 58025480 .word 0x58025480 8008600: 58025494 .word 0x58025494 8008604: fffe000f .word 0xfffe000f 8008608: 2310 movs r3, #16 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 800860a: 687a ldr r2, [r7, #4] 800860c: 68d2 ldr r2, [r2, #12] 800860e: 08d2 lsrs r2, r2, #3 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8008610: 431a orrs r2, r3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 8008612: 687b ldr r3, [r7, #4] 8008614: 691b ldr r3, [r3, #16] 8008616: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 8008618: 431a orrs r2, r3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 800861a: 687b ldr r3, [r7, #4] 800861c: 695b ldr r3, [r3, #20] 800861e: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 8008620: 431a orrs r2, r3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 8008622: 687b ldr r3, [r7, #4] 8008624: 699b ldr r3, [r3, #24] 8008626: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 8008628: 431a orrs r2, r3 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 800862a: 687b ldr r3, [r7, #4] 800862c: 69db ldr r3, [r3, #28] 800862e: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 8008630: 431a orrs r2, r3 DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); 8008632: 687b ldr r3, [r7, #4] 8008634: 6a1b ldr r3, [r3, #32] 8008636: 091b lsrs r3, r3, #4 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 8008638: 4313 orrs r3, r2 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 800863a: 697a ldr r2, [r7, #20] 800863c: 4313 orrs r3, r2 800863e: 617b str r3, [r7, #20] /* Write to DMA Channel CR register */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; 8008640: 687b ldr r3, [r7, #4] 8008642: 681b ldr r3, [r3, #0] 8008644: 697a ldr r2, [r7, #20] 8008646: 601a str r2, [r3, #0] /* calculation of the channel index */ hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; 8008648: 687b ldr r3, [r7, #4] 800864a: 681b ldr r3, [r3, #0] 800864c: 461a mov r2, r3 800864e: 4b6e ldr r3, [pc, #440] @ (8008808 ) 8008650: 4413 add r3, r2 8008652: 4a6e ldr r2, [pc, #440] @ (800880c ) 8008654: fba2 2303 umull r2, r3, r2, r3 8008658: 091b lsrs r3, r3, #4 800865a: 009a lsls r2, r3, #2 800865c: 687b ldr r3, [r7, #4] 800865e: 65da str r2, [r3, #92] @ 0x5c /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8008660: 6878 ldr r0, [r7, #4] 8008662: f002 f9a9 bl 800a9b8 8008666: 4603 mov r3, r0 8008668: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 800866a: 687b ldr r3, [r7, #4] 800866c: 6ddb ldr r3, [r3, #92] @ 0x5c 800866e: f003 031f and.w r3, r3, #31 8008672: 2201 movs r2, #1 8008674: 409a lsls r2, r3 8008676: 68fb ldr r3, [r7, #12] 8008678: 605a str r2, [r3, #4] 800867a: e008 b.n 800868e } else { hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 800867c: 687b ldr r3, [r7, #4] 800867e: 2240 movs r2, #64 @ 0x40 8008680: 655a str r2, [r3, #84] @ 0x54 hdma->State = HAL_DMA_STATE_ERROR; 8008682: 687b ldr r3, [r7, #4] 8008684: 2203 movs r2, #3 8008686: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 800868a: 2301 movs r3, #1 800868c: e0b7 b.n 80087fe } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800868e: 687b ldr r3, [r7, #4] 8008690: 681b ldr r3, [r3, #0] 8008692: 4a5f ldr r2, [pc, #380] @ (8008810 ) 8008694: 4293 cmp r3, r2 8008696: d072 beq.n 800877e 8008698: 687b ldr r3, [r7, #4] 800869a: 681b ldr r3, [r3, #0] 800869c: 4a5d ldr r2, [pc, #372] @ (8008814 ) 800869e: 4293 cmp r3, r2 80086a0: d06d beq.n 800877e 80086a2: 687b ldr r3, [r7, #4] 80086a4: 681b ldr r3, [r3, #0] 80086a6: 4a5c ldr r2, [pc, #368] @ (8008818 ) 80086a8: 4293 cmp r3, r2 80086aa: d068 beq.n 800877e 80086ac: 687b ldr r3, [r7, #4] 80086ae: 681b ldr r3, [r3, #0] 80086b0: 4a5a ldr r2, [pc, #360] @ (800881c ) 80086b2: 4293 cmp r3, r2 80086b4: d063 beq.n 800877e 80086b6: 687b ldr r3, [r7, #4] 80086b8: 681b ldr r3, [r3, #0] 80086ba: 4a59 ldr r2, [pc, #356] @ (8008820 ) 80086bc: 4293 cmp r3, r2 80086be: d05e beq.n 800877e 80086c0: 687b ldr r3, [r7, #4] 80086c2: 681b ldr r3, [r3, #0] 80086c4: 4a57 ldr r2, [pc, #348] @ (8008824 ) 80086c6: 4293 cmp r3, r2 80086c8: d059 beq.n 800877e 80086ca: 687b ldr r3, [r7, #4] 80086cc: 681b ldr r3, [r3, #0] 80086ce: 4a56 ldr r2, [pc, #344] @ (8008828 ) 80086d0: 4293 cmp r3, r2 80086d2: d054 beq.n 800877e 80086d4: 687b ldr r3, [r7, #4] 80086d6: 681b ldr r3, [r3, #0] 80086d8: 4a54 ldr r2, [pc, #336] @ (800882c ) 80086da: 4293 cmp r3, r2 80086dc: d04f beq.n 800877e 80086de: 687b ldr r3, [r7, #4] 80086e0: 681b ldr r3, [r3, #0] 80086e2: 4a53 ldr r2, [pc, #332] @ (8008830 ) 80086e4: 4293 cmp r3, r2 80086e6: d04a beq.n 800877e 80086e8: 687b ldr r3, [r7, #4] 80086ea: 681b ldr r3, [r3, #0] 80086ec: 4a51 ldr r2, [pc, #324] @ (8008834 ) 80086ee: 4293 cmp r3, r2 80086f0: d045 beq.n 800877e 80086f2: 687b ldr r3, [r7, #4] 80086f4: 681b ldr r3, [r3, #0] 80086f6: 4a50 ldr r2, [pc, #320] @ (8008838 ) 80086f8: 4293 cmp r3, r2 80086fa: d040 beq.n 800877e 80086fc: 687b ldr r3, [r7, #4] 80086fe: 681b ldr r3, [r3, #0] 8008700: 4a4e ldr r2, [pc, #312] @ (800883c ) 8008702: 4293 cmp r3, r2 8008704: d03b beq.n 800877e 8008706: 687b ldr r3, [r7, #4] 8008708: 681b ldr r3, [r3, #0] 800870a: 4a4d ldr r2, [pc, #308] @ (8008840 ) 800870c: 4293 cmp r3, r2 800870e: d036 beq.n 800877e 8008710: 687b ldr r3, [r7, #4] 8008712: 681b ldr r3, [r3, #0] 8008714: 4a4b ldr r2, [pc, #300] @ (8008844 ) 8008716: 4293 cmp r3, r2 8008718: d031 beq.n 800877e 800871a: 687b ldr r3, [r7, #4] 800871c: 681b ldr r3, [r3, #0] 800871e: 4a4a ldr r2, [pc, #296] @ (8008848 ) 8008720: 4293 cmp r3, r2 8008722: d02c beq.n 800877e 8008724: 687b ldr r3, [r7, #4] 8008726: 681b ldr r3, [r3, #0] 8008728: 4a48 ldr r2, [pc, #288] @ (800884c ) 800872a: 4293 cmp r3, r2 800872c: d027 beq.n 800877e 800872e: 687b ldr r3, [r7, #4] 8008730: 681b ldr r3, [r3, #0] 8008732: 4a47 ldr r2, [pc, #284] @ (8008850 ) 8008734: 4293 cmp r3, r2 8008736: d022 beq.n 800877e 8008738: 687b ldr r3, [r7, #4] 800873a: 681b ldr r3, [r3, #0] 800873c: 4a45 ldr r2, [pc, #276] @ (8008854 ) 800873e: 4293 cmp r3, r2 8008740: d01d beq.n 800877e 8008742: 687b ldr r3, [r7, #4] 8008744: 681b ldr r3, [r3, #0] 8008746: 4a44 ldr r2, [pc, #272] @ (8008858 ) 8008748: 4293 cmp r3, r2 800874a: d018 beq.n 800877e 800874c: 687b ldr r3, [r7, #4] 800874e: 681b ldr r3, [r3, #0] 8008750: 4a42 ldr r2, [pc, #264] @ (800885c ) 8008752: 4293 cmp r3, r2 8008754: d013 beq.n 800877e 8008756: 687b ldr r3, [r7, #4] 8008758: 681b ldr r3, [r3, #0] 800875a: 4a41 ldr r2, [pc, #260] @ (8008860 ) 800875c: 4293 cmp r3, r2 800875e: d00e beq.n 800877e 8008760: 687b ldr r3, [r7, #4] 8008762: 681b ldr r3, [r3, #0] 8008764: 4a3f ldr r2, [pc, #252] @ (8008864 ) 8008766: 4293 cmp r3, r2 8008768: d009 beq.n 800877e 800876a: 687b ldr r3, [r7, #4] 800876c: 681b ldr r3, [r3, #0] 800876e: 4a3e ldr r2, [pc, #248] @ (8008868 ) 8008770: 4293 cmp r3, r2 8008772: d004 beq.n 800877e 8008774: 687b ldr r3, [r7, #4] 8008776: 681b ldr r3, [r3, #0] 8008778: 4a3c ldr r2, [pc, #240] @ (800886c ) 800877a: 4293 cmp r3, r2 800877c: d101 bne.n 8008782 800877e: 2301 movs r3, #1 8008780: e000 b.n 8008784 8008782: 2300 movs r3, #0 8008784: 2b00 cmp r3, #0 8008786: d032 beq.n 80087ee { /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 8008788: 6878 ldr r0, [r7, #4] 800878a: f002 fa43 bl 800ac14 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 800878e: 687b ldr r3, [r7, #4] 8008790: 689b ldr r3, [r3, #8] 8008792: 2b80 cmp r3, #128 @ 0x80 8008794: d102 bne.n 800879c { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 8008796: 687b ldr r3, [r7, #4] 8008798: 2200 movs r2, #0 800879a: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 800879c: 687b ldr r3, [r7, #4] 800879e: 685a ldr r2, [r3, #4] 80087a0: 687b ldr r3, [r7, #4] 80087a2: 6e1b ldr r3, [r3, #96] @ 0x60 80087a4: b2d2 uxtb r2, r2 80087a6: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 80087a8: 687b ldr r3, [r7, #4] 80087aa: 6e5b ldr r3, [r3, #100] @ 0x64 80087ac: 687a ldr r2, [r7, #4] 80087ae: 6e92 ldr r2, [r2, #104] @ 0x68 80087b0: 605a str r2, [r3, #4] /* Initialize parameters for DMAMUX request generator : if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 */ if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) 80087b2: 687b ldr r3, [r7, #4] 80087b4: 685b ldr r3, [r3, #4] 80087b6: 2b00 cmp r3, #0 80087b8: d010 beq.n 80087dc 80087ba: 687b ldr r3, [r7, #4] 80087bc: 685b ldr r3, [r3, #4] 80087be: 2b08 cmp r3, #8 80087c0: d80c bhi.n 80087dc { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 80087c2: 6878 ldr r0, [r7, #4] 80087c4: f002 fac0 bl 800ad48 /* Reset the DMAMUX request generator register */ hdma->DMAmuxRequestGen->RGCR = 0U; 80087c8: 687b ldr r3, [r7, #4] 80087ca: 6edb ldr r3, [r3, #108] @ 0x6c 80087cc: 2200 movs r2, #0 80087ce: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 80087d0: 687b ldr r3, [r7, #4] 80087d2: 6f1b ldr r3, [r3, #112] @ 0x70 80087d4: 687a ldr r2, [r7, #4] 80087d6: 6f52 ldr r2, [r2, #116] @ 0x74 80087d8: 605a str r2, [r3, #4] 80087da: e008 b.n 80087ee } else { hdma->DMAmuxRequestGen = 0U; 80087dc: 687b ldr r3, [r7, #4] 80087de: 2200 movs r2, #0 80087e0: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = 0U; 80087e2: 687b ldr r3, [r7, #4] 80087e4: 2200 movs r2, #0 80087e6: 671a str r2, [r3, #112] @ 0x70 hdma->DMAmuxRequestGenStatusMask = 0U; 80087e8: 687b ldr r3, [r7, #4] 80087ea: 2200 movs r2, #0 80087ec: 675a str r2, [r3, #116] @ 0x74 } } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 80087ee: 687b ldr r3, [r7, #4] 80087f0: 2200 movs r2, #0 80087f2: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80087f4: 687b ldr r3, [r7, #4] 80087f6: 2201 movs r2, #1 80087f8: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 80087fc: 2300 movs r3, #0 } 80087fe: 4618 mov r0, r3 8008800: 3718 adds r7, #24 8008802: 46bd mov sp, r7 8008804: bd80 pop {r7, pc} 8008806: bf00 nop 8008808: a7fdabf8 .word 0xa7fdabf8 800880c: cccccccd .word 0xcccccccd 8008810: 40020010 .word 0x40020010 8008814: 40020028 .word 0x40020028 8008818: 40020040 .word 0x40020040 800881c: 40020058 .word 0x40020058 8008820: 40020070 .word 0x40020070 8008824: 40020088 .word 0x40020088 8008828: 400200a0 .word 0x400200a0 800882c: 400200b8 .word 0x400200b8 8008830: 40020410 .word 0x40020410 8008834: 40020428 .word 0x40020428 8008838: 40020440 .word 0x40020440 800883c: 40020458 .word 0x40020458 8008840: 40020470 .word 0x40020470 8008844: 40020488 .word 0x40020488 8008848: 400204a0 .word 0x400204a0 800884c: 400204b8 .word 0x400204b8 8008850: 58025408 .word 0x58025408 8008854: 5802541c .word 0x5802541c 8008858: 58025430 .word 0x58025430 800885c: 58025444 .word 0x58025444 8008860: 58025458 .word 0x58025458 8008864: 5802546c .word 0x5802546c 8008868: 58025480 .word 0x58025480 800886c: 58025494 .word 0x58025494 08008870 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8008870: b580 push {r7, lr} 8008872: b086 sub sp, #24 8008874: af00 add r7, sp, #0 8008876: 60f8 str r0, [r7, #12] 8008878: 60b9 str r1, [r7, #8] 800887a: 607a str r2, [r7, #4] 800887c: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800887e: 2300 movs r3, #0 8008880: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Check the DMA peripheral handle */ if(hdma == NULL) 8008882: 68fb ldr r3, [r7, #12] 8008884: 2b00 cmp r3, #0 8008886: d101 bne.n 800888c { return HAL_ERROR; 8008888: 2301 movs r3, #1 800888a: e226 b.n 8008cda } /* Process locked */ __HAL_LOCK(hdma); 800888c: 68fb ldr r3, [r7, #12] 800888e: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8008892: 2b01 cmp r3, #1 8008894: d101 bne.n 800889a 8008896: 2302 movs r3, #2 8008898: e21f b.n 8008cda 800889a: 68fb ldr r3, [r7, #12] 800889c: 2201 movs r2, #1 800889e: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 80088a2: 68fb ldr r3, [r7, #12] 80088a4: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 80088a8: b2db uxtb r3, r3 80088aa: 2b01 cmp r3, #1 80088ac: f040 820a bne.w 8008cc4 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80088b0: 68fb ldr r3, [r7, #12] 80088b2: 2202 movs r2, #2 80088b4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 80088b8: 68fb ldr r3, [r7, #12] 80088ba: 2200 movs r2, #0 80088bc: 655a str r2, [r3, #84] @ 0x54 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 80088be: 68fb ldr r3, [r7, #12] 80088c0: 681b ldr r3, [r3, #0] 80088c2: 4a68 ldr r2, [pc, #416] @ (8008a64 ) 80088c4: 4293 cmp r3, r2 80088c6: d04a beq.n 800895e 80088c8: 68fb ldr r3, [r7, #12] 80088ca: 681b ldr r3, [r3, #0] 80088cc: 4a66 ldr r2, [pc, #408] @ (8008a68 ) 80088ce: 4293 cmp r3, r2 80088d0: d045 beq.n 800895e 80088d2: 68fb ldr r3, [r7, #12] 80088d4: 681b ldr r3, [r3, #0] 80088d6: 4a65 ldr r2, [pc, #404] @ (8008a6c ) 80088d8: 4293 cmp r3, r2 80088da: d040 beq.n 800895e 80088dc: 68fb ldr r3, [r7, #12] 80088de: 681b ldr r3, [r3, #0] 80088e0: 4a63 ldr r2, [pc, #396] @ (8008a70 ) 80088e2: 4293 cmp r3, r2 80088e4: d03b beq.n 800895e 80088e6: 68fb ldr r3, [r7, #12] 80088e8: 681b ldr r3, [r3, #0] 80088ea: 4a62 ldr r2, [pc, #392] @ (8008a74 ) 80088ec: 4293 cmp r3, r2 80088ee: d036 beq.n 800895e 80088f0: 68fb ldr r3, [r7, #12] 80088f2: 681b ldr r3, [r3, #0] 80088f4: 4a60 ldr r2, [pc, #384] @ (8008a78 ) 80088f6: 4293 cmp r3, r2 80088f8: d031 beq.n 800895e 80088fa: 68fb ldr r3, [r7, #12] 80088fc: 681b ldr r3, [r3, #0] 80088fe: 4a5f ldr r2, [pc, #380] @ (8008a7c ) 8008900: 4293 cmp r3, r2 8008902: d02c beq.n 800895e 8008904: 68fb ldr r3, [r7, #12] 8008906: 681b ldr r3, [r3, #0] 8008908: 4a5d ldr r2, [pc, #372] @ (8008a80 ) 800890a: 4293 cmp r3, r2 800890c: d027 beq.n 800895e 800890e: 68fb ldr r3, [r7, #12] 8008910: 681b ldr r3, [r3, #0] 8008912: 4a5c ldr r2, [pc, #368] @ (8008a84 ) 8008914: 4293 cmp r3, r2 8008916: d022 beq.n 800895e 8008918: 68fb ldr r3, [r7, #12] 800891a: 681b ldr r3, [r3, #0] 800891c: 4a5a ldr r2, [pc, #360] @ (8008a88 ) 800891e: 4293 cmp r3, r2 8008920: d01d beq.n 800895e 8008922: 68fb ldr r3, [r7, #12] 8008924: 681b ldr r3, [r3, #0] 8008926: 4a59 ldr r2, [pc, #356] @ (8008a8c ) 8008928: 4293 cmp r3, r2 800892a: d018 beq.n 800895e 800892c: 68fb ldr r3, [r7, #12] 800892e: 681b ldr r3, [r3, #0] 8008930: 4a57 ldr r2, [pc, #348] @ (8008a90 ) 8008932: 4293 cmp r3, r2 8008934: d013 beq.n 800895e 8008936: 68fb ldr r3, [r7, #12] 8008938: 681b ldr r3, [r3, #0] 800893a: 4a56 ldr r2, [pc, #344] @ (8008a94 ) 800893c: 4293 cmp r3, r2 800893e: d00e beq.n 800895e 8008940: 68fb ldr r3, [r7, #12] 8008942: 681b ldr r3, [r3, #0] 8008944: 4a54 ldr r2, [pc, #336] @ (8008a98 ) 8008946: 4293 cmp r3, r2 8008948: d009 beq.n 800895e 800894a: 68fb ldr r3, [r7, #12] 800894c: 681b ldr r3, [r3, #0] 800894e: 4a53 ldr r2, [pc, #332] @ (8008a9c ) 8008950: 4293 cmp r3, r2 8008952: d004 beq.n 800895e 8008954: 68fb ldr r3, [r7, #12] 8008956: 681b ldr r3, [r3, #0] 8008958: 4a51 ldr r2, [pc, #324] @ (8008aa0 ) 800895a: 4293 cmp r3, r2 800895c: d108 bne.n 8008970 800895e: 68fb ldr r3, [r7, #12] 8008960: 681b ldr r3, [r3, #0] 8008962: 681a ldr r2, [r3, #0] 8008964: 68fb ldr r3, [r7, #12] 8008966: 681b ldr r3, [r3, #0] 8008968: f022 0201 bic.w r2, r2, #1 800896c: 601a str r2, [r3, #0] 800896e: e007 b.n 8008980 8008970: 68fb ldr r3, [r7, #12] 8008972: 681b ldr r3, [r3, #0] 8008974: 681a ldr r2, [r3, #0] 8008976: 68fb ldr r3, [r7, #12] 8008978: 681b ldr r3, [r3, #0] 800897a: f022 0201 bic.w r2, r2, #1 800897e: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8008980: 683b ldr r3, [r7, #0] 8008982: 687a ldr r2, [r7, #4] 8008984: 68b9 ldr r1, [r7, #8] 8008986: 68f8 ldr r0, [r7, #12] 8008988: f001 fe6a bl 800a660 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800898c: 68fb ldr r3, [r7, #12] 800898e: 681b ldr r3, [r3, #0] 8008990: 4a34 ldr r2, [pc, #208] @ (8008a64 ) 8008992: 4293 cmp r3, r2 8008994: d04a beq.n 8008a2c 8008996: 68fb ldr r3, [r7, #12] 8008998: 681b ldr r3, [r3, #0] 800899a: 4a33 ldr r2, [pc, #204] @ (8008a68 ) 800899c: 4293 cmp r3, r2 800899e: d045 beq.n 8008a2c 80089a0: 68fb ldr r3, [r7, #12] 80089a2: 681b ldr r3, [r3, #0] 80089a4: 4a31 ldr r2, [pc, #196] @ (8008a6c ) 80089a6: 4293 cmp r3, r2 80089a8: d040 beq.n 8008a2c 80089aa: 68fb ldr r3, [r7, #12] 80089ac: 681b ldr r3, [r3, #0] 80089ae: 4a30 ldr r2, [pc, #192] @ (8008a70 ) 80089b0: 4293 cmp r3, r2 80089b2: d03b beq.n 8008a2c 80089b4: 68fb ldr r3, [r7, #12] 80089b6: 681b ldr r3, [r3, #0] 80089b8: 4a2e ldr r2, [pc, #184] @ (8008a74 ) 80089ba: 4293 cmp r3, r2 80089bc: d036 beq.n 8008a2c 80089be: 68fb ldr r3, [r7, #12] 80089c0: 681b ldr r3, [r3, #0] 80089c2: 4a2d ldr r2, [pc, #180] @ (8008a78 ) 80089c4: 4293 cmp r3, r2 80089c6: d031 beq.n 8008a2c 80089c8: 68fb ldr r3, [r7, #12] 80089ca: 681b ldr r3, [r3, #0] 80089cc: 4a2b ldr r2, [pc, #172] @ (8008a7c ) 80089ce: 4293 cmp r3, r2 80089d0: d02c beq.n 8008a2c 80089d2: 68fb ldr r3, [r7, #12] 80089d4: 681b ldr r3, [r3, #0] 80089d6: 4a2a ldr r2, [pc, #168] @ (8008a80 ) 80089d8: 4293 cmp r3, r2 80089da: d027 beq.n 8008a2c 80089dc: 68fb ldr r3, [r7, #12] 80089de: 681b ldr r3, [r3, #0] 80089e0: 4a28 ldr r2, [pc, #160] @ (8008a84 ) 80089e2: 4293 cmp r3, r2 80089e4: d022 beq.n 8008a2c 80089e6: 68fb ldr r3, [r7, #12] 80089e8: 681b ldr r3, [r3, #0] 80089ea: 4a27 ldr r2, [pc, #156] @ (8008a88 ) 80089ec: 4293 cmp r3, r2 80089ee: d01d beq.n 8008a2c 80089f0: 68fb ldr r3, [r7, #12] 80089f2: 681b ldr r3, [r3, #0] 80089f4: 4a25 ldr r2, [pc, #148] @ (8008a8c ) 80089f6: 4293 cmp r3, r2 80089f8: d018 beq.n 8008a2c 80089fa: 68fb ldr r3, [r7, #12] 80089fc: 681b ldr r3, [r3, #0] 80089fe: 4a24 ldr r2, [pc, #144] @ (8008a90 ) 8008a00: 4293 cmp r3, r2 8008a02: d013 beq.n 8008a2c 8008a04: 68fb ldr r3, [r7, #12] 8008a06: 681b ldr r3, [r3, #0] 8008a08: 4a22 ldr r2, [pc, #136] @ (8008a94 ) 8008a0a: 4293 cmp r3, r2 8008a0c: d00e beq.n 8008a2c 8008a0e: 68fb ldr r3, [r7, #12] 8008a10: 681b ldr r3, [r3, #0] 8008a12: 4a21 ldr r2, [pc, #132] @ (8008a98 ) 8008a14: 4293 cmp r3, r2 8008a16: d009 beq.n 8008a2c 8008a18: 68fb ldr r3, [r7, #12] 8008a1a: 681b ldr r3, [r3, #0] 8008a1c: 4a1f ldr r2, [pc, #124] @ (8008a9c ) 8008a1e: 4293 cmp r3, r2 8008a20: d004 beq.n 8008a2c 8008a22: 68fb ldr r3, [r7, #12] 8008a24: 681b ldr r3, [r3, #0] 8008a26: 4a1e ldr r2, [pc, #120] @ (8008aa0 ) 8008a28: 4293 cmp r3, r2 8008a2a: d101 bne.n 8008a30 8008a2c: 2301 movs r3, #1 8008a2e: e000 b.n 8008a32 8008a30: 2300 movs r3, #0 8008a32: 2b00 cmp r3, #0 8008a34: d036 beq.n 8008aa4 { /* Enable Common interrupts*/ MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 8008a36: 68fb ldr r3, [r7, #12] 8008a38: 681b ldr r3, [r3, #0] 8008a3a: 681b ldr r3, [r3, #0] 8008a3c: f023 021e bic.w r2, r3, #30 8008a40: 68fb ldr r3, [r7, #12] 8008a42: 681b ldr r3, [r3, #0] 8008a44: f042 0216 orr.w r2, r2, #22 8008a48: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8008a4a: 68fb ldr r3, [r7, #12] 8008a4c: 6c1b ldr r3, [r3, #64] @ 0x40 8008a4e: 2b00 cmp r3, #0 8008a50: d03e beq.n 8008ad0 { /* Enable Half Transfer IT if corresponding Callback is set */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; 8008a52: 68fb ldr r3, [r7, #12] 8008a54: 681b ldr r3, [r3, #0] 8008a56: 681a ldr r2, [r3, #0] 8008a58: 68fb ldr r3, [r7, #12] 8008a5a: 681b ldr r3, [r3, #0] 8008a5c: f042 0208 orr.w r2, r2, #8 8008a60: 601a str r2, [r3, #0] 8008a62: e035 b.n 8008ad0 8008a64: 40020010 .word 0x40020010 8008a68: 40020028 .word 0x40020028 8008a6c: 40020040 .word 0x40020040 8008a70: 40020058 .word 0x40020058 8008a74: 40020070 .word 0x40020070 8008a78: 40020088 .word 0x40020088 8008a7c: 400200a0 .word 0x400200a0 8008a80: 400200b8 .word 0x400200b8 8008a84: 40020410 .word 0x40020410 8008a88: 40020428 .word 0x40020428 8008a8c: 40020440 .word 0x40020440 8008a90: 40020458 .word 0x40020458 8008a94: 40020470 .word 0x40020470 8008a98: 40020488 .word 0x40020488 8008a9c: 400204a0 .word 0x400204a0 8008aa0: 400204b8 .word 0x400204b8 } } else /* BDMA channel */ { /* Enable Common interrupts */ MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE)); 8008aa4: 68fb ldr r3, [r7, #12] 8008aa6: 681b ldr r3, [r3, #0] 8008aa8: 681b ldr r3, [r3, #0] 8008aaa: f023 020e bic.w r2, r3, #14 8008aae: 68fb ldr r3, [r7, #12] 8008ab0: 681b ldr r3, [r3, #0] 8008ab2: f042 020a orr.w r2, r2, #10 8008ab6: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8008ab8: 68fb ldr r3, [r7, #12] 8008aba: 6c1b ldr r3, [r3, #64] @ 0x40 8008abc: 2b00 cmp r3, #0 8008abe: d007 beq.n 8008ad0 { /*Enable Half Transfer IT if corresponding Callback is set */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; 8008ac0: 68fb ldr r3, [r7, #12] 8008ac2: 681b ldr r3, [r3, #0] 8008ac4: 681a ldr r2, [r3, #0] 8008ac6: 68fb ldr r3, [r7, #12] 8008ac8: 681b ldr r3, [r3, #0] 8008aca: f042 0204 orr.w r2, r2, #4 8008ace: 601a str r2, [r3, #0] } } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8008ad0: 68fb ldr r3, [r7, #12] 8008ad2: 681b ldr r3, [r3, #0] 8008ad4: 4a83 ldr r2, [pc, #524] @ (8008ce4 ) 8008ad6: 4293 cmp r3, r2 8008ad8: d072 beq.n 8008bc0 8008ada: 68fb ldr r3, [r7, #12] 8008adc: 681b ldr r3, [r3, #0] 8008ade: 4a82 ldr r2, [pc, #520] @ (8008ce8 ) 8008ae0: 4293 cmp r3, r2 8008ae2: d06d beq.n 8008bc0 8008ae4: 68fb ldr r3, [r7, #12] 8008ae6: 681b ldr r3, [r3, #0] 8008ae8: 4a80 ldr r2, [pc, #512] @ (8008cec ) 8008aea: 4293 cmp r3, r2 8008aec: d068 beq.n 8008bc0 8008aee: 68fb ldr r3, [r7, #12] 8008af0: 681b ldr r3, [r3, #0] 8008af2: 4a7f ldr r2, [pc, #508] @ (8008cf0 ) 8008af4: 4293 cmp r3, r2 8008af6: d063 beq.n 8008bc0 8008af8: 68fb ldr r3, [r7, #12] 8008afa: 681b ldr r3, [r3, #0] 8008afc: 4a7d ldr r2, [pc, #500] @ (8008cf4 ) 8008afe: 4293 cmp r3, r2 8008b00: d05e beq.n 8008bc0 8008b02: 68fb ldr r3, [r7, #12] 8008b04: 681b ldr r3, [r3, #0] 8008b06: 4a7c ldr r2, [pc, #496] @ (8008cf8 ) 8008b08: 4293 cmp r3, r2 8008b0a: d059 beq.n 8008bc0 8008b0c: 68fb ldr r3, [r7, #12] 8008b0e: 681b ldr r3, [r3, #0] 8008b10: 4a7a ldr r2, [pc, #488] @ (8008cfc ) 8008b12: 4293 cmp r3, r2 8008b14: d054 beq.n 8008bc0 8008b16: 68fb ldr r3, [r7, #12] 8008b18: 681b ldr r3, [r3, #0] 8008b1a: 4a79 ldr r2, [pc, #484] @ (8008d00 ) 8008b1c: 4293 cmp r3, r2 8008b1e: d04f beq.n 8008bc0 8008b20: 68fb ldr r3, [r7, #12] 8008b22: 681b ldr r3, [r3, #0] 8008b24: 4a77 ldr r2, [pc, #476] @ (8008d04 ) 8008b26: 4293 cmp r3, r2 8008b28: d04a beq.n 8008bc0 8008b2a: 68fb ldr r3, [r7, #12] 8008b2c: 681b ldr r3, [r3, #0] 8008b2e: 4a76 ldr r2, [pc, #472] @ (8008d08 ) 8008b30: 4293 cmp r3, r2 8008b32: d045 beq.n 8008bc0 8008b34: 68fb ldr r3, [r7, #12] 8008b36: 681b ldr r3, [r3, #0] 8008b38: 4a74 ldr r2, [pc, #464] @ (8008d0c ) 8008b3a: 4293 cmp r3, r2 8008b3c: d040 beq.n 8008bc0 8008b3e: 68fb ldr r3, [r7, #12] 8008b40: 681b ldr r3, [r3, #0] 8008b42: 4a73 ldr r2, [pc, #460] @ (8008d10 ) 8008b44: 4293 cmp r3, r2 8008b46: d03b beq.n 8008bc0 8008b48: 68fb ldr r3, [r7, #12] 8008b4a: 681b ldr r3, [r3, #0] 8008b4c: 4a71 ldr r2, [pc, #452] @ (8008d14 ) 8008b4e: 4293 cmp r3, r2 8008b50: d036 beq.n 8008bc0 8008b52: 68fb ldr r3, [r7, #12] 8008b54: 681b ldr r3, [r3, #0] 8008b56: 4a70 ldr r2, [pc, #448] @ (8008d18 ) 8008b58: 4293 cmp r3, r2 8008b5a: d031 beq.n 8008bc0 8008b5c: 68fb ldr r3, [r7, #12] 8008b5e: 681b ldr r3, [r3, #0] 8008b60: 4a6e ldr r2, [pc, #440] @ (8008d1c ) 8008b62: 4293 cmp r3, r2 8008b64: d02c beq.n 8008bc0 8008b66: 68fb ldr r3, [r7, #12] 8008b68: 681b ldr r3, [r3, #0] 8008b6a: 4a6d ldr r2, [pc, #436] @ (8008d20 ) 8008b6c: 4293 cmp r3, r2 8008b6e: d027 beq.n 8008bc0 8008b70: 68fb ldr r3, [r7, #12] 8008b72: 681b ldr r3, [r3, #0] 8008b74: 4a6b ldr r2, [pc, #428] @ (8008d24 ) 8008b76: 4293 cmp r3, r2 8008b78: d022 beq.n 8008bc0 8008b7a: 68fb ldr r3, [r7, #12] 8008b7c: 681b ldr r3, [r3, #0] 8008b7e: 4a6a ldr r2, [pc, #424] @ (8008d28 ) 8008b80: 4293 cmp r3, r2 8008b82: d01d beq.n 8008bc0 8008b84: 68fb ldr r3, [r7, #12] 8008b86: 681b ldr r3, [r3, #0] 8008b88: 4a68 ldr r2, [pc, #416] @ (8008d2c ) 8008b8a: 4293 cmp r3, r2 8008b8c: d018 beq.n 8008bc0 8008b8e: 68fb ldr r3, [r7, #12] 8008b90: 681b ldr r3, [r3, #0] 8008b92: 4a67 ldr r2, [pc, #412] @ (8008d30 ) 8008b94: 4293 cmp r3, r2 8008b96: d013 beq.n 8008bc0 8008b98: 68fb ldr r3, [r7, #12] 8008b9a: 681b ldr r3, [r3, #0] 8008b9c: 4a65 ldr r2, [pc, #404] @ (8008d34 ) 8008b9e: 4293 cmp r3, r2 8008ba0: d00e beq.n 8008bc0 8008ba2: 68fb ldr r3, [r7, #12] 8008ba4: 681b ldr r3, [r3, #0] 8008ba6: 4a64 ldr r2, [pc, #400] @ (8008d38 ) 8008ba8: 4293 cmp r3, r2 8008baa: d009 beq.n 8008bc0 8008bac: 68fb ldr r3, [r7, #12] 8008bae: 681b ldr r3, [r3, #0] 8008bb0: 4a62 ldr r2, [pc, #392] @ (8008d3c ) 8008bb2: 4293 cmp r3, r2 8008bb4: d004 beq.n 8008bc0 8008bb6: 68fb ldr r3, [r7, #12] 8008bb8: 681b ldr r3, [r3, #0] 8008bba: 4a61 ldr r2, [pc, #388] @ (8008d40 ) 8008bbc: 4293 cmp r3, r2 8008bbe: d101 bne.n 8008bc4 8008bc0: 2301 movs r3, #1 8008bc2: e000 b.n 8008bc6 8008bc4: 2300 movs r3, #0 8008bc6: 2b00 cmp r3, #0 8008bc8: d01a beq.n 8008c00 { /* Check if DMAMUX Synchronization is enabled */ if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) 8008bca: 68fb ldr r3, [r7, #12] 8008bcc: 6e1b ldr r3, [r3, #96] @ 0x60 8008bce: 681b ldr r3, [r3, #0] 8008bd0: f403 3380 and.w r3, r3, #65536 @ 0x10000 8008bd4: 2b00 cmp r3, #0 8008bd6: d007 beq.n 8008be8 { /* Enable DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; 8008bd8: 68fb ldr r3, [r7, #12] 8008bda: 6e1b ldr r3, [r3, #96] @ 0x60 8008bdc: 681a ldr r2, [r3, #0] 8008bde: 68fb ldr r3, [r7, #12] 8008be0: 6e1b ldr r3, [r3, #96] @ 0x60 8008be2: f442 7280 orr.w r2, r2, #256 @ 0x100 8008be6: 601a str r2, [r3, #0] } if(hdma->DMAmuxRequestGen != 0U) 8008be8: 68fb ldr r3, [r7, #12] 8008bea: 6edb ldr r3, [r3, #108] @ 0x6c 8008bec: 2b00 cmp r3, #0 8008bee: d007 beq.n 8008c00 { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 8008bf0: 68fb ldr r3, [r7, #12] 8008bf2: 6edb ldr r3, [r3, #108] @ 0x6c 8008bf4: 681a ldr r2, [r3, #0] 8008bf6: 68fb ldr r3, [r7, #12] 8008bf8: 6edb ldr r3, [r3, #108] @ 0x6c 8008bfa: f442 7280 orr.w r2, r2, #256 @ 0x100 8008bfe: 601a str r2, [r3, #0] } } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8008c00: 68fb ldr r3, [r7, #12] 8008c02: 681b ldr r3, [r3, #0] 8008c04: 4a37 ldr r2, [pc, #220] @ (8008ce4 ) 8008c06: 4293 cmp r3, r2 8008c08: d04a beq.n 8008ca0 8008c0a: 68fb ldr r3, [r7, #12] 8008c0c: 681b ldr r3, [r3, #0] 8008c0e: 4a36 ldr r2, [pc, #216] @ (8008ce8 ) 8008c10: 4293 cmp r3, r2 8008c12: d045 beq.n 8008ca0 8008c14: 68fb ldr r3, [r7, #12] 8008c16: 681b ldr r3, [r3, #0] 8008c18: 4a34 ldr r2, [pc, #208] @ (8008cec ) 8008c1a: 4293 cmp r3, r2 8008c1c: d040 beq.n 8008ca0 8008c1e: 68fb ldr r3, [r7, #12] 8008c20: 681b ldr r3, [r3, #0] 8008c22: 4a33 ldr r2, [pc, #204] @ (8008cf0 ) 8008c24: 4293 cmp r3, r2 8008c26: d03b beq.n 8008ca0 8008c28: 68fb ldr r3, [r7, #12] 8008c2a: 681b ldr r3, [r3, #0] 8008c2c: 4a31 ldr r2, [pc, #196] @ (8008cf4 ) 8008c2e: 4293 cmp r3, r2 8008c30: d036 beq.n 8008ca0 8008c32: 68fb ldr r3, [r7, #12] 8008c34: 681b ldr r3, [r3, #0] 8008c36: 4a30 ldr r2, [pc, #192] @ (8008cf8 ) 8008c38: 4293 cmp r3, r2 8008c3a: d031 beq.n 8008ca0 8008c3c: 68fb ldr r3, [r7, #12] 8008c3e: 681b ldr r3, [r3, #0] 8008c40: 4a2e ldr r2, [pc, #184] @ (8008cfc ) 8008c42: 4293 cmp r3, r2 8008c44: d02c beq.n 8008ca0 8008c46: 68fb ldr r3, [r7, #12] 8008c48: 681b ldr r3, [r3, #0] 8008c4a: 4a2d ldr r2, [pc, #180] @ (8008d00 ) 8008c4c: 4293 cmp r3, r2 8008c4e: d027 beq.n 8008ca0 8008c50: 68fb ldr r3, [r7, #12] 8008c52: 681b ldr r3, [r3, #0] 8008c54: 4a2b ldr r2, [pc, #172] @ (8008d04 ) 8008c56: 4293 cmp r3, r2 8008c58: d022 beq.n 8008ca0 8008c5a: 68fb ldr r3, [r7, #12] 8008c5c: 681b ldr r3, [r3, #0] 8008c5e: 4a2a ldr r2, [pc, #168] @ (8008d08 ) 8008c60: 4293 cmp r3, r2 8008c62: d01d beq.n 8008ca0 8008c64: 68fb ldr r3, [r7, #12] 8008c66: 681b ldr r3, [r3, #0] 8008c68: 4a28 ldr r2, [pc, #160] @ (8008d0c ) 8008c6a: 4293 cmp r3, r2 8008c6c: d018 beq.n 8008ca0 8008c6e: 68fb ldr r3, [r7, #12] 8008c70: 681b ldr r3, [r3, #0] 8008c72: 4a27 ldr r2, [pc, #156] @ (8008d10 ) 8008c74: 4293 cmp r3, r2 8008c76: d013 beq.n 8008ca0 8008c78: 68fb ldr r3, [r7, #12] 8008c7a: 681b ldr r3, [r3, #0] 8008c7c: 4a25 ldr r2, [pc, #148] @ (8008d14 ) 8008c7e: 4293 cmp r3, r2 8008c80: d00e beq.n 8008ca0 8008c82: 68fb ldr r3, [r7, #12] 8008c84: 681b ldr r3, [r3, #0] 8008c86: 4a24 ldr r2, [pc, #144] @ (8008d18 ) 8008c88: 4293 cmp r3, r2 8008c8a: d009 beq.n 8008ca0 8008c8c: 68fb ldr r3, [r7, #12] 8008c8e: 681b ldr r3, [r3, #0] 8008c90: 4a22 ldr r2, [pc, #136] @ (8008d1c ) 8008c92: 4293 cmp r3, r2 8008c94: d004 beq.n 8008ca0 8008c96: 68fb ldr r3, [r7, #12] 8008c98: 681b ldr r3, [r3, #0] 8008c9a: 4a21 ldr r2, [pc, #132] @ (8008d20 ) 8008c9c: 4293 cmp r3, r2 8008c9e: d108 bne.n 8008cb2 8008ca0: 68fb ldr r3, [r7, #12] 8008ca2: 681b ldr r3, [r3, #0] 8008ca4: 681a ldr r2, [r3, #0] 8008ca6: 68fb ldr r3, [r7, #12] 8008ca8: 681b ldr r3, [r3, #0] 8008caa: f042 0201 orr.w r2, r2, #1 8008cae: 601a str r2, [r3, #0] 8008cb0: e012 b.n 8008cd8 8008cb2: 68fb ldr r3, [r7, #12] 8008cb4: 681b ldr r3, [r3, #0] 8008cb6: 681a ldr r2, [r3, #0] 8008cb8: 68fb ldr r3, [r7, #12] 8008cba: 681b ldr r3, [r3, #0] 8008cbc: f042 0201 orr.w r2, r2, #1 8008cc0: 601a str r2, [r3, #0] 8008cc2: e009 b.n 8008cd8 } else { /* Set the error code to busy */ hdma->ErrorCode = HAL_DMA_ERROR_BUSY; 8008cc4: 68fb ldr r3, [r7, #12] 8008cc6: f44f 6200 mov.w r2, #2048 @ 0x800 8008cca: 655a str r2, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hdma); 8008ccc: 68fb ldr r3, [r7, #12] 8008cce: 2200 movs r2, #0 8008cd0: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Return error status */ status = HAL_ERROR; 8008cd4: 2301 movs r3, #1 8008cd6: 75fb strb r3, [r7, #23] } return status; 8008cd8: 7dfb ldrb r3, [r7, #23] } 8008cda: 4618 mov r0, r3 8008cdc: 3718 adds r7, #24 8008cde: 46bd mov sp, r7 8008ce0: bd80 pop {r7, pc} 8008ce2: bf00 nop 8008ce4: 40020010 .word 0x40020010 8008ce8: 40020028 .word 0x40020028 8008cec: 40020040 .word 0x40020040 8008cf0: 40020058 .word 0x40020058 8008cf4: 40020070 .word 0x40020070 8008cf8: 40020088 .word 0x40020088 8008cfc: 400200a0 .word 0x400200a0 8008d00: 400200b8 .word 0x400200b8 8008d04: 40020410 .word 0x40020410 8008d08: 40020428 .word 0x40020428 8008d0c: 40020440 .word 0x40020440 8008d10: 40020458 .word 0x40020458 8008d14: 40020470 .word 0x40020470 8008d18: 40020488 .word 0x40020488 8008d1c: 400204a0 .word 0x400204a0 8008d20: 400204b8 .word 0x400204b8 8008d24: 58025408 .word 0x58025408 8008d28: 5802541c .word 0x5802541c 8008d2c: 58025430 .word 0x58025430 8008d30: 58025444 .word 0x58025444 8008d34: 58025458 .word 0x58025458 8008d38: 5802546c .word 0x5802546c 8008d3c: 58025480 .word 0x58025480 8008d40: 58025494 .word 0x58025494 08008d44 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8008d44: b580 push {r7, lr} 8008d46: b086 sub sp, #24 8008d48: af00 add r7, sp, #0 8008d4a: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; const __IO uint32_t *enableRegister; uint32_t tickstart = HAL_GetTick(); 8008d4c: f7fc fda6 bl 800589c 8008d50: 6138 str r0, [r7, #16] /* Check the DMA peripheral handle */ if(hdma == NULL) 8008d52: 687b ldr r3, [r7, #4] 8008d54: 2b00 cmp r3, #0 8008d56: d101 bne.n 8008d5c { return HAL_ERROR; 8008d58: 2301 movs r3, #1 8008d5a: e2dc b.n 8009316 } /* Check the DMA peripheral state */ if(hdma->State != HAL_DMA_STATE_BUSY) 8008d5c: 687b ldr r3, [r7, #4] 8008d5e: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8008d62: b2db uxtb r3, r3 8008d64: 2b02 cmp r3, #2 8008d66: d008 beq.n 8008d7a { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8008d68: 687b ldr r3, [r7, #4] 8008d6a: 2280 movs r2, #128 @ 0x80 8008d6c: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8008d6e: 687b ldr r3, [r7, #4] 8008d70: 2200 movs r2, #0 8008d72: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8008d76: 2301 movs r3, #1 8008d78: e2cd b.n 8009316 } else { /* Disable all the transfer interrupts */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8008d7a: 687b ldr r3, [r7, #4] 8008d7c: 681b ldr r3, [r3, #0] 8008d7e: 4a76 ldr r2, [pc, #472] @ (8008f58 ) 8008d80: 4293 cmp r3, r2 8008d82: d04a beq.n 8008e1a 8008d84: 687b ldr r3, [r7, #4] 8008d86: 681b ldr r3, [r3, #0] 8008d88: 4a74 ldr r2, [pc, #464] @ (8008f5c ) 8008d8a: 4293 cmp r3, r2 8008d8c: d045 beq.n 8008e1a 8008d8e: 687b ldr r3, [r7, #4] 8008d90: 681b ldr r3, [r3, #0] 8008d92: 4a73 ldr r2, [pc, #460] @ (8008f60 ) 8008d94: 4293 cmp r3, r2 8008d96: d040 beq.n 8008e1a 8008d98: 687b ldr r3, [r7, #4] 8008d9a: 681b ldr r3, [r3, #0] 8008d9c: 4a71 ldr r2, [pc, #452] @ (8008f64 ) 8008d9e: 4293 cmp r3, r2 8008da0: d03b beq.n 8008e1a 8008da2: 687b ldr r3, [r7, #4] 8008da4: 681b ldr r3, [r3, #0] 8008da6: 4a70 ldr r2, [pc, #448] @ (8008f68 ) 8008da8: 4293 cmp r3, r2 8008daa: d036 beq.n 8008e1a 8008dac: 687b ldr r3, [r7, #4] 8008dae: 681b ldr r3, [r3, #0] 8008db0: 4a6e ldr r2, [pc, #440] @ (8008f6c ) 8008db2: 4293 cmp r3, r2 8008db4: d031 beq.n 8008e1a 8008db6: 687b ldr r3, [r7, #4] 8008db8: 681b ldr r3, [r3, #0] 8008dba: 4a6d ldr r2, [pc, #436] @ (8008f70 ) 8008dbc: 4293 cmp r3, r2 8008dbe: d02c beq.n 8008e1a 8008dc0: 687b ldr r3, [r7, #4] 8008dc2: 681b ldr r3, [r3, #0] 8008dc4: 4a6b ldr r2, [pc, #428] @ (8008f74 ) 8008dc6: 4293 cmp r3, r2 8008dc8: d027 beq.n 8008e1a 8008dca: 687b ldr r3, [r7, #4] 8008dcc: 681b ldr r3, [r3, #0] 8008dce: 4a6a ldr r2, [pc, #424] @ (8008f78 ) 8008dd0: 4293 cmp r3, r2 8008dd2: d022 beq.n 8008e1a 8008dd4: 687b ldr r3, [r7, #4] 8008dd6: 681b ldr r3, [r3, #0] 8008dd8: 4a68 ldr r2, [pc, #416] @ (8008f7c ) 8008dda: 4293 cmp r3, r2 8008ddc: d01d beq.n 8008e1a 8008dde: 687b ldr r3, [r7, #4] 8008de0: 681b ldr r3, [r3, #0] 8008de2: 4a67 ldr r2, [pc, #412] @ (8008f80 ) 8008de4: 4293 cmp r3, r2 8008de6: d018 beq.n 8008e1a 8008de8: 687b ldr r3, [r7, #4] 8008dea: 681b ldr r3, [r3, #0] 8008dec: 4a65 ldr r2, [pc, #404] @ (8008f84 ) 8008dee: 4293 cmp r3, r2 8008df0: d013 beq.n 8008e1a 8008df2: 687b ldr r3, [r7, #4] 8008df4: 681b ldr r3, [r3, #0] 8008df6: 4a64 ldr r2, [pc, #400] @ (8008f88 ) 8008df8: 4293 cmp r3, r2 8008dfa: d00e beq.n 8008e1a 8008dfc: 687b ldr r3, [r7, #4] 8008dfe: 681b ldr r3, [r3, #0] 8008e00: 4a62 ldr r2, [pc, #392] @ (8008f8c ) 8008e02: 4293 cmp r3, r2 8008e04: d009 beq.n 8008e1a 8008e06: 687b ldr r3, [r7, #4] 8008e08: 681b ldr r3, [r3, #0] 8008e0a: 4a61 ldr r2, [pc, #388] @ (8008f90 ) 8008e0c: 4293 cmp r3, r2 8008e0e: d004 beq.n 8008e1a 8008e10: 687b ldr r3, [r7, #4] 8008e12: 681b ldr r3, [r3, #0] 8008e14: 4a5f ldr r2, [pc, #380] @ (8008f94 ) 8008e16: 4293 cmp r3, r2 8008e18: d101 bne.n 8008e1e 8008e1a: 2301 movs r3, #1 8008e1c: e000 b.n 8008e20 8008e1e: 2300 movs r3, #0 8008e20: 2b00 cmp r3, #0 8008e22: d013 beq.n 8008e4c { /* Disable DMA All Interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 8008e24: 687b ldr r3, [r7, #4] 8008e26: 681b ldr r3, [r3, #0] 8008e28: 681a ldr r2, [r3, #0] 8008e2a: 687b ldr r3, [r7, #4] 8008e2c: 681b ldr r3, [r3, #0] 8008e2e: f022 021e bic.w r2, r2, #30 8008e32: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 8008e34: 687b ldr r3, [r7, #4] 8008e36: 681b ldr r3, [r3, #0] 8008e38: 695a ldr r2, [r3, #20] 8008e3a: 687b ldr r3, [r7, #4] 8008e3c: 681b ldr r3, [r3, #0] 8008e3e: f022 0280 bic.w r2, r2, #128 @ 0x80 8008e42: 615a str r2, [r3, #20] enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); 8008e44: 687b ldr r3, [r7, #4] 8008e46: 681b ldr r3, [r3, #0] 8008e48: 617b str r3, [r7, #20] 8008e4a: e00a b.n 8008e62 } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 8008e4c: 687b ldr r3, [r7, #4] 8008e4e: 681b ldr r3, [r3, #0] 8008e50: 681a ldr r2, [r3, #0] 8008e52: 687b ldr r3, [r7, #4] 8008e54: 681b ldr r3, [r3, #0] 8008e56: f022 020e bic.w r2, r2, #14 8008e5a: 601a str r2, [r3, #0] enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); 8008e5c: 687b ldr r3, [r7, #4] 8008e5e: 681b ldr r3, [r3, #0] 8008e60: 617b str r3, [r7, #20] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8008e62: 687b ldr r3, [r7, #4] 8008e64: 681b ldr r3, [r3, #0] 8008e66: 4a3c ldr r2, [pc, #240] @ (8008f58 ) 8008e68: 4293 cmp r3, r2 8008e6a: d072 beq.n 8008f52 8008e6c: 687b ldr r3, [r7, #4] 8008e6e: 681b ldr r3, [r3, #0] 8008e70: 4a3a ldr r2, [pc, #232] @ (8008f5c ) 8008e72: 4293 cmp r3, r2 8008e74: d06d beq.n 8008f52 8008e76: 687b ldr r3, [r7, #4] 8008e78: 681b ldr r3, [r3, #0] 8008e7a: 4a39 ldr r2, [pc, #228] @ (8008f60 ) 8008e7c: 4293 cmp r3, r2 8008e7e: d068 beq.n 8008f52 8008e80: 687b ldr r3, [r7, #4] 8008e82: 681b ldr r3, [r3, #0] 8008e84: 4a37 ldr r2, [pc, #220] @ (8008f64 ) 8008e86: 4293 cmp r3, r2 8008e88: d063 beq.n 8008f52 8008e8a: 687b ldr r3, [r7, #4] 8008e8c: 681b ldr r3, [r3, #0] 8008e8e: 4a36 ldr r2, [pc, #216] @ (8008f68 ) 8008e90: 4293 cmp r3, r2 8008e92: d05e beq.n 8008f52 8008e94: 687b ldr r3, [r7, #4] 8008e96: 681b ldr r3, [r3, #0] 8008e98: 4a34 ldr r2, [pc, #208] @ (8008f6c ) 8008e9a: 4293 cmp r3, r2 8008e9c: d059 beq.n 8008f52 8008e9e: 687b ldr r3, [r7, #4] 8008ea0: 681b ldr r3, [r3, #0] 8008ea2: 4a33 ldr r2, [pc, #204] @ (8008f70 ) 8008ea4: 4293 cmp r3, r2 8008ea6: d054 beq.n 8008f52 8008ea8: 687b ldr r3, [r7, #4] 8008eaa: 681b ldr r3, [r3, #0] 8008eac: 4a31 ldr r2, [pc, #196] @ (8008f74 ) 8008eae: 4293 cmp r3, r2 8008eb0: d04f beq.n 8008f52 8008eb2: 687b ldr r3, [r7, #4] 8008eb4: 681b ldr r3, [r3, #0] 8008eb6: 4a30 ldr r2, [pc, #192] @ (8008f78 ) 8008eb8: 4293 cmp r3, r2 8008eba: d04a beq.n 8008f52 8008ebc: 687b ldr r3, [r7, #4] 8008ebe: 681b ldr r3, [r3, #0] 8008ec0: 4a2e ldr r2, [pc, #184] @ (8008f7c ) 8008ec2: 4293 cmp r3, r2 8008ec4: d045 beq.n 8008f52 8008ec6: 687b ldr r3, [r7, #4] 8008ec8: 681b ldr r3, [r3, #0] 8008eca: 4a2d ldr r2, [pc, #180] @ (8008f80 ) 8008ecc: 4293 cmp r3, r2 8008ece: d040 beq.n 8008f52 8008ed0: 687b ldr r3, [r7, #4] 8008ed2: 681b ldr r3, [r3, #0] 8008ed4: 4a2b ldr r2, [pc, #172] @ (8008f84 ) 8008ed6: 4293 cmp r3, r2 8008ed8: d03b beq.n 8008f52 8008eda: 687b ldr r3, [r7, #4] 8008edc: 681b ldr r3, [r3, #0] 8008ede: 4a2a ldr r2, [pc, #168] @ (8008f88 ) 8008ee0: 4293 cmp r3, r2 8008ee2: d036 beq.n 8008f52 8008ee4: 687b ldr r3, [r7, #4] 8008ee6: 681b ldr r3, [r3, #0] 8008ee8: 4a28 ldr r2, [pc, #160] @ (8008f8c ) 8008eea: 4293 cmp r3, r2 8008eec: d031 beq.n 8008f52 8008eee: 687b ldr r3, [r7, #4] 8008ef0: 681b ldr r3, [r3, #0] 8008ef2: 4a27 ldr r2, [pc, #156] @ (8008f90 ) 8008ef4: 4293 cmp r3, r2 8008ef6: d02c beq.n 8008f52 8008ef8: 687b ldr r3, [r7, #4] 8008efa: 681b ldr r3, [r3, #0] 8008efc: 4a25 ldr r2, [pc, #148] @ (8008f94 ) 8008efe: 4293 cmp r3, r2 8008f00: d027 beq.n 8008f52 8008f02: 687b ldr r3, [r7, #4] 8008f04: 681b ldr r3, [r3, #0] 8008f06: 4a24 ldr r2, [pc, #144] @ (8008f98 ) 8008f08: 4293 cmp r3, r2 8008f0a: d022 beq.n 8008f52 8008f0c: 687b ldr r3, [r7, #4] 8008f0e: 681b ldr r3, [r3, #0] 8008f10: 4a22 ldr r2, [pc, #136] @ (8008f9c ) 8008f12: 4293 cmp r3, r2 8008f14: d01d beq.n 8008f52 8008f16: 687b ldr r3, [r7, #4] 8008f18: 681b ldr r3, [r3, #0] 8008f1a: 4a21 ldr r2, [pc, #132] @ (8008fa0 ) 8008f1c: 4293 cmp r3, r2 8008f1e: d018 beq.n 8008f52 8008f20: 687b ldr r3, [r7, #4] 8008f22: 681b ldr r3, [r3, #0] 8008f24: 4a1f ldr r2, [pc, #124] @ (8008fa4 ) 8008f26: 4293 cmp r3, r2 8008f28: d013 beq.n 8008f52 8008f2a: 687b ldr r3, [r7, #4] 8008f2c: 681b ldr r3, [r3, #0] 8008f2e: 4a1e ldr r2, [pc, #120] @ (8008fa8 ) 8008f30: 4293 cmp r3, r2 8008f32: d00e beq.n 8008f52 8008f34: 687b ldr r3, [r7, #4] 8008f36: 681b ldr r3, [r3, #0] 8008f38: 4a1c ldr r2, [pc, #112] @ (8008fac ) 8008f3a: 4293 cmp r3, r2 8008f3c: d009 beq.n 8008f52 8008f3e: 687b ldr r3, [r7, #4] 8008f40: 681b ldr r3, [r3, #0] 8008f42: 4a1b ldr r2, [pc, #108] @ (8008fb0 ) 8008f44: 4293 cmp r3, r2 8008f46: d004 beq.n 8008f52 8008f48: 687b ldr r3, [r7, #4] 8008f4a: 681b ldr r3, [r3, #0] 8008f4c: 4a19 ldr r2, [pc, #100] @ (8008fb4 ) 8008f4e: 4293 cmp r3, r2 8008f50: d132 bne.n 8008fb8 8008f52: 2301 movs r3, #1 8008f54: e031 b.n 8008fba 8008f56: bf00 nop 8008f58: 40020010 .word 0x40020010 8008f5c: 40020028 .word 0x40020028 8008f60: 40020040 .word 0x40020040 8008f64: 40020058 .word 0x40020058 8008f68: 40020070 .word 0x40020070 8008f6c: 40020088 .word 0x40020088 8008f70: 400200a0 .word 0x400200a0 8008f74: 400200b8 .word 0x400200b8 8008f78: 40020410 .word 0x40020410 8008f7c: 40020428 .word 0x40020428 8008f80: 40020440 .word 0x40020440 8008f84: 40020458 .word 0x40020458 8008f88: 40020470 .word 0x40020470 8008f8c: 40020488 .word 0x40020488 8008f90: 400204a0 .word 0x400204a0 8008f94: 400204b8 .word 0x400204b8 8008f98: 58025408 .word 0x58025408 8008f9c: 5802541c .word 0x5802541c 8008fa0: 58025430 .word 0x58025430 8008fa4: 58025444 .word 0x58025444 8008fa8: 58025458 .word 0x58025458 8008fac: 5802546c .word 0x5802546c 8008fb0: 58025480 .word 0x58025480 8008fb4: 58025494 .word 0x58025494 8008fb8: 2300 movs r3, #0 8008fba: 2b00 cmp r3, #0 8008fbc: d007 beq.n 8008fce { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8008fbe: 687b ldr r3, [r7, #4] 8008fc0: 6e1b ldr r3, [r3, #96] @ 0x60 8008fc2: 681a ldr r2, [r3, #0] 8008fc4: 687b ldr r3, [r7, #4] 8008fc6: 6e1b ldr r3, [r3, #96] @ 0x60 8008fc8: f422 7280 bic.w r2, r2, #256 @ 0x100 8008fcc: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8008fce: 687b ldr r3, [r7, #4] 8008fd0: 681b ldr r3, [r3, #0] 8008fd2: 4a6d ldr r2, [pc, #436] @ (8009188 ) 8008fd4: 4293 cmp r3, r2 8008fd6: d04a beq.n 800906e 8008fd8: 687b ldr r3, [r7, #4] 8008fda: 681b ldr r3, [r3, #0] 8008fdc: 4a6b ldr r2, [pc, #428] @ (800918c ) 8008fde: 4293 cmp r3, r2 8008fe0: d045 beq.n 800906e 8008fe2: 687b ldr r3, [r7, #4] 8008fe4: 681b ldr r3, [r3, #0] 8008fe6: 4a6a ldr r2, [pc, #424] @ (8009190 ) 8008fe8: 4293 cmp r3, r2 8008fea: d040 beq.n 800906e 8008fec: 687b ldr r3, [r7, #4] 8008fee: 681b ldr r3, [r3, #0] 8008ff0: 4a68 ldr r2, [pc, #416] @ (8009194 ) 8008ff2: 4293 cmp r3, r2 8008ff4: d03b beq.n 800906e 8008ff6: 687b ldr r3, [r7, #4] 8008ff8: 681b ldr r3, [r3, #0] 8008ffa: 4a67 ldr r2, [pc, #412] @ (8009198 ) 8008ffc: 4293 cmp r3, r2 8008ffe: d036 beq.n 800906e 8009000: 687b ldr r3, [r7, #4] 8009002: 681b ldr r3, [r3, #0] 8009004: 4a65 ldr r2, [pc, #404] @ (800919c ) 8009006: 4293 cmp r3, r2 8009008: d031 beq.n 800906e 800900a: 687b ldr r3, [r7, #4] 800900c: 681b ldr r3, [r3, #0] 800900e: 4a64 ldr r2, [pc, #400] @ (80091a0 ) 8009010: 4293 cmp r3, r2 8009012: d02c beq.n 800906e 8009014: 687b ldr r3, [r7, #4] 8009016: 681b ldr r3, [r3, #0] 8009018: 4a62 ldr r2, [pc, #392] @ (80091a4 ) 800901a: 4293 cmp r3, r2 800901c: d027 beq.n 800906e 800901e: 687b ldr r3, [r7, #4] 8009020: 681b ldr r3, [r3, #0] 8009022: 4a61 ldr r2, [pc, #388] @ (80091a8 ) 8009024: 4293 cmp r3, r2 8009026: d022 beq.n 800906e 8009028: 687b ldr r3, [r7, #4] 800902a: 681b ldr r3, [r3, #0] 800902c: 4a5f ldr r2, [pc, #380] @ (80091ac ) 800902e: 4293 cmp r3, r2 8009030: d01d beq.n 800906e 8009032: 687b ldr r3, [r7, #4] 8009034: 681b ldr r3, [r3, #0] 8009036: 4a5e ldr r2, [pc, #376] @ (80091b0 ) 8009038: 4293 cmp r3, r2 800903a: d018 beq.n 800906e 800903c: 687b ldr r3, [r7, #4] 800903e: 681b ldr r3, [r3, #0] 8009040: 4a5c ldr r2, [pc, #368] @ (80091b4 ) 8009042: 4293 cmp r3, r2 8009044: d013 beq.n 800906e 8009046: 687b ldr r3, [r7, #4] 8009048: 681b ldr r3, [r3, #0] 800904a: 4a5b ldr r2, [pc, #364] @ (80091b8 ) 800904c: 4293 cmp r3, r2 800904e: d00e beq.n 800906e 8009050: 687b ldr r3, [r7, #4] 8009052: 681b ldr r3, [r3, #0] 8009054: 4a59 ldr r2, [pc, #356] @ (80091bc ) 8009056: 4293 cmp r3, r2 8009058: d009 beq.n 800906e 800905a: 687b ldr r3, [r7, #4] 800905c: 681b ldr r3, [r3, #0] 800905e: 4a58 ldr r2, [pc, #352] @ (80091c0 ) 8009060: 4293 cmp r3, r2 8009062: d004 beq.n 800906e 8009064: 687b ldr r3, [r7, #4] 8009066: 681b ldr r3, [r3, #0] 8009068: 4a56 ldr r2, [pc, #344] @ (80091c4 ) 800906a: 4293 cmp r3, r2 800906c: d108 bne.n 8009080 800906e: 687b ldr r3, [r7, #4] 8009070: 681b ldr r3, [r3, #0] 8009072: 681a ldr r2, [r3, #0] 8009074: 687b ldr r3, [r7, #4] 8009076: 681b ldr r3, [r3, #0] 8009078: f022 0201 bic.w r2, r2, #1 800907c: 601a str r2, [r3, #0] 800907e: e007 b.n 8009090 8009080: 687b ldr r3, [r7, #4] 8009082: 681b ldr r3, [r3, #0] 8009084: 681a ldr r2, [r3, #0] 8009086: 687b ldr r3, [r7, #4] 8009088: 681b ldr r3, [r3, #0] 800908a: f022 0201 bic.w r2, r2, #1 800908e: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while(((*enableRegister) & DMA_SxCR_EN) != 0U) 8009090: e013 b.n 80090ba { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8009092: f7fc fc03 bl 800589c 8009096: 4602 mov r2, r0 8009098: 693b ldr r3, [r7, #16] 800909a: 1ad3 subs r3, r2, r3 800909c: 2b05 cmp r3, #5 800909e: d90c bls.n 80090ba { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 80090a0: 687b ldr r3, [r7, #4] 80090a2: 2220 movs r2, #32 80090a4: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 80090a6: 687b ldr r3, [r7, #4] 80090a8: 2203 movs r2, #3 80090aa: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80090ae: 687b ldr r3, [r7, #4] 80090b0: 2200 movs r2, #0 80090b2: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 80090b6: 2301 movs r3, #1 80090b8: e12d b.n 8009316 while(((*enableRegister) & DMA_SxCR_EN) != 0U) 80090ba: 697b ldr r3, [r7, #20] 80090bc: 681b ldr r3, [r3, #0] 80090be: f003 0301 and.w r3, r3, #1 80090c2: 2b00 cmp r3, #0 80090c4: d1e5 bne.n 8009092 } } /* Clear all interrupt flags at correct offset within the register */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80090c6: 687b ldr r3, [r7, #4] 80090c8: 681b ldr r3, [r3, #0] 80090ca: 4a2f ldr r2, [pc, #188] @ (8009188 ) 80090cc: 4293 cmp r3, r2 80090ce: d04a beq.n 8009166 80090d0: 687b ldr r3, [r7, #4] 80090d2: 681b ldr r3, [r3, #0] 80090d4: 4a2d ldr r2, [pc, #180] @ (800918c ) 80090d6: 4293 cmp r3, r2 80090d8: d045 beq.n 8009166 80090da: 687b ldr r3, [r7, #4] 80090dc: 681b ldr r3, [r3, #0] 80090de: 4a2c ldr r2, [pc, #176] @ (8009190 ) 80090e0: 4293 cmp r3, r2 80090e2: d040 beq.n 8009166 80090e4: 687b ldr r3, [r7, #4] 80090e6: 681b ldr r3, [r3, #0] 80090e8: 4a2a ldr r2, [pc, #168] @ (8009194 ) 80090ea: 4293 cmp r3, r2 80090ec: d03b beq.n 8009166 80090ee: 687b ldr r3, [r7, #4] 80090f0: 681b ldr r3, [r3, #0] 80090f2: 4a29 ldr r2, [pc, #164] @ (8009198 ) 80090f4: 4293 cmp r3, r2 80090f6: d036 beq.n 8009166 80090f8: 687b ldr r3, [r7, #4] 80090fa: 681b ldr r3, [r3, #0] 80090fc: 4a27 ldr r2, [pc, #156] @ (800919c ) 80090fe: 4293 cmp r3, r2 8009100: d031 beq.n 8009166 8009102: 687b ldr r3, [r7, #4] 8009104: 681b ldr r3, [r3, #0] 8009106: 4a26 ldr r2, [pc, #152] @ (80091a0 ) 8009108: 4293 cmp r3, r2 800910a: d02c beq.n 8009166 800910c: 687b ldr r3, [r7, #4] 800910e: 681b ldr r3, [r3, #0] 8009110: 4a24 ldr r2, [pc, #144] @ (80091a4 ) 8009112: 4293 cmp r3, r2 8009114: d027 beq.n 8009166 8009116: 687b ldr r3, [r7, #4] 8009118: 681b ldr r3, [r3, #0] 800911a: 4a23 ldr r2, [pc, #140] @ (80091a8 ) 800911c: 4293 cmp r3, r2 800911e: d022 beq.n 8009166 8009120: 687b ldr r3, [r7, #4] 8009122: 681b ldr r3, [r3, #0] 8009124: 4a21 ldr r2, [pc, #132] @ (80091ac ) 8009126: 4293 cmp r3, r2 8009128: d01d beq.n 8009166 800912a: 687b ldr r3, [r7, #4] 800912c: 681b ldr r3, [r3, #0] 800912e: 4a20 ldr r2, [pc, #128] @ (80091b0 ) 8009130: 4293 cmp r3, r2 8009132: d018 beq.n 8009166 8009134: 687b ldr r3, [r7, #4] 8009136: 681b ldr r3, [r3, #0] 8009138: 4a1e ldr r2, [pc, #120] @ (80091b4 ) 800913a: 4293 cmp r3, r2 800913c: d013 beq.n 8009166 800913e: 687b ldr r3, [r7, #4] 8009140: 681b ldr r3, [r3, #0] 8009142: 4a1d ldr r2, [pc, #116] @ (80091b8 ) 8009144: 4293 cmp r3, r2 8009146: d00e beq.n 8009166 8009148: 687b ldr r3, [r7, #4] 800914a: 681b ldr r3, [r3, #0] 800914c: 4a1b ldr r2, [pc, #108] @ (80091bc ) 800914e: 4293 cmp r3, r2 8009150: d009 beq.n 8009166 8009152: 687b ldr r3, [r7, #4] 8009154: 681b ldr r3, [r3, #0] 8009156: 4a1a ldr r2, [pc, #104] @ (80091c0 ) 8009158: 4293 cmp r3, r2 800915a: d004 beq.n 8009166 800915c: 687b ldr r3, [r7, #4] 800915e: 681b ldr r3, [r3, #0] 8009160: 4a18 ldr r2, [pc, #96] @ (80091c4 ) 8009162: 4293 cmp r3, r2 8009164: d101 bne.n 800916a 8009166: 2301 movs r3, #1 8009168: e000 b.n 800916c 800916a: 2300 movs r3, #0 800916c: 2b00 cmp r3, #0 800916e: d02b beq.n 80091c8 { regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8009170: 687b ldr r3, [r7, #4] 8009172: 6d9b ldr r3, [r3, #88] @ 0x58 8009174: 60bb str r3, [r7, #8] regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8009176: 687b ldr r3, [r7, #4] 8009178: 6ddb ldr r3, [r3, #92] @ 0x5c 800917a: f003 031f and.w r3, r3, #31 800917e: 223f movs r2, #63 @ 0x3f 8009180: 409a lsls r2, r3 8009182: 68bb ldr r3, [r7, #8] 8009184: 609a str r2, [r3, #8] 8009186: e02a b.n 80091de 8009188: 40020010 .word 0x40020010 800918c: 40020028 .word 0x40020028 8009190: 40020040 .word 0x40020040 8009194: 40020058 .word 0x40020058 8009198: 40020070 .word 0x40020070 800919c: 40020088 .word 0x40020088 80091a0: 400200a0 .word 0x400200a0 80091a4: 400200b8 .word 0x400200b8 80091a8: 40020410 .word 0x40020410 80091ac: 40020428 .word 0x40020428 80091b0: 40020440 .word 0x40020440 80091b4: 40020458 .word 0x40020458 80091b8: 40020470 .word 0x40020470 80091bc: 40020488 .word 0x40020488 80091c0: 400204a0 .word 0x400204a0 80091c4: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 80091c8: 687b ldr r3, [r7, #4] 80091ca: 6d9b ldr r3, [r3, #88] @ 0x58 80091cc: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 80091ce: 687b ldr r3, [r7, #4] 80091d0: 6ddb ldr r3, [r3, #92] @ 0x5c 80091d2: f003 031f and.w r3, r3, #31 80091d6: 2201 movs r2, #1 80091d8: 409a lsls r2, r3 80091da: 68fb ldr r3, [r7, #12] 80091dc: 605a str r2, [r3, #4] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80091de: 687b ldr r3, [r7, #4] 80091e0: 681b ldr r3, [r3, #0] 80091e2: 4a4f ldr r2, [pc, #316] @ (8009320 ) 80091e4: 4293 cmp r3, r2 80091e6: d072 beq.n 80092ce 80091e8: 687b ldr r3, [r7, #4] 80091ea: 681b ldr r3, [r3, #0] 80091ec: 4a4d ldr r2, [pc, #308] @ (8009324 ) 80091ee: 4293 cmp r3, r2 80091f0: d06d beq.n 80092ce 80091f2: 687b ldr r3, [r7, #4] 80091f4: 681b ldr r3, [r3, #0] 80091f6: 4a4c ldr r2, [pc, #304] @ (8009328 ) 80091f8: 4293 cmp r3, r2 80091fa: d068 beq.n 80092ce 80091fc: 687b ldr r3, [r7, #4] 80091fe: 681b ldr r3, [r3, #0] 8009200: 4a4a ldr r2, [pc, #296] @ (800932c ) 8009202: 4293 cmp r3, r2 8009204: d063 beq.n 80092ce 8009206: 687b ldr r3, [r7, #4] 8009208: 681b ldr r3, [r3, #0] 800920a: 4a49 ldr r2, [pc, #292] @ (8009330 ) 800920c: 4293 cmp r3, r2 800920e: d05e beq.n 80092ce 8009210: 687b ldr r3, [r7, #4] 8009212: 681b ldr r3, [r3, #0] 8009214: 4a47 ldr r2, [pc, #284] @ (8009334 ) 8009216: 4293 cmp r3, r2 8009218: d059 beq.n 80092ce 800921a: 687b ldr r3, [r7, #4] 800921c: 681b ldr r3, [r3, #0] 800921e: 4a46 ldr r2, [pc, #280] @ (8009338 ) 8009220: 4293 cmp r3, r2 8009222: d054 beq.n 80092ce 8009224: 687b ldr r3, [r7, #4] 8009226: 681b ldr r3, [r3, #0] 8009228: 4a44 ldr r2, [pc, #272] @ (800933c ) 800922a: 4293 cmp r3, r2 800922c: d04f beq.n 80092ce 800922e: 687b ldr r3, [r7, #4] 8009230: 681b ldr r3, [r3, #0] 8009232: 4a43 ldr r2, [pc, #268] @ (8009340 ) 8009234: 4293 cmp r3, r2 8009236: d04a beq.n 80092ce 8009238: 687b ldr r3, [r7, #4] 800923a: 681b ldr r3, [r3, #0] 800923c: 4a41 ldr r2, [pc, #260] @ (8009344 ) 800923e: 4293 cmp r3, r2 8009240: d045 beq.n 80092ce 8009242: 687b ldr r3, [r7, #4] 8009244: 681b ldr r3, [r3, #0] 8009246: 4a40 ldr r2, [pc, #256] @ (8009348 ) 8009248: 4293 cmp r3, r2 800924a: d040 beq.n 80092ce 800924c: 687b ldr r3, [r7, #4] 800924e: 681b ldr r3, [r3, #0] 8009250: 4a3e ldr r2, [pc, #248] @ (800934c ) 8009252: 4293 cmp r3, r2 8009254: d03b beq.n 80092ce 8009256: 687b ldr r3, [r7, #4] 8009258: 681b ldr r3, [r3, #0] 800925a: 4a3d ldr r2, [pc, #244] @ (8009350 ) 800925c: 4293 cmp r3, r2 800925e: d036 beq.n 80092ce 8009260: 687b ldr r3, [r7, #4] 8009262: 681b ldr r3, [r3, #0] 8009264: 4a3b ldr r2, [pc, #236] @ (8009354 ) 8009266: 4293 cmp r3, r2 8009268: d031 beq.n 80092ce 800926a: 687b ldr r3, [r7, #4] 800926c: 681b ldr r3, [r3, #0] 800926e: 4a3a ldr r2, [pc, #232] @ (8009358 ) 8009270: 4293 cmp r3, r2 8009272: d02c beq.n 80092ce 8009274: 687b ldr r3, [r7, #4] 8009276: 681b ldr r3, [r3, #0] 8009278: 4a38 ldr r2, [pc, #224] @ (800935c ) 800927a: 4293 cmp r3, r2 800927c: d027 beq.n 80092ce 800927e: 687b ldr r3, [r7, #4] 8009280: 681b ldr r3, [r3, #0] 8009282: 4a37 ldr r2, [pc, #220] @ (8009360 ) 8009284: 4293 cmp r3, r2 8009286: d022 beq.n 80092ce 8009288: 687b ldr r3, [r7, #4] 800928a: 681b ldr r3, [r3, #0] 800928c: 4a35 ldr r2, [pc, #212] @ (8009364 ) 800928e: 4293 cmp r3, r2 8009290: d01d beq.n 80092ce 8009292: 687b ldr r3, [r7, #4] 8009294: 681b ldr r3, [r3, #0] 8009296: 4a34 ldr r2, [pc, #208] @ (8009368 ) 8009298: 4293 cmp r3, r2 800929a: d018 beq.n 80092ce 800929c: 687b ldr r3, [r7, #4] 800929e: 681b ldr r3, [r3, #0] 80092a0: 4a32 ldr r2, [pc, #200] @ (800936c ) 80092a2: 4293 cmp r3, r2 80092a4: d013 beq.n 80092ce 80092a6: 687b ldr r3, [r7, #4] 80092a8: 681b ldr r3, [r3, #0] 80092aa: 4a31 ldr r2, [pc, #196] @ (8009370 ) 80092ac: 4293 cmp r3, r2 80092ae: d00e beq.n 80092ce 80092b0: 687b ldr r3, [r7, #4] 80092b2: 681b ldr r3, [r3, #0] 80092b4: 4a2f ldr r2, [pc, #188] @ (8009374 ) 80092b6: 4293 cmp r3, r2 80092b8: d009 beq.n 80092ce 80092ba: 687b ldr r3, [r7, #4] 80092bc: 681b ldr r3, [r3, #0] 80092be: 4a2e ldr r2, [pc, #184] @ (8009378 ) 80092c0: 4293 cmp r3, r2 80092c2: d004 beq.n 80092ce 80092c4: 687b ldr r3, [r7, #4] 80092c6: 681b ldr r3, [r3, #0] 80092c8: 4a2c ldr r2, [pc, #176] @ (800937c ) 80092ca: 4293 cmp r3, r2 80092cc: d101 bne.n 80092d2 80092ce: 2301 movs r3, #1 80092d0: e000 b.n 80092d4 80092d2: 2300 movs r3, #0 80092d4: 2b00 cmp r3, #0 80092d6: d015 beq.n 8009304 { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 80092d8: 687b ldr r3, [r7, #4] 80092da: 6e5b ldr r3, [r3, #100] @ 0x64 80092dc: 687a ldr r2, [r7, #4] 80092de: 6e92 ldr r2, [r2, #104] @ 0x68 80092e0: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 80092e2: 687b ldr r3, [r7, #4] 80092e4: 6edb ldr r3, [r3, #108] @ 0x6c 80092e6: 2b00 cmp r3, #0 80092e8: d00c beq.n 8009304 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 80092ea: 687b ldr r3, [r7, #4] 80092ec: 6edb ldr r3, [r3, #108] @ 0x6c 80092ee: 681a ldr r2, [r3, #0] 80092f0: 687b ldr r3, [r7, #4] 80092f2: 6edb ldr r3, [r3, #108] @ 0x6c 80092f4: f422 7280 bic.w r2, r2, #256 @ 0x100 80092f8: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 80092fa: 687b ldr r3, [r7, #4] 80092fc: 6f1b ldr r3, [r3, #112] @ 0x70 80092fe: 687a ldr r2, [r7, #4] 8009300: 6f52 ldr r2, [r2, #116] @ 0x74 8009302: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8009304: 687b ldr r3, [r7, #4] 8009306: 2201 movs r2, #1 8009308: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800930c: 687b ldr r3, [r7, #4] 800930e: 2200 movs r2, #0 8009310: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 8009314: 2300 movs r3, #0 } 8009316: 4618 mov r0, r3 8009318: 3718 adds r7, #24 800931a: 46bd mov sp, r7 800931c: bd80 pop {r7, pc} 800931e: bf00 nop 8009320: 40020010 .word 0x40020010 8009324: 40020028 .word 0x40020028 8009328: 40020040 .word 0x40020040 800932c: 40020058 .word 0x40020058 8009330: 40020070 .word 0x40020070 8009334: 40020088 .word 0x40020088 8009338: 400200a0 .word 0x400200a0 800933c: 400200b8 .word 0x400200b8 8009340: 40020410 .word 0x40020410 8009344: 40020428 .word 0x40020428 8009348: 40020440 .word 0x40020440 800934c: 40020458 .word 0x40020458 8009350: 40020470 .word 0x40020470 8009354: 40020488 .word 0x40020488 8009358: 400204a0 .word 0x400204a0 800935c: 400204b8 .word 0x400204b8 8009360: 58025408 .word 0x58025408 8009364: 5802541c .word 0x5802541c 8009368: 58025430 .word 0x58025430 800936c: 58025444 .word 0x58025444 8009370: 58025458 .word 0x58025458 8009374: 5802546c .word 0x5802546c 8009378: 58025480 .word 0x58025480 800937c: 58025494 .word 0x58025494 08009380 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8009380: b580 push {r7, lr} 8009382: b084 sub sp, #16 8009384: af00 add r7, sp, #0 8009386: 6078 str r0, [r7, #4] BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 8009388: 687b ldr r3, [r7, #4] 800938a: 2b00 cmp r3, #0 800938c: d101 bne.n 8009392 { return HAL_ERROR; 800938e: 2301 movs r3, #1 8009390: e237 b.n 8009802 } if(hdma->State != HAL_DMA_STATE_BUSY) 8009392: 687b ldr r3, [r7, #4] 8009394: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8009398: b2db uxtb r3, r3 800939a: 2b02 cmp r3, #2 800939c: d004 beq.n 80093a8 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800939e: 687b ldr r3, [r7, #4] 80093a0: 2280 movs r2, #128 @ 0x80 80093a2: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 80093a4: 2301 movs r3, #1 80093a6: e22c b.n 8009802 } else { if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80093a8: 687b ldr r3, [r7, #4] 80093aa: 681b ldr r3, [r3, #0] 80093ac: 4a5c ldr r2, [pc, #368] @ (8009520 ) 80093ae: 4293 cmp r3, r2 80093b0: d04a beq.n 8009448 80093b2: 687b ldr r3, [r7, #4] 80093b4: 681b ldr r3, [r3, #0] 80093b6: 4a5b ldr r2, [pc, #364] @ (8009524 ) 80093b8: 4293 cmp r3, r2 80093ba: d045 beq.n 8009448 80093bc: 687b ldr r3, [r7, #4] 80093be: 681b ldr r3, [r3, #0] 80093c0: 4a59 ldr r2, [pc, #356] @ (8009528 ) 80093c2: 4293 cmp r3, r2 80093c4: d040 beq.n 8009448 80093c6: 687b ldr r3, [r7, #4] 80093c8: 681b ldr r3, [r3, #0] 80093ca: 4a58 ldr r2, [pc, #352] @ (800952c ) 80093cc: 4293 cmp r3, r2 80093ce: d03b beq.n 8009448 80093d0: 687b ldr r3, [r7, #4] 80093d2: 681b ldr r3, [r3, #0] 80093d4: 4a56 ldr r2, [pc, #344] @ (8009530 ) 80093d6: 4293 cmp r3, r2 80093d8: d036 beq.n 8009448 80093da: 687b ldr r3, [r7, #4] 80093dc: 681b ldr r3, [r3, #0] 80093de: 4a55 ldr r2, [pc, #340] @ (8009534 ) 80093e0: 4293 cmp r3, r2 80093e2: d031 beq.n 8009448 80093e4: 687b ldr r3, [r7, #4] 80093e6: 681b ldr r3, [r3, #0] 80093e8: 4a53 ldr r2, [pc, #332] @ (8009538 ) 80093ea: 4293 cmp r3, r2 80093ec: d02c beq.n 8009448 80093ee: 687b ldr r3, [r7, #4] 80093f0: 681b ldr r3, [r3, #0] 80093f2: 4a52 ldr r2, [pc, #328] @ (800953c ) 80093f4: 4293 cmp r3, r2 80093f6: d027 beq.n 8009448 80093f8: 687b ldr r3, [r7, #4] 80093fa: 681b ldr r3, [r3, #0] 80093fc: 4a50 ldr r2, [pc, #320] @ (8009540 ) 80093fe: 4293 cmp r3, r2 8009400: d022 beq.n 8009448 8009402: 687b ldr r3, [r7, #4] 8009404: 681b ldr r3, [r3, #0] 8009406: 4a4f ldr r2, [pc, #316] @ (8009544 ) 8009408: 4293 cmp r3, r2 800940a: d01d beq.n 8009448 800940c: 687b ldr r3, [r7, #4] 800940e: 681b ldr r3, [r3, #0] 8009410: 4a4d ldr r2, [pc, #308] @ (8009548 ) 8009412: 4293 cmp r3, r2 8009414: d018 beq.n 8009448 8009416: 687b ldr r3, [r7, #4] 8009418: 681b ldr r3, [r3, #0] 800941a: 4a4c ldr r2, [pc, #304] @ (800954c ) 800941c: 4293 cmp r3, r2 800941e: d013 beq.n 8009448 8009420: 687b ldr r3, [r7, #4] 8009422: 681b ldr r3, [r3, #0] 8009424: 4a4a ldr r2, [pc, #296] @ (8009550 ) 8009426: 4293 cmp r3, r2 8009428: d00e beq.n 8009448 800942a: 687b ldr r3, [r7, #4] 800942c: 681b ldr r3, [r3, #0] 800942e: 4a49 ldr r2, [pc, #292] @ (8009554 ) 8009430: 4293 cmp r3, r2 8009432: d009 beq.n 8009448 8009434: 687b ldr r3, [r7, #4] 8009436: 681b ldr r3, [r3, #0] 8009438: 4a47 ldr r2, [pc, #284] @ (8009558 ) 800943a: 4293 cmp r3, r2 800943c: d004 beq.n 8009448 800943e: 687b ldr r3, [r7, #4] 8009440: 681b ldr r3, [r3, #0] 8009442: 4a46 ldr r2, [pc, #280] @ (800955c ) 8009444: 4293 cmp r3, r2 8009446: d101 bne.n 800944c 8009448: 2301 movs r3, #1 800944a: e000 b.n 800944e 800944c: 2300 movs r3, #0 800944e: 2b00 cmp r3, #0 8009450: f000 8086 beq.w 8009560 { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 8009454: 687b ldr r3, [r7, #4] 8009456: 2204 movs r2, #4 8009458: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800945c: 687b ldr r3, [r7, #4] 800945e: 681b ldr r3, [r3, #0] 8009460: 4a2f ldr r2, [pc, #188] @ (8009520 ) 8009462: 4293 cmp r3, r2 8009464: d04a beq.n 80094fc 8009466: 687b ldr r3, [r7, #4] 8009468: 681b ldr r3, [r3, #0] 800946a: 4a2e ldr r2, [pc, #184] @ (8009524 ) 800946c: 4293 cmp r3, r2 800946e: d045 beq.n 80094fc 8009470: 687b ldr r3, [r7, #4] 8009472: 681b ldr r3, [r3, #0] 8009474: 4a2c ldr r2, [pc, #176] @ (8009528 ) 8009476: 4293 cmp r3, r2 8009478: d040 beq.n 80094fc 800947a: 687b ldr r3, [r7, #4] 800947c: 681b ldr r3, [r3, #0] 800947e: 4a2b ldr r2, [pc, #172] @ (800952c ) 8009480: 4293 cmp r3, r2 8009482: d03b beq.n 80094fc 8009484: 687b ldr r3, [r7, #4] 8009486: 681b ldr r3, [r3, #0] 8009488: 4a29 ldr r2, [pc, #164] @ (8009530 ) 800948a: 4293 cmp r3, r2 800948c: d036 beq.n 80094fc 800948e: 687b ldr r3, [r7, #4] 8009490: 681b ldr r3, [r3, #0] 8009492: 4a28 ldr r2, [pc, #160] @ (8009534 ) 8009494: 4293 cmp r3, r2 8009496: d031 beq.n 80094fc 8009498: 687b ldr r3, [r7, #4] 800949a: 681b ldr r3, [r3, #0] 800949c: 4a26 ldr r2, [pc, #152] @ (8009538 ) 800949e: 4293 cmp r3, r2 80094a0: d02c beq.n 80094fc 80094a2: 687b ldr r3, [r7, #4] 80094a4: 681b ldr r3, [r3, #0] 80094a6: 4a25 ldr r2, [pc, #148] @ (800953c ) 80094a8: 4293 cmp r3, r2 80094aa: d027 beq.n 80094fc 80094ac: 687b ldr r3, [r7, #4] 80094ae: 681b ldr r3, [r3, #0] 80094b0: 4a23 ldr r2, [pc, #140] @ (8009540 ) 80094b2: 4293 cmp r3, r2 80094b4: d022 beq.n 80094fc 80094b6: 687b ldr r3, [r7, #4] 80094b8: 681b ldr r3, [r3, #0] 80094ba: 4a22 ldr r2, [pc, #136] @ (8009544 ) 80094bc: 4293 cmp r3, r2 80094be: d01d beq.n 80094fc 80094c0: 687b ldr r3, [r7, #4] 80094c2: 681b ldr r3, [r3, #0] 80094c4: 4a20 ldr r2, [pc, #128] @ (8009548 ) 80094c6: 4293 cmp r3, r2 80094c8: d018 beq.n 80094fc 80094ca: 687b ldr r3, [r7, #4] 80094cc: 681b ldr r3, [r3, #0] 80094ce: 4a1f ldr r2, [pc, #124] @ (800954c ) 80094d0: 4293 cmp r3, r2 80094d2: d013 beq.n 80094fc 80094d4: 687b ldr r3, [r7, #4] 80094d6: 681b ldr r3, [r3, #0] 80094d8: 4a1d ldr r2, [pc, #116] @ (8009550 ) 80094da: 4293 cmp r3, r2 80094dc: d00e beq.n 80094fc 80094de: 687b ldr r3, [r7, #4] 80094e0: 681b ldr r3, [r3, #0] 80094e2: 4a1c ldr r2, [pc, #112] @ (8009554 ) 80094e4: 4293 cmp r3, r2 80094e6: d009 beq.n 80094fc 80094e8: 687b ldr r3, [r7, #4] 80094ea: 681b ldr r3, [r3, #0] 80094ec: 4a1a ldr r2, [pc, #104] @ (8009558 ) 80094ee: 4293 cmp r3, r2 80094f0: d004 beq.n 80094fc 80094f2: 687b ldr r3, [r7, #4] 80094f4: 681b ldr r3, [r3, #0] 80094f6: 4a19 ldr r2, [pc, #100] @ (800955c ) 80094f8: 4293 cmp r3, r2 80094fa: d108 bne.n 800950e 80094fc: 687b ldr r3, [r7, #4] 80094fe: 681b ldr r3, [r3, #0] 8009500: 681a ldr r2, [r3, #0] 8009502: 687b ldr r3, [r7, #4] 8009504: 681b ldr r3, [r3, #0] 8009506: f022 0201 bic.w r2, r2, #1 800950a: 601a str r2, [r3, #0] 800950c: e178 b.n 8009800 800950e: 687b ldr r3, [r7, #4] 8009510: 681b ldr r3, [r3, #0] 8009512: 681a ldr r2, [r3, #0] 8009514: 687b ldr r3, [r7, #4] 8009516: 681b ldr r3, [r3, #0] 8009518: f022 0201 bic.w r2, r2, #1 800951c: 601a str r2, [r3, #0] 800951e: e16f b.n 8009800 8009520: 40020010 .word 0x40020010 8009524: 40020028 .word 0x40020028 8009528: 40020040 .word 0x40020040 800952c: 40020058 .word 0x40020058 8009530: 40020070 .word 0x40020070 8009534: 40020088 .word 0x40020088 8009538: 400200a0 .word 0x400200a0 800953c: 400200b8 .word 0x400200b8 8009540: 40020410 .word 0x40020410 8009544: 40020428 .word 0x40020428 8009548: 40020440 .word 0x40020440 800954c: 40020458 .word 0x40020458 8009550: 40020470 .word 0x40020470 8009554: 40020488 .word 0x40020488 8009558: 400204a0 .word 0x400204a0 800955c: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 8009560: 687b ldr r3, [r7, #4] 8009562: 681b ldr r3, [r3, #0] 8009564: 681a ldr r2, [r3, #0] 8009566: 687b ldr r3, [r7, #4] 8009568: 681b ldr r3, [r3, #0] 800956a: f022 020e bic.w r2, r2, #14 800956e: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8009570: 687b ldr r3, [r7, #4] 8009572: 681b ldr r3, [r3, #0] 8009574: 4a6c ldr r2, [pc, #432] @ (8009728 ) 8009576: 4293 cmp r3, r2 8009578: d04a beq.n 8009610 800957a: 687b ldr r3, [r7, #4] 800957c: 681b ldr r3, [r3, #0] 800957e: 4a6b ldr r2, [pc, #428] @ (800972c ) 8009580: 4293 cmp r3, r2 8009582: d045 beq.n 8009610 8009584: 687b ldr r3, [r7, #4] 8009586: 681b ldr r3, [r3, #0] 8009588: 4a69 ldr r2, [pc, #420] @ (8009730 ) 800958a: 4293 cmp r3, r2 800958c: d040 beq.n 8009610 800958e: 687b ldr r3, [r7, #4] 8009590: 681b ldr r3, [r3, #0] 8009592: 4a68 ldr r2, [pc, #416] @ (8009734 ) 8009594: 4293 cmp r3, r2 8009596: d03b beq.n 8009610 8009598: 687b ldr r3, [r7, #4] 800959a: 681b ldr r3, [r3, #0] 800959c: 4a66 ldr r2, [pc, #408] @ (8009738 ) 800959e: 4293 cmp r3, r2 80095a0: d036 beq.n 8009610 80095a2: 687b ldr r3, [r7, #4] 80095a4: 681b ldr r3, [r3, #0] 80095a6: 4a65 ldr r2, [pc, #404] @ (800973c ) 80095a8: 4293 cmp r3, r2 80095aa: d031 beq.n 8009610 80095ac: 687b ldr r3, [r7, #4] 80095ae: 681b ldr r3, [r3, #0] 80095b0: 4a63 ldr r2, [pc, #396] @ (8009740 ) 80095b2: 4293 cmp r3, r2 80095b4: d02c beq.n 8009610 80095b6: 687b ldr r3, [r7, #4] 80095b8: 681b ldr r3, [r3, #0] 80095ba: 4a62 ldr r2, [pc, #392] @ (8009744 ) 80095bc: 4293 cmp r3, r2 80095be: d027 beq.n 8009610 80095c0: 687b ldr r3, [r7, #4] 80095c2: 681b ldr r3, [r3, #0] 80095c4: 4a60 ldr r2, [pc, #384] @ (8009748 ) 80095c6: 4293 cmp r3, r2 80095c8: d022 beq.n 8009610 80095ca: 687b ldr r3, [r7, #4] 80095cc: 681b ldr r3, [r3, #0] 80095ce: 4a5f ldr r2, [pc, #380] @ (800974c ) 80095d0: 4293 cmp r3, r2 80095d2: d01d beq.n 8009610 80095d4: 687b ldr r3, [r7, #4] 80095d6: 681b ldr r3, [r3, #0] 80095d8: 4a5d ldr r2, [pc, #372] @ (8009750 ) 80095da: 4293 cmp r3, r2 80095dc: d018 beq.n 8009610 80095de: 687b ldr r3, [r7, #4] 80095e0: 681b ldr r3, [r3, #0] 80095e2: 4a5c ldr r2, [pc, #368] @ (8009754 ) 80095e4: 4293 cmp r3, r2 80095e6: d013 beq.n 8009610 80095e8: 687b ldr r3, [r7, #4] 80095ea: 681b ldr r3, [r3, #0] 80095ec: 4a5a ldr r2, [pc, #360] @ (8009758 ) 80095ee: 4293 cmp r3, r2 80095f0: d00e beq.n 8009610 80095f2: 687b ldr r3, [r7, #4] 80095f4: 681b ldr r3, [r3, #0] 80095f6: 4a59 ldr r2, [pc, #356] @ (800975c ) 80095f8: 4293 cmp r3, r2 80095fa: d009 beq.n 8009610 80095fc: 687b ldr r3, [r7, #4] 80095fe: 681b ldr r3, [r3, #0] 8009600: 4a57 ldr r2, [pc, #348] @ (8009760 ) 8009602: 4293 cmp r3, r2 8009604: d004 beq.n 8009610 8009606: 687b ldr r3, [r7, #4] 8009608: 681b ldr r3, [r3, #0] 800960a: 4a56 ldr r2, [pc, #344] @ (8009764 ) 800960c: 4293 cmp r3, r2 800960e: d108 bne.n 8009622 8009610: 687b ldr r3, [r7, #4] 8009612: 681b ldr r3, [r3, #0] 8009614: 681a ldr r2, [r3, #0] 8009616: 687b ldr r3, [r7, #4] 8009618: 681b ldr r3, [r3, #0] 800961a: f022 0201 bic.w r2, r2, #1 800961e: 601a str r2, [r3, #0] 8009620: e007 b.n 8009632 8009622: 687b ldr r3, [r7, #4] 8009624: 681b ldr r3, [r3, #0] 8009626: 681a ldr r2, [r3, #0] 8009628: 687b ldr r3, [r7, #4] 800962a: 681b ldr r3, [r3, #0] 800962c: f022 0201 bic.w r2, r2, #1 8009630: 601a str r2, [r3, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8009632: 687b ldr r3, [r7, #4] 8009634: 681b ldr r3, [r3, #0] 8009636: 4a3c ldr r2, [pc, #240] @ (8009728 ) 8009638: 4293 cmp r3, r2 800963a: d072 beq.n 8009722 800963c: 687b ldr r3, [r7, #4] 800963e: 681b ldr r3, [r3, #0] 8009640: 4a3a ldr r2, [pc, #232] @ (800972c ) 8009642: 4293 cmp r3, r2 8009644: d06d beq.n 8009722 8009646: 687b ldr r3, [r7, #4] 8009648: 681b ldr r3, [r3, #0] 800964a: 4a39 ldr r2, [pc, #228] @ (8009730 ) 800964c: 4293 cmp r3, r2 800964e: d068 beq.n 8009722 8009650: 687b ldr r3, [r7, #4] 8009652: 681b ldr r3, [r3, #0] 8009654: 4a37 ldr r2, [pc, #220] @ (8009734 ) 8009656: 4293 cmp r3, r2 8009658: d063 beq.n 8009722 800965a: 687b ldr r3, [r7, #4] 800965c: 681b ldr r3, [r3, #0] 800965e: 4a36 ldr r2, [pc, #216] @ (8009738 ) 8009660: 4293 cmp r3, r2 8009662: d05e beq.n 8009722 8009664: 687b ldr r3, [r7, #4] 8009666: 681b ldr r3, [r3, #0] 8009668: 4a34 ldr r2, [pc, #208] @ (800973c ) 800966a: 4293 cmp r3, r2 800966c: d059 beq.n 8009722 800966e: 687b ldr r3, [r7, #4] 8009670: 681b ldr r3, [r3, #0] 8009672: 4a33 ldr r2, [pc, #204] @ (8009740 ) 8009674: 4293 cmp r3, r2 8009676: d054 beq.n 8009722 8009678: 687b ldr r3, [r7, #4] 800967a: 681b ldr r3, [r3, #0] 800967c: 4a31 ldr r2, [pc, #196] @ (8009744 ) 800967e: 4293 cmp r3, r2 8009680: d04f beq.n 8009722 8009682: 687b ldr r3, [r7, #4] 8009684: 681b ldr r3, [r3, #0] 8009686: 4a30 ldr r2, [pc, #192] @ (8009748 ) 8009688: 4293 cmp r3, r2 800968a: d04a beq.n 8009722 800968c: 687b ldr r3, [r7, #4] 800968e: 681b ldr r3, [r3, #0] 8009690: 4a2e ldr r2, [pc, #184] @ (800974c ) 8009692: 4293 cmp r3, r2 8009694: d045 beq.n 8009722 8009696: 687b ldr r3, [r7, #4] 8009698: 681b ldr r3, [r3, #0] 800969a: 4a2d ldr r2, [pc, #180] @ (8009750 ) 800969c: 4293 cmp r3, r2 800969e: d040 beq.n 8009722 80096a0: 687b ldr r3, [r7, #4] 80096a2: 681b ldr r3, [r3, #0] 80096a4: 4a2b ldr r2, [pc, #172] @ (8009754 ) 80096a6: 4293 cmp r3, r2 80096a8: d03b beq.n 8009722 80096aa: 687b ldr r3, [r7, #4] 80096ac: 681b ldr r3, [r3, #0] 80096ae: 4a2a ldr r2, [pc, #168] @ (8009758 ) 80096b0: 4293 cmp r3, r2 80096b2: d036 beq.n 8009722 80096b4: 687b ldr r3, [r7, #4] 80096b6: 681b ldr r3, [r3, #0] 80096b8: 4a28 ldr r2, [pc, #160] @ (800975c ) 80096ba: 4293 cmp r3, r2 80096bc: d031 beq.n 8009722 80096be: 687b ldr r3, [r7, #4] 80096c0: 681b ldr r3, [r3, #0] 80096c2: 4a27 ldr r2, [pc, #156] @ (8009760 ) 80096c4: 4293 cmp r3, r2 80096c6: d02c beq.n 8009722 80096c8: 687b ldr r3, [r7, #4] 80096ca: 681b ldr r3, [r3, #0] 80096cc: 4a25 ldr r2, [pc, #148] @ (8009764 ) 80096ce: 4293 cmp r3, r2 80096d0: d027 beq.n 8009722 80096d2: 687b ldr r3, [r7, #4] 80096d4: 681b ldr r3, [r3, #0] 80096d6: 4a24 ldr r2, [pc, #144] @ (8009768 ) 80096d8: 4293 cmp r3, r2 80096da: d022 beq.n 8009722 80096dc: 687b ldr r3, [r7, #4] 80096de: 681b ldr r3, [r3, #0] 80096e0: 4a22 ldr r2, [pc, #136] @ (800976c ) 80096e2: 4293 cmp r3, r2 80096e4: d01d beq.n 8009722 80096e6: 687b ldr r3, [r7, #4] 80096e8: 681b ldr r3, [r3, #0] 80096ea: 4a21 ldr r2, [pc, #132] @ (8009770 ) 80096ec: 4293 cmp r3, r2 80096ee: d018 beq.n 8009722 80096f0: 687b ldr r3, [r7, #4] 80096f2: 681b ldr r3, [r3, #0] 80096f4: 4a1f ldr r2, [pc, #124] @ (8009774 ) 80096f6: 4293 cmp r3, r2 80096f8: d013 beq.n 8009722 80096fa: 687b ldr r3, [r7, #4] 80096fc: 681b ldr r3, [r3, #0] 80096fe: 4a1e ldr r2, [pc, #120] @ (8009778 ) 8009700: 4293 cmp r3, r2 8009702: d00e beq.n 8009722 8009704: 687b ldr r3, [r7, #4] 8009706: 681b ldr r3, [r3, #0] 8009708: 4a1c ldr r2, [pc, #112] @ (800977c ) 800970a: 4293 cmp r3, r2 800970c: d009 beq.n 8009722 800970e: 687b ldr r3, [r7, #4] 8009710: 681b ldr r3, [r3, #0] 8009712: 4a1b ldr r2, [pc, #108] @ (8009780 ) 8009714: 4293 cmp r3, r2 8009716: d004 beq.n 8009722 8009718: 687b ldr r3, [r7, #4] 800971a: 681b ldr r3, [r3, #0] 800971c: 4a19 ldr r2, [pc, #100] @ (8009784 ) 800971e: 4293 cmp r3, r2 8009720: d132 bne.n 8009788 8009722: 2301 movs r3, #1 8009724: e031 b.n 800978a 8009726: bf00 nop 8009728: 40020010 .word 0x40020010 800972c: 40020028 .word 0x40020028 8009730: 40020040 .word 0x40020040 8009734: 40020058 .word 0x40020058 8009738: 40020070 .word 0x40020070 800973c: 40020088 .word 0x40020088 8009740: 400200a0 .word 0x400200a0 8009744: 400200b8 .word 0x400200b8 8009748: 40020410 .word 0x40020410 800974c: 40020428 .word 0x40020428 8009750: 40020440 .word 0x40020440 8009754: 40020458 .word 0x40020458 8009758: 40020470 .word 0x40020470 800975c: 40020488 .word 0x40020488 8009760: 400204a0 .word 0x400204a0 8009764: 400204b8 .word 0x400204b8 8009768: 58025408 .word 0x58025408 800976c: 5802541c .word 0x5802541c 8009770: 58025430 .word 0x58025430 8009774: 58025444 .word 0x58025444 8009778: 58025458 .word 0x58025458 800977c: 5802546c .word 0x5802546c 8009780: 58025480 .word 0x58025480 8009784: 58025494 .word 0x58025494 8009788: 2300 movs r3, #0 800978a: 2b00 cmp r3, #0 800978c: d028 beq.n 80097e0 { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 800978e: 687b ldr r3, [r7, #4] 8009790: 6e1b ldr r3, [r3, #96] @ 0x60 8009792: 681a ldr r2, [r3, #0] 8009794: 687b ldr r3, [r7, #4] 8009796: 6e1b ldr r3, [r3, #96] @ 0x60 8009798: f422 7280 bic.w r2, r2, #256 @ 0x100 800979c: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 800979e: 687b ldr r3, [r7, #4] 80097a0: 6d9b ldr r3, [r3, #88] @ 0x58 80097a2: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 80097a4: 687b ldr r3, [r7, #4] 80097a6: 6ddb ldr r3, [r3, #92] @ 0x5c 80097a8: f003 031f and.w r3, r3, #31 80097ac: 2201 movs r2, #1 80097ae: 409a lsls r2, r3 80097b0: 68fb ldr r3, [r7, #12] 80097b2: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 80097b4: 687b ldr r3, [r7, #4] 80097b6: 6e5b ldr r3, [r3, #100] @ 0x64 80097b8: 687a ldr r2, [r7, #4] 80097ba: 6e92 ldr r2, [r2, #104] @ 0x68 80097bc: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 80097be: 687b ldr r3, [r7, #4] 80097c0: 6edb ldr r3, [r3, #108] @ 0x6c 80097c2: 2b00 cmp r3, #0 80097c4: d00c beq.n 80097e0 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 80097c6: 687b ldr r3, [r7, #4] 80097c8: 6edb ldr r3, [r3, #108] @ 0x6c 80097ca: 681a ldr r2, [r3, #0] 80097cc: 687b ldr r3, [r7, #4] 80097ce: 6edb ldr r3, [r3, #108] @ 0x6c 80097d0: f422 7280 bic.w r2, r2, #256 @ 0x100 80097d4: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 80097d6: 687b ldr r3, [r7, #4] 80097d8: 6f1b ldr r3, [r3, #112] @ 0x70 80097da: 687a ldr r2, [r7, #4] 80097dc: 6f52 ldr r2, [r2, #116] @ 0x74 80097de: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80097e0: 687b ldr r3, [r7, #4] 80097e2: 2201 movs r2, #1 80097e4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80097e8: 687b ldr r3, [r7, #4] 80097ea: 2200 movs r2, #0 80097ec: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 80097f0: 687b ldr r3, [r7, #4] 80097f2: 6d1b ldr r3, [r3, #80] @ 0x50 80097f4: 2b00 cmp r3, #0 80097f6: d003 beq.n 8009800 { hdma->XferAbortCallback(hdma); 80097f8: 687b ldr r3, [r7, #4] 80097fa: 6d1b ldr r3, [r3, #80] @ 0x50 80097fc: 6878 ldr r0, [r7, #4] 80097fe: 4798 blx r3 } } } return HAL_OK; 8009800: 2300 movs r3, #0 } 8009802: 4618 mov r0, r3 8009804: 3710 adds r7, #16 8009806: 46bd mov sp, r7 8009808: bd80 pop {r7, pc} 800980a: bf00 nop 0800980c : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 800980c: b580 push {r7, lr} 800980e: b08a sub sp, #40 @ 0x28 8009810: af00 add r7, sp, #0 8009812: 6078 str r0, [r7, #4] uint32_t tmpisr_dma, tmpisr_bdma; uint32_t ccr_reg; __IO uint32_t count = 0U; 8009814: 2300 movs r3, #0 8009816: 60fb str r3, [r7, #12] uint32_t timeout = SystemCoreClock / 9600U; 8009818: 4b67 ldr r3, [pc, #412] @ (80099b8 ) 800981a: 681b ldr r3, [r3, #0] 800981c: 4a67 ldr r2, [pc, #412] @ (80099bc ) 800981e: fba2 2303 umull r2, r3, r2, r3 8009822: 0a9b lsrs r3, r3, #10 8009824: 627b str r3, [r7, #36] @ 0x24 /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8009826: 687b ldr r3, [r7, #4] 8009828: 6d9b ldr r3, [r3, #88] @ 0x58 800982a: 623b str r3, [r7, #32] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 800982c: 687b ldr r3, [r7, #4] 800982e: 6d9b ldr r3, [r3, #88] @ 0x58 8009830: 61fb str r3, [r7, #28] tmpisr_dma = regs_dma->ISR; 8009832: 6a3b ldr r3, [r7, #32] 8009834: 681b ldr r3, [r3, #0] 8009836: 61bb str r3, [r7, #24] tmpisr_bdma = regs_bdma->ISR; 8009838: 69fb ldr r3, [r7, #28] 800983a: 681b ldr r3, [r3, #0] 800983c: 617b str r3, [r7, #20] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800983e: 687b ldr r3, [r7, #4] 8009840: 681b ldr r3, [r3, #0] 8009842: 4a5f ldr r2, [pc, #380] @ (80099c0 ) 8009844: 4293 cmp r3, r2 8009846: d04a beq.n 80098de 8009848: 687b ldr r3, [r7, #4] 800984a: 681b ldr r3, [r3, #0] 800984c: 4a5d ldr r2, [pc, #372] @ (80099c4 ) 800984e: 4293 cmp r3, r2 8009850: d045 beq.n 80098de 8009852: 687b ldr r3, [r7, #4] 8009854: 681b ldr r3, [r3, #0] 8009856: 4a5c ldr r2, [pc, #368] @ (80099c8 ) 8009858: 4293 cmp r3, r2 800985a: d040 beq.n 80098de 800985c: 687b ldr r3, [r7, #4] 800985e: 681b ldr r3, [r3, #0] 8009860: 4a5a ldr r2, [pc, #360] @ (80099cc ) 8009862: 4293 cmp r3, r2 8009864: d03b beq.n 80098de 8009866: 687b ldr r3, [r7, #4] 8009868: 681b ldr r3, [r3, #0] 800986a: 4a59 ldr r2, [pc, #356] @ (80099d0 ) 800986c: 4293 cmp r3, r2 800986e: d036 beq.n 80098de 8009870: 687b ldr r3, [r7, #4] 8009872: 681b ldr r3, [r3, #0] 8009874: 4a57 ldr r2, [pc, #348] @ (80099d4 ) 8009876: 4293 cmp r3, r2 8009878: d031 beq.n 80098de 800987a: 687b ldr r3, [r7, #4] 800987c: 681b ldr r3, [r3, #0] 800987e: 4a56 ldr r2, [pc, #344] @ (80099d8 ) 8009880: 4293 cmp r3, r2 8009882: d02c beq.n 80098de 8009884: 687b ldr r3, [r7, #4] 8009886: 681b ldr r3, [r3, #0] 8009888: 4a54 ldr r2, [pc, #336] @ (80099dc ) 800988a: 4293 cmp r3, r2 800988c: d027 beq.n 80098de 800988e: 687b ldr r3, [r7, #4] 8009890: 681b ldr r3, [r3, #0] 8009892: 4a53 ldr r2, [pc, #332] @ (80099e0 ) 8009894: 4293 cmp r3, r2 8009896: d022 beq.n 80098de 8009898: 687b ldr r3, [r7, #4] 800989a: 681b ldr r3, [r3, #0] 800989c: 4a51 ldr r2, [pc, #324] @ (80099e4 ) 800989e: 4293 cmp r3, r2 80098a0: d01d beq.n 80098de 80098a2: 687b ldr r3, [r7, #4] 80098a4: 681b ldr r3, [r3, #0] 80098a6: 4a50 ldr r2, [pc, #320] @ (80099e8 ) 80098a8: 4293 cmp r3, r2 80098aa: d018 beq.n 80098de 80098ac: 687b ldr r3, [r7, #4] 80098ae: 681b ldr r3, [r3, #0] 80098b0: 4a4e ldr r2, [pc, #312] @ (80099ec ) 80098b2: 4293 cmp r3, r2 80098b4: d013 beq.n 80098de 80098b6: 687b ldr r3, [r7, #4] 80098b8: 681b ldr r3, [r3, #0] 80098ba: 4a4d ldr r2, [pc, #308] @ (80099f0 ) 80098bc: 4293 cmp r3, r2 80098be: d00e beq.n 80098de 80098c0: 687b ldr r3, [r7, #4] 80098c2: 681b ldr r3, [r3, #0] 80098c4: 4a4b ldr r2, [pc, #300] @ (80099f4 ) 80098c6: 4293 cmp r3, r2 80098c8: d009 beq.n 80098de 80098ca: 687b ldr r3, [r7, #4] 80098cc: 681b ldr r3, [r3, #0] 80098ce: 4a4a ldr r2, [pc, #296] @ (80099f8 ) 80098d0: 4293 cmp r3, r2 80098d2: d004 beq.n 80098de 80098d4: 687b ldr r3, [r7, #4] 80098d6: 681b ldr r3, [r3, #0] 80098d8: 4a48 ldr r2, [pc, #288] @ (80099fc ) 80098da: 4293 cmp r3, r2 80098dc: d101 bne.n 80098e2 80098de: 2301 movs r3, #1 80098e0: e000 b.n 80098e4 80098e2: 2300 movs r3, #0 80098e4: 2b00 cmp r3, #0 80098e6: f000 842b beq.w 800a140 { /* Transfer Error Interrupt management ***************************************/ if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 80098ea: 687b ldr r3, [r7, #4] 80098ec: 6ddb ldr r3, [r3, #92] @ 0x5c 80098ee: f003 031f and.w r3, r3, #31 80098f2: 2208 movs r2, #8 80098f4: 409a lsls r2, r3 80098f6: 69bb ldr r3, [r7, #24] 80098f8: 4013 ands r3, r2 80098fa: 2b00 cmp r3, #0 80098fc: f000 80a2 beq.w 8009a44 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) 8009900: 687b ldr r3, [r7, #4] 8009902: 681b ldr r3, [r3, #0] 8009904: 4a2e ldr r2, [pc, #184] @ (80099c0 ) 8009906: 4293 cmp r3, r2 8009908: d04a beq.n 80099a0 800990a: 687b ldr r3, [r7, #4] 800990c: 681b ldr r3, [r3, #0] 800990e: 4a2d ldr r2, [pc, #180] @ (80099c4 ) 8009910: 4293 cmp r3, r2 8009912: d045 beq.n 80099a0 8009914: 687b ldr r3, [r7, #4] 8009916: 681b ldr r3, [r3, #0] 8009918: 4a2b ldr r2, [pc, #172] @ (80099c8 ) 800991a: 4293 cmp r3, r2 800991c: d040 beq.n 80099a0 800991e: 687b ldr r3, [r7, #4] 8009920: 681b ldr r3, [r3, #0] 8009922: 4a2a ldr r2, [pc, #168] @ (80099cc ) 8009924: 4293 cmp r3, r2 8009926: d03b beq.n 80099a0 8009928: 687b ldr r3, [r7, #4] 800992a: 681b ldr r3, [r3, #0] 800992c: 4a28 ldr r2, [pc, #160] @ (80099d0 ) 800992e: 4293 cmp r3, r2 8009930: d036 beq.n 80099a0 8009932: 687b ldr r3, [r7, #4] 8009934: 681b ldr r3, [r3, #0] 8009936: 4a27 ldr r2, [pc, #156] @ (80099d4 ) 8009938: 4293 cmp r3, r2 800993a: d031 beq.n 80099a0 800993c: 687b ldr r3, [r7, #4] 800993e: 681b ldr r3, [r3, #0] 8009940: 4a25 ldr r2, [pc, #148] @ (80099d8 ) 8009942: 4293 cmp r3, r2 8009944: d02c beq.n 80099a0 8009946: 687b ldr r3, [r7, #4] 8009948: 681b ldr r3, [r3, #0] 800994a: 4a24 ldr r2, [pc, #144] @ (80099dc ) 800994c: 4293 cmp r3, r2 800994e: d027 beq.n 80099a0 8009950: 687b ldr r3, [r7, #4] 8009952: 681b ldr r3, [r3, #0] 8009954: 4a22 ldr r2, [pc, #136] @ (80099e0 ) 8009956: 4293 cmp r3, r2 8009958: d022 beq.n 80099a0 800995a: 687b ldr r3, [r7, #4] 800995c: 681b ldr r3, [r3, #0] 800995e: 4a21 ldr r2, [pc, #132] @ (80099e4 ) 8009960: 4293 cmp r3, r2 8009962: d01d beq.n 80099a0 8009964: 687b ldr r3, [r7, #4] 8009966: 681b ldr r3, [r3, #0] 8009968: 4a1f ldr r2, [pc, #124] @ (80099e8 ) 800996a: 4293 cmp r3, r2 800996c: d018 beq.n 80099a0 800996e: 687b ldr r3, [r7, #4] 8009970: 681b ldr r3, [r3, #0] 8009972: 4a1e ldr r2, [pc, #120] @ (80099ec ) 8009974: 4293 cmp r3, r2 8009976: d013 beq.n 80099a0 8009978: 687b ldr r3, [r7, #4] 800997a: 681b ldr r3, [r3, #0] 800997c: 4a1c ldr r2, [pc, #112] @ (80099f0 ) 800997e: 4293 cmp r3, r2 8009980: d00e beq.n 80099a0 8009982: 687b ldr r3, [r7, #4] 8009984: 681b ldr r3, [r3, #0] 8009986: 4a1b ldr r2, [pc, #108] @ (80099f4 ) 8009988: 4293 cmp r3, r2 800998a: d009 beq.n 80099a0 800998c: 687b ldr r3, [r7, #4] 800998e: 681b ldr r3, [r3, #0] 8009990: 4a19 ldr r2, [pc, #100] @ (80099f8 ) 8009992: 4293 cmp r3, r2 8009994: d004 beq.n 80099a0 8009996: 687b ldr r3, [r7, #4] 8009998: 681b ldr r3, [r3, #0] 800999a: 4a18 ldr r2, [pc, #96] @ (80099fc ) 800999c: 4293 cmp r3, r2 800999e: d12f bne.n 8009a00 80099a0: 687b ldr r3, [r7, #4] 80099a2: 681b ldr r3, [r3, #0] 80099a4: 681b ldr r3, [r3, #0] 80099a6: f003 0304 and.w r3, r3, #4 80099aa: 2b00 cmp r3, #0 80099ac: bf14 ite ne 80099ae: 2301 movne r3, #1 80099b0: 2300 moveq r3, #0 80099b2: b2db uxtb r3, r3 80099b4: e02e b.n 8009a14 80099b6: bf00 nop 80099b8: 24000034 .word 0x24000034 80099bc: 1b4e81b5 .word 0x1b4e81b5 80099c0: 40020010 .word 0x40020010 80099c4: 40020028 .word 0x40020028 80099c8: 40020040 .word 0x40020040 80099cc: 40020058 .word 0x40020058 80099d0: 40020070 .word 0x40020070 80099d4: 40020088 .word 0x40020088 80099d8: 400200a0 .word 0x400200a0 80099dc: 400200b8 .word 0x400200b8 80099e0: 40020410 .word 0x40020410 80099e4: 40020428 .word 0x40020428 80099e8: 40020440 .word 0x40020440 80099ec: 40020458 .word 0x40020458 80099f0: 40020470 .word 0x40020470 80099f4: 40020488 .word 0x40020488 80099f8: 400204a0 .word 0x400204a0 80099fc: 400204b8 .word 0x400204b8 8009a00: 687b ldr r3, [r7, #4] 8009a02: 681b ldr r3, [r3, #0] 8009a04: 681b ldr r3, [r3, #0] 8009a06: f003 0308 and.w r3, r3, #8 8009a0a: 2b00 cmp r3, #0 8009a0c: bf14 ite ne 8009a0e: 2301 movne r3, #1 8009a10: 2300 moveq r3, #0 8009a12: b2db uxtb r3, r3 8009a14: 2b00 cmp r3, #0 8009a16: d015 beq.n 8009a44 { /* Disable the transfer error interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); 8009a18: 687b ldr r3, [r7, #4] 8009a1a: 681b ldr r3, [r3, #0] 8009a1c: 681a ldr r2, [r3, #0] 8009a1e: 687b ldr r3, [r7, #4] 8009a20: 681b ldr r3, [r3, #0] 8009a22: f022 0204 bic.w r2, r2, #4 8009a26: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009a28: 687b ldr r3, [r7, #4] 8009a2a: 6ddb ldr r3, [r3, #92] @ 0x5c 8009a2c: f003 031f and.w r3, r3, #31 8009a30: 2208 movs r2, #8 8009a32: 409a lsls r2, r3 8009a34: 6a3b ldr r3, [r7, #32] 8009a36: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 8009a38: 687b ldr r3, [r7, #4] 8009a3a: 6d5b ldr r3, [r3, #84] @ 0x54 8009a3c: f043 0201 orr.w r2, r3, #1 8009a40: 687b ldr r3, [r7, #4] 8009a42: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009a44: 687b ldr r3, [r7, #4] 8009a46: 6ddb ldr r3, [r3, #92] @ 0x5c 8009a48: f003 031f and.w r3, r3, #31 8009a4c: 69ba ldr r2, [r7, #24] 8009a4e: fa22 f303 lsr.w r3, r2, r3 8009a52: f003 0301 and.w r3, r3, #1 8009a56: 2b00 cmp r3, #0 8009a58: d06e beq.n 8009b38 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) 8009a5a: 687b ldr r3, [r7, #4] 8009a5c: 681b ldr r3, [r3, #0] 8009a5e: 4a69 ldr r2, [pc, #420] @ (8009c04 ) 8009a60: 4293 cmp r3, r2 8009a62: d04a beq.n 8009afa 8009a64: 687b ldr r3, [r7, #4] 8009a66: 681b ldr r3, [r3, #0] 8009a68: 4a67 ldr r2, [pc, #412] @ (8009c08 ) 8009a6a: 4293 cmp r3, r2 8009a6c: d045 beq.n 8009afa 8009a6e: 687b ldr r3, [r7, #4] 8009a70: 681b ldr r3, [r3, #0] 8009a72: 4a66 ldr r2, [pc, #408] @ (8009c0c ) 8009a74: 4293 cmp r3, r2 8009a76: d040 beq.n 8009afa 8009a78: 687b ldr r3, [r7, #4] 8009a7a: 681b ldr r3, [r3, #0] 8009a7c: 4a64 ldr r2, [pc, #400] @ (8009c10 ) 8009a7e: 4293 cmp r3, r2 8009a80: d03b beq.n 8009afa 8009a82: 687b ldr r3, [r7, #4] 8009a84: 681b ldr r3, [r3, #0] 8009a86: 4a63 ldr r2, [pc, #396] @ (8009c14 ) 8009a88: 4293 cmp r3, r2 8009a8a: d036 beq.n 8009afa 8009a8c: 687b ldr r3, [r7, #4] 8009a8e: 681b ldr r3, [r3, #0] 8009a90: 4a61 ldr r2, [pc, #388] @ (8009c18 ) 8009a92: 4293 cmp r3, r2 8009a94: d031 beq.n 8009afa 8009a96: 687b ldr r3, [r7, #4] 8009a98: 681b ldr r3, [r3, #0] 8009a9a: 4a60 ldr r2, [pc, #384] @ (8009c1c ) 8009a9c: 4293 cmp r3, r2 8009a9e: d02c beq.n 8009afa 8009aa0: 687b ldr r3, [r7, #4] 8009aa2: 681b ldr r3, [r3, #0] 8009aa4: 4a5e ldr r2, [pc, #376] @ (8009c20 ) 8009aa6: 4293 cmp r3, r2 8009aa8: d027 beq.n 8009afa 8009aaa: 687b ldr r3, [r7, #4] 8009aac: 681b ldr r3, [r3, #0] 8009aae: 4a5d ldr r2, [pc, #372] @ (8009c24 ) 8009ab0: 4293 cmp r3, r2 8009ab2: d022 beq.n 8009afa 8009ab4: 687b ldr r3, [r7, #4] 8009ab6: 681b ldr r3, [r3, #0] 8009ab8: 4a5b ldr r2, [pc, #364] @ (8009c28 ) 8009aba: 4293 cmp r3, r2 8009abc: d01d beq.n 8009afa 8009abe: 687b ldr r3, [r7, #4] 8009ac0: 681b ldr r3, [r3, #0] 8009ac2: 4a5a ldr r2, [pc, #360] @ (8009c2c ) 8009ac4: 4293 cmp r3, r2 8009ac6: d018 beq.n 8009afa 8009ac8: 687b ldr r3, [r7, #4] 8009aca: 681b ldr r3, [r3, #0] 8009acc: 4a58 ldr r2, [pc, #352] @ (8009c30 ) 8009ace: 4293 cmp r3, r2 8009ad0: d013 beq.n 8009afa 8009ad2: 687b ldr r3, [r7, #4] 8009ad4: 681b ldr r3, [r3, #0] 8009ad6: 4a57 ldr r2, [pc, #348] @ (8009c34 ) 8009ad8: 4293 cmp r3, r2 8009ada: d00e beq.n 8009afa 8009adc: 687b ldr r3, [r7, #4] 8009ade: 681b ldr r3, [r3, #0] 8009ae0: 4a55 ldr r2, [pc, #340] @ (8009c38 ) 8009ae2: 4293 cmp r3, r2 8009ae4: d009 beq.n 8009afa 8009ae6: 687b ldr r3, [r7, #4] 8009ae8: 681b ldr r3, [r3, #0] 8009aea: 4a54 ldr r2, [pc, #336] @ (8009c3c ) 8009aec: 4293 cmp r3, r2 8009aee: d004 beq.n 8009afa 8009af0: 687b ldr r3, [r7, #4] 8009af2: 681b ldr r3, [r3, #0] 8009af4: 4a52 ldr r2, [pc, #328] @ (8009c40 ) 8009af6: 4293 cmp r3, r2 8009af8: d10a bne.n 8009b10 8009afa: 687b ldr r3, [r7, #4] 8009afc: 681b ldr r3, [r3, #0] 8009afe: 695b ldr r3, [r3, #20] 8009b00: f003 0380 and.w r3, r3, #128 @ 0x80 8009b04: 2b00 cmp r3, #0 8009b06: bf14 ite ne 8009b08: 2301 movne r3, #1 8009b0a: 2300 moveq r3, #0 8009b0c: b2db uxtb r3, r3 8009b0e: e003 b.n 8009b18 8009b10: 687b ldr r3, [r7, #4] 8009b12: 681b ldr r3, [r3, #0] 8009b14: 681b ldr r3, [r3, #0] 8009b16: 2300 movs r3, #0 8009b18: 2b00 cmp r3, #0 8009b1a: d00d beq.n 8009b38 { /* Clear the FIFO error flag */ regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009b1c: 687b ldr r3, [r7, #4] 8009b1e: 6ddb ldr r3, [r3, #92] @ 0x5c 8009b20: f003 031f and.w r3, r3, #31 8009b24: 2201 movs r2, #1 8009b26: 409a lsls r2, r3 8009b28: 6a3b ldr r3, [r7, #32] 8009b2a: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 8009b2c: 687b ldr r3, [r7, #4] 8009b2e: 6d5b ldr r3, [r3, #84] @ 0x54 8009b30: f043 0202 orr.w r2, r3, #2 8009b34: 687b ldr r3, [r7, #4] 8009b36: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009b38: 687b ldr r3, [r7, #4] 8009b3a: 6ddb ldr r3, [r3, #92] @ 0x5c 8009b3c: f003 031f and.w r3, r3, #31 8009b40: 2204 movs r2, #4 8009b42: 409a lsls r2, r3 8009b44: 69bb ldr r3, [r7, #24] 8009b46: 4013 ands r3, r2 8009b48: 2b00 cmp r3, #0 8009b4a: f000 808f beq.w 8009c6c { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) 8009b4e: 687b ldr r3, [r7, #4] 8009b50: 681b ldr r3, [r3, #0] 8009b52: 4a2c ldr r2, [pc, #176] @ (8009c04 ) 8009b54: 4293 cmp r3, r2 8009b56: d04a beq.n 8009bee 8009b58: 687b ldr r3, [r7, #4] 8009b5a: 681b ldr r3, [r3, #0] 8009b5c: 4a2a ldr r2, [pc, #168] @ (8009c08 ) 8009b5e: 4293 cmp r3, r2 8009b60: d045 beq.n 8009bee 8009b62: 687b ldr r3, [r7, #4] 8009b64: 681b ldr r3, [r3, #0] 8009b66: 4a29 ldr r2, [pc, #164] @ (8009c0c ) 8009b68: 4293 cmp r3, r2 8009b6a: d040 beq.n 8009bee 8009b6c: 687b ldr r3, [r7, #4] 8009b6e: 681b ldr r3, [r3, #0] 8009b70: 4a27 ldr r2, [pc, #156] @ (8009c10 ) 8009b72: 4293 cmp r3, r2 8009b74: d03b beq.n 8009bee 8009b76: 687b ldr r3, [r7, #4] 8009b78: 681b ldr r3, [r3, #0] 8009b7a: 4a26 ldr r2, [pc, #152] @ (8009c14 ) 8009b7c: 4293 cmp r3, r2 8009b7e: d036 beq.n 8009bee 8009b80: 687b ldr r3, [r7, #4] 8009b82: 681b ldr r3, [r3, #0] 8009b84: 4a24 ldr r2, [pc, #144] @ (8009c18 ) 8009b86: 4293 cmp r3, r2 8009b88: d031 beq.n 8009bee 8009b8a: 687b ldr r3, [r7, #4] 8009b8c: 681b ldr r3, [r3, #0] 8009b8e: 4a23 ldr r2, [pc, #140] @ (8009c1c ) 8009b90: 4293 cmp r3, r2 8009b92: d02c beq.n 8009bee 8009b94: 687b ldr r3, [r7, #4] 8009b96: 681b ldr r3, [r3, #0] 8009b98: 4a21 ldr r2, [pc, #132] @ (8009c20 ) 8009b9a: 4293 cmp r3, r2 8009b9c: d027 beq.n 8009bee 8009b9e: 687b ldr r3, [r7, #4] 8009ba0: 681b ldr r3, [r3, #0] 8009ba2: 4a20 ldr r2, [pc, #128] @ (8009c24 ) 8009ba4: 4293 cmp r3, r2 8009ba6: d022 beq.n 8009bee 8009ba8: 687b ldr r3, [r7, #4] 8009baa: 681b ldr r3, [r3, #0] 8009bac: 4a1e ldr r2, [pc, #120] @ (8009c28 ) 8009bae: 4293 cmp r3, r2 8009bb0: d01d beq.n 8009bee 8009bb2: 687b ldr r3, [r7, #4] 8009bb4: 681b ldr r3, [r3, #0] 8009bb6: 4a1d ldr r2, [pc, #116] @ (8009c2c ) 8009bb8: 4293 cmp r3, r2 8009bba: d018 beq.n 8009bee 8009bbc: 687b ldr r3, [r7, #4] 8009bbe: 681b ldr r3, [r3, #0] 8009bc0: 4a1b ldr r2, [pc, #108] @ (8009c30 ) 8009bc2: 4293 cmp r3, r2 8009bc4: d013 beq.n 8009bee 8009bc6: 687b ldr r3, [r7, #4] 8009bc8: 681b ldr r3, [r3, #0] 8009bca: 4a1a ldr r2, [pc, #104] @ (8009c34 ) 8009bcc: 4293 cmp r3, r2 8009bce: d00e beq.n 8009bee 8009bd0: 687b ldr r3, [r7, #4] 8009bd2: 681b ldr r3, [r3, #0] 8009bd4: 4a18 ldr r2, [pc, #96] @ (8009c38 ) 8009bd6: 4293 cmp r3, r2 8009bd8: d009 beq.n 8009bee 8009bda: 687b ldr r3, [r7, #4] 8009bdc: 681b ldr r3, [r3, #0] 8009bde: 4a17 ldr r2, [pc, #92] @ (8009c3c ) 8009be0: 4293 cmp r3, r2 8009be2: d004 beq.n 8009bee 8009be4: 687b ldr r3, [r7, #4] 8009be6: 681b ldr r3, [r3, #0] 8009be8: 4a15 ldr r2, [pc, #84] @ (8009c40 ) 8009bea: 4293 cmp r3, r2 8009bec: d12a bne.n 8009c44 8009bee: 687b ldr r3, [r7, #4] 8009bf0: 681b ldr r3, [r3, #0] 8009bf2: 681b ldr r3, [r3, #0] 8009bf4: f003 0302 and.w r3, r3, #2 8009bf8: 2b00 cmp r3, #0 8009bfa: bf14 ite ne 8009bfc: 2301 movne r3, #1 8009bfe: 2300 moveq r3, #0 8009c00: b2db uxtb r3, r3 8009c02: e023 b.n 8009c4c 8009c04: 40020010 .word 0x40020010 8009c08: 40020028 .word 0x40020028 8009c0c: 40020040 .word 0x40020040 8009c10: 40020058 .word 0x40020058 8009c14: 40020070 .word 0x40020070 8009c18: 40020088 .word 0x40020088 8009c1c: 400200a0 .word 0x400200a0 8009c20: 400200b8 .word 0x400200b8 8009c24: 40020410 .word 0x40020410 8009c28: 40020428 .word 0x40020428 8009c2c: 40020440 .word 0x40020440 8009c30: 40020458 .word 0x40020458 8009c34: 40020470 .word 0x40020470 8009c38: 40020488 .word 0x40020488 8009c3c: 400204a0 .word 0x400204a0 8009c40: 400204b8 .word 0x400204b8 8009c44: 687b ldr r3, [r7, #4] 8009c46: 681b ldr r3, [r3, #0] 8009c48: 681b ldr r3, [r3, #0] 8009c4a: 2300 movs r3, #0 8009c4c: 2b00 cmp r3, #0 8009c4e: d00d beq.n 8009c6c { /* Clear the direct mode error flag */ regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009c50: 687b ldr r3, [r7, #4] 8009c52: 6ddb ldr r3, [r3, #92] @ 0x5c 8009c54: f003 031f and.w r3, r3, #31 8009c58: 2204 movs r2, #4 8009c5a: 409a lsls r2, r3 8009c5c: 6a3b ldr r3, [r7, #32] 8009c5e: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 8009c60: 687b ldr r3, [r7, #4] 8009c62: 6d5b ldr r3, [r3, #84] @ 0x54 8009c64: f043 0204 orr.w r2, r3, #4 8009c68: 687b ldr r3, [r7, #4] 8009c6a: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009c6c: 687b ldr r3, [r7, #4] 8009c6e: 6ddb ldr r3, [r3, #92] @ 0x5c 8009c70: f003 031f and.w r3, r3, #31 8009c74: 2210 movs r2, #16 8009c76: 409a lsls r2, r3 8009c78: 69bb ldr r3, [r7, #24] 8009c7a: 4013 ands r3, r2 8009c7c: 2b00 cmp r3, #0 8009c7e: f000 80a6 beq.w 8009dce { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) 8009c82: 687b ldr r3, [r7, #4] 8009c84: 681b ldr r3, [r3, #0] 8009c86: 4a85 ldr r2, [pc, #532] @ (8009e9c ) 8009c88: 4293 cmp r3, r2 8009c8a: d04a beq.n 8009d22 8009c8c: 687b ldr r3, [r7, #4] 8009c8e: 681b ldr r3, [r3, #0] 8009c90: 4a83 ldr r2, [pc, #524] @ (8009ea0 ) 8009c92: 4293 cmp r3, r2 8009c94: d045 beq.n 8009d22 8009c96: 687b ldr r3, [r7, #4] 8009c98: 681b ldr r3, [r3, #0] 8009c9a: 4a82 ldr r2, [pc, #520] @ (8009ea4 ) 8009c9c: 4293 cmp r3, r2 8009c9e: d040 beq.n 8009d22 8009ca0: 687b ldr r3, [r7, #4] 8009ca2: 681b ldr r3, [r3, #0] 8009ca4: 4a80 ldr r2, [pc, #512] @ (8009ea8 ) 8009ca6: 4293 cmp r3, r2 8009ca8: d03b beq.n 8009d22 8009caa: 687b ldr r3, [r7, #4] 8009cac: 681b ldr r3, [r3, #0] 8009cae: 4a7f ldr r2, [pc, #508] @ (8009eac ) 8009cb0: 4293 cmp r3, r2 8009cb2: d036 beq.n 8009d22 8009cb4: 687b ldr r3, [r7, #4] 8009cb6: 681b ldr r3, [r3, #0] 8009cb8: 4a7d ldr r2, [pc, #500] @ (8009eb0 ) 8009cba: 4293 cmp r3, r2 8009cbc: d031 beq.n 8009d22 8009cbe: 687b ldr r3, [r7, #4] 8009cc0: 681b ldr r3, [r3, #0] 8009cc2: 4a7c ldr r2, [pc, #496] @ (8009eb4 ) 8009cc4: 4293 cmp r3, r2 8009cc6: d02c beq.n 8009d22 8009cc8: 687b ldr r3, [r7, #4] 8009cca: 681b ldr r3, [r3, #0] 8009ccc: 4a7a ldr r2, [pc, #488] @ (8009eb8 ) 8009cce: 4293 cmp r3, r2 8009cd0: d027 beq.n 8009d22 8009cd2: 687b ldr r3, [r7, #4] 8009cd4: 681b ldr r3, [r3, #0] 8009cd6: 4a79 ldr r2, [pc, #484] @ (8009ebc ) 8009cd8: 4293 cmp r3, r2 8009cda: d022 beq.n 8009d22 8009cdc: 687b ldr r3, [r7, #4] 8009cde: 681b ldr r3, [r3, #0] 8009ce0: 4a77 ldr r2, [pc, #476] @ (8009ec0 ) 8009ce2: 4293 cmp r3, r2 8009ce4: d01d beq.n 8009d22 8009ce6: 687b ldr r3, [r7, #4] 8009ce8: 681b ldr r3, [r3, #0] 8009cea: 4a76 ldr r2, [pc, #472] @ (8009ec4 ) 8009cec: 4293 cmp r3, r2 8009cee: d018 beq.n 8009d22 8009cf0: 687b ldr r3, [r7, #4] 8009cf2: 681b ldr r3, [r3, #0] 8009cf4: 4a74 ldr r2, [pc, #464] @ (8009ec8 ) 8009cf6: 4293 cmp r3, r2 8009cf8: d013 beq.n 8009d22 8009cfa: 687b ldr r3, [r7, #4] 8009cfc: 681b ldr r3, [r3, #0] 8009cfe: 4a73 ldr r2, [pc, #460] @ (8009ecc ) 8009d00: 4293 cmp r3, r2 8009d02: d00e beq.n 8009d22 8009d04: 687b ldr r3, [r7, #4] 8009d06: 681b ldr r3, [r3, #0] 8009d08: 4a71 ldr r2, [pc, #452] @ (8009ed0 ) 8009d0a: 4293 cmp r3, r2 8009d0c: d009 beq.n 8009d22 8009d0e: 687b ldr r3, [r7, #4] 8009d10: 681b ldr r3, [r3, #0] 8009d12: 4a70 ldr r2, [pc, #448] @ (8009ed4 ) 8009d14: 4293 cmp r3, r2 8009d16: d004 beq.n 8009d22 8009d18: 687b ldr r3, [r7, #4] 8009d1a: 681b ldr r3, [r3, #0] 8009d1c: 4a6e ldr r2, [pc, #440] @ (8009ed8 ) 8009d1e: 4293 cmp r3, r2 8009d20: d10a bne.n 8009d38 8009d22: 687b ldr r3, [r7, #4] 8009d24: 681b ldr r3, [r3, #0] 8009d26: 681b ldr r3, [r3, #0] 8009d28: f003 0308 and.w r3, r3, #8 8009d2c: 2b00 cmp r3, #0 8009d2e: bf14 ite ne 8009d30: 2301 movne r3, #1 8009d32: 2300 moveq r3, #0 8009d34: b2db uxtb r3, r3 8009d36: e009 b.n 8009d4c 8009d38: 687b ldr r3, [r7, #4] 8009d3a: 681b ldr r3, [r3, #0] 8009d3c: 681b ldr r3, [r3, #0] 8009d3e: f003 0304 and.w r3, r3, #4 8009d42: 2b00 cmp r3, #0 8009d44: bf14 ite ne 8009d46: 2301 movne r3, #1 8009d48: 2300 moveq r3, #0 8009d4a: b2db uxtb r3, r3 8009d4c: 2b00 cmp r3, #0 8009d4e: d03e beq.n 8009dce { /* Clear the half transfer complete flag */ regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); 8009d50: 687b ldr r3, [r7, #4] 8009d52: 6ddb ldr r3, [r3, #92] @ 0x5c 8009d54: f003 031f and.w r3, r3, #31 8009d58: 2210 movs r2, #16 8009d5a: 409a lsls r2, r3 8009d5c: 6a3b ldr r3, [r7, #32] 8009d5e: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 8009d60: 687b ldr r3, [r7, #4] 8009d62: 681b ldr r3, [r3, #0] 8009d64: 681b ldr r3, [r3, #0] 8009d66: f403 2380 and.w r3, r3, #262144 @ 0x40000 8009d6a: 2b00 cmp r3, #0 8009d6c: d018 beq.n 8009da0 { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 8009d6e: 687b ldr r3, [r7, #4] 8009d70: 681b ldr r3, [r3, #0] 8009d72: 681b ldr r3, [r3, #0] 8009d74: f403 2300 and.w r3, r3, #524288 @ 0x80000 8009d78: 2b00 cmp r3, #0 8009d7a: d108 bne.n 8009d8e { if(hdma->XferHalfCpltCallback != NULL) 8009d7c: 687b ldr r3, [r7, #4] 8009d7e: 6c1b ldr r3, [r3, #64] @ 0x40 8009d80: 2b00 cmp r3, #0 8009d82: d024 beq.n 8009dce { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8009d84: 687b ldr r3, [r7, #4] 8009d86: 6c1b ldr r3, [r3, #64] @ 0x40 8009d88: 6878 ldr r0, [r7, #4] 8009d8a: 4798 blx r3 8009d8c: e01f b.n 8009dce } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 8009d8e: 687b ldr r3, [r7, #4] 8009d90: 6c9b ldr r3, [r3, #72] @ 0x48 8009d92: 2b00 cmp r3, #0 8009d94: d01b beq.n 8009dce { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 8009d96: 687b ldr r3, [r7, #4] 8009d98: 6c9b ldr r3, [r3, #72] @ 0x48 8009d9a: 6878 ldr r0, [r7, #4] 8009d9c: 4798 blx r3 8009d9e: e016 b.n 8009dce } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 8009da0: 687b ldr r3, [r7, #4] 8009da2: 681b ldr r3, [r3, #0] 8009da4: 681b ldr r3, [r3, #0] 8009da6: f403 7380 and.w r3, r3, #256 @ 0x100 8009daa: 2b00 cmp r3, #0 8009dac: d107 bne.n 8009dbe { /* Disable the half transfer interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 8009dae: 687b ldr r3, [r7, #4] 8009db0: 681b ldr r3, [r3, #0] 8009db2: 681a ldr r2, [r3, #0] 8009db4: 687b ldr r3, [r7, #4] 8009db6: 681b ldr r3, [r3, #0] 8009db8: f022 0208 bic.w r2, r2, #8 8009dbc: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 8009dbe: 687b ldr r3, [r7, #4] 8009dc0: 6c1b ldr r3, [r3, #64] @ 0x40 8009dc2: 2b00 cmp r3, #0 8009dc4: d003 beq.n 8009dce { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8009dc6: 687b ldr r3, [r7, #4] 8009dc8: 6c1b ldr r3, [r3, #64] @ 0x40 8009dca: 6878 ldr r0, [r7, #4] 8009dcc: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009dce: 687b ldr r3, [r7, #4] 8009dd0: 6ddb ldr r3, [r3, #92] @ 0x5c 8009dd2: f003 031f and.w r3, r3, #31 8009dd6: 2220 movs r2, #32 8009dd8: 409a lsls r2, r3 8009dda: 69bb ldr r3, [r7, #24] 8009ddc: 4013 ands r3, r2 8009dde: 2b00 cmp r3, #0 8009de0: f000 8110 beq.w 800a004 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) 8009de4: 687b ldr r3, [r7, #4] 8009de6: 681b ldr r3, [r3, #0] 8009de8: 4a2c ldr r2, [pc, #176] @ (8009e9c ) 8009dea: 4293 cmp r3, r2 8009dec: d04a beq.n 8009e84 8009dee: 687b ldr r3, [r7, #4] 8009df0: 681b ldr r3, [r3, #0] 8009df2: 4a2b ldr r2, [pc, #172] @ (8009ea0 ) 8009df4: 4293 cmp r3, r2 8009df6: d045 beq.n 8009e84 8009df8: 687b ldr r3, [r7, #4] 8009dfa: 681b ldr r3, [r3, #0] 8009dfc: 4a29 ldr r2, [pc, #164] @ (8009ea4 ) 8009dfe: 4293 cmp r3, r2 8009e00: d040 beq.n 8009e84 8009e02: 687b ldr r3, [r7, #4] 8009e04: 681b ldr r3, [r3, #0] 8009e06: 4a28 ldr r2, [pc, #160] @ (8009ea8 ) 8009e08: 4293 cmp r3, r2 8009e0a: d03b beq.n 8009e84 8009e0c: 687b ldr r3, [r7, #4] 8009e0e: 681b ldr r3, [r3, #0] 8009e10: 4a26 ldr r2, [pc, #152] @ (8009eac ) 8009e12: 4293 cmp r3, r2 8009e14: d036 beq.n 8009e84 8009e16: 687b ldr r3, [r7, #4] 8009e18: 681b ldr r3, [r3, #0] 8009e1a: 4a25 ldr r2, [pc, #148] @ (8009eb0 ) 8009e1c: 4293 cmp r3, r2 8009e1e: d031 beq.n 8009e84 8009e20: 687b ldr r3, [r7, #4] 8009e22: 681b ldr r3, [r3, #0] 8009e24: 4a23 ldr r2, [pc, #140] @ (8009eb4 ) 8009e26: 4293 cmp r3, r2 8009e28: d02c beq.n 8009e84 8009e2a: 687b ldr r3, [r7, #4] 8009e2c: 681b ldr r3, [r3, #0] 8009e2e: 4a22 ldr r2, [pc, #136] @ (8009eb8 ) 8009e30: 4293 cmp r3, r2 8009e32: d027 beq.n 8009e84 8009e34: 687b ldr r3, [r7, #4] 8009e36: 681b ldr r3, [r3, #0] 8009e38: 4a20 ldr r2, [pc, #128] @ (8009ebc ) 8009e3a: 4293 cmp r3, r2 8009e3c: d022 beq.n 8009e84 8009e3e: 687b ldr r3, [r7, #4] 8009e40: 681b ldr r3, [r3, #0] 8009e42: 4a1f ldr r2, [pc, #124] @ (8009ec0 ) 8009e44: 4293 cmp r3, r2 8009e46: d01d beq.n 8009e84 8009e48: 687b ldr r3, [r7, #4] 8009e4a: 681b ldr r3, [r3, #0] 8009e4c: 4a1d ldr r2, [pc, #116] @ (8009ec4 ) 8009e4e: 4293 cmp r3, r2 8009e50: d018 beq.n 8009e84 8009e52: 687b ldr r3, [r7, #4] 8009e54: 681b ldr r3, [r3, #0] 8009e56: 4a1c ldr r2, [pc, #112] @ (8009ec8 ) 8009e58: 4293 cmp r3, r2 8009e5a: d013 beq.n 8009e84 8009e5c: 687b ldr r3, [r7, #4] 8009e5e: 681b ldr r3, [r3, #0] 8009e60: 4a1a ldr r2, [pc, #104] @ (8009ecc ) 8009e62: 4293 cmp r3, r2 8009e64: d00e beq.n 8009e84 8009e66: 687b ldr r3, [r7, #4] 8009e68: 681b ldr r3, [r3, #0] 8009e6a: 4a19 ldr r2, [pc, #100] @ (8009ed0 ) 8009e6c: 4293 cmp r3, r2 8009e6e: d009 beq.n 8009e84 8009e70: 687b ldr r3, [r7, #4] 8009e72: 681b ldr r3, [r3, #0] 8009e74: 4a17 ldr r2, [pc, #92] @ (8009ed4 ) 8009e76: 4293 cmp r3, r2 8009e78: d004 beq.n 8009e84 8009e7a: 687b ldr r3, [r7, #4] 8009e7c: 681b ldr r3, [r3, #0] 8009e7e: 4a16 ldr r2, [pc, #88] @ (8009ed8 ) 8009e80: 4293 cmp r3, r2 8009e82: d12b bne.n 8009edc 8009e84: 687b ldr r3, [r7, #4] 8009e86: 681b ldr r3, [r3, #0] 8009e88: 681b ldr r3, [r3, #0] 8009e8a: f003 0310 and.w r3, r3, #16 8009e8e: 2b00 cmp r3, #0 8009e90: bf14 ite ne 8009e92: 2301 movne r3, #1 8009e94: 2300 moveq r3, #0 8009e96: b2db uxtb r3, r3 8009e98: e02a b.n 8009ef0 8009e9a: bf00 nop 8009e9c: 40020010 .word 0x40020010 8009ea0: 40020028 .word 0x40020028 8009ea4: 40020040 .word 0x40020040 8009ea8: 40020058 .word 0x40020058 8009eac: 40020070 .word 0x40020070 8009eb0: 40020088 .word 0x40020088 8009eb4: 400200a0 .word 0x400200a0 8009eb8: 400200b8 .word 0x400200b8 8009ebc: 40020410 .word 0x40020410 8009ec0: 40020428 .word 0x40020428 8009ec4: 40020440 .word 0x40020440 8009ec8: 40020458 .word 0x40020458 8009ecc: 40020470 .word 0x40020470 8009ed0: 40020488 .word 0x40020488 8009ed4: 400204a0 .word 0x400204a0 8009ed8: 400204b8 .word 0x400204b8 8009edc: 687b ldr r3, [r7, #4] 8009ede: 681b ldr r3, [r3, #0] 8009ee0: 681b ldr r3, [r3, #0] 8009ee2: f003 0302 and.w r3, r3, #2 8009ee6: 2b00 cmp r3, #0 8009ee8: bf14 ite ne 8009eea: 2301 movne r3, #1 8009eec: 2300 moveq r3, #0 8009eee: b2db uxtb r3, r3 8009ef0: 2b00 cmp r3, #0 8009ef2: f000 8087 beq.w 800a004 { /* Clear the transfer complete flag */ regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); 8009ef6: 687b ldr r3, [r7, #4] 8009ef8: 6ddb ldr r3, [r3, #92] @ 0x5c 8009efa: f003 031f and.w r3, r3, #31 8009efe: 2220 movs r2, #32 8009f00: 409a lsls r2, r3 8009f02: 6a3b ldr r3, [r7, #32] 8009f04: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 8009f06: 687b ldr r3, [r7, #4] 8009f08: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8009f0c: b2db uxtb r3, r3 8009f0e: 2b04 cmp r3, #4 8009f10: d139 bne.n 8009f86 { /* Disable all the transfer interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 8009f12: 687b ldr r3, [r7, #4] 8009f14: 681b ldr r3, [r3, #0] 8009f16: 681a ldr r2, [r3, #0] 8009f18: 687b ldr r3, [r7, #4] 8009f1a: 681b ldr r3, [r3, #0] 8009f1c: f022 0216 bic.w r2, r2, #22 8009f20: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 8009f22: 687b ldr r3, [r7, #4] 8009f24: 681b ldr r3, [r3, #0] 8009f26: 695a ldr r2, [r3, #20] 8009f28: 687b ldr r3, [r7, #4] 8009f2a: 681b ldr r3, [r3, #0] 8009f2c: f022 0280 bic.w r2, r2, #128 @ 0x80 8009f30: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 8009f32: 687b ldr r3, [r7, #4] 8009f34: 6c1b ldr r3, [r3, #64] @ 0x40 8009f36: 2b00 cmp r3, #0 8009f38: d103 bne.n 8009f42 8009f3a: 687b ldr r3, [r7, #4] 8009f3c: 6c9b ldr r3, [r3, #72] @ 0x48 8009f3e: 2b00 cmp r3, #0 8009f40: d007 beq.n 8009f52 { ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 8009f42: 687b ldr r3, [r7, #4] 8009f44: 681b ldr r3, [r3, #0] 8009f46: 681a ldr r2, [r3, #0] 8009f48: 687b ldr r3, [r7, #4] 8009f4a: 681b ldr r3, [r3, #0] 8009f4c: f022 0208 bic.w r2, r2, #8 8009f50: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8009f52: 687b ldr r3, [r7, #4] 8009f54: 6ddb ldr r3, [r3, #92] @ 0x5c 8009f56: f003 031f and.w r3, r3, #31 8009f5a: 223f movs r2, #63 @ 0x3f 8009f5c: 409a lsls r2, r3 8009f5e: 6a3b ldr r3, [r7, #32] 8009f60: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8009f62: 687b ldr r3, [r7, #4] 8009f64: 2201 movs r2, #1 8009f66: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009f6a: 687b ldr r3, [r7, #4] 8009f6c: 2200 movs r2, #0 8009f6e: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 8009f72: 687b ldr r3, [r7, #4] 8009f74: 6d1b ldr r3, [r3, #80] @ 0x50 8009f76: 2b00 cmp r3, #0 8009f78: f000 834a beq.w 800a610 { hdma->XferAbortCallback(hdma); 8009f7c: 687b ldr r3, [r7, #4] 8009f7e: 6d1b ldr r3, [r3, #80] @ 0x50 8009f80: 6878 ldr r0, [r7, #4] 8009f82: 4798 blx r3 } return; 8009f84: e344 b.n 800a610 } if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 8009f86: 687b ldr r3, [r7, #4] 8009f88: 681b ldr r3, [r3, #0] 8009f8a: 681b ldr r3, [r3, #0] 8009f8c: f403 2380 and.w r3, r3, #262144 @ 0x40000 8009f90: 2b00 cmp r3, #0 8009f92: d018 beq.n 8009fc6 { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 8009f94: 687b ldr r3, [r7, #4] 8009f96: 681b ldr r3, [r3, #0] 8009f98: 681b ldr r3, [r3, #0] 8009f9a: f403 2300 and.w r3, r3, #524288 @ 0x80000 8009f9e: 2b00 cmp r3, #0 8009fa0: d108 bne.n 8009fb4 { if(hdma->XferM1CpltCallback != NULL) 8009fa2: 687b ldr r3, [r7, #4] 8009fa4: 6c5b ldr r3, [r3, #68] @ 0x44 8009fa6: 2b00 cmp r3, #0 8009fa8: d02c beq.n 800a004 { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 8009faa: 687b ldr r3, [r7, #4] 8009fac: 6c5b ldr r3, [r3, #68] @ 0x44 8009fae: 6878 ldr r0, [r7, #4] 8009fb0: 4798 blx r3 8009fb2: e027 b.n 800a004 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 8009fb4: 687b ldr r3, [r7, #4] 8009fb6: 6bdb ldr r3, [r3, #60] @ 0x3c 8009fb8: 2b00 cmp r3, #0 8009fba: d023 beq.n 800a004 { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 8009fbc: 687b ldr r3, [r7, #4] 8009fbe: 6bdb ldr r3, [r3, #60] @ 0x3c 8009fc0: 6878 ldr r0, [r7, #4] 8009fc2: 4798 blx r3 8009fc4: e01e b.n 800a004 } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 8009fc6: 687b ldr r3, [r7, #4] 8009fc8: 681b ldr r3, [r3, #0] 8009fca: 681b ldr r3, [r3, #0] 8009fcc: f403 7380 and.w r3, r3, #256 @ 0x100 8009fd0: 2b00 cmp r3, #0 8009fd2: d10f bne.n 8009ff4 { /* Disable the transfer complete interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); 8009fd4: 687b ldr r3, [r7, #4] 8009fd6: 681b ldr r3, [r3, #0] 8009fd8: 681a ldr r2, [r3, #0] 8009fda: 687b ldr r3, [r7, #4] 8009fdc: 681b ldr r3, [r3, #0] 8009fde: f022 0210 bic.w r2, r2, #16 8009fe2: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8009fe4: 687b ldr r3, [r7, #4] 8009fe6: 2201 movs r2, #1 8009fe8: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009fec: 687b ldr r3, [r7, #4] 8009fee: 2200 movs r2, #0 8009ff0: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 8009ff4: 687b ldr r3, [r7, #4] 8009ff6: 6bdb ldr r3, [r3, #60] @ 0x3c 8009ff8: 2b00 cmp r3, #0 8009ffa: d003 beq.n 800a004 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8009ffc: 687b ldr r3, [r7, #4] 8009ffe: 6bdb ldr r3, [r3, #60] @ 0x3c 800a000: 6878 ldr r0, [r7, #4] 800a002: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 800a004: 687b ldr r3, [r7, #4] 800a006: 6d5b ldr r3, [r3, #84] @ 0x54 800a008: 2b00 cmp r3, #0 800a00a: f000 8306 beq.w 800a61a { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) 800a00e: 687b ldr r3, [r7, #4] 800a010: 6d5b ldr r3, [r3, #84] @ 0x54 800a012: f003 0301 and.w r3, r3, #1 800a016: 2b00 cmp r3, #0 800a018: f000 8088 beq.w 800a12c { hdma->State = HAL_DMA_STATE_ABORT; 800a01c: 687b ldr r3, [r7, #4] 800a01e: 2204 movs r2, #4 800a020: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800a024: 687b ldr r3, [r7, #4] 800a026: 681b ldr r3, [r3, #0] 800a028: 4a7a ldr r2, [pc, #488] @ (800a214 ) 800a02a: 4293 cmp r3, r2 800a02c: d04a beq.n 800a0c4 800a02e: 687b ldr r3, [r7, #4] 800a030: 681b ldr r3, [r3, #0] 800a032: 4a79 ldr r2, [pc, #484] @ (800a218 ) 800a034: 4293 cmp r3, r2 800a036: d045 beq.n 800a0c4 800a038: 687b ldr r3, [r7, #4] 800a03a: 681b ldr r3, [r3, #0] 800a03c: 4a77 ldr r2, [pc, #476] @ (800a21c ) 800a03e: 4293 cmp r3, r2 800a040: d040 beq.n 800a0c4 800a042: 687b ldr r3, [r7, #4] 800a044: 681b ldr r3, [r3, #0] 800a046: 4a76 ldr r2, [pc, #472] @ (800a220 ) 800a048: 4293 cmp r3, r2 800a04a: d03b beq.n 800a0c4 800a04c: 687b ldr r3, [r7, #4] 800a04e: 681b ldr r3, [r3, #0] 800a050: 4a74 ldr r2, [pc, #464] @ (800a224 ) 800a052: 4293 cmp r3, r2 800a054: d036 beq.n 800a0c4 800a056: 687b ldr r3, [r7, #4] 800a058: 681b ldr r3, [r3, #0] 800a05a: 4a73 ldr r2, [pc, #460] @ (800a228 ) 800a05c: 4293 cmp r3, r2 800a05e: d031 beq.n 800a0c4 800a060: 687b ldr r3, [r7, #4] 800a062: 681b ldr r3, [r3, #0] 800a064: 4a71 ldr r2, [pc, #452] @ (800a22c ) 800a066: 4293 cmp r3, r2 800a068: d02c beq.n 800a0c4 800a06a: 687b ldr r3, [r7, #4] 800a06c: 681b ldr r3, [r3, #0] 800a06e: 4a70 ldr r2, [pc, #448] @ (800a230 ) 800a070: 4293 cmp r3, r2 800a072: d027 beq.n 800a0c4 800a074: 687b ldr r3, [r7, #4] 800a076: 681b ldr r3, [r3, #0] 800a078: 4a6e ldr r2, [pc, #440] @ (800a234 ) 800a07a: 4293 cmp r3, r2 800a07c: d022 beq.n 800a0c4 800a07e: 687b ldr r3, [r7, #4] 800a080: 681b ldr r3, [r3, #0] 800a082: 4a6d ldr r2, [pc, #436] @ (800a238 ) 800a084: 4293 cmp r3, r2 800a086: d01d beq.n 800a0c4 800a088: 687b ldr r3, [r7, #4] 800a08a: 681b ldr r3, [r3, #0] 800a08c: 4a6b ldr r2, [pc, #428] @ (800a23c ) 800a08e: 4293 cmp r3, r2 800a090: d018 beq.n 800a0c4 800a092: 687b ldr r3, [r7, #4] 800a094: 681b ldr r3, [r3, #0] 800a096: 4a6a ldr r2, [pc, #424] @ (800a240 ) 800a098: 4293 cmp r3, r2 800a09a: d013 beq.n 800a0c4 800a09c: 687b ldr r3, [r7, #4] 800a09e: 681b ldr r3, [r3, #0] 800a0a0: 4a68 ldr r2, [pc, #416] @ (800a244 ) 800a0a2: 4293 cmp r3, r2 800a0a4: d00e beq.n 800a0c4 800a0a6: 687b ldr r3, [r7, #4] 800a0a8: 681b ldr r3, [r3, #0] 800a0aa: 4a67 ldr r2, [pc, #412] @ (800a248 ) 800a0ac: 4293 cmp r3, r2 800a0ae: d009 beq.n 800a0c4 800a0b0: 687b ldr r3, [r7, #4] 800a0b2: 681b ldr r3, [r3, #0] 800a0b4: 4a65 ldr r2, [pc, #404] @ (800a24c ) 800a0b6: 4293 cmp r3, r2 800a0b8: d004 beq.n 800a0c4 800a0ba: 687b ldr r3, [r7, #4] 800a0bc: 681b ldr r3, [r3, #0] 800a0be: 4a64 ldr r2, [pc, #400] @ (800a250 ) 800a0c0: 4293 cmp r3, r2 800a0c2: d108 bne.n 800a0d6 800a0c4: 687b ldr r3, [r7, #4] 800a0c6: 681b ldr r3, [r3, #0] 800a0c8: 681a ldr r2, [r3, #0] 800a0ca: 687b ldr r3, [r7, #4] 800a0cc: 681b ldr r3, [r3, #0] 800a0ce: f022 0201 bic.w r2, r2, #1 800a0d2: 601a str r2, [r3, #0] 800a0d4: e007 b.n 800a0e6 800a0d6: 687b ldr r3, [r7, #4] 800a0d8: 681b ldr r3, [r3, #0] 800a0da: 681a ldr r2, [r3, #0] 800a0dc: 687b ldr r3, [r7, #4] 800a0de: 681b ldr r3, [r3, #0] 800a0e0: f022 0201 bic.w r2, r2, #1 800a0e4: 601a str r2, [r3, #0] do { if (++count > timeout) 800a0e6: 68fb ldr r3, [r7, #12] 800a0e8: 3301 adds r3, #1 800a0ea: 60fb str r3, [r7, #12] 800a0ec: 6a7a ldr r2, [r7, #36] @ 0x24 800a0ee: 429a cmp r2, r3 800a0f0: d307 bcc.n 800a102 { break; } } while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); 800a0f2: 687b ldr r3, [r7, #4] 800a0f4: 681b ldr r3, [r3, #0] 800a0f6: 681b ldr r3, [r3, #0] 800a0f8: f003 0301 and.w r3, r3, #1 800a0fc: 2b00 cmp r3, #0 800a0fe: d1f2 bne.n 800a0e6 800a100: e000 b.n 800a104 break; 800a102: bf00 nop if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 800a104: 687b ldr r3, [r7, #4] 800a106: 681b ldr r3, [r3, #0] 800a108: 681b ldr r3, [r3, #0] 800a10a: f003 0301 and.w r3, r3, #1 800a10e: 2b00 cmp r3, #0 800a110: d004 beq.n 800a11c { /* Change the DMA state to error if DMA disable fails */ hdma->State = HAL_DMA_STATE_ERROR; 800a112: 687b ldr r3, [r7, #4] 800a114: 2203 movs r2, #3 800a116: f883 2035 strb.w r2, [r3, #53] @ 0x35 800a11a: e003 b.n 800a124 } else { /* Change the DMA state to Ready if DMA disable success */ hdma->State = HAL_DMA_STATE_READY; 800a11c: 687b ldr r3, [r7, #4] 800a11e: 2201 movs r2, #1 800a120: f883 2035 strb.w r2, [r3, #53] @ 0x35 } /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a124: 687b ldr r3, [r7, #4] 800a126: 2200 movs r2, #0 800a128: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 800a12c: 687b ldr r3, [r7, #4] 800a12e: 6cdb ldr r3, [r3, #76] @ 0x4c 800a130: 2b00 cmp r3, #0 800a132: f000 8272 beq.w 800a61a { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800a136: 687b ldr r3, [r7, #4] 800a138: 6cdb ldr r3, [r3, #76] @ 0x4c 800a13a: 6878 ldr r0, [r7, #4] 800a13c: 4798 blx r3 800a13e: e26c b.n 800a61a } } } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 800a140: 687b ldr r3, [r7, #4] 800a142: 681b ldr r3, [r3, #0] 800a144: 4a43 ldr r2, [pc, #268] @ (800a254 ) 800a146: 4293 cmp r3, r2 800a148: d022 beq.n 800a190 800a14a: 687b ldr r3, [r7, #4] 800a14c: 681b ldr r3, [r3, #0] 800a14e: 4a42 ldr r2, [pc, #264] @ (800a258 ) 800a150: 4293 cmp r3, r2 800a152: d01d beq.n 800a190 800a154: 687b ldr r3, [r7, #4] 800a156: 681b ldr r3, [r3, #0] 800a158: 4a40 ldr r2, [pc, #256] @ (800a25c ) 800a15a: 4293 cmp r3, r2 800a15c: d018 beq.n 800a190 800a15e: 687b ldr r3, [r7, #4] 800a160: 681b ldr r3, [r3, #0] 800a162: 4a3f ldr r2, [pc, #252] @ (800a260 ) 800a164: 4293 cmp r3, r2 800a166: d013 beq.n 800a190 800a168: 687b ldr r3, [r7, #4] 800a16a: 681b ldr r3, [r3, #0] 800a16c: 4a3d ldr r2, [pc, #244] @ (800a264 ) 800a16e: 4293 cmp r3, r2 800a170: d00e beq.n 800a190 800a172: 687b ldr r3, [r7, #4] 800a174: 681b ldr r3, [r3, #0] 800a176: 4a3c ldr r2, [pc, #240] @ (800a268 ) 800a178: 4293 cmp r3, r2 800a17a: d009 beq.n 800a190 800a17c: 687b ldr r3, [r7, #4] 800a17e: 681b ldr r3, [r3, #0] 800a180: 4a3a ldr r2, [pc, #232] @ (800a26c ) 800a182: 4293 cmp r3, r2 800a184: d004 beq.n 800a190 800a186: 687b ldr r3, [r7, #4] 800a188: 681b ldr r3, [r3, #0] 800a18a: 4a39 ldr r2, [pc, #228] @ (800a270 ) 800a18c: 4293 cmp r3, r2 800a18e: d101 bne.n 800a194 800a190: 2301 movs r3, #1 800a192: e000 b.n 800a196 800a194: 2300 movs r3, #0 800a196: 2b00 cmp r3, #0 800a198: f000 823f beq.w 800a61a { ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); 800a19c: 687b ldr r3, [r7, #4] 800a19e: 681b ldr r3, [r3, #0] 800a1a0: 681b ldr r3, [r3, #0] 800a1a2: 613b str r3, [r7, #16] /* Half Transfer Complete Interrupt management ******************************/ if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) 800a1a4: 687b ldr r3, [r7, #4] 800a1a6: 6ddb ldr r3, [r3, #92] @ 0x5c 800a1a8: f003 031f and.w r3, r3, #31 800a1ac: 2204 movs r2, #4 800a1ae: 409a lsls r2, r3 800a1b0: 697b ldr r3, [r7, #20] 800a1b2: 4013 ands r3, r2 800a1b4: 2b00 cmp r3, #0 800a1b6: f000 80cd beq.w 800a354 800a1ba: 693b ldr r3, [r7, #16] 800a1bc: f003 0304 and.w r3, r3, #4 800a1c0: 2b00 cmp r3, #0 800a1c2: f000 80c7 beq.w 800a354 { /* Clear the half transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); 800a1c6: 687b ldr r3, [r7, #4] 800a1c8: 6ddb ldr r3, [r3, #92] @ 0x5c 800a1ca: f003 031f and.w r3, r3, #31 800a1ce: 2204 movs r2, #4 800a1d0: 409a lsls r2, r3 800a1d2: 69fb ldr r3, [r7, #28] 800a1d4: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a1d6: 693b ldr r3, [r7, #16] 800a1d8: f403 4300 and.w r3, r3, #32768 @ 0x8000 800a1dc: 2b00 cmp r3, #0 800a1de: d049 beq.n 800a274 { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 800a1e0: 693b ldr r3, [r7, #16] 800a1e2: f403 3380 and.w r3, r3, #65536 @ 0x10000 800a1e6: 2b00 cmp r3, #0 800a1e8: d109 bne.n 800a1fe { if(hdma->XferM1HalfCpltCallback != NULL) 800a1ea: 687b ldr r3, [r7, #4] 800a1ec: 6c9b ldr r3, [r3, #72] @ 0x48 800a1ee: 2b00 cmp r3, #0 800a1f0: f000 8210 beq.w 800a614 { /* Half transfer Callback for Memory 1 */ hdma->XferM1HalfCpltCallback(hdma); 800a1f4: 687b ldr r3, [r7, #4] 800a1f6: 6c9b ldr r3, [r3, #72] @ 0x48 800a1f8: 6878 ldr r0, [r7, #4] 800a1fa: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a1fc: e20a b.n 800a614 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferHalfCpltCallback != NULL) 800a1fe: 687b ldr r3, [r7, #4] 800a200: 6c1b ldr r3, [r3, #64] @ 0x40 800a202: 2b00 cmp r3, #0 800a204: f000 8206 beq.w 800a614 { /* Half transfer Callback for Memory 0 */ hdma->XferHalfCpltCallback(hdma); 800a208: 687b ldr r3, [r7, #4] 800a20a: 6c1b ldr r3, [r3, #64] @ 0x40 800a20c: 6878 ldr r0, [r7, #4] 800a20e: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a210: e200 b.n 800a614 800a212: bf00 nop 800a214: 40020010 .word 0x40020010 800a218: 40020028 .word 0x40020028 800a21c: 40020040 .word 0x40020040 800a220: 40020058 .word 0x40020058 800a224: 40020070 .word 0x40020070 800a228: 40020088 .word 0x40020088 800a22c: 400200a0 .word 0x400200a0 800a230: 400200b8 .word 0x400200b8 800a234: 40020410 .word 0x40020410 800a238: 40020428 .word 0x40020428 800a23c: 40020440 .word 0x40020440 800a240: 40020458 .word 0x40020458 800a244: 40020470 .word 0x40020470 800a248: 40020488 .word 0x40020488 800a24c: 400204a0 .word 0x400204a0 800a250: 400204b8 .word 0x400204b8 800a254: 58025408 .word 0x58025408 800a258: 5802541c .word 0x5802541c 800a25c: 58025430 .word 0x58025430 800a260: 58025444 .word 0x58025444 800a264: 58025458 .word 0x58025458 800a268: 5802546c .word 0x5802546c 800a26c: 58025480 .word 0x58025480 800a270: 58025494 .word 0x58025494 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 800a274: 693b ldr r3, [r7, #16] 800a276: f003 0320 and.w r3, r3, #32 800a27a: 2b00 cmp r3, #0 800a27c: d160 bne.n 800a340 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800a27e: 687b ldr r3, [r7, #4] 800a280: 681b ldr r3, [r3, #0] 800a282: 4a7f ldr r2, [pc, #508] @ (800a480 ) 800a284: 4293 cmp r3, r2 800a286: d04a beq.n 800a31e 800a288: 687b ldr r3, [r7, #4] 800a28a: 681b ldr r3, [r3, #0] 800a28c: 4a7d ldr r2, [pc, #500] @ (800a484 ) 800a28e: 4293 cmp r3, r2 800a290: d045 beq.n 800a31e 800a292: 687b ldr r3, [r7, #4] 800a294: 681b ldr r3, [r3, #0] 800a296: 4a7c ldr r2, [pc, #496] @ (800a488 ) 800a298: 4293 cmp r3, r2 800a29a: d040 beq.n 800a31e 800a29c: 687b ldr r3, [r7, #4] 800a29e: 681b ldr r3, [r3, #0] 800a2a0: 4a7a ldr r2, [pc, #488] @ (800a48c ) 800a2a2: 4293 cmp r3, r2 800a2a4: d03b beq.n 800a31e 800a2a6: 687b ldr r3, [r7, #4] 800a2a8: 681b ldr r3, [r3, #0] 800a2aa: 4a79 ldr r2, [pc, #484] @ (800a490 ) 800a2ac: 4293 cmp r3, r2 800a2ae: d036 beq.n 800a31e 800a2b0: 687b ldr r3, [r7, #4] 800a2b2: 681b ldr r3, [r3, #0] 800a2b4: 4a77 ldr r2, [pc, #476] @ (800a494 ) 800a2b6: 4293 cmp r3, r2 800a2b8: d031 beq.n 800a31e 800a2ba: 687b ldr r3, [r7, #4] 800a2bc: 681b ldr r3, [r3, #0] 800a2be: 4a76 ldr r2, [pc, #472] @ (800a498 ) 800a2c0: 4293 cmp r3, r2 800a2c2: d02c beq.n 800a31e 800a2c4: 687b ldr r3, [r7, #4] 800a2c6: 681b ldr r3, [r3, #0] 800a2c8: 4a74 ldr r2, [pc, #464] @ (800a49c ) 800a2ca: 4293 cmp r3, r2 800a2cc: d027 beq.n 800a31e 800a2ce: 687b ldr r3, [r7, #4] 800a2d0: 681b ldr r3, [r3, #0] 800a2d2: 4a73 ldr r2, [pc, #460] @ (800a4a0 ) 800a2d4: 4293 cmp r3, r2 800a2d6: d022 beq.n 800a31e 800a2d8: 687b ldr r3, [r7, #4] 800a2da: 681b ldr r3, [r3, #0] 800a2dc: 4a71 ldr r2, [pc, #452] @ (800a4a4 ) 800a2de: 4293 cmp r3, r2 800a2e0: d01d beq.n 800a31e 800a2e2: 687b ldr r3, [r7, #4] 800a2e4: 681b ldr r3, [r3, #0] 800a2e6: 4a70 ldr r2, [pc, #448] @ (800a4a8 ) 800a2e8: 4293 cmp r3, r2 800a2ea: d018 beq.n 800a31e 800a2ec: 687b ldr r3, [r7, #4] 800a2ee: 681b ldr r3, [r3, #0] 800a2f0: 4a6e ldr r2, [pc, #440] @ (800a4ac ) 800a2f2: 4293 cmp r3, r2 800a2f4: d013 beq.n 800a31e 800a2f6: 687b ldr r3, [r7, #4] 800a2f8: 681b ldr r3, [r3, #0] 800a2fa: 4a6d ldr r2, [pc, #436] @ (800a4b0 ) 800a2fc: 4293 cmp r3, r2 800a2fe: d00e beq.n 800a31e 800a300: 687b ldr r3, [r7, #4] 800a302: 681b ldr r3, [r3, #0] 800a304: 4a6b ldr r2, [pc, #428] @ (800a4b4 ) 800a306: 4293 cmp r3, r2 800a308: d009 beq.n 800a31e 800a30a: 687b ldr r3, [r7, #4] 800a30c: 681b ldr r3, [r3, #0] 800a30e: 4a6a ldr r2, [pc, #424] @ (800a4b8 ) 800a310: 4293 cmp r3, r2 800a312: d004 beq.n 800a31e 800a314: 687b ldr r3, [r7, #4] 800a316: 681b ldr r3, [r3, #0] 800a318: 4a68 ldr r2, [pc, #416] @ (800a4bc ) 800a31a: 4293 cmp r3, r2 800a31c: d108 bne.n 800a330 800a31e: 687b ldr r3, [r7, #4] 800a320: 681b ldr r3, [r3, #0] 800a322: 681a ldr r2, [r3, #0] 800a324: 687b ldr r3, [r7, #4] 800a326: 681b ldr r3, [r3, #0] 800a328: f022 0208 bic.w r2, r2, #8 800a32c: 601a str r2, [r3, #0] 800a32e: e007 b.n 800a340 800a330: 687b ldr r3, [r7, #4] 800a332: 681b ldr r3, [r3, #0] 800a334: 681a ldr r2, [r3, #0] 800a336: 687b ldr r3, [r7, #4] 800a338: 681b ldr r3, [r3, #0] 800a33a: f022 0204 bic.w r2, r2, #4 800a33e: 601a str r2, [r3, #0] } /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 800a340: 687b ldr r3, [r7, #4] 800a342: 6c1b ldr r3, [r3, #64] @ 0x40 800a344: 2b00 cmp r3, #0 800a346: f000 8165 beq.w 800a614 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800a34a: 687b ldr r3, [r7, #4] 800a34c: 6c1b ldr r3, [r3, #64] @ 0x40 800a34e: 6878 ldr r0, [r7, #4] 800a350: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a352: e15f b.n 800a614 } } } /* Transfer Complete Interrupt management ***********************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) 800a354: 687b ldr r3, [r7, #4] 800a356: 6ddb ldr r3, [r3, #92] @ 0x5c 800a358: f003 031f and.w r3, r3, #31 800a35c: 2202 movs r2, #2 800a35e: 409a lsls r2, r3 800a360: 697b ldr r3, [r7, #20] 800a362: 4013 ands r3, r2 800a364: 2b00 cmp r3, #0 800a366: f000 80c5 beq.w 800a4f4 800a36a: 693b ldr r3, [r7, #16] 800a36c: f003 0302 and.w r3, r3, #2 800a370: 2b00 cmp r3, #0 800a372: f000 80bf beq.w 800a4f4 { /* Clear the transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); 800a376: 687b ldr r3, [r7, #4] 800a378: 6ddb ldr r3, [r3, #92] @ 0x5c 800a37a: f003 031f and.w r3, r3, #31 800a37e: 2202 movs r2, #2 800a380: 409a lsls r2, r3 800a382: 69fb ldr r3, [r7, #28] 800a384: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a386: 693b ldr r3, [r7, #16] 800a388: f403 4300 and.w r3, r3, #32768 @ 0x8000 800a38c: 2b00 cmp r3, #0 800a38e: d018 beq.n 800a3c2 { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 800a390: 693b ldr r3, [r7, #16] 800a392: f403 3380 and.w r3, r3, #65536 @ 0x10000 800a396: 2b00 cmp r3, #0 800a398: d109 bne.n 800a3ae { if(hdma->XferM1CpltCallback != NULL) 800a39a: 687b ldr r3, [r7, #4] 800a39c: 6c5b ldr r3, [r3, #68] @ 0x44 800a39e: 2b00 cmp r3, #0 800a3a0: f000 813a beq.w 800a618 { /* Transfer complete Callback for Memory 1 */ hdma->XferM1CpltCallback(hdma); 800a3a4: 687b ldr r3, [r7, #4] 800a3a6: 6c5b ldr r3, [r3, #68] @ 0x44 800a3a8: 6878 ldr r0, [r7, #4] 800a3aa: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a3ac: e134 b.n 800a618 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800a3ae: 687b ldr r3, [r7, #4] 800a3b0: 6bdb ldr r3, [r3, #60] @ 0x3c 800a3b2: 2b00 cmp r3, #0 800a3b4: f000 8130 beq.w 800a618 { /* Transfer complete Callback for Memory 0 */ hdma->XferCpltCallback(hdma); 800a3b8: 687b ldr r3, [r7, #4] 800a3ba: 6bdb ldr r3, [r3, #60] @ 0x3c 800a3bc: 6878 ldr r0, [r7, #4] 800a3be: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a3c0: e12a b.n 800a618 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 800a3c2: 693b ldr r3, [r7, #16] 800a3c4: f003 0320 and.w r3, r3, #32 800a3c8: 2b00 cmp r3, #0 800a3ca: f040 8089 bne.w 800a4e0 { /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 800a3ce: 687b ldr r3, [r7, #4] 800a3d0: 681b ldr r3, [r3, #0] 800a3d2: 4a2b ldr r2, [pc, #172] @ (800a480 ) 800a3d4: 4293 cmp r3, r2 800a3d6: d04a beq.n 800a46e 800a3d8: 687b ldr r3, [r7, #4] 800a3da: 681b ldr r3, [r3, #0] 800a3dc: 4a29 ldr r2, [pc, #164] @ (800a484 ) 800a3de: 4293 cmp r3, r2 800a3e0: d045 beq.n 800a46e 800a3e2: 687b ldr r3, [r7, #4] 800a3e4: 681b ldr r3, [r3, #0] 800a3e6: 4a28 ldr r2, [pc, #160] @ (800a488 ) 800a3e8: 4293 cmp r3, r2 800a3ea: d040 beq.n 800a46e 800a3ec: 687b ldr r3, [r7, #4] 800a3ee: 681b ldr r3, [r3, #0] 800a3f0: 4a26 ldr r2, [pc, #152] @ (800a48c ) 800a3f2: 4293 cmp r3, r2 800a3f4: d03b beq.n 800a46e 800a3f6: 687b ldr r3, [r7, #4] 800a3f8: 681b ldr r3, [r3, #0] 800a3fa: 4a25 ldr r2, [pc, #148] @ (800a490 ) 800a3fc: 4293 cmp r3, r2 800a3fe: d036 beq.n 800a46e 800a400: 687b ldr r3, [r7, #4] 800a402: 681b ldr r3, [r3, #0] 800a404: 4a23 ldr r2, [pc, #140] @ (800a494 ) 800a406: 4293 cmp r3, r2 800a408: d031 beq.n 800a46e 800a40a: 687b ldr r3, [r7, #4] 800a40c: 681b ldr r3, [r3, #0] 800a40e: 4a22 ldr r2, [pc, #136] @ (800a498 ) 800a410: 4293 cmp r3, r2 800a412: d02c beq.n 800a46e 800a414: 687b ldr r3, [r7, #4] 800a416: 681b ldr r3, [r3, #0] 800a418: 4a20 ldr r2, [pc, #128] @ (800a49c ) 800a41a: 4293 cmp r3, r2 800a41c: d027 beq.n 800a46e 800a41e: 687b ldr r3, [r7, #4] 800a420: 681b ldr r3, [r3, #0] 800a422: 4a1f ldr r2, [pc, #124] @ (800a4a0 ) 800a424: 4293 cmp r3, r2 800a426: d022 beq.n 800a46e 800a428: 687b ldr r3, [r7, #4] 800a42a: 681b ldr r3, [r3, #0] 800a42c: 4a1d ldr r2, [pc, #116] @ (800a4a4 ) 800a42e: 4293 cmp r3, r2 800a430: d01d beq.n 800a46e 800a432: 687b ldr r3, [r7, #4] 800a434: 681b ldr r3, [r3, #0] 800a436: 4a1c ldr r2, [pc, #112] @ (800a4a8 ) 800a438: 4293 cmp r3, r2 800a43a: d018 beq.n 800a46e 800a43c: 687b ldr r3, [r7, #4] 800a43e: 681b ldr r3, [r3, #0] 800a440: 4a1a ldr r2, [pc, #104] @ (800a4ac ) 800a442: 4293 cmp r3, r2 800a444: d013 beq.n 800a46e 800a446: 687b ldr r3, [r7, #4] 800a448: 681b ldr r3, [r3, #0] 800a44a: 4a19 ldr r2, [pc, #100] @ (800a4b0 ) 800a44c: 4293 cmp r3, r2 800a44e: d00e beq.n 800a46e 800a450: 687b ldr r3, [r7, #4] 800a452: 681b ldr r3, [r3, #0] 800a454: 4a17 ldr r2, [pc, #92] @ (800a4b4 ) 800a456: 4293 cmp r3, r2 800a458: d009 beq.n 800a46e 800a45a: 687b ldr r3, [r7, #4] 800a45c: 681b ldr r3, [r3, #0] 800a45e: 4a16 ldr r2, [pc, #88] @ (800a4b8 ) 800a460: 4293 cmp r3, r2 800a462: d004 beq.n 800a46e 800a464: 687b ldr r3, [r7, #4] 800a466: 681b ldr r3, [r3, #0] 800a468: 4a14 ldr r2, [pc, #80] @ (800a4bc ) 800a46a: 4293 cmp r3, r2 800a46c: d128 bne.n 800a4c0 800a46e: 687b ldr r3, [r7, #4] 800a470: 681b ldr r3, [r3, #0] 800a472: 681a ldr r2, [r3, #0] 800a474: 687b ldr r3, [r7, #4] 800a476: 681b ldr r3, [r3, #0] 800a478: f022 0214 bic.w r2, r2, #20 800a47c: 601a str r2, [r3, #0] 800a47e: e027 b.n 800a4d0 800a480: 40020010 .word 0x40020010 800a484: 40020028 .word 0x40020028 800a488: 40020040 .word 0x40020040 800a48c: 40020058 .word 0x40020058 800a490: 40020070 .word 0x40020070 800a494: 40020088 .word 0x40020088 800a498: 400200a0 .word 0x400200a0 800a49c: 400200b8 .word 0x400200b8 800a4a0: 40020410 .word 0x40020410 800a4a4: 40020428 .word 0x40020428 800a4a8: 40020440 .word 0x40020440 800a4ac: 40020458 .word 0x40020458 800a4b0: 40020470 .word 0x40020470 800a4b4: 40020488 .word 0x40020488 800a4b8: 400204a0 .word 0x400204a0 800a4bc: 400204b8 .word 0x400204b8 800a4c0: 687b ldr r3, [r7, #4] 800a4c2: 681b ldr r3, [r3, #0] 800a4c4: 681a ldr r2, [r3, #0] 800a4c6: 687b ldr r3, [r7, #4] 800a4c8: 681b ldr r3, [r3, #0] 800a4ca: f022 020a bic.w r2, r2, #10 800a4ce: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a4d0: 687b ldr r3, [r7, #4] 800a4d2: 2201 movs r2, #1 800a4d4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a4d8: 687b ldr r3, [r7, #4] 800a4da: 2200 movs r2, #0 800a4dc: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 800a4e0: 687b ldr r3, [r7, #4] 800a4e2: 6bdb ldr r3, [r3, #60] @ 0x3c 800a4e4: 2b00 cmp r3, #0 800a4e6: f000 8097 beq.w 800a618 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 800a4ea: 687b ldr r3, [r7, #4] 800a4ec: 6bdb ldr r3, [r3, #60] @ 0x3c 800a4ee: 6878 ldr r0, [r7, #4] 800a4f0: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a4f2: e091 b.n 800a618 } } } /* Transfer Error Interrupt management **************************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) 800a4f4: 687b ldr r3, [r7, #4] 800a4f6: 6ddb ldr r3, [r3, #92] @ 0x5c 800a4f8: f003 031f and.w r3, r3, #31 800a4fc: 2208 movs r2, #8 800a4fe: 409a lsls r2, r3 800a500: 697b ldr r3, [r7, #20] 800a502: 4013 ands r3, r2 800a504: 2b00 cmp r3, #0 800a506: f000 8088 beq.w 800a61a 800a50a: 693b ldr r3, [r7, #16] 800a50c: f003 0308 and.w r3, r3, #8 800a510: 2b00 cmp r3, #0 800a512: f000 8082 beq.w 800a61a { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800a516: 687b ldr r3, [r7, #4] 800a518: 681b ldr r3, [r3, #0] 800a51a: 4a41 ldr r2, [pc, #260] @ (800a620 ) 800a51c: 4293 cmp r3, r2 800a51e: d04a beq.n 800a5b6 800a520: 687b ldr r3, [r7, #4] 800a522: 681b ldr r3, [r3, #0] 800a524: 4a3f ldr r2, [pc, #252] @ (800a624 ) 800a526: 4293 cmp r3, r2 800a528: d045 beq.n 800a5b6 800a52a: 687b ldr r3, [r7, #4] 800a52c: 681b ldr r3, [r3, #0] 800a52e: 4a3e ldr r2, [pc, #248] @ (800a628 ) 800a530: 4293 cmp r3, r2 800a532: d040 beq.n 800a5b6 800a534: 687b ldr r3, [r7, #4] 800a536: 681b ldr r3, [r3, #0] 800a538: 4a3c ldr r2, [pc, #240] @ (800a62c ) 800a53a: 4293 cmp r3, r2 800a53c: d03b beq.n 800a5b6 800a53e: 687b ldr r3, [r7, #4] 800a540: 681b ldr r3, [r3, #0] 800a542: 4a3b ldr r2, [pc, #236] @ (800a630 ) 800a544: 4293 cmp r3, r2 800a546: d036 beq.n 800a5b6 800a548: 687b ldr r3, [r7, #4] 800a54a: 681b ldr r3, [r3, #0] 800a54c: 4a39 ldr r2, [pc, #228] @ (800a634 ) 800a54e: 4293 cmp r3, r2 800a550: d031 beq.n 800a5b6 800a552: 687b ldr r3, [r7, #4] 800a554: 681b ldr r3, [r3, #0] 800a556: 4a38 ldr r2, [pc, #224] @ (800a638 ) 800a558: 4293 cmp r3, r2 800a55a: d02c beq.n 800a5b6 800a55c: 687b ldr r3, [r7, #4] 800a55e: 681b ldr r3, [r3, #0] 800a560: 4a36 ldr r2, [pc, #216] @ (800a63c ) 800a562: 4293 cmp r3, r2 800a564: d027 beq.n 800a5b6 800a566: 687b ldr r3, [r7, #4] 800a568: 681b ldr r3, [r3, #0] 800a56a: 4a35 ldr r2, [pc, #212] @ (800a640 ) 800a56c: 4293 cmp r3, r2 800a56e: d022 beq.n 800a5b6 800a570: 687b ldr r3, [r7, #4] 800a572: 681b ldr r3, [r3, #0] 800a574: 4a33 ldr r2, [pc, #204] @ (800a644 ) 800a576: 4293 cmp r3, r2 800a578: d01d beq.n 800a5b6 800a57a: 687b ldr r3, [r7, #4] 800a57c: 681b ldr r3, [r3, #0] 800a57e: 4a32 ldr r2, [pc, #200] @ (800a648 ) 800a580: 4293 cmp r3, r2 800a582: d018 beq.n 800a5b6 800a584: 687b ldr r3, [r7, #4] 800a586: 681b ldr r3, [r3, #0] 800a588: 4a30 ldr r2, [pc, #192] @ (800a64c ) 800a58a: 4293 cmp r3, r2 800a58c: d013 beq.n 800a5b6 800a58e: 687b ldr r3, [r7, #4] 800a590: 681b ldr r3, [r3, #0] 800a592: 4a2f ldr r2, [pc, #188] @ (800a650 ) 800a594: 4293 cmp r3, r2 800a596: d00e beq.n 800a5b6 800a598: 687b ldr r3, [r7, #4] 800a59a: 681b ldr r3, [r3, #0] 800a59c: 4a2d ldr r2, [pc, #180] @ (800a654 ) 800a59e: 4293 cmp r3, r2 800a5a0: d009 beq.n 800a5b6 800a5a2: 687b ldr r3, [r7, #4] 800a5a4: 681b ldr r3, [r3, #0] 800a5a6: 4a2c ldr r2, [pc, #176] @ (800a658 ) 800a5a8: 4293 cmp r3, r2 800a5aa: d004 beq.n 800a5b6 800a5ac: 687b ldr r3, [r7, #4] 800a5ae: 681b ldr r3, [r3, #0] 800a5b0: 4a2a ldr r2, [pc, #168] @ (800a65c ) 800a5b2: 4293 cmp r3, r2 800a5b4: d108 bne.n 800a5c8 800a5b6: 687b ldr r3, [r7, #4] 800a5b8: 681b ldr r3, [r3, #0] 800a5ba: 681a ldr r2, [r3, #0] 800a5bc: 687b ldr r3, [r7, #4] 800a5be: 681b ldr r3, [r3, #0] 800a5c0: f022 021c bic.w r2, r2, #28 800a5c4: 601a str r2, [r3, #0] 800a5c6: e007 b.n 800a5d8 800a5c8: 687b ldr r3, [r7, #4] 800a5ca: 681b ldr r3, [r3, #0] 800a5cc: 681a ldr r2, [r3, #0] 800a5ce: 687b ldr r3, [r7, #4] 800a5d0: 681b ldr r3, [r3, #0] 800a5d2: f022 020e bic.w r2, r2, #14 800a5d6: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 800a5d8: 687b ldr r3, [r7, #4] 800a5da: 6ddb ldr r3, [r3, #92] @ 0x5c 800a5dc: f003 031f and.w r3, r3, #31 800a5e0: 2201 movs r2, #1 800a5e2: 409a lsls r2, r3 800a5e4: 69fb ldr r3, [r7, #28] 800a5e6: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 800a5e8: 687b ldr r3, [r7, #4] 800a5ea: 2201 movs r2, #1 800a5ec: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a5ee: 687b ldr r3, [r7, #4] 800a5f0: 2201 movs r2, #1 800a5f2: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a5f6: 687b ldr r3, [r7, #4] 800a5f8: 2200 movs r2, #0 800a5fa: f883 2034 strb.w r2, [r3, #52] @ 0x34 if (hdma->XferErrorCallback != NULL) 800a5fe: 687b ldr r3, [r7, #4] 800a600: 6cdb ldr r3, [r3, #76] @ 0x4c 800a602: 2b00 cmp r3, #0 800a604: d009 beq.n 800a61a { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800a606: 687b ldr r3, [r7, #4] 800a608: 6cdb ldr r3, [r3, #76] @ 0x4c 800a60a: 6878 ldr r0, [r7, #4] 800a60c: 4798 blx r3 800a60e: e004 b.n 800a61a return; 800a610: bf00 nop 800a612: e002 b.n 800a61a if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a614: bf00 nop 800a616: e000 b.n 800a61a if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a618: bf00 nop } else { /* Nothing To Do */ } } 800a61a: 3728 adds r7, #40 @ 0x28 800a61c: 46bd mov sp, r7 800a61e: bd80 pop {r7, pc} 800a620: 40020010 .word 0x40020010 800a624: 40020028 .word 0x40020028 800a628: 40020040 .word 0x40020040 800a62c: 40020058 .word 0x40020058 800a630: 40020070 .word 0x40020070 800a634: 40020088 .word 0x40020088 800a638: 400200a0 .word 0x400200a0 800a63c: 400200b8 .word 0x400200b8 800a640: 40020410 .word 0x40020410 800a644: 40020428 .word 0x40020428 800a648: 40020440 .word 0x40020440 800a64c: 40020458 .word 0x40020458 800a650: 40020470 .word 0x40020470 800a654: 40020488 .word 0x40020488 800a658: 400204a0 .word 0x400204a0 800a65c: 400204b8 .word 0x400204b8 0800a660 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval None */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 800a660: b480 push {r7} 800a662: b087 sub sp, #28 800a664: af00 add r7, sp, #0 800a666: 60f8 str r0, [r7, #12] 800a668: 60b9 str r1, [r7, #8] 800a66a: 607a str r2, [r7, #4] 800a66c: 603b str r3, [r7, #0] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 800a66e: 68fb ldr r3, [r7, #12] 800a670: 6d9b ldr r3, [r3, #88] @ 0x58 800a672: 617b str r3, [r7, #20] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 800a674: 68fb ldr r3, [r7, #12] 800a676: 6d9b ldr r3, [r3, #88] @ 0x58 800a678: 613b str r3, [r7, #16] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800a67a: 68fb ldr r3, [r7, #12] 800a67c: 681b ldr r3, [r3, #0] 800a67e: 4a7f ldr r2, [pc, #508] @ (800a87c ) 800a680: 4293 cmp r3, r2 800a682: d072 beq.n 800a76a 800a684: 68fb ldr r3, [r7, #12] 800a686: 681b ldr r3, [r3, #0] 800a688: 4a7d ldr r2, [pc, #500] @ (800a880 ) 800a68a: 4293 cmp r3, r2 800a68c: d06d beq.n 800a76a 800a68e: 68fb ldr r3, [r7, #12] 800a690: 681b ldr r3, [r3, #0] 800a692: 4a7c ldr r2, [pc, #496] @ (800a884 ) 800a694: 4293 cmp r3, r2 800a696: d068 beq.n 800a76a 800a698: 68fb ldr r3, [r7, #12] 800a69a: 681b ldr r3, [r3, #0] 800a69c: 4a7a ldr r2, [pc, #488] @ (800a888 ) 800a69e: 4293 cmp r3, r2 800a6a0: d063 beq.n 800a76a 800a6a2: 68fb ldr r3, [r7, #12] 800a6a4: 681b ldr r3, [r3, #0] 800a6a6: 4a79 ldr r2, [pc, #484] @ (800a88c ) 800a6a8: 4293 cmp r3, r2 800a6aa: d05e beq.n 800a76a 800a6ac: 68fb ldr r3, [r7, #12] 800a6ae: 681b ldr r3, [r3, #0] 800a6b0: 4a77 ldr r2, [pc, #476] @ (800a890 ) 800a6b2: 4293 cmp r3, r2 800a6b4: d059 beq.n 800a76a 800a6b6: 68fb ldr r3, [r7, #12] 800a6b8: 681b ldr r3, [r3, #0] 800a6ba: 4a76 ldr r2, [pc, #472] @ (800a894 ) 800a6bc: 4293 cmp r3, r2 800a6be: d054 beq.n 800a76a 800a6c0: 68fb ldr r3, [r7, #12] 800a6c2: 681b ldr r3, [r3, #0] 800a6c4: 4a74 ldr r2, [pc, #464] @ (800a898 ) 800a6c6: 4293 cmp r3, r2 800a6c8: d04f beq.n 800a76a 800a6ca: 68fb ldr r3, [r7, #12] 800a6cc: 681b ldr r3, [r3, #0] 800a6ce: 4a73 ldr r2, [pc, #460] @ (800a89c ) 800a6d0: 4293 cmp r3, r2 800a6d2: d04a beq.n 800a76a 800a6d4: 68fb ldr r3, [r7, #12] 800a6d6: 681b ldr r3, [r3, #0] 800a6d8: 4a71 ldr r2, [pc, #452] @ (800a8a0 ) 800a6da: 4293 cmp r3, r2 800a6dc: d045 beq.n 800a76a 800a6de: 68fb ldr r3, [r7, #12] 800a6e0: 681b ldr r3, [r3, #0] 800a6e2: 4a70 ldr r2, [pc, #448] @ (800a8a4 ) 800a6e4: 4293 cmp r3, r2 800a6e6: d040 beq.n 800a76a 800a6e8: 68fb ldr r3, [r7, #12] 800a6ea: 681b ldr r3, [r3, #0] 800a6ec: 4a6e ldr r2, [pc, #440] @ (800a8a8 ) 800a6ee: 4293 cmp r3, r2 800a6f0: d03b beq.n 800a76a 800a6f2: 68fb ldr r3, [r7, #12] 800a6f4: 681b ldr r3, [r3, #0] 800a6f6: 4a6d ldr r2, [pc, #436] @ (800a8ac ) 800a6f8: 4293 cmp r3, r2 800a6fa: d036 beq.n 800a76a 800a6fc: 68fb ldr r3, [r7, #12] 800a6fe: 681b ldr r3, [r3, #0] 800a700: 4a6b ldr r2, [pc, #428] @ (800a8b0 ) 800a702: 4293 cmp r3, r2 800a704: d031 beq.n 800a76a 800a706: 68fb ldr r3, [r7, #12] 800a708: 681b ldr r3, [r3, #0] 800a70a: 4a6a ldr r2, [pc, #424] @ (800a8b4 ) 800a70c: 4293 cmp r3, r2 800a70e: d02c beq.n 800a76a 800a710: 68fb ldr r3, [r7, #12] 800a712: 681b ldr r3, [r3, #0] 800a714: 4a68 ldr r2, [pc, #416] @ (800a8b8 ) 800a716: 4293 cmp r3, r2 800a718: d027 beq.n 800a76a 800a71a: 68fb ldr r3, [r7, #12] 800a71c: 681b ldr r3, [r3, #0] 800a71e: 4a67 ldr r2, [pc, #412] @ (800a8bc ) 800a720: 4293 cmp r3, r2 800a722: d022 beq.n 800a76a 800a724: 68fb ldr r3, [r7, #12] 800a726: 681b ldr r3, [r3, #0] 800a728: 4a65 ldr r2, [pc, #404] @ (800a8c0 ) 800a72a: 4293 cmp r3, r2 800a72c: d01d beq.n 800a76a 800a72e: 68fb ldr r3, [r7, #12] 800a730: 681b ldr r3, [r3, #0] 800a732: 4a64 ldr r2, [pc, #400] @ (800a8c4 ) 800a734: 4293 cmp r3, r2 800a736: d018 beq.n 800a76a 800a738: 68fb ldr r3, [r7, #12] 800a73a: 681b ldr r3, [r3, #0] 800a73c: 4a62 ldr r2, [pc, #392] @ (800a8c8 ) 800a73e: 4293 cmp r3, r2 800a740: d013 beq.n 800a76a 800a742: 68fb ldr r3, [r7, #12] 800a744: 681b ldr r3, [r3, #0] 800a746: 4a61 ldr r2, [pc, #388] @ (800a8cc ) 800a748: 4293 cmp r3, r2 800a74a: d00e beq.n 800a76a 800a74c: 68fb ldr r3, [r7, #12] 800a74e: 681b ldr r3, [r3, #0] 800a750: 4a5f ldr r2, [pc, #380] @ (800a8d0 ) 800a752: 4293 cmp r3, r2 800a754: d009 beq.n 800a76a 800a756: 68fb ldr r3, [r7, #12] 800a758: 681b ldr r3, [r3, #0] 800a75a: 4a5e ldr r2, [pc, #376] @ (800a8d4 ) 800a75c: 4293 cmp r3, r2 800a75e: d004 beq.n 800a76a 800a760: 68fb ldr r3, [r7, #12] 800a762: 681b ldr r3, [r3, #0] 800a764: 4a5c ldr r2, [pc, #368] @ (800a8d8 ) 800a766: 4293 cmp r3, r2 800a768: d101 bne.n 800a76e 800a76a: 2301 movs r3, #1 800a76c: e000 b.n 800a770 800a76e: 2300 movs r3, #0 800a770: 2b00 cmp r3, #0 800a772: d00d beq.n 800a790 { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 800a774: 68fb ldr r3, [r7, #12] 800a776: 6e5b ldr r3, [r3, #100] @ 0x64 800a778: 68fa ldr r2, [r7, #12] 800a77a: 6e92 ldr r2, [r2, #104] @ 0x68 800a77c: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 800a77e: 68fb ldr r3, [r7, #12] 800a780: 6edb ldr r3, [r3, #108] @ 0x6c 800a782: 2b00 cmp r3, #0 800a784: d004 beq.n 800a790 { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 800a786: 68fb ldr r3, [r7, #12] 800a788: 6f1b ldr r3, [r3, #112] @ 0x70 800a78a: 68fa ldr r2, [r7, #12] 800a78c: 6f52 ldr r2, [r2, #116] @ 0x74 800a78e: 605a str r2, [r3, #4] } } if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800a790: 68fb ldr r3, [r7, #12] 800a792: 681b ldr r3, [r3, #0] 800a794: 4a39 ldr r2, [pc, #228] @ (800a87c ) 800a796: 4293 cmp r3, r2 800a798: d04a beq.n 800a830 800a79a: 68fb ldr r3, [r7, #12] 800a79c: 681b ldr r3, [r3, #0] 800a79e: 4a38 ldr r2, [pc, #224] @ (800a880 ) 800a7a0: 4293 cmp r3, r2 800a7a2: d045 beq.n 800a830 800a7a4: 68fb ldr r3, [r7, #12] 800a7a6: 681b ldr r3, [r3, #0] 800a7a8: 4a36 ldr r2, [pc, #216] @ (800a884 ) 800a7aa: 4293 cmp r3, r2 800a7ac: d040 beq.n 800a830 800a7ae: 68fb ldr r3, [r7, #12] 800a7b0: 681b ldr r3, [r3, #0] 800a7b2: 4a35 ldr r2, [pc, #212] @ (800a888 ) 800a7b4: 4293 cmp r3, r2 800a7b6: d03b beq.n 800a830 800a7b8: 68fb ldr r3, [r7, #12] 800a7ba: 681b ldr r3, [r3, #0] 800a7bc: 4a33 ldr r2, [pc, #204] @ (800a88c ) 800a7be: 4293 cmp r3, r2 800a7c0: d036 beq.n 800a830 800a7c2: 68fb ldr r3, [r7, #12] 800a7c4: 681b ldr r3, [r3, #0] 800a7c6: 4a32 ldr r2, [pc, #200] @ (800a890 ) 800a7c8: 4293 cmp r3, r2 800a7ca: d031 beq.n 800a830 800a7cc: 68fb ldr r3, [r7, #12] 800a7ce: 681b ldr r3, [r3, #0] 800a7d0: 4a30 ldr r2, [pc, #192] @ (800a894 ) 800a7d2: 4293 cmp r3, r2 800a7d4: d02c beq.n 800a830 800a7d6: 68fb ldr r3, [r7, #12] 800a7d8: 681b ldr r3, [r3, #0] 800a7da: 4a2f ldr r2, [pc, #188] @ (800a898 ) 800a7dc: 4293 cmp r3, r2 800a7de: d027 beq.n 800a830 800a7e0: 68fb ldr r3, [r7, #12] 800a7e2: 681b ldr r3, [r3, #0] 800a7e4: 4a2d ldr r2, [pc, #180] @ (800a89c ) 800a7e6: 4293 cmp r3, r2 800a7e8: d022 beq.n 800a830 800a7ea: 68fb ldr r3, [r7, #12] 800a7ec: 681b ldr r3, [r3, #0] 800a7ee: 4a2c ldr r2, [pc, #176] @ (800a8a0 ) 800a7f0: 4293 cmp r3, r2 800a7f2: d01d beq.n 800a830 800a7f4: 68fb ldr r3, [r7, #12] 800a7f6: 681b ldr r3, [r3, #0] 800a7f8: 4a2a ldr r2, [pc, #168] @ (800a8a4 ) 800a7fa: 4293 cmp r3, r2 800a7fc: d018 beq.n 800a830 800a7fe: 68fb ldr r3, [r7, #12] 800a800: 681b ldr r3, [r3, #0] 800a802: 4a29 ldr r2, [pc, #164] @ (800a8a8 ) 800a804: 4293 cmp r3, r2 800a806: d013 beq.n 800a830 800a808: 68fb ldr r3, [r7, #12] 800a80a: 681b ldr r3, [r3, #0] 800a80c: 4a27 ldr r2, [pc, #156] @ (800a8ac ) 800a80e: 4293 cmp r3, r2 800a810: d00e beq.n 800a830 800a812: 68fb ldr r3, [r7, #12] 800a814: 681b ldr r3, [r3, #0] 800a816: 4a26 ldr r2, [pc, #152] @ (800a8b0 ) 800a818: 4293 cmp r3, r2 800a81a: d009 beq.n 800a830 800a81c: 68fb ldr r3, [r7, #12] 800a81e: 681b ldr r3, [r3, #0] 800a820: 4a24 ldr r2, [pc, #144] @ (800a8b4 ) 800a822: 4293 cmp r3, r2 800a824: d004 beq.n 800a830 800a826: 68fb ldr r3, [r7, #12] 800a828: 681b ldr r3, [r3, #0] 800a82a: 4a23 ldr r2, [pc, #140] @ (800a8b8 ) 800a82c: 4293 cmp r3, r2 800a82e: d101 bne.n 800a834 800a830: 2301 movs r3, #1 800a832: e000 b.n 800a836 800a834: 2300 movs r3, #0 800a836: 2b00 cmp r3, #0 800a838: d059 beq.n 800a8ee { /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800a83a: 68fb ldr r3, [r7, #12] 800a83c: 6ddb ldr r3, [r3, #92] @ 0x5c 800a83e: f003 031f and.w r3, r3, #31 800a842: 223f movs r2, #63 @ 0x3f 800a844: 409a lsls r2, r3 800a846: 697b ldr r3, [r7, #20] 800a848: 609a str r2, [r3, #8] /* Clear DBM bit */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM); 800a84a: 68fb ldr r3, [r7, #12] 800a84c: 681b ldr r3, [r3, #0] 800a84e: 681a ldr r2, [r3, #0] 800a850: 68fb ldr r3, [r7, #12] 800a852: 681b ldr r3, [r3, #0] 800a854: f422 2280 bic.w r2, r2, #262144 @ 0x40000 800a858: 601a str r2, [r3, #0] /* Configure DMA Stream data length */ ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; 800a85a: 68fb ldr r3, [r7, #12] 800a85c: 681b ldr r3, [r3, #0] 800a85e: 683a ldr r2, [r7, #0] 800a860: 605a str r2, [r3, #4] /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800a862: 68fb ldr r3, [r7, #12] 800a864: 689b ldr r3, [r3, #8] 800a866: 2b40 cmp r3, #64 @ 0x40 800a868: d138 bne.n 800a8dc { /* Configure DMA Stream destination address */ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; 800a86a: 68fb ldr r3, [r7, #12] 800a86c: 681b ldr r3, [r3, #0] 800a86e: 687a ldr r2, [r7, #4] 800a870: 609a str r2, [r3, #8] /* Configure DMA Stream source address */ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; 800a872: 68fb ldr r3, [r7, #12] 800a874: 681b ldr r3, [r3, #0] 800a876: 68ba ldr r2, [r7, #8] 800a878: 60da str r2, [r3, #12] } else { /* Nothing To Do */ } } 800a87a: e086 b.n 800a98a 800a87c: 40020010 .word 0x40020010 800a880: 40020028 .word 0x40020028 800a884: 40020040 .word 0x40020040 800a888: 40020058 .word 0x40020058 800a88c: 40020070 .word 0x40020070 800a890: 40020088 .word 0x40020088 800a894: 400200a0 .word 0x400200a0 800a898: 400200b8 .word 0x400200b8 800a89c: 40020410 .word 0x40020410 800a8a0: 40020428 .word 0x40020428 800a8a4: 40020440 .word 0x40020440 800a8a8: 40020458 .word 0x40020458 800a8ac: 40020470 .word 0x40020470 800a8b0: 40020488 .word 0x40020488 800a8b4: 400204a0 .word 0x400204a0 800a8b8: 400204b8 .word 0x400204b8 800a8bc: 58025408 .word 0x58025408 800a8c0: 5802541c .word 0x5802541c 800a8c4: 58025430 .word 0x58025430 800a8c8: 58025444 .word 0x58025444 800a8cc: 58025458 .word 0x58025458 800a8d0: 5802546c .word 0x5802546c 800a8d4: 58025480 .word 0x58025480 800a8d8: 58025494 .word 0x58025494 ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; 800a8dc: 68fb ldr r3, [r7, #12] 800a8de: 681b ldr r3, [r3, #0] 800a8e0: 68ba ldr r2, [r7, #8] 800a8e2: 609a str r2, [r3, #8] ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; 800a8e4: 68fb ldr r3, [r7, #12] 800a8e6: 681b ldr r3, [r3, #0] 800a8e8: 687a ldr r2, [r7, #4] 800a8ea: 60da str r2, [r3, #12] } 800a8ec: e04d b.n 800a98a else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 800a8ee: 68fb ldr r3, [r7, #12] 800a8f0: 681b ldr r3, [r3, #0] 800a8f2: 4a29 ldr r2, [pc, #164] @ (800a998 ) 800a8f4: 4293 cmp r3, r2 800a8f6: d022 beq.n 800a93e 800a8f8: 68fb ldr r3, [r7, #12] 800a8fa: 681b ldr r3, [r3, #0] 800a8fc: 4a27 ldr r2, [pc, #156] @ (800a99c ) 800a8fe: 4293 cmp r3, r2 800a900: d01d beq.n 800a93e 800a902: 68fb ldr r3, [r7, #12] 800a904: 681b ldr r3, [r3, #0] 800a906: 4a26 ldr r2, [pc, #152] @ (800a9a0 ) 800a908: 4293 cmp r3, r2 800a90a: d018 beq.n 800a93e 800a90c: 68fb ldr r3, [r7, #12] 800a90e: 681b ldr r3, [r3, #0] 800a910: 4a24 ldr r2, [pc, #144] @ (800a9a4 ) 800a912: 4293 cmp r3, r2 800a914: d013 beq.n 800a93e 800a916: 68fb ldr r3, [r7, #12] 800a918: 681b ldr r3, [r3, #0] 800a91a: 4a23 ldr r2, [pc, #140] @ (800a9a8 ) 800a91c: 4293 cmp r3, r2 800a91e: d00e beq.n 800a93e 800a920: 68fb ldr r3, [r7, #12] 800a922: 681b ldr r3, [r3, #0] 800a924: 4a21 ldr r2, [pc, #132] @ (800a9ac ) 800a926: 4293 cmp r3, r2 800a928: d009 beq.n 800a93e 800a92a: 68fb ldr r3, [r7, #12] 800a92c: 681b ldr r3, [r3, #0] 800a92e: 4a20 ldr r2, [pc, #128] @ (800a9b0 ) 800a930: 4293 cmp r3, r2 800a932: d004 beq.n 800a93e 800a934: 68fb ldr r3, [r7, #12] 800a936: 681b ldr r3, [r3, #0] 800a938: 4a1e ldr r2, [pc, #120] @ (800a9b4 ) 800a93a: 4293 cmp r3, r2 800a93c: d101 bne.n 800a942 800a93e: 2301 movs r3, #1 800a940: e000 b.n 800a944 800a942: 2300 movs r3, #0 800a944: 2b00 cmp r3, #0 800a946: d020 beq.n 800a98a regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 800a948: 68fb ldr r3, [r7, #12] 800a94a: 6ddb ldr r3, [r3, #92] @ 0x5c 800a94c: f003 031f and.w r3, r3, #31 800a950: 2201 movs r2, #1 800a952: 409a lsls r2, r3 800a954: 693b ldr r3, [r7, #16] 800a956: 605a str r2, [r3, #4] ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; 800a958: 68fb ldr r3, [r7, #12] 800a95a: 681b ldr r3, [r3, #0] 800a95c: 683a ldr r2, [r7, #0] 800a95e: 605a str r2, [r3, #4] if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800a960: 68fb ldr r3, [r7, #12] 800a962: 689b ldr r3, [r3, #8] 800a964: 2b40 cmp r3, #64 @ 0x40 800a966: d108 bne.n 800a97a ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; 800a968: 68fb ldr r3, [r7, #12] 800a96a: 681b ldr r3, [r3, #0] 800a96c: 687a ldr r2, [r7, #4] 800a96e: 609a str r2, [r3, #8] ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; 800a970: 68fb ldr r3, [r7, #12] 800a972: 681b ldr r3, [r3, #0] 800a974: 68ba ldr r2, [r7, #8] 800a976: 60da str r2, [r3, #12] } 800a978: e007 b.n 800a98a ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; 800a97a: 68fb ldr r3, [r7, #12] 800a97c: 681b ldr r3, [r3, #0] 800a97e: 68ba ldr r2, [r7, #8] 800a980: 609a str r2, [r3, #8] ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; 800a982: 68fb ldr r3, [r7, #12] 800a984: 681b ldr r3, [r3, #0] 800a986: 687a ldr r2, [r7, #4] 800a988: 60da str r2, [r3, #12] } 800a98a: bf00 nop 800a98c: 371c adds r7, #28 800a98e: 46bd mov sp, r7 800a990: f85d 7b04 ldr.w r7, [sp], #4 800a994: 4770 bx lr 800a996: bf00 nop 800a998: 58025408 .word 0x58025408 800a99c: 5802541c .word 0x5802541c 800a9a0: 58025430 .word 0x58025430 800a9a4: 58025444 .word 0x58025444 800a9a8: 58025458 .word 0x58025458 800a9ac: 5802546c .word 0x5802546c 800a9b0: 58025480 .word 0x58025480 800a9b4: 58025494 .word 0x58025494 0800a9b8 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 800a9b8: b480 push {r7} 800a9ba: b085 sub sp, #20 800a9bc: af00 add r7, sp, #0 800a9be: 6078 str r0, [r7, #4] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800a9c0: 687b ldr r3, [r7, #4] 800a9c2: 681b ldr r3, [r3, #0] 800a9c4: 4a42 ldr r2, [pc, #264] @ (800aad0 ) 800a9c6: 4293 cmp r3, r2 800a9c8: d04a beq.n 800aa60 800a9ca: 687b ldr r3, [r7, #4] 800a9cc: 681b ldr r3, [r3, #0] 800a9ce: 4a41 ldr r2, [pc, #260] @ (800aad4 ) 800a9d0: 4293 cmp r3, r2 800a9d2: d045 beq.n 800aa60 800a9d4: 687b ldr r3, [r7, #4] 800a9d6: 681b ldr r3, [r3, #0] 800a9d8: 4a3f ldr r2, [pc, #252] @ (800aad8 ) 800a9da: 4293 cmp r3, r2 800a9dc: d040 beq.n 800aa60 800a9de: 687b ldr r3, [r7, #4] 800a9e0: 681b ldr r3, [r3, #0] 800a9e2: 4a3e ldr r2, [pc, #248] @ (800aadc ) 800a9e4: 4293 cmp r3, r2 800a9e6: d03b beq.n 800aa60 800a9e8: 687b ldr r3, [r7, #4] 800a9ea: 681b ldr r3, [r3, #0] 800a9ec: 4a3c ldr r2, [pc, #240] @ (800aae0 ) 800a9ee: 4293 cmp r3, r2 800a9f0: d036 beq.n 800aa60 800a9f2: 687b ldr r3, [r7, #4] 800a9f4: 681b ldr r3, [r3, #0] 800a9f6: 4a3b ldr r2, [pc, #236] @ (800aae4 ) 800a9f8: 4293 cmp r3, r2 800a9fa: d031 beq.n 800aa60 800a9fc: 687b ldr r3, [r7, #4] 800a9fe: 681b ldr r3, [r3, #0] 800aa00: 4a39 ldr r2, [pc, #228] @ (800aae8 ) 800aa02: 4293 cmp r3, r2 800aa04: d02c beq.n 800aa60 800aa06: 687b ldr r3, [r7, #4] 800aa08: 681b ldr r3, [r3, #0] 800aa0a: 4a38 ldr r2, [pc, #224] @ (800aaec ) 800aa0c: 4293 cmp r3, r2 800aa0e: d027 beq.n 800aa60 800aa10: 687b ldr r3, [r7, #4] 800aa12: 681b ldr r3, [r3, #0] 800aa14: 4a36 ldr r2, [pc, #216] @ (800aaf0 ) 800aa16: 4293 cmp r3, r2 800aa18: d022 beq.n 800aa60 800aa1a: 687b ldr r3, [r7, #4] 800aa1c: 681b ldr r3, [r3, #0] 800aa1e: 4a35 ldr r2, [pc, #212] @ (800aaf4 ) 800aa20: 4293 cmp r3, r2 800aa22: d01d beq.n 800aa60 800aa24: 687b ldr r3, [r7, #4] 800aa26: 681b ldr r3, [r3, #0] 800aa28: 4a33 ldr r2, [pc, #204] @ (800aaf8 ) 800aa2a: 4293 cmp r3, r2 800aa2c: d018 beq.n 800aa60 800aa2e: 687b ldr r3, [r7, #4] 800aa30: 681b ldr r3, [r3, #0] 800aa32: 4a32 ldr r2, [pc, #200] @ (800aafc ) 800aa34: 4293 cmp r3, r2 800aa36: d013 beq.n 800aa60 800aa38: 687b ldr r3, [r7, #4] 800aa3a: 681b ldr r3, [r3, #0] 800aa3c: 4a30 ldr r2, [pc, #192] @ (800ab00 ) 800aa3e: 4293 cmp r3, r2 800aa40: d00e beq.n 800aa60 800aa42: 687b ldr r3, [r7, #4] 800aa44: 681b ldr r3, [r3, #0] 800aa46: 4a2f ldr r2, [pc, #188] @ (800ab04 ) 800aa48: 4293 cmp r3, r2 800aa4a: d009 beq.n 800aa60 800aa4c: 687b ldr r3, [r7, #4] 800aa4e: 681b ldr r3, [r3, #0] 800aa50: 4a2d ldr r2, [pc, #180] @ (800ab08 ) 800aa52: 4293 cmp r3, r2 800aa54: d004 beq.n 800aa60 800aa56: 687b ldr r3, [r7, #4] 800aa58: 681b ldr r3, [r3, #0] 800aa5a: 4a2c ldr r2, [pc, #176] @ (800ab0c ) 800aa5c: 4293 cmp r3, r2 800aa5e: d101 bne.n 800aa64 800aa60: 2301 movs r3, #1 800aa62: e000 b.n 800aa66 800aa64: 2300 movs r3, #0 800aa66: 2b00 cmp r3, #0 800aa68: d024 beq.n 800aab4 { uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800aa6a: 687b ldr r3, [r7, #4] 800aa6c: 681b ldr r3, [r3, #0] 800aa6e: b2db uxtb r3, r3 800aa70: 3b10 subs r3, #16 800aa72: 4a27 ldr r2, [pc, #156] @ (800ab10 ) 800aa74: fba2 2303 umull r2, r3, r2, r3 800aa78: 091b lsrs r3, r3, #4 800aa7a: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; 800aa7c: 68fb ldr r3, [r7, #12] 800aa7e: f003 0307 and.w r3, r3, #7 800aa82: 4a24 ldr r2, [pc, #144] @ (800ab14 ) 800aa84: 5cd3 ldrb r3, [r2, r3] 800aa86: 461a mov r2, r3 800aa88: 687b ldr r3, [r7, #4] 800aa8a: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 800aa8c: 68fb ldr r3, [r7, #12] 800aa8e: 2b03 cmp r3, #3 800aa90: d908 bls.n 800aaa4 { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); 800aa92: 687b ldr r3, [r7, #4] 800aa94: 681b ldr r3, [r3, #0] 800aa96: 461a mov r2, r3 800aa98: 4b1f ldr r3, [pc, #124] @ (800ab18 ) 800aa9a: 4013 ands r3, r2 800aa9c: 1d1a adds r2, r3, #4 800aa9e: 687b ldr r3, [r7, #4] 800aaa0: 659a str r2, [r3, #88] @ 0x58 800aaa2: e00d b.n 800aac0 } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); 800aaa4: 687b ldr r3, [r7, #4] 800aaa6: 681b ldr r3, [r3, #0] 800aaa8: 461a mov r2, r3 800aaaa: 4b1b ldr r3, [pc, #108] @ (800ab18 ) 800aaac: 4013 ands r3, r2 800aaae: 687a ldr r2, [r7, #4] 800aab0: 6593 str r3, [r2, #88] @ 0x58 800aab2: e005 b.n 800aac0 } } else /* BDMA instance(s) */ { /* return pointer to ISR and IFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); 800aab4: 687b ldr r3, [r7, #4] 800aab6: 681b ldr r3, [r3, #0] 800aab8: f023 02ff bic.w r2, r3, #255 @ 0xff 800aabc: 687b ldr r3, [r7, #4] 800aabe: 659a str r2, [r3, #88] @ 0x58 } return hdma->StreamBaseAddress; 800aac0: 687b ldr r3, [r7, #4] 800aac2: 6d9b ldr r3, [r3, #88] @ 0x58 } 800aac4: 4618 mov r0, r3 800aac6: 3714 adds r7, #20 800aac8: 46bd mov sp, r7 800aaca: f85d 7b04 ldr.w r7, [sp], #4 800aace: 4770 bx lr 800aad0: 40020010 .word 0x40020010 800aad4: 40020028 .word 0x40020028 800aad8: 40020040 .word 0x40020040 800aadc: 40020058 .word 0x40020058 800aae0: 40020070 .word 0x40020070 800aae4: 40020088 .word 0x40020088 800aae8: 400200a0 .word 0x400200a0 800aaec: 400200b8 .word 0x400200b8 800aaf0: 40020410 .word 0x40020410 800aaf4: 40020428 .word 0x40020428 800aaf8: 40020440 .word 0x40020440 800aafc: 40020458 .word 0x40020458 800ab00: 40020470 .word 0x40020470 800ab04: 40020488 .word 0x40020488 800ab08: 400204a0 .word 0x400204a0 800ab0c: 400204b8 .word 0x400204b8 800ab10: aaaaaaab .word 0xaaaaaaab 800ab14: 0801a298 .word 0x0801a298 800ab18: fffffc00 .word 0xfffffc00 0800ab1c : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 800ab1c: b480 push {r7} 800ab1e: b085 sub sp, #20 800ab20: af00 add r7, sp, #0 800ab22: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800ab24: 2300 movs r3, #0 800ab26: 73fb strb r3, [r7, #15] /* Memory Data size equal to Byte */ if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 800ab28: 687b ldr r3, [r7, #4] 800ab2a: 699b ldr r3, [r3, #24] 800ab2c: 2b00 cmp r3, #0 800ab2e: d120 bne.n 800ab72 { switch (hdma->Init.FIFOThreshold) 800ab30: 687b ldr r3, [r7, #4] 800ab32: 6a9b ldr r3, [r3, #40] @ 0x28 800ab34: 2b03 cmp r3, #3 800ab36: d858 bhi.n 800abea 800ab38: a201 add r2, pc, #4 @ (adr r2, 800ab40 ) 800ab3a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ab3e: bf00 nop 800ab40: 0800ab51 .word 0x0800ab51 800ab44: 0800ab63 .word 0x0800ab63 800ab48: 0800ab51 .word 0x0800ab51 800ab4c: 0800abeb .word 0x0800abeb { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800ab50: 687b ldr r3, [r7, #4] 800ab52: 6adb ldr r3, [r3, #44] @ 0x2c 800ab54: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800ab58: 2b00 cmp r3, #0 800ab5a: d048 beq.n 800abee { status = HAL_ERROR; 800ab5c: 2301 movs r3, #1 800ab5e: 73fb strb r3, [r7, #15] } break; 800ab60: e045 b.n 800abee case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 800ab62: 687b ldr r3, [r7, #4] 800ab64: 6adb ldr r3, [r3, #44] @ 0x2c 800ab66: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800ab6a: d142 bne.n 800abf2 { status = HAL_ERROR; 800ab6c: 2301 movs r3, #1 800ab6e: 73fb strb r3, [r7, #15] } break; 800ab70: e03f b.n 800abf2 break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 800ab72: 687b ldr r3, [r7, #4] 800ab74: 699b ldr r3, [r3, #24] 800ab76: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800ab7a: d123 bne.n 800abc4 { switch (hdma->Init.FIFOThreshold) 800ab7c: 687b ldr r3, [r7, #4] 800ab7e: 6a9b ldr r3, [r3, #40] @ 0x28 800ab80: 2b03 cmp r3, #3 800ab82: d838 bhi.n 800abf6 800ab84: a201 add r2, pc, #4 @ (adr r2, 800ab8c ) 800ab86: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ab8a: bf00 nop 800ab8c: 0800ab9d .word 0x0800ab9d 800ab90: 0800aba3 .word 0x0800aba3 800ab94: 0800ab9d .word 0x0800ab9d 800ab98: 0800abb5 .word 0x0800abb5 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 800ab9c: 2301 movs r3, #1 800ab9e: 73fb strb r3, [r7, #15] break; 800aba0: e030 b.n 800ac04 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800aba2: 687b ldr r3, [r7, #4] 800aba4: 6adb ldr r3, [r3, #44] @ 0x2c 800aba6: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800abaa: 2b00 cmp r3, #0 800abac: d025 beq.n 800abfa { status = HAL_ERROR; 800abae: 2301 movs r3, #1 800abb0: 73fb strb r3, [r7, #15] } break; 800abb2: e022 b.n 800abfa case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 800abb4: 687b ldr r3, [r7, #4] 800abb6: 6adb ldr r3, [r3, #44] @ 0x2c 800abb8: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800abbc: d11f bne.n 800abfe { status = HAL_ERROR; 800abbe: 2301 movs r3, #1 800abc0: 73fb strb r3, [r7, #15] } break; 800abc2: e01c b.n 800abfe } /* Memory Data size equal to Word */ else { switch (hdma->Init.FIFOThreshold) 800abc4: 687b ldr r3, [r7, #4] 800abc6: 6a9b ldr r3, [r3, #40] @ 0x28 800abc8: 2b02 cmp r3, #2 800abca: d902 bls.n 800abd2 800abcc: 2b03 cmp r3, #3 800abce: d003 beq.n 800abd8 status = HAL_ERROR; } break; default: break; 800abd0: e018 b.n 800ac04 status = HAL_ERROR; 800abd2: 2301 movs r3, #1 800abd4: 73fb strb r3, [r7, #15] break; 800abd6: e015 b.n 800ac04 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800abd8: 687b ldr r3, [r7, #4] 800abda: 6adb ldr r3, [r3, #44] @ 0x2c 800abdc: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800abe0: 2b00 cmp r3, #0 800abe2: d00e beq.n 800ac02 status = HAL_ERROR; 800abe4: 2301 movs r3, #1 800abe6: 73fb strb r3, [r7, #15] break; 800abe8: e00b b.n 800ac02 break; 800abea: bf00 nop 800abec: e00a b.n 800ac04 break; 800abee: bf00 nop 800abf0: e008 b.n 800ac04 break; 800abf2: bf00 nop 800abf4: e006 b.n 800ac04 break; 800abf6: bf00 nop 800abf8: e004 b.n 800ac04 break; 800abfa: bf00 nop 800abfc: e002 b.n 800ac04 break; 800abfe: bf00 nop 800ac00: e000 b.n 800ac04 break; 800ac02: bf00 nop } } return status; 800ac04: 7bfb ldrb r3, [r7, #15] } 800ac06: 4618 mov r0, r3 800ac08: 3714 adds r7, #20 800ac0a: 46bd mov sp, r7 800ac0c: f85d 7b04 ldr.w r7, [sp], #4 800ac10: 4770 bx lr 800ac12: bf00 nop 0800ac14 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 800ac14: b480 push {r7} 800ac16: b085 sub sp, #20 800ac18: af00 add r7, sp, #0 800ac1a: 6078 str r0, [r7, #4] uint32_t stream_number; uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); 800ac1c: 687b ldr r3, [r7, #4] 800ac1e: 681b ldr r3, [r3, #0] 800ac20: 60bb str r3, [r7, #8] if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 800ac22: 687b ldr r3, [r7, #4] 800ac24: 681b ldr r3, [r3, #0] 800ac26: 4a38 ldr r2, [pc, #224] @ (800ad08 ) 800ac28: 4293 cmp r3, r2 800ac2a: d022 beq.n 800ac72 800ac2c: 687b ldr r3, [r7, #4] 800ac2e: 681b ldr r3, [r3, #0] 800ac30: 4a36 ldr r2, [pc, #216] @ (800ad0c ) 800ac32: 4293 cmp r3, r2 800ac34: d01d beq.n 800ac72 800ac36: 687b ldr r3, [r7, #4] 800ac38: 681b ldr r3, [r3, #0] 800ac3a: 4a35 ldr r2, [pc, #212] @ (800ad10 ) 800ac3c: 4293 cmp r3, r2 800ac3e: d018 beq.n 800ac72 800ac40: 687b ldr r3, [r7, #4] 800ac42: 681b ldr r3, [r3, #0] 800ac44: 4a33 ldr r2, [pc, #204] @ (800ad14 ) 800ac46: 4293 cmp r3, r2 800ac48: d013 beq.n 800ac72 800ac4a: 687b ldr r3, [r7, #4] 800ac4c: 681b ldr r3, [r3, #0] 800ac4e: 4a32 ldr r2, [pc, #200] @ (800ad18 ) 800ac50: 4293 cmp r3, r2 800ac52: d00e beq.n 800ac72 800ac54: 687b ldr r3, [r7, #4] 800ac56: 681b ldr r3, [r3, #0] 800ac58: 4a30 ldr r2, [pc, #192] @ (800ad1c ) 800ac5a: 4293 cmp r3, r2 800ac5c: d009 beq.n 800ac72 800ac5e: 687b ldr r3, [r7, #4] 800ac60: 681b ldr r3, [r3, #0] 800ac62: 4a2f ldr r2, [pc, #188] @ (800ad20 ) 800ac64: 4293 cmp r3, r2 800ac66: d004 beq.n 800ac72 800ac68: 687b ldr r3, [r7, #4] 800ac6a: 681b ldr r3, [r3, #0] 800ac6c: 4a2d ldr r2, [pc, #180] @ (800ad24 ) 800ac6e: 4293 cmp r3, r2 800ac70: d101 bne.n 800ac76 800ac72: 2301 movs r3, #1 800ac74: e000 b.n 800ac78 800ac76: 2300 movs r3, #0 800ac78: 2b00 cmp r3, #0 800ac7a: d01a beq.n 800acb2 { /* BDMA Channels are connected to DMAMUX2 channels */ stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; 800ac7c: 687b ldr r3, [r7, #4] 800ac7e: 681b ldr r3, [r3, #0] 800ac80: b2db uxtb r3, r3 800ac82: 3b08 subs r3, #8 800ac84: 4a28 ldr r2, [pc, #160] @ (800ad28 ) 800ac86: fba2 2303 umull r2, r3, r2, r3 800ac8a: 091b lsrs r3, r3, #4 800ac8c: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); 800ac8e: 68fa ldr r2, [r7, #12] 800ac90: 4b26 ldr r3, [pc, #152] @ (800ad2c ) 800ac92: 4413 add r3, r2 800ac94: 009b lsls r3, r3, #2 800ac96: 461a mov r2, r3 800ac98: 687b ldr r3, [r7, #4] 800ac9a: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; 800ac9c: 687b ldr r3, [r7, #4] 800ac9e: 4a24 ldr r2, [pc, #144] @ (800ad30 ) 800aca0: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800aca2: 68fb ldr r3, [r7, #12] 800aca4: f003 031f and.w r3, r3, #31 800aca8: 2201 movs r2, #1 800acaa: 409a lsls r2, r3 800acac: 687b ldr r3, [r7, #4] 800acae: 669a str r2, [r3, #104] @ 0x68 } hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); } } 800acb0: e024 b.n 800acfc stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800acb2: 687b ldr r3, [r7, #4] 800acb4: 681b ldr r3, [r3, #0] 800acb6: b2db uxtb r3, r3 800acb8: 3b10 subs r3, #16 800acba: 4a1e ldr r2, [pc, #120] @ (800ad34 ) 800acbc: fba2 2303 umull r2, r3, r2, r3 800acc0: 091b lsrs r3, r3, #4 800acc2: 60fb str r3, [r7, #12] if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ 800acc4: 68bb ldr r3, [r7, #8] 800acc6: 4a1c ldr r2, [pc, #112] @ (800ad38 ) 800acc8: 4293 cmp r3, r2 800acca: d806 bhi.n 800acda 800accc: 68bb ldr r3, [r7, #8] 800acce: 4a1b ldr r2, [pc, #108] @ (800ad3c ) 800acd0: 4293 cmp r3, r2 800acd2: d902 bls.n 800acda stream_number += 8U; 800acd4: 68fb ldr r3, [r7, #12] 800acd6: 3308 adds r3, #8 800acd8: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); 800acda: 68fa ldr r2, [r7, #12] 800acdc: 4b18 ldr r3, [pc, #96] @ (800ad40 ) 800acde: 4413 add r3, r2 800ace0: 009b lsls r3, r3, #2 800ace2: 461a mov r2, r3 800ace4: 687b ldr r3, [r7, #4] 800ace6: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 800ace8: 687b ldr r3, [r7, #4] 800acea: 4a16 ldr r2, [pc, #88] @ (800ad44 ) 800acec: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800acee: 68fb ldr r3, [r7, #12] 800acf0: f003 031f and.w r3, r3, #31 800acf4: 2201 movs r2, #1 800acf6: 409a lsls r2, r3 800acf8: 687b ldr r3, [r7, #4] 800acfa: 669a str r2, [r3, #104] @ 0x68 } 800acfc: bf00 nop 800acfe: 3714 adds r7, #20 800ad00: 46bd mov sp, r7 800ad02: f85d 7b04 ldr.w r7, [sp], #4 800ad06: 4770 bx lr 800ad08: 58025408 .word 0x58025408 800ad0c: 5802541c .word 0x5802541c 800ad10: 58025430 .word 0x58025430 800ad14: 58025444 .word 0x58025444 800ad18: 58025458 .word 0x58025458 800ad1c: 5802546c .word 0x5802546c 800ad20: 58025480 .word 0x58025480 800ad24: 58025494 .word 0x58025494 800ad28: cccccccd .word 0xcccccccd 800ad2c: 16009600 .word 0x16009600 800ad30: 58025880 .word 0x58025880 800ad34: aaaaaaab .word 0xaaaaaaab 800ad38: 400204b8 .word 0x400204b8 800ad3c: 4002040f .word 0x4002040f 800ad40: 10008200 .word 0x10008200 800ad44: 40020880 .word 0x40020880 0800ad48 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 800ad48: b480 push {r7} 800ad4a: b085 sub sp, #20 800ad4c: af00 add r7, sp, #0 800ad4e: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 800ad50: 687b ldr r3, [r7, #4] 800ad52: 685b ldr r3, [r3, #4] 800ad54: b2db uxtb r3, r3 800ad56: 60fb str r3, [r7, #12] if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) 800ad58: 68fb ldr r3, [r7, #12] 800ad5a: 2b00 cmp r3, #0 800ad5c: d04a beq.n 800adf4 800ad5e: 68fb ldr r3, [r7, #12] 800ad60: 2b08 cmp r3, #8 800ad62: d847 bhi.n 800adf4 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 800ad64: 687b ldr r3, [r7, #4] 800ad66: 681b ldr r3, [r3, #0] 800ad68: 4a25 ldr r2, [pc, #148] @ (800ae00 ) 800ad6a: 4293 cmp r3, r2 800ad6c: d022 beq.n 800adb4 800ad6e: 687b ldr r3, [r7, #4] 800ad70: 681b ldr r3, [r3, #0] 800ad72: 4a24 ldr r2, [pc, #144] @ (800ae04 ) 800ad74: 4293 cmp r3, r2 800ad76: d01d beq.n 800adb4 800ad78: 687b ldr r3, [r7, #4] 800ad7a: 681b ldr r3, [r3, #0] 800ad7c: 4a22 ldr r2, [pc, #136] @ (800ae08 ) 800ad7e: 4293 cmp r3, r2 800ad80: d018 beq.n 800adb4 800ad82: 687b ldr r3, [r7, #4] 800ad84: 681b ldr r3, [r3, #0] 800ad86: 4a21 ldr r2, [pc, #132] @ (800ae0c ) 800ad88: 4293 cmp r3, r2 800ad8a: d013 beq.n 800adb4 800ad8c: 687b ldr r3, [r7, #4] 800ad8e: 681b ldr r3, [r3, #0] 800ad90: 4a1f ldr r2, [pc, #124] @ (800ae10 ) 800ad92: 4293 cmp r3, r2 800ad94: d00e beq.n 800adb4 800ad96: 687b ldr r3, [r7, #4] 800ad98: 681b ldr r3, [r3, #0] 800ad9a: 4a1e ldr r2, [pc, #120] @ (800ae14 ) 800ad9c: 4293 cmp r3, r2 800ad9e: d009 beq.n 800adb4 800ada0: 687b ldr r3, [r7, #4] 800ada2: 681b ldr r3, [r3, #0] 800ada4: 4a1c ldr r2, [pc, #112] @ (800ae18 ) 800ada6: 4293 cmp r3, r2 800ada8: d004 beq.n 800adb4 800adaa: 687b ldr r3, [r7, #4] 800adac: 681b ldr r3, [r3, #0] 800adae: 4a1b ldr r2, [pc, #108] @ (800ae1c ) 800adb0: 4293 cmp r3, r2 800adb2: d101 bne.n 800adb8 800adb4: 2301 movs r3, #1 800adb6: e000 b.n 800adba 800adb8: 2300 movs r3, #0 800adba: 2b00 cmp r3, #0 800adbc: d00a beq.n 800add4 { /* BDMA Channels are connected to DMAMUX2 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); 800adbe: 68fa ldr r2, [r7, #12] 800adc0: 4b17 ldr r3, [pc, #92] @ (800ae20 ) 800adc2: 4413 add r3, r2 800adc4: 009b lsls r3, r3, #2 800adc6: 461a mov r2, r3 800adc8: 687b ldr r3, [r7, #4] 800adca: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; 800adcc: 687b ldr r3, [r7, #4] 800adce: 4a15 ldr r2, [pc, #84] @ (800ae24 ) 800add0: 671a str r2, [r3, #112] @ 0x70 800add2: e009 b.n 800ade8 } else { /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 800add4: 68fa ldr r2, [r7, #12] 800add6: 4b14 ldr r3, [pc, #80] @ (800ae28 ) 800add8: 4413 add r3, r2 800adda: 009b lsls r3, r3, #2 800addc: 461a mov r2, r3 800adde: 687b ldr r3, [r7, #4] 800ade0: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 800ade2: 687b ldr r3, [r7, #4] 800ade4: 4a11 ldr r2, [pc, #68] @ (800ae2c ) 800ade6: 671a str r2, [r3, #112] @ 0x70 } hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); 800ade8: 68fb ldr r3, [r7, #12] 800adea: 3b01 subs r3, #1 800adec: 2201 movs r2, #1 800adee: 409a lsls r2, r3 800adf0: 687b ldr r3, [r7, #4] 800adf2: 675a str r2, [r3, #116] @ 0x74 } } 800adf4: bf00 nop 800adf6: 3714 adds r7, #20 800adf8: 46bd mov sp, r7 800adfa: f85d 7b04 ldr.w r7, [sp], #4 800adfe: 4770 bx lr 800ae00: 58025408 .word 0x58025408 800ae04: 5802541c .word 0x5802541c 800ae08: 58025430 .word 0x58025430 800ae0c: 58025444 .word 0x58025444 800ae10: 58025458 .word 0x58025458 800ae14: 5802546c .word 0x5802546c 800ae18: 58025480 .word 0x58025480 800ae1c: 58025494 .word 0x58025494 800ae20: 1600963f .word 0x1600963f 800ae24: 58025940 .word 0x58025940 800ae28: 1000823f .word 0x1000823f 800ae2c: 40020940 .word 0x40020940 0800ae30 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800ae30: b480 push {r7} 800ae32: b089 sub sp, #36 @ 0x24 800ae34: af00 add r7, sp, #0 800ae36: 6078 str r0, [r7, #4] 800ae38: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 800ae3a: 2300 movs r3, #0 800ae3c: 61fb str r3, [r7, #28] EXTI_Core_TypeDef *EXTI_CurrentCPU; #if defined(DUAL_CORE) && defined(CORE_CM4) EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ #else EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ 800ae3e: 4b89 ldr r3, [pc, #548] @ (800b064 ) 800ae40: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 800ae42: e194 b.n 800b16e { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 800ae44: 683b ldr r3, [r7, #0] 800ae46: 681a ldr r2, [r3, #0] 800ae48: 2101 movs r1, #1 800ae4a: 69fb ldr r3, [r7, #28] 800ae4c: fa01 f303 lsl.w r3, r1, r3 800ae50: 4013 ands r3, r2 800ae52: 613b str r3, [r7, #16] if (iocurrent != 0x00U) 800ae54: 693b ldr r3, [r7, #16] 800ae56: 2b00 cmp r3, #0 800ae58: f000 8186 beq.w 800b168 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 800ae5c: 683b ldr r3, [r7, #0] 800ae5e: 685b ldr r3, [r3, #4] 800ae60: f003 0303 and.w r3, r3, #3 800ae64: 2b01 cmp r3, #1 800ae66: d005 beq.n 800ae74 800ae68: 683b ldr r3, [r7, #0] 800ae6a: 685b ldr r3, [r3, #4] 800ae6c: f003 0303 and.w r3, r3, #3 800ae70: 2b02 cmp r3, #2 800ae72: d130 bne.n 800aed6 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 800ae74: 687b ldr r3, [r7, #4] 800ae76: 689b ldr r3, [r3, #8] 800ae78: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 800ae7a: 69fb ldr r3, [r7, #28] 800ae7c: 005b lsls r3, r3, #1 800ae7e: 2203 movs r2, #3 800ae80: fa02 f303 lsl.w r3, r2, r3 800ae84: 43db mvns r3, r3 800ae86: 69ba ldr r2, [r7, #24] 800ae88: 4013 ands r3, r2 800ae8a: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 800ae8c: 683b ldr r3, [r7, #0] 800ae8e: 68da ldr r2, [r3, #12] 800ae90: 69fb ldr r3, [r7, #28] 800ae92: 005b lsls r3, r3, #1 800ae94: fa02 f303 lsl.w r3, r2, r3 800ae98: 69ba ldr r2, [r7, #24] 800ae9a: 4313 orrs r3, r2 800ae9c: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 800ae9e: 687b ldr r3, [r7, #4] 800aea0: 69ba ldr r2, [r7, #24] 800aea2: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 800aea4: 687b ldr r3, [r7, #4] 800aea6: 685b ldr r3, [r3, #4] 800aea8: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT0 << position) ; 800aeaa: 2201 movs r2, #1 800aeac: 69fb ldr r3, [r7, #28] 800aeae: fa02 f303 lsl.w r3, r2, r3 800aeb2: 43db mvns r3, r3 800aeb4: 69ba ldr r2, [r7, #24] 800aeb6: 4013 ands r3, r2 800aeb8: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 800aeba: 683b ldr r3, [r7, #0] 800aebc: 685b ldr r3, [r3, #4] 800aebe: 091b lsrs r3, r3, #4 800aec0: f003 0201 and.w r2, r3, #1 800aec4: 69fb ldr r3, [r7, #28] 800aec6: fa02 f303 lsl.w r3, r2, r3 800aeca: 69ba ldr r2, [r7, #24] 800aecc: 4313 orrs r3, r2 800aece: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 800aed0: 687b ldr r3, [r7, #4] 800aed2: 69ba ldr r2, [r7, #24] 800aed4: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 800aed6: 683b ldr r3, [r7, #0] 800aed8: 685b ldr r3, [r3, #4] 800aeda: f003 0303 and.w r3, r3, #3 800aede: 2b03 cmp r3, #3 800aee0: d017 beq.n 800af12 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 800aee2: 687b ldr r3, [r7, #4] 800aee4: 68db ldr r3, [r3, #12] 800aee6: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 800aee8: 69fb ldr r3, [r7, #28] 800aeea: 005b lsls r3, r3, #1 800aeec: 2203 movs r2, #3 800aeee: fa02 f303 lsl.w r3, r2, r3 800aef2: 43db mvns r3, r3 800aef4: 69ba ldr r2, [r7, #24] 800aef6: 4013 ands r3, r2 800aef8: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 800aefa: 683b ldr r3, [r7, #0] 800aefc: 689a ldr r2, [r3, #8] 800aefe: 69fb ldr r3, [r7, #28] 800af00: 005b lsls r3, r3, #1 800af02: fa02 f303 lsl.w r3, r2, r3 800af06: 69ba ldr r2, [r7, #24] 800af08: 4313 orrs r3, r2 800af0a: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 800af0c: 687b ldr r3, [r7, #4] 800af0e: 69ba ldr r2, [r7, #24] 800af10: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 800af12: 683b ldr r3, [r7, #0] 800af14: 685b ldr r3, [r3, #4] 800af16: f003 0303 and.w r3, r3, #3 800af1a: 2b02 cmp r3, #2 800af1c: d123 bne.n 800af66 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 800af1e: 69fb ldr r3, [r7, #28] 800af20: 08da lsrs r2, r3, #3 800af22: 687b ldr r3, [r7, #4] 800af24: 3208 adds r2, #8 800af26: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800af2a: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 800af2c: 69fb ldr r3, [r7, #28] 800af2e: f003 0307 and.w r3, r3, #7 800af32: 009b lsls r3, r3, #2 800af34: 220f movs r2, #15 800af36: fa02 f303 lsl.w r3, r2, r3 800af3a: 43db mvns r3, r3 800af3c: 69ba ldr r2, [r7, #24] 800af3e: 4013 ands r3, r2 800af40: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 800af42: 683b ldr r3, [r7, #0] 800af44: 691a ldr r2, [r3, #16] 800af46: 69fb ldr r3, [r7, #28] 800af48: f003 0307 and.w r3, r3, #7 800af4c: 009b lsls r3, r3, #2 800af4e: fa02 f303 lsl.w r3, r2, r3 800af52: 69ba ldr r2, [r7, #24] 800af54: 4313 orrs r3, r2 800af56: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 800af58: 69fb ldr r3, [r7, #28] 800af5a: 08da lsrs r2, r3, #3 800af5c: 687b ldr r3, [r7, #4] 800af5e: 3208 adds r2, #8 800af60: 69b9 ldr r1, [r7, #24] 800af62: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 800af66: 687b ldr r3, [r7, #4] 800af68: 681b ldr r3, [r3, #0] 800af6a: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 800af6c: 69fb ldr r3, [r7, #28] 800af6e: 005b lsls r3, r3, #1 800af70: 2203 movs r2, #3 800af72: fa02 f303 lsl.w r3, r2, r3 800af76: 43db mvns r3, r3 800af78: 69ba ldr r2, [r7, #24] 800af7a: 4013 ands r3, r2 800af7c: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 800af7e: 683b ldr r3, [r7, #0] 800af80: 685b ldr r3, [r3, #4] 800af82: f003 0203 and.w r2, r3, #3 800af86: 69fb ldr r3, [r7, #28] 800af88: 005b lsls r3, r3, #1 800af8a: fa02 f303 lsl.w r3, r2, r3 800af8e: 69ba ldr r2, [r7, #24] 800af90: 4313 orrs r3, r2 800af92: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 800af94: 687b ldr r3, [r7, #4] 800af96: 69ba ldr r2, [r7, #24] 800af98: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 800af9a: 683b ldr r3, [r7, #0] 800af9c: 685b ldr r3, [r3, #4] 800af9e: f403 3340 and.w r3, r3, #196608 @ 0x30000 800afa2: 2b00 cmp r3, #0 800afa4: f000 80e0 beq.w 800b168 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800afa8: 4b2f ldr r3, [pc, #188] @ (800b068 ) 800afaa: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 800afae: 4a2e ldr r2, [pc, #184] @ (800b068 ) 800afb0: f043 0302 orr.w r3, r3, #2 800afb4: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 800afb8: 4b2b ldr r3, [pc, #172] @ (800b068 ) 800afba: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 800afbe: f003 0302 and.w r3, r3, #2 800afc2: 60fb str r3, [r7, #12] 800afc4: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 800afc6: 4a29 ldr r2, [pc, #164] @ (800b06c ) 800afc8: 69fb ldr r3, [r7, #28] 800afca: 089b lsrs r3, r3, #2 800afcc: 3302 adds r3, #2 800afce: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800afd2: 61bb str r3, [r7, #24] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 800afd4: 69fb ldr r3, [r7, #28] 800afd6: f003 0303 and.w r3, r3, #3 800afda: 009b lsls r3, r3, #2 800afdc: 220f movs r2, #15 800afde: fa02 f303 lsl.w r3, r2, r3 800afe2: 43db mvns r3, r3 800afe4: 69ba ldr r2, [r7, #24] 800afe6: 4013 ands r3, r2 800afe8: 61bb str r3, [r7, #24] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 800afea: 687b ldr r3, [r7, #4] 800afec: 4a20 ldr r2, [pc, #128] @ (800b070 ) 800afee: 4293 cmp r3, r2 800aff0: d052 beq.n 800b098 800aff2: 687b ldr r3, [r7, #4] 800aff4: 4a1f ldr r2, [pc, #124] @ (800b074 ) 800aff6: 4293 cmp r3, r2 800aff8: d031 beq.n 800b05e 800affa: 687b ldr r3, [r7, #4] 800affc: 4a1e ldr r2, [pc, #120] @ (800b078 ) 800affe: 4293 cmp r3, r2 800b000: d02b beq.n 800b05a 800b002: 687b ldr r3, [r7, #4] 800b004: 4a1d ldr r2, [pc, #116] @ (800b07c ) 800b006: 4293 cmp r3, r2 800b008: d025 beq.n 800b056 800b00a: 687b ldr r3, [r7, #4] 800b00c: 4a1c ldr r2, [pc, #112] @ (800b080 ) 800b00e: 4293 cmp r3, r2 800b010: d01f beq.n 800b052 800b012: 687b ldr r3, [r7, #4] 800b014: 4a1b ldr r2, [pc, #108] @ (800b084 ) 800b016: 4293 cmp r3, r2 800b018: d019 beq.n 800b04e 800b01a: 687b ldr r3, [r7, #4] 800b01c: 4a1a ldr r2, [pc, #104] @ (800b088 ) 800b01e: 4293 cmp r3, r2 800b020: d013 beq.n 800b04a 800b022: 687b ldr r3, [r7, #4] 800b024: 4a19 ldr r2, [pc, #100] @ (800b08c ) 800b026: 4293 cmp r3, r2 800b028: d00d beq.n 800b046 800b02a: 687b ldr r3, [r7, #4] 800b02c: 4a18 ldr r2, [pc, #96] @ (800b090 ) 800b02e: 4293 cmp r3, r2 800b030: d007 beq.n 800b042 800b032: 687b ldr r3, [r7, #4] 800b034: 4a17 ldr r2, [pc, #92] @ (800b094 ) 800b036: 4293 cmp r3, r2 800b038: d101 bne.n 800b03e 800b03a: 2309 movs r3, #9 800b03c: e02d b.n 800b09a 800b03e: 230a movs r3, #10 800b040: e02b b.n 800b09a 800b042: 2308 movs r3, #8 800b044: e029 b.n 800b09a 800b046: 2307 movs r3, #7 800b048: e027 b.n 800b09a 800b04a: 2306 movs r3, #6 800b04c: e025 b.n 800b09a 800b04e: 2305 movs r3, #5 800b050: e023 b.n 800b09a 800b052: 2304 movs r3, #4 800b054: e021 b.n 800b09a 800b056: 2303 movs r3, #3 800b058: e01f b.n 800b09a 800b05a: 2302 movs r3, #2 800b05c: e01d b.n 800b09a 800b05e: 2301 movs r3, #1 800b060: e01b b.n 800b09a 800b062: bf00 nop 800b064: 58000080 .word 0x58000080 800b068: 58024400 .word 0x58024400 800b06c: 58000400 .word 0x58000400 800b070: 58020000 .word 0x58020000 800b074: 58020400 .word 0x58020400 800b078: 58020800 .word 0x58020800 800b07c: 58020c00 .word 0x58020c00 800b080: 58021000 .word 0x58021000 800b084: 58021400 .word 0x58021400 800b088: 58021800 .word 0x58021800 800b08c: 58021c00 .word 0x58021c00 800b090: 58022000 .word 0x58022000 800b094: 58022400 .word 0x58022400 800b098: 2300 movs r3, #0 800b09a: 69fa ldr r2, [r7, #28] 800b09c: f002 0203 and.w r2, r2, #3 800b0a0: 0092 lsls r2, r2, #2 800b0a2: 4093 lsls r3, r2 800b0a4: 69ba ldr r2, [r7, #24] 800b0a6: 4313 orrs r3, r2 800b0a8: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 800b0aa: 4938 ldr r1, [pc, #224] @ (800b18c ) 800b0ac: 69fb ldr r3, [r7, #28] 800b0ae: 089b lsrs r3, r3, #2 800b0b0: 3302 adds r3, #2 800b0b2: 69ba ldr r2, [r7, #24] 800b0b4: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 800b0b8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b0bc: 681b ldr r3, [r3, #0] 800b0be: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b0c0: 693b ldr r3, [r7, #16] 800b0c2: 43db mvns r3, r3 800b0c4: 69ba ldr r2, [r7, #24] 800b0c6: 4013 ands r3, r2 800b0c8: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 800b0ca: 683b ldr r3, [r7, #0] 800b0cc: 685b ldr r3, [r3, #4] 800b0ce: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800b0d2: 2b00 cmp r3, #0 800b0d4: d003 beq.n 800b0de { temp |= iocurrent; 800b0d6: 69ba ldr r2, [r7, #24] 800b0d8: 693b ldr r3, [r7, #16] 800b0da: 4313 orrs r3, r2 800b0dc: 61bb str r3, [r7, #24] } EXTI->RTSR1 = temp; 800b0de: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b0e2: 69bb ldr r3, [r7, #24] 800b0e4: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 800b0e6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b0ea: 685b ldr r3, [r3, #4] 800b0ec: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b0ee: 693b ldr r3, [r7, #16] 800b0f0: 43db mvns r3, r3 800b0f2: 69ba ldr r2, [r7, #24] 800b0f4: 4013 ands r3, r2 800b0f6: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 800b0f8: 683b ldr r3, [r7, #0] 800b0fa: 685b ldr r3, [r3, #4] 800b0fc: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800b100: 2b00 cmp r3, #0 800b102: d003 beq.n 800b10c { temp |= iocurrent; 800b104: 69ba ldr r2, [r7, #24] 800b106: 693b ldr r3, [r7, #16] 800b108: 4313 orrs r3, r2 800b10a: 61bb str r3, [r7, #24] } EXTI->FTSR1 = temp; 800b10c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b110: 69bb ldr r3, [r7, #24] 800b112: 6053 str r3, [r2, #4] temp = EXTI_CurrentCPU->EMR1; 800b114: 697b ldr r3, [r7, #20] 800b116: 685b ldr r3, [r3, #4] 800b118: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b11a: 693b ldr r3, [r7, #16] 800b11c: 43db mvns r3, r3 800b11e: 69ba ldr r2, [r7, #24] 800b120: 4013 ands r3, r2 800b122: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 800b124: 683b ldr r3, [r7, #0] 800b126: 685b ldr r3, [r3, #4] 800b128: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b12c: 2b00 cmp r3, #0 800b12e: d003 beq.n 800b138 { temp |= iocurrent; 800b130: 69ba ldr r2, [r7, #24] 800b132: 693b ldr r3, [r7, #16] 800b134: 4313 orrs r3, r2 800b136: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->EMR1 = temp; 800b138: 697b ldr r3, [r7, #20] 800b13a: 69ba ldr r2, [r7, #24] 800b13c: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 800b13e: 697b ldr r3, [r7, #20] 800b140: 681b ldr r3, [r3, #0] 800b142: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b144: 693b ldr r3, [r7, #16] 800b146: 43db mvns r3, r3 800b148: 69ba ldr r2, [r7, #24] 800b14a: 4013 ands r3, r2 800b14c: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 800b14e: 683b ldr r3, [r7, #0] 800b150: 685b ldr r3, [r3, #4] 800b152: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b156: 2b00 cmp r3, #0 800b158: d003 beq.n 800b162 { temp |= iocurrent; 800b15a: 69ba ldr r2, [r7, #24] 800b15c: 693b ldr r3, [r7, #16] 800b15e: 4313 orrs r3, r2 800b160: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->IMR1 = temp; 800b162: 697b ldr r3, [r7, #20] 800b164: 69ba ldr r2, [r7, #24] 800b166: 601a str r2, [r3, #0] } } position++; 800b168: 69fb ldr r3, [r7, #28] 800b16a: 3301 adds r3, #1 800b16c: 61fb str r3, [r7, #28] while (((GPIO_Init->Pin) >> position) != 0x00U) 800b16e: 683b ldr r3, [r7, #0] 800b170: 681a ldr r2, [r3, #0] 800b172: 69fb ldr r3, [r7, #28] 800b174: fa22 f303 lsr.w r3, r2, r3 800b178: 2b00 cmp r3, #0 800b17a: f47f ae63 bne.w 800ae44 } } 800b17e: bf00 nop 800b180: bf00 nop 800b182: 3724 adds r7, #36 @ 0x24 800b184: 46bd mov sp, r7 800b186: f85d 7b04 ldr.w r7, [sp], #4 800b18a: 4770 bx lr 800b18c: 58000400 .word 0x58000400 0800b190 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800b190: b480 push {r7} 800b192: b085 sub sp, #20 800b194: af00 add r7, sp, #0 800b196: 6078 str r0, [r7, #4] 800b198: 460b mov r3, r1 800b19a: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0x00U) 800b19c: 687b ldr r3, [r7, #4] 800b19e: 691a ldr r2, [r3, #16] 800b1a0: 887b ldrh r3, [r7, #2] 800b1a2: 4013 ands r3, r2 800b1a4: 2b00 cmp r3, #0 800b1a6: d002 beq.n 800b1ae { bitstatus = GPIO_PIN_SET; 800b1a8: 2301 movs r3, #1 800b1aa: 73fb strb r3, [r7, #15] 800b1ac: e001 b.n 800b1b2 } else { bitstatus = GPIO_PIN_RESET; 800b1ae: 2300 movs r3, #0 800b1b0: 73fb strb r3, [r7, #15] } return bitstatus; 800b1b2: 7bfb ldrb r3, [r7, #15] } 800b1b4: 4618 mov r0, r3 800b1b6: 3714 adds r7, #20 800b1b8: 46bd mov sp, r7 800b1ba: f85d 7b04 ldr.w r7, [sp], #4 800b1be: 4770 bx lr 0800b1c0 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800b1c0: b480 push {r7} 800b1c2: b083 sub sp, #12 800b1c4: af00 add r7, sp, #0 800b1c6: 6078 str r0, [r7, #4] 800b1c8: 460b mov r3, r1 800b1ca: 807b strh r3, [r7, #2] 800b1cc: 4613 mov r3, r2 800b1ce: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800b1d0: 787b ldrb r3, [r7, #1] 800b1d2: 2b00 cmp r3, #0 800b1d4: d003 beq.n 800b1de { GPIOx->BSRR = GPIO_Pin; 800b1d6: 887a ldrh r2, [r7, #2] 800b1d8: 687b ldr r3, [r7, #4] 800b1da: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; } } 800b1dc: e003 b.n 800b1e6 GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 800b1de: 887b ldrh r3, [r7, #2] 800b1e0: 041a lsls r2, r3, #16 800b1e2: 687b ldr r3, [r7, #4] 800b1e4: 619a str r2, [r3, #24] } 800b1e6: bf00 nop 800b1e8: 370c adds r7, #12 800b1ea: 46bd mov sp, r7 800b1ec: f85d 7b04 ldr.w r7, [sp], #4 800b1f0: 4770 bx lr 0800b1f2 : * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral. * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800b1f2: b480 push {r7} 800b1f4: b085 sub sp, #20 800b1f6: af00 add r7, sp, #0 800b1f8: 6078 str r0, [r7, #4] 800b1fa: 460b mov r3, r1 800b1fc: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; 800b1fe: 687b ldr r3, [r7, #4] 800b200: 695b ldr r3, [r3, #20] 800b202: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 800b204: 887a ldrh r2, [r7, #2] 800b206: 68fb ldr r3, [r7, #12] 800b208: 4013 ands r3, r2 800b20a: 041a lsls r2, r3, #16 800b20c: 68fb ldr r3, [r7, #12] 800b20e: 43d9 mvns r1, r3 800b210: 887b ldrh r3, [r7, #2] 800b212: 400b ands r3, r1 800b214: 431a orrs r2, r3 800b216: 687b ldr r3, [r7, #4] 800b218: 619a str r2, [r3, #24] } 800b21a: bf00 nop 800b21c: 3714 adds r7, #20 800b21e: 46bd mov sp, r7 800b220: f85d 7b04 ldr.w r7, [sp], #4 800b224: 4770 bx lr 0800b226 : * @brief Handle EXTI interrupt request. * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 800b226: b580 push {r7, lr} 800b228: b082 sub sp, #8 800b22a: af00 add r7, sp, #0 800b22c: 4603 mov r3, r0 800b22e: 80fb strh r3, [r7, #6] __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); } #else /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U) 800b230: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b234: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 800b238: 88fb ldrh r3, [r7, #6] 800b23a: 4013 ands r3, r2 800b23c: 2b00 cmp r3, #0 800b23e: d008 beq.n 800b252 { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 800b240: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b244: 88fb ldrh r3, [r7, #6] 800b246: f8c2 3088 str.w r3, [r2, #136] @ 0x88 HAL_GPIO_EXTI_Callback(GPIO_Pin); 800b24a: 88fb ldrh r3, [r7, #6] 800b24c: 4618 mov r0, r3 800b24e: f7f5 fa6d bl 800072c } #endif } 800b252: bf00 nop 800b254: 3708 adds r7, #8 800b256: 46bd mov sp, r7 800b258: bd80 pop {r7, pc} 0800b25a : * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { 800b25a: b580 push {r7, lr} 800b25c: b084 sub sp, #16 800b25e: af00 add r7, sp, #0 800b260: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the IWDG handle allocation */ if (hiwdg == NULL) 800b262: 687b ldr r3, [r7, #4] 800b264: 2b00 cmp r3, #0 800b266: d101 bne.n 800b26c { return HAL_ERROR; 800b268: 2301 movs r3, #1 800b26a: e041 b.n 800b2f0 assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); /* Enable IWDG. LSI is turned on automatically */ __HAL_IWDG_START(hiwdg); 800b26c: 687b ldr r3, [r7, #4] 800b26e: 681b ldr r3, [r3, #0] 800b270: f64c 42cc movw r2, #52428 @ 0xcccc 800b274: 601a str r2, [r3, #0] /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing 0x5555 in KR */ IWDG_ENABLE_WRITE_ACCESS(hiwdg); 800b276: 687b ldr r3, [r7, #4] 800b278: 681b ldr r3, [r3, #0] 800b27a: f245 5255 movw r2, #21845 @ 0x5555 800b27e: 601a str r2, [r3, #0] /* Write to IWDG registers the Prescaler & Reload values to work with */ hiwdg->Instance->PR = hiwdg->Init.Prescaler; 800b280: 687b ldr r3, [r7, #4] 800b282: 681b ldr r3, [r3, #0] 800b284: 687a ldr r2, [r7, #4] 800b286: 6852 ldr r2, [r2, #4] 800b288: 605a str r2, [r3, #4] hiwdg->Instance->RLR = hiwdg->Init.Reload; 800b28a: 687b ldr r3, [r7, #4] 800b28c: 681b ldr r3, [r3, #0] 800b28e: 687a ldr r2, [r7, #4] 800b290: 6892 ldr r2, [r2, #8] 800b292: 609a str r2, [r3, #8] /* Check pending flag, if previous update not done, return timeout */ tickstart = HAL_GetTick(); 800b294: f7fa fb02 bl 800589c 800b298: 60f8 str r0, [r7, #12] /* Wait for register to be updated */ while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 800b29a: e00f b.n 800b2bc { if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) 800b29c: f7fa fafe bl 800589c 800b2a0: 4602 mov r2, r0 800b2a2: 68fb ldr r3, [r7, #12] 800b2a4: 1ad3 subs r3, r2, r3 800b2a6: 2b31 cmp r3, #49 @ 0x31 800b2a8: d908 bls.n 800b2bc { if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 800b2aa: 687b ldr r3, [r7, #4] 800b2ac: 681b ldr r3, [r3, #0] 800b2ae: 68db ldr r3, [r3, #12] 800b2b0: f003 0307 and.w r3, r3, #7 800b2b4: 2b00 cmp r3, #0 800b2b6: d001 beq.n 800b2bc { return HAL_TIMEOUT; 800b2b8: 2303 movs r3, #3 800b2ba: e019 b.n 800b2f0 while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 800b2bc: 687b ldr r3, [r7, #4] 800b2be: 681b ldr r3, [r3, #0] 800b2c0: 68db ldr r3, [r3, #12] 800b2c2: f003 0307 and.w r3, r3, #7 800b2c6: 2b00 cmp r3, #0 800b2c8: d1e8 bne.n 800b29c } } /* If window parameter is different than current value, modify window register */ if (hiwdg->Instance->WINR != hiwdg->Init.Window) 800b2ca: 687b ldr r3, [r7, #4] 800b2cc: 681b ldr r3, [r3, #0] 800b2ce: 691a ldr r2, [r3, #16] 800b2d0: 687b ldr r3, [r7, #4] 800b2d2: 68db ldr r3, [r3, #12] 800b2d4: 429a cmp r2, r3 800b2d6: d005 beq.n 800b2e4 { /* Write to IWDG WINR the IWDG_Window value to compare with. In any case, even if window feature is disabled, Watchdog will be reloaded by writing windows register */ hiwdg->Instance->WINR = hiwdg->Init.Window; 800b2d8: 687b ldr r3, [r7, #4] 800b2da: 681b ldr r3, [r3, #0] 800b2dc: 687a ldr r2, [r7, #4] 800b2de: 68d2 ldr r2, [r2, #12] 800b2e0: 611a str r2, [r3, #16] 800b2e2: e004 b.n 800b2ee } else { /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); 800b2e4: 687b ldr r3, [r7, #4] 800b2e6: 681b ldr r3, [r3, #0] 800b2e8: f64a 22aa movw r2, #43690 @ 0xaaaa 800b2ec: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 800b2ee: 2300 movs r3, #0 } 800b2f0: 4618 mov r0, r3 800b2f2: 3710 adds r7, #16 800b2f4: 46bd mov sp, r7 800b2f6: bd80 pop {r7, pc} 0800b2f8 : * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) { 800b2f8: b480 push {r7} 800b2fa: b083 sub sp, #12 800b2fc: af00 add r7, sp, #0 800b2fe: 6078 str r0, [r7, #4] /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); 800b300: 687b ldr r3, [r7, #4] 800b302: 681b ldr r3, [r3, #0] 800b304: f64a 22aa movw r2, #43690 @ 0xaaaa 800b308: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800b30a: 2300 movs r3, #0 } 800b30c: 4618 mov r0, r3 800b30e: 370c adds r7, #12 800b310: 46bd mov sp, r7 800b312: f85d 7b04 ldr.w r7, [sp], #4 800b316: 4770 bx lr 0800b318 : * driver. All combination are allowed: wake up only Cortex-M7, wake up * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4. * @retval None. */ void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD) { 800b318: b480 push {r7} 800b31a: b083 sub sp, #12 800b31c: af00 add r7, sp, #0 800b31e: 6078 str r0, [r7, #4] /* Check the PVD configuration parameter */ if (sConfigPVD == NULL) 800b320: 687b ldr r3, [r7, #4] 800b322: 2b00 cmp r3, #0 800b324: d069 beq.n 800b3fa /* Check the parameters */ assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel)); assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode)); /* Set PLS[7:5] bits according to PVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); 800b326: 4b38 ldr r3, [pc, #224] @ (800b408 ) 800b328: 681b ldr r3, [r3, #0] 800b32a: f023 02e0 bic.w r2, r3, #224 @ 0xe0 800b32e: 687b ldr r3, [r7, #4] 800b330: 681b ldr r3, [r3, #0] 800b332: 4935 ldr r1, [pc, #212] @ (800b408 ) 800b334: 4313 orrs r3, r2 800b336: 600b str r3, [r1, #0] /* Clear previous config */ #if !defined (DUAL_CORE) __HAL_PWR_PVD_EXTI_DISABLE_EVENT (); 800b338: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b33c: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b340: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b344: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b348: f8c2 3084 str.w r3, [r2, #132] @ 0x84 __HAL_PWR_PVD_EXTI_DISABLE_IT (); 800b34c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b350: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b354: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b358: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b35c: f8c2 3080 str.w r3, [r2, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE (); 800b360: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b364: 681b ldr r3, [r3, #0] 800b366: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b36a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b36e: 6013 str r3, [r2, #0] __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE (); 800b370: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b374: 685b ldr r3, [r3, #4] 800b376: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b37a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b37e: 6053 str r3, [r2, #4] #if !defined (DUAL_CORE) /* Interrupt mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 800b380: 687b ldr r3, [r7, #4] 800b382: 685b ldr r3, [r3, #4] 800b384: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b388: 2b00 cmp r3, #0 800b38a: d009 beq.n 800b3a0 { __HAL_PWR_PVD_EXTI_ENABLE_IT (); 800b38c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b390: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b394: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b398: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b39c: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } /* Event mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 800b3a0: 687b ldr r3, [r7, #4] 800b3a2: 685b ldr r3, [r3, #4] 800b3a4: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b3a8: 2b00 cmp r3, #0 800b3aa: d009 beq.n 800b3c0 { __HAL_PWR_PVD_EXTI_ENABLE_EVENT (); 800b3ac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b3b0: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b3b4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b3b8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b3bc: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 800b3c0: 687b ldr r3, [r7, #4] 800b3c2: 685b ldr r3, [r3, #4] 800b3c4: f003 0301 and.w r3, r3, #1 800b3c8: 2b00 cmp r3, #0 800b3ca: d007 beq.n 800b3dc { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE (); 800b3cc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b3d0: 681b ldr r3, [r3, #0] 800b3d2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b3d6: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b3da: 6013 str r3, [r2, #0] } /* Falling edge configuration */ if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 800b3dc: 687b ldr r3, [r7, #4] 800b3de: 685b ldr r3, [r3, #4] 800b3e0: f003 0302 and.w r3, r3, #2 800b3e4: 2b00 cmp r3, #0 800b3e6: d009 beq.n 800b3fc { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE (); 800b3e8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b3ec: 685b ldr r3, [r3, #4] 800b3ee: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b3f2: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b3f6: 6053 str r3, [r2, #4] 800b3f8: e000 b.n 800b3fc return; 800b3fa: bf00 nop } } 800b3fc: 370c adds r7, #12 800b3fe: 46bd mov sp, r7 800b400: f85d 7b04 ldr.w r7, [sp], #4 800b404: 4770 bx lr 800b406: bf00 nop 800b408: 58024800 .word 0x58024800 0800b40c : /** * @brief Enable the Programmable Voltage Detector (PVD). * @retval None. */ void HAL_PWR_EnablePVD (void) { 800b40c: b480 push {r7} 800b40e: af00 add r7, sp, #0 /* Enable the power voltage detector */ SET_BIT (PWR->CR1, PWR_CR1_PVDEN); 800b410: 4b05 ldr r3, [pc, #20] @ (800b428 ) 800b412: 681b ldr r3, [r3, #0] 800b414: 4a04 ldr r2, [pc, #16] @ (800b428 ) 800b416: f043 0310 orr.w r3, r3, #16 800b41a: 6013 str r3, [r2, #0] } 800b41c: bf00 nop 800b41e: 46bd mov sp, r7 800b420: f85d 7b04 ldr.w r7, [sp], #4 800b424: 4770 bx lr 800b426: bf00 nop 800b428: 58024800 .word 0x58024800 0800b42c : * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { 800b42c: b580 push {r7, lr} 800b42e: b084 sub sp, #16 800b430: af00 add r7, sp, #0 800b432: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_SUPPLY (SupplySource)); /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) 800b434: 4b19 ldr r3, [pc, #100] @ (800b49c ) 800b436: 68db ldr r3, [r3, #12] 800b438: f003 0304 and.w r3, r3, #4 800b43c: 2b04 cmp r3, #4 800b43e: d00a beq.n 800b456 #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 800b440: 4b16 ldr r3, [pc, #88] @ (800b49c ) 800b442: 68db ldr r3, [r3, #12] 800b444: f003 0307 and.w r3, r3, #7 800b448: 687a ldr r2, [r7, #4] 800b44a: 429a cmp r2, r3 800b44c: d001 beq.n 800b452 { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 800b44e: 2301 movs r3, #1 800b450: e01f b.n 800b492 else { /* Supply configuration update locked, but new supply configuration matches with old supply configuration : nothing to do */ return HAL_OK; 800b452: 2300 movs r3, #0 800b454: e01d b.n 800b492 } } /* Set the power supply configuration */ MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 800b456: 4b11 ldr r3, [pc, #68] @ (800b49c ) 800b458: 68db ldr r3, [r3, #12] 800b45a: f023 0207 bic.w r2, r3, #7 800b45e: 490f ldr r1, [pc, #60] @ (800b49c ) 800b460: 687b ldr r3, [r7, #4] 800b462: 4313 orrs r3, r2 800b464: 60cb str r3, [r1, #12] /* Get tick */ tickstart = HAL_GetTick (); 800b466: f7fa fa19 bl 800589c 800b46a: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800b46c: e009 b.n 800b482 { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 800b46e: f7fa fa15 bl 800589c 800b472: 4602 mov r2, r0 800b474: 68fb ldr r3, [r7, #12] 800b476: 1ad3 subs r3, r2, r3 800b478: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b47c: d901 bls.n 800b482 { return HAL_ERROR; 800b47e: 2301 movs r3, #1 800b480: e007 b.n 800b492 while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800b482: 4b06 ldr r3, [pc, #24] @ (800b49c ) 800b484: 685b ldr r3, [r3, #4] 800b486: f403 5300 and.w r3, r3, #8192 @ 0x2000 800b48a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800b48e: d1ee bne.n 800b46e } } } #endif /* defined (SMPS) */ return HAL_OK; 800b490: 2300 movs r3, #0 } 800b492: 4618 mov r0, r3 800b494: 3710 adds r7, #16 800b496: 46bd mov sp, r7 800b498: bd80 pop {r7, pc} 800b49a: bf00 nop 800b49c: 58024800 .word 0x58024800 0800b4a0 : * driver. All combination are allowed: wake up only Cortex-M7, wake up * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4. * @retval None. */ void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD) { 800b4a0: b480 push {r7} 800b4a2: b083 sub sp, #12 800b4a4: af00 add r7, sp, #0 800b4a6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode)); /* Set the ALS[18:17] bits according to AVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); 800b4a8: 4b37 ldr r3, [pc, #220] @ (800b588 ) 800b4aa: 681b ldr r3, [r3, #0] 800b4ac: f423 22c0 bic.w r2, r3, #393216 @ 0x60000 800b4b0: 687b ldr r3, [r7, #4] 800b4b2: 681b ldr r3, [r3, #0] 800b4b4: 4934 ldr r1, [pc, #208] @ (800b588 ) 800b4b6: 4313 orrs r3, r2 800b4b8: 600b str r3, [r1, #0] /* Clear any previous config */ #if !defined (DUAL_CORE) __HAL_PWR_AVD_EXTI_DISABLE_EVENT (); 800b4ba: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b4be: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b4c2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b4c6: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b4ca: f8c2 3084 str.w r3, [r2, #132] @ 0x84 __HAL_PWR_AVD_EXTI_DISABLE_IT (); 800b4ce: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b4d2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b4d6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b4da: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b4de: f8c2 3080 str.w r3, [r2, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE (); 800b4e2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b4e6: 681b ldr r3, [r3, #0] 800b4e8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b4ec: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b4f0: 6013 str r3, [r2, #0] __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE (); 800b4f2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b4f6: 685b ldr r3, [r3, #4] 800b4f8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b4fc: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b500: 6053 str r3, [r2, #4] #if !defined (DUAL_CORE) /* Configure the interrupt mode */ if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT) 800b502: 687b ldr r3, [r7, #4] 800b504: 685b ldr r3, [r3, #4] 800b506: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b50a: 2b00 cmp r3, #0 800b50c: d009 beq.n 800b522 { __HAL_PWR_AVD_EXTI_ENABLE_IT (); 800b50e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b512: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b516: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b51a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b51e: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } /* Configure the event mode */ if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT) 800b522: 687b ldr r3, [r7, #4] 800b524: 685b ldr r3, [r3, #4] 800b526: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b52a: 2b00 cmp r3, #0 800b52c: d009 beq.n 800b542 { __HAL_PWR_AVD_EXTI_ENABLE_EVENT (); 800b52e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b532: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b536: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b53a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b53e: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE) 800b542: 687b ldr r3, [r7, #4] 800b544: 685b ldr r3, [r3, #4] 800b546: f003 0301 and.w r3, r3, #1 800b54a: 2b00 cmp r3, #0 800b54c: d007 beq.n 800b55e { __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE (); 800b54e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b552: 681b ldr r3, [r3, #0] 800b554: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b558: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b55c: 6013 str r3, [r2, #0] } /* Falling edge configuration */ if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE) 800b55e: 687b ldr r3, [r7, #4] 800b560: 685b ldr r3, [r3, #4] 800b562: f003 0302 and.w r3, r3, #2 800b566: 2b00 cmp r3, #0 800b568: d007 beq.n 800b57a { __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE (); 800b56a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b56e: 685b ldr r3, [r3, #4] 800b570: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b574: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b578: 6053 str r3, [r2, #4] } } 800b57a: bf00 nop 800b57c: 370c adds r7, #12 800b57e: 46bd mov sp, r7 800b580: f85d 7b04 ldr.w r7, [sp], #4 800b584: 4770 bx lr 800b586: bf00 nop 800b588: 58024800 .word 0x58024800 0800b58c : /** * @brief Enable the Analog Voltage Detector (AVD). * @retval None. */ void HAL_PWREx_EnableAVD (void) { 800b58c: b480 push {r7} 800b58e: af00 add r7, sp, #0 /* Enable the Analog Voltage Detector */ SET_BIT (PWR->CR1, PWR_CR1_AVDEN); 800b590: 4b05 ldr r3, [pc, #20] @ (800b5a8 ) 800b592: 681b ldr r3, [r3, #0] 800b594: 4a04 ldr r2, [pc, #16] @ (800b5a8 ) 800b596: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b59a: 6013 str r3, [r2, #0] } 800b59c: bf00 nop 800b59e: 46bd mov sp, r7 800b5a0: f85d 7b04 ldr.w r7, [sp], #4 800b5a4: 4770 bx lr 800b5a6: bf00 nop 800b5a8: 58024800 .word 0x58024800 0800b5ac : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800b5ac: b580 push {r7, lr} 800b5ae: b08c sub sp, #48 @ 0x30 800b5b0: af00 add r7, sp, #0 800b5b2: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 800b5b4: 687b ldr r3, [r7, #4] 800b5b6: 2b00 cmp r3, #0 800b5b8: d102 bne.n 800b5c0 { return HAL_ERROR; 800b5ba: 2301 movs r3, #1 800b5bc: f000 bc48 b.w 800be50 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800b5c0: 687b ldr r3, [r7, #4] 800b5c2: 681b ldr r3, [r3, #0] 800b5c4: f003 0301 and.w r3, r3, #1 800b5c8: 2b00 cmp r3, #0 800b5ca: f000 8088 beq.w 800b6de { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b5ce: 4b99 ldr r3, [pc, #612] @ (800b834 ) 800b5d0: 691b ldr r3, [r3, #16] 800b5d2: f003 0338 and.w r3, r3, #56 @ 0x38 800b5d6: 62fb str r3, [r7, #44] @ 0x2c const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800b5d8: 4b96 ldr r3, [pc, #600] @ (800b834 ) 800b5da: 6a9b ldr r3, [r3, #40] @ 0x28 800b5dc: 62bb str r3, [r7, #40] @ 0x28 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 800b5de: 6afb ldr r3, [r7, #44] @ 0x2c 800b5e0: 2b10 cmp r3, #16 800b5e2: d007 beq.n 800b5f4 800b5e4: 6afb ldr r3, [r7, #44] @ 0x2c 800b5e6: 2b18 cmp r3, #24 800b5e8: d111 bne.n 800b60e 800b5ea: 6abb ldr r3, [r7, #40] @ 0x28 800b5ec: f003 0303 and.w r3, r3, #3 800b5f0: 2b02 cmp r3, #2 800b5f2: d10c bne.n 800b60e { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800b5f4: 4b8f ldr r3, [pc, #572] @ (800b834 ) 800b5f6: 681b ldr r3, [r3, #0] 800b5f8: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b5fc: 2b00 cmp r3, #0 800b5fe: d06d beq.n 800b6dc 800b600: 687b ldr r3, [r7, #4] 800b602: 685b ldr r3, [r3, #4] 800b604: 2b00 cmp r3, #0 800b606: d169 bne.n 800b6dc { return HAL_ERROR; 800b608: 2301 movs r3, #1 800b60a: f000 bc21 b.w 800be50 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800b60e: 687b ldr r3, [r7, #4] 800b610: 685b ldr r3, [r3, #4] 800b612: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800b616: d106 bne.n 800b626 800b618: 4b86 ldr r3, [pc, #536] @ (800b834 ) 800b61a: 681b ldr r3, [r3, #0] 800b61c: 4a85 ldr r2, [pc, #532] @ (800b834 ) 800b61e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b622: 6013 str r3, [r2, #0] 800b624: e02e b.n 800b684 800b626: 687b ldr r3, [r7, #4] 800b628: 685b ldr r3, [r3, #4] 800b62a: 2b00 cmp r3, #0 800b62c: d10c bne.n 800b648 800b62e: 4b81 ldr r3, [pc, #516] @ (800b834 ) 800b630: 681b ldr r3, [r3, #0] 800b632: 4a80 ldr r2, [pc, #512] @ (800b834 ) 800b634: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b638: 6013 str r3, [r2, #0] 800b63a: 4b7e ldr r3, [pc, #504] @ (800b834 ) 800b63c: 681b ldr r3, [r3, #0] 800b63e: 4a7d ldr r2, [pc, #500] @ (800b834 ) 800b640: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800b644: 6013 str r3, [r2, #0] 800b646: e01d b.n 800b684 800b648: 687b ldr r3, [r7, #4] 800b64a: 685b ldr r3, [r3, #4] 800b64c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800b650: d10c bne.n 800b66c 800b652: 4b78 ldr r3, [pc, #480] @ (800b834 ) 800b654: 681b ldr r3, [r3, #0] 800b656: 4a77 ldr r2, [pc, #476] @ (800b834 ) 800b658: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800b65c: 6013 str r3, [r2, #0] 800b65e: 4b75 ldr r3, [pc, #468] @ (800b834 ) 800b660: 681b ldr r3, [r3, #0] 800b662: 4a74 ldr r2, [pc, #464] @ (800b834 ) 800b664: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b668: 6013 str r3, [r2, #0] 800b66a: e00b b.n 800b684 800b66c: 4b71 ldr r3, [pc, #452] @ (800b834 ) 800b66e: 681b ldr r3, [r3, #0] 800b670: 4a70 ldr r2, [pc, #448] @ (800b834 ) 800b672: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b676: 6013 str r3, [r2, #0] 800b678: 4b6e ldr r3, [pc, #440] @ (800b834 ) 800b67a: 681b ldr r3, [r3, #0] 800b67c: 4a6d ldr r2, [pc, #436] @ (800b834 ) 800b67e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800b682: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 800b684: 687b ldr r3, [r7, #4] 800b686: 685b ldr r3, [r3, #4] 800b688: 2b00 cmp r3, #0 800b68a: d013 beq.n 800b6b4 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b68c: f7fa f906 bl 800589c 800b690: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800b692: e008 b.n 800b6a6 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800b694: f7fa f902 bl 800589c 800b698: 4602 mov r2, r0 800b69a: 6a7b ldr r3, [r7, #36] @ 0x24 800b69c: 1ad3 subs r3, r2, r3 800b69e: 2b64 cmp r3, #100 @ 0x64 800b6a0: d901 bls.n 800b6a6 { return HAL_TIMEOUT; 800b6a2: 2303 movs r3, #3 800b6a4: e3d4 b.n 800be50 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800b6a6: 4b63 ldr r3, [pc, #396] @ (800b834 ) 800b6a8: 681b ldr r3, [r3, #0] 800b6aa: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b6ae: 2b00 cmp r3, #0 800b6b0: d0f0 beq.n 800b694 800b6b2: e014 b.n 800b6de } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b6b4: f7fa f8f2 bl 800589c 800b6b8: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800b6ba: e008 b.n 800b6ce { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800b6bc: f7fa f8ee bl 800589c 800b6c0: 4602 mov r2, r0 800b6c2: 6a7b ldr r3, [r7, #36] @ 0x24 800b6c4: 1ad3 subs r3, r2, r3 800b6c6: 2b64 cmp r3, #100 @ 0x64 800b6c8: d901 bls.n 800b6ce { return HAL_TIMEOUT; 800b6ca: 2303 movs r3, #3 800b6cc: e3c0 b.n 800be50 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800b6ce: 4b59 ldr r3, [pc, #356] @ (800b834 ) 800b6d0: 681b ldr r3, [r3, #0] 800b6d2: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b6d6: 2b00 cmp r3, #0 800b6d8: d1f0 bne.n 800b6bc 800b6da: e000 b.n 800b6de if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800b6dc: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800b6de: 687b ldr r3, [r7, #4] 800b6e0: 681b ldr r3, [r3, #0] 800b6e2: f003 0302 and.w r3, r3, #2 800b6e6: 2b00 cmp r3, #0 800b6e8: f000 80ca beq.w 800b880 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b6ec: 4b51 ldr r3, [pc, #324] @ (800b834 ) 800b6ee: 691b ldr r3, [r3, #16] 800b6f0: f003 0338 and.w r3, r3, #56 @ 0x38 800b6f4: 623b str r3, [r7, #32] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800b6f6: 4b4f ldr r3, [pc, #316] @ (800b834 ) 800b6f8: 6a9b ldr r3, [r3, #40] @ 0x28 800b6fa: 61fb str r3, [r7, #28] if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 800b6fc: 6a3b ldr r3, [r7, #32] 800b6fe: 2b00 cmp r3, #0 800b700: d007 beq.n 800b712 800b702: 6a3b ldr r3, [r7, #32] 800b704: 2b18 cmp r3, #24 800b706: d156 bne.n 800b7b6 800b708: 69fb ldr r3, [r7, #28] 800b70a: f003 0303 and.w r3, r3, #3 800b70e: 2b00 cmp r3, #0 800b710: d151 bne.n 800b7b6 { /* When HSI is used as system clock it will not be disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800b712: 4b48 ldr r3, [pc, #288] @ (800b834 ) 800b714: 681b ldr r3, [r3, #0] 800b716: f003 0304 and.w r3, r3, #4 800b71a: 2b00 cmp r3, #0 800b71c: d005 beq.n 800b72a 800b71e: 687b ldr r3, [r7, #4] 800b720: 68db ldr r3, [r3, #12] 800b722: 2b00 cmp r3, #0 800b724: d101 bne.n 800b72a { return HAL_ERROR; 800b726: 2301 movs r3, #1 800b728: e392 b.n 800be50 } /* Otherwise, only HSI division and calibration are allowed */ else { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800b72a: 4b42 ldr r3, [pc, #264] @ (800b834 ) 800b72c: 681b ldr r3, [r3, #0] 800b72e: f023 0219 bic.w r2, r3, #25 800b732: 687b ldr r3, [r7, #4] 800b734: 68db ldr r3, [r3, #12] 800b736: 493f ldr r1, [pc, #252] @ (800b834 ) 800b738: 4313 orrs r3, r2 800b73a: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b73c: f7fa f8ae bl 800589c 800b740: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800b742: e008 b.n 800b756 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800b744: f7fa f8aa bl 800589c 800b748: 4602 mov r2, r0 800b74a: 6a7b ldr r3, [r7, #36] @ 0x24 800b74c: 1ad3 subs r3, r2, r3 800b74e: 2b02 cmp r3, #2 800b750: d901 bls.n 800b756 { return HAL_TIMEOUT; 800b752: 2303 movs r3, #3 800b754: e37c b.n 800be50 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800b756: 4b37 ldr r3, [pc, #220] @ (800b834 ) 800b758: 681b ldr r3, [r3, #0] 800b75a: f003 0304 and.w r3, r3, #4 800b75e: 2b00 cmp r3, #0 800b760: d0f0 beq.n 800b744 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800b762: f7fa f8a7 bl 80058b4 800b766: 4603 mov r3, r0 800b768: f241 0203 movw r2, #4099 @ 0x1003 800b76c: 4293 cmp r3, r2 800b76e: d817 bhi.n 800b7a0 800b770: 687b ldr r3, [r7, #4] 800b772: 691b ldr r3, [r3, #16] 800b774: 2b40 cmp r3, #64 @ 0x40 800b776: d108 bne.n 800b78a 800b778: 4b2e ldr r3, [pc, #184] @ (800b834 ) 800b77a: 685b ldr r3, [r3, #4] 800b77c: f423 337c bic.w r3, r3, #258048 @ 0x3f000 800b780: 4a2c ldr r2, [pc, #176] @ (800b834 ) 800b782: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800b786: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800b788: e07a b.n 800b880 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800b78a: 4b2a ldr r3, [pc, #168] @ (800b834 ) 800b78c: 685b ldr r3, [r3, #4] 800b78e: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800b792: 687b ldr r3, [r7, #4] 800b794: 691b ldr r3, [r3, #16] 800b796: 031b lsls r3, r3, #12 800b798: 4926 ldr r1, [pc, #152] @ (800b834 ) 800b79a: 4313 orrs r3, r2 800b79c: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800b79e: e06f b.n 800b880 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800b7a0: 4b24 ldr r3, [pc, #144] @ (800b834 ) 800b7a2: 685b ldr r3, [r3, #4] 800b7a4: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800b7a8: 687b ldr r3, [r7, #4] 800b7aa: 691b ldr r3, [r3, #16] 800b7ac: 061b lsls r3, r3, #24 800b7ae: 4921 ldr r1, [pc, #132] @ (800b834 ) 800b7b0: 4313 orrs r3, r2 800b7b2: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800b7b4: e064 b.n 800b880 } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 800b7b6: 687b ldr r3, [r7, #4] 800b7b8: 68db ldr r3, [r3, #12] 800b7ba: 2b00 cmp r3, #0 800b7bc: d047 beq.n 800b84e { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800b7be: 4b1d ldr r3, [pc, #116] @ (800b834 ) 800b7c0: 681b ldr r3, [r3, #0] 800b7c2: f023 0219 bic.w r2, r3, #25 800b7c6: 687b ldr r3, [r7, #4] 800b7c8: 68db ldr r3, [r3, #12] 800b7ca: 491a ldr r1, [pc, #104] @ (800b834 ) 800b7cc: 4313 orrs r3, r2 800b7ce: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b7d0: f7fa f864 bl 800589c 800b7d4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800b7d6: e008 b.n 800b7ea { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800b7d8: f7fa f860 bl 800589c 800b7dc: 4602 mov r2, r0 800b7de: 6a7b ldr r3, [r7, #36] @ 0x24 800b7e0: 1ad3 subs r3, r2, r3 800b7e2: 2b02 cmp r3, #2 800b7e4: d901 bls.n 800b7ea { return HAL_TIMEOUT; 800b7e6: 2303 movs r3, #3 800b7e8: e332 b.n 800be50 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800b7ea: 4b12 ldr r3, [pc, #72] @ (800b834 ) 800b7ec: 681b ldr r3, [r3, #0] 800b7ee: f003 0304 and.w r3, r3, #4 800b7f2: 2b00 cmp r3, #0 800b7f4: d0f0 beq.n 800b7d8 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800b7f6: f7fa f85d bl 80058b4 800b7fa: 4603 mov r3, r0 800b7fc: f241 0203 movw r2, #4099 @ 0x1003 800b800: 4293 cmp r3, r2 800b802: d819 bhi.n 800b838 800b804: 687b ldr r3, [r7, #4] 800b806: 691b ldr r3, [r3, #16] 800b808: 2b40 cmp r3, #64 @ 0x40 800b80a: d108 bne.n 800b81e 800b80c: 4b09 ldr r3, [pc, #36] @ (800b834 ) 800b80e: 685b ldr r3, [r3, #4] 800b810: f423 337c bic.w r3, r3, #258048 @ 0x3f000 800b814: 4a07 ldr r2, [pc, #28] @ (800b834 ) 800b816: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800b81a: 6053 str r3, [r2, #4] 800b81c: e030 b.n 800b880 800b81e: 4b05 ldr r3, [pc, #20] @ (800b834 ) 800b820: 685b ldr r3, [r3, #4] 800b822: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800b826: 687b ldr r3, [r7, #4] 800b828: 691b ldr r3, [r3, #16] 800b82a: 031b lsls r3, r3, #12 800b82c: 4901 ldr r1, [pc, #4] @ (800b834 ) 800b82e: 4313 orrs r3, r2 800b830: 604b str r3, [r1, #4] 800b832: e025 b.n 800b880 800b834: 58024400 .word 0x58024400 800b838: 4b9a ldr r3, [pc, #616] @ (800baa4 ) 800b83a: 685b ldr r3, [r3, #4] 800b83c: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800b840: 687b ldr r3, [r7, #4] 800b842: 691b ldr r3, [r3, #16] 800b844: 061b lsls r3, r3, #24 800b846: 4997 ldr r1, [pc, #604] @ (800baa4 ) 800b848: 4313 orrs r3, r2 800b84a: 604b str r3, [r1, #4] 800b84c: e018 b.n 800b880 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800b84e: 4b95 ldr r3, [pc, #596] @ (800baa4 ) 800b850: 681b ldr r3, [r3, #0] 800b852: 4a94 ldr r2, [pc, #592] @ (800baa4 ) 800b854: f023 0301 bic.w r3, r3, #1 800b858: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b85a: f7fa f81f bl 800589c 800b85e: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800b860: e008 b.n 800b874 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800b862: f7fa f81b bl 800589c 800b866: 4602 mov r2, r0 800b868: 6a7b ldr r3, [r7, #36] @ 0x24 800b86a: 1ad3 subs r3, r2, r3 800b86c: 2b02 cmp r3, #2 800b86e: d901 bls.n 800b874 { return HAL_TIMEOUT; 800b870: 2303 movs r3, #3 800b872: e2ed b.n 800be50 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800b874: 4b8b ldr r3, [pc, #556] @ (800baa4 ) 800b876: 681b ldr r3, [r3, #0] 800b878: f003 0304 and.w r3, r3, #4 800b87c: 2b00 cmp r3, #0 800b87e: d1f0 bne.n 800b862 } } } } /*----------------------------- CSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 800b880: 687b ldr r3, [r7, #4] 800b882: 681b ldr r3, [r3, #0] 800b884: f003 0310 and.w r3, r3, #16 800b888: 2b00 cmp r3, #0 800b88a: f000 80a9 beq.w 800b9e0 /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b88e: 4b85 ldr r3, [pc, #532] @ (800baa4 ) 800b890: 691b ldr r3, [r3, #16] 800b892: f003 0338 and.w r3, r3, #56 @ 0x38 800b896: 61bb str r3, [r7, #24] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800b898: 4b82 ldr r3, [pc, #520] @ (800baa4 ) 800b89a: 6a9b ldr r3, [r3, #40] @ 0x28 800b89c: 617b str r3, [r7, #20] if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 800b89e: 69bb ldr r3, [r7, #24] 800b8a0: 2b08 cmp r3, #8 800b8a2: d007 beq.n 800b8b4 800b8a4: 69bb ldr r3, [r7, #24] 800b8a6: 2b18 cmp r3, #24 800b8a8: d13a bne.n 800b920 800b8aa: 697b ldr r3, [r7, #20] 800b8ac: f003 0303 and.w r3, r3, #3 800b8b0: 2b01 cmp r3, #1 800b8b2: d135 bne.n 800b920 { /* When CSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800b8b4: 4b7b ldr r3, [pc, #492] @ (800baa4 ) 800b8b6: 681b ldr r3, [r3, #0] 800b8b8: f403 7380 and.w r3, r3, #256 @ 0x100 800b8bc: 2b00 cmp r3, #0 800b8be: d005 beq.n 800b8cc 800b8c0: 687b ldr r3, [r7, #4] 800b8c2: 69db ldr r3, [r3, #28] 800b8c4: 2b80 cmp r3, #128 @ 0x80 800b8c6: d001 beq.n 800b8cc { return HAL_ERROR; 800b8c8: 2301 movs r3, #1 800b8ca: e2c1 b.n 800be50 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800b8cc: f7f9 fff2 bl 80058b4 800b8d0: 4603 mov r3, r0 800b8d2: f241 0203 movw r2, #4099 @ 0x1003 800b8d6: 4293 cmp r3, r2 800b8d8: d817 bhi.n 800b90a 800b8da: 687b ldr r3, [r7, #4] 800b8dc: 6a1b ldr r3, [r3, #32] 800b8de: 2b20 cmp r3, #32 800b8e0: d108 bne.n 800b8f4 800b8e2: 4b70 ldr r3, [pc, #448] @ (800baa4 ) 800b8e4: 685b ldr r3, [r3, #4] 800b8e6: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 800b8ea: 4a6e ldr r2, [pc, #440] @ (800baa4 ) 800b8ec: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800b8f0: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800b8f2: e075 b.n 800b9e0 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800b8f4: 4b6b ldr r3, [pc, #428] @ (800baa4 ) 800b8f6: 685b ldr r3, [r3, #4] 800b8f8: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800b8fc: 687b ldr r3, [r7, #4] 800b8fe: 6a1b ldr r3, [r3, #32] 800b900: 069b lsls r3, r3, #26 800b902: 4968 ldr r1, [pc, #416] @ (800baa4 ) 800b904: 4313 orrs r3, r2 800b906: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800b908: e06a b.n 800b9e0 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800b90a: 4b66 ldr r3, [pc, #408] @ (800baa4 ) 800b90c: 68db ldr r3, [r3, #12] 800b90e: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 800b912: 687b ldr r3, [r7, #4] 800b914: 6a1b ldr r3, [r3, #32] 800b916: 061b lsls r3, r3, #24 800b918: 4962 ldr r1, [pc, #392] @ (800baa4 ) 800b91a: 4313 orrs r3, r2 800b91c: 60cb str r3, [r1, #12] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800b91e: e05f b.n 800b9e0 } } else { /* Check the CSI State */ if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) 800b920: 687b ldr r3, [r7, #4] 800b922: 69db ldr r3, [r3, #28] 800b924: 2b00 cmp r3, #0 800b926: d042 beq.n 800b9ae { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 800b928: 4b5e ldr r3, [pc, #376] @ (800baa4 ) 800b92a: 681b ldr r3, [r3, #0] 800b92c: 4a5d ldr r2, [pc, #372] @ (800baa4 ) 800b92e: f043 0380 orr.w r3, r3, #128 @ 0x80 800b932: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b934: f7f9 ffb2 bl 800589c 800b938: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800b93a: e008 b.n 800b94e { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 800b93c: f7f9 ffae bl 800589c 800b940: 4602 mov r2, r0 800b942: 6a7b ldr r3, [r7, #36] @ 0x24 800b944: 1ad3 subs r3, r2, r3 800b946: 2b02 cmp r3, #2 800b948: d901 bls.n 800b94e { return HAL_TIMEOUT; 800b94a: 2303 movs r3, #3 800b94c: e280 b.n 800be50 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800b94e: 4b55 ldr r3, [pc, #340] @ (800baa4 ) 800b950: 681b ldr r3, [r3, #0] 800b952: f403 7380 and.w r3, r3, #256 @ 0x100 800b956: 2b00 cmp r3, #0 800b958: d0f0 beq.n 800b93c } } /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800b95a: f7f9 ffab bl 80058b4 800b95e: 4603 mov r3, r0 800b960: f241 0203 movw r2, #4099 @ 0x1003 800b964: 4293 cmp r3, r2 800b966: d817 bhi.n 800b998 800b968: 687b ldr r3, [r7, #4] 800b96a: 6a1b ldr r3, [r3, #32] 800b96c: 2b20 cmp r3, #32 800b96e: d108 bne.n 800b982 800b970: 4b4c ldr r3, [pc, #304] @ (800baa4 ) 800b972: 685b ldr r3, [r3, #4] 800b974: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 800b978: 4a4a ldr r2, [pc, #296] @ (800baa4 ) 800b97a: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800b97e: 6053 str r3, [r2, #4] 800b980: e02e b.n 800b9e0 800b982: 4b48 ldr r3, [pc, #288] @ (800baa4 ) 800b984: 685b ldr r3, [r3, #4] 800b986: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800b98a: 687b ldr r3, [r7, #4] 800b98c: 6a1b ldr r3, [r3, #32] 800b98e: 069b lsls r3, r3, #26 800b990: 4944 ldr r1, [pc, #272] @ (800baa4 ) 800b992: 4313 orrs r3, r2 800b994: 604b str r3, [r1, #4] 800b996: e023 b.n 800b9e0 800b998: 4b42 ldr r3, [pc, #264] @ (800baa4 ) 800b99a: 68db ldr r3, [r3, #12] 800b99c: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 800b9a0: 687b ldr r3, [r7, #4] 800b9a2: 6a1b ldr r3, [r3, #32] 800b9a4: 061b lsls r3, r3, #24 800b9a6: 493f ldr r1, [pc, #252] @ (800baa4 ) 800b9a8: 4313 orrs r3, r2 800b9aa: 60cb str r3, [r1, #12] 800b9ac: e018 b.n 800b9e0 } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 800b9ae: 4b3d ldr r3, [pc, #244] @ (800baa4 ) 800b9b0: 681b ldr r3, [r3, #0] 800b9b2: 4a3c ldr r2, [pc, #240] @ (800baa4 ) 800b9b4: f023 0380 bic.w r3, r3, #128 @ 0x80 800b9b8: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b9ba: f7f9 ff6f bl 800589c 800b9be: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800b9c0: e008 b.n 800b9d4 { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 800b9c2: f7f9 ff6b bl 800589c 800b9c6: 4602 mov r2, r0 800b9c8: 6a7b ldr r3, [r7, #36] @ 0x24 800b9ca: 1ad3 subs r3, r2, r3 800b9cc: 2b02 cmp r3, #2 800b9ce: d901 bls.n 800b9d4 { return HAL_TIMEOUT; 800b9d0: 2303 movs r3, #3 800b9d2: e23d b.n 800be50 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800b9d4: 4b33 ldr r3, [pc, #204] @ (800baa4 ) 800b9d6: 681b ldr r3, [r3, #0] 800b9d8: f403 7380 and.w r3, r3, #256 @ 0x100 800b9dc: 2b00 cmp r3, #0 800b9de: d1f0 bne.n 800b9c2 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800b9e0: 687b ldr r3, [r7, #4] 800b9e2: 681b ldr r3, [r3, #0] 800b9e4: f003 0308 and.w r3, r3, #8 800b9e8: 2b00 cmp r3, #0 800b9ea: d036 beq.n 800ba5a { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 800b9ec: 687b ldr r3, [r7, #4] 800b9ee: 695b ldr r3, [r3, #20] 800b9f0: 2b00 cmp r3, #0 800b9f2: d019 beq.n 800ba28 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800b9f4: 4b2b ldr r3, [pc, #172] @ (800baa4 ) 800b9f6: 6f5b ldr r3, [r3, #116] @ 0x74 800b9f8: 4a2a ldr r2, [pc, #168] @ (800baa4 ) 800b9fa: f043 0301 orr.w r3, r3, #1 800b9fe: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ba00: f7f9 ff4c bl 800589c 800ba04: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800ba06: e008 b.n 800ba1a { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800ba08: f7f9 ff48 bl 800589c 800ba0c: 4602 mov r2, r0 800ba0e: 6a7b ldr r3, [r7, #36] @ 0x24 800ba10: 1ad3 subs r3, r2, r3 800ba12: 2b02 cmp r3, #2 800ba14: d901 bls.n 800ba1a { return HAL_TIMEOUT; 800ba16: 2303 movs r3, #3 800ba18: e21a b.n 800be50 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800ba1a: 4b22 ldr r3, [pc, #136] @ (800baa4 ) 800ba1c: 6f5b ldr r3, [r3, #116] @ 0x74 800ba1e: f003 0302 and.w r3, r3, #2 800ba22: 2b00 cmp r3, #0 800ba24: d0f0 beq.n 800ba08 800ba26: e018 b.n 800ba5a } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800ba28: 4b1e ldr r3, [pc, #120] @ (800baa4 ) 800ba2a: 6f5b ldr r3, [r3, #116] @ 0x74 800ba2c: 4a1d ldr r2, [pc, #116] @ (800baa4 ) 800ba2e: f023 0301 bic.w r3, r3, #1 800ba32: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ba34: f7f9 ff32 bl 800589c 800ba38: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800ba3a: e008 b.n 800ba4e { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800ba3c: f7f9 ff2e bl 800589c 800ba40: 4602 mov r2, r0 800ba42: 6a7b ldr r3, [r7, #36] @ 0x24 800ba44: 1ad3 subs r3, r2, r3 800ba46: 2b02 cmp r3, #2 800ba48: d901 bls.n 800ba4e { return HAL_TIMEOUT; 800ba4a: 2303 movs r3, #3 800ba4c: e200 b.n 800be50 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800ba4e: 4b15 ldr r3, [pc, #84] @ (800baa4 ) 800ba50: 6f5b ldr r3, [r3, #116] @ 0x74 800ba52: f003 0302 and.w r3, r3, #2 800ba56: 2b00 cmp r3, #0 800ba58: d1f0 bne.n 800ba3c } } } /*------------------------------ HSI48 Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 800ba5a: 687b ldr r3, [r7, #4] 800ba5c: 681b ldr r3, [r3, #0] 800ba5e: f003 0320 and.w r3, r3, #32 800ba62: 2b00 cmp r3, #0 800ba64: d039 beq.n 800bada { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) 800ba66: 687b ldr r3, [r7, #4] 800ba68: 699b ldr r3, [r3, #24] 800ba6a: 2b00 cmp r3, #0 800ba6c: d01c beq.n 800baa8 { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 800ba6e: 4b0d ldr r3, [pc, #52] @ (800baa4 ) 800ba70: 681b ldr r3, [r3, #0] 800ba72: 4a0c ldr r2, [pc, #48] @ (800baa4 ) 800ba74: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800ba78: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800ba7a: f7f9 ff0f bl 800589c 800ba7e: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 800ba80: e008 b.n 800ba94 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800ba82: f7f9 ff0b bl 800589c 800ba86: 4602 mov r2, r0 800ba88: 6a7b ldr r3, [r7, #36] @ 0x24 800ba8a: 1ad3 subs r3, r2, r3 800ba8c: 2b02 cmp r3, #2 800ba8e: d901 bls.n 800ba94 { return HAL_TIMEOUT; 800ba90: 2303 movs r3, #3 800ba92: e1dd b.n 800be50 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 800ba94: 4b03 ldr r3, [pc, #12] @ (800baa4 ) 800ba96: 681b ldr r3, [r3, #0] 800ba98: f403 5300 and.w r3, r3, #8192 @ 0x2000 800ba9c: 2b00 cmp r3, #0 800ba9e: d0f0 beq.n 800ba82 800baa0: e01b b.n 800bada 800baa2: bf00 nop 800baa4: 58024400 .word 0x58024400 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 800baa8: 4b9b ldr r3, [pc, #620] @ (800bd18 ) 800baaa: 681b ldr r3, [r3, #0] 800baac: 4a9a ldr r2, [pc, #616] @ (800bd18 ) 800baae: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800bab2: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800bab4: f7f9 fef2 bl 800589c 800bab8: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800baba: e008 b.n 800bace { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800babc: f7f9 feee bl 800589c 800bac0: 4602 mov r2, r0 800bac2: 6a7b ldr r3, [r7, #36] @ 0x24 800bac4: 1ad3 subs r3, r2, r3 800bac6: 2b02 cmp r3, #2 800bac8: d901 bls.n 800bace { return HAL_TIMEOUT; 800baca: 2303 movs r3, #3 800bacc: e1c0 b.n 800be50 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800bace: 4b92 ldr r3, [pc, #584] @ (800bd18 ) 800bad0: 681b ldr r3, [r3, #0] 800bad2: f403 5300 and.w r3, r3, #8192 @ 0x2000 800bad6: 2b00 cmp r3, #0 800bad8: d1f0 bne.n 800babc } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800bada: 687b ldr r3, [r7, #4] 800badc: 681b ldr r3, [r3, #0] 800bade: f003 0304 and.w r3, r3, #4 800bae2: 2b00 cmp r3, #0 800bae4: f000 8081 beq.w 800bbea { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 800bae8: 4b8c ldr r3, [pc, #560] @ (800bd1c ) 800baea: 681b ldr r3, [r3, #0] 800baec: 4a8b ldr r2, [pc, #556] @ (800bd1c ) 800baee: f443 7380 orr.w r3, r3, #256 @ 0x100 800baf2: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800baf4: f7f9 fed2 bl 800589c 800baf8: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800bafa: e008 b.n 800bb0e { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800bafc: f7f9 fece bl 800589c 800bb00: 4602 mov r2, r0 800bb02: 6a7b ldr r3, [r7, #36] @ 0x24 800bb04: 1ad3 subs r3, r2, r3 800bb06: 2b64 cmp r3, #100 @ 0x64 800bb08: d901 bls.n 800bb0e { return HAL_TIMEOUT; 800bb0a: 2303 movs r3, #3 800bb0c: e1a0 b.n 800be50 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800bb0e: 4b83 ldr r3, [pc, #524] @ (800bd1c ) 800bb10: 681b ldr r3, [r3, #0] 800bb12: f403 7380 and.w r3, r3, #256 @ 0x100 800bb16: 2b00 cmp r3, #0 800bb18: d0f0 beq.n 800bafc } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800bb1a: 687b ldr r3, [r7, #4] 800bb1c: 689b ldr r3, [r3, #8] 800bb1e: 2b01 cmp r3, #1 800bb20: d106 bne.n 800bb30 800bb22: 4b7d ldr r3, [pc, #500] @ (800bd18 ) 800bb24: 6f1b ldr r3, [r3, #112] @ 0x70 800bb26: 4a7c ldr r2, [pc, #496] @ (800bd18 ) 800bb28: f043 0301 orr.w r3, r3, #1 800bb2c: 6713 str r3, [r2, #112] @ 0x70 800bb2e: e02d b.n 800bb8c 800bb30: 687b ldr r3, [r7, #4] 800bb32: 689b ldr r3, [r3, #8] 800bb34: 2b00 cmp r3, #0 800bb36: d10c bne.n 800bb52 800bb38: 4b77 ldr r3, [pc, #476] @ (800bd18 ) 800bb3a: 6f1b ldr r3, [r3, #112] @ 0x70 800bb3c: 4a76 ldr r2, [pc, #472] @ (800bd18 ) 800bb3e: f023 0301 bic.w r3, r3, #1 800bb42: 6713 str r3, [r2, #112] @ 0x70 800bb44: 4b74 ldr r3, [pc, #464] @ (800bd18 ) 800bb46: 6f1b ldr r3, [r3, #112] @ 0x70 800bb48: 4a73 ldr r2, [pc, #460] @ (800bd18 ) 800bb4a: f023 0304 bic.w r3, r3, #4 800bb4e: 6713 str r3, [r2, #112] @ 0x70 800bb50: e01c b.n 800bb8c 800bb52: 687b ldr r3, [r7, #4] 800bb54: 689b ldr r3, [r3, #8] 800bb56: 2b05 cmp r3, #5 800bb58: d10c bne.n 800bb74 800bb5a: 4b6f ldr r3, [pc, #444] @ (800bd18 ) 800bb5c: 6f1b ldr r3, [r3, #112] @ 0x70 800bb5e: 4a6e ldr r2, [pc, #440] @ (800bd18 ) 800bb60: f043 0304 orr.w r3, r3, #4 800bb64: 6713 str r3, [r2, #112] @ 0x70 800bb66: 4b6c ldr r3, [pc, #432] @ (800bd18 ) 800bb68: 6f1b ldr r3, [r3, #112] @ 0x70 800bb6a: 4a6b ldr r2, [pc, #428] @ (800bd18 ) 800bb6c: f043 0301 orr.w r3, r3, #1 800bb70: 6713 str r3, [r2, #112] @ 0x70 800bb72: e00b b.n 800bb8c 800bb74: 4b68 ldr r3, [pc, #416] @ (800bd18 ) 800bb76: 6f1b ldr r3, [r3, #112] @ 0x70 800bb78: 4a67 ldr r2, [pc, #412] @ (800bd18 ) 800bb7a: f023 0301 bic.w r3, r3, #1 800bb7e: 6713 str r3, [r2, #112] @ 0x70 800bb80: 4b65 ldr r3, [pc, #404] @ (800bd18 ) 800bb82: 6f1b ldr r3, [r3, #112] @ 0x70 800bb84: 4a64 ldr r2, [pc, #400] @ (800bd18 ) 800bb86: f023 0304 bic.w r3, r3, #4 800bb8a: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 800bb8c: 687b ldr r3, [r7, #4] 800bb8e: 689b ldr r3, [r3, #8] 800bb90: 2b00 cmp r3, #0 800bb92: d015 beq.n 800bbc0 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bb94: f7f9 fe82 bl 800589c 800bb98: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800bb9a: e00a b.n 800bbb2 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800bb9c: f7f9 fe7e bl 800589c 800bba0: 4602 mov r2, r0 800bba2: 6a7b ldr r3, [r7, #36] @ 0x24 800bba4: 1ad3 subs r3, r2, r3 800bba6: f241 3288 movw r2, #5000 @ 0x1388 800bbaa: 4293 cmp r3, r2 800bbac: d901 bls.n 800bbb2 { return HAL_TIMEOUT; 800bbae: 2303 movs r3, #3 800bbb0: e14e b.n 800be50 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800bbb2: 4b59 ldr r3, [pc, #356] @ (800bd18 ) 800bbb4: 6f1b ldr r3, [r3, #112] @ 0x70 800bbb6: f003 0302 and.w r3, r3, #2 800bbba: 2b00 cmp r3, #0 800bbbc: d0ee beq.n 800bb9c 800bbbe: e014 b.n 800bbea } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bbc0: f7f9 fe6c bl 800589c 800bbc4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800bbc6: e00a b.n 800bbde { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800bbc8: f7f9 fe68 bl 800589c 800bbcc: 4602 mov r2, r0 800bbce: 6a7b ldr r3, [r7, #36] @ 0x24 800bbd0: 1ad3 subs r3, r2, r3 800bbd2: f241 3288 movw r2, #5000 @ 0x1388 800bbd6: 4293 cmp r3, r2 800bbd8: d901 bls.n 800bbde { return HAL_TIMEOUT; 800bbda: 2303 movs r3, #3 800bbdc: e138 b.n 800be50 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800bbde: 4b4e ldr r3, [pc, #312] @ (800bd18 ) 800bbe0: 6f1b ldr r3, [r3, #112] @ 0x70 800bbe2: f003 0302 and.w r3, r3, #2 800bbe6: 2b00 cmp r3, #0 800bbe8: d1ee bne.n 800bbc8 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800bbea: 687b ldr r3, [r7, #4] 800bbec: 6a5b ldr r3, [r3, #36] @ 0x24 800bbee: 2b00 cmp r3, #0 800bbf0: f000 812d beq.w 800be4e { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 800bbf4: 4b48 ldr r3, [pc, #288] @ (800bd18 ) 800bbf6: 691b ldr r3, [r3, #16] 800bbf8: f003 0338 and.w r3, r3, #56 @ 0x38 800bbfc: 2b18 cmp r3, #24 800bbfe: f000 80bd beq.w 800bd7c { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 800bc02: 687b ldr r3, [r7, #4] 800bc04: 6a5b ldr r3, [r3, #36] @ 0x24 800bc06: 2b02 cmp r3, #2 800bc08: f040 809e bne.w 800bd48 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800bc0c: 4b42 ldr r3, [pc, #264] @ (800bd18 ) 800bc0e: 681b ldr r3, [r3, #0] 800bc10: 4a41 ldr r2, [pc, #260] @ (800bd18 ) 800bc12: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800bc16: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bc18: f7f9 fe40 bl 800589c 800bc1c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800bc1e: e008 b.n 800bc32 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800bc20: f7f9 fe3c bl 800589c 800bc24: 4602 mov r2, r0 800bc26: 6a7b ldr r3, [r7, #36] @ 0x24 800bc28: 1ad3 subs r3, r2, r3 800bc2a: 2b02 cmp r3, #2 800bc2c: d901 bls.n 800bc32 { return HAL_TIMEOUT; 800bc2e: 2303 movs r3, #3 800bc30: e10e b.n 800be50 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800bc32: 4b39 ldr r3, [pc, #228] @ (800bd18 ) 800bc34: 681b ldr r3, [r3, #0] 800bc36: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800bc3a: 2b00 cmp r3, #0 800bc3c: d1f0 bne.n 800bc20 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 800bc3e: 4b36 ldr r3, [pc, #216] @ (800bd18 ) 800bc40: 6a9a ldr r2, [r3, #40] @ 0x28 800bc42: 4b37 ldr r3, [pc, #220] @ (800bd20 ) 800bc44: 4013 ands r3, r2 800bc46: 687a ldr r2, [r7, #4] 800bc48: 6a91 ldr r1, [r2, #40] @ 0x28 800bc4a: 687a ldr r2, [r7, #4] 800bc4c: 6ad2 ldr r2, [r2, #44] @ 0x2c 800bc4e: 0112 lsls r2, r2, #4 800bc50: 430a orrs r2, r1 800bc52: 4931 ldr r1, [pc, #196] @ (800bd18 ) 800bc54: 4313 orrs r3, r2 800bc56: 628b str r3, [r1, #40] @ 0x28 800bc58: 687b ldr r3, [r7, #4] 800bc5a: 6b1b ldr r3, [r3, #48] @ 0x30 800bc5c: 3b01 subs r3, #1 800bc5e: f3c3 0208 ubfx r2, r3, #0, #9 800bc62: 687b ldr r3, [r7, #4] 800bc64: 6b5b ldr r3, [r3, #52] @ 0x34 800bc66: 3b01 subs r3, #1 800bc68: 025b lsls r3, r3, #9 800bc6a: b29b uxth r3, r3 800bc6c: 431a orrs r2, r3 800bc6e: 687b ldr r3, [r7, #4] 800bc70: 6b9b ldr r3, [r3, #56] @ 0x38 800bc72: 3b01 subs r3, #1 800bc74: 041b lsls r3, r3, #16 800bc76: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800bc7a: 431a orrs r2, r3 800bc7c: 687b ldr r3, [r7, #4] 800bc7e: 6bdb ldr r3, [r3, #60] @ 0x3c 800bc80: 3b01 subs r3, #1 800bc82: 061b lsls r3, r3, #24 800bc84: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800bc88: 4923 ldr r1, [pc, #140] @ (800bd18 ) 800bc8a: 4313 orrs r3, r2 800bc8c: 630b str r3, [r1, #48] @ 0x30 RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Disable PLLFRACN . */ __HAL_RCC_PLLFRACN_DISABLE(); 800bc8e: 4b22 ldr r3, [pc, #136] @ (800bd18 ) 800bc90: 6adb ldr r3, [r3, #44] @ 0x2c 800bc92: 4a21 ldr r2, [pc, #132] @ (800bd18 ) 800bc94: f023 0301 bic.w r3, r3, #1 800bc98: 62d3 str r3, [r2, #44] @ 0x2c /* Configure PLL PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800bc9a: 4b1f ldr r3, [pc, #124] @ (800bd18 ) 800bc9c: 6b5a ldr r2, [r3, #52] @ 0x34 800bc9e: 4b21 ldr r3, [pc, #132] @ (800bd24 ) 800bca0: 4013 ands r3, r2 800bca2: 687a ldr r2, [r7, #4] 800bca4: 6c92 ldr r2, [r2, #72] @ 0x48 800bca6: 00d2 lsls r2, r2, #3 800bca8: 491b ldr r1, [pc, #108] @ (800bd18 ) 800bcaa: 4313 orrs r3, r2 800bcac: 634b str r3, [r1, #52] @ 0x34 /* Select PLL1 input reference frequency range: VCI */ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 800bcae: 4b1a ldr r3, [pc, #104] @ (800bd18 ) 800bcb0: 6adb ldr r3, [r3, #44] @ 0x2c 800bcb2: f023 020c bic.w r2, r3, #12 800bcb6: 687b ldr r3, [r7, #4] 800bcb8: 6c1b ldr r3, [r3, #64] @ 0x40 800bcba: 4917 ldr r1, [pc, #92] @ (800bd18 ) 800bcbc: 4313 orrs r3, r2 800bcbe: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL1 output frequency range : VCO */ __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 800bcc0: 4b15 ldr r3, [pc, #84] @ (800bd18 ) 800bcc2: 6adb ldr r3, [r3, #44] @ 0x2c 800bcc4: f023 0202 bic.w r2, r3, #2 800bcc8: 687b ldr r3, [r7, #4] 800bcca: 6c5b ldr r3, [r3, #68] @ 0x44 800bccc: 4912 ldr r1, [pc, #72] @ (800bd18 ) 800bcce: 4313 orrs r3, r2 800bcd0: 62cb str r3, [r1, #44] @ 0x2c /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 800bcd2: 4b11 ldr r3, [pc, #68] @ (800bd18 ) 800bcd4: 6adb ldr r3, [r3, #44] @ 0x2c 800bcd6: 4a10 ldr r2, [pc, #64] @ (800bd18 ) 800bcd8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800bcdc: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1Q Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800bcde: 4b0e ldr r3, [pc, #56] @ (800bd18 ) 800bce0: 6adb ldr r3, [r3, #44] @ 0x2c 800bce2: 4a0d ldr r2, [pc, #52] @ (800bd18 ) 800bce4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800bce8: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1R Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 800bcea: 4b0b ldr r3, [pc, #44] @ (800bd18 ) 800bcec: 6adb ldr r3, [r3, #44] @ 0x2c 800bcee: 4a0a ldr r2, [pc, #40] @ (800bd18 ) 800bcf0: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800bcf4: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1FRACN . */ __HAL_RCC_PLLFRACN_ENABLE(); 800bcf6: 4b08 ldr r3, [pc, #32] @ (800bd18 ) 800bcf8: 6adb ldr r3, [r3, #44] @ 0x2c 800bcfa: 4a07 ldr r2, [pc, #28] @ (800bd18 ) 800bcfc: f043 0301 orr.w r3, r3, #1 800bd00: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800bd02: 4b05 ldr r3, [pc, #20] @ (800bd18 ) 800bd04: 681b ldr r3, [r3, #0] 800bd06: 4a04 ldr r2, [pc, #16] @ (800bd18 ) 800bd08: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800bd0c: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bd0e: f7f9 fdc5 bl 800589c 800bd12: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800bd14: e011 b.n 800bd3a 800bd16: bf00 nop 800bd18: 58024400 .word 0x58024400 800bd1c: 58024800 .word 0x58024800 800bd20: fffffc0c .word 0xfffffc0c 800bd24: ffff0007 .word 0xffff0007 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800bd28: f7f9 fdb8 bl 800589c 800bd2c: 4602 mov r2, r0 800bd2e: 6a7b ldr r3, [r7, #36] @ 0x24 800bd30: 1ad3 subs r3, r2, r3 800bd32: 2b02 cmp r3, #2 800bd34: d901 bls.n 800bd3a { return HAL_TIMEOUT; 800bd36: 2303 movs r3, #3 800bd38: e08a b.n 800be50 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800bd3a: 4b47 ldr r3, [pc, #284] @ (800be58 ) 800bd3c: 681b ldr r3, [r3, #0] 800bd3e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800bd42: 2b00 cmp r3, #0 800bd44: d0f0 beq.n 800bd28 800bd46: e082 b.n 800be4e } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800bd48: 4b43 ldr r3, [pc, #268] @ (800be58 ) 800bd4a: 681b ldr r3, [r3, #0] 800bd4c: 4a42 ldr r2, [pc, #264] @ (800be58 ) 800bd4e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800bd52: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bd54: f7f9 fda2 bl 800589c 800bd58: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800bd5a: e008 b.n 800bd6e { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800bd5c: f7f9 fd9e bl 800589c 800bd60: 4602 mov r2, r0 800bd62: 6a7b ldr r3, [r7, #36] @ 0x24 800bd64: 1ad3 subs r3, r2, r3 800bd66: 2b02 cmp r3, #2 800bd68: d901 bls.n 800bd6e { return HAL_TIMEOUT; 800bd6a: 2303 movs r3, #3 800bd6c: e070 b.n 800be50 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800bd6e: 4b3a ldr r3, [pc, #232] @ (800be58 ) 800bd70: 681b ldr r3, [r3, #0] 800bd72: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800bd76: 2b00 cmp r3, #0 800bd78: d1f0 bne.n 800bd5c 800bd7a: e068 b.n 800be4e } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp1_pllckcfg = RCC->PLLCKSELR; 800bd7c: 4b36 ldr r3, [pc, #216] @ (800be58 ) 800bd7e: 6a9b ldr r3, [r3, #40] @ 0x28 800bd80: 613b str r3, [r7, #16] temp2_pllckcfg = RCC->PLL1DIVR; 800bd82: 4b35 ldr r3, [pc, #212] @ (800be58 ) 800bd84: 6b1b ldr r3, [r3, #48] @ 0x30 800bd86: 60fb str r3, [r7, #12] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800bd88: 687b ldr r3, [r7, #4] 800bd8a: 6a5b ldr r3, [r3, #36] @ 0x24 800bd8c: 2b01 cmp r3, #1 800bd8e: d031 beq.n 800bdf4 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800bd90: 693b ldr r3, [r7, #16] 800bd92: f003 0203 and.w r2, r3, #3 800bd96: 687b ldr r3, [r7, #4] 800bd98: 6a9b ldr r3, [r3, #40] @ 0x28 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800bd9a: 429a cmp r2, r3 800bd9c: d12a bne.n 800bdf4 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800bd9e: 693b ldr r3, [r7, #16] 800bda0: 091b lsrs r3, r3, #4 800bda2: f003 023f and.w r2, r3, #63 @ 0x3f 800bda6: 687b ldr r3, [r7, #4] 800bda8: 6adb ldr r3, [r3, #44] @ 0x2c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800bdaa: 429a cmp r2, r3 800bdac: d122 bne.n 800bdf4 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800bdae: 68fb ldr r3, [r7, #12] 800bdb0: f3c3 0208 ubfx r2, r3, #0, #9 800bdb4: 687b ldr r3, [r7, #4] 800bdb6: 6b1b ldr r3, [r3, #48] @ 0x30 800bdb8: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800bdba: 429a cmp r2, r3 800bdbc: d11a bne.n 800bdf4 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800bdbe: 68fb ldr r3, [r7, #12] 800bdc0: 0a5b lsrs r3, r3, #9 800bdc2: f003 027f and.w r2, r3, #127 @ 0x7f 800bdc6: 687b ldr r3, [r7, #4] 800bdc8: 6b5b ldr r3, [r3, #52] @ 0x34 800bdca: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800bdcc: 429a cmp r2, r3 800bdce: d111 bne.n 800bdf4 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 800bdd0: 68fb ldr r3, [r7, #12] 800bdd2: 0c1b lsrs r3, r3, #16 800bdd4: f003 027f and.w r2, r3, #127 @ 0x7f 800bdd8: 687b ldr r3, [r7, #4] 800bdda: 6b9b ldr r3, [r3, #56] @ 0x38 800bddc: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800bdde: 429a cmp r2, r3 800bde0: d108 bne.n 800bdf4 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 800bde2: 68fb ldr r3, [r7, #12] 800bde4: 0e1b lsrs r3, r3, #24 800bde6: f003 027f and.w r2, r3, #127 @ 0x7f 800bdea: 687b ldr r3, [r7, #4] 800bdec: 6bdb ldr r3, [r3, #60] @ 0x3c 800bdee: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 800bdf0: 429a cmp r2, r3 800bdf2: d001 beq.n 800bdf8 { return HAL_ERROR; 800bdf4: 2301 movs r3, #1 800bdf6: e02b b.n 800be50 } else { /* Check if only fractional part needs to be updated */ temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); 800bdf8: 4b17 ldr r3, [pc, #92] @ (800be58 ) 800bdfa: 6b5b ldr r3, [r3, #52] @ 0x34 800bdfc: 08db lsrs r3, r3, #3 800bdfe: f3c3 030c ubfx r3, r3, #0, #13 800be02: 613b str r3, [r7, #16] if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) 800be04: 687b ldr r3, [r7, #4] 800be06: 6c9b ldr r3, [r3, #72] @ 0x48 800be08: 693a ldr r2, [r7, #16] 800be0a: 429a cmp r2, r3 800be0c: d01f beq.n 800be4e { assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable PLL1FRACEN */ __HAL_RCC_PLLFRACN_DISABLE(); 800be0e: 4b12 ldr r3, [pc, #72] @ (800be58 ) 800be10: 6adb ldr r3, [r3, #44] @ 0x2c 800be12: 4a11 ldr r2, [pc, #68] @ (800be58 ) 800be14: f023 0301 bic.w r3, r3, #1 800be18: 62d3 str r3, [r2, #44] @ 0x2c /* Get Start Tick*/ tickstart = HAL_GetTick(); 800be1a: f7f9 fd3f bl 800589c 800be1e: 6278 str r0, [r7, #36] @ 0x24 /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) 800be20: bf00 nop 800be22: f7f9 fd3b bl 800589c 800be26: 4602 mov r2, r0 800be28: 6a7b ldr r3, [r7, #36] @ 0x24 800be2a: 4293 cmp r3, r2 800be2c: d0f9 beq.n 800be22 { } /* Configure PLL1 PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800be2e: 4b0a ldr r3, [pc, #40] @ (800be58 ) 800be30: 6b5a ldr r2, [r3, #52] @ 0x34 800be32: 4b0a ldr r3, [pc, #40] @ (800be5c ) 800be34: 4013 ands r3, r2 800be36: 687a ldr r2, [r7, #4] 800be38: 6c92 ldr r2, [r2, #72] @ 0x48 800be3a: 00d2 lsls r2, r2, #3 800be3c: 4906 ldr r1, [pc, #24] @ (800be58 ) 800be3e: 4313 orrs r3, r2 800be40: 634b str r3, [r1, #52] @ 0x34 /* Enable PLL1FRACEN to latch new value. */ __HAL_RCC_PLLFRACN_ENABLE(); 800be42: 4b05 ldr r3, [pc, #20] @ (800be58 ) 800be44: 6adb ldr r3, [r3, #44] @ 0x2c 800be46: 4a04 ldr r2, [pc, #16] @ (800be58 ) 800be48: f043 0301 orr.w r3, r3, #1 800be4c: 62d3 str r3, [r2, #44] @ 0x2c } } } } return HAL_OK; 800be4e: 2300 movs r3, #0 } 800be50: 4618 mov r0, r3 800be52: 3730 adds r7, #48 @ 0x30 800be54: 46bd mov sp, r7 800be56: bd80 pop {r7, pc} 800be58: 58024400 .word 0x58024400 800be5c: ffff0007 .word 0xffff0007 0800be60 : * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800be60: b580 push {r7, lr} 800be62: b086 sub sp, #24 800be64: af00 add r7, sp, #0 800be66: 6078 str r0, [r7, #4] 800be68: 6039 str r1, [r7, #0] HAL_StatusTypeDef halstatus; uint32_t tickstart; uint32_t common_system_clock; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800be6a: 687b ldr r3, [r7, #4] 800be6c: 2b00 cmp r3, #0 800be6e: d101 bne.n 800be74 { return HAL_ERROR; 800be70: 2301 movs r3, #1 800be72: e19c b.n 800c1ae /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 800be74: 4b8a ldr r3, [pc, #552] @ (800c0a0 ) 800be76: 681b ldr r3, [r3, #0] 800be78: f003 030f and.w r3, r3, #15 800be7c: 683a ldr r2, [r7, #0] 800be7e: 429a cmp r2, r3 800be80: d910 bls.n 800bea4 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800be82: 4b87 ldr r3, [pc, #540] @ (800c0a0 ) 800be84: 681b ldr r3, [r3, #0] 800be86: f023 020f bic.w r2, r3, #15 800be8a: 4985 ldr r1, [pc, #532] @ (800c0a0 ) 800be8c: 683b ldr r3, [r7, #0] 800be8e: 4313 orrs r3, r2 800be90: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800be92: 4b83 ldr r3, [pc, #524] @ (800c0a0 ) 800be94: 681b ldr r3, [r3, #0] 800be96: f003 030f and.w r3, r3, #15 800be9a: 683a ldr r2, [r7, #0] 800be9c: 429a cmp r2, r3 800be9e: d001 beq.n 800bea4 { return HAL_ERROR; 800bea0: 2301 movs r3, #1 800bea2: e184 b.n 800c1ae } /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 800bea4: 687b ldr r3, [r7, #4] 800bea6: 681b ldr r3, [r3, #0] 800bea8: f003 0304 and.w r3, r3, #4 800beac: 2b00 cmp r3, #0 800beae: d010 beq.n 800bed2 { #if defined (RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 800beb0: 687b ldr r3, [r7, #4] 800beb2: 691a ldr r2, [r3, #16] 800beb4: 4b7b ldr r3, [pc, #492] @ (800c0a4 ) 800beb6: 699b ldr r3, [r3, #24] 800beb8: f003 0370 and.w r3, r3, #112 @ 0x70 800bebc: 429a cmp r2, r3 800bebe: d908 bls.n 800bed2 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 800bec0: 4b78 ldr r3, [pc, #480] @ (800c0a4 ) 800bec2: 699b ldr r3, [r3, #24] 800bec4: f023 0270 bic.w r2, r3, #112 @ 0x70 800bec8: 687b ldr r3, [r7, #4] 800beca: 691b ldr r3, [r3, #16] 800becc: 4975 ldr r1, [pc, #468] @ (800c0a4 ) 800bece: 4313 orrs r3, r2 800bed0: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800bed2: 687b ldr r3, [r7, #4] 800bed4: 681b ldr r3, [r3, #0] 800bed6: f003 0308 and.w r3, r3, #8 800beda: 2b00 cmp r3, #0 800bedc: d010 beq.n 800bf00 { #if defined (RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800bede: 687b ldr r3, [r7, #4] 800bee0: 695a ldr r2, [r3, #20] 800bee2: 4b70 ldr r3, [pc, #448] @ (800c0a4 ) 800bee4: 69db ldr r3, [r3, #28] 800bee6: f003 0370 and.w r3, r3, #112 @ 0x70 800beea: 429a cmp r2, r3 800beec: d908 bls.n 800bf00 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800beee: 4b6d ldr r3, [pc, #436] @ (800c0a4 ) 800bef0: 69db ldr r3, [r3, #28] 800bef2: f023 0270 bic.w r2, r3, #112 @ 0x70 800bef6: 687b ldr r3, [r7, #4] 800bef8: 695b ldr r3, [r3, #20] 800befa: 496a ldr r1, [pc, #424] @ (800c0a4 ) 800befc: 4313 orrs r3, r2 800befe: 61cb str r3, [r1, #28] MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800bf00: 687b ldr r3, [r7, #4] 800bf02: 681b ldr r3, [r3, #0] 800bf04: f003 0310 and.w r3, r3, #16 800bf08: 2b00 cmp r3, #0 800bf0a: d010 beq.n 800bf2e { #if defined(RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800bf0c: 687b ldr r3, [r7, #4] 800bf0e: 699a ldr r2, [r3, #24] 800bf10: 4b64 ldr r3, [pc, #400] @ (800c0a4 ) 800bf12: 69db ldr r3, [r3, #28] 800bf14: f403 63e0 and.w r3, r3, #1792 @ 0x700 800bf18: 429a cmp r2, r3 800bf1a: d908 bls.n 800bf2e { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800bf1c: 4b61 ldr r3, [pc, #388] @ (800c0a4 ) 800bf1e: 69db ldr r3, [r3, #28] 800bf20: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800bf24: 687b ldr r3, [r7, #4] 800bf26: 699b ldr r3, [r3, #24] 800bf28: 495e ldr r1, [pc, #376] @ (800c0a4 ) 800bf2a: 4313 orrs r3, r2 800bf2c: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800bf2e: 687b ldr r3, [r7, #4] 800bf30: 681b ldr r3, [r3, #0] 800bf32: f003 0320 and.w r3, r3, #32 800bf36: 2b00 cmp r3, #0 800bf38: d010 beq.n 800bf5c { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800bf3a: 687b ldr r3, [r7, #4] 800bf3c: 69da ldr r2, [r3, #28] 800bf3e: 4b59 ldr r3, [pc, #356] @ (800c0a4 ) 800bf40: 6a1b ldr r3, [r3, #32] 800bf42: f003 0370 and.w r3, r3, #112 @ 0x70 800bf46: 429a cmp r2, r3 800bf48: d908 bls.n 800bf5c { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800bf4a: 4b56 ldr r3, [pc, #344] @ (800c0a4 ) 800bf4c: 6a1b ldr r3, [r3, #32] 800bf4e: f023 0270 bic.w r2, r3, #112 @ 0x70 800bf52: 687b ldr r3, [r7, #4] 800bf54: 69db ldr r3, [r3, #28] 800bf56: 4953 ldr r1, [pc, #332] @ (800c0a4 ) 800bf58: 4313 orrs r3, r2 800bf5a: 620b str r3, [r1, #32] } #endif } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800bf5c: 687b ldr r3, [r7, #4] 800bf5e: 681b ldr r3, [r3, #0] 800bf60: f003 0302 and.w r3, r3, #2 800bf64: 2b00 cmp r3, #0 800bf66: d010 beq.n 800bf8a { #if defined (RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800bf68: 687b ldr r3, [r7, #4] 800bf6a: 68da ldr r2, [r3, #12] 800bf6c: 4b4d ldr r3, [pc, #308] @ (800c0a4 ) 800bf6e: 699b ldr r3, [r3, #24] 800bf70: f003 030f and.w r3, r3, #15 800bf74: 429a cmp r2, r3 800bf76: d908 bls.n 800bf8a { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800bf78: 4b4a ldr r3, [pc, #296] @ (800c0a4 ) 800bf7a: 699b ldr r3, [r3, #24] 800bf7c: f023 020f bic.w r2, r3, #15 800bf80: 687b ldr r3, [r7, #4] 800bf82: 68db ldr r3, [r3, #12] 800bf84: 4947 ldr r1, [pc, #284] @ (800c0a4 ) 800bf86: 4313 orrs r3, r2 800bf88: 618b str r3, [r1, #24] } #endif } /*------------------------- SYSCLK Configuration -------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800bf8a: 687b ldr r3, [r7, #4] 800bf8c: 681b ldr r3, [r3, #0] 800bf8e: f003 0301 and.w r3, r3, #1 800bf92: 2b00 cmp r3, #0 800bf94: d055 beq.n 800c042 { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_D1CFGR_D1CPRE) MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); 800bf96: 4b43 ldr r3, [pc, #268] @ (800c0a4 ) 800bf98: 699b ldr r3, [r3, #24] 800bf9a: f423 6270 bic.w r2, r3, #3840 @ 0xf00 800bf9e: 687b ldr r3, [r7, #4] 800bfa0: 689b ldr r3, [r3, #8] 800bfa2: 4940 ldr r1, [pc, #256] @ (800c0a4 ) 800bfa4: 4313 orrs r3, r2 800bfa6: 618b str r3, [r1, #24] #else MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); #endif /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800bfa8: 687b ldr r3, [r7, #4] 800bfaa: 685b ldr r3, [r3, #4] 800bfac: 2b02 cmp r3, #2 800bfae: d107 bne.n 800bfc0 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800bfb0: 4b3c ldr r3, [pc, #240] @ (800c0a4 ) 800bfb2: 681b ldr r3, [r3, #0] 800bfb4: f403 3300 and.w r3, r3, #131072 @ 0x20000 800bfb8: 2b00 cmp r3, #0 800bfba: d121 bne.n 800c000 { return HAL_ERROR; 800bfbc: 2301 movs r3, #1 800bfbe: e0f6 b.n 800c1ae } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800bfc0: 687b ldr r3, [r7, #4] 800bfc2: 685b ldr r3, [r3, #4] 800bfc4: 2b03 cmp r3, #3 800bfc6: d107 bne.n 800bfd8 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800bfc8: 4b36 ldr r3, [pc, #216] @ (800c0a4 ) 800bfca: 681b ldr r3, [r3, #0] 800bfcc: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800bfd0: 2b00 cmp r3, #0 800bfd2: d115 bne.n 800c000 { return HAL_ERROR; 800bfd4: 2301 movs r3, #1 800bfd6: e0ea b.n 800c1ae } } /* CSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 800bfd8: 687b ldr r3, [r7, #4] 800bfda: 685b ldr r3, [r3, #4] 800bfdc: 2b01 cmp r3, #1 800bfde: d107 bne.n 800bff0 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800bfe0: 4b30 ldr r3, [pc, #192] @ (800c0a4 ) 800bfe2: 681b ldr r3, [r3, #0] 800bfe4: f403 7380 and.w r3, r3, #256 @ 0x100 800bfe8: 2b00 cmp r3, #0 800bfea: d109 bne.n 800c000 { return HAL_ERROR; 800bfec: 2301 movs r3, #1 800bfee: e0de b.n 800c1ae } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800bff0: 4b2c ldr r3, [pc, #176] @ (800c0a4 ) 800bff2: 681b ldr r3, [r3, #0] 800bff4: f003 0304 and.w r3, r3, #4 800bff8: 2b00 cmp r3, #0 800bffa: d101 bne.n 800c000 { return HAL_ERROR; 800bffc: 2301 movs r3, #1 800bffe: e0d6 b.n 800c1ae } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 800c000: 4b28 ldr r3, [pc, #160] @ (800c0a4 ) 800c002: 691b ldr r3, [r3, #16] 800c004: f023 0207 bic.w r2, r3, #7 800c008: 687b ldr r3, [r7, #4] 800c00a: 685b ldr r3, [r3, #4] 800c00c: 4925 ldr r1, [pc, #148] @ (800c0a4 ) 800c00e: 4313 orrs r3, r2 800c010: 610b str r3, [r1, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c012: f7f9 fc43 bl 800589c 800c016: 6178 str r0, [r7, #20] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800c018: e00a b.n 800c030 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800c01a: f7f9 fc3f bl 800589c 800c01e: 4602 mov r2, r0 800c020: 697b ldr r3, [r7, #20] 800c022: 1ad3 subs r3, r2, r3 800c024: f241 3288 movw r2, #5000 @ 0x1388 800c028: 4293 cmp r3, r2 800c02a: d901 bls.n 800c030 { return HAL_TIMEOUT; 800c02c: 2303 movs r3, #3 800c02e: e0be b.n 800c1ae while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800c030: 4b1c ldr r3, [pc, #112] @ (800c0a4 ) 800c032: 691b ldr r3, [r3, #16] 800c034: f003 0238 and.w r2, r3, #56 @ 0x38 800c038: 687b ldr r3, [r7, #4] 800c03a: 685b ldr r3, [r3, #4] 800c03c: 00db lsls r3, r3, #3 800c03e: 429a cmp r2, r3 800c040: d1eb bne.n 800c01a } /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800c042: 687b ldr r3, [r7, #4] 800c044: 681b ldr r3, [r3, #0] 800c046: f003 0302 and.w r3, r3, #2 800c04a: 2b00 cmp r3, #0 800c04c: d010 beq.n 800c070 { #if defined(RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800c04e: 687b ldr r3, [r7, #4] 800c050: 68da ldr r2, [r3, #12] 800c052: 4b14 ldr r3, [pc, #80] @ (800c0a4 ) 800c054: 699b ldr r3, [r3, #24] 800c056: f003 030f and.w r3, r3, #15 800c05a: 429a cmp r2, r3 800c05c: d208 bcs.n 800c070 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800c05e: 4b11 ldr r3, [pc, #68] @ (800c0a4 ) 800c060: 699b ldr r3, [r3, #24] 800c062: f023 020f bic.w r2, r3, #15 800c066: 687b ldr r3, [r7, #4] 800c068: 68db ldr r3, [r3, #12] 800c06a: 490e ldr r1, [pc, #56] @ (800c0a4 ) 800c06c: 4313 orrs r3, r2 800c06e: 618b str r3, [r1, #24] } #endif } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 800c070: 4b0b ldr r3, [pc, #44] @ (800c0a0 ) 800c072: 681b ldr r3, [r3, #0] 800c074: f003 030f and.w r3, r3, #15 800c078: 683a ldr r2, [r7, #0] 800c07a: 429a cmp r2, r3 800c07c: d214 bcs.n 800c0a8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800c07e: 4b08 ldr r3, [pc, #32] @ (800c0a0 ) 800c080: 681b ldr r3, [r3, #0] 800c082: f023 020f bic.w r2, r3, #15 800c086: 4906 ldr r1, [pc, #24] @ (800c0a0 ) 800c088: 683b ldr r3, [r7, #0] 800c08a: 4313 orrs r3, r2 800c08c: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800c08e: 4b04 ldr r3, [pc, #16] @ (800c0a0 ) 800c090: 681b ldr r3, [r3, #0] 800c092: f003 030f and.w r3, r3, #15 800c096: 683a ldr r2, [r7, #0] 800c098: 429a cmp r2, r3 800c09a: d005 beq.n 800c0a8 { return HAL_ERROR; 800c09c: 2301 movs r3, #1 800c09e: e086 b.n 800c1ae 800c0a0: 52002000 .word 0x52002000 800c0a4: 58024400 .word 0x58024400 } } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 800c0a8: 687b ldr r3, [r7, #4] 800c0aa: 681b ldr r3, [r3, #0] 800c0ac: f003 0304 and.w r3, r3, #4 800c0b0: 2b00 cmp r3, #0 800c0b2: d010 beq.n 800c0d6 { #if defined(RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 800c0b4: 687b ldr r3, [r7, #4] 800c0b6: 691a ldr r2, [r3, #16] 800c0b8: 4b3f ldr r3, [pc, #252] @ (800c1b8 ) 800c0ba: 699b ldr r3, [r3, #24] 800c0bc: f003 0370 and.w r3, r3, #112 @ 0x70 800c0c0: 429a cmp r2, r3 800c0c2: d208 bcs.n 800c0d6 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 800c0c4: 4b3c ldr r3, [pc, #240] @ (800c1b8 ) 800c0c6: 699b ldr r3, [r3, #24] 800c0c8: f023 0270 bic.w r2, r3, #112 @ 0x70 800c0cc: 687b ldr r3, [r7, #4] 800c0ce: 691b ldr r3, [r3, #16] 800c0d0: 4939 ldr r1, [pc, #228] @ (800c1b8 ) 800c0d2: 4313 orrs r3, r2 800c0d4: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800c0d6: 687b ldr r3, [r7, #4] 800c0d8: 681b ldr r3, [r3, #0] 800c0da: f003 0308 and.w r3, r3, #8 800c0de: 2b00 cmp r3, #0 800c0e0: d010 beq.n 800c104 { #if defined(RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800c0e2: 687b ldr r3, [r7, #4] 800c0e4: 695a ldr r2, [r3, #20] 800c0e6: 4b34 ldr r3, [pc, #208] @ (800c1b8 ) 800c0e8: 69db ldr r3, [r3, #28] 800c0ea: f003 0370 and.w r3, r3, #112 @ 0x70 800c0ee: 429a cmp r2, r3 800c0f0: d208 bcs.n 800c104 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800c0f2: 4b31 ldr r3, [pc, #196] @ (800c1b8 ) 800c0f4: 69db ldr r3, [r3, #28] 800c0f6: f023 0270 bic.w r2, r3, #112 @ 0x70 800c0fa: 687b ldr r3, [r7, #4] 800c0fc: 695b ldr r3, [r3, #20] 800c0fe: 492e ldr r1, [pc, #184] @ (800c1b8 ) 800c100: 4313 orrs r3, r2 800c102: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800c104: 687b ldr r3, [r7, #4] 800c106: 681b ldr r3, [r3, #0] 800c108: f003 0310 and.w r3, r3, #16 800c10c: 2b00 cmp r3, #0 800c10e: d010 beq.n 800c132 { #if defined (RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800c110: 687b ldr r3, [r7, #4] 800c112: 699a ldr r2, [r3, #24] 800c114: 4b28 ldr r3, [pc, #160] @ (800c1b8 ) 800c116: 69db ldr r3, [r3, #28] 800c118: f403 63e0 and.w r3, r3, #1792 @ 0x700 800c11c: 429a cmp r2, r3 800c11e: d208 bcs.n 800c132 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800c120: 4b25 ldr r3, [pc, #148] @ (800c1b8 ) 800c122: 69db ldr r3, [r3, #28] 800c124: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800c128: 687b ldr r3, [r7, #4] 800c12a: 699b ldr r3, [r3, #24] 800c12c: 4922 ldr r1, [pc, #136] @ (800c1b8 ) 800c12e: 4313 orrs r3, r2 800c130: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800c132: 687b ldr r3, [r7, #4] 800c134: 681b ldr r3, [r3, #0] 800c136: f003 0320 and.w r3, r3, #32 800c13a: 2b00 cmp r3, #0 800c13c: d010 beq.n 800c160 { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800c13e: 687b ldr r3, [r7, #4] 800c140: 69da ldr r2, [r3, #28] 800c142: 4b1d ldr r3, [pc, #116] @ (800c1b8 ) 800c144: 6a1b ldr r3, [r3, #32] 800c146: f003 0370 and.w r3, r3, #112 @ 0x70 800c14a: 429a cmp r2, r3 800c14c: d208 bcs.n 800c160 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800c14e: 4b1a ldr r3, [pc, #104] @ (800c1b8 ) 800c150: 6a1b ldr r3, [r3, #32] 800c152: f023 0270 bic.w r2, r3, #112 @ 0x70 800c156: 687b ldr r3, [r7, #4] 800c158: 69db ldr r3, [r3, #28] 800c15a: 4917 ldr r1, [pc, #92] @ (800c1b8 ) 800c15c: 4313 orrs r3, r2 800c15e: 620b str r3, [r1, #32] #endif } /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 800c160: f000 f834 bl 800c1cc 800c164: 4602 mov r2, r0 800c166: 4b14 ldr r3, [pc, #80] @ (800c1b8 ) 800c168: 699b ldr r3, [r3, #24] 800c16a: 0a1b lsrs r3, r3, #8 800c16c: f003 030f and.w r3, r3, #15 800c170: 4912 ldr r1, [pc, #72] @ (800c1bc ) 800c172: 5ccb ldrb r3, [r1, r3] 800c174: f003 031f and.w r3, r3, #31 800c178: fa22 f303 lsr.w r3, r2, r3 800c17c: 613b str r3, [r7, #16] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800c17e: 4b0e ldr r3, [pc, #56] @ (800c1b8 ) 800c180: 699b ldr r3, [r3, #24] 800c182: f003 030f and.w r3, r3, #15 800c186: 4a0d ldr r2, [pc, #52] @ (800c1bc ) 800c188: 5cd3 ldrb r3, [r2, r3] 800c18a: f003 031f and.w r3, r3, #31 800c18e: 693a ldr r2, [r7, #16] 800c190: fa22 f303 lsr.w r3, r2, r3 800c194: 4a0a ldr r2, [pc, #40] @ (800c1c0 ) 800c196: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 800c198: 4a0a ldr r2, [pc, #40] @ (800c1c4 ) 800c19a: 693b ldr r3, [r7, #16] 800c19c: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick(uwTickPrio); 800c19e: 4b0a ldr r3, [pc, #40] @ (800c1c8 ) 800c1a0: 681b ldr r3, [r3, #0] 800c1a2: 4618 mov r0, r3 800c1a4: f7f7 ff84 bl 80040b0 800c1a8: 4603 mov r3, r0 800c1aa: 73fb strb r3, [r7, #15] return halstatus; 800c1ac: 7bfb ldrb r3, [r7, #15] } 800c1ae: 4618 mov r0, r3 800c1b0: 3718 adds r7, #24 800c1b2: 46bd mov sp, r7 800c1b4: bd80 pop {r7, pc} 800c1b6: bf00 nop 800c1b8: 58024400 .word 0x58024400 800c1bc: 0801a288 .word 0x0801a288 800c1c0: 24000038 .word 0x24000038 800c1c4: 24000034 .word 0x24000034 800c1c8: 2400003c .word 0x2400003c 0800c1cc : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800c1cc: b480 push {r7} 800c1ce: b089 sub sp, #36 @ 0x24 800c1d0: af00 add r7, sp, #0 float_t fracn1, pllvco; uint32_t sysclockfreq; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 800c1d2: 4bb3 ldr r3, [pc, #716] @ (800c4a0 ) 800c1d4: 691b ldr r3, [r3, #16] 800c1d6: f003 0338 and.w r3, r3, #56 @ 0x38 800c1da: 2b18 cmp r3, #24 800c1dc: f200 8155 bhi.w 800c48a 800c1e0: a201 add r2, pc, #4 @ (adr r2, 800c1e8 ) 800c1e2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c1e6: bf00 nop 800c1e8: 0800c24d .word 0x0800c24d 800c1ec: 0800c48b .word 0x0800c48b 800c1f0: 0800c48b .word 0x0800c48b 800c1f4: 0800c48b .word 0x0800c48b 800c1f8: 0800c48b .word 0x0800c48b 800c1fc: 0800c48b .word 0x0800c48b 800c200: 0800c48b .word 0x0800c48b 800c204: 0800c48b .word 0x0800c48b 800c208: 0800c273 .word 0x0800c273 800c20c: 0800c48b .word 0x0800c48b 800c210: 0800c48b .word 0x0800c48b 800c214: 0800c48b .word 0x0800c48b 800c218: 0800c48b .word 0x0800c48b 800c21c: 0800c48b .word 0x0800c48b 800c220: 0800c48b .word 0x0800c48b 800c224: 0800c48b .word 0x0800c48b 800c228: 0800c279 .word 0x0800c279 800c22c: 0800c48b .word 0x0800c48b 800c230: 0800c48b .word 0x0800c48b 800c234: 0800c48b .word 0x0800c48b 800c238: 0800c48b .word 0x0800c48b 800c23c: 0800c48b .word 0x0800c48b 800c240: 0800c48b .word 0x0800c48b 800c244: 0800c48b .word 0x0800c48b 800c248: 0800c27f .word 0x0800c27f { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800c24c: 4b94 ldr r3, [pc, #592] @ (800c4a0 ) 800c24e: 681b ldr r3, [r3, #0] 800c250: f003 0320 and.w r3, r3, #32 800c254: 2b00 cmp r3, #0 800c256: d009 beq.n 800c26c { sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800c258: 4b91 ldr r3, [pc, #580] @ (800c4a0 ) 800c25a: 681b ldr r3, [r3, #0] 800c25c: 08db lsrs r3, r3, #3 800c25e: f003 0303 and.w r3, r3, #3 800c262: 4a90 ldr r2, [pc, #576] @ (800c4a4 ) 800c264: fa22 f303 lsr.w r3, r2, r3 800c268: 61bb str r3, [r7, #24] else { sysclockfreq = (uint32_t) HSI_VALUE; } break; 800c26a: e111 b.n 800c490 sysclockfreq = (uint32_t) HSI_VALUE; 800c26c: 4b8d ldr r3, [pc, #564] @ (800c4a4 ) 800c26e: 61bb str r3, [r7, #24] break; 800c270: e10e b.n 800c490 case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ sysclockfreq = CSI_VALUE; 800c272: 4b8d ldr r3, [pc, #564] @ (800c4a8 ) 800c274: 61bb str r3, [r7, #24] break; 800c276: e10b b.n 800c490 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 800c278: 4b8c ldr r3, [pc, #560] @ (800c4ac ) 800c27a: 61bb str r3, [r7, #24] break; 800c27c: e108 b.n 800c490 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800c27e: 4b88 ldr r3, [pc, #544] @ (800c4a0 ) 800c280: 6a9b ldr r3, [r3, #40] @ 0x28 800c282: f003 0303 and.w r3, r3, #3 800c286: 617b str r3, [r7, #20] pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; 800c288: 4b85 ldr r3, [pc, #532] @ (800c4a0 ) 800c28a: 6a9b ldr r3, [r3, #40] @ 0x28 800c28c: 091b lsrs r3, r3, #4 800c28e: f003 033f and.w r3, r3, #63 @ 0x3f 800c292: 613b str r3, [r7, #16] pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); 800c294: 4b82 ldr r3, [pc, #520] @ (800c4a0 ) 800c296: 6adb ldr r3, [r3, #44] @ 0x2c 800c298: f003 0301 and.w r3, r3, #1 800c29c: 60fb str r3, [r7, #12] fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800c29e: 4b80 ldr r3, [pc, #512] @ (800c4a0 ) 800c2a0: 6b5b ldr r3, [r3, #52] @ 0x34 800c2a2: 08db lsrs r3, r3, #3 800c2a4: f3c3 030c ubfx r3, r3, #0, #13 800c2a8: 68fa ldr r2, [r7, #12] 800c2aa: fb02 f303 mul.w r3, r2, r3 800c2ae: ee07 3a90 vmov s15, r3 800c2b2: eef8 7a67 vcvt.f32.u32 s15, s15 800c2b6: edc7 7a02 vstr s15, [r7, #8] if (pllm != 0U) 800c2ba: 693b ldr r3, [r7, #16] 800c2bc: 2b00 cmp r3, #0 800c2be: f000 80e1 beq.w 800c484 800c2c2: 697b ldr r3, [r7, #20] 800c2c4: 2b02 cmp r3, #2 800c2c6: f000 8083 beq.w 800c3d0 800c2ca: 697b ldr r3, [r7, #20] 800c2cc: 2b02 cmp r3, #2 800c2ce: f200 80a1 bhi.w 800c414 800c2d2: 697b ldr r3, [r7, #20] 800c2d4: 2b00 cmp r3, #0 800c2d6: d003 beq.n 800c2e0 800c2d8: 697b ldr r3, [r7, #20] 800c2da: 2b01 cmp r3, #1 800c2dc: d056 beq.n 800c38c 800c2de: e099 b.n 800c414 { switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800c2e0: 4b6f ldr r3, [pc, #444] @ (800c4a0 ) 800c2e2: 681b ldr r3, [r3, #0] 800c2e4: f003 0320 and.w r3, r3, #32 800c2e8: 2b00 cmp r3, #0 800c2ea: d02d beq.n 800c348 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800c2ec: 4b6c ldr r3, [pc, #432] @ (800c4a0 ) 800c2ee: 681b ldr r3, [r3, #0] 800c2f0: 08db lsrs r3, r3, #3 800c2f2: f003 0303 and.w r3, r3, #3 800c2f6: 4a6b ldr r2, [pc, #428] @ (800c4a4 ) 800c2f8: fa22 f303 lsr.w r3, r2, r3 800c2fc: 607b str r3, [r7, #4] pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c2fe: 687b ldr r3, [r7, #4] 800c300: ee07 3a90 vmov s15, r3 800c304: eef8 6a67 vcvt.f32.u32 s13, s15 800c308: 693b ldr r3, [r7, #16] 800c30a: ee07 3a90 vmov s15, r3 800c30e: eef8 7a67 vcvt.f32.u32 s15, s15 800c312: ee86 7aa7 vdiv.f32 s14, s13, s15 800c316: 4b62 ldr r3, [pc, #392] @ (800c4a0 ) 800c318: 6b1b ldr r3, [r3, #48] @ 0x30 800c31a: f3c3 0308 ubfx r3, r3, #0, #9 800c31e: ee07 3a90 vmov s15, r3 800c322: eef8 6a67 vcvt.f32.u32 s13, s15 800c326: ed97 6a02 vldr s12, [r7, #8] 800c32a: eddf 5a61 vldr s11, [pc, #388] @ 800c4b0 800c32e: eec6 7a25 vdiv.f32 s15, s12, s11 800c332: ee76 7aa7 vadd.f32 s15, s13, s15 800c336: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c33a: ee77 7aa6 vadd.f32 s15, s15, s13 800c33e: ee67 7a27 vmul.f32 s15, s14, s15 800c342: edc7 7a07 vstr s15, [r7, #28] } else { pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 800c346: e087 b.n 800c458 pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c348: 693b ldr r3, [r7, #16] 800c34a: ee07 3a90 vmov s15, r3 800c34e: eef8 7a67 vcvt.f32.u32 s15, s15 800c352: eddf 6a58 vldr s13, [pc, #352] @ 800c4b4 800c356: ee86 7aa7 vdiv.f32 s14, s13, s15 800c35a: 4b51 ldr r3, [pc, #324] @ (800c4a0 ) 800c35c: 6b1b ldr r3, [r3, #48] @ 0x30 800c35e: f3c3 0308 ubfx r3, r3, #0, #9 800c362: ee07 3a90 vmov s15, r3 800c366: eef8 6a67 vcvt.f32.u32 s13, s15 800c36a: ed97 6a02 vldr s12, [r7, #8] 800c36e: eddf 5a50 vldr s11, [pc, #320] @ 800c4b0 800c372: eec6 7a25 vdiv.f32 s15, s12, s11 800c376: ee76 7aa7 vadd.f32 s15, s13, s15 800c37a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c37e: ee77 7aa6 vadd.f32 s15, s15, s13 800c382: ee67 7a27 vmul.f32 s15, s14, s15 800c386: edc7 7a07 vstr s15, [r7, #28] break; 800c38a: e065 b.n 800c458 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c38c: 693b ldr r3, [r7, #16] 800c38e: ee07 3a90 vmov s15, r3 800c392: eef8 7a67 vcvt.f32.u32 s15, s15 800c396: eddf 6a48 vldr s13, [pc, #288] @ 800c4b8 800c39a: ee86 7aa7 vdiv.f32 s14, s13, s15 800c39e: 4b40 ldr r3, [pc, #256] @ (800c4a0 ) 800c3a0: 6b1b ldr r3, [r3, #48] @ 0x30 800c3a2: f3c3 0308 ubfx r3, r3, #0, #9 800c3a6: ee07 3a90 vmov s15, r3 800c3aa: eef8 6a67 vcvt.f32.u32 s13, s15 800c3ae: ed97 6a02 vldr s12, [r7, #8] 800c3b2: eddf 5a3f vldr s11, [pc, #252] @ 800c4b0 800c3b6: eec6 7a25 vdiv.f32 s15, s12, s11 800c3ba: ee76 7aa7 vadd.f32 s15, s13, s15 800c3be: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c3c2: ee77 7aa6 vadd.f32 s15, s15, s13 800c3c6: ee67 7a27 vmul.f32 s15, s14, s15 800c3ca: edc7 7a07 vstr s15, [r7, #28] break; 800c3ce: e043 b.n 800c458 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c3d0: 693b ldr r3, [r7, #16] 800c3d2: ee07 3a90 vmov s15, r3 800c3d6: eef8 7a67 vcvt.f32.u32 s15, s15 800c3da: eddf 6a38 vldr s13, [pc, #224] @ 800c4bc 800c3de: ee86 7aa7 vdiv.f32 s14, s13, s15 800c3e2: 4b2f ldr r3, [pc, #188] @ (800c4a0 ) 800c3e4: 6b1b ldr r3, [r3, #48] @ 0x30 800c3e6: f3c3 0308 ubfx r3, r3, #0, #9 800c3ea: ee07 3a90 vmov s15, r3 800c3ee: eef8 6a67 vcvt.f32.u32 s13, s15 800c3f2: ed97 6a02 vldr s12, [r7, #8] 800c3f6: eddf 5a2e vldr s11, [pc, #184] @ 800c4b0 800c3fa: eec6 7a25 vdiv.f32 s15, s12, s11 800c3fe: ee76 7aa7 vadd.f32 s15, s13, s15 800c402: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c406: ee77 7aa6 vadd.f32 s15, s15, s13 800c40a: ee67 7a27 vmul.f32 s15, s14, s15 800c40e: edc7 7a07 vstr s15, [r7, #28] break; 800c412: e021 b.n 800c458 default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c414: 693b ldr r3, [r7, #16] 800c416: ee07 3a90 vmov s15, r3 800c41a: eef8 7a67 vcvt.f32.u32 s15, s15 800c41e: eddf 6a26 vldr s13, [pc, #152] @ 800c4b8 800c422: ee86 7aa7 vdiv.f32 s14, s13, s15 800c426: 4b1e ldr r3, [pc, #120] @ (800c4a0 ) 800c428: 6b1b ldr r3, [r3, #48] @ 0x30 800c42a: f3c3 0308 ubfx r3, r3, #0, #9 800c42e: ee07 3a90 vmov s15, r3 800c432: eef8 6a67 vcvt.f32.u32 s13, s15 800c436: ed97 6a02 vldr s12, [r7, #8] 800c43a: eddf 5a1d vldr s11, [pc, #116] @ 800c4b0 800c43e: eec6 7a25 vdiv.f32 s15, s12, s11 800c442: ee76 7aa7 vadd.f32 s15, s13, s15 800c446: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c44a: ee77 7aa6 vadd.f32 s15, s15, s13 800c44e: ee67 7a27 vmul.f32 s15, s14, s15 800c452: edc7 7a07 vstr s15, [r7, #28] break; 800c456: bf00 nop } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; 800c458: 4b11 ldr r3, [pc, #68] @ (800c4a0 ) 800c45a: 6b1b ldr r3, [r3, #48] @ 0x30 800c45c: 0a5b lsrs r3, r3, #9 800c45e: f003 037f and.w r3, r3, #127 @ 0x7f 800c462: 3301 adds r3, #1 800c464: 603b str r3, [r7, #0] sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); 800c466: 683b ldr r3, [r7, #0] 800c468: ee07 3a90 vmov s15, r3 800c46c: eeb8 7a67 vcvt.f32.u32 s14, s15 800c470: edd7 6a07 vldr s13, [r7, #28] 800c474: eec6 7a87 vdiv.f32 s15, s13, s14 800c478: eefc 7ae7 vcvt.u32.f32 s15, s15 800c47c: ee17 3a90 vmov r3, s15 800c480: 61bb str r3, [r7, #24] } else { sysclockfreq = 0U; } break; 800c482: e005 b.n 800c490 sysclockfreq = 0U; 800c484: 2300 movs r3, #0 800c486: 61bb str r3, [r7, #24] break; 800c488: e002 b.n 800c490 default: sysclockfreq = CSI_VALUE; 800c48a: 4b07 ldr r3, [pc, #28] @ (800c4a8 ) 800c48c: 61bb str r3, [r7, #24] break; 800c48e: bf00 nop } return sysclockfreq; 800c490: 69bb ldr r3, [r7, #24] } 800c492: 4618 mov r0, r3 800c494: 3724 adds r7, #36 @ 0x24 800c496: 46bd mov sp, r7 800c498: f85d 7b04 ldr.w r7, [sp], #4 800c49c: 4770 bx lr 800c49e: bf00 nop 800c4a0: 58024400 .word 0x58024400 800c4a4: 03d09000 .word 0x03d09000 800c4a8: 003d0900 .word 0x003d0900 800c4ac: 017d7840 .word 0x017d7840 800c4b0: 46000000 .word 0x46000000 800c4b4: 4c742400 .word 0x4c742400 800c4b8: 4a742400 .word 0x4a742400 800c4bc: 4bbebc20 .word 0x4bbebc20 0800c4c0 : * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 800c4c0: b580 push {r7, lr} 800c4c2: b082 sub sp, #8 800c4c4: af00 add r7, sp, #0 uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 800c4c6: f7ff fe81 bl 800c1cc 800c4ca: 4602 mov r2, r0 800c4cc: 4b10 ldr r3, [pc, #64] @ (800c510 ) 800c4ce: 699b ldr r3, [r3, #24] 800c4d0: 0a1b lsrs r3, r3, #8 800c4d2: f003 030f and.w r3, r3, #15 800c4d6: 490f ldr r1, [pc, #60] @ (800c514 ) 800c4d8: 5ccb ldrb r3, [r1, r3] 800c4da: f003 031f and.w r3, r3, #31 800c4de: fa22 f303 lsr.w r3, r2, r3 800c4e2: 607b str r3, [r7, #4] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800c4e4: 4b0a ldr r3, [pc, #40] @ (800c510 ) 800c4e6: 699b ldr r3, [r3, #24] 800c4e8: f003 030f and.w r3, r3, #15 800c4ec: 4a09 ldr r2, [pc, #36] @ (800c514 ) 800c4ee: 5cd3 ldrb r3, [r2, r3] 800c4f0: f003 031f and.w r3, r3, #31 800c4f4: 687a ldr r2, [r7, #4] 800c4f6: fa22 f303 lsr.w r3, r2, r3 800c4fa: 4a07 ldr r2, [pc, #28] @ (800c518 ) 800c4fc: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 800c4fe: 4a07 ldr r2, [pc, #28] @ (800c51c ) 800c500: 687b ldr r3, [r7, #4] 800c502: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ return SystemD2Clock; 800c504: 4b04 ldr r3, [pc, #16] @ (800c518 ) 800c506: 681b ldr r3, [r3, #0] } 800c508: 4618 mov r0, r3 800c50a: 3708 adds r7, #8 800c50c: 46bd mov sp, r7 800c50e: bd80 pop {r7, pc} 800c510: 58024400 .word 0x58024400 800c514: 0801a288 .word 0x0801a288 800c518: 24000038 .word 0x24000038 800c51c: 24000034 .word 0x24000034 0800c520 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 800c520: b580 push {r7, lr} 800c522: af00 add r7, sp, #0 #if defined (RCC_D2CFGR_D2PPRE1) /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); 800c524: f7ff ffcc bl 800c4c0 800c528: 4602 mov r2, r0 800c52a: 4b06 ldr r3, [pc, #24] @ (800c544 ) 800c52c: 69db ldr r3, [r3, #28] 800c52e: 091b lsrs r3, r3, #4 800c530: f003 0307 and.w r3, r3, #7 800c534: 4904 ldr r1, [pc, #16] @ (800c548 ) 800c536: 5ccb ldrb r3, [r1, r3] 800c538: f003 031f and.w r3, r3, #31 800c53c: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); #endif } 800c540: 4618 mov r0, r3 800c542: bd80 pop {r7, pc} 800c544: 58024400 .word 0x58024400 800c548: 0801a288 .word 0x0801a288 0800c54c : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 800c54c: b580 push {r7, lr} 800c54e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ #if defined(RCC_D2CFGR_D2PPRE2) return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); 800c550: f7ff ffb6 bl 800c4c0 800c554: 4602 mov r2, r0 800c556: 4b06 ldr r3, [pc, #24] @ (800c570 ) 800c558: 69db ldr r3, [r3, #28] 800c55a: 0a1b lsrs r3, r3, #8 800c55c: f003 0307 and.w r3, r3, #7 800c560: 4904 ldr r1, [pc, #16] @ (800c574 ) 800c562: 5ccb ldrb r3, [r1, r3] 800c564: f003 031f and.w r3, r3, #31 800c568: fa22 f303 lsr.w r3, r2, r3 #else return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); #endif } 800c56c: 4618 mov r0, r3 800c56e: bd80 pop {r7, pc} 800c570: 58024400 .word 0x58024400 800c574: 0801a288 .word 0x0801a288 0800c578 : * will be configured. * @param pFLatency: Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 800c578: b480 push {r7} 800c57a: b083 sub sp, #12 800c57c: af00 add r7, sp, #0 800c57e: 6078 str r0, [r7, #4] 800c580: 6039 str r1, [r7, #0] /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | 800c582: 687b ldr r3, [r7, #4] 800c584: 223f movs r2, #63 @ 0x3f 800c586: 601a str r2, [r3, #0] RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ; /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 800c588: 4b1a ldr r3, [pc, #104] @ (800c5f4 ) 800c58a: 691b ldr r3, [r3, #16] 800c58c: f003 0207 and.w r2, r3, #7 800c590: 687b ldr r3, [r7, #4] 800c592: 605a str r2, [r3, #4] #if defined(RCC_D1CFGR_D1CPRE) /* Get the SYSCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE); 800c594: 4b17 ldr r3, [pc, #92] @ (800c5f4 ) 800c596: 699b ldr r3, [r3, #24] 800c598: f403 6270 and.w r2, r3, #3840 @ 0xf00 800c59c: 687b ldr r3, [r7, #4] 800c59e: 609a str r2, [r3, #8] /* Get the D1HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE); 800c5a0: 4b14 ldr r3, [pc, #80] @ (800c5f4 ) 800c5a2: 699b ldr r3, [r3, #24] 800c5a4: f003 020f and.w r2, r3, #15 800c5a8: 687b ldr r3, [r7, #4] 800c5aa: 60da str r2, [r3, #12] /* Get the APB3 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE); 800c5ac: 4b11 ldr r3, [pc, #68] @ (800c5f4 ) 800c5ae: 699b ldr r3, [r3, #24] 800c5b0: f003 0270 and.w r2, r3, #112 @ 0x70 800c5b4: 687b ldr r3, [r7, #4] 800c5b6: 611a str r2, [r3, #16] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1); 800c5b8: 4b0e ldr r3, [pc, #56] @ (800c5f4 ) 800c5ba: 69db ldr r3, [r3, #28] 800c5bc: f003 0270 and.w r2, r3, #112 @ 0x70 800c5c0: 687b ldr r3, [r7, #4] 800c5c2: 615a str r2, [r3, #20] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2); 800c5c4: 4b0b ldr r3, [pc, #44] @ (800c5f4 ) 800c5c6: 69db ldr r3, [r3, #28] 800c5c8: f403 62e0 and.w r2, r3, #1792 @ 0x700 800c5cc: 687b ldr r3, [r7, #4] 800c5ce: 619a str r2, [r3, #24] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); 800c5d0: 4b08 ldr r3, [pc, #32] @ (800c5f4 ) 800c5d2: 6a1b ldr r3, [r3, #32] 800c5d4: f003 0270 and.w r2, r3, #112 @ 0x70 800c5d8: 687b ldr r3, [r7, #4] 800c5da: 61da str r2, [r3, #28] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE); #endif /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 800c5dc: 4b06 ldr r3, [pc, #24] @ (800c5f8 ) 800c5de: 681b ldr r3, [r3, #0] 800c5e0: f003 020f and.w r2, r3, #15 800c5e4: 683b ldr r3, [r7, #0] 800c5e6: 601a str r2, [r3, #0] } 800c5e8: bf00 nop 800c5ea: 370c adds r7, #12 800c5ec: 46bd mov sp, r7 800c5ee: f85d 7b04 ldr.w r7, [sp], #4 800c5f2: 4770 bx lr 800c5f4: 58024400 .word 0x58024400 800c5f8: 52002000 .word 0x52002000 0800c5fc : * (*) : Available on some STM32H7 lines only. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 800c5fc: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 800c600: b0c8 sub sp, #288 @ 0x120 800c602: af00 add r7, sp, #0 800c604: f8c7 010c str.w r0, [r7, #268] @ 0x10c uint32_t tmpreg; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 800c608: 2300 movs r3, #0 800c60a: f887 311f strb.w r3, [r7, #287] @ 0x11f HAL_StatusTypeDef status = HAL_OK; /* Final status */ 800c60e: 2300 movs r3, #0 800c610: f887 311e strb.w r3, [r7, #286] @ 0x11e /*---------------------------- SPDIFRX configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 800c614: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c618: e9d3 2300 ldrd r2, r3, [r3] 800c61c: f002 6400 and.w r4, r2, #134217728 @ 0x8000000 800c620: 2500 movs r5, #0 800c622: ea54 0305 orrs.w r3, r4, r5 800c626: d049 beq.n 800c6bc { switch (PeriphClkInit->SpdifrxClockSelection) 800c628: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c62c: 6e9b ldr r3, [r3, #104] @ 0x68 800c62e: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800c632: d02f beq.n 800c694 800c634: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800c638: d828 bhi.n 800c68c 800c63a: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800c63e: d01a beq.n 800c676 800c640: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800c644: d822 bhi.n 800c68c 800c646: 2b00 cmp r3, #0 800c648: d003 beq.n 800c652 800c64a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800c64e: d007 beq.n 800c660 800c650: e01c b.n 800c68c { case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c652: 4bb8 ldr r3, [pc, #736] @ (800c934 ) 800c654: 6adb ldr r3, [r3, #44] @ 0x2c 800c656: 4ab7 ldr r2, [pc, #732] @ (800c934 ) 800c658: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c65c: 62d3 str r3, [r2, #44] @ 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 800c65e: e01a b.n 800c696 case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800c660: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c664: 3308 adds r3, #8 800c666: 2102 movs r1, #2 800c668: 4618 mov r0, r3 800c66a: f002 fb45 bl 800ecf8 800c66e: 4603 mov r3, r0 800c670: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 800c674: e00f b.n 800c696 case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800c676: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c67a: 3328 adds r3, #40 @ 0x28 800c67c: 2102 movs r1, #2 800c67e: 4618 mov r0, r3 800c680: f002 fbec bl 800ee5c 800c684: 4603 mov r3, r0 800c686: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 800c68a: e004 b.n 800c696 /* Internal OSC clock is used as source of SPDIFRX clock*/ /* SPDIFRX clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800c68c: 2301 movs r3, #1 800c68e: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c692: e000 b.n 800c696 break; 800c694: bf00 nop } if (ret == HAL_OK) 800c696: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c69a: 2b00 cmp r3, #0 800c69c: d10a bne.n 800c6b4 { /* Set the source of SPDIFRX clock*/ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 800c69e: 4ba5 ldr r3, [pc, #660] @ (800c934 ) 800c6a0: 6d1b ldr r3, [r3, #80] @ 0x50 800c6a2: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800c6a6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c6aa: 6e9b ldr r3, [r3, #104] @ 0x68 800c6ac: 4aa1 ldr r2, [pc, #644] @ (800c934 ) 800c6ae: 430b orrs r3, r1 800c6b0: 6513 str r3, [r2, #80] @ 0x50 800c6b2: e003 b.n 800c6bc } else { /* set overall return value */ status = ret; 800c6b4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c6b8: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 800c6bc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c6c0: e9d3 2300 ldrd r2, r3, [r3] 800c6c4: f402 7880 and.w r8, r2, #256 @ 0x100 800c6c8: f04f 0900 mov.w r9, #0 800c6cc: ea58 0309 orrs.w r3, r8, r9 800c6d0: d047 beq.n 800c762 { switch (PeriphClkInit->Sai1ClockSelection) 800c6d2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c6d6: 6d9b ldr r3, [r3, #88] @ 0x58 800c6d8: 2b04 cmp r3, #4 800c6da: d82a bhi.n 800c732 800c6dc: a201 add r2, pc, #4 @ (adr r2, 800c6e4 ) 800c6de: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c6e2: bf00 nop 800c6e4: 0800c6f9 .word 0x0800c6f9 800c6e8: 0800c707 .word 0x0800c707 800c6ec: 0800c71d .word 0x0800c71d 800c6f0: 0800c73b .word 0x0800c73b 800c6f4: 0800c73b .word 0x0800c73b { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c6f8: 4b8e ldr r3, [pc, #568] @ (800c934 ) 800c6fa: 6adb ldr r3, [r3, #44] @ 0x2c 800c6fc: 4a8d ldr r2, [pc, #564] @ (800c934 ) 800c6fe: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c702: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800c704: e01a b.n 800c73c case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800c706: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c70a: 3308 adds r3, #8 800c70c: 2100 movs r1, #0 800c70e: 4618 mov r0, r3 800c710: f002 faf2 bl 800ecf8 800c714: 4603 mov r3, r0 800c716: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800c71a: e00f b.n 800c73c case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800c71c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c720: 3328 adds r3, #40 @ 0x28 800c722: 2100 movs r1, #0 800c724: 4618 mov r0, r3 800c726: f002 fb99 bl 800ee5c 800c72a: 4603 mov r3, r0 800c72c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800c730: e004 b.n 800c73c /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800c732: 2301 movs r3, #1 800c734: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c738: e000 b.n 800c73c break; 800c73a: bf00 nop } if (ret == HAL_OK) 800c73c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c740: 2b00 cmp r3, #0 800c742: d10a bne.n 800c75a { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 800c744: 4b7b ldr r3, [pc, #492] @ (800c934 ) 800c746: 6d1b ldr r3, [r3, #80] @ 0x50 800c748: f023 0107 bic.w r1, r3, #7 800c74c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c750: 6d9b ldr r3, [r3, #88] @ 0x58 800c752: 4a78 ldr r2, [pc, #480] @ (800c934 ) 800c754: 430b orrs r3, r1 800c756: 6513 str r3, [r2, #80] @ 0x50 800c758: e003 b.n 800c762 } else { /* set overall return value */ status = ret; 800c75a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c75e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #if defined(SAI3) /*---------------------------- SAI2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) 800c762: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c766: e9d3 2300 ldrd r2, r3, [r3] 800c76a: f402 7a00 and.w sl, r2, #512 @ 0x200 800c76e: f04f 0b00 mov.w fp, #0 800c772: ea5a 030b orrs.w r3, sl, fp 800c776: d04c beq.n 800c812 { switch (PeriphClkInit->Sai23ClockSelection) 800c778: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c77c: 6ddb ldr r3, [r3, #92] @ 0x5c 800c77e: f5b3 7f80 cmp.w r3, #256 @ 0x100 800c782: d030 beq.n 800c7e6 800c784: f5b3 7f80 cmp.w r3, #256 @ 0x100 800c788: d829 bhi.n 800c7de 800c78a: 2bc0 cmp r3, #192 @ 0xc0 800c78c: d02d beq.n 800c7ea 800c78e: 2bc0 cmp r3, #192 @ 0xc0 800c790: d825 bhi.n 800c7de 800c792: 2b80 cmp r3, #128 @ 0x80 800c794: d018 beq.n 800c7c8 800c796: 2b80 cmp r3, #128 @ 0x80 800c798: d821 bhi.n 800c7de 800c79a: 2b00 cmp r3, #0 800c79c: d002 beq.n 800c7a4 800c79e: 2b40 cmp r3, #64 @ 0x40 800c7a0: d007 beq.n 800c7b2 800c7a2: e01c b.n 800c7de { case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c7a4: 4b63 ldr r3, [pc, #396] @ (800c934 ) 800c7a6: 6adb ldr r3, [r3, #44] @ 0x2c 800c7a8: 4a62 ldr r2, [pc, #392] @ (800c934 ) 800c7aa: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c7ae: 62d3 str r3, [r2, #44] @ 0x2c /* SAI2/3 clock source configuration done later after clock selection check */ break; 800c7b0: e01c b.n 800c7ec case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800c7b2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c7b6: 3308 adds r3, #8 800c7b8: 2100 movs r1, #0 800c7ba: 4618 mov r0, r3 800c7bc: f002 fa9c bl 800ecf8 800c7c0: 4603 mov r3, r0 800c7c2: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 800c7c6: e011 b.n 800c7ec case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800c7c8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c7cc: 3328 adds r3, #40 @ 0x28 800c7ce: 2100 movs r1, #0 800c7d0: 4618 mov r0, r3 800c7d2: f002 fb43 bl 800ee5c 800c7d6: 4603 mov r3, r0 800c7d8: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 800c7dc: e006 b.n 800c7ec /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ /* SAI2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800c7de: 2301 movs r3, #1 800c7e0: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c7e4: e002 b.n 800c7ec break; 800c7e6: bf00 nop 800c7e8: e000 b.n 800c7ec break; 800c7ea: bf00 nop } if (ret == HAL_OK) 800c7ec: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c7f0: 2b00 cmp r3, #0 800c7f2: d10a bne.n 800c80a { /* Set the source of SAI2/3 clock*/ __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); 800c7f4: 4b4f ldr r3, [pc, #316] @ (800c934 ) 800c7f6: 6d1b ldr r3, [r3, #80] @ 0x50 800c7f8: f423 71e0 bic.w r1, r3, #448 @ 0x1c0 800c7fc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c800: 6ddb ldr r3, [r3, #92] @ 0x5c 800c802: 4a4c ldr r2, [pc, #304] @ (800c934 ) 800c804: 430b orrs r3, r1 800c806: 6513 str r3, [r2, #80] @ 0x50 800c808: e003 b.n 800c812 } else { /* set overall return value */ status = ret; 800c80a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c80e: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI2B*/ #if defined(SAI4) /*---------------------------- SAI4A configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 800c812: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c816: e9d3 2300 ldrd r2, r3, [r3] 800c81a: f402 6380 and.w r3, r2, #1024 @ 0x400 800c81e: f8c7 3100 str.w r3, [r7, #256] @ 0x100 800c822: 2300 movs r3, #0 800c824: f8c7 3104 str.w r3, [r7, #260] @ 0x104 800c828: e9d7 1240 ldrd r1, r2, [r7, #256] @ 0x100 800c82c: 460b mov r3, r1 800c82e: 4313 orrs r3, r2 800c830: d053 beq.n 800c8da { switch (PeriphClkInit->Sai4AClockSelection) 800c832: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c836: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 800c83a: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800c83e: d035 beq.n 800c8ac 800c840: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800c844: d82e bhi.n 800c8a4 800c846: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800c84a: d031 beq.n 800c8b0 800c84c: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800c850: d828 bhi.n 800c8a4 800c852: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800c856: d01a beq.n 800c88e 800c858: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800c85c: d822 bhi.n 800c8a4 800c85e: 2b00 cmp r3, #0 800c860: d003 beq.n 800c86a 800c862: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800c866: d007 beq.n 800c878 800c868: e01c b.n 800c8a4 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c86a: 4b32 ldr r3, [pc, #200] @ (800c934 ) 800c86c: 6adb ldr r3, [r3, #44] @ 0x2c 800c86e: 4a31 ldr r2, [pc, #196] @ (800c934 ) 800c870: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c874: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800c876: e01c b.n 800c8b2 case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800c878: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c87c: 3308 adds r3, #8 800c87e: 2100 movs r1, #0 800c880: 4618 mov r0, r3 800c882: f002 fa39 bl 800ecf8 800c886: 4603 mov r3, r0 800c888: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800c88c: e011 b.n 800c8b2 case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800c88e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c892: 3328 adds r3, #40 @ 0x28 800c894: 2100 movs r1, #0 800c896: 4618 mov r0, r3 800c898: f002 fae0 bl 800ee5c 800c89c: 4603 mov r3, r0 800c89e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800c8a2: e006 b.n 800c8b2 /* SAI4A clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800c8a4: 2301 movs r3, #1 800c8a6: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c8aa: e002 b.n 800c8b2 break; 800c8ac: bf00 nop 800c8ae: e000 b.n 800c8b2 break; 800c8b0: bf00 nop } if (ret == HAL_OK) 800c8b2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c8b6: 2b00 cmp r3, #0 800c8b8: d10b bne.n 800c8d2 { /* Set the source of SAI4A clock*/ __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); 800c8ba: 4b1e ldr r3, [pc, #120] @ (800c934 ) 800c8bc: 6d9b ldr r3, [r3, #88] @ 0x58 800c8be: f423 0160 bic.w r1, r3, #14680064 @ 0xe00000 800c8c2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c8c6: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 800c8ca: 4a1a ldr r2, [pc, #104] @ (800c934 ) 800c8cc: 430b orrs r3, r1 800c8ce: 6593 str r3, [r2, #88] @ 0x58 800c8d0: e003 b.n 800c8da } else { /* set overall return value */ status = ret; 800c8d2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c8d6: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI4B configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 800c8da: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c8de: e9d3 2300 ldrd r2, r3, [r3] 800c8e2: f402 6300 and.w r3, r2, #2048 @ 0x800 800c8e6: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 800c8ea: 2300 movs r3, #0 800c8ec: f8c7 30fc str.w r3, [r7, #252] @ 0xfc 800c8f0: e9d7 123e ldrd r1, r2, [r7, #248] @ 0xf8 800c8f4: 460b mov r3, r1 800c8f6: 4313 orrs r3, r2 800c8f8: d056 beq.n 800c9a8 { switch (PeriphClkInit->Sai4BClockSelection) 800c8fa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c8fe: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 800c902: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800c906: d038 beq.n 800c97a 800c908: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800c90c: d831 bhi.n 800c972 800c90e: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800c912: d034 beq.n 800c97e 800c914: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800c918: d82b bhi.n 800c972 800c91a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800c91e: d01d beq.n 800c95c 800c920: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800c924: d825 bhi.n 800c972 800c926: 2b00 cmp r3, #0 800c928: d006 beq.n 800c938 800c92a: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800c92e: d00a beq.n 800c946 800c930: e01f b.n 800c972 800c932: bf00 nop 800c934: 58024400 .word 0x58024400 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c938: 4ba2 ldr r3, [pc, #648] @ (800cbc4 ) 800c93a: 6adb ldr r3, [r3, #44] @ 0x2c 800c93c: 4aa1 ldr r2, [pc, #644] @ (800cbc4 ) 800c93e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c942: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800c944: e01c b.n 800c980 case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800c946: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c94a: 3308 adds r3, #8 800c94c: 2100 movs r1, #0 800c94e: 4618 mov r0, r3 800c950: f002 f9d2 bl 800ecf8 800c954: 4603 mov r3, r0 800c956: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800c95a: e011 b.n 800c980 case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800c95c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c960: 3328 adds r3, #40 @ 0x28 800c962: 2100 movs r1, #0 800c964: 4618 mov r0, r3 800c966: f002 fa79 bl 800ee5c 800c96a: 4603 mov r3, r0 800c96c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800c970: e006 b.n 800c980 /* SAI4B clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800c972: 2301 movs r3, #1 800c974: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c978: e002 b.n 800c980 break; 800c97a: bf00 nop 800c97c: e000 b.n 800c980 break; 800c97e: bf00 nop } if (ret == HAL_OK) 800c980: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c984: 2b00 cmp r3, #0 800c986: d10b bne.n 800c9a0 { /* Set the source of SAI4B clock*/ __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); 800c988: 4b8e ldr r3, [pc, #568] @ (800cbc4 ) 800c98a: 6d9b ldr r3, [r3, #88] @ 0x58 800c98c: f023 61e0 bic.w r1, r3, #117440512 @ 0x7000000 800c990: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c994: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 800c998: 4a8a ldr r2, [pc, #552] @ (800cbc4 ) 800c99a: 430b orrs r3, r1 800c99c: 6593 str r3, [r2, #88] @ 0x58 800c99e: e003 b.n 800c9a8 } else { /* set overall return value */ status = ret; 800c9a0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c9a4: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI4*/ #if defined(QUADSPI) /*---------------------------- QSPI configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) 800c9a8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c9ac: e9d3 2300 ldrd r2, r3, [r3] 800c9b0: f002 7300 and.w r3, r2, #33554432 @ 0x2000000 800c9b4: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0 800c9b8: 2300 movs r3, #0 800c9ba: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4 800c9be: e9d7 123c ldrd r1, r2, [r7, #240] @ 0xf0 800c9c2: 460b mov r3, r1 800c9c4: 4313 orrs r3, r2 800c9c6: d03a beq.n 800ca3e { switch (PeriphClkInit->QspiClockSelection) 800c9c8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c9cc: 6cdb ldr r3, [r3, #76] @ 0x4c 800c9ce: 2b30 cmp r3, #48 @ 0x30 800c9d0: d01f beq.n 800ca12 800c9d2: 2b30 cmp r3, #48 @ 0x30 800c9d4: d819 bhi.n 800ca0a 800c9d6: 2b20 cmp r3, #32 800c9d8: d00c beq.n 800c9f4 800c9da: 2b20 cmp r3, #32 800c9dc: d815 bhi.n 800ca0a 800c9de: 2b00 cmp r3, #0 800c9e0: d019 beq.n 800ca16 800c9e2: 2b10 cmp r3, #16 800c9e4: d111 bne.n 800ca0a { case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ /* Enable QSPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c9e6: 4b77 ldr r3, [pc, #476] @ (800cbc4 ) 800c9e8: 6adb ldr r3, [r3, #44] @ 0x2c 800c9ea: 4a76 ldr r2, [pc, #472] @ (800cbc4 ) 800c9ec: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c9f0: 62d3 str r3, [r2, #44] @ 0x2c /* QSPI clock source configuration done later after clock selection check */ break; 800c9f2: e011 b.n 800ca18 case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800c9f4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c9f8: 3308 adds r3, #8 800c9fa: 2102 movs r1, #2 800c9fc: 4618 mov r0, r3 800c9fe: f002 f97b bl 800ecf8 800ca02: 4603 mov r3, r0 800ca04: f887 311f strb.w r3, [r7, #287] @ 0x11f /* QSPI clock source configuration done later after clock selection check */ break; 800ca08: e006 b.n 800ca18 case RCC_QSPICLKSOURCE_D1HCLK: /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ break; default: ret = HAL_ERROR; 800ca0a: 2301 movs r3, #1 800ca0c: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ca10: e002 b.n 800ca18 break; 800ca12: bf00 nop 800ca14: e000 b.n 800ca18 break; 800ca16: bf00 nop } if (ret == HAL_OK) 800ca18: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ca1c: 2b00 cmp r3, #0 800ca1e: d10a bne.n 800ca36 { /* Set the source of QSPI clock*/ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); 800ca20: 4b68 ldr r3, [pc, #416] @ (800cbc4 ) 800ca22: 6cdb ldr r3, [r3, #76] @ 0x4c 800ca24: f023 0130 bic.w r1, r3, #48 @ 0x30 800ca28: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca2c: 6cdb ldr r3, [r3, #76] @ 0x4c 800ca2e: 4a65 ldr r2, [pc, #404] @ (800cbc4 ) 800ca30: 430b orrs r3, r1 800ca32: 64d3 str r3, [r2, #76] @ 0x4c 800ca34: e003 b.n 800ca3e } else { /* set overall return value */ status = ret; 800ca36: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ca3a: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 800ca3e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca42: e9d3 2300 ldrd r2, r3, [r3] 800ca46: f402 5380 and.w r3, r2, #4096 @ 0x1000 800ca4a: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 800ca4e: 2300 movs r3, #0 800ca50: f8c7 30ec str.w r3, [r7, #236] @ 0xec 800ca54: e9d7 123a ldrd r1, r2, [r7, #232] @ 0xe8 800ca58: 460b mov r3, r1 800ca5a: 4313 orrs r3, r2 800ca5c: d051 beq.n 800cb02 { switch (PeriphClkInit->Spi123ClockSelection) 800ca5e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca62: 6e1b ldr r3, [r3, #96] @ 0x60 800ca64: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800ca68: d035 beq.n 800cad6 800ca6a: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800ca6e: d82e bhi.n 800cace 800ca70: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800ca74: d031 beq.n 800cada 800ca76: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800ca7a: d828 bhi.n 800cace 800ca7c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800ca80: d01a beq.n 800cab8 800ca82: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800ca86: d822 bhi.n 800cace 800ca88: 2b00 cmp r3, #0 800ca8a: d003 beq.n 800ca94 800ca8c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800ca90: d007 beq.n 800caa2 800ca92: e01c b.n 800cace { case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800ca94: 4b4b ldr r3, [pc, #300] @ (800cbc4 ) 800ca96: 6adb ldr r3, [r3, #44] @ 0x2c 800ca98: 4a4a ldr r2, [pc, #296] @ (800cbc4 ) 800ca9a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800ca9e: 62d3 str r3, [r2, #44] @ 0x2c /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800caa0: e01c b.n 800cadc case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800caa2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800caa6: 3308 adds r3, #8 800caa8: 2100 movs r1, #0 800caaa: 4618 mov r0, r3 800caac: f002 f924 bl 800ecf8 800cab0: 4603 mov r3, r0 800cab2: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800cab6: e011 b.n 800cadc case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800cab8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cabc: 3328 adds r3, #40 @ 0x28 800cabe: 2100 movs r1, #0 800cac0: 4618 mov r0, r3 800cac2: f002 f9cb bl 800ee5c 800cac6: 4603 mov r3, r0 800cac8: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800cacc: e006 b.n 800cadc /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ /* SPI1/2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cace: 2301 movs r3, #1 800cad0: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cad4: e002 b.n 800cadc break; 800cad6: bf00 nop 800cad8: e000 b.n 800cadc break; 800cada: bf00 nop } if (ret == HAL_OK) 800cadc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cae0: 2b00 cmp r3, #0 800cae2: d10a bne.n 800cafa { /* Set the source of SPI1/2/3 clock*/ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 800cae4: 4b37 ldr r3, [pc, #220] @ (800cbc4 ) 800cae6: 6d1b ldr r3, [r3, #80] @ 0x50 800cae8: f423 41e0 bic.w r1, r3, #28672 @ 0x7000 800caec: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800caf0: 6e1b ldr r3, [r3, #96] @ 0x60 800caf2: 4a34 ldr r2, [pc, #208] @ (800cbc4 ) 800caf4: 430b orrs r3, r1 800caf6: 6513 str r3, [r2, #80] @ 0x50 800caf8: e003 b.n 800cb02 } else { /* set overall return value */ status = ret; 800cafa: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cafe: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI4/5 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 800cb02: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb06: e9d3 2300 ldrd r2, r3, [r3] 800cb0a: f402 5300 and.w r3, r2, #8192 @ 0x2000 800cb0e: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 800cb12: 2300 movs r3, #0 800cb14: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 800cb18: e9d7 1238 ldrd r1, r2, [r7, #224] @ 0xe0 800cb1c: 460b mov r3, r1 800cb1e: 4313 orrs r3, r2 800cb20: d056 beq.n 800cbd0 { switch (PeriphClkInit->Spi45ClockSelection) 800cb22: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb26: 6e5b ldr r3, [r3, #100] @ 0x64 800cb28: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800cb2c: d033 beq.n 800cb96 800cb2e: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800cb32: d82c bhi.n 800cb8e 800cb34: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800cb38: d02f beq.n 800cb9a 800cb3a: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800cb3e: d826 bhi.n 800cb8e 800cb40: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800cb44: d02b beq.n 800cb9e 800cb46: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800cb4a: d820 bhi.n 800cb8e 800cb4c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800cb50: d012 beq.n 800cb78 800cb52: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800cb56: d81a bhi.n 800cb8e 800cb58: 2b00 cmp r3, #0 800cb5a: d022 beq.n 800cba2 800cb5c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800cb60: d115 bne.n 800cb8e /* SPI4/5 clock source configuration done later after clock selection check */ break; case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800cb62: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb66: 3308 adds r3, #8 800cb68: 2101 movs r1, #1 800cb6a: 4618 mov r0, r3 800cb6c: f002 f8c4 bl 800ecf8 800cb70: 4603 mov r3, r0 800cb72: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 800cb76: e015 b.n 800cba4 case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800cb78: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb7c: 3328 adds r3, #40 @ 0x28 800cb7e: 2101 movs r1, #1 800cb80: 4618 mov r0, r3 800cb82: f002 f96b bl 800ee5c 800cb86: 4603 mov r3, r0 800cb88: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 800cb8c: e00a b.n 800cba4 /* HSE, oscillator is used as source of SPI4/5 clock */ /* SPI4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cb8e: 2301 movs r3, #1 800cb90: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cb94: e006 b.n 800cba4 break; 800cb96: bf00 nop 800cb98: e004 b.n 800cba4 break; 800cb9a: bf00 nop 800cb9c: e002 b.n 800cba4 break; 800cb9e: bf00 nop 800cba0: e000 b.n 800cba4 break; 800cba2: bf00 nop } if (ret == HAL_OK) 800cba4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cba8: 2b00 cmp r3, #0 800cbaa: d10d bne.n 800cbc8 { /* Set the source of SPI4/5 clock*/ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 800cbac: 4b05 ldr r3, [pc, #20] @ (800cbc4 ) 800cbae: 6d1b ldr r3, [r3, #80] @ 0x50 800cbb0: f423 21e0 bic.w r1, r3, #458752 @ 0x70000 800cbb4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cbb8: 6e5b ldr r3, [r3, #100] @ 0x64 800cbba: 4a02 ldr r2, [pc, #8] @ (800cbc4 ) 800cbbc: 430b orrs r3, r1 800cbbe: 6513 str r3, [r2, #80] @ 0x50 800cbc0: e006 b.n 800cbd0 800cbc2: bf00 nop 800cbc4: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800cbc8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cbcc: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI6 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 800cbd0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cbd4: e9d3 2300 ldrd r2, r3, [r3] 800cbd8: f402 4380 and.w r3, r2, #16384 @ 0x4000 800cbdc: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 800cbe0: 2300 movs r3, #0 800cbe2: f8c7 30dc str.w r3, [r7, #220] @ 0xdc 800cbe6: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 800cbea: 460b mov r3, r1 800cbec: 4313 orrs r3, r2 800cbee: d055 beq.n 800cc9c { switch (PeriphClkInit->Spi6ClockSelection) 800cbf0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cbf4: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 800cbf8: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800cbfc: d033 beq.n 800cc66 800cbfe: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800cc02: d82c bhi.n 800cc5e 800cc04: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800cc08: d02f beq.n 800cc6a 800cc0a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800cc0e: d826 bhi.n 800cc5e 800cc10: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800cc14: d02b beq.n 800cc6e 800cc16: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800cc1a: d820 bhi.n 800cc5e 800cc1c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cc20: d012 beq.n 800cc48 800cc22: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cc26: d81a bhi.n 800cc5e 800cc28: 2b00 cmp r3, #0 800cc2a: d022 beq.n 800cc72 800cc2c: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800cc30: d115 bne.n 800cc5e /* SPI6 clock source configuration done later after clock selection check */ break; case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800cc32: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc36: 3308 adds r3, #8 800cc38: 2101 movs r1, #1 800cc3a: 4618 mov r0, r3 800cc3c: f002 f85c bl 800ecf8 800cc40: 4603 mov r3, r0 800cc42: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 800cc46: e015 b.n 800cc74 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800cc48: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc4c: 3328 adds r3, #40 @ 0x28 800cc4e: 2101 movs r1, #1 800cc50: 4618 mov r0, r3 800cc52: f002 f903 bl 800ee5c 800cc56: 4603 mov r3, r0 800cc58: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 800cc5c: e00a b.n 800cc74 /* SPI6 clock source configuration done later after clock selection check */ break; #endif default: ret = HAL_ERROR; 800cc5e: 2301 movs r3, #1 800cc60: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cc64: e006 b.n 800cc74 break; 800cc66: bf00 nop 800cc68: e004 b.n 800cc74 break; 800cc6a: bf00 nop 800cc6c: e002 b.n 800cc74 break; 800cc6e: bf00 nop 800cc70: e000 b.n 800cc74 break; 800cc72: bf00 nop } if (ret == HAL_OK) 800cc74: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cc78: 2b00 cmp r3, #0 800cc7a: d10b bne.n 800cc94 { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 800cc7c: 4ba3 ldr r3, [pc, #652] @ (800cf0c ) 800cc7e: 6d9b ldr r3, [r3, #88] @ 0x58 800cc80: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 800cc84: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc88: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 800cc8c: 4a9f ldr r2, [pc, #636] @ (800cf0c ) 800cc8e: 430b orrs r3, r1 800cc90: 6593 str r3, [r2, #88] @ 0x58 800cc92: e003 b.n 800cc9c } else { /* set overall return value */ status = ret; 800cc94: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cc98: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*DSI*/ #if defined(FDCAN1) || defined(FDCAN2) /*---------------------------- FDCAN configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 800cc9c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cca0: e9d3 2300 ldrd r2, r3, [r3] 800cca4: f402 4300 and.w r3, r2, #32768 @ 0x8000 800cca8: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 800ccac: 2300 movs r3, #0 800ccae: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 800ccb2: e9d7 1234 ldrd r1, r2, [r7, #208] @ 0xd0 800ccb6: 460b mov r3, r1 800ccb8: 4313 orrs r3, r2 800ccba: d037 beq.n 800cd2c { switch (PeriphClkInit->FdcanClockSelection) 800ccbc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ccc0: 6f1b ldr r3, [r3, #112] @ 0x70 800ccc2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800ccc6: d00e beq.n 800cce6 800ccc8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cccc: d816 bhi.n 800ccfc 800ccce: 2b00 cmp r3, #0 800ccd0: d018 beq.n 800cd04 800ccd2: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800ccd6: d111 bne.n 800ccfc { case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ /* Enable FDCAN Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800ccd8: 4b8c ldr r3, [pc, #560] @ (800cf0c ) 800ccda: 6adb ldr r3, [r3, #44] @ 0x2c 800ccdc: 4a8b ldr r2, [pc, #556] @ (800cf0c ) 800ccde: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cce2: 62d3 str r3, [r2, #44] @ 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 800cce4: e00f b.n 800cd06 case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800cce6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ccea: 3308 adds r3, #8 800ccec: 2101 movs r1, #1 800ccee: 4618 mov r0, r3 800ccf0: f002 f802 bl 800ecf8 800ccf4: 4603 mov r3, r0 800ccf6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FDCAN clock source configuration done later after clock selection check */ break; 800ccfa: e004 b.n 800cd06 /* HSE is used as clock source for FDCAN*/ /* FDCAN clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800ccfc: 2301 movs r3, #1 800ccfe: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cd02: e000 b.n 800cd06 break; 800cd04: bf00 nop } if (ret == HAL_OK) 800cd06: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cd0a: 2b00 cmp r3, #0 800cd0c: d10a bne.n 800cd24 { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 800cd0e: 4b7f ldr r3, [pc, #508] @ (800cf0c ) 800cd10: 6d1b ldr r3, [r3, #80] @ 0x50 800cd12: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 800cd16: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd1a: 6f1b ldr r3, [r3, #112] @ 0x70 800cd1c: 4a7b ldr r2, [pc, #492] @ (800cf0c ) 800cd1e: 430b orrs r3, r1 800cd20: 6513 str r3, [r2, #80] @ 0x50 800cd22: e003 b.n 800cd2c } else { /* set overall return value */ status = ret; 800cd24: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cd28: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*FDCAN1 || FDCAN2*/ /*---------------------------- FMC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 800cd2c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd30: e9d3 2300 ldrd r2, r3, [r3] 800cd34: f002 7380 and.w r3, r2, #16777216 @ 0x1000000 800cd38: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 800cd3c: 2300 movs r3, #0 800cd3e: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 800cd42: e9d7 1232 ldrd r1, r2, [r7, #200] @ 0xc8 800cd46: 460b mov r3, r1 800cd48: 4313 orrs r3, r2 800cd4a: d039 beq.n 800cdc0 { switch (PeriphClkInit->FmcClockSelection) 800cd4c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd50: 6c9b ldr r3, [r3, #72] @ 0x48 800cd52: 2b03 cmp r3, #3 800cd54: d81c bhi.n 800cd90 800cd56: a201 add r2, pc, #4 @ (adr r2, 800cd5c ) 800cd58: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800cd5c: 0800cd99 .word 0x0800cd99 800cd60: 0800cd6d .word 0x0800cd6d 800cd64: 0800cd7b .word 0x0800cd7b 800cd68: 0800cd99 .word 0x0800cd99 { case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ /* Enable FMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cd6c: 4b67 ldr r3, [pc, #412] @ (800cf0c ) 800cd6e: 6adb ldr r3, [r3, #44] @ 0x2c 800cd70: 4a66 ldr r2, [pc, #408] @ (800cf0c ) 800cd72: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cd76: 62d3 str r3, [r2, #44] @ 0x2c /* FMC clock source configuration done later after clock selection check */ break; 800cd78: e00f b.n 800cd9a case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800cd7a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd7e: 3308 adds r3, #8 800cd80: 2102 movs r1, #2 800cd82: 4618 mov r0, r3 800cd84: f001 ffb8 bl 800ecf8 800cd88: 4603 mov r3, r0 800cd8a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FMC clock source configuration done later after clock selection check */ break; 800cd8e: e004 b.n 800cd9a case RCC_FMCCLKSOURCE_HCLK: /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ break; default: ret = HAL_ERROR; 800cd90: 2301 movs r3, #1 800cd92: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cd96: e000 b.n 800cd9a break; 800cd98: bf00 nop } if (ret == HAL_OK) 800cd9a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cd9e: 2b00 cmp r3, #0 800cda0: d10a bne.n 800cdb8 { /* Set the source of FMC clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 800cda2: 4b5a ldr r3, [pc, #360] @ (800cf0c ) 800cda4: 6cdb ldr r3, [r3, #76] @ 0x4c 800cda6: f023 0103 bic.w r1, r3, #3 800cdaa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cdae: 6c9b ldr r3, [r3, #72] @ 0x48 800cdb0: 4a56 ldr r2, [pc, #344] @ (800cf0c ) 800cdb2: 430b orrs r3, r1 800cdb4: 64d3 str r3, [r2, #76] @ 0x4c 800cdb6: e003 b.n 800cdc0 } else { /* set overall return value */ status = ret; 800cdb8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cdbc: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- RTC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 800cdc0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cdc4: e9d3 2300 ldrd r2, r3, [r3] 800cdc8: f402 0380 and.w r3, r2, #4194304 @ 0x400000 800cdcc: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 800cdd0: 2300 movs r3, #0 800cdd2: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 800cdd6: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 800cdda: 460b mov r3, r1 800cddc: 4313 orrs r3, r2 800cdde: f000 809f beq.w 800cf20 { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 800cde2: 4b4b ldr r3, [pc, #300] @ (800cf10 ) 800cde4: 681b ldr r3, [r3, #0] 800cde6: 4a4a ldr r2, [pc, #296] @ (800cf10 ) 800cde8: f443 7380 orr.w r3, r3, #256 @ 0x100 800cdec: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800cdee: f7f8 fd55 bl 800589c 800cdf2: f8c7 0118 str.w r0, [r7, #280] @ 0x118 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800cdf6: e00b b.n 800ce10 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800cdf8: f7f8 fd50 bl 800589c 800cdfc: 4602 mov r2, r0 800cdfe: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 800ce02: 1ad3 subs r3, r2, r3 800ce04: 2b64 cmp r3, #100 @ 0x64 800ce06: d903 bls.n 800ce10 { ret = HAL_TIMEOUT; 800ce08: 2303 movs r3, #3 800ce0a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ce0e: e005 b.n 800ce1c while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800ce10: 4b3f ldr r3, [pc, #252] @ (800cf10 ) 800ce12: 681b ldr r3, [r3, #0] 800ce14: f403 7380 and.w r3, r3, #256 @ 0x100 800ce18: 2b00 cmp r3, #0 800ce1a: d0ed beq.n 800cdf8 } } if (ret == HAL_OK) 800ce1c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ce20: 2b00 cmp r3, #0 800ce22: d179 bne.n 800cf18 { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 800ce24: 4b39 ldr r3, [pc, #228] @ (800cf0c ) 800ce26: 6f1a ldr r2, [r3, #112] @ 0x70 800ce28: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce2c: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800ce30: 4053 eors r3, r2 800ce32: f403 7340 and.w r3, r3, #768 @ 0x300 800ce36: 2b00 cmp r3, #0 800ce38: d015 beq.n 800ce66 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800ce3a: 4b34 ldr r3, [pc, #208] @ (800cf0c ) 800ce3c: 6f1b ldr r3, [r3, #112] @ 0x70 800ce3e: f423 7340 bic.w r3, r3, #768 @ 0x300 800ce42: f8c7 3114 str.w r3, [r7, #276] @ 0x114 /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 800ce46: 4b31 ldr r3, [pc, #196] @ (800cf0c ) 800ce48: 6f1b ldr r3, [r3, #112] @ 0x70 800ce4a: 4a30 ldr r2, [pc, #192] @ (800cf0c ) 800ce4c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800ce50: 6713 str r3, [r2, #112] @ 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 800ce52: 4b2e ldr r3, [pc, #184] @ (800cf0c ) 800ce54: 6f1b ldr r3, [r3, #112] @ 0x70 800ce56: 4a2d ldr r2, [pc, #180] @ (800cf0c ) 800ce58: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ce5c: 6713 str r3, [r2, #112] @ 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg; 800ce5e: 4a2b ldr r2, [pc, #172] @ (800cf0c ) 800ce60: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800ce64: 6713 str r3, [r2, #112] @ 0x70 } /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 800ce66: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce6a: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800ce6e: f5b3 7f80 cmp.w r3, #256 @ 0x100 800ce72: d118 bne.n 800cea6 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ce74: f7f8 fd12 bl 800589c 800ce78: f8c7 0118 str.w r0, [r7, #280] @ 0x118 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800ce7c: e00d b.n 800ce9a { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800ce7e: f7f8 fd0d bl 800589c 800ce82: 4602 mov r2, r0 800ce84: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 800ce88: 1ad2 subs r2, r2, r3 800ce8a: f241 3388 movw r3, #5000 @ 0x1388 800ce8e: 429a cmp r2, r3 800ce90: d903 bls.n 800ce9a { ret = HAL_TIMEOUT; 800ce92: 2303 movs r3, #3 800ce94: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ce98: e005 b.n 800cea6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800ce9a: 4b1c ldr r3, [pc, #112] @ (800cf0c ) 800ce9c: 6f1b ldr r3, [r3, #112] @ 0x70 800ce9e: f003 0302 and.w r3, r3, #2 800cea2: 2b00 cmp r3, #0 800cea4: d0eb beq.n 800ce7e } } } if (ret == HAL_OK) 800cea6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ceaa: 2b00 cmp r3, #0 800ceac: d129 bne.n 800cf02 { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 800ceae: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ceb2: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800ceb6: f403 7340 and.w r3, r3, #768 @ 0x300 800ceba: f5b3 7f40 cmp.w r3, #768 @ 0x300 800cebe: d10e bne.n 800cede 800cec0: 4b12 ldr r3, [pc, #72] @ (800cf0c ) 800cec2: 691b ldr r3, [r3, #16] 800cec4: f423 517c bic.w r1, r3, #16128 @ 0x3f00 800cec8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cecc: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800ced0: 091a lsrs r2, r3, #4 800ced2: 4b10 ldr r3, [pc, #64] @ (800cf14 ) 800ced4: 4013 ands r3, r2 800ced6: 4a0d ldr r2, [pc, #52] @ (800cf0c ) 800ced8: 430b orrs r3, r1 800ceda: 6113 str r3, [r2, #16] 800cedc: e005 b.n 800ceea 800cede: 4b0b ldr r3, [pc, #44] @ (800cf0c ) 800cee0: 691b ldr r3, [r3, #16] 800cee2: 4a0a ldr r2, [pc, #40] @ (800cf0c ) 800cee4: f423 537c bic.w r3, r3, #16128 @ 0x3f00 800cee8: 6113 str r3, [r2, #16] 800ceea: 4b08 ldr r3, [pc, #32] @ (800cf0c ) 800ceec: 6f19 ldr r1, [r3, #112] @ 0x70 800ceee: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cef2: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800cef6: f3c3 030b ubfx r3, r3, #0, #12 800cefa: 4a04 ldr r2, [pc, #16] @ (800cf0c ) 800cefc: 430b orrs r3, r1 800cefe: 6713 str r3, [r2, #112] @ 0x70 800cf00: e00e b.n 800cf20 } else { /* set overall return value */ status = ret; 800cf02: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cf06: f887 311e strb.w r3, [r7, #286] @ 0x11e 800cf0a: e009 b.n 800cf20 800cf0c: 58024400 .word 0x58024400 800cf10: 58024800 .word 0x58024800 800cf14: 00ffffcf .word 0x00ffffcf } } else { /* set overall return value */ status = ret; 800cf18: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cf1c: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART1/6 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 800cf20: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf24: e9d3 2300 ldrd r2, r3, [r3] 800cf28: f002 0301 and.w r3, r2, #1 800cf2c: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 800cf30: 2300 movs r3, #0 800cf32: f8c7 30bc str.w r3, [r7, #188] @ 0xbc 800cf36: e9d7 122e ldrd r1, r2, [r7, #184] @ 0xb8 800cf3a: 460b mov r3, r1 800cf3c: 4313 orrs r3, r2 800cf3e: f000 8089 beq.w 800d054 { switch (PeriphClkInit->Usart16ClockSelection) 800cf42: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf46: 6fdb ldr r3, [r3, #124] @ 0x7c 800cf48: 2b28 cmp r3, #40 @ 0x28 800cf4a: d86b bhi.n 800d024 800cf4c: a201 add r2, pc, #4 @ (adr r2, 800cf54 ) 800cf4e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800cf52: bf00 nop 800cf54: 0800d02d .word 0x0800d02d 800cf58: 0800d025 .word 0x0800d025 800cf5c: 0800d025 .word 0x0800d025 800cf60: 0800d025 .word 0x0800d025 800cf64: 0800d025 .word 0x0800d025 800cf68: 0800d025 .word 0x0800d025 800cf6c: 0800d025 .word 0x0800d025 800cf70: 0800d025 .word 0x0800d025 800cf74: 0800cff9 .word 0x0800cff9 800cf78: 0800d025 .word 0x0800d025 800cf7c: 0800d025 .word 0x0800d025 800cf80: 0800d025 .word 0x0800d025 800cf84: 0800d025 .word 0x0800d025 800cf88: 0800d025 .word 0x0800d025 800cf8c: 0800d025 .word 0x0800d025 800cf90: 0800d025 .word 0x0800d025 800cf94: 0800d00f .word 0x0800d00f 800cf98: 0800d025 .word 0x0800d025 800cf9c: 0800d025 .word 0x0800d025 800cfa0: 0800d025 .word 0x0800d025 800cfa4: 0800d025 .word 0x0800d025 800cfa8: 0800d025 .word 0x0800d025 800cfac: 0800d025 .word 0x0800d025 800cfb0: 0800d025 .word 0x0800d025 800cfb4: 0800d02d .word 0x0800d02d 800cfb8: 0800d025 .word 0x0800d025 800cfbc: 0800d025 .word 0x0800d025 800cfc0: 0800d025 .word 0x0800d025 800cfc4: 0800d025 .word 0x0800d025 800cfc8: 0800d025 .word 0x0800d025 800cfcc: 0800d025 .word 0x0800d025 800cfd0: 0800d025 .word 0x0800d025 800cfd4: 0800d02d .word 0x0800d02d 800cfd8: 0800d025 .word 0x0800d025 800cfdc: 0800d025 .word 0x0800d025 800cfe0: 0800d025 .word 0x0800d025 800cfe4: 0800d025 .word 0x0800d025 800cfe8: 0800d025 .word 0x0800d025 800cfec: 0800d025 .word 0x0800d025 800cff0: 0800d025 .word 0x0800d025 800cff4: 0800d02d .word 0x0800d02d case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ /* USART1/6 clock source configuration done later after clock selection check */ break; case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800cff8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cffc: 3308 adds r3, #8 800cffe: 2101 movs r1, #1 800d000: 4618 mov r0, r3 800d002: f001 fe79 bl 800ecf8 800d006: 4603 mov r3, r0 800d008: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 800d00c: e00f b.n 800d02e case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d00e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d012: 3328 adds r3, #40 @ 0x28 800d014: 2101 movs r1, #1 800d016: 4618 mov r0, r3 800d018: f001 ff20 bl 800ee5c 800d01c: 4603 mov r3, r0 800d01e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 800d022: e004 b.n 800d02e /* LSE, oscillator is used as source of USART1/6 clock */ /* USART1/6 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d024: 2301 movs r3, #1 800d026: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d02a: e000 b.n 800d02e break; 800d02c: bf00 nop } if (ret == HAL_OK) 800d02e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d032: 2b00 cmp r3, #0 800d034: d10a bne.n 800d04c { /* Set the source of USART1/6 clock */ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 800d036: 4bbf ldr r3, [pc, #764] @ (800d334 ) 800d038: 6d5b ldr r3, [r3, #84] @ 0x54 800d03a: f023 0138 bic.w r1, r3, #56 @ 0x38 800d03e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d042: 6fdb ldr r3, [r3, #124] @ 0x7c 800d044: 4abb ldr r2, [pc, #748] @ (800d334 ) 800d046: 430b orrs r3, r1 800d048: 6553 str r3, [r2, #84] @ 0x54 800d04a: e003 b.n 800d054 } else { /* set overall return value */ status = ret; 800d04c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d050: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 800d054: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d058: e9d3 2300 ldrd r2, r3, [r3] 800d05c: f002 0302 and.w r3, r2, #2 800d060: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 800d064: 2300 movs r3, #0 800d066: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 800d06a: e9d7 122c ldrd r1, r2, [r7, #176] @ 0xb0 800d06e: 460b mov r3, r1 800d070: 4313 orrs r3, r2 800d072: d041 beq.n 800d0f8 { switch (PeriphClkInit->Usart234578ClockSelection) 800d074: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d078: 6f9b ldr r3, [r3, #120] @ 0x78 800d07a: 2b05 cmp r3, #5 800d07c: d824 bhi.n 800d0c8 800d07e: a201 add r2, pc, #4 @ (adr r2, 800d084 ) 800d080: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d084: 0800d0d1 .word 0x0800d0d1 800d088: 0800d09d .word 0x0800d09d 800d08c: 0800d0b3 .word 0x0800d0b3 800d090: 0800d0d1 .word 0x0800d0d1 800d094: 0800d0d1 .word 0x0800d0d1 800d098: 0800d0d1 .word 0x0800d0d1 case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d09c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0a0: 3308 adds r3, #8 800d0a2: 2101 movs r1, #1 800d0a4: 4618 mov r0, r3 800d0a6: f001 fe27 bl 800ecf8 800d0aa: 4603 mov r3, r0 800d0ac: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 800d0b0: e00f b.n 800d0d2 case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d0b2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0b6: 3328 adds r3, #40 @ 0x28 800d0b8: 2101 movs r1, #1 800d0ba: 4618 mov r0, r3 800d0bc: f001 fece bl 800ee5c 800d0c0: 4603 mov r3, r0 800d0c2: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 800d0c6: e004 b.n 800d0d2 /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d0c8: 2301 movs r3, #1 800d0ca: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d0ce: e000 b.n 800d0d2 break; 800d0d0: bf00 nop } if (ret == HAL_OK) 800d0d2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d0d6: 2b00 cmp r3, #0 800d0d8: d10a bne.n 800d0f0 { /* Set the source of USART2/3/4/5/7/8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 800d0da: 4b96 ldr r3, [pc, #600] @ (800d334 ) 800d0dc: 6d5b ldr r3, [r3, #84] @ 0x54 800d0de: f023 0107 bic.w r1, r3, #7 800d0e2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0e6: 6f9b ldr r3, [r3, #120] @ 0x78 800d0e8: 4a92 ldr r2, [pc, #584] @ (800d334 ) 800d0ea: 430b orrs r3, r1 800d0ec: 6553 str r3, [r2, #84] @ 0x54 800d0ee: e003 b.n 800d0f8 } else { /* set overall return value */ status = ret; 800d0f0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d0f4: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- LPUART1 Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 800d0f8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0fc: e9d3 2300 ldrd r2, r3, [r3] 800d100: f002 0304 and.w r3, r2, #4 800d104: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 800d108: 2300 movs r3, #0 800d10a: f8c7 30ac str.w r3, [r7, #172] @ 0xac 800d10e: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 800d112: 460b mov r3, r1 800d114: 4313 orrs r3, r2 800d116: d044 beq.n 800d1a2 { switch (PeriphClkInit->Lpuart1ClockSelection) 800d118: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d11c: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800d120: 2b05 cmp r3, #5 800d122: d825 bhi.n 800d170 800d124: a201 add r2, pc, #4 @ (adr r2, 800d12c ) 800d126: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d12a: bf00 nop 800d12c: 0800d179 .word 0x0800d179 800d130: 0800d145 .word 0x0800d145 800d134: 0800d15b .word 0x0800d15b 800d138: 0800d179 .word 0x0800d179 800d13c: 0800d179 .word 0x0800d179 800d140: 0800d179 .word 0x0800d179 case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d144: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d148: 3308 adds r3, #8 800d14a: 2101 movs r1, #1 800d14c: 4618 mov r0, r3 800d14e: f001 fdd3 bl 800ecf8 800d152: 4603 mov r3, r0 800d154: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 800d158: e00f b.n 800d17a case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d15a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d15e: 3328 adds r3, #40 @ 0x28 800d160: 2101 movs r1, #1 800d162: 4618 mov r0, r3 800d164: f001 fe7a bl 800ee5c 800d168: 4603 mov r3, r0 800d16a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 800d16e: e004 b.n 800d17a /* LSE, oscillator is used as source of LPUART1 clock */ /* LPUART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d170: 2301 movs r3, #1 800d172: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d176: e000 b.n 800d17a break; 800d178: bf00 nop } if (ret == HAL_OK) 800d17a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d17e: 2b00 cmp r3, #0 800d180: d10b bne.n 800d19a { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 800d182: 4b6c ldr r3, [pc, #432] @ (800d334 ) 800d184: 6d9b ldr r3, [r3, #88] @ 0x58 800d186: f023 0107 bic.w r1, r3, #7 800d18a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d18e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800d192: 4a68 ldr r2, [pc, #416] @ (800d334 ) 800d194: 430b orrs r3, r1 800d196: 6593 str r3, [r2, #88] @ 0x58 800d198: e003 b.n 800d1a2 } else { /* set overall return value */ status = ret; 800d19a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d19e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 800d1a2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d1a6: e9d3 2300 ldrd r2, r3, [r3] 800d1aa: f002 0320 and.w r3, r2, #32 800d1ae: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 800d1b2: 2300 movs r3, #0 800d1b4: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 800d1b8: e9d7 1228 ldrd r1, r2, [r7, #160] @ 0xa0 800d1bc: 460b mov r3, r1 800d1be: 4313 orrs r3, r2 800d1c0: d055 beq.n 800d26e { switch (PeriphClkInit->Lptim1ClockSelection) 800d1c2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d1c6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800d1ca: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800d1ce: d033 beq.n 800d238 800d1d0: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800d1d4: d82c bhi.n 800d230 800d1d6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800d1da: d02f beq.n 800d23c 800d1dc: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800d1e0: d826 bhi.n 800d230 800d1e2: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800d1e6: d02b beq.n 800d240 800d1e8: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800d1ec: d820 bhi.n 800d230 800d1ee: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d1f2: d012 beq.n 800d21a 800d1f4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d1f8: d81a bhi.n 800d230 800d1fa: 2b00 cmp r3, #0 800d1fc: d022 beq.n 800d244 800d1fe: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800d202: d115 bne.n 800d230 /* LPTIM1 clock source configuration done later after clock selection check */ break; case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d204: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d208: 3308 adds r3, #8 800d20a: 2100 movs r1, #0 800d20c: 4618 mov r0, r3 800d20e: f001 fd73 bl 800ecf8 800d212: 4603 mov r3, r0 800d214: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 800d218: e015 b.n 800d246 case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d21a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d21e: 3328 adds r3, #40 @ 0x28 800d220: 2102 movs r1, #2 800d222: 4618 mov r0, r3 800d224: f001 fe1a bl 800ee5c 800d228: 4603 mov r3, r0 800d22a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 800d22e: e00a b.n 800d246 /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ /* LPTIM1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d230: 2301 movs r3, #1 800d232: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d236: e006 b.n 800d246 break; 800d238: bf00 nop 800d23a: e004 b.n 800d246 break; 800d23c: bf00 nop 800d23e: e002 b.n 800d246 break; 800d240: bf00 nop 800d242: e000 b.n 800d246 break; 800d244: bf00 nop } if (ret == HAL_OK) 800d246: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d24a: 2b00 cmp r3, #0 800d24c: d10b bne.n 800d266 { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 800d24e: 4b39 ldr r3, [pc, #228] @ (800d334 ) 800d250: 6d5b ldr r3, [r3, #84] @ 0x54 800d252: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 800d256: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d25a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800d25e: 4a35 ldr r2, [pc, #212] @ (800d334 ) 800d260: 430b orrs r3, r1 800d262: 6553 str r3, [r2, #84] @ 0x54 800d264: e003 b.n 800d26e } else { /* set overall return value */ status = ret; 800d266: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d26a: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 800d26e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d272: e9d3 2300 ldrd r2, r3, [r3] 800d276: f002 0340 and.w r3, r2, #64 @ 0x40 800d27a: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800d27e: 2300 movs r3, #0 800d280: f8c7 309c str.w r3, [r7, #156] @ 0x9c 800d284: e9d7 1226 ldrd r1, r2, [r7, #152] @ 0x98 800d288: 460b mov r3, r1 800d28a: 4313 orrs r3, r2 800d28c: d058 beq.n 800d340 { switch (PeriphClkInit->Lptim2ClockSelection) 800d28e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d292: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800d296: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800d29a: d033 beq.n 800d304 800d29c: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800d2a0: d82c bhi.n 800d2fc 800d2a2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d2a6: d02f beq.n 800d308 800d2a8: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d2ac: d826 bhi.n 800d2fc 800d2ae: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 800d2b2: d02b beq.n 800d30c 800d2b4: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 800d2b8: d820 bhi.n 800d2fc 800d2ba: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800d2be: d012 beq.n 800d2e6 800d2c0: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800d2c4: d81a bhi.n 800d2fc 800d2c6: 2b00 cmp r3, #0 800d2c8: d022 beq.n 800d310 800d2ca: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800d2ce: d115 bne.n 800d2fc /* LPTIM2 clock source configuration done later after clock selection check */ break; case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d2d0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d2d4: 3308 adds r3, #8 800d2d6: 2100 movs r1, #0 800d2d8: 4618 mov r0, r3 800d2da: f001 fd0d bl 800ecf8 800d2de: 4603 mov r3, r0 800d2e0: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 800d2e4: e015 b.n 800d312 case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d2e6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d2ea: 3328 adds r3, #40 @ 0x28 800d2ec: 2102 movs r1, #2 800d2ee: 4618 mov r0, r3 800d2f0: f001 fdb4 bl 800ee5c 800d2f4: 4603 mov r3, r0 800d2f6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 800d2fa: e00a b.n 800d312 /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ /* LPTIM2 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d2fc: 2301 movs r3, #1 800d2fe: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d302: e006 b.n 800d312 break; 800d304: bf00 nop 800d306: e004 b.n 800d312 break; 800d308: bf00 nop 800d30a: e002 b.n 800d312 break; 800d30c: bf00 nop 800d30e: e000 b.n 800d312 break; 800d310: bf00 nop } if (ret == HAL_OK) 800d312: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d316: 2b00 cmp r3, #0 800d318: d10e bne.n 800d338 { /* Set the source of LPTIM2 clock*/ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 800d31a: 4b06 ldr r3, [pc, #24] @ (800d334 ) 800d31c: 6d9b ldr r3, [r3, #88] @ 0x58 800d31e: f423 51e0 bic.w r1, r3, #7168 @ 0x1c00 800d322: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d326: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800d32a: 4a02 ldr r2, [pc, #8] @ (800d334 ) 800d32c: 430b orrs r3, r1 800d32e: 6593 str r3, [r2, #88] @ 0x58 800d330: e006 b.n 800d340 800d332: bf00 nop 800d334: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800d338: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d33c: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM345 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 800d340: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d344: e9d3 2300 ldrd r2, r3, [r3] 800d348: f002 0380 and.w r3, r2, #128 @ 0x80 800d34c: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800d350: 2300 movs r3, #0 800d352: f8c7 3094 str.w r3, [r7, #148] @ 0x94 800d356: e9d7 1224 ldrd r1, r2, [r7, #144] @ 0x90 800d35a: 460b mov r3, r1 800d35c: 4313 orrs r3, r2 800d35e: d055 beq.n 800d40c { switch (PeriphClkInit->Lptim345ClockSelection) 800d360: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d364: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800d368: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 800d36c: d033 beq.n 800d3d6 800d36e: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 800d372: d82c bhi.n 800d3ce 800d374: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800d378: d02f beq.n 800d3da 800d37a: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800d37e: d826 bhi.n 800d3ce 800d380: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800d384: d02b beq.n 800d3de 800d386: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800d38a: d820 bhi.n 800d3ce 800d38c: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800d390: d012 beq.n 800d3b8 800d392: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800d396: d81a bhi.n 800d3ce 800d398: 2b00 cmp r3, #0 800d39a: d022 beq.n 800d3e2 800d39c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800d3a0: d115 bne.n 800d3ce case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d3a2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d3a6: 3308 adds r3, #8 800d3a8: 2100 movs r1, #0 800d3aa: 4618 mov r0, r3 800d3ac: f001 fca4 bl 800ecf8 800d3b0: 4603 mov r3, r0 800d3b2: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800d3b6: e015 b.n 800d3e4 case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d3b8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d3bc: 3328 adds r3, #40 @ 0x28 800d3be: 2102 movs r1, #2 800d3c0: 4618 mov r0, r3 800d3c2: f001 fd4b bl 800ee5c 800d3c6: 4603 mov r3, r0 800d3c8: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800d3cc: e00a b.n 800d3e4 /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d3ce: 2301 movs r3, #1 800d3d0: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d3d4: e006 b.n 800d3e4 break; 800d3d6: bf00 nop 800d3d8: e004 b.n 800d3e4 break; 800d3da: bf00 nop 800d3dc: e002 b.n 800d3e4 break; 800d3de: bf00 nop 800d3e0: e000 b.n 800d3e4 break; 800d3e2: bf00 nop } if (ret == HAL_OK) 800d3e4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d3e8: 2b00 cmp r3, #0 800d3ea: d10b bne.n 800d404 { /* Set the source of LPTIM3/4/5 clock */ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 800d3ec: 4bbb ldr r3, [pc, #748] @ (800d6dc ) 800d3ee: 6d9b ldr r3, [r3, #88] @ 0x58 800d3f0: f423 4160 bic.w r1, r3, #57344 @ 0xe000 800d3f4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d3f8: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800d3fc: 4ab7 ldr r2, [pc, #732] @ (800d6dc ) 800d3fe: 430b orrs r3, r1 800d400: 6593 str r3, [r2, #88] @ 0x58 800d402: e003 b.n 800d40c } else { /* set overall return value */ status = ret; 800d404: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d408: f887 311e strb.w r3, [r7, #286] @ 0x11e __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); } #else if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 800d40c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d410: e9d3 2300 ldrd r2, r3, [r3] 800d414: f002 0308 and.w r3, r2, #8 800d418: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800d41c: 2300 movs r3, #0 800d41e: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800d422: e9d7 1222 ldrd r1, r2, [r7, #136] @ 0x88 800d426: 460b mov r3, r1 800d428: 4313 orrs r3, r2 800d42a: d01e beq.n 800d46a { /* Check the parameters */ assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3) 800d42c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d430: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800d434: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d438: d10c bne.n 800d454 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800d43a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d43e: 3328 adds r3, #40 @ 0x28 800d440: 2102 movs r1, #2 800d442: 4618 mov r0, r3 800d444: f001 fd0a bl 800ee5c 800d448: 4603 mov r3, r0 800d44a: 2b00 cmp r3, #0 800d44c: d002 beq.n 800d454 { status = HAL_ERROR; 800d44e: 2301 movs r3, #1 800d450: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 800d454: 4ba1 ldr r3, [pc, #644] @ (800d6dc ) 800d456: 6d5b ldr r3, [r3, #84] @ 0x54 800d458: f423 5140 bic.w r1, r3, #12288 @ 0x3000 800d45c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d460: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800d464: 4a9d ldr r2, [pc, #628] @ (800d6dc ) 800d466: 430b orrs r3, r1 800d468: 6553 str r3, [r2, #84] @ 0x54 } #endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 800d46a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d46e: e9d3 2300 ldrd r2, r3, [r3] 800d472: f002 0310 and.w r3, r2, #16 800d476: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800d47a: 2300 movs r3, #0 800d47c: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800d480: e9d7 1220 ldrd r1, r2, [r7, #128] @ 0x80 800d484: 460b mov r3, r1 800d486: 4313 orrs r3, r2 800d488: d01e beq.n 800d4c8 { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) 800d48a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d48e: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800d492: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d496: d10c bne.n 800d4b2 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800d498: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d49c: 3328 adds r3, #40 @ 0x28 800d49e: 2102 movs r1, #2 800d4a0: 4618 mov r0, r3 800d4a2: f001 fcdb bl 800ee5c 800d4a6: 4603 mov r3, r0 800d4a8: 2b00 cmp r3, #0 800d4aa: d002 beq.n 800d4b2 { status = HAL_ERROR; 800d4ac: 2301 movs r3, #1 800d4ae: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 800d4b2: 4b8a ldr r3, [pc, #552] @ (800d6dc ) 800d4b4: 6d9b ldr r3, [r3, #88] @ 0x58 800d4b6: f423 7140 bic.w r1, r3, #768 @ 0x300 800d4ba: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d4be: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800d4c2: 4a86 ldr r2, [pc, #536] @ (800d6dc ) 800d4c4: 430b orrs r3, r1 800d4c6: 6593 str r3, [r2, #88] @ 0x58 } /*---------------------------- ADC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 800d4c8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d4cc: e9d3 2300 ldrd r2, r3, [r3] 800d4d0: f402 2300 and.w r3, r2, #524288 @ 0x80000 800d4d4: 67bb str r3, [r7, #120] @ 0x78 800d4d6: 2300 movs r3, #0 800d4d8: 67fb str r3, [r7, #124] @ 0x7c 800d4da: e9d7 121e ldrd r1, r2, [r7, #120] @ 0x78 800d4de: 460b mov r3, r1 800d4e0: 4313 orrs r3, r2 800d4e2: d03e beq.n 800d562 { switch (PeriphClkInit->AdcClockSelection) 800d4e4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d4e8: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 800d4ec: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d4f0: d022 beq.n 800d538 800d4f2: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d4f6: d81b bhi.n 800d530 800d4f8: 2b00 cmp r3, #0 800d4fa: d003 beq.n 800d504 800d4fc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800d500: d00b beq.n 800d51a 800d502: e015 b.n 800d530 { case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d504: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d508: 3308 adds r3, #8 800d50a: 2100 movs r1, #0 800d50c: 4618 mov r0, r3 800d50e: f001 fbf3 bl 800ecf8 800d512: 4603 mov r3, r0 800d514: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 800d518: e00f b.n 800d53a case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d51a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d51e: 3328 adds r3, #40 @ 0x28 800d520: 2102 movs r1, #2 800d522: 4618 mov r0, r3 800d524: f001 fc9a bl 800ee5c 800d528: 4603 mov r3, r0 800d52a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 800d52e: e004 b.n 800d53a /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ /* ADC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d530: 2301 movs r3, #1 800d532: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d536: e000 b.n 800d53a break; 800d538: bf00 nop } if (ret == HAL_OK) 800d53a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d53e: 2b00 cmp r3, #0 800d540: d10b bne.n 800d55a { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 800d542: 4b66 ldr r3, [pc, #408] @ (800d6dc ) 800d544: 6d9b ldr r3, [r3, #88] @ 0x58 800d546: f423 3140 bic.w r1, r3, #196608 @ 0x30000 800d54a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d54e: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 800d552: 4a62 ldr r2, [pc, #392] @ (800d6dc ) 800d554: 430b orrs r3, r1 800d556: 6593 str r3, [r2, #88] @ 0x58 800d558: e003 b.n 800d562 } else { /* set overall return value */ status = ret; 800d55a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d55e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ USB Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 800d562: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d566: e9d3 2300 ldrd r2, r3, [r3] 800d56a: f402 2380 and.w r3, r2, #262144 @ 0x40000 800d56e: 673b str r3, [r7, #112] @ 0x70 800d570: 2300 movs r3, #0 800d572: 677b str r3, [r7, #116] @ 0x74 800d574: e9d7 121c ldrd r1, r2, [r7, #112] @ 0x70 800d578: 460b mov r3, r1 800d57a: 4313 orrs r3, r2 800d57c: d03b beq.n 800d5f6 { switch (PeriphClkInit->UsbClockSelection) 800d57e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d582: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800d586: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800d58a: d01f beq.n 800d5cc 800d58c: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800d590: d818 bhi.n 800d5c4 800d592: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800d596: d003 beq.n 800d5a0 800d598: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800d59c: d007 beq.n 800d5ae 800d59e: e011 b.n 800d5c4 { case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ /* Enable USB Clock output generated form System USB . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d5a0: 4b4e ldr r3, [pc, #312] @ (800d6dc ) 800d5a2: 6adb ldr r3, [r3, #44] @ 0x2c 800d5a4: 4a4d ldr r2, [pc, #308] @ (800d6dc ) 800d5a6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d5aa: 62d3 str r3, [r2, #44] @ 0x2c /* USB clock source configuration done later after clock selection check */ break; 800d5ac: e00f b.n 800d5ce case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d5ae: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d5b2: 3328 adds r3, #40 @ 0x28 800d5b4: 2101 movs r1, #1 800d5b6: 4618 mov r0, r3 800d5b8: f001 fc50 bl 800ee5c 800d5bc: 4603 mov r3, r0 800d5be: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USB clock source configuration done later after clock selection check */ break; 800d5c2: e004 b.n 800d5ce /* HSI48 oscillator is used as source of USB clock */ /* USB clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d5c4: 2301 movs r3, #1 800d5c6: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d5ca: e000 b.n 800d5ce break; 800d5cc: bf00 nop } if (ret == HAL_OK) 800d5ce: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d5d2: 2b00 cmp r3, #0 800d5d4: d10b bne.n 800d5ee { /* Set the source of USB clock*/ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 800d5d6: 4b41 ldr r3, [pc, #260] @ (800d6dc ) 800d5d8: 6d5b ldr r3, [r3, #84] @ 0x54 800d5da: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800d5de: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d5e2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800d5e6: 4a3d ldr r2, [pc, #244] @ (800d6dc ) 800d5e8: 430b orrs r3, r1 800d5ea: 6553 str r3, [r2, #84] @ 0x54 800d5ec: e003 b.n 800d5f6 } else { /* set overall return value */ status = ret; 800d5ee: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d5f2: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------------- SDMMC Configuration ------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 800d5f6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d5fa: e9d3 2300 ldrd r2, r3, [r3] 800d5fe: f402 3380 and.w r3, r2, #65536 @ 0x10000 800d602: 66bb str r3, [r7, #104] @ 0x68 800d604: 2300 movs r3, #0 800d606: 66fb str r3, [r7, #108] @ 0x6c 800d608: e9d7 121a ldrd r1, r2, [r7, #104] @ 0x68 800d60c: 460b mov r3, r1 800d60e: 4313 orrs r3, r2 800d610: d031 beq.n 800d676 { /* Check the parameters */ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); switch (PeriphClkInit->SdmmcClockSelection) 800d612: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d616: 6d1b ldr r3, [r3, #80] @ 0x50 800d618: 2b00 cmp r3, #0 800d61a: d003 beq.n 800d624 800d61c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800d620: d007 beq.n 800d632 800d622: e011 b.n 800d648 { case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ /* Enable SDMMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d624: 4b2d ldr r3, [pc, #180] @ (800d6dc ) 800d626: 6adb ldr r3, [r3, #44] @ 0x2c 800d628: 4a2c ldr r2, [pc, #176] @ (800d6dc ) 800d62a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d62e: 62d3 str r3, [r2, #44] @ 0x2c /* SDMMC clock source configuration done later after clock selection check */ break; 800d630: e00e b.n 800d650 case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800d632: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d636: 3308 adds r3, #8 800d638: 2102 movs r1, #2 800d63a: 4618 mov r0, r3 800d63c: f001 fb5c bl 800ecf8 800d640: 4603 mov r3, r0 800d642: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SDMMC clock source configuration done later after clock selection check */ break; 800d646: e003 b.n 800d650 default: ret = HAL_ERROR; 800d648: 2301 movs r3, #1 800d64a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d64e: bf00 nop } if (ret == HAL_OK) 800d650: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d654: 2b00 cmp r3, #0 800d656: d10a bne.n 800d66e { /* Set the source of SDMMC clock*/ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 800d658: 4b20 ldr r3, [pc, #128] @ (800d6dc ) 800d65a: 6cdb ldr r3, [r3, #76] @ 0x4c 800d65c: f423 3180 bic.w r1, r3, #65536 @ 0x10000 800d660: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d664: 6d1b ldr r3, [r3, #80] @ 0x50 800d666: 4a1d ldr r2, [pc, #116] @ (800d6dc ) 800d668: 430b orrs r3, r1 800d66a: 64d3 str r3, [r2, #76] @ 0x4c 800d66c: e003 b.n 800d676 } else { /* set overall return value */ status = ret; 800d66e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d672: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /* LTDC */ /*------------------------------ RNG Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 800d676: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d67a: e9d3 2300 ldrd r2, r3, [r3] 800d67e: f402 3300 and.w r3, r2, #131072 @ 0x20000 800d682: 663b str r3, [r7, #96] @ 0x60 800d684: 2300 movs r3, #0 800d686: 667b str r3, [r7, #100] @ 0x64 800d688: e9d7 1218 ldrd r1, r2, [r7, #96] @ 0x60 800d68c: 460b mov r3, r1 800d68e: 4313 orrs r3, r2 800d690: d03b beq.n 800d70a { switch (PeriphClkInit->RngClockSelection) 800d692: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d696: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800d69a: f5b3 7f40 cmp.w r3, #768 @ 0x300 800d69e: d018 beq.n 800d6d2 800d6a0: f5b3 7f40 cmp.w r3, #768 @ 0x300 800d6a4: d811 bhi.n 800d6ca 800d6a6: f5b3 7f00 cmp.w r3, #512 @ 0x200 800d6aa: d014 beq.n 800d6d6 800d6ac: f5b3 7f00 cmp.w r3, #512 @ 0x200 800d6b0: d80b bhi.n 800d6ca 800d6b2: 2b00 cmp r3, #0 800d6b4: d014 beq.n 800d6e0 800d6b6: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d6ba: d106 bne.n 800d6ca { case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ /* Enable RNG Clock output generated form System RNG . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d6bc: 4b07 ldr r3, [pc, #28] @ (800d6dc ) 800d6be: 6adb ldr r3, [r3, #44] @ 0x2c 800d6c0: 4a06 ldr r2, [pc, #24] @ (800d6dc ) 800d6c2: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d6c6: 62d3 str r3, [r2, #44] @ 0x2c /* RNG clock source configuration done later after clock selection check */ break; 800d6c8: e00b b.n 800d6e2 /* HSI48 oscillator is used as source of RNG clock */ /* RNG clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d6ca: 2301 movs r3, #1 800d6cc: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d6d0: e007 b.n 800d6e2 break; 800d6d2: bf00 nop 800d6d4: e005 b.n 800d6e2 break; 800d6d6: bf00 nop 800d6d8: e003 b.n 800d6e2 800d6da: bf00 nop 800d6dc: 58024400 .word 0x58024400 break; 800d6e0: bf00 nop } if (ret == HAL_OK) 800d6e2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d6e6: 2b00 cmp r3, #0 800d6e8: d10b bne.n 800d702 { /* Set the source of RNG clock*/ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 800d6ea: 4bba ldr r3, [pc, #744] @ (800d9d4 ) 800d6ec: 6d5b ldr r3, [r3, #84] @ 0x54 800d6ee: f423 7140 bic.w r1, r3, #768 @ 0x300 800d6f2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d6f6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800d6fa: 4ab6 ldr r2, [pc, #728] @ (800d9d4 ) 800d6fc: 430b orrs r3, r1 800d6fe: 6553 str r3, [r2, #84] @ 0x54 800d700: e003 b.n 800d70a } else { /* set overall return value */ status = ret; 800d702: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d706: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ SWPMI1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 800d70a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d70e: e9d3 2300 ldrd r2, r3, [r3] 800d712: f402 1380 and.w r3, r2, #1048576 @ 0x100000 800d716: 65bb str r3, [r7, #88] @ 0x58 800d718: 2300 movs r3, #0 800d71a: 65fb str r3, [r7, #92] @ 0x5c 800d71c: e9d7 1216 ldrd r1, r2, [r7, #88] @ 0x58 800d720: 460b mov r3, r1 800d722: 4313 orrs r3, r2 800d724: d009 beq.n 800d73a { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 800d726: 4bab ldr r3, [pc, #684] @ (800d9d4 ) 800d728: 6d1b ldr r3, [r3, #80] @ 0x50 800d72a: f023 4100 bic.w r1, r3, #2147483648 @ 0x80000000 800d72e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d732: 6f5b ldr r3, [r3, #116] @ 0x74 800d734: 4aa7 ldr r2, [pc, #668] @ (800d9d4 ) 800d736: 430b orrs r3, r1 800d738: 6513 str r3, [r2, #80] @ 0x50 } #if defined(HRTIM1) /*------------------------------ HRTIM1 clock Configuration ----------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) 800d73a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d73e: e9d3 2300 ldrd r2, r3, [r3] 800d742: f002 5380 and.w r3, r2, #268435456 @ 0x10000000 800d746: 653b str r3, [r7, #80] @ 0x50 800d748: 2300 movs r3, #0 800d74a: 657b str r3, [r7, #84] @ 0x54 800d74c: e9d7 1214 ldrd r1, r2, [r7, #80] @ 0x50 800d750: 460b mov r3, r1 800d752: 4313 orrs r3, r2 800d754: d00a beq.n 800d76c { /* Check the parameters */ assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); 800d756: 4b9f ldr r3, [pc, #636] @ (800d9d4 ) 800d758: 691b ldr r3, [r3, #16] 800d75a: f423 4180 bic.w r1, r3, #16384 @ 0x4000 800d75e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d762: f8d3 30b8 ldr.w r3, [r3, #184] @ 0xb8 800d766: 4a9b ldr r2, [pc, #620] @ (800d9d4 ) 800d768: 430b orrs r3, r1 800d76a: 6113 str r3, [r2, #16] } #endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 800d76c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d770: e9d3 2300 ldrd r2, r3, [r3] 800d774: f402 1300 and.w r3, r2, #2097152 @ 0x200000 800d778: 64bb str r3, [r7, #72] @ 0x48 800d77a: 2300 movs r3, #0 800d77c: 64fb str r3, [r7, #76] @ 0x4c 800d77e: e9d7 1212 ldrd r1, r2, [r7, #72] @ 0x48 800d782: 460b mov r3, r1 800d784: 4313 orrs r3, r2 800d786: d009 beq.n 800d79c { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 800d788: 4b92 ldr r3, [pc, #584] @ (800d9d4 ) 800d78a: 6d1b ldr r3, [r3, #80] @ 0x50 800d78c: f023 7180 bic.w r1, r3, #16777216 @ 0x1000000 800d790: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d794: 6edb ldr r3, [r3, #108] @ 0x6c 800d796: 4a8f ldr r2, [pc, #572] @ (800d9d4 ) 800d798: 430b orrs r3, r1 800d79a: 6513 str r3, [r2, #80] @ 0x50 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); } #endif /* DFSDM2 */ /*------------------------------------ TIM configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 800d79c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7a0: e9d3 2300 ldrd r2, r3, [r3] 800d7a4: f002 4380 and.w r3, r2, #1073741824 @ 0x40000000 800d7a8: 643b str r3, [r7, #64] @ 0x40 800d7aa: 2300 movs r3, #0 800d7ac: 647b str r3, [r7, #68] @ 0x44 800d7ae: e9d7 1210 ldrd r1, r2, [r7, #64] @ 0x40 800d7b2: 460b mov r3, r1 800d7b4: 4313 orrs r3, r2 800d7b6: d00e beq.n 800d7d6 { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 800d7b8: 4b86 ldr r3, [pc, #536] @ (800d9d4 ) 800d7ba: 691b ldr r3, [r3, #16] 800d7bc: 4a85 ldr r2, [pc, #532] @ (800d9d4 ) 800d7be: f423 4300 bic.w r3, r3, #32768 @ 0x8000 800d7c2: 6113 str r3, [r2, #16] 800d7c4: 4b83 ldr r3, [pc, #524] @ (800d9d4 ) 800d7c6: 6919 ldr r1, [r3, #16] 800d7c8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7cc: f8d3 30bc ldr.w r3, [r3, #188] @ 0xbc 800d7d0: 4a80 ldr r2, [pc, #512] @ (800d9d4 ) 800d7d2: 430b orrs r3, r1 800d7d4: 6113 str r3, [r2, #16] } /*------------------------------------ CKPER configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 800d7d6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7da: e9d3 2300 ldrd r2, r3, [r3] 800d7de: f002 4300 and.w r3, r2, #2147483648 @ 0x80000000 800d7e2: 63bb str r3, [r7, #56] @ 0x38 800d7e4: 2300 movs r3, #0 800d7e6: 63fb str r3, [r7, #60] @ 0x3c 800d7e8: e9d7 120e ldrd r1, r2, [r7, #56] @ 0x38 800d7ec: 460b mov r3, r1 800d7ee: 4313 orrs r3, r2 800d7f0: d009 beq.n 800d806 { /* Check the parameters */ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); /* Configure the CKPER clock source */ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 800d7f2: 4b78 ldr r3, [pc, #480] @ (800d9d4 ) 800d7f4: 6cdb ldr r3, [r3, #76] @ 0x4c 800d7f6: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 800d7fa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7fe: 6d5b ldr r3, [r3, #84] @ 0x54 800d800: 4a74 ldr r2, [pc, #464] @ (800d9d4 ) 800d802: 430b orrs r3, r1 800d804: 64d3 str r3, [r2, #76] @ 0x4c } /*------------------------------ CEC Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 800d806: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d80a: e9d3 2300 ldrd r2, r3, [r3] 800d80e: f402 0300 and.w r3, r2, #8388608 @ 0x800000 800d812: 633b str r3, [r7, #48] @ 0x30 800d814: 2300 movs r3, #0 800d816: 637b str r3, [r7, #52] @ 0x34 800d818: e9d7 120c ldrd r1, r2, [r7, #48] @ 0x30 800d81c: 460b mov r3, r1 800d81e: 4313 orrs r3, r2 800d820: d00a beq.n 800d838 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC interface clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 800d822: 4b6c ldr r3, [pc, #432] @ (800d9d4 ) 800d824: 6d5b ldr r3, [r3, #84] @ 0x54 800d826: f423 0140 bic.w r1, r3, #12582912 @ 0xc00000 800d82a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d82e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800d832: 4a68 ldr r2, [pc, #416] @ (800d9d4 ) 800d834: 430b orrs r3, r1 800d836: 6553 str r3, [r2, #84] @ 0x54 } /*---------------------------- PLL2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) 800d838: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d83c: e9d3 2300 ldrd r2, r3, [r3] 800d840: 2100 movs r1, #0 800d842: 62b9 str r1, [r7, #40] @ 0x28 800d844: f003 0301 and.w r3, r3, #1 800d848: 62fb str r3, [r7, #44] @ 0x2c 800d84a: e9d7 120a ldrd r1, r2, [r7, #40] @ 0x28 800d84e: 460b mov r3, r1 800d850: 4313 orrs r3, r2 800d852: d011 beq.n 800d878 { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d854: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d858: 3308 adds r3, #8 800d85a: 2100 movs r1, #0 800d85c: 4618 mov r0, r3 800d85e: f001 fa4b bl 800ecf8 800d862: 4603 mov r3, r0 800d864: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800d868: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d86c: 2b00 cmp r3, #0 800d86e: d003 beq.n 800d878 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800d870: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d874: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) 800d878: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d87c: e9d3 2300 ldrd r2, r3, [r3] 800d880: 2100 movs r1, #0 800d882: 6239 str r1, [r7, #32] 800d884: f003 0302 and.w r3, r3, #2 800d888: 627b str r3, [r7, #36] @ 0x24 800d88a: e9d7 1208 ldrd r1, r2, [r7, #32] 800d88e: 460b mov r3, r1 800d890: 4313 orrs r3, r2 800d892: d011 beq.n 800d8b8 { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d894: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d898: 3308 adds r3, #8 800d89a: 2101 movs r1, #1 800d89c: 4618 mov r0, r3 800d89e: f001 fa2b bl 800ecf8 800d8a2: 4603 mov r3, r0 800d8a4: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800d8a8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d8ac: 2b00 cmp r3, #0 800d8ae: d003 beq.n 800d8b8 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800d8b0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d8b4: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) 800d8b8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8bc: e9d3 2300 ldrd r2, r3, [r3] 800d8c0: 2100 movs r1, #0 800d8c2: 61b9 str r1, [r7, #24] 800d8c4: f003 0304 and.w r3, r3, #4 800d8c8: 61fb str r3, [r7, #28] 800d8ca: e9d7 1206 ldrd r1, r2, [r7, #24] 800d8ce: 460b mov r3, r1 800d8d0: 4313 orrs r3, r2 800d8d2: d011 beq.n 800d8f8 { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800d8d4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8d8: 3308 adds r3, #8 800d8da: 2102 movs r1, #2 800d8dc: 4618 mov r0, r3 800d8de: f001 fa0b bl 800ecf8 800d8e2: 4603 mov r3, r0 800d8e4: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800d8e8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d8ec: 2b00 cmp r3, #0 800d8ee: d003 beq.n 800d8f8 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800d8f0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d8f4: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- PLL3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) 800d8f8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8fc: e9d3 2300 ldrd r2, r3, [r3] 800d900: 2100 movs r1, #0 800d902: 6139 str r1, [r7, #16] 800d904: f003 0308 and.w r3, r3, #8 800d908: 617b str r3, [r7, #20] 800d90a: e9d7 1204 ldrd r1, r2, [r7, #16] 800d90e: 460b mov r3, r1 800d910: 4313 orrs r3, r2 800d912: d011 beq.n 800d938 { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800d914: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d918: 3328 adds r3, #40 @ 0x28 800d91a: 2100 movs r1, #0 800d91c: 4618 mov r0, r3 800d91e: f001 fa9d bl 800ee5c 800d922: 4603 mov r3, r0 800d924: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800d928: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d92c: 2b00 cmp r3, #0 800d92e: d003 beq.n 800d938 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800d930: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d934: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) 800d938: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d93c: e9d3 2300 ldrd r2, r3, [r3] 800d940: 2100 movs r1, #0 800d942: 60b9 str r1, [r7, #8] 800d944: f003 0310 and.w r3, r3, #16 800d948: 60fb str r3, [r7, #12] 800d94a: e9d7 1202 ldrd r1, r2, [r7, #8] 800d94e: 460b mov r3, r1 800d950: 4313 orrs r3, r2 800d952: d011 beq.n 800d978 { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d954: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d958: 3328 adds r3, #40 @ 0x28 800d95a: 2101 movs r1, #1 800d95c: 4618 mov r0, r3 800d95e: f001 fa7d bl 800ee5c 800d962: 4603 mov r3, r0 800d964: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800d968: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d96c: 2b00 cmp r3, #0 800d96e: d003 beq.n 800d978 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800d970: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d974: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) 800d978: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d97c: e9d3 2300 ldrd r2, r3, [r3] 800d980: 2100 movs r1, #0 800d982: 6039 str r1, [r7, #0] 800d984: f003 0320 and.w r3, r3, #32 800d988: 607b str r3, [r7, #4] 800d98a: e9d7 1200 ldrd r1, r2, [r7] 800d98e: 460b mov r3, r1 800d990: 4313 orrs r3, r2 800d992: d011 beq.n 800d9b8 { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d994: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d998: 3328 adds r3, #40 @ 0x28 800d99a: 2102 movs r1, #2 800d99c: 4618 mov r0, r3 800d99e: f001 fa5d bl 800ee5c 800d9a2: 4603 mov r3, r0 800d9a4: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800d9a8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d9ac: 2b00 cmp r3, #0 800d9ae: d003 beq.n 800d9b8 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800d9b0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d9b4: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (status == HAL_OK) 800d9b8: f897 311e ldrb.w r3, [r7, #286] @ 0x11e 800d9bc: 2b00 cmp r3, #0 800d9be: d101 bne.n 800d9c4 { return HAL_OK; 800d9c0: 2300 movs r3, #0 800d9c2: e000 b.n 800d9c6 } return HAL_ERROR; 800d9c4: 2301 movs r3, #1 } 800d9c6: 4618 mov r0, r3 800d9c8: f507 7790 add.w r7, r7, #288 @ 0x120 800d9cc: 46bd mov sp, r7 800d9ce: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 800d9d2: bf00 nop 800d9d4: 58024400 .word 0x58024400 0800d9d8 : * @retval Frequency in KHz * * (*) : Available on some STM32H7 lines only. */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) { 800d9d8: b580 push {r7, lr} 800d9da: b090 sub sp, #64 @ 0x40 800d9dc: af00 add r7, sp, #0 800d9de: e9c7 0100 strd r0, r1, [r7] /* This variable is used to store the SAI and CKP clock source */ uint32_t saiclocksource; uint32_t ckpclocksource; uint32_t srcclk; if (PeriphClk == RCC_PERIPHCLK_SAI1) 800d9e2: e9d7 2300 ldrd r2, r3, [r7] 800d9e6: f5a2 7180 sub.w r1, r2, #256 @ 0x100 800d9ea: 430b orrs r3, r1 800d9ec: f040 8094 bne.w 800db18 { saiclocksource = __HAL_RCC_GET_SAI1_SOURCE(); 800d9f0: 4b9e ldr r3, [pc, #632] @ (800dc6c ) 800d9f2: 6d1b ldr r3, [r3, #80] @ 0x50 800d9f4: f003 0307 and.w r3, r3, #7 800d9f8: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800d9fa: 6b3b ldr r3, [r7, #48] @ 0x30 800d9fc: 2b04 cmp r3, #4 800d9fe: f200 8087 bhi.w 800db10 800da02: a201 add r2, pc, #4 @ (adr r2, 800da08 ) 800da04: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800da08: 0800da1d .word 0x0800da1d 800da0c: 0800da45 .word 0x0800da45 800da10: 0800da6d .word 0x0800da6d 800da14: 0800db09 .word 0x0800db09 800da18: 0800da95 .word 0x0800da95 { case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800da1c: 4b93 ldr r3, [pc, #588] @ (800dc6c ) 800da1e: 681b ldr r3, [r3, #0] 800da20: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800da24: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800da28: d108 bne.n 800da3c { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800da2a: f107 0324 add.w r3, r7, #36 @ 0x24 800da2e: 4618 mov r0, r3 800da30: f001 f810 bl 800ea54 frequency = pll1_clocks.PLL1_Q_Frequency; 800da34: 6abb ldr r3, [r7, #40] @ 0x28 800da36: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800da38: f000 bd45 b.w 800e4c6 frequency = 0; 800da3c: 2300 movs r3, #0 800da3e: 63fb str r3, [r7, #60] @ 0x3c break; 800da40: f000 bd41 b.w 800e4c6 } case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800da44: 4b89 ldr r3, [pc, #548] @ (800dc6c ) 800da46: 681b ldr r3, [r3, #0] 800da48: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800da4c: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800da50: d108 bne.n 800da64 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800da52: f107 0318 add.w r3, r7, #24 800da56: 4618 mov r0, r3 800da58: f000 fd54 bl 800e504 frequency = pll2_clocks.PLL2_P_Frequency; 800da5c: 69bb ldr r3, [r7, #24] 800da5e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800da60: f000 bd31 b.w 800e4c6 frequency = 0; 800da64: 2300 movs r3, #0 800da66: 63fb str r3, [r7, #60] @ 0x3c break; 800da68: f000 bd2d b.w 800e4c6 } case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800da6c: 4b7f ldr r3, [pc, #508] @ (800dc6c ) 800da6e: 681b ldr r3, [r3, #0] 800da70: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800da74: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800da78: d108 bne.n 800da8c { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800da7a: f107 030c add.w r3, r7, #12 800da7e: 4618 mov r0, r3 800da80: f000 fe94 bl 800e7ac frequency = pll3_clocks.PLL3_P_Frequency; 800da84: 68fb ldr r3, [r7, #12] 800da86: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800da88: f000 bd1d b.w 800e4c6 frequency = 0; 800da8c: 2300 movs r3, #0 800da8e: 63fb str r3, [r7, #60] @ 0x3c break; 800da90: f000 bd19 b.w 800e4c6 } case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800da94: 4b75 ldr r3, [pc, #468] @ (800dc6c ) 800da96: 6cdb ldr r3, [r3, #76] @ 0x4c 800da98: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800da9c: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800da9e: 4b73 ldr r3, [pc, #460] @ (800dc6c ) 800daa0: 681b ldr r3, [r3, #0] 800daa2: f003 0304 and.w r3, r3, #4 800daa6: 2b04 cmp r3, #4 800daa8: d10c bne.n 800dac4 800daaa: 6b7b ldr r3, [r7, #52] @ 0x34 800daac: 2b00 cmp r3, #0 800daae: d109 bne.n 800dac4 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800dab0: 4b6e ldr r3, [pc, #440] @ (800dc6c ) 800dab2: 681b ldr r3, [r3, #0] 800dab4: 08db lsrs r3, r3, #3 800dab6: f003 0303 and.w r3, r3, #3 800daba: 4a6d ldr r2, [pc, #436] @ (800dc70 ) 800dabc: fa22 f303 lsr.w r3, r2, r3 800dac0: 63fb str r3, [r7, #60] @ 0x3c 800dac2: e01f b.n 800db04 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800dac4: 4b69 ldr r3, [pc, #420] @ (800dc6c ) 800dac6: 681b ldr r3, [r3, #0] 800dac8: f403 7380 and.w r3, r3, #256 @ 0x100 800dacc: f5b3 7f80 cmp.w r3, #256 @ 0x100 800dad0: d106 bne.n 800dae0 800dad2: 6b7b ldr r3, [r7, #52] @ 0x34 800dad4: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800dad8: d102 bne.n 800dae0 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800dada: 4b66 ldr r3, [pc, #408] @ (800dc74 ) 800dadc: 63fb str r3, [r7, #60] @ 0x3c 800dade: e011 b.n 800db04 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800dae0: 4b62 ldr r3, [pc, #392] @ (800dc6c ) 800dae2: 681b ldr r3, [r3, #0] 800dae4: f403 3300 and.w r3, r3, #131072 @ 0x20000 800dae8: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800daec: d106 bne.n 800dafc 800daee: 6b7b ldr r3, [r7, #52] @ 0x34 800daf0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800daf4: d102 bne.n 800dafc { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800daf6: 4b60 ldr r3, [pc, #384] @ (800dc78 ) 800daf8: 63fb str r3, [r7, #60] @ 0x3c 800dafa: e003 b.n 800db04 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800dafc: 2300 movs r3, #0 800dafe: 63fb str r3, [r7, #60] @ 0x3c } break; 800db00: f000 bce1 b.w 800e4c6 800db04: f000 bcdf b.w 800e4c6 } case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ { frequency = EXTERNAL_CLOCK_VALUE; 800db08: 4b5c ldr r3, [pc, #368] @ (800dc7c ) 800db0a: 63fb str r3, [r7, #60] @ 0x3c break; 800db0c: f000 bcdb b.w 800e4c6 } default : { frequency = 0; 800db10: 2300 movs r3, #0 800db12: 63fb str r3, [r7, #60] @ 0x3c break; 800db14: f000 bcd7 b.w 800e4c6 } } } #if defined(SAI3) else if (PeriphClk == RCC_PERIPHCLK_SAI23) 800db18: e9d7 2300 ldrd r2, r3, [r7] 800db1c: f5a2 7100 sub.w r1, r2, #512 @ 0x200 800db20: 430b orrs r3, r1 800db22: f040 80ad bne.w 800dc80 { saiclocksource = __HAL_RCC_GET_SAI23_SOURCE(); 800db26: 4b51 ldr r3, [pc, #324] @ (800dc6c ) 800db28: 6d1b ldr r3, [r3, #80] @ 0x50 800db2a: f403 73e0 and.w r3, r3, #448 @ 0x1c0 800db2e: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800db30: 6b3b ldr r3, [r7, #48] @ 0x30 800db32: f5b3 7f80 cmp.w r3, #256 @ 0x100 800db36: d056 beq.n 800dbe6 800db38: 6b3b ldr r3, [r7, #48] @ 0x30 800db3a: f5b3 7f80 cmp.w r3, #256 @ 0x100 800db3e: f200 8090 bhi.w 800dc62 800db42: 6b3b ldr r3, [r7, #48] @ 0x30 800db44: 2bc0 cmp r3, #192 @ 0xc0 800db46: f000 8088 beq.w 800dc5a 800db4a: 6b3b ldr r3, [r7, #48] @ 0x30 800db4c: 2bc0 cmp r3, #192 @ 0xc0 800db4e: f200 8088 bhi.w 800dc62 800db52: 6b3b ldr r3, [r7, #48] @ 0x30 800db54: 2b80 cmp r3, #128 @ 0x80 800db56: d032 beq.n 800dbbe 800db58: 6b3b ldr r3, [r7, #48] @ 0x30 800db5a: 2b80 cmp r3, #128 @ 0x80 800db5c: f200 8081 bhi.w 800dc62 800db60: 6b3b ldr r3, [r7, #48] @ 0x30 800db62: 2b00 cmp r3, #0 800db64: d003 beq.n 800db6e 800db66: 6b3b ldr r3, [r7, #48] @ 0x30 800db68: 2b40 cmp r3, #64 @ 0x40 800db6a: d014 beq.n 800db96 800db6c: e079 b.n 800dc62 { case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800db6e: 4b3f ldr r3, [pc, #252] @ (800dc6c ) 800db70: 681b ldr r3, [r3, #0] 800db72: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800db76: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800db7a: d108 bne.n 800db8e { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800db7c: f107 0324 add.w r3, r7, #36 @ 0x24 800db80: 4618 mov r0, r3 800db82: f000 ff67 bl 800ea54 frequency = pll1_clocks.PLL1_Q_Frequency; 800db86: 6abb ldr r3, [r7, #40] @ 0x28 800db88: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800db8a: f000 bc9c b.w 800e4c6 frequency = 0; 800db8e: 2300 movs r3, #0 800db90: 63fb str r3, [r7, #60] @ 0x3c break; 800db92: f000 bc98 b.w 800e4c6 } case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800db96: 4b35 ldr r3, [pc, #212] @ (800dc6c ) 800db98: 681b ldr r3, [r3, #0] 800db9a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800db9e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800dba2: d108 bne.n 800dbb6 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800dba4: f107 0318 add.w r3, r7, #24 800dba8: 4618 mov r0, r3 800dbaa: f000 fcab bl 800e504 frequency = pll2_clocks.PLL2_P_Frequency; 800dbae: 69bb ldr r3, [r7, #24] 800dbb0: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dbb2: f000 bc88 b.w 800e4c6 frequency = 0; 800dbb6: 2300 movs r3, #0 800dbb8: 63fb str r3, [r7, #60] @ 0x3c break; 800dbba: f000 bc84 b.w 800e4c6 } case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800dbbe: 4b2b ldr r3, [pc, #172] @ (800dc6c ) 800dbc0: 681b ldr r3, [r3, #0] 800dbc2: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800dbc6: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800dbca: d108 bne.n 800dbde { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800dbcc: f107 030c add.w r3, r7, #12 800dbd0: 4618 mov r0, r3 800dbd2: f000 fdeb bl 800e7ac frequency = pll3_clocks.PLL3_P_Frequency; 800dbd6: 68fb ldr r3, [r7, #12] 800dbd8: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dbda: f000 bc74 b.w 800e4c6 frequency = 0; 800dbde: 2300 movs r3, #0 800dbe0: 63fb str r3, [r7, #60] @ 0x3c break; 800dbe2: f000 bc70 b.w 800e4c6 } case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800dbe6: 4b21 ldr r3, [pc, #132] @ (800dc6c ) 800dbe8: 6cdb ldr r3, [r3, #76] @ 0x4c 800dbea: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800dbee: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800dbf0: 4b1e ldr r3, [pc, #120] @ (800dc6c ) 800dbf2: 681b ldr r3, [r3, #0] 800dbf4: f003 0304 and.w r3, r3, #4 800dbf8: 2b04 cmp r3, #4 800dbfa: d10c bne.n 800dc16 800dbfc: 6b7b ldr r3, [r7, #52] @ 0x34 800dbfe: 2b00 cmp r3, #0 800dc00: d109 bne.n 800dc16 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800dc02: 4b1a ldr r3, [pc, #104] @ (800dc6c ) 800dc04: 681b ldr r3, [r3, #0] 800dc06: 08db lsrs r3, r3, #3 800dc08: f003 0303 and.w r3, r3, #3 800dc0c: 4a18 ldr r2, [pc, #96] @ (800dc70 ) 800dc0e: fa22 f303 lsr.w r3, r2, r3 800dc12: 63fb str r3, [r7, #60] @ 0x3c 800dc14: e01f b.n 800dc56 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800dc16: 4b15 ldr r3, [pc, #84] @ (800dc6c ) 800dc18: 681b ldr r3, [r3, #0] 800dc1a: f403 7380 and.w r3, r3, #256 @ 0x100 800dc1e: f5b3 7f80 cmp.w r3, #256 @ 0x100 800dc22: d106 bne.n 800dc32 800dc24: 6b7b ldr r3, [r7, #52] @ 0x34 800dc26: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800dc2a: d102 bne.n 800dc32 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800dc2c: 4b11 ldr r3, [pc, #68] @ (800dc74 ) 800dc2e: 63fb str r3, [r7, #60] @ 0x3c 800dc30: e011 b.n 800dc56 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800dc32: 4b0e ldr r3, [pc, #56] @ (800dc6c ) 800dc34: 681b ldr r3, [r3, #0] 800dc36: f403 3300 and.w r3, r3, #131072 @ 0x20000 800dc3a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800dc3e: d106 bne.n 800dc4e 800dc40: 6b7b ldr r3, [r7, #52] @ 0x34 800dc42: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800dc46: d102 bne.n 800dc4e { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800dc48: 4b0b ldr r3, [pc, #44] @ (800dc78 ) 800dc4a: 63fb str r3, [r7, #60] @ 0x3c 800dc4c: e003 b.n 800dc56 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800dc4e: 2300 movs r3, #0 800dc50: 63fb str r3, [r7, #60] @ 0x3c } break; 800dc52: f000 bc38 b.w 800e4c6 800dc56: f000 bc36 b.w 800e4c6 } case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ { frequency = EXTERNAL_CLOCK_VALUE; 800dc5a: 4b08 ldr r3, [pc, #32] @ (800dc7c ) 800dc5c: 63fb str r3, [r7, #60] @ 0x3c break; 800dc5e: f000 bc32 b.w 800e4c6 } default : { frequency = 0; 800dc62: 2300 movs r3, #0 800dc64: 63fb str r3, [r7, #60] @ 0x3c break; 800dc66: f000 bc2e b.w 800e4c6 800dc6a: bf00 nop 800dc6c: 58024400 .word 0x58024400 800dc70: 03d09000 .word 0x03d09000 800dc74: 003d0900 .word 0x003d0900 800dc78: 017d7840 .word 0x017d7840 800dc7c: 00bb8000 .word 0x00bb8000 } } #endif #if defined(SAI4) else if (PeriphClk == RCC_PERIPHCLK_SAI4A) 800dc80: e9d7 2300 ldrd r2, r3, [r7] 800dc84: f5a2 6180 sub.w r1, r2, #1024 @ 0x400 800dc88: 430b orrs r3, r1 800dc8a: f040 809c bne.w 800ddc6 { saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE(); 800dc8e: 4b9e ldr r3, [pc, #632] @ (800df08 ) 800dc90: 6d9b ldr r3, [r3, #88] @ 0x58 800dc92: f403 0360 and.w r3, r3, #14680064 @ 0xe00000 800dc96: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800dc98: 6b3b ldr r3, [r7, #48] @ 0x30 800dc9a: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800dc9e: d054 beq.n 800dd4a 800dca0: 6b3b ldr r3, [r7, #48] @ 0x30 800dca2: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800dca6: f200 808b bhi.w 800ddc0 800dcaa: 6b3b ldr r3, [r7, #48] @ 0x30 800dcac: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800dcb0: f000 8083 beq.w 800ddba 800dcb4: 6b3b ldr r3, [r7, #48] @ 0x30 800dcb6: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800dcba: f200 8081 bhi.w 800ddc0 800dcbe: 6b3b ldr r3, [r7, #48] @ 0x30 800dcc0: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800dcc4: d02f beq.n 800dd26 800dcc6: 6b3b ldr r3, [r7, #48] @ 0x30 800dcc8: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800dccc: d878 bhi.n 800ddc0 800dcce: 6b3b ldr r3, [r7, #48] @ 0x30 800dcd0: 2b00 cmp r3, #0 800dcd2: d004 beq.n 800dcde 800dcd4: 6b3b ldr r3, [r7, #48] @ 0x30 800dcd6: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800dcda: d012 beq.n 800dd02 800dcdc: e070 b.n 800ddc0 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800dcde: 4b8a ldr r3, [pc, #552] @ (800df08 ) 800dce0: 681b ldr r3, [r3, #0] 800dce2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800dce6: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800dcea: d107 bne.n 800dcfc { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800dcec: f107 0324 add.w r3, r7, #36 @ 0x24 800dcf0: 4618 mov r0, r3 800dcf2: f000 feaf bl 800ea54 frequency = pll1_clocks.PLL1_Q_Frequency; 800dcf6: 6abb ldr r3, [r7, #40] @ 0x28 800dcf8: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dcfa: e3e4 b.n 800e4c6 frequency = 0; 800dcfc: 2300 movs r3, #0 800dcfe: 63fb str r3, [r7, #60] @ 0x3c break; 800dd00: e3e1 b.n 800e4c6 } case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800dd02: 4b81 ldr r3, [pc, #516] @ (800df08 ) 800dd04: 681b ldr r3, [r3, #0] 800dd06: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800dd0a: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800dd0e: d107 bne.n 800dd20 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800dd10: f107 0318 add.w r3, r7, #24 800dd14: 4618 mov r0, r3 800dd16: f000 fbf5 bl 800e504 frequency = pll2_clocks.PLL2_P_Frequency; 800dd1a: 69bb ldr r3, [r7, #24] 800dd1c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dd1e: e3d2 b.n 800e4c6 frequency = 0; 800dd20: 2300 movs r3, #0 800dd22: 63fb str r3, [r7, #60] @ 0x3c break; 800dd24: e3cf b.n 800e4c6 } case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800dd26: 4b78 ldr r3, [pc, #480] @ (800df08 ) 800dd28: 681b ldr r3, [r3, #0] 800dd2a: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800dd2e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800dd32: d107 bne.n 800dd44 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800dd34: f107 030c add.w r3, r7, #12 800dd38: 4618 mov r0, r3 800dd3a: f000 fd37 bl 800e7ac frequency = pll3_clocks.PLL3_P_Frequency; 800dd3e: 68fb ldr r3, [r7, #12] 800dd40: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dd42: e3c0 b.n 800e4c6 frequency = 0; 800dd44: 2300 movs r3, #0 800dd46: 63fb str r3, [r7, #60] @ 0x3c break; 800dd48: e3bd b.n 800e4c6 } case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800dd4a: 4b6f ldr r3, [pc, #444] @ (800df08 ) 800dd4c: 6cdb ldr r3, [r3, #76] @ 0x4c 800dd4e: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800dd52: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800dd54: 4b6c ldr r3, [pc, #432] @ (800df08 ) 800dd56: 681b ldr r3, [r3, #0] 800dd58: f003 0304 and.w r3, r3, #4 800dd5c: 2b04 cmp r3, #4 800dd5e: d10c bne.n 800dd7a 800dd60: 6b7b ldr r3, [r7, #52] @ 0x34 800dd62: 2b00 cmp r3, #0 800dd64: d109 bne.n 800dd7a { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800dd66: 4b68 ldr r3, [pc, #416] @ (800df08 ) 800dd68: 681b ldr r3, [r3, #0] 800dd6a: 08db lsrs r3, r3, #3 800dd6c: f003 0303 and.w r3, r3, #3 800dd70: 4a66 ldr r2, [pc, #408] @ (800df0c ) 800dd72: fa22 f303 lsr.w r3, r2, r3 800dd76: 63fb str r3, [r7, #60] @ 0x3c 800dd78: e01e b.n 800ddb8 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800dd7a: 4b63 ldr r3, [pc, #396] @ (800df08 ) 800dd7c: 681b ldr r3, [r3, #0] 800dd7e: f403 7380 and.w r3, r3, #256 @ 0x100 800dd82: f5b3 7f80 cmp.w r3, #256 @ 0x100 800dd86: d106 bne.n 800dd96 800dd88: 6b7b ldr r3, [r7, #52] @ 0x34 800dd8a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800dd8e: d102 bne.n 800dd96 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800dd90: 4b5f ldr r3, [pc, #380] @ (800df10 ) 800dd92: 63fb str r3, [r7, #60] @ 0x3c 800dd94: e010 b.n 800ddb8 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800dd96: 4b5c ldr r3, [pc, #368] @ (800df08 ) 800dd98: 681b ldr r3, [r3, #0] 800dd9a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800dd9e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800dda2: d106 bne.n 800ddb2 800dda4: 6b7b ldr r3, [r7, #52] @ 0x34 800dda6: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800ddaa: d102 bne.n 800ddb2 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800ddac: 4b59 ldr r3, [pc, #356] @ (800df14 ) 800ddae: 63fb str r3, [r7, #60] @ 0x3c 800ddb0: e002 b.n 800ddb8 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800ddb2: 2300 movs r3, #0 800ddb4: 63fb str r3, [r7, #60] @ 0x3c } break; 800ddb6: e386 b.n 800e4c6 800ddb8: e385 b.n 800e4c6 } case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ { frequency = EXTERNAL_CLOCK_VALUE; 800ddba: 4b57 ldr r3, [pc, #348] @ (800df18 ) 800ddbc: 63fb str r3, [r7, #60] @ 0x3c break; 800ddbe: e382 b.n 800e4c6 } default : { frequency = 0; 800ddc0: 2300 movs r3, #0 800ddc2: 63fb str r3, [r7, #60] @ 0x3c break; 800ddc4: e37f b.n 800e4c6 } } } else if (PeriphClk == RCC_PERIPHCLK_SAI4B) 800ddc6: e9d7 2300 ldrd r2, r3, [r7] 800ddca: f5a2 6100 sub.w r1, r2, #2048 @ 0x800 800ddce: 430b orrs r3, r1 800ddd0: f040 80a7 bne.w 800df22 { saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE(); 800ddd4: 4b4c ldr r3, [pc, #304] @ (800df08 ) 800ddd6: 6d9b ldr r3, [r3, #88] @ 0x58 800ddd8: f003 63e0 and.w r3, r3, #117440512 @ 0x7000000 800dddc: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800ddde: 6b3b ldr r3, [r7, #48] @ 0x30 800dde0: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800dde4: d055 beq.n 800de92 800dde6: 6b3b ldr r3, [r7, #48] @ 0x30 800dde8: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800ddec: f200 8096 bhi.w 800df1c 800ddf0: 6b3b ldr r3, [r7, #48] @ 0x30 800ddf2: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800ddf6: f000 8084 beq.w 800df02 800ddfa: 6b3b ldr r3, [r7, #48] @ 0x30 800ddfc: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800de00: f200 808c bhi.w 800df1c 800de04: 6b3b ldr r3, [r7, #48] @ 0x30 800de06: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800de0a: d030 beq.n 800de6e 800de0c: 6b3b ldr r3, [r7, #48] @ 0x30 800de0e: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800de12: f200 8083 bhi.w 800df1c 800de16: 6b3b ldr r3, [r7, #48] @ 0x30 800de18: 2b00 cmp r3, #0 800de1a: d004 beq.n 800de26 800de1c: 6b3b ldr r3, [r7, #48] @ 0x30 800de1e: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800de22: d012 beq.n 800de4a 800de24: e07a b.n 800df1c { case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800de26: 4b38 ldr r3, [pc, #224] @ (800df08 ) 800de28: 681b ldr r3, [r3, #0] 800de2a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800de2e: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800de32: d107 bne.n 800de44 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800de34: f107 0324 add.w r3, r7, #36 @ 0x24 800de38: 4618 mov r0, r3 800de3a: f000 fe0b bl 800ea54 frequency = pll1_clocks.PLL1_Q_Frequency; 800de3e: 6abb ldr r3, [r7, #40] @ 0x28 800de40: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800de42: e340 b.n 800e4c6 frequency = 0; 800de44: 2300 movs r3, #0 800de46: 63fb str r3, [r7, #60] @ 0x3c break; 800de48: e33d b.n 800e4c6 } case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800de4a: 4b2f ldr r3, [pc, #188] @ (800df08 ) 800de4c: 681b ldr r3, [r3, #0] 800de4e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800de52: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800de56: d107 bne.n 800de68 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800de58: f107 0318 add.w r3, r7, #24 800de5c: 4618 mov r0, r3 800de5e: f000 fb51 bl 800e504 frequency = pll2_clocks.PLL2_P_Frequency; 800de62: 69bb ldr r3, [r7, #24] 800de64: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800de66: e32e b.n 800e4c6 frequency = 0; 800de68: 2300 movs r3, #0 800de6a: 63fb str r3, [r7, #60] @ 0x3c break; 800de6c: e32b b.n 800e4c6 } case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800de6e: 4b26 ldr r3, [pc, #152] @ (800df08 ) 800de70: 681b ldr r3, [r3, #0] 800de72: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800de76: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800de7a: d107 bne.n 800de8c { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800de7c: f107 030c add.w r3, r7, #12 800de80: 4618 mov r0, r3 800de82: f000 fc93 bl 800e7ac frequency = pll3_clocks.PLL3_P_Frequency; 800de86: 68fb ldr r3, [r7, #12] 800de88: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800de8a: e31c b.n 800e4c6 frequency = 0; 800de8c: 2300 movs r3, #0 800de8e: 63fb str r3, [r7, #60] @ 0x3c break; 800de90: e319 b.n 800e4c6 } case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800de92: 4b1d ldr r3, [pc, #116] @ (800df08 ) 800de94: 6cdb ldr r3, [r3, #76] @ 0x4c 800de96: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800de9a: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800de9c: 4b1a ldr r3, [pc, #104] @ (800df08 ) 800de9e: 681b ldr r3, [r3, #0] 800dea0: f003 0304 and.w r3, r3, #4 800dea4: 2b04 cmp r3, #4 800dea6: d10c bne.n 800dec2 800dea8: 6b7b ldr r3, [r7, #52] @ 0x34 800deaa: 2b00 cmp r3, #0 800deac: d109 bne.n 800dec2 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800deae: 4b16 ldr r3, [pc, #88] @ (800df08 ) 800deb0: 681b ldr r3, [r3, #0] 800deb2: 08db lsrs r3, r3, #3 800deb4: f003 0303 and.w r3, r3, #3 800deb8: 4a14 ldr r2, [pc, #80] @ (800df0c ) 800deba: fa22 f303 lsr.w r3, r2, r3 800debe: 63fb str r3, [r7, #60] @ 0x3c 800dec0: e01e b.n 800df00 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800dec2: 4b11 ldr r3, [pc, #68] @ (800df08 ) 800dec4: 681b ldr r3, [r3, #0] 800dec6: f403 7380 and.w r3, r3, #256 @ 0x100 800deca: f5b3 7f80 cmp.w r3, #256 @ 0x100 800dece: d106 bne.n 800dede 800ded0: 6b7b ldr r3, [r7, #52] @ 0x34 800ded2: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800ded6: d102 bne.n 800dede { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800ded8: 4b0d ldr r3, [pc, #52] @ (800df10 ) 800deda: 63fb str r3, [r7, #60] @ 0x3c 800dedc: e010 b.n 800df00 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800dede: 4b0a ldr r3, [pc, #40] @ (800df08 ) 800dee0: 681b ldr r3, [r3, #0] 800dee2: f403 3300 and.w r3, r3, #131072 @ 0x20000 800dee6: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800deea: d106 bne.n 800defa 800deec: 6b7b ldr r3, [r7, #52] @ 0x34 800deee: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800def2: d102 bne.n 800defa { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800def4: 4b07 ldr r3, [pc, #28] @ (800df14 ) 800def6: 63fb str r3, [r7, #60] @ 0x3c 800def8: e002 b.n 800df00 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800defa: 2300 movs r3, #0 800defc: 63fb str r3, [r7, #60] @ 0x3c } break; 800defe: e2e2 b.n 800e4c6 800df00: e2e1 b.n 800e4c6 } case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ { frequency = EXTERNAL_CLOCK_VALUE; 800df02: 4b05 ldr r3, [pc, #20] @ (800df18 ) 800df04: 63fb str r3, [r7, #60] @ 0x3c break; 800df06: e2de b.n 800e4c6 800df08: 58024400 .word 0x58024400 800df0c: 03d09000 .word 0x03d09000 800df10: 003d0900 .word 0x003d0900 800df14: 017d7840 .word 0x017d7840 800df18: 00bb8000 .word 0x00bb8000 } default : { frequency = 0; 800df1c: 2300 movs r3, #0 800df1e: 63fb str r3, [r7, #60] @ 0x3c break; 800df20: e2d1 b.n 800e4c6 } } } #endif /*SAI4*/ else if (PeriphClk == RCC_PERIPHCLK_SPI123) 800df22: e9d7 2300 ldrd r2, r3, [r7] 800df26: f5a2 5180 sub.w r1, r2, #4096 @ 0x1000 800df2a: 430b orrs r3, r1 800df2c: f040 809c bne.w 800e068 { /* Get SPI1/2/3 clock source */ srcclk = __HAL_RCC_GET_SPI123_SOURCE(); 800df30: 4b93 ldr r3, [pc, #588] @ (800e180 ) 800df32: 6d1b ldr r3, [r3, #80] @ 0x50 800df34: f403 43e0 and.w r3, r3, #28672 @ 0x7000 800df38: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800df3a: 6bbb ldr r3, [r7, #56] @ 0x38 800df3c: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800df40: d054 beq.n 800dfec 800df42: 6bbb ldr r3, [r7, #56] @ 0x38 800df44: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800df48: f200 808b bhi.w 800e062 800df4c: 6bbb ldr r3, [r7, #56] @ 0x38 800df4e: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800df52: f000 8083 beq.w 800e05c 800df56: 6bbb ldr r3, [r7, #56] @ 0x38 800df58: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800df5c: f200 8081 bhi.w 800e062 800df60: 6bbb ldr r3, [r7, #56] @ 0x38 800df62: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800df66: d02f beq.n 800dfc8 800df68: 6bbb ldr r3, [r7, #56] @ 0x38 800df6a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800df6e: d878 bhi.n 800e062 800df70: 6bbb ldr r3, [r7, #56] @ 0x38 800df72: 2b00 cmp r3, #0 800df74: d004 beq.n 800df80 800df76: 6bbb ldr r3, [r7, #56] @ 0x38 800df78: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800df7c: d012 beq.n 800dfa4 800df7e: e070 b.n 800e062 { case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800df80: 4b7f ldr r3, [pc, #508] @ (800e180 ) 800df82: 681b ldr r3, [r3, #0] 800df84: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800df88: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800df8c: d107 bne.n 800df9e { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800df8e: f107 0324 add.w r3, r7, #36 @ 0x24 800df92: 4618 mov r0, r3 800df94: f000 fd5e bl 800ea54 frequency = pll1_clocks.PLL1_Q_Frequency; 800df98: 6abb ldr r3, [r7, #40] @ 0x28 800df9a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800df9c: e293 b.n 800e4c6 frequency = 0; 800df9e: 2300 movs r3, #0 800dfa0: 63fb str r3, [r7, #60] @ 0x3c break; 800dfa2: e290 b.n 800e4c6 } case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800dfa4: 4b76 ldr r3, [pc, #472] @ (800e180 ) 800dfa6: 681b ldr r3, [r3, #0] 800dfa8: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800dfac: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800dfb0: d107 bne.n 800dfc2 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800dfb2: f107 0318 add.w r3, r7, #24 800dfb6: 4618 mov r0, r3 800dfb8: f000 faa4 bl 800e504 frequency = pll2_clocks.PLL2_P_Frequency; 800dfbc: 69bb ldr r3, [r7, #24] 800dfbe: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dfc0: e281 b.n 800e4c6 frequency = 0; 800dfc2: 2300 movs r3, #0 800dfc4: 63fb str r3, [r7, #60] @ 0x3c break; 800dfc6: e27e b.n 800e4c6 } case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800dfc8: 4b6d ldr r3, [pc, #436] @ (800e180 ) 800dfca: 681b ldr r3, [r3, #0] 800dfcc: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800dfd0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800dfd4: d107 bne.n 800dfe6 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800dfd6: f107 030c add.w r3, r7, #12 800dfda: 4618 mov r0, r3 800dfdc: f000 fbe6 bl 800e7ac frequency = pll3_clocks.PLL3_P_Frequency; 800dfe0: 68fb ldr r3, [r7, #12] 800dfe2: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dfe4: e26f b.n 800e4c6 frequency = 0; 800dfe6: 2300 movs r3, #0 800dfe8: 63fb str r3, [r7, #60] @ 0x3c break; 800dfea: e26c b.n 800e4c6 } case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800dfec: 4b64 ldr r3, [pc, #400] @ (800e180 ) 800dfee: 6cdb ldr r3, [r3, #76] @ 0x4c 800dff0: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800dff4: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800dff6: 4b62 ldr r3, [pc, #392] @ (800e180 ) 800dff8: 681b ldr r3, [r3, #0] 800dffa: f003 0304 and.w r3, r3, #4 800dffe: 2b04 cmp r3, #4 800e000: d10c bne.n 800e01c 800e002: 6b7b ldr r3, [r7, #52] @ 0x34 800e004: 2b00 cmp r3, #0 800e006: d109 bne.n 800e01c { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e008: 4b5d ldr r3, [pc, #372] @ (800e180 ) 800e00a: 681b ldr r3, [r3, #0] 800e00c: 08db lsrs r3, r3, #3 800e00e: f003 0303 and.w r3, r3, #3 800e012: 4a5c ldr r2, [pc, #368] @ (800e184 ) 800e014: fa22 f303 lsr.w r3, r2, r3 800e018: 63fb str r3, [r7, #60] @ 0x3c 800e01a: e01e b.n 800e05a } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e01c: 4b58 ldr r3, [pc, #352] @ (800e180 ) 800e01e: 681b ldr r3, [r3, #0] 800e020: f403 7380 and.w r3, r3, #256 @ 0x100 800e024: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e028: d106 bne.n 800e038 800e02a: 6b7b ldr r3, [r7, #52] @ 0x34 800e02c: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e030: d102 bne.n 800e038 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e032: 4b55 ldr r3, [pc, #340] @ (800e188 ) 800e034: 63fb str r3, [r7, #60] @ 0x3c 800e036: e010 b.n 800e05a } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e038: 4b51 ldr r3, [pc, #324] @ (800e180 ) 800e03a: 681b ldr r3, [r3, #0] 800e03c: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e040: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e044: d106 bne.n 800e054 800e046: 6b7b ldr r3, [r7, #52] @ 0x34 800e048: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e04c: d102 bne.n 800e054 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e04e: 4b4f ldr r3, [pc, #316] @ (800e18c ) 800e050: 63fb str r3, [r7, #60] @ 0x3c 800e052: e002 b.n 800e05a } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e054: 2300 movs r3, #0 800e056: 63fb str r3, [r7, #60] @ 0x3c } break; 800e058: e235 b.n 800e4c6 800e05a: e234 b.n 800e4c6 } case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ { frequency = EXTERNAL_CLOCK_VALUE; 800e05c: 4b4c ldr r3, [pc, #304] @ (800e190 ) 800e05e: 63fb str r3, [r7, #60] @ 0x3c break; 800e060: e231 b.n 800e4c6 } default : { frequency = 0; 800e062: 2300 movs r3, #0 800e064: 63fb str r3, [r7, #60] @ 0x3c break; 800e066: e22e b.n 800e4c6 } } } else if (PeriphClk == RCC_PERIPHCLK_SPI45) 800e068: e9d7 2300 ldrd r2, r3, [r7] 800e06c: f5a2 5100 sub.w r1, r2, #8192 @ 0x2000 800e070: 430b orrs r3, r1 800e072: f040 808f bne.w 800e194 { /* Get SPI45 clock source */ srcclk = __HAL_RCC_GET_SPI45_SOURCE(); 800e076: 4b42 ldr r3, [pc, #264] @ (800e180 ) 800e078: 6d1b ldr r3, [r3, #80] @ 0x50 800e07a: f403 23e0 and.w r3, r3, #458752 @ 0x70000 800e07e: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e080: 6bbb ldr r3, [r7, #56] @ 0x38 800e082: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800e086: d06b beq.n 800e160 800e088: 6bbb ldr r3, [r7, #56] @ 0x38 800e08a: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800e08e: d874 bhi.n 800e17a 800e090: 6bbb ldr r3, [r7, #56] @ 0x38 800e092: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800e096: d056 beq.n 800e146 800e098: 6bbb ldr r3, [r7, #56] @ 0x38 800e09a: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800e09e: d86c bhi.n 800e17a 800e0a0: 6bbb ldr r3, [r7, #56] @ 0x38 800e0a2: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800e0a6: d03b beq.n 800e120 800e0a8: 6bbb ldr r3, [r7, #56] @ 0x38 800e0aa: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800e0ae: d864 bhi.n 800e17a 800e0b0: 6bbb ldr r3, [r7, #56] @ 0x38 800e0b2: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e0b6: d021 beq.n 800e0fc 800e0b8: 6bbb ldr r3, [r7, #56] @ 0x38 800e0ba: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e0be: d85c bhi.n 800e17a 800e0c0: 6bbb ldr r3, [r7, #56] @ 0x38 800e0c2: 2b00 cmp r3, #0 800e0c4: d004 beq.n 800e0d0 800e0c6: 6bbb ldr r3, [r7, #56] @ 0x38 800e0c8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e0cc: d004 beq.n 800e0d8 800e0ce: e054 b.n 800e17a { case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */ { frequency = HAL_RCC_GetPCLK1Freq(); 800e0d0: f7fe fa26 bl 800c520 800e0d4: 63f8 str r0, [r7, #60] @ 0x3c break; 800e0d6: e1f6 b.n 800e4c6 } case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e0d8: 4b29 ldr r3, [pc, #164] @ (800e180 ) 800e0da: 681b ldr r3, [r3, #0] 800e0dc: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e0e0: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e0e4: d107 bne.n 800e0f6 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e0e6: f107 0318 add.w r3, r7, #24 800e0ea: 4618 mov r0, r3 800e0ec: f000 fa0a bl 800e504 frequency = pll2_clocks.PLL2_Q_Frequency; 800e0f0: 69fb ldr r3, [r7, #28] 800e0f2: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e0f4: e1e7 b.n 800e4c6 frequency = 0; 800e0f6: 2300 movs r3, #0 800e0f8: 63fb str r3, [r7, #60] @ 0x3c break; 800e0fa: e1e4 b.n 800e4c6 } case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e0fc: 4b20 ldr r3, [pc, #128] @ (800e180 ) 800e0fe: 681b ldr r3, [r3, #0] 800e100: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e104: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e108: d107 bne.n 800e11a { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e10a: f107 030c add.w r3, r7, #12 800e10e: 4618 mov r0, r3 800e110: f000 fb4c bl 800e7ac frequency = pll3_clocks.PLL3_Q_Frequency; 800e114: 693b ldr r3, [r7, #16] 800e116: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e118: e1d5 b.n 800e4c6 frequency = 0; 800e11a: 2300 movs r3, #0 800e11c: 63fb str r3, [r7, #60] @ 0x3c break; 800e11e: e1d2 b.n 800e4c6 } case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800e120: 4b17 ldr r3, [pc, #92] @ (800e180 ) 800e122: 681b ldr r3, [r3, #0] 800e124: f003 0304 and.w r3, r3, #4 800e128: 2b04 cmp r3, #4 800e12a: d109 bne.n 800e140 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e12c: 4b14 ldr r3, [pc, #80] @ (800e180 ) 800e12e: 681b ldr r3, [r3, #0] 800e130: 08db lsrs r3, r3, #3 800e132: f003 0303 and.w r3, r3, #3 800e136: 4a13 ldr r2, [pc, #76] @ (800e184 ) 800e138: fa22 f303 lsr.w r3, r2, r3 800e13c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e13e: e1c2 b.n 800e4c6 frequency = 0; 800e140: 2300 movs r3, #0 800e142: 63fb str r3, [r7, #60] @ 0x3c break; 800e144: e1bf b.n 800e4c6 } case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 800e146: 4b0e ldr r3, [pc, #56] @ (800e180 ) 800e148: 681b ldr r3, [r3, #0] 800e14a: f403 7380 and.w r3, r3, #256 @ 0x100 800e14e: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e152: d102 bne.n 800e15a { frequency = CSI_VALUE; 800e154: 4b0c ldr r3, [pc, #48] @ (800e188 ) 800e156: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e158: e1b5 b.n 800e4c6 frequency = 0; 800e15a: 2300 movs r3, #0 800e15c: 63fb str r3, [r7, #60] @ 0x3c break; 800e15e: e1b2 b.n 800e4c6 } case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e160: 4b07 ldr r3, [pc, #28] @ (800e180 ) 800e162: 681b ldr r3, [r3, #0] 800e164: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e168: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e16c: d102 bne.n 800e174 { frequency = HSE_VALUE; 800e16e: 4b07 ldr r3, [pc, #28] @ (800e18c ) 800e170: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e172: e1a8 b.n 800e4c6 frequency = 0; 800e174: 2300 movs r3, #0 800e176: 63fb str r3, [r7, #60] @ 0x3c break; 800e178: e1a5 b.n 800e4c6 } default : { frequency = 0; 800e17a: 2300 movs r3, #0 800e17c: 63fb str r3, [r7, #60] @ 0x3c break; 800e17e: e1a2 b.n 800e4c6 800e180: 58024400 .word 0x58024400 800e184: 03d09000 .word 0x03d09000 800e188: 003d0900 .word 0x003d0900 800e18c: 017d7840 .word 0x017d7840 800e190: 00bb8000 .word 0x00bb8000 } } } else if (PeriphClk == RCC_PERIPHCLK_ADC) 800e194: e9d7 2300 ldrd r2, r3, [r7] 800e198: f5a2 2100 sub.w r1, r2, #524288 @ 0x80000 800e19c: 430b orrs r3, r1 800e19e: d173 bne.n 800e288 { /* Get ADC clock source */ srcclk = __HAL_RCC_GET_ADC_SOURCE(); 800e1a0: 4b9c ldr r3, [pc, #624] @ (800e414 ) 800e1a2: 6d9b ldr r3, [r3, #88] @ 0x58 800e1a4: f403 3340 and.w r3, r3, #196608 @ 0x30000 800e1a8: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e1aa: 6bbb ldr r3, [r7, #56] @ 0x38 800e1ac: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e1b0: d02f beq.n 800e212 800e1b2: 6bbb ldr r3, [r7, #56] @ 0x38 800e1b4: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e1b8: d863 bhi.n 800e282 800e1ba: 6bbb ldr r3, [r7, #56] @ 0x38 800e1bc: 2b00 cmp r3, #0 800e1be: d004 beq.n 800e1ca 800e1c0: 6bbb ldr r3, [r7, #56] @ 0x38 800e1c2: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e1c6: d012 beq.n 800e1ee 800e1c8: e05b b.n 800e282 { case RCC_ADCCLKSOURCE_PLL2: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e1ca: 4b92 ldr r3, [pc, #584] @ (800e414 ) 800e1cc: 681b ldr r3, [r3, #0] 800e1ce: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e1d2: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e1d6: d107 bne.n 800e1e8 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e1d8: f107 0318 add.w r3, r7, #24 800e1dc: 4618 mov r0, r3 800e1de: f000 f991 bl 800e504 frequency = pll2_clocks.PLL2_P_Frequency; 800e1e2: 69bb ldr r3, [r7, #24] 800e1e4: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e1e6: e16e b.n 800e4c6 frequency = 0; 800e1e8: 2300 movs r3, #0 800e1ea: 63fb str r3, [r7, #60] @ 0x3c break; 800e1ec: e16b b.n 800e4c6 } case RCC_ADCCLKSOURCE_PLL3: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e1ee: 4b89 ldr r3, [pc, #548] @ (800e414 ) 800e1f0: 681b ldr r3, [r3, #0] 800e1f2: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e1f6: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e1fa: d107 bne.n 800e20c { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e1fc: f107 030c add.w r3, r7, #12 800e200: 4618 mov r0, r3 800e202: f000 fad3 bl 800e7ac frequency = pll3_clocks.PLL3_R_Frequency; 800e206: 697b ldr r3, [r7, #20] 800e208: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e20a: e15c b.n 800e4c6 frequency = 0; 800e20c: 2300 movs r3, #0 800e20e: 63fb str r3, [r7, #60] @ 0x3c break; 800e210: e159 b.n 800e4c6 } case RCC_ADCCLKSOURCE_CLKP: { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e212: 4b80 ldr r3, [pc, #512] @ (800e414 ) 800e214: 6cdb ldr r3, [r3, #76] @ 0x4c 800e216: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e21a: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e21c: 4b7d ldr r3, [pc, #500] @ (800e414 ) 800e21e: 681b ldr r3, [r3, #0] 800e220: f003 0304 and.w r3, r3, #4 800e224: 2b04 cmp r3, #4 800e226: d10c bne.n 800e242 800e228: 6b7b ldr r3, [r7, #52] @ 0x34 800e22a: 2b00 cmp r3, #0 800e22c: d109 bne.n 800e242 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e22e: 4b79 ldr r3, [pc, #484] @ (800e414 ) 800e230: 681b ldr r3, [r3, #0] 800e232: 08db lsrs r3, r3, #3 800e234: f003 0303 and.w r3, r3, #3 800e238: 4a77 ldr r2, [pc, #476] @ (800e418 ) 800e23a: fa22 f303 lsr.w r3, r2, r3 800e23e: 63fb str r3, [r7, #60] @ 0x3c 800e240: e01e b.n 800e280 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e242: 4b74 ldr r3, [pc, #464] @ (800e414 ) 800e244: 681b ldr r3, [r3, #0] 800e246: f403 7380 and.w r3, r3, #256 @ 0x100 800e24a: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e24e: d106 bne.n 800e25e 800e250: 6b7b ldr r3, [r7, #52] @ 0x34 800e252: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e256: d102 bne.n 800e25e { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e258: 4b70 ldr r3, [pc, #448] @ (800e41c ) 800e25a: 63fb str r3, [r7, #60] @ 0x3c 800e25c: e010 b.n 800e280 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e25e: 4b6d ldr r3, [pc, #436] @ (800e414 ) 800e260: 681b ldr r3, [r3, #0] 800e262: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e266: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e26a: d106 bne.n 800e27a 800e26c: 6b7b ldr r3, [r7, #52] @ 0x34 800e26e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e272: d102 bne.n 800e27a { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e274: 4b6a ldr r3, [pc, #424] @ (800e420 ) 800e276: 63fb str r3, [r7, #60] @ 0x3c 800e278: e002 b.n 800e280 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e27a: 2300 movs r3, #0 800e27c: 63fb str r3, [r7, #60] @ 0x3c } break; 800e27e: e122 b.n 800e4c6 800e280: e121 b.n 800e4c6 } default : { frequency = 0; 800e282: 2300 movs r3, #0 800e284: 63fb str r3, [r7, #60] @ 0x3c break; 800e286: e11e b.n 800e4c6 } } } else if (PeriphClk == RCC_PERIPHCLK_SDMMC) 800e288: e9d7 2300 ldrd r2, r3, [r7] 800e28c: f5a2 3180 sub.w r1, r2, #65536 @ 0x10000 800e290: 430b orrs r3, r1 800e292: d133 bne.n 800e2fc { /* Get SDMMC clock source */ srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); 800e294: 4b5f ldr r3, [pc, #380] @ (800e414 ) 800e296: 6cdb ldr r3, [r3, #76] @ 0x4c 800e298: f403 3380 and.w r3, r3, #65536 @ 0x10000 800e29c: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e29e: 6bbb ldr r3, [r7, #56] @ 0x38 800e2a0: 2b00 cmp r3, #0 800e2a2: d004 beq.n 800e2ae 800e2a4: 6bbb ldr r3, [r7, #56] @ 0x38 800e2a6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e2aa: d012 beq.n 800e2d2 800e2ac: e023 b.n 800e2f6 { case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e2ae: 4b59 ldr r3, [pc, #356] @ (800e414 ) 800e2b0: 681b ldr r3, [r3, #0] 800e2b2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e2b6: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e2ba: d107 bne.n 800e2cc { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e2bc: f107 0324 add.w r3, r7, #36 @ 0x24 800e2c0: 4618 mov r0, r3 800e2c2: f000 fbc7 bl 800ea54 frequency = pll1_clocks.PLL1_Q_Frequency; 800e2c6: 6abb ldr r3, [r7, #40] @ 0x28 800e2c8: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e2ca: e0fc b.n 800e4c6 frequency = 0; 800e2cc: 2300 movs r3, #0 800e2ce: 63fb str r3, [r7, #60] @ 0x3c break; 800e2d0: e0f9 b.n 800e4c6 } case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e2d2: 4b50 ldr r3, [pc, #320] @ (800e414 ) 800e2d4: 681b ldr r3, [r3, #0] 800e2d6: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e2da: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e2de: d107 bne.n 800e2f0 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e2e0: f107 0318 add.w r3, r7, #24 800e2e4: 4618 mov r0, r3 800e2e6: f000 f90d bl 800e504 frequency = pll2_clocks.PLL2_R_Frequency; 800e2ea: 6a3b ldr r3, [r7, #32] 800e2ec: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e2ee: e0ea b.n 800e4c6 frequency = 0; 800e2f0: 2300 movs r3, #0 800e2f2: 63fb str r3, [r7, #60] @ 0x3c break; 800e2f4: e0e7 b.n 800e4c6 } default : { frequency = 0; 800e2f6: 2300 movs r3, #0 800e2f8: 63fb str r3, [r7, #60] @ 0x3c break; 800e2fa: e0e4 b.n 800e4c6 } } } else if (PeriphClk == RCC_PERIPHCLK_SPI6) 800e2fc: e9d7 2300 ldrd r2, r3, [r7] 800e300: f5a2 4180 sub.w r1, r2, #16384 @ 0x4000 800e304: 430b orrs r3, r1 800e306: f040 808d bne.w 800e424 { /* Get SPI6 clock source */ srcclk = __HAL_RCC_GET_SPI6_SOURCE(); 800e30a: 4b42 ldr r3, [pc, #264] @ (800e414 ) 800e30c: 6d9b ldr r3, [r3, #88] @ 0x58 800e30e: f003 43e0 and.w r3, r3, #1879048192 @ 0x70000000 800e312: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e314: 6bbb ldr r3, [r7, #56] @ 0x38 800e316: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800e31a: d06b beq.n 800e3f4 800e31c: 6bbb ldr r3, [r7, #56] @ 0x38 800e31e: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800e322: d874 bhi.n 800e40e 800e324: 6bbb ldr r3, [r7, #56] @ 0x38 800e326: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800e32a: d056 beq.n 800e3da 800e32c: 6bbb ldr r3, [r7, #56] @ 0x38 800e32e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800e332: d86c bhi.n 800e40e 800e334: 6bbb ldr r3, [r7, #56] @ 0x38 800e336: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800e33a: d03b beq.n 800e3b4 800e33c: 6bbb ldr r3, [r7, #56] @ 0x38 800e33e: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800e342: d864 bhi.n 800e40e 800e344: 6bbb ldr r3, [r7, #56] @ 0x38 800e346: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e34a: d021 beq.n 800e390 800e34c: 6bbb ldr r3, [r7, #56] @ 0x38 800e34e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e352: d85c bhi.n 800e40e 800e354: 6bbb ldr r3, [r7, #56] @ 0x38 800e356: 2b00 cmp r3, #0 800e358: d004 beq.n 800e364 800e35a: 6bbb ldr r3, [r7, #56] @ 0x38 800e35c: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e360: d004 beq.n 800e36c 800e362: e054 b.n 800e40e { case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ { frequency = HAL_RCCEx_GetD3PCLK1Freq(); 800e364: f000 f8b8 bl 800e4d8 800e368: 63f8 str r0, [r7, #60] @ 0x3c break; 800e36a: e0ac b.n 800e4c6 } case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e36c: 4b29 ldr r3, [pc, #164] @ (800e414 ) 800e36e: 681b ldr r3, [r3, #0] 800e370: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e374: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e378: d107 bne.n 800e38a { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e37a: f107 0318 add.w r3, r7, #24 800e37e: 4618 mov r0, r3 800e380: f000 f8c0 bl 800e504 frequency = pll2_clocks.PLL2_Q_Frequency; 800e384: 69fb ldr r3, [r7, #28] 800e386: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e388: e09d b.n 800e4c6 frequency = 0; 800e38a: 2300 movs r3, #0 800e38c: 63fb str r3, [r7, #60] @ 0x3c break; 800e38e: e09a b.n 800e4c6 } case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e390: 4b20 ldr r3, [pc, #128] @ (800e414 ) 800e392: 681b ldr r3, [r3, #0] 800e394: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e398: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e39c: d107 bne.n 800e3ae { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e39e: f107 030c add.w r3, r7, #12 800e3a2: 4618 mov r0, r3 800e3a4: f000 fa02 bl 800e7ac frequency = pll3_clocks.PLL3_Q_Frequency; 800e3a8: 693b ldr r3, [r7, #16] 800e3aa: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e3ac: e08b b.n 800e4c6 frequency = 0; 800e3ae: 2300 movs r3, #0 800e3b0: 63fb str r3, [r7, #60] @ 0x3c break; 800e3b2: e088 b.n 800e4c6 } case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800e3b4: 4b17 ldr r3, [pc, #92] @ (800e414 ) 800e3b6: 681b ldr r3, [r3, #0] 800e3b8: f003 0304 and.w r3, r3, #4 800e3bc: 2b04 cmp r3, #4 800e3be: d109 bne.n 800e3d4 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e3c0: 4b14 ldr r3, [pc, #80] @ (800e414 ) 800e3c2: 681b ldr r3, [r3, #0] 800e3c4: 08db lsrs r3, r3, #3 800e3c6: f003 0303 and.w r3, r3, #3 800e3ca: 4a13 ldr r2, [pc, #76] @ (800e418 ) 800e3cc: fa22 f303 lsr.w r3, r2, r3 800e3d0: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e3d2: e078 b.n 800e4c6 frequency = 0; 800e3d4: 2300 movs r3, #0 800e3d6: 63fb str r3, [r7, #60] @ 0x3c break; 800e3d8: e075 b.n 800e4c6 } case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 800e3da: 4b0e ldr r3, [pc, #56] @ (800e414 ) 800e3dc: 681b ldr r3, [r3, #0] 800e3de: f403 7380 and.w r3, r3, #256 @ 0x100 800e3e2: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e3e6: d102 bne.n 800e3ee { frequency = CSI_VALUE; 800e3e8: 4b0c ldr r3, [pc, #48] @ (800e41c ) 800e3ea: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e3ec: e06b b.n 800e4c6 frequency = 0; 800e3ee: 2300 movs r3, #0 800e3f0: 63fb str r3, [r7, #60] @ 0x3c break; 800e3f2: e068 b.n 800e4c6 } case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e3f4: 4b07 ldr r3, [pc, #28] @ (800e414 ) 800e3f6: 681b ldr r3, [r3, #0] 800e3f8: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e3fc: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e400: d102 bne.n 800e408 { frequency = HSE_VALUE; 800e402: 4b07 ldr r3, [pc, #28] @ (800e420 ) 800e404: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e406: e05e b.n 800e4c6 frequency = 0; 800e408: 2300 movs r3, #0 800e40a: 63fb str r3, [r7, #60] @ 0x3c break; 800e40c: e05b b.n 800e4c6 break; } #endif /* RCC_SPI6CLKSOURCE_PIN */ default : { frequency = 0; 800e40e: 2300 movs r3, #0 800e410: 63fb str r3, [r7, #60] @ 0x3c break; 800e412: e058 b.n 800e4c6 800e414: 58024400 .word 0x58024400 800e418: 03d09000 .word 0x03d09000 800e41c: 003d0900 .word 0x003d0900 800e420: 017d7840 .word 0x017d7840 } } } else if (PeriphClk == RCC_PERIPHCLK_FDCAN) 800e424: e9d7 2300 ldrd r2, r3, [r7] 800e428: f5a2 4100 sub.w r1, r2, #32768 @ 0x8000 800e42c: 430b orrs r3, r1 800e42e: d148 bne.n 800e4c2 { /* Get FDCAN clock source */ srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); 800e430: 4b27 ldr r3, [pc, #156] @ (800e4d0 ) 800e432: 6d1b ldr r3, [r3, #80] @ 0x50 800e434: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e438: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e43a: 6bbb ldr r3, [r7, #56] @ 0x38 800e43c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e440: d02a beq.n 800e498 800e442: 6bbb ldr r3, [r7, #56] @ 0x38 800e444: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e448: d838 bhi.n 800e4bc 800e44a: 6bbb ldr r3, [r7, #56] @ 0x38 800e44c: 2b00 cmp r3, #0 800e44e: d004 beq.n 800e45a 800e450: 6bbb ldr r3, [r7, #56] @ 0x38 800e452: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e456: d00d beq.n 800e474 800e458: e030 b.n 800e4bc { case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e45a: 4b1d ldr r3, [pc, #116] @ (800e4d0 ) 800e45c: 681b ldr r3, [r3, #0] 800e45e: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e462: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e466: d102 bne.n 800e46e { frequency = HSE_VALUE; 800e468: 4b1a ldr r3, [pc, #104] @ (800e4d4 ) 800e46a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e46c: e02b b.n 800e4c6 frequency = 0; 800e46e: 2300 movs r3, #0 800e470: 63fb str r3, [r7, #60] @ 0x3c break; 800e472: e028 b.n 800e4c6 } case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e474: 4b16 ldr r3, [pc, #88] @ (800e4d0 ) 800e476: 681b ldr r3, [r3, #0] 800e478: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e47c: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e480: d107 bne.n 800e492 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e482: f107 0324 add.w r3, r7, #36 @ 0x24 800e486: 4618 mov r0, r3 800e488: f000 fae4 bl 800ea54 frequency = pll1_clocks.PLL1_Q_Frequency; 800e48c: 6abb ldr r3, [r7, #40] @ 0x28 800e48e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e490: e019 b.n 800e4c6 frequency = 0; 800e492: 2300 movs r3, #0 800e494: 63fb str r3, [r7, #60] @ 0x3c break; 800e496: e016 b.n 800e4c6 } case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e498: 4b0d ldr r3, [pc, #52] @ (800e4d0 ) 800e49a: 681b ldr r3, [r3, #0] 800e49c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e4a0: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e4a4: d107 bne.n 800e4b6 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e4a6: f107 0318 add.w r3, r7, #24 800e4aa: 4618 mov r0, r3 800e4ac: f000 f82a bl 800e504 frequency = pll2_clocks.PLL2_Q_Frequency; 800e4b0: 69fb ldr r3, [r7, #28] 800e4b2: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e4b4: e007 b.n 800e4c6 frequency = 0; 800e4b6: 2300 movs r3, #0 800e4b8: 63fb str r3, [r7, #60] @ 0x3c break; 800e4ba: e004 b.n 800e4c6 } default : { frequency = 0; 800e4bc: 2300 movs r3, #0 800e4be: 63fb str r3, [r7, #60] @ 0x3c break; 800e4c0: e001 b.n 800e4c6 } } } else { frequency = 0; 800e4c2: 2300 movs r3, #0 800e4c4: 63fb str r3, [r7, #60] @ 0x3c } return frequency; 800e4c6: 6bfb ldr r3, [r7, #60] @ 0x3c } 800e4c8: 4618 mov r0, r3 800e4ca: 3740 adds r7, #64 @ 0x40 800e4cc: 46bd mov sp, r7 800e4ce: bd80 pop {r7, pc} 800e4d0: 58024400 .word 0x58024400 800e4d4: 017d7840 .word 0x017d7840 0800e4d8 : * @note Each time D3PCLK1 changes, this function must be called to update the * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval D3PCLK1 frequency */ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) { 800e4d8: b580 push {r7, lr} 800e4da: af00 add r7, sp, #0 #if defined(RCC_D3CFGR_D3PPRE) /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); 800e4dc: f7fd fff0 bl 800c4c0 800e4e0: 4602 mov r2, r0 800e4e2: 4b06 ldr r3, [pc, #24] @ (800e4fc ) 800e4e4: 6a1b ldr r3, [r3, #32] 800e4e6: 091b lsrs r3, r3, #4 800e4e8: f003 0307 and.w r3, r3, #7 800e4ec: 4904 ldr r1, [pc, #16] @ (800e500 ) 800e4ee: 5ccb ldrb r3, [r1, r3] 800e4f0: f003 031f and.w r3, r3, #31 800e4f4: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); #endif } 800e4f8: 4618 mov r0, r3 800e4fa: bd80 pop {r7, pc} 800e4fc: 58024400 .word 0x58024400 800e500: 0801a288 .word 0x0801a288 0800e504 : * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL2_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) { 800e504: b480 push {r7} 800e506: b089 sub sp, #36 @ 0x24 800e508: af00 add r7, sp, #0 800e50a: 6078 str r0, [r7, #4] float_t fracn2, pll2vco; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N PLL2xCLK = PLL2_VCO / PLL2x */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800e50c: 4ba1 ldr r3, [pc, #644] @ (800e794 ) 800e50e: 6a9b ldr r3, [r3, #40] @ 0x28 800e510: f003 0303 and.w r3, r3, #3 800e514: 61bb str r3, [r7, #24] pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); 800e516: 4b9f ldr r3, [pc, #636] @ (800e794 ) 800e518: 6a9b ldr r3, [r3, #40] @ 0x28 800e51a: 0b1b lsrs r3, r3, #12 800e51c: f003 033f and.w r3, r3, #63 @ 0x3f 800e520: 617b str r3, [r7, #20] pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; 800e522: 4b9c ldr r3, [pc, #624] @ (800e794 ) 800e524: 6adb ldr r3, [r3, #44] @ 0x2c 800e526: 091b lsrs r3, r3, #4 800e528: f003 0301 and.w r3, r3, #1 800e52c: 613b str r3, [r7, #16] fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); 800e52e: 4b99 ldr r3, [pc, #612] @ (800e794 ) 800e530: 6bdb ldr r3, [r3, #60] @ 0x3c 800e532: 08db lsrs r3, r3, #3 800e534: f3c3 030c ubfx r3, r3, #0, #13 800e538: 693a ldr r2, [r7, #16] 800e53a: fb02 f303 mul.w r3, r2, r3 800e53e: ee07 3a90 vmov s15, r3 800e542: eef8 7a67 vcvt.f32.u32 s15, s15 800e546: edc7 7a03 vstr s15, [r7, #12] if (pll2m != 0U) 800e54a: 697b ldr r3, [r7, #20] 800e54c: 2b00 cmp r3, #0 800e54e: f000 8111 beq.w 800e774 { switch (pllsource) 800e552: 69bb ldr r3, [r7, #24] 800e554: 2b02 cmp r3, #2 800e556: f000 8083 beq.w 800e660 800e55a: 69bb ldr r3, [r7, #24] 800e55c: 2b02 cmp r3, #2 800e55e: f200 80a1 bhi.w 800e6a4 800e562: 69bb ldr r3, [r7, #24] 800e564: 2b00 cmp r3, #0 800e566: d003 beq.n 800e570 800e568: 69bb ldr r3, [r7, #24] 800e56a: 2b01 cmp r3, #1 800e56c: d056 beq.n 800e61c 800e56e: e099 b.n 800e6a4 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800e570: 4b88 ldr r3, [pc, #544] @ (800e794 ) 800e572: 681b ldr r3, [r3, #0] 800e574: f003 0320 and.w r3, r3, #32 800e578: 2b00 cmp r3, #0 800e57a: d02d beq.n 800e5d8 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e57c: 4b85 ldr r3, [pc, #532] @ (800e794 ) 800e57e: 681b ldr r3, [r3, #0] 800e580: 08db lsrs r3, r3, #3 800e582: f003 0303 and.w r3, r3, #3 800e586: 4a84 ldr r2, [pc, #528] @ (800e798 ) 800e588: fa22 f303 lsr.w r3, r2, r3 800e58c: 60bb str r3, [r7, #8] pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e58e: 68bb ldr r3, [r7, #8] 800e590: ee07 3a90 vmov s15, r3 800e594: eef8 6a67 vcvt.f32.u32 s13, s15 800e598: 697b ldr r3, [r7, #20] 800e59a: ee07 3a90 vmov s15, r3 800e59e: eef8 7a67 vcvt.f32.u32 s15, s15 800e5a2: ee86 7aa7 vdiv.f32 s14, s13, s15 800e5a6: 4b7b ldr r3, [pc, #492] @ (800e794 ) 800e5a8: 6b9b ldr r3, [r3, #56] @ 0x38 800e5aa: f3c3 0308 ubfx r3, r3, #0, #9 800e5ae: ee07 3a90 vmov s15, r3 800e5b2: eef8 6a67 vcvt.f32.u32 s13, s15 800e5b6: ed97 6a03 vldr s12, [r7, #12] 800e5ba: eddf 5a78 vldr s11, [pc, #480] @ 800e79c 800e5be: eec6 7a25 vdiv.f32 s15, s12, s11 800e5c2: ee76 7aa7 vadd.f32 s15, s13, s15 800e5c6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e5ca: ee77 7aa6 vadd.f32 s15, s15, s13 800e5ce: ee67 7a27 vmul.f32 s15, s14, s15 800e5d2: edc7 7a07 vstr s15, [r7, #28] } else { pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); } break; 800e5d6: e087 b.n 800e6e8 pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e5d8: 697b ldr r3, [r7, #20] 800e5da: ee07 3a90 vmov s15, r3 800e5de: eef8 7a67 vcvt.f32.u32 s15, s15 800e5e2: eddf 6a6f vldr s13, [pc, #444] @ 800e7a0 800e5e6: ee86 7aa7 vdiv.f32 s14, s13, s15 800e5ea: 4b6a ldr r3, [pc, #424] @ (800e794 ) 800e5ec: 6b9b ldr r3, [r3, #56] @ 0x38 800e5ee: f3c3 0308 ubfx r3, r3, #0, #9 800e5f2: ee07 3a90 vmov s15, r3 800e5f6: eef8 6a67 vcvt.f32.u32 s13, s15 800e5fa: ed97 6a03 vldr s12, [r7, #12] 800e5fe: eddf 5a67 vldr s11, [pc, #412] @ 800e79c 800e602: eec6 7a25 vdiv.f32 s15, s12, s11 800e606: ee76 7aa7 vadd.f32 s15, s13, s15 800e60a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e60e: ee77 7aa6 vadd.f32 s15, s15, s13 800e612: ee67 7a27 vmul.f32 s15, s14, s15 800e616: edc7 7a07 vstr s15, [r7, #28] break; 800e61a: e065 b.n 800e6e8 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e61c: 697b ldr r3, [r7, #20] 800e61e: ee07 3a90 vmov s15, r3 800e622: eef8 7a67 vcvt.f32.u32 s15, s15 800e626: eddf 6a5f vldr s13, [pc, #380] @ 800e7a4 800e62a: ee86 7aa7 vdiv.f32 s14, s13, s15 800e62e: 4b59 ldr r3, [pc, #356] @ (800e794 ) 800e630: 6b9b ldr r3, [r3, #56] @ 0x38 800e632: f3c3 0308 ubfx r3, r3, #0, #9 800e636: ee07 3a90 vmov s15, r3 800e63a: eef8 6a67 vcvt.f32.u32 s13, s15 800e63e: ed97 6a03 vldr s12, [r7, #12] 800e642: eddf 5a56 vldr s11, [pc, #344] @ 800e79c 800e646: eec6 7a25 vdiv.f32 s15, s12, s11 800e64a: ee76 7aa7 vadd.f32 s15, s13, s15 800e64e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e652: ee77 7aa6 vadd.f32 s15, s15, s13 800e656: ee67 7a27 vmul.f32 s15, s14, s15 800e65a: edc7 7a07 vstr s15, [r7, #28] break; 800e65e: e043 b.n 800e6e8 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e660: 697b ldr r3, [r7, #20] 800e662: ee07 3a90 vmov s15, r3 800e666: eef8 7a67 vcvt.f32.u32 s15, s15 800e66a: eddf 6a4f vldr s13, [pc, #316] @ 800e7a8 800e66e: ee86 7aa7 vdiv.f32 s14, s13, s15 800e672: 4b48 ldr r3, [pc, #288] @ (800e794 ) 800e674: 6b9b ldr r3, [r3, #56] @ 0x38 800e676: f3c3 0308 ubfx r3, r3, #0, #9 800e67a: ee07 3a90 vmov s15, r3 800e67e: eef8 6a67 vcvt.f32.u32 s13, s15 800e682: ed97 6a03 vldr s12, [r7, #12] 800e686: eddf 5a45 vldr s11, [pc, #276] @ 800e79c 800e68a: eec6 7a25 vdiv.f32 s15, s12, s11 800e68e: ee76 7aa7 vadd.f32 s15, s13, s15 800e692: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e696: ee77 7aa6 vadd.f32 s15, s15, s13 800e69a: ee67 7a27 vmul.f32 s15, s14, s15 800e69e: edc7 7a07 vstr s15, [r7, #28] break; 800e6a2: e021 b.n 800e6e8 default: pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e6a4: 697b ldr r3, [r7, #20] 800e6a6: ee07 3a90 vmov s15, r3 800e6aa: eef8 7a67 vcvt.f32.u32 s15, s15 800e6ae: eddf 6a3d vldr s13, [pc, #244] @ 800e7a4 800e6b2: ee86 7aa7 vdiv.f32 s14, s13, s15 800e6b6: 4b37 ldr r3, [pc, #220] @ (800e794 ) 800e6b8: 6b9b ldr r3, [r3, #56] @ 0x38 800e6ba: f3c3 0308 ubfx r3, r3, #0, #9 800e6be: ee07 3a90 vmov s15, r3 800e6c2: eef8 6a67 vcvt.f32.u32 s13, s15 800e6c6: ed97 6a03 vldr s12, [r7, #12] 800e6ca: eddf 5a34 vldr s11, [pc, #208] @ 800e79c 800e6ce: eec6 7a25 vdiv.f32 s15, s12, s11 800e6d2: ee76 7aa7 vadd.f32 s15, s13, s15 800e6d6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e6da: ee77 7aa6 vadd.f32 s15, s15, s13 800e6de: ee67 7a27 vmul.f32 s15, s14, s15 800e6e2: edc7 7a07 vstr s15, [r7, #28] break; 800e6e6: bf00 nop } PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; 800e6e8: 4b2a ldr r3, [pc, #168] @ (800e794 ) 800e6ea: 6b9b ldr r3, [r3, #56] @ 0x38 800e6ec: 0a5b lsrs r3, r3, #9 800e6ee: f003 037f and.w r3, r3, #127 @ 0x7f 800e6f2: ee07 3a90 vmov s15, r3 800e6f6: eef8 7a67 vcvt.f32.u32 s15, s15 800e6fa: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800e6fe: ee37 7a87 vadd.f32 s14, s15, s14 800e702: edd7 6a07 vldr s13, [r7, #28] 800e706: eec6 7a87 vdiv.f32 s15, s13, s14 800e70a: eefc 7ae7 vcvt.u32.f32 s15, s15 800e70e: ee17 2a90 vmov r2, s15 800e712: 687b ldr r3, [r7, #4] 800e714: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; 800e716: 4b1f ldr r3, [pc, #124] @ (800e794 ) 800e718: 6b9b ldr r3, [r3, #56] @ 0x38 800e71a: 0c1b lsrs r3, r3, #16 800e71c: f003 037f and.w r3, r3, #127 @ 0x7f 800e720: ee07 3a90 vmov s15, r3 800e724: eef8 7a67 vcvt.f32.u32 s15, s15 800e728: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800e72c: ee37 7a87 vadd.f32 s14, s15, s14 800e730: edd7 6a07 vldr s13, [r7, #28] 800e734: eec6 7a87 vdiv.f32 s15, s13, s14 800e738: eefc 7ae7 vcvt.u32.f32 s15, s15 800e73c: ee17 2a90 vmov r2, s15 800e740: 687b ldr r3, [r7, #4] 800e742: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; 800e744: 4b13 ldr r3, [pc, #76] @ (800e794 ) 800e746: 6b9b ldr r3, [r3, #56] @ 0x38 800e748: 0e1b lsrs r3, r3, #24 800e74a: f003 037f and.w r3, r3, #127 @ 0x7f 800e74e: ee07 3a90 vmov s15, r3 800e752: eef8 7a67 vcvt.f32.u32 s15, s15 800e756: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800e75a: ee37 7a87 vadd.f32 s14, s15, s14 800e75e: edd7 6a07 vldr s13, [r7, #28] 800e762: eec6 7a87 vdiv.f32 s15, s13, s14 800e766: eefc 7ae7 vcvt.u32.f32 s15, s15 800e76a: ee17 2a90 vmov r2, s15 800e76e: 687b ldr r3, [r7, #4] 800e770: 609a str r2, [r3, #8] { PLL2_Clocks->PLL2_P_Frequency = 0U; PLL2_Clocks->PLL2_Q_Frequency = 0U; PLL2_Clocks->PLL2_R_Frequency = 0U; } } 800e772: e008 b.n 800e786 PLL2_Clocks->PLL2_P_Frequency = 0U; 800e774: 687b ldr r3, [r7, #4] 800e776: 2200 movs r2, #0 800e778: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = 0U; 800e77a: 687b ldr r3, [r7, #4] 800e77c: 2200 movs r2, #0 800e77e: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = 0U; 800e780: 687b ldr r3, [r7, #4] 800e782: 2200 movs r2, #0 800e784: 609a str r2, [r3, #8] } 800e786: bf00 nop 800e788: 3724 adds r7, #36 @ 0x24 800e78a: 46bd mov sp, r7 800e78c: f85d 7b04 ldr.w r7, [sp], #4 800e790: 4770 bx lr 800e792: bf00 nop 800e794: 58024400 .word 0x58024400 800e798: 03d09000 .word 0x03d09000 800e79c: 46000000 .word 0x46000000 800e7a0: 4c742400 .word 0x4c742400 800e7a4: 4a742400 .word 0x4a742400 800e7a8: 4bbebc20 .word 0x4bbebc20 0800e7ac : * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL3_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) { 800e7ac: b480 push {r7} 800e7ae: b089 sub sp, #36 @ 0x24 800e7b0: af00 add r7, sp, #0 800e7b2: 6078 str r0, [r7, #4] float_t fracn3, pll3vco; /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N PLL3xCLK = PLL3_VCO / PLLxR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800e7b4: 4ba1 ldr r3, [pc, #644] @ (800ea3c ) 800e7b6: 6a9b ldr r3, [r3, #40] @ 0x28 800e7b8: f003 0303 and.w r3, r3, #3 800e7bc: 61bb str r3, [r7, #24] pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; 800e7be: 4b9f ldr r3, [pc, #636] @ (800ea3c ) 800e7c0: 6a9b ldr r3, [r3, #40] @ 0x28 800e7c2: 0d1b lsrs r3, r3, #20 800e7c4: f003 033f and.w r3, r3, #63 @ 0x3f 800e7c8: 617b str r3, [r7, #20] pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; 800e7ca: 4b9c ldr r3, [pc, #624] @ (800ea3c ) 800e7cc: 6adb ldr r3, [r3, #44] @ 0x2c 800e7ce: 0a1b lsrs r3, r3, #8 800e7d0: f003 0301 and.w r3, r3, #1 800e7d4: 613b str r3, [r7, #16] fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); 800e7d6: 4b99 ldr r3, [pc, #612] @ (800ea3c ) 800e7d8: 6c5b ldr r3, [r3, #68] @ 0x44 800e7da: 08db lsrs r3, r3, #3 800e7dc: f3c3 030c ubfx r3, r3, #0, #13 800e7e0: 693a ldr r2, [r7, #16] 800e7e2: fb02 f303 mul.w r3, r2, r3 800e7e6: ee07 3a90 vmov s15, r3 800e7ea: eef8 7a67 vcvt.f32.u32 s15, s15 800e7ee: edc7 7a03 vstr s15, [r7, #12] if (pll3m != 0U) 800e7f2: 697b ldr r3, [r7, #20] 800e7f4: 2b00 cmp r3, #0 800e7f6: f000 8111 beq.w 800ea1c { switch (pllsource) 800e7fa: 69bb ldr r3, [r7, #24] 800e7fc: 2b02 cmp r3, #2 800e7fe: f000 8083 beq.w 800e908 800e802: 69bb ldr r3, [r7, #24] 800e804: 2b02 cmp r3, #2 800e806: f200 80a1 bhi.w 800e94c 800e80a: 69bb ldr r3, [r7, #24] 800e80c: 2b00 cmp r3, #0 800e80e: d003 beq.n 800e818 800e810: 69bb ldr r3, [r7, #24] 800e812: 2b01 cmp r3, #1 800e814: d056 beq.n 800e8c4 800e816: e099 b.n 800e94c { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800e818: 4b88 ldr r3, [pc, #544] @ (800ea3c ) 800e81a: 681b ldr r3, [r3, #0] 800e81c: f003 0320 and.w r3, r3, #32 800e820: 2b00 cmp r3, #0 800e822: d02d beq.n 800e880 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e824: 4b85 ldr r3, [pc, #532] @ (800ea3c ) 800e826: 681b ldr r3, [r3, #0] 800e828: 08db lsrs r3, r3, #3 800e82a: f003 0303 and.w r3, r3, #3 800e82e: 4a84 ldr r2, [pc, #528] @ (800ea40 ) 800e830: fa22 f303 lsr.w r3, r2, r3 800e834: 60bb str r3, [r7, #8] pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800e836: 68bb ldr r3, [r7, #8] 800e838: ee07 3a90 vmov s15, r3 800e83c: eef8 6a67 vcvt.f32.u32 s13, s15 800e840: 697b ldr r3, [r7, #20] 800e842: ee07 3a90 vmov s15, r3 800e846: eef8 7a67 vcvt.f32.u32 s15, s15 800e84a: ee86 7aa7 vdiv.f32 s14, s13, s15 800e84e: 4b7b ldr r3, [pc, #492] @ (800ea3c ) 800e850: 6c1b ldr r3, [r3, #64] @ 0x40 800e852: f3c3 0308 ubfx r3, r3, #0, #9 800e856: ee07 3a90 vmov s15, r3 800e85a: eef8 6a67 vcvt.f32.u32 s13, s15 800e85e: ed97 6a03 vldr s12, [r7, #12] 800e862: eddf 5a78 vldr s11, [pc, #480] @ 800ea44 800e866: eec6 7a25 vdiv.f32 s15, s12, s11 800e86a: ee76 7aa7 vadd.f32 s15, s13, s15 800e86e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e872: ee77 7aa6 vadd.f32 s15, s15, s13 800e876: ee67 7a27 vmul.f32 s15, s14, s15 800e87a: edc7 7a07 vstr s15, [r7, #28] } else { pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); } break; 800e87e: e087 b.n 800e990 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800e880: 697b ldr r3, [r7, #20] 800e882: ee07 3a90 vmov s15, r3 800e886: eef8 7a67 vcvt.f32.u32 s15, s15 800e88a: eddf 6a6f vldr s13, [pc, #444] @ 800ea48 800e88e: ee86 7aa7 vdiv.f32 s14, s13, s15 800e892: 4b6a ldr r3, [pc, #424] @ (800ea3c ) 800e894: 6c1b ldr r3, [r3, #64] @ 0x40 800e896: f3c3 0308 ubfx r3, r3, #0, #9 800e89a: ee07 3a90 vmov s15, r3 800e89e: eef8 6a67 vcvt.f32.u32 s13, s15 800e8a2: ed97 6a03 vldr s12, [r7, #12] 800e8a6: eddf 5a67 vldr s11, [pc, #412] @ 800ea44 800e8aa: eec6 7a25 vdiv.f32 s15, s12, s11 800e8ae: ee76 7aa7 vadd.f32 s15, s13, s15 800e8b2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e8b6: ee77 7aa6 vadd.f32 s15, s15, s13 800e8ba: ee67 7a27 vmul.f32 s15, s14, s15 800e8be: edc7 7a07 vstr s15, [r7, #28] break; 800e8c2: e065 b.n 800e990 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800e8c4: 697b ldr r3, [r7, #20] 800e8c6: ee07 3a90 vmov s15, r3 800e8ca: eef8 7a67 vcvt.f32.u32 s15, s15 800e8ce: eddf 6a5f vldr s13, [pc, #380] @ 800ea4c 800e8d2: ee86 7aa7 vdiv.f32 s14, s13, s15 800e8d6: 4b59 ldr r3, [pc, #356] @ (800ea3c ) 800e8d8: 6c1b ldr r3, [r3, #64] @ 0x40 800e8da: f3c3 0308 ubfx r3, r3, #0, #9 800e8de: ee07 3a90 vmov s15, r3 800e8e2: eef8 6a67 vcvt.f32.u32 s13, s15 800e8e6: ed97 6a03 vldr s12, [r7, #12] 800e8ea: eddf 5a56 vldr s11, [pc, #344] @ 800ea44 800e8ee: eec6 7a25 vdiv.f32 s15, s12, s11 800e8f2: ee76 7aa7 vadd.f32 s15, s13, s15 800e8f6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e8fa: ee77 7aa6 vadd.f32 s15, s15, s13 800e8fe: ee67 7a27 vmul.f32 s15, s14, s15 800e902: edc7 7a07 vstr s15, [r7, #28] break; 800e906: e043 b.n 800e990 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800e908: 697b ldr r3, [r7, #20] 800e90a: ee07 3a90 vmov s15, r3 800e90e: eef8 7a67 vcvt.f32.u32 s15, s15 800e912: eddf 6a4f vldr s13, [pc, #316] @ 800ea50 800e916: ee86 7aa7 vdiv.f32 s14, s13, s15 800e91a: 4b48 ldr r3, [pc, #288] @ (800ea3c ) 800e91c: 6c1b ldr r3, [r3, #64] @ 0x40 800e91e: f3c3 0308 ubfx r3, r3, #0, #9 800e922: ee07 3a90 vmov s15, r3 800e926: eef8 6a67 vcvt.f32.u32 s13, s15 800e92a: ed97 6a03 vldr s12, [r7, #12] 800e92e: eddf 5a45 vldr s11, [pc, #276] @ 800ea44 800e932: eec6 7a25 vdiv.f32 s15, s12, s11 800e936: ee76 7aa7 vadd.f32 s15, s13, s15 800e93a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e93e: ee77 7aa6 vadd.f32 s15, s15, s13 800e942: ee67 7a27 vmul.f32 s15, s14, s15 800e946: edc7 7a07 vstr s15, [r7, #28] break; 800e94a: e021 b.n 800e990 default: pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800e94c: 697b ldr r3, [r7, #20] 800e94e: ee07 3a90 vmov s15, r3 800e952: eef8 7a67 vcvt.f32.u32 s15, s15 800e956: eddf 6a3d vldr s13, [pc, #244] @ 800ea4c 800e95a: ee86 7aa7 vdiv.f32 s14, s13, s15 800e95e: 4b37 ldr r3, [pc, #220] @ (800ea3c ) 800e960: 6c1b ldr r3, [r3, #64] @ 0x40 800e962: f3c3 0308 ubfx r3, r3, #0, #9 800e966: ee07 3a90 vmov s15, r3 800e96a: eef8 6a67 vcvt.f32.u32 s13, s15 800e96e: ed97 6a03 vldr s12, [r7, #12] 800e972: eddf 5a34 vldr s11, [pc, #208] @ 800ea44 800e976: eec6 7a25 vdiv.f32 s15, s12, s11 800e97a: ee76 7aa7 vadd.f32 s15, s13, s15 800e97e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e982: ee77 7aa6 vadd.f32 s15, s15, s13 800e986: ee67 7a27 vmul.f32 s15, s14, s15 800e98a: edc7 7a07 vstr s15, [r7, #28] break; 800e98e: bf00 nop } PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; 800e990: 4b2a ldr r3, [pc, #168] @ (800ea3c ) 800e992: 6c1b ldr r3, [r3, #64] @ 0x40 800e994: 0a5b lsrs r3, r3, #9 800e996: f003 037f and.w r3, r3, #127 @ 0x7f 800e99a: ee07 3a90 vmov s15, r3 800e99e: eef8 7a67 vcvt.f32.u32 s15, s15 800e9a2: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800e9a6: ee37 7a87 vadd.f32 s14, s15, s14 800e9aa: edd7 6a07 vldr s13, [r7, #28] 800e9ae: eec6 7a87 vdiv.f32 s15, s13, s14 800e9b2: eefc 7ae7 vcvt.u32.f32 s15, s15 800e9b6: ee17 2a90 vmov r2, s15 800e9ba: 687b ldr r3, [r7, #4] 800e9bc: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; 800e9be: 4b1f ldr r3, [pc, #124] @ (800ea3c ) 800e9c0: 6c1b ldr r3, [r3, #64] @ 0x40 800e9c2: 0c1b lsrs r3, r3, #16 800e9c4: f003 037f and.w r3, r3, #127 @ 0x7f 800e9c8: ee07 3a90 vmov s15, r3 800e9cc: eef8 7a67 vcvt.f32.u32 s15, s15 800e9d0: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800e9d4: ee37 7a87 vadd.f32 s14, s15, s14 800e9d8: edd7 6a07 vldr s13, [r7, #28] 800e9dc: eec6 7a87 vdiv.f32 s15, s13, s14 800e9e0: eefc 7ae7 vcvt.u32.f32 s15, s15 800e9e4: ee17 2a90 vmov r2, s15 800e9e8: 687b ldr r3, [r7, #4] 800e9ea: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; 800e9ec: 4b13 ldr r3, [pc, #76] @ (800ea3c ) 800e9ee: 6c1b ldr r3, [r3, #64] @ 0x40 800e9f0: 0e1b lsrs r3, r3, #24 800e9f2: f003 037f and.w r3, r3, #127 @ 0x7f 800e9f6: ee07 3a90 vmov s15, r3 800e9fa: eef8 7a67 vcvt.f32.u32 s15, s15 800e9fe: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ea02: ee37 7a87 vadd.f32 s14, s15, s14 800ea06: edd7 6a07 vldr s13, [r7, #28] 800ea0a: eec6 7a87 vdiv.f32 s15, s13, s14 800ea0e: eefc 7ae7 vcvt.u32.f32 s15, s15 800ea12: ee17 2a90 vmov r2, s15 800ea16: 687b ldr r3, [r7, #4] 800ea18: 609a str r2, [r3, #8] PLL3_Clocks->PLL3_P_Frequency = 0U; PLL3_Clocks->PLL3_Q_Frequency = 0U; PLL3_Clocks->PLL3_R_Frequency = 0U; } } 800ea1a: e008 b.n 800ea2e PLL3_Clocks->PLL3_P_Frequency = 0U; 800ea1c: 687b ldr r3, [r7, #4] 800ea1e: 2200 movs r2, #0 800ea20: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = 0U; 800ea22: 687b ldr r3, [r7, #4] 800ea24: 2200 movs r2, #0 800ea26: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = 0U; 800ea28: 687b ldr r3, [r7, #4] 800ea2a: 2200 movs r2, #0 800ea2c: 609a str r2, [r3, #8] } 800ea2e: bf00 nop 800ea30: 3724 adds r7, #36 @ 0x24 800ea32: 46bd mov sp, r7 800ea34: f85d 7b04 ldr.w r7, [sp], #4 800ea38: 4770 bx lr 800ea3a: bf00 nop 800ea3c: 58024400 .word 0x58024400 800ea40: 03d09000 .word 0x03d09000 800ea44: 46000000 .word 0x46000000 800ea48: 4c742400 .word 0x4c742400 800ea4c: 4a742400 .word 0x4a742400 800ea50: 4bbebc20 .word 0x4bbebc20 0800ea54 : * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL1_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) { 800ea54: b480 push {r7} 800ea56: b089 sub sp, #36 @ 0x24 800ea58: af00 add r7, sp, #0 800ea5a: 6078 str r0, [r7, #4] uint32_t pllsource, pll1m, pll1fracen, hsivalue; float_t fracn1, pll1vco; pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800ea5c: 4ba0 ldr r3, [pc, #640] @ (800ece0 ) 800ea5e: 6a9b ldr r3, [r3, #40] @ 0x28 800ea60: f003 0303 and.w r3, r3, #3 800ea64: 61bb str r3, [r7, #24] pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); 800ea66: 4b9e ldr r3, [pc, #632] @ (800ece0 ) 800ea68: 6a9b ldr r3, [r3, #40] @ 0x28 800ea6a: 091b lsrs r3, r3, #4 800ea6c: f003 033f and.w r3, r3, #63 @ 0x3f 800ea70: 617b str r3, [r7, #20] pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; 800ea72: 4b9b ldr r3, [pc, #620] @ (800ece0 ) 800ea74: 6adb ldr r3, [r3, #44] @ 0x2c 800ea76: f003 0301 and.w r3, r3, #1 800ea7a: 613b str r3, [r7, #16] fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800ea7c: 4b98 ldr r3, [pc, #608] @ (800ece0 ) 800ea7e: 6b5b ldr r3, [r3, #52] @ 0x34 800ea80: 08db lsrs r3, r3, #3 800ea82: f3c3 030c ubfx r3, r3, #0, #13 800ea86: 693a ldr r2, [r7, #16] 800ea88: fb02 f303 mul.w r3, r2, r3 800ea8c: ee07 3a90 vmov s15, r3 800ea90: eef8 7a67 vcvt.f32.u32 s15, s15 800ea94: edc7 7a03 vstr s15, [r7, #12] if (pll1m != 0U) 800ea98: 697b ldr r3, [r7, #20] 800ea9a: 2b00 cmp r3, #0 800ea9c: f000 8111 beq.w 800ecc2 { switch (pllsource) 800eaa0: 69bb ldr r3, [r7, #24] 800eaa2: 2b02 cmp r3, #2 800eaa4: f000 8083 beq.w 800ebae 800eaa8: 69bb ldr r3, [r7, #24] 800eaaa: 2b02 cmp r3, #2 800eaac: f200 80a1 bhi.w 800ebf2 800eab0: 69bb ldr r3, [r7, #24] 800eab2: 2b00 cmp r3, #0 800eab4: d003 beq.n 800eabe 800eab6: 69bb ldr r3, [r7, #24] 800eab8: 2b01 cmp r3, #1 800eaba: d056 beq.n 800eb6a 800eabc: e099 b.n 800ebf2 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800eabe: 4b88 ldr r3, [pc, #544] @ (800ece0 ) 800eac0: 681b ldr r3, [r3, #0] 800eac2: f003 0320 and.w r3, r3, #32 800eac6: 2b00 cmp r3, #0 800eac8: d02d beq.n 800eb26 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800eaca: 4b85 ldr r3, [pc, #532] @ (800ece0 ) 800eacc: 681b ldr r3, [r3, #0] 800eace: 08db lsrs r3, r3, #3 800ead0: f003 0303 and.w r3, r3, #3 800ead4: 4a83 ldr r2, [pc, #524] @ (800ece4 ) 800ead6: fa22 f303 lsr.w r3, r2, r3 800eada: 60bb str r3, [r7, #8] pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800eadc: 68bb ldr r3, [r7, #8] 800eade: ee07 3a90 vmov s15, r3 800eae2: eef8 6a67 vcvt.f32.u32 s13, s15 800eae6: 697b ldr r3, [r7, #20] 800eae8: ee07 3a90 vmov s15, r3 800eaec: eef8 7a67 vcvt.f32.u32 s15, s15 800eaf0: ee86 7aa7 vdiv.f32 s14, s13, s15 800eaf4: 4b7a ldr r3, [pc, #488] @ (800ece0 ) 800eaf6: 6b1b ldr r3, [r3, #48] @ 0x30 800eaf8: f3c3 0308 ubfx r3, r3, #0, #9 800eafc: ee07 3a90 vmov s15, r3 800eb00: eef8 6a67 vcvt.f32.u32 s13, s15 800eb04: ed97 6a03 vldr s12, [r7, #12] 800eb08: eddf 5a77 vldr s11, [pc, #476] @ 800ece8 800eb0c: eec6 7a25 vdiv.f32 s15, s12, s11 800eb10: ee76 7aa7 vadd.f32 s15, s13, s15 800eb14: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800eb18: ee77 7aa6 vadd.f32 s15, s15, s13 800eb1c: ee67 7a27 vmul.f32 s15, s14, s15 800eb20: edc7 7a07 vstr s15, [r7, #28] } else { pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 800eb24: e087 b.n 800ec36 pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800eb26: 697b ldr r3, [r7, #20] 800eb28: ee07 3a90 vmov s15, r3 800eb2c: eef8 7a67 vcvt.f32.u32 s15, s15 800eb30: eddf 6a6e vldr s13, [pc, #440] @ 800ecec 800eb34: ee86 7aa7 vdiv.f32 s14, s13, s15 800eb38: 4b69 ldr r3, [pc, #420] @ (800ece0 ) 800eb3a: 6b1b ldr r3, [r3, #48] @ 0x30 800eb3c: f3c3 0308 ubfx r3, r3, #0, #9 800eb40: ee07 3a90 vmov s15, r3 800eb44: eef8 6a67 vcvt.f32.u32 s13, s15 800eb48: ed97 6a03 vldr s12, [r7, #12] 800eb4c: eddf 5a66 vldr s11, [pc, #408] @ 800ece8 800eb50: eec6 7a25 vdiv.f32 s15, s12, s11 800eb54: ee76 7aa7 vadd.f32 s15, s13, s15 800eb58: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800eb5c: ee77 7aa6 vadd.f32 s15, s15, s13 800eb60: ee67 7a27 vmul.f32 s15, s14, s15 800eb64: edc7 7a07 vstr s15, [r7, #28] break; 800eb68: e065 b.n 800ec36 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800eb6a: 697b ldr r3, [r7, #20] 800eb6c: ee07 3a90 vmov s15, r3 800eb70: eef8 7a67 vcvt.f32.u32 s15, s15 800eb74: eddf 6a5e vldr s13, [pc, #376] @ 800ecf0 800eb78: ee86 7aa7 vdiv.f32 s14, s13, s15 800eb7c: 4b58 ldr r3, [pc, #352] @ (800ece0 ) 800eb7e: 6b1b ldr r3, [r3, #48] @ 0x30 800eb80: f3c3 0308 ubfx r3, r3, #0, #9 800eb84: ee07 3a90 vmov s15, r3 800eb88: eef8 6a67 vcvt.f32.u32 s13, s15 800eb8c: ed97 6a03 vldr s12, [r7, #12] 800eb90: eddf 5a55 vldr s11, [pc, #340] @ 800ece8 800eb94: eec6 7a25 vdiv.f32 s15, s12, s11 800eb98: ee76 7aa7 vadd.f32 s15, s13, s15 800eb9c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800eba0: ee77 7aa6 vadd.f32 s15, s15, s13 800eba4: ee67 7a27 vmul.f32 s15, s14, s15 800eba8: edc7 7a07 vstr s15, [r7, #28] break; 800ebac: e043 b.n 800ec36 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ebae: 697b ldr r3, [r7, #20] 800ebb0: ee07 3a90 vmov s15, r3 800ebb4: eef8 7a67 vcvt.f32.u32 s15, s15 800ebb8: eddf 6a4e vldr s13, [pc, #312] @ 800ecf4 800ebbc: ee86 7aa7 vdiv.f32 s14, s13, s15 800ebc0: 4b47 ldr r3, [pc, #284] @ (800ece0 ) 800ebc2: 6b1b ldr r3, [r3, #48] @ 0x30 800ebc4: f3c3 0308 ubfx r3, r3, #0, #9 800ebc8: ee07 3a90 vmov s15, r3 800ebcc: eef8 6a67 vcvt.f32.u32 s13, s15 800ebd0: ed97 6a03 vldr s12, [r7, #12] 800ebd4: eddf 5a44 vldr s11, [pc, #272] @ 800ece8 800ebd8: eec6 7a25 vdiv.f32 s15, s12, s11 800ebdc: ee76 7aa7 vadd.f32 s15, s13, s15 800ebe0: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ebe4: ee77 7aa6 vadd.f32 s15, s15, s13 800ebe8: ee67 7a27 vmul.f32 s15, s14, s15 800ebec: edc7 7a07 vstr s15, [r7, #28] break; 800ebf0: e021 b.n 800ec36 default: pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ebf2: 697b ldr r3, [r7, #20] 800ebf4: ee07 3a90 vmov s15, r3 800ebf8: eef8 7a67 vcvt.f32.u32 s15, s15 800ebfc: eddf 6a3b vldr s13, [pc, #236] @ 800ecec 800ec00: ee86 7aa7 vdiv.f32 s14, s13, s15 800ec04: 4b36 ldr r3, [pc, #216] @ (800ece0 ) 800ec06: 6b1b ldr r3, [r3, #48] @ 0x30 800ec08: f3c3 0308 ubfx r3, r3, #0, #9 800ec0c: ee07 3a90 vmov s15, r3 800ec10: eef8 6a67 vcvt.f32.u32 s13, s15 800ec14: ed97 6a03 vldr s12, [r7, #12] 800ec18: eddf 5a33 vldr s11, [pc, #204] @ 800ece8 800ec1c: eec6 7a25 vdiv.f32 s15, s12, s11 800ec20: ee76 7aa7 vadd.f32 s15, s13, s15 800ec24: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ec28: ee77 7aa6 vadd.f32 s15, s15, s13 800ec2c: ee67 7a27 vmul.f32 s15, s14, s15 800ec30: edc7 7a07 vstr s15, [r7, #28] break; 800ec34: bf00 nop } PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; 800ec36: 4b2a ldr r3, [pc, #168] @ (800ece0 ) 800ec38: 6b1b ldr r3, [r3, #48] @ 0x30 800ec3a: 0a5b lsrs r3, r3, #9 800ec3c: f003 037f and.w r3, r3, #127 @ 0x7f 800ec40: ee07 3a90 vmov s15, r3 800ec44: eef8 7a67 vcvt.f32.u32 s15, s15 800ec48: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ec4c: ee37 7a87 vadd.f32 s14, s15, s14 800ec50: edd7 6a07 vldr s13, [r7, #28] 800ec54: eec6 7a87 vdiv.f32 s15, s13, s14 800ec58: eefc 7ae7 vcvt.u32.f32 s15, s15 800ec5c: ee17 2a90 vmov r2, s15 800ec60: 687b ldr r3, [r7, #4] 800ec62: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ; 800ec64: 4b1e ldr r3, [pc, #120] @ (800ece0 ) 800ec66: 6b1b ldr r3, [r3, #48] @ 0x30 800ec68: 0c1b lsrs r3, r3, #16 800ec6a: f003 037f and.w r3, r3, #127 @ 0x7f 800ec6e: ee07 3a90 vmov s15, r3 800ec72: eef8 7a67 vcvt.f32.u32 s15, s15 800ec76: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ec7a: ee37 7a87 vadd.f32 s14, s15, s14 800ec7e: edd7 6a07 vldr s13, [r7, #28] 800ec82: eec6 7a87 vdiv.f32 s15, s13, s14 800ec86: eefc 7ae7 vcvt.u32.f32 s15, s15 800ec8a: ee17 2a90 vmov r2, s15 800ec8e: 687b ldr r3, [r7, #4] 800ec90: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; 800ec92: 4b13 ldr r3, [pc, #76] @ (800ece0 ) 800ec94: 6b1b ldr r3, [r3, #48] @ 0x30 800ec96: 0e1b lsrs r3, r3, #24 800ec98: f003 037f and.w r3, r3, #127 @ 0x7f 800ec9c: ee07 3a90 vmov s15, r3 800eca0: eef8 7a67 vcvt.f32.u32 s15, s15 800eca4: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800eca8: ee37 7a87 vadd.f32 s14, s15, s14 800ecac: edd7 6a07 vldr s13, [r7, #28] 800ecb0: eec6 7a87 vdiv.f32 s15, s13, s14 800ecb4: eefc 7ae7 vcvt.u32.f32 s15, s15 800ecb8: ee17 2a90 vmov r2, s15 800ecbc: 687b ldr r3, [r7, #4] 800ecbe: 609a str r2, [r3, #8] PLL1_Clocks->PLL1_P_Frequency = 0U; PLL1_Clocks->PLL1_Q_Frequency = 0U; PLL1_Clocks->PLL1_R_Frequency = 0U; } } 800ecc0: e008 b.n 800ecd4 PLL1_Clocks->PLL1_P_Frequency = 0U; 800ecc2: 687b ldr r3, [r7, #4] 800ecc4: 2200 movs r2, #0 800ecc6: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = 0U; 800ecc8: 687b ldr r3, [r7, #4] 800ecca: 2200 movs r2, #0 800eccc: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = 0U; 800ecce: 687b ldr r3, [r7, #4] 800ecd0: 2200 movs r2, #0 800ecd2: 609a str r2, [r3, #8] } 800ecd4: bf00 nop 800ecd6: 3724 adds r7, #36 @ 0x24 800ecd8: 46bd mov sp, r7 800ecda: f85d 7b04 ldr.w r7, [sp], #4 800ecde: 4770 bx lr 800ece0: 58024400 .word 0x58024400 800ece4: 03d09000 .word 0x03d09000 800ece8: 46000000 .word 0x46000000 800ecec: 4c742400 .word 0x4c742400 800ecf0: 4a742400 .word 0x4a742400 800ecf4: 4bbebc20 .word 0x4bbebc20 0800ecf8 : * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { 800ecf8: b580 push {r7, lr} 800ecfa: b084 sub sp, #16 800ecfc: af00 add r7, sp, #0 800ecfe: 6078 str r0, [r7, #4] 800ed00: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800ed02: 2300 movs r3, #0 800ed04: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800ed06: 4b53 ldr r3, [pc, #332] @ (800ee54 ) 800ed08: 6a9b ldr r3, [r3, #40] @ 0x28 800ed0a: f003 0303 and.w r3, r3, #3 800ed0e: 2b03 cmp r3, #3 800ed10: d101 bne.n 800ed16 { return HAL_ERROR; 800ed12: 2301 movs r3, #1 800ed14: e099 b.n 800ee4a else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 800ed16: 4b4f ldr r3, [pc, #316] @ (800ee54 ) 800ed18: 681b ldr r3, [r3, #0] 800ed1a: 4a4e ldr r2, [pc, #312] @ (800ee54 ) 800ed1c: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800ed20: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ed22: f7f6 fdbb bl 800589c 800ed26: 60b8 str r0, [r7, #8] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800ed28: e008 b.n 800ed3c { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800ed2a: f7f6 fdb7 bl 800589c 800ed2e: 4602 mov r2, r0 800ed30: 68bb ldr r3, [r7, #8] 800ed32: 1ad3 subs r3, r2, r3 800ed34: 2b02 cmp r3, #2 800ed36: d901 bls.n 800ed3c { return HAL_TIMEOUT; 800ed38: 2303 movs r3, #3 800ed3a: e086 b.n 800ee4a while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800ed3c: 4b45 ldr r3, [pc, #276] @ (800ee54 ) 800ed3e: 681b ldr r3, [r3, #0] 800ed40: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800ed44: 2b00 cmp r3, #0 800ed46: d1f0 bne.n 800ed2a } } /* Configure PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 800ed48: 4b42 ldr r3, [pc, #264] @ (800ee54 ) 800ed4a: 6a9b ldr r3, [r3, #40] @ 0x28 800ed4c: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800ed50: 687b ldr r3, [r7, #4] 800ed52: 681b ldr r3, [r3, #0] 800ed54: 031b lsls r3, r3, #12 800ed56: 493f ldr r1, [pc, #252] @ (800ee54 ) 800ed58: 4313 orrs r3, r2 800ed5a: 628b str r3, [r1, #40] @ 0x28 800ed5c: 687b ldr r3, [r7, #4] 800ed5e: 685b ldr r3, [r3, #4] 800ed60: 3b01 subs r3, #1 800ed62: f3c3 0208 ubfx r2, r3, #0, #9 800ed66: 687b ldr r3, [r7, #4] 800ed68: 689b ldr r3, [r3, #8] 800ed6a: 3b01 subs r3, #1 800ed6c: 025b lsls r3, r3, #9 800ed6e: b29b uxth r3, r3 800ed70: 431a orrs r2, r3 800ed72: 687b ldr r3, [r7, #4] 800ed74: 68db ldr r3, [r3, #12] 800ed76: 3b01 subs r3, #1 800ed78: 041b lsls r3, r3, #16 800ed7a: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800ed7e: 431a orrs r2, r3 800ed80: 687b ldr r3, [r7, #4] 800ed82: 691b ldr r3, [r3, #16] 800ed84: 3b01 subs r3, #1 800ed86: 061b lsls r3, r3, #24 800ed88: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800ed8c: 4931 ldr r1, [pc, #196] @ (800ee54 ) 800ed8e: 4313 orrs r3, r2 800ed90: 638b str r3, [r1, #56] @ 0x38 pll2->PLL2P, pll2->PLL2Q, pll2->PLL2R); /* Select PLL2 input reference frequency range: VCI */ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 800ed92: 4b30 ldr r3, [pc, #192] @ (800ee54 ) 800ed94: 6adb ldr r3, [r3, #44] @ 0x2c 800ed96: f023 02c0 bic.w r2, r3, #192 @ 0xc0 800ed9a: 687b ldr r3, [r7, #4] 800ed9c: 695b ldr r3, [r3, #20] 800ed9e: 492d ldr r1, [pc, #180] @ (800ee54 ) 800eda0: 4313 orrs r3, r2 800eda2: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL2 output frequency range : VCO */ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 800eda4: 4b2b ldr r3, [pc, #172] @ (800ee54 ) 800eda6: 6adb ldr r3, [r3, #44] @ 0x2c 800eda8: f023 0220 bic.w r2, r3, #32 800edac: 687b ldr r3, [r7, #4] 800edae: 699b ldr r3, [r3, #24] 800edb0: 4928 ldr r1, [pc, #160] @ (800ee54 ) 800edb2: 4313 orrs r3, r2 800edb4: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_DISABLE(); 800edb6: 4b27 ldr r3, [pc, #156] @ (800ee54 ) 800edb8: 6adb ldr r3, [r3, #44] @ 0x2c 800edba: 4a26 ldr r2, [pc, #152] @ (800ee54 ) 800edbc: f023 0310 bic.w r3, r3, #16 800edc0: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 800edc2: 4b24 ldr r3, [pc, #144] @ (800ee54 ) 800edc4: 6bda ldr r2, [r3, #60] @ 0x3c 800edc6: 4b24 ldr r3, [pc, #144] @ (800ee58 ) 800edc8: 4013 ands r3, r2 800edca: 687a ldr r2, [r7, #4] 800edcc: 69d2 ldr r2, [r2, #28] 800edce: 00d2 lsls r2, r2, #3 800edd0: 4920 ldr r1, [pc, #128] @ (800ee54 ) 800edd2: 4313 orrs r3, r2 800edd4: 63cb str r3, [r1, #60] @ 0x3c /* Enable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_ENABLE(); 800edd6: 4b1f ldr r3, [pc, #124] @ (800ee54 ) 800edd8: 6adb ldr r3, [r3, #44] @ 0x2c 800edda: 4a1e ldr r2, [pc, #120] @ (800ee54 ) 800eddc: f043 0310 orr.w r3, r3, #16 800ede0: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL2 clock output */ if (Divider == DIVIDER_P_UPDATE) 800ede2: 683b ldr r3, [r7, #0] 800ede4: 2b00 cmp r3, #0 800ede6: d106 bne.n 800edf6 { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 800ede8: 4b1a ldr r3, [pc, #104] @ (800ee54 ) 800edea: 6adb ldr r3, [r3, #44] @ 0x2c 800edec: 4a19 ldr r2, [pc, #100] @ (800ee54 ) 800edee: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800edf2: 62d3 str r3, [r2, #44] @ 0x2c 800edf4: e00f b.n 800ee16 } else if (Divider == DIVIDER_Q_UPDATE) 800edf6: 683b ldr r3, [r7, #0] 800edf8: 2b01 cmp r3, #1 800edfa: d106 bne.n 800ee0a { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 800edfc: 4b15 ldr r3, [pc, #84] @ (800ee54 ) 800edfe: 6adb ldr r3, [r3, #44] @ 0x2c 800ee00: 4a14 ldr r2, [pc, #80] @ (800ee54 ) 800ee02: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800ee06: 62d3 str r3, [r2, #44] @ 0x2c 800ee08: e005 b.n 800ee16 } else { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 800ee0a: 4b12 ldr r3, [pc, #72] @ (800ee54 ) 800ee0c: 6adb ldr r3, [r3, #44] @ 0x2c 800ee0e: 4a11 ldr r2, [pc, #68] @ (800ee54 ) 800ee10: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 800ee14: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL2. */ __HAL_RCC_PLL2_ENABLE(); 800ee16: 4b0f ldr r3, [pc, #60] @ (800ee54 ) 800ee18: 681b ldr r3, [r3, #0] 800ee1a: 4a0e ldr r2, [pc, #56] @ (800ee54 ) 800ee1c: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 800ee20: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ee22: f7f6 fd3b bl 800589c 800ee26: 60b8 str r0, [r7, #8] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800ee28: e008 b.n 800ee3c { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800ee2a: f7f6 fd37 bl 800589c 800ee2e: 4602 mov r2, r0 800ee30: 68bb ldr r3, [r7, #8] 800ee32: 1ad3 subs r3, r2, r3 800ee34: 2b02 cmp r3, #2 800ee36: d901 bls.n 800ee3c { return HAL_TIMEOUT; 800ee38: 2303 movs r3, #3 800ee3a: e006 b.n 800ee4a while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800ee3c: 4b05 ldr r3, [pc, #20] @ (800ee54 ) 800ee3e: 681b ldr r3, [r3, #0] 800ee40: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800ee44: 2b00 cmp r3, #0 800ee46: d0f0 beq.n 800ee2a } } return status; 800ee48: 7bfb ldrb r3, [r7, #15] } 800ee4a: 4618 mov r0, r3 800ee4c: 3710 adds r7, #16 800ee4e: 46bd mov sp, r7 800ee50: bd80 pop {r7, pc} 800ee52: bf00 nop 800ee54: 58024400 .word 0x58024400 800ee58: ffff0007 .word 0xffff0007 0800ee5c : * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { 800ee5c: b580 push {r7, lr} 800ee5e: b084 sub sp, #16 800ee60: af00 add r7, sp, #0 800ee62: 6078 str r0, [r7, #4] 800ee64: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800ee66: 2300 movs r3, #0 800ee68: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800ee6a: 4b53 ldr r3, [pc, #332] @ (800efb8 ) 800ee6c: 6a9b ldr r3, [r3, #40] @ 0x28 800ee6e: f003 0303 and.w r3, r3, #3 800ee72: 2b03 cmp r3, #3 800ee74: d101 bne.n 800ee7a { return HAL_ERROR; 800ee76: 2301 movs r3, #1 800ee78: e099 b.n 800efae else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 800ee7a: 4b4f ldr r3, [pc, #316] @ (800efb8 ) 800ee7c: 681b ldr r3, [r3, #0] 800ee7e: 4a4e ldr r2, [pc, #312] @ (800efb8 ) 800ee80: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800ee84: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ee86: f7f6 fd09 bl 800589c 800ee8a: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800ee8c: e008 b.n 800eea0 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800ee8e: f7f6 fd05 bl 800589c 800ee92: 4602 mov r2, r0 800ee94: 68bb ldr r3, [r7, #8] 800ee96: 1ad3 subs r3, r2, r3 800ee98: 2b02 cmp r3, #2 800ee9a: d901 bls.n 800eea0 { return HAL_TIMEOUT; 800ee9c: 2303 movs r3, #3 800ee9e: e086 b.n 800efae while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800eea0: 4b45 ldr r3, [pc, #276] @ (800efb8 ) 800eea2: 681b ldr r3, [r3, #0] 800eea4: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800eea8: 2b00 cmp r3, #0 800eeaa: d1f0 bne.n 800ee8e } } /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 800eeac: 4b42 ldr r3, [pc, #264] @ (800efb8 ) 800eeae: 6a9b ldr r3, [r3, #40] @ 0x28 800eeb0: f023 727c bic.w r2, r3, #66060288 @ 0x3f00000 800eeb4: 687b ldr r3, [r7, #4] 800eeb6: 681b ldr r3, [r3, #0] 800eeb8: 051b lsls r3, r3, #20 800eeba: 493f ldr r1, [pc, #252] @ (800efb8 ) 800eebc: 4313 orrs r3, r2 800eebe: 628b str r3, [r1, #40] @ 0x28 800eec0: 687b ldr r3, [r7, #4] 800eec2: 685b ldr r3, [r3, #4] 800eec4: 3b01 subs r3, #1 800eec6: f3c3 0208 ubfx r2, r3, #0, #9 800eeca: 687b ldr r3, [r7, #4] 800eecc: 689b ldr r3, [r3, #8] 800eece: 3b01 subs r3, #1 800eed0: 025b lsls r3, r3, #9 800eed2: b29b uxth r3, r3 800eed4: 431a orrs r2, r3 800eed6: 687b ldr r3, [r7, #4] 800eed8: 68db ldr r3, [r3, #12] 800eeda: 3b01 subs r3, #1 800eedc: 041b lsls r3, r3, #16 800eede: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800eee2: 431a orrs r2, r3 800eee4: 687b ldr r3, [r7, #4] 800eee6: 691b ldr r3, [r3, #16] 800eee8: 3b01 subs r3, #1 800eeea: 061b lsls r3, r3, #24 800eeec: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800eef0: 4931 ldr r1, [pc, #196] @ (800efb8 ) 800eef2: 4313 orrs r3, r2 800eef4: 640b str r3, [r1, #64] @ 0x40 pll3->PLL3P, pll3->PLL3Q, pll3->PLL3R); /* Select PLL3 input reference frequency range: VCI */ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 800eef6: 4b30 ldr r3, [pc, #192] @ (800efb8 ) 800eef8: 6adb ldr r3, [r3, #44] @ 0x2c 800eefa: f423 6240 bic.w r2, r3, #3072 @ 0xc00 800eefe: 687b ldr r3, [r7, #4] 800ef00: 695b ldr r3, [r3, #20] 800ef02: 492d ldr r1, [pc, #180] @ (800efb8 ) 800ef04: 4313 orrs r3, r2 800ef06: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL3 output frequency range : VCO */ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 800ef08: 4b2b ldr r3, [pc, #172] @ (800efb8 ) 800ef0a: 6adb ldr r3, [r3, #44] @ 0x2c 800ef0c: f423 7200 bic.w r2, r3, #512 @ 0x200 800ef10: 687b ldr r3, [r7, #4] 800ef12: 699b ldr r3, [r3, #24] 800ef14: 4928 ldr r1, [pc, #160] @ (800efb8 ) 800ef16: 4313 orrs r3, r2 800ef18: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_DISABLE(); 800ef1a: 4b27 ldr r3, [pc, #156] @ (800efb8 ) 800ef1c: 6adb ldr r3, [r3, #44] @ 0x2c 800ef1e: 4a26 ldr r2, [pc, #152] @ (800efb8 ) 800ef20: f423 7380 bic.w r3, r3, #256 @ 0x100 800ef24: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 800ef26: 4b24 ldr r3, [pc, #144] @ (800efb8 ) 800ef28: 6c5a ldr r2, [r3, #68] @ 0x44 800ef2a: 4b24 ldr r3, [pc, #144] @ (800efbc ) 800ef2c: 4013 ands r3, r2 800ef2e: 687a ldr r2, [r7, #4] 800ef30: 69d2 ldr r2, [r2, #28] 800ef32: 00d2 lsls r2, r2, #3 800ef34: 4920 ldr r1, [pc, #128] @ (800efb8 ) 800ef36: 4313 orrs r3, r2 800ef38: 644b str r3, [r1, #68] @ 0x44 /* Enable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_ENABLE(); 800ef3a: 4b1f ldr r3, [pc, #124] @ (800efb8 ) 800ef3c: 6adb ldr r3, [r3, #44] @ 0x2c 800ef3e: 4a1e ldr r2, [pc, #120] @ (800efb8 ) 800ef40: f443 7380 orr.w r3, r3, #256 @ 0x100 800ef44: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL3 clock output */ if (Divider == DIVIDER_P_UPDATE) 800ef46: 683b ldr r3, [r7, #0] 800ef48: 2b00 cmp r3, #0 800ef4a: d106 bne.n 800ef5a { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 800ef4c: 4b1a ldr r3, [pc, #104] @ (800efb8 ) 800ef4e: 6adb ldr r3, [r3, #44] @ 0x2c 800ef50: 4a19 ldr r2, [pc, #100] @ (800efb8 ) 800ef52: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 800ef56: 62d3 str r3, [r2, #44] @ 0x2c 800ef58: e00f b.n 800ef7a } else if (Divider == DIVIDER_Q_UPDATE) 800ef5a: 683b ldr r3, [r7, #0] 800ef5c: 2b01 cmp r3, #1 800ef5e: d106 bne.n 800ef6e { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 800ef60: 4b15 ldr r3, [pc, #84] @ (800efb8 ) 800ef62: 6adb ldr r3, [r3, #44] @ 0x2c 800ef64: 4a14 ldr r2, [pc, #80] @ (800efb8 ) 800ef66: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 800ef6a: 62d3 str r3, [r2, #44] @ 0x2c 800ef6c: e005 b.n 800ef7a } else { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 800ef6e: 4b12 ldr r3, [pc, #72] @ (800efb8 ) 800ef70: 6adb ldr r3, [r3, #44] @ 0x2c 800ef72: 4a11 ldr r2, [pc, #68] @ (800efb8 ) 800ef74: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800ef78: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL3. */ __HAL_RCC_PLL3_ENABLE(); 800ef7a: 4b0f ldr r3, [pc, #60] @ (800efb8 ) 800ef7c: 681b ldr r3, [r3, #0] 800ef7e: 4a0e ldr r2, [pc, #56] @ (800efb8 ) 800ef80: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800ef84: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ef86: f7f6 fc89 bl 800589c 800ef8a: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800ef8c: e008 b.n 800efa0 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800ef8e: f7f6 fc85 bl 800589c 800ef92: 4602 mov r2, r0 800ef94: 68bb ldr r3, [r7, #8] 800ef96: 1ad3 subs r3, r2, r3 800ef98: 2b02 cmp r3, #2 800ef9a: d901 bls.n 800efa0 { return HAL_TIMEOUT; 800ef9c: 2303 movs r3, #3 800ef9e: e006 b.n 800efae while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800efa0: 4b05 ldr r3, [pc, #20] @ (800efb8 ) 800efa2: 681b ldr r3, [r3, #0] 800efa4: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800efa8: 2b00 cmp r3, #0 800efaa: d0f0 beq.n 800ef8e } } return status; 800efac: 7bfb ldrb r3, [r7, #15] } 800efae: 4618 mov r0, r3 800efb0: 3710 adds r7, #16 800efb2: 46bd mov sp, r7 800efb4: bd80 pop {r7, pc} 800efb6: bf00 nop 800efb8: 58024400 .word 0x58024400 800efbc: ffff0007 .word 0xffff0007 0800efc0 : * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL status */ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { 800efc0: b580 push {r7, lr} 800efc2: b084 sub sp, #16 800efc4: af00 add r7, sp, #0 800efc6: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the RNG handle allocation */ if (hrng == NULL) 800efc8: 687b ldr r3, [r7, #4] 800efca: 2b00 cmp r3, #0 800efcc: d101 bne.n 800efd2 { return HAL_ERROR; 800efce: 2301 movs r3, #1 800efd0: e054 b.n 800f07c /* Init the low level hardware */ hrng->MspInitCallback(hrng); } #else if (hrng->State == HAL_RNG_STATE_RESET) 800efd2: 687b ldr r3, [r7, #4] 800efd4: 7a5b ldrb r3, [r3, #9] 800efd6: b2db uxtb r3, r3 800efd8: 2b00 cmp r3, #0 800efda: d105 bne.n 800efe8 { /* Allocate lock resource and initialize it */ hrng->Lock = HAL_UNLOCKED; 800efdc: 687b ldr r3, [r7, #4] 800efde: 2200 movs r2, #0 800efe0: 721a strb r2, [r3, #8] /* Init the low level hardware */ HAL_RNG_MspInit(hrng); 800efe2: 6878 ldr r0, [r7, #4] 800efe4: f7f4 fe9e bl 8003d24 } #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; 800efe8: 687b ldr r3, [r7, #4] 800efea: 2202 movs r2, #2 800efec: 725a strb r2, [r3, #9] } } } #else /* Clock Error Detection Configuration */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection); 800efee: 687b ldr r3, [r7, #4] 800eff0: 681b ldr r3, [r3, #0] 800eff2: 681b ldr r3, [r3, #0] 800eff4: f023 0120 bic.w r1, r3, #32 800eff8: 687b ldr r3, [r7, #4] 800effa: 685a ldr r2, [r3, #4] 800effc: 687b ldr r3, [r7, #4] 800effe: 681b ldr r3, [r3, #0] 800f000: 430a orrs r2, r1 800f002: 601a str r2, [r3, #0] #endif /* RNG_CR_CONDRST */ /* Enable the RNG Peripheral */ __HAL_RNG_ENABLE(hrng); 800f004: 687b ldr r3, [r7, #4] 800f006: 681b ldr r3, [r3, #0] 800f008: 681a ldr r2, [r3, #0] 800f00a: 687b ldr r3, [r7, #4] 800f00c: 681b ldr r3, [r3, #0] 800f00e: f042 0204 orr.w r2, r2, #4 800f012: 601a str r2, [r3, #0] /* verify that no seed error */ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) 800f014: 687b ldr r3, [r7, #4] 800f016: 681b ldr r3, [r3, #0] 800f018: 685b ldr r3, [r3, #4] 800f01a: f003 0340 and.w r3, r3, #64 @ 0x40 800f01e: 2b40 cmp r3, #64 @ 0x40 800f020: d104 bne.n 800f02c { hrng->State = HAL_RNG_STATE_ERROR; 800f022: 687b ldr r3, [r7, #4] 800f024: 2204 movs r2, #4 800f026: 725a strb r2, [r3, #9] return HAL_ERROR; 800f028: 2301 movs r3, #1 800f02a: e027 b.n 800f07c } /* Get tick */ tickstart = HAL_GetTick(); 800f02c: f7f6 fc36 bl 800589c 800f030: 60f8 str r0, [r7, #12] /* Check if data register contains valid random data */ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f032: e015 b.n 800f060 { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) 800f034: f7f6 fc32 bl 800589c 800f038: 4602 mov r2, r0 800f03a: 68fb ldr r3, [r7, #12] 800f03c: 1ad3 subs r3, r2, r3 800f03e: 2b02 cmp r3, #2 800f040: d90e bls.n 800f060 { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f042: 687b ldr r3, [r7, #4] 800f044: 681b ldr r3, [r3, #0] 800f046: 685b ldr r3, [r3, #4] 800f048: f003 0304 and.w r3, r3, #4 800f04c: 2b04 cmp r3, #4 800f04e: d107 bne.n 800f060 { hrng->State = HAL_RNG_STATE_ERROR; 800f050: 687b ldr r3, [r7, #4] 800f052: 2204 movs r2, #4 800f054: 725a strb r2, [r3, #9] hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; 800f056: 687b ldr r3, [r7, #4] 800f058: 2202 movs r2, #2 800f05a: 60da str r2, [r3, #12] return HAL_ERROR; 800f05c: 2301 movs r3, #1 800f05e: e00d b.n 800f07c while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f060: 687b ldr r3, [r7, #4] 800f062: 681b ldr r3, [r3, #0] 800f064: 685b ldr r3, [r3, #4] 800f066: f003 0304 and.w r3, r3, #4 800f06a: 2b04 cmp r3, #4 800f06c: d0e2 beq.n 800f034 } } } /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; 800f06e: 687b ldr r3, [r7, #4] 800f070: 2201 movs r2, #1 800f072: 725a strb r2, [r3, #9] /* Initialise the error code */ hrng->ErrorCode = HAL_RNG_ERROR_NONE; 800f074: 687b ldr r3, [r7, #4] 800f076: 2200 movs r2, #0 800f078: 60da str r2, [r3, #12] /* Return function status */ return HAL_OK; 800f07a: 2300 movs r3, #0 } 800f07c: 4618 mov r0, r3 800f07e: 3710 adds r7, #16 800f080: 46bd mov sp, r7 800f082: bd80 pop {r7, pc} 0800f084 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 800f084: b580 push {r7, lr} 800f086: b082 sub sp, #8 800f088: af00 add r7, sp, #0 800f08a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800f08c: 687b ldr r3, [r7, #4] 800f08e: 2b00 cmp r3, #0 800f090: d101 bne.n 800f096 { return HAL_ERROR; 800f092: 2301 movs r3, #1 800f094: e049 b.n 800f12a assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800f096: 687b ldr r3, [r7, #4] 800f098: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f09c: b2db uxtb r3, r3 800f09e: 2b00 cmp r3, #0 800f0a0: d106 bne.n 800f0b0 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800f0a2: 687b ldr r3, [r7, #4] 800f0a4: 2200 movs r2, #0 800f0a6: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800f0aa: 6878 ldr r0, [r7, #4] 800f0ac: f7f4 feae bl 8003e0c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f0b0: 687b ldr r3, [r7, #4] 800f0b2: 2202 movs r2, #2 800f0b4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800f0b8: 687b ldr r3, [r7, #4] 800f0ba: 681a ldr r2, [r3, #0] 800f0bc: 687b ldr r3, [r7, #4] 800f0be: 3304 adds r3, #4 800f0c0: 4619 mov r1, r3 800f0c2: 4610 mov r0, r2 800f0c4: f000 fe90 bl 800fde8 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800f0c8: 687b ldr r3, [r7, #4] 800f0ca: 2201 movs r2, #1 800f0cc: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f0d0: 687b ldr r3, [r7, #4] 800f0d2: 2201 movs r2, #1 800f0d4: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f0d8: 687b ldr r3, [r7, #4] 800f0da: 2201 movs r2, #1 800f0dc: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f0e0: 687b ldr r3, [r7, #4] 800f0e2: 2201 movs r2, #1 800f0e4: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f0e8: 687b ldr r3, [r7, #4] 800f0ea: 2201 movs r2, #1 800f0ec: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f0f0: 687b ldr r3, [r7, #4] 800f0f2: 2201 movs r2, #1 800f0f4: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f0f8: 687b ldr r3, [r7, #4] 800f0fa: 2201 movs r2, #1 800f0fc: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f100: 687b ldr r3, [r7, #4] 800f102: 2201 movs r2, #1 800f104: f883 2044 strb.w r2, [r3, #68] @ 0x44 800f108: 687b ldr r3, [r7, #4] 800f10a: 2201 movs r2, #1 800f10c: f883 2045 strb.w r2, [r3, #69] @ 0x45 800f110: 687b ldr r3, [r7, #4] 800f112: 2201 movs r2, #1 800f114: f883 2046 strb.w r2, [r3, #70] @ 0x46 800f118: 687b ldr r3, [r7, #4] 800f11a: 2201 movs r2, #1 800f11c: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800f120: 687b ldr r3, [r7, #4] 800f122: 2201 movs r2, #1 800f124: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800f128: 2300 movs r3, #0 } 800f12a: 4618 mov r0, r3 800f12c: 3708 adds r7, #8 800f12e: 46bd mov sp, r7 800f130: bd80 pop {r7, pc} ... 0800f134 : * @brief Starts the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { 800f134: b480 push {r7} 800f136: b085 sub sp, #20 800f138: af00 add r7, sp, #0 800f13a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800f13c: 687b ldr r3, [r7, #4] 800f13e: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f142: b2db uxtb r3, r3 800f144: 2b01 cmp r3, #1 800f146: d001 beq.n 800f14c { return HAL_ERROR; 800f148: 2301 movs r3, #1 800f14a: e04c b.n 800f1e6 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f14c: 687b ldr r3, [r7, #4] 800f14e: 2202 movs r2, #2 800f150: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f154: 687b ldr r3, [r7, #4] 800f156: 681b ldr r3, [r3, #0] 800f158: 4a26 ldr r2, [pc, #152] @ (800f1f4 ) 800f15a: 4293 cmp r3, r2 800f15c: d022 beq.n 800f1a4 800f15e: 687b ldr r3, [r7, #4] 800f160: 681b ldr r3, [r3, #0] 800f162: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f166: d01d beq.n 800f1a4 800f168: 687b ldr r3, [r7, #4] 800f16a: 681b ldr r3, [r3, #0] 800f16c: 4a22 ldr r2, [pc, #136] @ (800f1f8 ) 800f16e: 4293 cmp r3, r2 800f170: d018 beq.n 800f1a4 800f172: 687b ldr r3, [r7, #4] 800f174: 681b ldr r3, [r3, #0] 800f176: 4a21 ldr r2, [pc, #132] @ (800f1fc ) 800f178: 4293 cmp r3, r2 800f17a: d013 beq.n 800f1a4 800f17c: 687b ldr r3, [r7, #4] 800f17e: 681b ldr r3, [r3, #0] 800f180: 4a1f ldr r2, [pc, #124] @ (800f200 ) 800f182: 4293 cmp r3, r2 800f184: d00e beq.n 800f1a4 800f186: 687b ldr r3, [r7, #4] 800f188: 681b ldr r3, [r3, #0] 800f18a: 4a1e ldr r2, [pc, #120] @ (800f204 ) 800f18c: 4293 cmp r3, r2 800f18e: d009 beq.n 800f1a4 800f190: 687b ldr r3, [r7, #4] 800f192: 681b ldr r3, [r3, #0] 800f194: 4a1c ldr r2, [pc, #112] @ (800f208 ) 800f196: 4293 cmp r3, r2 800f198: d004 beq.n 800f1a4 800f19a: 687b ldr r3, [r7, #4] 800f19c: 681b ldr r3, [r3, #0] 800f19e: 4a1b ldr r2, [pc, #108] @ (800f20c ) 800f1a0: 4293 cmp r3, r2 800f1a2: d115 bne.n 800f1d0 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f1a4: 687b ldr r3, [r7, #4] 800f1a6: 681b ldr r3, [r3, #0] 800f1a8: 689a ldr r2, [r3, #8] 800f1aa: 4b19 ldr r3, [pc, #100] @ (800f210 ) 800f1ac: 4013 ands r3, r2 800f1ae: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f1b0: 68fb ldr r3, [r7, #12] 800f1b2: 2b06 cmp r3, #6 800f1b4: d015 beq.n 800f1e2 800f1b6: 68fb ldr r3, [r7, #12] 800f1b8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f1bc: d011 beq.n 800f1e2 { __HAL_TIM_ENABLE(htim); 800f1be: 687b ldr r3, [r7, #4] 800f1c0: 681b ldr r3, [r3, #0] 800f1c2: 681a ldr r2, [r3, #0] 800f1c4: 687b ldr r3, [r7, #4] 800f1c6: 681b ldr r3, [r3, #0] 800f1c8: f042 0201 orr.w r2, r2, #1 800f1cc: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f1ce: e008 b.n 800f1e2 } } else { __HAL_TIM_ENABLE(htim); 800f1d0: 687b ldr r3, [r7, #4] 800f1d2: 681b ldr r3, [r3, #0] 800f1d4: 681a ldr r2, [r3, #0] 800f1d6: 687b ldr r3, [r7, #4] 800f1d8: 681b ldr r3, [r3, #0] 800f1da: f042 0201 orr.w r2, r2, #1 800f1de: 601a str r2, [r3, #0] 800f1e0: e000 b.n 800f1e4 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f1e2: bf00 nop } /* Return function status */ return HAL_OK; 800f1e4: 2300 movs r3, #0 } 800f1e6: 4618 mov r0, r3 800f1e8: 3714 adds r7, #20 800f1ea: 46bd mov sp, r7 800f1ec: f85d 7b04 ldr.w r7, [sp], #4 800f1f0: 4770 bx lr 800f1f2: bf00 nop 800f1f4: 40010000 .word 0x40010000 800f1f8: 40000400 .word 0x40000400 800f1fc: 40000800 .word 0x40000800 800f200: 40000c00 .word 0x40000c00 800f204: 40010400 .word 0x40010400 800f208: 40001800 .word 0x40001800 800f20c: 40014000 .word 0x40014000 800f210: 00010007 .word 0x00010007 0800f214 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 800f214: b480 push {r7} 800f216: b085 sub sp, #20 800f218: af00 add r7, sp, #0 800f21a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800f21c: 687b ldr r3, [r7, #4] 800f21e: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f222: b2db uxtb r3, r3 800f224: 2b01 cmp r3, #1 800f226: d001 beq.n 800f22c { return HAL_ERROR; 800f228: 2301 movs r3, #1 800f22a: e054 b.n 800f2d6 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f22c: 687b ldr r3, [r7, #4] 800f22e: 2202 movs r2, #2 800f230: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 800f234: 687b ldr r3, [r7, #4] 800f236: 681b ldr r3, [r3, #0] 800f238: 68da ldr r2, [r3, #12] 800f23a: 687b ldr r3, [r7, #4] 800f23c: 681b ldr r3, [r3, #0] 800f23e: f042 0201 orr.w r2, r2, #1 800f242: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f244: 687b ldr r3, [r7, #4] 800f246: 681b ldr r3, [r3, #0] 800f248: 4a26 ldr r2, [pc, #152] @ (800f2e4 ) 800f24a: 4293 cmp r3, r2 800f24c: d022 beq.n 800f294 800f24e: 687b ldr r3, [r7, #4] 800f250: 681b ldr r3, [r3, #0] 800f252: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f256: d01d beq.n 800f294 800f258: 687b ldr r3, [r7, #4] 800f25a: 681b ldr r3, [r3, #0] 800f25c: 4a22 ldr r2, [pc, #136] @ (800f2e8 ) 800f25e: 4293 cmp r3, r2 800f260: d018 beq.n 800f294 800f262: 687b ldr r3, [r7, #4] 800f264: 681b ldr r3, [r3, #0] 800f266: 4a21 ldr r2, [pc, #132] @ (800f2ec ) 800f268: 4293 cmp r3, r2 800f26a: d013 beq.n 800f294 800f26c: 687b ldr r3, [r7, #4] 800f26e: 681b ldr r3, [r3, #0] 800f270: 4a1f ldr r2, [pc, #124] @ (800f2f0 ) 800f272: 4293 cmp r3, r2 800f274: d00e beq.n 800f294 800f276: 687b ldr r3, [r7, #4] 800f278: 681b ldr r3, [r3, #0] 800f27a: 4a1e ldr r2, [pc, #120] @ (800f2f4 ) 800f27c: 4293 cmp r3, r2 800f27e: d009 beq.n 800f294 800f280: 687b ldr r3, [r7, #4] 800f282: 681b ldr r3, [r3, #0] 800f284: 4a1c ldr r2, [pc, #112] @ (800f2f8 ) 800f286: 4293 cmp r3, r2 800f288: d004 beq.n 800f294 800f28a: 687b ldr r3, [r7, #4] 800f28c: 681b ldr r3, [r3, #0] 800f28e: 4a1b ldr r2, [pc, #108] @ (800f2fc ) 800f290: 4293 cmp r3, r2 800f292: d115 bne.n 800f2c0 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f294: 687b ldr r3, [r7, #4] 800f296: 681b ldr r3, [r3, #0] 800f298: 689a ldr r2, [r3, #8] 800f29a: 4b19 ldr r3, [pc, #100] @ (800f300 ) 800f29c: 4013 ands r3, r2 800f29e: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f2a0: 68fb ldr r3, [r7, #12] 800f2a2: 2b06 cmp r3, #6 800f2a4: d015 beq.n 800f2d2 800f2a6: 68fb ldr r3, [r7, #12] 800f2a8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f2ac: d011 beq.n 800f2d2 { __HAL_TIM_ENABLE(htim); 800f2ae: 687b ldr r3, [r7, #4] 800f2b0: 681b ldr r3, [r3, #0] 800f2b2: 681a ldr r2, [r3, #0] 800f2b4: 687b ldr r3, [r7, #4] 800f2b6: 681b ldr r3, [r3, #0] 800f2b8: f042 0201 orr.w r2, r2, #1 800f2bc: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f2be: e008 b.n 800f2d2 } } else { __HAL_TIM_ENABLE(htim); 800f2c0: 687b ldr r3, [r7, #4] 800f2c2: 681b ldr r3, [r3, #0] 800f2c4: 681a ldr r2, [r3, #0] 800f2c6: 687b ldr r3, [r7, #4] 800f2c8: 681b ldr r3, [r3, #0] 800f2ca: f042 0201 orr.w r2, r2, #1 800f2ce: 601a str r2, [r3, #0] 800f2d0: e000 b.n 800f2d4 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f2d2: bf00 nop } /* Return function status */ return HAL_OK; 800f2d4: 2300 movs r3, #0 } 800f2d6: 4618 mov r0, r3 800f2d8: 3714 adds r7, #20 800f2da: 46bd mov sp, r7 800f2dc: f85d 7b04 ldr.w r7, [sp], #4 800f2e0: 4770 bx lr 800f2e2: bf00 nop 800f2e4: 40010000 .word 0x40010000 800f2e8: 40000400 .word 0x40000400 800f2ec: 40000800 .word 0x40000800 800f2f0: 40000c00 .word 0x40000c00 800f2f4: 40010400 .word 0x40010400 800f2f8: 40001800 .word 0x40001800 800f2fc: 40014000 .word 0x40014000 800f300: 00010007 .word 0x00010007 0800f304 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 800f304: b580 push {r7, lr} 800f306: b082 sub sp, #8 800f308: af00 add r7, sp, #0 800f30a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800f30c: 687b ldr r3, [r7, #4] 800f30e: 2b00 cmp r3, #0 800f310: d101 bne.n 800f316 { return HAL_ERROR; 800f312: 2301 movs r3, #1 800f314: e049 b.n 800f3aa assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800f316: 687b ldr r3, [r7, #4] 800f318: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f31c: b2db uxtb r3, r3 800f31e: 2b00 cmp r3, #0 800f320: d106 bne.n 800f330 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800f322: 687b ldr r3, [r7, #4] 800f324: 2200 movs r2, #0 800f326: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 800f32a: 6878 ldr r0, [r7, #4] 800f32c: f7f4 fd34 bl 8003d98 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f330: 687b ldr r3, [r7, #4] 800f332: 2202 movs r2, #2 800f334: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800f338: 687b ldr r3, [r7, #4] 800f33a: 681a ldr r2, [r3, #0] 800f33c: 687b ldr r3, [r7, #4] 800f33e: 3304 adds r3, #4 800f340: 4619 mov r1, r3 800f342: 4610 mov r0, r2 800f344: f000 fd50 bl 800fde8 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800f348: 687b ldr r3, [r7, #4] 800f34a: 2201 movs r2, #1 800f34c: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f350: 687b ldr r3, [r7, #4] 800f352: 2201 movs r2, #1 800f354: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f358: 687b ldr r3, [r7, #4] 800f35a: 2201 movs r2, #1 800f35c: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f360: 687b ldr r3, [r7, #4] 800f362: 2201 movs r2, #1 800f364: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f368: 687b ldr r3, [r7, #4] 800f36a: 2201 movs r2, #1 800f36c: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f370: 687b ldr r3, [r7, #4] 800f372: 2201 movs r2, #1 800f374: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f378: 687b ldr r3, [r7, #4] 800f37a: 2201 movs r2, #1 800f37c: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f380: 687b ldr r3, [r7, #4] 800f382: 2201 movs r2, #1 800f384: f883 2044 strb.w r2, [r3, #68] @ 0x44 800f388: 687b ldr r3, [r7, #4] 800f38a: 2201 movs r2, #1 800f38c: f883 2045 strb.w r2, [r3, #69] @ 0x45 800f390: 687b ldr r3, [r7, #4] 800f392: 2201 movs r2, #1 800f394: f883 2046 strb.w r2, [r3, #70] @ 0x46 800f398: 687b ldr r3, [r7, #4] 800f39a: 2201 movs r2, #1 800f39c: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800f3a0: 687b ldr r3, [r7, #4] 800f3a2: 2201 movs r2, #1 800f3a4: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800f3a8: 2300 movs r3, #0 } 800f3aa: 4618 mov r0, r3 800f3ac: 3708 adds r7, #8 800f3ae: 46bd mov sp, r7 800f3b0: bd80 pop {r7, pc} ... 0800f3b4 : * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 800f3b4: b580 push {r7, lr} 800f3b6: b084 sub sp, #16 800f3b8: af00 add r7, sp, #0 800f3ba: 6078 str r0, [r7, #4] 800f3bc: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 800f3be: 683b ldr r3, [r7, #0] 800f3c0: 2b00 cmp r3, #0 800f3c2: d109 bne.n 800f3d8 800f3c4: 687b ldr r3, [r7, #4] 800f3c6: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800f3ca: b2db uxtb r3, r3 800f3cc: 2b01 cmp r3, #1 800f3ce: bf14 ite ne 800f3d0: 2301 movne r3, #1 800f3d2: 2300 moveq r3, #0 800f3d4: b2db uxtb r3, r3 800f3d6: e03c b.n 800f452 800f3d8: 683b ldr r3, [r7, #0] 800f3da: 2b04 cmp r3, #4 800f3dc: d109 bne.n 800f3f2 800f3de: 687b ldr r3, [r7, #4] 800f3e0: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800f3e4: b2db uxtb r3, r3 800f3e6: 2b01 cmp r3, #1 800f3e8: bf14 ite ne 800f3ea: 2301 movne r3, #1 800f3ec: 2300 moveq r3, #0 800f3ee: b2db uxtb r3, r3 800f3f0: e02f b.n 800f452 800f3f2: 683b ldr r3, [r7, #0] 800f3f4: 2b08 cmp r3, #8 800f3f6: d109 bne.n 800f40c 800f3f8: 687b ldr r3, [r7, #4] 800f3fa: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800f3fe: b2db uxtb r3, r3 800f400: 2b01 cmp r3, #1 800f402: bf14 ite ne 800f404: 2301 movne r3, #1 800f406: 2300 moveq r3, #0 800f408: b2db uxtb r3, r3 800f40a: e022 b.n 800f452 800f40c: 683b ldr r3, [r7, #0] 800f40e: 2b0c cmp r3, #12 800f410: d109 bne.n 800f426 800f412: 687b ldr r3, [r7, #4] 800f414: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800f418: b2db uxtb r3, r3 800f41a: 2b01 cmp r3, #1 800f41c: bf14 ite ne 800f41e: 2301 movne r3, #1 800f420: 2300 moveq r3, #0 800f422: b2db uxtb r3, r3 800f424: e015 b.n 800f452 800f426: 683b ldr r3, [r7, #0] 800f428: 2b10 cmp r3, #16 800f42a: d109 bne.n 800f440 800f42c: 687b ldr r3, [r7, #4] 800f42e: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800f432: b2db uxtb r3, r3 800f434: 2b01 cmp r3, #1 800f436: bf14 ite ne 800f438: 2301 movne r3, #1 800f43a: 2300 moveq r3, #0 800f43c: b2db uxtb r3, r3 800f43e: e008 b.n 800f452 800f440: 687b ldr r3, [r7, #4] 800f442: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800f446: b2db uxtb r3, r3 800f448: 2b01 cmp r3, #1 800f44a: bf14 ite ne 800f44c: 2301 movne r3, #1 800f44e: 2300 moveq r3, #0 800f450: b2db uxtb r3, r3 800f452: 2b00 cmp r3, #0 800f454: d001 beq.n 800f45a { return HAL_ERROR; 800f456: 2301 movs r3, #1 800f458: e0a1 b.n 800f59e } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800f45a: 683b ldr r3, [r7, #0] 800f45c: 2b00 cmp r3, #0 800f45e: d104 bne.n 800f46a 800f460: 687b ldr r3, [r7, #4] 800f462: 2202 movs r2, #2 800f464: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f468: e023 b.n 800f4b2 800f46a: 683b ldr r3, [r7, #0] 800f46c: 2b04 cmp r3, #4 800f46e: d104 bne.n 800f47a 800f470: 687b ldr r3, [r7, #4] 800f472: 2202 movs r2, #2 800f474: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f478: e01b b.n 800f4b2 800f47a: 683b ldr r3, [r7, #0] 800f47c: 2b08 cmp r3, #8 800f47e: d104 bne.n 800f48a 800f480: 687b ldr r3, [r7, #4] 800f482: 2202 movs r2, #2 800f484: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f488: e013 b.n 800f4b2 800f48a: 683b ldr r3, [r7, #0] 800f48c: 2b0c cmp r3, #12 800f48e: d104 bne.n 800f49a 800f490: 687b ldr r3, [r7, #4] 800f492: 2202 movs r2, #2 800f494: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f498: e00b b.n 800f4b2 800f49a: 683b ldr r3, [r7, #0] 800f49c: 2b10 cmp r3, #16 800f49e: d104 bne.n 800f4aa 800f4a0: 687b ldr r3, [r7, #4] 800f4a2: 2202 movs r2, #2 800f4a4: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f4a8: e003 b.n 800f4b2 800f4aa: 687b ldr r3, [r7, #4] 800f4ac: 2202 movs r2, #2 800f4ae: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 800f4b2: 687b ldr r3, [r7, #4] 800f4b4: 681b ldr r3, [r3, #0] 800f4b6: 2201 movs r2, #1 800f4b8: 6839 ldr r1, [r7, #0] 800f4ba: 4618 mov r0, r3 800f4bc: f001 f8ae bl 801061c if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800f4c0: 687b ldr r3, [r7, #4] 800f4c2: 681b ldr r3, [r3, #0] 800f4c4: 4a38 ldr r2, [pc, #224] @ (800f5a8 ) 800f4c6: 4293 cmp r3, r2 800f4c8: d013 beq.n 800f4f2 800f4ca: 687b ldr r3, [r7, #4] 800f4cc: 681b ldr r3, [r3, #0] 800f4ce: 4a37 ldr r2, [pc, #220] @ (800f5ac ) 800f4d0: 4293 cmp r3, r2 800f4d2: d00e beq.n 800f4f2 800f4d4: 687b ldr r3, [r7, #4] 800f4d6: 681b ldr r3, [r3, #0] 800f4d8: 4a35 ldr r2, [pc, #212] @ (800f5b0 ) 800f4da: 4293 cmp r3, r2 800f4dc: d009 beq.n 800f4f2 800f4de: 687b ldr r3, [r7, #4] 800f4e0: 681b ldr r3, [r3, #0] 800f4e2: 4a34 ldr r2, [pc, #208] @ (800f5b4 ) 800f4e4: 4293 cmp r3, r2 800f4e6: d004 beq.n 800f4f2 800f4e8: 687b ldr r3, [r7, #4] 800f4ea: 681b ldr r3, [r3, #0] 800f4ec: 4a32 ldr r2, [pc, #200] @ (800f5b8 ) 800f4ee: 4293 cmp r3, r2 800f4f0: d101 bne.n 800f4f6 800f4f2: 2301 movs r3, #1 800f4f4: e000 b.n 800f4f8 800f4f6: 2300 movs r3, #0 800f4f8: 2b00 cmp r3, #0 800f4fa: d007 beq.n 800f50c { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 800f4fc: 687b ldr r3, [r7, #4] 800f4fe: 681b ldr r3, [r3, #0] 800f500: 6c5a ldr r2, [r3, #68] @ 0x44 800f502: 687b ldr r3, [r7, #4] 800f504: 681b ldr r3, [r3, #0] 800f506: f442 4200 orr.w r2, r2, #32768 @ 0x8000 800f50a: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f50c: 687b ldr r3, [r7, #4] 800f50e: 681b ldr r3, [r3, #0] 800f510: 4a25 ldr r2, [pc, #148] @ (800f5a8 ) 800f512: 4293 cmp r3, r2 800f514: d022 beq.n 800f55c 800f516: 687b ldr r3, [r7, #4] 800f518: 681b ldr r3, [r3, #0] 800f51a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f51e: d01d beq.n 800f55c 800f520: 687b ldr r3, [r7, #4] 800f522: 681b ldr r3, [r3, #0] 800f524: 4a25 ldr r2, [pc, #148] @ (800f5bc ) 800f526: 4293 cmp r3, r2 800f528: d018 beq.n 800f55c 800f52a: 687b ldr r3, [r7, #4] 800f52c: 681b ldr r3, [r3, #0] 800f52e: 4a24 ldr r2, [pc, #144] @ (800f5c0 ) 800f530: 4293 cmp r3, r2 800f532: d013 beq.n 800f55c 800f534: 687b ldr r3, [r7, #4] 800f536: 681b ldr r3, [r3, #0] 800f538: 4a22 ldr r2, [pc, #136] @ (800f5c4 ) 800f53a: 4293 cmp r3, r2 800f53c: d00e beq.n 800f55c 800f53e: 687b ldr r3, [r7, #4] 800f540: 681b ldr r3, [r3, #0] 800f542: 4a1a ldr r2, [pc, #104] @ (800f5ac ) 800f544: 4293 cmp r3, r2 800f546: d009 beq.n 800f55c 800f548: 687b ldr r3, [r7, #4] 800f54a: 681b ldr r3, [r3, #0] 800f54c: 4a1e ldr r2, [pc, #120] @ (800f5c8 ) 800f54e: 4293 cmp r3, r2 800f550: d004 beq.n 800f55c 800f552: 687b ldr r3, [r7, #4] 800f554: 681b ldr r3, [r3, #0] 800f556: 4a16 ldr r2, [pc, #88] @ (800f5b0 ) 800f558: 4293 cmp r3, r2 800f55a: d115 bne.n 800f588 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f55c: 687b ldr r3, [r7, #4] 800f55e: 681b ldr r3, [r3, #0] 800f560: 689a ldr r2, [r3, #8] 800f562: 4b1a ldr r3, [pc, #104] @ (800f5cc ) 800f564: 4013 ands r3, r2 800f566: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f568: 68fb ldr r3, [r7, #12] 800f56a: 2b06 cmp r3, #6 800f56c: d015 beq.n 800f59a 800f56e: 68fb ldr r3, [r7, #12] 800f570: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f574: d011 beq.n 800f59a { __HAL_TIM_ENABLE(htim); 800f576: 687b ldr r3, [r7, #4] 800f578: 681b ldr r3, [r3, #0] 800f57a: 681a ldr r2, [r3, #0] 800f57c: 687b ldr r3, [r7, #4] 800f57e: 681b ldr r3, [r3, #0] 800f580: f042 0201 orr.w r2, r2, #1 800f584: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f586: e008 b.n 800f59a } } else { __HAL_TIM_ENABLE(htim); 800f588: 687b ldr r3, [r7, #4] 800f58a: 681b ldr r3, [r3, #0] 800f58c: 681a ldr r2, [r3, #0] 800f58e: 687b ldr r3, [r7, #4] 800f590: 681b ldr r3, [r3, #0] 800f592: f042 0201 orr.w r2, r2, #1 800f596: 601a str r2, [r3, #0] 800f598: e000 b.n 800f59c if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f59a: bf00 nop } /* Return function status */ return HAL_OK; 800f59c: 2300 movs r3, #0 } 800f59e: 4618 mov r0, r3 800f5a0: 3710 adds r7, #16 800f5a2: 46bd mov sp, r7 800f5a4: bd80 pop {r7, pc} 800f5a6: bf00 nop 800f5a8: 40010000 .word 0x40010000 800f5ac: 40010400 .word 0x40010400 800f5b0: 40014000 .word 0x40014000 800f5b4: 40014400 .word 0x40014400 800f5b8: 40014800 .word 0x40014800 800f5bc: 40000400 .word 0x40000400 800f5c0: 40000800 .word 0x40000800 800f5c4: 40000c00 .word 0x40000c00 800f5c8: 40001800 .word 0x40001800 800f5cc: 00010007 .word 0x00010007 0800f5d0 : * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { 800f5d0: b580 push {r7, lr} 800f5d2: b082 sub sp, #8 800f5d4: af00 add r7, sp, #0 800f5d6: 6078 str r0, [r7, #4] 800f5d8: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 800f5da: 687b ldr r3, [r7, #4] 800f5dc: 681b ldr r3, [r3, #0] 800f5de: 2200 movs r2, #0 800f5e0: 6839 ldr r1, [r7, #0] 800f5e2: 4618 mov r0, r3 800f5e4: f001 f81a bl 801061c if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800f5e8: 687b ldr r3, [r7, #4] 800f5ea: 681b ldr r3, [r3, #0] 800f5ec: 4a3e ldr r2, [pc, #248] @ (800f6e8 ) 800f5ee: 4293 cmp r3, r2 800f5f0: d013 beq.n 800f61a 800f5f2: 687b ldr r3, [r7, #4] 800f5f4: 681b ldr r3, [r3, #0] 800f5f6: 4a3d ldr r2, [pc, #244] @ (800f6ec ) 800f5f8: 4293 cmp r3, r2 800f5fa: d00e beq.n 800f61a 800f5fc: 687b ldr r3, [r7, #4] 800f5fe: 681b ldr r3, [r3, #0] 800f600: 4a3b ldr r2, [pc, #236] @ (800f6f0 ) 800f602: 4293 cmp r3, r2 800f604: d009 beq.n 800f61a 800f606: 687b ldr r3, [r7, #4] 800f608: 681b ldr r3, [r3, #0] 800f60a: 4a3a ldr r2, [pc, #232] @ (800f6f4 ) 800f60c: 4293 cmp r3, r2 800f60e: d004 beq.n 800f61a 800f610: 687b ldr r3, [r7, #4] 800f612: 681b ldr r3, [r3, #0] 800f614: 4a38 ldr r2, [pc, #224] @ (800f6f8 ) 800f616: 4293 cmp r3, r2 800f618: d101 bne.n 800f61e 800f61a: 2301 movs r3, #1 800f61c: e000 b.n 800f620 800f61e: 2300 movs r3, #0 800f620: 2b00 cmp r3, #0 800f622: d017 beq.n 800f654 { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); 800f624: 687b ldr r3, [r7, #4] 800f626: 681b ldr r3, [r3, #0] 800f628: 6a1a ldr r2, [r3, #32] 800f62a: f241 1311 movw r3, #4369 @ 0x1111 800f62e: 4013 ands r3, r2 800f630: 2b00 cmp r3, #0 800f632: d10f bne.n 800f654 800f634: 687b ldr r3, [r7, #4] 800f636: 681b ldr r3, [r3, #0] 800f638: 6a1a ldr r2, [r3, #32] 800f63a: f240 4344 movw r3, #1092 @ 0x444 800f63e: 4013 ands r3, r2 800f640: 2b00 cmp r3, #0 800f642: d107 bne.n 800f654 800f644: 687b ldr r3, [r7, #4] 800f646: 681b ldr r3, [r3, #0] 800f648: 6c5a ldr r2, [r3, #68] @ 0x44 800f64a: 687b ldr r3, [r7, #4] 800f64c: 681b ldr r3, [r3, #0] 800f64e: f422 4200 bic.w r2, r2, #32768 @ 0x8000 800f652: 645a str r2, [r3, #68] @ 0x44 } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); 800f654: 687b ldr r3, [r7, #4] 800f656: 681b ldr r3, [r3, #0] 800f658: 6a1a ldr r2, [r3, #32] 800f65a: f241 1311 movw r3, #4369 @ 0x1111 800f65e: 4013 ands r3, r2 800f660: 2b00 cmp r3, #0 800f662: d10f bne.n 800f684 800f664: 687b ldr r3, [r7, #4] 800f666: 681b ldr r3, [r3, #0] 800f668: 6a1a ldr r2, [r3, #32] 800f66a: f240 4344 movw r3, #1092 @ 0x444 800f66e: 4013 ands r3, r2 800f670: 2b00 cmp r3, #0 800f672: d107 bne.n 800f684 800f674: 687b ldr r3, [r7, #4] 800f676: 681b ldr r3, [r3, #0] 800f678: 681a ldr r2, [r3, #0] 800f67a: 687b ldr r3, [r7, #4] 800f67c: 681b ldr r3, [r3, #0] 800f67e: f022 0201 bic.w r2, r2, #1 800f682: 601a str r2, [r3, #0] /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); 800f684: 683b ldr r3, [r7, #0] 800f686: 2b00 cmp r3, #0 800f688: d104 bne.n 800f694 800f68a: 687b ldr r3, [r7, #4] 800f68c: 2201 movs r2, #1 800f68e: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f692: e023 b.n 800f6dc 800f694: 683b ldr r3, [r7, #0] 800f696: 2b04 cmp r3, #4 800f698: d104 bne.n 800f6a4 800f69a: 687b ldr r3, [r7, #4] 800f69c: 2201 movs r2, #1 800f69e: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f6a2: e01b b.n 800f6dc 800f6a4: 683b ldr r3, [r7, #0] 800f6a6: 2b08 cmp r3, #8 800f6a8: d104 bne.n 800f6b4 800f6aa: 687b ldr r3, [r7, #4] 800f6ac: 2201 movs r2, #1 800f6ae: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f6b2: e013 b.n 800f6dc 800f6b4: 683b ldr r3, [r7, #0] 800f6b6: 2b0c cmp r3, #12 800f6b8: d104 bne.n 800f6c4 800f6ba: 687b ldr r3, [r7, #4] 800f6bc: 2201 movs r2, #1 800f6be: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f6c2: e00b b.n 800f6dc 800f6c4: 683b ldr r3, [r7, #0] 800f6c6: 2b10 cmp r3, #16 800f6c8: d104 bne.n 800f6d4 800f6ca: 687b ldr r3, [r7, #4] 800f6cc: 2201 movs r2, #1 800f6ce: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f6d2: e003 b.n 800f6dc 800f6d4: 687b ldr r3, [r7, #4] 800f6d6: 2201 movs r2, #1 800f6d8: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Return function status */ return HAL_OK; 800f6dc: 2300 movs r3, #0 } 800f6de: 4618 mov r0, r3 800f6e0: 3708 adds r7, #8 800f6e2: 46bd mov sp, r7 800f6e4: bd80 pop {r7, pc} 800f6e6: bf00 nop 800f6e8: 40010000 .word 0x40010000 800f6ec: 40010400 .word 0x40010400 800f6f0: 40014000 .word 0x40014000 800f6f4: 40014400 .word 0x40014400 800f6f8: 40014800 .word 0x40014800 0800f6fc : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 800f6fc: b580 push {r7, lr} 800f6fe: b084 sub sp, #16 800f700: af00 add r7, sp, #0 800f702: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 800f704: 687b ldr r3, [r7, #4] 800f706: 681b ldr r3, [r3, #0] 800f708: 68db ldr r3, [r3, #12] 800f70a: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 800f70c: 687b ldr r3, [r7, #4] 800f70e: 681b ldr r3, [r3, #0] 800f710: 691b ldr r3, [r3, #16] 800f712: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 800f714: 68bb ldr r3, [r7, #8] 800f716: f003 0302 and.w r3, r3, #2 800f71a: 2b00 cmp r3, #0 800f71c: d020 beq.n 800f760 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 800f71e: 68fb ldr r3, [r7, #12] 800f720: f003 0302 and.w r3, r3, #2 800f724: 2b00 cmp r3, #0 800f726: d01b beq.n 800f760 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 800f728: 687b ldr r3, [r7, #4] 800f72a: 681b ldr r3, [r3, #0] 800f72c: f06f 0202 mvn.w r2, #2 800f730: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800f732: 687b ldr r3, [r7, #4] 800f734: 2201 movs r2, #1 800f736: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 800f738: 687b ldr r3, [r7, #4] 800f73a: 681b ldr r3, [r3, #0] 800f73c: 699b ldr r3, [r3, #24] 800f73e: f003 0303 and.w r3, r3, #3 800f742: 2b00 cmp r3, #0 800f744: d003 beq.n 800f74e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800f746: 6878 ldr r0, [r7, #4] 800f748: f000 faf6 bl 800fd38 800f74c: e005 b.n 800f75a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800f74e: 6878 ldr r0, [r7, #4] 800f750: f000 fae8 bl 800fd24 HAL_TIM_PWM_PulseFinishedCallback(htim); 800f754: 6878 ldr r0, [r7, #4] 800f756: f000 faf9 bl 800fd4c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800f75a: 687b ldr r3, [r7, #4] 800f75c: 2200 movs r2, #0 800f75e: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 800f760: 68bb ldr r3, [r7, #8] 800f762: f003 0304 and.w r3, r3, #4 800f766: 2b00 cmp r3, #0 800f768: d020 beq.n 800f7ac { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 800f76a: 68fb ldr r3, [r7, #12] 800f76c: f003 0304 and.w r3, r3, #4 800f770: 2b00 cmp r3, #0 800f772: d01b beq.n 800f7ac { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 800f774: 687b ldr r3, [r7, #4] 800f776: 681b ldr r3, [r3, #0] 800f778: f06f 0204 mvn.w r2, #4 800f77c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800f77e: 687b ldr r3, [r7, #4] 800f780: 2202 movs r2, #2 800f782: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 800f784: 687b ldr r3, [r7, #4] 800f786: 681b ldr r3, [r3, #0] 800f788: 699b ldr r3, [r3, #24] 800f78a: f403 7340 and.w r3, r3, #768 @ 0x300 800f78e: 2b00 cmp r3, #0 800f790: d003 beq.n 800f79a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800f792: 6878 ldr r0, [r7, #4] 800f794: f000 fad0 bl 800fd38 800f798: e005 b.n 800f7a6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800f79a: 6878 ldr r0, [r7, #4] 800f79c: f000 fac2 bl 800fd24 HAL_TIM_PWM_PulseFinishedCallback(htim); 800f7a0: 6878 ldr r0, [r7, #4] 800f7a2: f000 fad3 bl 800fd4c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800f7a6: 687b ldr r3, [r7, #4] 800f7a8: 2200 movs r2, #0 800f7aa: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 800f7ac: 68bb ldr r3, [r7, #8] 800f7ae: f003 0308 and.w r3, r3, #8 800f7b2: 2b00 cmp r3, #0 800f7b4: d020 beq.n 800f7f8 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 800f7b6: 68fb ldr r3, [r7, #12] 800f7b8: f003 0308 and.w r3, r3, #8 800f7bc: 2b00 cmp r3, #0 800f7be: d01b beq.n 800f7f8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 800f7c0: 687b ldr r3, [r7, #4] 800f7c2: 681b ldr r3, [r3, #0] 800f7c4: f06f 0208 mvn.w r2, #8 800f7c8: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800f7ca: 687b ldr r3, [r7, #4] 800f7cc: 2204 movs r2, #4 800f7ce: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800f7d0: 687b ldr r3, [r7, #4] 800f7d2: 681b ldr r3, [r3, #0] 800f7d4: 69db ldr r3, [r3, #28] 800f7d6: f003 0303 and.w r3, r3, #3 800f7da: 2b00 cmp r3, #0 800f7dc: d003 beq.n 800f7e6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800f7de: 6878 ldr r0, [r7, #4] 800f7e0: f000 faaa bl 800fd38 800f7e4: e005 b.n 800f7f2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800f7e6: 6878 ldr r0, [r7, #4] 800f7e8: f000 fa9c bl 800fd24 HAL_TIM_PWM_PulseFinishedCallback(htim); 800f7ec: 6878 ldr r0, [r7, #4] 800f7ee: f000 faad bl 800fd4c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800f7f2: 687b ldr r3, [r7, #4] 800f7f4: 2200 movs r2, #0 800f7f6: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 800f7f8: 68bb ldr r3, [r7, #8] 800f7fa: f003 0310 and.w r3, r3, #16 800f7fe: 2b00 cmp r3, #0 800f800: d020 beq.n 800f844 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 800f802: 68fb ldr r3, [r7, #12] 800f804: f003 0310 and.w r3, r3, #16 800f808: 2b00 cmp r3, #0 800f80a: d01b beq.n 800f844 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 800f80c: 687b ldr r3, [r7, #4] 800f80e: 681b ldr r3, [r3, #0] 800f810: f06f 0210 mvn.w r2, #16 800f814: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800f816: 687b ldr r3, [r7, #4] 800f818: 2208 movs r2, #8 800f81a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 800f81c: 687b ldr r3, [r7, #4] 800f81e: 681b ldr r3, [r3, #0] 800f820: 69db ldr r3, [r3, #28] 800f822: f403 7340 and.w r3, r3, #768 @ 0x300 800f826: 2b00 cmp r3, #0 800f828: d003 beq.n 800f832 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800f82a: 6878 ldr r0, [r7, #4] 800f82c: f000 fa84 bl 800fd38 800f830: e005 b.n 800f83e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800f832: 6878 ldr r0, [r7, #4] 800f834: f000 fa76 bl 800fd24 HAL_TIM_PWM_PulseFinishedCallback(htim); 800f838: 6878 ldr r0, [r7, #4] 800f83a: f000 fa87 bl 800fd4c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800f83e: 687b ldr r3, [r7, #4] 800f840: 2200 movs r2, #0 800f842: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 800f844: 68bb ldr r3, [r7, #8] 800f846: f003 0301 and.w r3, r3, #1 800f84a: 2b00 cmp r3, #0 800f84c: d00c beq.n 800f868 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 800f84e: 68fb ldr r3, [r7, #12] 800f850: f003 0301 and.w r3, r3, #1 800f854: 2b00 cmp r3, #0 800f856: d007 beq.n 800f868 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 800f858: 687b ldr r3, [r7, #4] 800f85a: 681b ldr r3, [r3, #0] 800f85c: f06f 0201 mvn.w r2, #1 800f860: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 800f862: 6878 ldr r0, [r7, #4] 800f864: f7f2 f95e bl 8001b24 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800f868: 68bb ldr r3, [r7, #8] 800f86a: f003 0380 and.w r3, r3, #128 @ 0x80 800f86e: 2b00 cmp r3, #0 800f870: d104 bne.n 800f87c ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) 800f872: 68bb ldr r3, [r7, #8] 800f874: f403 5300 and.w r3, r3, #8192 @ 0x2000 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800f878: 2b00 cmp r3, #0 800f87a: d00c beq.n 800f896 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800f87c: 68fb ldr r3, [r7, #12] 800f87e: f003 0380 and.w r3, r3, #128 @ 0x80 800f882: 2b00 cmp r3, #0 800f884: d007 beq.n 800f896 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 800f886: 687b ldr r3, [r7, #4] 800f888: 681b ldr r3, [r3, #0] 800f88a: f46f 5202 mvn.w r2, #8320 @ 0x2080 800f88e: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 800f890: 6878 ldr r0, [r7, #4] 800f892: f000 ffff bl 8010894 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 800f896: 68bb ldr r3, [r7, #8] 800f898: f403 7380 and.w r3, r3, #256 @ 0x100 800f89c: 2b00 cmp r3, #0 800f89e: d00c beq.n 800f8ba { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800f8a0: 68fb ldr r3, [r7, #12] 800f8a2: f003 0380 and.w r3, r3, #128 @ 0x80 800f8a6: 2b00 cmp r3, #0 800f8a8: d007 beq.n 800f8ba { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 800f8aa: 687b ldr r3, [r7, #4] 800f8ac: 681b ldr r3, [r3, #0] 800f8ae: f46f 7280 mvn.w r2, #256 @ 0x100 800f8b2: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 800f8b4: 6878 ldr r0, [r7, #4] 800f8b6: f000 fff7 bl 80108a8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 800f8ba: 68bb ldr r3, [r7, #8] 800f8bc: f003 0340 and.w r3, r3, #64 @ 0x40 800f8c0: 2b00 cmp r3, #0 800f8c2: d00c beq.n 800f8de { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 800f8c4: 68fb ldr r3, [r7, #12] 800f8c6: f003 0340 and.w r3, r3, #64 @ 0x40 800f8ca: 2b00 cmp r3, #0 800f8cc: d007 beq.n 800f8de { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 800f8ce: 687b ldr r3, [r7, #4] 800f8d0: 681b ldr r3, [r3, #0] 800f8d2: f06f 0240 mvn.w r2, #64 @ 0x40 800f8d6: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 800f8d8: 6878 ldr r0, [r7, #4] 800f8da: f000 fa41 bl 800fd60 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 800f8de: 68bb ldr r3, [r7, #8] 800f8e0: f003 0320 and.w r3, r3, #32 800f8e4: 2b00 cmp r3, #0 800f8e6: d00c beq.n 800f902 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 800f8e8: 68fb ldr r3, [r7, #12] 800f8ea: f003 0320 and.w r3, r3, #32 800f8ee: 2b00 cmp r3, #0 800f8f0: d007 beq.n 800f902 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 800f8f2: 687b ldr r3, [r7, #4] 800f8f4: 681b ldr r3, [r3, #0] 800f8f6: f06f 0220 mvn.w r2, #32 800f8fa: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 800f8fc: 6878 ldr r0, [r7, #4] 800f8fe: f000 ffbf bl 8010880 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 800f902: bf00 nop 800f904: 3710 adds r7, #16 800f906: 46bd mov sp, r7 800f908: bd80 pop {r7, pc} ... 0800f90c : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 800f90c: b580 push {r7, lr} 800f90e: b086 sub sp, #24 800f910: af00 add r7, sp, #0 800f912: 60f8 str r0, [r7, #12] 800f914: 60b9 str r1, [r7, #8] 800f916: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800f918: 2300 movs r3, #0 800f91a: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 800f91c: 68fb ldr r3, [r7, #12] 800f91e: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800f922: 2b01 cmp r3, #1 800f924: d101 bne.n 800f92a 800f926: 2302 movs r3, #2 800f928: e0ff b.n 800fb2a 800f92a: 68fb ldr r3, [r7, #12] 800f92c: 2201 movs r2, #1 800f92e: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 800f932: 687b ldr r3, [r7, #4] 800f934: 2b14 cmp r3, #20 800f936: f200 80f0 bhi.w 800fb1a 800f93a: a201 add r2, pc, #4 @ (adr r2, 800f940 ) 800f93c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800f940: 0800f995 .word 0x0800f995 800f944: 0800fb1b .word 0x0800fb1b 800f948: 0800fb1b .word 0x0800fb1b 800f94c: 0800fb1b .word 0x0800fb1b 800f950: 0800f9d5 .word 0x0800f9d5 800f954: 0800fb1b .word 0x0800fb1b 800f958: 0800fb1b .word 0x0800fb1b 800f95c: 0800fb1b .word 0x0800fb1b 800f960: 0800fa17 .word 0x0800fa17 800f964: 0800fb1b .word 0x0800fb1b 800f968: 0800fb1b .word 0x0800fb1b 800f96c: 0800fb1b .word 0x0800fb1b 800f970: 0800fa57 .word 0x0800fa57 800f974: 0800fb1b .word 0x0800fb1b 800f978: 0800fb1b .word 0x0800fb1b 800f97c: 0800fb1b .word 0x0800fb1b 800f980: 0800fa99 .word 0x0800fa99 800f984: 0800fb1b .word 0x0800fb1b 800f988: 0800fb1b .word 0x0800fb1b 800f98c: 0800fb1b .word 0x0800fb1b 800f990: 0800fad9 .word 0x0800fad9 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 800f994: 68fb ldr r3, [r7, #12] 800f996: 681b ldr r3, [r3, #0] 800f998: 68b9 ldr r1, [r7, #8] 800f99a: 4618 mov r0, r3 800f99c: f000 faca bl 800ff34 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 800f9a0: 68fb ldr r3, [r7, #12] 800f9a2: 681b ldr r3, [r3, #0] 800f9a4: 699a ldr r2, [r3, #24] 800f9a6: 68fb ldr r3, [r7, #12] 800f9a8: 681b ldr r3, [r3, #0] 800f9aa: f042 0208 orr.w r2, r2, #8 800f9ae: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 800f9b0: 68fb ldr r3, [r7, #12] 800f9b2: 681b ldr r3, [r3, #0] 800f9b4: 699a ldr r2, [r3, #24] 800f9b6: 68fb ldr r3, [r7, #12] 800f9b8: 681b ldr r3, [r3, #0] 800f9ba: f022 0204 bic.w r2, r2, #4 800f9be: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 800f9c0: 68fb ldr r3, [r7, #12] 800f9c2: 681b ldr r3, [r3, #0] 800f9c4: 6999 ldr r1, [r3, #24] 800f9c6: 68bb ldr r3, [r7, #8] 800f9c8: 691a ldr r2, [r3, #16] 800f9ca: 68fb ldr r3, [r7, #12] 800f9cc: 681b ldr r3, [r3, #0] 800f9ce: 430a orrs r2, r1 800f9d0: 619a str r2, [r3, #24] break; 800f9d2: e0a5 b.n 800fb20 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 800f9d4: 68fb ldr r3, [r7, #12] 800f9d6: 681b ldr r3, [r3, #0] 800f9d8: 68b9 ldr r1, [r7, #8] 800f9da: 4618 mov r0, r3 800f9dc: f000 fb3a bl 8010054 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 800f9e0: 68fb ldr r3, [r7, #12] 800f9e2: 681b ldr r3, [r3, #0] 800f9e4: 699a ldr r2, [r3, #24] 800f9e6: 68fb ldr r3, [r7, #12] 800f9e8: 681b ldr r3, [r3, #0] 800f9ea: f442 6200 orr.w r2, r2, #2048 @ 0x800 800f9ee: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 800f9f0: 68fb ldr r3, [r7, #12] 800f9f2: 681b ldr r3, [r3, #0] 800f9f4: 699a ldr r2, [r3, #24] 800f9f6: 68fb ldr r3, [r7, #12] 800f9f8: 681b ldr r3, [r3, #0] 800f9fa: f422 6280 bic.w r2, r2, #1024 @ 0x400 800f9fe: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 800fa00: 68fb ldr r3, [r7, #12] 800fa02: 681b ldr r3, [r3, #0] 800fa04: 6999 ldr r1, [r3, #24] 800fa06: 68bb ldr r3, [r7, #8] 800fa08: 691b ldr r3, [r3, #16] 800fa0a: 021a lsls r2, r3, #8 800fa0c: 68fb ldr r3, [r7, #12] 800fa0e: 681b ldr r3, [r3, #0] 800fa10: 430a orrs r2, r1 800fa12: 619a str r2, [r3, #24] break; 800fa14: e084 b.n 800fb20 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 800fa16: 68fb ldr r3, [r7, #12] 800fa18: 681b ldr r3, [r3, #0] 800fa1a: 68b9 ldr r1, [r7, #8] 800fa1c: 4618 mov r0, r3 800fa1e: f000 fba3 bl 8010168 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 800fa22: 68fb ldr r3, [r7, #12] 800fa24: 681b ldr r3, [r3, #0] 800fa26: 69da ldr r2, [r3, #28] 800fa28: 68fb ldr r3, [r7, #12] 800fa2a: 681b ldr r3, [r3, #0] 800fa2c: f042 0208 orr.w r2, r2, #8 800fa30: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 800fa32: 68fb ldr r3, [r7, #12] 800fa34: 681b ldr r3, [r3, #0] 800fa36: 69da ldr r2, [r3, #28] 800fa38: 68fb ldr r3, [r7, #12] 800fa3a: 681b ldr r3, [r3, #0] 800fa3c: f022 0204 bic.w r2, r2, #4 800fa40: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 800fa42: 68fb ldr r3, [r7, #12] 800fa44: 681b ldr r3, [r3, #0] 800fa46: 69d9 ldr r1, [r3, #28] 800fa48: 68bb ldr r3, [r7, #8] 800fa4a: 691a ldr r2, [r3, #16] 800fa4c: 68fb ldr r3, [r7, #12] 800fa4e: 681b ldr r3, [r3, #0] 800fa50: 430a orrs r2, r1 800fa52: 61da str r2, [r3, #28] break; 800fa54: e064 b.n 800fb20 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 800fa56: 68fb ldr r3, [r7, #12] 800fa58: 681b ldr r3, [r3, #0] 800fa5a: 68b9 ldr r1, [r7, #8] 800fa5c: 4618 mov r0, r3 800fa5e: f000 fc0b bl 8010278 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 800fa62: 68fb ldr r3, [r7, #12] 800fa64: 681b ldr r3, [r3, #0] 800fa66: 69da ldr r2, [r3, #28] 800fa68: 68fb ldr r3, [r7, #12] 800fa6a: 681b ldr r3, [r3, #0] 800fa6c: f442 6200 orr.w r2, r2, #2048 @ 0x800 800fa70: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 800fa72: 68fb ldr r3, [r7, #12] 800fa74: 681b ldr r3, [r3, #0] 800fa76: 69da ldr r2, [r3, #28] 800fa78: 68fb ldr r3, [r7, #12] 800fa7a: 681b ldr r3, [r3, #0] 800fa7c: f422 6280 bic.w r2, r2, #1024 @ 0x400 800fa80: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 800fa82: 68fb ldr r3, [r7, #12] 800fa84: 681b ldr r3, [r3, #0] 800fa86: 69d9 ldr r1, [r3, #28] 800fa88: 68bb ldr r3, [r7, #8] 800fa8a: 691b ldr r3, [r3, #16] 800fa8c: 021a lsls r2, r3, #8 800fa8e: 68fb ldr r3, [r7, #12] 800fa90: 681b ldr r3, [r3, #0] 800fa92: 430a orrs r2, r1 800fa94: 61da str r2, [r3, #28] break; 800fa96: e043 b.n 800fb20 { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); 800fa98: 68fb ldr r3, [r7, #12] 800fa9a: 681b ldr r3, [r3, #0] 800fa9c: 68b9 ldr r1, [r7, #8] 800fa9e: 4618 mov r0, r3 800faa0: f000 fc54 bl 801034c /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 800faa4: 68fb ldr r3, [r7, #12] 800faa6: 681b ldr r3, [r3, #0] 800faa8: 6d5a ldr r2, [r3, #84] @ 0x54 800faaa: 68fb ldr r3, [r7, #12] 800faac: 681b ldr r3, [r3, #0] 800faae: f042 0208 orr.w r2, r2, #8 800fab2: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 800fab4: 68fb ldr r3, [r7, #12] 800fab6: 681b ldr r3, [r3, #0] 800fab8: 6d5a ldr r2, [r3, #84] @ 0x54 800faba: 68fb ldr r3, [r7, #12] 800fabc: 681b ldr r3, [r3, #0] 800fabe: f022 0204 bic.w r2, r2, #4 800fac2: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; 800fac4: 68fb ldr r3, [r7, #12] 800fac6: 681b ldr r3, [r3, #0] 800fac8: 6d59 ldr r1, [r3, #84] @ 0x54 800faca: 68bb ldr r3, [r7, #8] 800facc: 691a ldr r2, [r3, #16] 800face: 68fb ldr r3, [r7, #12] 800fad0: 681b ldr r3, [r3, #0] 800fad2: 430a orrs r2, r1 800fad4: 655a str r2, [r3, #84] @ 0x54 break; 800fad6: e023 b.n 800fb20 { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); 800fad8: 68fb ldr r3, [r7, #12] 800fada: 681b ldr r3, [r3, #0] 800fadc: 68b9 ldr r1, [r7, #8] 800fade: 4618 mov r0, r3 800fae0: f000 fc98 bl 8010414 /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 800fae4: 68fb ldr r3, [r7, #12] 800fae6: 681b ldr r3, [r3, #0] 800fae8: 6d5a ldr r2, [r3, #84] @ 0x54 800faea: 68fb ldr r3, [r7, #12] 800faec: 681b ldr r3, [r3, #0] 800faee: f442 6200 orr.w r2, r2, #2048 @ 0x800 800faf2: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 800faf4: 68fb ldr r3, [r7, #12] 800faf6: 681b ldr r3, [r3, #0] 800faf8: 6d5a ldr r2, [r3, #84] @ 0x54 800fafa: 68fb ldr r3, [r7, #12] 800fafc: 681b ldr r3, [r3, #0] 800fafe: f422 6280 bic.w r2, r2, #1024 @ 0x400 800fb02: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 800fb04: 68fb ldr r3, [r7, #12] 800fb06: 681b ldr r3, [r3, #0] 800fb08: 6d59 ldr r1, [r3, #84] @ 0x54 800fb0a: 68bb ldr r3, [r7, #8] 800fb0c: 691b ldr r3, [r3, #16] 800fb0e: 021a lsls r2, r3, #8 800fb10: 68fb ldr r3, [r7, #12] 800fb12: 681b ldr r3, [r3, #0] 800fb14: 430a orrs r2, r1 800fb16: 655a str r2, [r3, #84] @ 0x54 break; 800fb18: e002 b.n 800fb20 } default: status = HAL_ERROR; 800fb1a: 2301 movs r3, #1 800fb1c: 75fb strb r3, [r7, #23] break; 800fb1e: bf00 nop } __HAL_UNLOCK(htim); 800fb20: 68fb ldr r3, [r7, #12] 800fb22: 2200 movs r2, #0 800fb24: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 800fb28: 7dfb ldrb r3, [r7, #23] } 800fb2a: 4618 mov r0, r3 800fb2c: 3718 adds r7, #24 800fb2e: 46bd mov sp, r7 800fb30: bd80 pop {r7, pc} 800fb32: bf00 nop 0800fb34 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 800fb34: b580 push {r7, lr} 800fb36: b084 sub sp, #16 800fb38: af00 add r7, sp, #0 800fb3a: 6078 str r0, [r7, #4] 800fb3c: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800fb3e: 2300 movs r3, #0 800fb40: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 800fb42: 687b ldr r3, [r7, #4] 800fb44: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800fb48: 2b01 cmp r3, #1 800fb4a: d101 bne.n 800fb50 800fb4c: 2302 movs r3, #2 800fb4e: e0dc b.n 800fd0a 800fb50: 687b ldr r3, [r7, #4] 800fb52: 2201 movs r2, #1 800fb54: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 800fb58: 687b ldr r3, [r7, #4] 800fb5a: 2202 movs r2, #2 800fb5c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 800fb60: 687b ldr r3, [r7, #4] 800fb62: 681b ldr r3, [r3, #0] 800fb64: 689b ldr r3, [r3, #8] 800fb66: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 800fb68: 68ba ldr r2, [r7, #8] 800fb6a: 4b6a ldr r3, [pc, #424] @ (800fd14 ) 800fb6c: 4013 ands r3, r2 800fb6e: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 800fb70: 68bb ldr r3, [r7, #8] 800fb72: f423 437f bic.w r3, r3, #65280 @ 0xff00 800fb76: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 800fb78: 687b ldr r3, [r7, #4] 800fb7a: 681b ldr r3, [r3, #0] 800fb7c: 68ba ldr r2, [r7, #8] 800fb7e: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 800fb80: 683b ldr r3, [r7, #0] 800fb82: 681b ldr r3, [r3, #0] 800fb84: 4a64 ldr r2, [pc, #400] @ (800fd18 ) 800fb86: 4293 cmp r3, r2 800fb88: f000 80a9 beq.w 800fcde 800fb8c: 4a62 ldr r2, [pc, #392] @ (800fd18 ) 800fb8e: 4293 cmp r3, r2 800fb90: f200 80ae bhi.w 800fcf0 800fb94: 4a61 ldr r2, [pc, #388] @ (800fd1c ) 800fb96: 4293 cmp r3, r2 800fb98: f000 80a1 beq.w 800fcde 800fb9c: 4a5f ldr r2, [pc, #380] @ (800fd1c ) 800fb9e: 4293 cmp r3, r2 800fba0: f200 80a6 bhi.w 800fcf0 800fba4: 4a5e ldr r2, [pc, #376] @ (800fd20 ) 800fba6: 4293 cmp r3, r2 800fba8: f000 8099 beq.w 800fcde 800fbac: 4a5c ldr r2, [pc, #368] @ (800fd20 ) 800fbae: 4293 cmp r3, r2 800fbb0: f200 809e bhi.w 800fcf0 800fbb4: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 800fbb8: f000 8091 beq.w 800fcde 800fbbc: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 800fbc0: f200 8096 bhi.w 800fcf0 800fbc4: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800fbc8: f000 8089 beq.w 800fcde 800fbcc: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800fbd0: f200 808e bhi.w 800fcf0 800fbd4: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800fbd8: d03e beq.n 800fc58 800fbda: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800fbde: f200 8087 bhi.w 800fcf0 800fbe2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800fbe6: f000 8086 beq.w 800fcf6 800fbea: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800fbee: d87f bhi.n 800fcf0 800fbf0: 2b70 cmp r3, #112 @ 0x70 800fbf2: d01a beq.n 800fc2a 800fbf4: 2b70 cmp r3, #112 @ 0x70 800fbf6: d87b bhi.n 800fcf0 800fbf8: 2b60 cmp r3, #96 @ 0x60 800fbfa: d050 beq.n 800fc9e 800fbfc: 2b60 cmp r3, #96 @ 0x60 800fbfe: d877 bhi.n 800fcf0 800fc00: 2b50 cmp r3, #80 @ 0x50 800fc02: d03c beq.n 800fc7e 800fc04: 2b50 cmp r3, #80 @ 0x50 800fc06: d873 bhi.n 800fcf0 800fc08: 2b40 cmp r3, #64 @ 0x40 800fc0a: d058 beq.n 800fcbe 800fc0c: 2b40 cmp r3, #64 @ 0x40 800fc0e: d86f bhi.n 800fcf0 800fc10: 2b30 cmp r3, #48 @ 0x30 800fc12: d064 beq.n 800fcde 800fc14: 2b30 cmp r3, #48 @ 0x30 800fc16: d86b bhi.n 800fcf0 800fc18: 2b20 cmp r3, #32 800fc1a: d060 beq.n 800fcde 800fc1c: 2b20 cmp r3, #32 800fc1e: d867 bhi.n 800fcf0 800fc20: 2b00 cmp r3, #0 800fc22: d05c beq.n 800fcde 800fc24: 2b10 cmp r3, #16 800fc26: d05a beq.n 800fcde 800fc28: e062 b.n 800fcf0 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 800fc2a: 687b ldr r3, [r7, #4] 800fc2c: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 800fc2e: 683b ldr r3, [r7, #0] 800fc30: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 800fc32: 683b ldr r3, [r7, #0] 800fc34: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 800fc36: 683b ldr r3, [r7, #0] 800fc38: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 800fc3a: f000 fccf bl 80105dc /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 800fc3e: 687b ldr r3, [r7, #4] 800fc40: 681b ldr r3, [r3, #0] 800fc42: 689b ldr r3, [r3, #8] 800fc44: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 800fc46: 68bb ldr r3, [r7, #8] 800fc48: f043 0377 orr.w r3, r3, #119 @ 0x77 800fc4c: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800fc4e: 687b ldr r3, [r7, #4] 800fc50: 681b ldr r3, [r3, #0] 800fc52: 68ba ldr r2, [r7, #8] 800fc54: 609a str r2, [r3, #8] break; 800fc56: e04f b.n 800fcf8 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 800fc58: 687b ldr r3, [r7, #4] 800fc5a: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 800fc5c: 683b ldr r3, [r7, #0] 800fc5e: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 800fc60: 683b ldr r3, [r7, #0] 800fc62: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 800fc64: 683b ldr r3, [r7, #0] 800fc66: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 800fc68: f000 fcb8 bl 80105dc /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 800fc6c: 687b ldr r3, [r7, #4] 800fc6e: 681b ldr r3, [r3, #0] 800fc70: 689a ldr r2, [r3, #8] 800fc72: 687b ldr r3, [r7, #4] 800fc74: 681b ldr r3, [r3, #0] 800fc76: f442 4280 orr.w r2, r2, #16384 @ 0x4000 800fc7a: 609a str r2, [r3, #8] break; 800fc7c: e03c b.n 800fcf8 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 800fc7e: 687b ldr r3, [r7, #4] 800fc80: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800fc82: 683b ldr r3, [r7, #0] 800fc84: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800fc86: 683b ldr r3, [r7, #0] 800fc88: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 800fc8a: 461a mov r2, r3 800fc8c: f000 fc28 bl 80104e0 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 800fc90: 687b ldr r3, [r7, #4] 800fc92: 681b ldr r3, [r3, #0] 800fc94: 2150 movs r1, #80 @ 0x50 800fc96: 4618 mov r0, r3 800fc98: f000 fc82 bl 80105a0 break; 800fc9c: e02c b.n 800fcf8 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 800fc9e: 687b ldr r3, [r7, #4] 800fca0: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800fca2: 683b ldr r3, [r7, #0] 800fca4: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800fca6: 683b ldr r3, [r7, #0] 800fca8: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 800fcaa: 461a mov r2, r3 800fcac: f000 fc47 bl 801053e TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 800fcb0: 687b ldr r3, [r7, #4] 800fcb2: 681b ldr r3, [r3, #0] 800fcb4: 2160 movs r1, #96 @ 0x60 800fcb6: 4618 mov r0, r3 800fcb8: f000 fc72 bl 80105a0 break; 800fcbc: e01c b.n 800fcf8 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 800fcbe: 687b ldr r3, [r7, #4] 800fcc0: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800fcc2: 683b ldr r3, [r7, #0] 800fcc4: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800fcc6: 683b ldr r3, [r7, #0] 800fcc8: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 800fcca: 461a mov r2, r3 800fccc: f000 fc08 bl 80104e0 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 800fcd0: 687b ldr r3, [r7, #4] 800fcd2: 681b ldr r3, [r3, #0] 800fcd4: 2140 movs r1, #64 @ 0x40 800fcd6: 4618 mov r0, r3 800fcd8: f000 fc62 bl 80105a0 break; 800fcdc: e00c b.n 800fcf8 case TIM_CLOCKSOURCE_ITR8: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 800fcde: 687b ldr r3, [r7, #4] 800fce0: 681a ldr r2, [r3, #0] 800fce2: 683b ldr r3, [r7, #0] 800fce4: 681b ldr r3, [r3, #0] 800fce6: 4619 mov r1, r3 800fce8: 4610 mov r0, r2 800fcea: f000 fc59 bl 80105a0 break; 800fcee: e003 b.n 800fcf8 } default: status = HAL_ERROR; 800fcf0: 2301 movs r3, #1 800fcf2: 73fb strb r3, [r7, #15] break; 800fcf4: e000 b.n 800fcf8 break; 800fcf6: bf00 nop } htim->State = HAL_TIM_STATE_READY; 800fcf8: 687b ldr r3, [r7, #4] 800fcfa: 2201 movs r2, #1 800fcfc: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 800fd00: 687b ldr r3, [r7, #4] 800fd02: 2200 movs r2, #0 800fd04: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 800fd08: 7bfb ldrb r3, [r7, #15] } 800fd0a: 4618 mov r0, r3 800fd0c: 3710 adds r7, #16 800fd0e: 46bd mov sp, r7 800fd10: bd80 pop {r7, pc} 800fd12: bf00 nop 800fd14: ffceff88 .word 0xffceff88 800fd18: 00100040 .word 0x00100040 800fd1c: 00100030 .word 0x00100030 800fd20: 00100020 .word 0x00100020 0800fd24 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 800fd24: b480 push {r7} 800fd26: b083 sub sp, #12 800fd28: af00 add r7, sp, #0 800fd2a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 800fd2c: bf00 nop 800fd2e: 370c adds r7, #12 800fd30: 46bd mov sp, r7 800fd32: f85d 7b04 ldr.w r7, [sp], #4 800fd36: 4770 bx lr 0800fd38 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 800fd38: b480 push {r7} 800fd3a: b083 sub sp, #12 800fd3c: af00 add r7, sp, #0 800fd3e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 800fd40: bf00 nop 800fd42: 370c adds r7, #12 800fd44: 46bd mov sp, r7 800fd46: f85d 7b04 ldr.w r7, [sp], #4 800fd4a: 4770 bx lr 0800fd4c : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 800fd4c: b480 push {r7} 800fd4e: b083 sub sp, #12 800fd50: af00 add r7, sp, #0 800fd52: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 800fd54: bf00 nop 800fd56: 370c adds r7, #12 800fd58: 46bd mov sp, r7 800fd5a: f85d 7b04 ldr.w r7, [sp], #4 800fd5e: 4770 bx lr 0800fd60 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 800fd60: b480 push {r7} 800fd62: b083 sub sp, #12 800fd64: af00 add r7, sp, #0 800fd66: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 800fd68: bf00 nop 800fd6a: 370c adds r7, #12 800fd6c: 46bd mov sp, r7 800fd6e: f85d 7b04 ldr.w r7, [sp], #4 800fd72: 4770 bx lr 0800fd74 : * @arg TIM_CHANNEL_5: TIM Channel 5 * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) { 800fd74: b480 push {r7} 800fd76: b085 sub sp, #20 800fd78: af00 add r7, sp, #0 800fd7a: 6078 str r0, [r7, #4] 800fd7c: 6039 str r1, [r7, #0] HAL_TIM_ChannelStateTypeDef channel_state; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); 800fd7e: 683b ldr r3, [r7, #0] 800fd80: 2b00 cmp r3, #0 800fd82: d104 bne.n 800fd8e 800fd84: 687b ldr r3, [r7, #4] 800fd86: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800fd8a: b2db uxtb r3, r3 800fd8c: e023 b.n 800fdd6 800fd8e: 683b ldr r3, [r7, #0] 800fd90: 2b04 cmp r3, #4 800fd92: d104 bne.n 800fd9e 800fd94: 687b ldr r3, [r7, #4] 800fd96: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800fd9a: b2db uxtb r3, r3 800fd9c: e01b b.n 800fdd6 800fd9e: 683b ldr r3, [r7, #0] 800fda0: 2b08 cmp r3, #8 800fda2: d104 bne.n 800fdae 800fda4: 687b ldr r3, [r7, #4] 800fda6: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800fdaa: b2db uxtb r3, r3 800fdac: e013 b.n 800fdd6 800fdae: 683b ldr r3, [r7, #0] 800fdb0: 2b0c cmp r3, #12 800fdb2: d104 bne.n 800fdbe 800fdb4: 687b ldr r3, [r7, #4] 800fdb6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800fdba: b2db uxtb r3, r3 800fdbc: e00b b.n 800fdd6 800fdbe: 683b ldr r3, [r7, #0] 800fdc0: 2b10 cmp r3, #16 800fdc2: d104 bne.n 800fdce 800fdc4: 687b ldr r3, [r7, #4] 800fdc6: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800fdca: b2db uxtb r3, r3 800fdcc: e003 b.n 800fdd6 800fdce: 687b ldr r3, [r7, #4] 800fdd0: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800fdd4: b2db uxtb r3, r3 800fdd6: 73fb strb r3, [r7, #15] return channel_state; 800fdd8: 7bfb ldrb r3, [r7, #15] } 800fdda: 4618 mov r0, r3 800fddc: 3714 adds r7, #20 800fdde: 46bd mov sp, r7 800fde0: f85d 7b04 ldr.w r7, [sp], #4 800fde4: 4770 bx lr ... 0800fde8 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 800fde8: b480 push {r7} 800fdea: b085 sub sp, #20 800fdec: af00 add r7, sp, #0 800fdee: 6078 str r0, [r7, #4] 800fdf0: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 800fdf2: 687b ldr r3, [r7, #4] 800fdf4: 681b ldr r3, [r3, #0] 800fdf6: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 800fdf8: 687b ldr r3, [r7, #4] 800fdfa: 4a46 ldr r2, [pc, #280] @ (800ff14 ) 800fdfc: 4293 cmp r3, r2 800fdfe: d013 beq.n 800fe28 800fe00: 687b ldr r3, [r7, #4] 800fe02: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800fe06: d00f beq.n 800fe28 800fe08: 687b ldr r3, [r7, #4] 800fe0a: 4a43 ldr r2, [pc, #268] @ (800ff18 ) 800fe0c: 4293 cmp r3, r2 800fe0e: d00b beq.n 800fe28 800fe10: 687b ldr r3, [r7, #4] 800fe12: 4a42 ldr r2, [pc, #264] @ (800ff1c ) 800fe14: 4293 cmp r3, r2 800fe16: d007 beq.n 800fe28 800fe18: 687b ldr r3, [r7, #4] 800fe1a: 4a41 ldr r2, [pc, #260] @ (800ff20 ) 800fe1c: 4293 cmp r3, r2 800fe1e: d003 beq.n 800fe28 800fe20: 687b ldr r3, [r7, #4] 800fe22: 4a40 ldr r2, [pc, #256] @ (800ff24 ) 800fe24: 4293 cmp r3, r2 800fe26: d108 bne.n 800fe3a { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 800fe28: 68fb ldr r3, [r7, #12] 800fe2a: f023 0370 bic.w r3, r3, #112 @ 0x70 800fe2e: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 800fe30: 683b ldr r3, [r7, #0] 800fe32: 685b ldr r3, [r3, #4] 800fe34: 68fa ldr r2, [r7, #12] 800fe36: 4313 orrs r3, r2 800fe38: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800fe3a: 687b ldr r3, [r7, #4] 800fe3c: 4a35 ldr r2, [pc, #212] @ (800ff14 ) 800fe3e: 4293 cmp r3, r2 800fe40: d01f beq.n 800fe82 800fe42: 687b ldr r3, [r7, #4] 800fe44: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800fe48: d01b beq.n 800fe82 800fe4a: 687b ldr r3, [r7, #4] 800fe4c: 4a32 ldr r2, [pc, #200] @ (800ff18 ) 800fe4e: 4293 cmp r3, r2 800fe50: d017 beq.n 800fe82 800fe52: 687b ldr r3, [r7, #4] 800fe54: 4a31 ldr r2, [pc, #196] @ (800ff1c ) 800fe56: 4293 cmp r3, r2 800fe58: d013 beq.n 800fe82 800fe5a: 687b ldr r3, [r7, #4] 800fe5c: 4a30 ldr r2, [pc, #192] @ (800ff20 ) 800fe5e: 4293 cmp r3, r2 800fe60: d00f beq.n 800fe82 800fe62: 687b ldr r3, [r7, #4] 800fe64: 4a2f ldr r2, [pc, #188] @ (800ff24 ) 800fe66: 4293 cmp r3, r2 800fe68: d00b beq.n 800fe82 800fe6a: 687b ldr r3, [r7, #4] 800fe6c: 4a2e ldr r2, [pc, #184] @ (800ff28 ) 800fe6e: 4293 cmp r3, r2 800fe70: d007 beq.n 800fe82 800fe72: 687b ldr r3, [r7, #4] 800fe74: 4a2d ldr r2, [pc, #180] @ (800ff2c ) 800fe76: 4293 cmp r3, r2 800fe78: d003 beq.n 800fe82 800fe7a: 687b ldr r3, [r7, #4] 800fe7c: 4a2c ldr r2, [pc, #176] @ (800ff30 ) 800fe7e: 4293 cmp r3, r2 800fe80: d108 bne.n 800fe94 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800fe82: 68fb ldr r3, [r7, #12] 800fe84: f423 7340 bic.w r3, r3, #768 @ 0x300 800fe88: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 800fe8a: 683b ldr r3, [r7, #0] 800fe8c: 68db ldr r3, [r3, #12] 800fe8e: 68fa ldr r2, [r7, #12] 800fe90: 4313 orrs r3, r2 800fe92: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 800fe94: 68fb ldr r3, [r7, #12] 800fe96: f023 0280 bic.w r2, r3, #128 @ 0x80 800fe9a: 683b ldr r3, [r7, #0] 800fe9c: 695b ldr r3, [r3, #20] 800fe9e: 4313 orrs r3, r2 800fea0: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 800fea2: 687b ldr r3, [r7, #4] 800fea4: 68fa ldr r2, [r7, #12] 800fea6: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 800fea8: 683b ldr r3, [r7, #0] 800feaa: 689a ldr r2, [r3, #8] 800feac: 687b ldr r3, [r7, #4] 800feae: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 800feb0: 683b ldr r3, [r7, #0] 800feb2: 681a ldr r2, [r3, #0] 800feb4: 687b ldr r3, [r7, #4] 800feb6: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800feb8: 687b ldr r3, [r7, #4] 800feba: 4a16 ldr r2, [pc, #88] @ (800ff14 ) 800febc: 4293 cmp r3, r2 800febe: d00f beq.n 800fee0 800fec0: 687b ldr r3, [r7, #4] 800fec2: 4a18 ldr r2, [pc, #96] @ (800ff24 ) 800fec4: 4293 cmp r3, r2 800fec6: d00b beq.n 800fee0 800fec8: 687b ldr r3, [r7, #4] 800feca: 4a17 ldr r2, [pc, #92] @ (800ff28 ) 800fecc: 4293 cmp r3, r2 800fece: d007 beq.n 800fee0 800fed0: 687b ldr r3, [r7, #4] 800fed2: 4a16 ldr r2, [pc, #88] @ (800ff2c ) 800fed4: 4293 cmp r3, r2 800fed6: d003 beq.n 800fee0 800fed8: 687b ldr r3, [r7, #4] 800feda: 4a15 ldr r2, [pc, #84] @ (800ff30 ) 800fedc: 4293 cmp r3, r2 800fede: d103 bne.n 800fee8 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 800fee0: 683b ldr r3, [r7, #0] 800fee2: 691a ldr r2, [r3, #16] 800fee4: 687b ldr r3, [r7, #4] 800fee6: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 800fee8: 687b ldr r3, [r7, #4] 800feea: 2201 movs r2, #1 800feec: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 800feee: 687b ldr r3, [r7, #4] 800fef0: 691b ldr r3, [r3, #16] 800fef2: f003 0301 and.w r3, r3, #1 800fef6: 2b01 cmp r3, #1 800fef8: d105 bne.n 800ff06 { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 800fefa: 687b ldr r3, [r7, #4] 800fefc: 691b ldr r3, [r3, #16] 800fefe: f023 0201 bic.w r2, r3, #1 800ff02: 687b ldr r3, [r7, #4] 800ff04: 611a str r2, [r3, #16] } } 800ff06: bf00 nop 800ff08: 3714 adds r7, #20 800ff0a: 46bd mov sp, r7 800ff0c: f85d 7b04 ldr.w r7, [sp], #4 800ff10: 4770 bx lr 800ff12: bf00 nop 800ff14: 40010000 .word 0x40010000 800ff18: 40000400 .word 0x40000400 800ff1c: 40000800 .word 0x40000800 800ff20: 40000c00 .word 0x40000c00 800ff24: 40010400 .word 0x40010400 800ff28: 40014000 .word 0x40014000 800ff2c: 40014400 .word 0x40014400 800ff30: 40014800 .word 0x40014800 0800ff34 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800ff34: b480 push {r7} 800ff36: b087 sub sp, #28 800ff38: af00 add r7, sp, #0 800ff3a: 6078 str r0, [r7, #4] 800ff3c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800ff3e: 687b ldr r3, [r7, #4] 800ff40: 6a1b ldr r3, [r3, #32] 800ff42: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 800ff44: 687b ldr r3, [r7, #4] 800ff46: 6a1b ldr r3, [r3, #32] 800ff48: f023 0201 bic.w r2, r3, #1 800ff4c: 687b ldr r3, [r7, #4] 800ff4e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800ff50: 687b ldr r3, [r7, #4] 800ff52: 685b ldr r3, [r3, #4] 800ff54: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 800ff56: 687b ldr r3, [r7, #4] 800ff58: 699b ldr r3, [r3, #24] 800ff5a: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 800ff5c: 68fa ldr r2, [r7, #12] 800ff5e: 4b37 ldr r3, [pc, #220] @ (801003c ) 800ff60: 4013 ands r3, r2 800ff62: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 800ff64: 68fb ldr r3, [r7, #12] 800ff66: f023 0303 bic.w r3, r3, #3 800ff6a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800ff6c: 683b ldr r3, [r7, #0] 800ff6e: 681b ldr r3, [r3, #0] 800ff70: 68fa ldr r2, [r7, #12] 800ff72: 4313 orrs r3, r2 800ff74: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 800ff76: 697b ldr r3, [r7, #20] 800ff78: f023 0302 bic.w r3, r3, #2 800ff7c: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 800ff7e: 683b ldr r3, [r7, #0] 800ff80: 689b ldr r3, [r3, #8] 800ff82: 697a ldr r2, [r7, #20] 800ff84: 4313 orrs r3, r2 800ff86: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 800ff88: 687b ldr r3, [r7, #4] 800ff8a: 4a2d ldr r2, [pc, #180] @ (8010040 ) 800ff8c: 4293 cmp r3, r2 800ff8e: d00f beq.n 800ffb0 800ff90: 687b ldr r3, [r7, #4] 800ff92: 4a2c ldr r2, [pc, #176] @ (8010044 ) 800ff94: 4293 cmp r3, r2 800ff96: d00b beq.n 800ffb0 800ff98: 687b ldr r3, [r7, #4] 800ff9a: 4a2b ldr r2, [pc, #172] @ (8010048 ) 800ff9c: 4293 cmp r3, r2 800ff9e: d007 beq.n 800ffb0 800ffa0: 687b ldr r3, [r7, #4] 800ffa2: 4a2a ldr r2, [pc, #168] @ (801004c ) 800ffa4: 4293 cmp r3, r2 800ffa6: d003 beq.n 800ffb0 800ffa8: 687b ldr r3, [r7, #4] 800ffaa: 4a29 ldr r2, [pc, #164] @ (8010050 ) 800ffac: 4293 cmp r3, r2 800ffae: d10c bne.n 800ffca { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 800ffb0: 697b ldr r3, [r7, #20] 800ffb2: f023 0308 bic.w r3, r3, #8 800ffb6: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 800ffb8: 683b ldr r3, [r7, #0] 800ffba: 68db ldr r3, [r3, #12] 800ffbc: 697a ldr r2, [r7, #20] 800ffbe: 4313 orrs r3, r2 800ffc0: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 800ffc2: 697b ldr r3, [r7, #20] 800ffc4: f023 0304 bic.w r3, r3, #4 800ffc8: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800ffca: 687b ldr r3, [r7, #4] 800ffcc: 4a1c ldr r2, [pc, #112] @ (8010040 ) 800ffce: 4293 cmp r3, r2 800ffd0: d00f beq.n 800fff2 800ffd2: 687b ldr r3, [r7, #4] 800ffd4: 4a1b ldr r2, [pc, #108] @ (8010044 ) 800ffd6: 4293 cmp r3, r2 800ffd8: d00b beq.n 800fff2 800ffda: 687b ldr r3, [r7, #4] 800ffdc: 4a1a ldr r2, [pc, #104] @ (8010048 ) 800ffde: 4293 cmp r3, r2 800ffe0: d007 beq.n 800fff2 800ffe2: 687b ldr r3, [r7, #4] 800ffe4: 4a19 ldr r2, [pc, #100] @ (801004c ) 800ffe6: 4293 cmp r3, r2 800ffe8: d003 beq.n 800fff2 800ffea: 687b ldr r3, [r7, #4] 800ffec: 4a18 ldr r2, [pc, #96] @ (8010050 ) 800ffee: 4293 cmp r3, r2 800fff0: d111 bne.n 8010016 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 800fff2: 693b ldr r3, [r7, #16] 800fff4: f423 7380 bic.w r3, r3, #256 @ 0x100 800fff8: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 800fffa: 693b ldr r3, [r7, #16] 800fffc: f423 7300 bic.w r3, r3, #512 @ 0x200 8010000: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8010002: 683b ldr r3, [r7, #0] 8010004: 695b ldr r3, [r3, #20] 8010006: 693a ldr r2, [r7, #16] 8010008: 4313 orrs r3, r2 801000a: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 801000c: 683b ldr r3, [r7, #0] 801000e: 699b ldr r3, [r3, #24] 8010010: 693a ldr r2, [r7, #16] 8010012: 4313 orrs r3, r2 8010014: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010016: 687b ldr r3, [r7, #4] 8010018: 693a ldr r2, [r7, #16] 801001a: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 801001c: 687b ldr r3, [r7, #4] 801001e: 68fa ldr r2, [r7, #12] 8010020: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 8010022: 683b ldr r3, [r7, #0] 8010024: 685a ldr r2, [r3, #4] 8010026: 687b ldr r3, [r7, #4] 8010028: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 801002a: 687b ldr r3, [r7, #4] 801002c: 697a ldr r2, [r7, #20] 801002e: 621a str r2, [r3, #32] } 8010030: bf00 nop 8010032: 371c adds r7, #28 8010034: 46bd mov sp, r7 8010036: f85d 7b04 ldr.w r7, [sp], #4 801003a: 4770 bx lr 801003c: fffeff8f .word 0xfffeff8f 8010040: 40010000 .word 0x40010000 8010044: 40010400 .word 0x40010400 8010048: 40014000 .word 0x40014000 801004c: 40014400 .word 0x40014400 8010050: 40014800 .word 0x40014800 08010054 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010054: b480 push {r7} 8010056: b087 sub sp, #28 8010058: af00 add r7, sp, #0 801005a: 6078 str r0, [r7, #4] 801005c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 801005e: 687b ldr r3, [r7, #4] 8010060: 6a1b ldr r3, [r3, #32] 8010062: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8010064: 687b ldr r3, [r7, #4] 8010066: 6a1b ldr r3, [r3, #32] 8010068: f023 0210 bic.w r2, r3, #16 801006c: 687b ldr r3, [r7, #4] 801006e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010070: 687b ldr r3, [r7, #4] 8010072: 685b ldr r3, [r3, #4] 8010074: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8010076: 687b ldr r3, [r7, #4] 8010078: 699b ldr r3, [r3, #24] 801007a: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 801007c: 68fa ldr r2, [r7, #12] 801007e: 4b34 ldr r3, [pc, #208] @ (8010150 ) 8010080: 4013 ands r3, r2 8010082: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8010084: 68fb ldr r3, [r7, #12] 8010086: f423 7340 bic.w r3, r3, #768 @ 0x300 801008a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 801008c: 683b ldr r3, [r7, #0] 801008e: 681b ldr r3, [r3, #0] 8010090: 021b lsls r3, r3, #8 8010092: 68fa ldr r2, [r7, #12] 8010094: 4313 orrs r3, r2 8010096: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 8010098: 697b ldr r3, [r7, #20] 801009a: f023 0320 bic.w r3, r3, #32 801009e: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 80100a0: 683b ldr r3, [r7, #0] 80100a2: 689b ldr r3, [r3, #8] 80100a4: 011b lsls r3, r3, #4 80100a6: 697a ldr r2, [r7, #20] 80100a8: 4313 orrs r3, r2 80100aa: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 80100ac: 687b ldr r3, [r7, #4] 80100ae: 4a29 ldr r2, [pc, #164] @ (8010154 ) 80100b0: 4293 cmp r3, r2 80100b2: d003 beq.n 80100bc 80100b4: 687b ldr r3, [r7, #4] 80100b6: 4a28 ldr r2, [pc, #160] @ (8010158 ) 80100b8: 4293 cmp r3, r2 80100ba: d10d bne.n 80100d8 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 80100bc: 697b ldr r3, [r7, #20] 80100be: f023 0380 bic.w r3, r3, #128 @ 0x80 80100c2: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 80100c4: 683b ldr r3, [r7, #0] 80100c6: 68db ldr r3, [r3, #12] 80100c8: 011b lsls r3, r3, #4 80100ca: 697a ldr r2, [r7, #20] 80100cc: 4313 orrs r3, r2 80100ce: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 80100d0: 697b ldr r3, [r7, #20] 80100d2: f023 0340 bic.w r3, r3, #64 @ 0x40 80100d6: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80100d8: 687b ldr r3, [r7, #4] 80100da: 4a1e ldr r2, [pc, #120] @ (8010154 ) 80100dc: 4293 cmp r3, r2 80100de: d00f beq.n 8010100 80100e0: 687b ldr r3, [r7, #4] 80100e2: 4a1d ldr r2, [pc, #116] @ (8010158 ) 80100e4: 4293 cmp r3, r2 80100e6: d00b beq.n 8010100 80100e8: 687b ldr r3, [r7, #4] 80100ea: 4a1c ldr r2, [pc, #112] @ (801015c ) 80100ec: 4293 cmp r3, r2 80100ee: d007 beq.n 8010100 80100f0: 687b ldr r3, [r7, #4] 80100f2: 4a1b ldr r2, [pc, #108] @ (8010160 ) 80100f4: 4293 cmp r3, r2 80100f6: d003 beq.n 8010100 80100f8: 687b ldr r3, [r7, #4] 80100fa: 4a1a ldr r2, [pc, #104] @ (8010164 ) 80100fc: 4293 cmp r3, r2 80100fe: d113 bne.n 8010128 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8010100: 693b ldr r3, [r7, #16] 8010102: f423 6380 bic.w r3, r3, #1024 @ 0x400 8010106: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8010108: 693b ldr r3, [r7, #16] 801010a: f423 6300 bic.w r3, r3, #2048 @ 0x800 801010e: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8010110: 683b ldr r3, [r7, #0] 8010112: 695b ldr r3, [r3, #20] 8010114: 009b lsls r3, r3, #2 8010116: 693a ldr r2, [r7, #16] 8010118: 4313 orrs r3, r2 801011a: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 801011c: 683b ldr r3, [r7, #0] 801011e: 699b ldr r3, [r3, #24] 8010120: 009b lsls r3, r3, #2 8010122: 693a ldr r2, [r7, #16] 8010124: 4313 orrs r3, r2 8010126: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010128: 687b ldr r3, [r7, #4] 801012a: 693a ldr r2, [r7, #16] 801012c: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 801012e: 687b ldr r3, [r7, #4] 8010130: 68fa ldr r2, [r7, #12] 8010132: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8010134: 683b ldr r3, [r7, #0] 8010136: 685a ldr r2, [r3, #4] 8010138: 687b ldr r3, [r7, #4] 801013a: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 801013c: 687b ldr r3, [r7, #4] 801013e: 697a ldr r2, [r7, #20] 8010140: 621a str r2, [r3, #32] } 8010142: bf00 nop 8010144: 371c adds r7, #28 8010146: 46bd mov sp, r7 8010148: f85d 7b04 ldr.w r7, [sp], #4 801014c: 4770 bx lr 801014e: bf00 nop 8010150: feff8fff .word 0xfeff8fff 8010154: 40010000 .word 0x40010000 8010158: 40010400 .word 0x40010400 801015c: 40014000 .word 0x40014000 8010160: 40014400 .word 0x40014400 8010164: 40014800 .word 0x40014800 08010168 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010168: b480 push {r7} 801016a: b087 sub sp, #28 801016c: af00 add r7, sp, #0 801016e: 6078 str r0, [r7, #4] 8010170: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010172: 687b ldr r3, [r7, #4] 8010174: 6a1b ldr r3, [r3, #32] 8010176: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8010178: 687b ldr r3, [r7, #4] 801017a: 6a1b ldr r3, [r3, #32] 801017c: f423 7280 bic.w r2, r3, #256 @ 0x100 8010180: 687b ldr r3, [r7, #4] 8010182: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010184: 687b ldr r3, [r7, #4] 8010186: 685b ldr r3, [r3, #4] 8010188: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 801018a: 687b ldr r3, [r7, #4] 801018c: 69db ldr r3, [r3, #28] 801018e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8010190: 68fa ldr r2, [r7, #12] 8010192: 4b33 ldr r3, [pc, #204] @ (8010260 ) 8010194: 4013 ands r3, r2 8010196: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8010198: 68fb ldr r3, [r7, #12] 801019a: f023 0303 bic.w r3, r3, #3 801019e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80101a0: 683b ldr r3, [r7, #0] 80101a2: 681b ldr r3, [r3, #0] 80101a4: 68fa ldr r2, [r7, #12] 80101a6: 4313 orrs r3, r2 80101a8: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 80101aa: 697b ldr r3, [r7, #20] 80101ac: f423 7300 bic.w r3, r3, #512 @ 0x200 80101b0: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 80101b2: 683b ldr r3, [r7, #0] 80101b4: 689b ldr r3, [r3, #8] 80101b6: 021b lsls r3, r3, #8 80101b8: 697a ldr r2, [r7, #20] 80101ba: 4313 orrs r3, r2 80101bc: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 80101be: 687b ldr r3, [r7, #4] 80101c0: 4a28 ldr r2, [pc, #160] @ (8010264 ) 80101c2: 4293 cmp r3, r2 80101c4: d003 beq.n 80101ce 80101c6: 687b ldr r3, [r7, #4] 80101c8: 4a27 ldr r2, [pc, #156] @ (8010268 ) 80101ca: 4293 cmp r3, r2 80101cc: d10d bne.n 80101ea { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 80101ce: 697b ldr r3, [r7, #20] 80101d0: f423 6300 bic.w r3, r3, #2048 @ 0x800 80101d4: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 80101d6: 683b ldr r3, [r7, #0] 80101d8: 68db ldr r3, [r3, #12] 80101da: 021b lsls r3, r3, #8 80101dc: 697a ldr r2, [r7, #20] 80101de: 4313 orrs r3, r2 80101e0: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 80101e2: 697b ldr r3, [r7, #20] 80101e4: f423 6380 bic.w r3, r3, #1024 @ 0x400 80101e8: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80101ea: 687b ldr r3, [r7, #4] 80101ec: 4a1d ldr r2, [pc, #116] @ (8010264 ) 80101ee: 4293 cmp r3, r2 80101f0: d00f beq.n 8010212 80101f2: 687b ldr r3, [r7, #4] 80101f4: 4a1c ldr r2, [pc, #112] @ (8010268 ) 80101f6: 4293 cmp r3, r2 80101f8: d00b beq.n 8010212 80101fa: 687b ldr r3, [r7, #4] 80101fc: 4a1b ldr r2, [pc, #108] @ (801026c ) 80101fe: 4293 cmp r3, r2 8010200: d007 beq.n 8010212 8010202: 687b ldr r3, [r7, #4] 8010204: 4a1a ldr r2, [pc, #104] @ (8010270 ) 8010206: 4293 cmp r3, r2 8010208: d003 beq.n 8010212 801020a: 687b ldr r3, [r7, #4] 801020c: 4a19 ldr r2, [pc, #100] @ (8010274 ) 801020e: 4293 cmp r3, r2 8010210: d113 bne.n 801023a /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8010212: 693b ldr r3, [r7, #16] 8010214: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8010218: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 801021a: 693b ldr r3, [r7, #16] 801021c: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8010220: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8010222: 683b ldr r3, [r7, #0] 8010224: 695b ldr r3, [r3, #20] 8010226: 011b lsls r3, r3, #4 8010228: 693a ldr r2, [r7, #16] 801022a: 4313 orrs r3, r2 801022c: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 801022e: 683b ldr r3, [r7, #0] 8010230: 699b ldr r3, [r3, #24] 8010232: 011b lsls r3, r3, #4 8010234: 693a ldr r2, [r7, #16] 8010236: 4313 orrs r3, r2 8010238: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 801023a: 687b ldr r3, [r7, #4] 801023c: 693a ldr r2, [r7, #16] 801023e: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8010240: 687b ldr r3, [r7, #4] 8010242: 68fa ldr r2, [r7, #12] 8010244: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8010246: 683b ldr r3, [r7, #0] 8010248: 685a ldr r2, [r3, #4] 801024a: 687b ldr r3, [r7, #4] 801024c: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 801024e: 687b ldr r3, [r7, #4] 8010250: 697a ldr r2, [r7, #20] 8010252: 621a str r2, [r3, #32] } 8010254: bf00 nop 8010256: 371c adds r7, #28 8010258: 46bd mov sp, r7 801025a: f85d 7b04 ldr.w r7, [sp], #4 801025e: 4770 bx lr 8010260: fffeff8f .word 0xfffeff8f 8010264: 40010000 .word 0x40010000 8010268: 40010400 .word 0x40010400 801026c: 40014000 .word 0x40014000 8010270: 40014400 .word 0x40014400 8010274: 40014800 .word 0x40014800 08010278 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010278: b480 push {r7} 801027a: b087 sub sp, #28 801027c: af00 add r7, sp, #0 801027e: 6078 str r0, [r7, #4] 8010280: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010282: 687b ldr r3, [r7, #4] 8010284: 6a1b ldr r3, [r3, #32] 8010286: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8010288: 687b ldr r3, [r7, #4] 801028a: 6a1b ldr r3, [r3, #32] 801028c: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8010290: 687b ldr r3, [r7, #4] 8010292: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010294: 687b ldr r3, [r7, #4] 8010296: 685b ldr r3, [r3, #4] 8010298: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 801029a: 687b ldr r3, [r7, #4] 801029c: 69db ldr r3, [r3, #28] 801029e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 80102a0: 68fa ldr r2, [r7, #12] 80102a2: 4b24 ldr r3, [pc, #144] @ (8010334 ) 80102a4: 4013 ands r3, r2 80102a6: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 80102a8: 68fb ldr r3, [r7, #12] 80102aa: f423 7340 bic.w r3, r3, #768 @ 0x300 80102ae: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80102b0: 683b ldr r3, [r7, #0] 80102b2: 681b ldr r3, [r3, #0] 80102b4: 021b lsls r3, r3, #8 80102b6: 68fa ldr r2, [r7, #12] 80102b8: 4313 orrs r3, r2 80102ba: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 80102bc: 693b ldr r3, [r7, #16] 80102be: f423 5300 bic.w r3, r3, #8192 @ 0x2000 80102c2: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 80102c4: 683b ldr r3, [r7, #0] 80102c6: 689b ldr r3, [r3, #8] 80102c8: 031b lsls r3, r3, #12 80102ca: 693a ldr r2, [r7, #16] 80102cc: 4313 orrs r3, r2 80102ce: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 80102d0: 687b ldr r3, [r7, #4] 80102d2: 4a19 ldr r2, [pc, #100] @ (8010338 ) 80102d4: 4293 cmp r3, r2 80102d6: d00f beq.n 80102f8 80102d8: 687b ldr r3, [r7, #4] 80102da: 4a18 ldr r2, [pc, #96] @ (801033c ) 80102dc: 4293 cmp r3, r2 80102de: d00b beq.n 80102f8 80102e0: 687b ldr r3, [r7, #4] 80102e2: 4a17 ldr r2, [pc, #92] @ (8010340 ) 80102e4: 4293 cmp r3, r2 80102e6: d007 beq.n 80102f8 80102e8: 687b ldr r3, [r7, #4] 80102ea: 4a16 ldr r2, [pc, #88] @ (8010344 ) 80102ec: 4293 cmp r3, r2 80102ee: d003 beq.n 80102f8 80102f0: 687b ldr r3, [r7, #4] 80102f2: 4a15 ldr r2, [pc, #84] @ (8010348 ) 80102f4: 4293 cmp r3, r2 80102f6: d109 bne.n 801030c { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 80102f8: 697b ldr r3, [r7, #20] 80102fa: f423 4380 bic.w r3, r3, #16384 @ 0x4000 80102fe: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8010300: 683b ldr r3, [r7, #0] 8010302: 695b ldr r3, [r3, #20] 8010304: 019b lsls r3, r3, #6 8010306: 697a ldr r2, [r7, #20] 8010308: 4313 orrs r3, r2 801030a: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 801030c: 687b ldr r3, [r7, #4] 801030e: 697a ldr r2, [r7, #20] 8010310: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8010312: 687b ldr r3, [r7, #4] 8010314: 68fa ldr r2, [r7, #12] 8010316: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8010318: 683b ldr r3, [r7, #0] 801031a: 685a ldr r2, [r3, #4] 801031c: 687b ldr r3, [r7, #4] 801031e: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010320: 687b ldr r3, [r7, #4] 8010322: 693a ldr r2, [r7, #16] 8010324: 621a str r2, [r3, #32] } 8010326: bf00 nop 8010328: 371c adds r7, #28 801032a: 46bd mov sp, r7 801032c: f85d 7b04 ldr.w r7, [sp], #4 8010330: 4770 bx lr 8010332: bf00 nop 8010334: feff8fff .word 0xfeff8fff 8010338: 40010000 .word 0x40010000 801033c: 40010400 .word 0x40010400 8010340: 40014000 .word 0x40014000 8010344: 40014400 .word 0x40014400 8010348: 40014800 .word 0x40014800 0801034c : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 801034c: b480 push {r7} 801034e: b087 sub sp, #28 8010350: af00 add r7, sp, #0 8010352: 6078 str r0, [r7, #4] 8010354: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010356: 687b ldr r3, [r7, #4] 8010358: 6a1b ldr r3, [r3, #32] 801035a: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; 801035c: 687b ldr r3, [r7, #4] 801035e: 6a1b ldr r3, [r3, #32] 8010360: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8010364: 687b ldr r3, [r7, #4] 8010366: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010368: 687b ldr r3, [r7, #4] 801036a: 685b ldr r3, [r3, #4] 801036c: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 801036e: 687b ldr r3, [r7, #4] 8010370: 6d5b ldr r3, [r3, #84] @ 0x54 8010372: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); 8010374: 68fa ldr r2, [r7, #12] 8010376: 4b21 ldr r3, [pc, #132] @ (80103fc ) 8010378: 4013 ands r3, r2 801037a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 801037c: 683b ldr r3, [r7, #0] 801037e: 681b ldr r3, [r3, #0] 8010380: 68fa ldr r2, [r7, #12] 8010382: 4313 orrs r3, r2 8010384: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; 8010386: 693b ldr r3, [r7, #16] 8010388: f423 3300 bic.w r3, r3, #131072 @ 0x20000 801038c: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); 801038e: 683b ldr r3, [r7, #0] 8010390: 689b ldr r3, [r3, #8] 8010392: 041b lsls r3, r3, #16 8010394: 693a ldr r2, [r7, #16] 8010396: 4313 orrs r3, r2 8010398: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 801039a: 687b ldr r3, [r7, #4] 801039c: 4a18 ldr r2, [pc, #96] @ (8010400 ) 801039e: 4293 cmp r3, r2 80103a0: d00f beq.n 80103c2 80103a2: 687b ldr r3, [r7, #4] 80103a4: 4a17 ldr r2, [pc, #92] @ (8010404 ) 80103a6: 4293 cmp r3, r2 80103a8: d00b beq.n 80103c2 80103aa: 687b ldr r3, [r7, #4] 80103ac: 4a16 ldr r2, [pc, #88] @ (8010408 ) 80103ae: 4293 cmp r3, r2 80103b0: d007 beq.n 80103c2 80103b2: 687b ldr r3, [r7, #4] 80103b4: 4a15 ldr r2, [pc, #84] @ (801040c ) 80103b6: 4293 cmp r3, r2 80103b8: d003 beq.n 80103c2 80103ba: 687b ldr r3, [r7, #4] 80103bc: 4a14 ldr r2, [pc, #80] @ (8010410 ) 80103be: 4293 cmp r3, r2 80103c0: d109 bne.n 80103d6 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; 80103c2: 697b ldr r3, [r7, #20] 80103c4: f423 3380 bic.w r3, r3, #65536 @ 0x10000 80103c8: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); 80103ca: 683b ldr r3, [r7, #0] 80103cc: 695b ldr r3, [r3, #20] 80103ce: 021b lsls r3, r3, #8 80103d0: 697a ldr r2, [r7, #20] 80103d2: 4313 orrs r3, r2 80103d4: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80103d6: 687b ldr r3, [r7, #4] 80103d8: 697a ldr r2, [r7, #20] 80103da: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 80103dc: 687b ldr r3, [r7, #4] 80103de: 68fa ldr r2, [r7, #12] 80103e0: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; 80103e2: 683b ldr r3, [r7, #0] 80103e4: 685a ldr r2, [r3, #4] 80103e6: 687b ldr r3, [r7, #4] 80103e8: 659a str r2, [r3, #88] @ 0x58 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80103ea: 687b ldr r3, [r7, #4] 80103ec: 693a ldr r2, [r7, #16] 80103ee: 621a str r2, [r3, #32] } 80103f0: bf00 nop 80103f2: 371c adds r7, #28 80103f4: 46bd mov sp, r7 80103f6: f85d 7b04 ldr.w r7, [sp], #4 80103fa: 4770 bx lr 80103fc: fffeff8f .word 0xfffeff8f 8010400: 40010000 .word 0x40010000 8010404: 40010400 .word 0x40010400 8010408: 40014000 .word 0x40014000 801040c: 40014400 .word 0x40014400 8010410: 40014800 .word 0x40014800 08010414 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010414: b480 push {r7} 8010416: b087 sub sp, #28 8010418: af00 add r7, sp, #0 801041a: 6078 str r0, [r7, #4] 801041c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 801041e: 687b ldr r3, [r7, #4] 8010420: 6a1b ldr r3, [r3, #32] 8010422: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; 8010424: 687b ldr r3, [r7, #4] 8010426: 6a1b ldr r3, [r3, #32] 8010428: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 801042c: 687b ldr r3, [r7, #4] 801042e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010430: 687b ldr r3, [r7, #4] 8010432: 685b ldr r3, [r3, #4] 8010434: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 8010436: 687b ldr r3, [r7, #4] 8010438: 6d5b ldr r3, [r3, #84] @ 0x54 801043a: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); 801043c: 68fa ldr r2, [r7, #12] 801043e: 4b22 ldr r3, [pc, #136] @ (80104c8 ) 8010440: 4013 ands r3, r2 8010442: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8010444: 683b ldr r3, [r7, #0] 8010446: 681b ldr r3, [r3, #0] 8010448: 021b lsls r3, r3, #8 801044a: 68fa ldr r2, [r7, #12] 801044c: 4313 orrs r3, r2 801044e: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; 8010450: 693b ldr r3, [r7, #16] 8010452: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8010456: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); 8010458: 683b ldr r3, [r7, #0] 801045a: 689b ldr r3, [r3, #8] 801045c: 051b lsls r3, r3, #20 801045e: 693a ldr r2, [r7, #16] 8010460: 4313 orrs r3, r2 8010462: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010464: 687b ldr r3, [r7, #4] 8010466: 4a19 ldr r2, [pc, #100] @ (80104cc ) 8010468: 4293 cmp r3, r2 801046a: d00f beq.n 801048c 801046c: 687b ldr r3, [r7, #4] 801046e: 4a18 ldr r2, [pc, #96] @ (80104d0 ) 8010470: 4293 cmp r3, r2 8010472: d00b beq.n 801048c 8010474: 687b ldr r3, [r7, #4] 8010476: 4a17 ldr r2, [pc, #92] @ (80104d4 ) 8010478: 4293 cmp r3, r2 801047a: d007 beq.n 801048c 801047c: 687b ldr r3, [r7, #4] 801047e: 4a16 ldr r2, [pc, #88] @ (80104d8 ) 8010480: 4293 cmp r3, r2 8010482: d003 beq.n 801048c 8010484: 687b ldr r3, [r7, #4] 8010486: 4a15 ldr r2, [pc, #84] @ (80104dc ) 8010488: 4293 cmp r3, r2 801048a: d109 bne.n 80104a0 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; 801048c: 697b ldr r3, [r7, #20] 801048e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010492: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); 8010494: 683b ldr r3, [r7, #0] 8010496: 695b ldr r3, [r3, #20] 8010498: 029b lsls r3, r3, #10 801049a: 697a ldr r2, [r7, #20] 801049c: 4313 orrs r3, r2 801049e: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80104a0: 687b ldr r3, [r7, #4] 80104a2: 697a ldr r2, [r7, #20] 80104a4: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 80104a6: 687b ldr r3, [r7, #4] 80104a8: 68fa ldr r2, [r7, #12] 80104aa: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; 80104ac: 683b ldr r3, [r7, #0] 80104ae: 685a ldr r2, [r3, #4] 80104b0: 687b ldr r3, [r7, #4] 80104b2: 65da str r2, [r3, #92] @ 0x5c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80104b4: 687b ldr r3, [r7, #4] 80104b6: 693a ldr r2, [r7, #16] 80104b8: 621a str r2, [r3, #32] } 80104ba: bf00 nop 80104bc: 371c adds r7, #28 80104be: 46bd mov sp, r7 80104c0: f85d 7b04 ldr.w r7, [sp], #4 80104c4: 4770 bx lr 80104c6: bf00 nop 80104c8: feff8fff .word 0xfeff8fff 80104cc: 40010000 .word 0x40010000 80104d0: 40010400 .word 0x40010400 80104d4: 40014000 .word 0x40014000 80104d8: 40014400 .word 0x40014400 80104dc: 40014800 .word 0x40014800 080104e0 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 80104e0: b480 push {r7} 80104e2: b087 sub sp, #28 80104e4: af00 add r7, sp, #0 80104e6: 60f8 str r0, [r7, #12] 80104e8: 60b9 str r1, [r7, #8] 80104ea: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 80104ec: 68fb ldr r3, [r7, #12] 80104ee: 6a1b ldr r3, [r3, #32] 80104f0: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 80104f2: 68fb ldr r3, [r7, #12] 80104f4: 6a1b ldr r3, [r3, #32] 80104f6: f023 0201 bic.w r2, r3, #1 80104fa: 68fb ldr r3, [r7, #12] 80104fc: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 80104fe: 68fb ldr r3, [r7, #12] 8010500: 699b ldr r3, [r3, #24] 8010502: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8010504: 693b ldr r3, [r7, #16] 8010506: f023 03f0 bic.w r3, r3, #240 @ 0xf0 801050a: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 801050c: 687b ldr r3, [r7, #4] 801050e: 011b lsls r3, r3, #4 8010510: 693a ldr r2, [r7, #16] 8010512: 4313 orrs r3, r2 8010514: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8010516: 697b ldr r3, [r7, #20] 8010518: f023 030a bic.w r3, r3, #10 801051c: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 801051e: 697a ldr r2, [r7, #20] 8010520: 68bb ldr r3, [r7, #8] 8010522: 4313 orrs r3, r2 8010524: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8010526: 68fb ldr r3, [r7, #12] 8010528: 693a ldr r2, [r7, #16] 801052a: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 801052c: 68fb ldr r3, [r7, #12] 801052e: 697a ldr r2, [r7, #20] 8010530: 621a str r2, [r3, #32] } 8010532: bf00 nop 8010534: 371c adds r7, #28 8010536: 46bd mov sp, r7 8010538: f85d 7b04 ldr.w r7, [sp], #4 801053c: 4770 bx lr 0801053e : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 801053e: b480 push {r7} 8010540: b087 sub sp, #28 8010542: af00 add r7, sp, #0 8010544: 60f8 str r0, [r7, #12] 8010546: 60b9 str r1, [r7, #8] 8010548: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 801054a: 68fb ldr r3, [r7, #12] 801054c: 6a1b ldr r3, [r3, #32] 801054e: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8010550: 68fb ldr r3, [r7, #12] 8010552: 6a1b ldr r3, [r3, #32] 8010554: f023 0210 bic.w r2, r3, #16 8010558: 68fb ldr r3, [r7, #12] 801055a: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 801055c: 68fb ldr r3, [r7, #12] 801055e: 699b ldr r3, [r3, #24] 8010560: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8010562: 693b ldr r3, [r7, #16] 8010564: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8010568: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 801056a: 687b ldr r3, [r7, #4] 801056c: 031b lsls r3, r3, #12 801056e: 693a ldr r2, [r7, #16] 8010570: 4313 orrs r3, r2 8010572: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8010574: 697b ldr r3, [r7, #20] 8010576: f023 03a0 bic.w r3, r3, #160 @ 0xa0 801057a: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 801057c: 68bb ldr r3, [r7, #8] 801057e: 011b lsls r3, r3, #4 8010580: 697a ldr r2, [r7, #20] 8010582: 4313 orrs r3, r2 8010584: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8010586: 68fb ldr r3, [r7, #12] 8010588: 693a ldr r2, [r7, #16] 801058a: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 801058c: 68fb ldr r3, [r7, #12] 801058e: 697a ldr r2, [r7, #20] 8010590: 621a str r2, [r3, #32] } 8010592: bf00 nop 8010594: 371c adds r7, #28 8010596: 46bd mov sp, r7 8010598: f85d 7b04 ldr.w r7, [sp], #4 801059c: 4770 bx lr ... 080105a0 : * (*) Value not defined in all devices. * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 80105a0: b480 push {r7} 80105a2: b085 sub sp, #20 80105a4: af00 add r7, sp, #0 80105a6: 6078 str r0, [r7, #4] 80105a8: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 80105aa: 687b ldr r3, [r7, #4] 80105ac: 689b ldr r3, [r3, #8] 80105ae: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 80105b0: 68fa ldr r2, [r7, #12] 80105b2: 4b09 ldr r3, [pc, #36] @ (80105d8 ) 80105b4: 4013 ands r3, r2 80105b6: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 80105b8: 683a ldr r2, [r7, #0] 80105ba: 68fb ldr r3, [r7, #12] 80105bc: 4313 orrs r3, r2 80105be: f043 0307 orr.w r3, r3, #7 80105c2: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 80105c4: 687b ldr r3, [r7, #4] 80105c6: 68fa ldr r2, [r7, #12] 80105c8: 609a str r2, [r3, #8] } 80105ca: bf00 nop 80105cc: 3714 adds r7, #20 80105ce: 46bd mov sp, r7 80105d0: f85d 7b04 ldr.w r7, [sp], #4 80105d4: 4770 bx lr 80105d6: bf00 nop 80105d8: ffcfff8f .word 0xffcfff8f 080105dc : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 80105dc: b480 push {r7} 80105de: b087 sub sp, #28 80105e0: af00 add r7, sp, #0 80105e2: 60f8 str r0, [r7, #12] 80105e4: 60b9 str r1, [r7, #8] 80105e6: 607a str r2, [r7, #4] 80105e8: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 80105ea: 68fb ldr r3, [r7, #12] 80105ec: 689b ldr r3, [r3, #8] 80105ee: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80105f0: 697b ldr r3, [r7, #20] 80105f2: f423 437f bic.w r3, r3, #65280 @ 0xff00 80105f6: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 80105f8: 683b ldr r3, [r7, #0] 80105fa: 021a lsls r2, r3, #8 80105fc: 687b ldr r3, [r7, #4] 80105fe: 431a orrs r2, r3 8010600: 68bb ldr r3, [r7, #8] 8010602: 4313 orrs r3, r2 8010604: 697a ldr r2, [r7, #20] 8010606: 4313 orrs r3, r2 8010608: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 801060a: 68fb ldr r3, [r7, #12] 801060c: 697a ldr r2, [r7, #20] 801060e: 609a str r2, [r3, #8] } 8010610: bf00 nop 8010612: 371c adds r7, #28 8010614: 46bd mov sp, r7 8010616: f85d 7b04 ldr.w r7, [sp], #4 801061a: 4770 bx lr 0801061c : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 801061c: b480 push {r7} 801061e: b087 sub sp, #28 8010620: af00 add r7, sp, #0 8010622: 60f8 str r0, [r7, #12] 8010624: 60b9 str r1, [r7, #8] 8010626: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8010628: 68bb ldr r3, [r7, #8] 801062a: f003 031f and.w r3, r3, #31 801062e: 2201 movs r2, #1 8010630: fa02 f303 lsl.w r3, r2, r3 8010634: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 8010636: 68fb ldr r3, [r7, #12] 8010638: 6a1a ldr r2, [r3, #32] 801063a: 697b ldr r3, [r7, #20] 801063c: 43db mvns r3, r3 801063e: 401a ands r2, r3 8010640: 68fb ldr r3, [r7, #12] 8010642: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8010644: 68fb ldr r3, [r7, #12] 8010646: 6a1a ldr r2, [r3, #32] 8010648: 68bb ldr r3, [r7, #8] 801064a: f003 031f and.w r3, r3, #31 801064e: 6879 ldr r1, [r7, #4] 8010650: fa01 f303 lsl.w r3, r1, r3 8010654: 431a orrs r2, r3 8010656: 68fb ldr r3, [r7, #12] 8010658: 621a str r2, [r3, #32] } 801065a: bf00 nop 801065c: 371c adds r7, #28 801065e: 46bd mov sp, r7 8010660: f85d 7b04 ldr.w r7, [sp], #4 8010664: 4770 bx lr ... 08010668 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8010668: b480 push {r7} 801066a: b085 sub sp, #20 801066c: af00 add r7, sp, #0 801066e: 6078 str r0, [r7, #4] 8010670: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8010672: 687b ldr r3, [r7, #4] 8010674: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8010678: 2b01 cmp r3, #1 801067a: d101 bne.n 8010680 801067c: 2302 movs r3, #2 801067e: e06d b.n 801075c 8010680: 687b ldr r3, [r7, #4] 8010682: 2201 movs r2, #1 8010684: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8010688: 687b ldr r3, [r7, #4] 801068a: 2202 movs r2, #2 801068c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8010690: 687b ldr r3, [r7, #4] 8010692: 681b ldr r3, [r3, #0] 8010694: 685b ldr r3, [r3, #4] 8010696: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8010698: 687b ldr r3, [r7, #4] 801069a: 681b ldr r3, [r3, #0] 801069c: 689b ldr r3, [r3, #8] 801069e: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 80106a0: 687b ldr r3, [r7, #4] 80106a2: 681b ldr r3, [r3, #0] 80106a4: 4a30 ldr r2, [pc, #192] @ (8010768 ) 80106a6: 4293 cmp r3, r2 80106a8: d004 beq.n 80106b4 80106aa: 687b ldr r3, [r7, #4] 80106ac: 681b ldr r3, [r3, #0] 80106ae: 4a2f ldr r2, [pc, #188] @ (801076c ) 80106b0: 4293 cmp r3, r2 80106b2: d108 bne.n 80106c6 { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 80106b4: 68fb ldr r3, [r7, #12] 80106b6: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 80106ba: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 80106bc: 683b ldr r3, [r7, #0] 80106be: 685b ldr r3, [r3, #4] 80106c0: 68fa ldr r2, [r7, #12] 80106c2: 4313 orrs r3, r2 80106c4: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 80106c6: 68fb ldr r3, [r7, #12] 80106c8: f023 0370 bic.w r3, r3, #112 @ 0x70 80106cc: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 80106ce: 683b ldr r3, [r7, #0] 80106d0: 681b ldr r3, [r3, #0] 80106d2: 68fa ldr r2, [r7, #12] 80106d4: 4313 orrs r3, r2 80106d6: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 80106d8: 687b ldr r3, [r7, #4] 80106da: 681b ldr r3, [r3, #0] 80106dc: 68fa ldr r2, [r7, #12] 80106de: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80106e0: 687b ldr r3, [r7, #4] 80106e2: 681b ldr r3, [r3, #0] 80106e4: 4a20 ldr r2, [pc, #128] @ (8010768 ) 80106e6: 4293 cmp r3, r2 80106e8: d022 beq.n 8010730 80106ea: 687b ldr r3, [r7, #4] 80106ec: 681b ldr r3, [r3, #0] 80106ee: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80106f2: d01d beq.n 8010730 80106f4: 687b ldr r3, [r7, #4] 80106f6: 681b ldr r3, [r3, #0] 80106f8: 4a1d ldr r2, [pc, #116] @ (8010770 ) 80106fa: 4293 cmp r3, r2 80106fc: d018 beq.n 8010730 80106fe: 687b ldr r3, [r7, #4] 8010700: 681b ldr r3, [r3, #0] 8010702: 4a1c ldr r2, [pc, #112] @ (8010774 ) 8010704: 4293 cmp r3, r2 8010706: d013 beq.n 8010730 8010708: 687b ldr r3, [r7, #4] 801070a: 681b ldr r3, [r3, #0] 801070c: 4a1a ldr r2, [pc, #104] @ (8010778 ) 801070e: 4293 cmp r3, r2 8010710: d00e beq.n 8010730 8010712: 687b ldr r3, [r7, #4] 8010714: 681b ldr r3, [r3, #0] 8010716: 4a15 ldr r2, [pc, #84] @ (801076c ) 8010718: 4293 cmp r3, r2 801071a: d009 beq.n 8010730 801071c: 687b ldr r3, [r7, #4] 801071e: 681b ldr r3, [r3, #0] 8010720: 4a16 ldr r2, [pc, #88] @ (801077c ) 8010722: 4293 cmp r3, r2 8010724: d004 beq.n 8010730 8010726: 687b ldr r3, [r7, #4] 8010728: 681b ldr r3, [r3, #0] 801072a: 4a15 ldr r2, [pc, #84] @ (8010780 ) 801072c: 4293 cmp r3, r2 801072e: d10c bne.n 801074a { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8010730: 68bb ldr r3, [r7, #8] 8010732: f023 0380 bic.w r3, r3, #128 @ 0x80 8010736: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8010738: 683b ldr r3, [r7, #0] 801073a: 689b ldr r3, [r3, #8] 801073c: 68ba ldr r2, [r7, #8] 801073e: 4313 orrs r3, r2 8010740: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8010742: 687b ldr r3, [r7, #4] 8010744: 681b ldr r3, [r3, #0] 8010746: 68ba ldr r2, [r7, #8] 8010748: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 801074a: 687b ldr r3, [r7, #4] 801074c: 2201 movs r2, #1 801074e: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8010752: 687b ldr r3, [r7, #4] 8010754: 2200 movs r2, #0 8010756: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 801075a: 2300 movs r3, #0 } 801075c: 4618 mov r0, r3 801075e: 3714 adds r7, #20 8010760: 46bd mov sp, r7 8010762: f85d 7b04 ldr.w r7, [sp], #4 8010766: 4770 bx lr 8010768: 40010000 .word 0x40010000 801076c: 40010400 .word 0x40010400 8010770: 40000400 .word 0x40000400 8010774: 40000800 .word 0x40000800 8010778: 40000c00 .word 0x40000c00 801077c: 40001800 .word 0x40001800 8010780: 40014000 .word 0x40014000 08010784 : * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { 8010784: b480 push {r7} 8010786: b085 sub sp, #20 8010788: af00 add r7, sp, #0 801078a: 6078 str r0, [r7, #4] 801078c: 6039 str r1, [r7, #0] /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; 801078e: 2300 movs r3, #0 8010790: 60fb str r3, [r7, #12] #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); #endif /* TIM_BDTR_BKBID */ /* Check input state */ __HAL_LOCK(htim); 8010792: 687b ldr r3, [r7, #4] 8010794: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8010798: 2b01 cmp r3, #1 801079a: d101 bne.n 80107a0 801079c: 2302 movs r3, #2 801079e: e065 b.n 801086c 80107a0: 687b ldr r3, [r7, #4] 80107a2: 2201 movs r2, #1 80107a4: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); 80107a8: 68fb ldr r3, [r7, #12] 80107aa: f023 02ff bic.w r2, r3, #255 @ 0xff 80107ae: 683b ldr r3, [r7, #0] 80107b0: 68db ldr r3, [r3, #12] 80107b2: 4313 orrs r3, r2 80107b4: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); 80107b6: 68fb ldr r3, [r7, #12] 80107b8: f423 7240 bic.w r2, r3, #768 @ 0x300 80107bc: 683b ldr r3, [r7, #0] 80107be: 689b ldr r3, [r3, #8] 80107c0: 4313 orrs r3, r2 80107c2: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 80107c4: 68fb ldr r3, [r7, #12] 80107c6: f423 6280 bic.w r2, r3, #1024 @ 0x400 80107ca: 683b ldr r3, [r7, #0] 80107cc: 685b ldr r3, [r3, #4] 80107ce: 4313 orrs r3, r2 80107d0: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 80107d2: 68fb ldr r3, [r7, #12] 80107d4: f423 6200 bic.w r2, r3, #2048 @ 0x800 80107d8: 683b ldr r3, [r7, #0] 80107da: 681b ldr r3, [r3, #0] 80107dc: 4313 orrs r3, r2 80107de: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 80107e0: 68fb ldr r3, [r7, #12] 80107e2: f423 5280 bic.w r2, r3, #4096 @ 0x1000 80107e6: 683b ldr r3, [r7, #0] 80107e8: 691b ldr r3, [r3, #16] 80107ea: 4313 orrs r3, r2 80107ec: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 80107ee: 68fb ldr r3, [r7, #12] 80107f0: f423 5200 bic.w r2, r3, #8192 @ 0x2000 80107f4: 683b ldr r3, [r7, #0] 80107f6: 695b ldr r3, [r3, #20] 80107f8: 4313 orrs r3, r2 80107fa: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 80107fc: 68fb ldr r3, [r7, #12] 80107fe: f423 4280 bic.w r2, r3, #16384 @ 0x4000 8010802: 683b ldr r3, [r7, #0] 8010804: 6a9b ldr r3, [r3, #40] @ 0x28 8010806: 4313 orrs r3, r2 8010808: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 801080a: 68fb ldr r3, [r7, #12] 801080c: f423 2270 bic.w r2, r3, #983040 @ 0xf0000 8010810: 683b ldr r3, [r7, #0] 8010812: 699b ldr r3, [r3, #24] 8010814: 041b lsls r3, r3, #16 8010816: 4313 orrs r3, r2 8010818: 60fb str r3, [r7, #12] #if defined(TIM_BDTR_BKBID) MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); #endif /* TIM_BDTR_BKBID */ if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) 801081a: 687b ldr r3, [r7, #4] 801081c: 681b ldr r3, [r3, #0] 801081e: 4a16 ldr r2, [pc, #88] @ (8010878 ) 8010820: 4293 cmp r3, r2 8010822: d004 beq.n 801082e 8010824: 687b ldr r3, [r7, #4] 8010826: 681b ldr r3, [r3, #0] 8010828: 4a14 ldr r2, [pc, #80] @ (801087c ) 801082a: 4293 cmp r3, r2 801082c: d115 bne.n 801085a #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); #endif /* TIM_BDTR_BKBID */ /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); 801082e: 68fb ldr r3, [r7, #12] 8010830: f423 0270 bic.w r2, r3, #15728640 @ 0xf00000 8010834: 683b ldr r3, [r7, #0] 8010836: 6a5b ldr r3, [r3, #36] @ 0x24 8010838: 051b lsls r3, r3, #20 801083a: 4313 orrs r3, r2 801083c: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); 801083e: 68fb ldr r3, [r7, #12] 8010840: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000 8010844: 683b ldr r3, [r7, #0] 8010846: 69db ldr r3, [r3, #28] 8010848: 4313 orrs r3, r2 801084a: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); 801084c: 68fb ldr r3, [r7, #12] 801084e: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000 8010852: 683b ldr r3, [r7, #0] 8010854: 6a1b ldr r3, [r3, #32] 8010856: 4313 orrs r3, r2 8010858: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); #endif /* TIM_BDTR_BKBID */ } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; 801085a: 687b ldr r3, [r7, #4] 801085c: 681b ldr r3, [r3, #0] 801085e: 68fa ldr r2, [r7, #12] 8010860: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(htim); 8010862: 687b ldr r3, [r7, #4] 8010864: 2200 movs r2, #0 8010866: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 801086a: 2300 movs r3, #0 } 801086c: 4618 mov r0, r3 801086e: 3714 adds r7, #20 8010870: 46bd mov sp, r7 8010872: f85d 7b04 ldr.w r7, [sp], #4 8010876: 4770 bx lr 8010878: 40010000 .word 0x40010000 801087c: 40010400 .word 0x40010400 08010880 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8010880: b480 push {r7} 8010882: b083 sub sp, #12 8010884: af00 add r7, sp, #0 8010886: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8010888: bf00 nop 801088a: 370c adds r7, #12 801088c: 46bd mov sp, r7 801088e: f85d 7b04 ldr.w r7, [sp], #4 8010892: 4770 bx lr 08010894 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8010894: b480 push {r7} 8010896: b083 sub sp, #12 8010898: af00 add r7, sp, #0 801089a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 801089c: bf00 nop 801089e: 370c adds r7, #12 80108a0: 46bd mov sp, r7 80108a2: f85d 7b04 ldr.w r7, [sp], #4 80108a6: 4770 bx lr 080108a8 : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 80108a8: b480 push {r7} 80108aa: b083 sub sp, #12 80108ac: af00 add r7, sp, #0 80108ae: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 80108b0: bf00 nop 80108b2: 370c adds r7, #12 80108b4: 46bd mov sp, r7 80108b6: f85d 7b04 ldr.w r7, [sp], #4 80108ba: 4770 bx lr 080108bc : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 80108bc: b580 push {r7, lr} 80108be: b082 sub sp, #8 80108c0: af00 add r7, sp, #0 80108c2: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 80108c4: 687b ldr r3, [r7, #4] 80108c6: 2b00 cmp r3, #0 80108c8: d101 bne.n 80108ce { return HAL_ERROR; 80108ca: 2301 movs r3, #1 80108cc: e042 b.n 8010954 { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 80108ce: 687b ldr r3, [r7, #4] 80108d0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80108d4: 2b00 cmp r3, #0 80108d6: d106 bne.n 80108e6 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 80108d8: 687b ldr r3, [r7, #4] 80108da: 2200 movs r2, #0 80108dc: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 80108e0: 6878 ldr r0, [r7, #4] 80108e2: f7f3 fb1b bl 8003f1c #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 80108e6: 687b ldr r3, [r7, #4] 80108e8: 2224 movs r2, #36 @ 0x24 80108ea: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UART_DISABLE(huart); 80108ee: 687b ldr r3, [r7, #4] 80108f0: 681b ldr r3, [r3, #0] 80108f2: 681a ldr r2, [r3, #0] 80108f4: 687b ldr r3, [r7, #4] 80108f6: 681b ldr r3, [r3, #0] 80108f8: f022 0201 bic.w r2, r2, #1 80108fc: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 80108fe: 687b ldr r3, [r7, #4] 8010900: 6a9b ldr r3, [r3, #40] @ 0x28 8010902: 2b00 cmp r3, #0 8010904: d002 beq.n 801090c { UART_AdvFeatureConfig(huart); 8010906: 6878 ldr r0, [r7, #4] 8010908: f001 f9e8 bl 8011cdc } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 801090c: 6878 ldr r0, [r7, #4] 801090e: f000 fc7d bl 801120c 8010912: 4603 mov r3, r0 8010914: 2b01 cmp r3, #1 8010916: d101 bne.n 801091c { return HAL_ERROR; 8010918: 2301 movs r3, #1 801091a: e01b b.n 8010954 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 801091c: 687b ldr r3, [r7, #4] 801091e: 681b ldr r3, [r3, #0] 8010920: 685a ldr r2, [r3, #4] 8010922: 687b ldr r3, [r7, #4] 8010924: 681b ldr r3, [r3, #0] 8010926: f422 4290 bic.w r2, r2, #18432 @ 0x4800 801092a: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 801092c: 687b ldr r3, [r7, #4] 801092e: 681b ldr r3, [r3, #0] 8010930: 689a ldr r2, [r3, #8] 8010932: 687b ldr r3, [r7, #4] 8010934: 681b ldr r3, [r3, #0] 8010936: f022 022a bic.w r2, r2, #42 @ 0x2a 801093a: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 801093c: 687b ldr r3, [r7, #4] 801093e: 681b ldr r3, [r3, #0] 8010940: 681a ldr r2, [r3, #0] 8010942: 687b ldr r3, [r7, #4] 8010944: 681b ldr r3, [r3, #0] 8010946: f042 0201 orr.w r2, r2, #1 801094a: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 801094c: 6878 ldr r0, [r7, #4] 801094e: f001 fa67 bl 8011e20 8010952: 4603 mov r3, r0 } 8010954: 4618 mov r0, r3 8010956: 3708 adds r7, #8 8010958: 46bd mov sp, r7 801095a: bd80 pop {r7, pc} 0801095c : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 801095c: b480 push {r7} 801095e: b091 sub sp, #68 @ 0x44 8010960: af00 add r7, sp, #0 8010962: 60f8 str r0, [r7, #12] 8010964: 60b9 str r1, [r7, #8] 8010966: 4613 mov r3, r2 8010968: 80fb strh r3, [r7, #6] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 801096a: 68fb ldr r3, [r7, #12] 801096c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8010970: 2b20 cmp r3, #32 8010972: d178 bne.n 8010a66 { if ((pData == NULL) || (Size == 0U)) 8010974: 68bb ldr r3, [r7, #8] 8010976: 2b00 cmp r3, #0 8010978: d002 beq.n 8010980 801097a: 88fb ldrh r3, [r7, #6] 801097c: 2b00 cmp r3, #0 801097e: d101 bne.n 8010984 { return HAL_ERROR; 8010980: 2301 movs r3, #1 8010982: e071 b.n 8010a68 } huart->pTxBuffPtr = pData; 8010984: 68fb ldr r3, [r7, #12] 8010986: 68ba ldr r2, [r7, #8] 8010988: 651a str r2, [r3, #80] @ 0x50 huart->TxXferSize = Size; 801098a: 68fb ldr r3, [r7, #12] 801098c: 88fa ldrh r2, [r7, #6] 801098e: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 huart->TxXferCount = Size; 8010992: 68fb ldr r3, [r7, #12] 8010994: 88fa ldrh r2, [r7, #6] 8010996: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 huart->TxISR = NULL; 801099a: 68fb ldr r3, [r7, #12] 801099c: 2200 movs r2, #0 801099e: 679a str r2, [r3, #120] @ 0x78 huart->ErrorCode = HAL_UART_ERROR_NONE; 80109a0: 68fb ldr r3, [r7, #12] 80109a2: 2200 movs r2, #0 80109a4: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->gState = HAL_UART_STATE_BUSY_TX; 80109a8: 68fb ldr r3, [r7, #12] 80109aa: 2221 movs r2, #33 @ 0x21 80109ac: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Configure Tx interrupt processing */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) 80109b0: 68fb ldr r3, [r7, #12] 80109b2: 6e5b ldr r3, [r3, #100] @ 0x64 80109b4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80109b8: d12a bne.n 8010a10 { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80109ba: 68fb ldr r3, [r7, #12] 80109bc: 689b ldr r3, [r3, #8] 80109be: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80109c2: d107 bne.n 80109d4 80109c4: 68fb ldr r3, [r7, #12] 80109c6: 691b ldr r3, [r3, #16] 80109c8: 2b00 cmp r3, #0 80109ca: d103 bne.n 80109d4 { huart->TxISR = UART_TxISR_16BIT_FIFOEN; 80109cc: 68fb ldr r3, [r7, #12] 80109ce: 4a29 ldr r2, [pc, #164] @ (8010a74 ) 80109d0: 679a str r2, [r3, #120] @ 0x78 80109d2: e002 b.n 80109da } else { huart->TxISR = UART_TxISR_8BIT_FIFOEN; 80109d4: 68fb ldr r3, [r7, #12] 80109d6: 4a28 ldr r2, [pc, #160] @ (8010a78 ) 80109d8: 679a str r2, [r3, #120] @ 0x78 } /* Enable the TX FIFO threshold interrupt */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 80109da: 68fb ldr r3, [r7, #12] 80109dc: 681b ldr r3, [r3, #0] 80109de: 3308 adds r3, #8 80109e0: 62bb str r3, [r7, #40] @ 0x28 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80109e2: 6abb ldr r3, [r7, #40] @ 0x28 80109e4: e853 3f00 ldrex r3, [r3] 80109e8: 627b str r3, [r7, #36] @ 0x24 return(result); 80109ea: 6a7b ldr r3, [r7, #36] @ 0x24 80109ec: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 80109f0: 63bb str r3, [r7, #56] @ 0x38 80109f2: 68fb ldr r3, [r7, #12] 80109f4: 681b ldr r3, [r3, #0] 80109f6: 3308 adds r3, #8 80109f8: 6bba ldr r2, [r7, #56] @ 0x38 80109fa: 637a str r2, [r7, #52] @ 0x34 80109fc: 633b str r3, [r7, #48] @ 0x30 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80109fe: 6b39 ldr r1, [r7, #48] @ 0x30 8010a00: 6b7a ldr r2, [r7, #52] @ 0x34 8010a02: e841 2300 strex r3, r2, [r1] 8010a06: 62fb str r3, [r7, #44] @ 0x2c return(result); 8010a08: 6afb ldr r3, [r7, #44] @ 0x2c 8010a0a: 2b00 cmp r3, #0 8010a0c: d1e5 bne.n 80109da 8010a0e: e028 b.n 8010a62 } else { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8010a10: 68fb ldr r3, [r7, #12] 8010a12: 689b ldr r3, [r3, #8] 8010a14: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8010a18: d107 bne.n 8010a2a 8010a1a: 68fb ldr r3, [r7, #12] 8010a1c: 691b ldr r3, [r3, #16] 8010a1e: 2b00 cmp r3, #0 8010a20: d103 bne.n 8010a2a { huart->TxISR = UART_TxISR_16BIT; 8010a22: 68fb ldr r3, [r7, #12] 8010a24: 4a15 ldr r2, [pc, #84] @ (8010a7c ) 8010a26: 679a str r2, [r3, #120] @ 0x78 8010a28: e002 b.n 8010a30 } else { huart->TxISR = UART_TxISR_8BIT; 8010a2a: 68fb ldr r3, [r7, #12] 8010a2c: 4a14 ldr r2, [pc, #80] @ (8010a80 ) 8010a2e: 679a str r2, [r3, #120] @ 0x78 } /* Enable the Transmit Data Register Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8010a30: 68fb ldr r3, [r7, #12] 8010a32: 681b ldr r3, [r3, #0] 8010a34: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010a36: 697b ldr r3, [r7, #20] 8010a38: e853 3f00 ldrex r3, [r3] 8010a3c: 613b str r3, [r7, #16] return(result); 8010a3e: 693b ldr r3, [r7, #16] 8010a40: f043 0380 orr.w r3, r3, #128 @ 0x80 8010a44: 63fb str r3, [r7, #60] @ 0x3c 8010a46: 68fb ldr r3, [r7, #12] 8010a48: 681b ldr r3, [r3, #0] 8010a4a: 461a mov r2, r3 8010a4c: 6bfb ldr r3, [r7, #60] @ 0x3c 8010a4e: 623b str r3, [r7, #32] 8010a50: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010a52: 69f9 ldr r1, [r7, #28] 8010a54: 6a3a ldr r2, [r7, #32] 8010a56: e841 2300 strex r3, r2, [r1] 8010a5a: 61bb str r3, [r7, #24] return(result); 8010a5c: 69bb ldr r3, [r7, #24] 8010a5e: 2b00 cmp r3, #0 8010a60: d1e6 bne.n 8010a30 } return HAL_OK; 8010a62: 2300 movs r3, #0 8010a64: e000 b.n 8010a68 } else { return HAL_BUSY; 8010a66: 2302 movs r3, #2 } } 8010a68: 4618 mov r0, r3 8010a6a: 3744 adds r7, #68 @ 0x44 8010a6c: 46bd mov sp, r7 8010a6e: f85d 7b04 ldr.w r7, [sp], #4 8010a72: 4770 bx lr 8010a74: 080125e7 .word 0x080125e7 8010a78: 08012507 .word 0x08012507 8010a7c: 08012445 .word 0x08012445 8010a80: 0801238d .word 0x0801238d 08010a84 : * @brief Handle UART interrupt request. * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8010a84: b580 push {r7, lr} 8010a86: b0ba sub sp, #232 @ 0xe8 8010a88: af00 add r7, sp, #0 8010a8a: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->ISR); 8010a8c: 687b ldr r3, [r7, #4] 8010a8e: 681b ldr r3, [r3, #0] 8010a90: 69db ldr r3, [r3, #28] 8010a92: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8010a96: 687b ldr r3, [r7, #4] 8010a98: 681b ldr r3, [r3, #0] 8010a9a: 681b ldr r3, [r3, #0] 8010a9c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8010aa0: 687b ldr r3, [r7, #4] 8010aa2: 681b ldr r3, [r3, #0] 8010aa4: 689b ldr r3, [r3, #8] 8010aa6: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags; uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); 8010aaa: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4 8010aae: f640 030f movw r3, #2063 @ 0x80f 8010ab2: 4013 ands r3, r2 8010ab4: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == 0U) 8010ab8: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8010abc: 2b00 cmp r3, #0 8010abe: d11b bne.n 8010af8 { /* UART in mode Receiver ---------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 8010ac0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010ac4: f003 0320 and.w r3, r3, #32 8010ac8: 2b00 cmp r3, #0 8010aca: d015 beq.n 8010af8 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 8010acc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010ad0: f003 0320 and.w r3, r3, #32 8010ad4: 2b00 cmp r3, #0 8010ad6: d105 bne.n 8010ae4 || ((cr3its & USART_CR3_RXFTIE) != 0U))) 8010ad8: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8010adc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010ae0: 2b00 cmp r3, #0 8010ae2: d009 beq.n 8010af8 { if (huart->RxISR != NULL) 8010ae4: 687b ldr r3, [r7, #4] 8010ae6: 6f5b ldr r3, [r3, #116] @ 0x74 8010ae8: 2b00 cmp r3, #0 8010aea: f000 8377 beq.w 80111dc { huart->RxISR(huart); 8010aee: 687b ldr r3, [r7, #4] 8010af0: 6f5b ldr r3, [r3, #116] @ 0x74 8010af2: 6878 ldr r0, [r7, #4] 8010af4: 4798 blx r3 } return; 8010af6: e371 b.n 80111dc } } /* If some errors occur */ if ((errorflags != 0U) 8010af8: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8010afc: 2b00 cmp r3, #0 8010afe: f000 8123 beq.w 8010d48 && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) 8010b02: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 8010b06: 4b8d ldr r3, [pc, #564] @ (8010d3c ) 8010b08: 4013 ands r3, r2 8010b0a: 2b00 cmp r3, #0 8010b0c: d106 bne.n 8010b1c || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) 8010b0e: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0 8010b12: 4b8b ldr r3, [pc, #556] @ (8010d40 ) 8010b14: 4013 ands r3, r2 8010b16: 2b00 cmp r3, #0 8010b18: f000 8116 beq.w 8010d48 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8010b1c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010b20: f003 0301 and.w r3, r3, #1 8010b24: 2b00 cmp r3, #0 8010b26: d011 beq.n 8010b4c 8010b28: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010b2c: f403 7380 and.w r3, r3, #256 @ 0x100 8010b30: 2b00 cmp r3, #0 8010b32: d00b beq.n 8010b4c { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8010b34: 687b ldr r3, [r7, #4] 8010b36: 681b ldr r3, [r3, #0] 8010b38: 2201 movs r2, #1 8010b3a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8010b3c: 687b ldr r3, [r7, #4] 8010b3e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010b42: f043 0201 orr.w r2, r3, #1 8010b46: 687b ldr r3, [r7, #4] 8010b48: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8010b4c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010b50: f003 0302 and.w r3, r3, #2 8010b54: 2b00 cmp r3, #0 8010b56: d011 beq.n 8010b7c 8010b58: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8010b5c: f003 0301 and.w r3, r3, #1 8010b60: 2b00 cmp r3, #0 8010b62: d00b beq.n 8010b7c { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8010b64: 687b ldr r3, [r7, #4] 8010b66: 681b ldr r3, [r3, #0] 8010b68: 2202 movs r2, #2 8010b6a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8010b6c: 687b ldr r3, [r7, #4] 8010b6e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010b72: f043 0204 orr.w r2, r3, #4 8010b76: 687b ldr r3, [r7, #4] 8010b78: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8010b7c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010b80: f003 0304 and.w r3, r3, #4 8010b84: 2b00 cmp r3, #0 8010b86: d011 beq.n 8010bac 8010b88: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8010b8c: f003 0301 and.w r3, r3, #1 8010b90: 2b00 cmp r3, #0 8010b92: d00b beq.n 8010bac { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8010b94: 687b ldr r3, [r7, #4] 8010b96: 681b ldr r3, [r3, #0] 8010b98: 2204 movs r2, #4 8010b9a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8010b9c: 687b ldr r3, [r7, #4] 8010b9e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010ba2: f043 0202 orr.w r2, r3, #2 8010ba6: 687b ldr r3, [r7, #4] 8010ba8: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Over-Run interrupt occurred -----------------------------------------*/ if (((isrflags & USART_ISR_ORE) != 0U) 8010bac: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010bb0: f003 0308 and.w r3, r3, #8 8010bb4: 2b00 cmp r3, #0 8010bb6: d017 beq.n 8010be8 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 8010bb8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010bbc: f003 0320 and.w r3, r3, #32 8010bc0: 2b00 cmp r3, #0 8010bc2: d105 bne.n 8010bd0 ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) 8010bc4: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 8010bc8: 4b5c ldr r3, [pc, #368] @ (8010d3c ) 8010bca: 4013 ands r3, r2 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 8010bcc: 2b00 cmp r3, #0 8010bce: d00b beq.n 8010be8 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8010bd0: 687b ldr r3, [r7, #4] 8010bd2: 681b ldr r3, [r3, #0] 8010bd4: 2208 movs r2, #8 8010bd6: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_ORE; 8010bd8: 687b ldr r3, [r7, #4] 8010bda: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010bde: f043 0208 orr.w r2, r3, #8 8010be2: 687b ldr r3, [r7, #4] 8010be4: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Receiver Timeout interrupt occurred ---------------------------------*/ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) 8010be8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010bec: f403 6300 and.w r3, r3, #2048 @ 0x800 8010bf0: 2b00 cmp r3, #0 8010bf2: d012 beq.n 8010c1a 8010bf4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010bf8: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8010bfc: 2b00 cmp r3, #0 8010bfe: d00c beq.n 8010c1a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8010c00: 687b ldr r3, [r7, #4] 8010c02: 681b ldr r3, [r3, #0] 8010c04: f44f 6200 mov.w r2, #2048 @ 0x800 8010c08: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_RTO; 8010c0a: 687b ldr r3, [r7, #4] 8010c0c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010c10: f043 0220 orr.w r2, r3, #32 8010c14: 687b ldr r3, [r7, #4] 8010c16: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8010c1a: 687b ldr r3, [r7, #4] 8010c1c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010c20: 2b00 cmp r3, #0 8010c22: f000 82dd beq.w 80111e0 { /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 8010c26: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010c2a: f003 0320 and.w r3, r3, #32 8010c2e: 2b00 cmp r3, #0 8010c30: d013 beq.n 8010c5a && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 8010c32: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010c36: f003 0320 and.w r3, r3, #32 8010c3a: 2b00 cmp r3, #0 8010c3c: d105 bne.n 8010c4a || ((cr3its & USART_CR3_RXFTIE) != 0U))) 8010c3e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8010c42: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010c46: 2b00 cmp r3, #0 8010c48: d007 beq.n 8010c5a { if (huart->RxISR != NULL) 8010c4a: 687b ldr r3, [r7, #4] 8010c4c: 6f5b ldr r3, [r3, #116] @ 0x74 8010c4e: 2b00 cmp r3, #0 8010c50: d003 beq.n 8010c5a { huart->RxISR(huart); 8010c52: 687b ldr r3, [r7, #4] 8010c54: 6f5b ldr r3, [r3, #116] @ 0x74 8010c56: 6878 ldr r0, [r7, #4] 8010c58: 4798 blx r3 /* If Error is to be considered as blocking : - Receiver Timeout error in Reception - Overrun error in Reception - any error occurs in DMA mode reception */ errorcode = huart->ErrorCode; 8010c5a: 687b ldr r3, [r7, #4] 8010c5c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010c60: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8010c64: 687b ldr r3, [r7, #4] 8010c66: 681b ldr r3, [r3, #0] 8010c68: 689b ldr r3, [r3, #8] 8010c6a: f003 0340 and.w r3, r3, #64 @ 0x40 8010c6e: 2b40 cmp r3, #64 @ 0x40 8010c70: d005 beq.n 8010c7e ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) 8010c72: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8010c76: f003 0328 and.w r3, r3, #40 @ 0x28 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8010c7a: 2b00 cmp r3, #0 8010c7c: d054 beq.n 8010d28 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8010c7e: 6878 ldr r0, [r7, #4] 8010c80: f001 fb08 bl 8012294 /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010c84: 687b ldr r3, [r7, #4] 8010c86: 681b ldr r3, [r3, #0] 8010c88: 689b ldr r3, [r3, #8] 8010c8a: f003 0340 and.w r3, r3, #64 @ 0x40 8010c8e: 2b40 cmp r3, #64 @ 0x40 8010c90: d146 bne.n 8010d20 { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8010c92: 687b ldr r3, [r7, #4] 8010c94: 681b ldr r3, [r3, #0] 8010c96: 3308 adds r3, #8 8010c98: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010c9c: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8010ca0: e853 3f00 ldrex r3, [r3] 8010ca4: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8010ca8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8010cac: f023 0340 bic.w r3, r3, #64 @ 0x40 8010cb0: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8010cb4: 687b ldr r3, [r7, #4] 8010cb6: 681b ldr r3, [r3, #0] 8010cb8: 3308 adds r3, #8 8010cba: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8010cbe: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8010cc2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010cc6: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8010cca: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8010cce: e841 2300 strex r3, r2, [r1] 8010cd2: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8010cd6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8010cda: 2b00 cmp r3, #0 8010cdc: d1d9 bne.n 8010c92 /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 8010cde: 687b ldr r3, [r7, #4] 8010ce0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010ce4: 2b00 cmp r3, #0 8010ce6: d017 beq.n 8010d18 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8010ce8: 687b ldr r3, [r7, #4] 8010cea: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010cee: 4a15 ldr r2, [pc, #84] @ (8010d44 ) 8010cf0: 651a str r2, [r3, #80] @ 0x50 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8010cf2: 687b ldr r3, [r7, #4] 8010cf4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010cf8: 4618 mov r0, r3 8010cfa: f7f8 fb41 bl 8009380 8010cfe: 4603 mov r3, r0 8010d00: 2b00 cmp r3, #0 8010d02: d019 beq.n 8010d38 { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8010d04: 687b ldr r3, [r7, #4] 8010d06: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010d0a: 6d1b ldr r3, [r3, #80] @ 0x50 8010d0c: 687a ldr r2, [r7, #4] 8010d0e: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80 8010d12: 4610 mov r0, r2 8010d14: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010d16: e00f b.n 8010d38 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8010d18: 6878 ldr r0, [r7, #4] 8010d1a: f000 fa6d bl 80111f8 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010d1e: e00b b.n 8010d38 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8010d20: 6878 ldr r0, [r7, #4] 8010d22: f000 fa69 bl 80111f8 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010d26: e007 b.n 8010d38 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8010d28: 6878 ldr r0, [r7, #4] 8010d2a: f000 fa65 bl 80111f8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8010d2e: 687b ldr r3, [r7, #4] 8010d30: 2200 movs r2, #0 8010d32: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } return; 8010d36: e253 b.n 80111e0 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010d38: bf00 nop return; 8010d3a: e251 b.n 80111e0 8010d3c: 10000001 .word 0x10000001 8010d40: 04000120 .word 0x04000120 8010d44: 08012361 .word 0x08012361 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8010d48: 687b ldr r3, [r7, #4] 8010d4a: 6edb ldr r3, [r3, #108] @ 0x6c 8010d4c: 2b01 cmp r3, #1 8010d4e: f040 81e7 bne.w 8011120 && ((isrflags & USART_ISR_IDLE) != 0U) 8010d52: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010d56: f003 0310 and.w r3, r3, #16 8010d5a: 2b00 cmp r3, #0 8010d5c: f000 81e0 beq.w 8011120 && ((cr1its & USART_ISR_IDLE) != 0U)) 8010d60: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010d64: f003 0310 and.w r3, r3, #16 8010d68: 2b00 cmp r3, #0 8010d6a: f000 81d9 beq.w 8011120 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8010d6e: 687b ldr r3, [r7, #4] 8010d70: 681b ldr r3, [r3, #0] 8010d72: 2210 movs r2, #16 8010d74: 621a str r2, [r3, #32] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010d76: 687b ldr r3, [r7, #4] 8010d78: 681b ldr r3, [r3, #0] 8010d7a: 689b ldr r3, [r3, #8] 8010d7c: f003 0340 and.w r3, r3, #64 @ 0x40 8010d80: 2b40 cmp r3, #64 @ 0x40 8010d82: f040 8151 bne.w 8011028 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8010d86: 687b ldr r3, [r7, #4] 8010d88: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010d8c: 681b ldr r3, [r3, #0] 8010d8e: 4a96 ldr r2, [pc, #600] @ (8010fe8 ) 8010d90: 4293 cmp r3, r2 8010d92: d068 beq.n 8010e66 8010d94: 687b ldr r3, [r7, #4] 8010d96: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010d9a: 681b ldr r3, [r3, #0] 8010d9c: 4a93 ldr r2, [pc, #588] @ (8010fec ) 8010d9e: 4293 cmp r3, r2 8010da0: d061 beq.n 8010e66 8010da2: 687b ldr r3, [r7, #4] 8010da4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010da8: 681b ldr r3, [r3, #0] 8010daa: 4a91 ldr r2, [pc, #580] @ (8010ff0 ) 8010dac: 4293 cmp r3, r2 8010dae: d05a beq.n 8010e66 8010db0: 687b ldr r3, [r7, #4] 8010db2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010db6: 681b ldr r3, [r3, #0] 8010db8: 4a8e ldr r2, [pc, #568] @ (8010ff4 ) 8010dba: 4293 cmp r3, r2 8010dbc: d053 beq.n 8010e66 8010dbe: 687b ldr r3, [r7, #4] 8010dc0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010dc4: 681b ldr r3, [r3, #0] 8010dc6: 4a8c ldr r2, [pc, #560] @ (8010ff8 ) 8010dc8: 4293 cmp r3, r2 8010dca: d04c beq.n 8010e66 8010dcc: 687b ldr r3, [r7, #4] 8010dce: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010dd2: 681b ldr r3, [r3, #0] 8010dd4: 4a89 ldr r2, [pc, #548] @ (8010ffc ) 8010dd6: 4293 cmp r3, r2 8010dd8: d045 beq.n 8010e66 8010dda: 687b ldr r3, [r7, #4] 8010ddc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010de0: 681b ldr r3, [r3, #0] 8010de2: 4a87 ldr r2, [pc, #540] @ (8011000 ) 8010de4: 4293 cmp r3, r2 8010de6: d03e beq.n 8010e66 8010de8: 687b ldr r3, [r7, #4] 8010dea: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010dee: 681b ldr r3, [r3, #0] 8010df0: 4a84 ldr r2, [pc, #528] @ (8011004 ) 8010df2: 4293 cmp r3, r2 8010df4: d037 beq.n 8010e66 8010df6: 687b ldr r3, [r7, #4] 8010df8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010dfc: 681b ldr r3, [r3, #0] 8010dfe: 4a82 ldr r2, [pc, #520] @ (8011008 ) 8010e00: 4293 cmp r3, r2 8010e02: d030 beq.n 8010e66 8010e04: 687b ldr r3, [r7, #4] 8010e06: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e0a: 681b ldr r3, [r3, #0] 8010e0c: 4a7f ldr r2, [pc, #508] @ (801100c ) 8010e0e: 4293 cmp r3, r2 8010e10: d029 beq.n 8010e66 8010e12: 687b ldr r3, [r7, #4] 8010e14: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e18: 681b ldr r3, [r3, #0] 8010e1a: 4a7d ldr r2, [pc, #500] @ (8011010 ) 8010e1c: 4293 cmp r3, r2 8010e1e: d022 beq.n 8010e66 8010e20: 687b ldr r3, [r7, #4] 8010e22: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e26: 681b ldr r3, [r3, #0] 8010e28: 4a7a ldr r2, [pc, #488] @ (8011014 ) 8010e2a: 4293 cmp r3, r2 8010e2c: d01b beq.n 8010e66 8010e2e: 687b ldr r3, [r7, #4] 8010e30: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e34: 681b ldr r3, [r3, #0] 8010e36: 4a78 ldr r2, [pc, #480] @ (8011018 ) 8010e38: 4293 cmp r3, r2 8010e3a: d014 beq.n 8010e66 8010e3c: 687b ldr r3, [r7, #4] 8010e3e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e42: 681b ldr r3, [r3, #0] 8010e44: 4a75 ldr r2, [pc, #468] @ (801101c ) 8010e46: 4293 cmp r3, r2 8010e48: d00d beq.n 8010e66 8010e4a: 687b ldr r3, [r7, #4] 8010e4c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e50: 681b ldr r3, [r3, #0] 8010e52: 4a73 ldr r2, [pc, #460] @ (8011020 ) 8010e54: 4293 cmp r3, r2 8010e56: d006 beq.n 8010e66 8010e58: 687b ldr r3, [r7, #4] 8010e5a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e5e: 681b ldr r3, [r3, #0] 8010e60: 4a70 ldr r2, [pc, #448] @ (8011024 ) 8010e62: 4293 cmp r3, r2 8010e64: d106 bne.n 8010e74 8010e66: 687b ldr r3, [r7, #4] 8010e68: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e6c: 681b ldr r3, [r3, #0] 8010e6e: 685b ldr r3, [r3, #4] 8010e70: b29b uxth r3, r3 8010e72: e005 b.n 8010e80 8010e74: 687b ldr r3, [r7, #4] 8010e76: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e7a: 681b ldr r3, [r3, #0] 8010e7c: 685b ldr r3, [r3, #4] 8010e7e: b29b uxth r3, r3 8010e80: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8010e84: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8010e88: 2b00 cmp r3, #0 8010e8a: f000 81ab beq.w 80111e4 && (nb_remaining_rx_data < huart->RxXferSize)) 8010e8e: 687b ldr r3, [r7, #4] 8010e90: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8010e94: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8010e98: 429a cmp r2, r3 8010e9a: f080 81a3 bcs.w 80111e4 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8010e9e: 687b ldr r3, [r7, #4] 8010ea0: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8010ea4: f8a3 205e strh.w r2, [r3, #94] @ 0x5e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8010ea8: 687b ldr r3, [r7, #4] 8010eaa: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010eae: 69db ldr r3, [r3, #28] 8010eb0: f5b3 7f80 cmp.w r3, #256 @ 0x100 8010eb4: f000 8087 beq.w 8010fc6 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8010eb8: 687b ldr r3, [r7, #4] 8010eba: 681b ldr r3, [r3, #0] 8010ebc: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010ec0: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8010ec4: e853 3f00 ldrex r3, [r3] 8010ec8: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8010ecc: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8010ed0: f423 7380 bic.w r3, r3, #256 @ 0x100 8010ed4: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8010ed8: 687b ldr r3, [r7, #4] 8010eda: 681b ldr r3, [r3, #0] 8010edc: 461a mov r2, r3 8010ede: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 8010ee2: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8010ee6: f8c7 2090 str.w r2, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010eea: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8010eee: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8010ef2: e841 2300 strex r3, r2, [r1] 8010ef6: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8010efa: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8010efe: 2b00 cmp r3, #0 8010f00: d1da bne.n 8010eb8 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8010f02: 687b ldr r3, [r7, #4] 8010f04: 681b ldr r3, [r3, #0] 8010f06: 3308 adds r3, #8 8010f08: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010f0a: 6f7b ldr r3, [r7, #116] @ 0x74 8010f0c: e853 3f00 ldrex r3, [r3] 8010f10: 673b str r3, [r7, #112] @ 0x70 return(result); 8010f12: 6f3b ldr r3, [r7, #112] @ 0x70 8010f14: f023 0301 bic.w r3, r3, #1 8010f18: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8010f1c: 687b ldr r3, [r7, #4] 8010f1e: 681b ldr r3, [r3, #0] 8010f20: 3308 adds r3, #8 8010f22: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8010f26: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8010f2a: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010f2c: 6ff9 ldr r1, [r7, #124] @ 0x7c 8010f2e: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8010f32: e841 2300 strex r3, r2, [r1] 8010f36: 67bb str r3, [r7, #120] @ 0x78 return(result); 8010f38: 6fbb ldr r3, [r7, #120] @ 0x78 8010f3a: 2b00 cmp r3, #0 8010f3c: d1e1 bne.n 8010f02 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8010f3e: 687b ldr r3, [r7, #4] 8010f40: 681b ldr r3, [r3, #0] 8010f42: 3308 adds r3, #8 8010f44: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010f46: 6e3b ldr r3, [r7, #96] @ 0x60 8010f48: e853 3f00 ldrex r3, [r3] 8010f4c: 65fb str r3, [r7, #92] @ 0x5c return(result); 8010f4e: 6dfb ldr r3, [r7, #92] @ 0x5c 8010f50: f023 0340 bic.w r3, r3, #64 @ 0x40 8010f54: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8010f58: 687b ldr r3, [r7, #4] 8010f5a: 681b ldr r3, [r3, #0] 8010f5c: 3308 adds r3, #8 8010f5e: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8010f62: 66fa str r2, [r7, #108] @ 0x6c 8010f64: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010f66: 6eb9 ldr r1, [r7, #104] @ 0x68 8010f68: 6efa ldr r2, [r7, #108] @ 0x6c 8010f6a: e841 2300 strex r3, r2, [r1] 8010f6e: 667b str r3, [r7, #100] @ 0x64 return(result); 8010f70: 6e7b ldr r3, [r7, #100] @ 0x64 8010f72: 2b00 cmp r3, #0 8010f74: d1e3 bne.n 8010f3e /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8010f76: 687b ldr r3, [r7, #4] 8010f78: 2220 movs r2, #32 8010f7a: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8010f7e: 687b ldr r3, [r7, #4] 8010f80: 2200 movs r2, #0 8010f82: 66da str r2, [r3, #108] @ 0x6c ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8010f84: 687b ldr r3, [r7, #4] 8010f86: 681b ldr r3, [r3, #0] 8010f88: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010f8a: 6cfb ldr r3, [r7, #76] @ 0x4c 8010f8c: e853 3f00 ldrex r3, [r3] 8010f90: 64bb str r3, [r7, #72] @ 0x48 return(result); 8010f92: 6cbb ldr r3, [r7, #72] @ 0x48 8010f94: f023 0310 bic.w r3, r3, #16 8010f98: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8010f9c: 687b ldr r3, [r7, #4] 8010f9e: 681b ldr r3, [r3, #0] 8010fa0: 461a mov r2, r3 8010fa2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010fa6: 65bb str r3, [r7, #88] @ 0x58 8010fa8: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010faa: 6d79 ldr r1, [r7, #84] @ 0x54 8010fac: 6dba ldr r2, [r7, #88] @ 0x58 8010fae: e841 2300 strex r3, r2, [r1] 8010fb2: 653b str r3, [r7, #80] @ 0x50 return(result); 8010fb4: 6d3b ldr r3, [r7, #80] @ 0x50 8010fb6: 2b00 cmp r3, #0 8010fb8: d1e4 bne.n 8010f84 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8010fba: 687b ldr r3, [r7, #4] 8010fbc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010fc0: 4618 mov r0, r3 8010fc2: f7f7 febf bl 8008d44 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8010fc6: 687b ldr r3, [r7, #4] 8010fc8: 2202 movs r2, #2 8010fca: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8010fcc: 687b ldr r3, [r7, #4] 8010fce: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 8010fd2: 687b ldr r3, [r7, #4] 8010fd4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8010fd8: b29b uxth r3, r3 8010fda: 1ad3 subs r3, r2, r3 8010fdc: b29b uxth r3, r3 8010fde: 4619 mov r1, r3 8010fe0: 6878 ldr r0, [r7, #4] 8010fe2: f7f3 fb3f bl 8004664 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 8010fe6: e0fd b.n 80111e4 8010fe8: 40020010 .word 0x40020010 8010fec: 40020028 .word 0x40020028 8010ff0: 40020040 .word 0x40020040 8010ff4: 40020058 .word 0x40020058 8010ff8: 40020070 .word 0x40020070 8010ffc: 40020088 .word 0x40020088 8011000: 400200a0 .word 0x400200a0 8011004: 400200b8 .word 0x400200b8 8011008: 40020410 .word 0x40020410 801100c: 40020428 .word 0x40020428 8011010: 40020440 .word 0x40020440 8011014: 40020458 .word 0x40020458 8011018: 40020470 .word 0x40020470 801101c: 40020488 .word 0x40020488 8011020: 400204a0 .word 0x400204a0 8011024: 400204b8 .word 0x400204b8 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8011028: 687b ldr r3, [r7, #4] 801102a: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 801102e: 687b ldr r3, [r7, #4] 8011030: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011034: b29b uxth r3, r3 8011036: 1ad3 subs r3, r2, r3 8011038: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 801103c: 687b ldr r3, [r7, #4] 801103e: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011042: b29b uxth r3, r3 8011044: 2b00 cmp r3, #0 8011046: f000 80cf beq.w 80111e8 && (nb_rx_data > 0U)) 801104a: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 801104e: 2b00 cmp r3, #0 8011050: f000 80ca beq.w 80111e8 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8011054: 687b ldr r3, [r7, #4] 8011056: 681b ldr r3, [r3, #0] 8011058: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801105a: 6bbb ldr r3, [r7, #56] @ 0x38 801105c: e853 3f00 ldrex r3, [r3] 8011060: 637b str r3, [r7, #52] @ 0x34 return(result); 8011062: 6b7b ldr r3, [r7, #52] @ 0x34 8011064: f423 7390 bic.w r3, r3, #288 @ 0x120 8011068: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 801106c: 687b ldr r3, [r7, #4] 801106e: 681b ldr r3, [r3, #0] 8011070: 461a mov r2, r3 8011072: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 8011076: 647b str r3, [r7, #68] @ 0x44 8011078: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801107a: 6c39 ldr r1, [r7, #64] @ 0x40 801107c: 6c7a ldr r2, [r7, #68] @ 0x44 801107e: e841 2300 strex r3, r2, [r1] 8011082: 63fb str r3, [r7, #60] @ 0x3c return(result); 8011084: 6bfb ldr r3, [r7, #60] @ 0x3c 8011086: 2b00 cmp r3, #0 8011088: d1e4 bne.n 8011054 /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 801108a: 687b ldr r3, [r7, #4] 801108c: 681b ldr r3, [r3, #0] 801108e: 3308 adds r3, #8 8011090: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011092: 6a7b ldr r3, [r7, #36] @ 0x24 8011094: e853 3f00 ldrex r3, [r3] 8011098: 623b str r3, [r7, #32] return(result); 801109a: 6a3a ldr r2, [r7, #32] 801109c: 4b55 ldr r3, [pc, #340] @ (80111f4 ) 801109e: 4013 ands r3, r2 80110a0: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 80110a4: 687b ldr r3, [r7, #4] 80110a6: 681b ldr r3, [r3, #0] 80110a8: 3308 adds r3, #8 80110aa: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 80110ae: 633a str r2, [r7, #48] @ 0x30 80110b0: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80110b2: 6af9 ldr r1, [r7, #44] @ 0x2c 80110b4: 6b3a ldr r2, [r7, #48] @ 0x30 80110b6: e841 2300 strex r3, r2, [r1] 80110ba: 62bb str r3, [r7, #40] @ 0x28 return(result); 80110bc: 6abb ldr r3, [r7, #40] @ 0x28 80110be: 2b00 cmp r3, #0 80110c0: d1e3 bne.n 801108a /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80110c2: 687b ldr r3, [r7, #4] 80110c4: 2220 movs r2, #32 80110c6: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80110ca: 687b ldr r3, [r7, #4] 80110cc: 2200 movs r2, #0 80110ce: 66da str r2, [r3, #108] @ 0x6c /* Clear RxISR function pointer */ huart->RxISR = NULL; 80110d0: 687b ldr r3, [r7, #4] 80110d2: 2200 movs r2, #0 80110d4: 675a str r2, [r3, #116] @ 0x74 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80110d6: 687b ldr r3, [r7, #4] 80110d8: 681b ldr r3, [r3, #0] 80110da: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80110dc: 693b ldr r3, [r7, #16] 80110de: e853 3f00 ldrex r3, [r3] 80110e2: 60fb str r3, [r7, #12] return(result); 80110e4: 68fb ldr r3, [r7, #12] 80110e6: f023 0310 bic.w r3, r3, #16 80110ea: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 80110ee: 687b ldr r3, [r7, #4] 80110f0: 681b ldr r3, [r3, #0] 80110f2: 461a mov r2, r3 80110f4: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 80110f8: 61fb str r3, [r7, #28] 80110fa: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80110fc: 69b9 ldr r1, [r7, #24] 80110fe: 69fa ldr r2, [r7, #28] 8011100: e841 2300 strex r3, r2, [r1] 8011104: 617b str r3, [r7, #20] return(result); 8011106: 697b ldr r3, [r7, #20] 8011108: 2b00 cmp r3, #0 801110a: d1e4 bne.n 80110d6 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 801110c: 687b ldr r3, [r7, #4] 801110e: 2202 movs r2, #2 8011110: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8011112: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8011116: 4619 mov r1, r3 8011118: 6878 ldr r0, [r7, #4] 801111a: f7f3 faa3 bl 8004664 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 801111e: e063 b.n 80111e8 } } /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) 8011120: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011124: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8011128: 2b00 cmp r3, #0 801112a: d00e beq.n 801114a 801112c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011130: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8011134: 2b00 cmp r3, #0 8011136: d008 beq.n 801114a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); 8011138: 687b ldr r3, [r7, #4] 801113a: 681b ldr r3, [r3, #0] 801113c: f44f 1280 mov.w r2, #1048576 @ 0x100000 8011140: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Wakeup Callback */ huart->WakeupCallback(huart); #else /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); 8011142: 6878 ldr r0, [r7, #4] 8011144: f002 f80c bl 8013160 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8011148: e051 b.n 80111ee } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) 801114a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801114e: f003 0380 and.w r3, r3, #128 @ 0x80 8011152: 2b00 cmp r3, #0 8011154: d014 beq.n 8011180 && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) 8011156: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801115a: f003 0380 and.w r3, r3, #128 @ 0x80 801115e: 2b00 cmp r3, #0 8011160: d105 bne.n 801116e || ((cr3its & USART_CR3_TXFTIE) != 0U))) 8011162: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011166: f403 0300 and.w r3, r3, #8388608 @ 0x800000 801116a: 2b00 cmp r3, #0 801116c: d008 beq.n 8011180 { if (huart->TxISR != NULL) 801116e: 687b ldr r3, [r7, #4] 8011170: 6f9b ldr r3, [r3, #120] @ 0x78 8011172: 2b00 cmp r3, #0 8011174: d03a beq.n 80111ec { huart->TxISR(huart); 8011176: 687b ldr r3, [r7, #4] 8011178: 6f9b ldr r3, [r3, #120] @ 0x78 801117a: 6878 ldr r0, [r7, #4] 801117c: 4798 blx r3 } return; 801117e: e035 b.n 80111ec } /* UART in mode Transmitter (transmission end) -----------------------------*/ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) 8011180: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011184: f003 0340 and.w r3, r3, #64 @ 0x40 8011188: 2b00 cmp r3, #0 801118a: d009 beq.n 80111a0 801118c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011190: f003 0340 and.w r3, r3, #64 @ 0x40 8011194: 2b00 cmp r3, #0 8011196: d003 beq.n 80111a0 { UART_EndTransmit_IT(huart); 8011198: 6878 ldr r0, [r7, #4] 801119a: f001 fa99 bl 80126d0 return; 801119e: e026 b.n 80111ee } /* UART TX Fifo Empty occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) 80111a0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80111a4: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80111a8: 2b00 cmp r3, #0 80111aa: d009 beq.n 80111c0 80111ac: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80111b0: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 80111b4: 2b00 cmp r3, #0 80111b6: d003 beq.n 80111c0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ huart->TxFifoEmptyCallback(huart); #else /* Call legacy weak Tx Fifo Empty Callback */ HAL_UARTEx_TxFifoEmptyCallback(huart); 80111b8: 6878 ldr r0, [r7, #4] 80111ba: f001 ffe5 bl 8013188 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 80111be: e016 b.n 80111ee } /* UART RX Fifo Full occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) 80111c0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80111c4: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80111c8: 2b00 cmp r3, #0 80111ca: d010 beq.n 80111ee 80111cc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80111d0: 2b00 cmp r3, #0 80111d2: da0c bge.n 80111ee #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ huart->RxFifoFullCallback(huart); #else /* Call legacy weak Rx Fifo Full Callback */ HAL_UARTEx_RxFifoFullCallback(huart); 80111d4: 6878 ldr r0, [r7, #4] 80111d6: f001 ffcd bl 8013174 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 80111da: e008 b.n 80111ee return; 80111dc: bf00 nop 80111de: e006 b.n 80111ee return; 80111e0: bf00 nop 80111e2: e004 b.n 80111ee return; 80111e4: bf00 nop 80111e6: e002 b.n 80111ee return; 80111e8: bf00 nop 80111ea: e000 b.n 80111ee return; 80111ec: bf00 nop } } 80111ee: 37e8 adds r7, #232 @ 0xe8 80111f0: 46bd mov sp, r7 80111f2: bd80 pop {r7, pc} 80111f4: effffffe .word 0xeffffffe 080111f8 : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 80111f8: b480 push {r7} 80111fa: b083 sub sp, #12 80111fc: af00 add r7, sp, #0 80111fe: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } 8011200: bf00 nop 8011202: 370c adds r7, #12 8011204: 46bd mov sp, r7 8011206: f85d 7b04 ldr.w r7, [sp], #4 801120a: 4770 bx lr 0801120c : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 801120c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8011210: b092 sub sp, #72 @ 0x48 8011212: af00 add r7, sp, #0 8011214: 6178 str r0, [r7, #20] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 8011216: 2300 movs r3, #0 8011218: f887 3042 strb.w r3, [r7, #66] @ 0x42 * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 801121c: 697b ldr r3, [r7, #20] 801121e: 689a ldr r2, [r3, #8] 8011220: 697b ldr r3, [r7, #20] 8011222: 691b ldr r3, [r3, #16] 8011224: 431a orrs r2, r3 8011226: 697b ldr r3, [r7, #20] 8011228: 695b ldr r3, [r3, #20] 801122a: 431a orrs r2, r3 801122c: 697b ldr r3, [r7, #20] 801122e: 69db ldr r3, [r3, #28] 8011230: 4313 orrs r3, r2 8011232: 647b str r3, [r7, #68] @ 0x44 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 8011234: 697b ldr r3, [r7, #20] 8011236: 681b ldr r3, [r3, #0] 8011238: 681a ldr r2, [r3, #0] 801123a: 4bbe ldr r3, [pc, #760] @ (8011534 ) 801123c: 4013 ands r3, r2 801123e: 697a ldr r2, [r7, #20] 8011240: 6812 ldr r2, [r2, #0] 8011242: 6c79 ldr r1, [r7, #68] @ 0x44 8011244: 430b orrs r3, r1 8011246: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8011248: 697b ldr r3, [r7, #20] 801124a: 681b ldr r3, [r3, #0] 801124c: 685b ldr r3, [r3, #4] 801124e: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8011252: 697b ldr r3, [r7, #20] 8011254: 68da ldr r2, [r3, #12] 8011256: 697b ldr r3, [r7, #20] 8011258: 681b ldr r3, [r3, #0] 801125a: 430a orrs r2, r1 801125c: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 801125e: 697b ldr r3, [r7, #20] 8011260: 699b ldr r3, [r3, #24] 8011262: 647b str r3, [r7, #68] @ 0x44 if (!(UART_INSTANCE_LOWPOWER(huart))) 8011264: 697b ldr r3, [r7, #20] 8011266: 681b ldr r3, [r3, #0] 8011268: 4ab3 ldr r2, [pc, #716] @ (8011538 ) 801126a: 4293 cmp r3, r2 801126c: d004 beq.n 8011278 { tmpreg |= huart->Init.OneBitSampling; 801126e: 697b ldr r3, [r7, #20] 8011270: 6a1b ldr r3, [r3, #32] 8011272: 6c7a ldr r2, [r7, #68] @ 0x44 8011274: 4313 orrs r3, r2 8011276: 647b str r3, [r7, #68] @ 0x44 } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 8011278: 697b ldr r3, [r7, #20] 801127a: 681b ldr r3, [r3, #0] 801127c: 689a ldr r2, [r3, #8] 801127e: 4baf ldr r3, [pc, #700] @ (801153c ) 8011280: 4013 ands r3, r2 8011282: 697a ldr r2, [r7, #20] 8011284: 6812 ldr r2, [r2, #0] 8011286: 6c79 ldr r1, [r7, #68] @ 0x44 8011288: 430b orrs r3, r1 801128a: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 801128c: 697b ldr r3, [r7, #20] 801128e: 681b ldr r3, [r3, #0] 8011290: 6adb ldr r3, [r3, #44] @ 0x2c 8011292: f023 010f bic.w r1, r3, #15 8011296: 697b ldr r3, [r7, #20] 8011298: 6a5a ldr r2, [r3, #36] @ 0x24 801129a: 697b ldr r3, [r7, #20] 801129c: 681b ldr r3, [r3, #0] 801129e: 430a orrs r2, r1 80112a0: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 80112a2: 697b ldr r3, [r7, #20] 80112a4: 681b ldr r3, [r3, #0] 80112a6: 4aa6 ldr r2, [pc, #664] @ (8011540 ) 80112a8: 4293 cmp r3, r2 80112aa: d177 bne.n 801139c 80112ac: 4ba5 ldr r3, [pc, #660] @ (8011544 ) 80112ae: 6d5b ldr r3, [r3, #84] @ 0x54 80112b0: f003 0338 and.w r3, r3, #56 @ 0x38 80112b4: 2b28 cmp r3, #40 @ 0x28 80112b6: d86d bhi.n 8011394 80112b8: a201 add r2, pc, #4 @ (adr r2, 80112c0 ) 80112ba: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80112be: bf00 nop 80112c0: 08011365 .word 0x08011365 80112c4: 08011395 .word 0x08011395 80112c8: 08011395 .word 0x08011395 80112cc: 08011395 .word 0x08011395 80112d0: 08011395 .word 0x08011395 80112d4: 08011395 .word 0x08011395 80112d8: 08011395 .word 0x08011395 80112dc: 08011395 .word 0x08011395 80112e0: 0801136d .word 0x0801136d 80112e4: 08011395 .word 0x08011395 80112e8: 08011395 .word 0x08011395 80112ec: 08011395 .word 0x08011395 80112f0: 08011395 .word 0x08011395 80112f4: 08011395 .word 0x08011395 80112f8: 08011395 .word 0x08011395 80112fc: 08011395 .word 0x08011395 8011300: 08011375 .word 0x08011375 8011304: 08011395 .word 0x08011395 8011308: 08011395 .word 0x08011395 801130c: 08011395 .word 0x08011395 8011310: 08011395 .word 0x08011395 8011314: 08011395 .word 0x08011395 8011318: 08011395 .word 0x08011395 801131c: 08011395 .word 0x08011395 8011320: 0801137d .word 0x0801137d 8011324: 08011395 .word 0x08011395 8011328: 08011395 .word 0x08011395 801132c: 08011395 .word 0x08011395 8011330: 08011395 .word 0x08011395 8011334: 08011395 .word 0x08011395 8011338: 08011395 .word 0x08011395 801133c: 08011395 .word 0x08011395 8011340: 08011385 .word 0x08011385 8011344: 08011395 .word 0x08011395 8011348: 08011395 .word 0x08011395 801134c: 08011395 .word 0x08011395 8011350: 08011395 .word 0x08011395 8011354: 08011395 .word 0x08011395 8011358: 08011395 .word 0x08011395 801135c: 08011395 .word 0x08011395 8011360: 0801138d .word 0x0801138d 8011364: 2301 movs r3, #1 8011366: f887 3043 strb.w r3, [r7, #67] @ 0x43 801136a: e222 b.n 80117b2 801136c: 2304 movs r3, #4 801136e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011372: e21e b.n 80117b2 8011374: 2308 movs r3, #8 8011376: f887 3043 strb.w r3, [r7, #67] @ 0x43 801137a: e21a b.n 80117b2 801137c: 2310 movs r3, #16 801137e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011382: e216 b.n 80117b2 8011384: 2320 movs r3, #32 8011386: f887 3043 strb.w r3, [r7, #67] @ 0x43 801138a: e212 b.n 80117b2 801138c: 2340 movs r3, #64 @ 0x40 801138e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011392: e20e b.n 80117b2 8011394: 2380 movs r3, #128 @ 0x80 8011396: f887 3043 strb.w r3, [r7, #67] @ 0x43 801139a: e20a b.n 80117b2 801139c: 697b ldr r3, [r7, #20] 801139e: 681b ldr r3, [r3, #0] 80113a0: 4a69 ldr r2, [pc, #420] @ (8011548 ) 80113a2: 4293 cmp r3, r2 80113a4: d130 bne.n 8011408 80113a6: 4b67 ldr r3, [pc, #412] @ (8011544 ) 80113a8: 6d5b ldr r3, [r3, #84] @ 0x54 80113aa: f003 0307 and.w r3, r3, #7 80113ae: 2b05 cmp r3, #5 80113b0: d826 bhi.n 8011400 80113b2: a201 add r2, pc, #4 @ (adr r2, 80113b8 ) 80113b4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80113b8: 080113d1 .word 0x080113d1 80113bc: 080113d9 .word 0x080113d9 80113c0: 080113e1 .word 0x080113e1 80113c4: 080113e9 .word 0x080113e9 80113c8: 080113f1 .word 0x080113f1 80113cc: 080113f9 .word 0x080113f9 80113d0: 2300 movs r3, #0 80113d2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80113d6: e1ec b.n 80117b2 80113d8: 2304 movs r3, #4 80113da: f887 3043 strb.w r3, [r7, #67] @ 0x43 80113de: e1e8 b.n 80117b2 80113e0: 2308 movs r3, #8 80113e2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80113e6: e1e4 b.n 80117b2 80113e8: 2310 movs r3, #16 80113ea: f887 3043 strb.w r3, [r7, #67] @ 0x43 80113ee: e1e0 b.n 80117b2 80113f0: 2320 movs r3, #32 80113f2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80113f6: e1dc b.n 80117b2 80113f8: 2340 movs r3, #64 @ 0x40 80113fa: f887 3043 strb.w r3, [r7, #67] @ 0x43 80113fe: e1d8 b.n 80117b2 8011400: 2380 movs r3, #128 @ 0x80 8011402: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011406: e1d4 b.n 80117b2 8011408: 697b ldr r3, [r7, #20] 801140a: 681b ldr r3, [r3, #0] 801140c: 4a4f ldr r2, [pc, #316] @ (801154c ) 801140e: 4293 cmp r3, r2 8011410: d130 bne.n 8011474 8011412: 4b4c ldr r3, [pc, #304] @ (8011544 ) 8011414: 6d5b ldr r3, [r3, #84] @ 0x54 8011416: f003 0307 and.w r3, r3, #7 801141a: 2b05 cmp r3, #5 801141c: d826 bhi.n 801146c 801141e: a201 add r2, pc, #4 @ (adr r2, 8011424 ) 8011420: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011424: 0801143d .word 0x0801143d 8011428: 08011445 .word 0x08011445 801142c: 0801144d .word 0x0801144d 8011430: 08011455 .word 0x08011455 8011434: 0801145d .word 0x0801145d 8011438: 08011465 .word 0x08011465 801143c: 2300 movs r3, #0 801143e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011442: e1b6 b.n 80117b2 8011444: 2304 movs r3, #4 8011446: f887 3043 strb.w r3, [r7, #67] @ 0x43 801144a: e1b2 b.n 80117b2 801144c: 2308 movs r3, #8 801144e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011452: e1ae b.n 80117b2 8011454: 2310 movs r3, #16 8011456: f887 3043 strb.w r3, [r7, #67] @ 0x43 801145a: e1aa b.n 80117b2 801145c: 2320 movs r3, #32 801145e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011462: e1a6 b.n 80117b2 8011464: 2340 movs r3, #64 @ 0x40 8011466: f887 3043 strb.w r3, [r7, #67] @ 0x43 801146a: e1a2 b.n 80117b2 801146c: 2380 movs r3, #128 @ 0x80 801146e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011472: e19e b.n 80117b2 8011474: 697b ldr r3, [r7, #20] 8011476: 681b ldr r3, [r3, #0] 8011478: 4a35 ldr r2, [pc, #212] @ (8011550 ) 801147a: 4293 cmp r3, r2 801147c: d130 bne.n 80114e0 801147e: 4b31 ldr r3, [pc, #196] @ (8011544 ) 8011480: 6d5b ldr r3, [r3, #84] @ 0x54 8011482: f003 0307 and.w r3, r3, #7 8011486: 2b05 cmp r3, #5 8011488: d826 bhi.n 80114d8 801148a: a201 add r2, pc, #4 @ (adr r2, 8011490 ) 801148c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011490: 080114a9 .word 0x080114a9 8011494: 080114b1 .word 0x080114b1 8011498: 080114b9 .word 0x080114b9 801149c: 080114c1 .word 0x080114c1 80114a0: 080114c9 .word 0x080114c9 80114a4: 080114d1 .word 0x080114d1 80114a8: 2300 movs r3, #0 80114aa: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114ae: e180 b.n 80117b2 80114b0: 2304 movs r3, #4 80114b2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114b6: e17c b.n 80117b2 80114b8: 2308 movs r3, #8 80114ba: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114be: e178 b.n 80117b2 80114c0: 2310 movs r3, #16 80114c2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114c6: e174 b.n 80117b2 80114c8: 2320 movs r3, #32 80114ca: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114ce: e170 b.n 80117b2 80114d0: 2340 movs r3, #64 @ 0x40 80114d2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114d6: e16c b.n 80117b2 80114d8: 2380 movs r3, #128 @ 0x80 80114da: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114de: e168 b.n 80117b2 80114e0: 697b ldr r3, [r7, #20] 80114e2: 681b ldr r3, [r3, #0] 80114e4: 4a1b ldr r2, [pc, #108] @ (8011554 ) 80114e6: 4293 cmp r3, r2 80114e8: d142 bne.n 8011570 80114ea: 4b16 ldr r3, [pc, #88] @ (8011544 ) 80114ec: 6d5b ldr r3, [r3, #84] @ 0x54 80114ee: f003 0307 and.w r3, r3, #7 80114f2: 2b05 cmp r3, #5 80114f4: d838 bhi.n 8011568 80114f6: a201 add r2, pc, #4 @ (adr r2, 80114fc ) 80114f8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80114fc: 08011515 .word 0x08011515 8011500: 0801151d .word 0x0801151d 8011504: 08011525 .word 0x08011525 8011508: 0801152d .word 0x0801152d 801150c: 08011559 .word 0x08011559 8011510: 08011561 .word 0x08011561 8011514: 2300 movs r3, #0 8011516: f887 3043 strb.w r3, [r7, #67] @ 0x43 801151a: e14a b.n 80117b2 801151c: 2304 movs r3, #4 801151e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011522: e146 b.n 80117b2 8011524: 2308 movs r3, #8 8011526: f887 3043 strb.w r3, [r7, #67] @ 0x43 801152a: e142 b.n 80117b2 801152c: 2310 movs r3, #16 801152e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011532: e13e b.n 80117b2 8011534: cfff69f3 .word 0xcfff69f3 8011538: 58000c00 .word 0x58000c00 801153c: 11fff4ff .word 0x11fff4ff 8011540: 40011000 .word 0x40011000 8011544: 58024400 .word 0x58024400 8011548: 40004400 .word 0x40004400 801154c: 40004800 .word 0x40004800 8011550: 40004c00 .word 0x40004c00 8011554: 40005000 .word 0x40005000 8011558: 2320 movs r3, #32 801155a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801155e: e128 b.n 80117b2 8011560: 2340 movs r3, #64 @ 0x40 8011562: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011566: e124 b.n 80117b2 8011568: 2380 movs r3, #128 @ 0x80 801156a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801156e: e120 b.n 80117b2 8011570: 697b ldr r3, [r7, #20] 8011572: 681b ldr r3, [r3, #0] 8011574: 4acb ldr r2, [pc, #812] @ (80118a4 ) 8011576: 4293 cmp r3, r2 8011578: d176 bne.n 8011668 801157a: 4bcb ldr r3, [pc, #812] @ (80118a8 ) 801157c: 6d5b ldr r3, [r3, #84] @ 0x54 801157e: f003 0338 and.w r3, r3, #56 @ 0x38 8011582: 2b28 cmp r3, #40 @ 0x28 8011584: d86c bhi.n 8011660 8011586: a201 add r2, pc, #4 @ (adr r2, 801158c ) 8011588: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801158c: 08011631 .word 0x08011631 8011590: 08011661 .word 0x08011661 8011594: 08011661 .word 0x08011661 8011598: 08011661 .word 0x08011661 801159c: 08011661 .word 0x08011661 80115a0: 08011661 .word 0x08011661 80115a4: 08011661 .word 0x08011661 80115a8: 08011661 .word 0x08011661 80115ac: 08011639 .word 0x08011639 80115b0: 08011661 .word 0x08011661 80115b4: 08011661 .word 0x08011661 80115b8: 08011661 .word 0x08011661 80115bc: 08011661 .word 0x08011661 80115c0: 08011661 .word 0x08011661 80115c4: 08011661 .word 0x08011661 80115c8: 08011661 .word 0x08011661 80115cc: 08011641 .word 0x08011641 80115d0: 08011661 .word 0x08011661 80115d4: 08011661 .word 0x08011661 80115d8: 08011661 .word 0x08011661 80115dc: 08011661 .word 0x08011661 80115e0: 08011661 .word 0x08011661 80115e4: 08011661 .word 0x08011661 80115e8: 08011661 .word 0x08011661 80115ec: 08011649 .word 0x08011649 80115f0: 08011661 .word 0x08011661 80115f4: 08011661 .word 0x08011661 80115f8: 08011661 .word 0x08011661 80115fc: 08011661 .word 0x08011661 8011600: 08011661 .word 0x08011661 8011604: 08011661 .word 0x08011661 8011608: 08011661 .word 0x08011661 801160c: 08011651 .word 0x08011651 8011610: 08011661 .word 0x08011661 8011614: 08011661 .word 0x08011661 8011618: 08011661 .word 0x08011661 801161c: 08011661 .word 0x08011661 8011620: 08011661 .word 0x08011661 8011624: 08011661 .word 0x08011661 8011628: 08011661 .word 0x08011661 801162c: 08011659 .word 0x08011659 8011630: 2301 movs r3, #1 8011632: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011636: e0bc b.n 80117b2 8011638: 2304 movs r3, #4 801163a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801163e: e0b8 b.n 80117b2 8011640: 2308 movs r3, #8 8011642: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011646: e0b4 b.n 80117b2 8011648: 2310 movs r3, #16 801164a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801164e: e0b0 b.n 80117b2 8011650: 2320 movs r3, #32 8011652: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011656: e0ac b.n 80117b2 8011658: 2340 movs r3, #64 @ 0x40 801165a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801165e: e0a8 b.n 80117b2 8011660: 2380 movs r3, #128 @ 0x80 8011662: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011666: e0a4 b.n 80117b2 8011668: 697b ldr r3, [r7, #20] 801166a: 681b ldr r3, [r3, #0] 801166c: 4a8f ldr r2, [pc, #572] @ (80118ac ) 801166e: 4293 cmp r3, r2 8011670: d130 bne.n 80116d4 8011672: 4b8d ldr r3, [pc, #564] @ (80118a8 ) 8011674: 6d5b ldr r3, [r3, #84] @ 0x54 8011676: f003 0307 and.w r3, r3, #7 801167a: 2b05 cmp r3, #5 801167c: d826 bhi.n 80116cc 801167e: a201 add r2, pc, #4 @ (adr r2, 8011684 ) 8011680: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011684: 0801169d .word 0x0801169d 8011688: 080116a5 .word 0x080116a5 801168c: 080116ad .word 0x080116ad 8011690: 080116b5 .word 0x080116b5 8011694: 080116bd .word 0x080116bd 8011698: 080116c5 .word 0x080116c5 801169c: 2300 movs r3, #0 801169e: f887 3043 strb.w r3, [r7, #67] @ 0x43 80116a2: e086 b.n 80117b2 80116a4: 2304 movs r3, #4 80116a6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80116aa: e082 b.n 80117b2 80116ac: 2308 movs r3, #8 80116ae: f887 3043 strb.w r3, [r7, #67] @ 0x43 80116b2: e07e b.n 80117b2 80116b4: 2310 movs r3, #16 80116b6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80116ba: e07a b.n 80117b2 80116bc: 2320 movs r3, #32 80116be: f887 3043 strb.w r3, [r7, #67] @ 0x43 80116c2: e076 b.n 80117b2 80116c4: 2340 movs r3, #64 @ 0x40 80116c6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80116ca: e072 b.n 80117b2 80116cc: 2380 movs r3, #128 @ 0x80 80116ce: f887 3043 strb.w r3, [r7, #67] @ 0x43 80116d2: e06e b.n 80117b2 80116d4: 697b ldr r3, [r7, #20] 80116d6: 681b ldr r3, [r3, #0] 80116d8: 4a75 ldr r2, [pc, #468] @ (80118b0 ) 80116da: 4293 cmp r3, r2 80116dc: d130 bne.n 8011740 80116de: 4b72 ldr r3, [pc, #456] @ (80118a8 ) 80116e0: 6d5b ldr r3, [r3, #84] @ 0x54 80116e2: f003 0307 and.w r3, r3, #7 80116e6: 2b05 cmp r3, #5 80116e8: d826 bhi.n 8011738 80116ea: a201 add r2, pc, #4 @ (adr r2, 80116f0 ) 80116ec: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80116f0: 08011709 .word 0x08011709 80116f4: 08011711 .word 0x08011711 80116f8: 08011719 .word 0x08011719 80116fc: 08011721 .word 0x08011721 8011700: 08011729 .word 0x08011729 8011704: 08011731 .word 0x08011731 8011708: 2300 movs r3, #0 801170a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801170e: e050 b.n 80117b2 8011710: 2304 movs r3, #4 8011712: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011716: e04c b.n 80117b2 8011718: 2308 movs r3, #8 801171a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801171e: e048 b.n 80117b2 8011720: 2310 movs r3, #16 8011722: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011726: e044 b.n 80117b2 8011728: 2320 movs r3, #32 801172a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801172e: e040 b.n 80117b2 8011730: 2340 movs r3, #64 @ 0x40 8011732: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011736: e03c b.n 80117b2 8011738: 2380 movs r3, #128 @ 0x80 801173a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801173e: e038 b.n 80117b2 8011740: 697b ldr r3, [r7, #20] 8011742: 681b ldr r3, [r3, #0] 8011744: 4a5b ldr r2, [pc, #364] @ (80118b4 ) 8011746: 4293 cmp r3, r2 8011748: d130 bne.n 80117ac 801174a: 4b57 ldr r3, [pc, #348] @ (80118a8 ) 801174c: 6d9b ldr r3, [r3, #88] @ 0x58 801174e: f003 0307 and.w r3, r3, #7 8011752: 2b05 cmp r3, #5 8011754: d826 bhi.n 80117a4 8011756: a201 add r2, pc, #4 @ (adr r2, 801175c ) 8011758: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801175c: 08011775 .word 0x08011775 8011760: 0801177d .word 0x0801177d 8011764: 08011785 .word 0x08011785 8011768: 0801178d .word 0x0801178d 801176c: 08011795 .word 0x08011795 8011770: 0801179d .word 0x0801179d 8011774: 2302 movs r3, #2 8011776: f887 3043 strb.w r3, [r7, #67] @ 0x43 801177a: e01a b.n 80117b2 801177c: 2304 movs r3, #4 801177e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011782: e016 b.n 80117b2 8011784: 2308 movs r3, #8 8011786: f887 3043 strb.w r3, [r7, #67] @ 0x43 801178a: e012 b.n 80117b2 801178c: 2310 movs r3, #16 801178e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011792: e00e b.n 80117b2 8011794: 2320 movs r3, #32 8011796: f887 3043 strb.w r3, [r7, #67] @ 0x43 801179a: e00a b.n 80117b2 801179c: 2340 movs r3, #64 @ 0x40 801179e: f887 3043 strb.w r3, [r7, #67] @ 0x43 80117a2: e006 b.n 80117b2 80117a4: 2380 movs r3, #128 @ 0x80 80117a6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80117aa: e002 b.n 80117b2 80117ac: 2380 movs r3, #128 @ 0x80 80117ae: f887 3043 strb.w r3, [r7, #67] @ 0x43 /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 80117b2: 697b ldr r3, [r7, #20] 80117b4: 681b ldr r3, [r3, #0] 80117b6: 4a3f ldr r2, [pc, #252] @ (80118b4 ) 80117b8: 4293 cmp r3, r2 80117ba: f040 80f8 bne.w 80119ae { /* Retrieve frequency clock */ switch (clocksource) 80117be: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 80117c2: 2b20 cmp r3, #32 80117c4: dc46 bgt.n 8011854 80117c6: 2b02 cmp r3, #2 80117c8: f2c0 8082 blt.w 80118d0 80117cc: 3b02 subs r3, #2 80117ce: 2b1e cmp r3, #30 80117d0: d87e bhi.n 80118d0 80117d2: a201 add r2, pc, #4 @ (adr r2, 80117d8 ) 80117d4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80117d8: 0801185b .word 0x0801185b 80117dc: 080118d1 .word 0x080118d1 80117e0: 08011863 .word 0x08011863 80117e4: 080118d1 .word 0x080118d1 80117e8: 080118d1 .word 0x080118d1 80117ec: 080118d1 .word 0x080118d1 80117f0: 08011873 .word 0x08011873 80117f4: 080118d1 .word 0x080118d1 80117f8: 080118d1 .word 0x080118d1 80117fc: 080118d1 .word 0x080118d1 8011800: 080118d1 .word 0x080118d1 8011804: 080118d1 .word 0x080118d1 8011808: 080118d1 .word 0x080118d1 801180c: 080118d1 .word 0x080118d1 8011810: 08011883 .word 0x08011883 8011814: 080118d1 .word 0x080118d1 8011818: 080118d1 .word 0x080118d1 801181c: 080118d1 .word 0x080118d1 8011820: 080118d1 .word 0x080118d1 8011824: 080118d1 .word 0x080118d1 8011828: 080118d1 .word 0x080118d1 801182c: 080118d1 .word 0x080118d1 8011830: 080118d1 .word 0x080118d1 8011834: 080118d1 .word 0x080118d1 8011838: 080118d1 .word 0x080118d1 801183c: 080118d1 .word 0x080118d1 8011840: 080118d1 .word 0x080118d1 8011844: 080118d1 .word 0x080118d1 8011848: 080118d1 .word 0x080118d1 801184c: 080118d1 .word 0x080118d1 8011850: 080118c3 .word 0x080118c3 8011854: 2b40 cmp r3, #64 @ 0x40 8011856: d037 beq.n 80118c8 8011858: e03a b.n 80118d0 { case UART_CLOCKSOURCE_D3PCLK1: pclk = HAL_RCCEx_GetD3PCLK1Freq(); 801185a: f7fc fe3d bl 800e4d8 801185e: 63f8 str r0, [r7, #60] @ 0x3c break; 8011860: e03c b.n 80118dc case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8011862: f107 0324 add.w r3, r7, #36 @ 0x24 8011866: 4618 mov r0, r3 8011868: f7fc fe4c bl 800e504 pclk = pll2_clocks.PLL2_Q_Frequency; 801186c: 6abb ldr r3, [r7, #40] @ 0x28 801186e: 63fb str r3, [r7, #60] @ 0x3c break; 8011870: e034 b.n 80118dc case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8011872: f107 0318 add.w r3, r7, #24 8011876: 4618 mov r0, r3 8011878: f7fc ff98 bl 800e7ac pclk = pll3_clocks.PLL3_Q_Frequency; 801187c: 69fb ldr r3, [r7, #28] 801187e: 63fb str r3, [r7, #60] @ 0x3c break; 8011880: e02c b.n 80118dc case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8011882: 4b09 ldr r3, [pc, #36] @ (80118a8 ) 8011884: 681b ldr r3, [r3, #0] 8011886: f003 0320 and.w r3, r3, #32 801188a: 2b00 cmp r3, #0 801188c: d016 beq.n 80118bc { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 801188e: 4b06 ldr r3, [pc, #24] @ (80118a8 ) 8011890: 681b ldr r3, [r3, #0] 8011892: 08db lsrs r3, r3, #3 8011894: f003 0303 and.w r3, r3, #3 8011898: 4a07 ldr r2, [pc, #28] @ (80118b8 ) 801189a: fa22 f303 lsr.w r3, r2, r3 801189e: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 80118a0: e01c b.n 80118dc 80118a2: bf00 nop 80118a4: 40011400 .word 0x40011400 80118a8: 58024400 .word 0x58024400 80118ac: 40007800 .word 0x40007800 80118b0: 40007c00 .word 0x40007c00 80118b4: 58000c00 .word 0x58000c00 80118b8: 03d09000 .word 0x03d09000 pclk = (uint32_t) HSI_VALUE; 80118bc: 4b9d ldr r3, [pc, #628] @ (8011b34 ) 80118be: 63fb str r3, [r7, #60] @ 0x3c break; 80118c0: e00c b.n 80118dc case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 80118c2: 4b9d ldr r3, [pc, #628] @ (8011b38 ) 80118c4: 63fb str r3, [r7, #60] @ 0x3c break; 80118c6: e009 b.n 80118dc case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 80118c8: f44f 4300 mov.w r3, #32768 @ 0x8000 80118cc: 63fb str r3, [r7, #60] @ 0x3c break; 80118ce: e005 b.n 80118dc default: pclk = 0U; 80118d0: 2300 movs r3, #0 80118d2: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 80118d4: 2301 movs r3, #1 80118d6: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 80118da: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 80118dc: 6bfb ldr r3, [r7, #60] @ 0x3c 80118de: 2b00 cmp r3, #0 80118e0: f000 81de beq.w 8011ca0 { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 80118e4: 697b ldr r3, [r7, #20] 80118e6: 6a5b ldr r3, [r3, #36] @ 0x24 80118e8: 4a94 ldr r2, [pc, #592] @ (8011b3c ) 80118ea: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80118ee: 461a mov r2, r3 80118f0: 6bfb ldr r3, [r7, #60] @ 0x3c 80118f2: fbb3 f3f2 udiv r3, r3, r2 80118f6: 633b str r3, [r7, #48] @ 0x30 /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 80118f8: 697b ldr r3, [r7, #20] 80118fa: 685a ldr r2, [r3, #4] 80118fc: 4613 mov r3, r2 80118fe: 005b lsls r3, r3, #1 8011900: 4413 add r3, r2 8011902: 6b3a ldr r2, [r7, #48] @ 0x30 8011904: 429a cmp r2, r3 8011906: d305 bcc.n 8011914 (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) 8011908: 697b ldr r3, [r7, #20] 801190a: 685b ldr r3, [r3, #4] 801190c: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 801190e: 6b3a ldr r2, [r7, #48] @ 0x30 8011910: 429a cmp r2, r3 8011912: d903 bls.n 801191c { ret = HAL_ERROR; 8011914: 2301 movs r3, #1 8011916: f887 3042 strb.w r3, [r7, #66] @ 0x42 801191a: e1c1 b.n 8011ca0 } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 801191c: 6bfb ldr r3, [r7, #60] @ 0x3c 801191e: 2200 movs r2, #0 8011920: 60bb str r3, [r7, #8] 8011922: 60fa str r2, [r7, #12] 8011924: 697b ldr r3, [r7, #20] 8011926: 6a5b ldr r3, [r3, #36] @ 0x24 8011928: 4a84 ldr r2, [pc, #528] @ (8011b3c ) 801192a: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 801192e: b29b uxth r3, r3 8011930: 2200 movs r2, #0 8011932: 603b str r3, [r7, #0] 8011934: 607a str r2, [r7, #4] 8011936: e9d7 2300 ldrd r2, r3, [r7] 801193a: e9d7 0102 ldrd r0, r1, [r7, #8] 801193e: f7ee fd27 bl 8000390 <__aeabi_uldivmod> 8011942: 4602 mov r2, r0 8011944: 460b mov r3, r1 8011946: 4610 mov r0, r2 8011948: 4619 mov r1, r3 801194a: f04f 0200 mov.w r2, #0 801194e: f04f 0300 mov.w r3, #0 8011952: 020b lsls r3, r1, #8 8011954: ea43 6310 orr.w r3, r3, r0, lsr #24 8011958: 0202 lsls r2, r0, #8 801195a: 6979 ldr r1, [r7, #20] 801195c: 6849 ldr r1, [r1, #4] 801195e: 0849 lsrs r1, r1, #1 8011960: 2000 movs r0, #0 8011962: 460c mov r4, r1 8011964: 4605 mov r5, r0 8011966: eb12 0804 adds.w r8, r2, r4 801196a: eb43 0905 adc.w r9, r3, r5 801196e: 697b ldr r3, [r7, #20] 8011970: 685b ldr r3, [r3, #4] 8011972: 2200 movs r2, #0 8011974: 469a mov sl, r3 8011976: 4693 mov fp, r2 8011978: 4652 mov r2, sl 801197a: 465b mov r3, fp 801197c: 4640 mov r0, r8 801197e: 4649 mov r1, r9 8011980: f7ee fd06 bl 8000390 <__aeabi_uldivmod> 8011984: 4602 mov r2, r0 8011986: 460b mov r3, r1 8011988: 4613 mov r3, r2 801198a: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 801198c: 6bbb ldr r3, [r7, #56] @ 0x38 801198e: f5b3 7f40 cmp.w r3, #768 @ 0x300 8011992: d308 bcc.n 80119a6 8011994: 6bbb ldr r3, [r7, #56] @ 0x38 8011996: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 801199a: d204 bcs.n 80119a6 { huart->Instance->BRR = usartdiv; 801199c: 697b ldr r3, [r7, #20] 801199e: 681b ldr r3, [r3, #0] 80119a0: 6bba ldr r2, [r7, #56] @ 0x38 80119a2: 60da str r2, [r3, #12] 80119a4: e17c b.n 8011ca0 } else { ret = HAL_ERROR; 80119a6: 2301 movs r3, #1 80119a8: f887 3042 strb.w r3, [r7, #66] @ 0x42 80119ac: e178 b.n 8011ca0 } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 80119ae: 697b ldr r3, [r7, #20] 80119b0: 69db ldr r3, [r3, #28] 80119b2: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 80119b6: f040 80c5 bne.w 8011b44 { switch (clocksource) 80119ba: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 80119be: 2b20 cmp r3, #32 80119c0: dc48 bgt.n 8011a54 80119c2: 2b00 cmp r3, #0 80119c4: db7b blt.n 8011abe 80119c6: 2b20 cmp r3, #32 80119c8: d879 bhi.n 8011abe 80119ca: a201 add r2, pc, #4 @ (adr r2, 80119d0 ) 80119cc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80119d0: 08011a5b .word 0x08011a5b 80119d4: 08011a63 .word 0x08011a63 80119d8: 08011abf .word 0x08011abf 80119dc: 08011abf .word 0x08011abf 80119e0: 08011a6b .word 0x08011a6b 80119e4: 08011abf .word 0x08011abf 80119e8: 08011abf .word 0x08011abf 80119ec: 08011abf .word 0x08011abf 80119f0: 08011a7b .word 0x08011a7b 80119f4: 08011abf .word 0x08011abf 80119f8: 08011abf .word 0x08011abf 80119fc: 08011abf .word 0x08011abf 8011a00: 08011abf .word 0x08011abf 8011a04: 08011abf .word 0x08011abf 8011a08: 08011abf .word 0x08011abf 8011a0c: 08011abf .word 0x08011abf 8011a10: 08011a8b .word 0x08011a8b 8011a14: 08011abf .word 0x08011abf 8011a18: 08011abf .word 0x08011abf 8011a1c: 08011abf .word 0x08011abf 8011a20: 08011abf .word 0x08011abf 8011a24: 08011abf .word 0x08011abf 8011a28: 08011abf .word 0x08011abf 8011a2c: 08011abf .word 0x08011abf 8011a30: 08011abf .word 0x08011abf 8011a34: 08011abf .word 0x08011abf 8011a38: 08011abf .word 0x08011abf 8011a3c: 08011abf .word 0x08011abf 8011a40: 08011abf .word 0x08011abf 8011a44: 08011abf .word 0x08011abf 8011a48: 08011abf .word 0x08011abf 8011a4c: 08011abf .word 0x08011abf 8011a50: 08011ab1 .word 0x08011ab1 8011a54: 2b40 cmp r3, #64 @ 0x40 8011a56: d02e beq.n 8011ab6 8011a58: e031 b.n 8011abe { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8011a5a: f7fa fd61 bl 800c520 8011a5e: 63f8 str r0, [r7, #60] @ 0x3c break; 8011a60: e033 b.n 8011aca case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8011a62: f7fa fd73 bl 800c54c 8011a66: 63f8 str r0, [r7, #60] @ 0x3c break; 8011a68: e02f b.n 8011aca case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8011a6a: f107 0324 add.w r3, r7, #36 @ 0x24 8011a6e: 4618 mov r0, r3 8011a70: f7fc fd48 bl 800e504 pclk = pll2_clocks.PLL2_Q_Frequency; 8011a74: 6abb ldr r3, [r7, #40] @ 0x28 8011a76: 63fb str r3, [r7, #60] @ 0x3c break; 8011a78: e027 b.n 8011aca case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8011a7a: f107 0318 add.w r3, r7, #24 8011a7e: 4618 mov r0, r3 8011a80: f7fc fe94 bl 800e7ac pclk = pll3_clocks.PLL3_Q_Frequency; 8011a84: 69fb ldr r3, [r7, #28] 8011a86: 63fb str r3, [r7, #60] @ 0x3c break; 8011a88: e01f b.n 8011aca case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8011a8a: 4b2d ldr r3, [pc, #180] @ (8011b40 ) 8011a8c: 681b ldr r3, [r3, #0] 8011a8e: f003 0320 and.w r3, r3, #32 8011a92: 2b00 cmp r3, #0 8011a94: d009 beq.n 8011aaa { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8011a96: 4b2a ldr r3, [pc, #168] @ (8011b40 ) 8011a98: 681b ldr r3, [r3, #0] 8011a9a: 08db lsrs r3, r3, #3 8011a9c: f003 0303 and.w r3, r3, #3 8011aa0: 4a24 ldr r2, [pc, #144] @ (8011b34 ) 8011aa2: fa22 f303 lsr.w r3, r2, r3 8011aa6: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8011aa8: e00f b.n 8011aca pclk = (uint32_t) HSI_VALUE; 8011aaa: 4b22 ldr r3, [pc, #136] @ (8011b34 ) 8011aac: 63fb str r3, [r7, #60] @ 0x3c break; 8011aae: e00c b.n 8011aca case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 8011ab0: 4b21 ldr r3, [pc, #132] @ (8011b38 ) 8011ab2: 63fb str r3, [r7, #60] @ 0x3c break; 8011ab4: e009 b.n 8011aca case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8011ab6: f44f 4300 mov.w r3, #32768 @ 0x8000 8011aba: 63fb str r3, [r7, #60] @ 0x3c break; 8011abc: e005 b.n 8011aca default: pclk = 0U; 8011abe: 2300 movs r3, #0 8011ac0: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 8011ac2: 2301 movs r3, #1 8011ac4: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 8011ac8: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 8011aca: 6bfb ldr r3, [r7, #60] @ 0x3c 8011acc: 2b00 cmp r3, #0 8011ace: f000 80e7 beq.w 8011ca0 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8011ad2: 697b ldr r3, [r7, #20] 8011ad4: 6a5b ldr r3, [r3, #36] @ 0x24 8011ad6: 4a19 ldr r2, [pc, #100] @ (8011b3c ) 8011ad8: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8011adc: 461a mov r2, r3 8011ade: 6bfb ldr r3, [r7, #60] @ 0x3c 8011ae0: fbb3 f3f2 udiv r3, r3, r2 8011ae4: 005a lsls r2, r3, #1 8011ae6: 697b ldr r3, [r7, #20] 8011ae8: 685b ldr r3, [r3, #4] 8011aea: 085b lsrs r3, r3, #1 8011aec: 441a add r2, r3 8011aee: 697b ldr r3, [r7, #20] 8011af0: 685b ldr r3, [r3, #4] 8011af2: fbb2 f3f3 udiv r3, r2, r3 8011af6: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8011af8: 6bbb ldr r3, [r7, #56] @ 0x38 8011afa: 2b0f cmp r3, #15 8011afc: d916 bls.n 8011b2c 8011afe: 6bbb ldr r3, [r7, #56] @ 0x38 8011b00: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8011b04: d212 bcs.n 8011b2c { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 8011b06: 6bbb ldr r3, [r7, #56] @ 0x38 8011b08: b29b uxth r3, r3 8011b0a: f023 030f bic.w r3, r3, #15 8011b0e: 86fb strh r3, [r7, #54] @ 0x36 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8011b10: 6bbb ldr r3, [r7, #56] @ 0x38 8011b12: 085b lsrs r3, r3, #1 8011b14: b29b uxth r3, r3 8011b16: f003 0307 and.w r3, r3, #7 8011b1a: b29a uxth r2, r3 8011b1c: 8efb ldrh r3, [r7, #54] @ 0x36 8011b1e: 4313 orrs r3, r2 8011b20: 86fb strh r3, [r7, #54] @ 0x36 huart->Instance->BRR = brrtemp; 8011b22: 697b ldr r3, [r7, #20] 8011b24: 681b ldr r3, [r3, #0] 8011b26: 8efa ldrh r2, [r7, #54] @ 0x36 8011b28: 60da str r2, [r3, #12] 8011b2a: e0b9 b.n 8011ca0 } else { ret = HAL_ERROR; 8011b2c: 2301 movs r3, #1 8011b2e: f887 3042 strb.w r3, [r7, #66] @ 0x42 8011b32: e0b5 b.n 8011ca0 8011b34: 03d09000 .word 0x03d09000 8011b38: 003d0900 .word 0x003d0900 8011b3c: 0801a2a0 .word 0x0801a2a0 8011b40: 58024400 .word 0x58024400 } } } else { switch (clocksource) 8011b44: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 8011b48: 2b20 cmp r3, #32 8011b4a: dc49 bgt.n 8011be0 8011b4c: 2b00 cmp r3, #0 8011b4e: db7c blt.n 8011c4a 8011b50: 2b20 cmp r3, #32 8011b52: d87a bhi.n 8011c4a 8011b54: a201 add r2, pc, #4 @ (adr r2, 8011b5c ) 8011b56: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011b5a: bf00 nop 8011b5c: 08011be7 .word 0x08011be7 8011b60: 08011bef .word 0x08011bef 8011b64: 08011c4b .word 0x08011c4b 8011b68: 08011c4b .word 0x08011c4b 8011b6c: 08011bf7 .word 0x08011bf7 8011b70: 08011c4b .word 0x08011c4b 8011b74: 08011c4b .word 0x08011c4b 8011b78: 08011c4b .word 0x08011c4b 8011b7c: 08011c07 .word 0x08011c07 8011b80: 08011c4b .word 0x08011c4b 8011b84: 08011c4b .word 0x08011c4b 8011b88: 08011c4b .word 0x08011c4b 8011b8c: 08011c4b .word 0x08011c4b 8011b90: 08011c4b .word 0x08011c4b 8011b94: 08011c4b .word 0x08011c4b 8011b98: 08011c4b .word 0x08011c4b 8011b9c: 08011c17 .word 0x08011c17 8011ba0: 08011c4b .word 0x08011c4b 8011ba4: 08011c4b .word 0x08011c4b 8011ba8: 08011c4b .word 0x08011c4b 8011bac: 08011c4b .word 0x08011c4b 8011bb0: 08011c4b .word 0x08011c4b 8011bb4: 08011c4b .word 0x08011c4b 8011bb8: 08011c4b .word 0x08011c4b 8011bbc: 08011c4b .word 0x08011c4b 8011bc0: 08011c4b .word 0x08011c4b 8011bc4: 08011c4b .word 0x08011c4b 8011bc8: 08011c4b .word 0x08011c4b 8011bcc: 08011c4b .word 0x08011c4b 8011bd0: 08011c4b .word 0x08011c4b 8011bd4: 08011c4b .word 0x08011c4b 8011bd8: 08011c4b .word 0x08011c4b 8011bdc: 08011c3d .word 0x08011c3d 8011be0: 2b40 cmp r3, #64 @ 0x40 8011be2: d02e beq.n 8011c42 8011be4: e031 b.n 8011c4a { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8011be6: f7fa fc9b bl 800c520 8011bea: 63f8 str r0, [r7, #60] @ 0x3c break; 8011bec: e033 b.n 8011c56 case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8011bee: f7fa fcad bl 800c54c 8011bf2: 63f8 str r0, [r7, #60] @ 0x3c break; 8011bf4: e02f b.n 8011c56 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8011bf6: f107 0324 add.w r3, r7, #36 @ 0x24 8011bfa: 4618 mov r0, r3 8011bfc: f7fc fc82 bl 800e504 pclk = pll2_clocks.PLL2_Q_Frequency; 8011c00: 6abb ldr r3, [r7, #40] @ 0x28 8011c02: 63fb str r3, [r7, #60] @ 0x3c break; 8011c04: e027 b.n 8011c56 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8011c06: f107 0318 add.w r3, r7, #24 8011c0a: 4618 mov r0, r3 8011c0c: f7fc fdce bl 800e7ac pclk = pll3_clocks.PLL3_Q_Frequency; 8011c10: 69fb ldr r3, [r7, #28] 8011c12: 63fb str r3, [r7, #60] @ 0x3c break; 8011c14: e01f b.n 8011c56 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8011c16: 4b2d ldr r3, [pc, #180] @ (8011ccc ) 8011c18: 681b ldr r3, [r3, #0] 8011c1a: f003 0320 and.w r3, r3, #32 8011c1e: 2b00 cmp r3, #0 8011c20: d009 beq.n 8011c36 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8011c22: 4b2a ldr r3, [pc, #168] @ (8011ccc ) 8011c24: 681b ldr r3, [r3, #0] 8011c26: 08db lsrs r3, r3, #3 8011c28: f003 0303 and.w r3, r3, #3 8011c2c: 4a28 ldr r2, [pc, #160] @ (8011cd0 ) 8011c2e: fa22 f303 lsr.w r3, r2, r3 8011c32: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8011c34: e00f b.n 8011c56 pclk = (uint32_t) HSI_VALUE; 8011c36: 4b26 ldr r3, [pc, #152] @ (8011cd0 ) 8011c38: 63fb str r3, [r7, #60] @ 0x3c break; 8011c3a: e00c b.n 8011c56 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 8011c3c: 4b25 ldr r3, [pc, #148] @ (8011cd4 ) 8011c3e: 63fb str r3, [r7, #60] @ 0x3c break; 8011c40: e009 b.n 8011c56 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8011c42: f44f 4300 mov.w r3, #32768 @ 0x8000 8011c46: 63fb str r3, [r7, #60] @ 0x3c break; 8011c48: e005 b.n 8011c56 default: pclk = 0U; 8011c4a: 2300 movs r3, #0 8011c4c: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 8011c4e: 2301 movs r3, #1 8011c50: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 8011c54: bf00 nop } if (pclk != 0U) 8011c56: 6bfb ldr r3, [r7, #60] @ 0x3c 8011c58: 2b00 cmp r3, #0 8011c5a: d021 beq.n 8011ca0 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8011c5c: 697b ldr r3, [r7, #20] 8011c5e: 6a5b ldr r3, [r3, #36] @ 0x24 8011c60: 4a1d ldr r2, [pc, #116] @ (8011cd8 ) 8011c62: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8011c66: 461a mov r2, r3 8011c68: 6bfb ldr r3, [r7, #60] @ 0x3c 8011c6a: fbb3 f2f2 udiv r2, r3, r2 8011c6e: 697b ldr r3, [r7, #20] 8011c70: 685b ldr r3, [r3, #4] 8011c72: 085b lsrs r3, r3, #1 8011c74: 441a add r2, r3 8011c76: 697b ldr r3, [r7, #20] 8011c78: 685b ldr r3, [r3, #4] 8011c7a: fbb2 f3f3 udiv r3, r2, r3 8011c7e: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8011c80: 6bbb ldr r3, [r7, #56] @ 0x38 8011c82: 2b0f cmp r3, #15 8011c84: d909 bls.n 8011c9a 8011c86: 6bbb ldr r3, [r7, #56] @ 0x38 8011c88: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8011c8c: d205 bcs.n 8011c9a { huart->Instance->BRR = (uint16_t)usartdiv; 8011c8e: 6bbb ldr r3, [r7, #56] @ 0x38 8011c90: b29a uxth r2, r3 8011c92: 697b ldr r3, [r7, #20] 8011c94: 681b ldr r3, [r3, #0] 8011c96: 60da str r2, [r3, #12] 8011c98: e002 b.n 8011ca0 } else { ret = HAL_ERROR; 8011c9a: 2301 movs r3, #1 8011c9c: f887 3042 strb.w r3, [r7, #66] @ 0x42 } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 8011ca0: 697b ldr r3, [r7, #20] 8011ca2: 2201 movs r2, #1 8011ca4: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1; 8011ca8: 697b ldr r3, [r7, #20] 8011caa: 2201 movs r2, #1 8011cac: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; 8011cb0: 697b ldr r3, [r7, #20] 8011cb2: 2200 movs r2, #0 8011cb4: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 8011cb6: 697b ldr r3, [r7, #20] 8011cb8: 2200 movs r2, #0 8011cba: 679a str r2, [r3, #120] @ 0x78 return ret; 8011cbc: f897 3042 ldrb.w r3, [r7, #66] @ 0x42 } 8011cc0: 4618 mov r0, r3 8011cc2: 3748 adds r7, #72 @ 0x48 8011cc4: 46bd mov sp, r7 8011cc6: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8011cca: bf00 nop 8011ccc: 58024400 .word 0x58024400 8011cd0: 03d09000 .word 0x03d09000 8011cd4: 003d0900 .word 0x003d0900 8011cd8: 0801a2a0 .word 0x0801a2a0 08011cdc : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 8011cdc: b480 push {r7} 8011cde: b083 sub sp, #12 8011ce0: af00 add r7, sp, #0 8011ce2: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 8011ce4: 687b ldr r3, [r7, #4] 8011ce6: 6a9b ldr r3, [r3, #40] @ 0x28 8011ce8: f003 0308 and.w r3, r3, #8 8011cec: 2b00 cmp r3, #0 8011cee: d00a beq.n 8011d06 { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 8011cf0: 687b ldr r3, [r7, #4] 8011cf2: 681b ldr r3, [r3, #0] 8011cf4: 685b ldr r3, [r3, #4] 8011cf6: f423 4100 bic.w r1, r3, #32768 @ 0x8000 8011cfa: 687b ldr r3, [r7, #4] 8011cfc: 6b9a ldr r2, [r3, #56] @ 0x38 8011cfe: 687b ldr r3, [r7, #4] 8011d00: 681b ldr r3, [r3, #0] 8011d02: 430a orrs r2, r1 8011d04: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 8011d06: 687b ldr r3, [r7, #4] 8011d08: 6a9b ldr r3, [r3, #40] @ 0x28 8011d0a: f003 0301 and.w r3, r3, #1 8011d0e: 2b00 cmp r3, #0 8011d10: d00a beq.n 8011d28 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 8011d12: 687b ldr r3, [r7, #4] 8011d14: 681b ldr r3, [r3, #0] 8011d16: 685b ldr r3, [r3, #4] 8011d18: f423 3100 bic.w r1, r3, #131072 @ 0x20000 8011d1c: 687b ldr r3, [r7, #4] 8011d1e: 6ada ldr r2, [r3, #44] @ 0x2c 8011d20: 687b ldr r3, [r7, #4] 8011d22: 681b ldr r3, [r3, #0] 8011d24: 430a orrs r2, r1 8011d26: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 8011d28: 687b ldr r3, [r7, #4] 8011d2a: 6a9b ldr r3, [r3, #40] @ 0x28 8011d2c: f003 0302 and.w r3, r3, #2 8011d30: 2b00 cmp r3, #0 8011d32: d00a beq.n 8011d4a { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 8011d34: 687b ldr r3, [r7, #4] 8011d36: 681b ldr r3, [r3, #0] 8011d38: 685b ldr r3, [r3, #4] 8011d3a: f423 3180 bic.w r1, r3, #65536 @ 0x10000 8011d3e: 687b ldr r3, [r7, #4] 8011d40: 6b1a ldr r2, [r3, #48] @ 0x30 8011d42: 687b ldr r3, [r7, #4] 8011d44: 681b ldr r3, [r3, #0] 8011d46: 430a orrs r2, r1 8011d48: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 8011d4a: 687b ldr r3, [r7, #4] 8011d4c: 6a9b ldr r3, [r3, #40] @ 0x28 8011d4e: f003 0304 and.w r3, r3, #4 8011d52: 2b00 cmp r3, #0 8011d54: d00a beq.n 8011d6c { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 8011d56: 687b ldr r3, [r7, #4] 8011d58: 681b ldr r3, [r3, #0] 8011d5a: 685b ldr r3, [r3, #4] 8011d5c: f423 2180 bic.w r1, r3, #262144 @ 0x40000 8011d60: 687b ldr r3, [r7, #4] 8011d62: 6b5a ldr r2, [r3, #52] @ 0x34 8011d64: 687b ldr r3, [r7, #4] 8011d66: 681b ldr r3, [r3, #0] 8011d68: 430a orrs r2, r1 8011d6a: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 8011d6c: 687b ldr r3, [r7, #4] 8011d6e: 6a9b ldr r3, [r3, #40] @ 0x28 8011d70: f003 0310 and.w r3, r3, #16 8011d74: 2b00 cmp r3, #0 8011d76: d00a beq.n 8011d8e { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 8011d78: 687b ldr r3, [r7, #4] 8011d7a: 681b ldr r3, [r3, #0] 8011d7c: 689b ldr r3, [r3, #8] 8011d7e: f423 5180 bic.w r1, r3, #4096 @ 0x1000 8011d82: 687b ldr r3, [r7, #4] 8011d84: 6bda ldr r2, [r3, #60] @ 0x3c 8011d86: 687b ldr r3, [r7, #4] 8011d88: 681b ldr r3, [r3, #0] 8011d8a: 430a orrs r2, r1 8011d8c: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 8011d8e: 687b ldr r3, [r7, #4] 8011d90: 6a9b ldr r3, [r3, #40] @ 0x28 8011d92: f003 0320 and.w r3, r3, #32 8011d96: 2b00 cmp r3, #0 8011d98: d00a beq.n 8011db0 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 8011d9a: 687b ldr r3, [r7, #4] 8011d9c: 681b ldr r3, [r3, #0] 8011d9e: 689b ldr r3, [r3, #8] 8011da0: f423 5100 bic.w r1, r3, #8192 @ 0x2000 8011da4: 687b ldr r3, [r7, #4] 8011da6: 6c1a ldr r2, [r3, #64] @ 0x40 8011da8: 687b ldr r3, [r7, #4] 8011daa: 681b ldr r3, [r3, #0] 8011dac: 430a orrs r2, r1 8011dae: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 8011db0: 687b ldr r3, [r7, #4] 8011db2: 6a9b ldr r3, [r3, #40] @ 0x28 8011db4: f003 0340 and.w r3, r3, #64 @ 0x40 8011db8: 2b00 cmp r3, #0 8011dba: d01a beq.n 8011df2 { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 8011dbc: 687b ldr r3, [r7, #4] 8011dbe: 681b ldr r3, [r3, #0] 8011dc0: 685b ldr r3, [r3, #4] 8011dc2: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 8011dc6: 687b ldr r3, [r7, #4] 8011dc8: 6c5a ldr r2, [r3, #68] @ 0x44 8011dca: 687b ldr r3, [r7, #4] 8011dcc: 681b ldr r3, [r3, #0] 8011dce: 430a orrs r2, r1 8011dd0: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 8011dd2: 687b ldr r3, [r7, #4] 8011dd4: 6c5b ldr r3, [r3, #68] @ 0x44 8011dd6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8011dda: d10a bne.n 8011df2 { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 8011ddc: 687b ldr r3, [r7, #4] 8011dde: 681b ldr r3, [r3, #0] 8011de0: 685b ldr r3, [r3, #4] 8011de2: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 8011de6: 687b ldr r3, [r7, #4] 8011de8: 6c9a ldr r2, [r3, #72] @ 0x48 8011dea: 687b ldr r3, [r7, #4] 8011dec: 681b ldr r3, [r3, #0] 8011dee: 430a orrs r2, r1 8011df0: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 8011df2: 687b ldr r3, [r7, #4] 8011df4: 6a9b ldr r3, [r3, #40] @ 0x28 8011df6: f003 0380 and.w r3, r3, #128 @ 0x80 8011dfa: 2b00 cmp r3, #0 8011dfc: d00a beq.n 8011e14 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 8011dfe: 687b ldr r3, [r7, #4] 8011e00: 681b ldr r3, [r3, #0] 8011e02: 685b ldr r3, [r3, #4] 8011e04: f423 2100 bic.w r1, r3, #524288 @ 0x80000 8011e08: 687b ldr r3, [r7, #4] 8011e0a: 6cda ldr r2, [r3, #76] @ 0x4c 8011e0c: 687b ldr r3, [r7, #4] 8011e0e: 681b ldr r3, [r3, #0] 8011e10: 430a orrs r2, r1 8011e12: 605a str r2, [r3, #4] } } 8011e14: bf00 nop 8011e16: 370c adds r7, #12 8011e18: 46bd mov sp, r7 8011e1a: f85d 7b04 ldr.w r7, [sp], #4 8011e1e: 4770 bx lr 08011e20 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 8011e20: b580 push {r7, lr} 8011e22: b098 sub sp, #96 @ 0x60 8011e24: af02 add r7, sp, #8 8011e26: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8011e28: 687b ldr r3, [r7, #4] 8011e2a: 2200 movs r2, #0 8011e2c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8011e30: f7f3 fd34 bl 800589c 8011e34: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 8011e36: 687b ldr r3, [r7, #4] 8011e38: 681b ldr r3, [r3, #0] 8011e3a: 681b ldr r3, [r3, #0] 8011e3c: f003 0308 and.w r3, r3, #8 8011e40: 2b08 cmp r3, #8 8011e42: d12f bne.n 8011ea4 { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8011e44: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8011e48: 9300 str r3, [sp, #0] 8011e4a: 6d7b ldr r3, [r7, #84] @ 0x54 8011e4c: 2200 movs r2, #0 8011e4e: f44f 1100 mov.w r1, #2097152 @ 0x200000 8011e52: 6878 ldr r0, [r7, #4] 8011e54: f000 f88e bl 8011f74 8011e58: 4603 mov r3, r0 8011e5a: 2b00 cmp r3, #0 8011e5c: d022 beq.n 8011ea4 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 8011e5e: 687b ldr r3, [r7, #4] 8011e60: 681b ldr r3, [r3, #0] 8011e62: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011e64: 6bbb ldr r3, [r7, #56] @ 0x38 8011e66: e853 3f00 ldrex r3, [r3] 8011e6a: 637b str r3, [r7, #52] @ 0x34 return(result); 8011e6c: 6b7b ldr r3, [r7, #52] @ 0x34 8011e6e: f023 0380 bic.w r3, r3, #128 @ 0x80 8011e72: 653b str r3, [r7, #80] @ 0x50 8011e74: 687b ldr r3, [r7, #4] 8011e76: 681b ldr r3, [r3, #0] 8011e78: 461a mov r2, r3 8011e7a: 6d3b ldr r3, [r7, #80] @ 0x50 8011e7c: 647b str r3, [r7, #68] @ 0x44 8011e7e: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011e80: 6c39 ldr r1, [r7, #64] @ 0x40 8011e82: 6c7a ldr r2, [r7, #68] @ 0x44 8011e84: e841 2300 strex r3, r2, [r1] 8011e88: 63fb str r3, [r7, #60] @ 0x3c return(result); 8011e8a: 6bfb ldr r3, [r7, #60] @ 0x3c 8011e8c: 2b00 cmp r3, #0 8011e8e: d1e6 bne.n 8011e5e huart->gState = HAL_UART_STATE_READY; 8011e90: 687b ldr r3, [r7, #4] 8011e92: 2220 movs r2, #32 8011e94: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); 8011e98: 687b ldr r3, [r7, #4] 8011e9a: 2200 movs r2, #0 8011e9c: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8011ea0: 2303 movs r3, #3 8011ea2: e063 b.n 8011f6c } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 8011ea4: 687b ldr r3, [r7, #4] 8011ea6: 681b ldr r3, [r3, #0] 8011ea8: 681b ldr r3, [r3, #0] 8011eaa: f003 0304 and.w r3, r3, #4 8011eae: 2b04 cmp r3, #4 8011eb0: d149 bne.n 8011f46 { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8011eb2: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8011eb6: 9300 str r3, [sp, #0] 8011eb8: 6d7b ldr r3, [r7, #84] @ 0x54 8011eba: 2200 movs r2, #0 8011ebc: f44f 0180 mov.w r1, #4194304 @ 0x400000 8011ec0: 6878 ldr r0, [r7, #4] 8011ec2: f000 f857 bl 8011f74 8011ec6: 4603 mov r3, r0 8011ec8: 2b00 cmp r3, #0 8011eca: d03c beq.n 8011f46 { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8011ecc: 687b ldr r3, [r7, #4] 8011ece: 681b ldr r3, [r3, #0] 8011ed0: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011ed2: 6a7b ldr r3, [r7, #36] @ 0x24 8011ed4: e853 3f00 ldrex r3, [r3] 8011ed8: 623b str r3, [r7, #32] return(result); 8011eda: 6a3b ldr r3, [r7, #32] 8011edc: f423 7390 bic.w r3, r3, #288 @ 0x120 8011ee0: 64fb str r3, [r7, #76] @ 0x4c 8011ee2: 687b ldr r3, [r7, #4] 8011ee4: 681b ldr r3, [r3, #0] 8011ee6: 461a mov r2, r3 8011ee8: 6cfb ldr r3, [r7, #76] @ 0x4c 8011eea: 633b str r3, [r7, #48] @ 0x30 8011eec: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011eee: 6af9 ldr r1, [r7, #44] @ 0x2c 8011ef0: 6b3a ldr r2, [r7, #48] @ 0x30 8011ef2: e841 2300 strex r3, r2, [r1] 8011ef6: 62bb str r3, [r7, #40] @ 0x28 return(result); 8011ef8: 6abb ldr r3, [r7, #40] @ 0x28 8011efa: 2b00 cmp r3, #0 8011efc: d1e6 bne.n 8011ecc ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8011efe: 687b ldr r3, [r7, #4] 8011f00: 681b ldr r3, [r3, #0] 8011f02: 3308 adds r3, #8 8011f04: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011f06: 693b ldr r3, [r7, #16] 8011f08: e853 3f00 ldrex r3, [r3] 8011f0c: 60fb str r3, [r7, #12] return(result); 8011f0e: 68fb ldr r3, [r7, #12] 8011f10: f023 0301 bic.w r3, r3, #1 8011f14: 64bb str r3, [r7, #72] @ 0x48 8011f16: 687b ldr r3, [r7, #4] 8011f18: 681b ldr r3, [r3, #0] 8011f1a: 3308 adds r3, #8 8011f1c: 6cba ldr r2, [r7, #72] @ 0x48 8011f1e: 61fa str r2, [r7, #28] 8011f20: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011f22: 69b9 ldr r1, [r7, #24] 8011f24: 69fa ldr r2, [r7, #28] 8011f26: e841 2300 strex r3, r2, [r1] 8011f2a: 617b str r3, [r7, #20] return(result); 8011f2c: 697b ldr r3, [r7, #20] 8011f2e: 2b00 cmp r3, #0 8011f30: d1e5 bne.n 8011efe huart->RxState = HAL_UART_STATE_READY; 8011f32: 687b ldr r3, [r7, #4] 8011f34: 2220 movs r2, #32 8011f36: f8c3 208c str.w r2, [r3, #140] @ 0x8c __HAL_UNLOCK(huart); 8011f3a: 687b ldr r3, [r7, #4] 8011f3c: 2200 movs r2, #0 8011f3e: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8011f42: 2303 movs r3, #3 8011f44: e012 b.n 8011f6c } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 8011f46: 687b ldr r3, [r7, #4] 8011f48: 2220 movs r2, #32 8011f4a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 huart->RxState = HAL_UART_STATE_READY; 8011f4e: 687b ldr r3, [r7, #4] 8011f50: 2220 movs r2, #32 8011f52: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8011f56: 687b ldr r3, [r7, #4] 8011f58: 2200 movs r2, #0 8011f5a: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8011f5c: 687b ldr r3, [r7, #4] 8011f5e: 2200 movs r2, #0 8011f60: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 8011f62: 687b ldr r3, [r7, #4] 8011f64: 2200 movs r2, #0 8011f66: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8011f6a: 2300 movs r3, #0 } 8011f6c: 4618 mov r0, r3 8011f6e: 3758 adds r7, #88 @ 0x58 8011f70: 46bd mov sp, r7 8011f72: bd80 pop {r7, pc} 08011f74 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8011f74: b580 push {r7, lr} 8011f76: b084 sub sp, #16 8011f78: af00 add r7, sp, #0 8011f7a: 60f8 str r0, [r7, #12] 8011f7c: 60b9 str r1, [r7, #8] 8011f7e: 603b str r3, [r7, #0] 8011f80: 4613 mov r3, r2 8011f82: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8011f84: e04f b.n 8012026 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8011f86: 69bb ldr r3, [r7, #24] 8011f88: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8011f8c: d04b beq.n 8012026 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8011f8e: f7f3 fc85 bl 800589c 8011f92: 4602 mov r2, r0 8011f94: 683b ldr r3, [r7, #0] 8011f96: 1ad3 subs r3, r2, r3 8011f98: 69ba ldr r2, [r7, #24] 8011f9a: 429a cmp r2, r3 8011f9c: d302 bcc.n 8011fa4 8011f9e: 69bb ldr r3, [r7, #24] 8011fa0: 2b00 cmp r3, #0 8011fa2: d101 bne.n 8011fa8 { return HAL_TIMEOUT; 8011fa4: 2303 movs r3, #3 8011fa6: e04e b.n 8012046 } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 8011fa8: 68fb ldr r3, [r7, #12] 8011faa: 681b ldr r3, [r3, #0] 8011fac: 681b ldr r3, [r3, #0] 8011fae: f003 0304 and.w r3, r3, #4 8011fb2: 2b00 cmp r3, #0 8011fb4: d037 beq.n 8012026 8011fb6: 68bb ldr r3, [r7, #8] 8011fb8: 2b80 cmp r3, #128 @ 0x80 8011fba: d034 beq.n 8012026 8011fbc: 68bb ldr r3, [r7, #8] 8011fbe: 2b40 cmp r3, #64 @ 0x40 8011fc0: d031 beq.n 8012026 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8011fc2: 68fb ldr r3, [r7, #12] 8011fc4: 681b ldr r3, [r3, #0] 8011fc6: 69db ldr r3, [r3, #28] 8011fc8: f003 0308 and.w r3, r3, #8 8011fcc: 2b08 cmp r3, #8 8011fce: d110 bne.n 8011ff2 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8011fd0: 68fb ldr r3, [r7, #12] 8011fd2: 681b ldr r3, [r3, #0] 8011fd4: 2208 movs r2, #8 8011fd6: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8011fd8: 68f8 ldr r0, [r7, #12] 8011fda: f000 f95b bl 8012294 huart->ErrorCode = HAL_UART_ERROR_ORE; 8011fde: 68fb ldr r3, [r7, #12] 8011fe0: 2208 movs r2, #8 8011fe2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8011fe6: 68fb ldr r3, [r7, #12] 8011fe8: 2200 movs r2, #0 8011fea: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_ERROR; 8011fee: 2301 movs r3, #1 8011ff0: e029 b.n 8012046 } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8011ff2: 68fb ldr r3, [r7, #12] 8011ff4: 681b ldr r3, [r3, #0] 8011ff6: 69db ldr r3, [r3, #28] 8011ff8: f403 6300 and.w r3, r3, #2048 @ 0x800 8011ffc: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8012000: d111 bne.n 8012026 { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8012002: 68fb ldr r3, [r7, #12] 8012004: 681b ldr r3, [r3, #0] 8012006: f44f 6200 mov.w r2, #2048 @ 0x800 801200a: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 801200c: 68f8 ldr r0, [r7, #12] 801200e: f000 f941 bl 8012294 huart->ErrorCode = HAL_UART_ERROR_RTO; 8012012: 68fb ldr r3, [r7, #12] 8012014: 2220 movs r2, #32 8012016: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 801201a: 68fb ldr r3, [r7, #12] 801201c: 2200 movs r2, #0 801201e: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_TIMEOUT; 8012022: 2303 movs r3, #3 8012024: e00f b.n 8012046 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8012026: 68fb ldr r3, [r7, #12] 8012028: 681b ldr r3, [r3, #0] 801202a: 69da ldr r2, [r3, #28] 801202c: 68bb ldr r3, [r7, #8] 801202e: 4013 ands r3, r2 8012030: 68ba ldr r2, [r7, #8] 8012032: 429a cmp r2, r3 8012034: bf0c ite eq 8012036: 2301 moveq r3, #1 8012038: 2300 movne r3, #0 801203a: b2db uxtb r3, r3 801203c: 461a mov r2, r3 801203e: 79fb ldrb r3, [r7, #7] 8012040: 429a cmp r2, r3 8012042: d0a0 beq.n 8011f86 } } } } return HAL_OK; 8012044: 2300 movs r3, #0 } 8012046: 4618 mov r0, r3 8012048: 3710 adds r7, #16 801204a: 46bd mov sp, r7 801204c: bd80 pop {r7, pc} ... 08012050 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8012050: b480 push {r7} 8012052: b0a3 sub sp, #140 @ 0x8c 8012054: af00 add r7, sp, #0 8012056: 60f8 str r0, [r7, #12] 8012058: 60b9 str r1, [r7, #8] 801205a: 4613 mov r3, r2 801205c: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 801205e: 68fb ldr r3, [r7, #12] 8012060: 68ba ldr r2, [r7, #8] 8012062: 659a str r2, [r3, #88] @ 0x58 huart->RxXferSize = Size; 8012064: 68fb ldr r3, [r7, #12] 8012066: 88fa ldrh r2, [r7, #6] 8012068: f8a3 205c strh.w r2, [r3, #92] @ 0x5c huart->RxXferCount = Size; 801206c: 68fb ldr r3, [r7, #12] 801206e: 88fa ldrh r2, [r7, #6] 8012070: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->RxISR = NULL; 8012074: 68fb ldr r3, [r7, #12] 8012076: 2200 movs r2, #0 8012078: 675a str r2, [r3, #116] @ 0x74 /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); 801207a: 68fb ldr r3, [r7, #12] 801207c: 689b ldr r3, [r3, #8] 801207e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012082: d10e bne.n 80120a2 8012084: 68fb ldr r3, [r7, #12] 8012086: 691b ldr r3, [r3, #16] 8012088: 2b00 cmp r3, #0 801208a: d105 bne.n 8012098 801208c: 68fb ldr r3, [r7, #12] 801208e: f240 12ff movw r2, #511 @ 0x1ff 8012092: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012096: e02d b.n 80120f4 8012098: 68fb ldr r3, [r7, #12] 801209a: 22ff movs r2, #255 @ 0xff 801209c: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 80120a0: e028 b.n 80120f4 80120a2: 68fb ldr r3, [r7, #12] 80120a4: 689b ldr r3, [r3, #8] 80120a6: 2b00 cmp r3, #0 80120a8: d10d bne.n 80120c6 80120aa: 68fb ldr r3, [r7, #12] 80120ac: 691b ldr r3, [r3, #16] 80120ae: 2b00 cmp r3, #0 80120b0: d104 bne.n 80120bc 80120b2: 68fb ldr r3, [r7, #12] 80120b4: 22ff movs r2, #255 @ 0xff 80120b6: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 80120ba: e01b b.n 80120f4 80120bc: 68fb ldr r3, [r7, #12] 80120be: 227f movs r2, #127 @ 0x7f 80120c0: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 80120c4: e016 b.n 80120f4 80120c6: 68fb ldr r3, [r7, #12] 80120c8: 689b ldr r3, [r3, #8] 80120ca: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80120ce: d10d bne.n 80120ec 80120d0: 68fb ldr r3, [r7, #12] 80120d2: 691b ldr r3, [r3, #16] 80120d4: 2b00 cmp r3, #0 80120d6: d104 bne.n 80120e2 80120d8: 68fb ldr r3, [r7, #12] 80120da: 227f movs r2, #127 @ 0x7f 80120dc: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 80120e0: e008 b.n 80120f4 80120e2: 68fb ldr r3, [r7, #12] 80120e4: 223f movs r2, #63 @ 0x3f 80120e6: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 80120ea: e003 b.n 80120f4 80120ec: 68fb ldr r3, [r7, #12] 80120ee: 2200 movs r2, #0 80120f0: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 huart->ErrorCode = HAL_UART_ERROR_NONE; 80120f4: 68fb ldr r3, [r7, #12] 80120f6: 2200 movs r2, #0 80120f8: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->RxState = HAL_UART_STATE_BUSY_RX; 80120fc: 68fb ldr r3, [r7, #12] 80120fe: 2222 movs r2, #34 @ 0x22 8012100: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012104: 68fb ldr r3, [r7, #12] 8012106: 681b ldr r3, [r3, #0] 8012108: 3308 adds r3, #8 801210a: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801210c: 6e7b ldr r3, [r7, #100] @ 0x64 801210e: e853 3f00 ldrex r3, [r3] 8012112: 663b str r3, [r7, #96] @ 0x60 return(result); 8012114: 6e3b ldr r3, [r7, #96] @ 0x60 8012116: f043 0301 orr.w r3, r3, #1 801211a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 801211e: 68fb ldr r3, [r7, #12] 8012120: 681b ldr r3, [r3, #0] 8012122: 3308 adds r3, #8 8012124: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 8012128: 673a str r2, [r7, #112] @ 0x70 801212a: 66fb str r3, [r7, #108] @ 0x6c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801212c: 6ef9 ldr r1, [r7, #108] @ 0x6c 801212e: 6f3a ldr r2, [r7, #112] @ 0x70 8012130: e841 2300 strex r3, r2, [r1] 8012134: 66bb str r3, [r7, #104] @ 0x68 return(result); 8012136: 6ebb ldr r3, [r7, #104] @ 0x68 8012138: 2b00 cmp r3, #0 801213a: d1e3 bne.n 8012104 /* Configure Rx interrupt processing */ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) 801213c: 68fb ldr r3, [r7, #12] 801213e: 6e5b ldr r3, [r3, #100] @ 0x64 8012140: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8012144: d14f bne.n 80121e6 8012146: 68fb ldr r3, [r7, #12] 8012148: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 801214c: 88fa ldrh r2, [r7, #6] 801214e: 429a cmp r2, r3 8012150: d349 bcc.n 80121e6 { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012152: 68fb ldr r3, [r7, #12] 8012154: 689b ldr r3, [r3, #8] 8012156: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 801215a: d107 bne.n 801216c 801215c: 68fb ldr r3, [r7, #12] 801215e: 691b ldr r3, [r3, #16] 8012160: 2b00 cmp r3, #0 8012162: d103 bne.n 801216c { huart->RxISR = UART_RxISR_16BIT_FIFOEN; 8012164: 68fb ldr r3, [r7, #12] 8012166: 4a47 ldr r2, [pc, #284] @ (8012284 ) 8012168: 675a str r2, [r3, #116] @ 0x74 801216a: e002 b.n 8012172 } else { huart->RxISR = UART_RxISR_8BIT_FIFOEN; 801216c: 68fb ldr r3, [r7, #12] 801216e: 4a46 ldr r2, [pc, #280] @ (8012288 ) 8012170: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8012172: 68fb ldr r3, [r7, #12] 8012174: 691b ldr r3, [r3, #16] 8012176: 2b00 cmp r3, #0 8012178: d01a beq.n 80121b0 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 801217a: 68fb ldr r3, [r7, #12] 801217c: 681b ldr r3, [r3, #0] 801217e: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012180: 6d3b ldr r3, [r7, #80] @ 0x50 8012182: e853 3f00 ldrex r3, [r3] 8012186: 64fb str r3, [r7, #76] @ 0x4c return(result); 8012188: 6cfb ldr r3, [r7, #76] @ 0x4c 801218a: f443 7380 orr.w r3, r3, #256 @ 0x100 801218e: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8012192: 68fb ldr r3, [r7, #12] 8012194: 681b ldr r3, [r3, #0] 8012196: 461a mov r2, r3 8012198: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 801219c: 65fb str r3, [r7, #92] @ 0x5c 801219e: 65ba str r2, [r7, #88] @ 0x58 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80121a0: 6db9 ldr r1, [r7, #88] @ 0x58 80121a2: 6dfa ldr r2, [r7, #92] @ 0x5c 80121a4: e841 2300 strex r3, r2, [r1] 80121a8: 657b str r3, [r7, #84] @ 0x54 return(result); 80121aa: 6d7b ldr r3, [r7, #84] @ 0x54 80121ac: 2b00 cmp r3, #0 80121ae: d1e4 bne.n 801217a } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 80121b0: 68fb ldr r3, [r7, #12] 80121b2: 681b ldr r3, [r3, #0] 80121b4: 3308 adds r3, #8 80121b6: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80121b8: 6bfb ldr r3, [r7, #60] @ 0x3c 80121ba: e853 3f00 ldrex r3, [r3] 80121be: 63bb str r3, [r7, #56] @ 0x38 return(result); 80121c0: 6bbb ldr r3, [r7, #56] @ 0x38 80121c2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80121c6: 67fb str r3, [r7, #124] @ 0x7c 80121c8: 68fb ldr r3, [r7, #12] 80121ca: 681b ldr r3, [r3, #0] 80121cc: 3308 adds r3, #8 80121ce: 6ffa ldr r2, [r7, #124] @ 0x7c 80121d0: 64ba str r2, [r7, #72] @ 0x48 80121d2: 647b str r3, [r7, #68] @ 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80121d4: 6c79 ldr r1, [r7, #68] @ 0x44 80121d6: 6cba ldr r2, [r7, #72] @ 0x48 80121d8: e841 2300 strex r3, r2, [r1] 80121dc: 643b str r3, [r7, #64] @ 0x40 return(result); 80121de: 6c3b ldr r3, [r7, #64] @ 0x40 80121e0: 2b00 cmp r3, #0 80121e2: d1e5 bne.n 80121b0 80121e4: e046 b.n 8012274 } else { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80121e6: 68fb ldr r3, [r7, #12] 80121e8: 689b ldr r3, [r3, #8] 80121ea: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80121ee: d107 bne.n 8012200 80121f0: 68fb ldr r3, [r7, #12] 80121f2: 691b ldr r3, [r3, #16] 80121f4: 2b00 cmp r3, #0 80121f6: d103 bne.n 8012200 { huart->RxISR = UART_RxISR_16BIT; 80121f8: 68fb ldr r3, [r7, #12] 80121fa: 4a24 ldr r2, [pc, #144] @ (801228c ) 80121fc: 675a str r2, [r3, #116] @ 0x74 80121fe: e002 b.n 8012206 } else { huart->RxISR = UART_RxISR_8BIT; 8012200: 68fb ldr r3, [r7, #12] 8012202: 4a23 ldr r2, [pc, #140] @ (8012290 ) 8012204: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8012206: 68fb ldr r3, [r7, #12] 8012208: 691b ldr r3, [r3, #16] 801220a: 2b00 cmp r3, #0 801220c: d019 beq.n 8012242 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); 801220e: 68fb ldr r3, [r7, #12] 8012210: 681b ldr r3, [r3, #0] 8012212: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012214: 6abb ldr r3, [r7, #40] @ 0x28 8012216: e853 3f00 ldrex r3, [r3] 801221a: 627b str r3, [r7, #36] @ 0x24 return(result); 801221c: 6a7b ldr r3, [r7, #36] @ 0x24 801221e: f443 7390 orr.w r3, r3, #288 @ 0x120 8012222: 677b str r3, [r7, #116] @ 0x74 8012224: 68fb ldr r3, [r7, #12] 8012226: 681b ldr r3, [r3, #0] 8012228: 461a mov r2, r3 801222a: 6f7b ldr r3, [r7, #116] @ 0x74 801222c: 637b str r3, [r7, #52] @ 0x34 801222e: 633a str r2, [r7, #48] @ 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012230: 6b39 ldr r1, [r7, #48] @ 0x30 8012232: 6b7a ldr r2, [r7, #52] @ 0x34 8012234: e841 2300 strex r3, r2, [r1] 8012238: 62fb str r3, [r7, #44] @ 0x2c return(result); 801223a: 6afb ldr r3, [r7, #44] @ 0x2c 801223c: 2b00 cmp r3, #0 801223e: d1e6 bne.n 801220e 8012240: e018 b.n 8012274 } else { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8012242: 68fb ldr r3, [r7, #12] 8012244: 681b ldr r3, [r3, #0] 8012246: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012248: 697b ldr r3, [r7, #20] 801224a: e853 3f00 ldrex r3, [r3] 801224e: 613b str r3, [r7, #16] return(result); 8012250: 693b ldr r3, [r7, #16] 8012252: f043 0320 orr.w r3, r3, #32 8012256: 67bb str r3, [r7, #120] @ 0x78 8012258: 68fb ldr r3, [r7, #12] 801225a: 681b ldr r3, [r3, #0] 801225c: 461a mov r2, r3 801225e: 6fbb ldr r3, [r7, #120] @ 0x78 8012260: 623b str r3, [r7, #32] 8012262: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012264: 69f9 ldr r1, [r7, #28] 8012266: 6a3a ldr r2, [r7, #32] 8012268: e841 2300 strex r3, r2, [r1] 801226c: 61bb str r3, [r7, #24] return(result); 801226e: 69bb ldr r3, [r7, #24] 8012270: 2b00 cmp r3, #0 8012272: d1e6 bne.n 8012242 } } return HAL_OK; 8012274: 2300 movs r3, #0 } 8012276: 4618 mov r0, r3 8012278: 378c adds r7, #140 @ 0x8c 801227a: 46bd mov sp, r7 801227c: f85d 7b04 ldr.w r7, [sp], #4 8012280: 4770 bx lr 8012282: bf00 nop 8012284: 08012df9 .word 0x08012df9 8012288: 08012a99 .word 0x08012a99 801228c: 080128e1 .word 0x080128e1 8012290: 08012729 .word 0x08012729 08012294 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8012294: b480 push {r7} 8012296: b095 sub sp, #84 @ 0x54 8012298: af00 add r7, sp, #0 801229a: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 801229c: 687b ldr r3, [r7, #4] 801229e: 681b ldr r3, [r3, #0] 80122a0: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80122a2: 6b7b ldr r3, [r7, #52] @ 0x34 80122a4: e853 3f00 ldrex r3, [r3] 80122a8: 633b str r3, [r7, #48] @ 0x30 return(result); 80122aa: 6b3b ldr r3, [r7, #48] @ 0x30 80122ac: f423 7390 bic.w r3, r3, #288 @ 0x120 80122b0: 64fb str r3, [r7, #76] @ 0x4c 80122b2: 687b ldr r3, [r7, #4] 80122b4: 681b ldr r3, [r3, #0] 80122b6: 461a mov r2, r3 80122b8: 6cfb ldr r3, [r7, #76] @ 0x4c 80122ba: 643b str r3, [r7, #64] @ 0x40 80122bc: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80122be: 6bf9 ldr r1, [r7, #60] @ 0x3c 80122c0: 6c3a ldr r2, [r7, #64] @ 0x40 80122c2: e841 2300 strex r3, r2, [r1] 80122c6: 63bb str r3, [r7, #56] @ 0x38 return(result); 80122c8: 6bbb ldr r3, [r7, #56] @ 0x38 80122ca: 2b00 cmp r3, #0 80122cc: d1e6 bne.n 801229c ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 80122ce: 687b ldr r3, [r7, #4] 80122d0: 681b ldr r3, [r3, #0] 80122d2: 3308 adds r3, #8 80122d4: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80122d6: 6a3b ldr r3, [r7, #32] 80122d8: e853 3f00 ldrex r3, [r3] 80122dc: 61fb str r3, [r7, #28] return(result); 80122de: 69fa ldr r2, [r7, #28] 80122e0: 4b1e ldr r3, [pc, #120] @ (801235c ) 80122e2: 4013 ands r3, r2 80122e4: 64bb str r3, [r7, #72] @ 0x48 80122e6: 687b ldr r3, [r7, #4] 80122e8: 681b ldr r3, [r3, #0] 80122ea: 3308 adds r3, #8 80122ec: 6cba ldr r2, [r7, #72] @ 0x48 80122ee: 62fa str r2, [r7, #44] @ 0x2c 80122f0: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80122f2: 6ab9 ldr r1, [r7, #40] @ 0x28 80122f4: 6afa ldr r2, [r7, #44] @ 0x2c 80122f6: e841 2300 strex r3, r2, [r1] 80122fa: 627b str r3, [r7, #36] @ 0x24 return(result); 80122fc: 6a7b ldr r3, [r7, #36] @ 0x24 80122fe: 2b00 cmp r3, #0 8012300: d1e5 bne.n 80122ce /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012302: 687b ldr r3, [r7, #4] 8012304: 6edb ldr r3, [r3, #108] @ 0x6c 8012306: 2b01 cmp r3, #1 8012308: d118 bne.n 801233c { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801230a: 687b ldr r3, [r7, #4] 801230c: 681b ldr r3, [r3, #0] 801230e: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012310: 68fb ldr r3, [r7, #12] 8012312: e853 3f00 ldrex r3, [r3] 8012316: 60bb str r3, [r7, #8] return(result); 8012318: 68bb ldr r3, [r7, #8] 801231a: f023 0310 bic.w r3, r3, #16 801231e: 647b str r3, [r7, #68] @ 0x44 8012320: 687b ldr r3, [r7, #4] 8012322: 681b ldr r3, [r3, #0] 8012324: 461a mov r2, r3 8012326: 6c7b ldr r3, [r7, #68] @ 0x44 8012328: 61bb str r3, [r7, #24] 801232a: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801232c: 6979 ldr r1, [r7, #20] 801232e: 69ba ldr r2, [r7, #24] 8012330: e841 2300 strex r3, r2, [r1] 8012334: 613b str r3, [r7, #16] return(result); 8012336: 693b ldr r3, [r7, #16] 8012338: 2b00 cmp r3, #0 801233a: d1e6 bne.n 801230a } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 801233c: 687b ldr r3, [r7, #4] 801233e: 2220 movs r2, #32 8012340: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012344: 687b ldr r3, [r7, #4] 8012346: 2200 movs r2, #0 8012348: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 801234a: 687b ldr r3, [r7, #4] 801234c: 2200 movs r2, #0 801234e: 675a str r2, [r3, #116] @ 0x74 } 8012350: bf00 nop 8012352: 3754 adds r7, #84 @ 0x54 8012354: 46bd mov sp, r7 8012356: f85d 7b04 ldr.w r7, [sp], #4 801235a: 4770 bx lr 801235c: effffffe .word 0xeffffffe 08012360 : * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8012360: b580 push {r7, lr} 8012362: b084 sub sp, #16 8012364: af00 add r7, sp, #0 8012366: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8012368: 687b ldr r3, [r7, #4] 801236a: 6b9b ldr r3, [r3, #56] @ 0x38 801236c: 60fb str r3, [r7, #12] huart->RxXferCount = 0U; 801236e: 68fb ldr r3, [r7, #12] 8012370: 2200 movs r2, #0 8012372: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->TxXferCount = 0U; 8012376: 68fb ldr r3, [r7, #12] 8012378: 2200 movs r2, #0 801237a: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 801237e: 68f8 ldr r0, [r7, #12] 8012380: f7fe ff3a bl 80111f8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8012384: bf00 nop 8012386: 3710 adds r7, #16 8012388: 46bd mov sp, r7 801238a: bd80 pop {r7, pc} 0801238c : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) { 801238c: b480 push {r7} 801238e: b08f sub sp, #60 @ 0x3c 8012390: af00 add r7, sp, #0 8012392: 6078 str r0, [r7, #4] /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8012394: 687b ldr r3, [r7, #4] 8012396: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 801239a: 2b21 cmp r3, #33 @ 0x21 801239c: d14c bne.n 8012438 { if (huart->TxXferCount == 0U) 801239e: 687b ldr r3, [r7, #4] 80123a0: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80123a4: b29b uxth r3, r3 80123a6: 2b00 cmp r3, #0 80123a8: d132 bne.n 8012410 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 80123aa: 687b ldr r3, [r7, #4] 80123ac: 681b ldr r3, [r3, #0] 80123ae: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80123b0: 6a3b ldr r3, [r7, #32] 80123b2: e853 3f00 ldrex r3, [r3] 80123b6: 61fb str r3, [r7, #28] return(result); 80123b8: 69fb ldr r3, [r7, #28] 80123ba: f023 0380 bic.w r3, r3, #128 @ 0x80 80123be: 637b str r3, [r7, #52] @ 0x34 80123c0: 687b ldr r3, [r7, #4] 80123c2: 681b ldr r3, [r3, #0] 80123c4: 461a mov r2, r3 80123c6: 6b7b ldr r3, [r7, #52] @ 0x34 80123c8: 62fb str r3, [r7, #44] @ 0x2c 80123ca: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80123cc: 6ab9 ldr r1, [r7, #40] @ 0x28 80123ce: 6afa ldr r2, [r7, #44] @ 0x2c 80123d0: e841 2300 strex r3, r2, [r1] 80123d4: 627b str r3, [r7, #36] @ 0x24 return(result); 80123d6: 6a7b ldr r3, [r7, #36] @ 0x24 80123d8: 2b00 cmp r3, #0 80123da: d1e6 bne.n 80123aa /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80123dc: 687b ldr r3, [r7, #4] 80123de: 681b ldr r3, [r3, #0] 80123e0: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80123e2: 68fb ldr r3, [r7, #12] 80123e4: e853 3f00 ldrex r3, [r3] 80123e8: 60bb str r3, [r7, #8] return(result); 80123ea: 68bb ldr r3, [r7, #8] 80123ec: f043 0340 orr.w r3, r3, #64 @ 0x40 80123f0: 633b str r3, [r7, #48] @ 0x30 80123f2: 687b ldr r3, [r7, #4] 80123f4: 681b ldr r3, [r3, #0] 80123f6: 461a mov r2, r3 80123f8: 6b3b ldr r3, [r7, #48] @ 0x30 80123fa: 61bb str r3, [r7, #24] 80123fc: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80123fe: 6979 ldr r1, [r7, #20] 8012400: 69ba ldr r2, [r7, #24] 8012402: e841 2300 strex r3, r2, [r1] 8012406: 613b str r3, [r7, #16] return(result); 8012408: 693b ldr r3, [r7, #16] 801240a: 2b00 cmp r3, #0 801240c: d1e6 bne.n 80123dc huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); huart->pTxBuffPtr++; huart->TxXferCount--; } } } 801240e: e013 b.n 8012438 huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 8012410: 687b ldr r3, [r7, #4] 8012412: 6d1b ldr r3, [r3, #80] @ 0x50 8012414: 781a ldrb r2, [r3, #0] 8012416: 687b ldr r3, [r7, #4] 8012418: 681b ldr r3, [r3, #0] 801241a: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 801241c: 687b ldr r3, [r7, #4] 801241e: 6d1b ldr r3, [r3, #80] @ 0x50 8012420: 1c5a adds r2, r3, #1 8012422: 687b ldr r3, [r7, #4] 8012424: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 8012426: 687b ldr r3, [r7, #4] 8012428: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 801242c: b29b uxth r3, r3 801242e: 3b01 subs r3, #1 8012430: b29a uxth r2, r3 8012432: 687b ldr r3, [r7, #4] 8012434: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 8012438: bf00 nop 801243a: 373c adds r7, #60 @ 0x3c 801243c: 46bd mov sp, r7 801243e: f85d 7b04 ldr.w r7, [sp], #4 8012442: 4770 bx lr 08012444 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { 8012444: b480 push {r7} 8012446: b091 sub sp, #68 @ 0x44 8012448: af00 add r7, sp, #0 801244a: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 801244c: 687b ldr r3, [r7, #4] 801244e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8012452: 2b21 cmp r3, #33 @ 0x21 8012454: d151 bne.n 80124fa { if (huart->TxXferCount == 0U) 8012456: 687b ldr r3, [r7, #4] 8012458: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 801245c: b29b uxth r3, r3 801245e: 2b00 cmp r3, #0 8012460: d132 bne.n 80124c8 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8012462: 687b ldr r3, [r7, #4] 8012464: 681b ldr r3, [r3, #0] 8012466: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012468: 6a7b ldr r3, [r7, #36] @ 0x24 801246a: e853 3f00 ldrex r3, [r3] 801246e: 623b str r3, [r7, #32] return(result); 8012470: 6a3b ldr r3, [r7, #32] 8012472: f023 0380 bic.w r3, r3, #128 @ 0x80 8012476: 63bb str r3, [r7, #56] @ 0x38 8012478: 687b ldr r3, [r7, #4] 801247a: 681b ldr r3, [r3, #0] 801247c: 461a mov r2, r3 801247e: 6bbb ldr r3, [r7, #56] @ 0x38 8012480: 633b str r3, [r7, #48] @ 0x30 8012482: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012484: 6af9 ldr r1, [r7, #44] @ 0x2c 8012486: 6b3a ldr r2, [r7, #48] @ 0x30 8012488: e841 2300 strex r3, r2, [r1] 801248c: 62bb str r3, [r7, #40] @ 0x28 return(result); 801248e: 6abb ldr r3, [r7, #40] @ 0x28 8012490: 2b00 cmp r3, #0 8012492: d1e6 bne.n 8012462 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8012494: 687b ldr r3, [r7, #4] 8012496: 681b ldr r3, [r3, #0] 8012498: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801249a: 693b ldr r3, [r7, #16] 801249c: e853 3f00 ldrex r3, [r3] 80124a0: 60fb str r3, [r7, #12] return(result); 80124a2: 68fb ldr r3, [r7, #12] 80124a4: f043 0340 orr.w r3, r3, #64 @ 0x40 80124a8: 637b str r3, [r7, #52] @ 0x34 80124aa: 687b ldr r3, [r7, #4] 80124ac: 681b ldr r3, [r3, #0] 80124ae: 461a mov r2, r3 80124b0: 6b7b ldr r3, [r7, #52] @ 0x34 80124b2: 61fb str r3, [r7, #28] 80124b4: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80124b6: 69b9 ldr r1, [r7, #24] 80124b8: 69fa ldr r2, [r7, #28] 80124ba: e841 2300 strex r3, r2, [r1] 80124be: 617b str r3, [r7, #20] return(result); 80124c0: 697b ldr r3, [r7, #20] 80124c2: 2b00 cmp r3, #0 80124c4: d1e6 bne.n 8012494 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; } } } 80124c6: e018 b.n 80124fa tmp = (const uint16_t *) huart->pTxBuffPtr; 80124c8: 687b ldr r3, [r7, #4] 80124ca: 6d1b ldr r3, [r3, #80] @ 0x50 80124cc: 63fb str r3, [r7, #60] @ 0x3c huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 80124ce: 6bfb ldr r3, [r7, #60] @ 0x3c 80124d0: 881b ldrh r3, [r3, #0] 80124d2: 461a mov r2, r3 80124d4: 687b ldr r3, [r7, #4] 80124d6: 681b ldr r3, [r3, #0] 80124d8: f3c2 0208 ubfx r2, r2, #0, #9 80124dc: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 80124de: 687b ldr r3, [r7, #4] 80124e0: 6d1b ldr r3, [r3, #80] @ 0x50 80124e2: 1c9a adds r2, r3, #2 80124e4: 687b ldr r3, [r7, #4] 80124e6: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 80124e8: 687b ldr r3, [r7, #4] 80124ea: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80124ee: b29b uxth r3, r3 80124f0: 3b01 subs r3, #1 80124f2: b29a uxth r2, r3 80124f4: 687b ldr r3, [r7, #4] 80124f6: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 80124fa: bf00 nop 80124fc: 3744 adds r7, #68 @ 0x44 80124fe: 46bd mov sp, r7 8012500: f85d 7b04 ldr.w r7, [sp], #4 8012504: 4770 bx lr 08012506 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 8012506: b480 push {r7} 8012508: b091 sub sp, #68 @ 0x44 801250a: af00 add r7, sp, #0 801250c: 6078 str r0, [r7, #4] uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 801250e: 687b ldr r3, [r7, #4] 8012510: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8012514: 2b21 cmp r3, #33 @ 0x21 8012516: d160 bne.n 80125da { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 8012518: 687b ldr r3, [r7, #4] 801251a: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 801251e: 87fb strh r3, [r7, #62] @ 0x3e 8012520: e057 b.n 80125d2 { if (huart->TxXferCount == 0U) 8012522: 687b ldr r3, [r7, #4] 8012524: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012528: b29b uxth r3, r3 801252a: 2b00 cmp r3, #0 801252c: d133 bne.n 8012596 { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 801252e: 687b ldr r3, [r7, #4] 8012530: 681b ldr r3, [r3, #0] 8012532: 3308 adds r3, #8 8012534: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012536: 6a7b ldr r3, [r7, #36] @ 0x24 8012538: e853 3f00 ldrex r3, [r3] 801253c: 623b str r3, [r7, #32] return(result); 801253e: 6a3b ldr r3, [r7, #32] 8012540: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 8012544: 63bb str r3, [r7, #56] @ 0x38 8012546: 687b ldr r3, [r7, #4] 8012548: 681b ldr r3, [r3, #0] 801254a: 3308 adds r3, #8 801254c: 6bba ldr r2, [r7, #56] @ 0x38 801254e: 633a str r2, [r7, #48] @ 0x30 8012550: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012552: 6af9 ldr r1, [r7, #44] @ 0x2c 8012554: 6b3a ldr r2, [r7, #48] @ 0x30 8012556: e841 2300 strex r3, r2, [r1] 801255a: 62bb str r3, [r7, #40] @ 0x28 return(result); 801255c: 6abb ldr r3, [r7, #40] @ 0x28 801255e: 2b00 cmp r3, #0 8012560: d1e5 bne.n 801252e /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8012562: 687b ldr r3, [r7, #4] 8012564: 681b ldr r3, [r3, #0] 8012566: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012568: 693b ldr r3, [r7, #16] 801256a: e853 3f00 ldrex r3, [r3] 801256e: 60fb str r3, [r7, #12] return(result); 8012570: 68fb ldr r3, [r7, #12] 8012572: f043 0340 orr.w r3, r3, #64 @ 0x40 8012576: 637b str r3, [r7, #52] @ 0x34 8012578: 687b ldr r3, [r7, #4] 801257a: 681b ldr r3, [r3, #0] 801257c: 461a mov r2, r3 801257e: 6b7b ldr r3, [r7, #52] @ 0x34 8012580: 61fb str r3, [r7, #28] 8012582: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012584: 69b9 ldr r1, [r7, #24] 8012586: 69fa ldr r2, [r7, #28] 8012588: e841 2300 strex r3, r2, [r1] 801258c: 617b str r3, [r7, #20] return(result); 801258e: 697b ldr r3, [r7, #20] 8012590: 2b00 cmp r3, #0 8012592: d1e6 bne.n 8012562 break; /* force exit loop */ 8012594: e021 b.n 80125da } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 8012596: 687b ldr r3, [r7, #4] 8012598: 681b ldr r3, [r3, #0] 801259a: 69db ldr r3, [r3, #28] 801259c: f003 0380 and.w r3, r3, #128 @ 0x80 80125a0: 2b00 cmp r3, #0 80125a2: d013 beq.n 80125cc { huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 80125a4: 687b ldr r3, [r7, #4] 80125a6: 6d1b ldr r3, [r3, #80] @ 0x50 80125a8: 781a ldrb r2, [r3, #0] 80125aa: 687b ldr r3, [r7, #4] 80125ac: 681b ldr r3, [r3, #0] 80125ae: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 80125b0: 687b ldr r3, [r7, #4] 80125b2: 6d1b ldr r3, [r3, #80] @ 0x50 80125b4: 1c5a adds r2, r3, #1 80125b6: 687b ldr r3, [r7, #4] 80125b8: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 80125ba: 687b ldr r3, [r7, #4] 80125bc: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80125c0: b29b uxth r3, r3 80125c2: 3b01 subs r3, #1 80125c4: b29a uxth r2, r3 80125c6: 687b ldr r3, [r7, #4] 80125c8: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80125cc: 8ffb ldrh r3, [r7, #62] @ 0x3e 80125ce: 3b01 subs r3, #1 80125d0: 87fb strh r3, [r7, #62] @ 0x3e 80125d2: 8ffb ldrh r3, [r7, #62] @ 0x3e 80125d4: 2b00 cmp r3, #0 80125d6: d1a4 bne.n 8012522 { /* Nothing to do */ } } } } 80125d8: e7ff b.n 80125da 80125da: bf00 nop 80125dc: 3744 adds r7, #68 @ 0x44 80125de: 46bd mov sp, r7 80125e0: f85d 7b04 ldr.w r7, [sp], #4 80125e4: 4770 bx lr 080125e6 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 80125e6: b480 push {r7} 80125e8: b091 sub sp, #68 @ 0x44 80125ea: af00 add r7, sp, #0 80125ec: 6078 str r0, [r7, #4] const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 80125ee: 687b ldr r3, [r7, #4] 80125f0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80125f4: 2b21 cmp r3, #33 @ 0x21 80125f6: d165 bne.n 80126c4 { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80125f8: 687b ldr r3, [r7, #4] 80125fa: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 80125fe: 87fb strh r3, [r7, #62] @ 0x3e 8012600: e05c b.n 80126bc { if (huart->TxXferCount == 0U) 8012602: 687b ldr r3, [r7, #4] 8012604: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012608: b29b uxth r3, r3 801260a: 2b00 cmp r3, #0 801260c: d133 bne.n 8012676 { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 801260e: 687b ldr r3, [r7, #4] 8012610: 681b ldr r3, [r3, #0] 8012612: 3308 adds r3, #8 8012614: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012616: 6a3b ldr r3, [r7, #32] 8012618: e853 3f00 ldrex r3, [r3] 801261c: 61fb str r3, [r7, #28] return(result); 801261e: 69fb ldr r3, [r7, #28] 8012620: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 8012624: 637b str r3, [r7, #52] @ 0x34 8012626: 687b ldr r3, [r7, #4] 8012628: 681b ldr r3, [r3, #0] 801262a: 3308 adds r3, #8 801262c: 6b7a ldr r2, [r7, #52] @ 0x34 801262e: 62fa str r2, [r7, #44] @ 0x2c 8012630: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012632: 6ab9 ldr r1, [r7, #40] @ 0x28 8012634: 6afa ldr r2, [r7, #44] @ 0x2c 8012636: e841 2300 strex r3, r2, [r1] 801263a: 627b str r3, [r7, #36] @ 0x24 return(result); 801263c: 6a7b ldr r3, [r7, #36] @ 0x24 801263e: 2b00 cmp r3, #0 8012640: d1e5 bne.n 801260e /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8012642: 687b ldr r3, [r7, #4] 8012644: 681b ldr r3, [r3, #0] 8012646: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012648: 68fb ldr r3, [r7, #12] 801264a: e853 3f00 ldrex r3, [r3] 801264e: 60bb str r3, [r7, #8] return(result); 8012650: 68bb ldr r3, [r7, #8] 8012652: f043 0340 orr.w r3, r3, #64 @ 0x40 8012656: 633b str r3, [r7, #48] @ 0x30 8012658: 687b ldr r3, [r7, #4] 801265a: 681b ldr r3, [r3, #0] 801265c: 461a mov r2, r3 801265e: 6b3b ldr r3, [r7, #48] @ 0x30 8012660: 61bb str r3, [r7, #24] 8012662: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012664: 6979 ldr r1, [r7, #20] 8012666: 69ba ldr r2, [r7, #24] 8012668: e841 2300 strex r3, r2, [r1] 801266c: 613b str r3, [r7, #16] return(result); 801266e: 693b ldr r3, [r7, #16] 8012670: 2b00 cmp r3, #0 8012672: d1e6 bne.n 8012642 break; /* force exit loop */ 8012674: e026 b.n 80126c4 } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 8012676: 687b ldr r3, [r7, #4] 8012678: 681b ldr r3, [r3, #0] 801267a: 69db ldr r3, [r3, #28] 801267c: f003 0380 and.w r3, r3, #128 @ 0x80 8012680: 2b00 cmp r3, #0 8012682: d018 beq.n 80126b6 { tmp = (const uint16_t *) huart->pTxBuffPtr; 8012684: 687b ldr r3, [r7, #4] 8012686: 6d1b ldr r3, [r3, #80] @ 0x50 8012688: 63bb str r3, [r7, #56] @ 0x38 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 801268a: 6bbb ldr r3, [r7, #56] @ 0x38 801268c: 881b ldrh r3, [r3, #0] 801268e: 461a mov r2, r3 8012690: 687b ldr r3, [r7, #4] 8012692: 681b ldr r3, [r3, #0] 8012694: f3c2 0208 ubfx r2, r2, #0, #9 8012698: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 801269a: 687b ldr r3, [r7, #4] 801269c: 6d1b ldr r3, [r3, #80] @ 0x50 801269e: 1c9a adds r2, r3, #2 80126a0: 687b ldr r3, [r7, #4] 80126a2: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 80126a4: 687b ldr r3, [r7, #4] 80126a6: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80126aa: b29b uxth r3, r3 80126ac: 3b01 subs r3, #1 80126ae: b29a uxth r2, r3 80126b0: 687b ldr r3, [r7, #4] 80126b2: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80126b6: 8ffb ldrh r3, [r7, #62] @ 0x3e 80126b8: 3b01 subs r3, #1 80126ba: 87fb strh r3, [r7, #62] @ 0x3e 80126bc: 8ffb ldrh r3, [r7, #62] @ 0x3e 80126be: 2b00 cmp r3, #0 80126c0: d19f bne.n 8012602 { /* Nothing to do */ } } } } 80126c2: e7ff b.n 80126c4 80126c4: bf00 nop 80126c6: 3744 adds r7, #68 @ 0x44 80126c8: 46bd mov sp, r7 80126ca: f85d 7b04 ldr.w r7, [sp], #4 80126ce: 4770 bx lr 080126d0 : * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 80126d0: b580 push {r7, lr} 80126d2: b088 sub sp, #32 80126d4: af00 add r7, sp, #0 80126d6: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80126d8: 687b ldr r3, [r7, #4] 80126da: 681b ldr r3, [r3, #0] 80126dc: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80126de: 68fb ldr r3, [r7, #12] 80126e0: e853 3f00 ldrex r3, [r3] 80126e4: 60bb str r3, [r7, #8] return(result); 80126e6: 68bb ldr r3, [r7, #8] 80126e8: f023 0340 bic.w r3, r3, #64 @ 0x40 80126ec: 61fb str r3, [r7, #28] 80126ee: 687b ldr r3, [r7, #4] 80126f0: 681b ldr r3, [r3, #0] 80126f2: 461a mov r2, r3 80126f4: 69fb ldr r3, [r7, #28] 80126f6: 61bb str r3, [r7, #24] 80126f8: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80126fa: 6979 ldr r1, [r7, #20] 80126fc: 69ba ldr r2, [r7, #24] 80126fe: e841 2300 strex r3, r2, [r1] 8012702: 613b str r3, [r7, #16] return(result); 8012704: 693b ldr r3, [r7, #16] 8012706: 2b00 cmp r3, #0 8012708: d1e6 bne.n 80126d8 /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 801270a: 687b ldr r3, [r7, #4] 801270c: 2220 movs r2, #32 801270e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Cleat TxISR function pointer */ huart->TxISR = NULL; 8012712: 687b ldr r3, [r7, #4] 8012714: 2200 movs r2, #0 8012716: 679a str r2, [r3, #120] @ 0x78 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8012718: 6878 ldr r0, [r7, #4] 801271a: f7f1 ffcd bl 80046b8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 801271e: bf00 nop 8012720: 3720 adds r7, #32 8012722: 46bd mov sp, r7 8012724: bd80 pop {r7, pc} ... 08012728 : * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) { 8012728: b580 push {r7, lr} 801272a: b09c sub sp, #112 @ 0x70 801272c: af00 add r7, sp, #0 801272e: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 8012730: 687b ldr r3, [r7, #4] 8012732: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8012736: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 801273a: 687b ldr r3, [r7, #4] 801273c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8012740: 2b22 cmp r3, #34 @ 0x22 8012742: f040 80be bne.w 80128c2 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8012746: 687b ldr r3, [r7, #4] 8012748: 681b ldr r3, [r3, #0] 801274a: 6a5b ldr r3, [r3, #36] @ 0x24 801274c: f8a7 306c strh.w r3, [r7, #108] @ 0x6c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 8012750: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 8012754: b2d9 uxtb r1, r3 8012756: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 801275a: b2da uxtb r2, r3 801275c: 687b ldr r3, [r7, #4] 801275e: 6d9b ldr r3, [r3, #88] @ 0x58 8012760: 400a ands r2, r1 8012762: b2d2 uxtb r2, r2 8012764: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8012766: 687b ldr r3, [r7, #4] 8012768: 6d9b ldr r3, [r3, #88] @ 0x58 801276a: 1c5a adds r2, r3, #1 801276c: 687b ldr r3, [r7, #4] 801276e: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8012770: 687b ldr r3, [r7, #4] 8012772: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012776: b29b uxth r3, r3 8012778: 3b01 subs r3, #1 801277a: b29a uxth r2, r3 801277c: 687b ldr r3, [r7, #4] 801277e: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 8012782: 687b ldr r3, [r7, #4] 8012784: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012788: b29b uxth r3, r3 801278a: 2b00 cmp r3, #0 801278c: f040 80a1 bne.w 80128d2 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8012790: 687b ldr r3, [r7, #4] 8012792: 681b ldr r3, [r3, #0] 8012794: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012796: 6cfb ldr r3, [r7, #76] @ 0x4c 8012798: e853 3f00 ldrex r3, [r3] 801279c: 64bb str r3, [r7, #72] @ 0x48 return(result); 801279e: 6cbb ldr r3, [r7, #72] @ 0x48 80127a0: f423 7390 bic.w r3, r3, #288 @ 0x120 80127a4: 66bb str r3, [r7, #104] @ 0x68 80127a6: 687b ldr r3, [r7, #4] 80127a8: 681b ldr r3, [r3, #0] 80127aa: 461a mov r2, r3 80127ac: 6ebb ldr r3, [r7, #104] @ 0x68 80127ae: 65bb str r3, [r7, #88] @ 0x58 80127b0: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80127b2: 6d79 ldr r1, [r7, #84] @ 0x54 80127b4: 6dba ldr r2, [r7, #88] @ 0x58 80127b6: e841 2300 strex r3, r2, [r1] 80127ba: 653b str r3, [r7, #80] @ 0x50 return(result); 80127bc: 6d3b ldr r3, [r7, #80] @ 0x50 80127be: 2b00 cmp r3, #0 80127c0: d1e6 bne.n 8012790 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80127c2: 687b ldr r3, [r7, #4] 80127c4: 681b ldr r3, [r3, #0] 80127c6: 3308 adds r3, #8 80127c8: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80127ca: 6bbb ldr r3, [r7, #56] @ 0x38 80127cc: e853 3f00 ldrex r3, [r3] 80127d0: 637b str r3, [r7, #52] @ 0x34 return(result); 80127d2: 6b7b ldr r3, [r7, #52] @ 0x34 80127d4: f023 0301 bic.w r3, r3, #1 80127d8: 667b str r3, [r7, #100] @ 0x64 80127da: 687b ldr r3, [r7, #4] 80127dc: 681b ldr r3, [r3, #0] 80127de: 3308 adds r3, #8 80127e0: 6e7a ldr r2, [r7, #100] @ 0x64 80127e2: 647a str r2, [r7, #68] @ 0x44 80127e4: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80127e6: 6c39 ldr r1, [r7, #64] @ 0x40 80127e8: 6c7a ldr r2, [r7, #68] @ 0x44 80127ea: e841 2300 strex r3, r2, [r1] 80127ee: 63fb str r3, [r7, #60] @ 0x3c return(result); 80127f0: 6bfb ldr r3, [r7, #60] @ 0x3c 80127f2: 2b00 cmp r3, #0 80127f4: d1e5 bne.n 80127c2 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80127f6: 687b ldr r3, [r7, #4] 80127f8: 2220 movs r2, #32 80127fa: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 80127fe: 687b ldr r3, [r7, #4] 8012800: 2200 movs r2, #0 8012802: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8012804: 687b ldr r3, [r7, #4] 8012806: 2200 movs r2, #0 8012808: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 801280a: 687b ldr r3, [r7, #4] 801280c: 681b ldr r3, [r3, #0] 801280e: 4a33 ldr r2, [pc, #204] @ (80128dc ) 8012810: 4293 cmp r3, r2 8012812: d01f beq.n 8012854 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8012814: 687b ldr r3, [r7, #4] 8012816: 681b ldr r3, [r3, #0] 8012818: 685b ldr r3, [r3, #4] 801281a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 801281e: 2b00 cmp r3, #0 8012820: d018 beq.n 8012854 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8012822: 687b ldr r3, [r7, #4] 8012824: 681b ldr r3, [r3, #0] 8012826: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012828: 6a7b ldr r3, [r7, #36] @ 0x24 801282a: e853 3f00 ldrex r3, [r3] 801282e: 623b str r3, [r7, #32] return(result); 8012830: 6a3b ldr r3, [r7, #32] 8012832: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8012836: 663b str r3, [r7, #96] @ 0x60 8012838: 687b ldr r3, [r7, #4] 801283a: 681b ldr r3, [r3, #0] 801283c: 461a mov r2, r3 801283e: 6e3b ldr r3, [r7, #96] @ 0x60 8012840: 633b str r3, [r7, #48] @ 0x30 8012842: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012844: 6af9 ldr r1, [r7, #44] @ 0x2c 8012846: 6b3a ldr r2, [r7, #48] @ 0x30 8012848: e841 2300 strex r3, r2, [r1] 801284c: 62bb str r3, [r7, #40] @ 0x28 return(result); 801284e: 6abb ldr r3, [r7, #40] @ 0x28 8012850: 2b00 cmp r3, #0 8012852: d1e6 bne.n 8012822 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012854: 687b ldr r3, [r7, #4] 8012856: 6edb ldr r3, [r3, #108] @ 0x6c 8012858: 2b01 cmp r3, #1 801285a: d12e bne.n 80128ba { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801285c: 687b ldr r3, [r7, #4] 801285e: 2200 movs r2, #0 8012860: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012862: 687b ldr r3, [r7, #4] 8012864: 681b ldr r3, [r3, #0] 8012866: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012868: 693b ldr r3, [r7, #16] 801286a: e853 3f00 ldrex r3, [r3] 801286e: 60fb str r3, [r7, #12] return(result); 8012870: 68fb ldr r3, [r7, #12] 8012872: f023 0310 bic.w r3, r3, #16 8012876: 65fb str r3, [r7, #92] @ 0x5c 8012878: 687b ldr r3, [r7, #4] 801287a: 681b ldr r3, [r3, #0] 801287c: 461a mov r2, r3 801287e: 6dfb ldr r3, [r7, #92] @ 0x5c 8012880: 61fb str r3, [r7, #28] 8012882: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012884: 69b9 ldr r1, [r7, #24] 8012886: 69fa ldr r2, [r7, #28] 8012888: e841 2300 strex r3, r2, [r1] 801288c: 617b str r3, [r7, #20] return(result); 801288e: 697b ldr r3, [r7, #20] 8012890: 2b00 cmp r3, #0 8012892: d1e6 bne.n 8012862 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8012894: 687b ldr r3, [r7, #4] 8012896: 681b ldr r3, [r3, #0] 8012898: 69db ldr r3, [r3, #28] 801289a: f003 0310 and.w r3, r3, #16 801289e: 2b10 cmp r3, #16 80128a0: d103 bne.n 80128aa { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 80128a2: 687b ldr r3, [r7, #4] 80128a4: 681b ldr r3, [r3, #0] 80128a6: 2210 movs r2, #16 80128a8: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 80128aa: 687b ldr r3, [r7, #4] 80128ac: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 80128b0: 4619 mov r1, r3 80128b2: 6878 ldr r0, [r7, #4] 80128b4: f7f1 fed6 bl 8004664 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 80128b8: e00b b.n 80128d2 HAL_UART_RxCpltCallback(huart); 80128ba: 6878 ldr r0, [r7, #4] 80128bc: f7f1 fec8 bl 8004650 } 80128c0: e007 b.n 80128d2 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 80128c2: 687b ldr r3, [r7, #4] 80128c4: 681b ldr r3, [r3, #0] 80128c6: 699a ldr r2, [r3, #24] 80128c8: 687b ldr r3, [r7, #4] 80128ca: 681b ldr r3, [r3, #0] 80128cc: f042 0208 orr.w r2, r2, #8 80128d0: 619a str r2, [r3, #24] } 80128d2: bf00 nop 80128d4: 3770 adds r7, #112 @ 0x70 80128d6: 46bd mov sp, r7 80128d8: bd80 pop {r7, pc} 80128da: bf00 nop 80128dc: 58000c00 .word 0x58000c00 080128e0 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { 80128e0: b580 push {r7, lr} 80128e2: b09c sub sp, #112 @ 0x70 80128e4: af00 add r7, sp, #0 80128e6: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 80128e8: 687b ldr r3, [r7, #4] 80128ea: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 80128ee: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80128f2: 687b ldr r3, [r7, #4] 80128f4: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80128f8: 2b22 cmp r3, #34 @ 0x22 80128fa: f040 80be bne.w 8012a7a { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 80128fe: 687b ldr r3, [r7, #4] 8012900: 681b ldr r3, [r3, #0] 8012902: 6a5b ldr r3, [r3, #36] @ 0x24 8012904: f8a7 306c strh.w r3, [r7, #108] @ 0x6c tmp = (uint16_t *) huart->pRxBuffPtr ; 8012908: 687b ldr r3, [r7, #4] 801290a: 6d9b ldr r3, [r3, #88] @ 0x58 801290c: 66bb str r3, [r7, #104] @ 0x68 *tmp = (uint16_t)(uhdata & uhMask); 801290e: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c 8012912: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 8012916: 4013 ands r3, r2 8012918: b29a uxth r2, r3 801291a: 6ebb ldr r3, [r7, #104] @ 0x68 801291c: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 801291e: 687b ldr r3, [r7, #4] 8012920: 6d9b ldr r3, [r3, #88] @ 0x58 8012922: 1c9a adds r2, r3, #2 8012924: 687b ldr r3, [r7, #4] 8012926: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8012928: 687b ldr r3, [r7, #4] 801292a: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 801292e: b29b uxth r3, r3 8012930: 3b01 subs r3, #1 8012932: b29a uxth r2, r3 8012934: 687b ldr r3, [r7, #4] 8012936: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 801293a: 687b ldr r3, [r7, #4] 801293c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012940: b29b uxth r3, r3 8012942: 2b00 cmp r3, #0 8012944: f040 80a1 bne.w 8012a8a { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8012948: 687b ldr r3, [r7, #4] 801294a: 681b ldr r3, [r3, #0] 801294c: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801294e: 6cbb ldr r3, [r7, #72] @ 0x48 8012950: e853 3f00 ldrex r3, [r3] 8012954: 647b str r3, [r7, #68] @ 0x44 return(result); 8012956: 6c7b ldr r3, [r7, #68] @ 0x44 8012958: f423 7390 bic.w r3, r3, #288 @ 0x120 801295c: 667b str r3, [r7, #100] @ 0x64 801295e: 687b ldr r3, [r7, #4] 8012960: 681b ldr r3, [r3, #0] 8012962: 461a mov r2, r3 8012964: 6e7b ldr r3, [r7, #100] @ 0x64 8012966: 657b str r3, [r7, #84] @ 0x54 8012968: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801296a: 6d39 ldr r1, [r7, #80] @ 0x50 801296c: 6d7a ldr r2, [r7, #84] @ 0x54 801296e: e841 2300 strex r3, r2, [r1] 8012972: 64fb str r3, [r7, #76] @ 0x4c return(result); 8012974: 6cfb ldr r3, [r7, #76] @ 0x4c 8012976: 2b00 cmp r3, #0 8012978: d1e6 bne.n 8012948 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 801297a: 687b ldr r3, [r7, #4] 801297c: 681b ldr r3, [r3, #0] 801297e: 3308 adds r3, #8 8012980: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012982: 6b7b ldr r3, [r7, #52] @ 0x34 8012984: e853 3f00 ldrex r3, [r3] 8012988: 633b str r3, [r7, #48] @ 0x30 return(result); 801298a: 6b3b ldr r3, [r7, #48] @ 0x30 801298c: f023 0301 bic.w r3, r3, #1 8012990: 663b str r3, [r7, #96] @ 0x60 8012992: 687b ldr r3, [r7, #4] 8012994: 681b ldr r3, [r3, #0] 8012996: 3308 adds r3, #8 8012998: 6e3a ldr r2, [r7, #96] @ 0x60 801299a: 643a str r2, [r7, #64] @ 0x40 801299c: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801299e: 6bf9 ldr r1, [r7, #60] @ 0x3c 80129a0: 6c3a ldr r2, [r7, #64] @ 0x40 80129a2: e841 2300 strex r3, r2, [r1] 80129a6: 63bb str r3, [r7, #56] @ 0x38 return(result); 80129a8: 6bbb ldr r3, [r7, #56] @ 0x38 80129aa: 2b00 cmp r3, #0 80129ac: d1e5 bne.n 801297a /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80129ae: 687b ldr r3, [r7, #4] 80129b0: 2220 movs r2, #32 80129b2: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 80129b6: 687b ldr r3, [r7, #4] 80129b8: 2200 movs r2, #0 80129ba: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80129bc: 687b ldr r3, [r7, #4] 80129be: 2200 movs r2, #0 80129c0: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 80129c2: 687b ldr r3, [r7, #4] 80129c4: 681b ldr r3, [r3, #0] 80129c6: 4a33 ldr r2, [pc, #204] @ (8012a94 ) 80129c8: 4293 cmp r3, r2 80129ca: d01f beq.n 8012a0c { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 80129cc: 687b ldr r3, [r7, #4] 80129ce: 681b ldr r3, [r3, #0] 80129d0: 685b ldr r3, [r3, #4] 80129d2: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80129d6: 2b00 cmp r3, #0 80129d8: d018 beq.n 8012a0c { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 80129da: 687b ldr r3, [r7, #4] 80129dc: 681b ldr r3, [r3, #0] 80129de: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80129e0: 6a3b ldr r3, [r7, #32] 80129e2: e853 3f00 ldrex r3, [r3] 80129e6: 61fb str r3, [r7, #28] return(result); 80129e8: 69fb ldr r3, [r7, #28] 80129ea: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 80129ee: 65fb str r3, [r7, #92] @ 0x5c 80129f0: 687b ldr r3, [r7, #4] 80129f2: 681b ldr r3, [r3, #0] 80129f4: 461a mov r2, r3 80129f6: 6dfb ldr r3, [r7, #92] @ 0x5c 80129f8: 62fb str r3, [r7, #44] @ 0x2c 80129fa: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80129fc: 6ab9 ldr r1, [r7, #40] @ 0x28 80129fe: 6afa ldr r2, [r7, #44] @ 0x2c 8012a00: e841 2300 strex r3, r2, [r1] 8012a04: 627b str r3, [r7, #36] @ 0x24 return(result); 8012a06: 6a7b ldr r3, [r7, #36] @ 0x24 8012a08: 2b00 cmp r3, #0 8012a0a: d1e6 bne.n 80129da } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012a0c: 687b ldr r3, [r7, #4] 8012a0e: 6edb ldr r3, [r3, #108] @ 0x6c 8012a10: 2b01 cmp r3, #1 8012a12: d12e bne.n 8012a72 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012a14: 687b ldr r3, [r7, #4] 8012a16: 2200 movs r2, #0 8012a18: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012a1a: 687b ldr r3, [r7, #4] 8012a1c: 681b ldr r3, [r3, #0] 8012a1e: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012a20: 68fb ldr r3, [r7, #12] 8012a22: e853 3f00 ldrex r3, [r3] 8012a26: 60bb str r3, [r7, #8] return(result); 8012a28: 68bb ldr r3, [r7, #8] 8012a2a: f023 0310 bic.w r3, r3, #16 8012a2e: 65bb str r3, [r7, #88] @ 0x58 8012a30: 687b ldr r3, [r7, #4] 8012a32: 681b ldr r3, [r3, #0] 8012a34: 461a mov r2, r3 8012a36: 6dbb ldr r3, [r7, #88] @ 0x58 8012a38: 61bb str r3, [r7, #24] 8012a3a: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012a3c: 6979 ldr r1, [r7, #20] 8012a3e: 69ba ldr r2, [r7, #24] 8012a40: e841 2300 strex r3, r2, [r1] 8012a44: 613b str r3, [r7, #16] return(result); 8012a46: 693b ldr r3, [r7, #16] 8012a48: 2b00 cmp r3, #0 8012a4a: d1e6 bne.n 8012a1a if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8012a4c: 687b ldr r3, [r7, #4] 8012a4e: 681b ldr r3, [r3, #0] 8012a50: 69db ldr r3, [r3, #28] 8012a52: f003 0310 and.w r3, r3, #16 8012a56: 2b10 cmp r3, #16 8012a58: d103 bne.n 8012a62 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8012a5a: 687b ldr r3, [r7, #4] 8012a5c: 681b ldr r3, [r3, #0] 8012a5e: 2210 movs r2, #16 8012a60: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8012a62: 687b ldr r3, [r7, #4] 8012a64: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8012a68: 4619 mov r1, r3 8012a6a: 6878 ldr r0, [r7, #4] 8012a6c: f7f1 fdfa bl 8004664 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8012a70: e00b b.n 8012a8a HAL_UART_RxCpltCallback(huart); 8012a72: 6878 ldr r0, [r7, #4] 8012a74: f7f1 fdec bl 8004650 } 8012a78: e007 b.n 8012a8a __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8012a7a: 687b ldr r3, [r7, #4] 8012a7c: 681b ldr r3, [r3, #0] 8012a7e: 699a ldr r2, [r3, #24] 8012a80: 687b ldr r3, [r7, #4] 8012a82: 681b ldr r3, [r3, #0] 8012a84: f042 0208 orr.w r2, r2, #8 8012a88: 619a str r2, [r3, #24] } 8012a8a: bf00 nop 8012a8c: 3770 adds r7, #112 @ 0x70 8012a8e: 46bd mov sp, r7 8012a90: bd80 pop {r7, pc} 8012a92: bf00 nop 8012a94: 58000c00 .word 0x58000c00 08012a98 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 8012a98: b580 push {r7, lr} 8012a9a: b0ac sub sp, #176 @ 0xb0 8012a9c: af00 add r7, sp, #0 8012a9e: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 8012aa0: 687b ldr r3, [r7, #4] 8012aa2: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8012aa6: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 8012aaa: 687b ldr r3, [r7, #4] 8012aac: 681b ldr r3, [r3, #0] 8012aae: 69db ldr r3, [r3, #28] 8012ab0: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr1its = READ_REG(huart->Instance->CR1); 8012ab4: 687b ldr r3, [r7, #4] 8012ab6: 681b ldr r3, [r3, #0] 8012ab8: 681b ldr r3, [r3, #0] 8012aba: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8012abe: 687b ldr r3, [r7, #4] 8012ac0: 681b ldr r3, [r3, #0] 8012ac2: 689b ldr r3, [r3, #8] 8012ac4: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8012ac8: 687b ldr r3, [r7, #4] 8012aca: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8012ace: 2b22 cmp r3, #34 @ 0x22 8012ad0: f040 8180 bne.w 8012dd4 { nb_rx_data = huart->NbRxDataToProcess; 8012ad4: 687b ldr r3, [r7, #4] 8012ad6: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8012ada: f8a7 309e strh.w r3, [r7, #158] @ 0x9e while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8012ade: e123 b.n 8012d28 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8012ae0: 687b ldr r3, [r7, #4] 8012ae2: 681b ldr r3, [r3, #0] 8012ae4: 6a5b ldr r3, [r3, #36] @ 0x24 8012ae6: f8a7 309c strh.w r3, [r7, #156] @ 0x9c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 8012aea: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c 8012aee: b2d9 uxtb r1, r3 8012af0: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa 8012af4: b2da uxtb r2, r3 8012af6: 687b ldr r3, [r7, #4] 8012af8: 6d9b ldr r3, [r3, #88] @ 0x58 8012afa: 400a ands r2, r1 8012afc: b2d2 uxtb r2, r2 8012afe: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8012b00: 687b ldr r3, [r7, #4] 8012b02: 6d9b ldr r3, [r3, #88] @ 0x58 8012b04: 1c5a adds r2, r3, #1 8012b06: 687b ldr r3, [r7, #4] 8012b08: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8012b0a: 687b ldr r3, [r7, #4] 8012b0c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012b10: b29b uxth r3, r3 8012b12: 3b01 subs r3, #1 8012b14: b29a uxth r2, r3 8012b16: 687b ldr r3, [r7, #4] 8012b18: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 8012b1c: 687b ldr r3, [r7, #4] 8012b1e: 681b ldr r3, [r3, #0] 8012b20: 69db ldr r3, [r3, #28] 8012b22: f8c7 30ac str.w r3, [r7, #172] @ 0xac /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8012b26: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012b2a: f003 0307 and.w r3, r3, #7 8012b2e: 2b00 cmp r3, #0 8012b30: d053 beq.n 8012bda { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8012b32: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012b36: f003 0301 and.w r3, r3, #1 8012b3a: 2b00 cmp r3, #0 8012b3c: d011 beq.n 8012b62 8012b3e: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 8012b42: f403 7380 and.w r3, r3, #256 @ 0x100 8012b46: 2b00 cmp r3, #0 8012b48: d00b beq.n 8012b62 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8012b4a: 687b ldr r3, [r7, #4] 8012b4c: 681b ldr r3, [r3, #0] 8012b4e: 2201 movs r2, #1 8012b50: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8012b52: 687b ldr r3, [r7, #4] 8012b54: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012b58: f043 0201 orr.w r2, r3, #1 8012b5c: 687b ldr r3, [r7, #4] 8012b5e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8012b62: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012b66: f003 0302 and.w r3, r3, #2 8012b6a: 2b00 cmp r3, #0 8012b6c: d011 beq.n 8012b92 8012b6e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8012b72: f003 0301 and.w r3, r3, #1 8012b76: 2b00 cmp r3, #0 8012b78: d00b beq.n 8012b92 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8012b7a: 687b ldr r3, [r7, #4] 8012b7c: 681b ldr r3, [r3, #0] 8012b7e: 2202 movs r2, #2 8012b80: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8012b82: 687b ldr r3, [r7, #4] 8012b84: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012b88: f043 0204 orr.w r2, r3, #4 8012b8c: 687b ldr r3, [r7, #4] 8012b8e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8012b92: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012b96: f003 0304 and.w r3, r3, #4 8012b9a: 2b00 cmp r3, #0 8012b9c: d011 beq.n 8012bc2 8012b9e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8012ba2: f003 0301 and.w r3, r3, #1 8012ba6: 2b00 cmp r3, #0 8012ba8: d00b beq.n 8012bc2 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8012baa: 687b ldr r3, [r7, #4] 8012bac: 681b ldr r3, [r3, #0] 8012bae: 2204 movs r2, #4 8012bb0: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8012bb2: 687b ldr r3, [r7, #4] 8012bb4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012bb8: f043 0202 orr.w r2, r3, #2 8012bbc: 687b ldr r3, [r7, #4] 8012bbe: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8012bc2: 687b ldr r3, [r7, #4] 8012bc4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012bc8: 2b00 cmp r3, #0 8012bca: d006 beq.n 8012bda #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8012bcc: 6878 ldr r0, [r7, #4] 8012bce: f7fe fb13 bl 80111f8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012bd2: 687b ldr r3, [r7, #4] 8012bd4: 2200 movs r2, #0 8012bd6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 8012bda: 687b ldr r3, [r7, #4] 8012bdc: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012be0: b29b uxth r3, r3 8012be2: 2b00 cmp r3, #0 8012be4: f040 80a0 bne.w 8012d28 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8012be8: 687b ldr r3, [r7, #4] 8012bea: 681b ldr r3, [r3, #0] 8012bec: 673b str r3, [r7, #112] @ 0x70 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012bee: 6f3b ldr r3, [r7, #112] @ 0x70 8012bf0: e853 3f00 ldrex r3, [r3] 8012bf4: 66fb str r3, [r7, #108] @ 0x6c return(result); 8012bf6: 6efb ldr r3, [r7, #108] @ 0x6c 8012bf8: f423 7380 bic.w r3, r3, #256 @ 0x100 8012bfc: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8012c00: 687b ldr r3, [r7, #4] 8012c02: 681b ldr r3, [r3, #0] 8012c04: 461a mov r2, r3 8012c06: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8012c0a: 67fb str r3, [r7, #124] @ 0x7c 8012c0c: 67ba str r2, [r7, #120] @ 0x78 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012c0e: 6fb9 ldr r1, [r7, #120] @ 0x78 8012c10: 6ffa ldr r2, [r7, #124] @ 0x7c 8012c12: e841 2300 strex r3, r2, [r1] 8012c16: 677b str r3, [r7, #116] @ 0x74 return(result); 8012c18: 6f7b ldr r3, [r7, #116] @ 0x74 8012c1a: 2b00 cmp r3, #0 8012c1c: d1e4 bne.n 8012be8 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8012c1e: 687b ldr r3, [r7, #4] 8012c20: 681b ldr r3, [r3, #0] 8012c22: 3308 adds r3, #8 8012c24: 65fb str r3, [r7, #92] @ 0x5c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012c26: 6dfb ldr r3, [r7, #92] @ 0x5c 8012c28: e853 3f00 ldrex r3, [r3] 8012c2c: 65bb str r3, [r7, #88] @ 0x58 return(result); 8012c2e: 6dba ldr r2, [r7, #88] @ 0x58 8012c30: 4b6e ldr r3, [pc, #440] @ (8012dec ) 8012c32: 4013 ands r3, r2 8012c34: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8012c38: 687b ldr r3, [r7, #4] 8012c3a: 681b ldr r3, [r3, #0] 8012c3c: 3308 adds r3, #8 8012c3e: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8012c42: 66ba str r2, [r7, #104] @ 0x68 8012c44: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012c46: 6e79 ldr r1, [r7, #100] @ 0x64 8012c48: 6eba ldr r2, [r7, #104] @ 0x68 8012c4a: e841 2300 strex r3, r2, [r1] 8012c4e: 663b str r3, [r7, #96] @ 0x60 return(result); 8012c50: 6e3b ldr r3, [r7, #96] @ 0x60 8012c52: 2b00 cmp r3, #0 8012c54: d1e3 bne.n 8012c1e /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012c56: 687b ldr r3, [r7, #4] 8012c58: 2220 movs r2, #32 8012c5a: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8012c5e: 687b ldr r3, [r7, #4] 8012c60: 2200 movs r2, #0 8012c62: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8012c64: 687b ldr r3, [r7, #4] 8012c66: 2200 movs r2, #0 8012c68: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8012c6a: 687b ldr r3, [r7, #4] 8012c6c: 681b ldr r3, [r3, #0] 8012c6e: 4a60 ldr r2, [pc, #384] @ (8012df0 ) 8012c70: 4293 cmp r3, r2 8012c72: d021 beq.n 8012cb8 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8012c74: 687b ldr r3, [r7, #4] 8012c76: 681b ldr r3, [r3, #0] 8012c78: 685b ldr r3, [r3, #4] 8012c7a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8012c7e: 2b00 cmp r3, #0 8012c80: d01a beq.n 8012cb8 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8012c82: 687b ldr r3, [r7, #4] 8012c84: 681b ldr r3, [r3, #0] 8012c86: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012c88: 6cbb ldr r3, [r7, #72] @ 0x48 8012c8a: e853 3f00 ldrex r3, [r3] 8012c8e: 647b str r3, [r7, #68] @ 0x44 return(result); 8012c90: 6c7b ldr r3, [r7, #68] @ 0x44 8012c92: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8012c96: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8012c9a: 687b ldr r3, [r7, #4] 8012c9c: 681b ldr r3, [r3, #0] 8012c9e: 461a mov r2, r3 8012ca0: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8012ca4: 657b str r3, [r7, #84] @ 0x54 8012ca6: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012ca8: 6d39 ldr r1, [r7, #80] @ 0x50 8012caa: 6d7a ldr r2, [r7, #84] @ 0x54 8012cac: e841 2300 strex r3, r2, [r1] 8012cb0: 64fb str r3, [r7, #76] @ 0x4c return(result); 8012cb2: 6cfb ldr r3, [r7, #76] @ 0x4c 8012cb4: 2b00 cmp r3, #0 8012cb6: d1e4 bne.n 8012c82 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012cb8: 687b ldr r3, [r7, #4] 8012cba: 6edb ldr r3, [r3, #108] @ 0x6c 8012cbc: 2b01 cmp r3, #1 8012cbe: d130 bne.n 8012d22 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012cc0: 687b ldr r3, [r7, #4] 8012cc2: 2200 movs r2, #0 8012cc4: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012cc6: 687b ldr r3, [r7, #4] 8012cc8: 681b ldr r3, [r3, #0] 8012cca: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012ccc: 6b7b ldr r3, [r7, #52] @ 0x34 8012cce: e853 3f00 ldrex r3, [r3] 8012cd2: 633b str r3, [r7, #48] @ 0x30 return(result); 8012cd4: 6b3b ldr r3, [r7, #48] @ 0x30 8012cd6: f023 0310 bic.w r3, r3, #16 8012cda: f8c7 308c str.w r3, [r7, #140] @ 0x8c 8012cde: 687b ldr r3, [r7, #4] 8012ce0: 681b ldr r3, [r3, #0] 8012ce2: 461a mov r2, r3 8012ce4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8012ce8: 643b str r3, [r7, #64] @ 0x40 8012cea: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012cec: 6bf9 ldr r1, [r7, #60] @ 0x3c 8012cee: 6c3a ldr r2, [r7, #64] @ 0x40 8012cf0: e841 2300 strex r3, r2, [r1] 8012cf4: 63bb str r3, [r7, #56] @ 0x38 return(result); 8012cf6: 6bbb ldr r3, [r7, #56] @ 0x38 8012cf8: 2b00 cmp r3, #0 8012cfa: d1e4 bne.n 8012cc6 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8012cfc: 687b ldr r3, [r7, #4] 8012cfe: 681b ldr r3, [r3, #0] 8012d00: 69db ldr r3, [r3, #28] 8012d02: f003 0310 and.w r3, r3, #16 8012d06: 2b10 cmp r3, #16 8012d08: d103 bne.n 8012d12 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8012d0a: 687b ldr r3, [r7, #4] 8012d0c: 681b ldr r3, [r3, #0] 8012d0e: 2210 movs r2, #16 8012d10: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8012d12: 687b ldr r3, [r7, #4] 8012d14: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8012d18: 4619 mov r1, r3 8012d1a: 6878 ldr r0, [r7, #4] 8012d1c: f7f1 fca2 bl 8004664 8012d20: e002 b.n 8012d28 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8012d22: 6878 ldr r0, [r7, #4] 8012d24: f7f1 fc94 bl 8004650 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8012d28: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e 8012d2c: 2b00 cmp r3, #0 8012d2e: d006 beq.n 8012d3e 8012d30: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012d34: f003 0320 and.w r3, r3, #32 8012d38: 2b00 cmp r3, #0 8012d3a: f47f aed1 bne.w 8012ae0 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 8012d3e: 687b ldr r3, [r7, #4] 8012d40: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012d44: f8a7 308a strh.w r3, [r7, #138] @ 0x8a if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 8012d48: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 8012d4c: 2b00 cmp r3, #0 8012d4e: d049 beq.n 8012de4 8012d50: 687b ldr r3, [r7, #4] 8012d52: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8012d56: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a 8012d5a: 429a cmp r2, r3 8012d5c: d242 bcs.n 8012de4 { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8012d5e: 687b ldr r3, [r7, #4] 8012d60: 681b ldr r3, [r3, #0] 8012d62: 3308 adds r3, #8 8012d64: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012d66: 6a3b ldr r3, [r7, #32] 8012d68: e853 3f00 ldrex r3, [r3] 8012d6c: 61fb str r3, [r7, #28] return(result); 8012d6e: 69fb ldr r3, [r7, #28] 8012d70: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8012d74: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8012d78: 687b ldr r3, [r7, #4] 8012d7a: 681b ldr r3, [r3, #0] 8012d7c: 3308 adds r3, #8 8012d7e: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 8012d82: 62fa str r2, [r7, #44] @ 0x2c 8012d84: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d86: 6ab9 ldr r1, [r7, #40] @ 0x28 8012d88: 6afa ldr r2, [r7, #44] @ 0x2c 8012d8a: e841 2300 strex r3, r2, [r1] 8012d8e: 627b str r3, [r7, #36] @ 0x24 return(result); 8012d90: 6a7b ldr r3, [r7, #36] @ 0x24 8012d92: 2b00 cmp r3, #0 8012d94: d1e3 bne.n 8012d5e /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; 8012d96: 687b ldr r3, [r7, #4] 8012d98: 4a16 ldr r2, [pc, #88] @ (8012df4 ) 8012d9a: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8012d9c: 687b ldr r3, [r7, #4] 8012d9e: 681b ldr r3, [r3, #0] 8012da0: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012da2: 68fb ldr r3, [r7, #12] 8012da4: e853 3f00 ldrex r3, [r3] 8012da8: 60bb str r3, [r7, #8] return(result); 8012daa: 68bb ldr r3, [r7, #8] 8012dac: f043 0320 orr.w r3, r3, #32 8012db0: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8012db4: 687b ldr r3, [r7, #4] 8012db6: 681b ldr r3, [r3, #0] 8012db8: 461a mov r2, r3 8012dba: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8012dbe: 61bb str r3, [r7, #24] 8012dc0: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012dc2: 6979 ldr r1, [r7, #20] 8012dc4: 69ba ldr r2, [r7, #24] 8012dc6: e841 2300 strex r3, r2, [r1] 8012dca: 613b str r3, [r7, #16] return(result); 8012dcc: 693b ldr r3, [r7, #16] 8012dce: 2b00 cmp r3, #0 8012dd0: d1e4 bne.n 8012d9c else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8012dd2: e007 b.n 8012de4 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8012dd4: 687b ldr r3, [r7, #4] 8012dd6: 681b ldr r3, [r3, #0] 8012dd8: 699a ldr r2, [r3, #24] 8012dda: 687b ldr r3, [r7, #4] 8012ddc: 681b ldr r3, [r3, #0] 8012dde: f042 0208 orr.w r2, r2, #8 8012de2: 619a str r2, [r3, #24] } 8012de4: bf00 nop 8012de6: 37b0 adds r7, #176 @ 0xb0 8012de8: 46bd mov sp, r7 8012dea: bd80 pop {r7, pc} 8012dec: effffffe .word 0xeffffffe 8012df0: 58000c00 .word 0x58000c00 8012df4: 08012729 .word 0x08012729 08012df8 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 8012df8: b580 push {r7, lr} 8012dfa: b0ae sub sp, #184 @ 0xb8 8012dfc: af00 add r7, sp, #0 8012dfe: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 8012e00: 687b ldr r3, [r7, #4] 8012e02: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8012e06: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2 uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 8012e0a: 687b ldr r3, [r7, #4] 8012e0c: 681b ldr r3, [r3, #0] 8012e0e: 69db ldr r3, [r3, #28] 8012e10: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8012e14: 687b ldr r3, [r7, #4] 8012e16: 681b ldr r3, [r3, #0] 8012e18: 681b ldr r3, [r3, #0] 8012e1a: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr3its = READ_REG(huart->Instance->CR3); 8012e1e: 687b ldr r3, [r7, #4] 8012e20: 681b ldr r3, [r3, #0] 8012e22: 689b ldr r3, [r3, #8] 8012e24: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8012e28: 687b ldr r3, [r7, #4] 8012e2a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8012e2e: 2b22 cmp r3, #34 @ 0x22 8012e30: f040 8184 bne.w 801313c { nb_rx_data = huart->NbRxDataToProcess; 8012e34: 687b ldr r3, [r7, #4] 8012e36: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8012e3a: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8012e3e: e127 b.n 8013090 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8012e40: 687b ldr r3, [r7, #4] 8012e42: 681b ldr r3, [r3, #0] 8012e44: 6a5b ldr r3, [r3, #36] @ 0x24 8012e46: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4 tmp = (uint16_t *) huart->pRxBuffPtr ; 8012e4a: 687b ldr r3, [r7, #4] 8012e4c: 6d9b ldr r3, [r3, #88] @ 0x58 8012e4e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 *tmp = (uint16_t)(uhdata & uhMask); 8012e52: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4 8012e56: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2 8012e5a: 4013 ands r3, r2 8012e5c: b29a uxth r2, r3 8012e5e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8012e62: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8012e64: 687b ldr r3, [r7, #4] 8012e66: 6d9b ldr r3, [r3, #88] @ 0x58 8012e68: 1c9a adds r2, r3, #2 8012e6a: 687b ldr r3, [r7, #4] 8012e6c: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8012e6e: 687b ldr r3, [r7, #4] 8012e70: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012e74: b29b uxth r3, r3 8012e76: 3b01 subs r3, #1 8012e78: b29a uxth r2, r3 8012e7a: 687b ldr r3, [r7, #4] 8012e7c: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 8012e80: 687b ldr r3, [r7, #4] 8012e82: 681b ldr r3, [r3, #0] 8012e84: 69db ldr r3, [r3, #28] 8012e86: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8012e8a: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8012e8e: f003 0307 and.w r3, r3, #7 8012e92: 2b00 cmp r3, #0 8012e94: d053 beq.n 8012f3e { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8012e96: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8012e9a: f003 0301 and.w r3, r3, #1 8012e9e: 2b00 cmp r3, #0 8012ea0: d011 beq.n 8012ec6 8012ea2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012ea6: f403 7380 and.w r3, r3, #256 @ 0x100 8012eaa: 2b00 cmp r3, #0 8012eac: d00b beq.n 8012ec6 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8012eae: 687b ldr r3, [r7, #4] 8012eb0: 681b ldr r3, [r3, #0] 8012eb2: 2201 movs r2, #1 8012eb4: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8012eb6: 687b ldr r3, [r7, #4] 8012eb8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012ebc: f043 0201 orr.w r2, r3, #1 8012ec0: 687b ldr r3, [r7, #4] 8012ec2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8012ec6: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8012eca: f003 0302 and.w r3, r3, #2 8012ece: 2b00 cmp r3, #0 8012ed0: d011 beq.n 8012ef6 8012ed2: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8012ed6: f003 0301 and.w r3, r3, #1 8012eda: 2b00 cmp r3, #0 8012edc: d00b beq.n 8012ef6 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8012ede: 687b ldr r3, [r7, #4] 8012ee0: 681b ldr r3, [r3, #0] 8012ee2: 2202 movs r2, #2 8012ee4: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8012ee6: 687b ldr r3, [r7, #4] 8012ee8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012eec: f043 0204 orr.w r2, r3, #4 8012ef0: 687b ldr r3, [r7, #4] 8012ef2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8012ef6: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8012efa: f003 0304 and.w r3, r3, #4 8012efe: 2b00 cmp r3, #0 8012f00: d011 beq.n 8012f26 8012f02: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8012f06: f003 0301 and.w r3, r3, #1 8012f0a: 2b00 cmp r3, #0 8012f0c: d00b beq.n 8012f26 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8012f0e: 687b ldr r3, [r7, #4] 8012f10: 681b ldr r3, [r3, #0] 8012f12: 2204 movs r2, #4 8012f14: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8012f16: 687b ldr r3, [r7, #4] 8012f18: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012f1c: f043 0202 orr.w r2, r3, #2 8012f20: 687b ldr r3, [r7, #4] 8012f22: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8012f26: 687b ldr r3, [r7, #4] 8012f28: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012f2c: 2b00 cmp r3, #0 8012f2e: d006 beq.n 8012f3e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8012f30: 6878 ldr r0, [r7, #4] 8012f32: f7fe f961 bl 80111f8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012f36: 687b ldr r3, [r7, #4] 8012f38: 2200 movs r2, #0 8012f3a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 8012f3e: 687b ldr r3, [r7, #4] 8012f40: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012f44: b29b uxth r3, r3 8012f46: 2b00 cmp r3, #0 8012f48: f040 80a2 bne.w 8013090 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8012f4c: 687b ldr r3, [r7, #4] 8012f4e: 681b ldr r3, [r3, #0] 8012f50: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012f52: 6f7b ldr r3, [r7, #116] @ 0x74 8012f54: e853 3f00 ldrex r3, [r3] 8012f58: 673b str r3, [r7, #112] @ 0x70 return(result); 8012f5a: 6f3b ldr r3, [r7, #112] @ 0x70 8012f5c: f423 7380 bic.w r3, r3, #256 @ 0x100 8012f60: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8012f64: 687b ldr r3, [r7, #4] 8012f66: 681b ldr r3, [r3, #0] 8012f68: 461a mov r2, r3 8012f6a: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8012f6e: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8012f72: 67fa str r2, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012f74: 6ff9 ldr r1, [r7, #124] @ 0x7c 8012f76: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8012f7a: e841 2300 strex r3, r2, [r1] 8012f7e: 67bb str r3, [r7, #120] @ 0x78 return(result); 8012f80: 6fbb ldr r3, [r7, #120] @ 0x78 8012f82: 2b00 cmp r3, #0 8012f84: d1e2 bne.n 8012f4c /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8012f86: 687b ldr r3, [r7, #4] 8012f88: 681b ldr r3, [r3, #0] 8012f8a: 3308 adds r3, #8 8012f8c: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012f8e: 6e3b ldr r3, [r7, #96] @ 0x60 8012f90: e853 3f00 ldrex r3, [r3] 8012f94: 65fb str r3, [r7, #92] @ 0x5c return(result); 8012f96: 6dfa ldr r2, [r7, #92] @ 0x5c 8012f98: 4b6e ldr r3, [pc, #440] @ (8013154 ) 8012f9a: 4013 ands r3, r2 8012f9c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8012fa0: 687b ldr r3, [r7, #4] 8012fa2: 681b ldr r3, [r3, #0] 8012fa4: 3308 adds r3, #8 8012fa6: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98 8012faa: 66fa str r2, [r7, #108] @ 0x6c 8012fac: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012fae: 6eb9 ldr r1, [r7, #104] @ 0x68 8012fb0: 6efa ldr r2, [r7, #108] @ 0x6c 8012fb2: e841 2300 strex r3, r2, [r1] 8012fb6: 667b str r3, [r7, #100] @ 0x64 return(result); 8012fb8: 6e7b ldr r3, [r7, #100] @ 0x64 8012fba: 2b00 cmp r3, #0 8012fbc: d1e3 bne.n 8012f86 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012fbe: 687b ldr r3, [r7, #4] 8012fc0: 2220 movs r2, #32 8012fc2: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8012fc6: 687b ldr r3, [r7, #4] 8012fc8: 2200 movs r2, #0 8012fca: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8012fcc: 687b ldr r3, [r7, #4] 8012fce: 2200 movs r2, #0 8012fd0: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8012fd2: 687b ldr r3, [r7, #4] 8012fd4: 681b ldr r3, [r3, #0] 8012fd6: 4a60 ldr r2, [pc, #384] @ (8013158 ) 8012fd8: 4293 cmp r3, r2 8012fda: d021 beq.n 8013020 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8012fdc: 687b ldr r3, [r7, #4] 8012fde: 681b ldr r3, [r3, #0] 8012fe0: 685b ldr r3, [r3, #4] 8012fe2: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8012fe6: 2b00 cmp r3, #0 8012fe8: d01a beq.n 8013020 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8012fea: 687b ldr r3, [r7, #4] 8012fec: 681b ldr r3, [r3, #0] 8012fee: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012ff0: 6cfb ldr r3, [r7, #76] @ 0x4c 8012ff2: e853 3f00 ldrex r3, [r3] 8012ff6: 64bb str r3, [r7, #72] @ 0x48 return(result); 8012ff8: 6cbb ldr r3, [r7, #72] @ 0x48 8012ffa: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8012ffe: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8013002: 687b ldr r3, [r7, #4] 8013004: 681b ldr r3, [r3, #0] 8013006: 461a mov r2, r3 8013008: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 801300c: 65bb str r3, [r7, #88] @ 0x58 801300e: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013010: 6d79 ldr r1, [r7, #84] @ 0x54 8013012: 6dba ldr r2, [r7, #88] @ 0x58 8013014: e841 2300 strex r3, r2, [r1] 8013018: 653b str r3, [r7, #80] @ 0x50 return(result); 801301a: 6d3b ldr r3, [r7, #80] @ 0x50 801301c: 2b00 cmp r3, #0 801301e: d1e4 bne.n 8012fea } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013020: 687b ldr r3, [r7, #4] 8013022: 6edb ldr r3, [r3, #108] @ 0x6c 8013024: 2b01 cmp r3, #1 8013026: d130 bne.n 801308a { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013028: 687b ldr r3, [r7, #4] 801302a: 2200 movs r2, #0 801302c: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801302e: 687b ldr r3, [r7, #4] 8013030: 681b ldr r3, [r3, #0] 8013032: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013034: 6bbb ldr r3, [r7, #56] @ 0x38 8013036: e853 3f00 ldrex r3, [r3] 801303a: 637b str r3, [r7, #52] @ 0x34 return(result); 801303c: 6b7b ldr r3, [r7, #52] @ 0x34 801303e: f023 0310 bic.w r3, r3, #16 8013042: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8013046: 687b ldr r3, [r7, #4] 8013048: 681b ldr r3, [r3, #0] 801304a: 461a mov r2, r3 801304c: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8013050: 647b str r3, [r7, #68] @ 0x44 8013052: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013054: 6c39 ldr r1, [r7, #64] @ 0x40 8013056: 6c7a ldr r2, [r7, #68] @ 0x44 8013058: e841 2300 strex r3, r2, [r1] 801305c: 63fb str r3, [r7, #60] @ 0x3c return(result); 801305e: 6bfb ldr r3, [r7, #60] @ 0x3c 8013060: 2b00 cmp r3, #0 8013062: d1e4 bne.n 801302e if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8013064: 687b ldr r3, [r7, #4] 8013066: 681b ldr r3, [r3, #0] 8013068: 69db ldr r3, [r3, #28] 801306a: f003 0310 and.w r3, r3, #16 801306e: 2b10 cmp r3, #16 8013070: d103 bne.n 801307a { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8013072: 687b ldr r3, [r7, #4] 8013074: 681b ldr r3, [r3, #0] 8013076: 2210 movs r2, #16 8013078: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 801307a: 687b ldr r3, [r7, #4] 801307c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8013080: 4619 mov r1, r3 8013082: 6878 ldr r0, [r7, #4] 8013084: f7f1 faee bl 8004664 8013088: e002 b.n 8013090 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 801308a: 6878 ldr r0, [r7, #4] 801308c: f7f1 fae0 bl 8004650 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8013090: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6 8013094: 2b00 cmp r3, #0 8013096: d006 beq.n 80130a6 8013098: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 801309c: f003 0320 and.w r3, r3, #32 80130a0: 2b00 cmp r3, #0 80130a2: f47f aecd bne.w 8012e40 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 80130a6: 687b ldr r3, [r7, #4] 80130a8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80130ac: f8a7 308e strh.w r3, [r7, #142] @ 0x8e if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 80130b0: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e 80130b4: 2b00 cmp r3, #0 80130b6: d049 beq.n 801314c 80130b8: 687b ldr r3, [r7, #4] 80130ba: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 80130be: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e 80130c2: 429a cmp r2, r3 80130c4: d242 bcs.n 801314c { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 80130c6: 687b ldr r3, [r7, #4] 80130c8: 681b ldr r3, [r3, #0] 80130ca: 3308 adds r3, #8 80130cc: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80130ce: 6a7b ldr r3, [r7, #36] @ 0x24 80130d0: e853 3f00 ldrex r3, [r3] 80130d4: 623b str r3, [r7, #32] return(result); 80130d6: 6a3b ldr r3, [r7, #32] 80130d8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80130dc: f8c7 3088 str.w r3, [r7, #136] @ 0x88 80130e0: 687b ldr r3, [r7, #4] 80130e2: 681b ldr r3, [r3, #0] 80130e4: 3308 adds r3, #8 80130e6: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88 80130ea: 633a str r2, [r7, #48] @ 0x30 80130ec: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80130ee: 6af9 ldr r1, [r7, #44] @ 0x2c 80130f0: 6b3a ldr r2, [r7, #48] @ 0x30 80130f2: e841 2300 strex r3, r2, [r1] 80130f6: 62bb str r3, [r7, #40] @ 0x28 return(result); 80130f8: 6abb ldr r3, [r7, #40] @ 0x28 80130fa: 2b00 cmp r3, #0 80130fc: d1e3 bne.n 80130c6 /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; 80130fe: 687b ldr r3, [r7, #4] 8013100: 4a16 ldr r2, [pc, #88] @ (801315c ) 8013102: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8013104: 687b ldr r3, [r7, #4] 8013106: 681b ldr r3, [r3, #0] 8013108: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801310a: 693b ldr r3, [r7, #16] 801310c: e853 3f00 ldrex r3, [r3] 8013110: 60fb str r3, [r7, #12] return(result); 8013112: 68fb ldr r3, [r7, #12] 8013114: f043 0320 orr.w r3, r3, #32 8013118: f8c7 3084 str.w r3, [r7, #132] @ 0x84 801311c: 687b ldr r3, [r7, #4] 801311e: 681b ldr r3, [r3, #0] 8013120: 461a mov r2, r3 8013122: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8013126: 61fb str r3, [r7, #28] 8013128: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801312a: 69b9 ldr r1, [r7, #24] 801312c: 69fa ldr r2, [r7, #28] 801312e: e841 2300 strex r3, r2, [r1] 8013132: 617b str r3, [r7, #20] return(result); 8013134: 697b ldr r3, [r7, #20] 8013136: 2b00 cmp r3, #0 8013138: d1e4 bne.n 8013104 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 801313a: e007 b.n 801314c __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 801313c: 687b ldr r3, [r7, #4] 801313e: 681b ldr r3, [r3, #0] 8013140: 699a ldr r2, [r3, #24] 8013142: 687b ldr r3, [r7, #4] 8013144: 681b ldr r3, [r3, #0] 8013146: f042 0208 orr.w r2, r2, #8 801314a: 619a str r2, [r3, #24] } 801314c: bf00 nop 801314e: 37b8 adds r7, #184 @ 0xb8 8013150: 46bd mov sp, r7 8013152: bd80 pop {r7, pc} 8013154: effffffe .word 0xeffffffe 8013158: 58000c00 .word 0x58000c00 801315c: 080128e1 .word 0x080128e1 08013160 : * @brief UART wakeup from Stop mode callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { 8013160: b480 push {r7} 8013162: b083 sub sp, #12 8013164: af00 add r7, sp, #0 8013166: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } 8013168: bf00 nop 801316a: 370c adds r7, #12 801316c: 46bd mov sp, r7 801316e: f85d 7b04 ldr.w r7, [sp], #4 8013172: 4770 bx lr 08013174 : * @brief UART RX Fifo full callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { 8013174: b480 push {r7} 8013176: b083 sub sp, #12 8013178: af00 add r7, sp, #0 801317a: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. */ } 801317c: bf00 nop 801317e: 370c adds r7, #12 8013180: 46bd mov sp, r7 8013182: f85d 7b04 ldr.w r7, [sp], #4 8013186: 4770 bx lr 08013188 : * @brief UART TX Fifo empty callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { 8013188: b480 push {r7} 801318a: b083 sub sp, #12 801318c: af00 add r7, sp, #0 801318e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } 8013190: bf00 nop 8013192: 370c adds r7, #12 8013194: 46bd mov sp, r7 8013196: f85d 7b04 ldr.w r7, [sp], #4 801319a: 4770 bx lr 0801319c : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 801319c: b480 push {r7} 801319e: b085 sub sp, #20 80131a0: af00 add r7, sp, #0 80131a2: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 80131a4: 687b ldr r3, [r7, #4] 80131a6: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 80131aa: 2b01 cmp r3, #1 80131ac: d101 bne.n 80131b2 80131ae: 2302 movs r3, #2 80131b0: e027 b.n 8013202 80131b2: 687b ldr r3, [r7, #4] 80131b4: 2201 movs r2, #1 80131b6: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 80131ba: 687b ldr r3, [r7, #4] 80131bc: 2224 movs r2, #36 @ 0x24 80131be: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 80131c2: 687b ldr r3, [r7, #4] 80131c4: 681b ldr r3, [r3, #0] 80131c6: 681b ldr r3, [r3, #0] 80131c8: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 80131ca: 687b ldr r3, [r7, #4] 80131cc: 681b ldr r3, [r3, #0] 80131ce: 681a ldr r2, [r3, #0] 80131d0: 687b ldr r3, [r7, #4] 80131d2: 681b ldr r3, [r3, #0] 80131d4: f022 0201 bic.w r2, r2, #1 80131d8: 601a str r2, [r3, #0] /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 80131da: 68fb ldr r3, [r7, #12] 80131dc: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000 80131e0: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 80131e2: 687b ldr r3, [r7, #4] 80131e4: 2200 movs r2, #0 80131e6: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 80131e8: 687b ldr r3, [r7, #4] 80131ea: 681b ldr r3, [r3, #0] 80131ec: 68fa ldr r2, [r7, #12] 80131ee: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 80131f0: 687b ldr r3, [r7, #4] 80131f2: 2220 movs r2, #32 80131f4: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 80131f8: 687b ldr r3, [r7, #4] 80131fa: 2200 movs r2, #0 80131fc: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8013200: 2300 movs r3, #0 } 8013202: 4618 mov r0, r3 8013204: 3714 adds r7, #20 8013206: 46bd mov sp, r7 8013208: f85d 7b04 ldr.w r7, [sp], #4 801320c: 4770 bx lr 0801320e : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 801320e: b580 push {r7, lr} 8013210: b084 sub sp, #16 8013212: af00 add r7, sp, #0 8013214: 6078 str r0, [r7, #4] 8013216: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8013218: 687b ldr r3, [r7, #4] 801321a: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 801321e: 2b01 cmp r3, #1 8013220: d101 bne.n 8013226 8013222: 2302 movs r3, #2 8013224: e02d b.n 8013282 8013226: 687b ldr r3, [r7, #4] 8013228: 2201 movs r2, #1 801322a: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 801322e: 687b ldr r3, [r7, #4] 8013230: 2224 movs r2, #36 @ 0x24 8013232: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8013236: 687b ldr r3, [r7, #4] 8013238: 681b ldr r3, [r3, #0] 801323a: 681b ldr r3, [r3, #0] 801323c: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 801323e: 687b ldr r3, [r7, #4] 8013240: 681b ldr r3, [r3, #0] 8013242: 681a ldr r2, [r3, #0] 8013244: 687b ldr r3, [r7, #4] 8013246: 681b ldr r3, [r3, #0] 8013248: f022 0201 bic.w r2, r2, #1 801324c: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 801324e: 687b ldr r3, [r7, #4] 8013250: 681b ldr r3, [r3, #0] 8013252: 689b ldr r3, [r3, #8] 8013254: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 8013258: 687b ldr r3, [r7, #4] 801325a: 681b ldr r3, [r3, #0] 801325c: 683a ldr r2, [r7, #0] 801325e: 430a orrs r2, r1 8013260: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8013262: 6878 ldr r0, [r7, #4] 8013264: f000 f8a0 bl 80133a8 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8013268: 687b ldr r3, [r7, #4] 801326a: 681b ldr r3, [r3, #0] 801326c: 68fa ldr r2, [r7, #12] 801326e: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8013270: 687b ldr r3, [r7, #4] 8013272: 2220 movs r2, #32 8013274: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8013278: 687b ldr r3, [r7, #4] 801327a: 2200 movs r2, #0 801327c: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8013280: 2300 movs r3, #0 } 8013282: 4618 mov r0, r3 8013284: 3710 adds r7, #16 8013286: 46bd mov sp, r7 8013288: bd80 pop {r7, pc} 0801328a : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 801328a: b580 push {r7, lr} 801328c: b084 sub sp, #16 801328e: af00 add r7, sp, #0 8013290: 6078 str r0, [r7, #4] 8013292: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8013294: 687b ldr r3, [r7, #4] 8013296: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 801329a: 2b01 cmp r3, #1 801329c: d101 bne.n 80132a2 801329e: 2302 movs r3, #2 80132a0: e02d b.n 80132fe 80132a2: 687b ldr r3, [r7, #4] 80132a4: 2201 movs r2, #1 80132a6: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 80132aa: 687b ldr r3, [r7, #4] 80132ac: 2224 movs r2, #36 @ 0x24 80132ae: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 80132b2: 687b ldr r3, [r7, #4] 80132b4: 681b ldr r3, [r3, #0] 80132b6: 681b ldr r3, [r3, #0] 80132b8: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 80132ba: 687b ldr r3, [r7, #4] 80132bc: 681b ldr r3, [r3, #0] 80132be: 681a ldr r2, [r3, #0] 80132c0: 687b ldr r3, [r7, #4] 80132c2: 681b ldr r3, [r3, #0] 80132c4: f022 0201 bic.w r2, r2, #1 80132c8: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 80132ca: 687b ldr r3, [r7, #4] 80132cc: 681b ldr r3, [r3, #0] 80132ce: 689b ldr r3, [r3, #8] 80132d0: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 80132d4: 687b ldr r3, [r7, #4] 80132d6: 681b ldr r3, [r3, #0] 80132d8: 683a ldr r2, [r7, #0] 80132da: 430a orrs r2, r1 80132dc: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 80132de: 6878 ldr r0, [r7, #4] 80132e0: f000 f862 bl 80133a8 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 80132e4: 687b ldr r3, [r7, #4] 80132e6: 681b ldr r3, [r3, #0] 80132e8: 68fa ldr r2, [r7, #12] 80132ea: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 80132ec: 687b ldr r3, [r7, #4] 80132ee: 2220 movs r2, #32 80132f0: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 80132f4: 687b ldr r3, [r7, #4] 80132f6: 2200 movs r2, #0 80132f8: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 80132fc: 2300 movs r3, #0 } 80132fe: 4618 mov r0, r3 8013300: 3710 adds r7, #16 8013302: 46bd mov sp, r7 8013304: bd80 pop {r7, pc} 08013306 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8013306: b580 push {r7, lr} 8013308: b08c sub sp, #48 @ 0x30 801330a: af00 add r7, sp, #0 801330c: 60f8 str r0, [r7, #12] 801330e: 60b9 str r1, [r7, #8] 8013310: 4613 mov r3, r2 8013312: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status = HAL_OK; 8013314: 2300 movs r3, #0 8013316: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 801331a: 68fb ldr r3, [r7, #12] 801331c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8013320: 2b20 cmp r3, #32 8013322: d13b bne.n 801339c { if ((pData == NULL) || (Size == 0U)) 8013324: 68bb ldr r3, [r7, #8] 8013326: 2b00 cmp r3, #0 8013328: d002 beq.n 8013330 801332a: 88fb ldrh r3, [r7, #6] 801332c: 2b00 cmp r3, #0 801332e: d101 bne.n 8013334 { return HAL_ERROR; 8013330: 2301 movs r3, #1 8013332: e034 b.n 801339e } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8013334: 68fb ldr r3, [r7, #12] 8013336: 2201 movs r2, #1 8013338: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 801333a: 68fb ldr r3, [r7, #12] 801333c: 2200 movs r2, #0 801333e: 671a str r2, [r3, #112] @ 0x70 (void)UART_Start_Receive_IT(huart, pData, Size); 8013340: 88fb ldrh r3, [r7, #6] 8013342: 461a mov r2, r3 8013344: 68b9 ldr r1, [r7, #8] 8013346: 68f8 ldr r0, [r7, #12] 8013348: f7fe fe82 bl 8012050 if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 801334c: 68fb ldr r3, [r7, #12] 801334e: 6edb ldr r3, [r3, #108] @ 0x6c 8013350: 2b01 cmp r3, #1 8013352: d11d bne.n 8013390 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8013354: 68fb ldr r3, [r7, #12] 8013356: 681b ldr r3, [r3, #0] 8013358: 2210 movs r2, #16 801335a: 621a str r2, [r3, #32] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801335c: 68fb ldr r3, [r7, #12] 801335e: 681b ldr r3, [r3, #0] 8013360: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013362: 69bb ldr r3, [r7, #24] 8013364: e853 3f00 ldrex r3, [r3] 8013368: 617b str r3, [r7, #20] return(result); 801336a: 697b ldr r3, [r7, #20] 801336c: f043 0310 orr.w r3, r3, #16 8013370: 62bb str r3, [r7, #40] @ 0x28 8013372: 68fb ldr r3, [r7, #12] 8013374: 681b ldr r3, [r3, #0] 8013376: 461a mov r2, r3 8013378: 6abb ldr r3, [r7, #40] @ 0x28 801337a: 627b str r3, [r7, #36] @ 0x24 801337c: 623a str r2, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801337e: 6a39 ldr r1, [r7, #32] 8013380: 6a7a ldr r2, [r7, #36] @ 0x24 8013382: e841 2300 strex r3, r2, [r1] 8013386: 61fb str r3, [r7, #28] return(result); 8013388: 69fb ldr r3, [r7, #28] 801338a: 2b00 cmp r3, #0 801338c: d1e6 bne.n 801335c 801338e: e002 b.n 8013396 { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8013390: 2301 movs r3, #1 8013392: f887 302f strb.w r3, [r7, #47] @ 0x2f } return status; 8013396: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 801339a: e000 b.n 801339e } else { return HAL_BUSY; 801339c: 2302 movs r3, #2 } } 801339e: 4618 mov r0, r3 80133a0: 3730 adds r7, #48 @ 0x30 80133a2: 46bd mov sp, r7 80133a4: bd80 pop {r7, pc} ... 080133a8 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 80133a8: b480 push {r7} 80133aa: b085 sub sp, #20 80133ac: af00 add r7, sp, #0 80133ae: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 80133b0: 687b ldr r3, [r7, #4] 80133b2: 6e5b ldr r3, [r3, #100] @ 0x64 80133b4: 2b00 cmp r3, #0 80133b6: d108 bne.n 80133ca { huart->NbTxDataToProcess = 1U; 80133b8: 687b ldr r3, [r7, #4] 80133ba: 2201 movs r2, #1 80133bc: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1U; 80133c0: 687b ldr r3, [r7, #4] 80133c2: 2201 movs r2, #1 80133c4: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 80133c8: e031 b.n 801342e rx_fifo_depth = RX_FIFO_DEPTH; 80133ca: 2310 movs r3, #16 80133cc: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 80133ce: 2310 movs r3, #16 80133d0: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 80133d2: 687b ldr r3, [r7, #4] 80133d4: 681b ldr r3, [r3, #0] 80133d6: 689b ldr r3, [r3, #8] 80133d8: 0e5b lsrs r3, r3, #25 80133da: b2db uxtb r3, r3 80133dc: f003 0307 and.w r3, r3, #7 80133e0: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 80133e2: 687b ldr r3, [r7, #4] 80133e4: 681b ldr r3, [r3, #0] 80133e6: 689b ldr r3, [r3, #8] 80133e8: 0f5b lsrs r3, r3, #29 80133ea: b2db uxtb r3, r3 80133ec: f003 0307 and.w r3, r3, #7 80133f0: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 80133f2: 7bbb ldrb r3, [r7, #14] 80133f4: 7b3a ldrb r2, [r7, #12] 80133f6: 4911 ldr r1, [pc, #68] @ (801343c ) 80133f8: 5c8a ldrb r2, [r1, r2] 80133fa: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 80133fe: 7b3a ldrb r2, [r7, #12] 8013400: 490f ldr r1, [pc, #60] @ (8013440 ) 8013402: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8013404: fb93 f3f2 sdiv r3, r3, r2 8013408: b29a uxth r2, r3 801340a: 687b ldr r3, [r7, #4] 801340c: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8013410: 7bfb ldrb r3, [r7, #15] 8013412: 7b7a ldrb r2, [r7, #13] 8013414: 4909 ldr r1, [pc, #36] @ (801343c ) 8013416: 5c8a ldrb r2, [r1, r2] 8013418: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 801341c: 7b7a ldrb r2, [r7, #13] 801341e: 4908 ldr r1, [pc, #32] @ (8013440 ) 8013420: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8013422: fb93 f3f2 sdiv r3, r3, r2 8013426: b29a uxth r2, r3 8013428: 687b ldr r3, [r7, #4] 801342a: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 } 801342e: bf00 nop 8013430: 3714 adds r7, #20 8013432: 46bd mov sp, r7 8013434: f85d 7b04 ldr.w r7, [sp], #4 8013438: 4770 bx lr 801343a: bf00 nop 801343c: 0801a2b8 .word 0x0801a2b8 8013440: 0801a2c0 .word 0x0801a2c0 08013444 <__NVIC_SetPriority>: { 8013444: b480 push {r7} 8013446: b083 sub sp, #12 8013448: af00 add r7, sp, #0 801344a: 4603 mov r3, r0 801344c: 6039 str r1, [r7, #0] 801344e: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8013450: f9b7 3006 ldrsh.w r3, [r7, #6] 8013454: 2b00 cmp r3, #0 8013456: db0a blt.n 801346e <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8013458: 683b ldr r3, [r7, #0] 801345a: b2da uxtb r2, r3 801345c: 490c ldr r1, [pc, #48] @ (8013490 <__NVIC_SetPriority+0x4c>) 801345e: f9b7 3006 ldrsh.w r3, [r7, #6] 8013462: 0112 lsls r2, r2, #4 8013464: b2d2 uxtb r2, r2 8013466: 440b add r3, r1 8013468: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 801346c: e00a b.n 8013484 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 801346e: 683b ldr r3, [r7, #0] 8013470: b2da uxtb r2, r3 8013472: 4908 ldr r1, [pc, #32] @ (8013494 <__NVIC_SetPriority+0x50>) 8013474: 88fb ldrh r3, [r7, #6] 8013476: f003 030f and.w r3, r3, #15 801347a: 3b04 subs r3, #4 801347c: 0112 lsls r2, r2, #4 801347e: b2d2 uxtb r2, r2 8013480: 440b add r3, r1 8013482: 761a strb r2, [r3, #24] } 8013484: bf00 nop 8013486: 370c adds r7, #12 8013488: 46bd mov sp, r7 801348a: f85d 7b04 ldr.w r7, [sp], #4 801348e: 4770 bx lr 8013490: e000e100 .word 0xe000e100 8013494: e000ed00 .word 0xe000ed00 08013498 : /* SysTick handler implementation that also clears overflow flag. */ #if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) void SysTick_Handler (void) { 8013498: b580 push {r7, lr} 801349a: af00 add r7, sp, #0 /* Clear overflow flag */ SysTick->CTRL; 801349c: 4b05 ldr r3, [pc, #20] @ (80134b4 ) 801349e: 681b ldr r3, [r3, #0] if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { 80134a0: f002 fd1e bl 8015ee0 80134a4: 4603 mov r3, r0 80134a6: 2b01 cmp r3, #1 80134a8: d001 beq.n 80134ae /* Call tick handler */ xPortSysTickHandler(); 80134aa: f003 ff2d bl 8017308 } } 80134ae: bf00 nop 80134b0: bd80 pop {r7, pc} 80134b2: bf00 nop 80134b4: e000e010 .word 0xe000e010 080134b8 : #endif /* SysTick */ /* Setup SVC to reset value. */ __STATIC_INLINE void SVC_Setup (void) { 80134b8: b580 push {r7, lr} 80134ba: af00 add r7, sp, #0 #if (__ARM_ARCH_7A__ == 0U) /* Service Call interrupt might be configured before kernel start */ /* and when its priority is lower or equal to BASEPRI, svc intruction */ /* causes a Hard Fault. */ NVIC_SetPriority (SVCall_IRQ_NBR, 0U); 80134bc: 2100 movs r1, #0 80134be: f06f 0004 mvn.w r0, #4 80134c2: f7ff ffbf bl 8013444 <__NVIC_SetPriority> #endif } 80134c6: bf00 nop 80134c8: bd80 pop {r7, pc} ... 080134cc : static uint32_t OS_Tick_GetOverflow (void); /* Get OS Tick interval */ static uint32_t OS_Tick_GetInterval (void); /*---------------------------------------------------------------------------*/ osStatus_t osKernelInitialize (void) { 80134cc: b480 push {r7} 80134ce: b083 sub sp, #12 80134d0: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80134d2: f3ef 8305 mrs r3, IPSR 80134d6: 603b str r3, [r7, #0] return(result); 80134d8: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 80134da: 2b00 cmp r3, #0 80134dc: d003 beq.n 80134e6 stat = osErrorISR; 80134de: f06f 0305 mvn.w r3, #5 80134e2: 607b str r3, [r7, #4] 80134e4: e00c b.n 8013500 } else { if (KernelState == osKernelInactive) { 80134e6: 4b0a ldr r3, [pc, #40] @ (8013510 ) 80134e8: 681b ldr r3, [r3, #0] 80134ea: 2b00 cmp r3, #0 80134ec: d105 bne.n 80134fa EvrFreeRTOSSetup(0U); #endif #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) vPortDefineHeapRegions (configHEAP_5_REGIONS); #endif KernelState = osKernelReady; 80134ee: 4b08 ldr r3, [pc, #32] @ (8013510 ) 80134f0: 2201 movs r2, #1 80134f2: 601a str r2, [r3, #0] stat = osOK; 80134f4: 2300 movs r3, #0 80134f6: 607b str r3, [r7, #4] 80134f8: e002 b.n 8013500 } else { stat = osError; 80134fa: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80134fe: 607b str r3, [r7, #4] } } return (stat); 8013500: 687b ldr r3, [r7, #4] } 8013502: 4618 mov r0, r3 8013504: 370c adds r7, #12 8013506: 46bd mov sp, r7 8013508: f85d 7b04 ldr.w r7, [sp], #4 801350c: 4770 bx lr 801350e: bf00 nop 8013510: 240011c0 .word 0x240011c0 08013514 : } return (state); } osStatus_t osKernelStart (void) { 8013514: b580 push {r7, lr} 8013516: b082 sub sp, #8 8013518: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801351a: f3ef 8305 mrs r3, IPSR 801351e: 603b str r3, [r7, #0] return(result); 8013520: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 8013522: 2b00 cmp r3, #0 8013524: d003 beq.n 801352e stat = osErrorISR; 8013526: f06f 0305 mvn.w r3, #5 801352a: 607b str r3, [r7, #4] 801352c: e010 b.n 8013550 } else { if (KernelState == osKernelReady) { 801352e: 4b0b ldr r3, [pc, #44] @ (801355c ) 8013530: 681b ldr r3, [r3, #0] 8013532: 2b01 cmp r3, #1 8013534: d109 bne.n 801354a /* Ensure SVC priority is at the reset value */ SVC_Setup(); 8013536: f7ff ffbf bl 80134b8 /* Change state to enable IRQ masking check */ KernelState = osKernelRunning; 801353a: 4b08 ldr r3, [pc, #32] @ (801355c ) 801353c: 2202 movs r2, #2 801353e: 601a str r2, [r3, #0] /* Start the kernel scheduler */ vTaskStartScheduler(); 8013540: f002 f824 bl 801558c stat = osOK; 8013544: 2300 movs r3, #0 8013546: 607b str r3, [r7, #4] 8013548: e002 b.n 8013550 } else { stat = osError; 801354a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801354e: 607b str r3, [r7, #4] } } return (stat); 8013550: 687b ldr r3, [r7, #4] } 8013552: 4618 mov r0, r3 8013554: 3708 adds r7, #8 8013556: 46bd mov sp, r7 8013558: bd80 pop {r7, pc} 801355a: bf00 nop 801355c: 240011c0 .word 0x240011c0 08013560 : return (configCPU_CLOCK_HZ); } /*---------------------------------------------------------------------------*/ osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { 8013560: b580 push {r7, lr} 8013562: b08e sub sp, #56 @ 0x38 8013564: af04 add r7, sp, #16 8013566: 60f8 str r0, [r7, #12] 8013568: 60b9 str r1, [r7, #8] 801356a: 607a str r2, [r7, #4] uint32_t stack; TaskHandle_t hTask; UBaseType_t prio; int32_t mem; hTask = NULL; 801356c: 2300 movs r3, #0 801356e: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013570: f3ef 8305 mrs r3, IPSR 8013574: 617b str r3, [r7, #20] return(result); 8013576: 697b ldr r3, [r7, #20] if (!IS_IRQ() && (func != NULL)) { 8013578: 2b00 cmp r3, #0 801357a: d17f bne.n 801367c 801357c: 68fb ldr r3, [r7, #12] 801357e: 2b00 cmp r3, #0 8013580: d07c beq.n 801367c stack = configMINIMAL_STACK_SIZE; 8013582: f44f 7300 mov.w r3, #512 @ 0x200 8013586: 623b str r3, [r7, #32] prio = (UBaseType_t)osPriorityNormal; 8013588: 2318 movs r3, #24 801358a: 61fb str r3, [r7, #28] name = NULL; 801358c: 2300 movs r3, #0 801358e: 627b str r3, [r7, #36] @ 0x24 mem = -1; 8013590: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8013594: 61bb str r3, [r7, #24] if (attr != NULL) { 8013596: 687b ldr r3, [r7, #4] 8013598: 2b00 cmp r3, #0 801359a: d045 beq.n 8013628 if (attr->name != NULL) { 801359c: 687b ldr r3, [r7, #4] 801359e: 681b ldr r3, [r3, #0] 80135a0: 2b00 cmp r3, #0 80135a2: d002 beq.n 80135aa name = attr->name; 80135a4: 687b ldr r3, [r7, #4] 80135a6: 681b ldr r3, [r3, #0] 80135a8: 627b str r3, [r7, #36] @ 0x24 } if (attr->priority != osPriorityNone) { 80135aa: 687b ldr r3, [r7, #4] 80135ac: 699b ldr r3, [r3, #24] 80135ae: 2b00 cmp r3, #0 80135b0: d002 beq.n 80135b8 prio = (UBaseType_t)attr->priority; 80135b2: 687b ldr r3, [r7, #4] 80135b4: 699b ldr r3, [r3, #24] 80135b6: 61fb str r3, [r7, #28] } if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { 80135b8: 69fb ldr r3, [r7, #28] 80135ba: 2b00 cmp r3, #0 80135bc: d008 beq.n 80135d0 80135be: 69fb ldr r3, [r7, #28] 80135c0: 2b38 cmp r3, #56 @ 0x38 80135c2: d805 bhi.n 80135d0 80135c4: 687b ldr r3, [r7, #4] 80135c6: 685b ldr r3, [r3, #4] 80135c8: f003 0301 and.w r3, r3, #1 80135cc: 2b00 cmp r3, #0 80135ce: d001 beq.n 80135d4 return (NULL); 80135d0: 2300 movs r3, #0 80135d2: e054 b.n 801367e } if (attr->stack_size > 0U) { 80135d4: 687b ldr r3, [r7, #4] 80135d6: 695b ldr r3, [r3, #20] 80135d8: 2b00 cmp r3, #0 80135da: d003 beq.n 80135e4 /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ stack = attr->stack_size / sizeof(StackType_t); 80135dc: 687b ldr r3, [r7, #4] 80135de: 695b ldr r3, [r3, #20] 80135e0: 089b lsrs r3, r3, #2 80135e2: 623b str r3, [r7, #32] } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 80135e4: 687b ldr r3, [r7, #4] 80135e6: 689b ldr r3, [r3, #8] 80135e8: 2b00 cmp r3, #0 80135ea: d00e beq.n 801360a 80135ec: 687b ldr r3, [r7, #4] 80135ee: 68db ldr r3, [r3, #12] 80135f0: 2ba7 cmp r3, #167 @ 0xa7 80135f2: d90a bls.n 801360a (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 80135f4: 687b ldr r3, [r7, #4] 80135f6: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 80135f8: 2b00 cmp r3, #0 80135fa: d006 beq.n 801360a (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 80135fc: 687b ldr r3, [r7, #4] 80135fe: 695b ldr r3, [r3, #20] 8013600: 2b00 cmp r3, #0 8013602: d002 beq.n 801360a mem = 1; 8013604: 2301 movs r3, #1 8013606: 61bb str r3, [r7, #24] 8013608: e010 b.n 801362c } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { 801360a: 687b ldr r3, [r7, #4] 801360c: 689b ldr r3, [r3, #8] 801360e: 2b00 cmp r3, #0 8013610: d10c bne.n 801362c 8013612: 687b ldr r3, [r7, #4] 8013614: 68db ldr r3, [r3, #12] 8013616: 2b00 cmp r3, #0 8013618: d108 bne.n 801362c 801361a: 687b ldr r3, [r7, #4] 801361c: 691b ldr r3, [r3, #16] 801361e: 2b00 cmp r3, #0 8013620: d104 bne.n 801362c mem = 0; 8013622: 2300 movs r3, #0 8013624: 61bb str r3, [r7, #24] 8013626: e001 b.n 801362c } } } else { mem = 0; 8013628: 2300 movs r3, #0 801362a: 61bb str r3, [r7, #24] } if (mem == 1) { 801362c: 69bb ldr r3, [r7, #24] 801362e: 2b01 cmp r3, #1 8013630: d110 bne.n 8013654 #if (configSUPPORT_STATIC_ALLOCATION == 1) hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 8013632: 687b ldr r3, [r7, #4] 8013634: 691b ldr r3, [r3, #16] (StaticTask_t *)attr->cb_mem); 8013636: 687a ldr r2, [r7, #4] 8013638: 6892 ldr r2, [r2, #8] hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 801363a: 9202 str r2, [sp, #8] 801363c: 9301 str r3, [sp, #4] 801363e: 69fb ldr r3, [r7, #28] 8013640: 9300 str r3, [sp, #0] 8013642: 68bb ldr r3, [r7, #8] 8013644: 6a3a ldr r2, [r7, #32] 8013646: 6a79 ldr r1, [r7, #36] @ 0x24 8013648: 68f8 ldr r0, [r7, #12] 801364a: f001 fdac bl 80151a6 801364e: 4603 mov r3, r0 8013650: 613b str r3, [r7, #16] 8013652: e013 b.n 801367c #endif } else { if (mem == 0) { 8013654: 69bb ldr r3, [r7, #24] 8013656: 2b00 cmp r3, #0 8013658: d110 bne.n 801367c #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { 801365a: 6a3b ldr r3, [r7, #32] 801365c: b29a uxth r2, r3 801365e: f107 0310 add.w r3, r7, #16 8013662: 9301 str r3, [sp, #4] 8013664: 69fb ldr r3, [r7, #28] 8013666: 9300 str r3, [sp, #0] 8013668: 68bb ldr r3, [r7, #8] 801366a: 6a79 ldr r1, [r7, #36] @ 0x24 801366c: 68f8 ldr r0, [r7, #12] 801366e: f001 fdfa bl 8015266 8013672: 4603 mov r3, r0 8013674: 2b01 cmp r3, #1 8013676: d001 beq.n 801367c hTask = NULL; 8013678: 2300 movs r3, #0 801367a: 613b str r3, [r7, #16] #endif } } } return ((osThreadId_t)hTask); 801367c: 693b ldr r3, [r7, #16] } 801367e: 4618 mov r0, r3 8013680: 3728 adds r7, #40 @ 0x28 8013682: 46bd mov sp, r7 8013684: bd80 pop {r7, pc} 08013686 : /* Return flags before clearing */ return (rflags); } #endif /* (configUSE_OS2_THREAD_FLAGS == 1) */ osStatus_t osDelay (uint32_t ticks) { 8013686: b580 push {r7, lr} 8013688: b084 sub sp, #16 801368a: af00 add r7, sp, #0 801368c: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801368e: f3ef 8305 mrs r3, IPSR 8013692: 60bb str r3, [r7, #8] return(result); 8013694: 68bb ldr r3, [r7, #8] osStatus_t stat; if (IS_IRQ()) { 8013696: 2b00 cmp r3, #0 8013698: d003 beq.n 80136a2 stat = osErrorISR; 801369a: f06f 0305 mvn.w r3, #5 801369e: 60fb str r3, [r7, #12] 80136a0: e007 b.n 80136b2 } else { stat = osOK; 80136a2: 2300 movs r3, #0 80136a4: 60fb str r3, [r7, #12] if (ticks != 0U) { 80136a6: 687b ldr r3, [r7, #4] 80136a8: 2b00 cmp r3, #0 80136aa: d002 beq.n 80136b2 vTaskDelay(ticks); 80136ac: 6878 ldr r0, [r7, #4] 80136ae: f001 ff37 bl 8015520 } } return (stat); 80136b2: 68fb ldr r3, [r7, #12] } 80136b4: 4618 mov r0, r3 80136b6: 3710 adds r7, #16 80136b8: 46bd mov sp, r7 80136ba: bd80 pop {r7, pc} 080136bc : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_TIMER == 1) static void TimerCallback (TimerHandle_t hTimer) { 80136bc: b580 push {r7, lr} 80136be: b084 sub sp, #16 80136c0: af00 add r7, sp, #0 80136c2: 6078 str r0, [r7, #4] TimerCallback_t *callb; callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); 80136c4: 6878 ldr r0, [r7, #4] 80136c6: f003 fc3d bl 8016f44 80136ca: 60f8 str r0, [r7, #12] if (callb != NULL) { 80136cc: 68fb ldr r3, [r7, #12] 80136ce: 2b00 cmp r3, #0 80136d0: d005 beq.n 80136de callb->func (callb->arg); 80136d2: 68fb ldr r3, [r7, #12] 80136d4: 681b ldr r3, [r3, #0] 80136d6: 68fa ldr r2, [r7, #12] 80136d8: 6852 ldr r2, [r2, #4] 80136da: 4610 mov r0, r2 80136dc: 4798 blx r3 } } 80136de: bf00 nop 80136e0: 3710 adds r7, #16 80136e2: 46bd mov sp, r7 80136e4: bd80 pop {r7, pc} ... 080136e8 : osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { 80136e8: b580 push {r7, lr} 80136ea: b08c sub sp, #48 @ 0x30 80136ec: af02 add r7, sp, #8 80136ee: 60f8 str r0, [r7, #12] 80136f0: 607a str r2, [r7, #4] 80136f2: 603b str r3, [r7, #0] 80136f4: 460b mov r3, r1 80136f6: 72fb strb r3, [r7, #11] TimerHandle_t hTimer; TimerCallback_t *callb; UBaseType_t reload; int32_t mem; hTimer = NULL; 80136f8: 2300 movs r3, #0 80136fa: 623b str r3, [r7, #32] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80136fc: f3ef 8305 mrs r3, IPSR 8013700: 613b str r3, [r7, #16] return(result); 8013702: 693b ldr r3, [r7, #16] if (!IS_IRQ() && (func != NULL)) { 8013704: 2b00 cmp r3, #0 8013706: d163 bne.n 80137d0 8013708: 68fb ldr r3, [r7, #12] 801370a: 2b00 cmp r3, #0 801370c: d060 beq.n 80137d0 /* Allocate memory to store callback function and argument */ callb = pvPortMalloc (sizeof(TimerCallback_t)); 801370e: 2008 movs r0, #8 8013710: f003 fe8c bl 801742c 8013714: 6178 str r0, [r7, #20] if (callb != NULL) { 8013716: 697b ldr r3, [r7, #20] 8013718: 2b00 cmp r3, #0 801371a: d059 beq.n 80137d0 callb->func = func; 801371c: 697b ldr r3, [r7, #20] 801371e: 68fa ldr r2, [r7, #12] 8013720: 601a str r2, [r3, #0] callb->arg = argument; 8013722: 697b ldr r3, [r7, #20] 8013724: 687a ldr r2, [r7, #4] 8013726: 605a str r2, [r3, #4] if (type == osTimerOnce) { 8013728: 7afb ldrb r3, [r7, #11] 801372a: 2b00 cmp r3, #0 801372c: d102 bne.n 8013734 reload = pdFALSE; 801372e: 2300 movs r3, #0 8013730: 61fb str r3, [r7, #28] 8013732: e001 b.n 8013738 } else { reload = pdTRUE; 8013734: 2301 movs r3, #1 8013736: 61fb str r3, [r7, #28] } mem = -1; 8013738: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801373c: 61bb str r3, [r7, #24] name = NULL; 801373e: 2300 movs r3, #0 8013740: 627b str r3, [r7, #36] @ 0x24 if (attr != NULL) { 8013742: 683b ldr r3, [r7, #0] 8013744: 2b00 cmp r3, #0 8013746: d01c beq.n 8013782 if (attr->name != NULL) { 8013748: 683b ldr r3, [r7, #0] 801374a: 681b ldr r3, [r3, #0] 801374c: 2b00 cmp r3, #0 801374e: d002 beq.n 8013756 name = attr->name; 8013750: 683b ldr r3, [r7, #0] 8013752: 681b ldr r3, [r3, #0] 8013754: 627b str r3, [r7, #36] @ 0x24 } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) { 8013756: 683b ldr r3, [r7, #0] 8013758: 689b ldr r3, [r3, #8] 801375a: 2b00 cmp r3, #0 801375c: d006 beq.n 801376c 801375e: 683b ldr r3, [r7, #0] 8013760: 68db ldr r3, [r3, #12] 8013762: 2b2b cmp r3, #43 @ 0x2b 8013764: d902 bls.n 801376c mem = 1; 8013766: 2301 movs r3, #1 8013768: 61bb str r3, [r7, #24] 801376a: e00c b.n 8013786 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 801376c: 683b ldr r3, [r7, #0] 801376e: 689b ldr r3, [r3, #8] 8013770: 2b00 cmp r3, #0 8013772: d108 bne.n 8013786 8013774: 683b ldr r3, [r7, #0] 8013776: 68db ldr r3, [r3, #12] 8013778: 2b00 cmp r3, #0 801377a: d104 bne.n 8013786 mem = 0; 801377c: 2300 movs r3, #0 801377e: 61bb str r3, [r7, #24] 8013780: e001 b.n 8013786 } } } else { mem = 0; 8013782: 2300 movs r3, #0 8013784: 61bb str r3, [r7, #24] } if (mem == 1) { 8013786: 69bb ldr r3, [r7, #24] 8013788: 2b01 cmp r3, #1 801378a: d10c bne.n 80137a6 #if (configSUPPORT_STATIC_ALLOCATION == 1) hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem); 801378c: 683b ldr r3, [r7, #0] 801378e: 689b ldr r3, [r3, #8] 8013790: 9301 str r3, [sp, #4] 8013792: 4b12 ldr r3, [pc, #72] @ (80137dc ) 8013794: 9300 str r3, [sp, #0] 8013796: 697b ldr r3, [r7, #20] 8013798: 69fa ldr r2, [r7, #28] 801379a: 2101 movs r1, #1 801379c: 6a78 ldr r0, [r7, #36] @ 0x24 801379e: f003 f81a bl 80167d6 80137a2: 6238 str r0, [r7, #32] 80137a4: e00b b.n 80137be #endif } else { if (mem == 0) { 80137a6: 69bb ldr r3, [r7, #24] 80137a8: 2b00 cmp r3, #0 80137aa: d108 bne.n 80137be #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback); 80137ac: 4b0b ldr r3, [pc, #44] @ (80137dc ) 80137ae: 9300 str r3, [sp, #0] 80137b0: 697b ldr r3, [r7, #20] 80137b2: 69fa ldr r2, [r7, #28] 80137b4: 2101 movs r1, #1 80137b6: 6a78 ldr r0, [r7, #36] @ 0x24 80137b8: f002 ffec bl 8016794 80137bc: 6238 str r0, [r7, #32] #endif } } if ((hTimer == NULL) && (callb != NULL)) { 80137be: 6a3b ldr r3, [r7, #32] 80137c0: 2b00 cmp r3, #0 80137c2: d105 bne.n 80137d0 80137c4: 697b ldr r3, [r7, #20] 80137c6: 2b00 cmp r3, #0 80137c8: d002 beq.n 80137d0 vPortFree (callb); 80137ca: 6978 ldr r0, [r7, #20] 80137cc: f003 fefc bl 80175c8 } } } return ((osTimerId_t)hTimer); 80137d0: 6a3b ldr r3, [r7, #32] } 80137d2: 4618 mov r0, r3 80137d4: 3728 adds r7, #40 @ 0x28 80137d6: 46bd mov sp, r7 80137d8: bd80 pop {r7, pc} 80137da: bf00 nop 80137dc: 080136bd .word 0x080136bd 080137e0 : } return (p); } osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) { 80137e0: b580 push {r7, lr} 80137e2: b088 sub sp, #32 80137e4: af02 add r7, sp, #8 80137e6: 6078 str r0, [r7, #4] 80137e8: 6039 str r1, [r7, #0] TimerHandle_t hTimer = (TimerHandle_t)timer_id; 80137ea: 687b ldr r3, [r7, #4] 80137ec: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80137ee: f3ef 8305 mrs r3, IPSR 80137f2: 60fb str r3, [r7, #12] return(result); 80137f4: 68fb ldr r3, [r7, #12] osStatus_t stat; if (IS_IRQ()) { 80137f6: 2b00 cmp r3, #0 80137f8: d003 beq.n 8013802 stat = osErrorISR; 80137fa: f06f 0305 mvn.w r3, #5 80137fe: 617b str r3, [r7, #20] 8013800: e017 b.n 8013832 } else if (hTimer == NULL) { 8013802: 693b ldr r3, [r7, #16] 8013804: 2b00 cmp r3, #0 8013806: d103 bne.n 8013810 stat = osErrorParameter; 8013808: f06f 0303 mvn.w r3, #3 801380c: 617b str r3, [r7, #20] 801380e: e010 b.n 8013832 } else { if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) { 8013810: 2300 movs r3, #0 8013812: 9300 str r3, [sp, #0] 8013814: 2300 movs r3, #0 8013816: 683a ldr r2, [r7, #0] 8013818: 2104 movs r1, #4 801381a: 6938 ldr r0, [r7, #16] 801381c: f003 f858 bl 80168d0 8013820: 4603 mov r3, r0 8013822: 2b01 cmp r3, #1 8013824: d102 bne.n 801382c stat = osOK; 8013826: 2300 movs r3, #0 8013828: 617b str r3, [r7, #20] 801382a: e002 b.n 8013832 } else { stat = osErrorResource; 801382c: f06f 0302 mvn.w r3, #2 8013830: 617b str r3, [r7, #20] } } return (stat); 8013832: 697b ldr r3, [r7, #20] } 8013834: 4618 mov r0, r3 8013836: 3718 adds r7, #24 8013838: 46bd mov sp, r7 801383a: bd80 pop {r7, pc} 0801383c : osStatus_t osTimerStop (osTimerId_t timer_id) { 801383c: b580 push {r7, lr} 801383e: b088 sub sp, #32 8013840: af02 add r7, sp, #8 8013842: 6078 str r0, [r7, #4] TimerHandle_t hTimer = (TimerHandle_t)timer_id; 8013844: 687b ldr r3, [r7, #4] 8013846: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013848: f3ef 8305 mrs r3, IPSR 801384c: 60fb str r3, [r7, #12] return(result); 801384e: 68fb ldr r3, [r7, #12] osStatus_t stat; if (IS_IRQ()) { 8013850: 2b00 cmp r3, #0 8013852: d003 beq.n 801385c stat = osErrorISR; 8013854: f06f 0305 mvn.w r3, #5 8013858: 617b str r3, [r7, #20] 801385a: e021 b.n 80138a0 } else if (hTimer == NULL) { 801385c: 693b ldr r3, [r7, #16] 801385e: 2b00 cmp r3, #0 8013860: d103 bne.n 801386a stat = osErrorParameter; 8013862: f06f 0303 mvn.w r3, #3 8013866: 617b str r3, [r7, #20] 8013868: e01a b.n 80138a0 } else { if (xTimerIsTimerActive (hTimer) == pdFALSE) { 801386a: 6938 ldr r0, [r7, #16] 801386c: f003 fb40 bl 8016ef0 8013870: 4603 mov r3, r0 8013872: 2b00 cmp r3, #0 8013874: d103 bne.n 801387e stat = osErrorResource; 8013876: f06f 0302 mvn.w r3, #2 801387a: 617b str r3, [r7, #20] 801387c: e010 b.n 80138a0 } else { if (xTimerStop (hTimer, 0) == pdPASS) { 801387e: 2300 movs r3, #0 8013880: 9300 str r3, [sp, #0] 8013882: 2300 movs r3, #0 8013884: 2200 movs r2, #0 8013886: 2103 movs r1, #3 8013888: 6938 ldr r0, [r7, #16] 801388a: f003 f821 bl 80168d0 801388e: 4603 mov r3, r0 8013890: 2b01 cmp r3, #1 8013892: d102 bne.n 801389a stat = osOK; 8013894: 2300 movs r3, #0 8013896: 617b str r3, [r7, #20] 8013898: e002 b.n 80138a0 } else { stat = osError; 801389a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801389e: 617b str r3, [r7, #20] } } } return (stat); 80138a0: 697b ldr r3, [r7, #20] } 80138a2: 4618 mov r0, r3 80138a4: 3718 adds r7, #24 80138a6: 46bd mov sp, r7 80138a8: bd80 pop {r7, pc} 080138aa : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_MUTEX == 1) osMutexId_t osMutexNew (const osMutexAttr_t *attr) { 80138aa: b580 push {r7, lr} 80138ac: b088 sub sp, #32 80138ae: af00 add r7, sp, #0 80138b0: 6078 str r0, [r7, #4] int32_t mem; #if (configQUEUE_REGISTRY_SIZE > 0) const char *name; #endif hMutex = NULL; 80138b2: 2300 movs r3, #0 80138b4: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80138b6: f3ef 8305 mrs r3, IPSR 80138ba: 60bb str r3, [r7, #8] return(result); 80138bc: 68bb ldr r3, [r7, #8] if (!IS_IRQ()) { 80138be: 2b00 cmp r3, #0 80138c0: d174 bne.n 80139ac if (attr != NULL) { 80138c2: 687b ldr r3, [r7, #4] 80138c4: 2b00 cmp r3, #0 80138c6: d003 beq.n 80138d0 type = attr->attr_bits; 80138c8: 687b ldr r3, [r7, #4] 80138ca: 685b ldr r3, [r3, #4] 80138cc: 61bb str r3, [r7, #24] 80138ce: e001 b.n 80138d4 } else { type = 0U; 80138d0: 2300 movs r3, #0 80138d2: 61bb str r3, [r7, #24] } if ((type & osMutexRecursive) == osMutexRecursive) { 80138d4: 69bb ldr r3, [r7, #24] 80138d6: f003 0301 and.w r3, r3, #1 80138da: 2b00 cmp r3, #0 80138dc: d002 beq.n 80138e4 rmtx = 1U; 80138de: 2301 movs r3, #1 80138e0: 617b str r3, [r7, #20] 80138e2: e001 b.n 80138e8 } else { rmtx = 0U; 80138e4: 2300 movs r3, #0 80138e6: 617b str r3, [r7, #20] } if ((type & osMutexRobust) != osMutexRobust) { 80138e8: 69bb ldr r3, [r7, #24] 80138ea: f003 0308 and.w r3, r3, #8 80138ee: 2b00 cmp r3, #0 80138f0: d15c bne.n 80139ac mem = -1; 80138f2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80138f6: 613b str r3, [r7, #16] if (attr != NULL) { 80138f8: 687b ldr r3, [r7, #4] 80138fa: 2b00 cmp r3, #0 80138fc: d015 beq.n 801392a if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { 80138fe: 687b ldr r3, [r7, #4] 8013900: 689b ldr r3, [r3, #8] 8013902: 2b00 cmp r3, #0 8013904: d006 beq.n 8013914 8013906: 687b ldr r3, [r7, #4] 8013908: 68db ldr r3, [r3, #12] 801390a: 2b4f cmp r3, #79 @ 0x4f 801390c: d902 bls.n 8013914 mem = 1; 801390e: 2301 movs r3, #1 8013910: 613b str r3, [r7, #16] 8013912: e00c b.n 801392e } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 8013914: 687b ldr r3, [r7, #4] 8013916: 689b ldr r3, [r3, #8] 8013918: 2b00 cmp r3, #0 801391a: d108 bne.n 801392e 801391c: 687b ldr r3, [r7, #4] 801391e: 68db ldr r3, [r3, #12] 8013920: 2b00 cmp r3, #0 8013922: d104 bne.n 801392e mem = 0; 8013924: 2300 movs r3, #0 8013926: 613b str r3, [r7, #16] 8013928: e001 b.n 801392e } } } else { mem = 0; 801392a: 2300 movs r3, #0 801392c: 613b str r3, [r7, #16] } if (mem == 1) { 801392e: 693b ldr r3, [r7, #16] 8013930: 2b01 cmp r3, #1 8013932: d112 bne.n 801395a #if (configSUPPORT_STATIC_ALLOCATION == 1) if (rmtx != 0U) { 8013934: 697b ldr r3, [r7, #20] 8013936: 2b00 cmp r3, #0 8013938: d007 beq.n 801394a #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem); 801393a: 687b ldr r3, [r7, #4] 801393c: 689b ldr r3, [r3, #8] 801393e: 4619 mov r1, r3 8013940: 2004 movs r0, #4 8013942: f000 fc50 bl 80141e6 8013946: 61f8 str r0, [r7, #28] 8013948: e016 b.n 8013978 #endif } else { hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem); 801394a: 687b ldr r3, [r7, #4] 801394c: 689b ldr r3, [r3, #8] 801394e: 4619 mov r1, r3 8013950: 2001 movs r0, #1 8013952: f000 fc48 bl 80141e6 8013956: 61f8 str r0, [r7, #28] 8013958: e00e b.n 8013978 } #endif } else { if (mem == 0) { 801395a: 693b ldr r3, [r7, #16] 801395c: 2b00 cmp r3, #0 801395e: d10b bne.n 8013978 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (rmtx != 0U) { 8013960: 697b ldr r3, [r7, #20] 8013962: 2b00 cmp r3, #0 8013964: d004 beq.n 8013970 #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutex (); 8013966: 2004 movs r0, #4 8013968: f000 fc25 bl 80141b6 801396c: 61f8 str r0, [r7, #28] 801396e: e003 b.n 8013978 #endif } else { hMutex = xSemaphoreCreateMutex (); 8013970: 2001 movs r0, #1 8013972: f000 fc20 bl 80141b6 8013976: 61f8 str r0, [r7, #28] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hMutex != NULL) { 8013978: 69fb ldr r3, [r7, #28] 801397a: 2b00 cmp r3, #0 801397c: d00c beq.n 8013998 if (attr != NULL) { 801397e: 687b ldr r3, [r7, #4] 8013980: 2b00 cmp r3, #0 8013982: d003 beq.n 801398c name = attr->name; 8013984: 687b ldr r3, [r7, #4] 8013986: 681b ldr r3, [r3, #0] 8013988: 60fb str r3, [r7, #12] 801398a: e001 b.n 8013990 } else { name = NULL; 801398c: 2300 movs r3, #0 801398e: 60fb str r3, [r7, #12] } vQueueAddToRegistry (hMutex, name); 8013990: 68f9 ldr r1, [r7, #12] 8013992: 69f8 ldr r0, [r7, #28] 8013994: f001 f9ea bl 8014d6c } #endif if ((hMutex != NULL) && (rmtx != 0U)) { 8013998: 69fb ldr r3, [r7, #28] 801399a: 2b00 cmp r3, #0 801399c: d006 beq.n 80139ac 801399e: 697b ldr r3, [r7, #20] 80139a0: 2b00 cmp r3, #0 80139a2: d003 beq.n 80139ac hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U); 80139a4: 69fb ldr r3, [r7, #28] 80139a6: f043 0301 orr.w r3, r3, #1 80139aa: 61fb str r3, [r7, #28] } } } return ((osMutexId_t)hMutex); 80139ac: 69fb ldr r3, [r7, #28] } 80139ae: 4618 mov r0, r3 80139b0: 3720 adds r7, #32 80139b2: 46bd mov sp, r7 80139b4: bd80 pop {r7, pc} 080139b6 : osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { 80139b6: b580 push {r7, lr} 80139b8: b086 sub sp, #24 80139ba: af00 add r7, sp, #0 80139bc: 6078 str r0, [r7, #4] 80139be: 6039 str r1, [r7, #0] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 80139c0: 687b ldr r3, [r7, #4] 80139c2: f023 0301 bic.w r3, r3, #1 80139c6: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 80139c8: 687b ldr r3, [r7, #4] 80139ca: f003 0301 and.w r3, r3, #1 80139ce: 60fb str r3, [r7, #12] stat = osOK; 80139d0: 2300 movs r3, #0 80139d2: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80139d4: f3ef 8305 mrs r3, IPSR 80139d8: 60bb str r3, [r7, #8] return(result); 80139da: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 80139dc: 2b00 cmp r3, #0 80139de: d003 beq.n 80139e8 stat = osErrorISR; 80139e0: f06f 0305 mvn.w r3, #5 80139e4: 617b str r3, [r7, #20] 80139e6: e02c b.n 8013a42 } else if (hMutex == NULL) { 80139e8: 693b ldr r3, [r7, #16] 80139ea: 2b00 cmp r3, #0 80139ec: d103 bne.n 80139f6 stat = osErrorParameter; 80139ee: f06f 0303 mvn.w r3, #3 80139f2: 617b str r3, [r7, #20] 80139f4: e025 b.n 8013a42 } else { if (rmtx != 0U) { 80139f6: 68fb ldr r3, [r7, #12] 80139f8: 2b00 cmp r3, #0 80139fa: d011 beq.n 8013a20 #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) { 80139fc: 6839 ldr r1, [r7, #0] 80139fe: 6938 ldr r0, [r7, #16] 8013a00: f000 fc41 bl 8014286 8013a04: 4603 mov r3, r0 8013a06: 2b01 cmp r3, #1 8013a08: d01b beq.n 8013a42 if (timeout != 0U) { 8013a0a: 683b ldr r3, [r7, #0] 8013a0c: 2b00 cmp r3, #0 8013a0e: d003 beq.n 8013a18 stat = osErrorTimeout; 8013a10: f06f 0301 mvn.w r3, #1 8013a14: 617b str r3, [r7, #20] 8013a16: e014 b.n 8013a42 } else { stat = osErrorResource; 8013a18: f06f 0302 mvn.w r3, #2 8013a1c: 617b str r3, [r7, #20] 8013a1e: e010 b.n 8013a42 } } #endif } else { if (xSemaphoreTake (hMutex, timeout) != pdPASS) { 8013a20: 6839 ldr r1, [r7, #0] 8013a22: 6938 ldr r0, [r7, #16] 8013a24: f000 fee8 bl 80147f8 8013a28: 4603 mov r3, r0 8013a2a: 2b01 cmp r3, #1 8013a2c: d009 beq.n 8013a42 if (timeout != 0U) { 8013a2e: 683b ldr r3, [r7, #0] 8013a30: 2b00 cmp r3, #0 8013a32: d003 beq.n 8013a3c stat = osErrorTimeout; 8013a34: f06f 0301 mvn.w r3, #1 8013a38: 617b str r3, [r7, #20] 8013a3a: e002 b.n 8013a42 } else { stat = osErrorResource; 8013a3c: f06f 0302 mvn.w r3, #2 8013a40: 617b str r3, [r7, #20] } } } } return (stat); 8013a42: 697b ldr r3, [r7, #20] } 8013a44: 4618 mov r0, r3 8013a46: 3718 adds r7, #24 8013a48: 46bd mov sp, r7 8013a4a: bd80 pop {r7, pc} 08013a4c : osStatus_t osMutexRelease (osMutexId_t mutex_id) { 8013a4c: b580 push {r7, lr} 8013a4e: b086 sub sp, #24 8013a50: af00 add r7, sp, #0 8013a52: 6078 str r0, [r7, #4] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 8013a54: 687b ldr r3, [r7, #4] 8013a56: f023 0301 bic.w r3, r3, #1 8013a5a: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 8013a5c: 687b ldr r3, [r7, #4] 8013a5e: f003 0301 and.w r3, r3, #1 8013a62: 60fb str r3, [r7, #12] stat = osOK; 8013a64: 2300 movs r3, #0 8013a66: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013a68: f3ef 8305 mrs r3, IPSR 8013a6c: 60bb str r3, [r7, #8] return(result); 8013a6e: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 8013a70: 2b00 cmp r3, #0 8013a72: d003 beq.n 8013a7c stat = osErrorISR; 8013a74: f06f 0305 mvn.w r3, #5 8013a78: 617b str r3, [r7, #20] 8013a7a: e01f b.n 8013abc } else if (hMutex == NULL) { 8013a7c: 693b ldr r3, [r7, #16] 8013a7e: 2b00 cmp r3, #0 8013a80: d103 bne.n 8013a8a stat = osErrorParameter; 8013a82: f06f 0303 mvn.w r3, #3 8013a86: 617b str r3, [r7, #20] 8013a88: e018 b.n 8013abc } else { if (rmtx != 0U) { 8013a8a: 68fb ldr r3, [r7, #12] 8013a8c: 2b00 cmp r3, #0 8013a8e: d009 beq.n 8013aa4 #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreGiveRecursive (hMutex) != pdPASS) { 8013a90: 6938 ldr r0, [r7, #16] 8013a92: f000 fbc3 bl 801421c 8013a96: 4603 mov r3, r0 8013a98: 2b01 cmp r3, #1 8013a9a: d00f beq.n 8013abc stat = osErrorResource; 8013a9c: f06f 0302 mvn.w r3, #2 8013aa0: 617b str r3, [r7, #20] 8013aa2: e00b b.n 8013abc } #endif } else { if (xSemaphoreGive (hMutex) != pdPASS) { 8013aa4: 2300 movs r3, #0 8013aa6: 2200 movs r2, #0 8013aa8: 2100 movs r1, #0 8013aaa: 6938 ldr r0, [r7, #16] 8013aac: f000 fc22 bl 80142f4 8013ab0: 4603 mov r3, r0 8013ab2: 2b01 cmp r3, #1 8013ab4: d002 beq.n 8013abc stat = osErrorResource; 8013ab6: f06f 0302 mvn.w r3, #2 8013aba: 617b str r3, [r7, #20] } } } return (stat); 8013abc: 697b ldr r3, [r7, #20] } 8013abe: 4618 mov r0, r3 8013ac0: 3718 adds r7, #24 8013ac2: 46bd mov sp, r7 8013ac4: bd80 pop {r7, pc} 08013ac6 : return (stat); } /*---------------------------------------------------------------------------*/ osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { 8013ac6: b580 push {r7, lr} 8013ac8: b08a sub sp, #40 @ 0x28 8013aca: af02 add r7, sp, #8 8013acc: 60f8 str r0, [r7, #12] 8013ace: 60b9 str r1, [r7, #8] 8013ad0: 607a str r2, [r7, #4] int32_t mem; #if (configQUEUE_REGISTRY_SIZE > 0) const char *name; #endif hQueue = NULL; 8013ad2: 2300 movs r3, #0 8013ad4: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013ad6: f3ef 8305 mrs r3, IPSR 8013ada: 613b str r3, [r7, #16] return(result); 8013adc: 693b ldr r3, [r7, #16] if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) { 8013ade: 2b00 cmp r3, #0 8013ae0: d15f bne.n 8013ba2 8013ae2: 68fb ldr r3, [r7, #12] 8013ae4: 2b00 cmp r3, #0 8013ae6: d05c beq.n 8013ba2 8013ae8: 68bb ldr r3, [r7, #8] 8013aea: 2b00 cmp r3, #0 8013aec: d059 beq.n 8013ba2 mem = -1; 8013aee: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8013af2: 61bb str r3, [r7, #24] if (attr != NULL) { 8013af4: 687b ldr r3, [r7, #4] 8013af6: 2b00 cmp r3, #0 8013af8: d029 beq.n 8013b4e if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 8013afa: 687b ldr r3, [r7, #4] 8013afc: 689b ldr r3, [r3, #8] 8013afe: 2b00 cmp r3, #0 8013b00: d012 beq.n 8013b28 8013b02: 687b ldr r3, [r7, #4] 8013b04: 68db ldr r3, [r3, #12] 8013b06: 2b4f cmp r3, #79 @ 0x4f 8013b08: d90e bls.n 8013b28 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 8013b0a: 687b ldr r3, [r7, #4] 8013b0c: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 8013b0e: 2b00 cmp r3, #0 8013b10: d00a beq.n 8013b28 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 8013b12: 687b ldr r3, [r7, #4] 8013b14: 695a ldr r2, [r3, #20] 8013b16: 68fb ldr r3, [r7, #12] 8013b18: 68b9 ldr r1, [r7, #8] 8013b1a: fb01 f303 mul.w r3, r1, r3 8013b1e: 429a cmp r2, r3 8013b20: d302 bcc.n 8013b28 mem = 1; 8013b22: 2301 movs r3, #1 8013b24: 61bb str r3, [r7, #24] 8013b26: e014 b.n 8013b52 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 8013b28: 687b ldr r3, [r7, #4] 8013b2a: 689b ldr r3, [r3, #8] 8013b2c: 2b00 cmp r3, #0 8013b2e: d110 bne.n 8013b52 8013b30: 687b ldr r3, [r7, #4] 8013b32: 68db ldr r3, [r3, #12] 8013b34: 2b00 cmp r3, #0 8013b36: d10c bne.n 8013b52 (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 8013b38: 687b ldr r3, [r7, #4] 8013b3a: 691b ldr r3, [r3, #16] if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 8013b3c: 2b00 cmp r3, #0 8013b3e: d108 bne.n 8013b52 (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 8013b40: 687b ldr r3, [r7, #4] 8013b42: 695b ldr r3, [r3, #20] 8013b44: 2b00 cmp r3, #0 8013b46: d104 bne.n 8013b52 mem = 0; 8013b48: 2300 movs r3, #0 8013b4a: 61bb str r3, [r7, #24] 8013b4c: e001 b.n 8013b52 } } } else { mem = 0; 8013b4e: 2300 movs r3, #0 8013b50: 61bb str r3, [r7, #24] } if (mem == 1) { 8013b52: 69bb ldr r3, [r7, #24] 8013b54: 2b01 cmp r3, #1 8013b56: d10b bne.n 8013b70 #if (configSUPPORT_STATIC_ALLOCATION == 1) hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem); 8013b58: 687b ldr r3, [r7, #4] 8013b5a: 691a ldr r2, [r3, #16] 8013b5c: 687b ldr r3, [r7, #4] 8013b5e: 689b ldr r3, [r3, #8] 8013b60: 2100 movs r1, #0 8013b62: 9100 str r1, [sp, #0] 8013b64: 68b9 ldr r1, [r7, #8] 8013b66: 68f8 ldr r0, [r7, #12] 8013b68: f000 fa30 bl 8013fcc 8013b6c: 61f8 str r0, [r7, #28] 8013b6e: e008 b.n 8013b82 #endif } else { if (mem == 0) { 8013b70: 69bb ldr r3, [r7, #24] 8013b72: 2b00 cmp r3, #0 8013b74: d105 bne.n 8013b82 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hQueue = xQueueCreate (msg_count, msg_size); 8013b76: 2200 movs r2, #0 8013b78: 68b9 ldr r1, [r7, #8] 8013b7a: 68f8 ldr r0, [r7, #12] 8013b7c: f000 faa3 bl 80140c6 8013b80: 61f8 str r0, [r7, #28] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hQueue != NULL) { 8013b82: 69fb ldr r3, [r7, #28] 8013b84: 2b00 cmp r3, #0 8013b86: d00c beq.n 8013ba2 if (attr != NULL) { 8013b88: 687b ldr r3, [r7, #4] 8013b8a: 2b00 cmp r3, #0 8013b8c: d003 beq.n 8013b96 name = attr->name; 8013b8e: 687b ldr r3, [r7, #4] 8013b90: 681b ldr r3, [r3, #0] 8013b92: 617b str r3, [r7, #20] 8013b94: e001 b.n 8013b9a } else { name = NULL; 8013b96: 2300 movs r3, #0 8013b98: 617b str r3, [r7, #20] } vQueueAddToRegistry (hQueue, name); 8013b9a: 6979 ldr r1, [r7, #20] 8013b9c: 69f8 ldr r0, [r7, #28] 8013b9e: f001 f8e5 bl 8014d6c } #endif } return ((osMessageQueueId_t)hQueue); 8013ba2: 69fb ldr r3, [r7, #28] } 8013ba4: 4618 mov r0, r3 8013ba6: 3720 adds r7, #32 8013ba8: 46bd mov sp, r7 8013baa: bd80 pop {r7, pc} 08013bac : osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { 8013bac: b580 push {r7, lr} 8013bae: b088 sub sp, #32 8013bb0: af00 add r7, sp, #0 8013bb2: 60f8 str r0, [r7, #12] 8013bb4: 60b9 str r1, [r7, #8] 8013bb6: 603b str r3, [r7, #0] 8013bb8: 4613 mov r3, r2 8013bba: 71fb strb r3, [r7, #7] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 8013bbc: 68fb ldr r3, [r7, #12] 8013bbe: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 8013bc0: 2300 movs r3, #0 8013bc2: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013bc4: f3ef 8305 mrs r3, IPSR 8013bc8: 617b str r3, [r7, #20] return(result); 8013bca: 697b ldr r3, [r7, #20] if (IS_IRQ()) { 8013bcc: 2b00 cmp r3, #0 8013bce: d028 beq.n 8013c22 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 8013bd0: 69bb ldr r3, [r7, #24] 8013bd2: 2b00 cmp r3, #0 8013bd4: d005 beq.n 8013be2 8013bd6: 68bb ldr r3, [r7, #8] 8013bd8: 2b00 cmp r3, #0 8013bda: d002 beq.n 8013be2 8013bdc: 683b ldr r3, [r7, #0] 8013bde: 2b00 cmp r3, #0 8013be0: d003 beq.n 8013bea stat = osErrorParameter; 8013be2: f06f 0303 mvn.w r3, #3 8013be6: 61fb str r3, [r7, #28] 8013be8: e038 b.n 8013c5c } else { yield = pdFALSE; 8013bea: 2300 movs r3, #0 8013bec: 613b str r3, [r7, #16] if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { 8013bee: f107 0210 add.w r2, r7, #16 8013bf2: 2300 movs r3, #0 8013bf4: 68b9 ldr r1, [r7, #8] 8013bf6: 69b8 ldr r0, [r7, #24] 8013bf8: f000 fc7e bl 80144f8 8013bfc: 4603 mov r3, r0 8013bfe: 2b01 cmp r3, #1 8013c00: d003 beq.n 8013c0a stat = osErrorResource; 8013c02: f06f 0302 mvn.w r3, #2 8013c06: 61fb str r3, [r7, #28] 8013c08: e028 b.n 8013c5c } else { portYIELD_FROM_ISR (yield); 8013c0a: 693b ldr r3, [r7, #16] 8013c0c: 2b00 cmp r3, #0 8013c0e: d025 beq.n 8013c5c 8013c10: 4b15 ldr r3, [pc, #84] @ (8013c68 ) 8013c12: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8013c16: 601a str r2, [r3, #0] 8013c18: f3bf 8f4f dsb sy 8013c1c: f3bf 8f6f isb sy 8013c20: e01c b.n 8013c5c } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 8013c22: 69bb ldr r3, [r7, #24] 8013c24: 2b00 cmp r3, #0 8013c26: d002 beq.n 8013c2e 8013c28: 68bb ldr r3, [r7, #8] 8013c2a: 2b00 cmp r3, #0 8013c2c: d103 bne.n 8013c36 stat = osErrorParameter; 8013c2e: f06f 0303 mvn.w r3, #3 8013c32: 61fb str r3, [r7, #28] 8013c34: e012 b.n 8013c5c } else { if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 8013c36: 2300 movs r3, #0 8013c38: 683a ldr r2, [r7, #0] 8013c3a: 68b9 ldr r1, [r7, #8] 8013c3c: 69b8 ldr r0, [r7, #24] 8013c3e: f000 fb59 bl 80142f4 8013c42: 4603 mov r3, r0 8013c44: 2b01 cmp r3, #1 8013c46: d009 beq.n 8013c5c if (timeout != 0U) { 8013c48: 683b ldr r3, [r7, #0] 8013c4a: 2b00 cmp r3, #0 8013c4c: d003 beq.n 8013c56 stat = osErrorTimeout; 8013c4e: f06f 0301 mvn.w r3, #1 8013c52: 61fb str r3, [r7, #28] 8013c54: e002 b.n 8013c5c } else { stat = osErrorResource; 8013c56: f06f 0302 mvn.w r3, #2 8013c5a: 61fb str r3, [r7, #28] } } } } return (stat); 8013c5c: 69fb ldr r3, [r7, #28] } 8013c5e: 4618 mov r0, r3 8013c60: 3720 adds r7, #32 8013c62: 46bd mov sp, r7 8013c64: bd80 pop {r7, pc} 8013c66: bf00 nop 8013c68: e000ed04 .word 0xe000ed04 08013c6c : osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { 8013c6c: b580 push {r7, lr} 8013c6e: b088 sub sp, #32 8013c70: af00 add r7, sp, #0 8013c72: 60f8 str r0, [r7, #12] 8013c74: 60b9 str r1, [r7, #8] 8013c76: 607a str r2, [r7, #4] 8013c78: 603b str r3, [r7, #0] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 8013c7a: 68fb ldr r3, [r7, #12] 8013c7c: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 8013c7e: 2300 movs r3, #0 8013c80: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013c82: f3ef 8305 mrs r3, IPSR 8013c86: 617b str r3, [r7, #20] return(result); 8013c88: 697b ldr r3, [r7, #20] if (IS_IRQ()) { 8013c8a: 2b00 cmp r3, #0 8013c8c: d028 beq.n 8013ce0 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 8013c8e: 69bb ldr r3, [r7, #24] 8013c90: 2b00 cmp r3, #0 8013c92: d005 beq.n 8013ca0 8013c94: 68bb ldr r3, [r7, #8] 8013c96: 2b00 cmp r3, #0 8013c98: d002 beq.n 8013ca0 8013c9a: 683b ldr r3, [r7, #0] 8013c9c: 2b00 cmp r3, #0 8013c9e: d003 beq.n 8013ca8 stat = osErrorParameter; 8013ca0: f06f 0303 mvn.w r3, #3 8013ca4: 61fb str r3, [r7, #28] 8013ca6: e037 b.n 8013d18 } else { yield = pdFALSE; 8013ca8: 2300 movs r3, #0 8013caa: 613b str r3, [r7, #16] if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) { 8013cac: f107 0310 add.w r3, r7, #16 8013cb0: 461a mov r2, r3 8013cb2: 68b9 ldr r1, [r7, #8] 8013cb4: 69b8 ldr r0, [r7, #24] 8013cb6: f000 feaf bl 8014a18 8013cba: 4603 mov r3, r0 8013cbc: 2b01 cmp r3, #1 8013cbe: d003 beq.n 8013cc8 stat = osErrorResource; 8013cc0: f06f 0302 mvn.w r3, #2 8013cc4: 61fb str r3, [r7, #28] 8013cc6: e027 b.n 8013d18 } else { portYIELD_FROM_ISR (yield); 8013cc8: 693b ldr r3, [r7, #16] 8013cca: 2b00 cmp r3, #0 8013ccc: d024 beq.n 8013d18 8013cce: 4b15 ldr r3, [pc, #84] @ (8013d24 ) 8013cd0: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8013cd4: 601a str r2, [r3, #0] 8013cd6: f3bf 8f4f dsb sy 8013cda: f3bf 8f6f isb sy 8013cde: e01b b.n 8013d18 } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 8013ce0: 69bb ldr r3, [r7, #24] 8013ce2: 2b00 cmp r3, #0 8013ce4: d002 beq.n 8013cec 8013ce6: 68bb ldr r3, [r7, #8] 8013ce8: 2b00 cmp r3, #0 8013cea: d103 bne.n 8013cf4 stat = osErrorParameter; 8013cec: f06f 0303 mvn.w r3, #3 8013cf0: 61fb str r3, [r7, #28] 8013cf2: e011 b.n 8013d18 } else { if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 8013cf4: 683a ldr r2, [r7, #0] 8013cf6: 68b9 ldr r1, [r7, #8] 8013cf8: 69b8 ldr r0, [r7, #24] 8013cfa: f000 fc9b bl 8014634 8013cfe: 4603 mov r3, r0 8013d00: 2b01 cmp r3, #1 8013d02: d009 beq.n 8013d18 if (timeout != 0U) { 8013d04: 683b ldr r3, [r7, #0] 8013d06: 2b00 cmp r3, #0 8013d08: d003 beq.n 8013d12 stat = osErrorTimeout; 8013d0a: f06f 0301 mvn.w r3, #1 8013d0e: 61fb str r3, [r7, #28] 8013d10: e002 b.n 8013d18 } else { stat = osErrorResource; 8013d12: f06f 0302 mvn.w r3, #2 8013d16: 61fb str r3, [r7, #28] } } } } return (stat); 8013d18: 69fb ldr r3, [r7, #28] } 8013d1a: 4618 mov r0, r3 8013d1c: 3720 adds r7, #32 8013d1e: 46bd mov sp, r7 8013d20: bd80 pop {r7, pc} 8013d22: bf00 nop 8013d24: e000ed04 .word 0xe000ed04 08013d28 : /* vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { 8013d28: b480 push {r7} 8013d2a: b085 sub sp, #20 8013d2c: af00 add r7, sp, #0 8013d2e: 60f8 str r0, [r7, #12] 8013d30: 60b9 str r1, [r7, #8] 8013d32: 607a str r2, [r7, #4] /* Idle task control block and stack */ static StaticTask_t Idle_TCB; static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; *ppxIdleTaskTCBBuffer = &Idle_TCB; 8013d34: 68fb ldr r3, [r7, #12] 8013d36: 4a07 ldr r2, [pc, #28] @ (8013d54 ) 8013d38: 601a str r2, [r3, #0] *ppxIdleTaskStackBuffer = &Idle_Stack[0]; 8013d3a: 68bb ldr r3, [r7, #8] 8013d3c: 4a06 ldr r2, [pc, #24] @ (8013d58 ) 8013d3e: 601a str r2, [r3, #0] *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; 8013d40: 687b ldr r3, [r7, #4] 8013d42: f44f 7200 mov.w r2, #512 @ 0x200 8013d46: 601a str r2, [r3, #0] } 8013d48: bf00 nop 8013d4a: 3714 adds r7, #20 8013d4c: 46bd mov sp, r7 8013d4e: f85d 7b04 ldr.w r7, [sp], #4 8013d52: 4770 bx lr 8013d54: 240011c4 .word 0x240011c4 8013d58: 2400126c .word 0x2400126c 08013d5c : /* vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { 8013d5c: b480 push {r7} 8013d5e: b085 sub sp, #20 8013d60: af00 add r7, sp, #0 8013d62: 60f8 str r0, [r7, #12] 8013d64: 60b9 str r1, [r7, #8] 8013d66: 607a str r2, [r7, #4] /* Timer task control block and stack */ static StaticTask_t Timer_TCB; static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; *ppxTimerTaskTCBBuffer = &Timer_TCB; 8013d68: 68fb ldr r3, [r7, #12] 8013d6a: 4a07 ldr r2, [pc, #28] @ (8013d88 ) 8013d6c: 601a str r2, [r3, #0] *ppxTimerTaskStackBuffer = &Timer_Stack[0]; 8013d6e: 68bb ldr r3, [r7, #8] 8013d70: 4a06 ldr r2, [pc, #24] @ (8013d8c ) 8013d72: 601a str r2, [r3, #0] *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; 8013d74: 687b ldr r3, [r7, #4] 8013d76: f44f 6280 mov.w r2, #1024 @ 0x400 8013d7a: 601a str r2, [r3, #0] } 8013d7c: bf00 nop 8013d7e: 3714 adds r7, #20 8013d80: 46bd mov sp, r7 8013d82: f85d 7b04 ldr.w r7, [sp], #4 8013d86: 4770 bx lr 8013d88: 24001a6c .word 0x24001a6c 8013d8c: 24001b14 .word 0x24001b14 08013d90 : /*----------------------------------------------------------- * PUBLIC LIST API documented in list.h *----------------------------------------------------------*/ void vListInitialise( List_t * const pxList ) { 8013d90: b480 push {r7} 8013d92: b083 sub sp, #12 8013d94: af00 add r7, sp, #0 8013d96: 6078 str r0, [r7, #4] /* The list structure contains a list item which is used to mark the end of the list. To initialise the list the list end is inserted as the only list entry. */ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8013d98: 687b ldr r3, [r7, #4] 8013d9a: f103 0208 add.w r2, r3, #8 8013d9e: 687b ldr r3, [r7, #4] 8013da0: 605a str r2, [r3, #4] /* The list end value is the highest possible value in the list to ensure it remains at the end of the list. */ pxList->xListEnd.xItemValue = portMAX_DELAY; 8013da2: 687b ldr r3, [r7, #4] 8013da4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8013da8: 609a str r2, [r3, #8] /* The list end next and previous pointers point to itself so we know when the list is empty. */ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8013daa: 687b ldr r3, [r7, #4] 8013dac: f103 0208 add.w r2, r3, #8 8013db0: 687b ldr r3, [r7, #4] 8013db2: 60da str r2, [r3, #12] pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8013db4: 687b ldr r3, [r7, #4] 8013db6: f103 0208 add.w r2, r3, #8 8013dba: 687b ldr r3, [r7, #4] 8013dbc: 611a str r2, [r3, #16] pxList->uxNumberOfItems = ( UBaseType_t ) 0U; 8013dbe: 687b ldr r3, [r7, #4] 8013dc0: 2200 movs r2, #0 8013dc2: 601a str r2, [r3, #0] /* Write known values into the list if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); } 8013dc4: bf00 nop 8013dc6: 370c adds r7, #12 8013dc8: 46bd mov sp, r7 8013dca: f85d 7b04 ldr.w r7, [sp], #4 8013dce: 4770 bx lr 08013dd0 : /*-----------------------------------------------------------*/ void vListInitialiseItem( ListItem_t * const pxItem ) { 8013dd0: b480 push {r7} 8013dd2: b083 sub sp, #12 8013dd4: af00 add r7, sp, #0 8013dd6: 6078 str r0, [r7, #4] /* Make sure the list item is not recorded as being on a list. */ pxItem->pxContainer = NULL; 8013dd8: 687b ldr r3, [r7, #4] 8013dda: 2200 movs r2, #0 8013ddc: 611a str r2, [r3, #16] /* Write known values into the list item if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } 8013dde: bf00 nop 8013de0: 370c adds r7, #12 8013de2: 46bd mov sp, r7 8013de4: f85d 7b04 ldr.w r7, [sp], #4 8013de8: 4770 bx lr 08013dea : /*-----------------------------------------------------------*/ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8013dea: b480 push {r7} 8013dec: b085 sub sp, #20 8013dee: af00 add r7, sp, #0 8013df0: 6078 str r0, [r7, #4] 8013df2: 6039 str r1, [r7, #0] ListItem_t * const pxIndex = pxList->pxIndex; 8013df4: 687b ldr r3, [r7, #4] 8013df6: 685b ldr r3, [r3, #4] 8013df8: 60fb str r3, [r7, #12] listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); /* Insert a new list item into pxList, but rather than sort the list, makes the new list item the last item to be removed by a call to listGET_OWNER_OF_NEXT_ENTRY(). */ pxNewListItem->pxNext = pxIndex; 8013dfa: 683b ldr r3, [r7, #0] 8013dfc: 68fa ldr r2, [r7, #12] 8013dfe: 605a str r2, [r3, #4] pxNewListItem->pxPrevious = pxIndex->pxPrevious; 8013e00: 68fb ldr r3, [r7, #12] 8013e02: 689a ldr r2, [r3, #8] 8013e04: 683b ldr r3, [r7, #0] 8013e06: 609a str r2, [r3, #8] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); pxIndex->pxPrevious->pxNext = pxNewListItem; 8013e08: 68fb ldr r3, [r7, #12] 8013e0a: 689b ldr r3, [r3, #8] 8013e0c: 683a ldr r2, [r7, #0] 8013e0e: 605a str r2, [r3, #4] pxIndex->pxPrevious = pxNewListItem; 8013e10: 68fb ldr r3, [r7, #12] 8013e12: 683a ldr r2, [r7, #0] 8013e14: 609a str r2, [r3, #8] /* Remember which list the item is in. */ pxNewListItem->pxContainer = pxList; 8013e16: 683b ldr r3, [r7, #0] 8013e18: 687a ldr r2, [r7, #4] 8013e1a: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8013e1c: 687b ldr r3, [r7, #4] 8013e1e: 681b ldr r3, [r3, #0] 8013e20: 1c5a adds r2, r3, #1 8013e22: 687b ldr r3, [r7, #4] 8013e24: 601a str r2, [r3, #0] } 8013e26: bf00 nop 8013e28: 3714 adds r7, #20 8013e2a: 46bd mov sp, r7 8013e2c: f85d 7b04 ldr.w r7, [sp], #4 8013e30: 4770 bx lr 08013e32 : /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8013e32: b480 push {r7} 8013e34: b085 sub sp, #20 8013e36: af00 add r7, sp, #0 8013e38: 6078 str r0, [r7, #4] 8013e3a: 6039 str r1, [r7, #0] ListItem_t *pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; 8013e3c: 683b ldr r3, [r7, #0] 8013e3e: 681b ldr r3, [r3, #0] 8013e40: 60bb str r3, [r7, #8] new list item should be placed after it. This ensures that TCBs which are stored in ready lists (all of which have the same xItemValue value) get a share of the CPU. However, if the xItemValue is the same as the back marker the iteration loop below will not end. Therefore the value is checked first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) 8013e42: 68bb ldr r3, [r7, #8] 8013e44: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8013e48: d103 bne.n 8013e52 { pxIterator = pxList->xListEnd.pxPrevious; 8013e4a: 687b ldr r3, [r7, #4] 8013e4c: 691b ldr r3, [r3, #16] 8013e4e: 60fb str r3, [r7, #12] 8013e50: e00c b.n 8013e6c 4) Using a queue or semaphore before it has been initialised or before the scheduler has been started (are interrupts firing before vTaskStartScheduler() has been called?). **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ 8013e52: 687b ldr r3, [r7, #4] 8013e54: 3308 adds r3, #8 8013e56: 60fb str r3, [r7, #12] 8013e58: e002 b.n 8013e60 8013e5a: 68fb ldr r3, [r7, #12] 8013e5c: 685b ldr r3, [r3, #4] 8013e5e: 60fb str r3, [r7, #12] 8013e60: 68fb ldr r3, [r7, #12] 8013e62: 685b ldr r3, [r3, #4] 8013e64: 681b ldr r3, [r3, #0] 8013e66: 68ba ldr r2, [r7, #8] 8013e68: 429a cmp r2, r3 8013e6a: d2f6 bcs.n 8013e5a /* There is nothing to do here, just iterating to the wanted insertion position. */ } } pxNewListItem->pxNext = pxIterator->pxNext; 8013e6c: 68fb ldr r3, [r7, #12] 8013e6e: 685a ldr r2, [r3, #4] 8013e70: 683b ldr r3, [r7, #0] 8013e72: 605a str r2, [r3, #4] pxNewListItem->pxNext->pxPrevious = pxNewListItem; 8013e74: 683b ldr r3, [r7, #0] 8013e76: 685b ldr r3, [r3, #4] 8013e78: 683a ldr r2, [r7, #0] 8013e7a: 609a str r2, [r3, #8] pxNewListItem->pxPrevious = pxIterator; 8013e7c: 683b ldr r3, [r7, #0] 8013e7e: 68fa ldr r2, [r7, #12] 8013e80: 609a str r2, [r3, #8] pxIterator->pxNext = pxNewListItem; 8013e82: 68fb ldr r3, [r7, #12] 8013e84: 683a ldr r2, [r7, #0] 8013e86: 605a str r2, [r3, #4] /* Remember which list the item is in. This allows fast removal of the item later. */ pxNewListItem->pxContainer = pxList; 8013e88: 683b ldr r3, [r7, #0] 8013e8a: 687a ldr r2, [r7, #4] 8013e8c: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8013e8e: 687b ldr r3, [r7, #4] 8013e90: 681b ldr r3, [r3, #0] 8013e92: 1c5a adds r2, r3, #1 8013e94: 687b ldr r3, [r7, #4] 8013e96: 601a str r2, [r3, #0] } 8013e98: bf00 nop 8013e9a: 3714 adds r7, #20 8013e9c: 46bd mov sp, r7 8013e9e: f85d 7b04 ldr.w r7, [sp], #4 8013ea2: 4770 bx lr 08013ea4 : /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { 8013ea4: b480 push {r7} 8013ea6: b085 sub sp, #20 8013ea8: af00 add r7, sp, #0 8013eaa: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list item. */ List_t * const pxList = pxItemToRemove->pxContainer; 8013eac: 687b ldr r3, [r7, #4] 8013eae: 691b ldr r3, [r3, #16] 8013eb0: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 8013eb2: 687b ldr r3, [r7, #4] 8013eb4: 685b ldr r3, [r3, #4] 8013eb6: 687a ldr r2, [r7, #4] 8013eb8: 6892 ldr r2, [r2, #8] 8013eba: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; 8013ebc: 687b ldr r3, [r7, #4] 8013ebe: 689b ldr r3, [r3, #8] 8013ec0: 687a ldr r2, [r7, #4] 8013ec2: 6852 ldr r2, [r2, #4] 8013ec4: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) 8013ec6: 68fb ldr r3, [r7, #12] 8013ec8: 685b ldr r3, [r3, #4] 8013eca: 687a ldr r2, [r7, #4] 8013ecc: 429a cmp r2, r3 8013ece: d103 bne.n 8013ed8 { pxList->pxIndex = pxItemToRemove->pxPrevious; 8013ed0: 687b ldr r3, [r7, #4] 8013ed2: 689a ldr r2, [r3, #8] 8013ed4: 68fb ldr r3, [r7, #12] 8013ed6: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; 8013ed8: 687b ldr r3, [r7, #4] 8013eda: 2200 movs r2, #0 8013edc: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; 8013ede: 68fb ldr r3, [r7, #12] 8013ee0: 681b ldr r3, [r3, #0] 8013ee2: 1e5a subs r2, r3, #1 8013ee4: 68fb ldr r3, [r7, #12] 8013ee6: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; 8013ee8: 68fb ldr r3, [r7, #12] 8013eea: 681b ldr r3, [r3, #0] } 8013eec: 4618 mov r0, r3 8013eee: 3714 adds r7, #20 8013ef0: 46bd mov sp, r7 8013ef2: f85d 7b04 ldr.w r7, [sp], #4 8013ef6: 4770 bx lr 08013ef8 : } \ taskEXIT_CRITICAL() /*-----------------------------------------------------------*/ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) { 8013ef8: b580 push {r7, lr} 8013efa: b084 sub sp, #16 8013efc: af00 add r7, sp, #0 8013efe: 6078 str r0, [r7, #4] 8013f00: 6039 str r1, [r7, #0] Queue_t * const pxQueue = xQueue; 8013f02: 687b ldr r3, [r7, #4] 8013f04: 60fb str r3, [r7, #12] configASSERT( pxQueue ); 8013f06: 68fb ldr r3, [r7, #12] 8013f08: 2b00 cmp r3, #0 8013f0a: d10b bne.n 8013f24 portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile 8013f0c: f04f 0350 mov.w r3, #80 @ 0x50 8013f10: f383 8811 msr BASEPRI, r3 8013f14: f3bf 8f6f isb sy 8013f18: f3bf 8f4f dsb sy 8013f1c: 60bb str r3, [r7, #8] " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } 8013f1e: bf00 nop 8013f20: bf00 nop 8013f22: e7fd b.n 8013f20 taskENTER_CRITICAL(); 8013f24: f003 f960 bl 80171e8 { pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8013f28: 68fb ldr r3, [r7, #12] 8013f2a: 681a ldr r2, [r3, #0] 8013f2c: 68fb ldr r3, [r7, #12] 8013f2e: 6bdb ldr r3, [r3, #60] @ 0x3c 8013f30: 68f9 ldr r1, [r7, #12] 8013f32: 6c09 ldr r1, [r1, #64] @ 0x40 8013f34: fb01 f303 mul.w r3, r1, r3 8013f38: 441a add r2, r3 8013f3a: 68fb ldr r3, [r7, #12] 8013f3c: 609a str r2, [r3, #8] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 8013f3e: 68fb ldr r3, [r7, #12] 8013f40: 2200 movs r2, #0 8013f42: 639a str r2, [r3, #56] @ 0x38 pxQueue->pcWriteTo = pxQueue->pcHead; 8013f44: 68fb ldr r3, [r7, #12] 8013f46: 681a ldr r2, [r3, #0] 8013f48: 68fb ldr r3, [r7, #12] 8013f4a: 605a str r2, [r3, #4] pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8013f4c: 68fb ldr r3, [r7, #12] 8013f4e: 681a ldr r2, [r3, #0] 8013f50: 68fb ldr r3, [r7, #12] 8013f52: 6bdb ldr r3, [r3, #60] @ 0x3c 8013f54: 3b01 subs r3, #1 8013f56: 68f9 ldr r1, [r7, #12] 8013f58: 6c09 ldr r1, [r1, #64] @ 0x40 8013f5a: fb01 f303 mul.w r3, r1, r3 8013f5e: 441a add r2, r3 8013f60: 68fb ldr r3, [r7, #12] 8013f62: 60da str r2, [r3, #12] pxQueue->cRxLock = queueUNLOCKED; 8013f64: 68fb ldr r3, [r7, #12] 8013f66: 22ff movs r2, #255 @ 0xff 8013f68: f883 2044 strb.w r2, [r3, #68] @ 0x44 pxQueue->cTxLock = queueUNLOCKED; 8013f6c: 68fb ldr r3, [r7, #12] 8013f6e: 22ff movs r2, #255 @ 0xff 8013f70: f883 2045 strb.w r2, [r3, #69] @ 0x45 if( xNewQueue == pdFALSE ) 8013f74: 683b ldr r3, [r7, #0] 8013f76: 2b00 cmp r3, #0 8013f78: d114 bne.n 8013fa4 /* If there are tasks blocked waiting to read from the queue, then the tasks will remain blocked as after this function exits the queue will still be empty. If there are tasks blocked waiting to write to the queue, then one should be unblocked as after this function exits it will be possible to write to it. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8013f7a: 68fb ldr r3, [r7, #12] 8013f7c: 691b ldr r3, [r3, #16] 8013f7e: 2b00 cmp r3, #0 8013f80: d01a beq.n 8013fb8 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8013f82: 68fb ldr r3, [r7, #12] 8013f84: 3310 adds r3, #16 8013f86: 4618 mov r0, r3 8013f88: f001 fdac bl 8015ae4 8013f8c: 4603 mov r3, r0 8013f8e: 2b00 cmp r3, #0 8013f90: d012 beq.n 8013fb8 { queueYIELD_IF_USING_PREEMPTION(); 8013f92: 4b0d ldr r3, [pc, #52] @ (8013fc8 ) 8013f94: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8013f98: 601a str r2, [r3, #0] 8013f9a: f3bf 8f4f dsb sy 8013f9e: f3bf 8f6f isb sy 8013fa2: e009 b.n 8013fb8 } } else { /* Ensure the event queues start in the correct state. */ vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 8013fa4: 68fb ldr r3, [r7, #12] 8013fa6: 3310 adds r3, #16 8013fa8: 4618 mov r0, r3 8013faa: f7ff fef1 bl 8013d90 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); 8013fae: 68fb ldr r3, [r7, #12] 8013fb0: 3324 adds r3, #36 @ 0x24 8013fb2: 4618 mov r0, r3 8013fb4: f7ff feec bl 8013d90 } } taskEXIT_CRITICAL(); 8013fb8: f003 f948 bl 801724c /* A value is returned for calling semantic consistency with previous versions. */ return pdPASS; 8013fbc: 2301 movs r3, #1 } 8013fbe: 4618 mov r0, r3 8013fc0: 3710 adds r7, #16 8013fc2: 46bd mov sp, r7 8013fc4: bd80 pop {r7, pc} 8013fc6: bf00 nop 8013fc8: e000ed04 .word 0xe000ed04 08013fcc : /*-----------------------------------------------------------*/ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) { 8013fcc: b580 push {r7, lr} 8013fce: b08e sub sp, #56 @ 0x38 8013fd0: af02 add r7, sp, #8 8013fd2: 60f8 str r0, [r7, #12] 8013fd4: 60b9 str r1, [r7, #8] 8013fd6: 607a str r2, [r7, #4] 8013fd8: 603b str r3, [r7, #0] Queue_t *pxNewQueue; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 8013fda: 68fb ldr r3, [r7, #12] 8013fdc: 2b00 cmp r3, #0 8013fde: d10b bne.n 8013ff8 __asm volatile 8013fe0: f04f 0350 mov.w r3, #80 @ 0x50 8013fe4: f383 8811 msr BASEPRI, r3 8013fe8: f3bf 8f6f isb sy 8013fec: f3bf 8f4f dsb sy 8013ff0: 62bb str r3, [r7, #40] @ 0x28 } 8013ff2: bf00 nop 8013ff4: bf00 nop 8013ff6: e7fd b.n 8013ff4 /* The StaticQueue_t structure and the queue storage area must be supplied. */ configASSERT( pxStaticQueue != NULL ); 8013ff8: 683b ldr r3, [r7, #0] 8013ffa: 2b00 cmp r3, #0 8013ffc: d10b bne.n 8014016 __asm volatile 8013ffe: f04f 0350 mov.w r3, #80 @ 0x50 8014002: f383 8811 msr BASEPRI, r3 8014006: f3bf 8f6f isb sy 801400a: f3bf 8f4f dsb sy 801400e: 627b str r3, [r7, #36] @ 0x24 } 8014010: bf00 nop 8014012: bf00 nop 8014014: e7fd b.n 8014012 /* A queue storage area should be provided if the item size is not 0, and should not be provided if the item size is 0. */ configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); 8014016: 687b ldr r3, [r7, #4] 8014018: 2b00 cmp r3, #0 801401a: d002 beq.n 8014022 801401c: 68bb ldr r3, [r7, #8] 801401e: 2b00 cmp r3, #0 8014020: d001 beq.n 8014026 8014022: 2301 movs r3, #1 8014024: e000 b.n 8014028 8014026: 2300 movs r3, #0 8014028: 2b00 cmp r3, #0 801402a: d10b bne.n 8014044 __asm volatile 801402c: f04f 0350 mov.w r3, #80 @ 0x50 8014030: f383 8811 msr BASEPRI, r3 8014034: f3bf 8f6f isb sy 8014038: f3bf 8f4f dsb sy 801403c: 623b str r3, [r7, #32] } 801403e: bf00 nop 8014040: bf00 nop 8014042: e7fd b.n 8014040 configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); 8014044: 687b ldr r3, [r7, #4] 8014046: 2b00 cmp r3, #0 8014048: d102 bne.n 8014050 801404a: 68bb ldr r3, [r7, #8] 801404c: 2b00 cmp r3, #0 801404e: d101 bne.n 8014054 8014050: 2301 movs r3, #1 8014052: e000 b.n 8014056 8014054: 2300 movs r3, #0 8014056: 2b00 cmp r3, #0 8014058: d10b bne.n 8014072 __asm volatile 801405a: f04f 0350 mov.w r3, #80 @ 0x50 801405e: f383 8811 msr BASEPRI, r3 8014062: f3bf 8f6f isb sy 8014066: f3bf 8f4f dsb sy 801406a: 61fb str r3, [r7, #28] } 801406c: bf00 nop 801406e: bf00 nop 8014070: e7fd b.n 801406e #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticQueue_t or StaticSemaphore_t equals the size of the real queue and semaphore structures. */ volatile size_t xSize = sizeof( StaticQueue_t ); 8014072: 2350 movs r3, #80 @ 0x50 8014074: 617b str r3, [r7, #20] configASSERT( xSize == sizeof( Queue_t ) ); 8014076: 697b ldr r3, [r7, #20] 8014078: 2b50 cmp r3, #80 @ 0x50 801407a: d00b beq.n 8014094 __asm volatile 801407c: f04f 0350 mov.w r3, #80 @ 0x50 8014080: f383 8811 msr BASEPRI, r3 8014084: f3bf 8f6f isb sy 8014088: f3bf 8f4f dsb sy 801408c: 61bb str r3, [r7, #24] } 801408e: bf00 nop 8014090: bf00 nop 8014092: e7fd b.n 8014090 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 8014094: 697b ldr r3, [r7, #20] #endif /* configASSERT_DEFINED */ /* The address of a statically allocated queue was passed in, use it. The address of a statically allocated storage area was also passed in but is already set. */ pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8014096: 683b ldr r3, [r7, #0] 8014098: 62fb str r3, [r7, #44] @ 0x2c if( pxNewQueue != NULL ) 801409a: 6afb ldr r3, [r7, #44] @ 0x2c 801409c: 2b00 cmp r3, #0 801409e: d00d beq.n 80140bc #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* Queues can be allocated wither statically or dynamically, so note this queue was allocated statically in case the queue is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdTRUE; 80140a0: 6afb ldr r3, [r7, #44] @ 0x2c 80140a2: 2201 movs r2, #1 80140a4: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 80140a8: f897 2038 ldrb.w r2, [r7, #56] @ 0x38 80140ac: 6afb ldr r3, [r7, #44] @ 0x2c 80140ae: 9300 str r3, [sp, #0] 80140b0: 4613 mov r3, r2 80140b2: 687a ldr r2, [r7, #4] 80140b4: 68b9 ldr r1, [r7, #8] 80140b6: 68f8 ldr r0, [r7, #12] 80140b8: f000 f840 bl 801413c { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 80140bc: 6afb ldr r3, [r7, #44] @ 0x2c } 80140be: 4618 mov r0, r3 80140c0: 3730 adds r7, #48 @ 0x30 80140c2: 46bd mov sp, r7 80140c4: bd80 pop {r7, pc} 080140c6 : /*-----------------------------------------------------------*/ #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) { 80140c6: b580 push {r7, lr} 80140c8: b08a sub sp, #40 @ 0x28 80140ca: af02 add r7, sp, #8 80140cc: 60f8 str r0, [r7, #12] 80140ce: 60b9 str r1, [r7, #8] 80140d0: 4613 mov r3, r2 80140d2: 71fb strb r3, [r7, #7] Queue_t *pxNewQueue; size_t xQueueSizeInBytes; uint8_t *pucQueueStorage; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 80140d4: 68fb ldr r3, [r7, #12] 80140d6: 2b00 cmp r3, #0 80140d8: d10b bne.n 80140f2 __asm volatile 80140da: f04f 0350 mov.w r3, #80 @ 0x50 80140de: f383 8811 msr BASEPRI, r3 80140e2: f3bf 8f6f isb sy 80140e6: f3bf 8f4f dsb sy 80140ea: 613b str r3, [r7, #16] } 80140ec: bf00 nop 80140ee: bf00 nop 80140f0: e7fd b.n 80140ee /* Allocate enough space to hold the maximum number of items that can be in the queue at any time. It is valid for uxItemSize to be zero in the case the queue is used as a semaphore. */ xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 80140f2: 68fb ldr r3, [r7, #12] 80140f4: 68ba ldr r2, [r7, #8] 80140f6: fb02 f303 mul.w r3, r2, r3 80140fa: 61fb str r3, [r7, #28] alignment requirements of the Queue_t structure - which in this case is an int8_t *. Therefore, whenever the stack alignment requirements are greater than or equal to the pointer to char requirements the cast is safe. In other cases alignment requirements are not strict (one or two bytes). */ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ 80140fc: 69fb ldr r3, [r7, #28] 80140fe: 3350 adds r3, #80 @ 0x50 8014100: 4618 mov r0, r3 8014102: f003 f993 bl 801742c 8014106: 61b8 str r0, [r7, #24] if( pxNewQueue != NULL ) 8014108: 69bb ldr r3, [r7, #24] 801410a: 2b00 cmp r3, #0 801410c: d011 beq.n 8014132 { /* Jump past the queue structure to find the location of the queue storage area. */ pucQueueStorage = ( uint8_t * ) pxNewQueue; 801410e: 69bb ldr r3, [r7, #24] 8014110: 617b str r3, [r7, #20] pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8014112: 697b ldr r3, [r7, #20] 8014114: 3350 adds r3, #80 @ 0x50 8014116: 617b str r3, [r7, #20] #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { /* Queues can be created either statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdFALSE; 8014118: 69bb ldr r3, [r7, #24] 801411a: 2200 movs r2, #0 801411c: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_STATIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8014120: 79fa ldrb r2, [r7, #7] 8014122: 69bb ldr r3, [r7, #24] 8014124: 9300 str r3, [sp, #0] 8014126: 4613 mov r3, r2 8014128: 697a ldr r2, [r7, #20] 801412a: 68b9 ldr r1, [r7, #8] 801412c: 68f8 ldr r0, [r7, #12] 801412e: f000 f805 bl 801413c { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 8014132: 69bb ldr r3, [r7, #24] } 8014134: 4618 mov r0, r3 8014136: 3720 adds r7, #32 8014138: 46bd mov sp, r7 801413a: bd80 pop {r7, pc} 0801413c : #endif /* configSUPPORT_STATIC_ALLOCATION */ /*-----------------------------------------------------------*/ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) { 801413c: b580 push {r7, lr} 801413e: b084 sub sp, #16 8014140: af00 add r7, sp, #0 8014142: 60f8 str r0, [r7, #12] 8014144: 60b9 str r1, [r7, #8] 8014146: 607a str r2, [r7, #4] 8014148: 70fb strb r3, [r7, #3] /* Remove compiler warnings about unused parameters should configUSE_TRACE_FACILITY not be set to 1. */ ( void ) ucQueueType; if( uxItemSize == ( UBaseType_t ) 0 ) 801414a: 68bb ldr r3, [r7, #8] 801414c: 2b00 cmp r3, #0 801414e: d103 bne.n 8014158 { /* No RAM was allocated for the queue storage area, but PC head cannot be set to NULL because NULL is used as a key to say the queue is used as a mutex. Therefore just set pcHead to point to the queue as a benign value that is known to be within the memory map. */ pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; 8014150: 69bb ldr r3, [r7, #24] 8014152: 69ba ldr r2, [r7, #24] 8014154: 601a str r2, [r3, #0] 8014156: e002 b.n 801415e } else { /* Set the head to the start of the queue storage area. */ pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; 8014158: 69bb ldr r3, [r7, #24] 801415a: 687a ldr r2, [r7, #4] 801415c: 601a str r2, [r3, #0] } /* Initialise the queue members as described where the queue type is defined. */ pxNewQueue->uxLength = uxQueueLength; 801415e: 69bb ldr r3, [r7, #24] 8014160: 68fa ldr r2, [r7, #12] 8014162: 63da str r2, [r3, #60] @ 0x3c pxNewQueue->uxItemSize = uxItemSize; 8014164: 69bb ldr r3, [r7, #24] 8014166: 68ba ldr r2, [r7, #8] 8014168: 641a str r2, [r3, #64] @ 0x40 ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); 801416a: 2101 movs r1, #1 801416c: 69b8 ldr r0, [r7, #24] 801416e: f7ff fec3 bl 8013ef8 #if ( configUSE_TRACE_FACILITY == 1 ) { pxNewQueue->ucQueueType = ucQueueType; 8014172: 69bb ldr r3, [r7, #24] 8014174: 78fa ldrb r2, [r7, #3] 8014176: f883 204c strb.w r2, [r3, #76] @ 0x4c pxNewQueue->pxQueueSetContainer = NULL; } #endif /* configUSE_QUEUE_SETS */ traceQUEUE_CREATE( pxNewQueue ); } 801417a: bf00 nop 801417c: 3710 adds r7, #16 801417e: 46bd mov sp, r7 8014180: bd80 pop {r7, pc} 08014182 : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static void prvInitialiseMutex( Queue_t *pxNewQueue ) { 8014182: b580 push {r7, lr} 8014184: b082 sub sp, #8 8014186: af00 add r7, sp, #0 8014188: 6078 str r0, [r7, #4] if( pxNewQueue != NULL ) 801418a: 687b ldr r3, [r7, #4] 801418c: 2b00 cmp r3, #0 801418e: d00e beq.n 80141ae { /* The queue create function will set all the queue structure members correctly for a generic queue, but this function is creating a mutex. Overwrite those members that need to be set differently - in particular the information required for priority inheritance. */ pxNewQueue->u.xSemaphore.xMutexHolder = NULL; 8014190: 687b ldr r3, [r7, #4] 8014192: 2200 movs r2, #0 8014194: 609a str r2, [r3, #8] pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; 8014196: 687b ldr r3, [r7, #4] 8014198: 2200 movs r2, #0 801419a: 601a str r2, [r3, #0] /* In case this is a recursive mutex. */ pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; 801419c: 687b ldr r3, [r7, #4] 801419e: 2200 movs r2, #0 80141a0: 60da str r2, [r3, #12] traceCREATE_MUTEX( pxNewQueue ); /* Start with the semaphore in the expected state. */ ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); 80141a2: 2300 movs r3, #0 80141a4: 2200 movs r2, #0 80141a6: 2100 movs r1, #0 80141a8: 6878 ldr r0, [r7, #4] 80141aa: f000 f8a3 bl 80142f4 } else { traceCREATE_MUTEX_FAILED(); } } 80141ae: bf00 nop 80141b0: 3708 adds r7, #8 80141b2: 46bd mov sp, r7 80141b4: bd80 pop {r7, pc} 080141b6 : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) { 80141b6: b580 push {r7, lr} 80141b8: b086 sub sp, #24 80141ba: af00 add r7, sp, #0 80141bc: 4603 mov r3, r0 80141be: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 80141c0: 2301 movs r3, #1 80141c2: 617b str r3, [r7, #20] 80141c4: 2300 movs r3, #0 80141c6: 613b str r3, [r7, #16] xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); 80141c8: 79fb ldrb r3, [r7, #7] 80141ca: 461a mov r2, r3 80141cc: 6939 ldr r1, [r7, #16] 80141ce: 6978 ldr r0, [r7, #20] 80141d0: f7ff ff79 bl 80140c6 80141d4: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 80141d6: 68f8 ldr r0, [r7, #12] 80141d8: f7ff ffd3 bl 8014182 return xNewQueue; 80141dc: 68fb ldr r3, [r7, #12] } 80141de: 4618 mov r0, r3 80141e0: 3718 adds r7, #24 80141e2: 46bd mov sp, r7 80141e4: bd80 pop {r7, pc} 080141e6 : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) { 80141e6: b580 push {r7, lr} 80141e8: b088 sub sp, #32 80141ea: af02 add r7, sp, #8 80141ec: 4603 mov r3, r0 80141ee: 6039 str r1, [r7, #0] 80141f0: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 80141f2: 2301 movs r3, #1 80141f4: 617b str r3, [r7, #20] 80141f6: 2300 movs r3, #0 80141f8: 613b str r3, [r7, #16] /* Prevent compiler warnings about unused parameters if configUSE_TRACE_FACILITY does not equal 1. */ ( void ) ucQueueType; xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); 80141fa: 79fb ldrb r3, [r7, #7] 80141fc: 9300 str r3, [sp, #0] 80141fe: 683b ldr r3, [r7, #0] 8014200: 2200 movs r2, #0 8014202: 6939 ldr r1, [r7, #16] 8014204: 6978 ldr r0, [r7, #20] 8014206: f7ff fee1 bl 8013fcc 801420a: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 801420c: 68f8 ldr r0, [r7, #12] 801420e: f7ff ffb8 bl 8014182 return xNewQueue; 8014212: 68fb ldr r3, [r7, #12] } 8014214: 4618 mov r0, r3 8014216: 3718 adds r7, #24 8014218: 46bd mov sp, r7 801421a: bd80 pop {r7, pc} 0801421c : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) { 801421c: b590 push {r4, r7, lr} 801421e: b087 sub sp, #28 8014220: af00 add r7, sp, #0 8014222: 6078 str r0, [r7, #4] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8014224: 687b ldr r3, [r7, #4] 8014226: 613b str r3, [r7, #16] configASSERT( pxMutex ); 8014228: 693b ldr r3, [r7, #16] 801422a: 2b00 cmp r3, #0 801422c: d10b bne.n 8014246 __asm volatile 801422e: f04f 0350 mov.w r3, #80 @ 0x50 8014232: f383 8811 msr BASEPRI, r3 8014236: f3bf 8f6f isb sy 801423a: f3bf 8f4f dsb sy 801423e: 60fb str r3, [r7, #12] } 8014240: bf00 nop 8014242: bf00 nop 8014244: e7fd b.n 8014242 change outside of this task. If this task does not hold the mutex then pxMutexHolder can never coincidentally equal the tasks handle, and as this is the only condition we are interested in it does not matter if pxMutexHolder is accessed simultaneously by another task. Therefore no mutual exclusion is required to test the pxMutexHolder variable. */ if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 8014246: 693b ldr r3, [r7, #16] 8014248: 689c ldr r4, [r3, #8] 801424a: f001 fe39 bl 8015ec0 801424e: 4603 mov r3, r0 8014250: 429c cmp r4, r3 8014252: d111 bne.n 8014278 /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to the task handle, therefore no underflow check is required. Also, uxRecursiveCallCount is only modified by the mutex holder, and as there can only be one, no mutual exclusion is required to modify the uxRecursiveCallCount member. */ ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; 8014254: 693b ldr r3, [r7, #16] 8014256: 68db ldr r3, [r3, #12] 8014258: 1e5a subs r2, r3, #1 801425a: 693b ldr r3, [r7, #16] 801425c: 60da str r2, [r3, #12] /* Has the recursive call count unwound to 0? */ if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) 801425e: 693b ldr r3, [r7, #16] 8014260: 68db ldr r3, [r3, #12] 8014262: 2b00 cmp r3, #0 8014264: d105 bne.n 8014272 { /* Return the mutex. This will automatically unblock any other task that might be waiting to access the mutex. */ ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); 8014266: 2300 movs r3, #0 8014268: 2200 movs r2, #0 801426a: 2100 movs r1, #0 801426c: 6938 ldr r0, [r7, #16] 801426e: f000 f841 bl 80142f4 else { mtCOVERAGE_TEST_MARKER(); } xReturn = pdPASS; 8014272: 2301 movs r3, #1 8014274: 617b str r3, [r7, #20] 8014276: e001 b.n 801427c } else { /* The mutex cannot be given because the calling task is not the holder. */ xReturn = pdFAIL; 8014278: 2300 movs r3, #0 801427a: 617b str r3, [r7, #20] traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); } return xReturn; 801427c: 697b ldr r3, [r7, #20] } 801427e: 4618 mov r0, r3 8014280: 371c adds r7, #28 8014282: 46bd mov sp, r7 8014284: bd90 pop {r4, r7, pc} 08014286 : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) { 8014286: b590 push {r4, r7, lr} 8014288: b087 sub sp, #28 801428a: af00 add r7, sp, #0 801428c: 6078 str r0, [r7, #4] 801428e: 6039 str r1, [r7, #0] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8014290: 687b ldr r3, [r7, #4] 8014292: 613b str r3, [r7, #16] configASSERT( pxMutex ); 8014294: 693b ldr r3, [r7, #16] 8014296: 2b00 cmp r3, #0 8014298: d10b bne.n 80142b2 __asm volatile 801429a: f04f 0350 mov.w r3, #80 @ 0x50 801429e: f383 8811 msr BASEPRI, r3 80142a2: f3bf 8f6f isb sy 80142a6: f3bf 8f4f dsb sy 80142aa: 60fb str r3, [r7, #12] } 80142ac: bf00 nop 80142ae: bf00 nop 80142b0: e7fd b.n 80142ae /* Comments regarding mutual exclusion as per those within xQueueGiveMutexRecursive(). */ traceTAKE_MUTEX_RECURSIVE( pxMutex ); if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 80142b2: 693b ldr r3, [r7, #16] 80142b4: 689c ldr r4, [r3, #8] 80142b6: f001 fe03 bl 8015ec0 80142ba: 4603 mov r3, r0 80142bc: 429c cmp r4, r3 80142be: d107 bne.n 80142d0 { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 80142c0: 693b ldr r3, [r7, #16] 80142c2: 68db ldr r3, [r3, #12] 80142c4: 1c5a adds r2, r3, #1 80142c6: 693b ldr r3, [r7, #16] 80142c8: 60da str r2, [r3, #12] xReturn = pdPASS; 80142ca: 2301 movs r3, #1 80142cc: 617b str r3, [r7, #20] 80142ce: e00c b.n 80142ea } else { xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait ); 80142d0: 6839 ldr r1, [r7, #0] 80142d2: 6938 ldr r0, [r7, #16] 80142d4: f000 fa90 bl 80147f8 80142d8: 6178 str r0, [r7, #20] /* pdPASS will only be returned if the mutex was successfully obtained. The calling task may have entered the Blocked state before reaching here. */ if( xReturn != pdFAIL ) 80142da: 697b ldr r3, [r7, #20] 80142dc: 2b00 cmp r3, #0 80142de: d004 beq.n 80142ea { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 80142e0: 693b ldr r3, [r7, #16] 80142e2: 68db ldr r3, [r3, #12] 80142e4: 1c5a adds r2, r3, #1 80142e6: 693b ldr r3, [r7, #16] 80142e8: 60da str r2, [r3, #12] { traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ); } } return xReturn; 80142ea: 697b ldr r3, [r7, #20] } 80142ec: 4618 mov r0, r3 80142ee: 371c adds r7, #28 80142f0: 46bd mov sp, r7 80142f2: bd90 pop {r4, r7, pc} 080142f4 : #endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) { 80142f4: b580 push {r7, lr} 80142f6: b08e sub sp, #56 @ 0x38 80142f8: af00 add r7, sp, #0 80142fa: 60f8 str r0, [r7, #12] 80142fc: 60b9 str r1, [r7, #8] 80142fe: 607a str r2, [r7, #4] 8014300: 603b str r3, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; 8014302: 2300 movs r3, #0 8014304: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8014306: 68fb ldr r3, [r7, #12] 8014308: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 801430a: 6b3b ldr r3, [r7, #48] @ 0x30 801430c: 2b00 cmp r3, #0 801430e: d10b bne.n 8014328 __asm volatile 8014310: f04f 0350 mov.w r3, #80 @ 0x50 8014314: f383 8811 msr BASEPRI, r3 8014318: f3bf 8f6f isb sy 801431c: f3bf 8f4f dsb sy 8014320: 62bb str r3, [r7, #40] @ 0x28 } 8014322: bf00 nop 8014324: bf00 nop 8014326: e7fd b.n 8014324 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8014328: 68bb ldr r3, [r7, #8] 801432a: 2b00 cmp r3, #0 801432c: d103 bne.n 8014336 801432e: 6b3b ldr r3, [r7, #48] @ 0x30 8014330: 6c1b ldr r3, [r3, #64] @ 0x40 8014332: 2b00 cmp r3, #0 8014334: d101 bne.n 801433a 8014336: 2301 movs r3, #1 8014338: e000 b.n 801433c 801433a: 2300 movs r3, #0 801433c: 2b00 cmp r3, #0 801433e: d10b bne.n 8014358 __asm volatile 8014340: f04f 0350 mov.w r3, #80 @ 0x50 8014344: f383 8811 msr BASEPRI, r3 8014348: f3bf 8f6f isb sy 801434c: f3bf 8f4f dsb sy 8014350: 627b str r3, [r7, #36] @ 0x24 } 8014352: bf00 nop 8014354: bf00 nop 8014356: e7fd b.n 8014354 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8014358: 683b ldr r3, [r7, #0] 801435a: 2b02 cmp r3, #2 801435c: d103 bne.n 8014366 801435e: 6b3b ldr r3, [r7, #48] @ 0x30 8014360: 6bdb ldr r3, [r3, #60] @ 0x3c 8014362: 2b01 cmp r3, #1 8014364: d101 bne.n 801436a 8014366: 2301 movs r3, #1 8014368: e000 b.n 801436c 801436a: 2300 movs r3, #0 801436c: 2b00 cmp r3, #0 801436e: d10b bne.n 8014388 __asm volatile 8014370: f04f 0350 mov.w r3, #80 @ 0x50 8014374: f383 8811 msr BASEPRI, r3 8014378: f3bf 8f6f isb sy 801437c: f3bf 8f4f dsb sy 8014380: 623b str r3, [r7, #32] } 8014382: bf00 nop 8014384: bf00 nop 8014386: e7fd b.n 8014384 #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8014388: f001 fdaa bl 8015ee0 801438c: 4603 mov r3, r0 801438e: 2b00 cmp r3, #0 8014390: d102 bne.n 8014398 8014392: 687b ldr r3, [r7, #4] 8014394: 2b00 cmp r3, #0 8014396: d101 bne.n 801439c 8014398: 2301 movs r3, #1 801439a: e000 b.n 801439e 801439c: 2300 movs r3, #0 801439e: 2b00 cmp r3, #0 80143a0: d10b bne.n 80143ba __asm volatile 80143a2: f04f 0350 mov.w r3, #80 @ 0x50 80143a6: f383 8811 msr BASEPRI, r3 80143aa: f3bf 8f6f isb sy 80143ae: f3bf 8f4f dsb sy 80143b2: 61fb str r3, [r7, #28] } 80143b4: bf00 nop 80143b6: bf00 nop 80143b8: e7fd b.n 80143b6 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 80143ba: f002 ff15 bl 80171e8 { /* Is there room on the queue now? The running task must be the highest priority task wanting to access the queue. If the head item in the queue is to be overwritten then it does not matter if the queue is full. */ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 80143be: 6b3b ldr r3, [r7, #48] @ 0x30 80143c0: 6b9a ldr r2, [r3, #56] @ 0x38 80143c2: 6b3b ldr r3, [r7, #48] @ 0x30 80143c4: 6bdb ldr r3, [r3, #60] @ 0x3c 80143c6: 429a cmp r2, r3 80143c8: d302 bcc.n 80143d0 80143ca: 683b ldr r3, [r7, #0] 80143cc: 2b02 cmp r3, #2 80143ce: d129 bne.n 8014424 } } } #else /* configUSE_QUEUE_SETS */ { xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 80143d0: 683a ldr r2, [r7, #0] 80143d2: 68b9 ldr r1, [r7, #8] 80143d4: 6b38 ldr r0, [r7, #48] @ 0x30 80143d6: f000 fbb9 bl 8014b4c 80143da: 62f8 str r0, [r7, #44] @ 0x2c /* If there was a task waiting for data to arrive on the queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 80143dc: 6b3b ldr r3, [r7, #48] @ 0x30 80143de: 6a5b ldr r3, [r3, #36] @ 0x24 80143e0: 2b00 cmp r3, #0 80143e2: d010 beq.n 8014406 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 80143e4: 6b3b ldr r3, [r7, #48] @ 0x30 80143e6: 3324 adds r3, #36 @ 0x24 80143e8: 4618 mov r0, r3 80143ea: f001 fb7b bl 8015ae4 80143ee: 4603 mov r3, r0 80143f0: 2b00 cmp r3, #0 80143f2: d013 beq.n 801441c { /* The unblocked task has a priority higher than our own so yield immediately. Yes it is ok to do this from within the critical section - the kernel takes care of that. */ queueYIELD_IF_USING_PREEMPTION(); 80143f4: 4b3f ldr r3, [pc, #252] @ (80144f4 ) 80143f6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80143fa: 601a str r2, [r3, #0] 80143fc: f3bf 8f4f dsb sy 8014400: f3bf 8f6f isb sy 8014404: e00a b.n 801441c else { mtCOVERAGE_TEST_MARKER(); } } else if( xYieldRequired != pdFALSE ) 8014406: 6afb ldr r3, [r7, #44] @ 0x2c 8014408: 2b00 cmp r3, #0 801440a: d007 beq.n 801441c { /* This path is a special case that will only get executed if the task was holding multiple mutexes and the mutexes were given back in an order that is different to that in which they were taken. */ queueYIELD_IF_USING_PREEMPTION(); 801440c: 4b39 ldr r3, [pc, #228] @ (80144f4 ) 801440e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014412: 601a str r2, [r3, #0] 8014414: f3bf 8f4f dsb sy 8014418: f3bf 8f6f isb sy mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); 801441c: f002 ff16 bl 801724c return pdPASS; 8014420: 2301 movs r3, #1 8014422: e063 b.n 80144ec } else { if( xTicksToWait == ( TickType_t ) 0 ) 8014424: 687b ldr r3, [r7, #4] 8014426: 2b00 cmp r3, #0 8014428: d103 bne.n 8014432 { /* The queue was full and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 801442a: f002 ff0f bl 801724c /* Return to the original privilege level before exiting the function. */ traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 801442e: 2300 movs r3, #0 8014430: e05c b.n 80144ec } else if( xEntryTimeSet == pdFALSE ) 8014432: 6b7b ldr r3, [r7, #52] @ 0x34 8014434: 2b00 cmp r3, #0 8014436: d106 bne.n 8014446 { /* The queue was full and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8014438: f107 0314 add.w r3, r7, #20 801443c: 4618 mov r0, r3 801443e: f001 fbdd bl 8015bfc xEntryTimeSet = pdTRUE; 8014442: 2301 movs r3, #1 8014444: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8014446: f002 ff01 bl 801724c /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 801444a: f001 f90f bl 801566c prvLockQueue( pxQueue ); 801444e: f002 fecb bl 80171e8 8014452: 6b3b ldr r3, [r7, #48] @ 0x30 8014454: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014458: b25b sxtb r3, r3 801445a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801445e: d103 bne.n 8014468 8014460: 6b3b ldr r3, [r7, #48] @ 0x30 8014462: 2200 movs r2, #0 8014464: f883 2044 strb.w r2, [r3, #68] @ 0x44 8014468: 6b3b ldr r3, [r7, #48] @ 0x30 801446a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 801446e: b25b sxtb r3, r3 8014470: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014474: d103 bne.n 801447e 8014476: 6b3b ldr r3, [r7, #48] @ 0x30 8014478: 2200 movs r2, #0 801447a: f883 2045 strb.w r2, [r3, #69] @ 0x45 801447e: f002 fee5 bl 801724c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8014482: 1d3a adds r2, r7, #4 8014484: f107 0314 add.w r3, r7, #20 8014488: 4611 mov r1, r2 801448a: 4618 mov r0, r3 801448c: f001 fbcc bl 8015c28 8014490: 4603 mov r3, r0 8014492: 2b00 cmp r3, #0 8014494: d124 bne.n 80144e0 { if( prvIsQueueFull( pxQueue ) != pdFALSE ) 8014496: 6b38 ldr r0, [r7, #48] @ 0x30 8014498: f000 fc50 bl 8014d3c 801449c: 4603 mov r3, r0 801449e: 2b00 cmp r3, #0 80144a0: d018 beq.n 80144d4 { traceBLOCKING_ON_QUEUE_SEND( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); 80144a2: 6b3b ldr r3, [r7, #48] @ 0x30 80144a4: 3310 adds r3, #16 80144a6: 687a ldr r2, [r7, #4] 80144a8: 4611 mov r1, r2 80144aa: 4618 mov r0, r3 80144ac: f001 fac8 bl 8015a40 /* Unlocking the queue means queue events can effect the event list. It is possible that interrupts occurring now remove this task from the event list again - but as the scheduler is suspended the task will go onto the pending ready last instead of the actual ready list. */ prvUnlockQueue( pxQueue ); 80144b0: 6b38 ldr r0, [r7, #48] @ 0x30 80144b2: f000 fbdb bl 8014c6c /* Resuming the scheduler will move tasks from the pending ready list into the ready list - so it is feasible that this task is already in a ready list before it yields - in which case the yield will not cause a context switch unless there is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) 80144b6: f001 f8e7 bl 8015688 80144ba: 4603 mov r3, r0 80144bc: 2b00 cmp r3, #0 80144be: f47f af7c bne.w 80143ba { portYIELD_WITHIN_API(); 80144c2: 4b0c ldr r3, [pc, #48] @ (80144f4 ) 80144c4: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80144c8: 601a str r2, [r3, #0] 80144ca: f3bf 8f4f dsb sy 80144ce: f3bf 8f6f isb sy 80144d2: e772 b.n 80143ba } } else { /* Try again. */ prvUnlockQueue( pxQueue ); 80144d4: 6b38 ldr r0, [r7, #48] @ 0x30 80144d6: f000 fbc9 bl 8014c6c ( void ) xTaskResumeAll(); 80144da: f001 f8d5 bl 8015688 80144de: e76c b.n 80143ba } } else { /* The timeout has expired. */ prvUnlockQueue( pxQueue ); 80144e0: 6b38 ldr r0, [r7, #48] @ 0x30 80144e2: f000 fbc3 bl 8014c6c ( void ) xTaskResumeAll(); 80144e6: f001 f8cf bl 8015688 traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 80144ea: 2300 movs r3, #0 } } /*lint -restore */ } 80144ec: 4618 mov r0, r3 80144ee: 3738 adds r7, #56 @ 0x38 80144f0: 46bd mov sp, r7 80144f2: bd80 pop {r7, pc} 80144f4: e000ed04 .word 0xe000ed04 080144f8 : /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) { 80144f8: b580 push {r7, lr} 80144fa: b090 sub sp, #64 @ 0x40 80144fc: af00 add r7, sp, #0 80144fe: 60f8 str r0, [r7, #12] 8014500: 60b9 str r1, [r7, #8] 8014502: 607a str r2, [r7, #4] 8014504: 603b str r3, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8014506: 68fb ldr r3, [r7, #12] 8014508: 63bb str r3, [r7, #56] @ 0x38 configASSERT( pxQueue ); 801450a: 6bbb ldr r3, [r7, #56] @ 0x38 801450c: 2b00 cmp r3, #0 801450e: d10b bne.n 8014528 __asm volatile 8014510: f04f 0350 mov.w r3, #80 @ 0x50 8014514: f383 8811 msr BASEPRI, r3 8014518: f3bf 8f6f isb sy 801451c: f3bf 8f4f dsb sy 8014520: 62bb str r3, [r7, #40] @ 0x28 } 8014522: bf00 nop 8014524: bf00 nop 8014526: e7fd b.n 8014524 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8014528: 68bb ldr r3, [r7, #8] 801452a: 2b00 cmp r3, #0 801452c: d103 bne.n 8014536 801452e: 6bbb ldr r3, [r7, #56] @ 0x38 8014530: 6c1b ldr r3, [r3, #64] @ 0x40 8014532: 2b00 cmp r3, #0 8014534: d101 bne.n 801453a 8014536: 2301 movs r3, #1 8014538: e000 b.n 801453c 801453a: 2300 movs r3, #0 801453c: 2b00 cmp r3, #0 801453e: d10b bne.n 8014558 __asm volatile 8014540: f04f 0350 mov.w r3, #80 @ 0x50 8014544: f383 8811 msr BASEPRI, r3 8014548: f3bf 8f6f isb sy 801454c: f3bf 8f4f dsb sy 8014550: 627b str r3, [r7, #36] @ 0x24 } 8014552: bf00 nop 8014554: bf00 nop 8014556: e7fd b.n 8014554 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8014558: 683b ldr r3, [r7, #0] 801455a: 2b02 cmp r3, #2 801455c: d103 bne.n 8014566 801455e: 6bbb ldr r3, [r7, #56] @ 0x38 8014560: 6bdb ldr r3, [r3, #60] @ 0x3c 8014562: 2b01 cmp r3, #1 8014564: d101 bne.n 801456a 8014566: 2301 movs r3, #1 8014568: e000 b.n 801456c 801456a: 2300 movs r3, #0 801456c: 2b00 cmp r3, #0 801456e: d10b bne.n 8014588 __asm volatile 8014570: f04f 0350 mov.w r3, #80 @ 0x50 8014574: f383 8811 msr BASEPRI, r3 8014578: f3bf 8f6f isb sy 801457c: f3bf 8f4f dsb sy 8014580: 623b str r3, [r7, #32] } 8014582: bf00 nop 8014584: bf00 nop 8014586: e7fd b.n 8014584 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8014588: f002 ff0e bl 80173a8 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile 801458c: f3ef 8211 mrs r2, BASEPRI 8014590: f04f 0350 mov.w r3, #80 @ 0x50 8014594: f383 8811 msr BASEPRI, r3 8014598: f3bf 8f6f isb sy 801459c: f3bf 8f4f dsb sy 80145a0: 61fa str r2, [r7, #28] 80145a2: 61bb str r3, [r7, #24] :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; 80145a4: 69fb ldr r3, [r7, #28] /* Similar to xQueueGenericSend, except without blocking if there is no room in the queue. Also don't directly wake a task that was blocked on a queue read, instead return a flag to say whether a context switch is required or not (i.e. has a task with a higher priority than us been woken by this post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 80145a6: 637b str r3, [r7, #52] @ 0x34 { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 80145a8: 6bbb ldr r3, [r7, #56] @ 0x38 80145aa: 6b9a ldr r2, [r3, #56] @ 0x38 80145ac: 6bbb ldr r3, [r7, #56] @ 0x38 80145ae: 6bdb ldr r3, [r3, #60] @ 0x3c 80145b0: 429a cmp r2, r3 80145b2: d302 bcc.n 80145ba 80145b4: 683b ldr r3, [r7, #0] 80145b6: 2b02 cmp r3, #2 80145b8: d12f bne.n 801461a { const int8_t cTxLock = pxQueue->cTxLock; 80145ba: 6bbb ldr r3, [r7, #56] @ 0x38 80145bc: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80145c0: f887 3033 strb.w r3, [r7, #51] @ 0x33 const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; 80145c4: 6bbb ldr r3, [r7, #56] @ 0x38 80145c6: 6b9b ldr r3, [r3, #56] @ 0x38 80145c8: 62fb str r3, [r7, #44] @ 0x2c /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a semaphore or mutex. That means prvCopyDataToQueue() cannot result in a task disinheriting a priority and prvCopyDataToQueue() can be called here even though the disinherit function does not check if the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 80145ca: 683a ldr r2, [r7, #0] 80145cc: 68b9 ldr r1, [r7, #8] 80145ce: 6bb8 ldr r0, [r7, #56] @ 0x38 80145d0: f000 fabc bl 8014b4c /* The event list is not altered if the queue is locked. This will be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 80145d4: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33 80145d8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80145dc: d112 bne.n 8014604 } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 80145de: 6bbb ldr r3, [r7, #56] @ 0x38 80145e0: 6a5b ldr r3, [r3, #36] @ 0x24 80145e2: 2b00 cmp r3, #0 80145e4: d016 beq.n 8014614 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 80145e6: 6bbb ldr r3, [r7, #56] @ 0x38 80145e8: 3324 adds r3, #36 @ 0x24 80145ea: 4618 mov r0, r3 80145ec: f001 fa7a bl 8015ae4 80145f0: 4603 mov r3, r0 80145f2: 2b00 cmp r3, #0 80145f4: d00e beq.n 8014614 { /* The task waiting has a higher priority so record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 80145f6: 687b ldr r3, [r7, #4] 80145f8: 2b00 cmp r3, #0 80145fa: d00b beq.n 8014614 { *pxHigherPriorityTaskWoken = pdTRUE; 80145fc: 687b ldr r3, [r7, #4] 80145fe: 2201 movs r2, #1 8014600: 601a str r2, [r3, #0] 8014602: e007 b.n 8014614 } else { /* Increment the lock count so the task that unlocks the queue knows that data was posted while it was locked. */ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); 8014604: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 8014608: 3301 adds r3, #1 801460a: b2db uxtb r3, r3 801460c: b25a sxtb r2, r3 801460e: 6bbb ldr r3, [r7, #56] @ 0x38 8014610: f883 2045 strb.w r2, [r3, #69] @ 0x45 } xReturn = pdPASS; 8014614: 2301 movs r3, #1 8014616: 63fb str r3, [r7, #60] @ 0x3c { 8014618: e001 b.n 801461e } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 801461a: 2300 movs r3, #0 801461c: 63fb str r3, [r7, #60] @ 0x3c 801461e: 6b7b ldr r3, [r7, #52] @ 0x34 8014620: 617b str r3, [r7, #20] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile 8014622: 697b ldr r3, [r7, #20] 8014624: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } 8014628: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 801462a: 6bfb ldr r3, [r7, #60] @ 0x3c } 801462c: 4618 mov r0, r3 801462e: 3740 adds r7, #64 @ 0x40 8014630: 46bd mov sp, r7 8014632: bd80 pop {r7, pc} 08014634 : return xReturn; } /*-----------------------------------------------------------*/ BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) { 8014634: b580 push {r7, lr} 8014636: b08c sub sp, #48 @ 0x30 8014638: af00 add r7, sp, #0 801463a: 60f8 str r0, [r7, #12] 801463c: 60b9 str r1, [r7, #8] 801463e: 607a str r2, [r7, #4] BaseType_t xEntryTimeSet = pdFALSE; 8014640: 2300 movs r3, #0 8014642: 62fb str r3, [r7, #44] @ 0x2c TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8014644: 68fb ldr r3, [r7, #12] 8014646: 62bb str r3, [r7, #40] @ 0x28 /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); 8014648: 6abb ldr r3, [r7, #40] @ 0x28 801464a: 2b00 cmp r3, #0 801464c: d10b bne.n 8014666 __asm volatile 801464e: f04f 0350 mov.w r3, #80 @ 0x50 8014652: f383 8811 msr BASEPRI, r3 8014656: f3bf 8f6f isb sy 801465a: f3bf 8f4f dsb sy 801465e: 623b str r3, [r7, #32] } 8014660: bf00 nop 8014662: bf00 nop 8014664: e7fd b.n 8014662 /* The buffer into which data is received can only be NULL if the data size is zero (so no data is copied into the buffer. */ configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8014666: 68bb ldr r3, [r7, #8] 8014668: 2b00 cmp r3, #0 801466a: d103 bne.n 8014674 801466c: 6abb ldr r3, [r7, #40] @ 0x28 801466e: 6c1b ldr r3, [r3, #64] @ 0x40 8014670: 2b00 cmp r3, #0 8014672: d101 bne.n 8014678 8014674: 2301 movs r3, #1 8014676: e000 b.n 801467a 8014678: 2300 movs r3, #0 801467a: 2b00 cmp r3, #0 801467c: d10b bne.n 8014696 __asm volatile 801467e: f04f 0350 mov.w r3, #80 @ 0x50 8014682: f383 8811 msr BASEPRI, r3 8014686: f3bf 8f6f isb sy 801468a: f3bf 8f4f dsb sy 801468e: 61fb str r3, [r7, #28] } 8014690: bf00 nop 8014692: bf00 nop 8014694: e7fd b.n 8014692 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8014696: f001 fc23 bl 8015ee0 801469a: 4603 mov r3, r0 801469c: 2b00 cmp r3, #0 801469e: d102 bne.n 80146a6 80146a0: 687b ldr r3, [r7, #4] 80146a2: 2b00 cmp r3, #0 80146a4: d101 bne.n 80146aa 80146a6: 2301 movs r3, #1 80146a8: e000 b.n 80146ac 80146aa: 2300 movs r3, #0 80146ac: 2b00 cmp r3, #0 80146ae: d10b bne.n 80146c8 __asm volatile 80146b0: f04f 0350 mov.w r3, #80 @ 0x50 80146b4: f383 8811 msr BASEPRI, r3 80146b8: f3bf 8f6f isb sy 80146bc: f3bf 8f4f dsb sy 80146c0: 61bb str r3, [r7, #24] } 80146c2: bf00 nop 80146c4: bf00 nop 80146c6: e7fd b.n 80146c4 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 80146c8: f002 fd8e bl 80171e8 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 80146cc: 6abb ldr r3, [r7, #40] @ 0x28 80146ce: 6b9b ldr r3, [r3, #56] @ 0x38 80146d0: 627b str r3, [r7, #36] @ 0x24 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 80146d2: 6a7b ldr r3, [r7, #36] @ 0x24 80146d4: 2b00 cmp r3, #0 80146d6: d01f beq.n 8014718 { /* Data available, remove one item. */ prvCopyDataFromQueue( pxQueue, pvBuffer ); 80146d8: 68b9 ldr r1, [r7, #8] 80146da: 6ab8 ldr r0, [r7, #40] @ 0x28 80146dc: f000 faa0 bl 8014c20 traceQUEUE_RECEIVE( pxQueue ); pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 80146e0: 6a7b ldr r3, [r7, #36] @ 0x24 80146e2: 1e5a subs r2, r3, #1 80146e4: 6abb ldr r3, [r7, #40] @ 0x28 80146e6: 639a str r2, [r3, #56] @ 0x38 /* There is now space in the queue, were any tasks waiting to post to the queue? If so, unblock the highest priority waiting task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80146e8: 6abb ldr r3, [r7, #40] @ 0x28 80146ea: 691b ldr r3, [r3, #16] 80146ec: 2b00 cmp r3, #0 80146ee: d00f beq.n 8014710 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80146f0: 6abb ldr r3, [r7, #40] @ 0x28 80146f2: 3310 adds r3, #16 80146f4: 4618 mov r0, r3 80146f6: f001 f9f5 bl 8015ae4 80146fa: 4603 mov r3, r0 80146fc: 2b00 cmp r3, #0 80146fe: d007 beq.n 8014710 { queueYIELD_IF_USING_PREEMPTION(); 8014700: 4b3c ldr r3, [pc, #240] @ (80147f4 ) 8014702: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014706: 601a str r2, [r3, #0] 8014708: f3bf 8f4f dsb sy 801470c: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 8014710: f002 fd9c bl 801724c return pdPASS; 8014714: 2301 movs r3, #1 8014716: e069 b.n 80147ec } else { if( xTicksToWait == ( TickType_t ) 0 ) 8014718: 687b ldr r3, [r7, #4] 801471a: 2b00 cmp r3, #0 801471c: d103 bne.n 8014726 { /* The queue was empty and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 801471e: f002 fd95 bl 801724c traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8014722: 2300 movs r3, #0 8014724: e062 b.n 80147ec } else if( xEntryTimeSet == pdFALSE ) 8014726: 6afb ldr r3, [r7, #44] @ 0x2c 8014728: 2b00 cmp r3, #0 801472a: d106 bne.n 801473a { /* The queue was empty and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 801472c: f107 0310 add.w r3, r7, #16 8014730: 4618 mov r0, r3 8014732: f001 fa63 bl 8015bfc xEntryTimeSet = pdTRUE; 8014736: 2301 movs r3, #1 8014738: 62fb str r3, [r7, #44] @ 0x2c /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 801473a: f002 fd87 bl 801724c /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 801473e: f000 ff95 bl 801566c prvLockQueue( pxQueue ); 8014742: f002 fd51 bl 80171e8 8014746: 6abb ldr r3, [r7, #40] @ 0x28 8014748: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 801474c: b25b sxtb r3, r3 801474e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014752: d103 bne.n 801475c 8014754: 6abb ldr r3, [r7, #40] @ 0x28 8014756: 2200 movs r2, #0 8014758: f883 2044 strb.w r2, [r3, #68] @ 0x44 801475c: 6abb ldr r3, [r7, #40] @ 0x28 801475e: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014762: b25b sxtb r3, r3 8014764: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014768: d103 bne.n 8014772 801476a: 6abb ldr r3, [r7, #40] @ 0x28 801476c: 2200 movs r2, #0 801476e: f883 2045 strb.w r2, [r3, #69] @ 0x45 8014772: f002 fd6b bl 801724c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8014776: 1d3a adds r2, r7, #4 8014778: f107 0310 add.w r3, r7, #16 801477c: 4611 mov r1, r2 801477e: 4618 mov r0, r3 8014780: f001 fa52 bl 8015c28 8014784: 4603 mov r3, r0 8014786: 2b00 cmp r3, #0 8014788: d123 bne.n 80147d2 { /* The timeout has not expired. If the queue is still empty place the task on the list of tasks waiting to receive from the queue. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 801478a: 6ab8 ldr r0, [r7, #40] @ 0x28 801478c: f000 fac0 bl 8014d10 8014790: 4603 mov r3, r0 8014792: 2b00 cmp r3, #0 8014794: d017 beq.n 80147c6 { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 8014796: 6abb ldr r3, [r7, #40] @ 0x28 8014798: 3324 adds r3, #36 @ 0x24 801479a: 687a ldr r2, [r7, #4] 801479c: 4611 mov r1, r2 801479e: 4618 mov r0, r3 80147a0: f001 f94e bl 8015a40 prvUnlockQueue( pxQueue ); 80147a4: 6ab8 ldr r0, [r7, #40] @ 0x28 80147a6: f000 fa61 bl 8014c6c if( xTaskResumeAll() == pdFALSE ) 80147aa: f000 ff6d bl 8015688 80147ae: 4603 mov r3, r0 80147b0: 2b00 cmp r3, #0 80147b2: d189 bne.n 80146c8 { portYIELD_WITHIN_API(); 80147b4: 4b0f ldr r3, [pc, #60] @ (80147f4 ) 80147b6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80147ba: 601a str r2, [r3, #0] 80147bc: f3bf 8f4f dsb sy 80147c0: f3bf 8f6f isb sy 80147c4: e780 b.n 80146c8 } else { /* The queue contains data again. Loop back to try and read the data. */ prvUnlockQueue( pxQueue ); 80147c6: 6ab8 ldr r0, [r7, #40] @ 0x28 80147c8: f000 fa50 bl 8014c6c ( void ) xTaskResumeAll(); 80147cc: f000 ff5c bl 8015688 80147d0: e77a b.n 80146c8 } else { /* Timed out. If there is no data in the queue exit, otherwise loop back and attempt to read the data. */ prvUnlockQueue( pxQueue ); 80147d2: 6ab8 ldr r0, [r7, #40] @ 0x28 80147d4: f000 fa4a bl 8014c6c ( void ) xTaskResumeAll(); 80147d8: f000 ff56 bl 8015688 if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80147dc: 6ab8 ldr r0, [r7, #40] @ 0x28 80147de: f000 fa97 bl 8014d10 80147e2: 4603 mov r3, r0 80147e4: 2b00 cmp r3, #0 80147e6: f43f af6f beq.w 80146c8 { traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 80147ea: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 80147ec: 4618 mov r0, r3 80147ee: 3730 adds r7, #48 @ 0x30 80147f0: 46bd mov sp, r7 80147f2: bd80 pop {r7, pc} 80147f4: e000ed04 .word 0xe000ed04 080147f8 : /*-----------------------------------------------------------*/ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) { 80147f8: b580 push {r7, lr} 80147fa: b08e sub sp, #56 @ 0x38 80147fc: af00 add r7, sp, #0 80147fe: 6078 str r0, [r7, #4] 8014800: 6039 str r1, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE; 8014802: 2300 movs r3, #0 8014804: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8014806: 687b ldr r3, [r7, #4] 8014808: 62fb str r3, [r7, #44] @ 0x2c #if( configUSE_MUTEXES == 1 ) BaseType_t xInheritanceOccurred = pdFALSE; 801480a: 2300 movs r3, #0 801480c: 633b str r3, [r7, #48] @ 0x30 #endif /* Check the queue pointer is not NULL. */ configASSERT( ( pxQueue ) ); 801480e: 6afb ldr r3, [r7, #44] @ 0x2c 8014810: 2b00 cmp r3, #0 8014812: d10b bne.n 801482c __asm volatile 8014814: f04f 0350 mov.w r3, #80 @ 0x50 8014818: f383 8811 msr BASEPRI, r3 801481c: f3bf 8f6f isb sy 8014820: f3bf 8f4f dsb sy 8014824: 623b str r3, [r7, #32] } 8014826: bf00 nop 8014828: bf00 nop 801482a: e7fd b.n 8014828 /* Check this really is a semaphore, in which case the item size will be 0. */ configASSERT( pxQueue->uxItemSize == 0 ); 801482c: 6afb ldr r3, [r7, #44] @ 0x2c 801482e: 6c1b ldr r3, [r3, #64] @ 0x40 8014830: 2b00 cmp r3, #0 8014832: d00b beq.n 801484c __asm volatile 8014834: f04f 0350 mov.w r3, #80 @ 0x50 8014838: f383 8811 msr BASEPRI, r3 801483c: f3bf 8f6f isb sy 8014840: f3bf 8f4f dsb sy 8014844: 61fb str r3, [r7, #28] } 8014846: bf00 nop 8014848: bf00 nop 801484a: e7fd b.n 8014848 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 801484c: f001 fb48 bl 8015ee0 8014850: 4603 mov r3, r0 8014852: 2b00 cmp r3, #0 8014854: d102 bne.n 801485c 8014856: 683b ldr r3, [r7, #0] 8014858: 2b00 cmp r3, #0 801485a: d101 bne.n 8014860 801485c: 2301 movs r3, #1 801485e: e000 b.n 8014862 8014860: 2300 movs r3, #0 8014862: 2b00 cmp r3, #0 8014864: d10b bne.n 801487e __asm volatile 8014866: f04f 0350 mov.w r3, #80 @ 0x50 801486a: f383 8811 msr BASEPRI, r3 801486e: f3bf 8f6f isb sy 8014872: f3bf 8f4f dsb sy 8014876: 61bb str r3, [r7, #24] } 8014878: bf00 nop 801487a: bf00 nop 801487c: e7fd b.n 801487a /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 801487e: f002 fcb3 bl 80171e8 { /* Semaphores are queues with an item size of 0, and where the number of messages in the queue is the semaphore's count value. */ const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; 8014882: 6afb ldr r3, [r7, #44] @ 0x2c 8014884: 6b9b ldr r3, [r3, #56] @ 0x38 8014886: 62bb str r3, [r7, #40] @ 0x28 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxSemaphoreCount > ( UBaseType_t ) 0 ) 8014888: 6abb ldr r3, [r7, #40] @ 0x28 801488a: 2b00 cmp r3, #0 801488c: d024 beq.n 80148d8 { traceQUEUE_RECEIVE( pxQueue ); /* Semaphores are queues with a data size of zero and where the messages waiting is the semaphore's count. Reduce the count. */ pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; 801488e: 6abb ldr r3, [r7, #40] @ 0x28 8014890: 1e5a subs r2, r3, #1 8014892: 6afb ldr r3, [r7, #44] @ 0x2c 8014894: 639a str r2, [r3, #56] @ 0x38 #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8014896: 6afb ldr r3, [r7, #44] @ 0x2c 8014898: 681b ldr r3, [r3, #0] 801489a: 2b00 cmp r3, #0 801489c: d104 bne.n 80148a8 { /* Record the information required to implement priority inheritance should it become necessary. */ pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); 801489e: f001 fc99 bl 80161d4 80148a2: 4602 mov r2, r0 80148a4: 6afb ldr r3, [r7, #44] @ 0x2c 80148a6: 609a str r2, [r3, #8] } #endif /* configUSE_MUTEXES */ /* Check to see if other tasks are blocked waiting to give the semaphore, and if so, unblock the highest priority such task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80148a8: 6afb ldr r3, [r7, #44] @ 0x2c 80148aa: 691b ldr r3, [r3, #16] 80148ac: 2b00 cmp r3, #0 80148ae: d00f beq.n 80148d0 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80148b0: 6afb ldr r3, [r7, #44] @ 0x2c 80148b2: 3310 adds r3, #16 80148b4: 4618 mov r0, r3 80148b6: f001 f915 bl 8015ae4 80148ba: 4603 mov r3, r0 80148bc: 2b00 cmp r3, #0 80148be: d007 beq.n 80148d0 { queueYIELD_IF_USING_PREEMPTION(); 80148c0: 4b54 ldr r3, [pc, #336] @ (8014a14 ) 80148c2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80148c6: 601a str r2, [r3, #0] 80148c8: f3bf 8f4f dsb sy 80148cc: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 80148d0: f002 fcbc bl 801724c return pdPASS; 80148d4: 2301 movs r3, #1 80148d6: e098 b.n 8014a0a } else { if( xTicksToWait == ( TickType_t ) 0 ) 80148d8: 683b ldr r3, [r7, #0] 80148da: 2b00 cmp r3, #0 80148dc: d112 bne.n 8014904 /* For inheritance to have occurred there must have been an initial timeout, and an adjusted timeout cannot become 0, as if it were 0 the function would have exited. */ #if( configUSE_MUTEXES == 1 ) { configASSERT( xInheritanceOccurred == pdFALSE ); 80148de: 6b3b ldr r3, [r7, #48] @ 0x30 80148e0: 2b00 cmp r3, #0 80148e2: d00b beq.n 80148fc __asm volatile 80148e4: f04f 0350 mov.w r3, #80 @ 0x50 80148e8: f383 8811 msr BASEPRI, r3 80148ec: f3bf 8f6f isb sy 80148f0: f3bf 8f4f dsb sy 80148f4: 617b str r3, [r7, #20] } 80148f6: bf00 nop 80148f8: bf00 nop 80148fa: e7fd b.n 80148f8 } #endif /* configUSE_MUTEXES */ /* The semaphore count was 0 and no block time is specified (or the block time has expired) so exit now. */ taskEXIT_CRITICAL(); 80148fc: f002 fca6 bl 801724c traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8014900: 2300 movs r3, #0 8014902: e082 b.n 8014a0a } else if( xEntryTimeSet == pdFALSE ) 8014904: 6b7b ldr r3, [r7, #52] @ 0x34 8014906: 2b00 cmp r3, #0 8014908: d106 bne.n 8014918 { /* The semaphore count was 0 and a block time was specified so configure the timeout structure ready to block. */ vTaskInternalSetTimeOutState( &xTimeOut ); 801490a: f107 030c add.w r3, r7, #12 801490e: 4618 mov r0, r3 8014910: f001 f974 bl 8015bfc xEntryTimeSet = pdTRUE; 8014914: 2301 movs r3, #1 8014916: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8014918: f002 fc98 bl 801724c /* Interrupts and other tasks can give to and take from the semaphore now the critical section has been exited. */ vTaskSuspendAll(); 801491c: f000 fea6 bl 801566c prvLockQueue( pxQueue ); 8014920: f002 fc62 bl 80171e8 8014924: 6afb ldr r3, [r7, #44] @ 0x2c 8014926: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 801492a: b25b sxtb r3, r3 801492c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014930: d103 bne.n 801493a 8014932: 6afb ldr r3, [r7, #44] @ 0x2c 8014934: 2200 movs r2, #0 8014936: f883 2044 strb.w r2, [r3, #68] @ 0x44 801493a: 6afb ldr r3, [r7, #44] @ 0x2c 801493c: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014940: b25b sxtb r3, r3 8014942: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014946: d103 bne.n 8014950 8014948: 6afb ldr r3, [r7, #44] @ 0x2c 801494a: 2200 movs r2, #0 801494c: f883 2045 strb.w r2, [r3, #69] @ 0x45 8014950: f002 fc7c bl 801724c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8014954: 463a mov r2, r7 8014956: f107 030c add.w r3, r7, #12 801495a: 4611 mov r1, r2 801495c: 4618 mov r0, r3 801495e: f001 f963 bl 8015c28 8014962: 4603 mov r3, r0 8014964: 2b00 cmp r3, #0 8014966: d132 bne.n 80149ce { /* A block time is specified and not expired. If the semaphore count is 0 then enter the Blocked state to wait for a semaphore to become available. As semaphores are implemented with queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8014968: 6af8 ldr r0, [r7, #44] @ 0x2c 801496a: f000 f9d1 bl 8014d10 801496e: 4603 mov r3, r0 8014970: 2b00 cmp r3, #0 8014972: d026 beq.n 80149c2 { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8014974: 6afb ldr r3, [r7, #44] @ 0x2c 8014976: 681b ldr r3, [r3, #0] 8014978: 2b00 cmp r3, #0 801497a: d109 bne.n 8014990 { taskENTER_CRITICAL(); 801497c: f002 fc34 bl 80171e8 { xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); 8014980: 6afb ldr r3, [r7, #44] @ 0x2c 8014982: 689b ldr r3, [r3, #8] 8014984: 4618 mov r0, r3 8014986: f001 fac9 bl 8015f1c 801498a: 6338 str r0, [r7, #48] @ 0x30 } taskEXIT_CRITICAL(); 801498c: f002 fc5e bl 801724c mtCOVERAGE_TEST_MARKER(); } } #endif vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 8014990: 6afb ldr r3, [r7, #44] @ 0x2c 8014992: 3324 adds r3, #36 @ 0x24 8014994: 683a ldr r2, [r7, #0] 8014996: 4611 mov r1, r2 8014998: 4618 mov r0, r3 801499a: f001 f851 bl 8015a40 prvUnlockQueue( pxQueue ); 801499e: 6af8 ldr r0, [r7, #44] @ 0x2c 80149a0: f000 f964 bl 8014c6c if( xTaskResumeAll() == pdFALSE ) 80149a4: f000 fe70 bl 8015688 80149a8: 4603 mov r3, r0 80149aa: 2b00 cmp r3, #0 80149ac: f47f af67 bne.w 801487e { portYIELD_WITHIN_API(); 80149b0: 4b18 ldr r3, [pc, #96] @ (8014a14 ) 80149b2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80149b6: 601a str r2, [r3, #0] 80149b8: f3bf 8f4f dsb sy 80149bc: f3bf 8f6f isb sy 80149c0: e75d b.n 801487e } else { /* There was no timeout and the semaphore count was not 0, so attempt to take the semaphore again. */ prvUnlockQueue( pxQueue ); 80149c2: 6af8 ldr r0, [r7, #44] @ 0x2c 80149c4: f000 f952 bl 8014c6c ( void ) xTaskResumeAll(); 80149c8: f000 fe5e bl 8015688 80149cc: e757 b.n 801487e } } else { /* Timed out. */ prvUnlockQueue( pxQueue ); 80149ce: 6af8 ldr r0, [r7, #44] @ 0x2c 80149d0: f000 f94c bl 8014c6c ( void ) xTaskResumeAll(); 80149d4: f000 fe58 bl 8015688 /* If the semaphore count is 0 exit now as the timeout has expired. Otherwise return to attempt to take the semaphore that is known to be available. As semaphores are implemented by queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80149d8: 6af8 ldr r0, [r7, #44] @ 0x2c 80149da: f000 f999 bl 8014d10 80149de: 4603 mov r3, r0 80149e0: 2b00 cmp r3, #0 80149e2: f43f af4c beq.w 801487e #if ( configUSE_MUTEXES == 1 ) { /* xInheritanceOccurred could only have be set if pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to test the mutex type again to check it is actually a mutex. */ if( xInheritanceOccurred != pdFALSE ) 80149e6: 6b3b ldr r3, [r7, #48] @ 0x30 80149e8: 2b00 cmp r3, #0 80149ea: d00d beq.n 8014a08 { taskENTER_CRITICAL(); 80149ec: f002 fbfc bl 80171e8 /* This task blocking on the mutex caused another task to inherit this task's priority. Now this task has timed out the priority should be disinherited again, but only as low as the next highest priority task that is waiting for the same mutex. */ uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); 80149f0: 6af8 ldr r0, [r7, #44] @ 0x2c 80149f2: f000 f893 bl 8014b1c 80149f6: 6278 str r0, [r7, #36] @ 0x24 vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); 80149f8: 6afb ldr r3, [r7, #44] @ 0x2c 80149fa: 689b ldr r3, [r3, #8] 80149fc: 6a79 ldr r1, [r7, #36] @ 0x24 80149fe: 4618 mov r0, r3 8014a00: f001 fb64 bl 80160cc } taskEXIT_CRITICAL(); 8014a04: f002 fc22 bl 801724c } } #endif /* configUSE_MUTEXES */ traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8014a08: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 8014a0a: 4618 mov r0, r3 8014a0c: 3738 adds r7, #56 @ 0x38 8014a0e: 46bd mov sp, r7 8014a10: bd80 pop {r7, pc} 8014a12: bf00 nop 8014a14: e000ed04 .word 0xe000ed04 08014a18 : } /*lint -restore */ } /*-----------------------------------------------------------*/ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) { 8014a18: b580 push {r7, lr} 8014a1a: b08e sub sp, #56 @ 0x38 8014a1c: af00 add r7, sp, #0 8014a1e: 60f8 str r0, [r7, #12] 8014a20: 60b9 str r1, [r7, #8] 8014a22: 607a str r2, [r7, #4] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8014a24: 68fb ldr r3, [r7, #12] 8014a26: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 8014a28: 6b3b ldr r3, [r7, #48] @ 0x30 8014a2a: 2b00 cmp r3, #0 8014a2c: d10b bne.n 8014a46 __asm volatile 8014a2e: f04f 0350 mov.w r3, #80 @ 0x50 8014a32: f383 8811 msr BASEPRI, r3 8014a36: f3bf 8f6f isb sy 8014a3a: f3bf 8f4f dsb sy 8014a3e: 623b str r3, [r7, #32] } 8014a40: bf00 nop 8014a42: bf00 nop 8014a44: e7fd b.n 8014a42 configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8014a46: 68bb ldr r3, [r7, #8] 8014a48: 2b00 cmp r3, #0 8014a4a: d103 bne.n 8014a54 8014a4c: 6b3b ldr r3, [r7, #48] @ 0x30 8014a4e: 6c1b ldr r3, [r3, #64] @ 0x40 8014a50: 2b00 cmp r3, #0 8014a52: d101 bne.n 8014a58 8014a54: 2301 movs r3, #1 8014a56: e000 b.n 8014a5a 8014a58: 2300 movs r3, #0 8014a5a: 2b00 cmp r3, #0 8014a5c: d10b bne.n 8014a76 __asm volatile 8014a5e: f04f 0350 mov.w r3, #80 @ 0x50 8014a62: f383 8811 msr BASEPRI, r3 8014a66: f3bf 8f6f isb sy 8014a6a: f3bf 8f4f dsb sy 8014a6e: 61fb str r3, [r7, #28] } 8014a70: bf00 nop 8014a72: bf00 nop 8014a74: e7fd b.n 8014a72 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8014a76: f002 fc97 bl 80173a8 __asm volatile 8014a7a: f3ef 8211 mrs r2, BASEPRI 8014a7e: f04f 0350 mov.w r3, #80 @ 0x50 8014a82: f383 8811 msr BASEPRI, r3 8014a86: f3bf 8f6f isb sy 8014a8a: f3bf 8f4f dsb sy 8014a8e: 61ba str r2, [r7, #24] 8014a90: 617b str r3, [r7, #20] return ulOriginalBASEPRI; 8014a92: 69bb ldr r3, [r7, #24] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8014a94: 62fb str r3, [r7, #44] @ 0x2c { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8014a96: 6b3b ldr r3, [r7, #48] @ 0x30 8014a98: 6b9b ldr r3, [r3, #56] @ 0x38 8014a9a: 62bb str r3, [r7, #40] @ 0x28 /* Cannot block in an ISR, so check there is data available. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 8014a9c: 6abb ldr r3, [r7, #40] @ 0x28 8014a9e: 2b00 cmp r3, #0 8014aa0: d02f beq.n 8014b02 { const int8_t cRxLock = pxQueue->cRxLock; 8014aa2: 6b3b ldr r3, [r7, #48] @ 0x30 8014aa4: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014aa8: f887 3027 strb.w r3, [r7, #39] @ 0x27 traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); prvCopyDataFromQueue( pxQueue, pvBuffer ); 8014aac: 68b9 ldr r1, [r7, #8] 8014aae: 6b38 ldr r0, [r7, #48] @ 0x30 8014ab0: f000 f8b6 bl 8014c20 pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 8014ab4: 6abb ldr r3, [r7, #40] @ 0x28 8014ab6: 1e5a subs r2, r3, #1 8014ab8: 6b3b ldr r3, [r7, #48] @ 0x30 8014aba: 639a str r2, [r3, #56] @ 0x38 /* If the queue is locked the event list will not be modified. Instead update the lock count so the task that unlocks the queue will know that an ISR has removed data while the queue was locked. */ if( cRxLock == queueUNLOCKED ) 8014abc: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27 8014ac0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014ac4: d112 bne.n 8014aec { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8014ac6: 6b3b ldr r3, [r7, #48] @ 0x30 8014ac8: 691b ldr r3, [r3, #16] 8014aca: 2b00 cmp r3, #0 8014acc: d016 beq.n 8014afc { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014ace: 6b3b ldr r3, [r7, #48] @ 0x30 8014ad0: 3310 adds r3, #16 8014ad2: 4618 mov r0, r3 8014ad4: f001 f806 bl 8015ae4 8014ad8: 4603 mov r3, r0 8014ada: 2b00 cmp r3, #0 8014adc: d00e beq.n 8014afc { /* The task waiting has a higher priority than us so force a context switch. */ if( pxHigherPriorityTaskWoken != NULL ) 8014ade: 687b ldr r3, [r7, #4] 8014ae0: 2b00 cmp r3, #0 8014ae2: d00b beq.n 8014afc { *pxHigherPriorityTaskWoken = pdTRUE; 8014ae4: 687b ldr r3, [r7, #4] 8014ae6: 2201 movs r2, #1 8014ae8: 601a str r2, [r3, #0] 8014aea: e007 b.n 8014afc } else { /* Increment the lock count so the task that unlocks the queue knows that data was removed while it was locked. */ pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 ); 8014aec: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8014af0: 3301 adds r3, #1 8014af2: b2db uxtb r3, r3 8014af4: b25a sxtb r2, r3 8014af6: 6b3b ldr r3, [r7, #48] @ 0x30 8014af8: f883 2044 strb.w r2, [r3, #68] @ 0x44 } xReturn = pdPASS; 8014afc: 2301 movs r3, #1 8014afe: 637b str r3, [r7, #52] @ 0x34 8014b00: e001 b.n 8014b06 } else { xReturn = pdFAIL; 8014b02: 2300 movs r3, #0 8014b04: 637b str r3, [r7, #52] @ 0x34 8014b06: 6afb ldr r3, [r7, #44] @ 0x2c 8014b08: 613b str r3, [r7, #16] __asm volatile 8014b0a: 693b ldr r3, [r7, #16] 8014b0c: f383 8811 msr BASEPRI, r3 } 8014b10: bf00 nop traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 8014b12: 6b7b ldr r3, [r7, #52] @ 0x34 } 8014b14: 4618 mov r0, r3 8014b16: 3738 adds r7, #56 @ 0x38 8014b18: 46bd mov sp, r7 8014b1a: bd80 pop {r7, pc} 08014b1c : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) { 8014b1c: b480 push {r7} 8014b1e: b085 sub sp, #20 8014b20: af00 add r7, sp, #0 8014b22: 6078 str r0, [r7, #4] priority, but the waiting task times out, then the holder should disinherit the priority - but only down to the highest priority of any other tasks that are waiting for the same mutex. For this purpose, return the priority of the highest priority task that is waiting for the mutex. */ if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) 8014b24: 687b ldr r3, [r7, #4] 8014b26: 6a5b ldr r3, [r3, #36] @ 0x24 8014b28: 2b00 cmp r3, #0 8014b2a: d006 beq.n 8014b3a { uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); 8014b2c: 687b ldr r3, [r7, #4] 8014b2e: 6b1b ldr r3, [r3, #48] @ 0x30 8014b30: 681b ldr r3, [r3, #0] 8014b32: f1c3 0338 rsb r3, r3, #56 @ 0x38 8014b36: 60fb str r3, [r7, #12] 8014b38: e001 b.n 8014b3e } else { uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; 8014b3a: 2300 movs r3, #0 8014b3c: 60fb str r3, [r7, #12] } return uxHighestPriorityOfWaitingTasks; 8014b3e: 68fb ldr r3, [r7, #12] } 8014b40: 4618 mov r0, r3 8014b42: 3714 adds r7, #20 8014b44: 46bd mov sp, r7 8014b46: f85d 7b04 ldr.w r7, [sp], #4 8014b4a: 4770 bx lr 08014b4c : #endif /* configUSE_MUTEXES */ /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) { 8014b4c: b580 push {r7, lr} 8014b4e: b086 sub sp, #24 8014b50: af00 add r7, sp, #0 8014b52: 60f8 str r0, [r7, #12] 8014b54: 60b9 str r1, [r7, #8] 8014b56: 607a str r2, [r7, #4] BaseType_t xReturn = pdFALSE; 8014b58: 2300 movs r3, #0 8014b5a: 617b str r3, [r7, #20] UBaseType_t uxMessagesWaiting; /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8014b5c: 68fb ldr r3, [r7, #12] 8014b5e: 6b9b ldr r3, [r3, #56] @ 0x38 8014b60: 613b str r3, [r7, #16] if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) 8014b62: 68fb ldr r3, [r7, #12] 8014b64: 6c1b ldr r3, [r3, #64] @ 0x40 8014b66: 2b00 cmp r3, #0 8014b68: d10d bne.n 8014b86 { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8014b6a: 68fb ldr r3, [r7, #12] 8014b6c: 681b ldr r3, [r3, #0] 8014b6e: 2b00 cmp r3, #0 8014b70: d14d bne.n 8014c0e { /* The mutex is no longer being held. */ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); 8014b72: 68fb ldr r3, [r7, #12] 8014b74: 689b ldr r3, [r3, #8] 8014b76: 4618 mov r0, r3 8014b78: f001 fa38 bl 8015fec 8014b7c: 6178 str r0, [r7, #20] pxQueue->u.xSemaphore.xMutexHolder = NULL; 8014b7e: 68fb ldr r3, [r7, #12] 8014b80: 2200 movs r2, #0 8014b82: 609a str r2, [r3, #8] 8014b84: e043 b.n 8014c0e mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_MUTEXES */ } else if( xPosition == queueSEND_TO_BACK ) 8014b86: 687b ldr r3, [r7, #4] 8014b88: 2b00 cmp r3, #0 8014b8a: d119 bne.n 8014bc0 { ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 8014b8c: 68fb ldr r3, [r7, #12] 8014b8e: 6858 ldr r0, [r3, #4] 8014b90: 68fb ldr r3, [r7, #12] 8014b92: 6c1b ldr r3, [r3, #64] @ 0x40 8014b94: 461a mov r2, r3 8014b96: 68b9 ldr r1, [r7, #8] 8014b98: f003 fd3b bl 8018612 pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 8014b9c: 68fb ldr r3, [r7, #12] 8014b9e: 685a ldr r2, [r3, #4] 8014ba0: 68fb ldr r3, [r7, #12] 8014ba2: 6c1b ldr r3, [r3, #64] @ 0x40 8014ba4: 441a add r2, r3 8014ba6: 68fb ldr r3, [r7, #12] 8014ba8: 605a str r2, [r3, #4] if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 8014baa: 68fb ldr r3, [r7, #12] 8014bac: 685a ldr r2, [r3, #4] 8014bae: 68fb ldr r3, [r7, #12] 8014bb0: 689b ldr r3, [r3, #8] 8014bb2: 429a cmp r2, r3 8014bb4: d32b bcc.n 8014c0e { pxQueue->pcWriteTo = pxQueue->pcHead; 8014bb6: 68fb ldr r3, [r7, #12] 8014bb8: 681a ldr r2, [r3, #0] 8014bba: 68fb ldr r3, [r7, #12] 8014bbc: 605a str r2, [r3, #4] 8014bbe: e026 b.n 8014c0e mtCOVERAGE_TEST_MARKER(); } } else { ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ 8014bc0: 68fb ldr r3, [r7, #12] 8014bc2: 68d8 ldr r0, [r3, #12] 8014bc4: 68fb ldr r3, [r7, #12] 8014bc6: 6c1b ldr r3, [r3, #64] @ 0x40 8014bc8: 461a mov r2, r3 8014bca: 68b9 ldr r1, [r7, #8] 8014bcc: f003 fd21 bl 8018612 pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; 8014bd0: 68fb ldr r3, [r7, #12] 8014bd2: 68da ldr r2, [r3, #12] 8014bd4: 68fb ldr r3, [r7, #12] 8014bd6: 6c1b ldr r3, [r3, #64] @ 0x40 8014bd8: 425b negs r3, r3 8014bda: 441a add r2, r3 8014bdc: 68fb ldr r3, [r7, #12] 8014bde: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 8014be0: 68fb ldr r3, [r7, #12] 8014be2: 68da ldr r2, [r3, #12] 8014be4: 68fb ldr r3, [r7, #12] 8014be6: 681b ldr r3, [r3, #0] 8014be8: 429a cmp r2, r3 8014bea: d207 bcs.n 8014bfc { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); 8014bec: 68fb ldr r3, [r7, #12] 8014bee: 689a ldr r2, [r3, #8] 8014bf0: 68fb ldr r3, [r7, #12] 8014bf2: 6c1b ldr r3, [r3, #64] @ 0x40 8014bf4: 425b negs r3, r3 8014bf6: 441a add r2, r3 8014bf8: 68fb ldr r3, [r7, #12] 8014bfa: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } if( xPosition == queueOVERWRITE ) 8014bfc: 687b ldr r3, [r7, #4] 8014bfe: 2b02 cmp r3, #2 8014c00: d105 bne.n 8014c0e { if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 8014c02: 693b ldr r3, [r7, #16] 8014c04: 2b00 cmp r3, #0 8014c06: d002 beq.n 8014c0e { /* An item is not being added but overwritten, so subtract one from the recorded number of items in the queue so when one is added again below the number of recorded items remains correct. */ --uxMessagesWaiting; 8014c08: 693b ldr r3, [r7, #16] 8014c0a: 3b01 subs r3, #1 8014c0c: 613b str r3, [r7, #16] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 8014c0e: 693b ldr r3, [r7, #16] 8014c10: 1c5a adds r2, r3, #1 8014c12: 68fb ldr r3, [r7, #12] 8014c14: 639a str r2, [r3, #56] @ 0x38 return xReturn; 8014c16: 697b ldr r3, [r7, #20] } 8014c18: 4618 mov r0, r3 8014c1a: 3718 adds r7, #24 8014c1c: 46bd mov sp, r7 8014c1e: bd80 pop {r7, pc} 08014c20 : /*-----------------------------------------------------------*/ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) { 8014c20: b580 push {r7, lr} 8014c22: b082 sub sp, #8 8014c24: af00 add r7, sp, #0 8014c26: 6078 str r0, [r7, #4] 8014c28: 6039 str r1, [r7, #0] if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) 8014c2a: 687b ldr r3, [r7, #4] 8014c2c: 6c1b ldr r3, [r3, #64] @ 0x40 8014c2e: 2b00 cmp r3, #0 8014c30: d018 beq.n 8014c64 { pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 8014c32: 687b ldr r3, [r7, #4] 8014c34: 68da ldr r2, [r3, #12] 8014c36: 687b ldr r3, [r7, #4] 8014c38: 6c1b ldr r3, [r3, #64] @ 0x40 8014c3a: 441a add r2, r3 8014c3c: 687b ldr r3, [r7, #4] 8014c3e: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 8014c40: 687b ldr r3, [r7, #4] 8014c42: 68da ldr r2, [r3, #12] 8014c44: 687b ldr r3, [r7, #4] 8014c46: 689b ldr r3, [r3, #8] 8014c48: 429a cmp r2, r3 8014c4a: d303 bcc.n 8014c54 { pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; 8014c4c: 687b ldr r3, [r7, #4] 8014c4e: 681a ldr r2, [r3, #0] 8014c50: 687b ldr r3, [r7, #4] 8014c52: 60da str r2, [r3, #12] } else { mtCOVERAGE_TEST_MARKER(); } ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 8014c54: 687b ldr r3, [r7, #4] 8014c56: 68d9 ldr r1, [r3, #12] 8014c58: 687b ldr r3, [r7, #4] 8014c5a: 6c1b ldr r3, [r3, #64] @ 0x40 8014c5c: 461a mov r2, r3 8014c5e: 6838 ldr r0, [r7, #0] 8014c60: f003 fcd7 bl 8018612 } } 8014c64: bf00 nop 8014c66: 3708 adds r7, #8 8014c68: 46bd mov sp, r7 8014c6a: bd80 pop {r7, pc} 08014c6c : /*-----------------------------------------------------------*/ static void prvUnlockQueue( Queue_t * const pxQueue ) { 8014c6c: b580 push {r7, lr} 8014c6e: b084 sub sp, #16 8014c70: af00 add r7, sp, #0 8014c72: 6078 str r0, [r7, #4] /* The lock counts contains the number of extra data items placed or removed from the queue while the queue was locked. When a queue is locked items can be added or removed, but the event lists cannot be updated. */ taskENTER_CRITICAL(); 8014c74: f002 fab8 bl 80171e8 { int8_t cTxLock = pxQueue->cTxLock; 8014c78: 687b ldr r3, [r7, #4] 8014c7a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014c7e: 73fb strb r3, [r7, #15] /* See if data was added to the queue while it was locked. */ while( cTxLock > queueLOCKED_UNMODIFIED ) 8014c80: e011 b.n 8014ca6 } #else /* configUSE_QUEUE_SETS */ { /* Tasks that are removed from the event list will get added to the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8014c82: 687b ldr r3, [r7, #4] 8014c84: 6a5b ldr r3, [r3, #36] @ 0x24 8014c86: 2b00 cmp r3, #0 8014c88: d012 beq.n 8014cb0 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8014c8a: 687b ldr r3, [r7, #4] 8014c8c: 3324 adds r3, #36 @ 0x24 8014c8e: 4618 mov r0, r3 8014c90: f000 ff28 bl 8015ae4 8014c94: 4603 mov r3, r0 8014c96: 2b00 cmp r3, #0 8014c98: d001 beq.n 8014c9e { /* The task waiting has a higher priority so record that a context switch is required. */ vTaskMissedYield(); 8014c9a: f001 f829 bl 8015cf0 break; } } #endif /* configUSE_QUEUE_SETS */ --cTxLock; 8014c9e: 7bfb ldrb r3, [r7, #15] 8014ca0: 3b01 subs r3, #1 8014ca2: b2db uxtb r3, r3 8014ca4: 73fb strb r3, [r7, #15] while( cTxLock > queueLOCKED_UNMODIFIED ) 8014ca6: f997 300f ldrsb.w r3, [r7, #15] 8014caa: 2b00 cmp r3, #0 8014cac: dce9 bgt.n 8014c82 8014cae: e000 b.n 8014cb2 break; 8014cb0: bf00 nop } pxQueue->cTxLock = queueUNLOCKED; 8014cb2: 687b ldr r3, [r7, #4] 8014cb4: 22ff movs r2, #255 @ 0xff 8014cb6: f883 2045 strb.w r2, [r3, #69] @ 0x45 } taskEXIT_CRITICAL(); 8014cba: f002 fac7 bl 801724c /* Do the same for the Rx lock. */ taskENTER_CRITICAL(); 8014cbe: f002 fa93 bl 80171e8 { int8_t cRxLock = pxQueue->cRxLock; 8014cc2: 687b ldr r3, [r7, #4] 8014cc4: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014cc8: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 8014cca: e011 b.n 8014cf0 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8014ccc: 687b ldr r3, [r7, #4] 8014cce: 691b ldr r3, [r3, #16] 8014cd0: 2b00 cmp r3, #0 8014cd2: d012 beq.n 8014cfa { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014cd4: 687b ldr r3, [r7, #4] 8014cd6: 3310 adds r3, #16 8014cd8: 4618 mov r0, r3 8014cda: f000 ff03 bl 8015ae4 8014cde: 4603 mov r3, r0 8014ce0: 2b00 cmp r3, #0 8014ce2: d001 beq.n 8014ce8 { vTaskMissedYield(); 8014ce4: f001 f804 bl 8015cf0 else { mtCOVERAGE_TEST_MARKER(); } --cRxLock; 8014ce8: 7bbb ldrb r3, [r7, #14] 8014cea: 3b01 subs r3, #1 8014cec: b2db uxtb r3, r3 8014cee: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 8014cf0: f997 300e ldrsb.w r3, [r7, #14] 8014cf4: 2b00 cmp r3, #0 8014cf6: dce9 bgt.n 8014ccc 8014cf8: e000 b.n 8014cfc } else { break; 8014cfa: bf00 nop } } pxQueue->cRxLock = queueUNLOCKED; 8014cfc: 687b ldr r3, [r7, #4] 8014cfe: 22ff movs r2, #255 @ 0xff 8014d00: f883 2044 strb.w r2, [r3, #68] @ 0x44 } taskEXIT_CRITICAL(); 8014d04: f002 faa2 bl 801724c } 8014d08: bf00 nop 8014d0a: 3710 adds r7, #16 8014d0c: 46bd mov sp, r7 8014d0e: bd80 pop {r7, pc} 08014d10 : /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) { 8014d10: b580 push {r7, lr} 8014d12: b084 sub sp, #16 8014d14: af00 add r7, sp, #0 8014d16: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8014d18: f002 fa66 bl 80171e8 { if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) 8014d1c: 687b ldr r3, [r7, #4] 8014d1e: 6b9b ldr r3, [r3, #56] @ 0x38 8014d20: 2b00 cmp r3, #0 8014d22: d102 bne.n 8014d2a { xReturn = pdTRUE; 8014d24: 2301 movs r3, #1 8014d26: 60fb str r3, [r7, #12] 8014d28: e001 b.n 8014d2e } else { xReturn = pdFALSE; 8014d2a: 2300 movs r3, #0 8014d2c: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8014d2e: f002 fa8d bl 801724c return xReturn; 8014d32: 68fb ldr r3, [r7, #12] } 8014d34: 4618 mov r0, r3 8014d36: 3710 adds r7, #16 8014d38: 46bd mov sp, r7 8014d3a: bd80 pop {r7, pc} 08014d3c : return xReturn; } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) { 8014d3c: b580 push {r7, lr} 8014d3e: b084 sub sp, #16 8014d40: af00 add r7, sp, #0 8014d42: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8014d44: f002 fa50 bl 80171e8 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) 8014d48: 687b ldr r3, [r7, #4] 8014d4a: 6b9a ldr r2, [r3, #56] @ 0x38 8014d4c: 687b ldr r3, [r7, #4] 8014d4e: 6bdb ldr r3, [r3, #60] @ 0x3c 8014d50: 429a cmp r2, r3 8014d52: d102 bne.n 8014d5a { xReturn = pdTRUE; 8014d54: 2301 movs r3, #1 8014d56: 60fb str r3, [r7, #12] 8014d58: e001 b.n 8014d5e } else { xReturn = pdFALSE; 8014d5a: 2300 movs r3, #0 8014d5c: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8014d5e: f002 fa75 bl 801724c return xReturn; 8014d62: 68fb ldr r3, [r7, #12] } 8014d64: 4618 mov r0, r3 8014d66: 3710 adds r7, #16 8014d68: 46bd mov sp, r7 8014d6a: bd80 pop {r7, pc} 08014d6c : /*-----------------------------------------------------------*/ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ { 8014d6c: b480 push {r7} 8014d6e: b085 sub sp, #20 8014d70: af00 add r7, sp, #0 8014d72: 6078 str r0, [r7, #4] 8014d74: 6039 str r1, [r7, #0] UBaseType_t ux; /* See if there is an empty space in the registry. A NULL name denotes a free slot. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8014d76: 2300 movs r3, #0 8014d78: 60fb str r3, [r7, #12] 8014d7a: e014 b.n 8014da6 { if( xQueueRegistry[ ux ].pcQueueName == NULL ) 8014d7c: 4a0f ldr r2, [pc, #60] @ (8014dbc ) 8014d7e: 68fb ldr r3, [r7, #12] 8014d80: f852 3033 ldr.w r3, [r2, r3, lsl #3] 8014d84: 2b00 cmp r3, #0 8014d86: d10b bne.n 8014da0 { /* Store the information on this queue. */ xQueueRegistry[ ux ].pcQueueName = pcQueueName; 8014d88: 490c ldr r1, [pc, #48] @ (8014dbc ) 8014d8a: 68fb ldr r3, [r7, #12] 8014d8c: 683a ldr r2, [r7, #0] 8014d8e: f841 2033 str.w r2, [r1, r3, lsl #3] xQueueRegistry[ ux ].xHandle = xQueue; 8014d92: 4a0a ldr r2, [pc, #40] @ (8014dbc ) 8014d94: 68fb ldr r3, [r7, #12] 8014d96: 00db lsls r3, r3, #3 8014d98: 4413 add r3, r2 8014d9a: 687a ldr r2, [r7, #4] 8014d9c: 605a str r2, [r3, #4] traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); break; 8014d9e: e006 b.n 8014dae for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8014da0: 68fb ldr r3, [r7, #12] 8014da2: 3301 adds r3, #1 8014da4: 60fb str r3, [r7, #12] 8014da6: 68fb ldr r3, [r7, #12] 8014da8: 2b07 cmp r3, #7 8014daa: d9e7 bls.n 8014d7c else { mtCOVERAGE_TEST_MARKER(); } } } 8014dac: bf00 nop 8014dae: bf00 nop 8014db0: 3714 adds r7, #20 8014db2: 46bd mov sp, r7 8014db4: f85d 7b04 ldr.w r7, [sp], #4 8014db8: 4770 bx lr 8014dba: bf00 nop 8014dbc: 24002b14 .word 0x24002b14 08014dc0 : /*-----------------------------------------------------------*/ #if ( configUSE_TIMERS == 1 ) void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 8014dc0: b580 push {r7, lr} 8014dc2: b086 sub sp, #24 8014dc4: af00 add r7, sp, #0 8014dc6: 60f8 str r0, [r7, #12] 8014dc8: 60b9 str r1, [r7, #8] 8014dca: 607a str r2, [r7, #4] Queue_t * const pxQueue = xQueue; 8014dcc: 68fb ldr r3, [r7, #12] 8014dce: 617b str r3, [r7, #20] will not actually cause the task to block, just place it on a blocked list. It will not block until the scheduler is unlocked - at which time a yield will be performed. If an item is added to the queue while the queue is locked, and the calling task blocks on the queue, then the calling task will be immediately unblocked when the queue is unlocked. */ prvLockQueue( pxQueue ); 8014dd0: f002 fa0a bl 80171e8 8014dd4: 697b ldr r3, [r7, #20] 8014dd6: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014dda: b25b sxtb r3, r3 8014ddc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014de0: d103 bne.n 8014dea 8014de2: 697b ldr r3, [r7, #20] 8014de4: 2200 movs r2, #0 8014de6: f883 2044 strb.w r2, [r3, #68] @ 0x44 8014dea: 697b ldr r3, [r7, #20] 8014dec: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014df0: b25b sxtb r3, r3 8014df2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014df6: d103 bne.n 8014e00 8014df8: 697b ldr r3, [r7, #20] 8014dfa: 2200 movs r2, #0 8014dfc: f883 2045 strb.w r2, [r3, #69] @ 0x45 8014e00: f002 fa24 bl 801724c if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) 8014e04: 697b ldr r3, [r7, #20] 8014e06: 6b9b ldr r3, [r3, #56] @ 0x38 8014e08: 2b00 cmp r3, #0 8014e0a: d106 bne.n 8014e1a { /* There is nothing in the queue, block for the specified period. */ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); 8014e0c: 697b ldr r3, [r7, #20] 8014e0e: 3324 adds r3, #36 @ 0x24 8014e10: 687a ldr r2, [r7, #4] 8014e12: 68b9 ldr r1, [r7, #8] 8014e14: 4618 mov r0, r3 8014e16: f000 fe39 bl 8015a8c } else { mtCOVERAGE_TEST_MARKER(); } prvUnlockQueue( pxQueue ); 8014e1a: 6978 ldr r0, [r7, #20] 8014e1c: f7ff ff26 bl 8014c6c } 8014e20: bf00 nop 8014e22: 3718 adds r7, #24 8014e24: 46bd mov sp, r7 8014e26: bd80 pop {r7, pc} 08014e28 : return xReturn; } /*-----------------------------------------------------------*/ size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) { 8014e28: b480 push {r7} 8014e2a: b087 sub sp, #28 8014e2c: af00 add r7, sp, #0 8014e2e: 6078 str r0, [r7, #4] const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 8014e30: 687b ldr r3, [r7, #4] 8014e32: 613b str r3, [r7, #16] size_t xSpace; configASSERT( pxStreamBuffer ); 8014e34: 693b ldr r3, [r7, #16] 8014e36: 2b00 cmp r3, #0 8014e38: d10b bne.n 8014e52 __asm volatile 8014e3a: f04f 0350 mov.w r3, #80 @ 0x50 8014e3e: f383 8811 msr BASEPRI, r3 8014e42: f3bf 8f6f isb sy 8014e46: f3bf 8f4f dsb sy 8014e4a: 60fb str r3, [r7, #12] } 8014e4c: bf00 nop 8014e4e: bf00 nop 8014e50: e7fd b.n 8014e4e xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; 8014e52: 693b ldr r3, [r7, #16] 8014e54: 689a ldr r2, [r3, #8] 8014e56: 693b ldr r3, [r7, #16] 8014e58: 681b ldr r3, [r3, #0] 8014e5a: 4413 add r3, r2 8014e5c: 617b str r3, [r7, #20] xSpace -= pxStreamBuffer->xHead; 8014e5e: 693b ldr r3, [r7, #16] 8014e60: 685b ldr r3, [r3, #4] 8014e62: 697a ldr r2, [r7, #20] 8014e64: 1ad3 subs r3, r2, r3 8014e66: 617b str r3, [r7, #20] xSpace -= ( size_t ) 1; 8014e68: 697b ldr r3, [r7, #20] 8014e6a: 3b01 subs r3, #1 8014e6c: 617b str r3, [r7, #20] if( xSpace >= pxStreamBuffer->xLength ) 8014e6e: 693b ldr r3, [r7, #16] 8014e70: 689b ldr r3, [r3, #8] 8014e72: 697a ldr r2, [r7, #20] 8014e74: 429a cmp r2, r3 8014e76: d304 bcc.n 8014e82 { xSpace -= pxStreamBuffer->xLength; 8014e78: 693b ldr r3, [r7, #16] 8014e7a: 689b ldr r3, [r3, #8] 8014e7c: 697a ldr r2, [r7, #20] 8014e7e: 1ad3 subs r3, r2, r3 8014e80: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xSpace; 8014e82: 697b ldr r3, [r7, #20] } 8014e84: 4618 mov r0, r3 8014e86: 371c adds r7, #28 8014e88: 46bd mov sp, r7 8014e8a: f85d 7b04 ldr.w r7, [sp], #4 8014e8e: 4770 bx lr 08014e90 : size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) { 8014e90: b580 push {r7, lr} 8014e92: b090 sub sp, #64 @ 0x40 8014e94: af02 add r7, sp, #8 8014e96: 60f8 str r0, [r7, #12] 8014e98: 60b9 str r1, [r7, #8] 8014e9a: 607a str r2, [r7, #4] 8014e9c: 603b str r3, [r7, #0] StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 8014e9e: 68fb ldr r3, [r7, #12] 8014ea0: 62fb str r3, [r7, #44] @ 0x2c size_t xReturn, xSpace = 0; 8014ea2: 2300 movs r3, #0 8014ea4: 637b str r3, [r7, #52] @ 0x34 size_t xRequiredSpace = xDataLengthBytes; 8014ea6: 687b ldr r3, [r7, #4] 8014ea8: 633b str r3, [r7, #48] @ 0x30 TimeOut_t xTimeOut; configASSERT( pvTxData ); 8014eaa: 68bb ldr r3, [r7, #8] 8014eac: 2b00 cmp r3, #0 8014eae: d10b bne.n 8014ec8 __asm volatile 8014eb0: f04f 0350 mov.w r3, #80 @ 0x50 8014eb4: f383 8811 msr BASEPRI, r3 8014eb8: f3bf 8f6f isb sy 8014ebc: f3bf 8f4f dsb sy 8014ec0: 627b str r3, [r7, #36] @ 0x24 } 8014ec2: bf00 nop 8014ec4: bf00 nop 8014ec6: e7fd b.n 8014ec4 configASSERT( pxStreamBuffer ); 8014ec8: 6afb ldr r3, [r7, #44] @ 0x2c 8014eca: 2b00 cmp r3, #0 8014ecc: d10b bne.n 8014ee6 __asm volatile 8014ece: f04f 0350 mov.w r3, #80 @ 0x50 8014ed2: f383 8811 msr BASEPRI, r3 8014ed6: f3bf 8f6f isb sy 8014eda: f3bf 8f4f dsb sy 8014ede: 623b str r3, [r7, #32] } 8014ee0: bf00 nop 8014ee2: bf00 nop 8014ee4: e7fd b.n 8014ee2 /* This send function is used to write to both message buffers and stream buffers. If this is a message buffer then the space needed must be increased by the amount of bytes needed to store the length of the message. */ if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) 8014ee6: 6afb ldr r3, [r7, #44] @ 0x2c 8014ee8: 7f1b ldrb r3, [r3, #28] 8014eea: f003 0301 and.w r3, r3, #1 8014eee: 2b00 cmp r3, #0 8014ef0: d012 beq.n 8014f18 { xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; 8014ef2: 6b3b ldr r3, [r7, #48] @ 0x30 8014ef4: 3304 adds r3, #4 8014ef6: 633b str r3, [r7, #48] @ 0x30 /* Overflow? */ configASSERT( xRequiredSpace > xDataLengthBytes ); 8014ef8: 6b3a ldr r2, [r7, #48] @ 0x30 8014efa: 687b ldr r3, [r7, #4] 8014efc: 429a cmp r2, r3 8014efe: d80b bhi.n 8014f18 __asm volatile 8014f00: f04f 0350 mov.w r3, #80 @ 0x50 8014f04: f383 8811 msr BASEPRI, r3 8014f08: f3bf 8f6f isb sy 8014f0c: f3bf 8f4f dsb sy 8014f10: 61fb str r3, [r7, #28] } 8014f12: bf00 nop 8014f14: bf00 nop 8014f16: e7fd b.n 8014f14 else { mtCOVERAGE_TEST_MARKER(); } if( xTicksToWait != ( TickType_t ) 0 ) 8014f18: 683b ldr r3, [r7, #0] 8014f1a: 2b00 cmp r3, #0 8014f1c: d03f beq.n 8014f9e { vTaskSetTimeOutState( &xTimeOut ); 8014f1e: f107 0310 add.w r3, r7, #16 8014f22: 4618 mov r0, r3 8014f24: f000 fe42 bl 8015bac do { /* Wait until the required number of bytes are free in the message buffer. */ taskENTER_CRITICAL(); 8014f28: f002 f95e bl 80171e8 { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 8014f2c: 6af8 ldr r0, [r7, #44] @ 0x2c 8014f2e: f7ff ff7b bl 8014e28 8014f32: 6378 str r0, [r7, #52] @ 0x34 if( xSpace < xRequiredSpace ) 8014f34: 6b7a ldr r2, [r7, #52] @ 0x34 8014f36: 6b3b ldr r3, [r7, #48] @ 0x30 8014f38: 429a cmp r2, r3 8014f3a: d218 bcs.n 8014f6e { /* Clear notification state as going to wait for space. */ ( void ) xTaskNotifyStateClear( NULL ); 8014f3c: 2000 movs r0, #0 8014f3e: f001 fb65 bl 801660c /* Should only be one writer. */ configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL ); 8014f42: 6afb ldr r3, [r7, #44] @ 0x2c 8014f44: 695b ldr r3, [r3, #20] 8014f46: 2b00 cmp r3, #0 8014f48: d00b beq.n 8014f62 __asm volatile 8014f4a: f04f 0350 mov.w r3, #80 @ 0x50 8014f4e: f383 8811 msr BASEPRI, r3 8014f52: f3bf 8f6f isb sy 8014f56: f3bf 8f4f dsb sy 8014f5a: 61bb str r3, [r7, #24] } 8014f5c: bf00 nop 8014f5e: bf00 nop 8014f60: e7fd b.n 8014f5e pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle(); 8014f62: f000 ffad bl 8015ec0 8014f66: 4602 mov r2, r0 8014f68: 6afb ldr r3, [r7, #44] @ 0x2c 8014f6a: 615a str r2, [r3, #20] 8014f6c: e002 b.n 8014f74 } else { taskEXIT_CRITICAL(); 8014f6e: f002 f96d bl 801724c break; 8014f72: e014 b.n 8014f9e } } taskEXIT_CRITICAL(); 8014f74: f002 f96a bl 801724c traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ); ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); 8014f78: 683b ldr r3, [r7, #0] 8014f7a: 2200 movs r2, #0 8014f7c: 2100 movs r1, #0 8014f7e: 2000 movs r0, #0 8014f80: f001 f93c bl 80161fc pxStreamBuffer->xTaskWaitingToSend = NULL; 8014f84: 6afb ldr r3, [r7, #44] @ 0x2c 8014f86: 2200 movs r2, #0 8014f88: 615a str r2, [r3, #20] } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); 8014f8a: 463a mov r2, r7 8014f8c: f107 0310 add.w r3, r7, #16 8014f90: 4611 mov r1, r2 8014f92: 4618 mov r0, r3 8014f94: f000 fe48 bl 8015c28 8014f98: 4603 mov r3, r0 8014f9a: 2b00 cmp r3, #0 8014f9c: d0c4 beq.n 8014f28 else { mtCOVERAGE_TEST_MARKER(); } if( xSpace == ( size_t ) 0 ) 8014f9e: 6b7b ldr r3, [r7, #52] @ 0x34 8014fa0: 2b00 cmp r3, #0 8014fa2: d103 bne.n 8014fac { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 8014fa4: 6af8 ldr r0, [r7, #44] @ 0x2c 8014fa6: f7ff ff3f bl 8014e28 8014faa: 6378 str r0, [r7, #52] @ 0x34 else { mtCOVERAGE_TEST_MARKER(); } xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); 8014fac: 6b3b ldr r3, [r7, #48] @ 0x30 8014fae: 9300 str r3, [sp, #0] 8014fb0: 6b7b ldr r3, [r7, #52] @ 0x34 8014fb2: 687a ldr r2, [r7, #4] 8014fb4: 68b9 ldr r1, [r7, #8] 8014fb6: 6af8 ldr r0, [r7, #44] @ 0x2c 8014fb8: f000 f823 bl 8015002 8014fbc: 62b8 str r0, [r7, #40] @ 0x28 if( xReturn > ( size_t ) 0 ) 8014fbe: 6abb ldr r3, [r7, #40] @ 0x28 8014fc0: 2b00 cmp r3, #0 8014fc2: d019 beq.n 8014ff8 { traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn ); /* Was a task waiting for the data? */ if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) 8014fc4: 6af8 ldr r0, [r7, #44] @ 0x2c 8014fc6: f000 f8ce bl 8015166 8014fca: 4602 mov r2, r0 8014fcc: 6afb ldr r3, [r7, #44] @ 0x2c 8014fce: 68db ldr r3, [r3, #12] 8014fd0: 429a cmp r2, r3 8014fd2: d311 bcc.n 8014ff8 { sbSEND_COMPLETED( pxStreamBuffer ); 8014fd4: f000 fb4a bl 801566c 8014fd8: 6afb ldr r3, [r7, #44] @ 0x2c 8014fda: 691b ldr r3, [r3, #16] 8014fdc: 2b00 cmp r3, #0 8014fde: d009 beq.n 8014ff4 8014fe0: 6afb ldr r3, [r7, #44] @ 0x2c 8014fe2: 6918 ldr r0, [r3, #16] 8014fe4: 2300 movs r3, #0 8014fe6: 2200 movs r2, #0 8014fe8: 2100 movs r1, #0 8014fea: f001 f967 bl 80162bc 8014fee: 6afb ldr r3, [r7, #44] @ 0x2c 8014ff0: 2200 movs r2, #0 8014ff2: 611a str r2, [r3, #16] 8014ff4: f000 fb48 bl 8015688 { mtCOVERAGE_TEST_MARKER(); traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ); } return xReturn; 8014ff8: 6abb ldr r3, [r7, #40] @ 0x28 } 8014ffa: 4618 mov r0, r3 8014ffc: 3738 adds r7, #56 @ 0x38 8014ffe: 46bd mov sp, r7 8015000: bd80 pop {r7, pc} 08015002 : static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, const void * pvTxData, size_t xDataLengthBytes, size_t xSpace, size_t xRequiredSpace ) { 8015002: b580 push {r7, lr} 8015004: b086 sub sp, #24 8015006: af00 add r7, sp, #0 8015008: 60f8 str r0, [r7, #12] 801500a: 60b9 str r1, [r7, #8] 801500c: 607a str r2, [r7, #4] 801500e: 603b str r3, [r7, #0] BaseType_t xShouldWrite; size_t xReturn; if( xSpace == ( size_t ) 0 ) 8015010: 683b ldr r3, [r7, #0] 8015012: 2b00 cmp r3, #0 8015014: d102 bne.n 801501c { /* Doesn't matter if this is a stream buffer or a message buffer, there is no space to write. */ xShouldWrite = pdFALSE; 8015016: 2300 movs r3, #0 8015018: 617b str r3, [r7, #20] 801501a: e01d b.n 8015058 } else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 ) 801501c: 68fb ldr r3, [r7, #12] 801501e: 7f1b ldrb r3, [r3, #28] 8015020: f003 0301 and.w r3, r3, #1 8015024: 2b00 cmp r3, #0 8015026: d108 bne.n 801503a { /* This is a stream buffer, as opposed to a message buffer, so writing a stream of bytes rather than discrete messages. Write as many bytes as possible. */ xShouldWrite = pdTRUE; 8015028: 2301 movs r3, #1 801502a: 617b str r3, [r7, #20] xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); 801502c: 687a ldr r2, [r7, #4] 801502e: 683b ldr r3, [r7, #0] 8015030: 4293 cmp r3, r2 8015032: bf28 it cs 8015034: 4613 movcs r3, r2 8015036: 607b str r3, [r7, #4] 8015038: e00e b.n 8015058 } else if( xSpace >= xRequiredSpace ) 801503a: 683a ldr r2, [r7, #0] 801503c: 6a3b ldr r3, [r7, #32] 801503e: 429a cmp r2, r3 8015040: d308 bcc.n 8015054 { /* This is a message buffer, as opposed to a stream buffer, and there is enough space to write both the message length and the message itself into the buffer. Start by writing the length of the data, the data itself will be written later in this function. */ xShouldWrite = pdTRUE; 8015042: 2301 movs r3, #1 8015044: 617b str r3, [r7, #20] ( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH ); 8015046: 1d3b adds r3, r7, #4 8015048: 2204 movs r2, #4 801504a: 4619 mov r1, r3 801504c: 68f8 ldr r0, [r7, #12] 801504e: f000 f815 bl 801507c 8015052: e001 b.n 8015058 } else { /* There is space available, but not enough space. */ xShouldWrite = pdFALSE; 8015054: 2300 movs r3, #0 8015056: 617b str r3, [r7, #20] } if( xShouldWrite != pdFALSE ) 8015058: 697b ldr r3, [r7, #20] 801505a: 2b00 cmp r3, #0 801505c: d007 beq.n 801506e { /* Writes the data itself. */ xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */ 801505e: 687b ldr r3, [r7, #4] 8015060: 461a mov r2, r3 8015062: 68b9 ldr r1, [r7, #8] 8015064: 68f8 ldr r0, [r7, #12] 8015066: f000 f809 bl 801507c 801506a: 6138 str r0, [r7, #16] 801506c: e001 b.n 8015072 } else { xReturn = 0; 801506e: 2300 movs r3, #0 8015070: 613b str r3, [r7, #16] } return xReturn; 8015072: 693b ldr r3, [r7, #16] } 8015074: 4618 mov r0, r3 8015076: 3718 adds r7, #24 8015078: 46bd mov sp, r7 801507a: bd80 pop {r7, pc} 0801507c : return xReturn; } /*-----------------------------------------------------------*/ static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) { 801507c: b580 push {r7, lr} 801507e: b08a sub sp, #40 @ 0x28 8015080: af00 add r7, sp, #0 8015082: 60f8 str r0, [r7, #12] 8015084: 60b9 str r1, [r7, #8] 8015086: 607a str r2, [r7, #4] size_t xNextHead, xFirstLength; configASSERT( xCount > ( size_t ) 0 ); 8015088: 687b ldr r3, [r7, #4] 801508a: 2b00 cmp r3, #0 801508c: d10b bne.n 80150a6 __asm volatile 801508e: f04f 0350 mov.w r3, #80 @ 0x50 8015092: f383 8811 msr BASEPRI, r3 8015096: f3bf 8f6f isb sy 801509a: f3bf 8f4f dsb sy 801509e: 61fb str r3, [r7, #28] } 80150a0: bf00 nop 80150a2: bf00 nop 80150a4: e7fd b.n 80150a2 xNextHead = pxStreamBuffer->xHead; 80150a6: 68fb ldr r3, [r7, #12] 80150a8: 685b ldr r3, [r3, #4] 80150aa: 627b str r3, [r7, #36] @ 0x24 /* Calculate the number of bytes that can be added in the first write - which may be less than the total number of bytes that need to be added if the buffer will wrap back to the beginning. */ xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount ); 80150ac: 68fb ldr r3, [r7, #12] 80150ae: 689a ldr r2, [r3, #8] 80150b0: 6a7b ldr r3, [r7, #36] @ 0x24 80150b2: 1ad3 subs r3, r2, r3 80150b4: 687a ldr r2, [r7, #4] 80150b6: 4293 cmp r3, r2 80150b8: bf28 it cs 80150ba: 4613 movcs r3, r2 80150bc: 623b str r3, [r7, #32] /* Write as many bytes as can be written in the first write. */ configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength ); 80150be: 6a7a ldr r2, [r7, #36] @ 0x24 80150c0: 6a3b ldr r3, [r7, #32] 80150c2: 441a add r2, r3 80150c4: 68fb ldr r3, [r7, #12] 80150c6: 689b ldr r3, [r3, #8] 80150c8: 429a cmp r2, r3 80150ca: d90b bls.n 80150e4 __asm volatile 80150cc: f04f 0350 mov.w r3, #80 @ 0x50 80150d0: f383 8811 msr BASEPRI, r3 80150d4: f3bf 8f6f isb sy 80150d8: f3bf 8f4f dsb sy 80150dc: 61bb str r3, [r7, #24] } 80150de: bf00 nop 80150e0: bf00 nop 80150e2: e7fd b.n 80150e0 ( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 80150e4: 68fb ldr r3, [r7, #12] 80150e6: 699a ldr r2, [r3, #24] 80150e8: 6a7b ldr r3, [r7, #36] @ 0x24 80150ea: 4413 add r3, r2 80150ec: 6a3a ldr r2, [r7, #32] 80150ee: 68b9 ldr r1, [r7, #8] 80150f0: 4618 mov r0, r3 80150f2: f003 fa8e bl 8018612 /* If the number of bytes written was less than the number that could be written in the first write... */ if( xCount > xFirstLength ) 80150f6: 687a ldr r2, [r7, #4] 80150f8: 6a3b ldr r3, [r7, #32] 80150fa: 429a cmp r2, r3 80150fc: d91d bls.n 801513a { /* ...then write the remaining bytes to the start of the buffer. */ configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength ); 80150fe: 687a ldr r2, [r7, #4] 8015100: 6a3b ldr r3, [r7, #32] 8015102: 1ad2 subs r2, r2, r3 8015104: 68fb ldr r3, [r7, #12] 8015106: 689b ldr r3, [r3, #8] 8015108: 429a cmp r2, r3 801510a: d90b bls.n 8015124 __asm volatile 801510c: f04f 0350 mov.w r3, #80 @ 0x50 8015110: f383 8811 msr BASEPRI, r3 8015114: f3bf 8f6f isb sy 8015118: f3bf 8f4f dsb sy 801511c: 617b str r3, [r7, #20] } 801511e: bf00 nop 8015120: bf00 nop 8015122: e7fd b.n 8015120 ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 8015124: 68fb ldr r3, [r7, #12] 8015126: 6998 ldr r0, [r3, #24] 8015128: 68ba ldr r2, [r7, #8] 801512a: 6a3b ldr r3, [r7, #32] 801512c: 18d1 adds r1, r2, r3 801512e: 687a ldr r2, [r7, #4] 8015130: 6a3b ldr r3, [r7, #32] 8015132: 1ad3 subs r3, r2, r3 8015134: 461a mov r2, r3 8015136: f003 fa6c bl 8018612 else { mtCOVERAGE_TEST_MARKER(); } xNextHead += xCount; 801513a: 6a7a ldr r2, [r7, #36] @ 0x24 801513c: 687b ldr r3, [r7, #4] 801513e: 4413 add r3, r2 8015140: 627b str r3, [r7, #36] @ 0x24 if( xNextHead >= pxStreamBuffer->xLength ) 8015142: 68fb ldr r3, [r7, #12] 8015144: 689b ldr r3, [r3, #8] 8015146: 6a7a ldr r2, [r7, #36] @ 0x24 8015148: 429a cmp r2, r3 801514a: d304 bcc.n 8015156 { xNextHead -= pxStreamBuffer->xLength; 801514c: 68fb ldr r3, [r7, #12] 801514e: 689b ldr r3, [r3, #8] 8015150: 6a7a ldr r2, [r7, #36] @ 0x24 8015152: 1ad3 subs r3, r2, r3 8015154: 627b str r3, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } pxStreamBuffer->xHead = xNextHead; 8015156: 68fb ldr r3, [r7, #12] 8015158: 6a7a ldr r2, [r7, #36] @ 0x24 801515a: 605a str r2, [r3, #4] return xCount; 801515c: 687b ldr r3, [r7, #4] } 801515e: 4618 mov r0, r3 8015160: 3728 adds r7, #40 @ 0x28 8015162: 46bd mov sp, r7 8015164: bd80 pop {r7, pc} 08015166 : return xCount; } /*-----------------------------------------------------------*/ static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) { 8015166: b480 push {r7} 8015168: b085 sub sp, #20 801516a: af00 add r7, sp, #0 801516c: 6078 str r0, [r7, #4] /* Returns the distance between xTail and xHead. */ size_t xCount; xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead; 801516e: 687b ldr r3, [r7, #4] 8015170: 689a ldr r2, [r3, #8] 8015172: 687b ldr r3, [r7, #4] 8015174: 685b ldr r3, [r3, #4] 8015176: 4413 add r3, r2 8015178: 60fb str r3, [r7, #12] xCount -= pxStreamBuffer->xTail; 801517a: 687b ldr r3, [r7, #4] 801517c: 681b ldr r3, [r3, #0] 801517e: 68fa ldr r2, [r7, #12] 8015180: 1ad3 subs r3, r2, r3 8015182: 60fb str r3, [r7, #12] if ( xCount >= pxStreamBuffer->xLength ) 8015184: 687b ldr r3, [r7, #4] 8015186: 689b ldr r3, [r3, #8] 8015188: 68fa ldr r2, [r7, #12] 801518a: 429a cmp r2, r3 801518c: d304 bcc.n 8015198 { xCount -= pxStreamBuffer->xLength; 801518e: 687b ldr r3, [r7, #4] 8015190: 689b ldr r3, [r3, #8] 8015192: 68fa ldr r2, [r7, #12] 8015194: 1ad3 subs r3, r2, r3 8015196: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xCount; 8015198: 68fb ldr r3, [r7, #12] } 801519a: 4618 mov r0, r3 801519c: 3714 adds r7, #20 801519e: 46bd mov sp, r7 80151a0: f85d 7b04 ldr.w r7, [sp], #4 80151a4: 4770 bx lr 080151a6 : const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) { 80151a6: b580 push {r7, lr} 80151a8: b08e sub sp, #56 @ 0x38 80151aa: af04 add r7, sp, #16 80151ac: 60f8 str r0, [r7, #12] 80151ae: 60b9 str r1, [r7, #8] 80151b0: 607a str r2, [r7, #4] 80151b2: 603b str r3, [r7, #0] TCB_t *pxNewTCB; TaskHandle_t xReturn; configASSERT( puxStackBuffer != NULL ); 80151b4: 6b7b ldr r3, [r7, #52] @ 0x34 80151b6: 2b00 cmp r3, #0 80151b8: d10b bne.n 80151d2 __asm volatile 80151ba: f04f 0350 mov.w r3, #80 @ 0x50 80151be: f383 8811 msr BASEPRI, r3 80151c2: f3bf 8f6f isb sy 80151c6: f3bf 8f4f dsb sy 80151ca: 623b str r3, [r7, #32] } 80151cc: bf00 nop 80151ce: bf00 nop 80151d0: e7fd b.n 80151ce configASSERT( pxTaskBuffer != NULL ); 80151d2: 6bbb ldr r3, [r7, #56] @ 0x38 80151d4: 2b00 cmp r3, #0 80151d6: d10b bne.n 80151f0 __asm volatile 80151d8: f04f 0350 mov.w r3, #80 @ 0x50 80151dc: f383 8811 msr BASEPRI, r3 80151e0: f3bf 8f6f isb sy 80151e4: f3bf 8f4f dsb sy 80151e8: 61fb str r3, [r7, #28] } 80151ea: bf00 nop 80151ec: bf00 nop 80151ee: e7fd b.n 80151ec #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTask_t equals the size of the real task structure. */ volatile size_t xSize = sizeof( StaticTask_t ); 80151f0: 23a8 movs r3, #168 @ 0xa8 80151f2: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( TCB_t ) ); 80151f4: 693b ldr r3, [r7, #16] 80151f6: 2ba8 cmp r3, #168 @ 0xa8 80151f8: d00b beq.n 8015212 __asm volatile 80151fa: f04f 0350 mov.w r3, #80 @ 0x50 80151fe: f383 8811 msr BASEPRI, r3 8015202: f3bf 8f6f isb sy 8015206: f3bf 8f4f dsb sy 801520a: 61bb str r3, [r7, #24] } 801520c: bf00 nop 801520e: bf00 nop 8015210: e7fd b.n 801520e ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ 8015212: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) 8015214: 6bbb ldr r3, [r7, #56] @ 0x38 8015216: 2b00 cmp r3, #0 8015218: d01e beq.n 8015258 801521a: 6b7b ldr r3, [r7, #52] @ 0x34 801521c: 2b00 cmp r3, #0 801521e: d01b beq.n 8015258 { /* The memory used for the task's TCB and stack are passed into this function - use them. */ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8015220: 6bbb ldr r3, [r7, #56] @ 0x38 8015222: 627b str r3, [r7, #36] @ 0x24 pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; 8015224: 6a7b ldr r3, [r7, #36] @ 0x24 8015226: 6b7a ldr r2, [r7, #52] @ 0x34 8015228: 631a str r2, [r3, #48] @ 0x30 #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created statically in case the task is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; 801522a: 6a7b ldr r3, [r7, #36] @ 0x24 801522c: 2202 movs r2, #2 801522e: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 8015232: 2300 movs r3, #0 8015234: 9303 str r3, [sp, #12] 8015236: 6a7b ldr r3, [r7, #36] @ 0x24 8015238: 9302 str r3, [sp, #8] 801523a: f107 0314 add.w r3, r7, #20 801523e: 9301 str r3, [sp, #4] 8015240: 6b3b ldr r3, [r7, #48] @ 0x30 8015242: 9300 str r3, [sp, #0] 8015244: 683b ldr r3, [r7, #0] 8015246: 687a ldr r2, [r7, #4] 8015248: 68b9 ldr r1, [r7, #8] 801524a: 68f8 ldr r0, [r7, #12] 801524c: f000 f850 bl 80152f0 prvAddNewTaskToReadyList( pxNewTCB ); 8015250: 6a78 ldr r0, [r7, #36] @ 0x24 8015252: f000 f8f5 bl 8015440 8015256: e001 b.n 801525c } else { xReturn = NULL; 8015258: 2300 movs r3, #0 801525a: 617b str r3, [r7, #20] } return xReturn; 801525c: 697b ldr r3, [r7, #20] } 801525e: 4618 mov r0, r3 8015260: 3728 adds r7, #40 @ 0x28 8015262: 46bd mov sp, r7 8015264: bd80 pop {r7, pc} 08015266 : const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const configSTACK_DEPTH_TYPE usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) { 8015266: b580 push {r7, lr} 8015268: b08c sub sp, #48 @ 0x30 801526a: af04 add r7, sp, #16 801526c: 60f8 str r0, [r7, #12] 801526e: 60b9 str r1, [r7, #8] 8015270: 603b str r3, [r7, #0] 8015272: 4613 mov r3, r2 8015274: 80fb strh r3, [r7, #6] #else /* portSTACK_GROWTH */ { StackType_t *pxStack; /* Allocate space for the stack used by the task being created. */ pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ 8015276: 88fb ldrh r3, [r7, #6] 8015278: 009b lsls r3, r3, #2 801527a: 4618 mov r0, r3 801527c: f002 f8d6 bl 801742c 8015280: 6178 str r0, [r7, #20] if( pxStack != NULL ) 8015282: 697b ldr r3, [r7, #20] 8015284: 2b00 cmp r3, #0 8015286: d00e beq.n 80152a6 { /* Allocate space for the TCB. */ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ 8015288: 20a8 movs r0, #168 @ 0xa8 801528a: f002 f8cf bl 801742c 801528e: 61f8 str r0, [r7, #28] if( pxNewTCB != NULL ) 8015290: 69fb ldr r3, [r7, #28] 8015292: 2b00 cmp r3, #0 8015294: d003 beq.n 801529e { /* Store the stack location in the TCB. */ pxNewTCB->pxStack = pxStack; 8015296: 69fb ldr r3, [r7, #28] 8015298: 697a ldr r2, [r7, #20] 801529a: 631a str r2, [r3, #48] @ 0x30 801529c: e005 b.n 80152aa } else { /* The stack cannot be used as the TCB was not created. Free it again. */ vPortFree( pxStack ); 801529e: 6978 ldr r0, [r7, #20] 80152a0: f002 f992 bl 80175c8 80152a4: e001 b.n 80152aa } } else { pxNewTCB = NULL; 80152a6: 2300 movs r3, #0 80152a8: 61fb str r3, [r7, #28] } } #endif /* portSTACK_GROWTH */ if( pxNewTCB != NULL ) 80152aa: 69fb ldr r3, [r7, #28] 80152ac: 2b00 cmp r3, #0 80152ae: d017 beq.n 80152e0 { #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; 80152b0: 69fb ldr r3, [r7, #28] 80152b2: 2200 movs r2, #0 80152b4: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); 80152b8: 88fa ldrh r2, [r7, #6] 80152ba: 2300 movs r3, #0 80152bc: 9303 str r3, [sp, #12] 80152be: 69fb ldr r3, [r7, #28] 80152c0: 9302 str r3, [sp, #8] 80152c2: 6afb ldr r3, [r7, #44] @ 0x2c 80152c4: 9301 str r3, [sp, #4] 80152c6: 6abb ldr r3, [r7, #40] @ 0x28 80152c8: 9300 str r3, [sp, #0] 80152ca: 683b ldr r3, [r7, #0] 80152cc: 68b9 ldr r1, [r7, #8] 80152ce: 68f8 ldr r0, [r7, #12] 80152d0: f000 f80e bl 80152f0 prvAddNewTaskToReadyList( pxNewTCB ); 80152d4: 69f8 ldr r0, [r7, #28] 80152d6: f000 f8b3 bl 8015440 xReturn = pdPASS; 80152da: 2301 movs r3, #1 80152dc: 61bb str r3, [r7, #24] 80152de: e002 b.n 80152e6 } else { xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; 80152e0: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80152e4: 61bb str r3, [r7, #24] } return xReturn; 80152e6: 69bb ldr r3, [r7, #24] } 80152e8: 4618 mov r0, r3 80152ea: 3720 adds r7, #32 80152ec: 46bd mov sp, r7 80152ee: bd80 pop {r7, pc} 080152f0 : void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, TCB_t *pxNewTCB, const MemoryRegion_t * const xRegions ) { 80152f0: b580 push {r7, lr} 80152f2: b088 sub sp, #32 80152f4: af00 add r7, sp, #0 80152f6: 60f8 str r0, [r7, #12] 80152f8: 60b9 str r1, [r7, #8] 80152fa: 607a str r2, [r7, #4] 80152fc: 603b str r3, [r7, #0] /* Avoid dependency on memset() if it is not required. */ #if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) { /* Fill the stack with a known value to assist debugging. */ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); 80152fe: 6b3b ldr r3, [r7, #48] @ 0x30 8015300: 6b18 ldr r0, [r3, #48] @ 0x30 8015302: 687b ldr r3, [r7, #4] 8015304: 009b lsls r3, r3, #2 8015306: 461a mov r2, r3 8015308: 21a5 movs r1, #165 @ 0xa5 801530a: f003 f8ad bl 8018468 grows from high memory to low (as per the 80x86) or vice versa. portSTACK_GROWTH is used to make the result positive or negative as required by the port. */ #if( portSTACK_GROWTH < 0 ) { pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); 801530e: 6b3b ldr r3, [r7, #48] @ 0x30 8015310: 6b1a ldr r2, [r3, #48] @ 0x30 8015312: 6879 ldr r1, [r7, #4] 8015314: f06f 4340 mvn.w r3, #3221225472 @ 0xc0000000 8015318: 440b add r3, r1 801531a: 009b lsls r3, r3, #2 801531c: 4413 add r3, r2 801531e: 61bb str r3, [r7, #24] pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ 8015320: 69bb ldr r3, [r7, #24] 8015322: f023 0307 bic.w r3, r3, #7 8015326: 61bb str r3, [r7, #24] /* Check the alignment of the calculated top of stack is correct. */ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); 8015328: 69bb ldr r3, [r7, #24] 801532a: f003 0307 and.w r3, r3, #7 801532e: 2b00 cmp r3, #0 8015330: d00b beq.n 801534a __asm volatile 8015332: f04f 0350 mov.w r3, #80 @ 0x50 8015336: f383 8811 msr BASEPRI, r3 801533a: f3bf 8f6f isb sy 801533e: f3bf 8f4f dsb sy 8015342: 617b str r3, [r7, #20] } 8015344: bf00 nop 8015346: bf00 nop 8015348: e7fd b.n 8015346 pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); } #endif /* portSTACK_GROWTH */ /* Store the task name in the TCB. */ if( pcName != NULL ) 801534a: 68bb ldr r3, [r7, #8] 801534c: 2b00 cmp r3, #0 801534e: d01f beq.n 8015390 { for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8015350: 2300 movs r3, #0 8015352: 61fb str r3, [r7, #28] 8015354: e012 b.n 801537c { pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 8015356: 68ba ldr r2, [r7, #8] 8015358: 69fb ldr r3, [r7, #28] 801535a: 4413 add r3, r2 801535c: 7819 ldrb r1, [r3, #0] 801535e: 6b3a ldr r2, [r7, #48] @ 0x30 8015360: 69fb ldr r3, [r7, #28] 8015362: 4413 add r3, r2 8015364: 3334 adds r3, #52 @ 0x34 8015366: 460a mov r2, r1 8015368: 701a strb r2, [r3, #0] /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than configMAX_TASK_NAME_LEN characters just in case the memory after the string is not accessible (extremely unlikely). */ if( pcName[ x ] == ( char ) 0x00 ) 801536a: 68ba ldr r2, [r7, #8] 801536c: 69fb ldr r3, [r7, #28] 801536e: 4413 add r3, r2 8015370: 781b ldrb r3, [r3, #0] 8015372: 2b00 cmp r3, #0 8015374: d006 beq.n 8015384 for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8015376: 69fb ldr r3, [r7, #28] 8015378: 3301 adds r3, #1 801537a: 61fb str r3, [r7, #28] 801537c: 69fb ldr r3, [r7, #28] 801537e: 2b0f cmp r3, #15 8015380: d9e9 bls.n 8015356 8015382: e000 b.n 8015386 { break; 8015384: bf00 nop } } /* Ensure the name string is terminated in the case that the string length was greater or equal to configMAX_TASK_NAME_LEN. */ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; 8015386: 6b3b ldr r3, [r7, #48] @ 0x30 8015388: 2200 movs r2, #0 801538a: f883 2043 strb.w r2, [r3, #67] @ 0x43 801538e: e003 b.n 8015398 } else { /* The task has not been given a name, so just ensure there is a NULL terminator when it is read out. */ pxNewTCB->pcTaskName[ 0 ] = 0x00; 8015390: 6b3b ldr r3, [r7, #48] @ 0x30 8015392: 2200 movs r2, #0 8015394: f883 2034 strb.w r2, [r3, #52] @ 0x34 } /* This is used as an array index so must ensure it's not too large. First remove the privilege bit if one is present. */ if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) 8015398: 6abb ldr r3, [r7, #40] @ 0x28 801539a: 2b37 cmp r3, #55 @ 0x37 801539c: d901 bls.n 80153a2 { uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; 801539e: 2337 movs r3, #55 @ 0x37 80153a0: 62bb str r3, [r7, #40] @ 0x28 else { mtCOVERAGE_TEST_MARKER(); } pxNewTCB->uxPriority = uxPriority; 80153a2: 6b3b ldr r3, [r7, #48] @ 0x30 80153a4: 6aba ldr r2, [r7, #40] @ 0x28 80153a6: 62da str r2, [r3, #44] @ 0x2c #if ( configUSE_MUTEXES == 1 ) { pxNewTCB->uxBasePriority = uxPriority; 80153a8: 6b3b ldr r3, [r7, #48] @ 0x30 80153aa: 6aba ldr r2, [r7, #40] @ 0x28 80153ac: 64da str r2, [r3, #76] @ 0x4c pxNewTCB->uxMutexesHeld = 0; 80153ae: 6b3b ldr r3, [r7, #48] @ 0x30 80153b0: 2200 movs r2, #0 80153b2: 651a str r2, [r3, #80] @ 0x50 } #endif /* configUSE_MUTEXES */ vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); 80153b4: 6b3b ldr r3, [r7, #48] @ 0x30 80153b6: 3304 adds r3, #4 80153b8: 4618 mov r0, r3 80153ba: f7fe fd09 bl 8013dd0 vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); 80153be: 6b3b ldr r3, [r7, #48] @ 0x30 80153c0: 3318 adds r3, #24 80153c2: 4618 mov r0, r3 80153c4: f7fe fd04 bl 8013dd0 /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get back to the containing TCB from a generic item in a list. */ listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); 80153c8: 6b3b ldr r3, [r7, #48] @ 0x30 80153ca: 6b3a ldr r2, [r7, #48] @ 0x30 80153cc: 611a str r2, [r3, #16] /* Event lists are always in priority order. */ listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 80153ce: 6abb ldr r3, [r7, #40] @ 0x28 80153d0: f1c3 0238 rsb r2, r3, #56 @ 0x38 80153d4: 6b3b ldr r3, [r7, #48] @ 0x30 80153d6: 619a str r2, [r3, #24] listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); 80153d8: 6b3b ldr r3, [r7, #48] @ 0x30 80153da: 6b3a ldr r2, [r7, #48] @ 0x30 80153dc: 625a str r2, [r3, #36] @ 0x24 } #endif #if ( configUSE_TASK_NOTIFICATIONS == 1 ) { pxNewTCB->ulNotifiedValue = 0; 80153de: 6b3b ldr r3, [r7, #48] @ 0x30 80153e0: 2200 movs r2, #0 80153e2: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 80153e6: 6b3b ldr r3, [r7, #48] @ 0x30 80153e8: 2200 movs r2, #0 80153ea: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 #if ( configUSE_NEWLIB_REENTRANT == 1 ) { /* Initialise this task's Newlib reent structure. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); 80153ee: 6b3b ldr r3, [r7, #48] @ 0x30 80153f0: 3354 adds r3, #84 @ 0x54 80153f2: 224c movs r2, #76 @ 0x4c 80153f4: 2100 movs r1, #0 80153f6: 4618 mov r0, r3 80153f8: f003 f836 bl 8018468 80153fc: 6b3b ldr r3, [r7, #48] @ 0x30 80153fe: 4a0d ldr r2, [pc, #52] @ (8015434 ) 8015400: 659a str r2, [r3, #88] @ 0x58 8015402: 6b3b ldr r3, [r7, #48] @ 0x30 8015404: 4a0c ldr r2, [pc, #48] @ (8015438 ) 8015406: 65da str r2, [r3, #92] @ 0x5c 8015408: 6b3b ldr r3, [r7, #48] @ 0x30 801540a: 4a0c ldr r2, [pc, #48] @ (801543c ) 801540c: 661a str r2, [r3, #96] @ 0x60 } #endif /* portSTACK_GROWTH */ } #else /* portHAS_STACK_OVERFLOW_CHECKING */ { pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); 801540e: 683a ldr r2, [r7, #0] 8015410: 68f9 ldr r1, [r7, #12] 8015412: 69b8 ldr r0, [r7, #24] 8015414: f001 fdb8 bl 8016f88 8015418: 4602 mov r2, r0 801541a: 6b3b ldr r3, [r7, #48] @ 0x30 801541c: 601a str r2, [r3, #0] } #endif /* portHAS_STACK_OVERFLOW_CHECKING */ } #endif /* portUSING_MPU_WRAPPERS */ if( pxCreatedTask != NULL ) 801541e: 6afb ldr r3, [r7, #44] @ 0x2c 8015420: 2b00 cmp r3, #0 8015422: d002 beq.n 801542a { /* Pass the handle out in an anonymous way. The handle can be used to change the created task's priority, delete the created task, etc.*/ *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; 8015424: 6afb ldr r3, [r7, #44] @ 0x2c 8015426: 6b3a ldr r2, [r7, #48] @ 0x30 8015428: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 801542a: bf00 nop 801542c: 3720 adds r7, #32 801542e: 46bd mov sp, r7 8015430: bd80 pop {r7, pc} 8015432: bf00 nop 8015434: 240131a8 .word 0x240131a8 8015438: 24013210 .word 0x24013210 801543c: 24013278 .word 0x24013278 08015440 : /*-----------------------------------------------------------*/ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) { 8015440: b580 push {r7, lr} 8015442: b082 sub sp, #8 8015444: af00 add r7, sp, #0 8015446: 6078 str r0, [r7, #4] /* Ensure interrupts don't access the task lists while the lists are being updated. */ taskENTER_CRITICAL(); 8015448: f001 fece bl 80171e8 { uxCurrentNumberOfTasks++; 801544c: 4b2d ldr r3, [pc, #180] @ (8015504 ) 801544e: 681b ldr r3, [r3, #0] 8015450: 3301 adds r3, #1 8015452: 4a2c ldr r2, [pc, #176] @ (8015504 ) 8015454: 6013 str r3, [r2, #0] if( pxCurrentTCB == NULL ) 8015456: 4b2c ldr r3, [pc, #176] @ (8015508 ) 8015458: 681b ldr r3, [r3, #0] 801545a: 2b00 cmp r3, #0 801545c: d109 bne.n 8015472 { /* There are no other tasks, or all the other tasks are in the suspended state - make this the current task. */ pxCurrentTCB = pxNewTCB; 801545e: 4a2a ldr r2, [pc, #168] @ (8015508 ) 8015460: 687b ldr r3, [r7, #4] 8015462: 6013 str r3, [r2, #0] if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) 8015464: 4b27 ldr r3, [pc, #156] @ (8015504 ) 8015466: 681b ldr r3, [r3, #0] 8015468: 2b01 cmp r3, #1 801546a: d110 bne.n 801548e { /* This is the first task to be created so do the preliminary initialisation required. We will not recover if this call fails, but we will report the failure. */ prvInitialiseTaskLists(); 801546c: f000 fc64 bl 8015d38 8015470: e00d b.n 801548e else { /* If the scheduler is not already running, make this task the current task if it is the highest priority task to be created so far. */ if( xSchedulerRunning == pdFALSE ) 8015472: 4b26 ldr r3, [pc, #152] @ (801550c ) 8015474: 681b ldr r3, [r3, #0] 8015476: 2b00 cmp r3, #0 8015478: d109 bne.n 801548e { if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) 801547a: 4b23 ldr r3, [pc, #140] @ (8015508 ) 801547c: 681b ldr r3, [r3, #0] 801547e: 6ada ldr r2, [r3, #44] @ 0x2c 8015480: 687b ldr r3, [r7, #4] 8015482: 6adb ldr r3, [r3, #44] @ 0x2c 8015484: 429a cmp r2, r3 8015486: d802 bhi.n 801548e { pxCurrentTCB = pxNewTCB; 8015488: 4a1f ldr r2, [pc, #124] @ (8015508 ) 801548a: 687b ldr r3, [r7, #4] 801548c: 6013 str r3, [r2, #0] { mtCOVERAGE_TEST_MARKER(); } } uxTaskNumber++; 801548e: 4b20 ldr r3, [pc, #128] @ (8015510 ) 8015490: 681b ldr r3, [r3, #0] 8015492: 3301 adds r3, #1 8015494: 4a1e ldr r2, [pc, #120] @ (8015510 ) 8015496: 6013 str r3, [r2, #0] #if ( configUSE_TRACE_FACILITY == 1 ) { /* Add a counter into the TCB for tracing only. */ pxNewTCB->uxTCBNumber = uxTaskNumber; 8015498: 4b1d ldr r3, [pc, #116] @ (8015510 ) 801549a: 681a ldr r2, [r3, #0] 801549c: 687b ldr r3, [r7, #4] 801549e: 645a str r2, [r3, #68] @ 0x44 } #endif /* configUSE_TRACE_FACILITY */ traceTASK_CREATE( pxNewTCB ); prvAddTaskToReadyList( pxNewTCB ); 80154a0: 687b ldr r3, [r7, #4] 80154a2: 6ada ldr r2, [r3, #44] @ 0x2c 80154a4: 4b1b ldr r3, [pc, #108] @ (8015514 ) 80154a6: 681b ldr r3, [r3, #0] 80154a8: 429a cmp r2, r3 80154aa: d903 bls.n 80154b4 80154ac: 687b ldr r3, [r7, #4] 80154ae: 6adb ldr r3, [r3, #44] @ 0x2c 80154b0: 4a18 ldr r2, [pc, #96] @ (8015514 ) 80154b2: 6013 str r3, [r2, #0] 80154b4: 687b ldr r3, [r7, #4] 80154b6: 6ada ldr r2, [r3, #44] @ 0x2c 80154b8: 4613 mov r3, r2 80154ba: 009b lsls r3, r3, #2 80154bc: 4413 add r3, r2 80154be: 009b lsls r3, r3, #2 80154c0: 4a15 ldr r2, [pc, #84] @ (8015518 ) 80154c2: 441a add r2, r3 80154c4: 687b ldr r3, [r7, #4] 80154c6: 3304 adds r3, #4 80154c8: 4619 mov r1, r3 80154ca: 4610 mov r0, r2 80154cc: f7fe fc8d bl 8013dea portSETUP_TCB( pxNewTCB ); } taskEXIT_CRITICAL(); 80154d0: f001 febc bl 801724c if( xSchedulerRunning != pdFALSE ) 80154d4: 4b0d ldr r3, [pc, #52] @ (801550c ) 80154d6: 681b ldr r3, [r3, #0] 80154d8: 2b00 cmp r3, #0 80154da: d00e beq.n 80154fa { /* If the created task is of a higher priority than the current task then it should run now. */ if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) 80154dc: 4b0a ldr r3, [pc, #40] @ (8015508 ) 80154de: 681b ldr r3, [r3, #0] 80154e0: 6ada ldr r2, [r3, #44] @ 0x2c 80154e2: 687b ldr r3, [r7, #4] 80154e4: 6adb ldr r3, [r3, #44] @ 0x2c 80154e6: 429a cmp r2, r3 80154e8: d207 bcs.n 80154fa { taskYIELD_IF_USING_PREEMPTION(); 80154ea: 4b0c ldr r3, [pc, #48] @ (801551c ) 80154ec: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80154f0: 601a str r2, [r3, #0] 80154f2: f3bf 8f4f dsb sy 80154f6: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 80154fa: bf00 nop 80154fc: 3708 adds r7, #8 80154fe: 46bd mov sp, r7 8015500: bd80 pop {r7, pc} 8015502: bf00 nop 8015504: 24003028 .word 0x24003028 8015508: 24002b54 .word 0x24002b54 801550c: 24003034 .word 0x24003034 8015510: 24003044 .word 0x24003044 8015514: 24003030 .word 0x24003030 8015518: 24002b58 .word 0x24002b58 801551c: e000ed04 .word 0xe000ed04 08015520 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelay == 1 ) void vTaskDelay( const TickType_t xTicksToDelay ) { 8015520: b580 push {r7, lr} 8015522: b084 sub sp, #16 8015524: af00 add r7, sp, #0 8015526: 6078 str r0, [r7, #4] BaseType_t xAlreadyYielded = pdFALSE; 8015528: 2300 movs r3, #0 801552a: 60fb str r3, [r7, #12] /* A delay time of zero just forces a reschedule. */ if( xTicksToDelay > ( TickType_t ) 0U ) 801552c: 687b ldr r3, [r7, #4] 801552e: 2b00 cmp r3, #0 8015530: d018 beq.n 8015564 { configASSERT( uxSchedulerSuspended == 0 ); 8015532: 4b14 ldr r3, [pc, #80] @ (8015584 ) 8015534: 681b ldr r3, [r3, #0] 8015536: 2b00 cmp r3, #0 8015538: d00b beq.n 8015552 __asm volatile 801553a: f04f 0350 mov.w r3, #80 @ 0x50 801553e: f383 8811 msr BASEPRI, r3 8015542: f3bf 8f6f isb sy 8015546: f3bf 8f4f dsb sy 801554a: 60bb str r3, [r7, #8] } 801554c: bf00 nop 801554e: bf00 nop 8015550: e7fd b.n 801554e vTaskSuspendAll(); 8015552: f000 f88b bl 801566c list or removed from the blocked list until the scheduler is resumed. This task cannot be in an event list as it is the currently executing task. */ prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); 8015556: 2100 movs r1, #0 8015558: 6878 ldr r0, [r7, #4] 801555a: f001 f87d bl 8016658 } xAlreadyYielded = xTaskResumeAll(); 801555e: f000 f893 bl 8015688 8015562: 60f8 str r0, [r7, #12] mtCOVERAGE_TEST_MARKER(); } /* Force a reschedule if xTaskResumeAll has not already done so, we may have put ourselves to sleep. */ if( xAlreadyYielded == pdFALSE ) 8015564: 68fb ldr r3, [r7, #12] 8015566: 2b00 cmp r3, #0 8015568: d107 bne.n 801557a { portYIELD_WITHIN_API(); 801556a: 4b07 ldr r3, [pc, #28] @ (8015588 ) 801556c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015570: 601a str r2, [r3, #0] 8015572: f3bf 8f4f dsb sy 8015576: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 801557a: bf00 nop 801557c: 3710 adds r7, #16 801557e: 46bd mov sp, r7 8015580: bd80 pop {r7, pc} 8015582: bf00 nop 8015584: 24003050 .word 0x24003050 8015588: e000ed04 .word 0xe000ed04 0801558c : #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ /*-----------------------------------------------------------*/ void vTaskStartScheduler( void ) { 801558c: b580 push {r7, lr} 801558e: b08a sub sp, #40 @ 0x28 8015590: af04 add r7, sp, #16 BaseType_t xReturn; /* Add the idle task at the lowest priority. */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxIdleTaskTCBBuffer = NULL; 8015592: 2300 movs r3, #0 8015594: 60bb str r3, [r7, #8] StackType_t *pxIdleTaskStackBuffer = NULL; 8015596: 2300 movs r3, #0 8015598: 607b str r3, [r7, #4] uint32_t ulIdleTaskStackSize; /* The Idle task is created using user provided RAM - obtain the address of the RAM then create the idle task. */ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); 801559a: 463a mov r2, r7 801559c: 1d39 adds r1, r7, #4 801559e: f107 0308 add.w r3, r7, #8 80155a2: 4618 mov r0, r3 80155a4: f7fe fbc0 bl 8013d28 xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, 80155a8: 6839 ldr r1, [r7, #0] 80155aa: 687b ldr r3, [r7, #4] 80155ac: 68ba ldr r2, [r7, #8] 80155ae: 9202 str r2, [sp, #8] 80155b0: 9301 str r3, [sp, #4] 80155b2: 2300 movs r3, #0 80155b4: 9300 str r3, [sp, #0] 80155b6: 2300 movs r3, #0 80155b8: 460a mov r2, r1 80155ba: 4924 ldr r1, [pc, #144] @ (801564c ) 80155bc: 4824 ldr r0, [pc, #144] @ (8015650 ) 80155be: f7ff fdf2 bl 80151a6 80155c2: 4603 mov r3, r0 80155c4: 4a23 ldr r2, [pc, #140] @ (8015654 ) 80155c6: 6013 str r3, [r2, #0] ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ pxIdleTaskStackBuffer, pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ if( xIdleTaskHandle != NULL ) 80155c8: 4b22 ldr r3, [pc, #136] @ (8015654 ) 80155ca: 681b ldr r3, [r3, #0] 80155cc: 2b00 cmp r3, #0 80155ce: d002 beq.n 80155d6 { xReturn = pdPASS; 80155d0: 2301 movs r3, #1 80155d2: 617b str r3, [r7, #20] 80155d4: e001 b.n 80155da } else { xReturn = pdFAIL; 80155d6: 2300 movs r3, #0 80155d8: 617b str r3, [r7, #20] } #endif /* configSUPPORT_STATIC_ALLOCATION */ #if ( configUSE_TIMERS == 1 ) { if( xReturn == pdPASS ) 80155da: 697b ldr r3, [r7, #20] 80155dc: 2b01 cmp r3, #1 80155de: d102 bne.n 80155e6 { xReturn = xTimerCreateTimerTask(); 80155e0: f001 f88e bl 8016700 80155e4: 6178 str r0, [r7, #20] mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_TIMERS */ if( xReturn == pdPASS ) 80155e6: 697b ldr r3, [r7, #20] 80155e8: 2b01 cmp r3, #1 80155ea: d11b bne.n 8015624 __asm volatile 80155ec: f04f 0350 mov.w r3, #80 @ 0x50 80155f0: f383 8811 msr BASEPRI, r3 80155f4: f3bf 8f6f isb sy 80155f8: f3bf 8f4f dsb sy 80155fc: 613b str r3, [r7, #16] } 80155fe: bf00 nop { /* Switch Newlib's _impure_ptr variable to point to the _reent structure specific to the task that will run first. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 8015600: 4b15 ldr r3, [pc, #84] @ (8015658 ) 8015602: 681b ldr r3, [r3, #0] 8015604: 3354 adds r3, #84 @ 0x54 8015606: 4a15 ldr r2, [pc, #84] @ (801565c ) 8015608: 6013 str r3, [r2, #0] } #endif /* configUSE_NEWLIB_REENTRANT */ xNextTaskUnblockTime = portMAX_DELAY; 801560a: 4b15 ldr r3, [pc, #84] @ (8015660 ) 801560c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8015610: 601a str r2, [r3, #0] xSchedulerRunning = pdTRUE; 8015612: 4b14 ldr r3, [pc, #80] @ (8015664 ) 8015614: 2201 movs r2, #1 8015616: 601a str r2, [r3, #0] xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; 8015618: 4b13 ldr r3, [pc, #76] @ (8015668 ) 801561a: 2200 movs r2, #0 801561c: 601a str r2, [r3, #0] traceTASK_SWITCHED_IN(); /* Setting up the timer tick is hardware specific and thus in the portable interface. */ if( xPortStartScheduler() != pdFALSE ) 801561e: f001 fd3f bl 80170a0 } /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, meaning xIdleTaskHandle is not used anywhere else. */ ( void ) xIdleTaskHandle; } 8015622: e00f b.n 8015644 configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); 8015624: 697b ldr r3, [r7, #20] 8015626: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801562a: d10b bne.n 8015644 __asm volatile 801562c: f04f 0350 mov.w r3, #80 @ 0x50 8015630: f383 8811 msr BASEPRI, r3 8015634: f3bf 8f6f isb sy 8015638: f3bf 8f4f dsb sy 801563c: 60fb str r3, [r7, #12] } 801563e: bf00 nop 8015640: bf00 nop 8015642: e7fd b.n 8015640 } 8015644: bf00 nop 8015646: 3718 adds r7, #24 8015648: 46bd mov sp, r7 801564a: bd80 pop {r7, pc} 801564c: 0801a20c .word 0x0801a20c 8015650: 08015d09 .word 0x08015d09 8015654: 2400304c .word 0x2400304c 8015658: 24002b54 .word 0x24002b54 801565c: 24000054 .word 0x24000054 8015660: 24003048 .word 0x24003048 8015664: 24003034 .word 0x24003034 8015668: 2400302c .word 0x2400302c 0801566c : vPortEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { 801566c: b480 push {r7} 801566e: af00 add r7, sp, #0 do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER(); /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; 8015670: 4b04 ldr r3, [pc, #16] @ (8015684 ) 8015672: 681b ldr r3, [r3, #0] 8015674: 3301 adds r3, #1 8015676: 4a03 ldr r2, [pc, #12] @ (8015684 ) 8015678: 6013 str r3, [r2, #0] /* Enforces ordering for ports and optimised compilers that may otherwise place the above increment elsewhere. */ portMEMORY_BARRIER(); } 801567a: bf00 nop 801567c: 46bd mov sp, r7 801567e: f85d 7b04 ldr.w r7, [sp], #4 8015682: 4770 bx lr 8015684: 24003050 .word 0x24003050 08015688 : #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ BaseType_t xTaskResumeAll( void ) { 8015688: b580 push {r7, lr} 801568a: b084 sub sp, #16 801568c: af00 add r7, sp, #0 TCB_t *pxTCB = NULL; 801568e: 2300 movs r3, #0 8015690: 60fb str r3, [r7, #12] BaseType_t xAlreadyYielded = pdFALSE; 8015692: 2300 movs r3, #0 8015694: 60bb str r3, [r7, #8] /* If uxSchedulerSuspended is zero then this function does not match a previous call to vTaskSuspendAll(). */ configASSERT( uxSchedulerSuspended ); 8015696: 4b42 ldr r3, [pc, #264] @ (80157a0 ) 8015698: 681b ldr r3, [r3, #0] 801569a: 2b00 cmp r3, #0 801569c: d10b bne.n 80156b6 __asm volatile 801569e: f04f 0350 mov.w r3, #80 @ 0x50 80156a2: f383 8811 msr BASEPRI, r3 80156a6: f3bf 8f6f isb sy 80156aa: f3bf 8f4f dsb sy 80156ae: 603b str r3, [r7, #0] } 80156b0: bf00 nop 80156b2: bf00 nop 80156b4: e7fd b.n 80156b2 /* It is possible that an ISR caused a task to be removed from an event list while the scheduler was suspended. If this was the case then the removed task will have been added to the xPendingReadyList. Once the scheduler has been resumed it is safe to move all the pending ready tasks from this list into their appropriate ready list. */ taskENTER_CRITICAL(); 80156b6: f001 fd97 bl 80171e8 { --uxSchedulerSuspended; 80156ba: 4b39 ldr r3, [pc, #228] @ (80157a0 ) 80156bc: 681b ldr r3, [r3, #0] 80156be: 3b01 subs r3, #1 80156c0: 4a37 ldr r2, [pc, #220] @ (80157a0 ) 80156c2: 6013 str r3, [r2, #0] if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80156c4: 4b36 ldr r3, [pc, #216] @ (80157a0 ) 80156c6: 681b ldr r3, [r3, #0] 80156c8: 2b00 cmp r3, #0 80156ca: d162 bne.n 8015792 { if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) 80156cc: 4b35 ldr r3, [pc, #212] @ (80157a4 ) 80156ce: 681b ldr r3, [r3, #0] 80156d0: 2b00 cmp r3, #0 80156d2: d05e beq.n 8015792 { /* Move any readied tasks from the pending list into the appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 80156d4: e02f b.n 8015736 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80156d6: 4b34 ldr r3, [pc, #208] @ (80157a8 ) 80156d8: 68db ldr r3, [r3, #12] 80156da: 68db ldr r3, [r3, #12] 80156dc: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 80156de: 68fb ldr r3, [r7, #12] 80156e0: 3318 adds r3, #24 80156e2: 4618 mov r0, r3 80156e4: f7fe fbde bl 8013ea4 ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80156e8: 68fb ldr r3, [r7, #12] 80156ea: 3304 adds r3, #4 80156ec: 4618 mov r0, r3 80156ee: f7fe fbd9 bl 8013ea4 prvAddTaskToReadyList( pxTCB ); 80156f2: 68fb ldr r3, [r7, #12] 80156f4: 6ada ldr r2, [r3, #44] @ 0x2c 80156f6: 4b2d ldr r3, [pc, #180] @ (80157ac ) 80156f8: 681b ldr r3, [r3, #0] 80156fa: 429a cmp r2, r3 80156fc: d903 bls.n 8015706 80156fe: 68fb ldr r3, [r7, #12] 8015700: 6adb ldr r3, [r3, #44] @ 0x2c 8015702: 4a2a ldr r2, [pc, #168] @ (80157ac ) 8015704: 6013 str r3, [r2, #0] 8015706: 68fb ldr r3, [r7, #12] 8015708: 6ada ldr r2, [r3, #44] @ 0x2c 801570a: 4613 mov r3, r2 801570c: 009b lsls r3, r3, #2 801570e: 4413 add r3, r2 8015710: 009b lsls r3, r3, #2 8015712: 4a27 ldr r2, [pc, #156] @ (80157b0 ) 8015714: 441a add r2, r3 8015716: 68fb ldr r3, [r7, #12] 8015718: 3304 adds r3, #4 801571a: 4619 mov r1, r3 801571c: 4610 mov r0, r2 801571e: f7fe fb64 bl 8013dea /* If the moved task has a priority higher than the current task then a yield must be performed. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 8015722: 68fb ldr r3, [r7, #12] 8015724: 6ada ldr r2, [r3, #44] @ 0x2c 8015726: 4b23 ldr r3, [pc, #140] @ (80157b4 ) 8015728: 681b ldr r3, [r3, #0] 801572a: 6adb ldr r3, [r3, #44] @ 0x2c 801572c: 429a cmp r2, r3 801572e: d302 bcc.n 8015736 { xYieldPending = pdTRUE; 8015730: 4b21 ldr r3, [pc, #132] @ (80157b8 ) 8015732: 2201 movs r2, #1 8015734: 601a str r2, [r3, #0] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 8015736: 4b1c ldr r3, [pc, #112] @ (80157a8 ) 8015738: 681b ldr r3, [r3, #0] 801573a: 2b00 cmp r3, #0 801573c: d1cb bne.n 80156d6 { mtCOVERAGE_TEST_MARKER(); } } if( pxTCB != NULL ) 801573e: 68fb ldr r3, [r7, #12] 8015740: 2b00 cmp r3, #0 8015742: d001 beq.n 8015748 which may have prevented the next unblock time from being re-calculated, in which case re-calculate it now. Mainly important for low power tickless implementations, where this can prevent an unnecessary exit from low power state. */ prvResetNextTaskUnblockTime(); 8015744: f000 fb9c bl 8015e80 /* If any ticks occurred while the scheduler was suspended then they should be processed now. This ensures the tick count does not slip, and that any delayed tasks are resumed at the correct time. */ { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ 8015748: 4b1c ldr r3, [pc, #112] @ (80157bc ) 801574a: 681b ldr r3, [r3, #0] 801574c: 607b str r3, [r7, #4] if( xPendedCounts > ( TickType_t ) 0U ) 801574e: 687b ldr r3, [r7, #4] 8015750: 2b00 cmp r3, #0 8015752: d010 beq.n 8015776 { do { if( xTaskIncrementTick() != pdFALSE ) 8015754: f000 f846 bl 80157e4 8015758: 4603 mov r3, r0 801575a: 2b00 cmp r3, #0 801575c: d002 beq.n 8015764 { xYieldPending = pdTRUE; 801575e: 4b16 ldr r3, [pc, #88] @ (80157b8 ) 8015760: 2201 movs r2, #1 8015762: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } --xPendedCounts; 8015764: 687b ldr r3, [r7, #4] 8015766: 3b01 subs r3, #1 8015768: 607b str r3, [r7, #4] } while( xPendedCounts > ( TickType_t ) 0U ); 801576a: 687b ldr r3, [r7, #4] 801576c: 2b00 cmp r3, #0 801576e: d1f1 bne.n 8015754 xPendedTicks = 0; 8015770: 4b12 ldr r3, [pc, #72] @ (80157bc ) 8015772: 2200 movs r2, #0 8015774: 601a str r2, [r3, #0] { mtCOVERAGE_TEST_MARKER(); } } if( xYieldPending != pdFALSE ) 8015776: 4b10 ldr r3, [pc, #64] @ (80157b8 ) 8015778: 681b ldr r3, [r3, #0] 801577a: 2b00 cmp r3, #0 801577c: d009 beq.n 8015792 { #if( configUSE_PREEMPTION != 0 ) { xAlreadyYielded = pdTRUE; 801577e: 2301 movs r3, #1 8015780: 60bb str r3, [r7, #8] } #endif taskYIELD_IF_USING_PREEMPTION(); 8015782: 4b0f ldr r3, [pc, #60] @ (80157c0 ) 8015784: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015788: 601a str r2, [r3, #0] 801578a: f3bf 8f4f dsb sy 801578e: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8015792: f001 fd5b bl 801724c return xAlreadyYielded; 8015796: 68bb ldr r3, [r7, #8] } 8015798: 4618 mov r0, r3 801579a: 3710 adds r7, #16 801579c: 46bd mov sp, r7 801579e: bd80 pop {r7, pc} 80157a0: 24003050 .word 0x24003050 80157a4: 24003028 .word 0x24003028 80157a8: 24002fe8 .word 0x24002fe8 80157ac: 24003030 .word 0x24003030 80157b0: 24002b58 .word 0x24002b58 80157b4: 24002b54 .word 0x24002b54 80157b8: 2400303c .word 0x2400303c 80157bc: 24003038 .word 0x24003038 80157c0: e000ed04 .word 0xe000ed04 080157c4 : /*-----------------------------------------------------------*/ TickType_t xTaskGetTickCount( void ) { 80157c4: b480 push {r7} 80157c6: b083 sub sp, #12 80157c8: af00 add r7, sp, #0 TickType_t xTicks; /* Critical section required if running on a 16 bit processor. */ portTICK_TYPE_ENTER_CRITICAL(); { xTicks = xTickCount; 80157ca: 4b05 ldr r3, [pc, #20] @ (80157e0 ) 80157cc: 681b ldr r3, [r3, #0] 80157ce: 607b str r3, [r7, #4] } portTICK_TYPE_EXIT_CRITICAL(); return xTicks; 80157d0: 687b ldr r3, [r7, #4] } 80157d2: 4618 mov r0, r3 80157d4: 370c adds r7, #12 80157d6: 46bd mov sp, r7 80157d8: f85d 7b04 ldr.w r7, [sp], #4 80157dc: 4770 bx lr 80157de: bf00 nop 80157e0: 2400302c .word 0x2400302c 080157e4 : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { 80157e4: b580 push {r7, lr} 80157e6: b086 sub sp, #24 80157e8: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; 80157ea: 2300 movs r3, #0 80157ec: 617b str r3, [r7, #20] /* Called by the portable layer each time a tick interrupt occurs. Increments the tick then checks to see if the new tick value will cause any tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80157ee: 4b4f ldr r3, [pc, #316] @ (801592c ) 80157f0: 681b ldr r3, [r3, #0] 80157f2: 2b00 cmp r3, #0 80157f4: f040 8090 bne.w 8015918 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 80157f8: 4b4d ldr r3, [pc, #308] @ (8015930 ) 80157fa: 681b ldr r3, [r3, #0] 80157fc: 3301 adds r3, #1 80157fe: 613b str r3, [r7, #16] /* Increment the RTOS tick, switching the delayed and overflowed delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; 8015800: 4a4b ldr r2, [pc, #300] @ (8015930 ) 8015802: 693b ldr r3, [r7, #16] 8015804: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ 8015806: 693b ldr r3, [r7, #16] 8015808: 2b00 cmp r3, #0 801580a: d121 bne.n 8015850 { taskSWITCH_DELAYED_LISTS(); 801580c: 4b49 ldr r3, [pc, #292] @ (8015934 ) 801580e: 681b ldr r3, [r3, #0] 8015810: 681b ldr r3, [r3, #0] 8015812: 2b00 cmp r3, #0 8015814: d00b beq.n 801582e __asm volatile 8015816: f04f 0350 mov.w r3, #80 @ 0x50 801581a: f383 8811 msr BASEPRI, r3 801581e: f3bf 8f6f isb sy 8015822: f3bf 8f4f dsb sy 8015826: 603b str r3, [r7, #0] } 8015828: bf00 nop 801582a: bf00 nop 801582c: e7fd b.n 801582a 801582e: 4b41 ldr r3, [pc, #260] @ (8015934 ) 8015830: 681b ldr r3, [r3, #0] 8015832: 60fb str r3, [r7, #12] 8015834: 4b40 ldr r3, [pc, #256] @ (8015938 ) 8015836: 681b ldr r3, [r3, #0] 8015838: 4a3e ldr r2, [pc, #248] @ (8015934 ) 801583a: 6013 str r3, [r2, #0] 801583c: 4a3e ldr r2, [pc, #248] @ (8015938 ) 801583e: 68fb ldr r3, [r7, #12] 8015840: 6013 str r3, [r2, #0] 8015842: 4b3e ldr r3, [pc, #248] @ (801593c ) 8015844: 681b ldr r3, [r3, #0] 8015846: 3301 adds r3, #1 8015848: 4a3c ldr r2, [pc, #240] @ (801593c ) 801584a: 6013 str r3, [r2, #0] 801584c: f000 fb18 bl 8015e80 /* See if this tick has made a timeout expire. Tasks are stored in the queue in the order of their wake time - meaning once one task has been found whose block time has not expired there is no need to look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) 8015850: 4b3b ldr r3, [pc, #236] @ (8015940 ) 8015852: 681b ldr r3, [r3, #0] 8015854: 693a ldr r2, [r7, #16] 8015856: 429a cmp r2, r3 8015858: d349 bcc.n 80158ee { for( ;; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 801585a: 4b36 ldr r3, [pc, #216] @ (8015934 ) 801585c: 681b ldr r3, [r3, #0] 801585e: 681b ldr r3, [r3, #0] 8015860: 2b00 cmp r3, #0 8015862: d104 bne.n 801586e /* The delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8015864: 4b36 ldr r3, [pc, #216] @ (8015940 ) 8015866: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801586a: 601a str r2, [r3, #0] break; 801586c: e03f b.n 80158ee { /* The delayed list is not empty, get the value of the item at the head of the delayed list. This is the time at which the task at the head of the delayed list must be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 801586e: 4b31 ldr r3, [pc, #196] @ (8015934 ) 8015870: 681b ldr r3, [r3, #0] 8015872: 68db ldr r3, [r3, #12] 8015874: 68db ldr r3, [r3, #12] 8015876: 60bb str r3, [r7, #8] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); 8015878: 68bb ldr r3, [r7, #8] 801587a: 685b ldr r3, [r3, #4] 801587c: 607b str r3, [r7, #4] if( xConstTickCount < xItemValue ) 801587e: 693a ldr r2, [r7, #16] 8015880: 687b ldr r3, [r7, #4] 8015882: 429a cmp r2, r3 8015884: d203 bcs.n 801588e /* It is not time to unblock this item yet, but the item value is the time at which the task at the head of the blocked list must be removed from the Blocked state - so record the item value in xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; 8015886: 4a2e ldr r2, [pc, #184] @ (8015940 ) 8015888: 687b ldr r3, [r7, #4] 801588a: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ 801588c: e02f b.n 80158ee { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 801588e: 68bb ldr r3, [r7, #8] 8015890: 3304 adds r3, #4 8015892: 4618 mov r0, r3 8015894: f7fe fb06 bl 8013ea4 /* Is the task waiting on an event also? If so remove it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 8015898: 68bb ldr r3, [r7, #8] 801589a: 6a9b ldr r3, [r3, #40] @ 0x28 801589c: 2b00 cmp r3, #0 801589e: d004 beq.n 80158aa { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 80158a0: 68bb ldr r3, [r7, #8] 80158a2: 3318 adds r3, #24 80158a4: 4618 mov r0, r3 80158a6: f7fe fafd bl 8013ea4 mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready list. */ prvAddTaskToReadyList( pxTCB ); 80158aa: 68bb ldr r3, [r7, #8] 80158ac: 6ada ldr r2, [r3, #44] @ 0x2c 80158ae: 4b25 ldr r3, [pc, #148] @ (8015944 ) 80158b0: 681b ldr r3, [r3, #0] 80158b2: 429a cmp r2, r3 80158b4: d903 bls.n 80158be 80158b6: 68bb ldr r3, [r7, #8] 80158b8: 6adb ldr r3, [r3, #44] @ 0x2c 80158ba: 4a22 ldr r2, [pc, #136] @ (8015944 ) 80158bc: 6013 str r3, [r2, #0] 80158be: 68bb ldr r3, [r7, #8] 80158c0: 6ada ldr r2, [r3, #44] @ 0x2c 80158c2: 4613 mov r3, r2 80158c4: 009b lsls r3, r3, #2 80158c6: 4413 add r3, r2 80158c8: 009b lsls r3, r3, #2 80158ca: 4a1f ldr r2, [pc, #124] @ (8015948 ) 80158cc: 441a add r2, r3 80158ce: 68bb ldr r3, [r7, #8] 80158d0: 3304 adds r3, #4 80158d2: 4619 mov r1, r3 80158d4: 4610 mov r0, r2 80158d6: f7fe fa88 bl 8013dea { /* Preemption is on, but a context switch should only be performed if the unblocked task has a priority that is equal to or higher than the currently executing task. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 80158da: 68bb ldr r3, [r7, #8] 80158dc: 6ada ldr r2, [r3, #44] @ 0x2c 80158de: 4b1b ldr r3, [pc, #108] @ (801594c ) 80158e0: 681b ldr r3, [r3, #0] 80158e2: 6adb ldr r3, [r3, #44] @ 0x2c 80158e4: 429a cmp r2, r3 80158e6: d3b8 bcc.n 801585a { xSwitchRequired = pdTRUE; 80158e8: 2301 movs r3, #1 80158ea: 617b str r3, [r7, #20] if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 80158ec: e7b5 b.n 801585a /* Tasks of equal priority to the currently running task will share processing time (time slice) if preemption is on, and the application writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 80158ee: 4b17 ldr r3, [pc, #92] @ (801594c ) 80158f0: 681b ldr r3, [r3, #0] 80158f2: 6ada ldr r2, [r3, #44] @ 0x2c 80158f4: 4914 ldr r1, [pc, #80] @ (8015948 ) 80158f6: 4613 mov r3, r2 80158f8: 009b lsls r3, r3, #2 80158fa: 4413 add r3, r2 80158fc: 009b lsls r3, r3, #2 80158fe: 440b add r3, r1 8015900: 681b ldr r3, [r3, #0] 8015902: 2b01 cmp r3, #1 8015904: d901 bls.n 801590a { xSwitchRequired = pdTRUE; 8015906: 2301 movs r3, #1 8015908: 617b str r3, [r7, #20] } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) 801590a: 4b11 ldr r3, [pc, #68] @ (8015950 ) 801590c: 681b ldr r3, [r3, #0] 801590e: 2b00 cmp r3, #0 8015910: d007 beq.n 8015922 { xSwitchRequired = pdTRUE; 8015912: 2301 movs r3, #1 8015914: 617b str r3, [r7, #20] 8015916: e004 b.n 8015922 } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; 8015918: 4b0e ldr r3, [pc, #56] @ (8015954 ) 801591a: 681b ldr r3, [r3, #0] 801591c: 3301 adds r3, #1 801591e: 4a0d ldr r2, [pc, #52] @ (8015954 ) 8015920: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; 8015922: 697b ldr r3, [r7, #20] } 8015924: 4618 mov r0, r3 8015926: 3718 adds r7, #24 8015928: 46bd mov sp, r7 801592a: bd80 pop {r7, pc} 801592c: 24003050 .word 0x24003050 8015930: 2400302c .word 0x2400302c 8015934: 24002fe0 .word 0x24002fe0 8015938: 24002fe4 .word 0x24002fe4 801593c: 24003040 .word 0x24003040 8015940: 24003048 .word 0x24003048 8015944: 24003030 .word 0x24003030 8015948: 24002b58 .word 0x24002b58 801594c: 24002b54 .word 0x24002b54 8015950: 2400303c .word 0x2400303c 8015954: 24003038 .word 0x24003038 08015958 : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { 8015958: b580 push {r7, lr} 801595a: b084 sub sp, #16 801595c: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) 801595e: 4b32 ldr r3, [pc, #200] @ (8015a28 ) 8015960: 681b ldr r3, [r3, #0] 8015962: 2b00 cmp r3, #0 8015964: d003 beq.n 801596e { /* The scheduler is currently suspended - do not allow a context switch. */ xYieldPending = pdTRUE; 8015966: 4b31 ldr r3, [pc, #196] @ (8015a2c ) 8015968: 2201 movs r2, #1 801596a: 601a str r2, [r3, #0] for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ } } 801596c: e058 b.n 8015a20 xYieldPending = pdFALSE; 801596e: 4b2f ldr r3, [pc, #188] @ (8015a2c ) 8015970: 2200 movs r2, #0 8015972: 601a str r2, [r3, #0] taskCHECK_FOR_STACK_OVERFLOW(); 8015974: 4b2e ldr r3, [pc, #184] @ (8015a30 ) 8015976: 681b ldr r3, [r3, #0] 8015978: 681a ldr r2, [r3, #0] 801597a: 4b2d ldr r3, [pc, #180] @ (8015a30 ) 801597c: 681b ldr r3, [r3, #0] 801597e: 6b1b ldr r3, [r3, #48] @ 0x30 8015980: 429a cmp r2, r3 8015982: d808 bhi.n 8015996 8015984: 4b2a ldr r3, [pc, #168] @ (8015a30 ) 8015986: 681a ldr r2, [r3, #0] 8015988: 4b29 ldr r3, [pc, #164] @ (8015a30 ) 801598a: 681b ldr r3, [r3, #0] 801598c: 3334 adds r3, #52 @ 0x34 801598e: 4619 mov r1, r3 8015990: 4610 mov r0, r2 8015992: f7ea fe75 bl 8000680 taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015996: 4b27 ldr r3, [pc, #156] @ (8015a34 ) 8015998: 681b ldr r3, [r3, #0] 801599a: 60fb str r3, [r7, #12] 801599c: e011 b.n 80159c2 801599e: 68fb ldr r3, [r7, #12] 80159a0: 2b00 cmp r3, #0 80159a2: d10b bne.n 80159bc __asm volatile 80159a4: f04f 0350 mov.w r3, #80 @ 0x50 80159a8: f383 8811 msr BASEPRI, r3 80159ac: f3bf 8f6f isb sy 80159b0: f3bf 8f4f dsb sy 80159b4: 607b str r3, [r7, #4] } 80159b6: bf00 nop 80159b8: bf00 nop 80159ba: e7fd b.n 80159b8 80159bc: 68fb ldr r3, [r7, #12] 80159be: 3b01 subs r3, #1 80159c0: 60fb str r3, [r7, #12] 80159c2: 491d ldr r1, [pc, #116] @ (8015a38 ) 80159c4: 68fa ldr r2, [r7, #12] 80159c6: 4613 mov r3, r2 80159c8: 009b lsls r3, r3, #2 80159ca: 4413 add r3, r2 80159cc: 009b lsls r3, r3, #2 80159ce: 440b add r3, r1 80159d0: 681b ldr r3, [r3, #0] 80159d2: 2b00 cmp r3, #0 80159d4: d0e3 beq.n 801599e 80159d6: 68fa ldr r2, [r7, #12] 80159d8: 4613 mov r3, r2 80159da: 009b lsls r3, r3, #2 80159dc: 4413 add r3, r2 80159de: 009b lsls r3, r3, #2 80159e0: 4a15 ldr r2, [pc, #84] @ (8015a38 ) 80159e2: 4413 add r3, r2 80159e4: 60bb str r3, [r7, #8] 80159e6: 68bb ldr r3, [r7, #8] 80159e8: 685b ldr r3, [r3, #4] 80159ea: 685a ldr r2, [r3, #4] 80159ec: 68bb ldr r3, [r7, #8] 80159ee: 605a str r2, [r3, #4] 80159f0: 68bb ldr r3, [r7, #8] 80159f2: 685a ldr r2, [r3, #4] 80159f4: 68bb ldr r3, [r7, #8] 80159f6: 3308 adds r3, #8 80159f8: 429a cmp r2, r3 80159fa: d104 bne.n 8015a06 80159fc: 68bb ldr r3, [r7, #8] 80159fe: 685b ldr r3, [r3, #4] 8015a00: 685a ldr r2, [r3, #4] 8015a02: 68bb ldr r3, [r7, #8] 8015a04: 605a str r2, [r3, #4] 8015a06: 68bb ldr r3, [r7, #8] 8015a08: 685b ldr r3, [r3, #4] 8015a0a: 68db ldr r3, [r3, #12] 8015a0c: 4a08 ldr r2, [pc, #32] @ (8015a30 ) 8015a0e: 6013 str r3, [r2, #0] 8015a10: 4a08 ldr r2, [pc, #32] @ (8015a34 ) 8015a12: 68fb ldr r3, [r7, #12] 8015a14: 6013 str r3, [r2, #0] _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 8015a16: 4b06 ldr r3, [pc, #24] @ (8015a30 ) 8015a18: 681b ldr r3, [r3, #0] 8015a1a: 3354 adds r3, #84 @ 0x54 8015a1c: 4a07 ldr r2, [pc, #28] @ (8015a3c ) 8015a1e: 6013 str r3, [r2, #0] } 8015a20: bf00 nop 8015a22: 3710 adds r7, #16 8015a24: 46bd mov sp, r7 8015a26: bd80 pop {r7, pc} 8015a28: 24003050 .word 0x24003050 8015a2c: 2400303c .word 0x2400303c 8015a30: 24002b54 .word 0x24002b54 8015a34: 24003030 .word 0x24003030 8015a38: 24002b58 .word 0x24002b58 8015a3c: 24000054 .word 0x24000054 08015a40 : /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { 8015a40: b580 push {r7, lr} 8015a42: b084 sub sp, #16 8015a44: af00 add r7, sp, #0 8015a46: 6078 str r0, [r7, #4] 8015a48: 6039 str r1, [r7, #0] configASSERT( pxEventList ); 8015a4a: 687b ldr r3, [r7, #4] 8015a4c: 2b00 cmp r3, #0 8015a4e: d10b bne.n 8015a68 __asm volatile 8015a50: f04f 0350 mov.w r3, #80 @ 0x50 8015a54: f383 8811 msr BASEPRI, r3 8015a58: f3bf 8f6f isb sy 8015a5c: f3bf 8f4f dsb sy 8015a60: 60fb str r3, [r7, #12] } 8015a62: bf00 nop 8015a64: bf00 nop 8015a66: e7fd b.n 8015a64 /* Place the event list item of the TCB in the appropriate event list. This is placed in the list in priority order so the highest priority task is the first to be woken by the event. The queue that contains the event list is locked, preventing simultaneous access from interrupts. */ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 8015a68: 4b07 ldr r3, [pc, #28] @ (8015a88 ) 8015a6a: 681b ldr r3, [r3, #0] 8015a6c: 3318 adds r3, #24 8015a6e: 4619 mov r1, r3 8015a70: 6878 ldr r0, [r7, #4] 8015a72: f7fe f9de bl 8013e32 prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 8015a76: 2101 movs r1, #1 8015a78: 6838 ldr r0, [r7, #0] 8015a7a: f000 fded bl 8016658 } 8015a7e: bf00 nop 8015a80: 3710 adds r7, #16 8015a82: 46bd mov sp, r7 8015a84: bd80 pop {r7, pc} 8015a86: bf00 nop 8015a88: 24002b54 .word 0x24002b54 08015a8c : /*-----------------------------------------------------------*/ #if( configUSE_TIMERS == 1 ) void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 8015a8c: b580 push {r7, lr} 8015a8e: b086 sub sp, #24 8015a90: af00 add r7, sp, #0 8015a92: 60f8 str r0, [r7, #12] 8015a94: 60b9 str r1, [r7, #8] 8015a96: 607a str r2, [r7, #4] configASSERT( pxEventList ); 8015a98: 68fb ldr r3, [r7, #12] 8015a9a: 2b00 cmp r3, #0 8015a9c: d10b bne.n 8015ab6 __asm volatile 8015a9e: f04f 0350 mov.w r3, #80 @ 0x50 8015aa2: f383 8811 msr BASEPRI, r3 8015aa6: f3bf 8f6f isb sy 8015aaa: f3bf 8f4f dsb sy 8015aae: 617b str r3, [r7, #20] } 8015ab0: bf00 nop 8015ab2: bf00 nop 8015ab4: e7fd b.n 8015ab2 /* Place the event list item of the TCB in the appropriate event list. In this case it is assume that this is the only task that is going to be waiting on this event list, so the faster vListInsertEnd() function can be used in place of vListInsert. */ vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 8015ab6: 4b0a ldr r3, [pc, #40] @ (8015ae0 ) 8015ab8: 681b ldr r3, [r3, #0] 8015aba: 3318 adds r3, #24 8015abc: 4619 mov r1, r3 8015abe: 68f8 ldr r0, [r7, #12] 8015ac0: f7fe f993 bl 8013dea /* If the task should block indefinitely then set the block time to a value that will be recognised as an indefinite delay inside the prvAddCurrentTaskToDelayedList() function. */ if( xWaitIndefinitely != pdFALSE ) 8015ac4: 687b ldr r3, [r7, #4] 8015ac6: 2b00 cmp r3, #0 8015ac8: d002 beq.n 8015ad0 { xTicksToWait = portMAX_DELAY; 8015aca: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8015ace: 60bb str r3, [r7, #8] } traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); 8015ad0: 6879 ldr r1, [r7, #4] 8015ad2: 68b8 ldr r0, [r7, #8] 8015ad4: f000 fdc0 bl 8016658 } 8015ad8: bf00 nop 8015ada: 3718 adds r7, #24 8015adc: 46bd mov sp, r7 8015ade: bd80 pop {r7, pc} 8015ae0: 24002b54 .word 0x24002b54 08015ae4 : #endif /* configUSE_TIMERS */ /*-----------------------------------------------------------*/ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { 8015ae4: b580 push {r7, lr} 8015ae6: b086 sub sp, #24 8015ae8: af00 add r7, sp, #0 8015aea: 6078 str r0, [r7, #4] get called - the lock count on the queue will get modified instead. This means exclusive access to the event list is guaranteed here. This function assumes that a check has already been made to ensure that pxEventList is not empty. */ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015aec: 687b ldr r3, [r7, #4] 8015aee: 68db ldr r3, [r3, #12] 8015af0: 68db ldr r3, [r3, #12] 8015af2: 613b str r3, [r7, #16] configASSERT( pxUnblockedTCB ); 8015af4: 693b ldr r3, [r7, #16] 8015af6: 2b00 cmp r3, #0 8015af8: d10b bne.n 8015b12 __asm volatile 8015afa: f04f 0350 mov.w r3, #80 @ 0x50 8015afe: f383 8811 msr BASEPRI, r3 8015b02: f3bf 8f6f isb sy 8015b06: f3bf 8f4f dsb sy 8015b0a: 60fb str r3, [r7, #12] } 8015b0c: bf00 nop 8015b0e: bf00 nop 8015b10: e7fd b.n 8015b0e ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); 8015b12: 693b ldr r3, [r7, #16] 8015b14: 3318 adds r3, #24 8015b16: 4618 mov r0, r3 8015b18: f7fe f9c4 bl 8013ea4 if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8015b1c: 4b1d ldr r3, [pc, #116] @ (8015b94 ) 8015b1e: 681b ldr r3, [r3, #0] 8015b20: 2b00 cmp r3, #0 8015b22: d11d bne.n 8015b60 { ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); 8015b24: 693b ldr r3, [r7, #16] 8015b26: 3304 adds r3, #4 8015b28: 4618 mov r0, r3 8015b2a: f7fe f9bb bl 8013ea4 prvAddTaskToReadyList( pxUnblockedTCB ); 8015b2e: 693b ldr r3, [r7, #16] 8015b30: 6ada ldr r2, [r3, #44] @ 0x2c 8015b32: 4b19 ldr r3, [pc, #100] @ (8015b98 ) 8015b34: 681b ldr r3, [r3, #0] 8015b36: 429a cmp r2, r3 8015b38: d903 bls.n 8015b42 8015b3a: 693b ldr r3, [r7, #16] 8015b3c: 6adb ldr r3, [r3, #44] @ 0x2c 8015b3e: 4a16 ldr r2, [pc, #88] @ (8015b98 ) 8015b40: 6013 str r3, [r2, #0] 8015b42: 693b ldr r3, [r7, #16] 8015b44: 6ada ldr r2, [r3, #44] @ 0x2c 8015b46: 4613 mov r3, r2 8015b48: 009b lsls r3, r3, #2 8015b4a: 4413 add r3, r2 8015b4c: 009b lsls r3, r3, #2 8015b4e: 4a13 ldr r2, [pc, #76] @ (8015b9c ) 8015b50: 441a add r2, r3 8015b52: 693b ldr r3, [r7, #16] 8015b54: 3304 adds r3, #4 8015b56: 4619 mov r1, r3 8015b58: 4610 mov r0, r2 8015b5a: f7fe f946 bl 8013dea 8015b5e: e005 b.n 8015b6c } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); 8015b60: 693b ldr r3, [r7, #16] 8015b62: 3318 adds r3, #24 8015b64: 4619 mov r1, r3 8015b66: 480e ldr r0, [pc, #56] @ (8015ba0 ) 8015b68: f7fe f93f bl 8013dea } if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) 8015b6c: 693b ldr r3, [r7, #16] 8015b6e: 6ada ldr r2, [r3, #44] @ 0x2c 8015b70: 4b0c ldr r3, [pc, #48] @ (8015ba4 ) 8015b72: 681b ldr r3, [r3, #0] 8015b74: 6adb ldr r3, [r3, #44] @ 0x2c 8015b76: 429a cmp r2, r3 8015b78: d905 bls.n 8015b86 { /* Return true if the task removed from the event list has a higher priority than the calling task. This allows the calling task to know if it should force a context switch now. */ xReturn = pdTRUE; 8015b7a: 2301 movs r3, #1 8015b7c: 617b str r3, [r7, #20] /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 8015b7e: 4b0a ldr r3, [pc, #40] @ (8015ba8 ) 8015b80: 2201 movs r2, #1 8015b82: 601a str r2, [r3, #0] 8015b84: e001 b.n 8015b8a } else { xReturn = pdFALSE; 8015b86: 2300 movs r3, #0 8015b88: 617b str r3, [r7, #20] } return xReturn; 8015b8a: 697b ldr r3, [r7, #20] } 8015b8c: 4618 mov r0, r3 8015b8e: 3718 adds r7, #24 8015b90: 46bd mov sp, r7 8015b92: bd80 pop {r7, pc} 8015b94: 24003050 .word 0x24003050 8015b98: 24003030 .word 0x24003030 8015b9c: 24002b58 .word 0x24002b58 8015ba0: 24002fe8 .word 0x24002fe8 8015ba4: 24002b54 .word 0x24002b54 8015ba8: 2400303c .word 0x2400303c 08015bac : } } /*-----------------------------------------------------------*/ void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) { 8015bac: b580 push {r7, lr} 8015bae: b084 sub sp, #16 8015bb0: af00 add r7, sp, #0 8015bb2: 6078 str r0, [r7, #4] configASSERT( pxTimeOut ); 8015bb4: 687b ldr r3, [r7, #4] 8015bb6: 2b00 cmp r3, #0 8015bb8: d10b bne.n 8015bd2 __asm volatile 8015bba: f04f 0350 mov.w r3, #80 @ 0x50 8015bbe: f383 8811 msr BASEPRI, r3 8015bc2: f3bf 8f6f isb sy 8015bc6: f3bf 8f4f dsb sy 8015bca: 60fb str r3, [r7, #12] } 8015bcc: bf00 nop 8015bce: bf00 nop 8015bd0: e7fd b.n 8015bce taskENTER_CRITICAL(); 8015bd2: f001 fb09 bl 80171e8 { pxTimeOut->xOverflowCount = xNumOfOverflows; 8015bd6: 4b07 ldr r3, [pc, #28] @ (8015bf4 ) 8015bd8: 681a ldr r2, [r3, #0] 8015bda: 687b ldr r3, [r7, #4] 8015bdc: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 8015bde: 4b06 ldr r3, [pc, #24] @ (8015bf8 ) 8015be0: 681a ldr r2, [r3, #0] 8015be2: 687b ldr r3, [r7, #4] 8015be4: 605a str r2, [r3, #4] } taskEXIT_CRITICAL(); 8015be6: f001 fb31 bl 801724c } 8015bea: bf00 nop 8015bec: 3710 adds r7, #16 8015bee: 46bd mov sp, r7 8015bf0: bd80 pop {r7, pc} 8015bf2: bf00 nop 8015bf4: 24003040 .word 0x24003040 8015bf8: 2400302c .word 0x2400302c 08015bfc : /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { 8015bfc: b480 push {r7} 8015bfe: b083 sub sp, #12 8015c00: af00 add r7, sp, #0 8015c02: 6078 str r0, [r7, #4] /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; 8015c04: 4b06 ldr r3, [pc, #24] @ (8015c20 ) 8015c06: 681a ldr r2, [r3, #0] 8015c08: 687b ldr r3, [r7, #4] 8015c0a: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 8015c0c: 4b05 ldr r3, [pc, #20] @ (8015c24 ) 8015c0e: 681a ldr r2, [r3, #0] 8015c10: 687b ldr r3, [r7, #4] 8015c12: 605a str r2, [r3, #4] } 8015c14: bf00 nop 8015c16: 370c adds r7, #12 8015c18: 46bd mov sp, r7 8015c1a: f85d 7b04 ldr.w r7, [sp], #4 8015c1e: 4770 bx lr 8015c20: 24003040 .word 0x24003040 8015c24: 2400302c .word 0x2400302c 08015c28 : /*-----------------------------------------------------------*/ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) { 8015c28: b580 push {r7, lr} 8015c2a: b088 sub sp, #32 8015c2c: af00 add r7, sp, #0 8015c2e: 6078 str r0, [r7, #4] 8015c30: 6039 str r1, [r7, #0] BaseType_t xReturn; configASSERT( pxTimeOut ); 8015c32: 687b ldr r3, [r7, #4] 8015c34: 2b00 cmp r3, #0 8015c36: d10b bne.n 8015c50 __asm volatile 8015c38: f04f 0350 mov.w r3, #80 @ 0x50 8015c3c: f383 8811 msr BASEPRI, r3 8015c40: f3bf 8f6f isb sy 8015c44: f3bf 8f4f dsb sy 8015c48: 613b str r3, [r7, #16] } 8015c4a: bf00 nop 8015c4c: bf00 nop 8015c4e: e7fd b.n 8015c4c configASSERT( pxTicksToWait ); 8015c50: 683b ldr r3, [r7, #0] 8015c52: 2b00 cmp r3, #0 8015c54: d10b bne.n 8015c6e __asm volatile 8015c56: f04f 0350 mov.w r3, #80 @ 0x50 8015c5a: f383 8811 msr BASEPRI, r3 8015c5e: f3bf 8f6f isb sy 8015c62: f3bf 8f4f dsb sy 8015c66: 60fb str r3, [r7, #12] } 8015c68: bf00 nop 8015c6a: bf00 nop 8015c6c: e7fd b.n 8015c6a taskENTER_CRITICAL(); 8015c6e: f001 fabb bl 80171e8 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; 8015c72: 4b1d ldr r3, [pc, #116] @ (8015ce8 ) 8015c74: 681b ldr r3, [r3, #0] 8015c76: 61bb str r3, [r7, #24] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; 8015c78: 687b ldr r3, [r7, #4] 8015c7a: 685b ldr r3, [r3, #4] 8015c7c: 69ba ldr r2, [r7, #24] 8015c7e: 1ad3 subs r3, r2, r3 8015c80: 617b str r3, [r7, #20] } else #endif #if ( INCLUDE_vTaskSuspend == 1 ) if( *pxTicksToWait == portMAX_DELAY ) 8015c82: 683b ldr r3, [r7, #0] 8015c84: 681b ldr r3, [r3, #0] 8015c86: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015c8a: d102 bne.n 8015c92 { /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is the maximum block time then the task should block indefinitely, and therefore never time out. */ xReturn = pdFALSE; 8015c8c: 2300 movs r3, #0 8015c8e: 61fb str r3, [r7, #28] 8015c90: e023 b.n 8015cda } else #endif if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ 8015c92: 687b ldr r3, [r7, #4] 8015c94: 681a ldr r2, [r3, #0] 8015c96: 4b15 ldr r3, [pc, #84] @ (8015cec ) 8015c98: 681b ldr r3, [r3, #0] 8015c9a: 429a cmp r2, r3 8015c9c: d007 beq.n 8015cae 8015c9e: 687b ldr r3, [r7, #4] 8015ca0: 685b ldr r3, [r3, #4] 8015ca2: 69ba ldr r2, [r7, #24] 8015ca4: 429a cmp r2, r3 8015ca6: d302 bcc.n 8015cae /* The tick count is greater than the time at which vTaskSetTimeout() was called, but has also overflowed since vTaskSetTimeOut() was called. It must have wrapped all the way around and gone past again. This passed since vTaskSetTimeout() was called. */ xReturn = pdTRUE; 8015ca8: 2301 movs r3, #1 8015caa: 61fb str r3, [r7, #28] 8015cac: e015 b.n 8015cda } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ 8015cae: 683b ldr r3, [r7, #0] 8015cb0: 681b ldr r3, [r3, #0] 8015cb2: 697a ldr r2, [r7, #20] 8015cb4: 429a cmp r2, r3 8015cb6: d20b bcs.n 8015cd0 { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; 8015cb8: 683b ldr r3, [r7, #0] 8015cba: 681a ldr r2, [r3, #0] 8015cbc: 697b ldr r3, [r7, #20] 8015cbe: 1ad2 subs r2, r2, r3 8015cc0: 683b ldr r3, [r7, #0] 8015cc2: 601a str r2, [r3, #0] vTaskInternalSetTimeOutState( pxTimeOut ); 8015cc4: 6878 ldr r0, [r7, #4] 8015cc6: f7ff ff99 bl 8015bfc xReturn = pdFALSE; 8015cca: 2300 movs r3, #0 8015ccc: 61fb str r3, [r7, #28] 8015cce: e004 b.n 8015cda } else { *pxTicksToWait = 0; 8015cd0: 683b ldr r3, [r7, #0] 8015cd2: 2200 movs r2, #0 8015cd4: 601a str r2, [r3, #0] xReturn = pdTRUE; 8015cd6: 2301 movs r3, #1 8015cd8: 61fb str r3, [r7, #28] } } taskEXIT_CRITICAL(); 8015cda: f001 fab7 bl 801724c return xReturn; 8015cde: 69fb ldr r3, [r7, #28] } 8015ce0: 4618 mov r0, r3 8015ce2: 3720 adds r7, #32 8015ce4: 46bd mov sp, r7 8015ce6: bd80 pop {r7, pc} 8015ce8: 2400302c .word 0x2400302c 8015cec: 24003040 .word 0x24003040 08015cf0 : /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { 8015cf0: b480 push {r7} 8015cf2: af00 add r7, sp, #0 xYieldPending = pdTRUE; 8015cf4: 4b03 ldr r3, [pc, #12] @ (8015d04 ) 8015cf6: 2201 movs r2, #1 8015cf8: 601a str r2, [r3, #0] } 8015cfa: bf00 nop 8015cfc: 46bd mov sp, r7 8015cfe: f85d 7b04 ldr.w r7, [sp], #4 8015d02: 4770 bx lr 8015d04: 2400303c .word 0x2400303c 08015d08 : * * void prvIdleTask( void *pvParameters ); * */ static portTASK_FUNCTION( prvIdleTask, pvParameters ) { 8015d08: b580 push {r7, lr} 8015d0a: b082 sub sp, #8 8015d0c: af00 add r7, sp, #0 8015d0e: 6078 str r0, [r7, #4] for( ;; ) { /* See if any tasks have deleted themselves - if so then the idle task is responsible for freeing the deleted task's TCB and stack. */ prvCheckTasksWaitingTermination(); 8015d10: f000 f852 bl 8015db8 A critical region is not required here as we are just reading from the list, and an occasional incorrect value will not matter. If the ready list at the idle priority contains more than one task then a task other than the idle task is ready to execute. */ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) 8015d14: 4b06 ldr r3, [pc, #24] @ (8015d30 ) 8015d16: 681b ldr r3, [r3, #0] 8015d18: 2b01 cmp r3, #1 8015d1a: d9f9 bls.n 8015d10 { taskYIELD(); 8015d1c: 4b05 ldr r3, [pc, #20] @ (8015d34 ) 8015d1e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015d22: 601a str r2, [r3, #0] 8015d24: f3bf 8f4f dsb sy 8015d28: f3bf 8f6f isb sy prvCheckTasksWaitingTermination(); 8015d2c: e7f0 b.n 8015d10 8015d2e: bf00 nop 8015d30: 24002b58 .word 0x24002b58 8015d34: e000ed04 .word 0xe000ed04 08015d38 : #endif /* portUSING_MPU_WRAPPERS */ /*-----------------------------------------------------------*/ static void prvInitialiseTaskLists( void ) { 8015d38: b580 push {r7, lr} 8015d3a: b082 sub sp, #8 8015d3c: af00 add r7, sp, #0 UBaseType_t uxPriority; for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 8015d3e: 2300 movs r3, #0 8015d40: 607b str r3, [r7, #4] 8015d42: e00c b.n 8015d5e { vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); 8015d44: 687a ldr r2, [r7, #4] 8015d46: 4613 mov r3, r2 8015d48: 009b lsls r3, r3, #2 8015d4a: 4413 add r3, r2 8015d4c: 009b lsls r3, r3, #2 8015d4e: 4a12 ldr r2, [pc, #72] @ (8015d98 ) 8015d50: 4413 add r3, r2 8015d52: 4618 mov r0, r3 8015d54: f7fe f81c bl 8013d90 for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 8015d58: 687b ldr r3, [r7, #4] 8015d5a: 3301 adds r3, #1 8015d5c: 607b str r3, [r7, #4] 8015d5e: 687b ldr r3, [r7, #4] 8015d60: 2b37 cmp r3, #55 @ 0x37 8015d62: d9ef bls.n 8015d44 } vListInitialise( &xDelayedTaskList1 ); 8015d64: 480d ldr r0, [pc, #52] @ (8015d9c ) 8015d66: f7fe f813 bl 8013d90 vListInitialise( &xDelayedTaskList2 ); 8015d6a: 480d ldr r0, [pc, #52] @ (8015da0 ) 8015d6c: f7fe f810 bl 8013d90 vListInitialise( &xPendingReadyList ); 8015d70: 480c ldr r0, [pc, #48] @ (8015da4 ) 8015d72: f7fe f80d bl 8013d90 #if ( INCLUDE_vTaskDelete == 1 ) { vListInitialise( &xTasksWaitingTermination ); 8015d76: 480c ldr r0, [pc, #48] @ (8015da8 ) 8015d78: f7fe f80a bl 8013d90 } #endif /* INCLUDE_vTaskDelete */ #if ( INCLUDE_vTaskSuspend == 1 ) { vListInitialise( &xSuspendedTaskList ); 8015d7c: 480b ldr r0, [pc, #44] @ (8015dac ) 8015d7e: f7fe f807 bl 8013d90 } #endif /* INCLUDE_vTaskSuspend */ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList using list2. */ pxDelayedTaskList = &xDelayedTaskList1; 8015d82: 4b0b ldr r3, [pc, #44] @ (8015db0 ) 8015d84: 4a05 ldr r2, [pc, #20] @ (8015d9c ) 8015d86: 601a str r2, [r3, #0] pxOverflowDelayedTaskList = &xDelayedTaskList2; 8015d88: 4b0a ldr r3, [pc, #40] @ (8015db4 ) 8015d8a: 4a05 ldr r2, [pc, #20] @ (8015da0 ) 8015d8c: 601a str r2, [r3, #0] } 8015d8e: bf00 nop 8015d90: 3708 adds r7, #8 8015d92: 46bd mov sp, r7 8015d94: bd80 pop {r7, pc} 8015d96: bf00 nop 8015d98: 24002b58 .word 0x24002b58 8015d9c: 24002fb8 .word 0x24002fb8 8015da0: 24002fcc .word 0x24002fcc 8015da4: 24002fe8 .word 0x24002fe8 8015da8: 24002ffc .word 0x24002ffc 8015dac: 24003014 .word 0x24003014 8015db0: 24002fe0 .word 0x24002fe0 8015db4: 24002fe4 .word 0x24002fe4 08015db8 : /*-----------------------------------------------------------*/ static void prvCheckTasksWaitingTermination( void ) { 8015db8: b580 push {r7, lr} 8015dba: b082 sub sp, #8 8015dbc: af00 add r7, sp, #0 { TCB_t *pxTCB; /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 8015dbe: e019 b.n 8015df4 { taskENTER_CRITICAL(); 8015dc0: f001 fa12 bl 80171e8 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015dc4: 4b10 ldr r3, [pc, #64] @ (8015e08 ) 8015dc6: 68db ldr r3, [r3, #12] 8015dc8: 68db ldr r3, [r3, #12] 8015dca: 607b str r3, [r7, #4] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8015dcc: 687b ldr r3, [r7, #4] 8015dce: 3304 adds r3, #4 8015dd0: 4618 mov r0, r3 8015dd2: f7fe f867 bl 8013ea4 --uxCurrentNumberOfTasks; 8015dd6: 4b0d ldr r3, [pc, #52] @ (8015e0c ) 8015dd8: 681b ldr r3, [r3, #0] 8015dda: 3b01 subs r3, #1 8015ddc: 4a0b ldr r2, [pc, #44] @ (8015e0c ) 8015dde: 6013 str r3, [r2, #0] --uxDeletedTasksWaitingCleanUp; 8015de0: 4b0b ldr r3, [pc, #44] @ (8015e10 ) 8015de2: 681b ldr r3, [r3, #0] 8015de4: 3b01 subs r3, #1 8015de6: 4a0a ldr r2, [pc, #40] @ (8015e10 ) 8015de8: 6013 str r3, [r2, #0] } taskEXIT_CRITICAL(); 8015dea: f001 fa2f bl 801724c prvDeleteTCB( pxTCB ); 8015dee: 6878 ldr r0, [r7, #4] 8015df0: f000 f810 bl 8015e14 while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 8015df4: 4b06 ldr r3, [pc, #24] @ (8015e10 ) 8015df6: 681b ldr r3, [r3, #0] 8015df8: 2b00 cmp r3, #0 8015dfa: d1e1 bne.n 8015dc0 } } #endif /* INCLUDE_vTaskDelete */ } 8015dfc: bf00 nop 8015dfe: bf00 nop 8015e00: 3708 adds r7, #8 8015e02: 46bd mov sp, r7 8015e04: bd80 pop {r7, pc} 8015e06: bf00 nop 8015e08: 24002ffc .word 0x24002ffc 8015e0c: 24003028 .word 0x24003028 8015e10: 24003010 .word 0x24003010 08015e14 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelete == 1 ) static void prvDeleteTCB( TCB_t *pxTCB ) { 8015e14: b580 push {r7, lr} 8015e16: b084 sub sp, #16 8015e18: af00 add r7, sp, #0 8015e1a: 6078 str r0, [r7, #4] to the task to free any memory allocated at the application level. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ #if ( configUSE_NEWLIB_REENTRANT == 1 ) { _reclaim_reent( &( pxTCB->xNewLib_reent ) ); 8015e1c: 687b ldr r3, [r7, #4] 8015e1e: 3354 adds r3, #84 @ 0x54 8015e20: 4618 mov r0, r3 8015e22: f002 fb3d bl 80184a0 <_reclaim_reent> #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* The task could have been allocated statically or dynamically, so check what was statically allocated before trying to free the memory. */ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) 8015e26: 687b ldr r3, [r7, #4] 8015e28: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8015e2c: 2b00 cmp r3, #0 8015e2e: d108 bne.n 8015e42 { /* Both the stack and TCB were allocated dynamically, so both must be freed. */ vPortFree( pxTCB->pxStack ); 8015e30: 687b ldr r3, [r7, #4] 8015e32: 6b1b ldr r3, [r3, #48] @ 0x30 8015e34: 4618 mov r0, r3 8015e36: f001 fbc7 bl 80175c8 vPortFree( pxTCB ); 8015e3a: 6878 ldr r0, [r7, #4] 8015e3c: f001 fbc4 bl 80175c8 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); mtCOVERAGE_TEST_MARKER(); } } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } 8015e40: e019 b.n 8015e76 else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) 8015e42: 687b ldr r3, [r7, #4] 8015e44: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8015e48: 2b01 cmp r3, #1 8015e4a: d103 bne.n 8015e54 vPortFree( pxTCB ); 8015e4c: 6878 ldr r0, [r7, #4] 8015e4e: f001 fbbb bl 80175c8 } 8015e52: e010 b.n 8015e76 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); 8015e54: 687b ldr r3, [r7, #4] 8015e56: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8015e5a: 2b02 cmp r3, #2 8015e5c: d00b beq.n 8015e76 __asm volatile 8015e5e: f04f 0350 mov.w r3, #80 @ 0x50 8015e62: f383 8811 msr BASEPRI, r3 8015e66: f3bf 8f6f isb sy 8015e6a: f3bf 8f4f dsb sy 8015e6e: 60fb str r3, [r7, #12] } 8015e70: bf00 nop 8015e72: bf00 nop 8015e74: e7fd b.n 8015e72 } 8015e76: bf00 nop 8015e78: 3710 adds r7, #16 8015e7a: 46bd mov sp, r7 8015e7c: bd80 pop {r7, pc} ... 08015e80 : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { 8015e80: b480 push {r7} 8015e82: b083 sub sp, #12 8015e84: af00 add r7, sp, #0 TCB_t *pxTCB; if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8015e86: 4b0c ldr r3, [pc, #48] @ (8015eb8 ) 8015e88: 681b ldr r3, [r3, #0] 8015e8a: 681b ldr r3, [r3, #0] 8015e8c: 2b00 cmp r3, #0 8015e8e: d104 bne.n 8015e9a { /* The new current delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass until there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; 8015e90: 4b0a ldr r3, [pc, #40] @ (8015ebc ) 8015e92: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8015e96: 601a str r2, [r3, #0] which the task at the head of the delayed list should be removed from the Blocked state. */ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); } } 8015e98: e008 b.n 8015eac ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015e9a: 4b07 ldr r3, [pc, #28] @ (8015eb8 ) 8015e9c: 681b ldr r3, [r3, #0] 8015e9e: 68db ldr r3, [r3, #12] 8015ea0: 68db ldr r3, [r3, #12] 8015ea2: 607b str r3, [r7, #4] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 8015ea4: 687b ldr r3, [r7, #4] 8015ea6: 685b ldr r3, [r3, #4] 8015ea8: 4a04 ldr r2, [pc, #16] @ (8015ebc ) 8015eaa: 6013 str r3, [r2, #0] } 8015eac: bf00 nop 8015eae: 370c adds r7, #12 8015eb0: 46bd mov sp, r7 8015eb2: f85d 7b04 ldr.w r7, [sp], #4 8015eb6: 4770 bx lr 8015eb8: 24002fe0 .word 0x24002fe0 8015ebc: 24003048 .word 0x24003048 08015ec0 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) TaskHandle_t xTaskGetCurrentTaskHandle( void ) { 8015ec0: b480 push {r7} 8015ec2: b083 sub sp, #12 8015ec4: af00 add r7, sp, #0 TaskHandle_t xReturn; /* A critical section is not required as this is not called from an interrupt and the current TCB will always be the same for any individual execution thread. */ xReturn = pxCurrentTCB; 8015ec6: 4b05 ldr r3, [pc, #20] @ (8015edc ) 8015ec8: 681b ldr r3, [r3, #0] 8015eca: 607b str r3, [r7, #4] return xReturn; 8015ecc: 687b ldr r3, [r7, #4] } 8015ece: 4618 mov r0, r3 8015ed0: 370c adds r7, #12 8015ed2: 46bd mov sp, r7 8015ed4: f85d 7b04 ldr.w r7, [sp], #4 8015ed8: 4770 bx lr 8015eda: bf00 nop 8015edc: 24002b54 .word 0x24002b54 08015ee0 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) BaseType_t xTaskGetSchedulerState( void ) { 8015ee0: b480 push {r7} 8015ee2: b083 sub sp, #12 8015ee4: af00 add r7, sp, #0 BaseType_t xReturn; if( xSchedulerRunning == pdFALSE ) 8015ee6: 4b0b ldr r3, [pc, #44] @ (8015f14 ) 8015ee8: 681b ldr r3, [r3, #0] 8015eea: 2b00 cmp r3, #0 8015eec: d102 bne.n 8015ef4 { xReturn = taskSCHEDULER_NOT_STARTED; 8015eee: 2301 movs r3, #1 8015ef0: 607b str r3, [r7, #4] 8015ef2: e008 b.n 8015f06 } else { if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8015ef4: 4b08 ldr r3, [pc, #32] @ (8015f18 ) 8015ef6: 681b ldr r3, [r3, #0] 8015ef8: 2b00 cmp r3, #0 8015efa: d102 bne.n 8015f02 { xReturn = taskSCHEDULER_RUNNING; 8015efc: 2302 movs r3, #2 8015efe: 607b str r3, [r7, #4] 8015f00: e001 b.n 8015f06 } else { xReturn = taskSCHEDULER_SUSPENDED; 8015f02: 2300 movs r3, #0 8015f04: 607b str r3, [r7, #4] } } return xReturn; 8015f06: 687b ldr r3, [r7, #4] } 8015f08: 4618 mov r0, r3 8015f0a: 370c adds r7, #12 8015f0c: 46bd mov sp, r7 8015f0e: f85d 7b04 ldr.w r7, [sp], #4 8015f12: 4770 bx lr 8015f14: 24003034 .word 0x24003034 8015f18: 24003050 .word 0x24003050 08015f1c : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) { 8015f1c: b580 push {r7, lr} 8015f1e: b084 sub sp, #16 8015f20: af00 add r7, sp, #0 8015f22: 6078 str r0, [r7, #4] TCB_t * const pxMutexHolderTCB = pxMutexHolder; 8015f24: 687b ldr r3, [r7, #4] 8015f26: 60bb str r3, [r7, #8] BaseType_t xReturn = pdFALSE; 8015f28: 2300 movs r3, #0 8015f2a: 60fb str r3, [r7, #12] /* If the mutex was given back by an interrupt while the queue was locked then the mutex holder might now be NULL. _RB_ Is this still needed as interrupts can no longer use mutexes? */ if( pxMutexHolder != NULL ) 8015f2c: 687b ldr r3, [r7, #4] 8015f2e: 2b00 cmp r3, #0 8015f30: d051 beq.n 8015fd6 { /* If the holder of the mutex has a priority below the priority of the task attempting to obtain the mutex then it will temporarily inherit the priority of the task attempting to obtain the mutex. */ if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) 8015f32: 68bb ldr r3, [r7, #8] 8015f34: 6ada ldr r2, [r3, #44] @ 0x2c 8015f36: 4b2a ldr r3, [pc, #168] @ (8015fe0 ) 8015f38: 681b ldr r3, [r3, #0] 8015f3a: 6adb ldr r3, [r3, #44] @ 0x2c 8015f3c: 429a cmp r2, r3 8015f3e: d241 bcs.n 8015fc4 { /* Adjust the mutex holder state to account for its new priority. Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 8015f40: 68bb ldr r3, [r7, #8] 8015f42: 699b ldr r3, [r3, #24] 8015f44: 2b00 cmp r3, #0 8015f46: db06 blt.n 8015f56 { listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8015f48: 4b25 ldr r3, [pc, #148] @ (8015fe0 ) 8015f4a: 681b ldr r3, [r3, #0] 8015f4c: 6adb ldr r3, [r3, #44] @ 0x2c 8015f4e: f1c3 0238 rsb r2, r3, #56 @ 0x38 8015f52: 68bb ldr r3, [r7, #8] 8015f54: 619a str r2, [r3, #24] mtCOVERAGE_TEST_MARKER(); } /* If the task being modified is in the ready state it will need to be moved into a new list. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) 8015f56: 68bb ldr r3, [r7, #8] 8015f58: 6959 ldr r1, [r3, #20] 8015f5a: 68bb ldr r3, [r7, #8] 8015f5c: 6ada ldr r2, [r3, #44] @ 0x2c 8015f5e: 4613 mov r3, r2 8015f60: 009b lsls r3, r3, #2 8015f62: 4413 add r3, r2 8015f64: 009b lsls r3, r3, #2 8015f66: 4a1f ldr r2, [pc, #124] @ (8015fe4 ) 8015f68: 4413 add r3, r2 8015f6a: 4299 cmp r1, r3 8015f6c: d122 bne.n 8015fb4 { if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8015f6e: 68bb ldr r3, [r7, #8] 8015f70: 3304 adds r3, #4 8015f72: 4618 mov r0, r3 8015f74: f7fd ff96 bl 8013ea4 { mtCOVERAGE_TEST_MARKER(); } /* Inherit the priority before being moved into the new list. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8015f78: 4b19 ldr r3, [pc, #100] @ (8015fe0 ) 8015f7a: 681b ldr r3, [r3, #0] 8015f7c: 6ada ldr r2, [r3, #44] @ 0x2c 8015f7e: 68bb ldr r3, [r7, #8] 8015f80: 62da str r2, [r3, #44] @ 0x2c prvAddTaskToReadyList( pxMutexHolderTCB ); 8015f82: 68bb ldr r3, [r7, #8] 8015f84: 6ada ldr r2, [r3, #44] @ 0x2c 8015f86: 4b18 ldr r3, [pc, #96] @ (8015fe8 ) 8015f88: 681b ldr r3, [r3, #0] 8015f8a: 429a cmp r2, r3 8015f8c: d903 bls.n 8015f96 8015f8e: 68bb ldr r3, [r7, #8] 8015f90: 6adb ldr r3, [r3, #44] @ 0x2c 8015f92: 4a15 ldr r2, [pc, #84] @ (8015fe8 ) 8015f94: 6013 str r3, [r2, #0] 8015f96: 68bb ldr r3, [r7, #8] 8015f98: 6ada ldr r2, [r3, #44] @ 0x2c 8015f9a: 4613 mov r3, r2 8015f9c: 009b lsls r3, r3, #2 8015f9e: 4413 add r3, r2 8015fa0: 009b lsls r3, r3, #2 8015fa2: 4a10 ldr r2, [pc, #64] @ (8015fe4 ) 8015fa4: 441a add r2, r3 8015fa6: 68bb ldr r3, [r7, #8] 8015fa8: 3304 adds r3, #4 8015faa: 4619 mov r1, r3 8015fac: 4610 mov r0, r2 8015fae: f7fd ff1c bl 8013dea 8015fb2: e004 b.n 8015fbe } else { /* Just inherit the priority. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8015fb4: 4b0a ldr r3, [pc, #40] @ (8015fe0 ) 8015fb6: 681b ldr r3, [r3, #0] 8015fb8: 6ada ldr r2, [r3, #44] @ 0x2c 8015fba: 68bb ldr r3, [r7, #8] 8015fbc: 62da str r2, [r3, #44] @ 0x2c } traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); /* Inheritance occurred. */ xReturn = pdTRUE; 8015fbe: 2301 movs r3, #1 8015fc0: 60fb str r3, [r7, #12] 8015fc2: e008 b.n 8015fd6 } else { if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) 8015fc4: 68bb ldr r3, [r7, #8] 8015fc6: 6cda ldr r2, [r3, #76] @ 0x4c 8015fc8: 4b05 ldr r3, [pc, #20] @ (8015fe0 ) 8015fca: 681b ldr r3, [r3, #0] 8015fcc: 6adb ldr r3, [r3, #44] @ 0x2c 8015fce: 429a cmp r2, r3 8015fd0: d201 bcs.n 8015fd6 current priority of the mutex holder is not lower than the priority of the task attempting to take the mutex. Therefore the mutex holder must have already inherited a priority, but inheritance would have occurred if that had not been the case. */ xReturn = pdTRUE; 8015fd2: 2301 movs r3, #1 8015fd4: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8015fd6: 68fb ldr r3, [r7, #12] } 8015fd8: 4618 mov r0, r3 8015fda: 3710 adds r7, #16 8015fdc: 46bd mov sp, r7 8015fde: bd80 pop {r7, pc} 8015fe0: 24002b54 .word 0x24002b54 8015fe4: 24002b58 .word 0x24002b58 8015fe8: 24003030 .word 0x24003030 08015fec : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { 8015fec: b580 push {r7, lr} 8015fee: b086 sub sp, #24 8015ff0: af00 add r7, sp, #0 8015ff2: 6078 str r0, [r7, #4] TCB_t * const pxTCB = pxMutexHolder; 8015ff4: 687b ldr r3, [r7, #4] 8015ff6: 613b str r3, [r7, #16] BaseType_t xReturn = pdFALSE; 8015ff8: 2300 movs r3, #0 8015ffa: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 8015ffc: 687b ldr r3, [r7, #4] 8015ffe: 2b00 cmp r3, #0 8016000: d058 beq.n 80160b4 { /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. */ configASSERT( pxTCB == pxCurrentTCB ); 8016002: 4b2f ldr r3, [pc, #188] @ (80160c0 ) 8016004: 681b ldr r3, [r3, #0] 8016006: 693a ldr r2, [r7, #16] 8016008: 429a cmp r2, r3 801600a: d00b beq.n 8016024 __asm volatile 801600c: f04f 0350 mov.w r3, #80 @ 0x50 8016010: f383 8811 msr BASEPRI, r3 8016014: f3bf 8f6f isb sy 8016018: f3bf 8f4f dsb sy 801601c: 60fb str r3, [r7, #12] } 801601e: bf00 nop 8016020: bf00 nop 8016022: e7fd b.n 8016020 configASSERT( pxTCB->uxMutexesHeld ); 8016024: 693b ldr r3, [r7, #16] 8016026: 6d1b ldr r3, [r3, #80] @ 0x50 8016028: 2b00 cmp r3, #0 801602a: d10b bne.n 8016044 __asm volatile 801602c: f04f 0350 mov.w r3, #80 @ 0x50 8016030: f383 8811 msr BASEPRI, r3 8016034: f3bf 8f6f isb sy 8016038: f3bf 8f4f dsb sy 801603c: 60bb str r3, [r7, #8] } 801603e: bf00 nop 8016040: bf00 nop 8016042: e7fd b.n 8016040 ( pxTCB->uxMutexesHeld )--; 8016044: 693b ldr r3, [r7, #16] 8016046: 6d1b ldr r3, [r3, #80] @ 0x50 8016048: 1e5a subs r2, r3, #1 801604a: 693b ldr r3, [r7, #16] 801604c: 651a str r2, [r3, #80] @ 0x50 /* Has the holder of the mutex inherited the priority of another task? */ if( pxTCB->uxPriority != pxTCB->uxBasePriority ) 801604e: 693b ldr r3, [r7, #16] 8016050: 6ada ldr r2, [r3, #44] @ 0x2c 8016052: 693b ldr r3, [r7, #16] 8016054: 6cdb ldr r3, [r3, #76] @ 0x4c 8016056: 429a cmp r2, r3 8016058: d02c beq.n 80160b4 { /* Only disinherit if no other mutexes are held. */ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) 801605a: 693b ldr r3, [r7, #16] 801605c: 6d1b ldr r3, [r3, #80] @ 0x50 801605e: 2b00 cmp r3, #0 8016060: d128 bne.n 80160b4 /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. Remove the holding task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016062: 693b ldr r3, [r7, #16] 8016064: 3304 adds r3, #4 8016066: 4618 mov r0, r3 8016068: f7fd ff1c bl 8013ea4 } /* Disinherit the priority before adding the task into the new ready list. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); pxTCB->uxPriority = pxTCB->uxBasePriority; 801606c: 693b ldr r3, [r7, #16] 801606e: 6cda ldr r2, [r3, #76] @ 0x4c 8016070: 693b ldr r3, [r7, #16] 8016072: 62da str r2, [r3, #44] @ 0x2c /* Reset the event list item value. It cannot be in use for any other purpose if this task is running, and it must be running to give back the mutex. */ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016074: 693b ldr r3, [r7, #16] 8016076: 6adb ldr r3, [r3, #44] @ 0x2c 8016078: f1c3 0238 rsb r2, r3, #56 @ 0x38 801607c: 693b ldr r3, [r7, #16] 801607e: 619a str r2, [r3, #24] prvAddTaskToReadyList( pxTCB ); 8016080: 693b ldr r3, [r7, #16] 8016082: 6ada ldr r2, [r3, #44] @ 0x2c 8016084: 4b0f ldr r3, [pc, #60] @ (80160c4 ) 8016086: 681b ldr r3, [r3, #0] 8016088: 429a cmp r2, r3 801608a: d903 bls.n 8016094 801608c: 693b ldr r3, [r7, #16] 801608e: 6adb ldr r3, [r3, #44] @ 0x2c 8016090: 4a0c ldr r2, [pc, #48] @ (80160c4 ) 8016092: 6013 str r3, [r2, #0] 8016094: 693b ldr r3, [r7, #16] 8016096: 6ada ldr r2, [r3, #44] @ 0x2c 8016098: 4613 mov r3, r2 801609a: 009b lsls r3, r3, #2 801609c: 4413 add r3, r2 801609e: 009b lsls r3, r3, #2 80160a0: 4a09 ldr r2, [pc, #36] @ (80160c8 ) 80160a2: 441a add r2, r3 80160a4: 693b ldr r3, [r7, #16] 80160a6: 3304 adds r3, #4 80160a8: 4619 mov r1, r3 80160aa: 4610 mov r0, r2 80160ac: f7fd fe9d bl 8013dea in an order different to that in which they were taken. If a context switch did not occur when the first mutex was returned, even if a task was waiting on it, then a context switch should occur when the last mutex is returned whether a task is waiting on it or not. */ xReturn = pdTRUE; 80160b0: 2301 movs r3, #1 80160b2: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 80160b4: 697b ldr r3, [r7, #20] } 80160b6: 4618 mov r0, r3 80160b8: 3718 adds r7, #24 80160ba: 46bd mov sp, r7 80160bc: bd80 pop {r7, pc} 80160be: bf00 nop 80160c0: 24002b54 .word 0x24002b54 80160c4: 24003030 .word 0x24003030 80160c8: 24002b58 .word 0x24002b58 080160cc : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) { 80160cc: b580 push {r7, lr} 80160ce: b088 sub sp, #32 80160d0: af00 add r7, sp, #0 80160d2: 6078 str r0, [r7, #4] 80160d4: 6039 str r1, [r7, #0] TCB_t * const pxTCB = pxMutexHolder; 80160d6: 687b ldr r3, [r7, #4] 80160d8: 61bb str r3, [r7, #24] UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; 80160da: 2301 movs r3, #1 80160dc: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 80160de: 687b ldr r3, [r7, #4] 80160e0: 2b00 cmp r3, #0 80160e2: d06c beq.n 80161be { /* If pxMutexHolder is not NULL then the holder must hold at least one mutex. */ configASSERT( pxTCB->uxMutexesHeld ); 80160e4: 69bb ldr r3, [r7, #24] 80160e6: 6d1b ldr r3, [r3, #80] @ 0x50 80160e8: 2b00 cmp r3, #0 80160ea: d10b bne.n 8016104 __asm volatile 80160ec: f04f 0350 mov.w r3, #80 @ 0x50 80160f0: f383 8811 msr BASEPRI, r3 80160f4: f3bf 8f6f isb sy 80160f8: f3bf 8f4f dsb sy 80160fc: 60fb str r3, [r7, #12] } 80160fe: bf00 nop 8016100: bf00 nop 8016102: e7fd b.n 8016100 /* Determine the priority to which the priority of the task that holds the mutex should be set. This will be the greater of the holding task's base priority and the priority of the highest priority task that is waiting to obtain the mutex. */ if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) 8016104: 69bb ldr r3, [r7, #24] 8016106: 6cdb ldr r3, [r3, #76] @ 0x4c 8016108: 683a ldr r2, [r7, #0] 801610a: 429a cmp r2, r3 801610c: d902 bls.n 8016114 { uxPriorityToUse = uxHighestPriorityWaitingTask; 801610e: 683b ldr r3, [r7, #0] 8016110: 61fb str r3, [r7, #28] 8016112: e002 b.n 801611a } else { uxPriorityToUse = pxTCB->uxBasePriority; 8016114: 69bb ldr r3, [r7, #24] 8016116: 6cdb ldr r3, [r3, #76] @ 0x4c 8016118: 61fb str r3, [r7, #28] } /* Does the priority need to change? */ if( pxTCB->uxPriority != uxPriorityToUse ) 801611a: 69bb ldr r3, [r7, #24] 801611c: 6adb ldr r3, [r3, #44] @ 0x2c 801611e: 69fa ldr r2, [r7, #28] 8016120: 429a cmp r2, r3 8016122: d04c beq.n 80161be { /* Only disinherit if no other mutexes are held. This is a simplification in the priority inheritance implementation. If the task that holds the mutex is also holding other mutexes then the other mutexes may have caused the priority inheritance. */ if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) 8016124: 69bb ldr r3, [r7, #24] 8016126: 6d1b ldr r3, [r3, #80] @ 0x50 8016128: 697a ldr r2, [r7, #20] 801612a: 429a cmp r2, r3 801612c: d147 bne.n 80161be { /* If a task has timed out because it already holds the mutex it was trying to obtain then it cannot of inherited its own priority. */ configASSERT( pxTCB != pxCurrentTCB ); 801612e: 4b26 ldr r3, [pc, #152] @ (80161c8 ) 8016130: 681b ldr r3, [r3, #0] 8016132: 69ba ldr r2, [r7, #24] 8016134: 429a cmp r2, r3 8016136: d10b bne.n 8016150 __asm volatile 8016138: f04f 0350 mov.w r3, #80 @ 0x50 801613c: f383 8811 msr BASEPRI, r3 8016140: f3bf 8f6f isb sy 8016144: f3bf 8f4f dsb sy 8016148: 60bb str r3, [r7, #8] } 801614a: bf00 nop 801614c: bf00 nop 801614e: e7fd b.n 801614c /* Disinherit the priority, remembering the previous priority to facilitate determining the subject task's state. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); uxPriorityUsedOnEntry = pxTCB->uxPriority; 8016150: 69bb ldr r3, [r7, #24] 8016152: 6adb ldr r3, [r3, #44] @ 0x2c 8016154: 613b str r3, [r7, #16] pxTCB->uxPriority = uxPriorityToUse; 8016156: 69bb ldr r3, [r7, #24] 8016158: 69fa ldr r2, [r7, #28] 801615a: 62da str r2, [r3, #44] @ 0x2c /* Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 801615c: 69bb ldr r3, [r7, #24] 801615e: 699b ldr r3, [r3, #24] 8016160: 2b00 cmp r3, #0 8016162: db04 blt.n 801616e { listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016164: 69fb ldr r3, [r7, #28] 8016166: f1c3 0238 rsb r2, r3, #56 @ 0x38 801616a: 69bb ldr r3, [r7, #24] 801616c: 619a str r2, [r3, #24] then the task that holds the mutex could be in either the Ready, Blocked or Suspended states. Only remove the task from its current state list if it is in the Ready state as the task's priority is going to change and there is one Ready list per priority. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) 801616e: 69bb ldr r3, [r7, #24] 8016170: 6959 ldr r1, [r3, #20] 8016172: 693a ldr r2, [r7, #16] 8016174: 4613 mov r3, r2 8016176: 009b lsls r3, r3, #2 8016178: 4413 add r3, r2 801617a: 009b lsls r3, r3, #2 801617c: 4a13 ldr r2, [pc, #76] @ (80161cc ) 801617e: 4413 add r3, r2 8016180: 4299 cmp r1, r3 8016182: d11c bne.n 80161be { if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016184: 69bb ldr r3, [r7, #24] 8016186: 3304 adds r3, #4 8016188: 4618 mov r0, r3 801618a: f7fd fe8b bl 8013ea4 else { mtCOVERAGE_TEST_MARKER(); } prvAddTaskToReadyList( pxTCB ); 801618e: 69bb ldr r3, [r7, #24] 8016190: 6ada ldr r2, [r3, #44] @ 0x2c 8016192: 4b0f ldr r3, [pc, #60] @ (80161d0 ) 8016194: 681b ldr r3, [r3, #0] 8016196: 429a cmp r2, r3 8016198: d903 bls.n 80161a2 801619a: 69bb ldr r3, [r7, #24] 801619c: 6adb ldr r3, [r3, #44] @ 0x2c 801619e: 4a0c ldr r2, [pc, #48] @ (80161d0 ) 80161a0: 6013 str r3, [r2, #0] 80161a2: 69bb ldr r3, [r7, #24] 80161a4: 6ada ldr r2, [r3, #44] @ 0x2c 80161a6: 4613 mov r3, r2 80161a8: 009b lsls r3, r3, #2 80161aa: 4413 add r3, r2 80161ac: 009b lsls r3, r3, #2 80161ae: 4a07 ldr r2, [pc, #28] @ (80161cc ) 80161b0: 441a add r2, r3 80161b2: 69bb ldr r3, [r7, #24] 80161b4: 3304 adds r3, #4 80161b6: 4619 mov r1, r3 80161b8: 4610 mov r0, r2 80161ba: f7fd fe16 bl 8013dea } else { mtCOVERAGE_TEST_MARKER(); } } 80161be: bf00 nop 80161c0: 3720 adds r7, #32 80161c2: 46bd mov sp, r7 80161c4: bd80 pop {r7, pc} 80161c6: bf00 nop 80161c8: 24002b54 .word 0x24002b54 80161cc: 24002b58 .word 0x24002b58 80161d0: 24003030 .word 0x24003030 080161d4 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) TaskHandle_t pvTaskIncrementMutexHeldCount( void ) { 80161d4: b480 push {r7} 80161d6: af00 add r7, sp, #0 /* If xSemaphoreCreateMutex() is called before any tasks have been created then pxCurrentTCB will be NULL. */ if( pxCurrentTCB != NULL ) 80161d8: 4b07 ldr r3, [pc, #28] @ (80161f8 ) 80161da: 681b ldr r3, [r3, #0] 80161dc: 2b00 cmp r3, #0 80161de: d004 beq.n 80161ea { ( pxCurrentTCB->uxMutexesHeld )++; 80161e0: 4b05 ldr r3, [pc, #20] @ (80161f8 ) 80161e2: 681b ldr r3, [r3, #0] 80161e4: 6d1a ldr r2, [r3, #80] @ 0x50 80161e6: 3201 adds r2, #1 80161e8: 651a str r2, [r3, #80] @ 0x50 } return pxCurrentTCB; 80161ea: 4b03 ldr r3, [pc, #12] @ (80161f8 ) 80161ec: 681b ldr r3, [r3, #0] } 80161ee: 4618 mov r0, r3 80161f0: 46bd mov sp, r7 80161f2: f85d 7b04 ldr.w r7, [sp], #4 80161f6: 4770 bx lr 80161f8: 24002b54 .word 0x24002b54 080161fc : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) { 80161fc: b580 push {r7, lr} 80161fe: b086 sub sp, #24 8016200: af00 add r7, sp, #0 8016202: 60f8 str r0, [r7, #12] 8016204: 60b9 str r1, [r7, #8] 8016206: 607a str r2, [r7, #4] 8016208: 603b str r3, [r7, #0] BaseType_t xReturn; taskENTER_CRITICAL(); 801620a: f000 ffed bl 80171e8 { /* Only block if a notification is not already pending. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 801620e: 4b29 ldr r3, [pc, #164] @ (80162b4 ) 8016210: 681b ldr r3, [r3, #0] 8016212: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016216: b2db uxtb r3, r3 8016218: 2b02 cmp r3, #2 801621a: d01c beq.n 8016256 { /* Clear bits in the task's notification value as bits may get set by the notifying task or interrupt. This can be used to clear the value to zero. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry; 801621c: 4b25 ldr r3, [pc, #148] @ (80162b4 ) 801621e: 681b ldr r3, [r3, #0] 8016220: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 8016224: 68fa ldr r2, [r7, #12] 8016226: 43d2 mvns r2, r2 8016228: 400a ands r2, r1 801622a: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 /* Mark this task as waiting for a notification. */ pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION; 801622e: 4b21 ldr r3, [pc, #132] @ (80162b4 ) 8016230: 681b ldr r3, [r3, #0] 8016232: 2201 movs r2, #1 8016234: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 if( xTicksToWait > ( TickType_t ) 0 ) 8016238: 683b ldr r3, [r7, #0] 801623a: 2b00 cmp r3, #0 801623c: d00b beq.n 8016256 { prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 801623e: 2101 movs r1, #1 8016240: 6838 ldr r0, [r7, #0] 8016242: f000 fa09 bl 8016658 /* All ports are written to allow a yield in a critical section (some will yield immediately, others wait until the critical section exits) - but it is not something that application code should ever do. */ portYIELD_WITHIN_API(); 8016246: 4b1c ldr r3, [pc, #112] @ (80162b8 ) 8016248: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801624c: 601a str r2, [r3, #0] 801624e: f3bf 8f4f dsb sy 8016252: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016256: f000 fff9 bl 801724c taskENTER_CRITICAL(); 801625a: f000 ffc5 bl 80171e8 { traceTASK_NOTIFY_WAIT(); if( pulNotificationValue != NULL ) 801625e: 687b ldr r3, [r7, #4] 8016260: 2b00 cmp r3, #0 8016262: d005 beq.n 8016270 { /* Output the current notification value, which may or may not have changed. */ *pulNotificationValue = pxCurrentTCB->ulNotifiedValue; 8016264: 4b13 ldr r3, [pc, #76] @ (80162b4 ) 8016266: 681b ldr r3, [r3, #0] 8016268: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 801626c: 687b ldr r3, [r7, #4] 801626e: 601a str r2, [r3, #0] /* If ucNotifyValue is set then either the task never entered the blocked state (because a notification was already pending) or the task unblocked because of a notification. Otherwise the task unblocked because of a timeout. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 8016270: 4b10 ldr r3, [pc, #64] @ (80162b4 ) 8016272: 681b ldr r3, [r3, #0] 8016274: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016278: b2db uxtb r3, r3 801627a: 2b02 cmp r3, #2 801627c: d002 beq.n 8016284 { /* A notification was not received. */ xReturn = pdFALSE; 801627e: 2300 movs r3, #0 8016280: 617b str r3, [r7, #20] 8016282: e00a b.n 801629a } else { /* A notification was already pending or a notification was received while the task was waiting. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit; 8016284: 4b0b ldr r3, [pc, #44] @ (80162b4 ) 8016286: 681b ldr r3, [r3, #0] 8016288: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 801628c: 68ba ldr r2, [r7, #8] 801628e: 43d2 mvns r2, r2 8016290: 400a ands r2, r1 8016292: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 xReturn = pdTRUE; 8016296: 2301 movs r3, #1 8016298: 617b str r3, [r7, #20] } pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 801629a: 4b06 ldr r3, [pc, #24] @ (80162b4 ) 801629c: 681b ldr r3, [r3, #0] 801629e: 2200 movs r2, #0 80162a0: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 } taskEXIT_CRITICAL(); 80162a4: f000 ffd2 bl 801724c return xReturn; 80162a8: 697b ldr r3, [r7, #20] } 80162aa: 4618 mov r0, r3 80162ac: 3718 adds r7, #24 80162ae: 46bd mov sp, r7 80162b0: bd80 pop {r7, pc} 80162b2: bf00 nop 80162b4: 24002b54 .word 0x24002b54 80162b8: e000ed04 .word 0xe000ed04 080162bc : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) { 80162bc: b580 push {r7, lr} 80162be: b08a sub sp, #40 @ 0x28 80162c0: af00 add r7, sp, #0 80162c2: 60f8 str r0, [r7, #12] 80162c4: 60b9 str r1, [r7, #8] 80162c6: 603b str r3, [r7, #0] 80162c8: 4613 mov r3, r2 80162ca: 71fb strb r3, [r7, #7] TCB_t * pxTCB; BaseType_t xReturn = pdPASS; 80162cc: 2301 movs r3, #1 80162ce: 627b str r3, [r7, #36] @ 0x24 uint8_t ucOriginalNotifyState; configASSERT( xTaskToNotify ); 80162d0: 68fb ldr r3, [r7, #12] 80162d2: 2b00 cmp r3, #0 80162d4: d10b bne.n 80162ee __asm volatile 80162d6: f04f 0350 mov.w r3, #80 @ 0x50 80162da: f383 8811 msr BASEPRI, r3 80162de: f3bf 8f6f isb sy 80162e2: f3bf 8f4f dsb sy 80162e6: 61bb str r3, [r7, #24] } 80162e8: bf00 nop 80162ea: bf00 nop 80162ec: e7fd b.n 80162ea pxTCB = xTaskToNotify; 80162ee: 68fb ldr r3, [r7, #12] 80162f0: 623b str r3, [r7, #32] taskENTER_CRITICAL(); 80162f2: f000 ff79 bl 80171e8 { if( pulPreviousNotificationValue != NULL ) 80162f6: 683b ldr r3, [r7, #0] 80162f8: 2b00 cmp r3, #0 80162fa: d004 beq.n 8016306 { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 80162fc: 6a3b ldr r3, [r7, #32] 80162fe: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016302: 683b ldr r3, [r7, #0] 8016304: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 8016306: 6a3b ldr r3, [r7, #32] 8016308: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 801630c: 77fb strb r3, [r7, #31] pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 801630e: 6a3b ldr r3, [r7, #32] 8016310: 2202 movs r2, #2 8016312: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 8016316: 79fb ldrb r3, [r7, #7] 8016318: 2b04 cmp r3, #4 801631a: d82e bhi.n 801637a 801631c: a201 add r2, pc, #4 @ (adr r2, 8016324 ) 801631e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016322: bf00 nop 8016324: 0801639f .word 0x0801639f 8016328: 08016339 .word 0x08016339 801632c: 0801634b .word 0x0801634b 8016330: 0801635b .word 0x0801635b 8016334: 08016365 .word 0x08016365 { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 8016338: 6a3b ldr r3, [r7, #32] 801633a: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 801633e: 68bb ldr r3, [r7, #8] 8016340: 431a orrs r2, r3 8016342: 6a3b ldr r3, [r7, #32] 8016344: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016348: e02c b.n 80163a4 case eIncrement : ( pxTCB->ulNotifiedValue )++; 801634a: 6a3b ldr r3, [r7, #32] 801634c: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016350: 1c5a adds r2, r3, #1 8016352: 6a3b ldr r3, [r7, #32] 8016354: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016358: e024 b.n 80163a4 case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 801635a: 6a3b ldr r3, [r7, #32] 801635c: 68ba ldr r2, [r7, #8] 801635e: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016362: e01f b.n 80163a4 case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 8016364: 7ffb ldrb r3, [r7, #31] 8016366: 2b02 cmp r3, #2 8016368: d004 beq.n 8016374 { pxTCB->ulNotifiedValue = ulValue; 801636a: 6a3b ldr r3, [r7, #32] 801636c: 68ba ldr r2, [r7, #8] 801636e: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 8016372: e017 b.n 80163a4 xReturn = pdFAIL; 8016374: 2300 movs r3, #0 8016376: 627b str r3, [r7, #36] @ 0x24 break; 8016378: e014 b.n 80163a4 default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 801637a: 6a3b ldr r3, [r7, #32] 801637c: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016380: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8016384: d00d beq.n 80163a2 __asm volatile 8016386: f04f 0350 mov.w r3, #80 @ 0x50 801638a: f383 8811 msr BASEPRI, r3 801638e: f3bf 8f6f isb sy 8016392: f3bf 8f4f dsb sy 8016396: 617b str r3, [r7, #20] } 8016398: bf00 nop 801639a: bf00 nop 801639c: e7fd b.n 801639a break; 801639e: bf00 nop 80163a0: e000 b.n 80163a4 break; 80163a2: bf00 nop traceTASK_NOTIFY(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 80163a4: 7ffb ldrb r3, [r7, #31] 80163a6: 2b01 cmp r3, #1 80163a8: d13b bne.n 8016422 { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80163aa: 6a3b ldr r3, [r7, #32] 80163ac: 3304 adds r3, #4 80163ae: 4618 mov r0, r3 80163b0: f7fd fd78 bl 8013ea4 prvAddTaskToReadyList( pxTCB ); 80163b4: 6a3b ldr r3, [r7, #32] 80163b6: 6ada ldr r2, [r3, #44] @ 0x2c 80163b8: 4b1d ldr r3, [pc, #116] @ (8016430 ) 80163ba: 681b ldr r3, [r3, #0] 80163bc: 429a cmp r2, r3 80163be: d903 bls.n 80163c8 80163c0: 6a3b ldr r3, [r7, #32] 80163c2: 6adb ldr r3, [r3, #44] @ 0x2c 80163c4: 4a1a ldr r2, [pc, #104] @ (8016430 ) 80163c6: 6013 str r3, [r2, #0] 80163c8: 6a3b ldr r3, [r7, #32] 80163ca: 6ada ldr r2, [r3, #44] @ 0x2c 80163cc: 4613 mov r3, r2 80163ce: 009b lsls r3, r3, #2 80163d0: 4413 add r3, r2 80163d2: 009b lsls r3, r3, #2 80163d4: 4a17 ldr r2, [pc, #92] @ (8016434 ) 80163d6: 441a add r2, r3 80163d8: 6a3b ldr r3, [r7, #32] 80163da: 3304 adds r3, #4 80163dc: 4619 mov r1, r3 80163de: 4610 mov r0, r2 80163e0: f7fd fd03 bl 8013dea /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 80163e4: 6a3b ldr r3, [r7, #32] 80163e6: 6a9b ldr r3, [r3, #40] @ 0x28 80163e8: 2b00 cmp r3, #0 80163ea: d00b beq.n 8016404 __asm volatile 80163ec: f04f 0350 mov.w r3, #80 @ 0x50 80163f0: f383 8811 msr BASEPRI, r3 80163f4: f3bf 8f6f isb sy 80163f8: f3bf 8f4f dsb sy 80163fc: 613b str r3, [r7, #16] } 80163fe: bf00 nop 8016400: bf00 nop 8016402: e7fd b.n 8016400 earliest possible time. */ prvResetNextTaskUnblockTime(); } #endif if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 8016404: 6a3b ldr r3, [r7, #32] 8016406: 6ada ldr r2, [r3, #44] @ 0x2c 8016408: 4b0b ldr r3, [pc, #44] @ (8016438 ) 801640a: 681b ldr r3, [r3, #0] 801640c: 6adb ldr r3, [r3, #44] @ 0x2c 801640e: 429a cmp r2, r3 8016410: d907 bls.n 8016422 { /* The notified task has a priority above the currently executing task so a yield is required. */ taskYIELD_IF_USING_PREEMPTION(); 8016412: 4b0a ldr r3, [pc, #40] @ (801643c ) 8016414: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016418: 601a str r2, [r3, #0] 801641a: f3bf 8f4f dsb sy 801641e: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016422: f000 ff13 bl 801724c return xReturn; 8016426: 6a7b ldr r3, [r7, #36] @ 0x24 } 8016428: 4618 mov r0, r3 801642a: 3728 adds r7, #40 @ 0x28 801642c: 46bd mov sp, r7 801642e: bd80 pop {r7, pc} 8016430: 24003030 .word 0x24003030 8016434: 24002b58 .word 0x24002b58 8016438: 24002b54 .word 0x24002b54 801643c: e000ed04 .word 0xe000ed04 08016440 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) { 8016440: b580 push {r7, lr} 8016442: b08e sub sp, #56 @ 0x38 8016444: af00 add r7, sp, #0 8016446: 60f8 str r0, [r7, #12] 8016448: 60b9 str r1, [r7, #8] 801644a: 603b str r3, [r7, #0] 801644c: 4613 mov r3, r2 801644e: 71fb strb r3, [r7, #7] TCB_t * pxTCB; uint8_t ucOriginalNotifyState; BaseType_t xReturn = pdPASS; 8016450: 2301 movs r3, #1 8016452: 637b str r3, [r7, #52] @ 0x34 UBaseType_t uxSavedInterruptStatus; configASSERT( xTaskToNotify ); 8016454: 68fb ldr r3, [r7, #12] 8016456: 2b00 cmp r3, #0 8016458: d10b bne.n 8016472 __asm volatile 801645a: f04f 0350 mov.w r3, #80 @ 0x50 801645e: f383 8811 msr BASEPRI, r3 8016462: f3bf 8f6f isb sy 8016466: f3bf 8f4f dsb sy 801646a: 627b str r3, [r7, #36] @ 0x24 } 801646c: bf00 nop 801646e: bf00 nop 8016470: e7fd b.n 801646e below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8016472: f000 ff99 bl 80173a8 pxTCB = xTaskToNotify; 8016476: 68fb ldr r3, [r7, #12] 8016478: 633b str r3, [r7, #48] @ 0x30 __asm volatile 801647a: f3ef 8211 mrs r2, BASEPRI 801647e: f04f 0350 mov.w r3, #80 @ 0x50 8016482: f383 8811 msr BASEPRI, r3 8016486: f3bf 8f6f isb sy 801648a: f3bf 8f4f dsb sy 801648e: 623a str r2, [r7, #32] 8016490: 61fb str r3, [r7, #28] return ulOriginalBASEPRI; 8016492: 6a3b ldr r3, [r7, #32] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8016494: 62fb str r3, [r7, #44] @ 0x2c { if( pulPreviousNotificationValue != NULL ) 8016496: 683b ldr r3, [r7, #0] 8016498: 2b00 cmp r3, #0 801649a: d004 beq.n 80164a6 { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 801649c: 6b3b ldr r3, [r7, #48] @ 0x30 801649e: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 80164a2: 683b ldr r3, [r7, #0] 80164a4: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 80164a6: 6b3b ldr r3, [r7, #48] @ 0x30 80164a8: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 80164ac: f887 302b strb.w r3, [r7, #43] @ 0x2b pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 80164b0: 6b3b ldr r3, [r7, #48] @ 0x30 80164b2: 2202 movs r2, #2 80164b4: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 80164b8: 79fb ldrb r3, [r7, #7] 80164ba: 2b04 cmp r3, #4 80164bc: d82e bhi.n 801651c 80164be: a201 add r2, pc, #4 @ (adr r2, 80164c4 ) 80164c0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80164c4: 08016541 .word 0x08016541 80164c8: 080164d9 .word 0x080164d9 80164cc: 080164eb .word 0x080164eb 80164d0: 080164fb .word 0x080164fb 80164d4: 08016505 .word 0x08016505 { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 80164d8: 6b3b ldr r3, [r7, #48] @ 0x30 80164da: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 80164de: 68bb ldr r3, [r7, #8] 80164e0: 431a orrs r2, r3 80164e2: 6b3b ldr r3, [r7, #48] @ 0x30 80164e4: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 80164e8: e02d b.n 8016546 case eIncrement : ( pxTCB->ulNotifiedValue )++; 80164ea: 6b3b ldr r3, [r7, #48] @ 0x30 80164ec: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 80164f0: 1c5a adds r2, r3, #1 80164f2: 6b3b ldr r3, [r7, #48] @ 0x30 80164f4: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 80164f8: e025 b.n 8016546 case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 80164fa: 6b3b ldr r3, [r7, #48] @ 0x30 80164fc: 68ba ldr r2, [r7, #8] 80164fe: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016502: e020 b.n 8016546 case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 8016504: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8016508: 2b02 cmp r3, #2 801650a: d004 beq.n 8016516 { pxTCB->ulNotifiedValue = ulValue; 801650c: 6b3b ldr r3, [r7, #48] @ 0x30 801650e: 68ba ldr r2, [r7, #8] 8016510: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 8016514: e017 b.n 8016546 xReturn = pdFAIL; 8016516: 2300 movs r3, #0 8016518: 637b str r3, [r7, #52] @ 0x34 break; 801651a: e014 b.n 8016546 default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 801651c: 6b3b ldr r3, [r7, #48] @ 0x30 801651e: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016522: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8016526: d00d beq.n 8016544 __asm volatile 8016528: f04f 0350 mov.w r3, #80 @ 0x50 801652c: f383 8811 msr BASEPRI, r3 8016530: f3bf 8f6f isb sy 8016534: f3bf 8f4f dsb sy 8016538: 61bb str r3, [r7, #24] } 801653a: bf00 nop 801653c: bf00 nop 801653e: e7fd b.n 801653c break; 8016540: bf00 nop 8016542: e000 b.n 8016546 break; 8016544: bf00 nop traceTASK_NOTIFY_FROM_ISR(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 8016546: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 801654a: 2b01 cmp r3, #1 801654c: d147 bne.n 80165de { /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 801654e: 6b3b ldr r3, [r7, #48] @ 0x30 8016550: 6a9b ldr r3, [r3, #40] @ 0x28 8016552: 2b00 cmp r3, #0 8016554: d00b beq.n 801656e __asm volatile 8016556: f04f 0350 mov.w r3, #80 @ 0x50 801655a: f383 8811 msr BASEPRI, r3 801655e: f3bf 8f6f isb sy 8016562: f3bf 8f4f dsb sy 8016566: 617b str r3, [r7, #20] } 8016568: bf00 nop 801656a: bf00 nop 801656c: e7fd b.n 801656a if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 801656e: 4b21 ldr r3, [pc, #132] @ (80165f4 ) 8016570: 681b ldr r3, [r3, #0] 8016572: 2b00 cmp r3, #0 8016574: d11d bne.n 80165b2 { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8016576: 6b3b ldr r3, [r7, #48] @ 0x30 8016578: 3304 adds r3, #4 801657a: 4618 mov r0, r3 801657c: f7fd fc92 bl 8013ea4 prvAddTaskToReadyList( pxTCB ); 8016580: 6b3b ldr r3, [r7, #48] @ 0x30 8016582: 6ada ldr r2, [r3, #44] @ 0x2c 8016584: 4b1c ldr r3, [pc, #112] @ (80165f8 ) 8016586: 681b ldr r3, [r3, #0] 8016588: 429a cmp r2, r3 801658a: d903 bls.n 8016594 801658c: 6b3b ldr r3, [r7, #48] @ 0x30 801658e: 6adb ldr r3, [r3, #44] @ 0x2c 8016590: 4a19 ldr r2, [pc, #100] @ (80165f8 ) 8016592: 6013 str r3, [r2, #0] 8016594: 6b3b ldr r3, [r7, #48] @ 0x30 8016596: 6ada ldr r2, [r3, #44] @ 0x2c 8016598: 4613 mov r3, r2 801659a: 009b lsls r3, r3, #2 801659c: 4413 add r3, r2 801659e: 009b lsls r3, r3, #2 80165a0: 4a16 ldr r2, [pc, #88] @ (80165fc ) 80165a2: 441a add r2, r3 80165a4: 6b3b ldr r3, [r7, #48] @ 0x30 80165a6: 3304 adds r3, #4 80165a8: 4619 mov r1, r3 80165aa: 4610 mov r0, r2 80165ac: f7fd fc1d bl 8013dea 80165b0: e005 b.n 80165be } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); 80165b2: 6b3b ldr r3, [r7, #48] @ 0x30 80165b4: 3318 adds r3, #24 80165b6: 4619 mov r1, r3 80165b8: 4811 ldr r0, [pc, #68] @ (8016600 ) 80165ba: f7fd fc16 bl 8013dea } if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 80165be: 6b3b ldr r3, [r7, #48] @ 0x30 80165c0: 6ada ldr r2, [r3, #44] @ 0x2c 80165c2: 4b10 ldr r3, [pc, #64] @ (8016604 ) 80165c4: 681b ldr r3, [r3, #0] 80165c6: 6adb ldr r3, [r3, #44] @ 0x2c 80165c8: 429a cmp r2, r3 80165ca: d908 bls.n 80165de { /* The notified task has a priority above the currently executing task so a yield is required. */ if( pxHigherPriorityTaskWoken != NULL ) 80165cc: 6c3b ldr r3, [r7, #64] @ 0x40 80165ce: 2b00 cmp r3, #0 80165d0: d002 beq.n 80165d8 { *pxHigherPriorityTaskWoken = pdTRUE; 80165d2: 6c3b ldr r3, [r7, #64] @ 0x40 80165d4: 2201 movs r2, #1 80165d6: 601a str r2, [r3, #0] } /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 80165d8: 4b0b ldr r3, [pc, #44] @ (8016608 ) 80165da: 2201 movs r2, #1 80165dc: 601a str r2, [r3, #0] 80165de: 6afb ldr r3, [r7, #44] @ 0x2c 80165e0: 613b str r3, [r7, #16] __asm volatile 80165e2: 693b ldr r3, [r7, #16] 80165e4: f383 8811 msr BASEPRI, r3 } 80165e8: bf00 nop } } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 80165ea: 6b7b ldr r3, [r7, #52] @ 0x34 } 80165ec: 4618 mov r0, r3 80165ee: 3738 adds r7, #56 @ 0x38 80165f0: 46bd mov sp, r7 80165f2: bd80 pop {r7, pc} 80165f4: 24003050 .word 0x24003050 80165f8: 24003030 .word 0x24003030 80165fc: 24002b58 .word 0x24002b58 8016600: 24002fe8 .word 0x24002fe8 8016604: 24002b54 .word 0x24002b54 8016608: 2400303c .word 0x2400303c 0801660c : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask ) { 801660c: b580 push {r7, lr} 801660e: b084 sub sp, #16 8016610: af00 add r7, sp, #0 8016612: 6078 str r0, [r7, #4] TCB_t *pxTCB; BaseType_t xReturn; /* If null is passed in here then it is the calling task that is having its notification state cleared. */ pxTCB = prvGetTCBFromHandle( xTask ); 8016614: 687b ldr r3, [r7, #4] 8016616: 2b00 cmp r3, #0 8016618: d102 bne.n 8016620 801661a: 4b0e ldr r3, [pc, #56] @ (8016654 ) 801661c: 681b ldr r3, [r3, #0] 801661e: e000 b.n 8016622 8016620: 687b ldr r3, [r7, #4] 8016622: 60bb str r3, [r7, #8] taskENTER_CRITICAL(); 8016624: f000 fde0 bl 80171e8 { if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED ) 8016628: 68bb ldr r3, [r7, #8] 801662a: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 801662e: b2db uxtb r3, r3 8016630: 2b02 cmp r3, #2 8016632: d106 bne.n 8016642 { pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8016634: 68bb ldr r3, [r7, #8] 8016636: 2200 movs r2, #0 8016638: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 xReturn = pdPASS; 801663c: 2301 movs r3, #1 801663e: 60fb str r3, [r7, #12] 8016640: e001 b.n 8016646 } else { xReturn = pdFAIL; 8016642: 2300 movs r3, #0 8016644: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8016646: f000 fe01 bl 801724c return xReturn; 801664a: 68fb ldr r3, [r7, #12] } 801664c: 4618 mov r0, r3 801664e: 3710 adds r7, #16 8016650: 46bd mov sp, r7 8016652: bd80 pop {r7, pc} 8016654: 24002b54 .word 0x24002b54 08016658 : #endif /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { 8016658: b580 push {r7, lr} 801665a: b084 sub sp, #16 801665c: af00 add r7, sp, #0 801665e: 6078 str r0, [r7, #4] 8016660: 6039 str r1, [r7, #0] TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; 8016662: 4b21 ldr r3, [pc, #132] @ (80166e8 ) 8016664: 681b ldr r3, [r3, #0] 8016666: 60fb str r3, [r7, #12] } #endif /* Remove the task from the ready list before adding it to the blocked list as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016668: 4b20 ldr r3, [pc, #128] @ (80166ec ) 801666a: 681b ldr r3, [r3, #0] 801666c: 3304 adds r3, #4 801666e: 4618 mov r0, r3 8016670: f7fd fc18 bl 8013ea4 mtCOVERAGE_TEST_MARKER(); } #if ( INCLUDE_vTaskSuspend == 1 ) { if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) 8016674: 687b ldr r3, [r7, #4] 8016676: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801667a: d10a bne.n 8016692 801667c: 683b ldr r3, [r7, #0] 801667e: 2b00 cmp r3, #0 8016680: d007 beq.n 8016692 { /* Add the task to the suspended task list instead of a delayed task list to ensure it is not woken by a timing event. It will block indefinitely. */ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8016682: 4b1a ldr r3, [pc, #104] @ (80166ec ) 8016684: 681b ldr r3, [r3, #0] 8016686: 3304 adds r3, #4 8016688: 4619 mov r1, r3 801668a: 4819 ldr r0, [pc, #100] @ (80166f0 ) 801668c: f7fd fbad bl 8013dea /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } 8016690: e026 b.n 80166e0 xTimeToWake = xConstTickCount + xTicksToWait; 8016692: 68fa ldr r2, [r7, #12] 8016694: 687b ldr r3, [r7, #4] 8016696: 4413 add r3, r2 8016698: 60bb str r3, [r7, #8] listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 801669a: 4b14 ldr r3, [pc, #80] @ (80166ec ) 801669c: 681b ldr r3, [r3, #0] 801669e: 68ba ldr r2, [r7, #8] 80166a0: 605a str r2, [r3, #4] if( xTimeToWake < xConstTickCount ) 80166a2: 68ba ldr r2, [r7, #8] 80166a4: 68fb ldr r3, [r7, #12] 80166a6: 429a cmp r2, r3 80166a8: d209 bcs.n 80166be vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 80166aa: 4b12 ldr r3, [pc, #72] @ (80166f4 ) 80166ac: 681a ldr r2, [r3, #0] 80166ae: 4b0f ldr r3, [pc, #60] @ (80166ec ) 80166b0: 681b ldr r3, [r3, #0] 80166b2: 3304 adds r3, #4 80166b4: 4619 mov r1, r3 80166b6: 4610 mov r0, r2 80166b8: f7fd fbbb bl 8013e32 } 80166bc: e010 b.n 80166e0 vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 80166be: 4b0e ldr r3, [pc, #56] @ (80166f8 ) 80166c0: 681a ldr r2, [r3, #0] 80166c2: 4b0a ldr r3, [pc, #40] @ (80166ec ) 80166c4: 681b ldr r3, [r3, #0] 80166c6: 3304 adds r3, #4 80166c8: 4619 mov r1, r3 80166ca: 4610 mov r0, r2 80166cc: f7fd fbb1 bl 8013e32 if( xTimeToWake < xNextTaskUnblockTime ) 80166d0: 4b0a ldr r3, [pc, #40] @ (80166fc ) 80166d2: 681b ldr r3, [r3, #0] 80166d4: 68ba ldr r2, [r7, #8] 80166d6: 429a cmp r2, r3 80166d8: d202 bcs.n 80166e0 xNextTaskUnblockTime = xTimeToWake; 80166da: 4a08 ldr r2, [pc, #32] @ (80166fc ) 80166dc: 68bb ldr r3, [r7, #8] 80166de: 6013 str r3, [r2, #0] } 80166e0: bf00 nop 80166e2: 3710 adds r7, #16 80166e4: 46bd mov sp, r7 80166e6: bd80 pop {r7, pc} 80166e8: 2400302c .word 0x2400302c 80166ec: 24002b54 .word 0x24002b54 80166f0: 24003014 .word 0x24003014 80166f4: 24002fe4 .word 0x24002fe4 80166f8: 24002fe0 .word 0x24002fe0 80166fc: 24003048 .word 0x24003048 08016700 : TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ BaseType_t xTimerCreateTimerTask( void ) { 8016700: b580 push {r7, lr} 8016702: b08a sub sp, #40 @ 0x28 8016704: af04 add r7, sp, #16 BaseType_t xReturn = pdFAIL; 8016706: 2300 movs r3, #0 8016708: 617b str r3, [r7, #20] /* This function is called when the scheduler is started if configUSE_TIMERS is set to 1. Check that the infrastructure used by the timer service task has been created/initialised. If timers have already been created then the initialisation will already have been performed. */ prvCheckForValidListAndQueue(); 801670a: f000 fbb1 bl 8016e70 if( xTimerQueue != NULL ) 801670e: 4b1d ldr r3, [pc, #116] @ (8016784 ) 8016710: 681b ldr r3, [r3, #0] 8016712: 2b00 cmp r3, #0 8016714: d021 beq.n 801675a { #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxTimerTaskTCBBuffer = NULL; 8016716: 2300 movs r3, #0 8016718: 60fb str r3, [r7, #12] StackType_t *pxTimerTaskStackBuffer = NULL; 801671a: 2300 movs r3, #0 801671c: 60bb str r3, [r7, #8] uint32_t ulTimerTaskStackSize; vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); 801671e: 1d3a adds r2, r7, #4 8016720: f107 0108 add.w r1, r7, #8 8016724: f107 030c add.w r3, r7, #12 8016728: 4618 mov r0, r3 801672a: f7fd fb17 bl 8013d5c xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, 801672e: 6879 ldr r1, [r7, #4] 8016730: 68bb ldr r3, [r7, #8] 8016732: 68fa ldr r2, [r7, #12] 8016734: 9202 str r2, [sp, #8] 8016736: 9301 str r3, [sp, #4] 8016738: 2302 movs r3, #2 801673a: 9300 str r3, [sp, #0] 801673c: 2300 movs r3, #0 801673e: 460a mov r2, r1 8016740: 4911 ldr r1, [pc, #68] @ (8016788 ) 8016742: 4812 ldr r0, [pc, #72] @ (801678c ) 8016744: f7fe fd2f bl 80151a6 8016748: 4603 mov r3, r0 801674a: 4a11 ldr r2, [pc, #68] @ (8016790 ) 801674c: 6013 str r3, [r2, #0] NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, pxTimerTaskStackBuffer, pxTimerTaskTCBBuffer ); if( xTimerTaskHandle != NULL ) 801674e: 4b10 ldr r3, [pc, #64] @ (8016790 ) 8016750: 681b ldr r3, [r3, #0] 8016752: 2b00 cmp r3, #0 8016754: d001 beq.n 801675a { xReturn = pdPASS; 8016756: 2301 movs r3, #1 8016758: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } configASSERT( xReturn ); 801675a: 697b ldr r3, [r7, #20] 801675c: 2b00 cmp r3, #0 801675e: d10b bne.n 8016778 __asm volatile 8016760: f04f 0350 mov.w r3, #80 @ 0x50 8016764: f383 8811 msr BASEPRI, r3 8016768: f3bf 8f6f isb sy 801676c: f3bf 8f4f dsb sy 8016770: 613b str r3, [r7, #16] } 8016772: bf00 nop 8016774: bf00 nop 8016776: e7fd b.n 8016774 return xReturn; 8016778: 697b ldr r3, [r7, #20] } 801677a: 4618 mov r0, r3 801677c: 3718 adds r7, #24 801677e: 46bd mov sp, r7 8016780: bd80 pop {r7, pc} 8016782: bf00 nop 8016784: 24003084 .word 0x24003084 8016788: 0801a214 .word 0x0801a214 801678c: 08016a09 .word 0x08016a09 8016790: 24003088 .word 0x24003088 08016794 : TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) { 8016794: b580 push {r7, lr} 8016796: b088 sub sp, #32 8016798: af02 add r7, sp, #8 801679a: 60f8 str r0, [r7, #12] 801679c: 60b9 str r1, [r7, #8] 801679e: 607a str r2, [r7, #4] 80167a0: 603b str r3, [r7, #0] Timer_t *pxNewTimer; pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */ 80167a2: 202c movs r0, #44 @ 0x2c 80167a4: f000 fe42 bl 801742c 80167a8: 6178 str r0, [r7, #20] if( pxNewTimer != NULL ) 80167aa: 697b ldr r3, [r7, #20] 80167ac: 2b00 cmp r3, #0 80167ae: d00d beq.n 80167cc { /* Status is thus far zero as the timer is not created statically and has not been started. The auto-reload bit may get set in prvInitialiseNewTimer. */ pxNewTimer->ucStatus = 0x00; 80167b0: 697b ldr r3, [r7, #20] 80167b2: 2200 movs r2, #0 80167b4: f883 2028 strb.w r2, [r3, #40] @ 0x28 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); 80167b8: 697b ldr r3, [r7, #20] 80167ba: 9301 str r3, [sp, #4] 80167bc: 6a3b ldr r3, [r7, #32] 80167be: 9300 str r3, [sp, #0] 80167c0: 683b ldr r3, [r7, #0] 80167c2: 687a ldr r2, [r7, #4] 80167c4: 68b9 ldr r1, [r7, #8] 80167c6: 68f8 ldr r0, [r7, #12] 80167c8: f000 f845 bl 8016856 } return pxNewTimer; 80167cc: 697b ldr r3, [r7, #20] } 80167ce: 4618 mov r0, r3 80167d0: 3718 adds r7, #24 80167d2: 46bd mov sp, r7 80167d4: bd80 pop {r7, pc} 080167d6 : const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) { 80167d6: b580 push {r7, lr} 80167d8: b08a sub sp, #40 @ 0x28 80167da: af02 add r7, sp, #8 80167dc: 60f8 str r0, [r7, #12] 80167de: 60b9 str r1, [r7, #8] 80167e0: 607a str r2, [r7, #4] 80167e2: 603b str r3, [r7, #0] #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTimer_t equals the size of the real timer structure. */ volatile size_t xSize = sizeof( StaticTimer_t ); 80167e4: 232c movs r3, #44 @ 0x2c 80167e6: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( Timer_t ) ); 80167e8: 693b ldr r3, [r7, #16] 80167ea: 2b2c cmp r3, #44 @ 0x2c 80167ec: d00b beq.n 8016806 __asm volatile 80167ee: f04f 0350 mov.w r3, #80 @ 0x50 80167f2: f383 8811 msr BASEPRI, r3 80167f6: f3bf 8f6f isb sy 80167fa: f3bf 8f4f dsb sy 80167fe: 61bb str r3, [r7, #24] } 8016800: bf00 nop 8016802: bf00 nop 8016804: e7fd b.n 8016802 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 8016806: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ /* A pointer to a StaticTimer_t structure MUST be provided, use it. */ configASSERT( pxTimerBuffer ); 8016808: 6afb ldr r3, [r7, #44] @ 0x2c 801680a: 2b00 cmp r3, #0 801680c: d10b bne.n 8016826 __asm volatile 801680e: f04f 0350 mov.w r3, #80 @ 0x50 8016812: f383 8811 msr BASEPRI, r3 8016816: f3bf 8f6f isb sy 801681a: f3bf 8f4f dsb sy 801681e: 617b str r3, [r7, #20] } 8016820: bf00 nop 8016822: bf00 nop 8016824: e7fd b.n 8016822 pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */ 8016826: 6afb ldr r3, [r7, #44] @ 0x2c 8016828: 61fb str r3, [r7, #28] if( pxNewTimer != NULL ) 801682a: 69fb ldr r3, [r7, #28] 801682c: 2b00 cmp r3, #0 801682e: d00d beq.n 801684c { /* Timers can be created statically or dynamically so note this timer was created statically in case it is later deleted. The auto-reload bit may get set in prvInitialiseNewTimer(). */ pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED; 8016830: 69fb ldr r3, [r7, #28] 8016832: 2202 movs r2, #2 8016834: f883 2028 strb.w r2, [r3, #40] @ 0x28 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); 8016838: 69fb ldr r3, [r7, #28] 801683a: 9301 str r3, [sp, #4] 801683c: 6abb ldr r3, [r7, #40] @ 0x28 801683e: 9300 str r3, [sp, #0] 8016840: 683b ldr r3, [r7, #0] 8016842: 687a ldr r2, [r7, #4] 8016844: 68b9 ldr r1, [r7, #8] 8016846: 68f8 ldr r0, [r7, #12] 8016848: f000 f805 bl 8016856 } return pxNewTimer; 801684c: 69fb ldr r3, [r7, #28] } 801684e: 4618 mov r0, r3 8016850: 3720 adds r7, #32 8016852: 46bd mov sp, r7 8016854: bd80 pop {r7, pc} 08016856 : const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) { 8016856: b580 push {r7, lr} 8016858: b086 sub sp, #24 801685a: af00 add r7, sp, #0 801685c: 60f8 str r0, [r7, #12] 801685e: 60b9 str r1, [r7, #8] 8016860: 607a str r2, [r7, #4] 8016862: 603b str r3, [r7, #0] /* 0 is not a valid value for xTimerPeriodInTicks. */ configASSERT( ( xTimerPeriodInTicks > 0 ) ); 8016864: 68bb ldr r3, [r7, #8] 8016866: 2b00 cmp r3, #0 8016868: d10b bne.n 8016882 __asm volatile 801686a: f04f 0350 mov.w r3, #80 @ 0x50 801686e: f383 8811 msr BASEPRI, r3 8016872: f3bf 8f6f isb sy 8016876: f3bf 8f4f dsb sy 801687a: 617b str r3, [r7, #20] } 801687c: bf00 nop 801687e: bf00 nop 8016880: e7fd b.n 801687e if( pxNewTimer != NULL ) 8016882: 6a7b ldr r3, [r7, #36] @ 0x24 8016884: 2b00 cmp r3, #0 8016886: d01e beq.n 80168c6 { /* Ensure the infrastructure used by the timer service task has been created/initialised. */ prvCheckForValidListAndQueue(); 8016888: f000 faf2 bl 8016e70 /* Initialise the timer structure members using the function parameters. */ pxNewTimer->pcTimerName = pcTimerName; 801688c: 6a7b ldr r3, [r7, #36] @ 0x24 801688e: 68fa ldr r2, [r7, #12] 8016890: 601a str r2, [r3, #0] pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks; 8016892: 6a7b ldr r3, [r7, #36] @ 0x24 8016894: 68ba ldr r2, [r7, #8] 8016896: 619a str r2, [r3, #24] pxNewTimer->pvTimerID = pvTimerID; 8016898: 6a7b ldr r3, [r7, #36] @ 0x24 801689a: 683a ldr r2, [r7, #0] 801689c: 61da str r2, [r3, #28] pxNewTimer->pxCallbackFunction = pxCallbackFunction; 801689e: 6a7b ldr r3, [r7, #36] @ 0x24 80168a0: 6a3a ldr r2, [r7, #32] 80168a2: 621a str r2, [r3, #32] vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); 80168a4: 6a7b ldr r3, [r7, #36] @ 0x24 80168a6: 3304 adds r3, #4 80168a8: 4618 mov r0, r3 80168aa: f7fd fa91 bl 8013dd0 if( uxAutoReload != pdFALSE ) 80168ae: 687b ldr r3, [r7, #4] 80168b0: 2b00 cmp r3, #0 80168b2: d008 beq.n 80168c6 { pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; 80168b4: 6a7b ldr r3, [r7, #36] @ 0x24 80168b6: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80168ba: f043 0304 orr.w r3, r3, #4 80168be: b2da uxtb r2, r3 80168c0: 6a7b ldr r3, [r7, #36] @ 0x24 80168c2: f883 2028 strb.w r2, [r3, #40] @ 0x28 } traceTIMER_CREATE( pxNewTimer ); } } 80168c6: bf00 nop 80168c8: 3718 adds r7, #24 80168ca: 46bd mov sp, r7 80168cc: bd80 pop {r7, pc} ... 080168d0 : /*-----------------------------------------------------------*/ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) { 80168d0: b580 push {r7, lr} 80168d2: b08a sub sp, #40 @ 0x28 80168d4: af00 add r7, sp, #0 80168d6: 60f8 str r0, [r7, #12] 80168d8: 60b9 str r1, [r7, #8] 80168da: 607a str r2, [r7, #4] 80168dc: 603b str r3, [r7, #0] BaseType_t xReturn = pdFAIL; 80168de: 2300 movs r3, #0 80168e0: 627b str r3, [r7, #36] @ 0x24 DaemonTaskMessage_t xMessage; configASSERT( xTimer ); 80168e2: 68fb ldr r3, [r7, #12] 80168e4: 2b00 cmp r3, #0 80168e6: d10b bne.n 8016900 __asm volatile 80168e8: f04f 0350 mov.w r3, #80 @ 0x50 80168ec: f383 8811 msr BASEPRI, r3 80168f0: f3bf 8f6f isb sy 80168f4: f3bf 8f4f dsb sy 80168f8: 623b str r3, [r7, #32] } 80168fa: bf00 nop 80168fc: bf00 nop 80168fe: e7fd b.n 80168fc /* Send a message to the timer service task to perform a particular action on a particular timer definition. */ if( xTimerQueue != NULL ) 8016900: 4b19 ldr r3, [pc, #100] @ (8016968 ) 8016902: 681b ldr r3, [r3, #0] 8016904: 2b00 cmp r3, #0 8016906: d02a beq.n 801695e { /* Send a command to the timer service task to start the xTimer timer. */ xMessage.xMessageID = xCommandID; 8016908: 68bb ldr r3, [r7, #8] 801690a: 613b str r3, [r7, #16] xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; 801690c: 687b ldr r3, [r7, #4] 801690e: 617b str r3, [r7, #20] xMessage.u.xTimerParameters.pxTimer = xTimer; 8016910: 68fb ldr r3, [r7, #12] 8016912: 61bb str r3, [r7, #24] if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) 8016914: 68bb ldr r3, [r7, #8] 8016916: 2b05 cmp r3, #5 8016918: dc18 bgt.n 801694c { if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) 801691a: f7ff fae1 bl 8015ee0 801691e: 4603 mov r3, r0 8016920: 2b02 cmp r3, #2 8016922: d109 bne.n 8016938 { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); 8016924: 4b10 ldr r3, [pc, #64] @ (8016968 ) 8016926: 6818 ldr r0, [r3, #0] 8016928: f107 0110 add.w r1, r7, #16 801692c: 2300 movs r3, #0 801692e: 6b3a ldr r2, [r7, #48] @ 0x30 8016930: f7fd fce0 bl 80142f4 8016934: 6278 str r0, [r7, #36] @ 0x24 8016936: e012 b.n 801695e } else { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); 8016938: 4b0b ldr r3, [pc, #44] @ (8016968 ) 801693a: 6818 ldr r0, [r3, #0] 801693c: f107 0110 add.w r1, r7, #16 8016940: 2300 movs r3, #0 8016942: 2200 movs r2, #0 8016944: f7fd fcd6 bl 80142f4 8016948: 6278 str r0, [r7, #36] @ 0x24 801694a: e008 b.n 801695e } } else { xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); 801694c: 4b06 ldr r3, [pc, #24] @ (8016968 ) 801694e: 6818 ldr r0, [r3, #0] 8016950: f107 0110 add.w r1, r7, #16 8016954: 2300 movs r3, #0 8016956: 683a ldr r2, [r7, #0] 8016958: f7fd fdce bl 80144f8 801695c: 6278 str r0, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 801695e: 6a7b ldr r3, [r7, #36] @ 0x24 } 8016960: 4618 mov r0, r3 8016962: 3728 adds r7, #40 @ 0x28 8016964: 46bd mov sp, r7 8016966: bd80 pop {r7, pc} 8016968: 24003084 .word 0x24003084 0801696c : return pxTimer->pcTimerName; } /*-----------------------------------------------------------*/ static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) { 801696c: b580 push {r7, lr} 801696e: b088 sub sp, #32 8016970: af02 add r7, sp, #8 8016972: 6078 str r0, [r7, #4] 8016974: 6039 str r1, [r7, #0] BaseType_t xResult; Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8016976: 4b23 ldr r3, [pc, #140] @ (8016a04 ) 8016978: 681b ldr r3, [r3, #0] 801697a: 68db ldr r3, [r3, #12] 801697c: 68db ldr r3, [r3, #12] 801697e: 617b str r3, [r7, #20] /* Remove the timer from the list of active timers. A check has already been performed to ensure the list is not empty. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8016980: 697b ldr r3, [r7, #20] 8016982: 3304 adds r3, #4 8016984: 4618 mov r0, r3 8016986: f7fd fa8d bl 8013ea4 traceTIMER_EXPIRED( pxTimer ); /* If the timer is an auto-reload timer then calculate the next expiry time and re-insert the timer in the list of active timers. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 801698a: 697b ldr r3, [r7, #20] 801698c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016990: f003 0304 and.w r3, r3, #4 8016994: 2b00 cmp r3, #0 8016996: d023 beq.n 80169e0 { /* The timer is inserted into a list using a time relative to anything other than the current time. It will therefore be inserted into the correct list relative to the time this task thinks it is now. */ if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) 8016998: 697b ldr r3, [r7, #20] 801699a: 699a ldr r2, [r3, #24] 801699c: 687b ldr r3, [r7, #4] 801699e: 18d1 adds r1, r2, r3 80169a0: 687b ldr r3, [r7, #4] 80169a2: 683a ldr r2, [r7, #0] 80169a4: 6978 ldr r0, [r7, #20] 80169a6: f000 f8d5 bl 8016b54 80169aa: 4603 mov r3, r0 80169ac: 2b00 cmp r3, #0 80169ae: d020 beq.n 80169f2 { /* The timer expired before it was added to the active timer list. Reload it now. */ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 80169b0: 2300 movs r3, #0 80169b2: 9300 str r3, [sp, #0] 80169b4: 2300 movs r3, #0 80169b6: 687a ldr r2, [r7, #4] 80169b8: 2100 movs r1, #0 80169ba: 6978 ldr r0, [r7, #20] 80169bc: f7ff ff88 bl 80168d0 80169c0: 6138 str r0, [r7, #16] configASSERT( xResult ); 80169c2: 693b ldr r3, [r7, #16] 80169c4: 2b00 cmp r3, #0 80169c6: d114 bne.n 80169f2 __asm volatile 80169c8: f04f 0350 mov.w r3, #80 @ 0x50 80169cc: f383 8811 msr BASEPRI, r3 80169d0: f3bf 8f6f isb sy 80169d4: f3bf 8f4f dsb sy 80169d8: 60fb str r3, [r7, #12] } 80169da: bf00 nop 80169dc: bf00 nop 80169de: e7fd b.n 80169dc mtCOVERAGE_TEST_MARKER(); } } else { pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 80169e0: 697b ldr r3, [r7, #20] 80169e2: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80169e6: f023 0301 bic.w r3, r3, #1 80169ea: b2da uxtb r2, r3 80169ec: 697b ldr r3, [r7, #20] 80169ee: f883 2028 strb.w r2, [r3, #40] @ 0x28 mtCOVERAGE_TEST_MARKER(); } /* Call the timer callback. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 80169f2: 697b ldr r3, [r7, #20] 80169f4: 6a1b ldr r3, [r3, #32] 80169f6: 6978 ldr r0, [r7, #20] 80169f8: 4798 blx r3 } 80169fa: bf00 nop 80169fc: 3718 adds r7, #24 80169fe: 46bd mov sp, r7 8016a00: bd80 pop {r7, pc} 8016a02: bf00 nop 8016a04: 2400307c .word 0x2400307c 08016a08 : /*-----------------------------------------------------------*/ static portTASK_FUNCTION( prvTimerTask, pvParameters ) { 8016a08: b580 push {r7, lr} 8016a0a: b084 sub sp, #16 8016a0c: af00 add r7, sp, #0 8016a0e: 6078 str r0, [r7, #4] for( ;; ) { /* Query the timers list to see if it contains any timers, and if so, obtain the time at which the next timer will expire. */ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8016a10: f107 0308 add.w r3, r7, #8 8016a14: 4618 mov r0, r3 8016a16: f000 f859 bl 8016acc 8016a1a: 60f8 str r0, [r7, #12] /* If a timer has expired, process it. Otherwise, block this task until either a timer does expire, or a command is received. */ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); 8016a1c: 68bb ldr r3, [r7, #8] 8016a1e: 4619 mov r1, r3 8016a20: 68f8 ldr r0, [r7, #12] 8016a22: f000 f805 bl 8016a30 /* Empty the command queue. */ prvProcessReceivedCommands(); 8016a26: f000 f8d7 bl 8016bd8 xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8016a2a: bf00 nop 8016a2c: e7f0 b.n 8016a10 ... 08016a30 : } } /*-----------------------------------------------------------*/ static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) { 8016a30: b580 push {r7, lr} 8016a32: b084 sub sp, #16 8016a34: af00 add r7, sp, #0 8016a36: 6078 str r0, [r7, #4] 8016a38: 6039 str r1, [r7, #0] TickType_t xTimeNow; BaseType_t xTimerListsWereSwitched; vTaskSuspendAll(); 8016a3a: f7fe fe17 bl 801566c /* Obtain the time now to make an assessment as to whether the timer has expired or not. If obtaining the time causes the lists to switch then don't process this timer as any timers that remained in the list when the lists were switched will have been processed within the prvSampleTimeNow() function. */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8016a3e: f107 0308 add.w r3, r7, #8 8016a42: 4618 mov r0, r3 8016a44: f000 f866 bl 8016b14 8016a48: 60f8 str r0, [r7, #12] if( xTimerListsWereSwitched == pdFALSE ) 8016a4a: 68bb ldr r3, [r7, #8] 8016a4c: 2b00 cmp r3, #0 8016a4e: d130 bne.n 8016ab2 { /* The tick count has not overflowed, has the timer expired? */ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) 8016a50: 683b ldr r3, [r7, #0] 8016a52: 2b00 cmp r3, #0 8016a54: d10a bne.n 8016a6c 8016a56: 687a ldr r2, [r7, #4] 8016a58: 68fb ldr r3, [r7, #12] 8016a5a: 429a cmp r2, r3 8016a5c: d806 bhi.n 8016a6c { ( void ) xTaskResumeAll(); 8016a5e: f7fe fe13 bl 8015688 prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); 8016a62: 68f9 ldr r1, [r7, #12] 8016a64: 6878 ldr r0, [r7, #4] 8016a66: f7ff ff81 bl 801696c else { ( void ) xTaskResumeAll(); } } } 8016a6a: e024 b.n 8016ab6 if( xListWasEmpty != pdFALSE ) 8016a6c: 683b ldr r3, [r7, #0] 8016a6e: 2b00 cmp r3, #0 8016a70: d008 beq.n 8016a84 xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); 8016a72: 4b13 ldr r3, [pc, #76] @ (8016ac0 ) 8016a74: 681b ldr r3, [r3, #0] 8016a76: 681b ldr r3, [r3, #0] 8016a78: 2b00 cmp r3, #0 8016a7a: d101 bne.n 8016a80 8016a7c: 2301 movs r3, #1 8016a7e: e000 b.n 8016a82 8016a80: 2300 movs r3, #0 8016a82: 603b str r3, [r7, #0] vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); 8016a84: 4b0f ldr r3, [pc, #60] @ (8016ac4 ) 8016a86: 6818 ldr r0, [r3, #0] 8016a88: 687a ldr r2, [r7, #4] 8016a8a: 68fb ldr r3, [r7, #12] 8016a8c: 1ad3 subs r3, r2, r3 8016a8e: 683a ldr r2, [r7, #0] 8016a90: 4619 mov r1, r3 8016a92: f7fe f995 bl 8014dc0 if( xTaskResumeAll() == pdFALSE ) 8016a96: f7fe fdf7 bl 8015688 8016a9a: 4603 mov r3, r0 8016a9c: 2b00 cmp r3, #0 8016a9e: d10a bne.n 8016ab6 portYIELD_WITHIN_API(); 8016aa0: 4b09 ldr r3, [pc, #36] @ (8016ac8 ) 8016aa2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016aa6: 601a str r2, [r3, #0] 8016aa8: f3bf 8f4f dsb sy 8016aac: f3bf 8f6f isb sy } 8016ab0: e001 b.n 8016ab6 ( void ) xTaskResumeAll(); 8016ab2: f7fe fde9 bl 8015688 } 8016ab6: bf00 nop 8016ab8: 3710 adds r7, #16 8016aba: 46bd mov sp, r7 8016abc: bd80 pop {r7, pc} 8016abe: bf00 nop 8016ac0: 24003080 .word 0x24003080 8016ac4: 24003084 .word 0x24003084 8016ac8: e000ed04 .word 0xe000ed04 08016acc : /*-----------------------------------------------------------*/ static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) { 8016acc: b480 push {r7} 8016ace: b085 sub sp, #20 8016ad0: af00 add r7, sp, #0 8016ad2: 6078 str r0, [r7, #4] the timer with the nearest expiry time will expire. If there are no active timers then just set the next expire time to 0. That will cause this task to unblock when the tick count overflows, at which point the timer lists will be switched and the next expiry time can be re-assessed. */ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); 8016ad4: 4b0e ldr r3, [pc, #56] @ (8016b10 ) 8016ad6: 681b ldr r3, [r3, #0] 8016ad8: 681b ldr r3, [r3, #0] 8016ada: 2b00 cmp r3, #0 8016adc: d101 bne.n 8016ae2 8016ade: 2201 movs r2, #1 8016ae0: e000 b.n 8016ae4 8016ae2: 2200 movs r2, #0 8016ae4: 687b ldr r3, [r7, #4] 8016ae6: 601a str r2, [r3, #0] if( *pxListWasEmpty == pdFALSE ) 8016ae8: 687b ldr r3, [r7, #4] 8016aea: 681b ldr r3, [r3, #0] 8016aec: 2b00 cmp r3, #0 8016aee: d105 bne.n 8016afc { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 8016af0: 4b07 ldr r3, [pc, #28] @ (8016b10 ) 8016af2: 681b ldr r3, [r3, #0] 8016af4: 68db ldr r3, [r3, #12] 8016af6: 681b ldr r3, [r3, #0] 8016af8: 60fb str r3, [r7, #12] 8016afa: e001 b.n 8016b00 } else { /* Ensure the task unblocks when the tick count rolls over. */ xNextExpireTime = ( TickType_t ) 0U; 8016afc: 2300 movs r3, #0 8016afe: 60fb str r3, [r7, #12] } return xNextExpireTime; 8016b00: 68fb ldr r3, [r7, #12] } 8016b02: 4618 mov r0, r3 8016b04: 3714 adds r7, #20 8016b06: 46bd mov sp, r7 8016b08: f85d 7b04 ldr.w r7, [sp], #4 8016b0c: 4770 bx lr 8016b0e: bf00 nop 8016b10: 2400307c .word 0x2400307c 08016b14 : /*-----------------------------------------------------------*/ static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) { 8016b14: b580 push {r7, lr} 8016b16: b084 sub sp, #16 8016b18: af00 add r7, sp, #0 8016b1a: 6078 str r0, [r7, #4] TickType_t xTimeNow; PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ xTimeNow = xTaskGetTickCount(); 8016b1c: f7fe fe52 bl 80157c4 8016b20: 60f8 str r0, [r7, #12] if( xTimeNow < xLastTime ) 8016b22: 4b0b ldr r3, [pc, #44] @ (8016b50 ) 8016b24: 681b ldr r3, [r3, #0] 8016b26: 68fa ldr r2, [r7, #12] 8016b28: 429a cmp r2, r3 8016b2a: d205 bcs.n 8016b38 { prvSwitchTimerLists(); 8016b2c: f000 f93a bl 8016da4 *pxTimerListsWereSwitched = pdTRUE; 8016b30: 687b ldr r3, [r7, #4] 8016b32: 2201 movs r2, #1 8016b34: 601a str r2, [r3, #0] 8016b36: e002 b.n 8016b3e } else { *pxTimerListsWereSwitched = pdFALSE; 8016b38: 687b ldr r3, [r7, #4] 8016b3a: 2200 movs r2, #0 8016b3c: 601a str r2, [r3, #0] } xLastTime = xTimeNow; 8016b3e: 4a04 ldr r2, [pc, #16] @ (8016b50 ) 8016b40: 68fb ldr r3, [r7, #12] 8016b42: 6013 str r3, [r2, #0] return xTimeNow; 8016b44: 68fb ldr r3, [r7, #12] } 8016b46: 4618 mov r0, r3 8016b48: 3710 adds r7, #16 8016b4a: 46bd mov sp, r7 8016b4c: bd80 pop {r7, pc} 8016b4e: bf00 nop 8016b50: 2400308c .word 0x2400308c 08016b54 : /*-----------------------------------------------------------*/ static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) { 8016b54: b580 push {r7, lr} 8016b56: b086 sub sp, #24 8016b58: af00 add r7, sp, #0 8016b5a: 60f8 str r0, [r7, #12] 8016b5c: 60b9 str r1, [r7, #8] 8016b5e: 607a str r2, [r7, #4] 8016b60: 603b str r3, [r7, #0] BaseType_t xProcessTimerNow = pdFALSE; 8016b62: 2300 movs r3, #0 8016b64: 617b str r3, [r7, #20] listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); 8016b66: 68fb ldr r3, [r7, #12] 8016b68: 68ba ldr r2, [r7, #8] 8016b6a: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 8016b6c: 68fb ldr r3, [r7, #12] 8016b6e: 68fa ldr r2, [r7, #12] 8016b70: 611a str r2, [r3, #16] if( xNextExpiryTime <= xTimeNow ) 8016b72: 68ba ldr r2, [r7, #8] 8016b74: 687b ldr r3, [r7, #4] 8016b76: 429a cmp r2, r3 8016b78: d812 bhi.n 8016ba0 { /* Has the expiry time elapsed between the command to start/reset a timer was issued, and the time the command was processed? */ if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016b7a: 687a ldr r2, [r7, #4] 8016b7c: 683b ldr r3, [r7, #0] 8016b7e: 1ad2 subs r2, r2, r3 8016b80: 68fb ldr r3, [r7, #12] 8016b82: 699b ldr r3, [r3, #24] 8016b84: 429a cmp r2, r3 8016b86: d302 bcc.n 8016b8e { /* The time between a command being issued and the command being processed actually exceeds the timers period. */ xProcessTimerNow = pdTRUE; 8016b88: 2301 movs r3, #1 8016b8a: 617b str r3, [r7, #20] 8016b8c: e01b b.n 8016bc6 } else { vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); 8016b8e: 4b10 ldr r3, [pc, #64] @ (8016bd0 ) 8016b90: 681a ldr r2, [r3, #0] 8016b92: 68fb ldr r3, [r7, #12] 8016b94: 3304 adds r3, #4 8016b96: 4619 mov r1, r3 8016b98: 4610 mov r0, r2 8016b9a: f7fd f94a bl 8013e32 8016b9e: e012 b.n 8016bc6 } } else { if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) 8016ba0: 687a ldr r2, [r7, #4] 8016ba2: 683b ldr r3, [r7, #0] 8016ba4: 429a cmp r2, r3 8016ba6: d206 bcs.n 8016bb6 8016ba8: 68ba ldr r2, [r7, #8] 8016baa: 683b ldr r3, [r7, #0] 8016bac: 429a cmp r2, r3 8016bae: d302 bcc.n 8016bb6 { /* If, since the command was issued, the tick count has overflowed but the expiry time has not, then the timer must have already passed its expiry time and should be processed immediately. */ xProcessTimerNow = pdTRUE; 8016bb0: 2301 movs r3, #1 8016bb2: 617b str r3, [r7, #20] 8016bb4: e007 b.n 8016bc6 } else { vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 8016bb6: 4b07 ldr r3, [pc, #28] @ (8016bd4 ) 8016bb8: 681a ldr r2, [r3, #0] 8016bba: 68fb ldr r3, [r7, #12] 8016bbc: 3304 adds r3, #4 8016bbe: 4619 mov r1, r3 8016bc0: 4610 mov r0, r2 8016bc2: f7fd f936 bl 8013e32 } } return xProcessTimerNow; 8016bc6: 697b ldr r3, [r7, #20] } 8016bc8: 4618 mov r0, r3 8016bca: 3718 adds r7, #24 8016bcc: 46bd mov sp, r7 8016bce: bd80 pop {r7, pc} 8016bd0: 24003080 .word 0x24003080 8016bd4: 2400307c .word 0x2400307c 08016bd8 : /*-----------------------------------------------------------*/ static void prvProcessReceivedCommands( void ) { 8016bd8: b580 push {r7, lr} 8016bda: b08e sub sp, #56 @ 0x38 8016bdc: af02 add r7, sp, #8 DaemonTaskMessage_t xMessage; Timer_t *pxTimer; BaseType_t xTimerListsWereSwitched, xResult; TickType_t xTimeNow; while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 8016bde: e0ce b.n 8016d7e { #if ( INCLUDE_xTimerPendFunctionCall == 1 ) { /* Negative commands are pended function calls rather than timer commands. */ if( xMessage.xMessageID < ( BaseType_t ) 0 ) 8016be0: 687b ldr r3, [r7, #4] 8016be2: 2b00 cmp r3, #0 8016be4: da19 bge.n 8016c1a { const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); 8016be6: 1d3b adds r3, r7, #4 8016be8: 3304 adds r3, #4 8016bea: 62fb str r3, [r7, #44] @ 0x2c /* The timer uses the xCallbackParameters member to request a callback be executed. Check the callback is not NULL. */ configASSERT( pxCallback ); 8016bec: 6afb ldr r3, [r7, #44] @ 0x2c 8016bee: 2b00 cmp r3, #0 8016bf0: d10b bne.n 8016c0a __asm volatile 8016bf2: f04f 0350 mov.w r3, #80 @ 0x50 8016bf6: f383 8811 msr BASEPRI, r3 8016bfa: f3bf 8f6f isb sy 8016bfe: f3bf 8f4f dsb sy 8016c02: 61fb str r3, [r7, #28] } 8016c04: bf00 nop 8016c06: bf00 nop 8016c08: e7fd b.n 8016c06 /* Call the function. */ pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); 8016c0a: 6afb ldr r3, [r7, #44] @ 0x2c 8016c0c: 681b ldr r3, [r3, #0] 8016c0e: 6afa ldr r2, [r7, #44] @ 0x2c 8016c10: 6850 ldr r0, [r2, #4] 8016c12: 6afa ldr r2, [r7, #44] @ 0x2c 8016c14: 6892 ldr r2, [r2, #8] 8016c16: 4611 mov r1, r2 8016c18: 4798 blx r3 } #endif /* INCLUDE_xTimerPendFunctionCall */ /* Commands that are positive are timer commands rather than pended function calls. */ if( xMessage.xMessageID >= ( BaseType_t ) 0 ) 8016c1a: 687b ldr r3, [r7, #4] 8016c1c: 2b00 cmp r3, #0 8016c1e: f2c0 80ae blt.w 8016d7e { /* The messages uses the xTimerParameters member to work on a software timer. */ pxTimer = xMessage.u.xTimerParameters.pxTimer; 8016c22: 68fb ldr r3, [r7, #12] 8016c24: 62bb str r3, [r7, #40] @ 0x28 if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ 8016c26: 6abb ldr r3, [r7, #40] @ 0x28 8016c28: 695b ldr r3, [r3, #20] 8016c2a: 2b00 cmp r3, #0 8016c2c: d004 beq.n 8016c38 { /* The timer is in a list, remove it. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8016c2e: 6abb ldr r3, [r7, #40] @ 0x28 8016c30: 3304 adds r3, #4 8016c32: 4618 mov r0, r3 8016c34: f7fd f936 bl 8013ea4 it must be present in the function call. prvSampleTimeNow() must be called after the message is received from xTimerQueue so there is no possibility of a higher priority task adding a message to the message queue with a time that is ahead of the timer daemon task (because it pre-empted the timer daemon task after the xTimeNow value was set). */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8016c38: 463b mov r3, r7 8016c3a: 4618 mov r0, r3 8016c3c: f7ff ff6a bl 8016b14 8016c40: 6278 str r0, [r7, #36] @ 0x24 switch( xMessage.xMessageID ) 8016c42: 687b ldr r3, [r7, #4] 8016c44: 2b09 cmp r3, #9 8016c46: f200 8097 bhi.w 8016d78 8016c4a: a201 add r2, pc, #4 @ (adr r2, 8016c50 ) 8016c4c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016c50: 08016c79 .word 0x08016c79 8016c54: 08016c79 .word 0x08016c79 8016c58: 08016c79 .word 0x08016c79 8016c5c: 08016cef .word 0x08016cef 8016c60: 08016d03 .word 0x08016d03 8016c64: 08016d4f .word 0x08016d4f 8016c68: 08016c79 .word 0x08016c79 8016c6c: 08016c79 .word 0x08016c79 8016c70: 08016cef .word 0x08016cef 8016c74: 08016d03 .word 0x08016d03 case tmrCOMMAND_START_FROM_ISR : case tmrCOMMAND_RESET : case tmrCOMMAND_RESET_FROM_ISR : case tmrCOMMAND_START_DONT_TRACE : /* Start or restart a timer. */ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8016c78: 6abb ldr r3, [r7, #40] @ 0x28 8016c7a: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016c7e: f043 0301 orr.w r3, r3, #1 8016c82: b2da uxtb r2, r3 8016c84: 6abb ldr r3, [r7, #40] @ 0x28 8016c86: f883 2028 strb.w r2, [r3, #40] @ 0x28 if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) 8016c8a: 68ba ldr r2, [r7, #8] 8016c8c: 6abb ldr r3, [r7, #40] @ 0x28 8016c8e: 699b ldr r3, [r3, #24] 8016c90: 18d1 adds r1, r2, r3 8016c92: 68bb ldr r3, [r7, #8] 8016c94: 6a7a ldr r2, [r7, #36] @ 0x24 8016c96: 6ab8 ldr r0, [r7, #40] @ 0x28 8016c98: f7ff ff5c bl 8016b54 8016c9c: 4603 mov r3, r0 8016c9e: 2b00 cmp r3, #0 8016ca0: d06c beq.n 8016d7c { /* The timer expired before it was added to the active timer list. Process it now. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8016ca2: 6abb ldr r3, [r7, #40] @ 0x28 8016ca4: 6a1b ldr r3, [r3, #32] 8016ca6: 6ab8 ldr r0, [r7, #40] @ 0x28 8016ca8: 4798 blx r3 traceTIMER_EXPIRED( pxTimer ); if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 8016caa: 6abb ldr r3, [r7, #40] @ 0x28 8016cac: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016cb0: f003 0304 and.w r3, r3, #4 8016cb4: 2b00 cmp r3, #0 8016cb6: d061 beq.n 8016d7c { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); 8016cb8: 68ba ldr r2, [r7, #8] 8016cba: 6abb ldr r3, [r7, #40] @ 0x28 8016cbc: 699b ldr r3, [r3, #24] 8016cbe: 441a add r2, r3 8016cc0: 2300 movs r3, #0 8016cc2: 9300 str r3, [sp, #0] 8016cc4: 2300 movs r3, #0 8016cc6: 2100 movs r1, #0 8016cc8: 6ab8 ldr r0, [r7, #40] @ 0x28 8016cca: f7ff fe01 bl 80168d0 8016cce: 6238 str r0, [r7, #32] configASSERT( xResult ); 8016cd0: 6a3b ldr r3, [r7, #32] 8016cd2: 2b00 cmp r3, #0 8016cd4: d152 bne.n 8016d7c __asm volatile 8016cd6: f04f 0350 mov.w r3, #80 @ 0x50 8016cda: f383 8811 msr BASEPRI, r3 8016cde: f3bf 8f6f isb sy 8016ce2: f3bf 8f4f dsb sy 8016ce6: 61bb str r3, [r7, #24] } 8016ce8: bf00 nop 8016cea: bf00 nop 8016cec: e7fd b.n 8016cea break; case tmrCOMMAND_STOP : case tmrCOMMAND_STOP_FROM_ISR : /* The timer has already been removed from the active list. */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8016cee: 6abb ldr r3, [r7, #40] @ 0x28 8016cf0: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016cf4: f023 0301 bic.w r3, r3, #1 8016cf8: b2da uxtb r2, r3 8016cfa: 6abb ldr r3, [r7, #40] @ 0x28 8016cfc: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8016d00: e03d b.n 8016d7e case tmrCOMMAND_CHANGE_PERIOD : case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR : pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8016d02: 6abb ldr r3, [r7, #40] @ 0x28 8016d04: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016d08: f043 0301 orr.w r3, r3, #1 8016d0c: b2da uxtb r2, r3 8016d0e: 6abb ldr r3, [r7, #40] @ 0x28 8016d10: f883 2028 strb.w r2, [r3, #40] @ 0x28 pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; 8016d14: 68ba ldr r2, [r7, #8] 8016d16: 6abb ldr r3, [r7, #40] @ 0x28 8016d18: 619a str r2, [r3, #24] configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); 8016d1a: 6abb ldr r3, [r7, #40] @ 0x28 8016d1c: 699b ldr r3, [r3, #24] 8016d1e: 2b00 cmp r3, #0 8016d20: d10b bne.n 8016d3a __asm volatile 8016d22: f04f 0350 mov.w r3, #80 @ 0x50 8016d26: f383 8811 msr BASEPRI, r3 8016d2a: f3bf 8f6f isb sy 8016d2e: f3bf 8f4f dsb sy 8016d32: 617b str r3, [r7, #20] } 8016d34: bf00 nop 8016d36: bf00 nop 8016d38: e7fd b.n 8016d36 be longer or shorter than the old one. The command time is therefore set to the current time, and as the period cannot be zero the next expiry time can only be in the future, meaning (unlike for the xTimerStart() case above) there is no fail case that needs to be handled here. */ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); 8016d3a: 6abb ldr r3, [r7, #40] @ 0x28 8016d3c: 699a ldr r2, [r3, #24] 8016d3e: 6a7b ldr r3, [r7, #36] @ 0x24 8016d40: 18d1 adds r1, r2, r3 8016d42: 6a7b ldr r3, [r7, #36] @ 0x24 8016d44: 6a7a ldr r2, [r7, #36] @ 0x24 8016d46: 6ab8 ldr r0, [r7, #40] @ 0x28 8016d48: f7ff ff04 bl 8016b54 break; 8016d4c: e017 b.n 8016d7e #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* The timer has already been removed from the active list, just free up the memory if the memory was dynamically allocated. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) 8016d4e: 6abb ldr r3, [r7, #40] @ 0x28 8016d50: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016d54: f003 0302 and.w r3, r3, #2 8016d58: 2b00 cmp r3, #0 8016d5a: d103 bne.n 8016d64 { vPortFree( pxTimer ); 8016d5c: 6ab8 ldr r0, [r7, #40] @ 0x28 8016d5e: f000 fc33 bl 80175c8 no need to free the memory - just mark the timer as "not active". */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ break; 8016d62: e00c b.n 8016d7e pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8016d64: 6abb ldr r3, [r7, #40] @ 0x28 8016d66: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016d6a: f023 0301 bic.w r3, r3, #1 8016d6e: b2da uxtb r2, r3 8016d70: 6abb ldr r3, [r7, #40] @ 0x28 8016d72: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8016d76: e002 b.n 8016d7e default : /* Don't expect to get here. */ break; 8016d78: bf00 nop 8016d7a: e000 b.n 8016d7e break; 8016d7c: bf00 nop while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 8016d7e: 4b08 ldr r3, [pc, #32] @ (8016da0 ) 8016d80: 681b ldr r3, [r3, #0] 8016d82: 1d39 adds r1, r7, #4 8016d84: 2200 movs r2, #0 8016d86: 4618 mov r0, r3 8016d88: f7fd fc54 bl 8014634 8016d8c: 4603 mov r3, r0 8016d8e: 2b00 cmp r3, #0 8016d90: f47f af26 bne.w 8016be0 } } } } 8016d94: bf00 nop 8016d96: bf00 nop 8016d98: 3730 adds r7, #48 @ 0x30 8016d9a: 46bd mov sp, r7 8016d9c: bd80 pop {r7, pc} 8016d9e: bf00 nop 8016da0: 24003084 .word 0x24003084 08016da4 : /*-----------------------------------------------------------*/ static void prvSwitchTimerLists( void ) { 8016da4: b580 push {r7, lr} 8016da6: b088 sub sp, #32 8016da8: af02 add r7, sp, #8 /* The tick count has overflowed. The timer lists must be switched. If there are any timers still referenced from the current timer list then they must have expired and should be processed before the lists are switched. */ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 8016daa: e049 b.n 8016e40 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 8016dac: 4b2e ldr r3, [pc, #184] @ (8016e68 ) 8016dae: 681b ldr r3, [r3, #0] 8016db0: 68db ldr r3, [r3, #12] 8016db2: 681b ldr r3, [r3, #0] 8016db4: 613b str r3, [r7, #16] /* Remove the timer from the list. */ pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8016db6: 4b2c ldr r3, [pc, #176] @ (8016e68 ) 8016db8: 681b ldr r3, [r3, #0] 8016dba: 68db ldr r3, [r3, #12] 8016dbc: 68db ldr r3, [r3, #12] 8016dbe: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8016dc0: 68fb ldr r3, [r7, #12] 8016dc2: 3304 adds r3, #4 8016dc4: 4618 mov r0, r3 8016dc6: f7fd f86d bl 8013ea4 traceTIMER_EXPIRED( pxTimer ); /* Execute its callback, then send a command to restart the timer if it is an auto-reload timer. It cannot be restarted here as the lists have not yet been switched. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8016dca: 68fb ldr r3, [r7, #12] 8016dcc: 6a1b ldr r3, [r3, #32] 8016dce: 68f8 ldr r0, [r7, #12] 8016dd0: 4798 blx r3 if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 8016dd2: 68fb ldr r3, [r7, #12] 8016dd4: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016dd8: f003 0304 and.w r3, r3, #4 8016ddc: 2b00 cmp r3, #0 8016dde: d02f beq.n 8016e40 the timer going into the same timer list then it has already expired and the timer should be re-inserted into the current list so it is processed again within this loop. Otherwise a command should be sent to restart the timer to ensure it is only inserted into a list after the lists have been swapped. */ xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); 8016de0: 68fb ldr r3, [r7, #12] 8016de2: 699b ldr r3, [r3, #24] 8016de4: 693a ldr r2, [r7, #16] 8016de6: 4413 add r3, r2 8016de8: 60bb str r3, [r7, #8] if( xReloadTime > xNextExpireTime ) 8016dea: 68ba ldr r2, [r7, #8] 8016dec: 693b ldr r3, [r7, #16] 8016dee: 429a cmp r2, r3 8016df0: d90e bls.n 8016e10 { listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); 8016df2: 68fb ldr r3, [r7, #12] 8016df4: 68ba ldr r2, [r7, #8] 8016df6: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 8016df8: 68fb ldr r3, [r7, #12] 8016dfa: 68fa ldr r2, [r7, #12] 8016dfc: 611a str r2, [r3, #16] vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 8016dfe: 4b1a ldr r3, [pc, #104] @ (8016e68 ) 8016e00: 681a ldr r2, [r3, #0] 8016e02: 68fb ldr r3, [r7, #12] 8016e04: 3304 adds r3, #4 8016e06: 4619 mov r1, r3 8016e08: 4610 mov r0, r2 8016e0a: f7fd f812 bl 8013e32 8016e0e: e017 b.n 8016e40 } else { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 8016e10: 2300 movs r3, #0 8016e12: 9300 str r3, [sp, #0] 8016e14: 2300 movs r3, #0 8016e16: 693a ldr r2, [r7, #16] 8016e18: 2100 movs r1, #0 8016e1a: 68f8 ldr r0, [r7, #12] 8016e1c: f7ff fd58 bl 80168d0 8016e20: 6078 str r0, [r7, #4] configASSERT( xResult ); 8016e22: 687b ldr r3, [r7, #4] 8016e24: 2b00 cmp r3, #0 8016e26: d10b bne.n 8016e40 __asm volatile 8016e28: f04f 0350 mov.w r3, #80 @ 0x50 8016e2c: f383 8811 msr BASEPRI, r3 8016e30: f3bf 8f6f isb sy 8016e34: f3bf 8f4f dsb sy 8016e38: 603b str r3, [r7, #0] } 8016e3a: bf00 nop 8016e3c: bf00 nop 8016e3e: e7fd b.n 8016e3c while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 8016e40: 4b09 ldr r3, [pc, #36] @ (8016e68 ) 8016e42: 681b ldr r3, [r3, #0] 8016e44: 681b ldr r3, [r3, #0] 8016e46: 2b00 cmp r3, #0 8016e48: d1b0 bne.n 8016dac { mtCOVERAGE_TEST_MARKER(); } } pxTemp = pxCurrentTimerList; 8016e4a: 4b07 ldr r3, [pc, #28] @ (8016e68 ) 8016e4c: 681b ldr r3, [r3, #0] 8016e4e: 617b str r3, [r7, #20] pxCurrentTimerList = pxOverflowTimerList; 8016e50: 4b06 ldr r3, [pc, #24] @ (8016e6c ) 8016e52: 681b ldr r3, [r3, #0] 8016e54: 4a04 ldr r2, [pc, #16] @ (8016e68 ) 8016e56: 6013 str r3, [r2, #0] pxOverflowTimerList = pxTemp; 8016e58: 4a04 ldr r2, [pc, #16] @ (8016e6c ) 8016e5a: 697b ldr r3, [r7, #20] 8016e5c: 6013 str r3, [r2, #0] } 8016e5e: bf00 nop 8016e60: 3718 adds r7, #24 8016e62: 46bd mov sp, r7 8016e64: bd80 pop {r7, pc} 8016e66: bf00 nop 8016e68: 2400307c .word 0x2400307c 8016e6c: 24003080 .word 0x24003080 08016e70 : /*-----------------------------------------------------------*/ static void prvCheckForValidListAndQueue( void ) { 8016e70: b580 push {r7, lr} 8016e72: b082 sub sp, #8 8016e74: af02 add r7, sp, #8 /* Check that the list from which active timers are referenced, and the queue used to communicate with the timer service, have been initialised. */ taskENTER_CRITICAL(); 8016e76: f000 f9b7 bl 80171e8 { if( xTimerQueue == NULL ) 8016e7a: 4b15 ldr r3, [pc, #84] @ (8016ed0 ) 8016e7c: 681b ldr r3, [r3, #0] 8016e7e: 2b00 cmp r3, #0 8016e80: d120 bne.n 8016ec4 { vListInitialise( &xActiveTimerList1 ); 8016e82: 4814 ldr r0, [pc, #80] @ (8016ed4 ) 8016e84: f7fc ff84 bl 8013d90 vListInitialise( &xActiveTimerList2 ); 8016e88: 4813 ldr r0, [pc, #76] @ (8016ed8 ) 8016e8a: f7fc ff81 bl 8013d90 pxCurrentTimerList = &xActiveTimerList1; 8016e8e: 4b13 ldr r3, [pc, #76] @ (8016edc ) 8016e90: 4a10 ldr r2, [pc, #64] @ (8016ed4 ) 8016e92: 601a str r2, [r3, #0] pxOverflowTimerList = &xActiveTimerList2; 8016e94: 4b12 ldr r3, [pc, #72] @ (8016ee0 ) 8016e96: 4a10 ldr r2, [pc, #64] @ (8016ed8 ) 8016e98: 601a str r2, [r3, #0] /* The timer queue is allocated statically in case configSUPPORT_DYNAMIC_ALLOCATION is 0. */ static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 8016e9a: 2300 movs r3, #0 8016e9c: 9300 str r3, [sp, #0] 8016e9e: 4b11 ldr r3, [pc, #68] @ (8016ee4 ) 8016ea0: 4a11 ldr r2, [pc, #68] @ (8016ee8 ) 8016ea2: 2110 movs r1, #16 8016ea4: 200a movs r0, #10 8016ea6: f7fd f891 bl 8013fcc 8016eaa: 4603 mov r3, r0 8016eac: 4a08 ldr r2, [pc, #32] @ (8016ed0 ) 8016eae: 6013 str r3, [r2, #0] } #endif #if ( configQUEUE_REGISTRY_SIZE > 0 ) { if( xTimerQueue != NULL ) 8016eb0: 4b07 ldr r3, [pc, #28] @ (8016ed0 ) 8016eb2: 681b ldr r3, [r3, #0] 8016eb4: 2b00 cmp r3, #0 8016eb6: d005 beq.n 8016ec4 { vQueueAddToRegistry( xTimerQueue, "TmrQ" ); 8016eb8: 4b05 ldr r3, [pc, #20] @ (8016ed0 ) 8016eba: 681b ldr r3, [r3, #0] 8016ebc: 490b ldr r1, [pc, #44] @ (8016eec ) 8016ebe: 4618 mov r0, r3 8016ec0: f7fd ff54 bl 8014d6c else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016ec4: f000 f9c2 bl 801724c } 8016ec8: bf00 nop 8016eca: 46bd mov sp, r7 8016ecc: bd80 pop {r7, pc} 8016ece: bf00 nop 8016ed0: 24003084 .word 0x24003084 8016ed4: 24003054 .word 0x24003054 8016ed8: 24003068 .word 0x24003068 8016edc: 2400307c .word 0x2400307c 8016ee0: 24003080 .word 0x24003080 8016ee4: 24003130 .word 0x24003130 8016ee8: 24003090 .word 0x24003090 8016eec: 0801a21c .word 0x0801a21c 08016ef0 : /*-----------------------------------------------------------*/ BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) { 8016ef0: b580 push {r7, lr} 8016ef2: b086 sub sp, #24 8016ef4: af00 add r7, sp, #0 8016ef6: 6078 str r0, [r7, #4] BaseType_t xReturn; Timer_t *pxTimer = xTimer; 8016ef8: 687b ldr r3, [r7, #4] 8016efa: 613b str r3, [r7, #16] configASSERT( xTimer ); 8016efc: 687b ldr r3, [r7, #4] 8016efe: 2b00 cmp r3, #0 8016f00: d10b bne.n 8016f1a __asm volatile 8016f02: f04f 0350 mov.w r3, #80 @ 0x50 8016f06: f383 8811 msr BASEPRI, r3 8016f0a: f3bf 8f6f isb sy 8016f0e: f3bf 8f4f dsb sy 8016f12: 60fb str r3, [r7, #12] } 8016f14: bf00 nop 8016f16: bf00 nop 8016f18: e7fd b.n 8016f16 /* Is the timer in the list of active timers? */ taskENTER_CRITICAL(); 8016f1a: f000 f965 bl 80171e8 { if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 ) 8016f1e: 693b ldr r3, [r7, #16] 8016f20: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016f24: f003 0301 and.w r3, r3, #1 8016f28: 2b00 cmp r3, #0 8016f2a: d102 bne.n 8016f32 { xReturn = pdFALSE; 8016f2c: 2300 movs r3, #0 8016f2e: 617b str r3, [r7, #20] 8016f30: e001 b.n 8016f36 } else { xReturn = pdTRUE; 8016f32: 2301 movs r3, #1 8016f34: 617b str r3, [r7, #20] } } taskEXIT_CRITICAL(); 8016f36: f000 f989 bl 801724c return xReturn; 8016f3a: 697b ldr r3, [r7, #20] } /*lint !e818 Can't be pointer to const due to the typedef. */ 8016f3c: 4618 mov r0, r3 8016f3e: 3718 adds r7, #24 8016f40: 46bd mov sp, r7 8016f42: bd80 pop {r7, pc} 08016f44 : /*-----------------------------------------------------------*/ void *pvTimerGetTimerID( const TimerHandle_t xTimer ) { 8016f44: b580 push {r7, lr} 8016f46: b086 sub sp, #24 8016f48: af00 add r7, sp, #0 8016f4a: 6078 str r0, [r7, #4] Timer_t * const pxTimer = xTimer; 8016f4c: 687b ldr r3, [r7, #4] 8016f4e: 617b str r3, [r7, #20] void *pvReturn; configASSERT( xTimer ); 8016f50: 687b ldr r3, [r7, #4] 8016f52: 2b00 cmp r3, #0 8016f54: d10b bne.n 8016f6e __asm volatile 8016f56: f04f 0350 mov.w r3, #80 @ 0x50 8016f5a: f383 8811 msr BASEPRI, r3 8016f5e: f3bf 8f6f isb sy 8016f62: f3bf 8f4f dsb sy 8016f66: 60fb str r3, [r7, #12] } 8016f68: bf00 nop 8016f6a: bf00 nop 8016f6c: e7fd b.n 8016f6a taskENTER_CRITICAL(); 8016f6e: f000 f93b bl 80171e8 { pvReturn = pxTimer->pvTimerID; 8016f72: 697b ldr r3, [r7, #20] 8016f74: 69db ldr r3, [r3, #28] 8016f76: 613b str r3, [r7, #16] } taskEXIT_CRITICAL(); 8016f78: f000 f968 bl 801724c return pvReturn; 8016f7c: 693b ldr r3, [r7, #16] } 8016f7e: 4618 mov r0, r3 8016f80: 3718 adds r7, #24 8016f82: 46bd mov sp, r7 8016f84: bd80 pop {r7, pc} ... 08016f88 : /* * See header file for description. */ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) { 8016f88: b480 push {r7} 8016f8a: b085 sub sp, #20 8016f8c: af00 add r7, sp, #0 8016f8e: 60f8 str r0, [r7, #12] 8016f90: 60b9 str r1, [r7, #8] 8016f92: 607a str r2, [r7, #4] /* Simulate the stack frame as it would be created by a context switch interrupt. */ /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts, and to ensure alignment. */ pxTopOfStack--; 8016f94: 68fb ldr r3, [r7, #12] 8016f96: 3b04 subs r3, #4 8016f98: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ 8016f9a: 68fb ldr r3, [r7, #12] 8016f9c: f04f 7280 mov.w r2, #16777216 @ 0x1000000 8016fa0: 601a str r2, [r3, #0] pxTopOfStack--; 8016fa2: 68fb ldr r3, [r7, #12] 8016fa4: 3b04 subs r3, #4 8016fa6: 60fb str r3, [r7, #12] *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ 8016fa8: 68bb ldr r3, [r7, #8] 8016faa: f023 0201 bic.w r2, r3, #1 8016fae: 68fb ldr r3, [r7, #12] 8016fb0: 601a str r2, [r3, #0] pxTopOfStack--; 8016fb2: 68fb ldr r3, [r7, #12] 8016fb4: 3b04 subs r3, #4 8016fb6: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ 8016fb8: 4a0c ldr r2, [pc, #48] @ (8016fec ) 8016fba: 68fb ldr r3, [r7, #12] 8016fbc: 601a str r2, [r3, #0] /* Save code space by skipping register initialisation. */ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ 8016fbe: 68fb ldr r3, [r7, #12] 8016fc0: 3b14 subs r3, #20 8016fc2: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ 8016fc4: 687a ldr r2, [r7, #4] 8016fc6: 68fb ldr r3, [r7, #12] 8016fc8: 601a str r2, [r3, #0] /* A save method is being used that requires each task to maintain its own exec return value. */ pxTopOfStack--; 8016fca: 68fb ldr r3, [r7, #12] 8016fcc: 3b04 subs r3, #4 8016fce: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_EXC_RETURN; 8016fd0: 68fb ldr r3, [r7, #12] 8016fd2: f06f 0202 mvn.w r2, #2 8016fd6: 601a str r2, [r3, #0] pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ 8016fd8: 68fb ldr r3, [r7, #12] 8016fda: 3b20 subs r3, #32 8016fdc: 60fb str r3, [r7, #12] return pxTopOfStack; 8016fde: 68fb ldr r3, [r7, #12] } 8016fe0: 4618 mov r0, r3 8016fe2: 3714 adds r7, #20 8016fe4: 46bd mov sp, r7 8016fe6: f85d 7b04 ldr.w r7, [sp], #4 8016fea: 4770 bx lr 8016fec: 08016ff1 .word 0x08016ff1 08016ff0 : /*-----------------------------------------------------------*/ static void prvTaskExitError( void ) { 8016ff0: b480 push {r7} 8016ff2: b085 sub sp, #20 8016ff4: af00 add r7, sp, #0 volatile uint32_t ulDummy = 0; 8016ff6: 2300 movs r3, #0 8016ff8: 607b str r3, [r7, #4] its caller as there is nothing to return to. If a task wants to exit it should instead call vTaskDelete( NULL ). Artificially force an assert() to be triggered if configASSERT() is defined, then stop here so application writers can catch the error. */ configASSERT( uxCriticalNesting == ~0UL ); 8016ffa: 4b13 ldr r3, [pc, #76] @ (8017048 ) 8016ffc: 681b ldr r3, [r3, #0] 8016ffe: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8017002: d00b beq.n 801701c __asm volatile 8017004: f04f 0350 mov.w r3, #80 @ 0x50 8017008: f383 8811 msr BASEPRI, r3 801700c: f3bf 8f6f isb sy 8017010: f3bf 8f4f dsb sy 8017014: 60fb str r3, [r7, #12] } 8017016: bf00 nop 8017018: bf00 nop 801701a: e7fd b.n 8017018 __asm volatile 801701c: f04f 0350 mov.w r3, #80 @ 0x50 8017020: f383 8811 msr BASEPRI, r3 8017024: f3bf 8f6f isb sy 8017028: f3bf 8f4f dsb sy 801702c: 60bb str r3, [r7, #8] } 801702e: bf00 nop portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) 8017030: bf00 nop 8017032: 687b ldr r3, [r7, #4] 8017034: 2b00 cmp r3, #0 8017036: d0fc beq.n 8017032 about code appearing after this function is called - making ulDummy volatile makes the compiler think the function could return and therefore not output an 'unreachable code' warning for code that appears after it. */ } } 8017038: bf00 nop 801703a: bf00 nop 801703c: 3714 adds r7, #20 801703e: 46bd mov sp, r7 8017040: f85d 7b04 ldr.w r7, [sp], #4 8017044: 4770 bx lr 8017046: bf00 nop 8017048: 24000044 .word 0x24000044 801704c: 00000000 .word 0x00000000 08017050 : /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( 8017050: 4b07 ldr r3, [pc, #28] @ (8017070 ) 8017052: 6819 ldr r1, [r3, #0] 8017054: 6808 ldr r0, [r1, #0] 8017056: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801705a: f380 8809 msr PSP, r0 801705e: f3bf 8f6f isb sy 8017062: f04f 0000 mov.w r0, #0 8017066: f380 8811 msr BASEPRI, r0 801706a: 4770 bx lr 801706c: f3af 8000 nop.w 08017070 : 8017070: 24002b54 .word 0x24002b54 " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } 8017074: bf00 nop 8017076: bf00 nop 08017078 : { /* Start the first task. This also clears the bit that indicates the FPU is in use in case the FPU was used before the scheduler was started - which would otherwise result in the unnecessary leaving of space in the SVC stack for lazy saving of FPU registers. */ __asm volatile( 8017078: 4808 ldr r0, [pc, #32] @ (801709c ) 801707a: 6800 ldr r0, [r0, #0] 801707c: 6800 ldr r0, [r0, #0] 801707e: f380 8808 msr MSP, r0 8017082: f04f 0000 mov.w r0, #0 8017086: f380 8814 msr CONTROL, r0 801708a: b662 cpsie i 801708c: b661 cpsie f 801708e: f3bf 8f4f dsb sy 8017092: f3bf 8f6f isb sy 8017096: df00 svc 0 8017098: bf00 nop " dsb \n" " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n" ); } 801709a: bf00 nop 801709c: e000ed08 .word 0xe000ed08 080170a0 : /* * See header file for description. */ BaseType_t xPortStartScheduler( void ) { 80170a0: b580 push {r7, lr} 80170a2: b086 sub sp, #24 80170a4: af00 add r7, sp, #0 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); /* This port can be used on all revisions of the Cortex-M7 core other than the r0p1 parts. r0p1 parts should use the port from the /source/portable/GCC/ARM_CM7/r0p1 directory. */ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); 80170a6: 4b47 ldr r3, [pc, #284] @ (80171c4 ) 80170a8: 681b ldr r3, [r3, #0] 80170aa: 4a47 ldr r2, [pc, #284] @ (80171c8 ) 80170ac: 4293 cmp r3, r2 80170ae: d10b bne.n 80170c8 __asm volatile 80170b0: f04f 0350 mov.w r3, #80 @ 0x50 80170b4: f383 8811 msr BASEPRI, r3 80170b8: f3bf 8f6f isb sy 80170bc: f3bf 8f4f dsb sy 80170c0: 613b str r3, [r7, #16] } 80170c2: bf00 nop 80170c4: bf00 nop 80170c6: e7fd b.n 80170c4 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); 80170c8: 4b3e ldr r3, [pc, #248] @ (80171c4 ) 80170ca: 681b ldr r3, [r3, #0] 80170cc: 4a3f ldr r2, [pc, #252] @ (80171cc ) 80170ce: 4293 cmp r3, r2 80170d0: d10b bne.n 80170ea __asm volatile 80170d2: f04f 0350 mov.w r3, #80 @ 0x50 80170d6: f383 8811 msr BASEPRI, r3 80170da: f3bf 8f6f isb sy 80170de: f3bf 8f4f dsb sy 80170e2: 60fb str r3, [r7, #12] } 80170e4: bf00 nop 80170e6: bf00 nop 80170e8: e7fd b.n 80170e6 #if( configASSERT_DEFINED == 1 ) { volatile uint32_t ulOriginalPriority; volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); 80170ea: 4b39 ldr r3, [pc, #228] @ (80171d0 ) 80170ec: 617b str r3, [r7, #20] functions can be called. ISR safe functions are those that end in "FromISR". FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. Save the interrupt priority value that is about to be clobbered. */ ulOriginalPriority = *pucFirstUserPriorityRegister; 80170ee: 697b ldr r3, [r7, #20] 80170f0: 781b ldrb r3, [r3, #0] 80170f2: b2db uxtb r3, r3 80170f4: 607b str r3, [r7, #4] /* Determine the number of priority bits available. First write to all possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; 80170f6: 697b ldr r3, [r7, #20] 80170f8: 22ff movs r2, #255 @ 0xff 80170fa: 701a strb r2, [r3, #0] /* Read the value back to see how many bits stuck. */ ucMaxPriorityValue = *pucFirstUserPriorityRegister; 80170fc: 697b ldr r3, [r7, #20] 80170fe: 781b ldrb r3, [r3, #0] 8017100: b2db uxtb r3, r3 8017102: 70fb strb r3, [r7, #3] /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; 8017104: 78fb ldrb r3, [r7, #3] 8017106: b2db uxtb r3, r3 8017108: f003 0350 and.w r3, r3, #80 @ 0x50 801710c: b2da uxtb r2, r3 801710e: 4b31 ldr r3, [pc, #196] @ (80171d4 ) 8017110: 701a strb r2, [r3, #0] /* Calculate the maximum acceptable priority group value for the number of bits read back. */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; 8017112: 4b31 ldr r3, [pc, #196] @ (80171d8 ) 8017114: 2207 movs r2, #7 8017116: 601a str r2, [r3, #0] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 8017118: e009 b.n 801712e { ulMaxPRIGROUPValue--; 801711a: 4b2f ldr r3, [pc, #188] @ (80171d8 ) 801711c: 681b ldr r3, [r3, #0] 801711e: 3b01 subs r3, #1 8017120: 4a2d ldr r2, [pc, #180] @ (80171d8 ) 8017122: 6013 str r3, [r2, #0] ucMaxPriorityValue <<= ( uint8_t ) 0x01; 8017124: 78fb ldrb r3, [r7, #3] 8017126: b2db uxtb r3, r3 8017128: 005b lsls r3, r3, #1 801712a: b2db uxtb r3, r3 801712c: 70fb strb r3, [r7, #3] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 801712e: 78fb ldrb r3, [r7, #3] 8017130: b2db uxtb r3, r3 8017132: f003 0380 and.w r3, r3, #128 @ 0x80 8017136: 2b80 cmp r3, #128 @ 0x80 8017138: d0ef beq.n 801711a #ifdef configPRIO_BITS { /* Check the FreeRTOS configuration that defines the number of priority bits matches the number of priority bits actually queried from the hardware. */ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); 801713a: 4b27 ldr r3, [pc, #156] @ (80171d8 ) 801713c: 681b ldr r3, [r3, #0] 801713e: f1c3 0307 rsb r3, r3, #7 8017142: 2b04 cmp r3, #4 8017144: d00b beq.n 801715e __asm volatile 8017146: f04f 0350 mov.w r3, #80 @ 0x50 801714a: f383 8811 msr BASEPRI, r3 801714e: f3bf 8f6f isb sy 8017152: f3bf 8f4f dsb sy 8017156: 60bb str r3, [r7, #8] } 8017158: bf00 nop 801715a: bf00 nop 801715c: e7fd b.n 801715a } #endif /* Shift the priority group value back to its position within the AIRCR register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; 801715e: 4b1e ldr r3, [pc, #120] @ (80171d8 ) 8017160: 681b ldr r3, [r3, #0] 8017162: 021b lsls r3, r3, #8 8017164: 4a1c ldr r2, [pc, #112] @ (80171d8 ) 8017166: 6013 str r3, [r2, #0] ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; 8017168: 4b1b ldr r3, [pc, #108] @ (80171d8 ) 801716a: 681b ldr r3, [r3, #0] 801716c: f403 63e0 and.w r3, r3, #1792 @ 0x700 8017170: 4a19 ldr r2, [pc, #100] @ (80171d8 ) 8017172: 6013 str r3, [r2, #0] /* Restore the clobbered interrupt priority register to its original value. */ *pucFirstUserPriorityRegister = ulOriginalPriority; 8017174: 687b ldr r3, [r7, #4] 8017176: b2da uxtb r2, r3 8017178: 697b ldr r3, [r7, #20] 801717a: 701a strb r2, [r3, #0] } #endif /* conifgASSERT_DEFINED */ /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; 801717c: 4b17 ldr r3, [pc, #92] @ (80171dc ) 801717e: 681b ldr r3, [r3, #0] 8017180: 4a16 ldr r2, [pc, #88] @ (80171dc ) 8017182: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8017186: 6013 str r3, [r2, #0] portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; 8017188: 4b14 ldr r3, [pc, #80] @ (80171dc ) 801718a: 681b ldr r3, [r3, #0] 801718c: 4a13 ldr r2, [pc, #76] @ (80171dc ) 801718e: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000 8017192: 6013 str r3, [r2, #0] /* Start the timer that generates the tick ISR. Interrupts are disabled here already. */ vPortSetupTimerInterrupt(); 8017194: f000 f8da bl 801734c /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; 8017198: 4b11 ldr r3, [pc, #68] @ (80171e0 ) 801719a: 2200 movs r2, #0 801719c: 601a str r2, [r3, #0] /* Ensure the VFP is enabled - it should be anyway. */ vPortEnableVFP(); 801719e: f000 f8f9 bl 8017394 /* Lazy save always. */ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; 80171a2: 4b10 ldr r3, [pc, #64] @ (80171e4 ) 80171a4: 681b ldr r3, [r3, #0] 80171a6: 4a0f ldr r2, [pc, #60] @ (80171e4 ) 80171a8: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000 80171ac: 6013 str r3, [r2, #0] /* Start the first task. */ prvPortStartFirstTask(); 80171ae: f7ff ff63 bl 8017078 exit error function to prevent compiler warnings about a static function not being called in the case that the application writer overrides this functionality by defining configTASK_RETURN_ADDRESS. Call vTaskSwitchContext() so link time optimisation does not remove the symbol. */ vTaskSwitchContext(); 80171b2: f7fe fbd1 bl 8015958 prvTaskExitError(); 80171b6: f7ff ff1b bl 8016ff0 /* Should not get here! */ return 0; 80171ba: 2300 movs r3, #0 } 80171bc: 4618 mov r0, r3 80171be: 3718 adds r7, #24 80171c0: 46bd mov sp, r7 80171c2: bd80 pop {r7, pc} 80171c4: e000ed00 .word 0xe000ed00 80171c8: 410fc271 .word 0x410fc271 80171cc: 410fc270 .word 0x410fc270 80171d0: e000e400 .word 0xe000e400 80171d4: 24003180 .word 0x24003180 80171d8: 24003184 .word 0x24003184 80171dc: e000ed20 .word 0xe000ed20 80171e0: 24000044 .word 0x24000044 80171e4: e000ef34 .word 0xe000ef34 080171e8 : configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) { 80171e8: b480 push {r7} 80171ea: b083 sub sp, #12 80171ec: af00 add r7, sp, #0 __asm volatile 80171ee: f04f 0350 mov.w r3, #80 @ 0x50 80171f2: f383 8811 msr BASEPRI, r3 80171f6: f3bf 8f6f isb sy 80171fa: f3bf 8f4f dsb sy 80171fe: 607b str r3, [r7, #4] } 8017200: bf00 nop portDISABLE_INTERRUPTS(); uxCriticalNesting++; 8017202: 4b10 ldr r3, [pc, #64] @ (8017244 ) 8017204: 681b ldr r3, [r3, #0] 8017206: 3301 adds r3, #1 8017208: 4a0e ldr r2, [pc, #56] @ (8017244 ) 801720a: 6013 str r3, [r2, #0] /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if( uxCriticalNesting == 1 ) 801720c: 4b0d ldr r3, [pc, #52] @ (8017244 ) 801720e: 681b ldr r3, [r3, #0] 8017210: 2b01 cmp r3, #1 8017212: d110 bne.n 8017236 { configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); 8017214: 4b0c ldr r3, [pc, #48] @ (8017248 ) 8017216: 681b ldr r3, [r3, #0] 8017218: b2db uxtb r3, r3 801721a: 2b00 cmp r3, #0 801721c: d00b beq.n 8017236 __asm volatile 801721e: f04f 0350 mov.w r3, #80 @ 0x50 8017222: f383 8811 msr BASEPRI, r3 8017226: f3bf 8f6f isb sy 801722a: f3bf 8f4f dsb sy 801722e: 603b str r3, [r7, #0] } 8017230: bf00 nop 8017232: bf00 nop 8017234: e7fd b.n 8017232 } } 8017236: bf00 nop 8017238: 370c adds r7, #12 801723a: 46bd mov sp, r7 801723c: f85d 7b04 ldr.w r7, [sp], #4 8017240: 4770 bx lr 8017242: bf00 nop 8017244: 24000044 .word 0x24000044 8017248: e000ed04 .word 0xe000ed04 0801724c : /*-----------------------------------------------------------*/ void vPortExitCritical( void ) { 801724c: b480 push {r7} 801724e: b083 sub sp, #12 8017250: af00 add r7, sp, #0 configASSERT( uxCriticalNesting ); 8017252: 4b12 ldr r3, [pc, #72] @ (801729c ) 8017254: 681b ldr r3, [r3, #0] 8017256: 2b00 cmp r3, #0 8017258: d10b bne.n 8017272 __asm volatile 801725a: f04f 0350 mov.w r3, #80 @ 0x50 801725e: f383 8811 msr BASEPRI, r3 8017262: f3bf 8f6f isb sy 8017266: f3bf 8f4f dsb sy 801726a: 607b str r3, [r7, #4] } 801726c: bf00 nop 801726e: bf00 nop 8017270: e7fd b.n 801726e uxCriticalNesting--; 8017272: 4b0a ldr r3, [pc, #40] @ (801729c ) 8017274: 681b ldr r3, [r3, #0] 8017276: 3b01 subs r3, #1 8017278: 4a08 ldr r2, [pc, #32] @ (801729c ) 801727a: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) 801727c: 4b07 ldr r3, [pc, #28] @ (801729c ) 801727e: 681b ldr r3, [r3, #0] 8017280: 2b00 cmp r3, #0 8017282: d105 bne.n 8017290 8017284: 2300 movs r3, #0 8017286: 603b str r3, [r7, #0] __asm volatile 8017288: 683b ldr r3, [r7, #0] 801728a: f383 8811 msr BASEPRI, r3 } 801728e: bf00 nop { portENABLE_INTERRUPTS(); } } 8017290: bf00 nop 8017292: 370c adds r7, #12 8017294: 46bd mov sp, r7 8017296: f85d 7b04 ldr.w r7, [sp], #4 801729a: 4770 bx lr 801729c: 24000044 .word 0x24000044 080172a0 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile 80172a0: f3ef 8009 mrs r0, PSP 80172a4: f3bf 8f6f isb sy 80172a8: 4b15 ldr r3, [pc, #84] @ (8017300 ) 80172aa: 681a ldr r2, [r3, #0] 80172ac: f01e 0f10 tst.w lr, #16 80172b0: bf08 it eq 80172b2: ed20 8a10 vstmdbeq r0!, {s16-s31} 80172b6: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80172ba: 6010 str r0, [r2, #0] 80172bc: e92d 0009 stmdb sp!, {r0, r3} 80172c0: f04f 0050 mov.w r0, #80 @ 0x50 80172c4: f380 8811 msr BASEPRI, r0 80172c8: f3bf 8f4f dsb sy 80172cc: f3bf 8f6f isb sy 80172d0: f7fe fb42 bl 8015958 80172d4: f04f 0000 mov.w r0, #0 80172d8: f380 8811 msr BASEPRI, r0 80172dc: bc09 pop {r0, r3} 80172de: 6819 ldr r1, [r3, #0] 80172e0: 6808 ldr r0, [r1, #0] 80172e2: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80172e6: f01e 0f10 tst.w lr, #16 80172ea: bf08 it eq 80172ec: ecb0 8a10 vldmiaeq r0!, {s16-s31} 80172f0: f380 8809 msr PSP, r0 80172f4: f3bf 8f6f isb sy 80172f8: 4770 bx lr 80172fa: bf00 nop 80172fc: f3af 8000 nop.w 08017300 : 8017300: 24002b54 .word 0x24002b54 " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ); } 8017304: bf00 nop 8017306: bf00 nop 08017308 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { 8017308: b580 push {r7, lr} 801730a: b082 sub sp, #8 801730c: af00 add r7, sp, #0 __asm volatile 801730e: f04f 0350 mov.w r3, #80 @ 0x50 8017312: f383 8811 msr BASEPRI, r3 8017316: f3bf 8f6f isb sy 801731a: f3bf 8f4f dsb sy 801731e: 607b str r3, [r7, #4] } 8017320: bf00 nop save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) 8017322: f7fe fa5f bl 80157e4 8017326: 4603 mov r3, r0 8017328: 2b00 cmp r3, #0 801732a: d003 beq.n 8017334 { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; 801732c: 4b06 ldr r3, [pc, #24] @ (8017348 ) 801732e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8017332: 601a str r2, [r3, #0] 8017334: 2300 movs r3, #0 8017336: 603b str r3, [r7, #0] __asm volatile 8017338: 683b ldr r3, [r7, #0] 801733a: f383 8811 msr BASEPRI, r3 } 801733e: bf00 nop } } portENABLE_INTERRUPTS(); } 8017340: bf00 nop 8017342: 3708 adds r7, #8 8017344: 46bd mov sp, r7 8017346: bd80 pop {r7, pc} 8017348: e000ed04 .word 0xe000ed04 0801734c : /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) { 801734c: b480 push {r7} 801734e: af00 add r7, sp, #0 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and clear the SysTick. */ portNVIC_SYSTICK_CTRL_REG = 0UL; 8017350: 4b0b ldr r3, [pc, #44] @ (8017380 ) 8017352: 2200 movs r2, #0 8017354: 601a str r2, [r3, #0] portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; 8017356: 4b0b ldr r3, [pc, #44] @ (8017384 ) 8017358: 2200 movs r2, #0 801735a: 601a str r2, [r3, #0] /* Configure SysTick to interrupt at the requested rate. */ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; 801735c: 4b0a ldr r3, [pc, #40] @ (8017388 ) 801735e: 681b ldr r3, [r3, #0] 8017360: 4a0a ldr r2, [pc, #40] @ (801738c ) 8017362: fba2 2303 umull r2, r3, r2, r3 8017366: 099b lsrs r3, r3, #6 8017368: 4a09 ldr r2, [pc, #36] @ (8017390 ) 801736a: 3b01 subs r3, #1 801736c: 6013 str r3, [r2, #0] portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); 801736e: 4b04 ldr r3, [pc, #16] @ (8017380 ) 8017370: 2207 movs r2, #7 8017372: 601a str r2, [r3, #0] } 8017374: bf00 nop 8017376: 46bd mov sp, r7 8017378: f85d 7b04 ldr.w r7, [sp], #4 801737c: 4770 bx lr 801737e: bf00 nop 8017380: e000e010 .word 0xe000e010 8017384: e000e018 .word 0xe000e018 8017388: 24000034 .word 0x24000034 801738c: 10624dd3 .word 0x10624dd3 8017390: e000e014 .word 0xe000e014 08017394 : /*-----------------------------------------------------------*/ /* This is a naked function. */ static void vPortEnableVFP( void ) { __asm volatile 8017394: f8df 000c ldr.w r0, [pc, #12] @ 80173a4 8017398: 6801 ldr r1, [r0, #0] 801739a: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 801739e: 6001 str r1, [r0, #0] 80173a0: 4770 bx lr " \n" " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ " str r1, [r0] \n" " bx r14 " ); } 80173a2: bf00 nop 80173a4: e000ed88 .word 0xe000ed88 080173a8 : /*-----------------------------------------------------------*/ #if( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { 80173a8: b480 push {r7} 80173aa: b085 sub sp, #20 80173ac: af00 add r7, sp, #0 uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); 80173ae: f3ef 8305 mrs r3, IPSR 80173b2: 60fb str r3, [r7, #12] /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) 80173b4: 68fb ldr r3, [r7, #12] 80173b6: 2b0f cmp r3, #15 80173b8: d915 bls.n 80173e6 { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; 80173ba: 4a18 ldr r2, [pc, #96] @ (801741c ) 80173bc: 68fb ldr r3, [r7, #12] 80173be: 4413 add r3, r2 80173c0: 781b ldrb r3, [r3, #0] 80173c2: 72fb strb r3, [r7, #11] interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); 80173c4: 4b16 ldr r3, [pc, #88] @ (8017420 ) 80173c6: 781b ldrb r3, [r3, #0] 80173c8: 7afa ldrb r2, [r7, #11] 80173ca: 429a cmp r2, r3 80173cc: d20b bcs.n 80173e6 __asm volatile 80173ce: f04f 0350 mov.w r3, #80 @ 0x50 80173d2: f383 8811 msr BASEPRI, r3 80173d6: f3bf 8f6f isb sy 80173da: f3bf 8f4f dsb sy 80173de: 607b str r3, [r7, #4] } 80173e0: bf00 nop 80173e2: bf00 nop 80173e4: e7fd b.n 80173e2 configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); 80173e6: 4b0f ldr r3, [pc, #60] @ (8017424 ) 80173e8: 681b ldr r3, [r3, #0] 80173ea: f403 62e0 and.w r2, r3, #1792 @ 0x700 80173ee: 4b0e ldr r3, [pc, #56] @ (8017428 ) 80173f0: 681b ldr r3, [r3, #0] 80173f2: 429a cmp r2, r3 80173f4: d90b bls.n 801740e __asm volatile 80173f6: f04f 0350 mov.w r3, #80 @ 0x50 80173fa: f383 8811 msr BASEPRI, r3 80173fe: f3bf 8f6f isb sy 8017402: f3bf 8f4f dsb sy 8017406: 603b str r3, [r7, #0] } 8017408: bf00 nop 801740a: bf00 nop 801740c: e7fd b.n 801740a } 801740e: bf00 nop 8017410: 3714 adds r7, #20 8017412: 46bd mov sp, r7 8017414: f85d 7b04 ldr.w r7, [sp], #4 8017418: 4770 bx lr 801741a: bf00 nop 801741c: e000e3f0 .word 0xe000e3f0 8017420: 24003180 .word 0x24003180 8017424: e000ed0c .word 0xe000ed0c 8017428: 24003184 .word 0x24003184 0801742c : static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ void *pvPortMalloc( size_t xWantedSize ) { 801742c: b580 push {r7, lr} 801742e: b08a sub sp, #40 @ 0x28 8017430: af00 add r7, sp, #0 8017432: 6078 str r0, [r7, #4] BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; void *pvReturn = NULL; 8017434: 2300 movs r3, #0 8017436: 61fb str r3, [r7, #28] vTaskSuspendAll(); 8017438: f7fe f918 bl 801566c { /* If this is the first call to malloc then the heap will require initialisation to setup the list of free blocks. */ if( pxEnd == NULL ) 801743c: 4b5c ldr r3, [pc, #368] @ (80175b0 ) 801743e: 681b ldr r3, [r3, #0] 8017440: 2b00 cmp r3, #0 8017442: d101 bne.n 8017448 { prvHeapInit(); 8017444: f000 f924 bl 8017690 /* Check the requested block size is not so large that the top bit is set. The top bit of the block size member of the BlockLink_t structure is used to determine who owns the block - the application or the kernel, so it must be free. */ if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) 8017448: 4b5a ldr r3, [pc, #360] @ (80175b4 ) 801744a: 681a ldr r2, [r3, #0] 801744c: 687b ldr r3, [r7, #4] 801744e: 4013 ands r3, r2 8017450: 2b00 cmp r3, #0 8017452: f040 8095 bne.w 8017580 { /* The wanted size is increased so it can contain a BlockLink_t structure in addition to the requested amount of bytes. */ if( xWantedSize > 0 ) 8017456: 687b ldr r3, [r7, #4] 8017458: 2b00 cmp r3, #0 801745a: d01e beq.n 801749a { xWantedSize += xHeapStructSize; 801745c: 2208 movs r2, #8 801745e: 687b ldr r3, [r7, #4] 8017460: 4413 add r3, r2 8017462: 607b str r3, [r7, #4] /* Ensure that blocks are always aligned to the required number of bytes. */ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) 8017464: 687b ldr r3, [r7, #4] 8017466: f003 0307 and.w r3, r3, #7 801746a: 2b00 cmp r3, #0 801746c: d015 beq.n 801749a { /* Byte alignment required. */ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); 801746e: 687b ldr r3, [r7, #4] 8017470: f023 0307 bic.w r3, r3, #7 8017474: 3308 adds r3, #8 8017476: 607b str r3, [r7, #4] configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); 8017478: 687b ldr r3, [r7, #4] 801747a: f003 0307 and.w r3, r3, #7 801747e: 2b00 cmp r3, #0 8017480: d00b beq.n 801749a __asm volatile 8017482: f04f 0350 mov.w r3, #80 @ 0x50 8017486: f383 8811 msr BASEPRI, r3 801748a: f3bf 8f6f isb sy 801748e: f3bf 8f4f dsb sy 8017492: 617b str r3, [r7, #20] } 8017494: bf00 nop 8017496: bf00 nop 8017498: e7fd b.n 8017496 else { mtCOVERAGE_TEST_MARKER(); } if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) 801749a: 687b ldr r3, [r7, #4] 801749c: 2b00 cmp r3, #0 801749e: d06f beq.n 8017580 80174a0: 4b45 ldr r3, [pc, #276] @ (80175b8 ) 80174a2: 681b ldr r3, [r3, #0] 80174a4: 687a ldr r2, [r7, #4] 80174a6: 429a cmp r2, r3 80174a8: d86a bhi.n 8017580 { /* Traverse the list from the start (lowest address) block until one of adequate size is found. */ pxPreviousBlock = &xStart; 80174aa: 4b44 ldr r3, [pc, #272] @ (80175bc ) 80174ac: 623b str r3, [r7, #32] pxBlock = xStart.pxNextFreeBlock; 80174ae: 4b43 ldr r3, [pc, #268] @ (80175bc ) 80174b0: 681b ldr r3, [r3, #0] 80174b2: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 80174b4: e004 b.n 80174c0 { pxPreviousBlock = pxBlock; 80174b6: 6a7b ldr r3, [r7, #36] @ 0x24 80174b8: 623b str r3, [r7, #32] pxBlock = pxBlock->pxNextFreeBlock; 80174ba: 6a7b ldr r3, [r7, #36] @ 0x24 80174bc: 681b ldr r3, [r3, #0] 80174be: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 80174c0: 6a7b ldr r3, [r7, #36] @ 0x24 80174c2: 685b ldr r3, [r3, #4] 80174c4: 687a ldr r2, [r7, #4] 80174c6: 429a cmp r2, r3 80174c8: d903 bls.n 80174d2 80174ca: 6a7b ldr r3, [r7, #36] @ 0x24 80174cc: 681b ldr r3, [r3, #0] 80174ce: 2b00 cmp r3, #0 80174d0: d1f1 bne.n 80174b6 } /* If the end marker was reached then a block of adequate size was not found. */ if( pxBlock != pxEnd ) 80174d2: 4b37 ldr r3, [pc, #220] @ (80175b0 ) 80174d4: 681b ldr r3, [r3, #0] 80174d6: 6a7a ldr r2, [r7, #36] @ 0x24 80174d8: 429a cmp r2, r3 80174da: d051 beq.n 8017580 { /* Return the memory space pointed to - jumping over the BlockLink_t structure at its start. */ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); 80174dc: 6a3b ldr r3, [r7, #32] 80174de: 681b ldr r3, [r3, #0] 80174e0: 2208 movs r2, #8 80174e2: 4413 add r3, r2 80174e4: 61fb str r3, [r7, #28] /* This block is being returned for use so must be taken out of the list of free blocks. */ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; 80174e6: 6a7b ldr r3, [r7, #36] @ 0x24 80174e8: 681a ldr r2, [r3, #0] 80174ea: 6a3b ldr r3, [r7, #32] 80174ec: 601a str r2, [r3, #0] /* If the block is larger than required it can be split into two. */ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) 80174ee: 6a7b ldr r3, [r7, #36] @ 0x24 80174f0: 685a ldr r2, [r3, #4] 80174f2: 687b ldr r3, [r7, #4] 80174f4: 1ad2 subs r2, r2, r3 80174f6: 2308 movs r3, #8 80174f8: 005b lsls r3, r3, #1 80174fa: 429a cmp r2, r3 80174fc: d920 bls.n 8017540 { /* This block is to be split into two. Create a new block following the number of bytes requested. The void cast is used to prevent byte alignment warnings from the compiler. */ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); 80174fe: 6a7a ldr r2, [r7, #36] @ 0x24 8017500: 687b ldr r3, [r7, #4] 8017502: 4413 add r3, r2 8017504: 61bb str r3, [r7, #24] configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); 8017506: 69bb ldr r3, [r7, #24] 8017508: f003 0307 and.w r3, r3, #7 801750c: 2b00 cmp r3, #0 801750e: d00b beq.n 8017528 __asm volatile 8017510: f04f 0350 mov.w r3, #80 @ 0x50 8017514: f383 8811 msr BASEPRI, r3 8017518: f3bf 8f6f isb sy 801751c: f3bf 8f4f dsb sy 8017520: 613b str r3, [r7, #16] } 8017522: bf00 nop 8017524: bf00 nop 8017526: e7fd b.n 8017524 /* Calculate the sizes of two blocks split from the single block. */ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; 8017528: 6a7b ldr r3, [r7, #36] @ 0x24 801752a: 685a ldr r2, [r3, #4] 801752c: 687b ldr r3, [r7, #4] 801752e: 1ad2 subs r2, r2, r3 8017530: 69bb ldr r3, [r7, #24] 8017532: 605a str r2, [r3, #4] pxBlock->xBlockSize = xWantedSize; 8017534: 6a7b ldr r3, [r7, #36] @ 0x24 8017536: 687a ldr r2, [r7, #4] 8017538: 605a str r2, [r3, #4] /* Insert the new block into the list of free blocks. */ prvInsertBlockIntoFreeList( pxNewBlockLink ); 801753a: 69b8 ldr r0, [r7, #24] 801753c: f000 f90a bl 8017754 else { mtCOVERAGE_TEST_MARKER(); } xFreeBytesRemaining -= pxBlock->xBlockSize; 8017540: 4b1d ldr r3, [pc, #116] @ (80175b8 ) 8017542: 681a ldr r2, [r3, #0] 8017544: 6a7b ldr r3, [r7, #36] @ 0x24 8017546: 685b ldr r3, [r3, #4] 8017548: 1ad3 subs r3, r2, r3 801754a: 4a1b ldr r2, [pc, #108] @ (80175b8 ) 801754c: 6013 str r3, [r2, #0] if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) 801754e: 4b1a ldr r3, [pc, #104] @ (80175b8 ) 8017550: 681a ldr r2, [r3, #0] 8017552: 4b1b ldr r3, [pc, #108] @ (80175c0 ) 8017554: 681b ldr r3, [r3, #0] 8017556: 429a cmp r2, r3 8017558: d203 bcs.n 8017562 { xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; 801755a: 4b17 ldr r3, [pc, #92] @ (80175b8 ) 801755c: 681b ldr r3, [r3, #0] 801755e: 4a18 ldr r2, [pc, #96] @ (80175c0 ) 8017560: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } /* The block is being returned - it is allocated and owned by the application and has no "next" block. */ pxBlock->xBlockSize |= xBlockAllocatedBit; 8017562: 6a7b ldr r3, [r7, #36] @ 0x24 8017564: 685a ldr r2, [r3, #4] 8017566: 4b13 ldr r3, [pc, #76] @ (80175b4 ) 8017568: 681b ldr r3, [r3, #0] 801756a: 431a orrs r2, r3 801756c: 6a7b ldr r3, [r7, #36] @ 0x24 801756e: 605a str r2, [r3, #4] pxBlock->pxNextFreeBlock = NULL; 8017570: 6a7b ldr r3, [r7, #36] @ 0x24 8017572: 2200 movs r2, #0 8017574: 601a str r2, [r3, #0] xNumberOfSuccessfulAllocations++; 8017576: 4b13 ldr r3, [pc, #76] @ (80175c4 ) 8017578: 681b ldr r3, [r3, #0] 801757a: 3301 adds r3, #1 801757c: 4a11 ldr r2, [pc, #68] @ (80175c4 ) 801757e: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } traceMALLOC( pvReturn, xWantedSize ); } ( void ) xTaskResumeAll(); 8017580: f7fe f882 bl 8015688 mtCOVERAGE_TEST_MARKER(); } } #endif configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); 8017584: 69fb ldr r3, [r7, #28] 8017586: f003 0307 and.w r3, r3, #7 801758a: 2b00 cmp r3, #0 801758c: d00b beq.n 80175a6 __asm volatile 801758e: f04f 0350 mov.w r3, #80 @ 0x50 8017592: f383 8811 msr BASEPRI, r3 8017596: f3bf 8f6f isb sy 801759a: f3bf 8f4f dsb sy 801759e: 60fb str r3, [r7, #12] } 80175a0: bf00 nop 80175a2: bf00 nop 80175a4: e7fd b.n 80175a2 return pvReturn; 80175a6: 69fb ldr r3, [r7, #28] } 80175a8: 4618 mov r0, r3 80175aa: 3728 adds r7, #40 @ 0x28 80175ac: 46bd mov sp, r7 80175ae: bd80 pop {r7, pc} 80175b0: 24013190 .word 0x24013190 80175b4: 240131a4 .word 0x240131a4 80175b8: 24013194 .word 0x24013194 80175bc: 24013188 .word 0x24013188 80175c0: 24013198 .word 0x24013198 80175c4: 2401319c .word 0x2401319c 080175c8 : /*-----------------------------------------------------------*/ void vPortFree( void *pv ) { 80175c8: b580 push {r7, lr} 80175ca: b086 sub sp, #24 80175cc: af00 add r7, sp, #0 80175ce: 6078 str r0, [r7, #4] uint8_t *puc = ( uint8_t * ) pv; 80175d0: 687b ldr r3, [r7, #4] 80175d2: 617b str r3, [r7, #20] BlockLink_t *pxLink; if( pv != NULL ) 80175d4: 687b ldr r3, [r7, #4] 80175d6: 2b00 cmp r3, #0 80175d8: d04f beq.n 801767a { /* The memory being freed will have an BlockLink_t structure immediately before it. */ puc -= xHeapStructSize; 80175da: 2308 movs r3, #8 80175dc: 425b negs r3, r3 80175de: 697a ldr r2, [r7, #20] 80175e0: 4413 add r3, r2 80175e2: 617b str r3, [r7, #20] /* This casting is to keep the compiler from issuing warnings. */ pxLink = ( void * ) puc; 80175e4: 697b ldr r3, [r7, #20] 80175e6: 613b str r3, [r7, #16] /* Check the block is actually allocated. */ configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); 80175e8: 693b ldr r3, [r7, #16] 80175ea: 685a ldr r2, [r3, #4] 80175ec: 4b25 ldr r3, [pc, #148] @ (8017684 ) 80175ee: 681b ldr r3, [r3, #0] 80175f0: 4013 ands r3, r2 80175f2: 2b00 cmp r3, #0 80175f4: d10b bne.n 801760e __asm volatile 80175f6: f04f 0350 mov.w r3, #80 @ 0x50 80175fa: f383 8811 msr BASEPRI, r3 80175fe: f3bf 8f6f isb sy 8017602: f3bf 8f4f dsb sy 8017606: 60fb str r3, [r7, #12] } 8017608: bf00 nop 801760a: bf00 nop 801760c: e7fd b.n 801760a configASSERT( pxLink->pxNextFreeBlock == NULL ); 801760e: 693b ldr r3, [r7, #16] 8017610: 681b ldr r3, [r3, #0] 8017612: 2b00 cmp r3, #0 8017614: d00b beq.n 801762e __asm volatile 8017616: f04f 0350 mov.w r3, #80 @ 0x50 801761a: f383 8811 msr BASEPRI, r3 801761e: f3bf 8f6f isb sy 8017622: f3bf 8f4f dsb sy 8017626: 60bb str r3, [r7, #8] } 8017628: bf00 nop 801762a: bf00 nop 801762c: e7fd b.n 801762a if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) 801762e: 693b ldr r3, [r7, #16] 8017630: 685a ldr r2, [r3, #4] 8017632: 4b14 ldr r3, [pc, #80] @ (8017684 ) 8017634: 681b ldr r3, [r3, #0] 8017636: 4013 ands r3, r2 8017638: 2b00 cmp r3, #0 801763a: d01e beq.n 801767a { if( pxLink->pxNextFreeBlock == NULL ) 801763c: 693b ldr r3, [r7, #16] 801763e: 681b ldr r3, [r3, #0] 8017640: 2b00 cmp r3, #0 8017642: d11a bne.n 801767a { /* The block is being returned to the heap - it is no longer allocated. */ pxLink->xBlockSize &= ~xBlockAllocatedBit; 8017644: 693b ldr r3, [r7, #16] 8017646: 685a ldr r2, [r3, #4] 8017648: 4b0e ldr r3, [pc, #56] @ (8017684 ) 801764a: 681b ldr r3, [r3, #0] 801764c: 43db mvns r3, r3 801764e: 401a ands r2, r3 8017650: 693b ldr r3, [r7, #16] 8017652: 605a str r2, [r3, #4] vTaskSuspendAll(); 8017654: f7fe f80a bl 801566c { /* Add this block to the list of free blocks. */ xFreeBytesRemaining += pxLink->xBlockSize; 8017658: 693b ldr r3, [r7, #16] 801765a: 685a ldr r2, [r3, #4] 801765c: 4b0a ldr r3, [pc, #40] @ (8017688 ) 801765e: 681b ldr r3, [r3, #0] 8017660: 4413 add r3, r2 8017662: 4a09 ldr r2, [pc, #36] @ (8017688 ) 8017664: 6013 str r3, [r2, #0] traceFREE( pv, pxLink->xBlockSize ); prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); 8017666: 6938 ldr r0, [r7, #16] 8017668: f000 f874 bl 8017754 xNumberOfSuccessfulFrees++; 801766c: 4b07 ldr r3, [pc, #28] @ (801768c ) 801766e: 681b ldr r3, [r3, #0] 8017670: 3301 adds r3, #1 8017672: 4a06 ldr r2, [pc, #24] @ (801768c ) 8017674: 6013 str r3, [r2, #0] } ( void ) xTaskResumeAll(); 8017676: f7fe f807 bl 8015688 else { mtCOVERAGE_TEST_MARKER(); } } } 801767a: bf00 nop 801767c: 3718 adds r7, #24 801767e: 46bd mov sp, r7 8017680: bd80 pop {r7, pc} 8017682: bf00 nop 8017684: 240131a4 .word 0x240131a4 8017688: 24013194 .word 0x24013194 801768c: 240131a0 .word 0x240131a0 08017690 : /* This just exists to keep the linker quiet. */ } /*-----------------------------------------------------------*/ static void prvHeapInit( void ) { 8017690: b480 push {r7} 8017692: b085 sub sp, #20 8017694: af00 add r7, sp, #0 BlockLink_t *pxFirstFreeBlock; uint8_t *pucAlignedHeap; size_t uxAddress; size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; 8017696: f44f 3380 mov.w r3, #65536 @ 0x10000 801769a: 60bb str r3, [r7, #8] /* Ensure the heap starts on a correctly aligned boundary. */ uxAddress = ( size_t ) ucHeap; 801769c: 4b27 ldr r3, [pc, #156] @ (801773c ) 801769e: 60fb str r3, [r7, #12] if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) 80176a0: 68fb ldr r3, [r7, #12] 80176a2: f003 0307 and.w r3, r3, #7 80176a6: 2b00 cmp r3, #0 80176a8: d00c beq.n 80176c4 { uxAddress += ( portBYTE_ALIGNMENT - 1 ); 80176aa: 68fb ldr r3, [r7, #12] 80176ac: 3307 adds r3, #7 80176ae: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 80176b0: 68fb ldr r3, [r7, #12] 80176b2: f023 0307 bic.w r3, r3, #7 80176b6: 60fb str r3, [r7, #12] xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; 80176b8: 68ba ldr r2, [r7, #8] 80176ba: 68fb ldr r3, [r7, #12] 80176bc: 1ad3 subs r3, r2, r3 80176be: 4a1f ldr r2, [pc, #124] @ (801773c ) 80176c0: 4413 add r3, r2 80176c2: 60bb str r3, [r7, #8] } pucAlignedHeap = ( uint8_t * ) uxAddress; 80176c4: 68fb ldr r3, [r7, #12] 80176c6: 607b str r3, [r7, #4] /* xStart is used to hold a pointer to the first item in the list of free blocks. The void cast is used to prevent compiler warnings. */ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; 80176c8: 4a1d ldr r2, [pc, #116] @ (8017740 ) 80176ca: 687b ldr r3, [r7, #4] 80176cc: 6013 str r3, [r2, #0] xStart.xBlockSize = ( size_t ) 0; 80176ce: 4b1c ldr r3, [pc, #112] @ (8017740 ) 80176d0: 2200 movs r2, #0 80176d2: 605a str r2, [r3, #4] /* pxEnd is used to mark the end of the list of free blocks and is inserted at the end of the heap space. */ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; 80176d4: 687b ldr r3, [r7, #4] 80176d6: 68ba ldr r2, [r7, #8] 80176d8: 4413 add r3, r2 80176da: 60fb str r3, [r7, #12] uxAddress -= xHeapStructSize; 80176dc: 2208 movs r2, #8 80176de: 68fb ldr r3, [r7, #12] 80176e0: 1a9b subs r3, r3, r2 80176e2: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 80176e4: 68fb ldr r3, [r7, #12] 80176e6: f023 0307 bic.w r3, r3, #7 80176ea: 60fb str r3, [r7, #12] pxEnd = ( void * ) uxAddress; 80176ec: 68fb ldr r3, [r7, #12] 80176ee: 4a15 ldr r2, [pc, #84] @ (8017744 ) 80176f0: 6013 str r3, [r2, #0] pxEnd->xBlockSize = 0; 80176f2: 4b14 ldr r3, [pc, #80] @ (8017744 ) 80176f4: 681b ldr r3, [r3, #0] 80176f6: 2200 movs r2, #0 80176f8: 605a str r2, [r3, #4] pxEnd->pxNextFreeBlock = NULL; 80176fa: 4b12 ldr r3, [pc, #72] @ (8017744 ) 80176fc: 681b ldr r3, [r3, #0] 80176fe: 2200 movs r2, #0 8017700: 601a str r2, [r3, #0] /* To start with there is a single free block that is sized to take up the entire heap space, minus the space taken by pxEnd. */ pxFirstFreeBlock = ( void * ) pucAlignedHeap; 8017702: 687b ldr r3, [r7, #4] 8017704: 603b str r3, [r7, #0] pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; 8017706: 683b ldr r3, [r7, #0] 8017708: 68fa ldr r2, [r7, #12] 801770a: 1ad2 subs r2, r2, r3 801770c: 683b ldr r3, [r7, #0] 801770e: 605a str r2, [r3, #4] pxFirstFreeBlock->pxNextFreeBlock = pxEnd; 8017710: 4b0c ldr r3, [pc, #48] @ (8017744 ) 8017712: 681a ldr r2, [r3, #0] 8017714: 683b ldr r3, [r7, #0] 8017716: 601a str r2, [r3, #0] /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8017718: 683b ldr r3, [r7, #0] 801771a: 685b ldr r3, [r3, #4] 801771c: 4a0a ldr r2, [pc, #40] @ (8017748 ) 801771e: 6013 str r3, [r2, #0] xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8017720: 683b ldr r3, [r7, #0] 8017722: 685b ldr r3, [r3, #4] 8017724: 4a09 ldr r2, [pc, #36] @ (801774c ) 8017726: 6013 str r3, [r2, #0] /* Work out the position of the top bit in a size_t variable. */ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); 8017728: 4b09 ldr r3, [pc, #36] @ (8017750 ) 801772a: f04f 4200 mov.w r2, #2147483648 @ 0x80000000 801772e: 601a str r2, [r3, #0] } 8017730: bf00 nop 8017732: 3714 adds r7, #20 8017734: 46bd mov sp, r7 8017736: f85d 7b04 ldr.w r7, [sp], #4 801773a: 4770 bx lr 801773c: 24003188 .word 0x24003188 8017740: 24013188 .word 0x24013188 8017744: 24013190 .word 0x24013190 8017748: 24013198 .word 0x24013198 801774c: 24013194 .word 0x24013194 8017750: 240131a4 .word 0x240131a4 08017754 : /*-----------------------------------------------------------*/ static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) { 8017754: b480 push {r7} 8017756: b085 sub sp, #20 8017758: af00 add r7, sp, #0 801775a: 6078 str r0, [r7, #4] BlockLink_t *pxIterator; uint8_t *puc; /* Iterate through the list until a block is found that has a higher address than the block being inserted. */ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) 801775c: 4b28 ldr r3, [pc, #160] @ (8017800 ) 801775e: 60fb str r3, [r7, #12] 8017760: e002 b.n 8017768 8017762: 68fb ldr r3, [r7, #12] 8017764: 681b ldr r3, [r3, #0] 8017766: 60fb str r3, [r7, #12] 8017768: 68fb ldr r3, [r7, #12] 801776a: 681b ldr r3, [r3, #0] 801776c: 687a ldr r2, [r7, #4] 801776e: 429a cmp r2, r3 8017770: d8f7 bhi.n 8017762 /* Nothing to do here, just iterate to the right position. */ } /* Do the block being inserted, and the block it is being inserted after make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; 8017772: 68fb ldr r3, [r7, #12] 8017774: 60bb str r3, [r7, #8] if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) 8017776: 68fb ldr r3, [r7, #12] 8017778: 685b ldr r3, [r3, #4] 801777a: 68ba ldr r2, [r7, #8] 801777c: 4413 add r3, r2 801777e: 687a ldr r2, [r7, #4] 8017780: 429a cmp r2, r3 8017782: d108 bne.n 8017796 { pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 8017784: 68fb ldr r3, [r7, #12] 8017786: 685a ldr r2, [r3, #4] 8017788: 687b ldr r3, [r7, #4] 801778a: 685b ldr r3, [r3, #4] 801778c: 441a add r2, r3 801778e: 68fb ldr r3, [r7, #12] 8017790: 605a str r2, [r3, #4] pxBlockToInsert = pxIterator; 8017792: 68fb ldr r3, [r7, #12] 8017794: 607b str r3, [r7, #4] mtCOVERAGE_TEST_MARKER(); } /* Do the block being inserted, and the block it is being inserted before make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; 8017796: 687b ldr r3, [r7, #4] 8017798: 60bb str r3, [r7, #8] if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 801779a: 687b ldr r3, [r7, #4] 801779c: 685b ldr r3, [r3, #4] 801779e: 68ba ldr r2, [r7, #8] 80177a0: 441a add r2, r3 80177a2: 68fb ldr r3, [r7, #12] 80177a4: 681b ldr r3, [r3, #0] 80177a6: 429a cmp r2, r3 80177a8: d118 bne.n 80177dc { if( pxIterator->pxNextFreeBlock != pxEnd ) 80177aa: 68fb ldr r3, [r7, #12] 80177ac: 681a ldr r2, [r3, #0] 80177ae: 4b15 ldr r3, [pc, #84] @ (8017804 ) 80177b0: 681b ldr r3, [r3, #0] 80177b2: 429a cmp r2, r3 80177b4: d00d beq.n 80177d2 { /* Form one big block from the two blocks. */ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; 80177b6: 687b ldr r3, [r7, #4] 80177b8: 685a ldr r2, [r3, #4] 80177ba: 68fb ldr r3, [r7, #12] 80177bc: 681b ldr r3, [r3, #0] 80177be: 685b ldr r3, [r3, #4] 80177c0: 441a add r2, r3 80177c2: 687b ldr r3, [r7, #4] 80177c4: 605a str r2, [r3, #4] pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; 80177c6: 68fb ldr r3, [r7, #12] 80177c8: 681b ldr r3, [r3, #0] 80177ca: 681a ldr r2, [r3, #0] 80177cc: 687b ldr r3, [r7, #4] 80177ce: 601a str r2, [r3, #0] 80177d0: e008 b.n 80177e4 } else { pxBlockToInsert->pxNextFreeBlock = pxEnd; 80177d2: 4b0c ldr r3, [pc, #48] @ (8017804 ) 80177d4: 681a ldr r2, [r3, #0] 80177d6: 687b ldr r3, [r7, #4] 80177d8: 601a str r2, [r3, #0] 80177da: e003 b.n 80177e4 } } else { pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; 80177dc: 68fb ldr r3, [r7, #12] 80177de: 681a ldr r2, [r3, #0] 80177e0: 687b ldr r3, [r7, #4] 80177e2: 601a str r2, [r3, #0] /* If the block being inserted plugged a gab, so was merged with the block before and the block after, then it's pxNextFreeBlock pointer will have already been set, and should not be set here as that would make it point to itself. */ if( pxIterator != pxBlockToInsert ) 80177e4: 68fa ldr r2, [r7, #12] 80177e6: 687b ldr r3, [r7, #4] 80177e8: 429a cmp r2, r3 80177ea: d002 beq.n 80177f2 { pxIterator->pxNextFreeBlock = pxBlockToInsert; 80177ec: 68fb ldr r3, [r7, #12] 80177ee: 687a ldr r2, [r7, #4] 80177f0: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 80177f2: bf00 nop 80177f4: 3714 adds r7, #20 80177f6: 46bd mov sp, r7 80177f8: f85d 7b04 ldr.w r7, [sp], #4 80177fc: 4770 bx lr 80177fe: bf00 nop 8017800: 24013188 .word 0x24013188 8017804: 24013190 .word 0x24013190 08017808 <__cvt>: 8017808: b5f0 push {r4, r5, r6, r7, lr} 801780a: ed2d 8b02 vpush {d8} 801780e: eeb0 8b40 vmov.f64 d8, d0 8017812: b085 sub sp, #20 8017814: 4617 mov r7, r2 8017816: 9d0d ldr r5, [sp, #52] @ 0x34 8017818: 9e0c ldr r6, [sp, #48] @ 0x30 801781a: ee18 2a90 vmov r2, s17 801781e: f025 0520 bic.w r5, r5, #32 8017822: 2a00 cmp r2, #0 8017824: bfb6 itet lt 8017826: 222d movlt r2, #45 @ 0x2d 8017828: 2200 movge r2, #0 801782a: eeb1 8b40 vneglt.f64 d8, d0 801782e: 2d46 cmp r5, #70 @ 0x46 8017830: 460c mov r4, r1 8017832: 701a strb r2, [r3, #0] 8017834: d004 beq.n 8017840 <__cvt+0x38> 8017836: 2d45 cmp r5, #69 @ 0x45 8017838: d100 bne.n 801783c <__cvt+0x34> 801783a: 3401 adds r4, #1 801783c: 2102 movs r1, #2 801783e: e000 b.n 8017842 <__cvt+0x3a> 8017840: 2103 movs r1, #3 8017842: ab03 add r3, sp, #12 8017844: 9301 str r3, [sp, #4] 8017846: ab02 add r3, sp, #8 8017848: 9300 str r3, [sp, #0] 801784a: 4622 mov r2, r4 801784c: 4633 mov r3, r6 801784e: eeb0 0b48 vmov.f64 d0, d8 8017852: f000 ff75 bl 8018740 <_dtoa_r> 8017856: 2d47 cmp r5, #71 @ 0x47 8017858: d114 bne.n 8017884 <__cvt+0x7c> 801785a: 07fb lsls r3, r7, #31 801785c: d50a bpl.n 8017874 <__cvt+0x6c> 801785e: 1902 adds r2, r0, r4 8017860: eeb5 8b40 vcmp.f64 d8, #0.0 8017864: eef1 fa10 vmrs APSR_nzcv, fpscr 8017868: bf08 it eq 801786a: 9203 streq r2, [sp, #12] 801786c: 2130 movs r1, #48 @ 0x30 801786e: 9b03 ldr r3, [sp, #12] 8017870: 4293 cmp r3, r2 8017872: d319 bcc.n 80178a8 <__cvt+0xa0> 8017874: 9b03 ldr r3, [sp, #12] 8017876: 9a0e ldr r2, [sp, #56] @ 0x38 8017878: 1a1b subs r3, r3, r0 801787a: 6013 str r3, [r2, #0] 801787c: b005 add sp, #20 801787e: ecbd 8b02 vpop {d8} 8017882: bdf0 pop {r4, r5, r6, r7, pc} 8017884: 2d46 cmp r5, #70 @ 0x46 8017886: eb00 0204 add.w r2, r0, r4 801788a: d1e9 bne.n 8017860 <__cvt+0x58> 801788c: 7803 ldrb r3, [r0, #0] 801788e: 2b30 cmp r3, #48 @ 0x30 8017890: d107 bne.n 80178a2 <__cvt+0x9a> 8017892: eeb5 8b40 vcmp.f64 d8, #0.0 8017896: eef1 fa10 vmrs APSR_nzcv, fpscr 801789a: bf1c itt ne 801789c: f1c4 0401 rsbne r4, r4, #1 80178a0: 6034 strne r4, [r6, #0] 80178a2: 6833 ldr r3, [r6, #0] 80178a4: 441a add r2, r3 80178a6: e7db b.n 8017860 <__cvt+0x58> 80178a8: 1c5c adds r4, r3, #1 80178aa: 9403 str r4, [sp, #12] 80178ac: 7019 strb r1, [r3, #0] 80178ae: e7de b.n 801786e <__cvt+0x66> 080178b0 <__exponent>: 80178b0: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 80178b2: 2900 cmp r1, #0 80178b4: bfba itte lt 80178b6: 4249 neglt r1, r1 80178b8: 232d movlt r3, #45 @ 0x2d 80178ba: 232b movge r3, #43 @ 0x2b 80178bc: 2909 cmp r1, #9 80178be: 7002 strb r2, [r0, #0] 80178c0: 7043 strb r3, [r0, #1] 80178c2: dd29 ble.n 8017918 <__exponent+0x68> 80178c4: f10d 0307 add.w r3, sp, #7 80178c8: 461d mov r5, r3 80178ca: 270a movs r7, #10 80178cc: 461a mov r2, r3 80178ce: fbb1 f6f7 udiv r6, r1, r7 80178d2: fb07 1416 mls r4, r7, r6, r1 80178d6: 3430 adds r4, #48 @ 0x30 80178d8: f802 4c01 strb.w r4, [r2, #-1] 80178dc: 460c mov r4, r1 80178de: 2c63 cmp r4, #99 @ 0x63 80178e0: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff 80178e4: 4631 mov r1, r6 80178e6: dcf1 bgt.n 80178cc <__exponent+0x1c> 80178e8: 3130 adds r1, #48 @ 0x30 80178ea: 1e94 subs r4, r2, #2 80178ec: f803 1c01 strb.w r1, [r3, #-1] 80178f0: 1c41 adds r1, r0, #1 80178f2: 4623 mov r3, r4 80178f4: 42ab cmp r3, r5 80178f6: d30a bcc.n 801790e <__exponent+0x5e> 80178f8: f10d 0309 add.w r3, sp, #9 80178fc: 1a9b subs r3, r3, r2 80178fe: 42ac cmp r4, r5 8017900: bf88 it hi 8017902: 2300 movhi r3, #0 8017904: 3302 adds r3, #2 8017906: 4403 add r3, r0 8017908: 1a18 subs r0, r3, r0 801790a: b003 add sp, #12 801790c: bdf0 pop {r4, r5, r6, r7, pc} 801790e: f813 6b01 ldrb.w r6, [r3], #1 8017912: f801 6f01 strb.w r6, [r1, #1]! 8017916: e7ed b.n 80178f4 <__exponent+0x44> 8017918: 2330 movs r3, #48 @ 0x30 801791a: 3130 adds r1, #48 @ 0x30 801791c: 7083 strb r3, [r0, #2] 801791e: 70c1 strb r1, [r0, #3] 8017920: 1d03 adds r3, r0, #4 8017922: e7f1 b.n 8017908 <__exponent+0x58> 8017924: 0000 movs r0, r0 ... 08017928 <_printf_float>: 8017928: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801792c: b08d sub sp, #52 @ 0x34 801792e: 460c mov r4, r1 8017930: f8dd 8058 ldr.w r8, [sp, #88] @ 0x58 8017934: 4616 mov r6, r2 8017936: 461f mov r7, r3 8017938: 4605 mov r5, r0 801793a: f000 fd9d bl 8018478 <_localeconv_r> 801793e: f8d0 b000 ldr.w fp, [r0] 8017942: 4658 mov r0, fp 8017944: f7e8 fd1c bl 8000380 8017948: 2300 movs r3, #0 801794a: 930a str r3, [sp, #40] @ 0x28 801794c: f8d8 3000 ldr.w r3, [r8] 8017950: f894 9018 ldrb.w r9, [r4, #24] 8017954: 6822 ldr r2, [r4, #0] 8017956: 9005 str r0, [sp, #20] 8017958: 3307 adds r3, #7 801795a: f023 0307 bic.w r3, r3, #7 801795e: f103 0108 add.w r1, r3, #8 8017962: f8c8 1000 str.w r1, [r8] 8017966: ed93 0b00 vldr d0, [r3] 801796a: ed9f 6b97 vldr d6, [pc, #604] @ 8017bc8 <_printf_float+0x2a0> 801796e: eeb0 7bc0 vabs.f64 d7, d0 8017972: eeb4 7b46 vcmp.f64 d7, d6 8017976: eef1 fa10 vmrs APSR_nzcv, fpscr 801797a: ed84 0b12 vstr d0, [r4, #72] @ 0x48 801797e: dd24 ble.n 80179ca <_printf_float+0xa2> 8017980: eeb5 0bc0 vcmpe.f64 d0, #0.0 8017984: eef1 fa10 vmrs APSR_nzcv, fpscr 8017988: d502 bpl.n 8017990 <_printf_float+0x68> 801798a: 232d movs r3, #45 @ 0x2d 801798c: f884 3043 strb.w r3, [r4, #67] @ 0x43 8017990: 498f ldr r1, [pc, #572] @ (8017bd0 <_printf_float+0x2a8>) 8017992: 4b90 ldr r3, [pc, #576] @ (8017bd4 <_printf_float+0x2ac>) 8017994: f1b9 0f47 cmp.w r9, #71 @ 0x47 8017998: bf94 ite ls 801799a: 4688 movls r8, r1 801799c: 4698 movhi r8, r3 801799e: f022 0204 bic.w r2, r2, #4 80179a2: 2303 movs r3, #3 80179a4: 6123 str r3, [r4, #16] 80179a6: 6022 str r2, [r4, #0] 80179a8: f04f 0a00 mov.w sl, #0 80179ac: 9700 str r7, [sp, #0] 80179ae: 4633 mov r3, r6 80179b0: aa0b add r2, sp, #44 @ 0x2c 80179b2: 4621 mov r1, r4 80179b4: 4628 mov r0, r5 80179b6: f000 f9d1 bl 8017d5c <_printf_common> 80179ba: 3001 adds r0, #1 80179bc: f040 8089 bne.w 8017ad2 <_printf_float+0x1aa> 80179c0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80179c4: b00d add sp, #52 @ 0x34 80179c6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80179ca: eeb4 0b40 vcmp.f64 d0, d0 80179ce: eef1 fa10 vmrs APSR_nzcv, fpscr 80179d2: d709 bvc.n 80179e8 <_printf_float+0xc0> 80179d4: ee10 3a90 vmov r3, s1 80179d8: 2b00 cmp r3, #0 80179da: bfbc itt lt 80179dc: 232d movlt r3, #45 @ 0x2d 80179de: f884 3043 strblt.w r3, [r4, #67] @ 0x43 80179e2: 497d ldr r1, [pc, #500] @ (8017bd8 <_printf_float+0x2b0>) 80179e4: 4b7d ldr r3, [pc, #500] @ (8017bdc <_printf_float+0x2b4>) 80179e6: e7d5 b.n 8017994 <_printf_float+0x6c> 80179e8: 6863 ldr r3, [r4, #4] 80179ea: 1c59 adds r1, r3, #1 80179ec: f009 0adf and.w sl, r9, #223 @ 0xdf 80179f0: d139 bne.n 8017a66 <_printf_float+0x13e> 80179f2: 2306 movs r3, #6 80179f4: 6063 str r3, [r4, #4] 80179f6: f442 6280 orr.w r2, r2, #1024 @ 0x400 80179fa: 2300 movs r3, #0 80179fc: 6022 str r2, [r4, #0] 80179fe: 9303 str r3, [sp, #12] 8017a00: ab0a add r3, sp, #40 @ 0x28 8017a02: e9cd 9301 strd r9, r3, [sp, #4] 8017a06: ab09 add r3, sp, #36 @ 0x24 8017a08: 9300 str r3, [sp, #0] 8017a0a: 6861 ldr r1, [r4, #4] 8017a0c: f10d 0323 add.w r3, sp, #35 @ 0x23 8017a10: 4628 mov r0, r5 8017a12: f7ff fef9 bl 8017808 <__cvt> 8017a16: f1ba 0f47 cmp.w sl, #71 @ 0x47 8017a1a: 9909 ldr r1, [sp, #36] @ 0x24 8017a1c: 4680 mov r8, r0 8017a1e: d129 bne.n 8017a74 <_printf_float+0x14c> 8017a20: 1cc8 adds r0, r1, #3 8017a22: db02 blt.n 8017a2a <_printf_float+0x102> 8017a24: 6863 ldr r3, [r4, #4] 8017a26: 4299 cmp r1, r3 8017a28: dd41 ble.n 8017aae <_printf_float+0x186> 8017a2a: f1a9 0902 sub.w r9, r9, #2 8017a2e: fa5f f989 uxtb.w r9, r9 8017a32: 3901 subs r1, #1 8017a34: 464a mov r2, r9 8017a36: f104 0050 add.w r0, r4, #80 @ 0x50 8017a3a: 9109 str r1, [sp, #36] @ 0x24 8017a3c: f7ff ff38 bl 80178b0 <__exponent> 8017a40: 9a0a ldr r2, [sp, #40] @ 0x28 8017a42: 1813 adds r3, r2, r0 8017a44: 2a01 cmp r2, #1 8017a46: 4682 mov sl, r0 8017a48: 6123 str r3, [r4, #16] 8017a4a: dc02 bgt.n 8017a52 <_printf_float+0x12a> 8017a4c: 6822 ldr r2, [r4, #0] 8017a4e: 07d2 lsls r2, r2, #31 8017a50: d501 bpl.n 8017a56 <_printf_float+0x12e> 8017a52: 3301 adds r3, #1 8017a54: 6123 str r3, [r4, #16] 8017a56: f89d 3023 ldrb.w r3, [sp, #35] @ 0x23 8017a5a: 2b00 cmp r3, #0 8017a5c: d0a6 beq.n 80179ac <_printf_float+0x84> 8017a5e: 232d movs r3, #45 @ 0x2d 8017a60: f884 3043 strb.w r3, [r4, #67] @ 0x43 8017a64: e7a2 b.n 80179ac <_printf_float+0x84> 8017a66: f1ba 0f47 cmp.w sl, #71 @ 0x47 8017a6a: d1c4 bne.n 80179f6 <_printf_float+0xce> 8017a6c: 2b00 cmp r3, #0 8017a6e: d1c2 bne.n 80179f6 <_printf_float+0xce> 8017a70: 2301 movs r3, #1 8017a72: e7bf b.n 80179f4 <_printf_float+0xcc> 8017a74: f1b9 0f65 cmp.w r9, #101 @ 0x65 8017a78: d9db bls.n 8017a32 <_printf_float+0x10a> 8017a7a: f1b9 0f66 cmp.w r9, #102 @ 0x66 8017a7e: d118 bne.n 8017ab2 <_printf_float+0x18a> 8017a80: 2900 cmp r1, #0 8017a82: 6863 ldr r3, [r4, #4] 8017a84: dd0b ble.n 8017a9e <_printf_float+0x176> 8017a86: 6121 str r1, [r4, #16] 8017a88: b913 cbnz r3, 8017a90 <_printf_float+0x168> 8017a8a: 6822 ldr r2, [r4, #0] 8017a8c: 07d0 lsls r0, r2, #31 8017a8e: d502 bpl.n 8017a96 <_printf_float+0x16e> 8017a90: 3301 adds r3, #1 8017a92: 440b add r3, r1 8017a94: 6123 str r3, [r4, #16] 8017a96: 65a1 str r1, [r4, #88] @ 0x58 8017a98: f04f 0a00 mov.w sl, #0 8017a9c: e7db b.n 8017a56 <_printf_float+0x12e> 8017a9e: b913 cbnz r3, 8017aa6 <_printf_float+0x17e> 8017aa0: 6822 ldr r2, [r4, #0] 8017aa2: 07d2 lsls r2, r2, #31 8017aa4: d501 bpl.n 8017aaa <_printf_float+0x182> 8017aa6: 3302 adds r3, #2 8017aa8: e7f4 b.n 8017a94 <_printf_float+0x16c> 8017aaa: 2301 movs r3, #1 8017aac: e7f2 b.n 8017a94 <_printf_float+0x16c> 8017aae: f04f 0967 mov.w r9, #103 @ 0x67 8017ab2: 9b0a ldr r3, [sp, #40] @ 0x28 8017ab4: 4299 cmp r1, r3 8017ab6: db05 blt.n 8017ac4 <_printf_float+0x19c> 8017ab8: 6823 ldr r3, [r4, #0] 8017aba: 6121 str r1, [r4, #16] 8017abc: 07d8 lsls r0, r3, #31 8017abe: d5ea bpl.n 8017a96 <_printf_float+0x16e> 8017ac0: 1c4b adds r3, r1, #1 8017ac2: e7e7 b.n 8017a94 <_printf_float+0x16c> 8017ac4: 2900 cmp r1, #0 8017ac6: bfd4 ite le 8017ac8: f1c1 0202 rsble r2, r1, #2 8017acc: 2201 movgt r2, #1 8017ace: 4413 add r3, r2 8017ad0: e7e0 b.n 8017a94 <_printf_float+0x16c> 8017ad2: 6823 ldr r3, [r4, #0] 8017ad4: 055a lsls r2, r3, #21 8017ad6: d407 bmi.n 8017ae8 <_printf_float+0x1c0> 8017ad8: 6923 ldr r3, [r4, #16] 8017ada: 4642 mov r2, r8 8017adc: 4631 mov r1, r6 8017ade: 4628 mov r0, r5 8017ae0: 47b8 blx r7 8017ae2: 3001 adds r0, #1 8017ae4: d12a bne.n 8017b3c <_printf_float+0x214> 8017ae6: e76b b.n 80179c0 <_printf_float+0x98> 8017ae8: f1b9 0f65 cmp.w r9, #101 @ 0x65 8017aec: f240 80e0 bls.w 8017cb0 <_printf_float+0x388> 8017af0: ed94 7b12 vldr d7, [r4, #72] @ 0x48 8017af4: eeb5 7b40 vcmp.f64 d7, #0.0 8017af8: eef1 fa10 vmrs APSR_nzcv, fpscr 8017afc: d133 bne.n 8017b66 <_printf_float+0x23e> 8017afe: 4a38 ldr r2, [pc, #224] @ (8017be0 <_printf_float+0x2b8>) 8017b00: 2301 movs r3, #1 8017b02: 4631 mov r1, r6 8017b04: 4628 mov r0, r5 8017b06: 47b8 blx r7 8017b08: 3001 adds r0, #1 8017b0a: f43f af59 beq.w 80179c0 <_printf_float+0x98> 8017b0e: e9dd 3809 ldrd r3, r8, [sp, #36] @ 0x24 8017b12: 4543 cmp r3, r8 8017b14: db02 blt.n 8017b1c <_printf_float+0x1f4> 8017b16: 6823 ldr r3, [r4, #0] 8017b18: 07d8 lsls r0, r3, #31 8017b1a: d50f bpl.n 8017b3c <_printf_float+0x214> 8017b1c: 9b05 ldr r3, [sp, #20] 8017b1e: 465a mov r2, fp 8017b20: 4631 mov r1, r6 8017b22: 4628 mov r0, r5 8017b24: 47b8 blx r7 8017b26: 3001 adds r0, #1 8017b28: f43f af4a beq.w 80179c0 <_printf_float+0x98> 8017b2c: f04f 0900 mov.w r9, #0 8017b30: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 8017b34: f104 0a1a add.w sl, r4, #26 8017b38: 45c8 cmp r8, r9 8017b3a: dc09 bgt.n 8017b50 <_printf_float+0x228> 8017b3c: 6823 ldr r3, [r4, #0] 8017b3e: 079b lsls r3, r3, #30 8017b40: f100 8107 bmi.w 8017d52 <_printf_float+0x42a> 8017b44: 68e0 ldr r0, [r4, #12] 8017b46: 9b0b ldr r3, [sp, #44] @ 0x2c 8017b48: 4298 cmp r0, r3 8017b4a: bfb8 it lt 8017b4c: 4618 movlt r0, r3 8017b4e: e739 b.n 80179c4 <_printf_float+0x9c> 8017b50: 2301 movs r3, #1 8017b52: 4652 mov r2, sl 8017b54: 4631 mov r1, r6 8017b56: 4628 mov r0, r5 8017b58: 47b8 blx r7 8017b5a: 3001 adds r0, #1 8017b5c: f43f af30 beq.w 80179c0 <_printf_float+0x98> 8017b60: f109 0901 add.w r9, r9, #1 8017b64: e7e8 b.n 8017b38 <_printf_float+0x210> 8017b66: 9b09 ldr r3, [sp, #36] @ 0x24 8017b68: 2b00 cmp r3, #0 8017b6a: dc3b bgt.n 8017be4 <_printf_float+0x2bc> 8017b6c: 4a1c ldr r2, [pc, #112] @ (8017be0 <_printf_float+0x2b8>) 8017b6e: 2301 movs r3, #1 8017b70: 4631 mov r1, r6 8017b72: 4628 mov r0, r5 8017b74: 47b8 blx r7 8017b76: 3001 adds r0, #1 8017b78: f43f af22 beq.w 80179c0 <_printf_float+0x98> 8017b7c: e9dd 3909 ldrd r3, r9, [sp, #36] @ 0x24 8017b80: ea59 0303 orrs.w r3, r9, r3 8017b84: d102 bne.n 8017b8c <_printf_float+0x264> 8017b86: 6823 ldr r3, [r4, #0] 8017b88: 07d9 lsls r1, r3, #31 8017b8a: d5d7 bpl.n 8017b3c <_printf_float+0x214> 8017b8c: 9b05 ldr r3, [sp, #20] 8017b8e: 465a mov r2, fp 8017b90: 4631 mov r1, r6 8017b92: 4628 mov r0, r5 8017b94: 47b8 blx r7 8017b96: 3001 adds r0, #1 8017b98: f43f af12 beq.w 80179c0 <_printf_float+0x98> 8017b9c: f04f 0a00 mov.w sl, #0 8017ba0: f104 0b1a add.w fp, r4, #26 8017ba4: 9b09 ldr r3, [sp, #36] @ 0x24 8017ba6: 425b negs r3, r3 8017ba8: 4553 cmp r3, sl 8017baa: dc01 bgt.n 8017bb0 <_printf_float+0x288> 8017bac: 464b mov r3, r9 8017bae: e794 b.n 8017ada <_printf_float+0x1b2> 8017bb0: 2301 movs r3, #1 8017bb2: 465a mov r2, fp 8017bb4: 4631 mov r1, r6 8017bb6: 4628 mov r0, r5 8017bb8: 47b8 blx r7 8017bba: 3001 adds r0, #1 8017bbc: f43f af00 beq.w 80179c0 <_printf_float+0x98> 8017bc0: f10a 0a01 add.w sl, sl, #1 8017bc4: e7ee b.n 8017ba4 <_printf_float+0x27c> 8017bc6: bf00 nop 8017bc8: ffffffff .word 0xffffffff 8017bcc: 7fefffff .word 0x7fefffff 8017bd0: 0801a2c8 .word 0x0801a2c8 8017bd4: 0801a2cc .word 0x0801a2cc 8017bd8: 0801a2d0 .word 0x0801a2d0 8017bdc: 0801a2d4 .word 0x0801a2d4 8017be0: 0801a2d8 .word 0x0801a2d8 8017be4: 6da3 ldr r3, [r4, #88] @ 0x58 8017be6: f8dd a028 ldr.w sl, [sp, #40] @ 0x28 8017bea: 4553 cmp r3, sl 8017bec: bfa8 it ge 8017bee: 4653 movge r3, sl 8017bf0: 2b00 cmp r3, #0 8017bf2: 4699 mov r9, r3 8017bf4: dc37 bgt.n 8017c66 <_printf_float+0x33e> 8017bf6: 2300 movs r3, #0 8017bf8: 9307 str r3, [sp, #28] 8017bfa: ea29 79e9 bic.w r9, r9, r9, asr #31 8017bfe: f104 021a add.w r2, r4, #26 8017c02: 6da3 ldr r3, [r4, #88] @ 0x58 8017c04: 9907 ldr r1, [sp, #28] 8017c06: 9306 str r3, [sp, #24] 8017c08: eba3 0309 sub.w r3, r3, r9 8017c0c: 428b cmp r3, r1 8017c0e: dc31 bgt.n 8017c74 <_printf_float+0x34c> 8017c10: 9b09 ldr r3, [sp, #36] @ 0x24 8017c12: 459a cmp sl, r3 8017c14: dc3b bgt.n 8017c8e <_printf_float+0x366> 8017c16: 6823 ldr r3, [r4, #0] 8017c18: 07da lsls r2, r3, #31 8017c1a: d438 bmi.n 8017c8e <_printf_float+0x366> 8017c1c: 9b09 ldr r3, [sp, #36] @ 0x24 8017c1e: ebaa 0903 sub.w r9, sl, r3 8017c22: 9b06 ldr r3, [sp, #24] 8017c24: ebaa 0303 sub.w r3, sl, r3 8017c28: 4599 cmp r9, r3 8017c2a: bfa8 it ge 8017c2c: 4699 movge r9, r3 8017c2e: f1b9 0f00 cmp.w r9, #0 8017c32: dc34 bgt.n 8017c9e <_printf_float+0x376> 8017c34: f04f 0800 mov.w r8, #0 8017c38: ea29 79e9 bic.w r9, r9, r9, asr #31 8017c3c: f104 0b1a add.w fp, r4, #26 8017c40: 9b09 ldr r3, [sp, #36] @ 0x24 8017c42: ebaa 0303 sub.w r3, sl, r3 8017c46: eba3 0309 sub.w r3, r3, r9 8017c4a: 4543 cmp r3, r8 8017c4c: f77f af76 ble.w 8017b3c <_printf_float+0x214> 8017c50: 2301 movs r3, #1 8017c52: 465a mov r2, fp 8017c54: 4631 mov r1, r6 8017c56: 4628 mov r0, r5 8017c58: 47b8 blx r7 8017c5a: 3001 adds r0, #1 8017c5c: f43f aeb0 beq.w 80179c0 <_printf_float+0x98> 8017c60: f108 0801 add.w r8, r8, #1 8017c64: e7ec b.n 8017c40 <_printf_float+0x318> 8017c66: 4642 mov r2, r8 8017c68: 4631 mov r1, r6 8017c6a: 4628 mov r0, r5 8017c6c: 47b8 blx r7 8017c6e: 3001 adds r0, #1 8017c70: d1c1 bne.n 8017bf6 <_printf_float+0x2ce> 8017c72: e6a5 b.n 80179c0 <_printf_float+0x98> 8017c74: 2301 movs r3, #1 8017c76: 4631 mov r1, r6 8017c78: 4628 mov r0, r5 8017c7a: 9206 str r2, [sp, #24] 8017c7c: 47b8 blx r7 8017c7e: 3001 adds r0, #1 8017c80: f43f ae9e beq.w 80179c0 <_printf_float+0x98> 8017c84: 9b07 ldr r3, [sp, #28] 8017c86: 9a06 ldr r2, [sp, #24] 8017c88: 3301 adds r3, #1 8017c8a: 9307 str r3, [sp, #28] 8017c8c: e7b9 b.n 8017c02 <_printf_float+0x2da> 8017c8e: 9b05 ldr r3, [sp, #20] 8017c90: 465a mov r2, fp 8017c92: 4631 mov r1, r6 8017c94: 4628 mov r0, r5 8017c96: 47b8 blx r7 8017c98: 3001 adds r0, #1 8017c9a: d1bf bne.n 8017c1c <_printf_float+0x2f4> 8017c9c: e690 b.n 80179c0 <_printf_float+0x98> 8017c9e: 9a06 ldr r2, [sp, #24] 8017ca0: 464b mov r3, r9 8017ca2: 4442 add r2, r8 8017ca4: 4631 mov r1, r6 8017ca6: 4628 mov r0, r5 8017ca8: 47b8 blx r7 8017caa: 3001 adds r0, #1 8017cac: d1c2 bne.n 8017c34 <_printf_float+0x30c> 8017cae: e687 b.n 80179c0 <_printf_float+0x98> 8017cb0: f8dd 9028 ldr.w r9, [sp, #40] @ 0x28 8017cb4: f1b9 0f01 cmp.w r9, #1 8017cb8: dc01 bgt.n 8017cbe <_printf_float+0x396> 8017cba: 07db lsls r3, r3, #31 8017cbc: d536 bpl.n 8017d2c <_printf_float+0x404> 8017cbe: 2301 movs r3, #1 8017cc0: 4642 mov r2, r8 8017cc2: 4631 mov r1, r6 8017cc4: 4628 mov r0, r5 8017cc6: 47b8 blx r7 8017cc8: 3001 adds r0, #1 8017cca: f43f ae79 beq.w 80179c0 <_printf_float+0x98> 8017cce: 9b05 ldr r3, [sp, #20] 8017cd0: 465a mov r2, fp 8017cd2: 4631 mov r1, r6 8017cd4: 4628 mov r0, r5 8017cd6: 47b8 blx r7 8017cd8: 3001 adds r0, #1 8017cda: f43f ae71 beq.w 80179c0 <_printf_float+0x98> 8017cde: ed94 7b12 vldr d7, [r4, #72] @ 0x48 8017ce2: eeb5 7b40 vcmp.f64 d7, #0.0 8017ce6: eef1 fa10 vmrs APSR_nzcv, fpscr 8017cea: f109 39ff add.w r9, r9, #4294967295 @ 0xffffffff 8017cee: d018 beq.n 8017d22 <_printf_float+0x3fa> 8017cf0: 464b mov r3, r9 8017cf2: f108 0201 add.w r2, r8, #1 8017cf6: 4631 mov r1, r6 8017cf8: 4628 mov r0, r5 8017cfa: 47b8 blx r7 8017cfc: 3001 adds r0, #1 8017cfe: d10c bne.n 8017d1a <_printf_float+0x3f2> 8017d00: e65e b.n 80179c0 <_printf_float+0x98> 8017d02: 2301 movs r3, #1 8017d04: 465a mov r2, fp 8017d06: 4631 mov r1, r6 8017d08: 4628 mov r0, r5 8017d0a: 47b8 blx r7 8017d0c: 3001 adds r0, #1 8017d0e: f43f ae57 beq.w 80179c0 <_printf_float+0x98> 8017d12: f108 0801 add.w r8, r8, #1 8017d16: 45c8 cmp r8, r9 8017d18: dbf3 blt.n 8017d02 <_printf_float+0x3da> 8017d1a: 4653 mov r3, sl 8017d1c: f104 0250 add.w r2, r4, #80 @ 0x50 8017d20: e6dc b.n 8017adc <_printf_float+0x1b4> 8017d22: f04f 0800 mov.w r8, #0 8017d26: f104 0b1a add.w fp, r4, #26 8017d2a: e7f4 b.n 8017d16 <_printf_float+0x3ee> 8017d2c: 2301 movs r3, #1 8017d2e: 4642 mov r2, r8 8017d30: e7e1 b.n 8017cf6 <_printf_float+0x3ce> 8017d32: 2301 movs r3, #1 8017d34: 464a mov r2, r9 8017d36: 4631 mov r1, r6 8017d38: 4628 mov r0, r5 8017d3a: 47b8 blx r7 8017d3c: 3001 adds r0, #1 8017d3e: f43f ae3f beq.w 80179c0 <_printf_float+0x98> 8017d42: f108 0801 add.w r8, r8, #1 8017d46: 68e3 ldr r3, [r4, #12] 8017d48: 990b ldr r1, [sp, #44] @ 0x2c 8017d4a: 1a5b subs r3, r3, r1 8017d4c: 4543 cmp r3, r8 8017d4e: dcf0 bgt.n 8017d32 <_printf_float+0x40a> 8017d50: e6f8 b.n 8017b44 <_printf_float+0x21c> 8017d52: f04f 0800 mov.w r8, #0 8017d56: f104 0919 add.w r9, r4, #25 8017d5a: e7f4 b.n 8017d46 <_printf_float+0x41e> 08017d5c <_printf_common>: 8017d5c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8017d60: 4616 mov r6, r2 8017d62: 4698 mov r8, r3 8017d64: 688a ldr r2, [r1, #8] 8017d66: 690b ldr r3, [r1, #16] 8017d68: f8dd 9020 ldr.w r9, [sp, #32] 8017d6c: 4293 cmp r3, r2 8017d6e: bfb8 it lt 8017d70: 4613 movlt r3, r2 8017d72: 6033 str r3, [r6, #0] 8017d74: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 8017d78: 4607 mov r7, r0 8017d7a: 460c mov r4, r1 8017d7c: b10a cbz r2, 8017d82 <_printf_common+0x26> 8017d7e: 3301 adds r3, #1 8017d80: 6033 str r3, [r6, #0] 8017d82: 6823 ldr r3, [r4, #0] 8017d84: 0699 lsls r1, r3, #26 8017d86: bf42 ittt mi 8017d88: 6833 ldrmi r3, [r6, #0] 8017d8a: 3302 addmi r3, #2 8017d8c: 6033 strmi r3, [r6, #0] 8017d8e: 6825 ldr r5, [r4, #0] 8017d90: f015 0506 ands.w r5, r5, #6 8017d94: d106 bne.n 8017da4 <_printf_common+0x48> 8017d96: f104 0a19 add.w sl, r4, #25 8017d9a: 68e3 ldr r3, [r4, #12] 8017d9c: 6832 ldr r2, [r6, #0] 8017d9e: 1a9b subs r3, r3, r2 8017da0: 42ab cmp r3, r5 8017da2: dc26 bgt.n 8017df2 <_printf_common+0x96> 8017da4: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 8017da8: 6822 ldr r2, [r4, #0] 8017daa: 3b00 subs r3, #0 8017dac: bf18 it ne 8017dae: 2301 movne r3, #1 8017db0: 0692 lsls r2, r2, #26 8017db2: d42b bmi.n 8017e0c <_printf_common+0xb0> 8017db4: f104 0243 add.w r2, r4, #67 @ 0x43 8017db8: 4641 mov r1, r8 8017dba: 4638 mov r0, r7 8017dbc: 47c8 blx r9 8017dbe: 3001 adds r0, #1 8017dc0: d01e beq.n 8017e00 <_printf_common+0xa4> 8017dc2: 6823 ldr r3, [r4, #0] 8017dc4: 6922 ldr r2, [r4, #16] 8017dc6: f003 0306 and.w r3, r3, #6 8017dca: 2b04 cmp r3, #4 8017dcc: bf02 ittt eq 8017dce: 68e5 ldreq r5, [r4, #12] 8017dd0: 6833 ldreq r3, [r6, #0] 8017dd2: 1aed subeq r5, r5, r3 8017dd4: 68a3 ldr r3, [r4, #8] 8017dd6: bf0c ite eq 8017dd8: ea25 75e5 biceq.w r5, r5, r5, asr #31 8017ddc: 2500 movne r5, #0 8017dde: 4293 cmp r3, r2 8017de0: bfc4 itt gt 8017de2: 1a9b subgt r3, r3, r2 8017de4: 18ed addgt r5, r5, r3 8017de6: 2600 movs r6, #0 8017de8: 341a adds r4, #26 8017dea: 42b5 cmp r5, r6 8017dec: d11a bne.n 8017e24 <_printf_common+0xc8> 8017dee: 2000 movs r0, #0 8017df0: e008 b.n 8017e04 <_printf_common+0xa8> 8017df2: 2301 movs r3, #1 8017df4: 4652 mov r2, sl 8017df6: 4641 mov r1, r8 8017df8: 4638 mov r0, r7 8017dfa: 47c8 blx r9 8017dfc: 3001 adds r0, #1 8017dfe: d103 bne.n 8017e08 <_printf_common+0xac> 8017e00: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8017e04: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8017e08: 3501 adds r5, #1 8017e0a: e7c6 b.n 8017d9a <_printf_common+0x3e> 8017e0c: 18e1 adds r1, r4, r3 8017e0e: 1c5a adds r2, r3, #1 8017e10: 2030 movs r0, #48 @ 0x30 8017e12: f881 0043 strb.w r0, [r1, #67] @ 0x43 8017e16: 4422 add r2, r4 8017e18: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 8017e1c: f882 1043 strb.w r1, [r2, #67] @ 0x43 8017e20: 3302 adds r3, #2 8017e22: e7c7 b.n 8017db4 <_printf_common+0x58> 8017e24: 2301 movs r3, #1 8017e26: 4622 mov r2, r4 8017e28: 4641 mov r1, r8 8017e2a: 4638 mov r0, r7 8017e2c: 47c8 blx r9 8017e2e: 3001 adds r0, #1 8017e30: d0e6 beq.n 8017e00 <_printf_common+0xa4> 8017e32: 3601 adds r6, #1 8017e34: e7d9 b.n 8017dea <_printf_common+0x8e> ... 08017e38 <_printf_i>: 8017e38: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8017e3c: 7e0f ldrb r7, [r1, #24] 8017e3e: 9e0c ldr r6, [sp, #48] @ 0x30 8017e40: 2f78 cmp r7, #120 @ 0x78 8017e42: 4691 mov r9, r2 8017e44: 4680 mov r8, r0 8017e46: 460c mov r4, r1 8017e48: 469a mov sl, r3 8017e4a: f101 0243 add.w r2, r1, #67 @ 0x43 8017e4e: d807 bhi.n 8017e60 <_printf_i+0x28> 8017e50: 2f62 cmp r7, #98 @ 0x62 8017e52: d80a bhi.n 8017e6a <_printf_i+0x32> 8017e54: 2f00 cmp r7, #0 8017e56: f000 80d2 beq.w 8017ffe <_printf_i+0x1c6> 8017e5a: 2f58 cmp r7, #88 @ 0x58 8017e5c: f000 80b9 beq.w 8017fd2 <_printf_i+0x19a> 8017e60: f104 0642 add.w r6, r4, #66 @ 0x42 8017e64: f884 7042 strb.w r7, [r4, #66] @ 0x42 8017e68: e03a b.n 8017ee0 <_printf_i+0xa8> 8017e6a: f1a7 0363 sub.w r3, r7, #99 @ 0x63 8017e6e: 2b15 cmp r3, #21 8017e70: d8f6 bhi.n 8017e60 <_printf_i+0x28> 8017e72: a101 add r1, pc, #4 @ (adr r1, 8017e78 <_printf_i+0x40>) 8017e74: f851 f023 ldr.w pc, [r1, r3, lsl #2] 8017e78: 08017ed1 .word 0x08017ed1 8017e7c: 08017ee5 .word 0x08017ee5 8017e80: 08017e61 .word 0x08017e61 8017e84: 08017e61 .word 0x08017e61 8017e88: 08017e61 .word 0x08017e61 8017e8c: 08017e61 .word 0x08017e61 8017e90: 08017ee5 .word 0x08017ee5 8017e94: 08017e61 .word 0x08017e61 8017e98: 08017e61 .word 0x08017e61 8017e9c: 08017e61 .word 0x08017e61 8017ea0: 08017e61 .word 0x08017e61 8017ea4: 08017fe5 .word 0x08017fe5 8017ea8: 08017f0f .word 0x08017f0f 8017eac: 08017f9f .word 0x08017f9f 8017eb0: 08017e61 .word 0x08017e61 8017eb4: 08017e61 .word 0x08017e61 8017eb8: 08018007 .word 0x08018007 8017ebc: 08017e61 .word 0x08017e61 8017ec0: 08017f0f .word 0x08017f0f 8017ec4: 08017e61 .word 0x08017e61 8017ec8: 08017e61 .word 0x08017e61 8017ecc: 08017fa7 .word 0x08017fa7 8017ed0: 6833 ldr r3, [r6, #0] 8017ed2: 1d1a adds r2, r3, #4 8017ed4: 681b ldr r3, [r3, #0] 8017ed6: 6032 str r2, [r6, #0] 8017ed8: f104 0642 add.w r6, r4, #66 @ 0x42 8017edc: f884 3042 strb.w r3, [r4, #66] @ 0x42 8017ee0: 2301 movs r3, #1 8017ee2: e09d b.n 8018020 <_printf_i+0x1e8> 8017ee4: 6833 ldr r3, [r6, #0] 8017ee6: 6820 ldr r0, [r4, #0] 8017ee8: 1d19 adds r1, r3, #4 8017eea: 6031 str r1, [r6, #0] 8017eec: 0606 lsls r6, r0, #24 8017eee: d501 bpl.n 8017ef4 <_printf_i+0xbc> 8017ef0: 681d ldr r5, [r3, #0] 8017ef2: e003 b.n 8017efc <_printf_i+0xc4> 8017ef4: 0645 lsls r5, r0, #25 8017ef6: d5fb bpl.n 8017ef0 <_printf_i+0xb8> 8017ef8: f9b3 5000 ldrsh.w r5, [r3] 8017efc: 2d00 cmp r5, #0 8017efe: da03 bge.n 8017f08 <_printf_i+0xd0> 8017f00: 232d movs r3, #45 @ 0x2d 8017f02: 426d negs r5, r5 8017f04: f884 3043 strb.w r3, [r4, #67] @ 0x43 8017f08: 4859 ldr r0, [pc, #356] @ (8018070 <_printf_i+0x238>) 8017f0a: 230a movs r3, #10 8017f0c: e011 b.n 8017f32 <_printf_i+0xfa> 8017f0e: 6821 ldr r1, [r4, #0] 8017f10: 6833 ldr r3, [r6, #0] 8017f12: 0608 lsls r0, r1, #24 8017f14: f853 5b04 ldr.w r5, [r3], #4 8017f18: d402 bmi.n 8017f20 <_printf_i+0xe8> 8017f1a: 0649 lsls r1, r1, #25 8017f1c: bf48 it mi 8017f1e: b2ad uxthmi r5, r5 8017f20: 2f6f cmp r7, #111 @ 0x6f 8017f22: 4853 ldr r0, [pc, #332] @ (8018070 <_printf_i+0x238>) 8017f24: 6033 str r3, [r6, #0] 8017f26: bf14 ite ne 8017f28: 230a movne r3, #10 8017f2a: 2308 moveq r3, #8 8017f2c: 2100 movs r1, #0 8017f2e: f884 1043 strb.w r1, [r4, #67] @ 0x43 8017f32: 6866 ldr r6, [r4, #4] 8017f34: 60a6 str r6, [r4, #8] 8017f36: 2e00 cmp r6, #0 8017f38: bfa2 ittt ge 8017f3a: 6821 ldrge r1, [r4, #0] 8017f3c: f021 0104 bicge.w r1, r1, #4 8017f40: 6021 strge r1, [r4, #0] 8017f42: b90d cbnz r5, 8017f48 <_printf_i+0x110> 8017f44: 2e00 cmp r6, #0 8017f46: d04b beq.n 8017fe0 <_printf_i+0x1a8> 8017f48: 4616 mov r6, r2 8017f4a: fbb5 f1f3 udiv r1, r5, r3 8017f4e: fb03 5711 mls r7, r3, r1, r5 8017f52: 5dc7 ldrb r7, [r0, r7] 8017f54: f806 7d01 strb.w r7, [r6, #-1]! 8017f58: 462f mov r7, r5 8017f5a: 42bb cmp r3, r7 8017f5c: 460d mov r5, r1 8017f5e: d9f4 bls.n 8017f4a <_printf_i+0x112> 8017f60: 2b08 cmp r3, #8 8017f62: d10b bne.n 8017f7c <_printf_i+0x144> 8017f64: 6823 ldr r3, [r4, #0] 8017f66: 07df lsls r7, r3, #31 8017f68: d508 bpl.n 8017f7c <_printf_i+0x144> 8017f6a: 6923 ldr r3, [r4, #16] 8017f6c: 6861 ldr r1, [r4, #4] 8017f6e: 4299 cmp r1, r3 8017f70: bfde ittt le 8017f72: 2330 movle r3, #48 @ 0x30 8017f74: f806 3c01 strble.w r3, [r6, #-1] 8017f78: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 8017f7c: 1b92 subs r2, r2, r6 8017f7e: 6122 str r2, [r4, #16] 8017f80: f8cd a000 str.w sl, [sp] 8017f84: 464b mov r3, r9 8017f86: aa03 add r2, sp, #12 8017f88: 4621 mov r1, r4 8017f8a: 4640 mov r0, r8 8017f8c: f7ff fee6 bl 8017d5c <_printf_common> 8017f90: 3001 adds r0, #1 8017f92: d14a bne.n 801802a <_printf_i+0x1f2> 8017f94: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8017f98: b004 add sp, #16 8017f9a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8017f9e: 6823 ldr r3, [r4, #0] 8017fa0: f043 0320 orr.w r3, r3, #32 8017fa4: 6023 str r3, [r4, #0] 8017fa6: 4833 ldr r0, [pc, #204] @ (8018074 <_printf_i+0x23c>) 8017fa8: 2778 movs r7, #120 @ 0x78 8017faa: f884 7045 strb.w r7, [r4, #69] @ 0x45 8017fae: 6823 ldr r3, [r4, #0] 8017fb0: 6831 ldr r1, [r6, #0] 8017fb2: 061f lsls r7, r3, #24 8017fb4: f851 5b04 ldr.w r5, [r1], #4 8017fb8: d402 bmi.n 8017fc0 <_printf_i+0x188> 8017fba: 065f lsls r7, r3, #25 8017fbc: bf48 it mi 8017fbe: b2ad uxthmi r5, r5 8017fc0: 6031 str r1, [r6, #0] 8017fc2: 07d9 lsls r1, r3, #31 8017fc4: bf44 itt mi 8017fc6: f043 0320 orrmi.w r3, r3, #32 8017fca: 6023 strmi r3, [r4, #0] 8017fcc: b11d cbz r5, 8017fd6 <_printf_i+0x19e> 8017fce: 2310 movs r3, #16 8017fd0: e7ac b.n 8017f2c <_printf_i+0xf4> 8017fd2: 4827 ldr r0, [pc, #156] @ (8018070 <_printf_i+0x238>) 8017fd4: e7e9 b.n 8017faa <_printf_i+0x172> 8017fd6: 6823 ldr r3, [r4, #0] 8017fd8: f023 0320 bic.w r3, r3, #32 8017fdc: 6023 str r3, [r4, #0] 8017fde: e7f6 b.n 8017fce <_printf_i+0x196> 8017fe0: 4616 mov r6, r2 8017fe2: e7bd b.n 8017f60 <_printf_i+0x128> 8017fe4: 6833 ldr r3, [r6, #0] 8017fe6: 6825 ldr r5, [r4, #0] 8017fe8: 6961 ldr r1, [r4, #20] 8017fea: 1d18 adds r0, r3, #4 8017fec: 6030 str r0, [r6, #0] 8017fee: 062e lsls r6, r5, #24 8017ff0: 681b ldr r3, [r3, #0] 8017ff2: d501 bpl.n 8017ff8 <_printf_i+0x1c0> 8017ff4: 6019 str r1, [r3, #0] 8017ff6: e002 b.n 8017ffe <_printf_i+0x1c6> 8017ff8: 0668 lsls r0, r5, #25 8017ffa: d5fb bpl.n 8017ff4 <_printf_i+0x1bc> 8017ffc: 8019 strh r1, [r3, #0] 8017ffe: 2300 movs r3, #0 8018000: 6123 str r3, [r4, #16] 8018002: 4616 mov r6, r2 8018004: e7bc b.n 8017f80 <_printf_i+0x148> 8018006: 6833 ldr r3, [r6, #0] 8018008: 1d1a adds r2, r3, #4 801800a: 6032 str r2, [r6, #0] 801800c: 681e ldr r6, [r3, #0] 801800e: 6862 ldr r2, [r4, #4] 8018010: 2100 movs r1, #0 8018012: 4630 mov r0, r6 8018014: f7e8 f964 bl 80002e0 8018018: b108 cbz r0, 801801e <_printf_i+0x1e6> 801801a: 1b80 subs r0, r0, r6 801801c: 6060 str r0, [r4, #4] 801801e: 6863 ldr r3, [r4, #4] 8018020: 6123 str r3, [r4, #16] 8018022: 2300 movs r3, #0 8018024: f884 3043 strb.w r3, [r4, #67] @ 0x43 8018028: e7aa b.n 8017f80 <_printf_i+0x148> 801802a: 6923 ldr r3, [r4, #16] 801802c: 4632 mov r2, r6 801802e: 4649 mov r1, r9 8018030: 4640 mov r0, r8 8018032: 47d0 blx sl 8018034: 3001 adds r0, #1 8018036: d0ad beq.n 8017f94 <_printf_i+0x15c> 8018038: 6823 ldr r3, [r4, #0] 801803a: 079b lsls r3, r3, #30 801803c: d413 bmi.n 8018066 <_printf_i+0x22e> 801803e: 68e0 ldr r0, [r4, #12] 8018040: 9b03 ldr r3, [sp, #12] 8018042: 4298 cmp r0, r3 8018044: bfb8 it lt 8018046: 4618 movlt r0, r3 8018048: e7a6 b.n 8017f98 <_printf_i+0x160> 801804a: 2301 movs r3, #1 801804c: 4632 mov r2, r6 801804e: 4649 mov r1, r9 8018050: 4640 mov r0, r8 8018052: 47d0 blx sl 8018054: 3001 adds r0, #1 8018056: d09d beq.n 8017f94 <_printf_i+0x15c> 8018058: 3501 adds r5, #1 801805a: 68e3 ldr r3, [r4, #12] 801805c: 9903 ldr r1, [sp, #12] 801805e: 1a5b subs r3, r3, r1 8018060: 42ab cmp r3, r5 8018062: dcf2 bgt.n 801804a <_printf_i+0x212> 8018064: e7eb b.n 801803e <_printf_i+0x206> 8018066: 2500 movs r5, #0 8018068: f104 0619 add.w r6, r4, #25 801806c: e7f5 b.n 801805a <_printf_i+0x222> 801806e: bf00 nop 8018070: 0801a2da .word 0x0801a2da 8018074: 0801a2eb .word 0x0801a2eb 08018078 : 8018078: 2300 movs r3, #0 801807a: b510 push {r4, lr} 801807c: 4604 mov r4, r0 801807e: e9c0 3300 strd r3, r3, [r0] 8018082: e9c0 3304 strd r3, r3, [r0, #16] 8018086: 6083 str r3, [r0, #8] 8018088: 8181 strh r1, [r0, #12] 801808a: 6643 str r3, [r0, #100] @ 0x64 801808c: 81c2 strh r2, [r0, #14] 801808e: 6183 str r3, [r0, #24] 8018090: 4619 mov r1, r3 8018092: 2208 movs r2, #8 8018094: 305c adds r0, #92 @ 0x5c 8018096: f000 f9e7 bl 8018468 801809a: 4b0d ldr r3, [pc, #52] @ (80180d0 ) 801809c: 6263 str r3, [r4, #36] @ 0x24 801809e: 4b0d ldr r3, [pc, #52] @ (80180d4 ) 80180a0: 62a3 str r3, [r4, #40] @ 0x28 80180a2: 4b0d ldr r3, [pc, #52] @ (80180d8 ) 80180a4: 62e3 str r3, [r4, #44] @ 0x2c 80180a6: 4b0d ldr r3, [pc, #52] @ (80180dc ) 80180a8: 6323 str r3, [r4, #48] @ 0x30 80180aa: 4b0d ldr r3, [pc, #52] @ (80180e0 ) 80180ac: 6224 str r4, [r4, #32] 80180ae: 429c cmp r4, r3 80180b0: d006 beq.n 80180c0 80180b2: f103 0268 add.w r2, r3, #104 @ 0x68 80180b6: 4294 cmp r4, r2 80180b8: d002 beq.n 80180c0 80180ba: 33d0 adds r3, #208 @ 0xd0 80180bc: 429c cmp r4, r3 80180be: d105 bne.n 80180cc 80180c0: f104 0058 add.w r0, r4, #88 @ 0x58 80180c4: e8bd 4010 ldmia.w sp!, {r4, lr} 80180c8: f000 baa0 b.w 801860c <__retarget_lock_init_recursive> 80180cc: bd10 pop {r4, pc} 80180ce: bf00 nop 80180d0: 080182b9 .word 0x080182b9 80180d4: 080182db .word 0x080182db 80180d8: 08018313 .word 0x08018313 80180dc: 08018337 .word 0x08018337 80180e0: 240131a8 .word 0x240131a8 080180e4 : 80180e4: 4a02 ldr r2, [pc, #8] @ (80180f0 ) 80180e6: 4903 ldr r1, [pc, #12] @ (80180f4 ) 80180e8: 4803 ldr r0, [pc, #12] @ (80180f8 ) 80180ea: f000 b869 b.w 80181c0 <_fwalk_sglue> 80180ee: bf00 nop 80180f0: 24000048 .word 0x24000048 80180f4: 08019bf9 .word 0x08019bf9 80180f8: 24000058 .word 0x24000058 080180fc : 80180fc: 6841 ldr r1, [r0, #4] 80180fe: 4b0c ldr r3, [pc, #48] @ (8018130 ) 8018100: 4299 cmp r1, r3 8018102: b510 push {r4, lr} 8018104: 4604 mov r4, r0 8018106: d001 beq.n 801810c 8018108: f001 fd76 bl 8019bf8 <_fflush_r> 801810c: 68a1 ldr r1, [r4, #8] 801810e: 4b09 ldr r3, [pc, #36] @ (8018134 ) 8018110: 4299 cmp r1, r3 8018112: d002 beq.n 801811a 8018114: 4620 mov r0, r4 8018116: f001 fd6f bl 8019bf8 <_fflush_r> 801811a: 68e1 ldr r1, [r4, #12] 801811c: 4b06 ldr r3, [pc, #24] @ (8018138 ) 801811e: 4299 cmp r1, r3 8018120: d004 beq.n 801812c 8018122: 4620 mov r0, r4 8018124: e8bd 4010 ldmia.w sp!, {r4, lr} 8018128: f001 bd66 b.w 8019bf8 <_fflush_r> 801812c: bd10 pop {r4, pc} 801812e: bf00 nop 8018130: 240131a8 .word 0x240131a8 8018134: 24013210 .word 0x24013210 8018138: 24013278 .word 0x24013278 0801813c : 801813c: b510 push {r4, lr} 801813e: 4b0b ldr r3, [pc, #44] @ (801816c ) 8018140: 4c0b ldr r4, [pc, #44] @ (8018170 ) 8018142: 4a0c ldr r2, [pc, #48] @ (8018174 ) 8018144: 601a str r2, [r3, #0] 8018146: 4620 mov r0, r4 8018148: 2200 movs r2, #0 801814a: 2104 movs r1, #4 801814c: f7ff ff94 bl 8018078 8018150: f104 0068 add.w r0, r4, #104 @ 0x68 8018154: 2201 movs r2, #1 8018156: 2109 movs r1, #9 8018158: f7ff ff8e bl 8018078 801815c: f104 00d0 add.w r0, r4, #208 @ 0xd0 8018160: 2202 movs r2, #2 8018162: e8bd 4010 ldmia.w sp!, {r4, lr} 8018166: 2112 movs r1, #18 8018168: f7ff bf86 b.w 8018078 801816c: 240132e0 .word 0x240132e0 8018170: 240131a8 .word 0x240131a8 8018174: 080180e5 .word 0x080180e5 08018178 <__sfp_lock_acquire>: 8018178: 4801 ldr r0, [pc, #4] @ (8018180 <__sfp_lock_acquire+0x8>) 801817a: f000 ba48 b.w 801860e <__retarget_lock_acquire_recursive> 801817e: bf00 nop 8018180: 240132e9 .word 0x240132e9 08018184 <__sfp_lock_release>: 8018184: 4801 ldr r0, [pc, #4] @ (801818c <__sfp_lock_release+0x8>) 8018186: f000 ba43 b.w 8018610 <__retarget_lock_release_recursive> 801818a: bf00 nop 801818c: 240132e9 .word 0x240132e9 08018190 <__sinit>: 8018190: b510 push {r4, lr} 8018192: 4604 mov r4, r0 8018194: f7ff fff0 bl 8018178 <__sfp_lock_acquire> 8018198: 6a23 ldr r3, [r4, #32] 801819a: b11b cbz r3, 80181a4 <__sinit+0x14> 801819c: e8bd 4010 ldmia.w sp!, {r4, lr} 80181a0: f7ff bff0 b.w 8018184 <__sfp_lock_release> 80181a4: 4b04 ldr r3, [pc, #16] @ (80181b8 <__sinit+0x28>) 80181a6: 6223 str r3, [r4, #32] 80181a8: 4b04 ldr r3, [pc, #16] @ (80181bc <__sinit+0x2c>) 80181aa: 681b ldr r3, [r3, #0] 80181ac: 2b00 cmp r3, #0 80181ae: d1f5 bne.n 801819c <__sinit+0xc> 80181b0: f7ff ffc4 bl 801813c 80181b4: e7f2 b.n 801819c <__sinit+0xc> 80181b6: bf00 nop 80181b8: 080180fd .word 0x080180fd 80181bc: 240132e0 .word 0x240132e0 080181c0 <_fwalk_sglue>: 80181c0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 80181c4: 4607 mov r7, r0 80181c6: 4688 mov r8, r1 80181c8: 4614 mov r4, r2 80181ca: 2600 movs r6, #0 80181cc: e9d4 9501 ldrd r9, r5, [r4, #4] 80181d0: f1b9 0901 subs.w r9, r9, #1 80181d4: d505 bpl.n 80181e2 <_fwalk_sglue+0x22> 80181d6: 6824 ldr r4, [r4, #0] 80181d8: 2c00 cmp r4, #0 80181da: d1f7 bne.n 80181cc <_fwalk_sglue+0xc> 80181dc: 4630 mov r0, r6 80181de: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 80181e2: 89ab ldrh r3, [r5, #12] 80181e4: 2b01 cmp r3, #1 80181e6: d907 bls.n 80181f8 <_fwalk_sglue+0x38> 80181e8: f9b5 300e ldrsh.w r3, [r5, #14] 80181ec: 3301 adds r3, #1 80181ee: d003 beq.n 80181f8 <_fwalk_sglue+0x38> 80181f0: 4629 mov r1, r5 80181f2: 4638 mov r0, r7 80181f4: 47c0 blx r8 80181f6: 4306 orrs r6, r0 80181f8: 3568 adds r5, #104 @ 0x68 80181fa: e7e9 b.n 80181d0 <_fwalk_sglue+0x10> 080181fc <_puts_r>: 80181fc: 6a03 ldr r3, [r0, #32] 80181fe: b570 push {r4, r5, r6, lr} 8018200: 6884 ldr r4, [r0, #8] 8018202: 4605 mov r5, r0 8018204: 460e mov r6, r1 8018206: b90b cbnz r3, 801820c <_puts_r+0x10> 8018208: f7ff ffc2 bl 8018190 <__sinit> 801820c: 6e63 ldr r3, [r4, #100] @ 0x64 801820e: 07db lsls r3, r3, #31 8018210: d405 bmi.n 801821e <_puts_r+0x22> 8018212: 89a3 ldrh r3, [r4, #12] 8018214: 0598 lsls r0, r3, #22 8018216: d402 bmi.n 801821e <_puts_r+0x22> 8018218: 6da0 ldr r0, [r4, #88] @ 0x58 801821a: f000 f9f8 bl 801860e <__retarget_lock_acquire_recursive> 801821e: 89a3 ldrh r3, [r4, #12] 8018220: 0719 lsls r1, r3, #28 8018222: d502 bpl.n 801822a <_puts_r+0x2e> 8018224: 6923 ldr r3, [r4, #16] 8018226: 2b00 cmp r3, #0 8018228: d135 bne.n 8018296 <_puts_r+0x9a> 801822a: 4621 mov r1, r4 801822c: 4628 mov r0, r5 801822e: f000 f8c5 bl 80183bc <__swsetup_r> 8018232: b380 cbz r0, 8018296 <_puts_r+0x9a> 8018234: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff 8018238: 6e63 ldr r3, [r4, #100] @ 0x64 801823a: 07da lsls r2, r3, #31 801823c: d405 bmi.n 801824a <_puts_r+0x4e> 801823e: 89a3 ldrh r3, [r4, #12] 8018240: 059b lsls r3, r3, #22 8018242: d402 bmi.n 801824a <_puts_r+0x4e> 8018244: 6da0 ldr r0, [r4, #88] @ 0x58 8018246: f000 f9e3 bl 8018610 <__retarget_lock_release_recursive> 801824a: 4628 mov r0, r5 801824c: bd70 pop {r4, r5, r6, pc} 801824e: 2b00 cmp r3, #0 8018250: da04 bge.n 801825c <_puts_r+0x60> 8018252: 69a2 ldr r2, [r4, #24] 8018254: 429a cmp r2, r3 8018256: dc17 bgt.n 8018288 <_puts_r+0x8c> 8018258: 290a cmp r1, #10 801825a: d015 beq.n 8018288 <_puts_r+0x8c> 801825c: 6823 ldr r3, [r4, #0] 801825e: 1c5a adds r2, r3, #1 8018260: 6022 str r2, [r4, #0] 8018262: 7019 strb r1, [r3, #0] 8018264: 68a3 ldr r3, [r4, #8] 8018266: f816 1f01 ldrb.w r1, [r6, #1]! 801826a: 3b01 subs r3, #1 801826c: 60a3 str r3, [r4, #8] 801826e: 2900 cmp r1, #0 8018270: d1ed bne.n 801824e <_puts_r+0x52> 8018272: 2b00 cmp r3, #0 8018274: da11 bge.n 801829a <_puts_r+0x9e> 8018276: 4622 mov r2, r4 8018278: 210a movs r1, #10 801827a: 4628 mov r0, r5 801827c: f000 f85f bl 801833e <__swbuf_r> 8018280: 3001 adds r0, #1 8018282: d0d7 beq.n 8018234 <_puts_r+0x38> 8018284: 250a movs r5, #10 8018286: e7d7 b.n 8018238 <_puts_r+0x3c> 8018288: 4622 mov r2, r4 801828a: 4628 mov r0, r5 801828c: f000 f857 bl 801833e <__swbuf_r> 8018290: 3001 adds r0, #1 8018292: d1e7 bne.n 8018264 <_puts_r+0x68> 8018294: e7ce b.n 8018234 <_puts_r+0x38> 8018296: 3e01 subs r6, #1 8018298: e7e4 b.n 8018264 <_puts_r+0x68> 801829a: 6823 ldr r3, [r4, #0] 801829c: 1c5a adds r2, r3, #1 801829e: 6022 str r2, [r4, #0] 80182a0: 220a movs r2, #10 80182a2: 701a strb r2, [r3, #0] 80182a4: e7ee b.n 8018284 <_puts_r+0x88> ... 080182a8 : 80182a8: 4b02 ldr r3, [pc, #8] @ (80182b4 ) 80182aa: 4601 mov r1, r0 80182ac: 6818 ldr r0, [r3, #0] 80182ae: f7ff bfa5 b.w 80181fc <_puts_r> 80182b2: bf00 nop 80182b4: 24000054 .word 0x24000054 080182b8 <__sread>: 80182b8: b510 push {r4, lr} 80182ba: 460c mov r4, r1 80182bc: f9b1 100e ldrsh.w r1, [r1, #14] 80182c0: f000 f956 bl 8018570 <_read_r> 80182c4: 2800 cmp r0, #0 80182c6: bfab itete ge 80182c8: 6d63 ldrge r3, [r4, #84] @ 0x54 80182ca: 89a3 ldrhlt r3, [r4, #12] 80182cc: 181b addge r3, r3, r0 80182ce: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 80182d2: bfac ite ge 80182d4: 6563 strge r3, [r4, #84] @ 0x54 80182d6: 81a3 strhlt r3, [r4, #12] 80182d8: bd10 pop {r4, pc} 080182da <__swrite>: 80182da: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80182de: 461f mov r7, r3 80182e0: 898b ldrh r3, [r1, #12] 80182e2: 05db lsls r3, r3, #23 80182e4: 4605 mov r5, r0 80182e6: 460c mov r4, r1 80182e8: 4616 mov r6, r2 80182ea: d505 bpl.n 80182f8 <__swrite+0x1e> 80182ec: f9b1 100e ldrsh.w r1, [r1, #14] 80182f0: 2302 movs r3, #2 80182f2: 2200 movs r2, #0 80182f4: f000 f92a bl 801854c <_lseek_r> 80182f8: 89a3 ldrh r3, [r4, #12] 80182fa: f9b4 100e ldrsh.w r1, [r4, #14] 80182fe: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8018302: 81a3 strh r3, [r4, #12] 8018304: 4632 mov r2, r6 8018306: 463b mov r3, r7 8018308: 4628 mov r0, r5 801830a: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 801830e: f000 b941 b.w 8018594 <_write_r> 08018312 <__sseek>: 8018312: b510 push {r4, lr} 8018314: 460c mov r4, r1 8018316: f9b1 100e ldrsh.w r1, [r1, #14] 801831a: f000 f917 bl 801854c <_lseek_r> 801831e: 1c43 adds r3, r0, #1 8018320: 89a3 ldrh r3, [r4, #12] 8018322: bf15 itete ne 8018324: 6560 strne r0, [r4, #84] @ 0x54 8018326: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 801832a: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 801832e: 81a3 strheq r3, [r4, #12] 8018330: bf18 it ne 8018332: 81a3 strhne r3, [r4, #12] 8018334: bd10 pop {r4, pc} 08018336 <__sclose>: 8018336: f9b1 100e ldrsh.w r1, [r1, #14] 801833a: f000 b8a1 b.w 8018480 <_close_r> 0801833e <__swbuf_r>: 801833e: b5f8 push {r3, r4, r5, r6, r7, lr} 8018340: 460e mov r6, r1 8018342: 4614 mov r4, r2 8018344: 4605 mov r5, r0 8018346: b118 cbz r0, 8018350 <__swbuf_r+0x12> 8018348: 6a03 ldr r3, [r0, #32] 801834a: b90b cbnz r3, 8018350 <__swbuf_r+0x12> 801834c: f7ff ff20 bl 8018190 <__sinit> 8018350: 69a3 ldr r3, [r4, #24] 8018352: 60a3 str r3, [r4, #8] 8018354: 89a3 ldrh r3, [r4, #12] 8018356: 071a lsls r2, r3, #28 8018358: d501 bpl.n 801835e <__swbuf_r+0x20> 801835a: 6923 ldr r3, [r4, #16] 801835c: b943 cbnz r3, 8018370 <__swbuf_r+0x32> 801835e: 4621 mov r1, r4 8018360: 4628 mov r0, r5 8018362: f000 f82b bl 80183bc <__swsetup_r> 8018366: b118 cbz r0, 8018370 <__swbuf_r+0x32> 8018368: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff 801836c: 4638 mov r0, r7 801836e: bdf8 pop {r3, r4, r5, r6, r7, pc} 8018370: 6823 ldr r3, [r4, #0] 8018372: 6922 ldr r2, [r4, #16] 8018374: 1a98 subs r0, r3, r2 8018376: 6963 ldr r3, [r4, #20] 8018378: b2f6 uxtb r6, r6 801837a: 4283 cmp r3, r0 801837c: 4637 mov r7, r6 801837e: dc05 bgt.n 801838c <__swbuf_r+0x4e> 8018380: 4621 mov r1, r4 8018382: 4628 mov r0, r5 8018384: f001 fc38 bl 8019bf8 <_fflush_r> 8018388: 2800 cmp r0, #0 801838a: d1ed bne.n 8018368 <__swbuf_r+0x2a> 801838c: 68a3 ldr r3, [r4, #8] 801838e: 3b01 subs r3, #1 8018390: 60a3 str r3, [r4, #8] 8018392: 6823 ldr r3, [r4, #0] 8018394: 1c5a adds r2, r3, #1 8018396: 6022 str r2, [r4, #0] 8018398: 701e strb r6, [r3, #0] 801839a: 6962 ldr r2, [r4, #20] 801839c: 1c43 adds r3, r0, #1 801839e: 429a cmp r2, r3 80183a0: d004 beq.n 80183ac <__swbuf_r+0x6e> 80183a2: 89a3 ldrh r3, [r4, #12] 80183a4: 07db lsls r3, r3, #31 80183a6: d5e1 bpl.n 801836c <__swbuf_r+0x2e> 80183a8: 2e0a cmp r6, #10 80183aa: d1df bne.n 801836c <__swbuf_r+0x2e> 80183ac: 4621 mov r1, r4 80183ae: 4628 mov r0, r5 80183b0: f001 fc22 bl 8019bf8 <_fflush_r> 80183b4: 2800 cmp r0, #0 80183b6: d0d9 beq.n 801836c <__swbuf_r+0x2e> 80183b8: e7d6 b.n 8018368 <__swbuf_r+0x2a> ... 080183bc <__swsetup_r>: 80183bc: b538 push {r3, r4, r5, lr} 80183be: 4b29 ldr r3, [pc, #164] @ (8018464 <__swsetup_r+0xa8>) 80183c0: 4605 mov r5, r0 80183c2: 6818 ldr r0, [r3, #0] 80183c4: 460c mov r4, r1 80183c6: b118 cbz r0, 80183d0 <__swsetup_r+0x14> 80183c8: 6a03 ldr r3, [r0, #32] 80183ca: b90b cbnz r3, 80183d0 <__swsetup_r+0x14> 80183cc: f7ff fee0 bl 8018190 <__sinit> 80183d0: f9b4 300c ldrsh.w r3, [r4, #12] 80183d4: 0719 lsls r1, r3, #28 80183d6: d422 bmi.n 801841e <__swsetup_r+0x62> 80183d8: 06da lsls r2, r3, #27 80183da: d407 bmi.n 80183ec <__swsetup_r+0x30> 80183dc: 2209 movs r2, #9 80183de: 602a str r2, [r5, #0] 80183e0: f043 0340 orr.w r3, r3, #64 @ 0x40 80183e4: 81a3 strh r3, [r4, #12] 80183e6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80183ea: e033 b.n 8018454 <__swsetup_r+0x98> 80183ec: 0758 lsls r0, r3, #29 80183ee: d512 bpl.n 8018416 <__swsetup_r+0x5a> 80183f0: 6b61 ldr r1, [r4, #52] @ 0x34 80183f2: b141 cbz r1, 8018406 <__swsetup_r+0x4a> 80183f4: f104 0344 add.w r3, r4, #68 @ 0x44 80183f8: 4299 cmp r1, r3 80183fa: d002 beq.n 8018402 <__swsetup_r+0x46> 80183fc: 4628 mov r0, r5 80183fe: f000 fef5 bl 80191ec <_free_r> 8018402: 2300 movs r3, #0 8018404: 6363 str r3, [r4, #52] @ 0x34 8018406: 89a3 ldrh r3, [r4, #12] 8018408: f023 0324 bic.w r3, r3, #36 @ 0x24 801840c: 81a3 strh r3, [r4, #12] 801840e: 2300 movs r3, #0 8018410: 6063 str r3, [r4, #4] 8018412: 6923 ldr r3, [r4, #16] 8018414: 6023 str r3, [r4, #0] 8018416: 89a3 ldrh r3, [r4, #12] 8018418: f043 0308 orr.w r3, r3, #8 801841c: 81a3 strh r3, [r4, #12] 801841e: 6923 ldr r3, [r4, #16] 8018420: b94b cbnz r3, 8018436 <__swsetup_r+0x7a> 8018422: 89a3 ldrh r3, [r4, #12] 8018424: f403 7320 and.w r3, r3, #640 @ 0x280 8018428: f5b3 7f00 cmp.w r3, #512 @ 0x200 801842c: d003 beq.n 8018436 <__swsetup_r+0x7a> 801842e: 4621 mov r1, r4 8018430: 4628 mov r0, r5 8018432: f001 fc2f bl 8019c94 <__smakebuf_r> 8018436: f9b4 300c ldrsh.w r3, [r4, #12] 801843a: f013 0201 ands.w r2, r3, #1 801843e: d00a beq.n 8018456 <__swsetup_r+0x9a> 8018440: 2200 movs r2, #0 8018442: 60a2 str r2, [r4, #8] 8018444: 6962 ldr r2, [r4, #20] 8018446: 4252 negs r2, r2 8018448: 61a2 str r2, [r4, #24] 801844a: 6922 ldr r2, [r4, #16] 801844c: b942 cbnz r2, 8018460 <__swsetup_r+0xa4> 801844e: f013 0080 ands.w r0, r3, #128 @ 0x80 8018452: d1c5 bne.n 80183e0 <__swsetup_r+0x24> 8018454: bd38 pop {r3, r4, r5, pc} 8018456: 0799 lsls r1, r3, #30 8018458: bf58 it pl 801845a: 6962 ldrpl r2, [r4, #20] 801845c: 60a2 str r2, [r4, #8] 801845e: e7f4 b.n 801844a <__swsetup_r+0x8e> 8018460: 2000 movs r0, #0 8018462: e7f7 b.n 8018454 <__swsetup_r+0x98> 8018464: 24000054 .word 0x24000054 08018468 : 8018468: 4402 add r2, r0 801846a: 4603 mov r3, r0 801846c: 4293 cmp r3, r2 801846e: d100 bne.n 8018472 8018470: 4770 bx lr 8018472: f803 1b01 strb.w r1, [r3], #1 8018476: e7f9 b.n 801846c 08018478 <_localeconv_r>: 8018478: 4800 ldr r0, [pc, #0] @ (801847c <_localeconv_r+0x4>) 801847a: 4770 bx lr 801847c: 24000194 .word 0x24000194 08018480 <_close_r>: 8018480: b538 push {r3, r4, r5, lr} 8018482: 4d06 ldr r5, [pc, #24] @ (801849c <_close_r+0x1c>) 8018484: 2300 movs r3, #0 8018486: 4604 mov r4, r0 8018488: 4608 mov r0, r1 801848a: 602b str r3, [r5, #0] 801848c: f7eb ff54 bl 8004338 <_close> 8018490: 1c43 adds r3, r0, #1 8018492: d102 bne.n 801849a <_close_r+0x1a> 8018494: 682b ldr r3, [r5, #0] 8018496: b103 cbz r3, 801849a <_close_r+0x1a> 8018498: 6023 str r3, [r4, #0] 801849a: bd38 pop {r3, r4, r5, pc} 801849c: 240132e4 .word 0x240132e4 080184a0 <_reclaim_reent>: 80184a0: 4b29 ldr r3, [pc, #164] @ (8018548 <_reclaim_reent+0xa8>) 80184a2: 681b ldr r3, [r3, #0] 80184a4: 4283 cmp r3, r0 80184a6: b570 push {r4, r5, r6, lr} 80184a8: 4604 mov r4, r0 80184aa: d04b beq.n 8018544 <_reclaim_reent+0xa4> 80184ac: 69c3 ldr r3, [r0, #28] 80184ae: b1ab cbz r3, 80184dc <_reclaim_reent+0x3c> 80184b0: 68db ldr r3, [r3, #12] 80184b2: b16b cbz r3, 80184d0 <_reclaim_reent+0x30> 80184b4: 2500 movs r5, #0 80184b6: 69e3 ldr r3, [r4, #28] 80184b8: 68db ldr r3, [r3, #12] 80184ba: 5959 ldr r1, [r3, r5] 80184bc: 2900 cmp r1, #0 80184be: d13b bne.n 8018538 <_reclaim_reent+0x98> 80184c0: 3504 adds r5, #4 80184c2: 2d80 cmp r5, #128 @ 0x80 80184c4: d1f7 bne.n 80184b6 <_reclaim_reent+0x16> 80184c6: 69e3 ldr r3, [r4, #28] 80184c8: 4620 mov r0, r4 80184ca: 68d9 ldr r1, [r3, #12] 80184cc: f000 fe8e bl 80191ec <_free_r> 80184d0: 69e3 ldr r3, [r4, #28] 80184d2: 6819 ldr r1, [r3, #0] 80184d4: b111 cbz r1, 80184dc <_reclaim_reent+0x3c> 80184d6: 4620 mov r0, r4 80184d8: f000 fe88 bl 80191ec <_free_r> 80184dc: 6961 ldr r1, [r4, #20] 80184de: b111 cbz r1, 80184e6 <_reclaim_reent+0x46> 80184e0: 4620 mov r0, r4 80184e2: f000 fe83 bl 80191ec <_free_r> 80184e6: 69e1 ldr r1, [r4, #28] 80184e8: b111 cbz r1, 80184f0 <_reclaim_reent+0x50> 80184ea: 4620 mov r0, r4 80184ec: f000 fe7e bl 80191ec <_free_r> 80184f0: 6b21 ldr r1, [r4, #48] @ 0x30 80184f2: b111 cbz r1, 80184fa <_reclaim_reent+0x5a> 80184f4: 4620 mov r0, r4 80184f6: f000 fe79 bl 80191ec <_free_r> 80184fa: 6b61 ldr r1, [r4, #52] @ 0x34 80184fc: b111 cbz r1, 8018504 <_reclaim_reent+0x64> 80184fe: 4620 mov r0, r4 8018500: f000 fe74 bl 80191ec <_free_r> 8018504: 6ba1 ldr r1, [r4, #56] @ 0x38 8018506: b111 cbz r1, 801850e <_reclaim_reent+0x6e> 8018508: 4620 mov r0, r4 801850a: f000 fe6f bl 80191ec <_free_r> 801850e: 6ca1 ldr r1, [r4, #72] @ 0x48 8018510: b111 cbz r1, 8018518 <_reclaim_reent+0x78> 8018512: 4620 mov r0, r4 8018514: f000 fe6a bl 80191ec <_free_r> 8018518: 6c61 ldr r1, [r4, #68] @ 0x44 801851a: b111 cbz r1, 8018522 <_reclaim_reent+0x82> 801851c: 4620 mov r0, r4 801851e: f000 fe65 bl 80191ec <_free_r> 8018522: 6ae1 ldr r1, [r4, #44] @ 0x2c 8018524: b111 cbz r1, 801852c <_reclaim_reent+0x8c> 8018526: 4620 mov r0, r4 8018528: f000 fe60 bl 80191ec <_free_r> 801852c: 6a23 ldr r3, [r4, #32] 801852e: b14b cbz r3, 8018544 <_reclaim_reent+0xa4> 8018530: 4620 mov r0, r4 8018532: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} 8018536: 4718 bx r3 8018538: 680e ldr r6, [r1, #0] 801853a: 4620 mov r0, r4 801853c: f000 fe56 bl 80191ec <_free_r> 8018540: 4631 mov r1, r6 8018542: e7bb b.n 80184bc <_reclaim_reent+0x1c> 8018544: bd70 pop {r4, r5, r6, pc} 8018546: bf00 nop 8018548: 24000054 .word 0x24000054 0801854c <_lseek_r>: 801854c: b538 push {r3, r4, r5, lr} 801854e: 4d07 ldr r5, [pc, #28] @ (801856c <_lseek_r+0x20>) 8018550: 4604 mov r4, r0 8018552: 4608 mov r0, r1 8018554: 4611 mov r1, r2 8018556: 2200 movs r2, #0 8018558: 602a str r2, [r5, #0] 801855a: 461a mov r2, r3 801855c: f7eb ff13 bl 8004386 <_lseek> 8018560: 1c43 adds r3, r0, #1 8018562: d102 bne.n 801856a <_lseek_r+0x1e> 8018564: 682b ldr r3, [r5, #0] 8018566: b103 cbz r3, 801856a <_lseek_r+0x1e> 8018568: 6023 str r3, [r4, #0] 801856a: bd38 pop {r3, r4, r5, pc} 801856c: 240132e4 .word 0x240132e4 08018570 <_read_r>: 8018570: b538 push {r3, r4, r5, lr} 8018572: 4d07 ldr r5, [pc, #28] @ (8018590 <_read_r+0x20>) 8018574: 4604 mov r4, r0 8018576: 4608 mov r0, r1 8018578: 4611 mov r1, r2 801857a: 2200 movs r2, #0 801857c: 602a str r2, [r5, #0] 801857e: 461a mov r2, r3 8018580: f7eb fea1 bl 80042c6 <_read> 8018584: 1c43 adds r3, r0, #1 8018586: d102 bne.n 801858e <_read_r+0x1e> 8018588: 682b ldr r3, [r5, #0] 801858a: b103 cbz r3, 801858e <_read_r+0x1e> 801858c: 6023 str r3, [r4, #0] 801858e: bd38 pop {r3, r4, r5, pc} 8018590: 240132e4 .word 0x240132e4 08018594 <_write_r>: 8018594: b538 push {r3, r4, r5, lr} 8018596: 4d07 ldr r5, [pc, #28] @ (80185b4 <_write_r+0x20>) 8018598: 4604 mov r4, r0 801859a: 4608 mov r0, r1 801859c: 4611 mov r1, r2 801859e: 2200 movs r2, #0 80185a0: 602a str r2, [r5, #0] 80185a2: 461a mov r2, r3 80185a4: f7eb feac bl 8004300 <_write> 80185a8: 1c43 adds r3, r0, #1 80185aa: d102 bne.n 80185b2 <_write_r+0x1e> 80185ac: 682b ldr r3, [r5, #0] 80185ae: b103 cbz r3, 80185b2 <_write_r+0x1e> 80185b0: 6023 str r3, [r4, #0] 80185b2: bd38 pop {r3, r4, r5, pc} 80185b4: 240132e4 .word 0x240132e4 080185b8 <__errno>: 80185b8: 4b01 ldr r3, [pc, #4] @ (80185c0 <__errno+0x8>) 80185ba: 6818 ldr r0, [r3, #0] 80185bc: 4770 bx lr 80185be: bf00 nop 80185c0: 24000054 .word 0x24000054 080185c4 <__libc_init_array>: 80185c4: b570 push {r4, r5, r6, lr} 80185c6: 4d0d ldr r5, [pc, #52] @ (80185fc <__libc_init_array+0x38>) 80185c8: 4c0d ldr r4, [pc, #52] @ (8018600 <__libc_init_array+0x3c>) 80185ca: 1b64 subs r4, r4, r5 80185cc: 10a4 asrs r4, r4, #2 80185ce: 2600 movs r6, #0 80185d0: 42a6 cmp r6, r4 80185d2: d109 bne.n 80185e8 <__libc_init_array+0x24> 80185d4: 4d0b ldr r5, [pc, #44] @ (8018604 <__libc_init_array+0x40>) 80185d6: 4c0c ldr r4, [pc, #48] @ (8018608 <__libc_init_array+0x44>) 80185d8: f001 fddc bl 801a194 <_init> 80185dc: 1b64 subs r4, r4, r5 80185de: 10a4 asrs r4, r4, #2 80185e0: 2600 movs r6, #0 80185e2: 42a6 cmp r6, r4 80185e4: d105 bne.n 80185f2 <__libc_init_array+0x2e> 80185e6: bd70 pop {r4, r5, r6, pc} 80185e8: f855 3b04 ldr.w r3, [r5], #4 80185ec: 4798 blx r3 80185ee: 3601 adds r6, #1 80185f0: e7ee b.n 80185d0 <__libc_init_array+0xc> 80185f2: f855 3b04 ldr.w r3, [r5], #4 80185f6: 4798 blx r3 80185f8: 3601 adds r6, #1 80185fa: e7f2 b.n 80185e2 <__libc_init_array+0x1e> 80185fc: 0801a640 .word 0x0801a640 8018600: 0801a640 .word 0x0801a640 8018604: 0801a640 .word 0x0801a640 8018608: 0801a644 .word 0x0801a644 0801860c <__retarget_lock_init_recursive>: 801860c: 4770 bx lr 0801860e <__retarget_lock_acquire_recursive>: 801860e: 4770 bx lr 08018610 <__retarget_lock_release_recursive>: 8018610: 4770 bx lr 08018612 : 8018612: 440a add r2, r1 8018614: 4291 cmp r1, r2 8018616: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 801861a: d100 bne.n 801861e 801861c: 4770 bx lr 801861e: b510 push {r4, lr} 8018620: f811 4b01 ldrb.w r4, [r1], #1 8018624: f803 4f01 strb.w r4, [r3, #1]! 8018628: 4291 cmp r1, r2 801862a: d1f9 bne.n 8018620 801862c: bd10 pop {r4, pc} 0801862e : 801862e: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8018632: 6903 ldr r3, [r0, #16] 8018634: 690c ldr r4, [r1, #16] 8018636: 42a3 cmp r3, r4 8018638: 4607 mov r7, r0 801863a: db7e blt.n 801873a 801863c: 3c01 subs r4, #1 801863e: f101 0814 add.w r8, r1, #20 8018642: 00a3 lsls r3, r4, #2 8018644: f100 0514 add.w r5, r0, #20 8018648: 9300 str r3, [sp, #0] 801864a: eb05 0384 add.w r3, r5, r4, lsl #2 801864e: 9301 str r3, [sp, #4] 8018650: f858 3024 ldr.w r3, [r8, r4, lsl #2] 8018654: f855 2024 ldr.w r2, [r5, r4, lsl #2] 8018658: 3301 adds r3, #1 801865a: 429a cmp r2, r3 801865c: eb08 0984 add.w r9, r8, r4, lsl #2 8018660: fbb2 f6f3 udiv r6, r2, r3 8018664: d32e bcc.n 80186c4 8018666: f04f 0a00 mov.w sl, #0 801866a: 46c4 mov ip, r8 801866c: 46ae mov lr, r5 801866e: 46d3 mov fp, sl 8018670: f85c 3b04 ldr.w r3, [ip], #4 8018674: b298 uxth r0, r3 8018676: fb06 a000 mla r0, r6, r0, sl 801867a: 0c02 lsrs r2, r0, #16 801867c: 0c1b lsrs r3, r3, #16 801867e: fb06 2303 mla r3, r6, r3, r2 8018682: f8de 2000 ldr.w r2, [lr] 8018686: b280 uxth r0, r0 8018688: b292 uxth r2, r2 801868a: 1a12 subs r2, r2, r0 801868c: 445a add r2, fp 801868e: f8de 0000 ldr.w r0, [lr] 8018692: ea4f 4a13 mov.w sl, r3, lsr #16 8018696: b29b uxth r3, r3 8018698: ebc3 4322 rsb r3, r3, r2, asr #16 801869c: eb03 4310 add.w r3, r3, r0, lsr #16 80186a0: b292 uxth r2, r2 80186a2: ea42 4203 orr.w r2, r2, r3, lsl #16 80186a6: 45e1 cmp r9, ip 80186a8: f84e 2b04 str.w r2, [lr], #4 80186ac: ea4f 4b23 mov.w fp, r3, asr #16 80186b0: d2de bcs.n 8018670 80186b2: 9b00 ldr r3, [sp, #0] 80186b4: 58eb ldr r3, [r5, r3] 80186b6: b92b cbnz r3, 80186c4 80186b8: 9b01 ldr r3, [sp, #4] 80186ba: 3b04 subs r3, #4 80186bc: 429d cmp r5, r3 80186be: 461a mov r2, r3 80186c0: d32f bcc.n 8018722 80186c2: 613c str r4, [r7, #16] 80186c4: 4638 mov r0, r7 80186c6: f001 f90b bl 80198e0 <__mcmp> 80186ca: 2800 cmp r0, #0 80186cc: db25 blt.n 801871a 80186ce: 4629 mov r1, r5 80186d0: 2000 movs r0, #0 80186d2: f858 2b04 ldr.w r2, [r8], #4 80186d6: f8d1 c000 ldr.w ip, [r1] 80186da: fa1f fe82 uxth.w lr, r2 80186de: fa1f f38c uxth.w r3, ip 80186e2: eba3 030e sub.w r3, r3, lr 80186e6: 4403 add r3, r0 80186e8: 0c12 lsrs r2, r2, #16 80186ea: ebc2 4223 rsb r2, r2, r3, asr #16 80186ee: eb02 421c add.w r2, r2, ip, lsr #16 80186f2: b29b uxth r3, r3 80186f4: ea43 4302 orr.w r3, r3, r2, lsl #16 80186f8: 45c1 cmp r9, r8 80186fa: f841 3b04 str.w r3, [r1], #4 80186fe: ea4f 4022 mov.w r0, r2, asr #16 8018702: d2e6 bcs.n 80186d2 8018704: f855 2024 ldr.w r2, [r5, r4, lsl #2] 8018708: eb05 0384 add.w r3, r5, r4, lsl #2 801870c: b922 cbnz r2, 8018718 801870e: 3b04 subs r3, #4 8018710: 429d cmp r5, r3 8018712: 461a mov r2, r3 8018714: d30b bcc.n 801872e 8018716: 613c str r4, [r7, #16] 8018718: 3601 adds r6, #1 801871a: 4630 mov r0, r6 801871c: b003 add sp, #12 801871e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8018722: 6812 ldr r2, [r2, #0] 8018724: 3b04 subs r3, #4 8018726: 2a00 cmp r2, #0 8018728: d1cb bne.n 80186c2 801872a: 3c01 subs r4, #1 801872c: e7c6 b.n 80186bc 801872e: 6812 ldr r2, [r2, #0] 8018730: 3b04 subs r3, #4 8018732: 2a00 cmp r2, #0 8018734: d1ef bne.n 8018716 8018736: 3c01 subs r4, #1 8018738: e7ea b.n 8018710 801873a: 2000 movs r0, #0 801873c: e7ee b.n 801871c ... 08018740 <_dtoa_r>: 8018740: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8018744: ed2d 8b02 vpush {d8} 8018748: 69c7 ldr r7, [r0, #28] 801874a: b091 sub sp, #68 @ 0x44 801874c: ed8d 0b02 vstr d0, [sp, #8] 8018750: ec55 4b10 vmov r4, r5, d0 8018754: 9e1c ldr r6, [sp, #112] @ 0x70 8018756: 9107 str r1, [sp, #28] 8018758: 4681 mov r9, r0 801875a: 9209 str r2, [sp, #36] @ 0x24 801875c: 930d str r3, [sp, #52] @ 0x34 801875e: b97f cbnz r7, 8018780 <_dtoa_r+0x40> 8018760: 2010 movs r0, #16 8018762: f000 fd8d bl 8019280 8018766: 4602 mov r2, r0 8018768: f8c9 001c str.w r0, [r9, #28] 801876c: b920 cbnz r0, 8018778 <_dtoa_r+0x38> 801876e: 4ba0 ldr r3, [pc, #640] @ (80189f0 <_dtoa_r+0x2b0>) 8018770: 21ef movs r1, #239 @ 0xef 8018772: 48a0 ldr r0, [pc, #640] @ (80189f4 <_dtoa_r+0x2b4>) 8018774: f001 fafc bl 8019d70 <__assert_func> 8018778: e9c0 7701 strd r7, r7, [r0, #4] 801877c: 6007 str r7, [r0, #0] 801877e: 60c7 str r7, [r0, #12] 8018780: f8d9 301c ldr.w r3, [r9, #28] 8018784: 6819 ldr r1, [r3, #0] 8018786: b159 cbz r1, 80187a0 <_dtoa_r+0x60> 8018788: 685a ldr r2, [r3, #4] 801878a: 604a str r2, [r1, #4] 801878c: 2301 movs r3, #1 801878e: 4093 lsls r3, r2 8018790: 608b str r3, [r1, #8] 8018792: 4648 mov r0, r9 8018794: f000 fe6a bl 801946c <_Bfree> 8018798: f8d9 301c ldr.w r3, [r9, #28] 801879c: 2200 movs r2, #0 801879e: 601a str r2, [r3, #0] 80187a0: 1e2b subs r3, r5, #0 80187a2: bfbb ittet lt 80187a4: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000 80187a8: 9303 strlt r3, [sp, #12] 80187aa: 2300 movge r3, #0 80187ac: 2201 movlt r2, #1 80187ae: bfac ite ge 80187b0: 6033 strge r3, [r6, #0] 80187b2: 6032 strlt r2, [r6, #0] 80187b4: 4b90 ldr r3, [pc, #576] @ (80189f8 <_dtoa_r+0x2b8>) 80187b6: 9e03 ldr r6, [sp, #12] 80187b8: 43b3 bics r3, r6 80187ba: d110 bne.n 80187de <_dtoa_r+0x9e> 80187bc: 9a0d ldr r2, [sp, #52] @ 0x34 80187be: f242 730f movw r3, #9999 @ 0x270f 80187c2: 6013 str r3, [r2, #0] 80187c4: f3c6 0313 ubfx r3, r6, #0, #20 80187c8: 4323 orrs r3, r4 80187ca: f000 84de beq.w 801918a <_dtoa_r+0xa4a> 80187ce: 9b1d ldr r3, [sp, #116] @ 0x74 80187d0: 4f8a ldr r7, [pc, #552] @ (80189fc <_dtoa_r+0x2bc>) 80187d2: 2b00 cmp r3, #0 80187d4: f000 84e0 beq.w 8019198 <_dtoa_r+0xa58> 80187d8: 1cfb adds r3, r7, #3 80187da: f000 bcdb b.w 8019194 <_dtoa_r+0xa54> 80187de: ed9d 8b02 vldr d8, [sp, #8] 80187e2: eeb5 8b40 vcmp.f64 d8, #0.0 80187e6: eef1 fa10 vmrs APSR_nzcv, fpscr 80187ea: d10a bne.n 8018802 <_dtoa_r+0xc2> 80187ec: 9a0d ldr r2, [sp, #52] @ 0x34 80187ee: 2301 movs r3, #1 80187f0: 6013 str r3, [r2, #0] 80187f2: 9b1d ldr r3, [sp, #116] @ 0x74 80187f4: b113 cbz r3, 80187fc <_dtoa_r+0xbc> 80187f6: 9a1d ldr r2, [sp, #116] @ 0x74 80187f8: 4b81 ldr r3, [pc, #516] @ (8018a00 <_dtoa_r+0x2c0>) 80187fa: 6013 str r3, [r2, #0] 80187fc: 4f81 ldr r7, [pc, #516] @ (8018a04 <_dtoa_r+0x2c4>) 80187fe: f000 bccb b.w 8019198 <_dtoa_r+0xa58> 8018802: aa0e add r2, sp, #56 @ 0x38 8018804: a90f add r1, sp, #60 @ 0x3c 8018806: 4648 mov r0, r9 8018808: eeb0 0b48 vmov.f64 d0, d8 801880c: f001 f918 bl 8019a40 <__d2b> 8018810: f3c6 530a ubfx r3, r6, #20, #11 8018814: 9a0e ldr r2, [sp, #56] @ 0x38 8018816: 9001 str r0, [sp, #4] 8018818: 2b00 cmp r3, #0 801881a: d045 beq.n 80188a8 <_dtoa_r+0x168> 801881c: eeb0 7b48 vmov.f64 d7, d8 8018820: ee18 1a90 vmov r1, s17 8018824: f3c1 0113 ubfx r1, r1, #0, #20 8018828: f041 517f orr.w r1, r1, #1069547520 @ 0x3fc00000 801882c: f441 1140 orr.w r1, r1, #3145728 @ 0x300000 8018830: f2a3 33ff subw r3, r3, #1023 @ 0x3ff 8018834: 2500 movs r5, #0 8018836: ee07 1a90 vmov s15, r1 801883a: eeb7 6b08 vmov.f64 d6, #120 @ 0x3fc00000 1.5 801883e: ed9f 5b66 vldr d5, [pc, #408] @ 80189d8 <_dtoa_r+0x298> 8018842: ee37 7b46 vsub.f64 d7, d7, d6 8018846: ed9f 6b66 vldr d6, [pc, #408] @ 80189e0 <_dtoa_r+0x2a0> 801884a: eea7 6b05 vfma.f64 d6, d7, d5 801884e: ed9f 5b66 vldr d5, [pc, #408] @ 80189e8 <_dtoa_r+0x2a8> 8018852: ee07 3a90 vmov s15, r3 8018856: eeb8 4be7 vcvt.f64.s32 d4, s15 801885a: eeb0 7b46 vmov.f64 d7, d6 801885e: eea4 7b05 vfma.f64 d7, d4, d5 8018862: eefd 6bc7 vcvt.s32.f64 s13, d7 8018866: eeb5 7bc0 vcmpe.f64 d7, #0.0 801886a: eef1 fa10 vmrs APSR_nzcv, fpscr 801886e: ee16 8a90 vmov r8, s13 8018872: d508 bpl.n 8018886 <_dtoa_r+0x146> 8018874: eeb8 6be6 vcvt.f64.s32 d6, s13 8018878: eeb4 6b47 vcmp.f64 d6, d7 801887c: eef1 fa10 vmrs APSR_nzcv, fpscr 8018880: bf18 it ne 8018882: f108 38ff addne.w r8, r8, #4294967295 @ 0xffffffff 8018886: f1b8 0f16 cmp.w r8, #22 801888a: d82b bhi.n 80188e4 <_dtoa_r+0x1a4> 801888c: 495e ldr r1, [pc, #376] @ (8018a08 <_dtoa_r+0x2c8>) 801888e: eb01 01c8 add.w r1, r1, r8, lsl #3 8018892: ed91 7b00 vldr d7, [r1] 8018896: eeb4 8bc7 vcmpe.f64 d8, d7 801889a: eef1 fa10 vmrs APSR_nzcv, fpscr 801889e: d501 bpl.n 80188a4 <_dtoa_r+0x164> 80188a0: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 80188a4: 2100 movs r1, #0 80188a6: e01e b.n 80188e6 <_dtoa_r+0x1a6> 80188a8: 9b0f ldr r3, [sp, #60] @ 0x3c 80188aa: 4413 add r3, r2 80188ac: f203 4132 addw r1, r3, #1074 @ 0x432 80188b0: 2920 cmp r1, #32 80188b2: bfc1 itttt gt 80188b4: f1c1 0140 rsbgt r1, r1, #64 @ 0x40 80188b8: 408e lslgt r6, r1 80188ba: f203 4112 addwgt r1, r3, #1042 @ 0x412 80188be: fa24 f101 lsrgt.w r1, r4, r1 80188c2: bfd6 itet le 80188c4: f1c1 0120 rsble r1, r1, #32 80188c8: 4331 orrgt r1, r6 80188ca: fa04 f101 lslle.w r1, r4, r1 80188ce: ee07 1a90 vmov s15, r1 80188d2: eeb8 7b67 vcvt.f64.u32 d7, s15 80188d6: 3b01 subs r3, #1 80188d8: ee17 1a90 vmov r1, s15 80188dc: 2501 movs r5, #1 80188de: f1a1 71f8 sub.w r1, r1, #32505856 @ 0x1f00000 80188e2: e7a8 b.n 8018836 <_dtoa_r+0xf6> 80188e4: 2101 movs r1, #1 80188e6: 1ad2 subs r2, r2, r3 80188e8: 1e53 subs r3, r2, #1 80188ea: 9306 str r3, [sp, #24] 80188ec: bf45 ittet mi 80188ee: f1c2 0301 rsbmi r3, r2, #1 80188f2: 9305 strmi r3, [sp, #20] 80188f4: 2300 movpl r3, #0 80188f6: 2300 movmi r3, #0 80188f8: bf4c ite mi 80188fa: 9306 strmi r3, [sp, #24] 80188fc: 9305 strpl r3, [sp, #20] 80188fe: f1b8 0f00 cmp.w r8, #0 8018902: 910c str r1, [sp, #48] @ 0x30 8018904: db18 blt.n 8018938 <_dtoa_r+0x1f8> 8018906: 9b06 ldr r3, [sp, #24] 8018908: f8cd 8028 str.w r8, [sp, #40] @ 0x28 801890c: 4443 add r3, r8 801890e: 9306 str r3, [sp, #24] 8018910: 2300 movs r3, #0 8018912: 9a07 ldr r2, [sp, #28] 8018914: 2a09 cmp r2, #9 8018916: d849 bhi.n 80189ac <_dtoa_r+0x26c> 8018918: 2a05 cmp r2, #5 801891a: bfc4 itt gt 801891c: 3a04 subgt r2, #4 801891e: 9207 strgt r2, [sp, #28] 8018920: 9a07 ldr r2, [sp, #28] 8018922: f1a2 0202 sub.w r2, r2, #2 8018926: bfcc ite gt 8018928: 2400 movgt r4, #0 801892a: 2401 movle r4, #1 801892c: 2a03 cmp r2, #3 801892e: d848 bhi.n 80189c2 <_dtoa_r+0x282> 8018930: e8df f002 tbb [pc, r2] 8018934: 3a2c2e0b .word 0x3a2c2e0b 8018938: 9b05 ldr r3, [sp, #20] 801893a: 2200 movs r2, #0 801893c: eba3 0308 sub.w r3, r3, r8 8018940: 9305 str r3, [sp, #20] 8018942: 920a str r2, [sp, #40] @ 0x28 8018944: f1c8 0300 rsb r3, r8, #0 8018948: e7e3 b.n 8018912 <_dtoa_r+0x1d2> 801894a: 2200 movs r2, #0 801894c: 9208 str r2, [sp, #32] 801894e: 9a09 ldr r2, [sp, #36] @ 0x24 8018950: 2a00 cmp r2, #0 8018952: dc39 bgt.n 80189c8 <_dtoa_r+0x288> 8018954: f04f 0b01 mov.w fp, #1 8018958: 46da mov sl, fp 801895a: 465a mov r2, fp 801895c: f8cd b024 str.w fp, [sp, #36] @ 0x24 8018960: f8d9 701c ldr.w r7, [r9, #28] 8018964: 2100 movs r1, #0 8018966: 2004 movs r0, #4 8018968: f100 0614 add.w r6, r0, #20 801896c: 4296 cmp r6, r2 801896e: d930 bls.n 80189d2 <_dtoa_r+0x292> 8018970: 6079 str r1, [r7, #4] 8018972: 4648 mov r0, r9 8018974: 9304 str r3, [sp, #16] 8018976: f000 fd39 bl 80193ec <_Balloc> 801897a: 9b04 ldr r3, [sp, #16] 801897c: 4607 mov r7, r0 801897e: 2800 cmp r0, #0 8018980: d146 bne.n 8018a10 <_dtoa_r+0x2d0> 8018982: 4b22 ldr r3, [pc, #136] @ (8018a0c <_dtoa_r+0x2cc>) 8018984: 4602 mov r2, r0 8018986: f240 11af movw r1, #431 @ 0x1af 801898a: e6f2 b.n 8018772 <_dtoa_r+0x32> 801898c: 2201 movs r2, #1 801898e: e7dd b.n 801894c <_dtoa_r+0x20c> 8018990: 2200 movs r2, #0 8018992: 9208 str r2, [sp, #32] 8018994: 9a09 ldr r2, [sp, #36] @ 0x24 8018996: eb08 0b02 add.w fp, r8, r2 801899a: f10b 0a01 add.w sl, fp, #1 801899e: 4652 mov r2, sl 80189a0: 2a01 cmp r2, #1 80189a2: bfb8 it lt 80189a4: 2201 movlt r2, #1 80189a6: e7db b.n 8018960 <_dtoa_r+0x220> 80189a8: 2201 movs r2, #1 80189aa: e7f2 b.n 8018992 <_dtoa_r+0x252> 80189ac: 2401 movs r4, #1 80189ae: 2200 movs r2, #0 80189b0: e9cd 2407 strd r2, r4, [sp, #28] 80189b4: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff 80189b8: 2100 movs r1, #0 80189ba: 46da mov sl, fp 80189bc: 2212 movs r2, #18 80189be: 9109 str r1, [sp, #36] @ 0x24 80189c0: e7ce b.n 8018960 <_dtoa_r+0x220> 80189c2: 2201 movs r2, #1 80189c4: 9208 str r2, [sp, #32] 80189c6: e7f5 b.n 80189b4 <_dtoa_r+0x274> 80189c8: f8dd b024 ldr.w fp, [sp, #36] @ 0x24 80189cc: 46da mov sl, fp 80189ce: 465a mov r2, fp 80189d0: e7c6 b.n 8018960 <_dtoa_r+0x220> 80189d2: 3101 adds r1, #1 80189d4: 0040 lsls r0, r0, #1 80189d6: e7c7 b.n 8018968 <_dtoa_r+0x228> 80189d8: 636f4361 .word 0x636f4361 80189dc: 3fd287a7 .word 0x3fd287a7 80189e0: 8b60c8b3 .word 0x8b60c8b3 80189e4: 3fc68a28 .word 0x3fc68a28 80189e8: 509f79fb .word 0x509f79fb 80189ec: 3fd34413 .word 0x3fd34413 80189f0: 0801a309 .word 0x0801a309 80189f4: 0801a320 .word 0x0801a320 80189f8: 7ff00000 .word 0x7ff00000 80189fc: 0801a305 .word 0x0801a305 8018a00: 0801a2d9 .word 0x0801a2d9 8018a04: 0801a2d8 .word 0x0801a2d8 8018a08: 0801a418 .word 0x0801a418 8018a0c: 0801a378 .word 0x0801a378 8018a10: f8d9 201c ldr.w r2, [r9, #28] 8018a14: f1ba 0f0e cmp.w sl, #14 8018a18: 6010 str r0, [r2, #0] 8018a1a: d86f bhi.n 8018afc <_dtoa_r+0x3bc> 8018a1c: 2c00 cmp r4, #0 8018a1e: d06d beq.n 8018afc <_dtoa_r+0x3bc> 8018a20: f1b8 0f00 cmp.w r8, #0 8018a24: f340 80c2 ble.w 8018bac <_dtoa_r+0x46c> 8018a28: 4aca ldr r2, [pc, #808] @ (8018d54 <_dtoa_r+0x614>) 8018a2a: f008 010f and.w r1, r8, #15 8018a2e: eb02 02c1 add.w r2, r2, r1, lsl #3 8018a32: f418 7f80 tst.w r8, #256 @ 0x100 8018a36: ed92 7b00 vldr d7, [r2] 8018a3a: ea4f 1128 mov.w r1, r8, asr #4 8018a3e: f000 80a9 beq.w 8018b94 <_dtoa_r+0x454> 8018a42: 4ac5 ldr r2, [pc, #788] @ (8018d58 <_dtoa_r+0x618>) 8018a44: ed92 6b08 vldr d6, [r2, #32] 8018a48: ee88 6b06 vdiv.f64 d6, d8, d6 8018a4c: ed8d 6b02 vstr d6, [sp, #8] 8018a50: f001 010f and.w r1, r1, #15 8018a54: 2203 movs r2, #3 8018a56: 48c0 ldr r0, [pc, #768] @ (8018d58 <_dtoa_r+0x618>) 8018a58: 2900 cmp r1, #0 8018a5a: f040 809d bne.w 8018b98 <_dtoa_r+0x458> 8018a5e: ed9d 6b02 vldr d6, [sp, #8] 8018a62: ee86 7b07 vdiv.f64 d7, d6, d7 8018a66: ed8d 7b02 vstr d7, [sp, #8] 8018a6a: 990c ldr r1, [sp, #48] @ 0x30 8018a6c: ed9d 7b02 vldr d7, [sp, #8] 8018a70: 2900 cmp r1, #0 8018a72: f000 80c1 beq.w 8018bf8 <_dtoa_r+0x4b8> 8018a76: eeb7 6b00 vmov.f64 d6, #112 @ 0x3f800000 1.0 8018a7a: eeb4 7bc6 vcmpe.f64 d7, d6 8018a7e: eef1 fa10 vmrs APSR_nzcv, fpscr 8018a82: f140 80b9 bpl.w 8018bf8 <_dtoa_r+0x4b8> 8018a86: f1ba 0f00 cmp.w sl, #0 8018a8a: f000 80b5 beq.w 8018bf8 <_dtoa_r+0x4b8> 8018a8e: f1bb 0f00 cmp.w fp, #0 8018a92: dd31 ble.n 8018af8 <_dtoa_r+0x3b8> 8018a94: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 8018a98: ee27 7b06 vmul.f64 d7, d7, d6 8018a9c: ed8d 7b02 vstr d7, [sp, #8] 8018aa0: f108 31ff add.w r1, r8, #4294967295 @ 0xffffffff 8018aa4: 9104 str r1, [sp, #16] 8018aa6: 3201 adds r2, #1 8018aa8: 465c mov r4, fp 8018aaa: ed9d 6b02 vldr d6, [sp, #8] 8018aae: eeb1 5b0c vmov.f64 d5, #28 @ 0x40e00000 7.0 8018ab2: ee07 2a90 vmov s15, r2 8018ab6: eeb8 7be7 vcvt.f64.s32 d7, s15 8018aba: eea7 5b06 vfma.f64 d5, d7, d6 8018abe: ee15 2a90 vmov r2, s11 8018ac2: ec51 0b15 vmov r0, r1, d5 8018ac6: f1a2 7150 sub.w r1, r2, #54525952 @ 0x3400000 8018aca: 2c00 cmp r4, #0 8018acc: f040 8098 bne.w 8018c00 <_dtoa_r+0x4c0> 8018ad0: eeb1 7b04 vmov.f64 d7, #20 @ 0x40a00000 5.0 8018ad4: ee36 6b47 vsub.f64 d6, d6, d7 8018ad8: ec41 0b17 vmov d7, r0, r1 8018adc: eeb4 6bc7 vcmpe.f64 d6, d7 8018ae0: eef1 fa10 vmrs APSR_nzcv, fpscr 8018ae4: f300 8261 bgt.w 8018faa <_dtoa_r+0x86a> 8018ae8: eeb1 7b47 vneg.f64 d7, d7 8018aec: eeb4 6bc7 vcmpe.f64 d6, d7 8018af0: eef1 fa10 vmrs APSR_nzcv, fpscr 8018af4: f100 80f5 bmi.w 8018ce2 <_dtoa_r+0x5a2> 8018af8: ed8d 8b02 vstr d8, [sp, #8] 8018afc: 9a0f ldr r2, [sp, #60] @ 0x3c 8018afe: 2a00 cmp r2, #0 8018b00: f2c0 812c blt.w 8018d5c <_dtoa_r+0x61c> 8018b04: f1b8 0f0e cmp.w r8, #14 8018b08: f300 8128 bgt.w 8018d5c <_dtoa_r+0x61c> 8018b0c: 4b91 ldr r3, [pc, #580] @ (8018d54 <_dtoa_r+0x614>) 8018b0e: eb03 03c8 add.w r3, r3, r8, lsl #3 8018b12: ed93 6b00 vldr d6, [r3] 8018b16: 9b09 ldr r3, [sp, #36] @ 0x24 8018b18: 2b00 cmp r3, #0 8018b1a: da03 bge.n 8018b24 <_dtoa_r+0x3e4> 8018b1c: f1ba 0f00 cmp.w sl, #0 8018b20: f340 80d2 ble.w 8018cc8 <_dtoa_r+0x588> 8018b24: eeb2 4b04 vmov.f64 d4, #36 @ 0x41200000 10.0 8018b28: ed9d 7b02 vldr d7, [sp, #8] 8018b2c: 463e mov r6, r7 8018b2e: ee87 5b06 vdiv.f64 d5, d7, d6 8018b32: eebd 5bc5 vcvt.s32.f64 s10, d5 8018b36: ee15 3a10 vmov r3, s10 8018b3a: 3330 adds r3, #48 @ 0x30 8018b3c: f806 3b01 strb.w r3, [r6], #1 8018b40: 1bf3 subs r3, r6, r7 8018b42: 459a cmp sl, r3 8018b44: eeb8 3bc5 vcvt.f64.s32 d3, s10 8018b48: eea3 7b46 vfms.f64 d7, d3, d6 8018b4c: f040 80f8 bne.w 8018d40 <_dtoa_r+0x600> 8018b50: ee37 7b07 vadd.f64 d7, d7, d7 8018b54: eeb4 7bc6 vcmpe.f64 d7, d6 8018b58: eef1 fa10 vmrs APSR_nzcv, fpscr 8018b5c: f300 80dd bgt.w 8018d1a <_dtoa_r+0x5da> 8018b60: eeb4 7b46 vcmp.f64 d7, d6 8018b64: eef1 fa10 vmrs APSR_nzcv, fpscr 8018b68: d104 bne.n 8018b74 <_dtoa_r+0x434> 8018b6a: ee15 3a10 vmov r3, s10 8018b6e: 07db lsls r3, r3, #31 8018b70: f100 80d3 bmi.w 8018d1a <_dtoa_r+0x5da> 8018b74: 9901 ldr r1, [sp, #4] 8018b76: 4648 mov r0, r9 8018b78: f000 fc78 bl 801946c <_Bfree> 8018b7c: 2300 movs r3, #0 8018b7e: 9a0d ldr r2, [sp, #52] @ 0x34 8018b80: 7033 strb r3, [r6, #0] 8018b82: f108 0301 add.w r3, r8, #1 8018b86: 6013 str r3, [r2, #0] 8018b88: 9b1d ldr r3, [sp, #116] @ 0x74 8018b8a: 2b00 cmp r3, #0 8018b8c: f000 8304 beq.w 8019198 <_dtoa_r+0xa58> 8018b90: 601e str r6, [r3, #0] 8018b92: e301 b.n 8019198 <_dtoa_r+0xa58> 8018b94: 2202 movs r2, #2 8018b96: e75e b.n 8018a56 <_dtoa_r+0x316> 8018b98: 07cc lsls r4, r1, #31 8018b9a: d504 bpl.n 8018ba6 <_dtoa_r+0x466> 8018b9c: ed90 6b00 vldr d6, [r0] 8018ba0: 3201 adds r2, #1 8018ba2: ee27 7b06 vmul.f64 d7, d7, d6 8018ba6: 1049 asrs r1, r1, #1 8018ba8: 3008 adds r0, #8 8018baa: e755 b.n 8018a58 <_dtoa_r+0x318> 8018bac: d022 beq.n 8018bf4 <_dtoa_r+0x4b4> 8018bae: f1c8 0100 rsb r1, r8, #0 8018bb2: 4a68 ldr r2, [pc, #416] @ (8018d54 <_dtoa_r+0x614>) 8018bb4: f001 000f and.w r0, r1, #15 8018bb8: eb02 02c0 add.w r2, r2, r0, lsl #3 8018bbc: ed92 7b00 vldr d7, [r2] 8018bc0: ee28 7b07 vmul.f64 d7, d8, d7 8018bc4: ed8d 7b02 vstr d7, [sp, #8] 8018bc8: 4863 ldr r0, [pc, #396] @ (8018d58 <_dtoa_r+0x618>) 8018bca: 1109 asrs r1, r1, #4 8018bcc: 2400 movs r4, #0 8018bce: 2202 movs r2, #2 8018bd0: b929 cbnz r1, 8018bde <_dtoa_r+0x49e> 8018bd2: 2c00 cmp r4, #0 8018bd4: f43f af49 beq.w 8018a6a <_dtoa_r+0x32a> 8018bd8: ed8d 7b02 vstr d7, [sp, #8] 8018bdc: e745 b.n 8018a6a <_dtoa_r+0x32a> 8018bde: 07ce lsls r6, r1, #31 8018be0: d505 bpl.n 8018bee <_dtoa_r+0x4ae> 8018be2: ed90 6b00 vldr d6, [r0] 8018be6: 3201 adds r2, #1 8018be8: 2401 movs r4, #1 8018bea: ee27 7b06 vmul.f64 d7, d7, d6 8018bee: 1049 asrs r1, r1, #1 8018bf0: 3008 adds r0, #8 8018bf2: e7ed b.n 8018bd0 <_dtoa_r+0x490> 8018bf4: 2202 movs r2, #2 8018bf6: e738 b.n 8018a6a <_dtoa_r+0x32a> 8018bf8: f8cd 8010 str.w r8, [sp, #16] 8018bfc: 4654 mov r4, sl 8018bfe: e754 b.n 8018aaa <_dtoa_r+0x36a> 8018c00: 4a54 ldr r2, [pc, #336] @ (8018d54 <_dtoa_r+0x614>) 8018c02: eb02 02c4 add.w r2, r2, r4, lsl #3 8018c06: ed12 4b02 vldr d4, [r2, #-8] 8018c0a: 9a08 ldr r2, [sp, #32] 8018c0c: ec41 0b17 vmov d7, r0, r1 8018c10: 443c add r4, r7 8018c12: b34a cbz r2, 8018c68 <_dtoa_r+0x528> 8018c14: eeb6 3b00 vmov.f64 d3, #96 @ 0x3f000000 0.5 8018c18: eeb7 2b00 vmov.f64 d2, #112 @ 0x3f800000 1.0 8018c1c: 463e mov r6, r7 8018c1e: ee83 5b04 vdiv.f64 d5, d3, d4 8018c22: eeb2 3b04 vmov.f64 d3, #36 @ 0x41200000 10.0 8018c26: ee35 7b47 vsub.f64 d7, d5, d7 8018c2a: eefd 4bc6 vcvt.s32.f64 s9, d6 8018c2e: ee14 2a90 vmov r2, s9 8018c32: eeb8 5be4 vcvt.f64.s32 d5, s9 8018c36: 3230 adds r2, #48 @ 0x30 8018c38: ee36 6b45 vsub.f64 d6, d6, d5 8018c3c: eeb4 6bc7 vcmpe.f64 d6, d7 8018c40: eef1 fa10 vmrs APSR_nzcv, fpscr 8018c44: f806 2b01 strb.w r2, [r6], #1 8018c48: d438 bmi.n 8018cbc <_dtoa_r+0x57c> 8018c4a: ee32 5b46 vsub.f64 d5, d2, d6 8018c4e: eeb4 5bc7 vcmpe.f64 d5, d7 8018c52: eef1 fa10 vmrs APSR_nzcv, fpscr 8018c56: d462 bmi.n 8018d1e <_dtoa_r+0x5de> 8018c58: 42a6 cmp r6, r4 8018c5a: f43f af4d beq.w 8018af8 <_dtoa_r+0x3b8> 8018c5e: ee27 7b03 vmul.f64 d7, d7, d3 8018c62: ee26 6b03 vmul.f64 d6, d6, d3 8018c66: e7e0 b.n 8018c2a <_dtoa_r+0x4ea> 8018c68: 4621 mov r1, r4 8018c6a: 463e mov r6, r7 8018c6c: ee27 7b04 vmul.f64 d7, d7, d4 8018c70: eeb2 3b04 vmov.f64 d3, #36 @ 0x41200000 10.0 8018c74: eefd 4bc6 vcvt.s32.f64 s9, d6 8018c78: ee14 2a90 vmov r2, s9 8018c7c: 3230 adds r2, #48 @ 0x30 8018c7e: f806 2b01 strb.w r2, [r6], #1 8018c82: 42a6 cmp r6, r4 8018c84: eeb8 5be4 vcvt.f64.s32 d5, s9 8018c88: ee36 6b45 vsub.f64 d6, d6, d5 8018c8c: d119 bne.n 8018cc2 <_dtoa_r+0x582> 8018c8e: eeb6 5b00 vmov.f64 d5, #96 @ 0x3f000000 0.5 8018c92: ee37 4b05 vadd.f64 d4, d7, d5 8018c96: eeb4 6bc4 vcmpe.f64 d6, d4 8018c9a: eef1 fa10 vmrs APSR_nzcv, fpscr 8018c9e: dc3e bgt.n 8018d1e <_dtoa_r+0x5de> 8018ca0: ee35 5b47 vsub.f64 d5, d5, d7 8018ca4: eeb4 6bc5 vcmpe.f64 d6, d5 8018ca8: eef1 fa10 vmrs APSR_nzcv, fpscr 8018cac: f57f af24 bpl.w 8018af8 <_dtoa_r+0x3b8> 8018cb0: 460e mov r6, r1 8018cb2: 3901 subs r1, #1 8018cb4: f816 3c01 ldrb.w r3, [r6, #-1] 8018cb8: 2b30 cmp r3, #48 @ 0x30 8018cba: d0f9 beq.n 8018cb0 <_dtoa_r+0x570> 8018cbc: f8dd 8010 ldr.w r8, [sp, #16] 8018cc0: e758 b.n 8018b74 <_dtoa_r+0x434> 8018cc2: ee26 6b03 vmul.f64 d6, d6, d3 8018cc6: e7d5 b.n 8018c74 <_dtoa_r+0x534> 8018cc8: d10b bne.n 8018ce2 <_dtoa_r+0x5a2> 8018cca: eeb1 7b04 vmov.f64 d7, #20 @ 0x40a00000 5.0 8018cce: ee26 6b07 vmul.f64 d6, d6, d7 8018cd2: ed9d 7b02 vldr d7, [sp, #8] 8018cd6: eeb4 6bc7 vcmpe.f64 d6, d7 8018cda: eef1 fa10 vmrs APSR_nzcv, fpscr 8018cde: f2c0 8161 blt.w 8018fa4 <_dtoa_r+0x864> 8018ce2: 2400 movs r4, #0 8018ce4: 4625 mov r5, r4 8018ce6: 9b09 ldr r3, [sp, #36] @ 0x24 8018ce8: 43db mvns r3, r3 8018cea: 9304 str r3, [sp, #16] 8018cec: 463e mov r6, r7 8018cee: f04f 0800 mov.w r8, #0 8018cf2: 4621 mov r1, r4 8018cf4: 4648 mov r0, r9 8018cf6: f000 fbb9 bl 801946c <_Bfree> 8018cfa: 2d00 cmp r5, #0 8018cfc: d0de beq.n 8018cbc <_dtoa_r+0x57c> 8018cfe: f1b8 0f00 cmp.w r8, #0 8018d02: d005 beq.n 8018d10 <_dtoa_r+0x5d0> 8018d04: 45a8 cmp r8, r5 8018d06: d003 beq.n 8018d10 <_dtoa_r+0x5d0> 8018d08: 4641 mov r1, r8 8018d0a: 4648 mov r0, r9 8018d0c: f000 fbae bl 801946c <_Bfree> 8018d10: 4629 mov r1, r5 8018d12: 4648 mov r0, r9 8018d14: f000 fbaa bl 801946c <_Bfree> 8018d18: e7d0 b.n 8018cbc <_dtoa_r+0x57c> 8018d1a: f8cd 8010 str.w r8, [sp, #16] 8018d1e: 4633 mov r3, r6 8018d20: 461e mov r6, r3 8018d22: f813 2d01 ldrb.w r2, [r3, #-1]! 8018d26: 2a39 cmp r2, #57 @ 0x39 8018d28: d106 bne.n 8018d38 <_dtoa_r+0x5f8> 8018d2a: 429f cmp r7, r3 8018d2c: d1f8 bne.n 8018d20 <_dtoa_r+0x5e0> 8018d2e: 9a04 ldr r2, [sp, #16] 8018d30: 3201 adds r2, #1 8018d32: 9204 str r2, [sp, #16] 8018d34: 2230 movs r2, #48 @ 0x30 8018d36: 703a strb r2, [r7, #0] 8018d38: 781a ldrb r2, [r3, #0] 8018d3a: 3201 adds r2, #1 8018d3c: 701a strb r2, [r3, #0] 8018d3e: e7bd b.n 8018cbc <_dtoa_r+0x57c> 8018d40: ee27 7b04 vmul.f64 d7, d7, d4 8018d44: eeb5 7b40 vcmp.f64 d7, #0.0 8018d48: eef1 fa10 vmrs APSR_nzcv, fpscr 8018d4c: f47f aeef bne.w 8018b2e <_dtoa_r+0x3ee> 8018d50: e710 b.n 8018b74 <_dtoa_r+0x434> 8018d52: bf00 nop 8018d54: 0801a418 .word 0x0801a418 8018d58: 0801a3f0 .word 0x0801a3f0 8018d5c: 9908 ldr r1, [sp, #32] 8018d5e: 2900 cmp r1, #0 8018d60: f000 80e3 beq.w 8018f2a <_dtoa_r+0x7ea> 8018d64: 9907 ldr r1, [sp, #28] 8018d66: 2901 cmp r1, #1 8018d68: f300 80c8 bgt.w 8018efc <_dtoa_r+0x7bc> 8018d6c: 2d00 cmp r5, #0 8018d6e: f000 80c1 beq.w 8018ef4 <_dtoa_r+0x7b4> 8018d72: f202 4233 addw r2, r2, #1075 @ 0x433 8018d76: 9e05 ldr r6, [sp, #20] 8018d78: 461c mov r4, r3 8018d7a: 9304 str r3, [sp, #16] 8018d7c: 9b05 ldr r3, [sp, #20] 8018d7e: 4413 add r3, r2 8018d80: 9305 str r3, [sp, #20] 8018d82: 9b06 ldr r3, [sp, #24] 8018d84: 2101 movs r1, #1 8018d86: 4413 add r3, r2 8018d88: 4648 mov r0, r9 8018d8a: 9306 str r3, [sp, #24] 8018d8c: f000 fc22 bl 80195d4 <__i2b> 8018d90: 9b04 ldr r3, [sp, #16] 8018d92: 4605 mov r5, r0 8018d94: b166 cbz r6, 8018db0 <_dtoa_r+0x670> 8018d96: 9a06 ldr r2, [sp, #24] 8018d98: 2a00 cmp r2, #0 8018d9a: dd09 ble.n 8018db0 <_dtoa_r+0x670> 8018d9c: 42b2 cmp r2, r6 8018d9e: 9905 ldr r1, [sp, #20] 8018da0: bfa8 it ge 8018da2: 4632 movge r2, r6 8018da4: 1a89 subs r1, r1, r2 8018da6: 9105 str r1, [sp, #20] 8018da8: 9906 ldr r1, [sp, #24] 8018daa: 1ab6 subs r6, r6, r2 8018dac: 1a8a subs r2, r1, r2 8018dae: 9206 str r2, [sp, #24] 8018db0: b1fb cbz r3, 8018df2 <_dtoa_r+0x6b2> 8018db2: 9a08 ldr r2, [sp, #32] 8018db4: 2a00 cmp r2, #0 8018db6: f000 80bc beq.w 8018f32 <_dtoa_r+0x7f2> 8018dba: b19c cbz r4, 8018de4 <_dtoa_r+0x6a4> 8018dbc: 4629 mov r1, r5 8018dbe: 4622 mov r2, r4 8018dc0: 4648 mov r0, r9 8018dc2: 930b str r3, [sp, #44] @ 0x2c 8018dc4: f000 fcc6 bl 8019754 <__pow5mult> 8018dc8: 9a01 ldr r2, [sp, #4] 8018dca: 4601 mov r1, r0 8018dcc: 4605 mov r5, r0 8018dce: 4648 mov r0, r9 8018dd0: f000 fc16 bl 8019600 <__multiply> 8018dd4: 9901 ldr r1, [sp, #4] 8018dd6: 9004 str r0, [sp, #16] 8018dd8: 4648 mov r0, r9 8018dda: f000 fb47 bl 801946c <_Bfree> 8018dde: 9a04 ldr r2, [sp, #16] 8018de0: 9b0b ldr r3, [sp, #44] @ 0x2c 8018de2: 9201 str r2, [sp, #4] 8018de4: 1b1a subs r2, r3, r4 8018de6: d004 beq.n 8018df2 <_dtoa_r+0x6b2> 8018de8: 9901 ldr r1, [sp, #4] 8018dea: 4648 mov r0, r9 8018dec: f000 fcb2 bl 8019754 <__pow5mult> 8018df0: 9001 str r0, [sp, #4] 8018df2: 2101 movs r1, #1 8018df4: 4648 mov r0, r9 8018df6: f000 fbed bl 80195d4 <__i2b> 8018dfa: 9b0a ldr r3, [sp, #40] @ 0x28 8018dfc: 4604 mov r4, r0 8018dfe: 2b00 cmp r3, #0 8018e00: f000 81d0 beq.w 80191a4 <_dtoa_r+0xa64> 8018e04: 461a mov r2, r3 8018e06: 4601 mov r1, r0 8018e08: 4648 mov r0, r9 8018e0a: f000 fca3 bl 8019754 <__pow5mult> 8018e0e: 9b07 ldr r3, [sp, #28] 8018e10: 2b01 cmp r3, #1 8018e12: 4604 mov r4, r0 8018e14: f300 8095 bgt.w 8018f42 <_dtoa_r+0x802> 8018e18: 9b02 ldr r3, [sp, #8] 8018e1a: 2b00 cmp r3, #0 8018e1c: f040 808b bne.w 8018f36 <_dtoa_r+0x7f6> 8018e20: 9b03 ldr r3, [sp, #12] 8018e22: f3c3 0213 ubfx r2, r3, #0, #20 8018e26: 2a00 cmp r2, #0 8018e28: f040 8087 bne.w 8018f3a <_dtoa_r+0x7fa> 8018e2c: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 8018e30: 0d12 lsrs r2, r2, #20 8018e32: 0512 lsls r2, r2, #20 8018e34: 2a00 cmp r2, #0 8018e36: f000 8082 beq.w 8018f3e <_dtoa_r+0x7fe> 8018e3a: 9b05 ldr r3, [sp, #20] 8018e3c: 3301 adds r3, #1 8018e3e: 9305 str r3, [sp, #20] 8018e40: 9b06 ldr r3, [sp, #24] 8018e42: 3301 adds r3, #1 8018e44: 9306 str r3, [sp, #24] 8018e46: 2301 movs r3, #1 8018e48: 930b str r3, [sp, #44] @ 0x2c 8018e4a: 9b0a ldr r3, [sp, #40] @ 0x28 8018e4c: 2b00 cmp r3, #0 8018e4e: f000 81af beq.w 80191b0 <_dtoa_r+0xa70> 8018e52: 6922 ldr r2, [r4, #16] 8018e54: eb04 0282 add.w r2, r4, r2, lsl #2 8018e58: 6910 ldr r0, [r2, #16] 8018e5a: f000 fb6f bl 801953c <__hi0bits> 8018e5e: f1c0 0020 rsb r0, r0, #32 8018e62: 9b06 ldr r3, [sp, #24] 8018e64: 4418 add r0, r3 8018e66: f010 001f ands.w r0, r0, #31 8018e6a: d076 beq.n 8018f5a <_dtoa_r+0x81a> 8018e6c: f1c0 0220 rsb r2, r0, #32 8018e70: 2a04 cmp r2, #4 8018e72: dd69 ble.n 8018f48 <_dtoa_r+0x808> 8018e74: 9b05 ldr r3, [sp, #20] 8018e76: f1c0 001c rsb r0, r0, #28 8018e7a: 4403 add r3, r0 8018e7c: 9305 str r3, [sp, #20] 8018e7e: 9b06 ldr r3, [sp, #24] 8018e80: 4406 add r6, r0 8018e82: 4403 add r3, r0 8018e84: 9306 str r3, [sp, #24] 8018e86: 9b05 ldr r3, [sp, #20] 8018e88: 2b00 cmp r3, #0 8018e8a: dd05 ble.n 8018e98 <_dtoa_r+0x758> 8018e8c: 9901 ldr r1, [sp, #4] 8018e8e: 461a mov r2, r3 8018e90: 4648 mov r0, r9 8018e92: f000 fcb9 bl 8019808 <__lshift> 8018e96: 9001 str r0, [sp, #4] 8018e98: 9b06 ldr r3, [sp, #24] 8018e9a: 2b00 cmp r3, #0 8018e9c: dd05 ble.n 8018eaa <_dtoa_r+0x76a> 8018e9e: 4621 mov r1, r4 8018ea0: 461a mov r2, r3 8018ea2: 4648 mov r0, r9 8018ea4: f000 fcb0 bl 8019808 <__lshift> 8018ea8: 4604 mov r4, r0 8018eaa: 9b0c ldr r3, [sp, #48] @ 0x30 8018eac: 2b00 cmp r3, #0 8018eae: d056 beq.n 8018f5e <_dtoa_r+0x81e> 8018eb0: 9801 ldr r0, [sp, #4] 8018eb2: 4621 mov r1, r4 8018eb4: f000 fd14 bl 80198e0 <__mcmp> 8018eb8: 2800 cmp r0, #0 8018eba: da50 bge.n 8018f5e <_dtoa_r+0x81e> 8018ebc: f108 33ff add.w r3, r8, #4294967295 @ 0xffffffff 8018ec0: 9304 str r3, [sp, #16] 8018ec2: 9901 ldr r1, [sp, #4] 8018ec4: 2300 movs r3, #0 8018ec6: 220a movs r2, #10 8018ec8: 4648 mov r0, r9 8018eca: f000 faf1 bl 80194b0 <__multadd> 8018ece: 9b08 ldr r3, [sp, #32] 8018ed0: 9001 str r0, [sp, #4] 8018ed2: 2b00 cmp r3, #0 8018ed4: f000 816e beq.w 80191b4 <_dtoa_r+0xa74> 8018ed8: 4629 mov r1, r5 8018eda: 2300 movs r3, #0 8018edc: 220a movs r2, #10 8018ede: 4648 mov r0, r9 8018ee0: f000 fae6 bl 80194b0 <__multadd> 8018ee4: f1bb 0f00 cmp.w fp, #0 8018ee8: 4605 mov r5, r0 8018eea: dc64 bgt.n 8018fb6 <_dtoa_r+0x876> 8018eec: 9b07 ldr r3, [sp, #28] 8018eee: 2b02 cmp r3, #2 8018ef0: dc3e bgt.n 8018f70 <_dtoa_r+0x830> 8018ef2: e060 b.n 8018fb6 <_dtoa_r+0x876> 8018ef4: 9a0e ldr r2, [sp, #56] @ 0x38 8018ef6: f1c2 0236 rsb r2, r2, #54 @ 0x36 8018efa: e73c b.n 8018d76 <_dtoa_r+0x636> 8018efc: f10a 34ff add.w r4, sl, #4294967295 @ 0xffffffff 8018f00: 42a3 cmp r3, r4 8018f02: bfbf itttt lt 8018f04: 1ae2 sublt r2, r4, r3 8018f06: 9b0a ldrlt r3, [sp, #40] @ 0x28 8018f08: 189b addlt r3, r3, r2 8018f0a: 930a strlt r3, [sp, #40] @ 0x28 8018f0c: bfae itee ge 8018f0e: 1b1c subge r4, r3, r4 8018f10: 4623 movlt r3, r4 8018f12: 2400 movlt r4, #0 8018f14: f1ba 0f00 cmp.w sl, #0 8018f18: bfb5 itete lt 8018f1a: 9a05 ldrlt r2, [sp, #20] 8018f1c: 9e05 ldrge r6, [sp, #20] 8018f1e: eba2 060a sublt.w r6, r2, sl 8018f22: 4652 movge r2, sl 8018f24: bfb8 it lt 8018f26: 2200 movlt r2, #0 8018f28: e727 b.n 8018d7a <_dtoa_r+0x63a> 8018f2a: 9e05 ldr r6, [sp, #20] 8018f2c: 9d08 ldr r5, [sp, #32] 8018f2e: 461c mov r4, r3 8018f30: e730 b.n 8018d94 <_dtoa_r+0x654> 8018f32: 461a mov r2, r3 8018f34: e758 b.n 8018de8 <_dtoa_r+0x6a8> 8018f36: 2300 movs r3, #0 8018f38: e786 b.n 8018e48 <_dtoa_r+0x708> 8018f3a: 9b02 ldr r3, [sp, #8] 8018f3c: e784 b.n 8018e48 <_dtoa_r+0x708> 8018f3e: 920b str r2, [sp, #44] @ 0x2c 8018f40: e783 b.n 8018e4a <_dtoa_r+0x70a> 8018f42: 2300 movs r3, #0 8018f44: 930b str r3, [sp, #44] @ 0x2c 8018f46: e784 b.n 8018e52 <_dtoa_r+0x712> 8018f48: d09d beq.n 8018e86 <_dtoa_r+0x746> 8018f4a: 9b05 ldr r3, [sp, #20] 8018f4c: 321c adds r2, #28 8018f4e: 4413 add r3, r2 8018f50: 9305 str r3, [sp, #20] 8018f52: 9b06 ldr r3, [sp, #24] 8018f54: 4416 add r6, r2 8018f56: 4413 add r3, r2 8018f58: e794 b.n 8018e84 <_dtoa_r+0x744> 8018f5a: 4602 mov r2, r0 8018f5c: e7f5 b.n 8018f4a <_dtoa_r+0x80a> 8018f5e: f1ba 0f00 cmp.w sl, #0 8018f62: f8cd 8010 str.w r8, [sp, #16] 8018f66: 46d3 mov fp, sl 8018f68: dc21 bgt.n 8018fae <_dtoa_r+0x86e> 8018f6a: 9b07 ldr r3, [sp, #28] 8018f6c: 2b02 cmp r3, #2 8018f6e: dd1e ble.n 8018fae <_dtoa_r+0x86e> 8018f70: f1bb 0f00 cmp.w fp, #0 8018f74: f47f aeb7 bne.w 8018ce6 <_dtoa_r+0x5a6> 8018f78: 4621 mov r1, r4 8018f7a: 465b mov r3, fp 8018f7c: 2205 movs r2, #5 8018f7e: 4648 mov r0, r9 8018f80: f000 fa96 bl 80194b0 <__multadd> 8018f84: 4601 mov r1, r0 8018f86: 4604 mov r4, r0 8018f88: 9801 ldr r0, [sp, #4] 8018f8a: f000 fca9 bl 80198e0 <__mcmp> 8018f8e: 2800 cmp r0, #0 8018f90: f77f aea9 ble.w 8018ce6 <_dtoa_r+0x5a6> 8018f94: 463e mov r6, r7 8018f96: 2331 movs r3, #49 @ 0x31 8018f98: f806 3b01 strb.w r3, [r6], #1 8018f9c: 9b04 ldr r3, [sp, #16] 8018f9e: 3301 adds r3, #1 8018fa0: 9304 str r3, [sp, #16] 8018fa2: e6a4 b.n 8018cee <_dtoa_r+0x5ae> 8018fa4: f8cd 8010 str.w r8, [sp, #16] 8018fa8: 4654 mov r4, sl 8018faa: 4625 mov r5, r4 8018fac: e7f2 b.n 8018f94 <_dtoa_r+0x854> 8018fae: 9b08 ldr r3, [sp, #32] 8018fb0: 2b00 cmp r3, #0 8018fb2: f000 8103 beq.w 80191bc <_dtoa_r+0xa7c> 8018fb6: 2e00 cmp r6, #0 8018fb8: dd05 ble.n 8018fc6 <_dtoa_r+0x886> 8018fba: 4629 mov r1, r5 8018fbc: 4632 mov r2, r6 8018fbe: 4648 mov r0, r9 8018fc0: f000 fc22 bl 8019808 <__lshift> 8018fc4: 4605 mov r5, r0 8018fc6: 9b0b ldr r3, [sp, #44] @ 0x2c 8018fc8: 2b00 cmp r3, #0 8018fca: d058 beq.n 801907e <_dtoa_r+0x93e> 8018fcc: 6869 ldr r1, [r5, #4] 8018fce: 4648 mov r0, r9 8018fd0: f000 fa0c bl 80193ec <_Balloc> 8018fd4: 4606 mov r6, r0 8018fd6: b928 cbnz r0, 8018fe4 <_dtoa_r+0x8a4> 8018fd8: 4b82 ldr r3, [pc, #520] @ (80191e4 <_dtoa_r+0xaa4>) 8018fda: 4602 mov r2, r0 8018fdc: f240 21ef movw r1, #751 @ 0x2ef 8018fe0: f7ff bbc7 b.w 8018772 <_dtoa_r+0x32> 8018fe4: 692a ldr r2, [r5, #16] 8018fe6: 3202 adds r2, #2 8018fe8: 0092 lsls r2, r2, #2 8018fea: f105 010c add.w r1, r5, #12 8018fee: 300c adds r0, #12 8018ff0: f7ff fb0f bl 8018612 8018ff4: 2201 movs r2, #1 8018ff6: 4631 mov r1, r6 8018ff8: 4648 mov r0, r9 8018ffa: f000 fc05 bl 8019808 <__lshift> 8018ffe: 1c7b adds r3, r7, #1 8019000: 9305 str r3, [sp, #20] 8019002: eb07 030b add.w r3, r7, fp 8019006: 9309 str r3, [sp, #36] @ 0x24 8019008: 9b02 ldr r3, [sp, #8] 801900a: f003 0301 and.w r3, r3, #1 801900e: 46a8 mov r8, r5 8019010: 9308 str r3, [sp, #32] 8019012: 4605 mov r5, r0 8019014: 9b05 ldr r3, [sp, #20] 8019016: 9801 ldr r0, [sp, #4] 8019018: 4621 mov r1, r4 801901a: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff 801901e: f7ff fb06 bl 801862e 8019022: 4641 mov r1, r8 8019024: 9002 str r0, [sp, #8] 8019026: f100 0a30 add.w sl, r0, #48 @ 0x30 801902a: 9801 ldr r0, [sp, #4] 801902c: f000 fc58 bl 80198e0 <__mcmp> 8019030: 462a mov r2, r5 8019032: 9006 str r0, [sp, #24] 8019034: 4621 mov r1, r4 8019036: 4648 mov r0, r9 8019038: f000 fc6e bl 8019918 <__mdiff> 801903c: 68c2 ldr r2, [r0, #12] 801903e: 4606 mov r6, r0 8019040: b9fa cbnz r2, 8019082 <_dtoa_r+0x942> 8019042: 4601 mov r1, r0 8019044: 9801 ldr r0, [sp, #4] 8019046: f000 fc4b bl 80198e0 <__mcmp> 801904a: 4602 mov r2, r0 801904c: 4631 mov r1, r6 801904e: 4648 mov r0, r9 8019050: 920a str r2, [sp, #40] @ 0x28 8019052: f000 fa0b bl 801946c <_Bfree> 8019056: 9b07 ldr r3, [sp, #28] 8019058: 9a0a ldr r2, [sp, #40] @ 0x28 801905a: 9e05 ldr r6, [sp, #20] 801905c: ea43 0102 orr.w r1, r3, r2 8019060: 9b08 ldr r3, [sp, #32] 8019062: 4319 orrs r1, r3 8019064: d10f bne.n 8019086 <_dtoa_r+0x946> 8019066: f1ba 0f39 cmp.w sl, #57 @ 0x39 801906a: d028 beq.n 80190be <_dtoa_r+0x97e> 801906c: 9b06 ldr r3, [sp, #24] 801906e: 2b00 cmp r3, #0 8019070: dd02 ble.n 8019078 <_dtoa_r+0x938> 8019072: 9b02 ldr r3, [sp, #8] 8019074: f103 0a31 add.w sl, r3, #49 @ 0x31 8019078: f88b a000 strb.w sl, [fp] 801907c: e639 b.n 8018cf2 <_dtoa_r+0x5b2> 801907e: 4628 mov r0, r5 8019080: e7bd b.n 8018ffe <_dtoa_r+0x8be> 8019082: 2201 movs r2, #1 8019084: e7e2 b.n 801904c <_dtoa_r+0x90c> 8019086: 9b06 ldr r3, [sp, #24] 8019088: 2b00 cmp r3, #0 801908a: db04 blt.n 8019096 <_dtoa_r+0x956> 801908c: 9907 ldr r1, [sp, #28] 801908e: 430b orrs r3, r1 8019090: 9908 ldr r1, [sp, #32] 8019092: 430b orrs r3, r1 8019094: d120 bne.n 80190d8 <_dtoa_r+0x998> 8019096: 2a00 cmp r2, #0 8019098: ddee ble.n 8019078 <_dtoa_r+0x938> 801909a: 9901 ldr r1, [sp, #4] 801909c: 2201 movs r2, #1 801909e: 4648 mov r0, r9 80190a0: f000 fbb2 bl 8019808 <__lshift> 80190a4: 4621 mov r1, r4 80190a6: 9001 str r0, [sp, #4] 80190a8: f000 fc1a bl 80198e0 <__mcmp> 80190ac: 2800 cmp r0, #0 80190ae: dc03 bgt.n 80190b8 <_dtoa_r+0x978> 80190b0: d1e2 bne.n 8019078 <_dtoa_r+0x938> 80190b2: f01a 0f01 tst.w sl, #1 80190b6: d0df beq.n 8019078 <_dtoa_r+0x938> 80190b8: f1ba 0f39 cmp.w sl, #57 @ 0x39 80190bc: d1d9 bne.n 8019072 <_dtoa_r+0x932> 80190be: 2339 movs r3, #57 @ 0x39 80190c0: f88b 3000 strb.w r3, [fp] 80190c4: 4633 mov r3, r6 80190c6: 461e mov r6, r3 80190c8: 3b01 subs r3, #1 80190ca: f816 2c01 ldrb.w r2, [r6, #-1] 80190ce: 2a39 cmp r2, #57 @ 0x39 80190d0: d053 beq.n 801917a <_dtoa_r+0xa3a> 80190d2: 3201 adds r2, #1 80190d4: 701a strb r2, [r3, #0] 80190d6: e60c b.n 8018cf2 <_dtoa_r+0x5b2> 80190d8: 2a00 cmp r2, #0 80190da: dd07 ble.n 80190ec <_dtoa_r+0x9ac> 80190dc: f1ba 0f39 cmp.w sl, #57 @ 0x39 80190e0: d0ed beq.n 80190be <_dtoa_r+0x97e> 80190e2: f10a 0301 add.w r3, sl, #1 80190e6: f88b 3000 strb.w r3, [fp] 80190ea: e602 b.n 8018cf2 <_dtoa_r+0x5b2> 80190ec: 9b05 ldr r3, [sp, #20] 80190ee: 9a05 ldr r2, [sp, #20] 80190f0: f803 ac01 strb.w sl, [r3, #-1] 80190f4: 9b09 ldr r3, [sp, #36] @ 0x24 80190f6: 4293 cmp r3, r2 80190f8: d029 beq.n 801914e <_dtoa_r+0xa0e> 80190fa: 9901 ldr r1, [sp, #4] 80190fc: 2300 movs r3, #0 80190fe: 220a movs r2, #10 8019100: 4648 mov r0, r9 8019102: f000 f9d5 bl 80194b0 <__multadd> 8019106: 45a8 cmp r8, r5 8019108: 9001 str r0, [sp, #4] 801910a: f04f 0300 mov.w r3, #0 801910e: f04f 020a mov.w r2, #10 8019112: 4641 mov r1, r8 8019114: 4648 mov r0, r9 8019116: d107 bne.n 8019128 <_dtoa_r+0x9e8> 8019118: f000 f9ca bl 80194b0 <__multadd> 801911c: 4680 mov r8, r0 801911e: 4605 mov r5, r0 8019120: 9b05 ldr r3, [sp, #20] 8019122: 3301 adds r3, #1 8019124: 9305 str r3, [sp, #20] 8019126: e775 b.n 8019014 <_dtoa_r+0x8d4> 8019128: f000 f9c2 bl 80194b0 <__multadd> 801912c: 4629 mov r1, r5 801912e: 4680 mov r8, r0 8019130: 2300 movs r3, #0 8019132: 220a movs r2, #10 8019134: 4648 mov r0, r9 8019136: f000 f9bb bl 80194b0 <__multadd> 801913a: 4605 mov r5, r0 801913c: e7f0 b.n 8019120 <_dtoa_r+0x9e0> 801913e: f1bb 0f00 cmp.w fp, #0 8019142: bfcc ite gt 8019144: 465e movgt r6, fp 8019146: 2601 movle r6, #1 8019148: 443e add r6, r7 801914a: f04f 0800 mov.w r8, #0 801914e: 9901 ldr r1, [sp, #4] 8019150: 2201 movs r2, #1 8019152: 4648 mov r0, r9 8019154: f000 fb58 bl 8019808 <__lshift> 8019158: 4621 mov r1, r4 801915a: 9001 str r0, [sp, #4] 801915c: f000 fbc0 bl 80198e0 <__mcmp> 8019160: 2800 cmp r0, #0 8019162: dcaf bgt.n 80190c4 <_dtoa_r+0x984> 8019164: d102 bne.n 801916c <_dtoa_r+0xa2c> 8019166: f01a 0f01 tst.w sl, #1 801916a: d1ab bne.n 80190c4 <_dtoa_r+0x984> 801916c: 4633 mov r3, r6 801916e: 461e mov r6, r3 8019170: f813 2d01 ldrb.w r2, [r3, #-1]! 8019174: 2a30 cmp r2, #48 @ 0x30 8019176: d0fa beq.n 801916e <_dtoa_r+0xa2e> 8019178: e5bb b.n 8018cf2 <_dtoa_r+0x5b2> 801917a: 429f cmp r7, r3 801917c: d1a3 bne.n 80190c6 <_dtoa_r+0x986> 801917e: 9b04 ldr r3, [sp, #16] 8019180: 3301 adds r3, #1 8019182: 9304 str r3, [sp, #16] 8019184: 2331 movs r3, #49 @ 0x31 8019186: 703b strb r3, [r7, #0] 8019188: e5b3 b.n 8018cf2 <_dtoa_r+0x5b2> 801918a: 9b1d ldr r3, [sp, #116] @ 0x74 801918c: 4f16 ldr r7, [pc, #88] @ (80191e8 <_dtoa_r+0xaa8>) 801918e: b11b cbz r3, 8019198 <_dtoa_r+0xa58> 8019190: f107 0308 add.w r3, r7, #8 8019194: 9a1d ldr r2, [sp, #116] @ 0x74 8019196: 6013 str r3, [r2, #0] 8019198: 4638 mov r0, r7 801919a: b011 add sp, #68 @ 0x44 801919c: ecbd 8b02 vpop {d8} 80191a0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80191a4: 9b07 ldr r3, [sp, #28] 80191a6: 2b01 cmp r3, #1 80191a8: f77f ae36 ble.w 8018e18 <_dtoa_r+0x6d8> 80191ac: 9b0a ldr r3, [sp, #40] @ 0x28 80191ae: 930b str r3, [sp, #44] @ 0x2c 80191b0: 2001 movs r0, #1 80191b2: e656 b.n 8018e62 <_dtoa_r+0x722> 80191b4: f1bb 0f00 cmp.w fp, #0 80191b8: f77f aed7 ble.w 8018f6a <_dtoa_r+0x82a> 80191bc: 463e mov r6, r7 80191be: 9801 ldr r0, [sp, #4] 80191c0: 4621 mov r1, r4 80191c2: f7ff fa34 bl 801862e 80191c6: f100 0a30 add.w sl, r0, #48 @ 0x30 80191ca: f806 ab01 strb.w sl, [r6], #1 80191ce: 1bf2 subs r2, r6, r7 80191d0: 4593 cmp fp, r2 80191d2: ddb4 ble.n 801913e <_dtoa_r+0x9fe> 80191d4: 9901 ldr r1, [sp, #4] 80191d6: 2300 movs r3, #0 80191d8: 220a movs r2, #10 80191da: 4648 mov r0, r9 80191dc: f000 f968 bl 80194b0 <__multadd> 80191e0: 9001 str r0, [sp, #4] 80191e2: e7ec b.n 80191be <_dtoa_r+0xa7e> 80191e4: 0801a378 .word 0x0801a378 80191e8: 0801a2fc .word 0x0801a2fc 080191ec <_free_r>: 80191ec: b538 push {r3, r4, r5, lr} 80191ee: 4605 mov r5, r0 80191f0: 2900 cmp r1, #0 80191f2: d041 beq.n 8019278 <_free_r+0x8c> 80191f4: f851 3c04 ldr.w r3, [r1, #-4] 80191f8: 1f0c subs r4, r1, #4 80191fa: 2b00 cmp r3, #0 80191fc: bfb8 it lt 80191fe: 18e4 addlt r4, r4, r3 8019200: f000 f8e8 bl 80193d4 <__malloc_lock> 8019204: 4a1d ldr r2, [pc, #116] @ (801927c <_free_r+0x90>) 8019206: 6813 ldr r3, [r2, #0] 8019208: b933 cbnz r3, 8019218 <_free_r+0x2c> 801920a: 6063 str r3, [r4, #4] 801920c: 6014 str r4, [r2, #0] 801920e: 4628 mov r0, r5 8019210: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8019214: f000 b8e4 b.w 80193e0 <__malloc_unlock> 8019218: 42a3 cmp r3, r4 801921a: d908 bls.n 801922e <_free_r+0x42> 801921c: 6820 ldr r0, [r4, #0] 801921e: 1821 adds r1, r4, r0 8019220: 428b cmp r3, r1 8019222: bf01 itttt eq 8019224: 6819 ldreq r1, [r3, #0] 8019226: 685b ldreq r3, [r3, #4] 8019228: 1809 addeq r1, r1, r0 801922a: 6021 streq r1, [r4, #0] 801922c: e7ed b.n 801920a <_free_r+0x1e> 801922e: 461a mov r2, r3 8019230: 685b ldr r3, [r3, #4] 8019232: b10b cbz r3, 8019238 <_free_r+0x4c> 8019234: 42a3 cmp r3, r4 8019236: d9fa bls.n 801922e <_free_r+0x42> 8019238: 6811 ldr r1, [r2, #0] 801923a: 1850 adds r0, r2, r1 801923c: 42a0 cmp r0, r4 801923e: d10b bne.n 8019258 <_free_r+0x6c> 8019240: 6820 ldr r0, [r4, #0] 8019242: 4401 add r1, r0 8019244: 1850 adds r0, r2, r1 8019246: 4283 cmp r3, r0 8019248: 6011 str r1, [r2, #0] 801924a: d1e0 bne.n 801920e <_free_r+0x22> 801924c: 6818 ldr r0, [r3, #0] 801924e: 685b ldr r3, [r3, #4] 8019250: 6053 str r3, [r2, #4] 8019252: 4408 add r0, r1 8019254: 6010 str r0, [r2, #0] 8019256: e7da b.n 801920e <_free_r+0x22> 8019258: d902 bls.n 8019260 <_free_r+0x74> 801925a: 230c movs r3, #12 801925c: 602b str r3, [r5, #0] 801925e: e7d6 b.n 801920e <_free_r+0x22> 8019260: 6820 ldr r0, [r4, #0] 8019262: 1821 adds r1, r4, r0 8019264: 428b cmp r3, r1 8019266: bf04 itt eq 8019268: 6819 ldreq r1, [r3, #0] 801926a: 685b ldreq r3, [r3, #4] 801926c: 6063 str r3, [r4, #4] 801926e: bf04 itt eq 8019270: 1809 addeq r1, r1, r0 8019272: 6021 streq r1, [r4, #0] 8019274: 6054 str r4, [r2, #4] 8019276: e7ca b.n 801920e <_free_r+0x22> 8019278: bd38 pop {r3, r4, r5, pc} 801927a: bf00 nop 801927c: 240132f0 .word 0x240132f0 08019280 : 8019280: 4b02 ldr r3, [pc, #8] @ (801928c ) 8019282: 4601 mov r1, r0 8019284: 6818 ldr r0, [r3, #0] 8019286: f000 b825 b.w 80192d4 <_malloc_r> 801928a: bf00 nop 801928c: 24000054 .word 0x24000054 08019290 : 8019290: b570 push {r4, r5, r6, lr} 8019292: 4e0f ldr r6, [pc, #60] @ (80192d0 ) 8019294: 460c mov r4, r1 8019296: 6831 ldr r1, [r6, #0] 8019298: 4605 mov r5, r0 801929a: b911 cbnz r1, 80192a2 801929c: f000 fd58 bl 8019d50 <_sbrk_r> 80192a0: 6030 str r0, [r6, #0] 80192a2: 4621 mov r1, r4 80192a4: 4628 mov r0, r5 80192a6: f000 fd53 bl 8019d50 <_sbrk_r> 80192aa: 1c43 adds r3, r0, #1 80192ac: d103 bne.n 80192b6 80192ae: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 80192b2: 4620 mov r0, r4 80192b4: bd70 pop {r4, r5, r6, pc} 80192b6: 1cc4 adds r4, r0, #3 80192b8: f024 0403 bic.w r4, r4, #3 80192bc: 42a0 cmp r0, r4 80192be: d0f8 beq.n 80192b2 80192c0: 1a21 subs r1, r4, r0 80192c2: 4628 mov r0, r5 80192c4: f000 fd44 bl 8019d50 <_sbrk_r> 80192c8: 3001 adds r0, #1 80192ca: d1f2 bne.n 80192b2 80192cc: e7ef b.n 80192ae 80192ce: bf00 nop 80192d0: 240132ec .word 0x240132ec 080192d4 <_malloc_r>: 80192d4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 80192d8: 1ccd adds r5, r1, #3 80192da: f025 0503 bic.w r5, r5, #3 80192de: 3508 adds r5, #8 80192e0: 2d0c cmp r5, #12 80192e2: bf38 it cc 80192e4: 250c movcc r5, #12 80192e6: 2d00 cmp r5, #0 80192e8: 4606 mov r6, r0 80192ea: db01 blt.n 80192f0 <_malloc_r+0x1c> 80192ec: 42a9 cmp r1, r5 80192ee: d904 bls.n 80192fa <_malloc_r+0x26> 80192f0: 230c movs r3, #12 80192f2: 6033 str r3, [r6, #0] 80192f4: 2000 movs r0, #0 80192f6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 80192fa: f8df 80d4 ldr.w r8, [pc, #212] @ 80193d0 <_malloc_r+0xfc> 80192fe: f000 f869 bl 80193d4 <__malloc_lock> 8019302: f8d8 3000 ldr.w r3, [r8] 8019306: 461c mov r4, r3 8019308: bb44 cbnz r4, 801935c <_malloc_r+0x88> 801930a: 4629 mov r1, r5 801930c: 4630 mov r0, r6 801930e: f7ff ffbf bl 8019290 8019312: 1c43 adds r3, r0, #1 8019314: 4604 mov r4, r0 8019316: d158 bne.n 80193ca <_malloc_r+0xf6> 8019318: f8d8 4000 ldr.w r4, [r8] 801931c: 4627 mov r7, r4 801931e: 2f00 cmp r7, #0 8019320: d143 bne.n 80193aa <_malloc_r+0xd6> 8019322: 2c00 cmp r4, #0 8019324: d04b beq.n 80193be <_malloc_r+0xea> 8019326: 6823 ldr r3, [r4, #0] 8019328: 4639 mov r1, r7 801932a: 4630 mov r0, r6 801932c: eb04 0903 add.w r9, r4, r3 8019330: f000 fd0e bl 8019d50 <_sbrk_r> 8019334: 4581 cmp r9, r0 8019336: d142 bne.n 80193be <_malloc_r+0xea> 8019338: 6821 ldr r1, [r4, #0] 801933a: 1a6d subs r5, r5, r1 801933c: 4629 mov r1, r5 801933e: 4630 mov r0, r6 8019340: f7ff ffa6 bl 8019290 8019344: 3001 adds r0, #1 8019346: d03a beq.n 80193be <_malloc_r+0xea> 8019348: 6823 ldr r3, [r4, #0] 801934a: 442b add r3, r5 801934c: 6023 str r3, [r4, #0] 801934e: f8d8 3000 ldr.w r3, [r8] 8019352: 685a ldr r2, [r3, #4] 8019354: bb62 cbnz r2, 80193b0 <_malloc_r+0xdc> 8019356: f8c8 7000 str.w r7, [r8] 801935a: e00f b.n 801937c <_malloc_r+0xa8> 801935c: 6822 ldr r2, [r4, #0] 801935e: 1b52 subs r2, r2, r5 8019360: d420 bmi.n 80193a4 <_malloc_r+0xd0> 8019362: 2a0b cmp r2, #11 8019364: d917 bls.n 8019396 <_malloc_r+0xc2> 8019366: 1961 adds r1, r4, r5 8019368: 42a3 cmp r3, r4 801936a: 6025 str r5, [r4, #0] 801936c: bf18 it ne 801936e: 6059 strne r1, [r3, #4] 8019370: 6863 ldr r3, [r4, #4] 8019372: bf08 it eq 8019374: f8c8 1000 streq.w r1, [r8] 8019378: 5162 str r2, [r4, r5] 801937a: 604b str r3, [r1, #4] 801937c: 4630 mov r0, r6 801937e: f000 f82f bl 80193e0 <__malloc_unlock> 8019382: f104 000b add.w r0, r4, #11 8019386: 1d23 adds r3, r4, #4 8019388: f020 0007 bic.w r0, r0, #7 801938c: 1ac2 subs r2, r0, r3 801938e: bf1c itt ne 8019390: 1a1b subne r3, r3, r0 8019392: 50a3 strne r3, [r4, r2] 8019394: e7af b.n 80192f6 <_malloc_r+0x22> 8019396: 6862 ldr r2, [r4, #4] 8019398: 42a3 cmp r3, r4 801939a: bf0c ite eq 801939c: f8c8 2000 streq.w r2, [r8] 80193a0: 605a strne r2, [r3, #4] 80193a2: e7eb b.n 801937c <_malloc_r+0xa8> 80193a4: 4623 mov r3, r4 80193a6: 6864 ldr r4, [r4, #4] 80193a8: e7ae b.n 8019308 <_malloc_r+0x34> 80193aa: 463c mov r4, r7 80193ac: 687f ldr r7, [r7, #4] 80193ae: e7b6 b.n 801931e <_malloc_r+0x4a> 80193b0: 461a mov r2, r3 80193b2: 685b ldr r3, [r3, #4] 80193b4: 42a3 cmp r3, r4 80193b6: d1fb bne.n 80193b0 <_malloc_r+0xdc> 80193b8: 2300 movs r3, #0 80193ba: 6053 str r3, [r2, #4] 80193bc: e7de b.n 801937c <_malloc_r+0xa8> 80193be: 230c movs r3, #12 80193c0: 6033 str r3, [r6, #0] 80193c2: 4630 mov r0, r6 80193c4: f000 f80c bl 80193e0 <__malloc_unlock> 80193c8: e794 b.n 80192f4 <_malloc_r+0x20> 80193ca: 6005 str r5, [r0, #0] 80193cc: e7d6 b.n 801937c <_malloc_r+0xa8> 80193ce: bf00 nop 80193d0: 240132f0 .word 0x240132f0 080193d4 <__malloc_lock>: 80193d4: 4801 ldr r0, [pc, #4] @ (80193dc <__malloc_lock+0x8>) 80193d6: f7ff b91a b.w 801860e <__retarget_lock_acquire_recursive> 80193da: bf00 nop 80193dc: 240132e8 .word 0x240132e8 080193e0 <__malloc_unlock>: 80193e0: 4801 ldr r0, [pc, #4] @ (80193e8 <__malloc_unlock+0x8>) 80193e2: f7ff b915 b.w 8018610 <__retarget_lock_release_recursive> 80193e6: bf00 nop 80193e8: 240132e8 .word 0x240132e8 080193ec <_Balloc>: 80193ec: b570 push {r4, r5, r6, lr} 80193ee: 69c6 ldr r6, [r0, #28] 80193f0: 4604 mov r4, r0 80193f2: 460d mov r5, r1 80193f4: b976 cbnz r6, 8019414 <_Balloc+0x28> 80193f6: 2010 movs r0, #16 80193f8: f7ff ff42 bl 8019280 80193fc: 4602 mov r2, r0 80193fe: 61e0 str r0, [r4, #28] 8019400: b920 cbnz r0, 801940c <_Balloc+0x20> 8019402: 4b18 ldr r3, [pc, #96] @ (8019464 <_Balloc+0x78>) 8019404: 4818 ldr r0, [pc, #96] @ (8019468 <_Balloc+0x7c>) 8019406: 216b movs r1, #107 @ 0x6b 8019408: f000 fcb2 bl 8019d70 <__assert_func> 801940c: e9c0 6601 strd r6, r6, [r0, #4] 8019410: 6006 str r6, [r0, #0] 8019412: 60c6 str r6, [r0, #12] 8019414: 69e6 ldr r6, [r4, #28] 8019416: 68f3 ldr r3, [r6, #12] 8019418: b183 cbz r3, 801943c <_Balloc+0x50> 801941a: 69e3 ldr r3, [r4, #28] 801941c: 68db ldr r3, [r3, #12] 801941e: f853 0025 ldr.w r0, [r3, r5, lsl #2] 8019422: b9b8 cbnz r0, 8019454 <_Balloc+0x68> 8019424: 2101 movs r1, #1 8019426: fa01 f605 lsl.w r6, r1, r5 801942a: 1d72 adds r2, r6, #5 801942c: 0092 lsls r2, r2, #2 801942e: 4620 mov r0, r4 8019430: f000 fcbc bl 8019dac <_calloc_r> 8019434: b160 cbz r0, 8019450 <_Balloc+0x64> 8019436: e9c0 5601 strd r5, r6, [r0, #4] 801943a: e00e b.n 801945a <_Balloc+0x6e> 801943c: 2221 movs r2, #33 @ 0x21 801943e: 2104 movs r1, #4 8019440: 4620 mov r0, r4 8019442: f000 fcb3 bl 8019dac <_calloc_r> 8019446: 69e3 ldr r3, [r4, #28] 8019448: 60f0 str r0, [r6, #12] 801944a: 68db ldr r3, [r3, #12] 801944c: 2b00 cmp r3, #0 801944e: d1e4 bne.n 801941a <_Balloc+0x2e> 8019450: 2000 movs r0, #0 8019452: bd70 pop {r4, r5, r6, pc} 8019454: 6802 ldr r2, [r0, #0] 8019456: f843 2025 str.w r2, [r3, r5, lsl #2] 801945a: 2300 movs r3, #0 801945c: e9c0 3303 strd r3, r3, [r0, #12] 8019460: e7f7 b.n 8019452 <_Balloc+0x66> 8019462: bf00 nop 8019464: 0801a309 .word 0x0801a309 8019468: 0801a389 .word 0x0801a389 0801946c <_Bfree>: 801946c: b570 push {r4, r5, r6, lr} 801946e: 69c6 ldr r6, [r0, #28] 8019470: 4605 mov r5, r0 8019472: 460c mov r4, r1 8019474: b976 cbnz r6, 8019494 <_Bfree+0x28> 8019476: 2010 movs r0, #16 8019478: f7ff ff02 bl 8019280 801947c: 4602 mov r2, r0 801947e: 61e8 str r0, [r5, #28] 8019480: b920 cbnz r0, 801948c <_Bfree+0x20> 8019482: 4b09 ldr r3, [pc, #36] @ (80194a8 <_Bfree+0x3c>) 8019484: 4809 ldr r0, [pc, #36] @ (80194ac <_Bfree+0x40>) 8019486: 218f movs r1, #143 @ 0x8f 8019488: f000 fc72 bl 8019d70 <__assert_func> 801948c: e9c0 6601 strd r6, r6, [r0, #4] 8019490: 6006 str r6, [r0, #0] 8019492: 60c6 str r6, [r0, #12] 8019494: b13c cbz r4, 80194a6 <_Bfree+0x3a> 8019496: 69eb ldr r3, [r5, #28] 8019498: 6862 ldr r2, [r4, #4] 801949a: 68db ldr r3, [r3, #12] 801949c: f853 1022 ldr.w r1, [r3, r2, lsl #2] 80194a0: 6021 str r1, [r4, #0] 80194a2: f843 4022 str.w r4, [r3, r2, lsl #2] 80194a6: bd70 pop {r4, r5, r6, pc} 80194a8: 0801a309 .word 0x0801a309 80194ac: 0801a389 .word 0x0801a389 080194b0 <__multadd>: 80194b0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80194b4: 690d ldr r5, [r1, #16] 80194b6: 4607 mov r7, r0 80194b8: 460c mov r4, r1 80194ba: 461e mov r6, r3 80194bc: f101 0c14 add.w ip, r1, #20 80194c0: 2000 movs r0, #0 80194c2: f8dc 3000 ldr.w r3, [ip] 80194c6: b299 uxth r1, r3 80194c8: fb02 6101 mla r1, r2, r1, r6 80194cc: 0c1e lsrs r6, r3, #16 80194ce: 0c0b lsrs r3, r1, #16 80194d0: fb02 3306 mla r3, r2, r6, r3 80194d4: b289 uxth r1, r1 80194d6: 3001 adds r0, #1 80194d8: eb01 4103 add.w r1, r1, r3, lsl #16 80194dc: 4285 cmp r5, r0 80194de: f84c 1b04 str.w r1, [ip], #4 80194e2: ea4f 4613 mov.w r6, r3, lsr #16 80194e6: dcec bgt.n 80194c2 <__multadd+0x12> 80194e8: b30e cbz r6, 801952e <__multadd+0x7e> 80194ea: 68a3 ldr r3, [r4, #8] 80194ec: 42ab cmp r3, r5 80194ee: dc19 bgt.n 8019524 <__multadd+0x74> 80194f0: 6861 ldr r1, [r4, #4] 80194f2: 4638 mov r0, r7 80194f4: 3101 adds r1, #1 80194f6: f7ff ff79 bl 80193ec <_Balloc> 80194fa: 4680 mov r8, r0 80194fc: b928 cbnz r0, 801950a <__multadd+0x5a> 80194fe: 4602 mov r2, r0 8019500: 4b0c ldr r3, [pc, #48] @ (8019534 <__multadd+0x84>) 8019502: 480d ldr r0, [pc, #52] @ (8019538 <__multadd+0x88>) 8019504: 21ba movs r1, #186 @ 0xba 8019506: f000 fc33 bl 8019d70 <__assert_func> 801950a: 6922 ldr r2, [r4, #16] 801950c: 3202 adds r2, #2 801950e: f104 010c add.w r1, r4, #12 8019512: 0092 lsls r2, r2, #2 8019514: 300c adds r0, #12 8019516: f7ff f87c bl 8018612 801951a: 4621 mov r1, r4 801951c: 4638 mov r0, r7 801951e: f7ff ffa5 bl 801946c <_Bfree> 8019522: 4644 mov r4, r8 8019524: eb04 0385 add.w r3, r4, r5, lsl #2 8019528: 3501 adds r5, #1 801952a: 615e str r6, [r3, #20] 801952c: 6125 str r5, [r4, #16] 801952e: 4620 mov r0, r4 8019530: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8019534: 0801a378 .word 0x0801a378 8019538: 0801a389 .word 0x0801a389 0801953c <__hi0bits>: 801953c: f5b0 3f80 cmp.w r0, #65536 @ 0x10000 8019540: 4603 mov r3, r0 8019542: bf36 itet cc 8019544: 0403 lslcc r3, r0, #16 8019546: 2000 movcs r0, #0 8019548: 2010 movcc r0, #16 801954a: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 801954e: bf3c itt cc 8019550: 021b lslcc r3, r3, #8 8019552: 3008 addcc r0, #8 8019554: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8019558: bf3c itt cc 801955a: 011b lslcc r3, r3, #4 801955c: 3004 addcc r0, #4 801955e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8019562: bf3c itt cc 8019564: 009b lslcc r3, r3, #2 8019566: 3002 addcc r0, #2 8019568: 2b00 cmp r3, #0 801956a: db05 blt.n 8019578 <__hi0bits+0x3c> 801956c: f013 4f80 tst.w r3, #1073741824 @ 0x40000000 8019570: f100 0001 add.w r0, r0, #1 8019574: bf08 it eq 8019576: 2020 moveq r0, #32 8019578: 4770 bx lr 0801957a <__lo0bits>: 801957a: 6803 ldr r3, [r0, #0] 801957c: 4602 mov r2, r0 801957e: f013 0007 ands.w r0, r3, #7 8019582: d00b beq.n 801959c <__lo0bits+0x22> 8019584: 07d9 lsls r1, r3, #31 8019586: d421 bmi.n 80195cc <__lo0bits+0x52> 8019588: 0798 lsls r0, r3, #30 801958a: bf49 itett mi 801958c: 085b lsrmi r3, r3, #1 801958e: 089b lsrpl r3, r3, #2 8019590: 2001 movmi r0, #1 8019592: 6013 strmi r3, [r2, #0] 8019594: bf5c itt pl 8019596: 6013 strpl r3, [r2, #0] 8019598: 2002 movpl r0, #2 801959a: 4770 bx lr 801959c: b299 uxth r1, r3 801959e: b909 cbnz r1, 80195a4 <__lo0bits+0x2a> 80195a0: 0c1b lsrs r3, r3, #16 80195a2: 2010 movs r0, #16 80195a4: b2d9 uxtb r1, r3 80195a6: b909 cbnz r1, 80195ac <__lo0bits+0x32> 80195a8: 3008 adds r0, #8 80195aa: 0a1b lsrs r3, r3, #8 80195ac: 0719 lsls r1, r3, #28 80195ae: bf04 itt eq 80195b0: 091b lsreq r3, r3, #4 80195b2: 3004 addeq r0, #4 80195b4: 0799 lsls r1, r3, #30 80195b6: bf04 itt eq 80195b8: 089b lsreq r3, r3, #2 80195ba: 3002 addeq r0, #2 80195bc: 07d9 lsls r1, r3, #31 80195be: d403 bmi.n 80195c8 <__lo0bits+0x4e> 80195c0: 085b lsrs r3, r3, #1 80195c2: f100 0001 add.w r0, r0, #1 80195c6: d003 beq.n 80195d0 <__lo0bits+0x56> 80195c8: 6013 str r3, [r2, #0] 80195ca: 4770 bx lr 80195cc: 2000 movs r0, #0 80195ce: 4770 bx lr 80195d0: 2020 movs r0, #32 80195d2: 4770 bx lr 080195d4 <__i2b>: 80195d4: b510 push {r4, lr} 80195d6: 460c mov r4, r1 80195d8: 2101 movs r1, #1 80195da: f7ff ff07 bl 80193ec <_Balloc> 80195de: 4602 mov r2, r0 80195e0: b928 cbnz r0, 80195ee <__i2b+0x1a> 80195e2: 4b05 ldr r3, [pc, #20] @ (80195f8 <__i2b+0x24>) 80195e4: 4805 ldr r0, [pc, #20] @ (80195fc <__i2b+0x28>) 80195e6: f240 1145 movw r1, #325 @ 0x145 80195ea: f000 fbc1 bl 8019d70 <__assert_func> 80195ee: 2301 movs r3, #1 80195f0: 6144 str r4, [r0, #20] 80195f2: 6103 str r3, [r0, #16] 80195f4: bd10 pop {r4, pc} 80195f6: bf00 nop 80195f8: 0801a378 .word 0x0801a378 80195fc: 0801a389 .word 0x0801a389 08019600 <__multiply>: 8019600: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8019604: 4614 mov r4, r2 8019606: 690a ldr r2, [r1, #16] 8019608: 6923 ldr r3, [r4, #16] 801960a: 429a cmp r2, r3 801960c: bfa8 it ge 801960e: 4623 movge r3, r4 8019610: 460f mov r7, r1 8019612: bfa4 itt ge 8019614: 460c movge r4, r1 8019616: 461f movge r7, r3 8019618: f8d4 a010 ldr.w sl, [r4, #16] 801961c: f8d7 9010 ldr.w r9, [r7, #16] 8019620: 68a3 ldr r3, [r4, #8] 8019622: 6861 ldr r1, [r4, #4] 8019624: eb0a 0609 add.w r6, sl, r9 8019628: 42b3 cmp r3, r6 801962a: b085 sub sp, #20 801962c: bfb8 it lt 801962e: 3101 addlt r1, #1 8019630: f7ff fedc bl 80193ec <_Balloc> 8019634: b930 cbnz r0, 8019644 <__multiply+0x44> 8019636: 4602 mov r2, r0 8019638: 4b44 ldr r3, [pc, #272] @ (801974c <__multiply+0x14c>) 801963a: 4845 ldr r0, [pc, #276] @ (8019750 <__multiply+0x150>) 801963c: f44f 71b1 mov.w r1, #354 @ 0x162 8019640: f000 fb96 bl 8019d70 <__assert_func> 8019644: f100 0514 add.w r5, r0, #20 8019648: eb05 0886 add.w r8, r5, r6, lsl #2 801964c: 462b mov r3, r5 801964e: 2200 movs r2, #0 8019650: 4543 cmp r3, r8 8019652: d321 bcc.n 8019698 <__multiply+0x98> 8019654: f107 0114 add.w r1, r7, #20 8019658: f104 0214 add.w r2, r4, #20 801965c: eb02 028a add.w r2, r2, sl, lsl #2 8019660: eb01 0389 add.w r3, r1, r9, lsl #2 8019664: 9302 str r3, [sp, #8] 8019666: 1b13 subs r3, r2, r4 8019668: 3b15 subs r3, #21 801966a: f023 0303 bic.w r3, r3, #3 801966e: 3304 adds r3, #4 8019670: f104 0715 add.w r7, r4, #21 8019674: 42ba cmp r2, r7 8019676: bf38 it cc 8019678: 2304 movcc r3, #4 801967a: 9301 str r3, [sp, #4] 801967c: 9b02 ldr r3, [sp, #8] 801967e: 9103 str r1, [sp, #12] 8019680: 428b cmp r3, r1 8019682: d80c bhi.n 801969e <__multiply+0x9e> 8019684: 2e00 cmp r6, #0 8019686: dd03 ble.n 8019690 <__multiply+0x90> 8019688: f858 3d04 ldr.w r3, [r8, #-4]! 801968c: 2b00 cmp r3, #0 801968e: d05b beq.n 8019748 <__multiply+0x148> 8019690: 6106 str r6, [r0, #16] 8019692: b005 add sp, #20 8019694: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8019698: f843 2b04 str.w r2, [r3], #4 801969c: e7d8 b.n 8019650 <__multiply+0x50> 801969e: f8b1 a000 ldrh.w sl, [r1] 80196a2: f1ba 0f00 cmp.w sl, #0 80196a6: d024 beq.n 80196f2 <__multiply+0xf2> 80196a8: f104 0e14 add.w lr, r4, #20 80196ac: 46a9 mov r9, r5 80196ae: f04f 0c00 mov.w ip, #0 80196b2: f85e 7b04 ldr.w r7, [lr], #4 80196b6: f8d9 3000 ldr.w r3, [r9] 80196ba: fa1f fb87 uxth.w fp, r7 80196be: b29b uxth r3, r3 80196c0: fb0a 330b mla r3, sl, fp, r3 80196c4: ea4f 4b17 mov.w fp, r7, lsr #16 80196c8: f8d9 7000 ldr.w r7, [r9] 80196cc: 4463 add r3, ip 80196ce: ea4f 4c17 mov.w ip, r7, lsr #16 80196d2: fb0a c70b mla r7, sl, fp, ip 80196d6: eb07 4713 add.w r7, r7, r3, lsr #16 80196da: b29b uxth r3, r3 80196dc: ea43 4307 orr.w r3, r3, r7, lsl #16 80196e0: 4572 cmp r2, lr 80196e2: f849 3b04 str.w r3, [r9], #4 80196e6: ea4f 4c17 mov.w ip, r7, lsr #16 80196ea: d8e2 bhi.n 80196b2 <__multiply+0xb2> 80196ec: 9b01 ldr r3, [sp, #4] 80196ee: f845 c003 str.w ip, [r5, r3] 80196f2: 9b03 ldr r3, [sp, #12] 80196f4: f8b3 9002 ldrh.w r9, [r3, #2] 80196f8: 3104 adds r1, #4 80196fa: f1b9 0f00 cmp.w r9, #0 80196fe: d021 beq.n 8019744 <__multiply+0x144> 8019700: 682b ldr r3, [r5, #0] 8019702: f104 0c14 add.w ip, r4, #20 8019706: 46ae mov lr, r5 8019708: f04f 0a00 mov.w sl, #0 801970c: f8bc b000 ldrh.w fp, [ip] 8019710: f8be 7002 ldrh.w r7, [lr, #2] 8019714: fb09 770b mla r7, r9, fp, r7 8019718: 4457 add r7, sl 801971a: b29b uxth r3, r3 801971c: ea43 4307 orr.w r3, r3, r7, lsl #16 8019720: f84e 3b04 str.w r3, [lr], #4 8019724: f85c 3b04 ldr.w r3, [ip], #4 8019728: ea4f 4a13 mov.w sl, r3, lsr #16 801972c: f8be 3000 ldrh.w r3, [lr] 8019730: fb09 330a mla r3, r9, sl, r3 8019734: eb03 4317 add.w r3, r3, r7, lsr #16 8019738: 4562 cmp r2, ip 801973a: ea4f 4a13 mov.w sl, r3, lsr #16 801973e: d8e5 bhi.n 801970c <__multiply+0x10c> 8019740: 9f01 ldr r7, [sp, #4] 8019742: 51eb str r3, [r5, r7] 8019744: 3504 adds r5, #4 8019746: e799 b.n 801967c <__multiply+0x7c> 8019748: 3e01 subs r6, #1 801974a: e79b b.n 8019684 <__multiply+0x84> 801974c: 0801a378 .word 0x0801a378 8019750: 0801a389 .word 0x0801a389 08019754 <__pow5mult>: 8019754: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8019758: 4615 mov r5, r2 801975a: f012 0203 ands.w r2, r2, #3 801975e: 4607 mov r7, r0 8019760: 460e mov r6, r1 8019762: d007 beq.n 8019774 <__pow5mult+0x20> 8019764: 4c25 ldr r4, [pc, #148] @ (80197fc <__pow5mult+0xa8>) 8019766: 3a01 subs r2, #1 8019768: 2300 movs r3, #0 801976a: f854 2022 ldr.w r2, [r4, r2, lsl #2] 801976e: f7ff fe9f bl 80194b0 <__multadd> 8019772: 4606 mov r6, r0 8019774: 10ad asrs r5, r5, #2 8019776: d03d beq.n 80197f4 <__pow5mult+0xa0> 8019778: 69fc ldr r4, [r7, #28] 801977a: b97c cbnz r4, 801979c <__pow5mult+0x48> 801977c: 2010 movs r0, #16 801977e: f7ff fd7f bl 8019280 8019782: 4602 mov r2, r0 8019784: 61f8 str r0, [r7, #28] 8019786: b928 cbnz r0, 8019794 <__pow5mult+0x40> 8019788: 4b1d ldr r3, [pc, #116] @ (8019800 <__pow5mult+0xac>) 801978a: 481e ldr r0, [pc, #120] @ (8019804 <__pow5mult+0xb0>) 801978c: f240 11b3 movw r1, #435 @ 0x1b3 8019790: f000 faee bl 8019d70 <__assert_func> 8019794: e9c0 4401 strd r4, r4, [r0, #4] 8019798: 6004 str r4, [r0, #0] 801979a: 60c4 str r4, [r0, #12] 801979c: f8d7 801c ldr.w r8, [r7, #28] 80197a0: f8d8 4008 ldr.w r4, [r8, #8] 80197a4: b94c cbnz r4, 80197ba <__pow5mult+0x66> 80197a6: f240 2171 movw r1, #625 @ 0x271 80197aa: 4638 mov r0, r7 80197ac: f7ff ff12 bl 80195d4 <__i2b> 80197b0: 2300 movs r3, #0 80197b2: f8c8 0008 str.w r0, [r8, #8] 80197b6: 4604 mov r4, r0 80197b8: 6003 str r3, [r0, #0] 80197ba: f04f 0900 mov.w r9, #0 80197be: 07eb lsls r3, r5, #31 80197c0: d50a bpl.n 80197d8 <__pow5mult+0x84> 80197c2: 4631 mov r1, r6 80197c4: 4622 mov r2, r4 80197c6: 4638 mov r0, r7 80197c8: f7ff ff1a bl 8019600 <__multiply> 80197cc: 4631 mov r1, r6 80197ce: 4680 mov r8, r0 80197d0: 4638 mov r0, r7 80197d2: f7ff fe4b bl 801946c <_Bfree> 80197d6: 4646 mov r6, r8 80197d8: 106d asrs r5, r5, #1 80197da: d00b beq.n 80197f4 <__pow5mult+0xa0> 80197dc: 6820 ldr r0, [r4, #0] 80197de: b938 cbnz r0, 80197f0 <__pow5mult+0x9c> 80197e0: 4622 mov r2, r4 80197e2: 4621 mov r1, r4 80197e4: 4638 mov r0, r7 80197e6: f7ff ff0b bl 8019600 <__multiply> 80197ea: 6020 str r0, [r4, #0] 80197ec: f8c0 9000 str.w r9, [r0] 80197f0: 4604 mov r4, r0 80197f2: e7e4 b.n 80197be <__pow5mult+0x6a> 80197f4: 4630 mov r0, r6 80197f6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 80197fa: bf00 nop 80197fc: 0801a3e4 .word 0x0801a3e4 8019800: 0801a309 .word 0x0801a309 8019804: 0801a389 .word 0x0801a389 08019808 <__lshift>: 8019808: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 801980c: 460c mov r4, r1 801980e: 6849 ldr r1, [r1, #4] 8019810: 6923 ldr r3, [r4, #16] 8019812: eb03 1862 add.w r8, r3, r2, asr #5 8019816: 68a3 ldr r3, [r4, #8] 8019818: 4607 mov r7, r0 801981a: 4691 mov r9, r2 801981c: ea4f 1a62 mov.w sl, r2, asr #5 8019820: f108 0601 add.w r6, r8, #1 8019824: 42b3 cmp r3, r6 8019826: db0b blt.n 8019840 <__lshift+0x38> 8019828: 4638 mov r0, r7 801982a: f7ff fddf bl 80193ec <_Balloc> 801982e: 4605 mov r5, r0 8019830: b948 cbnz r0, 8019846 <__lshift+0x3e> 8019832: 4602 mov r2, r0 8019834: 4b28 ldr r3, [pc, #160] @ (80198d8 <__lshift+0xd0>) 8019836: 4829 ldr r0, [pc, #164] @ (80198dc <__lshift+0xd4>) 8019838: f44f 71ef mov.w r1, #478 @ 0x1de 801983c: f000 fa98 bl 8019d70 <__assert_func> 8019840: 3101 adds r1, #1 8019842: 005b lsls r3, r3, #1 8019844: e7ee b.n 8019824 <__lshift+0x1c> 8019846: 2300 movs r3, #0 8019848: f100 0114 add.w r1, r0, #20 801984c: f100 0210 add.w r2, r0, #16 8019850: 4618 mov r0, r3 8019852: 4553 cmp r3, sl 8019854: db33 blt.n 80198be <__lshift+0xb6> 8019856: 6920 ldr r0, [r4, #16] 8019858: ea2a 7aea bic.w sl, sl, sl, asr #31 801985c: f104 0314 add.w r3, r4, #20 8019860: f019 091f ands.w r9, r9, #31 8019864: eb01 018a add.w r1, r1, sl, lsl #2 8019868: eb03 0c80 add.w ip, r3, r0, lsl #2 801986c: d02b beq.n 80198c6 <__lshift+0xbe> 801986e: f1c9 0e20 rsb lr, r9, #32 8019872: 468a mov sl, r1 8019874: 2200 movs r2, #0 8019876: 6818 ldr r0, [r3, #0] 8019878: fa00 f009 lsl.w r0, r0, r9 801987c: 4310 orrs r0, r2 801987e: f84a 0b04 str.w r0, [sl], #4 8019882: f853 2b04 ldr.w r2, [r3], #4 8019886: 459c cmp ip, r3 8019888: fa22 f20e lsr.w r2, r2, lr 801988c: d8f3 bhi.n 8019876 <__lshift+0x6e> 801988e: ebac 0304 sub.w r3, ip, r4 8019892: 3b15 subs r3, #21 8019894: f023 0303 bic.w r3, r3, #3 8019898: 3304 adds r3, #4 801989a: f104 0015 add.w r0, r4, #21 801989e: 4584 cmp ip, r0 80198a0: bf38 it cc 80198a2: 2304 movcc r3, #4 80198a4: 50ca str r2, [r1, r3] 80198a6: b10a cbz r2, 80198ac <__lshift+0xa4> 80198a8: f108 0602 add.w r6, r8, #2 80198ac: 3e01 subs r6, #1 80198ae: 4638 mov r0, r7 80198b0: 612e str r6, [r5, #16] 80198b2: 4621 mov r1, r4 80198b4: f7ff fdda bl 801946c <_Bfree> 80198b8: 4628 mov r0, r5 80198ba: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80198be: f842 0f04 str.w r0, [r2, #4]! 80198c2: 3301 adds r3, #1 80198c4: e7c5 b.n 8019852 <__lshift+0x4a> 80198c6: 3904 subs r1, #4 80198c8: f853 2b04 ldr.w r2, [r3], #4 80198cc: f841 2f04 str.w r2, [r1, #4]! 80198d0: 459c cmp ip, r3 80198d2: d8f9 bhi.n 80198c8 <__lshift+0xc0> 80198d4: e7ea b.n 80198ac <__lshift+0xa4> 80198d6: bf00 nop 80198d8: 0801a378 .word 0x0801a378 80198dc: 0801a389 .word 0x0801a389 080198e0 <__mcmp>: 80198e0: 690a ldr r2, [r1, #16] 80198e2: 4603 mov r3, r0 80198e4: 6900 ldr r0, [r0, #16] 80198e6: 1a80 subs r0, r0, r2 80198e8: b530 push {r4, r5, lr} 80198ea: d10e bne.n 801990a <__mcmp+0x2a> 80198ec: 3314 adds r3, #20 80198ee: 3114 adds r1, #20 80198f0: eb03 0482 add.w r4, r3, r2, lsl #2 80198f4: eb01 0182 add.w r1, r1, r2, lsl #2 80198f8: f854 5d04 ldr.w r5, [r4, #-4]! 80198fc: f851 2d04 ldr.w r2, [r1, #-4]! 8019900: 4295 cmp r5, r2 8019902: d003 beq.n 801990c <__mcmp+0x2c> 8019904: d205 bcs.n 8019912 <__mcmp+0x32> 8019906: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801990a: bd30 pop {r4, r5, pc} 801990c: 42a3 cmp r3, r4 801990e: d3f3 bcc.n 80198f8 <__mcmp+0x18> 8019910: e7fb b.n 801990a <__mcmp+0x2a> 8019912: 2001 movs r0, #1 8019914: e7f9 b.n 801990a <__mcmp+0x2a> ... 08019918 <__mdiff>: 8019918: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 801991c: 4689 mov r9, r1 801991e: 4606 mov r6, r0 8019920: 4611 mov r1, r2 8019922: 4648 mov r0, r9 8019924: 4614 mov r4, r2 8019926: f7ff ffdb bl 80198e0 <__mcmp> 801992a: 1e05 subs r5, r0, #0 801992c: d112 bne.n 8019954 <__mdiff+0x3c> 801992e: 4629 mov r1, r5 8019930: 4630 mov r0, r6 8019932: f7ff fd5b bl 80193ec <_Balloc> 8019936: 4602 mov r2, r0 8019938: b928 cbnz r0, 8019946 <__mdiff+0x2e> 801993a: 4b3f ldr r3, [pc, #252] @ (8019a38 <__mdiff+0x120>) 801993c: f240 2137 movw r1, #567 @ 0x237 8019940: 483e ldr r0, [pc, #248] @ (8019a3c <__mdiff+0x124>) 8019942: f000 fa15 bl 8019d70 <__assert_func> 8019946: 2301 movs r3, #1 8019948: e9c0 3504 strd r3, r5, [r0, #16] 801994c: 4610 mov r0, r2 801994e: b003 add sp, #12 8019950: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8019954: bfbc itt lt 8019956: 464b movlt r3, r9 8019958: 46a1 movlt r9, r4 801995a: 4630 mov r0, r6 801995c: f8d9 1004 ldr.w r1, [r9, #4] 8019960: bfba itte lt 8019962: 461c movlt r4, r3 8019964: 2501 movlt r5, #1 8019966: 2500 movge r5, #0 8019968: f7ff fd40 bl 80193ec <_Balloc> 801996c: 4602 mov r2, r0 801996e: b918 cbnz r0, 8019978 <__mdiff+0x60> 8019970: 4b31 ldr r3, [pc, #196] @ (8019a38 <__mdiff+0x120>) 8019972: f240 2145 movw r1, #581 @ 0x245 8019976: e7e3 b.n 8019940 <__mdiff+0x28> 8019978: f8d9 7010 ldr.w r7, [r9, #16] 801997c: 6926 ldr r6, [r4, #16] 801997e: 60c5 str r5, [r0, #12] 8019980: f109 0310 add.w r3, r9, #16 8019984: f109 0514 add.w r5, r9, #20 8019988: f104 0e14 add.w lr, r4, #20 801998c: f100 0b14 add.w fp, r0, #20 8019990: eb05 0887 add.w r8, r5, r7, lsl #2 8019994: eb0e 0686 add.w r6, lr, r6, lsl #2 8019998: 9301 str r3, [sp, #4] 801999a: 46d9 mov r9, fp 801999c: f04f 0c00 mov.w ip, #0 80199a0: 9b01 ldr r3, [sp, #4] 80199a2: f85e 0b04 ldr.w r0, [lr], #4 80199a6: f853 af04 ldr.w sl, [r3, #4]! 80199aa: 9301 str r3, [sp, #4] 80199ac: fa1f f38a uxth.w r3, sl 80199b0: 4619 mov r1, r3 80199b2: b283 uxth r3, r0 80199b4: 1acb subs r3, r1, r3 80199b6: 0c00 lsrs r0, r0, #16 80199b8: 4463 add r3, ip 80199ba: ebc0 401a rsb r0, r0, sl, lsr #16 80199be: eb00 4023 add.w r0, r0, r3, asr #16 80199c2: b29b uxth r3, r3 80199c4: ea43 4300 orr.w r3, r3, r0, lsl #16 80199c8: 4576 cmp r6, lr 80199ca: f849 3b04 str.w r3, [r9], #4 80199ce: ea4f 4c20 mov.w ip, r0, asr #16 80199d2: d8e5 bhi.n 80199a0 <__mdiff+0x88> 80199d4: 1b33 subs r3, r6, r4 80199d6: 3b15 subs r3, #21 80199d8: f023 0303 bic.w r3, r3, #3 80199dc: 3415 adds r4, #21 80199de: 3304 adds r3, #4 80199e0: 42a6 cmp r6, r4 80199e2: bf38 it cc 80199e4: 2304 movcc r3, #4 80199e6: 441d add r5, r3 80199e8: 445b add r3, fp 80199ea: 461e mov r6, r3 80199ec: 462c mov r4, r5 80199ee: 4544 cmp r4, r8 80199f0: d30e bcc.n 8019a10 <__mdiff+0xf8> 80199f2: f108 0103 add.w r1, r8, #3 80199f6: 1b49 subs r1, r1, r5 80199f8: f021 0103 bic.w r1, r1, #3 80199fc: 3d03 subs r5, #3 80199fe: 45a8 cmp r8, r5 8019a00: bf38 it cc 8019a02: 2100 movcc r1, #0 8019a04: 440b add r3, r1 8019a06: f853 1d04 ldr.w r1, [r3, #-4]! 8019a0a: b191 cbz r1, 8019a32 <__mdiff+0x11a> 8019a0c: 6117 str r7, [r2, #16] 8019a0e: e79d b.n 801994c <__mdiff+0x34> 8019a10: f854 1b04 ldr.w r1, [r4], #4 8019a14: 46e6 mov lr, ip 8019a16: 0c08 lsrs r0, r1, #16 8019a18: fa1c fc81 uxtah ip, ip, r1 8019a1c: 4471 add r1, lr 8019a1e: eb00 402c add.w r0, r0, ip, asr #16 8019a22: b289 uxth r1, r1 8019a24: ea41 4100 orr.w r1, r1, r0, lsl #16 8019a28: f846 1b04 str.w r1, [r6], #4 8019a2c: ea4f 4c20 mov.w ip, r0, asr #16 8019a30: e7dd b.n 80199ee <__mdiff+0xd6> 8019a32: 3f01 subs r7, #1 8019a34: e7e7 b.n 8019a06 <__mdiff+0xee> 8019a36: bf00 nop 8019a38: 0801a378 .word 0x0801a378 8019a3c: 0801a389 .word 0x0801a389 08019a40 <__d2b>: 8019a40: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} 8019a44: 460f mov r7, r1 8019a46: 2101 movs r1, #1 8019a48: ec59 8b10 vmov r8, r9, d0 8019a4c: 4616 mov r6, r2 8019a4e: f7ff fccd bl 80193ec <_Balloc> 8019a52: 4604 mov r4, r0 8019a54: b930 cbnz r0, 8019a64 <__d2b+0x24> 8019a56: 4602 mov r2, r0 8019a58: 4b23 ldr r3, [pc, #140] @ (8019ae8 <__d2b+0xa8>) 8019a5a: 4824 ldr r0, [pc, #144] @ (8019aec <__d2b+0xac>) 8019a5c: f240 310f movw r1, #783 @ 0x30f 8019a60: f000 f986 bl 8019d70 <__assert_func> 8019a64: f3c9 550a ubfx r5, r9, #20, #11 8019a68: f3c9 0313 ubfx r3, r9, #0, #20 8019a6c: b10d cbz r5, 8019a72 <__d2b+0x32> 8019a6e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8019a72: 9301 str r3, [sp, #4] 8019a74: f1b8 0300 subs.w r3, r8, #0 8019a78: d023 beq.n 8019ac2 <__d2b+0x82> 8019a7a: 4668 mov r0, sp 8019a7c: 9300 str r3, [sp, #0] 8019a7e: f7ff fd7c bl 801957a <__lo0bits> 8019a82: e9dd 1200 ldrd r1, r2, [sp] 8019a86: b1d0 cbz r0, 8019abe <__d2b+0x7e> 8019a88: f1c0 0320 rsb r3, r0, #32 8019a8c: fa02 f303 lsl.w r3, r2, r3 8019a90: 430b orrs r3, r1 8019a92: 40c2 lsrs r2, r0 8019a94: 6163 str r3, [r4, #20] 8019a96: 9201 str r2, [sp, #4] 8019a98: 9b01 ldr r3, [sp, #4] 8019a9a: 61a3 str r3, [r4, #24] 8019a9c: 2b00 cmp r3, #0 8019a9e: bf0c ite eq 8019aa0: 2201 moveq r2, #1 8019aa2: 2202 movne r2, #2 8019aa4: 6122 str r2, [r4, #16] 8019aa6: b1a5 cbz r5, 8019ad2 <__d2b+0x92> 8019aa8: f2a5 4533 subw r5, r5, #1075 @ 0x433 8019aac: 4405 add r5, r0 8019aae: 603d str r5, [r7, #0] 8019ab0: f1c0 0035 rsb r0, r0, #53 @ 0x35 8019ab4: 6030 str r0, [r6, #0] 8019ab6: 4620 mov r0, r4 8019ab8: b003 add sp, #12 8019aba: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 8019abe: 6161 str r1, [r4, #20] 8019ac0: e7ea b.n 8019a98 <__d2b+0x58> 8019ac2: a801 add r0, sp, #4 8019ac4: f7ff fd59 bl 801957a <__lo0bits> 8019ac8: 9b01 ldr r3, [sp, #4] 8019aca: 6163 str r3, [r4, #20] 8019acc: 3020 adds r0, #32 8019ace: 2201 movs r2, #1 8019ad0: e7e8 b.n 8019aa4 <__d2b+0x64> 8019ad2: eb04 0382 add.w r3, r4, r2, lsl #2 8019ad6: f2a0 4032 subw r0, r0, #1074 @ 0x432 8019ada: 6038 str r0, [r7, #0] 8019adc: 6918 ldr r0, [r3, #16] 8019ade: f7ff fd2d bl 801953c <__hi0bits> 8019ae2: ebc0 1042 rsb r0, r0, r2, lsl #5 8019ae6: e7e5 b.n 8019ab4 <__d2b+0x74> 8019ae8: 0801a378 .word 0x0801a378 8019aec: 0801a389 .word 0x0801a389 08019af0 <__sflush_r>: 8019af0: f9b1 200c ldrsh.w r2, [r1, #12] 8019af4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8019af8: 0716 lsls r6, r2, #28 8019afa: 4605 mov r5, r0 8019afc: 460c mov r4, r1 8019afe: d454 bmi.n 8019baa <__sflush_r+0xba> 8019b00: 684b ldr r3, [r1, #4] 8019b02: 2b00 cmp r3, #0 8019b04: dc02 bgt.n 8019b0c <__sflush_r+0x1c> 8019b06: 6c0b ldr r3, [r1, #64] @ 0x40 8019b08: 2b00 cmp r3, #0 8019b0a: dd48 ble.n 8019b9e <__sflush_r+0xae> 8019b0c: 6ae6 ldr r6, [r4, #44] @ 0x2c 8019b0e: 2e00 cmp r6, #0 8019b10: d045 beq.n 8019b9e <__sflush_r+0xae> 8019b12: 2300 movs r3, #0 8019b14: f412 5280 ands.w r2, r2, #4096 @ 0x1000 8019b18: 682f ldr r7, [r5, #0] 8019b1a: 6a21 ldr r1, [r4, #32] 8019b1c: 602b str r3, [r5, #0] 8019b1e: d030 beq.n 8019b82 <__sflush_r+0x92> 8019b20: 6d62 ldr r2, [r4, #84] @ 0x54 8019b22: 89a3 ldrh r3, [r4, #12] 8019b24: 0759 lsls r1, r3, #29 8019b26: d505 bpl.n 8019b34 <__sflush_r+0x44> 8019b28: 6863 ldr r3, [r4, #4] 8019b2a: 1ad2 subs r2, r2, r3 8019b2c: 6b63 ldr r3, [r4, #52] @ 0x34 8019b2e: b10b cbz r3, 8019b34 <__sflush_r+0x44> 8019b30: 6c23 ldr r3, [r4, #64] @ 0x40 8019b32: 1ad2 subs r2, r2, r3 8019b34: 2300 movs r3, #0 8019b36: 6ae6 ldr r6, [r4, #44] @ 0x2c 8019b38: 6a21 ldr r1, [r4, #32] 8019b3a: 4628 mov r0, r5 8019b3c: 47b0 blx r6 8019b3e: 1c43 adds r3, r0, #1 8019b40: 89a3 ldrh r3, [r4, #12] 8019b42: d106 bne.n 8019b52 <__sflush_r+0x62> 8019b44: 6829 ldr r1, [r5, #0] 8019b46: 291d cmp r1, #29 8019b48: d82b bhi.n 8019ba2 <__sflush_r+0xb2> 8019b4a: 4a2a ldr r2, [pc, #168] @ (8019bf4 <__sflush_r+0x104>) 8019b4c: 410a asrs r2, r1 8019b4e: 07d6 lsls r6, r2, #31 8019b50: d427 bmi.n 8019ba2 <__sflush_r+0xb2> 8019b52: 2200 movs r2, #0 8019b54: 6062 str r2, [r4, #4] 8019b56: 04d9 lsls r1, r3, #19 8019b58: 6922 ldr r2, [r4, #16] 8019b5a: 6022 str r2, [r4, #0] 8019b5c: d504 bpl.n 8019b68 <__sflush_r+0x78> 8019b5e: 1c42 adds r2, r0, #1 8019b60: d101 bne.n 8019b66 <__sflush_r+0x76> 8019b62: 682b ldr r3, [r5, #0] 8019b64: b903 cbnz r3, 8019b68 <__sflush_r+0x78> 8019b66: 6560 str r0, [r4, #84] @ 0x54 8019b68: 6b61 ldr r1, [r4, #52] @ 0x34 8019b6a: 602f str r7, [r5, #0] 8019b6c: b1b9 cbz r1, 8019b9e <__sflush_r+0xae> 8019b6e: f104 0344 add.w r3, r4, #68 @ 0x44 8019b72: 4299 cmp r1, r3 8019b74: d002 beq.n 8019b7c <__sflush_r+0x8c> 8019b76: 4628 mov r0, r5 8019b78: f7ff fb38 bl 80191ec <_free_r> 8019b7c: 2300 movs r3, #0 8019b7e: 6363 str r3, [r4, #52] @ 0x34 8019b80: e00d b.n 8019b9e <__sflush_r+0xae> 8019b82: 2301 movs r3, #1 8019b84: 4628 mov r0, r5 8019b86: 47b0 blx r6 8019b88: 4602 mov r2, r0 8019b8a: 1c50 adds r0, r2, #1 8019b8c: d1c9 bne.n 8019b22 <__sflush_r+0x32> 8019b8e: 682b ldr r3, [r5, #0] 8019b90: 2b00 cmp r3, #0 8019b92: d0c6 beq.n 8019b22 <__sflush_r+0x32> 8019b94: 2b1d cmp r3, #29 8019b96: d001 beq.n 8019b9c <__sflush_r+0xac> 8019b98: 2b16 cmp r3, #22 8019b9a: d11e bne.n 8019bda <__sflush_r+0xea> 8019b9c: 602f str r7, [r5, #0] 8019b9e: 2000 movs r0, #0 8019ba0: e022 b.n 8019be8 <__sflush_r+0xf8> 8019ba2: f043 0340 orr.w r3, r3, #64 @ 0x40 8019ba6: b21b sxth r3, r3 8019ba8: e01b b.n 8019be2 <__sflush_r+0xf2> 8019baa: 690f ldr r7, [r1, #16] 8019bac: 2f00 cmp r7, #0 8019bae: d0f6 beq.n 8019b9e <__sflush_r+0xae> 8019bb0: 0793 lsls r3, r2, #30 8019bb2: 680e ldr r6, [r1, #0] 8019bb4: bf08 it eq 8019bb6: 694b ldreq r3, [r1, #20] 8019bb8: 600f str r7, [r1, #0] 8019bba: bf18 it ne 8019bbc: 2300 movne r3, #0 8019bbe: eba6 0807 sub.w r8, r6, r7 8019bc2: 608b str r3, [r1, #8] 8019bc4: f1b8 0f00 cmp.w r8, #0 8019bc8: dde9 ble.n 8019b9e <__sflush_r+0xae> 8019bca: 6a21 ldr r1, [r4, #32] 8019bcc: 6aa6 ldr r6, [r4, #40] @ 0x28 8019bce: 4643 mov r3, r8 8019bd0: 463a mov r2, r7 8019bd2: 4628 mov r0, r5 8019bd4: 47b0 blx r6 8019bd6: 2800 cmp r0, #0 8019bd8: dc08 bgt.n 8019bec <__sflush_r+0xfc> 8019bda: f9b4 300c ldrsh.w r3, [r4, #12] 8019bde: f043 0340 orr.w r3, r3, #64 @ 0x40 8019be2: 81a3 strh r3, [r4, #12] 8019be4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8019be8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8019bec: 4407 add r7, r0 8019bee: eba8 0800 sub.w r8, r8, r0 8019bf2: e7e7 b.n 8019bc4 <__sflush_r+0xd4> 8019bf4: dfbffffe .word 0xdfbffffe 08019bf8 <_fflush_r>: 8019bf8: b538 push {r3, r4, r5, lr} 8019bfa: 690b ldr r3, [r1, #16] 8019bfc: 4605 mov r5, r0 8019bfe: 460c mov r4, r1 8019c00: b913 cbnz r3, 8019c08 <_fflush_r+0x10> 8019c02: 2500 movs r5, #0 8019c04: 4628 mov r0, r5 8019c06: bd38 pop {r3, r4, r5, pc} 8019c08: b118 cbz r0, 8019c12 <_fflush_r+0x1a> 8019c0a: 6a03 ldr r3, [r0, #32] 8019c0c: b90b cbnz r3, 8019c12 <_fflush_r+0x1a> 8019c0e: f7fe fabf bl 8018190 <__sinit> 8019c12: f9b4 300c ldrsh.w r3, [r4, #12] 8019c16: 2b00 cmp r3, #0 8019c18: d0f3 beq.n 8019c02 <_fflush_r+0xa> 8019c1a: 6e62 ldr r2, [r4, #100] @ 0x64 8019c1c: 07d0 lsls r0, r2, #31 8019c1e: d404 bmi.n 8019c2a <_fflush_r+0x32> 8019c20: 0599 lsls r1, r3, #22 8019c22: d402 bmi.n 8019c2a <_fflush_r+0x32> 8019c24: 6da0 ldr r0, [r4, #88] @ 0x58 8019c26: f7fe fcf2 bl 801860e <__retarget_lock_acquire_recursive> 8019c2a: 4628 mov r0, r5 8019c2c: 4621 mov r1, r4 8019c2e: f7ff ff5f bl 8019af0 <__sflush_r> 8019c32: 6e63 ldr r3, [r4, #100] @ 0x64 8019c34: 07da lsls r2, r3, #31 8019c36: 4605 mov r5, r0 8019c38: d4e4 bmi.n 8019c04 <_fflush_r+0xc> 8019c3a: 89a3 ldrh r3, [r4, #12] 8019c3c: 059b lsls r3, r3, #22 8019c3e: d4e1 bmi.n 8019c04 <_fflush_r+0xc> 8019c40: 6da0 ldr r0, [r4, #88] @ 0x58 8019c42: f7fe fce5 bl 8018610 <__retarget_lock_release_recursive> 8019c46: e7dd b.n 8019c04 <_fflush_r+0xc> 08019c48 <__swhatbuf_r>: 8019c48: b570 push {r4, r5, r6, lr} 8019c4a: 460c mov r4, r1 8019c4c: f9b1 100e ldrsh.w r1, [r1, #14] 8019c50: 2900 cmp r1, #0 8019c52: b096 sub sp, #88 @ 0x58 8019c54: 4615 mov r5, r2 8019c56: 461e mov r6, r3 8019c58: da0d bge.n 8019c76 <__swhatbuf_r+0x2e> 8019c5a: 89a3 ldrh r3, [r4, #12] 8019c5c: f013 0f80 tst.w r3, #128 @ 0x80 8019c60: f04f 0100 mov.w r1, #0 8019c64: bf14 ite ne 8019c66: 2340 movne r3, #64 @ 0x40 8019c68: f44f 6380 moveq.w r3, #1024 @ 0x400 8019c6c: 2000 movs r0, #0 8019c6e: 6031 str r1, [r6, #0] 8019c70: 602b str r3, [r5, #0] 8019c72: b016 add sp, #88 @ 0x58 8019c74: bd70 pop {r4, r5, r6, pc} 8019c76: 466a mov r2, sp 8019c78: f000 f848 bl 8019d0c <_fstat_r> 8019c7c: 2800 cmp r0, #0 8019c7e: dbec blt.n 8019c5a <__swhatbuf_r+0x12> 8019c80: 9901 ldr r1, [sp, #4] 8019c82: f401 4170 and.w r1, r1, #61440 @ 0xf000 8019c86: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 8019c8a: 4259 negs r1, r3 8019c8c: 4159 adcs r1, r3 8019c8e: f44f 6380 mov.w r3, #1024 @ 0x400 8019c92: e7eb b.n 8019c6c <__swhatbuf_r+0x24> 08019c94 <__smakebuf_r>: 8019c94: 898b ldrh r3, [r1, #12] 8019c96: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8019c98: 079d lsls r5, r3, #30 8019c9a: 4606 mov r6, r0 8019c9c: 460c mov r4, r1 8019c9e: d507 bpl.n 8019cb0 <__smakebuf_r+0x1c> 8019ca0: f104 0347 add.w r3, r4, #71 @ 0x47 8019ca4: 6023 str r3, [r4, #0] 8019ca6: 6123 str r3, [r4, #16] 8019ca8: 2301 movs r3, #1 8019caa: 6163 str r3, [r4, #20] 8019cac: b003 add sp, #12 8019cae: bdf0 pop {r4, r5, r6, r7, pc} 8019cb0: ab01 add r3, sp, #4 8019cb2: 466a mov r2, sp 8019cb4: f7ff ffc8 bl 8019c48 <__swhatbuf_r> 8019cb8: 9f00 ldr r7, [sp, #0] 8019cba: 4605 mov r5, r0 8019cbc: 4639 mov r1, r7 8019cbe: 4630 mov r0, r6 8019cc0: f7ff fb08 bl 80192d4 <_malloc_r> 8019cc4: b948 cbnz r0, 8019cda <__smakebuf_r+0x46> 8019cc6: f9b4 300c ldrsh.w r3, [r4, #12] 8019cca: 059a lsls r2, r3, #22 8019ccc: d4ee bmi.n 8019cac <__smakebuf_r+0x18> 8019cce: f023 0303 bic.w r3, r3, #3 8019cd2: f043 0302 orr.w r3, r3, #2 8019cd6: 81a3 strh r3, [r4, #12] 8019cd8: e7e2 b.n 8019ca0 <__smakebuf_r+0xc> 8019cda: 89a3 ldrh r3, [r4, #12] 8019cdc: 6020 str r0, [r4, #0] 8019cde: f043 0380 orr.w r3, r3, #128 @ 0x80 8019ce2: 81a3 strh r3, [r4, #12] 8019ce4: 9b01 ldr r3, [sp, #4] 8019ce6: e9c4 0704 strd r0, r7, [r4, #16] 8019cea: b15b cbz r3, 8019d04 <__smakebuf_r+0x70> 8019cec: f9b4 100e ldrsh.w r1, [r4, #14] 8019cf0: 4630 mov r0, r6 8019cf2: f000 f81d bl 8019d30 <_isatty_r> 8019cf6: b128 cbz r0, 8019d04 <__smakebuf_r+0x70> 8019cf8: 89a3 ldrh r3, [r4, #12] 8019cfa: f023 0303 bic.w r3, r3, #3 8019cfe: f043 0301 orr.w r3, r3, #1 8019d02: 81a3 strh r3, [r4, #12] 8019d04: 89a3 ldrh r3, [r4, #12] 8019d06: 431d orrs r5, r3 8019d08: 81a5 strh r5, [r4, #12] 8019d0a: e7cf b.n 8019cac <__smakebuf_r+0x18> 08019d0c <_fstat_r>: 8019d0c: b538 push {r3, r4, r5, lr} 8019d0e: 4d07 ldr r5, [pc, #28] @ (8019d2c <_fstat_r+0x20>) 8019d10: 2300 movs r3, #0 8019d12: 4604 mov r4, r0 8019d14: 4608 mov r0, r1 8019d16: 4611 mov r1, r2 8019d18: 602b str r3, [r5, #0] 8019d1a: f7ea fb19 bl 8004350 <_fstat> 8019d1e: 1c43 adds r3, r0, #1 8019d20: d102 bne.n 8019d28 <_fstat_r+0x1c> 8019d22: 682b ldr r3, [r5, #0] 8019d24: b103 cbz r3, 8019d28 <_fstat_r+0x1c> 8019d26: 6023 str r3, [r4, #0] 8019d28: bd38 pop {r3, r4, r5, pc} 8019d2a: bf00 nop 8019d2c: 240132e4 .word 0x240132e4 08019d30 <_isatty_r>: 8019d30: b538 push {r3, r4, r5, lr} 8019d32: 4d06 ldr r5, [pc, #24] @ (8019d4c <_isatty_r+0x1c>) 8019d34: 2300 movs r3, #0 8019d36: 4604 mov r4, r0 8019d38: 4608 mov r0, r1 8019d3a: 602b str r3, [r5, #0] 8019d3c: f7ea fb18 bl 8004370 <_isatty> 8019d40: 1c43 adds r3, r0, #1 8019d42: d102 bne.n 8019d4a <_isatty_r+0x1a> 8019d44: 682b ldr r3, [r5, #0] 8019d46: b103 cbz r3, 8019d4a <_isatty_r+0x1a> 8019d48: 6023 str r3, [r4, #0] 8019d4a: bd38 pop {r3, r4, r5, pc} 8019d4c: 240132e4 .word 0x240132e4 08019d50 <_sbrk_r>: 8019d50: b538 push {r3, r4, r5, lr} 8019d52: 4d06 ldr r5, [pc, #24] @ (8019d6c <_sbrk_r+0x1c>) 8019d54: 2300 movs r3, #0 8019d56: 4604 mov r4, r0 8019d58: 4608 mov r0, r1 8019d5a: 602b str r3, [r5, #0] 8019d5c: f7ea fb20 bl 80043a0 <_sbrk> 8019d60: 1c43 adds r3, r0, #1 8019d62: d102 bne.n 8019d6a <_sbrk_r+0x1a> 8019d64: 682b ldr r3, [r5, #0] 8019d66: b103 cbz r3, 8019d6a <_sbrk_r+0x1a> 8019d68: 6023 str r3, [r4, #0] 8019d6a: bd38 pop {r3, r4, r5, pc} 8019d6c: 240132e4 .word 0x240132e4 08019d70 <__assert_func>: 8019d70: b51f push {r0, r1, r2, r3, r4, lr} 8019d72: 4614 mov r4, r2 8019d74: 461a mov r2, r3 8019d76: 4b09 ldr r3, [pc, #36] @ (8019d9c <__assert_func+0x2c>) 8019d78: 681b ldr r3, [r3, #0] 8019d7a: 4605 mov r5, r0 8019d7c: 68d8 ldr r0, [r3, #12] 8019d7e: b954 cbnz r4, 8019d96 <__assert_func+0x26> 8019d80: 4b07 ldr r3, [pc, #28] @ (8019da0 <__assert_func+0x30>) 8019d82: 461c mov r4, r3 8019d84: e9cd 3401 strd r3, r4, [sp, #4] 8019d88: 9100 str r1, [sp, #0] 8019d8a: 462b mov r3, r5 8019d8c: 4905 ldr r1, [pc, #20] @ (8019da4 <__assert_func+0x34>) 8019d8e: f000 f841 bl 8019e14 8019d92: f000 f851 bl 8019e38 8019d96: 4b04 ldr r3, [pc, #16] @ (8019da8 <__assert_func+0x38>) 8019d98: e7f4 b.n 8019d84 <__assert_func+0x14> 8019d9a: bf00 nop 8019d9c: 24000054 .word 0x24000054 8019da0: 0801a525 .word 0x0801a525 8019da4: 0801a4f7 .word 0x0801a4f7 8019da8: 0801a4ea .word 0x0801a4ea 08019dac <_calloc_r>: 8019dac: b570 push {r4, r5, r6, lr} 8019dae: fba1 5402 umull r5, r4, r1, r2 8019db2: b93c cbnz r4, 8019dc4 <_calloc_r+0x18> 8019db4: 4629 mov r1, r5 8019db6: f7ff fa8d bl 80192d4 <_malloc_r> 8019dba: 4606 mov r6, r0 8019dbc: b928 cbnz r0, 8019dca <_calloc_r+0x1e> 8019dbe: 2600 movs r6, #0 8019dc0: 4630 mov r0, r6 8019dc2: bd70 pop {r4, r5, r6, pc} 8019dc4: 220c movs r2, #12 8019dc6: 6002 str r2, [r0, #0] 8019dc8: e7f9 b.n 8019dbe <_calloc_r+0x12> 8019dca: 462a mov r2, r5 8019dcc: 4621 mov r1, r4 8019dce: f7fe fb4b bl 8018468 8019dd2: e7f5 b.n 8019dc0 <_calloc_r+0x14> 08019dd4 <__ascii_mbtowc>: 8019dd4: b082 sub sp, #8 8019dd6: b901 cbnz r1, 8019dda <__ascii_mbtowc+0x6> 8019dd8: a901 add r1, sp, #4 8019dda: b142 cbz r2, 8019dee <__ascii_mbtowc+0x1a> 8019ddc: b14b cbz r3, 8019df2 <__ascii_mbtowc+0x1e> 8019dde: 7813 ldrb r3, [r2, #0] 8019de0: 600b str r3, [r1, #0] 8019de2: 7812 ldrb r2, [r2, #0] 8019de4: 1e10 subs r0, r2, #0 8019de6: bf18 it ne 8019de8: 2001 movne r0, #1 8019dea: b002 add sp, #8 8019dec: 4770 bx lr 8019dee: 4610 mov r0, r2 8019df0: e7fb b.n 8019dea <__ascii_mbtowc+0x16> 8019df2: f06f 0001 mvn.w r0, #1 8019df6: e7f8 b.n 8019dea <__ascii_mbtowc+0x16> 08019df8 <__ascii_wctomb>: 8019df8: 4603 mov r3, r0 8019dfa: 4608 mov r0, r1 8019dfc: b141 cbz r1, 8019e10 <__ascii_wctomb+0x18> 8019dfe: 2aff cmp r2, #255 @ 0xff 8019e00: d904 bls.n 8019e0c <__ascii_wctomb+0x14> 8019e02: 228a movs r2, #138 @ 0x8a 8019e04: 601a str r2, [r3, #0] 8019e06: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8019e0a: 4770 bx lr 8019e0c: 700a strb r2, [r1, #0] 8019e0e: 2001 movs r0, #1 8019e10: 4770 bx lr ... 08019e14 : 8019e14: b40e push {r1, r2, r3} 8019e16: b503 push {r0, r1, lr} 8019e18: 4601 mov r1, r0 8019e1a: ab03 add r3, sp, #12 8019e1c: 4805 ldr r0, [pc, #20] @ (8019e34 ) 8019e1e: f853 2b04 ldr.w r2, [r3], #4 8019e22: 6800 ldr r0, [r0, #0] 8019e24: 9301 str r3, [sp, #4] 8019e26: f000 f837 bl 8019e98 <_vfiprintf_r> 8019e2a: b002 add sp, #8 8019e2c: f85d eb04 ldr.w lr, [sp], #4 8019e30: b003 add sp, #12 8019e32: 4770 bx lr 8019e34: 24000054 .word 0x24000054 08019e38 : 8019e38: b508 push {r3, lr} 8019e3a: 2006 movs r0, #6 8019e3c: f000 f96c bl 801a118 8019e40: 2001 movs r0, #1 8019e42: f7ea fa35 bl 80042b0 <_exit> 08019e46 <__sfputc_r>: 8019e46: 6893 ldr r3, [r2, #8] 8019e48: 3b01 subs r3, #1 8019e4a: 2b00 cmp r3, #0 8019e4c: b410 push {r4} 8019e4e: 6093 str r3, [r2, #8] 8019e50: da08 bge.n 8019e64 <__sfputc_r+0x1e> 8019e52: 6994 ldr r4, [r2, #24] 8019e54: 42a3 cmp r3, r4 8019e56: db01 blt.n 8019e5c <__sfputc_r+0x16> 8019e58: 290a cmp r1, #10 8019e5a: d103 bne.n 8019e64 <__sfputc_r+0x1e> 8019e5c: f85d 4b04 ldr.w r4, [sp], #4 8019e60: f7fe ba6d b.w 801833e <__swbuf_r> 8019e64: 6813 ldr r3, [r2, #0] 8019e66: 1c58 adds r0, r3, #1 8019e68: 6010 str r0, [r2, #0] 8019e6a: 7019 strb r1, [r3, #0] 8019e6c: 4608 mov r0, r1 8019e6e: f85d 4b04 ldr.w r4, [sp], #4 8019e72: 4770 bx lr 08019e74 <__sfputs_r>: 8019e74: b5f8 push {r3, r4, r5, r6, r7, lr} 8019e76: 4606 mov r6, r0 8019e78: 460f mov r7, r1 8019e7a: 4614 mov r4, r2 8019e7c: 18d5 adds r5, r2, r3 8019e7e: 42ac cmp r4, r5 8019e80: d101 bne.n 8019e86 <__sfputs_r+0x12> 8019e82: 2000 movs r0, #0 8019e84: e007 b.n 8019e96 <__sfputs_r+0x22> 8019e86: f814 1b01 ldrb.w r1, [r4], #1 8019e8a: 463a mov r2, r7 8019e8c: 4630 mov r0, r6 8019e8e: f7ff ffda bl 8019e46 <__sfputc_r> 8019e92: 1c43 adds r3, r0, #1 8019e94: d1f3 bne.n 8019e7e <__sfputs_r+0xa> 8019e96: bdf8 pop {r3, r4, r5, r6, r7, pc} 08019e98 <_vfiprintf_r>: 8019e98: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8019e9c: 460d mov r5, r1 8019e9e: b09d sub sp, #116 @ 0x74 8019ea0: 4614 mov r4, r2 8019ea2: 4698 mov r8, r3 8019ea4: 4606 mov r6, r0 8019ea6: b118 cbz r0, 8019eb0 <_vfiprintf_r+0x18> 8019ea8: 6a03 ldr r3, [r0, #32] 8019eaa: b90b cbnz r3, 8019eb0 <_vfiprintf_r+0x18> 8019eac: f7fe f970 bl 8018190 <__sinit> 8019eb0: 6e6b ldr r3, [r5, #100] @ 0x64 8019eb2: 07d9 lsls r1, r3, #31 8019eb4: d405 bmi.n 8019ec2 <_vfiprintf_r+0x2a> 8019eb6: 89ab ldrh r3, [r5, #12] 8019eb8: 059a lsls r2, r3, #22 8019eba: d402 bmi.n 8019ec2 <_vfiprintf_r+0x2a> 8019ebc: 6da8 ldr r0, [r5, #88] @ 0x58 8019ebe: f7fe fba6 bl 801860e <__retarget_lock_acquire_recursive> 8019ec2: 89ab ldrh r3, [r5, #12] 8019ec4: 071b lsls r3, r3, #28 8019ec6: d501 bpl.n 8019ecc <_vfiprintf_r+0x34> 8019ec8: 692b ldr r3, [r5, #16] 8019eca: b99b cbnz r3, 8019ef4 <_vfiprintf_r+0x5c> 8019ecc: 4629 mov r1, r5 8019ece: 4630 mov r0, r6 8019ed0: f7fe fa74 bl 80183bc <__swsetup_r> 8019ed4: b170 cbz r0, 8019ef4 <_vfiprintf_r+0x5c> 8019ed6: 6e6b ldr r3, [r5, #100] @ 0x64 8019ed8: 07dc lsls r4, r3, #31 8019eda: d504 bpl.n 8019ee6 <_vfiprintf_r+0x4e> 8019edc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8019ee0: b01d add sp, #116 @ 0x74 8019ee2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8019ee6: 89ab ldrh r3, [r5, #12] 8019ee8: 0598 lsls r0, r3, #22 8019eea: d4f7 bmi.n 8019edc <_vfiprintf_r+0x44> 8019eec: 6da8 ldr r0, [r5, #88] @ 0x58 8019eee: f7fe fb8f bl 8018610 <__retarget_lock_release_recursive> 8019ef2: e7f3 b.n 8019edc <_vfiprintf_r+0x44> 8019ef4: 2300 movs r3, #0 8019ef6: 9309 str r3, [sp, #36] @ 0x24 8019ef8: 2320 movs r3, #32 8019efa: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8019efe: f8cd 800c str.w r8, [sp, #12] 8019f02: 2330 movs r3, #48 @ 0x30 8019f04: f8df 81ac ldr.w r8, [pc, #428] @ 801a0b4 <_vfiprintf_r+0x21c> 8019f08: f88d 302a strb.w r3, [sp, #42] @ 0x2a 8019f0c: f04f 0901 mov.w r9, #1 8019f10: 4623 mov r3, r4 8019f12: 469a mov sl, r3 8019f14: f813 2b01 ldrb.w r2, [r3], #1 8019f18: b10a cbz r2, 8019f1e <_vfiprintf_r+0x86> 8019f1a: 2a25 cmp r2, #37 @ 0x25 8019f1c: d1f9 bne.n 8019f12 <_vfiprintf_r+0x7a> 8019f1e: ebba 0b04 subs.w fp, sl, r4 8019f22: d00b beq.n 8019f3c <_vfiprintf_r+0xa4> 8019f24: 465b mov r3, fp 8019f26: 4622 mov r2, r4 8019f28: 4629 mov r1, r5 8019f2a: 4630 mov r0, r6 8019f2c: f7ff ffa2 bl 8019e74 <__sfputs_r> 8019f30: 3001 adds r0, #1 8019f32: f000 80a7 beq.w 801a084 <_vfiprintf_r+0x1ec> 8019f36: 9a09 ldr r2, [sp, #36] @ 0x24 8019f38: 445a add r2, fp 8019f3a: 9209 str r2, [sp, #36] @ 0x24 8019f3c: f89a 3000 ldrb.w r3, [sl] 8019f40: 2b00 cmp r3, #0 8019f42: f000 809f beq.w 801a084 <_vfiprintf_r+0x1ec> 8019f46: 2300 movs r3, #0 8019f48: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8019f4c: e9cd 2305 strd r2, r3, [sp, #20] 8019f50: f10a 0a01 add.w sl, sl, #1 8019f54: 9304 str r3, [sp, #16] 8019f56: 9307 str r3, [sp, #28] 8019f58: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8019f5c: 931a str r3, [sp, #104] @ 0x68 8019f5e: 4654 mov r4, sl 8019f60: 2205 movs r2, #5 8019f62: f814 1b01 ldrb.w r1, [r4], #1 8019f66: 4853 ldr r0, [pc, #332] @ (801a0b4 <_vfiprintf_r+0x21c>) 8019f68: f7e6 f9ba bl 80002e0 8019f6c: 9a04 ldr r2, [sp, #16] 8019f6e: b9d8 cbnz r0, 8019fa8 <_vfiprintf_r+0x110> 8019f70: 06d1 lsls r1, r2, #27 8019f72: bf44 itt mi 8019f74: 2320 movmi r3, #32 8019f76: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8019f7a: 0713 lsls r3, r2, #28 8019f7c: bf44 itt mi 8019f7e: 232b movmi r3, #43 @ 0x2b 8019f80: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8019f84: f89a 3000 ldrb.w r3, [sl] 8019f88: 2b2a cmp r3, #42 @ 0x2a 8019f8a: d015 beq.n 8019fb8 <_vfiprintf_r+0x120> 8019f8c: 9a07 ldr r2, [sp, #28] 8019f8e: 4654 mov r4, sl 8019f90: 2000 movs r0, #0 8019f92: f04f 0c0a mov.w ip, #10 8019f96: 4621 mov r1, r4 8019f98: f811 3b01 ldrb.w r3, [r1], #1 8019f9c: 3b30 subs r3, #48 @ 0x30 8019f9e: 2b09 cmp r3, #9 8019fa0: d94b bls.n 801a03a <_vfiprintf_r+0x1a2> 8019fa2: b1b0 cbz r0, 8019fd2 <_vfiprintf_r+0x13a> 8019fa4: 9207 str r2, [sp, #28] 8019fa6: e014 b.n 8019fd2 <_vfiprintf_r+0x13a> 8019fa8: eba0 0308 sub.w r3, r0, r8 8019fac: fa09 f303 lsl.w r3, r9, r3 8019fb0: 4313 orrs r3, r2 8019fb2: 9304 str r3, [sp, #16] 8019fb4: 46a2 mov sl, r4 8019fb6: e7d2 b.n 8019f5e <_vfiprintf_r+0xc6> 8019fb8: 9b03 ldr r3, [sp, #12] 8019fba: 1d19 adds r1, r3, #4 8019fbc: 681b ldr r3, [r3, #0] 8019fbe: 9103 str r1, [sp, #12] 8019fc0: 2b00 cmp r3, #0 8019fc2: bfbb ittet lt 8019fc4: 425b neglt r3, r3 8019fc6: f042 0202 orrlt.w r2, r2, #2 8019fca: 9307 strge r3, [sp, #28] 8019fcc: 9307 strlt r3, [sp, #28] 8019fce: bfb8 it lt 8019fd0: 9204 strlt r2, [sp, #16] 8019fd2: 7823 ldrb r3, [r4, #0] 8019fd4: 2b2e cmp r3, #46 @ 0x2e 8019fd6: d10a bne.n 8019fee <_vfiprintf_r+0x156> 8019fd8: 7863 ldrb r3, [r4, #1] 8019fda: 2b2a cmp r3, #42 @ 0x2a 8019fdc: d132 bne.n 801a044 <_vfiprintf_r+0x1ac> 8019fde: 9b03 ldr r3, [sp, #12] 8019fe0: 1d1a adds r2, r3, #4 8019fe2: 681b ldr r3, [r3, #0] 8019fe4: 9203 str r2, [sp, #12] 8019fe6: ea43 73e3 orr.w r3, r3, r3, asr #31 8019fea: 3402 adds r4, #2 8019fec: 9305 str r3, [sp, #20] 8019fee: f8df a0d4 ldr.w sl, [pc, #212] @ 801a0c4 <_vfiprintf_r+0x22c> 8019ff2: 7821 ldrb r1, [r4, #0] 8019ff4: 2203 movs r2, #3 8019ff6: 4650 mov r0, sl 8019ff8: f7e6 f972 bl 80002e0 8019ffc: b138 cbz r0, 801a00e <_vfiprintf_r+0x176> 8019ffe: 9b04 ldr r3, [sp, #16] 801a000: eba0 000a sub.w r0, r0, sl 801a004: 2240 movs r2, #64 @ 0x40 801a006: 4082 lsls r2, r0 801a008: 4313 orrs r3, r2 801a00a: 3401 adds r4, #1 801a00c: 9304 str r3, [sp, #16] 801a00e: f814 1b01 ldrb.w r1, [r4], #1 801a012: 4829 ldr r0, [pc, #164] @ (801a0b8 <_vfiprintf_r+0x220>) 801a014: f88d 1028 strb.w r1, [sp, #40] @ 0x28 801a018: 2206 movs r2, #6 801a01a: f7e6 f961 bl 80002e0 801a01e: 2800 cmp r0, #0 801a020: d03f beq.n 801a0a2 <_vfiprintf_r+0x20a> 801a022: 4b26 ldr r3, [pc, #152] @ (801a0bc <_vfiprintf_r+0x224>) 801a024: bb1b cbnz r3, 801a06e <_vfiprintf_r+0x1d6> 801a026: 9b03 ldr r3, [sp, #12] 801a028: 3307 adds r3, #7 801a02a: f023 0307 bic.w r3, r3, #7 801a02e: 3308 adds r3, #8 801a030: 9303 str r3, [sp, #12] 801a032: 9b09 ldr r3, [sp, #36] @ 0x24 801a034: 443b add r3, r7 801a036: 9309 str r3, [sp, #36] @ 0x24 801a038: e76a b.n 8019f10 <_vfiprintf_r+0x78> 801a03a: fb0c 3202 mla r2, ip, r2, r3 801a03e: 460c mov r4, r1 801a040: 2001 movs r0, #1 801a042: e7a8 b.n 8019f96 <_vfiprintf_r+0xfe> 801a044: 2300 movs r3, #0 801a046: 3401 adds r4, #1 801a048: 9305 str r3, [sp, #20] 801a04a: 4619 mov r1, r3 801a04c: f04f 0c0a mov.w ip, #10 801a050: 4620 mov r0, r4 801a052: f810 2b01 ldrb.w r2, [r0], #1 801a056: 3a30 subs r2, #48 @ 0x30 801a058: 2a09 cmp r2, #9 801a05a: d903 bls.n 801a064 <_vfiprintf_r+0x1cc> 801a05c: 2b00 cmp r3, #0 801a05e: d0c6 beq.n 8019fee <_vfiprintf_r+0x156> 801a060: 9105 str r1, [sp, #20] 801a062: e7c4 b.n 8019fee <_vfiprintf_r+0x156> 801a064: fb0c 2101 mla r1, ip, r1, r2 801a068: 4604 mov r4, r0 801a06a: 2301 movs r3, #1 801a06c: e7f0 b.n 801a050 <_vfiprintf_r+0x1b8> 801a06e: ab03 add r3, sp, #12 801a070: 9300 str r3, [sp, #0] 801a072: 462a mov r2, r5 801a074: 4b12 ldr r3, [pc, #72] @ (801a0c0 <_vfiprintf_r+0x228>) 801a076: a904 add r1, sp, #16 801a078: 4630 mov r0, r6 801a07a: f7fd fc55 bl 8017928 <_printf_float> 801a07e: 4607 mov r7, r0 801a080: 1c78 adds r0, r7, #1 801a082: d1d6 bne.n 801a032 <_vfiprintf_r+0x19a> 801a084: 6e6b ldr r3, [r5, #100] @ 0x64 801a086: 07d9 lsls r1, r3, #31 801a088: d405 bmi.n 801a096 <_vfiprintf_r+0x1fe> 801a08a: 89ab ldrh r3, [r5, #12] 801a08c: 059a lsls r2, r3, #22 801a08e: d402 bmi.n 801a096 <_vfiprintf_r+0x1fe> 801a090: 6da8 ldr r0, [r5, #88] @ 0x58 801a092: f7fe fabd bl 8018610 <__retarget_lock_release_recursive> 801a096: 89ab ldrh r3, [r5, #12] 801a098: 065b lsls r3, r3, #25 801a09a: f53f af1f bmi.w 8019edc <_vfiprintf_r+0x44> 801a09e: 9809 ldr r0, [sp, #36] @ 0x24 801a0a0: e71e b.n 8019ee0 <_vfiprintf_r+0x48> 801a0a2: ab03 add r3, sp, #12 801a0a4: 9300 str r3, [sp, #0] 801a0a6: 462a mov r2, r5 801a0a8: 4b05 ldr r3, [pc, #20] @ (801a0c0 <_vfiprintf_r+0x228>) 801a0aa: a904 add r1, sp, #16 801a0ac: 4630 mov r0, r6 801a0ae: f7fd fec3 bl 8017e38 <_printf_i> 801a0b2: e7e4 b.n 801a07e <_vfiprintf_r+0x1e6> 801a0b4: 0801a627 .word 0x0801a627 801a0b8: 0801a631 .word 0x0801a631 801a0bc: 08017929 .word 0x08017929 801a0c0: 08019e75 .word 0x08019e75 801a0c4: 0801a62d .word 0x0801a62d 0801a0c8 <_raise_r>: 801a0c8: 291f cmp r1, #31 801a0ca: b538 push {r3, r4, r5, lr} 801a0cc: 4605 mov r5, r0 801a0ce: 460c mov r4, r1 801a0d0: d904 bls.n 801a0dc <_raise_r+0x14> 801a0d2: 2316 movs r3, #22 801a0d4: 6003 str r3, [r0, #0] 801a0d6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801a0da: bd38 pop {r3, r4, r5, pc} 801a0dc: 6bc2 ldr r2, [r0, #60] @ 0x3c 801a0de: b112 cbz r2, 801a0e6 <_raise_r+0x1e> 801a0e0: f852 3021 ldr.w r3, [r2, r1, lsl #2] 801a0e4: b94b cbnz r3, 801a0fa <_raise_r+0x32> 801a0e6: 4628 mov r0, r5 801a0e8: f000 f830 bl 801a14c <_getpid_r> 801a0ec: 4622 mov r2, r4 801a0ee: 4601 mov r1, r0 801a0f0: 4628 mov r0, r5 801a0f2: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 801a0f6: f000 b817 b.w 801a128 <_kill_r> 801a0fa: 2b01 cmp r3, #1 801a0fc: d00a beq.n 801a114 <_raise_r+0x4c> 801a0fe: 1c59 adds r1, r3, #1 801a100: d103 bne.n 801a10a <_raise_r+0x42> 801a102: 2316 movs r3, #22 801a104: 6003 str r3, [r0, #0] 801a106: 2001 movs r0, #1 801a108: e7e7 b.n 801a0da <_raise_r+0x12> 801a10a: 2100 movs r1, #0 801a10c: f842 1024 str.w r1, [r2, r4, lsl #2] 801a110: 4620 mov r0, r4 801a112: 4798 blx r3 801a114: 2000 movs r0, #0 801a116: e7e0 b.n 801a0da <_raise_r+0x12> 0801a118 : 801a118: 4b02 ldr r3, [pc, #8] @ (801a124 ) 801a11a: 4601 mov r1, r0 801a11c: 6818 ldr r0, [r3, #0] 801a11e: f7ff bfd3 b.w 801a0c8 <_raise_r> 801a122: bf00 nop 801a124: 24000054 .word 0x24000054 0801a128 <_kill_r>: 801a128: b538 push {r3, r4, r5, lr} 801a12a: 4d07 ldr r5, [pc, #28] @ (801a148 <_kill_r+0x20>) 801a12c: 2300 movs r3, #0 801a12e: 4604 mov r4, r0 801a130: 4608 mov r0, r1 801a132: 4611 mov r1, r2 801a134: 602b str r3, [r5, #0] 801a136: f7ea f8ab bl 8004290 <_kill> 801a13a: 1c43 adds r3, r0, #1 801a13c: d102 bne.n 801a144 <_kill_r+0x1c> 801a13e: 682b ldr r3, [r5, #0] 801a140: b103 cbz r3, 801a144 <_kill_r+0x1c> 801a142: 6023 str r3, [r4, #0] 801a144: bd38 pop {r3, r4, r5, pc} 801a146: bf00 nop 801a148: 240132e4 .word 0x240132e4 0801a14c <_getpid_r>: 801a14c: f7ea b898 b.w 8004280 <_getpid> 0801a150 : 801a150: b508 push {r3, lr} 801a152: ed2d 8b02 vpush {d8} 801a156: eeb0 8a40 vmov.f32 s16, s0 801a15a: f000 f817 bl 801a18c <__ieee754_sqrtf> 801a15e: eeb4 8a48 vcmp.f32 s16, s16 801a162: eef1 fa10 vmrs APSR_nzcv, fpscr 801a166: d60c bvs.n 801a182 801a168: eddf 8a07 vldr s17, [pc, #28] @ 801a188 801a16c: eeb4 8ae8 vcmpe.f32 s16, s17 801a170: eef1 fa10 vmrs APSR_nzcv, fpscr 801a174: d505 bpl.n 801a182 801a176: f7fe fa1f bl 80185b8 <__errno> 801a17a: ee88 0aa8 vdiv.f32 s0, s17, s17 801a17e: 2321 movs r3, #33 @ 0x21 801a180: 6003 str r3, [r0, #0] 801a182: ecbd 8b02 vpop {d8} 801a186: bd08 pop {r3, pc} 801a188: 00000000 .word 0x00000000 0801a18c <__ieee754_sqrtf>: 801a18c: eeb1 0ac0 vsqrt.f32 s0, s0 801a190: 4770 bx lr ... 0801a194 <_init>: 801a194: b5f8 push {r3, r4, r5, r6, r7, lr} 801a196: bf00 nop 801a198: bcf8 pop {r3, r4, r5, r6, r7} 801a19a: bc08 pop {r3} 801a19c: 469e mov lr, r3 801a19e: 4770 bx lr 0801a1a0 <_fini>: 801a1a0: b5f8 push {r3, r4, r5, r6, r7, lr} 801a1a2: bf00 nop 801a1a4: bcf8 pop {r3, r4, r5, r6, r7} 801a1a6: bc08 pop {r3} 801a1a8: 469e mov lr, r3 801a1aa: 4770 bx lr