OZE_Sensor.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000298 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00018430 080002a0 080002a0 000012a0 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000104 080186d0 080186d0 000196d0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM 00000008 080187d4 080187d4 000197d4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .init_array 00000004 080187dc 080187dc 000197dc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .fini_array 00000004 080187e0 080187e0 000197e0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 6 .data 00000098 24000000 080187e4 0001a000 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .bss 000130ec 240000a0 0801887c 0001a0a0 2**5 ALLOC 8 ._user_heap_stack 00000604 2401318c 0801887c 0001a18c 2**0 ALLOC 9 .ARM.attributes 0000002e 00000000 00000000 0001a098 2**0 CONTENTS, READONLY 10 .debug_info 0003516a 00000000 00000000 0001a0c6 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_abbrev 00006463 00000000 00000000 0004f230 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_aranges 00002478 00000000 00000000 00055698 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_macro 0003ef04 00000000 00000000 00057b10 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_line 00031813 00000000 00000000 00096a14 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_str 00186a2c 00000000 00000000 000c8227 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .comment 00000043 00000000 00000000 0024ec53 2**0 CONTENTS, READONLY 17 .debug_rnglists 00001c1d 00000000 00000000 0024ec96 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_frame 00009d14 00000000 00000000 002508b4 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_line_str 00000066 00000000 00000000 0025a5c8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080002a0 <__do_global_dtors_aux>: 80002a0: b510 push {r4, lr} 80002a2: 4c05 ldr r4, [pc, #20] @ (80002b8 <__do_global_dtors_aux+0x18>) 80002a4: 7823 ldrb r3, [r4, #0] 80002a6: b933 cbnz r3, 80002b6 <__do_global_dtors_aux+0x16> 80002a8: 4b04 ldr r3, [pc, #16] @ (80002bc <__do_global_dtors_aux+0x1c>) 80002aa: b113 cbz r3, 80002b2 <__do_global_dtors_aux+0x12> 80002ac: 4804 ldr r0, [pc, #16] @ (80002c0 <__do_global_dtors_aux+0x20>) 80002ae: f3af 8000 nop.w 80002b2: 2301 movs r3, #1 80002b4: 7023 strb r3, [r4, #0] 80002b6: bd10 pop {r4, pc} 80002b8: 240000a0 .word 0x240000a0 80002bc: 00000000 .word 0x00000000 80002c0: 080186b8 .word 0x080186b8 080002c4 : 80002c4: b508 push {r3, lr} 80002c6: 4b03 ldr r3, [pc, #12] @ (80002d4 ) 80002c8: b11b cbz r3, 80002d2 80002ca: 4903 ldr r1, [pc, #12] @ (80002d8 ) 80002cc: 4803 ldr r0, [pc, #12] @ (80002dc ) 80002ce: f3af 8000 nop.w 80002d2: bd08 pop {r3, pc} 80002d4: 00000000 .word 0x00000000 80002d8: 240000a4 .word 0x240000a4 80002dc: 080186b8 .word 0x080186b8 080002e0 <__aeabi_uldivmod>: 80002e0: b953 cbnz r3, 80002f8 <__aeabi_uldivmod+0x18> 80002e2: b94a cbnz r2, 80002f8 <__aeabi_uldivmod+0x18> 80002e4: 2900 cmp r1, #0 80002e6: bf08 it eq 80002e8: 2800 cmpeq r0, #0 80002ea: bf1c itt ne 80002ec: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 80002f0: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 80002f4: f000 b96a b.w 80005cc <__aeabi_idiv0> 80002f8: f1ad 0c08 sub.w ip, sp, #8 80002fc: e96d ce04 strd ip, lr, [sp, #-16]! 8000300: f000 f806 bl 8000310 <__udivmoddi4> 8000304: f8dd e004 ldr.w lr, [sp, #4] 8000308: e9dd 2302 ldrd r2, r3, [sp, #8] 800030c: b004 add sp, #16 800030e: 4770 bx lr 08000310 <__udivmoddi4>: 8000310: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000314: 9d08 ldr r5, [sp, #32] 8000316: 460c mov r4, r1 8000318: 2b00 cmp r3, #0 800031a: d14e bne.n 80003ba <__udivmoddi4+0xaa> 800031c: 4694 mov ip, r2 800031e: 458c cmp ip, r1 8000320: 4686 mov lr, r0 8000322: fab2 f282 clz r2, r2 8000326: d962 bls.n 80003ee <__udivmoddi4+0xde> 8000328: b14a cbz r2, 800033e <__udivmoddi4+0x2e> 800032a: f1c2 0320 rsb r3, r2, #32 800032e: 4091 lsls r1, r2 8000330: fa20 f303 lsr.w r3, r0, r3 8000334: fa0c fc02 lsl.w ip, ip, r2 8000338: 4319 orrs r1, r3 800033a: fa00 fe02 lsl.w lr, r0, r2 800033e: ea4f 471c mov.w r7, ip, lsr #16 8000342: fa1f f68c uxth.w r6, ip 8000346: fbb1 f4f7 udiv r4, r1, r7 800034a: ea4f 431e mov.w r3, lr, lsr #16 800034e: fb07 1114 mls r1, r7, r4, r1 8000352: ea43 4301 orr.w r3, r3, r1, lsl #16 8000356: fb04 f106 mul.w r1, r4, r6 800035a: 4299 cmp r1, r3 800035c: d90a bls.n 8000374 <__udivmoddi4+0x64> 800035e: eb1c 0303 adds.w r3, ip, r3 8000362: f104 30ff add.w r0, r4, #4294967295 @ 0xffffffff 8000366: f080 8112 bcs.w 800058e <__udivmoddi4+0x27e> 800036a: 4299 cmp r1, r3 800036c: f240 810f bls.w 800058e <__udivmoddi4+0x27e> 8000370: 3c02 subs r4, #2 8000372: 4463 add r3, ip 8000374: 1a59 subs r1, r3, r1 8000376: fa1f f38e uxth.w r3, lr 800037a: fbb1 f0f7 udiv r0, r1, r7 800037e: fb07 1110 mls r1, r7, r0, r1 8000382: ea43 4301 orr.w r3, r3, r1, lsl #16 8000386: fb00 f606 mul.w r6, r0, r6 800038a: 429e cmp r6, r3 800038c: d90a bls.n 80003a4 <__udivmoddi4+0x94> 800038e: eb1c 0303 adds.w r3, ip, r3 8000392: f100 31ff add.w r1, r0, #4294967295 @ 0xffffffff 8000396: f080 80fc bcs.w 8000592 <__udivmoddi4+0x282> 800039a: 429e cmp r6, r3 800039c: f240 80f9 bls.w 8000592 <__udivmoddi4+0x282> 80003a0: 4463 add r3, ip 80003a2: 3802 subs r0, #2 80003a4: 1b9b subs r3, r3, r6 80003a6: ea40 4004 orr.w r0, r0, r4, lsl #16 80003aa: 2100 movs r1, #0 80003ac: b11d cbz r5, 80003b6 <__udivmoddi4+0xa6> 80003ae: 40d3 lsrs r3, r2 80003b0: 2200 movs r2, #0 80003b2: e9c5 3200 strd r3, r2, [r5] 80003b6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80003ba: 428b cmp r3, r1 80003bc: d905 bls.n 80003ca <__udivmoddi4+0xba> 80003be: b10d cbz r5, 80003c4 <__udivmoddi4+0xb4> 80003c0: e9c5 0100 strd r0, r1, [r5] 80003c4: 2100 movs r1, #0 80003c6: 4608 mov r0, r1 80003c8: e7f5 b.n 80003b6 <__udivmoddi4+0xa6> 80003ca: fab3 f183 clz r1, r3 80003ce: 2900 cmp r1, #0 80003d0: d146 bne.n 8000460 <__udivmoddi4+0x150> 80003d2: 42a3 cmp r3, r4 80003d4: d302 bcc.n 80003dc <__udivmoddi4+0xcc> 80003d6: 4290 cmp r0, r2 80003d8: f0c0 80f0 bcc.w 80005bc <__udivmoddi4+0x2ac> 80003dc: 1a86 subs r6, r0, r2 80003de: eb64 0303 sbc.w r3, r4, r3 80003e2: 2001 movs r0, #1 80003e4: 2d00 cmp r5, #0 80003e6: d0e6 beq.n 80003b6 <__udivmoddi4+0xa6> 80003e8: e9c5 6300 strd r6, r3, [r5] 80003ec: e7e3 b.n 80003b6 <__udivmoddi4+0xa6> 80003ee: 2a00 cmp r2, #0 80003f0: f040 8090 bne.w 8000514 <__udivmoddi4+0x204> 80003f4: eba1 040c sub.w r4, r1, ip 80003f8: ea4f 481c mov.w r8, ip, lsr #16 80003fc: fa1f f78c uxth.w r7, ip 8000400: 2101 movs r1, #1 8000402: fbb4 f6f8 udiv r6, r4, r8 8000406: ea4f 431e mov.w r3, lr, lsr #16 800040a: fb08 4416 mls r4, r8, r6, r4 800040e: ea43 4304 orr.w r3, r3, r4, lsl #16 8000412: fb07 f006 mul.w r0, r7, r6 8000416: 4298 cmp r0, r3 8000418: d908 bls.n 800042c <__udivmoddi4+0x11c> 800041a: eb1c 0303 adds.w r3, ip, r3 800041e: f106 34ff add.w r4, r6, #4294967295 @ 0xffffffff 8000422: d202 bcs.n 800042a <__udivmoddi4+0x11a> 8000424: 4298 cmp r0, r3 8000426: f200 80cd bhi.w 80005c4 <__udivmoddi4+0x2b4> 800042a: 4626 mov r6, r4 800042c: 1a1c subs r4, r3, r0 800042e: fa1f f38e uxth.w r3, lr 8000432: fbb4 f0f8 udiv r0, r4, r8 8000436: fb08 4410 mls r4, r8, r0, r4 800043a: ea43 4304 orr.w r3, r3, r4, lsl #16 800043e: fb00 f707 mul.w r7, r0, r7 8000442: 429f cmp r7, r3 8000444: d908 bls.n 8000458 <__udivmoddi4+0x148> 8000446: eb1c 0303 adds.w r3, ip, r3 800044a: f100 34ff add.w r4, r0, #4294967295 @ 0xffffffff 800044e: d202 bcs.n 8000456 <__udivmoddi4+0x146> 8000450: 429f cmp r7, r3 8000452: f200 80b0 bhi.w 80005b6 <__udivmoddi4+0x2a6> 8000456: 4620 mov r0, r4 8000458: 1bdb subs r3, r3, r7 800045a: ea40 4006 orr.w r0, r0, r6, lsl #16 800045e: e7a5 b.n 80003ac <__udivmoddi4+0x9c> 8000460: f1c1 0620 rsb r6, r1, #32 8000464: 408b lsls r3, r1 8000466: fa22 f706 lsr.w r7, r2, r6 800046a: 431f orrs r7, r3 800046c: fa20 fc06 lsr.w ip, r0, r6 8000470: fa04 f301 lsl.w r3, r4, r1 8000474: ea43 030c orr.w r3, r3, ip 8000478: 40f4 lsrs r4, r6 800047a: fa00 f801 lsl.w r8, r0, r1 800047e: 0c38 lsrs r0, r7, #16 8000480: ea4f 4913 mov.w r9, r3, lsr #16 8000484: fbb4 fef0 udiv lr, r4, r0 8000488: fa1f fc87 uxth.w ip, r7 800048c: fb00 441e mls r4, r0, lr, r4 8000490: ea49 4404 orr.w r4, r9, r4, lsl #16 8000494: fb0e f90c mul.w r9, lr, ip 8000498: 45a1 cmp r9, r4 800049a: fa02 f201 lsl.w r2, r2, r1 800049e: d90a bls.n 80004b6 <__udivmoddi4+0x1a6> 80004a0: 193c adds r4, r7, r4 80004a2: f10e 3aff add.w sl, lr, #4294967295 @ 0xffffffff 80004a6: f080 8084 bcs.w 80005b2 <__udivmoddi4+0x2a2> 80004aa: 45a1 cmp r9, r4 80004ac: f240 8081 bls.w 80005b2 <__udivmoddi4+0x2a2> 80004b0: f1ae 0e02 sub.w lr, lr, #2 80004b4: 443c add r4, r7 80004b6: eba4 0409 sub.w r4, r4, r9 80004ba: fa1f f983 uxth.w r9, r3 80004be: fbb4 f3f0 udiv r3, r4, r0 80004c2: fb00 4413 mls r4, r0, r3, r4 80004c6: ea49 4404 orr.w r4, r9, r4, lsl #16 80004ca: fb03 fc0c mul.w ip, r3, ip 80004ce: 45a4 cmp ip, r4 80004d0: d907 bls.n 80004e2 <__udivmoddi4+0x1d2> 80004d2: 193c adds r4, r7, r4 80004d4: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 80004d8: d267 bcs.n 80005aa <__udivmoddi4+0x29a> 80004da: 45a4 cmp ip, r4 80004dc: d965 bls.n 80005aa <__udivmoddi4+0x29a> 80004de: 3b02 subs r3, #2 80004e0: 443c add r4, r7 80004e2: ea43 400e orr.w r0, r3, lr, lsl #16 80004e6: fba0 9302 umull r9, r3, r0, r2 80004ea: eba4 040c sub.w r4, r4, ip 80004ee: 429c cmp r4, r3 80004f0: 46ce mov lr, r9 80004f2: 469c mov ip, r3 80004f4: d351 bcc.n 800059a <__udivmoddi4+0x28a> 80004f6: d04e beq.n 8000596 <__udivmoddi4+0x286> 80004f8: b155 cbz r5, 8000510 <__udivmoddi4+0x200> 80004fa: ebb8 030e subs.w r3, r8, lr 80004fe: eb64 040c sbc.w r4, r4, ip 8000502: fa04 f606 lsl.w r6, r4, r6 8000506: 40cb lsrs r3, r1 8000508: 431e orrs r6, r3 800050a: 40cc lsrs r4, r1 800050c: e9c5 6400 strd r6, r4, [r5] 8000510: 2100 movs r1, #0 8000512: e750 b.n 80003b6 <__udivmoddi4+0xa6> 8000514: f1c2 0320 rsb r3, r2, #32 8000518: fa20 f103 lsr.w r1, r0, r3 800051c: fa0c fc02 lsl.w ip, ip, r2 8000520: fa24 f303 lsr.w r3, r4, r3 8000524: 4094 lsls r4, r2 8000526: 430c orrs r4, r1 8000528: ea4f 481c mov.w r8, ip, lsr #16 800052c: fa00 fe02 lsl.w lr, r0, r2 8000530: fa1f f78c uxth.w r7, ip 8000534: fbb3 f0f8 udiv r0, r3, r8 8000538: fb08 3110 mls r1, r8, r0, r3 800053c: 0c23 lsrs r3, r4, #16 800053e: ea43 4301 orr.w r3, r3, r1, lsl #16 8000542: fb00 f107 mul.w r1, r0, r7 8000546: 4299 cmp r1, r3 8000548: d908 bls.n 800055c <__udivmoddi4+0x24c> 800054a: eb1c 0303 adds.w r3, ip, r3 800054e: f100 36ff add.w r6, r0, #4294967295 @ 0xffffffff 8000552: d22c bcs.n 80005ae <__udivmoddi4+0x29e> 8000554: 4299 cmp r1, r3 8000556: d92a bls.n 80005ae <__udivmoddi4+0x29e> 8000558: 3802 subs r0, #2 800055a: 4463 add r3, ip 800055c: 1a5b subs r3, r3, r1 800055e: b2a4 uxth r4, r4 8000560: fbb3 f1f8 udiv r1, r3, r8 8000564: fb08 3311 mls r3, r8, r1, r3 8000568: ea44 4403 orr.w r4, r4, r3, lsl #16 800056c: fb01 f307 mul.w r3, r1, r7 8000570: 42a3 cmp r3, r4 8000572: d908 bls.n 8000586 <__udivmoddi4+0x276> 8000574: eb1c 0404 adds.w r4, ip, r4 8000578: f101 36ff add.w r6, r1, #4294967295 @ 0xffffffff 800057c: d213 bcs.n 80005a6 <__udivmoddi4+0x296> 800057e: 42a3 cmp r3, r4 8000580: d911 bls.n 80005a6 <__udivmoddi4+0x296> 8000582: 3902 subs r1, #2 8000584: 4464 add r4, ip 8000586: 1ae4 subs r4, r4, r3 8000588: ea41 4100 orr.w r1, r1, r0, lsl #16 800058c: e739 b.n 8000402 <__udivmoddi4+0xf2> 800058e: 4604 mov r4, r0 8000590: e6f0 b.n 8000374 <__udivmoddi4+0x64> 8000592: 4608 mov r0, r1 8000594: e706 b.n 80003a4 <__udivmoddi4+0x94> 8000596: 45c8 cmp r8, r9 8000598: d2ae bcs.n 80004f8 <__udivmoddi4+0x1e8> 800059a: ebb9 0e02 subs.w lr, r9, r2 800059e: eb63 0c07 sbc.w ip, r3, r7 80005a2: 3801 subs r0, #1 80005a4: e7a8 b.n 80004f8 <__udivmoddi4+0x1e8> 80005a6: 4631 mov r1, r6 80005a8: e7ed b.n 8000586 <__udivmoddi4+0x276> 80005aa: 4603 mov r3, r0 80005ac: e799 b.n 80004e2 <__udivmoddi4+0x1d2> 80005ae: 4630 mov r0, r6 80005b0: e7d4 b.n 800055c <__udivmoddi4+0x24c> 80005b2: 46d6 mov lr, sl 80005b4: e77f b.n 80004b6 <__udivmoddi4+0x1a6> 80005b6: 4463 add r3, ip 80005b8: 3802 subs r0, #2 80005ba: e74d b.n 8000458 <__udivmoddi4+0x148> 80005bc: 4606 mov r6, r0 80005be: 4623 mov r3, r4 80005c0: 4608 mov r0, r1 80005c2: e70f b.n 80003e4 <__udivmoddi4+0xd4> 80005c4: 3e02 subs r6, #2 80005c6: 4463 add r3, ip 80005c8: e730 b.n 800042c <__udivmoddi4+0x11c> 80005ca: bf00 nop 080005cc <__aeabi_idiv0>: 80005cc: 4770 bx lr 80005ce: bf00 nop 080005d0 : /* Hook prototypes */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName); /* USER CODE BEGIN 4 */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName) { 80005d0: b480 push {r7} 80005d2: b083 sub sp, #12 80005d4: af00 add r7, sp, #0 80005d6: 6078 str r0, [r7, #4] 80005d8: 6039 str r1, [r7, #0] /* Run time stack overflow checking is performed if configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is called if a stack overflow is detected. */ } 80005da: bf00 nop 80005dc: 370c adds r7, #12 80005de: 46bd mov sp, r7 80005e0: f85d 7b04 ldr.w r7, [sp], #4 80005e4: 4770 bx lr ... 080005e8 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 80005e8: b480 push {r7} 80005ea: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 80005ec: f3bf 8f4f dsb sy } 80005f0: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 80005f2: 4b06 ldr r3, [pc, #24] @ (800060c <__NVIC_SystemReset+0x24>) 80005f4: 68db ldr r3, [r3, #12] 80005f6: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80005fa: 4904 ldr r1, [pc, #16] @ (800060c <__NVIC_SystemReset+0x24>) 80005fc: 4b04 ldr r3, [pc, #16] @ (8000610 <__NVIC_SystemReset+0x28>) 80005fe: 4313 orrs r3, r2 8000600: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 8000602: f3bf 8f4f dsb sy } 8000606: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 8000608: bf00 nop 800060a: e7fd b.n 8000608 <__NVIC_SystemReset+0x20> 800060c: e000ed00 .word 0xe000ed00 8000610: 05fa0004 .word 0x05fa0004 08000614 : #endif return ch; } void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 8000614: b580 push {r7, lr} 8000616: b084 sub sp, #16 8000618: af00 add r7, sp, #0 800061a: 4603 mov r3, r0 800061c: 80fb strh r3, [r7, #6] LimiterSwitchData limiterSwitchData = { 0 }; 800061e: 2300 movs r3, #0 8000620: 60fb str r3, [r7, #12] limiterSwitchData.gpioPin = GPIO_Pin; 8000622: 88fb ldrh r3, [r7, #6] 8000624: 81bb strh r3, [r7, #12] limiterSwitchData.pinState = HAL_GPIO_ReadPin(GPIOD, GPIO_Pin); 8000626: 88fb ldrh r3, [r7, #6] 8000628: 4619 mov r1, r3 800062a: 4808 ldr r0, [pc, #32] @ (800064c ) 800062c: f00a ffc2 bl 800b5b4 8000630: 4603 mov r3, r0 8000632: 73bb strb r3, [r7, #14] osMessageQueuePut(limiterSwitchDataQueue, &limiterSwitchData, 0, 0); 8000634: 4b06 ldr r3, [pc, #24] @ (8000650 ) 8000636: 6818 ldr r0, [r3, #0] 8000638: f107 010c add.w r1, r7, #12 800063c: 2300 movs r3, #0 800063e: 2200 movs r2, #0 8000640: f014 f878 bl 8014734 } 8000644: bf00 nop 8000646: 3710 adds r7, #16 8000648: 46bd mov sp, r7 800064a: bd80 pop {r7, pc} 800064c: 58020c00 .word 0x58020c00 8000650: 2400080c .word 0x2400080c 08000654
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000654: b580 push {r7, lr} 8000656: b084 sub sp, #16 8000658: af00 add r7, sp, #0 /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MPU Configuration--------------------------------------------------------*/ MPU_Config(); 800065a: f001 fbb1 bl 8001dc0 \details Turns on I-Cache */ __STATIC_FORCEINLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 800065e: 4b64 ldr r3, [pc, #400] @ (80007f0 ) 8000660: 695b ldr r3, [r3, #20] 8000662: f403 3300 and.w r3, r3, #131072 @ 0x20000 8000666: 2b00 cmp r3, #0 8000668: d11b bne.n 80006a2 __ASM volatile ("dsb 0xF":::"memory"); 800066a: f3bf 8f4f dsb sy } 800066e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000670: f3bf 8f6f isb sy } 8000674: bf00 nop __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 8000676: 4b5e ldr r3, [pc, #376] @ (80007f0 ) 8000678: 2200 movs r2, #0 800067a: f8c3 2250 str.w r2, [r3, #592] @ 0x250 __ASM volatile ("dsb 0xF":::"memory"); 800067e: f3bf 8f4f dsb sy } 8000682: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000684: f3bf 8f6f isb sy } 8000688: bf00 nop __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 800068a: 4b59 ldr r3, [pc, #356] @ (80007f0 ) 800068c: 695b ldr r3, [r3, #20] 800068e: 4a58 ldr r2, [pc, #352] @ (80007f0 ) 8000690: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8000694: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 8000696: f3bf 8f4f dsb sy } 800069a: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 800069c: f3bf 8f6f isb sy } 80006a0: e000 b.n 80006a4 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 80006a2: bf00 nop #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 80006a4: 4b52 ldr r3, [pc, #328] @ (80007f0 ) 80006a6: 695b ldr r3, [r3, #20] 80006a8: f403 3380 and.w r3, r3, #65536 @ 0x10000 80006ac: 2b00 cmp r3, #0 80006ae: d138 bne.n 8000722 SCB->CSSELR = 0U; /* select Level 1 data cache */ 80006b0: 4b4f ldr r3, [pc, #316] @ (80007f0 ) 80006b2: 2200 movs r2, #0 80006b4: f8c3 2084 str.w r2, [r3, #132] @ 0x84 __ASM volatile ("dsb 0xF":::"memory"); 80006b8: f3bf 8f4f dsb sy } 80006bc: bf00 nop __DSB(); ccsidr = SCB->CCSIDR; 80006be: 4b4c ldr r3, [pc, #304] @ (80007f0 ) 80006c0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80006c4: 60fb str r3, [r7, #12] /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 80006c6: 68fb ldr r3, [r7, #12] 80006c8: 0b5b lsrs r3, r3, #13 80006ca: f3c3 030e ubfx r3, r3, #0, #15 80006ce: 60bb str r3, [r7, #8] do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 80006d0: 68fb ldr r3, [r7, #12] 80006d2: 08db lsrs r3, r3, #3 80006d4: f3c3 0309 ubfx r3, r3, #0, #10 80006d8: 607b str r3, [r7, #4] do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 80006da: 68bb ldr r3, [r7, #8] 80006dc: 015a lsls r2, r3, #5 80006de: f643 73e0 movw r3, #16352 @ 0x3fe0 80006e2: 4013 ands r3, r2 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 80006e4: 687a ldr r2, [r7, #4] 80006e6: 0792 lsls r2, r2, #30 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 80006e8: 4941 ldr r1, [pc, #260] @ (80007f0 ) 80006ea: 4313 orrs r3, r2 80006ec: f8c1 3260 str.w r3, [r1, #608] @ 0x260 #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); 80006f0: 687b ldr r3, [r7, #4] 80006f2: 1e5a subs r2, r3, #1 80006f4: 607a str r2, [r7, #4] 80006f6: 2b00 cmp r3, #0 80006f8: d1ef bne.n 80006da } while(sets-- != 0U); 80006fa: 68bb ldr r3, [r7, #8] 80006fc: 1e5a subs r2, r3, #1 80006fe: 60ba str r2, [r7, #8] 8000700: 2b00 cmp r3, #0 8000702: d1e5 bne.n 80006d0 __ASM volatile ("dsb 0xF":::"memory"); 8000704: f3bf 8f4f dsb sy } 8000708: bf00 nop __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 800070a: 4b39 ldr r3, [pc, #228] @ (80007f0 ) 800070c: 695b ldr r3, [r3, #20] 800070e: 4a38 ldr r2, [pc, #224] @ (80007f0 ) 8000710: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8000714: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 8000716: f3bf 8f4f dsb sy } 800071a: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 800071c: f3bf 8f6f isb sy } 8000720: e000 b.n 8000724 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 8000722: bf00 nop SCB_EnableDCache(); /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000724: f005 fb6e bl 8005e04 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000728: f000 f884 bl 8000834 /* Configure the peripherals common clocks */ PeriphCommonClock_Config(); 800072c: f000 f900 bl 8000930 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000730: f000 ff88 bl 8001644 MX_DMA_Init(); 8000734: f000 ff56 bl 80015e4 MX_RNG_Init(); 8000738: f000 fc08 bl 8000f4c MX_USART1_UART_Init(); 800073c: f000 ff02 bl 8001544 MX_ADC1_Init(); 8000740: f000 f926 bl 8000990 MX_UART8_Init(); 8000744: f000 feb2 bl 80014ac MX_CRC_Init(); 8000748: f000 fb7e bl 8000e48 MX_ADC2_Init(); 800074c: f000 fa0a bl 8000b64 MX_ADC3_Init(); 8000750: f000 fa9c bl 8000c8c MX_TIM2_Init(); 8000754: f000 fcac bl 80010b0 MX_TIM1_Init(); 8000758: f000 fc0e bl 8000f78 MX_TIM3_Init(); 800075c: f000 fd26 bl 80011ac MX_DAC1_Init(); 8000760: f000 fb9c bl 8000e9c MX_COMP1_Init(); 8000764: f000 fb42 bl 8000dec MX_TIM4_Init(); 8000768: f000 fdcc bl 8001304 MX_TIM8_Init(); 800076c: f000 fe48 bl 8001400 #ifdef WATCHDOG_ENABLED MX_IWDG1_Init(); 8000770: f000 fbd0 bl 8000f14 #endif /* USER CODE BEGIN 2 */ #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8000774: 481f ldr r0, [pc, #124] @ (80007f4 ) 8000776: f00a ffd1 bl 800b71c #endif /* USER CODE END 2 */ /* Init scheduler */ osKernelInitialize(); 800077a: f013 fc6b bl 8014054 /* add semaphores, ... */ /* USER CODE END RTOS_SEMAPHORES */ /* Create the timer(s) */ /* creation of debugLedTimer */ debugLedTimerHandle = osTimerNew(debugLedTimerCallback, osTimerOnce, NULL, &debugLedTimer_attributes); 800077e: 4b1e ldr r3, [pc, #120] @ (80007f8 ) 8000780: 2200 movs r2, #0 8000782: 2100 movs r1, #0 8000784: 481d ldr r0, [pc, #116] @ (80007fc ) 8000786: f013 fd73 bl 8014270 800078a: 4603 mov r3, r0 800078c: 4a1c ldr r2, [pc, #112] @ (8000800 ) 800078e: 6013 str r3, [r2, #0] /* creation of fanTimer */ fanTimerHandle = osTimerNew(fanTimerCallback, osTimerOnce, NULL, &fanTimer_attributes); 8000790: 4b1c ldr r3, [pc, #112] @ (8000804 ) 8000792: 2200 movs r2, #0 8000794: 2100 movs r1, #0 8000796: 481c ldr r0, [pc, #112] @ (8000808 ) 8000798: f013 fd6a bl 8014270 800079c: 4603 mov r3, r0 800079e: 4a1b ldr r2, [pc, #108] @ (800080c ) 80007a0: 6013 str r3, [r2, #0] /* creation of motorXTimer */ motorXTimerHandle = osTimerNew(motorXTimerCallback, osTimerPeriodic, NULL, &motorXTimer_attributes); 80007a2: 4b1b ldr r3, [pc, #108] @ (8000810 ) 80007a4: 2200 movs r2, #0 80007a6: 2101 movs r1, #1 80007a8: 481a ldr r0, [pc, #104] @ (8000814 ) 80007aa: f013 fd61 bl 8014270 80007ae: 4603 mov r3, r0 80007b0: 4a19 ldr r2, [pc, #100] @ (8000818 ) 80007b2: 6013 str r3, [r2, #0] /* creation of motorYTimer */ motorYTimerHandle = osTimerNew(motorYTimerCallback, osTimerPeriodic, NULL, &motorYTimer_attributes); 80007b4: 4b19 ldr r3, [pc, #100] @ (800081c ) 80007b6: 2200 movs r2, #0 80007b8: 2101 movs r1, #1 80007ba: 4819 ldr r0, [pc, #100] @ (8000820 ) 80007bc: f013 fd58 bl 8014270 80007c0: 4603 mov r3, r0 80007c2: 4a18 ldr r2, [pc, #96] @ (8000824 ) 80007c4: 6013 str r3, [r2, #0] /* add queues, ... */ /* USER CODE END RTOS_QUEUES */ /* Create the thread(s) */ /* creation of defaultTask */ defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); 80007c6: 4a18 ldr r2, [pc, #96] @ (8000828 ) 80007c8: 2100 movs r1, #0 80007ca: 4818 ldr r0, [pc, #96] @ (800082c ) 80007cc: f013 fc8c bl 80140e8 80007d0: 4603 mov r3, r0 80007d2: 4a17 ldr r2, [pc, #92] @ (8000830 ) 80007d4: 6013 str r3, [r2, #0] /* USER CODE BEGIN RTOS_THREADS */ /* add threads, ... */ #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 80007d6: 4807 ldr r0, [pc, #28] @ (80007f4 ) 80007d8: f00a ffa0 bl 800b71c #endif UartTasksInit(); 80007dc: f004 f938 bl 8004a50 #ifdef USER_MOCKS MockMeasurmetsTaskInit(); #else MeasTasksInit(); 80007e0: f001 fb7a bl 8001ed8 #endif PositionControlTaskInit(); 80007e4: f002 fdf2 bl 80033cc /* USER CODE BEGIN RTOS_EVENTS */ /* add events, ... */ /* USER CODE END RTOS_EVENTS */ /* Start scheduler */ osKernelStart(); 80007e8: f013 fc58 bl 801409c /* We should never get here as control is now taken by the scheduler */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 80007ec: bf00 nop 80007ee: e7fd b.n 80007ec 80007f0: e000ed00 .word 0xe000ed00 80007f4: 24000418 .word 0x24000418 80007f8: 0801874c .word 0x0801874c 80007fc: 08001d15 .word 0x08001d15 8000800: 240006e4 .word 0x240006e4 8000804: 0801875c .word 0x0801875c 8000808: 08001d2d .word 0x08001d2d 800080c: 24000714 .word 0x24000714 8000810: 0801876c .word 0x0801876c 8000814: 08001d49 .word 0x08001d49 8000818: 24000744 .word 0x24000744 800081c: 0801877c .word 0x0801877c 8000820: 08001d85 .word 0x08001d85 8000824: 24000774 .word 0x24000774 8000828: 08018728 .word 0x08018728 800082c: 08001b59 .word 0x08001b59 8000830: 240006e0 .word 0x240006e0 08000834 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000834: b580 push {r7, lr} 8000836: b09c sub sp, #112 @ 0x70 8000838: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800083a: f107 0324 add.w r3, r7, #36 @ 0x24 800083e: 224c movs r2, #76 @ 0x4c 8000840: 2100 movs r1, #0 8000842: 4618 mov r0, r3 8000844: f017 fda8 bl 8018398 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000848: 1d3b adds r3, r7, #4 800084a: 2220 movs r2, #32 800084c: 2100 movs r1, #0 800084e: 4618 mov r0, r3 8000850: f017 fda2 bl 8018398 /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 8000854: 2002 movs r0, #2 8000856: f00a fffb bl 800b850 /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 800085a: 2300 movs r3, #0 800085c: 603b str r3, [r7, #0] 800085e: 4b32 ldr r3, [pc, #200] @ (8000928 ) 8000860: 6adb ldr r3, [r3, #44] @ 0x2c 8000862: 4a31 ldr r2, [pc, #196] @ (8000928 ) 8000864: f023 0301 bic.w r3, r3, #1 8000868: 62d3 str r3, [r2, #44] @ 0x2c 800086a: 4b2f ldr r3, [pc, #188] @ (8000928 ) 800086c: 6adb ldr r3, [r3, #44] @ 0x2c 800086e: f003 0301 and.w r3, r3, #1 8000872: 603b str r3, [r7, #0] 8000874: 4b2d ldr r3, [pc, #180] @ (800092c ) 8000876: 699b ldr r3, [r3, #24] 8000878: 4a2c ldr r2, [pc, #176] @ (800092c ) 800087a: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800087e: 6193 str r3, [r2, #24] 8000880: 4b2a ldr r3, [pc, #168] @ (800092c ) 8000882: 699b ldr r3, [r3, #24] 8000884: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000888: 603b str r3, [r7, #0] 800088a: 683b ldr r3, [r7, #0] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 800088c: bf00 nop 800088e: 4b27 ldr r3, [pc, #156] @ (800092c ) 8000890: 699b ldr r3, [r3, #24] 8000892: f403 5300 and.w r3, r3, #8192 @ 0x2000 8000896: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800089a: d1f8 bne.n 800088e /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_LSI 800089c: 2329 movs r3, #41 @ 0x29 800089e: 627b str r3, [r7, #36] @ 0x24 |RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; 80008a0: f44f 3380 mov.w r3, #65536 @ 0x10000 80008a4: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.LSIState = RCC_LSI_ON; 80008a6: 2301 movs r3, #1 80008a8: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; 80008aa: 2301 movs r3, #1 80008ac: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80008ae: 2302 movs r3, #2 80008b0: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 80008b2: 2302 movs r3, #2 80008b4: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.PLL.PLLM = 5; 80008b6: 2305 movs r3, #5 80008b8: 653b str r3, [r7, #80] @ 0x50 RCC_OscInitStruct.PLL.PLLN = 160; 80008ba: 23a0 movs r3, #160 @ 0xa0 80008bc: 657b str r3, [r7, #84] @ 0x54 RCC_OscInitStruct.PLL.PLLP = 2; 80008be: 2302 movs r3, #2 80008c0: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLQ = 2; 80008c2: 2302 movs r3, #2 80008c4: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLR = 2; 80008c6: 2302 movs r3, #2 80008c8: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 80008ca: 2308 movs r3, #8 80008cc: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 80008ce: 2300 movs r3, #0 80008d0: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL.PLLFRACN = 0; 80008d2: 2300 movs r3, #0 80008d4: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80008d6: f107 0324 add.w r3, r7, #36 @ 0x24 80008da: 4618 mov r0, r3 80008dc: f00b f878 bl 800b9d0 80008e0: 4603 mov r3, r0 80008e2: 2b00 cmp r3, #0 80008e4: d001 beq.n 80008ea { Error_Handler(); 80008e6: f001 faf1 bl 8001ecc } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80008ea: 233f movs r3, #63 @ 0x3f 80008ec: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80008ee: 2303 movs r3, #3 80008f0: 60bb str r3, [r7, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 80008f2: 2300 movs r3, #0 80008f4: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 80008f6: 2308 movs r3, #8 80008f8: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 80008fa: 2340 movs r3, #64 @ 0x40 80008fc: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 80008fe: 2340 movs r3, #64 @ 0x40 8000900: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 8000902: f44f 6380 mov.w r3, #1024 @ 0x400 8000906: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 8000908: 2340 movs r3, #64 @ 0x40 800090a: 623b str r3, [r7, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800090c: 1d3b adds r3, r7, #4 800090e: 2102 movs r1, #2 8000910: 4618 mov r0, r3 8000912: f00b fcb7 bl 800c284 8000916: 4603 mov r3, r0 8000918: 2b00 cmp r3, #0 800091a: d001 beq.n 8000920 { Error_Handler(); 800091c: f001 fad6 bl 8001ecc } } 8000920: bf00 nop 8000922: 3770 adds r7, #112 @ 0x70 8000924: 46bd mov sp, r7 8000926: bd80 pop {r7, pc} 8000928: 58000400 .word 0x58000400 800092c: 58024800 .word 0x58024800 08000930 : /** * @brief Peripherals Common Clock Configuration * @retval None */ void PeriphCommonClock_Config(void) { 8000930: b580 push {r7, lr} 8000932: b0b0 sub sp, #192 @ 0xc0 8000934: af00 add r7, sp, #0 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8000936: 463b mov r3, r7 8000938: 22c0 movs r2, #192 @ 0xc0 800093a: 2100 movs r1, #0 800093c: 4618 mov r0, r3 800093e: f017 fd2b bl 8018398 /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC; 8000942: f44f 2200 mov.w r2, #524288 @ 0x80000 8000946: f04f 0300 mov.w r3, #0 800094a: e9c7 2300 strd r2, r3, [r7] PeriphClkInitStruct.PLL2.PLL2M = 5; 800094e: 2305 movs r3, #5 8000950: 60bb str r3, [r7, #8] PeriphClkInitStruct.PLL2.PLL2N = 52; 8000952: 2334 movs r3, #52 @ 0x34 8000954: 60fb str r3, [r7, #12] PeriphClkInitStruct.PLL2.PLL2P = 26; 8000956: 231a movs r3, #26 8000958: 613b str r3, [r7, #16] PeriphClkInitStruct.PLL2.PLL2Q = 2; 800095a: 2302 movs r3, #2 800095c: 617b str r3, [r7, #20] PeriphClkInitStruct.PLL2.PLL2R = 2; 800095e: 2302 movs r3, #2 8000960: 61bb str r3, [r7, #24] PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2; 8000962: 2380 movs r3, #128 @ 0x80 8000964: 61fb str r3, [r7, #28] PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; 8000966: 2300 movs r3, #0 8000968: 623b str r3, [r7, #32] PeriphClkInitStruct.PLL2.PLL2FRACN = 0; 800096a: 2300 movs r3, #0 800096c: 627b str r3, [r7, #36] @ 0x24 PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; 800096e: 2300 movs r3, #0 8000970: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8000974: 463b mov r3, r7 8000976: 4618 mov r0, r3 8000978: f00c f852 bl 800ca20 800097c: 4603 mov r3, r0 800097e: 2b00 cmp r3, #0 8000980: d001 beq.n 8000986 { Error_Handler(); 8000982: f001 faa3 bl 8001ecc } } 8000986: bf00 nop 8000988: 37c0 adds r7, #192 @ 0xc0 800098a: 46bd mov sp, r7 800098c: bd80 pop {r7, pc} ... 08000990 : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 8000990: b580 push {r7, lr} 8000992: b08a sub sp, #40 @ 0x28 8000994: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_MultiModeTypeDef multimode = {0}; 8000996: f107 031c add.w r3, r7, #28 800099a: 2200 movs r2, #0 800099c: 601a str r2, [r3, #0] 800099e: 605a str r2, [r3, #4] 80009a0: 609a str r2, [r3, #8] ADC_ChannelConfTypeDef sConfig = {0}; 80009a2: 463b mov r3, r7 80009a4: 2200 movs r2, #0 80009a6: 601a str r2, [r3, #0] 80009a8: 605a str r2, [r3, #4] 80009aa: 609a str r2, [r3, #8] 80009ac: 60da str r2, [r3, #12] 80009ae: 611a str r2, [r3, #16] 80009b0: 615a str r2, [r3, #20] 80009b2: 619a str r2, [r3, #24] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 80009b4: 4b62 ldr r3, [pc, #392] @ (8000b40 ) 80009b6: 4a63 ldr r2, [pc, #396] @ (8000b44 ) 80009b8: 601a str r2, [r3, #0] hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 80009ba: 4b61 ldr r3, [pc, #388] @ (8000b40 ) 80009bc: 2200 movs r2, #0 80009be: 605a str r2, [r3, #4] hadc1.Init.Resolution = ADC_RESOLUTION_16B; 80009c0: 4b5f ldr r3, [pc, #380] @ (8000b40 ) 80009c2: 2200 movs r2, #0 80009c4: 609a str r2, [r3, #8] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 80009c6: 4b5e ldr r3, [pc, #376] @ (8000b40 ) 80009c8: 2201 movs r2, #1 80009ca: 60da str r2, [r3, #12] hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; 80009cc: 4b5c ldr r3, [pc, #368] @ (8000b40 ) 80009ce: 2208 movs r2, #8 80009d0: 611a str r2, [r3, #16] hadc1.Init.LowPowerAutoWait = DISABLE; 80009d2: 4b5b ldr r3, [pc, #364] @ (8000b40 ) 80009d4: 2200 movs r2, #0 80009d6: 751a strb r2, [r3, #20] hadc1.Init.ContinuousConvMode = ENABLE; 80009d8: 4b59 ldr r3, [pc, #356] @ (8000b40 ) 80009da: 2201 movs r2, #1 80009dc: 755a strb r2, [r3, #21] hadc1.Init.NbrOfConversion = 7; 80009de: 4b58 ldr r3, [pc, #352] @ (8000b40 ) 80009e0: 2207 movs r2, #7 80009e2: 619a str r2, [r3, #24] hadc1.Init.DiscontinuousConvMode = DISABLE; 80009e4: 4b56 ldr r3, [pc, #344] @ (8000b40 ) 80009e6: 2200 movs r2, #0 80009e8: 771a strb r2, [r3, #28] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T8_TRGO; 80009ea: 4b55 ldr r3, [pc, #340] @ (8000b40 ) 80009ec: f44f 629c mov.w r2, #1248 @ 0x4e0 80009f0: 625a str r2, [r3, #36] @ 0x24 hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 80009f2: 4b53 ldr r3, [pc, #332] @ (8000b40 ) 80009f4: f44f 6280 mov.w r2, #1024 @ 0x400 80009f8: 629a str r2, [r3, #40] @ 0x28 hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 80009fa: 4b51 ldr r3, [pc, #324] @ (8000b40 ) 80009fc: 2201 movs r2, #1 80009fe: 62da str r2, [r3, #44] @ 0x2c hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000a00: 4b4f ldr r3, [pc, #316] @ (8000b40 ) 8000a02: 2200 movs r2, #0 8000a04: 631a str r2, [r3, #48] @ 0x30 hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000a06: 4b4e ldr r3, [pc, #312] @ (8000b40 ) 8000a08: 2200 movs r2, #0 8000a0a: 635a str r2, [r3, #52] @ 0x34 hadc1.Init.OversamplingMode = DISABLE; 8000a0c: 4b4c ldr r3, [pc, #304] @ (8000b40 ) 8000a0e: 2200 movs r2, #0 8000a10: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc1) != HAL_OK) 8000a14: 484a ldr r0, [pc, #296] @ (8000b40 ) 8000a16: f005 fca5 bl 8006364 8000a1a: 4603 mov r3, r0 8000a1c: 2b00 cmp r3, #0 8000a1e: d001 beq.n 8000a24 { Error_Handler(); 8000a20: f001 fa54 bl 8001ecc } /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; 8000a24: 2300 movs r3, #0 8000a26: 61fb str r3, [r7, #28] if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 8000a28: f107 031c add.w r3, r7, #28 8000a2c: 4619 mov r1, r3 8000a2e: 4844 ldr r0, [pc, #272] @ (8000b40 ) 8000a30: f006 fdb6 bl 80075a0 8000a34: 4603 mov r3, r0 8000a36: 2b00 cmp r3, #0 8000a38: d001 beq.n 8000a3e { Error_Handler(); 8000a3a: f001 fa47 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8000a3e: 4b42 ldr r3, [pc, #264] @ (8000b48 ) 8000a40: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_1; 8000a42: 2306 movs r3, #6 8000a44: 607b str r3, [r7, #4] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000a46: 2306 movs r3, #6 8000a48: 60bb str r3, [r7, #8] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000a4a: f240 73ff movw r3, #2047 @ 0x7ff 8000a4e: 60fb str r3, [r7, #12] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000a50: 2304 movs r3, #4 8000a52: 613b str r3, [r7, #16] sConfig.Offset = 0; 8000a54: 2300 movs r3, #0 8000a56: 617b str r3, [r7, #20] sConfig.OffsetSignedSaturation = DISABLE; 8000a58: 2300 movs r3, #0 8000a5a: 767b strb r3, [r7, #25] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000a5c: 463b mov r3, r7 8000a5e: 4619 mov r1, r3 8000a60: 4837 ldr r0, [pc, #220] @ (8000b40 ) 8000a62: f005 fef9 bl 8006858 8000a66: 4603 mov r3, r0 8000a68: 2b00 cmp r3, #0 8000a6a: d001 beq.n 8000a70 { Error_Handler(); 8000a6c: f001 fa2e bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_7; 8000a70: 4b36 ldr r3, [pc, #216] @ (8000b4c ) 8000a72: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_2; 8000a74: 230c movs r3, #12 8000a76: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000a78: 463b mov r3, r7 8000a7a: 4619 mov r1, r3 8000a7c: 4830 ldr r0, [pc, #192] @ (8000b40 ) 8000a7e: f005 feeb bl 8006858 8000a82: 4603 mov r3, r0 8000a84: 2b00 cmp r3, #0 8000a86: d001 beq.n 8000a8c { Error_Handler(); 8000a88: f001 fa20 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_9; 8000a8c: 4b30 ldr r3, [pc, #192] @ (8000b50 ) 8000a8e: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_3; 8000a90: 2312 movs r3, #18 8000a92: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000a94: 463b mov r3, r7 8000a96: 4619 mov r1, r3 8000a98: 4829 ldr r0, [pc, #164] @ (8000b40 ) 8000a9a: f005 fedd bl 8006858 8000a9e: 4603 mov r3, r0 8000aa0: 2b00 cmp r3, #0 8000aa2: d001 beq.n 8000aa8 { Error_Handler(); 8000aa4: f001 fa12 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_16; 8000aa8: 4b2a ldr r3, [pc, #168] @ (8000b54 ) 8000aaa: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_4; 8000aac: 2318 movs r3, #24 8000aae: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000ab0: 463b mov r3, r7 8000ab2: 4619 mov r1, r3 8000ab4: 4822 ldr r0, [pc, #136] @ (8000b40 ) 8000ab6: f005 fecf bl 8006858 8000aba: 4603 mov r3, r0 8000abc: 2b00 cmp r3, #0 8000abe: d001 beq.n 8000ac4 { Error_Handler(); 8000ac0: f001 fa04 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_17; 8000ac4: 4b24 ldr r3, [pc, #144] @ (8000b58 ) 8000ac6: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_5; 8000ac8: f44f 7380 mov.w r3, #256 @ 0x100 8000acc: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000ace: 463b mov r3, r7 8000ad0: 4619 mov r1, r3 8000ad2: 481b ldr r0, [pc, #108] @ (8000b40 ) 8000ad4: f005 fec0 bl 8006858 8000ad8: 4603 mov r3, r0 8000ada: 2b00 cmp r3, #0 8000adc: d001 beq.n 8000ae2 { Error_Handler(); 8000ade: f001 f9f5 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_14; 8000ae2: 4b1e ldr r3, [pc, #120] @ (8000b5c ) 8000ae4: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_6; 8000ae6: f44f 7383 mov.w r3, #262 @ 0x106 8000aea: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000aec: 463b mov r3, r7 8000aee: 4619 mov r1, r3 8000af0: 4813 ldr r0, [pc, #76] @ (8000b40 ) 8000af2: f005 feb1 bl 8006858 8000af6: 4603 mov r3, r0 8000af8: 2b00 cmp r3, #0 8000afa: d001 beq.n 8000b00 { Error_Handler(); 8000afc: f001 f9e6 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_15; 8000b00: 4b17 ldr r3, [pc, #92] @ (8000b60 ) 8000b02: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_7; 8000b04: f44f 7386 mov.w r3, #268 @ 0x10c 8000b08: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000b0a: 463b mov r3, r7 8000b0c: 4619 mov r1, r3 8000b0e: 480c ldr r0, [pc, #48] @ (8000b40 ) 8000b10: f005 fea2 bl 8006858 8000b14: 4603 mov r3, r0 8000b16: 2b00 cmp r3, #0 8000b18: d001 beq.n 8000b1e { Error_Handler(); 8000b1a: f001 f9d7 bl 8001ecc } /* USER CODE BEGIN ADC1_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000b1e: f240 72ff movw r2, #2047 @ 0x7ff 8000b22: f04f 1101 mov.w r1, #65537 @ 0x10001 8000b26: 4806 ldr r0, [pc, #24] @ (8000b40 ) 8000b28: f006 fcd6 bl 80074d8 8000b2c: 4603 mov r3, r0 8000b2e: 2b00 cmp r3, #0 8000b30: d001 beq.n 8000b36 { Error_Handler(); 8000b32: f001 f9cb bl 8001ecc } /* USER CODE END ADC1_Init 2 */ } 8000b36: bf00 nop 8000b38: 3728 adds r7, #40 @ 0x28 8000b3a: 46bd mov sp, r7 8000b3c: bd80 pop {r7, pc} 8000b3e: bf00 nop 8000b40: 24000120 .word 0x24000120 8000b44: 40022000 .word 0x40022000 8000b48: 21800100 .word 0x21800100 8000b4c: 1d500080 .word 0x1d500080 8000b50: 25b00200 .word 0x25b00200 8000b54: 43210000 .word 0x43210000 8000b58: 47520000 .word 0x47520000 8000b5c: 3ac04000 .word 0x3ac04000 8000b60: 3ef08000 .word 0x3ef08000 08000b64 : * @brief ADC2 Initialization Function * @param None * @retval None */ static void MX_ADC2_Init(void) { 8000b64: b580 push {r7, lr} 8000b66: b088 sub sp, #32 8000b68: af00 add r7, sp, #0 /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000b6a: 1d3b adds r3, r7, #4 8000b6c: 2200 movs r2, #0 8000b6e: 601a str r2, [r3, #0] 8000b70: 605a str r2, [r3, #4] 8000b72: 609a str r2, [r3, #8] 8000b74: 60da str r2, [r3, #12] 8000b76: 611a str r2, [r3, #16] 8000b78: 615a str r2, [r3, #20] 8000b7a: 619a str r2, [r3, #24] /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; 8000b7c: 4b3e ldr r3, [pc, #248] @ (8000c78 ) 8000b7e: 4a3f ldr r2, [pc, #252] @ (8000c7c ) 8000b80: 601a str r2, [r3, #0] hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 8000b82: 4b3d ldr r3, [pc, #244] @ (8000c78 ) 8000b84: 2200 movs r2, #0 8000b86: 605a str r2, [r3, #4] hadc2.Init.Resolution = ADC_RESOLUTION_16B; 8000b88: 4b3b ldr r3, [pc, #236] @ (8000c78 ) 8000b8a: 2200 movs r2, #0 8000b8c: 609a str r2, [r3, #8] hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000b8e: 4b3a ldr r3, [pc, #232] @ (8000c78 ) 8000b90: 2201 movs r2, #1 8000b92: 60da str r2, [r3, #12] hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000b94: 4b38 ldr r3, [pc, #224] @ (8000c78 ) 8000b96: 2208 movs r2, #8 8000b98: 611a str r2, [r3, #16] hadc2.Init.LowPowerAutoWait = DISABLE; 8000b9a: 4b37 ldr r3, [pc, #220] @ (8000c78 ) 8000b9c: 2200 movs r2, #0 8000b9e: 751a strb r2, [r3, #20] hadc2.Init.ContinuousConvMode = ENABLE; 8000ba0: 4b35 ldr r3, [pc, #212] @ (8000c78 ) 8000ba2: 2201 movs r2, #1 8000ba4: 755a strb r2, [r3, #21] hadc2.Init.NbrOfConversion = 3; 8000ba6: 4b34 ldr r3, [pc, #208] @ (8000c78 ) 8000ba8: 2203 movs r2, #3 8000baa: 619a str r2, [r3, #24] hadc2.Init.DiscontinuousConvMode = DISABLE; 8000bac: 4b32 ldr r3, [pc, #200] @ (8000c78 ) 8000bae: 2200 movs r2, #0 8000bb0: 771a strb r2, [r3, #28] hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T8_TRGO; 8000bb2: 4b31 ldr r3, [pc, #196] @ (8000c78 ) 8000bb4: f44f 629c mov.w r2, #1248 @ 0x4e0 8000bb8: 625a str r2, [r3, #36] @ 0x24 hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000bba: 4b2f ldr r3, [pc, #188] @ (8000c78 ) 8000bbc: f44f 6280 mov.w r2, #1024 @ 0x400 8000bc0: 629a str r2, [r3, #40] @ 0x28 hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000bc2: 4b2d ldr r3, [pc, #180] @ (8000c78 ) 8000bc4: 2201 movs r2, #1 8000bc6: 62da str r2, [r3, #44] @ 0x2c hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000bc8: 4b2b ldr r3, [pc, #172] @ (8000c78 ) 8000bca: 2200 movs r2, #0 8000bcc: 631a str r2, [r3, #48] @ 0x30 hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000bce: 4b2a ldr r3, [pc, #168] @ (8000c78 ) 8000bd0: 2200 movs r2, #0 8000bd2: 635a str r2, [r3, #52] @ 0x34 hadc2.Init.OversamplingMode = DISABLE; 8000bd4: 4b28 ldr r3, [pc, #160] @ (8000c78 ) 8000bd6: 2200 movs r2, #0 8000bd8: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc2) != HAL_OK) 8000bdc: 4826 ldr r0, [pc, #152] @ (8000c78 ) 8000bde: f005 fbc1 bl 8006364 8000be2: 4603 mov r3, r0 8000be4: 2b00 cmp r3, #0 8000be6: d001 beq.n 8000bec { Error_Handler(); 8000be8: f001 f970 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 8000bec: 4b24 ldr r3, [pc, #144] @ (8000c80 ) 8000bee: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8000bf0: 2306 movs r3, #6 8000bf2: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000bf4: 2306 movs r3, #6 8000bf6: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000bf8: f240 73ff movw r3, #2047 @ 0x7ff 8000bfc: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000bfe: 2304 movs r3, #4 8000c00: 617b str r3, [r7, #20] sConfig.Offset = 0; 8000c02: 2300 movs r3, #0 8000c04: 61bb str r3, [r7, #24] sConfig.OffsetSignedSaturation = DISABLE; 8000c06: 2300 movs r3, #0 8000c08: 777b strb r3, [r7, #29] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000c0a: 1d3b adds r3, r7, #4 8000c0c: 4619 mov r1, r3 8000c0e: 481a ldr r0, [pc, #104] @ (8000c78 ) 8000c10: f005 fe22 bl 8006858 8000c14: 4603 mov r3, r0 8000c16: 2b00 cmp r3, #0 8000c18: d001 beq.n 8000c1e { Error_Handler(); 8000c1a: f001 f957 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8000c1e: 4b19 ldr r3, [pc, #100] @ (8000c84 ) 8000c20: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 8000c22: 230c movs r3, #12 8000c24: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000c26: 1d3b adds r3, r7, #4 8000c28: 4619 mov r1, r3 8000c2a: 4813 ldr r0, [pc, #76] @ (8000c78 ) 8000c2c: f005 fe14 bl 8006858 8000c30: 4603 mov r3, r0 8000c32: 2b00 cmp r3, #0 8000c34: d001 beq.n 8000c3a { Error_Handler(); 8000c36: f001 f949 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_5; 8000c3a: 4b13 ldr r3, [pc, #76] @ (8000c88 ) 8000c3c: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8000c3e: 2312 movs r3, #18 8000c40: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000c42: 1d3b adds r3, r7, #4 8000c44: 4619 mov r1, r3 8000c46: 480c ldr r0, [pc, #48] @ (8000c78 ) 8000c48: f005 fe06 bl 8006858 8000c4c: 4603 mov r3, r0 8000c4e: 2b00 cmp r3, #0 8000c50: d001 beq.n 8000c56 { Error_Handler(); 8000c52: f001 f93b bl 8001ecc } /* USER CODE BEGIN ADC2_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc2, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000c56: f240 72ff movw r2, #2047 @ 0x7ff 8000c5a: f04f 1101 mov.w r1, #65537 @ 0x10001 8000c5e: 4806 ldr r0, [pc, #24] @ (8000c78 ) 8000c60: f006 fc3a bl 80074d8 8000c64: 4603 mov r3, r0 8000c66: 2b00 cmp r3, #0 8000c68: d001 beq.n 8000c6e { Error_Handler(); 8000c6a: f001 f92f bl 8001ecc } /* USER CODE END ADC2_Init 2 */ } 8000c6e: bf00 nop 8000c70: 3720 adds r7, #32 8000c72: 46bd mov sp, r7 8000c74: bd80 pop {r7, pc} 8000c76: bf00 nop 8000c78: 24000184 .word 0x24000184 8000c7c: 40022100 .word 0x40022100 8000c80: 0c900008 .word 0x0c900008 8000c84: 10c00010 .word 0x10c00010 8000c88: 14f00020 .word 0x14f00020 08000c8c : * @brief ADC3 Initialization Function * @param None * @retval None */ static void MX_ADC3_Init(void) { 8000c8c: b580 push {r7, lr} 8000c8e: b088 sub sp, #32 8000c90: af00 add r7, sp, #0 /* USER CODE BEGIN ADC3_Init 0 */ /* USER CODE END ADC3_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000c92: 1d3b adds r3, r7, #4 8000c94: 2200 movs r2, #0 8000c96: 601a str r2, [r3, #0] 8000c98: 605a str r2, [r3, #4] 8000c9a: 609a str r2, [r3, #8] 8000c9c: 60da str r2, [r3, #12] 8000c9e: 611a str r2, [r3, #16] 8000ca0: 615a str r2, [r3, #20] 8000ca2: 619a str r2, [r3, #24] /* USER CODE END ADC3_Init 1 */ /** Common config */ hadc3.Instance = ADC3; 8000ca4: 4b4b ldr r3, [pc, #300] @ (8000dd4 ) 8000ca6: 4a4c ldr r2, [pc, #304] @ (8000dd8 ) 8000ca8: 601a str r2, [r3, #0] hadc3.Init.Resolution = ADC_RESOLUTION_16B; 8000caa: 4b4a ldr r3, [pc, #296] @ (8000dd4 ) 8000cac: 2200 movs r2, #0 8000cae: 609a str r2, [r3, #8] hadc3.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000cb0: 4b48 ldr r3, [pc, #288] @ (8000dd4 ) 8000cb2: 2201 movs r2, #1 8000cb4: 60da str r2, [r3, #12] hadc3.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000cb6: 4b47 ldr r3, [pc, #284] @ (8000dd4 ) 8000cb8: 2208 movs r2, #8 8000cba: 611a str r2, [r3, #16] hadc3.Init.LowPowerAutoWait = DISABLE; 8000cbc: 4b45 ldr r3, [pc, #276] @ (8000dd4 ) 8000cbe: 2200 movs r2, #0 8000cc0: 751a strb r2, [r3, #20] hadc3.Init.ContinuousConvMode = ENABLE; 8000cc2: 4b44 ldr r3, [pc, #272] @ (8000dd4 ) 8000cc4: 2201 movs r2, #1 8000cc6: 755a strb r2, [r3, #21] hadc3.Init.NbrOfConversion = 5; 8000cc8: 4b42 ldr r3, [pc, #264] @ (8000dd4 ) 8000cca: 2205 movs r2, #5 8000ccc: 619a str r2, [r3, #24] hadc3.Init.DiscontinuousConvMode = DISABLE; 8000cce: 4b41 ldr r3, [pc, #260] @ (8000dd4 ) 8000cd0: 2200 movs r2, #0 8000cd2: 771a strb r2, [r3, #28] hadc3.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T8_TRGO; 8000cd4: 4b3f ldr r3, [pc, #252] @ (8000dd4 ) 8000cd6: f44f 629c mov.w r2, #1248 @ 0x4e0 8000cda: 625a str r2, [r3, #36] @ 0x24 hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000cdc: 4b3d ldr r3, [pc, #244] @ (8000dd4 ) 8000cde: f44f 6280 mov.w r2, #1024 @ 0x400 8000ce2: 629a str r2, [r3, #40] @ 0x28 hadc3.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000ce4: 4b3b ldr r3, [pc, #236] @ (8000dd4 ) 8000ce6: 2201 movs r2, #1 8000ce8: 62da str r2, [r3, #44] @ 0x2c hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000cea: 4b3a ldr r3, [pc, #232] @ (8000dd4 ) 8000cec: 2200 movs r2, #0 8000cee: 631a str r2, [r3, #48] @ 0x30 hadc3.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000cf0: 4b38 ldr r3, [pc, #224] @ (8000dd4 ) 8000cf2: 2200 movs r2, #0 8000cf4: 635a str r2, [r3, #52] @ 0x34 hadc3.Init.OversamplingMode = DISABLE; 8000cf6: 4b37 ldr r3, [pc, #220] @ (8000dd4 ) 8000cf8: 2200 movs r2, #0 8000cfa: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc3) != HAL_OK) 8000cfe: 4835 ldr r0, [pc, #212] @ (8000dd4 ) 8000d00: f005 fb30 bl 8006364 8000d04: 4603 mov r3, r0 8000d06: 2b00 cmp r3, #0 8000d08: d001 beq.n 8000d0e { Error_Handler(); 8000d0a: f001 f8df bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_0; 8000d0e: 2301 movs r3, #1 8000d10: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8000d12: 2306 movs r3, #6 8000d14: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000d16: 2306 movs r3, #6 8000d18: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000d1a: f240 73ff movw r3, #2047 @ 0x7ff 8000d1e: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000d20: 2304 movs r3, #4 8000d22: 617b str r3, [r7, #20] sConfig.Offset = 0; 8000d24: 2300 movs r3, #0 8000d26: 61bb str r3, [r7, #24] sConfig.OffsetSignedSaturation = DISABLE; 8000d28: 2300 movs r3, #0 8000d2a: 777b strb r3, [r7, #29] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d2c: 1d3b adds r3, r7, #4 8000d2e: 4619 mov r1, r3 8000d30: 4828 ldr r0, [pc, #160] @ (8000dd4 ) 8000d32: f005 fd91 bl 8006858 8000d36: 4603 mov r3, r0 8000d38: 2b00 cmp r3, #0 8000d3a: d001 beq.n 8000d40 { Error_Handler(); 8000d3c: f001 f8c6 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 8000d40: 4b26 ldr r3, [pc, #152] @ (8000ddc ) 8000d42: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 8000d44: 230c movs r3, #12 8000d46: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d48: 1d3b adds r3, r7, #4 8000d4a: 4619 mov r1, r3 8000d4c: 4821 ldr r0, [pc, #132] @ (8000dd4 ) 8000d4e: f005 fd83 bl 8006858 8000d52: 4603 mov r3, r0 8000d54: 2b00 cmp r3, #0 8000d56: d001 beq.n 8000d5c { Error_Handler(); 8000d58: f001 f8b8 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_10; 8000d5c: 4b20 ldr r3, [pc, #128] @ (8000de0 ) 8000d5e: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8000d60: 2312 movs r3, #18 8000d62: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d64: 1d3b adds r3, r7, #4 8000d66: 4619 mov r1, r3 8000d68: 481a ldr r0, [pc, #104] @ (8000dd4 ) 8000d6a: f005 fd75 bl 8006858 8000d6e: 4603 mov r3, r0 8000d70: 2b00 cmp r3, #0 8000d72: d001 beq.n 8000d78 { Error_Handler(); 8000d74: f001 f8aa bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_11; 8000d78: 4b1a ldr r3, [pc, #104] @ (8000de4 ) 8000d7a: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_4; 8000d7c: 2318 movs r3, #24 8000d7e: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d80: 1d3b adds r3, r7, #4 8000d82: 4619 mov r1, r3 8000d84: 4813 ldr r0, [pc, #76] @ (8000dd4 ) 8000d86: f005 fd67 bl 8006858 8000d8a: 4603 mov r3, r0 8000d8c: 2b00 cmp r3, #0 8000d8e: d001 beq.n 8000d94 { Error_Handler(); 8000d90: f001 f89c bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; 8000d94: 4b14 ldr r3, [pc, #80] @ (8000de8 ) 8000d96: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_5; 8000d98: f44f 7380 mov.w r3, #256 @ 0x100 8000d9c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d9e: 1d3b adds r3, r7, #4 8000da0: 4619 mov r1, r3 8000da2: 480c ldr r0, [pc, #48] @ (8000dd4 ) 8000da4: f005 fd58 bl 8006858 8000da8: 4603 mov r3, r0 8000daa: 2b00 cmp r3, #0 8000dac: d001 beq.n 8000db2 { Error_Handler(); 8000dae: f001 f88d bl 8001ecc } /* USER CODE BEGIN ADC3_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc3, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000db2: f240 72ff movw r2, #2047 @ 0x7ff 8000db6: f04f 1101 mov.w r1, #65537 @ 0x10001 8000dba: 4806 ldr r0, [pc, #24] @ (8000dd4 ) 8000dbc: f006 fb8c bl 80074d8 8000dc0: 4603 mov r3, r0 8000dc2: 2b00 cmp r3, #0 8000dc4: d001 beq.n 8000dca { Error_Handler(); 8000dc6: f001 f881 bl 8001ecc } /* USER CODE END ADC3_Init 2 */ } 8000dca: bf00 nop 8000dcc: 3720 adds r7, #32 8000dce: 46bd mov sp, r7 8000dd0: bd80 pop {r7, pc} 8000dd2: bf00 nop 8000dd4: 240001e8 .word 0x240001e8 8000dd8: 58026000 .word 0x58026000 8000ddc: 04300002 .word 0x04300002 8000de0: 2a000400 .word 0x2a000400 8000de4: 2e300800 .word 0x2e300800 8000de8: cfb80000 .word 0xcfb80000 08000dec : * @brief COMP1 Initialization Function * @param None * @retval None */ static void MX_COMP1_Init(void) { 8000dec: b580 push {r7, lr} 8000dee: af00 add r7, sp, #0 /* USER CODE END COMP1_Init 0 */ /* USER CODE BEGIN COMP1_Init 1 */ /* USER CODE END COMP1_Init 1 */ hcomp1.Instance = COMP1; 8000df0: 4b12 ldr r3, [pc, #72] @ (8000e3c ) 8000df2: 4a13 ldr r2, [pc, #76] @ (8000e40 ) 8000df4: 601a str r2, [r3, #0] hcomp1.Init.InvertingInput = COMP_INPUT_MINUS_3_4VREFINT; 8000df6: 4b11 ldr r3, [pc, #68] @ (8000e3c ) 8000df8: 4a12 ldr r2, [pc, #72] @ (8000e44 ) 8000dfa: 611a str r2, [r3, #16] hcomp1.Init.NonInvertingInput = COMP_INPUT_PLUS_IO2; 8000dfc: 4b0f ldr r3, [pc, #60] @ (8000e3c ) 8000dfe: f44f 1280 mov.w r2, #1048576 @ 0x100000 8000e02: 60da str r2, [r3, #12] hcomp1.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED; 8000e04: 4b0d ldr r3, [pc, #52] @ (8000e3c ) 8000e06: 2200 movs r2, #0 8000e08: 619a str r2, [r3, #24] hcomp1.Init.Hysteresis = COMP_HYSTERESIS_NONE; 8000e0a: 4b0c ldr r3, [pc, #48] @ (8000e3c ) 8000e0c: 2200 movs r2, #0 8000e0e: 615a str r2, [r3, #20] hcomp1.Init.BlankingSrce = COMP_BLANKINGSRC_NONE; 8000e10: 4b0a ldr r3, [pc, #40] @ (8000e3c ) 8000e12: 2200 movs r2, #0 8000e14: 61da str r2, [r3, #28] hcomp1.Init.Mode = COMP_POWERMODE_HIGHSPEED; 8000e16: 4b09 ldr r3, [pc, #36] @ (8000e3c ) 8000e18: 2200 movs r2, #0 8000e1a: 609a str r2, [r3, #8] hcomp1.Init.WindowMode = COMP_WINDOWMODE_DISABLE; 8000e1c: 4b07 ldr r3, [pc, #28] @ (8000e3c ) 8000e1e: 2200 movs r2, #0 8000e20: 605a str r2, [r3, #4] hcomp1.Init.TriggerMode = COMP_TRIGGERMODE_NONE; 8000e22: 4b06 ldr r3, [pc, #24] @ (8000e3c ) 8000e24: 2200 movs r2, #0 8000e26: 621a str r2, [r3, #32] if (HAL_COMP_Init(&hcomp1) != HAL_OK) 8000e28: 4804 ldr r0, [pc, #16] @ (8000e3c ) 8000e2a: f006 fc97 bl 800775c 8000e2e: 4603 mov r3, r0 8000e30: 2b00 cmp r3, #0 8000e32: d001 beq.n 8000e38 { Error_Handler(); 8000e34: f001 f84a bl 8001ecc } /* USER CODE BEGIN COMP1_Init 2 */ /* USER CODE END COMP1_Init 2 */ } 8000e38: bf00 nop 8000e3a: bd80 pop {r7, pc} 8000e3c: 240003b4 .word 0x240003b4 8000e40: 5800380c .word 0x5800380c 8000e44: 00020006 .word 0x00020006 08000e48 : * @brief CRC Initialization Function * @param None * @retval None */ static void MX_CRC_Init(void) { 8000e48: b580 push {r7, lr} 8000e4a: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 8000e4c: 4b11 ldr r3, [pc, #68] @ (8000e94 ) 8000e4e: 4a12 ldr r2, [pc, #72] @ (8000e98 ) 8000e50: 601a str r2, [r3, #0] hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_DISABLE; 8000e52: 4b10 ldr r3, [pc, #64] @ (8000e94 ) 8000e54: 2201 movs r2, #1 8000e56: 711a strb r2, [r3, #4] hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE; 8000e58: 4b0e ldr r3, [pc, #56] @ (8000e94 ) 8000e5a: 2200 movs r2, #0 8000e5c: 715a strb r2, [r3, #5] hcrc.Init.GeneratingPolynomial = 4129; 8000e5e: 4b0d ldr r3, [pc, #52] @ (8000e94 ) 8000e60: f241 0221 movw r2, #4129 @ 0x1021 8000e64: 609a str r2, [r3, #8] hcrc.Init.CRCLength = CRC_POLYLENGTH_16B; 8000e66: 4b0b ldr r3, [pc, #44] @ (8000e94 ) 8000e68: 2208 movs r2, #8 8000e6a: 60da str r2, [r3, #12] hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE; 8000e6c: 4b09 ldr r3, [pc, #36] @ (8000e94 ) 8000e6e: 2200 movs r2, #0 8000e70: 615a str r2, [r3, #20] hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE; 8000e72: 4b08 ldr r3, [pc, #32] @ (8000e94 ) 8000e74: 2200 movs r2, #0 8000e76: 619a str r2, [r3, #24] hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; 8000e78: 4b06 ldr r3, [pc, #24] @ (8000e94 ) 8000e7a: 2201 movs r2, #1 8000e7c: 621a str r2, [r3, #32] if (HAL_CRC_Init(&hcrc) != HAL_OK) 8000e7e: 4805 ldr r0, [pc, #20] @ (8000e94 ) 8000e80: f006 ff56 bl 8007d30 8000e84: 4603 mov r3, r0 8000e86: 2b00 cmp r3, #0 8000e88: d001 beq.n 8000e8e { Error_Handler(); 8000e8a: f001 f81f bl 8001ecc } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 8000e8e: bf00 nop 8000e90: bd80 pop {r7, pc} 8000e92: bf00 nop 8000e94: 240003e0 .word 0x240003e0 8000e98: 58024c00 .word 0x58024c00 08000e9c : * @brief DAC1 Initialization Function * @param None * @retval None */ static void MX_DAC1_Init(void) { 8000e9c: b580 push {r7, lr} 8000e9e: b08a sub sp, #40 @ 0x28 8000ea0: af00 add r7, sp, #0 /* USER CODE BEGIN DAC1_Init 0 */ /* USER CODE END DAC1_Init 0 */ DAC_ChannelConfTypeDef sConfig = {0}; 8000ea2: 1d3b adds r3, r7, #4 8000ea4: 2224 movs r2, #36 @ 0x24 8000ea6: 2100 movs r1, #0 8000ea8: 4618 mov r0, r3 8000eaa: f017 fa75 bl 8018398 /* USER CODE END DAC1_Init 1 */ /** DAC Initialization */ hdac1.Instance = DAC1; 8000eae: 4b17 ldr r3, [pc, #92] @ (8000f0c ) 8000eb0: 4a17 ldr r2, [pc, #92] @ (8000f10 ) 8000eb2: 601a str r2, [r3, #0] if (HAL_DAC_Init(&hdac1) != HAL_OK) 8000eb4: 4815 ldr r0, [pc, #84] @ (8000f0c ) 8000eb6: f007 f941 bl 800813c 8000eba: 4603 mov r3, r0 8000ebc: 2b00 cmp r3, #0 8000ebe: d001 beq.n 8000ec4 { Error_Handler(); 8000ec0: f001 f804 bl 8001ecc } /** DAC channel OUT1 config */ sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; 8000ec4: 2300 movs r3, #0 8000ec6: 607b str r3, [r7, #4] sConfig.DAC_Trigger = DAC_TRIGGER_NONE; 8000ec8: 2300 movs r3, #0 8000eca: 60bb str r3, [r7, #8] sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; 8000ecc: 2300 movs r3, #0 8000ece: 60fb str r3, [r7, #12] sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE; 8000ed0: 2301 movs r3, #1 8000ed2: 613b str r3, [r7, #16] sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; 8000ed4: 2300 movs r3, #0 8000ed6: 617b str r3, [r7, #20] if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) 8000ed8: 1d3b adds r3, r7, #4 8000eda: 2200 movs r2, #0 8000edc: 4619 mov r1, r3 8000ede: 480b ldr r0, [pc, #44] @ (8000f0c ) 8000ee0: f007 fa30 bl 8008344 8000ee4: 4603 mov r3, r0 8000ee6: 2b00 cmp r3, #0 8000ee8: d001 beq.n 8000eee { Error_Handler(); 8000eea: f000 ffef bl 8001ecc } /** DAC channel OUT2 config */ if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK) 8000eee: 1d3b adds r3, r7, #4 8000ef0: 2210 movs r2, #16 8000ef2: 4619 mov r1, r3 8000ef4: 4805 ldr r0, [pc, #20] @ (8000f0c ) 8000ef6: f007 fa25 bl 8008344 8000efa: 4603 mov r3, r0 8000efc: 2b00 cmp r3, #0 8000efe: d001 beq.n 8000f04 { Error_Handler(); 8000f00: f000 ffe4 bl 8001ecc } /* USER CODE BEGIN DAC1_Init 2 */ /* USER CODE END DAC1_Init 2 */ } 8000f04: bf00 nop 8000f06: 3728 adds r7, #40 @ 0x28 8000f08: 46bd mov sp, r7 8000f0a: bd80 pop {r7, pc} 8000f0c: 24000404 .word 0x24000404 8000f10: 40007400 .word 0x40007400 08000f14 : * @brief IWDG1 Initialization Function * @param None * @retval None */ static void MX_IWDG1_Init(void) { 8000f14: b580 push {r7, lr} 8000f16: af00 add r7, sp, #0 /* USER CODE END IWDG1_Init 0 */ /* USER CODE BEGIN IWDG1_Init 1 */ /* USER CODE END IWDG1_Init 1 */ hiwdg1.Instance = IWDG1; 8000f18: 4b0a ldr r3, [pc, #40] @ (8000f44 ) 8000f1a: 4a0b ldr r2, [pc, #44] @ (8000f48 ) 8000f1c: 601a str r2, [r3, #0] hiwdg1.Init.Prescaler = IWDG_PRESCALER_64; 8000f1e: 4b09 ldr r3, [pc, #36] @ (8000f44 ) 8000f20: 2204 movs r2, #4 8000f22: 605a str r2, [r3, #4] hiwdg1.Init.Window = 249; 8000f24: 4b07 ldr r3, [pc, #28] @ (8000f44 ) 8000f26: 22f9 movs r2, #249 @ 0xf9 8000f28: 60da str r2, [r3, #12] hiwdg1.Init.Reload = 249; 8000f2a: 4b06 ldr r3, [pc, #24] @ (8000f44 ) 8000f2c: 22f9 movs r2, #249 @ 0xf9 8000f2e: 609a str r2, [r3, #8] if (HAL_IWDG_Init(&hiwdg1) != HAL_OK) 8000f30: 4804 ldr r0, [pc, #16] @ (8000f44 ) 8000f32: f00a fba4 bl 800b67e 8000f36: 4603 mov r3, r0 8000f38: 2b00 cmp r3, #0 8000f3a: d001 beq.n 8000f40 { Error_Handler(); 8000f3c: f000 ffc6 bl 8001ecc } /* USER CODE BEGIN IWDG1_Init 2 */ /* USER CODE END IWDG1_Init 2 */ } 8000f40: bf00 nop 8000f42: bd80 pop {r7, pc} 8000f44: 24000418 .word 0x24000418 8000f48: 58004800 .word 0x58004800 08000f4c : * @brief RNG Initialization Function * @param None * @retval None */ static void MX_RNG_Init(void) { 8000f4c: b580 push {r7, lr} 8000f4e: af00 add r7, sp, #0 /* USER CODE END RNG_Init 0 */ /* USER CODE BEGIN RNG_Init 1 */ /* USER CODE END RNG_Init 1 */ hrng.Instance = RNG; 8000f50: 4b07 ldr r3, [pc, #28] @ (8000f70 ) 8000f52: 4a08 ldr r2, [pc, #32] @ (8000f74 ) 8000f54: 601a str r2, [r3, #0] hrng.Init.ClockErrorDetection = RNG_CED_ENABLE; 8000f56: 4b06 ldr r3, [pc, #24] @ (8000f70 ) 8000f58: 2200 movs r2, #0 8000f5a: 605a str r2, [r3, #4] if (HAL_RNG_Init(&hrng) != HAL_OK) 8000f5c: 4804 ldr r0, [pc, #16] @ (8000f70 ) 8000f5e: f00e fa41 bl 800f3e4 8000f62: 4603 mov r3, r0 8000f64: 2b00 cmp r3, #0 8000f66: d001 beq.n 8000f6c { Error_Handler(); 8000f68: f000 ffb0 bl 8001ecc } /* USER CODE BEGIN RNG_Init 2 */ /* USER CODE END RNG_Init 2 */ } 8000f6c: bf00 nop 8000f6e: bd80 pop {r7, pc} 8000f70: 24000428 .word 0x24000428 8000f74: 48021800 .word 0x48021800 08000f78 : * @brief TIM1 Initialization Function * @param None * @retval None */ static void MX_TIM1_Init(void) { 8000f78: b5b0 push {r4, r5, r7, lr} 8000f7a: b096 sub sp, #88 @ 0x58 8000f7c: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000f7e: f107 034c add.w r3, r7, #76 @ 0x4c 8000f82: 2200 movs r2, #0 8000f84: 601a str r2, [r3, #0] 8000f86: 605a str r2, [r3, #4] 8000f88: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 8000f8a: f107 0330 add.w r3, r7, #48 @ 0x30 8000f8e: 2200 movs r2, #0 8000f90: 601a str r2, [r3, #0] 8000f92: 605a str r2, [r3, #4] 8000f94: 609a str r2, [r3, #8] 8000f96: 60da str r2, [r3, #12] 8000f98: 611a str r2, [r3, #16] 8000f9a: 615a str r2, [r3, #20] 8000f9c: 619a str r2, [r3, #24] TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 8000f9e: 1d3b adds r3, r7, #4 8000fa0: 222c movs r2, #44 @ 0x2c 8000fa2: 2100 movs r1, #0 8000fa4: 4618 mov r0, r3 8000fa6: f017 f9f7 bl 8018398 /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; 8000faa: 4b3e ldr r3, [pc, #248] @ (80010a4 ) 8000fac: 4a3e ldr r2, [pc, #248] @ (80010a8 ) 8000fae: 601a str r2, [r3, #0] htim1.Init.Prescaler = 199; 8000fb0: 4b3c ldr r3, [pc, #240] @ (80010a4 ) 8000fb2: 22c7 movs r2, #199 @ 0xc7 8000fb4: 605a str r2, [r3, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 8000fb6: 4b3b ldr r3, [pc, #236] @ (80010a4 ) 8000fb8: 2200 movs r2, #0 8000fba: 609a str r2, [r3, #8] htim1.Init.Period = 999; 8000fbc: 4b39 ldr r3, [pc, #228] @ (80010a4 ) 8000fbe: f240 32e7 movw r2, #999 @ 0x3e7 8000fc2: 60da str r2, [r3, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000fc4: 4b37 ldr r3, [pc, #220] @ (80010a4 ) 8000fc6: 2200 movs r2, #0 8000fc8: 611a str r2, [r3, #16] htim1.Init.RepetitionCounter = 0; 8000fca: 4b36 ldr r3, [pc, #216] @ (80010a4 ) 8000fcc: 2200 movs r2, #0 8000fce: 615a str r2, [r3, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8000fd0: 4b34 ldr r3, [pc, #208] @ (80010a4 ) 8000fd2: 2280 movs r2, #128 @ 0x80 8000fd4: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 8000fd6: 4833 ldr r0, [pc, #204] @ (80010a4 ) 8000fd8: f00e fba6 bl 800f728 8000fdc: 4603 mov r3, r0 8000fde: 2b00 cmp r3, #0 8000fe0: d001 beq.n 8000fe6 { Error_Handler(); 8000fe2: f000 ff73 bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000fe6: 2300 movs r3, #0 8000fe8: 64fb str r3, [r7, #76] @ 0x4c sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 8000fea: 2300 movs r3, #0 8000fec: 653b str r3, [r7, #80] @ 0x50 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000fee: 2300 movs r3, #0 8000ff0: 657b str r3, [r7, #84] @ 0x54 if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 8000ff2: f107 034c add.w r3, r7, #76 @ 0x4c 8000ff6: 4619 mov r1, r3 8000ff8: 482a ldr r0, [pc, #168] @ (80010a4 ) 8000ffa: f010 f8f9 bl 80111f0 8000ffe: 4603 mov r3, r0 8001000: 2b00 cmp r3, #0 8001002: d001 beq.n 8001008 { Error_Handler(); 8001004: f000 ff62 bl 8001ecc } sConfigOC.OCMode = TIM_OCMODE_PWM1; 8001008: 2360 movs r3, #96 @ 0x60 800100a: 633b str r3, [r7, #48] @ 0x30 sConfigOC.Pulse = 99; 800100c: 2363 movs r3, #99 @ 0x63 800100e: 637b str r3, [r7, #52] @ 0x34 sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8001010: 2300 movs r3, #0 8001012: 63bb str r3, [r7, #56] @ 0x38 sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 8001014: 2300 movs r3, #0 8001016: 63fb str r3, [r7, #60] @ 0x3c sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001018: 2300 movs r3, #0 800101a: 643b str r3, [r7, #64] @ 0x40 sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 800101c: 2300 movs r3, #0 800101e: 647b str r3, [r7, #68] @ 0x44 sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 8001020: 2300 movs r3, #0 8001022: 64bb str r3, [r7, #72] @ 0x48 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8001024: f107 0330 add.w r3, r7, #48 @ 0x30 8001028: 2204 movs r2, #4 800102a: 4619 mov r1, r3 800102c: 481d ldr r0, [pc, #116] @ (80010a4 ) 800102e: f00f f8cd bl 80101cc 8001032: 4603 mov r3, r0 8001034: 2b00 cmp r3, #0 8001036: d001 beq.n 800103c { Error_Handler(); 8001038: f000 ff48 bl 8001ecc } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 800103c: 2300 movs r3, #0 800103e: 607b str r3, [r7, #4] sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 8001040: 2300 movs r3, #0 8001042: 60bb str r3, [r7, #8] sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 8001044: 2300 movs r3, #0 8001046: 60fb str r3, [r7, #12] sBreakDeadTimeConfig.DeadTime = 0; 8001048: 2300 movs r3, #0 800104a: 613b str r3, [r7, #16] sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 800104c: 2300 movs r3, #0 800104e: 617b str r3, [r7, #20] sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 8001050: f44f 5300 mov.w r3, #8192 @ 0x2000 8001054: 61bb str r3, [r7, #24] sBreakDeadTimeConfig.BreakFilter = 0; 8001056: 2300 movs r3, #0 8001058: 61fb str r3, [r7, #28] sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 800105a: 2300 movs r3, #0 800105c: 623b str r3, [r7, #32] sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 800105e: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8001062: 627b str r3, [r7, #36] @ 0x24 sBreakDeadTimeConfig.Break2Filter = 0; 8001064: 2300 movs r3, #0 8001066: 62bb str r3, [r7, #40] @ 0x28 sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 8001068: 2300 movs r3, #0 800106a: 62fb str r3, [r7, #44] @ 0x2c if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 800106c: 1d3b adds r3, r7, #4 800106e: 4619 mov r1, r3 8001070: 480c ldr r0, [pc, #48] @ (80010a4 ) 8001072: f010 f94b bl 801130c 8001076: 4603 mov r3, r0 8001078: 2b00 cmp r3, #0 800107a: d001 beq.n 8001080 { Error_Handler(); 800107c: f000 ff26 bl 8001ecc } /* USER CODE BEGIN TIM1_Init 2 */ memcpy(&fanTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 8001080: 4b0a ldr r3, [pc, #40] @ (80010ac ) 8001082: 461d mov r5, r3 8001084: f107 0430 add.w r4, r7, #48 @ 0x30 8001088: cc0f ldmia r4!, {r0, r1, r2, r3} 800108a: c50f stmia r5!, {r0, r1, r2, r3} 800108c: e894 0007 ldmia.w r4, {r0, r1, r2} 8001090: e885 0007 stmia.w r5, {r0, r1, r2} /* USER CODE END TIM1_Init 2 */ HAL_TIM_MspPostInit(&htim1); 8001094: 4803 ldr r0, [pc, #12] @ (80010a4 ) 8001096: f003 fa05 bl 80044a4 } 800109a: bf00 nop 800109c: 3758 adds r7, #88 @ 0x58 800109e: 46bd mov sp, r7 80010a0: bdb0 pop {r4, r5, r7, pc} 80010a2: bf00 nop 80010a4: 2400043c .word 0x2400043c 80010a8: 40010000 .word 0x40010000 80010ac: 240007a4 .word 0x240007a4 080010b0 : * @brief TIM2 Initialization Function * @param None * @retval None */ static void MX_TIM2_Init(void) { 80010b0: b580 push {r7, lr} 80010b2: b08c sub sp, #48 @ 0x30 80010b4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80010b6: f107 0320 add.w r3, r7, #32 80010ba: 2200 movs r2, #0 80010bc: 601a str r2, [r3, #0] 80010be: 605a str r2, [r3, #4] 80010c0: 609a str r2, [r3, #8] 80010c2: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 80010c4: f107 0314 add.w r3, r7, #20 80010c8: 2200 movs r2, #0 80010ca: 601a str r2, [r3, #0] 80010cc: 605a str r2, [r3, #4] 80010ce: 609a str r2, [r3, #8] TIM_IC_InitTypeDef sConfigIC = {0}; 80010d0: 1d3b adds r3, r7, #4 80010d2: 2200 movs r2, #0 80010d4: 601a str r2, [r3, #0] 80010d6: 605a str r2, [r3, #4] 80010d8: 609a str r2, [r3, #8] 80010da: 60da str r2, [r3, #12] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 80010dc: 4b32 ldr r3, [pc, #200] @ (80011a8 ) 80010de: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 80010e2: 601a str r2, [r3, #0] htim2.Init.Prescaler = 9999; 80010e4: 4b30 ldr r3, [pc, #192] @ (80011a8 ) 80010e6: f242 720f movw r2, #9999 @ 0x270f 80010ea: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 80010ec: 4b2e ldr r3, [pc, #184] @ (80011a8 ) 80010ee: 2200 movs r2, #0 80010f0: 609a str r2, [r3, #8] htim2.Init.Period = 2999; 80010f2: 4b2d ldr r3, [pc, #180] @ (80011a8 ) 80010f4: f640 32b7 movw r2, #2999 @ 0xbb7 80010f8: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2; 80010fa: 4b2b ldr r3, [pc, #172] @ (80011a8 ) 80010fc: f44f 7280 mov.w r2, #256 @ 0x100 8001100: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001102: 4b29 ldr r3, [pc, #164] @ (80011a8 ) 8001104: 2280 movs r2, #128 @ 0x80 8001106: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 8001108: 4827 ldr r0, [pc, #156] @ (80011a8 ) 800110a: f00e f9cd bl 800f4a8 800110e: 4603 mov r3, r0 8001110: 2b00 cmp r3, #0 8001112: d001 beq.n 8001118 { Error_Handler(); 8001114: f000 feda bl 8001ecc } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8001118: f44f 5380 mov.w r3, #4096 @ 0x1000 800111c: 623b str r3, [r7, #32] if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 800111e: f107 0320 add.w r3, r7, #32 8001122: 4619 mov r1, r3 8001124: 4820 ldr r0, [pc, #128] @ (80011a8 ) 8001126: f00f f965 bl 80103f4 800112a: 4603 mov r3, r0 800112c: 2b00 cmp r3, #0 800112e: d001 beq.n 8001134 { Error_Handler(); 8001130: f000 fecc bl 8001ecc } if (HAL_TIM_IC_Init(&htim2) != HAL_OK) 8001134: 481c ldr r0, [pc, #112] @ (80011a8 ) 8001136: f00e fcf3 bl 800fb20 800113a: 4603 mov r3, r0 800113c: 2b00 cmp r3, #0 800113e: d001 beq.n 8001144 { Error_Handler(); 8001140: f000 fec4 bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 8001144: 2320 movs r3, #32 8001146: 617b str r3, [r7, #20] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; 8001148: 2380 movs r3, #128 @ 0x80 800114a: 61fb str r3, [r7, #28] if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 800114c: f107 0314 add.w r3, r7, #20 8001150: 4619 mov r1, r3 8001152: 4815 ldr r0, [pc, #84] @ (80011a8 ) 8001154: f010 f84c bl 80111f0 8001158: 4603 mov r3, r0 800115a: 2b00 cmp r3, #0 800115c: d001 beq.n 8001162 { Error_Handler(); 800115e: f000 feb5 bl 8001ecc } sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING; 8001162: 2300 movs r3, #0 8001164: 607b str r3, [r7, #4] sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI; 8001166: 2301 movs r3, #1 8001168: 60bb str r3, [r7, #8] sConfigIC.ICPrescaler = TIM_ICPSC_DIV1; 800116a: 2300 movs r3, #0 800116c: 60fb str r3, [r7, #12] sConfigIC.ICFilter = 0; 800116e: 2300 movs r3, #0 8001170: 613b str r3, [r7, #16] if (HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_3) != HAL_OK) 8001172: 1d3b adds r3, r7, #4 8001174: 2208 movs r2, #8 8001176: 4619 mov r1, r3 8001178: 480b ldr r0, [pc, #44] @ (80011a8 ) 800117a: f00e ff8a bl 8010092 800117e: 4603 mov r3, r0 8001180: 2b00 cmp r3, #0 8001182: d001 beq.n 8001188 { Error_Handler(); 8001184: f000 fea2 bl 8001ecc } if (HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_4) != HAL_OK) 8001188: 1d3b adds r3, r7, #4 800118a: 220c movs r2, #12 800118c: 4619 mov r1, r3 800118e: 4806 ldr r0, [pc, #24] @ (80011a8 ) 8001190: f00e ff7f bl 8010092 8001194: 4603 mov r3, r0 8001196: 2b00 cmp r3, #0 8001198: d001 beq.n 800119e { Error_Handler(); 800119a: f000 fe97 bl 8001ecc } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ } 800119e: bf00 nop 80011a0: 3730 adds r7, #48 @ 0x30 80011a2: 46bd mov sp, r7 80011a4: bd80 pop {r7, pc} 80011a6: bf00 nop 80011a8: 24000488 .word 0x24000488 080011ac : * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { 80011ac: b5b0 push {r4, r5, r7, lr} 80011ae: b08a sub sp, #40 @ 0x28 80011b0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 80011b2: f107 031c add.w r3, r7, #28 80011b6: 2200 movs r2, #0 80011b8: 601a str r2, [r3, #0] 80011ba: 605a str r2, [r3, #4] 80011bc: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 80011be: 463b mov r3, r7 80011c0: 2200 movs r2, #0 80011c2: 601a str r2, [r3, #0] 80011c4: 605a str r2, [r3, #4] 80011c6: 609a str r2, [r3, #8] 80011c8: 60da str r2, [r3, #12] 80011ca: 611a str r2, [r3, #16] 80011cc: 615a str r2, [r3, #20] 80011ce: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 80011d0: 4b48 ldr r3, [pc, #288] @ (80012f4 ) 80011d2: 4a49 ldr r2, [pc, #292] @ (80012f8 ) 80011d4: 601a str r2, [r3, #0] htim3.Init.Prescaler = 199; 80011d6: 4b47 ldr r3, [pc, #284] @ (80012f4 ) 80011d8: 22c7 movs r2, #199 @ 0xc7 80011da: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 80011dc: 4b45 ldr r3, [pc, #276] @ (80012f4 ) 80011de: 2200 movs r2, #0 80011e0: 609a str r2, [r3, #8] htim3.Init.Period = 999; 80011e2: 4b44 ldr r3, [pc, #272] @ (80012f4 ) 80011e4: f240 32e7 movw r2, #999 @ 0x3e7 80011e8: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80011ea: 4b42 ldr r3, [pc, #264] @ (80012f4 ) 80011ec: 2200 movs r2, #0 80011ee: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 80011f0: 4b40 ldr r3, [pc, #256] @ (80012f4 ) 80011f2: 2280 movs r2, #128 @ 0x80 80011f4: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 80011f6: 483f ldr r0, [pc, #252] @ (80012f4 ) 80011f8: f00e fa96 bl 800f728 80011fc: 4603 mov r3, r0 80011fe: 2b00 cmp r3, #0 8001200: d001 beq.n 8001206 { Error_Handler(); 8001202: f000 fe63 bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001206: 2300 movs r3, #0 8001208: 61fb str r3, [r7, #28] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800120a: 2300 movs r3, #0 800120c: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800120e: f107 031c add.w r3, r7, #28 8001212: 4619 mov r1, r3 8001214: 4837 ldr r0, [pc, #220] @ (80012f4 ) 8001216: f00f ffeb bl 80111f0 800121a: 4603 mov r3, r0 800121c: 2b00 cmp r3, #0 800121e: d001 beq.n 8001224 { Error_Handler(); 8001220: f000 fe54 bl 8001ecc } sConfigOC.OCMode = TIM_OCMODE_COMBINED_PWM1; 8001224: 4b35 ldr r3, [pc, #212] @ (80012fc ) 8001226: 603b str r3, [r7, #0] sConfigOC.Pulse = 500; 8001228: f44f 73fa mov.w r3, #500 @ 0x1f4 800122c: 607b str r3, [r7, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800122e: 2300 movs r3, #0 8001230: 60bb str r3, [r7, #8] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001232: 2300 movs r3, #0 8001234: 613b str r3, [r7, #16] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8001236: 463b mov r3, r7 8001238: 2200 movs r2, #0 800123a: 4619 mov r1, r3 800123c: 482d ldr r0, [pc, #180] @ (80012f4 ) 800123e: f00e ffc5 bl 80101cc 8001242: 4603 mov r3, r0 8001244: 2b00 cmp r3, #0 8001246: d001 beq.n 800124c { Error_Handler(); 8001248: f000 fe40 bl 8001ecc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_1); 800124c: 4b29 ldr r3, [pc, #164] @ (80012f4 ) 800124e: 681b ldr r3, [r3, #0] 8001250: 699a ldr r2, [r3, #24] 8001252: 4b28 ldr r3, [pc, #160] @ (80012f4 ) 8001254: 681b ldr r3, [r3, #0] 8001256: f022 0208 bic.w r2, r2, #8 800125a: 619a str r2, [r3, #24] sConfigOC.OCMode = TIM_OCMODE_PWM1; 800125c: 2360 movs r3, #96 @ 0x60 800125e: 603b str r3, [r7, #0] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8001260: 463b mov r3, r7 8001262: 2204 movs r2, #4 8001264: 4619 mov r1, r3 8001266: 4823 ldr r0, [pc, #140] @ (80012f4 ) 8001268: f00e ffb0 bl 80101cc 800126c: 4603 mov r3, r0 800126e: 2b00 cmp r3, #0 8001270: d001 beq.n 8001276 { Error_Handler(); 8001272: f000 fe2b bl 8001ecc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_2); 8001276: 4b1f ldr r3, [pc, #124] @ (80012f4 ) 8001278: 681b ldr r3, [r3, #0] 800127a: 699a ldr r2, [r3, #24] 800127c: 4b1d ldr r3, [pc, #116] @ (80012f4 ) 800127e: 681b ldr r3, [r3, #0] 8001280: f422 6200 bic.w r2, r2, #2048 @ 0x800 8001284: 619a str r2, [r3, #24] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 8001286: 463b mov r3, r7 8001288: 2208 movs r2, #8 800128a: 4619 mov r1, r3 800128c: 4819 ldr r0, [pc, #100] @ (80012f4 ) 800128e: f00e ff9d bl 80101cc 8001292: 4603 mov r3, r0 8001294: 2b00 cmp r3, #0 8001296: d001 beq.n 800129c { Error_Handler(); 8001298: f000 fe18 bl 8001ecc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_3); 800129c: 4b15 ldr r3, [pc, #84] @ (80012f4 ) 800129e: 681b ldr r3, [r3, #0] 80012a0: 69da ldr r2, [r3, #28] 80012a2: 4b14 ldr r3, [pc, #80] @ (80012f4 ) 80012a4: 681b ldr r3, [r3, #0] 80012a6: f022 0208 bic.w r2, r2, #8 80012aa: 61da str r2, [r3, #28] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 80012ac: 463b mov r3, r7 80012ae: 220c movs r2, #12 80012b0: 4619 mov r1, r3 80012b2: 4810 ldr r0, [pc, #64] @ (80012f4 ) 80012b4: f00e ff8a bl 80101cc 80012b8: 4603 mov r3, r0 80012ba: 2b00 cmp r3, #0 80012bc: d001 beq.n 80012c2 { Error_Handler(); 80012be: f000 fe05 bl 8001ecc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_4); 80012c2: 4b0c ldr r3, [pc, #48] @ (80012f4 ) 80012c4: 681b ldr r3, [r3, #0] 80012c6: 69da ldr r2, [r3, #28] 80012c8: 4b0a ldr r3, [pc, #40] @ (80012f4 ) 80012ca: 681b ldr r3, [r3, #0] 80012cc: f422 6200 bic.w r2, r2, #2048 @ 0x800 80012d0: 61da str r2, [r3, #28] /* USER CODE BEGIN TIM3_Init 2 */ memcpy(&motorXYTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 80012d2: 4b0b ldr r3, [pc, #44] @ (8001300 ) 80012d4: 461d mov r5, r3 80012d6: 463c mov r4, r7 80012d8: cc0f ldmia r4!, {r0, r1, r2, r3} 80012da: c50f stmia r5!, {r0, r1, r2, r3} 80012dc: e894 0007 ldmia.w r4, {r0, r1, r2} 80012e0: e885 0007 stmia.w r5, {r0, r1, r2} /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 80012e4: 4803 ldr r0, [pc, #12] @ (80012f4 ) 80012e6: f003 f8dd bl 80044a4 } 80012ea: bf00 nop 80012ec: 3728 adds r7, #40 @ 0x28 80012ee: 46bd mov sp, r7 80012f0: bdb0 pop {r4, r5, r7, pc} 80012f2: bf00 nop 80012f4: 240004d4 .word 0x240004d4 80012f8: 40000400 .word 0x40000400 80012fc: 00010040 .word 0x00010040 8001300: 240007c0 .word 0x240007c0 08001304 : * @brief TIM4 Initialization Function * @param None * @retval None */ static void MX_TIM4_Init(void) { 8001304: b580 push {r7, lr} 8001306: b08c sub sp, #48 @ 0x30 8001308: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800130a: f107 0320 add.w r3, r7, #32 800130e: 2200 movs r2, #0 8001310: 601a str r2, [r3, #0] 8001312: 605a str r2, [r3, #4] 8001314: 609a str r2, [r3, #8] 8001316: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001318: f107 0314 add.w r3, r7, #20 800131c: 2200 movs r2, #0 800131e: 601a str r2, [r3, #0] 8001320: 605a str r2, [r3, #4] 8001322: 609a str r2, [r3, #8] TIM_IC_InitTypeDef sConfigIC = {0}; 8001324: 1d3b adds r3, r7, #4 8001326: 2200 movs r2, #0 8001328: 601a str r2, [r3, #0] 800132a: 605a str r2, [r3, #4] 800132c: 609a str r2, [r3, #8] 800132e: 60da str r2, [r3, #12] /* USER CODE BEGIN TIM4_Init 1 */ /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; 8001330: 4b31 ldr r3, [pc, #196] @ (80013f8 ) 8001332: 4a32 ldr r2, [pc, #200] @ (80013fc ) 8001334: 601a str r2, [r3, #0] htim4.Init.Prescaler = 9999; 8001336: 4b30 ldr r3, [pc, #192] @ (80013f8 ) 8001338: f242 720f movw r2, #9999 @ 0x270f 800133c: 605a str r2, [r3, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 800133e: 4b2e ldr r3, [pc, #184] @ (80013f8 ) 8001340: 2200 movs r2, #0 8001342: 609a str r2, [r3, #8] htim4.Init.Period = 2999; 8001344: 4b2c ldr r3, [pc, #176] @ (80013f8 ) 8001346: f640 32b7 movw r2, #2999 @ 0xbb7 800134a: 60da str r2, [r3, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2; 800134c: 4b2a ldr r3, [pc, #168] @ (80013f8 ) 800134e: f44f 7280 mov.w r2, #256 @ 0x100 8001352: 611a str r2, [r3, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001354: 4b28 ldr r3, [pc, #160] @ (80013f8 ) 8001356: 2280 movs r2, #128 @ 0x80 8001358: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 800135a: 4827 ldr r0, [pc, #156] @ (80013f8 ) 800135c: f00e f8a4 bl 800f4a8 8001360: 4603 mov r3, r0 8001362: 2b00 cmp r3, #0 8001364: d001 beq.n 800136a { Error_Handler(); 8001366: f000 fdb1 bl 8001ecc } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800136a: f44f 5380 mov.w r3, #4096 @ 0x1000 800136e: 623b str r3, [r7, #32] if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 8001370: f107 0320 add.w r3, r7, #32 8001374: 4619 mov r1, r3 8001376: 4820 ldr r0, [pc, #128] @ (80013f8 ) 8001378: f00f f83c bl 80103f4 800137c: 4603 mov r3, r0 800137e: 2b00 cmp r3, #0 8001380: d001 beq.n 8001386 { Error_Handler(); 8001382: f000 fda3 bl 8001ecc } if (HAL_TIM_IC_Init(&htim4) != HAL_OK) 8001386: 481c ldr r0, [pc, #112] @ (80013f8 ) 8001388: f00e fbca bl 800fb20 800138c: 4603 mov r3, r0 800138e: 2b00 cmp r3, #0 8001390: d001 beq.n 8001396 { Error_Handler(); 8001392: f000 fd9b bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001396: 2300 movs r3, #0 8001398: 617b str r3, [r7, #20] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800139a: 2300 movs r3, #0 800139c: 61fb str r3, [r7, #28] if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 800139e: f107 0314 add.w r3, r7, #20 80013a2: 4619 mov r1, r3 80013a4: 4814 ldr r0, [pc, #80] @ (80013f8 ) 80013a6: f00f ff23 bl 80111f0 80013aa: 4603 mov r3, r0 80013ac: 2b00 cmp r3, #0 80013ae: d001 beq.n 80013b4 { Error_Handler(); 80013b0: f000 fd8c bl 8001ecc } sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING; 80013b4: 2300 movs r3, #0 80013b6: 607b str r3, [r7, #4] sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI; 80013b8: 2301 movs r3, #1 80013ba: 60bb str r3, [r7, #8] sConfigIC.ICPrescaler = TIM_ICPSC_DIV1; 80013bc: 2300 movs r3, #0 80013be: 60fb str r3, [r7, #12] sConfigIC.ICFilter = 0; 80013c0: 2300 movs r3, #0 80013c2: 613b str r3, [r7, #16] if (HAL_TIM_IC_ConfigChannel(&htim4, &sConfigIC, TIM_CHANNEL_3) != HAL_OK) 80013c4: 1d3b adds r3, r7, #4 80013c6: 2208 movs r2, #8 80013c8: 4619 mov r1, r3 80013ca: 480b ldr r0, [pc, #44] @ (80013f8 ) 80013cc: f00e fe61 bl 8010092 80013d0: 4603 mov r3, r0 80013d2: 2b00 cmp r3, #0 80013d4: d001 beq.n 80013da { Error_Handler(); 80013d6: f000 fd79 bl 8001ecc } if (HAL_TIM_IC_ConfigChannel(&htim4, &sConfigIC, TIM_CHANNEL_4) != HAL_OK) 80013da: 1d3b adds r3, r7, #4 80013dc: 220c movs r2, #12 80013de: 4619 mov r1, r3 80013e0: 4805 ldr r0, [pc, #20] @ (80013f8 ) 80013e2: f00e fe56 bl 8010092 80013e6: 4603 mov r3, r0 80013e8: 2b00 cmp r3, #0 80013ea: d001 beq.n 80013f0 { Error_Handler(); 80013ec: f000 fd6e bl 8001ecc } /* USER CODE BEGIN TIM4_Init 2 */ /* USER CODE END TIM4_Init 2 */ } 80013f0: bf00 nop 80013f2: 3730 adds r7, #48 @ 0x30 80013f4: 46bd mov sp, r7 80013f6: bd80 pop {r7, pc} 80013f8: 24000520 .word 0x24000520 80013fc: 40000800 .word 0x40000800 08001400 : * @brief TIM8 Initialization Function * @param None * @retval None */ static void MX_TIM8_Init(void) { 8001400: b580 push {r7, lr} 8001402: b088 sub sp, #32 8001404: af00 add r7, sp, #0 /* USER CODE BEGIN TIM8_Init 0 */ /* USER CODE END TIM8_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8001406: f107 0310 add.w r3, r7, #16 800140a: 2200 movs r2, #0 800140c: 601a str r2, [r3, #0] 800140e: 605a str r2, [r3, #4] 8001410: 609a str r2, [r3, #8] 8001412: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001414: 1d3b adds r3, r7, #4 8001416: 2200 movs r2, #0 8001418: 601a str r2, [r3, #0] 800141a: 605a str r2, [r3, #4] 800141c: 609a str r2, [r3, #8] /* USER CODE BEGIN TIM8_Init 1 */ /* USER CODE END TIM8_Init 1 */ htim8.Instance = TIM8; 800141e: 4b21 ldr r3, [pc, #132] @ (80014a4 ) 8001420: 4a21 ldr r2, [pc, #132] @ (80014a8 ) 8001422: 601a str r2, [r3, #0] htim8.Init.Prescaler = 9999; 8001424: 4b1f ldr r3, [pc, #124] @ (80014a4 ) 8001426: f242 720f movw r2, #9999 @ 0x270f 800142a: 605a str r2, [r3, #4] htim8.Init.CounterMode = TIM_COUNTERMODE_UP; 800142c: 4b1d ldr r3, [pc, #116] @ (80014a4 ) 800142e: 2200 movs r2, #0 8001430: 609a str r2, [r3, #8] htim8.Init.Period = 999; 8001432: 4b1c ldr r3, [pc, #112] @ (80014a4 ) 8001434: f240 32e7 movw r2, #999 @ 0x3e7 8001438: 60da str r2, [r3, #12] htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2; 800143a: 4b1a ldr r3, [pc, #104] @ (80014a4 ) 800143c: f44f 7280 mov.w r2, #256 @ 0x100 8001440: 611a str r2, [r3, #16] htim8.Init.RepetitionCounter = 0; 8001442: 4b18 ldr r3, [pc, #96] @ (80014a4 ) 8001444: 2200 movs r2, #0 8001446: 615a str r2, [r3, #20] htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001448: 4b16 ldr r3, [pc, #88] @ (80014a4 ) 800144a: 2280 movs r2, #128 @ 0x80 800144c: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim8) != HAL_OK) 800144e: 4815 ldr r0, [pc, #84] @ (80014a4 ) 8001450: f00e f82a bl 800f4a8 8001454: 4603 mov r3, r0 8001456: 2b00 cmp r3, #0 8001458: d001 beq.n 800145e { Error_Handler(); 800145a: f000 fd37 bl 8001ecc } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800145e: f44f 5380 mov.w r3, #4096 @ 0x1000 8001462: 613b str r3, [r7, #16] if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) 8001464: f107 0310 add.w r3, r7, #16 8001468: 4619 mov r1, r3 800146a: 480e ldr r0, [pc, #56] @ (80014a4 ) 800146c: f00e ffc2 bl 80103f4 8001470: 4603 mov r3, r0 8001472: 2b00 cmp r3, #0 8001474: d001 beq.n 800147a { Error_Handler(); 8001476: f000 fd29 bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 800147a: 2320 movs r3, #32 800147c: 607b str r3, [r7, #4] sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 800147e: 2300 movs r3, #0 8001480: 60bb str r3, [r7, #8] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; 8001482: 2380 movs r3, #128 @ 0x80 8001484: 60fb str r3, [r7, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 8001486: 1d3b adds r3, r7, #4 8001488: 4619 mov r1, r3 800148a: 4806 ldr r0, [pc, #24] @ (80014a4 ) 800148c: f00f feb0 bl 80111f0 8001490: 4603 mov r3, r0 8001492: 2b00 cmp r3, #0 8001494: d001 beq.n 800149a { Error_Handler(); 8001496: f000 fd19 bl 8001ecc } /* USER CODE BEGIN TIM8_Init 2 */ /* USER CODE END TIM8_Init 2 */ } 800149a: bf00 nop 800149c: 3720 adds r7, #32 800149e: 46bd mov sp, r7 80014a0: bd80 pop {r7, pc} 80014a2: bf00 nop 80014a4: 2400056c .word 0x2400056c 80014a8: 40010400 .word 0x40010400 080014ac : * @brief UART8 Initialization Function * @param None * @retval None */ static void MX_UART8_Init(void) { 80014ac: b580 push {r7, lr} 80014ae: af00 add r7, sp, #0 /* USER CODE END UART8_Init 0 */ /* USER CODE BEGIN UART8_Init 1 */ /* USER CODE END UART8_Init 1 */ huart8.Instance = UART8; 80014b0: 4b22 ldr r3, [pc, #136] @ (800153c ) 80014b2: 4a23 ldr r2, [pc, #140] @ (8001540 ) 80014b4: 601a str r2, [r3, #0] huart8.Init.BaudRate = 115200; 80014b6: 4b21 ldr r3, [pc, #132] @ (800153c ) 80014b8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80014bc: 605a str r2, [r3, #4] huart8.Init.WordLength = UART_WORDLENGTH_8B; 80014be: 4b1f ldr r3, [pc, #124] @ (800153c ) 80014c0: 2200 movs r2, #0 80014c2: 609a str r2, [r3, #8] huart8.Init.StopBits = UART_STOPBITS_1; 80014c4: 4b1d ldr r3, [pc, #116] @ (800153c ) 80014c6: 2200 movs r2, #0 80014c8: 60da str r2, [r3, #12] huart8.Init.Parity = UART_PARITY_NONE; 80014ca: 4b1c ldr r3, [pc, #112] @ (800153c ) 80014cc: 2200 movs r2, #0 80014ce: 611a str r2, [r3, #16] huart8.Init.Mode = UART_MODE_TX_RX; 80014d0: 4b1a ldr r3, [pc, #104] @ (800153c ) 80014d2: 220c movs r2, #12 80014d4: 615a str r2, [r3, #20] huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80014d6: 4b19 ldr r3, [pc, #100] @ (800153c ) 80014d8: 2200 movs r2, #0 80014da: 619a str r2, [r3, #24] huart8.Init.OverSampling = UART_OVERSAMPLING_16; 80014dc: 4b17 ldr r3, [pc, #92] @ (800153c ) 80014de: 2200 movs r2, #0 80014e0: 61da str r2, [r3, #28] huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 80014e2: 4b16 ldr r3, [pc, #88] @ (800153c ) 80014e4: 2200 movs r2, #0 80014e6: 621a str r2, [r3, #32] huart8.Init.ClockPrescaler = UART_PRESCALER_DIV1; 80014e8: 4b14 ldr r3, [pc, #80] @ (800153c ) 80014ea: 2200 movs r2, #0 80014ec: 625a str r2, [r3, #36] @ 0x24 huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 80014ee: 4b13 ldr r3, [pc, #76] @ (800153c ) 80014f0: 2200 movs r2, #0 80014f2: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart8) != HAL_OK) 80014f4: 4811 ldr r0, [pc, #68] @ (800153c ) 80014f6: f00f ffa5 bl 8011444 80014fa: 4603 mov r3, r0 80014fc: 2b00 cmp r3, #0 80014fe: d001 beq.n 8001504 { Error_Handler(); 8001500: f000 fce4 bl 8001ecc } if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8001504: 2100 movs r1, #0 8001506: 480d ldr r0, [pc, #52] @ (800153c ) 8001508: f012 fc45 bl 8013d96 800150c: 4603 mov r3, r0 800150e: 2b00 cmp r3, #0 8001510: d001 beq.n 8001516 { Error_Handler(); 8001512: f000 fcdb bl 8001ecc } if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8001516: 2100 movs r1, #0 8001518: 4808 ldr r0, [pc, #32] @ (800153c ) 800151a: f012 fc7a bl 8013e12 800151e: 4603 mov r3, r0 8001520: 2b00 cmp r3, #0 8001522: d001 beq.n 8001528 { Error_Handler(); 8001524: f000 fcd2 bl 8001ecc } if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK) 8001528: 4804 ldr r0, [pc, #16] @ (800153c ) 800152a: f012 fbfb bl 8013d24 800152e: 4603 mov r3, r0 8001530: 2b00 cmp r3, #0 8001532: d001 beq.n 8001538 { Error_Handler(); 8001534: f000 fcca bl 8001ecc } /* USER CODE BEGIN UART8_Init 2 */ /* USER CODE END UART8_Init 2 */ } 8001538: bf00 nop 800153a: bd80 pop {r7, pc} 800153c: 240005b8 .word 0x240005b8 8001540: 40007c00 .word 0x40007c00 08001544 : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 8001544: b580 push {r7, lr} 8001546: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8001548: 4b24 ldr r3, [pc, #144] @ (80015dc ) 800154a: 4a25 ldr r2, [pc, #148] @ (80015e0 ) 800154c: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800154e: 4b23 ldr r3, [pc, #140] @ (80015dc ) 8001550: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001554: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8001556: 4b21 ldr r3, [pc, #132] @ (80015dc ) 8001558: 2200 movs r2, #0 800155a: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 800155c: 4b1f ldr r3, [pc, #124] @ (80015dc ) 800155e: 2200 movs r2, #0 8001560: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8001562: 4b1e ldr r3, [pc, #120] @ (80015dc ) 8001564: 2200 movs r2, #0 8001566: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8001568: 4b1c ldr r3, [pc, #112] @ (80015dc ) 800156a: 220c movs r2, #12 800156c: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800156e: 4b1b ldr r3, [pc, #108] @ (80015dc ) 8001570: 2200 movs r2, #0 8001572: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8001574: 4b19 ldr r3, [pc, #100] @ (80015dc ) 8001576: 2200 movs r2, #0 8001578: 61da str r2, [r3, #28] huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 800157a: 4b18 ldr r3, [pc, #96] @ (80015dc ) 800157c: 2200 movs r2, #0 800157e: 621a str r2, [r3, #32] huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8001580: 4b16 ldr r3, [pc, #88] @ (80015dc ) 8001582: 2200 movs r2, #0 8001584: 625a str r2, [r3, #36] @ 0x24 huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_TXINVERT_INIT; 8001586: 4b15 ldr r3, [pc, #84] @ (80015dc ) 8001588: 2201 movs r2, #1 800158a: 629a str r2, [r3, #40] @ 0x28 huart1.AdvancedInit.TxPinLevelInvert = UART_ADVFEATURE_TXINV_ENABLE; 800158c: 4b13 ldr r3, [pc, #76] @ (80015dc ) 800158e: f44f 3200 mov.w r2, #131072 @ 0x20000 8001592: 62da str r2, [r3, #44] @ 0x2c if (HAL_UART_Init(&huart1) != HAL_OK) 8001594: 4811 ldr r0, [pc, #68] @ (80015dc ) 8001596: f00f ff55 bl 8011444 800159a: 4603 mov r3, r0 800159c: 2b00 cmp r3, #0 800159e: d001 beq.n 80015a4 { Error_Handler(); 80015a0: f000 fc94 bl 8001ecc } if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 80015a4: 2100 movs r1, #0 80015a6: 480d ldr r0, [pc, #52] @ (80015dc ) 80015a8: f012 fbf5 bl 8013d96 80015ac: 4603 mov r3, r0 80015ae: 2b00 cmp r3, #0 80015b0: d001 beq.n 80015b6 { Error_Handler(); 80015b2: f000 fc8b bl 8001ecc } if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 80015b6: 2100 movs r1, #0 80015b8: 4808 ldr r0, [pc, #32] @ (80015dc ) 80015ba: f012 fc2a bl 8013e12 80015be: 4603 mov r3, r0 80015c0: 2b00 cmp r3, #0 80015c2: d001 beq.n 80015c8 { Error_Handler(); 80015c4: f000 fc82 bl 8001ecc } if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) 80015c8: 4804 ldr r0, [pc, #16] @ (80015dc ) 80015ca: f012 fbab bl 8013d24 80015ce: 4603 mov r3, r0 80015d0: 2b00 cmp r3, #0 80015d2: d001 beq.n 80015d8 { Error_Handler(); 80015d4: f000 fc7a bl 8001ecc } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 80015d8: bf00 nop 80015da: bd80 pop {r7, pc} 80015dc: 2400064c .word 0x2400064c 80015e0: 40011000 .word 0x40011000 080015e4 : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 80015e4: b580 push {r7, lr} 80015e6: b082 sub sp, #8 80015e8: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 80015ea: 4b15 ldr r3, [pc, #84] @ (8001640 ) 80015ec: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 80015f0: 4a13 ldr r2, [pc, #76] @ (8001640 ) 80015f2: f043 0301 orr.w r3, r3, #1 80015f6: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 80015fa: 4b11 ldr r3, [pc, #68] @ (8001640 ) 80015fc: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8001600: f003 0301 and.w r3, r3, #1 8001604: 607b str r3, [r7, #4] 8001606: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0); 8001608: 2200 movs r2, #0 800160a: 2105 movs r1, #5 800160c: 200b movs r0, #11 800160e: f006 faef bl 8007bf0 HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 8001612: 200b movs r0, #11 8001614: f006 fb06 bl 8007c24 /* DMA1_Stream1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0); 8001618: 2200 movs r2, #0 800161a: 2105 movs r1, #5 800161c: 200c movs r0, #12 800161e: f006 fae7 bl 8007bf0 HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn); 8001622: 200c movs r0, #12 8001624: f006 fafe bl 8007c24 /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0); 8001628: 2200 movs r2, #0 800162a: 2105 movs r1, #5 800162c: 200d movs r0, #13 800162e: f006 fadf bl 8007bf0 HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 8001632: 200d movs r0, #13 8001634: f006 faf6 bl 8007c24 } 8001638: bf00 nop 800163a: 3708 adds r7, #8 800163c: 46bd mov sp, r7 800163e: bd80 pop {r7, pc} 8001640: 58024400 .word 0x58024400 08001644 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8001644: b580 push {r7, lr} 8001646: b08c sub sp, #48 @ 0x30 8001648: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800164a: f107 031c add.w r3, r7, #28 800164e: 2200 movs r2, #0 8001650: 601a str r2, [r3, #0] 8001652: 605a str r2, [r3, #4] 8001654: 609a str r2, [r3, #8] 8001656: 60da str r2, [r3, #12] 8001658: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 800165a: 4b58 ldr r3, [pc, #352] @ (80017bc ) 800165c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001660: 4a56 ldr r2, [pc, #344] @ (80017bc ) 8001662: f043 0380 orr.w r3, r3, #128 @ 0x80 8001666: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800166a: 4b54 ldr r3, [pc, #336] @ (80017bc ) 800166c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001670: f003 0380 and.w r3, r3, #128 @ 0x80 8001674: 61bb str r3, [r7, #24] 8001676: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOC_CLK_ENABLE(); 8001678: 4b50 ldr r3, [pc, #320] @ (80017bc ) 800167a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800167e: 4a4f ldr r2, [pc, #316] @ (80017bc ) 8001680: f043 0304 orr.w r3, r3, #4 8001684: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001688: 4b4c ldr r3, [pc, #304] @ (80017bc ) 800168a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800168e: f003 0304 and.w r3, r3, #4 8001692: 617b str r3, [r7, #20] 8001694: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001696: 4b49 ldr r3, [pc, #292] @ (80017bc ) 8001698: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800169c: 4a47 ldr r2, [pc, #284] @ (80017bc ) 800169e: f043 0301 orr.w r3, r3, #1 80016a2: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80016a6: 4b45 ldr r3, [pc, #276] @ (80017bc ) 80016a8: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016ac: f003 0301 and.w r3, r3, #1 80016b0: 613b str r3, [r7, #16] 80016b2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80016b4: 4b41 ldr r3, [pc, #260] @ (80017bc ) 80016b6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016ba: 4a40 ldr r2, [pc, #256] @ (80017bc ) 80016bc: f043 0302 orr.w r3, r3, #2 80016c0: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80016c4: 4b3d ldr r3, [pc, #244] @ (80017bc ) 80016c6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016ca: f003 0302 and.w r3, r3, #2 80016ce: 60fb str r3, [r7, #12] 80016d0: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 80016d2: 4b3a ldr r3, [pc, #232] @ (80017bc ) 80016d4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016d8: 4a38 ldr r2, [pc, #224] @ (80017bc ) 80016da: f043 0310 orr.w r3, r3, #16 80016de: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80016e2: 4b36 ldr r3, [pc, #216] @ (80017bc ) 80016e4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016e8: f003 0310 and.w r3, r3, #16 80016ec: 60bb str r3, [r7, #8] 80016ee: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 80016f0: 4b32 ldr r3, [pc, #200] @ (80017bc ) 80016f2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016f6: 4a31 ldr r2, [pc, #196] @ (80017bc ) 80016f8: f043 0308 orr.w r3, r3, #8 80016fc: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001700: 4b2e ldr r3, [pc, #184] @ (80017bc ) 8001702: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001706: f003 0308 and.w r3, r3, #8 800170a: 607b str r3, [r7, #4] 800170c: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 800170e: 2200 movs r2, #0 8001710: f24e 7180 movw r1, #59264 @ 0xe780 8001714: 482a ldr r0, [pc, #168] @ (80017c0 ) 8001716: f009 ff65 bl 800b5e4 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET); 800171a: 2200 movs r2, #0 800171c: 21f0 movs r1, #240 @ 0xf0 800171e: 4829 ldr r0, [pc, #164] @ (80017c4 ) 8001720: f009 ff60 bl 800b5e4 /*Configure GPIO pins : PE7 PE8 PE9 PE10 PE13 PE14 PE15 */ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 8001724: f24e 7380 movw r3, #59264 @ 0xe780 8001728: 61fb str r3, [r7, #28] |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800172a: 2301 movs r3, #1 800172c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800172e: 2300 movs r3, #0 8001730: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001732: 2300 movs r3, #0 8001734: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8001736: f107 031c add.w r3, r7, #28 800173a: 4619 mov r1, r3 800173c: 4820 ldr r0, [pc, #128] @ (80017c0 ) 800173e: f009 fd89 bl 800b254 /*Configure GPIO pins : PD8 PD9 PD10 PD11 PD12 PD13 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 8001742: f44f 537c mov.w r3, #16128 @ 0x3f00 8001746: 61fb str r3, [r7, #28] |GPIO_PIN_12|GPIO_PIN_13; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 8001748: f44f 1344 mov.w r3, #3211264 @ 0x310000 800174c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800174e: 2300 movs r3, #0 8001750: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001752: f107 031c add.w r3, r7, #28 8001756: 4619 mov r1, r3 8001758: 481a ldr r0, [pc, #104] @ (80017c4 ) 800175a: f009 fd7b bl 800b254 /*Configure GPIO pin : PD3 */ GPIO_InitStruct.Pin = GPIO_PIN_3; 800175e: 2308 movs r3, #8 8001760: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001762: 2300 movs r3, #0 8001764: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001766: 2300 movs r3, #0 8001768: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800176a: f107 031c add.w r3, r7, #28 800176e: 4619 mov r1, r3 8001770: 4814 ldr r0, [pc, #80] @ (80017c4 ) 8001772: f009 fd6f bl 800b254 /*Configure GPIO pins : PD4 PD5 PD6 PD7 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; 8001776: 23f0 movs r3, #240 @ 0xf0 8001778: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800177a: 2301 movs r3, #1 800177c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800177e: 2300 movs r3, #0 8001780: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001782: 2300 movs r3, #0 8001784: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001786: f107 031c add.w r3, r7, #28 800178a: 4619 mov r1, r3 800178c: 480d ldr r0, [pc, #52] @ (80017c4 ) 800178e: f009 fd61 bl 800b254 /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0); 8001792: 2200 movs r2, #0 8001794: 2105 movs r1, #5 8001796: 2017 movs r0, #23 8001798: f006 fa2a bl 8007bf0 HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); 800179c: 2017 movs r0, #23 800179e: f006 fa41 bl 8007c24 HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0); 80017a2: 2200 movs r2, #0 80017a4: 2105 movs r1, #5 80017a6: 2028 movs r0, #40 @ 0x28 80017a8: f006 fa22 bl 8007bf0 HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); 80017ac: 2028 movs r0, #40 @ 0x28 80017ae: f006 fa39 bl 8007c24 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 80017b2: bf00 nop 80017b4: 3730 adds r7, #48 @ 0x30 80017b6: 46bd mov sp, r7 80017b8: bd80 pop {r7, pc} 80017ba: bf00 nop 80017bc: 58024400 .word 0x58024400 80017c0: 58021000 .word 0x58021000 80017c4: 58020c00 .word 0x58020c00 080017c8 : /* USER CODE BEGIN 4 */ void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { 80017c8: b580 push {r7, lr} 80017ca: b08e sub sp, #56 @ 0x38 80017cc: af00 add r7, sp, #0 80017ce: 6078 str r0, [r7, #4] if(hadc->Instance == ADC1) 80017d0: 687b ldr r3, [r7, #4] 80017d2: 681b ldr r3, [r3, #0] 80017d4: 4a67 ldr r2, [pc, #412] @ (8001974 ) 80017d6: 4293 cmp r3, r2 80017d8: d13f bne.n 800185a { DbgLEDToggle(DBG_LED4); 80017da: 2080 movs r0, #128 @ 0x80 80017dc: f001 fbe6 bl 8002fac SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc1Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 80017e0: 4b65 ldr r3, [pc, #404] @ (8001978 ) 80017e2: f023 031f bic.w r3, r3, #31 80017e6: 637b str r3, [r7, #52] @ 0x34 80017e8: 2320 movs r3, #32 80017ea: 633b str r3, [r7, #48] @ 0x30 \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { 80017ec: 6b3b ldr r3, [r7, #48] @ 0x30 80017ee: 2b00 cmp r3, #0 80017f0: dd1d ble.n 800182e int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 80017f2: 6b7b ldr r3, [r7, #52] @ 0x34 80017f4: f003 021f and.w r2, r3, #31 80017f8: 6b3b ldr r3, [r7, #48] @ 0x30 80017fa: 4413 add r3, r2 80017fc: 62fb str r3, [r7, #44] @ 0x2c uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 80017fe: 6b7b ldr r3, [r7, #52] @ 0x34 8001800: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("dsb 0xF":::"memory"); 8001802: f3bf 8f4f dsb sy } 8001806: bf00 nop __DSB(); do { SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 8001808: 4a5c ldr r2, [pc, #368] @ (800197c ) 800180a: 6abb ldr r3, [r7, #40] @ 0x28 800180c: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 8001810: 6abb ldr r3, [r7, #40] @ 0x28 8001812: 3320 adds r3, #32 8001814: 62bb str r3, [r7, #40] @ 0x28 op_size -= __SCB_DCACHE_LINE_SIZE; 8001816: 6afb ldr r3, [r7, #44] @ 0x2c 8001818: 3b20 subs r3, #32 800181a: 62fb str r3, [r7, #44] @ 0x2c } while ( op_size > 0 ); 800181c: 6afb ldr r3, [r7, #44] @ 0x2c 800181e: 2b00 cmp r3, #0 8001820: dcf2 bgt.n 8001808 __ASM volatile ("dsb 0xF":::"memory"); 8001822: f3bf 8f4f dsb sy } 8001826: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8001828: f3bf 8f6f isb sy } 800182c: bf00 nop __DSB(); __ISB(); } #endif } 800182e: bf00 nop if(adc1MeasDataQueue != NULL) 8001830: 4b53 ldr r3, [pc, #332] @ (8001980 ) 8001832: 681b ldr r3, [r3, #0] 8001834: 2b00 cmp r3, #0 8001836: d006 beq.n 8001846 { osMessageQueuePut(adc1MeasDataQueue, &adc1Data, 0, 0); 8001838: 4b51 ldr r3, [pc, #324] @ (8001980 ) 800183a: 6818 ldr r0, [r3, #0] 800183c: 2300 movs r3, #0 800183e: 2200 movs r2, #0 8001840: 494d ldr r1, [pc, #308] @ (8001978 ) 8001842: f012 ff77 bl 8014734 } if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK) 8001846: 2207 movs r2, #7 8001848: 494b ldr r1, [pc, #300] @ (8001978 ) 800184a: 484e ldr r0, [pc, #312] @ (8001984 ) 800184c: f004 ff2c bl 80066a8 8001850: 4603 mov r3, r0 8001852: 2b00 cmp r3, #0 8001854: d001 beq.n 800185a { Error_Handler(); 8001856: f000 fb39 bl 8001ecc } } if(hadc->Instance == ADC2) 800185a: 687b ldr r3, [r7, #4] 800185c: 681b ldr r3, [r3, #0] 800185e: 4a4a ldr r2, [pc, #296] @ (8001988 ) 8001860: 4293 cmp r3, r2 8001862: d13c bne.n 80018de { SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc2Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 8001864: 4b49 ldr r3, [pc, #292] @ (800198c ) 8001866: f023 031f bic.w r3, r3, #31 800186a: 627b str r3, [r7, #36] @ 0x24 800186c: 2320 movs r3, #32 800186e: 623b str r3, [r7, #32] if ( dsize > 0 ) { 8001870: 6a3b ldr r3, [r7, #32] 8001872: 2b00 cmp r3, #0 8001874: dd1d ble.n 80018b2 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 8001876: 6a7b ldr r3, [r7, #36] @ 0x24 8001878: f003 021f and.w r2, r3, #31 800187c: 6a3b ldr r3, [r7, #32] 800187e: 4413 add r3, r2 8001880: 61fb str r3, [r7, #28] uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 8001882: 6a7b ldr r3, [r7, #36] @ 0x24 8001884: 61bb str r3, [r7, #24] __ASM volatile ("dsb 0xF":::"memory"); 8001886: f3bf 8f4f dsb sy } 800188a: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 800188c: 4a3b ldr r2, [pc, #236] @ (800197c ) 800188e: 69bb ldr r3, [r7, #24] 8001890: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 8001894: 69bb ldr r3, [r7, #24] 8001896: 3320 adds r3, #32 8001898: 61bb str r3, [r7, #24] op_size -= __SCB_DCACHE_LINE_SIZE; 800189a: 69fb ldr r3, [r7, #28] 800189c: 3b20 subs r3, #32 800189e: 61fb str r3, [r7, #28] } while ( op_size > 0 ); 80018a0: 69fb ldr r3, [r7, #28] 80018a2: 2b00 cmp r3, #0 80018a4: dcf2 bgt.n 800188c __ASM volatile ("dsb 0xF":::"memory"); 80018a6: f3bf 8f4f dsb sy } 80018aa: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80018ac: f3bf 8f6f isb sy } 80018b0: bf00 nop } 80018b2: bf00 nop if(adc2MeasDataQueue != NULL) 80018b4: 4b36 ldr r3, [pc, #216] @ (8001990 ) 80018b6: 681b ldr r3, [r3, #0] 80018b8: 2b00 cmp r3, #0 80018ba: d006 beq.n 80018ca { osMessageQueuePut(adc2MeasDataQueue, &adc2Data, 0, 0); 80018bc: 4b34 ldr r3, [pc, #208] @ (8001990 ) 80018be: 6818 ldr r0, [r3, #0] 80018c0: 2300 movs r3, #0 80018c2: 2200 movs r2, #0 80018c4: 4931 ldr r1, [pc, #196] @ (800198c ) 80018c6: f012 ff35 bl 8014734 } if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK) 80018ca: 2203 movs r2, #3 80018cc: 492f ldr r1, [pc, #188] @ (800198c ) 80018ce: 4831 ldr r0, [pc, #196] @ (8001994 ) 80018d0: f004 feea bl 80066a8 80018d4: 4603 mov r3, r0 80018d6: 2b00 cmp r3, #0 80018d8: d001 beq.n 80018de { Error_Handler(); 80018da: f000 faf7 bl 8001ecc } } if(hadc->Instance == ADC3) 80018de: 687b ldr r3, [r7, #4] 80018e0: 681b ldr r3, [r3, #0] 80018e2: 4a2d ldr r2, [pc, #180] @ (8001998 ) 80018e4: 4293 cmp r3, r2 80018e6: d13c bne.n 8001962 { SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc3Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 80018e8: 4b2c ldr r3, [pc, #176] @ (800199c ) 80018ea: f023 031f bic.w r3, r3, #31 80018ee: 617b str r3, [r7, #20] 80018f0: 2320 movs r3, #32 80018f2: 613b str r3, [r7, #16] if ( dsize > 0 ) { 80018f4: 693b ldr r3, [r7, #16] 80018f6: 2b00 cmp r3, #0 80018f8: dd1d ble.n 8001936 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 80018fa: 697b ldr r3, [r7, #20] 80018fc: f003 021f and.w r2, r3, #31 8001900: 693b ldr r3, [r7, #16] 8001902: 4413 add r3, r2 8001904: 60fb str r3, [r7, #12] uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 8001906: 697b ldr r3, [r7, #20] 8001908: 60bb str r3, [r7, #8] __ASM volatile ("dsb 0xF":::"memory"); 800190a: f3bf 8f4f dsb sy } 800190e: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 8001910: 4a1a ldr r2, [pc, #104] @ (800197c ) 8001912: 68bb ldr r3, [r7, #8] 8001914: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 8001918: 68bb ldr r3, [r7, #8] 800191a: 3320 adds r3, #32 800191c: 60bb str r3, [r7, #8] op_size -= __SCB_DCACHE_LINE_SIZE; 800191e: 68fb ldr r3, [r7, #12] 8001920: 3b20 subs r3, #32 8001922: 60fb str r3, [r7, #12] } while ( op_size > 0 ); 8001924: 68fb ldr r3, [r7, #12] 8001926: 2b00 cmp r3, #0 8001928: dcf2 bgt.n 8001910 __ASM volatile ("dsb 0xF":::"memory"); 800192a: f3bf 8f4f dsb sy } 800192e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8001930: f3bf 8f6f isb sy } 8001934: bf00 nop } 8001936: bf00 nop if(adc3MeasDataQueue != NULL) 8001938: 4b19 ldr r3, [pc, #100] @ (80019a0 ) 800193a: 681b ldr r3, [r3, #0] 800193c: 2b00 cmp r3, #0 800193e: d006 beq.n 800194e { osMessageQueuePut(adc3MeasDataQueue, &adc3Data, 0, 0); 8001940: 4b17 ldr r3, [pc, #92] @ (80019a0 ) 8001942: 6818 ldr r0, [r3, #0] 8001944: 2300 movs r3, #0 8001946: 2200 movs r2, #0 8001948: 4914 ldr r1, [pc, #80] @ (800199c ) 800194a: f012 fef3 bl 8014734 } if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK) 800194e: 2205 movs r2, #5 8001950: 4912 ldr r1, [pc, #72] @ (800199c ) 8001952: 4814 ldr r0, [pc, #80] @ (80019a4 ) 8001954: f004 fea8 bl 80066a8 8001958: 4603 mov r3, r0 800195a: 2b00 cmp r3, #0 800195c: d001 beq.n 8001962 { Error_Handler(); 800195e: f000 fab5 bl 8001ecc } }osTimerStop (debugLedTimerHandle); 8001962: 4b11 ldr r3, [pc, #68] @ (80019a8 ) 8001964: 681b ldr r3, [r3, #0] 8001966: 4618 mov r0, r3 8001968: f012 fd2c bl 80143c4 } 800196c: bf00 nop 800196e: 3738 adds r7, #56 @ 0x38 8001970: 46bd mov sp, r7 8001972: bd80 pop {r7, pc} 8001974: 40022000 .word 0x40022000 8001978: 240000c0 .word 0x240000c0 800197c: e000ed00 .word 0xe000ed00 8001980: 24000800 .word 0x24000800 8001984: 24000120 .word 0x24000120 8001988: 40022100 .word 0x40022100 800198c: 240000e0 .word 0x240000e0 8001990: 24000804 .word 0x24000804 8001994: 24000184 .word 0x24000184 8001998: 58026000 .word 0x58026000 800199c: 24000100 .word 0x24000100 80019a0: 24000808 .word 0x24000808 80019a4: 240001e8 .word 0x240001e8 80019a8: 240006e4 .word 0x240006e4 080019ac : void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 80019ac: b580 push {r7, lr} 80019ae: b084 sub sp, #16 80019b0: af00 add r7, sp, #0 80019b2: 6078 str r0, [r7, #4] if (htim->Instance == TIM4) 80019b4: 687b ldr r3, [r7, #4] 80019b6: 681b ldr r3, [r3, #0] 80019b8: 4a61 ldr r2, [pc, #388] @ (8001b40 ) 80019ba: 4293 cmp r3, r2 80019bc: d15a bne.n 8001a74 { if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_3) 80019be: 687b ldr r3, [r7, #4] 80019c0: 7f1b ldrb r3, [r3, #28] 80019c2: 2b04 cmp r3, #4 80019c4: d114 bne.n 80019f0 { if(encoderXChannelB > 0) 80019c6: 4b5f ldr r3, [pc, #380] @ (8001b44 ) 80019c8: 681b ldr r3, [r3, #0] 80019ca: 2b00 cmp r3, #0 80019cc: dd08 ble.n 80019e0 { encoderXChannelA = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_3); 80019ce: 2108 movs r1, #8 80019d0: 6878 ldr r0, [r7, #4] 80019d2: f00e fe07 bl 80105e4 80019d6: 4603 mov r3, r0 80019d8: 461a mov r2, r3 80019da: 4b5b ldr r3, [pc, #364] @ (8001b48 ) 80019dc: 601a str r2, [r3, #0] 80019de: e01f b.n 8001a20 } else { encoderXChannelA = 1; 80019e0: 4b59 ldr r3, [pc, #356] @ (8001b48 ) 80019e2: 2201 movs r2, #1 80019e4: 601a str r2, [r3, #0] __HAL_TIM_SET_COUNTER(htim,0); 80019e6: 687b ldr r3, [r7, #4] 80019e8: 681b ldr r3, [r3, #0] 80019ea: 2200 movs r2, #0 80019ec: 625a str r2, [r3, #36] @ 0x24 80019ee: e017 b.n 8001a20 } } else if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4) 80019f0: 687b ldr r3, [r7, #4] 80019f2: 7f1b ldrb r3, [r3, #28] 80019f4: 2b08 cmp r3, #8 80019f6: d113 bne.n 8001a20 { if(encoderXChannelA > 0) 80019f8: 4b53 ldr r3, [pc, #332] @ (8001b48 ) 80019fa: 681b ldr r3, [r3, #0] 80019fc: 2b00 cmp r3, #0 80019fe: dd08 ble.n 8001a12 { encoderXChannelB = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_4); 8001a00: 210c movs r1, #12 8001a02: 6878 ldr r0, [r7, #4] 8001a04: f00e fdee bl 80105e4 8001a08: 4603 mov r3, r0 8001a0a: 461a mov r2, r3 8001a0c: 4b4d ldr r3, [pc, #308] @ (8001b44 ) 8001a0e: 601a str r2, [r3, #0] 8001a10: e006 b.n 8001a20 } else { encoderXChannelB = 1; 8001a12: 4b4c ldr r3, [pc, #304] @ (8001b44 ) 8001a14: 2201 movs r2, #1 8001a16: 601a str r2, [r3, #0] __HAL_TIM_SET_COUNTER(htim,0); 8001a18: 687b ldr r3, [r7, #4] 8001a1a: 681b ldr r3, [r3, #0] 8001a1c: 2200 movs r2, #0 8001a1e: 625a str r2, [r3, #36] @ 0x24 } } if((encoderXChannelA != 0) && (encoderXChannelB != 0)) 8001a20: 4b49 ldr r3, [pc, #292] @ (8001b48 ) 8001a22: 681b ldr r3, [r3, #0] 8001a24: 2b00 cmp r3, #0 8001a26: f000 8086 beq.w 8001b36 8001a2a: 4b46 ldr r3, [pc, #280] @ (8001b44 ) 8001a2c: 681b ldr r3, [r3, #0] 8001a2e: 2b00 cmp r3, #0 8001a30: f000 8081 beq.w 8001b36 { EncoderData encoderData = { 0 }; 8001a34: 2300 movs r3, #0 8001a36: 81bb strh r3, [r7, #12] encoderData.axe = encoderAxeX; 8001a38: 2300 movs r3, #0 8001a3a: 733b strb r3, [r7, #12] encoderData.direction = encoderXChannelA - encoderXChannelB < 0 ? encoderCW : encoderCCW; 8001a3c: 4b42 ldr r3, [pc, #264] @ (8001b48 ) 8001a3e: 681a ldr r2, [r3, #0] 8001a40: 4b40 ldr r3, [pc, #256] @ (8001b44 ) 8001a42: 681b ldr r3, [r3, #0] 8001a44: 1ad3 subs r3, r2, r3 8001a46: 43db mvns r3, r3 8001a48: 0fdb lsrs r3, r3, #31 8001a4a: b2db uxtb r3, r3 8001a4c: 737b strb r3, [r7, #13] if (encoderData.direction == encoderCCW) 8001a4e: 7b7b ldrb r3, [r7, #13] 8001a50: 2b01 cmp r3, #1 8001a52: d100 bne.n 8001a56 { asm("nop;"); 8001a54: bf00 nop } osMessageQueuePut(encoderDataQueue, &encoderData, 0, 0); 8001a56: 4b3d ldr r3, [pc, #244] @ (8001b4c ) 8001a58: 6818 ldr r0, [r3, #0] 8001a5a: f107 010c add.w r1, r7, #12 8001a5e: 2300 movs r3, #0 8001a60: 2200 movs r2, #0 8001a62: f012 fe67 bl 8014734 encoderXChannelA = 0; 8001a66: 4b38 ldr r3, [pc, #224] @ (8001b48 ) 8001a68: 2200 movs r2, #0 8001a6a: 601a str r2, [r3, #0] encoderXChannelB = 0; 8001a6c: 4b35 ldr r3, [pc, #212] @ (8001b44 ) 8001a6e: 2200 movs r2, #0 8001a70: 601a str r2, [r3, #0] osMessageQueuePut(encoderDataQueue, &encoderData, 0, 0); encoderYChannelA = 0; encoderYChannelB = 0; } } } 8001a72: e060 b.n 8001b36 } else if (htim->Instance == TIM2) 8001a74: 687b ldr r3, [r7, #4] 8001a76: 681b ldr r3, [r3, #0] 8001a78: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001a7c: d15b bne.n 8001b36 if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_3) 8001a7e: 687b ldr r3, [r7, #4] 8001a80: 7f1b ldrb r3, [r3, #28] 8001a82: 2b04 cmp r3, #4 8001a84: d114 bne.n 8001ab0 if(encoderYChannelB > 0) 8001a86: 4b32 ldr r3, [pc, #200] @ (8001b50 ) 8001a88: 681b ldr r3, [r3, #0] 8001a8a: 2b00 cmp r3, #0 8001a8c: dd08 ble.n 8001aa0 encoderYChannelA = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_3); 8001a8e: 2108 movs r1, #8 8001a90: 6878 ldr r0, [r7, #4] 8001a92: f00e fda7 bl 80105e4 8001a96: 4603 mov r3, r0 8001a98: 461a mov r2, r3 8001a9a: 4b2e ldr r3, [pc, #184] @ (8001b54 ) 8001a9c: 601a str r2, [r3, #0] 8001a9e: e01f b.n 8001ae0 encoderYChannelA = 1; 8001aa0: 4b2c ldr r3, [pc, #176] @ (8001b54 ) 8001aa2: 2201 movs r2, #1 8001aa4: 601a str r2, [r3, #0] __HAL_TIM_SET_COUNTER(htim,0); 8001aa6: 687b ldr r3, [r7, #4] 8001aa8: 681b ldr r3, [r3, #0] 8001aaa: 2200 movs r2, #0 8001aac: 625a str r2, [r3, #36] @ 0x24 8001aae: e017 b.n 8001ae0 } else if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4) 8001ab0: 687b ldr r3, [r7, #4] 8001ab2: 7f1b ldrb r3, [r3, #28] 8001ab4: 2b08 cmp r3, #8 8001ab6: d113 bne.n 8001ae0 if(encoderYChannelA > 0) 8001ab8: 4b26 ldr r3, [pc, #152] @ (8001b54 ) 8001aba: 681b ldr r3, [r3, #0] 8001abc: 2b00 cmp r3, #0 8001abe: dd08 ble.n 8001ad2 encoderYChannelB = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_4); 8001ac0: 210c movs r1, #12 8001ac2: 6878 ldr r0, [r7, #4] 8001ac4: f00e fd8e bl 80105e4 8001ac8: 4603 mov r3, r0 8001aca: 461a mov r2, r3 8001acc: 4b20 ldr r3, [pc, #128] @ (8001b50 ) 8001ace: 601a str r2, [r3, #0] 8001ad0: e006 b.n 8001ae0 encoderYChannelB = 1; 8001ad2: 4b1f ldr r3, [pc, #124] @ (8001b50 ) 8001ad4: 2201 movs r2, #1 8001ad6: 601a str r2, [r3, #0] __HAL_TIM_SET_COUNTER(htim,0); 8001ad8: 687b ldr r3, [r7, #4] 8001ada: 681b ldr r3, [r3, #0] 8001adc: 2200 movs r2, #0 8001ade: 625a str r2, [r3, #36] @ 0x24 if((encoderYChannelA != 0) && (encoderYChannelB != 0)) 8001ae0: 4b1c ldr r3, [pc, #112] @ (8001b54 ) 8001ae2: 681b ldr r3, [r3, #0] 8001ae4: 2b00 cmp r3, #0 8001ae6: d026 beq.n 8001b36 8001ae8: 4b19 ldr r3, [pc, #100] @ (8001b50 ) 8001aea: 681b ldr r3, [r3, #0] 8001aec: 2b00 cmp r3, #0 8001aee: d022 beq.n 8001b36 EncoderData encoderData = { 0 }; 8001af0: 2300 movs r3, #0 8001af2: 813b strh r3, [r7, #8] encoderData.axe = encoderAxeY; 8001af4: 2301 movs r3, #1 8001af6: 723b strb r3, [r7, #8] encoderData.direction = encoderYChannelA - encoderYChannelB < 0 ? encoderCW : encoderCCW; 8001af8: 4b16 ldr r3, [pc, #88] @ (8001b54 ) 8001afa: 681a ldr r2, [r3, #0] 8001afc: 4b14 ldr r3, [pc, #80] @ (8001b50 ) 8001afe: 681b ldr r3, [r3, #0] 8001b00: 1ad3 subs r3, r2, r3 8001b02: 43db mvns r3, r3 8001b04: 0fdb lsrs r3, r3, #31 8001b06: b2db uxtb r3, r3 8001b08: 727b strb r3, [r7, #9] if (encoderData.direction == encoderCCW) 8001b0a: 7a7b ldrb r3, [r7, #9] 8001b0c: 2b01 cmp r3, #1 8001b0e: d100 bne.n 8001b12 asm("nop;"); 8001b10: bf00 nop if (encoderData.direction == encoderCW) 8001b12: 7a7b ldrb r3, [r7, #9] 8001b14: 2b00 cmp r3, #0 8001b16: d100 bne.n 8001b1a asm("nop;"); 8001b18: bf00 nop osMessageQueuePut(encoderDataQueue, &encoderData, 0, 0); 8001b1a: 4b0c ldr r3, [pc, #48] @ (8001b4c ) 8001b1c: 6818 ldr r0, [r3, #0] 8001b1e: f107 0108 add.w r1, r7, #8 8001b22: 2300 movs r3, #0 8001b24: 2200 movs r2, #0 8001b26: f012 fe05 bl 8014734 encoderYChannelA = 0; 8001b2a: 4b0a ldr r3, [pc, #40] @ (8001b54 ) 8001b2c: 2200 movs r2, #0 8001b2e: 601a str r2, [r3, #0] encoderYChannelB = 0; 8001b30: 4b07 ldr r3, [pc, #28] @ (8001b50 ) 8001b32: 2200 movs r2, #0 8001b34: 601a str r2, [r3, #0] } 8001b36: bf00 nop 8001b38: 3710 adds r7, #16 8001b3a: 46bd mov sp, r7 8001b3c: bd80 pop {r7, pc} 8001b3e: bf00 nop 8001b40: 40000800 .word 0x40000800 8001b44: 240007e0 .word 0x240007e0 8001b48: 240007dc .word 0x240007dc 8001b4c: 24000810 .word 0x24000810 8001b50: 240007e8 .word 0x240007e8 8001b54: 240007e4 .word 0x240007e4 08001b58 : * @param argument: Not used * @retval None */ /* USER CODE END Header_StartDefaultTask */ void StartDefaultTask(void *argument) { 8001b58: b580 push {r7, lr} 8001b5a: b082 sub sp, #8 8001b5c: af00 add r7, sp, #0 8001b5e: 6078 str r0, [r7, #4] /* USER CODE BEGIN 5 */ #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001b60: 485e ldr r0, [pc, #376] @ (8001cdc ) 8001b62: f009 fddb bl 800b71c #endif SelectCurrentSensorGain(CurrentSensorL1, csGain3); 8001b66: 2102 movs r1, #2 8001b68: 2000 movs r0, #0 8001b6a: f001 fa3d bl 8002fe8 SelectCurrentSensorGain(CurrentSensorL2, csGain3); 8001b6e: 2102 movs r1, #2 8001b70: 2001 movs r0, #1 8001b72: f001 fa39 bl 8002fe8 SelectCurrentSensorGain(CurrentSensorL3, csGain3); 8001b76: 2102 movs r1, #2 8001b78: 2002 movs r0, #2 8001b7a: f001 fa35 bl 8002fe8 EnableCurrentSensors(); 8001b7e: f001 fa27 bl 8002fd0 osDelay(pdMS_TO_TICKS(100)); 8001b82: 2064 movs r0, #100 @ 0x64 8001b84: f012 fb43 bl 801420e #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001b88: 4854 ldr r0, [pc, #336] @ (8001cdc ) 8001b8a: f009 fdc7 bl 800b71c #endif if(HAL_TIM_Base_Start(&htim8) != HAL_OK) 8001b8e: 4854 ldr r0, [pc, #336] @ (8001ce0 ) 8001b90: f00d fce2 bl 800f558 8001b94: 4603 mov r3, r0 8001b96: 2b00 cmp r3, #0 8001b98: d001 beq.n 8001b9e { Error_Handler(); 8001b9a: f000 f997 bl 8001ecc } if(HAL_TIM_Base_Start_IT(&htim2) != HAL_OK) 8001b9e: 4851 ldr r0, [pc, #324] @ (8001ce4 ) 8001ba0: f00d fd4a bl 800f638 8001ba4: 4603 mov r3, r0 8001ba6: 2b00 cmp r3, #0 8001ba8: d001 beq.n 8001bae { Error_Handler(); 8001baa: f000 f98f bl 8001ecc } if(HAL_TIM_Base_Start_IT(&htim4) != HAL_OK) 8001bae: 484e ldr r0, [pc, #312] @ (8001ce8 ) 8001bb0: f00d fd42 bl 800f638 8001bb4: 4603 mov r3, r0 8001bb6: 2b00 cmp r3, #0 8001bb8: d001 beq.n 8001bbe { Error_Handler(); 8001bba: f000 f987 bl 8001ecc } if(HAL_TIM_IC_Start_IT(&htim4, TIM_CHANNEL_3) != HAL_OK) 8001bbe: 2108 movs r1, #8 8001bc0: 4849 ldr r0, [pc, #292] @ (8001ce8 ) 8001bc2: f00e f80f bl 800fbe4 8001bc6: 4603 mov r3, r0 8001bc8: 2b00 cmp r3, #0 8001bca: d001 beq.n 8001bd0 { Error_Handler(); 8001bcc: f000 f97e bl 8001ecc } if(HAL_TIM_IC_Start_IT(&htim4, TIM_CHANNEL_4) != HAL_OK) 8001bd0: 210c movs r1, #12 8001bd2: 4845 ldr r0, [pc, #276] @ (8001ce8 ) 8001bd4: f00e f806 bl 800fbe4 8001bd8: 4603 mov r3, r0 8001bda: 2b00 cmp r3, #0 8001bdc: d001 beq.n 8001be2 { Error_Handler(); 8001bde: f000 f975 bl 8001ecc } if(HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_3) != HAL_OK) 8001be2: 2108 movs r1, #8 8001be4: 483f ldr r0, [pc, #252] @ (8001ce4 ) 8001be6: f00d fffd bl 800fbe4 8001bea: 4603 mov r3, r0 8001bec: 2b00 cmp r3, #0 8001bee: d001 beq.n 8001bf4 { Error_Handler(); 8001bf0: f000 f96c bl 8001ecc } if(HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_4) != HAL_OK) 8001bf4: 210c movs r1, #12 8001bf6: 483b ldr r0, [pc, #236] @ (8001ce4 ) 8001bf8: f00d fff4 bl 800fbe4 8001bfc: 4603 mov r3, r0 8001bfe: 2b00 cmp r3, #0 8001c00: d001 beq.n 8001c06 { Error_Handler(); 8001c02: f000 f963 bl 8001ecc } if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK) 8001c06: 2207 movs r2, #7 8001c08: 4938 ldr r1, [pc, #224] @ (8001cec ) 8001c0a: 4839 ldr r0, [pc, #228] @ (8001cf0 ) 8001c0c: f004 fd4c bl 80066a8 8001c10: 4603 mov r3, r0 8001c12: 2b00 cmp r3, #0 8001c14: d001 beq.n 8001c1a { Error_Handler(); 8001c16: f000 f959 bl 8001ecc } if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK) 8001c1a: 2203 movs r2, #3 8001c1c: 4935 ldr r1, [pc, #212] @ (8001cf4 ) 8001c1e: 4836 ldr r0, [pc, #216] @ (8001cf8 ) 8001c20: f004 fd42 bl 80066a8 8001c24: 4603 mov r3, r0 8001c26: 2b00 cmp r3, #0 8001c28: d001 beq.n 8001c2e { Error_Handler(); 8001c2a: f000 f94f bl 8001ecc } if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK) 8001c2e: 2205 movs r2, #5 8001c30: 4932 ldr r1, [pc, #200] @ (8001cfc ) 8001c32: 4833 ldr r0, [pc, #204] @ (8001d00 ) 8001c34: f004 fd38 bl 80066a8 8001c38: 4603 mov r3, r0 8001c3a: 2b00 cmp r3, #0 8001c3c: d001 beq.n 8001c42 { Error_Handler(); 8001c3e: f000 f945 bl 8001ecc } HAL_COMP_Start(&hcomp1); 8001c42: 4830 ldr r0, [pc, #192] @ (8001d04 ) 8001c44: f005 feb4 bl 80079b0 #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001c48: 4824 ldr r0, [pc, #144] @ (8001cdc ) 8001c4a: f009 fd67 bl 800b71c #endif /* Infinite loop */ for(;;) { osDelay(pdMS_TO_TICKS(100)); 8001c4e: 2064 movs r0, #100 @ 0x64 8001c50: f012 fadd bl 801420e #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001c54: 4821 ldr r0, [pc, #132] @ (8001cdc ) 8001c56: f009 fd61 bl 800b71c #endif if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 8001c5a: 2100 movs r1, #0 8001c5c: 482a ldr r0, [pc, #168] @ (8001d08 ) 8001c5e: f00e fd23 bl 80106a8 8001c62: 4603 mov r3, r0 8001c64: 2b01 cmp r3, #1 8001c66: d118 bne.n 8001c9a HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_2) == HAL_TIM_CHANNEL_STATE_READY) 8001c68: 2104 movs r1, #4 8001c6a: 4827 ldr r0, [pc, #156] @ (8001d08 ) 8001c6c: f00e fd1c bl 80106a8 8001c70: 4603 mov r3, r0 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 8001c72: 2b01 cmp r3, #1 8001c74: d111 bne.n 8001c9a { if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 8001c76: 4b25 ldr r3, [pc, #148] @ (8001d0c ) 8001c78: 681b ldr r3, [r3, #0] 8001c7a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001c7e: 4618 mov r0, r3 8001c80: f012 fc5d bl 801453e 8001c84: 4603 mov r3, r0 8001c86: 2b00 cmp r3, #0 8001c88: d107 bne.n 8001c9a { sensorsInfo.motorXStatus = 0; 8001c8a: 4b21 ldr r3, [pc, #132] @ (8001d10 ) 8001c8c: 2200 movs r2, #0 8001c8e: 751a strb r2, [r3, #20] osMutexRelease(sensorsInfoMutex); 8001c90: 4b1e ldr r3, [pc, #120] @ (8001d0c ) 8001c92: 681b ldr r3, [r3, #0] 8001c94: 4618 mov r0, r3 8001c96: f012 fc9d bl 80145d4 } } if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 8001c9a: 2108 movs r1, #8 8001c9c: 481a ldr r0, [pc, #104] @ (8001d08 ) 8001c9e: f00e fd03 bl 80106a8 8001ca2: 4603 mov r3, r0 8001ca4: 2b01 cmp r3, #1 8001ca6: d1d2 bne.n 8001c4e HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_4) == HAL_TIM_CHANNEL_STATE_READY) 8001ca8: 210c movs r1, #12 8001caa: 4817 ldr r0, [pc, #92] @ (8001d08 ) 8001cac: f00e fcfc bl 80106a8 8001cb0: 4603 mov r3, r0 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 8001cb2: 2b01 cmp r3, #1 8001cb4: d1cb bne.n 8001c4e { if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 8001cb6: 4b15 ldr r3, [pc, #84] @ (8001d0c ) 8001cb8: 681b ldr r3, [r3, #0] 8001cba: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001cbe: 4618 mov r0, r3 8001cc0: f012 fc3d bl 801453e 8001cc4: 4603 mov r3, r0 8001cc6: 2b00 cmp r3, #0 8001cc8: d1c1 bne.n 8001c4e { sensorsInfo.motorYStatus = 0; 8001cca: 4b11 ldr r3, [pc, #68] @ (8001d10 ) 8001ccc: 2200 movs r2, #0 8001cce: 755a strb r2, [r3, #21] osMutexRelease(sensorsInfoMutex); 8001cd0: 4b0e ldr r3, [pc, #56] @ (8001d0c ) 8001cd2: 681b ldr r3, [r3, #0] 8001cd4: 4618 mov r0, r3 8001cd6: f012 fc7d bl 80145d4 osDelay(pdMS_TO_TICKS(100)); 8001cda: e7b8 b.n 8001c4e 8001cdc: 24000418 .word 0x24000418 8001ce0: 2400056c .word 0x2400056c 8001ce4: 24000488 .word 0x24000488 8001ce8: 24000520 .word 0x24000520 8001cec: 240000c0 .word 0x240000c0 8001cf0: 24000120 .word 0x24000120 8001cf4: 240000e0 .word 0x240000e0 8001cf8: 24000184 .word 0x24000184 8001cfc: 24000100 .word 0x24000100 8001d00: 240001e8 .word 0x240001e8 8001d04: 240003b4 .word 0x240003b4 8001d08: 240004d4 .word 0x240004d4 8001d0c: 2400081c .word 0x2400081c 8001d10: 24000860 .word 0x24000860 08001d14 : /* USER CODE END 5 */ } /* debugLedTimerCallback function */ void debugLedTimerCallback(void *argument) { 8001d14: b580 push {r7, lr} 8001d16: b082 sub sp, #8 8001d18: af00 add r7, sp, #0 8001d1a: 6078 str r0, [r7, #4] /* USER CODE BEGIN debugLedTimerCallback */ DbgLEDOff (DBG_LED1); 8001d1c: 2010 movs r0, #16 8001d1e: f001 f933 bl 8002f88 /* USER CODE END debugLedTimerCallback */ } 8001d22: bf00 nop 8001d24: 3708 adds r7, #8 8001d26: 46bd mov sp, r7 8001d28: bd80 pop {r7, pc} ... 08001d2c : /* fanTimerCallback function */ void fanTimerCallback(void *argument) { 8001d2c: b580 push {r7, lr} 8001d2e: b082 sub sp, #8 8001d30: af00 add r7, sp, #0 8001d32: 6078 str r0, [r7, #4] /* USER CODE BEGIN fanTimerCallback */ HAL_TIM_PWM_Stop(&htim1, TIM_CHANNEL_2); 8001d34: 2104 movs r1, #4 8001d36: 4803 ldr r0, [pc, #12] @ (8001d44 ) 8001d38: f00d fe5c bl 800f9f4 /* USER CODE END fanTimerCallback */ } 8001d3c: bf00 nop 8001d3e: 3708 adds r7, #8 8001d40: 46bd mov sp, r7 8001d42: bd80 pop {r7, pc} 8001d44: 2400043c .word 0x2400043c 08001d48 : /* motorXTimerCallback function */ void motorXTimerCallback(void *argument) { 8001d48: b580 push {r7, lr} 8001d4a: b084 sub sp, #16 8001d4c: af02 add r7, sp, #8 8001d4e: 6078 str r0, [r7, #4] /* USER CODE BEGIN motorXTimerCallback */ MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, HiZ, 0); 8001d50: 2300 movs r3, #0 8001d52: 9301 str r3, [sp, #4] 8001d54: 2300 movs r3, #0 8001d56: 9300 str r3, [sp, #0] 8001d58: 2304 movs r3, #4 8001d5a: 2200 movs r2, #0 8001d5c: 4907 ldr r1, [pc, #28] @ (8001d7c ) 8001d5e: 4808 ldr r0, [pc, #32] @ (8001d80 ) 8001d60: f001 fac7 bl 80032f2 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_1); 8001d64: 2100 movs r1, #0 8001d66: 4806 ldr r0, [pc, #24] @ (8001d80 ) 8001d68: f00d fe44 bl 800f9f4 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_2); 8001d6c: 2104 movs r1, #4 8001d6e: 4804 ldr r0, [pc, #16] @ (8001d80 ) 8001d70: f00d fe40 bl 800f9f4 /* USER CODE END motorXTimerCallback */ } 8001d74: bf00 nop 8001d76: 3708 adds r7, #8 8001d78: 46bd mov sp, r7 8001d7a: bd80 pop {r7, pc} 8001d7c: 240007c0 .word 0x240007c0 8001d80: 240004d4 .word 0x240004d4 08001d84 : /* motorYTimerCallback function */ void motorYTimerCallback(void *argument) { 8001d84: b580 push {r7, lr} 8001d86: b084 sub sp, #16 8001d88: af02 add r7, sp, #8 8001d8a: 6078 str r0, [r7, #4] /* USER CODE BEGIN motorYTimerCallback */ MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, HiZ, 0); 8001d8c: 2300 movs r3, #0 8001d8e: 9301 str r3, [sp, #4] 8001d90: 2300 movs r3, #0 8001d92: 9300 str r3, [sp, #0] 8001d94: 230c movs r3, #12 8001d96: 2208 movs r2, #8 8001d98: 4907 ldr r1, [pc, #28] @ (8001db8 ) 8001d9a: 4808 ldr r0, [pc, #32] @ (8001dbc ) 8001d9c: f001 faa9 bl 80032f2 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_3); 8001da0: 2108 movs r1, #8 8001da2: 4806 ldr r0, [pc, #24] @ (8001dbc ) 8001da4: f00d fe26 bl 800f9f4 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_4); 8001da8: 210c movs r1, #12 8001daa: 4804 ldr r0, [pc, #16] @ (8001dbc ) 8001dac: f00d fe22 bl 800f9f4 /* USER CODE END motorYTimerCallback */ } 8001db0: bf00 nop 8001db2: 3708 adds r7, #8 8001db4: 46bd mov sp, r7 8001db6: bd80 pop {r7, pc} 8001db8: 240007c0 .word 0x240007c0 8001dbc: 240004d4 .word 0x240004d4 08001dc0 : /* MPU Configuration */ void MPU_Config(void) { 8001dc0: b580 push {r7, lr} 8001dc2: b084 sub sp, #16 8001dc4: af00 add r7, sp, #0 MPU_Region_InitTypeDef MPU_InitStruct = {0}; 8001dc6: 463b mov r3, r7 8001dc8: 2200 movs r2, #0 8001dca: 601a str r2, [r3, #0] 8001dcc: 605a str r2, [r3, #4] 8001dce: 609a str r2, [r3, #8] 8001dd0: 60da str r2, [r3, #12] /* Disables the MPU */ HAL_MPU_Disable(); 8001dd2: f005 ff35 bl 8007c40 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; 8001dd6: 2301 movs r3, #1 8001dd8: 703b strb r3, [r7, #0] MPU_InitStruct.Number = MPU_REGION_NUMBER0; 8001dda: 2300 movs r3, #0 8001ddc: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x0; 8001dde: 2300 movs r3, #0 8001de0: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; 8001de2: 231f movs r3, #31 8001de4: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x87; 8001de6: 2387 movs r3, #135 @ 0x87 8001de8: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8001dea: 2300 movs r3, #0 8001dec: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; 8001dee: 2300 movs r3, #0 8001df0: 72fb strb r3, [r7, #11] MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; 8001df2: 2301 movs r3, #1 8001df4: 733b strb r3, [r7, #12] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8001df6: 2301 movs r3, #1 8001df8: 737b strb r3, [r7, #13] MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; 8001dfa: 2300 movs r3, #0 8001dfc: 73bb strb r3, [r7, #14] MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; 8001dfe: 2300 movs r3, #0 8001e00: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001e02: 463b mov r3, r7 8001e04: 4618 mov r0, r3 8001e06: f005 ff53 bl 8007cb0 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER1; 8001e0a: 2301 movs r3, #1 8001e0c: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24020000; 8001e0e: 4b13 ldr r3, [pc, #76] @ (8001e5c ) 8001e10: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_128KB; 8001e12: 2310 movs r3, #16 8001e14: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x0; 8001e16: 2300 movs r3, #0 8001e18: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; 8001e1a: 2301 movs r3, #1 8001e1c: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; 8001e1e: 2303 movs r3, #3 8001e20: 72fb strb r3, [r7, #11] MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 8001e22: 2300 movs r3, #0 8001e24: 737b strb r3, [r7, #13] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001e26: 463b mov r3, r7 8001e28: 4618 mov r0, r3 8001e2a: f005 ff41 bl 8007cb0 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER2; 8001e2e: 2302 movs r3, #2 8001e30: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24040000; 8001e32: 4b0b ldr r3, [pc, #44] @ (8001e60 ) 8001e34: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_512B; 8001e36: 2308 movs r3, #8 8001e38: 723b strb r3, [r7, #8] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8001e3a: 2300 movs r3, #0 8001e3c: 72bb strb r3, [r7, #10] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8001e3e: 2301 movs r3, #1 8001e40: 737b strb r3, [r7, #13] MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; 8001e42: 2301 movs r3, #1 8001e44: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001e46: 463b mov r3, r7 8001e48: 4618 mov r0, r3 8001e4a: f005 ff31 bl 8007cb0 /* Enables the MPU */ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); 8001e4e: 2004 movs r0, #4 8001e50: f005 ff0e bl 8007c70 } 8001e54: bf00 nop 8001e56: 3710 adds r7, #16 8001e58: 46bd mov sp, r7 8001e5a: bd80 pop {r7, pc} 8001e5c: 24020000 .word 0x24020000 8001e60: 24040000 .word 0x24040000 08001e64 : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8001e64: b580 push {r7, lr} 8001e66: b082 sub sp, #8 8001e68: af00 add r7, sp, #0 8001e6a: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM6) { 8001e6c: 687b ldr r3, [r7, #4] 8001e6e: 681b ldr r3, [r3, #0] 8001e70: 4a10 ldr r2, [pc, #64] @ (8001eb4 ) 8001e72: 4293 cmp r3, r2 8001e74: d102 bne.n 8001e7c HAL_IncTick(); 8001e76: f004 f801 bl 8005e7c { encoderYChannelA = 0; encoderYChannelB = 0; } /* USER CODE END Callback 1 */ } 8001e7a: e016 b.n 8001eaa else if (htim->Instance == TIM4) 8001e7c: 687b ldr r3, [r7, #4] 8001e7e: 681b ldr r3, [r3, #0] 8001e80: 4a0d ldr r2, [pc, #52] @ (8001eb8 ) 8001e82: 4293 cmp r3, r2 8001e84: d106 bne.n 8001e94 encoderXChannelA = 0; 8001e86: 4b0d ldr r3, [pc, #52] @ (8001ebc ) 8001e88: 2200 movs r2, #0 8001e8a: 601a str r2, [r3, #0] encoderXChannelB = 0; 8001e8c: 4b0c ldr r3, [pc, #48] @ (8001ec0 ) 8001e8e: 2200 movs r2, #0 8001e90: 601a str r2, [r3, #0] } 8001e92: e00a b.n 8001eaa else if (htim->Instance == TIM2) 8001e94: 687b ldr r3, [r7, #4] 8001e96: 681b ldr r3, [r3, #0] 8001e98: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001e9c: d105 bne.n 8001eaa encoderYChannelA = 0; 8001e9e: 4b09 ldr r3, [pc, #36] @ (8001ec4 ) 8001ea0: 2200 movs r2, #0 8001ea2: 601a str r2, [r3, #0] encoderYChannelB = 0; 8001ea4: 4b08 ldr r3, [pc, #32] @ (8001ec8 ) 8001ea6: 2200 movs r2, #0 8001ea8: 601a str r2, [r3, #0] } 8001eaa: bf00 nop 8001eac: 3708 adds r7, #8 8001eae: 46bd mov sp, r7 8001eb0: bd80 pop {r7, pc} 8001eb2: bf00 nop 8001eb4: 40001000 .word 0x40001000 8001eb8: 40000800 .word 0x40000800 8001ebc: 240007dc .word 0x240007dc 8001ec0: 240007e0 .word 0x240007e0 8001ec4: 240007e4 .word 0x240007e4 8001ec8: 240007e8 .word 0x240007e8 08001ecc : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001ecc: b580 push {r7, lr} 8001ece: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 8001ed0: b672 cpsid i } 8001ed2: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); NVIC_SystemReset(); 8001ed4: f7fe fb88 bl 80005e8 <__NVIC_SystemReset> 08001ed8 : extern osTimerId_t motorXTimerHandle; extern osTimerId_t motorYTimerHandle; //extern osMutexId_t positionSettingMutex; void MeasTasksInit (void) { 8001ed8: b580 push {r7, lr} 8001eda: b0ae sub sp, #184 @ 0xb8 8001edc: af00 add r7, sp, #0 vRefmVMutex = osMutexNew (NULL); 8001ede: 2000 movs r0, #0 8001ee0: f012 faa7 bl 8014432 8001ee4: 4603 mov r3, r0 8001ee6: 4a58 ldr r2, [pc, #352] @ (8002048 ) 8001ee8: 6013 str r3, [r2, #0] resMeasurementsMutex = osMutexNew (NULL); 8001eea: 2000 movs r0, #0 8001eec: f012 faa1 bl 8014432 8001ef0: 4603 mov r3, r0 8001ef2: 4a56 ldr r2, [pc, #344] @ (800204c ) 8001ef4: 6013 str r3, [r2, #0] sensorsInfoMutex = osMutexNew (NULL); 8001ef6: 2000 movs r0, #0 8001ef8: f012 fa9b bl 8014432 8001efc: 4603 mov r3, r0 8001efe: 4a54 ldr r2, [pc, #336] @ (8002050 ) 8001f00: 6013 str r3, [r2, #0] ILxRefMutex = osMutexNew (NULL); 8001f02: 2000 movs r0, #0 8001f04: f012 fa95 bl 8014432 8001f08: 4603 mov r3, r0 8001f0a: 4a52 ldr r2, [pc, #328] @ (8002054 ) 8001f0c: 6013 str r3, [r2, #0] adc1MeasDataQueue = osMessageQueueNew (8, sizeof (ADC1_Data), NULL); 8001f0e: 2200 movs r2, #0 8001f10: 2120 movs r1, #32 8001f12: 2008 movs r0, #8 8001f14: f012 fb9b bl 801464e 8001f18: 4603 mov r3, r0 8001f1a: 4a4f ldr r2, [pc, #316] @ (8002058 ) 8001f1c: 6013 str r3, [r2, #0] adc2MeasDataQueue = osMessageQueueNew (8, sizeof (ADC2_Data), NULL); 8001f1e: 2200 movs r2, #0 8001f20: 2120 movs r1, #32 8001f22: 2008 movs r0, #8 8001f24: f012 fb93 bl 801464e 8001f28: 4603 mov r3, r0 8001f2a: 4a4c ldr r2, [pc, #304] @ (800205c ) 8001f2c: 6013 str r3, [r2, #0] adc3MeasDataQueue = osMessageQueueNew (8, sizeof (ADC3_Data), NULL); 8001f2e: 2200 movs r2, #0 8001f30: 2120 movs r1, #32 8001f32: 2008 movs r0, #8 8001f34: f012 fb8b bl 801464e 8001f38: 4603 mov r3, r0 8001f3a: 4a49 ldr r2, [pc, #292] @ (8002060 ) 8001f3c: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttradc1MeasTask = { 0 }; 8001f3e: f107 0394 add.w r3, r7, #148 @ 0x94 8001f42: 2224 movs r2, #36 @ 0x24 8001f44: 2100 movs r1, #0 8001f46: 4618 mov r0, r3 8001f48: f016 fa26 bl 8018398 osThreadAttr_t osThreadAttradc2MeasTask = { 0 }; 8001f4c: f107 0370 add.w r3, r7, #112 @ 0x70 8001f50: 2224 movs r2, #36 @ 0x24 8001f52: 2100 movs r1, #0 8001f54: 4618 mov r0, r3 8001f56: f016 fa1f bl 8018398 osThreadAttr_t osThreadAttradc3MeasTask = { 0 }; 8001f5a: f107 034c add.w r3, r7, #76 @ 0x4c 8001f5e: 2224 movs r2, #36 @ 0x24 8001f60: 2100 movs r1, #0 8001f62: 4618 mov r0, r3 8001f64: f016 fa18 bl 8018398 osThreadAttradc1MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001f68: f44f 6380 mov.w r3, #1024 @ 0x400 8001f6c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 osThreadAttradc1MeasTask.priority = (osPriority_t)osPriorityRealtime; 8001f70: 2330 movs r3, #48 @ 0x30 8001f72: f8c7 30ac str.w r3, [r7, #172] @ 0xac osThreadAttradc2MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001f76: f44f 6380 mov.w r3, #1024 @ 0x400 8001f7a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 osThreadAttradc2MeasTask.priority = (osPriority_t)osPriorityRealtime; 8001f7e: 2330 movs r3, #48 @ 0x30 8001f80: f8c7 3088 str.w r3, [r7, #136] @ 0x88 osThreadAttradc3MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001f84: f44f 6380 mov.w r3, #1024 @ 0x400 8001f88: 663b str r3, [r7, #96] @ 0x60 osThreadAttradc3MeasTask.priority = (osPriority_t)osPriorityNormal; 8001f8a: 2318 movs r3, #24 8001f8c: 667b str r3, [r7, #100] @ 0x64 adc1MeasTaskHandle = osThreadNew (ADC1MeasTask, NULL, &osThreadAttradc1MeasTask); 8001f8e: f107 0394 add.w r3, r7, #148 @ 0x94 8001f92: 461a mov r2, r3 8001f94: 2100 movs r1, #0 8001f96: 4833 ldr r0, [pc, #204] @ (8002064 ) 8001f98: f012 f8a6 bl 80140e8 8001f9c: 4603 mov r3, r0 8001f9e: 4a32 ldr r2, [pc, #200] @ (8002068 ) 8001fa0: 6013 str r3, [r2, #0] adc2MeasTaskHandle = osThreadNew (ADC2MeasTask, NULL, &osThreadAttradc2MeasTask); 8001fa2: f107 0370 add.w r3, r7, #112 @ 0x70 8001fa6: 461a mov r2, r3 8001fa8: 2100 movs r1, #0 8001faa: 4830 ldr r0, [pc, #192] @ (800206c ) 8001fac: f012 f89c bl 80140e8 8001fb0: 4603 mov r3, r0 8001fb2: 4a2f ldr r2, [pc, #188] @ (8002070 ) 8001fb4: 6013 str r3, [r2, #0] adc3MeasTaskHandle = osThreadNew (ADC3MeasTask, NULL, &osThreadAttradc3MeasTask); 8001fb6: f107 034c add.w r3, r7, #76 @ 0x4c 8001fba: 461a mov r2, r3 8001fbc: 2100 movs r1, #0 8001fbe: 482d ldr r0, [pc, #180] @ (8002074 ) 8001fc0: f012 f892 bl 80140e8 8001fc4: 4603 mov r3, r0 8001fc6: 4a2c ldr r2, [pc, #176] @ (8002078 ) 8001fc8: 6013 str r3, [r2, #0] limiterSwitchDataQueue = osMessageQueueNew (8, sizeof (LimiterSwitchData), NULL); 8001fca: 2200 movs r2, #0 8001fcc: 2104 movs r1, #4 8001fce: 2008 movs r0, #8 8001fd0: f012 fb3d bl 801464e 8001fd4: 4603 mov r3, r0 8001fd6: 4a29 ldr r2, [pc, #164] @ (800207c ) 8001fd8: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttradc1LimiterSwitchTask = { 0 }; 8001fda: f107 0328 add.w r3, r7, #40 @ 0x28 8001fde: 2224 movs r2, #36 @ 0x24 8001fe0: 2100 movs r1, #0 8001fe2: 4618 mov r0, r3 8001fe4: f016 f9d8 bl 8018398 osThreadAttradc1LimiterSwitchTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001fe8: f44f 6380 mov.w r3, #1024 @ 0x400 8001fec: 63fb str r3, [r7, #60] @ 0x3c osThreadAttradc1LimiterSwitchTask.priority = (osPriority_t)osPriorityNormal; 8001fee: 2318 movs r3, #24 8001ff0: 643b str r3, [r7, #64] @ 0x40 limiterSwitchTaskHandle = osThreadNew (LimiterSwitchTask, NULL, &osThreadAttradc1LimiterSwitchTask); 8001ff2: f107 0328 add.w r3, r7, #40 @ 0x28 8001ff6: 461a mov r2, r3 8001ff8: 2100 movs r1, #0 8001ffa: 4821 ldr r0, [pc, #132] @ (8002080 ) 8001ffc: f012 f874 bl 80140e8 8002000: 4603 mov r3, r0 8002002: 4a20 ldr r2, [pc, #128] @ (8002084 ) 8002004: 6013 str r3, [r2, #0] encoderDataQueue = osMessageQueueNew (16, sizeof (EncoderData), NULL); 8002006: 2200 movs r2, #0 8002008: 2102 movs r1, #2 800200a: 2010 movs r0, #16 800200c: f012 fb1f bl 801464e 8002010: 4603 mov r3, r0 8002012: 4a1d ldr r2, [pc, #116] @ (8002088 ) 8002014: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttrEncoderTask = { 0 }; 8002016: 1d3b adds r3, r7, #4 8002018: 2224 movs r2, #36 @ 0x24 800201a: 2100 movs r1, #0 800201c: 4618 mov r0, r3 800201e: f016 f9bb bl 8018398 osThreadAttrEncoderTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8002022: f44f 6380 mov.w r3, #1024 @ 0x400 8002026: 61bb str r3, [r7, #24] osThreadAttrEncoderTask.priority = (osPriority_t)osPriorityNormal; 8002028: 2318 movs r3, #24 800202a: 61fb str r3, [r7, #28] encoderTaskHandle = osThreadNew (EncoderTask, encoderDataQueue, &osThreadAttrEncoderTask); 800202c: 4b16 ldr r3, [pc, #88] @ (8002088 ) 800202e: 681b ldr r3, [r3, #0] 8002030: 1d3a adds r2, r7, #4 8002032: 4619 mov r1, r3 8002034: 4815 ldr r0, [pc, #84] @ (800208c ) 8002036: f012 f857 bl 80140e8 800203a: 4603 mov r3, r0 800203c: 4a14 ldr r2, [pc, #80] @ (8002090 ) 800203e: 6013 str r3, [r2, #0] } 8002040: bf00 nop 8002042: 37b8 adds r7, #184 @ 0xb8 8002044: 46bd mov sp, r7 8002046: bd80 pop {r7, pc} 8002048: 24000814 .word 0x24000814 800204c: 24000818 .word 0x24000818 8002050: 2400081c .word 0x2400081c 8002054: 24000820 .word 0x24000820 8002058: 24000800 .word 0x24000800 800205c: 24000804 .word 0x24000804 8002060: 24000808 .word 0x24000808 8002064: 08002099 .word 0x08002099 8002068: 240007ec .word 0x240007ec 800206c: 08002421 .word 0x08002421 8002070: 240007f0 .word 0x240007f0 8002074: 08002729 .word 0x08002729 8002078: 240007f4 .word 0x240007f4 800207c: 2400080c .word 0x2400080c 8002080: 08002aa5 .word 0x08002aa5 8002084: 240007f8 .word 0x240007f8 8002088: 24000810 .word 0x24000810 800208c: 08002d81 .word 0x08002d81 8002090: 240007fc .word 0x240007fc 8002094: 00000000 .word 0x00000000 08002098 : void ADC1MeasTask (void* arg) { 8002098: b580 push {r7, lr} 800209a: b09a sub sp, #104 @ 0x68 800209c: af00 add r7, sp, #0 800209e: 6078 str r0, [r7, #4] float circBuffer[VOLTAGES_COUNT][CIRC_BUFF_LEN] = { 0 }; 80020a0: f107 032c add.w r3, r7, #44 @ 0x2c 80020a4: 2228 movs r2, #40 @ 0x28 80020a6: 2100 movs r1, #0 80020a8: 4618 mov r0, r3 80020aa: f016 f975 bl 8018398 float rms[VOLTAGES_COUNT] = { 0 }; 80020ae: f04f 0300 mov.w r3, #0 80020b2: 62bb str r3, [r7, #40] @ 0x28 ; ADC1_Data adcData = { 0 }; 80020b4: f107 0308 add.w r3, r7, #8 80020b8: 2220 movs r2, #32 80020ba: 2100 movs r1, #0 80020bc: 4618 mov r0, r3 80020be: f016 f96b bl 8018398 uint32_t circBuffPos = 0; 80020c2: 2300 movs r3, #0 80020c4: 667b str r3, [r7, #100] @ 0x64 float gainCorrection = 1.0; 80020c6: f04f 537e mov.w r3, #1065353216 @ 0x3f800000 80020ca: 663b str r3, [r7, #96] @ 0x60 while (pdTRUE) { osMessageQueueGet (adc1MeasDataQueue, &adcData, 0, osWaitForever); 80020cc: 4bc8 ldr r3, [pc, #800] @ (80023f0 ) 80020ce: 6818 ldr r0, [r3, #0] 80020d0: f107 0108 add.w r1, r7, #8 80020d4: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80020d8: 2200 movs r2, #0 80020da: f012 fb8b bl 80147f4 #ifdef GAIN_AUTO_CORRECTION if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 80020de: 4bc5 ldr r3, [pc, #788] @ (80023f4 ) 80020e0: 681b ldr r3, [r3, #0] 80020e2: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80020e6: 4618 mov r0, r3 80020e8: f012 fa29 bl 801453e 80020ec: 4603 mov r3, r0 80020ee: 2b00 cmp r3, #0 80020f0: d10c bne.n 800210c gainCorrection = (float)vRefmV; 80020f2: 4bc1 ldr r3, [pc, #772] @ (80023f8 ) 80020f4: 681b ldr r3, [r3, #0] 80020f6: ee07 3a90 vmov s15, r3 80020fa: eef8 7a67 vcvt.f32.u32 s15, s15 80020fe: edc7 7a18 vstr s15, [r7, #96] @ 0x60 osMutexRelease (vRefmVMutex); 8002102: 4bbc ldr r3, [pc, #752] @ (80023f4 ) 8002104: 681b ldr r3, [r3, #0] 8002106: 4618 mov r0, r3 8002108: f012 fa64 bl 80145d4 } gainCorrection = gainCorrection / EXT_VREF_mV; 800210c: ed97 7a18 vldr s14, [r7, #96] @ 0x60 8002110: eddf 6aba vldr s13, [pc, #744] @ 80023fc 8002114: eec7 7a26 vdiv.f32 s15, s14, s13 8002118: edc7 7a18 vstr s15, [r7, #96] @ 0x60 #endif for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) { 800211c: 2300 movs r3, #0 800211e: f887 305f strb.w r3, [r7, #95] @ 0x5f 8002122: e0e7 b.n 80022f4 float val = adcData.adcDataBuffer[i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 8002124: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002128: 005b lsls r3, r3, #1 800212a: 3368 adds r3, #104 @ 0x68 800212c: 443b add r3, r7 800212e: f833 3c60 ldrh.w r3, [r3, #-96] 8002132: ee07 3a90 vmov s15, r3 8002136: eeb8 7be7 vcvt.f64.s32 d7, s15 800213a: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 800213e: ee27 6b06 vmul.f64 d6, d7, d6 8002142: ed9f 5ba5 vldr d5, [pc, #660] @ 80023d8 8002146: ee86 7b05 vdiv.f64 d7, d6, d5 800214a: ed9f 6ba5 vldr d6, [pc, #660] @ 80023e0 800214e: ee27 6b06 vmul.f64 d6, d7, d6 8002152: edd7 7a18 vldr s15, [r7, #96] @ 0x60 8002156: eeb7 7ae7 vcvt.f64.f32 d7, s15 800215a: ee26 6b07 vmul.f64 d6, d6, d7 800215e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002162: 4aa7 ldr r2, [pc, #668] @ (8002400 ) 8002164: 00db lsls r3, r3, #3 8002166: 4413 add r3, r2 8002168: edd3 7a00 vldr s15, [r3] 800216c: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002170: ee26 6b07 vmul.f64 d6, d6, d7 8002174: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002178: 4aa1 ldr r2, [pc, #644] @ (8002400 ) 800217a: 00db lsls r3, r3, #3 800217c: 4413 add r3, r2 800217e: 3304 adds r3, #4 8002180: edd3 7a00 vldr s15, [r3] 8002184: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002188: ee36 7b07 vadd.f64 d7, d6, d7 800218c: eef7 7bc7 vcvt.f32.f64 s15, d7 8002190: edc7 7a15 vstr s15, [r7, #84] @ 0x54 circBuffer[i][circBuffPos] = val; 8002194: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 8002198: 4613 mov r3, r2 800219a: 009b lsls r3, r3, #2 800219c: 4413 add r3, r2 800219e: 005b lsls r3, r3, #1 80021a0: 6e7a ldr r2, [r7, #100] @ 0x64 80021a2: 4413 add r3, r2 80021a4: 009b lsls r3, r3, #2 80021a6: 3368 adds r3, #104 @ 0x68 80021a8: 443b add r3, r7 80021aa: 3b3c subs r3, #60 @ 0x3c 80021ac: 6d7a ldr r2, [r7, #84] @ 0x54 80021ae: 601a str r2, [r3, #0] rms[i] = 0.0; 80021b0: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80021b4: 009b lsls r3, r3, #2 80021b6: 3368 adds r3, #104 @ 0x68 80021b8: 443b add r3, r7 80021ba: 3b40 subs r3, #64 @ 0x40 80021bc: f04f 0200 mov.w r2, #0 80021c0: 601a str r2, [r3, #0] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 80021c2: 2300 movs r3, #0 80021c4: f887 305e strb.w r3, [r7, #94] @ 0x5e 80021c8: e025 b.n 8002216 rms[i] += circBuffer[i][c]; 80021ca: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80021ce: 009b lsls r3, r3, #2 80021d0: 3368 adds r3, #104 @ 0x68 80021d2: 443b add r3, r7 80021d4: 3b40 subs r3, #64 @ 0x40 80021d6: ed93 7a00 vldr s14, [r3] 80021da: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 80021de: f897 105e ldrb.w r1, [r7, #94] @ 0x5e 80021e2: 4613 mov r3, r2 80021e4: 009b lsls r3, r3, #2 80021e6: 4413 add r3, r2 80021e8: 005b lsls r3, r3, #1 80021ea: 440b add r3, r1 80021ec: 009b lsls r3, r3, #2 80021ee: 3368 adds r3, #104 @ 0x68 80021f0: 443b add r3, r7 80021f2: 3b3c subs r3, #60 @ 0x3c 80021f4: edd3 7a00 vldr s15, [r3] 80021f8: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80021fc: ee77 7a27 vadd.f32 s15, s14, s15 8002200: 009b lsls r3, r3, #2 8002202: 3368 adds r3, #104 @ 0x68 8002204: 443b add r3, r7 8002206: 3b40 subs r3, #64 @ 0x40 8002208: edc3 7a00 vstr s15, [r3] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 800220c: f897 305e ldrb.w r3, [r7, #94] @ 0x5e 8002210: 3301 adds r3, #1 8002212: f887 305e strb.w r3, [r7, #94] @ 0x5e 8002216: f897 305e ldrb.w r3, [r7, #94] @ 0x5e 800221a: 2b09 cmp r3, #9 800221c: d9d5 bls.n 80021ca } rms[i] = rms[i] / CIRC_BUFF_LEN; 800221e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002222: 009b lsls r3, r3, #2 8002224: 3368 adds r3, #104 @ 0x68 8002226: 443b add r3, r7 8002228: 3b40 subs r3, #64 @ 0x40 800222a: ed93 7a00 vldr s14, [r3] 800222e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002232: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002236: eec7 7a26 vdiv.f32 s15, s14, s13 800223a: 009b lsls r3, r3, #2 800223c: 3368 adds r3, #104 @ 0x68 800223e: 443b add r3, r7 8002240: 3b40 subs r3, #64 @ 0x40 8002242: edc3 7a00 vstr s15, [r3] if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8002246: 4b6f ldr r3, [pc, #444] @ (8002404 ) 8002248: 681b ldr r3, [r3, #0] 800224a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800224e: 4618 mov r0, r3 8002250: f012 f975 bl 801453e 8002254: 4603 mov r3, r0 8002256: 2b00 cmp r3, #0 8002258: d147 bne.n 80022ea if (fabs (resMeasurements.voltagePeak[i]) < fabs (val)) { 800225a: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800225e: 4a6a ldr r2, [pc, #424] @ (8002408 ) 8002260: 3302 adds r3, #2 8002262: 009b lsls r3, r3, #2 8002264: 4413 add r3, r2 8002266: 3304 adds r3, #4 8002268: edd3 7a00 vldr s15, [r3] 800226c: eeb0 7ae7 vabs.f32 s14, s15 8002270: edd7 7a15 vldr s15, [r7, #84] @ 0x54 8002274: eef0 7ae7 vabs.f32 s15, s15 8002278: eeb4 7ae7 vcmpe.f32 s14, s15 800227c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002280: d508 bpl.n 8002294 resMeasurements.voltagePeak[i] = val; 8002282: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002286: 4a60 ldr r2, [pc, #384] @ (8002408 ) 8002288: 3302 adds r3, #2 800228a: 009b lsls r3, r3, #2 800228c: 4413 add r3, r2 800228e: 3304 adds r3, #4 8002290: 6d7a ldr r2, [r7, #84] @ 0x54 8002292: 601a str r2, [r3, #0] } resMeasurements.voltageRMS[i] = rms[i]; 8002294: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 8002298: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800229c: 0092 lsls r2, r2, #2 800229e: 3268 adds r2, #104 @ 0x68 80022a0: 443a add r2, r7 80022a2: 3a40 subs r2, #64 @ 0x40 80022a4: 6812 ldr r2, [r2, #0] 80022a6: 4958 ldr r1, [pc, #352] @ (8002408 ) 80022a8: 009b lsls r3, r3, #2 80022aa: 440b add r3, r1 80022ac: 601a str r2, [r3, #0] resMeasurements.power[i] = resMeasurements.voltageRMS[i] * resMeasurements.currentRMS[i]; 80022ae: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022b2: 4a55 ldr r2, [pc, #340] @ (8002408 ) 80022b4: 009b lsls r3, r3, #2 80022b6: 4413 add r3, r2 80022b8: ed93 7a00 vldr s14, [r3] 80022bc: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022c0: 4a51 ldr r2, [pc, #324] @ (8002408 ) 80022c2: 3306 adds r3, #6 80022c4: 009b lsls r3, r3, #2 80022c6: 4413 add r3, r2 80022c8: edd3 7a00 vldr s15, [r3] 80022cc: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022d0: ee67 7a27 vmul.f32 s15, s14, s15 80022d4: 4a4c ldr r2, [pc, #304] @ (8002408 ) 80022d6: 330c adds r3, #12 80022d8: 009b lsls r3, r3, #2 80022da: 4413 add r3, r2 80022dc: edc3 7a00 vstr s15, [r3] osMutexRelease (resMeasurementsMutex); 80022e0: 4b48 ldr r3, [pc, #288] @ (8002404 ) 80022e2: 681b ldr r3, [r3, #0] 80022e4: 4618 mov r0, r3 80022e6: f012 f975 bl 80145d4 for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) { 80022ea: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022ee: 3301 adds r3, #1 80022f0: f887 305f strb.w r3, [r7, #95] @ 0x5f 80022f4: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022f8: 2b00 cmp r3, #0 80022fa: f43f af13 beq.w 8002124 } } ++circBuffPos; 80022fe: 6e7b ldr r3, [r7, #100] @ 0x64 8002300: 3301 adds r3, #1 8002302: 667b str r3, [r7, #100] @ 0x64 circBuffPos = circBuffPos % CIRC_BUFF_LEN; 8002304: 6e7a ldr r2, [r7, #100] @ 0x64 8002306: 4b41 ldr r3, [pc, #260] @ (800240c ) 8002308: fba3 1302 umull r1, r3, r3, r2 800230c: 08d9 lsrs r1, r3, #3 800230e: 460b mov r3, r1 8002310: 009b lsls r3, r3, #2 8002312: 440b add r3, r1 8002314: 005b lsls r3, r3, #1 8002316: 1ad3 subs r3, r2, r3 8002318: 667b str r3, [r7, #100] @ 0x64 if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) { 800231a: 4b3d ldr r3, [pc, #244] @ (8002410 ) 800231c: 681b ldr r3, [r3, #0] 800231e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002322: 4618 mov r0, r3 8002324: f012 f90b bl 801453e 8002328: 4603 mov r3, r0 800232a: 2b00 cmp r3, #0 800232c: d124 bne.n 8002378 uint8_t refIdx = 0; 800232e: 2300 movs r3, #0 8002330: f887 305d strb.w r3, [r7, #93] @ 0x5d for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) { 8002334: 2303 movs r3, #3 8002336: f887 305c strb.w r3, [r7, #92] @ 0x5c 800233a: e014 b.n 8002366 ILxRef[refIdx++] = adcData.adcDataBuffer[i]; 800233c: f897 205c ldrb.w r2, [r7, #92] @ 0x5c 8002340: f897 305d ldrb.w r3, [r7, #93] @ 0x5d 8002344: 1c59 adds r1, r3, #1 8002346: f887 105d strb.w r1, [r7, #93] @ 0x5d 800234a: 4619 mov r1, r3 800234c: 0053 lsls r3, r2, #1 800234e: 3368 adds r3, #104 @ 0x68 8002350: 443b add r3, r7 8002352: f833 2c60 ldrh.w r2, [r3, #-96] 8002356: 4b2f ldr r3, [pc, #188] @ (8002414 ) 8002358: f823 2011 strh.w r2, [r3, r1, lsl #1] for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) { 800235c: f897 305c ldrb.w r3, [r7, #92] @ 0x5c 8002360: 3301 adds r3, #1 8002362: f887 305c strb.w r3, [r7, #92] @ 0x5c 8002366: f897 305c ldrb.w r3, [r7, #92] @ 0x5c 800236a: 2b05 cmp r3, #5 800236c: d9e6 bls.n 800233c } osMutexRelease (ILxRefMutex); 800236e: 4b28 ldr r3, [pc, #160] @ (8002410 ) 8002370: 681b ldr r3, [r3, #0] 8002372: 4618 mov r0, r3 8002374: f012 f92e bl 80145d4 } float fanFBVoltage = adcData.adcDataBuffer[FanFB] * deltaADC * -4.35 + 12; 8002378: 8abb ldrh r3, [r7, #20] 800237a: ee07 3a90 vmov s15, r3 800237e: eeb8 7be7 vcvt.f64.s32 d7, s15 8002382: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002386: ee27 6b06 vmul.f64 d6, d7, d6 800238a: ed9f 5b13 vldr d5, [pc, #76] @ 80023d8 800238e: ee86 7b05 vdiv.f64 d7, d6, d5 8002392: ed9f 6b15 vldr d6, [pc, #84] @ 80023e8 8002396: ee27 7b06 vmul.f64 d7, d7, d6 800239a: eeb2 6b08 vmov.f64 d6, #40 @ 0x41400000 12.0 800239e: ee37 7b06 vadd.f64 d7, d7, d6 80023a2: eef7 7bc7 vcvt.f32.f64 s15, d7 80023a6: edc7 7a16 vstr s15, [r7, #88] @ 0x58 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80023aa: 4b1b ldr r3, [pc, #108] @ (8002418 ) 80023ac: 681b ldr r3, [r3, #0] 80023ae: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80023b2: 4618 mov r0, r3 80023b4: f012 f8c3 bl 801453e 80023b8: 4603 mov r3, r0 80023ba: 2b00 cmp r3, #0 80023bc: f47f ae86 bne.w 80020cc sensorsInfo.fanVoltage = fanFBVoltage; 80023c0: 4a16 ldr r2, [pc, #88] @ (800241c ) 80023c2: 6dbb ldr r3, [r7, #88] @ 0x58 80023c4: 6093 str r3, [r2, #8] osMutexRelease (sensorsInfoMutex); 80023c6: 4b14 ldr r3, [pc, #80] @ (8002418 ) 80023c8: 681b ldr r3, [r3, #0] 80023ca: 4618 mov r0, r3 80023cc: f012 f902 bl 80145d4 while (pdTRUE) { 80023d0: e67c b.n 80020cc 80023d2: bf00 nop 80023d4: f3af 8000 nop.w 80023d8: 00000000 .word 0x00000000 80023dc: 40efffe0 .word 0x40efffe0 80023e0: f5c28f5c .word 0xf5c28f5c 80023e4: 401e5c28 .word 0x401e5c28 80023e8: 66666666 .word 0x66666666 80023ec: c0116666 .word 0xc0116666 80023f0: 24000800 .word 0x24000800 80023f4: 24000814 .word 0x24000814 80023f8: 24000030 .word 0x24000030 80023fc: 453b8000 .word 0x453b8000 8002400: 24000000 .word 0x24000000 8002404: 24000818 .word 0x24000818 8002408: 24000824 .word 0x24000824 800240c: cccccccd .word 0xcccccccd 8002410: 24000820 .word 0x24000820 8002414: 2400089c .word 0x2400089c 8002418: 2400081c .word 0x2400081c 800241c: 24000860 .word 0x24000860 08002420 : } } } void ADC2MeasTask (void* arg) { 8002420: b580 push {r7, lr} 8002422: b09c sub sp, #112 @ 0x70 8002424: af00 add r7, sp, #0 8002426: 6078 str r0, [r7, #4] float circBuffer[CURRENTS_COUNT][CIRC_BUFF_LEN] = { 0 }; 8002428: f107 0334 add.w r3, r7, #52 @ 0x34 800242c: 2228 movs r2, #40 @ 0x28 800242e: 2100 movs r1, #0 8002430: 4618 mov r0, r3 8002432: f015 ffb1 bl 8018398 float rms[CURRENTS_COUNT] = { 0 }; 8002436: f04f 0300 mov.w r3, #0 800243a: 633b str r3, [r7, #48] @ 0x30 ADC2_Data adcData = { 0 }; 800243c: f107 0310 add.w r3, r7, #16 8002440: 2220 movs r2, #32 8002442: 2100 movs r1, #0 8002444: 4618 mov r0, r3 8002446: f015 ffa7 bl 8018398 uint32_t circBuffPos = 0; 800244a: 2300 movs r3, #0 800244c: 66fb str r3, [r7, #108] @ 0x6c float gainCorrection = 1.0; 800244e: f04f 537e mov.w r3, #1065353216 @ 0x3f800000 8002452: 66bb str r3, [r7, #104] @ 0x68 while (pdTRUE) { osMessageQueueGet (adc2MeasDataQueue, &adcData, 0, osWaitForever); 8002454: 4baa ldr r3, [pc, #680] @ (8002700 ) 8002456: 6818 ldr r0, [r3, #0] 8002458: f107 0110 add.w r1, r7, #16 800245c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002460: 2200 movs r2, #0 8002462: f012 f9c7 bl 80147f4 if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 8002466: 4ba7 ldr r3, [pc, #668] @ (8002704 ) 8002468: 681b ldr r3, [r3, #0] 800246a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800246e: 4618 mov r0, r3 8002470: f012 f865 bl 801453e 8002474: 4603 mov r3, r0 8002476: 2b00 cmp r3, #0 8002478: d10c bne.n 8002494 gainCorrection = (float)vRefmV; 800247a: 4ba3 ldr r3, [pc, #652] @ (8002708 ) 800247c: 681b ldr r3, [r3, #0] 800247e: ee07 3a90 vmov s15, r3 8002482: eef8 7a67 vcvt.f32.u32 s15, s15 8002486: edc7 7a1a vstr s15, [r7, #104] @ 0x68 osMutexRelease (vRefmVMutex); 800248a: 4b9e ldr r3, [pc, #632] @ (8002704 ) 800248c: 681b ldr r3, [r3, #0] 800248e: 4618 mov r0, r3 8002490: f012 f8a0 bl 80145d4 } gainCorrection = gainCorrection / EXT_VREF_mV; 8002494: ed97 7a1a vldr s14, [r7, #104] @ 0x68 8002498: eddf 6a9c vldr s13, [pc, #624] @ 800270c 800249c: eec7 7a26 vdiv.f32 s15, s14, s13 80024a0: edc7 7a1a vstr s15, [r7, #104] @ 0x68 float ref[CURRENTS_COUNT] = { 0 }; 80024a4: f04f 0300 mov.w r3, #0 80024a8: 60fb str r3, [r7, #12] if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) { 80024aa: 4b99 ldr r3, [pc, #612] @ (8002710 ) 80024ac: 681b ldr r3, [r3, #0] 80024ae: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80024b2: 4618 mov r0, r3 80024b4: f012 f843 bl 801453e 80024b8: 4603 mov r3, r0 80024ba: 2b00 cmp r3, #0 80024bc: d122 bne.n 8002504 for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 80024be: 2300 movs r3, #0 80024c0: f887 3067 strb.w r3, [r7, #103] @ 0x67 80024c4: e015 b.n 80024f2 ref[i] = (float)ILxRef[i]; 80024c6: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80024ca: 4a92 ldr r2, [pc, #584] @ (8002714 ) 80024cc: f832 2013 ldrh.w r2, [r2, r3, lsl #1] 80024d0: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80024d4: ee07 2a90 vmov s15, r2 80024d8: eef8 7a67 vcvt.f32.u32 s15, s15 80024dc: 009b lsls r3, r3, #2 80024de: 3370 adds r3, #112 @ 0x70 80024e0: 443b add r3, r7 80024e2: 3b64 subs r3, #100 @ 0x64 80024e4: edc3 7a00 vstr s15, [r3] for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 80024e8: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80024ec: 3301 adds r3, #1 80024ee: f887 3067 strb.w r3, [r7, #103] @ 0x67 80024f2: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80024f6: 2b00 cmp r3, #0 80024f8: d0e5 beq.n 80024c6 } osMutexRelease (ILxRefMutex); 80024fa: 4b85 ldr r3, [pc, #532] @ (8002710 ) 80024fc: 681b ldr r3, [r3, #0] 80024fe: 4618 mov r0, r3 8002500: f012 f868 bl 80145d4 } for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 8002504: 2300 movs r3, #0 8002506: f887 3066 strb.w r3, [r7, #102] @ 0x66 800250a: e0db b.n 80026c4 float adcVal = (float)adcData.adcDataBuffer[i]; 800250c: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002510: 005b lsls r3, r3, #1 8002512: 3370 adds r3, #112 @ 0x70 8002514: 443b add r3, r7 8002516: f833 3c60 ldrh.w r3, [r3, #-96] 800251a: ee07 3a90 vmov s15, r3 800251e: eef8 7a67 vcvt.f32.u32 s15, s15 8002522: edc7 7a18 vstr s15, [r7, #96] @ 0x60 float val = (adcVal - ref[i]) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset; 8002526: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800252a: 009b lsls r3, r3, #2 800252c: 3370 adds r3, #112 @ 0x70 800252e: 443b add r3, r7 8002530: 3b64 subs r3, #100 @ 0x64 8002532: edd3 7a00 vldr s15, [r3] 8002536: ed97 7a18 vldr s14, [r7, #96] @ 0x60 800253a: ee77 7a67 vsub.f32 s15, s14, s15 800253e: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002542: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002546: ee27 6b06 vmul.f64 d6, d7, d6 800254a: ed9f 5b69 vldr d5, [pc, #420] @ 80026f0 800254e: ee86 7b05 vdiv.f64 d7, d6, d5 8002552: ed9f 6b69 vldr d6, [pc, #420] @ 80026f8 8002556: ee27 6b06 vmul.f64 d6, d7, d6 800255a: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800255e: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002562: ee26 6b07 vmul.f64 d6, d6, d7 8002566: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800256a: 4a6b ldr r2, [pc, #428] @ (8002718 ) 800256c: 00db lsls r3, r3, #3 800256e: 4413 add r3, r2 8002570: edd3 7a00 vldr s15, [r3] 8002574: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002578: ee26 6b07 vmul.f64 d6, d6, d7 800257c: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002580: 4a65 ldr r2, [pc, #404] @ (8002718 ) 8002582: 00db lsls r3, r3, #3 8002584: 4413 add r3, r2 8002586: 3304 adds r3, #4 8002588: edd3 7a00 vldr s15, [r3] 800258c: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002590: ee36 7b07 vadd.f64 d7, d6, d7 8002594: eef7 7bc7 vcvt.f32.f64 s15, d7 8002598: edc7 7a17 vstr s15, [r7, #92] @ 0x5c circBuffer[i][circBuffPos] = val; 800259c: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 80025a0: 4613 mov r3, r2 80025a2: 009b lsls r3, r3, #2 80025a4: 4413 add r3, r2 80025a6: 005b lsls r3, r3, #1 80025a8: 6efa ldr r2, [r7, #108] @ 0x6c 80025aa: 4413 add r3, r2 80025ac: 009b lsls r3, r3, #2 80025ae: 3370 adds r3, #112 @ 0x70 80025b0: 443b add r3, r7 80025b2: 3b3c subs r3, #60 @ 0x3c 80025b4: 6dfa ldr r2, [r7, #92] @ 0x5c 80025b6: 601a str r2, [r3, #0] rms[i] = 0.0; 80025b8: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80025bc: 009b lsls r3, r3, #2 80025be: 3370 adds r3, #112 @ 0x70 80025c0: 443b add r3, r7 80025c2: 3b40 subs r3, #64 @ 0x40 80025c4: f04f 0200 mov.w r2, #0 80025c8: 601a str r2, [r3, #0] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 80025ca: 2300 movs r3, #0 80025cc: f887 3065 strb.w r3, [r7, #101] @ 0x65 80025d0: e025 b.n 800261e rms[i] += circBuffer[i][c]; 80025d2: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80025d6: 009b lsls r3, r3, #2 80025d8: 3370 adds r3, #112 @ 0x70 80025da: 443b add r3, r7 80025dc: 3b40 subs r3, #64 @ 0x40 80025de: ed93 7a00 vldr s14, [r3] 80025e2: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 80025e6: f897 1065 ldrb.w r1, [r7, #101] @ 0x65 80025ea: 4613 mov r3, r2 80025ec: 009b lsls r3, r3, #2 80025ee: 4413 add r3, r2 80025f0: 005b lsls r3, r3, #1 80025f2: 440b add r3, r1 80025f4: 009b lsls r3, r3, #2 80025f6: 3370 adds r3, #112 @ 0x70 80025f8: 443b add r3, r7 80025fa: 3b3c subs r3, #60 @ 0x3c 80025fc: edd3 7a00 vldr s15, [r3] 8002600: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002604: ee77 7a27 vadd.f32 s15, s14, s15 8002608: 009b lsls r3, r3, #2 800260a: 3370 adds r3, #112 @ 0x70 800260c: 443b add r3, r7 800260e: 3b40 subs r3, #64 @ 0x40 8002610: edc3 7a00 vstr s15, [r3] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 8002614: f897 3065 ldrb.w r3, [r7, #101] @ 0x65 8002618: 3301 adds r3, #1 800261a: f887 3065 strb.w r3, [r7, #101] @ 0x65 800261e: f897 3065 ldrb.w r3, [r7, #101] @ 0x65 8002622: 2b09 cmp r3, #9 8002624: d9d5 bls.n 80025d2 } rms[i] = rms[i] / CIRC_BUFF_LEN; 8002626: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800262a: 009b lsls r3, r3, #2 800262c: 3370 adds r3, #112 @ 0x70 800262e: 443b add r3, r7 8002630: 3b40 subs r3, #64 @ 0x40 8002632: ed93 7a00 vldr s14, [r3] 8002636: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800263a: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 800263e: eec7 7a26 vdiv.f32 s15, s14, s13 8002642: 009b lsls r3, r3, #2 8002644: 3370 adds r3, #112 @ 0x70 8002646: 443b add r3, r7 8002648: 3b40 subs r3, #64 @ 0x40 800264a: edc3 7a00 vstr s15, [r3] if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 800264e: 4b33 ldr r3, [pc, #204] @ (800271c ) 8002650: 681b ldr r3, [r3, #0] 8002652: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002656: 4618 mov r0, r3 8002658: f011 ff71 bl 801453e 800265c: 4603 mov r3, r0 800265e: 2b00 cmp r3, #0 8002660: d12b bne.n 80026ba if (resMeasurements.currentPeak[i] < val) { 8002662: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002666: 4a2e ldr r2, [pc, #184] @ (8002720 ) 8002668: 3308 adds r3, #8 800266a: 009b lsls r3, r3, #2 800266c: 4413 add r3, r2 800266e: 3304 adds r3, #4 8002670: edd3 7a00 vldr s15, [r3] 8002674: ed97 7a17 vldr s14, [r7, #92] @ 0x5c 8002678: eeb4 7ae7 vcmpe.f32 s14, s15 800267c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002680: dd08 ble.n 8002694 resMeasurements.currentPeak[i] = val; 8002682: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002686: 4a26 ldr r2, [pc, #152] @ (8002720 ) 8002688: 3308 adds r3, #8 800268a: 009b lsls r3, r3, #2 800268c: 4413 add r3, r2 800268e: 3304 adds r3, #4 8002690: 6dfa ldr r2, [r7, #92] @ 0x5c 8002692: 601a str r2, [r3, #0] } resMeasurements.currentRMS[i] = rms[i]; 8002694: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 8002698: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800269c: 0092 lsls r2, r2, #2 800269e: 3270 adds r2, #112 @ 0x70 80026a0: 443a add r2, r7 80026a2: 3a40 subs r2, #64 @ 0x40 80026a4: 6812 ldr r2, [r2, #0] 80026a6: 491e ldr r1, [pc, #120] @ (8002720 ) 80026a8: 3306 adds r3, #6 80026aa: 009b lsls r3, r3, #2 80026ac: 440b add r3, r1 80026ae: 601a str r2, [r3, #0] osMutexRelease (resMeasurementsMutex); 80026b0: 4b1a ldr r3, [pc, #104] @ (800271c ) 80026b2: 681b ldr r3, [r3, #0] 80026b4: 4618 mov r0, r3 80026b6: f011 ff8d bl 80145d4 for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 80026ba: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80026be: 3301 adds r3, #1 80026c0: f887 3066 strb.w r3, [r7, #102] @ 0x66 80026c4: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80026c8: 2b00 cmp r3, #0 80026ca: f43f af1f beq.w 800250c } } ++circBuffPos; 80026ce: 6efb ldr r3, [r7, #108] @ 0x6c 80026d0: 3301 adds r3, #1 80026d2: 66fb str r3, [r7, #108] @ 0x6c circBuffPos = circBuffPos % CIRC_BUFF_LEN; 80026d4: 6efa ldr r2, [r7, #108] @ 0x6c 80026d6: 4b13 ldr r3, [pc, #76] @ (8002724 ) 80026d8: fba3 1302 umull r1, r3, r3, r2 80026dc: 08d9 lsrs r1, r3, #3 80026de: 460b mov r3, r1 80026e0: 009b lsls r3, r3, #2 80026e2: 440b add r3, r1 80026e4: 005b lsls r3, r3, #1 80026e6: 1ad3 subs r3, r2, r3 80026e8: 66fb str r3, [r7, #108] @ 0x6c while (pdTRUE) { 80026ea: e6b3 b.n 8002454 80026ec: f3af 8000 nop.w 80026f0: 00000000 .word 0x00000000 80026f4: 40efffe0 .word 0x40efffe0 80026f8: 83e425af .word 0x83e425af 80026fc: 401e4d9e .word 0x401e4d9e 8002700: 24000804 .word 0x24000804 8002704: 24000814 .word 0x24000814 8002708: 24000030 .word 0x24000030 800270c: 453b8000 .word 0x453b8000 8002710: 24000820 .word 0x24000820 8002714: 2400089c .word 0x2400089c 8002718: 24000018 .word 0x24000018 800271c: 24000818 .word 0x24000818 8002720: 24000824 .word 0x24000824 8002724: cccccccd .word 0xcccccccd 08002728 : } } void ADC3MeasTask (void* arg) { 8002728: b580 push {r7, lr} 800272a: b0bc sub sp, #240 @ 0xf0 800272c: af00 add r7, sp, #0 800272e: 6078 str r0, [r7, #4] float motorXSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 8002730: f107 03a4 add.w r3, r7, #164 @ 0xa4 8002734: 2228 movs r2, #40 @ 0x28 8002736: 2100 movs r1, #0 8002738: 4618 mov r0, r3 800273a: f015 fe2d bl 8018398 float motorYSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 800273e: f107 037c add.w r3, r7, #124 @ 0x7c 8002742: 2228 movs r2, #40 @ 0x28 8002744: 2100 movs r1, #0 8002746: 4618 mov r0, r3 8002748: f015 fe26 bl 8018398 float pvT1CircBuffer[CIRC_BUFF_LEN] = { 0 }; 800274c: f107 0354 add.w r3, r7, #84 @ 0x54 8002750: 2228 movs r2, #40 @ 0x28 8002752: 2100 movs r1, #0 8002754: 4618 mov r0, r3 8002756: f015 fe1f bl 8018398 float pvT2CircBuffer[CIRC_BUFF_LEN] = { 0 }; 800275a: f107 032c add.w r3, r7, #44 @ 0x2c 800275e: 2228 movs r2, #40 @ 0x28 8002760: 2100 movs r1, #0 8002762: 4618 mov r0, r3 8002764: f015 fe18 bl 8018398 uint32_t circBuffPos = 0; 8002768: 2300 movs r3, #0 800276a: f8c7 30ec str.w r3, [r7, #236] @ 0xec ADC3_Data adcData = { 0 }; 800276e: f107 030c add.w r3, r7, #12 8002772: 2220 movs r2, #32 8002774: 2100 movs r1, #0 8002776: 4618 mov r0, r3 8002778: f015 fe0e bl 8018398 while (pdTRUE) { osMessageQueueGet (adc3MeasDataQueue, &adcData, 0, osWaitForever); 800277c: 4bc2 ldr r3, [pc, #776] @ (8002a88 ) 800277e: 6818 ldr r0, [r3, #0] 8002780: f107 010c add.w r1, r7, #12 8002784: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002788: 2200 movs r2, #0 800278a: f012 f833 bl 80147f4 uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B); 800278e: 4bbf ldr r3, [pc, #764] @ (8002a8c ) 8002790: 881b ldrh r3, [r3, #0] 8002792: 461a mov r2, r3 8002794: f640 43e4 movw r3, #3300 @ 0xce4 8002798: fb02 f303 mul.w r3, r2, r3 800279c: 8aba ldrh r2, [r7, #20] 800279e: fbb3 f3f2 udiv r3, r3, r2 80027a2: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 80027a6: 4bba ldr r3, [pc, #744] @ (8002a90 ) 80027a8: 681b ldr r3, [r3, #0] 80027aa: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80027ae: 4618 mov r0, r3 80027b0: f011 fec5 bl 801453e 80027b4: 4603 mov r3, r0 80027b6: 2b00 cmp r3, #0 80027b8: d108 bne.n 80027cc vRefmV = vRef; 80027ba: 4ab6 ldr r2, [pc, #728] @ (8002a94 ) 80027bc: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 80027c0: 6013 str r3, [r2, #0] osMutexRelease (vRefmVMutex); 80027c2: 4bb3 ldr r3, [pc, #716] @ (8002a90 ) 80027c4: 681b ldr r3, [r3, #0] 80027c6: 4618 mov r0, r3 80027c8: f011 ff04 bl 80145d4 } float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333; 80027cc: 8a3b ldrh r3, [r7, #16] 80027ce: ee07 3a90 vmov s15, r3 80027d2: eeb8 7be7 vcvt.f64.s32 d7, s15 80027d6: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80027da: ee27 6b06 vmul.f64 d6, d7, d6 80027de: ed9f 5ba2 vldr d5, [pc, #648] @ 8002a68 80027e2: ee86 7b05 vdiv.f64 d7, d6, d5 80027e6: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 80027ea: ee27 6b06 vmul.f64 d6, d7, d6 80027ee: ed9f 5ba0 vldr d5, [pc, #640] @ 8002a70 80027f2: ee86 7b05 vdiv.f64 d7, d6, d5 80027f6: eef7 7bc7 vcvt.f32.f64 s15, d7 80027fa: edc7 7a34 vstr s15, [r7, #208] @ 0xd0 float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333; 80027fe: 8a7b ldrh r3, [r7, #18] 8002800: ee07 3a90 vmov s15, r3 8002804: eeb8 7be7 vcvt.f64.s32 d7, s15 8002808: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 800280c: ee27 6b06 vmul.f64 d6, d7, d6 8002810: ed9f 5b95 vldr d5, [pc, #596] @ 8002a68 8002814: ee86 7b05 vdiv.f64 d7, d6, d5 8002818: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 800281c: ee27 6b06 vmul.f64 d6, d7, d6 8002820: ed9f 5b93 vldr d5, [pc, #588] @ 8002a70 8002824: ee86 7b05 vdiv.f64 d7, d6, d5 8002828: eef7 7bc7 vcvt.f32.f64 s15, d7 800282c: edc7 7a33 vstr s15, [r7, #204] @ 0xcc motorXSensCircBuffer[circBuffPos] = motorXCurrentSense; 8002830: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002834: 009b lsls r3, r3, #2 8002836: 33f0 adds r3, #240 @ 0xf0 8002838: 443b add r3, r7 800283a: 3b4c subs r3, #76 @ 0x4c 800283c: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8002840: 601a str r2, [r3, #0] motorYSensCircBuffer[circBuffPos] = motorYCurrentSense; 8002842: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002846: 009b lsls r3, r3, #2 8002848: 33f0 adds r3, #240 @ 0xf0 800284a: 443b add r3, r7 800284c: 3b74 subs r3, #116 @ 0x74 800284e: f8d7 20cc ldr.w r2, [r7, #204] @ 0xcc 8002852: 601a str r2, [r3, #0] pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63; 8002854: 89bb ldrh r3, [r7, #12] 8002856: ee07 3a90 vmov s15, r3 800285a: eeb8 7be7 vcvt.f64.s32 d7, s15 800285e: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002862: ee27 6b06 vmul.f64 d6, d7, d6 8002866: ed9f 5b80 vldr d5, [pc, #512] @ 8002a68 800286a: ee86 7b05 vdiv.f64 d7, d6, d5 800286e: ed9f 6b82 vldr d6, [pc, #520] @ 8002a78 8002872: ee27 7b06 vmul.f64 d7, d7, d6 8002876: ed9f 6b82 vldr d6, [pc, #520] @ 8002a80 800287a: ee37 7b46 vsub.f64 d7, d7, d6 800287e: eef7 7bc7 vcvt.f32.f64 s15, d7 8002882: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002886: 009b lsls r3, r3, #2 8002888: 33f0 adds r3, #240 @ 0xf0 800288a: 443b add r3, r7 800288c: 3b9c subs r3, #156 @ 0x9c 800288e: edc3 7a00 vstr s15, [r3] pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63; 8002892: 89fb ldrh r3, [r7, #14] 8002894: ee07 3a90 vmov s15, r3 8002898: eeb8 7be7 vcvt.f64.s32 d7, s15 800289c: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80028a0: ee27 6b06 vmul.f64 d6, d7, d6 80028a4: ed9f 5b70 vldr d5, [pc, #448] @ 8002a68 80028a8: ee86 7b05 vdiv.f64 d7, d6, d5 80028ac: ed9f 6b72 vldr d6, [pc, #456] @ 8002a78 80028b0: ee27 7b06 vmul.f64 d7, d7, d6 80028b4: ed9f 6b72 vldr d6, [pc, #456] @ 8002a80 80028b8: ee37 7b46 vsub.f64 d7, d7, d6 80028bc: eef7 7bc7 vcvt.f32.f64 s15, d7 80028c0: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 80028c4: 009b lsls r3, r3, #2 80028c6: 33f0 adds r3, #240 @ 0xf0 80028c8: 443b add r3, r7 80028ca: 3bc4 subs r3, #196 @ 0xc4 80028cc: edc3 7a00 vstr s15, [r3] float motorXAveCurrent = 0; 80028d0: f04f 0300 mov.w r3, #0 80028d4: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 float motorYAveCurrent = 0; 80028d8: f04f 0300 mov.w r3, #0 80028dc: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 float pvT1AveTemp = 0; 80028e0: f04f 0300 mov.w r3, #0 80028e4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 float pvT2AveTemp = 0; 80028e8: f04f 0300 mov.w r3, #0 80028ec: f8c7 30dc str.w r3, [r7, #220] @ 0xdc for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) { 80028f0: 2300 movs r3, #0 80028f2: f887 30db strb.w r3, [r7, #219] @ 0xdb 80028f6: e03c b.n 8002972 motorXAveCurrent += motorXSensCircBuffer[i]; 80028f8: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 80028fc: 009b lsls r3, r3, #2 80028fe: 33f0 adds r3, #240 @ 0xf0 8002900: 443b add r3, r7 8002902: 3b4c subs r3, #76 @ 0x4c 8002904: edd3 7a00 vldr s15, [r3] 8002908: ed97 7a3a vldr s14, [r7, #232] @ 0xe8 800290c: ee77 7a27 vadd.f32 s15, s14, s15 8002910: edc7 7a3a vstr s15, [r7, #232] @ 0xe8 motorYAveCurrent += motorYSensCircBuffer[i]; 8002914: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002918: 009b lsls r3, r3, #2 800291a: 33f0 adds r3, #240 @ 0xf0 800291c: 443b add r3, r7 800291e: 3b74 subs r3, #116 @ 0x74 8002920: edd3 7a00 vldr s15, [r3] 8002924: ed97 7a39 vldr s14, [r7, #228] @ 0xe4 8002928: ee77 7a27 vadd.f32 s15, s14, s15 800292c: edc7 7a39 vstr s15, [r7, #228] @ 0xe4 #ifdef PV_BOARD pvT1AveTemp += pvT1CircBuffer[i]; 8002930: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002934: 009b lsls r3, r3, #2 8002936: 33f0 adds r3, #240 @ 0xf0 8002938: 443b add r3, r7 800293a: 3b9c subs r3, #156 @ 0x9c 800293c: edd3 7a00 vldr s15, [r3] 8002940: ed97 7a38 vldr s14, [r7, #224] @ 0xe0 8002944: ee77 7a27 vadd.f32 s15, s14, s15 8002948: edc7 7a38 vstr s15, [r7, #224] @ 0xe0 pvT2AveTemp += pvT2CircBuffer[i]; 800294c: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002950: 009b lsls r3, r3, #2 8002952: 33f0 adds r3, #240 @ 0xf0 8002954: 443b add r3, r7 8002956: 3bc4 subs r3, #196 @ 0xc4 8002958: edd3 7a00 vldr s15, [r3] 800295c: ed97 7a37 vldr s14, [r7, #220] @ 0xdc 8002960: ee77 7a27 vadd.f32 s15, s14, s15 8002964: edc7 7a37 vstr s15, [r7, #220] @ 0xdc for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) { 8002968: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 800296c: 3301 adds r3, #1 800296e: f887 30db strb.w r3, [r7, #219] @ 0xdb 8002972: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002976: 2b09 cmp r3, #9 8002978: d9be bls.n 80028f8 #endif } motorXAveCurrent /= CIRC_BUFF_LEN; 800297a: ed97 7a3a vldr s14, [r7, #232] @ 0xe8 800297e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002982: eec7 7a26 vdiv.f32 s15, s14, s13 8002986: edc7 7a3a vstr s15, [r7, #232] @ 0xe8 motorYAveCurrent /= CIRC_BUFF_LEN; 800298a: ed97 7a39 vldr s14, [r7, #228] @ 0xe4 800298e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002992: eec7 7a26 vdiv.f32 s15, s14, s13 8002996: edc7 7a39 vstr s15, [r7, #228] @ 0xe4 pvT1AveTemp /= CIRC_BUFF_LEN; 800299a: ed97 7a38 vldr s14, [r7, #224] @ 0xe0 800299e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 80029a2: eec7 7a26 vdiv.f32 s15, s14, s13 80029a6: edc7 7a38 vstr s15, [r7, #224] @ 0xe0 pvT2AveTemp /= CIRC_BUFF_LEN; 80029aa: ed97 7a37 vldr s14, [r7, #220] @ 0xdc 80029ae: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 80029b2: eec7 7a26 vdiv.f32 s15, s14, s13 80029b6: edc7 7a37 vstr s15, [r7, #220] @ 0xdc if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80029ba: 4b37 ldr r3, [pc, #220] @ (8002a98 ) 80029bc: 681b ldr r3, [r3, #0] 80029be: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80029c2: 4618 mov r0, r3 80029c4: f011 fdbb bl 801453e 80029c8: 4603 mov r3, r0 80029ca: 2b00 cmp r3, #0 80029cc: d138 bne.n 8002a40 if (sensorsInfo.motorXStatus == 1) { 80029ce: 4b33 ldr r3, [pc, #204] @ (8002a9c ) 80029d0: 7d1b ldrb r3, [r3, #20] 80029d2: 2b01 cmp r3, #1 80029d4: d111 bne.n 80029fa sensorsInfo.motorXAveCurrent = motorXAveCurrent; 80029d6: 4a31 ldr r2, [pc, #196] @ (8002a9c ) 80029d8: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8 80029dc: 6193 str r3, [r2, #24] if (sensorsInfo.motorXPeakCurrent < motorXCurrentSense) { 80029de: 4b2f ldr r3, [pc, #188] @ (8002a9c ) 80029e0: edd3 7a08 vldr s15, [r3, #32] 80029e4: ed97 7a34 vldr s14, [r7, #208] @ 0xd0 80029e8: eeb4 7ae7 vcmpe.f32 s14, s15 80029ec: eef1 fa10 vmrs APSR_nzcv, fpscr 80029f0: dd03 ble.n 80029fa sensorsInfo.motorXPeakCurrent = motorXCurrentSense; 80029f2: 4a2a ldr r2, [pc, #168] @ (8002a9c ) 80029f4: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0 80029f8: 6213 str r3, [r2, #32] } } if (sensorsInfo.motorYStatus == 1) { 80029fa: 4b28 ldr r3, [pc, #160] @ (8002a9c ) 80029fc: 7d5b ldrb r3, [r3, #21] 80029fe: 2b01 cmp r3, #1 8002a00: d111 bne.n 8002a26 sensorsInfo.motorYAveCurrent = motorYAveCurrent; 8002a02: 4a26 ldr r2, [pc, #152] @ (8002a9c ) 8002a04: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8002a08: 61d3 str r3, [r2, #28] if (sensorsInfo.motorYPeakCurrent < motorYCurrentSense) { 8002a0a: 4b24 ldr r3, [pc, #144] @ (8002a9c ) 8002a0c: edd3 7a09 vldr s15, [r3, #36] @ 0x24 8002a10: ed97 7a33 vldr s14, [r7, #204] @ 0xcc 8002a14: eeb4 7ae7 vcmpe.f32 s14, s15 8002a18: eef1 fa10 vmrs APSR_nzcv, fpscr 8002a1c: dd03 ble.n 8002a26 sensorsInfo.motorYPeakCurrent = motorYCurrentSense; 8002a1e: 4a1f ldr r2, [pc, #124] @ (8002a9c ) 8002a20: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc 8002a24: 6253 str r3, [r2, #36] @ 0x24 } } sensorsInfo.pvTemperature[0] = pvT1AveTemp; 8002a26: 4a1d ldr r2, [pc, #116] @ (8002a9c ) 8002a28: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8002a2c: 6013 str r3, [r2, #0] sensorsInfo.pvTemperature[1] = pvT2AveTemp; 8002a2e: 4a1b ldr r2, [pc, #108] @ (8002a9c ) 8002a30: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8002a34: 6053 str r3, [r2, #4] osMutexRelease (sensorsInfoMutex); 8002a36: 4b18 ldr r3, [pc, #96] @ (8002a98 ) 8002a38: 681b ldr r3, [r3, #0] 8002a3a: 4618 mov r0, r3 8002a3c: f011 fdca bl 80145d4 } ++circBuffPos; 8002a40: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002a44: 3301 adds r3, #1 8002a46: f8c7 30ec str.w r3, [r7, #236] @ 0xec circBuffPos = circBuffPos % CIRC_BUFF_LEN; 8002a4a: f8d7 20ec ldr.w r2, [r7, #236] @ 0xec 8002a4e: 4b14 ldr r3, [pc, #80] @ (8002aa0 ) 8002a50: fba3 1302 umull r1, r3, r3, r2 8002a54: 08d9 lsrs r1, r3, #3 8002a56: 460b mov r3, r1 8002a58: 009b lsls r3, r3, #2 8002a5a: 440b add r3, r1 8002a5c: 005b lsls r3, r3, #1 8002a5e: 1ad3 subs r3, r2, r3 8002a60: f8c7 30ec str.w r3, [r7, #236] @ 0xec while (pdTRUE) { 8002a64: e68a b.n 800277c 8002a66: bf00 nop 8002a68: 00000000 .word 0x00000000 8002a6c: 40efffe0 .word 0x40efffe0 8002a70: 3ad18d26 .word 0x3ad18d26 8002a74: 4020aaaa .word 0x4020aaaa 8002a78: aaa38226 .word 0xaaa38226 8002a7c: 4046aaaa .word 0x4046aaaa 8002a80: 00000000 .word 0x00000000 8002a84: 404f8000 .word 0x404f8000 8002a88: 24000808 .word 0x24000808 8002a8c: 1ff1e860 .word 0x1ff1e860 8002a90: 24000814 .word 0x24000814 8002a94: 24000030 .word 0x24000030 8002a98: 2400081c .word 0x2400081c 8002a9c: 24000860 .word 0x24000860 8002aa0: cccccccd .word 0xcccccccd 08002aa4 : } } void LimiterSwitchTask (void* arg) { 8002aa4: b580 push {r7, lr} 8002aa6: b08a sub sp, #40 @ 0x28 8002aa8: af06 add r7, sp, #24 8002aaa: 6078 str r0, [r7, #4] LimiterSwitchData limiterSwitchData = { 0 }; 8002aac: 2300 movs r3, #0 8002aae: 60bb str r3, [r7, #8] limiterSwitchData.gpioPin = GPIO_PIN_8; 8002ab0: f44f 7380 mov.w r3, #256 @ 0x100 8002ab4: 813b strh r3, [r7, #8] for (uint8_t i = 0; i < 6; i++) { 8002ab6: 2300 movs r3, #0 8002ab8: 73fb strb r3, [r7, #15] 8002aba: e02c b.n 8002b16 limiterSwitchData.pinState = HAL_GPIO_ReadPin (GPIOD, limiterSwitchData.gpioPin); 8002abc: 893b ldrh r3, [r7, #8] 8002abe: 4619 mov r1, r3 8002ac0: 48a5 ldr r0, [pc, #660] @ (8002d58 ) 8002ac2: f008 fd77 bl 800b5b4 8002ac6: 4603 mov r3, r0 8002ac8: 72bb strb r3, [r7, #10] osMessageQueuePut (limiterSwitchDataQueue, &limiterSwitchData, 0, 0); 8002aca: 4ba4 ldr r3, [pc, #656] @ (8002d5c ) 8002acc: 6818 ldr r0, [r3, #0] 8002ace: f107 0108 add.w r1, r7, #8 8002ad2: 2300 movs r3, #0 8002ad4: 2200 movs r2, #0 8002ad6: f011 fe2d bl 8014734 limiterSwitchData.gpioPin = limiterSwitchData.gpioPin << 1; 8002ada: 893b ldrh r3, [r7, #8] 8002adc: 005b lsls r3, r3, #1 8002ade: b29b uxth r3, r3 8002ae0: 813b strh r3, [r7, #8] if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8002ae2: 4b9f ldr r3, [pc, #636] @ (8002d60 ) 8002ae4: 681b ldr r3, [r3, #0] 8002ae6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002aea: 4618 mov r0, r3 8002aec: f011 fd27 bl 801453e 8002af0: 4603 mov r3, r0 8002af2: 2b00 cmp r3, #0 8002af4: d10c bne.n 8002b10 sensorsInfo.positionXWeak = 1; 8002af6: 4b9b ldr r3, [pc, #620] @ (8002d64 ) 8002af8: 2201 movs r2, #1 8002afa: f883 2038 strb.w r2, [r3, #56] @ 0x38 sensorsInfo.positionYWeak = 1; 8002afe: 4b99 ldr r3, [pc, #612] @ (8002d64 ) 8002b00: 2201 movs r2, #1 8002b02: f883 2039 strb.w r2, [r3, #57] @ 0x39 osMutexRelease (sensorsInfoMutex); 8002b06: 4b96 ldr r3, [pc, #600] @ (8002d60 ) 8002b08: 681b ldr r3, [r3, #0] 8002b0a: 4618 mov r0, r3 8002b0c: f011 fd62 bl 80145d4 for (uint8_t i = 0; i < 6; i++) { 8002b10: 7bfb ldrb r3, [r7, #15] 8002b12: 3301 adds r3, #1 8002b14: 73fb strb r3, [r7, #15] 8002b16: 7bfb ldrb r3, [r7, #15] 8002b18: 2b05 cmp r3, #5 8002b1a: d9cf bls.n 8002abc } } while (pdTRUE) { osMessageQueueGet (limiterSwitchDataQueue, &limiterSwitchData, 0, osWaitForever); 8002b1c: 4b8f ldr r3, [pc, #572] @ (8002d5c ) 8002b1e: 6818 ldr r0, [r3, #0] 8002b20: f107 0108 add.w r1, r7, #8 8002b24: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002b28: 2200 movs r2, #0 8002b2a: f011 fe63 bl 80147f4 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8002b2e: 4b8c ldr r3, [pc, #560] @ (8002d60 ) 8002b30: 681b ldr r3, [r3, #0] 8002b32: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002b36: 4618 mov r0, r3 8002b38: f011 fd01 bl 801453e 8002b3c: 4603 mov r3, r0 8002b3e: 2b00 cmp r3, #0 8002b40: d1ec bne.n 8002b1c switch (limiterSwitchData.gpioPin) { 8002b42: 893b ldrh r3, [r7, #8] 8002b44: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8002b48: f000 8094 beq.w 8002c74 8002b4c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8002b50: f300 80a8 bgt.w 8002ca4 8002b54: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8002b58: d075 beq.n 8002c46 8002b5a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8002b5e: f300 80a1 bgt.w 8002ca4 8002b62: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8002b66: d057 beq.n 8002c18 8002b68: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8002b6c: f300 809a bgt.w 8002ca4 8002b70: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8002b74: d039 beq.n 8002bea 8002b76: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8002b7a: f300 8093 bgt.w 8002ca4 8002b7e: f5b3 7f80 cmp.w r3, #256 @ 0x100 8002b82: d003 beq.n 8002b8c 8002b84: f5b3 7f00 cmp.w r3, #512 @ 0x200 8002b88: d017 beq.n 8002bba { sensorsInfo.currentXPosition = 0; sensorsInfo.positionXWeak = 0; } break; default: break; 8002b8a: e08b b.n 8002ca4 sensorsInfo.limitYSwitchCenter = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002b8c: 7abb ldrb r3, [r7, #10] 8002b8e: 2b01 cmp r3, #1 8002b90: bf0c ite eq 8002b92: 2301 moveq r3, #1 8002b94: 2300 movne r3, #0 8002b96: b2db uxtb r3, r3 8002b98: 461a mov r2, r3 8002b9a: 4b72 ldr r3, [pc, #456] @ (8002d64 ) 8002b9c: f883 202d strb.w r2, [r3, #45] @ 0x2d if (sensorsInfo.limitYSwitchCenter == 1) 8002ba0: 4b70 ldr r3, [pc, #448] @ (8002d64 ) 8002ba2: f893 302d ldrb.w r3, [r3, #45] @ 0x2d 8002ba6: 2b01 cmp r3, #1 8002ba8: d17e bne.n 8002ca8 sensorsInfo.currentYPosition = AXE_Y_MIDDLE_VALUE; 8002baa: 4b6e ldr r3, [pc, #440] @ (8002d64 ) 8002bac: 4a6e ldr r2, [pc, #440] @ (8002d68 ) 8002bae: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8002bb0: 4b6c ldr r3, [pc, #432] @ (8002d64 ) 8002bb2: 2200 movs r2, #0 8002bb4: f883 2039 strb.w r2, [r3, #57] @ 0x39 break; 8002bb8: e076 b.n 8002ca8 sensorsInfo.limitYSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002bba: 7abb ldrb r3, [r7, #10] 8002bbc: 2b01 cmp r3, #1 8002bbe: bf0c ite eq 8002bc0: 2301 moveq r3, #1 8002bc2: 2300 movne r3, #0 8002bc4: b2db uxtb r3, r3 8002bc6: 461a mov r2, r3 8002bc8: 4b66 ldr r3, [pc, #408] @ (8002d64 ) 8002bca: f883 202c strb.w r2, [r3, #44] @ 0x2c if (sensorsInfo.limitYSwitchDown == 1) 8002bce: 4b65 ldr r3, [pc, #404] @ (8002d64 ) 8002bd0: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 8002bd4: 2b01 cmp r3, #1 8002bd6: d169 bne.n 8002cac sensorsInfo.currentYPosition = 0; 8002bd8: 4b62 ldr r3, [pc, #392] @ (8002d64 ) 8002bda: f04f 0200 mov.w r2, #0 8002bde: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8002be0: 4b60 ldr r3, [pc, #384] @ (8002d64 ) 8002be2: 2200 movs r2, #0 8002be4: f883 2039 strb.w r2, [r3, #57] @ 0x39 break; 8002be8: e060 b.n 8002cac sensorsInfo.limitXSwitchCenter = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002bea: 7abb ldrb r3, [r7, #10] 8002bec: 2b01 cmp r3, #1 8002bee: bf0c ite eq 8002bf0: 2301 moveq r3, #1 8002bf2: 2300 movne r3, #0 8002bf4: b2db uxtb r3, r3 8002bf6: 461a mov r2, r3 8002bf8: 4b5a ldr r3, [pc, #360] @ (8002d64 ) 8002bfa: f883 202a strb.w r2, [r3, #42] @ 0x2a if (sensorsInfo.limitXSwitchCenter == 1) 8002bfe: 4b59 ldr r3, [pc, #356] @ (8002d64 ) 8002c00: f893 302a ldrb.w r3, [r3, #42] @ 0x2a 8002c04: 2b01 cmp r3, #1 8002c06: d153 bne.n 8002cb0 sensorsInfo.currentXPosition = AXE_X_MIDDLE_VALUE; 8002c08: 4b56 ldr r3, [pc, #344] @ (8002d64 ) 8002c0a: 4a57 ldr r2, [pc, #348] @ (8002d68 ) 8002c0c: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8002c0e: 4b55 ldr r3, [pc, #340] @ (8002d64 ) 8002c10: 2200 movs r2, #0 8002c12: f883 2038 strb.w r2, [r3, #56] @ 0x38 break; 8002c16: e04b b.n 8002cb0 sensorsInfo.limitYSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002c18: 7abb ldrb r3, [r7, #10] 8002c1a: 2b01 cmp r3, #1 8002c1c: bf0c ite eq 8002c1e: 2301 moveq r3, #1 8002c20: 2300 movne r3, #0 8002c22: b2db uxtb r3, r3 8002c24: 461a mov r2, r3 8002c26: 4b4f ldr r3, [pc, #316] @ (8002d64 ) 8002c28: f883 202b strb.w r2, [r3, #43] @ 0x2b if (sensorsInfo.limitYSwitchUp == 1) 8002c2c: 4b4d ldr r3, [pc, #308] @ (8002d64 ) 8002c2e: f893 302b ldrb.w r3, [r3, #43] @ 0x2b 8002c32: 2b01 cmp r3, #1 8002c34: d13e bne.n 8002cb4 sensorsInfo.currentYPosition = 100; 8002c36: 4b4b ldr r3, [pc, #300] @ (8002d64 ) 8002c38: 4a4c ldr r2, [pc, #304] @ (8002d6c ) 8002c3a: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8002c3c: 4b49 ldr r3, [pc, #292] @ (8002d64 ) 8002c3e: 2200 movs r2, #0 8002c40: f883 2039 strb.w r2, [r3, #57] @ 0x39 break; 8002c44: e036 b.n 8002cb4 sensorsInfo.limitXSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002c46: 7abb ldrb r3, [r7, #10] 8002c48: 2b01 cmp r3, #1 8002c4a: bf0c ite eq 8002c4c: 2301 moveq r3, #1 8002c4e: 2300 movne r3, #0 8002c50: b2db uxtb r3, r3 8002c52: 461a mov r2, r3 8002c54: 4b43 ldr r3, [pc, #268] @ (8002d64 ) 8002c56: f883 2028 strb.w r2, [r3, #40] @ 0x28 if (sensorsInfo.limitXSwitchUp == 1) 8002c5a: 4b42 ldr r3, [pc, #264] @ (8002d64 ) 8002c5c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8002c60: 2b01 cmp r3, #1 8002c62: d129 bne.n 8002cb8 sensorsInfo.currentXPosition = 100; 8002c64: 4b3f ldr r3, [pc, #252] @ (8002d64 ) 8002c66: 4a41 ldr r2, [pc, #260] @ (8002d6c ) 8002c68: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8002c6a: 4b3e ldr r3, [pc, #248] @ (8002d64 ) 8002c6c: 2200 movs r2, #0 8002c6e: f883 2038 strb.w r2, [r3, #56] @ 0x38 break; 8002c72: e021 b.n 8002cb8 sensorsInfo.limitXSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002c74: 7abb ldrb r3, [r7, #10] 8002c76: 2b01 cmp r3, #1 8002c78: bf0c ite eq 8002c7a: 2301 moveq r3, #1 8002c7c: 2300 movne r3, #0 8002c7e: b2db uxtb r3, r3 8002c80: 461a mov r2, r3 8002c82: 4b38 ldr r3, [pc, #224] @ (8002d64 ) 8002c84: f883 2029 strb.w r2, [r3, #41] @ 0x29 if (sensorsInfo.limitXSwitchDown == 1) 8002c88: 4b36 ldr r3, [pc, #216] @ (8002d64 ) 8002c8a: f893 3029 ldrb.w r3, [r3, #41] @ 0x29 8002c8e: 2b01 cmp r3, #1 8002c90: d114 bne.n 8002cbc sensorsInfo.currentXPosition = 0; 8002c92: 4b34 ldr r3, [pc, #208] @ (8002d64 ) 8002c94: f04f 0200 mov.w r2, #0 8002c98: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8002c9a: 4b32 ldr r3, [pc, #200] @ (8002d64 ) 8002c9c: 2200 movs r2, #0 8002c9e: f883 2038 strb.w r2, [r3, #56] @ 0x38 break; 8002ca2: e00b b.n 8002cbc default: break; 8002ca4: bf00 nop 8002ca6: e00a b.n 8002cbe break; 8002ca8: bf00 nop 8002caa: e008 b.n 8002cbe break; 8002cac: bf00 nop 8002cae: e006 b.n 8002cbe break; 8002cb0: bf00 nop 8002cb2: e004 b.n 8002cbe break; 8002cb4: bf00 nop 8002cb6: e002 b.n 8002cbe break; 8002cb8: bf00 nop 8002cba: e000 b.n 8002cbe break; 8002cbc: bf00 nop } if ((sensorsInfo.limitXSwitchDown == 1) || (sensorsInfo.limitXSwitchUp == 1)) { 8002cbe: 4b29 ldr r3, [pc, #164] @ (8002d64 ) 8002cc0: f893 3029 ldrb.w r3, [r3, #41] @ 0x29 8002cc4: 2b01 cmp r3, #1 8002cc6: d004 beq.n 8002cd2 8002cc8: 4b26 ldr r3, [pc, #152] @ (8002d64 ) 8002cca: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8002cce: 2b01 cmp r3, #1 8002cd0: d118 bne.n 8002d04 sensorsInfo.motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, 0, 0, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 8002cd2: 4b27 ldr r3, [pc, #156] @ (8002d70 ) 8002cd4: 681b ldr r3, [r3, #0] 8002cd6: 4a23 ldr r2, [pc, #140] @ (8002d64 ) 8002cd8: f892 2028 ldrb.w r2, [r2, #40] @ 0x28 8002cdc: 4921 ldr r1, [pc, #132] @ (8002d64 ) 8002cde: f891 1029 ldrb.w r1, [r1, #41] @ 0x29 8002ce2: 9104 str r1, [sp, #16] 8002ce4: 9203 str r2, [sp, #12] 8002ce6: 2200 movs r2, #0 8002ce8: 9202 str r2, [sp, #8] 8002cea: 2200 movs r2, #0 8002cec: 9201 str r2, [sp, #4] 8002cee: 9300 str r3, [sp, #0] 8002cf0: 2304 movs r3, #4 8002cf2: 2200 movs r2, #0 8002cf4: 491f ldr r1, [pc, #124] @ (8002d74 ) 8002cf6: 4820 ldr r0, [pc, #128] @ (8002d78 ) 8002cf8: f000 f9c2 bl 8003080 8002cfc: 4603 mov r3, r0 8002cfe: 461a mov r2, r3 8002d00: 4b18 ldr r3, [pc, #96] @ (8002d64 ) 8002d02: 751a strb r2, [r3, #20] } if ((sensorsInfo.limitYSwitchDown == 1) || (sensorsInfo.limitYSwitchUp == 1)) { 8002d04: 4b17 ldr r3, [pc, #92] @ (8002d64 ) 8002d06: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 8002d0a: 2b01 cmp r3, #1 8002d0c: d004 beq.n 8002d18 8002d0e: 4b15 ldr r3, [pc, #84] @ (8002d64 ) 8002d10: f893 302b ldrb.w r3, [r3, #43] @ 0x2b 8002d14: 2b01 cmp r3, #1 8002d16: d118 bne.n 8002d4a sensorsInfo.motorYStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, 0, 0, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 8002d18: 4b18 ldr r3, [pc, #96] @ (8002d7c ) 8002d1a: 681b ldr r3, [r3, #0] 8002d1c: 4a11 ldr r2, [pc, #68] @ (8002d64 ) 8002d1e: f892 202b ldrb.w r2, [r2, #43] @ 0x2b 8002d22: 4910 ldr r1, [pc, #64] @ (8002d64 ) 8002d24: f891 102c ldrb.w r1, [r1, #44] @ 0x2c 8002d28: 9104 str r1, [sp, #16] 8002d2a: 9203 str r2, [sp, #12] 8002d2c: 2200 movs r2, #0 8002d2e: 9202 str r2, [sp, #8] 8002d30: 2200 movs r2, #0 8002d32: 9201 str r2, [sp, #4] 8002d34: 9300 str r3, [sp, #0] 8002d36: 230c movs r3, #12 8002d38: 2208 movs r2, #8 8002d3a: 490e ldr r1, [pc, #56] @ (8002d74 ) 8002d3c: 480e ldr r0, [pc, #56] @ (8002d78 ) 8002d3e: f000 f99f bl 8003080 8002d42: 4603 mov r3, r0 8002d44: 461a mov r2, r3 8002d46: 4b07 ldr r3, [pc, #28] @ (8002d64 ) 8002d48: 755a strb r2, [r3, #21] } osMutexRelease (sensorsInfoMutex); 8002d4a: 4b05 ldr r3, [pc, #20] @ (8002d60 ) 8002d4c: 681b ldr r3, [r3, #0] 8002d4e: 4618 mov r0, r3 8002d50: f011 fc40 bl 80145d4 osMessageQueueGet (limiterSwitchDataQueue, &limiterSwitchData, 0, osWaitForever); 8002d54: e6e2 b.n 8002b1c 8002d56: bf00 nop 8002d58: 58020c00 .word 0x58020c00 8002d5c: 2400080c .word 0x2400080c 8002d60: 2400081c .word 0x2400081c 8002d64: 24000860 .word 0x24000860 8002d68: 42480000 .word 0x42480000 8002d6c: 42c80000 .word 0x42c80000 8002d70: 24000744 .word 0x24000744 8002d74: 240007c0 .word 0x240007c0 8002d78: 240004d4 .word 0x240004d4 8002d7c: 24000774 .word 0x24000774 08002d80 : } } } void EncoderTask (void* arg) { 8002d80: b580 push {r7, lr} 8002d82: b086 sub sp, #24 8002d84: af00 add r7, sp, #0 8002d86: 6078 str r0, [r7, #4] EncoderData encoderData = { 0 }; 8002d88: 2300 movs r3, #0 8002d8a: 813b strh r3, [r7, #8] osMessageQueueId_t encoderQueue = (osMessageQueueId_t)arg; 8002d8c: 687b ldr r3, [r7, #4] 8002d8e: 617b str r3, [r7, #20] while (pdTRUE) { osMessageQueueGet (encoderQueue, &encoderData, 0, osWaitForever); 8002d90: f107 0108 add.w r1, r7, #8 8002d94: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002d98: 2200 movs r2, #0 8002d9a: 6978 ldr r0, [r7, #20] 8002d9c: f011 fd2a bl 80147f4 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8002da0: 4b6b ldr r3, [pc, #428] @ (8002f50 ) 8002da2: 681b ldr r3, [r3, #0] 8002da4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002da8: 4618 mov r0, r3 8002daa: f011 fbc8 bl 801453e 8002dae: 4603 mov r3, r0 8002db0: 2b00 cmp r3, #0 8002db2: d1ed bne.n 8002d90 if (encoderData.axe == encoderAxeX) { 8002db4: 7a3b ldrb r3, [r7, #8] 8002db6: 2b00 cmp r3, #0 8002db8: d162 bne.n 8002e80 if (encoderData.direction == encoderCW) { 8002dba: 7a7b ldrb r3, [r7, #9] 8002dbc: 2b00 cmp r3, #0 8002dbe: d10a bne.n 8002dd6 sensorsInfo.pvEncoderX += 360.0 / ENCODER_X_IMP_PER_TURN; 8002dc0: 4b64 ldr r3, [pc, #400] @ (8002f54 ) 8002dc2: edd3 7a03 vldr s15, [r3, #12] 8002dc6: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002dca: ee77 7a87 vadd.f32 s15, s15, s14 8002dce: 4b61 ldr r3, [pc, #388] @ (8002f54 ) 8002dd0: edc3 7a03 vstr s15, [r3, #12] 8002dd4: e01b b.n 8002e0e } else { sensorsInfo.pvEncoderX -= 360.0 / ENCODER_X_IMP_PER_TURN; 8002dd6: 4b5f ldr r3, [pc, #380] @ (8002f54 ) 8002dd8: edd3 7a03 vldr s15, [r3, #12] 8002ddc: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002de0: ee77 7ac7 vsub.f32 s15, s15, s14 8002de4: 4b5b ldr r3, [pc, #364] @ (8002f54 ) 8002de6: edc3 7a03 vstr s15, [r3, #12] if(sensorsInfo.pvEncoderX < 0) 8002dea: 4b5a ldr r3, [pc, #360] @ (8002f54 ) 8002dec: edd3 7a03 vldr s15, [r3, #12] 8002df0: eef5 7ac0 vcmpe.f32 s15, #0.0 8002df4: eef1 fa10 vmrs APSR_nzcv, fpscr 8002df8: d509 bpl.n 8002e0e { sensorsInfo.pvEncoderX = 360.0 + sensorsInfo.pvEncoderX; 8002dfa: 4b56 ldr r3, [pc, #344] @ (8002f54 ) 8002dfc: edd3 7a03 vldr s15, [r3, #12] 8002e00: ed9f 7a55 vldr s14, [pc, #340] @ 8002f58 8002e04: ee77 7a87 vadd.f32 s15, s15, s14 8002e08: 4b52 ldr r3, [pc, #328] @ (8002f54 ) 8002e0a: edc3 7a03 vstr s15, [r3, #12] } } sensorsInfo.pvEncoderX = fmodf(sensorsInfo.pvEncoderX, 360.0); 8002e0e: 4b51 ldr r3, [pc, #324] @ (8002f54 ) 8002e10: edd3 7a03 vldr s15, [r3, #12] 8002e14: eddf 0a50 vldr s1, [pc, #320] @ 8002f58 8002e18: eeb0 0a67 vmov.f32 s0, s15 8002e1c: f015 fbaa bl 8018574 8002e20: eef0 7a40 vmov.f32 s15, s0 8002e24: 4b4b ldr r3, [pc, #300] @ (8002f54 ) 8002e26: edc3 7a03 vstr s15, [r3, #12] float currentPercentPos = 100 * sensorsInfo.pvEncoderX / MAX_X_AXE_ANGLE; 8002e2a: 4b4a ldr r3, [pc, #296] @ (8002f54 ) 8002e2c: edd3 7a03 vldr s15, [r3, #12] 8002e30: ed9f 7a4a vldr s14, [pc, #296] @ 8002f5c 8002e34: ee27 7a87 vmul.f32 s14, s15, s14 8002e38: eddf 6a47 vldr s13, [pc, #284] @ 8002f58 8002e3c: eec7 7a26 vdiv.f32 s15, s14, s13 8002e40: edc7 7a03 vstr s15, [r7, #12] currentPercentPos = currentPercentPos < 0 ? 0 : currentPercentPos; 8002e44: edd7 7a03 vldr s15, [r7, #12] 8002e48: eef5 7ac0 vcmpe.f32 s15, #0.0 8002e4c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002e50: d502 bpl.n 8002e58 8002e52: f04f 0300 mov.w r3, #0 8002e56: e000 b.n 8002e5a 8002e58: 68fb ldr r3, [r7, #12] 8002e5a: 60fb str r3, [r7, #12] sensorsInfo.currentXPosition = currentPercentPos > 100 ? 100 : currentPercentPos; 8002e5c: edd7 7a03 vldr s15, [r7, #12] 8002e60: ed9f 7a3e vldr s14, [pc, #248] @ 8002f5c 8002e64: eef4 7ac7 vcmpe.f32 s15, s14 8002e68: eef1 fa10 vmrs APSR_nzcv, fpscr 8002e6c: dd01 ble.n 8002e72 8002e6e: 4b3c ldr r3, [pc, #240] @ (8002f60 ) 8002e70: e000 b.n 8002e74 8002e72: 68fb ldr r3, [r7, #12] 8002e74: 4a37 ldr r2, [pc, #220] @ (8002f54 ) 8002e76: 6313 str r3, [r2, #48] @ 0x30 DbgLEDToggle(DBG_LED2); 8002e78: 2020 movs r0, #32 8002e7a: f000 f897 bl 8002fac 8002e7e: e061 b.n 8002f44 } else { if (encoderData.direction == encoderCW) { 8002e80: 7a7b ldrb r3, [r7, #9] 8002e82: 2b00 cmp r3, #0 8002e84: d10a bne.n 8002e9c sensorsInfo.pvEncoderY += 360.0 / ENCODER_Y_IMP_PER_TURN; 8002e86: 4b33 ldr r3, [pc, #204] @ (8002f54 ) 8002e88: edd3 7a04 vldr s15, [r3, #16] 8002e8c: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002e90: ee77 7a87 vadd.f32 s15, s15, s14 8002e94: 4b2f ldr r3, [pc, #188] @ (8002f54 ) 8002e96: edc3 7a04 vstr s15, [r3, #16] 8002e9a: e01b b.n 8002ed4 } else { sensorsInfo.pvEncoderY -= 360.0 / ENCODER_Y_IMP_PER_TURN; 8002e9c: 4b2d ldr r3, [pc, #180] @ (8002f54 ) 8002e9e: edd3 7a04 vldr s15, [r3, #16] 8002ea2: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002ea6: ee77 7ac7 vsub.f32 s15, s15, s14 8002eaa: 4b2a ldr r3, [pc, #168] @ (8002f54 ) 8002eac: edc3 7a04 vstr s15, [r3, #16] if(sensorsInfo.pvEncoderY < 0) 8002eb0: 4b28 ldr r3, [pc, #160] @ (8002f54 ) 8002eb2: edd3 7a04 vldr s15, [r3, #16] 8002eb6: eef5 7ac0 vcmpe.f32 s15, #0.0 8002eba: eef1 fa10 vmrs APSR_nzcv, fpscr 8002ebe: d509 bpl.n 8002ed4 { sensorsInfo.pvEncoderY = 360.0 + sensorsInfo.pvEncoderY; 8002ec0: 4b24 ldr r3, [pc, #144] @ (8002f54 ) 8002ec2: edd3 7a04 vldr s15, [r3, #16] 8002ec6: ed9f 7a24 vldr s14, [pc, #144] @ 8002f58 8002eca: ee77 7a87 vadd.f32 s15, s15, s14 8002ece: 4b21 ldr r3, [pc, #132] @ (8002f54 ) 8002ed0: edc3 7a04 vstr s15, [r3, #16] } } sensorsInfo.pvEncoderY = fmodf(sensorsInfo.pvEncoderY, 360.0); 8002ed4: 4b1f ldr r3, [pc, #124] @ (8002f54 ) 8002ed6: edd3 7a04 vldr s15, [r3, #16] 8002eda: eddf 0a1f vldr s1, [pc, #124] @ 8002f58 8002ede: eeb0 0a67 vmov.f32 s0, s15 8002ee2: f015 fb47 bl 8018574 8002ee6: eef0 7a40 vmov.f32 s15, s0 8002eea: 4b1a ldr r3, [pc, #104] @ (8002f54 ) 8002eec: edc3 7a04 vstr s15, [r3, #16] float currentPercentPos = 100 * sensorsInfo.pvEncoderY / MAX_X_AXE_ANGLE; 8002ef0: 4b18 ldr r3, [pc, #96] @ (8002f54 ) 8002ef2: edd3 7a04 vldr s15, [r3, #16] 8002ef6: ed9f 7a19 vldr s14, [pc, #100] @ 8002f5c 8002efa: ee27 7a87 vmul.f32 s14, s15, s14 8002efe: eddf 6a16 vldr s13, [pc, #88] @ 8002f58 8002f02: eec7 7a26 vdiv.f32 s15, s14, s13 8002f06: edc7 7a04 vstr s15, [r7, #16] currentPercentPos = currentPercentPos < 0 ? 0 : currentPercentPos; 8002f0a: edd7 7a04 vldr s15, [r7, #16] 8002f0e: eef5 7ac0 vcmpe.f32 s15, #0.0 8002f12: eef1 fa10 vmrs APSR_nzcv, fpscr 8002f16: d502 bpl.n 8002f1e 8002f18: f04f 0300 mov.w r3, #0 8002f1c: e000 b.n 8002f20 8002f1e: 693b ldr r3, [r7, #16] 8002f20: 613b str r3, [r7, #16] sensorsInfo.currentXPosition = currentPercentPos > 100 ? 100 : currentPercentPos; 8002f22: edd7 7a04 vldr s15, [r7, #16] 8002f26: ed9f 7a0d vldr s14, [pc, #52] @ 8002f5c 8002f2a: eef4 7ac7 vcmpe.f32 s15, s14 8002f2e: eef1 fa10 vmrs APSR_nzcv, fpscr 8002f32: dd01 ble.n 8002f38 8002f34: 4b0a ldr r3, [pc, #40] @ (8002f60 ) 8002f36: e000 b.n 8002f3a 8002f38: 693b ldr r3, [r7, #16] 8002f3a: 4a06 ldr r2, [pc, #24] @ (8002f54 ) 8002f3c: 6313 str r3, [r2, #48] @ 0x30 DbgLEDToggle(DBG_LED3); 8002f3e: 2040 movs r0, #64 @ 0x40 8002f40: f000 f834 bl 8002fac } osMutexRelease (sensorsInfoMutex); 8002f44: 4b02 ldr r3, [pc, #8] @ (8002f50 ) 8002f46: 681b ldr r3, [r3, #0] 8002f48: 4618 mov r0, r3 8002f4a: f011 fb43 bl 80145d4 osMessageQueueGet (encoderQueue, &encoderData, 0, osWaitForever); 8002f4e: e71f b.n 8002d90 8002f50: 2400081c .word 0x2400081c 8002f54: 24000860 .word 0x24000860 8002f58: 43b40000 .word 0x43b40000 8002f5c: 42c80000 .word 0x42c80000 8002f60: 42c80000 .word 0x42c80000 08002f64 : #include #include "peripherial.h" void DbgLEDOn (uint8_t ledNumber) { 8002f64: b580 push {r7, lr} 8002f66: b082 sub sp, #8 8002f68: af00 add r7, sp, #0 8002f6a: 4603 mov r3, r0 8002f6c: 71fb strb r3, [r7, #7] HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_SET); 8002f6e: 79fb ldrb r3, [r7, #7] 8002f70: b29b uxth r3, r3 8002f72: 2201 movs r2, #1 8002f74: 4619 mov r1, r3 8002f76: 4803 ldr r0, [pc, #12] @ (8002f84 ) 8002f78: f008 fb34 bl 800b5e4 } 8002f7c: bf00 nop 8002f7e: 3708 adds r7, #8 8002f80: 46bd mov sp, r7 8002f82: bd80 pop {r7, pc} 8002f84: 58020c00 .word 0x58020c00 08002f88 : void DbgLEDOff (uint8_t ledNumber) { 8002f88: b580 push {r7, lr} 8002f8a: b082 sub sp, #8 8002f8c: af00 add r7, sp, #0 8002f8e: 4603 mov r3, r0 8002f90: 71fb strb r3, [r7, #7] HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_RESET); 8002f92: 79fb ldrb r3, [r7, #7] 8002f94: b29b uxth r3, r3 8002f96: 2200 movs r2, #0 8002f98: 4619 mov r1, r3 8002f9a: 4803 ldr r0, [pc, #12] @ (8002fa8 ) 8002f9c: f008 fb22 bl 800b5e4 } 8002fa0: bf00 nop 8002fa2: 3708 adds r7, #8 8002fa4: 46bd mov sp, r7 8002fa6: bd80 pop {r7, pc} 8002fa8: 58020c00 .word 0x58020c00 08002fac : void DbgLEDToggle (uint8_t ledNumber) { 8002fac: b580 push {r7, lr} 8002fae: b082 sub sp, #8 8002fb0: af00 add r7, sp, #0 8002fb2: 4603 mov r3, r0 8002fb4: 71fb strb r3, [r7, #7] HAL_GPIO_TogglePin (GPIOD, ledNumber); 8002fb6: 79fb ldrb r3, [r7, #7] 8002fb8: b29b uxth r3, r3 8002fba: 4619 mov r1, r3 8002fbc: 4803 ldr r0, [pc, #12] @ (8002fcc ) 8002fbe: f008 fb2a bl 800b616 } 8002fc2: bf00 nop 8002fc4: 3708 adds r7, #8 8002fc6: 46bd mov sp, r7 8002fc8: bd80 pop {r7, pc} 8002fca: bf00 nop 8002fcc: 58020c00 .word 0x58020c00 08002fd0 : void EnableCurrentSensors (void) { 8002fd0: b580 push {r7, lr} 8002fd2: af00 add r7, sp, #0 HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_SET); 8002fd4: 2201 movs r2, #1 8002fd6: f44f 4100 mov.w r1, #32768 @ 0x8000 8002fda: 4802 ldr r0, [pc, #8] @ (8002fe4 ) 8002fdc: f008 fb02 bl 800b5e4 } 8002fe0: bf00 nop 8002fe2: bd80 pop {r7, pc} 8002fe4: 58021000 .word 0x58021000 08002fe8 : void DisableCurrentSensors (void) { HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_RESET); } void SelectCurrentSensorGain (CurrentSensor sensor, CurrentSensorGain gain) { 8002fe8: b580 push {r7, lr} 8002fea: b084 sub sp, #16 8002fec: af00 add r7, sp, #0 8002fee: 4603 mov r3, r0 8002ff0: 460a mov r2, r1 8002ff2: 71fb strb r3, [r7, #7] 8002ff4: 4613 mov r3, r2 8002ff6: 71bb strb r3, [r7, #6] uint8_t gpioOffset = 0; 8002ff8: 2300 movs r3, #0 8002ffa: 73fb strb r3, [r7, #15] switch (sensor) { 8002ffc: 79fb ldrb r3, [r7, #7] 8002ffe: 2b02 cmp r3, #2 8003000: d00c beq.n 800301c 8003002: 2b02 cmp r3, #2 8003004: dc0d bgt.n 8003022 8003006: 2b00 cmp r3, #0 8003008: d002 beq.n 8003010 800300a: 2b01 cmp r3, #1 800300c: d003 beq.n 8003016 case CurrentSensorL1: gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET; break; case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break; case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break; default: break; 800300e: e008 b.n 8003022 case CurrentSensorL1: gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET; break; 8003010: 2307 movs r3, #7 8003012: 73fb strb r3, [r7, #15] 8003014: e006 b.n 8003024 case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break; 8003016: 2309 movs r3, #9 8003018: 73fb strb r3, [r7, #15] 800301a: e003 b.n 8003024 case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break; 800301c: 230d movs r3, #13 800301e: 73fb strb r3, [r7, #15] 8003020: e000 b.n 8003024 default: break; 8003022: bf00 nop } if (gpioOffset > 0) { 8003024: 7bfb ldrb r3, [r7, #15] 8003026: 2b00 cmp r3, #0 8003028: d023 beq.n 8003072 uint16_t gain0Gpio = 1 << gpioOffset; 800302a: 7bfb ldrb r3, [r7, #15] 800302c: 2201 movs r2, #1 800302e: fa02 f303 lsl.w r3, r2, r3 8003032: 81bb strh r3, [r7, #12] uint16_t gain1Gpio = 1 << (gpioOffset + 1); 8003034: 7bfb ldrb r3, [r7, #15] 8003036: 3301 adds r3, #1 8003038: 2201 movs r2, #1 800303a: fa02 f303 lsl.w r3, r2, r3 800303e: 817b strh r3, [r7, #10] uint16_t gpioState = ((uint16_t)gain) & 0x0001; 8003040: 79bb ldrb r3, [r7, #6] 8003042: b29b uxth r3, r3 8003044: f003 0301 and.w r3, r3, #1 8003048: 813b strh r3, [r7, #8] HAL_GPIO_WritePin (GPIOE, gain0Gpio, gpioState); 800304a: 893b ldrh r3, [r7, #8] 800304c: b2da uxtb r2, r3 800304e: 89bb ldrh r3, [r7, #12] 8003050: 4619 mov r1, r3 8003052: 480a ldr r0, [pc, #40] @ (800307c ) 8003054: f008 fac6 bl 800b5e4 gpioState = (((uint16_t)gain) >> 1) & 0x0001; 8003058: 79bb ldrb r3, [r7, #6] 800305a: 085b lsrs r3, r3, #1 800305c: b2db uxtb r3, r3 800305e: f003 0301 and.w r3, r3, #1 8003062: 813b strh r3, [r7, #8] HAL_GPIO_WritePin (GPIOE, gain1Gpio, gpioState); 8003064: 893b ldrh r3, [r7, #8] 8003066: b2da uxtb r2, r3 8003068: 897b ldrh r3, [r7, #10] 800306a: 4619 mov r1, r3 800306c: 4803 ldr r0, [pc, #12] @ (800307c ) 800306e: f008 fab9 bl 800b5e4 } } 8003072: bf00 nop 8003074: 3710 adds r7, #16 8003076: 46bd mov sp, r7 8003078: bd80 pop {r7, pc} 800307a: bf00 nop 800307c: 58021000 .word 0x58021000 08003080 : uint8_t MotorControl (TIM_HandleTypeDef* htim, TIM_OC_InitTypeDef* motorTimerConfigOC, uint8_t channel1, uint8_t channel2, osTimerId_t motorTimerHandle, int32_t motorPWMPulse, int32_t motorTimerPeriod, uint8_t switchLimiterUpStat, uint8_t switchLimiterDownStat) { 8003080: b580 push {r7, lr} 8003082: b088 sub sp, #32 8003084: af02 add r7, sp, #8 8003086: 60f8 str r0, [r7, #12] 8003088: 60b9 str r1, [r7, #8] 800308a: 4611 mov r1, r2 800308c: 461a mov r2, r3 800308e: 460b mov r3, r1 8003090: 71fb strb r3, [r7, #7] 8003092: 4613 mov r3, r2 8003094: 71bb strb r3, [r7, #6] uint32_t motorStatus = 0; 8003096: 2300 movs r3, #0 8003098: 617b str r3, [r7, #20] MotorDriverState setMotorState = HiZ; 800309a: 2300 movs r3, #0 800309c: 74fb strb r3, [r7, #19] HAL_TIM_PWM_Stop (htim, channel1); 800309e: 79fb ldrb r3, [r7, #7] 80030a0: 4619 mov r1, r3 80030a2: 68f8 ldr r0, [r7, #12] 80030a4: f00c fca6 bl 800f9f4 HAL_TIM_PWM_Stop (htim, channel2); 80030a8: 79bb ldrb r3, [r7, #6] 80030aa: 4619 mov r1, r3 80030ac: 68f8 ldr r0, [r7, #12] 80030ae: f00c fca1 bl 800f9f4 if (motorTimerPeriod > 0) { 80030b2: 6abb ldr r3, [r7, #40] @ 0x28 80030b4: 2b00 cmp r3, #0 80030b6: f340 808c ble.w 80031d2 if (motorPWMPulse > 0) { 80030ba: 6a7b ldr r3, [r7, #36] @ 0x24 80030bc: 2b00 cmp r3, #0 80030be: dd2c ble.n 800311a // Forward if (switchLimiterUpStat == 0) { 80030c0: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 80030c4: 2b00 cmp r3, #0 80030c6: d11d bne.n 8003104 setMotorState = Forward; 80030c8: 2301 movs r3, #1 80030ca: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 80030cc: 79f9 ldrb r1, [r7, #7] 80030ce: 79b8 ldrb r0, [r7, #6] 80030d0: 6a7b ldr r3, [r7, #36] @ 0x24 80030d2: ea83 72e3 eor.w r2, r3, r3, asr #31 80030d6: eba2 72e3 sub.w r2, r2, r3, asr #31 80030da: 4613 mov r3, r2 80030dc: 009b lsls r3, r3, #2 80030de: 4413 add r3, r2 80030e0: 005b lsls r3, r3, #1 80030e2: 9301 str r3, [sp, #4] 80030e4: 7cfb ldrb r3, [r7, #19] 80030e6: 9300 str r3, [sp, #0] 80030e8: 4603 mov r3, r0 80030ea: 460a mov r2, r1 80030ec: 68b9 ldr r1, [r7, #8] 80030ee: 68f8 ldr r0, [r7, #12] 80030f0: f000 f8ff bl 80032f2 HAL_TIM_PWM_Start (htim, channel1); 80030f4: 79fb ldrb r3, [r7, #7] 80030f6: 4619 mov r1, r3 80030f8: 68f8 ldr r0, [r7, #12] 80030fa: f00c fb6d bl 800f7d8 motorStatus = 1; 80030fe: 2301 movs r3, #1 8003100: 617b str r3, [r7, #20] 8003102: e004 b.n 800310e } else { HAL_TIM_PWM_Stop (htim, channel1); 8003104: 79fb ldrb r3, [r7, #7] 8003106: 4619 mov r1, r3 8003108: 68f8 ldr r0, [r7, #12] 800310a: f00c fc73 bl 800f9f4 } HAL_TIM_PWM_Stop (htim, channel2); 800310e: 79bb ldrb r3, [r7, #6] 8003110: 4619 mov r1, r3 8003112: 68f8 ldr r0, [r7, #12] 8003114: f00c fc6e bl 800f9f4 8003118: e051 b.n 80031be } else if (motorPWMPulse < 0) { 800311a: 6a7b ldr r3, [r7, #36] @ 0x24 800311c: 2b00 cmp r3, #0 800311e: da2c bge.n 800317a // Reverse if (switchLimiterDownStat == 0) { 8003120: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 8003124: 2b00 cmp r3, #0 8003126: d11d bne.n 8003164 setMotorState = Reverse; 8003128: 2302 movs r3, #2 800312a: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 800312c: 79f9 ldrb r1, [r7, #7] 800312e: 79b8 ldrb r0, [r7, #6] 8003130: 6a7b ldr r3, [r7, #36] @ 0x24 8003132: ea83 72e3 eor.w r2, r3, r3, asr #31 8003136: eba2 72e3 sub.w r2, r2, r3, asr #31 800313a: 4613 mov r3, r2 800313c: 009b lsls r3, r3, #2 800313e: 4413 add r3, r2 8003140: 005b lsls r3, r3, #1 8003142: 9301 str r3, [sp, #4] 8003144: 7cfb ldrb r3, [r7, #19] 8003146: 9300 str r3, [sp, #0] 8003148: 4603 mov r3, r0 800314a: 460a mov r2, r1 800314c: 68b9 ldr r1, [r7, #8] 800314e: 68f8 ldr r0, [r7, #12] 8003150: f000 f8cf bl 80032f2 HAL_TIM_PWM_Start (htim, channel2); 8003154: 79bb ldrb r3, [r7, #6] 8003156: 4619 mov r1, r3 8003158: 68f8 ldr r0, [r7, #12] 800315a: f00c fb3d bl 800f7d8 motorStatus = 1; 800315e: 2301 movs r3, #1 8003160: 617b str r3, [r7, #20] 8003162: e004 b.n 800316e } else { HAL_TIM_PWM_Stop (htim, channel2); 8003164: 79bb ldrb r3, [r7, #6] 8003166: 4619 mov r1, r3 8003168: 68f8 ldr r0, [r7, #12] 800316a: f00c fc43 bl 800f9f4 } HAL_TIM_PWM_Stop (htim, channel1); 800316e: 79fb ldrb r3, [r7, #7] 8003170: 4619 mov r1, r3 8003172: 68f8 ldr r0, [r7, #12] 8003174: f00c fc3e bl 800f9f4 8003178: e021 b.n 80031be } else { // Brake setMotorState = Brake; 800317a: 2303 movs r3, #3 800317c: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 800317e: 79f9 ldrb r1, [r7, #7] 8003180: 79b8 ldrb r0, [r7, #6] 8003182: 6a7b ldr r3, [r7, #36] @ 0x24 8003184: ea83 72e3 eor.w r2, r3, r3, asr #31 8003188: eba2 72e3 sub.w r2, r2, r3, asr #31 800318c: 4613 mov r3, r2 800318e: 009b lsls r3, r3, #2 8003190: 4413 add r3, r2 8003192: 005b lsls r3, r3, #1 8003194: 9301 str r3, [sp, #4] 8003196: 7cfb ldrb r3, [r7, #19] 8003198: 9300 str r3, [sp, #0] 800319a: 4603 mov r3, r0 800319c: 460a mov r2, r1 800319e: 68b9 ldr r1, [r7, #8] 80031a0: 68f8 ldr r0, [r7, #12] 80031a2: f000 f8a6 bl 80032f2 HAL_TIM_PWM_Start (htim, channel1); 80031a6: 79fb ldrb r3, [r7, #7] 80031a8: 4619 mov r1, r3 80031aa: 68f8 ldr r0, [r7, #12] 80031ac: f00c fb14 bl 800f7d8 HAL_TIM_PWM_Start (htim, channel2); 80031b0: 79bb ldrb r3, [r7, #6] 80031b2: 4619 mov r1, r3 80031b4: 68f8 ldr r0, [r7, #12] 80031b6: f00c fb0f bl 800f7d8 motorStatus = 0; 80031ba: 2300 movs r3, #0 80031bc: 617b str r3, [r7, #20] } osTimerStart (motorTimerHandle, motorTimerPeriod * 1000); 80031be: 6abb ldr r3, [r7, #40] @ 0x28 80031c0: f44f 727a mov.w r2, #1000 @ 0x3e8 80031c4: fb02 f303 mul.w r3, r2, r3 80031c8: 4619 mov r1, r3 80031ca: 6a38 ldr r0, [r7, #32] 80031cc: f011 f8cc bl 8014368 80031d0: e089 b.n 80032e6 } else if ((motorTimerPeriod == 0) && (motorPWMPulse == 0)) { 80031d2: 6abb ldr r3, [r7, #40] @ 0x28 80031d4: 2b00 cmp r3, #0 80031d6: d126 bne.n 8003226 80031d8: 6a7b ldr r3, [r7, #36] @ 0x24 80031da: 2b00 cmp r3, #0 80031dc: d123 bne.n 8003226 MotorAction (htim, motorTimerConfigOC, channel1, channel2, HiZ, abs (motorPWMPulse) * 10); 80031de: 79f9 ldrb r1, [r7, #7] 80031e0: 79b8 ldrb r0, [r7, #6] 80031e2: 6a7b ldr r3, [r7, #36] @ 0x24 80031e4: ea83 72e3 eor.w r2, r3, r3, asr #31 80031e8: eba2 72e3 sub.w r2, r2, r3, asr #31 80031ec: 4613 mov r3, r2 80031ee: 009b lsls r3, r3, #2 80031f0: 4413 add r3, r2 80031f2: 005b lsls r3, r3, #1 80031f4: 9301 str r3, [sp, #4] 80031f6: 2300 movs r3, #0 80031f8: 9300 str r3, [sp, #0] 80031fa: 4603 mov r3, r0 80031fc: 460a mov r2, r1 80031fe: 68b9 ldr r1, [r7, #8] 8003200: 68f8 ldr r0, [r7, #12] 8003202: f000 f876 bl 80032f2 HAL_TIM_PWM_Stop (htim, channel1); 8003206: 79fb ldrb r3, [r7, #7] 8003208: 4619 mov r1, r3 800320a: 68f8 ldr r0, [r7, #12] 800320c: f00c fbf2 bl 800f9f4 HAL_TIM_PWM_Stop (htim, channel2); 8003210: 79bb ldrb r3, [r7, #6] 8003212: 4619 mov r1, r3 8003214: 68f8 ldr r0, [r7, #12] 8003216: f00c fbed bl 800f9f4 osTimerStop (motorTimerHandle); 800321a: 6a38 ldr r0, [r7, #32] 800321c: f011 f8d2 bl 80143c4 motorStatus = 0; 8003220: 2300 movs r3, #0 8003222: 617b str r3, [r7, #20] 8003224: e05f b.n 80032e6 } else if (motorTimerPeriod == -1) { 8003226: 6abb ldr r3, [r7, #40] @ 0x28 8003228: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800322c: d15b bne.n 80032e6 if (motorPWMPulse > 0) { 800322e: 6a7b ldr r3, [r7, #36] @ 0x24 8003230: 2b00 cmp r3, #0 8003232: dd2c ble.n 800328e // Forward if (switchLimiterUpStat == 0) { 8003234: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 8003238: 2b00 cmp r3, #0 800323a: d11d bne.n 8003278 setMotorState = Forward; 800323c: 2301 movs r3, #1 800323e: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 8003240: 79f9 ldrb r1, [r7, #7] 8003242: 79b8 ldrb r0, [r7, #6] 8003244: 6a7b ldr r3, [r7, #36] @ 0x24 8003246: ea83 72e3 eor.w r2, r3, r3, asr #31 800324a: eba2 72e3 sub.w r2, r2, r3, asr #31 800324e: 4613 mov r3, r2 8003250: 009b lsls r3, r3, #2 8003252: 4413 add r3, r2 8003254: 005b lsls r3, r3, #1 8003256: 9301 str r3, [sp, #4] 8003258: 7cfb ldrb r3, [r7, #19] 800325a: 9300 str r3, [sp, #0] 800325c: 4603 mov r3, r0 800325e: 460a mov r2, r1 8003260: 68b9 ldr r1, [r7, #8] 8003262: 68f8 ldr r0, [r7, #12] 8003264: f000 f845 bl 80032f2 HAL_TIM_PWM_Start (htim, channel1); 8003268: 79fb ldrb r3, [r7, #7] 800326a: 4619 mov r1, r3 800326c: 68f8 ldr r0, [r7, #12] 800326e: f00c fab3 bl 800f7d8 motorStatus = 1; 8003272: 2301 movs r3, #1 8003274: 617b str r3, [r7, #20] 8003276: e004 b.n 8003282 } else { HAL_TIM_PWM_Stop (htim, channel1); 8003278: 79fb ldrb r3, [r7, #7] 800327a: 4619 mov r1, r3 800327c: 68f8 ldr r0, [r7, #12] 800327e: f00c fbb9 bl 800f9f4 } HAL_TIM_PWM_Stop (htim, channel2); 8003282: 79bb ldrb r3, [r7, #6] 8003284: 4619 mov r1, r3 8003286: 68f8 ldr r0, [r7, #12] 8003288: f00c fbb4 bl 800f9f4 800328c: e02b b.n 80032e6 } else { // Reverse if (switchLimiterDownStat == 0) { 800328e: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 8003292: 2b00 cmp r3, #0 8003294: d11d bne.n 80032d2 setMotorState = Reverse; 8003296: 2302 movs r3, #2 8003298: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 800329a: 79f9 ldrb r1, [r7, #7] 800329c: 79b8 ldrb r0, [r7, #6] 800329e: 6a7b ldr r3, [r7, #36] @ 0x24 80032a0: ea83 72e3 eor.w r2, r3, r3, asr #31 80032a4: eba2 72e3 sub.w r2, r2, r3, asr #31 80032a8: 4613 mov r3, r2 80032aa: 009b lsls r3, r3, #2 80032ac: 4413 add r3, r2 80032ae: 005b lsls r3, r3, #1 80032b0: 9301 str r3, [sp, #4] 80032b2: 7cfb ldrb r3, [r7, #19] 80032b4: 9300 str r3, [sp, #0] 80032b6: 4603 mov r3, r0 80032b8: 460a mov r2, r1 80032ba: 68b9 ldr r1, [r7, #8] 80032bc: 68f8 ldr r0, [r7, #12] 80032be: f000 f818 bl 80032f2 HAL_TIM_PWM_Start (htim, channel2); 80032c2: 79bb ldrb r3, [r7, #6] 80032c4: 4619 mov r1, r3 80032c6: 68f8 ldr r0, [r7, #12] 80032c8: f00c fa86 bl 800f7d8 motorStatus = 1; 80032cc: 2301 movs r3, #1 80032ce: 617b str r3, [r7, #20] 80032d0: e004 b.n 80032dc } else { HAL_TIM_PWM_Stop (htim, channel2); 80032d2: 79bb ldrb r3, [r7, #6] 80032d4: 4619 mov r1, r3 80032d6: 68f8 ldr r0, [r7, #12] 80032d8: f00c fb8c bl 800f9f4 } HAL_TIM_PWM_Stop (htim, channel1); 80032dc: 79fb ldrb r3, [r7, #7] 80032de: 4619 mov r1, r3 80032e0: 68f8 ldr r0, [r7, #12] 80032e2: f00c fb87 bl 800f9f4 } } return motorStatus; 80032e6: 697b ldr r3, [r7, #20] 80032e8: b2db uxtb r3, r3 } 80032ea: 4618 mov r0, r3 80032ec: 3718 adds r7, #24 80032ee: 46bd mov sp, r7 80032f0: bd80 pop {r7, pc} 080032f2 : void MotorAction (TIM_HandleTypeDef* tim, TIM_OC_InitTypeDef* timerConf, uint32_t channel1, uint32_t channel2, MotorDriverState setState, uint32_t pulse) { 80032f2: b580 push {r7, lr} 80032f4: b084 sub sp, #16 80032f6: af00 add r7, sp, #0 80032f8: 60f8 str r0, [r7, #12] 80032fa: 60b9 str r1, [r7, #8] 80032fc: 607a str r2, [r7, #4] 80032fe: 603b str r3, [r7, #0] timerConf->Pulse = pulse; 8003300: 68bb ldr r3, [r7, #8] 8003302: 69fa ldr r2, [r7, #28] 8003304: 605a str r2, [r3, #4] switch (setState) { 8003306: 7e3b ldrb r3, [r7, #24] 8003308: 2b02 cmp r3, #2 800330a: dc02 bgt.n 8003312 800330c: 2b00 cmp r3, #0 800330e: da03 bge.n 8003318 8003310: e038 b.n 8003384 8003312: 2b03 cmp r3, #3 8003314: d01b beq.n 800334e 8003316: e035 b.n 8003384 case Forward: case Reverse: case HiZ: timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8003318: 68bb ldr r3, [r7, #8] 800331a: 2200 movs r2, #0 800331c: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 800331e: 687a ldr r2, [r7, #4] 8003320: 68b9 ldr r1, [r7, #8] 8003322: 68f8 ldr r0, [r7, #12] 8003324: f00c ff52 bl 80101cc 8003328: 4603 mov r3, r0 800332a: 2b00 cmp r3, #0 800332c: d001 beq.n 8003332 Error_Handler (); 800332e: f7fe fdcd bl 8001ecc } timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8003332: 68bb ldr r3, [r7, #8] 8003334: 2200 movs r2, #0 8003336: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 8003338: 683a ldr r2, [r7, #0] 800333a: 68b9 ldr r1, [r7, #8] 800333c: 68f8 ldr r0, [r7, #12] 800333e: f00c ff45 bl 80101cc 8003342: 4603 mov r3, r0 8003344: 2b00 cmp r3, #0 8003346: d038 beq.n 80033ba Error_Handler (); 8003348: f7fe fdc0 bl 8001ecc } break; 800334c: e035 b.n 80033ba case Brake: timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 800334e: 68bb ldr r3, [r7, #8] 8003350: 2202 movs r2, #2 8003352: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 8003354: 687a ldr r2, [r7, #4] 8003356: 68b9 ldr r1, [r7, #8] 8003358: 68f8 ldr r0, [r7, #12] 800335a: f00c ff37 bl 80101cc 800335e: 4603 mov r3, r0 8003360: 2b00 cmp r3, #0 8003362: d001 beq.n 8003368 Error_Handler (); 8003364: f7fe fdb2 bl 8001ecc } timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 8003368: 68bb ldr r3, [r7, #8] 800336a: 2202 movs r2, #2 800336c: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 800336e: 683a ldr r2, [r7, #0] 8003370: 68b9 ldr r1, [r7, #8] 8003372: 68f8 ldr r0, [r7, #12] 8003374: f00c ff2a bl 80101cc 8003378: 4603 mov r3, r0 800337a: 2b00 cmp r3, #0 800337c: d01f beq.n 80033be Error_Handler (); 800337e: f7fe fda5 bl 8001ecc } break; 8003382: e01c b.n 80033be default: timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8003384: 68bb ldr r3, [r7, #8] 8003386: 2200 movs r2, #0 8003388: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 800338a: 687a ldr r2, [r7, #4] 800338c: 68b9 ldr r1, [r7, #8] 800338e: 68f8 ldr r0, [r7, #12] 8003390: f00c ff1c bl 80101cc 8003394: 4603 mov r3, r0 8003396: 2b00 cmp r3, #0 8003398: d001 beq.n 800339e Error_Handler (); 800339a: f7fe fd97 bl 8001ecc } timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 800339e: 68bb ldr r3, [r7, #8] 80033a0: 2200 movs r2, #0 80033a2: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80033a4: 683a ldr r2, [r7, #0] 80033a6: 68b9 ldr r1, [r7, #8] 80033a8: 68f8 ldr r0, [r7, #12] 80033aa: f00c ff0f bl 80101cc 80033ae: 4603 mov r3, r0 80033b0: 2b00 cmp r3, #0 80033b2: d006 beq.n 80033c2 Error_Handler (); 80033b4: f7fe fd8a bl 8001ecc } break; 80033b8: e003 b.n 80033c2 break; 80033ba: bf00 nop 80033bc: e002 b.n 80033c4 break; 80033be: bf00 nop 80033c0: e000 b.n 80033c4 break; 80033c2: bf00 nop } } 80033c4: bf00 nop 80033c6: 3710 adds r7, #16 80033c8: 46bd mov sp, r7 80033ca: bd80 pop {r7, pc} 080033cc : extern osTimerId_t motorXTimerHandle; extern osTimerId_t motorYTimerHandle; extern TIM_HandleTypeDef htim3; extern TIM_OC_InitTypeDef motorXYTimerConfigOC; void PositionControlTaskInit (void) { 80033cc: b580 push {r7, lr} 80033ce: b08a sub sp, #40 @ 0x28 80033d0: af00 add r7, sp, #0 positionSettingMutex = osMutexNew (NULL); 80033d2: 2000 movs r0, #0 80033d4: f011 f82d bl 8014432 80033d8: 4603 mov r3, r0 80033da: 4a42 ldr r2, [pc, #264] @ (80034e4 ) 80033dc: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttrPositionControlTask = { 0 }; 80033de: 1d3b adds r3, r7, #4 80033e0: 2224 movs r2, #36 @ 0x24 80033e2: 2100 movs r1, #0 80033e4: 4618 mov r0, r3 80033e6: f014 ffd7 bl 8018398 osThreadAttrPositionControlTask.stack_size = configMINIMAL_STACK_SIZE * 2; 80033ea: f44f 6380 mov.w r3, #1024 @ 0x400 80033ee: 61bb str r3, [r7, #24] osThreadAttrPositionControlTask.priority = (osPriority_t)osPriorityNormal; 80033f0: 2318 movs r3, #24 80033f2: 61fb str r3, [r7, #28] positionXControlTaskInitArg.channel1 = TIM_CHANNEL_1; 80033f4: 4b3c ldr r3, [pc, #240] @ (80034e8 ) 80033f6: 2200 movs r2, #0 80033f8: 721a strb r2, [r3, #8] positionXControlTaskInitArg.channel2 = TIM_CHANNEL_2; 80033fa: 4b3b ldr r3, [pc, #236] @ (80034e8 ) 80033fc: 2204 movs r2, #4 80033fe: 725a strb r2, [r3, #9] positionXControlTaskInitArg.htim = &htim3; 8003400: 4b39 ldr r3, [pc, #228] @ (80034e8 ) 8003402: 4a3a ldr r2, [pc, #232] @ (80034ec ) 8003404: 601a str r2, [r3, #0] positionXControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC; 8003406: 4b38 ldr r3, [pc, #224] @ (80034e8 ) 8003408: 4a39 ldr r2, [pc, #228] @ (80034f0 ) 800340a: 605a str r2, [r3, #4] positionXControlTaskInitArg.motorTimerHandle = motorXTimerHandle; 800340c: 4b39 ldr r3, [pc, #228] @ (80034f4 ) 800340e: 681b ldr r3, [r3, #0] 8003410: 4a35 ldr r2, [pc, #212] @ (80034e8 ) 8003412: 60d3 str r3, [r2, #12] positionXControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 8003414: 2200 movs r2, #0 8003416: 2104 movs r1, #4 8003418: 2010 movs r0, #16 800341a: f011 f918 bl 801464e 800341e: 4603 mov r3, r0 8003420: 4a31 ldr r2, [pc, #196] @ (80034e8 ) 8003422: 6113 str r3, [r2, #16] positionXControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitXSwitchCenter); 8003424: 4b30 ldr r3, [pc, #192] @ (80034e8 ) 8003426: 4a34 ldr r2, [pc, #208] @ (80034f8 ) 8003428: 61da str r2, [r3, #28] positionXControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitXSwitchUp); 800342a: 4b2f ldr r3, [pc, #188] @ (80034e8 ) 800342c: 4a33 ldr r2, [pc, #204] @ (80034fc ) 800342e: 615a str r2, [r3, #20] positionXControlTaskInitArg.switchLimiterDownStat = &(sensorsInfo.limitXSwitchDown); 8003430: 4b2d ldr r3, [pc, #180] @ (80034e8 ) 8003432: 4a33 ldr r2, [pc, #204] @ (8003500 ) 8003434: 619a str r2, [r3, #24] positionXControlTaskInitArg.currentPosition = &(sensorsInfo.currentXPosition); 8003436: 4b2c ldr r3, [pc, #176] @ (80034e8 ) 8003438: 4a32 ldr r2, [pc, #200] @ (8003504 ) 800343a: 621a str r2, [r3, #32] positionXControlTaskInitArg.motorStatus = &(sensorsInfo.motorXStatus); 800343c: 4b2a ldr r3, [pc, #168] @ (80034e8 ) 800343e: 4a32 ldr r2, [pc, #200] @ (8003508 ) 8003440: 629a str r2, [r3, #40] @ 0x28 positionXControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorXPeakCurrent); 8003442: 4b29 ldr r3, [pc, #164] @ (80034e8 ) 8003444: 4a31 ldr r2, [pc, #196] @ (800350c ) 8003446: 62da str r2, [r3, #44] @ 0x2c positionXControlTaskInitArg.positionSetting = &positionXSetting; 8003448: 4b27 ldr r3, [pc, #156] @ (80034e8 ) 800344a: 4a31 ldr r2, [pc, #196] @ (8003510 ) 800344c: 625a str r2, [r3, #36] @ 0x24 positionXControlTaskInitArg.axe = 'X'; 800344e: 4b26 ldr r3, [pc, #152] @ (80034e8 ) 8003450: 2258 movs r2, #88 @ 0x58 8003452: f883 2030 strb.w r2, [r3, #48] @ 0x30 positionYControlTaskInitArg.channel1 = TIM_CHANNEL_3; 8003456: 4b2f ldr r3, [pc, #188] @ (8003514 ) 8003458: 2208 movs r2, #8 800345a: 721a strb r2, [r3, #8] positionYControlTaskInitArg.channel2 = TIM_CHANNEL_4; 800345c: 4b2d ldr r3, [pc, #180] @ (8003514 ) 800345e: 220c movs r2, #12 8003460: 725a strb r2, [r3, #9] positionYControlTaskInitArg.htim = &htim3; 8003462: 4b2c ldr r3, [pc, #176] @ (8003514 ) 8003464: 4a21 ldr r2, [pc, #132] @ (80034ec ) 8003466: 601a str r2, [r3, #0] positionYControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC; 8003468: 4b2a ldr r3, [pc, #168] @ (8003514 ) 800346a: 4a21 ldr r2, [pc, #132] @ (80034f0 ) 800346c: 605a str r2, [r3, #4] positionYControlTaskInitArg.motorTimerHandle = motorYTimerHandle; 800346e: 4b2a ldr r3, [pc, #168] @ (8003518 ) 8003470: 681b ldr r3, [r3, #0] 8003472: 4a28 ldr r2, [pc, #160] @ (8003514 ) 8003474: 60d3 str r3, [r2, #12] positionYControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 8003476: 2200 movs r2, #0 8003478: 2104 movs r1, #4 800347a: 2010 movs r0, #16 800347c: f011 f8e7 bl 801464e 8003480: 4603 mov r3, r0 8003482: 4a24 ldr r2, [pc, #144] @ (8003514 ) 8003484: 6113 str r3, [r2, #16] positionYControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitYSwitchCenter); 8003486: 4b23 ldr r3, [pc, #140] @ (8003514 ) 8003488: 4a24 ldr r2, [pc, #144] @ (800351c ) 800348a: 61da str r2, [r3, #28] positionYControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitYSwitchUp); 800348c: 4b21 ldr r3, [pc, #132] @ (8003514 ) 800348e: 4a24 ldr r2, [pc, #144] @ (8003520 ) 8003490: 615a str r2, [r3, #20] positionYControlTaskInitArg.switchLimiterDownStat = &(sensorsInfo.limitYSwitchDown); 8003492: 4b20 ldr r3, [pc, #128] @ (8003514 ) 8003494: 4a23 ldr r2, [pc, #140] @ (8003524 ) 8003496: 619a str r2, [r3, #24] positionYControlTaskInitArg.currentPosition = &(sensorsInfo.currentYPosition); 8003498: 4b1e ldr r3, [pc, #120] @ (8003514 ) 800349a: 4a23 ldr r2, [pc, #140] @ (8003528 ) 800349c: 621a str r2, [r3, #32] positionYControlTaskInitArg.motorStatus = &(sensorsInfo.motorYStatus); 800349e: 4b1d ldr r3, [pc, #116] @ (8003514 ) 80034a0: 4a22 ldr r2, [pc, #136] @ (800352c ) 80034a2: 629a str r2, [r3, #40] @ 0x28 positionYControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorYPeakCurrent); 80034a4: 4b1b ldr r3, [pc, #108] @ (8003514 ) 80034a6: 4a22 ldr r2, [pc, #136] @ (8003530 ) 80034a8: 62da str r2, [r3, #44] @ 0x2c positionXControlTaskInitArg.positionSetting = &positionYSetting; 80034aa: 4b0f ldr r3, [pc, #60] @ (80034e8 ) 80034ac: 4a21 ldr r2, [pc, #132] @ (8003534 ) 80034ae: 625a str r2, [r3, #36] @ 0x24 positionYControlTaskInitArg.axe = 'Y'; 80034b0: 4b18 ldr r3, [pc, #96] @ (8003514 ) 80034b2: 2259 movs r2, #89 @ 0x59 80034b4: f883 2030 strb.w r2, [r3, #48] @ 0x30 positionXControlTaskHandle = osThreadNew (PositionControlTask, &positionXControlTaskInitArg, &osThreadAttrPositionControlTask); 80034b8: 1d3b adds r3, r7, #4 80034ba: 461a mov r2, r3 80034bc: 490a ldr r1, [pc, #40] @ (80034e8 ) 80034be: 481e ldr r0, [pc, #120] @ (8003538 ) 80034c0: f010 fe12 bl 80140e8 80034c4: 4603 mov r3, r0 80034c6: 4a1d ldr r2, [pc, #116] @ (800353c ) 80034c8: 6013 str r3, [r2, #0] positionYControlTaskHandle = osThreadNew (PositionControlTask, &positionYControlTaskInitArg, &osThreadAttrPositionControlTask); 80034ca: 1d3b adds r3, r7, #4 80034cc: 461a mov r2, r3 80034ce: 4911 ldr r1, [pc, #68] @ (8003514 ) 80034d0: 4819 ldr r0, [pc, #100] @ (8003538 ) 80034d2: f010 fe09 bl 80140e8 80034d6: 4603 mov r3, r0 80034d8: 4a19 ldr r2, [pc, #100] @ (8003540 ) 80034da: 6013 str r3, [r2, #0] } 80034dc: bf00 nop 80034de: 3728 adds r7, #40 @ 0x28 80034e0: 46bd mov sp, r7 80034e2: bd80 pop {r7, pc} 80034e4: 240008a8 .word 0x240008a8 80034e8: 240008b4 .word 0x240008b4 80034ec: 240004d4 .word 0x240004d4 80034f0: 240007c0 .word 0x240007c0 80034f4: 24000744 .word 0x24000744 80034f8: 2400088a .word 0x2400088a 80034fc: 24000888 .word 0x24000888 8003500: 24000889 .word 0x24000889 8003504: 24000890 .word 0x24000890 8003508: 24000874 .word 0x24000874 800350c: 24000880 .word 0x24000880 8003510: 240008a0 .word 0x240008a0 8003514: 240008e8 .word 0x240008e8 8003518: 24000774 .word 0x24000774 800351c: 2400088d .word 0x2400088d 8003520: 2400088b .word 0x2400088b 8003524: 2400088c .word 0x2400088c 8003528: 24000894 .word 0x24000894 800352c: 24000875 .word 0x24000875 8003530: 24000884 .word 0x24000884 8003534: 240008a4 .word 0x240008a4 8003538: 08003545 .word 0x08003545 800353c: 240008ac .word 0x240008ac 8003540: 240008b0 .word 0x240008b0 08003544 : void PositionControlTask (void* argument) { 8003544: b5f0 push {r4, r5, r6, r7, lr} 8003546: b097 sub sp, #92 @ 0x5c 8003548: af06 add r7, sp, #24 800354a: 6078 str r0, [r7, #4] const int32_t PositionControlTaskTimeOut = 100; 800354c: 2364 movs r3, #100 @ 0x64 800354e: 623b str r3, [r7, #32] PositionControlTaskInitArg* posCtrlTaskArg = (PositionControlTaskInitArg*)argument; 8003550: 687b ldr r3, [r7, #4] 8003552: 61fb str r3, [r7, #28] PositionControlTaskData posCtrlData = { 0 }; 8003554: f04f 0300 mov.w r3, #0 8003558: 60bb str r3, [r7, #8] uint32_t motorStatus = 0; 800355a: 2300 movs r3, #0 800355c: 61bb str r3, [r7, #24] osStatus_t queueSatus; int32_t pwmValue = MOTOR_START_STOP_PWM_VALUE; 800355e: 233c movs r3, #60 @ 0x3c 8003560: 63fb str r3, [r7, #60] @ 0x3c int32_t sign = 0; 8003562: 2300 movs r3, #0 8003564: 63bb str r3, [r7, #56] @ 0x38 MovementPhases movementPhase = idlePhase; 8003566: 2300 movs r3, #0 8003568: f887 3037 strb.w r3, [r7, #55] @ 0x37 float startPosition = 0; 800356c: f04f 0300 mov.w r3, #0 8003570: 633b str r3, [r7, #48] @ 0x30 float prevPosition = 0; 8003572: f04f 0300 mov.w r3, #0 8003576: 62fb str r3, [r7, #44] @ 0x2c int32_t timeLeftMS = 0; 8003578: 2300 movs r3, #0 800357a: 62bb str r3, [r7, #40] @ 0x28 int32_t moveCmdTimeoutCounter = 0; 800357c: 2300 movs r3, #0 800357e: 627b str r3, [r7, #36] @ 0x24 while (pdTRUE) { queueSatus = osMessageQueueGet (posCtrlTaskArg->positionSettingQueue, &posCtrlData, 0, pdMS_TO_TICKS (PositionControlTaskTimeOut)); 8003580: 69fb ldr r3, [r7, #28] 8003582: 6918 ldr r0, [r3, #16] 8003584: 6a3b ldr r3, [r7, #32] 8003586: f44f 727a mov.w r2, #1000 @ 0x3e8 800358a: fb02 f303 mul.w r3, r2, r3 800358e: 4aa1 ldr r2, [pc, #644] @ (8003814 ) 8003590: fba2 2303 umull r2, r3, r2, r3 8003594: 099b lsrs r3, r3, #6 8003596: f107 0108 add.w r1, r7, #8 800359a: 2200 movs r2, #0 800359c: f011 f92a bl 80147f4 80035a0: 6178 str r0, [r7, #20] if (queueSatus == osOK) { 80035a2: 697b ldr r3, [r7, #20] 80035a4: 2b00 cmp r3, #0 80035a6: d14a bne.n 800363e if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80035a8: 4b9b ldr r3, [pc, #620] @ (8003818 ) 80035aa: 681b ldr r3, [r3, #0] 80035ac: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80035b0: 4618 mov r0, r3 80035b2: f010 ffc4 bl 801453e 80035b6: 4603 mov r3, r0 80035b8: 2b00 cmp r3, #0 80035ba: d1e1 bne.n 8003580 float posDiff = posCtrlData.positionSettingValue - *posCtrlTaskArg->currentPosition; 80035bc: ed97 7a02 vldr s14, [r7, #8] 80035c0: 69fb ldr r3, [r7, #28] 80035c2: 6a1b ldr r3, [r3, #32] 80035c4: edd3 7a00 vldr s15, [r3] 80035c8: ee77 7a67 vsub.f32 s15, s14, s15 80035cc: edc7 7a03 vstr s15, [r7, #12] if (posDiff != 0) { 80035d0: edd7 7a03 vldr s15, [r7, #12] 80035d4: eef5 7a40 vcmp.f32 s15, #0.0 80035d8: eef1 fa10 vmrs APSR_nzcv, fpscr 80035dc: d016 beq.n 800360c sign = posDiff > 0 ? 1 : -1; 80035de: edd7 7a03 vldr s15, [r7, #12] 80035e2: eef5 7ac0 vcmpe.f32 s15, #0.0 80035e6: eef1 fa10 vmrs APSR_nzcv, fpscr 80035ea: dd01 ble.n 80035f0 80035ec: 2301 movs r3, #1 80035ee: e001 b.n 80035f4 80035f0: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80035f4: 63bb str r3, [r7, #56] @ 0x38 startPosition = *posCtrlTaskArg->currentPosition; 80035f6: 69fb ldr r3, [r7, #28] 80035f8: 6a1b ldr r3, [r3, #32] 80035fa: 681b ldr r3, [r3, #0] 80035fc: 633b str r3, [r7, #48] @ 0x30 movementPhase = startPhase; 80035fe: 2301 movs r3, #1 8003600: f887 3037 strb.w r3, [r7, #55] @ 0x37 moveCmdTimeoutCounter = 0; 8003604: 2300 movs r3, #0 8003606: 627b str r3, [r7, #36] @ 0x24 timeLeftMS = 0; 8003608: 2300 movs r3, #0 800360a: 62bb str r3, [r7, #40] @ 0x28 #ifdef DBG_POSITION printf ("Axe %c start phase\n", posCtrlTaskArg->axe); #endif } osMutexRelease (sensorsInfoMutex); 800360c: 4b82 ldr r3, [pc, #520] @ (8003818 ) 800360e: 681b ldr r3, [r3, #0] 8003610: 4618 mov r0, r3 8003612: f010 ffdf bl 80145d4 if (osMutexAcquire (positionSettingMutex, osWaitForever) == osOK) { 8003616: 4b81 ldr r3, [pc, #516] @ (800381c ) 8003618: 681b ldr r3, [r3, #0] 800361a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800361e: 4618 mov r0, r3 8003620: f010 ff8d bl 801453e 8003624: 4603 mov r3, r0 8003626: 2b00 cmp r3, #0 8003628: d1aa bne.n 8003580 *positionXControlTaskInitArg.positionSetting = posCtrlData.positionSettingValue; 800362a: 4b7d ldr r3, [pc, #500] @ (8003820 ) 800362c: 6a5b ldr r3, [r3, #36] @ 0x24 800362e: 68ba ldr r2, [r7, #8] 8003630: 601a str r2, [r3, #0] osMutexRelease (positionSettingMutex); 8003632: 4b7a ldr r3, [pc, #488] @ (800381c ) 8003634: 681b ldr r3, [r3, #0] 8003636: 4618 mov r0, r3 8003638: f010 ffcc bl 80145d4 800363c: e7a0 b.n 8003580 } } } else if (queueSatus == osErrorTimeout) { 800363e: 697b ldr r3, [r7, #20] 8003640: f113 0f02 cmn.w r3, #2 8003644: d19c bne.n 8003580 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8003646: 4b74 ldr r3, [pc, #464] @ (8003818 ) 8003648: 681b ldr r3, [r3, #0] 800364a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800364e: 4618 mov r0, r3 8003650: f010 ff75 bl 801453e 8003654: 4603 mov r3, r0 8003656: 2b00 cmp r3, #0 8003658: d192 bne.n 8003580 if (((*posCtrlTaskArg->motorStatus != 0) && (movementPhase != idlePhase)) || (movementPhase == startPhase) ) { 800365a: 69fb ldr r3, [r7, #28] 800365c: 6a9b ldr r3, [r3, #40] @ 0x28 800365e: 781b ldrb r3, [r3, #0] 8003660: 2b00 cmp r3, #0 8003662: d003 beq.n 800366c 8003664: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 8003668: 2b00 cmp r3, #0 800366a: d104 bne.n 8003676 800366c: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 8003670: 2b01 cmp r3, #1 8003672: f040 81c4 bne.w 80039fe if (((*posCtrlTaskArg->switchLimiterDownStat == 1) && (*posCtrlTaskArg->switchLimiterUpStat == 1)) || 8003676: 69fb ldr r3, [r7, #28] 8003678: 699b ldr r3, [r3, #24] 800367a: 781b ldrb r3, [r3, #0] 800367c: 2b01 cmp r3, #1 800367e: d104 bne.n 800368a 8003680: 69fb ldr r3, [r7, #28] 8003682: 695b ldr r3, [r3, #20] 8003684: 781b ldrb r3, [r3, #0] 8003686: 2b01 cmp r3, #1 8003688: d009 beq.n 800369e ((*posCtrlTaskArg->switchLimiterUpStat == 1) && (*posCtrlTaskArg->switchLimiterCenterStat == 1))) { 800368a: 69fb ldr r3, [r7, #28] 800368c: 695b ldr r3, [r3, #20] 800368e: 781b ldrb r3, [r3, #0] if (((*posCtrlTaskArg->switchLimiterDownStat == 1) && (*posCtrlTaskArg->switchLimiterUpStat == 1)) || 8003690: 2b01 cmp r3, #1 8003692: d12a bne.n 80036ea ((*posCtrlTaskArg->switchLimiterUpStat == 1) && (*posCtrlTaskArg->switchLimiterCenterStat == 1))) { 8003694: 69fb ldr r3, [r7, #28] 8003696: 69db ldr r3, [r3, #28] 8003698: 781b ldrb r3, [r3, #0] 800369a: 2b01 cmp r3, #1 800369c: d125 bne.n 80036ea movementPhase = idlePhase; 800369e: 2300 movs r3, #0 80036a0: f887 3037 strb.w r3, [r7, #55] @ 0x37 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 80036a4: 69fb ldr r3, [r7, #28] 80036a6: 6818 ldr r0, [r3, #0] 80036a8: 69fb ldr r3, [r7, #28] 80036aa: 685c ldr r4, [r3, #4] 80036ac: 69fb ldr r3, [r7, #28] 80036ae: 7a1d ldrb r5, [r3, #8] 80036b0: 69fb ldr r3, [r7, #28] 80036b2: 7a5e ldrb r6, [r3, #9] 80036b4: 69fb ldr r3, [r7, #28] 80036b6: 68db ldr r3, [r3, #12] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80036b8: 69fa ldr r2, [r7, #28] 80036ba: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 80036bc: 7812 ldrb r2, [r2, #0] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80036be: 69f9 ldr r1, [r7, #28] 80036c0: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 80036c2: 7809 ldrb r1, [r1, #0] 80036c4: 9104 str r1, [sp, #16] 80036c6: 9203 str r2, [sp, #12] 80036c8: 2200 movs r2, #0 80036ca: 9202 str r2, [sp, #8] 80036cc: 2200 movs r2, #0 80036ce: 9201 str r2, [sp, #4] 80036d0: 9300 str r3, [sp, #0] 80036d2: 4633 mov r3, r6 80036d4: 462a mov r2, r5 80036d6: 4621 mov r1, r4 80036d8: f7ff fcd2 bl 8003080 80036dc: 4603 mov r3, r0 80036de: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 80036e0: 69fb ldr r3, [r7, #28] 80036e2: 6a9b ldr r3, [r3, #40] @ 0x28 80036e4: 69ba ldr r2, [r7, #24] 80036e6: b2d2 uxtb r2, r2 80036e8: 701a strb r2, [r3, #0] printf ("Axe %c limiters wrong state - idle phase\n", posCtrlTaskArg->axe); #endif } timeLeftMS += PositionControlTaskTimeOut; 80036ea: 6aba ldr r2, [r7, #40] @ 0x28 80036ec: 6a3b ldr r3, [r7, #32] 80036ee: 4413 add r3, r2 80036f0: 62bb str r3, [r7, #40] @ 0x28 if (prevPosition == *posCtrlTaskArg->currentPosition) { 80036f2: 69fb ldr r3, [r7, #28] 80036f4: 6a1b ldr r3, [r3, #32] 80036f6: edd3 7a00 vldr s15, [r3] 80036fa: ed97 7a0b vldr s14, [r7, #44] @ 0x2c 80036fe: eeb4 7a67 vcmp.f32 s14, s15 8003702: eef1 fa10 vmrs APSR_nzcv, fpscr 8003706: d104 bne.n 8003712 moveCmdTimeoutCounter += PositionControlTaskTimeOut; 8003708: 6a7a ldr r2, [r7, #36] @ 0x24 800370a: 6a3b ldr r3, [r7, #32] 800370c: 4413 add r3, r2 800370e: 627b str r3, [r7, #36] @ 0x24 8003710: e001 b.n 8003716 } else { moveCmdTimeoutCounter = 0; 8003712: 2300 movs r3, #0 8003714: 627b str r3, [r7, #36] @ 0x24 } prevPosition = *posCtrlTaskArg->currentPosition; 8003716: 69fb ldr r3, [r7, #28] 8003718: 6a1b ldr r3, [r3, #32] 800371a: 681b ldr r3, [r3, #0] 800371c: 62fb str r3, [r7, #44] @ 0x2c if (moveCmdTimeoutCounter > NO_MOVE_TIMEOUT_MS) { 800371e: 6a7b ldr r3, [r7, #36] @ 0x24 8003720: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8003724: dd25 ble.n 8003772 movementPhase = idlePhase; 8003726: 2300 movs r3, #0 8003728: f887 3037 strb.w r3, [r7, #55] @ 0x37 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 800372c: 69fb ldr r3, [r7, #28] 800372e: 6818 ldr r0, [r3, #0] 8003730: 69fb ldr r3, [r7, #28] 8003732: 685c ldr r4, [r3, #4] 8003734: 69fb ldr r3, [r7, #28] 8003736: 7a1d ldrb r5, [r3, #8] 8003738: 69fb ldr r3, [r7, #28] 800373a: 7a5e ldrb r6, [r3, #9] 800373c: 69fb ldr r3, [r7, #28] 800373e: 68db ldr r3, [r3, #12] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003740: 69fa ldr r2, [r7, #28] 8003742: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 8003744: 7812 ldrb r2, [r2, #0] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003746: 69f9 ldr r1, [r7, #28] 8003748: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 800374a: 7809 ldrb r1, [r1, #0] 800374c: 9104 str r1, [sp, #16] 800374e: 9203 str r2, [sp, #12] 8003750: 2200 movs r2, #0 8003752: 9202 str r2, [sp, #8] 8003754: 2200 movs r2, #0 8003756: 9201 str r2, [sp, #4] 8003758: 9300 str r3, [sp, #0] 800375a: 4633 mov r3, r6 800375c: 462a mov r2, r5 800375e: 4621 mov r1, r4 8003760: f7ff fc8e bl 8003080 8003764: 4603 mov r3, r0 8003766: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 8003768: 69fb ldr r3, [r7, #28] 800376a: 6a9b ldr r3, [r3, #40] @ 0x28 800376c: 69ba ldr r2, [r7, #24] 800376e: b2d2 uxtb r2, r2 8003770: 701a strb r2, [r3, #0] #ifdef DBG_POSITION printf ("Axe %c no movement idle phase\n", posCtrlTaskArg->axe); #endif } switch (movementPhase) { 8003772: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 8003776: 3b01 subs r3, #1 8003778: 2b04 cmp r3, #4 800377a: f200 8138 bhi.w 80039ee 800377e: a201 add r2, pc, #4 @ (adr r2, 8003784 ) 8003780: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003784: 08003799 .word 0x08003799 8003788: 08003825 .word 0x08003825 800378c: 080038af .word 0x080038af 8003790: 080038fd .word 0x080038fd 8003794: 0800395f .word 0x0800395f case startPhase: motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003798: 69fb ldr r3, [r7, #28] 800379a: 681c ldr r4, [r3, #0] 800379c: 69fb ldr r3, [r7, #28] 800379e: 685d ldr r5, [r3, #4] 80037a0: 69fb ldr r3, [r7, #28] 80037a2: 7a1e ldrb r6, [r3, #8] 80037a4: 69fb ldr r3, [r7, #28] 80037a6: f893 c009 ldrb.w ip, [r3, #9] 80037aa: 69fb ldr r3, [r7, #28] 80037ac: 68db ldr r3, [r3, #12] 80037ae: 6bba ldr r2, [r7, #56] @ 0x38 80037b0: 6bf9 ldr r1, [r7, #60] @ 0x3c 80037b2: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80037b6: 69f9 ldr r1, [r7, #28] 80037b8: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80037ba: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80037bc: 69f8 ldr r0, [r7, #28] 80037be: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80037c0: 7800 ldrb r0, [r0, #0] 80037c2: 9004 str r0, [sp, #16] 80037c4: 9103 str r1, [sp, #12] 80037c6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80037ca: 9102 str r1, [sp, #8] 80037cc: 9201 str r2, [sp, #4] 80037ce: 9300 str r3, [sp, #0] 80037d0: 4663 mov r3, ip 80037d2: 4632 mov r2, r6 80037d4: 4629 mov r1, r5 80037d6: 4620 mov r0, r4 80037d8: f7ff fc52 bl 8003080 80037dc: 4603 mov r3, r0 80037de: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 80037e0: 69fb ldr r3, [r7, #28] 80037e2: 6a9b ldr r3, [r3, #40] @ 0x28 80037e4: 69ba ldr r2, [r7, #24] 80037e6: b2d2 uxtb r2, r2 80037e8: 701a strb r2, [r3, #0] if (motorStatus == 1) { 80037ea: 69bb ldr r3, [r7, #24] 80037ec: 2b01 cmp r3, #1 80037ee: d10c bne.n 800380a *posCtrlTaskArg->motorPeakCurrent = 0.0; 80037f0: 69fb ldr r3, [r7, #28] 80037f2: 6adb ldr r3, [r3, #44] @ 0x2c 80037f4: f04f 0200 mov.w r2, #0 80037f8: 601a str r2, [r3, #0] #ifdef DBG_POSITION printf ("Axe %c speed up phase\n", posCtrlTaskArg->axe); #endif movementPhase = speedUpPhase; 80037fa: 2302 movs r3, #2 80037fc: f887 3037 strb.w r3, [r7, #55] @ 0x37 timeLeftMS = 0; 8003800: 2300 movs r3, #0 8003802: 62bb str r3, [r7, #40] @ 0x28 moveCmdTimeoutCounter = 0; 8003804: 2300 movs r3, #0 8003806: 627b str r3, [r7, #36] @ 0x24 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); #endif } break; 8003808: e0f8 b.n 80039fc movementPhase = idlePhase; 800380a: 2300 movs r3, #0 800380c: f887 3037 strb.w r3, [r7, #55] @ 0x37 break; 8003810: e0f4 b.n 80039fc 8003812: bf00 nop 8003814: 10624dd3 .word 0x10624dd3 8003818: 2400081c .word 0x2400081c 800381c: 240008a8 .word 0x240008a8 8003820: 240008b4 .word 0x240008b4 case speedUpPhase: if ((abs (*posCtrlTaskArg->currentPosition - startPosition) >= ANGLE_RANGE_FOR_MOTOR_SPEED_LIMIT) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) { 8003824: 69fb ldr r3, [r7, #28] 8003826: 6a1b ldr r3, [r3, #32] 8003828: ed93 7a00 vldr s14, [r3] 800382c: edd7 7a0c vldr s15, [r7, #48] @ 0x30 8003830: ee77 7a67 vsub.f32 s15, s14, s15 8003834: eefd 7ae7 vcvt.s32.f32 s15, s15 8003838: ee17 3a90 vmov r3, s15 800383c: 2b00 cmp r3, #0 800383e: bfb8 it lt 8003840: 425b neglt r3, r3 8003842: 2b04 cmp r3, #4 8003844: dc04 bgt.n 8003850 8003846: 6abb ldr r3, [r7, #40] @ 0x28 8003848: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800384c: f2c0 80d1 blt.w 80039f2 pwmValue = MOTOR_HIGH_SPEED_PWM_VALUE; 8003850: 2364 movs r3, #100 @ 0x64 8003852: 63fb str r3, [r7, #60] @ 0x3c motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003854: 69fb ldr r3, [r7, #28] 8003856: 681c ldr r4, [r3, #0] 8003858: 69fb ldr r3, [r7, #28] 800385a: 685d ldr r5, [r3, #4] 800385c: 69fb ldr r3, [r7, #28] 800385e: 7a1e ldrb r6, [r3, #8] 8003860: 69fb ldr r3, [r7, #28] 8003862: f893 c009 ldrb.w ip, [r3, #9] 8003866: 69fb ldr r3, [r7, #28] 8003868: 68db ldr r3, [r3, #12] 800386a: 6bba ldr r2, [r7, #56] @ 0x38 800386c: 6bf9 ldr r1, [r7, #60] @ 0x3c 800386e: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003872: 69f9 ldr r1, [r7, #28] 8003874: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003876: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003878: 69f8 ldr r0, [r7, #28] 800387a: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 800387c: 7800 ldrb r0, [r0, #0] 800387e: 9004 str r0, [sp, #16] 8003880: 9103 str r1, [sp, #12] 8003882: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003886: 9102 str r1, [sp, #8] 8003888: 9201 str r2, [sp, #4] 800388a: 9300 str r3, [sp, #0] 800388c: 4663 mov r3, ip 800388e: 4632 mov r2, r6 8003890: 4629 mov r1, r5 8003892: 4620 mov r0, r4 8003894: f7ff fbf4 bl 8003080 8003898: 4603 mov r3, r0 800389a: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 800389c: 69fb ldr r3, [r7, #28] 800389e: 6a9b ldr r3, [r3, #40] @ 0x28 80038a0: 69ba ldr r2, [r7, #24] 80038a2: b2d2 uxtb r2, r2 80038a4: 701a strb r2, [r3, #0] movementPhase = movePhase; 80038a6: 2303 movs r3, #3 80038a8: f887 3037 strb.w r3, [r7, #55] @ 0x37 #ifdef DBG_POSITION printf ("Axe %c move phase\n", posCtrlTaskArg->axe); #endif } break; 80038ac: e0a1 b.n 80039f2 case movePhase: if (abs (*posCtrlTaskArg->currentPosition - *posCtrlTaskArg->positionSetting) <= ANGLE_RANGE_FOR_MOTOR_SPEED_LIMIT) { 80038ae: 69fb ldr r3, [r7, #28] 80038b0: 6a1b ldr r3, [r3, #32] 80038b2: ed93 7a00 vldr s14, [r3] 80038b6: 69fb ldr r3, [r7, #28] 80038b8: 6a5b ldr r3, [r3, #36] @ 0x24 80038ba: edd3 7a00 vldr s15, [r3] 80038be: ee77 7a67 vsub.f32 s15, s14, s15 80038c2: eefd 7ae7 vcvt.s32.f32 s15, s15 80038c6: ee17 3a90 vmov r3, s15 80038ca: f113 0f05 cmn.w r3, #5 80038ce: f2c0 8092 blt.w 80039f6 80038d2: 69fb ldr r3, [r7, #28] 80038d4: 6a1b ldr r3, [r3, #32] 80038d6: ed93 7a00 vldr s14, [r3] 80038da: 69fb ldr r3, [r7, #28] 80038dc: 6a5b ldr r3, [r3, #36] @ 0x24 80038de: edd3 7a00 vldr s15, [r3] 80038e2: ee77 7a67 vsub.f32 s15, s14, s15 80038e6: eefd 7ae7 vcvt.s32.f32 s15, s15 80038ea: ee17 3a90 vmov r3, s15 80038ee: 2b05 cmp r3, #5 80038f0: f300 8081 bgt.w 80039f6 movementPhase = slowDownPhase; 80038f4: 2304 movs r3, #4 80038f6: f887 3037 strb.w r3, [r7, #55] @ 0x37 #ifdef DBG_POSITION printf ("Axe %c slow down phase\n", posCtrlTaskArg->axe); #endif } break; 80038fa: e07c b.n 80039f6 case slowDownPhase: pwmValue = MOTOR_START_STOP_PWM_VALUE; 80038fc: 233c movs r3, #60 @ 0x3c 80038fe: 63fb str r3, [r7, #60] @ 0x3c motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003900: 69fb ldr r3, [r7, #28] 8003902: 681c ldr r4, [r3, #0] 8003904: 69fb ldr r3, [r7, #28] 8003906: 685d ldr r5, [r3, #4] 8003908: 69fb ldr r3, [r7, #28] 800390a: 7a1e ldrb r6, [r3, #8] 800390c: 69fb ldr r3, [r7, #28] 800390e: f893 c009 ldrb.w ip, [r3, #9] 8003912: 69fb ldr r3, [r7, #28] 8003914: 68db ldr r3, [r3, #12] 8003916: 6bba ldr r2, [r7, #56] @ 0x38 8003918: 6bf9 ldr r1, [r7, #60] @ 0x3c 800391a: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 800391e: 69f9 ldr r1, [r7, #28] 8003920: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003922: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003924: 69f8 ldr r0, [r7, #28] 8003926: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003928: 7800 ldrb r0, [r0, #0] 800392a: 9004 str r0, [sp, #16] 800392c: 9103 str r1, [sp, #12] 800392e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003932: 9102 str r1, [sp, #8] 8003934: 9201 str r2, [sp, #4] 8003936: 9300 str r3, [sp, #0] 8003938: 4663 mov r3, ip 800393a: 4632 mov r2, r6 800393c: 4629 mov r1, r5 800393e: 4620 mov r0, r4 8003940: f7ff fb9e bl 8003080 8003944: 4603 mov r3, r0 8003946: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 8003948: 69fb ldr r3, [r7, #28] 800394a: 6a9b ldr r3, [r3, #40] @ 0x28 800394c: 69ba ldr r2, [r7, #24] 800394e: b2d2 uxtb r2, r2 8003950: 701a strb r2, [r3, #0] movementPhase = stopPhase; 8003952: 2305 movs r3, #5 8003954: f887 3037 strb.w r3, [r7, #55] @ 0x37 timeLeftMS = 0; 8003958: 2300 movs r3, #0 800395a: 62bb str r3, [r7, #40] @ 0x28 #ifdef DBG_POSITION printf ("Axe %c stop phase\n", posCtrlTaskArg->axe); #endif break; 800395c: e04e b.n 80039fc case stopPhase: float posDiff = sign > 0 ? posCtrlData.positionSettingValue - *posCtrlTaskArg->currentPosition : *posCtrlTaskArg->currentPosition - posCtrlData.positionSettingValue; 800395e: 6bbb ldr r3, [r7, #56] @ 0x38 8003960: 2b00 cmp r3, #0 8003962: dd08 ble.n 8003976 8003964: ed97 7a02 vldr s14, [r7, #8] 8003968: 69fb ldr r3, [r7, #28] 800396a: 6a1b ldr r3, [r3, #32] 800396c: edd3 7a00 vldr s15, [r3] 8003970: ee77 7a67 vsub.f32 s15, s14, s15 8003974: e007 b.n 8003986 8003976: 69fb ldr r3, [r7, #28] 8003978: 6a1b ldr r3, [r3, #32] 800397a: ed93 7a00 vldr s14, [r3] 800397e: edd7 7a02 vldr s15, [r7, #8] 8003982: ee77 7a67 vsub.f32 s15, s14, s15 8003986: edc7 7a04 vstr s15, [r7, #16] if ((posDiff <= 0) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) { 800398a: edd7 7a04 vldr s15, [r7, #16] 800398e: eef5 7ac0 vcmpe.f32 s15, #0.0 8003992: eef1 fa10 vmrs APSR_nzcv, fpscr 8003996: d903 bls.n 80039a0 8003998: 6abb ldr r3, [r7, #40] @ 0x28 800399a: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800399e: db2c blt.n 80039fa motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80039a0: 69fb ldr r3, [r7, #28] 80039a2: 6818 ldr r0, [r3, #0] 80039a4: 69fb ldr r3, [r7, #28] 80039a6: 685c ldr r4, [r3, #4] 80039a8: 69fb ldr r3, [r7, #28] 80039aa: 7a1d ldrb r5, [r3, #8] 80039ac: 69fb ldr r3, [r7, #28] 80039ae: 7a5e ldrb r6, [r3, #9] 80039b0: 69fb ldr r3, [r7, #28] 80039b2: 68db ldr r3, [r3, #12] 0, 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80039b4: 69fa ldr r2, [r7, #28] 80039b6: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80039b8: 7812 ldrb r2, [r2, #0] 0, 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80039ba: 69f9 ldr r1, [r7, #28] 80039bc: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80039be: 7809 ldrb r1, [r1, #0] 80039c0: 9104 str r1, [sp, #16] 80039c2: 9203 str r2, [sp, #12] 80039c4: 2200 movs r2, #0 80039c6: 9202 str r2, [sp, #8] 80039c8: 2200 movs r2, #0 80039ca: 9201 str r2, [sp, #4] 80039cc: 9300 str r3, [sp, #0] 80039ce: 4633 mov r3, r6 80039d0: 462a mov r2, r5 80039d2: 4621 mov r1, r4 80039d4: f7ff fb54 bl 8003080 80039d8: 4603 mov r3, r0 80039da: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 80039dc: 69fb ldr r3, [r7, #28] 80039de: 6a9b ldr r3, [r3, #40] @ 0x28 80039e0: 69ba ldr r2, [r7, #24] 80039e2: b2d2 uxtb r2, r2 80039e4: 701a strb r2, [r3, #0] movementPhase = idlePhase; 80039e6: 2300 movs r3, #0 80039e8: f887 3037 strb.w r3, [r7, #55] @ 0x37 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); #endif } break; 80039ec: e005 b.n 80039fa default: break; 80039ee: bf00 nop 80039f0: e011 b.n 8003a16 break; 80039f2: bf00 nop 80039f4: e00f b.n 8003a16 break; 80039f6: bf00 nop 80039f8: e00d b.n 8003a16 break; 80039fa: bf00 nop switch (movementPhase) { 80039fc: e00b b.n 8003a16 } } else { if ((*posCtrlTaskArg->motorStatus == 0) && (movementPhase != idlePhase)) { 80039fe: 69fb ldr r3, [r7, #28] 8003a00: 6a9b ldr r3, [r3, #40] @ 0x28 8003a02: 781b ldrb r3, [r3, #0] 8003a04: 2b00 cmp r3, #0 8003a06: d106 bne.n 8003a16 8003a08: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 8003a0c: 2b00 cmp r3, #0 8003a0e: d002 beq.n 8003a16 movementPhase = idlePhase; 8003a10: 2300 movs r3, #0 8003a12: f887 3037 strb.w r3, [r7, #55] @ 0x37 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); #endif } } osMutexRelease (sensorsInfoMutex); 8003a16: 4b03 ldr r3, [pc, #12] @ (8003a24 ) 8003a18: 681b ldr r3, [r3, #0] 8003a1a: 4618 mov r0, r3 8003a1c: f010 fdda bl 80145d4 queueSatus = osMessageQueueGet (posCtrlTaskArg->positionSettingQueue, &posCtrlData, 0, pdMS_TO_TICKS (PositionControlTaskTimeOut)); 8003a20: e5ae b.n 8003580 8003a22: bf00 nop 8003a24: 2400081c .word 0x2400081c 08003a28 : buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); } *buffPos = newBuffPos; } void WriteDataToBuffer (uint8_t* buff, uint16_t* buffPos, void* data, uint8_t dataSize) { 8003a28: b480 push {r7} 8003a2a: b089 sub sp, #36 @ 0x24 8003a2c: af00 add r7, sp, #0 8003a2e: 60f8 str r0, [r7, #12] 8003a30: 60b9 str r1, [r7, #8] 8003a32: 607a str r2, [r7, #4] 8003a34: 70fb strb r3, [r7, #3] uint32_t* uDataPtr = data; 8003a36: 687b ldr r3, [r7, #4] 8003a38: 61bb str r3, [r7, #24] uint32_t uData = *uDataPtr; 8003a3a: 69bb ldr r3, [r7, #24] 8003a3c: 681b ldr r3, [r3, #0] 8003a3e: 617b str r3, [r7, #20] uint8_t i = 0; 8003a40: 2300 movs r3, #0 8003a42: 77fb strb r3, [r7, #31] uint8_t newBuffPos = *buffPos; 8003a44: 68bb ldr r3, [r7, #8] 8003a46: 881b ldrh r3, [r3, #0] 8003a48: 77bb strb r3, [r7, #30] for (i = 0; i < dataSize; i++) { 8003a4a: 2300 movs r3, #0 8003a4c: 77fb strb r3, [r7, #31] 8003a4e: e00e b.n 8003a6e buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); 8003a50: 7ffb ldrb r3, [r7, #31] 8003a52: 00db lsls r3, r3, #3 8003a54: 697a ldr r2, [r7, #20] 8003a56: 40da lsrs r2, r3 8003a58: 7fbb ldrb r3, [r7, #30] 8003a5a: 1c59 adds r1, r3, #1 8003a5c: 77b9 strb r1, [r7, #30] 8003a5e: 4619 mov r1, r3 8003a60: 68fb ldr r3, [r7, #12] 8003a62: 440b add r3, r1 8003a64: b2d2 uxtb r2, r2 8003a66: 701a strb r2, [r3, #0] for (i = 0; i < dataSize; i++) { 8003a68: 7ffb ldrb r3, [r7, #31] 8003a6a: 3301 adds r3, #1 8003a6c: 77fb strb r3, [r7, #31] 8003a6e: 7ffa ldrb r2, [r7, #31] 8003a70: 78fb ldrb r3, [r7, #3] 8003a72: 429a cmp r2, r3 8003a74: d3ec bcc.n 8003a50 } *buffPos = newBuffPos; 8003a76: 7fbb ldrb r3, [r7, #30] 8003a78: b29a uxth r2, r3 8003a7a: 68bb ldr r3, [r7, #8] 8003a7c: 801a strh r2, [r3, #0] } 8003a7e: bf00 nop 8003a80: 3724 adds r7, #36 @ 0x24 8003a82: 46bd mov sp, r7 8003a84: f85d 7b04 ldr.w r7, [sp], #4 8003a88: 4770 bx lr 08003a8a : void ReadFloatFromBuffer(uint8_t* buff, uint16_t* buffPos, float* data) { 8003a8a: b480 push {r7} 8003a8c: b087 sub sp, #28 8003a8e: af00 add r7, sp, #0 8003a90: 60f8 str r0, [r7, #12] 8003a92: 60b9 str r1, [r7, #8] 8003a94: 607a str r2, [r7, #4] uint32_t* word = (uint32_t *)data; 8003a96: 687b ldr r3, [r7, #4] 8003a98: 617b str r3, [r7, #20] *word = CONVERT_BYTES_TO_WORD(&buff[*buffPos]); 8003a9a: 68bb ldr r3, [r7, #8] 8003a9c: 881b ldrh r3, [r3, #0] 8003a9e: 3303 adds r3, #3 8003aa0: 68fa ldr r2, [r7, #12] 8003aa2: 4413 add r3, r2 8003aa4: 781b ldrb r3, [r3, #0] 8003aa6: 061a lsls r2, r3, #24 8003aa8: 68bb ldr r3, [r7, #8] 8003aaa: 881b ldrh r3, [r3, #0] 8003aac: 3302 adds r3, #2 8003aae: 68f9 ldr r1, [r7, #12] 8003ab0: 440b add r3, r1 8003ab2: 781b ldrb r3, [r3, #0] 8003ab4: 041b lsls r3, r3, #16 8003ab6: 431a orrs r2, r3 8003ab8: 68bb ldr r3, [r7, #8] 8003aba: 881b ldrh r3, [r3, #0] 8003abc: 3301 adds r3, #1 8003abe: 68f9 ldr r1, [r7, #12] 8003ac0: 440b add r3, r1 8003ac2: 781b ldrb r3, [r3, #0] 8003ac4: 021b lsls r3, r3, #8 8003ac6: 4313 orrs r3, r2 8003ac8: 68ba ldr r2, [r7, #8] 8003aca: 8812 ldrh r2, [r2, #0] 8003acc: 4611 mov r1, r2 8003ace: 68fa ldr r2, [r7, #12] 8003ad0: 440a add r2, r1 8003ad2: 7812 ldrb r2, [r2, #0] 8003ad4: 4313 orrs r3, r2 8003ad6: 461a mov r2, r3 8003ad8: 697b ldr r3, [r7, #20] 8003ada: 601a str r2, [r3, #0] *buffPos += sizeof(float); 8003adc: 68bb ldr r3, [r7, #8] 8003ade: 881b ldrh r3, [r3, #0] 8003ae0: 3304 adds r3, #4 8003ae2: b29a uxth r2, r3 8003ae4: 68bb ldr r3, [r7, #8] 8003ae6: 801a strh r2, [r3, #0] } 8003ae8: bf00 nop 8003aea: 371c adds r7, #28 8003aec: 46bd mov sp, r7 8003aee: f85d 7b04 ldr.w r7, [sp], #4 8003af2: 4770 bx lr 08003af4 : *data = CONVERT_BYTES_TO_SHORT_WORD(&buff[*buffPos]); *buffPos += sizeof(uint16_t); } void ReadWordFromBufer(uint8_t* buff, uint16_t* buffPos, uint32_t* data) { 8003af4: b480 push {r7} 8003af6: b085 sub sp, #20 8003af8: af00 add r7, sp, #0 8003afa: 60f8 str r0, [r7, #12] 8003afc: 60b9 str r1, [r7, #8] 8003afe: 607a str r2, [r7, #4] *data = CONVERT_BYTES_TO_WORD(&buff[*buffPos]); 8003b00: 68bb ldr r3, [r7, #8] 8003b02: 881b ldrh r3, [r3, #0] 8003b04: 3303 adds r3, #3 8003b06: 68fa ldr r2, [r7, #12] 8003b08: 4413 add r3, r2 8003b0a: 781b ldrb r3, [r3, #0] 8003b0c: 061a lsls r2, r3, #24 8003b0e: 68bb ldr r3, [r7, #8] 8003b10: 881b ldrh r3, [r3, #0] 8003b12: 3302 adds r3, #2 8003b14: 68f9 ldr r1, [r7, #12] 8003b16: 440b add r3, r1 8003b18: 781b ldrb r3, [r3, #0] 8003b1a: 041b lsls r3, r3, #16 8003b1c: 431a orrs r2, r3 8003b1e: 68bb ldr r3, [r7, #8] 8003b20: 881b ldrh r3, [r3, #0] 8003b22: 3301 adds r3, #1 8003b24: 68f9 ldr r1, [r7, #12] 8003b26: 440b add r3, r1 8003b28: 781b ldrb r3, [r3, #0] 8003b2a: 021b lsls r3, r3, #8 8003b2c: 4313 orrs r3, r2 8003b2e: 68ba ldr r2, [r7, #8] 8003b30: 8812 ldrh r2, [r2, #0] 8003b32: 4611 mov r1, r2 8003b34: 68fa ldr r2, [r7, #12] 8003b36: 440a add r2, r1 8003b38: 7812 ldrb r2, [r2, #0] 8003b3a: 4313 orrs r3, r2 8003b3c: 461a mov r2, r3 8003b3e: 687b ldr r3, [r7, #4] 8003b40: 601a str r2, [r3, #0] *buffPos += sizeof(uint32_t); 8003b42: 68bb ldr r3, [r7, #8] 8003b44: 881b ldrh r3, [r3, #0] 8003b46: 3304 adds r3, #4 8003b48: b29a uxth r2, r3 8003b4a: 68bb ldr r3, [r7, #8] 8003b4c: 801a strh r2, [r3, #0] } 8003b4e: bf00 nop 8003b50: 3714 adds r7, #20 8003b52: 46bd mov sp, r7 8003b54: f85d 7b04 ldr.w r7, [sp], #4 8003b58: 4770 bx lr ... 08003b5c : txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); return txBufferPos; } uint16_t PrepareRespFrame (uint8_t* txBuffer, uint16_t frameId, SerialProtocolCommands frameCommand, SerialProtocolRespStatus respStatus, uint8_t* dataBuffer, uint16_t dataLength) { 8003b5c: b580 push {r7, lr} 8003b5e: b084 sub sp, #16 8003b60: af00 add r7, sp, #0 8003b62: 6078 str r0, [r7, #4] 8003b64: 4608 mov r0, r1 8003b66: 4611 mov r1, r2 8003b68: 461a mov r2, r3 8003b6a: 4603 mov r3, r0 8003b6c: 807b strh r3, [r7, #2] 8003b6e: 460b mov r3, r1 8003b70: 707b strb r3, [r7, #1] 8003b72: 4613 mov r3, r2 8003b74: 703b strb r3, [r7, #0] uint16_t crc = 0; 8003b76: 2300 movs r3, #0 8003b78: 81bb strh r3, [r7, #12] uint16_t txBufferPos = 0; 8003b7a: 2300 movs r3, #0 8003b7c: 81fb strh r3, [r7, #14] uint16_t frameCmd = ((uint16_t)frameCommand) | 0x8000; // MSB set means response 8003b7e: 787b ldrb r3, [r7, #1] 8003b80: b21a sxth r2, r3 8003b82: 4b43 ldr r3, [pc, #268] @ (8003c90 ) 8003b84: 4313 orrs r3, r2 8003b86: b21b sxth r3, r3 8003b88: 817b strh r3, [r7, #10] memset (txBuffer, 0x00, dataLength); 8003b8a: 8bbb ldrh r3, [r7, #28] 8003b8c: 461a mov r2, r3 8003b8e: 2100 movs r1, #0 8003b90: 6878 ldr r0, [r7, #4] 8003b92: f014 fc01 bl 8018398 txBuffer[txBufferPos++] = FRAME_INDICATOR; 8003b96: 89fb ldrh r3, [r7, #14] 8003b98: 1c5a adds r2, r3, #1 8003b9a: 81fa strh r2, [r7, #14] 8003b9c: 461a mov r2, r3 8003b9e: 687b ldr r3, [r7, #4] 8003ba0: 4413 add r3, r2 8003ba2: 22aa movs r2, #170 @ 0xaa 8003ba4: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameId); 8003ba6: 89fb ldrh r3, [r7, #14] 8003ba8: 1c5a adds r2, r3, #1 8003baa: 81fa strh r2, [r7, #14] 8003bac: 461a mov r2, r3 8003bae: 687b ldr r3, [r7, #4] 8003bb0: 4413 add r3, r2 8003bb2: 887a ldrh r2, [r7, #2] 8003bb4: b2d2 uxtb r2, r2 8003bb6: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameId); 8003bb8: 887b ldrh r3, [r7, #2] 8003bba: 0a1b lsrs r3, r3, #8 8003bbc: b29a uxth r2, r3 8003bbe: 89fb ldrh r3, [r7, #14] 8003bc0: 1c59 adds r1, r3, #1 8003bc2: 81f9 strh r1, [r7, #14] 8003bc4: 4619 mov r1, r3 8003bc6: 687b ldr r3, [r7, #4] 8003bc8: 440b add r3, r1 8003bca: b2d2 uxtb r2, r2 8003bcc: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameCmd); 8003bce: 89fb ldrh r3, [r7, #14] 8003bd0: 1c5a adds r2, r3, #1 8003bd2: 81fa strh r2, [r7, #14] 8003bd4: 461a mov r2, r3 8003bd6: 687b ldr r3, [r7, #4] 8003bd8: 4413 add r3, r2 8003bda: 897a ldrh r2, [r7, #10] 8003bdc: b2d2 uxtb r2, r2 8003bde: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameCmd); 8003be0: 897b ldrh r3, [r7, #10] 8003be2: 0a1b lsrs r3, r3, #8 8003be4: b29a uxth r2, r3 8003be6: 89fb ldrh r3, [r7, #14] 8003be8: 1c59 adds r1, r3, #1 8003bea: 81f9 strh r1, [r7, #14] 8003bec: 4619 mov r1, r3 8003bee: 687b ldr r3, [r7, #4] 8003bf0: 440b add r3, r1 8003bf2: b2d2 uxtb r2, r2 8003bf4: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (dataLength); 8003bf6: 89fb ldrh r3, [r7, #14] 8003bf8: 1c5a adds r2, r3, #1 8003bfa: 81fa strh r2, [r7, #14] 8003bfc: 461a mov r2, r3 8003bfe: 687b ldr r3, [r7, #4] 8003c00: 4413 add r3, r2 8003c02: 8bba ldrh r2, [r7, #28] 8003c04: b2d2 uxtb r2, r2 8003c06: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (dataLength); 8003c08: 8bbb ldrh r3, [r7, #28] 8003c0a: 0a1b lsrs r3, r3, #8 8003c0c: b29a uxth r2, r3 8003c0e: 89fb ldrh r3, [r7, #14] 8003c10: 1c59 adds r1, r3, #1 8003c12: 81f9 strh r1, [r7, #14] 8003c14: 4619 mov r1, r3 8003c16: 687b ldr r3, [r7, #4] 8003c18: 440b add r3, r1 8003c1a: b2d2 uxtb r2, r2 8003c1c: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = (uint8_t)respStatus; 8003c1e: 89fb ldrh r3, [r7, #14] 8003c20: 1c5a adds r2, r3, #1 8003c22: 81fa strh r2, [r7, #14] 8003c24: 461a mov r2, r3 8003c26: 687b ldr r3, [r7, #4] 8003c28: 4413 add r3, r2 8003c2a: 783a ldrb r2, [r7, #0] 8003c2c: 701a strb r2, [r3, #0] if (dataLength > 0) { 8003c2e: 8bbb ldrh r3, [r7, #28] 8003c30: 2b00 cmp r3, #0 8003c32: d00b beq.n 8003c4c memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength); 8003c34: 89fb ldrh r3, [r7, #14] 8003c36: 687a ldr r2, [r7, #4] 8003c38: 4413 add r3, r2 8003c3a: 8bba ldrh r2, [r7, #28] 8003c3c: 69b9 ldr r1, [r7, #24] 8003c3e: 4618 mov r0, r3 8003c40: f014 fc34 bl 80184ac txBufferPos += dataLength; 8003c44: 89fa ldrh r2, [r7, #14] 8003c46: 8bbb ldrh r3, [r7, #28] 8003c48: 4413 add r3, r2 8003c4a: 81fb strh r3, [r7, #14] } crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)txBuffer, txBufferPos); 8003c4c: 89fb ldrh r3, [r7, #14] 8003c4e: 461a mov r2, r3 8003c50: 6879 ldr r1, [r7, #4] 8003c52: 4810 ldr r0, [pc, #64] @ (8003c94 ) 8003c54: f004 f8d0 bl 8007df8 8003c58: 4603 mov r3, r0 8003c5a: 81bb strh r3, [r7, #12] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (crc); 8003c5c: 89fb ldrh r3, [r7, #14] 8003c5e: 1c5a adds r2, r3, #1 8003c60: 81fa strh r2, [r7, #14] 8003c62: 461a mov r2, r3 8003c64: 687b ldr r3, [r7, #4] 8003c66: 4413 add r3, r2 8003c68: 89ba ldrh r2, [r7, #12] 8003c6a: b2d2 uxtb r2, r2 8003c6c: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); 8003c6e: 89bb ldrh r3, [r7, #12] 8003c70: 0a1b lsrs r3, r3, #8 8003c72: b29a uxth r2, r3 8003c74: 89fb ldrh r3, [r7, #14] 8003c76: 1c59 adds r1, r3, #1 8003c78: 81f9 strh r1, [r7, #14] 8003c7a: 4619 mov r1, r3 8003c7c: 687b ldr r3, [r7, #4] 8003c7e: 440b add r3, r1 8003c80: b2d2 uxtb r2, r2 8003c82: 701a strb r2, [r3, #0] return txBufferPos; 8003c84: 89fb ldrh r3, [r7, #14] } 8003c86: 4618 mov r0, r3 8003c88: 3710 adds r7, #16 8003c8a: 46bd mov sp, r7 8003c8c: bd80 pop {r7, pc} 8003c8e: bf00 nop 8003c90: ffff8000 .word 0xffff8000 8003c94: 240003e0 .word 0x240003e0 08003c98 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8003c98: b580 push {r7, lr} 8003c9a: b086 sub sp, #24 8003c9c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ PWREx_AVDTypeDef sConfigAVD = {0}; 8003c9e: f107 0310 add.w r3, r7, #16 8003ca2: 2200 movs r2, #0 8003ca4: 601a str r2, [r3, #0] 8003ca6: 605a str r2, [r3, #4] PWR_PVDTypeDef sConfigPVD = {0}; 8003ca8: f107 0308 add.w r3, r7, #8 8003cac: 2200 movs r2, #0 8003cae: 601a str r2, [r3, #0] 8003cb0: 605a str r2, [r3, #4] __HAL_RCC_SYSCFG_CLK_ENABLE(); 8003cb2: 4b26 ldr r3, [pc, #152] @ (8003d4c ) 8003cb4: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003cb8: 4a24 ldr r2, [pc, #144] @ (8003d4c ) 8003cba: f043 0302 orr.w r3, r3, #2 8003cbe: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8003cc2: 4b22 ldr r3, [pc, #136] @ (8003d4c ) 8003cc4: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003cc8: f003 0302 and.w r3, r3, #2 8003ccc: 607b str r3, [r7, #4] 8003cce: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 8003cd0: 2200 movs r2, #0 8003cd2: 210f movs r1, #15 8003cd4: f06f 0001 mvn.w r0, #1 8003cd8: f003 ff8a bl 8007bf0 /* Peripheral interrupt init */ /* RCC_IRQn interrupt configuration */ HAL_NVIC_SetPriority(RCC_IRQn, 5, 0); 8003cdc: 2200 movs r2, #0 8003cde: 2105 movs r1, #5 8003ce0: 2005 movs r0, #5 8003ce2: f003 ff85 bl 8007bf0 HAL_NVIC_EnableIRQ(RCC_IRQn); 8003ce6: 2005 movs r0, #5 8003ce8: f003 ff9c bl 8007c24 /** AVD Configuration */ sConfigAVD.AVDLevel = PWR_AVDLEVEL_3; 8003cec: f44f 23c0 mov.w r3, #393216 @ 0x60000 8003cf0: 613b str r3, [r7, #16] sConfigAVD.Mode = PWR_AVD_MODE_NORMAL; 8003cf2: 2300 movs r3, #0 8003cf4: 617b str r3, [r7, #20] HAL_PWREx_ConfigAVD(&sConfigAVD); 8003cf6: f107 0310 add.w r3, r7, #16 8003cfa: 4618 mov r0, r3 8003cfc: f007 fde2 bl 800b8c4 /** Enable the AVD Output */ HAL_PWREx_EnableAVD(); 8003d00: f007 fe56 bl 800b9b0 /** PVD Configuration */ sConfigPVD.PVDLevel = PWR_PVDLEVEL_6; 8003d04: 23c0 movs r3, #192 @ 0xc0 8003d06: 60bb str r3, [r7, #8] sConfigPVD.Mode = PWR_PVD_MODE_NORMAL; 8003d08: 2300 movs r3, #0 8003d0a: 60fb str r3, [r7, #12] HAL_PWR_ConfigPVD(&sConfigPVD); 8003d0c: f107 0308 add.w r3, r7, #8 8003d10: 4618 mov r0, r3 8003d12: f007 fd13 bl 800b73c /** Enable the PVD Output */ HAL_PWR_EnablePVD(); 8003d16: f007 fd8b bl 800b830 /** Enable the VREF clock */ __HAL_RCC_VREF_CLK_ENABLE(); 8003d1a: 4b0c ldr r3, [pc, #48] @ (8003d4c ) 8003d1c: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003d20: 4a0a ldr r2, [pc, #40] @ (8003d4c ) 8003d22: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8003d26: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8003d2a: 4b08 ldr r3, [pc, #32] @ (8003d4c ) 8003d2c: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003d30: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003d34: 603b str r3, [r7, #0] 8003d36: 683b ldr r3, [r7, #0] /** Disable the Internal Voltage Reference buffer */ HAL_SYSCFG_DisableVREFBUF(); 8003d38: f002 f8e0 bl 8005efc /** Configure the internal voltage reference buffer high impedance mode */ HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE); 8003d3c: 2002 movs r0, #2 8003d3e: f002 f8c9 bl 8005ed4 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8003d42: bf00 nop 8003d44: 3718 adds r7, #24 8003d46: 46bd mov sp, r7 8003d48: bd80 pop {r7, pc} 8003d4a: bf00 nop 8003d4c: 58024400 .word 0x58024400 08003d50 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8003d50: b580 push {r7, lr} 8003d52: b092 sub sp, #72 @ 0x48 8003d54: af00 add r7, sp, #0 8003d56: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003d58: f107 0334 add.w r3, r7, #52 @ 0x34 8003d5c: 2200 movs r2, #0 8003d5e: 601a str r2, [r3, #0] 8003d60: 605a str r2, [r3, #4] 8003d62: 609a str r2, [r3, #8] 8003d64: 60da str r2, [r3, #12] 8003d66: 611a str r2, [r3, #16] if(hadc->Instance==ADC1) 8003d68: 687b ldr r3, [r7, #4] 8003d6a: 681b ldr r3, [r3, #0] 8003d6c: 4a9d ldr r2, [pc, #628] @ (8003fe4 ) 8003d6e: 4293 cmp r3, r2 8003d70: f040 8099 bne.w 8003ea6 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; 8003d74: 4b9c ldr r3, [pc, #624] @ (8003fe8 ) 8003d76: 681b ldr r3, [r3, #0] 8003d78: 3301 adds r3, #1 8003d7a: 4a9b ldr r2, [pc, #620] @ (8003fe8 ) 8003d7c: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8003d7e: 4b9a ldr r3, [pc, #616] @ (8003fe8 ) 8003d80: 681b ldr r3, [r3, #0] 8003d82: 2b01 cmp r3, #1 8003d84: d10e bne.n 8003da4 __HAL_RCC_ADC12_CLK_ENABLE(); 8003d86: 4b99 ldr r3, [pc, #612] @ (8003fec ) 8003d88: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003d8c: 4a97 ldr r2, [pc, #604] @ (8003fec ) 8003d8e: f043 0320 orr.w r3, r3, #32 8003d92: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8003d96: 4b95 ldr r3, [pc, #596] @ (8003fec ) 8003d98: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003d9c: f003 0320 and.w r3, r3, #32 8003da0: 633b str r3, [r7, #48] @ 0x30 8003da2: 6b3b ldr r3, [r7, #48] @ 0x30 } __HAL_RCC_GPIOA_CLK_ENABLE(); 8003da4: 4b91 ldr r3, [pc, #580] @ (8003fec ) 8003da6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003daa: 4a90 ldr r2, [pc, #576] @ (8003fec ) 8003dac: f043 0301 orr.w r3, r3, #1 8003db0: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003db4: 4b8d ldr r3, [pc, #564] @ (8003fec ) 8003db6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003dba: f003 0301 and.w r3, r3, #1 8003dbe: 62fb str r3, [r7, #44] @ 0x2c 8003dc0: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 8003dc2: 4b8a ldr r3, [pc, #552] @ (8003fec ) 8003dc4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003dc8: 4a88 ldr r2, [pc, #544] @ (8003fec ) 8003dca: f043 0304 orr.w r3, r3, #4 8003dce: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003dd2: 4b86 ldr r3, [pc, #536] @ (8003fec ) 8003dd4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003dd8: f003 0304 and.w r3, r3, #4 8003ddc: 62bb str r3, [r7, #40] @ 0x28 8003dde: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOB_CLK_ENABLE(); 8003de0: 4b82 ldr r3, [pc, #520] @ (8003fec ) 8003de2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003de6: 4a81 ldr r2, [pc, #516] @ (8003fec ) 8003de8: f043 0302 orr.w r3, r3, #2 8003dec: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003df0: 4b7e ldr r3, [pc, #504] @ (8003fec ) 8003df2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003df6: f003 0302 and.w r3, r3, #2 8003dfa: 627b str r3, [r7, #36] @ 0x24 8003dfc: 6a7b ldr r3, [r7, #36] @ 0x24 PA3 ------> ADC1_INP15 PA7 ------> ADC1_INP7 PC5 ------> ADC1_INP8 PB0 ------> ADC1_INP9 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 8003dfe: 238f movs r3, #143 @ 0x8f 8003e00: 637b str r3, [r7, #52] @ 0x34 |GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003e02: 2303 movs r3, #3 8003e04: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003e06: 2300 movs r3, #0 8003e08: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003e0a: f107 0334 add.w r3, r7, #52 @ 0x34 8003e0e: 4619 mov r1, r3 8003e10: 4877 ldr r0, [pc, #476] @ (8003ff0 ) 8003e12: f007 fa1f bl 800b254 GPIO_InitStruct.Pin = GPIO_PIN_5; 8003e16: 2320 movs r3, #32 8003e18: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003e1a: 2303 movs r3, #3 8003e1c: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003e1e: 2300 movs r3, #0 8003e20: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003e22: f107 0334 add.w r3, r7, #52 @ 0x34 8003e26: 4619 mov r1, r3 8003e28: 4872 ldr r0, [pc, #456] @ (8003ff4 ) 8003e2a: f007 fa13 bl 800b254 GPIO_InitStruct.Pin = GPIO_PIN_0; 8003e2e: 2301 movs r3, #1 8003e30: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003e32: 2303 movs r3, #3 8003e34: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003e36: 2300 movs r3, #0 8003e38: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003e3a: f107 0334 add.w r3, r7, #52 @ 0x34 8003e3e: 4619 mov r1, r3 8003e40: 486d ldr r0, [pc, #436] @ (8003ff8 ) 8003e42: f007 fa07 bl 800b254 /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Stream0; 8003e46: 4b6d ldr r3, [pc, #436] @ (8003ffc ) 8003e48: 4a6d ldr r2, [pc, #436] @ (8004000 ) 8003e4a: 601a str r2, [r3, #0] hdma_adc1.Init.Request = DMA_REQUEST_ADC1; 8003e4c: 4b6b ldr r3, [pc, #428] @ (8003ffc ) 8003e4e: 2209 movs r2, #9 8003e50: 605a str r2, [r3, #4] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003e52: 4b6a ldr r3, [pc, #424] @ (8003ffc ) 8003e54: 2200 movs r2, #0 8003e56: 609a str r2, [r3, #8] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8003e58: 4b68 ldr r3, [pc, #416] @ (8003ffc ) 8003e5a: 2200 movs r2, #0 8003e5c: 60da str r2, [r3, #12] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8003e5e: 4b67 ldr r3, [pc, #412] @ (8003ffc ) 8003e60: f44f 6280 mov.w r2, #1024 @ 0x400 8003e64: 611a str r2, [r3, #16] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8003e66: 4b65 ldr r3, [pc, #404] @ (8003ffc ) 8003e68: f44f 6200 mov.w r2, #2048 @ 0x800 8003e6c: 615a str r2, [r3, #20] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8003e6e: 4b63 ldr r3, [pc, #396] @ (8003ffc ) 8003e70: f44f 5200 mov.w r2, #8192 @ 0x2000 8003e74: 619a str r2, [r3, #24] hdma_adc1.Init.Mode = DMA_NORMAL; 8003e76: 4b61 ldr r3, [pc, #388] @ (8003ffc ) 8003e78: 2200 movs r2, #0 8003e7a: 61da str r2, [r3, #28] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; 8003e7c: 4b5f ldr r3, [pc, #380] @ (8003ffc ) 8003e7e: 2200 movs r2, #0 8003e80: 621a str r2, [r3, #32] hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003e82: 4b5e ldr r3, [pc, #376] @ (8003ffc ) 8003e84: 2200 movs r2, #0 8003e86: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 8003e88: 485c ldr r0, [pc, #368] @ (8003ffc ) 8003e8a: f004 fba7 bl 80085dc 8003e8e: 4603 mov r3, r0 8003e90: 2b00 cmp r3, #0 8003e92: d001 beq.n 8003e98 { Error_Handler(); 8003e94: f7fe f81a bl 8001ecc } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); 8003e98: 687b ldr r3, [r7, #4] 8003e9a: 4a58 ldr r2, [pc, #352] @ (8003ffc ) 8003e9c: 64da str r2, [r3, #76] @ 0x4c 8003e9e: 4a57 ldr r2, [pc, #348] @ (8003ffc ) 8003ea0: 687b ldr r3, [r7, #4] 8003ea2: 6393 str r3, [r2, #56] @ 0x38 /* USER CODE BEGIN ADC3_MspInit 1 */ /* USER CODE END ADC3_MspInit 1 */ } } 8003ea4: e11e b.n 80040e4 else if(hadc->Instance==ADC2) 8003ea6: 687b ldr r3, [r7, #4] 8003ea8: 681b ldr r3, [r3, #0] 8003eaa: 4a56 ldr r2, [pc, #344] @ (8004004 ) 8003eac: 4293 cmp r3, r2 8003eae: f040 80af bne.w 8004010 HAL_RCC_ADC12_CLK_ENABLED++; 8003eb2: 4b4d ldr r3, [pc, #308] @ (8003fe8 ) 8003eb4: 681b ldr r3, [r3, #0] 8003eb6: 3301 adds r3, #1 8003eb8: 4a4b ldr r2, [pc, #300] @ (8003fe8 ) 8003eba: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8003ebc: 4b4a ldr r3, [pc, #296] @ (8003fe8 ) 8003ebe: 681b ldr r3, [r3, #0] 8003ec0: 2b01 cmp r3, #1 8003ec2: d10e bne.n 8003ee2 __HAL_RCC_ADC12_CLK_ENABLE(); 8003ec4: 4b49 ldr r3, [pc, #292] @ (8003fec ) 8003ec6: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003eca: 4a48 ldr r2, [pc, #288] @ (8003fec ) 8003ecc: f043 0320 orr.w r3, r3, #32 8003ed0: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8003ed4: 4b45 ldr r3, [pc, #276] @ (8003fec ) 8003ed6: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003eda: f003 0320 and.w r3, r3, #32 8003ede: 623b str r3, [r7, #32] 8003ee0: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 8003ee2: 4b42 ldr r3, [pc, #264] @ (8003fec ) 8003ee4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003ee8: 4a40 ldr r2, [pc, #256] @ (8003fec ) 8003eea: f043 0301 orr.w r3, r3, #1 8003eee: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003ef2: 4b3e ldr r3, [pc, #248] @ (8003fec ) 8003ef4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003ef8: f003 0301 and.w r3, r3, #1 8003efc: 61fb str r3, [r7, #28] 8003efe: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOC_CLK_ENABLE(); 8003f00: 4b3a ldr r3, [pc, #232] @ (8003fec ) 8003f02: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003f06: 4a39 ldr r2, [pc, #228] @ (8003fec ) 8003f08: f043 0304 orr.w r3, r3, #4 8003f0c: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003f10: 4b36 ldr r3, [pc, #216] @ (8003fec ) 8003f12: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003f16: f003 0304 and.w r3, r3, #4 8003f1a: 61bb str r3, [r7, #24] 8003f1c: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 8003f1e: 4b33 ldr r3, [pc, #204] @ (8003fec ) 8003f20: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003f24: 4a31 ldr r2, [pc, #196] @ (8003fec ) 8003f26: f043 0302 orr.w r3, r3, #2 8003f2a: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003f2e: 4b2f ldr r3, [pc, #188] @ (8003fec ) 8003f30: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003f34: f003 0302 and.w r3, r3, #2 8003f38: 617b str r3, [r7, #20] 8003f3a: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_6; 8003f3c: 2340 movs r3, #64 @ 0x40 8003f3e: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003f40: 2303 movs r3, #3 8003f42: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003f44: 2300 movs r3, #0 8003f46: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003f48: f107 0334 add.w r3, r7, #52 @ 0x34 8003f4c: 4619 mov r1, r3 8003f4e: 4828 ldr r0, [pc, #160] @ (8003ff0 ) 8003f50: f007 f980 bl 800b254 GPIO_InitStruct.Pin = GPIO_PIN_4; 8003f54: 2310 movs r3, #16 8003f56: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003f58: 2303 movs r3, #3 8003f5a: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003f5c: 2300 movs r3, #0 8003f5e: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003f60: f107 0334 add.w r3, r7, #52 @ 0x34 8003f64: 4619 mov r1, r3 8003f66: 4823 ldr r0, [pc, #140] @ (8003ff4 ) 8003f68: f007 f974 bl 800b254 GPIO_InitStruct.Pin = GPIO_PIN_1; 8003f6c: 2302 movs r3, #2 8003f6e: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003f70: 2303 movs r3, #3 8003f72: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003f74: 2300 movs r3, #0 8003f76: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003f78: f107 0334 add.w r3, r7, #52 @ 0x34 8003f7c: 4619 mov r1, r3 8003f7e: 481e ldr r0, [pc, #120] @ (8003ff8 ) 8003f80: f007 f968 bl 800b254 hdma_adc2.Instance = DMA1_Stream1; 8003f84: 4b20 ldr r3, [pc, #128] @ (8004008 ) 8003f86: 4a21 ldr r2, [pc, #132] @ (800400c ) 8003f88: 601a str r2, [r3, #0] hdma_adc2.Init.Request = DMA_REQUEST_ADC2; 8003f8a: 4b1f ldr r3, [pc, #124] @ (8004008 ) 8003f8c: 220a movs r2, #10 8003f8e: 605a str r2, [r3, #4] hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003f90: 4b1d ldr r3, [pc, #116] @ (8004008 ) 8003f92: 2200 movs r2, #0 8003f94: 609a str r2, [r3, #8] hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; 8003f96: 4b1c ldr r3, [pc, #112] @ (8004008 ) 8003f98: 2200 movs r2, #0 8003f9a: 60da str r2, [r3, #12] hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; 8003f9c: 4b1a ldr r3, [pc, #104] @ (8004008 ) 8003f9e: f44f 6280 mov.w r2, #1024 @ 0x400 8003fa2: 611a str r2, [r3, #16] hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8003fa4: 4b18 ldr r3, [pc, #96] @ (8004008 ) 8003fa6: f44f 6200 mov.w r2, #2048 @ 0x800 8003faa: 615a str r2, [r3, #20] hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8003fac: 4b16 ldr r3, [pc, #88] @ (8004008 ) 8003fae: f44f 5200 mov.w r2, #8192 @ 0x2000 8003fb2: 619a str r2, [r3, #24] hdma_adc2.Init.Mode = DMA_NORMAL; 8003fb4: 4b14 ldr r3, [pc, #80] @ (8004008 ) 8003fb6: 2200 movs r2, #0 8003fb8: 61da str r2, [r3, #28] hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; 8003fba: 4b13 ldr r3, [pc, #76] @ (8004008 ) 8003fbc: 2200 movs r2, #0 8003fbe: 621a str r2, [r3, #32] hdma_adc2.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003fc0: 4b11 ldr r3, [pc, #68] @ (8004008 ) 8003fc2: 2200 movs r2, #0 8003fc4: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) 8003fc6: 4810 ldr r0, [pc, #64] @ (8004008 ) 8003fc8: f004 fb08 bl 80085dc 8003fcc: 4603 mov r3, r0 8003fce: 2b00 cmp r3, #0 8003fd0: d001 beq.n 8003fd6 Error_Handler(); 8003fd2: f7fd ff7b bl 8001ecc __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2); 8003fd6: 687b ldr r3, [r7, #4] 8003fd8: 4a0b ldr r2, [pc, #44] @ (8004008 ) 8003fda: 64da str r2, [r3, #76] @ 0x4c 8003fdc: 4a0a ldr r2, [pc, #40] @ (8004008 ) 8003fde: 687b ldr r3, [r7, #4] 8003fe0: 6393 str r3, [r2, #56] @ 0x38 } 8003fe2: e07f b.n 80040e4 8003fe4: 40022000 .word 0x40022000 8003fe8: 2400091c .word 0x2400091c 8003fec: 58024400 .word 0x58024400 8003ff0: 58020000 .word 0x58020000 8003ff4: 58020800 .word 0x58020800 8003ff8: 58020400 .word 0x58020400 8003ffc: 2400024c .word 0x2400024c 8004000: 40020010 .word 0x40020010 8004004: 40022100 .word 0x40022100 8004008: 240002c4 .word 0x240002c4 800400c: 40020028 .word 0x40020028 else if(hadc->Instance==ADC3) 8004010: 687b ldr r3, [r7, #4] 8004012: 681b ldr r3, [r3, #0] 8004014: 4a35 ldr r2, [pc, #212] @ (80040ec ) 8004016: 4293 cmp r3, r2 8004018: d164 bne.n 80040e4 __HAL_RCC_ADC3_CLK_ENABLE(); 800401a: 4b35 ldr r3, [pc, #212] @ (80040f0 ) 800401c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004020: 4a33 ldr r2, [pc, #204] @ (80040f0 ) 8004022: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8004026: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800402a: 4b31 ldr r3, [pc, #196] @ (80040f0 ) 800402c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004030: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8004034: 613b str r3, [r7, #16] 8004036: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 8004038: 4b2d ldr r3, [pc, #180] @ (80040f0 ) 800403a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800403e: 4a2c ldr r2, [pc, #176] @ (80040f0 ) 8004040: f043 0304 orr.w r3, r3, #4 8004044: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004048: 4b29 ldr r3, [pc, #164] @ (80040f0 ) 800404a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800404e: f003 0304 and.w r3, r3, #4 8004052: 60fb str r3, [r7, #12] 8004054: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8004056: 2303 movs r3, #3 8004058: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 800405a: 2303 movs r3, #3 800405c: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 800405e: 2300 movs r3, #0 8004060: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8004062: f107 0334 add.w r3, r7, #52 @ 0x34 8004066: 4619 mov r1, r3 8004068: 4822 ldr r0, [pc, #136] @ (80040f4 ) 800406a: f007 f8f3 bl 800b254 HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC2, SYSCFG_SWITCH_PC2_OPEN); 800406e: f04f 6180 mov.w r1, #67108864 @ 0x4000000 8004072: f04f 6080 mov.w r0, #67108864 @ 0x4000000 8004076: f001 ff51 bl 8005f1c HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC3, SYSCFG_SWITCH_PC3_OPEN); 800407a: f04f 6100 mov.w r1, #134217728 @ 0x8000000 800407e: f04f 6000 mov.w r0, #134217728 @ 0x8000000 8004082: f001 ff4b bl 8005f1c hdma_adc3.Instance = DMA1_Stream2; 8004086: 4b1c ldr r3, [pc, #112] @ (80040f8 ) 8004088: 4a1c ldr r2, [pc, #112] @ (80040fc ) 800408a: 601a str r2, [r3, #0] hdma_adc3.Init.Request = DMA_REQUEST_ADC3; 800408c: 4b1a ldr r3, [pc, #104] @ (80040f8 ) 800408e: 2273 movs r2, #115 @ 0x73 8004090: 605a str r2, [r3, #4] hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY; 8004092: 4b19 ldr r3, [pc, #100] @ (80040f8 ) 8004094: 2200 movs r2, #0 8004096: 609a str r2, [r3, #8] hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE; 8004098: 4b17 ldr r3, [pc, #92] @ (80040f8 ) 800409a: 2200 movs r2, #0 800409c: 60da str r2, [r3, #12] hdma_adc3.Init.MemInc = DMA_MINC_ENABLE; 800409e: 4b16 ldr r3, [pc, #88] @ (80040f8 ) 80040a0: f44f 6280 mov.w r2, #1024 @ 0x400 80040a4: 611a str r2, [r3, #16] hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 80040a6: 4b14 ldr r3, [pc, #80] @ (80040f8 ) 80040a8: f44f 6200 mov.w r2, #2048 @ 0x800 80040ac: 615a str r2, [r3, #20] hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 80040ae: 4b12 ldr r3, [pc, #72] @ (80040f8 ) 80040b0: f44f 5200 mov.w r2, #8192 @ 0x2000 80040b4: 619a str r2, [r3, #24] hdma_adc3.Init.Mode = DMA_NORMAL; 80040b6: 4b10 ldr r3, [pc, #64] @ (80040f8 ) 80040b8: 2200 movs r2, #0 80040ba: 61da str r2, [r3, #28] hdma_adc3.Init.Priority = DMA_PRIORITY_LOW; 80040bc: 4b0e ldr r3, [pc, #56] @ (80040f8 ) 80040be: 2200 movs r2, #0 80040c0: 621a str r2, [r3, #32] hdma_adc3.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80040c2: 4b0d ldr r3, [pc, #52] @ (80040f8 ) 80040c4: 2200 movs r2, #0 80040c6: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc3) != HAL_OK) 80040c8: 480b ldr r0, [pc, #44] @ (80040f8 ) 80040ca: f004 fa87 bl 80085dc 80040ce: 4603 mov r3, r0 80040d0: 2b00 cmp r3, #0 80040d2: d001 beq.n 80040d8 Error_Handler(); 80040d4: f7fd fefa bl 8001ecc __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc3); 80040d8: 687b ldr r3, [r7, #4] 80040da: 4a07 ldr r2, [pc, #28] @ (80040f8 ) 80040dc: 64da str r2, [r3, #76] @ 0x4c 80040de: 4a06 ldr r2, [pc, #24] @ (80040f8 ) 80040e0: 687b ldr r3, [r7, #4] 80040e2: 6393 str r3, [r2, #56] @ 0x38 } 80040e4: bf00 nop 80040e6: 3748 adds r7, #72 @ 0x48 80040e8: 46bd mov sp, r7 80040ea: bd80 pop {r7, pc} 80040ec: 58026000 .word 0x58026000 80040f0: 58024400 .word 0x58024400 80040f4: 58020800 .word 0x58020800 80040f8: 2400033c .word 0x2400033c 80040fc: 40020040 .word 0x40020040 08004100 : * This function configures the hardware resources used in this example * @param hcomp: COMP handle pointer * @retval None */ void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp) { 8004100: b580 push {r7, lr} 8004102: b08a sub sp, #40 @ 0x28 8004104: af00 add r7, sp, #0 8004106: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004108: f107 0314 add.w r3, r7, #20 800410c: 2200 movs r2, #0 800410e: 601a str r2, [r3, #0] 8004110: 605a str r2, [r3, #4] 8004112: 609a str r2, [r3, #8] 8004114: 60da str r2, [r3, #12] 8004116: 611a str r2, [r3, #16] if(hcomp->Instance==COMP1) 8004118: 687b ldr r3, [r7, #4] 800411a: 681b ldr r3, [r3, #0] 800411c: 4a18 ldr r2, [pc, #96] @ (8004180 ) 800411e: 4293 cmp r3, r2 8004120: d129 bne.n 8004176 { /* USER CODE BEGIN COMP1_MspInit 0 */ /* USER CODE END COMP1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_COMP12_CLK_ENABLE(); 8004122: 4b18 ldr r3, [pc, #96] @ (8004184 ) 8004124: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8004128: 4a16 ldr r2, [pc, #88] @ (8004184 ) 800412a: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800412e: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8004132: 4b14 ldr r3, [pc, #80] @ (8004184 ) 8004134: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8004138: f403 4380 and.w r3, r3, #16384 @ 0x4000 800413c: 613b str r3, [r7, #16] 800413e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8004140: 4b10 ldr r3, [pc, #64] @ (8004184 ) 8004142: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004146: 4a0f ldr r2, [pc, #60] @ (8004184 ) 8004148: f043 0302 orr.w r3, r3, #2 800414c: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004150: 4b0c ldr r3, [pc, #48] @ (8004184 ) 8004152: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004156: f003 0302 and.w r3, r3, #2 800415a: 60fb str r3, [r7, #12] 800415c: 68fb ldr r3, [r7, #12] /**COMP1 GPIO Configuration PB2 ------> COMP1_INP */ GPIO_InitStruct.Pin = GPIO_PIN_2; 800415e: 2304 movs r3, #4 8004160: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8004162: 2303 movs r3, #3 8004164: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004166: 2300 movs r3, #0 8004168: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800416a: f107 0314 add.w r3, r7, #20 800416e: 4619 mov r1, r3 8004170: 4805 ldr r0, [pc, #20] @ (8004188 ) 8004172: f007 f86f bl 800b254 /* USER CODE BEGIN COMP1_MspInit 1 */ /* USER CODE END COMP1_MspInit 1 */ } } 8004176: bf00 nop 8004178: 3728 adds r7, #40 @ 0x28 800417a: 46bd mov sp, r7 800417c: bd80 pop {r7, pc} 800417e: bf00 nop 8004180: 5800380c .word 0x5800380c 8004184: 58024400 .word 0x58024400 8004188: 58020400 .word 0x58020400 0800418c : * This function configures the hardware resources used in this example * @param hcrc: CRC handle pointer * @retval None */ void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) { 800418c: b480 push {r7} 800418e: b085 sub sp, #20 8004190: af00 add r7, sp, #0 8004192: 6078 str r0, [r7, #4] if(hcrc->Instance==CRC) 8004194: 687b ldr r3, [r7, #4] 8004196: 681b ldr r3, [r3, #0] 8004198: 4a0b ldr r2, [pc, #44] @ (80041c8 ) 800419a: 4293 cmp r3, r2 800419c: d10e bne.n 80041bc { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 800419e: 4b0b ldr r3, [pc, #44] @ (80041cc ) 80041a0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80041a4: 4a09 ldr r2, [pc, #36] @ (80041cc ) 80041a6: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80041aa: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80041ae: 4b07 ldr r3, [pc, #28] @ (80041cc ) 80041b0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80041b4: f403 2300 and.w r3, r3, #524288 @ 0x80000 80041b8: 60fb str r3, [r7, #12] 80041ba: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 80041bc: bf00 nop 80041be: 3714 adds r7, #20 80041c0: 46bd mov sp, r7 80041c2: f85d 7b04 ldr.w r7, [sp], #4 80041c6: 4770 bx lr 80041c8: 58024c00 .word 0x58024c00 80041cc: 58024400 .word 0x58024400 080041d0 : * This function configures the hardware resources used in this example * @param hdac: DAC handle pointer * @retval None */ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) { 80041d0: b580 push {r7, lr} 80041d2: b08a sub sp, #40 @ 0x28 80041d4: af00 add r7, sp, #0 80041d6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80041d8: f107 0314 add.w r3, r7, #20 80041dc: 2200 movs r2, #0 80041de: 601a str r2, [r3, #0] 80041e0: 605a str r2, [r3, #4] 80041e2: 609a str r2, [r3, #8] 80041e4: 60da str r2, [r3, #12] 80041e6: 611a str r2, [r3, #16] if(hdac->Instance==DAC1) 80041e8: 687b ldr r3, [r7, #4] 80041ea: 681b ldr r3, [r3, #0] 80041ec: 4a1c ldr r2, [pc, #112] @ (8004260 ) 80041ee: 4293 cmp r3, r2 80041f0: d131 bne.n 8004256 { /* USER CODE BEGIN DAC1_MspInit 0 */ /* USER CODE END DAC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DAC12_CLK_ENABLE(); 80041f2: 4b1c ldr r3, [pc, #112] @ (8004264 ) 80041f4: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80041f8: 4a1a ldr r2, [pc, #104] @ (8004264 ) 80041fa: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 80041fe: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8004202: 4b18 ldr r3, [pc, #96] @ (8004264 ) 8004204: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004208: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800420c: 613b str r3, [r7, #16] 800420e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8004210: 4b14 ldr r3, [pc, #80] @ (8004264 ) 8004212: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004216: 4a13 ldr r2, [pc, #76] @ (8004264 ) 8004218: f043 0301 orr.w r3, r3, #1 800421c: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004220: 4b10 ldr r3, [pc, #64] @ (8004264 ) 8004222: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004226: f003 0301 and.w r3, r3, #1 800422a: 60fb str r3, [r7, #12] 800422c: 68fb ldr r3, [r7, #12] /**DAC1 GPIO Configuration PA4 ------> DAC1_OUT1 PA5 ------> DAC1_OUT2 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 800422e: 2330 movs r3, #48 @ 0x30 8004230: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8004232: 2303 movs r3, #3 8004234: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004236: 2300 movs r3, #0 8004238: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800423a: f107 0314 add.w r3, r7, #20 800423e: 4619 mov r1, r3 8004240: 4809 ldr r0, [pc, #36] @ (8004268 ) 8004242: f007 f807 bl 800b254 /* DAC1 interrupt Init */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 5, 0); 8004246: 2200 movs r2, #0 8004248: 2105 movs r1, #5 800424a: 2036 movs r0, #54 @ 0x36 800424c: f003 fcd0 bl 8007bf0 HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 8004250: 2036 movs r0, #54 @ 0x36 8004252: f003 fce7 bl 8007c24 /* USER CODE BEGIN DAC1_MspInit 1 */ /* USER CODE END DAC1_MspInit 1 */ } } 8004256: bf00 nop 8004258: 3728 adds r7, #40 @ 0x28 800425a: 46bd mov sp, r7 800425c: bd80 pop {r7, pc} 800425e: bf00 nop 8004260: 40007400 .word 0x40007400 8004264: 58024400 .word 0x58024400 8004268: 58020000 .word 0x58020000 0800426c : * This function configures the hardware resources used in this example * @param hrng: RNG handle pointer * @retval None */ void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) { 800426c: b580 push {r7, lr} 800426e: b0b4 sub sp, #208 @ 0xd0 8004270: af00 add r7, sp, #0 8004272: 6078 str r0, [r7, #4] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8004274: f107 0310 add.w r3, r7, #16 8004278: 22c0 movs r2, #192 @ 0xc0 800427a: 2100 movs r1, #0 800427c: 4618 mov r0, r3 800427e: f014 f88b bl 8018398 if(hrng->Instance==RNG) 8004282: 687b ldr r3, [r7, #4] 8004284: 681b ldr r3, [r3, #0] 8004286: 4a14 ldr r2, [pc, #80] @ (80042d8 ) 8004288: 4293 cmp r3, r2 800428a: d121 bne.n 80042d0 /* USER CODE END RNG_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG; 800428c: f44f 3200 mov.w r2, #131072 @ 0x20000 8004290: f04f 0300 mov.w r3, #0 8004294: e9c7 2304 strd r2, r3, [r7, #16] PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48; 8004298: 2300 movs r3, #0 800429a: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800429e: f107 0310 add.w r3, r7, #16 80042a2: 4618 mov r0, r3 80042a4: f008 fbbc bl 800ca20 80042a8: 4603 mov r3, r0 80042aa: 2b00 cmp r3, #0 80042ac: d001 beq.n 80042b2 { Error_Handler(); 80042ae: f7fd fe0d bl 8001ecc } /* Peripheral clock enable */ __HAL_RCC_RNG_CLK_ENABLE(); 80042b2: 4b0a ldr r3, [pc, #40] @ (80042dc ) 80042b4: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 80042b8: 4a08 ldr r2, [pc, #32] @ (80042dc ) 80042ba: f043 0340 orr.w r3, r3, #64 @ 0x40 80042be: f8c2 30dc str.w r3, [r2, #220] @ 0xdc 80042c2: 4b06 ldr r3, [pc, #24] @ (80042dc ) 80042c4: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 80042c8: f003 0340 and.w r3, r3, #64 @ 0x40 80042cc: 60fb str r3, [r7, #12] 80042ce: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN RNG_MspInit 1 */ /* USER CODE END RNG_MspInit 1 */ } } 80042d0: bf00 nop 80042d2: 37d0 adds r7, #208 @ 0xd0 80042d4: 46bd mov sp, r7 80042d6: bd80 pop {r7, pc} 80042d8: 48021800 .word 0x48021800 80042dc: 58024400 .word 0x58024400 080042e0 : * This function configures the hardware resources used in this example * @param htim_pwm: TIM_PWM handle pointer * @retval None */ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) { 80042e0: b480 push {r7} 80042e2: b085 sub sp, #20 80042e4: af00 add r7, sp, #0 80042e6: 6078 str r0, [r7, #4] if(htim_pwm->Instance==TIM1) 80042e8: 687b ldr r3, [r7, #4] 80042ea: 681b ldr r3, [r3, #0] 80042ec: 4a16 ldr r2, [pc, #88] @ (8004348 ) 80042ee: 4293 cmp r3, r2 80042f0: d10f bne.n 8004312 { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 80042f2: 4b16 ldr r3, [pc, #88] @ (800434c ) 80042f4: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80042f8: 4a14 ldr r2, [pc, #80] @ (800434c ) 80042fa: f043 0301 orr.w r3, r3, #1 80042fe: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 8004302: 4b12 ldr r3, [pc, #72] @ (800434c ) 8004304: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8004308: f003 0301 and.w r3, r3, #1 800430c: 60fb str r3, [r7, #12] 800430e: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 8004310: e013 b.n 800433a else if(htim_pwm->Instance==TIM3) 8004312: 687b ldr r3, [r7, #4] 8004314: 681b ldr r3, [r3, #0] 8004316: 4a0e ldr r2, [pc, #56] @ (8004350 ) 8004318: 4293 cmp r3, r2 800431a: d10e bne.n 800433a __HAL_RCC_TIM3_CLK_ENABLE(); 800431c: 4b0b ldr r3, [pc, #44] @ (800434c ) 800431e: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004322: 4a0a ldr r2, [pc, #40] @ (800434c ) 8004324: f043 0302 orr.w r3, r3, #2 8004328: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 800432c: 4b07 ldr r3, [pc, #28] @ (800434c ) 800432e: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004332: f003 0302 and.w r3, r3, #2 8004336: 60bb str r3, [r7, #8] 8004338: 68bb ldr r3, [r7, #8] } 800433a: bf00 nop 800433c: 3714 adds r7, #20 800433e: 46bd mov sp, r7 8004340: f85d 7b04 ldr.w r7, [sp], #4 8004344: 4770 bx lr 8004346: bf00 nop 8004348: 40010000 .word 0x40010000 800434c: 58024400 .word 0x58024400 8004350: 40000400 .word 0x40000400 08004354 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8004354: b580 push {r7, lr} 8004356: b08c sub sp, #48 @ 0x30 8004358: af00 add r7, sp, #0 800435a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800435c: f107 031c add.w r3, r7, #28 8004360: 2200 movs r2, #0 8004362: 601a str r2, [r3, #0] 8004364: 605a str r2, [r3, #4] 8004366: 609a str r2, [r3, #8] 8004368: 60da str r2, [r3, #12] 800436a: 611a str r2, [r3, #16] if(htim_base->Instance==TIM2) 800436c: 687b ldr r3, [r7, #4] 800436e: 681b ldr r3, [r3, #0] 8004370: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8004374: d137 bne.n 80043e6 { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 8004376: 4b46 ldr r3, [pc, #280] @ (8004490 ) 8004378: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800437c: 4a44 ldr r2, [pc, #272] @ (8004490 ) 800437e: f043 0301 orr.w r3, r3, #1 8004382: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8004386: 4b42 ldr r3, [pc, #264] @ (8004490 ) 8004388: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800438c: f003 0301 and.w r3, r3, #1 8004390: 61bb str r3, [r7, #24] 8004392: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 8004394: 4b3e ldr r3, [pc, #248] @ (8004490 ) 8004396: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800439a: 4a3d ldr r2, [pc, #244] @ (8004490 ) 800439c: f043 0302 orr.w r3, r3, #2 80043a0: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80043a4: 4b3a ldr r3, [pc, #232] @ (8004490 ) 80043a6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80043aa: f003 0302 and.w r3, r3, #2 80043ae: 617b str r3, [r7, #20] 80043b0: 697b ldr r3, [r7, #20] /**TIM2 GPIO Configuration PB10 ------> TIM2_CH3 PB11 ------> TIM2_CH4 */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; 80043b2: f44f 6340 mov.w r3, #3072 @ 0xc00 80043b6: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80043b8: 2302 movs r3, #2 80043ba: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 80043bc: 2300 movs r3, #0 80043be: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80043c0: 2300 movs r3, #0 80043c2: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 80043c4: 2301 movs r3, #1 80043c6: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80043c8: f107 031c add.w r3, r7, #28 80043cc: 4619 mov r1, r3 80043ce: 4831 ldr r0, [pc, #196] @ (8004494 ) 80043d0: f006 ff40 bl 800b254 /* TIM2 interrupt Init */ HAL_NVIC_SetPriority(TIM2_IRQn, 5, 0); 80043d4: 2200 movs r2, #0 80043d6: 2105 movs r1, #5 80043d8: 201c movs r0, #28 80043da: f003 fc09 bl 8007bf0 HAL_NVIC_EnableIRQ(TIM2_IRQn); 80043de: 201c movs r0, #28 80043e0: f003 fc20 bl 8007c24 /* USER CODE BEGIN TIM8_MspInit 1 */ /* USER CODE END TIM8_MspInit 1 */ } } 80043e4: e050 b.n 8004488 else if(htim_base->Instance==TIM4) 80043e6: 687b ldr r3, [r7, #4] 80043e8: 681b ldr r3, [r3, #0] 80043ea: 4a2b ldr r2, [pc, #172] @ (8004498 ) 80043ec: 4293 cmp r3, r2 80043ee: d137 bne.n 8004460 __HAL_RCC_TIM4_CLK_ENABLE(); 80043f0: 4b27 ldr r3, [pc, #156] @ (8004490 ) 80043f2: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80043f6: 4a26 ldr r2, [pc, #152] @ (8004490 ) 80043f8: f043 0304 orr.w r3, r3, #4 80043fc: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8004400: 4b23 ldr r3, [pc, #140] @ (8004490 ) 8004402: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004406: f003 0304 and.w r3, r3, #4 800440a: 613b str r3, [r7, #16] 800440c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOD_CLK_ENABLE(); 800440e: 4b20 ldr r3, [pc, #128] @ (8004490 ) 8004410: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004414: 4a1e ldr r2, [pc, #120] @ (8004490 ) 8004416: f043 0308 orr.w r3, r3, #8 800441a: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800441e: 4b1c ldr r3, [pc, #112] @ (8004490 ) 8004420: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004424: f003 0308 and.w r3, r3, #8 8004428: 60fb str r3, [r7, #12] 800442a: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 800442c: f44f 4340 mov.w r3, #49152 @ 0xc000 8004430: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004432: 2302 movs r3, #2 8004434: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004436: 2300 movs r3, #0 8004438: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800443a: 2300 movs r3, #0 800443c: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; 800443e: 2302 movs r3, #2 8004440: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8004442: f107 031c add.w r3, r7, #28 8004446: 4619 mov r1, r3 8004448: 4814 ldr r0, [pc, #80] @ (800449c ) 800444a: f006 ff03 bl 800b254 HAL_NVIC_SetPriority(TIM4_IRQn, 5, 0); 800444e: 2200 movs r2, #0 8004450: 2105 movs r1, #5 8004452: 201e movs r0, #30 8004454: f003 fbcc bl 8007bf0 HAL_NVIC_EnableIRQ(TIM4_IRQn); 8004458: 201e movs r0, #30 800445a: f003 fbe3 bl 8007c24 } 800445e: e013 b.n 8004488 else if(htim_base->Instance==TIM8) 8004460: 687b ldr r3, [r7, #4] 8004462: 681b ldr r3, [r3, #0] 8004464: 4a0e ldr r2, [pc, #56] @ (80044a0 ) 8004466: 4293 cmp r3, r2 8004468: d10e bne.n 8004488 __HAL_RCC_TIM8_CLK_ENABLE(); 800446a: 4b09 ldr r3, [pc, #36] @ (8004490 ) 800446c: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8004470: 4a07 ldr r2, [pc, #28] @ (8004490 ) 8004472: f043 0302 orr.w r3, r3, #2 8004476: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 800447a: 4b05 ldr r3, [pc, #20] @ (8004490 ) 800447c: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8004480: f003 0302 and.w r3, r3, #2 8004484: 60bb str r3, [r7, #8] 8004486: 68bb ldr r3, [r7, #8] } 8004488: bf00 nop 800448a: 3730 adds r7, #48 @ 0x30 800448c: 46bd mov sp, r7 800448e: bd80 pop {r7, pc} 8004490: 58024400 .word 0x58024400 8004494: 58020400 .word 0x58020400 8004498: 40000800 .word 0x40000800 800449c: 58020c00 .word 0x58020c00 80044a0: 40010400 .word 0x40010400 080044a4 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 80044a4: b580 push {r7, lr} 80044a6: b08a sub sp, #40 @ 0x28 80044a8: af00 add r7, sp, #0 80044aa: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80044ac: f107 0314 add.w r3, r7, #20 80044b0: 2200 movs r2, #0 80044b2: 601a str r2, [r3, #0] 80044b4: 605a str r2, [r3, #4] 80044b6: 609a str r2, [r3, #8] 80044b8: 60da str r2, [r3, #12] 80044ba: 611a str r2, [r3, #16] if(htim->Instance==TIM1) 80044bc: 687b ldr r3, [r7, #4] 80044be: 681b ldr r3, [r3, #0] 80044c0: 4a26 ldr r2, [pc, #152] @ (800455c ) 80044c2: 4293 cmp r3, r2 80044c4: d120 bne.n 8004508 { /* USER CODE BEGIN TIM1_MspPostInit 0 */ /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 80044c6: 4b26 ldr r3, [pc, #152] @ (8004560 ) 80044c8: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80044cc: 4a24 ldr r2, [pc, #144] @ (8004560 ) 80044ce: f043 0301 orr.w r3, r3, #1 80044d2: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80044d6: 4b22 ldr r3, [pc, #136] @ (8004560 ) 80044d8: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80044dc: f003 0301 and.w r3, r3, #1 80044e0: 613b str r3, [r7, #16] 80044e2: 693b ldr r3, [r7, #16] /**TIM1 GPIO Configuration PA9 ------> TIM1_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_9; 80044e4: f44f 7300 mov.w r3, #512 @ 0x200 80044e8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80044ea: 2302 movs r3, #2 80044ec: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80044ee: 2300 movs r3, #0 80044f0: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80044f2: 2300 movs r3, #0 80044f4: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; 80044f6: 2301 movs r3, #1 80044f8: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80044fa: f107 0314 add.w r3, r7, #20 80044fe: 4619 mov r1, r3 8004500: 4818 ldr r0, [pc, #96] @ (8004564 ) 8004502: f006 fea7 bl 800b254 /* USER CODE BEGIN TIM3_MspPostInit 1 */ /* USER CODE END TIM3_MspPostInit 1 */ } } 8004506: e024 b.n 8004552 else if(htim->Instance==TIM3) 8004508: 687b ldr r3, [r7, #4] 800450a: 681b ldr r3, [r3, #0] 800450c: 4a16 ldr r2, [pc, #88] @ (8004568 ) 800450e: 4293 cmp r3, r2 8004510: d11f bne.n 8004552 __HAL_RCC_GPIOC_CLK_ENABLE(); 8004512: 4b13 ldr r3, [pc, #76] @ (8004560 ) 8004514: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004518: 4a11 ldr r2, [pc, #68] @ (8004560 ) 800451a: f043 0304 orr.w r3, r3, #4 800451e: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004522: 4b0f ldr r3, [pc, #60] @ (8004560 ) 8004524: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004528: f003 0304 and.w r3, r3, #4 800452c: 60fb str r3, [r7, #12] 800452e: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 8004530: f44f 7370 mov.w r3, #960 @ 0x3c0 8004534: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004536: 2302 movs r3, #2 8004538: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800453a: 2300 movs r3, #0 800453c: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 800453e: 2301 movs r3, #1 8004540: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 8004542: 2302 movs r3, #2 8004544: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8004546: f107 0314 add.w r3, r7, #20 800454a: 4619 mov r1, r3 800454c: 4807 ldr r0, [pc, #28] @ (800456c ) 800454e: f006 fe81 bl 800b254 } 8004552: bf00 nop 8004554: 3728 adds r7, #40 @ 0x28 8004556: 46bd mov sp, r7 8004558: bd80 pop {r7, pc} 800455a: bf00 nop 800455c: 40010000 .word 0x40010000 8004560: 58024400 .word 0x58024400 8004564: 58020000 .word 0x58020000 8004568: 40000400 .word 0x40000400 800456c: 58020800 .word 0x58020800 08004570 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8004570: b580 push {r7, lr} 8004572: b0bc sub sp, #240 @ 0xf0 8004574: af00 add r7, sp, #0 8004576: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004578: f107 03dc add.w r3, r7, #220 @ 0xdc 800457c: 2200 movs r2, #0 800457e: 601a str r2, [r3, #0] 8004580: 605a str r2, [r3, #4] 8004582: 609a str r2, [r3, #8] 8004584: 60da str r2, [r3, #12] 8004586: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8004588: f107 0318 add.w r3, r7, #24 800458c: 22c0 movs r2, #192 @ 0xc0 800458e: 2100 movs r1, #0 8004590: 4618 mov r0, r3 8004592: f013 ff01 bl 8018398 if(huart->Instance==UART8) 8004596: 687b ldr r3, [r7, #4] 8004598: 681b ldr r3, [r3, #0] 800459a: 4a55 ldr r2, [pc, #340] @ (80046f0 ) 800459c: 4293 cmp r3, r2 800459e: d14e bne.n 800463e /* USER CODE END UART8_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8; 80045a0: f04f 0202 mov.w r2, #2 80045a4: f04f 0300 mov.w r3, #0 80045a8: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 80045ac: 2300 movs r3, #0 80045ae: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80045b2: f107 0318 add.w r3, r7, #24 80045b6: 4618 mov r0, r3 80045b8: f008 fa32 bl 800ca20 80045bc: 4603 mov r3, r0 80045be: 2b00 cmp r3, #0 80045c0: d001 beq.n 80045c6 { Error_Handler(); 80045c2: f7fd fc83 bl 8001ecc } /* Peripheral clock enable */ __HAL_RCC_UART8_CLK_ENABLE(); 80045c6: 4b4b ldr r3, [pc, #300] @ (80046f4 ) 80045c8: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80045cc: 4a49 ldr r2, [pc, #292] @ (80046f4 ) 80045ce: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80045d2: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 80045d6: 4b47 ldr r3, [pc, #284] @ (80046f4 ) 80045d8: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80045dc: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80045e0: 617b str r3, [r7, #20] 80045e2: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOE_CLK_ENABLE(); 80045e4: 4b43 ldr r3, [pc, #268] @ (80046f4 ) 80045e6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80045ea: 4a42 ldr r2, [pc, #264] @ (80046f4 ) 80045ec: f043 0310 orr.w r3, r3, #16 80045f0: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80045f4: 4b3f ldr r3, [pc, #252] @ (80046f4 ) 80045f6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80045fa: f003 0310 and.w r3, r3, #16 80045fe: 613b str r3, [r7, #16] 8004600: 693b ldr r3, [r7, #16] /**UART8 GPIO Configuration PE0 ------> UART8_RX PE1 ------> UART8_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8004602: 2303 movs r3, #3 8004604: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004608: 2302 movs r3, #2 800460a: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 800460e: 2300 movs r3, #0 8004610: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8004614: 2300 movs r3, #0 8004616: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF8_UART8; 800461a: 2308 movs r3, #8 800461c: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8004620: f107 03dc add.w r3, r7, #220 @ 0xdc 8004624: 4619 mov r1, r3 8004626: 4834 ldr r0, [pc, #208] @ (80046f8 ) 8004628: f006 fe14 bl 800b254 /* UART8 interrupt Init */ HAL_NVIC_SetPriority(UART8_IRQn, 5, 0); 800462c: 2200 movs r2, #0 800462e: 2105 movs r1, #5 8004630: 2053 movs r0, #83 @ 0x53 8004632: f003 fadd bl 8007bf0 HAL_NVIC_EnableIRQ(UART8_IRQn); 8004636: 2053 movs r0, #83 @ 0x53 8004638: f003 faf4 bl 8007c24 /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 800463c: e053 b.n 80046e6 else if(huart->Instance==USART1) 800463e: 687b ldr r3, [r7, #4] 8004640: 681b ldr r3, [r3, #0] 8004642: 4a2e ldr r2, [pc, #184] @ (80046fc ) 8004644: 4293 cmp r3, r2 8004646: d14e bne.n 80046e6 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; 8004648: f04f 0201 mov.w r2, #1 800464c: f04f 0300 mov.w r3, #0 8004650: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; 8004654: 2300 movs r3, #0 8004656: f8c7 3094 str.w r3, [r7, #148] @ 0x94 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800465a: f107 0318 add.w r3, r7, #24 800465e: 4618 mov r0, r3 8004660: f008 f9de bl 800ca20 8004664: 4603 mov r3, r0 8004666: 2b00 cmp r3, #0 8004668: d001 beq.n 800466e Error_Handler(); 800466a: f7fd fc2f bl 8001ecc __HAL_RCC_USART1_CLK_ENABLE(); 800466e: 4b21 ldr r3, [pc, #132] @ (80046f4 ) 8004670: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8004674: 4a1f ldr r2, [pc, #124] @ (80046f4 ) 8004676: f043 0310 orr.w r3, r3, #16 800467a: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 800467e: 4b1d ldr r3, [pc, #116] @ (80046f4 ) 8004680: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8004684: f003 0310 and.w r3, r3, #16 8004688: 60fb str r3, [r7, #12] 800468a: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 800468c: 4b19 ldr r3, [pc, #100] @ (80046f4 ) 800468e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004692: 4a18 ldr r2, [pc, #96] @ (80046f4 ) 8004694: f043 0302 orr.w r3, r3, #2 8004698: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800469c: 4b15 ldr r3, [pc, #84] @ (80046f4 ) 800469e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80046a2: f003 0302 and.w r3, r3, #2 80046a6: 60bb str r3, [r7, #8] 80046a8: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 80046aa: f44f 4340 mov.w r3, #49152 @ 0xc000 80046ae: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80046b2: 2302 movs r3, #2 80046b4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 80046b8: 2300 movs r3, #0 80046ba: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80046be: 2300 movs r3, #0 80046c0: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF4_USART1; 80046c4: 2304 movs r3, #4 80046c6: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80046ca: f107 03dc add.w r3, r7, #220 @ 0xdc 80046ce: 4619 mov r1, r3 80046d0: 480b ldr r0, [pc, #44] @ (8004700 ) 80046d2: f006 fdbf bl 800b254 HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 80046d6: 2200 movs r2, #0 80046d8: 2105 movs r1, #5 80046da: 2025 movs r0, #37 @ 0x25 80046dc: f003 fa88 bl 8007bf0 HAL_NVIC_EnableIRQ(USART1_IRQn); 80046e0: 2025 movs r0, #37 @ 0x25 80046e2: f003 fa9f bl 8007c24 } 80046e6: bf00 nop 80046e8: 37f0 adds r7, #240 @ 0xf0 80046ea: 46bd mov sp, r7 80046ec: bd80 pop {r7, pc} 80046ee: bf00 nop 80046f0: 40007c00 .word 0x40007c00 80046f4: 58024400 .word 0x58024400 80046f8: 58021000 .word 0x58021000 80046fc: 40011000 .word 0x40011000 8004700: 58020400 .word 0x58020400 08004704 : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8004704: b580 push {r7, lr} 8004706: b090 sub sp, #64 @ 0x40 8004708: af00 add r7, sp, #0 800470a: 6078 str r0, [r7, #4] uint32_t uwTimclock, uwAPB1Prescaler; uint32_t uwPrescalerValue; uint32_t pFLatency; /*Configure the TIM6 IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800470c: 687b ldr r3, [r7, #4] 800470e: 2b0f cmp r3, #15 8004710: d827 bhi.n 8004762 { HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U); 8004712: 2200 movs r2, #0 8004714: 6879 ldr r1, [r7, #4] 8004716: 2036 movs r0, #54 @ 0x36 8004718: f003 fa6a bl 8007bf0 /* Enable the TIM6 global Interrupt */ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 800471c: 2036 movs r0, #54 @ 0x36 800471e: f003 fa81 bl 8007c24 uwTickPrio = TickPriority; 8004722: 4a29 ldr r2, [pc, #164] @ (80047c8 ) 8004724: 687b ldr r3, [r7, #4] 8004726: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Enable TIM6 clock */ __HAL_RCC_TIM6_CLK_ENABLE(); 8004728: 4b28 ldr r3, [pc, #160] @ (80047cc ) 800472a: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800472e: 4a27 ldr r2, [pc, #156] @ (80047cc ) 8004730: f043 0310 orr.w r3, r3, #16 8004734: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8004738: 4b24 ldr r3, [pc, #144] @ (80047cc ) 800473a: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800473e: f003 0310 and.w r3, r3, #16 8004742: 60fb str r3, [r7, #12] 8004744: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 8004746: f107 0210 add.w r2, r7, #16 800474a: f107 0314 add.w r3, r7, #20 800474e: 4611 mov r1, r2 8004750: 4618 mov r0, r3 8004752: f008 f923 bl 800c99c /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; 8004756: 6abb ldr r3, [r7, #40] @ 0x28 8004758: 63bb str r3, [r7, #56] @ 0x38 /* Compute TIM6 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) 800475a: 6bbb ldr r3, [r7, #56] @ 0x38 800475c: 2b00 cmp r3, #0 800475e: d106 bne.n 800476e 8004760: e001 b.n 8004766 return HAL_ERROR; 8004762: 2301 movs r3, #1 8004764: e02b b.n 80047be { uwTimclock = HAL_RCC_GetPCLK1Freq(); 8004766: f008 f8ed bl 800c944 800476a: 63f8 str r0, [r7, #60] @ 0x3c 800476c: e004 b.n 8004778 } else { uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); 800476e: f008 f8e9 bl 800c944 8004772: 4603 mov r3, r0 8004774: 005b lsls r3, r3, #1 8004776: 63fb str r3, [r7, #60] @ 0x3c } /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 8004778: 6bfb ldr r3, [r7, #60] @ 0x3c 800477a: 4a15 ldr r2, [pc, #84] @ (80047d0 ) 800477c: fba2 2303 umull r2, r3, r2, r3 8004780: 0c9b lsrs r3, r3, #18 8004782: 3b01 subs r3, #1 8004784: 637b str r3, [r7, #52] @ 0x34 /* Initialize TIM6 */ htim6.Instance = TIM6; 8004786: 4b13 ldr r3, [pc, #76] @ (80047d4 ) 8004788: 4a13 ldr r2, [pc, #76] @ (80047d8 ) 800478a: 601a str r2, [r3, #0] + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up */ htim6.Init.Period = (1000000U / 1000U) - 1U; 800478c: 4b11 ldr r3, [pc, #68] @ (80047d4 ) 800478e: f240 32e7 movw r2, #999 @ 0x3e7 8004792: 60da str r2, [r3, #12] htim6.Init.Prescaler = uwPrescalerValue; 8004794: 4a0f ldr r2, [pc, #60] @ (80047d4 ) 8004796: 6b7b ldr r3, [r7, #52] @ 0x34 8004798: 6053 str r3, [r2, #4] htim6.Init.ClockDivision = 0; 800479a: 4b0e ldr r3, [pc, #56] @ (80047d4 ) 800479c: 2200 movs r2, #0 800479e: 611a str r2, [r3, #16] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 80047a0: 4b0c ldr r3, [pc, #48] @ (80047d4 ) 80047a2: 2200 movs r2, #0 80047a4: 609a str r2, [r3, #8] if(HAL_TIM_Base_Init(&htim6) == HAL_OK) 80047a6: 480b ldr r0, [pc, #44] @ (80047d4 ) 80047a8: f00a fe7e bl 800f4a8 80047ac: 4603 mov r3, r0 80047ae: 2b00 cmp r3, #0 80047b0: d104 bne.n 80047bc { /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&htim6); 80047b2: 4808 ldr r0, [pc, #32] @ (80047d4 ) 80047b4: f00a ff40 bl 800f638 80047b8: 4603 mov r3, r0 80047ba: e000 b.n 80047be } /* Return function status */ return HAL_ERROR; 80047bc: 2301 movs r3, #1 } 80047be: 4618 mov r0, r3 80047c0: 3740 adds r7, #64 @ 0x40 80047c2: 46bd mov sp, r7 80047c4: bd80 pop {r7, pc} 80047c6: bf00 nop 80047c8: 2400003c .word 0x2400003c 80047cc: 58024400 .word 0x58024400 80047d0: 431bde83 .word 0x431bde83 80047d4: 24000920 .word 0x24000920 80047d8: 40001000 .word 0x40001000 080047dc : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80047dc: b480 push {r7} 80047de: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80047e0: bf00 nop 80047e2: e7fd b.n 80047e0 080047e4 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80047e4: b480 push {r7} 80047e6: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80047e8: bf00 nop 80047ea: e7fd b.n 80047e8 080047ec : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80047ec: b480 push {r7} 80047ee: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80047f0: bf00 nop 80047f2: e7fd b.n 80047f0 080047f4 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 80047f4: b480 push {r7} 80047f6: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80047f8: bf00 nop 80047fa: e7fd b.n 80047f8 080047fc : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80047fc: b480 push {r7} 80047fe: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8004800: bf00 nop 8004802: e7fd b.n 8004800 08004804 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8004804: b480 push {r7} 8004806: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8004808: bf00 nop 800480a: 46bd mov sp, r7 800480c: f85d 7b04 ldr.w r7, [sp], #4 8004810: 4770 bx lr 08004812 : /** * @brief This function handles RCC global interrupt. */ void RCC_IRQHandler(void) { 8004812: b480 push {r7} 8004814: af00 add r7, sp, #0 /* USER CODE END RCC_IRQn 0 */ /* USER CODE BEGIN RCC_IRQn 1 */ /* USER CODE END RCC_IRQn 1 */ } 8004816: bf00 nop 8004818: 46bd mov sp, r7 800481a: f85d 7b04 ldr.w r7, [sp], #4 800481e: 4770 bx lr 08004820 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 8004820: b580 push {r7, lr} 8004822: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 8004824: 4802 ldr r0, [pc, #8] @ (8004830 ) 8004826: f005 fa03 bl 8009c30 /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 800482a: bf00 nop 800482c: bd80 pop {r7, pc} 800482e: bf00 nop 8004830: 2400024c .word 0x2400024c 08004834 : /** * @brief This function handles DMA1 stream1 global interrupt. */ void DMA1_Stream1_IRQHandler(void) { 8004834: b580 push {r7, lr} 8004836: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */ /* USER CODE END DMA1_Stream1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc2); 8004838: 4802 ldr r0, [pc, #8] @ (8004844 ) 800483a: f005 f9f9 bl 8009c30 /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */ /* USER CODE END DMA1_Stream1_IRQn 1 */ } 800483e: bf00 nop 8004840: bd80 pop {r7, pc} 8004842: bf00 nop 8004844: 240002c4 .word 0x240002c4 08004848 : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 8004848: b580 push {r7, lr} 800484a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc3); 800484c: 4802 ldr r0, [pc, #8] @ (8004858 ) 800484e: f005 f9ef bl 8009c30 /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 8004852: bf00 nop 8004854: bd80 pop {r7, pc} 8004856: bf00 nop 8004858: 2400033c .word 0x2400033c 0800485c : /** * @brief This function handles EXTI line[9:5] interrupts. */ void EXTI9_5_IRQHandler(void) { 800485c: b580 push {r7, lr} 800485e: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI9_5_IRQn 0 */ /* USER CODE END EXTI9_5_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8); 8004860: f44f 7080 mov.w r0, #256 @ 0x100 8004864: f006 fef1 bl 800b64a HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9); 8004868: f44f 7000 mov.w r0, #512 @ 0x200 800486c: f006 feed bl 800b64a /* USER CODE BEGIN EXTI9_5_IRQn 1 */ /* USER CODE END EXTI9_5_IRQn 1 */ } 8004870: bf00 nop 8004872: bd80 pop {r7, pc} 08004874 : /** * @brief This function handles TIM2 global interrupt. */ void TIM2_IRQHandler(void) { 8004874: b580 push {r7, lr} 8004876: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_IRQn 0 */ /* USER CODE END TIM2_IRQn 0 */ HAL_TIM_IRQHandler(&htim2); 8004878: 4802 ldr r0, [pc, #8] @ (8004884 ) 800487a: f00b fb03 bl 800fe84 /* USER CODE BEGIN TIM2_IRQn 1 */ /* USER CODE END TIM2_IRQn 1 */ } 800487e: bf00 nop 8004880: bd80 pop {r7, pc} 8004882: bf00 nop 8004884: 24000488 .word 0x24000488 08004888 : /** * @brief This function handles TIM4 global interrupt. */ void TIM4_IRQHandler(void) { 8004888: b580 push {r7, lr} 800488a: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_IRQn 0 */ /* USER CODE END TIM4_IRQn 0 */ HAL_TIM_IRQHandler(&htim4); 800488c: 4802 ldr r0, [pc, #8] @ (8004898 ) 800488e: f00b faf9 bl 800fe84 /* USER CODE BEGIN TIM4_IRQn 1 */ /* USER CODE END TIM4_IRQn 1 */ } 8004892: bf00 nop 8004894: bd80 pop {r7, pc} 8004896: bf00 nop 8004898: 24000520 .word 0x24000520 0800489c : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 800489c: b580 push {r7, lr} 800489e: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 80048a0: 4802 ldr r0, [pc, #8] @ (80048ac ) 80048a2: f00c feb3 bl 801160c /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 80048a6: bf00 nop 80048a8: bd80 pop {r7, pc} 80048aa: bf00 nop 80048ac: 2400064c .word 0x2400064c 080048b0 : /** * @brief This function handles EXTI line[15:10] interrupts. */ void EXTI15_10_IRQHandler(void) { 80048b0: b580 push {r7, lr} 80048b2: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI15_10_IRQn 0 */ /* USER CODE END EXTI15_10_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10); 80048b4: f44f 6080 mov.w r0, #1024 @ 0x400 80048b8: f006 fec7 bl 800b64a HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); 80048bc: f44f 6000 mov.w r0, #2048 @ 0x800 80048c0: f006 fec3 bl 800b64a HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); 80048c4: f44f 5080 mov.w r0, #4096 @ 0x1000 80048c8: f006 febf bl 800b64a HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13); 80048cc: f44f 5000 mov.w r0, #8192 @ 0x2000 80048d0: f006 febb bl 800b64a /* USER CODE BEGIN EXTI15_10_IRQn 1 */ /* USER CODE END EXTI15_10_IRQn 1 */ } 80048d4: bf00 nop 80048d6: bd80 pop {r7, pc} 080048d8 : /** * @brief This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 80048d8: b580 push {r7, lr} 80048da: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ if (hdac1.State != HAL_DAC_STATE_RESET) { 80048dc: 4b06 ldr r3, [pc, #24] @ (80048f8 ) 80048de: 791b ldrb r3, [r3, #4] 80048e0: b2db uxtb r3, r3 80048e2: 2b00 cmp r3, #0 80048e4: d002 beq.n 80048ec HAL_DAC_IRQHandler(&hdac1); 80048e6: 4804 ldr r0, [pc, #16] @ (80048f8 ) 80048e8: f003 fca1 bl 800822e } HAL_TIM_IRQHandler(&htim6); 80048ec: 4803 ldr r0, [pc, #12] @ (80048fc ) 80048ee: f00b fac9 bl 800fe84 /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 80048f2: bf00 nop 80048f4: bd80 pop {r7, pc} 80048f6: bf00 nop 80048f8: 24000404 .word 0x24000404 80048fc: 24000920 .word 0x24000920 08004900 : /** * @brief This function handles UART8 global interrupt. */ void UART8_IRQHandler(void) { 8004900: b580 push {r7, lr} 8004902: af00 add r7, sp, #0 /* USER CODE BEGIN UART8_IRQn 0 */ /* USER CODE END UART8_IRQn 0 */ HAL_UART_IRQHandler(&huart8); 8004904: 4802 ldr r0, [pc, #8] @ (8004910 ) 8004906: f00c fe81 bl 801160c /* USER CODE BEGIN UART8_IRQn 1 */ /* USER CODE END UART8_IRQn 1 */ } 800490a: bf00 nop 800490c: bd80 pop {r7, pc} 800490e: bf00 nop 8004910: 240005b8 .word 0x240005b8 08004914 : * configuration. * @param None * @retval None */ void SystemInit (void) { 8004914: b480 push {r7} 8004916: af00 add r7, sp, #0 __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8004918: 4b37 ldr r3, [pc, #220] @ (80049f8 ) 800491a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800491e: 4a36 ldr r2, [pc, #216] @ (80049f8 ) 8004920: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8004924: f8c2 3088 str.w r3, [r2, #136] @ 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8004928: 4b34 ldr r3, [pc, #208] @ (80049fc ) 800492a: 681b ldr r3, [r3, #0] 800492c: f003 030f and.w r3, r3, #15 8004930: 2b06 cmp r3, #6 8004932: d807 bhi.n 8004944 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8004934: 4b31 ldr r3, [pc, #196] @ (80049fc ) 8004936: 681b ldr r3, [r3, #0] 8004938: f023 030f bic.w r3, r3, #15 800493c: 4a2f ldr r2, [pc, #188] @ (80049fc ) 800493e: f043 0307 orr.w r3, r3, #7 8004942: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 8004944: 4b2e ldr r3, [pc, #184] @ (8004a00 ) 8004946: 681b ldr r3, [r3, #0] 8004948: 4a2d ldr r2, [pc, #180] @ (8004a00 ) 800494a: f043 0301 orr.w r3, r3, #1 800494e: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 8004950: 4b2b ldr r3, [pc, #172] @ (8004a00 ) 8004952: 2200 movs r2, #0 8004954: 611a str r2, [r3, #16] /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 8004956: 4b2a ldr r3, [pc, #168] @ (8004a00 ) 8004958: 681a ldr r2, [r3, #0] 800495a: 4929 ldr r1, [pc, #164] @ (8004a00 ) 800495c: 4b29 ldr r3, [pc, #164] @ (8004a04 ) 800495e: 4013 ands r3, r2 8004960: 600b str r3, [r1, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8004962: 4b26 ldr r3, [pc, #152] @ (80049fc ) 8004964: 681b ldr r3, [r3, #0] 8004966: f003 0308 and.w r3, r3, #8 800496a: 2b00 cmp r3, #0 800496c: d007 beq.n 800497e { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 800496e: 4b23 ldr r3, [pc, #140] @ (80049fc ) 8004970: 681b ldr r3, [r3, #0] 8004972: f023 030f bic.w r3, r3, #15 8004976: 4a21 ldr r2, [pc, #132] @ (80049fc ) 8004978: f043 0307 orr.w r3, r3, #7 800497c: 6013 str r3, [r2, #0] } #if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; 800497e: 4b20 ldr r3, [pc, #128] @ (8004a00 ) 8004980: 2200 movs r2, #0 8004982: 619a str r2, [r3, #24] /* Reset D2CFGR register */ RCC->D2CFGR = 0x00000000; 8004984: 4b1e ldr r3, [pc, #120] @ (8004a00 ) 8004986: 2200 movs r2, #0 8004988: 61da str r2, [r3, #28] /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; 800498a: 4b1d ldr r3, [pc, #116] @ (8004a00 ) 800498c: 2200 movs r2, #0 800498e: 621a str r2, [r3, #32] /* Reset SRDCFGR register */ RCC->SRDCFGR = 0x00000000; #endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; 8004990: 4b1b ldr r3, [pc, #108] @ (8004a00 ) 8004992: 4a1d ldr r2, [pc, #116] @ (8004a08 ) 8004994: 629a str r2, [r3, #40] @ 0x28 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; 8004996: 4b1a ldr r3, [pc, #104] @ (8004a00 ) 8004998: 4a1c ldr r2, [pc, #112] @ (8004a0c ) 800499a: 62da str r2, [r3, #44] @ 0x2c /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 800499c: 4b18 ldr r3, [pc, #96] @ (8004a00 ) 800499e: 4a1c ldr r2, [pc, #112] @ (8004a10 ) 80049a0: 631a str r2, [r3, #48] @ 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 80049a2: 4b17 ldr r3, [pc, #92] @ (8004a00 ) 80049a4: 2200 movs r2, #0 80049a6: 635a str r2, [r3, #52] @ 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 80049a8: 4b15 ldr r3, [pc, #84] @ (8004a00 ) 80049aa: 4a19 ldr r2, [pc, #100] @ (8004a10 ) 80049ac: 639a str r2, [r3, #56] @ 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 80049ae: 4b14 ldr r3, [pc, #80] @ (8004a00 ) 80049b0: 2200 movs r2, #0 80049b2: 63da str r2, [r3, #60] @ 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 80049b4: 4b12 ldr r3, [pc, #72] @ (8004a00 ) 80049b6: 4a16 ldr r2, [pc, #88] @ (8004a10 ) 80049b8: 641a str r2, [r3, #64] @ 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 80049ba: 4b11 ldr r3, [pc, #68] @ (8004a00 ) 80049bc: 2200 movs r2, #0 80049be: 645a str r2, [r3, #68] @ 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 80049c0: 4b0f ldr r3, [pc, #60] @ (8004a00 ) 80049c2: 681b ldr r3, [r3, #0] 80049c4: 4a0e ldr r2, [pc, #56] @ (8004a00 ) 80049c6: f423 2380 bic.w r3, r3, #262144 @ 0x40000 80049ca: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 80049cc: 4b0c ldr r3, [pc, #48] @ (8004a00 ) 80049ce: 2200 movs r2, #0 80049d0: 661a str r2, [r3, #96] @ 0x60 #if (STM32H7_DEV_ID == 0x450UL) /* dual core CM7 or single core line */ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) 80049d2: 4b10 ldr r3, [pc, #64] @ (8004a14 ) 80049d4: 681a ldr r2, [r3, #0] 80049d6: 4b10 ldr r3, [pc, #64] @ (8004a18 ) 80049d8: 4013 ands r3, r2 80049da: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80049de: d202 bcs.n 80049e6 { /* if stm32h7 revY*/ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; 80049e0: 4b0e ldr r3, [pc, #56] @ (8004a1c ) 80049e2: 2201 movs r2, #1 80049e4: 601a str r2, [r3, #0] /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 80049e6: 4b0e ldr r3, [pc, #56] @ (8004a20 ) 80049e8: f243 02d2 movw r2, #12498 @ 0x30d2 80049ec: 601a str r2, [r3, #0] #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ } 80049ee: bf00 nop 80049f0: 46bd mov sp, r7 80049f2: f85d 7b04 ldr.w r7, [sp], #4 80049f6: 4770 bx lr 80049f8: e000ed00 .word 0xe000ed00 80049fc: 52002000 .word 0x52002000 8004a00: 58024400 .word 0x58024400 8004a04: eaf6ed7f .word 0xeaf6ed7f 8004a08: 02020200 .word 0x02020200 8004a0c: 01ff0000 .word 0x01ff0000 8004a10: 01010280 .word 0x01010280 8004a14: 5c001000 .word 0x5c001000 8004a18: ffff0000 .word 0xffff0000 8004a1c: 51008108 .word 0x51008108 8004a20: 52004000 .word 0x52004000 08004a24 <__NVIC_SystemReset>: { 8004a24: b480 push {r7} 8004a26: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 8004a28: f3bf 8f4f dsb sy } 8004a2c: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 8004a2e: 4b06 ldr r3, [pc, #24] @ (8004a48 <__NVIC_SystemReset+0x24>) 8004a30: 68db ldr r3, [r3, #12] 8004a32: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8004a36: 4904 ldr r1, [pc, #16] @ (8004a48 <__NVIC_SystemReset+0x24>) 8004a38: 4b04 ldr r3, [pc, #16] @ (8004a4c <__NVIC_SystemReset+0x28>) 8004a3a: 4313 orrs r3, r2 8004a3c: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 8004a3e: f3bf 8f4f dsb sy } 8004a42: bf00 nop __NOP(); 8004a44: bf00 nop 8004a46: e7fd b.n 8004a44 <__NVIC_SystemReset+0x20> 8004a48: e000ed00 .word 0xe000ed00 8004a4c: 05fa0004 .word 0x05fa0004 08004a50 : uint8_t outputDataBuffer[OUTPUT_DATA_BUFF_SIZE]; uint16_t outputDataBufferPos = 0; extern RNG_HandleTypeDef hrng; void UartTasksInit (void) { 8004a50: b580 push {r7, lr} 8004a52: af00 add r7, sp, #0 uart1TaskData.uartRxBuffer = uart1RxBuffer; 8004a54: 4b24 ldr r3, [pc, #144] @ (8004ae8 ) 8004a56: 4a25 ldr r2, [pc, #148] @ (8004aec ) 8004a58: 601a str r2, [r3, #0] uart1TaskData.uartRxBufferLen = UART1_RX_BUFF_SIZE; 8004a5a: 4b23 ldr r3, [pc, #140] @ (8004ae8 ) 8004a5c: f44f 7280 mov.w r2, #256 @ 0x100 8004a60: 809a strh r2, [r3, #4] uart1TaskData.uartTxBuffer = uart1TxBuffer; 8004a62: 4b21 ldr r3, [pc, #132] @ (8004ae8 ) 8004a64: 4a22 ldr r2, [pc, #136] @ (8004af0 ) 8004a66: 609a str r2, [r3, #8] uart1TaskData.uartRxBufferLen = UART1_TX_BUFF_SIZE; 8004a68: 4b1f ldr r3, [pc, #124] @ (8004ae8 ) 8004a6a: f44f 7280 mov.w r2, #256 @ 0x100 8004a6e: 809a strh r2, [r3, #4] uart1TaskData.frameData = uart1TaskFrameData; 8004a70: 4b1d ldr r3, [pc, #116] @ (8004ae8 ) 8004a72: 4a20 ldr r2, [pc, #128] @ (8004af4 ) 8004a74: 611a str r2, [r3, #16] uart1TaskData.frameDataLen = UART1_RX_BUFF_SIZE; 8004a76: 4b1c ldr r3, [pc, #112] @ (8004ae8 ) 8004a78: f44f 7280 mov.w r2, #256 @ 0x100 8004a7c: 829a strh r2, [r3, #20] uart1TaskData.huart = &huart1; 8004a7e: 4b1a ldr r3, [pc, #104] @ (8004ae8 ) 8004a80: 4a1d ldr r2, [pc, #116] @ (8004af8 ) 8004a82: 631a str r2, [r3, #48] @ 0x30 uart1TaskData.uartNumber = 1; 8004a84: 4b18 ldr r3, [pc, #96] @ (8004ae8 ) 8004a86: 2201 movs r2, #1 8004a88: f883 2034 strb.w r2, [r3, #52] @ 0x34 uart1TaskData.processDataCb = Uart1ReceivedDataProcessCallback; 8004a8c: 4b16 ldr r3, [pc, #88] @ (8004ae8 ) 8004a8e: 4a1b ldr r2, [pc, #108] @ (8004afc ) 8004a90: 629a str r2, [r3, #40] @ 0x28 uart1TaskData.processRxDataMsgBuffer = NULL; 8004a92: 4b15 ldr r3, [pc, #84] @ (8004ae8 ) 8004a94: 2200 movs r2, #0 8004a96: 625a str r2, [r3, #36] @ 0x24 uart8TaskData.uartRxBuffer = uart8RxBuffer; 8004a98: 4b19 ldr r3, [pc, #100] @ (8004b00 ) 8004a9a: 4a1a ldr r2, [pc, #104] @ (8004b04 ) 8004a9c: 601a str r2, [r3, #0] uart8TaskData.uartRxBufferLen = UART8_RX_BUFF_SIZE; 8004a9e: 4b18 ldr r3, [pc, #96] @ (8004b00 ) 8004aa0: f44f 7280 mov.w r2, #256 @ 0x100 8004aa4: 809a strh r2, [r3, #4] uart8TaskData.uartTxBuffer = uart8TxBuffer; 8004aa6: 4b16 ldr r3, [pc, #88] @ (8004b00 ) 8004aa8: 4a17 ldr r2, [pc, #92] @ (8004b08 ) 8004aaa: 609a str r2, [r3, #8] uart8TaskData.uartRxBufferLen = UART8_TX_BUFF_SIZE; 8004aac: 4b14 ldr r3, [pc, #80] @ (8004b00 ) 8004aae: f44f 7280 mov.w r2, #256 @ 0x100 8004ab2: 809a strh r2, [r3, #4] uart8TaskData.frameData = uart8TaskFrameData; 8004ab4: 4b12 ldr r3, [pc, #72] @ (8004b00 ) 8004ab6: 4a15 ldr r2, [pc, #84] @ (8004b0c ) 8004ab8: 611a str r2, [r3, #16] uart8TaskData.frameDataLen = UART8_RX_BUFF_SIZE; 8004aba: 4b11 ldr r3, [pc, #68] @ (8004b00 ) 8004abc: f44f 7280 mov.w r2, #256 @ 0x100 8004ac0: 829a strh r2, [r3, #20] uart8TaskData.huart = &huart8; 8004ac2: 4b0f ldr r3, [pc, #60] @ (8004b00 ) 8004ac4: 4a12 ldr r2, [pc, #72] @ (8004b10 ) 8004ac6: 631a str r2, [r3, #48] @ 0x30 uart8TaskData.uartNumber = 8; 8004ac8: 4b0d ldr r3, [pc, #52] @ (8004b00 ) 8004aca: 2208 movs r2, #8 8004acc: f883 2034 strb.w r2, [r3, #52] @ 0x34 uart8TaskData.processDataCb = Uart8ReceivedDataProcessCallback; 8004ad0: 4b0b ldr r3, [pc, #44] @ (8004b00 ) 8004ad2: 4a10 ldr r2, [pc, #64] @ (8004b14 ) 8004ad4: 629a str r2, [r3, #40] @ 0x28 uart8TaskData.processRxDataMsgBuffer = NULL; 8004ad6: 4b0a ldr r3, [pc, #40] @ (8004b00 ) 8004ad8: 2200 movs r2, #0 8004ada: 625a str r2, [r3, #36] @ 0x24 #ifdef USE_UART8_INSTEAD_UART1 UartTaskCreate (&uart8TaskData); #else UartTaskCreate (&uart1TaskData); 8004adc: 4802 ldr r0, [pc, #8] @ (8004ae8 ) 8004ade: f000 f81b bl 8004b18 #endif } 8004ae2: bf00 nop 8004ae4: bd80 pop {r7, pc} 8004ae6: bf00 nop 8004ae8: 24000f6c .word 0x24000f6c 8004aec: 2400096c .word 0x2400096c 8004af0: 24000a6c .word 0x24000a6c 8004af4: 24000b6c .word 0x24000b6c 8004af8: 2400064c .word 0x2400064c 8004afc: 080051c1 .word 0x080051c1 8004b00: 24000fa4 .word 0x24000fa4 8004b04: 24000c6c .word 0x24000c6c 8004b08: 24000d6c .word 0x24000d6c 8004b0c: 24000e6c .word 0x24000e6c 8004b10: 240005b8 .word 0x240005b8 8004b14: 080051a5 .word 0x080051a5 08004b18 : void UartTaskCreate (UartTaskData* uartTaskData) { 8004b18: b580 push {r7, lr} 8004b1a: b08c sub sp, #48 @ 0x30 8004b1c: af00 add r7, sp, #0 8004b1e: 6078 str r0, [r7, #4] osThreadAttr_t osThreadAttrRxUart = { 0 }; 8004b20: f107 030c add.w r3, r7, #12 8004b24: 2224 movs r2, #36 @ 0x24 8004b26: 2100 movs r1, #0 8004b28: 4618 mov r0, r3 8004b2a: f013 fc35 bl 8018398 osThreadAttrRxUart.stack_size = configMINIMAL_STACK_SIZE * 2; 8004b2e: f44f 6380 mov.w r3, #1024 @ 0x400 8004b32: 623b str r3, [r7, #32] osThreadAttrRxUart.priority = (osPriority_t)osPriorityHigh; 8004b34: 2328 movs r3, #40 @ 0x28 8004b36: 627b str r3, [r7, #36] @ 0x24 uartTaskData->uartRecieveTaskHandle = osThreadNew (UartRxTask, uartTaskData, &osThreadAttrRxUart); 8004b38: f107 030c add.w r3, r7, #12 8004b3c: 461a mov r2, r3 8004b3e: 6879 ldr r1, [r7, #4] 8004b40: 4804 ldr r0, [pc, #16] @ (8004b54 ) 8004b42: f00f fad1 bl 80140e8 8004b46: 4602 mov r2, r0 8004b48: 687b ldr r3, [r7, #4] 8004b4a: 619a str r2, [r3, #24] } 8004b4c: bf00 nop 8004b4e: 3730 adds r7, #48 @ 0x30 8004b50: 46bd mov sp, r7 8004b52: bd80 pop {r7, pc} 8004b54: 08004c6d .word 0x08004c6d 08004b58 : void HAL_UART_RxCpltCallback (UART_HandleTypeDef* huart) { 8004b58: b480 push {r7} 8004b5a: b083 sub sp, #12 8004b5c: af00 add r7, sp, #0 8004b5e: 6078 str r0, [r7, #4] } 8004b60: bf00 nop 8004b62: 370c adds r7, #12 8004b64: 46bd mov sp, r7 8004b66: f85d 7b04 ldr.w r7, [sp], #4 8004b6a: 4770 bx lr 08004b6c : void HAL_UARTEx_RxEventCallback (UART_HandleTypeDef* huart, uint16_t Size) { 8004b6c: b580 push {r7, lr} 8004b6e: b082 sub sp, #8 8004b70: af00 add r7, sp, #0 8004b72: 6078 str r0, [r7, #4] 8004b74: 460b mov r3, r1 8004b76: 807b strh r3, [r7, #2] if (huart->Instance == USART1) { 8004b78: 687b ldr r3, [r7, #4] 8004b7a: 681b ldr r3, [r3, #0] 8004b7c: 4a0c ldr r2, [pc, #48] @ (8004bb0 ) 8004b7e: 4293 cmp r3, r2 8004b80: d106 bne.n 8004b90 HandleUartRxCallback (&uart1TaskData, huart, Size); 8004b82: 887b ldrh r3, [r7, #2] 8004b84: 461a mov r2, r3 8004b86: 6879 ldr r1, [r7, #4] 8004b88: 480a ldr r0, [pc, #40] @ (8004bb4 ) 8004b8a: f000 f823 bl 8004bd4 } else if (huart->Instance == UART8) { HandleUartRxCallback (&uart8TaskData, huart, Size); } } 8004b8e: e00a b.n 8004ba6 } else if (huart->Instance == UART8) { 8004b90: 687b ldr r3, [r7, #4] 8004b92: 681b ldr r3, [r3, #0] 8004b94: 4a08 ldr r2, [pc, #32] @ (8004bb8 ) 8004b96: 4293 cmp r3, r2 8004b98: d105 bne.n 8004ba6 HandleUartRxCallback (&uart8TaskData, huart, Size); 8004b9a: 887b ldrh r3, [r7, #2] 8004b9c: 461a mov r2, r3 8004b9e: 6879 ldr r1, [r7, #4] 8004ba0: 4806 ldr r0, [pc, #24] @ (8004bbc ) 8004ba2: f000 f817 bl 8004bd4 } 8004ba6: bf00 nop 8004ba8: 3708 adds r7, #8 8004baa: 46bd mov sp, r7 8004bac: bd80 pop {r7, pc} 8004bae: bf00 nop 8004bb0: 40011000 .word 0x40011000 8004bb4: 24000f6c .word 0x24000f6c 8004bb8: 40007c00 .word 0x40007c00 8004bbc: 24000fa4 .word 0x24000fa4 08004bc0 : void HAL_UART_TxCpltCallback (UART_HandleTypeDef* huart) { 8004bc0: b480 push {r7} 8004bc2: b083 sub sp, #12 8004bc4: af00 add r7, sp, #0 8004bc6: 6078 str r0, [r7, #4] if (huart->Instance == UART8) { } } 8004bc8: bf00 nop 8004bca: 370c adds r7, #12 8004bcc: 46bd mov sp, r7 8004bce: f85d 7b04 ldr.w r7, [sp], #4 8004bd2: 4770 bx lr 08004bd4 : void HandleUartRxCallback (UartTaskData* uartTaskData, UART_HandleTypeDef* huart, uint16_t Size) { 8004bd4: b580 push {r7, lr} 8004bd6: b088 sub sp, #32 8004bd8: af02 add r7, sp, #8 8004bda: 60f8 str r0, [r7, #12] 8004bdc: 60b9 str r1, [r7, #8] 8004bde: 4613 mov r3, r2 8004be0: 80fb strh r3, [r7, #6] BaseType_t pxHigherPriorityTaskWoken = pdFALSE; 8004be2: 2300 movs r3, #0 8004be4: 617b str r3, [r7, #20] osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004be6: 68fb ldr r3, [r7, #12] 8004be8: 6a1b ldr r3, [r3, #32] 8004bea: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004bee: 4618 mov r0, r3 8004bf0: f00f fca5 bl 801453e memcpy (&(uartTaskData->frameData[uartTaskData->frameBytesCount]), uartTaskData->uartRxBuffer, Size); 8004bf4: 68fb ldr r3, [r7, #12] 8004bf6: 691b ldr r3, [r3, #16] 8004bf8: 68fa ldr r2, [r7, #12] 8004bfa: 8ad2 ldrh r2, [r2, #22] 8004bfc: 1898 adds r0, r3, r2 8004bfe: 68fb ldr r3, [r7, #12] 8004c00: 681b ldr r3, [r3, #0] 8004c02: 88fa ldrh r2, [r7, #6] 8004c04: 4619 mov r1, r3 8004c06: f013 fc51 bl 80184ac uartTaskData->frameBytesCount += Size; 8004c0a: 68fb ldr r3, [r7, #12] 8004c0c: 8ada ldrh r2, [r3, #22] 8004c0e: 88fb ldrh r3, [r7, #6] 8004c10: 4413 add r3, r2 8004c12: b29a uxth r2, r3 8004c14: 68fb ldr r3, [r7, #12] 8004c16: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 8004c18: 68fb ldr r3, [r7, #12] 8004c1a: 6a1b ldr r3, [r3, #32] 8004c1c: 4618 mov r0, r3 8004c1e: f00f fcd9 bl 80145d4 xTaskNotifyFromISR (uartTaskData->uartRecieveTaskHandle, Size, eSetValueWithOverwrite, &pxHigherPriorityTaskWoken); 8004c22: 68fb ldr r3, [r7, #12] 8004c24: 6998 ldr r0, [r3, #24] 8004c26: 88f9 ldrh r1, [r7, #6] 8004c28: f107 0314 add.w r3, r7, #20 8004c2c: 9300 str r3, [sp, #0] 8004c2e: 2300 movs r3, #0 8004c30: 2203 movs r2, #3 8004c32: f012 f9c9 bl 8016fc8 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8004c36: 68fb ldr r3, [r7, #12] 8004c38: 6b18 ldr r0, [r3, #48] @ 0x30 8004c3a: 68fb ldr r3, [r7, #12] 8004c3c: 6819 ldr r1, [r3, #0] 8004c3e: 68fb ldr r3, [r7, #12] 8004c40: 889b ldrh r3, [r3, #4] 8004c42: 461a mov r2, r3 8004c44: f00f f923 bl 8013e8e portEND_SWITCHING_ISR (pxHigherPriorityTaskWoken); 8004c48: 697b ldr r3, [r7, #20] 8004c4a: 2b00 cmp r3, #0 8004c4c: d007 beq.n 8004c5e 8004c4e: 4b06 ldr r3, [pc, #24] @ (8004c68 ) 8004c50: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8004c54: 601a str r2, [r3, #0] 8004c56: f3bf 8f4f dsb sy 8004c5a: f3bf 8f6f isb sy } 8004c5e: bf00 nop 8004c60: 3718 adds r7, #24 8004c62: 46bd mov sp, r7 8004c64: bd80 pop {r7, pc} 8004c66: bf00 nop 8004c68: e000ed04 .word 0xe000ed04 08004c6c : void UartRxTask (void* argument) { 8004c6c: b580 push {r7, lr} 8004c6e: b0d2 sub sp, #328 @ 0x148 8004c70: af02 add r7, sp, #8 8004c72: f507 73a0 add.w r3, r7, #320 @ 0x140 8004c76: f5a3 739e sub.w r3, r3, #316 @ 0x13c 8004c7a: 6018 str r0, [r3, #0] UartTaskData* uartTaskData = (UartTaskData*)argument; 8004c7c: f507 73a0 add.w r3, r7, #320 @ 0x140 8004c80: f5a3 739e sub.w r3, r3, #316 @ 0x13c 8004c84: 681b ldr r3, [r3, #0] 8004c86: f8c7 312c str.w r3, [r7, #300] @ 0x12c SerialProtocolFrameData spFrameData = { 0 }; 8004c8a: f507 73a0 add.w r3, r7, #320 @ 0x140 8004c8e: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004c92: 4618 mov r0, r3 8004c94: f44f 7386 mov.w r3, #268 @ 0x10c 8004c98: 461a mov r2, r3 8004c9a: 2100 movs r1, #0 8004c9c: f013 fb7c bl 8018398 uint32_t bytesRec = 0; 8004ca0: f507 73a0 add.w r3, r7, #320 @ 0x140 8004ca4: f5a3 739a sub.w r3, r3, #308 @ 0x134 8004ca8: 2200 movs r2, #0 8004caa: 601a str r2, [r3, #0] uint32_t crc = 0; 8004cac: 2300 movs r3, #0 8004cae: f8c7 3128 str.w r3, [r7, #296] @ 0x128 uint16_t frameCommandRaw = 0x0000; 8004cb2: 2300 movs r3, #0 8004cb4: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 uint16_t frameBytesCount = 0; 8004cb8: 2300 movs r3, #0 8004cba: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 uint16_t frameCrc = 0; 8004cbe: 2300 movs r3, #0 8004cc0: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 uint16_t frameTotalLength = 0; 8004cc4: 2300 movs r3, #0 8004cc6: f8a7 313e strh.w r3, [r7, #318] @ 0x13e uint16_t dataToSend = 0; 8004cca: 2300 movs r3, #0 8004ccc: f8a7 313c strh.w r3, [r7, #316] @ 0x13c portBASE_TYPE crcPass = pdFAIL; 8004cd0: 2300 movs r3, #0 8004cd2: f8c7 3138 str.w r3, [r7, #312] @ 0x138 portBASE_TYPE proceed = pdFALSE; 8004cd6: 2300 movs r3, #0 8004cd8: f8c7 3134 str.w r3, [r7, #308] @ 0x134 portBASE_TYPE frameTimeout = pdFAIL; 8004cdc: 2300 movs r3, #0 8004cde: f8c7 311c str.w r3, [r7, #284] @ 0x11c enum SerialReceiverStates receverState = srWaitForHeader; 8004ce2: 2300 movs r3, #0 8004ce4: f887 3133 strb.w r3, [r7, #307] @ 0x133 uartTaskData->rxDataBufferMutex = osMutexNew (NULL); 8004ce8: 2000 movs r0, #0 8004cea: f00f fba2 bl 8014432 8004cee: 4602 mov r2, r0 8004cf0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004cf4: 621a str r2, [r3, #32] HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8004cf6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004cfa: 6b18 ldr r0, [r3, #48] @ 0x30 8004cfc: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d00: 6819 ldr r1, [r3, #0] 8004d02: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d06: 889b ldrh r3, [r3, #4] 8004d08: 461a mov r2, r3 8004d0a: f00f f8c0 bl 8013e8e while (pdTRUE) { frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8004d0e: f107 020c add.w r2, r7, #12 8004d12: f44f 63fa mov.w r3, #2000 @ 0x7d0 8004d16: 2100 movs r1, #0 8004d18: 2000 movs r0, #0 8004d1a: f012 f833 bl 8016d84 8004d1e: 4603 mov r3, r0 8004d20: 2b00 cmp r3, #0 8004d22: bf0c ite eq 8004d24: 2301 moveq r3, #1 8004d26: 2300 movne r3, #0 8004d28: b2db uxtb r3, r3 8004d2a: f8c7 311c str.w r3, [r7, #284] @ 0x11c osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004d2e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d32: 6a1b ldr r3, [r3, #32] 8004d34: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004d38: 4618 mov r0, r3 8004d3a: f00f fc00 bl 801453e frameBytesCount = uartTaskData->frameBytesCount; 8004d3e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d42: 8adb ldrh r3, [r3, #22] 8004d44: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 osMutexRelease (uartTaskData->rxDataBufferMutex); 8004d48: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d4c: 6a1b ldr r3, [r3, #32] 8004d4e: 4618 mov r0, r3 8004d50: f00f fc40 bl 80145d4 if ((frameTimeout == pdTRUE) && (frameBytesCount > 0)) { 8004d54: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8004d58: 2b01 cmp r3, #1 8004d5a: d10a bne.n 8004d72 8004d5c: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004d60: 2b00 cmp r3, #0 8004d62: d006 beq.n 8004d72 receverState = srFail; 8004d64: 2304 movs r3, #4 8004d66: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdTRUE; 8004d6a: 2301 movs r3, #1 8004d6c: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004d70: e01b b.n 8004daa } else { if (frameTimeout == pdFALSE) { 8004d72: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8004d76: 2b00 cmp r3, #0 8004d78: d103 bne.n 8004d82 proceed = pdTRUE; 8004d7a: 2301 movs r3, #1 8004d7c: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004d80: e206 b.n 8005190 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: RX bytes received: %ld\n", uartTaskData->uartNumber, bytesRec); #endif } else { if (uartTaskData->huart->RxState == HAL_UART_STATE_READY) { 8004d82: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d86: 6b1b ldr r3, [r3, #48] @ 0x30 8004d88: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004d8c: 2b20 cmp r3, #32 8004d8e: f040 81ff bne.w 8005190 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8004d92: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d96: 6b18 ldr r0, [r3, #48] @ 0x30 8004d98: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d9c: 6819 ldr r1, [r3, #0] 8004d9e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004da2: 889b ldrh r3, [r3, #4] 8004da4: 461a mov r2, r3 8004da6: f00f f872 bl 8013e8e } } } while (proceed) { 8004daa: e1f1 b.n 8005190 switch (receverState) { 8004dac: f897 3133 ldrb.w r3, [r7, #307] @ 0x133 8004db0: 2b04 cmp r3, #4 8004db2: f200 81c8 bhi.w 8005146 8004db6: a201 add r2, pc, #4 @ (adr r2, 8004dbc ) 8004db8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004dbc: 08004dd1 .word 0x08004dd1 8004dc0: 08004f33 .word 0x08004f33 8004dc4: 08004f17 .word 0x08004f17 8004dc8: 08004fc3 .word 0x08004fc3 8004dcc: 0800506f .word 0x0800506f case srWaitForHeader: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004dd0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004dd4: 6a1b ldr r3, [r3, #32] 8004dd6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004dda: 4618 mov r0, r3 8004ddc: f00f fbaf bl 801453e if (uartTaskData->frameData[0] == FRAME_INDICATOR) { 8004de0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004de4: 691b ldr r3, [r3, #16] 8004de6: 781b ldrb r3, [r3, #0] 8004de8: 2baa cmp r3, #170 @ 0xaa 8004dea: f040 8082 bne.w 8004ef2 if (frameBytesCount > FRAME_ID_LENGTH) { 8004dee: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004df2: 2b02 cmp r3, #2 8004df4: d914 bls.n 8004e20 spFrameData.frameHeader.frameId = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_ID_LENGTH - FRAME_COMMAND_LENGTH])); 8004df6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004dfa: 691b ldr r3, [r3, #16] 8004dfc: 3302 adds r3, #2 8004dfe: 781b ldrb r3, [r3, #0] 8004e00: 021b lsls r3, r3, #8 8004e02: b21a sxth r2, r3 8004e04: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e08: 691b ldr r3, [r3, #16] 8004e0a: 3301 adds r3, #1 8004e0c: 781b ldrb r3, [r3, #0] 8004e0e: b21b sxth r3, r3 8004e10: 4313 orrs r3, r2 8004e12: b21b sxth r3, r3 8004e14: b29a uxth r2, r3 spFrameData.frameHeader.frameId = 8004e16: f507 73a0 add.w r3, r7, #320 @ 0x140 8004e1a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004e1e: 801a strh r2, [r3, #0] } if (frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH) { 8004e20: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004e24: 2b04 cmp r3, #4 8004e26: d923 bls.n 8004e70 frameCommandRaw = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_COMMAND_LENGTH])); 8004e28: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e2c: 691b ldr r3, [r3, #16] 8004e2e: 3304 adds r3, #4 8004e30: 781b ldrb r3, [r3, #0] 8004e32: 021b lsls r3, r3, #8 8004e34: b21a sxth r2, r3 8004e36: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e3a: 691b ldr r3, [r3, #16] 8004e3c: 3303 adds r3, #3 8004e3e: 781b ldrb r3, [r3, #0] 8004e40: b21b sxth r3, r3 8004e42: 4313 orrs r3, r2 8004e44: b21b sxth r3, r3 8004e46: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 spFrameData.frameHeader.frameCommand = (SerialProtocolCommands)(frameCommandRaw & 0x7FFF); 8004e4a: f8b7 3126 ldrh.w r3, [r7, #294] @ 0x126 8004e4e: b2da uxtb r2, r3 8004e50: f507 73a0 add.w r3, r7, #320 @ 0x140 8004e54: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004e58: 709a strb r2, [r3, #2] spFrameData.frameHeader.isResponseFrame = (frameCommandRaw & 0x8000) != 0 ? pdTRUE : pdFALSE; 8004e5a: f9b7 3126 ldrsh.w r3, [r7, #294] @ 0x126 8004e5e: 13db asrs r3, r3, #15 8004e60: b21b sxth r3, r3 8004e62: f003 0201 and.w r2, r3, #1 8004e66: f507 73a0 add.w r3, r7, #320 @ 0x140 8004e6a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004e6e: 609a str r2, [r3, #8] } if ((frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH) && ((spFrameData.frameHeader.frameCommand & 0x8000) != 0)) { 8004e70: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004e74: 2b05 cmp r3, #5 8004e76: d913 bls.n 8004ea0 8004e78: f507 73a0 add.w r3, r7, #320 @ 0x140 8004e7c: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004e80: 789b ldrb r3, [r3, #2] 8004e82: f403 4300 and.w r3, r3, #32768 @ 0x8000 8004e86: 2b00 cmp r3, #0 8004e88: d00a beq.n 8004ea0 spFrameData.frameHeader.respStatus = (SerialProtocolRespStatus)(uartTaskData->frameData[FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH]); 8004e8a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e8e: 691b ldr r3, [r3, #16] 8004e90: 3305 adds r3, #5 8004e92: 781b ldrb r3, [r3, #0] 8004e94: b25a sxtb r2, r3 8004e96: f507 73a0 add.w r3, r7, #320 @ 0x140 8004e9a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004e9e: 70da strb r2, [r3, #3] } if (frameBytesCount >= FRAME_HEADER_LENGTH) { 8004ea0: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004ea4: 2b07 cmp r3, #7 8004ea6: d920 bls.n 8004eea spFrameData.frameHeader.frameDataLength = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH])); 8004ea8: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004eac: 691b ldr r3, [r3, #16] 8004eae: 3306 adds r3, #6 8004eb0: 781b ldrb r3, [r3, #0] 8004eb2: 021b lsls r3, r3, #8 8004eb4: b21a sxth r2, r3 8004eb6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004eba: 691b ldr r3, [r3, #16] 8004ebc: 3305 adds r3, #5 8004ebe: 781b ldrb r3, [r3, #0] 8004ec0: b21b sxth r3, r3 8004ec2: 4313 orrs r3, r2 8004ec4: b21b sxth r3, r3 8004ec6: b29a uxth r2, r3 8004ec8: f507 73a0 add.w r3, r7, #320 @ 0x140 8004ecc: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004ed0: 809a strh r2, [r3, #4] frameTotalLength = FRAME_HEADER_LENGTH + spFrameData.frameHeader.frameDataLength + FRAME_CRC_LENGTH; 8004ed2: f507 73a0 add.w r3, r7, #320 @ 0x140 8004ed6: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004eda: 889b ldrh r3, [r3, #4] 8004edc: 330a adds r3, #10 8004ede: f8a7 313e strh.w r3, [r7, #318] @ 0x13e receverState = srRecieveData; 8004ee2: 2302 movs r3, #2 8004ee4: f887 3133 strb.w r3, [r7, #307] @ 0x133 8004ee8: e00e b.n 8004f08 } else { proceed = pdFALSE; 8004eea: 2300 movs r3, #0 8004eec: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004ef0: e00a b.n 8004f08 } } else { if (frameBytesCount > 0) { 8004ef2: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004ef6: 2b00 cmp r3, #0 8004ef8: d003 beq.n 8004f02 receverState = srFail; 8004efa: 2304 movs r3, #4 8004efc: f887 3133 strb.w r3, [r7, #307] @ 0x133 8004f00: e002 b.n 8004f08 } else { proceed = pdFALSE; 8004f02: 2300 movs r3, #0 8004f04: f8c7 3134 str.w r3, [r7, #308] @ 0x134 } } osMutexRelease (uartTaskData->rxDataBufferMutex); 8004f08: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f0c: 6a1b ldr r3, [r3, #32] 8004f0e: 4618 mov r0, r3 8004f10: f00f fb60 bl 80145d4 break; 8004f14: e13c b.n 8005190 case srRecieveData: if (frameBytesCount >= frameTotalLength) { 8004f16: f8b7 2124 ldrh.w r2, [r7, #292] @ 0x124 8004f1a: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004f1e: 429a cmp r2, r3 8004f20: d303 bcc.n 8004f2a receverState = srCheckCrc; 8004f22: 2301 movs r3, #1 8004f24: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { proceed = pdFALSE; } break; 8004f28: e132 b.n 8005190 proceed = pdFALSE; 8004f2a: 2300 movs r3, #0 8004f2c: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 8004f30: e12e b.n 8005190 case srCheckCrc: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004f32: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f36: 6a1b ldr r3, [r3, #32] 8004f38: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004f3c: 4618 mov r0, r3 8004f3e: f00f fafe bl 801453e frameCrc = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[frameTotalLength - FRAME_CRC_LENGTH])); 8004f42: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f46: 691a ldr r2, [r3, #16] 8004f48: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004f4c: 3b01 subs r3, #1 8004f4e: 4413 add r3, r2 8004f50: 781b ldrb r3, [r3, #0] 8004f52: 021b lsls r3, r3, #8 8004f54: b21a sxth r2, r3 8004f56: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f5a: 6919 ldr r1, [r3, #16] 8004f5c: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004f60: 3b02 subs r3, #2 8004f62: 440b add r3, r1 8004f64: 781b ldrb r3, [r3, #0] 8004f66: b21b sxth r3, r3 8004f68: 4313 orrs r3, r2 8004f6a: b21b sxth r3, r3 8004f6c: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)(uartTaskData->frameData), frameTotalLength - FRAME_CRC_LENGTH); 8004f70: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f74: 6919 ldr r1, [r3, #16] 8004f76: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004f7a: 3b02 subs r3, #2 8004f7c: 461a mov r2, r3 8004f7e: 4887 ldr r0, [pc, #540] @ (800519c ) 8004f80: f002 ff3a bl 8007df8 8004f84: f8c7 0128 str.w r0, [r7, #296] @ 0x128 osMutexRelease (uartTaskData->rxDataBufferMutex); 8004f88: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f8c: 6a1b ldr r3, [r3, #32] 8004f8e: 4618 mov r0, r3 8004f90: f00f fb20 bl 80145d4 crcPass = frameCrc == crc; 8004f94: f8b7 3122 ldrh.w r3, [r7, #290] @ 0x122 8004f98: f8d7 2128 ldr.w r2, [r7, #296] @ 0x128 8004f9c: 429a cmp r2, r3 8004f9e: bf0c ite eq 8004fa0: 2301 moveq r3, #1 8004fa2: 2300 movne r3, #0 8004fa4: b2db uxtb r3, r3 8004fa6: f8c7 3138 str.w r3, [r7, #312] @ 0x138 if (crcPass) { 8004faa: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 8004fae: 2b00 cmp r3, #0 8004fb0: d003 beq.n 8004fba #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: Frame CRC PASS\n", uartTaskData->uartNumber); #endif receverState = srExecuteCmd; 8004fb2: 2303 movs r3, #3 8004fb4: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { receverState = srFail; } break; 8004fb8: e0ea b.n 8005190 receverState = srFail; 8004fba: 2304 movs r3, #4 8004fbc: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004fc0: e0e6 b.n 8005190 case srExecuteCmd: if ((uartTaskData->processDataCb != NULL) || (uartTaskData->processRxDataMsgBuffer != NULL)) { 8004fc2: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004fc6: 6a9b ldr r3, [r3, #40] @ 0x28 8004fc8: 2b00 cmp r3, #0 8004fca: d104 bne.n 8004fd6 8004fcc: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004fd0: 6a5b ldr r3, [r3, #36] @ 0x24 8004fd2: 2b00 cmp r3, #0 8004fd4: d01e beq.n 8005014 osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004fd6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004fda: 6a1b ldr r3, [r3, #32] 8004fdc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004fe0: 4618 mov r0, r3 8004fe2: f00f faac bl 801453e memcpy (spFrameData.dataBuffer, &(uartTaskData->frameData[FRAME_HEADER_LENGTH]), spFrameData.frameHeader.frameDataLength); 8004fe6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004fea: 691b ldr r3, [r3, #16] 8004fec: f103 0108 add.w r1, r3, #8 8004ff0: f507 73a0 add.w r3, r7, #320 @ 0x140 8004ff4: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004ff8: 889b ldrh r3, [r3, #4] 8004ffa: 461a mov r2, r3 8004ffc: f107 0310 add.w r3, r7, #16 8005000: 330c adds r3, #12 8005002: 4618 mov r0, r3 8005004: f013 fa52 bl 80184ac osMutexRelease (uartTaskData->rxDataBufferMutex); 8005008: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800500c: 6a1b ldr r3, [r3, #32] 800500e: 4618 mov r0, r3 8005010: f00f fae0 bl 80145d4 } if (uartTaskData->processRxDataMsgBuffer != NULL) { 8005014: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8005018: 6a5b ldr r3, [r3, #36] @ 0x24 800501a: 2b00 cmp r3, #0 800501c: d015 beq.n 800504a if (xMessageBufferSend (uartTaskData->processRxDataMsgBuffer, &spFrameData, sizeof (SerialProtocolFrameHeader) + spFrameData.frameHeader.frameDataLength, pdMS_TO_TICKS (200)) == pdFALSE) { 800501e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8005022: 6a58 ldr r0, [r3, #36] @ 0x24 8005024: f507 73a0 add.w r3, r7, #320 @ 0x140 8005028: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800502c: 889b ldrh r3, [r3, #4] 800502e: f103 020c add.w r2, r3, #12 8005032: f107 0110 add.w r1, r7, #16 8005036: 23c8 movs r3, #200 @ 0xc8 8005038: f010 fcee bl 8015a18 800503c: 4603 mov r3, r0 800503e: 2b00 cmp r3, #0 8005040: d103 bne.n 800504a receverState = srFail; 8005042: 2304 movs r3, #4 8005044: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8005048: e0a2 b.n 8005190 } } if (uartTaskData->processDataCb != NULL) { 800504a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800504e: 6a9b ldr r3, [r3, #40] @ 0x28 8005050: 2b00 cmp r3, #0 8005052: d008 beq.n 8005066 uartTaskData->processDataCb (uartTaskData, &spFrameData); 8005054: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8005058: 6a9b ldr r3, [r3, #40] @ 0x28 800505a: f107 0210 add.w r2, r7, #16 800505e: 4611 mov r1, r2 8005060: f8d7 012c ldr.w r0, [r7, #300] @ 0x12c 8005064: 4798 blx r3 } receverState = srFinish; 8005066: 2305 movs r3, #5 8005068: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 800506c: e090 b.n 8005190 case srFail: dataToSend = 0; 800506e: 2300 movs r3, #0 8005070: f8a7 313c strh.w r3, [r7, #316] @ 0x13c if ((frameTimeout == pdTRUE) && (frameBytesCount > 2)) { 8005074: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8005078: 2b01 cmp r3, #1 800507a: d11c bne.n 80050b6 800507c: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8005080: 2b02 cmp r3, #2 8005082: d918 bls.n 80050b6 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0); 8005084: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8005088: 6898 ldr r0, [r3, #8] 800508a: f507 73a0 add.w r3, r7, #320 @ 0x140 800508e: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8005092: 8819 ldrh r1, [r3, #0] 8005094: f507 73a0 add.w r3, r7, #320 @ 0x140 8005098: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800509c: 789a ldrb r2, [r3, #2] 800509e: 2300 movs r3, #0 80050a0: 9301 str r3, [sp, #4] 80050a2: 2300 movs r3, #0 80050a4: 9300 str r3, [sp, #0] 80050a6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80050aa: f7fe fd57 bl 8003b5c 80050ae: 4603 mov r3, r0 80050b0: f8a7 313c strh.w r3, [r7, #316] @ 0x13c 80050b4: e034 b.n 8005120 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: RX data receiver timeout!\n", uartTaskData->uartNumber); #endif } else if (!crcPass) { 80050b6: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 80050ba: 2b00 cmp r3, #0 80050bc: d118 bne.n 80050f0 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spCrcFail, NULL, 0); 80050be: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80050c2: 6898 ldr r0, [r3, #8] 80050c4: f507 73a0 add.w r3, r7, #320 @ 0x140 80050c8: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80050cc: 8819 ldrh r1, [r3, #0] 80050ce: f507 73a0 add.w r3, r7, #320 @ 0x140 80050d2: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80050d6: 789a ldrb r2, [r3, #2] 80050d8: 2300 movs r3, #0 80050da: 9301 str r3, [sp, #4] 80050dc: 2300 movs r3, #0 80050de: 9300 str r3, [sp, #0] 80050e0: f06f 0301 mvn.w r3, #1 80050e4: f7fe fd3a bl 8003b5c 80050e8: 4603 mov r3, r0 80050ea: f8a7 313c strh.w r3, [r7, #316] @ 0x13c 80050ee: e017 b.n 8005120 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: Frame CRC FAIL\n", uartTaskData->uartNumber); #endif } else { dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spInternalError, NULL, 0); 80050f0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80050f4: 6898 ldr r0, [r3, #8] 80050f6: f507 73a0 add.w r3, r7, #320 @ 0x140 80050fa: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80050fe: 8819 ldrh r1, [r3, #0] 8005100: f507 73a0 add.w r3, r7, #320 @ 0x140 8005104: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8005108: 789a ldrb r2, [r3, #2] 800510a: 2300 movs r3, #0 800510c: 9301 str r3, [sp, #4] 800510e: 2300 movs r3, #0 8005110: 9300 str r3, [sp, #0] 8005112: f06f 0303 mvn.w r3, #3 8005116: f7fe fd21 bl 8003b5c 800511a: 4603 mov r3, r0 800511c: f8a7 313c strh.w r3, [r7, #316] @ 0x13c } if (dataToSend > 0) { 8005120: f8b7 313c ldrh.w r3, [r7, #316] @ 0x13c 8005124: 2b00 cmp r3, #0 8005126: d00a beq.n 800513e HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 8005128: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800512c: 6b18 ldr r0, [r3, #48] @ 0x30 800512e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8005132: 689b ldr r3, [r3, #8] 8005134: f8b7 213c ldrh.w r2, [r7, #316] @ 0x13c 8005138: 4619 mov r1, r3 800513a: f00c f9d3 bl 80114e4 } #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: TX bytes sent: %d\n", dataToSend, uartTaskData->uartNumber); #endif receverState = srFinish; 800513e: 2305 movs r3, #5 8005140: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8005144: e024 b.n 8005190 case srFinish: default: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8005146: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800514a: 6a1b ldr r3, [r3, #32] 800514c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005150: 4618 mov r0, r3 8005152: f00f f9f4 bl 801453e uartTaskData->frameBytesCount = 0; 8005156: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800515a: 2200 movs r2, #0 800515c: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 800515e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8005162: 6a1b ldr r3, [r3, #32] 8005164: 4618 mov r0, r3 8005166: f00f fa35 bl 80145d4 spFrameData.frameHeader.frameCommand = spUnknown; 800516a: f507 73a0 add.w r3, r7, #320 @ 0x140 800516e: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8005172: 2212 movs r2, #18 8005174: 709a strb r2, [r3, #2] frameTotalLength = 0; 8005176: 2300 movs r3, #0 8005178: f8a7 313e strh.w r3, [r7, #318] @ 0x13e outputDataBufferPos = 0; 800517c: 4b08 ldr r3, [pc, #32] @ (80051a0 ) 800517e: 2200 movs r2, #0 8005180: 801a strh r2, [r3, #0] receverState = srWaitForHeader; 8005182: 2300 movs r3, #0 8005184: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdFALSE; 8005188: 2300 movs r3, #0 800518a: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 800518e: bf00 nop while (proceed) { 8005190: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 8005194: 2b00 cmp r3, #0 8005196: f47f ae09 bne.w 8004dac frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 800519a: e5b8 b.n 8004d0e 800519c: 240003e0 .word 0x240003e0 80051a0: 2400105c .word 0x2400105c 080051a4 : } } } } void Uart8ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 80051a4: b580 push {r7, lr} 80051a6: b082 sub sp, #8 80051a8: af00 add r7, sp, #0 80051aa: 6078 str r0, [r7, #4] 80051ac: 6039 str r1, [r7, #0] Uart1ReceivedDataProcessCallback (arg, spFrameData); 80051ae: 6839 ldr r1, [r7, #0] 80051b0: 6878 ldr r0, [r7, #4] 80051b2: f000 f805 bl 80051c0 } 80051b6: bf00 nop 80051b8: 3708 adds r7, #8 80051ba: 46bd mov sp, r7 80051bc: bd80 pop {r7, pc} ... 080051c0 : void Uart1ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 80051c0: b590 push {r4, r7, lr} 80051c2: b0ad sub sp, #180 @ 0xb4 80051c4: af06 add r7, sp, #24 80051c6: 6078 str r0, [r7, #4] 80051c8: 6039 str r1, [r7, #0] UartTaskData* uartTaskData = (UartTaskData*)arg; 80051ca: 687b ldr r3, [r7, #4] 80051cc: 677b str r3, [r7, #116] @ 0x74 uint16_t dataToSend = 0; 80051ce: 2300 movs r3, #0 80051d0: f8a7 3072 strh.w r3, [r7, #114] @ 0x72 outputDataBufferPos = 0; 80051d4: 4b64 ldr r3, [pc, #400] @ (8005368 ) 80051d6: 2200 movs r2, #0 80051d8: 801a strh r2, [r3, #0] uint16_t inputDataBufferPos = 0; 80051da: 2300 movs r3, #0 80051dc: f8a7 3044 strh.w r3, [r7, #68] @ 0x44 SerialProtocolRespStatus respStatus = spUnknownCommand; 80051e0: 23fd movs r3, #253 @ 0xfd 80051e2: f887 3097 strb.w r3, [r7, #151] @ 0x97 switch (spFrameData->frameHeader.frameCommand) { 80051e6: 683b ldr r3, [r7, #0] 80051e8: 789b ldrb r3, [r3, #2] 80051ea: 2b11 cmp r3, #17 80051ec: f200 85a2 bhi.w 8005d34 80051f0: a201 add r2, pc, #4 @ (adr r2, 80051f8 ) 80051f2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80051f6: bf00 nop 80051f8: 08005241 .word 0x08005241 80051fc: 08005379 .word 0x08005379 8005200: 080054f3 .word 0x080054f3 8005204: 08005629 .word 0x08005629 8005208: 080056cb .word 0x080056cb 800520c: 080057e9 .word 0x080057e9 8005210: 0800583f .word 0x0800583f 8005214: 0800576d .word 0x0800576d 8005218: 08005895 .word 0x08005895 800521c: 08005935 .word 0x08005935 8005220: 08005981 .word 0x08005981 8005224: 080059cd .word 0x080059cd 8005228: 08005a2f .word 0x08005a2f 800522c: 08005a93 .word 0x08005a93 8005230: 08005af5 .word 0x08005af5 8005234: 08005b59 .word 0x08005b59 8005238: 08005b61 .word 0x08005b61 800523c: 08005c65 .word 0x08005c65 case spGetElectricalMeasurments: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005240: 4b4a ldr r3, [pc, #296] @ (800536c ) 8005242: 681b ldr r3, [r3, #0] 8005244: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005248: 4618 mov r0, r3 800524a: f00f f978 bl 801453e 800524e: 4603 mov r3, r0 8005250: 2b00 cmp r3, #0 8005252: f040 8083 bne.w 800535c for (int i = 0; i < 3; i++) { 8005256: 2300 movs r3, #0 8005258: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800525c: e00e b.n 800527c WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltageRMS[i], sizeof (float)); 800525e: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8005262: 009b lsls r3, r3, #2 8005264: 4a42 ldr r2, [pc, #264] @ (8005370 ) 8005266: 441a add r2, r3 8005268: 2304 movs r3, #4 800526a: 493f ldr r1, [pc, #252] @ (8005368 ) 800526c: 4841 ldr r0, [pc, #260] @ (8005374 ) 800526e: f7fe fbdb bl 8003a28 for (int i = 0; i < 3; i++) { 8005272: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8005276: 3301 adds r3, #1 8005278: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800527c: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8005280: 2b02 cmp r3, #2 8005282: ddec ble.n 800525e } for (int i = 0; i < 3; i++) { 8005284: 2300 movs r3, #0 8005286: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800528a: e010 b.n 80052ae WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltagePeak[i], sizeof (float)); 800528c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8005290: 3302 adds r3, #2 8005292: 009b lsls r3, r3, #2 8005294: 4a36 ldr r2, [pc, #216] @ (8005370 ) 8005296: 4413 add r3, r2 8005298: 1d1a adds r2, r3, #4 800529a: 2304 movs r3, #4 800529c: 4932 ldr r1, [pc, #200] @ (8005368 ) 800529e: 4835 ldr r0, [pc, #212] @ (8005374 ) 80052a0: f7fe fbc2 bl 8003a28 for (int i = 0; i < 3; i++) { 80052a4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 80052a8: 3301 adds r3, #1 80052aa: f8c7 308c str.w r3, [r7, #140] @ 0x8c 80052ae: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 80052b2: 2b02 cmp r3, #2 80052b4: ddea ble.n 800528c } for (int i = 0; i < 3; i++) { 80052b6: 2300 movs r3, #0 80052b8: f8c7 3088 str.w r3, [r7, #136] @ 0x88 80052bc: e00f b.n 80052de WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentRMS[i], sizeof (float)); 80052be: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 80052c2: 3306 adds r3, #6 80052c4: 009b lsls r3, r3, #2 80052c6: 4a2a ldr r2, [pc, #168] @ (8005370 ) 80052c8: 441a add r2, r3 80052ca: 2304 movs r3, #4 80052cc: 4926 ldr r1, [pc, #152] @ (8005368 ) 80052ce: 4829 ldr r0, [pc, #164] @ (8005374 ) 80052d0: f7fe fbaa bl 8003a28 for (int i = 0; i < 3; i++) { 80052d4: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 80052d8: 3301 adds r3, #1 80052da: f8c7 3088 str.w r3, [r7, #136] @ 0x88 80052de: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 80052e2: 2b02 cmp r3, #2 80052e4: ddeb ble.n 80052be } for (int i = 0; i < 3; i++) { 80052e6: 2300 movs r3, #0 80052e8: f8c7 3084 str.w r3, [r7, #132] @ 0x84 80052ec: e010 b.n 8005310 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentPeak[i], sizeof (float)); 80052ee: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 80052f2: 3308 adds r3, #8 80052f4: 009b lsls r3, r3, #2 80052f6: 4a1e ldr r2, [pc, #120] @ (8005370 ) 80052f8: 4413 add r3, r2 80052fa: 1d1a adds r2, r3, #4 80052fc: 2304 movs r3, #4 80052fe: 491a ldr r1, [pc, #104] @ (8005368 ) 8005300: 481c ldr r0, [pc, #112] @ (8005374 ) 8005302: f7fe fb91 bl 8003a28 for (int i = 0; i < 3; i++) { 8005306: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 800530a: 3301 adds r3, #1 800530c: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8005310: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8005314: 2b02 cmp r3, #2 8005316: ddea ble.n 80052ee } for (int i = 0; i < 3; i++) { 8005318: 2300 movs r3, #0 800531a: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800531e: e00f b.n 8005340 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.power[i], sizeof (float)); 8005320: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8005324: 330c adds r3, #12 8005326: 009b lsls r3, r3, #2 8005328: 4a11 ldr r2, [pc, #68] @ (8005370 ) 800532a: 441a add r2, r3 800532c: 2304 movs r3, #4 800532e: 490e ldr r1, [pc, #56] @ (8005368 ) 8005330: 4810 ldr r0, [pc, #64] @ (8005374 ) 8005332: f7fe fb79 bl 8003a28 for (int i = 0; i < 3; i++) { 8005336: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 800533a: 3301 adds r3, #1 800533c: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8005340: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8005344: 2b02 cmp r3, #2 8005346: ddeb ble.n 8005320 } osMutexRelease (resMeasurementsMutex); 8005348: 4b08 ldr r3, [pc, #32] @ (800536c ) 800534a: 681b ldr r3, [r3, #0] 800534c: 4618 mov r0, r3 800534e: f00f f941 bl 80145d4 respStatus = spOK; 8005352: 2300 movs r3, #0 8005354: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005358: f000 bcf3 b.w 8005d42 respStatus = spInternalError; 800535c: 23fc movs r3, #252 @ 0xfc 800535e: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005362: f000 bcee b.w 8005d42 8005366: bf00 nop 8005368: 2400105c .word 0x2400105c 800536c: 24000818 .word 0x24000818 8005370: 24000824 .word 0x24000824 8005374: 24000fdc .word 0x24000fdc case spGetSensorMeasurments: if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8005378: 4b8d ldr r3, [pc, #564] @ (80055b0 ) 800537a: 681b ldr r3, [r3, #0] 800537c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005380: 4618 mov r0, r3 8005382: f00f f8dc bl 801453e 8005386: 4603 mov r3, r0 8005388: 2b00 cmp r3, #0 800538a: f040 80ad bne.w 80054e8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[0], sizeof (float)); 800538e: 2304 movs r3, #4 8005390: 4a88 ldr r2, [pc, #544] @ (80055b4 ) 8005392: 4989 ldr r1, [pc, #548] @ (80055b8 ) 8005394: 4889 ldr r0, [pc, #548] @ (80055bc ) 8005396: f7fe fb47 bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[1], sizeof (float)); 800539a: 2304 movs r3, #4 800539c: 4a88 ldr r2, [pc, #544] @ (80055c0 ) 800539e: 4986 ldr r1, [pc, #536] @ (80055b8 ) 80053a0: 4886 ldr r0, [pc, #536] @ (80055bc ) 80053a2: f7fe fb41 bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.fanVoltage, sizeof (float)); 80053a6: 2304 movs r3, #4 80053a8: 4a86 ldr r2, [pc, #536] @ (80055c4 ) 80053aa: 4983 ldr r1, [pc, #524] @ (80055b8 ) 80053ac: 4883 ldr r0, [pc, #524] @ (80055bc ) 80053ae: f7fe fb3b bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderX, sizeof (float)); 80053b2: 2304 movs r3, #4 80053b4: 4a84 ldr r2, [pc, #528] @ (80055c8 ) 80053b6: 4980 ldr r1, [pc, #512] @ (80055b8 ) 80053b8: 4880 ldr r0, [pc, #512] @ (80055bc ) 80053ba: f7fe fb35 bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderY, sizeof (float)); 80053be: 2304 movs r3, #4 80053c0: 4a82 ldr r2, [pc, #520] @ (80055cc ) 80053c2: 497d ldr r1, [pc, #500] @ (80055b8 ) 80053c4: 487d ldr r0, [pc, #500] @ (80055bc ) 80053c6: f7fe fb2f bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXStatus, sizeof (uint8_t)); 80053ca: 2301 movs r3, #1 80053cc: 4a80 ldr r2, [pc, #512] @ (80055d0 ) 80053ce: 497a ldr r1, [pc, #488] @ (80055b8 ) 80053d0: 487a ldr r0, [pc, #488] @ (80055bc ) 80053d2: f7fe fb29 bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYStatus, sizeof (uint8_t)); 80053d6: 2301 movs r3, #1 80053d8: 4a7e ldr r2, [pc, #504] @ (80055d4 ) 80053da: 4977 ldr r1, [pc, #476] @ (80055b8 ) 80053dc: 4877 ldr r0, [pc, #476] @ (80055bc ) 80053de: f7fe fb23 bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXAveCurrent, sizeof (float)); 80053e2: 2304 movs r3, #4 80053e4: 4a7c ldr r2, [pc, #496] @ (80055d8 ) 80053e6: 4974 ldr r1, [pc, #464] @ (80055b8 ) 80053e8: 4874 ldr r0, [pc, #464] @ (80055bc ) 80053ea: f7fe fb1d bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYAveCurrent, sizeof (float)); 80053ee: 2304 movs r3, #4 80053f0: 4a7a ldr r2, [pc, #488] @ (80055dc ) 80053f2: 4971 ldr r1, [pc, #452] @ (80055b8 ) 80053f4: 4871 ldr r0, [pc, #452] @ (80055bc ) 80053f6: f7fe fb17 bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXPeakCurrent, sizeof (float)); 80053fa: 2304 movs r3, #4 80053fc: 4a78 ldr r2, [pc, #480] @ (80055e0 ) 80053fe: 496e ldr r1, [pc, #440] @ (80055b8 ) 8005400: 486e ldr r0, [pc, #440] @ (80055bc ) 8005402: f7fe fb11 bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYPeakCurrent, sizeof (float)); 8005406: 2304 movs r3, #4 8005408: 4a76 ldr r2, [pc, #472] @ (80055e4 ) 800540a: 496b ldr r1, [pc, #428] @ (80055b8 ) 800540c: 486b ldr r0, [pc, #428] @ (80055bc ) 800540e: f7fe fb0b bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchUp, sizeof (uint8_t)); 8005412: 2301 movs r3, #1 8005414: 4a74 ldr r2, [pc, #464] @ (80055e8 ) 8005416: 4968 ldr r1, [pc, #416] @ (80055b8 ) 8005418: 4868 ldr r0, [pc, #416] @ (80055bc ) 800541a: f7fe fb05 bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchDown, sizeof (uint8_t)); 800541e: 2301 movs r3, #1 8005420: 4a72 ldr r2, [pc, #456] @ (80055ec ) 8005422: 4965 ldr r1, [pc, #404] @ (80055b8 ) 8005424: 4865 ldr r0, [pc, #404] @ (80055bc ) 8005426: f7fe faff bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchCenter, sizeof (uint8_t)); 800542a: 2301 movs r3, #1 800542c: 4a70 ldr r2, [pc, #448] @ (80055f0 ) 800542e: 4962 ldr r1, [pc, #392] @ (80055b8 ) 8005430: 4862 ldr r0, [pc, #392] @ (80055bc ) 8005432: f7fe faf9 bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchUp, sizeof (uint8_t)); 8005436: 2301 movs r3, #1 8005438: 4a6e ldr r2, [pc, #440] @ (80055f4 ) 800543a: 495f ldr r1, [pc, #380] @ (80055b8 ) 800543c: 485f ldr r0, [pc, #380] @ (80055bc ) 800543e: f7fe faf3 bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchDown, sizeof (uint8_t)); 8005442: 2301 movs r3, #1 8005444: 4a6c ldr r2, [pc, #432] @ (80055f8 ) 8005446: 495c ldr r1, [pc, #368] @ (80055b8 ) 8005448: 485c ldr r0, [pc, #368] @ (80055bc ) 800544a: f7fe faed bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchCenter, sizeof (uint8_t)); 800544e: 2301 movs r3, #1 8005450: 4a6a ldr r2, [pc, #424] @ (80055fc ) 8005452: 4959 ldr r1, [pc, #356] @ (80055b8 ) 8005454: 4859 ldr r0, [pc, #356] @ (80055bc ) 8005456: f7fe fae7 bl 8003a28 uint8_t comparatorOutput = HAL_COMP_GetOutputLevel (&hcomp1) == COMP_OUTPUT_LEVEL_HIGH ? 1 : 0; 800545a: 4869 ldr r0, [pc, #420] @ (8005600 ) 800545c: f002 faf2 bl 8007a44 8005460: 4603 mov r3, r0 8005462: 2b01 cmp r3, #1 8005464: bf0c ite eq 8005466: 2301 moveq r3, #1 8005468: 2300 movne r3, #0 800546a: b2db uxtb r3, r3 800546c: f887 3047 strb.w r3, [r7, #71] @ 0x47 sensorsInfo.powerSupplyFailMask = ~((comparatorOutput << 1) | HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_3)) & 0x01; 8005470: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 8005474: 005c lsls r4, r3, #1 8005476: 2108 movs r1, #8 8005478: 4862 ldr r0, [pc, #392] @ (8005604 ) 800547a: f006 f89b bl 800b5b4 800547e: 4603 mov r3, r0 8005480: 4323 orrs r3, r4 8005482: f003 0301 and.w r3, r3, #1 8005486: 2b00 cmp r3, #0 8005488: bf0c ite eq 800548a: 2301 moveq r3, #1 800548c: 2300 movne r3, #0 800548e: b2db uxtb r3, r3 8005490: 461a mov r2, r3 8005492: 4b48 ldr r3, [pc, #288] @ (80055b4 ) 8005494: f883 202e strb.w r2, [r3, #46] @ 0x2e WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.powerSupplyFailMask, sizeof (uint8_t)); 8005498: 2301 movs r3, #1 800549a: 4a5b ldr r2, [pc, #364] @ (8005608 ) 800549c: 4946 ldr r1, [pc, #280] @ (80055b8 ) 800549e: 4847 ldr r0, [pc, #284] @ (80055bc ) 80054a0: f7fe fac2 bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.currentXPosition, sizeof (float)); 80054a4: 2304 movs r3, #4 80054a6: 4a59 ldr r2, [pc, #356] @ (800560c ) 80054a8: 4943 ldr r1, [pc, #268] @ (80055b8 ) 80054aa: 4844 ldr r0, [pc, #272] @ (80055bc ) 80054ac: f7fe fabc bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.currentYPosition, sizeof (float)); 80054b0: 2304 movs r3, #4 80054b2: 4a57 ldr r2, [pc, #348] @ (8005610 ) 80054b4: 4940 ldr r1, [pc, #256] @ (80055b8 ) 80054b6: 4841 ldr r0, [pc, #260] @ (80055bc ) 80054b8: f7fe fab6 bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.positionXWeak, sizeof (uint8_t)); 80054bc: 2301 movs r3, #1 80054be: 4a55 ldr r2, [pc, #340] @ (8005614 ) 80054c0: 493d ldr r1, [pc, #244] @ (80055b8 ) 80054c2: 483e ldr r0, [pc, #248] @ (80055bc ) 80054c4: f7fe fab0 bl 8003a28 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.positionYWeak, sizeof (uint8_t)); 80054c8: 2301 movs r3, #1 80054ca: 4a53 ldr r2, [pc, #332] @ (8005618 ) 80054cc: 493a ldr r1, [pc, #232] @ (80055b8 ) 80054ce: 483b ldr r0, [pc, #236] @ (80055bc ) 80054d0: f7fe faaa bl 8003a28 osMutexRelease (sensorsInfoMutex); 80054d4: 4b36 ldr r3, [pc, #216] @ (80055b0 ) 80054d6: 681b ldr r3, [r3, #0] 80054d8: 4618 mov r0, r3 80054da: f00f f87b bl 80145d4 respStatus = spOK; 80054de: 2300 movs r3, #0 80054e0: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 80054e4: f000 bc2d b.w 8005d42 respStatus = spInternalError; 80054e8: 23fc movs r3, #252 @ 0xfc 80054ea: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80054ee: f000 bc28 b.w 8005d42 case spSetFanSpeed: osTimerStop (fanTimerHandle); 80054f2: 4b4a ldr r3, [pc, #296] @ (800561c ) 80054f4: 681b ldr r3, [r3, #0] 80054f6: 4618 mov r0, r3 80054f8: f00e ff64 bl 80143c4 int32_t fanTimerPeriod = 0; 80054fc: 2300 movs r3, #0 80054fe: 643b str r3, [r7, #64] @ 0x40 uint32_t pulse = 0; 8005500: 2300 movs r3, #0 8005502: 63fb str r3, [r7, #60] @ 0x3c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse); 8005504: 683b ldr r3, [r7, #0] 8005506: 330c adds r3, #12 8005508: f107 023c add.w r2, r7, #60 @ 0x3c 800550c: f107 0144 add.w r1, r7, #68 @ 0x44 8005510: 4618 mov r0, r3 8005512: f7fe faef bl 8003af4 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&fanTimerPeriod); 8005516: 683b ldr r3, [r7, #0] 8005518: 330c adds r3, #12 800551a: f107 0240 add.w r2, r7, #64 @ 0x40 800551e: f107 0144 add.w r1, r7, #68 @ 0x44 8005522: 4618 mov r0, r3 8005524: f7fe fae6 bl 8003af4 fanTimerConfigOC.Pulse = pulse * 10; 8005528: 6bfa ldr r2, [r7, #60] @ 0x3c 800552a: 4613 mov r3, r2 800552c: 009b lsls r3, r3, #2 800552e: 4413 add r3, r2 8005530: 005b lsls r3, r3, #1 8005532: 461a mov r2, r3 8005534: 4b3a ldr r3, [pc, #232] @ (8005620 ) 8005536: 605a str r2, [r3, #4] if (HAL_TIM_PWM_ConfigChannel (&htim1, &fanTimerConfigOC, TIM_CHANNEL_2) != HAL_OK) { 8005538: 2204 movs r2, #4 800553a: 4939 ldr r1, [pc, #228] @ (8005620 ) 800553c: 4839 ldr r0, [pc, #228] @ (8005624 ) 800553e: f00a fe45 bl 80101cc 8005542: 4603 mov r3, r0 8005544: 2b00 cmp r3, #0 8005546: d001 beq.n 800554c Error_Handler (); 8005548: f7fc fcc0 bl 8001ecc } if (fanTimerPeriod > 0) { 800554c: 6c3b ldr r3, [r7, #64] @ 0x40 800554e: 2b00 cmp r3, #0 8005550: dd0f ble.n 8005572 osTimerStart (fanTimerHandle, fanTimerPeriod * 1000); 8005552: 4b32 ldr r3, [pc, #200] @ (800561c ) 8005554: 681a ldr r2, [r3, #0] 8005556: 6c3b ldr r3, [r7, #64] @ 0x40 8005558: f44f 717a mov.w r1, #1000 @ 0x3e8 800555c: fb01 f303 mul.w r3, r1, r3 8005560: 4619 mov r1, r3 8005562: 4610 mov r0, r2 8005564: f00e ff00 bl 8014368 HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 8005568: 2104 movs r1, #4 800556a: 482e ldr r0, [pc, #184] @ (8005624 ) 800556c: f00a f934 bl 800f7d8 8005570: e019 b.n 80055a6 } else if (fanTimerPeriod == 0) { 8005572: 6c3b ldr r3, [r7, #64] @ 0x40 8005574: 2b00 cmp r3, #0 8005576: d109 bne.n 800558c osTimerStop (fanTimerHandle); 8005578: 4b28 ldr r3, [pc, #160] @ (800561c ) 800557a: 681b ldr r3, [r3, #0] 800557c: 4618 mov r0, r3 800557e: f00e ff21 bl 80143c4 HAL_TIM_PWM_Stop (&htim1, TIM_CHANNEL_2); 8005582: 2104 movs r1, #4 8005584: 4827 ldr r0, [pc, #156] @ (8005624 ) 8005586: f00a fa35 bl 800f9f4 800558a: e00c b.n 80055a6 } else if (fanTimerPeriod == -1) { 800558c: 6c3b ldr r3, [r7, #64] @ 0x40 800558e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8005592: d108 bne.n 80055a6 osTimerStop (fanTimerHandle); 8005594: 4b21 ldr r3, [pc, #132] @ (800561c ) 8005596: 681b ldr r3, [r3, #0] 8005598: 4618 mov r0, r3 800559a: f00e ff13 bl 80143c4 HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 800559e: 2104 movs r1, #4 80055a0: 4820 ldr r0, [pc, #128] @ (8005624 ) 80055a2: f00a f919 bl 800f7d8 } respStatus = spOK; 80055a6: 2300 movs r3, #0 80055a8: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80055ac: e3c9 b.n 8005d42 80055ae: bf00 nop 80055b0: 2400081c .word 0x2400081c 80055b4: 24000860 .word 0x24000860 80055b8: 2400105c .word 0x2400105c 80055bc: 24000fdc .word 0x24000fdc 80055c0: 24000864 .word 0x24000864 80055c4: 24000868 .word 0x24000868 80055c8: 2400086c .word 0x2400086c 80055cc: 24000870 .word 0x24000870 80055d0: 24000874 .word 0x24000874 80055d4: 24000875 .word 0x24000875 80055d8: 24000878 .word 0x24000878 80055dc: 2400087c .word 0x2400087c 80055e0: 24000880 .word 0x24000880 80055e4: 24000884 .word 0x24000884 80055e8: 24000888 .word 0x24000888 80055ec: 24000889 .word 0x24000889 80055f0: 2400088a .word 0x2400088a 80055f4: 2400088b .word 0x2400088b 80055f8: 2400088c .word 0x2400088c 80055fc: 2400088d .word 0x2400088d 8005600: 240003b4 .word 0x240003b4 8005604: 58020c00 .word 0x58020c00 8005608: 2400088e .word 0x2400088e 800560c: 24000890 .word 0x24000890 8005610: 24000894 .word 0x24000894 8005614: 24000898 .word 0x24000898 8005618: 24000899 .word 0x24000899 800561c: 24000714 .word 0x24000714 8005620: 240007a4 .word 0x240007a4 8005624: 2400043c .word 0x2400043c case spSetMotorXOn: int32_t motorXPWMPulse = 0; 8005628: 2300 movs r3, #0 800562a: 63bb str r3, [r7, #56] @ 0x38 int32_t motorXTimerPeriod = 0; 800562c: 2300 movs r3, #0 800562e: 637b str r3, [r7, #52] @ 0x34 uint32_t motorXStatus = 0; 8005630: 2300 movs r3, #0 8005632: 64bb str r3, [r7, #72] @ 0x48 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXPWMPulse); 8005634: 683b ldr r3, [r7, #0] 8005636: 330c adds r3, #12 8005638: f107 0238 add.w r2, r7, #56 @ 0x38 800563c: f107 0144 add.w r1, r7, #68 @ 0x44 8005640: 4618 mov r0, r3 8005642: f7fe fa57 bl 8003af4 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXTimerPeriod); 8005646: 683b ldr r3, [r7, #0] 8005648: 330c adds r3, #12 800564a: f107 0234 add.w r2, r7, #52 @ 0x34 800564e: f107 0144 add.w r1, r7, #68 @ 0x44 8005652: 4618 mov r0, r3 8005654: f7fe fa4e bl 8003af4 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8005658: 4bab ldr r3, [pc, #684] @ (8005908 ) 800565a: 681b ldr r3, [r3, #0] 800565c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005660: 4618 mov r0, r3 8005662: f00e ff6c bl 801453e 8005666: 4603 mov r3, r0 8005668: 2b00 cmp r3, #0 800566a: d12a bne.n 80056c2 motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, motorXPWMPulse, motorXTimerPeriod, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 800566c: 4ba7 ldr r3, [pc, #668] @ (800590c ) 800566e: 681b ldr r3, [r3, #0] 8005670: 6bba ldr r2, [r7, #56] @ 0x38 8005672: 6b79 ldr r1, [r7, #52] @ 0x34 8005674: 48a6 ldr r0, [pc, #664] @ (8005910 ) 8005676: f890 0028 ldrb.w r0, [r0, #40] @ 0x28 800567a: 4ca5 ldr r4, [pc, #660] @ (8005910 ) 800567c: f894 4029 ldrb.w r4, [r4, #41] @ 0x29 8005680: 9404 str r4, [sp, #16] 8005682: 9003 str r0, [sp, #12] 8005684: 9102 str r1, [sp, #8] 8005686: 9201 str r2, [sp, #4] 8005688: 9300 str r3, [sp, #0] 800568a: 2304 movs r3, #4 800568c: 2200 movs r2, #0 800568e: 49a1 ldr r1, [pc, #644] @ (8005914 ) 8005690: 48a1 ldr r0, [pc, #644] @ (8005918 ) 8005692: f7fd fcf5 bl 8003080 8005696: 4603 mov r3, r0 motorXStatus = 8005698: 64bb str r3, [r7, #72] @ 0x48 sensorsInfo.motorXStatus = motorXStatus; 800569a: 6cbb ldr r3, [r7, #72] @ 0x48 800569c: b2da uxtb r2, r3 800569e: 4b9c ldr r3, [pc, #624] @ (8005910 ) 80056a0: 751a strb r2, [r3, #20] if (motorXStatus == 1) { 80056a2: 6cbb ldr r3, [r7, #72] @ 0x48 80056a4: 2b01 cmp r3, #1 80056a6: d103 bne.n 80056b0 sensorsInfo.motorXPeakCurrent = 0.0; 80056a8: 4b99 ldr r3, [pc, #612] @ (8005910 ) 80056aa: f04f 0200 mov.w r2, #0 80056ae: 621a str r2, [r3, #32] } osMutexRelease (sensorsInfoMutex); 80056b0: 4b95 ldr r3, [pc, #596] @ (8005908 ) 80056b2: 681b ldr r3, [r3, #0] 80056b4: 4618 mov r0, r3 80056b6: f00e ff8d bl 80145d4 respStatus = spOK; 80056ba: 2300 movs r3, #0 80056bc: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 80056c0: e33f b.n 8005d42 respStatus = spInternalError; 80056c2: 23fc movs r3, #252 @ 0xfc 80056c4: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80056c8: e33b b.n 8005d42 case spSetMotorYOn: int32_t motorYPWMPulse = 0; 80056ca: 2300 movs r3, #0 80056cc: 633b str r3, [r7, #48] @ 0x30 int32_t motorYTimerPeriod = 0; 80056ce: 2300 movs r3, #0 80056d0: 62fb str r3, [r7, #44] @ 0x2c uint32_t motorYStatus = 0; 80056d2: 2300 movs r3, #0 80056d4: 64fb str r3, [r7, #76] @ 0x4c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYPWMPulse); 80056d6: 683b ldr r3, [r7, #0] 80056d8: 330c adds r3, #12 80056da: f107 0230 add.w r2, r7, #48 @ 0x30 80056de: f107 0144 add.w r1, r7, #68 @ 0x44 80056e2: 4618 mov r0, r3 80056e4: f7fe fa06 bl 8003af4 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYTimerPeriod); 80056e8: 683b ldr r3, [r7, #0] 80056ea: 330c adds r3, #12 80056ec: f107 022c add.w r2, r7, #44 @ 0x2c 80056f0: f107 0144 add.w r1, r7, #68 @ 0x44 80056f4: 4618 mov r0, r3 80056f6: f7fe f9fd bl 8003af4 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80056fa: 4b83 ldr r3, [pc, #524] @ (8005908 ) 80056fc: 681b ldr r3, [r3, #0] 80056fe: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005702: 4618 mov r0, r3 8005704: f00e ff1b bl 801453e 8005708: 4603 mov r3, r0 800570a: 2b00 cmp r3, #0 800570c: d12a bne.n 8005764 motorYStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, motorYPWMPulse, motorYTimerPeriod, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 800570e: 4b83 ldr r3, [pc, #524] @ (800591c ) 8005710: 681b ldr r3, [r3, #0] 8005712: 6b3a ldr r2, [r7, #48] @ 0x30 8005714: 6af9 ldr r1, [r7, #44] @ 0x2c 8005716: 487e ldr r0, [pc, #504] @ (8005910 ) 8005718: f890 002b ldrb.w r0, [r0, #43] @ 0x2b 800571c: 4c7c ldr r4, [pc, #496] @ (8005910 ) 800571e: f894 402c ldrb.w r4, [r4, #44] @ 0x2c 8005722: 9404 str r4, [sp, #16] 8005724: 9003 str r0, [sp, #12] 8005726: 9102 str r1, [sp, #8] 8005728: 9201 str r2, [sp, #4] 800572a: 9300 str r3, [sp, #0] 800572c: 230c movs r3, #12 800572e: 2208 movs r2, #8 8005730: 4978 ldr r1, [pc, #480] @ (8005914 ) 8005732: 4879 ldr r0, [pc, #484] @ (8005918 ) 8005734: f7fd fca4 bl 8003080 8005738: 4603 mov r3, r0 motorYStatus = 800573a: 64fb str r3, [r7, #76] @ 0x4c sensorsInfo.motorYStatus = motorYStatus; 800573c: 6cfb ldr r3, [r7, #76] @ 0x4c 800573e: b2da uxtb r2, r3 8005740: 4b73 ldr r3, [pc, #460] @ (8005910 ) 8005742: 755a strb r2, [r3, #21] if (motorYStatus == 1) { 8005744: 6cfb ldr r3, [r7, #76] @ 0x4c 8005746: 2b01 cmp r3, #1 8005748: d103 bne.n 8005752 sensorsInfo.motorYPeakCurrent = 0.0; 800574a: 4b71 ldr r3, [pc, #452] @ (8005910 ) 800574c: f04f 0200 mov.w r2, #0 8005750: 625a str r2, [r3, #36] @ 0x24 } osMutexRelease (sensorsInfoMutex); 8005752: 4b6d ldr r3, [pc, #436] @ (8005908 ) 8005754: 681b ldr r3, [r3, #0] 8005756: 4618 mov r0, r3 8005758: f00e ff3c bl 80145d4 respStatus = spOK; 800575c: 2300 movs r3, #0 800575e: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005762: e2ee b.n 8005d42 respStatus = spInternalError; 8005764: 23fc movs r3, #252 @ 0xfc 8005766: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 800576a: e2ea b.n 8005d42 case spSetDiodeOn: osTimerStop (debugLedTimerHandle); 800576c: 4b6c ldr r3, [pc, #432] @ (8005920 ) 800576e: 681b ldr r3, [r3, #0] 8005770: 4618 mov r0, r3 8005772: f00e fe27 bl 80143c4 int32_t dbgLedTimerPeriod = 0; 8005776: 2300 movs r3, #0 8005778: 62bb str r3, [r7, #40] @ 0x28 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&dbgLedTimerPeriod); 800577a: 683b ldr r3, [r7, #0] 800577c: 330c adds r3, #12 800577e: f107 0228 add.w r2, r7, #40 @ 0x28 8005782: f107 0144 add.w r1, r7, #68 @ 0x44 8005786: 4618 mov r0, r3 8005788: f7fe f9b4 bl 8003af4 if (dbgLedTimerPeriod > 0) { 800578c: 6abb ldr r3, [r7, #40] @ 0x28 800578e: 2b00 cmp r3, #0 8005790: dd0e ble.n 80057b0 osTimerStart (debugLedTimerHandle, dbgLedTimerPeriod * 1000); 8005792: 4b63 ldr r3, [pc, #396] @ (8005920 ) 8005794: 681a ldr r2, [r3, #0] 8005796: 6abb ldr r3, [r7, #40] @ 0x28 8005798: f44f 717a mov.w r1, #1000 @ 0x3e8 800579c: fb01 f303 mul.w r3, r1, r3 80057a0: 4619 mov r1, r3 80057a2: 4610 mov r0, r2 80057a4: f00e fde0 bl 8014368 DbgLEDOn (DBG_LED1); 80057a8: 2010 movs r0, #16 80057aa: f7fd fbdb bl 8002f64 80057ae: e017 b.n 80057e0 } else if (dbgLedTimerPeriod == 0) { 80057b0: 6abb ldr r3, [r7, #40] @ 0x28 80057b2: 2b00 cmp r3, #0 80057b4: d108 bne.n 80057c8 osTimerStop (debugLedTimerHandle); 80057b6: 4b5a ldr r3, [pc, #360] @ (8005920 ) 80057b8: 681b ldr r3, [r3, #0] 80057ba: 4618 mov r0, r3 80057bc: f00e fe02 bl 80143c4 DbgLEDOff (DBG_LED1); 80057c0: 2010 movs r0, #16 80057c2: f7fd fbe1 bl 8002f88 80057c6: e00b b.n 80057e0 } else if (dbgLedTimerPeriod == -1) { 80057c8: 6abb ldr r3, [r7, #40] @ 0x28 80057ca: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80057ce: d107 bne.n 80057e0 osTimerStop (debugLedTimerHandle); 80057d0: 4b53 ldr r3, [pc, #332] @ (8005920 ) 80057d2: 681b ldr r3, [r3, #0] 80057d4: 4618 mov r0, r3 80057d6: f00e fdf5 bl 80143c4 DbgLEDOn (DBG_LED1); 80057da: 2010 movs r0, #16 80057dc: f7fd fbc2 bl 8002f64 } respStatus = spOK; 80057e0: 2300 movs r3, #0 80057e2: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80057e6: e2ac b.n 8005d42 case spSetmotorXMaxCurrent: float motorXMaxCurrent = 0; 80057e8: f04f 0300 mov.w r3, #0 80057ec: 627b str r3, [r7, #36] @ 0x24 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXMaxCurrent); 80057ee: 683b ldr r3, [r7, #0] 80057f0: 330c adds r3, #12 80057f2: f107 0224 add.w r2, r7, #36 @ 0x24 80057f6: f107 0144 add.w r1, r7, #68 @ 0x44 80057fa: 4618 mov r0, r3 80057fc: f7fe f97a bl 8003af4 uint32_t dacDataCh1 = (uint32_t)(4095 * motorXMaxCurrent / (EXT_VREF_mV * 0.001)); 8005800: edd7 7a09 vldr s15, [r7, #36] @ 0x24 8005804: ed9f 7a47 vldr s14, [pc, #284] @ 8005924 8005808: ee67 7a87 vmul.f32 s15, s15, s14 800580c: eeb7 6ae7 vcvt.f64.f32 d6, s15 8005810: eeb0 5b08 vmov.f64 d5, #8 @ 0x40400000 3.0 8005814: ee86 7b05 vdiv.f64 d7, d6, d5 8005818: eefc 7bc7 vcvt.u32.f64 s15, d7 800581c: ee17 3a90 vmov r3, s15 8005820: 653b str r3, [r7, #80] @ 0x50 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, dacDataCh1); 8005822: 6d3b ldr r3, [r7, #80] @ 0x50 8005824: 2200 movs r2, #0 8005826: 2100 movs r1, #0 8005828: 483f ldr r0, [pc, #252] @ (8005928 ) 800582a: f002 fd56 bl 80082da HAL_DAC_Start (&hdac1, DAC_CHANNEL_1); 800582e: 2100 movs r1, #0 8005830: 483d ldr r0, [pc, #244] @ (8005928 ) 8005832: f002 fca5 bl 8008180 respStatus = spOK; 8005836: 2300 movs r3, #0 8005838: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 800583c: e281 b.n 8005d42 case spSetmotorYMaxCurrent: float motorYMaxCurrent = 0; 800583e: f04f 0300 mov.w r3, #0 8005842: 623b str r3, [r7, #32] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYMaxCurrent); 8005844: 683b ldr r3, [r7, #0] 8005846: 330c adds r3, #12 8005848: f107 0220 add.w r2, r7, #32 800584c: f107 0144 add.w r1, r7, #68 @ 0x44 8005850: 4618 mov r0, r3 8005852: f7fe f94f bl 8003af4 uint32_t dacDataCh2 = (uint32_t)(4095 * motorYMaxCurrent / (EXT_VREF_mV * 0.001)); 8005856: edd7 7a08 vldr s15, [r7, #32] 800585a: ed9f 7a32 vldr s14, [pc, #200] @ 8005924 800585e: ee67 7a87 vmul.f32 s15, s15, s14 8005862: eeb7 6ae7 vcvt.f64.f32 d6, s15 8005866: eeb0 5b08 vmov.f64 d5, #8 @ 0x40400000 3.0 800586a: ee86 7b05 vdiv.f64 d7, d6, d5 800586e: eefc 7bc7 vcvt.u32.f64 s15, d7 8005872: ee17 3a90 vmov r3, s15 8005876: 657b str r3, [r7, #84] @ 0x54 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, dacDataCh2); 8005878: 6d7b ldr r3, [r7, #84] @ 0x54 800587a: 2200 movs r2, #0 800587c: 2110 movs r1, #16 800587e: 482a ldr r0, [pc, #168] @ (8005928 ) 8005880: f002 fd2b bl 80082da HAL_DAC_Start (&hdac1, DAC_CHANNEL_2); 8005884: 2110 movs r1, #16 8005886: 4828 ldr r0, [pc, #160] @ (8005928 ) 8005888: f002 fc7a bl 8008180 respStatus = spOK; 800588c: 2300 movs r3, #0 800588e: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005892: e256 b.n 8005d42 case spClearPeakMeasurments: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005894: 4b25 ldr r3, [pc, #148] @ (800592c ) 8005896: 681b ldr r3, [r3, #0] 8005898: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800589c: 4618 mov r0, r3 800589e: f00e fe4e bl 801453e 80058a2: 4603 mov r3, r0 80058a4: 2b00 cmp r3, #0 80058a6: d12a bne.n 80058fe for (int i = 0; i < 3; i++) { 80058a8: 2300 movs r3, #0 80058aa: 67fb str r3, [r7, #124] @ 0x7c 80058ac: e01b b.n 80058e6 resMeasurements.voltagePeak[i] = resMeasurements.voltageRMS[i]; 80058ae: 4a20 ldr r2, [pc, #128] @ (8005930 ) 80058b0: 6ffb ldr r3, [r7, #124] @ 0x7c 80058b2: 009b lsls r3, r3, #2 80058b4: 4413 add r3, r2 80058b6: 681a ldr r2, [r3, #0] 80058b8: 491d ldr r1, [pc, #116] @ (8005930 ) 80058ba: 6ffb ldr r3, [r7, #124] @ 0x7c 80058bc: 3302 adds r3, #2 80058be: 009b lsls r3, r3, #2 80058c0: 440b add r3, r1 80058c2: 3304 adds r3, #4 80058c4: 601a str r2, [r3, #0] resMeasurements.currentPeak[i] = resMeasurements.currentRMS[i]; 80058c6: 4a1a ldr r2, [pc, #104] @ (8005930 ) 80058c8: 6ffb ldr r3, [r7, #124] @ 0x7c 80058ca: 3306 adds r3, #6 80058cc: 009b lsls r3, r3, #2 80058ce: 4413 add r3, r2 80058d0: 681a ldr r2, [r3, #0] 80058d2: 4917 ldr r1, [pc, #92] @ (8005930 ) 80058d4: 6ffb ldr r3, [r7, #124] @ 0x7c 80058d6: 3308 adds r3, #8 80058d8: 009b lsls r3, r3, #2 80058da: 440b add r3, r1 80058dc: 3304 adds r3, #4 80058de: 601a str r2, [r3, #0] for (int i = 0; i < 3; i++) { 80058e0: 6ffb ldr r3, [r7, #124] @ 0x7c 80058e2: 3301 adds r3, #1 80058e4: 67fb str r3, [r7, #124] @ 0x7c 80058e6: 6ffb ldr r3, [r7, #124] @ 0x7c 80058e8: 2b02 cmp r3, #2 80058ea: dde0 ble.n 80058ae } osMutexRelease (resMeasurementsMutex); 80058ec: 4b0f ldr r3, [pc, #60] @ (800592c ) 80058ee: 681b ldr r3, [r3, #0] 80058f0: 4618 mov r0, r3 80058f2: f00e fe6f bl 80145d4 respStatus = spOK; 80058f6: 2300 movs r3, #0 80058f8: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 80058fc: e221 b.n 8005d42 respStatus = spInternalError; 80058fe: 23fc movs r3, #252 @ 0xfc 8005900: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005904: e21d b.n 8005d42 8005906: bf00 nop 8005908: 2400081c .word 0x2400081c 800590c: 24000744 .word 0x24000744 8005910: 24000860 .word 0x24000860 8005914: 240007c0 .word 0x240007c0 8005918: 240004d4 .word 0x240004d4 800591c: 24000774 .word 0x24000774 8005920: 240006e4 .word 0x240006e4 8005924: 457ff000 .word 0x457ff000 8005928: 24000404 .word 0x24000404 800592c: 24000818 .word 0x24000818 8005930: 24000824 .word 0x24000824 case spSetEncoderXValue: float enocoderXValue = 0; 8005934: f04f 0300 mov.w r3, #0 8005938: 61fb str r3, [r7, #28] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderXValue); 800593a: 683b ldr r3, [r7, #0] 800593c: 330c adds r3, #12 800593e: f107 021c add.w r2, r7, #28 8005942: f107 0144 add.w r1, r7, #68 @ 0x44 8005946: 4618 mov r0, r3 8005948: f7fe f8d4 bl 8003af4 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800594c: 4bbc ldr r3, [pc, #752] @ (8005c40 ) 800594e: 681b ldr r3, [r3, #0] 8005950: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005954: 4618 mov r0, r3 8005956: f00e fdf2 bl 801453e 800595a: 4603 mov r3, r0 800595c: 2b00 cmp r3, #0 800595e: d10b bne.n 8005978 sensorsInfo.pvEncoderX = enocoderXValue; 8005960: 69fb ldr r3, [r7, #28] 8005962: 4ab8 ldr r2, [pc, #736] @ (8005c44 ) 8005964: 60d3 str r3, [r2, #12] osMutexRelease (sensorsInfoMutex); 8005966: 4bb6 ldr r3, [pc, #728] @ (8005c40 ) 8005968: 681b ldr r3, [r3, #0] 800596a: 4618 mov r0, r3 800596c: f00e fe32 bl 80145d4 respStatus = spOK; 8005970: 2300 movs r3, #0 8005972: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005976: e1e4 b.n 8005d42 respStatus = spInternalError; 8005978: 23fc movs r3, #252 @ 0xfc 800597a: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 800597e: e1e0 b.n 8005d42 case spSetEncoderYValue: float enocoderYValue = 0; 8005980: f04f 0300 mov.w r3, #0 8005984: 61bb str r3, [r7, #24] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderYValue); 8005986: 683b ldr r3, [r7, #0] 8005988: 330c adds r3, #12 800598a: f107 0218 add.w r2, r7, #24 800598e: f107 0144 add.w r1, r7, #68 @ 0x44 8005992: 4618 mov r0, r3 8005994: f7fe f8ae bl 8003af4 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8005998: 4ba9 ldr r3, [pc, #676] @ (8005c40 ) 800599a: 681b ldr r3, [r3, #0] 800599c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80059a0: 4618 mov r0, r3 80059a2: f00e fdcc bl 801453e 80059a6: 4603 mov r3, r0 80059a8: 2b00 cmp r3, #0 80059aa: d10b bne.n 80059c4 sensorsInfo.pvEncoderY = enocoderYValue; 80059ac: 69bb ldr r3, [r7, #24] 80059ae: 4aa5 ldr r2, [pc, #660] @ (8005c44 ) 80059b0: 6113 str r3, [r2, #16] osMutexRelease (sensorsInfoMutex); 80059b2: 4ba3 ldr r3, [pc, #652] @ (8005c40 ) 80059b4: 681b ldr r3, [r3, #0] 80059b6: 4618 mov r0, r3 80059b8: f00e fe0c bl 80145d4 respStatus = spOK; 80059bc: 2300 movs r3, #0 80059be: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 80059c2: e1be b.n 8005d42 respStatus = spInternalError; 80059c4: 23fc movs r3, #252 @ 0xfc 80059c6: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80059ca: e1ba b.n 8005d42 case spSetVoltageMeasGains: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 80059cc: 4b9e ldr r3, [pc, #632] @ (8005c48 ) 80059ce: 681b ldr r3, [r3, #0] 80059d0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80059d4: 4618 mov r0, r3 80059d6: f00e fdb2 bl 801453e 80059da: 4603 mov r3, r0 80059dc: 2b00 cmp r3, #0 80059de: d122 bne.n 8005a26 for (uint8_t i = 0; i < 3; i++) { 80059e0: 2300 movs r3, #0 80059e2: f887 307b strb.w r3, [r7, #123] @ 0x7b 80059e6: e011 b.n 8005a0c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].gain); 80059e8: 683b ldr r3, [r7, #0] 80059ea: f103 000c add.w r0, r3, #12 80059ee: f897 307b ldrb.w r3, [r7, #123] @ 0x7b 80059f2: 00db lsls r3, r3, #3 80059f4: 4a95 ldr r2, [pc, #596] @ (8005c4c ) 80059f6: 441a add r2, r3 80059f8: f107 0344 add.w r3, r7, #68 @ 0x44 80059fc: 4619 mov r1, r3 80059fe: f7fe f879 bl 8003af4 for (uint8_t i = 0; i < 3; i++) { 8005a02: f897 307b ldrb.w r3, [r7, #123] @ 0x7b 8005a06: 3301 adds r3, #1 8005a08: f887 307b strb.w r3, [r7, #123] @ 0x7b 8005a0c: f897 307b ldrb.w r3, [r7, #123] @ 0x7b 8005a10: 2b02 cmp r3, #2 8005a12: d9e9 bls.n 80059e8 } osMutexRelease (resMeasurementsMutex); 8005a14: 4b8c ldr r3, [pc, #560] @ (8005c48 ) 8005a16: 681b ldr r3, [r3, #0] 8005a18: 4618 mov r0, r3 8005a1a: f00e fddb bl 80145d4 respStatus = spOK; 8005a1e: 2300 movs r3, #0 8005a20: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005a24: e18d b.n 8005d42 respStatus = spInternalError; 8005a26: 23fc movs r3, #252 @ 0xfc 8005a28: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005a2c: e189 b.n 8005d42 case spSetVoltageMeasOffsets: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005a2e: 4b86 ldr r3, [pc, #536] @ (8005c48 ) 8005a30: 681b ldr r3, [r3, #0] 8005a32: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005a36: 4618 mov r0, r3 8005a38: f00e fd81 bl 801453e 8005a3c: 4603 mov r3, r0 8005a3e: 2b00 cmp r3, #0 8005a40: d123 bne.n 8005a8a for (uint8_t i = 0; i < 3; i++) { 8005a42: 2300 movs r3, #0 8005a44: f887 307a strb.w r3, [r7, #122] @ 0x7a 8005a48: e012 b.n 8005a70 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].offset); 8005a4a: 683b ldr r3, [r7, #0] 8005a4c: f103 000c add.w r0, r3, #12 8005a50: f897 307a ldrb.w r3, [r7, #122] @ 0x7a 8005a54: 00db lsls r3, r3, #3 8005a56: 4a7d ldr r2, [pc, #500] @ (8005c4c ) 8005a58: 4413 add r3, r2 8005a5a: 1d1a adds r2, r3, #4 8005a5c: f107 0344 add.w r3, r7, #68 @ 0x44 8005a60: 4619 mov r1, r3 8005a62: f7fe f847 bl 8003af4 for (uint8_t i = 0; i < 3; i++) { 8005a66: f897 307a ldrb.w r3, [r7, #122] @ 0x7a 8005a6a: 3301 adds r3, #1 8005a6c: f887 307a strb.w r3, [r7, #122] @ 0x7a 8005a70: f897 307a ldrb.w r3, [r7, #122] @ 0x7a 8005a74: 2b02 cmp r3, #2 8005a76: d9e8 bls.n 8005a4a } osMutexRelease (resMeasurementsMutex); 8005a78: 4b73 ldr r3, [pc, #460] @ (8005c48 ) 8005a7a: 681b ldr r3, [r3, #0] 8005a7c: 4618 mov r0, r3 8005a7e: f00e fda9 bl 80145d4 respStatus = spOK; 8005a82: 2300 movs r3, #0 8005a84: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005a88: e15b b.n 8005d42 respStatus = spInternalError; 8005a8a: 23fc movs r3, #252 @ 0xfc 8005a8c: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005a90: e157 b.n 8005d42 case spSetCurrentMeasGains: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005a92: 4b6d ldr r3, [pc, #436] @ (8005c48 ) 8005a94: 681b ldr r3, [r3, #0] 8005a96: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005a9a: 4618 mov r0, r3 8005a9c: f00e fd4f bl 801453e 8005aa0: 4603 mov r3, r0 8005aa2: 2b00 cmp r3, #0 8005aa4: d122 bne.n 8005aec for (uint8_t i = 0; i < 3; i++) { 8005aa6: 2300 movs r3, #0 8005aa8: f887 3079 strb.w r3, [r7, #121] @ 0x79 8005aac: e011 b.n 8005ad2 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].gain); 8005aae: 683b ldr r3, [r7, #0] 8005ab0: f103 000c add.w r0, r3, #12 8005ab4: f897 3079 ldrb.w r3, [r7, #121] @ 0x79 8005ab8: 00db lsls r3, r3, #3 8005aba: 4a65 ldr r2, [pc, #404] @ (8005c50 ) 8005abc: 441a add r2, r3 8005abe: f107 0344 add.w r3, r7, #68 @ 0x44 8005ac2: 4619 mov r1, r3 8005ac4: f7fe f816 bl 8003af4 for (uint8_t i = 0; i < 3; i++) { 8005ac8: f897 3079 ldrb.w r3, [r7, #121] @ 0x79 8005acc: 3301 adds r3, #1 8005ace: f887 3079 strb.w r3, [r7, #121] @ 0x79 8005ad2: f897 3079 ldrb.w r3, [r7, #121] @ 0x79 8005ad6: 2b02 cmp r3, #2 8005ad8: d9e9 bls.n 8005aae } osMutexRelease (resMeasurementsMutex); 8005ada: 4b5b ldr r3, [pc, #364] @ (8005c48 ) 8005adc: 681b ldr r3, [r3, #0] 8005ade: 4618 mov r0, r3 8005ae0: f00e fd78 bl 80145d4 respStatus = spOK; 8005ae4: 2300 movs r3, #0 8005ae6: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005aea: e12a b.n 8005d42 respStatus = spInternalError; 8005aec: 23fc movs r3, #252 @ 0xfc 8005aee: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005af2: e126 b.n 8005d42 case spSetCurrentMeasOffsets: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005af4: 4b54 ldr r3, [pc, #336] @ (8005c48 ) 8005af6: 681b ldr r3, [r3, #0] 8005af8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005afc: 4618 mov r0, r3 8005afe: f00e fd1e bl 801453e 8005b02: 4603 mov r3, r0 8005b04: 2b00 cmp r3, #0 8005b06: d123 bne.n 8005b50 for (uint8_t i = 0; i < 3; i++) { 8005b08: 2300 movs r3, #0 8005b0a: f887 3078 strb.w r3, [r7, #120] @ 0x78 8005b0e: e012 b.n 8005b36 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].offset); 8005b10: 683b ldr r3, [r7, #0] 8005b12: f103 000c add.w r0, r3, #12 8005b16: f897 3078 ldrb.w r3, [r7, #120] @ 0x78 8005b1a: 00db lsls r3, r3, #3 8005b1c: 4a4c ldr r2, [pc, #304] @ (8005c50 ) 8005b1e: 4413 add r3, r2 8005b20: 1d1a adds r2, r3, #4 8005b22: f107 0344 add.w r3, r7, #68 @ 0x44 8005b26: 4619 mov r1, r3 8005b28: f7fd ffe4 bl 8003af4 for (uint8_t i = 0; i < 3; i++) { 8005b2c: f897 3078 ldrb.w r3, [r7, #120] @ 0x78 8005b30: 3301 adds r3, #1 8005b32: f887 3078 strb.w r3, [r7, #120] @ 0x78 8005b36: f897 3078 ldrb.w r3, [r7, #120] @ 0x78 8005b3a: 2b02 cmp r3, #2 8005b3c: d9e8 bls.n 8005b10 } osMutexRelease (resMeasurementsMutex); 8005b3e: 4b42 ldr r3, [pc, #264] @ (8005c48 ) 8005b40: 681b ldr r3, [r3, #0] 8005b42: 4618 mov r0, r3 8005b44: f00e fd46 bl 80145d4 respStatus = spOK; 8005b48: 2300 movs r3, #0 8005b4a: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005b4e: e0f8 b.n 8005d42 respStatus = spInternalError; 8005b50: 23fc movs r3, #252 @ 0xfc 8005b52: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005b56: e0f4 b.n 8005d42 __ASM volatile ("cpsid i" : : : "memory"); 8005b58: b672 cpsid i } 8005b5a: bf00 nop case spResetSystem: __disable_irq(); NVIC_SystemReset(); 8005b5c: f7fe ff62 bl 8004a24 <__NVIC_SystemReset> break; case spSetPositonX: PositionControlTaskData posXData = { 0 }; 8005b60: f04f 0300 mov.w r3, #0 8005b64: 617b str r3, [r7, #20] if (positionXControlTaskInitArg.positionSettingQueue != NULL) 8005b66: 4b3b ldr r3, [pc, #236] @ (8005c54 ) 8005b68: 691b ldr r3, [r3, #16] 8005b6a: 2b00 cmp r3, #0 8005b6c: f000 80e6 beq.w 8005d3c { float posXPercent = 0; 8005b70: f04f 0300 mov.w r3, #0 8005b74: 60fb str r3, [r7, #12] ReadFloatFromBuffer(spFrameData->dataBuffer, &inputDataBufferPos, &posXPercent); 8005b76: 683b ldr r3, [r7, #0] 8005b78: 330c adds r3, #12 8005b7a: f107 020c add.w r2, r7, #12 8005b7e: f107 0144 add.w r1, r7, #68 @ 0x44 8005b82: 4618 mov r0, r3 8005b84: f7fd ff81 bl 8003a8a float posXDegress = MAX_X_AXE_ANGLE * posXPercent * 0.01; 8005b88: edd7 7a03 vldr s15, [r7, #12] 8005b8c: ed9f 7a32 vldr s14, [pc, #200] @ 8005c58 8005b90: ee67 7a87 vmul.f32 s15, s15, s14 8005b94: eeb7 7ae7 vcvt.f64.f32 d7, s15 8005b98: ed9f 6b27 vldr d6, [pc, #156] @ 8005c38 8005b9c: ee27 7b06 vmul.f64 d7, d7, d6 8005ba0: eef7 7bc7 vcvt.f32.f64 s15, d7 8005ba4: edc7 7a18 vstr s15, [r7, #96] @ 0x60 float angleDelta = 360 / ENCODER_X_IMP_PER_TURN; 8005ba8: 4b2c ldr r3, [pc, #176] @ (8005c5c ) 8005baa: 65fb str r3, [r7, #92] @ 0x5c float rest = fmodf(posXDegress, angleDelta); 8005bac: edd7 0a17 vldr s1, [r7, #92] @ 0x5c 8005bb0: ed97 0a18 vldr s0, [r7, #96] @ 0x60 8005bb4: f012 fcde bl 8018574 8005bb8: ed87 0a16 vstr s0, [r7, #88] @ 0x58 if ( rest > (angleDelta/2)) 8005bbc: ed97 7a17 vldr s14, [r7, #92] @ 0x5c 8005bc0: eef0 6a00 vmov.f32 s13, #0 @ 0x40000000 2.0 8005bc4: eec7 7a26 vdiv.f32 s15, s14, s13 8005bc8: ed97 7a16 vldr s14, [r7, #88] @ 0x58 8005bcc: eeb4 7ae7 vcmpe.f32 s14, s15 8005bd0: eef1 fa10 vmrs APSR_nzcv, fpscr 8005bd4: dd14 ble.n 8005c00 { posXData.positionSettingValue = 100 * (posXDegress - rest + angleDelta) / MAX_X_AXE_ANGLE; 8005bd6: ed97 7a18 vldr s14, [r7, #96] @ 0x60 8005bda: edd7 7a16 vldr s15, [r7, #88] @ 0x58 8005bde: ee37 7a67 vsub.f32 s14, s14, s15 8005be2: edd7 7a17 vldr s15, [r7, #92] @ 0x5c 8005be6: ee77 7a27 vadd.f32 s15, s14, s15 8005bea: ed9f 7a1d vldr s14, [pc, #116] @ 8005c60 8005bee: ee27 7a87 vmul.f32 s14, s15, s14 8005bf2: eddf 6a19 vldr s13, [pc, #100] @ 8005c58 8005bf6: eec7 7a26 vdiv.f32 s15, s14, s13 8005bfa: edc7 7a05 vstr s15, [r7, #20] 8005bfe: e00f b.n 8005c20 } else { posXData.positionSettingValue = 100 * (posXDegress - rest) / MAX_X_AXE_ANGLE; 8005c00: ed97 7a18 vldr s14, [r7, #96] @ 0x60 8005c04: edd7 7a16 vldr s15, [r7, #88] @ 0x58 8005c08: ee77 7a67 vsub.f32 s15, s14, s15 8005c0c: ed9f 7a14 vldr s14, [pc, #80] @ 8005c60 8005c10: ee27 7a87 vmul.f32 s14, s15, s14 8005c14: eddf 6a10 vldr s13, [pc, #64] @ 8005c58 8005c18: eec7 7a26 vdiv.f32 s15, s14, s13 8005c1c: edc7 7a05 vstr s15, [r7, #20] } osMessageQueuePut(positionXControlTaskInitArg.positionSettingQueue, &posXData, 0, 0); 8005c20: 4b0c ldr r3, [pc, #48] @ (8005c54 ) 8005c22: 6918 ldr r0, [r3, #16] 8005c24: f107 0114 add.w r1, r7, #20 8005c28: 2300 movs r3, #0 8005c2a: 2200 movs r2, #0 8005c2c: f00e fd82 bl 8014734 } break; 8005c30: e084 b.n 8005d3c 8005c32: bf00 nop 8005c34: f3af 8000 nop.w 8005c38: 47ae147b .word 0x47ae147b 8005c3c: 3f847ae1 .word 0x3f847ae1 8005c40: 2400081c .word 0x2400081c 8005c44: 24000860 .word 0x24000860 8005c48: 24000818 .word 0x24000818 8005c4c: 24000000 .word 0x24000000 8005c50: 24000018 .word 0x24000018 8005c54: 240008b4 .word 0x240008b4 8005c58: 43b40000 .word 0x43b40000 8005c5c: 41900000 .word 0x41900000 8005c60: 42c80000 .word 0x42c80000 case spSetPositonY: PositionControlTaskData posYData = { 0 }; 8005c64: f04f 0300 mov.w r3, #0 8005c68: 613b str r3, [r7, #16] if (positionYControlTaskInitArg.positionSettingQueue != NULL) 8005c6a: 4b4b ldr r3, [pc, #300] @ (8005d98 ) 8005c6c: 691b ldr r3, [r3, #16] 8005c6e: 2b00 cmp r3, #0 8005c70: d066 beq.n 8005d40 { float posYPercent = 0; 8005c72: f04f 0300 mov.w r3, #0 8005c76: 60bb str r3, [r7, #8] ReadFloatFromBuffer(spFrameData->dataBuffer, &inputDataBufferPos, &posYPercent); 8005c78: 683b ldr r3, [r7, #0] 8005c7a: 330c adds r3, #12 8005c7c: f107 0208 add.w r2, r7, #8 8005c80: f107 0144 add.w r1, r7, #68 @ 0x44 8005c84: 4618 mov r0, r3 8005c86: f7fd ff00 bl 8003a8a float posYDegress = MAX_Y_AXE_ANGLE * posYPercent * 0.01; 8005c8a: edd7 7a02 vldr s15, [r7, #8] 8005c8e: ed9f 7a43 vldr s14, [pc, #268] @ 8005d9c 8005c92: ee67 7a87 vmul.f32 s15, s15, s14 8005c96: eeb7 7ae7 vcvt.f64.f32 d7, s15 8005c9a: ed9f 6b3d vldr d6, [pc, #244] @ 8005d90 8005c9e: ee27 7b06 vmul.f64 d7, d7, d6 8005ca2: eef7 7bc7 vcvt.f32.f64 s15, d7 8005ca6: edc7 7a1b vstr s15, [r7, #108] @ 0x6c float angleDelta = 360 / ENCODER_Y_IMP_PER_TURN; 8005caa: 4b3d ldr r3, [pc, #244] @ (8005da0 ) 8005cac: 66bb str r3, [r7, #104] @ 0x68 float rest = fmodf(posYDegress, angleDelta); 8005cae: edd7 0a1a vldr s1, [r7, #104] @ 0x68 8005cb2: ed97 0a1b vldr s0, [r7, #108] @ 0x6c 8005cb6: f012 fc5d bl 8018574 8005cba: ed87 0a19 vstr s0, [r7, #100] @ 0x64 if ( rest > (angleDelta/2)) 8005cbe: ed97 7a1a vldr s14, [r7, #104] @ 0x68 8005cc2: eef0 6a00 vmov.f32 s13, #0 @ 0x40000000 2.0 8005cc6: eec7 7a26 vdiv.f32 s15, s14, s13 8005cca: ed97 7a19 vldr s14, [r7, #100] @ 0x64 8005cce: eeb4 7ae7 vcmpe.f32 s14, s15 8005cd2: eef1 fa10 vmrs APSR_nzcv, fpscr 8005cd6: dd14 ble.n 8005d02 { posYData.positionSettingValue = 100 * (posYDegress - rest + angleDelta) / MAX_Y_AXE_ANGLE; 8005cd8: ed97 7a1b vldr s14, [r7, #108] @ 0x6c 8005cdc: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8005ce0: ee37 7a67 vsub.f32 s14, s14, s15 8005ce4: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8005ce8: ee77 7a27 vadd.f32 s15, s14, s15 8005cec: ed9f 7a2d vldr s14, [pc, #180] @ 8005da4 8005cf0: ee27 7a87 vmul.f32 s14, s15, s14 8005cf4: eddf 6a29 vldr s13, [pc, #164] @ 8005d9c 8005cf8: eec7 7a26 vdiv.f32 s15, s14, s13 8005cfc: edc7 7a04 vstr s15, [r7, #16] 8005d00: e00f b.n 8005d22 } else { posYData.positionSettingValue = 100 * (posYDegress - rest) / MAX_Y_AXE_ANGLE; 8005d02: ed97 7a1b vldr s14, [r7, #108] @ 0x6c 8005d06: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8005d0a: ee77 7a67 vsub.f32 s15, s14, s15 8005d0e: ed9f 7a25 vldr s14, [pc, #148] @ 8005da4 8005d12: ee27 7a87 vmul.f32 s14, s15, s14 8005d16: eddf 6a21 vldr s13, [pc, #132] @ 8005d9c 8005d1a: eec7 7a26 vdiv.f32 s15, s14, s13 8005d1e: edc7 7a04 vstr s15, [r7, #16] } osMessageQueuePut(positionYControlTaskInitArg.positionSettingQueue, &posYData, 0, 0); 8005d22: 4b1d ldr r3, [pc, #116] @ (8005d98 ) 8005d24: 6918 ldr r0, [r3, #16] 8005d26: f107 0110 add.w r1, r7, #16 8005d2a: 2300 movs r3, #0 8005d2c: 2200 movs r2, #0 8005d2e: f00e fd01 bl 8014734 } break; 8005d32: e005 b.n 8005d40 default: respStatus = spUnknownCommand; break; 8005d34: 23fd movs r3, #253 @ 0xfd 8005d36: f887 3097 strb.w r3, [r7, #151] @ 0x97 8005d3a: e002 b.n 8005d42 break; 8005d3c: bf00 nop 8005d3e: e000 b.n 8005d42 break; 8005d40: bf00 nop } dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8005d42: 6f7b ldr r3, [r7, #116] @ 0x74 8005d44: 6898 ldr r0, [r3, #8] 8005d46: 683b ldr r3, [r7, #0] 8005d48: 8819 ldrh r1, [r3, #0] 8005d4a: 683b ldr r3, [r7, #0] 8005d4c: 789a ldrb r2, [r3, #2] 8005d4e: 4b16 ldr r3, [pc, #88] @ (8005da8 ) 8005d50: 881b ldrh r3, [r3, #0] 8005d52: f997 4097 ldrsb.w r4, [r7, #151] @ 0x97 8005d56: 9301 str r3, [sp, #4] 8005d58: 4b14 ldr r3, [pc, #80] @ (8005dac ) 8005d5a: 9300 str r3, [sp, #0] 8005d5c: 4623 mov r3, r4 8005d5e: f7fd fefd bl 8003b5c 8005d62: 4603 mov r3, r0 8005d64: f8a7 3072 strh.w r3, [r7, #114] @ 0x72 if (dataToSend > 0) { 8005d68: f8b7 3072 ldrh.w r3, [r7, #114] @ 0x72 8005d6c: 2b00 cmp r3, #0 8005d6e: d008 beq.n 8005d82 HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 8005d70: 6f7b ldr r3, [r7, #116] @ 0x74 8005d72: 6b18 ldr r0, [r3, #48] @ 0x30 8005d74: 6f7b ldr r3, [r7, #116] @ 0x74 8005d76: 689b ldr r3, [r3, #8] 8005d78: f8b7 2072 ldrh.w r2, [r7, #114] @ 0x72 8005d7c: 4619 mov r1, r3 8005d7e: f00b fbb1 bl 80114e4 } #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: TX bytes sent: %d\n", uartTaskData->uartNumber, dataToSend); #endif } 8005d82: bf00 nop 8005d84: 379c adds r7, #156 @ 0x9c 8005d86: 46bd mov sp, r7 8005d88: bd90 pop {r4, r7, pc} 8005d8a: bf00 nop 8005d8c: f3af 8000 nop.w 8005d90: 47ae147b .word 0x47ae147b 8005d94: 3f847ae1 .word 0x3f847ae1 8005d98: 240008e8 .word 0x240008e8 8005d9c: 43b40000 .word 0x43b40000 8005da0: 41900000 .word 0x41900000 8005da4: 42c80000 .word 0x42c80000 8005da8: 2400105c .word 0x2400105c 8005dac: 24000fdc .word 0x24000fdc 08005db0 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8005db0: f8df d034 ldr.w sp, [pc, #52] @ 8005de8 /* Call the clock system initialization function.*/ bl SystemInit 8005db4: f7fe fdae bl 8004914 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8005db8: 480c ldr r0, [pc, #48] @ (8005dec ) ldr r1, =_edata 8005dba: 490d ldr r1, [pc, #52] @ (8005df0 ) ldr r2, =_sidata 8005dbc: 4a0d ldr r2, [pc, #52] @ (8005df4 ) movs r3, #0 8005dbe: 2300 movs r3, #0 b LoopCopyDataInit 8005dc0: e002 b.n 8005dc8 08005dc2 : CopyDataInit: ldr r4, [r2, r3] 8005dc2: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8005dc4: 50c4 str r4, [r0, r3] adds r3, r3, #4 8005dc6: 3304 adds r3, #4 08005dc8 : LoopCopyDataInit: adds r4, r0, r3 8005dc8: 18c4 adds r4, r0, r3 cmp r4, r1 8005dca: 428c cmp r4, r1 bcc CopyDataInit 8005dcc: d3f9 bcc.n 8005dc2 /* Zero fill the bss segment. */ ldr r2, =_sbss 8005dce: 4a0a ldr r2, [pc, #40] @ (8005df8 ) ldr r4, =_ebss 8005dd0: 4c0a ldr r4, [pc, #40] @ (8005dfc ) movs r3, #0 8005dd2: 2300 movs r3, #0 b LoopFillZerobss 8005dd4: e001 b.n 8005dda 08005dd6 : FillZerobss: str r3, [r2] 8005dd6: 6013 str r3, [r2, #0] adds r2, r2, #4 8005dd8: 3204 adds r2, #4 08005dda : LoopFillZerobss: cmp r2, r4 8005dda: 42a2 cmp r2, r4 bcc FillZerobss 8005ddc: d3fb bcc.n 8005dd6 /* Call static constructors */ bl __libc_init_array 8005dde: f012 fb3f bl 8018460 <__libc_init_array> /* Call the application's entry point.*/ bl main 8005de2: f7fa fc37 bl 8000654
bx lr 8005de6: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8005de8: 24060000 .word 0x24060000 ldr r0, =_sdata 8005dec: 24000000 .word 0x24000000 ldr r1, =_edata 8005df0: 24000098 .word 0x24000098 ldr r2, =_sidata 8005df4: 080187e4 .word 0x080187e4 ldr r2, =_sbss 8005df8: 240000a0 .word 0x240000a0 ldr r4, =_ebss 8005dfc: 2401318c .word 0x2401318c 08005e00 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8005e00: e7fe b.n 8005e00 ... 08005e04 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8005e04: b580 push {r7, lr} 8005e06: b082 sub sp, #8 8005e08: af00 add r7, sp, #0 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ #endif /* DUAL_CORE && CORE_CM4 */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8005e0a: 2003 movs r0, #3 8005e0c: f001 fee5 bl 8007bda /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8005e10: f006 fbee bl 800c5f0 8005e14: 4602 mov r2, r0 8005e16: 4b15 ldr r3, [pc, #84] @ (8005e6c ) 8005e18: 699b ldr r3, [r3, #24] 8005e1a: 0a1b lsrs r3, r3, #8 8005e1c: f003 030f and.w r3, r3, #15 8005e20: 4913 ldr r1, [pc, #76] @ (8005e70 ) 8005e22: 5ccb ldrb r3, [r1, r3] 8005e24: f003 031f and.w r3, r3, #31 8005e28: fa22 f303 lsr.w r3, r2, r3 8005e2c: 607b str r3, [r7, #4] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8005e2e: 4b0f ldr r3, [pc, #60] @ (8005e6c ) 8005e30: 699b ldr r3, [r3, #24] 8005e32: f003 030f and.w r3, r3, #15 8005e36: 4a0e ldr r2, [pc, #56] @ (8005e70 ) 8005e38: 5cd3 ldrb r3, [r2, r3] 8005e3a: f003 031f and.w r3, r3, #31 8005e3e: 687a ldr r2, [r7, #4] 8005e40: fa22 f303 lsr.w r3, r2, r3 8005e44: 4a0b ldr r2, [pc, #44] @ (8005e74 ) 8005e46: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8005e48: 4a0b ldr r2, [pc, #44] @ (8005e78 ) 8005e4a: 687b ldr r3, [r7, #4] 8005e4c: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8005e4e: 2005 movs r0, #5 8005e50: f7fe fc58 bl 8004704 8005e54: 4603 mov r3, r0 8005e56: 2b00 cmp r3, #0 8005e58: d001 beq.n 8005e5e { return HAL_ERROR; 8005e5a: 2301 movs r3, #1 8005e5c: e002 b.n 8005e64 } /* Init the low level hardware */ HAL_MspInit(); 8005e5e: f7fd ff1b bl 8003c98 /* Return function status */ return HAL_OK; 8005e62: 2300 movs r3, #0 } 8005e64: 4618 mov r0, r3 8005e66: 3708 adds r7, #8 8005e68: 46bd mov sp, r7 8005e6a: bd80 pop {r7, pc} 8005e6c: 58024400 .word 0x58024400 8005e70: 0801878c .word 0x0801878c 8005e74: 24000038 .word 0x24000038 8005e78: 24000034 .word 0x24000034 08005e7c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8005e7c: b480 push {r7} 8005e7e: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 8005e80: 4b06 ldr r3, [pc, #24] @ (8005e9c ) 8005e82: 781b ldrb r3, [r3, #0] 8005e84: 461a mov r2, r3 8005e86: 4b06 ldr r3, [pc, #24] @ (8005ea0 ) 8005e88: 681b ldr r3, [r3, #0] 8005e8a: 4413 add r3, r2 8005e8c: 4a04 ldr r2, [pc, #16] @ (8005ea0 ) 8005e8e: 6013 str r3, [r2, #0] } 8005e90: bf00 nop 8005e92: 46bd mov sp, r7 8005e94: f85d 7b04 ldr.w r7, [sp], #4 8005e98: 4770 bx lr 8005e9a: bf00 nop 8005e9c: 24000040 .word 0x24000040 8005ea0: 24001060 .word 0x24001060 08005ea4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8005ea4: b480 push {r7} 8005ea6: af00 add r7, sp, #0 return uwTick; 8005ea8: 4b03 ldr r3, [pc, #12] @ (8005eb8 ) 8005eaa: 681b ldr r3, [r3, #0] } 8005eac: 4618 mov r0, r3 8005eae: 46bd mov sp, r7 8005eb0: f85d 7b04 ldr.w r7, [sp], #4 8005eb4: 4770 bx lr 8005eb6: bf00 nop 8005eb8: 24001060 .word 0x24001060 08005ebc : /** * @brief Returns the device revision identifier. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { 8005ebc: b480 push {r7} 8005ebe: af00 add r7, sp, #0 return((DBGMCU->IDCODE) >> 16); 8005ec0: 4b03 ldr r3, [pc, #12] @ (8005ed0 ) 8005ec2: 681b ldr r3, [r3, #0] 8005ec4: 0c1b lsrs r3, r3, #16 } 8005ec6: 4618 mov r0, r3 8005ec8: 46bd mov sp, r7 8005eca: f85d 7b04 ldr.w r7, [sp], #4 8005ece: 4770 bx lr 8005ed0: 5c001000 .word 0x5c001000 08005ed4 : * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. * @retval None */ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) { 8005ed4: b480 push {r7} 8005ed6: b083 sub sp, #12 8005ed8: af00 add r7, sp, #0 8005eda: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); 8005edc: 4b06 ldr r3, [pc, #24] @ (8005ef8 ) 8005ede: 681b ldr r3, [r3, #0] 8005ee0: f023 0202 bic.w r2, r3, #2 8005ee4: 4904 ldr r1, [pc, #16] @ (8005ef8 ) 8005ee6: 687b ldr r3, [r7, #4] 8005ee8: 4313 orrs r3, r2 8005eea: 600b str r3, [r1, #0] } 8005eec: bf00 nop 8005eee: 370c adds r7, #12 8005ef0: 46bd mov sp, r7 8005ef2: f85d 7b04 ldr.w r7, [sp], #4 8005ef6: 4770 bx lr 8005ef8: 58003c00 .word 0x58003c00 08005efc : * @brief Disable the Internal Voltage Reference buffer (VREFBUF). * * @retval None */ void HAL_SYSCFG_DisableVREFBUF(void) { 8005efc: b480 push {r7} 8005efe: af00 add r7, sp, #0 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); 8005f00: 4b05 ldr r3, [pc, #20] @ (8005f18 ) 8005f02: 681b ldr r3, [r3, #0] 8005f04: 4a04 ldr r2, [pc, #16] @ (8005f18 ) 8005f06: f023 0301 bic.w r3, r3, #1 8005f0a: 6013 str r3, [r2, #0] } 8005f0c: bf00 nop 8005f0e: 46bd mov sp, r7 8005f10: f85d 7b04 ldr.w r7, [sp], #4 8005f14: 4770 bx lr 8005f16: bf00 nop 8005f18: 58003c00 .word 0x58003c00 08005f1c : * @arg SYSCFG_SWITCH_PC3_CLOSE * @retval None */ void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ) { 8005f1c: b480 push {r7} 8005f1e: b083 sub sp, #12 8005f20: af00 add r7, sp, #0 8005f22: 6078 str r0, [r7, #4] 8005f24: 6039 str r1, [r7, #0] /* Check the parameter */ assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch)); assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState)); MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState)); 8005f26: 4b07 ldr r3, [pc, #28] @ (8005f44 ) 8005f28: 685a ldr r2, [r3, #4] 8005f2a: 687b ldr r3, [r7, #4] 8005f2c: 43db mvns r3, r3 8005f2e: 401a ands r2, r3 8005f30: 4904 ldr r1, [pc, #16] @ (8005f44 ) 8005f32: 683b ldr r3, [r7, #0] 8005f34: 4313 orrs r3, r2 8005f36: 604b str r3, [r1, #4] } 8005f38: bf00 nop 8005f3a: 370c adds r7, #12 8005f3c: 46bd mov sp, r7 8005f3e: f85d 7b04 ldr.w r7, [sp], #4 8005f42: 4770 bx lr 8005f44: 58000400 .word 0x58000400 08005f48 : * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) { 8005f48: b480 push {r7} 8005f4a: b083 sub sp, #12 8005f4c: af00 add r7, sp, #0 8005f4e: 6078 str r0, [r7, #4] 8005f50: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); 8005f52: 687b ldr r3, [r7, #4] 8005f54: 689b ldr r3, [r3, #8] 8005f56: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000 8005f5a: 683b ldr r3, [r7, #0] 8005f5c: 431a orrs r2, r3 8005f5e: 687b ldr r3, [r7, #4] 8005f60: 609a str r2, [r3, #8] } 8005f62: bf00 nop 8005f64: 370c adds r7, #12 8005f66: 46bd mov sp, r7 8005f68: f85d 7b04 ldr.w r7, [sp], #4 8005f6c: 4770 bx lr 08005f6e : * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { 8005f6e: b480 push {r7} 8005f70: b083 sub sp, #12 8005f72: af00 add r7, sp, #0 8005f74: 6078 str r0, [r7, #4] 8005f76: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); 8005f78: 687b ldr r3, [r7, #4] 8005f7a: 689b ldr r3, [r3, #8] 8005f7c: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000 8005f80: 683b ldr r3, [r7, #0] 8005f82: 431a orrs r2, r3 8005f84: 687b ldr r3, [r7, #4] 8005f86: 609a str r2, [r3, #8] } 8005f88: bf00 nop 8005f8a: 370c adds r7, #12 8005f8c: 46bd mov sp, r7 8005f8e: f85d 7b04 ldr.w r7, [sp], #4 8005f92: 4770 bx lr 08005f94 : * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) { 8005f94: b480 push {r7} 8005f96: b083 sub sp, #12 8005f98: af00 add r7, sp, #0 8005f9a: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 8005f9c: 687b ldr r3, [r7, #4] 8005f9e: 689b ldr r3, [r3, #8] 8005fa0: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000 } 8005fa4: 4618 mov r0, r3 8005fa6: 370c adds r7, #12 8005fa8: 46bd mov sp, r7 8005faa: f85d 7b04 ldr.w r7, [sp], #4 8005fae: 4770 bx lr 08005fb0 : * Other channels are slow channels (conversion rate: refer to reference manual). * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x3FFFFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { 8005fb0: b480 push {r7} 8005fb2: b087 sub sp, #28 8005fb4: af00 add r7, sp, #0 8005fb6: 60f8 str r0, [r7, #12] 8005fb8: 60b9 str r1, [r7, #8] 8005fba: 607a str r2, [r7, #4] 8005fbc: 603b str r3, [r7, #0] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8005fbe: 68fb ldr r3, [r7, #12] 8005fc0: 3360 adds r3, #96 @ 0x60 8005fc2: 461a mov r2, r3 8005fc4: 68bb ldr r3, [r7, #8] 8005fc6: 009b lsls r3, r3, #2 8005fc8: 4413 add r3, r2 8005fca: 617b str r3, [r7, #20] ADC3_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } else #endif /* ADC_VER_V5_V90 */ { MODIFY_REG(*preg, 8005fcc: 697b ldr r3, [r7, #20] 8005fce: 681b ldr r3, [r3, #0] 8005fd0: f003 4200 and.w r2, r3, #2147483648 @ 0x80000000 8005fd4: 687b ldr r3, [r7, #4] 8005fd6: f003 41f8 and.w r1, r3, #2080374784 @ 0x7c000000 8005fda: 683b ldr r3, [r7, #0] 8005fdc: 430b orrs r3, r1 8005fde: 431a orrs r2, r3 8005fe0: 697b ldr r3, [r7, #20] 8005fe2: 601a str r2, [r3, #0] ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } } 8005fe4: bf00 nop 8005fe6: 371c adds r7, #28 8005fe8: 46bd mov sp, r7 8005fea: f85d 7b04 ldr.w r7, [sp], #4 8005fee: 4770 bx lr 08005ff0 : * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift) { 8005ff0: b480 push {r7} 8005ff2: b085 sub sp, #20 8005ff4: af00 add r7, sp, #0 8005ff6: 60f8 str r0, [r7, #12] 8005ff8: 60b9 str r1, [r7, #8] 8005ffa: 607a str r2, [r7, #4] MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL)); 8005ffc: 68fb ldr r3, [r7, #12] 8005ffe: 691b ldr r3, [r3, #16] 8006000: f423 42f0 bic.w r2, r3, #30720 @ 0x7800 8006004: 68bb ldr r3, [r7, #8] 8006006: f003 031f and.w r3, r3, #31 800600a: 6879 ldr r1, [r7, #4] 800600c: fa01 f303 lsl.w r3, r1, r3 8006010: 431a orrs r2, r3 8006012: 68fb ldr r3, [r7, #12] 8006014: 611a str r2, [r3, #16] } 8006016: bf00 nop 8006018: 3714 adds r7, #20 800601a: 46bd mov sp, r7 800601c: f85d 7b04 ldr.w r7, [sp], #4 8006020: 4770 bx lr 08006022 : * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation) { 8006022: b480 push {r7} 8006024: b087 sub sp, #28 8006026: af00 add r7, sp, #0 8006028: 60f8 str r0, [r7, #12] 800602a: 60b9 str r1, [r7, #8] 800602c: 607a str r2, [r7, #4] /* Function not available on this instance */ } else #endif /* ADC_VER_V5_V90 */ { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 800602e: 68fb ldr r3, [r7, #12] 8006030: 3360 adds r3, #96 @ 0x60 8006032: 461a mov r2, r3 8006034: 68bb ldr r3, [r7, #8] 8006036: 009b lsls r3, r3, #2 8006038: 4413 add r3, r2 800603a: 617b str r3, [r7, #20] MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation); 800603c: 697b ldr r3, [r7, #20] 800603e: 681b ldr r3, [r3, #0] 8006040: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 8006044: 687b ldr r3, [r7, #4] 8006046: 431a orrs r2, r3 8006048: 697b ldr r3, [r7, #20] 800604a: 601a str r2, [r3, #0] } } 800604c: bf00 nop 800604e: 371c adds r7, #28 8006050: 46bd mov sp, r7 8006052: f85d 7b04 ldr.w r7, [sp], #4 8006056: 4770 bx lr 08006058 : * @param ADCx ADC instance * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { 8006058: b480 push {r7} 800605a: b083 sub sp, #12 800605c: af00 add r7, sp, #0 800605e: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); 8006060: 687b ldr r3, [r7, #4] 8006062: 68db ldr r3, [r3, #12] 8006064: f403 6340 and.w r3, r3, #3072 @ 0xc00 8006068: 2b00 cmp r3, #0 800606a: d101 bne.n 8006070 800606c: 2301 movs r3, #1 800606e: e000 b.n 8006072 8006070: 2300 movs r3, #0 } 8006072: 4618 mov r0, r3 8006074: 370c adds r7, #12 8006076: 46bd mov sp, r7 8006078: f85d 7b04 ldr.w r7, [sp], #4 800607c: 4770 bx lr 0800607e : * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { 800607e: b480 push {r7} 8006080: b087 sub sp, #28 8006082: af00 add r7, sp, #0 8006084: 60f8 str r0, [r7, #12] 8006086: 60b9 str r1, [r7, #8] 8006088: 607a str r2, [r7, #4] /* Set bits with content of parameter "Channel" with bits position */ /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); 800608a: 68fb ldr r3, [r7, #12] 800608c: 3330 adds r3, #48 @ 0x30 800608e: 461a mov r2, r3 8006090: 68bb ldr r3, [r7, #8] 8006092: 0a1b lsrs r3, r3, #8 8006094: 009b lsls r3, r3, #2 8006096: f003 030c and.w r3, r3, #12 800609a: 4413 add r3, r2 800609c: 617b str r3, [r7, #20] MODIFY_REG(*preg, 800609e: 697b ldr r3, [r7, #20] 80060a0: 681a ldr r2, [r3, #0] 80060a2: 68bb ldr r3, [r7, #8] 80060a4: f003 031f and.w r3, r3, #31 80060a8: 211f movs r1, #31 80060aa: fa01 f303 lsl.w r3, r1, r3 80060ae: 43db mvns r3, r3 80060b0: 401a ands r2, r3 80060b2: 687b ldr r3, [r7, #4] 80060b4: 0e9b lsrs r3, r3, #26 80060b6: f003 011f and.w r1, r3, #31 80060ba: 68bb ldr r3, [r7, #8] 80060bc: f003 031f and.w r3, r3, #31 80060c0: fa01 f303 lsl.w r3, r1, r3 80060c4: 431a orrs r2, r3 80060c6: 697b ldr r3, [r7, #20] 80060c8: 601a str r2, [r3, #0] ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } 80060ca: bf00 nop 80060cc: 371c adds r7, #28 80060ce: 46bd mov sp, r7 80060d0: f85d 7b04 ldr.w r7, [sp], #4 80060d4: 4770 bx lr 080060d6 : * @param ADCx ADC instance * @param DataTransferMode Select Data Management configuration * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode) { 80060d6: b480 push {r7} 80060d8: b083 sub sp, #12 80060da: af00 add r7, sp, #0 80060dc: 6078 str r0, [r7, #4] 80060de: 6039 str r1, [r7, #0] MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode); 80060e0: 687b ldr r3, [r7, #4] 80060e2: 68db ldr r3, [r3, #12] 80060e4: f023 0203 bic.w r2, r3, #3 80060e8: 683b ldr r3, [r7, #0] 80060ea: 431a orrs r2, r3 80060ec: 687b ldr r3, [r7, #4] 80060ee: 60da str r2, [r3, #12] } 80060f0: bf00 nop 80060f2: 370c adds r7, #12 80060f4: 46bd mov sp, r7 80060f6: f85d 7b04 ldr.w r7, [sp], #4 80060fa: 4770 bx lr 080060fc : * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5 * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) { 80060fc: b480 push {r7} 80060fe: b087 sub sp, #28 8006100: af00 add r7, sp, #0 8006102: 60f8 str r0, [r7, #12] 8006104: 60b9 str r1, [r7, #8] 8006106: 607a str r2, [r7, #4] /* Set bits with content of parameter "SamplingTime" with bits position */ /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 8006108: 68fb ldr r3, [r7, #12] 800610a: 3314 adds r3, #20 800610c: 461a mov r2, r3 800610e: 68bb ldr r3, [r7, #8] 8006110: 0e5b lsrs r3, r3, #25 8006112: 009b lsls r3, r3, #2 8006114: f003 0304 and.w r3, r3, #4 8006118: 4413 add r3, r2 800611a: 617b str r3, [r7, #20] MODIFY_REG(*preg, 800611c: 697b ldr r3, [r7, #20] 800611e: 681a ldr r2, [r3, #0] 8006120: 68bb ldr r3, [r7, #8] 8006122: 0d1b lsrs r3, r3, #20 8006124: f003 031f and.w r3, r3, #31 8006128: 2107 movs r1, #7 800612a: fa01 f303 lsl.w r3, r1, r3 800612e: 43db mvns r3, r3 8006130: 401a ands r2, r3 8006132: 68bb ldr r3, [r7, #8] 8006134: 0d1b lsrs r3, r3, #20 8006136: f003 031f and.w r3, r3, #31 800613a: 6879 ldr r1, [r7, #4] 800613c: fa01 f303 lsl.w r3, r1, r3 8006140: 431a orrs r2, r3 8006142: 697b ldr r3, [r7, #20] 8006144: 601a str r2, [r3, #0] ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); } 8006146: bf00 nop 8006148: 371c adds r7, #28 800614a: 46bd mov sp, r7 800614c: f85d 7b04 ldr.w r7, [sp], #4 8006150: 4770 bx lr ... 08006154 : * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) { 8006154: b480 push {r7} 8006156: b085 sub sp, #20 8006158: af00 add r7, sp, #0 800615a: 60f8 str r0, [r7, #12] 800615c: 60b9 str r1, [r7, #8] 800615e: 607a str r2, [r7, #4] } #else /* ADC_VER_V5_V90 */ /* Bits of channels in single or differential mode are set only for */ /* differential mode (for single mode, mask of bits allowed to be set is */ /* shifted out of range of bits of channels in single or differential mode. */ MODIFY_REG(ADCx->DIFSEL, 8006160: 68fb ldr r3, [r7, #12] 8006162: f8d3 20c0 ldr.w r2, [r3, #192] @ 0xc0 8006166: 68bb ldr r3, [r7, #8] 8006168: f3c3 0313 ubfx r3, r3, #0, #20 800616c: 43db mvns r3, r3 800616e: 401a ands r2, r3 8006170: 687b ldr r3, [r7, #4] 8006172: f003 0318 and.w r3, r3, #24 8006176: 4908 ldr r1, [pc, #32] @ (8006198 ) 8006178: 40d9 lsrs r1, r3 800617a: 68bb ldr r3, [r7, #8] 800617c: 400b ands r3, r1 800617e: f3c3 0313 ubfx r3, r3, #0, #20 8006182: 431a orrs r2, r3 8006184: 68fb ldr r3, [r7, #12] 8006186: f8c3 20c0 str.w r2, [r3, #192] @ 0xc0 Channel & ADC_SINGLEDIFF_CHANNEL_MASK, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); #endif /* ADC_VER_V5_V90 */ } 800618a: bf00 nop 800618c: 3714 adds r7, #20 800618e: 46bd mov sp, r7 8006190: f85d 7b04 ldr.w r7, [sp], #4 8006194: 4770 bx lr 8006196: bf00 nop 8006198: 000fffff .word 0x000fffff 0800619c : * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) { 800619c: b480 push {r7} 800619e: b083 sub sp, #12 80061a0: af00 add r7, sp, #0 80061a2: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 80061a4: 687b ldr r3, [r7, #4] 80061a6: 689b ldr r3, [r3, #8] 80061a8: f003 031f and.w r3, r3, #31 } 80061ac: 4618 mov r0, r3 80061ae: 370c adds r7, #12 80061b0: 46bd mov sp, r7 80061b2: f85d 7b04 ldr.w r7, [sp], #4 80061b6: 4770 bx lr 080061b8 : * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) { 80061b8: b480 push {r7} 80061ba: b083 sub sp, #12 80061bc: af00 add r7, sp, #0 80061be: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); 80061c0: 687b ldr r3, [r7, #4] 80061c2: 689a ldr r2, [r3, #8] 80061c4: 4b04 ldr r3, [pc, #16] @ (80061d8 ) 80061c6: 4013 ands r3, r2 80061c8: 687a ldr r2, [r7, #4] 80061ca: 6093 str r3, [r2, #8] } 80061cc: bf00 nop 80061ce: 370c adds r7, #12 80061d0: 46bd mov sp, r7 80061d2: f85d 7b04 ldr.w r7, [sp], #4 80061d6: 4770 bx lr 80061d8: 5fffffc0 .word 0x5fffffc0 080061dc : * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) { 80061dc: b480 push {r7} 80061de: b083 sub sp, #12 80061e0: af00 add r7, sp, #0 80061e2: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); 80061e4: 687b ldr r3, [r7, #4] 80061e6: 689b ldr r3, [r3, #8] 80061e8: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80061ec: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80061f0: d101 bne.n 80061f6 80061f2: 2301 movs r3, #1 80061f4: e000 b.n 80061f8 80061f6: 2300 movs r3, #0 } 80061f8: 4618 mov r0, r3 80061fa: 370c adds r7, #12 80061fc: 46bd mov sp, r7 80061fe: f85d 7b04 ldr.w r7, [sp], #4 8006202: 4770 bx lr 08006204 : * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) { 8006204: b480 push {r7} 8006206: b083 sub sp, #12 8006208: af00 add r7, sp, #0 800620a: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 800620c: 687b ldr r3, [r7, #4] 800620e: 689a ldr r2, [r3, #8] 8006210: 4b05 ldr r3, [pc, #20] @ (8006228 ) 8006212: 4013 ands r3, r2 8006214: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000 8006218: 687b ldr r3, [r7, #4] 800621a: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); } 800621c: bf00 nop 800621e: 370c adds r7, #12 8006220: 46bd mov sp, r7 8006222: f85d 7b04 ldr.w r7, [sp], #4 8006226: 4770 bx lr 8006228: 6fffffc0 .word 0x6fffffc0 0800622c : * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) { 800622c: b480 push {r7} 800622e: b083 sub sp, #12 8006230: af00 add r7, sp, #0 8006232: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 8006234: 687b ldr r3, [r7, #4] 8006236: 689b ldr r3, [r3, #8] 8006238: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800623c: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8006240: d101 bne.n 8006246 8006242: 2301 movs r3, #1 8006244: e000 b.n 8006248 8006246: 2300 movs r3, #0 } 8006248: 4618 mov r0, r3 800624a: 370c adds r7, #12 800624c: 46bd mov sp, r7 800624e: f85d 7b04 ldr.w r7, [sp], #4 8006252: 4770 bx lr 08006254 : * @rmtoll CR ADEN LL_ADC_Enable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) { 8006254: b480 push {r7} 8006256: b083 sub sp, #12 8006258: af00 add r7, sp, #0 800625a: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 800625c: 687b ldr r3, [r7, #4] 800625e: 689a ldr r2, [r3, #8] 8006260: 4b05 ldr r3, [pc, #20] @ (8006278 ) 8006262: 4013 ands r3, r2 8006264: f043 0201 orr.w r2, r3, #1 8006268: 687b ldr r3, [r7, #4] 800626a: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN); } 800626c: bf00 nop 800626e: 370c adds r7, #12 8006270: 46bd mov sp, r7 8006272: f85d 7b04 ldr.w r7, [sp], #4 8006276: 4770 bx lr 8006278: 7fffffc0 .word 0x7fffffc0 0800627c : * @rmtoll CR ADDIS LL_ADC_Disable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) { 800627c: b480 push {r7} 800627e: b083 sub sp, #12 8006280: af00 add r7, sp, #0 8006282: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8006284: 687b ldr r3, [r7, #4] 8006286: 689a ldr r2, [r3, #8] 8006288: 4b05 ldr r3, [pc, #20] @ (80062a0 ) 800628a: 4013 ands r3, r2 800628c: f043 0202 orr.w r2, r3, #2 8006290: 687b ldr r3, [r7, #4] 8006292: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS); } 8006294: bf00 nop 8006296: 370c adds r7, #12 8006298: 46bd mov sp, r7 800629a: f85d 7b04 ldr.w r7, [sp], #4 800629e: 4770 bx lr 80062a0: 7fffffc0 .word 0x7fffffc0 080062a4 : * @rmtoll CR ADEN LL_ADC_IsEnabled * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) { 80062a4: b480 push {r7} 80062a6: b083 sub sp, #12 80062a8: af00 add r7, sp, #0 80062aa: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 80062ac: 687b ldr r3, [r7, #4] 80062ae: 689b ldr r3, [r3, #8] 80062b0: f003 0301 and.w r3, r3, #1 80062b4: 2b01 cmp r3, #1 80062b6: d101 bne.n 80062bc 80062b8: 2301 movs r3, #1 80062ba: e000 b.n 80062be 80062bc: 2300 movs r3, #0 } 80062be: 4618 mov r0, r3 80062c0: 370c adds r7, #12 80062c2: 46bd mov sp, r7 80062c4: f85d 7b04 ldr.w r7, [sp], #4 80062c8: 4770 bx lr 080062ca : * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) { 80062ca: b480 push {r7} 80062cc: b083 sub sp, #12 80062ce: af00 add r7, sp, #0 80062d0: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); 80062d2: 687b ldr r3, [r7, #4] 80062d4: 689b ldr r3, [r3, #8] 80062d6: f003 0302 and.w r3, r3, #2 80062da: 2b02 cmp r3, #2 80062dc: d101 bne.n 80062e2 80062de: 2301 movs r3, #1 80062e0: e000 b.n 80062e4 80062e2: 2300 movs r3, #0 } 80062e4: 4618 mov r0, r3 80062e6: 370c adds r7, #12 80062e8: 46bd mov sp, r7 80062ea: f85d 7b04 ldr.w r7, [sp], #4 80062ee: 4770 bx lr 080062f0 : * @rmtoll CR ADSTART LL_ADC_REG_StartConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) { 80062f0: b480 push {r7} 80062f2: b083 sub sp, #12 80062f4: af00 add r7, sp, #0 80062f6: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 80062f8: 687b ldr r3, [r7, #4] 80062fa: 689a ldr r2, [r3, #8] 80062fc: 4b05 ldr r3, [pc, #20] @ (8006314 ) 80062fe: 4013 ands r3, r2 8006300: f043 0204 orr.w r2, r3, #4 8006304: 687b ldr r3, [r7, #4] 8006306: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART); } 8006308: bf00 nop 800630a: 370c adds r7, #12 800630c: 46bd mov sp, r7 800630e: f85d 7b04 ldr.w r7, [sp], #4 8006312: 4770 bx lr 8006314: 7fffffc0 .word 0x7fffffc0 08006318 : * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) { 8006318: b480 push {r7} 800631a: b083 sub sp, #12 800631c: af00 add r7, sp, #0 800631e: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8006320: 687b ldr r3, [r7, #4] 8006322: 689b ldr r3, [r3, #8] 8006324: f003 0304 and.w r3, r3, #4 8006328: 2b04 cmp r3, #4 800632a: d101 bne.n 8006330 800632c: 2301 movs r3, #1 800632e: e000 b.n 8006332 8006330: 2300 movs r3, #0 } 8006332: 4618 mov r0, r3 8006334: 370c adds r7, #12 8006336: 46bd mov sp, r7 8006338: f85d 7b04 ldr.w r7, [sp], #4 800633c: 4770 bx lr 0800633e : * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) { 800633e: b480 push {r7} 8006340: b083 sub sp, #12 8006342: af00 add r7, sp, #0 8006344: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 8006346: 687b ldr r3, [r7, #4] 8006348: 689b ldr r3, [r3, #8] 800634a: f003 0308 and.w r3, r3, #8 800634e: 2b08 cmp r3, #8 8006350: d101 bne.n 8006356 8006352: 2301 movs r3, #1 8006354: e000 b.n 8006358 8006356: 2300 movs r3, #0 } 8006358: 4618 mov r0, r3 800635a: 370c adds r7, #12 800635c: 46bd mov sp, r7 800635e: f85d 7b04 ldr.w r7, [sp], #4 8006362: 4770 bx lr 08006364 : * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { 8006364: b590 push {r4, r7, lr} 8006366: b089 sub sp, #36 @ 0x24 8006368: af00 add r7, sp, #0 800636a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800636c: 2300 movs r3, #0 800636e: 77fb strb r3, [r7, #31] uint32_t tmpCFGR; uint32_t tmp_adc_reg_is_conversion_on_going; __IO uint32_t wait_loop_index = 0UL; 8006370: 2300 movs r3, #0 8006372: 60bb str r3, [r7, #8] uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check ADC handle */ if (hadc == NULL) 8006374: 687b ldr r3, [r7, #4] 8006376: 2b00 cmp r3, #0 8006378: d101 bne.n 800637e { return HAL_ERROR; 800637a: 2301 movs r3, #1 800637c: e18f b.n 800669e assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 800637e: 687b ldr r3, [r7, #4] 8006380: 68db ldr r3, [r3, #12] 8006382: 2b00 cmp r3, #0 /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8006384: 687b ldr r3, [r7, #4] 8006386: 6d5b ldr r3, [r3, #84] @ 0x54 8006388: 2b00 cmp r3, #0 800638a: d109 bne.n 80063a0 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800638c: 6878 ldr r0, [r7, #4] 800638e: f7fd fcdf bl 8003d50 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8006392: 687b ldr r3, [r7, #4] 8006394: 2200 movs r2, #0 8006396: 659a str r2, [r3, #88] @ 0x58 /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; 8006398: 687b ldr r3, [r7, #4] 800639a: 2200 movs r2, #0 800639c: f883 2050 strb.w r2, [r3, #80] @ 0x50 } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) 80063a0: 687b ldr r3, [r7, #4] 80063a2: 681b ldr r3, [r3, #0] 80063a4: 4618 mov r0, r3 80063a6: f7ff ff19 bl 80061dc 80063aa: 4603 mov r3, r0 80063ac: 2b00 cmp r3, #0 80063ae: d004 beq.n 80063ba { /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); 80063b0: 687b ldr r3, [r7, #4] 80063b2: 681b ldr r3, [r3, #0] 80063b4: 4618 mov r0, r3 80063b6: f7ff feff bl 80061b8 /* System was in deep power down mode, calibration must be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 80063ba: 687b ldr r3, [r7, #4] 80063bc: 681b ldr r3, [r3, #0] 80063be: 4618 mov r0, r3 80063c0: f7ff ff34 bl 800622c 80063c4: 4603 mov r3, r0 80063c6: 2b00 cmp r3, #0 80063c8: d114 bne.n 80063f4 { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); 80063ca: 687b ldr r3, [r7, #4] 80063cc: 681b ldr r3, [r3, #0] 80063ce: 4618 mov r0, r3 80063d0: f7ff ff18 bl 8006204 /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 80063d4: 4b87 ldr r3, [pc, #540] @ (80065f4 ) 80063d6: 681b ldr r3, [r3, #0] 80063d8: 099b lsrs r3, r3, #6 80063da: 4a87 ldr r2, [pc, #540] @ (80065f8 ) 80063dc: fba2 2303 umull r2, r3, r2, r3 80063e0: 099b lsrs r3, r3, #6 80063e2: 3301 adds r3, #1 80063e4: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 80063e6: e002 b.n 80063ee { wait_loop_index--; 80063e8: 68bb ldr r3, [r7, #8] 80063ea: 3b01 subs r3, #1 80063ec: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 80063ee: 68bb ldr r3, [r7, #8] 80063f0: 2b00 cmp r3, #0 80063f2: d1f9 bne.n 80063e8 } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 80063f4: 687b ldr r3, [r7, #4] 80063f6: 681b ldr r3, [r3, #0] 80063f8: 4618 mov r0, r3 80063fa: f7ff ff17 bl 800622c 80063fe: 4603 mov r3, r0 8006400: 2b00 cmp r3, #0 8006402: d10d bne.n 8006420 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006404: 687b ldr r3, [r7, #4] 8006406: 6d5b ldr r3, [r3, #84] @ 0x54 8006408: f043 0210 orr.w r2, r3, #16 800640c: 687b ldr r3, [r7, #4] 800640e: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006410: 687b ldr r3, [r7, #4] 8006412: 6d9b ldr r3, [r3, #88] @ 0x58 8006414: f043 0201 orr.w r2, r3, #1 8006418: 687b ldr r3, [r7, #4] 800641a: 659a str r2, [r3, #88] @ 0x58 tmp_hal_status = HAL_ERROR; 800641c: 2301 movs r3, #1 800641e: 77fb strb r3, [r7, #31] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8006420: 687b ldr r3, [r7, #4] 8006422: 681b ldr r3, [r3, #0] 8006424: 4618 mov r0, r3 8006426: f7ff ff77 bl 8006318 800642a: 6178 str r0, [r7, #20] if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 800642c: 687b ldr r3, [r7, #4] 800642e: 6d5b ldr r3, [r3, #84] @ 0x54 8006430: f003 0310 and.w r3, r3, #16 8006434: 2b00 cmp r3, #0 8006436: f040 8129 bne.w 800668c && (tmp_adc_reg_is_conversion_on_going == 0UL) 800643a: 697b ldr r3, [r7, #20] 800643c: 2b00 cmp r3, #0 800643e: f040 8125 bne.w 800668c ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8006442: 687b ldr r3, [r7, #4] 8006444: 6d5b ldr r3, [r3, #84] @ 0x54 8006446: f423 7381 bic.w r3, r3, #258 @ 0x102 800644a: f043 0202 orr.w r2, r3, #2 800644e: 687b ldr r3, [r7, #4] 8006450: 655a str r2, [r3, #84] @ 0x54 /* Configuration of common ADC parameters */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8006452: 687b ldr r3, [r7, #4] 8006454: 681b ldr r3, [r3, #0] 8006456: 4618 mov r0, r3 8006458: f7ff ff24 bl 80062a4 800645c: 4603 mov r3, r0 800645e: 2b00 cmp r3, #0 8006460: d136 bne.n 80064d0 { if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8006462: 687b ldr r3, [r7, #4] 8006464: 681b ldr r3, [r3, #0] 8006466: 4a65 ldr r2, [pc, #404] @ (80065fc ) 8006468: 4293 cmp r3, r2 800646a: d004 beq.n 8006476 800646c: 687b ldr r3, [r7, #4] 800646e: 681b ldr r3, [r3, #0] 8006470: 4a63 ldr r2, [pc, #396] @ (8006600 ) 8006472: 4293 cmp r3, r2 8006474: d10e bne.n 8006494 8006476: 4861 ldr r0, [pc, #388] @ (80065fc ) 8006478: f7ff ff14 bl 80062a4 800647c: 4604 mov r4, r0 800647e: 4860 ldr r0, [pc, #384] @ (8006600 ) 8006480: f7ff ff10 bl 80062a4 8006484: 4603 mov r3, r0 8006486: 4323 orrs r3, r4 8006488: 2b00 cmp r3, #0 800648a: bf0c ite eq 800648c: 2301 moveq r3, #1 800648e: 2300 movne r3, #0 8006490: b2db uxtb r3, r3 8006492: e008 b.n 80064a6 8006494: 485b ldr r0, [pc, #364] @ (8006604 ) 8006496: f7ff ff05 bl 80062a4 800649a: 4603 mov r3, r0 800649c: 2b00 cmp r3, #0 800649e: bf0c ite eq 80064a0: 2301 moveq r3, #1 80064a2: 2300 movne r3, #0 80064a4: b2db uxtb r3, r3 80064a6: 2b00 cmp r3, #0 80064a8: d012 beq.n 80064d0 /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ /* HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); 80064aa: 687b ldr r3, [r7, #4] 80064ac: 681b ldr r3, [r3, #0] 80064ae: 4a53 ldr r2, [pc, #332] @ (80065fc ) 80064b0: 4293 cmp r3, r2 80064b2: d004 beq.n 80064be 80064b4: 687b ldr r3, [r7, #4] 80064b6: 681b ldr r3, [r3, #0] 80064b8: 4a51 ldr r2, [pc, #324] @ (8006600 ) 80064ba: 4293 cmp r3, r2 80064bc: d101 bne.n 80064c2 80064be: 4a52 ldr r2, [pc, #328] @ (8006608 ) 80064c0: e000 b.n 80064c4 80064c2: 4a52 ldr r2, [pc, #328] @ (800660c ) 80064c4: 687b ldr r3, [r7, #4] 80064c6: 685b ldr r3, [r3, #4] 80064c8: 4619 mov r1, r3 80064ca: 4610 mov r0, r2 80064cc: f7ff fd3c bl 8005f48 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); } #else if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution)) 80064d0: f7ff fcf4 bl 8005ebc 80064d4: 4603 mov r3, r0 80064d6: f241 0203 movw r2, #4099 @ 0x1003 80064da: 4293 cmp r3, r2 80064dc: d914 bls.n 8006508 80064de: 687b ldr r3, [r7, #4] 80064e0: 689b ldr r3, [r3, #8] 80064e2: 2b10 cmp r3, #16 80064e4: d110 bne.n 8006508 { /* for STM32H7 silicon rev.B and above , ADC_CFGR_RES value for 8bits resolution is : b111 */ tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 80064e6: 687b ldr r3, [r7, #4] 80064e8: 7d5b ldrb r3, [r3, #21] 80064ea: 035a lsls r2, r3, #13 hadc->Init.Overrun | 80064ec: 687b ldr r3, [r7, #4] 80064ee: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 80064f0: 431a orrs r2, r3 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 80064f2: 687b ldr r3, [r7, #4] 80064f4: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 80064f6: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 80064f8: 687b ldr r3, [r7, #4] 80064fa: 7f1b ldrb r3, [r3, #28] 80064fc: 041b lsls r3, r3, #16 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 80064fe: 4313 orrs r3, r2 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006500: f043 030c orr.w r3, r3, #12 8006504: 61bb str r3, [r7, #24] 8006506: e00d b.n 8006524 } else { tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006508: 687b ldr r3, [r7, #4] 800650a: 7d5b ldrb r3, [r3, #21] 800650c: 035a lsls r2, r3, #13 hadc->Init.Overrun | 800650e: 687b ldr r3, [r7, #4] 8006510: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006512: 431a orrs r2, r3 hadc->Init.Resolution | 8006514: 687b ldr r3, [r7, #4] 8006516: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 8006518: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 800651a: 687b ldr r3, [r7, #4] 800651c: 7f1b ldrb r3, [r3, #28] 800651e: 041b lsls r3, r3, #16 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006520: 4313 orrs r3, r2 8006522: 61bb str r3, [r7, #24] } #endif /* ADC_VER_V5_3 */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8006524: 687b ldr r3, [r7, #4] 8006526: 7f1b ldrb r3, [r3, #28] 8006528: 2b01 cmp r3, #1 800652a: d106 bne.n 800653a { tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); 800652c: 687b ldr r3, [r7, #4] 800652e: 6a1b ldr r3, [r3, #32] 8006530: 3b01 subs r3, #1 8006532: 045b lsls r3, r3, #17 8006534: 69ba ldr r2, [r7, #24] 8006536: 4313 orrs r3, r2 8006538: 61bb str r3, [r7, #24] /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 800653a: 687b ldr r3, [r7, #4] 800653c: 6a5b ldr r3, [r3, #36] @ 0x24 800653e: 2b00 cmp r3, #0 8006540: d009 beq.n 8006556 { tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8006542: 687b ldr r3, [r7, #4] 8006544: 6a5b ldr r3, [r3, #36] @ 0x24 8006546: f403 7278 and.w r2, r3, #992 @ 0x3e0 | hadc->Init.ExternalTrigConvEdge 800654a: 687b ldr r3, [r7, #4] 800654c: 6a9b ldr r3, [r3, #40] @ 0x28 800654e: 4313 orrs r3, r2 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8006550: 69ba ldr r2, [r7, #24] 8006552: 4313 orrs r3, r2 8006554: 61bb str r3, [r7, #24] /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); } #else /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); 8006556: 687b ldr r3, [r7, #4] 8006558: 681b ldr r3, [r3, #0] 800655a: 68da ldr r2, [r3, #12] 800655c: 4b2c ldr r3, [pc, #176] @ (8006610 ) 800655e: 4013 ands r3, r2 8006560: 687a ldr r2, [r7, #4] 8006562: 6812 ldr r2, [r2, #0] 8006564: 69b9 ldr r1, [r7, #24] 8006566: 430b orrs r3, r1 8006568: 60d3 str r3, [r2, #12] /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - Conversion data management Init.ConversionDataManagement */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 800656a: 687b ldr r3, [r7, #4] 800656c: 681b ldr r3, [r3, #0] 800656e: 4618 mov r0, r3 8006570: f7ff fed2 bl 8006318 8006574: 6138 str r0, [r7, #16] tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 8006576: 687b ldr r3, [r7, #4] 8006578: 681b ldr r3, [r3, #0] 800657a: 4618 mov r0, r3 800657c: f7ff fedf bl 800633e 8006580: 60f8 str r0, [r7, #12] if ((tmp_adc_is_conversion_on_going_regular == 0UL) 8006582: 693b ldr r3, [r7, #16] 8006584: 2b00 cmp r3, #0 8006586: d15f bne.n 8006648 && (tmp_adc_is_conversion_on_going_injected == 0UL) 8006588: 68fb ldr r3, [r7, #12] 800658a: 2b00 cmp r3, #0 800658c: d15c bne.n 8006648 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); } #else tmpCFGR = ( ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 800658e: 687b ldr r3, [r7, #4] 8006590: 7d1b ldrb r3, [r3, #20] 8006592: 039a lsls r2, r3, #14 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); 8006594: 687b ldr r3, [r7, #4] 8006596: 6adb ldr r3, [r3, #44] @ 0x2c tmpCFGR = ( 8006598: 4313 orrs r3, r2 800659a: 61bb str r3, [r7, #24] #endif MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 800659c: 687b ldr r3, [r7, #4] 800659e: 681b ldr r3, [r3, #0] 80065a0: 68da ldr r2, [r3, #12] 80065a2: 4b1c ldr r3, [pc, #112] @ (8006614 ) 80065a4: 4013 ands r3, r2 80065a6: 687a ldr r2, [r7, #4] 80065a8: 6812 ldr r2, [r2, #0] 80065aa: 69b9 ldr r1, [r7, #24] 80065ac: 430b orrs r3, r1 80065ae: 60d3 str r3, [r2, #12] if (hadc->Init.OversamplingMode == ENABLE) 80065b0: 687b ldr r3, [r7, #4] 80065b2: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 80065b6: 2b01 cmp r3, #1 80065b8: d130 bne.n 800661c #endif assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START) 80065ba: 687b ldr r3, [r7, #4] 80065bc: 6a5b ldr r3, [r3, #36] @ 0x24 80065be: 2b00 cmp r3, #0 /* - Oversampling Ratio */ /* - Right bit shift */ /* - Left bit shift */ /* - Triggered mode */ /* - Oversampling mode (continued/resumed) */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, 80065c0: 687b ldr r3, [r7, #4] 80065c2: 681b ldr r3, [r3, #0] 80065c4: 691a ldr r2, [r3, #16] 80065c6: 4b14 ldr r3, [pc, #80] @ (8006618 ) 80065c8: 4013 ands r3, r2 80065ca: 687a ldr r2, [r7, #4] 80065cc: 6bd2 ldr r2, [r2, #60] @ 0x3c 80065ce: 3a01 subs r2, #1 80065d0: 0411 lsls r1, r2, #16 80065d2: 687a ldr r2, [r7, #4] 80065d4: 6c12 ldr r2, [r2, #64] @ 0x40 80065d6: 4311 orrs r1, r2 80065d8: 687a ldr r2, [r7, #4] 80065da: 6c52 ldr r2, [r2, #68] @ 0x44 80065dc: 4311 orrs r1, r2 80065de: 687a ldr r2, [r7, #4] 80065e0: 6c92 ldr r2, [r2, #72] @ 0x48 80065e2: 430a orrs r2, r1 80065e4: 431a orrs r2, r3 80065e6: 687b ldr r3, [r7, #4] 80065e8: 681b ldr r3, [r3, #0] 80065ea: f042 0201 orr.w r2, r2, #1 80065ee: 611a str r2, [r3, #16] 80065f0: e01c b.n 800662c 80065f2: bf00 nop 80065f4: 24000034 .word 0x24000034 80065f8: 053e2d63 .word 0x053e2d63 80065fc: 40022000 .word 0x40022000 8006600: 40022100 .word 0x40022100 8006604: 58026000 .word 0x58026000 8006608: 40022300 .word 0x40022300 800660c: 58026300 .word 0x58026300 8006610: fff0c003 .word 0xfff0c003 8006614: ffffbffc .word 0xffffbffc 8006618: fc00f81e .word 0xfc00f81e } else { /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); 800661c: 687b ldr r3, [r7, #4] 800661e: 681b ldr r3, [r3, #0] 8006620: 691a ldr r2, [r3, #16] 8006622: 687b ldr r3, [r7, #4] 8006624: 681b ldr r3, [r3, #0] 8006626: f022 0201 bic.w r2, r2, #1 800662a: 611a str r2, [r3, #16] } /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift); 800662c: 687b ldr r3, [r7, #4] 800662e: 681b ldr r3, [r3, #0] 8006630: 691b ldr r3, [r3, #16] 8006632: f023 4170 bic.w r1, r3, #4026531840 @ 0xf0000000 8006636: 687b ldr r3, [r7, #4] 8006638: 6b5a ldr r2, [r3, #52] @ 0x34 800663a: 687b ldr r3, [r7, #4] 800663c: 681b ldr r3, [r3, #0] 800663e: 430a orrs r2, r1 8006640: 611a str r2, [r3, #16] /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); } #else /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); 8006642: 6878 ldr r0, [r7, #4] 8006644: f000 fde2 bl 800720c /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 8006648: 687b ldr r3, [r7, #4] 800664a: 68db ldr r3, [r3, #12] 800664c: 2b01 cmp r3, #1 800664e: d10c bne.n 800666a { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); 8006650: 687b ldr r3, [r7, #4] 8006652: 681b ldr r3, [r3, #0] 8006654: 6b1b ldr r3, [r3, #48] @ 0x30 8006656: f023 010f bic.w r1, r3, #15 800665a: 687b ldr r3, [r7, #4] 800665c: 699b ldr r3, [r3, #24] 800665e: 1e5a subs r2, r3, #1 8006660: 687b ldr r3, [r7, #4] 8006662: 681b ldr r3, [r3, #0] 8006664: 430a orrs r2, r1 8006666: 631a str r2, [r3, #48] @ 0x30 8006668: e007 b.n 800667a } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 800666a: 687b ldr r3, [r7, #4] 800666c: 681b ldr r3, [r3, #0] 800666e: 6b1a ldr r2, [r3, #48] @ 0x30 8006670: 687b ldr r3, [r7, #4] 8006672: 681b ldr r3, [r3, #0] 8006674: f022 020f bic.w r2, r2, #15 8006678: 631a str r2, [r3, #48] @ 0x30 } /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); 800667a: 687b ldr r3, [r7, #4] 800667c: 6d5b ldr r3, [r3, #84] @ 0x54 800667e: f023 0303 bic.w r3, r3, #3 8006682: f043 0201 orr.w r2, r3, #1 8006686: 687b ldr r3, [r7, #4] 8006688: 655a str r2, [r3, #84] @ 0x54 800668a: e007 b.n 800669c } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800668c: 687b ldr r3, [r7, #4] 800668e: 6d5b ldr r3, [r3, #84] @ 0x54 8006690: f043 0210 orr.w r2, r3, #16 8006694: 687b ldr r3, [r7, #4] 8006696: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8006698: 2301 movs r3, #1 800669a: 77fb strb r3, [r7, #31] } /* Return function status */ return tmp_hal_status; 800669c: 7ffb ldrb r3, [r7, #31] } 800669e: 4618 mov r0, r3 80066a0: 3724 adds r7, #36 @ 0x24 80066a2: 46bd mov sp, r7 80066a4: bd90 pop {r4, r7, pc} 80066a6: bf00 nop 080066a8 : * @param pData Destination Buffer address. * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { 80066a8: b580 push {r7, lr} 80066aa: b086 sub sp, #24 80066ac: af00 add r7, sp, #0 80066ae: 60f8 str r0, [r7, #12] 80066b0: 60b9 str r1, [r7, #8] 80066b2: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 80066b4: 68fb ldr r3, [r7, #12] 80066b6: 681b ldr r3, [r3, #0] 80066b8: 4a55 ldr r2, [pc, #340] @ (8006810 ) 80066ba: 4293 cmp r3, r2 80066bc: d004 beq.n 80066c8 80066be: 68fb ldr r3, [r7, #12] 80066c0: 681b ldr r3, [r3, #0] 80066c2: 4a54 ldr r2, [pc, #336] @ (8006814 ) 80066c4: 4293 cmp r3, r2 80066c6: d101 bne.n 80066cc 80066c8: 4b53 ldr r3, [pc, #332] @ (8006818 ) 80066ca: e000 b.n 80066ce 80066cc: 4b53 ldr r3, [pc, #332] @ (800681c ) 80066ce: 4618 mov r0, r3 80066d0: f7ff fd64 bl 800619c 80066d4: 6138 str r0, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 80066d6: 68fb ldr r3, [r7, #12] 80066d8: 681b ldr r3, [r3, #0] 80066da: 4618 mov r0, r3 80066dc: f7ff fe1c bl 8006318 80066e0: 4603 mov r3, r0 80066e2: 2b00 cmp r3, #0 80066e4: f040 808c bne.w 8006800 { /* Process locked */ __HAL_LOCK(hadc); 80066e8: 68fb ldr r3, [r7, #12] 80066ea: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 80066ee: 2b01 cmp r3, #1 80066f0: d101 bne.n 80066f6 80066f2: 2302 movs r3, #2 80066f4: e087 b.n 8006806 80066f6: 68fb ldr r3, [r7, #12] 80066f8: 2201 movs r2, #1 80066fa: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Ensure that multimode regular conversions are not enabled. */ /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 80066fe: 693b ldr r3, [r7, #16] 8006700: 2b00 cmp r3, #0 8006702: d005 beq.n 8006710 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) 8006704: 693b ldr r3, [r7, #16] 8006706: 2b05 cmp r3, #5 8006708: d002 beq.n 8006710 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) 800670a: 693b ldr r3, [r7, #16] 800670c: 2b09 cmp r3, #9 800670e: d170 bne.n 80067f2 ) { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8006710: 68f8 ldr r0, [r7, #12] 8006712: f000 fbfd bl 8006f10 8006716: 4603 mov r3, r0 8006718: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800671a: 7dfb ldrb r3, [r7, #23] 800671c: 2b00 cmp r3, #0 800671e: d163 bne.n 80067e8 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8006720: 68fb ldr r3, [r7, #12] 8006722: 6d5a ldr r2, [r3, #84] @ 0x54 8006724: 4b3e ldr r3, [pc, #248] @ (8006820 ) 8006726: 4013 ands r3, r2 8006728: f443 7280 orr.w r2, r3, #256 @ 0x100 800672c: 68fb ldr r3, [r7, #12] 800672e: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_REG_BUSY); /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8006730: 68fb ldr r3, [r7, #12] 8006732: 681b ldr r3, [r3, #0] 8006734: 4a37 ldr r2, [pc, #220] @ (8006814 ) 8006736: 4293 cmp r3, r2 8006738: d002 beq.n 8006740 800673a: 68fb ldr r3, [r7, #12] 800673c: 681b ldr r3, [r3, #0] 800673e: e000 b.n 8006742 8006740: 4b33 ldr r3, [pc, #204] @ (8006810 ) 8006742: 68fa ldr r2, [r7, #12] 8006744: 6812 ldr r2, [r2, #0] 8006746: 4293 cmp r3, r2 8006748: d002 beq.n 8006750 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 800674a: 693b ldr r3, [r7, #16] 800674c: 2b00 cmp r3, #0 800674e: d105 bne.n 800675c ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8006750: 68fb ldr r3, [r7, #12] 8006752: 6d5b ldr r3, [r3, #84] @ 0x54 8006754: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 8006758: 68fb ldr r3, [r7, #12] 800675a: 655a str r2, [r3, #84] @ 0x54 } /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) 800675c: 68fb ldr r3, [r7, #12] 800675e: 6d5b ldr r3, [r3, #84] @ 0x54 8006760: f403 5380 and.w r3, r3, #4096 @ 0x1000 8006764: 2b00 cmp r3, #0 8006766: d006 beq.n 8006776 { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8006768: 68fb ldr r3, [r7, #12] 800676a: 6d9b ldr r3, [r3, #88] @ 0x58 800676c: f023 0206 bic.w r2, r3, #6 8006770: 68fb ldr r3, [r7, #12] 8006772: 659a str r2, [r3, #88] @ 0x58 8006774: e002 b.n 800677c } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8006776: 68fb ldr r3, [r7, #12] 8006778: 2200 movs r2, #0 800677a: 659a str r2, [r3, #88] @ 0x58 } /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 800677c: 68fb ldr r3, [r7, #12] 800677e: 6cdb ldr r3, [r3, #76] @ 0x4c 8006780: 4a28 ldr r2, [pc, #160] @ (8006824 ) 8006782: 63da str r2, [r3, #60] @ 0x3c /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 8006784: 68fb ldr r3, [r7, #12] 8006786: 6cdb ldr r3, [r3, #76] @ 0x4c 8006788: 4a27 ldr r2, [pc, #156] @ (8006828 ) 800678a: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 800678c: 68fb ldr r3, [r7, #12] 800678e: 6cdb ldr r3, [r3, #76] @ 0x4c 8006790: 4a26 ldr r2, [pc, #152] @ (800682c ) 8006792: 64da str r2, [r3, #76] @ 0x4c /* ADC start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 8006794: 68fb ldr r3, [r7, #12] 8006796: 681b ldr r3, [r3, #0] 8006798: 221c movs r2, #28 800679a: 601a str r2, [r3, #0] /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 800679c: 68fb ldr r3, [r7, #12] 800679e: 2200 movs r2, #0 80067a0: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* With DMA, overrun event is always considered as an error even if hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, ADC_IT_OVR is enabled. */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 80067a4: 68fb ldr r3, [r7, #12] 80067a6: 681b ldr r3, [r3, #0] 80067a8: 685a ldr r2, [r3, #4] 80067aa: 68fb ldr r3, [r7, #12] 80067ac: 681b ldr r3, [r3, #0] 80067ae: f042 0210 orr.w r2, r2, #16 80067b2: 605a str r2, [r3, #4] { LL_ADC_REG_SetDataTransferMode(hadc->Instance, ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); } #else LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement); 80067b4: 68fb ldr r3, [r7, #12] 80067b6: 681a ldr r2, [r3, #0] 80067b8: 68fb ldr r3, [r7, #12] 80067ba: 6adb ldr r3, [r3, #44] @ 0x2c 80067bc: 4619 mov r1, r3 80067be: 4610 mov r0, r2 80067c0: f7ff fc89 bl 80060d6 #endif /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 80067c4: 68fb ldr r3, [r7, #12] 80067c6: 6cd8 ldr r0, [r3, #76] @ 0x4c 80067c8: 68fb ldr r3, [r7, #12] 80067ca: 681b ldr r3, [r3, #0] 80067cc: 3340 adds r3, #64 @ 0x40 80067ce: 4619 mov r1, r3 80067d0: 68ba ldr r2, [r7, #8] 80067d2: 687b ldr r3, [r7, #4] 80067d4: f002 fa5e bl 8008c94 80067d8: 4603 mov r3, r0 80067da: 75fb strb r3, [r7, #23] /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); 80067dc: 68fb ldr r3, [r7, #12] 80067de: 681b ldr r3, [r3, #0] 80067e0: 4618 mov r0, r3 80067e2: f7ff fd85 bl 80062f0 if (tmp_hal_status == HAL_OK) 80067e6: e00d b.n 8006804 } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 80067e8: 68fb ldr r3, [r7, #12] 80067ea: 2200 movs r2, #0 80067ec: f883 2050 strb.w r2, [r3, #80] @ 0x50 if (tmp_hal_status == HAL_OK) 80067f0: e008 b.n 8006804 } } else { tmp_hal_status = HAL_ERROR; 80067f2: 2301 movs r3, #1 80067f4: 75fb strb r3, [r7, #23] /* Process unlocked */ __HAL_UNLOCK(hadc); 80067f6: 68fb ldr r3, [r7, #12] 80067f8: 2200 movs r2, #0 80067fa: f883 2050 strb.w r2, [r3, #80] @ 0x50 80067fe: e001 b.n 8006804 } } else { tmp_hal_status = HAL_BUSY; 8006800: 2302 movs r3, #2 8006802: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 8006804: 7dfb ldrb r3, [r7, #23] } 8006806: 4618 mov r0, r3 8006808: 3718 adds r7, #24 800680a: 46bd mov sp, r7 800680c: bd80 pop {r7, pc} 800680e: bf00 nop 8006810: 40022000 .word 0x40022000 8006814: 40022100 .word 0x40022100 8006818: 40022300 .word 0x40022300 800681c: 58026300 .word 0x58026300 8006820: fffff0fe .word 0xfffff0fe 8006824: 080070e3 .word 0x080070e3 8006828: 080071bb .word 0x080071bb 800682c: 080071d7 .word 0x080071d7 08006830 : * @brief Conversion DMA half-transfer callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { 8006830: b480 push {r7} 8006832: b083 sub sp, #12 8006834: af00 add r7, sp, #0 8006836: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 8006838: bf00 nop 800683a: 370c adds r7, #12 800683c: 46bd mov sp, r7 800683e: f85d 7b04 ldr.w r7, [sp], #4 8006842: 4770 bx lr 08006844 : * (this function is also clearing overrun flag) * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 8006844: b480 push {r7} 8006846: b083 sub sp, #12 8006848: af00 add r7, sp, #0 800684a: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 800684c: bf00 nop 800684e: 370c adds r7, #12 8006850: 46bd mov sp, r7 8006852: f85d 7b04 ldr.w r7, [sp], #4 8006856: 4770 bx lr 08006858 : * @param hadc ADC handle * @param sConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { 8006858: b590 push {r4, r7, lr} 800685a: b0a1 sub sp, #132 @ 0x84 800685c: af00 add r7, sp, #0 800685e: 6078 str r0, [r7, #4] 8006860: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8006862: 2300 movs r3, #0 8006864: f887 307f strb.w r3, [r7, #127] @ 0x7f uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0; 8006868: 2300 movs r3, #0 800686a: 60bb str r3, [r7, #8] /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); /* Verification of channel number */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) 800686c: 683b ldr r3, [r7, #0] 800686e: 68db ldr r3, [r3, #12] 8006870: 4a65 ldr r2, [pc, #404] @ (8006a08 ) 8006872: 4293 cmp r3, r2 } #endif } /* Process locked */ __HAL_LOCK(hadc); 8006874: 687b ldr r3, [r7, #4] 8006876: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 800687a: 2b01 cmp r3, #1 800687c: d101 bne.n 8006882 800687e: 2302 movs r3, #2 8006880: e32e b.n 8006ee0 8006882: 687b ldr r3, [r7, #4] 8006884: 2201 movs r2, #1 8006886: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 800688a: 687b ldr r3, [r7, #4] 800688c: 681b ldr r3, [r3, #0] 800688e: 4618 mov r0, r3 8006890: f7ff fd42 bl 8006318 8006894: 4603 mov r3, r0 8006896: 2b00 cmp r3, #0 8006898: f040 8313 bne.w 8006ec2 { if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))) 800689c: 683b ldr r3, [r7, #0] 800689e: 681b ldr r3, [r3, #0] 80068a0: 2b00 cmp r3, #0 80068a2: db2c blt.n 80068fe /* ADC channels preselection */ hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); } #else /* ADC channels preselection */ hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); 80068a4: 683b ldr r3, [r7, #0] 80068a6: 681b ldr r3, [r3, #0] 80068a8: f3c3 0313 ubfx r3, r3, #0, #20 80068ac: 2b00 cmp r3, #0 80068ae: d108 bne.n 80068c2 80068b0: 683b ldr r3, [r7, #0] 80068b2: 681b ldr r3, [r3, #0] 80068b4: 0e9b lsrs r3, r3, #26 80068b6: f003 031f and.w r3, r3, #31 80068ba: 2201 movs r2, #1 80068bc: fa02 f303 lsl.w r3, r2, r3 80068c0: e016 b.n 80068f0 80068c2: 683b ldr r3, [r7, #0] 80068c4: 681b ldr r3, [r3, #0] 80068c6: 667b str r3, [r7, #100] @ 0x64 uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80068c8: 6e7b ldr r3, [r7, #100] @ 0x64 80068ca: fa93 f3a3 rbit r3, r3 80068ce: 663b str r3, [r7, #96] @ 0x60 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 80068d0: 6e3b ldr r3, [r7, #96] @ 0x60 80068d2: 66bb str r3, [r7, #104] @ 0x68 optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 80068d4: 6ebb ldr r3, [r7, #104] @ 0x68 80068d6: 2b00 cmp r3, #0 80068d8: d101 bne.n 80068de { return 32U; 80068da: 2320 movs r3, #32 80068dc: e003 b.n 80068e6 } return __builtin_clz(value); 80068de: 6ebb ldr r3, [r7, #104] @ 0x68 80068e0: fab3 f383 clz r3, r3 80068e4: b2db uxtb r3, r3 80068e6: f003 031f and.w r3, r3, #31 80068ea: 2201 movs r2, #1 80068ec: fa02 f303 lsl.w r3, r2, r3 80068f0: 687a ldr r2, [r7, #4] 80068f2: 6812 ldr r2, [r2, #0] 80068f4: 69d1 ldr r1, [r2, #28] 80068f6: 687a ldr r2, [r7, #4] 80068f8: 6812 ldr r2, [r2, #0] 80068fa: 430b orrs r3, r1 80068fc: 61d3 str r3, [r2, #28] #endif /* ADC_VER_V5_V90 */ } /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); 80068fe: 687b ldr r3, [r7, #4] 8006900: 6818 ldr r0, [r3, #0] 8006902: 683b ldr r3, [r7, #0] 8006904: 6859 ldr r1, [r3, #4] 8006906: 683b ldr r3, [r7, #0] 8006908: 681b ldr r3, [r3, #0] 800690a: 461a mov r2, r3 800690c: f7ff fbb7 bl 800607e /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8006910: 687b ldr r3, [r7, #4] 8006912: 681b ldr r3, [r3, #0] 8006914: 4618 mov r0, r3 8006916: f7ff fcff bl 8006318 800691a: 67b8 str r0, [r7, #120] @ 0x78 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 800691c: 687b ldr r3, [r7, #4] 800691e: 681b ldr r3, [r3, #0] 8006920: 4618 mov r0, r3 8006922: f7ff fd0c bl 800633e 8006926: 6778 str r0, [r7, #116] @ 0x74 if ((tmp_adc_is_conversion_on_going_regular == 0UL) 8006928: 6fbb ldr r3, [r7, #120] @ 0x78 800692a: 2b00 cmp r3, #0 800692c: f040 80b8 bne.w 8006aa0 && (tmp_adc_is_conversion_on_going_injected == 0UL) 8006930: 6f7b ldr r3, [r7, #116] @ 0x74 8006932: 2b00 cmp r3, #0 8006934: f040 80b4 bne.w 8006aa0 ) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); 8006938: 687b ldr r3, [r7, #4] 800693a: 6818 ldr r0, [r3, #0] 800693c: 683b ldr r3, [r7, #0] 800693e: 6819 ldr r1, [r3, #0] 8006940: 683b ldr r3, [r7, #0] 8006942: 689b ldr r3, [r3, #8] 8006944: 461a mov r2, r3 8006946: f7ff fbd9 bl 80060fc tmpOffsetShifted = ADC3_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); } else #endif /* ADC_VER_V5_V90 */ { tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); 800694a: 4b30 ldr r3, [pc, #192] @ (8006a0c ) 800694c: 681b ldr r3, [r3, #0] 800694e: f003 4370 and.w r3, r3, #4026531840 @ 0xf0000000 8006952: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8006956: d10b bne.n 8006970 8006958: 683b ldr r3, [r7, #0] 800695a: 695a ldr r2, [r3, #20] 800695c: 687b ldr r3, [r7, #4] 800695e: 681b ldr r3, [r3, #0] 8006960: 68db ldr r3, [r3, #12] 8006962: 089b lsrs r3, r3, #2 8006964: f003 0307 and.w r3, r3, #7 8006968: 005b lsls r3, r3, #1 800696a: fa02 f303 lsl.w r3, r2, r3 800696e: e01d b.n 80069ac 8006970: 687b ldr r3, [r7, #4] 8006972: 681b ldr r3, [r3, #0] 8006974: 68db ldr r3, [r3, #12] 8006976: f003 0310 and.w r3, r3, #16 800697a: 2b00 cmp r3, #0 800697c: d10b bne.n 8006996 800697e: 683b ldr r3, [r7, #0] 8006980: 695a ldr r2, [r3, #20] 8006982: 687b ldr r3, [r7, #4] 8006984: 681b ldr r3, [r3, #0] 8006986: 68db ldr r3, [r3, #12] 8006988: 089b lsrs r3, r3, #2 800698a: f003 0307 and.w r3, r3, #7 800698e: 005b lsls r3, r3, #1 8006990: fa02 f303 lsl.w r3, r2, r3 8006994: e00a b.n 80069ac 8006996: 683b ldr r3, [r7, #0] 8006998: 695a ldr r2, [r3, #20] 800699a: 687b ldr r3, [r7, #4] 800699c: 681b ldr r3, [r3, #0] 800699e: 68db ldr r3, [r3, #12] 80069a0: 089b lsrs r3, r3, #2 80069a2: f003 0304 and.w r3, r3, #4 80069a6: 005b lsls r3, r3, #1 80069a8: fa02 f303 lsl.w r3, r2, r3 80069ac: 673b str r3, [r7, #112] @ 0x70 } if (sConfig->OffsetNumber != ADC_OFFSET_NONE) 80069ae: 683b ldr r3, [r7, #0] 80069b0: 691b ldr r3, [r3, #16] 80069b2: 2b04 cmp r3, #4 80069b4: d02c beq.n 8006a10 { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); 80069b6: 687b ldr r3, [r7, #4] 80069b8: 6818 ldr r0, [r3, #0] 80069ba: 683b ldr r3, [r7, #0] 80069bc: 6919 ldr r1, [r3, #16] 80069be: 683b ldr r3, [r7, #0] 80069c0: 681a ldr r2, [r3, #0] 80069c2: 6f3b ldr r3, [r7, #112] @ 0x70 80069c4: f7ff faf4 bl 8005fb0 else #endif /* ADC_VER_V5_V90 */ { assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation)); /* Set ADC selected offset signed saturation */ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); 80069c8: 687b ldr r3, [r7, #4] 80069ca: 6818 ldr r0, [r3, #0] 80069cc: 683b ldr r3, [r7, #0] 80069ce: 6919 ldr r1, [r3, #16] 80069d0: 683b ldr r3, [r7, #0] 80069d2: 7e5b ldrb r3, [r3, #25] 80069d4: 2b01 cmp r3, #1 80069d6: d102 bne.n 80069de 80069d8: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 80069dc: e000 b.n 80069e0 80069de: 2300 movs r3, #0 80069e0: 461a mov r2, r3 80069e2: f7ff fb1e bl 8006022 assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift)); /* Set ADC selected offset right shift */ LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); 80069e6: 687b ldr r3, [r7, #4] 80069e8: 6818 ldr r0, [r3, #0] 80069ea: 683b ldr r3, [r7, #0] 80069ec: 6919 ldr r1, [r3, #16] 80069ee: 683b ldr r3, [r7, #0] 80069f0: 7e1b ldrb r3, [r3, #24] 80069f2: 2b01 cmp r3, #1 80069f4: d102 bne.n 80069fc 80069f6: f44f 6300 mov.w r3, #2048 @ 0x800 80069fa: e000 b.n 80069fe 80069fc: 2300 movs r3, #0 80069fe: 461a mov r2, r3 8006a00: f7ff faf6 bl 8005ff0 8006a04: e04c b.n 8006aa0 8006a06: bf00 nop 8006a08: 47ff0000 .word 0x47ff0000 8006a0c: 5c001000 .word 0x5c001000 } } else #endif /* ADC_VER_V5_V90 */ { if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8006a10: 687b ldr r3, [r7, #4] 8006a12: 681b ldr r3, [r3, #0] 8006a14: 6e1b ldr r3, [r3, #96] @ 0x60 8006a16: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006a1a: 683b ldr r3, [r7, #0] 8006a1c: 681b ldr r3, [r3, #0] 8006a1e: 069b lsls r3, r3, #26 8006a20: 429a cmp r2, r3 8006a22: d107 bne.n 8006a34 { CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE); 8006a24: 687b ldr r3, [r7, #4] 8006a26: 681b ldr r3, [r3, #0] 8006a28: 6e1a ldr r2, [r3, #96] @ 0x60 8006a2a: 687b ldr r3, [r7, #4] 8006a2c: 681b ldr r3, [r3, #0] 8006a2e: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8006a32: 661a str r2, [r3, #96] @ 0x60 } if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8006a34: 687b ldr r3, [r7, #4] 8006a36: 681b ldr r3, [r3, #0] 8006a38: 6e5b ldr r3, [r3, #100] @ 0x64 8006a3a: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006a3e: 683b ldr r3, [r7, #0] 8006a40: 681b ldr r3, [r3, #0] 8006a42: 069b lsls r3, r3, #26 8006a44: 429a cmp r2, r3 8006a46: d107 bne.n 8006a58 { CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE); 8006a48: 687b ldr r3, [r7, #4] 8006a4a: 681b ldr r3, [r3, #0] 8006a4c: 6e5a ldr r2, [r3, #100] @ 0x64 8006a4e: 687b ldr r3, [r7, #4] 8006a50: 681b ldr r3, [r3, #0] 8006a52: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8006a56: 665a str r2, [r3, #100] @ 0x64 } if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8006a58: 687b ldr r3, [r7, #4] 8006a5a: 681b ldr r3, [r3, #0] 8006a5c: 6e9b ldr r3, [r3, #104] @ 0x68 8006a5e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006a62: 683b ldr r3, [r7, #0] 8006a64: 681b ldr r3, [r3, #0] 8006a66: 069b lsls r3, r3, #26 8006a68: 429a cmp r2, r3 8006a6a: d107 bne.n 8006a7c { CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE); 8006a6c: 687b ldr r3, [r7, #4] 8006a6e: 681b ldr r3, [r3, #0] 8006a70: 6e9a ldr r2, [r3, #104] @ 0x68 8006a72: 687b ldr r3, [r7, #4] 8006a74: 681b ldr r3, [r3, #0] 8006a76: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8006a7a: 669a str r2, [r3, #104] @ 0x68 } if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8006a7c: 687b ldr r3, [r7, #4] 8006a7e: 681b ldr r3, [r3, #0] 8006a80: 6edb ldr r3, [r3, #108] @ 0x6c 8006a82: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006a86: 683b ldr r3, [r7, #0] 8006a88: 681b ldr r3, [r3, #0] 8006a8a: 069b lsls r3, r3, #26 8006a8c: 429a cmp r2, r3 8006a8e: d107 bne.n 8006aa0 { CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE); 8006a90: 687b ldr r3, [r7, #4] 8006a92: 681b ldr r3, [r3, #0] 8006a94: 6eda ldr r2, [r3, #108] @ 0x6c 8006a96: 687b ldr r3, [r7, #4] 8006a98: 681b ldr r3, [r3, #0] 8006a9a: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8006a9e: 66da str r2, [r3, #108] @ 0x6c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8006aa0: 687b ldr r3, [r7, #4] 8006aa2: 681b ldr r3, [r3, #0] 8006aa4: 4618 mov r0, r3 8006aa6: f7ff fbfd bl 80062a4 8006aaa: 4603 mov r3, r0 8006aac: 2b00 cmp r3, #0 8006aae: f040 8211 bne.w 8006ed4 { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); 8006ab2: 687b ldr r3, [r7, #4] 8006ab4: 6818 ldr r0, [r3, #0] 8006ab6: 683b ldr r3, [r7, #0] 8006ab8: 6819 ldr r1, [r3, #0] 8006aba: 683b ldr r3, [r7, #0] 8006abc: 68db ldr r3, [r3, #12] 8006abe: 461a mov r2, r3 8006ac0: f7ff fb48 bl 8006154 /* Configuration of differential mode */ if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) 8006ac4: 683b ldr r3, [r7, #0] 8006ac6: 68db ldr r3, [r3, #12] 8006ac8: 4aa1 ldr r2, [pc, #644] @ (8006d50 ) 8006aca: 4293 cmp r3, r2 8006acc: f040 812e bne.w 8006d2c { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006ad0: 687b ldr r3, [r7, #4] 8006ad2: 6818 ldr r0, [r3, #0] (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8006ad4: 683b ldr r3, [r7, #0] 8006ad6: 681b ldr r3, [r3, #0] 8006ad8: f3c3 0313 ubfx r3, r3, #0, #20 8006adc: 2b00 cmp r3, #0 8006ade: d10b bne.n 8006af8 8006ae0: 683b ldr r3, [r7, #0] 8006ae2: 681b ldr r3, [r3, #0] 8006ae4: 0e9b lsrs r3, r3, #26 8006ae6: 3301 adds r3, #1 8006ae8: f003 031f and.w r3, r3, #31 8006aec: 2b09 cmp r3, #9 8006aee: bf94 ite ls 8006af0: 2301 movls r3, #1 8006af2: 2300 movhi r3, #0 8006af4: b2db uxtb r3, r3 8006af6: e019 b.n 8006b2c 8006af8: 683b ldr r3, [r7, #0] 8006afa: 681b ldr r3, [r3, #0] 8006afc: 65bb str r3, [r7, #88] @ 0x58 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006afe: 6dbb ldr r3, [r7, #88] @ 0x58 8006b00: fa93 f3a3 rbit r3, r3 8006b04: 657b str r3, [r7, #84] @ 0x54 return result; 8006b06: 6d7b ldr r3, [r7, #84] @ 0x54 8006b08: 65fb str r3, [r7, #92] @ 0x5c if (value == 0U) 8006b0a: 6dfb ldr r3, [r7, #92] @ 0x5c 8006b0c: 2b00 cmp r3, #0 8006b0e: d101 bne.n 8006b14 return 32U; 8006b10: 2320 movs r3, #32 8006b12: e003 b.n 8006b1c return __builtin_clz(value); 8006b14: 6dfb ldr r3, [r7, #92] @ 0x5c 8006b16: fab3 f383 clz r3, r3 8006b1a: b2db uxtb r3, r3 8006b1c: 3301 adds r3, #1 8006b1e: f003 031f and.w r3, r3, #31 8006b22: 2b09 cmp r3, #9 8006b24: bf94 ite ls 8006b26: 2301 movls r3, #1 8006b28: 2300 movhi r3, #0 8006b2a: b2db uxtb r3, r3 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006b2c: 2b00 cmp r3, #0 8006b2e: d079 beq.n 8006c24 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8006b30: 683b ldr r3, [r7, #0] 8006b32: 681b ldr r3, [r3, #0] 8006b34: f3c3 0313 ubfx r3, r3, #0, #20 8006b38: 2b00 cmp r3, #0 8006b3a: d107 bne.n 8006b4c 8006b3c: 683b ldr r3, [r7, #0] 8006b3e: 681b ldr r3, [r3, #0] 8006b40: 0e9b lsrs r3, r3, #26 8006b42: 3301 adds r3, #1 8006b44: 069b lsls r3, r3, #26 8006b46: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006b4a: e015 b.n 8006b78 8006b4c: 683b ldr r3, [r7, #0] 8006b4e: 681b ldr r3, [r3, #0] 8006b50: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006b52: 6cfb ldr r3, [r7, #76] @ 0x4c 8006b54: fa93 f3a3 rbit r3, r3 8006b58: 64bb str r3, [r7, #72] @ 0x48 return result; 8006b5a: 6cbb ldr r3, [r7, #72] @ 0x48 8006b5c: 653b str r3, [r7, #80] @ 0x50 if (value == 0U) 8006b5e: 6d3b ldr r3, [r7, #80] @ 0x50 8006b60: 2b00 cmp r3, #0 8006b62: d101 bne.n 8006b68 return 32U; 8006b64: 2320 movs r3, #32 8006b66: e003 b.n 8006b70 return __builtin_clz(value); 8006b68: 6d3b ldr r3, [r7, #80] @ 0x50 8006b6a: fab3 f383 clz r3, r3 8006b6e: b2db uxtb r3, r3 8006b70: 3301 adds r3, #1 8006b72: 069b lsls r3, r3, #26 8006b74: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006b78: 683b ldr r3, [r7, #0] 8006b7a: 681b ldr r3, [r3, #0] 8006b7c: f3c3 0313 ubfx r3, r3, #0, #20 8006b80: 2b00 cmp r3, #0 8006b82: d109 bne.n 8006b98 8006b84: 683b ldr r3, [r7, #0] 8006b86: 681b ldr r3, [r3, #0] 8006b88: 0e9b lsrs r3, r3, #26 8006b8a: 3301 adds r3, #1 8006b8c: f003 031f and.w r3, r3, #31 8006b90: 2101 movs r1, #1 8006b92: fa01 f303 lsl.w r3, r1, r3 8006b96: e017 b.n 8006bc8 8006b98: 683b ldr r3, [r7, #0] 8006b9a: 681b ldr r3, [r3, #0] 8006b9c: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006b9e: 6c3b ldr r3, [r7, #64] @ 0x40 8006ba0: fa93 f3a3 rbit r3, r3 8006ba4: 63fb str r3, [r7, #60] @ 0x3c return result; 8006ba6: 6bfb ldr r3, [r7, #60] @ 0x3c 8006ba8: 647b str r3, [r7, #68] @ 0x44 if (value == 0U) 8006baa: 6c7b ldr r3, [r7, #68] @ 0x44 8006bac: 2b00 cmp r3, #0 8006bae: d101 bne.n 8006bb4 return 32U; 8006bb0: 2320 movs r3, #32 8006bb2: e003 b.n 8006bbc return __builtin_clz(value); 8006bb4: 6c7b ldr r3, [r7, #68] @ 0x44 8006bb6: fab3 f383 clz r3, r3 8006bba: b2db uxtb r3, r3 8006bbc: 3301 adds r3, #1 8006bbe: f003 031f and.w r3, r3, #31 8006bc2: 2101 movs r1, #1 8006bc4: fa01 f303 lsl.w r3, r1, r3 8006bc8: ea42 0103 orr.w r1, r2, r3 8006bcc: 683b ldr r3, [r7, #0] 8006bce: 681b ldr r3, [r3, #0] 8006bd0: f3c3 0313 ubfx r3, r3, #0, #20 8006bd4: 2b00 cmp r3, #0 8006bd6: d10a bne.n 8006bee 8006bd8: 683b ldr r3, [r7, #0] 8006bda: 681b ldr r3, [r3, #0] 8006bdc: 0e9b lsrs r3, r3, #26 8006bde: 3301 adds r3, #1 8006be0: f003 021f and.w r2, r3, #31 8006be4: 4613 mov r3, r2 8006be6: 005b lsls r3, r3, #1 8006be8: 4413 add r3, r2 8006bea: 051b lsls r3, r3, #20 8006bec: e018 b.n 8006c20 8006bee: 683b ldr r3, [r7, #0] 8006bf0: 681b ldr r3, [r3, #0] 8006bf2: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006bf4: 6b7b ldr r3, [r7, #52] @ 0x34 8006bf6: fa93 f3a3 rbit r3, r3 8006bfa: 633b str r3, [r7, #48] @ 0x30 return result; 8006bfc: 6b3b ldr r3, [r7, #48] @ 0x30 8006bfe: 63bb str r3, [r7, #56] @ 0x38 if (value == 0U) 8006c00: 6bbb ldr r3, [r7, #56] @ 0x38 8006c02: 2b00 cmp r3, #0 8006c04: d101 bne.n 8006c0a return 32U; 8006c06: 2320 movs r3, #32 8006c08: e003 b.n 8006c12 return __builtin_clz(value); 8006c0a: 6bbb ldr r3, [r7, #56] @ 0x38 8006c0c: fab3 f383 clz r3, r3 8006c10: b2db uxtb r3, r3 8006c12: 3301 adds r3, #1 8006c14: f003 021f and.w r2, r3, #31 8006c18: 4613 mov r3, r2 8006c1a: 005b lsls r3, r3, #1 8006c1c: 4413 add r3, r2 8006c1e: 051b lsls r3, r3, #20 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006c20: 430b orrs r3, r1 8006c22: e07e b.n 8006d22 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8006c24: 683b ldr r3, [r7, #0] 8006c26: 681b ldr r3, [r3, #0] 8006c28: f3c3 0313 ubfx r3, r3, #0, #20 8006c2c: 2b00 cmp r3, #0 8006c2e: d107 bne.n 8006c40 8006c30: 683b ldr r3, [r7, #0] 8006c32: 681b ldr r3, [r3, #0] 8006c34: 0e9b lsrs r3, r3, #26 8006c36: 3301 adds r3, #1 8006c38: 069b lsls r3, r3, #26 8006c3a: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006c3e: e015 b.n 8006c6c 8006c40: 683b ldr r3, [r7, #0] 8006c42: 681b ldr r3, [r3, #0] 8006c44: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006c46: 6abb ldr r3, [r7, #40] @ 0x28 8006c48: fa93 f3a3 rbit r3, r3 8006c4c: 627b str r3, [r7, #36] @ 0x24 return result; 8006c4e: 6a7b ldr r3, [r7, #36] @ 0x24 8006c50: 62fb str r3, [r7, #44] @ 0x2c if (value == 0U) 8006c52: 6afb ldr r3, [r7, #44] @ 0x2c 8006c54: 2b00 cmp r3, #0 8006c56: d101 bne.n 8006c5c return 32U; 8006c58: 2320 movs r3, #32 8006c5a: e003 b.n 8006c64 return __builtin_clz(value); 8006c5c: 6afb ldr r3, [r7, #44] @ 0x2c 8006c5e: fab3 f383 clz r3, r3 8006c62: b2db uxtb r3, r3 8006c64: 3301 adds r3, #1 8006c66: 069b lsls r3, r3, #26 8006c68: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006c6c: 683b ldr r3, [r7, #0] 8006c6e: 681b ldr r3, [r3, #0] 8006c70: f3c3 0313 ubfx r3, r3, #0, #20 8006c74: 2b00 cmp r3, #0 8006c76: d109 bne.n 8006c8c 8006c78: 683b ldr r3, [r7, #0] 8006c7a: 681b ldr r3, [r3, #0] 8006c7c: 0e9b lsrs r3, r3, #26 8006c7e: 3301 adds r3, #1 8006c80: f003 031f and.w r3, r3, #31 8006c84: 2101 movs r1, #1 8006c86: fa01 f303 lsl.w r3, r1, r3 8006c8a: e017 b.n 8006cbc 8006c8c: 683b ldr r3, [r7, #0] 8006c8e: 681b ldr r3, [r3, #0] 8006c90: 61fb str r3, [r7, #28] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006c92: 69fb ldr r3, [r7, #28] 8006c94: fa93 f3a3 rbit r3, r3 8006c98: 61bb str r3, [r7, #24] return result; 8006c9a: 69bb ldr r3, [r7, #24] 8006c9c: 623b str r3, [r7, #32] if (value == 0U) 8006c9e: 6a3b ldr r3, [r7, #32] 8006ca0: 2b00 cmp r3, #0 8006ca2: d101 bne.n 8006ca8 return 32U; 8006ca4: 2320 movs r3, #32 8006ca6: e003 b.n 8006cb0 return __builtin_clz(value); 8006ca8: 6a3b ldr r3, [r7, #32] 8006caa: fab3 f383 clz r3, r3 8006cae: b2db uxtb r3, r3 8006cb0: 3301 adds r3, #1 8006cb2: f003 031f and.w r3, r3, #31 8006cb6: 2101 movs r1, #1 8006cb8: fa01 f303 lsl.w r3, r1, r3 8006cbc: ea42 0103 orr.w r1, r2, r3 8006cc0: 683b ldr r3, [r7, #0] 8006cc2: 681b ldr r3, [r3, #0] 8006cc4: f3c3 0313 ubfx r3, r3, #0, #20 8006cc8: 2b00 cmp r3, #0 8006cca: d10d bne.n 8006ce8 8006ccc: 683b ldr r3, [r7, #0] 8006cce: 681b ldr r3, [r3, #0] 8006cd0: 0e9b lsrs r3, r3, #26 8006cd2: 3301 adds r3, #1 8006cd4: f003 021f and.w r2, r3, #31 8006cd8: 4613 mov r3, r2 8006cda: 005b lsls r3, r3, #1 8006cdc: 4413 add r3, r2 8006cde: 3b1e subs r3, #30 8006ce0: 051b lsls r3, r3, #20 8006ce2: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8006ce6: e01b b.n 8006d20 8006ce8: 683b ldr r3, [r7, #0] 8006cea: 681b ldr r3, [r3, #0] 8006cec: 613b str r3, [r7, #16] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006cee: 693b ldr r3, [r7, #16] 8006cf0: fa93 f3a3 rbit r3, r3 8006cf4: 60fb str r3, [r7, #12] return result; 8006cf6: 68fb ldr r3, [r7, #12] 8006cf8: 617b str r3, [r7, #20] if (value == 0U) 8006cfa: 697b ldr r3, [r7, #20] 8006cfc: 2b00 cmp r3, #0 8006cfe: d101 bne.n 8006d04 return 32U; 8006d00: 2320 movs r3, #32 8006d02: e003 b.n 8006d0c return __builtin_clz(value); 8006d04: 697b ldr r3, [r7, #20] 8006d06: fab3 f383 clz r3, r3 8006d0a: b2db uxtb r3, r3 8006d0c: 3301 adds r3, #1 8006d0e: f003 021f and.w r2, r3, #31 8006d12: 4613 mov r3, r2 8006d14: 005b lsls r3, r3, #1 8006d16: 4413 add r3, r2 8006d18: 3b1e subs r3, #30 8006d1a: 051b lsls r3, r3, #20 8006d1c: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006d20: 430b orrs r3, r1 8006d22: 683a ldr r2, [r7, #0] 8006d24: 6892 ldr r2, [r2, #8] 8006d26: 4619 mov r1, r3 8006d28: f7ff f9e8 bl 80060fc /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 8006d2c: 683b ldr r3, [r7, #0] 8006d2e: 681b ldr r3, [r3, #0] 8006d30: 2b00 cmp r3, #0 8006d32: f280 80cf bge.w 8006ed4 { /* Configuration of common ADC parameters */ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8006d36: 687b ldr r3, [r7, #4] 8006d38: 681b ldr r3, [r3, #0] 8006d3a: 4a06 ldr r2, [pc, #24] @ (8006d54 ) 8006d3c: 4293 cmp r3, r2 8006d3e: d004 beq.n 8006d4a 8006d40: 687b ldr r3, [r7, #4] 8006d42: 681b ldr r3, [r3, #0] 8006d44: 4a04 ldr r2, [pc, #16] @ (8006d58 ) 8006d46: 4293 cmp r3, r2 8006d48: d10a bne.n 8006d60 8006d4a: 4b04 ldr r3, [pc, #16] @ (8006d5c ) 8006d4c: e009 b.n 8006d62 8006d4e: bf00 nop 8006d50: 47ff0000 .word 0x47ff0000 8006d54: 40022000 .word 0x40022000 8006d58: 40022100 .word 0x40022100 8006d5c: 40022300 .word 0x40022300 8006d60: 4b61 ldr r3, [pc, #388] @ (8006ee8 ) 8006d62: 4618 mov r0, r3 8006d64: f7ff f916 bl 8005f94 8006d68: 66f8 str r0, [r7, #108] @ 0x6c /* Software is allowed to change common parameters only when all ADCs */ /* of the common group are disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8006d6a: 687b ldr r3, [r7, #4] 8006d6c: 681b ldr r3, [r3, #0] 8006d6e: 4a5f ldr r2, [pc, #380] @ (8006eec ) 8006d70: 4293 cmp r3, r2 8006d72: d004 beq.n 8006d7e 8006d74: 687b ldr r3, [r7, #4] 8006d76: 681b ldr r3, [r3, #0] 8006d78: 4a5d ldr r2, [pc, #372] @ (8006ef0 ) 8006d7a: 4293 cmp r3, r2 8006d7c: d10e bne.n 8006d9c 8006d7e: 485b ldr r0, [pc, #364] @ (8006eec ) 8006d80: f7ff fa90 bl 80062a4 8006d84: 4604 mov r4, r0 8006d86: 485a ldr r0, [pc, #360] @ (8006ef0 ) 8006d88: f7ff fa8c bl 80062a4 8006d8c: 4603 mov r3, r0 8006d8e: 4323 orrs r3, r4 8006d90: 2b00 cmp r3, #0 8006d92: bf0c ite eq 8006d94: 2301 moveq r3, #1 8006d96: 2300 movne r3, #0 8006d98: b2db uxtb r3, r3 8006d9a: e008 b.n 8006dae 8006d9c: 4855 ldr r0, [pc, #340] @ (8006ef4 ) 8006d9e: f7ff fa81 bl 80062a4 8006da2: 4603 mov r3, r0 8006da4: 2b00 cmp r3, #0 8006da6: bf0c ite eq 8006da8: 2301 moveq r3, #1 8006daa: 2300 movne r3, #0 8006dac: b2db uxtb r3, r3 8006dae: 2b00 cmp r3, #0 8006db0: d07d beq.n 8006eae { /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 8006db2: 683b ldr r3, [r7, #0] 8006db4: 681b ldr r3, [r3, #0] 8006db6: 4a50 ldr r2, [pc, #320] @ (8006ef8 ) 8006db8: 4293 cmp r3, r2 8006dba: d130 bne.n 8006e1e 8006dbc: 6efb ldr r3, [r7, #108] @ 0x6c 8006dbe: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8006dc2: 2b00 cmp r3, #0 8006dc4: d12b bne.n 8006e1e { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8006dc6: 687b ldr r3, [r7, #4] 8006dc8: 681b ldr r3, [r3, #0] 8006dca: 4a4a ldr r2, [pc, #296] @ (8006ef4 ) 8006dcc: 4293 cmp r3, r2 8006dce: f040 8081 bne.w 8006ed4 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); 8006dd2: 687b ldr r3, [r7, #4] 8006dd4: 681b ldr r3, [r3, #0] 8006dd6: 4a45 ldr r2, [pc, #276] @ (8006eec ) 8006dd8: 4293 cmp r3, r2 8006dda: d004 beq.n 8006de6 8006ddc: 687b ldr r3, [r7, #4] 8006dde: 681b ldr r3, [r3, #0] 8006de0: 4a43 ldr r2, [pc, #268] @ (8006ef0 ) 8006de2: 4293 cmp r3, r2 8006de4: d101 bne.n 8006dea 8006de6: 4a45 ldr r2, [pc, #276] @ (8006efc ) 8006de8: e000 b.n 8006dec 8006dea: 4a3f ldr r2, [pc, #252] @ (8006ee8 ) 8006dec: 6efb ldr r3, [r7, #108] @ 0x6c 8006dee: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 8006df2: 4619 mov r1, r3 8006df4: 4610 mov r0, r2 8006df6: f7ff f8ba bl 8005f6e /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8006dfa: 4b41 ldr r3, [pc, #260] @ (8006f00 ) 8006dfc: 681b ldr r3, [r3, #0] 8006dfe: 099b lsrs r3, r3, #6 8006e00: 4a40 ldr r2, [pc, #256] @ (8006f04 ) 8006e02: fba2 2303 umull r2, r3, r2, r3 8006e06: 099b lsrs r3, r3, #6 8006e08: 3301 adds r3, #1 8006e0a: 005b lsls r3, r3, #1 8006e0c: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8006e0e: e002 b.n 8006e16 { wait_loop_index--; 8006e10: 68bb ldr r3, [r7, #8] 8006e12: 3b01 subs r3, #1 8006e14: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8006e16: 68bb ldr r3, [r7, #8] 8006e18: 2b00 cmp r3, #0 8006e1a: d1f9 bne.n 8006e10 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8006e1c: e05a b.n 8006ed4 } } } else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 8006e1e: 683b ldr r3, [r7, #0] 8006e20: 681b ldr r3, [r3, #0] 8006e22: 4a39 ldr r2, [pc, #228] @ (8006f08 ) 8006e24: 4293 cmp r3, r2 8006e26: d11e bne.n 8006e66 8006e28: 6efb ldr r3, [r7, #108] @ 0x6c 8006e2a: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8006e2e: 2b00 cmp r3, #0 8006e30: d119 bne.n 8006e66 { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 8006e32: 687b ldr r3, [r7, #4] 8006e34: 681b ldr r3, [r3, #0] 8006e36: 4a2f ldr r2, [pc, #188] @ (8006ef4 ) 8006e38: 4293 cmp r3, r2 8006e3a: d14b bne.n 8006ed4 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); 8006e3c: 687b ldr r3, [r7, #4] 8006e3e: 681b ldr r3, [r3, #0] 8006e40: 4a2a ldr r2, [pc, #168] @ (8006eec ) 8006e42: 4293 cmp r3, r2 8006e44: d004 beq.n 8006e50 8006e46: 687b ldr r3, [r7, #4] 8006e48: 681b ldr r3, [r3, #0] 8006e4a: 4a29 ldr r2, [pc, #164] @ (8006ef0 ) 8006e4c: 4293 cmp r3, r2 8006e4e: d101 bne.n 8006e54 8006e50: 4a2a ldr r2, [pc, #168] @ (8006efc ) 8006e52: e000 b.n 8006e56 8006e54: 4a24 ldr r2, [pc, #144] @ (8006ee8 ) 8006e56: 6efb ldr r3, [r7, #108] @ 0x6c 8006e58: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8006e5c: 4619 mov r1, r3 8006e5e: 4610 mov r0, r2 8006e60: f7ff f885 bl 8005f6e if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 8006e64: e036 b.n 8006ed4 } } else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) 8006e66: 683b ldr r3, [r7, #0] 8006e68: 681b ldr r3, [r3, #0] 8006e6a: 4a28 ldr r2, [pc, #160] @ (8006f0c ) 8006e6c: 4293 cmp r3, r2 8006e6e: d131 bne.n 8006ed4 8006e70: 6efb ldr r3, [r7, #108] @ 0x6c 8006e72: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8006e76: 2b00 cmp r3, #0 8006e78: d12c bne.n 8006ed4 { if (ADC_VREFINT_INSTANCE(hadc)) 8006e7a: 687b ldr r3, [r7, #4] 8006e7c: 681b ldr r3, [r3, #0] 8006e7e: 4a1d ldr r2, [pc, #116] @ (8006ef4 ) 8006e80: 4293 cmp r3, r2 8006e82: d127 bne.n 8006ed4 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); 8006e84: 687b ldr r3, [r7, #4] 8006e86: 681b ldr r3, [r3, #0] 8006e88: 4a18 ldr r2, [pc, #96] @ (8006eec ) 8006e8a: 4293 cmp r3, r2 8006e8c: d004 beq.n 8006e98 8006e8e: 687b ldr r3, [r7, #4] 8006e90: 681b ldr r3, [r3, #0] 8006e92: 4a17 ldr r2, [pc, #92] @ (8006ef0 ) 8006e94: 4293 cmp r3, r2 8006e96: d101 bne.n 8006e9c 8006e98: 4a18 ldr r2, [pc, #96] @ (8006efc ) 8006e9a: e000 b.n 8006e9e 8006e9c: 4a12 ldr r2, [pc, #72] @ (8006ee8 ) 8006e9e: 6efb ldr r3, [r7, #108] @ 0x6c 8006ea0: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8006ea4: 4619 mov r1, r3 8006ea6: 4610 mov r0, r2 8006ea8: f7ff f861 bl 8005f6e 8006eac: e012 b.n 8006ed4 /* enabled and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8006eae: 687b ldr r3, [r7, #4] 8006eb0: 6d5b ldr r3, [r3, #84] @ 0x54 8006eb2: f043 0220 orr.w r2, r3, #32 8006eb6: 687b ldr r3, [r7, #4] 8006eb8: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8006eba: 2301 movs r3, #1 8006ebc: f887 307f strb.w r3, [r7, #127] @ 0x7f 8006ec0: e008 b.n 8006ed4 /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8006ec2: 687b ldr r3, [r7, #4] 8006ec4: 6d5b ldr r3, [r3, #84] @ 0x54 8006ec6: f043 0220 orr.w r2, r3, #32 8006eca: 687b ldr r3, [r7, #4] 8006ecc: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8006ece: 2301 movs r3, #1 8006ed0: f887 307f strb.w r3, [r7, #127] @ 0x7f } /* Process unlocked */ __HAL_UNLOCK(hadc); 8006ed4: 687b ldr r3, [r7, #4] 8006ed6: 2200 movs r2, #0 8006ed8: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 8006edc: f897 307f ldrb.w r3, [r7, #127] @ 0x7f } 8006ee0: 4618 mov r0, r3 8006ee2: 3784 adds r7, #132 @ 0x84 8006ee4: 46bd mov sp, r7 8006ee6: bd90 pop {r4, r7, pc} 8006ee8: 58026300 .word 0x58026300 8006eec: 40022000 .word 0x40022000 8006ef0: 40022100 .word 0x40022100 8006ef4: 58026000 .word 0x58026000 8006ef8: cb840000 .word 0xcb840000 8006efc: 40022300 .word 0x40022300 8006f00: 24000034 .word 0x24000034 8006f04: 053e2d63 .word 0x053e2d63 8006f08: c7520000 .word 0xc7520000 8006f0c: cfb80000 .word 0xcfb80000 08006f10 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { 8006f10: b580 push {r7, lr} 8006f12: b084 sub sp, #16 8006f14: af00 add r7, sp, #0 8006f16: 6078 str r0, [r7, #4] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8006f18: 687b ldr r3, [r7, #4] 8006f1a: 681b ldr r3, [r3, #0] 8006f1c: 4618 mov r0, r3 8006f1e: f7ff f9c1 bl 80062a4 8006f22: 4603 mov r3, r0 8006f24: 2b00 cmp r3, #0 8006f26: d16e bne.n 8007006 { /* Check if conditions to enable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) 8006f28: 687b ldr r3, [r7, #4] 8006f2a: 681b ldr r3, [r3, #0] 8006f2c: 689a ldr r2, [r3, #8] 8006f2e: 4b38 ldr r3, [pc, #224] @ (8007010 ) 8006f30: 4013 ands r3, r2 8006f32: 2b00 cmp r3, #0 8006f34: d00d beq.n 8006f52 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006f36: 687b ldr r3, [r7, #4] 8006f38: 6d5b ldr r3, [r3, #84] @ 0x54 8006f3a: f043 0210 orr.w r2, r3, #16 8006f3e: 687b ldr r3, [r7, #4] 8006f40: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006f42: 687b ldr r3, [r7, #4] 8006f44: 6d9b ldr r3, [r3, #88] @ 0x58 8006f46: f043 0201 orr.w r2, r3, #1 8006f4a: 687b ldr r3, [r7, #4] 8006f4c: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006f4e: 2301 movs r3, #1 8006f50: e05a b.n 8007008 } /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); 8006f52: 687b ldr r3, [r7, #4] 8006f54: 681b ldr r3, [r3, #0] 8006f56: 4618 mov r0, r3 8006f58: f7ff f97c bl 8006254 /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); 8006f5c: f7fe ffa2 bl 8005ea4 8006f60: 60f8 str r0, [r7, #12] /* Poll for ADC ready flag raised except case of multimode enabled and ADC slave selected. */ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8006f62: 687b ldr r3, [r7, #4] 8006f64: 681b ldr r3, [r3, #0] 8006f66: 4a2b ldr r2, [pc, #172] @ (8007014 ) 8006f68: 4293 cmp r3, r2 8006f6a: d004 beq.n 8006f76 8006f6c: 687b ldr r3, [r7, #4] 8006f6e: 681b ldr r3, [r3, #0] 8006f70: 4a29 ldr r2, [pc, #164] @ (8007018 ) 8006f72: 4293 cmp r3, r2 8006f74: d101 bne.n 8006f7a 8006f76: 4b29 ldr r3, [pc, #164] @ (800701c ) 8006f78: e000 b.n 8006f7c 8006f7a: 4b29 ldr r3, [pc, #164] @ (8007020 ) 8006f7c: 4618 mov r0, r3 8006f7e: f7ff f90d bl 800619c 8006f82: 60b8 str r0, [r7, #8] if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8006f84: 687b ldr r3, [r7, #4] 8006f86: 681b ldr r3, [r3, #0] 8006f88: 4a23 ldr r2, [pc, #140] @ (8007018 ) 8006f8a: 4293 cmp r3, r2 8006f8c: d002 beq.n 8006f94 8006f8e: 687b ldr r3, [r7, #4] 8006f90: 681b ldr r3, [r3, #0] 8006f92: e000 b.n 8006f96 8006f94: 4b1f ldr r3, [pc, #124] @ (8007014 ) 8006f96: 687a ldr r2, [r7, #4] 8006f98: 6812 ldr r2, [r2, #0] 8006f9a: 4293 cmp r3, r2 8006f9c: d02c beq.n 8006ff8 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8006f9e: 68bb ldr r3, [r7, #8] 8006fa0: 2b00 cmp r3, #0 8006fa2: d130 bne.n 8007006 ) { while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8006fa4: e028 b.n 8006ff8 The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ /* Note: Test of ADC enabled required due to hardware constraint to */ /* not enable ADC if already enabled. */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8006fa6: 687b ldr r3, [r7, #4] 8006fa8: 681b ldr r3, [r3, #0] 8006faa: 4618 mov r0, r3 8006fac: f7ff f97a bl 80062a4 8006fb0: 4603 mov r3, r0 8006fb2: 2b00 cmp r3, #0 8006fb4: d104 bne.n 8006fc0 { LL_ADC_Enable(hadc->Instance); 8006fb6: 687b ldr r3, [r7, #4] 8006fb8: 681b ldr r3, [r3, #0] 8006fba: 4618 mov r0, r3 8006fbc: f7ff f94a bl 8006254 } if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8006fc0: f7fe ff70 bl 8005ea4 8006fc4: 4602 mov r2, r0 8006fc6: 68fb ldr r3, [r7, #12] 8006fc8: 1ad3 subs r3, r2, r3 8006fca: 2b02 cmp r3, #2 8006fcc: d914 bls.n 8006ff8 { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8006fce: 687b ldr r3, [r7, #4] 8006fd0: 681b ldr r3, [r3, #0] 8006fd2: 681b ldr r3, [r3, #0] 8006fd4: f003 0301 and.w r3, r3, #1 8006fd8: 2b01 cmp r3, #1 8006fda: d00d beq.n 8006ff8 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006fdc: 687b ldr r3, [r7, #4] 8006fde: 6d5b ldr r3, [r3, #84] @ 0x54 8006fe0: f043 0210 orr.w r2, r3, #16 8006fe4: 687b ldr r3, [r7, #4] 8006fe6: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006fe8: 687b ldr r3, [r7, #4] 8006fea: 6d9b ldr r3, [r3, #88] @ 0x58 8006fec: f043 0201 orr.w r2, r3, #1 8006ff0: 687b ldr r3, [r7, #4] 8006ff2: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006ff4: 2301 movs r3, #1 8006ff6: e007 b.n 8007008 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8006ff8: 687b ldr r3, [r7, #4] 8006ffa: 681b ldr r3, [r3, #0] 8006ffc: 681b ldr r3, [r3, #0] 8006ffe: f003 0301 and.w r3, r3, #1 8007002: 2b01 cmp r3, #1 8007004: d1cf bne.n 8006fa6 } } } /* Return HAL status */ return HAL_OK; 8007006: 2300 movs r3, #0 } 8007008: 4618 mov r0, r3 800700a: 3710 adds r7, #16 800700c: 46bd mov sp, r7 800700e: bd80 pop {r7, pc} 8007010: 8000003f .word 0x8000003f 8007014: 40022000 .word 0x40022000 8007018: 40022100 .word 0x40022100 800701c: 40022300 .word 0x40022300 8007020: 58026300 .word 0x58026300 08007024 : * stopped. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { 8007024: b580 push {r7, lr} 8007026: b084 sub sp, #16 8007028: af00 add r7, sp, #0 800702a: 6078 str r0, [r7, #4] uint32_t tickstart; const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); 800702c: 687b ldr r3, [r7, #4] 800702e: 681b ldr r3, [r3, #0] 8007030: 4618 mov r0, r3 8007032: f7ff f94a bl 80062ca 8007036: 60f8 str r0, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) 8007038: 687b ldr r3, [r7, #4] 800703a: 681b ldr r3, [r3, #0] 800703c: 4618 mov r0, r3 800703e: f7ff f931 bl 80062a4 8007042: 4603 mov r3, r0 8007044: 2b00 cmp r3, #0 8007046: d047 beq.n 80070d8 && (tmp_adc_is_disable_on_going == 0UL) 8007048: 68fb ldr r3, [r7, #12] 800704a: 2b00 cmp r3, #0 800704c: d144 bne.n 80070d8 ) { /* Check if conditions to disable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) 800704e: 687b ldr r3, [r7, #4] 8007050: 681b ldr r3, [r3, #0] 8007052: 689b ldr r3, [r3, #8] 8007054: f003 030d and.w r3, r3, #13 8007058: 2b01 cmp r3, #1 800705a: d10c bne.n 8007076 { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); 800705c: 687b ldr r3, [r7, #4] 800705e: 681b ldr r3, [r3, #0] 8007060: 4618 mov r0, r3 8007062: f7ff f90b bl 800627c __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); 8007066: 687b ldr r3, [r7, #4] 8007068: 681b ldr r3, [r3, #0] 800706a: 2203 movs r2, #3 800706c: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); 800706e: f7fe ff19 bl 8005ea4 8007072: 60b8 str r0, [r7, #8] while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8007074: e029 b.n 80070ca SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8007076: 687b ldr r3, [r7, #4] 8007078: 6d5b ldr r3, [r3, #84] @ 0x54 800707a: f043 0210 orr.w r2, r3, #16 800707e: 687b ldr r3, [r7, #4] 8007080: 655a str r2, [r3, #84] @ 0x54 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8007082: 687b ldr r3, [r7, #4] 8007084: 6d9b ldr r3, [r3, #88] @ 0x58 8007086: f043 0201 orr.w r2, r3, #1 800708a: 687b ldr r3, [r7, #4] 800708c: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 800708e: 2301 movs r3, #1 8007090: e023 b.n 80070da { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8007092: f7fe ff07 bl 8005ea4 8007096: 4602 mov r2, r0 8007098: 68bb ldr r3, [r7, #8] 800709a: 1ad3 subs r3, r2, r3 800709c: 2b02 cmp r3, #2 800709e: d914 bls.n 80070ca { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 80070a0: 687b ldr r3, [r7, #4] 80070a2: 681b ldr r3, [r3, #0] 80070a4: 689b ldr r3, [r3, #8] 80070a6: f003 0301 and.w r3, r3, #1 80070aa: 2b00 cmp r3, #0 80070ac: d00d beq.n 80070ca { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80070ae: 687b ldr r3, [r7, #4] 80070b0: 6d5b ldr r3, [r3, #84] @ 0x54 80070b2: f043 0210 orr.w r2, r3, #16 80070b6: 687b ldr r3, [r7, #4] 80070b8: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80070ba: 687b ldr r3, [r7, #4] 80070bc: 6d9b ldr r3, [r3, #88] @ 0x58 80070be: f043 0201 orr.w r2, r3, #1 80070c2: 687b ldr r3, [r7, #4] 80070c4: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 80070c6: 2301 movs r3, #1 80070c8: e007 b.n 80070da while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 80070ca: 687b ldr r3, [r7, #4] 80070cc: 681b ldr r3, [r3, #0] 80070ce: 689b ldr r3, [r3, #8] 80070d0: f003 0301 and.w r3, r3, #1 80070d4: 2b00 cmp r3, #0 80070d6: d1dc bne.n 8007092 } } } /* Return HAL status */ return HAL_OK; 80070d8: 2300 movs r3, #0 } 80070da: 4618 mov r0, r3 80070dc: 3710 adds r7, #16 80070de: 46bd mov sp, r7 80070e0: bd80 pop {r7, pc} 080070e2 : * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 80070e2: b580 push {r7, lr} 80070e4: b084 sub sp, #16 80070e6: af00 add r7, sp, #0 80070e8: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80070ea: 687b ldr r3, [r7, #4] 80070ec: 6b9b ldr r3, [r3, #56] @ 0x38 80070ee: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) 80070f0: 68fb ldr r3, [r7, #12] 80070f2: 6d5b ldr r3, [r3, #84] @ 0x54 80070f4: f003 0350 and.w r3, r3, #80 @ 0x50 80070f8: 2b00 cmp r3, #0 80070fa: d14b bne.n 8007194 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 80070fc: 68fb ldr r3, [r7, #12] 80070fe: 6d5b ldr r3, [r3, #84] @ 0x54 8007100: f443 7200 orr.w r2, r3, #512 @ 0x200 8007104: 68fb ldr r3, [r7, #12] 8007106: 655a str r2, [r3, #84] @ 0x54 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ /* Is it the end of the regular sequence ? */ if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) 8007108: 68fb ldr r3, [r7, #12] 800710a: 681b ldr r3, [r3, #0] 800710c: 681b ldr r3, [r3, #0] 800710e: f003 0308 and.w r3, r3, #8 8007112: 2b00 cmp r3, #0 8007114: d021 beq.n 800715a { /* Are conversions software-triggered ? */ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) 8007116: 68fb ldr r3, [r7, #12] 8007118: 681b ldr r3, [r3, #0] 800711a: 4618 mov r0, r3 800711c: f7fe ff9c bl 8006058 8007120: 4603 mov r3, r0 8007122: 2b00 cmp r3, #0 8007124: d032 beq.n 800718c { /* Is CONT bit set ? */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) 8007126: 68fb ldr r3, [r7, #12] 8007128: 681b ldr r3, [r3, #0] 800712a: 68db ldr r3, [r3, #12] 800712c: f403 5300 and.w r3, r3, #8192 @ 0x2000 8007130: 2b00 cmp r3, #0 8007132: d12b bne.n 800718c { /* CONT bit is not set, no more conversions expected */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8007134: 68fb ldr r3, [r7, #12] 8007136: 6d5b ldr r3, [r3, #84] @ 0x54 8007138: f423 7280 bic.w r2, r3, #256 @ 0x100 800713c: 68fb ldr r3, [r7, #12] 800713e: 655a str r2, [r3, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 8007140: 68fb ldr r3, [r7, #12] 8007142: 6d5b ldr r3, [r3, #84] @ 0x54 8007144: f403 5380 and.w r3, r3, #4096 @ 0x1000 8007148: 2b00 cmp r3, #0 800714a: d11f bne.n 800718c { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800714c: 68fb ldr r3, [r7, #12] 800714e: 6d5b ldr r3, [r3, #84] @ 0x54 8007150: f043 0201 orr.w r2, r3, #1 8007154: 68fb ldr r3, [r7, #12] 8007156: 655a str r2, [r3, #84] @ 0x54 8007158: e018 b.n 800718c } else { /* DMA End of Transfer interrupt was triggered but conversions sequence is not over. If DMACFG is set to 0, conversions are stopped. */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL) 800715a: 68fb ldr r3, [r7, #12] 800715c: 681b ldr r3, [r3, #0] 800715e: 68db ldr r3, [r3, #12] 8007160: f003 0303 and.w r3, r3, #3 8007164: 2b00 cmp r3, #0 8007166: d111 bne.n 800718c { /* DMACFG bit is not set, conversions are stopped. */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8007168: 68fb ldr r3, [r7, #12] 800716a: 6d5b ldr r3, [r3, #84] @ 0x54 800716c: f423 7280 bic.w r2, r3, #256 @ 0x100 8007170: 68fb ldr r3, [r7, #12] 8007172: 655a str r2, [r3, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 8007174: 68fb ldr r3, [r7, #12] 8007176: 6d5b ldr r3, [r3, #84] @ 0x54 8007178: f403 5380 and.w r3, r3, #4096 @ 0x1000 800717c: 2b00 cmp r3, #0 800717e: d105 bne.n 800718c { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8007180: 68fb ldr r3, [r7, #12] 8007182: 6d5b ldr r3, [r3, #84] @ 0x54 8007184: f043 0201 orr.w r2, r3, #1 8007188: 68fb ldr r3, [r7, #12] 800718a: 655a str r2, [r3, #84] @ 0x54 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800718c: 68f8 ldr r0, [r7, #12] 800718e: f7fa fb1b bl 80017c8 { /* Call ADC DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } } 8007192: e00e b.n 80071b2 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) 8007194: 68fb ldr r3, [r7, #12] 8007196: 6d5b ldr r3, [r3, #84] @ 0x54 8007198: f003 0310 and.w r3, r3, #16 800719c: 2b00 cmp r3, #0 800719e: d003 beq.n 80071a8 HAL_ADC_ErrorCallback(hadc); 80071a0: 68f8 ldr r0, [r7, #12] 80071a2: f7ff fb4f bl 8006844 } 80071a6: e004 b.n 80071b2 hadc->DMA_Handle->XferErrorCallback(hdma); 80071a8: 68fb ldr r3, [r7, #12] 80071aa: 6cdb ldr r3, [r3, #76] @ 0x4c 80071ac: 6cdb ldr r3, [r3, #76] @ 0x4c 80071ae: 6878 ldr r0, [r7, #4] 80071b0: 4798 blx r3 } 80071b2: bf00 nop 80071b4: 3710 adds r7, #16 80071b6: 46bd mov sp, r7 80071b8: bd80 pop {r7, pc} 080071ba : * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 80071ba: b580 push {r7, lr} 80071bc: b084 sub sp, #16 80071be: af00 add r7, sp, #0 80071c0: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80071c2: 687b ldr r3, [r7, #4] 80071c4: 6b9b ldr r3, [r3, #56] @ 0x38 80071c6: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 80071c8: 68f8 ldr r0, [r7, #12] 80071ca: f7ff fb31 bl 8006830 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 80071ce: bf00 nop 80071d0: 3710 adds r7, #16 80071d2: 46bd mov sp, r7 80071d4: bd80 pop {r7, pc} 080071d6 : * @brief DMA error callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 80071d6: b580 push {r7, lr} 80071d8: b084 sub sp, #16 80071da: af00 add r7, sp, #0 80071dc: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80071de: 687b ldr r3, [r7, #4] 80071e0: 6b9b ldr r3, [r3, #56] @ 0x38 80071e2: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 80071e4: 68fb ldr r3, [r7, #12] 80071e6: 6d5b ldr r3, [r3, #84] @ 0x54 80071e8: f043 0240 orr.w r2, r3, #64 @ 0x40 80071ec: 68fb ldr r3, [r7, #12] 80071ee: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 80071f0: 68fb ldr r3, [r7, #12] 80071f2: 6d9b ldr r3, [r3, #88] @ 0x58 80071f4: f043 0204 orr.w r2, r3, #4 80071f8: 68fb ldr r3, [r7, #12] 80071fa: 659a str r2, [r3, #88] @ 0x58 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 80071fc: 68f8 ldr r0, [r7, #12] 80071fe: f7ff fb21 bl 8006844 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8007202: bf00 nop 8007204: 3710 adds r7, #16 8007206: 46bd mov sp, r7 8007208: bd80 pop {r7, pc} ... 0800720c : * stopped. * @param hadc ADC handle * @retval None. */ void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc) { 800720c: b580 push {r7, lr} 800720e: b084 sub sp, #16 8007210: af00 add r7, sp, #0 8007212: 6078 str r0, [r7, #4] uint32_t freq; if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc)) 8007214: 687b ldr r3, [r7, #4] 8007216: 681b ldr r3, [r3, #0] 8007218: 4a7a ldr r2, [pc, #488] @ (8007404 ) 800721a: 4293 cmp r3, r2 800721c: d004 beq.n 8007228 800721e: 687b ldr r3, [r7, #4] 8007220: 681b ldr r3, [r3, #0] 8007222: 4a79 ldr r2, [pc, #484] @ (8007408 ) 8007224: 4293 cmp r3, r2 8007226: d109 bne.n 800723c 8007228: 4b78 ldr r3, [pc, #480] @ (800740c ) 800722a: 689b ldr r3, [r3, #8] 800722c: f403 3340 and.w r3, r3, #196608 @ 0x30000 8007230: 2b00 cmp r3, #0 8007232: bf14 ite ne 8007234: 2301 movne r3, #1 8007236: 2300 moveq r3, #0 8007238: b2db uxtb r3, r3 800723a: e008 b.n 800724e 800723c: 4b74 ldr r3, [pc, #464] @ (8007410 ) 800723e: 689b ldr r3, [r3, #8] 8007240: f403 3340 and.w r3, r3, #196608 @ 0x30000 8007244: 2b00 cmp r3, #0 8007246: bf14 ite ne 8007248: 2301 movne r3, #1 800724a: 2300 moveq r3, #0 800724c: b2db uxtb r3, r3 800724e: 2b00 cmp r3, #0 8007250: d01c beq.n 800728c { freq = HAL_RCC_GetHCLKFreq(); 8007252: f005 fb47 bl 800c8e4 8007256: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 8007258: 687b ldr r3, [r7, #4] 800725a: 685b ldr r3, [r3, #4] 800725c: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8007260: d010 beq.n 8007284 8007262: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8007266: d873 bhi.n 8007350 8007268: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800726c: d002 beq.n 8007274 800726e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8007272: d16d bne.n 8007350 { case ADC_CLOCK_SYNC_PCLK_DIV1: case ADC_CLOCK_SYNC_PCLK_DIV2: freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos); 8007274: 687b ldr r3, [r7, #4] 8007276: 685b ldr r3, [r3, #4] 8007278: 0c1b lsrs r3, r3, #16 800727a: 68fa ldr r2, [r7, #12] 800727c: fbb2 f3f3 udiv r3, r2, r3 8007280: 60fb str r3, [r7, #12] break; 8007282: e068 b.n 8007356 case ADC_CLOCK_SYNC_PCLK_DIV4: freq /= 4UL; 8007284: 68fb ldr r3, [r7, #12] 8007286: 089b lsrs r3, r3, #2 8007288: 60fb str r3, [r7, #12] break; 800728a: e064 b.n 8007356 break; } } else { freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC); 800728c: f44f 2000 mov.w r0, #524288 @ 0x80000 8007290: f04f 0100 mov.w r1, #0 8007294: f006 fdb2 bl 800ddfc 8007298: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 800729a: 687b ldr r3, [r7, #4] 800729c: 685b ldr r3, [r3, #4] 800729e: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 80072a2: d051 beq.n 8007348 80072a4: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 80072a8: d854 bhi.n 8007354 80072aa: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 80072ae: d047 beq.n 8007340 80072b0: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 80072b4: d84e bhi.n 8007354 80072b6: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 80072ba: d03d beq.n 8007338 80072bc: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 80072c0: d848 bhi.n 8007354 80072c2: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 80072c6: d033 beq.n 8007330 80072c8: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 80072cc: d842 bhi.n 8007354 80072ce: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 80072d2: d029 beq.n 8007328 80072d4: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 80072d8: d83c bhi.n 8007354 80072da: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 80072de: d01a beq.n 8007316 80072e0: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 80072e4: d836 bhi.n 8007354 80072e6: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 80072ea: d014 beq.n 8007316 80072ec: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 80072f0: d830 bhi.n 8007354 80072f2: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80072f6: d00e beq.n 8007316 80072f8: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80072fc: d82a bhi.n 8007354 80072fe: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8007302: d008 beq.n 8007316 8007304: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8007308: d824 bhi.n 8007354 800730a: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800730e: d002 beq.n 8007316 8007310: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 8007314: d11e bne.n 8007354 case ADC_CLOCK_ASYNC_DIV4: case ADC_CLOCK_ASYNC_DIV6: case ADC_CLOCK_ASYNC_DIV8: case ADC_CLOCK_ASYNC_DIV10: case ADC_CLOCK_ASYNC_DIV12: freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL); 8007316: 687b ldr r3, [r7, #4] 8007318: 685b ldr r3, [r3, #4] 800731a: 0c9b lsrs r3, r3, #18 800731c: 005b lsls r3, r3, #1 800731e: 68fa ldr r2, [r7, #12] 8007320: fbb2 f3f3 udiv r3, r2, r3 8007324: 60fb str r3, [r7, #12] break; 8007326: e016 b.n 8007356 case ADC_CLOCK_ASYNC_DIV16: freq /= 16UL; 8007328: 68fb ldr r3, [r7, #12] 800732a: 091b lsrs r3, r3, #4 800732c: 60fb str r3, [r7, #12] break; 800732e: e012 b.n 8007356 case ADC_CLOCK_ASYNC_DIV32: freq /= 32UL; 8007330: 68fb ldr r3, [r7, #12] 8007332: 095b lsrs r3, r3, #5 8007334: 60fb str r3, [r7, #12] break; 8007336: e00e b.n 8007356 case ADC_CLOCK_ASYNC_DIV64: freq /= 64UL; 8007338: 68fb ldr r3, [r7, #12] 800733a: 099b lsrs r3, r3, #6 800733c: 60fb str r3, [r7, #12] break; 800733e: e00a b.n 8007356 case ADC_CLOCK_ASYNC_DIV128: freq /= 128UL; 8007340: 68fb ldr r3, [r7, #12] 8007342: 09db lsrs r3, r3, #7 8007344: 60fb str r3, [r7, #12] break; 8007346: e006 b.n 8007356 case ADC_CLOCK_ASYNC_DIV256: freq /= 256UL; 8007348: 68fb ldr r3, [r7, #12] 800734a: 0a1b lsrs r3, r3, #8 800734c: 60fb str r3, [r7, #12] break; 800734e: e002 b.n 8007356 break; 8007350: bf00 nop 8007352: e000 b.n 8007356 default: break; 8007354: bf00 nop else /* if(freq > 25000000UL) */ { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } #else if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */ 8007356: f7fe fdb1 bl 8005ebc 800735a: 4603 mov r3, r0 800735c: f241 0203 movw r2, #4099 @ 0x1003 8007360: 4293 cmp r3, r2 8007362: d815 bhi.n 8007390 { if (freq > 20000000UL) 8007364: 68fb ldr r3, [r7, #12] 8007366: 4a2b ldr r2, [pc, #172] @ (8007414 ) 8007368: 4293 cmp r3, r2 800736a: d908 bls.n 800737e { SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 800736c: 687b ldr r3, [r7, #4] 800736e: 681b ldr r3, [r3, #0] 8007370: 689a ldr r2, [r3, #8] 8007372: 687b ldr r3, [r7, #4] 8007374: 681b ldr r3, [r3, #0] 8007376: f442 7280 orr.w r2, r2, #256 @ 0x100 800737a: 609a str r2, [r3, #8] { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } } #endif /* ADC_VER_V5_3 */ } 800737c: e03e b.n 80073fc CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 800737e: 687b ldr r3, [r7, #4] 8007380: 681b ldr r3, [r3, #0] 8007382: 689a ldr r2, [r3, #8] 8007384: 687b ldr r3, [r7, #4] 8007386: 681b ldr r3, [r3, #0] 8007388: f422 7280 bic.w r2, r2, #256 @ 0x100 800738c: 609a str r2, [r3, #8] } 800738e: e035 b.n 80073fc freq /= 2U; /* divider by 2 for Rev.V */ 8007390: 68fb ldr r3, [r7, #12] 8007392: 085b lsrs r3, r3, #1 8007394: 60fb str r3, [r7, #12] if (freq <= 6250000UL) 8007396: 68fb ldr r3, [r7, #12] 8007398: 4a1f ldr r2, [pc, #124] @ (8007418 ) 800739a: 4293 cmp r3, r2 800739c: d808 bhi.n 80073b0 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL); 800739e: 687b ldr r3, [r7, #4] 80073a0: 681b ldr r3, [r3, #0] 80073a2: 689a ldr r2, [r3, #8] 80073a4: 687b ldr r3, [r7, #4] 80073a6: 681b ldr r3, [r3, #0] 80073a8: f422 7240 bic.w r2, r2, #768 @ 0x300 80073ac: 609a str r2, [r3, #8] } 80073ae: e025 b.n 80073fc else if (freq <= 12500000UL) 80073b0: 68fb ldr r3, [r7, #12] 80073b2: 4a1a ldr r2, [pc, #104] @ (800741c ) 80073b4: 4293 cmp r3, r2 80073b6: d80a bhi.n 80073ce MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0); 80073b8: 687b ldr r3, [r7, #4] 80073ba: 681b ldr r3, [r3, #0] 80073bc: 689b ldr r3, [r3, #8] 80073be: f423 7240 bic.w r2, r3, #768 @ 0x300 80073c2: 687b ldr r3, [r7, #4] 80073c4: 681b ldr r3, [r3, #0] 80073c6: f442 7280 orr.w r2, r2, #256 @ 0x100 80073ca: 609a str r2, [r3, #8] } 80073cc: e016 b.n 80073fc else if (freq <= 25000000UL) 80073ce: 68fb ldr r3, [r7, #12] 80073d0: 4a13 ldr r2, [pc, #76] @ (8007420 ) 80073d2: 4293 cmp r3, r2 80073d4: d80a bhi.n 80073ec MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1); 80073d6: 687b ldr r3, [r7, #4] 80073d8: 681b ldr r3, [r3, #0] 80073da: 689b ldr r3, [r3, #8] 80073dc: f423 7240 bic.w r2, r3, #768 @ 0x300 80073e0: 687b ldr r3, [r7, #4] 80073e2: 681b ldr r3, [r3, #0] 80073e4: f442 7200 orr.w r2, r2, #512 @ 0x200 80073e8: 609a str r2, [r3, #8] } 80073ea: e007 b.n 80073fc MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); 80073ec: 687b ldr r3, [r7, #4] 80073ee: 681b ldr r3, [r3, #0] 80073f0: 689a ldr r2, [r3, #8] 80073f2: 687b ldr r3, [r7, #4] 80073f4: 681b ldr r3, [r3, #0] 80073f6: f442 7240 orr.w r2, r2, #768 @ 0x300 80073fa: 609a str r2, [r3, #8] } 80073fc: bf00 nop 80073fe: 3710 adds r7, #16 8007400: 46bd mov sp, r7 8007402: bd80 pop {r7, pc} 8007404: 40022000 .word 0x40022000 8007408: 40022100 .word 0x40022100 800740c: 40022300 .word 0x40022300 8007410: 58026300 .word 0x58026300 8007414: 01312d00 .word 0x01312d00 8007418: 005f5e10 .word 0x005f5e10 800741c: 00bebc20 .word 0x00bebc20 8007420: 017d7840 .word 0x017d7840 08007424 : { 8007424: b480 push {r7} 8007426: b083 sub sp, #12 8007428: af00 add r7, sp, #0 800742a: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 800742c: 687b ldr r3, [r7, #4] 800742e: 689b ldr r3, [r3, #8] 8007430: f003 0301 and.w r3, r3, #1 8007434: 2b01 cmp r3, #1 8007436: d101 bne.n 800743c 8007438: 2301 movs r3, #1 800743a: e000 b.n 800743e 800743c: 2300 movs r3, #0 } 800743e: 4618 mov r0, r3 8007440: 370c adds r7, #12 8007442: 46bd mov sp, r7 8007444: f85d 7b04 ldr.w r7, [sp], #4 8007448: 4770 bx lr ... 0800744c : { 800744c: b480 push {r7} 800744e: b085 sub sp, #20 8007450: af00 add r7, sp, #0 8007452: 60f8 str r0, [r7, #12] 8007454: 60b9 str r1, [r7, #8] 8007456: 607a str r2, [r7, #4] MODIFY_REG(ADCx->CR, 8007458: 68fb ldr r3, [r7, #12] 800745a: 689a ldr r2, [r3, #8] 800745c: 4b09 ldr r3, [pc, #36] @ (8007484 ) 800745e: 4013 ands r3, r2 8007460: 68ba ldr r2, [r7, #8] 8007462: f402 3180 and.w r1, r2, #65536 @ 0x10000 8007466: 687a ldr r2, [r7, #4] 8007468: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 800746c: 430a orrs r2, r1 800746e: 4313 orrs r3, r2 8007470: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 8007474: 68fb ldr r3, [r7, #12] 8007476: 609a str r2, [r3, #8] } 8007478: bf00 nop 800747a: 3714 adds r7, #20 800747c: 46bd mov sp, r7 800747e: f85d 7b04 ldr.w r7, [sp], #4 8007482: 4770 bx lr 8007484: 3ffeffc0 .word 0x3ffeffc0 08007488 : { 8007488: b480 push {r7} 800748a: b083 sub sp, #12 800748c: af00 add r7, sp, #0 800748e: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); 8007490: 687b ldr r3, [r7, #4] 8007492: 689b ldr r3, [r3, #8] 8007494: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007498: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800749c: d101 bne.n 80074a2 800749e: 2301 movs r3, #1 80074a0: e000 b.n 80074a4 80074a2: 2300 movs r3, #0 } 80074a4: 4618 mov r0, r3 80074a6: 370c adds r7, #12 80074a8: 46bd mov sp, r7 80074aa: f85d 7b04 ldr.w r7, [sp], #4 80074ae: 4770 bx lr 080074b0 : { 80074b0: b480 push {r7} 80074b2: b083 sub sp, #12 80074b4: af00 add r7, sp, #0 80074b6: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 80074b8: 687b ldr r3, [r7, #4] 80074ba: 689b ldr r3, [r3, #8] 80074bc: f003 0304 and.w r3, r3, #4 80074c0: 2b04 cmp r3, #4 80074c2: d101 bne.n 80074c8 80074c4: 2301 movs r3, #1 80074c6: e000 b.n 80074ca 80074c8: 2300 movs r3, #0 } 80074ca: 4618 mov r0, r3 80074cc: 370c adds r7, #12 80074ce: 46bd mov sp, r7 80074d0: f85d 7b04 ldr.w r7, [sp], #4 80074d4: 4770 bx lr ... 080074d8 : * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff) { 80074d8: b580 push {r7, lr} 80074da: b086 sub sp, #24 80074dc: af00 add r7, sp, #0 80074de: 60f8 str r0, [r7, #12] 80074e0: 60b9 str r1, [r7, #8] 80074e2: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; 80074e4: 2300 movs r3, #0 80074e6: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Process locked */ __HAL_LOCK(hadc); 80074e8: 68fb ldr r3, [r7, #12] 80074ea: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 80074ee: 2b01 cmp r3, #1 80074f0: d101 bne.n 80074f6 80074f2: 2302 movs r3, #2 80074f4: e04c b.n 8007590 80074f6: 68fb ldr r3, [r7, #12] 80074f8: 2201 movs r2, #1 80074fa: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Calibration prerequisite: ADC must be disabled. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); 80074fe: 68f8 ldr r0, [r7, #12] 8007500: f7ff fd90 bl 8007024 8007504: 4603 mov r3, r0 8007506: 75fb strb r3, [r7, #23] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8007508: 7dfb ldrb r3, [r7, #23] 800750a: 2b00 cmp r3, #0 800750c: d135 bne.n 800757a { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800750e: 68fb ldr r3, [r7, #12] 8007510: 6d5a ldr r2, [r3, #84] @ 0x54 8007512: 4b21 ldr r3, [pc, #132] @ (8007598 ) 8007514: 4013 ands r3, r2 8007516: f043 0202 orr.w r2, r3, #2 800751a: 68fb ldr r3, [r7, #12] 800751c: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Start ADC calibration in mode single-ended or differential */ LL_ADC_StartCalibration(hadc->Instance, CalibrationMode, SingleDiff); 800751e: 68fb ldr r3, [r7, #12] 8007520: 681b ldr r3, [r3, #0] 8007522: 687a ldr r2, [r7, #4] 8007524: 68b9 ldr r1, [r7, #8] 8007526: 4618 mov r0, r3 8007528: f7ff ff90 bl 800744c /* Wait for calibration completion */ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 800752c: e014 b.n 8007558 { wait_loop_index++; 800752e: 693b ldr r3, [r7, #16] 8007530: 3301 adds r3, #1 8007532: 613b str r3, [r7, #16] if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) 8007534: 693b ldr r3, [r7, #16] 8007536: 4a19 ldr r2, [pc, #100] @ (800759c ) 8007538: 4293 cmp r3, r2 800753a: d30d bcc.n 8007558 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800753c: 68fb ldr r3, [r7, #12] 800753e: 6d5b ldr r3, [r3, #84] @ 0x54 8007540: f023 0312 bic.w r3, r3, #18 8007544: f043 0210 orr.w r2, r3, #16 8007548: 68fb ldr r3, [r7, #12] 800754a: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800754c: 68fb ldr r3, [r7, #12] 800754e: 2200 movs r2, #0 8007550: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 8007554: 2301 movs r3, #1 8007556: e01b b.n 8007590 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 8007558: 68fb ldr r3, [r7, #12] 800755a: 681b ldr r3, [r3, #0] 800755c: 4618 mov r0, r3 800755e: f7ff ff93 bl 8007488 8007562: 4603 mov r3, r0 8007564: 2b00 cmp r3, #0 8007566: d1e2 bne.n 800752e } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8007568: 68fb ldr r3, [r7, #12] 800756a: 6d5b ldr r3, [r3, #84] @ 0x54 800756c: f023 0303 bic.w r3, r3, #3 8007570: f043 0201 orr.w r2, r3, #1 8007574: 68fb ldr r3, [r7, #12] 8007576: 655a str r2, [r3, #84] @ 0x54 8007578: e005 b.n 8007586 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800757a: 68fb ldr r3, [r7, #12] 800757c: 6d5b ldr r3, [r3, #84] @ 0x54 800757e: f043 0210 orr.w r2, r3, #16 8007582: 68fb ldr r3, [r7, #12] 8007584: 655a str r2, [r3, #84] @ 0x54 /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } /* Process unlocked */ __HAL_UNLOCK(hadc); 8007586: 68fb ldr r3, [r7, #12] 8007588: 2200 movs r2, #0 800758a: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 800758e: 7dfb ldrb r3, [r7, #23] } 8007590: 4618 mov r0, r3 8007592: 3718 adds r7, #24 8007594: 46bd mov sp, r7 8007596: bd80 pop {r7, pc} 8007598: ffffeefd .word 0xffffeefd 800759c: 25c3f800 .word 0x25c3f800 080075a0 : * @param hadc Master ADC handle * @param multimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { 80075a0: b590 push {r4, r7, lr} 80075a2: b09f sub sp, #124 @ 0x7c 80075a4: af00 add r7, sp, #0 80075a6: 6078 str r0, [r7, #4] 80075a8: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80075aa: 2300 movs r3, #0 80075ac: f887 3077 strb.w r3, [r7, #119] @ 0x77 assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); 80075b0: 687b ldr r3, [r7, #4] 80075b2: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 80075b6: 2b01 cmp r3, #1 80075b8: d101 bne.n 80075be 80075ba: 2302 movs r3, #2 80075bc: e0be b.n 800773c 80075be: 687b ldr r3, [r7, #4] 80075c0: 2201 movs r2, #1 80075c2: f883 2050 strb.w r2, [r3, #80] @ 0x50 tmphadcSlave.State = HAL_ADC_STATE_RESET; 80075c6: 2300 movs r3, #0 80075c8: 65fb str r3, [r7, #92] @ 0x5c tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; 80075ca: 2300 movs r3, #0 80075cc: 663b str r3, [r7, #96] @ 0x60 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 80075ce: 687b ldr r3, [r7, #4] 80075d0: 681b ldr r3, [r3, #0] 80075d2: 4a5c ldr r2, [pc, #368] @ (8007744 ) 80075d4: 4293 cmp r3, r2 80075d6: d102 bne.n 80075de 80075d8: 4b5b ldr r3, [pc, #364] @ (8007748 ) 80075da: 60bb str r3, [r7, #8] 80075dc: e001 b.n 80075e2 80075de: 2300 movs r3, #0 80075e0: 60bb str r3, [r7, #8] if (tmphadcSlave.Instance == NULL) 80075e2: 68bb ldr r3, [r7, #8] 80075e4: 2b00 cmp r3, #0 80075e6: d10b bne.n 8007600 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80075e8: 687b ldr r3, [r7, #4] 80075ea: 6d5b ldr r3, [r3, #84] @ 0x54 80075ec: f043 0220 orr.w r2, r3, #32 80075f0: 687b ldr r3, [r7, #4] 80075f2: 655a str r2, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hadc); 80075f4: 687b ldr r3, [r7, #4] 80075f6: 2200 movs r2, #0 80075f8: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 80075fc: 2301 movs r3, #1 80075fe: e09d b.n 800773c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DATA Format configuration */ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); 8007600: 68bb ldr r3, [r7, #8] 8007602: 4618 mov r0, r3 8007604: f7ff ff54 bl 80074b0 8007608: 6738 str r0, [r7, #112] @ 0x70 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 800760a: 687b ldr r3, [r7, #4] 800760c: 681b ldr r3, [r3, #0] 800760e: 4618 mov r0, r3 8007610: f7ff ff4e bl 80074b0 8007614: 4603 mov r3, r0 8007616: 2b00 cmp r3, #0 8007618: d17f bne.n 800771a && (tmphadcSlave_conversion_on_going == 0UL)) 800761a: 6f3b ldr r3, [r7, #112] @ 0x70 800761c: 2b00 cmp r3, #0 800761e: d17c bne.n 800771a { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); 8007620: 687b ldr r3, [r7, #4] 8007622: 681b ldr r3, [r3, #0] 8007624: 4a47 ldr r2, [pc, #284] @ (8007744 ) 8007626: 4293 cmp r3, r2 8007628: d004 beq.n 8007634 800762a: 687b ldr r3, [r7, #4] 800762c: 681b ldr r3, [r3, #0] 800762e: 4a46 ldr r2, [pc, #280] @ (8007748 ) 8007630: 4293 cmp r3, r2 8007632: d101 bne.n 8007638 8007634: 4b45 ldr r3, [pc, #276] @ (800774c ) 8007636: e000 b.n 800763a 8007638: 4b45 ldr r3, [pc, #276] @ (8007750 ) 800763a: 66fb str r3, [r7, #108] @ 0x6c /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if (multimode->Mode != ADC_MODE_INDEPENDENT) 800763c: 683b ldr r3, [r7, #0] 800763e: 681b ldr r3, [r3, #0] 8007640: 2b00 cmp r3, #0 8007642: d039 beq.n 80076b8 { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData); 8007644: 6efb ldr r3, [r7, #108] @ 0x6c 8007646: 689b ldr r3, [r3, #8] 8007648: f423 4240 bic.w r2, r3, #49152 @ 0xc000 800764c: 683b ldr r3, [r7, #0] 800764e: 685b ldr r3, [r3, #4] 8007650: 431a orrs r2, r3 8007652: 6efb ldr r3, [r7, #108] @ 0x6c 8007654: 609a str r2, [r3, #8] /* from 1 to 8 clock cycles for 12 bits */ /* from 1 to 6 clock cycles for 10 and 8 bits */ /* If a higher delay is selected, it will be clipped to maximum delay */ /* range */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8007656: 687b ldr r3, [r7, #4] 8007658: 681b ldr r3, [r3, #0] 800765a: 4a3a ldr r2, [pc, #232] @ (8007744 ) 800765c: 4293 cmp r3, r2 800765e: d004 beq.n 800766a 8007660: 687b ldr r3, [r7, #4] 8007662: 681b ldr r3, [r3, #0] 8007664: 4a38 ldr r2, [pc, #224] @ (8007748 ) 8007666: 4293 cmp r3, r2 8007668: d10e bne.n 8007688 800766a: 4836 ldr r0, [pc, #216] @ (8007744 ) 800766c: f7ff feda bl 8007424 8007670: 4604 mov r4, r0 8007672: 4835 ldr r0, [pc, #212] @ (8007748 ) 8007674: f7ff fed6 bl 8007424 8007678: 4603 mov r3, r0 800767a: 4323 orrs r3, r4 800767c: 2b00 cmp r3, #0 800767e: bf0c ite eq 8007680: 2301 moveq r3, #1 8007682: 2300 movne r3, #0 8007684: b2db uxtb r3, r3 8007686: e008 b.n 800769a 8007688: 4832 ldr r0, [pc, #200] @ (8007754 ) 800768a: f7ff fecb bl 8007424 800768e: 4603 mov r3, r0 8007690: 2b00 cmp r3, #0 8007692: bf0c ite eq 8007694: 2301 moveq r3, #1 8007696: 2300 movne r3, #0 8007698: b2db uxtb r3, r3 800769a: 2b00 cmp r3, #0 800769c: d047 beq.n 800772e { MODIFY_REG(tmpADC_Common->CCR, 800769e: 6efb ldr r3, [r7, #108] @ 0x6c 80076a0: 689a ldr r2, [r3, #8] 80076a2: 4b2d ldr r3, [pc, #180] @ (8007758 ) 80076a4: 4013 ands r3, r2 80076a6: 683a ldr r2, [r7, #0] 80076a8: 6811 ldr r1, [r2, #0] 80076aa: 683a ldr r2, [r7, #0] 80076ac: 6892 ldr r2, [r2, #8] 80076ae: 430a orrs r2, r1 80076b0: 431a orrs r2, r3 80076b2: 6efb ldr r3, [r7, #108] @ 0x6c 80076b4: 609a str r2, [r3, #8] if (multimode->Mode != ADC_MODE_INDEPENDENT) 80076b6: e03a b.n 800772e ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF); 80076b8: 6efb ldr r3, [r7, #108] @ 0x6c 80076ba: 689b ldr r3, [r3, #8] 80076bc: f423 4240 bic.w r2, r3, #49152 @ 0xc000 80076c0: 6efb ldr r3, [r7, #108] @ 0x6c 80076c2: 609a str r2, [r3, #8] /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 80076c4: 687b ldr r3, [r7, #4] 80076c6: 681b ldr r3, [r3, #0] 80076c8: 4a1e ldr r2, [pc, #120] @ (8007744 ) 80076ca: 4293 cmp r3, r2 80076cc: d004 beq.n 80076d8 80076ce: 687b ldr r3, [r7, #4] 80076d0: 681b ldr r3, [r3, #0] 80076d2: 4a1d ldr r2, [pc, #116] @ (8007748 ) 80076d4: 4293 cmp r3, r2 80076d6: d10e bne.n 80076f6 80076d8: 481a ldr r0, [pc, #104] @ (8007744 ) 80076da: f7ff fea3 bl 8007424 80076de: 4604 mov r4, r0 80076e0: 4819 ldr r0, [pc, #100] @ (8007748 ) 80076e2: f7ff fe9f bl 8007424 80076e6: 4603 mov r3, r0 80076e8: 4323 orrs r3, r4 80076ea: 2b00 cmp r3, #0 80076ec: bf0c ite eq 80076ee: 2301 moveq r3, #1 80076f0: 2300 movne r3, #0 80076f2: b2db uxtb r3, r3 80076f4: e008 b.n 8007708 80076f6: 4817 ldr r0, [pc, #92] @ (8007754 ) 80076f8: f7ff fe94 bl 8007424 80076fc: 4603 mov r3, r0 80076fe: 2b00 cmp r3, #0 8007700: bf0c ite eq 8007702: 2301 moveq r3, #1 8007704: 2300 movne r3, #0 8007706: b2db uxtb r3, r3 8007708: 2b00 cmp r3, #0 800770a: d010 beq.n 800772e { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); 800770c: 6efb ldr r3, [r7, #108] @ 0x6c 800770e: 689a ldr r2, [r3, #8] 8007710: 4b11 ldr r3, [pc, #68] @ (8007758 ) 8007712: 4013 ands r3, r2 8007714: 6efa ldr r2, [r7, #108] @ 0x6c 8007716: 6093 str r3, [r2, #8] if (multimode->Mode != ADC_MODE_INDEPENDENT) 8007718: e009 b.n 800772e /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800771a: 687b ldr r3, [r7, #4] 800771c: 6d5b ldr r3, [r3, #84] @ 0x54 800771e: f043 0220 orr.w r2, r3, #32 8007722: 687b ldr r3, [r7, #4] 8007724: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8007726: 2301 movs r3, #1 8007728: f887 3077 strb.w r3, [r7, #119] @ 0x77 800772c: e000 b.n 8007730 if (multimode->Mode != ADC_MODE_INDEPENDENT) 800772e: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); 8007730: 687b ldr r3, [r7, #4] 8007732: 2200 movs r2, #0 8007734: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 8007738: f897 3077 ldrb.w r3, [r7, #119] @ 0x77 } 800773c: 4618 mov r0, r3 800773e: 377c adds r7, #124 @ 0x7c 8007740: 46bd mov sp, r7 8007742: bd90 pop {r4, r7, pc} 8007744: 40022000 .word 0x40022000 8007748: 40022100 .word 0x40022100 800774c: 40022300 .word 0x40022300 8007750: 58026300 .word 0x58026300 8007754: 58026000 .word 0x58026000 8007758: fffff0e0 .word 0xfffff0e0 0800775c : * To unlock the configuration, perform a system reset. * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { 800775c: b580 push {r7, lr} 800775e: b088 sub sp, #32 8007760: af00 add r7, sp, #0 8007762: 6078 str r0, [r7, #4] uint32_t tmp_csr ; uint32_t exti_line ; uint32_t comp_voltage_scaler_initialized; /* Value "0" is comparator voltage scaler is not initialized */ __IO uint32_t wait_loop_index = 0UL; 8007764: 2300 movs r3, #0 8007766: 60fb str r3, [r7, #12] HAL_StatusTypeDef status = HAL_OK; 8007768: 2300 movs r3, #0 800776a: 77fb strb r3, [r7, #31] /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) 800776c: 687b ldr r3, [r7, #4] 800776e: 2b00 cmp r3, #0 8007770: d102 bne.n 8007778 { status = HAL_ERROR; 8007772: 2301 movs r3, #1 8007774: 77fb strb r3, [r7, #31] 8007776: e10e b.n 8007996 } else if(__HAL_COMP_IS_LOCKED(hcomp)) 8007778: 687b ldr r3, [r7, #4] 800777a: 681b ldr r3, [r3, #0] 800777c: 681b ldr r3, [r3, #0] 800777e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007782: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007786: d102 bne.n 800778e { status = HAL_ERROR; 8007788: 2301 movs r3, #1 800778a: 77fb strb r3, [r7, #31] 800778c: e103 b.n 8007996 assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); if(hcomp->State == HAL_COMP_STATE_RESET) 800778e: 687b ldr r3, [r7, #4] 8007790: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8007794: b2db uxtb r3, r3 8007796: 2b00 cmp r3, #0 8007798: d109 bne.n 80077ae { /* Allocate lock resource and initialize it */ hcomp->Lock = HAL_UNLOCKED; 800779a: 687b ldr r3, [r7, #4] 800779c: 2200 movs r2, #0 800779e: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Set COMP error code to none */ COMP_CLEAR_ERRORCODE(hcomp); 80077a2: 687b ldr r3, [r7, #4] 80077a4: 2200 movs r2, #0 80077a6: 629a str r2, [r3, #40] @ 0x28 /* Init the low level hardware */ hcomp->MspInitCallback(hcomp); #else /* Init the low level hardware */ HAL_COMP_MspInit(hcomp); 80077a8: 6878 ldr r0, [r7, #4] 80077aa: f7fc fca9 bl 8004100 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } /* Memorize voltage scaler state before initialization */ comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN); 80077ae: 687b ldr r3, [r7, #4] 80077b0: 681b ldr r3, [r3, #0] 80077b2: 681b ldr r3, [r3, #0] 80077b4: f003 0304 and.w r3, r3, #4 80077b8: 61bb str r3, [r7, #24] /* Set BLANKING bits according to hcomp->Init.BlankingSrce value */ /* Set HYST bits according to hcomp->Init.Hysteresis value */ /* Set POLARITY bit according to hcomp->Init.OutputPol value */ /* Set POWERMODE bits according to hcomp->Init.Mode value */ tmp_csr = (hcomp->Init.InvertingInput | \ 80077ba: 687b ldr r3, [r7, #4] 80077bc: 691a ldr r2, [r3, #16] hcomp->Init.NonInvertingInput | \ 80077be: 687b ldr r3, [r7, #4] 80077c0: 68db ldr r3, [r3, #12] tmp_csr = (hcomp->Init.InvertingInput | \ 80077c2: 431a orrs r2, r3 hcomp->Init.BlankingSrce | \ 80077c4: 687b ldr r3, [r7, #4] 80077c6: 69db ldr r3, [r3, #28] hcomp->Init.NonInvertingInput | \ 80077c8: 431a orrs r2, r3 hcomp->Init.Hysteresis | \ 80077ca: 687b ldr r3, [r7, #4] 80077cc: 695b ldr r3, [r3, #20] hcomp->Init.BlankingSrce | \ 80077ce: 431a orrs r2, r3 hcomp->Init.OutputPol | \ 80077d0: 687b ldr r3, [r7, #4] 80077d2: 699b ldr r3, [r3, #24] hcomp->Init.Hysteresis | \ 80077d4: 431a orrs r2, r3 hcomp->Init.Mode ); 80077d6: 687b ldr r3, [r7, #4] 80077d8: 689b ldr r3, [r3, #8] tmp_csr = (hcomp->Init.InvertingInput | \ 80077da: 4313 orrs r3, r2 80077dc: 617b str r3, [r7, #20] COMP_CFGRx_INP2SEL | COMP_CFGRx_WINMODE | COMP_CFGRx_POLARITY | COMP_CFGRx_HYST | COMP_CFGRx_BLANKING | COMP_CFGRx_BRGEN | COMP_CFGRx_SCALEN, tmp_csr ); #else MODIFY_REG(hcomp->Instance->CFGR, 80077de: 687b ldr r3, [r7, #4] 80077e0: 681b ldr r3, [r3, #0] 80077e2: 681a ldr r2, [r3, #0] 80077e4: 4b6e ldr r3, [pc, #440] @ (80079a0 ) 80077e6: 4013 ands r3, r2 80077e8: 687a ldr r2, [r7, #4] 80077ea: 6812 ldr r2, [r2, #0] 80077ec: 6979 ldr r1, [r7, #20] 80077ee: 430b orrs r3, r1 80077f0: 6013 str r3, [r2, #0] #endif /* Set window mode */ /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ /* instances. Therefore, this function can update another COMP */ /* instance that the one currently selected. */ if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) 80077f2: 687b ldr r3, [r7, #4] 80077f4: 685b ldr r3, [r3, #4] 80077f6: 2b10 cmp r3, #16 80077f8: d108 bne.n 800780c { SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE); 80077fa: 687b ldr r3, [r7, #4] 80077fc: 681b ldr r3, [r3, #0] 80077fe: 681a ldr r2, [r3, #0] 8007800: 687b ldr r3, [r7, #4] 8007802: 681b ldr r3, [r3, #0] 8007804: f042 0210 orr.w r2, r2, #16 8007808: 601a str r2, [r3, #0] 800780a: e007 b.n 800781c } else { CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE); 800780c: 687b ldr r3, [r7, #4] 800780e: 681b ldr r3, [r3, #0] 8007810: 681a ldr r2, [r3, #0] 8007812: 687b ldr r3, [r7, #4] 8007814: 681b ldr r3, [r3, #0] 8007816: f022 0210 bic.w r2, r2, #16 800781a: 601a str r2, [r3, #0] } /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is enabled for the first time */ if ((READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN) != 0UL) && 800781c: 687b ldr r3, [r7, #4] 800781e: 681b ldr r3, [r3, #0] 8007820: 681b ldr r3, [r3, #0] 8007822: f003 0304 and.w r3, r3, #4 8007826: 2b00 cmp r3, #0 8007828: d016 beq.n 8007858 800782a: 69bb ldr r3, [r7, #24] 800782c: 2b00 cmp r3, #0 800782e: d013 beq.n 8007858 { /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles.*/ wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8007830: 4b5c ldr r3, [pc, #368] @ (80079a4 ) 8007832: 681b ldr r3, [r3, #0] 8007834: 099b lsrs r3, r3, #6 8007836: 4a5c ldr r2, [pc, #368] @ (80079a8 ) 8007838: fba2 2303 umull r2, r3, r2, r3 800783c: 099b lsrs r3, r3, #6 800783e: 1c5a adds r2, r3, #1 8007840: 4613 mov r3, r2 8007842: 009b lsls r3, r3, #2 8007844: 4413 add r3, r2 8007846: 009b lsls r3, r3, #2 8007848: 60fb str r3, [r7, #12] while(wait_loop_index != 0UL) 800784a: e002 b.n 8007852 { wait_loop_index --; 800784c: 68fb ldr r3, [r7, #12] 800784e: 3b01 subs r3, #1 8007850: 60fb str r3, [r7, #12] while(wait_loop_index != 0UL) 8007852: 68fb ldr r3, [r7, #12] 8007854: 2b00 cmp r3, #0 8007856: d1f9 bne.n 800784c } } /* Get the EXTI line corresponding to the selected COMP instance */ exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); 8007858: 687b ldr r3, [r7, #4] 800785a: 681b ldr r3, [r3, #0] 800785c: 4a53 ldr r2, [pc, #332] @ (80079ac ) 800785e: 4293 cmp r3, r2 8007860: d102 bne.n 8007868 8007862: f44f 1380 mov.w r3, #1048576 @ 0x100000 8007866: e001 b.n 800786c 8007868: f44f 1300 mov.w r3, #2097152 @ 0x200000 800786c: 613b str r3, [r7, #16] /* Manage EXTI settings */ if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) 800786e: 687b ldr r3, [r7, #4] 8007870: 6a1b ldr r3, [r3, #32] 8007872: f003 0303 and.w r3, r3, #3 8007876: 2b00 cmp r3, #0 8007878: d06d beq.n 8007956 { /* Configure EXTI rising edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) 800787a: 687b ldr r3, [r7, #4] 800787c: 6a1b ldr r3, [r3, #32] 800787e: f003 0310 and.w r3, r3, #16 8007882: 2b00 cmp r3, #0 8007884: d008 beq.n 8007898 { SET_BIT(EXTI->RTSR1, exti_line); 8007886: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800788a: 681a ldr r2, [r3, #0] 800788c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007890: 693b ldr r3, [r7, #16] 8007892: 4313 orrs r3, r2 8007894: 600b str r3, [r1, #0] 8007896: e008 b.n 80078aa } else { CLEAR_BIT(EXTI->RTSR1, exti_line); 8007898: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800789c: 681a ldr r2, [r3, #0] 800789e: 693b ldr r3, [r7, #16] 80078a0: 43db mvns r3, r3 80078a2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80078a6: 4013 ands r3, r2 80078a8: 600b str r3, [r1, #0] } /* Configure EXTI falling edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) 80078aa: 687b ldr r3, [r7, #4] 80078ac: 6a1b ldr r3, [r3, #32] 80078ae: f003 0320 and.w r3, r3, #32 80078b2: 2b00 cmp r3, #0 80078b4: d008 beq.n 80078c8 { SET_BIT(EXTI->FTSR1, exti_line); 80078b6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80078ba: 685a ldr r2, [r3, #4] 80078bc: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80078c0: 693b ldr r3, [r7, #16] 80078c2: 4313 orrs r3, r2 80078c4: 604b str r3, [r1, #4] 80078c6: e008 b.n 80078da } else { CLEAR_BIT(EXTI->FTSR1, exti_line); 80078c8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80078cc: 685a ldr r2, [r3, #4] 80078ce: 693b ldr r3, [r7, #16] 80078d0: 43db mvns r3, r3 80078d2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80078d6: 4013 ands r3, r2 80078d8: 604b str r3, [r1, #4] } #if !defined (CORE_CM4) /* Clear COMP EXTI pending bit (if any) */ WRITE_REG(EXTI->PR1, exti_line); 80078da: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 80078de: 693b ldr r3, [r7, #16] 80078e0: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure EXTI event mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) 80078e4: 687b ldr r3, [r7, #4] 80078e6: 6a1b ldr r3, [r3, #32] 80078e8: f003 0302 and.w r3, r3, #2 80078ec: 2b00 cmp r3, #0 80078ee: d00a beq.n 8007906 { SET_BIT(EXTI->EMR1, exti_line); 80078f0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80078f4: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 80078f8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80078fc: 693b ldr r3, [r7, #16] 80078fe: 4313 orrs r3, r2 8007900: f8c1 3084 str.w r3, [r1, #132] @ 0x84 8007904: e00a b.n 800791c } else { CLEAR_BIT(EXTI->EMR1, exti_line); 8007906: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800790a: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 800790e: 693b ldr r3, [r7, #16] 8007910: 43db mvns r3, r3 8007912: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007916: 4013 ands r3, r2 8007918: f8c1 3084 str.w r3, [r1, #132] @ 0x84 } /* Configure EXTI interrupt mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) 800791c: 687b ldr r3, [r7, #4] 800791e: 6a1b ldr r3, [r3, #32] 8007920: f003 0301 and.w r3, r3, #1 8007924: 2b00 cmp r3, #0 8007926: d00a beq.n 800793e { SET_BIT(EXTI->IMR1, exti_line); 8007928: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800792c: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 8007930: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007934: 693b ldr r3, [r7, #16] 8007936: 4313 orrs r3, r2 8007938: f8c1 3080 str.w r3, [r1, #128] @ 0x80 800793c: e021 b.n 8007982 } else { CLEAR_BIT(EXTI->IMR1, exti_line); 800793e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007942: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 8007946: 693b ldr r3, [r7, #16] 8007948: 43db mvns r3, r3 800794a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800794e: 4013 ands r3, r2 8007950: f8c1 3080 str.w r3, [r1, #128] @ 0x80 8007954: e015 b.n 8007982 } } else { /* Disable EXTI event mode */ CLEAR_BIT(EXTI->EMR1, exti_line); 8007956: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800795a: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 800795e: 693b ldr r3, [r7, #16] 8007960: 43db mvns r3, r3 8007962: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007966: 4013 ands r3, r2 8007968: f8c1 3084 str.w r3, [r1, #132] @ 0x84 /* Disable EXTI interrupt mode */ CLEAR_BIT(EXTI->IMR1, exti_line); 800796c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007970: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 8007974: 693b ldr r3, [r7, #16] 8007976: 43db mvns r3, r3 8007978: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800797c: 4013 ands r3, r2 800797e: f8c1 3080 str.w r3, [r1, #128] @ 0x80 } #endif /* Set HAL COMP handle state */ /* Note: Transition from state reset to state ready, */ /* otherwise (coming from state ready or busy) no state update. */ if (hcomp->State == HAL_COMP_STATE_RESET) 8007982: 687b ldr r3, [r7, #4] 8007984: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8007988: b2db uxtb r3, r3 800798a: 2b00 cmp r3, #0 800798c: d103 bne.n 8007996 { hcomp->State = HAL_COMP_STATE_READY; 800798e: 687b ldr r3, [r7, #4] 8007990: 2201 movs r2, #1 8007992: f883 2025 strb.w r2, [r3, #37] @ 0x25 } } return status; 8007996: 7ffb ldrb r3, [r7, #31] } 8007998: 4618 mov r0, r3 800799a: 3720 adds r7, #32 800799c: 46bd mov sp, r7 800799e: bd80 pop {r7, pc} 80079a0: f0e8cce1 .word 0xf0e8cce1 80079a4: 24000034 .word 0x24000034 80079a8: 053e2d63 .word 0x053e2d63 80079ac: 5800380c .word 0x5800380c 080079b0 : * @brief Start the comparator. * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { 80079b0: b480 push {r7} 80079b2: b085 sub sp, #20 80079b4: af00 add r7, sp, #0 80079b6: 6078 str r0, [r7, #4] __IO uint32_t wait_loop_index = 0UL; 80079b8: 2300 movs r3, #0 80079ba: 60bb str r3, [r7, #8] HAL_StatusTypeDef status = HAL_OK; 80079bc: 2300 movs r3, #0 80079be: 73fb strb r3, [r7, #15] /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) 80079c0: 687b ldr r3, [r7, #4] 80079c2: 2b00 cmp r3, #0 80079c4: d102 bne.n 80079cc { status = HAL_ERROR; 80079c6: 2301 movs r3, #1 80079c8: 73fb strb r3, [r7, #15] 80079ca: e030 b.n 8007a2e } else if(__HAL_COMP_IS_LOCKED(hcomp)) 80079cc: 687b ldr r3, [r7, #4] 80079ce: 681b ldr r3, [r3, #0] 80079d0: 681b ldr r3, [r3, #0] 80079d2: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80079d6: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80079da: d102 bne.n 80079e2 { status = HAL_ERROR; 80079dc: 2301 movs r3, #1 80079de: 73fb strb r3, [r7, #15] 80079e0: e025 b.n 8007a2e else { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); if(hcomp->State == HAL_COMP_STATE_READY) 80079e2: 687b ldr r3, [r7, #4] 80079e4: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 80079e8: b2db uxtb r3, r3 80079ea: 2b01 cmp r3, #1 80079ec: d11d bne.n 8007a2a { /* Enable the selected comparator */ SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN); 80079ee: 687b ldr r3, [r7, #4] 80079f0: 681b ldr r3, [r3, #0] 80079f2: 681a ldr r2, [r3, #0] 80079f4: 687b ldr r3, [r7, #4] 80079f6: 681b ldr r3, [r3, #0] 80079f8: f042 0201 orr.w r2, r2, #1 80079fc: 601a str r2, [r3, #0] /* Set HAL COMP handle state */ hcomp->State = HAL_COMP_STATE_BUSY; 80079fe: 687b ldr r3, [r7, #4] 8007a00: 2202 movs r2, #2 8007a02: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Delay for COMP startup time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8007a06: 4b0d ldr r3, [pc, #52] @ (8007a3c ) 8007a08: 681b ldr r3, [r3, #0] 8007a0a: 099b lsrs r3, r3, #6 8007a0c: 4a0c ldr r2, [pc, #48] @ (8007a40 ) 8007a0e: fba2 2303 umull r2, r3, r2, r3 8007a12: 099b lsrs r3, r3, #6 8007a14: 3301 adds r3, #1 8007a16: 00db lsls r3, r3, #3 8007a18: 60bb str r3, [r7, #8] while(wait_loop_index != 0UL) 8007a1a: e002 b.n 8007a22 { wait_loop_index--; 8007a1c: 68bb ldr r3, [r7, #8] 8007a1e: 3b01 subs r3, #1 8007a20: 60bb str r3, [r7, #8] while(wait_loop_index != 0UL) 8007a22: 68bb ldr r3, [r7, #8] 8007a24: 2b00 cmp r3, #0 8007a26: d1f9 bne.n 8007a1c 8007a28: e001 b.n 8007a2e } } else { status = HAL_ERROR; 8007a2a: 2301 movs r3, #1 8007a2c: 73fb strb r3, [r7, #15] } } return status; 8007a2e: 7bfb ldrb r3, [r7, #15] } 8007a30: 4618 mov r0, r3 8007a32: 3714 adds r7, #20 8007a34: 46bd mov sp, r7 8007a36: f85d 7b04 ldr.w r7, [sp], #4 8007a3a: 4770 bx lr 8007a3c: 24000034 .word 0x24000034 8007a40: 053e2d63 .word 0x053e2d63 08007a44 : * @arg @ref COMP_OUTPUT_LEVEL_LOW * @arg @ref COMP_OUTPUT_LEVEL_HIGH * */ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) { 8007a44: b480 push {r7} 8007a46: b083 sub sp, #12 8007a48: af00 add r7, sp, #0 8007a4a: 6078 str r0, [r7, #4] /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); if (hcomp->Instance == COMP1) 8007a4c: 687b ldr r3, [r7, #4] 8007a4e: 681b ldr r3, [r3, #0] 8007a50: 4a09 ldr r2, [pc, #36] @ (8007a78 ) 8007a52: 4293 cmp r3, r2 8007a54: d104 bne.n 8007a60 { return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL)); 8007a56: 4b09 ldr r3, [pc, #36] @ (8007a7c ) 8007a58: 681b ldr r3, [r3, #0] 8007a5a: f003 0301 and.w r3, r3, #1 8007a5e: e004 b.n 8007a6a } else { return (uint32_t)((READ_BIT(COMP12->SR, COMP_SR_C2VAL))>> 1UL); 8007a60: 4b06 ldr r3, [pc, #24] @ (8007a7c ) 8007a62: 681b ldr r3, [r3, #0] 8007a64: 085b lsrs r3, r3, #1 8007a66: f003 0301 and.w r3, r3, #1 } } 8007a6a: 4618 mov r0, r3 8007a6c: 370c adds r7, #12 8007a6e: 46bd mov sp, r7 8007a70: f85d 7b04 ldr.w r7, [sp], #4 8007a74: 4770 bx lr 8007a76: bf00 nop 8007a78: 5800380c .word 0x5800380c 8007a7c: 58003800 .word 0x58003800 08007a80 <__NVIC_SetPriorityGrouping>: { 8007a80: b480 push {r7} 8007a82: b085 sub sp, #20 8007a84: af00 add r7, sp, #0 8007a86: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8007a88: 687b ldr r3, [r7, #4] 8007a8a: f003 0307 and.w r3, r3, #7 8007a8e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8007a90: 4b0b ldr r3, [pc, #44] @ (8007ac0 <__NVIC_SetPriorityGrouping+0x40>) 8007a92: 68db ldr r3, [r3, #12] 8007a94: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8007a96: 68ba ldr r2, [r7, #8] 8007a98: f64f 03ff movw r3, #63743 @ 0xf8ff 8007a9c: 4013 ands r3, r2 8007a9e: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8007aa0: 68fb ldr r3, [r7, #12] 8007aa2: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8007aa4: 68bb ldr r3, [r7, #8] 8007aa6: 431a orrs r2, r3 reg_value = (reg_value | 8007aa8: 4b06 ldr r3, [pc, #24] @ (8007ac4 <__NVIC_SetPriorityGrouping+0x44>) 8007aaa: 4313 orrs r3, r2 8007aac: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8007aae: 4a04 ldr r2, [pc, #16] @ (8007ac0 <__NVIC_SetPriorityGrouping+0x40>) 8007ab0: 68bb ldr r3, [r7, #8] 8007ab2: 60d3 str r3, [r2, #12] } 8007ab4: bf00 nop 8007ab6: 3714 adds r7, #20 8007ab8: 46bd mov sp, r7 8007aba: f85d 7b04 ldr.w r7, [sp], #4 8007abe: 4770 bx lr 8007ac0: e000ed00 .word 0xe000ed00 8007ac4: 05fa0000 .word 0x05fa0000 08007ac8 <__NVIC_GetPriorityGrouping>: { 8007ac8: b480 push {r7} 8007aca: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8007acc: 4b04 ldr r3, [pc, #16] @ (8007ae0 <__NVIC_GetPriorityGrouping+0x18>) 8007ace: 68db ldr r3, [r3, #12] 8007ad0: 0a1b lsrs r3, r3, #8 8007ad2: f003 0307 and.w r3, r3, #7 } 8007ad6: 4618 mov r0, r3 8007ad8: 46bd mov sp, r7 8007ada: f85d 7b04 ldr.w r7, [sp], #4 8007ade: 4770 bx lr 8007ae0: e000ed00 .word 0xe000ed00 08007ae4 <__NVIC_EnableIRQ>: { 8007ae4: b480 push {r7} 8007ae6: b083 sub sp, #12 8007ae8: af00 add r7, sp, #0 8007aea: 4603 mov r3, r0 8007aec: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8007aee: f9b7 3006 ldrsh.w r3, [r7, #6] 8007af2: 2b00 cmp r3, #0 8007af4: db0b blt.n 8007b0e <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8007af6: 88fb ldrh r3, [r7, #6] 8007af8: f003 021f and.w r2, r3, #31 8007afc: 4907 ldr r1, [pc, #28] @ (8007b1c <__NVIC_EnableIRQ+0x38>) 8007afe: f9b7 3006 ldrsh.w r3, [r7, #6] 8007b02: 095b lsrs r3, r3, #5 8007b04: 2001 movs r0, #1 8007b06: fa00 f202 lsl.w r2, r0, r2 8007b0a: f841 2023 str.w r2, [r1, r3, lsl #2] } 8007b0e: bf00 nop 8007b10: 370c adds r7, #12 8007b12: 46bd mov sp, r7 8007b14: f85d 7b04 ldr.w r7, [sp], #4 8007b18: 4770 bx lr 8007b1a: bf00 nop 8007b1c: e000e100 .word 0xe000e100 08007b20 <__NVIC_SetPriority>: { 8007b20: b480 push {r7} 8007b22: b083 sub sp, #12 8007b24: af00 add r7, sp, #0 8007b26: 4603 mov r3, r0 8007b28: 6039 str r1, [r7, #0] 8007b2a: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8007b2c: f9b7 3006 ldrsh.w r3, [r7, #6] 8007b30: 2b00 cmp r3, #0 8007b32: db0a blt.n 8007b4a <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8007b34: 683b ldr r3, [r7, #0] 8007b36: b2da uxtb r2, r3 8007b38: 490c ldr r1, [pc, #48] @ (8007b6c <__NVIC_SetPriority+0x4c>) 8007b3a: f9b7 3006 ldrsh.w r3, [r7, #6] 8007b3e: 0112 lsls r2, r2, #4 8007b40: b2d2 uxtb r2, r2 8007b42: 440b add r3, r1 8007b44: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 8007b48: e00a b.n 8007b60 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8007b4a: 683b ldr r3, [r7, #0] 8007b4c: b2da uxtb r2, r3 8007b4e: 4908 ldr r1, [pc, #32] @ (8007b70 <__NVIC_SetPriority+0x50>) 8007b50: 88fb ldrh r3, [r7, #6] 8007b52: f003 030f and.w r3, r3, #15 8007b56: 3b04 subs r3, #4 8007b58: 0112 lsls r2, r2, #4 8007b5a: b2d2 uxtb r2, r2 8007b5c: 440b add r3, r1 8007b5e: 761a strb r2, [r3, #24] } 8007b60: bf00 nop 8007b62: 370c adds r7, #12 8007b64: 46bd mov sp, r7 8007b66: f85d 7b04 ldr.w r7, [sp], #4 8007b6a: 4770 bx lr 8007b6c: e000e100 .word 0xe000e100 8007b70: e000ed00 .word 0xe000ed00 08007b74 : { 8007b74: b480 push {r7} 8007b76: b089 sub sp, #36 @ 0x24 8007b78: af00 add r7, sp, #0 8007b7a: 60f8 str r0, [r7, #12] 8007b7c: 60b9 str r1, [r7, #8] 8007b7e: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8007b80: 68fb ldr r3, [r7, #12] 8007b82: f003 0307 and.w r3, r3, #7 8007b86: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8007b88: 69fb ldr r3, [r7, #28] 8007b8a: f1c3 0307 rsb r3, r3, #7 8007b8e: 2b04 cmp r3, #4 8007b90: bf28 it cs 8007b92: 2304 movcs r3, #4 8007b94: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8007b96: 69fb ldr r3, [r7, #28] 8007b98: 3304 adds r3, #4 8007b9a: 2b06 cmp r3, #6 8007b9c: d902 bls.n 8007ba4 8007b9e: 69fb ldr r3, [r7, #28] 8007ba0: 3b03 subs r3, #3 8007ba2: e000 b.n 8007ba6 8007ba4: 2300 movs r3, #0 8007ba6: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8007ba8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007bac: 69bb ldr r3, [r7, #24] 8007bae: fa02 f303 lsl.w r3, r2, r3 8007bb2: 43da mvns r2, r3 8007bb4: 68bb ldr r3, [r7, #8] 8007bb6: 401a ands r2, r3 8007bb8: 697b ldr r3, [r7, #20] 8007bba: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8007bbc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8007bc0: 697b ldr r3, [r7, #20] 8007bc2: fa01 f303 lsl.w r3, r1, r3 8007bc6: 43d9 mvns r1, r3 8007bc8: 687b ldr r3, [r7, #4] 8007bca: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8007bcc: 4313 orrs r3, r2 } 8007bce: 4618 mov r0, r3 8007bd0: 3724 adds r7, #36 @ 0x24 8007bd2: 46bd mov sp, r7 8007bd4: f85d 7b04 ldr.w r7, [sp], #4 8007bd8: 4770 bx lr 08007bda : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8007bda: b580 push {r7, lr} 8007bdc: b082 sub sp, #8 8007bde: af00 add r7, sp, #0 8007be0: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8007be2: 6878 ldr r0, [r7, #4] 8007be4: f7ff ff4c bl 8007a80 <__NVIC_SetPriorityGrouping> } 8007be8: bf00 nop 8007bea: 3708 adds r7, #8 8007bec: 46bd mov sp, r7 8007bee: bd80 pop {r7, pc} 08007bf0 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8007bf0: b580 push {r7, lr} 8007bf2: b086 sub sp, #24 8007bf4: af00 add r7, sp, #0 8007bf6: 4603 mov r3, r0 8007bf8: 60b9 str r1, [r7, #8] 8007bfa: 607a str r2, [r7, #4] 8007bfc: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8007bfe: f7ff ff63 bl 8007ac8 <__NVIC_GetPriorityGrouping> 8007c02: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8007c04: 687a ldr r2, [r7, #4] 8007c06: 68b9 ldr r1, [r7, #8] 8007c08: 6978 ldr r0, [r7, #20] 8007c0a: f7ff ffb3 bl 8007b74 8007c0e: 4602 mov r2, r0 8007c10: f9b7 300e ldrsh.w r3, [r7, #14] 8007c14: 4611 mov r1, r2 8007c16: 4618 mov r0, r3 8007c18: f7ff ff82 bl 8007b20 <__NVIC_SetPriority> } 8007c1c: bf00 nop 8007c1e: 3718 adds r7, #24 8007c20: 46bd mov sp, r7 8007c22: bd80 pop {r7, pc} 08007c24 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8007c24: b580 push {r7, lr} 8007c26: b082 sub sp, #8 8007c28: af00 add r7, sp, #0 8007c2a: 4603 mov r3, r0 8007c2c: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8007c2e: f9b7 3006 ldrsh.w r3, [r7, #6] 8007c32: 4618 mov r0, r3 8007c34: f7ff ff56 bl 8007ae4 <__NVIC_EnableIRQ> } 8007c38: bf00 nop 8007c3a: 3708 adds r7, #8 8007c3c: 46bd mov sp, r7 8007c3e: bd80 pop {r7, pc} 08007c40 : /** * @brief Disables the MPU * @retval None */ void HAL_MPU_Disable(void) { 8007c40: b480 push {r7} 8007c42: af00 add r7, sp, #0 __ASM volatile ("dmb 0xF":::"memory"); 8007c44: f3bf 8f5f dmb sy } 8007c48: bf00 nop /* Make sure outstanding transfers are done */ __DMB(); /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 8007c4a: 4b07 ldr r3, [pc, #28] @ (8007c68 ) 8007c4c: 6a5b ldr r3, [r3, #36] @ 0x24 8007c4e: 4a06 ldr r2, [pc, #24] @ (8007c68 ) 8007c50: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8007c54: 6253 str r3, [r2, #36] @ 0x24 /* Disable the MPU and clear the control register*/ MPU->CTRL = 0; 8007c56: 4b05 ldr r3, [pc, #20] @ (8007c6c ) 8007c58: 2200 movs r2, #0 8007c5a: 605a str r2, [r3, #4] } 8007c5c: bf00 nop 8007c5e: 46bd mov sp, r7 8007c60: f85d 7b04 ldr.w r7, [sp], #4 8007c64: 4770 bx lr 8007c66: bf00 nop 8007c68: e000ed00 .word 0xe000ed00 8007c6c: e000ed90 .word 0xe000ed90 08007c70 : * @arg MPU_PRIVILEGED_DEFAULT * @arg MPU_HFNMI_PRIVDEF * @retval None */ void HAL_MPU_Enable(uint32_t MPU_Control) { 8007c70: b480 push {r7} 8007c72: b083 sub sp, #12 8007c74: af00 add r7, sp, #0 8007c76: 6078 str r0, [r7, #4] /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 8007c78: 4a0b ldr r2, [pc, #44] @ (8007ca8 ) 8007c7a: 687b ldr r3, [r7, #4] 8007c7c: f043 0301 orr.w r3, r3, #1 8007c80: 6053 str r3, [r2, #4] /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 8007c82: 4b0a ldr r3, [pc, #40] @ (8007cac ) 8007c84: 6a5b ldr r3, [r3, #36] @ 0x24 8007c86: 4a09 ldr r2, [pc, #36] @ (8007cac ) 8007c88: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8007c8c: 6253 str r3, [r2, #36] @ 0x24 __ASM volatile ("dsb 0xF":::"memory"); 8007c8e: f3bf 8f4f dsb sy } 8007c92: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8007c94: f3bf 8f6f isb sy } 8007c98: bf00 nop /* Ensure MPU setting take effects */ __DSB(); __ISB(); } 8007c9a: bf00 nop 8007c9c: 370c adds r7, #12 8007c9e: 46bd mov sp, r7 8007ca0: f85d 7b04 ldr.w r7, [sp], #4 8007ca4: 4770 bx lr 8007ca6: bf00 nop 8007ca8: e000ed90 .word 0xe000ed90 8007cac: e000ed00 .word 0xe000ed00 08007cb0 : * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) { 8007cb0: b480 push {r7} 8007cb2: b083 sub sp, #12 8007cb4: af00 add r7, sp, #0 8007cb6: 6078 str r0, [r7, #4] assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; 8007cb8: 687b ldr r3, [r7, #4] 8007cba: 785a ldrb r2, [r3, #1] 8007cbc: 4b1b ldr r3, [pc, #108] @ (8007d2c ) 8007cbe: 609a str r2, [r3, #8] /* Disable the Region */ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 8007cc0: 4b1a ldr r3, [pc, #104] @ (8007d2c ) 8007cc2: 691b ldr r3, [r3, #16] 8007cc4: 4a19 ldr r2, [pc, #100] @ (8007d2c ) 8007cc6: f023 0301 bic.w r3, r3, #1 8007cca: 6113 str r3, [r2, #16] /* Apply configuration */ MPU->RBAR = MPU_Init->BaseAddress; 8007ccc: 4a17 ldr r2, [pc, #92] @ (8007d2c ) 8007cce: 687b ldr r3, [r7, #4] 8007cd0: 685b ldr r3, [r3, #4] 8007cd2: 60d3 str r3, [r2, #12] MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007cd4: 687b ldr r3, [r7, #4] 8007cd6: 7b1b ldrb r3, [r3, #12] 8007cd8: 071a lsls r2, r3, #28 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 8007cda: 687b ldr r3, [r7, #4] 8007cdc: 7adb ldrb r3, [r3, #11] 8007cde: 061b lsls r3, r3, #24 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007ce0: 431a orrs r2, r3 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 8007ce2: 687b ldr r3, [r7, #4] 8007ce4: 7a9b ldrb r3, [r3, #10] 8007ce6: 04db lsls r3, r3, #19 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 8007ce8: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8007cea: 687b ldr r3, [r7, #4] 8007cec: 7b5b ldrb r3, [r3, #13] 8007cee: 049b lsls r3, r3, #18 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 8007cf0: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 8007cf2: 687b ldr r3, [r7, #4] 8007cf4: 7b9b ldrb r3, [r3, #14] 8007cf6: 045b lsls r3, r3, #17 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8007cf8: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8007cfa: 687b ldr r3, [r7, #4] 8007cfc: 7bdb ldrb r3, [r3, #15] 8007cfe: 041b lsls r3, r3, #16 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 8007d00: 431a orrs r2, r3 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 8007d02: 687b ldr r3, [r7, #4] 8007d04: 7a5b ldrb r3, [r3, #9] 8007d06: 021b lsls r3, r3, #8 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8007d08: 431a orrs r2, r3 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8007d0a: 687b ldr r3, [r7, #4] 8007d0c: 7a1b ldrb r3, [r3, #8] 8007d0e: 005b lsls r3, r3, #1 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 8007d10: 4313 orrs r3, r2 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); 8007d12: 687a ldr r2, [r7, #4] 8007d14: 7812 ldrb r2, [r2, #0] 8007d16: 4611 mov r1, r2 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007d18: 4a04 ldr r2, [pc, #16] @ (8007d2c ) ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8007d1a: 430b orrs r3, r1 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007d1c: 6113 str r3, [r2, #16] } 8007d1e: bf00 nop 8007d20: 370c adds r7, #12 8007d22: 46bd mov sp, r7 8007d24: f85d 7b04 ldr.w r7, [sp], #4 8007d28: 4770 bx lr 8007d2a: bf00 nop 8007d2c: e000ed90 .word 0xe000ed90 08007d30 : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 8007d30: b580 push {r7, lr} 8007d32: b082 sub sp, #8 8007d34: af00 add r7, sp, #0 8007d36: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 8007d38: 687b ldr r3, [r7, #4] 8007d3a: 2b00 cmp r3, #0 8007d3c: d101 bne.n 8007d42 { return HAL_ERROR; 8007d3e: 2301 movs r3, #1 8007d40: e054 b.n 8007dec } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 8007d42: 687b ldr r3, [r7, #4] 8007d44: 7f5b ldrb r3, [r3, #29] 8007d46: b2db uxtb r3, r3 8007d48: 2b00 cmp r3, #0 8007d4a: d105 bne.n 8007d58 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 8007d4c: 687b ldr r3, [r7, #4] 8007d4e: 2200 movs r2, #0 8007d50: 771a strb r2, [r3, #28] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 8007d52: 6878 ldr r0, [r7, #4] 8007d54: f7fc fa1a bl 800418c } hcrc->State = HAL_CRC_STATE_BUSY; 8007d58: 687b ldr r3, [r7, #4] 8007d5a: 2202 movs r2, #2 8007d5c: 775a strb r2, [r3, #29] /* check whether or not non-default generating polynomial has been * picked up by user */ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) 8007d5e: 687b ldr r3, [r7, #4] 8007d60: 791b ldrb r3, [r3, #4] 8007d62: 2b00 cmp r3, #0 8007d64: d10c bne.n 8007d80 { /* initialize peripheral with default generating polynomial */ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); 8007d66: 687b ldr r3, [r7, #4] 8007d68: 681b ldr r3, [r3, #0] 8007d6a: 4a22 ldr r2, [pc, #136] @ (8007df4 ) 8007d6c: 615a str r2, [r3, #20] MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); 8007d6e: 687b ldr r3, [r7, #4] 8007d70: 681b ldr r3, [r3, #0] 8007d72: 689a ldr r2, [r3, #8] 8007d74: 687b ldr r3, [r7, #4] 8007d76: 681b ldr r3, [r3, #0] 8007d78: f022 0218 bic.w r2, r2, #24 8007d7c: 609a str r2, [r3, #8] 8007d7e: e00c b.n 8007d9a } else { /* initialize CRC peripheral with generating polynomial defined by user */ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) 8007d80: 687b ldr r3, [r7, #4] 8007d82: 6899 ldr r1, [r3, #8] 8007d84: 687b ldr r3, [r7, #4] 8007d86: 68db ldr r3, [r3, #12] 8007d88: 461a mov r2, r3 8007d8a: 6878 ldr r0, [r7, #4] 8007d8c: f000 f948 bl 8008020 8007d90: 4603 mov r3, r0 8007d92: 2b00 cmp r3, #0 8007d94: d001 beq.n 8007d9a { return HAL_ERROR; 8007d96: 2301 movs r3, #1 8007d98: e028 b.n 8007dec } /* check whether or not non-default CRC initial value has been * picked up by user */ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) 8007d9a: 687b ldr r3, [r7, #4] 8007d9c: 795b ldrb r3, [r3, #5] 8007d9e: 2b00 cmp r3, #0 8007da0: d105 bne.n 8007dae { WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); 8007da2: 687b ldr r3, [r7, #4] 8007da4: 681b ldr r3, [r3, #0] 8007da6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007daa: 611a str r2, [r3, #16] 8007dac: e004 b.n 8007db8 } else { WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); 8007dae: 687b ldr r3, [r7, #4] 8007db0: 681b ldr r3, [r3, #0] 8007db2: 687a ldr r2, [r7, #4] 8007db4: 6912 ldr r2, [r2, #16] 8007db6: 611a str r2, [r3, #16] } /* set input data inversion mode */ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); 8007db8: 687b ldr r3, [r7, #4] 8007dba: 681b ldr r3, [r3, #0] 8007dbc: 689b ldr r3, [r3, #8] 8007dbe: f023 0160 bic.w r1, r3, #96 @ 0x60 8007dc2: 687b ldr r3, [r7, #4] 8007dc4: 695a ldr r2, [r3, #20] 8007dc6: 687b ldr r3, [r7, #4] 8007dc8: 681b ldr r3, [r3, #0] 8007dca: 430a orrs r2, r1 8007dcc: 609a str r2, [r3, #8] /* set output data inversion mode */ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); 8007dce: 687b ldr r3, [r7, #4] 8007dd0: 681b ldr r3, [r3, #0] 8007dd2: 689b ldr r3, [r3, #8] 8007dd4: f023 0180 bic.w r1, r3, #128 @ 0x80 8007dd8: 687b ldr r3, [r7, #4] 8007dda: 699a ldr r2, [r3, #24] 8007ddc: 687b ldr r3, [r7, #4] 8007dde: 681b ldr r3, [r3, #0] 8007de0: 430a orrs r2, r1 8007de2: 609a str r2, [r3, #8] /* makes sure the input data format (bytes, halfwords or words stream) * is properly specified by user */ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 8007de4: 687b ldr r3, [r7, #4] 8007de6: 2201 movs r2, #1 8007de8: 775a strb r2, [r3, #29] /* Return function status */ return HAL_OK; 8007dea: 2300 movs r3, #0 } 8007dec: 4618 mov r0, r3 8007dee: 3708 adds r7, #8 8007df0: 46bd mov sp, r7 8007df2: bd80 pop {r7, pc} 8007df4: 04c11db7 .word 0x04c11db7 08007df8 : * and the API will internally adjust its input data processing based on the * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { 8007df8: b580 push {r7, lr} 8007dfa: b086 sub sp, #24 8007dfc: af00 add r7, sp, #0 8007dfe: 60f8 str r0, [r7, #12] 8007e00: 60b9 str r1, [r7, #8] 8007e02: 607a str r2, [r7, #4] uint32_t index; /* CRC input data buffer index */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ 8007e04: 2300 movs r3, #0 8007e06: 613b str r3, [r7, #16] /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; 8007e08: 68fb ldr r3, [r7, #12] 8007e0a: 2202 movs r2, #2 8007e0c: 775a strb r2, [r3, #29] /* Reset CRC Calculation Unit (hcrc->Instance->INIT is * written in hcrc->Instance->DR) */ __HAL_CRC_DR_RESET(hcrc); 8007e0e: 68fb ldr r3, [r7, #12] 8007e10: 681b ldr r3, [r3, #0] 8007e12: 689a ldr r2, [r3, #8] 8007e14: 68fb ldr r3, [r7, #12] 8007e16: 681b ldr r3, [r3, #0] 8007e18: f042 0201 orr.w r2, r2, #1 8007e1c: 609a str r2, [r3, #8] switch (hcrc->InputDataFormat) 8007e1e: 68fb ldr r3, [r7, #12] 8007e20: 6a1b ldr r3, [r3, #32] 8007e22: 2b03 cmp r3, #3 8007e24: d006 beq.n 8007e34 8007e26: 2b03 cmp r3, #3 8007e28: d829 bhi.n 8007e7e 8007e2a: 2b01 cmp r3, #1 8007e2c: d019 beq.n 8007e62 8007e2e: 2b02 cmp r3, #2 8007e30: d01e beq.n 8007e70 /* Specific 16-bit input data handling */ temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: break; 8007e32: e024 b.n 8007e7e for (index = 0U; index < BufferLength; index++) 8007e34: 2300 movs r3, #0 8007e36: 617b str r3, [r7, #20] 8007e38: e00a b.n 8007e50 hcrc->Instance->DR = pBuffer[index]; 8007e3a: 697b ldr r3, [r7, #20] 8007e3c: 009b lsls r3, r3, #2 8007e3e: 68ba ldr r2, [r7, #8] 8007e40: 441a add r2, r3 8007e42: 68fb ldr r3, [r7, #12] 8007e44: 681b ldr r3, [r3, #0] 8007e46: 6812 ldr r2, [r2, #0] 8007e48: 601a str r2, [r3, #0] for (index = 0U; index < BufferLength; index++) 8007e4a: 697b ldr r3, [r7, #20] 8007e4c: 3301 adds r3, #1 8007e4e: 617b str r3, [r7, #20] 8007e50: 697a ldr r2, [r7, #20] 8007e52: 687b ldr r3, [r7, #4] 8007e54: 429a cmp r2, r3 8007e56: d3f0 bcc.n 8007e3a temp = hcrc->Instance->DR; 8007e58: 68fb ldr r3, [r7, #12] 8007e5a: 681b ldr r3, [r3, #0] 8007e5c: 681b ldr r3, [r3, #0] 8007e5e: 613b str r3, [r7, #16] break; 8007e60: e00e b.n 8007e80 temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); 8007e62: 687a ldr r2, [r7, #4] 8007e64: 68b9 ldr r1, [r7, #8] 8007e66: 68f8 ldr r0, [r7, #12] 8007e68: f000 f812 bl 8007e90 8007e6c: 6138 str r0, [r7, #16] break; 8007e6e: e007 b.n 8007e80 temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ 8007e70: 687a ldr r2, [r7, #4] 8007e72: 68b9 ldr r1, [r7, #8] 8007e74: 68f8 ldr r0, [r7, #12] 8007e76: f000 f899 bl 8007fac 8007e7a: 6138 str r0, [r7, #16] break; 8007e7c: e000 b.n 8007e80 break; 8007e7e: bf00 nop } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 8007e80: 68fb ldr r3, [r7, #12] 8007e82: 2201 movs r2, #1 8007e84: 775a strb r2, [r3, #29] /* Return the CRC computed value */ return temp; 8007e86: 693b ldr r3, [r7, #16] } 8007e88: 4618 mov r0, r3 8007e8a: 3718 adds r7, #24 8007e8c: 46bd mov sp, r7 8007e8e: bd80 pop {r7, pc} 08007e90 : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { 8007e90: b480 push {r7} 8007e92: b089 sub sp, #36 @ 0x24 8007e94: af00 add r7, sp, #0 8007e96: 60f8 str r0, [r7, #12] 8007e98: 60b9 str r1, [r7, #8] 8007e9a: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 4 bytes are entered in a row with a single word write, * last bytes must be carefully fed to the CRC calculator to ensure a correct type * handling by the peripheral */ for (i = 0U; i < (BufferLength / 4U); i++) 8007e9c: 2300 movs r3, #0 8007e9e: 61fb str r3, [r7, #28] 8007ea0: e023 b.n 8007eea { hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007ea2: 69fb ldr r3, [r7, #28] 8007ea4: 009b lsls r3, r3, #2 8007ea6: 68ba ldr r2, [r7, #8] 8007ea8: 4413 add r3, r2 8007eaa: 781b ldrb r3, [r3, #0] 8007eac: 061a lsls r2, r3, #24 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8007eae: 69fb ldr r3, [r7, #28] 8007eb0: 009b lsls r3, r3, #2 8007eb2: 3301 adds r3, #1 8007eb4: 68b9 ldr r1, [r7, #8] 8007eb6: 440b add r3, r1 8007eb8: 781b ldrb r3, [r3, #0] 8007eba: 041b lsls r3, r3, #16 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007ebc: 431a orrs r2, r3 ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 8007ebe: 69fb ldr r3, [r7, #28] 8007ec0: 009b lsls r3, r3, #2 8007ec2: 3302 adds r3, #2 8007ec4: 68b9 ldr r1, [r7, #8] 8007ec6: 440b add r3, r1 8007ec8: 781b ldrb r3, [r3, #0] 8007eca: 021b lsls r3, r3, #8 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8007ecc: 431a orrs r2, r3 (uint32_t)pBuffer[(4U * i) + 3U]; 8007ece: 69fb ldr r3, [r7, #28] 8007ed0: 009b lsls r3, r3, #2 8007ed2: 3303 adds r3, #3 8007ed4: 68b9 ldr r1, [r7, #8] 8007ed6: 440b add r3, r1 8007ed8: 781b ldrb r3, [r3, #0] 8007eda: 4619 mov r1, r3 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007edc: 68fb ldr r3, [r7, #12] 8007ede: 681b ldr r3, [r3, #0] ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 8007ee0: 430a orrs r2, r1 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007ee2: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 4U); i++) 8007ee4: 69fb ldr r3, [r7, #28] 8007ee6: 3301 adds r3, #1 8007ee8: 61fb str r3, [r7, #28] 8007eea: 687b ldr r3, [r7, #4] 8007eec: 089b lsrs r3, r3, #2 8007eee: 69fa ldr r2, [r7, #28] 8007ef0: 429a cmp r2, r3 8007ef2: d3d6 bcc.n 8007ea2 } /* last bytes specific handling */ if ((BufferLength % 4U) != 0U) 8007ef4: 687b ldr r3, [r7, #4] 8007ef6: f003 0303 and.w r3, r3, #3 8007efa: 2b00 cmp r3, #0 8007efc: d04d beq.n 8007f9a { if ((BufferLength % 4U) == 1U) 8007efe: 687b ldr r3, [r7, #4] 8007f00: f003 0303 and.w r3, r3, #3 8007f04: 2b01 cmp r3, #1 8007f06: d107 bne.n 8007f18 { *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ 8007f08: 69fb ldr r3, [r7, #28] 8007f0a: 009b lsls r3, r3, #2 8007f0c: 68ba ldr r2, [r7, #8] 8007f0e: 4413 add r3, r2 8007f10: 68fa ldr r2, [r7, #12] 8007f12: 6812 ldr r2, [r2, #0] 8007f14: 781b ldrb r3, [r3, #0] 8007f16: 7013 strb r3, [r2, #0] } if ((BufferLength % 4U) == 2U) 8007f18: 687b ldr r3, [r7, #4] 8007f1a: f003 0303 and.w r3, r3, #3 8007f1e: 2b02 cmp r3, #2 8007f20: d116 bne.n 8007f50 { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 8007f22: 69fb ldr r3, [r7, #28] 8007f24: 009b lsls r3, r3, #2 8007f26: 68ba ldr r2, [r7, #8] 8007f28: 4413 add r3, r2 8007f2a: 781b ldrb r3, [r3, #0] 8007f2c: 021b lsls r3, r3, #8 8007f2e: b21a sxth r2, r3 8007f30: 69fb ldr r3, [r7, #28] 8007f32: 009b lsls r3, r3, #2 8007f34: 3301 adds r3, #1 8007f36: 68b9 ldr r1, [r7, #8] 8007f38: 440b add r3, r1 8007f3a: 781b ldrb r3, [r3, #0] 8007f3c: b21b sxth r3, r3 8007f3e: 4313 orrs r3, r2 8007f40: b21b sxth r3, r3 8007f42: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007f44: 68fb ldr r3, [r7, #12] 8007f46: 681b ldr r3, [r3, #0] 8007f48: 617b str r3, [r7, #20] *pReg = data; 8007f4a: 697b ldr r3, [r7, #20] 8007f4c: 8b7a ldrh r2, [r7, #26] 8007f4e: 801a strh r2, [r3, #0] } if ((BufferLength % 4U) == 3U) 8007f50: 687b ldr r3, [r7, #4] 8007f52: f003 0303 and.w r3, r3, #3 8007f56: 2b03 cmp r3, #3 8007f58: d11f bne.n 8007f9a { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 8007f5a: 69fb ldr r3, [r7, #28] 8007f5c: 009b lsls r3, r3, #2 8007f5e: 68ba ldr r2, [r7, #8] 8007f60: 4413 add r3, r2 8007f62: 781b ldrb r3, [r3, #0] 8007f64: 021b lsls r3, r3, #8 8007f66: b21a sxth r2, r3 8007f68: 69fb ldr r3, [r7, #28] 8007f6a: 009b lsls r3, r3, #2 8007f6c: 3301 adds r3, #1 8007f6e: 68b9 ldr r1, [r7, #8] 8007f70: 440b add r3, r1 8007f72: 781b ldrb r3, [r3, #0] 8007f74: b21b sxth r3, r3 8007f76: 4313 orrs r3, r2 8007f78: b21b sxth r3, r3 8007f7a: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007f7c: 68fb ldr r3, [r7, #12] 8007f7e: 681b ldr r3, [r3, #0] 8007f80: 617b str r3, [r7, #20] *pReg = data; 8007f82: 697b ldr r3, [r7, #20] 8007f84: 8b7a ldrh r2, [r7, #26] 8007f86: 801a strh r2, [r3, #0] *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ 8007f88: 69fb ldr r3, [r7, #28] 8007f8a: 009b lsls r3, r3, #2 8007f8c: 3302 adds r3, #2 8007f8e: 68ba ldr r2, [r7, #8] 8007f90: 4413 add r3, r2 8007f92: 68fa ldr r2, [r7, #12] 8007f94: 6812 ldr r2, [r2, #0] 8007f96: 781b ldrb r3, [r3, #0] 8007f98: 7013 strb r3, [r2, #0] } } /* Return the CRC computed value */ return hcrc->Instance->DR; 8007f9a: 68fb ldr r3, [r7, #12] 8007f9c: 681b ldr r3, [r3, #0] 8007f9e: 681b ldr r3, [r3, #0] } 8007fa0: 4618 mov r0, r3 8007fa2: 3724 adds r7, #36 @ 0x24 8007fa4: 46bd mov sp, r7 8007fa6: f85d 7b04 ldr.w r7, [sp], #4 8007faa: 4770 bx lr 08007fac : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { 8007fac: b480 push {r7} 8007fae: b087 sub sp, #28 8007fb0: af00 add r7, sp, #0 8007fb2: 60f8 str r0, [r7, #12] 8007fb4: 60b9 str r1, [r7, #8] 8007fb6: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the peripheral */ for (i = 0U; i < (BufferLength / 2U); i++) 8007fb8: 2300 movs r3, #0 8007fba: 617b str r3, [r7, #20] 8007fbc: e013 b.n 8007fe6 { hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; 8007fbe: 697b ldr r3, [r7, #20] 8007fc0: 009b lsls r3, r3, #2 8007fc2: 68ba ldr r2, [r7, #8] 8007fc4: 4413 add r3, r2 8007fc6: 881b ldrh r3, [r3, #0] 8007fc8: 041a lsls r2, r3, #16 8007fca: 697b ldr r3, [r7, #20] 8007fcc: 009b lsls r3, r3, #2 8007fce: 3302 adds r3, #2 8007fd0: 68b9 ldr r1, [r7, #8] 8007fd2: 440b add r3, r1 8007fd4: 881b ldrh r3, [r3, #0] 8007fd6: 4619 mov r1, r3 8007fd8: 68fb ldr r3, [r7, #12] 8007fda: 681b ldr r3, [r3, #0] 8007fdc: 430a orrs r2, r1 8007fde: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 2U); i++) 8007fe0: 697b ldr r3, [r7, #20] 8007fe2: 3301 adds r3, #1 8007fe4: 617b str r3, [r7, #20] 8007fe6: 687b ldr r3, [r7, #4] 8007fe8: 085b lsrs r3, r3, #1 8007fea: 697a ldr r2, [r7, #20] 8007fec: 429a cmp r2, r3 8007fee: d3e6 bcc.n 8007fbe } if ((BufferLength % 2U) != 0U) 8007ff0: 687b ldr r3, [r7, #4] 8007ff2: f003 0301 and.w r3, r3, #1 8007ff6: 2b00 cmp r3, #0 8007ff8: d009 beq.n 800800e { pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007ffa: 68fb ldr r3, [r7, #12] 8007ffc: 681b ldr r3, [r3, #0] 8007ffe: 613b str r3, [r7, #16] *pReg = pBuffer[2U * i]; 8008000: 697b ldr r3, [r7, #20] 8008002: 009b lsls r3, r3, #2 8008004: 68ba ldr r2, [r7, #8] 8008006: 4413 add r3, r2 8008008: 881a ldrh r2, [r3, #0] 800800a: 693b ldr r3, [r7, #16] 800800c: 801a strh r2, [r3, #0] } /* Return the CRC computed value */ return hcrc->Instance->DR; 800800e: 68fb ldr r3, [r7, #12] 8008010: 681b ldr r3, [r3, #0] 8008012: 681b ldr r3, [r3, #0] } 8008014: 4618 mov r0, r3 8008016: 371c adds r7, #28 8008018: 46bd mov sp, r7 800801a: f85d 7b04 ldr.w r7, [sp], #4 800801e: 4770 bx lr 08008020 : * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) { 8008020: b480 push {r7} 8008022: b087 sub sp, #28 8008024: af00 add r7, sp, #0 8008026: 60f8 str r0, [r7, #12] 8008028: 60b9 str r1, [r7, #8] 800802a: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800802c: 2300 movs r3, #0 800802e: 75fb strb r3, [r7, #23] uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ 8008030: 231f movs r3, #31 8008032: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); /* Ensure that the generating polynomial is odd */ if ((Pol & (uint32_t)(0x1U)) == 0U) 8008034: 68bb ldr r3, [r7, #8] 8008036: f003 0301 and.w r3, r3, #1 800803a: 2b00 cmp r3, #0 800803c: d102 bne.n 8008044 { status = HAL_ERROR; 800803e: 2301 movs r3, #1 8008040: 75fb strb r3, [r7, #23] 8008042: e063 b.n 800810c * definition. HAL_ERROR is reported if Pol degree is * larger than that indicated by PolyLength. * Look for MSB position: msb will contain the degree of * the second to the largest polynomial member. E.g., for * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) 8008044: bf00 nop 8008046: 693b ldr r3, [r7, #16] 8008048: 1e5a subs r2, r3, #1 800804a: 613a str r2, [r7, #16] 800804c: 2b00 cmp r3, #0 800804e: d009 beq.n 8008064 8008050: 693b ldr r3, [r7, #16] 8008052: f003 031f and.w r3, r3, #31 8008056: 68ba ldr r2, [r7, #8] 8008058: fa22 f303 lsr.w r3, r2, r3 800805c: f003 0301 and.w r3, r3, #1 8008060: 2b00 cmp r3, #0 8008062: d0f0 beq.n 8008046 { } switch (PolyLength) 8008064: 687b ldr r3, [r7, #4] 8008066: 2b18 cmp r3, #24 8008068: d846 bhi.n 80080f8 800806a: a201 add r2, pc, #4 @ (adr r2, 8008070 ) 800806c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008070: 080080ff .word 0x080080ff 8008074: 080080f9 .word 0x080080f9 8008078: 080080f9 .word 0x080080f9 800807c: 080080f9 .word 0x080080f9 8008080: 080080f9 .word 0x080080f9 8008084: 080080f9 .word 0x080080f9 8008088: 080080f9 .word 0x080080f9 800808c: 080080f9 .word 0x080080f9 8008090: 080080ed .word 0x080080ed 8008094: 080080f9 .word 0x080080f9 8008098: 080080f9 .word 0x080080f9 800809c: 080080f9 .word 0x080080f9 80080a0: 080080f9 .word 0x080080f9 80080a4: 080080f9 .word 0x080080f9 80080a8: 080080f9 .word 0x080080f9 80080ac: 080080f9 .word 0x080080f9 80080b0: 080080e1 .word 0x080080e1 80080b4: 080080f9 .word 0x080080f9 80080b8: 080080f9 .word 0x080080f9 80080bc: 080080f9 .word 0x080080f9 80080c0: 080080f9 .word 0x080080f9 80080c4: 080080f9 .word 0x080080f9 80080c8: 080080f9 .word 0x080080f9 80080cc: 080080f9 .word 0x080080f9 80080d0: 080080d5 .word 0x080080d5 { case CRC_POLYLENGTH_7B: if (msb >= HAL_CRC_LENGTH_7B) 80080d4: 693b ldr r3, [r7, #16] 80080d6: 2b06 cmp r3, #6 80080d8: d913 bls.n 8008102 { status = HAL_ERROR; 80080da: 2301 movs r3, #1 80080dc: 75fb strb r3, [r7, #23] } break; 80080de: e010 b.n 8008102 case CRC_POLYLENGTH_8B: if (msb >= HAL_CRC_LENGTH_8B) 80080e0: 693b ldr r3, [r7, #16] 80080e2: 2b07 cmp r3, #7 80080e4: d90f bls.n 8008106 { status = HAL_ERROR; 80080e6: 2301 movs r3, #1 80080e8: 75fb strb r3, [r7, #23] } break; 80080ea: e00c b.n 8008106 case CRC_POLYLENGTH_16B: if (msb >= HAL_CRC_LENGTH_16B) 80080ec: 693b ldr r3, [r7, #16] 80080ee: 2b0f cmp r3, #15 80080f0: d90b bls.n 800810a { status = HAL_ERROR; 80080f2: 2301 movs r3, #1 80080f4: 75fb strb r3, [r7, #23] } break; 80080f6: e008 b.n 800810a case CRC_POLYLENGTH_32B: /* no polynomial definition vs. polynomial length issue possible */ break; default: status = HAL_ERROR; 80080f8: 2301 movs r3, #1 80080fa: 75fb strb r3, [r7, #23] break; 80080fc: e006 b.n 800810c break; 80080fe: bf00 nop 8008100: e004 b.n 800810c break; 8008102: bf00 nop 8008104: e002 b.n 800810c break; 8008106: bf00 nop 8008108: e000 b.n 800810c break; 800810a: bf00 nop } } if (status == HAL_OK) 800810c: 7dfb ldrb r3, [r7, #23] 800810e: 2b00 cmp r3, #0 8008110: d10d bne.n 800812e { /* set generating polynomial */ WRITE_REG(hcrc->Instance->POL, Pol); 8008112: 68fb ldr r3, [r7, #12] 8008114: 681b ldr r3, [r3, #0] 8008116: 68ba ldr r2, [r7, #8] 8008118: 615a str r2, [r3, #20] /* set generating polynomial size */ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); 800811a: 68fb ldr r3, [r7, #12] 800811c: 681b ldr r3, [r3, #0] 800811e: 689b ldr r3, [r3, #8] 8008120: f023 0118 bic.w r1, r3, #24 8008124: 68fb ldr r3, [r7, #12] 8008126: 681b ldr r3, [r3, #0] 8008128: 687a ldr r2, [r7, #4] 800812a: 430a orrs r2, r1 800812c: 609a str r2, [r3, #8] } /* Return function status */ return status; 800812e: 7dfb ldrb r3, [r7, #23] } 8008130: 4618 mov r0, r3 8008132: 371c adds r7, #28 8008134: 46bd mov sp, r7 8008136: f85d 7b04 ldr.w r7, [sp], #4 800813a: 4770 bx lr 0800813c : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { 800813c: b580 push {r7, lr} 800813e: b082 sub sp, #8 8008140: af00 add r7, sp, #0 8008142: 6078 str r0, [r7, #4] /* Check the DAC peripheral handle */ if (hdac == NULL) 8008144: 687b ldr r3, [r7, #4] 8008146: 2b00 cmp r3, #0 8008148: d101 bne.n 800814e { return HAL_ERROR; 800814a: 2301 movs r3, #1 800814c: e014 b.n 8008178 } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); if (hdac->State == HAL_DAC_STATE_RESET) 800814e: 687b ldr r3, [r7, #4] 8008150: 791b ldrb r3, [r3, #4] 8008152: b2db uxtb r3, r3 8008154: 2b00 cmp r3, #0 8008156: d105 bne.n 8008164 hdac->MspInitCallback = HAL_DAC_MspInit; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /* Allocate lock resource and initialize it */ hdac->Lock = HAL_UNLOCKED; 8008158: 687b ldr r3, [r7, #4] 800815a: 2200 movs r2, #0 800815c: 715a strb r2, [r3, #5] #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* Init the low level hardware */ hdac->MspInitCallback(hdac); #else /* Init the low level hardware */ HAL_DAC_MspInit(hdac); 800815e: 6878 ldr r0, [r7, #4] 8008160: f7fc f836 bl 80041d0 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; 8008164: 687b ldr r3, [r7, #4] 8008166: 2202 movs r2, #2 8008168: 711a strb r2, [r3, #4] /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; 800816a: 687b ldr r3, [r7, #4] 800816c: 2200 movs r2, #0 800816e: 611a str r2, [r3, #16] /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; 8008170: 687b ldr r3, [r7, #4] 8008172: 2201 movs r2, #1 8008174: 711a strb r2, [r3, #4] /* Return function status */ return HAL_OK; 8008176: 2300 movs r3, #0 } 8008178: 4618 mov r0, r3 800817a: 3708 adds r7, #8 800817c: 46bd mov sp, r7 800817e: bd80 pop {r7, pc} 08008180 : * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { 8008180: b480 push {r7} 8008182: b083 sub sp, #12 8008184: af00 add r7, sp, #0 8008186: 6078 str r0, [r7, #4] 8008188: 6039 str r1, [r7, #0] /* Check the DAC peripheral handle */ if (hdac == NULL) 800818a: 687b ldr r3, [r7, #4] 800818c: 2b00 cmp r3, #0 800818e: d101 bne.n 8008194 { return HAL_ERROR; 8008190: 2301 movs r3, #1 8008192: e046 b.n 8008222 /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 8008194: 687b ldr r3, [r7, #4] 8008196: 795b ldrb r3, [r3, #5] 8008198: 2b01 cmp r3, #1 800819a: d101 bne.n 80081a0 800819c: 2302 movs r3, #2 800819e: e040 b.n 8008222 80081a0: 687b ldr r3, [r7, #4] 80081a2: 2201 movs r2, #1 80081a4: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 80081a6: 687b ldr r3, [r7, #4] 80081a8: 2202 movs r2, #2 80081aa: 711a strb r2, [r3, #4] /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); 80081ac: 687b ldr r3, [r7, #4] 80081ae: 681b ldr r3, [r3, #0] 80081b0: 6819 ldr r1, [r3, #0] 80081b2: 683b ldr r3, [r7, #0] 80081b4: f003 0310 and.w r3, r3, #16 80081b8: 2201 movs r2, #1 80081ba: 409a lsls r2, r3 80081bc: 687b ldr r3, [r7, #4] 80081be: 681b ldr r3, [r3, #0] 80081c0: 430a orrs r2, r1 80081c2: 601a str r2, [r3, #0] if (Channel == DAC_CHANNEL_1) 80081c4: 683b ldr r3, [r7, #0] 80081c6: 2b00 cmp r3, #0 80081c8: d10f bne.n 80081ea { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) 80081ca: 687b ldr r3, [r7, #4] 80081cc: 681b ldr r3, [r3, #0] 80081ce: 681b ldr r3, [r3, #0] 80081d0: f003 033e and.w r3, r3, #62 @ 0x3e 80081d4: 2b02 cmp r3, #2 80081d6: d11d bne.n 8008214 { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); 80081d8: 687b ldr r3, [r7, #4] 80081da: 681b ldr r3, [r3, #0] 80081dc: 685a ldr r2, [r3, #4] 80081de: 687b ldr r3, [r7, #4] 80081e0: 681b ldr r3, [r3, #0] 80081e2: f042 0201 orr.w r2, r2, #1 80081e6: 605a str r2, [r3, #4] 80081e8: e014 b.n 8008214 } else { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) 80081ea: 687b ldr r3, [r7, #4] 80081ec: 681b ldr r3, [r3, #0] 80081ee: 681b ldr r3, [r3, #0] 80081f0: f403 1278 and.w r2, r3, #4063232 @ 0x3e0000 80081f4: 683b ldr r3, [r7, #0] 80081f6: f003 0310 and.w r3, r3, #16 80081fa: 2102 movs r1, #2 80081fc: fa01 f303 lsl.w r3, r1, r3 8008200: 429a cmp r2, r3 8008202: d107 bne.n 8008214 { /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); 8008204: 687b ldr r3, [r7, #4] 8008206: 681b ldr r3, [r3, #0] 8008208: 685a ldr r2, [r3, #4] 800820a: 687b ldr r3, [r7, #4] 800820c: 681b ldr r3, [r3, #0] 800820e: f042 0202 orr.w r2, r2, #2 8008212: 605a str r2, [r3, #4] } } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 8008214: 687b ldr r3, [r7, #4] 8008216: 2201 movs r2, #1 8008218: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 800821a: 687b ldr r3, [r7, #4] 800821c: 2200 movs r2, #0 800821e: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 8008220: 2300 movs r3, #0 } 8008222: 4618 mov r0, r3 8008224: 370c adds r7, #12 8008226: 46bd mov sp, r7 8008228: f85d 7b04 ldr.w r7, [sp], #4 800822c: 4770 bx lr 0800822e : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { 800822e: b580 push {r7, lr} 8008230: b084 sub sp, #16 8008232: af00 add r7, sp, #0 8008234: 6078 str r0, [r7, #4] uint32_t itsource = hdac->Instance->CR; 8008236: 687b ldr r3, [r7, #4] 8008238: 681b ldr r3, [r3, #0] 800823a: 681b ldr r3, [r3, #0] 800823c: 60fb str r3, [r7, #12] uint32_t itflag = hdac->Instance->SR; 800823e: 687b ldr r3, [r7, #4] 8008240: 681b ldr r3, [r3, #0] 8008242: 6b5b ldr r3, [r3, #52] @ 0x34 8008244: 60bb str r3, [r7, #8] if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1) 8008246: 68fb ldr r3, [r7, #12] 8008248: f403 5300 and.w r3, r3, #8192 @ 0x2000 800824c: 2b00 cmp r3, #0 800824e: d01d beq.n 800828c { /* Check underrun flag of DAC channel 1 */ if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1) 8008250: 68bb ldr r3, [r7, #8] 8008252: f403 5300 and.w r3, r3, #8192 @ 0x2000 8008256: 2b00 cmp r3, #0 8008258: d018 beq.n 800828c { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; 800825a: 687b ldr r3, [r7, #4] 800825c: 2204 movs r2, #4 800825e: 711a strb r2, [r3, #4] /* Set DAC error code to channel1 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); 8008260: 687b ldr r3, [r7, #4] 8008262: 691b ldr r3, [r3, #16] 8008264: f043 0201 orr.w r2, r3, #1 8008268: 687b ldr r3, [r7, #4] 800826a: 611a str r2, [r3, #16] /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); 800826c: 687b ldr r3, [r7, #4] 800826e: 681b ldr r3, [r3, #0] 8008270: f44f 5200 mov.w r2, #8192 @ 0x2000 8008274: 635a str r2, [r3, #52] @ 0x34 /* Disable the selected DAC channel1 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1); 8008276: 687b ldr r3, [r7, #4] 8008278: 681b ldr r3, [r3, #0] 800827a: 681a ldr r2, [r3, #0] 800827c: 687b ldr r3, [r7, #4] 800827e: 681b ldr r3, [r3, #0] 8008280: f422 5280 bic.w r2, r2, #4096 @ 0x1000 8008284: 601a str r2, [r3, #0] /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh1(hdac); #else HAL_DAC_DMAUnderrunCallbackCh1(hdac); 8008286: 6878 ldr r0, [r7, #4] 8008288: f000 f851 bl 800832e #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2) 800828c: 68fb ldr r3, [r7, #12] 800828e: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8008292: 2b00 cmp r3, #0 8008294: d01d beq.n 80082d2 { /* Check underrun flag of DAC channel 2 */ if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2) 8008296: 68bb ldr r3, [r7, #8] 8008298: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800829c: 2b00 cmp r3, #0 800829e: d018 beq.n 80082d2 { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; 80082a0: 687b ldr r3, [r7, #4] 80082a2: 2204 movs r2, #4 80082a4: 711a strb r2, [r3, #4] /* Set DAC error code to channel2 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); 80082a6: 687b ldr r3, [r7, #4] 80082a8: 691b ldr r3, [r3, #16] 80082aa: f043 0202 orr.w r2, r3, #2 80082ae: 687b ldr r3, [r7, #4] 80082b0: 611a str r2, [r3, #16] /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); 80082b2: 687b ldr r3, [r7, #4] 80082b4: 681b ldr r3, [r3, #0] 80082b6: f04f 5200 mov.w r2, #536870912 @ 0x20000000 80082ba: 635a str r2, [r3, #52] @ 0x34 /* Disable the selected DAC channel2 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2); 80082bc: 687b ldr r3, [r7, #4] 80082be: 681b ldr r3, [r3, #0] 80082c0: 681a ldr r2, [r3, #0] 80082c2: 687b ldr r3, [r7, #4] 80082c4: 681b ldr r3, [r3, #0] 80082c6: f022 5280 bic.w r2, r2, #268435456 @ 0x10000000 80082ca: 601a str r2, [r3, #0] /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh2(hdac); #else HAL_DACEx_DMAUnderrunCallbackCh2(hdac); 80082cc: 6878 ldr r0, [r7, #4] 80082ce: f000 f97b bl 80085c8 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } } 80082d2: bf00 nop 80082d4: 3710 adds r7, #16 80082d6: 46bd mov sp, r7 80082d8: bd80 pop {r7, pc} 080082da : * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { 80082da: b480 push {r7} 80082dc: b087 sub sp, #28 80082de: af00 add r7, sp, #0 80082e0: 60f8 str r0, [r7, #12] 80082e2: 60b9 str r1, [r7, #8] 80082e4: 607a str r2, [r7, #4] 80082e6: 603b str r3, [r7, #0] __IO uint32_t tmp = 0UL; 80082e8: 2300 movs r3, #0 80082ea: 617b str r3, [r7, #20] /* Check the DAC peripheral handle */ if (hdac == NULL) 80082ec: 68fb ldr r3, [r7, #12] 80082ee: 2b00 cmp r3, #0 80082f0: d101 bne.n 80082f6 { return HAL_ERROR; 80082f2: 2301 movs r3, #1 80082f4: e015 b.n 8008322 /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)hdac->Instance; 80082f6: 68fb ldr r3, [r7, #12] 80082f8: 681b ldr r3, [r3, #0] 80082fa: 617b str r3, [r7, #20] if (Channel == DAC_CHANNEL_1) 80082fc: 68bb ldr r3, [r7, #8] 80082fe: 2b00 cmp r3, #0 8008300: d105 bne.n 800830e { tmp += DAC_DHR12R1_ALIGNMENT(Alignment); 8008302: 697a ldr r2, [r7, #20] 8008304: 687b ldr r3, [r7, #4] 8008306: 4413 add r3, r2 8008308: 3308 adds r3, #8 800830a: 617b str r3, [r7, #20] 800830c: e004 b.n 8008318 } else { tmp += DAC_DHR12R2_ALIGNMENT(Alignment); 800830e: 697a ldr r2, [r7, #20] 8008310: 687b ldr r3, [r7, #4] 8008312: 4413 add r3, r2 8008314: 3314 adds r3, #20 8008316: 617b str r3, [r7, #20] } /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; 8008318: 697b ldr r3, [r7, #20] 800831a: 461a mov r2, r3 800831c: 683b ldr r3, [r7, #0] 800831e: 6013 str r3, [r2, #0] /* Return function status */ return HAL_OK; 8008320: 2300 movs r3, #0 } 8008322: 4618 mov r0, r3 8008324: 371c adds r7, #28 8008326: 46bd mov sp, r7 8008328: f85d 7b04 ldr.w r7, [sp], #4 800832c: 4770 bx lr 0800832e : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) { 800832e: b480 push {r7} 8008330: b083 sub sp, #12 8008332: af00 add r7, sp, #0 8008334: 6078 str r0, [r7, #4] UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file */ } 8008336: bf00 nop 8008338: 370c adds r7, #12 800833a: 46bd mov sp, r7 800833c: f85d 7b04 ldr.w r7, [sp], #4 8008340: 4770 bx lr ... 08008344 : * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { 8008344: b580 push {r7, lr} 8008346: b08a sub sp, #40 @ 0x28 8008348: af00 add r7, sp, #0 800834a: 60f8 str r0, [r7, #12] 800834c: 60b9 str r1, [r7, #8] 800834e: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8008350: 2300 movs r3, #0 8008352: f887 3023 strb.w r3, [r7, #35] @ 0x23 uint32_t tmpreg2; uint32_t tickstart; uint32_t connectOnChip; /* Check the DAC peripheral handle and channel configuration struct */ if ((hdac == NULL) || (sConfig == NULL)) 8008356: 68fb ldr r3, [r7, #12] 8008358: 2b00 cmp r3, #0 800835a: d002 beq.n 8008362 800835c: 68bb ldr r3, [r7, #8] 800835e: 2b00 cmp r3, #0 8008360: d101 bne.n 8008366 { return HAL_ERROR; 8008362: 2301 movs r3, #1 8008364: e12a b.n 80085bc assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 8008366: 68fb ldr r3, [r7, #12] 8008368: 795b ldrb r3, [r3, #5] 800836a: 2b01 cmp r3, #1 800836c: d101 bne.n 8008372 800836e: 2302 movs r3, #2 8008370: e124 b.n 80085bc 8008372: 68fb ldr r3, [r7, #12] 8008374: 2201 movs r2, #1 8008376: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 8008378: 68fb ldr r3, [r7, #12] 800837a: 2202 movs r2, #2 800837c: 711a strb r2, [r3, #4] /* Sample and hold configuration */ if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) 800837e: 68bb ldr r3, [r7, #8] 8008380: 681b ldr r3, [r3, #0] 8008382: 2b04 cmp r3, #4 8008384: d17a bne.n 800847c { /* Get timeout */ tickstart = HAL_GetTick(); 8008386: f7fd fd8d bl 8005ea4 800838a: 61f8 str r0, [r7, #28] if (Channel == DAC_CHANNEL_1) 800838c: 687b ldr r3, [r7, #4] 800838e: 2b00 cmp r3, #0 8008390: d13d bne.n 800840e { /* SHSR1 can be written when BWST1 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 8008392: e018 b.n 80083c6 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8008394: f7fd fd86 bl 8005ea4 8008398: 4602 mov r2, r0 800839a: 69fb ldr r3, [r7, #28] 800839c: 1ad3 subs r3, r2, r3 800839e: 2b01 cmp r3, #1 80083a0: d911 bls.n 80083c6 { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 80083a2: 68fb ldr r3, [r7, #12] 80083a4: 681b ldr r3, [r3, #0] 80083a6: 6b5a ldr r2, [r3, #52] @ 0x34 80083a8: 4b86 ldr r3, [pc, #536] @ (80085c4 ) 80083aa: 4013 ands r3, r2 80083ac: 2b00 cmp r3, #0 80083ae: d00a beq.n 80083c6 { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 80083b0: 68fb ldr r3, [r7, #12] 80083b2: 691b ldr r3, [r3, #16] 80083b4: f043 0208 orr.w r2, r3, #8 80083b8: 68fb ldr r3, [r7, #12] 80083ba: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 80083bc: 68fb ldr r3, [r7, #12] 80083be: 2203 movs r2, #3 80083c0: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 80083c2: 2303 movs r3, #3 80083c4: e0fa b.n 80085bc while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 80083c6: 68fb ldr r3, [r7, #12] 80083c8: 681b ldr r3, [r3, #0] 80083ca: 6b5a ldr r2, [r3, #52] @ 0x34 80083cc: 4b7d ldr r3, [pc, #500] @ (80085c4 ) 80083ce: 4013 ands r3, r2 80083d0: 2b00 cmp r3, #0 80083d2: d1df bne.n 8008394 } } } hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 80083d4: 68fb ldr r3, [r7, #12] 80083d6: 681b ldr r3, [r3, #0] 80083d8: 68ba ldr r2, [r7, #8] 80083da: 6992 ldr r2, [r2, #24] 80083dc: 641a str r2, [r3, #64] @ 0x40 80083de: e020 b.n 8008422 { /* SHSR2 can be written when BWST2 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 80083e0: f7fd fd60 bl 8005ea4 80083e4: 4602 mov r2, r0 80083e6: 69fb ldr r3, [r7, #28] 80083e8: 1ad3 subs r3, r2, r3 80083ea: 2b01 cmp r3, #1 80083ec: d90f bls.n 800840e { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 80083ee: 68fb ldr r3, [r7, #12] 80083f0: 681b ldr r3, [r3, #0] 80083f2: 6b5b ldr r3, [r3, #52] @ 0x34 80083f4: 2b00 cmp r3, #0 80083f6: da0a bge.n 800840e { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 80083f8: 68fb ldr r3, [r7, #12] 80083fa: 691b ldr r3, [r3, #16] 80083fc: f043 0208 orr.w r2, r3, #8 8008400: 68fb ldr r3, [r7, #12] 8008402: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 8008404: 68fb ldr r3, [r7, #12] 8008406: 2203 movs r2, #3 8008408: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 800840a: 2303 movs r3, #3 800840c: e0d6 b.n 80085bc while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 800840e: 68fb ldr r3, [r7, #12] 8008410: 681b ldr r3, [r3, #0] 8008412: 6b5b ldr r3, [r3, #52] @ 0x34 8008414: 2b00 cmp r3, #0 8008416: dbe3 blt.n 80083e0 } } } hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 8008418: 68fb ldr r3, [r7, #12] 800841a: 681b ldr r3, [r3, #0] 800841c: 68ba ldr r2, [r7, #8] 800841e: 6992 ldr r2, [r2, #24] 8008420: 645a str r2, [r3, #68] @ 0x44 } /* HoldTime */ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), 8008422: 68fb ldr r3, [r7, #12] 8008424: 681b ldr r3, [r3, #0] 8008426: 6c9a ldr r2, [r3, #72] @ 0x48 8008428: 687b ldr r3, [r7, #4] 800842a: f003 0310 and.w r3, r3, #16 800842e: f240 31ff movw r1, #1023 @ 0x3ff 8008432: fa01 f303 lsl.w r3, r1, r3 8008436: 43db mvns r3, r3 8008438: ea02 0103 and.w r1, r2, r3 800843c: 68bb ldr r3, [r7, #8] 800843e: 69da ldr r2, [r3, #28] 8008440: 687b ldr r3, [r7, #4] 8008442: f003 0310 and.w r3, r3, #16 8008446: 409a lsls r2, r3 8008448: 68fb ldr r3, [r7, #12] 800844a: 681b ldr r3, [r3, #0] 800844c: 430a orrs r2, r1 800844e: 649a str r2, [r3, #72] @ 0x48 (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); /* RefreshTime */ MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), 8008450: 68fb ldr r3, [r7, #12] 8008452: 681b ldr r3, [r3, #0] 8008454: 6cda ldr r2, [r3, #76] @ 0x4c 8008456: 687b ldr r3, [r7, #4] 8008458: f003 0310 and.w r3, r3, #16 800845c: 21ff movs r1, #255 @ 0xff 800845e: fa01 f303 lsl.w r3, r1, r3 8008462: 43db mvns r3, r3 8008464: ea02 0103 and.w r1, r2, r3 8008468: 68bb ldr r3, [r7, #8] 800846a: 6a1a ldr r2, [r3, #32] 800846c: 687b ldr r3, [r7, #4] 800846e: f003 0310 and.w r3, r3, #16 8008472: 409a lsls r2, r3 8008474: 68fb ldr r3, [r7, #12] 8008476: 681b ldr r3, [r3, #0] 8008478: 430a orrs r2, r1 800847a: 64da str r2, [r3, #76] @ 0x4c (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); } if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) 800847c: 68bb ldr r3, [r7, #8] 800847e: 691b ldr r3, [r3, #16] 8008480: 2b01 cmp r3, #1 8008482: d11d bne.n 80084c0 /* USER TRIMMING */ { /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; 8008484: 68fb ldr r3, [r7, #12] 8008486: 681b ldr r3, [r3, #0] 8008488: 6b9b ldr r3, [r3, #56] @ 0x38 800848a: 61bb str r3, [r7, #24] /* Clear trimming value */ tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); 800848c: 687b ldr r3, [r7, #4] 800848e: f003 0310 and.w r3, r3, #16 8008492: 221f movs r2, #31 8008494: fa02 f303 lsl.w r3, r2, r3 8008498: 43db mvns r3, r3 800849a: 69ba ldr r2, [r7, #24] 800849c: 4013 ands r3, r2 800849e: 61bb str r3, [r7, #24] /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; 80084a0: 68bb ldr r3, [r7, #8] 80084a2: 695b ldr r3, [r3, #20] 80084a4: 617b str r3, [r7, #20] /* Calculate CCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 80084a6: 687b ldr r3, [r7, #4] 80084a8: f003 0310 and.w r3, r3, #16 80084ac: 697a ldr r2, [r7, #20] 80084ae: fa02 f303 lsl.w r3, r2, r3 80084b2: 69ba ldr r2, [r7, #24] 80084b4: 4313 orrs r3, r2 80084b6: 61bb str r3, [r7, #24] /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; 80084b8: 68fb ldr r3, [r7, #12] 80084ba: 681b ldr r3, [r3, #0] 80084bc: 69ba ldr r2, [r7, #24] 80084be: 639a str r2, [r3, #56] @ 0x38 } /* else factory trimming is used (factory setting are available at reset)*/ /* SW Nothing has nothing to do */ /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; 80084c0: 68fb ldr r3, [r7, #12] 80084c2: 681b ldr r3, [r3, #0] 80084c4: 6bdb ldr r3, [r3, #60] @ 0x3c 80084c6: 61bb str r3, [r7, #24] /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); 80084c8: 687b ldr r3, [r7, #4] 80084ca: f003 0310 and.w r3, r3, #16 80084ce: 2207 movs r2, #7 80084d0: fa02 f303 lsl.w r3, r2, r3 80084d4: 43db mvns r3, r3 80084d6: 69ba ldr r2, [r7, #24] 80084d8: 4013 ands r3, r2 80084da: 61bb str r3, [r7, #24] /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) 80084dc: 68bb ldr r3, [r7, #8] 80084de: 68db ldr r3, [r3, #12] 80084e0: 2b01 cmp r3, #1 80084e2: d102 bne.n 80084ea { connectOnChip = 0x00000000UL; 80084e4: 2300 movs r3, #0 80084e6: 627b str r3, [r7, #36] @ 0x24 80084e8: e00f b.n 800850a } else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL) 80084ea: 68bb ldr r3, [r7, #8] 80084ec: 68db ldr r3, [r3, #12] 80084ee: 2b02 cmp r3, #2 80084f0: d102 bne.n 80084f8 { connectOnChip = DAC_MCR_MODE1_0; 80084f2: 2301 movs r3, #1 80084f4: 627b str r3, [r7, #36] @ 0x24 80084f6: e008 b.n 800850a } else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */ { if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) 80084f8: 68bb ldr r3, [r7, #8] 80084fa: 689b ldr r3, [r3, #8] 80084fc: 2b00 cmp r3, #0 80084fe: d102 bne.n 8008506 { connectOnChip = DAC_MCR_MODE1_0; 8008500: 2301 movs r3, #1 8008502: 627b str r3, [r7, #36] @ 0x24 8008504: e001 b.n 800850a } else { connectOnChip = 0x00000000UL; 8008506: 2300 movs r3, #0 8008508: 627b str r3, [r7, #36] @ 0x24 } } tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); 800850a: 68bb ldr r3, [r7, #8] 800850c: 681a ldr r2, [r3, #0] 800850e: 68bb ldr r3, [r7, #8] 8008510: 689b ldr r3, [r3, #8] 8008512: 4313 orrs r3, r2 8008514: 6a7a ldr r2, [r7, #36] @ 0x24 8008516: 4313 orrs r3, r2 8008518: 617b str r3, [r7, #20] /* Calculate MCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 800851a: 687b ldr r3, [r7, #4] 800851c: f003 0310 and.w r3, r3, #16 8008520: 697a ldr r2, [r7, #20] 8008522: fa02 f303 lsl.w r3, r2, r3 8008526: 69ba ldr r2, [r7, #24] 8008528: 4313 orrs r3, r2 800852a: 61bb str r3, [r7, #24] /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; 800852c: 68fb ldr r3, [r7, #12] 800852e: 681b ldr r3, [r3, #0] 8008530: 69ba ldr r2, [r7, #24] 8008532: 63da str r2, [r3, #60] @ 0x3c /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); 8008534: 68fb ldr r3, [r7, #12] 8008536: 681b ldr r3, [r3, #0] 8008538: 6819 ldr r1, [r3, #0] 800853a: 687b ldr r3, [r7, #4] 800853c: f003 0310 and.w r3, r3, #16 8008540: f44f 4280 mov.w r2, #16384 @ 0x4000 8008544: fa02 f303 lsl.w r3, r2, r3 8008548: 43da mvns r2, r3 800854a: 68fb ldr r3, [r7, #12] 800854c: 681b ldr r3, [r3, #0] 800854e: 400a ands r2, r1 8008550: 601a str r2, [r3, #0] /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; 8008552: 68fb ldr r3, [r7, #12] 8008554: 681b ldr r3, [r3, #0] 8008556: 681b ldr r3, [r3, #0] 8008558: 61bb str r3, [r7, #24] /* Clear TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); 800855a: 687b ldr r3, [r7, #4] 800855c: f003 0310 and.w r3, r3, #16 8008560: f640 72fe movw r2, #4094 @ 0xffe 8008564: fa02 f303 lsl.w r3, r2, r3 8008568: 43db mvns r3, r3 800856a: 69ba ldr r2, [r7, #24] 800856c: 4013 ands r3, r2 800856e: 61bb str r3, [r7, #24] /* Configure for the selected DAC channel: trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ tmpreg2 = sConfig->DAC_Trigger; 8008570: 68bb ldr r3, [r7, #8] 8008572: 685b ldr r3, [r3, #4] 8008574: 617b str r3, [r7, #20] /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8008576: 687b ldr r3, [r7, #4] 8008578: f003 0310 and.w r3, r3, #16 800857c: 697a ldr r2, [r7, #20] 800857e: fa02 f303 lsl.w r3, r2, r3 8008582: 69ba ldr r2, [r7, #24] 8008584: 4313 orrs r3, r2 8008586: 61bb str r3, [r7, #24] /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; 8008588: 68fb ldr r3, [r7, #12] 800858a: 681b ldr r3, [r3, #0] 800858c: 69ba ldr r2, [r7, #24] 800858e: 601a str r2, [r3, #0] /* Disable wave generation */ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); 8008590: 68fb ldr r3, [r7, #12] 8008592: 681b ldr r3, [r3, #0] 8008594: 6819 ldr r1, [r3, #0] 8008596: 687b ldr r3, [r7, #4] 8008598: f003 0310 and.w r3, r3, #16 800859c: 22c0 movs r2, #192 @ 0xc0 800859e: fa02 f303 lsl.w r3, r2, r3 80085a2: 43da mvns r2, r3 80085a4: 68fb ldr r3, [r7, #12] 80085a6: 681b ldr r3, [r3, #0] 80085a8: 400a ands r2, r1 80085aa: 601a str r2, [r3, #0] /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 80085ac: 68fb ldr r3, [r7, #12] 80085ae: 2201 movs r2, #1 80085b0: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 80085b2: 68fb ldr r3, [r7, #12] 80085b4: 2200 movs r2, #0 80085b6: 715a strb r2, [r3, #5] /* Return function status */ return status; 80085b8: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 } 80085bc: 4618 mov r0, r3 80085be: 3728 adds r7, #40 @ 0x28 80085c0: 46bd mov sp, r7 80085c2: bd80 pop {r7, pc} 80085c4: 20008000 .word 0x20008000 080085c8 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) { 80085c8: b480 push {r7} 80085ca: b083 sub sp, #12 80085cc: af00 add r7, sp, #0 80085ce: 6078 str r0, [r7, #4] UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file */ } 80085d0: bf00 nop 80085d2: 370c adds r7, #12 80085d4: 46bd mov sp, r7 80085d6: f85d 7b04 ldr.w r7, [sp], #4 80085da: 4770 bx lr 080085dc : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 80085dc: b580 push {r7, lr} 80085de: b086 sub sp, #24 80085e0: af00 add r7, sp, #0 80085e2: 6078 str r0, [r7, #4] uint32_t registerValue; uint32_t tickstart = HAL_GetTick(); 80085e4: f7fd fc5e bl 8005ea4 80085e8: 6138 str r0, [r7, #16] DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 80085ea: 687b ldr r3, [r7, #4] 80085ec: 2b00 cmp r3, #0 80085ee: d101 bne.n 80085f4 { return HAL_ERROR; 80085f0: 2301 movs r3, #1 80085f2: e316 b.n 8008c22 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80085f4: 687b ldr r3, [r7, #4] 80085f6: 681b ldr r3, [r3, #0] 80085f8: 4a66 ldr r2, [pc, #408] @ (8008794 ) 80085fa: 4293 cmp r3, r2 80085fc: d04a beq.n 8008694 80085fe: 687b ldr r3, [r7, #4] 8008600: 681b ldr r3, [r3, #0] 8008602: 4a65 ldr r2, [pc, #404] @ (8008798 ) 8008604: 4293 cmp r3, r2 8008606: d045 beq.n 8008694 8008608: 687b ldr r3, [r7, #4] 800860a: 681b ldr r3, [r3, #0] 800860c: 4a63 ldr r2, [pc, #396] @ (800879c ) 800860e: 4293 cmp r3, r2 8008610: d040 beq.n 8008694 8008612: 687b ldr r3, [r7, #4] 8008614: 681b ldr r3, [r3, #0] 8008616: 4a62 ldr r2, [pc, #392] @ (80087a0 ) 8008618: 4293 cmp r3, r2 800861a: d03b beq.n 8008694 800861c: 687b ldr r3, [r7, #4] 800861e: 681b ldr r3, [r3, #0] 8008620: 4a60 ldr r2, [pc, #384] @ (80087a4 ) 8008622: 4293 cmp r3, r2 8008624: d036 beq.n 8008694 8008626: 687b ldr r3, [r7, #4] 8008628: 681b ldr r3, [r3, #0] 800862a: 4a5f ldr r2, [pc, #380] @ (80087a8 ) 800862c: 4293 cmp r3, r2 800862e: d031 beq.n 8008694 8008630: 687b ldr r3, [r7, #4] 8008632: 681b ldr r3, [r3, #0] 8008634: 4a5d ldr r2, [pc, #372] @ (80087ac ) 8008636: 4293 cmp r3, r2 8008638: d02c beq.n 8008694 800863a: 687b ldr r3, [r7, #4] 800863c: 681b ldr r3, [r3, #0] 800863e: 4a5c ldr r2, [pc, #368] @ (80087b0 ) 8008640: 4293 cmp r3, r2 8008642: d027 beq.n 8008694 8008644: 687b ldr r3, [r7, #4] 8008646: 681b ldr r3, [r3, #0] 8008648: 4a5a ldr r2, [pc, #360] @ (80087b4 ) 800864a: 4293 cmp r3, r2 800864c: d022 beq.n 8008694 800864e: 687b ldr r3, [r7, #4] 8008650: 681b ldr r3, [r3, #0] 8008652: 4a59 ldr r2, [pc, #356] @ (80087b8 ) 8008654: 4293 cmp r3, r2 8008656: d01d beq.n 8008694 8008658: 687b ldr r3, [r7, #4] 800865a: 681b ldr r3, [r3, #0] 800865c: 4a57 ldr r2, [pc, #348] @ (80087bc ) 800865e: 4293 cmp r3, r2 8008660: d018 beq.n 8008694 8008662: 687b ldr r3, [r7, #4] 8008664: 681b ldr r3, [r3, #0] 8008666: 4a56 ldr r2, [pc, #344] @ (80087c0 ) 8008668: 4293 cmp r3, r2 800866a: d013 beq.n 8008694 800866c: 687b ldr r3, [r7, #4] 800866e: 681b ldr r3, [r3, #0] 8008670: 4a54 ldr r2, [pc, #336] @ (80087c4 ) 8008672: 4293 cmp r3, r2 8008674: d00e beq.n 8008694 8008676: 687b ldr r3, [r7, #4] 8008678: 681b ldr r3, [r3, #0] 800867a: 4a53 ldr r2, [pc, #332] @ (80087c8 ) 800867c: 4293 cmp r3, r2 800867e: d009 beq.n 8008694 8008680: 687b ldr r3, [r7, #4] 8008682: 681b ldr r3, [r3, #0] 8008684: 4a51 ldr r2, [pc, #324] @ (80087cc ) 8008686: 4293 cmp r3, r2 8008688: d004 beq.n 8008694 800868a: 687b ldr r3, [r7, #4] 800868c: 681b ldr r3, [r3, #0] 800868e: 4a50 ldr r2, [pc, #320] @ (80087d0 ) 8008690: 4293 cmp r3, r2 8008692: d101 bne.n 8008698 8008694: 2301 movs r3, #1 8008696: e000 b.n 800869a 8008698: 2300 movs r3, #0 800869a: 2b00 cmp r3, #0 800869c: f000 813b beq.w 8008916 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80086a0: 687b ldr r3, [r7, #4] 80086a2: 2202 movs r2, #2 80086a4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 80086a8: 687b ldr r3, [r7, #4] 80086aa: 2200 movs r2, #0 80086ac: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 80086b0: 687b ldr r3, [r7, #4] 80086b2: 681b ldr r3, [r3, #0] 80086b4: 4a37 ldr r2, [pc, #220] @ (8008794 ) 80086b6: 4293 cmp r3, r2 80086b8: d04a beq.n 8008750 80086ba: 687b ldr r3, [r7, #4] 80086bc: 681b ldr r3, [r3, #0] 80086be: 4a36 ldr r2, [pc, #216] @ (8008798 ) 80086c0: 4293 cmp r3, r2 80086c2: d045 beq.n 8008750 80086c4: 687b ldr r3, [r7, #4] 80086c6: 681b ldr r3, [r3, #0] 80086c8: 4a34 ldr r2, [pc, #208] @ (800879c ) 80086ca: 4293 cmp r3, r2 80086cc: d040 beq.n 8008750 80086ce: 687b ldr r3, [r7, #4] 80086d0: 681b ldr r3, [r3, #0] 80086d2: 4a33 ldr r2, [pc, #204] @ (80087a0 ) 80086d4: 4293 cmp r3, r2 80086d6: d03b beq.n 8008750 80086d8: 687b ldr r3, [r7, #4] 80086da: 681b ldr r3, [r3, #0] 80086dc: 4a31 ldr r2, [pc, #196] @ (80087a4 ) 80086de: 4293 cmp r3, r2 80086e0: d036 beq.n 8008750 80086e2: 687b ldr r3, [r7, #4] 80086e4: 681b ldr r3, [r3, #0] 80086e6: 4a30 ldr r2, [pc, #192] @ (80087a8 ) 80086e8: 4293 cmp r3, r2 80086ea: d031 beq.n 8008750 80086ec: 687b ldr r3, [r7, #4] 80086ee: 681b ldr r3, [r3, #0] 80086f0: 4a2e ldr r2, [pc, #184] @ (80087ac ) 80086f2: 4293 cmp r3, r2 80086f4: d02c beq.n 8008750 80086f6: 687b ldr r3, [r7, #4] 80086f8: 681b ldr r3, [r3, #0] 80086fa: 4a2d ldr r2, [pc, #180] @ (80087b0 ) 80086fc: 4293 cmp r3, r2 80086fe: d027 beq.n 8008750 8008700: 687b ldr r3, [r7, #4] 8008702: 681b ldr r3, [r3, #0] 8008704: 4a2b ldr r2, [pc, #172] @ (80087b4 ) 8008706: 4293 cmp r3, r2 8008708: d022 beq.n 8008750 800870a: 687b ldr r3, [r7, #4] 800870c: 681b ldr r3, [r3, #0] 800870e: 4a2a ldr r2, [pc, #168] @ (80087b8 ) 8008710: 4293 cmp r3, r2 8008712: d01d beq.n 8008750 8008714: 687b ldr r3, [r7, #4] 8008716: 681b ldr r3, [r3, #0] 8008718: 4a28 ldr r2, [pc, #160] @ (80087bc ) 800871a: 4293 cmp r3, r2 800871c: d018 beq.n 8008750 800871e: 687b ldr r3, [r7, #4] 8008720: 681b ldr r3, [r3, #0] 8008722: 4a27 ldr r2, [pc, #156] @ (80087c0 ) 8008724: 4293 cmp r3, r2 8008726: d013 beq.n 8008750 8008728: 687b ldr r3, [r7, #4] 800872a: 681b ldr r3, [r3, #0] 800872c: 4a25 ldr r2, [pc, #148] @ (80087c4 ) 800872e: 4293 cmp r3, r2 8008730: d00e beq.n 8008750 8008732: 687b ldr r3, [r7, #4] 8008734: 681b ldr r3, [r3, #0] 8008736: 4a24 ldr r2, [pc, #144] @ (80087c8 ) 8008738: 4293 cmp r3, r2 800873a: d009 beq.n 8008750 800873c: 687b ldr r3, [r7, #4] 800873e: 681b ldr r3, [r3, #0] 8008740: 4a22 ldr r2, [pc, #136] @ (80087cc ) 8008742: 4293 cmp r3, r2 8008744: d004 beq.n 8008750 8008746: 687b ldr r3, [r7, #4] 8008748: 681b ldr r3, [r3, #0] 800874a: 4a21 ldr r2, [pc, #132] @ (80087d0 ) 800874c: 4293 cmp r3, r2 800874e: d108 bne.n 8008762 8008750: 687b ldr r3, [r7, #4] 8008752: 681b ldr r3, [r3, #0] 8008754: 681a ldr r2, [r3, #0] 8008756: 687b ldr r3, [r7, #4] 8008758: 681b ldr r3, [r3, #0] 800875a: f022 0201 bic.w r2, r2, #1 800875e: 601a str r2, [r3, #0] 8008760: e007 b.n 8008772 8008762: 687b ldr r3, [r7, #4] 8008764: 681b ldr r3, [r3, #0] 8008766: 681a ldr r2, [r3, #0] 8008768: 687b ldr r3, [r7, #4] 800876a: 681b ldr r3, [r3, #0] 800876c: f022 0201 bic.w r2, r2, #1 8008770: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 8008772: e02f b.n 80087d4 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8008774: f7fd fb96 bl 8005ea4 8008778: 4602 mov r2, r0 800877a: 693b ldr r3, [r7, #16] 800877c: 1ad3 subs r3, r2, r3 800877e: 2b05 cmp r3, #5 8008780: d928 bls.n 80087d4 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8008782: 687b ldr r3, [r7, #4] 8008784: 2220 movs r2, #32 8008786: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 8008788: 687b ldr r3, [r7, #4] 800878a: 2203 movs r2, #3 800878c: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8008790: 2301 movs r3, #1 8008792: e246 b.n 8008c22 8008794: 40020010 .word 0x40020010 8008798: 40020028 .word 0x40020028 800879c: 40020040 .word 0x40020040 80087a0: 40020058 .word 0x40020058 80087a4: 40020070 .word 0x40020070 80087a8: 40020088 .word 0x40020088 80087ac: 400200a0 .word 0x400200a0 80087b0: 400200b8 .word 0x400200b8 80087b4: 40020410 .word 0x40020410 80087b8: 40020428 .word 0x40020428 80087bc: 40020440 .word 0x40020440 80087c0: 40020458 .word 0x40020458 80087c4: 40020470 .word 0x40020470 80087c8: 40020488 .word 0x40020488 80087cc: 400204a0 .word 0x400204a0 80087d0: 400204b8 .word 0x400204b8 while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 80087d4: 687b ldr r3, [r7, #4] 80087d6: 681b ldr r3, [r3, #0] 80087d8: 681b ldr r3, [r3, #0] 80087da: f003 0301 and.w r3, r3, #1 80087de: 2b00 cmp r3, #0 80087e0: d1c8 bne.n 8008774 } } /* Get the CR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; 80087e2: 687b ldr r3, [r7, #4] 80087e4: 681b ldr r3, [r3, #0] 80087e6: 681b ldr r3, [r3, #0] 80087e8: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 80087ea: 697a ldr r2, [r7, #20] 80087ec: 4b83 ldr r3, [pc, #524] @ (80089fc ) 80087ee: 4013 ands r3, r2 80087f0: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ registerValue |= hdma->Init.Direction | 80087f2: 687b ldr r3, [r7, #4] 80087f4: 689a ldr r2, [r3, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 80087f6: 687b ldr r3, [r7, #4] 80087f8: 68db ldr r3, [r3, #12] registerValue |= hdma->Init.Direction | 80087fa: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 80087fc: 687b ldr r3, [r7, #4] 80087fe: 691b ldr r3, [r3, #16] 8008800: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8008802: 687b ldr r3, [r7, #4] 8008804: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8008806: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8008808: 687b ldr r3, [r7, #4] 800880a: 699b ldr r3, [r3, #24] 800880c: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800880e: 687b ldr r3, [r7, #4] 8008810: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8008812: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8008814: 687b ldr r3, [r7, #4] 8008816: 6a1b ldr r3, [r3, #32] 8008818: 4313 orrs r3, r2 registerValue |= hdma->Init.Direction | 800881a: 697a ldr r2, [r7, #20] 800881c: 4313 orrs r3, r2 800881e: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8008820: 687b ldr r3, [r7, #4] 8008822: 6a5b ldr r3, [r3, #36] @ 0x24 8008824: 2b04 cmp r3, #4 8008826: d107 bne.n 8008838 { /* Get memory burst and peripheral burst */ registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 8008828: 687b ldr r3, [r7, #4] 800882a: 6ada ldr r2, [r3, #44] @ 0x2c 800882c: 687b ldr r3, [r7, #4] 800882e: 6b1b ldr r3, [r3, #48] @ 0x30 8008830: 4313 orrs r3, r2 8008832: 697a ldr r2, [r7, #20] 8008834: 4313 orrs r3, r2 8008836: 617b str r3, [r7, #20] } /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be lock when transferring data to/from USART/UART */ #if (STM32H7_DEV_ID == 0x450UL) if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) 8008838: 4b71 ldr r3, [pc, #452] @ (8008a00 ) 800883a: 681a ldr r2, [r3, #0] 800883c: 4b71 ldr r3, [pc, #452] @ (8008a04 ) 800883e: 4013 ands r3, r2 8008840: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8008844: d328 bcc.n 8008898 { #endif /* STM32H7_DEV_ID == 0x450UL */ if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) 8008846: 687b ldr r3, [r7, #4] 8008848: 685b ldr r3, [r3, #4] 800884a: 2b28 cmp r3, #40 @ 0x28 800884c: d903 bls.n 8008856 800884e: 687b ldr r3, [r7, #4] 8008850: 685b ldr r3, [r3, #4] 8008852: 2b2e cmp r3, #46 @ 0x2e 8008854: d917 bls.n 8008886 8008856: 687b ldr r3, [r7, #4] 8008858: 685b ldr r3, [r3, #4] 800885a: 2b3e cmp r3, #62 @ 0x3e 800885c: d903 bls.n 8008866 800885e: 687b ldr r3, [r7, #4] 8008860: 685b ldr r3, [r3, #4] 8008862: 2b42 cmp r3, #66 @ 0x42 8008864: d90f bls.n 8008886 8008866: 687b ldr r3, [r7, #4] 8008868: 685b ldr r3, [r3, #4] 800886a: 2b46 cmp r3, #70 @ 0x46 800886c: d903 bls.n 8008876 800886e: 687b ldr r3, [r7, #4] 8008870: 685b ldr r3, [r3, #4] 8008872: 2b48 cmp r3, #72 @ 0x48 8008874: d907 bls.n 8008886 8008876: 687b ldr r3, [r7, #4] 8008878: 685b ldr r3, [r3, #4] 800887a: 2b4e cmp r3, #78 @ 0x4e 800887c: d905 bls.n 800888a 800887e: 687b ldr r3, [r7, #4] 8008880: 685b ldr r3, [r3, #4] 8008882: 2b52 cmp r3, #82 @ 0x52 8008884: d801 bhi.n 800888a 8008886: 2301 movs r3, #1 8008888: e000 b.n 800888c 800888a: 2300 movs r3, #0 800888c: 2b00 cmp r3, #0 800888e: d003 beq.n 8008898 { registerValue |= DMA_SxCR_TRBUFF; 8008890: 697b ldr r3, [r7, #20] 8008892: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8008896: 617b str r3, [r7, #20] #if (STM32H7_DEV_ID == 0x450UL) } #endif /* STM32H7_DEV_ID == 0x450UL */ /* Write to DMA Stream CR register */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; 8008898: 687b ldr r3, [r7, #4] 800889a: 681b ldr r3, [r3, #0] 800889c: 697a ldr r2, [r7, #20] 800889e: 601a str r2, [r3, #0] /* Get the FCR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; 80088a0: 687b ldr r3, [r7, #4] 80088a2: 681b ldr r3, [r3, #0] 80088a4: 695b ldr r3, [r3, #20] 80088a6: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 80088a8: 697b ldr r3, [r7, #20] 80088aa: f023 0307 bic.w r3, r3, #7 80088ae: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ registerValue |= hdma->Init.FIFOMode; 80088b0: 687b ldr r3, [r7, #4] 80088b2: 6a5b ldr r3, [r3, #36] @ 0x24 80088b4: 697a ldr r2, [r7, #20] 80088b6: 4313 orrs r3, r2 80088b8: 617b str r3, [r7, #20] /* the FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 80088ba: 687b ldr r3, [r7, #4] 80088bc: 6a5b ldr r3, [r3, #36] @ 0x24 80088be: 2b04 cmp r3, #4 80088c0: d117 bne.n 80088f2 { /* Get the FIFO threshold */ registerValue |= hdma->Init.FIFOThreshold; 80088c2: 687b ldr r3, [r7, #4] 80088c4: 6a9b ldr r3, [r3, #40] @ 0x28 80088c6: 697a ldr r2, [r7, #20] 80088c8: 4313 orrs r3, r2 80088ca: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 */ if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) 80088cc: 687b ldr r3, [r7, #4] 80088ce: 6adb ldr r3, [r3, #44] @ 0x2c 80088d0: 2b00 cmp r3, #0 80088d2: d00e beq.n 80088f2 { if (DMA_CheckFifoParam(hdma) != HAL_OK) 80088d4: 6878 ldr r0, [r7, #4] 80088d6: f002 fb33 bl 800af40 80088da: 4603 mov r3, r0 80088dc: 2b00 cmp r3, #0 80088de: d008 beq.n 80088f2 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 80088e0: 687b ldr r3, [r7, #4] 80088e2: 2240 movs r2, #64 @ 0x40 80088e4: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80088e6: 687b ldr r3, [r7, #4] 80088e8: 2201 movs r2, #1 80088ea: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 80088ee: 2301 movs r3, #1 80088f0: e197 b.n 8008c22 } } } /* Write to DMA Stream FCR */ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; 80088f2: 687b ldr r3, [r7, #4] 80088f4: 681b ldr r3, [r3, #0] 80088f6: 697a ldr r2, [r7, #20] 80088f8: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 80088fa: 6878 ldr r0, [r7, #4] 80088fc: f002 fa6e bl 800addc 8008900: 4603 mov r3, r0 8008902: 60bb str r3, [r7, #8] /* Clear all interrupt flags */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8008904: 687b ldr r3, [r7, #4] 8008906: 6ddb ldr r3, [r3, #92] @ 0x5c 8008908: f003 031f and.w r3, r3, #31 800890c: 223f movs r2, #63 @ 0x3f 800890e: 409a lsls r2, r3 8008910: 68bb ldr r3, [r7, #8] 8008912: 609a str r2, [r3, #8] 8008914: e0cd b.n 8008ab2 } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 8008916: 687b ldr r3, [r7, #4] 8008918: 681b ldr r3, [r3, #0] 800891a: 4a3b ldr r2, [pc, #236] @ (8008a08 ) 800891c: 4293 cmp r3, r2 800891e: d022 beq.n 8008966 8008920: 687b ldr r3, [r7, #4] 8008922: 681b ldr r3, [r3, #0] 8008924: 4a39 ldr r2, [pc, #228] @ (8008a0c ) 8008926: 4293 cmp r3, r2 8008928: d01d beq.n 8008966 800892a: 687b ldr r3, [r7, #4] 800892c: 681b ldr r3, [r3, #0] 800892e: 4a38 ldr r2, [pc, #224] @ (8008a10 ) 8008930: 4293 cmp r3, r2 8008932: d018 beq.n 8008966 8008934: 687b ldr r3, [r7, #4] 8008936: 681b ldr r3, [r3, #0] 8008938: 4a36 ldr r2, [pc, #216] @ (8008a14 ) 800893a: 4293 cmp r3, r2 800893c: d013 beq.n 8008966 800893e: 687b ldr r3, [r7, #4] 8008940: 681b ldr r3, [r3, #0] 8008942: 4a35 ldr r2, [pc, #212] @ (8008a18 ) 8008944: 4293 cmp r3, r2 8008946: d00e beq.n 8008966 8008948: 687b ldr r3, [r7, #4] 800894a: 681b ldr r3, [r3, #0] 800894c: 4a33 ldr r2, [pc, #204] @ (8008a1c ) 800894e: 4293 cmp r3, r2 8008950: d009 beq.n 8008966 8008952: 687b ldr r3, [r7, #4] 8008954: 681b ldr r3, [r3, #0] 8008956: 4a32 ldr r2, [pc, #200] @ (8008a20 ) 8008958: 4293 cmp r3, r2 800895a: d004 beq.n 8008966 800895c: 687b ldr r3, [r7, #4] 800895e: 681b ldr r3, [r3, #0] 8008960: 4a30 ldr r2, [pc, #192] @ (8008a24 ) 8008962: 4293 cmp r3, r2 8008964: d101 bne.n 800896a 8008966: 2301 movs r3, #1 8008968: e000 b.n 800896c 800896a: 2300 movs r3, #0 800896c: 2b00 cmp r3, #0 800896e: f000 8097 beq.w 8008aa0 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 8008972: 687b ldr r3, [r7, #4] 8008974: 681b ldr r3, [r3, #0] 8008976: 4a24 ldr r2, [pc, #144] @ (8008a08 ) 8008978: 4293 cmp r3, r2 800897a: d021 beq.n 80089c0 800897c: 687b ldr r3, [r7, #4] 800897e: 681b ldr r3, [r3, #0] 8008980: 4a22 ldr r2, [pc, #136] @ (8008a0c ) 8008982: 4293 cmp r3, r2 8008984: d01c beq.n 80089c0 8008986: 687b ldr r3, [r7, #4] 8008988: 681b ldr r3, [r3, #0] 800898a: 4a21 ldr r2, [pc, #132] @ (8008a10 ) 800898c: 4293 cmp r3, r2 800898e: d017 beq.n 80089c0 8008990: 687b ldr r3, [r7, #4] 8008992: 681b ldr r3, [r3, #0] 8008994: 4a1f ldr r2, [pc, #124] @ (8008a14 ) 8008996: 4293 cmp r3, r2 8008998: d012 beq.n 80089c0 800899a: 687b ldr r3, [r7, #4] 800899c: 681b ldr r3, [r3, #0] 800899e: 4a1e ldr r2, [pc, #120] @ (8008a18 ) 80089a0: 4293 cmp r3, r2 80089a2: d00d beq.n 80089c0 80089a4: 687b ldr r3, [r7, #4] 80089a6: 681b ldr r3, [r3, #0] 80089a8: 4a1c ldr r2, [pc, #112] @ (8008a1c ) 80089aa: 4293 cmp r3, r2 80089ac: d008 beq.n 80089c0 80089ae: 687b ldr r3, [r7, #4] 80089b0: 681b ldr r3, [r3, #0] 80089b2: 4a1b ldr r2, [pc, #108] @ (8008a20 ) 80089b4: 4293 cmp r3, r2 80089b6: d003 beq.n 80089c0 80089b8: 687b ldr r3, [r7, #4] 80089ba: 681b ldr r3, [r3, #0] 80089bc: 4a19 ldr r2, [pc, #100] @ (8008a24 ) 80089be: 4293 cmp r3, r2 /* Check the request parameter */ assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80089c0: 687b ldr r3, [r7, #4] 80089c2: 2202 movs r2, #2 80089c4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 80089c8: 687b ldr r3, [r7, #4] 80089ca: 2200 movs r2, #0 80089cc: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Get the CR register value */ registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; 80089d0: 687b ldr r3, [r7, #4] 80089d2: 681b ldr r3, [r3, #0] 80089d4: 681b ldr r3, [r3, #0] 80089d6: 617b str r3, [r7, #20] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */ registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ 80089d8: 697a ldr r2, [r7, #20] 80089da: 4b13 ldr r3, [pc, #76] @ (8008a28 ) 80089dc: 4013 ands r3, r2 80089de: 617b str r3, [r7, #20] BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \ BDMA_CCR_CT)); /* Prepare the DMA Channel configuration */ registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 80089e0: 687b ldr r3, [r7, #4] 80089e2: 689b ldr r3, [r3, #8] 80089e4: 2b40 cmp r3, #64 @ 0x40 80089e6: d021 beq.n 8008a2c 80089e8: 687b ldr r3, [r7, #4] 80089ea: 689b ldr r3, [r3, #8] 80089ec: 2b80 cmp r3, #128 @ 0x80 80089ee: d102 bne.n 80089f6 80089f0: f44f 4380 mov.w r3, #16384 @ 0x4000 80089f4: e01b b.n 8008a2e 80089f6: 2300 movs r3, #0 80089f8: e019 b.n 8008a2e 80089fa: bf00 nop 80089fc: fe10803f .word 0xfe10803f 8008a00: 5c001000 .word 0x5c001000 8008a04: ffff0000 .word 0xffff0000 8008a08: 58025408 .word 0x58025408 8008a0c: 5802541c .word 0x5802541c 8008a10: 58025430 .word 0x58025430 8008a14: 58025444 .word 0x58025444 8008a18: 58025458 .word 0x58025458 8008a1c: 5802546c .word 0x5802546c 8008a20: 58025480 .word 0x58025480 8008a24: 58025494 .word 0x58025494 8008a28: fffe000f .word 0xfffe000f 8008a2c: 2310 movs r3, #16 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 8008a2e: 687a ldr r2, [r7, #4] 8008a30: 68d2 ldr r2, [r2, #12] 8008a32: 08d2 lsrs r2, r2, #3 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8008a34: 431a orrs r2, r3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 8008a36: 687b ldr r3, [r7, #4] 8008a38: 691b ldr r3, [r3, #16] 8008a3a: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 8008a3c: 431a orrs r2, r3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 8008a3e: 687b ldr r3, [r7, #4] 8008a40: 695b ldr r3, [r3, #20] 8008a42: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 8008a44: 431a orrs r2, r3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 8008a46: 687b ldr r3, [r7, #4] 8008a48: 699b ldr r3, [r3, #24] 8008a4a: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 8008a4c: 431a orrs r2, r3 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 8008a4e: 687b ldr r3, [r7, #4] 8008a50: 69db ldr r3, [r3, #28] 8008a52: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 8008a54: 431a orrs r2, r3 DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); 8008a56: 687b ldr r3, [r7, #4] 8008a58: 6a1b ldr r3, [r3, #32] 8008a5a: 091b lsrs r3, r3, #4 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 8008a5c: 4313 orrs r3, r2 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8008a5e: 697a ldr r2, [r7, #20] 8008a60: 4313 orrs r3, r2 8008a62: 617b str r3, [r7, #20] /* Write to DMA Channel CR register */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; 8008a64: 687b ldr r3, [r7, #4] 8008a66: 681b ldr r3, [r3, #0] 8008a68: 697a ldr r2, [r7, #20] 8008a6a: 601a str r2, [r3, #0] /* calculation of the channel index */ hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; 8008a6c: 687b ldr r3, [r7, #4] 8008a6e: 681b ldr r3, [r3, #0] 8008a70: 461a mov r2, r3 8008a72: 4b6e ldr r3, [pc, #440] @ (8008c2c ) 8008a74: 4413 add r3, r2 8008a76: 4a6e ldr r2, [pc, #440] @ (8008c30 ) 8008a78: fba2 2303 umull r2, r3, r2, r3 8008a7c: 091b lsrs r3, r3, #4 8008a7e: 009a lsls r2, r3, #2 8008a80: 687b ldr r3, [r7, #4] 8008a82: 65da str r2, [r3, #92] @ 0x5c /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8008a84: 6878 ldr r0, [r7, #4] 8008a86: f002 f9a9 bl 800addc 8008a8a: 4603 mov r3, r0 8008a8c: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8008a8e: 687b ldr r3, [r7, #4] 8008a90: 6ddb ldr r3, [r3, #92] @ 0x5c 8008a92: f003 031f and.w r3, r3, #31 8008a96: 2201 movs r2, #1 8008a98: 409a lsls r2, r3 8008a9a: 68fb ldr r3, [r7, #12] 8008a9c: 605a str r2, [r3, #4] 8008a9e: e008 b.n 8008ab2 } else { hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8008aa0: 687b ldr r3, [r7, #4] 8008aa2: 2240 movs r2, #64 @ 0x40 8008aa4: 655a str r2, [r3, #84] @ 0x54 hdma->State = HAL_DMA_STATE_ERROR; 8008aa6: 687b ldr r3, [r7, #4] 8008aa8: 2203 movs r2, #3 8008aaa: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8008aae: 2301 movs r3, #1 8008ab0: e0b7 b.n 8008c22 } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8008ab2: 687b ldr r3, [r7, #4] 8008ab4: 681b ldr r3, [r3, #0] 8008ab6: 4a5f ldr r2, [pc, #380] @ (8008c34 ) 8008ab8: 4293 cmp r3, r2 8008aba: d072 beq.n 8008ba2 8008abc: 687b ldr r3, [r7, #4] 8008abe: 681b ldr r3, [r3, #0] 8008ac0: 4a5d ldr r2, [pc, #372] @ (8008c38 ) 8008ac2: 4293 cmp r3, r2 8008ac4: d06d beq.n 8008ba2 8008ac6: 687b ldr r3, [r7, #4] 8008ac8: 681b ldr r3, [r3, #0] 8008aca: 4a5c ldr r2, [pc, #368] @ (8008c3c ) 8008acc: 4293 cmp r3, r2 8008ace: d068 beq.n 8008ba2 8008ad0: 687b ldr r3, [r7, #4] 8008ad2: 681b ldr r3, [r3, #0] 8008ad4: 4a5a ldr r2, [pc, #360] @ (8008c40 ) 8008ad6: 4293 cmp r3, r2 8008ad8: d063 beq.n 8008ba2 8008ada: 687b ldr r3, [r7, #4] 8008adc: 681b ldr r3, [r3, #0] 8008ade: 4a59 ldr r2, [pc, #356] @ (8008c44 ) 8008ae0: 4293 cmp r3, r2 8008ae2: d05e beq.n 8008ba2 8008ae4: 687b ldr r3, [r7, #4] 8008ae6: 681b ldr r3, [r3, #0] 8008ae8: 4a57 ldr r2, [pc, #348] @ (8008c48 ) 8008aea: 4293 cmp r3, r2 8008aec: d059 beq.n 8008ba2 8008aee: 687b ldr r3, [r7, #4] 8008af0: 681b ldr r3, [r3, #0] 8008af2: 4a56 ldr r2, [pc, #344] @ (8008c4c ) 8008af4: 4293 cmp r3, r2 8008af6: d054 beq.n 8008ba2 8008af8: 687b ldr r3, [r7, #4] 8008afa: 681b ldr r3, [r3, #0] 8008afc: 4a54 ldr r2, [pc, #336] @ (8008c50 ) 8008afe: 4293 cmp r3, r2 8008b00: d04f beq.n 8008ba2 8008b02: 687b ldr r3, [r7, #4] 8008b04: 681b ldr r3, [r3, #0] 8008b06: 4a53 ldr r2, [pc, #332] @ (8008c54 ) 8008b08: 4293 cmp r3, r2 8008b0a: d04a beq.n 8008ba2 8008b0c: 687b ldr r3, [r7, #4] 8008b0e: 681b ldr r3, [r3, #0] 8008b10: 4a51 ldr r2, [pc, #324] @ (8008c58 ) 8008b12: 4293 cmp r3, r2 8008b14: d045 beq.n 8008ba2 8008b16: 687b ldr r3, [r7, #4] 8008b18: 681b ldr r3, [r3, #0] 8008b1a: 4a50 ldr r2, [pc, #320] @ (8008c5c ) 8008b1c: 4293 cmp r3, r2 8008b1e: d040 beq.n 8008ba2 8008b20: 687b ldr r3, [r7, #4] 8008b22: 681b ldr r3, [r3, #0] 8008b24: 4a4e ldr r2, [pc, #312] @ (8008c60 ) 8008b26: 4293 cmp r3, r2 8008b28: d03b beq.n 8008ba2 8008b2a: 687b ldr r3, [r7, #4] 8008b2c: 681b ldr r3, [r3, #0] 8008b2e: 4a4d ldr r2, [pc, #308] @ (8008c64 ) 8008b30: 4293 cmp r3, r2 8008b32: d036 beq.n 8008ba2 8008b34: 687b ldr r3, [r7, #4] 8008b36: 681b ldr r3, [r3, #0] 8008b38: 4a4b ldr r2, [pc, #300] @ (8008c68 ) 8008b3a: 4293 cmp r3, r2 8008b3c: d031 beq.n 8008ba2 8008b3e: 687b ldr r3, [r7, #4] 8008b40: 681b ldr r3, [r3, #0] 8008b42: 4a4a ldr r2, [pc, #296] @ (8008c6c ) 8008b44: 4293 cmp r3, r2 8008b46: d02c beq.n 8008ba2 8008b48: 687b ldr r3, [r7, #4] 8008b4a: 681b ldr r3, [r3, #0] 8008b4c: 4a48 ldr r2, [pc, #288] @ (8008c70 ) 8008b4e: 4293 cmp r3, r2 8008b50: d027 beq.n 8008ba2 8008b52: 687b ldr r3, [r7, #4] 8008b54: 681b ldr r3, [r3, #0] 8008b56: 4a47 ldr r2, [pc, #284] @ (8008c74 ) 8008b58: 4293 cmp r3, r2 8008b5a: d022 beq.n 8008ba2 8008b5c: 687b ldr r3, [r7, #4] 8008b5e: 681b ldr r3, [r3, #0] 8008b60: 4a45 ldr r2, [pc, #276] @ (8008c78 ) 8008b62: 4293 cmp r3, r2 8008b64: d01d beq.n 8008ba2 8008b66: 687b ldr r3, [r7, #4] 8008b68: 681b ldr r3, [r3, #0] 8008b6a: 4a44 ldr r2, [pc, #272] @ (8008c7c ) 8008b6c: 4293 cmp r3, r2 8008b6e: d018 beq.n 8008ba2 8008b70: 687b ldr r3, [r7, #4] 8008b72: 681b ldr r3, [r3, #0] 8008b74: 4a42 ldr r2, [pc, #264] @ (8008c80 ) 8008b76: 4293 cmp r3, r2 8008b78: d013 beq.n 8008ba2 8008b7a: 687b ldr r3, [r7, #4] 8008b7c: 681b ldr r3, [r3, #0] 8008b7e: 4a41 ldr r2, [pc, #260] @ (8008c84 ) 8008b80: 4293 cmp r3, r2 8008b82: d00e beq.n 8008ba2 8008b84: 687b ldr r3, [r7, #4] 8008b86: 681b ldr r3, [r3, #0] 8008b88: 4a3f ldr r2, [pc, #252] @ (8008c88 ) 8008b8a: 4293 cmp r3, r2 8008b8c: d009 beq.n 8008ba2 8008b8e: 687b ldr r3, [r7, #4] 8008b90: 681b ldr r3, [r3, #0] 8008b92: 4a3e ldr r2, [pc, #248] @ (8008c8c ) 8008b94: 4293 cmp r3, r2 8008b96: d004 beq.n 8008ba2 8008b98: 687b ldr r3, [r7, #4] 8008b9a: 681b ldr r3, [r3, #0] 8008b9c: 4a3c ldr r2, [pc, #240] @ (8008c90 ) 8008b9e: 4293 cmp r3, r2 8008ba0: d101 bne.n 8008ba6 8008ba2: 2301 movs r3, #1 8008ba4: e000 b.n 8008ba8 8008ba6: 2300 movs r3, #0 8008ba8: 2b00 cmp r3, #0 8008baa: d032 beq.n 8008c12 { /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 8008bac: 6878 ldr r0, [r7, #4] 8008bae: f002 fa43 bl 800b038 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 8008bb2: 687b ldr r3, [r7, #4] 8008bb4: 689b ldr r3, [r3, #8] 8008bb6: 2b80 cmp r3, #128 @ 0x80 8008bb8: d102 bne.n 8008bc0 { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 8008bba: 687b ldr r3, [r7, #4] 8008bbc: 2200 movs r2, #0 8008bbe: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8008bc0: 687b ldr r3, [r7, #4] 8008bc2: 685a ldr r2, [r3, #4] 8008bc4: 687b ldr r3, [r7, #4] 8008bc6: 6e1b ldr r3, [r3, #96] @ 0x60 8008bc8: b2d2 uxtb r2, r2 8008bca: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8008bcc: 687b ldr r3, [r7, #4] 8008bce: 6e5b ldr r3, [r3, #100] @ 0x64 8008bd0: 687a ldr r2, [r7, #4] 8008bd2: 6e92 ldr r2, [r2, #104] @ 0x68 8008bd4: 605a str r2, [r3, #4] /* Initialize parameters for DMAMUX request generator : if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 */ if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) 8008bd6: 687b ldr r3, [r7, #4] 8008bd8: 685b ldr r3, [r3, #4] 8008bda: 2b00 cmp r3, #0 8008bdc: d010 beq.n 8008c00 8008bde: 687b ldr r3, [r7, #4] 8008be0: 685b ldr r3, [r3, #4] 8008be2: 2b08 cmp r3, #8 8008be4: d80c bhi.n 8008c00 { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 8008be6: 6878 ldr r0, [r7, #4] 8008be8: f002 fac0 bl 800b16c /* Reset the DMAMUX request generator register */ hdma->DMAmuxRequestGen->RGCR = 0U; 8008bec: 687b ldr r3, [r7, #4] 8008bee: 6edb ldr r3, [r3, #108] @ 0x6c 8008bf0: 2200 movs r2, #0 8008bf2: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8008bf4: 687b ldr r3, [r7, #4] 8008bf6: 6f1b ldr r3, [r3, #112] @ 0x70 8008bf8: 687a ldr r2, [r7, #4] 8008bfa: 6f52 ldr r2, [r2, #116] @ 0x74 8008bfc: 605a str r2, [r3, #4] 8008bfe: e008 b.n 8008c12 } else { hdma->DMAmuxRequestGen = 0U; 8008c00: 687b ldr r3, [r7, #4] 8008c02: 2200 movs r2, #0 8008c04: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = 0U; 8008c06: 687b ldr r3, [r7, #4] 8008c08: 2200 movs r2, #0 8008c0a: 671a str r2, [r3, #112] @ 0x70 hdma->DMAmuxRequestGenStatusMask = 0U; 8008c0c: 687b ldr r3, [r7, #4] 8008c0e: 2200 movs r2, #0 8008c10: 675a str r2, [r3, #116] @ 0x74 } } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8008c12: 687b ldr r3, [r7, #4] 8008c14: 2200 movs r2, #0 8008c16: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8008c18: 687b ldr r3, [r7, #4] 8008c1a: 2201 movs r2, #1 8008c1c: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 8008c20: 2300 movs r3, #0 } 8008c22: 4618 mov r0, r3 8008c24: 3718 adds r7, #24 8008c26: 46bd mov sp, r7 8008c28: bd80 pop {r7, pc} 8008c2a: bf00 nop 8008c2c: a7fdabf8 .word 0xa7fdabf8 8008c30: cccccccd .word 0xcccccccd 8008c34: 40020010 .word 0x40020010 8008c38: 40020028 .word 0x40020028 8008c3c: 40020040 .word 0x40020040 8008c40: 40020058 .word 0x40020058 8008c44: 40020070 .word 0x40020070 8008c48: 40020088 .word 0x40020088 8008c4c: 400200a0 .word 0x400200a0 8008c50: 400200b8 .word 0x400200b8 8008c54: 40020410 .word 0x40020410 8008c58: 40020428 .word 0x40020428 8008c5c: 40020440 .word 0x40020440 8008c60: 40020458 .word 0x40020458 8008c64: 40020470 .word 0x40020470 8008c68: 40020488 .word 0x40020488 8008c6c: 400204a0 .word 0x400204a0 8008c70: 400204b8 .word 0x400204b8 8008c74: 58025408 .word 0x58025408 8008c78: 5802541c .word 0x5802541c 8008c7c: 58025430 .word 0x58025430 8008c80: 58025444 .word 0x58025444 8008c84: 58025458 .word 0x58025458 8008c88: 5802546c .word 0x5802546c 8008c8c: 58025480 .word 0x58025480 8008c90: 58025494 .word 0x58025494 08008c94 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8008c94: b580 push {r7, lr} 8008c96: b086 sub sp, #24 8008c98: af00 add r7, sp, #0 8008c9a: 60f8 str r0, [r7, #12] 8008c9c: 60b9 str r1, [r7, #8] 8008c9e: 607a str r2, [r7, #4] 8008ca0: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8008ca2: 2300 movs r3, #0 8008ca4: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Check the DMA peripheral handle */ if(hdma == NULL) 8008ca6: 68fb ldr r3, [r7, #12] 8008ca8: 2b00 cmp r3, #0 8008caa: d101 bne.n 8008cb0 { return HAL_ERROR; 8008cac: 2301 movs r3, #1 8008cae: e226 b.n 80090fe } /* Process locked */ __HAL_LOCK(hdma); 8008cb0: 68fb ldr r3, [r7, #12] 8008cb2: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8008cb6: 2b01 cmp r3, #1 8008cb8: d101 bne.n 8008cbe 8008cba: 2302 movs r3, #2 8008cbc: e21f b.n 80090fe 8008cbe: 68fb ldr r3, [r7, #12] 8008cc0: 2201 movs r2, #1 8008cc2: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 8008cc6: 68fb ldr r3, [r7, #12] 8008cc8: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8008ccc: b2db uxtb r3, r3 8008cce: 2b01 cmp r3, #1 8008cd0: f040 820a bne.w 80090e8 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8008cd4: 68fb ldr r3, [r7, #12] 8008cd6: 2202 movs r2, #2 8008cd8: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8008cdc: 68fb ldr r3, [r7, #12] 8008cde: 2200 movs r2, #0 8008ce0: 655a str r2, [r3, #84] @ 0x54 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8008ce2: 68fb ldr r3, [r7, #12] 8008ce4: 681b ldr r3, [r3, #0] 8008ce6: 4a68 ldr r2, [pc, #416] @ (8008e88 ) 8008ce8: 4293 cmp r3, r2 8008cea: d04a beq.n 8008d82 8008cec: 68fb ldr r3, [r7, #12] 8008cee: 681b ldr r3, [r3, #0] 8008cf0: 4a66 ldr r2, [pc, #408] @ (8008e8c ) 8008cf2: 4293 cmp r3, r2 8008cf4: d045 beq.n 8008d82 8008cf6: 68fb ldr r3, [r7, #12] 8008cf8: 681b ldr r3, [r3, #0] 8008cfa: 4a65 ldr r2, [pc, #404] @ (8008e90 ) 8008cfc: 4293 cmp r3, r2 8008cfe: d040 beq.n 8008d82 8008d00: 68fb ldr r3, [r7, #12] 8008d02: 681b ldr r3, [r3, #0] 8008d04: 4a63 ldr r2, [pc, #396] @ (8008e94 ) 8008d06: 4293 cmp r3, r2 8008d08: d03b beq.n 8008d82 8008d0a: 68fb ldr r3, [r7, #12] 8008d0c: 681b ldr r3, [r3, #0] 8008d0e: 4a62 ldr r2, [pc, #392] @ (8008e98 ) 8008d10: 4293 cmp r3, r2 8008d12: d036 beq.n 8008d82 8008d14: 68fb ldr r3, [r7, #12] 8008d16: 681b ldr r3, [r3, #0] 8008d18: 4a60 ldr r2, [pc, #384] @ (8008e9c ) 8008d1a: 4293 cmp r3, r2 8008d1c: d031 beq.n 8008d82 8008d1e: 68fb ldr r3, [r7, #12] 8008d20: 681b ldr r3, [r3, #0] 8008d22: 4a5f ldr r2, [pc, #380] @ (8008ea0 ) 8008d24: 4293 cmp r3, r2 8008d26: d02c beq.n 8008d82 8008d28: 68fb ldr r3, [r7, #12] 8008d2a: 681b ldr r3, [r3, #0] 8008d2c: 4a5d ldr r2, [pc, #372] @ (8008ea4 ) 8008d2e: 4293 cmp r3, r2 8008d30: d027 beq.n 8008d82 8008d32: 68fb ldr r3, [r7, #12] 8008d34: 681b ldr r3, [r3, #0] 8008d36: 4a5c ldr r2, [pc, #368] @ (8008ea8 ) 8008d38: 4293 cmp r3, r2 8008d3a: d022 beq.n 8008d82 8008d3c: 68fb ldr r3, [r7, #12] 8008d3e: 681b ldr r3, [r3, #0] 8008d40: 4a5a ldr r2, [pc, #360] @ (8008eac ) 8008d42: 4293 cmp r3, r2 8008d44: d01d beq.n 8008d82 8008d46: 68fb ldr r3, [r7, #12] 8008d48: 681b ldr r3, [r3, #0] 8008d4a: 4a59 ldr r2, [pc, #356] @ (8008eb0 ) 8008d4c: 4293 cmp r3, r2 8008d4e: d018 beq.n 8008d82 8008d50: 68fb ldr r3, [r7, #12] 8008d52: 681b ldr r3, [r3, #0] 8008d54: 4a57 ldr r2, [pc, #348] @ (8008eb4 ) 8008d56: 4293 cmp r3, r2 8008d58: d013 beq.n 8008d82 8008d5a: 68fb ldr r3, [r7, #12] 8008d5c: 681b ldr r3, [r3, #0] 8008d5e: 4a56 ldr r2, [pc, #344] @ (8008eb8 ) 8008d60: 4293 cmp r3, r2 8008d62: d00e beq.n 8008d82 8008d64: 68fb ldr r3, [r7, #12] 8008d66: 681b ldr r3, [r3, #0] 8008d68: 4a54 ldr r2, [pc, #336] @ (8008ebc ) 8008d6a: 4293 cmp r3, r2 8008d6c: d009 beq.n 8008d82 8008d6e: 68fb ldr r3, [r7, #12] 8008d70: 681b ldr r3, [r3, #0] 8008d72: 4a53 ldr r2, [pc, #332] @ (8008ec0 ) 8008d74: 4293 cmp r3, r2 8008d76: d004 beq.n 8008d82 8008d78: 68fb ldr r3, [r7, #12] 8008d7a: 681b ldr r3, [r3, #0] 8008d7c: 4a51 ldr r2, [pc, #324] @ (8008ec4 ) 8008d7e: 4293 cmp r3, r2 8008d80: d108 bne.n 8008d94 8008d82: 68fb ldr r3, [r7, #12] 8008d84: 681b ldr r3, [r3, #0] 8008d86: 681a ldr r2, [r3, #0] 8008d88: 68fb ldr r3, [r7, #12] 8008d8a: 681b ldr r3, [r3, #0] 8008d8c: f022 0201 bic.w r2, r2, #1 8008d90: 601a str r2, [r3, #0] 8008d92: e007 b.n 8008da4 8008d94: 68fb ldr r3, [r7, #12] 8008d96: 681b ldr r3, [r3, #0] 8008d98: 681a ldr r2, [r3, #0] 8008d9a: 68fb ldr r3, [r7, #12] 8008d9c: 681b ldr r3, [r3, #0] 8008d9e: f022 0201 bic.w r2, r2, #1 8008da2: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8008da4: 683b ldr r3, [r7, #0] 8008da6: 687a ldr r2, [r7, #4] 8008da8: 68b9 ldr r1, [r7, #8] 8008daa: 68f8 ldr r0, [r7, #12] 8008dac: f001 fe6a bl 800aa84 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8008db0: 68fb ldr r3, [r7, #12] 8008db2: 681b ldr r3, [r3, #0] 8008db4: 4a34 ldr r2, [pc, #208] @ (8008e88 ) 8008db6: 4293 cmp r3, r2 8008db8: d04a beq.n 8008e50 8008dba: 68fb ldr r3, [r7, #12] 8008dbc: 681b ldr r3, [r3, #0] 8008dbe: 4a33 ldr r2, [pc, #204] @ (8008e8c ) 8008dc0: 4293 cmp r3, r2 8008dc2: d045 beq.n 8008e50 8008dc4: 68fb ldr r3, [r7, #12] 8008dc6: 681b ldr r3, [r3, #0] 8008dc8: 4a31 ldr r2, [pc, #196] @ (8008e90 ) 8008dca: 4293 cmp r3, r2 8008dcc: d040 beq.n 8008e50 8008dce: 68fb ldr r3, [r7, #12] 8008dd0: 681b ldr r3, [r3, #0] 8008dd2: 4a30 ldr r2, [pc, #192] @ (8008e94 ) 8008dd4: 4293 cmp r3, r2 8008dd6: d03b beq.n 8008e50 8008dd8: 68fb ldr r3, [r7, #12] 8008dda: 681b ldr r3, [r3, #0] 8008ddc: 4a2e ldr r2, [pc, #184] @ (8008e98 ) 8008dde: 4293 cmp r3, r2 8008de0: d036 beq.n 8008e50 8008de2: 68fb ldr r3, [r7, #12] 8008de4: 681b ldr r3, [r3, #0] 8008de6: 4a2d ldr r2, [pc, #180] @ (8008e9c ) 8008de8: 4293 cmp r3, r2 8008dea: d031 beq.n 8008e50 8008dec: 68fb ldr r3, [r7, #12] 8008dee: 681b ldr r3, [r3, #0] 8008df0: 4a2b ldr r2, [pc, #172] @ (8008ea0 ) 8008df2: 4293 cmp r3, r2 8008df4: d02c beq.n 8008e50 8008df6: 68fb ldr r3, [r7, #12] 8008df8: 681b ldr r3, [r3, #0] 8008dfa: 4a2a ldr r2, [pc, #168] @ (8008ea4 ) 8008dfc: 4293 cmp r3, r2 8008dfe: d027 beq.n 8008e50 8008e00: 68fb ldr r3, [r7, #12] 8008e02: 681b ldr r3, [r3, #0] 8008e04: 4a28 ldr r2, [pc, #160] @ (8008ea8 ) 8008e06: 4293 cmp r3, r2 8008e08: d022 beq.n 8008e50 8008e0a: 68fb ldr r3, [r7, #12] 8008e0c: 681b ldr r3, [r3, #0] 8008e0e: 4a27 ldr r2, [pc, #156] @ (8008eac ) 8008e10: 4293 cmp r3, r2 8008e12: d01d beq.n 8008e50 8008e14: 68fb ldr r3, [r7, #12] 8008e16: 681b ldr r3, [r3, #0] 8008e18: 4a25 ldr r2, [pc, #148] @ (8008eb0 ) 8008e1a: 4293 cmp r3, r2 8008e1c: d018 beq.n 8008e50 8008e1e: 68fb ldr r3, [r7, #12] 8008e20: 681b ldr r3, [r3, #0] 8008e22: 4a24 ldr r2, [pc, #144] @ (8008eb4 ) 8008e24: 4293 cmp r3, r2 8008e26: d013 beq.n 8008e50 8008e28: 68fb ldr r3, [r7, #12] 8008e2a: 681b ldr r3, [r3, #0] 8008e2c: 4a22 ldr r2, [pc, #136] @ (8008eb8 ) 8008e2e: 4293 cmp r3, r2 8008e30: d00e beq.n 8008e50 8008e32: 68fb ldr r3, [r7, #12] 8008e34: 681b ldr r3, [r3, #0] 8008e36: 4a21 ldr r2, [pc, #132] @ (8008ebc ) 8008e38: 4293 cmp r3, r2 8008e3a: d009 beq.n 8008e50 8008e3c: 68fb ldr r3, [r7, #12] 8008e3e: 681b ldr r3, [r3, #0] 8008e40: 4a1f ldr r2, [pc, #124] @ (8008ec0 ) 8008e42: 4293 cmp r3, r2 8008e44: d004 beq.n 8008e50 8008e46: 68fb ldr r3, [r7, #12] 8008e48: 681b ldr r3, [r3, #0] 8008e4a: 4a1e ldr r2, [pc, #120] @ (8008ec4 ) 8008e4c: 4293 cmp r3, r2 8008e4e: d101 bne.n 8008e54 8008e50: 2301 movs r3, #1 8008e52: e000 b.n 8008e56 8008e54: 2300 movs r3, #0 8008e56: 2b00 cmp r3, #0 8008e58: d036 beq.n 8008ec8 { /* Enable Common interrupts*/ MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 8008e5a: 68fb ldr r3, [r7, #12] 8008e5c: 681b ldr r3, [r3, #0] 8008e5e: 681b ldr r3, [r3, #0] 8008e60: f023 021e bic.w r2, r3, #30 8008e64: 68fb ldr r3, [r7, #12] 8008e66: 681b ldr r3, [r3, #0] 8008e68: f042 0216 orr.w r2, r2, #22 8008e6c: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8008e6e: 68fb ldr r3, [r7, #12] 8008e70: 6c1b ldr r3, [r3, #64] @ 0x40 8008e72: 2b00 cmp r3, #0 8008e74: d03e beq.n 8008ef4 { /* Enable Half Transfer IT if corresponding Callback is set */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; 8008e76: 68fb ldr r3, [r7, #12] 8008e78: 681b ldr r3, [r3, #0] 8008e7a: 681a ldr r2, [r3, #0] 8008e7c: 68fb ldr r3, [r7, #12] 8008e7e: 681b ldr r3, [r3, #0] 8008e80: f042 0208 orr.w r2, r2, #8 8008e84: 601a str r2, [r3, #0] 8008e86: e035 b.n 8008ef4 8008e88: 40020010 .word 0x40020010 8008e8c: 40020028 .word 0x40020028 8008e90: 40020040 .word 0x40020040 8008e94: 40020058 .word 0x40020058 8008e98: 40020070 .word 0x40020070 8008e9c: 40020088 .word 0x40020088 8008ea0: 400200a0 .word 0x400200a0 8008ea4: 400200b8 .word 0x400200b8 8008ea8: 40020410 .word 0x40020410 8008eac: 40020428 .word 0x40020428 8008eb0: 40020440 .word 0x40020440 8008eb4: 40020458 .word 0x40020458 8008eb8: 40020470 .word 0x40020470 8008ebc: 40020488 .word 0x40020488 8008ec0: 400204a0 .word 0x400204a0 8008ec4: 400204b8 .word 0x400204b8 } } else /* BDMA channel */ { /* Enable Common interrupts */ MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE)); 8008ec8: 68fb ldr r3, [r7, #12] 8008eca: 681b ldr r3, [r3, #0] 8008ecc: 681b ldr r3, [r3, #0] 8008ece: f023 020e bic.w r2, r3, #14 8008ed2: 68fb ldr r3, [r7, #12] 8008ed4: 681b ldr r3, [r3, #0] 8008ed6: f042 020a orr.w r2, r2, #10 8008eda: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8008edc: 68fb ldr r3, [r7, #12] 8008ede: 6c1b ldr r3, [r3, #64] @ 0x40 8008ee0: 2b00 cmp r3, #0 8008ee2: d007 beq.n 8008ef4 { /*Enable Half Transfer IT if corresponding Callback is set */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; 8008ee4: 68fb ldr r3, [r7, #12] 8008ee6: 681b ldr r3, [r3, #0] 8008ee8: 681a ldr r2, [r3, #0] 8008eea: 68fb ldr r3, [r7, #12] 8008eec: 681b ldr r3, [r3, #0] 8008eee: f042 0204 orr.w r2, r2, #4 8008ef2: 601a str r2, [r3, #0] } } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8008ef4: 68fb ldr r3, [r7, #12] 8008ef6: 681b ldr r3, [r3, #0] 8008ef8: 4a83 ldr r2, [pc, #524] @ (8009108 ) 8008efa: 4293 cmp r3, r2 8008efc: d072 beq.n 8008fe4 8008efe: 68fb ldr r3, [r7, #12] 8008f00: 681b ldr r3, [r3, #0] 8008f02: 4a82 ldr r2, [pc, #520] @ (800910c ) 8008f04: 4293 cmp r3, r2 8008f06: d06d beq.n 8008fe4 8008f08: 68fb ldr r3, [r7, #12] 8008f0a: 681b ldr r3, [r3, #0] 8008f0c: 4a80 ldr r2, [pc, #512] @ (8009110 ) 8008f0e: 4293 cmp r3, r2 8008f10: d068 beq.n 8008fe4 8008f12: 68fb ldr r3, [r7, #12] 8008f14: 681b ldr r3, [r3, #0] 8008f16: 4a7f ldr r2, [pc, #508] @ (8009114 ) 8008f18: 4293 cmp r3, r2 8008f1a: d063 beq.n 8008fe4 8008f1c: 68fb ldr r3, [r7, #12] 8008f1e: 681b ldr r3, [r3, #0] 8008f20: 4a7d ldr r2, [pc, #500] @ (8009118 ) 8008f22: 4293 cmp r3, r2 8008f24: d05e beq.n 8008fe4 8008f26: 68fb ldr r3, [r7, #12] 8008f28: 681b ldr r3, [r3, #0] 8008f2a: 4a7c ldr r2, [pc, #496] @ (800911c ) 8008f2c: 4293 cmp r3, r2 8008f2e: d059 beq.n 8008fe4 8008f30: 68fb ldr r3, [r7, #12] 8008f32: 681b ldr r3, [r3, #0] 8008f34: 4a7a ldr r2, [pc, #488] @ (8009120 ) 8008f36: 4293 cmp r3, r2 8008f38: d054 beq.n 8008fe4 8008f3a: 68fb ldr r3, [r7, #12] 8008f3c: 681b ldr r3, [r3, #0] 8008f3e: 4a79 ldr r2, [pc, #484] @ (8009124 ) 8008f40: 4293 cmp r3, r2 8008f42: d04f beq.n 8008fe4 8008f44: 68fb ldr r3, [r7, #12] 8008f46: 681b ldr r3, [r3, #0] 8008f48: 4a77 ldr r2, [pc, #476] @ (8009128 ) 8008f4a: 4293 cmp r3, r2 8008f4c: d04a beq.n 8008fe4 8008f4e: 68fb ldr r3, [r7, #12] 8008f50: 681b ldr r3, [r3, #0] 8008f52: 4a76 ldr r2, [pc, #472] @ (800912c ) 8008f54: 4293 cmp r3, r2 8008f56: d045 beq.n 8008fe4 8008f58: 68fb ldr r3, [r7, #12] 8008f5a: 681b ldr r3, [r3, #0] 8008f5c: 4a74 ldr r2, [pc, #464] @ (8009130 ) 8008f5e: 4293 cmp r3, r2 8008f60: d040 beq.n 8008fe4 8008f62: 68fb ldr r3, [r7, #12] 8008f64: 681b ldr r3, [r3, #0] 8008f66: 4a73 ldr r2, [pc, #460] @ (8009134 ) 8008f68: 4293 cmp r3, r2 8008f6a: d03b beq.n 8008fe4 8008f6c: 68fb ldr r3, [r7, #12] 8008f6e: 681b ldr r3, [r3, #0] 8008f70: 4a71 ldr r2, [pc, #452] @ (8009138 ) 8008f72: 4293 cmp r3, r2 8008f74: d036 beq.n 8008fe4 8008f76: 68fb ldr r3, [r7, #12] 8008f78: 681b ldr r3, [r3, #0] 8008f7a: 4a70 ldr r2, [pc, #448] @ (800913c ) 8008f7c: 4293 cmp r3, r2 8008f7e: d031 beq.n 8008fe4 8008f80: 68fb ldr r3, [r7, #12] 8008f82: 681b ldr r3, [r3, #0] 8008f84: 4a6e ldr r2, [pc, #440] @ (8009140 ) 8008f86: 4293 cmp r3, r2 8008f88: d02c beq.n 8008fe4 8008f8a: 68fb ldr r3, [r7, #12] 8008f8c: 681b ldr r3, [r3, #0] 8008f8e: 4a6d ldr r2, [pc, #436] @ (8009144 ) 8008f90: 4293 cmp r3, r2 8008f92: d027 beq.n 8008fe4 8008f94: 68fb ldr r3, [r7, #12] 8008f96: 681b ldr r3, [r3, #0] 8008f98: 4a6b ldr r2, [pc, #428] @ (8009148 ) 8008f9a: 4293 cmp r3, r2 8008f9c: d022 beq.n 8008fe4 8008f9e: 68fb ldr r3, [r7, #12] 8008fa0: 681b ldr r3, [r3, #0] 8008fa2: 4a6a ldr r2, [pc, #424] @ (800914c ) 8008fa4: 4293 cmp r3, r2 8008fa6: d01d beq.n 8008fe4 8008fa8: 68fb ldr r3, [r7, #12] 8008faa: 681b ldr r3, [r3, #0] 8008fac: 4a68 ldr r2, [pc, #416] @ (8009150 ) 8008fae: 4293 cmp r3, r2 8008fb0: d018 beq.n 8008fe4 8008fb2: 68fb ldr r3, [r7, #12] 8008fb4: 681b ldr r3, [r3, #0] 8008fb6: 4a67 ldr r2, [pc, #412] @ (8009154 ) 8008fb8: 4293 cmp r3, r2 8008fba: d013 beq.n 8008fe4 8008fbc: 68fb ldr r3, [r7, #12] 8008fbe: 681b ldr r3, [r3, #0] 8008fc0: 4a65 ldr r2, [pc, #404] @ (8009158 ) 8008fc2: 4293 cmp r3, r2 8008fc4: d00e beq.n 8008fe4 8008fc6: 68fb ldr r3, [r7, #12] 8008fc8: 681b ldr r3, [r3, #0] 8008fca: 4a64 ldr r2, [pc, #400] @ (800915c ) 8008fcc: 4293 cmp r3, r2 8008fce: d009 beq.n 8008fe4 8008fd0: 68fb ldr r3, [r7, #12] 8008fd2: 681b ldr r3, [r3, #0] 8008fd4: 4a62 ldr r2, [pc, #392] @ (8009160 ) 8008fd6: 4293 cmp r3, r2 8008fd8: d004 beq.n 8008fe4 8008fda: 68fb ldr r3, [r7, #12] 8008fdc: 681b ldr r3, [r3, #0] 8008fde: 4a61 ldr r2, [pc, #388] @ (8009164 ) 8008fe0: 4293 cmp r3, r2 8008fe2: d101 bne.n 8008fe8 8008fe4: 2301 movs r3, #1 8008fe6: e000 b.n 8008fea 8008fe8: 2300 movs r3, #0 8008fea: 2b00 cmp r3, #0 8008fec: d01a beq.n 8009024 { /* Check if DMAMUX Synchronization is enabled */ if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) 8008fee: 68fb ldr r3, [r7, #12] 8008ff0: 6e1b ldr r3, [r3, #96] @ 0x60 8008ff2: 681b ldr r3, [r3, #0] 8008ff4: f403 3380 and.w r3, r3, #65536 @ 0x10000 8008ff8: 2b00 cmp r3, #0 8008ffa: d007 beq.n 800900c { /* Enable DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; 8008ffc: 68fb ldr r3, [r7, #12] 8008ffe: 6e1b ldr r3, [r3, #96] @ 0x60 8009000: 681a ldr r2, [r3, #0] 8009002: 68fb ldr r3, [r7, #12] 8009004: 6e1b ldr r3, [r3, #96] @ 0x60 8009006: f442 7280 orr.w r2, r2, #256 @ 0x100 800900a: 601a str r2, [r3, #0] } if(hdma->DMAmuxRequestGen != 0U) 800900c: 68fb ldr r3, [r7, #12] 800900e: 6edb ldr r3, [r3, #108] @ 0x6c 8009010: 2b00 cmp r3, #0 8009012: d007 beq.n 8009024 { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 8009014: 68fb ldr r3, [r7, #12] 8009016: 6edb ldr r3, [r3, #108] @ 0x6c 8009018: 681a ldr r2, [r3, #0] 800901a: 68fb ldr r3, [r7, #12] 800901c: 6edb ldr r3, [r3, #108] @ 0x6c 800901e: f442 7280 orr.w r2, r2, #256 @ 0x100 8009022: 601a str r2, [r3, #0] } } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8009024: 68fb ldr r3, [r7, #12] 8009026: 681b ldr r3, [r3, #0] 8009028: 4a37 ldr r2, [pc, #220] @ (8009108 ) 800902a: 4293 cmp r3, r2 800902c: d04a beq.n 80090c4 800902e: 68fb ldr r3, [r7, #12] 8009030: 681b ldr r3, [r3, #0] 8009032: 4a36 ldr r2, [pc, #216] @ (800910c ) 8009034: 4293 cmp r3, r2 8009036: d045 beq.n 80090c4 8009038: 68fb ldr r3, [r7, #12] 800903a: 681b ldr r3, [r3, #0] 800903c: 4a34 ldr r2, [pc, #208] @ (8009110 ) 800903e: 4293 cmp r3, r2 8009040: d040 beq.n 80090c4 8009042: 68fb ldr r3, [r7, #12] 8009044: 681b ldr r3, [r3, #0] 8009046: 4a33 ldr r2, [pc, #204] @ (8009114 ) 8009048: 4293 cmp r3, r2 800904a: d03b beq.n 80090c4 800904c: 68fb ldr r3, [r7, #12] 800904e: 681b ldr r3, [r3, #0] 8009050: 4a31 ldr r2, [pc, #196] @ (8009118 ) 8009052: 4293 cmp r3, r2 8009054: d036 beq.n 80090c4 8009056: 68fb ldr r3, [r7, #12] 8009058: 681b ldr r3, [r3, #0] 800905a: 4a30 ldr r2, [pc, #192] @ (800911c ) 800905c: 4293 cmp r3, r2 800905e: d031 beq.n 80090c4 8009060: 68fb ldr r3, [r7, #12] 8009062: 681b ldr r3, [r3, #0] 8009064: 4a2e ldr r2, [pc, #184] @ (8009120 ) 8009066: 4293 cmp r3, r2 8009068: d02c beq.n 80090c4 800906a: 68fb ldr r3, [r7, #12] 800906c: 681b ldr r3, [r3, #0] 800906e: 4a2d ldr r2, [pc, #180] @ (8009124 ) 8009070: 4293 cmp r3, r2 8009072: d027 beq.n 80090c4 8009074: 68fb ldr r3, [r7, #12] 8009076: 681b ldr r3, [r3, #0] 8009078: 4a2b ldr r2, [pc, #172] @ (8009128 ) 800907a: 4293 cmp r3, r2 800907c: d022 beq.n 80090c4 800907e: 68fb ldr r3, [r7, #12] 8009080: 681b ldr r3, [r3, #0] 8009082: 4a2a ldr r2, [pc, #168] @ (800912c ) 8009084: 4293 cmp r3, r2 8009086: d01d beq.n 80090c4 8009088: 68fb ldr r3, [r7, #12] 800908a: 681b ldr r3, [r3, #0] 800908c: 4a28 ldr r2, [pc, #160] @ (8009130 ) 800908e: 4293 cmp r3, r2 8009090: d018 beq.n 80090c4 8009092: 68fb ldr r3, [r7, #12] 8009094: 681b ldr r3, [r3, #0] 8009096: 4a27 ldr r2, [pc, #156] @ (8009134 ) 8009098: 4293 cmp r3, r2 800909a: d013 beq.n 80090c4 800909c: 68fb ldr r3, [r7, #12] 800909e: 681b ldr r3, [r3, #0] 80090a0: 4a25 ldr r2, [pc, #148] @ (8009138 ) 80090a2: 4293 cmp r3, r2 80090a4: d00e beq.n 80090c4 80090a6: 68fb ldr r3, [r7, #12] 80090a8: 681b ldr r3, [r3, #0] 80090aa: 4a24 ldr r2, [pc, #144] @ (800913c ) 80090ac: 4293 cmp r3, r2 80090ae: d009 beq.n 80090c4 80090b0: 68fb ldr r3, [r7, #12] 80090b2: 681b ldr r3, [r3, #0] 80090b4: 4a22 ldr r2, [pc, #136] @ (8009140 ) 80090b6: 4293 cmp r3, r2 80090b8: d004 beq.n 80090c4 80090ba: 68fb ldr r3, [r7, #12] 80090bc: 681b ldr r3, [r3, #0] 80090be: 4a21 ldr r2, [pc, #132] @ (8009144 ) 80090c0: 4293 cmp r3, r2 80090c2: d108 bne.n 80090d6 80090c4: 68fb ldr r3, [r7, #12] 80090c6: 681b ldr r3, [r3, #0] 80090c8: 681a ldr r2, [r3, #0] 80090ca: 68fb ldr r3, [r7, #12] 80090cc: 681b ldr r3, [r3, #0] 80090ce: f042 0201 orr.w r2, r2, #1 80090d2: 601a str r2, [r3, #0] 80090d4: e012 b.n 80090fc 80090d6: 68fb ldr r3, [r7, #12] 80090d8: 681b ldr r3, [r3, #0] 80090da: 681a ldr r2, [r3, #0] 80090dc: 68fb ldr r3, [r7, #12] 80090de: 681b ldr r3, [r3, #0] 80090e0: f042 0201 orr.w r2, r2, #1 80090e4: 601a str r2, [r3, #0] 80090e6: e009 b.n 80090fc } else { /* Set the error code to busy */ hdma->ErrorCode = HAL_DMA_ERROR_BUSY; 80090e8: 68fb ldr r3, [r7, #12] 80090ea: f44f 6200 mov.w r2, #2048 @ 0x800 80090ee: 655a str r2, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hdma); 80090f0: 68fb ldr r3, [r7, #12] 80090f2: 2200 movs r2, #0 80090f4: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Return error status */ status = HAL_ERROR; 80090f8: 2301 movs r3, #1 80090fa: 75fb strb r3, [r7, #23] } return status; 80090fc: 7dfb ldrb r3, [r7, #23] } 80090fe: 4618 mov r0, r3 8009100: 3718 adds r7, #24 8009102: 46bd mov sp, r7 8009104: bd80 pop {r7, pc} 8009106: bf00 nop 8009108: 40020010 .word 0x40020010 800910c: 40020028 .word 0x40020028 8009110: 40020040 .word 0x40020040 8009114: 40020058 .word 0x40020058 8009118: 40020070 .word 0x40020070 800911c: 40020088 .word 0x40020088 8009120: 400200a0 .word 0x400200a0 8009124: 400200b8 .word 0x400200b8 8009128: 40020410 .word 0x40020410 800912c: 40020428 .word 0x40020428 8009130: 40020440 .word 0x40020440 8009134: 40020458 .word 0x40020458 8009138: 40020470 .word 0x40020470 800913c: 40020488 .word 0x40020488 8009140: 400204a0 .word 0x400204a0 8009144: 400204b8 .word 0x400204b8 8009148: 58025408 .word 0x58025408 800914c: 5802541c .word 0x5802541c 8009150: 58025430 .word 0x58025430 8009154: 58025444 .word 0x58025444 8009158: 58025458 .word 0x58025458 800915c: 5802546c .word 0x5802546c 8009160: 58025480 .word 0x58025480 8009164: 58025494 .word 0x58025494 08009168 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8009168: b580 push {r7, lr} 800916a: b086 sub sp, #24 800916c: af00 add r7, sp, #0 800916e: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; const __IO uint32_t *enableRegister; uint32_t tickstart = HAL_GetTick(); 8009170: f7fc fe98 bl 8005ea4 8009174: 6138 str r0, [r7, #16] /* Check the DMA peripheral handle */ if(hdma == NULL) 8009176: 687b ldr r3, [r7, #4] 8009178: 2b00 cmp r3, #0 800917a: d101 bne.n 8009180 { return HAL_ERROR; 800917c: 2301 movs r3, #1 800917e: e2dc b.n 800973a } /* Check the DMA peripheral state */ if(hdma->State != HAL_DMA_STATE_BUSY) 8009180: 687b ldr r3, [r7, #4] 8009182: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8009186: b2db uxtb r3, r3 8009188: 2b02 cmp r3, #2 800918a: d008 beq.n 800919e { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800918c: 687b ldr r3, [r7, #4] 800918e: 2280 movs r2, #128 @ 0x80 8009190: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009192: 687b ldr r3, [r7, #4] 8009194: 2200 movs r2, #0 8009196: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 800919a: 2301 movs r3, #1 800919c: e2cd b.n 800973a } else { /* Disable all the transfer interrupts */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800919e: 687b ldr r3, [r7, #4] 80091a0: 681b ldr r3, [r3, #0] 80091a2: 4a76 ldr r2, [pc, #472] @ (800937c ) 80091a4: 4293 cmp r3, r2 80091a6: d04a beq.n 800923e 80091a8: 687b ldr r3, [r7, #4] 80091aa: 681b ldr r3, [r3, #0] 80091ac: 4a74 ldr r2, [pc, #464] @ (8009380 ) 80091ae: 4293 cmp r3, r2 80091b0: d045 beq.n 800923e 80091b2: 687b ldr r3, [r7, #4] 80091b4: 681b ldr r3, [r3, #0] 80091b6: 4a73 ldr r2, [pc, #460] @ (8009384 ) 80091b8: 4293 cmp r3, r2 80091ba: d040 beq.n 800923e 80091bc: 687b ldr r3, [r7, #4] 80091be: 681b ldr r3, [r3, #0] 80091c0: 4a71 ldr r2, [pc, #452] @ (8009388 ) 80091c2: 4293 cmp r3, r2 80091c4: d03b beq.n 800923e 80091c6: 687b ldr r3, [r7, #4] 80091c8: 681b ldr r3, [r3, #0] 80091ca: 4a70 ldr r2, [pc, #448] @ (800938c ) 80091cc: 4293 cmp r3, r2 80091ce: d036 beq.n 800923e 80091d0: 687b ldr r3, [r7, #4] 80091d2: 681b ldr r3, [r3, #0] 80091d4: 4a6e ldr r2, [pc, #440] @ (8009390 ) 80091d6: 4293 cmp r3, r2 80091d8: d031 beq.n 800923e 80091da: 687b ldr r3, [r7, #4] 80091dc: 681b ldr r3, [r3, #0] 80091de: 4a6d ldr r2, [pc, #436] @ (8009394 ) 80091e0: 4293 cmp r3, r2 80091e2: d02c beq.n 800923e 80091e4: 687b ldr r3, [r7, #4] 80091e6: 681b ldr r3, [r3, #0] 80091e8: 4a6b ldr r2, [pc, #428] @ (8009398 ) 80091ea: 4293 cmp r3, r2 80091ec: d027 beq.n 800923e 80091ee: 687b ldr r3, [r7, #4] 80091f0: 681b ldr r3, [r3, #0] 80091f2: 4a6a ldr r2, [pc, #424] @ (800939c ) 80091f4: 4293 cmp r3, r2 80091f6: d022 beq.n 800923e 80091f8: 687b ldr r3, [r7, #4] 80091fa: 681b ldr r3, [r3, #0] 80091fc: 4a68 ldr r2, [pc, #416] @ (80093a0 ) 80091fe: 4293 cmp r3, r2 8009200: d01d beq.n 800923e 8009202: 687b ldr r3, [r7, #4] 8009204: 681b ldr r3, [r3, #0] 8009206: 4a67 ldr r2, [pc, #412] @ (80093a4 ) 8009208: 4293 cmp r3, r2 800920a: d018 beq.n 800923e 800920c: 687b ldr r3, [r7, #4] 800920e: 681b ldr r3, [r3, #0] 8009210: 4a65 ldr r2, [pc, #404] @ (80093a8 ) 8009212: 4293 cmp r3, r2 8009214: d013 beq.n 800923e 8009216: 687b ldr r3, [r7, #4] 8009218: 681b ldr r3, [r3, #0] 800921a: 4a64 ldr r2, [pc, #400] @ (80093ac ) 800921c: 4293 cmp r3, r2 800921e: d00e beq.n 800923e 8009220: 687b ldr r3, [r7, #4] 8009222: 681b ldr r3, [r3, #0] 8009224: 4a62 ldr r2, [pc, #392] @ (80093b0 ) 8009226: 4293 cmp r3, r2 8009228: d009 beq.n 800923e 800922a: 687b ldr r3, [r7, #4] 800922c: 681b ldr r3, [r3, #0] 800922e: 4a61 ldr r2, [pc, #388] @ (80093b4 ) 8009230: 4293 cmp r3, r2 8009232: d004 beq.n 800923e 8009234: 687b ldr r3, [r7, #4] 8009236: 681b ldr r3, [r3, #0] 8009238: 4a5f ldr r2, [pc, #380] @ (80093b8 ) 800923a: 4293 cmp r3, r2 800923c: d101 bne.n 8009242 800923e: 2301 movs r3, #1 8009240: e000 b.n 8009244 8009242: 2300 movs r3, #0 8009244: 2b00 cmp r3, #0 8009246: d013 beq.n 8009270 { /* Disable DMA All Interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 8009248: 687b ldr r3, [r7, #4] 800924a: 681b ldr r3, [r3, #0] 800924c: 681a ldr r2, [r3, #0] 800924e: 687b ldr r3, [r7, #4] 8009250: 681b ldr r3, [r3, #0] 8009252: f022 021e bic.w r2, r2, #30 8009256: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 8009258: 687b ldr r3, [r7, #4] 800925a: 681b ldr r3, [r3, #0] 800925c: 695a ldr r2, [r3, #20] 800925e: 687b ldr r3, [r7, #4] 8009260: 681b ldr r3, [r3, #0] 8009262: f022 0280 bic.w r2, r2, #128 @ 0x80 8009266: 615a str r2, [r3, #20] enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); 8009268: 687b ldr r3, [r7, #4] 800926a: 681b ldr r3, [r3, #0] 800926c: 617b str r3, [r7, #20] 800926e: e00a b.n 8009286 } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 8009270: 687b ldr r3, [r7, #4] 8009272: 681b ldr r3, [r3, #0] 8009274: 681a ldr r2, [r3, #0] 8009276: 687b ldr r3, [r7, #4] 8009278: 681b ldr r3, [r3, #0] 800927a: f022 020e bic.w r2, r2, #14 800927e: 601a str r2, [r3, #0] enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); 8009280: 687b ldr r3, [r7, #4] 8009282: 681b ldr r3, [r3, #0] 8009284: 617b str r3, [r7, #20] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8009286: 687b ldr r3, [r7, #4] 8009288: 681b ldr r3, [r3, #0] 800928a: 4a3c ldr r2, [pc, #240] @ (800937c ) 800928c: 4293 cmp r3, r2 800928e: d072 beq.n 8009376 8009290: 687b ldr r3, [r7, #4] 8009292: 681b ldr r3, [r3, #0] 8009294: 4a3a ldr r2, [pc, #232] @ (8009380 ) 8009296: 4293 cmp r3, r2 8009298: d06d beq.n 8009376 800929a: 687b ldr r3, [r7, #4] 800929c: 681b ldr r3, [r3, #0] 800929e: 4a39 ldr r2, [pc, #228] @ (8009384 ) 80092a0: 4293 cmp r3, r2 80092a2: d068 beq.n 8009376 80092a4: 687b ldr r3, [r7, #4] 80092a6: 681b ldr r3, [r3, #0] 80092a8: 4a37 ldr r2, [pc, #220] @ (8009388 ) 80092aa: 4293 cmp r3, r2 80092ac: d063 beq.n 8009376 80092ae: 687b ldr r3, [r7, #4] 80092b0: 681b ldr r3, [r3, #0] 80092b2: 4a36 ldr r2, [pc, #216] @ (800938c ) 80092b4: 4293 cmp r3, r2 80092b6: d05e beq.n 8009376 80092b8: 687b ldr r3, [r7, #4] 80092ba: 681b ldr r3, [r3, #0] 80092bc: 4a34 ldr r2, [pc, #208] @ (8009390 ) 80092be: 4293 cmp r3, r2 80092c0: d059 beq.n 8009376 80092c2: 687b ldr r3, [r7, #4] 80092c4: 681b ldr r3, [r3, #0] 80092c6: 4a33 ldr r2, [pc, #204] @ (8009394 ) 80092c8: 4293 cmp r3, r2 80092ca: d054 beq.n 8009376 80092cc: 687b ldr r3, [r7, #4] 80092ce: 681b ldr r3, [r3, #0] 80092d0: 4a31 ldr r2, [pc, #196] @ (8009398 ) 80092d2: 4293 cmp r3, r2 80092d4: d04f beq.n 8009376 80092d6: 687b ldr r3, [r7, #4] 80092d8: 681b ldr r3, [r3, #0] 80092da: 4a30 ldr r2, [pc, #192] @ (800939c ) 80092dc: 4293 cmp r3, r2 80092de: d04a beq.n 8009376 80092e0: 687b ldr r3, [r7, #4] 80092e2: 681b ldr r3, [r3, #0] 80092e4: 4a2e ldr r2, [pc, #184] @ (80093a0 ) 80092e6: 4293 cmp r3, r2 80092e8: d045 beq.n 8009376 80092ea: 687b ldr r3, [r7, #4] 80092ec: 681b ldr r3, [r3, #0] 80092ee: 4a2d ldr r2, [pc, #180] @ (80093a4 ) 80092f0: 4293 cmp r3, r2 80092f2: d040 beq.n 8009376 80092f4: 687b ldr r3, [r7, #4] 80092f6: 681b ldr r3, [r3, #0] 80092f8: 4a2b ldr r2, [pc, #172] @ (80093a8 ) 80092fa: 4293 cmp r3, r2 80092fc: d03b beq.n 8009376 80092fe: 687b ldr r3, [r7, #4] 8009300: 681b ldr r3, [r3, #0] 8009302: 4a2a ldr r2, [pc, #168] @ (80093ac ) 8009304: 4293 cmp r3, r2 8009306: d036 beq.n 8009376 8009308: 687b ldr r3, [r7, #4] 800930a: 681b ldr r3, [r3, #0] 800930c: 4a28 ldr r2, [pc, #160] @ (80093b0 ) 800930e: 4293 cmp r3, r2 8009310: d031 beq.n 8009376 8009312: 687b ldr r3, [r7, #4] 8009314: 681b ldr r3, [r3, #0] 8009316: 4a27 ldr r2, [pc, #156] @ (80093b4 ) 8009318: 4293 cmp r3, r2 800931a: d02c beq.n 8009376 800931c: 687b ldr r3, [r7, #4] 800931e: 681b ldr r3, [r3, #0] 8009320: 4a25 ldr r2, [pc, #148] @ (80093b8 ) 8009322: 4293 cmp r3, r2 8009324: d027 beq.n 8009376 8009326: 687b ldr r3, [r7, #4] 8009328: 681b ldr r3, [r3, #0] 800932a: 4a24 ldr r2, [pc, #144] @ (80093bc ) 800932c: 4293 cmp r3, r2 800932e: d022 beq.n 8009376 8009330: 687b ldr r3, [r7, #4] 8009332: 681b ldr r3, [r3, #0] 8009334: 4a22 ldr r2, [pc, #136] @ (80093c0 ) 8009336: 4293 cmp r3, r2 8009338: d01d beq.n 8009376 800933a: 687b ldr r3, [r7, #4] 800933c: 681b ldr r3, [r3, #0] 800933e: 4a21 ldr r2, [pc, #132] @ (80093c4 ) 8009340: 4293 cmp r3, r2 8009342: d018 beq.n 8009376 8009344: 687b ldr r3, [r7, #4] 8009346: 681b ldr r3, [r3, #0] 8009348: 4a1f ldr r2, [pc, #124] @ (80093c8 ) 800934a: 4293 cmp r3, r2 800934c: d013 beq.n 8009376 800934e: 687b ldr r3, [r7, #4] 8009350: 681b ldr r3, [r3, #0] 8009352: 4a1e ldr r2, [pc, #120] @ (80093cc ) 8009354: 4293 cmp r3, r2 8009356: d00e beq.n 8009376 8009358: 687b ldr r3, [r7, #4] 800935a: 681b ldr r3, [r3, #0] 800935c: 4a1c ldr r2, [pc, #112] @ (80093d0 ) 800935e: 4293 cmp r3, r2 8009360: d009 beq.n 8009376 8009362: 687b ldr r3, [r7, #4] 8009364: 681b ldr r3, [r3, #0] 8009366: 4a1b ldr r2, [pc, #108] @ (80093d4 ) 8009368: 4293 cmp r3, r2 800936a: d004 beq.n 8009376 800936c: 687b ldr r3, [r7, #4] 800936e: 681b ldr r3, [r3, #0] 8009370: 4a19 ldr r2, [pc, #100] @ (80093d8 ) 8009372: 4293 cmp r3, r2 8009374: d132 bne.n 80093dc 8009376: 2301 movs r3, #1 8009378: e031 b.n 80093de 800937a: bf00 nop 800937c: 40020010 .word 0x40020010 8009380: 40020028 .word 0x40020028 8009384: 40020040 .word 0x40020040 8009388: 40020058 .word 0x40020058 800938c: 40020070 .word 0x40020070 8009390: 40020088 .word 0x40020088 8009394: 400200a0 .word 0x400200a0 8009398: 400200b8 .word 0x400200b8 800939c: 40020410 .word 0x40020410 80093a0: 40020428 .word 0x40020428 80093a4: 40020440 .word 0x40020440 80093a8: 40020458 .word 0x40020458 80093ac: 40020470 .word 0x40020470 80093b0: 40020488 .word 0x40020488 80093b4: 400204a0 .word 0x400204a0 80093b8: 400204b8 .word 0x400204b8 80093bc: 58025408 .word 0x58025408 80093c0: 5802541c .word 0x5802541c 80093c4: 58025430 .word 0x58025430 80093c8: 58025444 .word 0x58025444 80093cc: 58025458 .word 0x58025458 80093d0: 5802546c .word 0x5802546c 80093d4: 58025480 .word 0x58025480 80093d8: 58025494 .word 0x58025494 80093dc: 2300 movs r3, #0 80093de: 2b00 cmp r3, #0 80093e0: d007 beq.n 80093f2 { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 80093e2: 687b ldr r3, [r7, #4] 80093e4: 6e1b ldr r3, [r3, #96] @ 0x60 80093e6: 681a ldr r2, [r3, #0] 80093e8: 687b ldr r3, [r7, #4] 80093ea: 6e1b ldr r3, [r3, #96] @ 0x60 80093ec: f422 7280 bic.w r2, r2, #256 @ 0x100 80093f0: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80093f2: 687b ldr r3, [r7, #4] 80093f4: 681b ldr r3, [r3, #0] 80093f6: 4a6d ldr r2, [pc, #436] @ (80095ac ) 80093f8: 4293 cmp r3, r2 80093fa: d04a beq.n 8009492 80093fc: 687b ldr r3, [r7, #4] 80093fe: 681b ldr r3, [r3, #0] 8009400: 4a6b ldr r2, [pc, #428] @ (80095b0 ) 8009402: 4293 cmp r3, r2 8009404: d045 beq.n 8009492 8009406: 687b ldr r3, [r7, #4] 8009408: 681b ldr r3, [r3, #0] 800940a: 4a6a ldr r2, [pc, #424] @ (80095b4 ) 800940c: 4293 cmp r3, r2 800940e: d040 beq.n 8009492 8009410: 687b ldr r3, [r7, #4] 8009412: 681b ldr r3, [r3, #0] 8009414: 4a68 ldr r2, [pc, #416] @ (80095b8 ) 8009416: 4293 cmp r3, r2 8009418: d03b beq.n 8009492 800941a: 687b ldr r3, [r7, #4] 800941c: 681b ldr r3, [r3, #0] 800941e: 4a67 ldr r2, [pc, #412] @ (80095bc ) 8009420: 4293 cmp r3, r2 8009422: d036 beq.n 8009492 8009424: 687b ldr r3, [r7, #4] 8009426: 681b ldr r3, [r3, #0] 8009428: 4a65 ldr r2, [pc, #404] @ (80095c0 ) 800942a: 4293 cmp r3, r2 800942c: d031 beq.n 8009492 800942e: 687b ldr r3, [r7, #4] 8009430: 681b ldr r3, [r3, #0] 8009432: 4a64 ldr r2, [pc, #400] @ (80095c4 ) 8009434: 4293 cmp r3, r2 8009436: d02c beq.n 8009492 8009438: 687b ldr r3, [r7, #4] 800943a: 681b ldr r3, [r3, #0] 800943c: 4a62 ldr r2, [pc, #392] @ (80095c8 ) 800943e: 4293 cmp r3, r2 8009440: d027 beq.n 8009492 8009442: 687b ldr r3, [r7, #4] 8009444: 681b ldr r3, [r3, #0] 8009446: 4a61 ldr r2, [pc, #388] @ (80095cc ) 8009448: 4293 cmp r3, r2 800944a: d022 beq.n 8009492 800944c: 687b ldr r3, [r7, #4] 800944e: 681b ldr r3, [r3, #0] 8009450: 4a5f ldr r2, [pc, #380] @ (80095d0 ) 8009452: 4293 cmp r3, r2 8009454: d01d beq.n 8009492 8009456: 687b ldr r3, [r7, #4] 8009458: 681b ldr r3, [r3, #0] 800945a: 4a5e ldr r2, [pc, #376] @ (80095d4 ) 800945c: 4293 cmp r3, r2 800945e: d018 beq.n 8009492 8009460: 687b ldr r3, [r7, #4] 8009462: 681b ldr r3, [r3, #0] 8009464: 4a5c ldr r2, [pc, #368] @ (80095d8 ) 8009466: 4293 cmp r3, r2 8009468: d013 beq.n 8009492 800946a: 687b ldr r3, [r7, #4] 800946c: 681b ldr r3, [r3, #0] 800946e: 4a5b ldr r2, [pc, #364] @ (80095dc ) 8009470: 4293 cmp r3, r2 8009472: d00e beq.n 8009492 8009474: 687b ldr r3, [r7, #4] 8009476: 681b ldr r3, [r3, #0] 8009478: 4a59 ldr r2, [pc, #356] @ (80095e0 ) 800947a: 4293 cmp r3, r2 800947c: d009 beq.n 8009492 800947e: 687b ldr r3, [r7, #4] 8009480: 681b ldr r3, [r3, #0] 8009482: 4a58 ldr r2, [pc, #352] @ (80095e4 ) 8009484: 4293 cmp r3, r2 8009486: d004 beq.n 8009492 8009488: 687b ldr r3, [r7, #4] 800948a: 681b ldr r3, [r3, #0] 800948c: 4a56 ldr r2, [pc, #344] @ (80095e8 ) 800948e: 4293 cmp r3, r2 8009490: d108 bne.n 80094a4 8009492: 687b ldr r3, [r7, #4] 8009494: 681b ldr r3, [r3, #0] 8009496: 681a ldr r2, [r3, #0] 8009498: 687b ldr r3, [r7, #4] 800949a: 681b ldr r3, [r3, #0] 800949c: f022 0201 bic.w r2, r2, #1 80094a0: 601a str r2, [r3, #0] 80094a2: e007 b.n 80094b4 80094a4: 687b ldr r3, [r7, #4] 80094a6: 681b ldr r3, [r3, #0] 80094a8: 681a ldr r2, [r3, #0] 80094aa: 687b ldr r3, [r7, #4] 80094ac: 681b ldr r3, [r3, #0] 80094ae: f022 0201 bic.w r2, r2, #1 80094b2: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while(((*enableRegister) & DMA_SxCR_EN) != 0U) 80094b4: e013 b.n 80094de { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 80094b6: f7fc fcf5 bl 8005ea4 80094ba: 4602 mov r2, r0 80094bc: 693b ldr r3, [r7, #16] 80094be: 1ad3 subs r3, r2, r3 80094c0: 2b05 cmp r3, #5 80094c2: d90c bls.n 80094de { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 80094c4: 687b ldr r3, [r7, #4] 80094c6: 2220 movs r2, #32 80094c8: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 80094ca: 687b ldr r3, [r7, #4] 80094cc: 2203 movs r2, #3 80094ce: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80094d2: 687b ldr r3, [r7, #4] 80094d4: 2200 movs r2, #0 80094d6: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 80094da: 2301 movs r3, #1 80094dc: e12d b.n 800973a while(((*enableRegister) & DMA_SxCR_EN) != 0U) 80094de: 697b ldr r3, [r7, #20] 80094e0: 681b ldr r3, [r3, #0] 80094e2: f003 0301 and.w r3, r3, #1 80094e6: 2b00 cmp r3, #0 80094e8: d1e5 bne.n 80094b6 } } /* Clear all interrupt flags at correct offset within the register */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80094ea: 687b ldr r3, [r7, #4] 80094ec: 681b ldr r3, [r3, #0] 80094ee: 4a2f ldr r2, [pc, #188] @ (80095ac ) 80094f0: 4293 cmp r3, r2 80094f2: d04a beq.n 800958a 80094f4: 687b ldr r3, [r7, #4] 80094f6: 681b ldr r3, [r3, #0] 80094f8: 4a2d ldr r2, [pc, #180] @ (80095b0 ) 80094fa: 4293 cmp r3, r2 80094fc: d045 beq.n 800958a 80094fe: 687b ldr r3, [r7, #4] 8009500: 681b ldr r3, [r3, #0] 8009502: 4a2c ldr r2, [pc, #176] @ (80095b4 ) 8009504: 4293 cmp r3, r2 8009506: d040 beq.n 800958a 8009508: 687b ldr r3, [r7, #4] 800950a: 681b ldr r3, [r3, #0] 800950c: 4a2a ldr r2, [pc, #168] @ (80095b8 ) 800950e: 4293 cmp r3, r2 8009510: d03b beq.n 800958a 8009512: 687b ldr r3, [r7, #4] 8009514: 681b ldr r3, [r3, #0] 8009516: 4a29 ldr r2, [pc, #164] @ (80095bc ) 8009518: 4293 cmp r3, r2 800951a: d036 beq.n 800958a 800951c: 687b ldr r3, [r7, #4] 800951e: 681b ldr r3, [r3, #0] 8009520: 4a27 ldr r2, [pc, #156] @ (80095c0 ) 8009522: 4293 cmp r3, r2 8009524: d031 beq.n 800958a 8009526: 687b ldr r3, [r7, #4] 8009528: 681b ldr r3, [r3, #0] 800952a: 4a26 ldr r2, [pc, #152] @ (80095c4 ) 800952c: 4293 cmp r3, r2 800952e: d02c beq.n 800958a 8009530: 687b ldr r3, [r7, #4] 8009532: 681b ldr r3, [r3, #0] 8009534: 4a24 ldr r2, [pc, #144] @ (80095c8 ) 8009536: 4293 cmp r3, r2 8009538: d027 beq.n 800958a 800953a: 687b ldr r3, [r7, #4] 800953c: 681b ldr r3, [r3, #0] 800953e: 4a23 ldr r2, [pc, #140] @ (80095cc ) 8009540: 4293 cmp r3, r2 8009542: d022 beq.n 800958a 8009544: 687b ldr r3, [r7, #4] 8009546: 681b ldr r3, [r3, #0] 8009548: 4a21 ldr r2, [pc, #132] @ (80095d0 ) 800954a: 4293 cmp r3, r2 800954c: d01d beq.n 800958a 800954e: 687b ldr r3, [r7, #4] 8009550: 681b ldr r3, [r3, #0] 8009552: 4a20 ldr r2, [pc, #128] @ (80095d4 ) 8009554: 4293 cmp r3, r2 8009556: d018 beq.n 800958a 8009558: 687b ldr r3, [r7, #4] 800955a: 681b ldr r3, [r3, #0] 800955c: 4a1e ldr r2, [pc, #120] @ (80095d8 ) 800955e: 4293 cmp r3, r2 8009560: d013 beq.n 800958a 8009562: 687b ldr r3, [r7, #4] 8009564: 681b ldr r3, [r3, #0] 8009566: 4a1d ldr r2, [pc, #116] @ (80095dc ) 8009568: 4293 cmp r3, r2 800956a: d00e beq.n 800958a 800956c: 687b ldr r3, [r7, #4] 800956e: 681b ldr r3, [r3, #0] 8009570: 4a1b ldr r2, [pc, #108] @ (80095e0 ) 8009572: 4293 cmp r3, r2 8009574: d009 beq.n 800958a 8009576: 687b ldr r3, [r7, #4] 8009578: 681b ldr r3, [r3, #0] 800957a: 4a1a ldr r2, [pc, #104] @ (80095e4 ) 800957c: 4293 cmp r3, r2 800957e: d004 beq.n 800958a 8009580: 687b ldr r3, [r7, #4] 8009582: 681b ldr r3, [r3, #0] 8009584: 4a18 ldr r2, [pc, #96] @ (80095e8 ) 8009586: 4293 cmp r3, r2 8009588: d101 bne.n 800958e 800958a: 2301 movs r3, #1 800958c: e000 b.n 8009590 800958e: 2300 movs r3, #0 8009590: 2b00 cmp r3, #0 8009592: d02b beq.n 80095ec { regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8009594: 687b ldr r3, [r7, #4] 8009596: 6d9b ldr r3, [r3, #88] @ 0x58 8009598: 60bb str r3, [r7, #8] regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800959a: 687b ldr r3, [r7, #4] 800959c: 6ddb ldr r3, [r3, #92] @ 0x5c 800959e: f003 031f and.w r3, r3, #31 80095a2: 223f movs r2, #63 @ 0x3f 80095a4: 409a lsls r2, r3 80095a6: 68bb ldr r3, [r7, #8] 80095a8: 609a str r2, [r3, #8] 80095aa: e02a b.n 8009602 80095ac: 40020010 .word 0x40020010 80095b0: 40020028 .word 0x40020028 80095b4: 40020040 .word 0x40020040 80095b8: 40020058 .word 0x40020058 80095bc: 40020070 .word 0x40020070 80095c0: 40020088 .word 0x40020088 80095c4: 400200a0 .word 0x400200a0 80095c8: 400200b8 .word 0x400200b8 80095cc: 40020410 .word 0x40020410 80095d0: 40020428 .word 0x40020428 80095d4: 40020440 .word 0x40020440 80095d8: 40020458 .word 0x40020458 80095dc: 40020470 .word 0x40020470 80095e0: 40020488 .word 0x40020488 80095e4: 400204a0 .word 0x400204a0 80095e8: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 80095ec: 687b ldr r3, [r7, #4] 80095ee: 6d9b ldr r3, [r3, #88] @ 0x58 80095f0: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 80095f2: 687b ldr r3, [r7, #4] 80095f4: 6ddb ldr r3, [r3, #92] @ 0x5c 80095f6: f003 031f and.w r3, r3, #31 80095fa: 2201 movs r2, #1 80095fc: 409a lsls r2, r3 80095fe: 68fb ldr r3, [r7, #12] 8009600: 605a str r2, [r3, #4] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8009602: 687b ldr r3, [r7, #4] 8009604: 681b ldr r3, [r3, #0] 8009606: 4a4f ldr r2, [pc, #316] @ (8009744 ) 8009608: 4293 cmp r3, r2 800960a: d072 beq.n 80096f2 800960c: 687b ldr r3, [r7, #4] 800960e: 681b ldr r3, [r3, #0] 8009610: 4a4d ldr r2, [pc, #308] @ (8009748 ) 8009612: 4293 cmp r3, r2 8009614: d06d beq.n 80096f2 8009616: 687b ldr r3, [r7, #4] 8009618: 681b ldr r3, [r3, #0] 800961a: 4a4c ldr r2, [pc, #304] @ (800974c ) 800961c: 4293 cmp r3, r2 800961e: d068 beq.n 80096f2 8009620: 687b ldr r3, [r7, #4] 8009622: 681b ldr r3, [r3, #0] 8009624: 4a4a ldr r2, [pc, #296] @ (8009750 ) 8009626: 4293 cmp r3, r2 8009628: d063 beq.n 80096f2 800962a: 687b ldr r3, [r7, #4] 800962c: 681b ldr r3, [r3, #0] 800962e: 4a49 ldr r2, [pc, #292] @ (8009754 ) 8009630: 4293 cmp r3, r2 8009632: d05e beq.n 80096f2 8009634: 687b ldr r3, [r7, #4] 8009636: 681b ldr r3, [r3, #0] 8009638: 4a47 ldr r2, [pc, #284] @ (8009758 ) 800963a: 4293 cmp r3, r2 800963c: d059 beq.n 80096f2 800963e: 687b ldr r3, [r7, #4] 8009640: 681b ldr r3, [r3, #0] 8009642: 4a46 ldr r2, [pc, #280] @ (800975c ) 8009644: 4293 cmp r3, r2 8009646: d054 beq.n 80096f2 8009648: 687b ldr r3, [r7, #4] 800964a: 681b ldr r3, [r3, #0] 800964c: 4a44 ldr r2, [pc, #272] @ (8009760 ) 800964e: 4293 cmp r3, r2 8009650: d04f beq.n 80096f2 8009652: 687b ldr r3, [r7, #4] 8009654: 681b ldr r3, [r3, #0] 8009656: 4a43 ldr r2, [pc, #268] @ (8009764 ) 8009658: 4293 cmp r3, r2 800965a: d04a beq.n 80096f2 800965c: 687b ldr r3, [r7, #4] 800965e: 681b ldr r3, [r3, #0] 8009660: 4a41 ldr r2, [pc, #260] @ (8009768 ) 8009662: 4293 cmp r3, r2 8009664: d045 beq.n 80096f2 8009666: 687b ldr r3, [r7, #4] 8009668: 681b ldr r3, [r3, #0] 800966a: 4a40 ldr r2, [pc, #256] @ (800976c ) 800966c: 4293 cmp r3, r2 800966e: d040 beq.n 80096f2 8009670: 687b ldr r3, [r7, #4] 8009672: 681b ldr r3, [r3, #0] 8009674: 4a3e ldr r2, [pc, #248] @ (8009770 ) 8009676: 4293 cmp r3, r2 8009678: d03b beq.n 80096f2 800967a: 687b ldr r3, [r7, #4] 800967c: 681b ldr r3, [r3, #0] 800967e: 4a3d ldr r2, [pc, #244] @ (8009774 ) 8009680: 4293 cmp r3, r2 8009682: d036 beq.n 80096f2 8009684: 687b ldr r3, [r7, #4] 8009686: 681b ldr r3, [r3, #0] 8009688: 4a3b ldr r2, [pc, #236] @ (8009778 ) 800968a: 4293 cmp r3, r2 800968c: d031 beq.n 80096f2 800968e: 687b ldr r3, [r7, #4] 8009690: 681b ldr r3, [r3, #0] 8009692: 4a3a ldr r2, [pc, #232] @ (800977c ) 8009694: 4293 cmp r3, r2 8009696: d02c beq.n 80096f2 8009698: 687b ldr r3, [r7, #4] 800969a: 681b ldr r3, [r3, #0] 800969c: 4a38 ldr r2, [pc, #224] @ (8009780 ) 800969e: 4293 cmp r3, r2 80096a0: d027 beq.n 80096f2 80096a2: 687b ldr r3, [r7, #4] 80096a4: 681b ldr r3, [r3, #0] 80096a6: 4a37 ldr r2, [pc, #220] @ (8009784 ) 80096a8: 4293 cmp r3, r2 80096aa: d022 beq.n 80096f2 80096ac: 687b ldr r3, [r7, #4] 80096ae: 681b ldr r3, [r3, #0] 80096b0: 4a35 ldr r2, [pc, #212] @ (8009788 ) 80096b2: 4293 cmp r3, r2 80096b4: d01d beq.n 80096f2 80096b6: 687b ldr r3, [r7, #4] 80096b8: 681b ldr r3, [r3, #0] 80096ba: 4a34 ldr r2, [pc, #208] @ (800978c ) 80096bc: 4293 cmp r3, r2 80096be: d018 beq.n 80096f2 80096c0: 687b ldr r3, [r7, #4] 80096c2: 681b ldr r3, [r3, #0] 80096c4: 4a32 ldr r2, [pc, #200] @ (8009790 ) 80096c6: 4293 cmp r3, r2 80096c8: d013 beq.n 80096f2 80096ca: 687b ldr r3, [r7, #4] 80096cc: 681b ldr r3, [r3, #0] 80096ce: 4a31 ldr r2, [pc, #196] @ (8009794 ) 80096d0: 4293 cmp r3, r2 80096d2: d00e beq.n 80096f2 80096d4: 687b ldr r3, [r7, #4] 80096d6: 681b ldr r3, [r3, #0] 80096d8: 4a2f ldr r2, [pc, #188] @ (8009798 ) 80096da: 4293 cmp r3, r2 80096dc: d009 beq.n 80096f2 80096de: 687b ldr r3, [r7, #4] 80096e0: 681b ldr r3, [r3, #0] 80096e2: 4a2e ldr r2, [pc, #184] @ (800979c ) 80096e4: 4293 cmp r3, r2 80096e6: d004 beq.n 80096f2 80096e8: 687b ldr r3, [r7, #4] 80096ea: 681b ldr r3, [r3, #0] 80096ec: 4a2c ldr r2, [pc, #176] @ (80097a0 ) 80096ee: 4293 cmp r3, r2 80096f0: d101 bne.n 80096f6 80096f2: 2301 movs r3, #1 80096f4: e000 b.n 80096f8 80096f6: 2300 movs r3, #0 80096f8: 2b00 cmp r3, #0 80096fa: d015 beq.n 8009728 { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 80096fc: 687b ldr r3, [r7, #4] 80096fe: 6e5b ldr r3, [r3, #100] @ 0x64 8009700: 687a ldr r2, [r7, #4] 8009702: 6e92 ldr r2, [r2, #104] @ 0x68 8009704: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 8009706: 687b ldr r3, [r7, #4] 8009708: 6edb ldr r3, [r3, #108] @ 0x6c 800970a: 2b00 cmp r3, #0 800970c: d00c beq.n 8009728 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 800970e: 687b ldr r3, [r7, #4] 8009710: 6edb ldr r3, [r3, #108] @ 0x6c 8009712: 681a ldr r2, [r3, #0] 8009714: 687b ldr r3, [r7, #4] 8009716: 6edb ldr r3, [r3, #108] @ 0x6c 8009718: f422 7280 bic.w r2, r2, #256 @ 0x100 800971c: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 800971e: 687b ldr r3, [r7, #4] 8009720: 6f1b ldr r3, [r3, #112] @ 0x70 8009722: 687a ldr r2, [r7, #4] 8009724: 6f52 ldr r2, [r2, #116] @ 0x74 8009726: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8009728: 687b ldr r3, [r7, #4] 800972a: 2201 movs r2, #1 800972c: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009730: 687b ldr r3, [r7, #4] 8009732: 2200 movs r2, #0 8009734: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 8009738: 2300 movs r3, #0 } 800973a: 4618 mov r0, r3 800973c: 3718 adds r7, #24 800973e: 46bd mov sp, r7 8009740: bd80 pop {r7, pc} 8009742: bf00 nop 8009744: 40020010 .word 0x40020010 8009748: 40020028 .word 0x40020028 800974c: 40020040 .word 0x40020040 8009750: 40020058 .word 0x40020058 8009754: 40020070 .word 0x40020070 8009758: 40020088 .word 0x40020088 800975c: 400200a0 .word 0x400200a0 8009760: 400200b8 .word 0x400200b8 8009764: 40020410 .word 0x40020410 8009768: 40020428 .word 0x40020428 800976c: 40020440 .word 0x40020440 8009770: 40020458 .word 0x40020458 8009774: 40020470 .word 0x40020470 8009778: 40020488 .word 0x40020488 800977c: 400204a0 .word 0x400204a0 8009780: 400204b8 .word 0x400204b8 8009784: 58025408 .word 0x58025408 8009788: 5802541c .word 0x5802541c 800978c: 58025430 .word 0x58025430 8009790: 58025444 .word 0x58025444 8009794: 58025458 .word 0x58025458 8009798: 5802546c .word 0x5802546c 800979c: 58025480 .word 0x58025480 80097a0: 58025494 .word 0x58025494 080097a4 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 80097a4: b580 push {r7, lr} 80097a6: b084 sub sp, #16 80097a8: af00 add r7, sp, #0 80097aa: 6078 str r0, [r7, #4] BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 80097ac: 687b ldr r3, [r7, #4] 80097ae: 2b00 cmp r3, #0 80097b0: d101 bne.n 80097b6 { return HAL_ERROR; 80097b2: 2301 movs r3, #1 80097b4: e237 b.n 8009c26 } if(hdma->State != HAL_DMA_STATE_BUSY) 80097b6: 687b ldr r3, [r7, #4] 80097b8: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 80097bc: b2db uxtb r3, r3 80097be: 2b02 cmp r3, #2 80097c0: d004 beq.n 80097cc { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80097c2: 687b ldr r3, [r7, #4] 80097c4: 2280 movs r2, #128 @ 0x80 80097c6: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 80097c8: 2301 movs r3, #1 80097ca: e22c b.n 8009c26 } else { if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80097cc: 687b ldr r3, [r7, #4] 80097ce: 681b ldr r3, [r3, #0] 80097d0: 4a5c ldr r2, [pc, #368] @ (8009944 ) 80097d2: 4293 cmp r3, r2 80097d4: d04a beq.n 800986c 80097d6: 687b ldr r3, [r7, #4] 80097d8: 681b ldr r3, [r3, #0] 80097da: 4a5b ldr r2, [pc, #364] @ (8009948 ) 80097dc: 4293 cmp r3, r2 80097de: d045 beq.n 800986c 80097e0: 687b ldr r3, [r7, #4] 80097e2: 681b ldr r3, [r3, #0] 80097e4: 4a59 ldr r2, [pc, #356] @ (800994c ) 80097e6: 4293 cmp r3, r2 80097e8: d040 beq.n 800986c 80097ea: 687b ldr r3, [r7, #4] 80097ec: 681b ldr r3, [r3, #0] 80097ee: 4a58 ldr r2, [pc, #352] @ (8009950 ) 80097f0: 4293 cmp r3, r2 80097f2: d03b beq.n 800986c 80097f4: 687b ldr r3, [r7, #4] 80097f6: 681b ldr r3, [r3, #0] 80097f8: 4a56 ldr r2, [pc, #344] @ (8009954 ) 80097fa: 4293 cmp r3, r2 80097fc: d036 beq.n 800986c 80097fe: 687b ldr r3, [r7, #4] 8009800: 681b ldr r3, [r3, #0] 8009802: 4a55 ldr r2, [pc, #340] @ (8009958 ) 8009804: 4293 cmp r3, r2 8009806: d031 beq.n 800986c 8009808: 687b ldr r3, [r7, #4] 800980a: 681b ldr r3, [r3, #0] 800980c: 4a53 ldr r2, [pc, #332] @ (800995c ) 800980e: 4293 cmp r3, r2 8009810: d02c beq.n 800986c 8009812: 687b ldr r3, [r7, #4] 8009814: 681b ldr r3, [r3, #0] 8009816: 4a52 ldr r2, [pc, #328] @ (8009960 ) 8009818: 4293 cmp r3, r2 800981a: d027 beq.n 800986c 800981c: 687b ldr r3, [r7, #4] 800981e: 681b ldr r3, [r3, #0] 8009820: 4a50 ldr r2, [pc, #320] @ (8009964 ) 8009822: 4293 cmp r3, r2 8009824: d022 beq.n 800986c 8009826: 687b ldr r3, [r7, #4] 8009828: 681b ldr r3, [r3, #0] 800982a: 4a4f ldr r2, [pc, #316] @ (8009968 ) 800982c: 4293 cmp r3, r2 800982e: d01d beq.n 800986c 8009830: 687b ldr r3, [r7, #4] 8009832: 681b ldr r3, [r3, #0] 8009834: 4a4d ldr r2, [pc, #308] @ (800996c ) 8009836: 4293 cmp r3, r2 8009838: d018 beq.n 800986c 800983a: 687b ldr r3, [r7, #4] 800983c: 681b ldr r3, [r3, #0] 800983e: 4a4c ldr r2, [pc, #304] @ (8009970 ) 8009840: 4293 cmp r3, r2 8009842: d013 beq.n 800986c 8009844: 687b ldr r3, [r7, #4] 8009846: 681b ldr r3, [r3, #0] 8009848: 4a4a ldr r2, [pc, #296] @ (8009974 ) 800984a: 4293 cmp r3, r2 800984c: d00e beq.n 800986c 800984e: 687b ldr r3, [r7, #4] 8009850: 681b ldr r3, [r3, #0] 8009852: 4a49 ldr r2, [pc, #292] @ (8009978 ) 8009854: 4293 cmp r3, r2 8009856: d009 beq.n 800986c 8009858: 687b ldr r3, [r7, #4] 800985a: 681b ldr r3, [r3, #0] 800985c: 4a47 ldr r2, [pc, #284] @ (800997c ) 800985e: 4293 cmp r3, r2 8009860: d004 beq.n 800986c 8009862: 687b ldr r3, [r7, #4] 8009864: 681b ldr r3, [r3, #0] 8009866: 4a46 ldr r2, [pc, #280] @ (8009980 ) 8009868: 4293 cmp r3, r2 800986a: d101 bne.n 8009870 800986c: 2301 movs r3, #1 800986e: e000 b.n 8009872 8009870: 2300 movs r3, #0 8009872: 2b00 cmp r3, #0 8009874: f000 8086 beq.w 8009984 { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 8009878: 687b ldr r3, [r7, #4] 800987a: 2204 movs r2, #4 800987c: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8009880: 687b ldr r3, [r7, #4] 8009882: 681b ldr r3, [r3, #0] 8009884: 4a2f ldr r2, [pc, #188] @ (8009944 ) 8009886: 4293 cmp r3, r2 8009888: d04a beq.n 8009920 800988a: 687b ldr r3, [r7, #4] 800988c: 681b ldr r3, [r3, #0] 800988e: 4a2e ldr r2, [pc, #184] @ (8009948 ) 8009890: 4293 cmp r3, r2 8009892: d045 beq.n 8009920 8009894: 687b ldr r3, [r7, #4] 8009896: 681b ldr r3, [r3, #0] 8009898: 4a2c ldr r2, [pc, #176] @ (800994c ) 800989a: 4293 cmp r3, r2 800989c: d040 beq.n 8009920 800989e: 687b ldr r3, [r7, #4] 80098a0: 681b ldr r3, [r3, #0] 80098a2: 4a2b ldr r2, [pc, #172] @ (8009950 ) 80098a4: 4293 cmp r3, r2 80098a6: d03b beq.n 8009920 80098a8: 687b ldr r3, [r7, #4] 80098aa: 681b ldr r3, [r3, #0] 80098ac: 4a29 ldr r2, [pc, #164] @ (8009954 ) 80098ae: 4293 cmp r3, r2 80098b0: d036 beq.n 8009920 80098b2: 687b ldr r3, [r7, #4] 80098b4: 681b ldr r3, [r3, #0] 80098b6: 4a28 ldr r2, [pc, #160] @ (8009958 ) 80098b8: 4293 cmp r3, r2 80098ba: d031 beq.n 8009920 80098bc: 687b ldr r3, [r7, #4] 80098be: 681b ldr r3, [r3, #0] 80098c0: 4a26 ldr r2, [pc, #152] @ (800995c ) 80098c2: 4293 cmp r3, r2 80098c4: d02c beq.n 8009920 80098c6: 687b ldr r3, [r7, #4] 80098c8: 681b ldr r3, [r3, #0] 80098ca: 4a25 ldr r2, [pc, #148] @ (8009960 ) 80098cc: 4293 cmp r3, r2 80098ce: d027 beq.n 8009920 80098d0: 687b ldr r3, [r7, #4] 80098d2: 681b ldr r3, [r3, #0] 80098d4: 4a23 ldr r2, [pc, #140] @ (8009964 ) 80098d6: 4293 cmp r3, r2 80098d8: d022 beq.n 8009920 80098da: 687b ldr r3, [r7, #4] 80098dc: 681b ldr r3, [r3, #0] 80098de: 4a22 ldr r2, [pc, #136] @ (8009968 ) 80098e0: 4293 cmp r3, r2 80098e2: d01d beq.n 8009920 80098e4: 687b ldr r3, [r7, #4] 80098e6: 681b ldr r3, [r3, #0] 80098e8: 4a20 ldr r2, [pc, #128] @ (800996c ) 80098ea: 4293 cmp r3, r2 80098ec: d018 beq.n 8009920 80098ee: 687b ldr r3, [r7, #4] 80098f0: 681b ldr r3, [r3, #0] 80098f2: 4a1f ldr r2, [pc, #124] @ (8009970 ) 80098f4: 4293 cmp r3, r2 80098f6: d013 beq.n 8009920 80098f8: 687b ldr r3, [r7, #4] 80098fa: 681b ldr r3, [r3, #0] 80098fc: 4a1d ldr r2, [pc, #116] @ (8009974 ) 80098fe: 4293 cmp r3, r2 8009900: d00e beq.n 8009920 8009902: 687b ldr r3, [r7, #4] 8009904: 681b ldr r3, [r3, #0] 8009906: 4a1c ldr r2, [pc, #112] @ (8009978 ) 8009908: 4293 cmp r3, r2 800990a: d009 beq.n 8009920 800990c: 687b ldr r3, [r7, #4] 800990e: 681b ldr r3, [r3, #0] 8009910: 4a1a ldr r2, [pc, #104] @ (800997c ) 8009912: 4293 cmp r3, r2 8009914: d004 beq.n 8009920 8009916: 687b ldr r3, [r7, #4] 8009918: 681b ldr r3, [r3, #0] 800991a: 4a19 ldr r2, [pc, #100] @ (8009980 ) 800991c: 4293 cmp r3, r2 800991e: d108 bne.n 8009932 8009920: 687b ldr r3, [r7, #4] 8009922: 681b ldr r3, [r3, #0] 8009924: 681a ldr r2, [r3, #0] 8009926: 687b ldr r3, [r7, #4] 8009928: 681b ldr r3, [r3, #0] 800992a: f022 0201 bic.w r2, r2, #1 800992e: 601a str r2, [r3, #0] 8009930: e178 b.n 8009c24 8009932: 687b ldr r3, [r7, #4] 8009934: 681b ldr r3, [r3, #0] 8009936: 681a ldr r2, [r3, #0] 8009938: 687b ldr r3, [r7, #4] 800993a: 681b ldr r3, [r3, #0] 800993c: f022 0201 bic.w r2, r2, #1 8009940: 601a str r2, [r3, #0] 8009942: e16f b.n 8009c24 8009944: 40020010 .word 0x40020010 8009948: 40020028 .word 0x40020028 800994c: 40020040 .word 0x40020040 8009950: 40020058 .word 0x40020058 8009954: 40020070 .word 0x40020070 8009958: 40020088 .word 0x40020088 800995c: 400200a0 .word 0x400200a0 8009960: 400200b8 .word 0x400200b8 8009964: 40020410 .word 0x40020410 8009968: 40020428 .word 0x40020428 800996c: 40020440 .word 0x40020440 8009970: 40020458 .word 0x40020458 8009974: 40020470 .word 0x40020470 8009978: 40020488 .word 0x40020488 800997c: 400204a0 .word 0x400204a0 8009980: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 8009984: 687b ldr r3, [r7, #4] 8009986: 681b ldr r3, [r3, #0] 8009988: 681a ldr r2, [r3, #0] 800998a: 687b ldr r3, [r7, #4] 800998c: 681b ldr r3, [r3, #0] 800998e: f022 020e bic.w r2, r2, #14 8009992: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8009994: 687b ldr r3, [r7, #4] 8009996: 681b ldr r3, [r3, #0] 8009998: 4a6c ldr r2, [pc, #432] @ (8009b4c ) 800999a: 4293 cmp r3, r2 800999c: d04a beq.n 8009a34 800999e: 687b ldr r3, [r7, #4] 80099a0: 681b ldr r3, [r3, #0] 80099a2: 4a6b ldr r2, [pc, #428] @ (8009b50 ) 80099a4: 4293 cmp r3, r2 80099a6: d045 beq.n 8009a34 80099a8: 687b ldr r3, [r7, #4] 80099aa: 681b ldr r3, [r3, #0] 80099ac: 4a69 ldr r2, [pc, #420] @ (8009b54 ) 80099ae: 4293 cmp r3, r2 80099b0: d040 beq.n 8009a34 80099b2: 687b ldr r3, [r7, #4] 80099b4: 681b ldr r3, [r3, #0] 80099b6: 4a68 ldr r2, [pc, #416] @ (8009b58 ) 80099b8: 4293 cmp r3, r2 80099ba: d03b beq.n 8009a34 80099bc: 687b ldr r3, [r7, #4] 80099be: 681b ldr r3, [r3, #0] 80099c0: 4a66 ldr r2, [pc, #408] @ (8009b5c ) 80099c2: 4293 cmp r3, r2 80099c4: d036 beq.n 8009a34 80099c6: 687b ldr r3, [r7, #4] 80099c8: 681b ldr r3, [r3, #0] 80099ca: 4a65 ldr r2, [pc, #404] @ (8009b60 ) 80099cc: 4293 cmp r3, r2 80099ce: d031 beq.n 8009a34 80099d0: 687b ldr r3, [r7, #4] 80099d2: 681b ldr r3, [r3, #0] 80099d4: 4a63 ldr r2, [pc, #396] @ (8009b64 ) 80099d6: 4293 cmp r3, r2 80099d8: d02c beq.n 8009a34 80099da: 687b ldr r3, [r7, #4] 80099dc: 681b ldr r3, [r3, #0] 80099de: 4a62 ldr r2, [pc, #392] @ (8009b68 ) 80099e0: 4293 cmp r3, r2 80099e2: d027 beq.n 8009a34 80099e4: 687b ldr r3, [r7, #4] 80099e6: 681b ldr r3, [r3, #0] 80099e8: 4a60 ldr r2, [pc, #384] @ (8009b6c ) 80099ea: 4293 cmp r3, r2 80099ec: d022 beq.n 8009a34 80099ee: 687b ldr r3, [r7, #4] 80099f0: 681b ldr r3, [r3, #0] 80099f2: 4a5f ldr r2, [pc, #380] @ (8009b70 ) 80099f4: 4293 cmp r3, r2 80099f6: d01d beq.n 8009a34 80099f8: 687b ldr r3, [r7, #4] 80099fa: 681b ldr r3, [r3, #0] 80099fc: 4a5d ldr r2, [pc, #372] @ (8009b74 ) 80099fe: 4293 cmp r3, r2 8009a00: d018 beq.n 8009a34 8009a02: 687b ldr r3, [r7, #4] 8009a04: 681b ldr r3, [r3, #0] 8009a06: 4a5c ldr r2, [pc, #368] @ (8009b78 ) 8009a08: 4293 cmp r3, r2 8009a0a: d013 beq.n 8009a34 8009a0c: 687b ldr r3, [r7, #4] 8009a0e: 681b ldr r3, [r3, #0] 8009a10: 4a5a ldr r2, [pc, #360] @ (8009b7c ) 8009a12: 4293 cmp r3, r2 8009a14: d00e beq.n 8009a34 8009a16: 687b ldr r3, [r7, #4] 8009a18: 681b ldr r3, [r3, #0] 8009a1a: 4a59 ldr r2, [pc, #356] @ (8009b80 ) 8009a1c: 4293 cmp r3, r2 8009a1e: d009 beq.n 8009a34 8009a20: 687b ldr r3, [r7, #4] 8009a22: 681b ldr r3, [r3, #0] 8009a24: 4a57 ldr r2, [pc, #348] @ (8009b84 ) 8009a26: 4293 cmp r3, r2 8009a28: d004 beq.n 8009a34 8009a2a: 687b ldr r3, [r7, #4] 8009a2c: 681b ldr r3, [r3, #0] 8009a2e: 4a56 ldr r2, [pc, #344] @ (8009b88 ) 8009a30: 4293 cmp r3, r2 8009a32: d108 bne.n 8009a46 8009a34: 687b ldr r3, [r7, #4] 8009a36: 681b ldr r3, [r3, #0] 8009a38: 681a ldr r2, [r3, #0] 8009a3a: 687b ldr r3, [r7, #4] 8009a3c: 681b ldr r3, [r3, #0] 8009a3e: f022 0201 bic.w r2, r2, #1 8009a42: 601a str r2, [r3, #0] 8009a44: e007 b.n 8009a56 8009a46: 687b ldr r3, [r7, #4] 8009a48: 681b ldr r3, [r3, #0] 8009a4a: 681a ldr r2, [r3, #0] 8009a4c: 687b ldr r3, [r7, #4] 8009a4e: 681b ldr r3, [r3, #0] 8009a50: f022 0201 bic.w r2, r2, #1 8009a54: 601a str r2, [r3, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8009a56: 687b ldr r3, [r7, #4] 8009a58: 681b ldr r3, [r3, #0] 8009a5a: 4a3c ldr r2, [pc, #240] @ (8009b4c ) 8009a5c: 4293 cmp r3, r2 8009a5e: d072 beq.n 8009b46 8009a60: 687b ldr r3, [r7, #4] 8009a62: 681b ldr r3, [r3, #0] 8009a64: 4a3a ldr r2, [pc, #232] @ (8009b50 ) 8009a66: 4293 cmp r3, r2 8009a68: d06d beq.n 8009b46 8009a6a: 687b ldr r3, [r7, #4] 8009a6c: 681b ldr r3, [r3, #0] 8009a6e: 4a39 ldr r2, [pc, #228] @ (8009b54 ) 8009a70: 4293 cmp r3, r2 8009a72: d068 beq.n 8009b46 8009a74: 687b ldr r3, [r7, #4] 8009a76: 681b ldr r3, [r3, #0] 8009a78: 4a37 ldr r2, [pc, #220] @ (8009b58 ) 8009a7a: 4293 cmp r3, r2 8009a7c: d063 beq.n 8009b46 8009a7e: 687b ldr r3, [r7, #4] 8009a80: 681b ldr r3, [r3, #0] 8009a82: 4a36 ldr r2, [pc, #216] @ (8009b5c ) 8009a84: 4293 cmp r3, r2 8009a86: d05e beq.n 8009b46 8009a88: 687b ldr r3, [r7, #4] 8009a8a: 681b ldr r3, [r3, #0] 8009a8c: 4a34 ldr r2, [pc, #208] @ (8009b60 ) 8009a8e: 4293 cmp r3, r2 8009a90: d059 beq.n 8009b46 8009a92: 687b ldr r3, [r7, #4] 8009a94: 681b ldr r3, [r3, #0] 8009a96: 4a33 ldr r2, [pc, #204] @ (8009b64 ) 8009a98: 4293 cmp r3, r2 8009a9a: d054 beq.n 8009b46 8009a9c: 687b ldr r3, [r7, #4] 8009a9e: 681b ldr r3, [r3, #0] 8009aa0: 4a31 ldr r2, [pc, #196] @ (8009b68 ) 8009aa2: 4293 cmp r3, r2 8009aa4: d04f beq.n 8009b46 8009aa6: 687b ldr r3, [r7, #4] 8009aa8: 681b ldr r3, [r3, #0] 8009aaa: 4a30 ldr r2, [pc, #192] @ (8009b6c ) 8009aac: 4293 cmp r3, r2 8009aae: d04a beq.n 8009b46 8009ab0: 687b ldr r3, [r7, #4] 8009ab2: 681b ldr r3, [r3, #0] 8009ab4: 4a2e ldr r2, [pc, #184] @ (8009b70 ) 8009ab6: 4293 cmp r3, r2 8009ab8: d045 beq.n 8009b46 8009aba: 687b ldr r3, [r7, #4] 8009abc: 681b ldr r3, [r3, #0] 8009abe: 4a2d ldr r2, [pc, #180] @ (8009b74 ) 8009ac0: 4293 cmp r3, r2 8009ac2: d040 beq.n 8009b46 8009ac4: 687b ldr r3, [r7, #4] 8009ac6: 681b ldr r3, [r3, #0] 8009ac8: 4a2b ldr r2, [pc, #172] @ (8009b78 ) 8009aca: 4293 cmp r3, r2 8009acc: d03b beq.n 8009b46 8009ace: 687b ldr r3, [r7, #4] 8009ad0: 681b ldr r3, [r3, #0] 8009ad2: 4a2a ldr r2, [pc, #168] @ (8009b7c ) 8009ad4: 4293 cmp r3, r2 8009ad6: d036 beq.n 8009b46 8009ad8: 687b ldr r3, [r7, #4] 8009ada: 681b ldr r3, [r3, #0] 8009adc: 4a28 ldr r2, [pc, #160] @ (8009b80 ) 8009ade: 4293 cmp r3, r2 8009ae0: d031 beq.n 8009b46 8009ae2: 687b ldr r3, [r7, #4] 8009ae4: 681b ldr r3, [r3, #0] 8009ae6: 4a27 ldr r2, [pc, #156] @ (8009b84 ) 8009ae8: 4293 cmp r3, r2 8009aea: d02c beq.n 8009b46 8009aec: 687b ldr r3, [r7, #4] 8009aee: 681b ldr r3, [r3, #0] 8009af0: 4a25 ldr r2, [pc, #148] @ (8009b88 ) 8009af2: 4293 cmp r3, r2 8009af4: d027 beq.n 8009b46 8009af6: 687b ldr r3, [r7, #4] 8009af8: 681b ldr r3, [r3, #0] 8009afa: 4a24 ldr r2, [pc, #144] @ (8009b8c ) 8009afc: 4293 cmp r3, r2 8009afe: d022 beq.n 8009b46 8009b00: 687b ldr r3, [r7, #4] 8009b02: 681b ldr r3, [r3, #0] 8009b04: 4a22 ldr r2, [pc, #136] @ (8009b90 ) 8009b06: 4293 cmp r3, r2 8009b08: d01d beq.n 8009b46 8009b0a: 687b ldr r3, [r7, #4] 8009b0c: 681b ldr r3, [r3, #0] 8009b0e: 4a21 ldr r2, [pc, #132] @ (8009b94 ) 8009b10: 4293 cmp r3, r2 8009b12: d018 beq.n 8009b46 8009b14: 687b ldr r3, [r7, #4] 8009b16: 681b ldr r3, [r3, #0] 8009b18: 4a1f ldr r2, [pc, #124] @ (8009b98 ) 8009b1a: 4293 cmp r3, r2 8009b1c: d013 beq.n 8009b46 8009b1e: 687b ldr r3, [r7, #4] 8009b20: 681b ldr r3, [r3, #0] 8009b22: 4a1e ldr r2, [pc, #120] @ (8009b9c ) 8009b24: 4293 cmp r3, r2 8009b26: d00e beq.n 8009b46 8009b28: 687b ldr r3, [r7, #4] 8009b2a: 681b ldr r3, [r3, #0] 8009b2c: 4a1c ldr r2, [pc, #112] @ (8009ba0 ) 8009b2e: 4293 cmp r3, r2 8009b30: d009 beq.n 8009b46 8009b32: 687b ldr r3, [r7, #4] 8009b34: 681b ldr r3, [r3, #0] 8009b36: 4a1b ldr r2, [pc, #108] @ (8009ba4 ) 8009b38: 4293 cmp r3, r2 8009b3a: d004 beq.n 8009b46 8009b3c: 687b ldr r3, [r7, #4] 8009b3e: 681b ldr r3, [r3, #0] 8009b40: 4a19 ldr r2, [pc, #100] @ (8009ba8 ) 8009b42: 4293 cmp r3, r2 8009b44: d132 bne.n 8009bac 8009b46: 2301 movs r3, #1 8009b48: e031 b.n 8009bae 8009b4a: bf00 nop 8009b4c: 40020010 .word 0x40020010 8009b50: 40020028 .word 0x40020028 8009b54: 40020040 .word 0x40020040 8009b58: 40020058 .word 0x40020058 8009b5c: 40020070 .word 0x40020070 8009b60: 40020088 .word 0x40020088 8009b64: 400200a0 .word 0x400200a0 8009b68: 400200b8 .word 0x400200b8 8009b6c: 40020410 .word 0x40020410 8009b70: 40020428 .word 0x40020428 8009b74: 40020440 .word 0x40020440 8009b78: 40020458 .word 0x40020458 8009b7c: 40020470 .word 0x40020470 8009b80: 40020488 .word 0x40020488 8009b84: 400204a0 .word 0x400204a0 8009b88: 400204b8 .word 0x400204b8 8009b8c: 58025408 .word 0x58025408 8009b90: 5802541c .word 0x5802541c 8009b94: 58025430 .word 0x58025430 8009b98: 58025444 .word 0x58025444 8009b9c: 58025458 .word 0x58025458 8009ba0: 5802546c .word 0x5802546c 8009ba4: 58025480 .word 0x58025480 8009ba8: 58025494 .word 0x58025494 8009bac: 2300 movs r3, #0 8009bae: 2b00 cmp r3, #0 8009bb0: d028 beq.n 8009c04 { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8009bb2: 687b ldr r3, [r7, #4] 8009bb4: 6e1b ldr r3, [r3, #96] @ 0x60 8009bb6: 681a ldr r2, [r3, #0] 8009bb8: 687b ldr r3, [r7, #4] 8009bba: 6e1b ldr r3, [r3, #96] @ 0x60 8009bbc: f422 7280 bic.w r2, r2, #256 @ 0x100 8009bc0: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8009bc2: 687b ldr r3, [r7, #4] 8009bc4: 6d9b ldr r3, [r3, #88] @ 0x58 8009bc6: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8009bc8: 687b ldr r3, [r7, #4] 8009bca: 6ddb ldr r3, [r3, #92] @ 0x5c 8009bcc: f003 031f and.w r3, r3, #31 8009bd0: 2201 movs r2, #1 8009bd2: 409a lsls r2, r3 8009bd4: 68fb ldr r3, [r7, #12] 8009bd6: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8009bd8: 687b ldr r3, [r7, #4] 8009bda: 6e5b ldr r3, [r3, #100] @ 0x64 8009bdc: 687a ldr r2, [r7, #4] 8009bde: 6e92 ldr r2, [r2, #104] @ 0x68 8009be0: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 8009be2: 687b ldr r3, [r7, #4] 8009be4: 6edb ldr r3, [r3, #108] @ 0x6c 8009be6: 2b00 cmp r3, #0 8009be8: d00c beq.n 8009c04 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8009bea: 687b ldr r3, [r7, #4] 8009bec: 6edb ldr r3, [r3, #108] @ 0x6c 8009bee: 681a ldr r2, [r3, #0] 8009bf0: 687b ldr r3, [r7, #4] 8009bf2: 6edb ldr r3, [r3, #108] @ 0x6c 8009bf4: f422 7280 bic.w r2, r2, #256 @ 0x100 8009bf8: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8009bfa: 687b ldr r3, [r7, #4] 8009bfc: 6f1b ldr r3, [r3, #112] @ 0x70 8009bfe: 687a ldr r2, [r7, #4] 8009c00: 6f52 ldr r2, [r2, #116] @ 0x74 8009c02: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8009c04: 687b ldr r3, [r7, #4] 8009c06: 2201 movs r2, #1 8009c08: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009c0c: 687b ldr r3, [r7, #4] 8009c0e: 2200 movs r2, #0 8009c10: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8009c14: 687b ldr r3, [r7, #4] 8009c16: 6d1b ldr r3, [r3, #80] @ 0x50 8009c18: 2b00 cmp r3, #0 8009c1a: d003 beq.n 8009c24 { hdma->XferAbortCallback(hdma); 8009c1c: 687b ldr r3, [r7, #4] 8009c1e: 6d1b ldr r3, [r3, #80] @ 0x50 8009c20: 6878 ldr r0, [r7, #4] 8009c22: 4798 blx r3 } } } return HAL_OK; 8009c24: 2300 movs r3, #0 } 8009c26: 4618 mov r0, r3 8009c28: 3710 adds r7, #16 8009c2a: 46bd mov sp, r7 8009c2c: bd80 pop {r7, pc} 8009c2e: bf00 nop 08009c30 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8009c30: b580 push {r7, lr} 8009c32: b08a sub sp, #40 @ 0x28 8009c34: af00 add r7, sp, #0 8009c36: 6078 str r0, [r7, #4] uint32_t tmpisr_dma, tmpisr_bdma; uint32_t ccr_reg; __IO uint32_t count = 0U; 8009c38: 2300 movs r3, #0 8009c3a: 60fb str r3, [r7, #12] uint32_t timeout = SystemCoreClock / 9600U; 8009c3c: 4b67 ldr r3, [pc, #412] @ (8009ddc ) 8009c3e: 681b ldr r3, [r3, #0] 8009c40: 4a67 ldr r2, [pc, #412] @ (8009de0 ) 8009c42: fba2 2303 umull r2, r3, r2, r3 8009c46: 0a9b lsrs r3, r3, #10 8009c48: 627b str r3, [r7, #36] @ 0x24 /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8009c4a: 687b ldr r3, [r7, #4] 8009c4c: 6d9b ldr r3, [r3, #88] @ 0x58 8009c4e: 623b str r3, [r7, #32] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8009c50: 687b ldr r3, [r7, #4] 8009c52: 6d9b ldr r3, [r3, #88] @ 0x58 8009c54: 61fb str r3, [r7, #28] tmpisr_dma = regs_dma->ISR; 8009c56: 6a3b ldr r3, [r7, #32] 8009c58: 681b ldr r3, [r3, #0] 8009c5a: 61bb str r3, [r7, #24] tmpisr_bdma = regs_bdma->ISR; 8009c5c: 69fb ldr r3, [r7, #28] 8009c5e: 681b ldr r3, [r3, #0] 8009c60: 617b str r3, [r7, #20] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8009c62: 687b ldr r3, [r7, #4] 8009c64: 681b ldr r3, [r3, #0] 8009c66: 4a5f ldr r2, [pc, #380] @ (8009de4 ) 8009c68: 4293 cmp r3, r2 8009c6a: d04a beq.n 8009d02 8009c6c: 687b ldr r3, [r7, #4] 8009c6e: 681b ldr r3, [r3, #0] 8009c70: 4a5d ldr r2, [pc, #372] @ (8009de8 ) 8009c72: 4293 cmp r3, r2 8009c74: d045 beq.n 8009d02 8009c76: 687b ldr r3, [r7, #4] 8009c78: 681b ldr r3, [r3, #0] 8009c7a: 4a5c ldr r2, [pc, #368] @ (8009dec ) 8009c7c: 4293 cmp r3, r2 8009c7e: d040 beq.n 8009d02 8009c80: 687b ldr r3, [r7, #4] 8009c82: 681b ldr r3, [r3, #0] 8009c84: 4a5a ldr r2, [pc, #360] @ (8009df0 ) 8009c86: 4293 cmp r3, r2 8009c88: d03b beq.n 8009d02 8009c8a: 687b ldr r3, [r7, #4] 8009c8c: 681b ldr r3, [r3, #0] 8009c8e: 4a59 ldr r2, [pc, #356] @ (8009df4 ) 8009c90: 4293 cmp r3, r2 8009c92: d036 beq.n 8009d02 8009c94: 687b ldr r3, [r7, #4] 8009c96: 681b ldr r3, [r3, #0] 8009c98: 4a57 ldr r2, [pc, #348] @ (8009df8 ) 8009c9a: 4293 cmp r3, r2 8009c9c: d031 beq.n 8009d02 8009c9e: 687b ldr r3, [r7, #4] 8009ca0: 681b ldr r3, [r3, #0] 8009ca2: 4a56 ldr r2, [pc, #344] @ (8009dfc ) 8009ca4: 4293 cmp r3, r2 8009ca6: d02c beq.n 8009d02 8009ca8: 687b ldr r3, [r7, #4] 8009caa: 681b ldr r3, [r3, #0] 8009cac: 4a54 ldr r2, [pc, #336] @ (8009e00 ) 8009cae: 4293 cmp r3, r2 8009cb0: d027 beq.n 8009d02 8009cb2: 687b ldr r3, [r7, #4] 8009cb4: 681b ldr r3, [r3, #0] 8009cb6: 4a53 ldr r2, [pc, #332] @ (8009e04 ) 8009cb8: 4293 cmp r3, r2 8009cba: d022 beq.n 8009d02 8009cbc: 687b ldr r3, [r7, #4] 8009cbe: 681b ldr r3, [r3, #0] 8009cc0: 4a51 ldr r2, [pc, #324] @ (8009e08 ) 8009cc2: 4293 cmp r3, r2 8009cc4: d01d beq.n 8009d02 8009cc6: 687b ldr r3, [r7, #4] 8009cc8: 681b ldr r3, [r3, #0] 8009cca: 4a50 ldr r2, [pc, #320] @ (8009e0c ) 8009ccc: 4293 cmp r3, r2 8009cce: d018 beq.n 8009d02 8009cd0: 687b ldr r3, [r7, #4] 8009cd2: 681b ldr r3, [r3, #0] 8009cd4: 4a4e ldr r2, [pc, #312] @ (8009e10 ) 8009cd6: 4293 cmp r3, r2 8009cd8: d013 beq.n 8009d02 8009cda: 687b ldr r3, [r7, #4] 8009cdc: 681b ldr r3, [r3, #0] 8009cde: 4a4d ldr r2, [pc, #308] @ (8009e14 ) 8009ce0: 4293 cmp r3, r2 8009ce2: d00e beq.n 8009d02 8009ce4: 687b ldr r3, [r7, #4] 8009ce6: 681b ldr r3, [r3, #0] 8009ce8: 4a4b ldr r2, [pc, #300] @ (8009e18 ) 8009cea: 4293 cmp r3, r2 8009cec: d009 beq.n 8009d02 8009cee: 687b ldr r3, [r7, #4] 8009cf0: 681b ldr r3, [r3, #0] 8009cf2: 4a4a ldr r2, [pc, #296] @ (8009e1c ) 8009cf4: 4293 cmp r3, r2 8009cf6: d004 beq.n 8009d02 8009cf8: 687b ldr r3, [r7, #4] 8009cfa: 681b ldr r3, [r3, #0] 8009cfc: 4a48 ldr r2, [pc, #288] @ (8009e20 ) 8009cfe: 4293 cmp r3, r2 8009d00: d101 bne.n 8009d06 8009d02: 2301 movs r3, #1 8009d04: e000 b.n 8009d08 8009d06: 2300 movs r3, #0 8009d08: 2b00 cmp r3, #0 8009d0a: f000 842b beq.w 800a564 { /* Transfer Error Interrupt management ***************************************/ if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009d0e: 687b ldr r3, [r7, #4] 8009d10: 6ddb ldr r3, [r3, #92] @ 0x5c 8009d12: f003 031f and.w r3, r3, #31 8009d16: 2208 movs r2, #8 8009d18: 409a lsls r2, r3 8009d1a: 69bb ldr r3, [r7, #24] 8009d1c: 4013 ands r3, r2 8009d1e: 2b00 cmp r3, #0 8009d20: f000 80a2 beq.w 8009e68 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) 8009d24: 687b ldr r3, [r7, #4] 8009d26: 681b ldr r3, [r3, #0] 8009d28: 4a2e ldr r2, [pc, #184] @ (8009de4 ) 8009d2a: 4293 cmp r3, r2 8009d2c: d04a beq.n 8009dc4 8009d2e: 687b ldr r3, [r7, #4] 8009d30: 681b ldr r3, [r3, #0] 8009d32: 4a2d ldr r2, [pc, #180] @ (8009de8 ) 8009d34: 4293 cmp r3, r2 8009d36: d045 beq.n 8009dc4 8009d38: 687b ldr r3, [r7, #4] 8009d3a: 681b ldr r3, [r3, #0] 8009d3c: 4a2b ldr r2, [pc, #172] @ (8009dec ) 8009d3e: 4293 cmp r3, r2 8009d40: d040 beq.n 8009dc4 8009d42: 687b ldr r3, [r7, #4] 8009d44: 681b ldr r3, [r3, #0] 8009d46: 4a2a ldr r2, [pc, #168] @ (8009df0 ) 8009d48: 4293 cmp r3, r2 8009d4a: d03b beq.n 8009dc4 8009d4c: 687b ldr r3, [r7, #4] 8009d4e: 681b ldr r3, [r3, #0] 8009d50: 4a28 ldr r2, [pc, #160] @ (8009df4 ) 8009d52: 4293 cmp r3, r2 8009d54: d036 beq.n 8009dc4 8009d56: 687b ldr r3, [r7, #4] 8009d58: 681b ldr r3, [r3, #0] 8009d5a: 4a27 ldr r2, [pc, #156] @ (8009df8 ) 8009d5c: 4293 cmp r3, r2 8009d5e: d031 beq.n 8009dc4 8009d60: 687b ldr r3, [r7, #4] 8009d62: 681b ldr r3, [r3, #0] 8009d64: 4a25 ldr r2, [pc, #148] @ (8009dfc ) 8009d66: 4293 cmp r3, r2 8009d68: d02c beq.n 8009dc4 8009d6a: 687b ldr r3, [r7, #4] 8009d6c: 681b ldr r3, [r3, #0] 8009d6e: 4a24 ldr r2, [pc, #144] @ (8009e00 ) 8009d70: 4293 cmp r3, r2 8009d72: d027 beq.n 8009dc4 8009d74: 687b ldr r3, [r7, #4] 8009d76: 681b ldr r3, [r3, #0] 8009d78: 4a22 ldr r2, [pc, #136] @ (8009e04 ) 8009d7a: 4293 cmp r3, r2 8009d7c: d022 beq.n 8009dc4 8009d7e: 687b ldr r3, [r7, #4] 8009d80: 681b ldr r3, [r3, #0] 8009d82: 4a21 ldr r2, [pc, #132] @ (8009e08 ) 8009d84: 4293 cmp r3, r2 8009d86: d01d beq.n 8009dc4 8009d88: 687b ldr r3, [r7, #4] 8009d8a: 681b ldr r3, [r3, #0] 8009d8c: 4a1f ldr r2, [pc, #124] @ (8009e0c ) 8009d8e: 4293 cmp r3, r2 8009d90: d018 beq.n 8009dc4 8009d92: 687b ldr r3, [r7, #4] 8009d94: 681b ldr r3, [r3, #0] 8009d96: 4a1e ldr r2, [pc, #120] @ (8009e10 ) 8009d98: 4293 cmp r3, r2 8009d9a: d013 beq.n 8009dc4 8009d9c: 687b ldr r3, [r7, #4] 8009d9e: 681b ldr r3, [r3, #0] 8009da0: 4a1c ldr r2, [pc, #112] @ (8009e14 ) 8009da2: 4293 cmp r3, r2 8009da4: d00e beq.n 8009dc4 8009da6: 687b ldr r3, [r7, #4] 8009da8: 681b ldr r3, [r3, #0] 8009daa: 4a1b ldr r2, [pc, #108] @ (8009e18 ) 8009dac: 4293 cmp r3, r2 8009dae: d009 beq.n 8009dc4 8009db0: 687b ldr r3, [r7, #4] 8009db2: 681b ldr r3, [r3, #0] 8009db4: 4a19 ldr r2, [pc, #100] @ (8009e1c ) 8009db6: 4293 cmp r3, r2 8009db8: d004 beq.n 8009dc4 8009dba: 687b ldr r3, [r7, #4] 8009dbc: 681b ldr r3, [r3, #0] 8009dbe: 4a18 ldr r2, [pc, #96] @ (8009e20 ) 8009dc0: 4293 cmp r3, r2 8009dc2: d12f bne.n 8009e24 8009dc4: 687b ldr r3, [r7, #4] 8009dc6: 681b ldr r3, [r3, #0] 8009dc8: 681b ldr r3, [r3, #0] 8009dca: f003 0304 and.w r3, r3, #4 8009dce: 2b00 cmp r3, #0 8009dd0: bf14 ite ne 8009dd2: 2301 movne r3, #1 8009dd4: 2300 moveq r3, #0 8009dd6: b2db uxtb r3, r3 8009dd8: e02e b.n 8009e38 8009dda: bf00 nop 8009ddc: 24000034 .word 0x24000034 8009de0: 1b4e81b5 .word 0x1b4e81b5 8009de4: 40020010 .word 0x40020010 8009de8: 40020028 .word 0x40020028 8009dec: 40020040 .word 0x40020040 8009df0: 40020058 .word 0x40020058 8009df4: 40020070 .word 0x40020070 8009df8: 40020088 .word 0x40020088 8009dfc: 400200a0 .word 0x400200a0 8009e00: 400200b8 .word 0x400200b8 8009e04: 40020410 .word 0x40020410 8009e08: 40020428 .word 0x40020428 8009e0c: 40020440 .word 0x40020440 8009e10: 40020458 .word 0x40020458 8009e14: 40020470 .word 0x40020470 8009e18: 40020488 .word 0x40020488 8009e1c: 400204a0 .word 0x400204a0 8009e20: 400204b8 .word 0x400204b8 8009e24: 687b ldr r3, [r7, #4] 8009e26: 681b ldr r3, [r3, #0] 8009e28: 681b ldr r3, [r3, #0] 8009e2a: f003 0308 and.w r3, r3, #8 8009e2e: 2b00 cmp r3, #0 8009e30: bf14 ite ne 8009e32: 2301 movne r3, #1 8009e34: 2300 moveq r3, #0 8009e36: b2db uxtb r3, r3 8009e38: 2b00 cmp r3, #0 8009e3a: d015 beq.n 8009e68 { /* Disable the transfer error interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); 8009e3c: 687b ldr r3, [r7, #4] 8009e3e: 681b ldr r3, [r3, #0] 8009e40: 681a ldr r2, [r3, #0] 8009e42: 687b ldr r3, [r7, #4] 8009e44: 681b ldr r3, [r3, #0] 8009e46: f022 0204 bic.w r2, r2, #4 8009e4a: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009e4c: 687b ldr r3, [r7, #4] 8009e4e: 6ddb ldr r3, [r3, #92] @ 0x5c 8009e50: f003 031f and.w r3, r3, #31 8009e54: 2208 movs r2, #8 8009e56: 409a lsls r2, r3 8009e58: 6a3b ldr r3, [r7, #32] 8009e5a: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 8009e5c: 687b ldr r3, [r7, #4] 8009e5e: 6d5b ldr r3, [r3, #84] @ 0x54 8009e60: f043 0201 orr.w r2, r3, #1 8009e64: 687b ldr r3, [r7, #4] 8009e66: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009e68: 687b ldr r3, [r7, #4] 8009e6a: 6ddb ldr r3, [r3, #92] @ 0x5c 8009e6c: f003 031f and.w r3, r3, #31 8009e70: 69ba ldr r2, [r7, #24] 8009e72: fa22 f303 lsr.w r3, r2, r3 8009e76: f003 0301 and.w r3, r3, #1 8009e7a: 2b00 cmp r3, #0 8009e7c: d06e beq.n 8009f5c { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) 8009e7e: 687b ldr r3, [r7, #4] 8009e80: 681b ldr r3, [r3, #0] 8009e82: 4a69 ldr r2, [pc, #420] @ (800a028 ) 8009e84: 4293 cmp r3, r2 8009e86: d04a beq.n 8009f1e 8009e88: 687b ldr r3, [r7, #4] 8009e8a: 681b ldr r3, [r3, #0] 8009e8c: 4a67 ldr r2, [pc, #412] @ (800a02c ) 8009e8e: 4293 cmp r3, r2 8009e90: d045 beq.n 8009f1e 8009e92: 687b ldr r3, [r7, #4] 8009e94: 681b ldr r3, [r3, #0] 8009e96: 4a66 ldr r2, [pc, #408] @ (800a030 ) 8009e98: 4293 cmp r3, r2 8009e9a: d040 beq.n 8009f1e 8009e9c: 687b ldr r3, [r7, #4] 8009e9e: 681b ldr r3, [r3, #0] 8009ea0: 4a64 ldr r2, [pc, #400] @ (800a034 ) 8009ea2: 4293 cmp r3, r2 8009ea4: d03b beq.n 8009f1e 8009ea6: 687b ldr r3, [r7, #4] 8009ea8: 681b ldr r3, [r3, #0] 8009eaa: 4a63 ldr r2, [pc, #396] @ (800a038 ) 8009eac: 4293 cmp r3, r2 8009eae: d036 beq.n 8009f1e 8009eb0: 687b ldr r3, [r7, #4] 8009eb2: 681b ldr r3, [r3, #0] 8009eb4: 4a61 ldr r2, [pc, #388] @ (800a03c ) 8009eb6: 4293 cmp r3, r2 8009eb8: d031 beq.n 8009f1e 8009eba: 687b ldr r3, [r7, #4] 8009ebc: 681b ldr r3, [r3, #0] 8009ebe: 4a60 ldr r2, [pc, #384] @ (800a040 ) 8009ec0: 4293 cmp r3, r2 8009ec2: d02c beq.n 8009f1e 8009ec4: 687b ldr r3, [r7, #4] 8009ec6: 681b ldr r3, [r3, #0] 8009ec8: 4a5e ldr r2, [pc, #376] @ (800a044 ) 8009eca: 4293 cmp r3, r2 8009ecc: d027 beq.n 8009f1e 8009ece: 687b ldr r3, [r7, #4] 8009ed0: 681b ldr r3, [r3, #0] 8009ed2: 4a5d ldr r2, [pc, #372] @ (800a048 ) 8009ed4: 4293 cmp r3, r2 8009ed6: d022 beq.n 8009f1e 8009ed8: 687b ldr r3, [r7, #4] 8009eda: 681b ldr r3, [r3, #0] 8009edc: 4a5b ldr r2, [pc, #364] @ (800a04c ) 8009ede: 4293 cmp r3, r2 8009ee0: d01d beq.n 8009f1e 8009ee2: 687b ldr r3, [r7, #4] 8009ee4: 681b ldr r3, [r3, #0] 8009ee6: 4a5a ldr r2, [pc, #360] @ (800a050 ) 8009ee8: 4293 cmp r3, r2 8009eea: d018 beq.n 8009f1e 8009eec: 687b ldr r3, [r7, #4] 8009eee: 681b ldr r3, [r3, #0] 8009ef0: 4a58 ldr r2, [pc, #352] @ (800a054 ) 8009ef2: 4293 cmp r3, r2 8009ef4: d013 beq.n 8009f1e 8009ef6: 687b ldr r3, [r7, #4] 8009ef8: 681b ldr r3, [r3, #0] 8009efa: 4a57 ldr r2, [pc, #348] @ (800a058 ) 8009efc: 4293 cmp r3, r2 8009efe: d00e beq.n 8009f1e 8009f00: 687b ldr r3, [r7, #4] 8009f02: 681b ldr r3, [r3, #0] 8009f04: 4a55 ldr r2, [pc, #340] @ (800a05c ) 8009f06: 4293 cmp r3, r2 8009f08: d009 beq.n 8009f1e 8009f0a: 687b ldr r3, [r7, #4] 8009f0c: 681b ldr r3, [r3, #0] 8009f0e: 4a54 ldr r2, [pc, #336] @ (800a060 ) 8009f10: 4293 cmp r3, r2 8009f12: d004 beq.n 8009f1e 8009f14: 687b ldr r3, [r7, #4] 8009f16: 681b ldr r3, [r3, #0] 8009f18: 4a52 ldr r2, [pc, #328] @ (800a064 ) 8009f1a: 4293 cmp r3, r2 8009f1c: d10a bne.n 8009f34 8009f1e: 687b ldr r3, [r7, #4] 8009f20: 681b ldr r3, [r3, #0] 8009f22: 695b ldr r3, [r3, #20] 8009f24: f003 0380 and.w r3, r3, #128 @ 0x80 8009f28: 2b00 cmp r3, #0 8009f2a: bf14 ite ne 8009f2c: 2301 movne r3, #1 8009f2e: 2300 moveq r3, #0 8009f30: b2db uxtb r3, r3 8009f32: e003 b.n 8009f3c 8009f34: 687b ldr r3, [r7, #4] 8009f36: 681b ldr r3, [r3, #0] 8009f38: 681b ldr r3, [r3, #0] 8009f3a: 2300 movs r3, #0 8009f3c: 2b00 cmp r3, #0 8009f3e: d00d beq.n 8009f5c { /* Clear the FIFO error flag */ regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009f40: 687b ldr r3, [r7, #4] 8009f42: 6ddb ldr r3, [r3, #92] @ 0x5c 8009f44: f003 031f and.w r3, r3, #31 8009f48: 2201 movs r2, #1 8009f4a: 409a lsls r2, r3 8009f4c: 6a3b ldr r3, [r7, #32] 8009f4e: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 8009f50: 687b ldr r3, [r7, #4] 8009f52: 6d5b ldr r3, [r3, #84] @ 0x54 8009f54: f043 0202 orr.w r2, r3, #2 8009f58: 687b ldr r3, [r7, #4] 8009f5a: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009f5c: 687b ldr r3, [r7, #4] 8009f5e: 6ddb ldr r3, [r3, #92] @ 0x5c 8009f60: f003 031f and.w r3, r3, #31 8009f64: 2204 movs r2, #4 8009f66: 409a lsls r2, r3 8009f68: 69bb ldr r3, [r7, #24] 8009f6a: 4013 ands r3, r2 8009f6c: 2b00 cmp r3, #0 8009f6e: f000 808f beq.w 800a090 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) 8009f72: 687b ldr r3, [r7, #4] 8009f74: 681b ldr r3, [r3, #0] 8009f76: 4a2c ldr r2, [pc, #176] @ (800a028 ) 8009f78: 4293 cmp r3, r2 8009f7a: d04a beq.n 800a012 8009f7c: 687b ldr r3, [r7, #4] 8009f7e: 681b ldr r3, [r3, #0] 8009f80: 4a2a ldr r2, [pc, #168] @ (800a02c ) 8009f82: 4293 cmp r3, r2 8009f84: d045 beq.n 800a012 8009f86: 687b ldr r3, [r7, #4] 8009f88: 681b ldr r3, [r3, #0] 8009f8a: 4a29 ldr r2, [pc, #164] @ (800a030 ) 8009f8c: 4293 cmp r3, r2 8009f8e: d040 beq.n 800a012 8009f90: 687b ldr r3, [r7, #4] 8009f92: 681b ldr r3, [r3, #0] 8009f94: 4a27 ldr r2, [pc, #156] @ (800a034 ) 8009f96: 4293 cmp r3, r2 8009f98: d03b beq.n 800a012 8009f9a: 687b ldr r3, [r7, #4] 8009f9c: 681b ldr r3, [r3, #0] 8009f9e: 4a26 ldr r2, [pc, #152] @ (800a038 ) 8009fa0: 4293 cmp r3, r2 8009fa2: d036 beq.n 800a012 8009fa4: 687b ldr r3, [r7, #4] 8009fa6: 681b ldr r3, [r3, #0] 8009fa8: 4a24 ldr r2, [pc, #144] @ (800a03c ) 8009faa: 4293 cmp r3, r2 8009fac: d031 beq.n 800a012 8009fae: 687b ldr r3, [r7, #4] 8009fb0: 681b ldr r3, [r3, #0] 8009fb2: 4a23 ldr r2, [pc, #140] @ (800a040 ) 8009fb4: 4293 cmp r3, r2 8009fb6: d02c beq.n 800a012 8009fb8: 687b ldr r3, [r7, #4] 8009fba: 681b ldr r3, [r3, #0] 8009fbc: 4a21 ldr r2, [pc, #132] @ (800a044 ) 8009fbe: 4293 cmp r3, r2 8009fc0: d027 beq.n 800a012 8009fc2: 687b ldr r3, [r7, #4] 8009fc4: 681b ldr r3, [r3, #0] 8009fc6: 4a20 ldr r2, [pc, #128] @ (800a048 ) 8009fc8: 4293 cmp r3, r2 8009fca: d022 beq.n 800a012 8009fcc: 687b ldr r3, [r7, #4] 8009fce: 681b ldr r3, [r3, #0] 8009fd0: 4a1e ldr r2, [pc, #120] @ (800a04c ) 8009fd2: 4293 cmp r3, r2 8009fd4: d01d beq.n 800a012 8009fd6: 687b ldr r3, [r7, #4] 8009fd8: 681b ldr r3, [r3, #0] 8009fda: 4a1d ldr r2, [pc, #116] @ (800a050 ) 8009fdc: 4293 cmp r3, r2 8009fde: d018 beq.n 800a012 8009fe0: 687b ldr r3, [r7, #4] 8009fe2: 681b ldr r3, [r3, #0] 8009fe4: 4a1b ldr r2, [pc, #108] @ (800a054 ) 8009fe6: 4293 cmp r3, r2 8009fe8: d013 beq.n 800a012 8009fea: 687b ldr r3, [r7, #4] 8009fec: 681b ldr r3, [r3, #0] 8009fee: 4a1a ldr r2, [pc, #104] @ (800a058 ) 8009ff0: 4293 cmp r3, r2 8009ff2: d00e beq.n 800a012 8009ff4: 687b ldr r3, [r7, #4] 8009ff6: 681b ldr r3, [r3, #0] 8009ff8: 4a18 ldr r2, [pc, #96] @ (800a05c ) 8009ffa: 4293 cmp r3, r2 8009ffc: d009 beq.n 800a012 8009ffe: 687b ldr r3, [r7, #4] 800a000: 681b ldr r3, [r3, #0] 800a002: 4a17 ldr r2, [pc, #92] @ (800a060 ) 800a004: 4293 cmp r3, r2 800a006: d004 beq.n 800a012 800a008: 687b ldr r3, [r7, #4] 800a00a: 681b ldr r3, [r3, #0] 800a00c: 4a15 ldr r2, [pc, #84] @ (800a064 ) 800a00e: 4293 cmp r3, r2 800a010: d12a bne.n 800a068 800a012: 687b ldr r3, [r7, #4] 800a014: 681b ldr r3, [r3, #0] 800a016: 681b ldr r3, [r3, #0] 800a018: f003 0302 and.w r3, r3, #2 800a01c: 2b00 cmp r3, #0 800a01e: bf14 ite ne 800a020: 2301 movne r3, #1 800a022: 2300 moveq r3, #0 800a024: b2db uxtb r3, r3 800a026: e023 b.n 800a070 800a028: 40020010 .word 0x40020010 800a02c: 40020028 .word 0x40020028 800a030: 40020040 .word 0x40020040 800a034: 40020058 .word 0x40020058 800a038: 40020070 .word 0x40020070 800a03c: 40020088 .word 0x40020088 800a040: 400200a0 .word 0x400200a0 800a044: 400200b8 .word 0x400200b8 800a048: 40020410 .word 0x40020410 800a04c: 40020428 .word 0x40020428 800a050: 40020440 .word 0x40020440 800a054: 40020458 .word 0x40020458 800a058: 40020470 .word 0x40020470 800a05c: 40020488 .word 0x40020488 800a060: 400204a0 .word 0x400204a0 800a064: 400204b8 .word 0x400204b8 800a068: 687b ldr r3, [r7, #4] 800a06a: 681b ldr r3, [r3, #0] 800a06c: 681b ldr r3, [r3, #0] 800a06e: 2300 movs r3, #0 800a070: 2b00 cmp r3, #0 800a072: d00d beq.n 800a090 { /* Clear the direct mode error flag */ regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); 800a074: 687b ldr r3, [r7, #4] 800a076: 6ddb ldr r3, [r3, #92] @ 0x5c 800a078: f003 031f and.w r3, r3, #31 800a07c: 2204 movs r2, #4 800a07e: 409a lsls r2, r3 800a080: 6a3b ldr r3, [r7, #32] 800a082: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 800a084: 687b ldr r3, [r7, #4] 800a086: 6d5b ldr r3, [r3, #84] @ 0x54 800a088: f043 0204 orr.w r2, r3, #4 800a08c: 687b ldr r3, [r7, #4] 800a08e: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 800a090: 687b ldr r3, [r7, #4] 800a092: 6ddb ldr r3, [r3, #92] @ 0x5c 800a094: f003 031f and.w r3, r3, #31 800a098: 2210 movs r2, #16 800a09a: 409a lsls r2, r3 800a09c: 69bb ldr r3, [r7, #24] 800a09e: 4013 ands r3, r2 800a0a0: 2b00 cmp r3, #0 800a0a2: f000 80a6 beq.w 800a1f2 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) 800a0a6: 687b ldr r3, [r7, #4] 800a0a8: 681b ldr r3, [r3, #0] 800a0aa: 4a85 ldr r2, [pc, #532] @ (800a2c0 ) 800a0ac: 4293 cmp r3, r2 800a0ae: d04a beq.n 800a146 800a0b0: 687b ldr r3, [r7, #4] 800a0b2: 681b ldr r3, [r3, #0] 800a0b4: 4a83 ldr r2, [pc, #524] @ (800a2c4 ) 800a0b6: 4293 cmp r3, r2 800a0b8: d045 beq.n 800a146 800a0ba: 687b ldr r3, [r7, #4] 800a0bc: 681b ldr r3, [r3, #0] 800a0be: 4a82 ldr r2, [pc, #520] @ (800a2c8 ) 800a0c0: 4293 cmp r3, r2 800a0c2: d040 beq.n 800a146 800a0c4: 687b ldr r3, [r7, #4] 800a0c6: 681b ldr r3, [r3, #0] 800a0c8: 4a80 ldr r2, [pc, #512] @ (800a2cc ) 800a0ca: 4293 cmp r3, r2 800a0cc: d03b beq.n 800a146 800a0ce: 687b ldr r3, [r7, #4] 800a0d0: 681b ldr r3, [r3, #0] 800a0d2: 4a7f ldr r2, [pc, #508] @ (800a2d0 ) 800a0d4: 4293 cmp r3, r2 800a0d6: d036 beq.n 800a146 800a0d8: 687b ldr r3, [r7, #4] 800a0da: 681b ldr r3, [r3, #0] 800a0dc: 4a7d ldr r2, [pc, #500] @ (800a2d4 ) 800a0de: 4293 cmp r3, r2 800a0e0: d031 beq.n 800a146 800a0e2: 687b ldr r3, [r7, #4] 800a0e4: 681b ldr r3, [r3, #0] 800a0e6: 4a7c ldr r2, [pc, #496] @ (800a2d8 ) 800a0e8: 4293 cmp r3, r2 800a0ea: d02c beq.n 800a146 800a0ec: 687b ldr r3, [r7, #4] 800a0ee: 681b ldr r3, [r3, #0] 800a0f0: 4a7a ldr r2, [pc, #488] @ (800a2dc ) 800a0f2: 4293 cmp r3, r2 800a0f4: d027 beq.n 800a146 800a0f6: 687b ldr r3, [r7, #4] 800a0f8: 681b ldr r3, [r3, #0] 800a0fa: 4a79 ldr r2, [pc, #484] @ (800a2e0 ) 800a0fc: 4293 cmp r3, r2 800a0fe: d022 beq.n 800a146 800a100: 687b ldr r3, [r7, #4] 800a102: 681b ldr r3, [r3, #0] 800a104: 4a77 ldr r2, [pc, #476] @ (800a2e4 ) 800a106: 4293 cmp r3, r2 800a108: d01d beq.n 800a146 800a10a: 687b ldr r3, [r7, #4] 800a10c: 681b ldr r3, [r3, #0] 800a10e: 4a76 ldr r2, [pc, #472] @ (800a2e8 ) 800a110: 4293 cmp r3, r2 800a112: d018 beq.n 800a146 800a114: 687b ldr r3, [r7, #4] 800a116: 681b ldr r3, [r3, #0] 800a118: 4a74 ldr r2, [pc, #464] @ (800a2ec ) 800a11a: 4293 cmp r3, r2 800a11c: d013 beq.n 800a146 800a11e: 687b ldr r3, [r7, #4] 800a120: 681b ldr r3, [r3, #0] 800a122: 4a73 ldr r2, [pc, #460] @ (800a2f0 ) 800a124: 4293 cmp r3, r2 800a126: d00e beq.n 800a146 800a128: 687b ldr r3, [r7, #4] 800a12a: 681b ldr r3, [r3, #0] 800a12c: 4a71 ldr r2, [pc, #452] @ (800a2f4 ) 800a12e: 4293 cmp r3, r2 800a130: d009 beq.n 800a146 800a132: 687b ldr r3, [r7, #4] 800a134: 681b ldr r3, [r3, #0] 800a136: 4a70 ldr r2, [pc, #448] @ (800a2f8 ) 800a138: 4293 cmp r3, r2 800a13a: d004 beq.n 800a146 800a13c: 687b ldr r3, [r7, #4] 800a13e: 681b ldr r3, [r3, #0] 800a140: 4a6e ldr r2, [pc, #440] @ (800a2fc ) 800a142: 4293 cmp r3, r2 800a144: d10a bne.n 800a15c 800a146: 687b ldr r3, [r7, #4] 800a148: 681b ldr r3, [r3, #0] 800a14a: 681b ldr r3, [r3, #0] 800a14c: f003 0308 and.w r3, r3, #8 800a150: 2b00 cmp r3, #0 800a152: bf14 ite ne 800a154: 2301 movne r3, #1 800a156: 2300 moveq r3, #0 800a158: b2db uxtb r3, r3 800a15a: e009 b.n 800a170 800a15c: 687b ldr r3, [r7, #4] 800a15e: 681b ldr r3, [r3, #0] 800a160: 681b ldr r3, [r3, #0] 800a162: f003 0304 and.w r3, r3, #4 800a166: 2b00 cmp r3, #0 800a168: bf14 ite ne 800a16a: 2301 movne r3, #1 800a16c: 2300 moveq r3, #0 800a16e: b2db uxtb r3, r3 800a170: 2b00 cmp r3, #0 800a172: d03e beq.n 800a1f2 { /* Clear the half transfer complete flag */ regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); 800a174: 687b ldr r3, [r7, #4] 800a176: 6ddb ldr r3, [r3, #92] @ 0x5c 800a178: f003 031f and.w r3, r3, #31 800a17c: 2210 movs r2, #16 800a17e: 409a lsls r2, r3 800a180: 6a3b ldr r3, [r7, #32] 800a182: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 800a184: 687b ldr r3, [r7, #4] 800a186: 681b ldr r3, [r3, #0] 800a188: 681b ldr r3, [r3, #0] 800a18a: f403 2380 and.w r3, r3, #262144 @ 0x40000 800a18e: 2b00 cmp r3, #0 800a190: d018 beq.n 800a1c4 { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 800a192: 687b ldr r3, [r7, #4] 800a194: 681b ldr r3, [r3, #0] 800a196: 681b ldr r3, [r3, #0] 800a198: f403 2300 and.w r3, r3, #524288 @ 0x80000 800a19c: 2b00 cmp r3, #0 800a19e: d108 bne.n 800a1b2 { if(hdma->XferHalfCpltCallback != NULL) 800a1a0: 687b ldr r3, [r7, #4] 800a1a2: 6c1b ldr r3, [r3, #64] @ 0x40 800a1a4: 2b00 cmp r3, #0 800a1a6: d024 beq.n 800a1f2 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800a1a8: 687b ldr r3, [r7, #4] 800a1aa: 6c1b ldr r3, [r3, #64] @ 0x40 800a1ac: 6878 ldr r0, [r7, #4] 800a1ae: 4798 blx r3 800a1b0: e01f b.n 800a1f2 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 800a1b2: 687b ldr r3, [r7, #4] 800a1b4: 6c9b ldr r3, [r3, #72] @ 0x48 800a1b6: 2b00 cmp r3, #0 800a1b8: d01b beq.n 800a1f2 { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 800a1ba: 687b ldr r3, [r7, #4] 800a1bc: 6c9b ldr r3, [r3, #72] @ 0x48 800a1be: 6878 ldr r0, [r7, #4] 800a1c0: 4798 blx r3 800a1c2: e016 b.n 800a1f2 } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 800a1c4: 687b ldr r3, [r7, #4] 800a1c6: 681b ldr r3, [r3, #0] 800a1c8: 681b ldr r3, [r3, #0] 800a1ca: f403 7380 and.w r3, r3, #256 @ 0x100 800a1ce: 2b00 cmp r3, #0 800a1d0: d107 bne.n 800a1e2 { /* Disable the half transfer interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 800a1d2: 687b ldr r3, [r7, #4] 800a1d4: 681b ldr r3, [r3, #0] 800a1d6: 681a ldr r2, [r3, #0] 800a1d8: 687b ldr r3, [r7, #4] 800a1da: 681b ldr r3, [r3, #0] 800a1dc: f022 0208 bic.w r2, r2, #8 800a1e0: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 800a1e2: 687b ldr r3, [r7, #4] 800a1e4: 6c1b ldr r3, [r3, #64] @ 0x40 800a1e6: 2b00 cmp r3, #0 800a1e8: d003 beq.n 800a1f2 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800a1ea: 687b ldr r3, [r7, #4] 800a1ec: 6c1b ldr r3, [r3, #64] @ 0x40 800a1ee: 6878 ldr r0, [r7, #4] 800a1f0: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 800a1f2: 687b ldr r3, [r7, #4] 800a1f4: 6ddb ldr r3, [r3, #92] @ 0x5c 800a1f6: f003 031f and.w r3, r3, #31 800a1fa: 2220 movs r2, #32 800a1fc: 409a lsls r2, r3 800a1fe: 69bb ldr r3, [r7, #24] 800a200: 4013 ands r3, r2 800a202: 2b00 cmp r3, #0 800a204: f000 8110 beq.w 800a428 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) 800a208: 687b ldr r3, [r7, #4] 800a20a: 681b ldr r3, [r3, #0] 800a20c: 4a2c ldr r2, [pc, #176] @ (800a2c0 ) 800a20e: 4293 cmp r3, r2 800a210: d04a beq.n 800a2a8 800a212: 687b ldr r3, [r7, #4] 800a214: 681b ldr r3, [r3, #0] 800a216: 4a2b ldr r2, [pc, #172] @ (800a2c4 ) 800a218: 4293 cmp r3, r2 800a21a: d045 beq.n 800a2a8 800a21c: 687b ldr r3, [r7, #4] 800a21e: 681b ldr r3, [r3, #0] 800a220: 4a29 ldr r2, [pc, #164] @ (800a2c8 ) 800a222: 4293 cmp r3, r2 800a224: d040 beq.n 800a2a8 800a226: 687b ldr r3, [r7, #4] 800a228: 681b ldr r3, [r3, #0] 800a22a: 4a28 ldr r2, [pc, #160] @ (800a2cc ) 800a22c: 4293 cmp r3, r2 800a22e: d03b beq.n 800a2a8 800a230: 687b ldr r3, [r7, #4] 800a232: 681b ldr r3, [r3, #0] 800a234: 4a26 ldr r2, [pc, #152] @ (800a2d0 ) 800a236: 4293 cmp r3, r2 800a238: d036 beq.n 800a2a8 800a23a: 687b ldr r3, [r7, #4] 800a23c: 681b ldr r3, [r3, #0] 800a23e: 4a25 ldr r2, [pc, #148] @ (800a2d4 ) 800a240: 4293 cmp r3, r2 800a242: d031 beq.n 800a2a8 800a244: 687b ldr r3, [r7, #4] 800a246: 681b ldr r3, [r3, #0] 800a248: 4a23 ldr r2, [pc, #140] @ (800a2d8 ) 800a24a: 4293 cmp r3, r2 800a24c: d02c beq.n 800a2a8 800a24e: 687b ldr r3, [r7, #4] 800a250: 681b ldr r3, [r3, #0] 800a252: 4a22 ldr r2, [pc, #136] @ (800a2dc ) 800a254: 4293 cmp r3, r2 800a256: d027 beq.n 800a2a8 800a258: 687b ldr r3, [r7, #4] 800a25a: 681b ldr r3, [r3, #0] 800a25c: 4a20 ldr r2, [pc, #128] @ (800a2e0 ) 800a25e: 4293 cmp r3, r2 800a260: d022 beq.n 800a2a8 800a262: 687b ldr r3, [r7, #4] 800a264: 681b ldr r3, [r3, #0] 800a266: 4a1f ldr r2, [pc, #124] @ (800a2e4 ) 800a268: 4293 cmp r3, r2 800a26a: d01d beq.n 800a2a8 800a26c: 687b ldr r3, [r7, #4] 800a26e: 681b ldr r3, [r3, #0] 800a270: 4a1d ldr r2, [pc, #116] @ (800a2e8 ) 800a272: 4293 cmp r3, r2 800a274: d018 beq.n 800a2a8 800a276: 687b ldr r3, [r7, #4] 800a278: 681b ldr r3, [r3, #0] 800a27a: 4a1c ldr r2, [pc, #112] @ (800a2ec ) 800a27c: 4293 cmp r3, r2 800a27e: d013 beq.n 800a2a8 800a280: 687b ldr r3, [r7, #4] 800a282: 681b ldr r3, [r3, #0] 800a284: 4a1a ldr r2, [pc, #104] @ (800a2f0 ) 800a286: 4293 cmp r3, r2 800a288: d00e beq.n 800a2a8 800a28a: 687b ldr r3, [r7, #4] 800a28c: 681b ldr r3, [r3, #0] 800a28e: 4a19 ldr r2, [pc, #100] @ (800a2f4 ) 800a290: 4293 cmp r3, r2 800a292: d009 beq.n 800a2a8 800a294: 687b ldr r3, [r7, #4] 800a296: 681b ldr r3, [r3, #0] 800a298: 4a17 ldr r2, [pc, #92] @ (800a2f8 ) 800a29a: 4293 cmp r3, r2 800a29c: d004 beq.n 800a2a8 800a29e: 687b ldr r3, [r7, #4] 800a2a0: 681b ldr r3, [r3, #0] 800a2a2: 4a16 ldr r2, [pc, #88] @ (800a2fc ) 800a2a4: 4293 cmp r3, r2 800a2a6: d12b bne.n 800a300 800a2a8: 687b ldr r3, [r7, #4] 800a2aa: 681b ldr r3, [r3, #0] 800a2ac: 681b ldr r3, [r3, #0] 800a2ae: f003 0310 and.w r3, r3, #16 800a2b2: 2b00 cmp r3, #0 800a2b4: bf14 ite ne 800a2b6: 2301 movne r3, #1 800a2b8: 2300 moveq r3, #0 800a2ba: b2db uxtb r3, r3 800a2bc: e02a b.n 800a314 800a2be: bf00 nop 800a2c0: 40020010 .word 0x40020010 800a2c4: 40020028 .word 0x40020028 800a2c8: 40020040 .word 0x40020040 800a2cc: 40020058 .word 0x40020058 800a2d0: 40020070 .word 0x40020070 800a2d4: 40020088 .word 0x40020088 800a2d8: 400200a0 .word 0x400200a0 800a2dc: 400200b8 .word 0x400200b8 800a2e0: 40020410 .word 0x40020410 800a2e4: 40020428 .word 0x40020428 800a2e8: 40020440 .word 0x40020440 800a2ec: 40020458 .word 0x40020458 800a2f0: 40020470 .word 0x40020470 800a2f4: 40020488 .word 0x40020488 800a2f8: 400204a0 .word 0x400204a0 800a2fc: 400204b8 .word 0x400204b8 800a300: 687b ldr r3, [r7, #4] 800a302: 681b ldr r3, [r3, #0] 800a304: 681b ldr r3, [r3, #0] 800a306: f003 0302 and.w r3, r3, #2 800a30a: 2b00 cmp r3, #0 800a30c: bf14 ite ne 800a30e: 2301 movne r3, #1 800a310: 2300 moveq r3, #0 800a312: b2db uxtb r3, r3 800a314: 2b00 cmp r3, #0 800a316: f000 8087 beq.w 800a428 { /* Clear the transfer complete flag */ regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); 800a31a: 687b ldr r3, [r7, #4] 800a31c: 6ddb ldr r3, [r3, #92] @ 0x5c 800a31e: f003 031f and.w r3, r3, #31 800a322: 2220 movs r2, #32 800a324: 409a lsls r2, r3 800a326: 6a3b ldr r3, [r7, #32] 800a328: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 800a32a: 687b ldr r3, [r7, #4] 800a32c: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 800a330: b2db uxtb r3, r3 800a332: 2b04 cmp r3, #4 800a334: d139 bne.n 800a3aa { /* Disable all the transfer interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 800a336: 687b ldr r3, [r7, #4] 800a338: 681b ldr r3, [r3, #0] 800a33a: 681a ldr r2, [r3, #0] 800a33c: 687b ldr r3, [r7, #4] 800a33e: 681b ldr r3, [r3, #0] 800a340: f022 0216 bic.w r2, r2, #22 800a344: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 800a346: 687b ldr r3, [r7, #4] 800a348: 681b ldr r3, [r3, #0] 800a34a: 695a ldr r2, [r3, #20] 800a34c: 687b ldr r3, [r7, #4] 800a34e: 681b ldr r3, [r3, #0] 800a350: f022 0280 bic.w r2, r2, #128 @ 0x80 800a354: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 800a356: 687b ldr r3, [r7, #4] 800a358: 6c1b ldr r3, [r3, #64] @ 0x40 800a35a: 2b00 cmp r3, #0 800a35c: d103 bne.n 800a366 800a35e: 687b ldr r3, [r7, #4] 800a360: 6c9b ldr r3, [r3, #72] @ 0x48 800a362: 2b00 cmp r3, #0 800a364: d007 beq.n 800a376 { ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 800a366: 687b ldr r3, [r7, #4] 800a368: 681b ldr r3, [r3, #0] 800a36a: 681a ldr r2, [r3, #0] 800a36c: 687b ldr r3, [r7, #4] 800a36e: 681b ldr r3, [r3, #0] 800a370: f022 0208 bic.w r2, r2, #8 800a374: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800a376: 687b ldr r3, [r7, #4] 800a378: 6ddb ldr r3, [r3, #92] @ 0x5c 800a37a: f003 031f and.w r3, r3, #31 800a37e: 223f movs r2, #63 @ 0x3f 800a380: 409a lsls r2, r3 800a382: 6a3b ldr r3, [r7, #32] 800a384: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a386: 687b ldr r3, [r7, #4] 800a388: 2201 movs r2, #1 800a38a: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a38e: 687b ldr r3, [r7, #4] 800a390: 2200 movs r2, #0 800a392: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 800a396: 687b ldr r3, [r7, #4] 800a398: 6d1b ldr r3, [r3, #80] @ 0x50 800a39a: 2b00 cmp r3, #0 800a39c: f000 834a beq.w 800aa34 { hdma->XferAbortCallback(hdma); 800a3a0: 687b ldr r3, [r7, #4] 800a3a2: 6d1b ldr r3, [r3, #80] @ 0x50 800a3a4: 6878 ldr r0, [r7, #4] 800a3a6: 4798 blx r3 } return; 800a3a8: e344 b.n 800aa34 } if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 800a3aa: 687b ldr r3, [r7, #4] 800a3ac: 681b ldr r3, [r3, #0] 800a3ae: 681b ldr r3, [r3, #0] 800a3b0: f403 2380 and.w r3, r3, #262144 @ 0x40000 800a3b4: 2b00 cmp r3, #0 800a3b6: d018 beq.n 800a3ea { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 800a3b8: 687b ldr r3, [r7, #4] 800a3ba: 681b ldr r3, [r3, #0] 800a3bc: 681b ldr r3, [r3, #0] 800a3be: f403 2300 and.w r3, r3, #524288 @ 0x80000 800a3c2: 2b00 cmp r3, #0 800a3c4: d108 bne.n 800a3d8 { if(hdma->XferM1CpltCallback != NULL) 800a3c6: 687b ldr r3, [r7, #4] 800a3c8: 6c5b ldr r3, [r3, #68] @ 0x44 800a3ca: 2b00 cmp r3, #0 800a3cc: d02c beq.n 800a428 { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 800a3ce: 687b ldr r3, [r7, #4] 800a3d0: 6c5b ldr r3, [r3, #68] @ 0x44 800a3d2: 6878 ldr r0, [r7, #4] 800a3d4: 4798 blx r3 800a3d6: e027 b.n 800a428 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800a3d8: 687b ldr r3, [r7, #4] 800a3da: 6bdb ldr r3, [r3, #60] @ 0x3c 800a3dc: 2b00 cmp r3, #0 800a3de: d023 beq.n 800a428 { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 800a3e0: 687b ldr r3, [r7, #4] 800a3e2: 6bdb ldr r3, [r3, #60] @ 0x3c 800a3e4: 6878 ldr r0, [r7, #4] 800a3e6: 4798 blx r3 800a3e8: e01e b.n 800a428 } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 800a3ea: 687b ldr r3, [r7, #4] 800a3ec: 681b ldr r3, [r3, #0] 800a3ee: 681b ldr r3, [r3, #0] 800a3f0: f403 7380 and.w r3, r3, #256 @ 0x100 800a3f4: 2b00 cmp r3, #0 800a3f6: d10f bne.n 800a418 { /* Disable the transfer complete interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); 800a3f8: 687b ldr r3, [r7, #4] 800a3fa: 681b ldr r3, [r3, #0] 800a3fc: 681a ldr r2, [r3, #0] 800a3fe: 687b ldr r3, [r7, #4] 800a400: 681b ldr r3, [r3, #0] 800a402: f022 0210 bic.w r2, r2, #16 800a406: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a408: 687b ldr r3, [r7, #4] 800a40a: 2201 movs r2, #1 800a40c: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a410: 687b ldr r3, [r7, #4] 800a412: 2200 movs r2, #0 800a414: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 800a418: 687b ldr r3, [r7, #4] 800a41a: 6bdb ldr r3, [r3, #60] @ 0x3c 800a41c: 2b00 cmp r3, #0 800a41e: d003 beq.n 800a428 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 800a420: 687b ldr r3, [r7, #4] 800a422: 6bdb ldr r3, [r3, #60] @ 0x3c 800a424: 6878 ldr r0, [r7, #4] 800a426: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 800a428: 687b ldr r3, [r7, #4] 800a42a: 6d5b ldr r3, [r3, #84] @ 0x54 800a42c: 2b00 cmp r3, #0 800a42e: f000 8306 beq.w 800aa3e { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) 800a432: 687b ldr r3, [r7, #4] 800a434: 6d5b ldr r3, [r3, #84] @ 0x54 800a436: f003 0301 and.w r3, r3, #1 800a43a: 2b00 cmp r3, #0 800a43c: f000 8088 beq.w 800a550 { hdma->State = HAL_DMA_STATE_ABORT; 800a440: 687b ldr r3, [r7, #4] 800a442: 2204 movs r2, #4 800a444: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800a448: 687b ldr r3, [r7, #4] 800a44a: 681b ldr r3, [r3, #0] 800a44c: 4a7a ldr r2, [pc, #488] @ (800a638 ) 800a44e: 4293 cmp r3, r2 800a450: d04a beq.n 800a4e8 800a452: 687b ldr r3, [r7, #4] 800a454: 681b ldr r3, [r3, #0] 800a456: 4a79 ldr r2, [pc, #484] @ (800a63c ) 800a458: 4293 cmp r3, r2 800a45a: d045 beq.n 800a4e8 800a45c: 687b ldr r3, [r7, #4] 800a45e: 681b ldr r3, [r3, #0] 800a460: 4a77 ldr r2, [pc, #476] @ (800a640 ) 800a462: 4293 cmp r3, r2 800a464: d040 beq.n 800a4e8 800a466: 687b ldr r3, [r7, #4] 800a468: 681b ldr r3, [r3, #0] 800a46a: 4a76 ldr r2, [pc, #472] @ (800a644 ) 800a46c: 4293 cmp r3, r2 800a46e: d03b beq.n 800a4e8 800a470: 687b ldr r3, [r7, #4] 800a472: 681b ldr r3, [r3, #0] 800a474: 4a74 ldr r2, [pc, #464] @ (800a648 ) 800a476: 4293 cmp r3, r2 800a478: d036 beq.n 800a4e8 800a47a: 687b ldr r3, [r7, #4] 800a47c: 681b ldr r3, [r3, #0] 800a47e: 4a73 ldr r2, [pc, #460] @ (800a64c ) 800a480: 4293 cmp r3, r2 800a482: d031 beq.n 800a4e8 800a484: 687b ldr r3, [r7, #4] 800a486: 681b ldr r3, [r3, #0] 800a488: 4a71 ldr r2, [pc, #452] @ (800a650 ) 800a48a: 4293 cmp r3, r2 800a48c: d02c beq.n 800a4e8 800a48e: 687b ldr r3, [r7, #4] 800a490: 681b ldr r3, [r3, #0] 800a492: 4a70 ldr r2, [pc, #448] @ (800a654 ) 800a494: 4293 cmp r3, r2 800a496: d027 beq.n 800a4e8 800a498: 687b ldr r3, [r7, #4] 800a49a: 681b ldr r3, [r3, #0] 800a49c: 4a6e ldr r2, [pc, #440] @ (800a658 ) 800a49e: 4293 cmp r3, r2 800a4a0: d022 beq.n 800a4e8 800a4a2: 687b ldr r3, [r7, #4] 800a4a4: 681b ldr r3, [r3, #0] 800a4a6: 4a6d ldr r2, [pc, #436] @ (800a65c ) 800a4a8: 4293 cmp r3, r2 800a4aa: d01d beq.n 800a4e8 800a4ac: 687b ldr r3, [r7, #4] 800a4ae: 681b ldr r3, [r3, #0] 800a4b0: 4a6b ldr r2, [pc, #428] @ (800a660 ) 800a4b2: 4293 cmp r3, r2 800a4b4: d018 beq.n 800a4e8 800a4b6: 687b ldr r3, [r7, #4] 800a4b8: 681b ldr r3, [r3, #0] 800a4ba: 4a6a ldr r2, [pc, #424] @ (800a664 ) 800a4bc: 4293 cmp r3, r2 800a4be: d013 beq.n 800a4e8 800a4c0: 687b ldr r3, [r7, #4] 800a4c2: 681b ldr r3, [r3, #0] 800a4c4: 4a68 ldr r2, [pc, #416] @ (800a668 ) 800a4c6: 4293 cmp r3, r2 800a4c8: d00e beq.n 800a4e8 800a4ca: 687b ldr r3, [r7, #4] 800a4cc: 681b ldr r3, [r3, #0] 800a4ce: 4a67 ldr r2, [pc, #412] @ (800a66c ) 800a4d0: 4293 cmp r3, r2 800a4d2: d009 beq.n 800a4e8 800a4d4: 687b ldr r3, [r7, #4] 800a4d6: 681b ldr r3, [r3, #0] 800a4d8: 4a65 ldr r2, [pc, #404] @ (800a670 ) 800a4da: 4293 cmp r3, r2 800a4dc: d004 beq.n 800a4e8 800a4de: 687b ldr r3, [r7, #4] 800a4e0: 681b ldr r3, [r3, #0] 800a4e2: 4a64 ldr r2, [pc, #400] @ (800a674 ) 800a4e4: 4293 cmp r3, r2 800a4e6: d108 bne.n 800a4fa 800a4e8: 687b ldr r3, [r7, #4] 800a4ea: 681b ldr r3, [r3, #0] 800a4ec: 681a ldr r2, [r3, #0] 800a4ee: 687b ldr r3, [r7, #4] 800a4f0: 681b ldr r3, [r3, #0] 800a4f2: f022 0201 bic.w r2, r2, #1 800a4f6: 601a str r2, [r3, #0] 800a4f8: e007 b.n 800a50a 800a4fa: 687b ldr r3, [r7, #4] 800a4fc: 681b ldr r3, [r3, #0] 800a4fe: 681a ldr r2, [r3, #0] 800a500: 687b ldr r3, [r7, #4] 800a502: 681b ldr r3, [r3, #0] 800a504: f022 0201 bic.w r2, r2, #1 800a508: 601a str r2, [r3, #0] do { if (++count > timeout) 800a50a: 68fb ldr r3, [r7, #12] 800a50c: 3301 adds r3, #1 800a50e: 60fb str r3, [r7, #12] 800a510: 6a7a ldr r2, [r7, #36] @ 0x24 800a512: 429a cmp r2, r3 800a514: d307 bcc.n 800a526 { break; } } while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); 800a516: 687b ldr r3, [r7, #4] 800a518: 681b ldr r3, [r3, #0] 800a51a: 681b ldr r3, [r3, #0] 800a51c: f003 0301 and.w r3, r3, #1 800a520: 2b00 cmp r3, #0 800a522: d1f2 bne.n 800a50a 800a524: e000 b.n 800a528 break; 800a526: bf00 nop if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 800a528: 687b ldr r3, [r7, #4] 800a52a: 681b ldr r3, [r3, #0] 800a52c: 681b ldr r3, [r3, #0] 800a52e: f003 0301 and.w r3, r3, #1 800a532: 2b00 cmp r3, #0 800a534: d004 beq.n 800a540 { /* Change the DMA state to error if DMA disable fails */ hdma->State = HAL_DMA_STATE_ERROR; 800a536: 687b ldr r3, [r7, #4] 800a538: 2203 movs r2, #3 800a53a: f883 2035 strb.w r2, [r3, #53] @ 0x35 800a53e: e003 b.n 800a548 } else { /* Change the DMA state to Ready if DMA disable success */ hdma->State = HAL_DMA_STATE_READY; 800a540: 687b ldr r3, [r7, #4] 800a542: 2201 movs r2, #1 800a544: f883 2035 strb.w r2, [r3, #53] @ 0x35 } /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a548: 687b ldr r3, [r7, #4] 800a54a: 2200 movs r2, #0 800a54c: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 800a550: 687b ldr r3, [r7, #4] 800a552: 6cdb ldr r3, [r3, #76] @ 0x4c 800a554: 2b00 cmp r3, #0 800a556: f000 8272 beq.w 800aa3e { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800a55a: 687b ldr r3, [r7, #4] 800a55c: 6cdb ldr r3, [r3, #76] @ 0x4c 800a55e: 6878 ldr r0, [r7, #4] 800a560: 4798 blx r3 800a562: e26c b.n 800aa3e } } } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 800a564: 687b ldr r3, [r7, #4] 800a566: 681b ldr r3, [r3, #0] 800a568: 4a43 ldr r2, [pc, #268] @ (800a678 ) 800a56a: 4293 cmp r3, r2 800a56c: d022 beq.n 800a5b4 800a56e: 687b ldr r3, [r7, #4] 800a570: 681b ldr r3, [r3, #0] 800a572: 4a42 ldr r2, [pc, #264] @ (800a67c ) 800a574: 4293 cmp r3, r2 800a576: d01d beq.n 800a5b4 800a578: 687b ldr r3, [r7, #4] 800a57a: 681b ldr r3, [r3, #0] 800a57c: 4a40 ldr r2, [pc, #256] @ (800a680 ) 800a57e: 4293 cmp r3, r2 800a580: d018 beq.n 800a5b4 800a582: 687b ldr r3, [r7, #4] 800a584: 681b ldr r3, [r3, #0] 800a586: 4a3f ldr r2, [pc, #252] @ (800a684 ) 800a588: 4293 cmp r3, r2 800a58a: d013 beq.n 800a5b4 800a58c: 687b ldr r3, [r7, #4] 800a58e: 681b ldr r3, [r3, #0] 800a590: 4a3d ldr r2, [pc, #244] @ (800a688 ) 800a592: 4293 cmp r3, r2 800a594: d00e beq.n 800a5b4 800a596: 687b ldr r3, [r7, #4] 800a598: 681b ldr r3, [r3, #0] 800a59a: 4a3c ldr r2, [pc, #240] @ (800a68c ) 800a59c: 4293 cmp r3, r2 800a59e: d009 beq.n 800a5b4 800a5a0: 687b ldr r3, [r7, #4] 800a5a2: 681b ldr r3, [r3, #0] 800a5a4: 4a3a ldr r2, [pc, #232] @ (800a690 ) 800a5a6: 4293 cmp r3, r2 800a5a8: d004 beq.n 800a5b4 800a5aa: 687b ldr r3, [r7, #4] 800a5ac: 681b ldr r3, [r3, #0] 800a5ae: 4a39 ldr r2, [pc, #228] @ (800a694 ) 800a5b0: 4293 cmp r3, r2 800a5b2: d101 bne.n 800a5b8 800a5b4: 2301 movs r3, #1 800a5b6: e000 b.n 800a5ba 800a5b8: 2300 movs r3, #0 800a5ba: 2b00 cmp r3, #0 800a5bc: f000 823f beq.w 800aa3e { ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); 800a5c0: 687b ldr r3, [r7, #4] 800a5c2: 681b ldr r3, [r3, #0] 800a5c4: 681b ldr r3, [r3, #0] 800a5c6: 613b str r3, [r7, #16] /* Half Transfer Complete Interrupt management ******************************/ if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) 800a5c8: 687b ldr r3, [r7, #4] 800a5ca: 6ddb ldr r3, [r3, #92] @ 0x5c 800a5cc: f003 031f and.w r3, r3, #31 800a5d0: 2204 movs r2, #4 800a5d2: 409a lsls r2, r3 800a5d4: 697b ldr r3, [r7, #20] 800a5d6: 4013 ands r3, r2 800a5d8: 2b00 cmp r3, #0 800a5da: f000 80cd beq.w 800a778 800a5de: 693b ldr r3, [r7, #16] 800a5e0: f003 0304 and.w r3, r3, #4 800a5e4: 2b00 cmp r3, #0 800a5e6: f000 80c7 beq.w 800a778 { /* Clear the half transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); 800a5ea: 687b ldr r3, [r7, #4] 800a5ec: 6ddb ldr r3, [r3, #92] @ 0x5c 800a5ee: f003 031f and.w r3, r3, #31 800a5f2: 2204 movs r2, #4 800a5f4: 409a lsls r2, r3 800a5f6: 69fb ldr r3, [r7, #28] 800a5f8: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a5fa: 693b ldr r3, [r7, #16] 800a5fc: f403 4300 and.w r3, r3, #32768 @ 0x8000 800a600: 2b00 cmp r3, #0 800a602: d049 beq.n 800a698 { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 800a604: 693b ldr r3, [r7, #16] 800a606: f403 3380 and.w r3, r3, #65536 @ 0x10000 800a60a: 2b00 cmp r3, #0 800a60c: d109 bne.n 800a622 { if(hdma->XferM1HalfCpltCallback != NULL) 800a60e: 687b ldr r3, [r7, #4] 800a610: 6c9b ldr r3, [r3, #72] @ 0x48 800a612: 2b00 cmp r3, #0 800a614: f000 8210 beq.w 800aa38 { /* Half transfer Callback for Memory 1 */ hdma->XferM1HalfCpltCallback(hdma); 800a618: 687b ldr r3, [r7, #4] 800a61a: 6c9b ldr r3, [r3, #72] @ 0x48 800a61c: 6878 ldr r0, [r7, #4] 800a61e: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a620: e20a b.n 800aa38 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferHalfCpltCallback != NULL) 800a622: 687b ldr r3, [r7, #4] 800a624: 6c1b ldr r3, [r3, #64] @ 0x40 800a626: 2b00 cmp r3, #0 800a628: f000 8206 beq.w 800aa38 { /* Half transfer Callback for Memory 0 */ hdma->XferHalfCpltCallback(hdma); 800a62c: 687b ldr r3, [r7, #4] 800a62e: 6c1b ldr r3, [r3, #64] @ 0x40 800a630: 6878 ldr r0, [r7, #4] 800a632: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a634: e200 b.n 800aa38 800a636: bf00 nop 800a638: 40020010 .word 0x40020010 800a63c: 40020028 .word 0x40020028 800a640: 40020040 .word 0x40020040 800a644: 40020058 .word 0x40020058 800a648: 40020070 .word 0x40020070 800a64c: 40020088 .word 0x40020088 800a650: 400200a0 .word 0x400200a0 800a654: 400200b8 .word 0x400200b8 800a658: 40020410 .word 0x40020410 800a65c: 40020428 .word 0x40020428 800a660: 40020440 .word 0x40020440 800a664: 40020458 .word 0x40020458 800a668: 40020470 .word 0x40020470 800a66c: 40020488 .word 0x40020488 800a670: 400204a0 .word 0x400204a0 800a674: 400204b8 .word 0x400204b8 800a678: 58025408 .word 0x58025408 800a67c: 5802541c .word 0x5802541c 800a680: 58025430 .word 0x58025430 800a684: 58025444 .word 0x58025444 800a688: 58025458 .word 0x58025458 800a68c: 5802546c .word 0x5802546c 800a690: 58025480 .word 0x58025480 800a694: 58025494 .word 0x58025494 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 800a698: 693b ldr r3, [r7, #16] 800a69a: f003 0320 and.w r3, r3, #32 800a69e: 2b00 cmp r3, #0 800a6a0: d160 bne.n 800a764 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800a6a2: 687b ldr r3, [r7, #4] 800a6a4: 681b ldr r3, [r3, #0] 800a6a6: 4a7f ldr r2, [pc, #508] @ (800a8a4 ) 800a6a8: 4293 cmp r3, r2 800a6aa: d04a beq.n 800a742 800a6ac: 687b ldr r3, [r7, #4] 800a6ae: 681b ldr r3, [r3, #0] 800a6b0: 4a7d ldr r2, [pc, #500] @ (800a8a8 ) 800a6b2: 4293 cmp r3, r2 800a6b4: d045 beq.n 800a742 800a6b6: 687b ldr r3, [r7, #4] 800a6b8: 681b ldr r3, [r3, #0] 800a6ba: 4a7c ldr r2, [pc, #496] @ (800a8ac ) 800a6bc: 4293 cmp r3, r2 800a6be: d040 beq.n 800a742 800a6c0: 687b ldr r3, [r7, #4] 800a6c2: 681b ldr r3, [r3, #0] 800a6c4: 4a7a ldr r2, [pc, #488] @ (800a8b0 ) 800a6c6: 4293 cmp r3, r2 800a6c8: d03b beq.n 800a742 800a6ca: 687b ldr r3, [r7, #4] 800a6cc: 681b ldr r3, [r3, #0] 800a6ce: 4a79 ldr r2, [pc, #484] @ (800a8b4 ) 800a6d0: 4293 cmp r3, r2 800a6d2: d036 beq.n 800a742 800a6d4: 687b ldr r3, [r7, #4] 800a6d6: 681b ldr r3, [r3, #0] 800a6d8: 4a77 ldr r2, [pc, #476] @ (800a8b8 ) 800a6da: 4293 cmp r3, r2 800a6dc: d031 beq.n 800a742 800a6de: 687b ldr r3, [r7, #4] 800a6e0: 681b ldr r3, [r3, #0] 800a6e2: 4a76 ldr r2, [pc, #472] @ (800a8bc ) 800a6e4: 4293 cmp r3, r2 800a6e6: d02c beq.n 800a742 800a6e8: 687b ldr r3, [r7, #4] 800a6ea: 681b ldr r3, [r3, #0] 800a6ec: 4a74 ldr r2, [pc, #464] @ (800a8c0 ) 800a6ee: 4293 cmp r3, r2 800a6f0: d027 beq.n 800a742 800a6f2: 687b ldr r3, [r7, #4] 800a6f4: 681b ldr r3, [r3, #0] 800a6f6: 4a73 ldr r2, [pc, #460] @ (800a8c4 ) 800a6f8: 4293 cmp r3, r2 800a6fa: d022 beq.n 800a742 800a6fc: 687b ldr r3, [r7, #4] 800a6fe: 681b ldr r3, [r3, #0] 800a700: 4a71 ldr r2, [pc, #452] @ (800a8c8 ) 800a702: 4293 cmp r3, r2 800a704: d01d beq.n 800a742 800a706: 687b ldr r3, [r7, #4] 800a708: 681b ldr r3, [r3, #0] 800a70a: 4a70 ldr r2, [pc, #448] @ (800a8cc ) 800a70c: 4293 cmp r3, r2 800a70e: d018 beq.n 800a742 800a710: 687b ldr r3, [r7, #4] 800a712: 681b ldr r3, [r3, #0] 800a714: 4a6e ldr r2, [pc, #440] @ (800a8d0 ) 800a716: 4293 cmp r3, r2 800a718: d013 beq.n 800a742 800a71a: 687b ldr r3, [r7, #4] 800a71c: 681b ldr r3, [r3, #0] 800a71e: 4a6d ldr r2, [pc, #436] @ (800a8d4 ) 800a720: 4293 cmp r3, r2 800a722: d00e beq.n 800a742 800a724: 687b ldr r3, [r7, #4] 800a726: 681b ldr r3, [r3, #0] 800a728: 4a6b ldr r2, [pc, #428] @ (800a8d8 ) 800a72a: 4293 cmp r3, r2 800a72c: d009 beq.n 800a742 800a72e: 687b ldr r3, [r7, #4] 800a730: 681b ldr r3, [r3, #0] 800a732: 4a6a ldr r2, [pc, #424] @ (800a8dc ) 800a734: 4293 cmp r3, r2 800a736: d004 beq.n 800a742 800a738: 687b ldr r3, [r7, #4] 800a73a: 681b ldr r3, [r3, #0] 800a73c: 4a68 ldr r2, [pc, #416] @ (800a8e0 ) 800a73e: 4293 cmp r3, r2 800a740: d108 bne.n 800a754 800a742: 687b ldr r3, [r7, #4] 800a744: 681b ldr r3, [r3, #0] 800a746: 681a ldr r2, [r3, #0] 800a748: 687b ldr r3, [r7, #4] 800a74a: 681b ldr r3, [r3, #0] 800a74c: f022 0208 bic.w r2, r2, #8 800a750: 601a str r2, [r3, #0] 800a752: e007 b.n 800a764 800a754: 687b ldr r3, [r7, #4] 800a756: 681b ldr r3, [r3, #0] 800a758: 681a ldr r2, [r3, #0] 800a75a: 687b ldr r3, [r7, #4] 800a75c: 681b ldr r3, [r3, #0] 800a75e: f022 0204 bic.w r2, r2, #4 800a762: 601a str r2, [r3, #0] } /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 800a764: 687b ldr r3, [r7, #4] 800a766: 6c1b ldr r3, [r3, #64] @ 0x40 800a768: 2b00 cmp r3, #0 800a76a: f000 8165 beq.w 800aa38 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800a76e: 687b ldr r3, [r7, #4] 800a770: 6c1b ldr r3, [r3, #64] @ 0x40 800a772: 6878 ldr r0, [r7, #4] 800a774: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a776: e15f b.n 800aa38 } } } /* Transfer Complete Interrupt management ***********************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) 800a778: 687b ldr r3, [r7, #4] 800a77a: 6ddb ldr r3, [r3, #92] @ 0x5c 800a77c: f003 031f and.w r3, r3, #31 800a780: 2202 movs r2, #2 800a782: 409a lsls r2, r3 800a784: 697b ldr r3, [r7, #20] 800a786: 4013 ands r3, r2 800a788: 2b00 cmp r3, #0 800a78a: f000 80c5 beq.w 800a918 800a78e: 693b ldr r3, [r7, #16] 800a790: f003 0302 and.w r3, r3, #2 800a794: 2b00 cmp r3, #0 800a796: f000 80bf beq.w 800a918 { /* Clear the transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); 800a79a: 687b ldr r3, [r7, #4] 800a79c: 6ddb ldr r3, [r3, #92] @ 0x5c 800a79e: f003 031f and.w r3, r3, #31 800a7a2: 2202 movs r2, #2 800a7a4: 409a lsls r2, r3 800a7a6: 69fb ldr r3, [r7, #28] 800a7a8: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a7aa: 693b ldr r3, [r7, #16] 800a7ac: f403 4300 and.w r3, r3, #32768 @ 0x8000 800a7b0: 2b00 cmp r3, #0 800a7b2: d018 beq.n 800a7e6 { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 800a7b4: 693b ldr r3, [r7, #16] 800a7b6: f403 3380 and.w r3, r3, #65536 @ 0x10000 800a7ba: 2b00 cmp r3, #0 800a7bc: d109 bne.n 800a7d2 { if(hdma->XferM1CpltCallback != NULL) 800a7be: 687b ldr r3, [r7, #4] 800a7c0: 6c5b ldr r3, [r3, #68] @ 0x44 800a7c2: 2b00 cmp r3, #0 800a7c4: f000 813a beq.w 800aa3c { /* Transfer complete Callback for Memory 1 */ hdma->XferM1CpltCallback(hdma); 800a7c8: 687b ldr r3, [r7, #4] 800a7ca: 6c5b ldr r3, [r3, #68] @ 0x44 800a7cc: 6878 ldr r0, [r7, #4] 800a7ce: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a7d0: e134 b.n 800aa3c } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800a7d2: 687b ldr r3, [r7, #4] 800a7d4: 6bdb ldr r3, [r3, #60] @ 0x3c 800a7d6: 2b00 cmp r3, #0 800a7d8: f000 8130 beq.w 800aa3c { /* Transfer complete Callback for Memory 0 */ hdma->XferCpltCallback(hdma); 800a7dc: 687b ldr r3, [r7, #4] 800a7de: 6bdb ldr r3, [r3, #60] @ 0x3c 800a7e0: 6878 ldr r0, [r7, #4] 800a7e2: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a7e4: e12a b.n 800aa3c } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 800a7e6: 693b ldr r3, [r7, #16] 800a7e8: f003 0320 and.w r3, r3, #32 800a7ec: 2b00 cmp r3, #0 800a7ee: f040 8089 bne.w 800a904 { /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 800a7f2: 687b ldr r3, [r7, #4] 800a7f4: 681b ldr r3, [r3, #0] 800a7f6: 4a2b ldr r2, [pc, #172] @ (800a8a4 ) 800a7f8: 4293 cmp r3, r2 800a7fa: d04a beq.n 800a892 800a7fc: 687b ldr r3, [r7, #4] 800a7fe: 681b ldr r3, [r3, #0] 800a800: 4a29 ldr r2, [pc, #164] @ (800a8a8 ) 800a802: 4293 cmp r3, r2 800a804: d045 beq.n 800a892 800a806: 687b ldr r3, [r7, #4] 800a808: 681b ldr r3, [r3, #0] 800a80a: 4a28 ldr r2, [pc, #160] @ (800a8ac ) 800a80c: 4293 cmp r3, r2 800a80e: d040 beq.n 800a892 800a810: 687b ldr r3, [r7, #4] 800a812: 681b ldr r3, [r3, #0] 800a814: 4a26 ldr r2, [pc, #152] @ (800a8b0 ) 800a816: 4293 cmp r3, r2 800a818: d03b beq.n 800a892 800a81a: 687b ldr r3, [r7, #4] 800a81c: 681b ldr r3, [r3, #0] 800a81e: 4a25 ldr r2, [pc, #148] @ (800a8b4 ) 800a820: 4293 cmp r3, r2 800a822: d036 beq.n 800a892 800a824: 687b ldr r3, [r7, #4] 800a826: 681b ldr r3, [r3, #0] 800a828: 4a23 ldr r2, [pc, #140] @ (800a8b8 ) 800a82a: 4293 cmp r3, r2 800a82c: d031 beq.n 800a892 800a82e: 687b ldr r3, [r7, #4] 800a830: 681b ldr r3, [r3, #0] 800a832: 4a22 ldr r2, [pc, #136] @ (800a8bc ) 800a834: 4293 cmp r3, r2 800a836: d02c beq.n 800a892 800a838: 687b ldr r3, [r7, #4] 800a83a: 681b ldr r3, [r3, #0] 800a83c: 4a20 ldr r2, [pc, #128] @ (800a8c0 ) 800a83e: 4293 cmp r3, r2 800a840: d027 beq.n 800a892 800a842: 687b ldr r3, [r7, #4] 800a844: 681b ldr r3, [r3, #0] 800a846: 4a1f ldr r2, [pc, #124] @ (800a8c4 ) 800a848: 4293 cmp r3, r2 800a84a: d022 beq.n 800a892 800a84c: 687b ldr r3, [r7, #4] 800a84e: 681b ldr r3, [r3, #0] 800a850: 4a1d ldr r2, [pc, #116] @ (800a8c8 ) 800a852: 4293 cmp r3, r2 800a854: d01d beq.n 800a892 800a856: 687b ldr r3, [r7, #4] 800a858: 681b ldr r3, [r3, #0] 800a85a: 4a1c ldr r2, [pc, #112] @ (800a8cc ) 800a85c: 4293 cmp r3, r2 800a85e: d018 beq.n 800a892 800a860: 687b ldr r3, [r7, #4] 800a862: 681b ldr r3, [r3, #0] 800a864: 4a1a ldr r2, [pc, #104] @ (800a8d0 ) 800a866: 4293 cmp r3, r2 800a868: d013 beq.n 800a892 800a86a: 687b ldr r3, [r7, #4] 800a86c: 681b ldr r3, [r3, #0] 800a86e: 4a19 ldr r2, [pc, #100] @ (800a8d4 ) 800a870: 4293 cmp r3, r2 800a872: d00e beq.n 800a892 800a874: 687b ldr r3, [r7, #4] 800a876: 681b ldr r3, [r3, #0] 800a878: 4a17 ldr r2, [pc, #92] @ (800a8d8 ) 800a87a: 4293 cmp r3, r2 800a87c: d009 beq.n 800a892 800a87e: 687b ldr r3, [r7, #4] 800a880: 681b ldr r3, [r3, #0] 800a882: 4a16 ldr r2, [pc, #88] @ (800a8dc ) 800a884: 4293 cmp r3, r2 800a886: d004 beq.n 800a892 800a888: 687b ldr r3, [r7, #4] 800a88a: 681b ldr r3, [r3, #0] 800a88c: 4a14 ldr r2, [pc, #80] @ (800a8e0 ) 800a88e: 4293 cmp r3, r2 800a890: d128 bne.n 800a8e4 800a892: 687b ldr r3, [r7, #4] 800a894: 681b ldr r3, [r3, #0] 800a896: 681a ldr r2, [r3, #0] 800a898: 687b ldr r3, [r7, #4] 800a89a: 681b ldr r3, [r3, #0] 800a89c: f022 0214 bic.w r2, r2, #20 800a8a0: 601a str r2, [r3, #0] 800a8a2: e027 b.n 800a8f4 800a8a4: 40020010 .word 0x40020010 800a8a8: 40020028 .word 0x40020028 800a8ac: 40020040 .word 0x40020040 800a8b0: 40020058 .word 0x40020058 800a8b4: 40020070 .word 0x40020070 800a8b8: 40020088 .word 0x40020088 800a8bc: 400200a0 .word 0x400200a0 800a8c0: 400200b8 .word 0x400200b8 800a8c4: 40020410 .word 0x40020410 800a8c8: 40020428 .word 0x40020428 800a8cc: 40020440 .word 0x40020440 800a8d0: 40020458 .word 0x40020458 800a8d4: 40020470 .word 0x40020470 800a8d8: 40020488 .word 0x40020488 800a8dc: 400204a0 .word 0x400204a0 800a8e0: 400204b8 .word 0x400204b8 800a8e4: 687b ldr r3, [r7, #4] 800a8e6: 681b ldr r3, [r3, #0] 800a8e8: 681a ldr r2, [r3, #0] 800a8ea: 687b ldr r3, [r7, #4] 800a8ec: 681b ldr r3, [r3, #0] 800a8ee: f022 020a bic.w r2, r2, #10 800a8f2: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a8f4: 687b ldr r3, [r7, #4] 800a8f6: 2201 movs r2, #1 800a8f8: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a8fc: 687b ldr r3, [r7, #4] 800a8fe: 2200 movs r2, #0 800a900: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 800a904: 687b ldr r3, [r7, #4] 800a906: 6bdb ldr r3, [r3, #60] @ 0x3c 800a908: 2b00 cmp r3, #0 800a90a: f000 8097 beq.w 800aa3c { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 800a90e: 687b ldr r3, [r7, #4] 800a910: 6bdb ldr r3, [r3, #60] @ 0x3c 800a912: 6878 ldr r0, [r7, #4] 800a914: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a916: e091 b.n 800aa3c } } } /* Transfer Error Interrupt management **************************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) 800a918: 687b ldr r3, [r7, #4] 800a91a: 6ddb ldr r3, [r3, #92] @ 0x5c 800a91c: f003 031f and.w r3, r3, #31 800a920: 2208 movs r2, #8 800a922: 409a lsls r2, r3 800a924: 697b ldr r3, [r7, #20] 800a926: 4013 ands r3, r2 800a928: 2b00 cmp r3, #0 800a92a: f000 8088 beq.w 800aa3e 800a92e: 693b ldr r3, [r7, #16] 800a930: f003 0308 and.w r3, r3, #8 800a934: 2b00 cmp r3, #0 800a936: f000 8082 beq.w 800aa3e { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800a93a: 687b ldr r3, [r7, #4] 800a93c: 681b ldr r3, [r3, #0] 800a93e: 4a41 ldr r2, [pc, #260] @ (800aa44 ) 800a940: 4293 cmp r3, r2 800a942: d04a beq.n 800a9da 800a944: 687b ldr r3, [r7, #4] 800a946: 681b ldr r3, [r3, #0] 800a948: 4a3f ldr r2, [pc, #252] @ (800aa48 ) 800a94a: 4293 cmp r3, r2 800a94c: d045 beq.n 800a9da 800a94e: 687b ldr r3, [r7, #4] 800a950: 681b ldr r3, [r3, #0] 800a952: 4a3e ldr r2, [pc, #248] @ (800aa4c ) 800a954: 4293 cmp r3, r2 800a956: d040 beq.n 800a9da 800a958: 687b ldr r3, [r7, #4] 800a95a: 681b ldr r3, [r3, #0] 800a95c: 4a3c ldr r2, [pc, #240] @ (800aa50 ) 800a95e: 4293 cmp r3, r2 800a960: d03b beq.n 800a9da 800a962: 687b ldr r3, [r7, #4] 800a964: 681b ldr r3, [r3, #0] 800a966: 4a3b ldr r2, [pc, #236] @ (800aa54 ) 800a968: 4293 cmp r3, r2 800a96a: d036 beq.n 800a9da 800a96c: 687b ldr r3, [r7, #4] 800a96e: 681b ldr r3, [r3, #0] 800a970: 4a39 ldr r2, [pc, #228] @ (800aa58 ) 800a972: 4293 cmp r3, r2 800a974: d031 beq.n 800a9da 800a976: 687b ldr r3, [r7, #4] 800a978: 681b ldr r3, [r3, #0] 800a97a: 4a38 ldr r2, [pc, #224] @ (800aa5c ) 800a97c: 4293 cmp r3, r2 800a97e: d02c beq.n 800a9da 800a980: 687b ldr r3, [r7, #4] 800a982: 681b ldr r3, [r3, #0] 800a984: 4a36 ldr r2, [pc, #216] @ (800aa60 ) 800a986: 4293 cmp r3, r2 800a988: d027 beq.n 800a9da 800a98a: 687b ldr r3, [r7, #4] 800a98c: 681b ldr r3, [r3, #0] 800a98e: 4a35 ldr r2, [pc, #212] @ (800aa64 ) 800a990: 4293 cmp r3, r2 800a992: d022 beq.n 800a9da 800a994: 687b ldr r3, [r7, #4] 800a996: 681b ldr r3, [r3, #0] 800a998: 4a33 ldr r2, [pc, #204] @ (800aa68 ) 800a99a: 4293 cmp r3, r2 800a99c: d01d beq.n 800a9da 800a99e: 687b ldr r3, [r7, #4] 800a9a0: 681b ldr r3, [r3, #0] 800a9a2: 4a32 ldr r2, [pc, #200] @ (800aa6c ) 800a9a4: 4293 cmp r3, r2 800a9a6: d018 beq.n 800a9da 800a9a8: 687b ldr r3, [r7, #4] 800a9aa: 681b ldr r3, [r3, #0] 800a9ac: 4a30 ldr r2, [pc, #192] @ (800aa70 ) 800a9ae: 4293 cmp r3, r2 800a9b0: d013 beq.n 800a9da 800a9b2: 687b ldr r3, [r7, #4] 800a9b4: 681b ldr r3, [r3, #0] 800a9b6: 4a2f ldr r2, [pc, #188] @ (800aa74 ) 800a9b8: 4293 cmp r3, r2 800a9ba: d00e beq.n 800a9da 800a9bc: 687b ldr r3, [r7, #4] 800a9be: 681b ldr r3, [r3, #0] 800a9c0: 4a2d ldr r2, [pc, #180] @ (800aa78 ) 800a9c2: 4293 cmp r3, r2 800a9c4: d009 beq.n 800a9da 800a9c6: 687b ldr r3, [r7, #4] 800a9c8: 681b ldr r3, [r3, #0] 800a9ca: 4a2c ldr r2, [pc, #176] @ (800aa7c ) 800a9cc: 4293 cmp r3, r2 800a9ce: d004 beq.n 800a9da 800a9d0: 687b ldr r3, [r7, #4] 800a9d2: 681b ldr r3, [r3, #0] 800a9d4: 4a2a ldr r2, [pc, #168] @ (800aa80 ) 800a9d6: 4293 cmp r3, r2 800a9d8: d108 bne.n 800a9ec 800a9da: 687b ldr r3, [r7, #4] 800a9dc: 681b ldr r3, [r3, #0] 800a9de: 681a ldr r2, [r3, #0] 800a9e0: 687b ldr r3, [r7, #4] 800a9e2: 681b ldr r3, [r3, #0] 800a9e4: f022 021c bic.w r2, r2, #28 800a9e8: 601a str r2, [r3, #0] 800a9ea: e007 b.n 800a9fc 800a9ec: 687b ldr r3, [r7, #4] 800a9ee: 681b ldr r3, [r3, #0] 800a9f0: 681a ldr r2, [r3, #0] 800a9f2: 687b ldr r3, [r7, #4] 800a9f4: 681b ldr r3, [r3, #0] 800a9f6: f022 020e bic.w r2, r2, #14 800a9fa: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 800a9fc: 687b ldr r3, [r7, #4] 800a9fe: 6ddb ldr r3, [r3, #92] @ 0x5c 800aa00: f003 031f and.w r3, r3, #31 800aa04: 2201 movs r2, #1 800aa06: 409a lsls r2, r3 800aa08: 69fb ldr r3, [r7, #28] 800aa0a: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 800aa0c: 687b ldr r3, [r7, #4] 800aa0e: 2201 movs r2, #1 800aa10: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800aa12: 687b ldr r3, [r7, #4] 800aa14: 2201 movs r2, #1 800aa16: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800aa1a: 687b ldr r3, [r7, #4] 800aa1c: 2200 movs r2, #0 800aa1e: f883 2034 strb.w r2, [r3, #52] @ 0x34 if (hdma->XferErrorCallback != NULL) 800aa22: 687b ldr r3, [r7, #4] 800aa24: 6cdb ldr r3, [r3, #76] @ 0x4c 800aa26: 2b00 cmp r3, #0 800aa28: d009 beq.n 800aa3e { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800aa2a: 687b ldr r3, [r7, #4] 800aa2c: 6cdb ldr r3, [r3, #76] @ 0x4c 800aa2e: 6878 ldr r0, [r7, #4] 800aa30: 4798 blx r3 800aa32: e004 b.n 800aa3e return; 800aa34: bf00 nop 800aa36: e002 b.n 800aa3e if((ccr_reg & BDMA_CCR_DBM) != 0U) 800aa38: bf00 nop 800aa3a: e000 b.n 800aa3e if((ccr_reg & BDMA_CCR_DBM) != 0U) 800aa3c: bf00 nop } else { /* Nothing To Do */ } } 800aa3e: 3728 adds r7, #40 @ 0x28 800aa40: 46bd mov sp, r7 800aa42: bd80 pop {r7, pc} 800aa44: 40020010 .word 0x40020010 800aa48: 40020028 .word 0x40020028 800aa4c: 40020040 .word 0x40020040 800aa50: 40020058 .word 0x40020058 800aa54: 40020070 .word 0x40020070 800aa58: 40020088 .word 0x40020088 800aa5c: 400200a0 .word 0x400200a0 800aa60: 400200b8 .word 0x400200b8 800aa64: 40020410 .word 0x40020410 800aa68: 40020428 .word 0x40020428 800aa6c: 40020440 .word 0x40020440 800aa70: 40020458 .word 0x40020458 800aa74: 40020470 .word 0x40020470 800aa78: 40020488 .word 0x40020488 800aa7c: 400204a0 .word 0x400204a0 800aa80: 400204b8 .word 0x400204b8 0800aa84 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval None */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 800aa84: b480 push {r7} 800aa86: b087 sub sp, #28 800aa88: af00 add r7, sp, #0 800aa8a: 60f8 str r0, [r7, #12] 800aa8c: 60b9 str r1, [r7, #8] 800aa8e: 607a str r2, [r7, #4] 800aa90: 603b str r3, [r7, #0] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 800aa92: 68fb ldr r3, [r7, #12] 800aa94: 6d9b ldr r3, [r3, #88] @ 0x58 800aa96: 617b str r3, [r7, #20] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 800aa98: 68fb ldr r3, [r7, #12] 800aa9a: 6d9b ldr r3, [r3, #88] @ 0x58 800aa9c: 613b str r3, [r7, #16] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800aa9e: 68fb ldr r3, [r7, #12] 800aaa0: 681b ldr r3, [r3, #0] 800aaa2: 4a7f ldr r2, [pc, #508] @ (800aca0 ) 800aaa4: 4293 cmp r3, r2 800aaa6: d072 beq.n 800ab8e 800aaa8: 68fb ldr r3, [r7, #12] 800aaaa: 681b ldr r3, [r3, #0] 800aaac: 4a7d ldr r2, [pc, #500] @ (800aca4 ) 800aaae: 4293 cmp r3, r2 800aab0: d06d beq.n 800ab8e 800aab2: 68fb ldr r3, [r7, #12] 800aab4: 681b ldr r3, [r3, #0] 800aab6: 4a7c ldr r2, [pc, #496] @ (800aca8 ) 800aab8: 4293 cmp r3, r2 800aaba: d068 beq.n 800ab8e 800aabc: 68fb ldr r3, [r7, #12] 800aabe: 681b ldr r3, [r3, #0] 800aac0: 4a7a ldr r2, [pc, #488] @ (800acac ) 800aac2: 4293 cmp r3, r2 800aac4: d063 beq.n 800ab8e 800aac6: 68fb ldr r3, [r7, #12] 800aac8: 681b ldr r3, [r3, #0] 800aaca: 4a79 ldr r2, [pc, #484] @ (800acb0 ) 800aacc: 4293 cmp r3, r2 800aace: d05e beq.n 800ab8e 800aad0: 68fb ldr r3, [r7, #12] 800aad2: 681b ldr r3, [r3, #0] 800aad4: 4a77 ldr r2, [pc, #476] @ (800acb4 ) 800aad6: 4293 cmp r3, r2 800aad8: d059 beq.n 800ab8e 800aada: 68fb ldr r3, [r7, #12] 800aadc: 681b ldr r3, [r3, #0] 800aade: 4a76 ldr r2, [pc, #472] @ (800acb8 ) 800aae0: 4293 cmp r3, r2 800aae2: d054 beq.n 800ab8e 800aae4: 68fb ldr r3, [r7, #12] 800aae6: 681b ldr r3, [r3, #0] 800aae8: 4a74 ldr r2, [pc, #464] @ (800acbc ) 800aaea: 4293 cmp r3, r2 800aaec: d04f beq.n 800ab8e 800aaee: 68fb ldr r3, [r7, #12] 800aaf0: 681b ldr r3, [r3, #0] 800aaf2: 4a73 ldr r2, [pc, #460] @ (800acc0 ) 800aaf4: 4293 cmp r3, r2 800aaf6: d04a beq.n 800ab8e 800aaf8: 68fb ldr r3, [r7, #12] 800aafa: 681b ldr r3, [r3, #0] 800aafc: 4a71 ldr r2, [pc, #452] @ (800acc4 ) 800aafe: 4293 cmp r3, r2 800ab00: d045 beq.n 800ab8e 800ab02: 68fb ldr r3, [r7, #12] 800ab04: 681b ldr r3, [r3, #0] 800ab06: 4a70 ldr r2, [pc, #448] @ (800acc8 ) 800ab08: 4293 cmp r3, r2 800ab0a: d040 beq.n 800ab8e 800ab0c: 68fb ldr r3, [r7, #12] 800ab0e: 681b ldr r3, [r3, #0] 800ab10: 4a6e ldr r2, [pc, #440] @ (800accc ) 800ab12: 4293 cmp r3, r2 800ab14: d03b beq.n 800ab8e 800ab16: 68fb ldr r3, [r7, #12] 800ab18: 681b ldr r3, [r3, #0] 800ab1a: 4a6d ldr r2, [pc, #436] @ (800acd0 ) 800ab1c: 4293 cmp r3, r2 800ab1e: d036 beq.n 800ab8e 800ab20: 68fb ldr r3, [r7, #12] 800ab22: 681b ldr r3, [r3, #0] 800ab24: 4a6b ldr r2, [pc, #428] @ (800acd4 ) 800ab26: 4293 cmp r3, r2 800ab28: d031 beq.n 800ab8e 800ab2a: 68fb ldr r3, [r7, #12] 800ab2c: 681b ldr r3, [r3, #0] 800ab2e: 4a6a ldr r2, [pc, #424] @ (800acd8 ) 800ab30: 4293 cmp r3, r2 800ab32: d02c beq.n 800ab8e 800ab34: 68fb ldr r3, [r7, #12] 800ab36: 681b ldr r3, [r3, #0] 800ab38: 4a68 ldr r2, [pc, #416] @ (800acdc ) 800ab3a: 4293 cmp r3, r2 800ab3c: d027 beq.n 800ab8e 800ab3e: 68fb ldr r3, [r7, #12] 800ab40: 681b ldr r3, [r3, #0] 800ab42: 4a67 ldr r2, [pc, #412] @ (800ace0 ) 800ab44: 4293 cmp r3, r2 800ab46: d022 beq.n 800ab8e 800ab48: 68fb ldr r3, [r7, #12] 800ab4a: 681b ldr r3, [r3, #0] 800ab4c: 4a65 ldr r2, [pc, #404] @ (800ace4 ) 800ab4e: 4293 cmp r3, r2 800ab50: d01d beq.n 800ab8e 800ab52: 68fb ldr r3, [r7, #12] 800ab54: 681b ldr r3, [r3, #0] 800ab56: 4a64 ldr r2, [pc, #400] @ (800ace8 ) 800ab58: 4293 cmp r3, r2 800ab5a: d018 beq.n 800ab8e 800ab5c: 68fb ldr r3, [r7, #12] 800ab5e: 681b ldr r3, [r3, #0] 800ab60: 4a62 ldr r2, [pc, #392] @ (800acec ) 800ab62: 4293 cmp r3, r2 800ab64: d013 beq.n 800ab8e 800ab66: 68fb ldr r3, [r7, #12] 800ab68: 681b ldr r3, [r3, #0] 800ab6a: 4a61 ldr r2, [pc, #388] @ (800acf0 ) 800ab6c: 4293 cmp r3, r2 800ab6e: d00e beq.n 800ab8e 800ab70: 68fb ldr r3, [r7, #12] 800ab72: 681b ldr r3, [r3, #0] 800ab74: 4a5f ldr r2, [pc, #380] @ (800acf4 ) 800ab76: 4293 cmp r3, r2 800ab78: d009 beq.n 800ab8e 800ab7a: 68fb ldr r3, [r7, #12] 800ab7c: 681b ldr r3, [r3, #0] 800ab7e: 4a5e ldr r2, [pc, #376] @ (800acf8 ) 800ab80: 4293 cmp r3, r2 800ab82: d004 beq.n 800ab8e 800ab84: 68fb ldr r3, [r7, #12] 800ab86: 681b ldr r3, [r3, #0] 800ab88: 4a5c ldr r2, [pc, #368] @ (800acfc ) 800ab8a: 4293 cmp r3, r2 800ab8c: d101 bne.n 800ab92 800ab8e: 2301 movs r3, #1 800ab90: e000 b.n 800ab94 800ab92: 2300 movs r3, #0 800ab94: 2b00 cmp r3, #0 800ab96: d00d beq.n 800abb4 { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 800ab98: 68fb ldr r3, [r7, #12] 800ab9a: 6e5b ldr r3, [r3, #100] @ 0x64 800ab9c: 68fa ldr r2, [r7, #12] 800ab9e: 6e92 ldr r2, [r2, #104] @ 0x68 800aba0: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 800aba2: 68fb ldr r3, [r7, #12] 800aba4: 6edb ldr r3, [r3, #108] @ 0x6c 800aba6: 2b00 cmp r3, #0 800aba8: d004 beq.n 800abb4 { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 800abaa: 68fb ldr r3, [r7, #12] 800abac: 6f1b ldr r3, [r3, #112] @ 0x70 800abae: 68fa ldr r2, [r7, #12] 800abb0: 6f52 ldr r2, [r2, #116] @ 0x74 800abb2: 605a str r2, [r3, #4] } } if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800abb4: 68fb ldr r3, [r7, #12] 800abb6: 681b ldr r3, [r3, #0] 800abb8: 4a39 ldr r2, [pc, #228] @ (800aca0 ) 800abba: 4293 cmp r3, r2 800abbc: d04a beq.n 800ac54 800abbe: 68fb ldr r3, [r7, #12] 800abc0: 681b ldr r3, [r3, #0] 800abc2: 4a38 ldr r2, [pc, #224] @ (800aca4 ) 800abc4: 4293 cmp r3, r2 800abc6: d045 beq.n 800ac54 800abc8: 68fb ldr r3, [r7, #12] 800abca: 681b ldr r3, [r3, #0] 800abcc: 4a36 ldr r2, [pc, #216] @ (800aca8 ) 800abce: 4293 cmp r3, r2 800abd0: d040 beq.n 800ac54 800abd2: 68fb ldr r3, [r7, #12] 800abd4: 681b ldr r3, [r3, #0] 800abd6: 4a35 ldr r2, [pc, #212] @ (800acac ) 800abd8: 4293 cmp r3, r2 800abda: d03b beq.n 800ac54 800abdc: 68fb ldr r3, [r7, #12] 800abde: 681b ldr r3, [r3, #0] 800abe0: 4a33 ldr r2, [pc, #204] @ (800acb0 ) 800abe2: 4293 cmp r3, r2 800abe4: d036 beq.n 800ac54 800abe6: 68fb ldr r3, [r7, #12] 800abe8: 681b ldr r3, [r3, #0] 800abea: 4a32 ldr r2, [pc, #200] @ (800acb4 ) 800abec: 4293 cmp r3, r2 800abee: d031 beq.n 800ac54 800abf0: 68fb ldr r3, [r7, #12] 800abf2: 681b ldr r3, [r3, #0] 800abf4: 4a30 ldr r2, [pc, #192] @ (800acb8 ) 800abf6: 4293 cmp r3, r2 800abf8: d02c beq.n 800ac54 800abfa: 68fb ldr r3, [r7, #12] 800abfc: 681b ldr r3, [r3, #0] 800abfe: 4a2f ldr r2, [pc, #188] @ (800acbc ) 800ac00: 4293 cmp r3, r2 800ac02: d027 beq.n 800ac54 800ac04: 68fb ldr r3, [r7, #12] 800ac06: 681b ldr r3, [r3, #0] 800ac08: 4a2d ldr r2, [pc, #180] @ (800acc0 ) 800ac0a: 4293 cmp r3, r2 800ac0c: d022 beq.n 800ac54 800ac0e: 68fb ldr r3, [r7, #12] 800ac10: 681b ldr r3, [r3, #0] 800ac12: 4a2c ldr r2, [pc, #176] @ (800acc4 ) 800ac14: 4293 cmp r3, r2 800ac16: d01d beq.n 800ac54 800ac18: 68fb ldr r3, [r7, #12] 800ac1a: 681b ldr r3, [r3, #0] 800ac1c: 4a2a ldr r2, [pc, #168] @ (800acc8 ) 800ac1e: 4293 cmp r3, r2 800ac20: d018 beq.n 800ac54 800ac22: 68fb ldr r3, [r7, #12] 800ac24: 681b ldr r3, [r3, #0] 800ac26: 4a29 ldr r2, [pc, #164] @ (800accc ) 800ac28: 4293 cmp r3, r2 800ac2a: d013 beq.n 800ac54 800ac2c: 68fb ldr r3, [r7, #12] 800ac2e: 681b ldr r3, [r3, #0] 800ac30: 4a27 ldr r2, [pc, #156] @ (800acd0 ) 800ac32: 4293 cmp r3, r2 800ac34: d00e beq.n 800ac54 800ac36: 68fb ldr r3, [r7, #12] 800ac38: 681b ldr r3, [r3, #0] 800ac3a: 4a26 ldr r2, [pc, #152] @ (800acd4 ) 800ac3c: 4293 cmp r3, r2 800ac3e: d009 beq.n 800ac54 800ac40: 68fb ldr r3, [r7, #12] 800ac42: 681b ldr r3, [r3, #0] 800ac44: 4a24 ldr r2, [pc, #144] @ (800acd8 ) 800ac46: 4293 cmp r3, r2 800ac48: d004 beq.n 800ac54 800ac4a: 68fb ldr r3, [r7, #12] 800ac4c: 681b ldr r3, [r3, #0] 800ac4e: 4a23 ldr r2, [pc, #140] @ (800acdc ) 800ac50: 4293 cmp r3, r2 800ac52: d101 bne.n 800ac58 800ac54: 2301 movs r3, #1 800ac56: e000 b.n 800ac5a 800ac58: 2300 movs r3, #0 800ac5a: 2b00 cmp r3, #0 800ac5c: d059 beq.n 800ad12 { /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800ac5e: 68fb ldr r3, [r7, #12] 800ac60: 6ddb ldr r3, [r3, #92] @ 0x5c 800ac62: f003 031f and.w r3, r3, #31 800ac66: 223f movs r2, #63 @ 0x3f 800ac68: 409a lsls r2, r3 800ac6a: 697b ldr r3, [r7, #20] 800ac6c: 609a str r2, [r3, #8] /* Clear DBM bit */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM); 800ac6e: 68fb ldr r3, [r7, #12] 800ac70: 681b ldr r3, [r3, #0] 800ac72: 681a ldr r2, [r3, #0] 800ac74: 68fb ldr r3, [r7, #12] 800ac76: 681b ldr r3, [r3, #0] 800ac78: f422 2280 bic.w r2, r2, #262144 @ 0x40000 800ac7c: 601a str r2, [r3, #0] /* Configure DMA Stream data length */ ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; 800ac7e: 68fb ldr r3, [r7, #12] 800ac80: 681b ldr r3, [r3, #0] 800ac82: 683a ldr r2, [r7, #0] 800ac84: 605a str r2, [r3, #4] /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800ac86: 68fb ldr r3, [r7, #12] 800ac88: 689b ldr r3, [r3, #8] 800ac8a: 2b40 cmp r3, #64 @ 0x40 800ac8c: d138 bne.n 800ad00 { /* Configure DMA Stream destination address */ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; 800ac8e: 68fb ldr r3, [r7, #12] 800ac90: 681b ldr r3, [r3, #0] 800ac92: 687a ldr r2, [r7, #4] 800ac94: 609a str r2, [r3, #8] /* Configure DMA Stream source address */ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; 800ac96: 68fb ldr r3, [r7, #12] 800ac98: 681b ldr r3, [r3, #0] 800ac9a: 68ba ldr r2, [r7, #8] 800ac9c: 60da str r2, [r3, #12] } else { /* Nothing To Do */ } } 800ac9e: e086 b.n 800adae 800aca0: 40020010 .word 0x40020010 800aca4: 40020028 .word 0x40020028 800aca8: 40020040 .word 0x40020040 800acac: 40020058 .word 0x40020058 800acb0: 40020070 .word 0x40020070 800acb4: 40020088 .word 0x40020088 800acb8: 400200a0 .word 0x400200a0 800acbc: 400200b8 .word 0x400200b8 800acc0: 40020410 .word 0x40020410 800acc4: 40020428 .word 0x40020428 800acc8: 40020440 .word 0x40020440 800accc: 40020458 .word 0x40020458 800acd0: 40020470 .word 0x40020470 800acd4: 40020488 .word 0x40020488 800acd8: 400204a0 .word 0x400204a0 800acdc: 400204b8 .word 0x400204b8 800ace0: 58025408 .word 0x58025408 800ace4: 5802541c .word 0x5802541c 800ace8: 58025430 .word 0x58025430 800acec: 58025444 .word 0x58025444 800acf0: 58025458 .word 0x58025458 800acf4: 5802546c .word 0x5802546c 800acf8: 58025480 .word 0x58025480 800acfc: 58025494 .word 0x58025494 ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; 800ad00: 68fb ldr r3, [r7, #12] 800ad02: 681b ldr r3, [r3, #0] 800ad04: 68ba ldr r2, [r7, #8] 800ad06: 609a str r2, [r3, #8] ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; 800ad08: 68fb ldr r3, [r7, #12] 800ad0a: 681b ldr r3, [r3, #0] 800ad0c: 687a ldr r2, [r7, #4] 800ad0e: 60da str r2, [r3, #12] } 800ad10: e04d b.n 800adae else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 800ad12: 68fb ldr r3, [r7, #12] 800ad14: 681b ldr r3, [r3, #0] 800ad16: 4a29 ldr r2, [pc, #164] @ (800adbc ) 800ad18: 4293 cmp r3, r2 800ad1a: d022 beq.n 800ad62 800ad1c: 68fb ldr r3, [r7, #12] 800ad1e: 681b ldr r3, [r3, #0] 800ad20: 4a27 ldr r2, [pc, #156] @ (800adc0 ) 800ad22: 4293 cmp r3, r2 800ad24: d01d beq.n 800ad62 800ad26: 68fb ldr r3, [r7, #12] 800ad28: 681b ldr r3, [r3, #0] 800ad2a: 4a26 ldr r2, [pc, #152] @ (800adc4 ) 800ad2c: 4293 cmp r3, r2 800ad2e: d018 beq.n 800ad62 800ad30: 68fb ldr r3, [r7, #12] 800ad32: 681b ldr r3, [r3, #0] 800ad34: 4a24 ldr r2, [pc, #144] @ (800adc8 ) 800ad36: 4293 cmp r3, r2 800ad38: d013 beq.n 800ad62 800ad3a: 68fb ldr r3, [r7, #12] 800ad3c: 681b ldr r3, [r3, #0] 800ad3e: 4a23 ldr r2, [pc, #140] @ (800adcc ) 800ad40: 4293 cmp r3, r2 800ad42: d00e beq.n 800ad62 800ad44: 68fb ldr r3, [r7, #12] 800ad46: 681b ldr r3, [r3, #0] 800ad48: 4a21 ldr r2, [pc, #132] @ (800add0 ) 800ad4a: 4293 cmp r3, r2 800ad4c: d009 beq.n 800ad62 800ad4e: 68fb ldr r3, [r7, #12] 800ad50: 681b ldr r3, [r3, #0] 800ad52: 4a20 ldr r2, [pc, #128] @ (800add4 ) 800ad54: 4293 cmp r3, r2 800ad56: d004 beq.n 800ad62 800ad58: 68fb ldr r3, [r7, #12] 800ad5a: 681b ldr r3, [r3, #0] 800ad5c: 4a1e ldr r2, [pc, #120] @ (800add8 ) 800ad5e: 4293 cmp r3, r2 800ad60: d101 bne.n 800ad66 800ad62: 2301 movs r3, #1 800ad64: e000 b.n 800ad68 800ad66: 2300 movs r3, #0 800ad68: 2b00 cmp r3, #0 800ad6a: d020 beq.n 800adae regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 800ad6c: 68fb ldr r3, [r7, #12] 800ad6e: 6ddb ldr r3, [r3, #92] @ 0x5c 800ad70: f003 031f and.w r3, r3, #31 800ad74: 2201 movs r2, #1 800ad76: 409a lsls r2, r3 800ad78: 693b ldr r3, [r7, #16] 800ad7a: 605a str r2, [r3, #4] ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; 800ad7c: 68fb ldr r3, [r7, #12] 800ad7e: 681b ldr r3, [r3, #0] 800ad80: 683a ldr r2, [r7, #0] 800ad82: 605a str r2, [r3, #4] if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800ad84: 68fb ldr r3, [r7, #12] 800ad86: 689b ldr r3, [r3, #8] 800ad88: 2b40 cmp r3, #64 @ 0x40 800ad8a: d108 bne.n 800ad9e ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; 800ad8c: 68fb ldr r3, [r7, #12] 800ad8e: 681b ldr r3, [r3, #0] 800ad90: 687a ldr r2, [r7, #4] 800ad92: 609a str r2, [r3, #8] ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; 800ad94: 68fb ldr r3, [r7, #12] 800ad96: 681b ldr r3, [r3, #0] 800ad98: 68ba ldr r2, [r7, #8] 800ad9a: 60da str r2, [r3, #12] } 800ad9c: e007 b.n 800adae ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; 800ad9e: 68fb ldr r3, [r7, #12] 800ada0: 681b ldr r3, [r3, #0] 800ada2: 68ba ldr r2, [r7, #8] 800ada4: 609a str r2, [r3, #8] ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; 800ada6: 68fb ldr r3, [r7, #12] 800ada8: 681b ldr r3, [r3, #0] 800adaa: 687a ldr r2, [r7, #4] 800adac: 60da str r2, [r3, #12] } 800adae: bf00 nop 800adb0: 371c adds r7, #28 800adb2: 46bd mov sp, r7 800adb4: f85d 7b04 ldr.w r7, [sp], #4 800adb8: 4770 bx lr 800adba: bf00 nop 800adbc: 58025408 .word 0x58025408 800adc0: 5802541c .word 0x5802541c 800adc4: 58025430 .word 0x58025430 800adc8: 58025444 .word 0x58025444 800adcc: 58025458 .word 0x58025458 800add0: 5802546c .word 0x5802546c 800add4: 58025480 .word 0x58025480 800add8: 58025494 .word 0x58025494 0800addc : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 800addc: b480 push {r7} 800adde: b085 sub sp, #20 800ade0: af00 add r7, sp, #0 800ade2: 6078 str r0, [r7, #4] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800ade4: 687b ldr r3, [r7, #4] 800ade6: 681b ldr r3, [r3, #0] 800ade8: 4a42 ldr r2, [pc, #264] @ (800aef4 ) 800adea: 4293 cmp r3, r2 800adec: d04a beq.n 800ae84 800adee: 687b ldr r3, [r7, #4] 800adf0: 681b ldr r3, [r3, #0] 800adf2: 4a41 ldr r2, [pc, #260] @ (800aef8 ) 800adf4: 4293 cmp r3, r2 800adf6: d045 beq.n 800ae84 800adf8: 687b ldr r3, [r7, #4] 800adfa: 681b ldr r3, [r3, #0] 800adfc: 4a3f ldr r2, [pc, #252] @ (800aefc ) 800adfe: 4293 cmp r3, r2 800ae00: d040 beq.n 800ae84 800ae02: 687b ldr r3, [r7, #4] 800ae04: 681b ldr r3, [r3, #0] 800ae06: 4a3e ldr r2, [pc, #248] @ (800af00 ) 800ae08: 4293 cmp r3, r2 800ae0a: d03b beq.n 800ae84 800ae0c: 687b ldr r3, [r7, #4] 800ae0e: 681b ldr r3, [r3, #0] 800ae10: 4a3c ldr r2, [pc, #240] @ (800af04 ) 800ae12: 4293 cmp r3, r2 800ae14: d036 beq.n 800ae84 800ae16: 687b ldr r3, [r7, #4] 800ae18: 681b ldr r3, [r3, #0] 800ae1a: 4a3b ldr r2, [pc, #236] @ (800af08 ) 800ae1c: 4293 cmp r3, r2 800ae1e: d031 beq.n 800ae84 800ae20: 687b ldr r3, [r7, #4] 800ae22: 681b ldr r3, [r3, #0] 800ae24: 4a39 ldr r2, [pc, #228] @ (800af0c ) 800ae26: 4293 cmp r3, r2 800ae28: d02c beq.n 800ae84 800ae2a: 687b ldr r3, [r7, #4] 800ae2c: 681b ldr r3, [r3, #0] 800ae2e: 4a38 ldr r2, [pc, #224] @ (800af10 ) 800ae30: 4293 cmp r3, r2 800ae32: d027 beq.n 800ae84 800ae34: 687b ldr r3, [r7, #4] 800ae36: 681b ldr r3, [r3, #0] 800ae38: 4a36 ldr r2, [pc, #216] @ (800af14 ) 800ae3a: 4293 cmp r3, r2 800ae3c: d022 beq.n 800ae84 800ae3e: 687b ldr r3, [r7, #4] 800ae40: 681b ldr r3, [r3, #0] 800ae42: 4a35 ldr r2, [pc, #212] @ (800af18 ) 800ae44: 4293 cmp r3, r2 800ae46: d01d beq.n 800ae84 800ae48: 687b ldr r3, [r7, #4] 800ae4a: 681b ldr r3, [r3, #0] 800ae4c: 4a33 ldr r2, [pc, #204] @ (800af1c ) 800ae4e: 4293 cmp r3, r2 800ae50: d018 beq.n 800ae84 800ae52: 687b ldr r3, [r7, #4] 800ae54: 681b ldr r3, [r3, #0] 800ae56: 4a32 ldr r2, [pc, #200] @ (800af20 ) 800ae58: 4293 cmp r3, r2 800ae5a: d013 beq.n 800ae84 800ae5c: 687b ldr r3, [r7, #4] 800ae5e: 681b ldr r3, [r3, #0] 800ae60: 4a30 ldr r2, [pc, #192] @ (800af24 ) 800ae62: 4293 cmp r3, r2 800ae64: d00e beq.n 800ae84 800ae66: 687b ldr r3, [r7, #4] 800ae68: 681b ldr r3, [r3, #0] 800ae6a: 4a2f ldr r2, [pc, #188] @ (800af28 ) 800ae6c: 4293 cmp r3, r2 800ae6e: d009 beq.n 800ae84 800ae70: 687b ldr r3, [r7, #4] 800ae72: 681b ldr r3, [r3, #0] 800ae74: 4a2d ldr r2, [pc, #180] @ (800af2c ) 800ae76: 4293 cmp r3, r2 800ae78: d004 beq.n 800ae84 800ae7a: 687b ldr r3, [r7, #4] 800ae7c: 681b ldr r3, [r3, #0] 800ae7e: 4a2c ldr r2, [pc, #176] @ (800af30 ) 800ae80: 4293 cmp r3, r2 800ae82: d101 bne.n 800ae88 800ae84: 2301 movs r3, #1 800ae86: e000 b.n 800ae8a 800ae88: 2300 movs r3, #0 800ae8a: 2b00 cmp r3, #0 800ae8c: d024 beq.n 800aed8 { uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800ae8e: 687b ldr r3, [r7, #4] 800ae90: 681b ldr r3, [r3, #0] 800ae92: b2db uxtb r3, r3 800ae94: 3b10 subs r3, #16 800ae96: 4a27 ldr r2, [pc, #156] @ (800af34 ) 800ae98: fba2 2303 umull r2, r3, r2, r3 800ae9c: 091b lsrs r3, r3, #4 800ae9e: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; 800aea0: 68fb ldr r3, [r7, #12] 800aea2: f003 0307 and.w r3, r3, #7 800aea6: 4a24 ldr r2, [pc, #144] @ (800af38 ) 800aea8: 5cd3 ldrb r3, [r2, r3] 800aeaa: 461a mov r2, r3 800aeac: 687b ldr r3, [r7, #4] 800aeae: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 800aeb0: 68fb ldr r3, [r7, #12] 800aeb2: 2b03 cmp r3, #3 800aeb4: d908 bls.n 800aec8 { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); 800aeb6: 687b ldr r3, [r7, #4] 800aeb8: 681b ldr r3, [r3, #0] 800aeba: 461a mov r2, r3 800aebc: 4b1f ldr r3, [pc, #124] @ (800af3c ) 800aebe: 4013 ands r3, r2 800aec0: 1d1a adds r2, r3, #4 800aec2: 687b ldr r3, [r7, #4] 800aec4: 659a str r2, [r3, #88] @ 0x58 800aec6: e00d b.n 800aee4 } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); 800aec8: 687b ldr r3, [r7, #4] 800aeca: 681b ldr r3, [r3, #0] 800aecc: 461a mov r2, r3 800aece: 4b1b ldr r3, [pc, #108] @ (800af3c ) 800aed0: 4013 ands r3, r2 800aed2: 687a ldr r2, [r7, #4] 800aed4: 6593 str r3, [r2, #88] @ 0x58 800aed6: e005 b.n 800aee4 } } else /* BDMA instance(s) */ { /* return pointer to ISR and IFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); 800aed8: 687b ldr r3, [r7, #4] 800aeda: 681b ldr r3, [r3, #0] 800aedc: f023 02ff bic.w r2, r3, #255 @ 0xff 800aee0: 687b ldr r3, [r7, #4] 800aee2: 659a str r2, [r3, #88] @ 0x58 } return hdma->StreamBaseAddress; 800aee4: 687b ldr r3, [r7, #4] 800aee6: 6d9b ldr r3, [r3, #88] @ 0x58 } 800aee8: 4618 mov r0, r3 800aeea: 3714 adds r7, #20 800aeec: 46bd mov sp, r7 800aeee: f85d 7b04 ldr.w r7, [sp], #4 800aef2: 4770 bx lr 800aef4: 40020010 .word 0x40020010 800aef8: 40020028 .word 0x40020028 800aefc: 40020040 .word 0x40020040 800af00: 40020058 .word 0x40020058 800af04: 40020070 .word 0x40020070 800af08: 40020088 .word 0x40020088 800af0c: 400200a0 .word 0x400200a0 800af10: 400200b8 .word 0x400200b8 800af14: 40020410 .word 0x40020410 800af18: 40020428 .word 0x40020428 800af1c: 40020440 .word 0x40020440 800af20: 40020458 .word 0x40020458 800af24: 40020470 .word 0x40020470 800af28: 40020488 .word 0x40020488 800af2c: 400204a0 .word 0x400204a0 800af30: 400204b8 .word 0x400204b8 800af34: aaaaaaab .word 0xaaaaaaab 800af38: 0801879c .word 0x0801879c 800af3c: fffffc00 .word 0xfffffc00 0800af40 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 800af40: b480 push {r7} 800af42: b085 sub sp, #20 800af44: af00 add r7, sp, #0 800af46: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800af48: 2300 movs r3, #0 800af4a: 73fb strb r3, [r7, #15] /* Memory Data size equal to Byte */ if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 800af4c: 687b ldr r3, [r7, #4] 800af4e: 699b ldr r3, [r3, #24] 800af50: 2b00 cmp r3, #0 800af52: d120 bne.n 800af96 { switch (hdma->Init.FIFOThreshold) 800af54: 687b ldr r3, [r7, #4] 800af56: 6a9b ldr r3, [r3, #40] @ 0x28 800af58: 2b03 cmp r3, #3 800af5a: d858 bhi.n 800b00e 800af5c: a201 add r2, pc, #4 @ (adr r2, 800af64 ) 800af5e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800af62: bf00 nop 800af64: 0800af75 .word 0x0800af75 800af68: 0800af87 .word 0x0800af87 800af6c: 0800af75 .word 0x0800af75 800af70: 0800b00f .word 0x0800b00f { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800af74: 687b ldr r3, [r7, #4] 800af76: 6adb ldr r3, [r3, #44] @ 0x2c 800af78: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800af7c: 2b00 cmp r3, #0 800af7e: d048 beq.n 800b012 { status = HAL_ERROR; 800af80: 2301 movs r3, #1 800af82: 73fb strb r3, [r7, #15] } break; 800af84: e045 b.n 800b012 case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 800af86: 687b ldr r3, [r7, #4] 800af88: 6adb ldr r3, [r3, #44] @ 0x2c 800af8a: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800af8e: d142 bne.n 800b016 { status = HAL_ERROR; 800af90: 2301 movs r3, #1 800af92: 73fb strb r3, [r7, #15] } break; 800af94: e03f b.n 800b016 break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 800af96: 687b ldr r3, [r7, #4] 800af98: 699b ldr r3, [r3, #24] 800af9a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800af9e: d123 bne.n 800afe8 { switch (hdma->Init.FIFOThreshold) 800afa0: 687b ldr r3, [r7, #4] 800afa2: 6a9b ldr r3, [r3, #40] @ 0x28 800afa4: 2b03 cmp r3, #3 800afa6: d838 bhi.n 800b01a 800afa8: a201 add r2, pc, #4 @ (adr r2, 800afb0 ) 800afaa: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800afae: bf00 nop 800afb0: 0800afc1 .word 0x0800afc1 800afb4: 0800afc7 .word 0x0800afc7 800afb8: 0800afc1 .word 0x0800afc1 800afbc: 0800afd9 .word 0x0800afd9 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 800afc0: 2301 movs r3, #1 800afc2: 73fb strb r3, [r7, #15] break; 800afc4: e030 b.n 800b028 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800afc6: 687b ldr r3, [r7, #4] 800afc8: 6adb ldr r3, [r3, #44] @ 0x2c 800afca: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800afce: 2b00 cmp r3, #0 800afd0: d025 beq.n 800b01e { status = HAL_ERROR; 800afd2: 2301 movs r3, #1 800afd4: 73fb strb r3, [r7, #15] } break; 800afd6: e022 b.n 800b01e case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 800afd8: 687b ldr r3, [r7, #4] 800afda: 6adb ldr r3, [r3, #44] @ 0x2c 800afdc: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800afe0: d11f bne.n 800b022 { status = HAL_ERROR; 800afe2: 2301 movs r3, #1 800afe4: 73fb strb r3, [r7, #15] } break; 800afe6: e01c b.n 800b022 } /* Memory Data size equal to Word */ else { switch (hdma->Init.FIFOThreshold) 800afe8: 687b ldr r3, [r7, #4] 800afea: 6a9b ldr r3, [r3, #40] @ 0x28 800afec: 2b02 cmp r3, #2 800afee: d902 bls.n 800aff6 800aff0: 2b03 cmp r3, #3 800aff2: d003 beq.n 800affc status = HAL_ERROR; } break; default: break; 800aff4: e018 b.n 800b028 status = HAL_ERROR; 800aff6: 2301 movs r3, #1 800aff8: 73fb strb r3, [r7, #15] break; 800affa: e015 b.n 800b028 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800affc: 687b ldr r3, [r7, #4] 800affe: 6adb ldr r3, [r3, #44] @ 0x2c 800b000: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800b004: 2b00 cmp r3, #0 800b006: d00e beq.n 800b026 status = HAL_ERROR; 800b008: 2301 movs r3, #1 800b00a: 73fb strb r3, [r7, #15] break; 800b00c: e00b b.n 800b026 break; 800b00e: bf00 nop 800b010: e00a b.n 800b028 break; 800b012: bf00 nop 800b014: e008 b.n 800b028 break; 800b016: bf00 nop 800b018: e006 b.n 800b028 break; 800b01a: bf00 nop 800b01c: e004 b.n 800b028 break; 800b01e: bf00 nop 800b020: e002 b.n 800b028 break; 800b022: bf00 nop 800b024: e000 b.n 800b028 break; 800b026: bf00 nop } } return status; 800b028: 7bfb ldrb r3, [r7, #15] } 800b02a: 4618 mov r0, r3 800b02c: 3714 adds r7, #20 800b02e: 46bd mov sp, r7 800b030: f85d 7b04 ldr.w r7, [sp], #4 800b034: 4770 bx lr 800b036: bf00 nop 0800b038 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 800b038: b480 push {r7} 800b03a: b085 sub sp, #20 800b03c: af00 add r7, sp, #0 800b03e: 6078 str r0, [r7, #4] uint32_t stream_number; uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); 800b040: 687b ldr r3, [r7, #4] 800b042: 681b ldr r3, [r3, #0] 800b044: 60bb str r3, [r7, #8] if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 800b046: 687b ldr r3, [r7, #4] 800b048: 681b ldr r3, [r3, #0] 800b04a: 4a38 ldr r2, [pc, #224] @ (800b12c ) 800b04c: 4293 cmp r3, r2 800b04e: d022 beq.n 800b096 800b050: 687b ldr r3, [r7, #4] 800b052: 681b ldr r3, [r3, #0] 800b054: 4a36 ldr r2, [pc, #216] @ (800b130 ) 800b056: 4293 cmp r3, r2 800b058: d01d beq.n 800b096 800b05a: 687b ldr r3, [r7, #4] 800b05c: 681b ldr r3, [r3, #0] 800b05e: 4a35 ldr r2, [pc, #212] @ (800b134 ) 800b060: 4293 cmp r3, r2 800b062: d018 beq.n 800b096 800b064: 687b ldr r3, [r7, #4] 800b066: 681b ldr r3, [r3, #0] 800b068: 4a33 ldr r2, [pc, #204] @ (800b138 ) 800b06a: 4293 cmp r3, r2 800b06c: d013 beq.n 800b096 800b06e: 687b ldr r3, [r7, #4] 800b070: 681b ldr r3, [r3, #0] 800b072: 4a32 ldr r2, [pc, #200] @ (800b13c ) 800b074: 4293 cmp r3, r2 800b076: d00e beq.n 800b096 800b078: 687b ldr r3, [r7, #4] 800b07a: 681b ldr r3, [r3, #0] 800b07c: 4a30 ldr r2, [pc, #192] @ (800b140 ) 800b07e: 4293 cmp r3, r2 800b080: d009 beq.n 800b096 800b082: 687b ldr r3, [r7, #4] 800b084: 681b ldr r3, [r3, #0] 800b086: 4a2f ldr r2, [pc, #188] @ (800b144 ) 800b088: 4293 cmp r3, r2 800b08a: d004 beq.n 800b096 800b08c: 687b ldr r3, [r7, #4] 800b08e: 681b ldr r3, [r3, #0] 800b090: 4a2d ldr r2, [pc, #180] @ (800b148 ) 800b092: 4293 cmp r3, r2 800b094: d101 bne.n 800b09a 800b096: 2301 movs r3, #1 800b098: e000 b.n 800b09c 800b09a: 2300 movs r3, #0 800b09c: 2b00 cmp r3, #0 800b09e: d01a beq.n 800b0d6 { /* BDMA Channels are connected to DMAMUX2 channels */ stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; 800b0a0: 687b ldr r3, [r7, #4] 800b0a2: 681b ldr r3, [r3, #0] 800b0a4: b2db uxtb r3, r3 800b0a6: 3b08 subs r3, #8 800b0a8: 4a28 ldr r2, [pc, #160] @ (800b14c ) 800b0aa: fba2 2303 umull r2, r3, r2, r3 800b0ae: 091b lsrs r3, r3, #4 800b0b0: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); 800b0b2: 68fa ldr r2, [r7, #12] 800b0b4: 4b26 ldr r3, [pc, #152] @ (800b150 ) 800b0b6: 4413 add r3, r2 800b0b8: 009b lsls r3, r3, #2 800b0ba: 461a mov r2, r3 800b0bc: 687b ldr r3, [r7, #4] 800b0be: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; 800b0c0: 687b ldr r3, [r7, #4] 800b0c2: 4a24 ldr r2, [pc, #144] @ (800b154 ) 800b0c4: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800b0c6: 68fb ldr r3, [r7, #12] 800b0c8: f003 031f and.w r3, r3, #31 800b0cc: 2201 movs r2, #1 800b0ce: 409a lsls r2, r3 800b0d0: 687b ldr r3, [r7, #4] 800b0d2: 669a str r2, [r3, #104] @ 0x68 } hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); } } 800b0d4: e024 b.n 800b120 stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800b0d6: 687b ldr r3, [r7, #4] 800b0d8: 681b ldr r3, [r3, #0] 800b0da: b2db uxtb r3, r3 800b0dc: 3b10 subs r3, #16 800b0de: 4a1e ldr r2, [pc, #120] @ (800b158 ) 800b0e0: fba2 2303 umull r2, r3, r2, r3 800b0e4: 091b lsrs r3, r3, #4 800b0e6: 60fb str r3, [r7, #12] if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ 800b0e8: 68bb ldr r3, [r7, #8] 800b0ea: 4a1c ldr r2, [pc, #112] @ (800b15c ) 800b0ec: 4293 cmp r3, r2 800b0ee: d806 bhi.n 800b0fe 800b0f0: 68bb ldr r3, [r7, #8] 800b0f2: 4a1b ldr r2, [pc, #108] @ (800b160 ) 800b0f4: 4293 cmp r3, r2 800b0f6: d902 bls.n 800b0fe stream_number += 8U; 800b0f8: 68fb ldr r3, [r7, #12] 800b0fa: 3308 adds r3, #8 800b0fc: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); 800b0fe: 68fa ldr r2, [r7, #12] 800b100: 4b18 ldr r3, [pc, #96] @ (800b164 ) 800b102: 4413 add r3, r2 800b104: 009b lsls r3, r3, #2 800b106: 461a mov r2, r3 800b108: 687b ldr r3, [r7, #4] 800b10a: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 800b10c: 687b ldr r3, [r7, #4] 800b10e: 4a16 ldr r2, [pc, #88] @ (800b168 ) 800b110: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800b112: 68fb ldr r3, [r7, #12] 800b114: f003 031f and.w r3, r3, #31 800b118: 2201 movs r2, #1 800b11a: 409a lsls r2, r3 800b11c: 687b ldr r3, [r7, #4] 800b11e: 669a str r2, [r3, #104] @ 0x68 } 800b120: bf00 nop 800b122: 3714 adds r7, #20 800b124: 46bd mov sp, r7 800b126: f85d 7b04 ldr.w r7, [sp], #4 800b12a: 4770 bx lr 800b12c: 58025408 .word 0x58025408 800b130: 5802541c .word 0x5802541c 800b134: 58025430 .word 0x58025430 800b138: 58025444 .word 0x58025444 800b13c: 58025458 .word 0x58025458 800b140: 5802546c .word 0x5802546c 800b144: 58025480 .word 0x58025480 800b148: 58025494 .word 0x58025494 800b14c: cccccccd .word 0xcccccccd 800b150: 16009600 .word 0x16009600 800b154: 58025880 .word 0x58025880 800b158: aaaaaaab .word 0xaaaaaaab 800b15c: 400204b8 .word 0x400204b8 800b160: 4002040f .word 0x4002040f 800b164: 10008200 .word 0x10008200 800b168: 40020880 .word 0x40020880 0800b16c : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 800b16c: b480 push {r7} 800b16e: b085 sub sp, #20 800b170: af00 add r7, sp, #0 800b172: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 800b174: 687b ldr r3, [r7, #4] 800b176: 685b ldr r3, [r3, #4] 800b178: b2db uxtb r3, r3 800b17a: 60fb str r3, [r7, #12] if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) 800b17c: 68fb ldr r3, [r7, #12] 800b17e: 2b00 cmp r3, #0 800b180: d04a beq.n 800b218 800b182: 68fb ldr r3, [r7, #12] 800b184: 2b08 cmp r3, #8 800b186: d847 bhi.n 800b218 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 800b188: 687b ldr r3, [r7, #4] 800b18a: 681b ldr r3, [r3, #0] 800b18c: 4a25 ldr r2, [pc, #148] @ (800b224 ) 800b18e: 4293 cmp r3, r2 800b190: d022 beq.n 800b1d8 800b192: 687b ldr r3, [r7, #4] 800b194: 681b ldr r3, [r3, #0] 800b196: 4a24 ldr r2, [pc, #144] @ (800b228 ) 800b198: 4293 cmp r3, r2 800b19a: d01d beq.n 800b1d8 800b19c: 687b ldr r3, [r7, #4] 800b19e: 681b ldr r3, [r3, #0] 800b1a0: 4a22 ldr r2, [pc, #136] @ (800b22c ) 800b1a2: 4293 cmp r3, r2 800b1a4: d018 beq.n 800b1d8 800b1a6: 687b ldr r3, [r7, #4] 800b1a8: 681b ldr r3, [r3, #0] 800b1aa: 4a21 ldr r2, [pc, #132] @ (800b230 ) 800b1ac: 4293 cmp r3, r2 800b1ae: d013 beq.n 800b1d8 800b1b0: 687b ldr r3, [r7, #4] 800b1b2: 681b ldr r3, [r3, #0] 800b1b4: 4a1f ldr r2, [pc, #124] @ (800b234 ) 800b1b6: 4293 cmp r3, r2 800b1b8: d00e beq.n 800b1d8 800b1ba: 687b ldr r3, [r7, #4] 800b1bc: 681b ldr r3, [r3, #0] 800b1be: 4a1e ldr r2, [pc, #120] @ (800b238 ) 800b1c0: 4293 cmp r3, r2 800b1c2: d009 beq.n 800b1d8 800b1c4: 687b ldr r3, [r7, #4] 800b1c6: 681b ldr r3, [r3, #0] 800b1c8: 4a1c ldr r2, [pc, #112] @ (800b23c ) 800b1ca: 4293 cmp r3, r2 800b1cc: d004 beq.n 800b1d8 800b1ce: 687b ldr r3, [r7, #4] 800b1d0: 681b ldr r3, [r3, #0] 800b1d2: 4a1b ldr r2, [pc, #108] @ (800b240 ) 800b1d4: 4293 cmp r3, r2 800b1d6: d101 bne.n 800b1dc 800b1d8: 2301 movs r3, #1 800b1da: e000 b.n 800b1de 800b1dc: 2300 movs r3, #0 800b1de: 2b00 cmp r3, #0 800b1e0: d00a beq.n 800b1f8 { /* BDMA Channels are connected to DMAMUX2 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); 800b1e2: 68fa ldr r2, [r7, #12] 800b1e4: 4b17 ldr r3, [pc, #92] @ (800b244 ) 800b1e6: 4413 add r3, r2 800b1e8: 009b lsls r3, r3, #2 800b1ea: 461a mov r2, r3 800b1ec: 687b ldr r3, [r7, #4] 800b1ee: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; 800b1f0: 687b ldr r3, [r7, #4] 800b1f2: 4a15 ldr r2, [pc, #84] @ (800b248 ) 800b1f4: 671a str r2, [r3, #112] @ 0x70 800b1f6: e009 b.n 800b20c } else { /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 800b1f8: 68fa ldr r2, [r7, #12] 800b1fa: 4b14 ldr r3, [pc, #80] @ (800b24c ) 800b1fc: 4413 add r3, r2 800b1fe: 009b lsls r3, r3, #2 800b200: 461a mov r2, r3 800b202: 687b ldr r3, [r7, #4] 800b204: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 800b206: 687b ldr r3, [r7, #4] 800b208: 4a11 ldr r2, [pc, #68] @ (800b250 ) 800b20a: 671a str r2, [r3, #112] @ 0x70 } hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); 800b20c: 68fb ldr r3, [r7, #12] 800b20e: 3b01 subs r3, #1 800b210: 2201 movs r2, #1 800b212: 409a lsls r2, r3 800b214: 687b ldr r3, [r7, #4] 800b216: 675a str r2, [r3, #116] @ 0x74 } } 800b218: bf00 nop 800b21a: 3714 adds r7, #20 800b21c: 46bd mov sp, r7 800b21e: f85d 7b04 ldr.w r7, [sp], #4 800b222: 4770 bx lr 800b224: 58025408 .word 0x58025408 800b228: 5802541c .word 0x5802541c 800b22c: 58025430 .word 0x58025430 800b230: 58025444 .word 0x58025444 800b234: 58025458 .word 0x58025458 800b238: 5802546c .word 0x5802546c 800b23c: 58025480 .word 0x58025480 800b240: 58025494 .word 0x58025494 800b244: 1600963f .word 0x1600963f 800b248: 58025940 .word 0x58025940 800b24c: 1000823f .word 0x1000823f 800b250: 40020940 .word 0x40020940 0800b254 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800b254: b480 push {r7} 800b256: b089 sub sp, #36 @ 0x24 800b258: af00 add r7, sp, #0 800b25a: 6078 str r0, [r7, #4] 800b25c: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 800b25e: 2300 movs r3, #0 800b260: 61fb str r3, [r7, #28] EXTI_Core_TypeDef *EXTI_CurrentCPU; #if defined(DUAL_CORE) && defined(CORE_CM4) EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ #else EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ 800b262: 4b89 ldr r3, [pc, #548] @ (800b488 ) 800b264: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 800b266: e194 b.n 800b592 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 800b268: 683b ldr r3, [r7, #0] 800b26a: 681a ldr r2, [r3, #0] 800b26c: 2101 movs r1, #1 800b26e: 69fb ldr r3, [r7, #28] 800b270: fa01 f303 lsl.w r3, r1, r3 800b274: 4013 ands r3, r2 800b276: 613b str r3, [r7, #16] if (iocurrent != 0x00U) 800b278: 693b ldr r3, [r7, #16] 800b27a: 2b00 cmp r3, #0 800b27c: f000 8186 beq.w 800b58c { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 800b280: 683b ldr r3, [r7, #0] 800b282: 685b ldr r3, [r3, #4] 800b284: f003 0303 and.w r3, r3, #3 800b288: 2b01 cmp r3, #1 800b28a: d005 beq.n 800b298 800b28c: 683b ldr r3, [r7, #0] 800b28e: 685b ldr r3, [r3, #4] 800b290: f003 0303 and.w r3, r3, #3 800b294: 2b02 cmp r3, #2 800b296: d130 bne.n 800b2fa { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 800b298: 687b ldr r3, [r7, #4] 800b29a: 689b ldr r3, [r3, #8] 800b29c: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 800b29e: 69fb ldr r3, [r7, #28] 800b2a0: 005b lsls r3, r3, #1 800b2a2: 2203 movs r2, #3 800b2a4: fa02 f303 lsl.w r3, r2, r3 800b2a8: 43db mvns r3, r3 800b2aa: 69ba ldr r2, [r7, #24] 800b2ac: 4013 ands r3, r2 800b2ae: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 800b2b0: 683b ldr r3, [r7, #0] 800b2b2: 68da ldr r2, [r3, #12] 800b2b4: 69fb ldr r3, [r7, #28] 800b2b6: 005b lsls r3, r3, #1 800b2b8: fa02 f303 lsl.w r3, r2, r3 800b2bc: 69ba ldr r2, [r7, #24] 800b2be: 4313 orrs r3, r2 800b2c0: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 800b2c2: 687b ldr r3, [r7, #4] 800b2c4: 69ba ldr r2, [r7, #24] 800b2c6: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 800b2c8: 687b ldr r3, [r7, #4] 800b2ca: 685b ldr r3, [r3, #4] 800b2cc: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT0 << position) ; 800b2ce: 2201 movs r2, #1 800b2d0: 69fb ldr r3, [r7, #28] 800b2d2: fa02 f303 lsl.w r3, r2, r3 800b2d6: 43db mvns r3, r3 800b2d8: 69ba ldr r2, [r7, #24] 800b2da: 4013 ands r3, r2 800b2dc: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 800b2de: 683b ldr r3, [r7, #0] 800b2e0: 685b ldr r3, [r3, #4] 800b2e2: 091b lsrs r3, r3, #4 800b2e4: f003 0201 and.w r2, r3, #1 800b2e8: 69fb ldr r3, [r7, #28] 800b2ea: fa02 f303 lsl.w r3, r2, r3 800b2ee: 69ba ldr r2, [r7, #24] 800b2f0: 4313 orrs r3, r2 800b2f2: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 800b2f4: 687b ldr r3, [r7, #4] 800b2f6: 69ba ldr r2, [r7, #24] 800b2f8: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 800b2fa: 683b ldr r3, [r7, #0] 800b2fc: 685b ldr r3, [r3, #4] 800b2fe: f003 0303 and.w r3, r3, #3 800b302: 2b03 cmp r3, #3 800b304: d017 beq.n 800b336 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 800b306: 687b ldr r3, [r7, #4] 800b308: 68db ldr r3, [r3, #12] 800b30a: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 800b30c: 69fb ldr r3, [r7, #28] 800b30e: 005b lsls r3, r3, #1 800b310: 2203 movs r2, #3 800b312: fa02 f303 lsl.w r3, r2, r3 800b316: 43db mvns r3, r3 800b318: 69ba ldr r2, [r7, #24] 800b31a: 4013 ands r3, r2 800b31c: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 800b31e: 683b ldr r3, [r7, #0] 800b320: 689a ldr r2, [r3, #8] 800b322: 69fb ldr r3, [r7, #28] 800b324: 005b lsls r3, r3, #1 800b326: fa02 f303 lsl.w r3, r2, r3 800b32a: 69ba ldr r2, [r7, #24] 800b32c: 4313 orrs r3, r2 800b32e: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 800b330: 687b ldr r3, [r7, #4] 800b332: 69ba ldr r2, [r7, #24] 800b334: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 800b336: 683b ldr r3, [r7, #0] 800b338: 685b ldr r3, [r3, #4] 800b33a: f003 0303 and.w r3, r3, #3 800b33e: 2b02 cmp r3, #2 800b340: d123 bne.n 800b38a /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 800b342: 69fb ldr r3, [r7, #28] 800b344: 08da lsrs r2, r3, #3 800b346: 687b ldr r3, [r7, #4] 800b348: 3208 adds r2, #8 800b34a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800b34e: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 800b350: 69fb ldr r3, [r7, #28] 800b352: f003 0307 and.w r3, r3, #7 800b356: 009b lsls r3, r3, #2 800b358: 220f movs r2, #15 800b35a: fa02 f303 lsl.w r3, r2, r3 800b35e: 43db mvns r3, r3 800b360: 69ba ldr r2, [r7, #24] 800b362: 4013 ands r3, r2 800b364: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 800b366: 683b ldr r3, [r7, #0] 800b368: 691a ldr r2, [r3, #16] 800b36a: 69fb ldr r3, [r7, #28] 800b36c: f003 0307 and.w r3, r3, #7 800b370: 009b lsls r3, r3, #2 800b372: fa02 f303 lsl.w r3, r2, r3 800b376: 69ba ldr r2, [r7, #24] 800b378: 4313 orrs r3, r2 800b37a: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 800b37c: 69fb ldr r3, [r7, #28] 800b37e: 08da lsrs r2, r3, #3 800b380: 687b ldr r3, [r7, #4] 800b382: 3208 adds r2, #8 800b384: 69b9 ldr r1, [r7, #24] 800b386: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 800b38a: 687b ldr r3, [r7, #4] 800b38c: 681b ldr r3, [r3, #0] 800b38e: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 800b390: 69fb ldr r3, [r7, #28] 800b392: 005b lsls r3, r3, #1 800b394: 2203 movs r2, #3 800b396: fa02 f303 lsl.w r3, r2, r3 800b39a: 43db mvns r3, r3 800b39c: 69ba ldr r2, [r7, #24] 800b39e: 4013 ands r3, r2 800b3a0: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 800b3a2: 683b ldr r3, [r7, #0] 800b3a4: 685b ldr r3, [r3, #4] 800b3a6: f003 0203 and.w r2, r3, #3 800b3aa: 69fb ldr r3, [r7, #28] 800b3ac: 005b lsls r3, r3, #1 800b3ae: fa02 f303 lsl.w r3, r2, r3 800b3b2: 69ba ldr r2, [r7, #24] 800b3b4: 4313 orrs r3, r2 800b3b6: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 800b3b8: 687b ldr r3, [r7, #4] 800b3ba: 69ba ldr r2, [r7, #24] 800b3bc: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 800b3be: 683b ldr r3, [r7, #0] 800b3c0: 685b ldr r3, [r3, #4] 800b3c2: f403 3340 and.w r3, r3, #196608 @ 0x30000 800b3c6: 2b00 cmp r3, #0 800b3c8: f000 80e0 beq.w 800b58c { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800b3cc: 4b2f ldr r3, [pc, #188] @ (800b48c ) 800b3ce: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 800b3d2: 4a2e ldr r2, [pc, #184] @ (800b48c ) 800b3d4: f043 0302 orr.w r3, r3, #2 800b3d8: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 800b3dc: 4b2b ldr r3, [pc, #172] @ (800b48c ) 800b3de: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 800b3e2: f003 0302 and.w r3, r3, #2 800b3e6: 60fb str r3, [r7, #12] 800b3e8: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 800b3ea: 4a29 ldr r2, [pc, #164] @ (800b490 ) 800b3ec: 69fb ldr r3, [r7, #28] 800b3ee: 089b lsrs r3, r3, #2 800b3f0: 3302 adds r3, #2 800b3f2: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800b3f6: 61bb str r3, [r7, #24] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 800b3f8: 69fb ldr r3, [r7, #28] 800b3fa: f003 0303 and.w r3, r3, #3 800b3fe: 009b lsls r3, r3, #2 800b400: 220f movs r2, #15 800b402: fa02 f303 lsl.w r3, r2, r3 800b406: 43db mvns r3, r3 800b408: 69ba ldr r2, [r7, #24] 800b40a: 4013 ands r3, r2 800b40c: 61bb str r3, [r7, #24] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 800b40e: 687b ldr r3, [r7, #4] 800b410: 4a20 ldr r2, [pc, #128] @ (800b494 ) 800b412: 4293 cmp r3, r2 800b414: d052 beq.n 800b4bc 800b416: 687b ldr r3, [r7, #4] 800b418: 4a1f ldr r2, [pc, #124] @ (800b498 ) 800b41a: 4293 cmp r3, r2 800b41c: d031 beq.n 800b482 800b41e: 687b ldr r3, [r7, #4] 800b420: 4a1e ldr r2, [pc, #120] @ (800b49c ) 800b422: 4293 cmp r3, r2 800b424: d02b beq.n 800b47e 800b426: 687b ldr r3, [r7, #4] 800b428: 4a1d ldr r2, [pc, #116] @ (800b4a0 ) 800b42a: 4293 cmp r3, r2 800b42c: d025 beq.n 800b47a 800b42e: 687b ldr r3, [r7, #4] 800b430: 4a1c ldr r2, [pc, #112] @ (800b4a4 ) 800b432: 4293 cmp r3, r2 800b434: d01f beq.n 800b476 800b436: 687b ldr r3, [r7, #4] 800b438: 4a1b ldr r2, [pc, #108] @ (800b4a8 ) 800b43a: 4293 cmp r3, r2 800b43c: d019 beq.n 800b472 800b43e: 687b ldr r3, [r7, #4] 800b440: 4a1a ldr r2, [pc, #104] @ (800b4ac ) 800b442: 4293 cmp r3, r2 800b444: d013 beq.n 800b46e 800b446: 687b ldr r3, [r7, #4] 800b448: 4a19 ldr r2, [pc, #100] @ (800b4b0 ) 800b44a: 4293 cmp r3, r2 800b44c: d00d beq.n 800b46a 800b44e: 687b ldr r3, [r7, #4] 800b450: 4a18 ldr r2, [pc, #96] @ (800b4b4 ) 800b452: 4293 cmp r3, r2 800b454: d007 beq.n 800b466 800b456: 687b ldr r3, [r7, #4] 800b458: 4a17 ldr r2, [pc, #92] @ (800b4b8 ) 800b45a: 4293 cmp r3, r2 800b45c: d101 bne.n 800b462 800b45e: 2309 movs r3, #9 800b460: e02d b.n 800b4be 800b462: 230a movs r3, #10 800b464: e02b b.n 800b4be 800b466: 2308 movs r3, #8 800b468: e029 b.n 800b4be 800b46a: 2307 movs r3, #7 800b46c: e027 b.n 800b4be 800b46e: 2306 movs r3, #6 800b470: e025 b.n 800b4be 800b472: 2305 movs r3, #5 800b474: e023 b.n 800b4be 800b476: 2304 movs r3, #4 800b478: e021 b.n 800b4be 800b47a: 2303 movs r3, #3 800b47c: e01f b.n 800b4be 800b47e: 2302 movs r3, #2 800b480: e01d b.n 800b4be 800b482: 2301 movs r3, #1 800b484: e01b b.n 800b4be 800b486: bf00 nop 800b488: 58000080 .word 0x58000080 800b48c: 58024400 .word 0x58024400 800b490: 58000400 .word 0x58000400 800b494: 58020000 .word 0x58020000 800b498: 58020400 .word 0x58020400 800b49c: 58020800 .word 0x58020800 800b4a0: 58020c00 .word 0x58020c00 800b4a4: 58021000 .word 0x58021000 800b4a8: 58021400 .word 0x58021400 800b4ac: 58021800 .word 0x58021800 800b4b0: 58021c00 .word 0x58021c00 800b4b4: 58022000 .word 0x58022000 800b4b8: 58022400 .word 0x58022400 800b4bc: 2300 movs r3, #0 800b4be: 69fa ldr r2, [r7, #28] 800b4c0: f002 0203 and.w r2, r2, #3 800b4c4: 0092 lsls r2, r2, #2 800b4c6: 4093 lsls r3, r2 800b4c8: 69ba ldr r2, [r7, #24] 800b4ca: 4313 orrs r3, r2 800b4cc: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 800b4ce: 4938 ldr r1, [pc, #224] @ (800b5b0 ) 800b4d0: 69fb ldr r3, [r7, #28] 800b4d2: 089b lsrs r3, r3, #2 800b4d4: 3302 adds r3, #2 800b4d6: 69ba ldr r2, [r7, #24] 800b4d8: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 800b4dc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b4e0: 681b ldr r3, [r3, #0] 800b4e2: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b4e4: 693b ldr r3, [r7, #16] 800b4e6: 43db mvns r3, r3 800b4e8: 69ba ldr r2, [r7, #24] 800b4ea: 4013 ands r3, r2 800b4ec: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 800b4ee: 683b ldr r3, [r7, #0] 800b4f0: 685b ldr r3, [r3, #4] 800b4f2: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800b4f6: 2b00 cmp r3, #0 800b4f8: d003 beq.n 800b502 { temp |= iocurrent; 800b4fa: 69ba ldr r2, [r7, #24] 800b4fc: 693b ldr r3, [r7, #16] 800b4fe: 4313 orrs r3, r2 800b500: 61bb str r3, [r7, #24] } EXTI->RTSR1 = temp; 800b502: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b506: 69bb ldr r3, [r7, #24] 800b508: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 800b50a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b50e: 685b ldr r3, [r3, #4] 800b510: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b512: 693b ldr r3, [r7, #16] 800b514: 43db mvns r3, r3 800b516: 69ba ldr r2, [r7, #24] 800b518: 4013 ands r3, r2 800b51a: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 800b51c: 683b ldr r3, [r7, #0] 800b51e: 685b ldr r3, [r3, #4] 800b520: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800b524: 2b00 cmp r3, #0 800b526: d003 beq.n 800b530 { temp |= iocurrent; 800b528: 69ba ldr r2, [r7, #24] 800b52a: 693b ldr r3, [r7, #16] 800b52c: 4313 orrs r3, r2 800b52e: 61bb str r3, [r7, #24] } EXTI->FTSR1 = temp; 800b530: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b534: 69bb ldr r3, [r7, #24] 800b536: 6053 str r3, [r2, #4] temp = EXTI_CurrentCPU->EMR1; 800b538: 697b ldr r3, [r7, #20] 800b53a: 685b ldr r3, [r3, #4] 800b53c: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b53e: 693b ldr r3, [r7, #16] 800b540: 43db mvns r3, r3 800b542: 69ba ldr r2, [r7, #24] 800b544: 4013 ands r3, r2 800b546: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 800b548: 683b ldr r3, [r7, #0] 800b54a: 685b ldr r3, [r3, #4] 800b54c: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b550: 2b00 cmp r3, #0 800b552: d003 beq.n 800b55c { temp |= iocurrent; 800b554: 69ba ldr r2, [r7, #24] 800b556: 693b ldr r3, [r7, #16] 800b558: 4313 orrs r3, r2 800b55a: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->EMR1 = temp; 800b55c: 697b ldr r3, [r7, #20] 800b55e: 69ba ldr r2, [r7, #24] 800b560: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 800b562: 697b ldr r3, [r7, #20] 800b564: 681b ldr r3, [r3, #0] 800b566: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b568: 693b ldr r3, [r7, #16] 800b56a: 43db mvns r3, r3 800b56c: 69ba ldr r2, [r7, #24] 800b56e: 4013 ands r3, r2 800b570: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 800b572: 683b ldr r3, [r7, #0] 800b574: 685b ldr r3, [r3, #4] 800b576: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b57a: 2b00 cmp r3, #0 800b57c: d003 beq.n 800b586 { temp |= iocurrent; 800b57e: 69ba ldr r2, [r7, #24] 800b580: 693b ldr r3, [r7, #16] 800b582: 4313 orrs r3, r2 800b584: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->IMR1 = temp; 800b586: 697b ldr r3, [r7, #20] 800b588: 69ba ldr r2, [r7, #24] 800b58a: 601a str r2, [r3, #0] } } position++; 800b58c: 69fb ldr r3, [r7, #28] 800b58e: 3301 adds r3, #1 800b590: 61fb str r3, [r7, #28] while (((GPIO_Init->Pin) >> position) != 0x00U) 800b592: 683b ldr r3, [r7, #0] 800b594: 681a ldr r2, [r3, #0] 800b596: 69fb ldr r3, [r7, #28] 800b598: fa22 f303 lsr.w r3, r2, r3 800b59c: 2b00 cmp r3, #0 800b59e: f47f ae63 bne.w 800b268 } } 800b5a2: bf00 nop 800b5a4: bf00 nop 800b5a6: 3724 adds r7, #36 @ 0x24 800b5a8: 46bd mov sp, r7 800b5aa: f85d 7b04 ldr.w r7, [sp], #4 800b5ae: 4770 bx lr 800b5b0: 58000400 .word 0x58000400 0800b5b4 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800b5b4: b480 push {r7} 800b5b6: b085 sub sp, #20 800b5b8: af00 add r7, sp, #0 800b5ba: 6078 str r0, [r7, #4] 800b5bc: 460b mov r3, r1 800b5be: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0x00U) 800b5c0: 687b ldr r3, [r7, #4] 800b5c2: 691a ldr r2, [r3, #16] 800b5c4: 887b ldrh r3, [r7, #2] 800b5c6: 4013 ands r3, r2 800b5c8: 2b00 cmp r3, #0 800b5ca: d002 beq.n 800b5d2 { bitstatus = GPIO_PIN_SET; 800b5cc: 2301 movs r3, #1 800b5ce: 73fb strb r3, [r7, #15] 800b5d0: e001 b.n 800b5d6 } else { bitstatus = GPIO_PIN_RESET; 800b5d2: 2300 movs r3, #0 800b5d4: 73fb strb r3, [r7, #15] } return bitstatus; 800b5d6: 7bfb ldrb r3, [r7, #15] } 800b5d8: 4618 mov r0, r3 800b5da: 3714 adds r7, #20 800b5dc: 46bd mov sp, r7 800b5de: f85d 7b04 ldr.w r7, [sp], #4 800b5e2: 4770 bx lr 0800b5e4 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800b5e4: b480 push {r7} 800b5e6: b083 sub sp, #12 800b5e8: af00 add r7, sp, #0 800b5ea: 6078 str r0, [r7, #4] 800b5ec: 460b mov r3, r1 800b5ee: 807b strh r3, [r7, #2] 800b5f0: 4613 mov r3, r2 800b5f2: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800b5f4: 787b ldrb r3, [r7, #1] 800b5f6: 2b00 cmp r3, #0 800b5f8: d003 beq.n 800b602 { GPIOx->BSRR = GPIO_Pin; 800b5fa: 887a ldrh r2, [r7, #2] 800b5fc: 687b ldr r3, [r7, #4] 800b5fe: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; } } 800b600: e003 b.n 800b60a GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 800b602: 887b ldrh r3, [r7, #2] 800b604: 041a lsls r2, r3, #16 800b606: 687b ldr r3, [r7, #4] 800b608: 619a str r2, [r3, #24] } 800b60a: bf00 nop 800b60c: 370c adds r7, #12 800b60e: 46bd mov sp, r7 800b610: f85d 7b04 ldr.w r7, [sp], #4 800b614: 4770 bx lr 0800b616 : * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral. * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800b616: b480 push {r7} 800b618: b085 sub sp, #20 800b61a: af00 add r7, sp, #0 800b61c: 6078 str r0, [r7, #4] 800b61e: 460b mov r3, r1 800b620: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; 800b622: 687b ldr r3, [r7, #4] 800b624: 695b ldr r3, [r3, #20] 800b626: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 800b628: 887a ldrh r2, [r7, #2] 800b62a: 68fb ldr r3, [r7, #12] 800b62c: 4013 ands r3, r2 800b62e: 041a lsls r2, r3, #16 800b630: 68fb ldr r3, [r7, #12] 800b632: 43d9 mvns r1, r3 800b634: 887b ldrh r3, [r7, #2] 800b636: 400b ands r3, r1 800b638: 431a orrs r2, r3 800b63a: 687b ldr r3, [r7, #4] 800b63c: 619a str r2, [r3, #24] } 800b63e: bf00 nop 800b640: 3714 adds r7, #20 800b642: 46bd mov sp, r7 800b644: f85d 7b04 ldr.w r7, [sp], #4 800b648: 4770 bx lr 0800b64a : * @brief Handle EXTI interrupt request. * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 800b64a: b580 push {r7, lr} 800b64c: b082 sub sp, #8 800b64e: af00 add r7, sp, #0 800b650: 4603 mov r3, r0 800b652: 80fb strh r3, [r7, #6] __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); } #else /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U) 800b654: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b658: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 800b65c: 88fb ldrh r3, [r7, #6] 800b65e: 4013 ands r3, r2 800b660: 2b00 cmp r3, #0 800b662: d008 beq.n 800b676 { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 800b664: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b668: 88fb ldrh r3, [r7, #6] 800b66a: f8c2 3088 str.w r3, [r2, #136] @ 0x88 HAL_GPIO_EXTI_Callback(GPIO_Pin); 800b66e: 88fb ldrh r3, [r7, #6] 800b670: 4618 mov r0, r3 800b672: f7f4 ffcf bl 8000614 } #endif } 800b676: bf00 nop 800b678: 3708 adds r7, #8 800b67a: 46bd mov sp, r7 800b67c: bd80 pop {r7, pc} 0800b67e : * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { 800b67e: b580 push {r7, lr} 800b680: b084 sub sp, #16 800b682: af00 add r7, sp, #0 800b684: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the IWDG handle allocation */ if (hiwdg == NULL) 800b686: 687b ldr r3, [r7, #4] 800b688: 2b00 cmp r3, #0 800b68a: d101 bne.n 800b690 { return HAL_ERROR; 800b68c: 2301 movs r3, #1 800b68e: e041 b.n 800b714 assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); /* Enable IWDG. LSI is turned on automatically */ __HAL_IWDG_START(hiwdg); 800b690: 687b ldr r3, [r7, #4] 800b692: 681b ldr r3, [r3, #0] 800b694: f64c 42cc movw r2, #52428 @ 0xcccc 800b698: 601a str r2, [r3, #0] /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing 0x5555 in KR */ IWDG_ENABLE_WRITE_ACCESS(hiwdg); 800b69a: 687b ldr r3, [r7, #4] 800b69c: 681b ldr r3, [r3, #0] 800b69e: f245 5255 movw r2, #21845 @ 0x5555 800b6a2: 601a str r2, [r3, #0] /* Write to IWDG registers the Prescaler & Reload values to work with */ hiwdg->Instance->PR = hiwdg->Init.Prescaler; 800b6a4: 687b ldr r3, [r7, #4] 800b6a6: 681b ldr r3, [r3, #0] 800b6a8: 687a ldr r2, [r7, #4] 800b6aa: 6852 ldr r2, [r2, #4] 800b6ac: 605a str r2, [r3, #4] hiwdg->Instance->RLR = hiwdg->Init.Reload; 800b6ae: 687b ldr r3, [r7, #4] 800b6b0: 681b ldr r3, [r3, #0] 800b6b2: 687a ldr r2, [r7, #4] 800b6b4: 6892 ldr r2, [r2, #8] 800b6b6: 609a str r2, [r3, #8] /* Check pending flag, if previous update not done, return timeout */ tickstart = HAL_GetTick(); 800b6b8: f7fa fbf4 bl 8005ea4 800b6bc: 60f8 str r0, [r7, #12] /* Wait for register to be updated */ while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 800b6be: e00f b.n 800b6e0 { if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) 800b6c0: f7fa fbf0 bl 8005ea4 800b6c4: 4602 mov r2, r0 800b6c6: 68fb ldr r3, [r7, #12] 800b6c8: 1ad3 subs r3, r2, r3 800b6ca: 2b31 cmp r3, #49 @ 0x31 800b6cc: d908 bls.n 800b6e0 { if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 800b6ce: 687b ldr r3, [r7, #4] 800b6d0: 681b ldr r3, [r3, #0] 800b6d2: 68db ldr r3, [r3, #12] 800b6d4: f003 0307 and.w r3, r3, #7 800b6d8: 2b00 cmp r3, #0 800b6da: d001 beq.n 800b6e0 { return HAL_TIMEOUT; 800b6dc: 2303 movs r3, #3 800b6de: e019 b.n 800b714 while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 800b6e0: 687b ldr r3, [r7, #4] 800b6e2: 681b ldr r3, [r3, #0] 800b6e4: 68db ldr r3, [r3, #12] 800b6e6: f003 0307 and.w r3, r3, #7 800b6ea: 2b00 cmp r3, #0 800b6ec: d1e8 bne.n 800b6c0 } } /* If window parameter is different than current value, modify window register */ if (hiwdg->Instance->WINR != hiwdg->Init.Window) 800b6ee: 687b ldr r3, [r7, #4] 800b6f0: 681b ldr r3, [r3, #0] 800b6f2: 691a ldr r2, [r3, #16] 800b6f4: 687b ldr r3, [r7, #4] 800b6f6: 68db ldr r3, [r3, #12] 800b6f8: 429a cmp r2, r3 800b6fa: d005 beq.n 800b708 { /* Write to IWDG WINR the IWDG_Window value to compare with. In any case, even if window feature is disabled, Watchdog will be reloaded by writing windows register */ hiwdg->Instance->WINR = hiwdg->Init.Window; 800b6fc: 687b ldr r3, [r7, #4] 800b6fe: 681b ldr r3, [r3, #0] 800b700: 687a ldr r2, [r7, #4] 800b702: 68d2 ldr r2, [r2, #12] 800b704: 611a str r2, [r3, #16] 800b706: e004 b.n 800b712 } else { /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); 800b708: 687b ldr r3, [r7, #4] 800b70a: 681b ldr r3, [r3, #0] 800b70c: f64a 22aa movw r2, #43690 @ 0xaaaa 800b710: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 800b712: 2300 movs r3, #0 } 800b714: 4618 mov r0, r3 800b716: 3710 adds r7, #16 800b718: 46bd mov sp, r7 800b71a: bd80 pop {r7, pc} 0800b71c : * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) { 800b71c: b480 push {r7} 800b71e: b083 sub sp, #12 800b720: af00 add r7, sp, #0 800b722: 6078 str r0, [r7, #4] /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); 800b724: 687b ldr r3, [r7, #4] 800b726: 681b ldr r3, [r3, #0] 800b728: f64a 22aa movw r2, #43690 @ 0xaaaa 800b72c: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800b72e: 2300 movs r3, #0 } 800b730: 4618 mov r0, r3 800b732: 370c adds r7, #12 800b734: 46bd mov sp, r7 800b736: f85d 7b04 ldr.w r7, [sp], #4 800b73a: 4770 bx lr 0800b73c : * driver. All combination are allowed: wake up only Cortex-M7, wake up * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4. * @retval None. */ void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD) { 800b73c: b480 push {r7} 800b73e: b083 sub sp, #12 800b740: af00 add r7, sp, #0 800b742: 6078 str r0, [r7, #4] /* Check the PVD configuration parameter */ if (sConfigPVD == NULL) 800b744: 687b ldr r3, [r7, #4] 800b746: 2b00 cmp r3, #0 800b748: d069 beq.n 800b81e /* Check the parameters */ assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel)); assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode)); /* Set PLS[7:5] bits according to PVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); 800b74a: 4b38 ldr r3, [pc, #224] @ (800b82c ) 800b74c: 681b ldr r3, [r3, #0] 800b74e: f023 02e0 bic.w r2, r3, #224 @ 0xe0 800b752: 687b ldr r3, [r7, #4] 800b754: 681b ldr r3, [r3, #0] 800b756: 4935 ldr r1, [pc, #212] @ (800b82c ) 800b758: 4313 orrs r3, r2 800b75a: 600b str r3, [r1, #0] /* Clear previous config */ #if !defined (DUAL_CORE) __HAL_PWR_PVD_EXTI_DISABLE_EVENT (); 800b75c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b760: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b764: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b768: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b76c: f8c2 3084 str.w r3, [r2, #132] @ 0x84 __HAL_PWR_PVD_EXTI_DISABLE_IT (); 800b770: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b774: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b778: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b77c: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b780: f8c2 3080 str.w r3, [r2, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE (); 800b784: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b788: 681b ldr r3, [r3, #0] 800b78a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b78e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b792: 6013 str r3, [r2, #0] __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE (); 800b794: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b798: 685b ldr r3, [r3, #4] 800b79a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b79e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b7a2: 6053 str r3, [r2, #4] #if !defined (DUAL_CORE) /* Interrupt mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 800b7a4: 687b ldr r3, [r7, #4] 800b7a6: 685b ldr r3, [r3, #4] 800b7a8: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b7ac: 2b00 cmp r3, #0 800b7ae: d009 beq.n 800b7c4 { __HAL_PWR_PVD_EXTI_ENABLE_IT (); 800b7b0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b7b4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b7b8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b7bc: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b7c0: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } /* Event mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 800b7c4: 687b ldr r3, [r7, #4] 800b7c6: 685b ldr r3, [r3, #4] 800b7c8: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b7cc: 2b00 cmp r3, #0 800b7ce: d009 beq.n 800b7e4 { __HAL_PWR_PVD_EXTI_ENABLE_EVENT (); 800b7d0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b7d4: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b7d8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b7dc: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b7e0: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 800b7e4: 687b ldr r3, [r7, #4] 800b7e6: 685b ldr r3, [r3, #4] 800b7e8: f003 0301 and.w r3, r3, #1 800b7ec: 2b00 cmp r3, #0 800b7ee: d007 beq.n 800b800 { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE (); 800b7f0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b7f4: 681b ldr r3, [r3, #0] 800b7f6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b7fa: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b7fe: 6013 str r3, [r2, #0] } /* Falling edge configuration */ if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 800b800: 687b ldr r3, [r7, #4] 800b802: 685b ldr r3, [r3, #4] 800b804: f003 0302 and.w r3, r3, #2 800b808: 2b00 cmp r3, #0 800b80a: d009 beq.n 800b820 { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE (); 800b80c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b810: 685b ldr r3, [r3, #4] 800b812: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b816: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b81a: 6053 str r3, [r2, #4] 800b81c: e000 b.n 800b820 return; 800b81e: bf00 nop } } 800b820: 370c adds r7, #12 800b822: 46bd mov sp, r7 800b824: f85d 7b04 ldr.w r7, [sp], #4 800b828: 4770 bx lr 800b82a: bf00 nop 800b82c: 58024800 .word 0x58024800 0800b830 : /** * @brief Enable the Programmable Voltage Detector (PVD). * @retval None. */ void HAL_PWR_EnablePVD (void) { 800b830: b480 push {r7} 800b832: af00 add r7, sp, #0 /* Enable the power voltage detector */ SET_BIT (PWR->CR1, PWR_CR1_PVDEN); 800b834: 4b05 ldr r3, [pc, #20] @ (800b84c ) 800b836: 681b ldr r3, [r3, #0] 800b838: 4a04 ldr r2, [pc, #16] @ (800b84c ) 800b83a: f043 0310 orr.w r3, r3, #16 800b83e: 6013 str r3, [r2, #0] } 800b840: bf00 nop 800b842: 46bd mov sp, r7 800b844: f85d 7b04 ldr.w r7, [sp], #4 800b848: 4770 bx lr 800b84a: bf00 nop 800b84c: 58024800 .word 0x58024800 0800b850 : * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { 800b850: b580 push {r7, lr} 800b852: b084 sub sp, #16 800b854: af00 add r7, sp, #0 800b856: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_SUPPLY (SupplySource)); /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) 800b858: 4b19 ldr r3, [pc, #100] @ (800b8c0 ) 800b85a: 68db ldr r3, [r3, #12] 800b85c: f003 0304 and.w r3, r3, #4 800b860: 2b04 cmp r3, #4 800b862: d00a beq.n 800b87a #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 800b864: 4b16 ldr r3, [pc, #88] @ (800b8c0 ) 800b866: 68db ldr r3, [r3, #12] 800b868: f003 0307 and.w r3, r3, #7 800b86c: 687a ldr r2, [r7, #4] 800b86e: 429a cmp r2, r3 800b870: d001 beq.n 800b876 { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 800b872: 2301 movs r3, #1 800b874: e01f b.n 800b8b6 else { /* Supply configuration update locked, but new supply configuration matches with old supply configuration : nothing to do */ return HAL_OK; 800b876: 2300 movs r3, #0 800b878: e01d b.n 800b8b6 } } /* Set the power supply configuration */ MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 800b87a: 4b11 ldr r3, [pc, #68] @ (800b8c0 ) 800b87c: 68db ldr r3, [r3, #12] 800b87e: f023 0207 bic.w r2, r3, #7 800b882: 490f ldr r1, [pc, #60] @ (800b8c0 ) 800b884: 687b ldr r3, [r7, #4] 800b886: 4313 orrs r3, r2 800b888: 60cb str r3, [r1, #12] /* Get tick */ tickstart = HAL_GetTick (); 800b88a: f7fa fb0b bl 8005ea4 800b88e: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800b890: e009 b.n 800b8a6 { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 800b892: f7fa fb07 bl 8005ea4 800b896: 4602 mov r2, r0 800b898: 68fb ldr r3, [r7, #12] 800b89a: 1ad3 subs r3, r2, r3 800b89c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b8a0: d901 bls.n 800b8a6 { return HAL_ERROR; 800b8a2: 2301 movs r3, #1 800b8a4: e007 b.n 800b8b6 while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800b8a6: 4b06 ldr r3, [pc, #24] @ (800b8c0 ) 800b8a8: 685b ldr r3, [r3, #4] 800b8aa: f403 5300 and.w r3, r3, #8192 @ 0x2000 800b8ae: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800b8b2: d1ee bne.n 800b892 } } } #endif /* defined (SMPS) */ return HAL_OK; 800b8b4: 2300 movs r3, #0 } 800b8b6: 4618 mov r0, r3 800b8b8: 3710 adds r7, #16 800b8ba: 46bd mov sp, r7 800b8bc: bd80 pop {r7, pc} 800b8be: bf00 nop 800b8c0: 58024800 .word 0x58024800 0800b8c4 : * driver. All combination are allowed: wake up only Cortex-M7, wake up * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4. * @retval None. */ void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD) { 800b8c4: b480 push {r7} 800b8c6: b083 sub sp, #12 800b8c8: af00 add r7, sp, #0 800b8ca: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode)); /* Set the ALS[18:17] bits according to AVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); 800b8cc: 4b37 ldr r3, [pc, #220] @ (800b9ac ) 800b8ce: 681b ldr r3, [r3, #0] 800b8d0: f423 22c0 bic.w r2, r3, #393216 @ 0x60000 800b8d4: 687b ldr r3, [r7, #4] 800b8d6: 681b ldr r3, [r3, #0] 800b8d8: 4934 ldr r1, [pc, #208] @ (800b9ac ) 800b8da: 4313 orrs r3, r2 800b8dc: 600b str r3, [r1, #0] /* Clear any previous config */ #if !defined (DUAL_CORE) __HAL_PWR_AVD_EXTI_DISABLE_EVENT (); 800b8de: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b8e2: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b8e6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b8ea: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b8ee: f8c2 3084 str.w r3, [r2, #132] @ 0x84 __HAL_PWR_AVD_EXTI_DISABLE_IT (); 800b8f2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b8f6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b8fa: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b8fe: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b902: f8c2 3080 str.w r3, [r2, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE (); 800b906: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b90a: 681b ldr r3, [r3, #0] 800b90c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b910: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b914: 6013 str r3, [r2, #0] __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE (); 800b916: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b91a: 685b ldr r3, [r3, #4] 800b91c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b920: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b924: 6053 str r3, [r2, #4] #if !defined (DUAL_CORE) /* Configure the interrupt mode */ if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT) 800b926: 687b ldr r3, [r7, #4] 800b928: 685b ldr r3, [r3, #4] 800b92a: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b92e: 2b00 cmp r3, #0 800b930: d009 beq.n 800b946 { __HAL_PWR_AVD_EXTI_ENABLE_IT (); 800b932: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b936: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b93a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b93e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b942: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } /* Configure the event mode */ if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT) 800b946: 687b ldr r3, [r7, #4] 800b948: 685b ldr r3, [r3, #4] 800b94a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b94e: 2b00 cmp r3, #0 800b950: d009 beq.n 800b966 { __HAL_PWR_AVD_EXTI_ENABLE_EVENT (); 800b952: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b956: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b95a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b95e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b962: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE) 800b966: 687b ldr r3, [r7, #4] 800b968: 685b ldr r3, [r3, #4] 800b96a: f003 0301 and.w r3, r3, #1 800b96e: 2b00 cmp r3, #0 800b970: d007 beq.n 800b982 { __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE (); 800b972: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b976: 681b ldr r3, [r3, #0] 800b978: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b97c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b980: 6013 str r3, [r2, #0] } /* Falling edge configuration */ if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE) 800b982: 687b ldr r3, [r7, #4] 800b984: 685b ldr r3, [r3, #4] 800b986: f003 0302 and.w r3, r3, #2 800b98a: 2b00 cmp r3, #0 800b98c: d007 beq.n 800b99e { __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE (); 800b98e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b992: 685b ldr r3, [r3, #4] 800b994: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b998: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b99c: 6053 str r3, [r2, #4] } } 800b99e: bf00 nop 800b9a0: 370c adds r7, #12 800b9a2: 46bd mov sp, r7 800b9a4: f85d 7b04 ldr.w r7, [sp], #4 800b9a8: 4770 bx lr 800b9aa: bf00 nop 800b9ac: 58024800 .word 0x58024800 0800b9b0 : /** * @brief Enable the Analog Voltage Detector (AVD). * @retval None. */ void HAL_PWREx_EnableAVD (void) { 800b9b0: b480 push {r7} 800b9b2: af00 add r7, sp, #0 /* Enable the Analog Voltage Detector */ SET_BIT (PWR->CR1, PWR_CR1_AVDEN); 800b9b4: 4b05 ldr r3, [pc, #20] @ (800b9cc ) 800b9b6: 681b ldr r3, [r3, #0] 800b9b8: 4a04 ldr r2, [pc, #16] @ (800b9cc ) 800b9ba: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b9be: 6013 str r3, [r2, #0] } 800b9c0: bf00 nop 800b9c2: 46bd mov sp, r7 800b9c4: f85d 7b04 ldr.w r7, [sp], #4 800b9c8: 4770 bx lr 800b9ca: bf00 nop 800b9cc: 58024800 .word 0x58024800 0800b9d0 : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800b9d0: b580 push {r7, lr} 800b9d2: b08c sub sp, #48 @ 0x30 800b9d4: af00 add r7, sp, #0 800b9d6: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 800b9d8: 687b ldr r3, [r7, #4] 800b9da: 2b00 cmp r3, #0 800b9dc: d102 bne.n 800b9e4 { return HAL_ERROR; 800b9de: 2301 movs r3, #1 800b9e0: f000 bc48 b.w 800c274 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800b9e4: 687b ldr r3, [r7, #4] 800b9e6: 681b ldr r3, [r3, #0] 800b9e8: f003 0301 and.w r3, r3, #1 800b9ec: 2b00 cmp r3, #0 800b9ee: f000 8088 beq.w 800bb02 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b9f2: 4b99 ldr r3, [pc, #612] @ (800bc58 ) 800b9f4: 691b ldr r3, [r3, #16] 800b9f6: f003 0338 and.w r3, r3, #56 @ 0x38 800b9fa: 62fb str r3, [r7, #44] @ 0x2c const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800b9fc: 4b96 ldr r3, [pc, #600] @ (800bc58 ) 800b9fe: 6a9b ldr r3, [r3, #40] @ 0x28 800ba00: 62bb str r3, [r7, #40] @ 0x28 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 800ba02: 6afb ldr r3, [r7, #44] @ 0x2c 800ba04: 2b10 cmp r3, #16 800ba06: d007 beq.n 800ba18 800ba08: 6afb ldr r3, [r7, #44] @ 0x2c 800ba0a: 2b18 cmp r3, #24 800ba0c: d111 bne.n 800ba32 800ba0e: 6abb ldr r3, [r7, #40] @ 0x28 800ba10: f003 0303 and.w r3, r3, #3 800ba14: 2b02 cmp r3, #2 800ba16: d10c bne.n 800ba32 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800ba18: 4b8f ldr r3, [pc, #572] @ (800bc58 ) 800ba1a: 681b ldr r3, [r3, #0] 800ba1c: f403 3300 and.w r3, r3, #131072 @ 0x20000 800ba20: 2b00 cmp r3, #0 800ba22: d06d beq.n 800bb00 800ba24: 687b ldr r3, [r7, #4] 800ba26: 685b ldr r3, [r3, #4] 800ba28: 2b00 cmp r3, #0 800ba2a: d169 bne.n 800bb00 { return HAL_ERROR; 800ba2c: 2301 movs r3, #1 800ba2e: f000 bc21 b.w 800c274 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800ba32: 687b ldr r3, [r7, #4] 800ba34: 685b ldr r3, [r3, #4] 800ba36: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800ba3a: d106 bne.n 800ba4a 800ba3c: 4b86 ldr r3, [pc, #536] @ (800bc58 ) 800ba3e: 681b ldr r3, [r3, #0] 800ba40: 4a85 ldr r2, [pc, #532] @ (800bc58 ) 800ba42: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800ba46: 6013 str r3, [r2, #0] 800ba48: e02e b.n 800baa8 800ba4a: 687b ldr r3, [r7, #4] 800ba4c: 685b ldr r3, [r3, #4] 800ba4e: 2b00 cmp r3, #0 800ba50: d10c bne.n 800ba6c 800ba52: 4b81 ldr r3, [pc, #516] @ (800bc58 ) 800ba54: 681b ldr r3, [r3, #0] 800ba56: 4a80 ldr r2, [pc, #512] @ (800bc58 ) 800ba58: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ba5c: 6013 str r3, [r2, #0] 800ba5e: 4b7e ldr r3, [pc, #504] @ (800bc58 ) 800ba60: 681b ldr r3, [r3, #0] 800ba62: 4a7d ldr r2, [pc, #500] @ (800bc58 ) 800ba64: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800ba68: 6013 str r3, [r2, #0] 800ba6a: e01d b.n 800baa8 800ba6c: 687b ldr r3, [r7, #4] 800ba6e: 685b ldr r3, [r3, #4] 800ba70: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800ba74: d10c bne.n 800ba90 800ba76: 4b78 ldr r3, [pc, #480] @ (800bc58 ) 800ba78: 681b ldr r3, [r3, #0] 800ba7a: 4a77 ldr r2, [pc, #476] @ (800bc58 ) 800ba7c: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800ba80: 6013 str r3, [r2, #0] 800ba82: 4b75 ldr r3, [pc, #468] @ (800bc58 ) 800ba84: 681b ldr r3, [r3, #0] 800ba86: 4a74 ldr r2, [pc, #464] @ (800bc58 ) 800ba88: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800ba8c: 6013 str r3, [r2, #0] 800ba8e: e00b b.n 800baa8 800ba90: 4b71 ldr r3, [pc, #452] @ (800bc58 ) 800ba92: 681b ldr r3, [r3, #0] 800ba94: 4a70 ldr r2, [pc, #448] @ (800bc58 ) 800ba96: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ba9a: 6013 str r3, [r2, #0] 800ba9c: 4b6e ldr r3, [pc, #440] @ (800bc58 ) 800ba9e: 681b ldr r3, [r3, #0] 800baa0: 4a6d ldr r2, [pc, #436] @ (800bc58 ) 800baa2: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800baa6: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 800baa8: 687b ldr r3, [r7, #4] 800baaa: 685b ldr r3, [r3, #4] 800baac: 2b00 cmp r3, #0 800baae: d013 beq.n 800bad8 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bab0: f7fa f9f8 bl 8005ea4 800bab4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800bab6: e008 b.n 800baca { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800bab8: f7fa f9f4 bl 8005ea4 800babc: 4602 mov r2, r0 800babe: 6a7b ldr r3, [r7, #36] @ 0x24 800bac0: 1ad3 subs r3, r2, r3 800bac2: 2b64 cmp r3, #100 @ 0x64 800bac4: d901 bls.n 800baca { return HAL_TIMEOUT; 800bac6: 2303 movs r3, #3 800bac8: e3d4 b.n 800c274 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800baca: 4b63 ldr r3, [pc, #396] @ (800bc58 ) 800bacc: 681b ldr r3, [r3, #0] 800bace: f403 3300 and.w r3, r3, #131072 @ 0x20000 800bad2: 2b00 cmp r3, #0 800bad4: d0f0 beq.n 800bab8 800bad6: e014 b.n 800bb02 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bad8: f7fa f9e4 bl 8005ea4 800badc: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800bade: e008 b.n 800baf2 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800bae0: f7fa f9e0 bl 8005ea4 800bae4: 4602 mov r2, r0 800bae6: 6a7b ldr r3, [r7, #36] @ 0x24 800bae8: 1ad3 subs r3, r2, r3 800baea: 2b64 cmp r3, #100 @ 0x64 800baec: d901 bls.n 800baf2 { return HAL_TIMEOUT; 800baee: 2303 movs r3, #3 800baf0: e3c0 b.n 800c274 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800baf2: 4b59 ldr r3, [pc, #356] @ (800bc58 ) 800baf4: 681b ldr r3, [r3, #0] 800baf6: f403 3300 and.w r3, r3, #131072 @ 0x20000 800bafa: 2b00 cmp r3, #0 800bafc: d1f0 bne.n 800bae0 800bafe: e000 b.n 800bb02 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800bb00: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800bb02: 687b ldr r3, [r7, #4] 800bb04: 681b ldr r3, [r3, #0] 800bb06: f003 0302 and.w r3, r3, #2 800bb0a: 2b00 cmp r3, #0 800bb0c: f000 80ca beq.w 800bca4 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800bb10: 4b51 ldr r3, [pc, #324] @ (800bc58 ) 800bb12: 691b ldr r3, [r3, #16] 800bb14: f003 0338 and.w r3, r3, #56 @ 0x38 800bb18: 623b str r3, [r7, #32] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800bb1a: 4b4f ldr r3, [pc, #316] @ (800bc58 ) 800bb1c: 6a9b ldr r3, [r3, #40] @ 0x28 800bb1e: 61fb str r3, [r7, #28] if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 800bb20: 6a3b ldr r3, [r7, #32] 800bb22: 2b00 cmp r3, #0 800bb24: d007 beq.n 800bb36 800bb26: 6a3b ldr r3, [r7, #32] 800bb28: 2b18 cmp r3, #24 800bb2a: d156 bne.n 800bbda 800bb2c: 69fb ldr r3, [r7, #28] 800bb2e: f003 0303 and.w r3, r3, #3 800bb32: 2b00 cmp r3, #0 800bb34: d151 bne.n 800bbda { /* When HSI is used as system clock it will not be disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800bb36: 4b48 ldr r3, [pc, #288] @ (800bc58 ) 800bb38: 681b ldr r3, [r3, #0] 800bb3a: f003 0304 and.w r3, r3, #4 800bb3e: 2b00 cmp r3, #0 800bb40: d005 beq.n 800bb4e 800bb42: 687b ldr r3, [r7, #4] 800bb44: 68db ldr r3, [r3, #12] 800bb46: 2b00 cmp r3, #0 800bb48: d101 bne.n 800bb4e { return HAL_ERROR; 800bb4a: 2301 movs r3, #1 800bb4c: e392 b.n 800c274 } /* Otherwise, only HSI division and calibration are allowed */ else { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800bb4e: 4b42 ldr r3, [pc, #264] @ (800bc58 ) 800bb50: 681b ldr r3, [r3, #0] 800bb52: f023 0219 bic.w r2, r3, #25 800bb56: 687b ldr r3, [r7, #4] 800bb58: 68db ldr r3, [r3, #12] 800bb5a: 493f ldr r1, [pc, #252] @ (800bc58 ) 800bb5c: 4313 orrs r3, r2 800bb5e: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bb60: f7fa f9a0 bl 8005ea4 800bb64: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800bb66: e008 b.n 800bb7a { if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800bb68: f7fa f99c bl 8005ea4 800bb6c: 4602 mov r2, r0 800bb6e: 6a7b ldr r3, [r7, #36] @ 0x24 800bb70: 1ad3 subs r3, r2, r3 800bb72: 2b02 cmp r3, #2 800bb74: d901 bls.n 800bb7a { return HAL_TIMEOUT; 800bb76: 2303 movs r3, #3 800bb78: e37c b.n 800c274 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800bb7a: 4b37 ldr r3, [pc, #220] @ (800bc58 ) 800bb7c: 681b ldr r3, [r3, #0] 800bb7e: f003 0304 and.w r3, r3, #4 800bb82: 2b00 cmp r3, #0 800bb84: d0f0 beq.n 800bb68 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800bb86: f7fa f999 bl 8005ebc 800bb8a: 4603 mov r3, r0 800bb8c: f241 0203 movw r2, #4099 @ 0x1003 800bb90: 4293 cmp r3, r2 800bb92: d817 bhi.n 800bbc4 800bb94: 687b ldr r3, [r7, #4] 800bb96: 691b ldr r3, [r3, #16] 800bb98: 2b40 cmp r3, #64 @ 0x40 800bb9a: d108 bne.n 800bbae 800bb9c: 4b2e ldr r3, [pc, #184] @ (800bc58 ) 800bb9e: 685b ldr r3, [r3, #4] 800bba0: f423 337c bic.w r3, r3, #258048 @ 0x3f000 800bba4: 4a2c ldr r2, [pc, #176] @ (800bc58 ) 800bba6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800bbaa: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800bbac: e07a b.n 800bca4 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800bbae: 4b2a ldr r3, [pc, #168] @ (800bc58 ) 800bbb0: 685b ldr r3, [r3, #4] 800bbb2: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800bbb6: 687b ldr r3, [r7, #4] 800bbb8: 691b ldr r3, [r3, #16] 800bbba: 031b lsls r3, r3, #12 800bbbc: 4926 ldr r1, [pc, #152] @ (800bc58 ) 800bbbe: 4313 orrs r3, r2 800bbc0: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800bbc2: e06f b.n 800bca4 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800bbc4: 4b24 ldr r3, [pc, #144] @ (800bc58 ) 800bbc6: 685b ldr r3, [r3, #4] 800bbc8: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800bbcc: 687b ldr r3, [r7, #4] 800bbce: 691b ldr r3, [r3, #16] 800bbd0: 061b lsls r3, r3, #24 800bbd2: 4921 ldr r1, [pc, #132] @ (800bc58 ) 800bbd4: 4313 orrs r3, r2 800bbd6: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800bbd8: e064 b.n 800bca4 } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 800bbda: 687b ldr r3, [r7, #4] 800bbdc: 68db ldr r3, [r3, #12] 800bbde: 2b00 cmp r3, #0 800bbe0: d047 beq.n 800bc72 { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800bbe2: 4b1d ldr r3, [pc, #116] @ (800bc58 ) 800bbe4: 681b ldr r3, [r3, #0] 800bbe6: f023 0219 bic.w r2, r3, #25 800bbea: 687b ldr r3, [r7, #4] 800bbec: 68db ldr r3, [r3, #12] 800bbee: 491a ldr r1, [pc, #104] @ (800bc58 ) 800bbf0: 4313 orrs r3, r2 800bbf2: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bbf4: f7fa f956 bl 8005ea4 800bbf8: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800bbfa: e008 b.n 800bc0e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800bbfc: f7fa f952 bl 8005ea4 800bc00: 4602 mov r2, r0 800bc02: 6a7b ldr r3, [r7, #36] @ 0x24 800bc04: 1ad3 subs r3, r2, r3 800bc06: 2b02 cmp r3, #2 800bc08: d901 bls.n 800bc0e { return HAL_TIMEOUT; 800bc0a: 2303 movs r3, #3 800bc0c: e332 b.n 800c274 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800bc0e: 4b12 ldr r3, [pc, #72] @ (800bc58 ) 800bc10: 681b ldr r3, [r3, #0] 800bc12: f003 0304 and.w r3, r3, #4 800bc16: 2b00 cmp r3, #0 800bc18: d0f0 beq.n 800bbfc } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800bc1a: f7fa f94f bl 8005ebc 800bc1e: 4603 mov r3, r0 800bc20: f241 0203 movw r2, #4099 @ 0x1003 800bc24: 4293 cmp r3, r2 800bc26: d819 bhi.n 800bc5c 800bc28: 687b ldr r3, [r7, #4] 800bc2a: 691b ldr r3, [r3, #16] 800bc2c: 2b40 cmp r3, #64 @ 0x40 800bc2e: d108 bne.n 800bc42 800bc30: 4b09 ldr r3, [pc, #36] @ (800bc58 ) 800bc32: 685b ldr r3, [r3, #4] 800bc34: f423 337c bic.w r3, r3, #258048 @ 0x3f000 800bc38: 4a07 ldr r2, [pc, #28] @ (800bc58 ) 800bc3a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800bc3e: 6053 str r3, [r2, #4] 800bc40: e030 b.n 800bca4 800bc42: 4b05 ldr r3, [pc, #20] @ (800bc58 ) 800bc44: 685b ldr r3, [r3, #4] 800bc46: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800bc4a: 687b ldr r3, [r7, #4] 800bc4c: 691b ldr r3, [r3, #16] 800bc4e: 031b lsls r3, r3, #12 800bc50: 4901 ldr r1, [pc, #4] @ (800bc58 ) 800bc52: 4313 orrs r3, r2 800bc54: 604b str r3, [r1, #4] 800bc56: e025 b.n 800bca4 800bc58: 58024400 .word 0x58024400 800bc5c: 4b9a ldr r3, [pc, #616] @ (800bec8 ) 800bc5e: 685b ldr r3, [r3, #4] 800bc60: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800bc64: 687b ldr r3, [r7, #4] 800bc66: 691b ldr r3, [r3, #16] 800bc68: 061b lsls r3, r3, #24 800bc6a: 4997 ldr r1, [pc, #604] @ (800bec8 ) 800bc6c: 4313 orrs r3, r2 800bc6e: 604b str r3, [r1, #4] 800bc70: e018 b.n 800bca4 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800bc72: 4b95 ldr r3, [pc, #596] @ (800bec8 ) 800bc74: 681b ldr r3, [r3, #0] 800bc76: 4a94 ldr r2, [pc, #592] @ (800bec8 ) 800bc78: f023 0301 bic.w r3, r3, #1 800bc7c: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bc7e: f7fa f911 bl 8005ea4 800bc82: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800bc84: e008 b.n 800bc98 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800bc86: f7fa f90d bl 8005ea4 800bc8a: 4602 mov r2, r0 800bc8c: 6a7b ldr r3, [r7, #36] @ 0x24 800bc8e: 1ad3 subs r3, r2, r3 800bc90: 2b02 cmp r3, #2 800bc92: d901 bls.n 800bc98 { return HAL_TIMEOUT; 800bc94: 2303 movs r3, #3 800bc96: e2ed b.n 800c274 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800bc98: 4b8b ldr r3, [pc, #556] @ (800bec8 ) 800bc9a: 681b ldr r3, [r3, #0] 800bc9c: f003 0304 and.w r3, r3, #4 800bca0: 2b00 cmp r3, #0 800bca2: d1f0 bne.n 800bc86 } } } } /*----------------------------- CSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 800bca4: 687b ldr r3, [r7, #4] 800bca6: 681b ldr r3, [r3, #0] 800bca8: f003 0310 and.w r3, r3, #16 800bcac: 2b00 cmp r3, #0 800bcae: f000 80a9 beq.w 800be04 /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800bcb2: 4b85 ldr r3, [pc, #532] @ (800bec8 ) 800bcb4: 691b ldr r3, [r3, #16] 800bcb6: f003 0338 and.w r3, r3, #56 @ 0x38 800bcba: 61bb str r3, [r7, #24] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800bcbc: 4b82 ldr r3, [pc, #520] @ (800bec8 ) 800bcbe: 6a9b ldr r3, [r3, #40] @ 0x28 800bcc0: 617b str r3, [r7, #20] if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 800bcc2: 69bb ldr r3, [r7, #24] 800bcc4: 2b08 cmp r3, #8 800bcc6: d007 beq.n 800bcd8 800bcc8: 69bb ldr r3, [r7, #24] 800bcca: 2b18 cmp r3, #24 800bccc: d13a bne.n 800bd44 800bcce: 697b ldr r3, [r7, #20] 800bcd0: f003 0303 and.w r3, r3, #3 800bcd4: 2b01 cmp r3, #1 800bcd6: d135 bne.n 800bd44 { /* When CSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800bcd8: 4b7b ldr r3, [pc, #492] @ (800bec8 ) 800bcda: 681b ldr r3, [r3, #0] 800bcdc: f403 7380 and.w r3, r3, #256 @ 0x100 800bce0: 2b00 cmp r3, #0 800bce2: d005 beq.n 800bcf0 800bce4: 687b ldr r3, [r7, #4] 800bce6: 69db ldr r3, [r3, #28] 800bce8: 2b80 cmp r3, #128 @ 0x80 800bcea: d001 beq.n 800bcf0 { return HAL_ERROR; 800bcec: 2301 movs r3, #1 800bcee: e2c1 b.n 800c274 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800bcf0: f7fa f8e4 bl 8005ebc 800bcf4: 4603 mov r3, r0 800bcf6: f241 0203 movw r2, #4099 @ 0x1003 800bcfa: 4293 cmp r3, r2 800bcfc: d817 bhi.n 800bd2e 800bcfe: 687b ldr r3, [r7, #4] 800bd00: 6a1b ldr r3, [r3, #32] 800bd02: 2b20 cmp r3, #32 800bd04: d108 bne.n 800bd18 800bd06: 4b70 ldr r3, [pc, #448] @ (800bec8 ) 800bd08: 685b ldr r3, [r3, #4] 800bd0a: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 800bd0e: 4a6e ldr r2, [pc, #440] @ (800bec8 ) 800bd10: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800bd14: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800bd16: e075 b.n 800be04 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800bd18: 4b6b ldr r3, [pc, #428] @ (800bec8 ) 800bd1a: 685b ldr r3, [r3, #4] 800bd1c: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800bd20: 687b ldr r3, [r7, #4] 800bd22: 6a1b ldr r3, [r3, #32] 800bd24: 069b lsls r3, r3, #26 800bd26: 4968 ldr r1, [pc, #416] @ (800bec8 ) 800bd28: 4313 orrs r3, r2 800bd2a: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800bd2c: e06a b.n 800be04 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800bd2e: 4b66 ldr r3, [pc, #408] @ (800bec8 ) 800bd30: 68db ldr r3, [r3, #12] 800bd32: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 800bd36: 687b ldr r3, [r7, #4] 800bd38: 6a1b ldr r3, [r3, #32] 800bd3a: 061b lsls r3, r3, #24 800bd3c: 4962 ldr r1, [pc, #392] @ (800bec8 ) 800bd3e: 4313 orrs r3, r2 800bd40: 60cb str r3, [r1, #12] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800bd42: e05f b.n 800be04 } } else { /* Check the CSI State */ if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) 800bd44: 687b ldr r3, [r7, #4] 800bd46: 69db ldr r3, [r3, #28] 800bd48: 2b00 cmp r3, #0 800bd4a: d042 beq.n 800bdd2 { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 800bd4c: 4b5e ldr r3, [pc, #376] @ (800bec8 ) 800bd4e: 681b ldr r3, [r3, #0] 800bd50: 4a5d ldr r2, [pc, #372] @ (800bec8 ) 800bd52: f043 0380 orr.w r3, r3, #128 @ 0x80 800bd56: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bd58: f7fa f8a4 bl 8005ea4 800bd5c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800bd5e: e008 b.n 800bd72 { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 800bd60: f7fa f8a0 bl 8005ea4 800bd64: 4602 mov r2, r0 800bd66: 6a7b ldr r3, [r7, #36] @ 0x24 800bd68: 1ad3 subs r3, r2, r3 800bd6a: 2b02 cmp r3, #2 800bd6c: d901 bls.n 800bd72 { return HAL_TIMEOUT; 800bd6e: 2303 movs r3, #3 800bd70: e280 b.n 800c274 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800bd72: 4b55 ldr r3, [pc, #340] @ (800bec8 ) 800bd74: 681b ldr r3, [r3, #0] 800bd76: f403 7380 and.w r3, r3, #256 @ 0x100 800bd7a: 2b00 cmp r3, #0 800bd7c: d0f0 beq.n 800bd60 } } /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800bd7e: f7fa f89d bl 8005ebc 800bd82: 4603 mov r3, r0 800bd84: f241 0203 movw r2, #4099 @ 0x1003 800bd88: 4293 cmp r3, r2 800bd8a: d817 bhi.n 800bdbc 800bd8c: 687b ldr r3, [r7, #4] 800bd8e: 6a1b ldr r3, [r3, #32] 800bd90: 2b20 cmp r3, #32 800bd92: d108 bne.n 800bda6 800bd94: 4b4c ldr r3, [pc, #304] @ (800bec8 ) 800bd96: 685b ldr r3, [r3, #4] 800bd98: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 800bd9c: 4a4a ldr r2, [pc, #296] @ (800bec8 ) 800bd9e: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800bda2: 6053 str r3, [r2, #4] 800bda4: e02e b.n 800be04 800bda6: 4b48 ldr r3, [pc, #288] @ (800bec8 ) 800bda8: 685b ldr r3, [r3, #4] 800bdaa: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800bdae: 687b ldr r3, [r7, #4] 800bdb0: 6a1b ldr r3, [r3, #32] 800bdb2: 069b lsls r3, r3, #26 800bdb4: 4944 ldr r1, [pc, #272] @ (800bec8 ) 800bdb6: 4313 orrs r3, r2 800bdb8: 604b str r3, [r1, #4] 800bdba: e023 b.n 800be04 800bdbc: 4b42 ldr r3, [pc, #264] @ (800bec8 ) 800bdbe: 68db ldr r3, [r3, #12] 800bdc0: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 800bdc4: 687b ldr r3, [r7, #4] 800bdc6: 6a1b ldr r3, [r3, #32] 800bdc8: 061b lsls r3, r3, #24 800bdca: 493f ldr r1, [pc, #252] @ (800bec8 ) 800bdcc: 4313 orrs r3, r2 800bdce: 60cb str r3, [r1, #12] 800bdd0: e018 b.n 800be04 } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 800bdd2: 4b3d ldr r3, [pc, #244] @ (800bec8 ) 800bdd4: 681b ldr r3, [r3, #0] 800bdd6: 4a3c ldr r2, [pc, #240] @ (800bec8 ) 800bdd8: f023 0380 bic.w r3, r3, #128 @ 0x80 800bddc: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bdde: f7fa f861 bl 8005ea4 800bde2: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800bde4: e008 b.n 800bdf8 { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 800bde6: f7fa f85d bl 8005ea4 800bdea: 4602 mov r2, r0 800bdec: 6a7b ldr r3, [r7, #36] @ 0x24 800bdee: 1ad3 subs r3, r2, r3 800bdf0: 2b02 cmp r3, #2 800bdf2: d901 bls.n 800bdf8 { return HAL_TIMEOUT; 800bdf4: 2303 movs r3, #3 800bdf6: e23d b.n 800c274 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800bdf8: 4b33 ldr r3, [pc, #204] @ (800bec8 ) 800bdfa: 681b ldr r3, [r3, #0] 800bdfc: f403 7380 and.w r3, r3, #256 @ 0x100 800be00: 2b00 cmp r3, #0 800be02: d1f0 bne.n 800bde6 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800be04: 687b ldr r3, [r7, #4] 800be06: 681b ldr r3, [r3, #0] 800be08: f003 0308 and.w r3, r3, #8 800be0c: 2b00 cmp r3, #0 800be0e: d036 beq.n 800be7e { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 800be10: 687b ldr r3, [r7, #4] 800be12: 695b ldr r3, [r3, #20] 800be14: 2b00 cmp r3, #0 800be16: d019 beq.n 800be4c { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800be18: 4b2b ldr r3, [pc, #172] @ (800bec8 ) 800be1a: 6f5b ldr r3, [r3, #116] @ 0x74 800be1c: 4a2a ldr r2, [pc, #168] @ (800bec8 ) 800be1e: f043 0301 orr.w r3, r3, #1 800be22: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800be24: f7fa f83e bl 8005ea4 800be28: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800be2a: e008 b.n 800be3e { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800be2c: f7fa f83a bl 8005ea4 800be30: 4602 mov r2, r0 800be32: 6a7b ldr r3, [r7, #36] @ 0x24 800be34: 1ad3 subs r3, r2, r3 800be36: 2b02 cmp r3, #2 800be38: d901 bls.n 800be3e { return HAL_TIMEOUT; 800be3a: 2303 movs r3, #3 800be3c: e21a b.n 800c274 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800be3e: 4b22 ldr r3, [pc, #136] @ (800bec8 ) 800be40: 6f5b ldr r3, [r3, #116] @ 0x74 800be42: f003 0302 and.w r3, r3, #2 800be46: 2b00 cmp r3, #0 800be48: d0f0 beq.n 800be2c 800be4a: e018 b.n 800be7e } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800be4c: 4b1e ldr r3, [pc, #120] @ (800bec8 ) 800be4e: 6f5b ldr r3, [r3, #116] @ 0x74 800be50: 4a1d ldr r2, [pc, #116] @ (800bec8 ) 800be52: f023 0301 bic.w r3, r3, #1 800be56: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800be58: f7fa f824 bl 8005ea4 800be5c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800be5e: e008 b.n 800be72 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800be60: f7fa f820 bl 8005ea4 800be64: 4602 mov r2, r0 800be66: 6a7b ldr r3, [r7, #36] @ 0x24 800be68: 1ad3 subs r3, r2, r3 800be6a: 2b02 cmp r3, #2 800be6c: d901 bls.n 800be72 { return HAL_TIMEOUT; 800be6e: 2303 movs r3, #3 800be70: e200 b.n 800c274 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800be72: 4b15 ldr r3, [pc, #84] @ (800bec8 ) 800be74: 6f5b ldr r3, [r3, #116] @ 0x74 800be76: f003 0302 and.w r3, r3, #2 800be7a: 2b00 cmp r3, #0 800be7c: d1f0 bne.n 800be60 } } } /*------------------------------ HSI48 Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 800be7e: 687b ldr r3, [r7, #4] 800be80: 681b ldr r3, [r3, #0] 800be82: f003 0320 and.w r3, r3, #32 800be86: 2b00 cmp r3, #0 800be88: d039 beq.n 800befe { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) 800be8a: 687b ldr r3, [r7, #4] 800be8c: 699b ldr r3, [r3, #24] 800be8e: 2b00 cmp r3, #0 800be90: d01c beq.n 800becc { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 800be92: 4b0d ldr r3, [pc, #52] @ (800bec8 ) 800be94: 681b ldr r3, [r3, #0] 800be96: 4a0c ldr r2, [pc, #48] @ (800bec8 ) 800be98: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800be9c: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800be9e: f7fa f801 bl 8005ea4 800bea2: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 800bea4: e008 b.n 800beb8 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800bea6: f7f9 fffd bl 8005ea4 800beaa: 4602 mov r2, r0 800beac: 6a7b ldr r3, [r7, #36] @ 0x24 800beae: 1ad3 subs r3, r2, r3 800beb0: 2b02 cmp r3, #2 800beb2: d901 bls.n 800beb8 { return HAL_TIMEOUT; 800beb4: 2303 movs r3, #3 800beb6: e1dd b.n 800c274 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 800beb8: 4b03 ldr r3, [pc, #12] @ (800bec8 ) 800beba: 681b ldr r3, [r3, #0] 800bebc: f403 5300 and.w r3, r3, #8192 @ 0x2000 800bec0: 2b00 cmp r3, #0 800bec2: d0f0 beq.n 800bea6 800bec4: e01b b.n 800befe 800bec6: bf00 nop 800bec8: 58024400 .word 0x58024400 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 800becc: 4b9b ldr r3, [pc, #620] @ (800c13c ) 800bece: 681b ldr r3, [r3, #0] 800bed0: 4a9a ldr r2, [pc, #616] @ (800c13c ) 800bed2: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800bed6: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800bed8: f7f9 ffe4 bl 8005ea4 800bedc: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800bede: e008 b.n 800bef2 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800bee0: f7f9 ffe0 bl 8005ea4 800bee4: 4602 mov r2, r0 800bee6: 6a7b ldr r3, [r7, #36] @ 0x24 800bee8: 1ad3 subs r3, r2, r3 800beea: 2b02 cmp r3, #2 800beec: d901 bls.n 800bef2 { return HAL_TIMEOUT; 800beee: 2303 movs r3, #3 800bef0: e1c0 b.n 800c274 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800bef2: 4b92 ldr r3, [pc, #584] @ (800c13c ) 800bef4: 681b ldr r3, [r3, #0] 800bef6: f403 5300 and.w r3, r3, #8192 @ 0x2000 800befa: 2b00 cmp r3, #0 800befc: d1f0 bne.n 800bee0 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800befe: 687b ldr r3, [r7, #4] 800bf00: 681b ldr r3, [r3, #0] 800bf02: f003 0304 and.w r3, r3, #4 800bf06: 2b00 cmp r3, #0 800bf08: f000 8081 beq.w 800c00e { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 800bf0c: 4b8c ldr r3, [pc, #560] @ (800c140 ) 800bf0e: 681b ldr r3, [r3, #0] 800bf10: 4a8b ldr r2, [pc, #556] @ (800c140 ) 800bf12: f443 7380 orr.w r3, r3, #256 @ 0x100 800bf16: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800bf18: f7f9 ffc4 bl 8005ea4 800bf1c: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800bf1e: e008 b.n 800bf32 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800bf20: f7f9 ffc0 bl 8005ea4 800bf24: 4602 mov r2, r0 800bf26: 6a7b ldr r3, [r7, #36] @ 0x24 800bf28: 1ad3 subs r3, r2, r3 800bf2a: 2b64 cmp r3, #100 @ 0x64 800bf2c: d901 bls.n 800bf32 { return HAL_TIMEOUT; 800bf2e: 2303 movs r3, #3 800bf30: e1a0 b.n 800c274 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800bf32: 4b83 ldr r3, [pc, #524] @ (800c140 ) 800bf34: 681b ldr r3, [r3, #0] 800bf36: f403 7380 and.w r3, r3, #256 @ 0x100 800bf3a: 2b00 cmp r3, #0 800bf3c: d0f0 beq.n 800bf20 } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800bf3e: 687b ldr r3, [r7, #4] 800bf40: 689b ldr r3, [r3, #8] 800bf42: 2b01 cmp r3, #1 800bf44: d106 bne.n 800bf54 800bf46: 4b7d ldr r3, [pc, #500] @ (800c13c ) 800bf48: 6f1b ldr r3, [r3, #112] @ 0x70 800bf4a: 4a7c ldr r2, [pc, #496] @ (800c13c ) 800bf4c: f043 0301 orr.w r3, r3, #1 800bf50: 6713 str r3, [r2, #112] @ 0x70 800bf52: e02d b.n 800bfb0 800bf54: 687b ldr r3, [r7, #4] 800bf56: 689b ldr r3, [r3, #8] 800bf58: 2b00 cmp r3, #0 800bf5a: d10c bne.n 800bf76 800bf5c: 4b77 ldr r3, [pc, #476] @ (800c13c ) 800bf5e: 6f1b ldr r3, [r3, #112] @ 0x70 800bf60: 4a76 ldr r2, [pc, #472] @ (800c13c ) 800bf62: f023 0301 bic.w r3, r3, #1 800bf66: 6713 str r3, [r2, #112] @ 0x70 800bf68: 4b74 ldr r3, [pc, #464] @ (800c13c ) 800bf6a: 6f1b ldr r3, [r3, #112] @ 0x70 800bf6c: 4a73 ldr r2, [pc, #460] @ (800c13c ) 800bf6e: f023 0304 bic.w r3, r3, #4 800bf72: 6713 str r3, [r2, #112] @ 0x70 800bf74: e01c b.n 800bfb0 800bf76: 687b ldr r3, [r7, #4] 800bf78: 689b ldr r3, [r3, #8] 800bf7a: 2b05 cmp r3, #5 800bf7c: d10c bne.n 800bf98 800bf7e: 4b6f ldr r3, [pc, #444] @ (800c13c ) 800bf80: 6f1b ldr r3, [r3, #112] @ 0x70 800bf82: 4a6e ldr r2, [pc, #440] @ (800c13c ) 800bf84: f043 0304 orr.w r3, r3, #4 800bf88: 6713 str r3, [r2, #112] @ 0x70 800bf8a: 4b6c ldr r3, [pc, #432] @ (800c13c ) 800bf8c: 6f1b ldr r3, [r3, #112] @ 0x70 800bf8e: 4a6b ldr r2, [pc, #428] @ (800c13c ) 800bf90: f043 0301 orr.w r3, r3, #1 800bf94: 6713 str r3, [r2, #112] @ 0x70 800bf96: e00b b.n 800bfb0 800bf98: 4b68 ldr r3, [pc, #416] @ (800c13c ) 800bf9a: 6f1b ldr r3, [r3, #112] @ 0x70 800bf9c: 4a67 ldr r2, [pc, #412] @ (800c13c ) 800bf9e: f023 0301 bic.w r3, r3, #1 800bfa2: 6713 str r3, [r2, #112] @ 0x70 800bfa4: 4b65 ldr r3, [pc, #404] @ (800c13c ) 800bfa6: 6f1b ldr r3, [r3, #112] @ 0x70 800bfa8: 4a64 ldr r2, [pc, #400] @ (800c13c ) 800bfaa: f023 0304 bic.w r3, r3, #4 800bfae: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 800bfb0: 687b ldr r3, [r7, #4] 800bfb2: 689b ldr r3, [r3, #8] 800bfb4: 2b00 cmp r3, #0 800bfb6: d015 beq.n 800bfe4 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bfb8: f7f9 ff74 bl 8005ea4 800bfbc: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800bfbe: e00a b.n 800bfd6 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800bfc0: f7f9 ff70 bl 8005ea4 800bfc4: 4602 mov r2, r0 800bfc6: 6a7b ldr r3, [r7, #36] @ 0x24 800bfc8: 1ad3 subs r3, r2, r3 800bfca: f241 3288 movw r2, #5000 @ 0x1388 800bfce: 4293 cmp r3, r2 800bfd0: d901 bls.n 800bfd6 { return HAL_TIMEOUT; 800bfd2: 2303 movs r3, #3 800bfd4: e14e b.n 800c274 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800bfd6: 4b59 ldr r3, [pc, #356] @ (800c13c ) 800bfd8: 6f1b ldr r3, [r3, #112] @ 0x70 800bfda: f003 0302 and.w r3, r3, #2 800bfde: 2b00 cmp r3, #0 800bfe0: d0ee beq.n 800bfc0 800bfe2: e014 b.n 800c00e } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bfe4: f7f9 ff5e bl 8005ea4 800bfe8: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800bfea: e00a b.n 800c002 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800bfec: f7f9 ff5a bl 8005ea4 800bff0: 4602 mov r2, r0 800bff2: 6a7b ldr r3, [r7, #36] @ 0x24 800bff4: 1ad3 subs r3, r2, r3 800bff6: f241 3288 movw r2, #5000 @ 0x1388 800bffa: 4293 cmp r3, r2 800bffc: d901 bls.n 800c002 { return HAL_TIMEOUT; 800bffe: 2303 movs r3, #3 800c000: e138 b.n 800c274 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800c002: 4b4e ldr r3, [pc, #312] @ (800c13c ) 800c004: 6f1b ldr r3, [r3, #112] @ 0x70 800c006: f003 0302 and.w r3, r3, #2 800c00a: 2b00 cmp r3, #0 800c00c: d1ee bne.n 800bfec } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800c00e: 687b ldr r3, [r7, #4] 800c010: 6a5b ldr r3, [r3, #36] @ 0x24 800c012: 2b00 cmp r3, #0 800c014: f000 812d beq.w 800c272 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 800c018: 4b48 ldr r3, [pc, #288] @ (800c13c ) 800c01a: 691b ldr r3, [r3, #16] 800c01c: f003 0338 and.w r3, r3, #56 @ 0x38 800c020: 2b18 cmp r3, #24 800c022: f000 80bd beq.w 800c1a0 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 800c026: 687b ldr r3, [r7, #4] 800c028: 6a5b ldr r3, [r3, #36] @ 0x24 800c02a: 2b02 cmp r3, #2 800c02c: f040 809e bne.w 800c16c assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800c030: 4b42 ldr r3, [pc, #264] @ (800c13c ) 800c032: 681b ldr r3, [r3, #0] 800c034: 4a41 ldr r2, [pc, #260] @ (800c13c ) 800c036: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800c03a: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c03c: f7f9 ff32 bl 8005ea4 800c040: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800c042: e008 b.n 800c056 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800c044: f7f9 ff2e bl 8005ea4 800c048: 4602 mov r2, r0 800c04a: 6a7b ldr r3, [r7, #36] @ 0x24 800c04c: 1ad3 subs r3, r2, r3 800c04e: 2b02 cmp r3, #2 800c050: d901 bls.n 800c056 { return HAL_TIMEOUT; 800c052: 2303 movs r3, #3 800c054: e10e b.n 800c274 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800c056: 4b39 ldr r3, [pc, #228] @ (800c13c ) 800c058: 681b ldr r3, [r3, #0] 800c05a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800c05e: 2b00 cmp r3, #0 800c060: d1f0 bne.n 800c044 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 800c062: 4b36 ldr r3, [pc, #216] @ (800c13c ) 800c064: 6a9a ldr r2, [r3, #40] @ 0x28 800c066: 4b37 ldr r3, [pc, #220] @ (800c144 ) 800c068: 4013 ands r3, r2 800c06a: 687a ldr r2, [r7, #4] 800c06c: 6a91 ldr r1, [r2, #40] @ 0x28 800c06e: 687a ldr r2, [r7, #4] 800c070: 6ad2 ldr r2, [r2, #44] @ 0x2c 800c072: 0112 lsls r2, r2, #4 800c074: 430a orrs r2, r1 800c076: 4931 ldr r1, [pc, #196] @ (800c13c ) 800c078: 4313 orrs r3, r2 800c07a: 628b str r3, [r1, #40] @ 0x28 800c07c: 687b ldr r3, [r7, #4] 800c07e: 6b1b ldr r3, [r3, #48] @ 0x30 800c080: 3b01 subs r3, #1 800c082: f3c3 0208 ubfx r2, r3, #0, #9 800c086: 687b ldr r3, [r7, #4] 800c088: 6b5b ldr r3, [r3, #52] @ 0x34 800c08a: 3b01 subs r3, #1 800c08c: 025b lsls r3, r3, #9 800c08e: b29b uxth r3, r3 800c090: 431a orrs r2, r3 800c092: 687b ldr r3, [r7, #4] 800c094: 6b9b ldr r3, [r3, #56] @ 0x38 800c096: 3b01 subs r3, #1 800c098: 041b lsls r3, r3, #16 800c09a: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800c09e: 431a orrs r2, r3 800c0a0: 687b ldr r3, [r7, #4] 800c0a2: 6bdb ldr r3, [r3, #60] @ 0x3c 800c0a4: 3b01 subs r3, #1 800c0a6: 061b lsls r3, r3, #24 800c0a8: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800c0ac: 4923 ldr r1, [pc, #140] @ (800c13c ) 800c0ae: 4313 orrs r3, r2 800c0b0: 630b str r3, [r1, #48] @ 0x30 RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Disable PLLFRACN . */ __HAL_RCC_PLLFRACN_DISABLE(); 800c0b2: 4b22 ldr r3, [pc, #136] @ (800c13c ) 800c0b4: 6adb ldr r3, [r3, #44] @ 0x2c 800c0b6: 4a21 ldr r2, [pc, #132] @ (800c13c ) 800c0b8: f023 0301 bic.w r3, r3, #1 800c0bc: 62d3 str r3, [r2, #44] @ 0x2c /* Configure PLL PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800c0be: 4b1f ldr r3, [pc, #124] @ (800c13c ) 800c0c0: 6b5a ldr r2, [r3, #52] @ 0x34 800c0c2: 4b21 ldr r3, [pc, #132] @ (800c148 ) 800c0c4: 4013 ands r3, r2 800c0c6: 687a ldr r2, [r7, #4] 800c0c8: 6c92 ldr r2, [r2, #72] @ 0x48 800c0ca: 00d2 lsls r2, r2, #3 800c0cc: 491b ldr r1, [pc, #108] @ (800c13c ) 800c0ce: 4313 orrs r3, r2 800c0d0: 634b str r3, [r1, #52] @ 0x34 /* Select PLL1 input reference frequency range: VCI */ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 800c0d2: 4b1a ldr r3, [pc, #104] @ (800c13c ) 800c0d4: 6adb ldr r3, [r3, #44] @ 0x2c 800c0d6: f023 020c bic.w r2, r3, #12 800c0da: 687b ldr r3, [r7, #4] 800c0dc: 6c1b ldr r3, [r3, #64] @ 0x40 800c0de: 4917 ldr r1, [pc, #92] @ (800c13c ) 800c0e0: 4313 orrs r3, r2 800c0e2: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL1 output frequency range : VCO */ __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 800c0e4: 4b15 ldr r3, [pc, #84] @ (800c13c ) 800c0e6: 6adb ldr r3, [r3, #44] @ 0x2c 800c0e8: f023 0202 bic.w r2, r3, #2 800c0ec: 687b ldr r3, [r7, #4] 800c0ee: 6c5b ldr r3, [r3, #68] @ 0x44 800c0f0: 4912 ldr r1, [pc, #72] @ (800c13c ) 800c0f2: 4313 orrs r3, r2 800c0f4: 62cb str r3, [r1, #44] @ 0x2c /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 800c0f6: 4b11 ldr r3, [pc, #68] @ (800c13c ) 800c0f8: 6adb ldr r3, [r3, #44] @ 0x2c 800c0fa: 4a10 ldr r2, [pc, #64] @ (800c13c ) 800c0fc: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800c100: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1Q Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c102: 4b0e ldr r3, [pc, #56] @ (800c13c ) 800c104: 6adb ldr r3, [r3, #44] @ 0x2c 800c106: 4a0d ldr r2, [pc, #52] @ (800c13c ) 800c108: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c10c: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1R Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 800c10e: 4b0b ldr r3, [pc, #44] @ (800c13c ) 800c110: 6adb ldr r3, [r3, #44] @ 0x2c 800c112: 4a0a ldr r2, [pc, #40] @ (800c13c ) 800c114: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800c118: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1FRACN . */ __HAL_RCC_PLLFRACN_ENABLE(); 800c11a: 4b08 ldr r3, [pc, #32] @ (800c13c ) 800c11c: 6adb ldr r3, [r3, #44] @ 0x2c 800c11e: 4a07 ldr r2, [pc, #28] @ (800c13c ) 800c120: f043 0301 orr.w r3, r3, #1 800c124: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800c126: 4b05 ldr r3, [pc, #20] @ (800c13c ) 800c128: 681b ldr r3, [r3, #0] 800c12a: 4a04 ldr r2, [pc, #16] @ (800c13c ) 800c12c: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800c130: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c132: f7f9 feb7 bl 8005ea4 800c136: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800c138: e011 b.n 800c15e 800c13a: bf00 nop 800c13c: 58024400 .word 0x58024400 800c140: 58024800 .word 0x58024800 800c144: fffffc0c .word 0xfffffc0c 800c148: ffff0007 .word 0xffff0007 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800c14c: f7f9 feaa bl 8005ea4 800c150: 4602 mov r2, r0 800c152: 6a7b ldr r3, [r7, #36] @ 0x24 800c154: 1ad3 subs r3, r2, r3 800c156: 2b02 cmp r3, #2 800c158: d901 bls.n 800c15e { return HAL_TIMEOUT; 800c15a: 2303 movs r3, #3 800c15c: e08a b.n 800c274 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800c15e: 4b47 ldr r3, [pc, #284] @ (800c27c ) 800c160: 681b ldr r3, [r3, #0] 800c162: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800c166: 2b00 cmp r3, #0 800c168: d0f0 beq.n 800c14c 800c16a: e082 b.n 800c272 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800c16c: 4b43 ldr r3, [pc, #268] @ (800c27c ) 800c16e: 681b ldr r3, [r3, #0] 800c170: 4a42 ldr r2, [pc, #264] @ (800c27c ) 800c172: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800c176: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c178: f7f9 fe94 bl 8005ea4 800c17c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800c17e: e008 b.n 800c192 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800c180: f7f9 fe90 bl 8005ea4 800c184: 4602 mov r2, r0 800c186: 6a7b ldr r3, [r7, #36] @ 0x24 800c188: 1ad3 subs r3, r2, r3 800c18a: 2b02 cmp r3, #2 800c18c: d901 bls.n 800c192 { return HAL_TIMEOUT; 800c18e: 2303 movs r3, #3 800c190: e070 b.n 800c274 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800c192: 4b3a ldr r3, [pc, #232] @ (800c27c ) 800c194: 681b ldr r3, [r3, #0] 800c196: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800c19a: 2b00 cmp r3, #0 800c19c: d1f0 bne.n 800c180 800c19e: e068 b.n 800c272 } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp1_pllckcfg = RCC->PLLCKSELR; 800c1a0: 4b36 ldr r3, [pc, #216] @ (800c27c ) 800c1a2: 6a9b ldr r3, [r3, #40] @ 0x28 800c1a4: 613b str r3, [r7, #16] temp2_pllckcfg = RCC->PLL1DIVR; 800c1a6: 4b35 ldr r3, [pc, #212] @ (800c27c ) 800c1a8: 6b1b ldr r3, [r3, #48] @ 0x30 800c1aa: 60fb str r3, [r7, #12] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800c1ac: 687b ldr r3, [r7, #4] 800c1ae: 6a5b ldr r3, [r3, #36] @ 0x24 800c1b0: 2b01 cmp r3, #1 800c1b2: d031 beq.n 800c218 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800c1b4: 693b ldr r3, [r7, #16] 800c1b6: f003 0203 and.w r2, r3, #3 800c1ba: 687b ldr r3, [r7, #4] 800c1bc: 6a9b ldr r3, [r3, #40] @ 0x28 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800c1be: 429a cmp r2, r3 800c1c0: d12a bne.n 800c218 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800c1c2: 693b ldr r3, [r7, #16] 800c1c4: 091b lsrs r3, r3, #4 800c1c6: f003 023f and.w r2, r3, #63 @ 0x3f 800c1ca: 687b ldr r3, [r7, #4] 800c1cc: 6adb ldr r3, [r3, #44] @ 0x2c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800c1ce: 429a cmp r2, r3 800c1d0: d122 bne.n 800c218 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800c1d2: 68fb ldr r3, [r7, #12] 800c1d4: f3c3 0208 ubfx r2, r3, #0, #9 800c1d8: 687b ldr r3, [r7, #4] 800c1da: 6b1b ldr r3, [r3, #48] @ 0x30 800c1dc: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800c1de: 429a cmp r2, r3 800c1e0: d11a bne.n 800c218 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800c1e2: 68fb ldr r3, [r7, #12] 800c1e4: 0a5b lsrs r3, r3, #9 800c1e6: f003 027f and.w r2, r3, #127 @ 0x7f 800c1ea: 687b ldr r3, [r7, #4] 800c1ec: 6b5b ldr r3, [r3, #52] @ 0x34 800c1ee: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800c1f0: 429a cmp r2, r3 800c1f2: d111 bne.n 800c218 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 800c1f4: 68fb ldr r3, [r7, #12] 800c1f6: 0c1b lsrs r3, r3, #16 800c1f8: f003 027f and.w r2, r3, #127 @ 0x7f 800c1fc: 687b ldr r3, [r7, #4] 800c1fe: 6b9b ldr r3, [r3, #56] @ 0x38 800c200: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800c202: 429a cmp r2, r3 800c204: d108 bne.n 800c218 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 800c206: 68fb ldr r3, [r7, #12] 800c208: 0e1b lsrs r3, r3, #24 800c20a: f003 027f and.w r2, r3, #127 @ 0x7f 800c20e: 687b ldr r3, [r7, #4] 800c210: 6bdb ldr r3, [r3, #60] @ 0x3c 800c212: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 800c214: 429a cmp r2, r3 800c216: d001 beq.n 800c21c { return HAL_ERROR; 800c218: 2301 movs r3, #1 800c21a: e02b b.n 800c274 } else { /* Check if only fractional part needs to be updated */ temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); 800c21c: 4b17 ldr r3, [pc, #92] @ (800c27c ) 800c21e: 6b5b ldr r3, [r3, #52] @ 0x34 800c220: 08db lsrs r3, r3, #3 800c222: f3c3 030c ubfx r3, r3, #0, #13 800c226: 613b str r3, [r7, #16] if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) 800c228: 687b ldr r3, [r7, #4] 800c22a: 6c9b ldr r3, [r3, #72] @ 0x48 800c22c: 693a ldr r2, [r7, #16] 800c22e: 429a cmp r2, r3 800c230: d01f beq.n 800c272 { assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable PLL1FRACEN */ __HAL_RCC_PLLFRACN_DISABLE(); 800c232: 4b12 ldr r3, [pc, #72] @ (800c27c ) 800c234: 6adb ldr r3, [r3, #44] @ 0x2c 800c236: 4a11 ldr r2, [pc, #68] @ (800c27c ) 800c238: f023 0301 bic.w r3, r3, #1 800c23c: 62d3 str r3, [r2, #44] @ 0x2c /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c23e: f7f9 fe31 bl 8005ea4 800c242: 6278 str r0, [r7, #36] @ 0x24 /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) 800c244: bf00 nop 800c246: f7f9 fe2d bl 8005ea4 800c24a: 4602 mov r2, r0 800c24c: 6a7b ldr r3, [r7, #36] @ 0x24 800c24e: 4293 cmp r3, r2 800c250: d0f9 beq.n 800c246 { } /* Configure PLL1 PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800c252: 4b0a ldr r3, [pc, #40] @ (800c27c ) 800c254: 6b5a ldr r2, [r3, #52] @ 0x34 800c256: 4b0a ldr r3, [pc, #40] @ (800c280 ) 800c258: 4013 ands r3, r2 800c25a: 687a ldr r2, [r7, #4] 800c25c: 6c92 ldr r2, [r2, #72] @ 0x48 800c25e: 00d2 lsls r2, r2, #3 800c260: 4906 ldr r1, [pc, #24] @ (800c27c ) 800c262: 4313 orrs r3, r2 800c264: 634b str r3, [r1, #52] @ 0x34 /* Enable PLL1FRACEN to latch new value. */ __HAL_RCC_PLLFRACN_ENABLE(); 800c266: 4b05 ldr r3, [pc, #20] @ (800c27c ) 800c268: 6adb ldr r3, [r3, #44] @ 0x2c 800c26a: 4a04 ldr r2, [pc, #16] @ (800c27c ) 800c26c: f043 0301 orr.w r3, r3, #1 800c270: 62d3 str r3, [r2, #44] @ 0x2c } } } } return HAL_OK; 800c272: 2300 movs r3, #0 } 800c274: 4618 mov r0, r3 800c276: 3730 adds r7, #48 @ 0x30 800c278: 46bd mov sp, r7 800c27a: bd80 pop {r7, pc} 800c27c: 58024400 .word 0x58024400 800c280: ffff0007 .word 0xffff0007 0800c284 : * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800c284: b580 push {r7, lr} 800c286: b086 sub sp, #24 800c288: af00 add r7, sp, #0 800c28a: 6078 str r0, [r7, #4] 800c28c: 6039 str r1, [r7, #0] HAL_StatusTypeDef halstatus; uint32_t tickstart; uint32_t common_system_clock; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800c28e: 687b ldr r3, [r7, #4] 800c290: 2b00 cmp r3, #0 800c292: d101 bne.n 800c298 { return HAL_ERROR; 800c294: 2301 movs r3, #1 800c296: e19c b.n 800c5d2 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 800c298: 4b8a ldr r3, [pc, #552] @ (800c4c4 ) 800c29a: 681b ldr r3, [r3, #0] 800c29c: f003 030f and.w r3, r3, #15 800c2a0: 683a ldr r2, [r7, #0] 800c2a2: 429a cmp r2, r3 800c2a4: d910 bls.n 800c2c8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800c2a6: 4b87 ldr r3, [pc, #540] @ (800c4c4 ) 800c2a8: 681b ldr r3, [r3, #0] 800c2aa: f023 020f bic.w r2, r3, #15 800c2ae: 4985 ldr r1, [pc, #532] @ (800c4c4 ) 800c2b0: 683b ldr r3, [r7, #0] 800c2b2: 4313 orrs r3, r2 800c2b4: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800c2b6: 4b83 ldr r3, [pc, #524] @ (800c4c4 ) 800c2b8: 681b ldr r3, [r3, #0] 800c2ba: f003 030f and.w r3, r3, #15 800c2be: 683a ldr r2, [r7, #0] 800c2c0: 429a cmp r2, r3 800c2c2: d001 beq.n 800c2c8 { return HAL_ERROR; 800c2c4: 2301 movs r3, #1 800c2c6: e184 b.n 800c5d2 } /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 800c2c8: 687b ldr r3, [r7, #4] 800c2ca: 681b ldr r3, [r3, #0] 800c2cc: f003 0304 and.w r3, r3, #4 800c2d0: 2b00 cmp r3, #0 800c2d2: d010 beq.n 800c2f6 { #if defined (RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 800c2d4: 687b ldr r3, [r7, #4] 800c2d6: 691a ldr r2, [r3, #16] 800c2d8: 4b7b ldr r3, [pc, #492] @ (800c4c8 ) 800c2da: 699b ldr r3, [r3, #24] 800c2dc: f003 0370 and.w r3, r3, #112 @ 0x70 800c2e0: 429a cmp r2, r3 800c2e2: d908 bls.n 800c2f6 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 800c2e4: 4b78 ldr r3, [pc, #480] @ (800c4c8 ) 800c2e6: 699b ldr r3, [r3, #24] 800c2e8: f023 0270 bic.w r2, r3, #112 @ 0x70 800c2ec: 687b ldr r3, [r7, #4] 800c2ee: 691b ldr r3, [r3, #16] 800c2f0: 4975 ldr r1, [pc, #468] @ (800c4c8 ) 800c2f2: 4313 orrs r3, r2 800c2f4: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800c2f6: 687b ldr r3, [r7, #4] 800c2f8: 681b ldr r3, [r3, #0] 800c2fa: f003 0308 and.w r3, r3, #8 800c2fe: 2b00 cmp r3, #0 800c300: d010 beq.n 800c324 { #if defined (RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800c302: 687b ldr r3, [r7, #4] 800c304: 695a ldr r2, [r3, #20] 800c306: 4b70 ldr r3, [pc, #448] @ (800c4c8 ) 800c308: 69db ldr r3, [r3, #28] 800c30a: f003 0370 and.w r3, r3, #112 @ 0x70 800c30e: 429a cmp r2, r3 800c310: d908 bls.n 800c324 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800c312: 4b6d ldr r3, [pc, #436] @ (800c4c8 ) 800c314: 69db ldr r3, [r3, #28] 800c316: f023 0270 bic.w r2, r3, #112 @ 0x70 800c31a: 687b ldr r3, [r7, #4] 800c31c: 695b ldr r3, [r3, #20] 800c31e: 496a ldr r1, [pc, #424] @ (800c4c8 ) 800c320: 4313 orrs r3, r2 800c322: 61cb str r3, [r1, #28] MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800c324: 687b ldr r3, [r7, #4] 800c326: 681b ldr r3, [r3, #0] 800c328: f003 0310 and.w r3, r3, #16 800c32c: 2b00 cmp r3, #0 800c32e: d010 beq.n 800c352 { #if defined(RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800c330: 687b ldr r3, [r7, #4] 800c332: 699a ldr r2, [r3, #24] 800c334: 4b64 ldr r3, [pc, #400] @ (800c4c8 ) 800c336: 69db ldr r3, [r3, #28] 800c338: f403 63e0 and.w r3, r3, #1792 @ 0x700 800c33c: 429a cmp r2, r3 800c33e: d908 bls.n 800c352 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800c340: 4b61 ldr r3, [pc, #388] @ (800c4c8 ) 800c342: 69db ldr r3, [r3, #28] 800c344: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800c348: 687b ldr r3, [r7, #4] 800c34a: 699b ldr r3, [r3, #24] 800c34c: 495e ldr r1, [pc, #376] @ (800c4c8 ) 800c34e: 4313 orrs r3, r2 800c350: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800c352: 687b ldr r3, [r7, #4] 800c354: 681b ldr r3, [r3, #0] 800c356: f003 0320 and.w r3, r3, #32 800c35a: 2b00 cmp r3, #0 800c35c: d010 beq.n 800c380 { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800c35e: 687b ldr r3, [r7, #4] 800c360: 69da ldr r2, [r3, #28] 800c362: 4b59 ldr r3, [pc, #356] @ (800c4c8 ) 800c364: 6a1b ldr r3, [r3, #32] 800c366: f003 0370 and.w r3, r3, #112 @ 0x70 800c36a: 429a cmp r2, r3 800c36c: d908 bls.n 800c380 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800c36e: 4b56 ldr r3, [pc, #344] @ (800c4c8 ) 800c370: 6a1b ldr r3, [r3, #32] 800c372: f023 0270 bic.w r2, r3, #112 @ 0x70 800c376: 687b ldr r3, [r7, #4] 800c378: 69db ldr r3, [r3, #28] 800c37a: 4953 ldr r1, [pc, #332] @ (800c4c8 ) 800c37c: 4313 orrs r3, r2 800c37e: 620b str r3, [r1, #32] } #endif } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800c380: 687b ldr r3, [r7, #4] 800c382: 681b ldr r3, [r3, #0] 800c384: f003 0302 and.w r3, r3, #2 800c388: 2b00 cmp r3, #0 800c38a: d010 beq.n 800c3ae { #if defined (RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800c38c: 687b ldr r3, [r7, #4] 800c38e: 68da ldr r2, [r3, #12] 800c390: 4b4d ldr r3, [pc, #308] @ (800c4c8 ) 800c392: 699b ldr r3, [r3, #24] 800c394: f003 030f and.w r3, r3, #15 800c398: 429a cmp r2, r3 800c39a: d908 bls.n 800c3ae { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800c39c: 4b4a ldr r3, [pc, #296] @ (800c4c8 ) 800c39e: 699b ldr r3, [r3, #24] 800c3a0: f023 020f bic.w r2, r3, #15 800c3a4: 687b ldr r3, [r7, #4] 800c3a6: 68db ldr r3, [r3, #12] 800c3a8: 4947 ldr r1, [pc, #284] @ (800c4c8 ) 800c3aa: 4313 orrs r3, r2 800c3ac: 618b str r3, [r1, #24] } #endif } /*------------------------- SYSCLK Configuration -------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800c3ae: 687b ldr r3, [r7, #4] 800c3b0: 681b ldr r3, [r3, #0] 800c3b2: f003 0301 and.w r3, r3, #1 800c3b6: 2b00 cmp r3, #0 800c3b8: d055 beq.n 800c466 { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_D1CFGR_D1CPRE) MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); 800c3ba: 4b43 ldr r3, [pc, #268] @ (800c4c8 ) 800c3bc: 699b ldr r3, [r3, #24] 800c3be: f423 6270 bic.w r2, r3, #3840 @ 0xf00 800c3c2: 687b ldr r3, [r7, #4] 800c3c4: 689b ldr r3, [r3, #8] 800c3c6: 4940 ldr r1, [pc, #256] @ (800c4c8 ) 800c3c8: 4313 orrs r3, r2 800c3ca: 618b str r3, [r1, #24] #else MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); #endif /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800c3cc: 687b ldr r3, [r7, #4] 800c3ce: 685b ldr r3, [r3, #4] 800c3d0: 2b02 cmp r3, #2 800c3d2: d107 bne.n 800c3e4 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800c3d4: 4b3c ldr r3, [pc, #240] @ (800c4c8 ) 800c3d6: 681b ldr r3, [r3, #0] 800c3d8: f403 3300 and.w r3, r3, #131072 @ 0x20000 800c3dc: 2b00 cmp r3, #0 800c3de: d121 bne.n 800c424 { return HAL_ERROR; 800c3e0: 2301 movs r3, #1 800c3e2: e0f6 b.n 800c5d2 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800c3e4: 687b ldr r3, [r7, #4] 800c3e6: 685b ldr r3, [r3, #4] 800c3e8: 2b03 cmp r3, #3 800c3ea: d107 bne.n 800c3fc { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800c3ec: 4b36 ldr r3, [pc, #216] @ (800c4c8 ) 800c3ee: 681b ldr r3, [r3, #0] 800c3f0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800c3f4: 2b00 cmp r3, #0 800c3f6: d115 bne.n 800c424 { return HAL_ERROR; 800c3f8: 2301 movs r3, #1 800c3fa: e0ea b.n 800c5d2 } } /* CSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 800c3fc: 687b ldr r3, [r7, #4] 800c3fe: 685b ldr r3, [r3, #4] 800c400: 2b01 cmp r3, #1 800c402: d107 bne.n 800c414 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800c404: 4b30 ldr r3, [pc, #192] @ (800c4c8 ) 800c406: 681b ldr r3, [r3, #0] 800c408: f403 7380 and.w r3, r3, #256 @ 0x100 800c40c: 2b00 cmp r3, #0 800c40e: d109 bne.n 800c424 { return HAL_ERROR; 800c410: 2301 movs r3, #1 800c412: e0de b.n 800c5d2 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800c414: 4b2c ldr r3, [pc, #176] @ (800c4c8 ) 800c416: 681b ldr r3, [r3, #0] 800c418: f003 0304 and.w r3, r3, #4 800c41c: 2b00 cmp r3, #0 800c41e: d101 bne.n 800c424 { return HAL_ERROR; 800c420: 2301 movs r3, #1 800c422: e0d6 b.n 800c5d2 } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 800c424: 4b28 ldr r3, [pc, #160] @ (800c4c8 ) 800c426: 691b ldr r3, [r3, #16] 800c428: f023 0207 bic.w r2, r3, #7 800c42c: 687b ldr r3, [r7, #4] 800c42e: 685b ldr r3, [r3, #4] 800c430: 4925 ldr r1, [pc, #148] @ (800c4c8 ) 800c432: 4313 orrs r3, r2 800c434: 610b str r3, [r1, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c436: f7f9 fd35 bl 8005ea4 800c43a: 6178 str r0, [r7, #20] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800c43c: e00a b.n 800c454 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800c43e: f7f9 fd31 bl 8005ea4 800c442: 4602 mov r2, r0 800c444: 697b ldr r3, [r7, #20] 800c446: 1ad3 subs r3, r2, r3 800c448: f241 3288 movw r2, #5000 @ 0x1388 800c44c: 4293 cmp r3, r2 800c44e: d901 bls.n 800c454 { return HAL_TIMEOUT; 800c450: 2303 movs r3, #3 800c452: e0be b.n 800c5d2 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800c454: 4b1c ldr r3, [pc, #112] @ (800c4c8 ) 800c456: 691b ldr r3, [r3, #16] 800c458: f003 0238 and.w r2, r3, #56 @ 0x38 800c45c: 687b ldr r3, [r7, #4] 800c45e: 685b ldr r3, [r3, #4] 800c460: 00db lsls r3, r3, #3 800c462: 429a cmp r2, r3 800c464: d1eb bne.n 800c43e } /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800c466: 687b ldr r3, [r7, #4] 800c468: 681b ldr r3, [r3, #0] 800c46a: f003 0302 and.w r3, r3, #2 800c46e: 2b00 cmp r3, #0 800c470: d010 beq.n 800c494 { #if defined(RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800c472: 687b ldr r3, [r7, #4] 800c474: 68da ldr r2, [r3, #12] 800c476: 4b14 ldr r3, [pc, #80] @ (800c4c8 ) 800c478: 699b ldr r3, [r3, #24] 800c47a: f003 030f and.w r3, r3, #15 800c47e: 429a cmp r2, r3 800c480: d208 bcs.n 800c494 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800c482: 4b11 ldr r3, [pc, #68] @ (800c4c8 ) 800c484: 699b ldr r3, [r3, #24] 800c486: f023 020f bic.w r2, r3, #15 800c48a: 687b ldr r3, [r7, #4] 800c48c: 68db ldr r3, [r3, #12] 800c48e: 490e ldr r1, [pc, #56] @ (800c4c8 ) 800c490: 4313 orrs r3, r2 800c492: 618b str r3, [r1, #24] } #endif } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 800c494: 4b0b ldr r3, [pc, #44] @ (800c4c4 ) 800c496: 681b ldr r3, [r3, #0] 800c498: f003 030f and.w r3, r3, #15 800c49c: 683a ldr r2, [r7, #0] 800c49e: 429a cmp r2, r3 800c4a0: d214 bcs.n 800c4cc { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800c4a2: 4b08 ldr r3, [pc, #32] @ (800c4c4 ) 800c4a4: 681b ldr r3, [r3, #0] 800c4a6: f023 020f bic.w r2, r3, #15 800c4aa: 4906 ldr r1, [pc, #24] @ (800c4c4 ) 800c4ac: 683b ldr r3, [r7, #0] 800c4ae: 4313 orrs r3, r2 800c4b0: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800c4b2: 4b04 ldr r3, [pc, #16] @ (800c4c4 ) 800c4b4: 681b ldr r3, [r3, #0] 800c4b6: f003 030f and.w r3, r3, #15 800c4ba: 683a ldr r2, [r7, #0] 800c4bc: 429a cmp r2, r3 800c4be: d005 beq.n 800c4cc { return HAL_ERROR; 800c4c0: 2301 movs r3, #1 800c4c2: e086 b.n 800c5d2 800c4c4: 52002000 .word 0x52002000 800c4c8: 58024400 .word 0x58024400 } } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 800c4cc: 687b ldr r3, [r7, #4] 800c4ce: 681b ldr r3, [r3, #0] 800c4d0: f003 0304 and.w r3, r3, #4 800c4d4: 2b00 cmp r3, #0 800c4d6: d010 beq.n 800c4fa { #if defined(RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 800c4d8: 687b ldr r3, [r7, #4] 800c4da: 691a ldr r2, [r3, #16] 800c4dc: 4b3f ldr r3, [pc, #252] @ (800c5dc ) 800c4de: 699b ldr r3, [r3, #24] 800c4e0: f003 0370 and.w r3, r3, #112 @ 0x70 800c4e4: 429a cmp r2, r3 800c4e6: d208 bcs.n 800c4fa { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 800c4e8: 4b3c ldr r3, [pc, #240] @ (800c5dc ) 800c4ea: 699b ldr r3, [r3, #24] 800c4ec: f023 0270 bic.w r2, r3, #112 @ 0x70 800c4f0: 687b ldr r3, [r7, #4] 800c4f2: 691b ldr r3, [r3, #16] 800c4f4: 4939 ldr r1, [pc, #228] @ (800c5dc ) 800c4f6: 4313 orrs r3, r2 800c4f8: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800c4fa: 687b ldr r3, [r7, #4] 800c4fc: 681b ldr r3, [r3, #0] 800c4fe: f003 0308 and.w r3, r3, #8 800c502: 2b00 cmp r3, #0 800c504: d010 beq.n 800c528 { #if defined(RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800c506: 687b ldr r3, [r7, #4] 800c508: 695a ldr r2, [r3, #20] 800c50a: 4b34 ldr r3, [pc, #208] @ (800c5dc ) 800c50c: 69db ldr r3, [r3, #28] 800c50e: f003 0370 and.w r3, r3, #112 @ 0x70 800c512: 429a cmp r2, r3 800c514: d208 bcs.n 800c528 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800c516: 4b31 ldr r3, [pc, #196] @ (800c5dc ) 800c518: 69db ldr r3, [r3, #28] 800c51a: f023 0270 bic.w r2, r3, #112 @ 0x70 800c51e: 687b ldr r3, [r7, #4] 800c520: 695b ldr r3, [r3, #20] 800c522: 492e ldr r1, [pc, #184] @ (800c5dc ) 800c524: 4313 orrs r3, r2 800c526: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800c528: 687b ldr r3, [r7, #4] 800c52a: 681b ldr r3, [r3, #0] 800c52c: f003 0310 and.w r3, r3, #16 800c530: 2b00 cmp r3, #0 800c532: d010 beq.n 800c556 { #if defined (RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800c534: 687b ldr r3, [r7, #4] 800c536: 699a ldr r2, [r3, #24] 800c538: 4b28 ldr r3, [pc, #160] @ (800c5dc ) 800c53a: 69db ldr r3, [r3, #28] 800c53c: f403 63e0 and.w r3, r3, #1792 @ 0x700 800c540: 429a cmp r2, r3 800c542: d208 bcs.n 800c556 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800c544: 4b25 ldr r3, [pc, #148] @ (800c5dc ) 800c546: 69db ldr r3, [r3, #28] 800c548: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800c54c: 687b ldr r3, [r7, #4] 800c54e: 699b ldr r3, [r3, #24] 800c550: 4922 ldr r1, [pc, #136] @ (800c5dc ) 800c552: 4313 orrs r3, r2 800c554: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800c556: 687b ldr r3, [r7, #4] 800c558: 681b ldr r3, [r3, #0] 800c55a: f003 0320 and.w r3, r3, #32 800c55e: 2b00 cmp r3, #0 800c560: d010 beq.n 800c584 { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800c562: 687b ldr r3, [r7, #4] 800c564: 69da ldr r2, [r3, #28] 800c566: 4b1d ldr r3, [pc, #116] @ (800c5dc ) 800c568: 6a1b ldr r3, [r3, #32] 800c56a: f003 0370 and.w r3, r3, #112 @ 0x70 800c56e: 429a cmp r2, r3 800c570: d208 bcs.n 800c584 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800c572: 4b1a ldr r3, [pc, #104] @ (800c5dc ) 800c574: 6a1b ldr r3, [r3, #32] 800c576: f023 0270 bic.w r2, r3, #112 @ 0x70 800c57a: 687b ldr r3, [r7, #4] 800c57c: 69db ldr r3, [r3, #28] 800c57e: 4917 ldr r1, [pc, #92] @ (800c5dc ) 800c580: 4313 orrs r3, r2 800c582: 620b str r3, [r1, #32] #endif } /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 800c584: f000 f834 bl 800c5f0 800c588: 4602 mov r2, r0 800c58a: 4b14 ldr r3, [pc, #80] @ (800c5dc ) 800c58c: 699b ldr r3, [r3, #24] 800c58e: 0a1b lsrs r3, r3, #8 800c590: f003 030f and.w r3, r3, #15 800c594: 4912 ldr r1, [pc, #72] @ (800c5e0 ) 800c596: 5ccb ldrb r3, [r1, r3] 800c598: f003 031f and.w r3, r3, #31 800c59c: fa22 f303 lsr.w r3, r2, r3 800c5a0: 613b str r3, [r7, #16] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800c5a2: 4b0e ldr r3, [pc, #56] @ (800c5dc ) 800c5a4: 699b ldr r3, [r3, #24] 800c5a6: f003 030f and.w r3, r3, #15 800c5aa: 4a0d ldr r2, [pc, #52] @ (800c5e0 ) 800c5ac: 5cd3 ldrb r3, [r2, r3] 800c5ae: f003 031f and.w r3, r3, #31 800c5b2: 693a ldr r2, [r7, #16] 800c5b4: fa22 f303 lsr.w r3, r2, r3 800c5b8: 4a0a ldr r2, [pc, #40] @ (800c5e4 ) 800c5ba: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 800c5bc: 4a0a ldr r2, [pc, #40] @ (800c5e8 ) 800c5be: 693b ldr r3, [r7, #16] 800c5c0: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick(uwTickPrio); 800c5c2: 4b0a ldr r3, [pc, #40] @ (800c5ec ) 800c5c4: 681b ldr r3, [r3, #0] 800c5c6: 4618 mov r0, r3 800c5c8: f7f8 f89c bl 8004704 800c5cc: 4603 mov r3, r0 800c5ce: 73fb strb r3, [r7, #15] return halstatus; 800c5d0: 7bfb ldrb r3, [r7, #15] } 800c5d2: 4618 mov r0, r3 800c5d4: 3718 adds r7, #24 800c5d6: 46bd mov sp, r7 800c5d8: bd80 pop {r7, pc} 800c5da: bf00 nop 800c5dc: 58024400 .word 0x58024400 800c5e0: 0801878c .word 0x0801878c 800c5e4: 24000038 .word 0x24000038 800c5e8: 24000034 .word 0x24000034 800c5ec: 2400003c .word 0x2400003c 0800c5f0 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800c5f0: b480 push {r7} 800c5f2: b089 sub sp, #36 @ 0x24 800c5f4: af00 add r7, sp, #0 float_t fracn1, pllvco; uint32_t sysclockfreq; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 800c5f6: 4bb3 ldr r3, [pc, #716] @ (800c8c4 ) 800c5f8: 691b ldr r3, [r3, #16] 800c5fa: f003 0338 and.w r3, r3, #56 @ 0x38 800c5fe: 2b18 cmp r3, #24 800c600: f200 8155 bhi.w 800c8ae 800c604: a201 add r2, pc, #4 @ (adr r2, 800c60c ) 800c606: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c60a: bf00 nop 800c60c: 0800c671 .word 0x0800c671 800c610: 0800c8af .word 0x0800c8af 800c614: 0800c8af .word 0x0800c8af 800c618: 0800c8af .word 0x0800c8af 800c61c: 0800c8af .word 0x0800c8af 800c620: 0800c8af .word 0x0800c8af 800c624: 0800c8af .word 0x0800c8af 800c628: 0800c8af .word 0x0800c8af 800c62c: 0800c697 .word 0x0800c697 800c630: 0800c8af .word 0x0800c8af 800c634: 0800c8af .word 0x0800c8af 800c638: 0800c8af .word 0x0800c8af 800c63c: 0800c8af .word 0x0800c8af 800c640: 0800c8af .word 0x0800c8af 800c644: 0800c8af .word 0x0800c8af 800c648: 0800c8af .word 0x0800c8af 800c64c: 0800c69d .word 0x0800c69d 800c650: 0800c8af .word 0x0800c8af 800c654: 0800c8af .word 0x0800c8af 800c658: 0800c8af .word 0x0800c8af 800c65c: 0800c8af .word 0x0800c8af 800c660: 0800c8af .word 0x0800c8af 800c664: 0800c8af .word 0x0800c8af 800c668: 0800c8af .word 0x0800c8af 800c66c: 0800c6a3 .word 0x0800c6a3 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800c670: 4b94 ldr r3, [pc, #592] @ (800c8c4 ) 800c672: 681b ldr r3, [r3, #0] 800c674: f003 0320 and.w r3, r3, #32 800c678: 2b00 cmp r3, #0 800c67a: d009 beq.n 800c690 { sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800c67c: 4b91 ldr r3, [pc, #580] @ (800c8c4 ) 800c67e: 681b ldr r3, [r3, #0] 800c680: 08db lsrs r3, r3, #3 800c682: f003 0303 and.w r3, r3, #3 800c686: 4a90 ldr r2, [pc, #576] @ (800c8c8 ) 800c688: fa22 f303 lsr.w r3, r2, r3 800c68c: 61bb str r3, [r7, #24] else { sysclockfreq = (uint32_t) HSI_VALUE; } break; 800c68e: e111 b.n 800c8b4 sysclockfreq = (uint32_t) HSI_VALUE; 800c690: 4b8d ldr r3, [pc, #564] @ (800c8c8 ) 800c692: 61bb str r3, [r7, #24] break; 800c694: e10e b.n 800c8b4 case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ sysclockfreq = CSI_VALUE; 800c696: 4b8d ldr r3, [pc, #564] @ (800c8cc ) 800c698: 61bb str r3, [r7, #24] break; 800c69a: e10b b.n 800c8b4 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 800c69c: 4b8c ldr r3, [pc, #560] @ (800c8d0 ) 800c69e: 61bb str r3, [r7, #24] break; 800c6a0: e108 b.n 800c8b4 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800c6a2: 4b88 ldr r3, [pc, #544] @ (800c8c4 ) 800c6a4: 6a9b ldr r3, [r3, #40] @ 0x28 800c6a6: f003 0303 and.w r3, r3, #3 800c6aa: 617b str r3, [r7, #20] pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; 800c6ac: 4b85 ldr r3, [pc, #532] @ (800c8c4 ) 800c6ae: 6a9b ldr r3, [r3, #40] @ 0x28 800c6b0: 091b lsrs r3, r3, #4 800c6b2: f003 033f and.w r3, r3, #63 @ 0x3f 800c6b6: 613b str r3, [r7, #16] pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); 800c6b8: 4b82 ldr r3, [pc, #520] @ (800c8c4 ) 800c6ba: 6adb ldr r3, [r3, #44] @ 0x2c 800c6bc: f003 0301 and.w r3, r3, #1 800c6c0: 60fb str r3, [r7, #12] fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800c6c2: 4b80 ldr r3, [pc, #512] @ (800c8c4 ) 800c6c4: 6b5b ldr r3, [r3, #52] @ 0x34 800c6c6: 08db lsrs r3, r3, #3 800c6c8: f3c3 030c ubfx r3, r3, #0, #13 800c6cc: 68fa ldr r2, [r7, #12] 800c6ce: fb02 f303 mul.w r3, r2, r3 800c6d2: ee07 3a90 vmov s15, r3 800c6d6: eef8 7a67 vcvt.f32.u32 s15, s15 800c6da: edc7 7a02 vstr s15, [r7, #8] if (pllm != 0U) 800c6de: 693b ldr r3, [r7, #16] 800c6e0: 2b00 cmp r3, #0 800c6e2: f000 80e1 beq.w 800c8a8 800c6e6: 697b ldr r3, [r7, #20] 800c6e8: 2b02 cmp r3, #2 800c6ea: f000 8083 beq.w 800c7f4 800c6ee: 697b ldr r3, [r7, #20] 800c6f0: 2b02 cmp r3, #2 800c6f2: f200 80a1 bhi.w 800c838 800c6f6: 697b ldr r3, [r7, #20] 800c6f8: 2b00 cmp r3, #0 800c6fa: d003 beq.n 800c704 800c6fc: 697b ldr r3, [r7, #20] 800c6fe: 2b01 cmp r3, #1 800c700: d056 beq.n 800c7b0 800c702: e099 b.n 800c838 { switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800c704: 4b6f ldr r3, [pc, #444] @ (800c8c4 ) 800c706: 681b ldr r3, [r3, #0] 800c708: f003 0320 and.w r3, r3, #32 800c70c: 2b00 cmp r3, #0 800c70e: d02d beq.n 800c76c { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800c710: 4b6c ldr r3, [pc, #432] @ (800c8c4 ) 800c712: 681b ldr r3, [r3, #0] 800c714: 08db lsrs r3, r3, #3 800c716: f003 0303 and.w r3, r3, #3 800c71a: 4a6b ldr r2, [pc, #428] @ (800c8c8 ) 800c71c: fa22 f303 lsr.w r3, r2, r3 800c720: 607b str r3, [r7, #4] pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c722: 687b ldr r3, [r7, #4] 800c724: ee07 3a90 vmov s15, r3 800c728: eef8 6a67 vcvt.f32.u32 s13, s15 800c72c: 693b ldr r3, [r7, #16] 800c72e: ee07 3a90 vmov s15, r3 800c732: eef8 7a67 vcvt.f32.u32 s15, s15 800c736: ee86 7aa7 vdiv.f32 s14, s13, s15 800c73a: 4b62 ldr r3, [pc, #392] @ (800c8c4 ) 800c73c: 6b1b ldr r3, [r3, #48] @ 0x30 800c73e: f3c3 0308 ubfx r3, r3, #0, #9 800c742: ee07 3a90 vmov s15, r3 800c746: eef8 6a67 vcvt.f32.u32 s13, s15 800c74a: ed97 6a02 vldr s12, [r7, #8] 800c74e: eddf 5a61 vldr s11, [pc, #388] @ 800c8d4 800c752: eec6 7a25 vdiv.f32 s15, s12, s11 800c756: ee76 7aa7 vadd.f32 s15, s13, s15 800c75a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c75e: ee77 7aa6 vadd.f32 s15, s15, s13 800c762: ee67 7a27 vmul.f32 s15, s14, s15 800c766: edc7 7a07 vstr s15, [r7, #28] } else { pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 800c76a: e087 b.n 800c87c pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c76c: 693b ldr r3, [r7, #16] 800c76e: ee07 3a90 vmov s15, r3 800c772: eef8 7a67 vcvt.f32.u32 s15, s15 800c776: eddf 6a58 vldr s13, [pc, #352] @ 800c8d8 800c77a: ee86 7aa7 vdiv.f32 s14, s13, s15 800c77e: 4b51 ldr r3, [pc, #324] @ (800c8c4 ) 800c780: 6b1b ldr r3, [r3, #48] @ 0x30 800c782: f3c3 0308 ubfx r3, r3, #0, #9 800c786: ee07 3a90 vmov s15, r3 800c78a: eef8 6a67 vcvt.f32.u32 s13, s15 800c78e: ed97 6a02 vldr s12, [r7, #8] 800c792: eddf 5a50 vldr s11, [pc, #320] @ 800c8d4 800c796: eec6 7a25 vdiv.f32 s15, s12, s11 800c79a: ee76 7aa7 vadd.f32 s15, s13, s15 800c79e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c7a2: ee77 7aa6 vadd.f32 s15, s15, s13 800c7a6: ee67 7a27 vmul.f32 s15, s14, s15 800c7aa: edc7 7a07 vstr s15, [r7, #28] break; 800c7ae: e065 b.n 800c87c case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c7b0: 693b ldr r3, [r7, #16] 800c7b2: ee07 3a90 vmov s15, r3 800c7b6: eef8 7a67 vcvt.f32.u32 s15, s15 800c7ba: eddf 6a48 vldr s13, [pc, #288] @ 800c8dc 800c7be: ee86 7aa7 vdiv.f32 s14, s13, s15 800c7c2: 4b40 ldr r3, [pc, #256] @ (800c8c4 ) 800c7c4: 6b1b ldr r3, [r3, #48] @ 0x30 800c7c6: f3c3 0308 ubfx r3, r3, #0, #9 800c7ca: ee07 3a90 vmov s15, r3 800c7ce: eef8 6a67 vcvt.f32.u32 s13, s15 800c7d2: ed97 6a02 vldr s12, [r7, #8] 800c7d6: eddf 5a3f vldr s11, [pc, #252] @ 800c8d4 800c7da: eec6 7a25 vdiv.f32 s15, s12, s11 800c7de: ee76 7aa7 vadd.f32 s15, s13, s15 800c7e2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c7e6: ee77 7aa6 vadd.f32 s15, s15, s13 800c7ea: ee67 7a27 vmul.f32 s15, s14, s15 800c7ee: edc7 7a07 vstr s15, [r7, #28] break; 800c7f2: e043 b.n 800c87c case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c7f4: 693b ldr r3, [r7, #16] 800c7f6: ee07 3a90 vmov s15, r3 800c7fa: eef8 7a67 vcvt.f32.u32 s15, s15 800c7fe: eddf 6a38 vldr s13, [pc, #224] @ 800c8e0 800c802: ee86 7aa7 vdiv.f32 s14, s13, s15 800c806: 4b2f ldr r3, [pc, #188] @ (800c8c4 ) 800c808: 6b1b ldr r3, [r3, #48] @ 0x30 800c80a: f3c3 0308 ubfx r3, r3, #0, #9 800c80e: ee07 3a90 vmov s15, r3 800c812: eef8 6a67 vcvt.f32.u32 s13, s15 800c816: ed97 6a02 vldr s12, [r7, #8] 800c81a: eddf 5a2e vldr s11, [pc, #184] @ 800c8d4 800c81e: eec6 7a25 vdiv.f32 s15, s12, s11 800c822: ee76 7aa7 vadd.f32 s15, s13, s15 800c826: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c82a: ee77 7aa6 vadd.f32 s15, s15, s13 800c82e: ee67 7a27 vmul.f32 s15, s14, s15 800c832: edc7 7a07 vstr s15, [r7, #28] break; 800c836: e021 b.n 800c87c default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c838: 693b ldr r3, [r7, #16] 800c83a: ee07 3a90 vmov s15, r3 800c83e: eef8 7a67 vcvt.f32.u32 s15, s15 800c842: eddf 6a26 vldr s13, [pc, #152] @ 800c8dc 800c846: ee86 7aa7 vdiv.f32 s14, s13, s15 800c84a: 4b1e ldr r3, [pc, #120] @ (800c8c4 ) 800c84c: 6b1b ldr r3, [r3, #48] @ 0x30 800c84e: f3c3 0308 ubfx r3, r3, #0, #9 800c852: ee07 3a90 vmov s15, r3 800c856: eef8 6a67 vcvt.f32.u32 s13, s15 800c85a: ed97 6a02 vldr s12, [r7, #8] 800c85e: eddf 5a1d vldr s11, [pc, #116] @ 800c8d4 800c862: eec6 7a25 vdiv.f32 s15, s12, s11 800c866: ee76 7aa7 vadd.f32 s15, s13, s15 800c86a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c86e: ee77 7aa6 vadd.f32 s15, s15, s13 800c872: ee67 7a27 vmul.f32 s15, s14, s15 800c876: edc7 7a07 vstr s15, [r7, #28] break; 800c87a: bf00 nop } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; 800c87c: 4b11 ldr r3, [pc, #68] @ (800c8c4 ) 800c87e: 6b1b ldr r3, [r3, #48] @ 0x30 800c880: 0a5b lsrs r3, r3, #9 800c882: f003 037f and.w r3, r3, #127 @ 0x7f 800c886: 3301 adds r3, #1 800c888: 603b str r3, [r7, #0] sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); 800c88a: 683b ldr r3, [r7, #0] 800c88c: ee07 3a90 vmov s15, r3 800c890: eeb8 7a67 vcvt.f32.u32 s14, s15 800c894: edd7 6a07 vldr s13, [r7, #28] 800c898: eec6 7a87 vdiv.f32 s15, s13, s14 800c89c: eefc 7ae7 vcvt.u32.f32 s15, s15 800c8a0: ee17 3a90 vmov r3, s15 800c8a4: 61bb str r3, [r7, #24] } else { sysclockfreq = 0U; } break; 800c8a6: e005 b.n 800c8b4 sysclockfreq = 0U; 800c8a8: 2300 movs r3, #0 800c8aa: 61bb str r3, [r7, #24] break; 800c8ac: e002 b.n 800c8b4 default: sysclockfreq = CSI_VALUE; 800c8ae: 4b07 ldr r3, [pc, #28] @ (800c8cc ) 800c8b0: 61bb str r3, [r7, #24] break; 800c8b2: bf00 nop } return sysclockfreq; 800c8b4: 69bb ldr r3, [r7, #24] } 800c8b6: 4618 mov r0, r3 800c8b8: 3724 adds r7, #36 @ 0x24 800c8ba: 46bd mov sp, r7 800c8bc: f85d 7b04 ldr.w r7, [sp], #4 800c8c0: 4770 bx lr 800c8c2: bf00 nop 800c8c4: 58024400 .word 0x58024400 800c8c8: 03d09000 .word 0x03d09000 800c8cc: 003d0900 .word 0x003d0900 800c8d0: 017d7840 .word 0x017d7840 800c8d4: 46000000 .word 0x46000000 800c8d8: 4c742400 .word 0x4c742400 800c8dc: 4a742400 .word 0x4a742400 800c8e0: 4bbebc20 .word 0x4bbebc20 0800c8e4 : * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 800c8e4: b580 push {r7, lr} 800c8e6: b082 sub sp, #8 800c8e8: af00 add r7, sp, #0 uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 800c8ea: f7ff fe81 bl 800c5f0 800c8ee: 4602 mov r2, r0 800c8f0: 4b10 ldr r3, [pc, #64] @ (800c934 ) 800c8f2: 699b ldr r3, [r3, #24] 800c8f4: 0a1b lsrs r3, r3, #8 800c8f6: f003 030f and.w r3, r3, #15 800c8fa: 490f ldr r1, [pc, #60] @ (800c938 ) 800c8fc: 5ccb ldrb r3, [r1, r3] 800c8fe: f003 031f and.w r3, r3, #31 800c902: fa22 f303 lsr.w r3, r2, r3 800c906: 607b str r3, [r7, #4] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800c908: 4b0a ldr r3, [pc, #40] @ (800c934 ) 800c90a: 699b ldr r3, [r3, #24] 800c90c: f003 030f and.w r3, r3, #15 800c910: 4a09 ldr r2, [pc, #36] @ (800c938 ) 800c912: 5cd3 ldrb r3, [r2, r3] 800c914: f003 031f and.w r3, r3, #31 800c918: 687a ldr r2, [r7, #4] 800c91a: fa22 f303 lsr.w r3, r2, r3 800c91e: 4a07 ldr r2, [pc, #28] @ (800c93c ) 800c920: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 800c922: 4a07 ldr r2, [pc, #28] @ (800c940 ) 800c924: 687b ldr r3, [r7, #4] 800c926: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ return SystemD2Clock; 800c928: 4b04 ldr r3, [pc, #16] @ (800c93c ) 800c92a: 681b ldr r3, [r3, #0] } 800c92c: 4618 mov r0, r3 800c92e: 3708 adds r7, #8 800c930: 46bd mov sp, r7 800c932: bd80 pop {r7, pc} 800c934: 58024400 .word 0x58024400 800c938: 0801878c .word 0x0801878c 800c93c: 24000038 .word 0x24000038 800c940: 24000034 .word 0x24000034 0800c944 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 800c944: b580 push {r7, lr} 800c946: af00 add r7, sp, #0 #if defined (RCC_D2CFGR_D2PPRE1) /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); 800c948: f7ff ffcc bl 800c8e4 800c94c: 4602 mov r2, r0 800c94e: 4b06 ldr r3, [pc, #24] @ (800c968 ) 800c950: 69db ldr r3, [r3, #28] 800c952: 091b lsrs r3, r3, #4 800c954: f003 0307 and.w r3, r3, #7 800c958: 4904 ldr r1, [pc, #16] @ (800c96c ) 800c95a: 5ccb ldrb r3, [r1, r3] 800c95c: f003 031f and.w r3, r3, #31 800c960: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); #endif } 800c964: 4618 mov r0, r3 800c966: bd80 pop {r7, pc} 800c968: 58024400 .word 0x58024400 800c96c: 0801878c .word 0x0801878c 0800c970 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 800c970: b580 push {r7, lr} 800c972: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ #if defined(RCC_D2CFGR_D2PPRE2) return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); 800c974: f7ff ffb6 bl 800c8e4 800c978: 4602 mov r2, r0 800c97a: 4b06 ldr r3, [pc, #24] @ (800c994 ) 800c97c: 69db ldr r3, [r3, #28] 800c97e: 0a1b lsrs r3, r3, #8 800c980: f003 0307 and.w r3, r3, #7 800c984: 4904 ldr r1, [pc, #16] @ (800c998 ) 800c986: 5ccb ldrb r3, [r1, r3] 800c988: f003 031f and.w r3, r3, #31 800c98c: fa22 f303 lsr.w r3, r2, r3 #else return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); #endif } 800c990: 4618 mov r0, r3 800c992: bd80 pop {r7, pc} 800c994: 58024400 .word 0x58024400 800c998: 0801878c .word 0x0801878c 0800c99c : * will be configured. * @param pFLatency: Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 800c99c: b480 push {r7} 800c99e: b083 sub sp, #12 800c9a0: af00 add r7, sp, #0 800c9a2: 6078 str r0, [r7, #4] 800c9a4: 6039 str r1, [r7, #0] /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | 800c9a6: 687b ldr r3, [r7, #4] 800c9a8: 223f movs r2, #63 @ 0x3f 800c9aa: 601a str r2, [r3, #0] RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ; /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 800c9ac: 4b1a ldr r3, [pc, #104] @ (800ca18 ) 800c9ae: 691b ldr r3, [r3, #16] 800c9b0: f003 0207 and.w r2, r3, #7 800c9b4: 687b ldr r3, [r7, #4] 800c9b6: 605a str r2, [r3, #4] #if defined(RCC_D1CFGR_D1CPRE) /* Get the SYSCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE); 800c9b8: 4b17 ldr r3, [pc, #92] @ (800ca18 ) 800c9ba: 699b ldr r3, [r3, #24] 800c9bc: f403 6270 and.w r2, r3, #3840 @ 0xf00 800c9c0: 687b ldr r3, [r7, #4] 800c9c2: 609a str r2, [r3, #8] /* Get the D1HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE); 800c9c4: 4b14 ldr r3, [pc, #80] @ (800ca18 ) 800c9c6: 699b ldr r3, [r3, #24] 800c9c8: f003 020f and.w r2, r3, #15 800c9cc: 687b ldr r3, [r7, #4] 800c9ce: 60da str r2, [r3, #12] /* Get the APB3 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE); 800c9d0: 4b11 ldr r3, [pc, #68] @ (800ca18 ) 800c9d2: 699b ldr r3, [r3, #24] 800c9d4: f003 0270 and.w r2, r3, #112 @ 0x70 800c9d8: 687b ldr r3, [r7, #4] 800c9da: 611a str r2, [r3, #16] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1); 800c9dc: 4b0e ldr r3, [pc, #56] @ (800ca18 ) 800c9de: 69db ldr r3, [r3, #28] 800c9e0: f003 0270 and.w r2, r3, #112 @ 0x70 800c9e4: 687b ldr r3, [r7, #4] 800c9e6: 615a str r2, [r3, #20] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2); 800c9e8: 4b0b ldr r3, [pc, #44] @ (800ca18 ) 800c9ea: 69db ldr r3, [r3, #28] 800c9ec: f403 62e0 and.w r2, r3, #1792 @ 0x700 800c9f0: 687b ldr r3, [r7, #4] 800c9f2: 619a str r2, [r3, #24] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); 800c9f4: 4b08 ldr r3, [pc, #32] @ (800ca18 ) 800c9f6: 6a1b ldr r3, [r3, #32] 800c9f8: f003 0270 and.w r2, r3, #112 @ 0x70 800c9fc: 687b ldr r3, [r7, #4] 800c9fe: 61da str r2, [r3, #28] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE); #endif /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 800ca00: 4b06 ldr r3, [pc, #24] @ (800ca1c ) 800ca02: 681b ldr r3, [r3, #0] 800ca04: f003 020f and.w r2, r3, #15 800ca08: 683b ldr r3, [r7, #0] 800ca0a: 601a str r2, [r3, #0] } 800ca0c: bf00 nop 800ca0e: 370c adds r7, #12 800ca10: 46bd mov sp, r7 800ca12: f85d 7b04 ldr.w r7, [sp], #4 800ca16: 4770 bx lr 800ca18: 58024400 .word 0x58024400 800ca1c: 52002000 .word 0x52002000 0800ca20 : * (*) : Available on some STM32H7 lines only. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 800ca20: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 800ca24: b0c8 sub sp, #288 @ 0x120 800ca26: af00 add r7, sp, #0 800ca28: f8c7 010c str.w r0, [r7, #268] @ 0x10c uint32_t tmpreg; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 800ca2c: 2300 movs r3, #0 800ca2e: f887 311f strb.w r3, [r7, #287] @ 0x11f HAL_StatusTypeDef status = HAL_OK; /* Final status */ 800ca32: 2300 movs r3, #0 800ca34: f887 311e strb.w r3, [r7, #286] @ 0x11e /*---------------------------- SPDIFRX configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 800ca38: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca3c: e9d3 2300 ldrd r2, r3, [r3] 800ca40: f002 6400 and.w r4, r2, #134217728 @ 0x8000000 800ca44: 2500 movs r5, #0 800ca46: ea54 0305 orrs.w r3, r4, r5 800ca4a: d049 beq.n 800cae0 { switch (PeriphClkInit->SpdifrxClockSelection) 800ca4c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca50: 6e9b ldr r3, [r3, #104] @ 0x68 800ca52: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800ca56: d02f beq.n 800cab8 800ca58: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800ca5c: d828 bhi.n 800cab0 800ca5e: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800ca62: d01a beq.n 800ca9a 800ca64: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800ca68: d822 bhi.n 800cab0 800ca6a: 2b00 cmp r3, #0 800ca6c: d003 beq.n 800ca76 800ca6e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800ca72: d007 beq.n 800ca84 800ca74: e01c b.n 800cab0 { case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800ca76: 4bb8 ldr r3, [pc, #736] @ (800cd58 ) 800ca78: 6adb ldr r3, [r3, #44] @ 0x2c 800ca7a: 4ab7 ldr r2, [pc, #732] @ (800cd58 ) 800ca7c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800ca80: 62d3 str r3, [r2, #44] @ 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 800ca82: e01a b.n 800caba case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800ca84: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca88: 3308 adds r3, #8 800ca8a: 2102 movs r1, #2 800ca8c: 4618 mov r0, r3 800ca8e: f002 fb45 bl 800f11c 800ca92: 4603 mov r3, r0 800ca94: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 800ca98: e00f b.n 800caba case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800ca9a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca9e: 3328 adds r3, #40 @ 0x28 800caa0: 2102 movs r1, #2 800caa2: 4618 mov r0, r3 800caa4: f002 fbec bl 800f280 800caa8: 4603 mov r3, r0 800caaa: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 800caae: e004 b.n 800caba /* Internal OSC clock is used as source of SPDIFRX clock*/ /* SPDIFRX clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cab0: 2301 movs r3, #1 800cab2: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cab6: e000 b.n 800caba break; 800cab8: bf00 nop } if (ret == HAL_OK) 800caba: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cabe: 2b00 cmp r3, #0 800cac0: d10a bne.n 800cad8 { /* Set the source of SPDIFRX clock*/ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 800cac2: 4ba5 ldr r3, [pc, #660] @ (800cd58 ) 800cac4: 6d1b ldr r3, [r3, #80] @ 0x50 800cac6: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800caca: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cace: 6e9b ldr r3, [r3, #104] @ 0x68 800cad0: 4aa1 ldr r2, [pc, #644] @ (800cd58 ) 800cad2: 430b orrs r3, r1 800cad4: 6513 str r3, [r2, #80] @ 0x50 800cad6: e003 b.n 800cae0 } else { /* set overall return value */ status = ret; 800cad8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cadc: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 800cae0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cae4: e9d3 2300 ldrd r2, r3, [r3] 800cae8: f402 7880 and.w r8, r2, #256 @ 0x100 800caec: f04f 0900 mov.w r9, #0 800caf0: ea58 0309 orrs.w r3, r8, r9 800caf4: d047 beq.n 800cb86 { switch (PeriphClkInit->Sai1ClockSelection) 800caf6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cafa: 6d9b ldr r3, [r3, #88] @ 0x58 800cafc: 2b04 cmp r3, #4 800cafe: d82a bhi.n 800cb56 800cb00: a201 add r2, pc, #4 @ (adr r2, 800cb08 ) 800cb02: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800cb06: bf00 nop 800cb08: 0800cb1d .word 0x0800cb1d 800cb0c: 0800cb2b .word 0x0800cb2b 800cb10: 0800cb41 .word 0x0800cb41 800cb14: 0800cb5f .word 0x0800cb5f 800cb18: 0800cb5f .word 0x0800cb5f { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cb1c: 4b8e ldr r3, [pc, #568] @ (800cd58 ) 800cb1e: 6adb ldr r3, [r3, #44] @ 0x2c 800cb20: 4a8d ldr r2, [pc, #564] @ (800cd58 ) 800cb22: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cb26: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800cb28: e01a b.n 800cb60 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800cb2a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb2e: 3308 adds r3, #8 800cb30: 2100 movs r1, #0 800cb32: 4618 mov r0, r3 800cb34: f002 faf2 bl 800f11c 800cb38: 4603 mov r3, r0 800cb3a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800cb3e: e00f b.n 800cb60 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800cb40: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb44: 3328 adds r3, #40 @ 0x28 800cb46: 2100 movs r1, #0 800cb48: 4618 mov r0, r3 800cb4a: f002 fb99 bl 800f280 800cb4e: 4603 mov r3, r0 800cb50: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800cb54: e004 b.n 800cb60 /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cb56: 2301 movs r3, #1 800cb58: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cb5c: e000 b.n 800cb60 break; 800cb5e: bf00 nop } if (ret == HAL_OK) 800cb60: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cb64: 2b00 cmp r3, #0 800cb66: d10a bne.n 800cb7e { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 800cb68: 4b7b ldr r3, [pc, #492] @ (800cd58 ) 800cb6a: 6d1b ldr r3, [r3, #80] @ 0x50 800cb6c: f023 0107 bic.w r1, r3, #7 800cb70: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb74: 6d9b ldr r3, [r3, #88] @ 0x58 800cb76: 4a78 ldr r2, [pc, #480] @ (800cd58 ) 800cb78: 430b orrs r3, r1 800cb7a: 6513 str r3, [r2, #80] @ 0x50 800cb7c: e003 b.n 800cb86 } else { /* set overall return value */ status = ret; 800cb7e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cb82: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #if defined(SAI3) /*---------------------------- SAI2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) 800cb86: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb8a: e9d3 2300 ldrd r2, r3, [r3] 800cb8e: f402 7a00 and.w sl, r2, #512 @ 0x200 800cb92: f04f 0b00 mov.w fp, #0 800cb96: ea5a 030b orrs.w r3, sl, fp 800cb9a: d04c beq.n 800cc36 { switch (PeriphClkInit->Sai23ClockSelection) 800cb9c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cba0: 6ddb ldr r3, [r3, #92] @ 0x5c 800cba2: f5b3 7f80 cmp.w r3, #256 @ 0x100 800cba6: d030 beq.n 800cc0a 800cba8: f5b3 7f80 cmp.w r3, #256 @ 0x100 800cbac: d829 bhi.n 800cc02 800cbae: 2bc0 cmp r3, #192 @ 0xc0 800cbb0: d02d beq.n 800cc0e 800cbb2: 2bc0 cmp r3, #192 @ 0xc0 800cbb4: d825 bhi.n 800cc02 800cbb6: 2b80 cmp r3, #128 @ 0x80 800cbb8: d018 beq.n 800cbec 800cbba: 2b80 cmp r3, #128 @ 0x80 800cbbc: d821 bhi.n 800cc02 800cbbe: 2b00 cmp r3, #0 800cbc0: d002 beq.n 800cbc8 800cbc2: 2b40 cmp r3, #64 @ 0x40 800cbc4: d007 beq.n 800cbd6 800cbc6: e01c b.n 800cc02 { case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cbc8: 4b63 ldr r3, [pc, #396] @ (800cd58 ) 800cbca: 6adb ldr r3, [r3, #44] @ 0x2c 800cbcc: 4a62 ldr r2, [pc, #392] @ (800cd58 ) 800cbce: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cbd2: 62d3 str r3, [r2, #44] @ 0x2c /* SAI2/3 clock source configuration done later after clock selection check */ break; 800cbd4: e01c b.n 800cc10 case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800cbd6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cbda: 3308 adds r3, #8 800cbdc: 2100 movs r1, #0 800cbde: 4618 mov r0, r3 800cbe0: f002 fa9c bl 800f11c 800cbe4: 4603 mov r3, r0 800cbe6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 800cbea: e011 b.n 800cc10 case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800cbec: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cbf0: 3328 adds r3, #40 @ 0x28 800cbf2: 2100 movs r1, #0 800cbf4: 4618 mov r0, r3 800cbf6: f002 fb43 bl 800f280 800cbfa: 4603 mov r3, r0 800cbfc: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 800cc00: e006 b.n 800cc10 /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ /* SAI2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cc02: 2301 movs r3, #1 800cc04: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cc08: e002 b.n 800cc10 break; 800cc0a: bf00 nop 800cc0c: e000 b.n 800cc10 break; 800cc0e: bf00 nop } if (ret == HAL_OK) 800cc10: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cc14: 2b00 cmp r3, #0 800cc16: d10a bne.n 800cc2e { /* Set the source of SAI2/3 clock*/ __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); 800cc18: 4b4f ldr r3, [pc, #316] @ (800cd58 ) 800cc1a: 6d1b ldr r3, [r3, #80] @ 0x50 800cc1c: f423 71e0 bic.w r1, r3, #448 @ 0x1c0 800cc20: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc24: 6ddb ldr r3, [r3, #92] @ 0x5c 800cc26: 4a4c ldr r2, [pc, #304] @ (800cd58 ) 800cc28: 430b orrs r3, r1 800cc2a: 6513 str r3, [r2, #80] @ 0x50 800cc2c: e003 b.n 800cc36 } else { /* set overall return value */ status = ret; 800cc2e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cc32: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI2B*/ #if defined(SAI4) /*---------------------------- SAI4A configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 800cc36: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc3a: e9d3 2300 ldrd r2, r3, [r3] 800cc3e: f402 6380 and.w r3, r2, #1024 @ 0x400 800cc42: f8c7 3100 str.w r3, [r7, #256] @ 0x100 800cc46: 2300 movs r3, #0 800cc48: f8c7 3104 str.w r3, [r7, #260] @ 0x104 800cc4c: e9d7 1240 ldrd r1, r2, [r7, #256] @ 0x100 800cc50: 460b mov r3, r1 800cc52: 4313 orrs r3, r2 800cc54: d053 beq.n 800ccfe { switch (PeriphClkInit->Sai4AClockSelection) 800cc56: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc5a: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 800cc5e: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800cc62: d035 beq.n 800ccd0 800cc64: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800cc68: d82e bhi.n 800ccc8 800cc6a: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800cc6e: d031 beq.n 800ccd4 800cc70: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800cc74: d828 bhi.n 800ccc8 800cc76: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800cc7a: d01a beq.n 800ccb2 800cc7c: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800cc80: d822 bhi.n 800ccc8 800cc82: 2b00 cmp r3, #0 800cc84: d003 beq.n 800cc8e 800cc86: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800cc8a: d007 beq.n 800cc9c 800cc8c: e01c b.n 800ccc8 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cc8e: 4b32 ldr r3, [pc, #200] @ (800cd58 ) 800cc90: 6adb ldr r3, [r3, #44] @ 0x2c 800cc92: 4a31 ldr r2, [pc, #196] @ (800cd58 ) 800cc94: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cc98: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800cc9a: e01c b.n 800ccd6 case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800cc9c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cca0: 3308 adds r3, #8 800cca2: 2100 movs r1, #0 800cca4: 4618 mov r0, r3 800cca6: f002 fa39 bl 800f11c 800ccaa: 4603 mov r3, r0 800ccac: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800ccb0: e011 b.n 800ccd6 case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800ccb2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ccb6: 3328 adds r3, #40 @ 0x28 800ccb8: 2100 movs r1, #0 800ccba: 4618 mov r0, r3 800ccbc: f002 fae0 bl 800f280 800ccc0: 4603 mov r3, r0 800ccc2: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800ccc6: e006 b.n 800ccd6 /* SAI4A clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800ccc8: 2301 movs r3, #1 800ccca: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ccce: e002 b.n 800ccd6 break; 800ccd0: bf00 nop 800ccd2: e000 b.n 800ccd6 break; 800ccd4: bf00 nop } if (ret == HAL_OK) 800ccd6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ccda: 2b00 cmp r3, #0 800ccdc: d10b bne.n 800ccf6 { /* Set the source of SAI4A clock*/ __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); 800ccde: 4b1e ldr r3, [pc, #120] @ (800cd58 ) 800cce0: 6d9b ldr r3, [r3, #88] @ 0x58 800cce2: f423 0160 bic.w r1, r3, #14680064 @ 0xe00000 800cce6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ccea: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 800ccee: 4a1a ldr r2, [pc, #104] @ (800cd58 ) 800ccf0: 430b orrs r3, r1 800ccf2: 6593 str r3, [r2, #88] @ 0x58 800ccf4: e003 b.n 800ccfe } else { /* set overall return value */ status = ret; 800ccf6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ccfa: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI4B configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 800ccfe: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd02: e9d3 2300 ldrd r2, r3, [r3] 800cd06: f402 6300 and.w r3, r2, #2048 @ 0x800 800cd0a: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 800cd0e: 2300 movs r3, #0 800cd10: f8c7 30fc str.w r3, [r7, #252] @ 0xfc 800cd14: e9d7 123e ldrd r1, r2, [r7, #248] @ 0xf8 800cd18: 460b mov r3, r1 800cd1a: 4313 orrs r3, r2 800cd1c: d056 beq.n 800cdcc { switch (PeriphClkInit->Sai4BClockSelection) 800cd1e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd22: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 800cd26: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800cd2a: d038 beq.n 800cd9e 800cd2c: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800cd30: d831 bhi.n 800cd96 800cd32: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800cd36: d034 beq.n 800cda2 800cd38: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800cd3c: d82b bhi.n 800cd96 800cd3e: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800cd42: d01d beq.n 800cd80 800cd44: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800cd48: d825 bhi.n 800cd96 800cd4a: 2b00 cmp r3, #0 800cd4c: d006 beq.n 800cd5c 800cd4e: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800cd52: d00a beq.n 800cd6a 800cd54: e01f b.n 800cd96 800cd56: bf00 nop 800cd58: 58024400 .word 0x58024400 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cd5c: 4ba2 ldr r3, [pc, #648] @ (800cfe8 ) 800cd5e: 6adb ldr r3, [r3, #44] @ 0x2c 800cd60: 4aa1 ldr r2, [pc, #644] @ (800cfe8 ) 800cd62: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cd66: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800cd68: e01c b.n 800cda4 case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800cd6a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd6e: 3308 adds r3, #8 800cd70: 2100 movs r1, #0 800cd72: 4618 mov r0, r3 800cd74: f002 f9d2 bl 800f11c 800cd78: 4603 mov r3, r0 800cd7a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800cd7e: e011 b.n 800cda4 case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800cd80: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd84: 3328 adds r3, #40 @ 0x28 800cd86: 2100 movs r1, #0 800cd88: 4618 mov r0, r3 800cd8a: f002 fa79 bl 800f280 800cd8e: 4603 mov r3, r0 800cd90: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800cd94: e006 b.n 800cda4 /* SAI4B clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800cd96: 2301 movs r3, #1 800cd98: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cd9c: e002 b.n 800cda4 break; 800cd9e: bf00 nop 800cda0: e000 b.n 800cda4 break; 800cda2: bf00 nop } if (ret == HAL_OK) 800cda4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cda8: 2b00 cmp r3, #0 800cdaa: d10b bne.n 800cdc4 { /* Set the source of SAI4B clock*/ __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); 800cdac: 4b8e ldr r3, [pc, #568] @ (800cfe8 ) 800cdae: 6d9b ldr r3, [r3, #88] @ 0x58 800cdb0: f023 61e0 bic.w r1, r3, #117440512 @ 0x7000000 800cdb4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cdb8: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 800cdbc: 4a8a ldr r2, [pc, #552] @ (800cfe8 ) 800cdbe: 430b orrs r3, r1 800cdc0: 6593 str r3, [r2, #88] @ 0x58 800cdc2: e003 b.n 800cdcc } else { /* set overall return value */ status = ret; 800cdc4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cdc8: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI4*/ #if defined(QUADSPI) /*---------------------------- QSPI configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) 800cdcc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cdd0: e9d3 2300 ldrd r2, r3, [r3] 800cdd4: f002 7300 and.w r3, r2, #33554432 @ 0x2000000 800cdd8: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0 800cddc: 2300 movs r3, #0 800cdde: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4 800cde2: e9d7 123c ldrd r1, r2, [r7, #240] @ 0xf0 800cde6: 460b mov r3, r1 800cde8: 4313 orrs r3, r2 800cdea: d03a beq.n 800ce62 { switch (PeriphClkInit->QspiClockSelection) 800cdec: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cdf0: 6cdb ldr r3, [r3, #76] @ 0x4c 800cdf2: 2b30 cmp r3, #48 @ 0x30 800cdf4: d01f beq.n 800ce36 800cdf6: 2b30 cmp r3, #48 @ 0x30 800cdf8: d819 bhi.n 800ce2e 800cdfa: 2b20 cmp r3, #32 800cdfc: d00c beq.n 800ce18 800cdfe: 2b20 cmp r3, #32 800ce00: d815 bhi.n 800ce2e 800ce02: 2b00 cmp r3, #0 800ce04: d019 beq.n 800ce3a 800ce06: 2b10 cmp r3, #16 800ce08: d111 bne.n 800ce2e { case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ /* Enable QSPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800ce0a: 4b77 ldr r3, [pc, #476] @ (800cfe8 ) 800ce0c: 6adb ldr r3, [r3, #44] @ 0x2c 800ce0e: 4a76 ldr r2, [pc, #472] @ (800cfe8 ) 800ce10: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800ce14: 62d3 str r3, [r2, #44] @ 0x2c /* QSPI clock source configuration done later after clock selection check */ break; 800ce16: e011 b.n 800ce3c case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800ce18: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce1c: 3308 adds r3, #8 800ce1e: 2102 movs r1, #2 800ce20: 4618 mov r0, r3 800ce22: f002 f97b bl 800f11c 800ce26: 4603 mov r3, r0 800ce28: f887 311f strb.w r3, [r7, #287] @ 0x11f /* QSPI clock source configuration done later after clock selection check */ break; 800ce2c: e006 b.n 800ce3c case RCC_QSPICLKSOURCE_D1HCLK: /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ break; default: ret = HAL_ERROR; 800ce2e: 2301 movs r3, #1 800ce30: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ce34: e002 b.n 800ce3c break; 800ce36: bf00 nop 800ce38: e000 b.n 800ce3c break; 800ce3a: bf00 nop } if (ret == HAL_OK) 800ce3c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ce40: 2b00 cmp r3, #0 800ce42: d10a bne.n 800ce5a { /* Set the source of QSPI clock*/ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); 800ce44: 4b68 ldr r3, [pc, #416] @ (800cfe8 ) 800ce46: 6cdb ldr r3, [r3, #76] @ 0x4c 800ce48: f023 0130 bic.w r1, r3, #48 @ 0x30 800ce4c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce50: 6cdb ldr r3, [r3, #76] @ 0x4c 800ce52: 4a65 ldr r2, [pc, #404] @ (800cfe8 ) 800ce54: 430b orrs r3, r1 800ce56: 64d3 str r3, [r2, #76] @ 0x4c 800ce58: e003 b.n 800ce62 } else { /* set overall return value */ status = ret; 800ce5a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ce5e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 800ce62: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce66: e9d3 2300 ldrd r2, r3, [r3] 800ce6a: f402 5380 and.w r3, r2, #4096 @ 0x1000 800ce6e: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 800ce72: 2300 movs r3, #0 800ce74: f8c7 30ec str.w r3, [r7, #236] @ 0xec 800ce78: e9d7 123a ldrd r1, r2, [r7, #232] @ 0xe8 800ce7c: 460b mov r3, r1 800ce7e: 4313 orrs r3, r2 800ce80: d051 beq.n 800cf26 { switch (PeriphClkInit->Spi123ClockSelection) 800ce82: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce86: 6e1b ldr r3, [r3, #96] @ 0x60 800ce88: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800ce8c: d035 beq.n 800cefa 800ce8e: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800ce92: d82e bhi.n 800cef2 800ce94: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800ce98: d031 beq.n 800cefe 800ce9a: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800ce9e: d828 bhi.n 800cef2 800cea0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800cea4: d01a beq.n 800cedc 800cea6: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800ceaa: d822 bhi.n 800cef2 800ceac: 2b00 cmp r3, #0 800ceae: d003 beq.n 800ceb8 800ceb0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800ceb4: d007 beq.n 800cec6 800ceb6: e01c b.n 800cef2 { case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800ceb8: 4b4b ldr r3, [pc, #300] @ (800cfe8 ) 800ceba: 6adb ldr r3, [r3, #44] @ 0x2c 800cebc: 4a4a ldr r2, [pc, #296] @ (800cfe8 ) 800cebe: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cec2: 62d3 str r3, [r2, #44] @ 0x2c /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800cec4: e01c b.n 800cf00 case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800cec6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ceca: 3308 adds r3, #8 800cecc: 2100 movs r1, #0 800cece: 4618 mov r0, r3 800ced0: f002 f924 bl 800f11c 800ced4: 4603 mov r3, r0 800ced6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800ceda: e011 b.n 800cf00 case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800cedc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cee0: 3328 adds r3, #40 @ 0x28 800cee2: 2100 movs r1, #0 800cee4: 4618 mov r0, r3 800cee6: f002 f9cb bl 800f280 800ceea: 4603 mov r3, r0 800ceec: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800cef0: e006 b.n 800cf00 /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ /* SPI1/2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cef2: 2301 movs r3, #1 800cef4: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cef8: e002 b.n 800cf00 break; 800cefa: bf00 nop 800cefc: e000 b.n 800cf00 break; 800cefe: bf00 nop } if (ret == HAL_OK) 800cf00: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cf04: 2b00 cmp r3, #0 800cf06: d10a bne.n 800cf1e { /* Set the source of SPI1/2/3 clock*/ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 800cf08: 4b37 ldr r3, [pc, #220] @ (800cfe8 ) 800cf0a: 6d1b ldr r3, [r3, #80] @ 0x50 800cf0c: f423 41e0 bic.w r1, r3, #28672 @ 0x7000 800cf10: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf14: 6e1b ldr r3, [r3, #96] @ 0x60 800cf16: 4a34 ldr r2, [pc, #208] @ (800cfe8 ) 800cf18: 430b orrs r3, r1 800cf1a: 6513 str r3, [r2, #80] @ 0x50 800cf1c: e003 b.n 800cf26 } else { /* set overall return value */ status = ret; 800cf1e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cf22: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI4/5 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 800cf26: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf2a: e9d3 2300 ldrd r2, r3, [r3] 800cf2e: f402 5300 and.w r3, r2, #8192 @ 0x2000 800cf32: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 800cf36: 2300 movs r3, #0 800cf38: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 800cf3c: e9d7 1238 ldrd r1, r2, [r7, #224] @ 0xe0 800cf40: 460b mov r3, r1 800cf42: 4313 orrs r3, r2 800cf44: d056 beq.n 800cff4 { switch (PeriphClkInit->Spi45ClockSelection) 800cf46: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf4a: 6e5b ldr r3, [r3, #100] @ 0x64 800cf4c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800cf50: d033 beq.n 800cfba 800cf52: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800cf56: d82c bhi.n 800cfb2 800cf58: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800cf5c: d02f beq.n 800cfbe 800cf5e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800cf62: d826 bhi.n 800cfb2 800cf64: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800cf68: d02b beq.n 800cfc2 800cf6a: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800cf6e: d820 bhi.n 800cfb2 800cf70: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800cf74: d012 beq.n 800cf9c 800cf76: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800cf7a: d81a bhi.n 800cfb2 800cf7c: 2b00 cmp r3, #0 800cf7e: d022 beq.n 800cfc6 800cf80: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800cf84: d115 bne.n 800cfb2 /* SPI4/5 clock source configuration done later after clock selection check */ break; case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800cf86: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf8a: 3308 adds r3, #8 800cf8c: 2101 movs r1, #1 800cf8e: 4618 mov r0, r3 800cf90: f002 f8c4 bl 800f11c 800cf94: 4603 mov r3, r0 800cf96: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 800cf9a: e015 b.n 800cfc8 case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800cf9c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cfa0: 3328 adds r3, #40 @ 0x28 800cfa2: 2101 movs r1, #1 800cfa4: 4618 mov r0, r3 800cfa6: f002 f96b bl 800f280 800cfaa: 4603 mov r3, r0 800cfac: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 800cfb0: e00a b.n 800cfc8 /* HSE, oscillator is used as source of SPI4/5 clock */ /* SPI4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cfb2: 2301 movs r3, #1 800cfb4: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cfb8: e006 b.n 800cfc8 break; 800cfba: bf00 nop 800cfbc: e004 b.n 800cfc8 break; 800cfbe: bf00 nop 800cfc0: e002 b.n 800cfc8 break; 800cfc2: bf00 nop 800cfc4: e000 b.n 800cfc8 break; 800cfc6: bf00 nop } if (ret == HAL_OK) 800cfc8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cfcc: 2b00 cmp r3, #0 800cfce: d10d bne.n 800cfec { /* Set the source of SPI4/5 clock*/ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 800cfd0: 4b05 ldr r3, [pc, #20] @ (800cfe8 ) 800cfd2: 6d1b ldr r3, [r3, #80] @ 0x50 800cfd4: f423 21e0 bic.w r1, r3, #458752 @ 0x70000 800cfd8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cfdc: 6e5b ldr r3, [r3, #100] @ 0x64 800cfde: 4a02 ldr r2, [pc, #8] @ (800cfe8 ) 800cfe0: 430b orrs r3, r1 800cfe2: 6513 str r3, [r2, #80] @ 0x50 800cfe4: e006 b.n 800cff4 800cfe6: bf00 nop 800cfe8: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800cfec: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cff0: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI6 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 800cff4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cff8: e9d3 2300 ldrd r2, r3, [r3] 800cffc: f402 4380 and.w r3, r2, #16384 @ 0x4000 800d000: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 800d004: 2300 movs r3, #0 800d006: f8c7 30dc str.w r3, [r7, #220] @ 0xdc 800d00a: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 800d00e: 460b mov r3, r1 800d010: 4313 orrs r3, r2 800d012: d055 beq.n 800d0c0 { switch (PeriphClkInit->Spi6ClockSelection) 800d014: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d018: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 800d01c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800d020: d033 beq.n 800d08a 800d022: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800d026: d82c bhi.n 800d082 800d028: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800d02c: d02f beq.n 800d08e 800d02e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800d032: d826 bhi.n 800d082 800d034: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800d038: d02b beq.n 800d092 800d03a: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800d03e: d820 bhi.n 800d082 800d040: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d044: d012 beq.n 800d06c 800d046: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d04a: d81a bhi.n 800d082 800d04c: 2b00 cmp r3, #0 800d04e: d022 beq.n 800d096 800d050: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800d054: d115 bne.n 800d082 /* SPI6 clock source configuration done later after clock selection check */ break; case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d056: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d05a: 3308 adds r3, #8 800d05c: 2101 movs r1, #1 800d05e: 4618 mov r0, r3 800d060: f002 f85c bl 800f11c 800d064: 4603 mov r3, r0 800d066: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 800d06a: e015 b.n 800d098 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d06c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d070: 3328 adds r3, #40 @ 0x28 800d072: 2101 movs r1, #1 800d074: 4618 mov r0, r3 800d076: f002 f903 bl 800f280 800d07a: 4603 mov r3, r0 800d07c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 800d080: e00a b.n 800d098 /* SPI6 clock source configuration done later after clock selection check */ break; #endif default: ret = HAL_ERROR; 800d082: 2301 movs r3, #1 800d084: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d088: e006 b.n 800d098 break; 800d08a: bf00 nop 800d08c: e004 b.n 800d098 break; 800d08e: bf00 nop 800d090: e002 b.n 800d098 break; 800d092: bf00 nop 800d094: e000 b.n 800d098 break; 800d096: bf00 nop } if (ret == HAL_OK) 800d098: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d09c: 2b00 cmp r3, #0 800d09e: d10b bne.n 800d0b8 { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 800d0a0: 4ba3 ldr r3, [pc, #652] @ (800d330 ) 800d0a2: 6d9b ldr r3, [r3, #88] @ 0x58 800d0a4: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 800d0a8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0ac: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 800d0b0: 4a9f ldr r2, [pc, #636] @ (800d330 ) 800d0b2: 430b orrs r3, r1 800d0b4: 6593 str r3, [r2, #88] @ 0x58 800d0b6: e003 b.n 800d0c0 } else { /* set overall return value */ status = ret; 800d0b8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d0bc: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*DSI*/ #if defined(FDCAN1) || defined(FDCAN2) /*---------------------------- FDCAN configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 800d0c0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0c4: e9d3 2300 ldrd r2, r3, [r3] 800d0c8: f402 4300 and.w r3, r2, #32768 @ 0x8000 800d0cc: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 800d0d0: 2300 movs r3, #0 800d0d2: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 800d0d6: e9d7 1234 ldrd r1, r2, [r7, #208] @ 0xd0 800d0da: 460b mov r3, r1 800d0dc: 4313 orrs r3, r2 800d0de: d037 beq.n 800d150 { switch (PeriphClkInit->FdcanClockSelection) 800d0e0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0e4: 6f1b ldr r3, [r3, #112] @ 0x70 800d0e6: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d0ea: d00e beq.n 800d10a 800d0ec: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d0f0: d816 bhi.n 800d120 800d0f2: 2b00 cmp r3, #0 800d0f4: d018 beq.n 800d128 800d0f6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800d0fa: d111 bne.n 800d120 { case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ /* Enable FDCAN Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d0fc: 4b8c ldr r3, [pc, #560] @ (800d330 ) 800d0fe: 6adb ldr r3, [r3, #44] @ 0x2c 800d100: 4a8b ldr r2, [pc, #556] @ (800d330 ) 800d102: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d106: 62d3 str r3, [r2, #44] @ 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 800d108: e00f b.n 800d12a case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d10a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d10e: 3308 adds r3, #8 800d110: 2101 movs r1, #1 800d112: 4618 mov r0, r3 800d114: f002 f802 bl 800f11c 800d118: 4603 mov r3, r0 800d11a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FDCAN clock source configuration done later after clock selection check */ break; 800d11e: e004 b.n 800d12a /* HSE is used as clock source for FDCAN*/ /* FDCAN clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d120: 2301 movs r3, #1 800d122: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d126: e000 b.n 800d12a break; 800d128: bf00 nop } if (ret == HAL_OK) 800d12a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d12e: 2b00 cmp r3, #0 800d130: d10a bne.n 800d148 { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 800d132: 4b7f ldr r3, [pc, #508] @ (800d330 ) 800d134: 6d1b ldr r3, [r3, #80] @ 0x50 800d136: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 800d13a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d13e: 6f1b ldr r3, [r3, #112] @ 0x70 800d140: 4a7b ldr r2, [pc, #492] @ (800d330 ) 800d142: 430b orrs r3, r1 800d144: 6513 str r3, [r2, #80] @ 0x50 800d146: e003 b.n 800d150 } else { /* set overall return value */ status = ret; 800d148: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d14c: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*FDCAN1 || FDCAN2*/ /*---------------------------- FMC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 800d150: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d154: e9d3 2300 ldrd r2, r3, [r3] 800d158: f002 7380 and.w r3, r2, #16777216 @ 0x1000000 800d15c: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 800d160: 2300 movs r3, #0 800d162: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 800d166: e9d7 1232 ldrd r1, r2, [r7, #200] @ 0xc8 800d16a: 460b mov r3, r1 800d16c: 4313 orrs r3, r2 800d16e: d039 beq.n 800d1e4 { switch (PeriphClkInit->FmcClockSelection) 800d170: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d174: 6c9b ldr r3, [r3, #72] @ 0x48 800d176: 2b03 cmp r3, #3 800d178: d81c bhi.n 800d1b4 800d17a: a201 add r2, pc, #4 @ (adr r2, 800d180 ) 800d17c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d180: 0800d1bd .word 0x0800d1bd 800d184: 0800d191 .word 0x0800d191 800d188: 0800d19f .word 0x0800d19f 800d18c: 0800d1bd .word 0x0800d1bd { case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ /* Enable FMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d190: 4b67 ldr r3, [pc, #412] @ (800d330 ) 800d192: 6adb ldr r3, [r3, #44] @ 0x2c 800d194: 4a66 ldr r2, [pc, #408] @ (800d330 ) 800d196: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d19a: 62d3 str r3, [r2, #44] @ 0x2c /* FMC clock source configuration done later after clock selection check */ break; 800d19c: e00f b.n 800d1be case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800d19e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d1a2: 3308 adds r3, #8 800d1a4: 2102 movs r1, #2 800d1a6: 4618 mov r0, r3 800d1a8: f001 ffb8 bl 800f11c 800d1ac: 4603 mov r3, r0 800d1ae: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FMC clock source configuration done later after clock selection check */ break; 800d1b2: e004 b.n 800d1be case RCC_FMCCLKSOURCE_HCLK: /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ break; default: ret = HAL_ERROR; 800d1b4: 2301 movs r3, #1 800d1b6: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d1ba: e000 b.n 800d1be break; 800d1bc: bf00 nop } if (ret == HAL_OK) 800d1be: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d1c2: 2b00 cmp r3, #0 800d1c4: d10a bne.n 800d1dc { /* Set the source of FMC clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 800d1c6: 4b5a ldr r3, [pc, #360] @ (800d330 ) 800d1c8: 6cdb ldr r3, [r3, #76] @ 0x4c 800d1ca: f023 0103 bic.w r1, r3, #3 800d1ce: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d1d2: 6c9b ldr r3, [r3, #72] @ 0x48 800d1d4: 4a56 ldr r2, [pc, #344] @ (800d330 ) 800d1d6: 430b orrs r3, r1 800d1d8: 64d3 str r3, [r2, #76] @ 0x4c 800d1da: e003 b.n 800d1e4 } else { /* set overall return value */ status = ret; 800d1dc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d1e0: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- RTC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 800d1e4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d1e8: e9d3 2300 ldrd r2, r3, [r3] 800d1ec: f402 0380 and.w r3, r2, #4194304 @ 0x400000 800d1f0: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 800d1f4: 2300 movs r3, #0 800d1f6: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 800d1fa: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 800d1fe: 460b mov r3, r1 800d200: 4313 orrs r3, r2 800d202: f000 809f beq.w 800d344 { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 800d206: 4b4b ldr r3, [pc, #300] @ (800d334 ) 800d208: 681b ldr r3, [r3, #0] 800d20a: 4a4a ldr r2, [pc, #296] @ (800d334 ) 800d20c: f443 7380 orr.w r3, r3, #256 @ 0x100 800d210: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800d212: f7f8 fe47 bl 8005ea4 800d216: f8c7 0118 str.w r0, [r7, #280] @ 0x118 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800d21a: e00b b.n 800d234 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800d21c: f7f8 fe42 bl 8005ea4 800d220: 4602 mov r2, r0 800d222: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 800d226: 1ad3 subs r3, r2, r3 800d228: 2b64 cmp r3, #100 @ 0x64 800d22a: d903 bls.n 800d234 { ret = HAL_TIMEOUT; 800d22c: 2303 movs r3, #3 800d22e: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d232: e005 b.n 800d240 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800d234: 4b3f ldr r3, [pc, #252] @ (800d334 ) 800d236: 681b ldr r3, [r3, #0] 800d238: f403 7380 and.w r3, r3, #256 @ 0x100 800d23c: 2b00 cmp r3, #0 800d23e: d0ed beq.n 800d21c } } if (ret == HAL_OK) 800d240: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d244: 2b00 cmp r3, #0 800d246: d179 bne.n 800d33c { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 800d248: 4b39 ldr r3, [pc, #228] @ (800d330 ) 800d24a: 6f1a ldr r2, [r3, #112] @ 0x70 800d24c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d250: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d254: 4053 eors r3, r2 800d256: f403 7340 and.w r3, r3, #768 @ 0x300 800d25a: 2b00 cmp r3, #0 800d25c: d015 beq.n 800d28a { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800d25e: 4b34 ldr r3, [pc, #208] @ (800d330 ) 800d260: 6f1b ldr r3, [r3, #112] @ 0x70 800d262: f423 7340 bic.w r3, r3, #768 @ 0x300 800d266: f8c7 3114 str.w r3, [r7, #276] @ 0x114 /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 800d26a: 4b31 ldr r3, [pc, #196] @ (800d330 ) 800d26c: 6f1b ldr r3, [r3, #112] @ 0x70 800d26e: 4a30 ldr r2, [pc, #192] @ (800d330 ) 800d270: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800d274: 6713 str r3, [r2, #112] @ 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 800d276: 4b2e ldr r3, [pc, #184] @ (800d330 ) 800d278: 6f1b ldr r3, [r3, #112] @ 0x70 800d27a: 4a2d ldr r2, [pc, #180] @ (800d330 ) 800d27c: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800d280: 6713 str r3, [r2, #112] @ 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg; 800d282: 4a2b ldr r2, [pc, #172] @ (800d330 ) 800d284: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800d288: 6713 str r3, [r2, #112] @ 0x70 } /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 800d28a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d28e: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d292: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d296: d118 bne.n 800d2ca { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800d298: f7f8 fe04 bl 8005ea4 800d29c: f8c7 0118 str.w r0, [r7, #280] @ 0x118 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800d2a0: e00d b.n 800d2be { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800d2a2: f7f8 fdff bl 8005ea4 800d2a6: 4602 mov r2, r0 800d2a8: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 800d2ac: 1ad2 subs r2, r2, r3 800d2ae: f241 3388 movw r3, #5000 @ 0x1388 800d2b2: 429a cmp r2, r3 800d2b4: d903 bls.n 800d2be { ret = HAL_TIMEOUT; 800d2b6: 2303 movs r3, #3 800d2b8: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d2bc: e005 b.n 800d2ca while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800d2be: 4b1c ldr r3, [pc, #112] @ (800d330 ) 800d2c0: 6f1b ldr r3, [r3, #112] @ 0x70 800d2c2: f003 0302 and.w r3, r3, #2 800d2c6: 2b00 cmp r3, #0 800d2c8: d0eb beq.n 800d2a2 } } } if (ret == HAL_OK) 800d2ca: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d2ce: 2b00 cmp r3, #0 800d2d0: d129 bne.n 800d326 { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 800d2d2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d2d6: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d2da: f403 7340 and.w r3, r3, #768 @ 0x300 800d2de: f5b3 7f40 cmp.w r3, #768 @ 0x300 800d2e2: d10e bne.n 800d302 800d2e4: 4b12 ldr r3, [pc, #72] @ (800d330 ) 800d2e6: 691b ldr r3, [r3, #16] 800d2e8: f423 517c bic.w r1, r3, #16128 @ 0x3f00 800d2ec: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d2f0: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d2f4: 091a lsrs r2, r3, #4 800d2f6: 4b10 ldr r3, [pc, #64] @ (800d338 ) 800d2f8: 4013 ands r3, r2 800d2fa: 4a0d ldr r2, [pc, #52] @ (800d330 ) 800d2fc: 430b orrs r3, r1 800d2fe: 6113 str r3, [r2, #16] 800d300: e005 b.n 800d30e 800d302: 4b0b ldr r3, [pc, #44] @ (800d330 ) 800d304: 691b ldr r3, [r3, #16] 800d306: 4a0a ldr r2, [pc, #40] @ (800d330 ) 800d308: f423 537c bic.w r3, r3, #16128 @ 0x3f00 800d30c: 6113 str r3, [r2, #16] 800d30e: 4b08 ldr r3, [pc, #32] @ (800d330 ) 800d310: 6f19 ldr r1, [r3, #112] @ 0x70 800d312: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d316: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d31a: f3c3 030b ubfx r3, r3, #0, #12 800d31e: 4a04 ldr r2, [pc, #16] @ (800d330 ) 800d320: 430b orrs r3, r1 800d322: 6713 str r3, [r2, #112] @ 0x70 800d324: e00e b.n 800d344 } else { /* set overall return value */ status = ret; 800d326: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d32a: f887 311e strb.w r3, [r7, #286] @ 0x11e 800d32e: e009 b.n 800d344 800d330: 58024400 .word 0x58024400 800d334: 58024800 .word 0x58024800 800d338: 00ffffcf .word 0x00ffffcf } } else { /* set overall return value */ status = ret; 800d33c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d340: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART1/6 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 800d344: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d348: e9d3 2300 ldrd r2, r3, [r3] 800d34c: f002 0301 and.w r3, r2, #1 800d350: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 800d354: 2300 movs r3, #0 800d356: f8c7 30bc str.w r3, [r7, #188] @ 0xbc 800d35a: e9d7 122e ldrd r1, r2, [r7, #184] @ 0xb8 800d35e: 460b mov r3, r1 800d360: 4313 orrs r3, r2 800d362: f000 8089 beq.w 800d478 { switch (PeriphClkInit->Usart16ClockSelection) 800d366: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d36a: 6fdb ldr r3, [r3, #124] @ 0x7c 800d36c: 2b28 cmp r3, #40 @ 0x28 800d36e: d86b bhi.n 800d448 800d370: a201 add r2, pc, #4 @ (adr r2, 800d378 ) 800d372: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d376: bf00 nop 800d378: 0800d451 .word 0x0800d451 800d37c: 0800d449 .word 0x0800d449 800d380: 0800d449 .word 0x0800d449 800d384: 0800d449 .word 0x0800d449 800d388: 0800d449 .word 0x0800d449 800d38c: 0800d449 .word 0x0800d449 800d390: 0800d449 .word 0x0800d449 800d394: 0800d449 .word 0x0800d449 800d398: 0800d41d .word 0x0800d41d 800d39c: 0800d449 .word 0x0800d449 800d3a0: 0800d449 .word 0x0800d449 800d3a4: 0800d449 .word 0x0800d449 800d3a8: 0800d449 .word 0x0800d449 800d3ac: 0800d449 .word 0x0800d449 800d3b0: 0800d449 .word 0x0800d449 800d3b4: 0800d449 .word 0x0800d449 800d3b8: 0800d433 .word 0x0800d433 800d3bc: 0800d449 .word 0x0800d449 800d3c0: 0800d449 .word 0x0800d449 800d3c4: 0800d449 .word 0x0800d449 800d3c8: 0800d449 .word 0x0800d449 800d3cc: 0800d449 .word 0x0800d449 800d3d0: 0800d449 .word 0x0800d449 800d3d4: 0800d449 .word 0x0800d449 800d3d8: 0800d451 .word 0x0800d451 800d3dc: 0800d449 .word 0x0800d449 800d3e0: 0800d449 .word 0x0800d449 800d3e4: 0800d449 .word 0x0800d449 800d3e8: 0800d449 .word 0x0800d449 800d3ec: 0800d449 .word 0x0800d449 800d3f0: 0800d449 .word 0x0800d449 800d3f4: 0800d449 .word 0x0800d449 800d3f8: 0800d451 .word 0x0800d451 800d3fc: 0800d449 .word 0x0800d449 800d400: 0800d449 .word 0x0800d449 800d404: 0800d449 .word 0x0800d449 800d408: 0800d449 .word 0x0800d449 800d40c: 0800d449 .word 0x0800d449 800d410: 0800d449 .word 0x0800d449 800d414: 0800d449 .word 0x0800d449 800d418: 0800d451 .word 0x0800d451 case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ /* USART1/6 clock source configuration done later after clock selection check */ break; case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d41c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d420: 3308 adds r3, #8 800d422: 2101 movs r1, #1 800d424: 4618 mov r0, r3 800d426: f001 fe79 bl 800f11c 800d42a: 4603 mov r3, r0 800d42c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 800d430: e00f b.n 800d452 case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d432: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d436: 3328 adds r3, #40 @ 0x28 800d438: 2101 movs r1, #1 800d43a: 4618 mov r0, r3 800d43c: f001 ff20 bl 800f280 800d440: 4603 mov r3, r0 800d442: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 800d446: e004 b.n 800d452 /* LSE, oscillator is used as source of USART1/6 clock */ /* USART1/6 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d448: 2301 movs r3, #1 800d44a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d44e: e000 b.n 800d452 break; 800d450: bf00 nop } if (ret == HAL_OK) 800d452: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d456: 2b00 cmp r3, #0 800d458: d10a bne.n 800d470 { /* Set the source of USART1/6 clock */ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 800d45a: 4bbf ldr r3, [pc, #764] @ (800d758 ) 800d45c: 6d5b ldr r3, [r3, #84] @ 0x54 800d45e: f023 0138 bic.w r1, r3, #56 @ 0x38 800d462: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d466: 6fdb ldr r3, [r3, #124] @ 0x7c 800d468: 4abb ldr r2, [pc, #748] @ (800d758 ) 800d46a: 430b orrs r3, r1 800d46c: 6553 str r3, [r2, #84] @ 0x54 800d46e: e003 b.n 800d478 } else { /* set overall return value */ status = ret; 800d470: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d474: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 800d478: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d47c: e9d3 2300 ldrd r2, r3, [r3] 800d480: f002 0302 and.w r3, r2, #2 800d484: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 800d488: 2300 movs r3, #0 800d48a: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 800d48e: e9d7 122c ldrd r1, r2, [r7, #176] @ 0xb0 800d492: 460b mov r3, r1 800d494: 4313 orrs r3, r2 800d496: d041 beq.n 800d51c { switch (PeriphClkInit->Usart234578ClockSelection) 800d498: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d49c: 6f9b ldr r3, [r3, #120] @ 0x78 800d49e: 2b05 cmp r3, #5 800d4a0: d824 bhi.n 800d4ec 800d4a2: a201 add r2, pc, #4 @ (adr r2, 800d4a8 ) 800d4a4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d4a8: 0800d4f5 .word 0x0800d4f5 800d4ac: 0800d4c1 .word 0x0800d4c1 800d4b0: 0800d4d7 .word 0x0800d4d7 800d4b4: 0800d4f5 .word 0x0800d4f5 800d4b8: 0800d4f5 .word 0x0800d4f5 800d4bc: 0800d4f5 .word 0x0800d4f5 case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d4c0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d4c4: 3308 adds r3, #8 800d4c6: 2101 movs r1, #1 800d4c8: 4618 mov r0, r3 800d4ca: f001 fe27 bl 800f11c 800d4ce: 4603 mov r3, r0 800d4d0: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 800d4d4: e00f b.n 800d4f6 case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d4d6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d4da: 3328 adds r3, #40 @ 0x28 800d4dc: 2101 movs r1, #1 800d4de: 4618 mov r0, r3 800d4e0: f001 fece bl 800f280 800d4e4: 4603 mov r3, r0 800d4e6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 800d4ea: e004 b.n 800d4f6 /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d4ec: 2301 movs r3, #1 800d4ee: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d4f2: e000 b.n 800d4f6 break; 800d4f4: bf00 nop } if (ret == HAL_OK) 800d4f6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d4fa: 2b00 cmp r3, #0 800d4fc: d10a bne.n 800d514 { /* Set the source of USART2/3/4/5/7/8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 800d4fe: 4b96 ldr r3, [pc, #600] @ (800d758 ) 800d500: 6d5b ldr r3, [r3, #84] @ 0x54 800d502: f023 0107 bic.w r1, r3, #7 800d506: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d50a: 6f9b ldr r3, [r3, #120] @ 0x78 800d50c: 4a92 ldr r2, [pc, #584] @ (800d758 ) 800d50e: 430b orrs r3, r1 800d510: 6553 str r3, [r2, #84] @ 0x54 800d512: e003 b.n 800d51c } else { /* set overall return value */ status = ret; 800d514: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d518: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- LPUART1 Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 800d51c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d520: e9d3 2300 ldrd r2, r3, [r3] 800d524: f002 0304 and.w r3, r2, #4 800d528: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 800d52c: 2300 movs r3, #0 800d52e: f8c7 30ac str.w r3, [r7, #172] @ 0xac 800d532: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 800d536: 460b mov r3, r1 800d538: 4313 orrs r3, r2 800d53a: d044 beq.n 800d5c6 { switch (PeriphClkInit->Lpuart1ClockSelection) 800d53c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d540: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800d544: 2b05 cmp r3, #5 800d546: d825 bhi.n 800d594 800d548: a201 add r2, pc, #4 @ (adr r2, 800d550 ) 800d54a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d54e: bf00 nop 800d550: 0800d59d .word 0x0800d59d 800d554: 0800d569 .word 0x0800d569 800d558: 0800d57f .word 0x0800d57f 800d55c: 0800d59d .word 0x0800d59d 800d560: 0800d59d .word 0x0800d59d 800d564: 0800d59d .word 0x0800d59d case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d568: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d56c: 3308 adds r3, #8 800d56e: 2101 movs r1, #1 800d570: 4618 mov r0, r3 800d572: f001 fdd3 bl 800f11c 800d576: 4603 mov r3, r0 800d578: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 800d57c: e00f b.n 800d59e case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d57e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d582: 3328 adds r3, #40 @ 0x28 800d584: 2101 movs r1, #1 800d586: 4618 mov r0, r3 800d588: f001 fe7a bl 800f280 800d58c: 4603 mov r3, r0 800d58e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 800d592: e004 b.n 800d59e /* LSE, oscillator is used as source of LPUART1 clock */ /* LPUART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d594: 2301 movs r3, #1 800d596: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d59a: e000 b.n 800d59e break; 800d59c: bf00 nop } if (ret == HAL_OK) 800d59e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d5a2: 2b00 cmp r3, #0 800d5a4: d10b bne.n 800d5be { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 800d5a6: 4b6c ldr r3, [pc, #432] @ (800d758 ) 800d5a8: 6d9b ldr r3, [r3, #88] @ 0x58 800d5aa: f023 0107 bic.w r1, r3, #7 800d5ae: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d5b2: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800d5b6: 4a68 ldr r2, [pc, #416] @ (800d758 ) 800d5b8: 430b orrs r3, r1 800d5ba: 6593 str r3, [r2, #88] @ 0x58 800d5bc: e003 b.n 800d5c6 } else { /* set overall return value */ status = ret; 800d5be: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d5c2: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 800d5c6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d5ca: e9d3 2300 ldrd r2, r3, [r3] 800d5ce: f002 0320 and.w r3, r2, #32 800d5d2: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 800d5d6: 2300 movs r3, #0 800d5d8: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 800d5dc: e9d7 1228 ldrd r1, r2, [r7, #160] @ 0xa0 800d5e0: 460b mov r3, r1 800d5e2: 4313 orrs r3, r2 800d5e4: d055 beq.n 800d692 { switch (PeriphClkInit->Lptim1ClockSelection) 800d5e6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d5ea: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800d5ee: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800d5f2: d033 beq.n 800d65c 800d5f4: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800d5f8: d82c bhi.n 800d654 800d5fa: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800d5fe: d02f beq.n 800d660 800d600: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800d604: d826 bhi.n 800d654 800d606: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800d60a: d02b beq.n 800d664 800d60c: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800d610: d820 bhi.n 800d654 800d612: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d616: d012 beq.n 800d63e 800d618: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d61c: d81a bhi.n 800d654 800d61e: 2b00 cmp r3, #0 800d620: d022 beq.n 800d668 800d622: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800d626: d115 bne.n 800d654 /* LPTIM1 clock source configuration done later after clock selection check */ break; case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d628: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d62c: 3308 adds r3, #8 800d62e: 2100 movs r1, #0 800d630: 4618 mov r0, r3 800d632: f001 fd73 bl 800f11c 800d636: 4603 mov r3, r0 800d638: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 800d63c: e015 b.n 800d66a case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d63e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d642: 3328 adds r3, #40 @ 0x28 800d644: 2102 movs r1, #2 800d646: 4618 mov r0, r3 800d648: f001 fe1a bl 800f280 800d64c: 4603 mov r3, r0 800d64e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 800d652: e00a b.n 800d66a /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ /* LPTIM1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d654: 2301 movs r3, #1 800d656: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d65a: e006 b.n 800d66a break; 800d65c: bf00 nop 800d65e: e004 b.n 800d66a break; 800d660: bf00 nop 800d662: e002 b.n 800d66a break; 800d664: bf00 nop 800d666: e000 b.n 800d66a break; 800d668: bf00 nop } if (ret == HAL_OK) 800d66a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d66e: 2b00 cmp r3, #0 800d670: d10b bne.n 800d68a { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 800d672: 4b39 ldr r3, [pc, #228] @ (800d758 ) 800d674: 6d5b ldr r3, [r3, #84] @ 0x54 800d676: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 800d67a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d67e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800d682: 4a35 ldr r2, [pc, #212] @ (800d758 ) 800d684: 430b orrs r3, r1 800d686: 6553 str r3, [r2, #84] @ 0x54 800d688: e003 b.n 800d692 } else { /* set overall return value */ status = ret; 800d68a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d68e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 800d692: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d696: e9d3 2300 ldrd r2, r3, [r3] 800d69a: f002 0340 and.w r3, r2, #64 @ 0x40 800d69e: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800d6a2: 2300 movs r3, #0 800d6a4: f8c7 309c str.w r3, [r7, #156] @ 0x9c 800d6a8: e9d7 1226 ldrd r1, r2, [r7, #152] @ 0x98 800d6ac: 460b mov r3, r1 800d6ae: 4313 orrs r3, r2 800d6b0: d058 beq.n 800d764 { switch (PeriphClkInit->Lptim2ClockSelection) 800d6b2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d6b6: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800d6ba: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800d6be: d033 beq.n 800d728 800d6c0: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800d6c4: d82c bhi.n 800d720 800d6c6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d6ca: d02f beq.n 800d72c 800d6cc: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d6d0: d826 bhi.n 800d720 800d6d2: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 800d6d6: d02b beq.n 800d730 800d6d8: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 800d6dc: d820 bhi.n 800d720 800d6de: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800d6e2: d012 beq.n 800d70a 800d6e4: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800d6e8: d81a bhi.n 800d720 800d6ea: 2b00 cmp r3, #0 800d6ec: d022 beq.n 800d734 800d6ee: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800d6f2: d115 bne.n 800d720 /* LPTIM2 clock source configuration done later after clock selection check */ break; case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d6f4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d6f8: 3308 adds r3, #8 800d6fa: 2100 movs r1, #0 800d6fc: 4618 mov r0, r3 800d6fe: f001 fd0d bl 800f11c 800d702: 4603 mov r3, r0 800d704: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 800d708: e015 b.n 800d736 case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d70a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d70e: 3328 adds r3, #40 @ 0x28 800d710: 2102 movs r1, #2 800d712: 4618 mov r0, r3 800d714: f001 fdb4 bl 800f280 800d718: 4603 mov r3, r0 800d71a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 800d71e: e00a b.n 800d736 /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ /* LPTIM2 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d720: 2301 movs r3, #1 800d722: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d726: e006 b.n 800d736 break; 800d728: bf00 nop 800d72a: e004 b.n 800d736 break; 800d72c: bf00 nop 800d72e: e002 b.n 800d736 break; 800d730: bf00 nop 800d732: e000 b.n 800d736 break; 800d734: bf00 nop } if (ret == HAL_OK) 800d736: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d73a: 2b00 cmp r3, #0 800d73c: d10e bne.n 800d75c { /* Set the source of LPTIM2 clock*/ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 800d73e: 4b06 ldr r3, [pc, #24] @ (800d758 ) 800d740: 6d9b ldr r3, [r3, #88] @ 0x58 800d742: f423 51e0 bic.w r1, r3, #7168 @ 0x1c00 800d746: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d74a: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800d74e: 4a02 ldr r2, [pc, #8] @ (800d758 ) 800d750: 430b orrs r3, r1 800d752: 6593 str r3, [r2, #88] @ 0x58 800d754: e006 b.n 800d764 800d756: bf00 nop 800d758: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800d75c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d760: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM345 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 800d764: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d768: e9d3 2300 ldrd r2, r3, [r3] 800d76c: f002 0380 and.w r3, r2, #128 @ 0x80 800d770: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800d774: 2300 movs r3, #0 800d776: f8c7 3094 str.w r3, [r7, #148] @ 0x94 800d77a: e9d7 1224 ldrd r1, r2, [r7, #144] @ 0x90 800d77e: 460b mov r3, r1 800d780: 4313 orrs r3, r2 800d782: d055 beq.n 800d830 { switch (PeriphClkInit->Lptim345ClockSelection) 800d784: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d788: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800d78c: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 800d790: d033 beq.n 800d7fa 800d792: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 800d796: d82c bhi.n 800d7f2 800d798: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800d79c: d02f beq.n 800d7fe 800d79e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800d7a2: d826 bhi.n 800d7f2 800d7a4: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800d7a8: d02b beq.n 800d802 800d7aa: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800d7ae: d820 bhi.n 800d7f2 800d7b0: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800d7b4: d012 beq.n 800d7dc 800d7b6: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800d7ba: d81a bhi.n 800d7f2 800d7bc: 2b00 cmp r3, #0 800d7be: d022 beq.n 800d806 800d7c0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800d7c4: d115 bne.n 800d7f2 case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d7c6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7ca: 3308 adds r3, #8 800d7cc: 2100 movs r1, #0 800d7ce: 4618 mov r0, r3 800d7d0: f001 fca4 bl 800f11c 800d7d4: 4603 mov r3, r0 800d7d6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800d7da: e015 b.n 800d808 case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d7dc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7e0: 3328 adds r3, #40 @ 0x28 800d7e2: 2102 movs r1, #2 800d7e4: 4618 mov r0, r3 800d7e6: f001 fd4b bl 800f280 800d7ea: 4603 mov r3, r0 800d7ec: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800d7f0: e00a b.n 800d808 /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d7f2: 2301 movs r3, #1 800d7f4: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d7f8: e006 b.n 800d808 break; 800d7fa: bf00 nop 800d7fc: e004 b.n 800d808 break; 800d7fe: bf00 nop 800d800: e002 b.n 800d808 break; 800d802: bf00 nop 800d804: e000 b.n 800d808 break; 800d806: bf00 nop } if (ret == HAL_OK) 800d808: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d80c: 2b00 cmp r3, #0 800d80e: d10b bne.n 800d828 { /* Set the source of LPTIM3/4/5 clock */ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 800d810: 4bbb ldr r3, [pc, #748] @ (800db00 ) 800d812: 6d9b ldr r3, [r3, #88] @ 0x58 800d814: f423 4160 bic.w r1, r3, #57344 @ 0xe000 800d818: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d81c: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800d820: 4ab7 ldr r2, [pc, #732] @ (800db00 ) 800d822: 430b orrs r3, r1 800d824: 6593 str r3, [r2, #88] @ 0x58 800d826: e003 b.n 800d830 } else { /* set overall return value */ status = ret; 800d828: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d82c: f887 311e strb.w r3, [r7, #286] @ 0x11e __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); } #else if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 800d830: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d834: e9d3 2300 ldrd r2, r3, [r3] 800d838: f002 0308 and.w r3, r2, #8 800d83c: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800d840: 2300 movs r3, #0 800d842: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800d846: e9d7 1222 ldrd r1, r2, [r7, #136] @ 0x88 800d84a: 460b mov r3, r1 800d84c: 4313 orrs r3, r2 800d84e: d01e beq.n 800d88e { /* Check the parameters */ assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3) 800d850: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d854: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800d858: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d85c: d10c bne.n 800d878 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800d85e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d862: 3328 adds r3, #40 @ 0x28 800d864: 2102 movs r1, #2 800d866: 4618 mov r0, r3 800d868: f001 fd0a bl 800f280 800d86c: 4603 mov r3, r0 800d86e: 2b00 cmp r3, #0 800d870: d002 beq.n 800d878 { status = HAL_ERROR; 800d872: 2301 movs r3, #1 800d874: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 800d878: 4ba1 ldr r3, [pc, #644] @ (800db00 ) 800d87a: 6d5b ldr r3, [r3, #84] @ 0x54 800d87c: f423 5140 bic.w r1, r3, #12288 @ 0x3000 800d880: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d884: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800d888: 4a9d ldr r2, [pc, #628] @ (800db00 ) 800d88a: 430b orrs r3, r1 800d88c: 6553 str r3, [r2, #84] @ 0x54 } #endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 800d88e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d892: e9d3 2300 ldrd r2, r3, [r3] 800d896: f002 0310 and.w r3, r2, #16 800d89a: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800d89e: 2300 movs r3, #0 800d8a0: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800d8a4: e9d7 1220 ldrd r1, r2, [r7, #128] @ 0x80 800d8a8: 460b mov r3, r1 800d8aa: 4313 orrs r3, r2 800d8ac: d01e beq.n 800d8ec { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) 800d8ae: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8b2: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800d8b6: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d8ba: d10c bne.n 800d8d6 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800d8bc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8c0: 3328 adds r3, #40 @ 0x28 800d8c2: 2102 movs r1, #2 800d8c4: 4618 mov r0, r3 800d8c6: f001 fcdb bl 800f280 800d8ca: 4603 mov r3, r0 800d8cc: 2b00 cmp r3, #0 800d8ce: d002 beq.n 800d8d6 { status = HAL_ERROR; 800d8d0: 2301 movs r3, #1 800d8d2: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 800d8d6: 4b8a ldr r3, [pc, #552] @ (800db00 ) 800d8d8: 6d9b ldr r3, [r3, #88] @ 0x58 800d8da: f423 7140 bic.w r1, r3, #768 @ 0x300 800d8de: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8e2: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800d8e6: 4a86 ldr r2, [pc, #536] @ (800db00 ) 800d8e8: 430b orrs r3, r1 800d8ea: 6593 str r3, [r2, #88] @ 0x58 } /*---------------------------- ADC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 800d8ec: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8f0: e9d3 2300 ldrd r2, r3, [r3] 800d8f4: f402 2300 and.w r3, r2, #524288 @ 0x80000 800d8f8: 67bb str r3, [r7, #120] @ 0x78 800d8fa: 2300 movs r3, #0 800d8fc: 67fb str r3, [r7, #124] @ 0x7c 800d8fe: e9d7 121e ldrd r1, r2, [r7, #120] @ 0x78 800d902: 460b mov r3, r1 800d904: 4313 orrs r3, r2 800d906: d03e beq.n 800d986 { switch (PeriphClkInit->AdcClockSelection) 800d908: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d90c: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 800d910: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d914: d022 beq.n 800d95c 800d916: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d91a: d81b bhi.n 800d954 800d91c: 2b00 cmp r3, #0 800d91e: d003 beq.n 800d928 800d920: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800d924: d00b beq.n 800d93e 800d926: e015 b.n 800d954 { case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d928: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d92c: 3308 adds r3, #8 800d92e: 2100 movs r1, #0 800d930: 4618 mov r0, r3 800d932: f001 fbf3 bl 800f11c 800d936: 4603 mov r3, r0 800d938: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 800d93c: e00f b.n 800d95e case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d93e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d942: 3328 adds r3, #40 @ 0x28 800d944: 2102 movs r1, #2 800d946: 4618 mov r0, r3 800d948: f001 fc9a bl 800f280 800d94c: 4603 mov r3, r0 800d94e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 800d952: e004 b.n 800d95e /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ /* ADC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d954: 2301 movs r3, #1 800d956: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d95a: e000 b.n 800d95e break; 800d95c: bf00 nop } if (ret == HAL_OK) 800d95e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d962: 2b00 cmp r3, #0 800d964: d10b bne.n 800d97e { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 800d966: 4b66 ldr r3, [pc, #408] @ (800db00 ) 800d968: 6d9b ldr r3, [r3, #88] @ 0x58 800d96a: f423 3140 bic.w r1, r3, #196608 @ 0x30000 800d96e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d972: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 800d976: 4a62 ldr r2, [pc, #392] @ (800db00 ) 800d978: 430b orrs r3, r1 800d97a: 6593 str r3, [r2, #88] @ 0x58 800d97c: e003 b.n 800d986 } else { /* set overall return value */ status = ret; 800d97e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d982: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ USB Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 800d986: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d98a: e9d3 2300 ldrd r2, r3, [r3] 800d98e: f402 2380 and.w r3, r2, #262144 @ 0x40000 800d992: 673b str r3, [r7, #112] @ 0x70 800d994: 2300 movs r3, #0 800d996: 677b str r3, [r7, #116] @ 0x74 800d998: e9d7 121c ldrd r1, r2, [r7, #112] @ 0x70 800d99c: 460b mov r3, r1 800d99e: 4313 orrs r3, r2 800d9a0: d03b beq.n 800da1a { switch (PeriphClkInit->UsbClockSelection) 800d9a2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d9a6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800d9aa: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800d9ae: d01f beq.n 800d9f0 800d9b0: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800d9b4: d818 bhi.n 800d9e8 800d9b6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800d9ba: d003 beq.n 800d9c4 800d9bc: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800d9c0: d007 beq.n 800d9d2 800d9c2: e011 b.n 800d9e8 { case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ /* Enable USB Clock output generated form System USB . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d9c4: 4b4e ldr r3, [pc, #312] @ (800db00 ) 800d9c6: 6adb ldr r3, [r3, #44] @ 0x2c 800d9c8: 4a4d ldr r2, [pc, #308] @ (800db00 ) 800d9ca: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d9ce: 62d3 str r3, [r2, #44] @ 0x2c /* USB clock source configuration done later after clock selection check */ break; 800d9d0: e00f b.n 800d9f2 case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d9d2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d9d6: 3328 adds r3, #40 @ 0x28 800d9d8: 2101 movs r1, #1 800d9da: 4618 mov r0, r3 800d9dc: f001 fc50 bl 800f280 800d9e0: 4603 mov r3, r0 800d9e2: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USB clock source configuration done later after clock selection check */ break; 800d9e6: e004 b.n 800d9f2 /* HSI48 oscillator is used as source of USB clock */ /* USB clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d9e8: 2301 movs r3, #1 800d9ea: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d9ee: e000 b.n 800d9f2 break; 800d9f0: bf00 nop } if (ret == HAL_OK) 800d9f2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d9f6: 2b00 cmp r3, #0 800d9f8: d10b bne.n 800da12 { /* Set the source of USB clock*/ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 800d9fa: 4b41 ldr r3, [pc, #260] @ (800db00 ) 800d9fc: 6d5b ldr r3, [r3, #84] @ 0x54 800d9fe: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800da02: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da06: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800da0a: 4a3d ldr r2, [pc, #244] @ (800db00 ) 800da0c: 430b orrs r3, r1 800da0e: 6553 str r3, [r2, #84] @ 0x54 800da10: e003 b.n 800da1a } else { /* set overall return value */ status = ret; 800da12: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800da16: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------------- SDMMC Configuration ------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 800da1a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da1e: e9d3 2300 ldrd r2, r3, [r3] 800da22: f402 3380 and.w r3, r2, #65536 @ 0x10000 800da26: 66bb str r3, [r7, #104] @ 0x68 800da28: 2300 movs r3, #0 800da2a: 66fb str r3, [r7, #108] @ 0x6c 800da2c: e9d7 121a ldrd r1, r2, [r7, #104] @ 0x68 800da30: 460b mov r3, r1 800da32: 4313 orrs r3, r2 800da34: d031 beq.n 800da9a { /* Check the parameters */ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); switch (PeriphClkInit->SdmmcClockSelection) 800da36: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da3a: 6d1b ldr r3, [r3, #80] @ 0x50 800da3c: 2b00 cmp r3, #0 800da3e: d003 beq.n 800da48 800da40: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800da44: d007 beq.n 800da56 800da46: e011 b.n 800da6c { case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ /* Enable SDMMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800da48: 4b2d ldr r3, [pc, #180] @ (800db00 ) 800da4a: 6adb ldr r3, [r3, #44] @ 0x2c 800da4c: 4a2c ldr r2, [pc, #176] @ (800db00 ) 800da4e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800da52: 62d3 str r3, [r2, #44] @ 0x2c /* SDMMC clock source configuration done later after clock selection check */ break; 800da54: e00e b.n 800da74 case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800da56: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da5a: 3308 adds r3, #8 800da5c: 2102 movs r1, #2 800da5e: 4618 mov r0, r3 800da60: f001 fb5c bl 800f11c 800da64: 4603 mov r3, r0 800da66: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SDMMC clock source configuration done later after clock selection check */ break; 800da6a: e003 b.n 800da74 default: ret = HAL_ERROR; 800da6c: 2301 movs r3, #1 800da6e: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800da72: bf00 nop } if (ret == HAL_OK) 800da74: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800da78: 2b00 cmp r3, #0 800da7a: d10a bne.n 800da92 { /* Set the source of SDMMC clock*/ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 800da7c: 4b20 ldr r3, [pc, #128] @ (800db00 ) 800da7e: 6cdb ldr r3, [r3, #76] @ 0x4c 800da80: f423 3180 bic.w r1, r3, #65536 @ 0x10000 800da84: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da88: 6d1b ldr r3, [r3, #80] @ 0x50 800da8a: 4a1d ldr r2, [pc, #116] @ (800db00 ) 800da8c: 430b orrs r3, r1 800da8e: 64d3 str r3, [r2, #76] @ 0x4c 800da90: e003 b.n 800da9a } else { /* set overall return value */ status = ret; 800da92: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800da96: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /* LTDC */ /*------------------------------ RNG Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 800da9a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da9e: e9d3 2300 ldrd r2, r3, [r3] 800daa2: f402 3300 and.w r3, r2, #131072 @ 0x20000 800daa6: 663b str r3, [r7, #96] @ 0x60 800daa8: 2300 movs r3, #0 800daaa: 667b str r3, [r7, #100] @ 0x64 800daac: e9d7 1218 ldrd r1, r2, [r7, #96] @ 0x60 800dab0: 460b mov r3, r1 800dab2: 4313 orrs r3, r2 800dab4: d03b beq.n 800db2e { switch (PeriphClkInit->RngClockSelection) 800dab6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800daba: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800dabe: f5b3 7f40 cmp.w r3, #768 @ 0x300 800dac2: d018 beq.n 800daf6 800dac4: f5b3 7f40 cmp.w r3, #768 @ 0x300 800dac8: d811 bhi.n 800daee 800daca: f5b3 7f00 cmp.w r3, #512 @ 0x200 800dace: d014 beq.n 800dafa 800dad0: f5b3 7f00 cmp.w r3, #512 @ 0x200 800dad4: d80b bhi.n 800daee 800dad6: 2b00 cmp r3, #0 800dad8: d014 beq.n 800db04 800dada: f5b3 7f80 cmp.w r3, #256 @ 0x100 800dade: d106 bne.n 800daee { case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ /* Enable RNG Clock output generated form System RNG . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800dae0: 4b07 ldr r3, [pc, #28] @ (800db00 ) 800dae2: 6adb ldr r3, [r3, #44] @ 0x2c 800dae4: 4a06 ldr r2, [pc, #24] @ (800db00 ) 800dae6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800daea: 62d3 str r3, [r2, #44] @ 0x2c /* RNG clock source configuration done later after clock selection check */ break; 800daec: e00b b.n 800db06 /* HSI48 oscillator is used as source of RNG clock */ /* RNG clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800daee: 2301 movs r3, #1 800daf0: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800daf4: e007 b.n 800db06 break; 800daf6: bf00 nop 800daf8: e005 b.n 800db06 break; 800dafa: bf00 nop 800dafc: e003 b.n 800db06 800dafe: bf00 nop 800db00: 58024400 .word 0x58024400 break; 800db04: bf00 nop } if (ret == HAL_OK) 800db06: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800db0a: 2b00 cmp r3, #0 800db0c: d10b bne.n 800db26 { /* Set the source of RNG clock*/ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 800db0e: 4bba ldr r3, [pc, #744] @ (800ddf8 ) 800db10: 6d5b ldr r3, [r3, #84] @ 0x54 800db12: f423 7140 bic.w r1, r3, #768 @ 0x300 800db16: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db1a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800db1e: 4ab6 ldr r2, [pc, #728] @ (800ddf8 ) 800db20: 430b orrs r3, r1 800db22: 6553 str r3, [r2, #84] @ 0x54 800db24: e003 b.n 800db2e } else { /* set overall return value */ status = ret; 800db26: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800db2a: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ SWPMI1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 800db2e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db32: e9d3 2300 ldrd r2, r3, [r3] 800db36: f402 1380 and.w r3, r2, #1048576 @ 0x100000 800db3a: 65bb str r3, [r7, #88] @ 0x58 800db3c: 2300 movs r3, #0 800db3e: 65fb str r3, [r7, #92] @ 0x5c 800db40: e9d7 1216 ldrd r1, r2, [r7, #88] @ 0x58 800db44: 460b mov r3, r1 800db46: 4313 orrs r3, r2 800db48: d009 beq.n 800db5e { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 800db4a: 4bab ldr r3, [pc, #684] @ (800ddf8 ) 800db4c: 6d1b ldr r3, [r3, #80] @ 0x50 800db4e: f023 4100 bic.w r1, r3, #2147483648 @ 0x80000000 800db52: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db56: 6f5b ldr r3, [r3, #116] @ 0x74 800db58: 4aa7 ldr r2, [pc, #668] @ (800ddf8 ) 800db5a: 430b orrs r3, r1 800db5c: 6513 str r3, [r2, #80] @ 0x50 } #if defined(HRTIM1) /*------------------------------ HRTIM1 clock Configuration ----------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) 800db5e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db62: e9d3 2300 ldrd r2, r3, [r3] 800db66: f002 5380 and.w r3, r2, #268435456 @ 0x10000000 800db6a: 653b str r3, [r7, #80] @ 0x50 800db6c: 2300 movs r3, #0 800db6e: 657b str r3, [r7, #84] @ 0x54 800db70: e9d7 1214 ldrd r1, r2, [r7, #80] @ 0x50 800db74: 460b mov r3, r1 800db76: 4313 orrs r3, r2 800db78: d00a beq.n 800db90 { /* Check the parameters */ assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); 800db7a: 4b9f ldr r3, [pc, #636] @ (800ddf8 ) 800db7c: 691b ldr r3, [r3, #16] 800db7e: f423 4180 bic.w r1, r3, #16384 @ 0x4000 800db82: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db86: f8d3 30b8 ldr.w r3, [r3, #184] @ 0xb8 800db8a: 4a9b ldr r2, [pc, #620] @ (800ddf8 ) 800db8c: 430b orrs r3, r1 800db8e: 6113 str r3, [r2, #16] } #endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 800db90: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db94: e9d3 2300 ldrd r2, r3, [r3] 800db98: f402 1300 and.w r3, r2, #2097152 @ 0x200000 800db9c: 64bb str r3, [r7, #72] @ 0x48 800db9e: 2300 movs r3, #0 800dba0: 64fb str r3, [r7, #76] @ 0x4c 800dba2: e9d7 1212 ldrd r1, r2, [r7, #72] @ 0x48 800dba6: 460b mov r3, r1 800dba8: 4313 orrs r3, r2 800dbaa: d009 beq.n 800dbc0 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 800dbac: 4b92 ldr r3, [pc, #584] @ (800ddf8 ) 800dbae: 6d1b ldr r3, [r3, #80] @ 0x50 800dbb0: f023 7180 bic.w r1, r3, #16777216 @ 0x1000000 800dbb4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dbb8: 6edb ldr r3, [r3, #108] @ 0x6c 800dbba: 4a8f ldr r2, [pc, #572] @ (800ddf8 ) 800dbbc: 430b orrs r3, r1 800dbbe: 6513 str r3, [r2, #80] @ 0x50 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); } #endif /* DFSDM2 */ /*------------------------------------ TIM configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 800dbc0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dbc4: e9d3 2300 ldrd r2, r3, [r3] 800dbc8: f002 4380 and.w r3, r2, #1073741824 @ 0x40000000 800dbcc: 643b str r3, [r7, #64] @ 0x40 800dbce: 2300 movs r3, #0 800dbd0: 647b str r3, [r7, #68] @ 0x44 800dbd2: e9d7 1210 ldrd r1, r2, [r7, #64] @ 0x40 800dbd6: 460b mov r3, r1 800dbd8: 4313 orrs r3, r2 800dbda: d00e beq.n 800dbfa { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 800dbdc: 4b86 ldr r3, [pc, #536] @ (800ddf8 ) 800dbde: 691b ldr r3, [r3, #16] 800dbe0: 4a85 ldr r2, [pc, #532] @ (800ddf8 ) 800dbe2: f423 4300 bic.w r3, r3, #32768 @ 0x8000 800dbe6: 6113 str r3, [r2, #16] 800dbe8: 4b83 ldr r3, [pc, #524] @ (800ddf8 ) 800dbea: 6919 ldr r1, [r3, #16] 800dbec: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dbf0: f8d3 30bc ldr.w r3, [r3, #188] @ 0xbc 800dbf4: 4a80 ldr r2, [pc, #512] @ (800ddf8 ) 800dbf6: 430b orrs r3, r1 800dbf8: 6113 str r3, [r2, #16] } /*------------------------------------ CKPER configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 800dbfa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dbfe: e9d3 2300 ldrd r2, r3, [r3] 800dc02: f002 4300 and.w r3, r2, #2147483648 @ 0x80000000 800dc06: 63bb str r3, [r7, #56] @ 0x38 800dc08: 2300 movs r3, #0 800dc0a: 63fb str r3, [r7, #60] @ 0x3c 800dc0c: e9d7 120e ldrd r1, r2, [r7, #56] @ 0x38 800dc10: 460b mov r3, r1 800dc12: 4313 orrs r3, r2 800dc14: d009 beq.n 800dc2a { /* Check the parameters */ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); /* Configure the CKPER clock source */ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 800dc16: 4b78 ldr r3, [pc, #480] @ (800ddf8 ) 800dc18: 6cdb ldr r3, [r3, #76] @ 0x4c 800dc1a: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 800dc1e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc22: 6d5b ldr r3, [r3, #84] @ 0x54 800dc24: 4a74 ldr r2, [pc, #464] @ (800ddf8 ) 800dc26: 430b orrs r3, r1 800dc28: 64d3 str r3, [r2, #76] @ 0x4c } /*------------------------------ CEC Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 800dc2a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc2e: e9d3 2300 ldrd r2, r3, [r3] 800dc32: f402 0300 and.w r3, r2, #8388608 @ 0x800000 800dc36: 633b str r3, [r7, #48] @ 0x30 800dc38: 2300 movs r3, #0 800dc3a: 637b str r3, [r7, #52] @ 0x34 800dc3c: e9d7 120c ldrd r1, r2, [r7, #48] @ 0x30 800dc40: 460b mov r3, r1 800dc42: 4313 orrs r3, r2 800dc44: d00a beq.n 800dc5c { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC interface clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 800dc46: 4b6c ldr r3, [pc, #432] @ (800ddf8 ) 800dc48: 6d5b ldr r3, [r3, #84] @ 0x54 800dc4a: f423 0140 bic.w r1, r3, #12582912 @ 0xc00000 800dc4e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc52: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800dc56: 4a68 ldr r2, [pc, #416] @ (800ddf8 ) 800dc58: 430b orrs r3, r1 800dc5a: 6553 str r3, [r2, #84] @ 0x54 } /*---------------------------- PLL2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) 800dc5c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc60: e9d3 2300 ldrd r2, r3, [r3] 800dc64: 2100 movs r1, #0 800dc66: 62b9 str r1, [r7, #40] @ 0x28 800dc68: f003 0301 and.w r3, r3, #1 800dc6c: 62fb str r3, [r7, #44] @ 0x2c 800dc6e: e9d7 120a ldrd r1, r2, [r7, #40] @ 0x28 800dc72: 460b mov r3, r1 800dc74: 4313 orrs r3, r2 800dc76: d011 beq.n 800dc9c { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800dc78: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc7c: 3308 adds r3, #8 800dc7e: 2100 movs r1, #0 800dc80: 4618 mov r0, r3 800dc82: f001 fa4b bl 800f11c 800dc86: 4603 mov r3, r0 800dc88: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dc8c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc90: 2b00 cmp r3, #0 800dc92: d003 beq.n 800dc9c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dc94: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc98: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) 800dc9c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dca0: e9d3 2300 ldrd r2, r3, [r3] 800dca4: 2100 movs r1, #0 800dca6: 6239 str r1, [r7, #32] 800dca8: f003 0302 and.w r3, r3, #2 800dcac: 627b str r3, [r7, #36] @ 0x24 800dcae: e9d7 1208 ldrd r1, r2, [r7, #32] 800dcb2: 460b mov r3, r1 800dcb4: 4313 orrs r3, r2 800dcb6: d011 beq.n 800dcdc { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800dcb8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dcbc: 3308 adds r3, #8 800dcbe: 2101 movs r1, #1 800dcc0: 4618 mov r0, r3 800dcc2: f001 fa2b bl 800f11c 800dcc6: 4603 mov r3, r0 800dcc8: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dccc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dcd0: 2b00 cmp r3, #0 800dcd2: d003 beq.n 800dcdc /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dcd4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dcd8: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) 800dcdc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dce0: e9d3 2300 ldrd r2, r3, [r3] 800dce4: 2100 movs r1, #0 800dce6: 61b9 str r1, [r7, #24] 800dce8: f003 0304 and.w r3, r3, #4 800dcec: 61fb str r3, [r7, #28] 800dcee: e9d7 1206 ldrd r1, r2, [r7, #24] 800dcf2: 460b mov r3, r1 800dcf4: 4313 orrs r3, r2 800dcf6: d011 beq.n 800dd1c { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800dcf8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dcfc: 3308 adds r3, #8 800dcfe: 2102 movs r1, #2 800dd00: 4618 mov r0, r3 800dd02: f001 fa0b bl 800f11c 800dd06: 4603 mov r3, r0 800dd08: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dd0c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dd10: 2b00 cmp r3, #0 800dd12: d003 beq.n 800dd1c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dd14: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dd18: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- PLL3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) 800dd1c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dd20: e9d3 2300 ldrd r2, r3, [r3] 800dd24: 2100 movs r1, #0 800dd26: 6139 str r1, [r7, #16] 800dd28: f003 0308 and.w r3, r3, #8 800dd2c: 617b str r3, [r7, #20] 800dd2e: e9d7 1204 ldrd r1, r2, [r7, #16] 800dd32: 460b mov r3, r1 800dd34: 4313 orrs r3, r2 800dd36: d011 beq.n 800dd5c { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800dd38: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dd3c: 3328 adds r3, #40 @ 0x28 800dd3e: 2100 movs r1, #0 800dd40: 4618 mov r0, r3 800dd42: f001 fa9d bl 800f280 800dd46: 4603 mov r3, r0 800dd48: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dd4c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dd50: 2b00 cmp r3, #0 800dd52: d003 beq.n 800dd5c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dd54: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dd58: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) 800dd5c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dd60: e9d3 2300 ldrd r2, r3, [r3] 800dd64: 2100 movs r1, #0 800dd66: 60b9 str r1, [r7, #8] 800dd68: f003 0310 and.w r3, r3, #16 800dd6c: 60fb str r3, [r7, #12] 800dd6e: e9d7 1202 ldrd r1, r2, [r7, #8] 800dd72: 460b mov r3, r1 800dd74: 4313 orrs r3, r2 800dd76: d011 beq.n 800dd9c { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800dd78: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dd7c: 3328 adds r3, #40 @ 0x28 800dd7e: 2101 movs r1, #1 800dd80: 4618 mov r0, r3 800dd82: f001 fa7d bl 800f280 800dd86: 4603 mov r3, r0 800dd88: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dd8c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dd90: 2b00 cmp r3, #0 800dd92: d003 beq.n 800dd9c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dd94: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dd98: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) 800dd9c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dda0: e9d3 2300 ldrd r2, r3, [r3] 800dda4: 2100 movs r1, #0 800dda6: 6039 str r1, [r7, #0] 800dda8: f003 0320 and.w r3, r3, #32 800ddac: 607b str r3, [r7, #4] 800ddae: e9d7 1200 ldrd r1, r2, [r7] 800ddb2: 460b mov r3, r1 800ddb4: 4313 orrs r3, r2 800ddb6: d011 beq.n 800dddc { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800ddb8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ddbc: 3328 adds r3, #40 @ 0x28 800ddbe: 2102 movs r1, #2 800ddc0: 4618 mov r0, r3 800ddc2: f001 fa5d bl 800f280 800ddc6: 4603 mov r3, r0 800ddc8: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800ddcc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ddd0: 2b00 cmp r3, #0 800ddd2: d003 beq.n 800dddc /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800ddd4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ddd8: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (status == HAL_OK) 800dddc: f897 311e ldrb.w r3, [r7, #286] @ 0x11e 800dde0: 2b00 cmp r3, #0 800dde2: d101 bne.n 800dde8 { return HAL_OK; 800dde4: 2300 movs r3, #0 800dde6: e000 b.n 800ddea } return HAL_ERROR; 800dde8: 2301 movs r3, #1 } 800ddea: 4618 mov r0, r3 800ddec: f507 7790 add.w r7, r7, #288 @ 0x120 800ddf0: 46bd mov sp, r7 800ddf2: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 800ddf6: bf00 nop 800ddf8: 58024400 .word 0x58024400 0800ddfc : * @retval Frequency in KHz * * (*) : Available on some STM32H7 lines only. */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) { 800ddfc: b580 push {r7, lr} 800ddfe: b090 sub sp, #64 @ 0x40 800de00: af00 add r7, sp, #0 800de02: e9c7 0100 strd r0, r1, [r7] /* This variable is used to store the SAI and CKP clock source */ uint32_t saiclocksource; uint32_t ckpclocksource; uint32_t srcclk; if (PeriphClk == RCC_PERIPHCLK_SAI1) 800de06: e9d7 2300 ldrd r2, r3, [r7] 800de0a: f5a2 7180 sub.w r1, r2, #256 @ 0x100 800de0e: 430b orrs r3, r1 800de10: f040 8094 bne.w 800df3c { saiclocksource = __HAL_RCC_GET_SAI1_SOURCE(); 800de14: 4b9e ldr r3, [pc, #632] @ (800e090 ) 800de16: 6d1b ldr r3, [r3, #80] @ 0x50 800de18: f003 0307 and.w r3, r3, #7 800de1c: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800de1e: 6b3b ldr r3, [r7, #48] @ 0x30 800de20: 2b04 cmp r3, #4 800de22: f200 8087 bhi.w 800df34 800de26: a201 add r2, pc, #4 @ (adr r2, 800de2c ) 800de28: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800de2c: 0800de41 .word 0x0800de41 800de30: 0800de69 .word 0x0800de69 800de34: 0800de91 .word 0x0800de91 800de38: 0800df2d .word 0x0800df2d 800de3c: 0800deb9 .word 0x0800deb9 { case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800de40: 4b93 ldr r3, [pc, #588] @ (800e090 ) 800de42: 681b ldr r3, [r3, #0] 800de44: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800de48: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800de4c: d108 bne.n 800de60 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800de4e: f107 0324 add.w r3, r7, #36 @ 0x24 800de52: 4618 mov r0, r3 800de54: f001 f810 bl 800ee78 frequency = pll1_clocks.PLL1_Q_Frequency; 800de58: 6abb ldr r3, [r7, #40] @ 0x28 800de5a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800de5c: f000 bd45 b.w 800e8ea frequency = 0; 800de60: 2300 movs r3, #0 800de62: 63fb str r3, [r7, #60] @ 0x3c break; 800de64: f000 bd41 b.w 800e8ea } case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800de68: 4b89 ldr r3, [pc, #548] @ (800e090 ) 800de6a: 681b ldr r3, [r3, #0] 800de6c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800de70: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800de74: d108 bne.n 800de88 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800de76: f107 0318 add.w r3, r7, #24 800de7a: 4618 mov r0, r3 800de7c: f000 fd54 bl 800e928 frequency = pll2_clocks.PLL2_P_Frequency; 800de80: 69bb ldr r3, [r7, #24] 800de82: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800de84: f000 bd31 b.w 800e8ea frequency = 0; 800de88: 2300 movs r3, #0 800de8a: 63fb str r3, [r7, #60] @ 0x3c break; 800de8c: f000 bd2d b.w 800e8ea } case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800de90: 4b7f ldr r3, [pc, #508] @ (800e090 ) 800de92: 681b ldr r3, [r3, #0] 800de94: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800de98: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800de9c: d108 bne.n 800deb0 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800de9e: f107 030c add.w r3, r7, #12 800dea2: 4618 mov r0, r3 800dea4: f000 fe94 bl 800ebd0 frequency = pll3_clocks.PLL3_P_Frequency; 800dea8: 68fb ldr r3, [r7, #12] 800deaa: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800deac: f000 bd1d b.w 800e8ea frequency = 0; 800deb0: 2300 movs r3, #0 800deb2: 63fb str r3, [r7, #60] @ 0x3c break; 800deb4: f000 bd19 b.w 800e8ea } case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800deb8: 4b75 ldr r3, [pc, #468] @ (800e090 ) 800deba: 6cdb ldr r3, [r3, #76] @ 0x4c 800debc: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800dec0: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800dec2: 4b73 ldr r3, [pc, #460] @ (800e090 ) 800dec4: 681b ldr r3, [r3, #0] 800dec6: f003 0304 and.w r3, r3, #4 800deca: 2b04 cmp r3, #4 800decc: d10c bne.n 800dee8 800dece: 6b7b ldr r3, [r7, #52] @ 0x34 800ded0: 2b00 cmp r3, #0 800ded2: d109 bne.n 800dee8 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800ded4: 4b6e ldr r3, [pc, #440] @ (800e090 ) 800ded6: 681b ldr r3, [r3, #0] 800ded8: 08db lsrs r3, r3, #3 800deda: f003 0303 and.w r3, r3, #3 800dede: 4a6d ldr r2, [pc, #436] @ (800e094 ) 800dee0: fa22 f303 lsr.w r3, r2, r3 800dee4: 63fb str r3, [r7, #60] @ 0x3c 800dee6: e01f b.n 800df28 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800dee8: 4b69 ldr r3, [pc, #420] @ (800e090 ) 800deea: 681b ldr r3, [r3, #0] 800deec: f403 7380 and.w r3, r3, #256 @ 0x100 800def0: f5b3 7f80 cmp.w r3, #256 @ 0x100 800def4: d106 bne.n 800df04 800def6: 6b7b ldr r3, [r7, #52] @ 0x34 800def8: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800defc: d102 bne.n 800df04 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800defe: 4b66 ldr r3, [pc, #408] @ (800e098 ) 800df00: 63fb str r3, [r7, #60] @ 0x3c 800df02: e011 b.n 800df28 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800df04: 4b62 ldr r3, [pc, #392] @ (800e090 ) 800df06: 681b ldr r3, [r3, #0] 800df08: f403 3300 and.w r3, r3, #131072 @ 0x20000 800df0c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800df10: d106 bne.n 800df20 800df12: 6b7b ldr r3, [r7, #52] @ 0x34 800df14: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800df18: d102 bne.n 800df20 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800df1a: 4b60 ldr r3, [pc, #384] @ (800e09c ) 800df1c: 63fb str r3, [r7, #60] @ 0x3c 800df1e: e003 b.n 800df28 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800df20: 2300 movs r3, #0 800df22: 63fb str r3, [r7, #60] @ 0x3c } break; 800df24: f000 bce1 b.w 800e8ea 800df28: f000 bcdf b.w 800e8ea } case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ { frequency = EXTERNAL_CLOCK_VALUE; 800df2c: 4b5c ldr r3, [pc, #368] @ (800e0a0 ) 800df2e: 63fb str r3, [r7, #60] @ 0x3c break; 800df30: f000 bcdb b.w 800e8ea } default : { frequency = 0; 800df34: 2300 movs r3, #0 800df36: 63fb str r3, [r7, #60] @ 0x3c break; 800df38: f000 bcd7 b.w 800e8ea } } } #if defined(SAI3) else if (PeriphClk == RCC_PERIPHCLK_SAI23) 800df3c: e9d7 2300 ldrd r2, r3, [r7] 800df40: f5a2 7100 sub.w r1, r2, #512 @ 0x200 800df44: 430b orrs r3, r1 800df46: f040 80ad bne.w 800e0a4 { saiclocksource = __HAL_RCC_GET_SAI23_SOURCE(); 800df4a: 4b51 ldr r3, [pc, #324] @ (800e090 ) 800df4c: 6d1b ldr r3, [r3, #80] @ 0x50 800df4e: f403 73e0 and.w r3, r3, #448 @ 0x1c0 800df52: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800df54: 6b3b ldr r3, [r7, #48] @ 0x30 800df56: f5b3 7f80 cmp.w r3, #256 @ 0x100 800df5a: d056 beq.n 800e00a 800df5c: 6b3b ldr r3, [r7, #48] @ 0x30 800df5e: f5b3 7f80 cmp.w r3, #256 @ 0x100 800df62: f200 8090 bhi.w 800e086 800df66: 6b3b ldr r3, [r7, #48] @ 0x30 800df68: 2bc0 cmp r3, #192 @ 0xc0 800df6a: f000 8088 beq.w 800e07e 800df6e: 6b3b ldr r3, [r7, #48] @ 0x30 800df70: 2bc0 cmp r3, #192 @ 0xc0 800df72: f200 8088 bhi.w 800e086 800df76: 6b3b ldr r3, [r7, #48] @ 0x30 800df78: 2b80 cmp r3, #128 @ 0x80 800df7a: d032 beq.n 800dfe2 800df7c: 6b3b ldr r3, [r7, #48] @ 0x30 800df7e: 2b80 cmp r3, #128 @ 0x80 800df80: f200 8081 bhi.w 800e086 800df84: 6b3b ldr r3, [r7, #48] @ 0x30 800df86: 2b00 cmp r3, #0 800df88: d003 beq.n 800df92 800df8a: 6b3b ldr r3, [r7, #48] @ 0x30 800df8c: 2b40 cmp r3, #64 @ 0x40 800df8e: d014 beq.n 800dfba 800df90: e079 b.n 800e086 { case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800df92: 4b3f ldr r3, [pc, #252] @ (800e090 ) 800df94: 681b ldr r3, [r3, #0] 800df96: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800df9a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800df9e: d108 bne.n 800dfb2 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800dfa0: f107 0324 add.w r3, r7, #36 @ 0x24 800dfa4: 4618 mov r0, r3 800dfa6: f000 ff67 bl 800ee78 frequency = pll1_clocks.PLL1_Q_Frequency; 800dfaa: 6abb ldr r3, [r7, #40] @ 0x28 800dfac: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dfae: f000 bc9c b.w 800e8ea frequency = 0; 800dfb2: 2300 movs r3, #0 800dfb4: 63fb str r3, [r7, #60] @ 0x3c break; 800dfb6: f000 bc98 b.w 800e8ea } case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800dfba: 4b35 ldr r3, [pc, #212] @ (800e090 ) 800dfbc: 681b ldr r3, [r3, #0] 800dfbe: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800dfc2: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800dfc6: d108 bne.n 800dfda { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800dfc8: f107 0318 add.w r3, r7, #24 800dfcc: 4618 mov r0, r3 800dfce: f000 fcab bl 800e928 frequency = pll2_clocks.PLL2_P_Frequency; 800dfd2: 69bb ldr r3, [r7, #24] 800dfd4: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dfd6: f000 bc88 b.w 800e8ea frequency = 0; 800dfda: 2300 movs r3, #0 800dfdc: 63fb str r3, [r7, #60] @ 0x3c break; 800dfde: f000 bc84 b.w 800e8ea } case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800dfe2: 4b2b ldr r3, [pc, #172] @ (800e090 ) 800dfe4: 681b ldr r3, [r3, #0] 800dfe6: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800dfea: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800dfee: d108 bne.n 800e002 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800dff0: f107 030c add.w r3, r7, #12 800dff4: 4618 mov r0, r3 800dff6: f000 fdeb bl 800ebd0 frequency = pll3_clocks.PLL3_P_Frequency; 800dffa: 68fb ldr r3, [r7, #12] 800dffc: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dffe: f000 bc74 b.w 800e8ea frequency = 0; 800e002: 2300 movs r3, #0 800e004: 63fb str r3, [r7, #60] @ 0x3c break; 800e006: f000 bc70 b.w 800e8ea } case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e00a: 4b21 ldr r3, [pc, #132] @ (800e090 ) 800e00c: 6cdb ldr r3, [r3, #76] @ 0x4c 800e00e: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e012: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e014: 4b1e ldr r3, [pc, #120] @ (800e090 ) 800e016: 681b ldr r3, [r3, #0] 800e018: f003 0304 and.w r3, r3, #4 800e01c: 2b04 cmp r3, #4 800e01e: d10c bne.n 800e03a 800e020: 6b7b ldr r3, [r7, #52] @ 0x34 800e022: 2b00 cmp r3, #0 800e024: d109 bne.n 800e03a { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e026: 4b1a ldr r3, [pc, #104] @ (800e090 ) 800e028: 681b ldr r3, [r3, #0] 800e02a: 08db lsrs r3, r3, #3 800e02c: f003 0303 and.w r3, r3, #3 800e030: 4a18 ldr r2, [pc, #96] @ (800e094 ) 800e032: fa22 f303 lsr.w r3, r2, r3 800e036: 63fb str r3, [r7, #60] @ 0x3c 800e038: e01f b.n 800e07a } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e03a: 4b15 ldr r3, [pc, #84] @ (800e090 ) 800e03c: 681b ldr r3, [r3, #0] 800e03e: f403 7380 and.w r3, r3, #256 @ 0x100 800e042: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e046: d106 bne.n 800e056 800e048: 6b7b ldr r3, [r7, #52] @ 0x34 800e04a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e04e: d102 bne.n 800e056 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e050: 4b11 ldr r3, [pc, #68] @ (800e098 ) 800e052: 63fb str r3, [r7, #60] @ 0x3c 800e054: e011 b.n 800e07a } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e056: 4b0e ldr r3, [pc, #56] @ (800e090 ) 800e058: 681b ldr r3, [r3, #0] 800e05a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e05e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e062: d106 bne.n 800e072 800e064: 6b7b ldr r3, [r7, #52] @ 0x34 800e066: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e06a: d102 bne.n 800e072 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e06c: 4b0b ldr r3, [pc, #44] @ (800e09c ) 800e06e: 63fb str r3, [r7, #60] @ 0x3c 800e070: e003 b.n 800e07a } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e072: 2300 movs r3, #0 800e074: 63fb str r3, [r7, #60] @ 0x3c } break; 800e076: f000 bc38 b.w 800e8ea 800e07a: f000 bc36 b.w 800e8ea } case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ { frequency = EXTERNAL_CLOCK_VALUE; 800e07e: 4b08 ldr r3, [pc, #32] @ (800e0a0 ) 800e080: 63fb str r3, [r7, #60] @ 0x3c break; 800e082: f000 bc32 b.w 800e8ea } default : { frequency = 0; 800e086: 2300 movs r3, #0 800e088: 63fb str r3, [r7, #60] @ 0x3c break; 800e08a: f000 bc2e b.w 800e8ea 800e08e: bf00 nop 800e090: 58024400 .word 0x58024400 800e094: 03d09000 .word 0x03d09000 800e098: 003d0900 .word 0x003d0900 800e09c: 017d7840 .word 0x017d7840 800e0a0: 00bb8000 .word 0x00bb8000 } } #endif #if defined(SAI4) else if (PeriphClk == RCC_PERIPHCLK_SAI4A) 800e0a4: e9d7 2300 ldrd r2, r3, [r7] 800e0a8: f5a2 6180 sub.w r1, r2, #1024 @ 0x400 800e0ac: 430b orrs r3, r1 800e0ae: f040 809c bne.w 800e1ea { saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE(); 800e0b2: 4b9e ldr r3, [pc, #632] @ (800e32c ) 800e0b4: 6d9b ldr r3, [r3, #88] @ 0x58 800e0b6: f403 0360 and.w r3, r3, #14680064 @ 0xe00000 800e0ba: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800e0bc: 6b3b ldr r3, [r7, #48] @ 0x30 800e0be: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800e0c2: d054 beq.n 800e16e 800e0c4: 6b3b ldr r3, [r7, #48] @ 0x30 800e0c6: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800e0ca: f200 808b bhi.w 800e1e4 800e0ce: 6b3b ldr r3, [r7, #48] @ 0x30 800e0d0: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800e0d4: f000 8083 beq.w 800e1de 800e0d8: 6b3b ldr r3, [r7, #48] @ 0x30 800e0da: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800e0de: f200 8081 bhi.w 800e1e4 800e0e2: 6b3b ldr r3, [r7, #48] @ 0x30 800e0e4: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800e0e8: d02f beq.n 800e14a 800e0ea: 6b3b ldr r3, [r7, #48] @ 0x30 800e0ec: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800e0f0: d878 bhi.n 800e1e4 800e0f2: 6b3b ldr r3, [r7, #48] @ 0x30 800e0f4: 2b00 cmp r3, #0 800e0f6: d004 beq.n 800e102 800e0f8: 6b3b ldr r3, [r7, #48] @ 0x30 800e0fa: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800e0fe: d012 beq.n 800e126 800e100: e070 b.n 800e1e4 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e102: 4b8a ldr r3, [pc, #552] @ (800e32c ) 800e104: 681b ldr r3, [r3, #0] 800e106: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e10a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e10e: d107 bne.n 800e120 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e110: f107 0324 add.w r3, r7, #36 @ 0x24 800e114: 4618 mov r0, r3 800e116: f000 feaf bl 800ee78 frequency = pll1_clocks.PLL1_Q_Frequency; 800e11a: 6abb ldr r3, [r7, #40] @ 0x28 800e11c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e11e: e3e4 b.n 800e8ea frequency = 0; 800e120: 2300 movs r3, #0 800e122: 63fb str r3, [r7, #60] @ 0x3c break; 800e124: e3e1 b.n 800e8ea } case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e126: 4b81 ldr r3, [pc, #516] @ (800e32c ) 800e128: 681b ldr r3, [r3, #0] 800e12a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e12e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e132: d107 bne.n 800e144 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e134: f107 0318 add.w r3, r7, #24 800e138: 4618 mov r0, r3 800e13a: f000 fbf5 bl 800e928 frequency = pll2_clocks.PLL2_P_Frequency; 800e13e: 69bb ldr r3, [r7, #24] 800e140: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e142: e3d2 b.n 800e8ea frequency = 0; 800e144: 2300 movs r3, #0 800e146: 63fb str r3, [r7, #60] @ 0x3c break; 800e148: e3cf b.n 800e8ea } case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e14a: 4b78 ldr r3, [pc, #480] @ (800e32c ) 800e14c: 681b ldr r3, [r3, #0] 800e14e: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e152: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e156: d107 bne.n 800e168 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e158: f107 030c add.w r3, r7, #12 800e15c: 4618 mov r0, r3 800e15e: f000 fd37 bl 800ebd0 frequency = pll3_clocks.PLL3_P_Frequency; 800e162: 68fb ldr r3, [r7, #12] 800e164: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e166: e3c0 b.n 800e8ea frequency = 0; 800e168: 2300 movs r3, #0 800e16a: 63fb str r3, [r7, #60] @ 0x3c break; 800e16c: e3bd b.n 800e8ea } case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e16e: 4b6f ldr r3, [pc, #444] @ (800e32c ) 800e170: 6cdb ldr r3, [r3, #76] @ 0x4c 800e172: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e176: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e178: 4b6c ldr r3, [pc, #432] @ (800e32c ) 800e17a: 681b ldr r3, [r3, #0] 800e17c: f003 0304 and.w r3, r3, #4 800e180: 2b04 cmp r3, #4 800e182: d10c bne.n 800e19e 800e184: 6b7b ldr r3, [r7, #52] @ 0x34 800e186: 2b00 cmp r3, #0 800e188: d109 bne.n 800e19e { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e18a: 4b68 ldr r3, [pc, #416] @ (800e32c ) 800e18c: 681b ldr r3, [r3, #0] 800e18e: 08db lsrs r3, r3, #3 800e190: f003 0303 and.w r3, r3, #3 800e194: 4a66 ldr r2, [pc, #408] @ (800e330 ) 800e196: fa22 f303 lsr.w r3, r2, r3 800e19a: 63fb str r3, [r7, #60] @ 0x3c 800e19c: e01e b.n 800e1dc } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e19e: 4b63 ldr r3, [pc, #396] @ (800e32c ) 800e1a0: 681b ldr r3, [r3, #0] 800e1a2: f403 7380 and.w r3, r3, #256 @ 0x100 800e1a6: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e1aa: d106 bne.n 800e1ba 800e1ac: 6b7b ldr r3, [r7, #52] @ 0x34 800e1ae: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e1b2: d102 bne.n 800e1ba { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e1b4: 4b5f ldr r3, [pc, #380] @ (800e334 ) 800e1b6: 63fb str r3, [r7, #60] @ 0x3c 800e1b8: e010 b.n 800e1dc } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e1ba: 4b5c ldr r3, [pc, #368] @ (800e32c ) 800e1bc: 681b ldr r3, [r3, #0] 800e1be: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e1c2: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e1c6: d106 bne.n 800e1d6 800e1c8: 6b7b ldr r3, [r7, #52] @ 0x34 800e1ca: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e1ce: d102 bne.n 800e1d6 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e1d0: 4b59 ldr r3, [pc, #356] @ (800e338 ) 800e1d2: 63fb str r3, [r7, #60] @ 0x3c 800e1d4: e002 b.n 800e1dc } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e1d6: 2300 movs r3, #0 800e1d8: 63fb str r3, [r7, #60] @ 0x3c } break; 800e1da: e386 b.n 800e8ea 800e1dc: e385 b.n 800e8ea } case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ { frequency = EXTERNAL_CLOCK_VALUE; 800e1de: 4b57 ldr r3, [pc, #348] @ (800e33c ) 800e1e0: 63fb str r3, [r7, #60] @ 0x3c break; 800e1e2: e382 b.n 800e8ea } default : { frequency = 0; 800e1e4: 2300 movs r3, #0 800e1e6: 63fb str r3, [r7, #60] @ 0x3c break; 800e1e8: e37f b.n 800e8ea } } } else if (PeriphClk == RCC_PERIPHCLK_SAI4B) 800e1ea: e9d7 2300 ldrd r2, r3, [r7] 800e1ee: f5a2 6100 sub.w r1, r2, #2048 @ 0x800 800e1f2: 430b orrs r3, r1 800e1f4: f040 80a7 bne.w 800e346 { saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE(); 800e1f8: 4b4c ldr r3, [pc, #304] @ (800e32c ) 800e1fa: 6d9b ldr r3, [r3, #88] @ 0x58 800e1fc: f003 63e0 and.w r3, r3, #117440512 @ 0x7000000 800e200: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800e202: 6b3b ldr r3, [r7, #48] @ 0x30 800e204: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800e208: d055 beq.n 800e2b6 800e20a: 6b3b ldr r3, [r7, #48] @ 0x30 800e20c: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800e210: f200 8096 bhi.w 800e340 800e214: 6b3b ldr r3, [r7, #48] @ 0x30 800e216: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800e21a: f000 8084 beq.w 800e326 800e21e: 6b3b ldr r3, [r7, #48] @ 0x30 800e220: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800e224: f200 808c bhi.w 800e340 800e228: 6b3b ldr r3, [r7, #48] @ 0x30 800e22a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e22e: d030 beq.n 800e292 800e230: 6b3b ldr r3, [r7, #48] @ 0x30 800e232: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e236: f200 8083 bhi.w 800e340 800e23a: 6b3b ldr r3, [r7, #48] @ 0x30 800e23c: 2b00 cmp r3, #0 800e23e: d004 beq.n 800e24a 800e240: 6b3b ldr r3, [r7, #48] @ 0x30 800e242: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800e246: d012 beq.n 800e26e 800e248: e07a b.n 800e340 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e24a: 4b38 ldr r3, [pc, #224] @ (800e32c ) 800e24c: 681b ldr r3, [r3, #0] 800e24e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e252: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e256: d107 bne.n 800e268 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e258: f107 0324 add.w r3, r7, #36 @ 0x24 800e25c: 4618 mov r0, r3 800e25e: f000 fe0b bl 800ee78 frequency = pll1_clocks.PLL1_Q_Frequency; 800e262: 6abb ldr r3, [r7, #40] @ 0x28 800e264: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e266: e340 b.n 800e8ea frequency = 0; 800e268: 2300 movs r3, #0 800e26a: 63fb str r3, [r7, #60] @ 0x3c break; 800e26c: e33d b.n 800e8ea } case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e26e: 4b2f ldr r3, [pc, #188] @ (800e32c ) 800e270: 681b ldr r3, [r3, #0] 800e272: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e276: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e27a: d107 bne.n 800e28c { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e27c: f107 0318 add.w r3, r7, #24 800e280: 4618 mov r0, r3 800e282: f000 fb51 bl 800e928 frequency = pll2_clocks.PLL2_P_Frequency; 800e286: 69bb ldr r3, [r7, #24] 800e288: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e28a: e32e b.n 800e8ea frequency = 0; 800e28c: 2300 movs r3, #0 800e28e: 63fb str r3, [r7, #60] @ 0x3c break; 800e290: e32b b.n 800e8ea } case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e292: 4b26 ldr r3, [pc, #152] @ (800e32c ) 800e294: 681b ldr r3, [r3, #0] 800e296: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e29a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e29e: d107 bne.n 800e2b0 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e2a0: f107 030c add.w r3, r7, #12 800e2a4: 4618 mov r0, r3 800e2a6: f000 fc93 bl 800ebd0 frequency = pll3_clocks.PLL3_P_Frequency; 800e2aa: 68fb ldr r3, [r7, #12] 800e2ac: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e2ae: e31c b.n 800e8ea frequency = 0; 800e2b0: 2300 movs r3, #0 800e2b2: 63fb str r3, [r7, #60] @ 0x3c break; 800e2b4: e319 b.n 800e8ea } case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e2b6: 4b1d ldr r3, [pc, #116] @ (800e32c ) 800e2b8: 6cdb ldr r3, [r3, #76] @ 0x4c 800e2ba: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e2be: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e2c0: 4b1a ldr r3, [pc, #104] @ (800e32c ) 800e2c2: 681b ldr r3, [r3, #0] 800e2c4: f003 0304 and.w r3, r3, #4 800e2c8: 2b04 cmp r3, #4 800e2ca: d10c bne.n 800e2e6 800e2cc: 6b7b ldr r3, [r7, #52] @ 0x34 800e2ce: 2b00 cmp r3, #0 800e2d0: d109 bne.n 800e2e6 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e2d2: 4b16 ldr r3, [pc, #88] @ (800e32c ) 800e2d4: 681b ldr r3, [r3, #0] 800e2d6: 08db lsrs r3, r3, #3 800e2d8: f003 0303 and.w r3, r3, #3 800e2dc: 4a14 ldr r2, [pc, #80] @ (800e330 ) 800e2de: fa22 f303 lsr.w r3, r2, r3 800e2e2: 63fb str r3, [r7, #60] @ 0x3c 800e2e4: e01e b.n 800e324 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e2e6: 4b11 ldr r3, [pc, #68] @ (800e32c ) 800e2e8: 681b ldr r3, [r3, #0] 800e2ea: f403 7380 and.w r3, r3, #256 @ 0x100 800e2ee: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e2f2: d106 bne.n 800e302 800e2f4: 6b7b ldr r3, [r7, #52] @ 0x34 800e2f6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e2fa: d102 bne.n 800e302 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e2fc: 4b0d ldr r3, [pc, #52] @ (800e334 ) 800e2fe: 63fb str r3, [r7, #60] @ 0x3c 800e300: e010 b.n 800e324 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e302: 4b0a ldr r3, [pc, #40] @ (800e32c ) 800e304: 681b ldr r3, [r3, #0] 800e306: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e30a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e30e: d106 bne.n 800e31e 800e310: 6b7b ldr r3, [r7, #52] @ 0x34 800e312: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e316: d102 bne.n 800e31e { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e318: 4b07 ldr r3, [pc, #28] @ (800e338 ) 800e31a: 63fb str r3, [r7, #60] @ 0x3c 800e31c: e002 b.n 800e324 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e31e: 2300 movs r3, #0 800e320: 63fb str r3, [r7, #60] @ 0x3c } break; 800e322: e2e2 b.n 800e8ea 800e324: e2e1 b.n 800e8ea } case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ { frequency = EXTERNAL_CLOCK_VALUE; 800e326: 4b05 ldr r3, [pc, #20] @ (800e33c ) 800e328: 63fb str r3, [r7, #60] @ 0x3c break; 800e32a: e2de b.n 800e8ea 800e32c: 58024400 .word 0x58024400 800e330: 03d09000 .word 0x03d09000 800e334: 003d0900 .word 0x003d0900 800e338: 017d7840 .word 0x017d7840 800e33c: 00bb8000 .word 0x00bb8000 } default : { frequency = 0; 800e340: 2300 movs r3, #0 800e342: 63fb str r3, [r7, #60] @ 0x3c break; 800e344: e2d1 b.n 800e8ea } } } #endif /*SAI4*/ else if (PeriphClk == RCC_PERIPHCLK_SPI123) 800e346: e9d7 2300 ldrd r2, r3, [r7] 800e34a: f5a2 5180 sub.w r1, r2, #4096 @ 0x1000 800e34e: 430b orrs r3, r1 800e350: f040 809c bne.w 800e48c { /* Get SPI1/2/3 clock source */ srcclk = __HAL_RCC_GET_SPI123_SOURCE(); 800e354: 4b93 ldr r3, [pc, #588] @ (800e5a4 ) 800e356: 6d1b ldr r3, [r3, #80] @ 0x50 800e358: f403 43e0 and.w r3, r3, #28672 @ 0x7000 800e35c: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e35e: 6bbb ldr r3, [r7, #56] @ 0x38 800e360: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800e364: d054 beq.n 800e410 800e366: 6bbb ldr r3, [r7, #56] @ 0x38 800e368: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800e36c: f200 808b bhi.w 800e486 800e370: 6bbb ldr r3, [r7, #56] @ 0x38 800e372: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800e376: f000 8083 beq.w 800e480 800e37a: 6bbb ldr r3, [r7, #56] @ 0x38 800e37c: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800e380: f200 8081 bhi.w 800e486 800e384: 6bbb ldr r3, [r7, #56] @ 0x38 800e386: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800e38a: d02f beq.n 800e3ec 800e38c: 6bbb ldr r3, [r7, #56] @ 0x38 800e38e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800e392: d878 bhi.n 800e486 800e394: 6bbb ldr r3, [r7, #56] @ 0x38 800e396: 2b00 cmp r3, #0 800e398: d004 beq.n 800e3a4 800e39a: 6bbb ldr r3, [r7, #56] @ 0x38 800e39c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800e3a0: d012 beq.n 800e3c8 800e3a2: e070 b.n 800e486 { case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e3a4: 4b7f ldr r3, [pc, #508] @ (800e5a4 ) 800e3a6: 681b ldr r3, [r3, #0] 800e3a8: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e3ac: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e3b0: d107 bne.n 800e3c2 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e3b2: f107 0324 add.w r3, r7, #36 @ 0x24 800e3b6: 4618 mov r0, r3 800e3b8: f000 fd5e bl 800ee78 frequency = pll1_clocks.PLL1_Q_Frequency; 800e3bc: 6abb ldr r3, [r7, #40] @ 0x28 800e3be: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e3c0: e293 b.n 800e8ea frequency = 0; 800e3c2: 2300 movs r3, #0 800e3c4: 63fb str r3, [r7, #60] @ 0x3c break; 800e3c6: e290 b.n 800e8ea } case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e3c8: 4b76 ldr r3, [pc, #472] @ (800e5a4 ) 800e3ca: 681b ldr r3, [r3, #0] 800e3cc: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e3d0: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e3d4: d107 bne.n 800e3e6 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e3d6: f107 0318 add.w r3, r7, #24 800e3da: 4618 mov r0, r3 800e3dc: f000 faa4 bl 800e928 frequency = pll2_clocks.PLL2_P_Frequency; 800e3e0: 69bb ldr r3, [r7, #24] 800e3e2: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e3e4: e281 b.n 800e8ea frequency = 0; 800e3e6: 2300 movs r3, #0 800e3e8: 63fb str r3, [r7, #60] @ 0x3c break; 800e3ea: e27e b.n 800e8ea } case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e3ec: 4b6d ldr r3, [pc, #436] @ (800e5a4 ) 800e3ee: 681b ldr r3, [r3, #0] 800e3f0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e3f4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e3f8: d107 bne.n 800e40a { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e3fa: f107 030c add.w r3, r7, #12 800e3fe: 4618 mov r0, r3 800e400: f000 fbe6 bl 800ebd0 frequency = pll3_clocks.PLL3_P_Frequency; 800e404: 68fb ldr r3, [r7, #12] 800e406: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e408: e26f b.n 800e8ea frequency = 0; 800e40a: 2300 movs r3, #0 800e40c: 63fb str r3, [r7, #60] @ 0x3c break; 800e40e: e26c b.n 800e8ea } case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e410: 4b64 ldr r3, [pc, #400] @ (800e5a4 ) 800e412: 6cdb ldr r3, [r3, #76] @ 0x4c 800e414: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e418: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e41a: 4b62 ldr r3, [pc, #392] @ (800e5a4 ) 800e41c: 681b ldr r3, [r3, #0] 800e41e: f003 0304 and.w r3, r3, #4 800e422: 2b04 cmp r3, #4 800e424: d10c bne.n 800e440 800e426: 6b7b ldr r3, [r7, #52] @ 0x34 800e428: 2b00 cmp r3, #0 800e42a: d109 bne.n 800e440 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e42c: 4b5d ldr r3, [pc, #372] @ (800e5a4 ) 800e42e: 681b ldr r3, [r3, #0] 800e430: 08db lsrs r3, r3, #3 800e432: f003 0303 and.w r3, r3, #3 800e436: 4a5c ldr r2, [pc, #368] @ (800e5a8 ) 800e438: fa22 f303 lsr.w r3, r2, r3 800e43c: 63fb str r3, [r7, #60] @ 0x3c 800e43e: e01e b.n 800e47e } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e440: 4b58 ldr r3, [pc, #352] @ (800e5a4 ) 800e442: 681b ldr r3, [r3, #0] 800e444: f403 7380 and.w r3, r3, #256 @ 0x100 800e448: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e44c: d106 bne.n 800e45c 800e44e: 6b7b ldr r3, [r7, #52] @ 0x34 800e450: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e454: d102 bne.n 800e45c { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e456: 4b55 ldr r3, [pc, #340] @ (800e5ac ) 800e458: 63fb str r3, [r7, #60] @ 0x3c 800e45a: e010 b.n 800e47e } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e45c: 4b51 ldr r3, [pc, #324] @ (800e5a4 ) 800e45e: 681b ldr r3, [r3, #0] 800e460: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e464: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e468: d106 bne.n 800e478 800e46a: 6b7b ldr r3, [r7, #52] @ 0x34 800e46c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e470: d102 bne.n 800e478 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e472: 4b4f ldr r3, [pc, #316] @ (800e5b0 ) 800e474: 63fb str r3, [r7, #60] @ 0x3c 800e476: e002 b.n 800e47e } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e478: 2300 movs r3, #0 800e47a: 63fb str r3, [r7, #60] @ 0x3c } break; 800e47c: e235 b.n 800e8ea 800e47e: e234 b.n 800e8ea } case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ { frequency = EXTERNAL_CLOCK_VALUE; 800e480: 4b4c ldr r3, [pc, #304] @ (800e5b4 ) 800e482: 63fb str r3, [r7, #60] @ 0x3c break; 800e484: e231 b.n 800e8ea } default : { frequency = 0; 800e486: 2300 movs r3, #0 800e488: 63fb str r3, [r7, #60] @ 0x3c break; 800e48a: e22e b.n 800e8ea } } } else if (PeriphClk == RCC_PERIPHCLK_SPI45) 800e48c: e9d7 2300 ldrd r2, r3, [r7] 800e490: f5a2 5100 sub.w r1, r2, #8192 @ 0x2000 800e494: 430b orrs r3, r1 800e496: f040 808f bne.w 800e5b8 { /* Get SPI45 clock source */ srcclk = __HAL_RCC_GET_SPI45_SOURCE(); 800e49a: 4b42 ldr r3, [pc, #264] @ (800e5a4 ) 800e49c: 6d1b ldr r3, [r3, #80] @ 0x50 800e49e: f403 23e0 and.w r3, r3, #458752 @ 0x70000 800e4a2: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e4a4: 6bbb ldr r3, [r7, #56] @ 0x38 800e4a6: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800e4aa: d06b beq.n 800e584 800e4ac: 6bbb ldr r3, [r7, #56] @ 0x38 800e4ae: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800e4b2: d874 bhi.n 800e59e 800e4b4: 6bbb ldr r3, [r7, #56] @ 0x38 800e4b6: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800e4ba: d056 beq.n 800e56a 800e4bc: 6bbb ldr r3, [r7, #56] @ 0x38 800e4be: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800e4c2: d86c bhi.n 800e59e 800e4c4: 6bbb ldr r3, [r7, #56] @ 0x38 800e4c6: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800e4ca: d03b beq.n 800e544 800e4cc: 6bbb ldr r3, [r7, #56] @ 0x38 800e4ce: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800e4d2: d864 bhi.n 800e59e 800e4d4: 6bbb ldr r3, [r7, #56] @ 0x38 800e4d6: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e4da: d021 beq.n 800e520 800e4dc: 6bbb ldr r3, [r7, #56] @ 0x38 800e4de: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e4e2: d85c bhi.n 800e59e 800e4e4: 6bbb ldr r3, [r7, #56] @ 0x38 800e4e6: 2b00 cmp r3, #0 800e4e8: d004 beq.n 800e4f4 800e4ea: 6bbb ldr r3, [r7, #56] @ 0x38 800e4ec: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e4f0: d004 beq.n 800e4fc 800e4f2: e054 b.n 800e59e { case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */ { frequency = HAL_RCC_GetPCLK1Freq(); 800e4f4: f7fe fa26 bl 800c944 800e4f8: 63f8 str r0, [r7, #60] @ 0x3c break; 800e4fa: e1f6 b.n 800e8ea } case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e4fc: 4b29 ldr r3, [pc, #164] @ (800e5a4 ) 800e4fe: 681b ldr r3, [r3, #0] 800e500: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e504: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e508: d107 bne.n 800e51a { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e50a: f107 0318 add.w r3, r7, #24 800e50e: 4618 mov r0, r3 800e510: f000 fa0a bl 800e928 frequency = pll2_clocks.PLL2_Q_Frequency; 800e514: 69fb ldr r3, [r7, #28] 800e516: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e518: e1e7 b.n 800e8ea frequency = 0; 800e51a: 2300 movs r3, #0 800e51c: 63fb str r3, [r7, #60] @ 0x3c break; 800e51e: e1e4 b.n 800e8ea } case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e520: 4b20 ldr r3, [pc, #128] @ (800e5a4 ) 800e522: 681b ldr r3, [r3, #0] 800e524: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e528: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e52c: d107 bne.n 800e53e { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e52e: f107 030c add.w r3, r7, #12 800e532: 4618 mov r0, r3 800e534: f000 fb4c bl 800ebd0 frequency = pll3_clocks.PLL3_Q_Frequency; 800e538: 693b ldr r3, [r7, #16] 800e53a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e53c: e1d5 b.n 800e8ea frequency = 0; 800e53e: 2300 movs r3, #0 800e540: 63fb str r3, [r7, #60] @ 0x3c break; 800e542: e1d2 b.n 800e8ea } case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800e544: 4b17 ldr r3, [pc, #92] @ (800e5a4 ) 800e546: 681b ldr r3, [r3, #0] 800e548: f003 0304 and.w r3, r3, #4 800e54c: 2b04 cmp r3, #4 800e54e: d109 bne.n 800e564 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e550: 4b14 ldr r3, [pc, #80] @ (800e5a4 ) 800e552: 681b ldr r3, [r3, #0] 800e554: 08db lsrs r3, r3, #3 800e556: f003 0303 and.w r3, r3, #3 800e55a: 4a13 ldr r2, [pc, #76] @ (800e5a8 ) 800e55c: fa22 f303 lsr.w r3, r2, r3 800e560: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e562: e1c2 b.n 800e8ea frequency = 0; 800e564: 2300 movs r3, #0 800e566: 63fb str r3, [r7, #60] @ 0x3c break; 800e568: e1bf b.n 800e8ea } case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 800e56a: 4b0e ldr r3, [pc, #56] @ (800e5a4 ) 800e56c: 681b ldr r3, [r3, #0] 800e56e: f403 7380 and.w r3, r3, #256 @ 0x100 800e572: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e576: d102 bne.n 800e57e { frequency = CSI_VALUE; 800e578: 4b0c ldr r3, [pc, #48] @ (800e5ac ) 800e57a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e57c: e1b5 b.n 800e8ea frequency = 0; 800e57e: 2300 movs r3, #0 800e580: 63fb str r3, [r7, #60] @ 0x3c break; 800e582: e1b2 b.n 800e8ea } case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e584: 4b07 ldr r3, [pc, #28] @ (800e5a4 ) 800e586: 681b ldr r3, [r3, #0] 800e588: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e58c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e590: d102 bne.n 800e598 { frequency = HSE_VALUE; 800e592: 4b07 ldr r3, [pc, #28] @ (800e5b0 ) 800e594: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e596: e1a8 b.n 800e8ea frequency = 0; 800e598: 2300 movs r3, #0 800e59a: 63fb str r3, [r7, #60] @ 0x3c break; 800e59c: e1a5 b.n 800e8ea } default : { frequency = 0; 800e59e: 2300 movs r3, #0 800e5a0: 63fb str r3, [r7, #60] @ 0x3c break; 800e5a2: e1a2 b.n 800e8ea 800e5a4: 58024400 .word 0x58024400 800e5a8: 03d09000 .word 0x03d09000 800e5ac: 003d0900 .word 0x003d0900 800e5b0: 017d7840 .word 0x017d7840 800e5b4: 00bb8000 .word 0x00bb8000 } } } else if (PeriphClk == RCC_PERIPHCLK_ADC) 800e5b8: e9d7 2300 ldrd r2, r3, [r7] 800e5bc: f5a2 2100 sub.w r1, r2, #524288 @ 0x80000 800e5c0: 430b orrs r3, r1 800e5c2: d173 bne.n 800e6ac { /* Get ADC clock source */ srcclk = __HAL_RCC_GET_ADC_SOURCE(); 800e5c4: 4b9c ldr r3, [pc, #624] @ (800e838 ) 800e5c6: 6d9b ldr r3, [r3, #88] @ 0x58 800e5c8: f403 3340 and.w r3, r3, #196608 @ 0x30000 800e5cc: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e5ce: 6bbb ldr r3, [r7, #56] @ 0x38 800e5d0: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e5d4: d02f beq.n 800e636 800e5d6: 6bbb ldr r3, [r7, #56] @ 0x38 800e5d8: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e5dc: d863 bhi.n 800e6a6 800e5de: 6bbb ldr r3, [r7, #56] @ 0x38 800e5e0: 2b00 cmp r3, #0 800e5e2: d004 beq.n 800e5ee 800e5e4: 6bbb ldr r3, [r7, #56] @ 0x38 800e5e6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e5ea: d012 beq.n 800e612 800e5ec: e05b b.n 800e6a6 { case RCC_ADCCLKSOURCE_PLL2: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e5ee: 4b92 ldr r3, [pc, #584] @ (800e838 ) 800e5f0: 681b ldr r3, [r3, #0] 800e5f2: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e5f6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e5fa: d107 bne.n 800e60c { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e5fc: f107 0318 add.w r3, r7, #24 800e600: 4618 mov r0, r3 800e602: f000 f991 bl 800e928 frequency = pll2_clocks.PLL2_P_Frequency; 800e606: 69bb ldr r3, [r7, #24] 800e608: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e60a: e16e b.n 800e8ea frequency = 0; 800e60c: 2300 movs r3, #0 800e60e: 63fb str r3, [r7, #60] @ 0x3c break; 800e610: e16b b.n 800e8ea } case RCC_ADCCLKSOURCE_PLL3: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e612: 4b89 ldr r3, [pc, #548] @ (800e838 ) 800e614: 681b ldr r3, [r3, #0] 800e616: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e61a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e61e: d107 bne.n 800e630 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e620: f107 030c add.w r3, r7, #12 800e624: 4618 mov r0, r3 800e626: f000 fad3 bl 800ebd0 frequency = pll3_clocks.PLL3_R_Frequency; 800e62a: 697b ldr r3, [r7, #20] 800e62c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e62e: e15c b.n 800e8ea frequency = 0; 800e630: 2300 movs r3, #0 800e632: 63fb str r3, [r7, #60] @ 0x3c break; 800e634: e159 b.n 800e8ea } case RCC_ADCCLKSOURCE_CLKP: { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e636: 4b80 ldr r3, [pc, #512] @ (800e838 ) 800e638: 6cdb ldr r3, [r3, #76] @ 0x4c 800e63a: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e63e: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e640: 4b7d ldr r3, [pc, #500] @ (800e838 ) 800e642: 681b ldr r3, [r3, #0] 800e644: f003 0304 and.w r3, r3, #4 800e648: 2b04 cmp r3, #4 800e64a: d10c bne.n 800e666 800e64c: 6b7b ldr r3, [r7, #52] @ 0x34 800e64e: 2b00 cmp r3, #0 800e650: d109 bne.n 800e666 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e652: 4b79 ldr r3, [pc, #484] @ (800e838 ) 800e654: 681b ldr r3, [r3, #0] 800e656: 08db lsrs r3, r3, #3 800e658: f003 0303 and.w r3, r3, #3 800e65c: 4a77 ldr r2, [pc, #476] @ (800e83c ) 800e65e: fa22 f303 lsr.w r3, r2, r3 800e662: 63fb str r3, [r7, #60] @ 0x3c 800e664: e01e b.n 800e6a4 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e666: 4b74 ldr r3, [pc, #464] @ (800e838 ) 800e668: 681b ldr r3, [r3, #0] 800e66a: f403 7380 and.w r3, r3, #256 @ 0x100 800e66e: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e672: d106 bne.n 800e682 800e674: 6b7b ldr r3, [r7, #52] @ 0x34 800e676: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e67a: d102 bne.n 800e682 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e67c: 4b70 ldr r3, [pc, #448] @ (800e840 ) 800e67e: 63fb str r3, [r7, #60] @ 0x3c 800e680: e010 b.n 800e6a4 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e682: 4b6d ldr r3, [pc, #436] @ (800e838 ) 800e684: 681b ldr r3, [r3, #0] 800e686: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e68a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e68e: d106 bne.n 800e69e 800e690: 6b7b ldr r3, [r7, #52] @ 0x34 800e692: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e696: d102 bne.n 800e69e { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e698: 4b6a ldr r3, [pc, #424] @ (800e844 ) 800e69a: 63fb str r3, [r7, #60] @ 0x3c 800e69c: e002 b.n 800e6a4 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e69e: 2300 movs r3, #0 800e6a0: 63fb str r3, [r7, #60] @ 0x3c } break; 800e6a2: e122 b.n 800e8ea 800e6a4: e121 b.n 800e8ea } default : { frequency = 0; 800e6a6: 2300 movs r3, #0 800e6a8: 63fb str r3, [r7, #60] @ 0x3c break; 800e6aa: e11e b.n 800e8ea } } } else if (PeriphClk == RCC_PERIPHCLK_SDMMC) 800e6ac: e9d7 2300 ldrd r2, r3, [r7] 800e6b0: f5a2 3180 sub.w r1, r2, #65536 @ 0x10000 800e6b4: 430b orrs r3, r1 800e6b6: d133 bne.n 800e720 { /* Get SDMMC clock source */ srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); 800e6b8: 4b5f ldr r3, [pc, #380] @ (800e838 ) 800e6ba: 6cdb ldr r3, [r3, #76] @ 0x4c 800e6bc: f403 3380 and.w r3, r3, #65536 @ 0x10000 800e6c0: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e6c2: 6bbb ldr r3, [r7, #56] @ 0x38 800e6c4: 2b00 cmp r3, #0 800e6c6: d004 beq.n 800e6d2 800e6c8: 6bbb ldr r3, [r7, #56] @ 0x38 800e6ca: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e6ce: d012 beq.n 800e6f6 800e6d0: e023 b.n 800e71a { case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e6d2: 4b59 ldr r3, [pc, #356] @ (800e838 ) 800e6d4: 681b ldr r3, [r3, #0] 800e6d6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e6da: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e6de: d107 bne.n 800e6f0 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e6e0: f107 0324 add.w r3, r7, #36 @ 0x24 800e6e4: 4618 mov r0, r3 800e6e6: f000 fbc7 bl 800ee78 frequency = pll1_clocks.PLL1_Q_Frequency; 800e6ea: 6abb ldr r3, [r7, #40] @ 0x28 800e6ec: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e6ee: e0fc b.n 800e8ea frequency = 0; 800e6f0: 2300 movs r3, #0 800e6f2: 63fb str r3, [r7, #60] @ 0x3c break; 800e6f4: e0f9 b.n 800e8ea } case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e6f6: 4b50 ldr r3, [pc, #320] @ (800e838 ) 800e6f8: 681b ldr r3, [r3, #0] 800e6fa: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e6fe: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e702: d107 bne.n 800e714 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e704: f107 0318 add.w r3, r7, #24 800e708: 4618 mov r0, r3 800e70a: f000 f90d bl 800e928 frequency = pll2_clocks.PLL2_R_Frequency; 800e70e: 6a3b ldr r3, [r7, #32] 800e710: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e712: e0ea b.n 800e8ea frequency = 0; 800e714: 2300 movs r3, #0 800e716: 63fb str r3, [r7, #60] @ 0x3c break; 800e718: e0e7 b.n 800e8ea } default : { frequency = 0; 800e71a: 2300 movs r3, #0 800e71c: 63fb str r3, [r7, #60] @ 0x3c break; 800e71e: e0e4 b.n 800e8ea } } } else if (PeriphClk == RCC_PERIPHCLK_SPI6) 800e720: e9d7 2300 ldrd r2, r3, [r7] 800e724: f5a2 4180 sub.w r1, r2, #16384 @ 0x4000 800e728: 430b orrs r3, r1 800e72a: f040 808d bne.w 800e848 { /* Get SPI6 clock source */ srcclk = __HAL_RCC_GET_SPI6_SOURCE(); 800e72e: 4b42 ldr r3, [pc, #264] @ (800e838 ) 800e730: 6d9b ldr r3, [r3, #88] @ 0x58 800e732: f003 43e0 and.w r3, r3, #1879048192 @ 0x70000000 800e736: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e738: 6bbb ldr r3, [r7, #56] @ 0x38 800e73a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800e73e: d06b beq.n 800e818 800e740: 6bbb ldr r3, [r7, #56] @ 0x38 800e742: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800e746: d874 bhi.n 800e832 800e748: 6bbb ldr r3, [r7, #56] @ 0x38 800e74a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800e74e: d056 beq.n 800e7fe 800e750: 6bbb ldr r3, [r7, #56] @ 0x38 800e752: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800e756: d86c bhi.n 800e832 800e758: 6bbb ldr r3, [r7, #56] @ 0x38 800e75a: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800e75e: d03b beq.n 800e7d8 800e760: 6bbb ldr r3, [r7, #56] @ 0x38 800e762: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800e766: d864 bhi.n 800e832 800e768: 6bbb ldr r3, [r7, #56] @ 0x38 800e76a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e76e: d021 beq.n 800e7b4 800e770: 6bbb ldr r3, [r7, #56] @ 0x38 800e772: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e776: d85c bhi.n 800e832 800e778: 6bbb ldr r3, [r7, #56] @ 0x38 800e77a: 2b00 cmp r3, #0 800e77c: d004 beq.n 800e788 800e77e: 6bbb ldr r3, [r7, #56] @ 0x38 800e780: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e784: d004 beq.n 800e790 800e786: e054 b.n 800e832 { case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ { frequency = HAL_RCCEx_GetD3PCLK1Freq(); 800e788: f000 f8b8 bl 800e8fc 800e78c: 63f8 str r0, [r7, #60] @ 0x3c break; 800e78e: e0ac b.n 800e8ea } case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e790: 4b29 ldr r3, [pc, #164] @ (800e838 ) 800e792: 681b ldr r3, [r3, #0] 800e794: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e798: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e79c: d107 bne.n 800e7ae { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e79e: f107 0318 add.w r3, r7, #24 800e7a2: 4618 mov r0, r3 800e7a4: f000 f8c0 bl 800e928 frequency = pll2_clocks.PLL2_Q_Frequency; 800e7a8: 69fb ldr r3, [r7, #28] 800e7aa: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e7ac: e09d b.n 800e8ea frequency = 0; 800e7ae: 2300 movs r3, #0 800e7b0: 63fb str r3, [r7, #60] @ 0x3c break; 800e7b2: e09a b.n 800e8ea } case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e7b4: 4b20 ldr r3, [pc, #128] @ (800e838 ) 800e7b6: 681b ldr r3, [r3, #0] 800e7b8: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e7bc: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e7c0: d107 bne.n 800e7d2 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e7c2: f107 030c add.w r3, r7, #12 800e7c6: 4618 mov r0, r3 800e7c8: f000 fa02 bl 800ebd0 frequency = pll3_clocks.PLL3_Q_Frequency; 800e7cc: 693b ldr r3, [r7, #16] 800e7ce: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e7d0: e08b b.n 800e8ea frequency = 0; 800e7d2: 2300 movs r3, #0 800e7d4: 63fb str r3, [r7, #60] @ 0x3c break; 800e7d6: e088 b.n 800e8ea } case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800e7d8: 4b17 ldr r3, [pc, #92] @ (800e838 ) 800e7da: 681b ldr r3, [r3, #0] 800e7dc: f003 0304 and.w r3, r3, #4 800e7e0: 2b04 cmp r3, #4 800e7e2: d109 bne.n 800e7f8 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e7e4: 4b14 ldr r3, [pc, #80] @ (800e838 ) 800e7e6: 681b ldr r3, [r3, #0] 800e7e8: 08db lsrs r3, r3, #3 800e7ea: f003 0303 and.w r3, r3, #3 800e7ee: 4a13 ldr r2, [pc, #76] @ (800e83c ) 800e7f0: fa22 f303 lsr.w r3, r2, r3 800e7f4: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e7f6: e078 b.n 800e8ea frequency = 0; 800e7f8: 2300 movs r3, #0 800e7fa: 63fb str r3, [r7, #60] @ 0x3c break; 800e7fc: e075 b.n 800e8ea } case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 800e7fe: 4b0e ldr r3, [pc, #56] @ (800e838 ) 800e800: 681b ldr r3, [r3, #0] 800e802: f403 7380 and.w r3, r3, #256 @ 0x100 800e806: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e80a: d102 bne.n 800e812 { frequency = CSI_VALUE; 800e80c: 4b0c ldr r3, [pc, #48] @ (800e840 ) 800e80e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e810: e06b b.n 800e8ea frequency = 0; 800e812: 2300 movs r3, #0 800e814: 63fb str r3, [r7, #60] @ 0x3c break; 800e816: e068 b.n 800e8ea } case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e818: 4b07 ldr r3, [pc, #28] @ (800e838 ) 800e81a: 681b ldr r3, [r3, #0] 800e81c: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e820: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e824: d102 bne.n 800e82c { frequency = HSE_VALUE; 800e826: 4b07 ldr r3, [pc, #28] @ (800e844 ) 800e828: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e82a: e05e b.n 800e8ea frequency = 0; 800e82c: 2300 movs r3, #0 800e82e: 63fb str r3, [r7, #60] @ 0x3c break; 800e830: e05b b.n 800e8ea break; } #endif /* RCC_SPI6CLKSOURCE_PIN */ default : { frequency = 0; 800e832: 2300 movs r3, #0 800e834: 63fb str r3, [r7, #60] @ 0x3c break; 800e836: e058 b.n 800e8ea 800e838: 58024400 .word 0x58024400 800e83c: 03d09000 .word 0x03d09000 800e840: 003d0900 .word 0x003d0900 800e844: 017d7840 .word 0x017d7840 } } } else if (PeriphClk == RCC_PERIPHCLK_FDCAN) 800e848: e9d7 2300 ldrd r2, r3, [r7] 800e84c: f5a2 4100 sub.w r1, r2, #32768 @ 0x8000 800e850: 430b orrs r3, r1 800e852: d148 bne.n 800e8e6 { /* Get FDCAN clock source */ srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); 800e854: 4b27 ldr r3, [pc, #156] @ (800e8f4 ) 800e856: 6d1b ldr r3, [r3, #80] @ 0x50 800e858: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e85c: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e85e: 6bbb ldr r3, [r7, #56] @ 0x38 800e860: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e864: d02a beq.n 800e8bc 800e866: 6bbb ldr r3, [r7, #56] @ 0x38 800e868: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e86c: d838 bhi.n 800e8e0 800e86e: 6bbb ldr r3, [r7, #56] @ 0x38 800e870: 2b00 cmp r3, #0 800e872: d004 beq.n 800e87e 800e874: 6bbb ldr r3, [r7, #56] @ 0x38 800e876: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e87a: d00d beq.n 800e898 800e87c: e030 b.n 800e8e0 { case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e87e: 4b1d ldr r3, [pc, #116] @ (800e8f4 ) 800e880: 681b ldr r3, [r3, #0] 800e882: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e886: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e88a: d102 bne.n 800e892 { frequency = HSE_VALUE; 800e88c: 4b1a ldr r3, [pc, #104] @ (800e8f8 ) 800e88e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e890: e02b b.n 800e8ea frequency = 0; 800e892: 2300 movs r3, #0 800e894: 63fb str r3, [r7, #60] @ 0x3c break; 800e896: e028 b.n 800e8ea } case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e898: 4b16 ldr r3, [pc, #88] @ (800e8f4 ) 800e89a: 681b ldr r3, [r3, #0] 800e89c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e8a0: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e8a4: d107 bne.n 800e8b6 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e8a6: f107 0324 add.w r3, r7, #36 @ 0x24 800e8aa: 4618 mov r0, r3 800e8ac: f000 fae4 bl 800ee78 frequency = pll1_clocks.PLL1_Q_Frequency; 800e8b0: 6abb ldr r3, [r7, #40] @ 0x28 800e8b2: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e8b4: e019 b.n 800e8ea frequency = 0; 800e8b6: 2300 movs r3, #0 800e8b8: 63fb str r3, [r7, #60] @ 0x3c break; 800e8ba: e016 b.n 800e8ea } case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e8bc: 4b0d ldr r3, [pc, #52] @ (800e8f4 ) 800e8be: 681b ldr r3, [r3, #0] 800e8c0: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e8c4: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e8c8: d107 bne.n 800e8da { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e8ca: f107 0318 add.w r3, r7, #24 800e8ce: 4618 mov r0, r3 800e8d0: f000 f82a bl 800e928 frequency = pll2_clocks.PLL2_Q_Frequency; 800e8d4: 69fb ldr r3, [r7, #28] 800e8d6: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e8d8: e007 b.n 800e8ea frequency = 0; 800e8da: 2300 movs r3, #0 800e8dc: 63fb str r3, [r7, #60] @ 0x3c break; 800e8de: e004 b.n 800e8ea } default : { frequency = 0; 800e8e0: 2300 movs r3, #0 800e8e2: 63fb str r3, [r7, #60] @ 0x3c break; 800e8e4: e001 b.n 800e8ea } } } else { frequency = 0; 800e8e6: 2300 movs r3, #0 800e8e8: 63fb str r3, [r7, #60] @ 0x3c } return frequency; 800e8ea: 6bfb ldr r3, [r7, #60] @ 0x3c } 800e8ec: 4618 mov r0, r3 800e8ee: 3740 adds r7, #64 @ 0x40 800e8f0: 46bd mov sp, r7 800e8f2: bd80 pop {r7, pc} 800e8f4: 58024400 .word 0x58024400 800e8f8: 017d7840 .word 0x017d7840 0800e8fc : * @note Each time D3PCLK1 changes, this function must be called to update the * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval D3PCLK1 frequency */ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) { 800e8fc: b580 push {r7, lr} 800e8fe: af00 add r7, sp, #0 #if defined(RCC_D3CFGR_D3PPRE) /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); 800e900: f7fd fff0 bl 800c8e4 800e904: 4602 mov r2, r0 800e906: 4b06 ldr r3, [pc, #24] @ (800e920 ) 800e908: 6a1b ldr r3, [r3, #32] 800e90a: 091b lsrs r3, r3, #4 800e90c: f003 0307 and.w r3, r3, #7 800e910: 4904 ldr r1, [pc, #16] @ (800e924 ) 800e912: 5ccb ldrb r3, [r1, r3] 800e914: f003 031f and.w r3, r3, #31 800e918: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); #endif } 800e91c: 4618 mov r0, r3 800e91e: bd80 pop {r7, pc} 800e920: 58024400 .word 0x58024400 800e924: 0801878c .word 0x0801878c 0800e928 : * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL2_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) { 800e928: b480 push {r7} 800e92a: b089 sub sp, #36 @ 0x24 800e92c: af00 add r7, sp, #0 800e92e: 6078 str r0, [r7, #4] float_t fracn2, pll2vco; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N PLL2xCLK = PLL2_VCO / PLL2x */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800e930: 4ba1 ldr r3, [pc, #644] @ (800ebb8 ) 800e932: 6a9b ldr r3, [r3, #40] @ 0x28 800e934: f003 0303 and.w r3, r3, #3 800e938: 61bb str r3, [r7, #24] pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); 800e93a: 4b9f ldr r3, [pc, #636] @ (800ebb8 ) 800e93c: 6a9b ldr r3, [r3, #40] @ 0x28 800e93e: 0b1b lsrs r3, r3, #12 800e940: f003 033f and.w r3, r3, #63 @ 0x3f 800e944: 617b str r3, [r7, #20] pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; 800e946: 4b9c ldr r3, [pc, #624] @ (800ebb8 ) 800e948: 6adb ldr r3, [r3, #44] @ 0x2c 800e94a: 091b lsrs r3, r3, #4 800e94c: f003 0301 and.w r3, r3, #1 800e950: 613b str r3, [r7, #16] fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); 800e952: 4b99 ldr r3, [pc, #612] @ (800ebb8 ) 800e954: 6bdb ldr r3, [r3, #60] @ 0x3c 800e956: 08db lsrs r3, r3, #3 800e958: f3c3 030c ubfx r3, r3, #0, #13 800e95c: 693a ldr r2, [r7, #16] 800e95e: fb02 f303 mul.w r3, r2, r3 800e962: ee07 3a90 vmov s15, r3 800e966: eef8 7a67 vcvt.f32.u32 s15, s15 800e96a: edc7 7a03 vstr s15, [r7, #12] if (pll2m != 0U) 800e96e: 697b ldr r3, [r7, #20] 800e970: 2b00 cmp r3, #0 800e972: f000 8111 beq.w 800eb98 { switch (pllsource) 800e976: 69bb ldr r3, [r7, #24] 800e978: 2b02 cmp r3, #2 800e97a: f000 8083 beq.w 800ea84 800e97e: 69bb ldr r3, [r7, #24] 800e980: 2b02 cmp r3, #2 800e982: f200 80a1 bhi.w 800eac8 800e986: 69bb ldr r3, [r7, #24] 800e988: 2b00 cmp r3, #0 800e98a: d003 beq.n 800e994 800e98c: 69bb ldr r3, [r7, #24] 800e98e: 2b01 cmp r3, #1 800e990: d056 beq.n 800ea40 800e992: e099 b.n 800eac8 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800e994: 4b88 ldr r3, [pc, #544] @ (800ebb8 ) 800e996: 681b ldr r3, [r3, #0] 800e998: f003 0320 and.w r3, r3, #32 800e99c: 2b00 cmp r3, #0 800e99e: d02d beq.n 800e9fc { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e9a0: 4b85 ldr r3, [pc, #532] @ (800ebb8 ) 800e9a2: 681b ldr r3, [r3, #0] 800e9a4: 08db lsrs r3, r3, #3 800e9a6: f003 0303 and.w r3, r3, #3 800e9aa: 4a84 ldr r2, [pc, #528] @ (800ebbc ) 800e9ac: fa22 f303 lsr.w r3, r2, r3 800e9b0: 60bb str r3, [r7, #8] pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e9b2: 68bb ldr r3, [r7, #8] 800e9b4: ee07 3a90 vmov s15, r3 800e9b8: eef8 6a67 vcvt.f32.u32 s13, s15 800e9bc: 697b ldr r3, [r7, #20] 800e9be: ee07 3a90 vmov s15, r3 800e9c2: eef8 7a67 vcvt.f32.u32 s15, s15 800e9c6: ee86 7aa7 vdiv.f32 s14, s13, s15 800e9ca: 4b7b ldr r3, [pc, #492] @ (800ebb8 ) 800e9cc: 6b9b ldr r3, [r3, #56] @ 0x38 800e9ce: f3c3 0308 ubfx r3, r3, #0, #9 800e9d2: ee07 3a90 vmov s15, r3 800e9d6: eef8 6a67 vcvt.f32.u32 s13, s15 800e9da: ed97 6a03 vldr s12, [r7, #12] 800e9de: eddf 5a78 vldr s11, [pc, #480] @ 800ebc0 800e9e2: eec6 7a25 vdiv.f32 s15, s12, s11 800e9e6: ee76 7aa7 vadd.f32 s15, s13, s15 800e9ea: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e9ee: ee77 7aa6 vadd.f32 s15, s15, s13 800e9f2: ee67 7a27 vmul.f32 s15, s14, s15 800e9f6: edc7 7a07 vstr s15, [r7, #28] } else { pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); } break; 800e9fa: e087 b.n 800eb0c pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e9fc: 697b ldr r3, [r7, #20] 800e9fe: ee07 3a90 vmov s15, r3 800ea02: eef8 7a67 vcvt.f32.u32 s15, s15 800ea06: eddf 6a6f vldr s13, [pc, #444] @ 800ebc4 800ea0a: ee86 7aa7 vdiv.f32 s14, s13, s15 800ea0e: 4b6a ldr r3, [pc, #424] @ (800ebb8 ) 800ea10: 6b9b ldr r3, [r3, #56] @ 0x38 800ea12: f3c3 0308 ubfx r3, r3, #0, #9 800ea16: ee07 3a90 vmov s15, r3 800ea1a: eef8 6a67 vcvt.f32.u32 s13, s15 800ea1e: ed97 6a03 vldr s12, [r7, #12] 800ea22: eddf 5a67 vldr s11, [pc, #412] @ 800ebc0 800ea26: eec6 7a25 vdiv.f32 s15, s12, s11 800ea2a: ee76 7aa7 vadd.f32 s15, s13, s15 800ea2e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ea32: ee77 7aa6 vadd.f32 s15, s15, s13 800ea36: ee67 7a27 vmul.f32 s15, s14, s15 800ea3a: edc7 7a07 vstr s15, [r7, #28] break; 800ea3e: e065 b.n 800eb0c case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800ea40: 697b ldr r3, [r7, #20] 800ea42: ee07 3a90 vmov s15, r3 800ea46: eef8 7a67 vcvt.f32.u32 s15, s15 800ea4a: eddf 6a5f vldr s13, [pc, #380] @ 800ebc8 800ea4e: ee86 7aa7 vdiv.f32 s14, s13, s15 800ea52: 4b59 ldr r3, [pc, #356] @ (800ebb8 ) 800ea54: 6b9b ldr r3, [r3, #56] @ 0x38 800ea56: f3c3 0308 ubfx r3, r3, #0, #9 800ea5a: ee07 3a90 vmov s15, r3 800ea5e: eef8 6a67 vcvt.f32.u32 s13, s15 800ea62: ed97 6a03 vldr s12, [r7, #12] 800ea66: eddf 5a56 vldr s11, [pc, #344] @ 800ebc0 800ea6a: eec6 7a25 vdiv.f32 s15, s12, s11 800ea6e: ee76 7aa7 vadd.f32 s15, s13, s15 800ea72: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ea76: ee77 7aa6 vadd.f32 s15, s15, s13 800ea7a: ee67 7a27 vmul.f32 s15, s14, s15 800ea7e: edc7 7a07 vstr s15, [r7, #28] break; 800ea82: e043 b.n 800eb0c case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800ea84: 697b ldr r3, [r7, #20] 800ea86: ee07 3a90 vmov s15, r3 800ea8a: eef8 7a67 vcvt.f32.u32 s15, s15 800ea8e: eddf 6a4f vldr s13, [pc, #316] @ 800ebcc 800ea92: ee86 7aa7 vdiv.f32 s14, s13, s15 800ea96: 4b48 ldr r3, [pc, #288] @ (800ebb8 ) 800ea98: 6b9b ldr r3, [r3, #56] @ 0x38 800ea9a: f3c3 0308 ubfx r3, r3, #0, #9 800ea9e: ee07 3a90 vmov s15, r3 800eaa2: eef8 6a67 vcvt.f32.u32 s13, s15 800eaa6: ed97 6a03 vldr s12, [r7, #12] 800eaaa: eddf 5a45 vldr s11, [pc, #276] @ 800ebc0 800eaae: eec6 7a25 vdiv.f32 s15, s12, s11 800eab2: ee76 7aa7 vadd.f32 s15, s13, s15 800eab6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800eaba: ee77 7aa6 vadd.f32 s15, s15, s13 800eabe: ee67 7a27 vmul.f32 s15, s14, s15 800eac2: edc7 7a07 vstr s15, [r7, #28] break; 800eac6: e021 b.n 800eb0c default: pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800eac8: 697b ldr r3, [r7, #20] 800eaca: ee07 3a90 vmov s15, r3 800eace: eef8 7a67 vcvt.f32.u32 s15, s15 800ead2: eddf 6a3d vldr s13, [pc, #244] @ 800ebc8 800ead6: ee86 7aa7 vdiv.f32 s14, s13, s15 800eada: 4b37 ldr r3, [pc, #220] @ (800ebb8 ) 800eadc: 6b9b ldr r3, [r3, #56] @ 0x38 800eade: f3c3 0308 ubfx r3, r3, #0, #9 800eae2: ee07 3a90 vmov s15, r3 800eae6: eef8 6a67 vcvt.f32.u32 s13, s15 800eaea: ed97 6a03 vldr s12, [r7, #12] 800eaee: eddf 5a34 vldr s11, [pc, #208] @ 800ebc0 800eaf2: eec6 7a25 vdiv.f32 s15, s12, s11 800eaf6: ee76 7aa7 vadd.f32 s15, s13, s15 800eafa: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800eafe: ee77 7aa6 vadd.f32 s15, s15, s13 800eb02: ee67 7a27 vmul.f32 s15, s14, s15 800eb06: edc7 7a07 vstr s15, [r7, #28] break; 800eb0a: bf00 nop } PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; 800eb0c: 4b2a ldr r3, [pc, #168] @ (800ebb8 ) 800eb0e: 6b9b ldr r3, [r3, #56] @ 0x38 800eb10: 0a5b lsrs r3, r3, #9 800eb12: f003 037f and.w r3, r3, #127 @ 0x7f 800eb16: ee07 3a90 vmov s15, r3 800eb1a: eef8 7a67 vcvt.f32.u32 s15, s15 800eb1e: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800eb22: ee37 7a87 vadd.f32 s14, s15, s14 800eb26: edd7 6a07 vldr s13, [r7, #28] 800eb2a: eec6 7a87 vdiv.f32 s15, s13, s14 800eb2e: eefc 7ae7 vcvt.u32.f32 s15, s15 800eb32: ee17 2a90 vmov r2, s15 800eb36: 687b ldr r3, [r7, #4] 800eb38: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; 800eb3a: 4b1f ldr r3, [pc, #124] @ (800ebb8 ) 800eb3c: 6b9b ldr r3, [r3, #56] @ 0x38 800eb3e: 0c1b lsrs r3, r3, #16 800eb40: f003 037f and.w r3, r3, #127 @ 0x7f 800eb44: ee07 3a90 vmov s15, r3 800eb48: eef8 7a67 vcvt.f32.u32 s15, s15 800eb4c: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800eb50: ee37 7a87 vadd.f32 s14, s15, s14 800eb54: edd7 6a07 vldr s13, [r7, #28] 800eb58: eec6 7a87 vdiv.f32 s15, s13, s14 800eb5c: eefc 7ae7 vcvt.u32.f32 s15, s15 800eb60: ee17 2a90 vmov r2, s15 800eb64: 687b ldr r3, [r7, #4] 800eb66: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; 800eb68: 4b13 ldr r3, [pc, #76] @ (800ebb8 ) 800eb6a: 6b9b ldr r3, [r3, #56] @ 0x38 800eb6c: 0e1b lsrs r3, r3, #24 800eb6e: f003 037f and.w r3, r3, #127 @ 0x7f 800eb72: ee07 3a90 vmov s15, r3 800eb76: eef8 7a67 vcvt.f32.u32 s15, s15 800eb7a: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800eb7e: ee37 7a87 vadd.f32 s14, s15, s14 800eb82: edd7 6a07 vldr s13, [r7, #28] 800eb86: eec6 7a87 vdiv.f32 s15, s13, s14 800eb8a: eefc 7ae7 vcvt.u32.f32 s15, s15 800eb8e: ee17 2a90 vmov r2, s15 800eb92: 687b ldr r3, [r7, #4] 800eb94: 609a str r2, [r3, #8] { PLL2_Clocks->PLL2_P_Frequency = 0U; PLL2_Clocks->PLL2_Q_Frequency = 0U; PLL2_Clocks->PLL2_R_Frequency = 0U; } } 800eb96: e008 b.n 800ebaa PLL2_Clocks->PLL2_P_Frequency = 0U; 800eb98: 687b ldr r3, [r7, #4] 800eb9a: 2200 movs r2, #0 800eb9c: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = 0U; 800eb9e: 687b ldr r3, [r7, #4] 800eba0: 2200 movs r2, #0 800eba2: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = 0U; 800eba4: 687b ldr r3, [r7, #4] 800eba6: 2200 movs r2, #0 800eba8: 609a str r2, [r3, #8] } 800ebaa: bf00 nop 800ebac: 3724 adds r7, #36 @ 0x24 800ebae: 46bd mov sp, r7 800ebb0: f85d 7b04 ldr.w r7, [sp], #4 800ebb4: 4770 bx lr 800ebb6: bf00 nop 800ebb8: 58024400 .word 0x58024400 800ebbc: 03d09000 .word 0x03d09000 800ebc0: 46000000 .word 0x46000000 800ebc4: 4c742400 .word 0x4c742400 800ebc8: 4a742400 .word 0x4a742400 800ebcc: 4bbebc20 .word 0x4bbebc20 0800ebd0 : * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL3_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) { 800ebd0: b480 push {r7} 800ebd2: b089 sub sp, #36 @ 0x24 800ebd4: af00 add r7, sp, #0 800ebd6: 6078 str r0, [r7, #4] float_t fracn3, pll3vco; /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N PLL3xCLK = PLL3_VCO / PLLxR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800ebd8: 4ba1 ldr r3, [pc, #644] @ (800ee60 ) 800ebda: 6a9b ldr r3, [r3, #40] @ 0x28 800ebdc: f003 0303 and.w r3, r3, #3 800ebe0: 61bb str r3, [r7, #24] pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; 800ebe2: 4b9f ldr r3, [pc, #636] @ (800ee60 ) 800ebe4: 6a9b ldr r3, [r3, #40] @ 0x28 800ebe6: 0d1b lsrs r3, r3, #20 800ebe8: f003 033f and.w r3, r3, #63 @ 0x3f 800ebec: 617b str r3, [r7, #20] pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; 800ebee: 4b9c ldr r3, [pc, #624] @ (800ee60 ) 800ebf0: 6adb ldr r3, [r3, #44] @ 0x2c 800ebf2: 0a1b lsrs r3, r3, #8 800ebf4: f003 0301 and.w r3, r3, #1 800ebf8: 613b str r3, [r7, #16] fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); 800ebfa: 4b99 ldr r3, [pc, #612] @ (800ee60 ) 800ebfc: 6c5b ldr r3, [r3, #68] @ 0x44 800ebfe: 08db lsrs r3, r3, #3 800ec00: f3c3 030c ubfx r3, r3, #0, #13 800ec04: 693a ldr r2, [r7, #16] 800ec06: fb02 f303 mul.w r3, r2, r3 800ec0a: ee07 3a90 vmov s15, r3 800ec0e: eef8 7a67 vcvt.f32.u32 s15, s15 800ec12: edc7 7a03 vstr s15, [r7, #12] if (pll3m != 0U) 800ec16: 697b ldr r3, [r7, #20] 800ec18: 2b00 cmp r3, #0 800ec1a: f000 8111 beq.w 800ee40 { switch (pllsource) 800ec1e: 69bb ldr r3, [r7, #24] 800ec20: 2b02 cmp r3, #2 800ec22: f000 8083 beq.w 800ed2c 800ec26: 69bb ldr r3, [r7, #24] 800ec28: 2b02 cmp r3, #2 800ec2a: f200 80a1 bhi.w 800ed70 800ec2e: 69bb ldr r3, [r7, #24] 800ec30: 2b00 cmp r3, #0 800ec32: d003 beq.n 800ec3c 800ec34: 69bb ldr r3, [r7, #24] 800ec36: 2b01 cmp r3, #1 800ec38: d056 beq.n 800ece8 800ec3a: e099 b.n 800ed70 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800ec3c: 4b88 ldr r3, [pc, #544] @ (800ee60 ) 800ec3e: 681b ldr r3, [r3, #0] 800ec40: f003 0320 and.w r3, r3, #32 800ec44: 2b00 cmp r3, #0 800ec46: d02d beq.n 800eca4 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800ec48: 4b85 ldr r3, [pc, #532] @ (800ee60 ) 800ec4a: 681b ldr r3, [r3, #0] 800ec4c: 08db lsrs r3, r3, #3 800ec4e: f003 0303 and.w r3, r3, #3 800ec52: 4a84 ldr r2, [pc, #528] @ (800ee64 ) 800ec54: fa22 f303 lsr.w r3, r2, r3 800ec58: 60bb str r3, [r7, #8] pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ec5a: 68bb ldr r3, [r7, #8] 800ec5c: ee07 3a90 vmov s15, r3 800ec60: eef8 6a67 vcvt.f32.u32 s13, s15 800ec64: 697b ldr r3, [r7, #20] 800ec66: ee07 3a90 vmov s15, r3 800ec6a: eef8 7a67 vcvt.f32.u32 s15, s15 800ec6e: ee86 7aa7 vdiv.f32 s14, s13, s15 800ec72: 4b7b ldr r3, [pc, #492] @ (800ee60 ) 800ec74: 6c1b ldr r3, [r3, #64] @ 0x40 800ec76: f3c3 0308 ubfx r3, r3, #0, #9 800ec7a: ee07 3a90 vmov s15, r3 800ec7e: eef8 6a67 vcvt.f32.u32 s13, s15 800ec82: ed97 6a03 vldr s12, [r7, #12] 800ec86: eddf 5a78 vldr s11, [pc, #480] @ 800ee68 800ec8a: eec6 7a25 vdiv.f32 s15, s12, s11 800ec8e: ee76 7aa7 vadd.f32 s15, s13, s15 800ec92: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ec96: ee77 7aa6 vadd.f32 s15, s15, s13 800ec9a: ee67 7a27 vmul.f32 s15, s14, s15 800ec9e: edc7 7a07 vstr s15, [r7, #28] } else { pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); } break; 800eca2: e087 b.n 800edb4 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800eca4: 697b ldr r3, [r7, #20] 800eca6: ee07 3a90 vmov s15, r3 800ecaa: eef8 7a67 vcvt.f32.u32 s15, s15 800ecae: eddf 6a6f vldr s13, [pc, #444] @ 800ee6c 800ecb2: ee86 7aa7 vdiv.f32 s14, s13, s15 800ecb6: 4b6a ldr r3, [pc, #424] @ (800ee60 ) 800ecb8: 6c1b ldr r3, [r3, #64] @ 0x40 800ecba: f3c3 0308 ubfx r3, r3, #0, #9 800ecbe: ee07 3a90 vmov s15, r3 800ecc2: eef8 6a67 vcvt.f32.u32 s13, s15 800ecc6: ed97 6a03 vldr s12, [r7, #12] 800ecca: eddf 5a67 vldr s11, [pc, #412] @ 800ee68 800ecce: eec6 7a25 vdiv.f32 s15, s12, s11 800ecd2: ee76 7aa7 vadd.f32 s15, s13, s15 800ecd6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ecda: ee77 7aa6 vadd.f32 s15, s15, s13 800ecde: ee67 7a27 vmul.f32 s15, s14, s15 800ece2: edc7 7a07 vstr s15, [r7, #28] break; 800ece6: e065 b.n 800edb4 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ece8: 697b ldr r3, [r7, #20] 800ecea: ee07 3a90 vmov s15, r3 800ecee: eef8 7a67 vcvt.f32.u32 s15, s15 800ecf2: eddf 6a5f vldr s13, [pc, #380] @ 800ee70 800ecf6: ee86 7aa7 vdiv.f32 s14, s13, s15 800ecfa: 4b59 ldr r3, [pc, #356] @ (800ee60 ) 800ecfc: 6c1b ldr r3, [r3, #64] @ 0x40 800ecfe: f3c3 0308 ubfx r3, r3, #0, #9 800ed02: ee07 3a90 vmov s15, r3 800ed06: eef8 6a67 vcvt.f32.u32 s13, s15 800ed0a: ed97 6a03 vldr s12, [r7, #12] 800ed0e: eddf 5a56 vldr s11, [pc, #344] @ 800ee68 800ed12: eec6 7a25 vdiv.f32 s15, s12, s11 800ed16: ee76 7aa7 vadd.f32 s15, s13, s15 800ed1a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ed1e: ee77 7aa6 vadd.f32 s15, s15, s13 800ed22: ee67 7a27 vmul.f32 s15, s14, s15 800ed26: edc7 7a07 vstr s15, [r7, #28] break; 800ed2a: e043 b.n 800edb4 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ed2c: 697b ldr r3, [r7, #20] 800ed2e: ee07 3a90 vmov s15, r3 800ed32: eef8 7a67 vcvt.f32.u32 s15, s15 800ed36: eddf 6a4f vldr s13, [pc, #316] @ 800ee74 800ed3a: ee86 7aa7 vdiv.f32 s14, s13, s15 800ed3e: 4b48 ldr r3, [pc, #288] @ (800ee60 ) 800ed40: 6c1b ldr r3, [r3, #64] @ 0x40 800ed42: f3c3 0308 ubfx r3, r3, #0, #9 800ed46: ee07 3a90 vmov s15, r3 800ed4a: eef8 6a67 vcvt.f32.u32 s13, s15 800ed4e: ed97 6a03 vldr s12, [r7, #12] 800ed52: eddf 5a45 vldr s11, [pc, #276] @ 800ee68 800ed56: eec6 7a25 vdiv.f32 s15, s12, s11 800ed5a: ee76 7aa7 vadd.f32 s15, s13, s15 800ed5e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ed62: ee77 7aa6 vadd.f32 s15, s15, s13 800ed66: ee67 7a27 vmul.f32 s15, s14, s15 800ed6a: edc7 7a07 vstr s15, [r7, #28] break; 800ed6e: e021 b.n 800edb4 default: pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ed70: 697b ldr r3, [r7, #20] 800ed72: ee07 3a90 vmov s15, r3 800ed76: eef8 7a67 vcvt.f32.u32 s15, s15 800ed7a: eddf 6a3d vldr s13, [pc, #244] @ 800ee70 800ed7e: ee86 7aa7 vdiv.f32 s14, s13, s15 800ed82: 4b37 ldr r3, [pc, #220] @ (800ee60 ) 800ed84: 6c1b ldr r3, [r3, #64] @ 0x40 800ed86: f3c3 0308 ubfx r3, r3, #0, #9 800ed8a: ee07 3a90 vmov s15, r3 800ed8e: eef8 6a67 vcvt.f32.u32 s13, s15 800ed92: ed97 6a03 vldr s12, [r7, #12] 800ed96: eddf 5a34 vldr s11, [pc, #208] @ 800ee68 800ed9a: eec6 7a25 vdiv.f32 s15, s12, s11 800ed9e: ee76 7aa7 vadd.f32 s15, s13, s15 800eda2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800eda6: ee77 7aa6 vadd.f32 s15, s15, s13 800edaa: ee67 7a27 vmul.f32 s15, s14, s15 800edae: edc7 7a07 vstr s15, [r7, #28] break; 800edb2: bf00 nop } PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; 800edb4: 4b2a ldr r3, [pc, #168] @ (800ee60 ) 800edb6: 6c1b ldr r3, [r3, #64] @ 0x40 800edb8: 0a5b lsrs r3, r3, #9 800edba: f003 037f and.w r3, r3, #127 @ 0x7f 800edbe: ee07 3a90 vmov s15, r3 800edc2: eef8 7a67 vcvt.f32.u32 s15, s15 800edc6: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800edca: ee37 7a87 vadd.f32 s14, s15, s14 800edce: edd7 6a07 vldr s13, [r7, #28] 800edd2: eec6 7a87 vdiv.f32 s15, s13, s14 800edd6: eefc 7ae7 vcvt.u32.f32 s15, s15 800edda: ee17 2a90 vmov r2, s15 800edde: 687b ldr r3, [r7, #4] 800ede0: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; 800ede2: 4b1f ldr r3, [pc, #124] @ (800ee60 ) 800ede4: 6c1b ldr r3, [r3, #64] @ 0x40 800ede6: 0c1b lsrs r3, r3, #16 800ede8: f003 037f and.w r3, r3, #127 @ 0x7f 800edec: ee07 3a90 vmov s15, r3 800edf0: eef8 7a67 vcvt.f32.u32 s15, s15 800edf4: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800edf8: ee37 7a87 vadd.f32 s14, s15, s14 800edfc: edd7 6a07 vldr s13, [r7, #28] 800ee00: eec6 7a87 vdiv.f32 s15, s13, s14 800ee04: eefc 7ae7 vcvt.u32.f32 s15, s15 800ee08: ee17 2a90 vmov r2, s15 800ee0c: 687b ldr r3, [r7, #4] 800ee0e: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; 800ee10: 4b13 ldr r3, [pc, #76] @ (800ee60 ) 800ee12: 6c1b ldr r3, [r3, #64] @ 0x40 800ee14: 0e1b lsrs r3, r3, #24 800ee16: f003 037f and.w r3, r3, #127 @ 0x7f 800ee1a: ee07 3a90 vmov s15, r3 800ee1e: eef8 7a67 vcvt.f32.u32 s15, s15 800ee22: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ee26: ee37 7a87 vadd.f32 s14, s15, s14 800ee2a: edd7 6a07 vldr s13, [r7, #28] 800ee2e: eec6 7a87 vdiv.f32 s15, s13, s14 800ee32: eefc 7ae7 vcvt.u32.f32 s15, s15 800ee36: ee17 2a90 vmov r2, s15 800ee3a: 687b ldr r3, [r7, #4] 800ee3c: 609a str r2, [r3, #8] PLL3_Clocks->PLL3_P_Frequency = 0U; PLL3_Clocks->PLL3_Q_Frequency = 0U; PLL3_Clocks->PLL3_R_Frequency = 0U; } } 800ee3e: e008 b.n 800ee52 PLL3_Clocks->PLL3_P_Frequency = 0U; 800ee40: 687b ldr r3, [r7, #4] 800ee42: 2200 movs r2, #0 800ee44: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = 0U; 800ee46: 687b ldr r3, [r7, #4] 800ee48: 2200 movs r2, #0 800ee4a: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = 0U; 800ee4c: 687b ldr r3, [r7, #4] 800ee4e: 2200 movs r2, #0 800ee50: 609a str r2, [r3, #8] } 800ee52: bf00 nop 800ee54: 3724 adds r7, #36 @ 0x24 800ee56: 46bd mov sp, r7 800ee58: f85d 7b04 ldr.w r7, [sp], #4 800ee5c: 4770 bx lr 800ee5e: bf00 nop 800ee60: 58024400 .word 0x58024400 800ee64: 03d09000 .word 0x03d09000 800ee68: 46000000 .word 0x46000000 800ee6c: 4c742400 .word 0x4c742400 800ee70: 4a742400 .word 0x4a742400 800ee74: 4bbebc20 .word 0x4bbebc20 0800ee78 : * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL1_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) { 800ee78: b480 push {r7} 800ee7a: b089 sub sp, #36 @ 0x24 800ee7c: af00 add r7, sp, #0 800ee7e: 6078 str r0, [r7, #4] uint32_t pllsource, pll1m, pll1fracen, hsivalue; float_t fracn1, pll1vco; pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800ee80: 4ba0 ldr r3, [pc, #640] @ (800f104 ) 800ee82: 6a9b ldr r3, [r3, #40] @ 0x28 800ee84: f003 0303 and.w r3, r3, #3 800ee88: 61bb str r3, [r7, #24] pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); 800ee8a: 4b9e ldr r3, [pc, #632] @ (800f104 ) 800ee8c: 6a9b ldr r3, [r3, #40] @ 0x28 800ee8e: 091b lsrs r3, r3, #4 800ee90: f003 033f and.w r3, r3, #63 @ 0x3f 800ee94: 617b str r3, [r7, #20] pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; 800ee96: 4b9b ldr r3, [pc, #620] @ (800f104 ) 800ee98: 6adb ldr r3, [r3, #44] @ 0x2c 800ee9a: f003 0301 and.w r3, r3, #1 800ee9e: 613b str r3, [r7, #16] fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800eea0: 4b98 ldr r3, [pc, #608] @ (800f104 ) 800eea2: 6b5b ldr r3, [r3, #52] @ 0x34 800eea4: 08db lsrs r3, r3, #3 800eea6: f3c3 030c ubfx r3, r3, #0, #13 800eeaa: 693a ldr r2, [r7, #16] 800eeac: fb02 f303 mul.w r3, r2, r3 800eeb0: ee07 3a90 vmov s15, r3 800eeb4: eef8 7a67 vcvt.f32.u32 s15, s15 800eeb8: edc7 7a03 vstr s15, [r7, #12] if (pll1m != 0U) 800eebc: 697b ldr r3, [r7, #20] 800eebe: 2b00 cmp r3, #0 800eec0: f000 8111 beq.w 800f0e6 { switch (pllsource) 800eec4: 69bb ldr r3, [r7, #24] 800eec6: 2b02 cmp r3, #2 800eec8: f000 8083 beq.w 800efd2 800eecc: 69bb ldr r3, [r7, #24] 800eece: 2b02 cmp r3, #2 800eed0: f200 80a1 bhi.w 800f016 800eed4: 69bb ldr r3, [r7, #24] 800eed6: 2b00 cmp r3, #0 800eed8: d003 beq.n 800eee2 800eeda: 69bb ldr r3, [r7, #24] 800eedc: 2b01 cmp r3, #1 800eede: d056 beq.n 800ef8e 800eee0: e099 b.n 800f016 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800eee2: 4b88 ldr r3, [pc, #544] @ (800f104 ) 800eee4: 681b ldr r3, [r3, #0] 800eee6: f003 0320 and.w r3, r3, #32 800eeea: 2b00 cmp r3, #0 800eeec: d02d beq.n 800ef4a { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800eeee: 4b85 ldr r3, [pc, #532] @ (800f104 ) 800eef0: 681b ldr r3, [r3, #0] 800eef2: 08db lsrs r3, r3, #3 800eef4: f003 0303 and.w r3, r3, #3 800eef8: 4a83 ldr r2, [pc, #524] @ (800f108 ) 800eefa: fa22 f303 lsr.w r3, r2, r3 800eefe: 60bb str r3, [r7, #8] pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ef00: 68bb ldr r3, [r7, #8] 800ef02: ee07 3a90 vmov s15, r3 800ef06: eef8 6a67 vcvt.f32.u32 s13, s15 800ef0a: 697b ldr r3, [r7, #20] 800ef0c: ee07 3a90 vmov s15, r3 800ef10: eef8 7a67 vcvt.f32.u32 s15, s15 800ef14: ee86 7aa7 vdiv.f32 s14, s13, s15 800ef18: 4b7a ldr r3, [pc, #488] @ (800f104 ) 800ef1a: 6b1b ldr r3, [r3, #48] @ 0x30 800ef1c: f3c3 0308 ubfx r3, r3, #0, #9 800ef20: ee07 3a90 vmov s15, r3 800ef24: eef8 6a67 vcvt.f32.u32 s13, s15 800ef28: ed97 6a03 vldr s12, [r7, #12] 800ef2c: eddf 5a77 vldr s11, [pc, #476] @ 800f10c 800ef30: eec6 7a25 vdiv.f32 s15, s12, s11 800ef34: ee76 7aa7 vadd.f32 s15, s13, s15 800ef38: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ef3c: ee77 7aa6 vadd.f32 s15, s15, s13 800ef40: ee67 7a27 vmul.f32 s15, s14, s15 800ef44: edc7 7a07 vstr s15, [r7, #28] } else { pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 800ef48: e087 b.n 800f05a pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ef4a: 697b ldr r3, [r7, #20] 800ef4c: ee07 3a90 vmov s15, r3 800ef50: eef8 7a67 vcvt.f32.u32 s15, s15 800ef54: eddf 6a6e vldr s13, [pc, #440] @ 800f110 800ef58: ee86 7aa7 vdiv.f32 s14, s13, s15 800ef5c: 4b69 ldr r3, [pc, #420] @ (800f104 ) 800ef5e: 6b1b ldr r3, [r3, #48] @ 0x30 800ef60: f3c3 0308 ubfx r3, r3, #0, #9 800ef64: ee07 3a90 vmov s15, r3 800ef68: eef8 6a67 vcvt.f32.u32 s13, s15 800ef6c: ed97 6a03 vldr s12, [r7, #12] 800ef70: eddf 5a66 vldr s11, [pc, #408] @ 800f10c 800ef74: eec6 7a25 vdiv.f32 s15, s12, s11 800ef78: ee76 7aa7 vadd.f32 s15, s13, s15 800ef7c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ef80: ee77 7aa6 vadd.f32 s15, s15, s13 800ef84: ee67 7a27 vmul.f32 s15, s14, s15 800ef88: edc7 7a07 vstr s15, [r7, #28] break; 800ef8c: e065 b.n 800f05a case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ef8e: 697b ldr r3, [r7, #20] 800ef90: ee07 3a90 vmov s15, r3 800ef94: eef8 7a67 vcvt.f32.u32 s15, s15 800ef98: eddf 6a5e vldr s13, [pc, #376] @ 800f114 800ef9c: ee86 7aa7 vdiv.f32 s14, s13, s15 800efa0: 4b58 ldr r3, [pc, #352] @ (800f104 ) 800efa2: 6b1b ldr r3, [r3, #48] @ 0x30 800efa4: f3c3 0308 ubfx r3, r3, #0, #9 800efa8: ee07 3a90 vmov s15, r3 800efac: eef8 6a67 vcvt.f32.u32 s13, s15 800efb0: ed97 6a03 vldr s12, [r7, #12] 800efb4: eddf 5a55 vldr s11, [pc, #340] @ 800f10c 800efb8: eec6 7a25 vdiv.f32 s15, s12, s11 800efbc: ee76 7aa7 vadd.f32 s15, s13, s15 800efc0: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800efc4: ee77 7aa6 vadd.f32 s15, s15, s13 800efc8: ee67 7a27 vmul.f32 s15, s14, s15 800efcc: edc7 7a07 vstr s15, [r7, #28] break; 800efd0: e043 b.n 800f05a case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800efd2: 697b ldr r3, [r7, #20] 800efd4: ee07 3a90 vmov s15, r3 800efd8: eef8 7a67 vcvt.f32.u32 s15, s15 800efdc: eddf 6a4e vldr s13, [pc, #312] @ 800f118 800efe0: ee86 7aa7 vdiv.f32 s14, s13, s15 800efe4: 4b47 ldr r3, [pc, #284] @ (800f104 ) 800efe6: 6b1b ldr r3, [r3, #48] @ 0x30 800efe8: f3c3 0308 ubfx r3, r3, #0, #9 800efec: ee07 3a90 vmov s15, r3 800eff0: eef8 6a67 vcvt.f32.u32 s13, s15 800eff4: ed97 6a03 vldr s12, [r7, #12] 800eff8: eddf 5a44 vldr s11, [pc, #272] @ 800f10c 800effc: eec6 7a25 vdiv.f32 s15, s12, s11 800f000: ee76 7aa7 vadd.f32 s15, s13, s15 800f004: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800f008: ee77 7aa6 vadd.f32 s15, s15, s13 800f00c: ee67 7a27 vmul.f32 s15, s14, s15 800f010: edc7 7a07 vstr s15, [r7, #28] break; 800f014: e021 b.n 800f05a default: pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800f016: 697b ldr r3, [r7, #20] 800f018: ee07 3a90 vmov s15, r3 800f01c: eef8 7a67 vcvt.f32.u32 s15, s15 800f020: eddf 6a3b vldr s13, [pc, #236] @ 800f110 800f024: ee86 7aa7 vdiv.f32 s14, s13, s15 800f028: 4b36 ldr r3, [pc, #216] @ (800f104 ) 800f02a: 6b1b ldr r3, [r3, #48] @ 0x30 800f02c: f3c3 0308 ubfx r3, r3, #0, #9 800f030: ee07 3a90 vmov s15, r3 800f034: eef8 6a67 vcvt.f32.u32 s13, s15 800f038: ed97 6a03 vldr s12, [r7, #12] 800f03c: eddf 5a33 vldr s11, [pc, #204] @ 800f10c 800f040: eec6 7a25 vdiv.f32 s15, s12, s11 800f044: ee76 7aa7 vadd.f32 s15, s13, s15 800f048: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800f04c: ee77 7aa6 vadd.f32 s15, s15, s13 800f050: ee67 7a27 vmul.f32 s15, s14, s15 800f054: edc7 7a07 vstr s15, [r7, #28] break; 800f058: bf00 nop } PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; 800f05a: 4b2a ldr r3, [pc, #168] @ (800f104 ) 800f05c: 6b1b ldr r3, [r3, #48] @ 0x30 800f05e: 0a5b lsrs r3, r3, #9 800f060: f003 037f and.w r3, r3, #127 @ 0x7f 800f064: ee07 3a90 vmov s15, r3 800f068: eef8 7a67 vcvt.f32.u32 s15, s15 800f06c: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800f070: ee37 7a87 vadd.f32 s14, s15, s14 800f074: edd7 6a07 vldr s13, [r7, #28] 800f078: eec6 7a87 vdiv.f32 s15, s13, s14 800f07c: eefc 7ae7 vcvt.u32.f32 s15, s15 800f080: ee17 2a90 vmov r2, s15 800f084: 687b ldr r3, [r7, #4] 800f086: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ; 800f088: 4b1e ldr r3, [pc, #120] @ (800f104 ) 800f08a: 6b1b ldr r3, [r3, #48] @ 0x30 800f08c: 0c1b lsrs r3, r3, #16 800f08e: f003 037f and.w r3, r3, #127 @ 0x7f 800f092: ee07 3a90 vmov s15, r3 800f096: eef8 7a67 vcvt.f32.u32 s15, s15 800f09a: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800f09e: ee37 7a87 vadd.f32 s14, s15, s14 800f0a2: edd7 6a07 vldr s13, [r7, #28] 800f0a6: eec6 7a87 vdiv.f32 s15, s13, s14 800f0aa: eefc 7ae7 vcvt.u32.f32 s15, s15 800f0ae: ee17 2a90 vmov r2, s15 800f0b2: 687b ldr r3, [r7, #4] 800f0b4: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; 800f0b6: 4b13 ldr r3, [pc, #76] @ (800f104 ) 800f0b8: 6b1b ldr r3, [r3, #48] @ 0x30 800f0ba: 0e1b lsrs r3, r3, #24 800f0bc: f003 037f and.w r3, r3, #127 @ 0x7f 800f0c0: ee07 3a90 vmov s15, r3 800f0c4: eef8 7a67 vcvt.f32.u32 s15, s15 800f0c8: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800f0cc: ee37 7a87 vadd.f32 s14, s15, s14 800f0d0: edd7 6a07 vldr s13, [r7, #28] 800f0d4: eec6 7a87 vdiv.f32 s15, s13, s14 800f0d8: eefc 7ae7 vcvt.u32.f32 s15, s15 800f0dc: ee17 2a90 vmov r2, s15 800f0e0: 687b ldr r3, [r7, #4] 800f0e2: 609a str r2, [r3, #8] PLL1_Clocks->PLL1_P_Frequency = 0U; PLL1_Clocks->PLL1_Q_Frequency = 0U; PLL1_Clocks->PLL1_R_Frequency = 0U; } } 800f0e4: e008 b.n 800f0f8 PLL1_Clocks->PLL1_P_Frequency = 0U; 800f0e6: 687b ldr r3, [r7, #4] 800f0e8: 2200 movs r2, #0 800f0ea: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = 0U; 800f0ec: 687b ldr r3, [r7, #4] 800f0ee: 2200 movs r2, #0 800f0f0: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = 0U; 800f0f2: 687b ldr r3, [r7, #4] 800f0f4: 2200 movs r2, #0 800f0f6: 609a str r2, [r3, #8] } 800f0f8: bf00 nop 800f0fa: 3724 adds r7, #36 @ 0x24 800f0fc: 46bd mov sp, r7 800f0fe: f85d 7b04 ldr.w r7, [sp], #4 800f102: 4770 bx lr 800f104: 58024400 .word 0x58024400 800f108: 03d09000 .word 0x03d09000 800f10c: 46000000 .word 0x46000000 800f110: 4c742400 .word 0x4c742400 800f114: 4a742400 .word 0x4a742400 800f118: 4bbebc20 .word 0x4bbebc20 0800f11c : * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { 800f11c: b580 push {r7, lr} 800f11e: b084 sub sp, #16 800f120: af00 add r7, sp, #0 800f122: 6078 str r0, [r7, #4] 800f124: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800f126: 2300 movs r3, #0 800f128: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800f12a: 4b53 ldr r3, [pc, #332] @ (800f278 ) 800f12c: 6a9b ldr r3, [r3, #40] @ 0x28 800f12e: f003 0303 and.w r3, r3, #3 800f132: 2b03 cmp r3, #3 800f134: d101 bne.n 800f13a { return HAL_ERROR; 800f136: 2301 movs r3, #1 800f138: e099 b.n 800f26e else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 800f13a: 4b4f ldr r3, [pc, #316] @ (800f278 ) 800f13c: 681b ldr r3, [r3, #0] 800f13e: 4a4e ldr r2, [pc, #312] @ (800f278 ) 800f140: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800f144: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800f146: f7f6 fead bl 8005ea4 800f14a: 60b8 str r0, [r7, #8] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800f14c: e008 b.n 800f160 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800f14e: f7f6 fea9 bl 8005ea4 800f152: 4602 mov r2, r0 800f154: 68bb ldr r3, [r7, #8] 800f156: 1ad3 subs r3, r2, r3 800f158: 2b02 cmp r3, #2 800f15a: d901 bls.n 800f160 { return HAL_TIMEOUT; 800f15c: 2303 movs r3, #3 800f15e: e086 b.n 800f26e while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800f160: 4b45 ldr r3, [pc, #276] @ (800f278 ) 800f162: 681b ldr r3, [r3, #0] 800f164: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800f168: 2b00 cmp r3, #0 800f16a: d1f0 bne.n 800f14e } } /* Configure PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 800f16c: 4b42 ldr r3, [pc, #264] @ (800f278 ) 800f16e: 6a9b ldr r3, [r3, #40] @ 0x28 800f170: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800f174: 687b ldr r3, [r7, #4] 800f176: 681b ldr r3, [r3, #0] 800f178: 031b lsls r3, r3, #12 800f17a: 493f ldr r1, [pc, #252] @ (800f278 ) 800f17c: 4313 orrs r3, r2 800f17e: 628b str r3, [r1, #40] @ 0x28 800f180: 687b ldr r3, [r7, #4] 800f182: 685b ldr r3, [r3, #4] 800f184: 3b01 subs r3, #1 800f186: f3c3 0208 ubfx r2, r3, #0, #9 800f18a: 687b ldr r3, [r7, #4] 800f18c: 689b ldr r3, [r3, #8] 800f18e: 3b01 subs r3, #1 800f190: 025b lsls r3, r3, #9 800f192: b29b uxth r3, r3 800f194: 431a orrs r2, r3 800f196: 687b ldr r3, [r7, #4] 800f198: 68db ldr r3, [r3, #12] 800f19a: 3b01 subs r3, #1 800f19c: 041b lsls r3, r3, #16 800f19e: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800f1a2: 431a orrs r2, r3 800f1a4: 687b ldr r3, [r7, #4] 800f1a6: 691b ldr r3, [r3, #16] 800f1a8: 3b01 subs r3, #1 800f1aa: 061b lsls r3, r3, #24 800f1ac: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800f1b0: 4931 ldr r1, [pc, #196] @ (800f278 ) 800f1b2: 4313 orrs r3, r2 800f1b4: 638b str r3, [r1, #56] @ 0x38 pll2->PLL2P, pll2->PLL2Q, pll2->PLL2R); /* Select PLL2 input reference frequency range: VCI */ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 800f1b6: 4b30 ldr r3, [pc, #192] @ (800f278 ) 800f1b8: 6adb ldr r3, [r3, #44] @ 0x2c 800f1ba: f023 02c0 bic.w r2, r3, #192 @ 0xc0 800f1be: 687b ldr r3, [r7, #4] 800f1c0: 695b ldr r3, [r3, #20] 800f1c2: 492d ldr r1, [pc, #180] @ (800f278 ) 800f1c4: 4313 orrs r3, r2 800f1c6: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL2 output frequency range : VCO */ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 800f1c8: 4b2b ldr r3, [pc, #172] @ (800f278 ) 800f1ca: 6adb ldr r3, [r3, #44] @ 0x2c 800f1cc: f023 0220 bic.w r2, r3, #32 800f1d0: 687b ldr r3, [r7, #4] 800f1d2: 699b ldr r3, [r3, #24] 800f1d4: 4928 ldr r1, [pc, #160] @ (800f278 ) 800f1d6: 4313 orrs r3, r2 800f1d8: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_DISABLE(); 800f1da: 4b27 ldr r3, [pc, #156] @ (800f278 ) 800f1dc: 6adb ldr r3, [r3, #44] @ 0x2c 800f1de: 4a26 ldr r2, [pc, #152] @ (800f278 ) 800f1e0: f023 0310 bic.w r3, r3, #16 800f1e4: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 800f1e6: 4b24 ldr r3, [pc, #144] @ (800f278 ) 800f1e8: 6bda ldr r2, [r3, #60] @ 0x3c 800f1ea: 4b24 ldr r3, [pc, #144] @ (800f27c ) 800f1ec: 4013 ands r3, r2 800f1ee: 687a ldr r2, [r7, #4] 800f1f0: 69d2 ldr r2, [r2, #28] 800f1f2: 00d2 lsls r2, r2, #3 800f1f4: 4920 ldr r1, [pc, #128] @ (800f278 ) 800f1f6: 4313 orrs r3, r2 800f1f8: 63cb str r3, [r1, #60] @ 0x3c /* Enable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_ENABLE(); 800f1fa: 4b1f ldr r3, [pc, #124] @ (800f278 ) 800f1fc: 6adb ldr r3, [r3, #44] @ 0x2c 800f1fe: 4a1e ldr r2, [pc, #120] @ (800f278 ) 800f200: f043 0310 orr.w r3, r3, #16 800f204: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL2 clock output */ if (Divider == DIVIDER_P_UPDATE) 800f206: 683b ldr r3, [r7, #0] 800f208: 2b00 cmp r3, #0 800f20a: d106 bne.n 800f21a { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 800f20c: 4b1a ldr r3, [pc, #104] @ (800f278 ) 800f20e: 6adb ldr r3, [r3, #44] @ 0x2c 800f210: 4a19 ldr r2, [pc, #100] @ (800f278 ) 800f212: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800f216: 62d3 str r3, [r2, #44] @ 0x2c 800f218: e00f b.n 800f23a } else if (Divider == DIVIDER_Q_UPDATE) 800f21a: 683b ldr r3, [r7, #0] 800f21c: 2b01 cmp r3, #1 800f21e: d106 bne.n 800f22e { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 800f220: 4b15 ldr r3, [pc, #84] @ (800f278 ) 800f222: 6adb ldr r3, [r3, #44] @ 0x2c 800f224: 4a14 ldr r2, [pc, #80] @ (800f278 ) 800f226: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800f22a: 62d3 str r3, [r2, #44] @ 0x2c 800f22c: e005 b.n 800f23a } else { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 800f22e: 4b12 ldr r3, [pc, #72] @ (800f278 ) 800f230: 6adb ldr r3, [r3, #44] @ 0x2c 800f232: 4a11 ldr r2, [pc, #68] @ (800f278 ) 800f234: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 800f238: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL2. */ __HAL_RCC_PLL2_ENABLE(); 800f23a: 4b0f ldr r3, [pc, #60] @ (800f278 ) 800f23c: 681b ldr r3, [r3, #0] 800f23e: 4a0e ldr r2, [pc, #56] @ (800f278 ) 800f240: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 800f244: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800f246: f7f6 fe2d bl 8005ea4 800f24a: 60b8 str r0, [r7, #8] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800f24c: e008 b.n 800f260 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800f24e: f7f6 fe29 bl 8005ea4 800f252: 4602 mov r2, r0 800f254: 68bb ldr r3, [r7, #8] 800f256: 1ad3 subs r3, r2, r3 800f258: 2b02 cmp r3, #2 800f25a: d901 bls.n 800f260 { return HAL_TIMEOUT; 800f25c: 2303 movs r3, #3 800f25e: e006 b.n 800f26e while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800f260: 4b05 ldr r3, [pc, #20] @ (800f278 ) 800f262: 681b ldr r3, [r3, #0] 800f264: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800f268: 2b00 cmp r3, #0 800f26a: d0f0 beq.n 800f24e } } return status; 800f26c: 7bfb ldrb r3, [r7, #15] } 800f26e: 4618 mov r0, r3 800f270: 3710 adds r7, #16 800f272: 46bd mov sp, r7 800f274: bd80 pop {r7, pc} 800f276: bf00 nop 800f278: 58024400 .word 0x58024400 800f27c: ffff0007 .word 0xffff0007 0800f280 : * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { 800f280: b580 push {r7, lr} 800f282: b084 sub sp, #16 800f284: af00 add r7, sp, #0 800f286: 6078 str r0, [r7, #4] 800f288: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800f28a: 2300 movs r3, #0 800f28c: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800f28e: 4b53 ldr r3, [pc, #332] @ (800f3dc ) 800f290: 6a9b ldr r3, [r3, #40] @ 0x28 800f292: f003 0303 and.w r3, r3, #3 800f296: 2b03 cmp r3, #3 800f298: d101 bne.n 800f29e { return HAL_ERROR; 800f29a: 2301 movs r3, #1 800f29c: e099 b.n 800f3d2 else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 800f29e: 4b4f ldr r3, [pc, #316] @ (800f3dc ) 800f2a0: 681b ldr r3, [r3, #0] 800f2a2: 4a4e ldr r2, [pc, #312] @ (800f3dc ) 800f2a4: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800f2a8: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800f2aa: f7f6 fdfb bl 8005ea4 800f2ae: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800f2b0: e008 b.n 800f2c4 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800f2b2: f7f6 fdf7 bl 8005ea4 800f2b6: 4602 mov r2, r0 800f2b8: 68bb ldr r3, [r7, #8] 800f2ba: 1ad3 subs r3, r2, r3 800f2bc: 2b02 cmp r3, #2 800f2be: d901 bls.n 800f2c4 { return HAL_TIMEOUT; 800f2c0: 2303 movs r3, #3 800f2c2: e086 b.n 800f3d2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800f2c4: 4b45 ldr r3, [pc, #276] @ (800f3dc ) 800f2c6: 681b ldr r3, [r3, #0] 800f2c8: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800f2cc: 2b00 cmp r3, #0 800f2ce: d1f0 bne.n 800f2b2 } } /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 800f2d0: 4b42 ldr r3, [pc, #264] @ (800f3dc ) 800f2d2: 6a9b ldr r3, [r3, #40] @ 0x28 800f2d4: f023 727c bic.w r2, r3, #66060288 @ 0x3f00000 800f2d8: 687b ldr r3, [r7, #4] 800f2da: 681b ldr r3, [r3, #0] 800f2dc: 051b lsls r3, r3, #20 800f2de: 493f ldr r1, [pc, #252] @ (800f3dc ) 800f2e0: 4313 orrs r3, r2 800f2e2: 628b str r3, [r1, #40] @ 0x28 800f2e4: 687b ldr r3, [r7, #4] 800f2e6: 685b ldr r3, [r3, #4] 800f2e8: 3b01 subs r3, #1 800f2ea: f3c3 0208 ubfx r2, r3, #0, #9 800f2ee: 687b ldr r3, [r7, #4] 800f2f0: 689b ldr r3, [r3, #8] 800f2f2: 3b01 subs r3, #1 800f2f4: 025b lsls r3, r3, #9 800f2f6: b29b uxth r3, r3 800f2f8: 431a orrs r2, r3 800f2fa: 687b ldr r3, [r7, #4] 800f2fc: 68db ldr r3, [r3, #12] 800f2fe: 3b01 subs r3, #1 800f300: 041b lsls r3, r3, #16 800f302: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800f306: 431a orrs r2, r3 800f308: 687b ldr r3, [r7, #4] 800f30a: 691b ldr r3, [r3, #16] 800f30c: 3b01 subs r3, #1 800f30e: 061b lsls r3, r3, #24 800f310: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800f314: 4931 ldr r1, [pc, #196] @ (800f3dc ) 800f316: 4313 orrs r3, r2 800f318: 640b str r3, [r1, #64] @ 0x40 pll3->PLL3P, pll3->PLL3Q, pll3->PLL3R); /* Select PLL3 input reference frequency range: VCI */ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 800f31a: 4b30 ldr r3, [pc, #192] @ (800f3dc ) 800f31c: 6adb ldr r3, [r3, #44] @ 0x2c 800f31e: f423 6240 bic.w r2, r3, #3072 @ 0xc00 800f322: 687b ldr r3, [r7, #4] 800f324: 695b ldr r3, [r3, #20] 800f326: 492d ldr r1, [pc, #180] @ (800f3dc ) 800f328: 4313 orrs r3, r2 800f32a: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL3 output frequency range : VCO */ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 800f32c: 4b2b ldr r3, [pc, #172] @ (800f3dc ) 800f32e: 6adb ldr r3, [r3, #44] @ 0x2c 800f330: f423 7200 bic.w r2, r3, #512 @ 0x200 800f334: 687b ldr r3, [r7, #4] 800f336: 699b ldr r3, [r3, #24] 800f338: 4928 ldr r1, [pc, #160] @ (800f3dc ) 800f33a: 4313 orrs r3, r2 800f33c: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_DISABLE(); 800f33e: 4b27 ldr r3, [pc, #156] @ (800f3dc ) 800f340: 6adb ldr r3, [r3, #44] @ 0x2c 800f342: 4a26 ldr r2, [pc, #152] @ (800f3dc ) 800f344: f423 7380 bic.w r3, r3, #256 @ 0x100 800f348: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 800f34a: 4b24 ldr r3, [pc, #144] @ (800f3dc ) 800f34c: 6c5a ldr r2, [r3, #68] @ 0x44 800f34e: 4b24 ldr r3, [pc, #144] @ (800f3e0 ) 800f350: 4013 ands r3, r2 800f352: 687a ldr r2, [r7, #4] 800f354: 69d2 ldr r2, [r2, #28] 800f356: 00d2 lsls r2, r2, #3 800f358: 4920 ldr r1, [pc, #128] @ (800f3dc ) 800f35a: 4313 orrs r3, r2 800f35c: 644b str r3, [r1, #68] @ 0x44 /* Enable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_ENABLE(); 800f35e: 4b1f ldr r3, [pc, #124] @ (800f3dc ) 800f360: 6adb ldr r3, [r3, #44] @ 0x2c 800f362: 4a1e ldr r2, [pc, #120] @ (800f3dc ) 800f364: f443 7380 orr.w r3, r3, #256 @ 0x100 800f368: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL3 clock output */ if (Divider == DIVIDER_P_UPDATE) 800f36a: 683b ldr r3, [r7, #0] 800f36c: 2b00 cmp r3, #0 800f36e: d106 bne.n 800f37e { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 800f370: 4b1a ldr r3, [pc, #104] @ (800f3dc ) 800f372: 6adb ldr r3, [r3, #44] @ 0x2c 800f374: 4a19 ldr r2, [pc, #100] @ (800f3dc ) 800f376: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 800f37a: 62d3 str r3, [r2, #44] @ 0x2c 800f37c: e00f b.n 800f39e } else if (Divider == DIVIDER_Q_UPDATE) 800f37e: 683b ldr r3, [r7, #0] 800f380: 2b01 cmp r3, #1 800f382: d106 bne.n 800f392 { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 800f384: 4b15 ldr r3, [pc, #84] @ (800f3dc ) 800f386: 6adb ldr r3, [r3, #44] @ 0x2c 800f388: 4a14 ldr r2, [pc, #80] @ (800f3dc ) 800f38a: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 800f38e: 62d3 str r3, [r2, #44] @ 0x2c 800f390: e005 b.n 800f39e } else { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 800f392: 4b12 ldr r3, [pc, #72] @ (800f3dc ) 800f394: 6adb ldr r3, [r3, #44] @ 0x2c 800f396: 4a11 ldr r2, [pc, #68] @ (800f3dc ) 800f398: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800f39c: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL3. */ __HAL_RCC_PLL3_ENABLE(); 800f39e: 4b0f ldr r3, [pc, #60] @ (800f3dc ) 800f3a0: 681b ldr r3, [r3, #0] 800f3a2: 4a0e ldr r2, [pc, #56] @ (800f3dc ) 800f3a4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800f3a8: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800f3aa: f7f6 fd7b bl 8005ea4 800f3ae: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800f3b0: e008 b.n 800f3c4 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800f3b2: f7f6 fd77 bl 8005ea4 800f3b6: 4602 mov r2, r0 800f3b8: 68bb ldr r3, [r7, #8] 800f3ba: 1ad3 subs r3, r2, r3 800f3bc: 2b02 cmp r3, #2 800f3be: d901 bls.n 800f3c4 { return HAL_TIMEOUT; 800f3c0: 2303 movs r3, #3 800f3c2: e006 b.n 800f3d2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800f3c4: 4b05 ldr r3, [pc, #20] @ (800f3dc ) 800f3c6: 681b ldr r3, [r3, #0] 800f3c8: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800f3cc: 2b00 cmp r3, #0 800f3ce: d0f0 beq.n 800f3b2 } } return status; 800f3d0: 7bfb ldrb r3, [r7, #15] } 800f3d2: 4618 mov r0, r3 800f3d4: 3710 adds r7, #16 800f3d6: 46bd mov sp, r7 800f3d8: bd80 pop {r7, pc} 800f3da: bf00 nop 800f3dc: 58024400 .word 0x58024400 800f3e0: ffff0007 .word 0xffff0007 0800f3e4 : * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL status */ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { 800f3e4: b580 push {r7, lr} 800f3e6: b084 sub sp, #16 800f3e8: af00 add r7, sp, #0 800f3ea: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the RNG handle allocation */ if (hrng == NULL) 800f3ec: 687b ldr r3, [r7, #4] 800f3ee: 2b00 cmp r3, #0 800f3f0: d101 bne.n 800f3f6 { return HAL_ERROR; 800f3f2: 2301 movs r3, #1 800f3f4: e054 b.n 800f4a0 /* Init the low level hardware */ hrng->MspInitCallback(hrng); } #else if (hrng->State == HAL_RNG_STATE_RESET) 800f3f6: 687b ldr r3, [r7, #4] 800f3f8: 7a5b ldrb r3, [r3, #9] 800f3fa: b2db uxtb r3, r3 800f3fc: 2b00 cmp r3, #0 800f3fe: d105 bne.n 800f40c { /* Allocate lock resource and initialize it */ hrng->Lock = HAL_UNLOCKED; 800f400: 687b ldr r3, [r7, #4] 800f402: 2200 movs r2, #0 800f404: 721a strb r2, [r3, #8] /* Init the low level hardware */ HAL_RNG_MspInit(hrng); 800f406: 6878 ldr r0, [r7, #4] 800f408: f7f4 ff30 bl 800426c } #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; 800f40c: 687b ldr r3, [r7, #4] 800f40e: 2202 movs r2, #2 800f410: 725a strb r2, [r3, #9] } } } #else /* Clock Error Detection Configuration */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection); 800f412: 687b ldr r3, [r7, #4] 800f414: 681b ldr r3, [r3, #0] 800f416: 681b ldr r3, [r3, #0] 800f418: f023 0120 bic.w r1, r3, #32 800f41c: 687b ldr r3, [r7, #4] 800f41e: 685a ldr r2, [r3, #4] 800f420: 687b ldr r3, [r7, #4] 800f422: 681b ldr r3, [r3, #0] 800f424: 430a orrs r2, r1 800f426: 601a str r2, [r3, #0] #endif /* RNG_CR_CONDRST */ /* Enable the RNG Peripheral */ __HAL_RNG_ENABLE(hrng); 800f428: 687b ldr r3, [r7, #4] 800f42a: 681b ldr r3, [r3, #0] 800f42c: 681a ldr r2, [r3, #0] 800f42e: 687b ldr r3, [r7, #4] 800f430: 681b ldr r3, [r3, #0] 800f432: f042 0204 orr.w r2, r2, #4 800f436: 601a str r2, [r3, #0] /* verify that no seed error */ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) 800f438: 687b ldr r3, [r7, #4] 800f43a: 681b ldr r3, [r3, #0] 800f43c: 685b ldr r3, [r3, #4] 800f43e: f003 0340 and.w r3, r3, #64 @ 0x40 800f442: 2b40 cmp r3, #64 @ 0x40 800f444: d104 bne.n 800f450 { hrng->State = HAL_RNG_STATE_ERROR; 800f446: 687b ldr r3, [r7, #4] 800f448: 2204 movs r2, #4 800f44a: 725a strb r2, [r3, #9] return HAL_ERROR; 800f44c: 2301 movs r3, #1 800f44e: e027 b.n 800f4a0 } /* Get tick */ tickstart = HAL_GetTick(); 800f450: f7f6 fd28 bl 8005ea4 800f454: 60f8 str r0, [r7, #12] /* Check if data register contains valid random data */ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f456: e015 b.n 800f484 { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) 800f458: f7f6 fd24 bl 8005ea4 800f45c: 4602 mov r2, r0 800f45e: 68fb ldr r3, [r7, #12] 800f460: 1ad3 subs r3, r2, r3 800f462: 2b02 cmp r3, #2 800f464: d90e bls.n 800f484 { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f466: 687b ldr r3, [r7, #4] 800f468: 681b ldr r3, [r3, #0] 800f46a: 685b ldr r3, [r3, #4] 800f46c: f003 0304 and.w r3, r3, #4 800f470: 2b04 cmp r3, #4 800f472: d107 bne.n 800f484 { hrng->State = HAL_RNG_STATE_ERROR; 800f474: 687b ldr r3, [r7, #4] 800f476: 2204 movs r2, #4 800f478: 725a strb r2, [r3, #9] hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; 800f47a: 687b ldr r3, [r7, #4] 800f47c: 2202 movs r2, #2 800f47e: 60da str r2, [r3, #12] return HAL_ERROR; 800f480: 2301 movs r3, #1 800f482: e00d b.n 800f4a0 while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f484: 687b ldr r3, [r7, #4] 800f486: 681b ldr r3, [r3, #0] 800f488: 685b ldr r3, [r3, #4] 800f48a: f003 0304 and.w r3, r3, #4 800f48e: 2b04 cmp r3, #4 800f490: d0e2 beq.n 800f458 } } } /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; 800f492: 687b ldr r3, [r7, #4] 800f494: 2201 movs r2, #1 800f496: 725a strb r2, [r3, #9] /* Initialise the error code */ hrng->ErrorCode = HAL_RNG_ERROR_NONE; 800f498: 687b ldr r3, [r7, #4] 800f49a: 2200 movs r2, #0 800f49c: 60da str r2, [r3, #12] /* Return function status */ return HAL_OK; 800f49e: 2300 movs r3, #0 } 800f4a0: 4618 mov r0, r3 800f4a2: 3710 adds r7, #16 800f4a4: 46bd mov sp, r7 800f4a6: bd80 pop {r7, pc} 0800f4a8 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 800f4a8: b580 push {r7, lr} 800f4aa: b082 sub sp, #8 800f4ac: af00 add r7, sp, #0 800f4ae: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800f4b0: 687b ldr r3, [r7, #4] 800f4b2: 2b00 cmp r3, #0 800f4b4: d101 bne.n 800f4ba { return HAL_ERROR; 800f4b6: 2301 movs r3, #1 800f4b8: e049 b.n 800f54e assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800f4ba: 687b ldr r3, [r7, #4] 800f4bc: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f4c0: b2db uxtb r3, r3 800f4c2: 2b00 cmp r3, #0 800f4c4: d106 bne.n 800f4d4 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800f4c6: 687b ldr r3, [r7, #4] 800f4c8: 2200 movs r2, #0 800f4ca: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800f4ce: 6878 ldr r0, [r7, #4] 800f4d0: f7f4 ff40 bl 8004354 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f4d4: 687b ldr r3, [r7, #4] 800f4d6: 2202 movs r2, #2 800f4d8: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800f4dc: 687b ldr r3, [r7, #4] 800f4de: 681a ldr r2, [r3, #0] 800f4e0: 687b ldr r3, [r7, #4] 800f4e2: 3304 adds r3, #4 800f4e4: 4619 mov r1, r3 800f4e6: 4610 mov r0, r2 800f4e8: f001 f918 bl 801071c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800f4ec: 687b ldr r3, [r7, #4] 800f4ee: 2201 movs r2, #1 800f4f0: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f4f4: 687b ldr r3, [r7, #4] 800f4f6: 2201 movs r2, #1 800f4f8: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f4fc: 687b ldr r3, [r7, #4] 800f4fe: 2201 movs r2, #1 800f500: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f504: 687b ldr r3, [r7, #4] 800f506: 2201 movs r2, #1 800f508: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f50c: 687b ldr r3, [r7, #4] 800f50e: 2201 movs r2, #1 800f510: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f514: 687b ldr r3, [r7, #4] 800f516: 2201 movs r2, #1 800f518: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f51c: 687b ldr r3, [r7, #4] 800f51e: 2201 movs r2, #1 800f520: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f524: 687b ldr r3, [r7, #4] 800f526: 2201 movs r2, #1 800f528: f883 2044 strb.w r2, [r3, #68] @ 0x44 800f52c: 687b ldr r3, [r7, #4] 800f52e: 2201 movs r2, #1 800f530: f883 2045 strb.w r2, [r3, #69] @ 0x45 800f534: 687b ldr r3, [r7, #4] 800f536: 2201 movs r2, #1 800f538: f883 2046 strb.w r2, [r3, #70] @ 0x46 800f53c: 687b ldr r3, [r7, #4] 800f53e: 2201 movs r2, #1 800f540: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800f544: 687b ldr r3, [r7, #4] 800f546: 2201 movs r2, #1 800f548: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800f54c: 2300 movs r3, #0 } 800f54e: 4618 mov r0, r3 800f550: 3708 adds r7, #8 800f552: 46bd mov sp, r7 800f554: bd80 pop {r7, pc} ... 0800f558 : * @brief Starts the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { 800f558: b480 push {r7} 800f55a: b085 sub sp, #20 800f55c: af00 add r7, sp, #0 800f55e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800f560: 687b ldr r3, [r7, #4] 800f562: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f566: b2db uxtb r3, r3 800f568: 2b01 cmp r3, #1 800f56a: d001 beq.n 800f570 { return HAL_ERROR; 800f56c: 2301 movs r3, #1 800f56e: e04c b.n 800f60a } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f570: 687b ldr r3, [r7, #4] 800f572: 2202 movs r2, #2 800f574: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f578: 687b ldr r3, [r7, #4] 800f57a: 681b ldr r3, [r3, #0] 800f57c: 4a26 ldr r2, [pc, #152] @ (800f618 ) 800f57e: 4293 cmp r3, r2 800f580: d022 beq.n 800f5c8 800f582: 687b ldr r3, [r7, #4] 800f584: 681b ldr r3, [r3, #0] 800f586: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f58a: d01d beq.n 800f5c8 800f58c: 687b ldr r3, [r7, #4] 800f58e: 681b ldr r3, [r3, #0] 800f590: 4a22 ldr r2, [pc, #136] @ (800f61c ) 800f592: 4293 cmp r3, r2 800f594: d018 beq.n 800f5c8 800f596: 687b ldr r3, [r7, #4] 800f598: 681b ldr r3, [r3, #0] 800f59a: 4a21 ldr r2, [pc, #132] @ (800f620 ) 800f59c: 4293 cmp r3, r2 800f59e: d013 beq.n 800f5c8 800f5a0: 687b ldr r3, [r7, #4] 800f5a2: 681b ldr r3, [r3, #0] 800f5a4: 4a1f ldr r2, [pc, #124] @ (800f624 ) 800f5a6: 4293 cmp r3, r2 800f5a8: d00e beq.n 800f5c8 800f5aa: 687b ldr r3, [r7, #4] 800f5ac: 681b ldr r3, [r3, #0] 800f5ae: 4a1e ldr r2, [pc, #120] @ (800f628 ) 800f5b0: 4293 cmp r3, r2 800f5b2: d009 beq.n 800f5c8 800f5b4: 687b ldr r3, [r7, #4] 800f5b6: 681b ldr r3, [r3, #0] 800f5b8: 4a1c ldr r2, [pc, #112] @ (800f62c ) 800f5ba: 4293 cmp r3, r2 800f5bc: d004 beq.n 800f5c8 800f5be: 687b ldr r3, [r7, #4] 800f5c0: 681b ldr r3, [r3, #0] 800f5c2: 4a1b ldr r2, [pc, #108] @ (800f630 ) 800f5c4: 4293 cmp r3, r2 800f5c6: d115 bne.n 800f5f4 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f5c8: 687b ldr r3, [r7, #4] 800f5ca: 681b ldr r3, [r3, #0] 800f5cc: 689a ldr r2, [r3, #8] 800f5ce: 4b19 ldr r3, [pc, #100] @ (800f634 ) 800f5d0: 4013 ands r3, r2 800f5d2: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f5d4: 68fb ldr r3, [r7, #12] 800f5d6: 2b06 cmp r3, #6 800f5d8: d015 beq.n 800f606 800f5da: 68fb ldr r3, [r7, #12] 800f5dc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f5e0: d011 beq.n 800f606 { __HAL_TIM_ENABLE(htim); 800f5e2: 687b ldr r3, [r7, #4] 800f5e4: 681b ldr r3, [r3, #0] 800f5e6: 681a ldr r2, [r3, #0] 800f5e8: 687b ldr r3, [r7, #4] 800f5ea: 681b ldr r3, [r3, #0] 800f5ec: f042 0201 orr.w r2, r2, #1 800f5f0: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f5f2: e008 b.n 800f606 } } else { __HAL_TIM_ENABLE(htim); 800f5f4: 687b ldr r3, [r7, #4] 800f5f6: 681b ldr r3, [r3, #0] 800f5f8: 681a ldr r2, [r3, #0] 800f5fa: 687b ldr r3, [r7, #4] 800f5fc: 681b ldr r3, [r3, #0] 800f5fe: f042 0201 orr.w r2, r2, #1 800f602: 601a str r2, [r3, #0] 800f604: e000 b.n 800f608 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f606: bf00 nop } /* Return function status */ return HAL_OK; 800f608: 2300 movs r3, #0 } 800f60a: 4618 mov r0, r3 800f60c: 3714 adds r7, #20 800f60e: 46bd mov sp, r7 800f610: f85d 7b04 ldr.w r7, [sp], #4 800f614: 4770 bx lr 800f616: bf00 nop 800f618: 40010000 .word 0x40010000 800f61c: 40000400 .word 0x40000400 800f620: 40000800 .word 0x40000800 800f624: 40000c00 .word 0x40000c00 800f628: 40010400 .word 0x40010400 800f62c: 40001800 .word 0x40001800 800f630: 40014000 .word 0x40014000 800f634: 00010007 .word 0x00010007 0800f638 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 800f638: b480 push {r7} 800f63a: b085 sub sp, #20 800f63c: af00 add r7, sp, #0 800f63e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800f640: 687b ldr r3, [r7, #4] 800f642: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f646: b2db uxtb r3, r3 800f648: 2b01 cmp r3, #1 800f64a: d001 beq.n 800f650 { return HAL_ERROR; 800f64c: 2301 movs r3, #1 800f64e: e054 b.n 800f6fa } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f650: 687b ldr r3, [r7, #4] 800f652: 2202 movs r2, #2 800f654: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 800f658: 687b ldr r3, [r7, #4] 800f65a: 681b ldr r3, [r3, #0] 800f65c: 68da ldr r2, [r3, #12] 800f65e: 687b ldr r3, [r7, #4] 800f660: 681b ldr r3, [r3, #0] 800f662: f042 0201 orr.w r2, r2, #1 800f666: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f668: 687b ldr r3, [r7, #4] 800f66a: 681b ldr r3, [r3, #0] 800f66c: 4a26 ldr r2, [pc, #152] @ (800f708 ) 800f66e: 4293 cmp r3, r2 800f670: d022 beq.n 800f6b8 800f672: 687b ldr r3, [r7, #4] 800f674: 681b ldr r3, [r3, #0] 800f676: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f67a: d01d beq.n 800f6b8 800f67c: 687b ldr r3, [r7, #4] 800f67e: 681b ldr r3, [r3, #0] 800f680: 4a22 ldr r2, [pc, #136] @ (800f70c ) 800f682: 4293 cmp r3, r2 800f684: d018 beq.n 800f6b8 800f686: 687b ldr r3, [r7, #4] 800f688: 681b ldr r3, [r3, #0] 800f68a: 4a21 ldr r2, [pc, #132] @ (800f710 ) 800f68c: 4293 cmp r3, r2 800f68e: d013 beq.n 800f6b8 800f690: 687b ldr r3, [r7, #4] 800f692: 681b ldr r3, [r3, #0] 800f694: 4a1f ldr r2, [pc, #124] @ (800f714 ) 800f696: 4293 cmp r3, r2 800f698: d00e beq.n 800f6b8 800f69a: 687b ldr r3, [r7, #4] 800f69c: 681b ldr r3, [r3, #0] 800f69e: 4a1e ldr r2, [pc, #120] @ (800f718 ) 800f6a0: 4293 cmp r3, r2 800f6a2: d009 beq.n 800f6b8 800f6a4: 687b ldr r3, [r7, #4] 800f6a6: 681b ldr r3, [r3, #0] 800f6a8: 4a1c ldr r2, [pc, #112] @ (800f71c ) 800f6aa: 4293 cmp r3, r2 800f6ac: d004 beq.n 800f6b8 800f6ae: 687b ldr r3, [r7, #4] 800f6b0: 681b ldr r3, [r3, #0] 800f6b2: 4a1b ldr r2, [pc, #108] @ (800f720 ) 800f6b4: 4293 cmp r3, r2 800f6b6: d115 bne.n 800f6e4 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f6b8: 687b ldr r3, [r7, #4] 800f6ba: 681b ldr r3, [r3, #0] 800f6bc: 689a ldr r2, [r3, #8] 800f6be: 4b19 ldr r3, [pc, #100] @ (800f724 ) 800f6c0: 4013 ands r3, r2 800f6c2: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f6c4: 68fb ldr r3, [r7, #12] 800f6c6: 2b06 cmp r3, #6 800f6c8: d015 beq.n 800f6f6 800f6ca: 68fb ldr r3, [r7, #12] 800f6cc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f6d0: d011 beq.n 800f6f6 { __HAL_TIM_ENABLE(htim); 800f6d2: 687b ldr r3, [r7, #4] 800f6d4: 681b ldr r3, [r3, #0] 800f6d6: 681a ldr r2, [r3, #0] 800f6d8: 687b ldr r3, [r7, #4] 800f6da: 681b ldr r3, [r3, #0] 800f6dc: f042 0201 orr.w r2, r2, #1 800f6e0: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f6e2: e008 b.n 800f6f6 } } else { __HAL_TIM_ENABLE(htim); 800f6e4: 687b ldr r3, [r7, #4] 800f6e6: 681b ldr r3, [r3, #0] 800f6e8: 681a ldr r2, [r3, #0] 800f6ea: 687b ldr r3, [r7, #4] 800f6ec: 681b ldr r3, [r3, #0] 800f6ee: f042 0201 orr.w r2, r2, #1 800f6f2: 601a str r2, [r3, #0] 800f6f4: e000 b.n 800f6f8 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f6f6: bf00 nop } /* Return function status */ return HAL_OK; 800f6f8: 2300 movs r3, #0 } 800f6fa: 4618 mov r0, r3 800f6fc: 3714 adds r7, #20 800f6fe: 46bd mov sp, r7 800f700: f85d 7b04 ldr.w r7, [sp], #4 800f704: 4770 bx lr 800f706: bf00 nop 800f708: 40010000 .word 0x40010000 800f70c: 40000400 .word 0x40000400 800f710: 40000800 .word 0x40000800 800f714: 40000c00 .word 0x40000c00 800f718: 40010400 .word 0x40010400 800f71c: 40001800 .word 0x40001800 800f720: 40014000 .word 0x40014000 800f724: 00010007 .word 0x00010007 0800f728 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 800f728: b580 push {r7, lr} 800f72a: b082 sub sp, #8 800f72c: af00 add r7, sp, #0 800f72e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800f730: 687b ldr r3, [r7, #4] 800f732: 2b00 cmp r3, #0 800f734: d101 bne.n 800f73a { return HAL_ERROR; 800f736: 2301 movs r3, #1 800f738: e049 b.n 800f7ce assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800f73a: 687b ldr r3, [r7, #4] 800f73c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f740: b2db uxtb r3, r3 800f742: 2b00 cmp r3, #0 800f744: d106 bne.n 800f754 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800f746: 687b ldr r3, [r7, #4] 800f748: 2200 movs r2, #0 800f74a: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 800f74e: 6878 ldr r0, [r7, #4] 800f750: f7f4 fdc6 bl 80042e0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f754: 687b ldr r3, [r7, #4] 800f756: 2202 movs r2, #2 800f758: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800f75c: 687b ldr r3, [r7, #4] 800f75e: 681a ldr r2, [r3, #0] 800f760: 687b ldr r3, [r7, #4] 800f762: 3304 adds r3, #4 800f764: 4619 mov r1, r3 800f766: 4610 mov r0, r2 800f768: f000 ffd8 bl 801071c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800f76c: 687b ldr r3, [r7, #4] 800f76e: 2201 movs r2, #1 800f770: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f774: 687b ldr r3, [r7, #4] 800f776: 2201 movs r2, #1 800f778: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f77c: 687b ldr r3, [r7, #4] 800f77e: 2201 movs r2, #1 800f780: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f784: 687b ldr r3, [r7, #4] 800f786: 2201 movs r2, #1 800f788: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f78c: 687b ldr r3, [r7, #4] 800f78e: 2201 movs r2, #1 800f790: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f794: 687b ldr r3, [r7, #4] 800f796: 2201 movs r2, #1 800f798: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f79c: 687b ldr r3, [r7, #4] 800f79e: 2201 movs r2, #1 800f7a0: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f7a4: 687b ldr r3, [r7, #4] 800f7a6: 2201 movs r2, #1 800f7a8: f883 2044 strb.w r2, [r3, #68] @ 0x44 800f7ac: 687b ldr r3, [r7, #4] 800f7ae: 2201 movs r2, #1 800f7b0: f883 2045 strb.w r2, [r3, #69] @ 0x45 800f7b4: 687b ldr r3, [r7, #4] 800f7b6: 2201 movs r2, #1 800f7b8: f883 2046 strb.w r2, [r3, #70] @ 0x46 800f7bc: 687b ldr r3, [r7, #4] 800f7be: 2201 movs r2, #1 800f7c0: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800f7c4: 687b ldr r3, [r7, #4] 800f7c6: 2201 movs r2, #1 800f7c8: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800f7cc: 2300 movs r3, #0 } 800f7ce: 4618 mov r0, r3 800f7d0: 3708 adds r7, #8 800f7d2: 46bd mov sp, r7 800f7d4: bd80 pop {r7, pc} ... 0800f7d8 : * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 800f7d8: b580 push {r7, lr} 800f7da: b084 sub sp, #16 800f7dc: af00 add r7, sp, #0 800f7de: 6078 str r0, [r7, #4] 800f7e0: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 800f7e2: 683b ldr r3, [r7, #0] 800f7e4: 2b00 cmp r3, #0 800f7e6: d109 bne.n 800f7fc 800f7e8: 687b ldr r3, [r7, #4] 800f7ea: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800f7ee: b2db uxtb r3, r3 800f7f0: 2b01 cmp r3, #1 800f7f2: bf14 ite ne 800f7f4: 2301 movne r3, #1 800f7f6: 2300 moveq r3, #0 800f7f8: b2db uxtb r3, r3 800f7fa: e03c b.n 800f876 800f7fc: 683b ldr r3, [r7, #0] 800f7fe: 2b04 cmp r3, #4 800f800: d109 bne.n 800f816 800f802: 687b ldr r3, [r7, #4] 800f804: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800f808: b2db uxtb r3, r3 800f80a: 2b01 cmp r3, #1 800f80c: bf14 ite ne 800f80e: 2301 movne r3, #1 800f810: 2300 moveq r3, #0 800f812: b2db uxtb r3, r3 800f814: e02f b.n 800f876 800f816: 683b ldr r3, [r7, #0] 800f818: 2b08 cmp r3, #8 800f81a: d109 bne.n 800f830 800f81c: 687b ldr r3, [r7, #4] 800f81e: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800f822: b2db uxtb r3, r3 800f824: 2b01 cmp r3, #1 800f826: bf14 ite ne 800f828: 2301 movne r3, #1 800f82a: 2300 moveq r3, #0 800f82c: b2db uxtb r3, r3 800f82e: e022 b.n 800f876 800f830: 683b ldr r3, [r7, #0] 800f832: 2b0c cmp r3, #12 800f834: d109 bne.n 800f84a 800f836: 687b ldr r3, [r7, #4] 800f838: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800f83c: b2db uxtb r3, r3 800f83e: 2b01 cmp r3, #1 800f840: bf14 ite ne 800f842: 2301 movne r3, #1 800f844: 2300 moveq r3, #0 800f846: b2db uxtb r3, r3 800f848: e015 b.n 800f876 800f84a: 683b ldr r3, [r7, #0] 800f84c: 2b10 cmp r3, #16 800f84e: d109 bne.n 800f864 800f850: 687b ldr r3, [r7, #4] 800f852: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800f856: b2db uxtb r3, r3 800f858: 2b01 cmp r3, #1 800f85a: bf14 ite ne 800f85c: 2301 movne r3, #1 800f85e: 2300 moveq r3, #0 800f860: b2db uxtb r3, r3 800f862: e008 b.n 800f876 800f864: 687b ldr r3, [r7, #4] 800f866: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800f86a: b2db uxtb r3, r3 800f86c: 2b01 cmp r3, #1 800f86e: bf14 ite ne 800f870: 2301 movne r3, #1 800f872: 2300 moveq r3, #0 800f874: b2db uxtb r3, r3 800f876: 2b00 cmp r3, #0 800f878: d001 beq.n 800f87e { return HAL_ERROR; 800f87a: 2301 movs r3, #1 800f87c: e0a1 b.n 800f9c2 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800f87e: 683b ldr r3, [r7, #0] 800f880: 2b00 cmp r3, #0 800f882: d104 bne.n 800f88e 800f884: 687b ldr r3, [r7, #4] 800f886: 2202 movs r2, #2 800f888: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f88c: e023 b.n 800f8d6 800f88e: 683b ldr r3, [r7, #0] 800f890: 2b04 cmp r3, #4 800f892: d104 bne.n 800f89e 800f894: 687b ldr r3, [r7, #4] 800f896: 2202 movs r2, #2 800f898: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f89c: e01b b.n 800f8d6 800f89e: 683b ldr r3, [r7, #0] 800f8a0: 2b08 cmp r3, #8 800f8a2: d104 bne.n 800f8ae 800f8a4: 687b ldr r3, [r7, #4] 800f8a6: 2202 movs r2, #2 800f8a8: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f8ac: e013 b.n 800f8d6 800f8ae: 683b ldr r3, [r7, #0] 800f8b0: 2b0c cmp r3, #12 800f8b2: d104 bne.n 800f8be 800f8b4: 687b ldr r3, [r7, #4] 800f8b6: 2202 movs r2, #2 800f8b8: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f8bc: e00b b.n 800f8d6 800f8be: 683b ldr r3, [r7, #0] 800f8c0: 2b10 cmp r3, #16 800f8c2: d104 bne.n 800f8ce 800f8c4: 687b ldr r3, [r7, #4] 800f8c6: 2202 movs r2, #2 800f8c8: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f8cc: e003 b.n 800f8d6 800f8ce: 687b ldr r3, [r7, #4] 800f8d0: 2202 movs r2, #2 800f8d2: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 800f8d6: 687b ldr r3, [r7, #4] 800f8d8: 681b ldr r3, [r3, #0] 800f8da: 2201 movs r2, #1 800f8dc: 6839 ldr r1, [r7, #0] 800f8de: 4618 mov r0, r3 800f8e0: f001 fc60 bl 80111a4 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800f8e4: 687b ldr r3, [r7, #4] 800f8e6: 681b ldr r3, [r3, #0] 800f8e8: 4a38 ldr r2, [pc, #224] @ (800f9cc ) 800f8ea: 4293 cmp r3, r2 800f8ec: d013 beq.n 800f916 800f8ee: 687b ldr r3, [r7, #4] 800f8f0: 681b ldr r3, [r3, #0] 800f8f2: 4a37 ldr r2, [pc, #220] @ (800f9d0 ) 800f8f4: 4293 cmp r3, r2 800f8f6: d00e beq.n 800f916 800f8f8: 687b ldr r3, [r7, #4] 800f8fa: 681b ldr r3, [r3, #0] 800f8fc: 4a35 ldr r2, [pc, #212] @ (800f9d4 ) 800f8fe: 4293 cmp r3, r2 800f900: d009 beq.n 800f916 800f902: 687b ldr r3, [r7, #4] 800f904: 681b ldr r3, [r3, #0] 800f906: 4a34 ldr r2, [pc, #208] @ (800f9d8 ) 800f908: 4293 cmp r3, r2 800f90a: d004 beq.n 800f916 800f90c: 687b ldr r3, [r7, #4] 800f90e: 681b ldr r3, [r3, #0] 800f910: 4a32 ldr r2, [pc, #200] @ (800f9dc ) 800f912: 4293 cmp r3, r2 800f914: d101 bne.n 800f91a 800f916: 2301 movs r3, #1 800f918: e000 b.n 800f91c 800f91a: 2300 movs r3, #0 800f91c: 2b00 cmp r3, #0 800f91e: d007 beq.n 800f930 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 800f920: 687b ldr r3, [r7, #4] 800f922: 681b ldr r3, [r3, #0] 800f924: 6c5a ldr r2, [r3, #68] @ 0x44 800f926: 687b ldr r3, [r7, #4] 800f928: 681b ldr r3, [r3, #0] 800f92a: f442 4200 orr.w r2, r2, #32768 @ 0x8000 800f92e: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f930: 687b ldr r3, [r7, #4] 800f932: 681b ldr r3, [r3, #0] 800f934: 4a25 ldr r2, [pc, #148] @ (800f9cc ) 800f936: 4293 cmp r3, r2 800f938: d022 beq.n 800f980 800f93a: 687b ldr r3, [r7, #4] 800f93c: 681b ldr r3, [r3, #0] 800f93e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f942: d01d beq.n 800f980 800f944: 687b ldr r3, [r7, #4] 800f946: 681b ldr r3, [r3, #0] 800f948: 4a25 ldr r2, [pc, #148] @ (800f9e0 ) 800f94a: 4293 cmp r3, r2 800f94c: d018 beq.n 800f980 800f94e: 687b ldr r3, [r7, #4] 800f950: 681b ldr r3, [r3, #0] 800f952: 4a24 ldr r2, [pc, #144] @ (800f9e4 ) 800f954: 4293 cmp r3, r2 800f956: d013 beq.n 800f980 800f958: 687b ldr r3, [r7, #4] 800f95a: 681b ldr r3, [r3, #0] 800f95c: 4a22 ldr r2, [pc, #136] @ (800f9e8 ) 800f95e: 4293 cmp r3, r2 800f960: d00e beq.n 800f980 800f962: 687b ldr r3, [r7, #4] 800f964: 681b ldr r3, [r3, #0] 800f966: 4a1a ldr r2, [pc, #104] @ (800f9d0 ) 800f968: 4293 cmp r3, r2 800f96a: d009 beq.n 800f980 800f96c: 687b ldr r3, [r7, #4] 800f96e: 681b ldr r3, [r3, #0] 800f970: 4a1e ldr r2, [pc, #120] @ (800f9ec ) 800f972: 4293 cmp r3, r2 800f974: d004 beq.n 800f980 800f976: 687b ldr r3, [r7, #4] 800f978: 681b ldr r3, [r3, #0] 800f97a: 4a16 ldr r2, [pc, #88] @ (800f9d4 ) 800f97c: 4293 cmp r3, r2 800f97e: d115 bne.n 800f9ac { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f980: 687b ldr r3, [r7, #4] 800f982: 681b ldr r3, [r3, #0] 800f984: 689a ldr r2, [r3, #8] 800f986: 4b1a ldr r3, [pc, #104] @ (800f9f0 ) 800f988: 4013 ands r3, r2 800f98a: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f98c: 68fb ldr r3, [r7, #12] 800f98e: 2b06 cmp r3, #6 800f990: d015 beq.n 800f9be 800f992: 68fb ldr r3, [r7, #12] 800f994: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f998: d011 beq.n 800f9be { __HAL_TIM_ENABLE(htim); 800f99a: 687b ldr r3, [r7, #4] 800f99c: 681b ldr r3, [r3, #0] 800f99e: 681a ldr r2, [r3, #0] 800f9a0: 687b ldr r3, [r7, #4] 800f9a2: 681b ldr r3, [r3, #0] 800f9a4: f042 0201 orr.w r2, r2, #1 800f9a8: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f9aa: e008 b.n 800f9be } } else { __HAL_TIM_ENABLE(htim); 800f9ac: 687b ldr r3, [r7, #4] 800f9ae: 681b ldr r3, [r3, #0] 800f9b0: 681a ldr r2, [r3, #0] 800f9b2: 687b ldr r3, [r7, #4] 800f9b4: 681b ldr r3, [r3, #0] 800f9b6: f042 0201 orr.w r2, r2, #1 800f9ba: 601a str r2, [r3, #0] 800f9bc: e000 b.n 800f9c0 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f9be: bf00 nop } /* Return function status */ return HAL_OK; 800f9c0: 2300 movs r3, #0 } 800f9c2: 4618 mov r0, r3 800f9c4: 3710 adds r7, #16 800f9c6: 46bd mov sp, r7 800f9c8: bd80 pop {r7, pc} 800f9ca: bf00 nop 800f9cc: 40010000 .word 0x40010000 800f9d0: 40010400 .word 0x40010400 800f9d4: 40014000 .word 0x40014000 800f9d8: 40014400 .word 0x40014400 800f9dc: 40014800 .word 0x40014800 800f9e0: 40000400 .word 0x40000400 800f9e4: 40000800 .word 0x40000800 800f9e8: 40000c00 .word 0x40000c00 800f9ec: 40001800 .word 0x40001800 800f9f0: 00010007 .word 0x00010007 0800f9f4 : * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { 800f9f4: b580 push {r7, lr} 800f9f6: b082 sub sp, #8 800f9f8: af00 add r7, sp, #0 800f9fa: 6078 str r0, [r7, #4] 800f9fc: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 800f9fe: 687b ldr r3, [r7, #4] 800fa00: 681b ldr r3, [r3, #0] 800fa02: 2200 movs r2, #0 800fa04: 6839 ldr r1, [r7, #0] 800fa06: 4618 mov r0, r3 800fa08: f001 fbcc bl 80111a4 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800fa0c: 687b ldr r3, [r7, #4] 800fa0e: 681b ldr r3, [r3, #0] 800fa10: 4a3e ldr r2, [pc, #248] @ (800fb0c ) 800fa12: 4293 cmp r3, r2 800fa14: d013 beq.n 800fa3e 800fa16: 687b ldr r3, [r7, #4] 800fa18: 681b ldr r3, [r3, #0] 800fa1a: 4a3d ldr r2, [pc, #244] @ (800fb10 ) 800fa1c: 4293 cmp r3, r2 800fa1e: d00e beq.n 800fa3e 800fa20: 687b ldr r3, [r7, #4] 800fa22: 681b ldr r3, [r3, #0] 800fa24: 4a3b ldr r2, [pc, #236] @ (800fb14 ) 800fa26: 4293 cmp r3, r2 800fa28: d009 beq.n 800fa3e 800fa2a: 687b ldr r3, [r7, #4] 800fa2c: 681b ldr r3, [r3, #0] 800fa2e: 4a3a ldr r2, [pc, #232] @ (800fb18 ) 800fa30: 4293 cmp r3, r2 800fa32: d004 beq.n 800fa3e 800fa34: 687b ldr r3, [r7, #4] 800fa36: 681b ldr r3, [r3, #0] 800fa38: 4a38 ldr r2, [pc, #224] @ (800fb1c ) 800fa3a: 4293 cmp r3, r2 800fa3c: d101 bne.n 800fa42 800fa3e: 2301 movs r3, #1 800fa40: e000 b.n 800fa44 800fa42: 2300 movs r3, #0 800fa44: 2b00 cmp r3, #0 800fa46: d017 beq.n 800fa78 { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); 800fa48: 687b ldr r3, [r7, #4] 800fa4a: 681b ldr r3, [r3, #0] 800fa4c: 6a1a ldr r2, [r3, #32] 800fa4e: f241 1311 movw r3, #4369 @ 0x1111 800fa52: 4013 ands r3, r2 800fa54: 2b00 cmp r3, #0 800fa56: d10f bne.n 800fa78 800fa58: 687b ldr r3, [r7, #4] 800fa5a: 681b ldr r3, [r3, #0] 800fa5c: 6a1a ldr r2, [r3, #32] 800fa5e: f240 4344 movw r3, #1092 @ 0x444 800fa62: 4013 ands r3, r2 800fa64: 2b00 cmp r3, #0 800fa66: d107 bne.n 800fa78 800fa68: 687b ldr r3, [r7, #4] 800fa6a: 681b ldr r3, [r3, #0] 800fa6c: 6c5a ldr r2, [r3, #68] @ 0x44 800fa6e: 687b ldr r3, [r7, #4] 800fa70: 681b ldr r3, [r3, #0] 800fa72: f422 4200 bic.w r2, r2, #32768 @ 0x8000 800fa76: 645a str r2, [r3, #68] @ 0x44 } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); 800fa78: 687b ldr r3, [r7, #4] 800fa7a: 681b ldr r3, [r3, #0] 800fa7c: 6a1a ldr r2, [r3, #32] 800fa7e: f241 1311 movw r3, #4369 @ 0x1111 800fa82: 4013 ands r3, r2 800fa84: 2b00 cmp r3, #0 800fa86: d10f bne.n 800faa8 800fa88: 687b ldr r3, [r7, #4] 800fa8a: 681b ldr r3, [r3, #0] 800fa8c: 6a1a ldr r2, [r3, #32] 800fa8e: f240 4344 movw r3, #1092 @ 0x444 800fa92: 4013 ands r3, r2 800fa94: 2b00 cmp r3, #0 800fa96: d107 bne.n 800faa8 800fa98: 687b ldr r3, [r7, #4] 800fa9a: 681b ldr r3, [r3, #0] 800fa9c: 681a ldr r2, [r3, #0] 800fa9e: 687b ldr r3, [r7, #4] 800faa0: 681b ldr r3, [r3, #0] 800faa2: f022 0201 bic.w r2, r2, #1 800faa6: 601a str r2, [r3, #0] /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); 800faa8: 683b ldr r3, [r7, #0] 800faaa: 2b00 cmp r3, #0 800faac: d104 bne.n 800fab8 800faae: 687b ldr r3, [r7, #4] 800fab0: 2201 movs r2, #1 800fab2: f883 203e strb.w r2, [r3, #62] @ 0x3e 800fab6: e023 b.n 800fb00 800fab8: 683b ldr r3, [r7, #0] 800faba: 2b04 cmp r3, #4 800fabc: d104 bne.n 800fac8 800fabe: 687b ldr r3, [r7, #4] 800fac0: 2201 movs r2, #1 800fac2: f883 203f strb.w r2, [r3, #63] @ 0x3f 800fac6: e01b b.n 800fb00 800fac8: 683b ldr r3, [r7, #0] 800faca: 2b08 cmp r3, #8 800facc: d104 bne.n 800fad8 800face: 687b ldr r3, [r7, #4] 800fad0: 2201 movs r2, #1 800fad2: f883 2040 strb.w r2, [r3, #64] @ 0x40 800fad6: e013 b.n 800fb00 800fad8: 683b ldr r3, [r7, #0] 800fada: 2b0c cmp r3, #12 800fadc: d104 bne.n 800fae8 800fade: 687b ldr r3, [r7, #4] 800fae0: 2201 movs r2, #1 800fae2: f883 2041 strb.w r2, [r3, #65] @ 0x41 800fae6: e00b b.n 800fb00 800fae8: 683b ldr r3, [r7, #0] 800faea: 2b10 cmp r3, #16 800faec: d104 bne.n 800faf8 800faee: 687b ldr r3, [r7, #4] 800faf0: 2201 movs r2, #1 800faf2: f883 2042 strb.w r2, [r3, #66] @ 0x42 800faf6: e003 b.n 800fb00 800faf8: 687b ldr r3, [r7, #4] 800fafa: 2201 movs r2, #1 800fafc: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Return function status */ return HAL_OK; 800fb00: 2300 movs r3, #0 } 800fb02: 4618 mov r0, r3 800fb04: 3708 adds r7, #8 800fb06: 46bd mov sp, r7 800fb08: bd80 pop {r7, pc} 800fb0a: bf00 nop 800fb0c: 40010000 .word 0x40010000 800fb10: 40010400 .word 0x40010400 800fb14: 40014000 .word 0x40014000 800fb18: 40014400 .word 0x40014400 800fb1c: 40014800 .word 0x40014800 0800fb20 : * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) { 800fb20: b580 push {r7, lr} 800fb22: b082 sub sp, #8 800fb24: af00 add r7, sp, #0 800fb26: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800fb28: 687b ldr r3, [r7, #4] 800fb2a: 2b00 cmp r3, #0 800fb2c: d101 bne.n 800fb32 { return HAL_ERROR; 800fb2e: 2301 movs r3, #1 800fb30: e049 b.n 800fbc6 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800fb32: 687b ldr r3, [r7, #4] 800fb34: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800fb38: b2db uxtb r3, r3 800fb3a: 2b00 cmp r3, #0 800fb3c: d106 bne.n 800fb4c { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800fb3e: 687b ldr r3, [r7, #4] 800fb40: 2200 movs r2, #0 800fb42: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->IC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); 800fb46: 6878 ldr r0, [r7, #4] 800fb48: f000 f841 bl 800fbce #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800fb4c: 687b ldr r3, [r7, #4] 800fb4e: 2202 movs r2, #2 800fb50: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800fb54: 687b ldr r3, [r7, #4] 800fb56: 681a ldr r2, [r3, #0] 800fb58: 687b ldr r3, [r7, #4] 800fb5a: 3304 adds r3, #4 800fb5c: 4619 mov r1, r3 800fb5e: 4610 mov r0, r2 800fb60: f000 fddc bl 801071c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800fb64: 687b ldr r3, [r7, #4] 800fb66: 2201 movs r2, #1 800fb68: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800fb6c: 687b ldr r3, [r7, #4] 800fb6e: 2201 movs r2, #1 800fb70: f883 203e strb.w r2, [r3, #62] @ 0x3e 800fb74: 687b ldr r3, [r7, #4] 800fb76: 2201 movs r2, #1 800fb78: f883 203f strb.w r2, [r3, #63] @ 0x3f 800fb7c: 687b ldr r3, [r7, #4] 800fb7e: 2201 movs r2, #1 800fb80: f883 2040 strb.w r2, [r3, #64] @ 0x40 800fb84: 687b ldr r3, [r7, #4] 800fb86: 2201 movs r2, #1 800fb88: f883 2041 strb.w r2, [r3, #65] @ 0x41 800fb8c: 687b ldr r3, [r7, #4] 800fb8e: 2201 movs r2, #1 800fb90: f883 2042 strb.w r2, [r3, #66] @ 0x42 800fb94: 687b ldr r3, [r7, #4] 800fb96: 2201 movs r2, #1 800fb98: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800fb9c: 687b ldr r3, [r7, #4] 800fb9e: 2201 movs r2, #1 800fba0: f883 2044 strb.w r2, [r3, #68] @ 0x44 800fba4: 687b ldr r3, [r7, #4] 800fba6: 2201 movs r2, #1 800fba8: f883 2045 strb.w r2, [r3, #69] @ 0x45 800fbac: 687b ldr r3, [r7, #4] 800fbae: 2201 movs r2, #1 800fbb0: f883 2046 strb.w r2, [r3, #70] @ 0x46 800fbb4: 687b ldr r3, [r7, #4] 800fbb6: 2201 movs r2, #1 800fbb8: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800fbbc: 687b ldr r3, [r7, #4] 800fbbe: 2201 movs r2, #1 800fbc0: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800fbc4: 2300 movs r3, #0 } 800fbc6: 4618 mov r0, r3 800fbc8: 3708 adds r7, #8 800fbca: 46bd mov sp, r7 800fbcc: bd80 pop {r7, pc} 0800fbce : * @brief Initializes the TIM Input Capture MSP. * @param htim TIM Input Capture handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) { 800fbce: b480 push {r7} 800fbd0: b083 sub sp, #12 800fbd2: af00 add r7, sp, #0 800fbd4: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_MspInit could be implemented in the user file */ } 800fbd6: bf00 nop 800fbd8: 370c adds r7, #12 800fbda: 46bd mov sp, r7 800fbdc: f85d 7b04 ldr.w r7, [sp], #4 800fbe0: 4770 bx lr ... 0800fbe4 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { 800fbe4: b580 push {r7, lr} 800fbe6: b084 sub sp, #16 800fbe8: af00 add r7, sp, #0 800fbea: 6078 str r0, [r7, #4] 800fbec: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800fbee: 2300 movs r3, #0 800fbf0: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); 800fbf2: 683b ldr r3, [r7, #0] 800fbf4: 2b00 cmp r3, #0 800fbf6: d104 bne.n 800fc02 800fbf8: 687b ldr r3, [r7, #4] 800fbfa: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800fbfe: b2db uxtb r3, r3 800fc00: e023 b.n 800fc4a 800fc02: 683b ldr r3, [r7, #0] 800fc04: 2b04 cmp r3, #4 800fc06: d104 bne.n 800fc12 800fc08: 687b ldr r3, [r7, #4] 800fc0a: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800fc0e: b2db uxtb r3, r3 800fc10: e01b b.n 800fc4a 800fc12: 683b ldr r3, [r7, #0] 800fc14: 2b08 cmp r3, #8 800fc16: d104 bne.n 800fc22 800fc18: 687b ldr r3, [r7, #4] 800fc1a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800fc1e: b2db uxtb r3, r3 800fc20: e013 b.n 800fc4a 800fc22: 683b ldr r3, [r7, #0] 800fc24: 2b0c cmp r3, #12 800fc26: d104 bne.n 800fc32 800fc28: 687b ldr r3, [r7, #4] 800fc2a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800fc2e: b2db uxtb r3, r3 800fc30: e00b b.n 800fc4a 800fc32: 683b ldr r3, [r7, #0] 800fc34: 2b10 cmp r3, #16 800fc36: d104 bne.n 800fc42 800fc38: 687b ldr r3, [r7, #4] 800fc3a: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800fc3e: b2db uxtb r3, r3 800fc40: e003 b.n 800fc4a 800fc42: 687b ldr r3, [r7, #4] 800fc44: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800fc48: b2db uxtb r3, r3 800fc4a: 73bb strb r3, [r7, #14] HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); 800fc4c: 683b ldr r3, [r7, #0] 800fc4e: 2b00 cmp r3, #0 800fc50: d104 bne.n 800fc5c 800fc52: 687b ldr r3, [r7, #4] 800fc54: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 800fc58: b2db uxtb r3, r3 800fc5a: e013 b.n 800fc84 800fc5c: 683b ldr r3, [r7, #0] 800fc5e: 2b04 cmp r3, #4 800fc60: d104 bne.n 800fc6c 800fc62: 687b ldr r3, [r7, #4] 800fc64: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 800fc68: b2db uxtb r3, r3 800fc6a: e00b b.n 800fc84 800fc6c: 683b ldr r3, [r7, #0] 800fc6e: 2b08 cmp r3, #8 800fc70: d104 bne.n 800fc7c 800fc72: 687b ldr r3, [r7, #4] 800fc74: f893 3046 ldrb.w r3, [r3, #70] @ 0x46 800fc78: b2db uxtb r3, r3 800fc7a: e003 b.n 800fc84 800fc7c: 687b ldr r3, [r7, #4] 800fc7e: f893 3047 ldrb.w r3, [r3, #71] @ 0x47 800fc82: b2db uxtb r3, r3 800fc84: 737b strb r3, [r7, #13] /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) 800fc86: 7bbb ldrb r3, [r7, #14] 800fc88: 2b01 cmp r3, #1 800fc8a: d102 bne.n 800fc92 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) 800fc8c: 7b7b ldrb r3, [r7, #13] 800fc8e: 2b01 cmp r3, #1 800fc90: d001 beq.n 800fc96 { return HAL_ERROR; 800fc92: 2301 movs r3, #1 800fc94: e0e2 b.n 800fe5c } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800fc96: 683b ldr r3, [r7, #0] 800fc98: 2b00 cmp r3, #0 800fc9a: d104 bne.n 800fca6 800fc9c: 687b ldr r3, [r7, #4] 800fc9e: 2202 movs r2, #2 800fca0: f883 203e strb.w r2, [r3, #62] @ 0x3e 800fca4: e023 b.n 800fcee 800fca6: 683b ldr r3, [r7, #0] 800fca8: 2b04 cmp r3, #4 800fcaa: d104 bne.n 800fcb6 800fcac: 687b ldr r3, [r7, #4] 800fcae: 2202 movs r2, #2 800fcb0: f883 203f strb.w r2, [r3, #63] @ 0x3f 800fcb4: e01b b.n 800fcee 800fcb6: 683b ldr r3, [r7, #0] 800fcb8: 2b08 cmp r3, #8 800fcba: d104 bne.n 800fcc6 800fcbc: 687b ldr r3, [r7, #4] 800fcbe: 2202 movs r2, #2 800fcc0: f883 2040 strb.w r2, [r3, #64] @ 0x40 800fcc4: e013 b.n 800fcee 800fcc6: 683b ldr r3, [r7, #0] 800fcc8: 2b0c cmp r3, #12 800fcca: d104 bne.n 800fcd6 800fccc: 687b ldr r3, [r7, #4] 800fcce: 2202 movs r2, #2 800fcd0: f883 2041 strb.w r2, [r3, #65] @ 0x41 800fcd4: e00b b.n 800fcee 800fcd6: 683b ldr r3, [r7, #0] 800fcd8: 2b10 cmp r3, #16 800fcda: d104 bne.n 800fce6 800fcdc: 687b ldr r3, [r7, #4] 800fcde: 2202 movs r2, #2 800fce0: f883 2042 strb.w r2, [r3, #66] @ 0x42 800fce4: e003 b.n 800fcee 800fce6: 687b ldr r3, [r7, #4] 800fce8: 2202 movs r2, #2 800fcea: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800fcee: 683b ldr r3, [r7, #0] 800fcf0: 2b00 cmp r3, #0 800fcf2: d104 bne.n 800fcfe 800fcf4: 687b ldr r3, [r7, #4] 800fcf6: 2202 movs r2, #2 800fcf8: f883 2044 strb.w r2, [r3, #68] @ 0x44 800fcfc: e013 b.n 800fd26 800fcfe: 683b ldr r3, [r7, #0] 800fd00: 2b04 cmp r3, #4 800fd02: d104 bne.n 800fd0e 800fd04: 687b ldr r3, [r7, #4] 800fd06: 2202 movs r2, #2 800fd08: f883 2045 strb.w r2, [r3, #69] @ 0x45 800fd0c: e00b b.n 800fd26 800fd0e: 683b ldr r3, [r7, #0] 800fd10: 2b08 cmp r3, #8 800fd12: d104 bne.n 800fd1e 800fd14: 687b ldr r3, [r7, #4] 800fd16: 2202 movs r2, #2 800fd18: f883 2046 strb.w r2, [r3, #70] @ 0x46 800fd1c: e003 b.n 800fd26 800fd1e: 687b ldr r3, [r7, #4] 800fd20: 2202 movs r2, #2 800fd22: f883 2047 strb.w r2, [r3, #71] @ 0x47 switch (Channel) 800fd26: 683b ldr r3, [r7, #0] 800fd28: 2b0c cmp r3, #12 800fd2a: d841 bhi.n 800fdb0 800fd2c: a201 add r2, pc, #4 @ (adr r2, 800fd34 ) 800fd2e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800fd32: bf00 nop 800fd34: 0800fd69 .word 0x0800fd69 800fd38: 0800fdb1 .word 0x0800fdb1 800fd3c: 0800fdb1 .word 0x0800fdb1 800fd40: 0800fdb1 .word 0x0800fdb1 800fd44: 0800fd7b .word 0x0800fd7b 800fd48: 0800fdb1 .word 0x0800fdb1 800fd4c: 0800fdb1 .word 0x0800fdb1 800fd50: 0800fdb1 .word 0x0800fdb1 800fd54: 0800fd8d .word 0x0800fd8d 800fd58: 0800fdb1 .word 0x0800fdb1 800fd5c: 0800fdb1 .word 0x0800fdb1 800fd60: 0800fdb1 .word 0x0800fdb1 800fd64: 0800fd9f .word 0x0800fd9f { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 800fd68: 687b ldr r3, [r7, #4] 800fd6a: 681b ldr r3, [r3, #0] 800fd6c: 68da ldr r2, [r3, #12] 800fd6e: 687b ldr r3, [r7, #4] 800fd70: 681b ldr r3, [r3, #0] 800fd72: f042 0202 orr.w r2, r2, #2 800fd76: 60da str r2, [r3, #12] break; 800fd78: e01d b.n 800fdb6 } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 800fd7a: 687b ldr r3, [r7, #4] 800fd7c: 681b ldr r3, [r3, #0] 800fd7e: 68da ldr r2, [r3, #12] 800fd80: 687b ldr r3, [r7, #4] 800fd82: 681b ldr r3, [r3, #0] 800fd84: f042 0204 orr.w r2, r2, #4 800fd88: 60da str r2, [r3, #12] break; 800fd8a: e014 b.n 800fdb6 } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 800fd8c: 687b ldr r3, [r7, #4] 800fd8e: 681b ldr r3, [r3, #0] 800fd90: 68da ldr r2, [r3, #12] 800fd92: 687b ldr r3, [r7, #4] 800fd94: 681b ldr r3, [r3, #0] 800fd96: f042 0208 orr.w r2, r2, #8 800fd9a: 60da str r2, [r3, #12] break; 800fd9c: e00b b.n 800fdb6 } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 800fd9e: 687b ldr r3, [r7, #4] 800fda0: 681b ldr r3, [r3, #0] 800fda2: 68da ldr r2, [r3, #12] 800fda4: 687b ldr r3, [r7, #4] 800fda6: 681b ldr r3, [r3, #0] 800fda8: f042 0210 orr.w r2, r2, #16 800fdac: 60da str r2, [r3, #12] break; 800fdae: e002 b.n 800fdb6 } default: status = HAL_ERROR; 800fdb0: 2301 movs r3, #1 800fdb2: 73fb strb r3, [r7, #15] break; 800fdb4: bf00 nop } if (status == HAL_OK) 800fdb6: 7bfb ldrb r3, [r7, #15] 800fdb8: 2b00 cmp r3, #0 800fdba: d14e bne.n 800fe5a { /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 800fdbc: 687b ldr r3, [r7, #4] 800fdbe: 681b ldr r3, [r3, #0] 800fdc0: 2201 movs r2, #1 800fdc2: 6839 ldr r1, [r7, #0] 800fdc4: 4618 mov r0, r3 800fdc6: f001 f9ed bl 80111a4 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800fdca: 687b ldr r3, [r7, #4] 800fdcc: 681b ldr r3, [r3, #0] 800fdce: 4a25 ldr r2, [pc, #148] @ (800fe64 ) 800fdd0: 4293 cmp r3, r2 800fdd2: d022 beq.n 800fe1a 800fdd4: 687b ldr r3, [r7, #4] 800fdd6: 681b ldr r3, [r3, #0] 800fdd8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800fddc: d01d beq.n 800fe1a 800fdde: 687b ldr r3, [r7, #4] 800fde0: 681b ldr r3, [r3, #0] 800fde2: 4a21 ldr r2, [pc, #132] @ (800fe68 ) 800fde4: 4293 cmp r3, r2 800fde6: d018 beq.n 800fe1a 800fde8: 687b ldr r3, [r7, #4] 800fdea: 681b ldr r3, [r3, #0] 800fdec: 4a1f ldr r2, [pc, #124] @ (800fe6c ) 800fdee: 4293 cmp r3, r2 800fdf0: d013 beq.n 800fe1a 800fdf2: 687b ldr r3, [r7, #4] 800fdf4: 681b ldr r3, [r3, #0] 800fdf6: 4a1e ldr r2, [pc, #120] @ (800fe70 ) 800fdf8: 4293 cmp r3, r2 800fdfa: d00e beq.n 800fe1a 800fdfc: 687b ldr r3, [r7, #4] 800fdfe: 681b ldr r3, [r3, #0] 800fe00: 4a1c ldr r2, [pc, #112] @ (800fe74 ) 800fe02: 4293 cmp r3, r2 800fe04: d009 beq.n 800fe1a 800fe06: 687b ldr r3, [r7, #4] 800fe08: 681b ldr r3, [r3, #0] 800fe0a: 4a1b ldr r2, [pc, #108] @ (800fe78 ) 800fe0c: 4293 cmp r3, r2 800fe0e: d004 beq.n 800fe1a 800fe10: 687b ldr r3, [r7, #4] 800fe12: 681b ldr r3, [r3, #0] 800fe14: 4a19 ldr r2, [pc, #100] @ (800fe7c ) 800fe16: 4293 cmp r3, r2 800fe18: d115 bne.n 800fe46 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800fe1a: 687b ldr r3, [r7, #4] 800fe1c: 681b ldr r3, [r3, #0] 800fe1e: 689a ldr r2, [r3, #8] 800fe20: 4b17 ldr r3, [pc, #92] @ (800fe80 ) 800fe22: 4013 ands r3, r2 800fe24: 60bb str r3, [r7, #8] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800fe26: 68bb ldr r3, [r7, #8] 800fe28: 2b06 cmp r3, #6 800fe2a: d015 beq.n 800fe58 800fe2c: 68bb ldr r3, [r7, #8] 800fe2e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800fe32: d011 beq.n 800fe58 { __HAL_TIM_ENABLE(htim); 800fe34: 687b ldr r3, [r7, #4] 800fe36: 681b ldr r3, [r3, #0] 800fe38: 681a ldr r2, [r3, #0] 800fe3a: 687b ldr r3, [r7, #4] 800fe3c: 681b ldr r3, [r3, #0] 800fe3e: f042 0201 orr.w r2, r2, #1 800fe42: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800fe44: e008 b.n 800fe58 } } else { __HAL_TIM_ENABLE(htim); 800fe46: 687b ldr r3, [r7, #4] 800fe48: 681b ldr r3, [r3, #0] 800fe4a: 681a ldr r2, [r3, #0] 800fe4c: 687b ldr r3, [r7, #4] 800fe4e: 681b ldr r3, [r3, #0] 800fe50: f042 0201 orr.w r2, r2, #1 800fe54: 601a str r2, [r3, #0] 800fe56: e000 b.n 800fe5a if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800fe58: bf00 nop } } /* Return function status */ return status; 800fe5a: 7bfb ldrb r3, [r7, #15] } 800fe5c: 4618 mov r0, r3 800fe5e: 3710 adds r7, #16 800fe60: 46bd mov sp, r7 800fe62: bd80 pop {r7, pc} 800fe64: 40010000 .word 0x40010000 800fe68: 40000400 .word 0x40000400 800fe6c: 40000800 .word 0x40000800 800fe70: 40000c00 .word 0x40000c00 800fe74: 40010400 .word 0x40010400 800fe78: 40001800 .word 0x40001800 800fe7c: 40014000 .word 0x40014000 800fe80: 00010007 .word 0x00010007 0800fe84 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 800fe84: b580 push {r7, lr} 800fe86: b084 sub sp, #16 800fe88: af00 add r7, sp, #0 800fe8a: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 800fe8c: 687b ldr r3, [r7, #4] 800fe8e: 681b ldr r3, [r3, #0] 800fe90: 68db ldr r3, [r3, #12] 800fe92: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 800fe94: 687b ldr r3, [r7, #4] 800fe96: 681b ldr r3, [r3, #0] 800fe98: 691b ldr r3, [r3, #16] 800fe9a: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 800fe9c: 68bb ldr r3, [r7, #8] 800fe9e: f003 0302 and.w r3, r3, #2 800fea2: 2b00 cmp r3, #0 800fea4: d020 beq.n 800fee8 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 800fea6: 68fb ldr r3, [r7, #12] 800fea8: f003 0302 and.w r3, r3, #2 800feac: 2b00 cmp r3, #0 800feae: d01b beq.n 800fee8 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 800feb0: 687b ldr r3, [r7, #4] 800feb2: 681b ldr r3, [r3, #0] 800feb4: f06f 0202 mvn.w r2, #2 800feb8: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800feba: 687b ldr r3, [r7, #4] 800febc: 2201 movs r2, #1 800febe: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 800fec0: 687b ldr r3, [r7, #4] 800fec2: 681b ldr r3, [r3, #0] 800fec4: 699b ldr r3, [r3, #24] 800fec6: f003 0303 and.w r3, r3, #3 800feca: 2b00 cmp r3, #0 800fecc: d003 beq.n 800fed6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800fece: 6878 ldr r0, [r7, #4] 800fed0: f7f1 fd6c bl 80019ac 800fed4: e005 b.n 800fee2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800fed6: 6878 ldr r0, [r7, #4] 800fed8: f000 fbc8 bl 801066c HAL_TIM_PWM_PulseFinishedCallback(htim); 800fedc: 6878 ldr r0, [r7, #4] 800fede: f000 fbcf bl 8010680 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800fee2: 687b ldr r3, [r7, #4] 800fee4: 2200 movs r2, #0 800fee6: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 800fee8: 68bb ldr r3, [r7, #8] 800feea: f003 0304 and.w r3, r3, #4 800feee: 2b00 cmp r3, #0 800fef0: d020 beq.n 800ff34 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 800fef2: 68fb ldr r3, [r7, #12] 800fef4: f003 0304 and.w r3, r3, #4 800fef8: 2b00 cmp r3, #0 800fefa: d01b beq.n 800ff34 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 800fefc: 687b ldr r3, [r7, #4] 800fefe: 681b ldr r3, [r3, #0] 800ff00: f06f 0204 mvn.w r2, #4 800ff04: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800ff06: 687b ldr r3, [r7, #4] 800ff08: 2202 movs r2, #2 800ff0a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 800ff0c: 687b ldr r3, [r7, #4] 800ff0e: 681b ldr r3, [r3, #0] 800ff10: 699b ldr r3, [r3, #24] 800ff12: f403 7340 and.w r3, r3, #768 @ 0x300 800ff16: 2b00 cmp r3, #0 800ff18: d003 beq.n 800ff22 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800ff1a: 6878 ldr r0, [r7, #4] 800ff1c: f7f1 fd46 bl 80019ac 800ff20: e005 b.n 800ff2e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800ff22: 6878 ldr r0, [r7, #4] 800ff24: f000 fba2 bl 801066c HAL_TIM_PWM_PulseFinishedCallback(htim); 800ff28: 6878 ldr r0, [r7, #4] 800ff2a: f000 fba9 bl 8010680 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800ff2e: 687b ldr r3, [r7, #4] 800ff30: 2200 movs r2, #0 800ff32: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 800ff34: 68bb ldr r3, [r7, #8] 800ff36: f003 0308 and.w r3, r3, #8 800ff3a: 2b00 cmp r3, #0 800ff3c: d020 beq.n 800ff80 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 800ff3e: 68fb ldr r3, [r7, #12] 800ff40: f003 0308 and.w r3, r3, #8 800ff44: 2b00 cmp r3, #0 800ff46: d01b beq.n 800ff80 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 800ff48: 687b ldr r3, [r7, #4] 800ff4a: 681b ldr r3, [r3, #0] 800ff4c: f06f 0208 mvn.w r2, #8 800ff50: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800ff52: 687b ldr r3, [r7, #4] 800ff54: 2204 movs r2, #4 800ff56: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800ff58: 687b ldr r3, [r7, #4] 800ff5a: 681b ldr r3, [r3, #0] 800ff5c: 69db ldr r3, [r3, #28] 800ff5e: f003 0303 and.w r3, r3, #3 800ff62: 2b00 cmp r3, #0 800ff64: d003 beq.n 800ff6e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800ff66: 6878 ldr r0, [r7, #4] 800ff68: f7f1 fd20 bl 80019ac 800ff6c: e005 b.n 800ff7a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800ff6e: 6878 ldr r0, [r7, #4] 800ff70: f000 fb7c bl 801066c HAL_TIM_PWM_PulseFinishedCallback(htim); 800ff74: 6878 ldr r0, [r7, #4] 800ff76: f000 fb83 bl 8010680 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800ff7a: 687b ldr r3, [r7, #4] 800ff7c: 2200 movs r2, #0 800ff7e: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 800ff80: 68bb ldr r3, [r7, #8] 800ff82: f003 0310 and.w r3, r3, #16 800ff86: 2b00 cmp r3, #0 800ff88: d020 beq.n 800ffcc { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 800ff8a: 68fb ldr r3, [r7, #12] 800ff8c: f003 0310 and.w r3, r3, #16 800ff90: 2b00 cmp r3, #0 800ff92: d01b beq.n 800ffcc { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 800ff94: 687b ldr r3, [r7, #4] 800ff96: 681b ldr r3, [r3, #0] 800ff98: f06f 0210 mvn.w r2, #16 800ff9c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800ff9e: 687b ldr r3, [r7, #4] 800ffa0: 2208 movs r2, #8 800ffa2: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 800ffa4: 687b ldr r3, [r7, #4] 800ffa6: 681b ldr r3, [r3, #0] 800ffa8: 69db ldr r3, [r3, #28] 800ffaa: f403 7340 and.w r3, r3, #768 @ 0x300 800ffae: 2b00 cmp r3, #0 800ffb0: d003 beq.n 800ffba { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800ffb2: 6878 ldr r0, [r7, #4] 800ffb4: f7f1 fcfa bl 80019ac 800ffb8: e005 b.n 800ffc6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800ffba: 6878 ldr r0, [r7, #4] 800ffbc: f000 fb56 bl 801066c HAL_TIM_PWM_PulseFinishedCallback(htim); 800ffc0: 6878 ldr r0, [r7, #4] 800ffc2: f000 fb5d bl 8010680 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800ffc6: 687b ldr r3, [r7, #4] 800ffc8: 2200 movs r2, #0 800ffca: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 800ffcc: 68bb ldr r3, [r7, #8] 800ffce: f003 0301 and.w r3, r3, #1 800ffd2: 2b00 cmp r3, #0 800ffd4: d00c beq.n 800fff0 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 800ffd6: 68fb ldr r3, [r7, #12] 800ffd8: f003 0301 and.w r3, r3, #1 800ffdc: 2b00 cmp r3, #0 800ffde: d007 beq.n 800fff0 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 800ffe0: 687b ldr r3, [r7, #4] 800ffe2: 681b ldr r3, [r3, #0] 800ffe4: f06f 0201 mvn.w r2, #1 800ffe8: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 800ffea: 6878 ldr r0, [r7, #4] 800ffec: f7f1 ff3a bl 8001e64 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800fff0: 68bb ldr r3, [r7, #8] 800fff2: f003 0380 and.w r3, r3, #128 @ 0x80 800fff6: 2b00 cmp r3, #0 800fff8: d104 bne.n 8010004 ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) 800fffa: 68bb ldr r3, [r7, #8] 800fffc: f403 5300 and.w r3, r3, #8192 @ 0x2000 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 8010000: 2b00 cmp r3, #0 8010002: d00c beq.n 801001e { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8010004: 68fb ldr r3, [r7, #12] 8010006: f003 0380 and.w r3, r3, #128 @ 0x80 801000a: 2b00 cmp r3, #0 801000c: d007 beq.n 801001e { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 801000e: 687b ldr r3, [r7, #4] 8010010: 681b ldr r3, [r3, #0] 8010012: f46f 5202 mvn.w r2, #8320 @ 0x2080 8010016: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8010018: 6878 ldr r0, [r7, #4] 801001a: f001 f9ff bl 801141c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 801001e: 68bb ldr r3, [r7, #8] 8010020: f403 7380 and.w r3, r3, #256 @ 0x100 8010024: 2b00 cmp r3, #0 8010026: d00c beq.n 8010042 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8010028: 68fb ldr r3, [r7, #12] 801002a: f003 0380 and.w r3, r3, #128 @ 0x80 801002e: 2b00 cmp r3, #0 8010030: d007 beq.n 8010042 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 8010032: 687b ldr r3, [r7, #4] 8010034: 681b ldr r3, [r3, #0] 8010036: f46f 7280 mvn.w r2, #256 @ 0x100 801003a: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 801003c: 6878 ldr r0, [r7, #4] 801003e: f001 f9f7 bl 8011430 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 8010042: 68bb ldr r3, [r7, #8] 8010044: f003 0340 and.w r3, r3, #64 @ 0x40 8010048: 2b00 cmp r3, #0 801004a: d00c beq.n 8010066 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 801004c: 68fb ldr r3, [r7, #12] 801004e: f003 0340 and.w r3, r3, #64 @ 0x40 8010052: 2b00 cmp r3, #0 8010054: d007 beq.n 8010066 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 8010056: 687b ldr r3, [r7, #4] 8010058: 681b ldr r3, [r3, #0] 801005a: f06f 0240 mvn.w r2, #64 @ 0x40 801005e: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 8010060: 6878 ldr r0, [r7, #4] 8010062: f000 fb17 bl 8010694 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 8010066: 68bb ldr r3, [r7, #8] 8010068: f003 0320 and.w r3, r3, #32 801006c: 2b00 cmp r3, #0 801006e: d00c beq.n 801008a { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 8010070: 68fb ldr r3, [r7, #12] 8010072: f003 0320 and.w r3, r3, #32 8010076: 2b00 cmp r3, #0 8010078: d007 beq.n 801008a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 801007a: 687b ldr r3, [r7, #4] 801007c: 681b ldr r3, [r3, #0] 801007e: f06f 0220 mvn.w r2, #32 8010082: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8010084: 6878 ldr r0, [r7, #4] 8010086: f001 f9bf bl 8011408 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 801008a: bf00 nop 801008c: 3710 adds r7, #16 801008e: 46bd mov sp, r7 8010090: bd80 pop {r7, pc} 08010092 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { 8010092: b580 push {r7, lr} 8010094: b086 sub sp, #24 8010096: af00 add r7, sp, #0 8010098: 60f8 str r0, [r7, #12] 801009a: 60b9 str r1, [r7, #8] 801009c: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 801009e: 2300 movs r3, #0 80100a0: 75fb strb r3, [r7, #23] assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); /* Process Locked */ __HAL_LOCK(htim); 80100a2: 68fb ldr r3, [r7, #12] 80100a4: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80100a8: 2b01 cmp r3, #1 80100aa: d101 bne.n 80100b0 80100ac: 2302 movs r3, #2 80100ae: e088 b.n 80101c2 80100b0: 68fb ldr r3, [r7, #12] 80100b2: 2201 movs r2, #1 80100b4: f883 203c strb.w r2, [r3, #60] @ 0x3c if (Channel == TIM_CHANNEL_1) 80100b8: 687b ldr r3, [r7, #4] 80100ba: 2b00 cmp r3, #0 80100bc: d11b bne.n 80100f6 { /* TI1 Configuration */ TIM_TI1_SetConfig(htim->Instance, 80100be: 68fb ldr r3, [r7, #12] 80100c0: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 80100c2: 68bb ldr r3, [r7, #8] 80100c4: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 80100c6: 68bb ldr r3, [r7, #8] 80100c8: 685a ldr r2, [r3, #4] sConfig->ICFilter); 80100ca: 68bb ldr r3, [r7, #8] 80100cc: 68db ldr r3, [r3, #12] TIM_TI1_SetConfig(htim->Instance, 80100ce: f000 fea1 bl 8010e14 /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; 80100d2: 68fb ldr r3, [r7, #12] 80100d4: 681b ldr r3, [r3, #0] 80100d6: 699a ldr r2, [r3, #24] 80100d8: 68fb ldr r3, [r7, #12] 80100da: 681b ldr r3, [r3, #0] 80100dc: f022 020c bic.w r2, r2, #12 80100e0: 619a str r2, [r3, #24] /* Set the IC1PSC value */ htim->Instance->CCMR1 |= sConfig->ICPrescaler; 80100e2: 68fb ldr r3, [r7, #12] 80100e4: 681b ldr r3, [r3, #0] 80100e6: 6999 ldr r1, [r3, #24] 80100e8: 68bb ldr r3, [r7, #8] 80100ea: 689a ldr r2, [r3, #8] 80100ec: 68fb ldr r3, [r7, #12] 80100ee: 681b ldr r3, [r3, #0] 80100f0: 430a orrs r2, r1 80100f2: 619a str r2, [r3, #24] 80100f4: e060 b.n 80101b8 } else if (Channel == TIM_CHANNEL_2) 80100f6: 687b ldr r3, [r7, #4] 80100f8: 2b04 cmp r3, #4 80100fa: d11c bne.n 8010136 { /* TI2 Configuration */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_TI2_SetConfig(htim->Instance, 80100fc: 68fb ldr r3, [r7, #12] 80100fe: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 8010100: 68bb ldr r3, [r7, #8] 8010102: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 8010104: 68bb ldr r3, [r7, #8] 8010106: 685a ldr r2, [r3, #4] sConfig->ICFilter); 8010108: 68bb ldr r3, [r7, #8] 801010a: 68db ldr r3, [r3, #12] TIM_TI2_SetConfig(htim->Instance, 801010c: f000 ff25 bl 8010f5a /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; 8010110: 68fb ldr r3, [r7, #12] 8010112: 681b ldr r3, [r3, #0] 8010114: 699a ldr r2, [r3, #24] 8010116: 68fb ldr r3, [r7, #12] 8010118: 681b ldr r3, [r3, #0] 801011a: f422 6240 bic.w r2, r2, #3072 @ 0xc00 801011e: 619a str r2, [r3, #24] /* Set the IC2PSC value */ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); 8010120: 68fb ldr r3, [r7, #12] 8010122: 681b ldr r3, [r3, #0] 8010124: 6999 ldr r1, [r3, #24] 8010126: 68bb ldr r3, [r7, #8] 8010128: 689b ldr r3, [r3, #8] 801012a: 021a lsls r2, r3, #8 801012c: 68fb ldr r3, [r7, #12] 801012e: 681b ldr r3, [r3, #0] 8010130: 430a orrs r2, r1 8010132: 619a str r2, [r3, #24] 8010134: e040 b.n 80101b8 } else if (Channel == TIM_CHANNEL_3) 8010136: 687b ldr r3, [r7, #4] 8010138: 2b08 cmp r3, #8 801013a: d11b bne.n 8010174 { /* TI3 Configuration */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); TIM_TI3_SetConfig(htim->Instance, 801013c: 68fb ldr r3, [r7, #12] 801013e: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 8010140: 68bb ldr r3, [r7, #8] 8010142: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 8010144: 68bb ldr r3, [r7, #8] 8010146: 685a ldr r2, [r3, #4] sConfig->ICFilter); 8010148: 68bb ldr r3, [r7, #8] 801014a: 68db ldr r3, [r3, #12] TIM_TI3_SetConfig(htim->Instance, 801014c: f000 ff72 bl 8011034 /* Reset the IC3PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; 8010150: 68fb ldr r3, [r7, #12] 8010152: 681b ldr r3, [r3, #0] 8010154: 69da ldr r2, [r3, #28] 8010156: 68fb ldr r3, [r7, #12] 8010158: 681b ldr r3, [r3, #0] 801015a: f022 020c bic.w r2, r2, #12 801015e: 61da str r2, [r3, #28] /* Set the IC3PSC value */ htim->Instance->CCMR2 |= sConfig->ICPrescaler; 8010160: 68fb ldr r3, [r7, #12] 8010162: 681b ldr r3, [r3, #0] 8010164: 69d9 ldr r1, [r3, #28] 8010166: 68bb ldr r3, [r7, #8] 8010168: 689a ldr r2, [r3, #8] 801016a: 68fb ldr r3, [r7, #12] 801016c: 681b ldr r3, [r3, #0] 801016e: 430a orrs r2, r1 8010170: 61da str r2, [r3, #28] 8010172: e021 b.n 80101b8 } else if (Channel == TIM_CHANNEL_4) 8010174: 687b ldr r3, [r7, #4] 8010176: 2b0c cmp r3, #12 8010178: d11c bne.n 80101b4 { /* TI4 Configuration */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); TIM_TI4_SetConfig(htim->Instance, 801017a: 68fb ldr r3, [r7, #12] 801017c: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 801017e: 68bb ldr r3, [r7, #8] 8010180: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 8010182: 68bb ldr r3, [r7, #8] 8010184: 685a ldr r2, [r3, #4] sConfig->ICFilter); 8010186: 68bb ldr r3, [r7, #8] 8010188: 68db ldr r3, [r3, #12] TIM_TI4_SetConfig(htim->Instance, 801018a: f000 ff8f bl 80110ac /* Reset the IC4PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; 801018e: 68fb ldr r3, [r7, #12] 8010190: 681b ldr r3, [r3, #0] 8010192: 69da ldr r2, [r3, #28] 8010194: 68fb ldr r3, [r7, #12] 8010196: 681b ldr r3, [r3, #0] 8010198: f422 6240 bic.w r2, r2, #3072 @ 0xc00 801019c: 61da str r2, [r3, #28] /* Set the IC4PSC value */ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); 801019e: 68fb ldr r3, [r7, #12] 80101a0: 681b ldr r3, [r3, #0] 80101a2: 69d9 ldr r1, [r3, #28] 80101a4: 68bb ldr r3, [r7, #8] 80101a6: 689b ldr r3, [r3, #8] 80101a8: 021a lsls r2, r3, #8 80101aa: 68fb ldr r3, [r7, #12] 80101ac: 681b ldr r3, [r3, #0] 80101ae: 430a orrs r2, r1 80101b0: 61da str r2, [r3, #28] 80101b2: e001 b.n 80101b8 } else { status = HAL_ERROR; 80101b4: 2301 movs r3, #1 80101b6: 75fb strb r3, [r7, #23] } __HAL_UNLOCK(htim); 80101b8: 68fb ldr r3, [r7, #12] 80101ba: 2200 movs r2, #0 80101bc: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 80101c0: 7dfb ldrb r3, [r7, #23] } 80101c2: 4618 mov r0, r3 80101c4: 3718 adds r7, #24 80101c6: 46bd mov sp, r7 80101c8: bd80 pop {r7, pc} ... 080101cc : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 80101cc: b580 push {r7, lr} 80101ce: b086 sub sp, #24 80101d0: af00 add r7, sp, #0 80101d2: 60f8 str r0, [r7, #12] 80101d4: 60b9 str r1, [r7, #8] 80101d6: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80101d8: 2300 movs r3, #0 80101da: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 80101dc: 68fb ldr r3, [r7, #12] 80101de: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80101e2: 2b01 cmp r3, #1 80101e4: d101 bne.n 80101ea 80101e6: 2302 movs r3, #2 80101e8: e0ff b.n 80103ea 80101ea: 68fb ldr r3, [r7, #12] 80101ec: 2201 movs r2, #1 80101ee: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 80101f2: 687b ldr r3, [r7, #4] 80101f4: 2b14 cmp r3, #20 80101f6: f200 80f0 bhi.w 80103da 80101fa: a201 add r2, pc, #4 @ (adr r2, 8010200 ) 80101fc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8010200: 08010255 .word 0x08010255 8010204: 080103db .word 0x080103db 8010208: 080103db .word 0x080103db 801020c: 080103db .word 0x080103db 8010210: 08010295 .word 0x08010295 8010214: 080103db .word 0x080103db 8010218: 080103db .word 0x080103db 801021c: 080103db .word 0x080103db 8010220: 080102d7 .word 0x080102d7 8010224: 080103db .word 0x080103db 8010228: 080103db .word 0x080103db 801022c: 080103db .word 0x080103db 8010230: 08010317 .word 0x08010317 8010234: 080103db .word 0x080103db 8010238: 080103db .word 0x080103db 801023c: 080103db .word 0x080103db 8010240: 08010359 .word 0x08010359 8010244: 080103db .word 0x080103db 8010248: 080103db .word 0x080103db 801024c: 080103db .word 0x080103db 8010250: 08010399 .word 0x08010399 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8010254: 68fb ldr r3, [r7, #12] 8010256: 681b ldr r3, [r3, #0] 8010258: 68b9 ldr r1, [r7, #8] 801025a: 4618 mov r0, r3 801025c: f000 fb04 bl 8010868 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 8010260: 68fb ldr r3, [r7, #12] 8010262: 681b ldr r3, [r3, #0] 8010264: 699a ldr r2, [r3, #24] 8010266: 68fb ldr r3, [r7, #12] 8010268: 681b ldr r3, [r3, #0] 801026a: f042 0208 orr.w r2, r2, #8 801026e: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 8010270: 68fb ldr r3, [r7, #12] 8010272: 681b ldr r3, [r3, #0] 8010274: 699a ldr r2, [r3, #24] 8010276: 68fb ldr r3, [r7, #12] 8010278: 681b ldr r3, [r3, #0] 801027a: f022 0204 bic.w r2, r2, #4 801027e: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 8010280: 68fb ldr r3, [r7, #12] 8010282: 681b ldr r3, [r3, #0] 8010284: 6999 ldr r1, [r3, #24] 8010286: 68bb ldr r3, [r7, #8] 8010288: 691a ldr r2, [r3, #16] 801028a: 68fb ldr r3, [r7, #12] 801028c: 681b ldr r3, [r3, #0] 801028e: 430a orrs r2, r1 8010290: 619a str r2, [r3, #24] break; 8010292: e0a5 b.n 80103e0 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8010294: 68fb ldr r3, [r7, #12] 8010296: 681b ldr r3, [r3, #0] 8010298: 68b9 ldr r1, [r7, #8] 801029a: 4618 mov r0, r3 801029c: f000 fb74 bl 8010988 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 80102a0: 68fb ldr r3, [r7, #12] 80102a2: 681b ldr r3, [r3, #0] 80102a4: 699a ldr r2, [r3, #24] 80102a6: 68fb ldr r3, [r7, #12] 80102a8: 681b ldr r3, [r3, #0] 80102aa: f442 6200 orr.w r2, r2, #2048 @ 0x800 80102ae: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 80102b0: 68fb ldr r3, [r7, #12] 80102b2: 681b ldr r3, [r3, #0] 80102b4: 699a ldr r2, [r3, #24] 80102b6: 68fb ldr r3, [r7, #12] 80102b8: 681b ldr r3, [r3, #0] 80102ba: f422 6280 bic.w r2, r2, #1024 @ 0x400 80102be: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 80102c0: 68fb ldr r3, [r7, #12] 80102c2: 681b ldr r3, [r3, #0] 80102c4: 6999 ldr r1, [r3, #24] 80102c6: 68bb ldr r3, [r7, #8] 80102c8: 691b ldr r3, [r3, #16] 80102ca: 021a lsls r2, r3, #8 80102cc: 68fb ldr r3, [r7, #12] 80102ce: 681b ldr r3, [r3, #0] 80102d0: 430a orrs r2, r1 80102d2: 619a str r2, [r3, #24] break; 80102d4: e084 b.n 80103e0 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 80102d6: 68fb ldr r3, [r7, #12] 80102d8: 681b ldr r3, [r3, #0] 80102da: 68b9 ldr r1, [r7, #8] 80102dc: 4618 mov r0, r3 80102de: f000 fbdd bl 8010a9c /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 80102e2: 68fb ldr r3, [r7, #12] 80102e4: 681b ldr r3, [r3, #0] 80102e6: 69da ldr r2, [r3, #28] 80102e8: 68fb ldr r3, [r7, #12] 80102ea: 681b ldr r3, [r3, #0] 80102ec: f042 0208 orr.w r2, r2, #8 80102f0: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 80102f2: 68fb ldr r3, [r7, #12] 80102f4: 681b ldr r3, [r3, #0] 80102f6: 69da ldr r2, [r3, #28] 80102f8: 68fb ldr r3, [r7, #12] 80102fa: 681b ldr r3, [r3, #0] 80102fc: f022 0204 bic.w r2, r2, #4 8010300: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 8010302: 68fb ldr r3, [r7, #12] 8010304: 681b ldr r3, [r3, #0] 8010306: 69d9 ldr r1, [r3, #28] 8010308: 68bb ldr r3, [r7, #8] 801030a: 691a ldr r2, [r3, #16] 801030c: 68fb ldr r3, [r7, #12] 801030e: 681b ldr r3, [r3, #0] 8010310: 430a orrs r2, r1 8010312: 61da str r2, [r3, #28] break; 8010314: e064 b.n 80103e0 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8010316: 68fb ldr r3, [r7, #12] 8010318: 681b ldr r3, [r3, #0] 801031a: 68b9 ldr r1, [r7, #8] 801031c: 4618 mov r0, r3 801031e: f000 fc45 bl 8010bac /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 8010322: 68fb ldr r3, [r7, #12] 8010324: 681b ldr r3, [r3, #0] 8010326: 69da ldr r2, [r3, #28] 8010328: 68fb ldr r3, [r7, #12] 801032a: 681b ldr r3, [r3, #0] 801032c: f442 6200 orr.w r2, r2, #2048 @ 0x800 8010330: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 8010332: 68fb ldr r3, [r7, #12] 8010334: 681b ldr r3, [r3, #0] 8010336: 69da ldr r2, [r3, #28] 8010338: 68fb ldr r3, [r7, #12] 801033a: 681b ldr r3, [r3, #0] 801033c: f422 6280 bic.w r2, r2, #1024 @ 0x400 8010340: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 8010342: 68fb ldr r3, [r7, #12] 8010344: 681b ldr r3, [r3, #0] 8010346: 69d9 ldr r1, [r3, #28] 8010348: 68bb ldr r3, [r7, #8] 801034a: 691b ldr r3, [r3, #16] 801034c: 021a lsls r2, r3, #8 801034e: 68fb ldr r3, [r7, #12] 8010350: 681b ldr r3, [r3, #0] 8010352: 430a orrs r2, r1 8010354: 61da str r2, [r3, #28] break; 8010356: e043 b.n 80103e0 { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); 8010358: 68fb ldr r3, [r7, #12] 801035a: 681b ldr r3, [r3, #0] 801035c: 68b9 ldr r1, [r7, #8] 801035e: 4618 mov r0, r3 8010360: f000 fc8e bl 8010c80 /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 8010364: 68fb ldr r3, [r7, #12] 8010366: 681b ldr r3, [r3, #0] 8010368: 6d5a ldr r2, [r3, #84] @ 0x54 801036a: 68fb ldr r3, [r7, #12] 801036c: 681b ldr r3, [r3, #0] 801036e: f042 0208 orr.w r2, r2, #8 8010372: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 8010374: 68fb ldr r3, [r7, #12] 8010376: 681b ldr r3, [r3, #0] 8010378: 6d5a ldr r2, [r3, #84] @ 0x54 801037a: 68fb ldr r3, [r7, #12] 801037c: 681b ldr r3, [r3, #0] 801037e: f022 0204 bic.w r2, r2, #4 8010382: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; 8010384: 68fb ldr r3, [r7, #12] 8010386: 681b ldr r3, [r3, #0] 8010388: 6d59 ldr r1, [r3, #84] @ 0x54 801038a: 68bb ldr r3, [r7, #8] 801038c: 691a ldr r2, [r3, #16] 801038e: 68fb ldr r3, [r7, #12] 8010390: 681b ldr r3, [r3, #0] 8010392: 430a orrs r2, r1 8010394: 655a str r2, [r3, #84] @ 0x54 break; 8010396: e023 b.n 80103e0 { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); 8010398: 68fb ldr r3, [r7, #12] 801039a: 681b ldr r3, [r3, #0] 801039c: 68b9 ldr r1, [r7, #8] 801039e: 4618 mov r0, r3 80103a0: f000 fcd2 bl 8010d48 /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 80103a4: 68fb ldr r3, [r7, #12] 80103a6: 681b ldr r3, [r3, #0] 80103a8: 6d5a ldr r2, [r3, #84] @ 0x54 80103aa: 68fb ldr r3, [r7, #12] 80103ac: 681b ldr r3, [r3, #0] 80103ae: f442 6200 orr.w r2, r2, #2048 @ 0x800 80103b2: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 80103b4: 68fb ldr r3, [r7, #12] 80103b6: 681b ldr r3, [r3, #0] 80103b8: 6d5a ldr r2, [r3, #84] @ 0x54 80103ba: 68fb ldr r3, [r7, #12] 80103bc: 681b ldr r3, [r3, #0] 80103be: f422 6280 bic.w r2, r2, #1024 @ 0x400 80103c2: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 80103c4: 68fb ldr r3, [r7, #12] 80103c6: 681b ldr r3, [r3, #0] 80103c8: 6d59 ldr r1, [r3, #84] @ 0x54 80103ca: 68bb ldr r3, [r7, #8] 80103cc: 691b ldr r3, [r3, #16] 80103ce: 021a lsls r2, r3, #8 80103d0: 68fb ldr r3, [r7, #12] 80103d2: 681b ldr r3, [r3, #0] 80103d4: 430a orrs r2, r1 80103d6: 655a str r2, [r3, #84] @ 0x54 break; 80103d8: e002 b.n 80103e0 } default: status = HAL_ERROR; 80103da: 2301 movs r3, #1 80103dc: 75fb strb r3, [r7, #23] break; 80103de: bf00 nop } __HAL_UNLOCK(htim); 80103e0: 68fb ldr r3, [r7, #12] 80103e2: 2200 movs r2, #0 80103e4: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 80103e8: 7dfb ldrb r3, [r7, #23] } 80103ea: 4618 mov r0, r3 80103ec: 3718 adds r7, #24 80103ee: 46bd mov sp, r7 80103f0: bd80 pop {r7, pc} 80103f2: bf00 nop 080103f4 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 80103f4: b580 push {r7, lr} 80103f6: b084 sub sp, #16 80103f8: af00 add r7, sp, #0 80103fa: 6078 str r0, [r7, #4] 80103fc: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 80103fe: 2300 movs r3, #0 8010400: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 8010402: 687b ldr r3, [r7, #4] 8010404: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8010408: 2b01 cmp r3, #1 801040a: d101 bne.n 8010410 801040c: 2302 movs r3, #2 801040e: e0dc b.n 80105ca 8010410: 687b ldr r3, [r7, #4] 8010412: 2201 movs r2, #1 8010414: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 8010418: 687b ldr r3, [r7, #4] 801041a: 2202 movs r2, #2 801041c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 8010420: 687b ldr r3, [r7, #4] 8010422: 681b ldr r3, [r3, #0] 8010424: 689b ldr r3, [r3, #8] 8010426: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 8010428: 68ba ldr r2, [r7, #8] 801042a: 4b6a ldr r3, [pc, #424] @ (80105d4 ) 801042c: 4013 ands r3, r2 801042e: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8010430: 68bb ldr r3, [r7, #8] 8010432: f423 437f bic.w r3, r3, #65280 @ 0xff00 8010436: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 8010438: 687b ldr r3, [r7, #4] 801043a: 681b ldr r3, [r3, #0] 801043c: 68ba ldr r2, [r7, #8] 801043e: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 8010440: 683b ldr r3, [r7, #0] 8010442: 681b ldr r3, [r3, #0] 8010444: 4a64 ldr r2, [pc, #400] @ (80105d8 ) 8010446: 4293 cmp r3, r2 8010448: f000 80a9 beq.w 801059e 801044c: 4a62 ldr r2, [pc, #392] @ (80105d8 ) 801044e: 4293 cmp r3, r2 8010450: f200 80ae bhi.w 80105b0 8010454: 4a61 ldr r2, [pc, #388] @ (80105dc ) 8010456: 4293 cmp r3, r2 8010458: f000 80a1 beq.w 801059e 801045c: 4a5f ldr r2, [pc, #380] @ (80105dc ) 801045e: 4293 cmp r3, r2 8010460: f200 80a6 bhi.w 80105b0 8010464: 4a5e ldr r2, [pc, #376] @ (80105e0 ) 8010466: 4293 cmp r3, r2 8010468: f000 8099 beq.w 801059e 801046c: 4a5c ldr r2, [pc, #368] @ (80105e0 ) 801046e: 4293 cmp r3, r2 8010470: f200 809e bhi.w 80105b0 8010474: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 8010478: f000 8091 beq.w 801059e 801047c: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 8010480: f200 8096 bhi.w 80105b0 8010484: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8010488: f000 8089 beq.w 801059e 801048c: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8010490: f200 808e bhi.w 80105b0 8010494: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8010498: d03e beq.n 8010518 801049a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 801049e: f200 8087 bhi.w 80105b0 80104a2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80104a6: f000 8086 beq.w 80105b6 80104aa: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80104ae: d87f bhi.n 80105b0 80104b0: 2b70 cmp r3, #112 @ 0x70 80104b2: d01a beq.n 80104ea 80104b4: 2b70 cmp r3, #112 @ 0x70 80104b6: d87b bhi.n 80105b0 80104b8: 2b60 cmp r3, #96 @ 0x60 80104ba: d050 beq.n 801055e 80104bc: 2b60 cmp r3, #96 @ 0x60 80104be: d877 bhi.n 80105b0 80104c0: 2b50 cmp r3, #80 @ 0x50 80104c2: d03c beq.n 801053e 80104c4: 2b50 cmp r3, #80 @ 0x50 80104c6: d873 bhi.n 80105b0 80104c8: 2b40 cmp r3, #64 @ 0x40 80104ca: d058 beq.n 801057e 80104cc: 2b40 cmp r3, #64 @ 0x40 80104ce: d86f bhi.n 80105b0 80104d0: 2b30 cmp r3, #48 @ 0x30 80104d2: d064 beq.n 801059e 80104d4: 2b30 cmp r3, #48 @ 0x30 80104d6: d86b bhi.n 80105b0 80104d8: 2b20 cmp r3, #32 80104da: d060 beq.n 801059e 80104dc: 2b20 cmp r3, #32 80104de: d867 bhi.n 80105b0 80104e0: 2b00 cmp r3, #0 80104e2: d05c beq.n 801059e 80104e4: 2b10 cmp r3, #16 80104e6: d05a beq.n 801059e 80104e8: e062 b.n 80105b0 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80104ea: 687b ldr r3, [r7, #4] 80104ec: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 80104ee: 683b ldr r3, [r7, #0] 80104f0: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 80104f2: 683b ldr r3, [r7, #0] 80104f4: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 80104f6: 683b ldr r3, [r7, #0] 80104f8: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 80104fa: f000 fe33 bl 8011164 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 80104fe: 687b ldr r3, [r7, #4] 8010500: 681b ldr r3, [r3, #0] 8010502: 689b ldr r3, [r3, #8] 8010504: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 8010506: 68bb ldr r3, [r7, #8] 8010508: f043 0377 orr.w r3, r3, #119 @ 0x77 801050c: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 801050e: 687b ldr r3, [r7, #4] 8010510: 681b ldr r3, [r3, #0] 8010512: 68ba ldr r2, [r7, #8] 8010514: 609a str r2, [r3, #8] break; 8010516: e04f b.n 80105b8 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8010518: 687b ldr r3, [r7, #4] 801051a: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 801051c: 683b ldr r3, [r7, #0] 801051e: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 8010520: 683b ldr r3, [r7, #0] 8010522: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8010524: 683b ldr r3, [r7, #0] 8010526: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8010528: f000 fe1c bl 8011164 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 801052c: 687b ldr r3, [r7, #4] 801052e: 681b ldr r3, [r3, #0] 8010530: 689a ldr r2, [r3, #8] 8010532: 687b ldr r3, [r7, #4] 8010534: 681b ldr r3, [r3, #0] 8010536: f442 4280 orr.w r2, r2, #16384 @ 0x4000 801053a: 609a str r2, [r3, #8] break; 801053c: e03c b.n 80105b8 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 801053e: 687b ldr r3, [r7, #4] 8010540: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8010542: 683b ldr r3, [r7, #0] 8010544: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8010546: 683b ldr r3, [r7, #0] 8010548: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 801054a: 461a mov r2, r3 801054c: f000 fcd6 bl 8010efc TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 8010550: 687b ldr r3, [r7, #4] 8010552: 681b ldr r3, [r3, #0] 8010554: 2150 movs r1, #80 @ 0x50 8010556: 4618 mov r0, r3 8010558: f000 fde6 bl 8011128 break; 801055c: e02c b.n 80105b8 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 801055e: 687b ldr r3, [r7, #4] 8010560: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8010562: 683b ldr r3, [r7, #0] 8010564: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8010566: 683b ldr r3, [r7, #0] 8010568: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 801056a: 461a mov r2, r3 801056c: f000 fd32 bl 8010fd4 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 8010570: 687b ldr r3, [r7, #4] 8010572: 681b ldr r3, [r3, #0] 8010574: 2160 movs r1, #96 @ 0x60 8010576: 4618 mov r0, r3 8010578: f000 fdd6 bl 8011128 break; 801057c: e01c b.n 80105b8 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 801057e: 687b ldr r3, [r7, #4] 8010580: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8010582: 683b ldr r3, [r7, #0] 8010584: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8010586: 683b ldr r3, [r7, #0] 8010588: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 801058a: 461a mov r2, r3 801058c: f000 fcb6 bl 8010efc TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 8010590: 687b ldr r3, [r7, #4] 8010592: 681b ldr r3, [r3, #0] 8010594: 2140 movs r1, #64 @ 0x40 8010596: 4618 mov r0, r3 8010598: f000 fdc6 bl 8011128 break; 801059c: e00c b.n 80105b8 case TIM_CLOCKSOURCE_ITR8: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 801059e: 687b ldr r3, [r7, #4] 80105a0: 681a ldr r2, [r3, #0] 80105a2: 683b ldr r3, [r7, #0] 80105a4: 681b ldr r3, [r3, #0] 80105a6: 4619 mov r1, r3 80105a8: 4610 mov r0, r2 80105aa: f000 fdbd bl 8011128 break; 80105ae: e003 b.n 80105b8 } default: status = HAL_ERROR; 80105b0: 2301 movs r3, #1 80105b2: 73fb strb r3, [r7, #15] break; 80105b4: e000 b.n 80105b8 break; 80105b6: bf00 nop } htim->State = HAL_TIM_STATE_READY; 80105b8: 687b ldr r3, [r7, #4] 80105ba: 2201 movs r2, #1 80105bc: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 80105c0: 687b ldr r3, [r7, #4] 80105c2: 2200 movs r2, #0 80105c4: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 80105c8: 7bfb ldrb r3, [r7, #15] } 80105ca: 4618 mov r0, r3 80105cc: 3710 adds r7, #16 80105ce: 46bd mov sp, r7 80105d0: bd80 pop {r7, pc} 80105d2: bf00 nop 80105d4: ffceff88 .word 0xffceff88 80105d8: 00100040 .word 0x00100040 80105dc: 00100030 .word 0x00100030 80105e0: 00100020 .word 0x00100020 080105e4 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval Captured value */ uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) { 80105e4: b480 push {r7} 80105e6: b085 sub sp, #20 80105e8: af00 add r7, sp, #0 80105ea: 6078 str r0, [r7, #4] 80105ec: 6039 str r1, [r7, #0] uint32_t tmpreg = 0U; 80105ee: 2300 movs r3, #0 80105f0: 60fb str r3, [r7, #12] switch (Channel) 80105f2: 683b ldr r3, [r7, #0] 80105f4: 2b0c cmp r3, #12 80105f6: d831 bhi.n 801065c 80105f8: a201 add r2, pc, #4 @ (adr r2, 8010600 ) 80105fa: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80105fe: bf00 nop 8010600: 08010635 .word 0x08010635 8010604: 0801065d .word 0x0801065d 8010608: 0801065d .word 0x0801065d 801060c: 0801065d .word 0x0801065d 8010610: 0801063f .word 0x0801063f 8010614: 0801065d .word 0x0801065d 8010618: 0801065d .word 0x0801065d 801061c: 0801065d .word 0x0801065d 8010620: 08010649 .word 0x08010649 8010624: 0801065d .word 0x0801065d 8010628: 0801065d .word 0x0801065d 801062c: 0801065d .word 0x0801065d 8010630: 08010653 .word 0x08010653 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Return the capture 1 value */ tmpreg = htim->Instance->CCR1; 8010634: 687b ldr r3, [r7, #4] 8010636: 681b ldr r3, [r3, #0] 8010638: 6b5b ldr r3, [r3, #52] @ 0x34 801063a: 60fb str r3, [r7, #12] break; 801063c: e00f b.n 801065e { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Return the capture 2 value */ tmpreg = htim->Instance->CCR2; 801063e: 687b ldr r3, [r7, #4] 8010640: 681b ldr r3, [r3, #0] 8010642: 6b9b ldr r3, [r3, #56] @ 0x38 8010644: 60fb str r3, [r7, #12] break; 8010646: e00a b.n 801065e { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Return the capture 3 value */ tmpreg = htim->Instance->CCR3; 8010648: 687b ldr r3, [r7, #4] 801064a: 681b ldr r3, [r3, #0] 801064c: 6bdb ldr r3, [r3, #60] @ 0x3c 801064e: 60fb str r3, [r7, #12] break; 8010650: e005 b.n 801065e { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Return the capture 4 value */ tmpreg = htim->Instance->CCR4; 8010652: 687b ldr r3, [r7, #4] 8010654: 681b ldr r3, [r3, #0] 8010656: 6c1b ldr r3, [r3, #64] @ 0x40 8010658: 60fb str r3, [r7, #12] break; 801065a: e000 b.n 801065e } default: break; 801065c: bf00 nop } return tmpreg; 801065e: 68fb ldr r3, [r7, #12] } 8010660: 4618 mov r0, r3 8010662: 3714 adds r7, #20 8010664: 46bd mov sp, r7 8010666: f85d 7b04 ldr.w r7, [sp], #4 801066a: 4770 bx lr 0801066c : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 801066c: b480 push {r7} 801066e: b083 sub sp, #12 8010670: af00 add r7, sp, #0 8010672: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 8010674: bf00 nop 8010676: 370c adds r7, #12 8010678: 46bd mov sp, r7 801067a: f85d 7b04 ldr.w r7, [sp], #4 801067e: 4770 bx lr 08010680 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8010680: b480 push {r7} 8010682: b083 sub sp, #12 8010684: af00 add r7, sp, #0 8010686: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8010688: bf00 nop 801068a: 370c adds r7, #12 801068c: 46bd mov sp, r7 801068e: f85d 7b04 ldr.w r7, [sp], #4 8010692: 4770 bx lr 08010694 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8010694: b480 push {r7} 8010696: b083 sub sp, #12 8010698: af00 add r7, sp, #0 801069a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 801069c: bf00 nop 801069e: 370c adds r7, #12 80106a0: 46bd mov sp, r7 80106a2: f85d 7b04 ldr.w r7, [sp], #4 80106a6: 4770 bx lr 080106a8 : * @arg TIM_CHANNEL_5: TIM Channel 5 * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) { 80106a8: b480 push {r7} 80106aa: b085 sub sp, #20 80106ac: af00 add r7, sp, #0 80106ae: 6078 str r0, [r7, #4] 80106b0: 6039 str r1, [r7, #0] HAL_TIM_ChannelStateTypeDef channel_state; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); 80106b2: 683b ldr r3, [r7, #0] 80106b4: 2b00 cmp r3, #0 80106b6: d104 bne.n 80106c2 80106b8: 687b ldr r3, [r7, #4] 80106ba: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 80106be: b2db uxtb r3, r3 80106c0: e023 b.n 801070a 80106c2: 683b ldr r3, [r7, #0] 80106c4: 2b04 cmp r3, #4 80106c6: d104 bne.n 80106d2 80106c8: 687b ldr r3, [r7, #4] 80106ca: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 80106ce: b2db uxtb r3, r3 80106d0: e01b b.n 801070a 80106d2: 683b ldr r3, [r7, #0] 80106d4: 2b08 cmp r3, #8 80106d6: d104 bne.n 80106e2 80106d8: 687b ldr r3, [r7, #4] 80106da: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 80106de: b2db uxtb r3, r3 80106e0: e013 b.n 801070a 80106e2: 683b ldr r3, [r7, #0] 80106e4: 2b0c cmp r3, #12 80106e6: d104 bne.n 80106f2 80106e8: 687b ldr r3, [r7, #4] 80106ea: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80106ee: b2db uxtb r3, r3 80106f0: e00b b.n 801070a 80106f2: 683b ldr r3, [r7, #0] 80106f4: 2b10 cmp r3, #16 80106f6: d104 bne.n 8010702 80106f8: 687b ldr r3, [r7, #4] 80106fa: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 80106fe: b2db uxtb r3, r3 8010700: e003 b.n 801070a 8010702: 687b ldr r3, [r7, #4] 8010704: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 8010708: b2db uxtb r3, r3 801070a: 73fb strb r3, [r7, #15] return channel_state; 801070c: 7bfb ldrb r3, [r7, #15] } 801070e: 4618 mov r0, r3 8010710: 3714 adds r7, #20 8010712: 46bd mov sp, r7 8010714: f85d 7b04 ldr.w r7, [sp], #4 8010718: 4770 bx lr ... 0801071c : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 801071c: b480 push {r7} 801071e: b085 sub sp, #20 8010720: af00 add r7, sp, #0 8010722: 6078 str r0, [r7, #4] 8010724: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8010726: 687b ldr r3, [r7, #4] 8010728: 681b ldr r3, [r3, #0] 801072a: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 801072c: 687b ldr r3, [r7, #4] 801072e: 4a46 ldr r2, [pc, #280] @ (8010848 ) 8010730: 4293 cmp r3, r2 8010732: d013 beq.n 801075c 8010734: 687b ldr r3, [r7, #4] 8010736: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 801073a: d00f beq.n 801075c 801073c: 687b ldr r3, [r7, #4] 801073e: 4a43 ldr r2, [pc, #268] @ (801084c ) 8010740: 4293 cmp r3, r2 8010742: d00b beq.n 801075c 8010744: 687b ldr r3, [r7, #4] 8010746: 4a42 ldr r2, [pc, #264] @ (8010850 ) 8010748: 4293 cmp r3, r2 801074a: d007 beq.n 801075c 801074c: 687b ldr r3, [r7, #4] 801074e: 4a41 ldr r2, [pc, #260] @ (8010854 ) 8010750: 4293 cmp r3, r2 8010752: d003 beq.n 801075c 8010754: 687b ldr r3, [r7, #4] 8010756: 4a40 ldr r2, [pc, #256] @ (8010858 ) 8010758: 4293 cmp r3, r2 801075a: d108 bne.n 801076e { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 801075c: 68fb ldr r3, [r7, #12] 801075e: f023 0370 bic.w r3, r3, #112 @ 0x70 8010762: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8010764: 683b ldr r3, [r7, #0] 8010766: 685b ldr r3, [r3, #4] 8010768: 68fa ldr r2, [r7, #12] 801076a: 4313 orrs r3, r2 801076c: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 801076e: 687b ldr r3, [r7, #4] 8010770: 4a35 ldr r2, [pc, #212] @ (8010848 ) 8010772: 4293 cmp r3, r2 8010774: d01f beq.n 80107b6 8010776: 687b ldr r3, [r7, #4] 8010778: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 801077c: d01b beq.n 80107b6 801077e: 687b ldr r3, [r7, #4] 8010780: 4a32 ldr r2, [pc, #200] @ (801084c ) 8010782: 4293 cmp r3, r2 8010784: d017 beq.n 80107b6 8010786: 687b ldr r3, [r7, #4] 8010788: 4a31 ldr r2, [pc, #196] @ (8010850 ) 801078a: 4293 cmp r3, r2 801078c: d013 beq.n 80107b6 801078e: 687b ldr r3, [r7, #4] 8010790: 4a30 ldr r2, [pc, #192] @ (8010854 ) 8010792: 4293 cmp r3, r2 8010794: d00f beq.n 80107b6 8010796: 687b ldr r3, [r7, #4] 8010798: 4a2f ldr r2, [pc, #188] @ (8010858 ) 801079a: 4293 cmp r3, r2 801079c: d00b beq.n 80107b6 801079e: 687b ldr r3, [r7, #4] 80107a0: 4a2e ldr r2, [pc, #184] @ (801085c ) 80107a2: 4293 cmp r3, r2 80107a4: d007 beq.n 80107b6 80107a6: 687b ldr r3, [r7, #4] 80107a8: 4a2d ldr r2, [pc, #180] @ (8010860 ) 80107aa: 4293 cmp r3, r2 80107ac: d003 beq.n 80107b6 80107ae: 687b ldr r3, [r7, #4] 80107b0: 4a2c ldr r2, [pc, #176] @ (8010864 ) 80107b2: 4293 cmp r3, r2 80107b4: d108 bne.n 80107c8 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 80107b6: 68fb ldr r3, [r7, #12] 80107b8: f423 7340 bic.w r3, r3, #768 @ 0x300 80107bc: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80107be: 683b ldr r3, [r7, #0] 80107c0: 68db ldr r3, [r3, #12] 80107c2: 68fa ldr r2, [r7, #12] 80107c4: 4313 orrs r3, r2 80107c6: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80107c8: 68fb ldr r3, [r7, #12] 80107ca: f023 0280 bic.w r2, r3, #128 @ 0x80 80107ce: 683b ldr r3, [r7, #0] 80107d0: 695b ldr r3, [r3, #20] 80107d2: 4313 orrs r3, r2 80107d4: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 80107d6: 687b ldr r3, [r7, #4] 80107d8: 68fa ldr r2, [r7, #12] 80107da: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 80107dc: 683b ldr r3, [r7, #0] 80107de: 689a ldr r2, [r3, #8] 80107e0: 687b ldr r3, [r7, #4] 80107e2: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 80107e4: 683b ldr r3, [r7, #0] 80107e6: 681a ldr r2, [r3, #0] 80107e8: 687b ldr r3, [r7, #4] 80107ea: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80107ec: 687b ldr r3, [r7, #4] 80107ee: 4a16 ldr r2, [pc, #88] @ (8010848 ) 80107f0: 4293 cmp r3, r2 80107f2: d00f beq.n 8010814 80107f4: 687b ldr r3, [r7, #4] 80107f6: 4a18 ldr r2, [pc, #96] @ (8010858 ) 80107f8: 4293 cmp r3, r2 80107fa: d00b beq.n 8010814 80107fc: 687b ldr r3, [r7, #4] 80107fe: 4a17 ldr r2, [pc, #92] @ (801085c ) 8010800: 4293 cmp r3, r2 8010802: d007 beq.n 8010814 8010804: 687b ldr r3, [r7, #4] 8010806: 4a16 ldr r2, [pc, #88] @ (8010860 ) 8010808: 4293 cmp r3, r2 801080a: d003 beq.n 8010814 801080c: 687b ldr r3, [r7, #4] 801080e: 4a15 ldr r2, [pc, #84] @ (8010864 ) 8010810: 4293 cmp r3, r2 8010812: d103 bne.n 801081c { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8010814: 683b ldr r3, [r7, #0] 8010816: 691a ldr r2, [r3, #16] 8010818: 687b ldr r3, [r7, #4] 801081a: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 801081c: 687b ldr r3, [r7, #4] 801081e: 2201 movs r2, #1 8010820: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 8010822: 687b ldr r3, [r7, #4] 8010824: 691b ldr r3, [r3, #16] 8010826: f003 0301 and.w r3, r3, #1 801082a: 2b01 cmp r3, #1 801082c: d105 bne.n 801083a { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 801082e: 687b ldr r3, [r7, #4] 8010830: 691b ldr r3, [r3, #16] 8010832: f023 0201 bic.w r2, r3, #1 8010836: 687b ldr r3, [r7, #4] 8010838: 611a str r2, [r3, #16] } } 801083a: bf00 nop 801083c: 3714 adds r7, #20 801083e: 46bd mov sp, r7 8010840: f85d 7b04 ldr.w r7, [sp], #4 8010844: 4770 bx lr 8010846: bf00 nop 8010848: 40010000 .word 0x40010000 801084c: 40000400 .word 0x40000400 8010850: 40000800 .word 0x40000800 8010854: 40000c00 .word 0x40000c00 8010858: 40010400 .word 0x40010400 801085c: 40014000 .word 0x40014000 8010860: 40014400 .word 0x40014400 8010864: 40014800 .word 0x40014800 08010868 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010868: b480 push {r7} 801086a: b087 sub sp, #28 801086c: af00 add r7, sp, #0 801086e: 6078 str r0, [r7, #4] 8010870: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010872: 687b ldr r3, [r7, #4] 8010874: 6a1b ldr r3, [r3, #32] 8010876: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 8010878: 687b ldr r3, [r7, #4] 801087a: 6a1b ldr r3, [r3, #32] 801087c: f023 0201 bic.w r2, r3, #1 8010880: 687b ldr r3, [r7, #4] 8010882: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010884: 687b ldr r3, [r7, #4] 8010886: 685b ldr r3, [r3, #4] 8010888: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 801088a: 687b ldr r3, [r7, #4] 801088c: 699b ldr r3, [r3, #24] 801088e: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 8010890: 68fa ldr r2, [r7, #12] 8010892: 4b37 ldr r3, [pc, #220] @ (8010970 ) 8010894: 4013 ands r3, r2 8010896: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 8010898: 68fb ldr r3, [r7, #12] 801089a: f023 0303 bic.w r3, r3, #3 801089e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80108a0: 683b ldr r3, [r7, #0] 80108a2: 681b ldr r3, [r3, #0] 80108a4: 68fa ldr r2, [r7, #12] 80108a6: 4313 orrs r3, r2 80108a8: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 80108aa: 697b ldr r3, [r7, #20] 80108ac: f023 0302 bic.w r3, r3, #2 80108b0: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 80108b2: 683b ldr r3, [r7, #0] 80108b4: 689b ldr r3, [r3, #8] 80108b6: 697a ldr r2, [r7, #20] 80108b8: 4313 orrs r3, r2 80108ba: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 80108bc: 687b ldr r3, [r7, #4] 80108be: 4a2d ldr r2, [pc, #180] @ (8010974 ) 80108c0: 4293 cmp r3, r2 80108c2: d00f beq.n 80108e4 80108c4: 687b ldr r3, [r7, #4] 80108c6: 4a2c ldr r2, [pc, #176] @ (8010978 ) 80108c8: 4293 cmp r3, r2 80108ca: d00b beq.n 80108e4 80108cc: 687b ldr r3, [r7, #4] 80108ce: 4a2b ldr r2, [pc, #172] @ (801097c ) 80108d0: 4293 cmp r3, r2 80108d2: d007 beq.n 80108e4 80108d4: 687b ldr r3, [r7, #4] 80108d6: 4a2a ldr r2, [pc, #168] @ (8010980 ) 80108d8: 4293 cmp r3, r2 80108da: d003 beq.n 80108e4 80108dc: 687b ldr r3, [r7, #4] 80108de: 4a29 ldr r2, [pc, #164] @ (8010984 ) 80108e0: 4293 cmp r3, r2 80108e2: d10c bne.n 80108fe { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 80108e4: 697b ldr r3, [r7, #20] 80108e6: f023 0308 bic.w r3, r3, #8 80108ea: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 80108ec: 683b ldr r3, [r7, #0] 80108ee: 68db ldr r3, [r3, #12] 80108f0: 697a ldr r2, [r7, #20] 80108f2: 4313 orrs r3, r2 80108f4: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 80108f6: 697b ldr r3, [r7, #20] 80108f8: f023 0304 bic.w r3, r3, #4 80108fc: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80108fe: 687b ldr r3, [r7, #4] 8010900: 4a1c ldr r2, [pc, #112] @ (8010974 ) 8010902: 4293 cmp r3, r2 8010904: d00f beq.n 8010926 8010906: 687b ldr r3, [r7, #4] 8010908: 4a1b ldr r2, [pc, #108] @ (8010978 ) 801090a: 4293 cmp r3, r2 801090c: d00b beq.n 8010926 801090e: 687b ldr r3, [r7, #4] 8010910: 4a1a ldr r2, [pc, #104] @ (801097c ) 8010912: 4293 cmp r3, r2 8010914: d007 beq.n 8010926 8010916: 687b ldr r3, [r7, #4] 8010918: 4a19 ldr r2, [pc, #100] @ (8010980 ) 801091a: 4293 cmp r3, r2 801091c: d003 beq.n 8010926 801091e: 687b ldr r3, [r7, #4] 8010920: 4a18 ldr r2, [pc, #96] @ (8010984 ) 8010922: 4293 cmp r3, r2 8010924: d111 bne.n 801094a /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 8010926: 693b ldr r3, [r7, #16] 8010928: f423 7380 bic.w r3, r3, #256 @ 0x100 801092c: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 801092e: 693b ldr r3, [r7, #16] 8010930: f423 7300 bic.w r3, r3, #512 @ 0x200 8010934: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8010936: 683b ldr r3, [r7, #0] 8010938: 695b ldr r3, [r3, #20] 801093a: 693a ldr r2, [r7, #16] 801093c: 4313 orrs r3, r2 801093e: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8010940: 683b ldr r3, [r7, #0] 8010942: 699b ldr r3, [r3, #24] 8010944: 693a ldr r2, [r7, #16] 8010946: 4313 orrs r3, r2 8010948: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 801094a: 687b ldr r3, [r7, #4] 801094c: 693a ldr r2, [r7, #16] 801094e: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8010950: 687b ldr r3, [r7, #4] 8010952: 68fa ldr r2, [r7, #12] 8010954: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 8010956: 683b ldr r3, [r7, #0] 8010958: 685a ldr r2, [r3, #4] 801095a: 687b ldr r3, [r7, #4] 801095c: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 801095e: 687b ldr r3, [r7, #4] 8010960: 697a ldr r2, [r7, #20] 8010962: 621a str r2, [r3, #32] } 8010964: bf00 nop 8010966: 371c adds r7, #28 8010968: 46bd mov sp, r7 801096a: f85d 7b04 ldr.w r7, [sp], #4 801096e: 4770 bx lr 8010970: fffeff8f .word 0xfffeff8f 8010974: 40010000 .word 0x40010000 8010978: 40010400 .word 0x40010400 801097c: 40014000 .word 0x40014000 8010980: 40014400 .word 0x40014400 8010984: 40014800 .word 0x40014800 08010988 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010988: b480 push {r7} 801098a: b087 sub sp, #28 801098c: af00 add r7, sp, #0 801098e: 6078 str r0, [r7, #4] 8010990: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010992: 687b ldr r3, [r7, #4] 8010994: 6a1b ldr r3, [r3, #32] 8010996: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8010998: 687b ldr r3, [r7, #4] 801099a: 6a1b ldr r3, [r3, #32] 801099c: f023 0210 bic.w r2, r3, #16 80109a0: 687b ldr r3, [r7, #4] 80109a2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80109a4: 687b ldr r3, [r7, #4] 80109a6: 685b ldr r3, [r3, #4] 80109a8: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80109aa: 687b ldr r3, [r7, #4] 80109ac: 699b ldr r3, [r3, #24] 80109ae: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 80109b0: 68fa ldr r2, [r7, #12] 80109b2: 4b34 ldr r3, [pc, #208] @ (8010a84 ) 80109b4: 4013 ands r3, r2 80109b6: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 80109b8: 68fb ldr r3, [r7, #12] 80109ba: f423 7340 bic.w r3, r3, #768 @ 0x300 80109be: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80109c0: 683b ldr r3, [r7, #0] 80109c2: 681b ldr r3, [r3, #0] 80109c4: 021b lsls r3, r3, #8 80109c6: 68fa ldr r2, [r7, #12] 80109c8: 4313 orrs r3, r2 80109ca: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 80109cc: 697b ldr r3, [r7, #20] 80109ce: f023 0320 bic.w r3, r3, #32 80109d2: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 80109d4: 683b ldr r3, [r7, #0] 80109d6: 689b ldr r3, [r3, #8] 80109d8: 011b lsls r3, r3, #4 80109da: 697a ldr r2, [r7, #20] 80109dc: 4313 orrs r3, r2 80109de: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 80109e0: 687b ldr r3, [r7, #4] 80109e2: 4a29 ldr r2, [pc, #164] @ (8010a88 ) 80109e4: 4293 cmp r3, r2 80109e6: d003 beq.n 80109f0 80109e8: 687b ldr r3, [r7, #4] 80109ea: 4a28 ldr r2, [pc, #160] @ (8010a8c ) 80109ec: 4293 cmp r3, r2 80109ee: d10d bne.n 8010a0c { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 80109f0: 697b ldr r3, [r7, #20] 80109f2: f023 0380 bic.w r3, r3, #128 @ 0x80 80109f6: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 80109f8: 683b ldr r3, [r7, #0] 80109fa: 68db ldr r3, [r3, #12] 80109fc: 011b lsls r3, r3, #4 80109fe: 697a ldr r2, [r7, #20] 8010a00: 4313 orrs r3, r2 8010a02: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8010a04: 697b ldr r3, [r7, #20] 8010a06: f023 0340 bic.w r3, r3, #64 @ 0x40 8010a0a: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010a0c: 687b ldr r3, [r7, #4] 8010a0e: 4a1e ldr r2, [pc, #120] @ (8010a88 ) 8010a10: 4293 cmp r3, r2 8010a12: d00f beq.n 8010a34 8010a14: 687b ldr r3, [r7, #4] 8010a16: 4a1d ldr r2, [pc, #116] @ (8010a8c ) 8010a18: 4293 cmp r3, r2 8010a1a: d00b beq.n 8010a34 8010a1c: 687b ldr r3, [r7, #4] 8010a1e: 4a1c ldr r2, [pc, #112] @ (8010a90 ) 8010a20: 4293 cmp r3, r2 8010a22: d007 beq.n 8010a34 8010a24: 687b ldr r3, [r7, #4] 8010a26: 4a1b ldr r2, [pc, #108] @ (8010a94 ) 8010a28: 4293 cmp r3, r2 8010a2a: d003 beq.n 8010a34 8010a2c: 687b ldr r3, [r7, #4] 8010a2e: 4a1a ldr r2, [pc, #104] @ (8010a98 ) 8010a30: 4293 cmp r3, r2 8010a32: d113 bne.n 8010a5c /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8010a34: 693b ldr r3, [r7, #16] 8010a36: f423 6380 bic.w r3, r3, #1024 @ 0x400 8010a3a: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8010a3c: 693b ldr r3, [r7, #16] 8010a3e: f423 6300 bic.w r3, r3, #2048 @ 0x800 8010a42: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8010a44: 683b ldr r3, [r7, #0] 8010a46: 695b ldr r3, [r3, #20] 8010a48: 009b lsls r3, r3, #2 8010a4a: 693a ldr r2, [r7, #16] 8010a4c: 4313 orrs r3, r2 8010a4e: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8010a50: 683b ldr r3, [r7, #0] 8010a52: 699b ldr r3, [r3, #24] 8010a54: 009b lsls r3, r3, #2 8010a56: 693a ldr r2, [r7, #16] 8010a58: 4313 orrs r3, r2 8010a5a: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010a5c: 687b ldr r3, [r7, #4] 8010a5e: 693a ldr r2, [r7, #16] 8010a60: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8010a62: 687b ldr r3, [r7, #4] 8010a64: 68fa ldr r2, [r7, #12] 8010a66: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8010a68: 683b ldr r3, [r7, #0] 8010a6a: 685a ldr r2, [r3, #4] 8010a6c: 687b ldr r3, [r7, #4] 8010a6e: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010a70: 687b ldr r3, [r7, #4] 8010a72: 697a ldr r2, [r7, #20] 8010a74: 621a str r2, [r3, #32] } 8010a76: bf00 nop 8010a78: 371c adds r7, #28 8010a7a: 46bd mov sp, r7 8010a7c: f85d 7b04 ldr.w r7, [sp], #4 8010a80: 4770 bx lr 8010a82: bf00 nop 8010a84: feff8fff .word 0xfeff8fff 8010a88: 40010000 .word 0x40010000 8010a8c: 40010400 .word 0x40010400 8010a90: 40014000 .word 0x40014000 8010a94: 40014400 .word 0x40014400 8010a98: 40014800 .word 0x40014800 08010a9c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010a9c: b480 push {r7} 8010a9e: b087 sub sp, #28 8010aa0: af00 add r7, sp, #0 8010aa2: 6078 str r0, [r7, #4] 8010aa4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010aa6: 687b ldr r3, [r7, #4] 8010aa8: 6a1b ldr r3, [r3, #32] 8010aaa: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8010aac: 687b ldr r3, [r7, #4] 8010aae: 6a1b ldr r3, [r3, #32] 8010ab0: f423 7280 bic.w r2, r3, #256 @ 0x100 8010ab4: 687b ldr r3, [r7, #4] 8010ab6: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010ab8: 687b ldr r3, [r7, #4] 8010aba: 685b ldr r3, [r3, #4] 8010abc: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8010abe: 687b ldr r3, [r7, #4] 8010ac0: 69db ldr r3, [r3, #28] 8010ac2: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8010ac4: 68fa ldr r2, [r7, #12] 8010ac6: 4b33 ldr r3, [pc, #204] @ (8010b94 ) 8010ac8: 4013 ands r3, r2 8010aca: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8010acc: 68fb ldr r3, [r7, #12] 8010ace: f023 0303 bic.w r3, r3, #3 8010ad2: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8010ad4: 683b ldr r3, [r7, #0] 8010ad6: 681b ldr r3, [r3, #0] 8010ad8: 68fa ldr r2, [r7, #12] 8010ada: 4313 orrs r3, r2 8010adc: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8010ade: 697b ldr r3, [r7, #20] 8010ae0: f423 7300 bic.w r3, r3, #512 @ 0x200 8010ae4: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 8010ae6: 683b ldr r3, [r7, #0] 8010ae8: 689b ldr r3, [r3, #8] 8010aea: 021b lsls r3, r3, #8 8010aec: 697a ldr r2, [r7, #20] 8010aee: 4313 orrs r3, r2 8010af0: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8010af2: 687b ldr r3, [r7, #4] 8010af4: 4a28 ldr r2, [pc, #160] @ (8010b98 ) 8010af6: 4293 cmp r3, r2 8010af8: d003 beq.n 8010b02 8010afa: 687b ldr r3, [r7, #4] 8010afc: 4a27 ldr r2, [pc, #156] @ (8010b9c ) 8010afe: 4293 cmp r3, r2 8010b00: d10d bne.n 8010b1e { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8010b02: 697b ldr r3, [r7, #20] 8010b04: f423 6300 bic.w r3, r3, #2048 @ 0x800 8010b08: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 8010b0a: 683b ldr r3, [r7, #0] 8010b0c: 68db ldr r3, [r3, #12] 8010b0e: 021b lsls r3, r3, #8 8010b10: 697a ldr r2, [r7, #20] 8010b12: 4313 orrs r3, r2 8010b14: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8010b16: 697b ldr r3, [r7, #20] 8010b18: f423 6380 bic.w r3, r3, #1024 @ 0x400 8010b1c: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010b1e: 687b ldr r3, [r7, #4] 8010b20: 4a1d ldr r2, [pc, #116] @ (8010b98 ) 8010b22: 4293 cmp r3, r2 8010b24: d00f beq.n 8010b46 8010b26: 687b ldr r3, [r7, #4] 8010b28: 4a1c ldr r2, [pc, #112] @ (8010b9c ) 8010b2a: 4293 cmp r3, r2 8010b2c: d00b beq.n 8010b46 8010b2e: 687b ldr r3, [r7, #4] 8010b30: 4a1b ldr r2, [pc, #108] @ (8010ba0 ) 8010b32: 4293 cmp r3, r2 8010b34: d007 beq.n 8010b46 8010b36: 687b ldr r3, [r7, #4] 8010b38: 4a1a ldr r2, [pc, #104] @ (8010ba4 ) 8010b3a: 4293 cmp r3, r2 8010b3c: d003 beq.n 8010b46 8010b3e: 687b ldr r3, [r7, #4] 8010b40: 4a19 ldr r2, [pc, #100] @ (8010ba8 ) 8010b42: 4293 cmp r3, r2 8010b44: d113 bne.n 8010b6e /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8010b46: 693b ldr r3, [r7, #16] 8010b48: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8010b4c: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8010b4e: 693b ldr r3, [r7, #16] 8010b50: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8010b54: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8010b56: 683b ldr r3, [r7, #0] 8010b58: 695b ldr r3, [r3, #20] 8010b5a: 011b lsls r3, r3, #4 8010b5c: 693a ldr r2, [r7, #16] 8010b5e: 4313 orrs r3, r2 8010b60: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 8010b62: 683b ldr r3, [r7, #0] 8010b64: 699b ldr r3, [r3, #24] 8010b66: 011b lsls r3, r3, #4 8010b68: 693a ldr r2, [r7, #16] 8010b6a: 4313 orrs r3, r2 8010b6c: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010b6e: 687b ldr r3, [r7, #4] 8010b70: 693a ldr r2, [r7, #16] 8010b72: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8010b74: 687b ldr r3, [r7, #4] 8010b76: 68fa ldr r2, [r7, #12] 8010b78: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8010b7a: 683b ldr r3, [r7, #0] 8010b7c: 685a ldr r2, [r3, #4] 8010b7e: 687b ldr r3, [r7, #4] 8010b80: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010b82: 687b ldr r3, [r7, #4] 8010b84: 697a ldr r2, [r7, #20] 8010b86: 621a str r2, [r3, #32] } 8010b88: bf00 nop 8010b8a: 371c adds r7, #28 8010b8c: 46bd mov sp, r7 8010b8e: f85d 7b04 ldr.w r7, [sp], #4 8010b92: 4770 bx lr 8010b94: fffeff8f .word 0xfffeff8f 8010b98: 40010000 .word 0x40010000 8010b9c: 40010400 .word 0x40010400 8010ba0: 40014000 .word 0x40014000 8010ba4: 40014400 .word 0x40014400 8010ba8: 40014800 .word 0x40014800 08010bac : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010bac: b480 push {r7} 8010bae: b087 sub sp, #28 8010bb0: af00 add r7, sp, #0 8010bb2: 6078 str r0, [r7, #4] 8010bb4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010bb6: 687b ldr r3, [r7, #4] 8010bb8: 6a1b ldr r3, [r3, #32] 8010bba: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8010bbc: 687b ldr r3, [r7, #4] 8010bbe: 6a1b ldr r3, [r3, #32] 8010bc0: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8010bc4: 687b ldr r3, [r7, #4] 8010bc6: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010bc8: 687b ldr r3, [r7, #4] 8010bca: 685b ldr r3, [r3, #4] 8010bcc: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8010bce: 687b ldr r3, [r7, #4] 8010bd0: 69db ldr r3, [r3, #28] 8010bd2: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8010bd4: 68fa ldr r2, [r7, #12] 8010bd6: 4b24 ldr r3, [pc, #144] @ (8010c68 ) 8010bd8: 4013 ands r3, r2 8010bda: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8010bdc: 68fb ldr r3, [r7, #12] 8010bde: f423 7340 bic.w r3, r3, #768 @ 0x300 8010be2: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8010be4: 683b ldr r3, [r7, #0] 8010be6: 681b ldr r3, [r3, #0] 8010be8: 021b lsls r3, r3, #8 8010bea: 68fa ldr r2, [r7, #12] 8010bec: 4313 orrs r3, r2 8010bee: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8010bf0: 693b ldr r3, [r7, #16] 8010bf2: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8010bf6: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8010bf8: 683b ldr r3, [r7, #0] 8010bfa: 689b ldr r3, [r3, #8] 8010bfc: 031b lsls r3, r3, #12 8010bfe: 693a ldr r2, [r7, #16] 8010c00: 4313 orrs r3, r2 8010c02: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010c04: 687b ldr r3, [r7, #4] 8010c06: 4a19 ldr r2, [pc, #100] @ (8010c6c ) 8010c08: 4293 cmp r3, r2 8010c0a: d00f beq.n 8010c2c 8010c0c: 687b ldr r3, [r7, #4] 8010c0e: 4a18 ldr r2, [pc, #96] @ (8010c70 ) 8010c10: 4293 cmp r3, r2 8010c12: d00b beq.n 8010c2c 8010c14: 687b ldr r3, [r7, #4] 8010c16: 4a17 ldr r2, [pc, #92] @ (8010c74 ) 8010c18: 4293 cmp r3, r2 8010c1a: d007 beq.n 8010c2c 8010c1c: 687b ldr r3, [r7, #4] 8010c1e: 4a16 ldr r2, [pc, #88] @ (8010c78 ) 8010c20: 4293 cmp r3, r2 8010c22: d003 beq.n 8010c2c 8010c24: 687b ldr r3, [r7, #4] 8010c26: 4a15 ldr r2, [pc, #84] @ (8010c7c ) 8010c28: 4293 cmp r3, r2 8010c2a: d109 bne.n 8010c40 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8010c2c: 697b ldr r3, [r7, #20] 8010c2e: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8010c32: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8010c34: 683b ldr r3, [r7, #0] 8010c36: 695b ldr r3, [r3, #20] 8010c38: 019b lsls r3, r3, #6 8010c3a: 697a ldr r2, [r7, #20] 8010c3c: 4313 orrs r3, r2 8010c3e: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010c40: 687b ldr r3, [r7, #4] 8010c42: 697a ldr r2, [r7, #20] 8010c44: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8010c46: 687b ldr r3, [r7, #4] 8010c48: 68fa ldr r2, [r7, #12] 8010c4a: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8010c4c: 683b ldr r3, [r7, #0] 8010c4e: 685a ldr r2, [r3, #4] 8010c50: 687b ldr r3, [r7, #4] 8010c52: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010c54: 687b ldr r3, [r7, #4] 8010c56: 693a ldr r2, [r7, #16] 8010c58: 621a str r2, [r3, #32] } 8010c5a: bf00 nop 8010c5c: 371c adds r7, #28 8010c5e: 46bd mov sp, r7 8010c60: f85d 7b04 ldr.w r7, [sp], #4 8010c64: 4770 bx lr 8010c66: bf00 nop 8010c68: feff8fff .word 0xfeff8fff 8010c6c: 40010000 .word 0x40010000 8010c70: 40010400 .word 0x40010400 8010c74: 40014000 .word 0x40014000 8010c78: 40014400 .word 0x40014400 8010c7c: 40014800 .word 0x40014800 08010c80 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010c80: b480 push {r7} 8010c82: b087 sub sp, #28 8010c84: af00 add r7, sp, #0 8010c86: 6078 str r0, [r7, #4] 8010c88: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010c8a: 687b ldr r3, [r7, #4] 8010c8c: 6a1b ldr r3, [r3, #32] 8010c8e: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; 8010c90: 687b ldr r3, [r7, #4] 8010c92: 6a1b ldr r3, [r3, #32] 8010c94: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8010c98: 687b ldr r3, [r7, #4] 8010c9a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010c9c: 687b ldr r3, [r7, #4] 8010c9e: 685b ldr r3, [r3, #4] 8010ca0: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 8010ca2: 687b ldr r3, [r7, #4] 8010ca4: 6d5b ldr r3, [r3, #84] @ 0x54 8010ca6: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); 8010ca8: 68fa ldr r2, [r7, #12] 8010caa: 4b21 ldr r3, [pc, #132] @ (8010d30 ) 8010cac: 4013 ands r3, r2 8010cae: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8010cb0: 683b ldr r3, [r7, #0] 8010cb2: 681b ldr r3, [r3, #0] 8010cb4: 68fa ldr r2, [r7, #12] 8010cb6: 4313 orrs r3, r2 8010cb8: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; 8010cba: 693b ldr r3, [r7, #16] 8010cbc: f423 3300 bic.w r3, r3, #131072 @ 0x20000 8010cc0: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); 8010cc2: 683b ldr r3, [r7, #0] 8010cc4: 689b ldr r3, [r3, #8] 8010cc6: 041b lsls r3, r3, #16 8010cc8: 693a ldr r2, [r7, #16] 8010cca: 4313 orrs r3, r2 8010ccc: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010cce: 687b ldr r3, [r7, #4] 8010cd0: 4a18 ldr r2, [pc, #96] @ (8010d34 ) 8010cd2: 4293 cmp r3, r2 8010cd4: d00f beq.n 8010cf6 8010cd6: 687b ldr r3, [r7, #4] 8010cd8: 4a17 ldr r2, [pc, #92] @ (8010d38 ) 8010cda: 4293 cmp r3, r2 8010cdc: d00b beq.n 8010cf6 8010cde: 687b ldr r3, [r7, #4] 8010ce0: 4a16 ldr r2, [pc, #88] @ (8010d3c ) 8010ce2: 4293 cmp r3, r2 8010ce4: d007 beq.n 8010cf6 8010ce6: 687b ldr r3, [r7, #4] 8010ce8: 4a15 ldr r2, [pc, #84] @ (8010d40 ) 8010cea: 4293 cmp r3, r2 8010cec: d003 beq.n 8010cf6 8010cee: 687b ldr r3, [r7, #4] 8010cf0: 4a14 ldr r2, [pc, #80] @ (8010d44 ) 8010cf2: 4293 cmp r3, r2 8010cf4: d109 bne.n 8010d0a { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; 8010cf6: 697b ldr r3, [r7, #20] 8010cf8: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8010cfc: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); 8010cfe: 683b ldr r3, [r7, #0] 8010d00: 695b ldr r3, [r3, #20] 8010d02: 021b lsls r3, r3, #8 8010d04: 697a ldr r2, [r7, #20] 8010d06: 4313 orrs r3, r2 8010d08: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010d0a: 687b ldr r3, [r7, #4] 8010d0c: 697a ldr r2, [r7, #20] 8010d0e: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 8010d10: 687b ldr r3, [r7, #4] 8010d12: 68fa ldr r2, [r7, #12] 8010d14: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; 8010d16: 683b ldr r3, [r7, #0] 8010d18: 685a ldr r2, [r3, #4] 8010d1a: 687b ldr r3, [r7, #4] 8010d1c: 659a str r2, [r3, #88] @ 0x58 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010d1e: 687b ldr r3, [r7, #4] 8010d20: 693a ldr r2, [r7, #16] 8010d22: 621a str r2, [r3, #32] } 8010d24: bf00 nop 8010d26: 371c adds r7, #28 8010d28: 46bd mov sp, r7 8010d2a: f85d 7b04 ldr.w r7, [sp], #4 8010d2e: 4770 bx lr 8010d30: fffeff8f .word 0xfffeff8f 8010d34: 40010000 .word 0x40010000 8010d38: 40010400 .word 0x40010400 8010d3c: 40014000 .word 0x40014000 8010d40: 40014400 .word 0x40014400 8010d44: 40014800 .word 0x40014800 08010d48 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010d48: b480 push {r7} 8010d4a: b087 sub sp, #28 8010d4c: af00 add r7, sp, #0 8010d4e: 6078 str r0, [r7, #4] 8010d50: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010d52: 687b ldr r3, [r7, #4] 8010d54: 6a1b ldr r3, [r3, #32] 8010d56: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; 8010d58: 687b ldr r3, [r7, #4] 8010d5a: 6a1b ldr r3, [r3, #32] 8010d5c: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 8010d60: 687b ldr r3, [r7, #4] 8010d62: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010d64: 687b ldr r3, [r7, #4] 8010d66: 685b ldr r3, [r3, #4] 8010d68: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 8010d6a: 687b ldr r3, [r7, #4] 8010d6c: 6d5b ldr r3, [r3, #84] @ 0x54 8010d6e: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); 8010d70: 68fa ldr r2, [r7, #12] 8010d72: 4b22 ldr r3, [pc, #136] @ (8010dfc ) 8010d74: 4013 ands r3, r2 8010d76: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8010d78: 683b ldr r3, [r7, #0] 8010d7a: 681b ldr r3, [r3, #0] 8010d7c: 021b lsls r3, r3, #8 8010d7e: 68fa ldr r2, [r7, #12] 8010d80: 4313 orrs r3, r2 8010d82: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; 8010d84: 693b ldr r3, [r7, #16] 8010d86: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8010d8a: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); 8010d8c: 683b ldr r3, [r7, #0] 8010d8e: 689b ldr r3, [r3, #8] 8010d90: 051b lsls r3, r3, #20 8010d92: 693a ldr r2, [r7, #16] 8010d94: 4313 orrs r3, r2 8010d96: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010d98: 687b ldr r3, [r7, #4] 8010d9a: 4a19 ldr r2, [pc, #100] @ (8010e00 ) 8010d9c: 4293 cmp r3, r2 8010d9e: d00f beq.n 8010dc0 8010da0: 687b ldr r3, [r7, #4] 8010da2: 4a18 ldr r2, [pc, #96] @ (8010e04 ) 8010da4: 4293 cmp r3, r2 8010da6: d00b beq.n 8010dc0 8010da8: 687b ldr r3, [r7, #4] 8010daa: 4a17 ldr r2, [pc, #92] @ (8010e08 ) 8010dac: 4293 cmp r3, r2 8010dae: d007 beq.n 8010dc0 8010db0: 687b ldr r3, [r7, #4] 8010db2: 4a16 ldr r2, [pc, #88] @ (8010e0c ) 8010db4: 4293 cmp r3, r2 8010db6: d003 beq.n 8010dc0 8010db8: 687b ldr r3, [r7, #4] 8010dba: 4a15 ldr r2, [pc, #84] @ (8010e10 ) 8010dbc: 4293 cmp r3, r2 8010dbe: d109 bne.n 8010dd4 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; 8010dc0: 697b ldr r3, [r7, #20] 8010dc2: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010dc6: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); 8010dc8: 683b ldr r3, [r7, #0] 8010dca: 695b ldr r3, [r3, #20] 8010dcc: 029b lsls r3, r3, #10 8010dce: 697a ldr r2, [r7, #20] 8010dd0: 4313 orrs r3, r2 8010dd2: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010dd4: 687b ldr r3, [r7, #4] 8010dd6: 697a ldr r2, [r7, #20] 8010dd8: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 8010dda: 687b ldr r3, [r7, #4] 8010ddc: 68fa ldr r2, [r7, #12] 8010dde: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; 8010de0: 683b ldr r3, [r7, #0] 8010de2: 685a ldr r2, [r3, #4] 8010de4: 687b ldr r3, [r7, #4] 8010de6: 65da str r2, [r3, #92] @ 0x5c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010de8: 687b ldr r3, [r7, #4] 8010dea: 693a ldr r2, [r7, #16] 8010dec: 621a str r2, [r3, #32] } 8010dee: bf00 nop 8010df0: 371c adds r7, #28 8010df2: 46bd mov sp, r7 8010df4: f85d 7b04 ldr.w r7, [sp], #4 8010df8: 4770 bx lr 8010dfa: bf00 nop 8010dfc: feff8fff .word 0xfeff8fff 8010e00: 40010000 .word 0x40010000 8010e04: 40010400 .word 0x40010400 8010e08: 40014000 .word 0x40014000 8010e0c: 40014400 .word 0x40014400 8010e10: 40014800 .word 0x40014800 08010e14 : * (on channel2 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 8010e14: b480 push {r7} 8010e16: b087 sub sp, #28 8010e18: af00 add r7, sp, #0 8010e1a: 60f8 str r0, [r7, #12] 8010e1c: 60b9 str r1, [r7, #8] 8010e1e: 607a str r2, [r7, #4] 8010e20: 603b str r3, [r7, #0] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8010e22: 68fb ldr r3, [r7, #12] 8010e24: 6a1b ldr r3, [r3, #32] 8010e26: 613b str r3, [r7, #16] TIMx->CCER &= ~TIM_CCER_CC1E; 8010e28: 68fb ldr r3, [r7, #12] 8010e2a: 6a1b ldr r3, [r3, #32] 8010e2c: f023 0201 bic.w r2, r3, #1 8010e30: 68fb ldr r3, [r7, #12] 8010e32: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010e34: 68fb ldr r3, [r7, #12] 8010e36: 699b ldr r3, [r3, #24] 8010e38: 617b str r3, [r7, #20] /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) 8010e3a: 68fb ldr r3, [r7, #12] 8010e3c: 4a28 ldr r2, [pc, #160] @ (8010ee0 ) 8010e3e: 4293 cmp r3, r2 8010e40: d01b beq.n 8010e7a 8010e42: 68fb ldr r3, [r7, #12] 8010e44: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8010e48: d017 beq.n 8010e7a 8010e4a: 68fb ldr r3, [r7, #12] 8010e4c: 4a25 ldr r2, [pc, #148] @ (8010ee4 ) 8010e4e: 4293 cmp r3, r2 8010e50: d013 beq.n 8010e7a 8010e52: 68fb ldr r3, [r7, #12] 8010e54: 4a24 ldr r2, [pc, #144] @ (8010ee8 ) 8010e56: 4293 cmp r3, r2 8010e58: d00f beq.n 8010e7a 8010e5a: 68fb ldr r3, [r7, #12] 8010e5c: 4a23 ldr r2, [pc, #140] @ (8010eec ) 8010e5e: 4293 cmp r3, r2 8010e60: d00b beq.n 8010e7a 8010e62: 68fb ldr r3, [r7, #12] 8010e64: 4a22 ldr r2, [pc, #136] @ (8010ef0 ) 8010e66: 4293 cmp r3, r2 8010e68: d007 beq.n 8010e7a 8010e6a: 68fb ldr r3, [r7, #12] 8010e6c: 4a21 ldr r2, [pc, #132] @ (8010ef4 ) 8010e6e: 4293 cmp r3, r2 8010e70: d003 beq.n 8010e7a 8010e72: 68fb ldr r3, [r7, #12] 8010e74: 4a20 ldr r2, [pc, #128] @ (8010ef8 ) 8010e76: 4293 cmp r3, r2 8010e78: d101 bne.n 8010e7e 8010e7a: 2301 movs r3, #1 8010e7c: e000 b.n 8010e80 8010e7e: 2300 movs r3, #0 8010e80: 2b00 cmp r3, #0 8010e82: d008 beq.n 8010e96 { tmpccmr1 &= ~TIM_CCMR1_CC1S; 8010e84: 697b ldr r3, [r7, #20] 8010e86: f023 0303 bic.w r3, r3, #3 8010e8a: 617b str r3, [r7, #20] tmpccmr1 |= TIM_ICSelection; 8010e8c: 697a ldr r2, [r7, #20] 8010e8e: 687b ldr r3, [r7, #4] 8010e90: 4313 orrs r3, r2 8010e92: 617b str r3, [r7, #20] 8010e94: e003 b.n 8010e9e } else { tmpccmr1 |= TIM_CCMR1_CC1S_0; 8010e96: 697b ldr r3, [r7, #20] 8010e98: f043 0301 orr.w r3, r3, #1 8010e9c: 617b str r3, [r7, #20] } /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8010e9e: 697b ldr r3, [r7, #20] 8010ea0: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8010ea4: 617b str r3, [r7, #20] tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); 8010ea6: 683b ldr r3, [r7, #0] 8010ea8: 011b lsls r3, r3, #4 8010eaa: b2db uxtb r3, r3 8010eac: 697a ldr r2, [r7, #20] 8010eae: 4313 orrs r3, r2 8010eb0: 617b str r3, [r7, #20] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8010eb2: 693b ldr r3, [r7, #16] 8010eb4: f023 030a bic.w r3, r3, #10 8010eb8: 613b str r3, [r7, #16] tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); 8010eba: 68bb ldr r3, [r7, #8] 8010ebc: f003 030a and.w r3, r3, #10 8010ec0: 693a ldr r2, [r7, #16] 8010ec2: 4313 orrs r3, r2 8010ec4: 613b str r3, [r7, #16] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8010ec6: 68fb ldr r3, [r7, #12] 8010ec8: 697a ldr r2, [r7, #20] 8010eca: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8010ecc: 68fb ldr r3, [r7, #12] 8010ece: 693a ldr r2, [r7, #16] 8010ed0: 621a str r2, [r3, #32] } 8010ed2: bf00 nop 8010ed4: 371c adds r7, #28 8010ed6: 46bd mov sp, r7 8010ed8: f85d 7b04 ldr.w r7, [sp], #4 8010edc: 4770 bx lr 8010ede: bf00 nop 8010ee0: 40010000 .word 0x40010000 8010ee4: 40000400 .word 0x40000400 8010ee8: 40000800 .word 0x40000800 8010eec: 40000c00 .word 0x40000c00 8010ef0: 40010400 .word 0x40010400 8010ef4: 40001800 .word 0x40001800 8010ef8: 40014000 .word 0x40014000 08010efc : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8010efc: b480 push {r7} 8010efe: b087 sub sp, #28 8010f00: af00 add r7, sp, #0 8010f02: 60f8 str r0, [r7, #12] 8010f04: 60b9 str r1, [r7, #8] 8010f06: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8010f08: 68fb ldr r3, [r7, #12] 8010f0a: 6a1b ldr r3, [r3, #32] 8010f0c: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8010f0e: 68fb ldr r3, [r7, #12] 8010f10: 6a1b ldr r3, [r3, #32] 8010f12: f023 0201 bic.w r2, r3, #1 8010f16: 68fb ldr r3, [r7, #12] 8010f18: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010f1a: 68fb ldr r3, [r7, #12] 8010f1c: 699b ldr r3, [r3, #24] 8010f1e: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8010f20: 693b ldr r3, [r7, #16] 8010f22: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8010f26: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8010f28: 687b ldr r3, [r7, #4] 8010f2a: 011b lsls r3, r3, #4 8010f2c: 693a ldr r2, [r7, #16] 8010f2e: 4313 orrs r3, r2 8010f30: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8010f32: 697b ldr r3, [r7, #20] 8010f34: f023 030a bic.w r3, r3, #10 8010f38: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8010f3a: 697a ldr r2, [r7, #20] 8010f3c: 68bb ldr r3, [r7, #8] 8010f3e: 4313 orrs r3, r2 8010f40: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8010f42: 68fb ldr r3, [r7, #12] 8010f44: 693a ldr r2, [r7, #16] 8010f46: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8010f48: 68fb ldr r3, [r7, #12] 8010f4a: 697a ldr r2, [r7, #20] 8010f4c: 621a str r2, [r3, #32] } 8010f4e: bf00 nop 8010f50: 371c adds r7, #28 8010f52: 46bd mov sp, r7 8010f54: f85d 7b04 ldr.w r7, [sp], #4 8010f58: 4770 bx lr 08010f5a : * (on channel1 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 8010f5a: b480 push {r7} 8010f5c: b087 sub sp, #28 8010f5e: af00 add r7, sp, #0 8010f60: 60f8 str r0, [r7, #12] 8010f62: 60b9 str r1, [r7, #8] 8010f64: 607a str r2, [r7, #4] 8010f66: 603b str r3, [r7, #0] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8010f68: 68fb ldr r3, [r7, #12] 8010f6a: 6a1b ldr r3, [r3, #32] 8010f6c: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8010f6e: 68fb ldr r3, [r7, #12] 8010f70: 6a1b ldr r3, [r3, #32] 8010f72: f023 0210 bic.w r2, r3, #16 8010f76: 68fb ldr r3, [r7, #12] 8010f78: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010f7a: 68fb ldr r3, [r7, #12] 8010f7c: 699b ldr r3, [r3, #24] 8010f7e: 613b str r3, [r7, #16] /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; 8010f80: 693b ldr r3, [r7, #16] 8010f82: f423 7340 bic.w r3, r3, #768 @ 0x300 8010f86: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICSelection << 8U); 8010f88: 687b ldr r3, [r7, #4] 8010f8a: 021b lsls r3, r3, #8 8010f8c: 693a ldr r2, [r7, #16] 8010f8e: 4313 orrs r3, r2 8010f90: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8010f92: 693b ldr r3, [r7, #16] 8010f94: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8010f98: 613b str r3, [r7, #16] tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); 8010f9a: 683b ldr r3, [r7, #0] 8010f9c: 031b lsls r3, r3, #12 8010f9e: b29b uxth r3, r3 8010fa0: 693a ldr r2, [r7, #16] 8010fa2: 4313 orrs r3, r2 8010fa4: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8010fa6: 697b ldr r3, [r7, #20] 8010fa8: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8010fac: 617b str r3, [r7, #20] tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); 8010fae: 68bb ldr r3, [r7, #8] 8010fb0: 011b lsls r3, r3, #4 8010fb2: f003 03a0 and.w r3, r3, #160 @ 0xa0 8010fb6: 697a ldr r2, [r7, #20] 8010fb8: 4313 orrs r3, r2 8010fba: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8010fbc: 68fb ldr r3, [r7, #12] 8010fbe: 693a ldr r2, [r7, #16] 8010fc0: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8010fc2: 68fb ldr r3, [r7, #12] 8010fc4: 697a ldr r2, [r7, #20] 8010fc6: 621a str r2, [r3, #32] } 8010fc8: bf00 nop 8010fca: 371c adds r7, #28 8010fcc: 46bd mov sp, r7 8010fce: f85d 7b04 ldr.w r7, [sp], #4 8010fd2: 4770 bx lr 08010fd4 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8010fd4: b480 push {r7} 8010fd6: b087 sub sp, #28 8010fd8: af00 add r7, sp, #0 8010fda: 60f8 str r0, [r7, #12] 8010fdc: 60b9 str r1, [r7, #8] 8010fde: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8010fe0: 68fb ldr r3, [r7, #12] 8010fe2: 6a1b ldr r3, [r3, #32] 8010fe4: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8010fe6: 68fb ldr r3, [r7, #12] 8010fe8: 6a1b ldr r3, [r3, #32] 8010fea: f023 0210 bic.w r2, r3, #16 8010fee: 68fb ldr r3, [r7, #12] 8010ff0: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010ff2: 68fb ldr r3, [r7, #12] 8010ff4: 699b ldr r3, [r3, #24] 8010ff6: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8010ff8: 693b ldr r3, [r7, #16] 8010ffa: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8010ffe: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8011000: 687b ldr r3, [r7, #4] 8011002: 031b lsls r3, r3, #12 8011004: 693a ldr r2, [r7, #16] 8011006: 4313 orrs r3, r2 8011008: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 801100a: 697b ldr r3, [r7, #20] 801100c: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8011010: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8011012: 68bb ldr r3, [r7, #8] 8011014: 011b lsls r3, r3, #4 8011016: 697a ldr r2, [r7, #20] 8011018: 4313 orrs r3, r2 801101a: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 801101c: 68fb ldr r3, [r7, #12] 801101e: 693a ldr r2, [r7, #16] 8011020: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8011022: 68fb ldr r3, [r7, #12] 8011024: 697a ldr r2, [r7, #20] 8011026: 621a str r2, [r3, #32] } 8011028: bf00 nop 801102a: 371c adds r7, #28 801102c: 46bd mov sp, r7 801102e: f85d 7b04 ldr.w r7, [sp], #4 8011032: 4770 bx lr 08011034 : * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 8011034: b480 push {r7} 8011036: b087 sub sp, #28 8011038: af00 add r7, sp, #0 801103a: 60f8 str r0, [r7, #12] 801103c: 60b9 str r1, [r7, #8] 801103e: 607a str r2, [r7, #4] 8011040: 603b str r3, [r7, #0] uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ tmpccer = TIMx->CCER; 8011042: 68fb ldr r3, [r7, #12] 8011044: 6a1b ldr r3, [r3, #32] 8011046: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC3E; 8011048: 68fb ldr r3, [r7, #12] 801104a: 6a1b ldr r3, [r3, #32] 801104c: f423 7280 bic.w r2, r3, #256 @ 0x100 8011050: 68fb ldr r3, [r7, #12] 8011052: 621a str r2, [r3, #32] tmpccmr2 = TIMx->CCMR2; 8011054: 68fb ldr r3, [r7, #12] 8011056: 69db ldr r3, [r3, #28] 8011058: 613b str r3, [r7, #16] /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; 801105a: 693b ldr r3, [r7, #16] 801105c: f023 0303 bic.w r3, r3, #3 8011060: 613b str r3, [r7, #16] tmpccmr2 |= TIM_ICSelection; 8011062: 693a ldr r2, [r7, #16] 8011064: 687b ldr r3, [r7, #4] 8011066: 4313 orrs r3, r2 8011068: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; 801106a: 693b ldr r3, [r7, #16] 801106c: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8011070: 613b str r3, [r7, #16] tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); 8011072: 683b ldr r3, [r7, #0] 8011074: 011b lsls r3, r3, #4 8011076: b2db uxtb r3, r3 8011078: 693a ldr r2, [r7, #16] 801107a: 4313 orrs r3, r2 801107c: 613b str r3, [r7, #16] /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); 801107e: 697b ldr r3, [r7, #20] 8011080: f423 6320 bic.w r3, r3, #2560 @ 0xa00 8011084: 617b str r3, [r7, #20] tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); 8011086: 68bb ldr r3, [r7, #8] 8011088: 021b lsls r3, r3, #8 801108a: f403 6320 and.w r3, r3, #2560 @ 0xa00 801108e: 697a ldr r2, [r7, #20] 8011090: 4313 orrs r3, r2 8011092: 617b str r3, [r7, #20] /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; 8011094: 68fb ldr r3, [r7, #12] 8011096: 693a ldr r2, [r7, #16] 8011098: 61da str r2, [r3, #28] TIMx->CCER = tmpccer; 801109a: 68fb ldr r3, [r7, #12] 801109c: 697a ldr r2, [r7, #20] 801109e: 621a str r2, [r3, #32] } 80110a0: bf00 nop 80110a2: 371c adds r7, #28 80110a4: 46bd mov sp, r7 80110a6: f85d 7b04 ldr.w r7, [sp], #4 80110aa: 4770 bx lr 080110ac : * protected against un-initialized filter and polarity values. * @retval None */ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 80110ac: b480 push {r7} 80110ae: b087 sub sp, #28 80110b0: af00 add r7, sp, #0 80110b2: 60f8 str r0, [r7, #12] 80110b4: 60b9 str r1, [r7, #8] 80110b6: 607a str r2, [r7, #4] 80110b8: 603b str r3, [r7, #0] uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ tmpccer = TIMx->CCER; 80110ba: 68fb ldr r3, [r7, #12] 80110bc: 6a1b ldr r3, [r3, #32] 80110be: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC4E; 80110c0: 68fb ldr r3, [r7, #12] 80110c2: 6a1b ldr r3, [r3, #32] 80110c4: f423 5280 bic.w r2, r3, #4096 @ 0x1000 80110c8: 68fb ldr r3, [r7, #12] 80110ca: 621a str r2, [r3, #32] tmpccmr2 = TIMx->CCMR2; 80110cc: 68fb ldr r3, [r7, #12] 80110ce: 69db ldr r3, [r3, #28] 80110d0: 613b str r3, [r7, #16] /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; 80110d2: 693b ldr r3, [r7, #16] 80110d4: f423 7340 bic.w r3, r3, #768 @ 0x300 80110d8: 613b str r3, [r7, #16] tmpccmr2 |= (TIM_ICSelection << 8U); 80110da: 687b ldr r3, [r7, #4] 80110dc: 021b lsls r3, r3, #8 80110de: 693a ldr r2, [r7, #16] 80110e0: 4313 orrs r3, r2 80110e2: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; 80110e4: 693b ldr r3, [r7, #16] 80110e6: f423 4370 bic.w r3, r3, #61440 @ 0xf000 80110ea: 613b str r3, [r7, #16] tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); 80110ec: 683b ldr r3, [r7, #0] 80110ee: 031b lsls r3, r3, #12 80110f0: b29b uxth r3, r3 80110f2: 693a ldr r2, [r7, #16] 80110f4: 4313 orrs r3, r2 80110f6: 613b str r3, [r7, #16] /* Select the Polarity and set the CC4E Bit */ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); 80110f8: 697b ldr r3, [r7, #20] 80110fa: f423 4320 bic.w r3, r3, #40960 @ 0xa000 80110fe: 617b str r3, [r7, #20] tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); 8011100: 68bb ldr r3, [r7, #8] 8011102: 031b lsls r3, r3, #12 8011104: f403 4320 and.w r3, r3, #40960 @ 0xa000 8011108: 697a ldr r2, [r7, #20] 801110a: 4313 orrs r3, r2 801110c: 617b str r3, [r7, #20] /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; 801110e: 68fb ldr r3, [r7, #12] 8011110: 693a ldr r2, [r7, #16] 8011112: 61da str r2, [r3, #28] TIMx->CCER = tmpccer ; 8011114: 68fb ldr r3, [r7, #12] 8011116: 697a ldr r2, [r7, #20] 8011118: 621a str r2, [r3, #32] } 801111a: bf00 nop 801111c: 371c adds r7, #28 801111e: 46bd mov sp, r7 8011120: f85d 7b04 ldr.w r7, [sp], #4 8011124: 4770 bx lr ... 08011128 : * (*) Value not defined in all devices. * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8011128: b480 push {r7} 801112a: b085 sub sp, #20 801112c: af00 add r7, sp, #0 801112e: 6078 str r0, [r7, #4] 8011130: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8011132: 687b ldr r3, [r7, #4] 8011134: 689b ldr r3, [r3, #8] 8011136: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8011138: 68fa ldr r2, [r7, #12] 801113a: 4b09 ldr r3, [pc, #36] @ (8011160 ) 801113c: 4013 ands r3, r2 801113e: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8011140: 683a ldr r2, [r7, #0] 8011142: 68fb ldr r3, [r7, #12] 8011144: 4313 orrs r3, r2 8011146: f043 0307 orr.w r3, r3, #7 801114a: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 801114c: 687b ldr r3, [r7, #4] 801114e: 68fa ldr r2, [r7, #12] 8011150: 609a str r2, [r3, #8] } 8011152: bf00 nop 8011154: 3714 adds r7, #20 8011156: 46bd mov sp, r7 8011158: f85d 7b04 ldr.w r7, [sp], #4 801115c: 4770 bx lr 801115e: bf00 nop 8011160: ffcfff8f .word 0xffcfff8f 08011164 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8011164: b480 push {r7} 8011166: b087 sub sp, #28 8011168: af00 add r7, sp, #0 801116a: 60f8 str r0, [r7, #12] 801116c: 60b9 str r1, [r7, #8] 801116e: 607a str r2, [r7, #4] 8011170: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8011172: 68fb ldr r3, [r7, #12] 8011174: 689b ldr r3, [r3, #8] 8011176: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8011178: 697b ldr r3, [r7, #20] 801117a: f423 437f bic.w r3, r3, #65280 @ 0xff00 801117e: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8011180: 683b ldr r3, [r7, #0] 8011182: 021a lsls r2, r3, #8 8011184: 687b ldr r3, [r7, #4] 8011186: 431a orrs r2, r3 8011188: 68bb ldr r3, [r7, #8] 801118a: 4313 orrs r3, r2 801118c: 697a ldr r2, [r7, #20] 801118e: 4313 orrs r3, r2 8011190: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8011192: 68fb ldr r3, [r7, #12] 8011194: 697a ldr r2, [r7, #20] 8011196: 609a str r2, [r3, #8] } 8011198: bf00 nop 801119a: 371c adds r7, #28 801119c: 46bd mov sp, r7 801119e: f85d 7b04 ldr.w r7, [sp], #4 80111a2: 4770 bx lr 080111a4 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 80111a4: b480 push {r7} 80111a6: b087 sub sp, #28 80111a8: af00 add r7, sp, #0 80111aa: 60f8 str r0, [r7, #12] 80111ac: 60b9 str r1, [r7, #8] 80111ae: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 80111b0: 68bb ldr r3, [r7, #8] 80111b2: f003 031f and.w r3, r3, #31 80111b6: 2201 movs r2, #1 80111b8: fa02 f303 lsl.w r3, r2, r3 80111bc: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 80111be: 68fb ldr r3, [r7, #12] 80111c0: 6a1a ldr r2, [r3, #32] 80111c2: 697b ldr r3, [r7, #20] 80111c4: 43db mvns r3, r3 80111c6: 401a ands r2, r3 80111c8: 68fb ldr r3, [r7, #12] 80111ca: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 80111cc: 68fb ldr r3, [r7, #12] 80111ce: 6a1a ldr r2, [r3, #32] 80111d0: 68bb ldr r3, [r7, #8] 80111d2: f003 031f and.w r3, r3, #31 80111d6: 6879 ldr r1, [r7, #4] 80111d8: fa01 f303 lsl.w r3, r1, r3 80111dc: 431a orrs r2, r3 80111de: 68fb ldr r3, [r7, #12] 80111e0: 621a str r2, [r3, #32] } 80111e2: bf00 nop 80111e4: 371c adds r7, #28 80111e6: 46bd mov sp, r7 80111e8: f85d 7b04 ldr.w r7, [sp], #4 80111ec: 4770 bx lr ... 080111f0 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 80111f0: b480 push {r7} 80111f2: b085 sub sp, #20 80111f4: af00 add r7, sp, #0 80111f6: 6078 str r0, [r7, #4] 80111f8: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 80111fa: 687b ldr r3, [r7, #4] 80111fc: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8011200: 2b01 cmp r3, #1 8011202: d101 bne.n 8011208 8011204: 2302 movs r3, #2 8011206: e06d b.n 80112e4 8011208: 687b ldr r3, [r7, #4] 801120a: 2201 movs r2, #1 801120c: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8011210: 687b ldr r3, [r7, #4] 8011212: 2202 movs r2, #2 8011214: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8011218: 687b ldr r3, [r7, #4] 801121a: 681b ldr r3, [r3, #0] 801121c: 685b ldr r3, [r3, #4] 801121e: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8011220: 687b ldr r3, [r7, #4] 8011222: 681b ldr r3, [r3, #0] 8011224: 689b ldr r3, [r3, #8] 8011226: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 8011228: 687b ldr r3, [r7, #4] 801122a: 681b ldr r3, [r3, #0] 801122c: 4a30 ldr r2, [pc, #192] @ (80112f0 ) 801122e: 4293 cmp r3, r2 8011230: d004 beq.n 801123c 8011232: 687b ldr r3, [r7, #4] 8011234: 681b ldr r3, [r3, #0] 8011236: 4a2f ldr r2, [pc, #188] @ (80112f4 ) 8011238: 4293 cmp r3, r2 801123a: d108 bne.n 801124e { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 801123c: 68fb ldr r3, [r7, #12] 801123e: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 8011242: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 8011244: 683b ldr r3, [r7, #0] 8011246: 685b ldr r3, [r3, #4] 8011248: 68fa ldr r2, [r7, #12] 801124a: 4313 orrs r3, r2 801124c: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 801124e: 68fb ldr r3, [r7, #12] 8011250: f023 0370 bic.w r3, r3, #112 @ 0x70 8011254: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8011256: 683b ldr r3, [r7, #0] 8011258: 681b ldr r3, [r3, #0] 801125a: 68fa ldr r2, [r7, #12] 801125c: 4313 orrs r3, r2 801125e: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8011260: 687b ldr r3, [r7, #4] 8011262: 681b ldr r3, [r3, #0] 8011264: 68fa ldr r2, [r7, #12] 8011266: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8011268: 687b ldr r3, [r7, #4] 801126a: 681b ldr r3, [r3, #0] 801126c: 4a20 ldr r2, [pc, #128] @ (80112f0 ) 801126e: 4293 cmp r3, r2 8011270: d022 beq.n 80112b8 8011272: 687b ldr r3, [r7, #4] 8011274: 681b ldr r3, [r3, #0] 8011276: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 801127a: d01d beq.n 80112b8 801127c: 687b ldr r3, [r7, #4] 801127e: 681b ldr r3, [r3, #0] 8011280: 4a1d ldr r2, [pc, #116] @ (80112f8 ) 8011282: 4293 cmp r3, r2 8011284: d018 beq.n 80112b8 8011286: 687b ldr r3, [r7, #4] 8011288: 681b ldr r3, [r3, #0] 801128a: 4a1c ldr r2, [pc, #112] @ (80112fc ) 801128c: 4293 cmp r3, r2 801128e: d013 beq.n 80112b8 8011290: 687b ldr r3, [r7, #4] 8011292: 681b ldr r3, [r3, #0] 8011294: 4a1a ldr r2, [pc, #104] @ (8011300 ) 8011296: 4293 cmp r3, r2 8011298: d00e beq.n 80112b8 801129a: 687b ldr r3, [r7, #4] 801129c: 681b ldr r3, [r3, #0] 801129e: 4a15 ldr r2, [pc, #84] @ (80112f4 ) 80112a0: 4293 cmp r3, r2 80112a2: d009 beq.n 80112b8 80112a4: 687b ldr r3, [r7, #4] 80112a6: 681b ldr r3, [r3, #0] 80112a8: 4a16 ldr r2, [pc, #88] @ (8011304 ) 80112aa: 4293 cmp r3, r2 80112ac: d004 beq.n 80112b8 80112ae: 687b ldr r3, [r7, #4] 80112b0: 681b ldr r3, [r3, #0] 80112b2: 4a15 ldr r2, [pc, #84] @ (8011308 ) 80112b4: 4293 cmp r3, r2 80112b6: d10c bne.n 80112d2 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 80112b8: 68bb ldr r3, [r7, #8] 80112ba: f023 0380 bic.w r3, r3, #128 @ 0x80 80112be: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 80112c0: 683b ldr r3, [r7, #0] 80112c2: 689b ldr r3, [r3, #8] 80112c4: 68ba ldr r2, [r7, #8] 80112c6: 4313 orrs r3, r2 80112c8: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80112ca: 687b ldr r3, [r7, #4] 80112cc: 681b ldr r3, [r3, #0] 80112ce: 68ba ldr r2, [r7, #8] 80112d0: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 80112d2: 687b ldr r3, [r7, #4] 80112d4: 2201 movs r2, #1 80112d6: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 80112da: 687b ldr r3, [r7, #4] 80112dc: 2200 movs r2, #0 80112de: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 80112e2: 2300 movs r3, #0 } 80112e4: 4618 mov r0, r3 80112e6: 3714 adds r7, #20 80112e8: 46bd mov sp, r7 80112ea: f85d 7b04 ldr.w r7, [sp], #4 80112ee: 4770 bx lr 80112f0: 40010000 .word 0x40010000 80112f4: 40010400 .word 0x40010400 80112f8: 40000400 .word 0x40000400 80112fc: 40000800 .word 0x40000800 8011300: 40000c00 .word 0x40000c00 8011304: 40001800 .word 0x40001800 8011308: 40014000 .word 0x40014000 0801130c : * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { 801130c: b480 push {r7} 801130e: b085 sub sp, #20 8011310: af00 add r7, sp, #0 8011312: 6078 str r0, [r7, #4] 8011314: 6039 str r1, [r7, #0] /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; 8011316: 2300 movs r3, #0 8011318: 60fb str r3, [r7, #12] #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); #endif /* TIM_BDTR_BKBID */ /* Check input state */ __HAL_LOCK(htim); 801131a: 687b ldr r3, [r7, #4] 801131c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8011320: 2b01 cmp r3, #1 8011322: d101 bne.n 8011328 8011324: 2302 movs r3, #2 8011326: e065 b.n 80113f4 8011328: 687b ldr r3, [r7, #4] 801132a: 2201 movs r2, #1 801132c: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); 8011330: 68fb ldr r3, [r7, #12] 8011332: f023 02ff bic.w r2, r3, #255 @ 0xff 8011336: 683b ldr r3, [r7, #0] 8011338: 68db ldr r3, [r3, #12] 801133a: 4313 orrs r3, r2 801133c: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); 801133e: 68fb ldr r3, [r7, #12] 8011340: f423 7240 bic.w r2, r3, #768 @ 0x300 8011344: 683b ldr r3, [r7, #0] 8011346: 689b ldr r3, [r3, #8] 8011348: 4313 orrs r3, r2 801134a: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 801134c: 68fb ldr r3, [r7, #12] 801134e: f423 6280 bic.w r2, r3, #1024 @ 0x400 8011352: 683b ldr r3, [r7, #0] 8011354: 685b ldr r3, [r3, #4] 8011356: 4313 orrs r3, r2 8011358: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 801135a: 68fb ldr r3, [r7, #12] 801135c: f423 6200 bic.w r2, r3, #2048 @ 0x800 8011360: 683b ldr r3, [r7, #0] 8011362: 681b ldr r3, [r3, #0] 8011364: 4313 orrs r3, r2 8011366: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 8011368: 68fb ldr r3, [r7, #12] 801136a: f423 5280 bic.w r2, r3, #4096 @ 0x1000 801136e: 683b ldr r3, [r7, #0] 8011370: 691b ldr r3, [r3, #16] 8011372: 4313 orrs r3, r2 8011374: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 8011376: 68fb ldr r3, [r7, #12] 8011378: f423 5200 bic.w r2, r3, #8192 @ 0x2000 801137c: 683b ldr r3, [r7, #0] 801137e: 695b ldr r3, [r3, #20] 8011380: 4313 orrs r3, r2 8011382: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 8011384: 68fb ldr r3, [r7, #12] 8011386: f423 4280 bic.w r2, r3, #16384 @ 0x4000 801138a: 683b ldr r3, [r7, #0] 801138c: 6a9b ldr r3, [r3, #40] @ 0x28 801138e: 4313 orrs r3, r2 8011390: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 8011392: 68fb ldr r3, [r7, #12] 8011394: f423 2270 bic.w r2, r3, #983040 @ 0xf0000 8011398: 683b ldr r3, [r7, #0] 801139a: 699b ldr r3, [r3, #24] 801139c: 041b lsls r3, r3, #16 801139e: 4313 orrs r3, r2 80113a0: 60fb str r3, [r7, #12] #if defined(TIM_BDTR_BKBID) MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); #endif /* TIM_BDTR_BKBID */ if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) 80113a2: 687b ldr r3, [r7, #4] 80113a4: 681b ldr r3, [r3, #0] 80113a6: 4a16 ldr r2, [pc, #88] @ (8011400 ) 80113a8: 4293 cmp r3, r2 80113aa: d004 beq.n 80113b6 80113ac: 687b ldr r3, [r7, #4] 80113ae: 681b ldr r3, [r3, #0] 80113b0: 4a14 ldr r2, [pc, #80] @ (8011404 ) 80113b2: 4293 cmp r3, r2 80113b4: d115 bne.n 80113e2 #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); #endif /* TIM_BDTR_BKBID */ /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); 80113b6: 68fb ldr r3, [r7, #12] 80113b8: f423 0270 bic.w r2, r3, #15728640 @ 0xf00000 80113bc: 683b ldr r3, [r7, #0] 80113be: 6a5b ldr r3, [r3, #36] @ 0x24 80113c0: 051b lsls r3, r3, #20 80113c2: 4313 orrs r3, r2 80113c4: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); 80113c6: 68fb ldr r3, [r7, #12] 80113c8: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000 80113cc: 683b ldr r3, [r7, #0] 80113ce: 69db ldr r3, [r3, #28] 80113d0: 4313 orrs r3, r2 80113d2: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); 80113d4: 68fb ldr r3, [r7, #12] 80113d6: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000 80113da: 683b ldr r3, [r7, #0] 80113dc: 6a1b ldr r3, [r3, #32] 80113de: 4313 orrs r3, r2 80113e0: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); #endif /* TIM_BDTR_BKBID */ } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; 80113e2: 687b ldr r3, [r7, #4] 80113e4: 681b ldr r3, [r3, #0] 80113e6: 68fa ldr r2, [r7, #12] 80113e8: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(htim); 80113ea: 687b ldr r3, [r7, #4] 80113ec: 2200 movs r2, #0 80113ee: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 80113f2: 2300 movs r3, #0 } 80113f4: 4618 mov r0, r3 80113f6: 3714 adds r7, #20 80113f8: 46bd mov sp, r7 80113fa: f85d 7b04 ldr.w r7, [sp], #4 80113fe: 4770 bx lr 8011400: 40010000 .word 0x40010000 8011404: 40010400 .word 0x40010400 08011408 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8011408: b480 push {r7} 801140a: b083 sub sp, #12 801140c: af00 add r7, sp, #0 801140e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8011410: bf00 nop 8011412: 370c adds r7, #12 8011414: 46bd mov sp, r7 8011416: f85d 7b04 ldr.w r7, [sp], #4 801141a: 4770 bx lr 0801141c : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 801141c: b480 push {r7} 801141e: b083 sub sp, #12 8011420: af00 add r7, sp, #0 8011422: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8011424: bf00 nop 8011426: 370c adds r7, #12 8011428: 46bd mov sp, r7 801142a: f85d 7b04 ldr.w r7, [sp], #4 801142e: 4770 bx lr 08011430 : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 8011430: b480 push {r7} 8011432: b083 sub sp, #12 8011434: af00 add r7, sp, #0 8011436: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 8011438: bf00 nop 801143a: 370c adds r7, #12 801143c: 46bd mov sp, r7 801143e: f85d 7b04 ldr.w r7, [sp], #4 8011442: 4770 bx lr 08011444 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8011444: b580 push {r7, lr} 8011446: b082 sub sp, #8 8011448: af00 add r7, sp, #0 801144a: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 801144c: 687b ldr r3, [r7, #4] 801144e: 2b00 cmp r3, #0 8011450: d101 bne.n 8011456 { return HAL_ERROR; 8011452: 2301 movs r3, #1 8011454: e042 b.n 80114dc { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 8011456: 687b ldr r3, [r7, #4] 8011458: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 801145c: 2b00 cmp r3, #0 801145e: d106 bne.n 801146e { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8011460: 687b ldr r3, [r7, #4] 8011462: 2200 movs r2, #0 8011464: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8011468: 6878 ldr r0, [r7, #4] 801146a: f7f3 f881 bl 8004570 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 801146e: 687b ldr r3, [r7, #4] 8011470: 2224 movs r2, #36 @ 0x24 8011472: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UART_DISABLE(huart); 8011476: 687b ldr r3, [r7, #4] 8011478: 681b ldr r3, [r3, #0] 801147a: 681a ldr r2, [r3, #0] 801147c: 687b ldr r3, [r7, #4] 801147e: 681b ldr r3, [r3, #0] 8011480: f022 0201 bic.w r2, r2, #1 8011484: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 8011486: 687b ldr r3, [r7, #4] 8011488: 6a9b ldr r3, [r3, #40] @ 0x28 801148a: 2b00 cmp r3, #0 801148c: d002 beq.n 8011494 { UART_AdvFeatureConfig(huart); 801148e: 6878 ldr r0, [r7, #4] 8011490: f001 f9e8 bl 8012864 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 8011494: 6878 ldr r0, [r7, #4] 8011496: f000 fc7d bl 8011d94 801149a: 4603 mov r3, r0 801149c: 2b01 cmp r3, #1 801149e: d101 bne.n 80114a4 { return HAL_ERROR; 80114a0: 2301 movs r3, #1 80114a2: e01b b.n 80114dc } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 80114a4: 687b ldr r3, [r7, #4] 80114a6: 681b ldr r3, [r3, #0] 80114a8: 685a ldr r2, [r3, #4] 80114aa: 687b ldr r3, [r7, #4] 80114ac: 681b ldr r3, [r3, #0] 80114ae: f422 4290 bic.w r2, r2, #18432 @ 0x4800 80114b2: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 80114b4: 687b ldr r3, [r7, #4] 80114b6: 681b ldr r3, [r3, #0] 80114b8: 689a ldr r2, [r3, #8] 80114ba: 687b ldr r3, [r7, #4] 80114bc: 681b ldr r3, [r3, #0] 80114be: f022 022a bic.w r2, r2, #42 @ 0x2a 80114c2: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 80114c4: 687b ldr r3, [r7, #4] 80114c6: 681b ldr r3, [r3, #0] 80114c8: 681a ldr r2, [r3, #0] 80114ca: 687b ldr r3, [r7, #4] 80114cc: 681b ldr r3, [r3, #0] 80114ce: f042 0201 orr.w r2, r2, #1 80114d2: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 80114d4: 6878 ldr r0, [r7, #4] 80114d6: f001 fa67 bl 80129a8 80114da: 4603 mov r3, r0 } 80114dc: 4618 mov r0, r3 80114de: 3708 adds r7, #8 80114e0: 46bd mov sp, r7 80114e2: bd80 pop {r7, pc} 080114e4 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 80114e4: b480 push {r7} 80114e6: b091 sub sp, #68 @ 0x44 80114e8: af00 add r7, sp, #0 80114ea: 60f8 str r0, [r7, #12] 80114ec: 60b9 str r1, [r7, #8] 80114ee: 4613 mov r3, r2 80114f0: 80fb strh r3, [r7, #6] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 80114f2: 68fb ldr r3, [r7, #12] 80114f4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80114f8: 2b20 cmp r3, #32 80114fa: d178 bne.n 80115ee { if ((pData == NULL) || (Size == 0U)) 80114fc: 68bb ldr r3, [r7, #8] 80114fe: 2b00 cmp r3, #0 8011500: d002 beq.n 8011508 8011502: 88fb ldrh r3, [r7, #6] 8011504: 2b00 cmp r3, #0 8011506: d101 bne.n 801150c { return HAL_ERROR; 8011508: 2301 movs r3, #1 801150a: e071 b.n 80115f0 } huart->pTxBuffPtr = pData; 801150c: 68fb ldr r3, [r7, #12] 801150e: 68ba ldr r2, [r7, #8] 8011510: 651a str r2, [r3, #80] @ 0x50 huart->TxXferSize = Size; 8011512: 68fb ldr r3, [r7, #12] 8011514: 88fa ldrh r2, [r7, #6] 8011516: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 huart->TxXferCount = Size; 801151a: 68fb ldr r3, [r7, #12] 801151c: 88fa ldrh r2, [r7, #6] 801151e: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 huart->TxISR = NULL; 8011522: 68fb ldr r3, [r7, #12] 8011524: 2200 movs r2, #0 8011526: 679a str r2, [r3, #120] @ 0x78 huart->ErrorCode = HAL_UART_ERROR_NONE; 8011528: 68fb ldr r3, [r7, #12] 801152a: 2200 movs r2, #0 801152c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->gState = HAL_UART_STATE_BUSY_TX; 8011530: 68fb ldr r3, [r7, #12] 8011532: 2221 movs r2, #33 @ 0x21 8011534: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Configure Tx interrupt processing */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) 8011538: 68fb ldr r3, [r7, #12] 801153a: 6e5b ldr r3, [r3, #100] @ 0x64 801153c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8011540: d12a bne.n 8011598 { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8011542: 68fb ldr r3, [r7, #12] 8011544: 689b ldr r3, [r3, #8] 8011546: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 801154a: d107 bne.n 801155c 801154c: 68fb ldr r3, [r7, #12] 801154e: 691b ldr r3, [r3, #16] 8011550: 2b00 cmp r3, #0 8011552: d103 bne.n 801155c { huart->TxISR = UART_TxISR_16BIT_FIFOEN; 8011554: 68fb ldr r3, [r7, #12] 8011556: 4a29 ldr r2, [pc, #164] @ (80115fc ) 8011558: 679a str r2, [r3, #120] @ 0x78 801155a: e002 b.n 8011562 } else { huart->TxISR = UART_TxISR_8BIT_FIFOEN; 801155c: 68fb ldr r3, [r7, #12] 801155e: 4a28 ldr r2, [pc, #160] @ (8011600 ) 8011560: 679a str r2, [r3, #120] @ 0x78 } /* Enable the TX FIFO threshold interrupt */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 8011562: 68fb ldr r3, [r7, #12] 8011564: 681b ldr r3, [r3, #0] 8011566: 3308 adds r3, #8 8011568: 62bb str r3, [r7, #40] @ 0x28 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801156a: 6abb ldr r3, [r7, #40] @ 0x28 801156c: e853 3f00 ldrex r3, [r3] 8011570: 627b str r3, [r7, #36] @ 0x24 return(result); 8011572: 6a7b ldr r3, [r7, #36] @ 0x24 8011574: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 8011578: 63bb str r3, [r7, #56] @ 0x38 801157a: 68fb ldr r3, [r7, #12] 801157c: 681b ldr r3, [r3, #0] 801157e: 3308 adds r3, #8 8011580: 6bba ldr r2, [r7, #56] @ 0x38 8011582: 637a str r2, [r7, #52] @ 0x34 8011584: 633b str r3, [r7, #48] @ 0x30 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011586: 6b39 ldr r1, [r7, #48] @ 0x30 8011588: 6b7a ldr r2, [r7, #52] @ 0x34 801158a: e841 2300 strex r3, r2, [r1] 801158e: 62fb str r3, [r7, #44] @ 0x2c return(result); 8011590: 6afb ldr r3, [r7, #44] @ 0x2c 8011592: 2b00 cmp r3, #0 8011594: d1e5 bne.n 8011562 8011596: e028 b.n 80115ea } else { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8011598: 68fb ldr r3, [r7, #12] 801159a: 689b ldr r3, [r3, #8] 801159c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80115a0: d107 bne.n 80115b2 80115a2: 68fb ldr r3, [r7, #12] 80115a4: 691b ldr r3, [r3, #16] 80115a6: 2b00 cmp r3, #0 80115a8: d103 bne.n 80115b2 { huart->TxISR = UART_TxISR_16BIT; 80115aa: 68fb ldr r3, [r7, #12] 80115ac: 4a15 ldr r2, [pc, #84] @ (8011604 ) 80115ae: 679a str r2, [r3, #120] @ 0x78 80115b0: e002 b.n 80115b8 } else { huart->TxISR = UART_TxISR_8BIT; 80115b2: 68fb ldr r3, [r7, #12] 80115b4: 4a14 ldr r2, [pc, #80] @ (8011608 ) 80115b6: 679a str r2, [r3, #120] @ 0x78 } /* Enable the Transmit Data Register Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 80115b8: 68fb ldr r3, [r7, #12] 80115ba: 681b ldr r3, [r3, #0] 80115bc: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80115be: 697b ldr r3, [r7, #20] 80115c0: e853 3f00 ldrex r3, [r3] 80115c4: 613b str r3, [r7, #16] return(result); 80115c6: 693b ldr r3, [r7, #16] 80115c8: f043 0380 orr.w r3, r3, #128 @ 0x80 80115cc: 63fb str r3, [r7, #60] @ 0x3c 80115ce: 68fb ldr r3, [r7, #12] 80115d0: 681b ldr r3, [r3, #0] 80115d2: 461a mov r2, r3 80115d4: 6bfb ldr r3, [r7, #60] @ 0x3c 80115d6: 623b str r3, [r7, #32] 80115d8: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80115da: 69f9 ldr r1, [r7, #28] 80115dc: 6a3a ldr r2, [r7, #32] 80115de: e841 2300 strex r3, r2, [r1] 80115e2: 61bb str r3, [r7, #24] return(result); 80115e4: 69bb ldr r3, [r7, #24] 80115e6: 2b00 cmp r3, #0 80115e8: d1e6 bne.n 80115b8 } return HAL_OK; 80115ea: 2300 movs r3, #0 80115ec: e000 b.n 80115f0 } else { return HAL_BUSY; 80115ee: 2302 movs r3, #2 } } 80115f0: 4618 mov r0, r3 80115f2: 3744 adds r7, #68 @ 0x44 80115f4: 46bd mov sp, r7 80115f6: f85d 7b04 ldr.w r7, [sp], #4 80115fa: 4770 bx lr 80115fc: 0801316f .word 0x0801316f 8011600: 0801308f .word 0x0801308f 8011604: 08012fcd .word 0x08012fcd 8011608: 08012f15 .word 0x08012f15 0801160c : * @brief Handle UART interrupt request. * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 801160c: b580 push {r7, lr} 801160e: b0ba sub sp, #232 @ 0xe8 8011610: af00 add r7, sp, #0 8011612: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->ISR); 8011614: 687b ldr r3, [r7, #4] 8011616: 681b ldr r3, [r3, #0] 8011618: 69db ldr r3, [r3, #28] 801161a: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 801161e: 687b ldr r3, [r7, #4] 8011620: 681b ldr r3, [r3, #0] 8011622: 681b ldr r3, [r3, #0] 8011624: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8011628: 687b ldr r3, [r7, #4] 801162a: 681b ldr r3, [r3, #0] 801162c: 689b ldr r3, [r3, #8] 801162e: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags; uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); 8011632: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4 8011636: f640 030f movw r3, #2063 @ 0x80f 801163a: 4013 ands r3, r2 801163c: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == 0U) 8011640: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8011644: 2b00 cmp r3, #0 8011646: d11b bne.n 8011680 { /* UART in mode Receiver ---------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 8011648: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801164c: f003 0320 and.w r3, r3, #32 8011650: 2b00 cmp r3, #0 8011652: d015 beq.n 8011680 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 8011654: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011658: f003 0320 and.w r3, r3, #32 801165c: 2b00 cmp r3, #0 801165e: d105 bne.n 801166c || ((cr3its & USART_CR3_RXFTIE) != 0U))) 8011660: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011664: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011668: 2b00 cmp r3, #0 801166a: d009 beq.n 8011680 { if (huart->RxISR != NULL) 801166c: 687b ldr r3, [r7, #4] 801166e: 6f5b ldr r3, [r3, #116] @ 0x74 8011670: 2b00 cmp r3, #0 8011672: f000 8377 beq.w 8011d64 { huart->RxISR(huart); 8011676: 687b ldr r3, [r7, #4] 8011678: 6f5b ldr r3, [r3, #116] @ 0x74 801167a: 6878 ldr r0, [r7, #4] 801167c: 4798 blx r3 } return; 801167e: e371 b.n 8011d64 } } /* If some errors occur */ if ((errorflags != 0U) 8011680: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8011684: 2b00 cmp r3, #0 8011686: f000 8123 beq.w 80118d0 && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) 801168a: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 801168e: 4b8d ldr r3, [pc, #564] @ (80118c4 ) 8011690: 4013 ands r3, r2 8011692: 2b00 cmp r3, #0 8011694: d106 bne.n 80116a4 || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) 8011696: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0 801169a: 4b8b ldr r3, [pc, #556] @ (80118c8 ) 801169c: 4013 ands r3, r2 801169e: 2b00 cmp r3, #0 80116a0: f000 8116 beq.w 80118d0 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 80116a4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80116a8: f003 0301 and.w r3, r3, #1 80116ac: 2b00 cmp r3, #0 80116ae: d011 beq.n 80116d4 80116b0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80116b4: f403 7380 and.w r3, r3, #256 @ 0x100 80116b8: 2b00 cmp r3, #0 80116ba: d00b beq.n 80116d4 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 80116bc: 687b ldr r3, [r7, #4] 80116be: 681b ldr r3, [r3, #0] 80116c0: 2201 movs r2, #1 80116c2: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 80116c4: 687b ldr r3, [r7, #4] 80116c6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80116ca: f043 0201 orr.w r2, r3, #1 80116ce: 687b ldr r3, [r7, #4] 80116d0: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 80116d4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80116d8: f003 0302 and.w r3, r3, #2 80116dc: 2b00 cmp r3, #0 80116de: d011 beq.n 8011704 80116e0: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80116e4: f003 0301 and.w r3, r3, #1 80116e8: 2b00 cmp r3, #0 80116ea: d00b beq.n 8011704 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 80116ec: 687b ldr r3, [r7, #4] 80116ee: 681b ldr r3, [r3, #0] 80116f0: 2202 movs r2, #2 80116f2: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 80116f4: 687b ldr r3, [r7, #4] 80116f6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80116fa: f043 0204 orr.w r2, r3, #4 80116fe: 687b ldr r3, [r7, #4] 8011700: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8011704: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011708: f003 0304 and.w r3, r3, #4 801170c: 2b00 cmp r3, #0 801170e: d011 beq.n 8011734 8011710: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011714: f003 0301 and.w r3, r3, #1 8011718: 2b00 cmp r3, #0 801171a: d00b beq.n 8011734 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 801171c: 687b ldr r3, [r7, #4] 801171e: 681b ldr r3, [r3, #0] 8011720: 2204 movs r2, #4 8011722: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8011724: 687b ldr r3, [r7, #4] 8011726: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 801172a: f043 0202 orr.w r2, r3, #2 801172e: 687b ldr r3, [r7, #4] 8011730: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Over-Run interrupt occurred -----------------------------------------*/ if (((isrflags & USART_ISR_ORE) != 0U) 8011734: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011738: f003 0308 and.w r3, r3, #8 801173c: 2b00 cmp r3, #0 801173e: d017 beq.n 8011770 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 8011740: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011744: f003 0320 and.w r3, r3, #32 8011748: 2b00 cmp r3, #0 801174a: d105 bne.n 8011758 ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) 801174c: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 8011750: 4b5c ldr r3, [pc, #368] @ (80118c4 ) 8011752: 4013 ands r3, r2 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 8011754: 2b00 cmp r3, #0 8011756: d00b beq.n 8011770 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8011758: 687b ldr r3, [r7, #4] 801175a: 681b ldr r3, [r3, #0] 801175c: 2208 movs r2, #8 801175e: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_ORE; 8011760: 687b ldr r3, [r7, #4] 8011762: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011766: f043 0208 orr.w r2, r3, #8 801176a: 687b ldr r3, [r7, #4] 801176c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Receiver Timeout interrupt occurred ---------------------------------*/ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) 8011770: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011774: f403 6300 and.w r3, r3, #2048 @ 0x800 8011778: 2b00 cmp r3, #0 801177a: d012 beq.n 80117a2 801177c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011780: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8011784: 2b00 cmp r3, #0 8011786: d00c beq.n 80117a2 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8011788: 687b ldr r3, [r7, #4] 801178a: 681b ldr r3, [r3, #0] 801178c: f44f 6200 mov.w r2, #2048 @ 0x800 8011790: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_RTO; 8011792: 687b ldr r3, [r7, #4] 8011794: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011798: f043 0220 orr.w r2, r3, #32 801179c: 687b ldr r3, [r7, #4] 801179e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 80117a2: 687b ldr r3, [r7, #4] 80117a4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80117a8: 2b00 cmp r3, #0 80117aa: f000 82dd beq.w 8011d68 { /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 80117ae: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80117b2: f003 0320 and.w r3, r3, #32 80117b6: 2b00 cmp r3, #0 80117b8: d013 beq.n 80117e2 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 80117ba: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80117be: f003 0320 and.w r3, r3, #32 80117c2: 2b00 cmp r3, #0 80117c4: d105 bne.n 80117d2 || ((cr3its & USART_CR3_RXFTIE) != 0U))) 80117c6: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80117ca: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80117ce: 2b00 cmp r3, #0 80117d0: d007 beq.n 80117e2 { if (huart->RxISR != NULL) 80117d2: 687b ldr r3, [r7, #4] 80117d4: 6f5b ldr r3, [r3, #116] @ 0x74 80117d6: 2b00 cmp r3, #0 80117d8: d003 beq.n 80117e2 { huart->RxISR(huart); 80117da: 687b ldr r3, [r7, #4] 80117dc: 6f5b ldr r3, [r3, #116] @ 0x74 80117de: 6878 ldr r0, [r7, #4] 80117e0: 4798 blx r3 /* If Error is to be considered as blocking : - Receiver Timeout error in Reception - Overrun error in Reception - any error occurs in DMA mode reception */ errorcode = huart->ErrorCode; 80117e2: 687b ldr r3, [r7, #4] 80117e4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80117e8: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 80117ec: 687b ldr r3, [r7, #4] 80117ee: 681b ldr r3, [r3, #0] 80117f0: 689b ldr r3, [r3, #8] 80117f2: f003 0340 and.w r3, r3, #64 @ 0x40 80117f6: 2b40 cmp r3, #64 @ 0x40 80117f8: d005 beq.n 8011806 ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) 80117fa: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 80117fe: f003 0328 and.w r3, r3, #40 @ 0x28 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8011802: 2b00 cmp r3, #0 8011804: d054 beq.n 80118b0 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8011806: 6878 ldr r0, [r7, #4] 8011808: f001 fb08 bl 8012e1c /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801180c: 687b ldr r3, [r7, #4] 801180e: 681b ldr r3, [r3, #0] 8011810: 689b ldr r3, [r3, #8] 8011812: f003 0340 and.w r3, r3, #64 @ 0x40 8011816: 2b40 cmp r3, #64 @ 0x40 8011818: d146 bne.n 80118a8 { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 801181a: 687b ldr r3, [r7, #4] 801181c: 681b ldr r3, [r3, #0] 801181e: 3308 adds r3, #8 8011820: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011824: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8011828: e853 3f00 ldrex r3, [r3] 801182c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8011830: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8011834: f023 0340 bic.w r3, r3, #64 @ 0x40 8011838: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 801183c: 687b ldr r3, [r7, #4] 801183e: 681b ldr r3, [r3, #0] 8011840: 3308 adds r3, #8 8011842: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8011846: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 801184a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801184e: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8011852: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8011856: e841 2300 strex r3, r2, [r1] 801185a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 801185e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8011862: 2b00 cmp r3, #0 8011864: d1d9 bne.n 801181a /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 8011866: 687b ldr r3, [r7, #4] 8011868: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801186c: 2b00 cmp r3, #0 801186e: d017 beq.n 80118a0 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8011870: 687b ldr r3, [r7, #4] 8011872: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011876: 4a15 ldr r2, [pc, #84] @ (80118cc ) 8011878: 651a str r2, [r3, #80] @ 0x50 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 801187a: 687b ldr r3, [r7, #4] 801187c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011880: 4618 mov r0, r3 8011882: f7f7 ff8f bl 80097a4 8011886: 4603 mov r3, r0 8011888: 2b00 cmp r3, #0 801188a: d019 beq.n 80118c0 { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 801188c: 687b ldr r3, [r7, #4] 801188e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011892: 6d1b ldr r3, [r3, #80] @ 0x50 8011894: 687a ldr r2, [r7, #4] 8011896: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80 801189a: 4610 mov r0, r2 801189c: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801189e: e00f b.n 80118c0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80118a0: 6878 ldr r0, [r7, #4] 80118a2: f000 fa6d bl 8011d80 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80118a6: e00b b.n 80118c0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80118a8: 6878 ldr r0, [r7, #4] 80118aa: f000 fa69 bl 8011d80 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80118ae: e007 b.n 80118c0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80118b0: 6878 ldr r0, [r7, #4] 80118b2: f000 fa65 bl 8011d80 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80118b6: 687b ldr r3, [r7, #4] 80118b8: 2200 movs r2, #0 80118ba: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } return; 80118be: e253 b.n 8011d68 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80118c0: bf00 nop return; 80118c2: e251 b.n 8011d68 80118c4: 10000001 .word 0x10000001 80118c8: 04000120 .word 0x04000120 80118cc: 08012ee9 .word 0x08012ee9 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80118d0: 687b ldr r3, [r7, #4] 80118d2: 6edb ldr r3, [r3, #108] @ 0x6c 80118d4: 2b01 cmp r3, #1 80118d6: f040 81e7 bne.w 8011ca8 && ((isrflags & USART_ISR_IDLE) != 0U) 80118da: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80118de: f003 0310 and.w r3, r3, #16 80118e2: 2b00 cmp r3, #0 80118e4: f000 81e0 beq.w 8011ca8 && ((cr1its & USART_ISR_IDLE) != 0U)) 80118e8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80118ec: f003 0310 and.w r3, r3, #16 80118f0: 2b00 cmp r3, #0 80118f2: f000 81d9 beq.w 8011ca8 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 80118f6: 687b ldr r3, [r7, #4] 80118f8: 681b ldr r3, [r3, #0] 80118fa: 2210 movs r2, #16 80118fc: 621a str r2, [r3, #32] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80118fe: 687b ldr r3, [r7, #4] 8011900: 681b ldr r3, [r3, #0] 8011902: 689b ldr r3, [r3, #8] 8011904: f003 0340 and.w r3, r3, #64 @ 0x40 8011908: 2b40 cmp r3, #64 @ 0x40 801190a: f040 8151 bne.w 8011bb0 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 801190e: 687b ldr r3, [r7, #4] 8011910: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011914: 681b ldr r3, [r3, #0] 8011916: 4a96 ldr r2, [pc, #600] @ (8011b70 ) 8011918: 4293 cmp r3, r2 801191a: d068 beq.n 80119ee 801191c: 687b ldr r3, [r7, #4] 801191e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011922: 681b ldr r3, [r3, #0] 8011924: 4a93 ldr r2, [pc, #588] @ (8011b74 ) 8011926: 4293 cmp r3, r2 8011928: d061 beq.n 80119ee 801192a: 687b ldr r3, [r7, #4] 801192c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011930: 681b ldr r3, [r3, #0] 8011932: 4a91 ldr r2, [pc, #580] @ (8011b78 ) 8011934: 4293 cmp r3, r2 8011936: d05a beq.n 80119ee 8011938: 687b ldr r3, [r7, #4] 801193a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801193e: 681b ldr r3, [r3, #0] 8011940: 4a8e ldr r2, [pc, #568] @ (8011b7c ) 8011942: 4293 cmp r3, r2 8011944: d053 beq.n 80119ee 8011946: 687b ldr r3, [r7, #4] 8011948: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801194c: 681b ldr r3, [r3, #0] 801194e: 4a8c ldr r2, [pc, #560] @ (8011b80 ) 8011950: 4293 cmp r3, r2 8011952: d04c beq.n 80119ee 8011954: 687b ldr r3, [r7, #4] 8011956: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801195a: 681b ldr r3, [r3, #0] 801195c: 4a89 ldr r2, [pc, #548] @ (8011b84 ) 801195e: 4293 cmp r3, r2 8011960: d045 beq.n 80119ee 8011962: 687b ldr r3, [r7, #4] 8011964: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011968: 681b ldr r3, [r3, #0] 801196a: 4a87 ldr r2, [pc, #540] @ (8011b88 ) 801196c: 4293 cmp r3, r2 801196e: d03e beq.n 80119ee 8011970: 687b ldr r3, [r7, #4] 8011972: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011976: 681b ldr r3, [r3, #0] 8011978: 4a84 ldr r2, [pc, #528] @ (8011b8c ) 801197a: 4293 cmp r3, r2 801197c: d037 beq.n 80119ee 801197e: 687b ldr r3, [r7, #4] 8011980: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011984: 681b ldr r3, [r3, #0] 8011986: 4a82 ldr r2, [pc, #520] @ (8011b90 ) 8011988: 4293 cmp r3, r2 801198a: d030 beq.n 80119ee 801198c: 687b ldr r3, [r7, #4] 801198e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011992: 681b ldr r3, [r3, #0] 8011994: 4a7f ldr r2, [pc, #508] @ (8011b94 ) 8011996: 4293 cmp r3, r2 8011998: d029 beq.n 80119ee 801199a: 687b ldr r3, [r7, #4] 801199c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80119a0: 681b ldr r3, [r3, #0] 80119a2: 4a7d ldr r2, [pc, #500] @ (8011b98 ) 80119a4: 4293 cmp r3, r2 80119a6: d022 beq.n 80119ee 80119a8: 687b ldr r3, [r7, #4] 80119aa: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80119ae: 681b ldr r3, [r3, #0] 80119b0: 4a7a ldr r2, [pc, #488] @ (8011b9c ) 80119b2: 4293 cmp r3, r2 80119b4: d01b beq.n 80119ee 80119b6: 687b ldr r3, [r7, #4] 80119b8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80119bc: 681b ldr r3, [r3, #0] 80119be: 4a78 ldr r2, [pc, #480] @ (8011ba0 ) 80119c0: 4293 cmp r3, r2 80119c2: d014 beq.n 80119ee 80119c4: 687b ldr r3, [r7, #4] 80119c6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80119ca: 681b ldr r3, [r3, #0] 80119cc: 4a75 ldr r2, [pc, #468] @ (8011ba4 ) 80119ce: 4293 cmp r3, r2 80119d0: d00d beq.n 80119ee 80119d2: 687b ldr r3, [r7, #4] 80119d4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80119d8: 681b ldr r3, [r3, #0] 80119da: 4a73 ldr r2, [pc, #460] @ (8011ba8 ) 80119dc: 4293 cmp r3, r2 80119de: d006 beq.n 80119ee 80119e0: 687b ldr r3, [r7, #4] 80119e2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80119e6: 681b ldr r3, [r3, #0] 80119e8: 4a70 ldr r2, [pc, #448] @ (8011bac ) 80119ea: 4293 cmp r3, r2 80119ec: d106 bne.n 80119fc 80119ee: 687b ldr r3, [r7, #4] 80119f0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80119f4: 681b ldr r3, [r3, #0] 80119f6: 685b ldr r3, [r3, #4] 80119f8: b29b uxth r3, r3 80119fa: e005 b.n 8011a08 80119fc: 687b ldr r3, [r7, #4] 80119fe: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011a02: 681b ldr r3, [r3, #0] 8011a04: 685b ldr r3, [r3, #4] 8011a06: b29b uxth r3, r3 8011a08: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8011a0c: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8011a10: 2b00 cmp r3, #0 8011a12: f000 81ab beq.w 8011d6c && (nb_remaining_rx_data < huart->RxXferSize)) 8011a16: 687b ldr r3, [r7, #4] 8011a18: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8011a1c: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8011a20: 429a cmp r2, r3 8011a22: f080 81a3 bcs.w 8011d6c { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8011a26: 687b ldr r3, [r7, #4] 8011a28: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8011a2c: f8a3 205e strh.w r2, [r3, #94] @ 0x5e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8011a30: 687b ldr r3, [r7, #4] 8011a32: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011a36: 69db ldr r3, [r3, #28] 8011a38: f5b3 7f80 cmp.w r3, #256 @ 0x100 8011a3c: f000 8087 beq.w 8011b4e { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8011a40: 687b ldr r3, [r7, #4] 8011a42: 681b ldr r3, [r3, #0] 8011a44: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011a48: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8011a4c: e853 3f00 ldrex r3, [r3] 8011a50: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8011a54: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8011a58: f423 7380 bic.w r3, r3, #256 @ 0x100 8011a5c: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8011a60: 687b ldr r3, [r7, #4] 8011a62: 681b ldr r3, [r3, #0] 8011a64: 461a mov r2, r3 8011a66: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 8011a6a: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8011a6e: f8c7 2090 str.w r2, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011a72: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8011a76: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8011a7a: e841 2300 strex r3, r2, [r1] 8011a7e: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8011a82: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8011a86: 2b00 cmp r3, #0 8011a88: d1da bne.n 8011a40 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8011a8a: 687b ldr r3, [r7, #4] 8011a8c: 681b ldr r3, [r3, #0] 8011a8e: 3308 adds r3, #8 8011a90: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011a92: 6f7b ldr r3, [r7, #116] @ 0x74 8011a94: e853 3f00 ldrex r3, [r3] 8011a98: 673b str r3, [r7, #112] @ 0x70 return(result); 8011a9a: 6f3b ldr r3, [r7, #112] @ 0x70 8011a9c: f023 0301 bic.w r3, r3, #1 8011aa0: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8011aa4: 687b ldr r3, [r7, #4] 8011aa6: 681b ldr r3, [r3, #0] 8011aa8: 3308 adds r3, #8 8011aaa: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8011aae: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8011ab2: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011ab4: 6ff9 ldr r1, [r7, #124] @ 0x7c 8011ab6: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8011aba: e841 2300 strex r3, r2, [r1] 8011abe: 67bb str r3, [r7, #120] @ 0x78 return(result); 8011ac0: 6fbb ldr r3, [r7, #120] @ 0x78 8011ac2: 2b00 cmp r3, #0 8011ac4: d1e1 bne.n 8011a8a /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8011ac6: 687b ldr r3, [r7, #4] 8011ac8: 681b ldr r3, [r3, #0] 8011aca: 3308 adds r3, #8 8011acc: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011ace: 6e3b ldr r3, [r7, #96] @ 0x60 8011ad0: e853 3f00 ldrex r3, [r3] 8011ad4: 65fb str r3, [r7, #92] @ 0x5c return(result); 8011ad6: 6dfb ldr r3, [r7, #92] @ 0x5c 8011ad8: f023 0340 bic.w r3, r3, #64 @ 0x40 8011adc: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8011ae0: 687b ldr r3, [r7, #4] 8011ae2: 681b ldr r3, [r3, #0] 8011ae4: 3308 adds r3, #8 8011ae6: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8011aea: 66fa str r2, [r7, #108] @ 0x6c 8011aec: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011aee: 6eb9 ldr r1, [r7, #104] @ 0x68 8011af0: 6efa ldr r2, [r7, #108] @ 0x6c 8011af2: e841 2300 strex r3, r2, [r1] 8011af6: 667b str r3, [r7, #100] @ 0x64 return(result); 8011af8: 6e7b ldr r3, [r7, #100] @ 0x64 8011afa: 2b00 cmp r3, #0 8011afc: d1e3 bne.n 8011ac6 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8011afe: 687b ldr r3, [r7, #4] 8011b00: 2220 movs r2, #32 8011b02: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8011b06: 687b ldr r3, [r7, #4] 8011b08: 2200 movs r2, #0 8011b0a: 66da str r2, [r3, #108] @ 0x6c ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8011b0c: 687b ldr r3, [r7, #4] 8011b0e: 681b ldr r3, [r3, #0] 8011b10: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011b12: 6cfb ldr r3, [r7, #76] @ 0x4c 8011b14: e853 3f00 ldrex r3, [r3] 8011b18: 64bb str r3, [r7, #72] @ 0x48 return(result); 8011b1a: 6cbb ldr r3, [r7, #72] @ 0x48 8011b1c: f023 0310 bic.w r3, r3, #16 8011b20: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8011b24: 687b ldr r3, [r7, #4] 8011b26: 681b ldr r3, [r3, #0] 8011b28: 461a mov r2, r3 8011b2a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8011b2e: 65bb str r3, [r7, #88] @ 0x58 8011b30: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011b32: 6d79 ldr r1, [r7, #84] @ 0x54 8011b34: 6dba ldr r2, [r7, #88] @ 0x58 8011b36: e841 2300 strex r3, r2, [r1] 8011b3a: 653b str r3, [r7, #80] @ 0x50 return(result); 8011b3c: 6d3b ldr r3, [r7, #80] @ 0x50 8011b3e: 2b00 cmp r3, #0 8011b40: d1e4 bne.n 8011b0c /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8011b42: 687b ldr r3, [r7, #4] 8011b44: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011b48: 4618 mov r0, r3 8011b4a: f7f7 fb0d bl 8009168 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8011b4e: 687b ldr r3, [r7, #4] 8011b50: 2202 movs r2, #2 8011b52: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8011b54: 687b ldr r3, [r7, #4] 8011b56: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 8011b5a: 687b ldr r3, [r7, #4] 8011b5c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011b60: b29b uxth r3, r3 8011b62: 1ad3 subs r3, r2, r3 8011b64: b29b uxth r3, r3 8011b66: 4619 mov r1, r3 8011b68: 6878 ldr r0, [r7, #4] 8011b6a: f7f2 ffff bl 8004b6c #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 8011b6e: e0fd b.n 8011d6c 8011b70: 40020010 .word 0x40020010 8011b74: 40020028 .word 0x40020028 8011b78: 40020040 .word 0x40020040 8011b7c: 40020058 .word 0x40020058 8011b80: 40020070 .word 0x40020070 8011b84: 40020088 .word 0x40020088 8011b88: 400200a0 .word 0x400200a0 8011b8c: 400200b8 .word 0x400200b8 8011b90: 40020410 .word 0x40020410 8011b94: 40020428 .word 0x40020428 8011b98: 40020440 .word 0x40020440 8011b9c: 40020458 .word 0x40020458 8011ba0: 40020470 .word 0x40020470 8011ba4: 40020488 .word 0x40020488 8011ba8: 400204a0 .word 0x400204a0 8011bac: 400204b8 .word 0x400204b8 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8011bb0: 687b ldr r3, [r7, #4] 8011bb2: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 8011bb6: 687b ldr r3, [r7, #4] 8011bb8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011bbc: b29b uxth r3, r3 8011bbe: 1ad3 subs r3, r2, r3 8011bc0: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8011bc4: 687b ldr r3, [r7, #4] 8011bc6: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011bca: b29b uxth r3, r3 8011bcc: 2b00 cmp r3, #0 8011bce: f000 80cf beq.w 8011d70 && (nb_rx_data > 0U)) 8011bd2: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8011bd6: 2b00 cmp r3, #0 8011bd8: f000 80ca beq.w 8011d70 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8011bdc: 687b ldr r3, [r7, #4] 8011bde: 681b ldr r3, [r3, #0] 8011be0: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011be2: 6bbb ldr r3, [r7, #56] @ 0x38 8011be4: e853 3f00 ldrex r3, [r3] 8011be8: 637b str r3, [r7, #52] @ 0x34 return(result); 8011bea: 6b7b ldr r3, [r7, #52] @ 0x34 8011bec: f423 7390 bic.w r3, r3, #288 @ 0x120 8011bf0: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8011bf4: 687b ldr r3, [r7, #4] 8011bf6: 681b ldr r3, [r3, #0] 8011bf8: 461a mov r2, r3 8011bfa: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 8011bfe: 647b str r3, [r7, #68] @ 0x44 8011c00: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011c02: 6c39 ldr r1, [r7, #64] @ 0x40 8011c04: 6c7a ldr r2, [r7, #68] @ 0x44 8011c06: e841 2300 strex r3, r2, [r1] 8011c0a: 63fb str r3, [r7, #60] @ 0x3c return(result); 8011c0c: 6bfb ldr r3, [r7, #60] @ 0x3c 8011c0e: 2b00 cmp r3, #0 8011c10: d1e4 bne.n 8011bdc /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8011c12: 687b ldr r3, [r7, #4] 8011c14: 681b ldr r3, [r3, #0] 8011c16: 3308 adds r3, #8 8011c18: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011c1a: 6a7b ldr r3, [r7, #36] @ 0x24 8011c1c: e853 3f00 ldrex r3, [r3] 8011c20: 623b str r3, [r7, #32] return(result); 8011c22: 6a3a ldr r2, [r7, #32] 8011c24: 4b55 ldr r3, [pc, #340] @ (8011d7c ) 8011c26: 4013 ands r3, r2 8011c28: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8011c2c: 687b ldr r3, [r7, #4] 8011c2e: 681b ldr r3, [r3, #0] 8011c30: 3308 adds r3, #8 8011c32: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8011c36: 633a str r2, [r7, #48] @ 0x30 8011c38: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011c3a: 6af9 ldr r1, [r7, #44] @ 0x2c 8011c3c: 6b3a ldr r2, [r7, #48] @ 0x30 8011c3e: e841 2300 strex r3, r2, [r1] 8011c42: 62bb str r3, [r7, #40] @ 0x28 return(result); 8011c44: 6abb ldr r3, [r7, #40] @ 0x28 8011c46: 2b00 cmp r3, #0 8011c48: d1e3 bne.n 8011c12 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8011c4a: 687b ldr r3, [r7, #4] 8011c4c: 2220 movs r2, #32 8011c4e: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8011c52: 687b ldr r3, [r7, #4] 8011c54: 2200 movs r2, #0 8011c56: 66da str r2, [r3, #108] @ 0x6c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8011c58: 687b ldr r3, [r7, #4] 8011c5a: 2200 movs r2, #0 8011c5c: 675a str r2, [r3, #116] @ 0x74 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8011c5e: 687b ldr r3, [r7, #4] 8011c60: 681b ldr r3, [r3, #0] 8011c62: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011c64: 693b ldr r3, [r7, #16] 8011c66: e853 3f00 ldrex r3, [r3] 8011c6a: 60fb str r3, [r7, #12] return(result); 8011c6c: 68fb ldr r3, [r7, #12] 8011c6e: f023 0310 bic.w r3, r3, #16 8011c72: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8011c76: 687b ldr r3, [r7, #4] 8011c78: 681b ldr r3, [r3, #0] 8011c7a: 461a mov r2, r3 8011c7c: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 8011c80: 61fb str r3, [r7, #28] 8011c82: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011c84: 69b9 ldr r1, [r7, #24] 8011c86: 69fa ldr r2, [r7, #28] 8011c88: e841 2300 strex r3, r2, [r1] 8011c8c: 617b str r3, [r7, #20] return(result); 8011c8e: 697b ldr r3, [r7, #20] 8011c90: 2b00 cmp r3, #0 8011c92: d1e4 bne.n 8011c5e /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8011c94: 687b ldr r3, [r7, #4] 8011c96: 2202 movs r2, #2 8011c98: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8011c9a: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8011c9e: 4619 mov r1, r3 8011ca0: 6878 ldr r0, [r7, #4] 8011ca2: f7f2 ff63 bl 8004b6c #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 8011ca6: e063 b.n 8011d70 } } /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) 8011ca8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011cac: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8011cb0: 2b00 cmp r3, #0 8011cb2: d00e beq.n 8011cd2 8011cb4: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011cb8: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8011cbc: 2b00 cmp r3, #0 8011cbe: d008 beq.n 8011cd2 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); 8011cc0: 687b ldr r3, [r7, #4] 8011cc2: 681b ldr r3, [r3, #0] 8011cc4: f44f 1280 mov.w r2, #1048576 @ 0x100000 8011cc8: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Wakeup Callback */ huart->WakeupCallback(huart); #else /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); 8011cca: 6878 ldr r0, [r7, #4] 8011ccc: f002 f80c bl 8013ce8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8011cd0: e051 b.n 8011d76 } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) 8011cd2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011cd6: f003 0380 and.w r3, r3, #128 @ 0x80 8011cda: 2b00 cmp r3, #0 8011cdc: d014 beq.n 8011d08 && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) 8011cde: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011ce2: f003 0380 and.w r3, r3, #128 @ 0x80 8011ce6: 2b00 cmp r3, #0 8011ce8: d105 bne.n 8011cf6 || ((cr3its & USART_CR3_TXFTIE) != 0U))) 8011cea: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011cee: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8011cf2: 2b00 cmp r3, #0 8011cf4: d008 beq.n 8011d08 { if (huart->TxISR != NULL) 8011cf6: 687b ldr r3, [r7, #4] 8011cf8: 6f9b ldr r3, [r3, #120] @ 0x78 8011cfa: 2b00 cmp r3, #0 8011cfc: d03a beq.n 8011d74 { huart->TxISR(huart); 8011cfe: 687b ldr r3, [r7, #4] 8011d00: 6f9b ldr r3, [r3, #120] @ 0x78 8011d02: 6878 ldr r0, [r7, #4] 8011d04: 4798 blx r3 } return; 8011d06: e035 b.n 8011d74 } /* UART in mode Transmitter (transmission end) -----------------------------*/ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) 8011d08: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011d0c: f003 0340 and.w r3, r3, #64 @ 0x40 8011d10: 2b00 cmp r3, #0 8011d12: d009 beq.n 8011d28 8011d14: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011d18: f003 0340 and.w r3, r3, #64 @ 0x40 8011d1c: 2b00 cmp r3, #0 8011d1e: d003 beq.n 8011d28 { UART_EndTransmit_IT(huart); 8011d20: 6878 ldr r0, [r7, #4] 8011d22: f001 fa99 bl 8013258 return; 8011d26: e026 b.n 8011d76 } /* UART TX Fifo Empty occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) 8011d28: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011d2c: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8011d30: 2b00 cmp r3, #0 8011d32: d009 beq.n 8011d48 8011d34: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011d38: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 8011d3c: 2b00 cmp r3, #0 8011d3e: d003 beq.n 8011d48 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ huart->TxFifoEmptyCallback(huart); #else /* Call legacy weak Tx Fifo Empty Callback */ HAL_UARTEx_TxFifoEmptyCallback(huart); 8011d40: 6878 ldr r0, [r7, #4] 8011d42: f001 ffe5 bl 8013d10 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8011d46: e016 b.n 8011d76 } /* UART RX Fifo Full occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) 8011d48: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011d4c: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8011d50: 2b00 cmp r3, #0 8011d52: d010 beq.n 8011d76 8011d54: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011d58: 2b00 cmp r3, #0 8011d5a: da0c bge.n 8011d76 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ huart->RxFifoFullCallback(huart); #else /* Call legacy weak Rx Fifo Full Callback */ HAL_UARTEx_RxFifoFullCallback(huart); 8011d5c: 6878 ldr r0, [r7, #4] 8011d5e: f001 ffcd bl 8013cfc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8011d62: e008 b.n 8011d76 return; 8011d64: bf00 nop 8011d66: e006 b.n 8011d76 return; 8011d68: bf00 nop 8011d6a: e004 b.n 8011d76 return; 8011d6c: bf00 nop 8011d6e: e002 b.n 8011d76 return; 8011d70: bf00 nop 8011d72: e000 b.n 8011d76 return; 8011d74: bf00 nop } } 8011d76: 37e8 adds r7, #232 @ 0xe8 8011d78: 46bd mov sp, r7 8011d7a: bd80 pop {r7, pc} 8011d7c: effffffe .word 0xeffffffe 08011d80 : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8011d80: b480 push {r7} 8011d82: b083 sub sp, #12 8011d84: af00 add r7, sp, #0 8011d86: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } 8011d88: bf00 nop 8011d8a: 370c adds r7, #12 8011d8c: 46bd mov sp, r7 8011d8e: f85d 7b04 ldr.w r7, [sp], #4 8011d92: 4770 bx lr 08011d94 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 8011d94: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8011d98: b092 sub sp, #72 @ 0x48 8011d9a: af00 add r7, sp, #0 8011d9c: 6178 str r0, [r7, #20] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 8011d9e: 2300 movs r3, #0 8011da0: f887 3042 strb.w r3, [r7, #66] @ 0x42 * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 8011da4: 697b ldr r3, [r7, #20] 8011da6: 689a ldr r2, [r3, #8] 8011da8: 697b ldr r3, [r7, #20] 8011daa: 691b ldr r3, [r3, #16] 8011dac: 431a orrs r2, r3 8011dae: 697b ldr r3, [r7, #20] 8011db0: 695b ldr r3, [r3, #20] 8011db2: 431a orrs r2, r3 8011db4: 697b ldr r3, [r7, #20] 8011db6: 69db ldr r3, [r3, #28] 8011db8: 4313 orrs r3, r2 8011dba: 647b str r3, [r7, #68] @ 0x44 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 8011dbc: 697b ldr r3, [r7, #20] 8011dbe: 681b ldr r3, [r3, #0] 8011dc0: 681a ldr r2, [r3, #0] 8011dc2: 4bbe ldr r3, [pc, #760] @ (80120bc ) 8011dc4: 4013 ands r3, r2 8011dc6: 697a ldr r2, [r7, #20] 8011dc8: 6812 ldr r2, [r2, #0] 8011dca: 6c79 ldr r1, [r7, #68] @ 0x44 8011dcc: 430b orrs r3, r1 8011dce: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8011dd0: 697b ldr r3, [r7, #20] 8011dd2: 681b ldr r3, [r3, #0] 8011dd4: 685b ldr r3, [r3, #4] 8011dd6: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8011dda: 697b ldr r3, [r7, #20] 8011ddc: 68da ldr r2, [r3, #12] 8011dde: 697b ldr r3, [r7, #20] 8011de0: 681b ldr r3, [r3, #0] 8011de2: 430a orrs r2, r1 8011de4: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 8011de6: 697b ldr r3, [r7, #20] 8011de8: 699b ldr r3, [r3, #24] 8011dea: 647b str r3, [r7, #68] @ 0x44 if (!(UART_INSTANCE_LOWPOWER(huart))) 8011dec: 697b ldr r3, [r7, #20] 8011dee: 681b ldr r3, [r3, #0] 8011df0: 4ab3 ldr r2, [pc, #716] @ (80120c0 ) 8011df2: 4293 cmp r3, r2 8011df4: d004 beq.n 8011e00 { tmpreg |= huart->Init.OneBitSampling; 8011df6: 697b ldr r3, [r7, #20] 8011df8: 6a1b ldr r3, [r3, #32] 8011dfa: 6c7a ldr r2, [r7, #68] @ 0x44 8011dfc: 4313 orrs r3, r2 8011dfe: 647b str r3, [r7, #68] @ 0x44 } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 8011e00: 697b ldr r3, [r7, #20] 8011e02: 681b ldr r3, [r3, #0] 8011e04: 689a ldr r2, [r3, #8] 8011e06: 4baf ldr r3, [pc, #700] @ (80120c4 ) 8011e08: 4013 ands r3, r2 8011e0a: 697a ldr r2, [r7, #20] 8011e0c: 6812 ldr r2, [r2, #0] 8011e0e: 6c79 ldr r1, [r7, #68] @ 0x44 8011e10: 430b orrs r3, r1 8011e12: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 8011e14: 697b ldr r3, [r7, #20] 8011e16: 681b ldr r3, [r3, #0] 8011e18: 6adb ldr r3, [r3, #44] @ 0x2c 8011e1a: f023 010f bic.w r1, r3, #15 8011e1e: 697b ldr r3, [r7, #20] 8011e20: 6a5a ldr r2, [r3, #36] @ 0x24 8011e22: 697b ldr r3, [r7, #20] 8011e24: 681b ldr r3, [r3, #0] 8011e26: 430a orrs r2, r1 8011e28: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 8011e2a: 697b ldr r3, [r7, #20] 8011e2c: 681b ldr r3, [r3, #0] 8011e2e: 4aa6 ldr r2, [pc, #664] @ (80120c8 ) 8011e30: 4293 cmp r3, r2 8011e32: d177 bne.n 8011f24 8011e34: 4ba5 ldr r3, [pc, #660] @ (80120cc ) 8011e36: 6d5b ldr r3, [r3, #84] @ 0x54 8011e38: f003 0338 and.w r3, r3, #56 @ 0x38 8011e3c: 2b28 cmp r3, #40 @ 0x28 8011e3e: d86d bhi.n 8011f1c 8011e40: a201 add r2, pc, #4 @ (adr r2, 8011e48 ) 8011e42: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011e46: bf00 nop 8011e48: 08011eed .word 0x08011eed 8011e4c: 08011f1d .word 0x08011f1d 8011e50: 08011f1d .word 0x08011f1d 8011e54: 08011f1d .word 0x08011f1d 8011e58: 08011f1d .word 0x08011f1d 8011e5c: 08011f1d .word 0x08011f1d 8011e60: 08011f1d .word 0x08011f1d 8011e64: 08011f1d .word 0x08011f1d 8011e68: 08011ef5 .word 0x08011ef5 8011e6c: 08011f1d .word 0x08011f1d 8011e70: 08011f1d .word 0x08011f1d 8011e74: 08011f1d .word 0x08011f1d 8011e78: 08011f1d .word 0x08011f1d 8011e7c: 08011f1d .word 0x08011f1d 8011e80: 08011f1d .word 0x08011f1d 8011e84: 08011f1d .word 0x08011f1d 8011e88: 08011efd .word 0x08011efd 8011e8c: 08011f1d .word 0x08011f1d 8011e90: 08011f1d .word 0x08011f1d 8011e94: 08011f1d .word 0x08011f1d 8011e98: 08011f1d .word 0x08011f1d 8011e9c: 08011f1d .word 0x08011f1d 8011ea0: 08011f1d .word 0x08011f1d 8011ea4: 08011f1d .word 0x08011f1d 8011ea8: 08011f05 .word 0x08011f05 8011eac: 08011f1d .word 0x08011f1d 8011eb0: 08011f1d .word 0x08011f1d 8011eb4: 08011f1d .word 0x08011f1d 8011eb8: 08011f1d .word 0x08011f1d 8011ebc: 08011f1d .word 0x08011f1d 8011ec0: 08011f1d .word 0x08011f1d 8011ec4: 08011f1d .word 0x08011f1d 8011ec8: 08011f0d .word 0x08011f0d 8011ecc: 08011f1d .word 0x08011f1d 8011ed0: 08011f1d .word 0x08011f1d 8011ed4: 08011f1d .word 0x08011f1d 8011ed8: 08011f1d .word 0x08011f1d 8011edc: 08011f1d .word 0x08011f1d 8011ee0: 08011f1d .word 0x08011f1d 8011ee4: 08011f1d .word 0x08011f1d 8011ee8: 08011f15 .word 0x08011f15 8011eec: 2301 movs r3, #1 8011eee: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ef2: e222 b.n 801233a 8011ef4: 2304 movs r3, #4 8011ef6: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011efa: e21e b.n 801233a 8011efc: 2308 movs r3, #8 8011efe: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f02: e21a b.n 801233a 8011f04: 2310 movs r3, #16 8011f06: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f0a: e216 b.n 801233a 8011f0c: 2320 movs r3, #32 8011f0e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f12: e212 b.n 801233a 8011f14: 2340 movs r3, #64 @ 0x40 8011f16: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f1a: e20e b.n 801233a 8011f1c: 2380 movs r3, #128 @ 0x80 8011f1e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f22: e20a b.n 801233a 8011f24: 697b ldr r3, [r7, #20] 8011f26: 681b ldr r3, [r3, #0] 8011f28: 4a69 ldr r2, [pc, #420] @ (80120d0 ) 8011f2a: 4293 cmp r3, r2 8011f2c: d130 bne.n 8011f90 8011f2e: 4b67 ldr r3, [pc, #412] @ (80120cc ) 8011f30: 6d5b ldr r3, [r3, #84] @ 0x54 8011f32: f003 0307 and.w r3, r3, #7 8011f36: 2b05 cmp r3, #5 8011f38: d826 bhi.n 8011f88 8011f3a: a201 add r2, pc, #4 @ (adr r2, 8011f40 ) 8011f3c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011f40: 08011f59 .word 0x08011f59 8011f44: 08011f61 .word 0x08011f61 8011f48: 08011f69 .word 0x08011f69 8011f4c: 08011f71 .word 0x08011f71 8011f50: 08011f79 .word 0x08011f79 8011f54: 08011f81 .word 0x08011f81 8011f58: 2300 movs r3, #0 8011f5a: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f5e: e1ec b.n 801233a 8011f60: 2304 movs r3, #4 8011f62: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f66: e1e8 b.n 801233a 8011f68: 2308 movs r3, #8 8011f6a: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f6e: e1e4 b.n 801233a 8011f70: 2310 movs r3, #16 8011f72: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f76: e1e0 b.n 801233a 8011f78: 2320 movs r3, #32 8011f7a: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f7e: e1dc b.n 801233a 8011f80: 2340 movs r3, #64 @ 0x40 8011f82: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f86: e1d8 b.n 801233a 8011f88: 2380 movs r3, #128 @ 0x80 8011f8a: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f8e: e1d4 b.n 801233a 8011f90: 697b ldr r3, [r7, #20] 8011f92: 681b ldr r3, [r3, #0] 8011f94: 4a4f ldr r2, [pc, #316] @ (80120d4 ) 8011f96: 4293 cmp r3, r2 8011f98: d130 bne.n 8011ffc 8011f9a: 4b4c ldr r3, [pc, #304] @ (80120cc ) 8011f9c: 6d5b ldr r3, [r3, #84] @ 0x54 8011f9e: f003 0307 and.w r3, r3, #7 8011fa2: 2b05 cmp r3, #5 8011fa4: d826 bhi.n 8011ff4 8011fa6: a201 add r2, pc, #4 @ (adr r2, 8011fac ) 8011fa8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011fac: 08011fc5 .word 0x08011fc5 8011fb0: 08011fcd .word 0x08011fcd 8011fb4: 08011fd5 .word 0x08011fd5 8011fb8: 08011fdd .word 0x08011fdd 8011fbc: 08011fe5 .word 0x08011fe5 8011fc0: 08011fed .word 0x08011fed 8011fc4: 2300 movs r3, #0 8011fc6: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fca: e1b6 b.n 801233a 8011fcc: 2304 movs r3, #4 8011fce: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fd2: e1b2 b.n 801233a 8011fd4: 2308 movs r3, #8 8011fd6: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fda: e1ae b.n 801233a 8011fdc: 2310 movs r3, #16 8011fde: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fe2: e1aa b.n 801233a 8011fe4: 2320 movs r3, #32 8011fe6: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fea: e1a6 b.n 801233a 8011fec: 2340 movs r3, #64 @ 0x40 8011fee: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ff2: e1a2 b.n 801233a 8011ff4: 2380 movs r3, #128 @ 0x80 8011ff6: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ffa: e19e b.n 801233a 8011ffc: 697b ldr r3, [r7, #20] 8011ffe: 681b ldr r3, [r3, #0] 8012000: 4a35 ldr r2, [pc, #212] @ (80120d8 ) 8012002: 4293 cmp r3, r2 8012004: d130 bne.n 8012068 8012006: 4b31 ldr r3, [pc, #196] @ (80120cc ) 8012008: 6d5b ldr r3, [r3, #84] @ 0x54 801200a: f003 0307 and.w r3, r3, #7 801200e: 2b05 cmp r3, #5 8012010: d826 bhi.n 8012060 8012012: a201 add r2, pc, #4 @ (adr r2, 8012018 ) 8012014: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012018: 08012031 .word 0x08012031 801201c: 08012039 .word 0x08012039 8012020: 08012041 .word 0x08012041 8012024: 08012049 .word 0x08012049 8012028: 08012051 .word 0x08012051 801202c: 08012059 .word 0x08012059 8012030: 2300 movs r3, #0 8012032: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012036: e180 b.n 801233a 8012038: 2304 movs r3, #4 801203a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801203e: e17c b.n 801233a 8012040: 2308 movs r3, #8 8012042: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012046: e178 b.n 801233a 8012048: 2310 movs r3, #16 801204a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801204e: e174 b.n 801233a 8012050: 2320 movs r3, #32 8012052: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012056: e170 b.n 801233a 8012058: 2340 movs r3, #64 @ 0x40 801205a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801205e: e16c b.n 801233a 8012060: 2380 movs r3, #128 @ 0x80 8012062: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012066: e168 b.n 801233a 8012068: 697b ldr r3, [r7, #20] 801206a: 681b ldr r3, [r3, #0] 801206c: 4a1b ldr r2, [pc, #108] @ (80120dc ) 801206e: 4293 cmp r3, r2 8012070: d142 bne.n 80120f8 8012072: 4b16 ldr r3, [pc, #88] @ (80120cc ) 8012074: 6d5b ldr r3, [r3, #84] @ 0x54 8012076: f003 0307 and.w r3, r3, #7 801207a: 2b05 cmp r3, #5 801207c: d838 bhi.n 80120f0 801207e: a201 add r2, pc, #4 @ (adr r2, 8012084 ) 8012080: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012084: 0801209d .word 0x0801209d 8012088: 080120a5 .word 0x080120a5 801208c: 080120ad .word 0x080120ad 8012090: 080120b5 .word 0x080120b5 8012094: 080120e1 .word 0x080120e1 8012098: 080120e9 .word 0x080120e9 801209c: 2300 movs r3, #0 801209e: f887 3043 strb.w r3, [r7, #67] @ 0x43 80120a2: e14a b.n 801233a 80120a4: 2304 movs r3, #4 80120a6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80120aa: e146 b.n 801233a 80120ac: 2308 movs r3, #8 80120ae: f887 3043 strb.w r3, [r7, #67] @ 0x43 80120b2: e142 b.n 801233a 80120b4: 2310 movs r3, #16 80120b6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80120ba: e13e b.n 801233a 80120bc: cfff69f3 .word 0xcfff69f3 80120c0: 58000c00 .word 0x58000c00 80120c4: 11fff4ff .word 0x11fff4ff 80120c8: 40011000 .word 0x40011000 80120cc: 58024400 .word 0x58024400 80120d0: 40004400 .word 0x40004400 80120d4: 40004800 .word 0x40004800 80120d8: 40004c00 .word 0x40004c00 80120dc: 40005000 .word 0x40005000 80120e0: 2320 movs r3, #32 80120e2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80120e6: e128 b.n 801233a 80120e8: 2340 movs r3, #64 @ 0x40 80120ea: f887 3043 strb.w r3, [r7, #67] @ 0x43 80120ee: e124 b.n 801233a 80120f0: 2380 movs r3, #128 @ 0x80 80120f2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80120f6: e120 b.n 801233a 80120f8: 697b ldr r3, [r7, #20] 80120fa: 681b ldr r3, [r3, #0] 80120fc: 4acb ldr r2, [pc, #812] @ (801242c ) 80120fe: 4293 cmp r3, r2 8012100: d176 bne.n 80121f0 8012102: 4bcb ldr r3, [pc, #812] @ (8012430 ) 8012104: 6d5b ldr r3, [r3, #84] @ 0x54 8012106: f003 0338 and.w r3, r3, #56 @ 0x38 801210a: 2b28 cmp r3, #40 @ 0x28 801210c: d86c bhi.n 80121e8 801210e: a201 add r2, pc, #4 @ (adr r2, 8012114 ) 8012110: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012114: 080121b9 .word 0x080121b9 8012118: 080121e9 .word 0x080121e9 801211c: 080121e9 .word 0x080121e9 8012120: 080121e9 .word 0x080121e9 8012124: 080121e9 .word 0x080121e9 8012128: 080121e9 .word 0x080121e9 801212c: 080121e9 .word 0x080121e9 8012130: 080121e9 .word 0x080121e9 8012134: 080121c1 .word 0x080121c1 8012138: 080121e9 .word 0x080121e9 801213c: 080121e9 .word 0x080121e9 8012140: 080121e9 .word 0x080121e9 8012144: 080121e9 .word 0x080121e9 8012148: 080121e9 .word 0x080121e9 801214c: 080121e9 .word 0x080121e9 8012150: 080121e9 .word 0x080121e9 8012154: 080121c9 .word 0x080121c9 8012158: 080121e9 .word 0x080121e9 801215c: 080121e9 .word 0x080121e9 8012160: 080121e9 .word 0x080121e9 8012164: 080121e9 .word 0x080121e9 8012168: 080121e9 .word 0x080121e9 801216c: 080121e9 .word 0x080121e9 8012170: 080121e9 .word 0x080121e9 8012174: 080121d1 .word 0x080121d1 8012178: 080121e9 .word 0x080121e9 801217c: 080121e9 .word 0x080121e9 8012180: 080121e9 .word 0x080121e9 8012184: 080121e9 .word 0x080121e9 8012188: 080121e9 .word 0x080121e9 801218c: 080121e9 .word 0x080121e9 8012190: 080121e9 .word 0x080121e9 8012194: 080121d9 .word 0x080121d9 8012198: 080121e9 .word 0x080121e9 801219c: 080121e9 .word 0x080121e9 80121a0: 080121e9 .word 0x080121e9 80121a4: 080121e9 .word 0x080121e9 80121a8: 080121e9 .word 0x080121e9 80121ac: 080121e9 .word 0x080121e9 80121b0: 080121e9 .word 0x080121e9 80121b4: 080121e1 .word 0x080121e1 80121b8: 2301 movs r3, #1 80121ba: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121be: e0bc b.n 801233a 80121c0: 2304 movs r3, #4 80121c2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121c6: e0b8 b.n 801233a 80121c8: 2308 movs r3, #8 80121ca: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121ce: e0b4 b.n 801233a 80121d0: 2310 movs r3, #16 80121d2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121d6: e0b0 b.n 801233a 80121d8: 2320 movs r3, #32 80121da: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121de: e0ac b.n 801233a 80121e0: 2340 movs r3, #64 @ 0x40 80121e2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121e6: e0a8 b.n 801233a 80121e8: 2380 movs r3, #128 @ 0x80 80121ea: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121ee: e0a4 b.n 801233a 80121f0: 697b ldr r3, [r7, #20] 80121f2: 681b ldr r3, [r3, #0] 80121f4: 4a8f ldr r2, [pc, #572] @ (8012434 ) 80121f6: 4293 cmp r3, r2 80121f8: d130 bne.n 801225c 80121fa: 4b8d ldr r3, [pc, #564] @ (8012430 ) 80121fc: 6d5b ldr r3, [r3, #84] @ 0x54 80121fe: f003 0307 and.w r3, r3, #7 8012202: 2b05 cmp r3, #5 8012204: d826 bhi.n 8012254 8012206: a201 add r2, pc, #4 @ (adr r2, 801220c ) 8012208: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801220c: 08012225 .word 0x08012225 8012210: 0801222d .word 0x0801222d 8012214: 08012235 .word 0x08012235 8012218: 0801223d .word 0x0801223d 801221c: 08012245 .word 0x08012245 8012220: 0801224d .word 0x0801224d 8012224: 2300 movs r3, #0 8012226: f887 3043 strb.w r3, [r7, #67] @ 0x43 801222a: e086 b.n 801233a 801222c: 2304 movs r3, #4 801222e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012232: e082 b.n 801233a 8012234: 2308 movs r3, #8 8012236: f887 3043 strb.w r3, [r7, #67] @ 0x43 801223a: e07e b.n 801233a 801223c: 2310 movs r3, #16 801223e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012242: e07a b.n 801233a 8012244: 2320 movs r3, #32 8012246: f887 3043 strb.w r3, [r7, #67] @ 0x43 801224a: e076 b.n 801233a 801224c: 2340 movs r3, #64 @ 0x40 801224e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012252: e072 b.n 801233a 8012254: 2380 movs r3, #128 @ 0x80 8012256: f887 3043 strb.w r3, [r7, #67] @ 0x43 801225a: e06e b.n 801233a 801225c: 697b ldr r3, [r7, #20] 801225e: 681b ldr r3, [r3, #0] 8012260: 4a75 ldr r2, [pc, #468] @ (8012438 ) 8012262: 4293 cmp r3, r2 8012264: d130 bne.n 80122c8 8012266: 4b72 ldr r3, [pc, #456] @ (8012430 ) 8012268: 6d5b ldr r3, [r3, #84] @ 0x54 801226a: f003 0307 and.w r3, r3, #7 801226e: 2b05 cmp r3, #5 8012270: d826 bhi.n 80122c0 8012272: a201 add r2, pc, #4 @ (adr r2, 8012278 ) 8012274: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012278: 08012291 .word 0x08012291 801227c: 08012299 .word 0x08012299 8012280: 080122a1 .word 0x080122a1 8012284: 080122a9 .word 0x080122a9 8012288: 080122b1 .word 0x080122b1 801228c: 080122b9 .word 0x080122b9 8012290: 2300 movs r3, #0 8012292: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012296: e050 b.n 801233a 8012298: 2304 movs r3, #4 801229a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801229e: e04c b.n 801233a 80122a0: 2308 movs r3, #8 80122a2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80122a6: e048 b.n 801233a 80122a8: 2310 movs r3, #16 80122aa: f887 3043 strb.w r3, [r7, #67] @ 0x43 80122ae: e044 b.n 801233a 80122b0: 2320 movs r3, #32 80122b2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80122b6: e040 b.n 801233a 80122b8: 2340 movs r3, #64 @ 0x40 80122ba: f887 3043 strb.w r3, [r7, #67] @ 0x43 80122be: e03c b.n 801233a 80122c0: 2380 movs r3, #128 @ 0x80 80122c2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80122c6: e038 b.n 801233a 80122c8: 697b ldr r3, [r7, #20] 80122ca: 681b ldr r3, [r3, #0] 80122cc: 4a5b ldr r2, [pc, #364] @ (801243c ) 80122ce: 4293 cmp r3, r2 80122d0: d130 bne.n 8012334 80122d2: 4b57 ldr r3, [pc, #348] @ (8012430 ) 80122d4: 6d9b ldr r3, [r3, #88] @ 0x58 80122d6: f003 0307 and.w r3, r3, #7 80122da: 2b05 cmp r3, #5 80122dc: d826 bhi.n 801232c 80122de: a201 add r2, pc, #4 @ (adr r2, 80122e4 ) 80122e0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80122e4: 080122fd .word 0x080122fd 80122e8: 08012305 .word 0x08012305 80122ec: 0801230d .word 0x0801230d 80122f0: 08012315 .word 0x08012315 80122f4: 0801231d .word 0x0801231d 80122f8: 08012325 .word 0x08012325 80122fc: 2302 movs r3, #2 80122fe: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012302: e01a b.n 801233a 8012304: 2304 movs r3, #4 8012306: f887 3043 strb.w r3, [r7, #67] @ 0x43 801230a: e016 b.n 801233a 801230c: 2308 movs r3, #8 801230e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012312: e012 b.n 801233a 8012314: 2310 movs r3, #16 8012316: f887 3043 strb.w r3, [r7, #67] @ 0x43 801231a: e00e b.n 801233a 801231c: 2320 movs r3, #32 801231e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012322: e00a b.n 801233a 8012324: 2340 movs r3, #64 @ 0x40 8012326: f887 3043 strb.w r3, [r7, #67] @ 0x43 801232a: e006 b.n 801233a 801232c: 2380 movs r3, #128 @ 0x80 801232e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012332: e002 b.n 801233a 8012334: 2380 movs r3, #128 @ 0x80 8012336: f887 3043 strb.w r3, [r7, #67] @ 0x43 /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 801233a: 697b ldr r3, [r7, #20] 801233c: 681b ldr r3, [r3, #0] 801233e: 4a3f ldr r2, [pc, #252] @ (801243c ) 8012340: 4293 cmp r3, r2 8012342: f040 80f8 bne.w 8012536 { /* Retrieve frequency clock */ switch (clocksource) 8012346: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 801234a: 2b20 cmp r3, #32 801234c: dc46 bgt.n 80123dc 801234e: 2b02 cmp r3, #2 8012350: f2c0 8082 blt.w 8012458 8012354: 3b02 subs r3, #2 8012356: 2b1e cmp r3, #30 8012358: d87e bhi.n 8012458 801235a: a201 add r2, pc, #4 @ (adr r2, 8012360 ) 801235c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012360: 080123e3 .word 0x080123e3 8012364: 08012459 .word 0x08012459 8012368: 080123eb .word 0x080123eb 801236c: 08012459 .word 0x08012459 8012370: 08012459 .word 0x08012459 8012374: 08012459 .word 0x08012459 8012378: 080123fb .word 0x080123fb 801237c: 08012459 .word 0x08012459 8012380: 08012459 .word 0x08012459 8012384: 08012459 .word 0x08012459 8012388: 08012459 .word 0x08012459 801238c: 08012459 .word 0x08012459 8012390: 08012459 .word 0x08012459 8012394: 08012459 .word 0x08012459 8012398: 0801240b .word 0x0801240b 801239c: 08012459 .word 0x08012459 80123a0: 08012459 .word 0x08012459 80123a4: 08012459 .word 0x08012459 80123a8: 08012459 .word 0x08012459 80123ac: 08012459 .word 0x08012459 80123b0: 08012459 .word 0x08012459 80123b4: 08012459 .word 0x08012459 80123b8: 08012459 .word 0x08012459 80123bc: 08012459 .word 0x08012459 80123c0: 08012459 .word 0x08012459 80123c4: 08012459 .word 0x08012459 80123c8: 08012459 .word 0x08012459 80123cc: 08012459 .word 0x08012459 80123d0: 08012459 .word 0x08012459 80123d4: 08012459 .word 0x08012459 80123d8: 0801244b .word 0x0801244b 80123dc: 2b40 cmp r3, #64 @ 0x40 80123de: d037 beq.n 8012450 80123e0: e03a b.n 8012458 { case UART_CLOCKSOURCE_D3PCLK1: pclk = HAL_RCCEx_GetD3PCLK1Freq(); 80123e2: f7fc fa8b bl 800e8fc 80123e6: 63f8 str r0, [r7, #60] @ 0x3c break; 80123e8: e03c b.n 8012464 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80123ea: f107 0324 add.w r3, r7, #36 @ 0x24 80123ee: 4618 mov r0, r3 80123f0: f7fc fa9a bl 800e928 pclk = pll2_clocks.PLL2_Q_Frequency; 80123f4: 6abb ldr r3, [r7, #40] @ 0x28 80123f6: 63fb str r3, [r7, #60] @ 0x3c break; 80123f8: e034 b.n 8012464 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 80123fa: f107 0318 add.w r3, r7, #24 80123fe: 4618 mov r0, r3 8012400: f7fc fbe6 bl 800ebd0 pclk = pll3_clocks.PLL3_Q_Frequency; 8012404: 69fb ldr r3, [r7, #28] 8012406: 63fb str r3, [r7, #60] @ 0x3c break; 8012408: e02c b.n 8012464 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 801240a: 4b09 ldr r3, [pc, #36] @ (8012430 ) 801240c: 681b ldr r3, [r3, #0] 801240e: f003 0320 and.w r3, r3, #32 8012412: 2b00 cmp r3, #0 8012414: d016 beq.n 8012444 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8012416: 4b06 ldr r3, [pc, #24] @ (8012430 ) 8012418: 681b ldr r3, [r3, #0] 801241a: 08db lsrs r3, r3, #3 801241c: f003 0303 and.w r3, r3, #3 8012420: 4a07 ldr r2, [pc, #28] @ (8012440 ) 8012422: fa22 f303 lsr.w r3, r2, r3 8012426: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8012428: e01c b.n 8012464 801242a: bf00 nop 801242c: 40011400 .word 0x40011400 8012430: 58024400 .word 0x58024400 8012434: 40007800 .word 0x40007800 8012438: 40007c00 .word 0x40007c00 801243c: 58000c00 .word 0x58000c00 8012440: 03d09000 .word 0x03d09000 pclk = (uint32_t) HSI_VALUE; 8012444: 4b9d ldr r3, [pc, #628] @ (80126bc ) 8012446: 63fb str r3, [r7, #60] @ 0x3c break; 8012448: e00c b.n 8012464 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 801244a: 4b9d ldr r3, [pc, #628] @ (80126c0 ) 801244c: 63fb str r3, [r7, #60] @ 0x3c break; 801244e: e009 b.n 8012464 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8012450: f44f 4300 mov.w r3, #32768 @ 0x8000 8012454: 63fb str r3, [r7, #60] @ 0x3c break; 8012456: e005 b.n 8012464 default: pclk = 0U; 8012458: 2300 movs r3, #0 801245a: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 801245c: 2301 movs r3, #1 801245e: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 8012462: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 8012464: 6bfb ldr r3, [r7, #60] @ 0x3c 8012466: 2b00 cmp r3, #0 8012468: f000 81de beq.w 8012828 { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 801246c: 697b ldr r3, [r7, #20] 801246e: 6a5b ldr r3, [r3, #36] @ 0x24 8012470: 4a94 ldr r2, [pc, #592] @ (80126c4 ) 8012472: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8012476: 461a mov r2, r3 8012478: 6bfb ldr r3, [r7, #60] @ 0x3c 801247a: fbb3 f3f2 udiv r3, r3, r2 801247e: 633b str r3, [r7, #48] @ 0x30 /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 8012480: 697b ldr r3, [r7, #20] 8012482: 685a ldr r2, [r3, #4] 8012484: 4613 mov r3, r2 8012486: 005b lsls r3, r3, #1 8012488: 4413 add r3, r2 801248a: 6b3a ldr r2, [r7, #48] @ 0x30 801248c: 429a cmp r2, r3 801248e: d305 bcc.n 801249c (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) 8012490: 697b ldr r3, [r7, #20] 8012492: 685b ldr r3, [r3, #4] 8012494: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 8012496: 6b3a ldr r2, [r7, #48] @ 0x30 8012498: 429a cmp r2, r3 801249a: d903 bls.n 80124a4 { ret = HAL_ERROR; 801249c: 2301 movs r3, #1 801249e: f887 3042 strb.w r3, [r7, #66] @ 0x42 80124a2: e1c1 b.n 8012828 } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 80124a4: 6bfb ldr r3, [r7, #60] @ 0x3c 80124a6: 2200 movs r2, #0 80124a8: 60bb str r3, [r7, #8] 80124aa: 60fa str r2, [r7, #12] 80124ac: 697b ldr r3, [r7, #20] 80124ae: 6a5b ldr r3, [r3, #36] @ 0x24 80124b0: 4a84 ldr r2, [pc, #528] @ (80126c4 ) 80124b2: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80124b6: b29b uxth r3, r3 80124b8: 2200 movs r2, #0 80124ba: 603b str r3, [r7, #0] 80124bc: 607a str r2, [r7, #4] 80124be: e9d7 2300 ldrd r2, r3, [r7] 80124c2: e9d7 0102 ldrd r0, r1, [r7, #8] 80124c6: f7ed ff0b bl 80002e0 <__aeabi_uldivmod> 80124ca: 4602 mov r2, r0 80124cc: 460b mov r3, r1 80124ce: 4610 mov r0, r2 80124d0: 4619 mov r1, r3 80124d2: f04f 0200 mov.w r2, #0 80124d6: f04f 0300 mov.w r3, #0 80124da: 020b lsls r3, r1, #8 80124dc: ea43 6310 orr.w r3, r3, r0, lsr #24 80124e0: 0202 lsls r2, r0, #8 80124e2: 6979 ldr r1, [r7, #20] 80124e4: 6849 ldr r1, [r1, #4] 80124e6: 0849 lsrs r1, r1, #1 80124e8: 2000 movs r0, #0 80124ea: 460c mov r4, r1 80124ec: 4605 mov r5, r0 80124ee: eb12 0804 adds.w r8, r2, r4 80124f2: eb43 0905 adc.w r9, r3, r5 80124f6: 697b ldr r3, [r7, #20] 80124f8: 685b ldr r3, [r3, #4] 80124fa: 2200 movs r2, #0 80124fc: 469a mov sl, r3 80124fe: 4693 mov fp, r2 8012500: 4652 mov r2, sl 8012502: 465b mov r3, fp 8012504: 4640 mov r0, r8 8012506: 4649 mov r1, r9 8012508: f7ed feea bl 80002e0 <__aeabi_uldivmod> 801250c: 4602 mov r2, r0 801250e: 460b mov r3, r1 8012510: 4613 mov r3, r2 8012512: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 8012514: 6bbb ldr r3, [r7, #56] @ 0x38 8012516: f5b3 7f40 cmp.w r3, #768 @ 0x300 801251a: d308 bcc.n 801252e 801251c: 6bbb ldr r3, [r7, #56] @ 0x38 801251e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8012522: d204 bcs.n 801252e { huart->Instance->BRR = usartdiv; 8012524: 697b ldr r3, [r7, #20] 8012526: 681b ldr r3, [r3, #0] 8012528: 6bba ldr r2, [r7, #56] @ 0x38 801252a: 60da str r2, [r3, #12] 801252c: e17c b.n 8012828 } else { ret = HAL_ERROR; 801252e: 2301 movs r3, #1 8012530: f887 3042 strb.w r3, [r7, #66] @ 0x42 8012534: e178 b.n 8012828 } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8012536: 697b ldr r3, [r7, #20] 8012538: 69db ldr r3, [r3, #28] 801253a: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 801253e: f040 80c5 bne.w 80126cc { switch (clocksource) 8012542: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 8012546: 2b20 cmp r3, #32 8012548: dc48 bgt.n 80125dc 801254a: 2b00 cmp r3, #0 801254c: db7b blt.n 8012646 801254e: 2b20 cmp r3, #32 8012550: d879 bhi.n 8012646 8012552: a201 add r2, pc, #4 @ (adr r2, 8012558 ) 8012554: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012558: 080125e3 .word 0x080125e3 801255c: 080125eb .word 0x080125eb 8012560: 08012647 .word 0x08012647 8012564: 08012647 .word 0x08012647 8012568: 080125f3 .word 0x080125f3 801256c: 08012647 .word 0x08012647 8012570: 08012647 .word 0x08012647 8012574: 08012647 .word 0x08012647 8012578: 08012603 .word 0x08012603 801257c: 08012647 .word 0x08012647 8012580: 08012647 .word 0x08012647 8012584: 08012647 .word 0x08012647 8012588: 08012647 .word 0x08012647 801258c: 08012647 .word 0x08012647 8012590: 08012647 .word 0x08012647 8012594: 08012647 .word 0x08012647 8012598: 08012613 .word 0x08012613 801259c: 08012647 .word 0x08012647 80125a0: 08012647 .word 0x08012647 80125a4: 08012647 .word 0x08012647 80125a8: 08012647 .word 0x08012647 80125ac: 08012647 .word 0x08012647 80125b0: 08012647 .word 0x08012647 80125b4: 08012647 .word 0x08012647 80125b8: 08012647 .word 0x08012647 80125bc: 08012647 .word 0x08012647 80125c0: 08012647 .word 0x08012647 80125c4: 08012647 .word 0x08012647 80125c8: 08012647 .word 0x08012647 80125cc: 08012647 .word 0x08012647 80125d0: 08012647 .word 0x08012647 80125d4: 08012647 .word 0x08012647 80125d8: 08012639 .word 0x08012639 80125dc: 2b40 cmp r3, #64 @ 0x40 80125de: d02e beq.n 801263e 80125e0: e031 b.n 8012646 { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 80125e2: f7fa f9af bl 800c944 80125e6: 63f8 str r0, [r7, #60] @ 0x3c break; 80125e8: e033 b.n 8012652 case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 80125ea: f7fa f9c1 bl 800c970 80125ee: 63f8 str r0, [r7, #60] @ 0x3c break; 80125f0: e02f b.n 8012652 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80125f2: f107 0324 add.w r3, r7, #36 @ 0x24 80125f6: 4618 mov r0, r3 80125f8: f7fc f996 bl 800e928 pclk = pll2_clocks.PLL2_Q_Frequency; 80125fc: 6abb ldr r3, [r7, #40] @ 0x28 80125fe: 63fb str r3, [r7, #60] @ 0x3c break; 8012600: e027 b.n 8012652 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8012602: f107 0318 add.w r3, r7, #24 8012606: 4618 mov r0, r3 8012608: f7fc fae2 bl 800ebd0 pclk = pll3_clocks.PLL3_Q_Frequency; 801260c: 69fb ldr r3, [r7, #28] 801260e: 63fb str r3, [r7, #60] @ 0x3c break; 8012610: e01f b.n 8012652 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8012612: 4b2d ldr r3, [pc, #180] @ (80126c8 ) 8012614: 681b ldr r3, [r3, #0] 8012616: f003 0320 and.w r3, r3, #32 801261a: 2b00 cmp r3, #0 801261c: d009 beq.n 8012632 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 801261e: 4b2a ldr r3, [pc, #168] @ (80126c8 ) 8012620: 681b ldr r3, [r3, #0] 8012622: 08db lsrs r3, r3, #3 8012624: f003 0303 and.w r3, r3, #3 8012628: 4a24 ldr r2, [pc, #144] @ (80126bc ) 801262a: fa22 f303 lsr.w r3, r2, r3 801262e: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8012630: e00f b.n 8012652 pclk = (uint32_t) HSI_VALUE; 8012632: 4b22 ldr r3, [pc, #136] @ (80126bc ) 8012634: 63fb str r3, [r7, #60] @ 0x3c break; 8012636: e00c b.n 8012652 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 8012638: 4b21 ldr r3, [pc, #132] @ (80126c0 ) 801263a: 63fb str r3, [r7, #60] @ 0x3c break; 801263c: e009 b.n 8012652 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 801263e: f44f 4300 mov.w r3, #32768 @ 0x8000 8012642: 63fb str r3, [r7, #60] @ 0x3c break; 8012644: e005 b.n 8012652 default: pclk = 0U; 8012646: 2300 movs r3, #0 8012648: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 801264a: 2301 movs r3, #1 801264c: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 8012650: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 8012652: 6bfb ldr r3, [r7, #60] @ 0x3c 8012654: 2b00 cmp r3, #0 8012656: f000 80e7 beq.w 8012828 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 801265a: 697b ldr r3, [r7, #20] 801265c: 6a5b ldr r3, [r3, #36] @ 0x24 801265e: 4a19 ldr r2, [pc, #100] @ (80126c4 ) 8012660: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8012664: 461a mov r2, r3 8012666: 6bfb ldr r3, [r7, #60] @ 0x3c 8012668: fbb3 f3f2 udiv r3, r3, r2 801266c: 005a lsls r2, r3, #1 801266e: 697b ldr r3, [r7, #20] 8012670: 685b ldr r3, [r3, #4] 8012672: 085b lsrs r3, r3, #1 8012674: 441a add r2, r3 8012676: 697b ldr r3, [r7, #20] 8012678: 685b ldr r3, [r3, #4] 801267a: fbb2 f3f3 udiv r3, r2, r3 801267e: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8012680: 6bbb ldr r3, [r7, #56] @ 0x38 8012682: 2b0f cmp r3, #15 8012684: d916 bls.n 80126b4 8012686: 6bbb ldr r3, [r7, #56] @ 0x38 8012688: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 801268c: d212 bcs.n 80126b4 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 801268e: 6bbb ldr r3, [r7, #56] @ 0x38 8012690: b29b uxth r3, r3 8012692: f023 030f bic.w r3, r3, #15 8012696: 86fb strh r3, [r7, #54] @ 0x36 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8012698: 6bbb ldr r3, [r7, #56] @ 0x38 801269a: 085b lsrs r3, r3, #1 801269c: b29b uxth r3, r3 801269e: f003 0307 and.w r3, r3, #7 80126a2: b29a uxth r2, r3 80126a4: 8efb ldrh r3, [r7, #54] @ 0x36 80126a6: 4313 orrs r3, r2 80126a8: 86fb strh r3, [r7, #54] @ 0x36 huart->Instance->BRR = brrtemp; 80126aa: 697b ldr r3, [r7, #20] 80126ac: 681b ldr r3, [r3, #0] 80126ae: 8efa ldrh r2, [r7, #54] @ 0x36 80126b0: 60da str r2, [r3, #12] 80126b2: e0b9 b.n 8012828 } else { ret = HAL_ERROR; 80126b4: 2301 movs r3, #1 80126b6: f887 3042 strb.w r3, [r7, #66] @ 0x42 80126ba: e0b5 b.n 8012828 80126bc: 03d09000 .word 0x03d09000 80126c0: 003d0900 .word 0x003d0900 80126c4: 080187a4 .word 0x080187a4 80126c8: 58024400 .word 0x58024400 } } } else { switch (clocksource) 80126cc: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 80126d0: 2b20 cmp r3, #32 80126d2: dc49 bgt.n 8012768 80126d4: 2b00 cmp r3, #0 80126d6: db7c blt.n 80127d2 80126d8: 2b20 cmp r3, #32 80126da: d87a bhi.n 80127d2 80126dc: a201 add r2, pc, #4 @ (adr r2, 80126e4 ) 80126de: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80126e2: bf00 nop 80126e4: 0801276f .word 0x0801276f 80126e8: 08012777 .word 0x08012777 80126ec: 080127d3 .word 0x080127d3 80126f0: 080127d3 .word 0x080127d3 80126f4: 0801277f .word 0x0801277f 80126f8: 080127d3 .word 0x080127d3 80126fc: 080127d3 .word 0x080127d3 8012700: 080127d3 .word 0x080127d3 8012704: 0801278f .word 0x0801278f 8012708: 080127d3 .word 0x080127d3 801270c: 080127d3 .word 0x080127d3 8012710: 080127d3 .word 0x080127d3 8012714: 080127d3 .word 0x080127d3 8012718: 080127d3 .word 0x080127d3 801271c: 080127d3 .word 0x080127d3 8012720: 080127d3 .word 0x080127d3 8012724: 0801279f .word 0x0801279f 8012728: 080127d3 .word 0x080127d3 801272c: 080127d3 .word 0x080127d3 8012730: 080127d3 .word 0x080127d3 8012734: 080127d3 .word 0x080127d3 8012738: 080127d3 .word 0x080127d3 801273c: 080127d3 .word 0x080127d3 8012740: 080127d3 .word 0x080127d3 8012744: 080127d3 .word 0x080127d3 8012748: 080127d3 .word 0x080127d3 801274c: 080127d3 .word 0x080127d3 8012750: 080127d3 .word 0x080127d3 8012754: 080127d3 .word 0x080127d3 8012758: 080127d3 .word 0x080127d3 801275c: 080127d3 .word 0x080127d3 8012760: 080127d3 .word 0x080127d3 8012764: 080127c5 .word 0x080127c5 8012768: 2b40 cmp r3, #64 @ 0x40 801276a: d02e beq.n 80127ca 801276c: e031 b.n 80127d2 { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 801276e: f7fa f8e9 bl 800c944 8012772: 63f8 str r0, [r7, #60] @ 0x3c break; 8012774: e033 b.n 80127de case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8012776: f7fa f8fb bl 800c970 801277a: 63f8 str r0, [r7, #60] @ 0x3c break; 801277c: e02f b.n 80127de case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 801277e: f107 0324 add.w r3, r7, #36 @ 0x24 8012782: 4618 mov r0, r3 8012784: f7fc f8d0 bl 800e928 pclk = pll2_clocks.PLL2_Q_Frequency; 8012788: 6abb ldr r3, [r7, #40] @ 0x28 801278a: 63fb str r3, [r7, #60] @ 0x3c break; 801278c: e027 b.n 80127de case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 801278e: f107 0318 add.w r3, r7, #24 8012792: 4618 mov r0, r3 8012794: f7fc fa1c bl 800ebd0 pclk = pll3_clocks.PLL3_Q_Frequency; 8012798: 69fb ldr r3, [r7, #28] 801279a: 63fb str r3, [r7, #60] @ 0x3c break; 801279c: e01f b.n 80127de case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 801279e: 4b2d ldr r3, [pc, #180] @ (8012854 ) 80127a0: 681b ldr r3, [r3, #0] 80127a2: f003 0320 and.w r3, r3, #32 80127a6: 2b00 cmp r3, #0 80127a8: d009 beq.n 80127be { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 80127aa: 4b2a ldr r3, [pc, #168] @ (8012854 ) 80127ac: 681b ldr r3, [r3, #0] 80127ae: 08db lsrs r3, r3, #3 80127b0: f003 0303 and.w r3, r3, #3 80127b4: 4a28 ldr r2, [pc, #160] @ (8012858 ) 80127b6: fa22 f303 lsr.w r3, r2, r3 80127ba: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 80127bc: e00f b.n 80127de pclk = (uint32_t) HSI_VALUE; 80127be: 4b26 ldr r3, [pc, #152] @ (8012858 ) 80127c0: 63fb str r3, [r7, #60] @ 0x3c break; 80127c2: e00c b.n 80127de case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 80127c4: 4b25 ldr r3, [pc, #148] @ (801285c ) 80127c6: 63fb str r3, [r7, #60] @ 0x3c break; 80127c8: e009 b.n 80127de case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 80127ca: f44f 4300 mov.w r3, #32768 @ 0x8000 80127ce: 63fb str r3, [r7, #60] @ 0x3c break; 80127d0: e005 b.n 80127de default: pclk = 0U; 80127d2: 2300 movs r3, #0 80127d4: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 80127d6: 2301 movs r3, #1 80127d8: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 80127dc: bf00 nop } if (pclk != 0U) 80127de: 6bfb ldr r3, [r7, #60] @ 0x3c 80127e0: 2b00 cmp r3, #0 80127e2: d021 beq.n 8012828 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 80127e4: 697b ldr r3, [r7, #20] 80127e6: 6a5b ldr r3, [r3, #36] @ 0x24 80127e8: 4a1d ldr r2, [pc, #116] @ (8012860 ) 80127ea: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80127ee: 461a mov r2, r3 80127f0: 6bfb ldr r3, [r7, #60] @ 0x3c 80127f2: fbb3 f2f2 udiv r2, r3, r2 80127f6: 697b ldr r3, [r7, #20] 80127f8: 685b ldr r3, [r3, #4] 80127fa: 085b lsrs r3, r3, #1 80127fc: 441a add r2, r3 80127fe: 697b ldr r3, [r7, #20] 8012800: 685b ldr r3, [r3, #4] 8012802: fbb2 f3f3 udiv r3, r2, r3 8012806: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8012808: 6bbb ldr r3, [r7, #56] @ 0x38 801280a: 2b0f cmp r3, #15 801280c: d909 bls.n 8012822 801280e: 6bbb ldr r3, [r7, #56] @ 0x38 8012810: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8012814: d205 bcs.n 8012822 { huart->Instance->BRR = (uint16_t)usartdiv; 8012816: 6bbb ldr r3, [r7, #56] @ 0x38 8012818: b29a uxth r2, r3 801281a: 697b ldr r3, [r7, #20] 801281c: 681b ldr r3, [r3, #0] 801281e: 60da str r2, [r3, #12] 8012820: e002 b.n 8012828 } else { ret = HAL_ERROR; 8012822: 2301 movs r3, #1 8012824: f887 3042 strb.w r3, [r7, #66] @ 0x42 } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 8012828: 697b ldr r3, [r7, #20] 801282a: 2201 movs r2, #1 801282c: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1; 8012830: 697b ldr r3, [r7, #20] 8012832: 2201 movs r2, #1 8012834: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; 8012838: 697b ldr r3, [r7, #20] 801283a: 2200 movs r2, #0 801283c: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 801283e: 697b ldr r3, [r7, #20] 8012840: 2200 movs r2, #0 8012842: 679a str r2, [r3, #120] @ 0x78 return ret; 8012844: f897 3042 ldrb.w r3, [r7, #66] @ 0x42 } 8012848: 4618 mov r0, r3 801284a: 3748 adds r7, #72 @ 0x48 801284c: 46bd mov sp, r7 801284e: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8012852: bf00 nop 8012854: 58024400 .word 0x58024400 8012858: 03d09000 .word 0x03d09000 801285c: 003d0900 .word 0x003d0900 8012860: 080187a4 .word 0x080187a4 08012864 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 8012864: b480 push {r7} 8012866: b083 sub sp, #12 8012868: af00 add r7, sp, #0 801286a: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 801286c: 687b ldr r3, [r7, #4] 801286e: 6a9b ldr r3, [r3, #40] @ 0x28 8012870: f003 0308 and.w r3, r3, #8 8012874: 2b00 cmp r3, #0 8012876: d00a beq.n 801288e { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 8012878: 687b ldr r3, [r7, #4] 801287a: 681b ldr r3, [r3, #0] 801287c: 685b ldr r3, [r3, #4] 801287e: f423 4100 bic.w r1, r3, #32768 @ 0x8000 8012882: 687b ldr r3, [r7, #4] 8012884: 6b9a ldr r2, [r3, #56] @ 0x38 8012886: 687b ldr r3, [r7, #4] 8012888: 681b ldr r3, [r3, #0] 801288a: 430a orrs r2, r1 801288c: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 801288e: 687b ldr r3, [r7, #4] 8012890: 6a9b ldr r3, [r3, #40] @ 0x28 8012892: f003 0301 and.w r3, r3, #1 8012896: 2b00 cmp r3, #0 8012898: d00a beq.n 80128b0 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 801289a: 687b ldr r3, [r7, #4] 801289c: 681b ldr r3, [r3, #0] 801289e: 685b ldr r3, [r3, #4] 80128a0: f423 3100 bic.w r1, r3, #131072 @ 0x20000 80128a4: 687b ldr r3, [r7, #4] 80128a6: 6ada ldr r2, [r3, #44] @ 0x2c 80128a8: 687b ldr r3, [r7, #4] 80128aa: 681b ldr r3, [r3, #0] 80128ac: 430a orrs r2, r1 80128ae: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 80128b0: 687b ldr r3, [r7, #4] 80128b2: 6a9b ldr r3, [r3, #40] @ 0x28 80128b4: f003 0302 and.w r3, r3, #2 80128b8: 2b00 cmp r3, #0 80128ba: d00a beq.n 80128d2 { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 80128bc: 687b ldr r3, [r7, #4] 80128be: 681b ldr r3, [r3, #0] 80128c0: 685b ldr r3, [r3, #4] 80128c2: f423 3180 bic.w r1, r3, #65536 @ 0x10000 80128c6: 687b ldr r3, [r7, #4] 80128c8: 6b1a ldr r2, [r3, #48] @ 0x30 80128ca: 687b ldr r3, [r7, #4] 80128cc: 681b ldr r3, [r3, #0] 80128ce: 430a orrs r2, r1 80128d0: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 80128d2: 687b ldr r3, [r7, #4] 80128d4: 6a9b ldr r3, [r3, #40] @ 0x28 80128d6: f003 0304 and.w r3, r3, #4 80128da: 2b00 cmp r3, #0 80128dc: d00a beq.n 80128f4 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 80128de: 687b ldr r3, [r7, #4] 80128e0: 681b ldr r3, [r3, #0] 80128e2: 685b ldr r3, [r3, #4] 80128e4: f423 2180 bic.w r1, r3, #262144 @ 0x40000 80128e8: 687b ldr r3, [r7, #4] 80128ea: 6b5a ldr r2, [r3, #52] @ 0x34 80128ec: 687b ldr r3, [r7, #4] 80128ee: 681b ldr r3, [r3, #0] 80128f0: 430a orrs r2, r1 80128f2: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 80128f4: 687b ldr r3, [r7, #4] 80128f6: 6a9b ldr r3, [r3, #40] @ 0x28 80128f8: f003 0310 and.w r3, r3, #16 80128fc: 2b00 cmp r3, #0 80128fe: d00a beq.n 8012916 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 8012900: 687b ldr r3, [r7, #4] 8012902: 681b ldr r3, [r3, #0] 8012904: 689b ldr r3, [r3, #8] 8012906: f423 5180 bic.w r1, r3, #4096 @ 0x1000 801290a: 687b ldr r3, [r7, #4] 801290c: 6bda ldr r2, [r3, #60] @ 0x3c 801290e: 687b ldr r3, [r7, #4] 8012910: 681b ldr r3, [r3, #0] 8012912: 430a orrs r2, r1 8012914: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 8012916: 687b ldr r3, [r7, #4] 8012918: 6a9b ldr r3, [r3, #40] @ 0x28 801291a: f003 0320 and.w r3, r3, #32 801291e: 2b00 cmp r3, #0 8012920: d00a beq.n 8012938 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 8012922: 687b ldr r3, [r7, #4] 8012924: 681b ldr r3, [r3, #0] 8012926: 689b ldr r3, [r3, #8] 8012928: f423 5100 bic.w r1, r3, #8192 @ 0x2000 801292c: 687b ldr r3, [r7, #4] 801292e: 6c1a ldr r2, [r3, #64] @ 0x40 8012930: 687b ldr r3, [r7, #4] 8012932: 681b ldr r3, [r3, #0] 8012934: 430a orrs r2, r1 8012936: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 8012938: 687b ldr r3, [r7, #4] 801293a: 6a9b ldr r3, [r3, #40] @ 0x28 801293c: f003 0340 and.w r3, r3, #64 @ 0x40 8012940: 2b00 cmp r3, #0 8012942: d01a beq.n 801297a { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 8012944: 687b ldr r3, [r7, #4] 8012946: 681b ldr r3, [r3, #0] 8012948: 685b ldr r3, [r3, #4] 801294a: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 801294e: 687b ldr r3, [r7, #4] 8012950: 6c5a ldr r2, [r3, #68] @ 0x44 8012952: 687b ldr r3, [r7, #4] 8012954: 681b ldr r3, [r3, #0] 8012956: 430a orrs r2, r1 8012958: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 801295a: 687b ldr r3, [r7, #4] 801295c: 6c5b ldr r3, [r3, #68] @ 0x44 801295e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8012962: d10a bne.n 801297a { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 8012964: 687b ldr r3, [r7, #4] 8012966: 681b ldr r3, [r3, #0] 8012968: 685b ldr r3, [r3, #4] 801296a: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 801296e: 687b ldr r3, [r7, #4] 8012970: 6c9a ldr r2, [r3, #72] @ 0x48 8012972: 687b ldr r3, [r7, #4] 8012974: 681b ldr r3, [r3, #0] 8012976: 430a orrs r2, r1 8012978: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 801297a: 687b ldr r3, [r7, #4] 801297c: 6a9b ldr r3, [r3, #40] @ 0x28 801297e: f003 0380 and.w r3, r3, #128 @ 0x80 8012982: 2b00 cmp r3, #0 8012984: d00a beq.n 801299c { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 8012986: 687b ldr r3, [r7, #4] 8012988: 681b ldr r3, [r3, #0] 801298a: 685b ldr r3, [r3, #4] 801298c: f423 2100 bic.w r1, r3, #524288 @ 0x80000 8012990: 687b ldr r3, [r7, #4] 8012992: 6cda ldr r2, [r3, #76] @ 0x4c 8012994: 687b ldr r3, [r7, #4] 8012996: 681b ldr r3, [r3, #0] 8012998: 430a orrs r2, r1 801299a: 605a str r2, [r3, #4] } } 801299c: bf00 nop 801299e: 370c adds r7, #12 80129a0: 46bd mov sp, r7 80129a2: f85d 7b04 ldr.w r7, [sp], #4 80129a6: 4770 bx lr 080129a8 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 80129a8: b580 push {r7, lr} 80129aa: b098 sub sp, #96 @ 0x60 80129ac: af02 add r7, sp, #8 80129ae: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80129b0: 687b ldr r3, [r7, #4] 80129b2: 2200 movs r2, #0 80129b4: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 80129b8: f7f3 fa74 bl 8005ea4 80129bc: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 80129be: 687b ldr r3, [r7, #4] 80129c0: 681b ldr r3, [r3, #0] 80129c2: 681b ldr r3, [r3, #0] 80129c4: f003 0308 and.w r3, r3, #8 80129c8: 2b08 cmp r3, #8 80129ca: d12f bne.n 8012a2c { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 80129cc: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 80129d0: 9300 str r3, [sp, #0] 80129d2: 6d7b ldr r3, [r7, #84] @ 0x54 80129d4: 2200 movs r2, #0 80129d6: f44f 1100 mov.w r1, #2097152 @ 0x200000 80129da: 6878 ldr r0, [r7, #4] 80129dc: f000 f88e bl 8012afc 80129e0: 4603 mov r3, r0 80129e2: 2b00 cmp r3, #0 80129e4: d022 beq.n 8012a2c { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 80129e6: 687b ldr r3, [r7, #4] 80129e8: 681b ldr r3, [r3, #0] 80129ea: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80129ec: 6bbb ldr r3, [r7, #56] @ 0x38 80129ee: e853 3f00 ldrex r3, [r3] 80129f2: 637b str r3, [r7, #52] @ 0x34 return(result); 80129f4: 6b7b ldr r3, [r7, #52] @ 0x34 80129f6: f023 0380 bic.w r3, r3, #128 @ 0x80 80129fa: 653b str r3, [r7, #80] @ 0x50 80129fc: 687b ldr r3, [r7, #4] 80129fe: 681b ldr r3, [r3, #0] 8012a00: 461a mov r2, r3 8012a02: 6d3b ldr r3, [r7, #80] @ 0x50 8012a04: 647b str r3, [r7, #68] @ 0x44 8012a06: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012a08: 6c39 ldr r1, [r7, #64] @ 0x40 8012a0a: 6c7a ldr r2, [r7, #68] @ 0x44 8012a0c: e841 2300 strex r3, r2, [r1] 8012a10: 63fb str r3, [r7, #60] @ 0x3c return(result); 8012a12: 6bfb ldr r3, [r7, #60] @ 0x3c 8012a14: 2b00 cmp r3, #0 8012a16: d1e6 bne.n 80129e6 huart->gState = HAL_UART_STATE_READY; 8012a18: 687b ldr r3, [r7, #4] 8012a1a: 2220 movs r2, #32 8012a1c: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); 8012a20: 687b ldr r3, [r7, #4] 8012a22: 2200 movs r2, #0 8012a24: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8012a28: 2303 movs r3, #3 8012a2a: e063 b.n 8012af4 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 8012a2c: 687b ldr r3, [r7, #4] 8012a2e: 681b ldr r3, [r3, #0] 8012a30: 681b ldr r3, [r3, #0] 8012a32: f003 0304 and.w r3, r3, #4 8012a36: 2b04 cmp r3, #4 8012a38: d149 bne.n 8012ace { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8012a3a: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8012a3e: 9300 str r3, [sp, #0] 8012a40: 6d7b ldr r3, [r7, #84] @ 0x54 8012a42: 2200 movs r2, #0 8012a44: f44f 0180 mov.w r1, #4194304 @ 0x400000 8012a48: 6878 ldr r0, [r7, #4] 8012a4a: f000 f857 bl 8012afc 8012a4e: 4603 mov r3, r0 8012a50: 2b00 cmp r3, #0 8012a52: d03c beq.n 8012ace { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8012a54: 687b ldr r3, [r7, #4] 8012a56: 681b ldr r3, [r3, #0] 8012a58: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012a5a: 6a7b ldr r3, [r7, #36] @ 0x24 8012a5c: e853 3f00 ldrex r3, [r3] 8012a60: 623b str r3, [r7, #32] return(result); 8012a62: 6a3b ldr r3, [r7, #32] 8012a64: f423 7390 bic.w r3, r3, #288 @ 0x120 8012a68: 64fb str r3, [r7, #76] @ 0x4c 8012a6a: 687b ldr r3, [r7, #4] 8012a6c: 681b ldr r3, [r3, #0] 8012a6e: 461a mov r2, r3 8012a70: 6cfb ldr r3, [r7, #76] @ 0x4c 8012a72: 633b str r3, [r7, #48] @ 0x30 8012a74: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012a76: 6af9 ldr r1, [r7, #44] @ 0x2c 8012a78: 6b3a ldr r2, [r7, #48] @ 0x30 8012a7a: e841 2300 strex r3, r2, [r1] 8012a7e: 62bb str r3, [r7, #40] @ 0x28 return(result); 8012a80: 6abb ldr r3, [r7, #40] @ 0x28 8012a82: 2b00 cmp r3, #0 8012a84: d1e6 bne.n 8012a54 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012a86: 687b ldr r3, [r7, #4] 8012a88: 681b ldr r3, [r3, #0] 8012a8a: 3308 adds r3, #8 8012a8c: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012a8e: 693b ldr r3, [r7, #16] 8012a90: e853 3f00 ldrex r3, [r3] 8012a94: 60fb str r3, [r7, #12] return(result); 8012a96: 68fb ldr r3, [r7, #12] 8012a98: f023 0301 bic.w r3, r3, #1 8012a9c: 64bb str r3, [r7, #72] @ 0x48 8012a9e: 687b ldr r3, [r7, #4] 8012aa0: 681b ldr r3, [r3, #0] 8012aa2: 3308 adds r3, #8 8012aa4: 6cba ldr r2, [r7, #72] @ 0x48 8012aa6: 61fa str r2, [r7, #28] 8012aa8: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012aaa: 69b9 ldr r1, [r7, #24] 8012aac: 69fa ldr r2, [r7, #28] 8012aae: e841 2300 strex r3, r2, [r1] 8012ab2: 617b str r3, [r7, #20] return(result); 8012ab4: 697b ldr r3, [r7, #20] 8012ab6: 2b00 cmp r3, #0 8012ab8: d1e5 bne.n 8012a86 huart->RxState = HAL_UART_STATE_READY; 8012aba: 687b ldr r3, [r7, #4] 8012abc: 2220 movs r2, #32 8012abe: f8c3 208c str.w r2, [r3, #140] @ 0x8c __HAL_UNLOCK(huart); 8012ac2: 687b ldr r3, [r7, #4] 8012ac4: 2200 movs r2, #0 8012ac6: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8012aca: 2303 movs r3, #3 8012acc: e012 b.n 8012af4 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 8012ace: 687b ldr r3, [r7, #4] 8012ad0: 2220 movs r2, #32 8012ad2: f8c3 2088 str.w r2, [r3, #136] @ 0x88 huart->RxState = HAL_UART_STATE_READY; 8012ad6: 687b ldr r3, [r7, #4] 8012ad8: 2220 movs r2, #32 8012ada: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012ade: 687b ldr r3, [r7, #4] 8012ae0: 2200 movs r2, #0 8012ae2: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8012ae4: 687b ldr r3, [r7, #4] 8012ae6: 2200 movs r2, #0 8012ae8: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 8012aea: 687b ldr r3, [r7, #4] 8012aec: 2200 movs r2, #0 8012aee: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8012af2: 2300 movs r3, #0 } 8012af4: 4618 mov r0, r3 8012af6: 3758 adds r7, #88 @ 0x58 8012af8: 46bd mov sp, r7 8012afa: bd80 pop {r7, pc} 08012afc : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8012afc: b580 push {r7, lr} 8012afe: b084 sub sp, #16 8012b00: af00 add r7, sp, #0 8012b02: 60f8 str r0, [r7, #12] 8012b04: 60b9 str r1, [r7, #8] 8012b06: 603b str r3, [r7, #0] 8012b08: 4613 mov r3, r2 8012b0a: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8012b0c: e04f b.n 8012bae { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8012b0e: 69bb ldr r3, [r7, #24] 8012b10: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8012b14: d04b beq.n 8012bae { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8012b16: f7f3 f9c5 bl 8005ea4 8012b1a: 4602 mov r2, r0 8012b1c: 683b ldr r3, [r7, #0] 8012b1e: 1ad3 subs r3, r2, r3 8012b20: 69ba ldr r2, [r7, #24] 8012b22: 429a cmp r2, r3 8012b24: d302 bcc.n 8012b2c 8012b26: 69bb ldr r3, [r7, #24] 8012b28: 2b00 cmp r3, #0 8012b2a: d101 bne.n 8012b30 { return HAL_TIMEOUT; 8012b2c: 2303 movs r3, #3 8012b2e: e04e b.n 8012bce } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 8012b30: 68fb ldr r3, [r7, #12] 8012b32: 681b ldr r3, [r3, #0] 8012b34: 681b ldr r3, [r3, #0] 8012b36: f003 0304 and.w r3, r3, #4 8012b3a: 2b00 cmp r3, #0 8012b3c: d037 beq.n 8012bae 8012b3e: 68bb ldr r3, [r7, #8] 8012b40: 2b80 cmp r3, #128 @ 0x80 8012b42: d034 beq.n 8012bae 8012b44: 68bb ldr r3, [r7, #8] 8012b46: 2b40 cmp r3, #64 @ 0x40 8012b48: d031 beq.n 8012bae { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8012b4a: 68fb ldr r3, [r7, #12] 8012b4c: 681b ldr r3, [r3, #0] 8012b4e: 69db ldr r3, [r3, #28] 8012b50: f003 0308 and.w r3, r3, #8 8012b54: 2b08 cmp r3, #8 8012b56: d110 bne.n 8012b7a { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8012b58: 68fb ldr r3, [r7, #12] 8012b5a: 681b ldr r3, [r3, #0] 8012b5c: 2208 movs r2, #8 8012b5e: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8012b60: 68f8 ldr r0, [r7, #12] 8012b62: f000 f95b bl 8012e1c huart->ErrorCode = HAL_UART_ERROR_ORE; 8012b66: 68fb ldr r3, [r7, #12] 8012b68: 2208 movs r2, #8 8012b6a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8012b6e: 68fb ldr r3, [r7, #12] 8012b70: 2200 movs r2, #0 8012b72: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_ERROR; 8012b76: 2301 movs r3, #1 8012b78: e029 b.n 8012bce } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8012b7a: 68fb ldr r3, [r7, #12] 8012b7c: 681b ldr r3, [r3, #0] 8012b7e: 69db ldr r3, [r3, #28] 8012b80: f403 6300 and.w r3, r3, #2048 @ 0x800 8012b84: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8012b88: d111 bne.n 8012bae { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8012b8a: 68fb ldr r3, [r7, #12] 8012b8c: 681b ldr r3, [r3, #0] 8012b8e: f44f 6200 mov.w r2, #2048 @ 0x800 8012b92: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8012b94: 68f8 ldr r0, [r7, #12] 8012b96: f000 f941 bl 8012e1c huart->ErrorCode = HAL_UART_ERROR_RTO; 8012b9a: 68fb ldr r3, [r7, #12] 8012b9c: 2220 movs r2, #32 8012b9e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8012ba2: 68fb ldr r3, [r7, #12] 8012ba4: 2200 movs r2, #0 8012ba6: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_TIMEOUT; 8012baa: 2303 movs r3, #3 8012bac: e00f b.n 8012bce while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8012bae: 68fb ldr r3, [r7, #12] 8012bb0: 681b ldr r3, [r3, #0] 8012bb2: 69da ldr r2, [r3, #28] 8012bb4: 68bb ldr r3, [r7, #8] 8012bb6: 4013 ands r3, r2 8012bb8: 68ba ldr r2, [r7, #8] 8012bba: 429a cmp r2, r3 8012bbc: bf0c ite eq 8012bbe: 2301 moveq r3, #1 8012bc0: 2300 movne r3, #0 8012bc2: b2db uxtb r3, r3 8012bc4: 461a mov r2, r3 8012bc6: 79fb ldrb r3, [r7, #7] 8012bc8: 429a cmp r2, r3 8012bca: d0a0 beq.n 8012b0e } } } } return HAL_OK; 8012bcc: 2300 movs r3, #0 } 8012bce: 4618 mov r0, r3 8012bd0: 3710 adds r7, #16 8012bd2: 46bd mov sp, r7 8012bd4: bd80 pop {r7, pc} ... 08012bd8 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8012bd8: b480 push {r7} 8012bda: b0a3 sub sp, #140 @ 0x8c 8012bdc: af00 add r7, sp, #0 8012bde: 60f8 str r0, [r7, #12] 8012be0: 60b9 str r1, [r7, #8] 8012be2: 4613 mov r3, r2 8012be4: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 8012be6: 68fb ldr r3, [r7, #12] 8012be8: 68ba ldr r2, [r7, #8] 8012bea: 659a str r2, [r3, #88] @ 0x58 huart->RxXferSize = Size; 8012bec: 68fb ldr r3, [r7, #12] 8012bee: 88fa ldrh r2, [r7, #6] 8012bf0: f8a3 205c strh.w r2, [r3, #92] @ 0x5c huart->RxXferCount = Size; 8012bf4: 68fb ldr r3, [r7, #12] 8012bf6: 88fa ldrh r2, [r7, #6] 8012bf8: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->RxISR = NULL; 8012bfc: 68fb ldr r3, [r7, #12] 8012bfe: 2200 movs r2, #0 8012c00: 675a str r2, [r3, #116] @ 0x74 /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); 8012c02: 68fb ldr r3, [r7, #12] 8012c04: 689b ldr r3, [r3, #8] 8012c06: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012c0a: d10e bne.n 8012c2a 8012c0c: 68fb ldr r3, [r7, #12] 8012c0e: 691b ldr r3, [r3, #16] 8012c10: 2b00 cmp r3, #0 8012c12: d105 bne.n 8012c20 8012c14: 68fb ldr r3, [r7, #12] 8012c16: f240 12ff movw r2, #511 @ 0x1ff 8012c1a: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012c1e: e02d b.n 8012c7c 8012c20: 68fb ldr r3, [r7, #12] 8012c22: 22ff movs r2, #255 @ 0xff 8012c24: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012c28: e028 b.n 8012c7c 8012c2a: 68fb ldr r3, [r7, #12] 8012c2c: 689b ldr r3, [r3, #8] 8012c2e: 2b00 cmp r3, #0 8012c30: d10d bne.n 8012c4e 8012c32: 68fb ldr r3, [r7, #12] 8012c34: 691b ldr r3, [r3, #16] 8012c36: 2b00 cmp r3, #0 8012c38: d104 bne.n 8012c44 8012c3a: 68fb ldr r3, [r7, #12] 8012c3c: 22ff movs r2, #255 @ 0xff 8012c3e: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012c42: e01b b.n 8012c7c 8012c44: 68fb ldr r3, [r7, #12] 8012c46: 227f movs r2, #127 @ 0x7f 8012c48: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012c4c: e016 b.n 8012c7c 8012c4e: 68fb ldr r3, [r7, #12] 8012c50: 689b ldr r3, [r3, #8] 8012c52: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8012c56: d10d bne.n 8012c74 8012c58: 68fb ldr r3, [r7, #12] 8012c5a: 691b ldr r3, [r3, #16] 8012c5c: 2b00 cmp r3, #0 8012c5e: d104 bne.n 8012c6a 8012c60: 68fb ldr r3, [r7, #12] 8012c62: 227f movs r2, #127 @ 0x7f 8012c64: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012c68: e008 b.n 8012c7c 8012c6a: 68fb ldr r3, [r7, #12] 8012c6c: 223f movs r2, #63 @ 0x3f 8012c6e: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012c72: e003 b.n 8012c7c 8012c74: 68fb ldr r3, [r7, #12] 8012c76: 2200 movs r2, #0 8012c78: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 huart->ErrorCode = HAL_UART_ERROR_NONE; 8012c7c: 68fb ldr r3, [r7, #12] 8012c7e: 2200 movs r2, #0 8012c80: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->RxState = HAL_UART_STATE_BUSY_RX; 8012c84: 68fb ldr r3, [r7, #12] 8012c86: 2222 movs r2, #34 @ 0x22 8012c88: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012c8c: 68fb ldr r3, [r7, #12] 8012c8e: 681b ldr r3, [r3, #0] 8012c90: 3308 adds r3, #8 8012c92: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012c94: 6e7b ldr r3, [r7, #100] @ 0x64 8012c96: e853 3f00 ldrex r3, [r3] 8012c9a: 663b str r3, [r7, #96] @ 0x60 return(result); 8012c9c: 6e3b ldr r3, [r7, #96] @ 0x60 8012c9e: f043 0301 orr.w r3, r3, #1 8012ca2: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8012ca6: 68fb ldr r3, [r7, #12] 8012ca8: 681b ldr r3, [r3, #0] 8012caa: 3308 adds r3, #8 8012cac: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 8012cb0: 673a str r2, [r7, #112] @ 0x70 8012cb2: 66fb str r3, [r7, #108] @ 0x6c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012cb4: 6ef9 ldr r1, [r7, #108] @ 0x6c 8012cb6: 6f3a ldr r2, [r7, #112] @ 0x70 8012cb8: e841 2300 strex r3, r2, [r1] 8012cbc: 66bb str r3, [r7, #104] @ 0x68 return(result); 8012cbe: 6ebb ldr r3, [r7, #104] @ 0x68 8012cc0: 2b00 cmp r3, #0 8012cc2: d1e3 bne.n 8012c8c /* Configure Rx interrupt processing */ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) 8012cc4: 68fb ldr r3, [r7, #12] 8012cc6: 6e5b ldr r3, [r3, #100] @ 0x64 8012cc8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8012ccc: d14f bne.n 8012d6e 8012cce: 68fb ldr r3, [r7, #12] 8012cd0: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8012cd4: 88fa ldrh r2, [r7, #6] 8012cd6: 429a cmp r2, r3 8012cd8: d349 bcc.n 8012d6e { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012cda: 68fb ldr r3, [r7, #12] 8012cdc: 689b ldr r3, [r3, #8] 8012cde: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012ce2: d107 bne.n 8012cf4 8012ce4: 68fb ldr r3, [r7, #12] 8012ce6: 691b ldr r3, [r3, #16] 8012ce8: 2b00 cmp r3, #0 8012cea: d103 bne.n 8012cf4 { huart->RxISR = UART_RxISR_16BIT_FIFOEN; 8012cec: 68fb ldr r3, [r7, #12] 8012cee: 4a47 ldr r2, [pc, #284] @ (8012e0c ) 8012cf0: 675a str r2, [r3, #116] @ 0x74 8012cf2: e002 b.n 8012cfa } else { huart->RxISR = UART_RxISR_8BIT_FIFOEN; 8012cf4: 68fb ldr r3, [r7, #12] 8012cf6: 4a46 ldr r2, [pc, #280] @ (8012e10 ) 8012cf8: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8012cfa: 68fb ldr r3, [r7, #12] 8012cfc: 691b ldr r3, [r3, #16] 8012cfe: 2b00 cmp r3, #0 8012d00: d01a beq.n 8012d38 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8012d02: 68fb ldr r3, [r7, #12] 8012d04: 681b ldr r3, [r3, #0] 8012d06: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012d08: 6d3b ldr r3, [r7, #80] @ 0x50 8012d0a: e853 3f00 ldrex r3, [r3] 8012d0e: 64fb str r3, [r7, #76] @ 0x4c return(result); 8012d10: 6cfb ldr r3, [r7, #76] @ 0x4c 8012d12: f443 7380 orr.w r3, r3, #256 @ 0x100 8012d16: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8012d1a: 68fb ldr r3, [r7, #12] 8012d1c: 681b ldr r3, [r3, #0] 8012d1e: 461a mov r2, r3 8012d20: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8012d24: 65fb str r3, [r7, #92] @ 0x5c 8012d26: 65ba str r2, [r7, #88] @ 0x58 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d28: 6db9 ldr r1, [r7, #88] @ 0x58 8012d2a: 6dfa ldr r2, [r7, #92] @ 0x5c 8012d2c: e841 2300 strex r3, r2, [r1] 8012d30: 657b str r3, [r7, #84] @ 0x54 return(result); 8012d32: 6d7b ldr r3, [r7, #84] @ 0x54 8012d34: 2b00 cmp r3, #0 8012d36: d1e4 bne.n 8012d02 } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8012d38: 68fb ldr r3, [r7, #12] 8012d3a: 681b ldr r3, [r3, #0] 8012d3c: 3308 adds r3, #8 8012d3e: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012d40: 6bfb ldr r3, [r7, #60] @ 0x3c 8012d42: e853 3f00 ldrex r3, [r3] 8012d46: 63bb str r3, [r7, #56] @ 0x38 return(result); 8012d48: 6bbb ldr r3, [r7, #56] @ 0x38 8012d4a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8012d4e: 67fb str r3, [r7, #124] @ 0x7c 8012d50: 68fb ldr r3, [r7, #12] 8012d52: 681b ldr r3, [r3, #0] 8012d54: 3308 adds r3, #8 8012d56: 6ffa ldr r2, [r7, #124] @ 0x7c 8012d58: 64ba str r2, [r7, #72] @ 0x48 8012d5a: 647b str r3, [r7, #68] @ 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d5c: 6c79 ldr r1, [r7, #68] @ 0x44 8012d5e: 6cba ldr r2, [r7, #72] @ 0x48 8012d60: e841 2300 strex r3, r2, [r1] 8012d64: 643b str r3, [r7, #64] @ 0x40 return(result); 8012d66: 6c3b ldr r3, [r7, #64] @ 0x40 8012d68: 2b00 cmp r3, #0 8012d6a: d1e5 bne.n 8012d38 8012d6c: e046 b.n 8012dfc } else { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012d6e: 68fb ldr r3, [r7, #12] 8012d70: 689b ldr r3, [r3, #8] 8012d72: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012d76: d107 bne.n 8012d88 8012d78: 68fb ldr r3, [r7, #12] 8012d7a: 691b ldr r3, [r3, #16] 8012d7c: 2b00 cmp r3, #0 8012d7e: d103 bne.n 8012d88 { huart->RxISR = UART_RxISR_16BIT; 8012d80: 68fb ldr r3, [r7, #12] 8012d82: 4a24 ldr r2, [pc, #144] @ (8012e14 ) 8012d84: 675a str r2, [r3, #116] @ 0x74 8012d86: e002 b.n 8012d8e } else { huart->RxISR = UART_RxISR_8BIT; 8012d88: 68fb ldr r3, [r7, #12] 8012d8a: 4a23 ldr r2, [pc, #140] @ (8012e18 ) 8012d8c: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8012d8e: 68fb ldr r3, [r7, #12] 8012d90: 691b ldr r3, [r3, #16] 8012d92: 2b00 cmp r3, #0 8012d94: d019 beq.n 8012dca { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); 8012d96: 68fb ldr r3, [r7, #12] 8012d98: 681b ldr r3, [r3, #0] 8012d9a: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012d9c: 6abb ldr r3, [r7, #40] @ 0x28 8012d9e: e853 3f00 ldrex r3, [r3] 8012da2: 627b str r3, [r7, #36] @ 0x24 return(result); 8012da4: 6a7b ldr r3, [r7, #36] @ 0x24 8012da6: f443 7390 orr.w r3, r3, #288 @ 0x120 8012daa: 677b str r3, [r7, #116] @ 0x74 8012dac: 68fb ldr r3, [r7, #12] 8012dae: 681b ldr r3, [r3, #0] 8012db0: 461a mov r2, r3 8012db2: 6f7b ldr r3, [r7, #116] @ 0x74 8012db4: 637b str r3, [r7, #52] @ 0x34 8012db6: 633a str r2, [r7, #48] @ 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012db8: 6b39 ldr r1, [r7, #48] @ 0x30 8012dba: 6b7a ldr r2, [r7, #52] @ 0x34 8012dbc: e841 2300 strex r3, r2, [r1] 8012dc0: 62fb str r3, [r7, #44] @ 0x2c return(result); 8012dc2: 6afb ldr r3, [r7, #44] @ 0x2c 8012dc4: 2b00 cmp r3, #0 8012dc6: d1e6 bne.n 8012d96 8012dc8: e018 b.n 8012dfc } else { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8012dca: 68fb ldr r3, [r7, #12] 8012dcc: 681b ldr r3, [r3, #0] 8012dce: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012dd0: 697b ldr r3, [r7, #20] 8012dd2: e853 3f00 ldrex r3, [r3] 8012dd6: 613b str r3, [r7, #16] return(result); 8012dd8: 693b ldr r3, [r7, #16] 8012dda: f043 0320 orr.w r3, r3, #32 8012dde: 67bb str r3, [r7, #120] @ 0x78 8012de0: 68fb ldr r3, [r7, #12] 8012de2: 681b ldr r3, [r3, #0] 8012de4: 461a mov r2, r3 8012de6: 6fbb ldr r3, [r7, #120] @ 0x78 8012de8: 623b str r3, [r7, #32] 8012dea: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012dec: 69f9 ldr r1, [r7, #28] 8012dee: 6a3a ldr r2, [r7, #32] 8012df0: e841 2300 strex r3, r2, [r1] 8012df4: 61bb str r3, [r7, #24] return(result); 8012df6: 69bb ldr r3, [r7, #24] 8012df8: 2b00 cmp r3, #0 8012dfa: d1e6 bne.n 8012dca } } return HAL_OK; 8012dfc: 2300 movs r3, #0 } 8012dfe: 4618 mov r0, r3 8012e00: 378c adds r7, #140 @ 0x8c 8012e02: 46bd mov sp, r7 8012e04: f85d 7b04 ldr.w r7, [sp], #4 8012e08: 4770 bx lr 8012e0a: bf00 nop 8012e0c: 08013981 .word 0x08013981 8012e10: 08013621 .word 0x08013621 8012e14: 08013469 .word 0x08013469 8012e18: 080132b1 .word 0x080132b1 08012e1c : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8012e1c: b480 push {r7} 8012e1e: b095 sub sp, #84 @ 0x54 8012e20: af00 add r7, sp, #0 8012e22: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8012e24: 687b ldr r3, [r7, #4] 8012e26: 681b ldr r3, [r3, #0] 8012e28: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012e2a: 6b7b ldr r3, [r7, #52] @ 0x34 8012e2c: e853 3f00 ldrex r3, [r3] 8012e30: 633b str r3, [r7, #48] @ 0x30 return(result); 8012e32: 6b3b ldr r3, [r7, #48] @ 0x30 8012e34: f423 7390 bic.w r3, r3, #288 @ 0x120 8012e38: 64fb str r3, [r7, #76] @ 0x4c 8012e3a: 687b ldr r3, [r7, #4] 8012e3c: 681b ldr r3, [r3, #0] 8012e3e: 461a mov r2, r3 8012e40: 6cfb ldr r3, [r7, #76] @ 0x4c 8012e42: 643b str r3, [r7, #64] @ 0x40 8012e44: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012e46: 6bf9 ldr r1, [r7, #60] @ 0x3c 8012e48: 6c3a ldr r2, [r7, #64] @ 0x40 8012e4a: e841 2300 strex r3, r2, [r1] 8012e4e: 63bb str r3, [r7, #56] @ 0x38 return(result); 8012e50: 6bbb ldr r3, [r7, #56] @ 0x38 8012e52: 2b00 cmp r3, #0 8012e54: d1e6 bne.n 8012e24 ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8012e56: 687b ldr r3, [r7, #4] 8012e58: 681b ldr r3, [r3, #0] 8012e5a: 3308 adds r3, #8 8012e5c: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012e5e: 6a3b ldr r3, [r7, #32] 8012e60: e853 3f00 ldrex r3, [r3] 8012e64: 61fb str r3, [r7, #28] return(result); 8012e66: 69fa ldr r2, [r7, #28] 8012e68: 4b1e ldr r3, [pc, #120] @ (8012ee4 ) 8012e6a: 4013 ands r3, r2 8012e6c: 64bb str r3, [r7, #72] @ 0x48 8012e6e: 687b ldr r3, [r7, #4] 8012e70: 681b ldr r3, [r3, #0] 8012e72: 3308 adds r3, #8 8012e74: 6cba ldr r2, [r7, #72] @ 0x48 8012e76: 62fa str r2, [r7, #44] @ 0x2c 8012e78: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012e7a: 6ab9 ldr r1, [r7, #40] @ 0x28 8012e7c: 6afa ldr r2, [r7, #44] @ 0x2c 8012e7e: e841 2300 strex r3, r2, [r1] 8012e82: 627b str r3, [r7, #36] @ 0x24 return(result); 8012e84: 6a7b ldr r3, [r7, #36] @ 0x24 8012e86: 2b00 cmp r3, #0 8012e88: d1e5 bne.n 8012e56 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012e8a: 687b ldr r3, [r7, #4] 8012e8c: 6edb ldr r3, [r3, #108] @ 0x6c 8012e8e: 2b01 cmp r3, #1 8012e90: d118 bne.n 8012ec4 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012e92: 687b ldr r3, [r7, #4] 8012e94: 681b ldr r3, [r3, #0] 8012e96: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012e98: 68fb ldr r3, [r7, #12] 8012e9a: e853 3f00 ldrex r3, [r3] 8012e9e: 60bb str r3, [r7, #8] return(result); 8012ea0: 68bb ldr r3, [r7, #8] 8012ea2: f023 0310 bic.w r3, r3, #16 8012ea6: 647b str r3, [r7, #68] @ 0x44 8012ea8: 687b ldr r3, [r7, #4] 8012eaa: 681b ldr r3, [r3, #0] 8012eac: 461a mov r2, r3 8012eae: 6c7b ldr r3, [r7, #68] @ 0x44 8012eb0: 61bb str r3, [r7, #24] 8012eb2: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012eb4: 6979 ldr r1, [r7, #20] 8012eb6: 69ba ldr r2, [r7, #24] 8012eb8: e841 2300 strex r3, r2, [r1] 8012ebc: 613b str r3, [r7, #16] return(result); 8012ebe: 693b ldr r3, [r7, #16] 8012ec0: 2b00 cmp r3, #0 8012ec2: d1e6 bne.n 8012e92 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012ec4: 687b ldr r3, [r7, #4] 8012ec6: 2220 movs r2, #32 8012ec8: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012ecc: 687b ldr r3, [r7, #4] 8012ece: 2200 movs r2, #0 8012ed0: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 8012ed2: 687b ldr r3, [r7, #4] 8012ed4: 2200 movs r2, #0 8012ed6: 675a str r2, [r3, #116] @ 0x74 } 8012ed8: bf00 nop 8012eda: 3754 adds r7, #84 @ 0x54 8012edc: 46bd mov sp, r7 8012ede: f85d 7b04 ldr.w r7, [sp], #4 8012ee2: 4770 bx lr 8012ee4: effffffe .word 0xeffffffe 08012ee8 : * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8012ee8: b580 push {r7, lr} 8012eea: b084 sub sp, #16 8012eec: af00 add r7, sp, #0 8012eee: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8012ef0: 687b ldr r3, [r7, #4] 8012ef2: 6b9b ldr r3, [r3, #56] @ 0x38 8012ef4: 60fb str r3, [r7, #12] huart->RxXferCount = 0U; 8012ef6: 68fb ldr r3, [r7, #12] 8012ef8: 2200 movs r2, #0 8012efa: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->TxXferCount = 0U; 8012efe: 68fb ldr r3, [r7, #12] 8012f00: 2200 movs r2, #0 8012f02: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8012f06: 68f8 ldr r0, [r7, #12] 8012f08: f7fe ff3a bl 8011d80 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8012f0c: bf00 nop 8012f0e: 3710 adds r7, #16 8012f10: 46bd mov sp, r7 8012f12: bd80 pop {r7, pc} 08012f14 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) { 8012f14: b480 push {r7} 8012f16: b08f sub sp, #60 @ 0x3c 8012f18: af00 add r7, sp, #0 8012f1a: 6078 str r0, [r7, #4] /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8012f1c: 687b ldr r3, [r7, #4] 8012f1e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8012f22: 2b21 cmp r3, #33 @ 0x21 8012f24: d14c bne.n 8012fc0 { if (huart->TxXferCount == 0U) 8012f26: 687b ldr r3, [r7, #4] 8012f28: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012f2c: b29b uxth r3, r3 8012f2e: 2b00 cmp r3, #0 8012f30: d132 bne.n 8012f98 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8012f32: 687b ldr r3, [r7, #4] 8012f34: 681b ldr r3, [r3, #0] 8012f36: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012f38: 6a3b ldr r3, [r7, #32] 8012f3a: e853 3f00 ldrex r3, [r3] 8012f3e: 61fb str r3, [r7, #28] return(result); 8012f40: 69fb ldr r3, [r7, #28] 8012f42: f023 0380 bic.w r3, r3, #128 @ 0x80 8012f46: 637b str r3, [r7, #52] @ 0x34 8012f48: 687b ldr r3, [r7, #4] 8012f4a: 681b ldr r3, [r3, #0] 8012f4c: 461a mov r2, r3 8012f4e: 6b7b ldr r3, [r7, #52] @ 0x34 8012f50: 62fb str r3, [r7, #44] @ 0x2c 8012f52: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012f54: 6ab9 ldr r1, [r7, #40] @ 0x28 8012f56: 6afa ldr r2, [r7, #44] @ 0x2c 8012f58: e841 2300 strex r3, r2, [r1] 8012f5c: 627b str r3, [r7, #36] @ 0x24 return(result); 8012f5e: 6a7b ldr r3, [r7, #36] @ 0x24 8012f60: 2b00 cmp r3, #0 8012f62: d1e6 bne.n 8012f32 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8012f64: 687b ldr r3, [r7, #4] 8012f66: 681b ldr r3, [r3, #0] 8012f68: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012f6a: 68fb ldr r3, [r7, #12] 8012f6c: e853 3f00 ldrex r3, [r3] 8012f70: 60bb str r3, [r7, #8] return(result); 8012f72: 68bb ldr r3, [r7, #8] 8012f74: f043 0340 orr.w r3, r3, #64 @ 0x40 8012f78: 633b str r3, [r7, #48] @ 0x30 8012f7a: 687b ldr r3, [r7, #4] 8012f7c: 681b ldr r3, [r3, #0] 8012f7e: 461a mov r2, r3 8012f80: 6b3b ldr r3, [r7, #48] @ 0x30 8012f82: 61bb str r3, [r7, #24] 8012f84: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012f86: 6979 ldr r1, [r7, #20] 8012f88: 69ba ldr r2, [r7, #24] 8012f8a: e841 2300 strex r3, r2, [r1] 8012f8e: 613b str r3, [r7, #16] return(result); 8012f90: 693b ldr r3, [r7, #16] 8012f92: 2b00 cmp r3, #0 8012f94: d1e6 bne.n 8012f64 huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); huart->pTxBuffPtr++; huart->TxXferCount--; } } } 8012f96: e013 b.n 8012fc0 huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 8012f98: 687b ldr r3, [r7, #4] 8012f9a: 6d1b ldr r3, [r3, #80] @ 0x50 8012f9c: 781a ldrb r2, [r3, #0] 8012f9e: 687b ldr r3, [r7, #4] 8012fa0: 681b ldr r3, [r3, #0] 8012fa2: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 8012fa4: 687b ldr r3, [r7, #4] 8012fa6: 6d1b ldr r3, [r3, #80] @ 0x50 8012fa8: 1c5a adds r2, r3, #1 8012faa: 687b ldr r3, [r7, #4] 8012fac: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 8012fae: 687b ldr r3, [r7, #4] 8012fb0: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012fb4: b29b uxth r3, r3 8012fb6: 3b01 subs r3, #1 8012fb8: b29a uxth r2, r3 8012fba: 687b ldr r3, [r7, #4] 8012fbc: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 8012fc0: bf00 nop 8012fc2: 373c adds r7, #60 @ 0x3c 8012fc4: 46bd mov sp, r7 8012fc6: f85d 7b04 ldr.w r7, [sp], #4 8012fca: 4770 bx lr 08012fcc : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { 8012fcc: b480 push {r7} 8012fce: b091 sub sp, #68 @ 0x44 8012fd0: af00 add r7, sp, #0 8012fd2: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8012fd4: 687b ldr r3, [r7, #4] 8012fd6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8012fda: 2b21 cmp r3, #33 @ 0x21 8012fdc: d151 bne.n 8013082 { if (huart->TxXferCount == 0U) 8012fde: 687b ldr r3, [r7, #4] 8012fe0: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012fe4: b29b uxth r3, r3 8012fe6: 2b00 cmp r3, #0 8012fe8: d132 bne.n 8013050 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8012fea: 687b ldr r3, [r7, #4] 8012fec: 681b ldr r3, [r3, #0] 8012fee: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012ff0: 6a7b ldr r3, [r7, #36] @ 0x24 8012ff2: e853 3f00 ldrex r3, [r3] 8012ff6: 623b str r3, [r7, #32] return(result); 8012ff8: 6a3b ldr r3, [r7, #32] 8012ffa: f023 0380 bic.w r3, r3, #128 @ 0x80 8012ffe: 63bb str r3, [r7, #56] @ 0x38 8013000: 687b ldr r3, [r7, #4] 8013002: 681b ldr r3, [r3, #0] 8013004: 461a mov r2, r3 8013006: 6bbb ldr r3, [r7, #56] @ 0x38 8013008: 633b str r3, [r7, #48] @ 0x30 801300a: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801300c: 6af9 ldr r1, [r7, #44] @ 0x2c 801300e: 6b3a ldr r2, [r7, #48] @ 0x30 8013010: e841 2300 strex r3, r2, [r1] 8013014: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013016: 6abb ldr r3, [r7, #40] @ 0x28 8013018: 2b00 cmp r3, #0 801301a: d1e6 bne.n 8012fea /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 801301c: 687b ldr r3, [r7, #4] 801301e: 681b ldr r3, [r3, #0] 8013020: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013022: 693b ldr r3, [r7, #16] 8013024: e853 3f00 ldrex r3, [r3] 8013028: 60fb str r3, [r7, #12] return(result); 801302a: 68fb ldr r3, [r7, #12] 801302c: f043 0340 orr.w r3, r3, #64 @ 0x40 8013030: 637b str r3, [r7, #52] @ 0x34 8013032: 687b ldr r3, [r7, #4] 8013034: 681b ldr r3, [r3, #0] 8013036: 461a mov r2, r3 8013038: 6b7b ldr r3, [r7, #52] @ 0x34 801303a: 61fb str r3, [r7, #28] 801303c: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801303e: 69b9 ldr r1, [r7, #24] 8013040: 69fa ldr r2, [r7, #28] 8013042: e841 2300 strex r3, r2, [r1] 8013046: 617b str r3, [r7, #20] return(result); 8013048: 697b ldr r3, [r7, #20] 801304a: 2b00 cmp r3, #0 801304c: d1e6 bne.n 801301c huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; } } } 801304e: e018 b.n 8013082 tmp = (const uint16_t *) huart->pTxBuffPtr; 8013050: 687b ldr r3, [r7, #4] 8013052: 6d1b ldr r3, [r3, #80] @ 0x50 8013054: 63fb str r3, [r7, #60] @ 0x3c huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 8013056: 6bfb ldr r3, [r7, #60] @ 0x3c 8013058: 881b ldrh r3, [r3, #0] 801305a: 461a mov r2, r3 801305c: 687b ldr r3, [r7, #4] 801305e: 681b ldr r3, [r3, #0] 8013060: f3c2 0208 ubfx r2, r2, #0, #9 8013064: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 8013066: 687b ldr r3, [r7, #4] 8013068: 6d1b ldr r3, [r3, #80] @ 0x50 801306a: 1c9a adds r2, r3, #2 801306c: 687b ldr r3, [r7, #4] 801306e: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 8013070: 687b ldr r3, [r7, #4] 8013072: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8013076: b29b uxth r3, r3 8013078: 3b01 subs r3, #1 801307a: b29a uxth r2, r3 801307c: 687b ldr r3, [r7, #4] 801307e: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 8013082: bf00 nop 8013084: 3744 adds r7, #68 @ 0x44 8013086: 46bd mov sp, r7 8013088: f85d 7b04 ldr.w r7, [sp], #4 801308c: 4770 bx lr 0801308e : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 801308e: b480 push {r7} 8013090: b091 sub sp, #68 @ 0x44 8013092: af00 add r7, sp, #0 8013094: 6078 str r0, [r7, #4] uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8013096: 687b ldr r3, [r7, #4] 8013098: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 801309c: 2b21 cmp r3, #33 @ 0x21 801309e: d160 bne.n 8013162 { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80130a0: 687b ldr r3, [r7, #4] 80130a2: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 80130a6: 87fb strh r3, [r7, #62] @ 0x3e 80130a8: e057 b.n 801315a { if (huart->TxXferCount == 0U) 80130aa: 687b ldr r3, [r7, #4] 80130ac: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80130b0: b29b uxth r3, r3 80130b2: 2b00 cmp r3, #0 80130b4: d133 bne.n 801311e { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 80130b6: 687b ldr r3, [r7, #4] 80130b8: 681b ldr r3, [r3, #0] 80130ba: 3308 adds r3, #8 80130bc: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80130be: 6a7b ldr r3, [r7, #36] @ 0x24 80130c0: e853 3f00 ldrex r3, [r3] 80130c4: 623b str r3, [r7, #32] return(result); 80130c6: 6a3b ldr r3, [r7, #32] 80130c8: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 80130cc: 63bb str r3, [r7, #56] @ 0x38 80130ce: 687b ldr r3, [r7, #4] 80130d0: 681b ldr r3, [r3, #0] 80130d2: 3308 adds r3, #8 80130d4: 6bba ldr r2, [r7, #56] @ 0x38 80130d6: 633a str r2, [r7, #48] @ 0x30 80130d8: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80130da: 6af9 ldr r1, [r7, #44] @ 0x2c 80130dc: 6b3a ldr r2, [r7, #48] @ 0x30 80130de: e841 2300 strex r3, r2, [r1] 80130e2: 62bb str r3, [r7, #40] @ 0x28 return(result); 80130e4: 6abb ldr r3, [r7, #40] @ 0x28 80130e6: 2b00 cmp r3, #0 80130e8: d1e5 bne.n 80130b6 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80130ea: 687b ldr r3, [r7, #4] 80130ec: 681b ldr r3, [r3, #0] 80130ee: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80130f0: 693b ldr r3, [r7, #16] 80130f2: e853 3f00 ldrex r3, [r3] 80130f6: 60fb str r3, [r7, #12] return(result); 80130f8: 68fb ldr r3, [r7, #12] 80130fa: f043 0340 orr.w r3, r3, #64 @ 0x40 80130fe: 637b str r3, [r7, #52] @ 0x34 8013100: 687b ldr r3, [r7, #4] 8013102: 681b ldr r3, [r3, #0] 8013104: 461a mov r2, r3 8013106: 6b7b ldr r3, [r7, #52] @ 0x34 8013108: 61fb str r3, [r7, #28] 801310a: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801310c: 69b9 ldr r1, [r7, #24] 801310e: 69fa ldr r2, [r7, #28] 8013110: e841 2300 strex r3, r2, [r1] 8013114: 617b str r3, [r7, #20] return(result); 8013116: 697b ldr r3, [r7, #20] 8013118: 2b00 cmp r3, #0 801311a: d1e6 bne.n 80130ea break; /* force exit loop */ 801311c: e021 b.n 8013162 } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 801311e: 687b ldr r3, [r7, #4] 8013120: 681b ldr r3, [r3, #0] 8013122: 69db ldr r3, [r3, #28] 8013124: f003 0380 and.w r3, r3, #128 @ 0x80 8013128: 2b00 cmp r3, #0 801312a: d013 beq.n 8013154 { huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 801312c: 687b ldr r3, [r7, #4] 801312e: 6d1b ldr r3, [r3, #80] @ 0x50 8013130: 781a ldrb r2, [r3, #0] 8013132: 687b ldr r3, [r7, #4] 8013134: 681b ldr r3, [r3, #0] 8013136: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 8013138: 687b ldr r3, [r7, #4] 801313a: 6d1b ldr r3, [r3, #80] @ 0x50 801313c: 1c5a adds r2, r3, #1 801313e: 687b ldr r3, [r7, #4] 8013140: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 8013142: 687b ldr r3, [r7, #4] 8013144: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8013148: b29b uxth r3, r3 801314a: 3b01 subs r3, #1 801314c: b29a uxth r2, r3 801314e: 687b ldr r3, [r7, #4] 8013150: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 8013154: 8ffb ldrh r3, [r7, #62] @ 0x3e 8013156: 3b01 subs r3, #1 8013158: 87fb strh r3, [r7, #62] @ 0x3e 801315a: 8ffb ldrh r3, [r7, #62] @ 0x3e 801315c: 2b00 cmp r3, #0 801315e: d1a4 bne.n 80130aa { /* Nothing to do */ } } } } 8013160: e7ff b.n 8013162 8013162: bf00 nop 8013164: 3744 adds r7, #68 @ 0x44 8013166: 46bd mov sp, r7 8013168: f85d 7b04 ldr.w r7, [sp], #4 801316c: 4770 bx lr 0801316e : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 801316e: b480 push {r7} 8013170: b091 sub sp, #68 @ 0x44 8013172: af00 add r7, sp, #0 8013174: 6078 str r0, [r7, #4] const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8013176: 687b ldr r3, [r7, #4] 8013178: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 801317c: 2b21 cmp r3, #33 @ 0x21 801317e: d165 bne.n 801324c { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 8013180: 687b ldr r3, [r7, #4] 8013182: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 8013186: 87fb strh r3, [r7, #62] @ 0x3e 8013188: e05c b.n 8013244 { if (huart->TxXferCount == 0U) 801318a: 687b ldr r3, [r7, #4] 801318c: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8013190: b29b uxth r3, r3 8013192: 2b00 cmp r3, #0 8013194: d133 bne.n 80131fe { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 8013196: 687b ldr r3, [r7, #4] 8013198: 681b ldr r3, [r3, #0] 801319a: 3308 adds r3, #8 801319c: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801319e: 6a3b ldr r3, [r7, #32] 80131a0: e853 3f00 ldrex r3, [r3] 80131a4: 61fb str r3, [r7, #28] return(result); 80131a6: 69fb ldr r3, [r7, #28] 80131a8: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 80131ac: 637b str r3, [r7, #52] @ 0x34 80131ae: 687b ldr r3, [r7, #4] 80131b0: 681b ldr r3, [r3, #0] 80131b2: 3308 adds r3, #8 80131b4: 6b7a ldr r2, [r7, #52] @ 0x34 80131b6: 62fa str r2, [r7, #44] @ 0x2c 80131b8: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80131ba: 6ab9 ldr r1, [r7, #40] @ 0x28 80131bc: 6afa ldr r2, [r7, #44] @ 0x2c 80131be: e841 2300 strex r3, r2, [r1] 80131c2: 627b str r3, [r7, #36] @ 0x24 return(result); 80131c4: 6a7b ldr r3, [r7, #36] @ 0x24 80131c6: 2b00 cmp r3, #0 80131c8: d1e5 bne.n 8013196 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80131ca: 687b ldr r3, [r7, #4] 80131cc: 681b ldr r3, [r3, #0] 80131ce: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80131d0: 68fb ldr r3, [r7, #12] 80131d2: e853 3f00 ldrex r3, [r3] 80131d6: 60bb str r3, [r7, #8] return(result); 80131d8: 68bb ldr r3, [r7, #8] 80131da: f043 0340 orr.w r3, r3, #64 @ 0x40 80131de: 633b str r3, [r7, #48] @ 0x30 80131e0: 687b ldr r3, [r7, #4] 80131e2: 681b ldr r3, [r3, #0] 80131e4: 461a mov r2, r3 80131e6: 6b3b ldr r3, [r7, #48] @ 0x30 80131e8: 61bb str r3, [r7, #24] 80131ea: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80131ec: 6979 ldr r1, [r7, #20] 80131ee: 69ba ldr r2, [r7, #24] 80131f0: e841 2300 strex r3, r2, [r1] 80131f4: 613b str r3, [r7, #16] return(result); 80131f6: 693b ldr r3, [r7, #16] 80131f8: 2b00 cmp r3, #0 80131fa: d1e6 bne.n 80131ca break; /* force exit loop */ 80131fc: e026 b.n 801324c } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 80131fe: 687b ldr r3, [r7, #4] 8013200: 681b ldr r3, [r3, #0] 8013202: 69db ldr r3, [r3, #28] 8013204: f003 0380 and.w r3, r3, #128 @ 0x80 8013208: 2b00 cmp r3, #0 801320a: d018 beq.n 801323e { tmp = (const uint16_t *) huart->pTxBuffPtr; 801320c: 687b ldr r3, [r7, #4] 801320e: 6d1b ldr r3, [r3, #80] @ 0x50 8013210: 63bb str r3, [r7, #56] @ 0x38 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 8013212: 6bbb ldr r3, [r7, #56] @ 0x38 8013214: 881b ldrh r3, [r3, #0] 8013216: 461a mov r2, r3 8013218: 687b ldr r3, [r7, #4] 801321a: 681b ldr r3, [r3, #0] 801321c: f3c2 0208 ubfx r2, r2, #0, #9 8013220: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 8013222: 687b ldr r3, [r7, #4] 8013224: 6d1b ldr r3, [r3, #80] @ 0x50 8013226: 1c9a adds r2, r3, #2 8013228: 687b ldr r3, [r7, #4] 801322a: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 801322c: 687b ldr r3, [r7, #4] 801322e: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8013232: b29b uxth r3, r3 8013234: 3b01 subs r3, #1 8013236: b29a uxth r2, r3 8013238: 687b ldr r3, [r7, #4] 801323a: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 801323e: 8ffb ldrh r3, [r7, #62] @ 0x3e 8013240: 3b01 subs r3, #1 8013242: 87fb strh r3, [r7, #62] @ 0x3e 8013244: 8ffb ldrh r3, [r7, #62] @ 0x3e 8013246: 2b00 cmp r3, #0 8013248: d19f bne.n 801318a { /* Nothing to do */ } } } } 801324a: e7ff b.n 801324c 801324c: bf00 nop 801324e: 3744 adds r7, #68 @ 0x44 8013250: 46bd mov sp, r7 8013252: f85d 7b04 ldr.w r7, [sp], #4 8013256: 4770 bx lr 08013258 : * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8013258: b580 push {r7, lr} 801325a: b088 sub sp, #32 801325c: af00 add r7, sp, #0 801325e: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8013260: 687b ldr r3, [r7, #4] 8013262: 681b ldr r3, [r3, #0] 8013264: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013266: 68fb ldr r3, [r7, #12] 8013268: e853 3f00 ldrex r3, [r3] 801326c: 60bb str r3, [r7, #8] return(result); 801326e: 68bb ldr r3, [r7, #8] 8013270: f023 0340 bic.w r3, r3, #64 @ 0x40 8013274: 61fb str r3, [r7, #28] 8013276: 687b ldr r3, [r7, #4] 8013278: 681b ldr r3, [r3, #0] 801327a: 461a mov r2, r3 801327c: 69fb ldr r3, [r7, #28] 801327e: 61bb str r3, [r7, #24] 8013280: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013282: 6979 ldr r1, [r7, #20] 8013284: 69ba ldr r2, [r7, #24] 8013286: e841 2300 strex r3, r2, [r1] 801328a: 613b str r3, [r7, #16] return(result); 801328c: 693b ldr r3, [r7, #16] 801328e: 2b00 cmp r3, #0 8013290: d1e6 bne.n 8013260 /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8013292: 687b ldr r3, [r7, #4] 8013294: 2220 movs r2, #32 8013296: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Cleat TxISR function pointer */ huart->TxISR = NULL; 801329a: 687b ldr r3, [r7, #4] 801329c: 2200 movs r2, #0 801329e: 679a str r2, [r3, #120] @ 0x78 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 80132a0: 6878 ldr r0, [r7, #4] 80132a2: f7f1 fc8d bl 8004bc0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80132a6: bf00 nop 80132a8: 3720 adds r7, #32 80132aa: 46bd mov sp, r7 80132ac: bd80 pop {r7, pc} ... 080132b0 : * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) { 80132b0: b580 push {r7, lr} 80132b2: b09c sub sp, #112 @ 0x70 80132b4: af00 add r7, sp, #0 80132b6: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 80132b8: 687b ldr r3, [r7, #4] 80132ba: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 80132be: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80132c2: 687b ldr r3, [r7, #4] 80132c4: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80132c8: 2b22 cmp r3, #34 @ 0x22 80132ca: f040 80be bne.w 801344a { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 80132ce: 687b ldr r3, [r7, #4] 80132d0: 681b ldr r3, [r3, #0] 80132d2: 6a5b ldr r3, [r3, #36] @ 0x24 80132d4: f8a7 306c strh.w r3, [r7, #108] @ 0x6c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 80132d8: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 80132dc: b2d9 uxtb r1, r3 80132de: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 80132e2: b2da uxtb r2, r3 80132e4: 687b ldr r3, [r7, #4] 80132e6: 6d9b ldr r3, [r3, #88] @ 0x58 80132e8: 400a ands r2, r1 80132ea: b2d2 uxtb r2, r2 80132ec: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 80132ee: 687b ldr r3, [r7, #4] 80132f0: 6d9b ldr r3, [r3, #88] @ 0x58 80132f2: 1c5a adds r2, r3, #1 80132f4: 687b ldr r3, [r7, #4] 80132f6: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 80132f8: 687b ldr r3, [r7, #4] 80132fa: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80132fe: b29b uxth r3, r3 8013300: 3b01 subs r3, #1 8013302: b29a uxth r2, r3 8013304: 687b ldr r3, [r7, #4] 8013306: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 801330a: 687b ldr r3, [r7, #4] 801330c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013310: b29b uxth r3, r3 8013312: 2b00 cmp r3, #0 8013314: f040 80a1 bne.w 801345a { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8013318: 687b ldr r3, [r7, #4] 801331a: 681b ldr r3, [r3, #0] 801331c: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801331e: 6cfb ldr r3, [r7, #76] @ 0x4c 8013320: e853 3f00 ldrex r3, [r3] 8013324: 64bb str r3, [r7, #72] @ 0x48 return(result); 8013326: 6cbb ldr r3, [r7, #72] @ 0x48 8013328: f423 7390 bic.w r3, r3, #288 @ 0x120 801332c: 66bb str r3, [r7, #104] @ 0x68 801332e: 687b ldr r3, [r7, #4] 8013330: 681b ldr r3, [r3, #0] 8013332: 461a mov r2, r3 8013334: 6ebb ldr r3, [r7, #104] @ 0x68 8013336: 65bb str r3, [r7, #88] @ 0x58 8013338: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801333a: 6d79 ldr r1, [r7, #84] @ 0x54 801333c: 6dba ldr r2, [r7, #88] @ 0x58 801333e: e841 2300 strex r3, r2, [r1] 8013342: 653b str r3, [r7, #80] @ 0x50 return(result); 8013344: 6d3b ldr r3, [r7, #80] @ 0x50 8013346: 2b00 cmp r3, #0 8013348: d1e6 bne.n 8013318 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 801334a: 687b ldr r3, [r7, #4] 801334c: 681b ldr r3, [r3, #0] 801334e: 3308 adds r3, #8 8013350: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013352: 6bbb ldr r3, [r7, #56] @ 0x38 8013354: e853 3f00 ldrex r3, [r3] 8013358: 637b str r3, [r7, #52] @ 0x34 return(result); 801335a: 6b7b ldr r3, [r7, #52] @ 0x34 801335c: f023 0301 bic.w r3, r3, #1 8013360: 667b str r3, [r7, #100] @ 0x64 8013362: 687b ldr r3, [r7, #4] 8013364: 681b ldr r3, [r3, #0] 8013366: 3308 adds r3, #8 8013368: 6e7a ldr r2, [r7, #100] @ 0x64 801336a: 647a str r2, [r7, #68] @ 0x44 801336c: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801336e: 6c39 ldr r1, [r7, #64] @ 0x40 8013370: 6c7a ldr r2, [r7, #68] @ 0x44 8013372: e841 2300 strex r3, r2, [r1] 8013376: 63fb str r3, [r7, #60] @ 0x3c return(result); 8013378: 6bfb ldr r3, [r7, #60] @ 0x3c 801337a: 2b00 cmp r3, #0 801337c: d1e5 bne.n 801334a /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 801337e: 687b ldr r3, [r7, #4] 8013380: 2220 movs r2, #32 8013382: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8013386: 687b ldr r3, [r7, #4] 8013388: 2200 movs r2, #0 801338a: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 801338c: 687b ldr r3, [r7, #4] 801338e: 2200 movs r2, #0 8013390: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8013392: 687b ldr r3, [r7, #4] 8013394: 681b ldr r3, [r3, #0] 8013396: 4a33 ldr r2, [pc, #204] @ (8013464 ) 8013398: 4293 cmp r3, r2 801339a: d01f beq.n 80133dc { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 801339c: 687b ldr r3, [r7, #4] 801339e: 681b ldr r3, [r3, #0] 80133a0: 685b ldr r3, [r3, #4] 80133a2: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80133a6: 2b00 cmp r3, #0 80133a8: d018 beq.n 80133dc { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 80133aa: 687b ldr r3, [r7, #4] 80133ac: 681b ldr r3, [r3, #0] 80133ae: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80133b0: 6a7b ldr r3, [r7, #36] @ 0x24 80133b2: e853 3f00 ldrex r3, [r3] 80133b6: 623b str r3, [r7, #32] return(result); 80133b8: 6a3b ldr r3, [r7, #32] 80133ba: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 80133be: 663b str r3, [r7, #96] @ 0x60 80133c0: 687b ldr r3, [r7, #4] 80133c2: 681b ldr r3, [r3, #0] 80133c4: 461a mov r2, r3 80133c6: 6e3b ldr r3, [r7, #96] @ 0x60 80133c8: 633b str r3, [r7, #48] @ 0x30 80133ca: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80133cc: 6af9 ldr r1, [r7, #44] @ 0x2c 80133ce: 6b3a ldr r2, [r7, #48] @ 0x30 80133d0: e841 2300 strex r3, r2, [r1] 80133d4: 62bb str r3, [r7, #40] @ 0x28 return(result); 80133d6: 6abb ldr r3, [r7, #40] @ 0x28 80133d8: 2b00 cmp r3, #0 80133da: d1e6 bne.n 80133aa } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80133dc: 687b ldr r3, [r7, #4] 80133de: 6edb ldr r3, [r3, #108] @ 0x6c 80133e0: 2b01 cmp r3, #1 80133e2: d12e bne.n 8013442 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80133e4: 687b ldr r3, [r7, #4] 80133e6: 2200 movs r2, #0 80133e8: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80133ea: 687b ldr r3, [r7, #4] 80133ec: 681b ldr r3, [r3, #0] 80133ee: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80133f0: 693b ldr r3, [r7, #16] 80133f2: e853 3f00 ldrex r3, [r3] 80133f6: 60fb str r3, [r7, #12] return(result); 80133f8: 68fb ldr r3, [r7, #12] 80133fa: f023 0310 bic.w r3, r3, #16 80133fe: 65fb str r3, [r7, #92] @ 0x5c 8013400: 687b ldr r3, [r7, #4] 8013402: 681b ldr r3, [r3, #0] 8013404: 461a mov r2, r3 8013406: 6dfb ldr r3, [r7, #92] @ 0x5c 8013408: 61fb str r3, [r7, #28] 801340a: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801340c: 69b9 ldr r1, [r7, #24] 801340e: 69fa ldr r2, [r7, #28] 8013410: e841 2300 strex r3, r2, [r1] 8013414: 617b str r3, [r7, #20] return(result); 8013416: 697b ldr r3, [r7, #20] 8013418: 2b00 cmp r3, #0 801341a: d1e6 bne.n 80133ea if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 801341c: 687b ldr r3, [r7, #4] 801341e: 681b ldr r3, [r3, #0] 8013420: 69db ldr r3, [r3, #28] 8013422: f003 0310 and.w r3, r3, #16 8013426: 2b10 cmp r3, #16 8013428: d103 bne.n 8013432 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 801342a: 687b ldr r3, [r7, #4] 801342c: 681b ldr r3, [r3, #0] 801342e: 2210 movs r2, #16 8013430: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8013432: 687b ldr r3, [r7, #4] 8013434: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8013438: 4619 mov r1, r3 801343a: 6878 ldr r0, [r7, #4] 801343c: f7f1 fb96 bl 8004b6c else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8013440: e00b b.n 801345a HAL_UART_RxCpltCallback(huart); 8013442: 6878 ldr r0, [r7, #4] 8013444: f7f1 fb88 bl 8004b58 } 8013448: e007 b.n 801345a __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 801344a: 687b ldr r3, [r7, #4] 801344c: 681b ldr r3, [r3, #0] 801344e: 699a ldr r2, [r3, #24] 8013450: 687b ldr r3, [r7, #4] 8013452: 681b ldr r3, [r3, #0] 8013454: f042 0208 orr.w r2, r2, #8 8013458: 619a str r2, [r3, #24] } 801345a: bf00 nop 801345c: 3770 adds r7, #112 @ 0x70 801345e: 46bd mov sp, r7 8013460: bd80 pop {r7, pc} 8013462: bf00 nop 8013464: 58000c00 .word 0x58000c00 08013468 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { 8013468: b580 push {r7, lr} 801346a: b09c sub sp, #112 @ 0x70 801346c: af00 add r7, sp, #0 801346e: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 8013470: 687b ldr r3, [r7, #4] 8013472: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8013476: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 801347a: 687b ldr r3, [r7, #4] 801347c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8013480: 2b22 cmp r3, #34 @ 0x22 8013482: f040 80be bne.w 8013602 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8013486: 687b ldr r3, [r7, #4] 8013488: 681b ldr r3, [r3, #0] 801348a: 6a5b ldr r3, [r3, #36] @ 0x24 801348c: f8a7 306c strh.w r3, [r7, #108] @ 0x6c tmp = (uint16_t *) huart->pRxBuffPtr ; 8013490: 687b ldr r3, [r7, #4] 8013492: 6d9b ldr r3, [r3, #88] @ 0x58 8013494: 66bb str r3, [r7, #104] @ 0x68 *tmp = (uint16_t)(uhdata & uhMask); 8013496: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c 801349a: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 801349e: 4013 ands r3, r2 80134a0: b29a uxth r2, r3 80134a2: 6ebb ldr r3, [r7, #104] @ 0x68 80134a4: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 80134a6: 687b ldr r3, [r7, #4] 80134a8: 6d9b ldr r3, [r3, #88] @ 0x58 80134aa: 1c9a adds r2, r3, #2 80134ac: 687b ldr r3, [r7, #4] 80134ae: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 80134b0: 687b ldr r3, [r7, #4] 80134b2: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80134b6: b29b uxth r3, r3 80134b8: 3b01 subs r3, #1 80134ba: b29a uxth r2, r3 80134bc: 687b ldr r3, [r7, #4] 80134be: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 80134c2: 687b ldr r3, [r7, #4] 80134c4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80134c8: b29b uxth r3, r3 80134ca: 2b00 cmp r3, #0 80134cc: f040 80a1 bne.w 8013612 { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 80134d0: 687b ldr r3, [r7, #4] 80134d2: 681b ldr r3, [r3, #0] 80134d4: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80134d6: 6cbb ldr r3, [r7, #72] @ 0x48 80134d8: e853 3f00 ldrex r3, [r3] 80134dc: 647b str r3, [r7, #68] @ 0x44 return(result); 80134de: 6c7b ldr r3, [r7, #68] @ 0x44 80134e0: f423 7390 bic.w r3, r3, #288 @ 0x120 80134e4: 667b str r3, [r7, #100] @ 0x64 80134e6: 687b ldr r3, [r7, #4] 80134e8: 681b ldr r3, [r3, #0] 80134ea: 461a mov r2, r3 80134ec: 6e7b ldr r3, [r7, #100] @ 0x64 80134ee: 657b str r3, [r7, #84] @ 0x54 80134f0: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80134f2: 6d39 ldr r1, [r7, #80] @ 0x50 80134f4: 6d7a ldr r2, [r7, #84] @ 0x54 80134f6: e841 2300 strex r3, r2, [r1] 80134fa: 64fb str r3, [r7, #76] @ 0x4c return(result); 80134fc: 6cfb ldr r3, [r7, #76] @ 0x4c 80134fe: 2b00 cmp r3, #0 8013500: d1e6 bne.n 80134d0 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013502: 687b ldr r3, [r7, #4] 8013504: 681b ldr r3, [r3, #0] 8013506: 3308 adds r3, #8 8013508: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801350a: 6b7b ldr r3, [r7, #52] @ 0x34 801350c: e853 3f00 ldrex r3, [r3] 8013510: 633b str r3, [r7, #48] @ 0x30 return(result); 8013512: 6b3b ldr r3, [r7, #48] @ 0x30 8013514: f023 0301 bic.w r3, r3, #1 8013518: 663b str r3, [r7, #96] @ 0x60 801351a: 687b ldr r3, [r7, #4] 801351c: 681b ldr r3, [r3, #0] 801351e: 3308 adds r3, #8 8013520: 6e3a ldr r2, [r7, #96] @ 0x60 8013522: 643a str r2, [r7, #64] @ 0x40 8013524: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013526: 6bf9 ldr r1, [r7, #60] @ 0x3c 8013528: 6c3a ldr r2, [r7, #64] @ 0x40 801352a: e841 2300 strex r3, r2, [r1] 801352e: 63bb str r3, [r7, #56] @ 0x38 return(result); 8013530: 6bbb ldr r3, [r7, #56] @ 0x38 8013532: 2b00 cmp r3, #0 8013534: d1e5 bne.n 8013502 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013536: 687b ldr r3, [r7, #4] 8013538: 2220 movs r2, #32 801353a: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 801353e: 687b ldr r3, [r7, #4] 8013540: 2200 movs r2, #0 8013542: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8013544: 687b ldr r3, [r7, #4] 8013546: 2200 movs r2, #0 8013548: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 801354a: 687b ldr r3, [r7, #4] 801354c: 681b ldr r3, [r3, #0] 801354e: 4a33 ldr r2, [pc, #204] @ (801361c ) 8013550: 4293 cmp r3, r2 8013552: d01f beq.n 8013594 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8013554: 687b ldr r3, [r7, #4] 8013556: 681b ldr r3, [r3, #0] 8013558: 685b ldr r3, [r3, #4] 801355a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 801355e: 2b00 cmp r3, #0 8013560: d018 beq.n 8013594 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8013562: 687b ldr r3, [r7, #4] 8013564: 681b ldr r3, [r3, #0] 8013566: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013568: 6a3b ldr r3, [r7, #32] 801356a: e853 3f00 ldrex r3, [r3] 801356e: 61fb str r3, [r7, #28] return(result); 8013570: 69fb ldr r3, [r7, #28] 8013572: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8013576: 65fb str r3, [r7, #92] @ 0x5c 8013578: 687b ldr r3, [r7, #4] 801357a: 681b ldr r3, [r3, #0] 801357c: 461a mov r2, r3 801357e: 6dfb ldr r3, [r7, #92] @ 0x5c 8013580: 62fb str r3, [r7, #44] @ 0x2c 8013582: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013584: 6ab9 ldr r1, [r7, #40] @ 0x28 8013586: 6afa ldr r2, [r7, #44] @ 0x2c 8013588: e841 2300 strex r3, r2, [r1] 801358c: 627b str r3, [r7, #36] @ 0x24 return(result); 801358e: 6a7b ldr r3, [r7, #36] @ 0x24 8013590: 2b00 cmp r3, #0 8013592: d1e6 bne.n 8013562 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013594: 687b ldr r3, [r7, #4] 8013596: 6edb ldr r3, [r3, #108] @ 0x6c 8013598: 2b01 cmp r3, #1 801359a: d12e bne.n 80135fa { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801359c: 687b ldr r3, [r7, #4] 801359e: 2200 movs r2, #0 80135a0: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80135a2: 687b ldr r3, [r7, #4] 80135a4: 681b ldr r3, [r3, #0] 80135a6: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80135a8: 68fb ldr r3, [r7, #12] 80135aa: e853 3f00 ldrex r3, [r3] 80135ae: 60bb str r3, [r7, #8] return(result); 80135b0: 68bb ldr r3, [r7, #8] 80135b2: f023 0310 bic.w r3, r3, #16 80135b6: 65bb str r3, [r7, #88] @ 0x58 80135b8: 687b ldr r3, [r7, #4] 80135ba: 681b ldr r3, [r3, #0] 80135bc: 461a mov r2, r3 80135be: 6dbb ldr r3, [r7, #88] @ 0x58 80135c0: 61bb str r3, [r7, #24] 80135c2: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80135c4: 6979 ldr r1, [r7, #20] 80135c6: 69ba ldr r2, [r7, #24] 80135c8: e841 2300 strex r3, r2, [r1] 80135cc: 613b str r3, [r7, #16] return(result); 80135ce: 693b ldr r3, [r7, #16] 80135d0: 2b00 cmp r3, #0 80135d2: d1e6 bne.n 80135a2 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 80135d4: 687b ldr r3, [r7, #4] 80135d6: 681b ldr r3, [r3, #0] 80135d8: 69db ldr r3, [r3, #28] 80135da: f003 0310 and.w r3, r3, #16 80135de: 2b10 cmp r3, #16 80135e0: d103 bne.n 80135ea { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 80135e2: 687b ldr r3, [r7, #4] 80135e4: 681b ldr r3, [r3, #0] 80135e6: 2210 movs r2, #16 80135e8: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 80135ea: 687b ldr r3, [r7, #4] 80135ec: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 80135f0: 4619 mov r1, r3 80135f2: 6878 ldr r0, [r7, #4] 80135f4: f7f1 faba bl 8004b6c else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 80135f8: e00b b.n 8013612 HAL_UART_RxCpltCallback(huart); 80135fa: 6878 ldr r0, [r7, #4] 80135fc: f7f1 faac bl 8004b58 } 8013600: e007 b.n 8013612 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8013602: 687b ldr r3, [r7, #4] 8013604: 681b ldr r3, [r3, #0] 8013606: 699a ldr r2, [r3, #24] 8013608: 687b ldr r3, [r7, #4] 801360a: 681b ldr r3, [r3, #0] 801360c: f042 0208 orr.w r2, r2, #8 8013610: 619a str r2, [r3, #24] } 8013612: bf00 nop 8013614: 3770 adds r7, #112 @ 0x70 8013616: 46bd mov sp, r7 8013618: bd80 pop {r7, pc} 801361a: bf00 nop 801361c: 58000c00 .word 0x58000c00 08013620 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 8013620: b580 push {r7, lr} 8013622: b0ac sub sp, #176 @ 0xb0 8013624: af00 add r7, sp, #0 8013626: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 8013628: 687b ldr r3, [r7, #4] 801362a: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 801362e: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 8013632: 687b ldr r3, [r7, #4] 8013634: 681b ldr r3, [r3, #0] 8013636: 69db ldr r3, [r3, #28] 8013638: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr1its = READ_REG(huart->Instance->CR1); 801363c: 687b ldr r3, [r7, #4] 801363e: 681b ldr r3, [r3, #0] 8013640: 681b ldr r3, [r3, #0] 8013642: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8013646: 687b ldr r3, [r7, #4] 8013648: 681b ldr r3, [r3, #0] 801364a: 689b ldr r3, [r3, #8] 801364c: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8013650: 687b ldr r3, [r7, #4] 8013652: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8013656: 2b22 cmp r3, #34 @ 0x22 8013658: f040 8180 bne.w 801395c { nb_rx_data = huart->NbRxDataToProcess; 801365c: 687b ldr r3, [r7, #4] 801365e: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8013662: f8a7 309e strh.w r3, [r7, #158] @ 0x9e while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8013666: e123 b.n 80138b0 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8013668: 687b ldr r3, [r7, #4] 801366a: 681b ldr r3, [r3, #0] 801366c: 6a5b ldr r3, [r3, #36] @ 0x24 801366e: f8a7 309c strh.w r3, [r7, #156] @ 0x9c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 8013672: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c 8013676: b2d9 uxtb r1, r3 8013678: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa 801367c: b2da uxtb r2, r3 801367e: 687b ldr r3, [r7, #4] 8013680: 6d9b ldr r3, [r3, #88] @ 0x58 8013682: 400a ands r2, r1 8013684: b2d2 uxtb r2, r2 8013686: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8013688: 687b ldr r3, [r7, #4] 801368a: 6d9b ldr r3, [r3, #88] @ 0x58 801368c: 1c5a adds r2, r3, #1 801368e: 687b ldr r3, [r7, #4] 8013690: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8013692: 687b ldr r3, [r7, #4] 8013694: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013698: b29b uxth r3, r3 801369a: 3b01 subs r3, #1 801369c: b29a uxth r2, r3 801369e: 687b ldr r3, [r7, #4] 80136a0: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 80136a4: 687b ldr r3, [r7, #4] 80136a6: 681b ldr r3, [r3, #0] 80136a8: 69db ldr r3, [r3, #28] 80136aa: f8c7 30ac str.w r3, [r7, #172] @ 0xac /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 80136ae: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80136b2: f003 0307 and.w r3, r3, #7 80136b6: 2b00 cmp r3, #0 80136b8: d053 beq.n 8013762 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 80136ba: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80136be: f003 0301 and.w r3, r3, #1 80136c2: 2b00 cmp r3, #0 80136c4: d011 beq.n 80136ea 80136c6: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 80136ca: f403 7380 and.w r3, r3, #256 @ 0x100 80136ce: 2b00 cmp r3, #0 80136d0: d00b beq.n 80136ea { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 80136d2: 687b ldr r3, [r7, #4] 80136d4: 681b ldr r3, [r3, #0] 80136d6: 2201 movs r2, #1 80136d8: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 80136da: 687b ldr r3, [r7, #4] 80136dc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80136e0: f043 0201 orr.w r2, r3, #1 80136e4: 687b ldr r3, [r7, #4] 80136e6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 80136ea: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80136ee: f003 0302 and.w r3, r3, #2 80136f2: 2b00 cmp r3, #0 80136f4: d011 beq.n 801371a 80136f6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80136fa: f003 0301 and.w r3, r3, #1 80136fe: 2b00 cmp r3, #0 8013700: d00b beq.n 801371a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8013702: 687b ldr r3, [r7, #4] 8013704: 681b ldr r3, [r3, #0] 8013706: 2202 movs r2, #2 8013708: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 801370a: 687b ldr r3, [r7, #4] 801370c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013710: f043 0204 orr.w r2, r3, #4 8013714: 687b ldr r3, [r7, #4] 8013716: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 801371a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801371e: f003 0304 and.w r3, r3, #4 8013722: 2b00 cmp r3, #0 8013724: d011 beq.n 801374a 8013726: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 801372a: f003 0301 and.w r3, r3, #1 801372e: 2b00 cmp r3, #0 8013730: d00b beq.n 801374a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8013732: 687b ldr r3, [r7, #4] 8013734: 681b ldr r3, [r3, #0] 8013736: 2204 movs r2, #4 8013738: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 801373a: 687b ldr r3, [r7, #4] 801373c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013740: f043 0202 orr.w r2, r3, #2 8013744: 687b ldr r3, [r7, #4] 8013746: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 801374a: 687b ldr r3, [r7, #4] 801374c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013750: 2b00 cmp r3, #0 8013752: d006 beq.n 8013762 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013754: 6878 ldr r0, [r7, #4] 8013756: f7fe fb13 bl 8011d80 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 801375a: 687b ldr r3, [r7, #4] 801375c: 2200 movs r2, #0 801375e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 8013762: 687b ldr r3, [r7, #4] 8013764: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013768: b29b uxth r3, r3 801376a: 2b00 cmp r3, #0 801376c: f040 80a0 bne.w 80138b0 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8013770: 687b ldr r3, [r7, #4] 8013772: 681b ldr r3, [r3, #0] 8013774: 673b str r3, [r7, #112] @ 0x70 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013776: 6f3b ldr r3, [r7, #112] @ 0x70 8013778: e853 3f00 ldrex r3, [r3] 801377c: 66fb str r3, [r7, #108] @ 0x6c return(result); 801377e: 6efb ldr r3, [r7, #108] @ 0x6c 8013780: f423 7380 bic.w r3, r3, #256 @ 0x100 8013784: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8013788: 687b ldr r3, [r7, #4] 801378a: 681b ldr r3, [r3, #0] 801378c: 461a mov r2, r3 801378e: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8013792: 67fb str r3, [r7, #124] @ 0x7c 8013794: 67ba str r2, [r7, #120] @ 0x78 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013796: 6fb9 ldr r1, [r7, #120] @ 0x78 8013798: 6ffa ldr r2, [r7, #124] @ 0x7c 801379a: e841 2300 strex r3, r2, [r1] 801379e: 677b str r3, [r7, #116] @ 0x74 return(result); 80137a0: 6f7b ldr r3, [r7, #116] @ 0x74 80137a2: 2b00 cmp r3, #0 80137a4: d1e4 bne.n 8013770 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 80137a6: 687b ldr r3, [r7, #4] 80137a8: 681b ldr r3, [r3, #0] 80137aa: 3308 adds r3, #8 80137ac: 65fb str r3, [r7, #92] @ 0x5c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80137ae: 6dfb ldr r3, [r7, #92] @ 0x5c 80137b0: e853 3f00 ldrex r3, [r3] 80137b4: 65bb str r3, [r7, #88] @ 0x58 return(result); 80137b6: 6dba ldr r2, [r7, #88] @ 0x58 80137b8: 4b6e ldr r3, [pc, #440] @ (8013974 ) 80137ba: 4013 ands r3, r2 80137bc: f8c7 3094 str.w r3, [r7, #148] @ 0x94 80137c0: 687b ldr r3, [r7, #4] 80137c2: 681b ldr r3, [r3, #0] 80137c4: 3308 adds r3, #8 80137c6: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 80137ca: 66ba str r2, [r7, #104] @ 0x68 80137cc: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80137ce: 6e79 ldr r1, [r7, #100] @ 0x64 80137d0: 6eba ldr r2, [r7, #104] @ 0x68 80137d2: e841 2300 strex r3, r2, [r1] 80137d6: 663b str r3, [r7, #96] @ 0x60 return(result); 80137d8: 6e3b ldr r3, [r7, #96] @ 0x60 80137da: 2b00 cmp r3, #0 80137dc: d1e3 bne.n 80137a6 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80137de: 687b ldr r3, [r7, #4] 80137e0: 2220 movs r2, #32 80137e2: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 80137e6: 687b ldr r3, [r7, #4] 80137e8: 2200 movs r2, #0 80137ea: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80137ec: 687b ldr r3, [r7, #4] 80137ee: 2200 movs r2, #0 80137f0: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 80137f2: 687b ldr r3, [r7, #4] 80137f4: 681b ldr r3, [r3, #0] 80137f6: 4a60 ldr r2, [pc, #384] @ (8013978 ) 80137f8: 4293 cmp r3, r2 80137fa: d021 beq.n 8013840 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 80137fc: 687b ldr r3, [r7, #4] 80137fe: 681b ldr r3, [r3, #0] 8013800: 685b ldr r3, [r3, #4] 8013802: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8013806: 2b00 cmp r3, #0 8013808: d01a beq.n 8013840 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 801380a: 687b ldr r3, [r7, #4] 801380c: 681b ldr r3, [r3, #0] 801380e: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013810: 6cbb ldr r3, [r7, #72] @ 0x48 8013812: e853 3f00 ldrex r3, [r3] 8013816: 647b str r3, [r7, #68] @ 0x44 return(result); 8013818: 6c7b ldr r3, [r7, #68] @ 0x44 801381a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 801381e: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8013822: 687b ldr r3, [r7, #4] 8013824: 681b ldr r3, [r3, #0] 8013826: 461a mov r2, r3 8013828: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 801382c: 657b str r3, [r7, #84] @ 0x54 801382e: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013830: 6d39 ldr r1, [r7, #80] @ 0x50 8013832: 6d7a ldr r2, [r7, #84] @ 0x54 8013834: e841 2300 strex r3, r2, [r1] 8013838: 64fb str r3, [r7, #76] @ 0x4c return(result); 801383a: 6cfb ldr r3, [r7, #76] @ 0x4c 801383c: 2b00 cmp r3, #0 801383e: d1e4 bne.n 801380a } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013840: 687b ldr r3, [r7, #4] 8013842: 6edb ldr r3, [r3, #108] @ 0x6c 8013844: 2b01 cmp r3, #1 8013846: d130 bne.n 80138aa { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013848: 687b ldr r3, [r7, #4] 801384a: 2200 movs r2, #0 801384c: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801384e: 687b ldr r3, [r7, #4] 8013850: 681b ldr r3, [r3, #0] 8013852: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013854: 6b7b ldr r3, [r7, #52] @ 0x34 8013856: e853 3f00 ldrex r3, [r3] 801385a: 633b str r3, [r7, #48] @ 0x30 return(result); 801385c: 6b3b ldr r3, [r7, #48] @ 0x30 801385e: f023 0310 bic.w r3, r3, #16 8013862: f8c7 308c str.w r3, [r7, #140] @ 0x8c 8013866: 687b ldr r3, [r7, #4] 8013868: 681b ldr r3, [r3, #0] 801386a: 461a mov r2, r3 801386c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8013870: 643b str r3, [r7, #64] @ 0x40 8013872: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013874: 6bf9 ldr r1, [r7, #60] @ 0x3c 8013876: 6c3a ldr r2, [r7, #64] @ 0x40 8013878: e841 2300 strex r3, r2, [r1] 801387c: 63bb str r3, [r7, #56] @ 0x38 return(result); 801387e: 6bbb ldr r3, [r7, #56] @ 0x38 8013880: 2b00 cmp r3, #0 8013882: d1e4 bne.n 801384e if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8013884: 687b ldr r3, [r7, #4] 8013886: 681b ldr r3, [r3, #0] 8013888: 69db ldr r3, [r3, #28] 801388a: f003 0310 and.w r3, r3, #16 801388e: 2b10 cmp r3, #16 8013890: d103 bne.n 801389a { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8013892: 687b ldr r3, [r7, #4] 8013894: 681b ldr r3, [r3, #0] 8013896: 2210 movs r2, #16 8013898: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 801389a: 687b ldr r3, [r7, #4] 801389c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 80138a0: 4619 mov r1, r3 80138a2: 6878 ldr r0, [r7, #4] 80138a4: f7f1 f962 bl 8004b6c 80138a8: e002 b.n 80138b0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 80138aa: 6878 ldr r0, [r7, #4] 80138ac: f7f1 f954 bl 8004b58 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 80138b0: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e 80138b4: 2b00 cmp r3, #0 80138b6: d006 beq.n 80138c6 80138b8: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80138bc: f003 0320 and.w r3, r3, #32 80138c0: 2b00 cmp r3, #0 80138c2: f47f aed1 bne.w 8013668 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 80138c6: 687b ldr r3, [r7, #4] 80138c8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80138cc: f8a7 308a strh.w r3, [r7, #138] @ 0x8a if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 80138d0: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 80138d4: 2b00 cmp r3, #0 80138d6: d049 beq.n 801396c 80138d8: 687b ldr r3, [r7, #4] 80138da: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 80138de: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a 80138e2: 429a cmp r2, r3 80138e4: d242 bcs.n 801396c { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 80138e6: 687b ldr r3, [r7, #4] 80138e8: 681b ldr r3, [r3, #0] 80138ea: 3308 adds r3, #8 80138ec: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80138ee: 6a3b ldr r3, [r7, #32] 80138f0: e853 3f00 ldrex r3, [r3] 80138f4: 61fb str r3, [r7, #28] return(result); 80138f6: 69fb ldr r3, [r7, #28] 80138f8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80138fc: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8013900: 687b ldr r3, [r7, #4] 8013902: 681b ldr r3, [r3, #0] 8013904: 3308 adds r3, #8 8013906: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 801390a: 62fa str r2, [r7, #44] @ 0x2c 801390c: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801390e: 6ab9 ldr r1, [r7, #40] @ 0x28 8013910: 6afa ldr r2, [r7, #44] @ 0x2c 8013912: e841 2300 strex r3, r2, [r1] 8013916: 627b str r3, [r7, #36] @ 0x24 return(result); 8013918: 6a7b ldr r3, [r7, #36] @ 0x24 801391a: 2b00 cmp r3, #0 801391c: d1e3 bne.n 80138e6 /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; 801391e: 687b ldr r3, [r7, #4] 8013920: 4a16 ldr r2, [pc, #88] @ (801397c ) 8013922: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8013924: 687b ldr r3, [r7, #4] 8013926: 681b ldr r3, [r3, #0] 8013928: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801392a: 68fb ldr r3, [r7, #12] 801392c: e853 3f00 ldrex r3, [r3] 8013930: 60bb str r3, [r7, #8] return(result); 8013932: 68bb ldr r3, [r7, #8] 8013934: f043 0320 orr.w r3, r3, #32 8013938: f8c7 3080 str.w r3, [r7, #128] @ 0x80 801393c: 687b ldr r3, [r7, #4] 801393e: 681b ldr r3, [r3, #0] 8013940: 461a mov r2, r3 8013942: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8013946: 61bb str r3, [r7, #24] 8013948: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801394a: 6979 ldr r1, [r7, #20] 801394c: 69ba ldr r2, [r7, #24] 801394e: e841 2300 strex r3, r2, [r1] 8013952: 613b str r3, [r7, #16] return(result); 8013954: 693b ldr r3, [r7, #16] 8013956: 2b00 cmp r3, #0 8013958: d1e4 bne.n 8013924 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 801395a: e007 b.n 801396c __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 801395c: 687b ldr r3, [r7, #4] 801395e: 681b ldr r3, [r3, #0] 8013960: 699a ldr r2, [r3, #24] 8013962: 687b ldr r3, [r7, #4] 8013964: 681b ldr r3, [r3, #0] 8013966: f042 0208 orr.w r2, r2, #8 801396a: 619a str r2, [r3, #24] } 801396c: bf00 nop 801396e: 37b0 adds r7, #176 @ 0xb0 8013970: 46bd mov sp, r7 8013972: bd80 pop {r7, pc} 8013974: effffffe .word 0xeffffffe 8013978: 58000c00 .word 0x58000c00 801397c: 080132b1 .word 0x080132b1 08013980 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 8013980: b580 push {r7, lr} 8013982: b0ae sub sp, #184 @ 0xb8 8013984: af00 add r7, sp, #0 8013986: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 8013988: 687b ldr r3, [r7, #4] 801398a: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 801398e: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2 uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 8013992: 687b ldr r3, [r7, #4] 8013994: 681b ldr r3, [r3, #0] 8013996: 69db ldr r3, [r3, #28] 8013998: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 801399c: 687b ldr r3, [r7, #4] 801399e: 681b ldr r3, [r3, #0] 80139a0: 681b ldr r3, [r3, #0] 80139a2: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr3its = READ_REG(huart->Instance->CR3); 80139a6: 687b ldr r3, [r7, #4] 80139a8: 681b ldr r3, [r3, #0] 80139aa: 689b ldr r3, [r3, #8] 80139ac: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80139b0: 687b ldr r3, [r7, #4] 80139b2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80139b6: 2b22 cmp r3, #34 @ 0x22 80139b8: f040 8184 bne.w 8013cc4 { nb_rx_data = huart->NbRxDataToProcess; 80139bc: 687b ldr r3, [r7, #4] 80139be: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 80139c2: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 80139c6: e127 b.n 8013c18 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 80139c8: 687b ldr r3, [r7, #4] 80139ca: 681b ldr r3, [r3, #0] 80139cc: 6a5b ldr r3, [r3, #36] @ 0x24 80139ce: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4 tmp = (uint16_t *) huart->pRxBuffPtr ; 80139d2: 687b ldr r3, [r7, #4] 80139d4: 6d9b ldr r3, [r3, #88] @ 0x58 80139d6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 *tmp = (uint16_t)(uhdata & uhMask); 80139da: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4 80139de: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2 80139e2: 4013 ands r3, r2 80139e4: b29a uxth r2, r3 80139e6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80139ea: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 80139ec: 687b ldr r3, [r7, #4] 80139ee: 6d9b ldr r3, [r3, #88] @ 0x58 80139f0: 1c9a adds r2, r3, #2 80139f2: 687b ldr r3, [r7, #4] 80139f4: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 80139f6: 687b ldr r3, [r7, #4] 80139f8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80139fc: b29b uxth r3, r3 80139fe: 3b01 subs r3, #1 8013a00: b29a uxth r2, r3 8013a02: 687b ldr r3, [r7, #4] 8013a04: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 8013a08: 687b ldr r3, [r7, #4] 8013a0a: 681b ldr r3, [r3, #0] 8013a0c: 69db ldr r3, [r3, #28] 8013a0e: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8013a12: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8013a16: f003 0307 and.w r3, r3, #7 8013a1a: 2b00 cmp r3, #0 8013a1c: d053 beq.n 8013ac6 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8013a1e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8013a22: f003 0301 and.w r3, r3, #1 8013a26: 2b00 cmp r3, #0 8013a28: d011 beq.n 8013a4e 8013a2a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8013a2e: f403 7380 and.w r3, r3, #256 @ 0x100 8013a32: 2b00 cmp r3, #0 8013a34: d00b beq.n 8013a4e { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8013a36: 687b ldr r3, [r7, #4] 8013a38: 681b ldr r3, [r3, #0] 8013a3a: 2201 movs r2, #1 8013a3c: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8013a3e: 687b ldr r3, [r7, #4] 8013a40: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013a44: f043 0201 orr.w r2, r3, #1 8013a48: 687b ldr r3, [r7, #4] 8013a4a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8013a4e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8013a52: f003 0302 and.w r3, r3, #2 8013a56: 2b00 cmp r3, #0 8013a58: d011 beq.n 8013a7e 8013a5a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8013a5e: f003 0301 and.w r3, r3, #1 8013a62: 2b00 cmp r3, #0 8013a64: d00b beq.n 8013a7e { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8013a66: 687b ldr r3, [r7, #4] 8013a68: 681b ldr r3, [r3, #0] 8013a6a: 2202 movs r2, #2 8013a6c: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8013a6e: 687b ldr r3, [r7, #4] 8013a70: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013a74: f043 0204 orr.w r2, r3, #4 8013a78: 687b ldr r3, [r7, #4] 8013a7a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8013a7e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8013a82: f003 0304 and.w r3, r3, #4 8013a86: 2b00 cmp r3, #0 8013a88: d011 beq.n 8013aae 8013a8a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8013a8e: f003 0301 and.w r3, r3, #1 8013a92: 2b00 cmp r3, #0 8013a94: d00b beq.n 8013aae { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8013a96: 687b ldr r3, [r7, #4] 8013a98: 681b ldr r3, [r3, #0] 8013a9a: 2204 movs r2, #4 8013a9c: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8013a9e: 687b ldr r3, [r7, #4] 8013aa0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013aa4: f043 0202 orr.w r2, r3, #2 8013aa8: 687b ldr r3, [r7, #4] 8013aaa: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8013aae: 687b ldr r3, [r7, #4] 8013ab0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013ab4: 2b00 cmp r3, #0 8013ab6: d006 beq.n 8013ac6 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013ab8: 6878 ldr r0, [r7, #4] 8013aba: f7fe f961 bl 8011d80 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8013abe: 687b ldr r3, [r7, #4] 8013ac0: 2200 movs r2, #0 8013ac2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 8013ac6: 687b ldr r3, [r7, #4] 8013ac8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013acc: b29b uxth r3, r3 8013ace: 2b00 cmp r3, #0 8013ad0: f040 80a2 bne.w 8013c18 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8013ad4: 687b ldr r3, [r7, #4] 8013ad6: 681b ldr r3, [r3, #0] 8013ad8: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013ada: 6f7b ldr r3, [r7, #116] @ 0x74 8013adc: e853 3f00 ldrex r3, [r3] 8013ae0: 673b str r3, [r7, #112] @ 0x70 return(result); 8013ae2: 6f3b ldr r3, [r7, #112] @ 0x70 8013ae4: f423 7380 bic.w r3, r3, #256 @ 0x100 8013ae8: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8013aec: 687b ldr r3, [r7, #4] 8013aee: 681b ldr r3, [r3, #0] 8013af0: 461a mov r2, r3 8013af2: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8013af6: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8013afa: 67fa str r2, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013afc: 6ff9 ldr r1, [r7, #124] @ 0x7c 8013afe: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8013b02: e841 2300 strex r3, r2, [r1] 8013b06: 67bb str r3, [r7, #120] @ 0x78 return(result); 8013b08: 6fbb ldr r3, [r7, #120] @ 0x78 8013b0a: 2b00 cmp r3, #0 8013b0c: d1e2 bne.n 8013ad4 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8013b0e: 687b ldr r3, [r7, #4] 8013b10: 681b ldr r3, [r3, #0] 8013b12: 3308 adds r3, #8 8013b14: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013b16: 6e3b ldr r3, [r7, #96] @ 0x60 8013b18: e853 3f00 ldrex r3, [r3] 8013b1c: 65fb str r3, [r7, #92] @ 0x5c return(result); 8013b1e: 6dfa ldr r2, [r7, #92] @ 0x5c 8013b20: 4b6e ldr r3, [pc, #440] @ (8013cdc ) 8013b22: 4013 ands r3, r2 8013b24: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8013b28: 687b ldr r3, [r7, #4] 8013b2a: 681b ldr r3, [r3, #0] 8013b2c: 3308 adds r3, #8 8013b2e: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98 8013b32: 66fa str r2, [r7, #108] @ 0x6c 8013b34: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013b36: 6eb9 ldr r1, [r7, #104] @ 0x68 8013b38: 6efa ldr r2, [r7, #108] @ 0x6c 8013b3a: e841 2300 strex r3, r2, [r1] 8013b3e: 667b str r3, [r7, #100] @ 0x64 return(result); 8013b40: 6e7b ldr r3, [r7, #100] @ 0x64 8013b42: 2b00 cmp r3, #0 8013b44: d1e3 bne.n 8013b0e /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013b46: 687b ldr r3, [r7, #4] 8013b48: 2220 movs r2, #32 8013b4a: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8013b4e: 687b ldr r3, [r7, #4] 8013b50: 2200 movs r2, #0 8013b52: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8013b54: 687b ldr r3, [r7, #4] 8013b56: 2200 movs r2, #0 8013b58: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8013b5a: 687b ldr r3, [r7, #4] 8013b5c: 681b ldr r3, [r3, #0] 8013b5e: 4a60 ldr r2, [pc, #384] @ (8013ce0 ) 8013b60: 4293 cmp r3, r2 8013b62: d021 beq.n 8013ba8 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8013b64: 687b ldr r3, [r7, #4] 8013b66: 681b ldr r3, [r3, #0] 8013b68: 685b ldr r3, [r3, #4] 8013b6a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8013b6e: 2b00 cmp r3, #0 8013b70: d01a beq.n 8013ba8 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8013b72: 687b ldr r3, [r7, #4] 8013b74: 681b ldr r3, [r3, #0] 8013b76: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013b78: 6cfb ldr r3, [r7, #76] @ 0x4c 8013b7a: e853 3f00 ldrex r3, [r3] 8013b7e: 64bb str r3, [r7, #72] @ 0x48 return(result); 8013b80: 6cbb ldr r3, [r7, #72] @ 0x48 8013b82: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8013b86: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8013b8a: 687b ldr r3, [r7, #4] 8013b8c: 681b ldr r3, [r3, #0] 8013b8e: 461a mov r2, r3 8013b90: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 8013b94: 65bb str r3, [r7, #88] @ 0x58 8013b96: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013b98: 6d79 ldr r1, [r7, #84] @ 0x54 8013b9a: 6dba ldr r2, [r7, #88] @ 0x58 8013b9c: e841 2300 strex r3, r2, [r1] 8013ba0: 653b str r3, [r7, #80] @ 0x50 return(result); 8013ba2: 6d3b ldr r3, [r7, #80] @ 0x50 8013ba4: 2b00 cmp r3, #0 8013ba6: d1e4 bne.n 8013b72 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013ba8: 687b ldr r3, [r7, #4] 8013baa: 6edb ldr r3, [r3, #108] @ 0x6c 8013bac: 2b01 cmp r3, #1 8013bae: d130 bne.n 8013c12 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013bb0: 687b ldr r3, [r7, #4] 8013bb2: 2200 movs r2, #0 8013bb4: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013bb6: 687b ldr r3, [r7, #4] 8013bb8: 681b ldr r3, [r3, #0] 8013bba: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013bbc: 6bbb ldr r3, [r7, #56] @ 0x38 8013bbe: e853 3f00 ldrex r3, [r3] 8013bc2: 637b str r3, [r7, #52] @ 0x34 return(result); 8013bc4: 6b7b ldr r3, [r7, #52] @ 0x34 8013bc6: f023 0310 bic.w r3, r3, #16 8013bca: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8013bce: 687b ldr r3, [r7, #4] 8013bd0: 681b ldr r3, [r3, #0] 8013bd2: 461a mov r2, r3 8013bd4: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8013bd8: 647b str r3, [r7, #68] @ 0x44 8013bda: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013bdc: 6c39 ldr r1, [r7, #64] @ 0x40 8013bde: 6c7a ldr r2, [r7, #68] @ 0x44 8013be0: e841 2300 strex r3, r2, [r1] 8013be4: 63fb str r3, [r7, #60] @ 0x3c return(result); 8013be6: 6bfb ldr r3, [r7, #60] @ 0x3c 8013be8: 2b00 cmp r3, #0 8013bea: d1e4 bne.n 8013bb6 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8013bec: 687b ldr r3, [r7, #4] 8013bee: 681b ldr r3, [r3, #0] 8013bf0: 69db ldr r3, [r3, #28] 8013bf2: f003 0310 and.w r3, r3, #16 8013bf6: 2b10 cmp r3, #16 8013bf8: d103 bne.n 8013c02 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8013bfa: 687b ldr r3, [r7, #4] 8013bfc: 681b ldr r3, [r3, #0] 8013bfe: 2210 movs r2, #16 8013c00: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8013c02: 687b ldr r3, [r7, #4] 8013c04: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8013c08: 4619 mov r1, r3 8013c0a: 6878 ldr r0, [r7, #4] 8013c0c: f7f0 ffae bl 8004b6c 8013c10: e002 b.n 8013c18 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8013c12: 6878 ldr r0, [r7, #4] 8013c14: f7f0 ffa0 bl 8004b58 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8013c18: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6 8013c1c: 2b00 cmp r3, #0 8013c1e: d006 beq.n 8013c2e 8013c20: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8013c24: f003 0320 and.w r3, r3, #32 8013c28: 2b00 cmp r3, #0 8013c2a: f47f aecd bne.w 80139c8 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 8013c2e: 687b ldr r3, [r7, #4] 8013c30: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013c34: f8a7 308e strh.w r3, [r7, #142] @ 0x8e if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 8013c38: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e 8013c3c: 2b00 cmp r3, #0 8013c3e: d049 beq.n 8013cd4 8013c40: 687b ldr r3, [r7, #4] 8013c42: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8013c46: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e 8013c4a: 429a cmp r2, r3 8013c4c: d242 bcs.n 8013cd4 { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8013c4e: 687b ldr r3, [r7, #4] 8013c50: 681b ldr r3, [r3, #0] 8013c52: 3308 adds r3, #8 8013c54: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013c56: 6a7b ldr r3, [r7, #36] @ 0x24 8013c58: e853 3f00 ldrex r3, [r3] 8013c5c: 623b str r3, [r7, #32] return(result); 8013c5e: 6a3b ldr r3, [r7, #32] 8013c60: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8013c64: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8013c68: 687b ldr r3, [r7, #4] 8013c6a: 681b ldr r3, [r3, #0] 8013c6c: 3308 adds r3, #8 8013c6e: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88 8013c72: 633a str r2, [r7, #48] @ 0x30 8013c74: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013c76: 6af9 ldr r1, [r7, #44] @ 0x2c 8013c78: 6b3a ldr r2, [r7, #48] @ 0x30 8013c7a: e841 2300 strex r3, r2, [r1] 8013c7e: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013c80: 6abb ldr r3, [r7, #40] @ 0x28 8013c82: 2b00 cmp r3, #0 8013c84: d1e3 bne.n 8013c4e /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; 8013c86: 687b ldr r3, [r7, #4] 8013c88: 4a16 ldr r2, [pc, #88] @ (8013ce4 ) 8013c8a: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8013c8c: 687b ldr r3, [r7, #4] 8013c8e: 681b ldr r3, [r3, #0] 8013c90: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013c92: 693b ldr r3, [r7, #16] 8013c94: e853 3f00 ldrex r3, [r3] 8013c98: 60fb str r3, [r7, #12] return(result); 8013c9a: 68fb ldr r3, [r7, #12] 8013c9c: f043 0320 orr.w r3, r3, #32 8013ca0: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8013ca4: 687b ldr r3, [r7, #4] 8013ca6: 681b ldr r3, [r3, #0] 8013ca8: 461a mov r2, r3 8013caa: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8013cae: 61fb str r3, [r7, #28] 8013cb0: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013cb2: 69b9 ldr r1, [r7, #24] 8013cb4: 69fa ldr r2, [r7, #28] 8013cb6: e841 2300 strex r3, r2, [r1] 8013cba: 617b str r3, [r7, #20] return(result); 8013cbc: 697b ldr r3, [r7, #20] 8013cbe: 2b00 cmp r3, #0 8013cc0: d1e4 bne.n 8013c8c else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8013cc2: e007 b.n 8013cd4 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8013cc4: 687b ldr r3, [r7, #4] 8013cc6: 681b ldr r3, [r3, #0] 8013cc8: 699a ldr r2, [r3, #24] 8013cca: 687b ldr r3, [r7, #4] 8013ccc: 681b ldr r3, [r3, #0] 8013cce: f042 0208 orr.w r2, r2, #8 8013cd2: 619a str r2, [r3, #24] } 8013cd4: bf00 nop 8013cd6: 37b8 adds r7, #184 @ 0xb8 8013cd8: 46bd mov sp, r7 8013cda: bd80 pop {r7, pc} 8013cdc: effffffe .word 0xeffffffe 8013ce0: 58000c00 .word 0x58000c00 8013ce4: 08013469 .word 0x08013469 08013ce8 : * @brief UART wakeup from Stop mode callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { 8013ce8: b480 push {r7} 8013cea: b083 sub sp, #12 8013cec: af00 add r7, sp, #0 8013cee: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } 8013cf0: bf00 nop 8013cf2: 370c adds r7, #12 8013cf4: 46bd mov sp, r7 8013cf6: f85d 7b04 ldr.w r7, [sp], #4 8013cfa: 4770 bx lr 08013cfc : * @brief UART RX Fifo full callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { 8013cfc: b480 push {r7} 8013cfe: b083 sub sp, #12 8013d00: af00 add r7, sp, #0 8013d02: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. */ } 8013d04: bf00 nop 8013d06: 370c adds r7, #12 8013d08: 46bd mov sp, r7 8013d0a: f85d 7b04 ldr.w r7, [sp], #4 8013d0e: 4770 bx lr 08013d10 : * @brief UART TX Fifo empty callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { 8013d10: b480 push {r7} 8013d12: b083 sub sp, #12 8013d14: af00 add r7, sp, #0 8013d16: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } 8013d18: bf00 nop 8013d1a: 370c adds r7, #12 8013d1c: 46bd mov sp, r7 8013d1e: f85d 7b04 ldr.w r7, [sp], #4 8013d22: 4770 bx lr 08013d24 : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 8013d24: b480 push {r7} 8013d26: b085 sub sp, #20 8013d28: af00 add r7, sp, #0 8013d2a: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 8013d2c: 687b ldr r3, [r7, #4] 8013d2e: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8013d32: 2b01 cmp r3, #1 8013d34: d101 bne.n 8013d3a 8013d36: 2302 movs r3, #2 8013d38: e027 b.n 8013d8a 8013d3a: 687b ldr r3, [r7, #4] 8013d3c: 2201 movs r2, #1 8013d3e: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8013d42: 687b ldr r3, [r7, #4] 8013d44: 2224 movs r2, #36 @ 0x24 8013d46: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8013d4a: 687b ldr r3, [r7, #4] 8013d4c: 681b ldr r3, [r3, #0] 8013d4e: 681b ldr r3, [r3, #0] 8013d50: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8013d52: 687b ldr r3, [r7, #4] 8013d54: 681b ldr r3, [r3, #0] 8013d56: 681a ldr r2, [r3, #0] 8013d58: 687b ldr r3, [r7, #4] 8013d5a: 681b ldr r3, [r3, #0] 8013d5c: f022 0201 bic.w r2, r2, #1 8013d60: 601a str r2, [r3, #0] /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 8013d62: 68fb ldr r3, [r7, #12] 8013d64: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000 8013d68: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 8013d6a: 687b ldr r3, [r7, #4] 8013d6c: 2200 movs r2, #0 8013d6e: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8013d70: 687b ldr r3, [r7, #4] 8013d72: 681b ldr r3, [r3, #0] 8013d74: 68fa ldr r2, [r7, #12] 8013d76: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8013d78: 687b ldr r3, [r7, #4] 8013d7a: 2220 movs r2, #32 8013d7c: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8013d80: 687b ldr r3, [r7, #4] 8013d82: 2200 movs r2, #0 8013d84: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8013d88: 2300 movs r3, #0 } 8013d8a: 4618 mov r0, r3 8013d8c: 3714 adds r7, #20 8013d8e: 46bd mov sp, r7 8013d90: f85d 7b04 ldr.w r7, [sp], #4 8013d94: 4770 bx lr 08013d96 : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8013d96: b580 push {r7, lr} 8013d98: b084 sub sp, #16 8013d9a: af00 add r7, sp, #0 8013d9c: 6078 str r0, [r7, #4] 8013d9e: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8013da0: 687b ldr r3, [r7, #4] 8013da2: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8013da6: 2b01 cmp r3, #1 8013da8: d101 bne.n 8013dae 8013daa: 2302 movs r3, #2 8013dac: e02d b.n 8013e0a 8013dae: 687b ldr r3, [r7, #4] 8013db0: 2201 movs r2, #1 8013db2: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8013db6: 687b ldr r3, [r7, #4] 8013db8: 2224 movs r2, #36 @ 0x24 8013dba: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8013dbe: 687b ldr r3, [r7, #4] 8013dc0: 681b ldr r3, [r3, #0] 8013dc2: 681b ldr r3, [r3, #0] 8013dc4: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8013dc6: 687b ldr r3, [r7, #4] 8013dc8: 681b ldr r3, [r3, #0] 8013dca: 681a ldr r2, [r3, #0] 8013dcc: 687b ldr r3, [r7, #4] 8013dce: 681b ldr r3, [r3, #0] 8013dd0: f022 0201 bic.w r2, r2, #1 8013dd4: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 8013dd6: 687b ldr r3, [r7, #4] 8013dd8: 681b ldr r3, [r3, #0] 8013dda: 689b ldr r3, [r3, #8] 8013ddc: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 8013de0: 687b ldr r3, [r7, #4] 8013de2: 681b ldr r3, [r3, #0] 8013de4: 683a ldr r2, [r7, #0] 8013de6: 430a orrs r2, r1 8013de8: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8013dea: 6878 ldr r0, [r7, #4] 8013dec: f000 f8a0 bl 8013f30 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8013df0: 687b ldr r3, [r7, #4] 8013df2: 681b ldr r3, [r3, #0] 8013df4: 68fa ldr r2, [r7, #12] 8013df6: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8013df8: 687b ldr r3, [r7, #4] 8013dfa: 2220 movs r2, #32 8013dfc: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8013e00: 687b ldr r3, [r7, #4] 8013e02: 2200 movs r2, #0 8013e04: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8013e08: 2300 movs r3, #0 } 8013e0a: 4618 mov r0, r3 8013e0c: 3710 adds r7, #16 8013e0e: 46bd mov sp, r7 8013e10: bd80 pop {r7, pc} 08013e12 : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8013e12: b580 push {r7, lr} 8013e14: b084 sub sp, #16 8013e16: af00 add r7, sp, #0 8013e18: 6078 str r0, [r7, #4] 8013e1a: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8013e1c: 687b ldr r3, [r7, #4] 8013e1e: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8013e22: 2b01 cmp r3, #1 8013e24: d101 bne.n 8013e2a 8013e26: 2302 movs r3, #2 8013e28: e02d b.n 8013e86 8013e2a: 687b ldr r3, [r7, #4] 8013e2c: 2201 movs r2, #1 8013e2e: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8013e32: 687b ldr r3, [r7, #4] 8013e34: 2224 movs r2, #36 @ 0x24 8013e36: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8013e3a: 687b ldr r3, [r7, #4] 8013e3c: 681b ldr r3, [r3, #0] 8013e3e: 681b ldr r3, [r3, #0] 8013e40: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8013e42: 687b ldr r3, [r7, #4] 8013e44: 681b ldr r3, [r3, #0] 8013e46: 681a ldr r2, [r3, #0] 8013e48: 687b ldr r3, [r7, #4] 8013e4a: 681b ldr r3, [r3, #0] 8013e4c: f022 0201 bic.w r2, r2, #1 8013e50: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 8013e52: 687b ldr r3, [r7, #4] 8013e54: 681b ldr r3, [r3, #0] 8013e56: 689b ldr r3, [r3, #8] 8013e58: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 8013e5c: 687b ldr r3, [r7, #4] 8013e5e: 681b ldr r3, [r3, #0] 8013e60: 683a ldr r2, [r7, #0] 8013e62: 430a orrs r2, r1 8013e64: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8013e66: 6878 ldr r0, [r7, #4] 8013e68: f000 f862 bl 8013f30 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8013e6c: 687b ldr r3, [r7, #4] 8013e6e: 681b ldr r3, [r3, #0] 8013e70: 68fa ldr r2, [r7, #12] 8013e72: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8013e74: 687b ldr r3, [r7, #4] 8013e76: 2220 movs r2, #32 8013e78: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8013e7c: 687b ldr r3, [r7, #4] 8013e7e: 2200 movs r2, #0 8013e80: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8013e84: 2300 movs r3, #0 } 8013e86: 4618 mov r0, r3 8013e88: 3710 adds r7, #16 8013e8a: 46bd mov sp, r7 8013e8c: bd80 pop {r7, pc} 08013e8e : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8013e8e: b580 push {r7, lr} 8013e90: b08c sub sp, #48 @ 0x30 8013e92: af00 add r7, sp, #0 8013e94: 60f8 str r0, [r7, #12] 8013e96: 60b9 str r1, [r7, #8] 8013e98: 4613 mov r3, r2 8013e9a: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status = HAL_OK; 8013e9c: 2300 movs r3, #0 8013e9e: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8013ea2: 68fb ldr r3, [r7, #12] 8013ea4: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8013ea8: 2b20 cmp r3, #32 8013eaa: d13b bne.n 8013f24 { if ((pData == NULL) || (Size == 0U)) 8013eac: 68bb ldr r3, [r7, #8] 8013eae: 2b00 cmp r3, #0 8013eb0: d002 beq.n 8013eb8 8013eb2: 88fb ldrh r3, [r7, #6] 8013eb4: 2b00 cmp r3, #0 8013eb6: d101 bne.n 8013ebc { return HAL_ERROR; 8013eb8: 2301 movs r3, #1 8013eba: e034 b.n 8013f26 } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8013ebc: 68fb ldr r3, [r7, #12] 8013ebe: 2201 movs r2, #1 8013ec0: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8013ec2: 68fb ldr r3, [r7, #12] 8013ec4: 2200 movs r2, #0 8013ec6: 671a str r2, [r3, #112] @ 0x70 (void)UART_Start_Receive_IT(huart, pData, Size); 8013ec8: 88fb ldrh r3, [r7, #6] 8013eca: 461a mov r2, r3 8013ecc: 68b9 ldr r1, [r7, #8] 8013ece: 68f8 ldr r0, [r7, #12] 8013ed0: f7fe fe82 bl 8012bd8 if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013ed4: 68fb ldr r3, [r7, #12] 8013ed6: 6edb ldr r3, [r3, #108] @ 0x6c 8013ed8: 2b01 cmp r3, #1 8013eda: d11d bne.n 8013f18 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8013edc: 68fb ldr r3, [r7, #12] 8013ede: 681b ldr r3, [r3, #0] 8013ee0: 2210 movs r2, #16 8013ee2: 621a str r2, [r3, #32] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013ee4: 68fb ldr r3, [r7, #12] 8013ee6: 681b ldr r3, [r3, #0] 8013ee8: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013eea: 69bb ldr r3, [r7, #24] 8013eec: e853 3f00 ldrex r3, [r3] 8013ef0: 617b str r3, [r7, #20] return(result); 8013ef2: 697b ldr r3, [r7, #20] 8013ef4: f043 0310 orr.w r3, r3, #16 8013ef8: 62bb str r3, [r7, #40] @ 0x28 8013efa: 68fb ldr r3, [r7, #12] 8013efc: 681b ldr r3, [r3, #0] 8013efe: 461a mov r2, r3 8013f00: 6abb ldr r3, [r7, #40] @ 0x28 8013f02: 627b str r3, [r7, #36] @ 0x24 8013f04: 623a str r2, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013f06: 6a39 ldr r1, [r7, #32] 8013f08: 6a7a ldr r2, [r7, #36] @ 0x24 8013f0a: e841 2300 strex r3, r2, [r1] 8013f0e: 61fb str r3, [r7, #28] return(result); 8013f10: 69fb ldr r3, [r7, #28] 8013f12: 2b00 cmp r3, #0 8013f14: d1e6 bne.n 8013ee4 8013f16: e002 b.n 8013f1e { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8013f18: 2301 movs r3, #1 8013f1a: f887 302f strb.w r3, [r7, #47] @ 0x2f } return status; 8013f1e: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8013f22: e000 b.n 8013f26 } else { return HAL_BUSY; 8013f24: 2302 movs r3, #2 } } 8013f26: 4618 mov r0, r3 8013f28: 3730 adds r7, #48 @ 0x30 8013f2a: 46bd mov sp, r7 8013f2c: bd80 pop {r7, pc} ... 08013f30 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 8013f30: b480 push {r7} 8013f32: b085 sub sp, #20 8013f34: af00 add r7, sp, #0 8013f36: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 8013f38: 687b ldr r3, [r7, #4] 8013f3a: 6e5b ldr r3, [r3, #100] @ 0x64 8013f3c: 2b00 cmp r3, #0 8013f3e: d108 bne.n 8013f52 { huart->NbTxDataToProcess = 1U; 8013f40: 687b ldr r3, [r7, #4] 8013f42: 2201 movs r2, #1 8013f44: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1U; 8013f48: 687b ldr r3, [r7, #4] 8013f4a: 2201 movs r2, #1 8013f4c: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 8013f50: e031 b.n 8013fb6 rx_fifo_depth = RX_FIFO_DEPTH; 8013f52: 2310 movs r3, #16 8013f54: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 8013f56: 2310 movs r3, #16 8013f58: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 8013f5a: 687b ldr r3, [r7, #4] 8013f5c: 681b ldr r3, [r3, #0] 8013f5e: 689b ldr r3, [r3, #8] 8013f60: 0e5b lsrs r3, r3, #25 8013f62: b2db uxtb r3, r3 8013f64: f003 0307 and.w r3, r3, #7 8013f68: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 8013f6a: 687b ldr r3, [r7, #4] 8013f6c: 681b ldr r3, [r3, #0] 8013f6e: 689b ldr r3, [r3, #8] 8013f70: 0f5b lsrs r3, r3, #29 8013f72: b2db uxtb r3, r3 8013f74: f003 0307 and.w r3, r3, #7 8013f78: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8013f7a: 7bbb ldrb r3, [r7, #14] 8013f7c: 7b3a ldrb r2, [r7, #12] 8013f7e: 4911 ldr r1, [pc, #68] @ (8013fc4 ) 8013f80: 5c8a ldrb r2, [r1, r2] 8013f82: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 8013f86: 7b3a ldrb r2, [r7, #12] 8013f88: 490f ldr r1, [pc, #60] @ (8013fc8 ) 8013f8a: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8013f8c: fb93 f3f2 sdiv r3, r3, r2 8013f90: b29a uxth r2, r3 8013f92: 687b ldr r3, [r7, #4] 8013f94: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8013f98: 7bfb ldrb r3, [r7, #15] 8013f9a: 7b7a ldrb r2, [r7, #13] 8013f9c: 4909 ldr r1, [pc, #36] @ (8013fc4 ) 8013f9e: 5c8a ldrb r2, [r1, r2] 8013fa0: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 8013fa4: 7b7a ldrb r2, [r7, #13] 8013fa6: 4908 ldr r1, [pc, #32] @ (8013fc8 ) 8013fa8: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8013faa: fb93 f3f2 sdiv r3, r3, r2 8013fae: b29a uxth r2, r3 8013fb0: 687b ldr r3, [r7, #4] 8013fb2: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 } 8013fb6: bf00 nop 8013fb8: 3714 adds r7, #20 8013fba: 46bd mov sp, r7 8013fbc: f85d 7b04 ldr.w r7, [sp], #4 8013fc0: 4770 bx lr 8013fc2: bf00 nop 8013fc4: 080187bc .word 0x080187bc 8013fc8: 080187c4 .word 0x080187c4 08013fcc <__NVIC_SetPriority>: { 8013fcc: b480 push {r7} 8013fce: b083 sub sp, #12 8013fd0: af00 add r7, sp, #0 8013fd2: 4603 mov r3, r0 8013fd4: 6039 str r1, [r7, #0] 8013fd6: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8013fd8: f9b7 3006 ldrsh.w r3, [r7, #6] 8013fdc: 2b00 cmp r3, #0 8013fde: db0a blt.n 8013ff6 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8013fe0: 683b ldr r3, [r7, #0] 8013fe2: b2da uxtb r2, r3 8013fe4: 490c ldr r1, [pc, #48] @ (8014018 <__NVIC_SetPriority+0x4c>) 8013fe6: f9b7 3006 ldrsh.w r3, [r7, #6] 8013fea: 0112 lsls r2, r2, #4 8013fec: b2d2 uxtb r2, r2 8013fee: 440b add r3, r1 8013ff0: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 8013ff4: e00a b.n 801400c <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8013ff6: 683b ldr r3, [r7, #0] 8013ff8: b2da uxtb r2, r3 8013ffa: 4908 ldr r1, [pc, #32] @ (801401c <__NVIC_SetPriority+0x50>) 8013ffc: 88fb ldrh r3, [r7, #6] 8013ffe: f003 030f and.w r3, r3, #15 8014002: 3b04 subs r3, #4 8014004: 0112 lsls r2, r2, #4 8014006: b2d2 uxtb r2, r2 8014008: 440b add r3, r1 801400a: 761a strb r2, [r3, #24] } 801400c: bf00 nop 801400e: 370c adds r7, #12 8014010: 46bd mov sp, r7 8014012: f85d 7b04 ldr.w r7, [sp], #4 8014016: 4770 bx lr 8014018: e000e100 .word 0xe000e100 801401c: e000ed00 .word 0xe000ed00 08014020 : /* SysTick handler implementation that also clears overflow flag. */ #if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) void SysTick_Handler (void) { 8014020: b580 push {r7, lr} 8014022: af00 add r7, sp, #0 /* Clear overflow flag */ SysTick->CTRL; 8014024: 4b05 ldr r3, [pc, #20] @ (801403c ) 8014026: 681b ldr r3, [r3, #0] if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { 8014028: f002 fd1e bl 8016a68 801402c: 4603 mov r3, r0 801402e: 2b01 cmp r3, #1 8014030: d001 beq.n 8014036 /* Call tick handler */ xPortSysTickHandler(); 8014032: f003 ff31 bl 8017e98 } } 8014036: bf00 nop 8014038: bd80 pop {r7, pc} 801403a: bf00 nop 801403c: e000e010 .word 0xe000e010 08014040 : #endif /* SysTick */ /* Setup SVC to reset value. */ __STATIC_INLINE void SVC_Setup (void) { 8014040: b580 push {r7, lr} 8014042: af00 add r7, sp, #0 #if (__ARM_ARCH_7A__ == 0U) /* Service Call interrupt might be configured before kernel start */ /* and when its priority is lower or equal to BASEPRI, svc intruction */ /* causes a Hard Fault. */ NVIC_SetPriority (SVCall_IRQ_NBR, 0U); 8014044: 2100 movs r1, #0 8014046: f06f 0004 mvn.w r0, #4 801404a: f7ff ffbf bl 8013fcc <__NVIC_SetPriority> #endif } 801404e: bf00 nop 8014050: bd80 pop {r7, pc} ... 08014054 : static uint32_t OS_Tick_GetOverflow (void); /* Get OS Tick interval */ static uint32_t OS_Tick_GetInterval (void); /*---------------------------------------------------------------------------*/ osStatus_t osKernelInitialize (void) { 8014054: b480 push {r7} 8014056: b083 sub sp, #12 8014058: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801405a: f3ef 8305 mrs r3, IPSR 801405e: 603b str r3, [r7, #0] return(result); 8014060: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 8014062: 2b00 cmp r3, #0 8014064: d003 beq.n 801406e stat = osErrorISR; 8014066: f06f 0305 mvn.w r3, #5 801406a: 607b str r3, [r7, #4] 801406c: e00c b.n 8014088 } else { if (KernelState == osKernelInactive) { 801406e: 4b0a ldr r3, [pc, #40] @ (8014098 ) 8014070: 681b ldr r3, [r3, #0] 8014072: 2b00 cmp r3, #0 8014074: d105 bne.n 8014082 EvrFreeRTOSSetup(0U); #endif #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) vPortDefineHeapRegions (configHEAP_5_REGIONS); #endif KernelState = osKernelReady; 8014076: 4b08 ldr r3, [pc, #32] @ (8014098 ) 8014078: 2201 movs r2, #1 801407a: 601a str r2, [r3, #0] stat = osOK; 801407c: 2300 movs r3, #0 801407e: 607b str r3, [r7, #4] 8014080: e002 b.n 8014088 } else { stat = osError; 8014082: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8014086: 607b str r3, [r7, #4] } } return (stat); 8014088: 687b ldr r3, [r7, #4] } 801408a: 4618 mov r0, r3 801408c: 370c adds r7, #12 801408e: 46bd mov sp, r7 8014090: f85d 7b04 ldr.w r7, [sp], #4 8014094: 4770 bx lr 8014096: bf00 nop 8014098: 24001064 .word 0x24001064 0801409c : } return (state); } osStatus_t osKernelStart (void) { 801409c: b580 push {r7, lr} 801409e: b082 sub sp, #8 80140a0: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80140a2: f3ef 8305 mrs r3, IPSR 80140a6: 603b str r3, [r7, #0] return(result); 80140a8: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 80140aa: 2b00 cmp r3, #0 80140ac: d003 beq.n 80140b6 stat = osErrorISR; 80140ae: f06f 0305 mvn.w r3, #5 80140b2: 607b str r3, [r7, #4] 80140b4: e010 b.n 80140d8 } else { if (KernelState == osKernelReady) { 80140b6: 4b0b ldr r3, [pc, #44] @ (80140e4 ) 80140b8: 681b ldr r3, [r3, #0] 80140ba: 2b01 cmp r3, #1 80140bc: d109 bne.n 80140d2 /* Ensure SVC priority is at the reset value */ SVC_Setup(); 80140be: f7ff ffbf bl 8014040 /* Change state to enable IRQ masking check */ KernelState = osKernelRunning; 80140c2: 4b08 ldr r3, [pc, #32] @ (80140e4 ) 80140c4: 2202 movs r2, #2 80140c6: 601a str r2, [r3, #0] /* Start the kernel scheduler */ vTaskStartScheduler(); 80140c8: f002 f824 bl 8016114 stat = osOK; 80140cc: 2300 movs r3, #0 80140ce: 607b str r3, [r7, #4] 80140d0: e002 b.n 80140d8 } else { stat = osError; 80140d2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80140d6: 607b str r3, [r7, #4] } } return (stat); 80140d8: 687b ldr r3, [r7, #4] } 80140da: 4618 mov r0, r3 80140dc: 3708 adds r7, #8 80140de: 46bd mov sp, r7 80140e0: bd80 pop {r7, pc} 80140e2: bf00 nop 80140e4: 24001064 .word 0x24001064 080140e8 : return (configCPU_CLOCK_HZ); } /*---------------------------------------------------------------------------*/ osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { 80140e8: b580 push {r7, lr} 80140ea: b08e sub sp, #56 @ 0x38 80140ec: af04 add r7, sp, #16 80140ee: 60f8 str r0, [r7, #12] 80140f0: 60b9 str r1, [r7, #8] 80140f2: 607a str r2, [r7, #4] uint32_t stack; TaskHandle_t hTask; UBaseType_t prio; int32_t mem; hTask = NULL; 80140f4: 2300 movs r3, #0 80140f6: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80140f8: f3ef 8305 mrs r3, IPSR 80140fc: 617b str r3, [r7, #20] return(result); 80140fe: 697b ldr r3, [r7, #20] if (!IS_IRQ() && (func != NULL)) { 8014100: 2b00 cmp r3, #0 8014102: d17f bne.n 8014204 8014104: 68fb ldr r3, [r7, #12] 8014106: 2b00 cmp r3, #0 8014108: d07c beq.n 8014204 stack = configMINIMAL_STACK_SIZE; 801410a: f44f 7300 mov.w r3, #512 @ 0x200 801410e: 623b str r3, [r7, #32] prio = (UBaseType_t)osPriorityNormal; 8014110: 2318 movs r3, #24 8014112: 61fb str r3, [r7, #28] name = NULL; 8014114: 2300 movs r3, #0 8014116: 627b str r3, [r7, #36] @ 0x24 mem = -1; 8014118: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801411c: 61bb str r3, [r7, #24] if (attr != NULL) { 801411e: 687b ldr r3, [r7, #4] 8014120: 2b00 cmp r3, #0 8014122: d045 beq.n 80141b0 if (attr->name != NULL) { 8014124: 687b ldr r3, [r7, #4] 8014126: 681b ldr r3, [r3, #0] 8014128: 2b00 cmp r3, #0 801412a: d002 beq.n 8014132 name = attr->name; 801412c: 687b ldr r3, [r7, #4] 801412e: 681b ldr r3, [r3, #0] 8014130: 627b str r3, [r7, #36] @ 0x24 } if (attr->priority != osPriorityNone) { 8014132: 687b ldr r3, [r7, #4] 8014134: 699b ldr r3, [r3, #24] 8014136: 2b00 cmp r3, #0 8014138: d002 beq.n 8014140 prio = (UBaseType_t)attr->priority; 801413a: 687b ldr r3, [r7, #4] 801413c: 699b ldr r3, [r3, #24] 801413e: 61fb str r3, [r7, #28] } if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { 8014140: 69fb ldr r3, [r7, #28] 8014142: 2b00 cmp r3, #0 8014144: d008 beq.n 8014158 8014146: 69fb ldr r3, [r7, #28] 8014148: 2b38 cmp r3, #56 @ 0x38 801414a: d805 bhi.n 8014158 801414c: 687b ldr r3, [r7, #4] 801414e: 685b ldr r3, [r3, #4] 8014150: f003 0301 and.w r3, r3, #1 8014154: 2b00 cmp r3, #0 8014156: d001 beq.n 801415c return (NULL); 8014158: 2300 movs r3, #0 801415a: e054 b.n 8014206 } if (attr->stack_size > 0U) { 801415c: 687b ldr r3, [r7, #4] 801415e: 695b ldr r3, [r3, #20] 8014160: 2b00 cmp r3, #0 8014162: d003 beq.n 801416c /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ stack = attr->stack_size / sizeof(StackType_t); 8014164: 687b ldr r3, [r7, #4] 8014166: 695b ldr r3, [r3, #20] 8014168: 089b lsrs r3, r3, #2 801416a: 623b str r3, [r7, #32] } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 801416c: 687b ldr r3, [r7, #4] 801416e: 689b ldr r3, [r3, #8] 8014170: 2b00 cmp r3, #0 8014172: d00e beq.n 8014192 8014174: 687b ldr r3, [r7, #4] 8014176: 68db ldr r3, [r3, #12] 8014178: 2ba7 cmp r3, #167 @ 0xa7 801417a: d90a bls.n 8014192 (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 801417c: 687b ldr r3, [r7, #4] 801417e: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 8014180: 2b00 cmp r3, #0 8014182: d006 beq.n 8014192 (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 8014184: 687b ldr r3, [r7, #4] 8014186: 695b ldr r3, [r3, #20] 8014188: 2b00 cmp r3, #0 801418a: d002 beq.n 8014192 mem = 1; 801418c: 2301 movs r3, #1 801418e: 61bb str r3, [r7, #24] 8014190: e010 b.n 80141b4 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { 8014192: 687b ldr r3, [r7, #4] 8014194: 689b ldr r3, [r3, #8] 8014196: 2b00 cmp r3, #0 8014198: d10c bne.n 80141b4 801419a: 687b ldr r3, [r7, #4] 801419c: 68db ldr r3, [r3, #12] 801419e: 2b00 cmp r3, #0 80141a0: d108 bne.n 80141b4 80141a2: 687b ldr r3, [r7, #4] 80141a4: 691b ldr r3, [r3, #16] 80141a6: 2b00 cmp r3, #0 80141a8: d104 bne.n 80141b4 mem = 0; 80141aa: 2300 movs r3, #0 80141ac: 61bb str r3, [r7, #24] 80141ae: e001 b.n 80141b4 } } } else { mem = 0; 80141b0: 2300 movs r3, #0 80141b2: 61bb str r3, [r7, #24] } if (mem == 1) { 80141b4: 69bb ldr r3, [r7, #24] 80141b6: 2b01 cmp r3, #1 80141b8: d110 bne.n 80141dc #if (configSUPPORT_STATIC_ALLOCATION == 1) hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 80141ba: 687b ldr r3, [r7, #4] 80141bc: 691b ldr r3, [r3, #16] (StaticTask_t *)attr->cb_mem); 80141be: 687a ldr r2, [r7, #4] 80141c0: 6892 ldr r2, [r2, #8] hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 80141c2: 9202 str r2, [sp, #8] 80141c4: 9301 str r3, [sp, #4] 80141c6: 69fb ldr r3, [r7, #28] 80141c8: 9300 str r3, [sp, #0] 80141ca: 68bb ldr r3, [r7, #8] 80141cc: 6a3a ldr r2, [r7, #32] 80141ce: 6a79 ldr r1, [r7, #36] @ 0x24 80141d0: 68f8 ldr r0, [r7, #12] 80141d2: f001 fdac bl 8015d2e 80141d6: 4603 mov r3, r0 80141d8: 613b str r3, [r7, #16] 80141da: e013 b.n 8014204 #endif } else { if (mem == 0) { 80141dc: 69bb ldr r3, [r7, #24] 80141de: 2b00 cmp r3, #0 80141e0: d110 bne.n 8014204 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { 80141e2: 6a3b ldr r3, [r7, #32] 80141e4: b29a uxth r2, r3 80141e6: f107 0310 add.w r3, r7, #16 80141ea: 9301 str r3, [sp, #4] 80141ec: 69fb ldr r3, [r7, #28] 80141ee: 9300 str r3, [sp, #0] 80141f0: 68bb ldr r3, [r7, #8] 80141f2: 6a79 ldr r1, [r7, #36] @ 0x24 80141f4: 68f8 ldr r0, [r7, #12] 80141f6: f001 fdfa bl 8015dee 80141fa: 4603 mov r3, r0 80141fc: 2b01 cmp r3, #1 80141fe: d001 beq.n 8014204 hTask = NULL; 8014200: 2300 movs r3, #0 8014202: 613b str r3, [r7, #16] #endif } } } return ((osThreadId_t)hTask); 8014204: 693b ldr r3, [r7, #16] } 8014206: 4618 mov r0, r3 8014208: 3728 adds r7, #40 @ 0x28 801420a: 46bd mov sp, r7 801420c: bd80 pop {r7, pc} 0801420e : /* Return flags before clearing */ return (rflags); } #endif /* (configUSE_OS2_THREAD_FLAGS == 1) */ osStatus_t osDelay (uint32_t ticks) { 801420e: b580 push {r7, lr} 8014210: b084 sub sp, #16 8014212: af00 add r7, sp, #0 8014214: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014216: f3ef 8305 mrs r3, IPSR 801421a: 60bb str r3, [r7, #8] return(result); 801421c: 68bb ldr r3, [r7, #8] osStatus_t stat; if (IS_IRQ()) { 801421e: 2b00 cmp r3, #0 8014220: d003 beq.n 801422a stat = osErrorISR; 8014222: f06f 0305 mvn.w r3, #5 8014226: 60fb str r3, [r7, #12] 8014228: e007 b.n 801423a } else { stat = osOK; 801422a: 2300 movs r3, #0 801422c: 60fb str r3, [r7, #12] if (ticks != 0U) { 801422e: 687b ldr r3, [r7, #4] 8014230: 2b00 cmp r3, #0 8014232: d002 beq.n 801423a vTaskDelay(ticks); 8014234: 6878 ldr r0, [r7, #4] 8014236: f001 ff37 bl 80160a8 } } return (stat); 801423a: 68fb ldr r3, [r7, #12] } 801423c: 4618 mov r0, r3 801423e: 3710 adds r7, #16 8014240: 46bd mov sp, r7 8014242: bd80 pop {r7, pc} 08014244 : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_TIMER == 1) static void TimerCallback (TimerHandle_t hTimer) { 8014244: b580 push {r7, lr} 8014246: b084 sub sp, #16 8014248: af00 add r7, sp, #0 801424a: 6078 str r0, [r7, #4] TimerCallback_t *callb; callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); 801424c: 6878 ldr r0, [r7, #4] 801424e: f003 fc3d bl 8017acc 8014252: 60f8 str r0, [r7, #12] if (callb != NULL) { 8014254: 68fb ldr r3, [r7, #12] 8014256: 2b00 cmp r3, #0 8014258: d005 beq.n 8014266 callb->func (callb->arg); 801425a: 68fb ldr r3, [r7, #12] 801425c: 681b ldr r3, [r3, #0] 801425e: 68fa ldr r2, [r7, #12] 8014260: 6852 ldr r2, [r2, #4] 8014262: 4610 mov r0, r2 8014264: 4798 blx r3 } } 8014266: bf00 nop 8014268: 3710 adds r7, #16 801426a: 46bd mov sp, r7 801426c: bd80 pop {r7, pc} ... 08014270 : osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { 8014270: b580 push {r7, lr} 8014272: b08c sub sp, #48 @ 0x30 8014274: af02 add r7, sp, #8 8014276: 60f8 str r0, [r7, #12] 8014278: 607a str r2, [r7, #4] 801427a: 603b str r3, [r7, #0] 801427c: 460b mov r3, r1 801427e: 72fb strb r3, [r7, #11] TimerHandle_t hTimer; TimerCallback_t *callb; UBaseType_t reload; int32_t mem; hTimer = NULL; 8014280: 2300 movs r3, #0 8014282: 623b str r3, [r7, #32] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014284: f3ef 8305 mrs r3, IPSR 8014288: 613b str r3, [r7, #16] return(result); 801428a: 693b ldr r3, [r7, #16] if (!IS_IRQ() && (func != NULL)) { 801428c: 2b00 cmp r3, #0 801428e: d163 bne.n 8014358 8014290: 68fb ldr r3, [r7, #12] 8014292: 2b00 cmp r3, #0 8014294: d060 beq.n 8014358 /* Allocate memory to store callback function and argument */ callb = pvPortMalloc (sizeof(TimerCallback_t)); 8014296: 2008 movs r0, #8 8014298: f003 fe90 bl 8017fbc 801429c: 6178 str r0, [r7, #20] if (callb != NULL) { 801429e: 697b ldr r3, [r7, #20] 80142a0: 2b00 cmp r3, #0 80142a2: d059 beq.n 8014358 callb->func = func; 80142a4: 697b ldr r3, [r7, #20] 80142a6: 68fa ldr r2, [r7, #12] 80142a8: 601a str r2, [r3, #0] callb->arg = argument; 80142aa: 697b ldr r3, [r7, #20] 80142ac: 687a ldr r2, [r7, #4] 80142ae: 605a str r2, [r3, #4] if (type == osTimerOnce) { 80142b0: 7afb ldrb r3, [r7, #11] 80142b2: 2b00 cmp r3, #0 80142b4: d102 bne.n 80142bc reload = pdFALSE; 80142b6: 2300 movs r3, #0 80142b8: 61fb str r3, [r7, #28] 80142ba: e001 b.n 80142c0 } else { reload = pdTRUE; 80142bc: 2301 movs r3, #1 80142be: 61fb str r3, [r7, #28] } mem = -1; 80142c0: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80142c4: 61bb str r3, [r7, #24] name = NULL; 80142c6: 2300 movs r3, #0 80142c8: 627b str r3, [r7, #36] @ 0x24 if (attr != NULL) { 80142ca: 683b ldr r3, [r7, #0] 80142cc: 2b00 cmp r3, #0 80142ce: d01c beq.n 801430a if (attr->name != NULL) { 80142d0: 683b ldr r3, [r7, #0] 80142d2: 681b ldr r3, [r3, #0] 80142d4: 2b00 cmp r3, #0 80142d6: d002 beq.n 80142de name = attr->name; 80142d8: 683b ldr r3, [r7, #0] 80142da: 681b ldr r3, [r3, #0] 80142dc: 627b str r3, [r7, #36] @ 0x24 } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) { 80142de: 683b ldr r3, [r7, #0] 80142e0: 689b ldr r3, [r3, #8] 80142e2: 2b00 cmp r3, #0 80142e4: d006 beq.n 80142f4 80142e6: 683b ldr r3, [r7, #0] 80142e8: 68db ldr r3, [r3, #12] 80142ea: 2b2b cmp r3, #43 @ 0x2b 80142ec: d902 bls.n 80142f4 mem = 1; 80142ee: 2301 movs r3, #1 80142f0: 61bb str r3, [r7, #24] 80142f2: e00c b.n 801430e } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 80142f4: 683b ldr r3, [r7, #0] 80142f6: 689b ldr r3, [r3, #8] 80142f8: 2b00 cmp r3, #0 80142fa: d108 bne.n 801430e 80142fc: 683b ldr r3, [r7, #0] 80142fe: 68db ldr r3, [r3, #12] 8014300: 2b00 cmp r3, #0 8014302: d104 bne.n 801430e mem = 0; 8014304: 2300 movs r3, #0 8014306: 61bb str r3, [r7, #24] 8014308: e001 b.n 801430e } } } else { mem = 0; 801430a: 2300 movs r3, #0 801430c: 61bb str r3, [r7, #24] } if (mem == 1) { 801430e: 69bb ldr r3, [r7, #24] 8014310: 2b01 cmp r3, #1 8014312: d10c bne.n 801432e #if (configSUPPORT_STATIC_ALLOCATION == 1) hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem); 8014314: 683b ldr r3, [r7, #0] 8014316: 689b ldr r3, [r3, #8] 8014318: 9301 str r3, [sp, #4] 801431a: 4b12 ldr r3, [pc, #72] @ (8014364 ) 801431c: 9300 str r3, [sp, #0] 801431e: 697b ldr r3, [r7, #20] 8014320: 69fa ldr r2, [r7, #28] 8014322: 2101 movs r1, #1 8014324: 6a78 ldr r0, [r7, #36] @ 0x24 8014326: f003 f81a bl 801735e 801432a: 6238 str r0, [r7, #32] 801432c: e00b b.n 8014346 #endif } else { if (mem == 0) { 801432e: 69bb ldr r3, [r7, #24] 8014330: 2b00 cmp r3, #0 8014332: d108 bne.n 8014346 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback); 8014334: 4b0b ldr r3, [pc, #44] @ (8014364 ) 8014336: 9300 str r3, [sp, #0] 8014338: 697b ldr r3, [r7, #20] 801433a: 69fa ldr r2, [r7, #28] 801433c: 2101 movs r1, #1 801433e: 6a78 ldr r0, [r7, #36] @ 0x24 8014340: f002 ffec bl 801731c 8014344: 6238 str r0, [r7, #32] #endif } } if ((hTimer == NULL) && (callb != NULL)) { 8014346: 6a3b ldr r3, [r7, #32] 8014348: 2b00 cmp r3, #0 801434a: d105 bne.n 8014358 801434c: 697b ldr r3, [r7, #20] 801434e: 2b00 cmp r3, #0 8014350: d002 beq.n 8014358 vPortFree (callb); 8014352: 6978 ldr r0, [r7, #20] 8014354: f003 ff00 bl 8018158 } } } return ((osTimerId_t)hTimer); 8014358: 6a3b ldr r3, [r7, #32] } 801435a: 4618 mov r0, r3 801435c: 3728 adds r7, #40 @ 0x28 801435e: 46bd mov sp, r7 8014360: bd80 pop {r7, pc} 8014362: bf00 nop 8014364: 08014245 .word 0x08014245 08014368 : } return (p); } osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) { 8014368: b580 push {r7, lr} 801436a: b088 sub sp, #32 801436c: af02 add r7, sp, #8 801436e: 6078 str r0, [r7, #4] 8014370: 6039 str r1, [r7, #0] TimerHandle_t hTimer = (TimerHandle_t)timer_id; 8014372: 687b ldr r3, [r7, #4] 8014374: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014376: f3ef 8305 mrs r3, IPSR 801437a: 60fb str r3, [r7, #12] return(result); 801437c: 68fb ldr r3, [r7, #12] osStatus_t stat; if (IS_IRQ()) { 801437e: 2b00 cmp r3, #0 8014380: d003 beq.n 801438a stat = osErrorISR; 8014382: f06f 0305 mvn.w r3, #5 8014386: 617b str r3, [r7, #20] 8014388: e017 b.n 80143ba } else if (hTimer == NULL) { 801438a: 693b ldr r3, [r7, #16] 801438c: 2b00 cmp r3, #0 801438e: d103 bne.n 8014398 stat = osErrorParameter; 8014390: f06f 0303 mvn.w r3, #3 8014394: 617b str r3, [r7, #20] 8014396: e010 b.n 80143ba } else { if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) { 8014398: 2300 movs r3, #0 801439a: 9300 str r3, [sp, #0] 801439c: 2300 movs r3, #0 801439e: 683a ldr r2, [r7, #0] 80143a0: 2104 movs r1, #4 80143a2: 6938 ldr r0, [r7, #16] 80143a4: f003 f858 bl 8017458 80143a8: 4603 mov r3, r0 80143aa: 2b01 cmp r3, #1 80143ac: d102 bne.n 80143b4 stat = osOK; 80143ae: 2300 movs r3, #0 80143b0: 617b str r3, [r7, #20] 80143b2: e002 b.n 80143ba } else { stat = osErrorResource; 80143b4: f06f 0302 mvn.w r3, #2 80143b8: 617b str r3, [r7, #20] } } return (stat); 80143ba: 697b ldr r3, [r7, #20] } 80143bc: 4618 mov r0, r3 80143be: 3718 adds r7, #24 80143c0: 46bd mov sp, r7 80143c2: bd80 pop {r7, pc} 080143c4 : osStatus_t osTimerStop (osTimerId_t timer_id) { 80143c4: b580 push {r7, lr} 80143c6: b088 sub sp, #32 80143c8: af02 add r7, sp, #8 80143ca: 6078 str r0, [r7, #4] TimerHandle_t hTimer = (TimerHandle_t)timer_id; 80143cc: 687b ldr r3, [r7, #4] 80143ce: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80143d0: f3ef 8305 mrs r3, IPSR 80143d4: 60fb str r3, [r7, #12] return(result); 80143d6: 68fb ldr r3, [r7, #12] osStatus_t stat; if (IS_IRQ()) { 80143d8: 2b00 cmp r3, #0 80143da: d003 beq.n 80143e4 stat = osErrorISR; 80143dc: f06f 0305 mvn.w r3, #5 80143e0: 617b str r3, [r7, #20] 80143e2: e021 b.n 8014428 } else if (hTimer == NULL) { 80143e4: 693b ldr r3, [r7, #16] 80143e6: 2b00 cmp r3, #0 80143e8: d103 bne.n 80143f2 stat = osErrorParameter; 80143ea: f06f 0303 mvn.w r3, #3 80143ee: 617b str r3, [r7, #20] 80143f0: e01a b.n 8014428 } else { if (xTimerIsTimerActive (hTimer) == pdFALSE) { 80143f2: 6938 ldr r0, [r7, #16] 80143f4: f003 fb40 bl 8017a78 80143f8: 4603 mov r3, r0 80143fa: 2b00 cmp r3, #0 80143fc: d103 bne.n 8014406 stat = osErrorResource; 80143fe: f06f 0302 mvn.w r3, #2 8014402: 617b str r3, [r7, #20] 8014404: e010 b.n 8014428 } else { if (xTimerStop (hTimer, 0) == pdPASS) { 8014406: 2300 movs r3, #0 8014408: 9300 str r3, [sp, #0] 801440a: 2300 movs r3, #0 801440c: 2200 movs r2, #0 801440e: 2103 movs r1, #3 8014410: 6938 ldr r0, [r7, #16] 8014412: f003 f821 bl 8017458 8014416: 4603 mov r3, r0 8014418: 2b01 cmp r3, #1 801441a: d102 bne.n 8014422 stat = osOK; 801441c: 2300 movs r3, #0 801441e: 617b str r3, [r7, #20] 8014420: e002 b.n 8014428 } else { stat = osError; 8014422: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8014426: 617b str r3, [r7, #20] } } } return (stat); 8014428: 697b ldr r3, [r7, #20] } 801442a: 4618 mov r0, r3 801442c: 3718 adds r7, #24 801442e: 46bd mov sp, r7 8014430: bd80 pop {r7, pc} 08014432 : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_MUTEX == 1) osMutexId_t osMutexNew (const osMutexAttr_t *attr) { 8014432: b580 push {r7, lr} 8014434: b088 sub sp, #32 8014436: af00 add r7, sp, #0 8014438: 6078 str r0, [r7, #4] int32_t mem; #if (configQUEUE_REGISTRY_SIZE > 0) const char *name; #endif hMutex = NULL; 801443a: 2300 movs r3, #0 801443c: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801443e: f3ef 8305 mrs r3, IPSR 8014442: 60bb str r3, [r7, #8] return(result); 8014444: 68bb ldr r3, [r7, #8] if (!IS_IRQ()) { 8014446: 2b00 cmp r3, #0 8014448: d174 bne.n 8014534 if (attr != NULL) { 801444a: 687b ldr r3, [r7, #4] 801444c: 2b00 cmp r3, #0 801444e: d003 beq.n 8014458 type = attr->attr_bits; 8014450: 687b ldr r3, [r7, #4] 8014452: 685b ldr r3, [r3, #4] 8014454: 61bb str r3, [r7, #24] 8014456: e001 b.n 801445c } else { type = 0U; 8014458: 2300 movs r3, #0 801445a: 61bb str r3, [r7, #24] } if ((type & osMutexRecursive) == osMutexRecursive) { 801445c: 69bb ldr r3, [r7, #24] 801445e: f003 0301 and.w r3, r3, #1 8014462: 2b00 cmp r3, #0 8014464: d002 beq.n 801446c rmtx = 1U; 8014466: 2301 movs r3, #1 8014468: 617b str r3, [r7, #20] 801446a: e001 b.n 8014470 } else { rmtx = 0U; 801446c: 2300 movs r3, #0 801446e: 617b str r3, [r7, #20] } if ((type & osMutexRobust) != osMutexRobust) { 8014470: 69bb ldr r3, [r7, #24] 8014472: f003 0308 and.w r3, r3, #8 8014476: 2b00 cmp r3, #0 8014478: d15c bne.n 8014534 mem = -1; 801447a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801447e: 613b str r3, [r7, #16] if (attr != NULL) { 8014480: 687b ldr r3, [r7, #4] 8014482: 2b00 cmp r3, #0 8014484: d015 beq.n 80144b2 if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { 8014486: 687b ldr r3, [r7, #4] 8014488: 689b ldr r3, [r3, #8] 801448a: 2b00 cmp r3, #0 801448c: d006 beq.n 801449c 801448e: 687b ldr r3, [r7, #4] 8014490: 68db ldr r3, [r3, #12] 8014492: 2b4f cmp r3, #79 @ 0x4f 8014494: d902 bls.n 801449c mem = 1; 8014496: 2301 movs r3, #1 8014498: 613b str r3, [r7, #16] 801449a: e00c b.n 80144b6 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 801449c: 687b ldr r3, [r7, #4] 801449e: 689b ldr r3, [r3, #8] 80144a0: 2b00 cmp r3, #0 80144a2: d108 bne.n 80144b6 80144a4: 687b ldr r3, [r7, #4] 80144a6: 68db ldr r3, [r3, #12] 80144a8: 2b00 cmp r3, #0 80144aa: d104 bne.n 80144b6 mem = 0; 80144ac: 2300 movs r3, #0 80144ae: 613b str r3, [r7, #16] 80144b0: e001 b.n 80144b6 } } } else { mem = 0; 80144b2: 2300 movs r3, #0 80144b4: 613b str r3, [r7, #16] } if (mem == 1) { 80144b6: 693b ldr r3, [r7, #16] 80144b8: 2b01 cmp r3, #1 80144ba: d112 bne.n 80144e2 #if (configSUPPORT_STATIC_ALLOCATION == 1) if (rmtx != 0U) { 80144bc: 697b ldr r3, [r7, #20] 80144be: 2b00 cmp r3, #0 80144c0: d007 beq.n 80144d2 #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem); 80144c2: 687b ldr r3, [r7, #4] 80144c4: 689b ldr r3, [r3, #8] 80144c6: 4619 mov r1, r3 80144c8: 2004 movs r0, #4 80144ca: f000 fc50 bl 8014d6e 80144ce: 61f8 str r0, [r7, #28] 80144d0: e016 b.n 8014500 #endif } else { hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem); 80144d2: 687b ldr r3, [r7, #4] 80144d4: 689b ldr r3, [r3, #8] 80144d6: 4619 mov r1, r3 80144d8: 2001 movs r0, #1 80144da: f000 fc48 bl 8014d6e 80144de: 61f8 str r0, [r7, #28] 80144e0: e00e b.n 8014500 } #endif } else { if (mem == 0) { 80144e2: 693b ldr r3, [r7, #16] 80144e4: 2b00 cmp r3, #0 80144e6: d10b bne.n 8014500 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (rmtx != 0U) { 80144e8: 697b ldr r3, [r7, #20] 80144ea: 2b00 cmp r3, #0 80144ec: d004 beq.n 80144f8 #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutex (); 80144ee: 2004 movs r0, #4 80144f0: f000 fc25 bl 8014d3e 80144f4: 61f8 str r0, [r7, #28] 80144f6: e003 b.n 8014500 #endif } else { hMutex = xSemaphoreCreateMutex (); 80144f8: 2001 movs r0, #1 80144fa: f000 fc20 bl 8014d3e 80144fe: 61f8 str r0, [r7, #28] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hMutex != NULL) { 8014500: 69fb ldr r3, [r7, #28] 8014502: 2b00 cmp r3, #0 8014504: d00c beq.n 8014520 if (attr != NULL) { 8014506: 687b ldr r3, [r7, #4] 8014508: 2b00 cmp r3, #0 801450a: d003 beq.n 8014514 name = attr->name; 801450c: 687b ldr r3, [r7, #4] 801450e: 681b ldr r3, [r3, #0] 8014510: 60fb str r3, [r7, #12] 8014512: e001 b.n 8014518 } else { name = NULL; 8014514: 2300 movs r3, #0 8014516: 60fb str r3, [r7, #12] } vQueueAddToRegistry (hMutex, name); 8014518: 68f9 ldr r1, [r7, #12] 801451a: 69f8 ldr r0, [r7, #28] 801451c: f001 f9ea bl 80158f4 } #endif if ((hMutex != NULL) && (rmtx != 0U)) { 8014520: 69fb ldr r3, [r7, #28] 8014522: 2b00 cmp r3, #0 8014524: d006 beq.n 8014534 8014526: 697b ldr r3, [r7, #20] 8014528: 2b00 cmp r3, #0 801452a: d003 beq.n 8014534 hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U); 801452c: 69fb ldr r3, [r7, #28] 801452e: f043 0301 orr.w r3, r3, #1 8014532: 61fb str r3, [r7, #28] } } } return ((osMutexId_t)hMutex); 8014534: 69fb ldr r3, [r7, #28] } 8014536: 4618 mov r0, r3 8014538: 3720 adds r7, #32 801453a: 46bd mov sp, r7 801453c: bd80 pop {r7, pc} 0801453e : osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { 801453e: b580 push {r7, lr} 8014540: b086 sub sp, #24 8014542: af00 add r7, sp, #0 8014544: 6078 str r0, [r7, #4] 8014546: 6039 str r1, [r7, #0] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 8014548: 687b ldr r3, [r7, #4] 801454a: f023 0301 bic.w r3, r3, #1 801454e: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 8014550: 687b ldr r3, [r7, #4] 8014552: f003 0301 and.w r3, r3, #1 8014556: 60fb str r3, [r7, #12] stat = osOK; 8014558: 2300 movs r3, #0 801455a: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801455c: f3ef 8305 mrs r3, IPSR 8014560: 60bb str r3, [r7, #8] return(result); 8014562: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 8014564: 2b00 cmp r3, #0 8014566: d003 beq.n 8014570 stat = osErrorISR; 8014568: f06f 0305 mvn.w r3, #5 801456c: 617b str r3, [r7, #20] 801456e: e02c b.n 80145ca } else if (hMutex == NULL) { 8014570: 693b ldr r3, [r7, #16] 8014572: 2b00 cmp r3, #0 8014574: d103 bne.n 801457e stat = osErrorParameter; 8014576: f06f 0303 mvn.w r3, #3 801457a: 617b str r3, [r7, #20] 801457c: e025 b.n 80145ca } else { if (rmtx != 0U) { 801457e: 68fb ldr r3, [r7, #12] 8014580: 2b00 cmp r3, #0 8014582: d011 beq.n 80145a8 #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) { 8014584: 6839 ldr r1, [r7, #0] 8014586: 6938 ldr r0, [r7, #16] 8014588: f000 fc41 bl 8014e0e 801458c: 4603 mov r3, r0 801458e: 2b01 cmp r3, #1 8014590: d01b beq.n 80145ca if (timeout != 0U) { 8014592: 683b ldr r3, [r7, #0] 8014594: 2b00 cmp r3, #0 8014596: d003 beq.n 80145a0 stat = osErrorTimeout; 8014598: f06f 0301 mvn.w r3, #1 801459c: 617b str r3, [r7, #20] 801459e: e014 b.n 80145ca } else { stat = osErrorResource; 80145a0: f06f 0302 mvn.w r3, #2 80145a4: 617b str r3, [r7, #20] 80145a6: e010 b.n 80145ca } } #endif } else { if (xSemaphoreTake (hMutex, timeout) != pdPASS) { 80145a8: 6839 ldr r1, [r7, #0] 80145aa: 6938 ldr r0, [r7, #16] 80145ac: f000 fee8 bl 8015380 80145b0: 4603 mov r3, r0 80145b2: 2b01 cmp r3, #1 80145b4: d009 beq.n 80145ca if (timeout != 0U) { 80145b6: 683b ldr r3, [r7, #0] 80145b8: 2b00 cmp r3, #0 80145ba: d003 beq.n 80145c4 stat = osErrorTimeout; 80145bc: f06f 0301 mvn.w r3, #1 80145c0: 617b str r3, [r7, #20] 80145c2: e002 b.n 80145ca } else { stat = osErrorResource; 80145c4: f06f 0302 mvn.w r3, #2 80145c8: 617b str r3, [r7, #20] } } } } return (stat); 80145ca: 697b ldr r3, [r7, #20] } 80145cc: 4618 mov r0, r3 80145ce: 3718 adds r7, #24 80145d0: 46bd mov sp, r7 80145d2: bd80 pop {r7, pc} 080145d4 : osStatus_t osMutexRelease (osMutexId_t mutex_id) { 80145d4: b580 push {r7, lr} 80145d6: b086 sub sp, #24 80145d8: af00 add r7, sp, #0 80145da: 6078 str r0, [r7, #4] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 80145dc: 687b ldr r3, [r7, #4] 80145de: f023 0301 bic.w r3, r3, #1 80145e2: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 80145e4: 687b ldr r3, [r7, #4] 80145e6: f003 0301 and.w r3, r3, #1 80145ea: 60fb str r3, [r7, #12] stat = osOK; 80145ec: 2300 movs r3, #0 80145ee: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80145f0: f3ef 8305 mrs r3, IPSR 80145f4: 60bb str r3, [r7, #8] return(result); 80145f6: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 80145f8: 2b00 cmp r3, #0 80145fa: d003 beq.n 8014604 stat = osErrorISR; 80145fc: f06f 0305 mvn.w r3, #5 8014600: 617b str r3, [r7, #20] 8014602: e01f b.n 8014644 } else if (hMutex == NULL) { 8014604: 693b ldr r3, [r7, #16] 8014606: 2b00 cmp r3, #0 8014608: d103 bne.n 8014612 stat = osErrorParameter; 801460a: f06f 0303 mvn.w r3, #3 801460e: 617b str r3, [r7, #20] 8014610: e018 b.n 8014644 } else { if (rmtx != 0U) { 8014612: 68fb ldr r3, [r7, #12] 8014614: 2b00 cmp r3, #0 8014616: d009 beq.n 801462c #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreGiveRecursive (hMutex) != pdPASS) { 8014618: 6938 ldr r0, [r7, #16] 801461a: f000 fbc3 bl 8014da4 801461e: 4603 mov r3, r0 8014620: 2b01 cmp r3, #1 8014622: d00f beq.n 8014644 stat = osErrorResource; 8014624: f06f 0302 mvn.w r3, #2 8014628: 617b str r3, [r7, #20] 801462a: e00b b.n 8014644 } #endif } else { if (xSemaphoreGive (hMutex) != pdPASS) { 801462c: 2300 movs r3, #0 801462e: 2200 movs r2, #0 8014630: 2100 movs r1, #0 8014632: 6938 ldr r0, [r7, #16] 8014634: f000 fc22 bl 8014e7c 8014638: 4603 mov r3, r0 801463a: 2b01 cmp r3, #1 801463c: d002 beq.n 8014644 stat = osErrorResource; 801463e: f06f 0302 mvn.w r3, #2 8014642: 617b str r3, [r7, #20] } } } return (stat); 8014644: 697b ldr r3, [r7, #20] } 8014646: 4618 mov r0, r3 8014648: 3718 adds r7, #24 801464a: 46bd mov sp, r7 801464c: bd80 pop {r7, pc} 0801464e : return (stat); } /*---------------------------------------------------------------------------*/ osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { 801464e: b580 push {r7, lr} 8014650: b08a sub sp, #40 @ 0x28 8014652: af02 add r7, sp, #8 8014654: 60f8 str r0, [r7, #12] 8014656: 60b9 str r1, [r7, #8] 8014658: 607a str r2, [r7, #4] int32_t mem; #if (configQUEUE_REGISTRY_SIZE > 0) const char *name; #endif hQueue = NULL; 801465a: 2300 movs r3, #0 801465c: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801465e: f3ef 8305 mrs r3, IPSR 8014662: 613b str r3, [r7, #16] return(result); 8014664: 693b ldr r3, [r7, #16] if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) { 8014666: 2b00 cmp r3, #0 8014668: d15f bne.n 801472a 801466a: 68fb ldr r3, [r7, #12] 801466c: 2b00 cmp r3, #0 801466e: d05c beq.n 801472a 8014670: 68bb ldr r3, [r7, #8] 8014672: 2b00 cmp r3, #0 8014674: d059 beq.n 801472a mem = -1; 8014676: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801467a: 61bb str r3, [r7, #24] if (attr != NULL) { 801467c: 687b ldr r3, [r7, #4] 801467e: 2b00 cmp r3, #0 8014680: d029 beq.n 80146d6 if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 8014682: 687b ldr r3, [r7, #4] 8014684: 689b ldr r3, [r3, #8] 8014686: 2b00 cmp r3, #0 8014688: d012 beq.n 80146b0 801468a: 687b ldr r3, [r7, #4] 801468c: 68db ldr r3, [r3, #12] 801468e: 2b4f cmp r3, #79 @ 0x4f 8014690: d90e bls.n 80146b0 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 8014692: 687b ldr r3, [r7, #4] 8014694: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 8014696: 2b00 cmp r3, #0 8014698: d00a beq.n 80146b0 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 801469a: 687b ldr r3, [r7, #4] 801469c: 695a ldr r2, [r3, #20] 801469e: 68fb ldr r3, [r7, #12] 80146a0: 68b9 ldr r1, [r7, #8] 80146a2: fb01 f303 mul.w r3, r1, r3 80146a6: 429a cmp r2, r3 80146a8: d302 bcc.n 80146b0 mem = 1; 80146aa: 2301 movs r3, #1 80146ac: 61bb str r3, [r7, #24] 80146ae: e014 b.n 80146da } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 80146b0: 687b ldr r3, [r7, #4] 80146b2: 689b ldr r3, [r3, #8] 80146b4: 2b00 cmp r3, #0 80146b6: d110 bne.n 80146da 80146b8: 687b ldr r3, [r7, #4] 80146ba: 68db ldr r3, [r3, #12] 80146bc: 2b00 cmp r3, #0 80146be: d10c bne.n 80146da (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 80146c0: 687b ldr r3, [r7, #4] 80146c2: 691b ldr r3, [r3, #16] if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 80146c4: 2b00 cmp r3, #0 80146c6: d108 bne.n 80146da (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 80146c8: 687b ldr r3, [r7, #4] 80146ca: 695b ldr r3, [r3, #20] 80146cc: 2b00 cmp r3, #0 80146ce: d104 bne.n 80146da mem = 0; 80146d0: 2300 movs r3, #0 80146d2: 61bb str r3, [r7, #24] 80146d4: e001 b.n 80146da } } } else { mem = 0; 80146d6: 2300 movs r3, #0 80146d8: 61bb str r3, [r7, #24] } if (mem == 1) { 80146da: 69bb ldr r3, [r7, #24] 80146dc: 2b01 cmp r3, #1 80146de: d10b bne.n 80146f8 #if (configSUPPORT_STATIC_ALLOCATION == 1) hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem); 80146e0: 687b ldr r3, [r7, #4] 80146e2: 691a ldr r2, [r3, #16] 80146e4: 687b ldr r3, [r7, #4] 80146e6: 689b ldr r3, [r3, #8] 80146e8: 2100 movs r1, #0 80146ea: 9100 str r1, [sp, #0] 80146ec: 68b9 ldr r1, [r7, #8] 80146ee: 68f8 ldr r0, [r7, #12] 80146f0: f000 fa30 bl 8014b54 80146f4: 61f8 str r0, [r7, #28] 80146f6: e008 b.n 801470a #endif } else { if (mem == 0) { 80146f8: 69bb ldr r3, [r7, #24] 80146fa: 2b00 cmp r3, #0 80146fc: d105 bne.n 801470a #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hQueue = xQueueCreate (msg_count, msg_size); 80146fe: 2200 movs r2, #0 8014700: 68b9 ldr r1, [r7, #8] 8014702: 68f8 ldr r0, [r7, #12] 8014704: f000 faa3 bl 8014c4e 8014708: 61f8 str r0, [r7, #28] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hQueue != NULL) { 801470a: 69fb ldr r3, [r7, #28] 801470c: 2b00 cmp r3, #0 801470e: d00c beq.n 801472a if (attr != NULL) { 8014710: 687b ldr r3, [r7, #4] 8014712: 2b00 cmp r3, #0 8014714: d003 beq.n 801471e name = attr->name; 8014716: 687b ldr r3, [r7, #4] 8014718: 681b ldr r3, [r3, #0] 801471a: 617b str r3, [r7, #20] 801471c: e001 b.n 8014722 } else { name = NULL; 801471e: 2300 movs r3, #0 8014720: 617b str r3, [r7, #20] } vQueueAddToRegistry (hQueue, name); 8014722: 6979 ldr r1, [r7, #20] 8014724: 69f8 ldr r0, [r7, #28] 8014726: f001 f8e5 bl 80158f4 } #endif } return ((osMessageQueueId_t)hQueue); 801472a: 69fb ldr r3, [r7, #28] } 801472c: 4618 mov r0, r3 801472e: 3720 adds r7, #32 8014730: 46bd mov sp, r7 8014732: bd80 pop {r7, pc} 08014734 : osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { 8014734: b580 push {r7, lr} 8014736: b088 sub sp, #32 8014738: af00 add r7, sp, #0 801473a: 60f8 str r0, [r7, #12] 801473c: 60b9 str r1, [r7, #8] 801473e: 603b str r3, [r7, #0] 8014740: 4613 mov r3, r2 8014742: 71fb strb r3, [r7, #7] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 8014744: 68fb ldr r3, [r7, #12] 8014746: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 8014748: 2300 movs r3, #0 801474a: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801474c: f3ef 8305 mrs r3, IPSR 8014750: 617b str r3, [r7, #20] return(result); 8014752: 697b ldr r3, [r7, #20] if (IS_IRQ()) { 8014754: 2b00 cmp r3, #0 8014756: d028 beq.n 80147aa if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 8014758: 69bb ldr r3, [r7, #24] 801475a: 2b00 cmp r3, #0 801475c: d005 beq.n 801476a 801475e: 68bb ldr r3, [r7, #8] 8014760: 2b00 cmp r3, #0 8014762: d002 beq.n 801476a 8014764: 683b ldr r3, [r7, #0] 8014766: 2b00 cmp r3, #0 8014768: d003 beq.n 8014772 stat = osErrorParameter; 801476a: f06f 0303 mvn.w r3, #3 801476e: 61fb str r3, [r7, #28] 8014770: e038 b.n 80147e4 } else { yield = pdFALSE; 8014772: 2300 movs r3, #0 8014774: 613b str r3, [r7, #16] if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { 8014776: f107 0210 add.w r2, r7, #16 801477a: 2300 movs r3, #0 801477c: 68b9 ldr r1, [r7, #8] 801477e: 69b8 ldr r0, [r7, #24] 8014780: f000 fc7e bl 8015080 8014784: 4603 mov r3, r0 8014786: 2b01 cmp r3, #1 8014788: d003 beq.n 8014792 stat = osErrorResource; 801478a: f06f 0302 mvn.w r3, #2 801478e: 61fb str r3, [r7, #28] 8014790: e028 b.n 80147e4 } else { portYIELD_FROM_ISR (yield); 8014792: 693b ldr r3, [r7, #16] 8014794: 2b00 cmp r3, #0 8014796: d025 beq.n 80147e4 8014798: 4b15 ldr r3, [pc, #84] @ (80147f0 ) 801479a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801479e: 601a str r2, [r3, #0] 80147a0: f3bf 8f4f dsb sy 80147a4: f3bf 8f6f isb sy 80147a8: e01c b.n 80147e4 } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 80147aa: 69bb ldr r3, [r7, #24] 80147ac: 2b00 cmp r3, #0 80147ae: d002 beq.n 80147b6 80147b0: 68bb ldr r3, [r7, #8] 80147b2: 2b00 cmp r3, #0 80147b4: d103 bne.n 80147be stat = osErrorParameter; 80147b6: f06f 0303 mvn.w r3, #3 80147ba: 61fb str r3, [r7, #28] 80147bc: e012 b.n 80147e4 } else { if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 80147be: 2300 movs r3, #0 80147c0: 683a ldr r2, [r7, #0] 80147c2: 68b9 ldr r1, [r7, #8] 80147c4: 69b8 ldr r0, [r7, #24] 80147c6: f000 fb59 bl 8014e7c 80147ca: 4603 mov r3, r0 80147cc: 2b01 cmp r3, #1 80147ce: d009 beq.n 80147e4 if (timeout != 0U) { 80147d0: 683b ldr r3, [r7, #0] 80147d2: 2b00 cmp r3, #0 80147d4: d003 beq.n 80147de stat = osErrorTimeout; 80147d6: f06f 0301 mvn.w r3, #1 80147da: 61fb str r3, [r7, #28] 80147dc: e002 b.n 80147e4 } else { stat = osErrorResource; 80147de: f06f 0302 mvn.w r3, #2 80147e2: 61fb str r3, [r7, #28] } } } } return (stat); 80147e4: 69fb ldr r3, [r7, #28] } 80147e6: 4618 mov r0, r3 80147e8: 3720 adds r7, #32 80147ea: 46bd mov sp, r7 80147ec: bd80 pop {r7, pc} 80147ee: bf00 nop 80147f0: e000ed04 .word 0xe000ed04 080147f4 : osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { 80147f4: b580 push {r7, lr} 80147f6: b088 sub sp, #32 80147f8: af00 add r7, sp, #0 80147fa: 60f8 str r0, [r7, #12] 80147fc: 60b9 str r1, [r7, #8] 80147fe: 607a str r2, [r7, #4] 8014800: 603b str r3, [r7, #0] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 8014802: 68fb ldr r3, [r7, #12] 8014804: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 8014806: 2300 movs r3, #0 8014808: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801480a: f3ef 8305 mrs r3, IPSR 801480e: 617b str r3, [r7, #20] return(result); 8014810: 697b ldr r3, [r7, #20] if (IS_IRQ()) { 8014812: 2b00 cmp r3, #0 8014814: d028 beq.n 8014868 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 8014816: 69bb ldr r3, [r7, #24] 8014818: 2b00 cmp r3, #0 801481a: d005 beq.n 8014828 801481c: 68bb ldr r3, [r7, #8] 801481e: 2b00 cmp r3, #0 8014820: d002 beq.n 8014828 8014822: 683b ldr r3, [r7, #0] 8014824: 2b00 cmp r3, #0 8014826: d003 beq.n 8014830 stat = osErrorParameter; 8014828: f06f 0303 mvn.w r3, #3 801482c: 61fb str r3, [r7, #28] 801482e: e037 b.n 80148a0 } else { yield = pdFALSE; 8014830: 2300 movs r3, #0 8014832: 613b str r3, [r7, #16] if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) { 8014834: f107 0310 add.w r3, r7, #16 8014838: 461a mov r2, r3 801483a: 68b9 ldr r1, [r7, #8] 801483c: 69b8 ldr r0, [r7, #24] 801483e: f000 feaf bl 80155a0 8014842: 4603 mov r3, r0 8014844: 2b01 cmp r3, #1 8014846: d003 beq.n 8014850 stat = osErrorResource; 8014848: f06f 0302 mvn.w r3, #2 801484c: 61fb str r3, [r7, #28] 801484e: e027 b.n 80148a0 } else { portYIELD_FROM_ISR (yield); 8014850: 693b ldr r3, [r7, #16] 8014852: 2b00 cmp r3, #0 8014854: d024 beq.n 80148a0 8014856: 4b15 ldr r3, [pc, #84] @ (80148ac ) 8014858: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801485c: 601a str r2, [r3, #0] 801485e: f3bf 8f4f dsb sy 8014862: f3bf 8f6f isb sy 8014866: e01b b.n 80148a0 } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 8014868: 69bb ldr r3, [r7, #24] 801486a: 2b00 cmp r3, #0 801486c: d002 beq.n 8014874 801486e: 68bb ldr r3, [r7, #8] 8014870: 2b00 cmp r3, #0 8014872: d103 bne.n 801487c stat = osErrorParameter; 8014874: f06f 0303 mvn.w r3, #3 8014878: 61fb str r3, [r7, #28] 801487a: e011 b.n 80148a0 } else { if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 801487c: 683a ldr r2, [r7, #0] 801487e: 68b9 ldr r1, [r7, #8] 8014880: 69b8 ldr r0, [r7, #24] 8014882: f000 fc9b bl 80151bc 8014886: 4603 mov r3, r0 8014888: 2b01 cmp r3, #1 801488a: d009 beq.n 80148a0 if (timeout != 0U) { 801488c: 683b ldr r3, [r7, #0] 801488e: 2b00 cmp r3, #0 8014890: d003 beq.n 801489a stat = osErrorTimeout; 8014892: f06f 0301 mvn.w r3, #1 8014896: 61fb str r3, [r7, #28] 8014898: e002 b.n 80148a0 } else { stat = osErrorResource; 801489a: f06f 0302 mvn.w r3, #2 801489e: 61fb str r3, [r7, #28] } } } } return (stat); 80148a0: 69fb ldr r3, [r7, #28] } 80148a2: 4618 mov r0, r3 80148a4: 3720 adds r7, #32 80148a6: 46bd mov sp, r7 80148a8: bd80 pop {r7, pc} 80148aa: bf00 nop 80148ac: e000ed04 .word 0xe000ed04 080148b0 : /* vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { 80148b0: b480 push {r7} 80148b2: b085 sub sp, #20 80148b4: af00 add r7, sp, #0 80148b6: 60f8 str r0, [r7, #12] 80148b8: 60b9 str r1, [r7, #8] 80148ba: 607a str r2, [r7, #4] /* Idle task control block and stack */ static StaticTask_t Idle_TCB; static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; *ppxIdleTaskTCBBuffer = &Idle_TCB; 80148bc: 68fb ldr r3, [r7, #12] 80148be: 4a07 ldr r2, [pc, #28] @ (80148dc ) 80148c0: 601a str r2, [r3, #0] *ppxIdleTaskStackBuffer = &Idle_Stack[0]; 80148c2: 68bb ldr r3, [r7, #8] 80148c4: 4a06 ldr r2, [pc, #24] @ (80148e0 ) 80148c6: 601a str r2, [r3, #0] *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; 80148c8: 687b ldr r3, [r7, #4] 80148ca: f44f 7200 mov.w r2, #512 @ 0x200 80148ce: 601a str r2, [r3, #0] } 80148d0: bf00 nop 80148d2: 3714 adds r7, #20 80148d4: 46bd mov sp, r7 80148d6: f85d 7b04 ldr.w r7, [sp], #4 80148da: 4770 bx lr 80148dc: 24001068 .word 0x24001068 80148e0: 24001110 .word 0x24001110 080148e4 : /* vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { 80148e4: b480 push {r7} 80148e6: b085 sub sp, #20 80148e8: af00 add r7, sp, #0 80148ea: 60f8 str r0, [r7, #12] 80148ec: 60b9 str r1, [r7, #8] 80148ee: 607a str r2, [r7, #4] /* Timer task control block and stack */ static StaticTask_t Timer_TCB; static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; *ppxTimerTaskTCBBuffer = &Timer_TCB; 80148f0: 68fb ldr r3, [r7, #12] 80148f2: 4a07 ldr r2, [pc, #28] @ (8014910 ) 80148f4: 601a str r2, [r3, #0] *ppxTimerTaskStackBuffer = &Timer_Stack[0]; 80148f6: 68bb ldr r3, [r7, #8] 80148f8: 4a06 ldr r2, [pc, #24] @ (8014914 ) 80148fa: 601a str r2, [r3, #0] *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; 80148fc: 687b ldr r3, [r7, #4] 80148fe: f44f 6280 mov.w r2, #1024 @ 0x400 8014902: 601a str r2, [r3, #0] } 8014904: bf00 nop 8014906: 3714 adds r7, #20 8014908: 46bd mov sp, r7 801490a: f85d 7b04 ldr.w r7, [sp], #4 801490e: 4770 bx lr 8014910: 24001910 .word 0x24001910 8014914: 240019b8 .word 0x240019b8 08014918 : /*----------------------------------------------------------- * PUBLIC LIST API documented in list.h *----------------------------------------------------------*/ void vListInitialise( List_t * const pxList ) { 8014918: b480 push {r7} 801491a: b083 sub sp, #12 801491c: af00 add r7, sp, #0 801491e: 6078 str r0, [r7, #4] /* The list structure contains a list item which is used to mark the end of the list. To initialise the list the list end is inserted as the only list entry. */ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8014920: 687b ldr r3, [r7, #4] 8014922: f103 0208 add.w r2, r3, #8 8014926: 687b ldr r3, [r7, #4] 8014928: 605a str r2, [r3, #4] /* The list end value is the highest possible value in the list to ensure it remains at the end of the list. */ pxList->xListEnd.xItemValue = portMAX_DELAY; 801492a: 687b ldr r3, [r7, #4] 801492c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8014930: 609a str r2, [r3, #8] /* The list end next and previous pointers point to itself so we know when the list is empty. */ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8014932: 687b ldr r3, [r7, #4] 8014934: f103 0208 add.w r2, r3, #8 8014938: 687b ldr r3, [r7, #4] 801493a: 60da str r2, [r3, #12] pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 801493c: 687b ldr r3, [r7, #4] 801493e: f103 0208 add.w r2, r3, #8 8014942: 687b ldr r3, [r7, #4] 8014944: 611a str r2, [r3, #16] pxList->uxNumberOfItems = ( UBaseType_t ) 0U; 8014946: 687b ldr r3, [r7, #4] 8014948: 2200 movs r2, #0 801494a: 601a str r2, [r3, #0] /* Write known values into the list if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); } 801494c: bf00 nop 801494e: 370c adds r7, #12 8014950: 46bd mov sp, r7 8014952: f85d 7b04 ldr.w r7, [sp], #4 8014956: 4770 bx lr 08014958 : /*-----------------------------------------------------------*/ void vListInitialiseItem( ListItem_t * const pxItem ) { 8014958: b480 push {r7} 801495a: b083 sub sp, #12 801495c: af00 add r7, sp, #0 801495e: 6078 str r0, [r7, #4] /* Make sure the list item is not recorded as being on a list. */ pxItem->pxContainer = NULL; 8014960: 687b ldr r3, [r7, #4] 8014962: 2200 movs r2, #0 8014964: 611a str r2, [r3, #16] /* Write known values into the list item if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } 8014966: bf00 nop 8014968: 370c adds r7, #12 801496a: 46bd mov sp, r7 801496c: f85d 7b04 ldr.w r7, [sp], #4 8014970: 4770 bx lr 08014972 : /*-----------------------------------------------------------*/ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8014972: b480 push {r7} 8014974: b085 sub sp, #20 8014976: af00 add r7, sp, #0 8014978: 6078 str r0, [r7, #4] 801497a: 6039 str r1, [r7, #0] ListItem_t * const pxIndex = pxList->pxIndex; 801497c: 687b ldr r3, [r7, #4] 801497e: 685b ldr r3, [r3, #4] 8014980: 60fb str r3, [r7, #12] listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); /* Insert a new list item into pxList, but rather than sort the list, makes the new list item the last item to be removed by a call to listGET_OWNER_OF_NEXT_ENTRY(). */ pxNewListItem->pxNext = pxIndex; 8014982: 683b ldr r3, [r7, #0] 8014984: 68fa ldr r2, [r7, #12] 8014986: 605a str r2, [r3, #4] pxNewListItem->pxPrevious = pxIndex->pxPrevious; 8014988: 68fb ldr r3, [r7, #12] 801498a: 689a ldr r2, [r3, #8] 801498c: 683b ldr r3, [r7, #0] 801498e: 609a str r2, [r3, #8] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); pxIndex->pxPrevious->pxNext = pxNewListItem; 8014990: 68fb ldr r3, [r7, #12] 8014992: 689b ldr r3, [r3, #8] 8014994: 683a ldr r2, [r7, #0] 8014996: 605a str r2, [r3, #4] pxIndex->pxPrevious = pxNewListItem; 8014998: 68fb ldr r3, [r7, #12] 801499a: 683a ldr r2, [r7, #0] 801499c: 609a str r2, [r3, #8] /* Remember which list the item is in. */ pxNewListItem->pxContainer = pxList; 801499e: 683b ldr r3, [r7, #0] 80149a0: 687a ldr r2, [r7, #4] 80149a2: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 80149a4: 687b ldr r3, [r7, #4] 80149a6: 681b ldr r3, [r3, #0] 80149a8: 1c5a adds r2, r3, #1 80149aa: 687b ldr r3, [r7, #4] 80149ac: 601a str r2, [r3, #0] } 80149ae: bf00 nop 80149b0: 3714 adds r7, #20 80149b2: 46bd mov sp, r7 80149b4: f85d 7b04 ldr.w r7, [sp], #4 80149b8: 4770 bx lr 080149ba : /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { 80149ba: b480 push {r7} 80149bc: b085 sub sp, #20 80149be: af00 add r7, sp, #0 80149c0: 6078 str r0, [r7, #4] 80149c2: 6039 str r1, [r7, #0] ListItem_t *pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; 80149c4: 683b ldr r3, [r7, #0] 80149c6: 681b ldr r3, [r3, #0] 80149c8: 60bb str r3, [r7, #8] new list item should be placed after it. This ensures that TCBs which are stored in ready lists (all of which have the same xItemValue value) get a share of the CPU. However, if the xItemValue is the same as the back marker the iteration loop below will not end. Therefore the value is checked first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) 80149ca: 68bb ldr r3, [r7, #8] 80149cc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80149d0: d103 bne.n 80149da { pxIterator = pxList->xListEnd.pxPrevious; 80149d2: 687b ldr r3, [r7, #4] 80149d4: 691b ldr r3, [r3, #16] 80149d6: 60fb str r3, [r7, #12] 80149d8: e00c b.n 80149f4 4) Using a queue or semaphore before it has been initialised or before the scheduler has been started (are interrupts firing before vTaskStartScheduler() has been called?). **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ 80149da: 687b ldr r3, [r7, #4] 80149dc: 3308 adds r3, #8 80149de: 60fb str r3, [r7, #12] 80149e0: e002 b.n 80149e8 80149e2: 68fb ldr r3, [r7, #12] 80149e4: 685b ldr r3, [r3, #4] 80149e6: 60fb str r3, [r7, #12] 80149e8: 68fb ldr r3, [r7, #12] 80149ea: 685b ldr r3, [r3, #4] 80149ec: 681b ldr r3, [r3, #0] 80149ee: 68ba ldr r2, [r7, #8] 80149f0: 429a cmp r2, r3 80149f2: d2f6 bcs.n 80149e2 /* There is nothing to do here, just iterating to the wanted insertion position. */ } } pxNewListItem->pxNext = pxIterator->pxNext; 80149f4: 68fb ldr r3, [r7, #12] 80149f6: 685a ldr r2, [r3, #4] 80149f8: 683b ldr r3, [r7, #0] 80149fa: 605a str r2, [r3, #4] pxNewListItem->pxNext->pxPrevious = pxNewListItem; 80149fc: 683b ldr r3, [r7, #0] 80149fe: 685b ldr r3, [r3, #4] 8014a00: 683a ldr r2, [r7, #0] 8014a02: 609a str r2, [r3, #8] pxNewListItem->pxPrevious = pxIterator; 8014a04: 683b ldr r3, [r7, #0] 8014a06: 68fa ldr r2, [r7, #12] 8014a08: 609a str r2, [r3, #8] pxIterator->pxNext = pxNewListItem; 8014a0a: 68fb ldr r3, [r7, #12] 8014a0c: 683a ldr r2, [r7, #0] 8014a0e: 605a str r2, [r3, #4] /* Remember which list the item is in. This allows fast removal of the item later. */ pxNewListItem->pxContainer = pxList; 8014a10: 683b ldr r3, [r7, #0] 8014a12: 687a ldr r2, [r7, #4] 8014a14: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8014a16: 687b ldr r3, [r7, #4] 8014a18: 681b ldr r3, [r3, #0] 8014a1a: 1c5a adds r2, r3, #1 8014a1c: 687b ldr r3, [r7, #4] 8014a1e: 601a str r2, [r3, #0] } 8014a20: bf00 nop 8014a22: 3714 adds r7, #20 8014a24: 46bd mov sp, r7 8014a26: f85d 7b04 ldr.w r7, [sp], #4 8014a2a: 4770 bx lr 08014a2c : /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { 8014a2c: b480 push {r7} 8014a2e: b085 sub sp, #20 8014a30: af00 add r7, sp, #0 8014a32: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list item. */ List_t * const pxList = pxItemToRemove->pxContainer; 8014a34: 687b ldr r3, [r7, #4] 8014a36: 691b ldr r3, [r3, #16] 8014a38: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 8014a3a: 687b ldr r3, [r7, #4] 8014a3c: 685b ldr r3, [r3, #4] 8014a3e: 687a ldr r2, [r7, #4] 8014a40: 6892 ldr r2, [r2, #8] 8014a42: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; 8014a44: 687b ldr r3, [r7, #4] 8014a46: 689b ldr r3, [r3, #8] 8014a48: 687a ldr r2, [r7, #4] 8014a4a: 6852 ldr r2, [r2, #4] 8014a4c: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) 8014a4e: 68fb ldr r3, [r7, #12] 8014a50: 685b ldr r3, [r3, #4] 8014a52: 687a ldr r2, [r7, #4] 8014a54: 429a cmp r2, r3 8014a56: d103 bne.n 8014a60 { pxList->pxIndex = pxItemToRemove->pxPrevious; 8014a58: 687b ldr r3, [r7, #4] 8014a5a: 689a ldr r2, [r3, #8] 8014a5c: 68fb ldr r3, [r7, #12] 8014a5e: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; 8014a60: 687b ldr r3, [r7, #4] 8014a62: 2200 movs r2, #0 8014a64: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; 8014a66: 68fb ldr r3, [r7, #12] 8014a68: 681b ldr r3, [r3, #0] 8014a6a: 1e5a subs r2, r3, #1 8014a6c: 68fb ldr r3, [r7, #12] 8014a6e: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; 8014a70: 68fb ldr r3, [r7, #12] 8014a72: 681b ldr r3, [r3, #0] } 8014a74: 4618 mov r0, r3 8014a76: 3714 adds r7, #20 8014a78: 46bd mov sp, r7 8014a7a: f85d 7b04 ldr.w r7, [sp], #4 8014a7e: 4770 bx lr 08014a80 : } \ taskEXIT_CRITICAL() /*-----------------------------------------------------------*/ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) { 8014a80: b580 push {r7, lr} 8014a82: b084 sub sp, #16 8014a84: af00 add r7, sp, #0 8014a86: 6078 str r0, [r7, #4] 8014a88: 6039 str r1, [r7, #0] Queue_t * const pxQueue = xQueue; 8014a8a: 687b ldr r3, [r7, #4] 8014a8c: 60fb str r3, [r7, #12] configASSERT( pxQueue ); 8014a8e: 68fb ldr r3, [r7, #12] 8014a90: 2b00 cmp r3, #0 8014a92: d10b bne.n 8014aac portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile 8014a94: f04f 0350 mov.w r3, #80 @ 0x50 8014a98: f383 8811 msr BASEPRI, r3 8014a9c: f3bf 8f6f isb sy 8014aa0: f3bf 8f4f dsb sy 8014aa4: 60bb str r3, [r7, #8] " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } 8014aa6: bf00 nop 8014aa8: bf00 nop 8014aaa: e7fd b.n 8014aa8 taskENTER_CRITICAL(); 8014aac: f003 f964 bl 8017d78 { pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8014ab0: 68fb ldr r3, [r7, #12] 8014ab2: 681a ldr r2, [r3, #0] 8014ab4: 68fb ldr r3, [r7, #12] 8014ab6: 6bdb ldr r3, [r3, #60] @ 0x3c 8014ab8: 68f9 ldr r1, [r7, #12] 8014aba: 6c09 ldr r1, [r1, #64] @ 0x40 8014abc: fb01 f303 mul.w r3, r1, r3 8014ac0: 441a add r2, r3 8014ac2: 68fb ldr r3, [r7, #12] 8014ac4: 609a str r2, [r3, #8] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 8014ac6: 68fb ldr r3, [r7, #12] 8014ac8: 2200 movs r2, #0 8014aca: 639a str r2, [r3, #56] @ 0x38 pxQueue->pcWriteTo = pxQueue->pcHead; 8014acc: 68fb ldr r3, [r7, #12] 8014ace: 681a ldr r2, [r3, #0] 8014ad0: 68fb ldr r3, [r7, #12] 8014ad2: 605a str r2, [r3, #4] pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8014ad4: 68fb ldr r3, [r7, #12] 8014ad6: 681a ldr r2, [r3, #0] 8014ad8: 68fb ldr r3, [r7, #12] 8014ada: 6bdb ldr r3, [r3, #60] @ 0x3c 8014adc: 3b01 subs r3, #1 8014ade: 68f9 ldr r1, [r7, #12] 8014ae0: 6c09 ldr r1, [r1, #64] @ 0x40 8014ae2: fb01 f303 mul.w r3, r1, r3 8014ae6: 441a add r2, r3 8014ae8: 68fb ldr r3, [r7, #12] 8014aea: 60da str r2, [r3, #12] pxQueue->cRxLock = queueUNLOCKED; 8014aec: 68fb ldr r3, [r7, #12] 8014aee: 22ff movs r2, #255 @ 0xff 8014af0: f883 2044 strb.w r2, [r3, #68] @ 0x44 pxQueue->cTxLock = queueUNLOCKED; 8014af4: 68fb ldr r3, [r7, #12] 8014af6: 22ff movs r2, #255 @ 0xff 8014af8: f883 2045 strb.w r2, [r3, #69] @ 0x45 if( xNewQueue == pdFALSE ) 8014afc: 683b ldr r3, [r7, #0] 8014afe: 2b00 cmp r3, #0 8014b00: d114 bne.n 8014b2c /* If there are tasks blocked waiting to read from the queue, then the tasks will remain blocked as after this function exits the queue will still be empty. If there are tasks blocked waiting to write to the queue, then one should be unblocked as after this function exits it will be possible to write to it. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8014b02: 68fb ldr r3, [r7, #12] 8014b04: 691b ldr r3, [r3, #16] 8014b06: 2b00 cmp r3, #0 8014b08: d01a beq.n 8014b40 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014b0a: 68fb ldr r3, [r7, #12] 8014b0c: 3310 adds r3, #16 8014b0e: 4618 mov r0, r3 8014b10: f001 fdac bl 801666c 8014b14: 4603 mov r3, r0 8014b16: 2b00 cmp r3, #0 8014b18: d012 beq.n 8014b40 { queueYIELD_IF_USING_PREEMPTION(); 8014b1a: 4b0d ldr r3, [pc, #52] @ (8014b50 ) 8014b1c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014b20: 601a str r2, [r3, #0] 8014b22: f3bf 8f4f dsb sy 8014b26: f3bf 8f6f isb sy 8014b2a: e009 b.n 8014b40 } } else { /* Ensure the event queues start in the correct state. */ vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 8014b2c: 68fb ldr r3, [r7, #12] 8014b2e: 3310 adds r3, #16 8014b30: 4618 mov r0, r3 8014b32: f7ff fef1 bl 8014918 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); 8014b36: 68fb ldr r3, [r7, #12] 8014b38: 3324 adds r3, #36 @ 0x24 8014b3a: 4618 mov r0, r3 8014b3c: f7ff feec bl 8014918 } } taskEXIT_CRITICAL(); 8014b40: f003 f94c bl 8017ddc /* A value is returned for calling semantic consistency with previous versions. */ return pdPASS; 8014b44: 2301 movs r3, #1 } 8014b46: 4618 mov r0, r3 8014b48: 3710 adds r7, #16 8014b4a: 46bd mov sp, r7 8014b4c: bd80 pop {r7, pc} 8014b4e: bf00 nop 8014b50: e000ed04 .word 0xe000ed04 08014b54 : /*-----------------------------------------------------------*/ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) { 8014b54: b580 push {r7, lr} 8014b56: b08e sub sp, #56 @ 0x38 8014b58: af02 add r7, sp, #8 8014b5a: 60f8 str r0, [r7, #12] 8014b5c: 60b9 str r1, [r7, #8] 8014b5e: 607a str r2, [r7, #4] 8014b60: 603b str r3, [r7, #0] Queue_t *pxNewQueue; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 8014b62: 68fb ldr r3, [r7, #12] 8014b64: 2b00 cmp r3, #0 8014b66: d10b bne.n 8014b80 __asm volatile 8014b68: f04f 0350 mov.w r3, #80 @ 0x50 8014b6c: f383 8811 msr BASEPRI, r3 8014b70: f3bf 8f6f isb sy 8014b74: f3bf 8f4f dsb sy 8014b78: 62bb str r3, [r7, #40] @ 0x28 } 8014b7a: bf00 nop 8014b7c: bf00 nop 8014b7e: e7fd b.n 8014b7c /* The StaticQueue_t structure and the queue storage area must be supplied. */ configASSERT( pxStaticQueue != NULL ); 8014b80: 683b ldr r3, [r7, #0] 8014b82: 2b00 cmp r3, #0 8014b84: d10b bne.n 8014b9e __asm volatile 8014b86: f04f 0350 mov.w r3, #80 @ 0x50 8014b8a: f383 8811 msr BASEPRI, r3 8014b8e: f3bf 8f6f isb sy 8014b92: f3bf 8f4f dsb sy 8014b96: 627b str r3, [r7, #36] @ 0x24 } 8014b98: bf00 nop 8014b9a: bf00 nop 8014b9c: e7fd b.n 8014b9a /* A queue storage area should be provided if the item size is not 0, and should not be provided if the item size is 0. */ configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); 8014b9e: 687b ldr r3, [r7, #4] 8014ba0: 2b00 cmp r3, #0 8014ba2: d002 beq.n 8014baa 8014ba4: 68bb ldr r3, [r7, #8] 8014ba6: 2b00 cmp r3, #0 8014ba8: d001 beq.n 8014bae 8014baa: 2301 movs r3, #1 8014bac: e000 b.n 8014bb0 8014bae: 2300 movs r3, #0 8014bb0: 2b00 cmp r3, #0 8014bb2: d10b bne.n 8014bcc __asm volatile 8014bb4: f04f 0350 mov.w r3, #80 @ 0x50 8014bb8: f383 8811 msr BASEPRI, r3 8014bbc: f3bf 8f6f isb sy 8014bc0: f3bf 8f4f dsb sy 8014bc4: 623b str r3, [r7, #32] } 8014bc6: bf00 nop 8014bc8: bf00 nop 8014bca: e7fd b.n 8014bc8 configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); 8014bcc: 687b ldr r3, [r7, #4] 8014bce: 2b00 cmp r3, #0 8014bd0: d102 bne.n 8014bd8 8014bd2: 68bb ldr r3, [r7, #8] 8014bd4: 2b00 cmp r3, #0 8014bd6: d101 bne.n 8014bdc 8014bd8: 2301 movs r3, #1 8014bda: e000 b.n 8014bde 8014bdc: 2300 movs r3, #0 8014bde: 2b00 cmp r3, #0 8014be0: d10b bne.n 8014bfa __asm volatile 8014be2: f04f 0350 mov.w r3, #80 @ 0x50 8014be6: f383 8811 msr BASEPRI, r3 8014bea: f3bf 8f6f isb sy 8014bee: f3bf 8f4f dsb sy 8014bf2: 61fb str r3, [r7, #28] } 8014bf4: bf00 nop 8014bf6: bf00 nop 8014bf8: e7fd b.n 8014bf6 #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticQueue_t or StaticSemaphore_t equals the size of the real queue and semaphore structures. */ volatile size_t xSize = sizeof( StaticQueue_t ); 8014bfa: 2350 movs r3, #80 @ 0x50 8014bfc: 617b str r3, [r7, #20] configASSERT( xSize == sizeof( Queue_t ) ); 8014bfe: 697b ldr r3, [r7, #20] 8014c00: 2b50 cmp r3, #80 @ 0x50 8014c02: d00b beq.n 8014c1c __asm volatile 8014c04: f04f 0350 mov.w r3, #80 @ 0x50 8014c08: f383 8811 msr BASEPRI, r3 8014c0c: f3bf 8f6f isb sy 8014c10: f3bf 8f4f dsb sy 8014c14: 61bb str r3, [r7, #24] } 8014c16: bf00 nop 8014c18: bf00 nop 8014c1a: e7fd b.n 8014c18 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 8014c1c: 697b ldr r3, [r7, #20] #endif /* configASSERT_DEFINED */ /* The address of a statically allocated queue was passed in, use it. The address of a statically allocated storage area was also passed in but is already set. */ pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8014c1e: 683b ldr r3, [r7, #0] 8014c20: 62fb str r3, [r7, #44] @ 0x2c if( pxNewQueue != NULL ) 8014c22: 6afb ldr r3, [r7, #44] @ 0x2c 8014c24: 2b00 cmp r3, #0 8014c26: d00d beq.n 8014c44 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* Queues can be allocated wither statically or dynamically, so note this queue was allocated statically in case the queue is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdTRUE; 8014c28: 6afb ldr r3, [r7, #44] @ 0x2c 8014c2a: 2201 movs r2, #1 8014c2c: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8014c30: f897 2038 ldrb.w r2, [r7, #56] @ 0x38 8014c34: 6afb ldr r3, [r7, #44] @ 0x2c 8014c36: 9300 str r3, [sp, #0] 8014c38: 4613 mov r3, r2 8014c3a: 687a ldr r2, [r7, #4] 8014c3c: 68b9 ldr r1, [r7, #8] 8014c3e: 68f8 ldr r0, [r7, #12] 8014c40: f000 f840 bl 8014cc4 { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 8014c44: 6afb ldr r3, [r7, #44] @ 0x2c } 8014c46: 4618 mov r0, r3 8014c48: 3730 adds r7, #48 @ 0x30 8014c4a: 46bd mov sp, r7 8014c4c: bd80 pop {r7, pc} 08014c4e : /*-----------------------------------------------------------*/ #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) { 8014c4e: b580 push {r7, lr} 8014c50: b08a sub sp, #40 @ 0x28 8014c52: af02 add r7, sp, #8 8014c54: 60f8 str r0, [r7, #12] 8014c56: 60b9 str r1, [r7, #8] 8014c58: 4613 mov r3, r2 8014c5a: 71fb strb r3, [r7, #7] Queue_t *pxNewQueue; size_t xQueueSizeInBytes; uint8_t *pucQueueStorage; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 8014c5c: 68fb ldr r3, [r7, #12] 8014c5e: 2b00 cmp r3, #0 8014c60: d10b bne.n 8014c7a __asm volatile 8014c62: f04f 0350 mov.w r3, #80 @ 0x50 8014c66: f383 8811 msr BASEPRI, r3 8014c6a: f3bf 8f6f isb sy 8014c6e: f3bf 8f4f dsb sy 8014c72: 613b str r3, [r7, #16] } 8014c74: bf00 nop 8014c76: bf00 nop 8014c78: e7fd b.n 8014c76 /* Allocate enough space to hold the maximum number of items that can be in the queue at any time. It is valid for uxItemSize to be zero in the case the queue is used as a semaphore. */ xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8014c7a: 68fb ldr r3, [r7, #12] 8014c7c: 68ba ldr r2, [r7, #8] 8014c7e: fb02 f303 mul.w r3, r2, r3 8014c82: 61fb str r3, [r7, #28] alignment requirements of the Queue_t structure - which in this case is an int8_t *. Therefore, whenever the stack alignment requirements are greater than or equal to the pointer to char requirements the cast is safe. In other cases alignment requirements are not strict (one or two bytes). */ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ 8014c84: 69fb ldr r3, [r7, #28] 8014c86: 3350 adds r3, #80 @ 0x50 8014c88: 4618 mov r0, r3 8014c8a: f003 f997 bl 8017fbc 8014c8e: 61b8 str r0, [r7, #24] if( pxNewQueue != NULL ) 8014c90: 69bb ldr r3, [r7, #24] 8014c92: 2b00 cmp r3, #0 8014c94: d011 beq.n 8014cba { /* Jump past the queue structure to find the location of the queue storage area. */ pucQueueStorage = ( uint8_t * ) pxNewQueue; 8014c96: 69bb ldr r3, [r7, #24] 8014c98: 617b str r3, [r7, #20] pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8014c9a: 697b ldr r3, [r7, #20] 8014c9c: 3350 adds r3, #80 @ 0x50 8014c9e: 617b str r3, [r7, #20] #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { /* Queues can be created either statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdFALSE; 8014ca0: 69bb ldr r3, [r7, #24] 8014ca2: 2200 movs r2, #0 8014ca4: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_STATIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8014ca8: 79fa ldrb r2, [r7, #7] 8014caa: 69bb ldr r3, [r7, #24] 8014cac: 9300 str r3, [sp, #0] 8014cae: 4613 mov r3, r2 8014cb0: 697a ldr r2, [r7, #20] 8014cb2: 68b9 ldr r1, [r7, #8] 8014cb4: 68f8 ldr r0, [r7, #12] 8014cb6: f000 f805 bl 8014cc4 { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 8014cba: 69bb ldr r3, [r7, #24] } 8014cbc: 4618 mov r0, r3 8014cbe: 3720 adds r7, #32 8014cc0: 46bd mov sp, r7 8014cc2: bd80 pop {r7, pc} 08014cc4 : #endif /* configSUPPORT_STATIC_ALLOCATION */ /*-----------------------------------------------------------*/ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) { 8014cc4: b580 push {r7, lr} 8014cc6: b084 sub sp, #16 8014cc8: af00 add r7, sp, #0 8014cca: 60f8 str r0, [r7, #12] 8014ccc: 60b9 str r1, [r7, #8] 8014cce: 607a str r2, [r7, #4] 8014cd0: 70fb strb r3, [r7, #3] /* Remove compiler warnings about unused parameters should configUSE_TRACE_FACILITY not be set to 1. */ ( void ) ucQueueType; if( uxItemSize == ( UBaseType_t ) 0 ) 8014cd2: 68bb ldr r3, [r7, #8] 8014cd4: 2b00 cmp r3, #0 8014cd6: d103 bne.n 8014ce0 { /* No RAM was allocated for the queue storage area, but PC head cannot be set to NULL because NULL is used as a key to say the queue is used as a mutex. Therefore just set pcHead to point to the queue as a benign value that is known to be within the memory map. */ pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; 8014cd8: 69bb ldr r3, [r7, #24] 8014cda: 69ba ldr r2, [r7, #24] 8014cdc: 601a str r2, [r3, #0] 8014cde: e002 b.n 8014ce6 } else { /* Set the head to the start of the queue storage area. */ pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; 8014ce0: 69bb ldr r3, [r7, #24] 8014ce2: 687a ldr r2, [r7, #4] 8014ce4: 601a str r2, [r3, #0] } /* Initialise the queue members as described where the queue type is defined. */ pxNewQueue->uxLength = uxQueueLength; 8014ce6: 69bb ldr r3, [r7, #24] 8014ce8: 68fa ldr r2, [r7, #12] 8014cea: 63da str r2, [r3, #60] @ 0x3c pxNewQueue->uxItemSize = uxItemSize; 8014cec: 69bb ldr r3, [r7, #24] 8014cee: 68ba ldr r2, [r7, #8] 8014cf0: 641a str r2, [r3, #64] @ 0x40 ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); 8014cf2: 2101 movs r1, #1 8014cf4: 69b8 ldr r0, [r7, #24] 8014cf6: f7ff fec3 bl 8014a80 #if ( configUSE_TRACE_FACILITY == 1 ) { pxNewQueue->ucQueueType = ucQueueType; 8014cfa: 69bb ldr r3, [r7, #24] 8014cfc: 78fa ldrb r2, [r7, #3] 8014cfe: f883 204c strb.w r2, [r3, #76] @ 0x4c pxNewQueue->pxQueueSetContainer = NULL; } #endif /* configUSE_QUEUE_SETS */ traceQUEUE_CREATE( pxNewQueue ); } 8014d02: bf00 nop 8014d04: 3710 adds r7, #16 8014d06: 46bd mov sp, r7 8014d08: bd80 pop {r7, pc} 08014d0a : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static void prvInitialiseMutex( Queue_t *pxNewQueue ) { 8014d0a: b580 push {r7, lr} 8014d0c: b082 sub sp, #8 8014d0e: af00 add r7, sp, #0 8014d10: 6078 str r0, [r7, #4] if( pxNewQueue != NULL ) 8014d12: 687b ldr r3, [r7, #4] 8014d14: 2b00 cmp r3, #0 8014d16: d00e beq.n 8014d36 { /* The queue create function will set all the queue structure members correctly for a generic queue, but this function is creating a mutex. Overwrite those members that need to be set differently - in particular the information required for priority inheritance. */ pxNewQueue->u.xSemaphore.xMutexHolder = NULL; 8014d18: 687b ldr r3, [r7, #4] 8014d1a: 2200 movs r2, #0 8014d1c: 609a str r2, [r3, #8] pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; 8014d1e: 687b ldr r3, [r7, #4] 8014d20: 2200 movs r2, #0 8014d22: 601a str r2, [r3, #0] /* In case this is a recursive mutex. */ pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; 8014d24: 687b ldr r3, [r7, #4] 8014d26: 2200 movs r2, #0 8014d28: 60da str r2, [r3, #12] traceCREATE_MUTEX( pxNewQueue ); /* Start with the semaphore in the expected state. */ ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); 8014d2a: 2300 movs r3, #0 8014d2c: 2200 movs r2, #0 8014d2e: 2100 movs r1, #0 8014d30: 6878 ldr r0, [r7, #4] 8014d32: f000 f8a3 bl 8014e7c } else { traceCREATE_MUTEX_FAILED(); } } 8014d36: bf00 nop 8014d38: 3708 adds r7, #8 8014d3a: 46bd mov sp, r7 8014d3c: bd80 pop {r7, pc} 08014d3e : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) { 8014d3e: b580 push {r7, lr} 8014d40: b086 sub sp, #24 8014d42: af00 add r7, sp, #0 8014d44: 4603 mov r3, r0 8014d46: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8014d48: 2301 movs r3, #1 8014d4a: 617b str r3, [r7, #20] 8014d4c: 2300 movs r3, #0 8014d4e: 613b str r3, [r7, #16] xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); 8014d50: 79fb ldrb r3, [r7, #7] 8014d52: 461a mov r2, r3 8014d54: 6939 ldr r1, [r7, #16] 8014d56: 6978 ldr r0, [r7, #20] 8014d58: f7ff ff79 bl 8014c4e 8014d5c: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 8014d5e: 68f8 ldr r0, [r7, #12] 8014d60: f7ff ffd3 bl 8014d0a return xNewQueue; 8014d64: 68fb ldr r3, [r7, #12] } 8014d66: 4618 mov r0, r3 8014d68: 3718 adds r7, #24 8014d6a: 46bd mov sp, r7 8014d6c: bd80 pop {r7, pc} 08014d6e : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) { 8014d6e: b580 push {r7, lr} 8014d70: b088 sub sp, #32 8014d72: af02 add r7, sp, #8 8014d74: 4603 mov r3, r0 8014d76: 6039 str r1, [r7, #0] 8014d78: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8014d7a: 2301 movs r3, #1 8014d7c: 617b str r3, [r7, #20] 8014d7e: 2300 movs r3, #0 8014d80: 613b str r3, [r7, #16] /* Prevent compiler warnings about unused parameters if configUSE_TRACE_FACILITY does not equal 1. */ ( void ) ucQueueType; xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); 8014d82: 79fb ldrb r3, [r7, #7] 8014d84: 9300 str r3, [sp, #0] 8014d86: 683b ldr r3, [r7, #0] 8014d88: 2200 movs r2, #0 8014d8a: 6939 ldr r1, [r7, #16] 8014d8c: 6978 ldr r0, [r7, #20] 8014d8e: f7ff fee1 bl 8014b54 8014d92: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 8014d94: 68f8 ldr r0, [r7, #12] 8014d96: f7ff ffb8 bl 8014d0a return xNewQueue; 8014d9a: 68fb ldr r3, [r7, #12] } 8014d9c: 4618 mov r0, r3 8014d9e: 3718 adds r7, #24 8014da0: 46bd mov sp, r7 8014da2: bd80 pop {r7, pc} 08014da4 : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) { 8014da4: b590 push {r4, r7, lr} 8014da6: b087 sub sp, #28 8014da8: af00 add r7, sp, #0 8014daa: 6078 str r0, [r7, #4] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8014dac: 687b ldr r3, [r7, #4] 8014dae: 613b str r3, [r7, #16] configASSERT( pxMutex ); 8014db0: 693b ldr r3, [r7, #16] 8014db2: 2b00 cmp r3, #0 8014db4: d10b bne.n 8014dce __asm volatile 8014db6: f04f 0350 mov.w r3, #80 @ 0x50 8014dba: f383 8811 msr BASEPRI, r3 8014dbe: f3bf 8f6f isb sy 8014dc2: f3bf 8f4f dsb sy 8014dc6: 60fb str r3, [r7, #12] } 8014dc8: bf00 nop 8014dca: bf00 nop 8014dcc: e7fd b.n 8014dca change outside of this task. If this task does not hold the mutex then pxMutexHolder can never coincidentally equal the tasks handle, and as this is the only condition we are interested in it does not matter if pxMutexHolder is accessed simultaneously by another task. Therefore no mutual exclusion is required to test the pxMutexHolder variable. */ if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 8014dce: 693b ldr r3, [r7, #16] 8014dd0: 689c ldr r4, [r3, #8] 8014dd2: f001 fe39 bl 8016a48 8014dd6: 4603 mov r3, r0 8014dd8: 429c cmp r4, r3 8014dda: d111 bne.n 8014e00 /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to the task handle, therefore no underflow check is required. Also, uxRecursiveCallCount is only modified by the mutex holder, and as there can only be one, no mutual exclusion is required to modify the uxRecursiveCallCount member. */ ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; 8014ddc: 693b ldr r3, [r7, #16] 8014dde: 68db ldr r3, [r3, #12] 8014de0: 1e5a subs r2, r3, #1 8014de2: 693b ldr r3, [r7, #16] 8014de4: 60da str r2, [r3, #12] /* Has the recursive call count unwound to 0? */ if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) 8014de6: 693b ldr r3, [r7, #16] 8014de8: 68db ldr r3, [r3, #12] 8014dea: 2b00 cmp r3, #0 8014dec: d105 bne.n 8014dfa { /* Return the mutex. This will automatically unblock any other task that might be waiting to access the mutex. */ ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); 8014dee: 2300 movs r3, #0 8014df0: 2200 movs r2, #0 8014df2: 2100 movs r1, #0 8014df4: 6938 ldr r0, [r7, #16] 8014df6: f000 f841 bl 8014e7c else { mtCOVERAGE_TEST_MARKER(); } xReturn = pdPASS; 8014dfa: 2301 movs r3, #1 8014dfc: 617b str r3, [r7, #20] 8014dfe: e001 b.n 8014e04 } else { /* The mutex cannot be given because the calling task is not the holder. */ xReturn = pdFAIL; 8014e00: 2300 movs r3, #0 8014e02: 617b str r3, [r7, #20] traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); } return xReturn; 8014e04: 697b ldr r3, [r7, #20] } 8014e06: 4618 mov r0, r3 8014e08: 371c adds r7, #28 8014e0a: 46bd mov sp, r7 8014e0c: bd90 pop {r4, r7, pc} 08014e0e : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) { 8014e0e: b590 push {r4, r7, lr} 8014e10: b087 sub sp, #28 8014e12: af00 add r7, sp, #0 8014e14: 6078 str r0, [r7, #4] 8014e16: 6039 str r1, [r7, #0] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8014e18: 687b ldr r3, [r7, #4] 8014e1a: 613b str r3, [r7, #16] configASSERT( pxMutex ); 8014e1c: 693b ldr r3, [r7, #16] 8014e1e: 2b00 cmp r3, #0 8014e20: d10b bne.n 8014e3a __asm volatile 8014e22: f04f 0350 mov.w r3, #80 @ 0x50 8014e26: f383 8811 msr BASEPRI, r3 8014e2a: f3bf 8f6f isb sy 8014e2e: f3bf 8f4f dsb sy 8014e32: 60fb str r3, [r7, #12] } 8014e34: bf00 nop 8014e36: bf00 nop 8014e38: e7fd b.n 8014e36 /* Comments regarding mutual exclusion as per those within xQueueGiveMutexRecursive(). */ traceTAKE_MUTEX_RECURSIVE( pxMutex ); if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 8014e3a: 693b ldr r3, [r7, #16] 8014e3c: 689c ldr r4, [r3, #8] 8014e3e: f001 fe03 bl 8016a48 8014e42: 4603 mov r3, r0 8014e44: 429c cmp r4, r3 8014e46: d107 bne.n 8014e58 { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 8014e48: 693b ldr r3, [r7, #16] 8014e4a: 68db ldr r3, [r3, #12] 8014e4c: 1c5a adds r2, r3, #1 8014e4e: 693b ldr r3, [r7, #16] 8014e50: 60da str r2, [r3, #12] xReturn = pdPASS; 8014e52: 2301 movs r3, #1 8014e54: 617b str r3, [r7, #20] 8014e56: e00c b.n 8014e72 } else { xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait ); 8014e58: 6839 ldr r1, [r7, #0] 8014e5a: 6938 ldr r0, [r7, #16] 8014e5c: f000 fa90 bl 8015380 8014e60: 6178 str r0, [r7, #20] /* pdPASS will only be returned if the mutex was successfully obtained. The calling task may have entered the Blocked state before reaching here. */ if( xReturn != pdFAIL ) 8014e62: 697b ldr r3, [r7, #20] 8014e64: 2b00 cmp r3, #0 8014e66: d004 beq.n 8014e72 { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 8014e68: 693b ldr r3, [r7, #16] 8014e6a: 68db ldr r3, [r3, #12] 8014e6c: 1c5a adds r2, r3, #1 8014e6e: 693b ldr r3, [r7, #16] 8014e70: 60da str r2, [r3, #12] { traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ); } } return xReturn; 8014e72: 697b ldr r3, [r7, #20] } 8014e74: 4618 mov r0, r3 8014e76: 371c adds r7, #28 8014e78: 46bd mov sp, r7 8014e7a: bd90 pop {r4, r7, pc} 08014e7c : #endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) { 8014e7c: b580 push {r7, lr} 8014e7e: b08e sub sp, #56 @ 0x38 8014e80: af00 add r7, sp, #0 8014e82: 60f8 str r0, [r7, #12] 8014e84: 60b9 str r1, [r7, #8] 8014e86: 607a str r2, [r7, #4] 8014e88: 603b str r3, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; 8014e8a: 2300 movs r3, #0 8014e8c: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8014e8e: 68fb ldr r3, [r7, #12] 8014e90: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 8014e92: 6b3b ldr r3, [r7, #48] @ 0x30 8014e94: 2b00 cmp r3, #0 8014e96: d10b bne.n 8014eb0 __asm volatile 8014e98: f04f 0350 mov.w r3, #80 @ 0x50 8014e9c: f383 8811 msr BASEPRI, r3 8014ea0: f3bf 8f6f isb sy 8014ea4: f3bf 8f4f dsb sy 8014ea8: 62bb str r3, [r7, #40] @ 0x28 } 8014eaa: bf00 nop 8014eac: bf00 nop 8014eae: e7fd b.n 8014eac configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8014eb0: 68bb ldr r3, [r7, #8] 8014eb2: 2b00 cmp r3, #0 8014eb4: d103 bne.n 8014ebe 8014eb6: 6b3b ldr r3, [r7, #48] @ 0x30 8014eb8: 6c1b ldr r3, [r3, #64] @ 0x40 8014eba: 2b00 cmp r3, #0 8014ebc: d101 bne.n 8014ec2 8014ebe: 2301 movs r3, #1 8014ec0: e000 b.n 8014ec4 8014ec2: 2300 movs r3, #0 8014ec4: 2b00 cmp r3, #0 8014ec6: d10b bne.n 8014ee0 __asm volatile 8014ec8: f04f 0350 mov.w r3, #80 @ 0x50 8014ecc: f383 8811 msr BASEPRI, r3 8014ed0: f3bf 8f6f isb sy 8014ed4: f3bf 8f4f dsb sy 8014ed8: 627b str r3, [r7, #36] @ 0x24 } 8014eda: bf00 nop 8014edc: bf00 nop 8014ede: e7fd b.n 8014edc configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8014ee0: 683b ldr r3, [r7, #0] 8014ee2: 2b02 cmp r3, #2 8014ee4: d103 bne.n 8014eee 8014ee6: 6b3b ldr r3, [r7, #48] @ 0x30 8014ee8: 6bdb ldr r3, [r3, #60] @ 0x3c 8014eea: 2b01 cmp r3, #1 8014eec: d101 bne.n 8014ef2 8014eee: 2301 movs r3, #1 8014ef0: e000 b.n 8014ef4 8014ef2: 2300 movs r3, #0 8014ef4: 2b00 cmp r3, #0 8014ef6: d10b bne.n 8014f10 __asm volatile 8014ef8: f04f 0350 mov.w r3, #80 @ 0x50 8014efc: f383 8811 msr BASEPRI, r3 8014f00: f3bf 8f6f isb sy 8014f04: f3bf 8f4f dsb sy 8014f08: 623b str r3, [r7, #32] } 8014f0a: bf00 nop 8014f0c: bf00 nop 8014f0e: e7fd b.n 8014f0c #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8014f10: f001 fdaa bl 8016a68 8014f14: 4603 mov r3, r0 8014f16: 2b00 cmp r3, #0 8014f18: d102 bne.n 8014f20 8014f1a: 687b ldr r3, [r7, #4] 8014f1c: 2b00 cmp r3, #0 8014f1e: d101 bne.n 8014f24 8014f20: 2301 movs r3, #1 8014f22: e000 b.n 8014f26 8014f24: 2300 movs r3, #0 8014f26: 2b00 cmp r3, #0 8014f28: d10b bne.n 8014f42 __asm volatile 8014f2a: f04f 0350 mov.w r3, #80 @ 0x50 8014f2e: f383 8811 msr BASEPRI, r3 8014f32: f3bf 8f6f isb sy 8014f36: f3bf 8f4f dsb sy 8014f3a: 61fb str r3, [r7, #28] } 8014f3c: bf00 nop 8014f3e: bf00 nop 8014f40: e7fd b.n 8014f3e /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 8014f42: f002 ff19 bl 8017d78 { /* Is there room on the queue now? The running task must be the highest priority task wanting to access the queue. If the head item in the queue is to be overwritten then it does not matter if the queue is full. */ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 8014f46: 6b3b ldr r3, [r7, #48] @ 0x30 8014f48: 6b9a ldr r2, [r3, #56] @ 0x38 8014f4a: 6b3b ldr r3, [r7, #48] @ 0x30 8014f4c: 6bdb ldr r3, [r3, #60] @ 0x3c 8014f4e: 429a cmp r2, r3 8014f50: d302 bcc.n 8014f58 8014f52: 683b ldr r3, [r7, #0] 8014f54: 2b02 cmp r3, #2 8014f56: d129 bne.n 8014fac } } } #else /* configUSE_QUEUE_SETS */ { xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 8014f58: 683a ldr r2, [r7, #0] 8014f5a: 68b9 ldr r1, [r7, #8] 8014f5c: 6b38 ldr r0, [r7, #48] @ 0x30 8014f5e: f000 fbb9 bl 80156d4 8014f62: 62f8 str r0, [r7, #44] @ 0x2c /* If there was a task waiting for data to arrive on the queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8014f64: 6b3b ldr r3, [r7, #48] @ 0x30 8014f66: 6a5b ldr r3, [r3, #36] @ 0x24 8014f68: 2b00 cmp r3, #0 8014f6a: d010 beq.n 8014f8e { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8014f6c: 6b3b ldr r3, [r7, #48] @ 0x30 8014f6e: 3324 adds r3, #36 @ 0x24 8014f70: 4618 mov r0, r3 8014f72: f001 fb7b bl 801666c 8014f76: 4603 mov r3, r0 8014f78: 2b00 cmp r3, #0 8014f7a: d013 beq.n 8014fa4 { /* The unblocked task has a priority higher than our own so yield immediately. Yes it is ok to do this from within the critical section - the kernel takes care of that. */ queueYIELD_IF_USING_PREEMPTION(); 8014f7c: 4b3f ldr r3, [pc, #252] @ (801507c ) 8014f7e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014f82: 601a str r2, [r3, #0] 8014f84: f3bf 8f4f dsb sy 8014f88: f3bf 8f6f isb sy 8014f8c: e00a b.n 8014fa4 else { mtCOVERAGE_TEST_MARKER(); } } else if( xYieldRequired != pdFALSE ) 8014f8e: 6afb ldr r3, [r7, #44] @ 0x2c 8014f90: 2b00 cmp r3, #0 8014f92: d007 beq.n 8014fa4 { /* This path is a special case that will only get executed if the task was holding multiple mutexes and the mutexes were given back in an order that is different to that in which they were taken. */ queueYIELD_IF_USING_PREEMPTION(); 8014f94: 4b39 ldr r3, [pc, #228] @ (801507c ) 8014f96: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014f9a: 601a str r2, [r3, #0] 8014f9c: f3bf 8f4f dsb sy 8014fa0: f3bf 8f6f isb sy mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); 8014fa4: f002 ff1a bl 8017ddc return pdPASS; 8014fa8: 2301 movs r3, #1 8014faa: e063 b.n 8015074 } else { if( xTicksToWait == ( TickType_t ) 0 ) 8014fac: 687b ldr r3, [r7, #4] 8014fae: 2b00 cmp r3, #0 8014fb0: d103 bne.n 8014fba { /* The queue was full and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 8014fb2: f002 ff13 bl 8017ddc /* Return to the original privilege level before exiting the function. */ traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 8014fb6: 2300 movs r3, #0 8014fb8: e05c b.n 8015074 } else if( xEntryTimeSet == pdFALSE ) 8014fba: 6b7b ldr r3, [r7, #52] @ 0x34 8014fbc: 2b00 cmp r3, #0 8014fbe: d106 bne.n 8014fce { /* The queue was full and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8014fc0: f107 0314 add.w r3, r7, #20 8014fc4: 4618 mov r0, r3 8014fc6: f001 fbdd bl 8016784 xEntryTimeSet = pdTRUE; 8014fca: 2301 movs r3, #1 8014fcc: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8014fce: f002 ff05 bl 8017ddc /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 8014fd2: f001 f90f bl 80161f4 prvLockQueue( pxQueue ); 8014fd6: f002 fecf bl 8017d78 8014fda: 6b3b ldr r3, [r7, #48] @ 0x30 8014fdc: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014fe0: b25b sxtb r3, r3 8014fe2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014fe6: d103 bne.n 8014ff0 8014fe8: 6b3b ldr r3, [r7, #48] @ 0x30 8014fea: 2200 movs r2, #0 8014fec: f883 2044 strb.w r2, [r3, #68] @ 0x44 8014ff0: 6b3b ldr r3, [r7, #48] @ 0x30 8014ff2: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014ff6: b25b sxtb r3, r3 8014ff8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014ffc: d103 bne.n 8015006 8014ffe: 6b3b ldr r3, [r7, #48] @ 0x30 8015000: 2200 movs r2, #0 8015002: f883 2045 strb.w r2, [r3, #69] @ 0x45 8015006: f002 fee9 bl 8017ddc /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 801500a: 1d3a adds r2, r7, #4 801500c: f107 0314 add.w r3, r7, #20 8015010: 4611 mov r1, r2 8015012: 4618 mov r0, r3 8015014: f001 fbcc bl 80167b0 8015018: 4603 mov r3, r0 801501a: 2b00 cmp r3, #0 801501c: d124 bne.n 8015068 { if( prvIsQueueFull( pxQueue ) != pdFALSE ) 801501e: 6b38 ldr r0, [r7, #48] @ 0x30 8015020: f000 fc50 bl 80158c4 8015024: 4603 mov r3, r0 8015026: 2b00 cmp r3, #0 8015028: d018 beq.n 801505c { traceBLOCKING_ON_QUEUE_SEND( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); 801502a: 6b3b ldr r3, [r7, #48] @ 0x30 801502c: 3310 adds r3, #16 801502e: 687a ldr r2, [r7, #4] 8015030: 4611 mov r1, r2 8015032: 4618 mov r0, r3 8015034: f001 fac8 bl 80165c8 /* Unlocking the queue means queue events can effect the event list. It is possible that interrupts occurring now remove this task from the event list again - but as the scheduler is suspended the task will go onto the pending ready last instead of the actual ready list. */ prvUnlockQueue( pxQueue ); 8015038: 6b38 ldr r0, [r7, #48] @ 0x30 801503a: f000 fbdb bl 80157f4 /* Resuming the scheduler will move tasks from the pending ready list into the ready list - so it is feasible that this task is already in a ready list before it yields - in which case the yield will not cause a context switch unless there is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) 801503e: f001 f8e7 bl 8016210 8015042: 4603 mov r3, r0 8015044: 2b00 cmp r3, #0 8015046: f47f af7c bne.w 8014f42 { portYIELD_WITHIN_API(); 801504a: 4b0c ldr r3, [pc, #48] @ (801507c ) 801504c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015050: 601a str r2, [r3, #0] 8015052: f3bf 8f4f dsb sy 8015056: f3bf 8f6f isb sy 801505a: e772 b.n 8014f42 } } else { /* Try again. */ prvUnlockQueue( pxQueue ); 801505c: 6b38 ldr r0, [r7, #48] @ 0x30 801505e: f000 fbc9 bl 80157f4 ( void ) xTaskResumeAll(); 8015062: f001 f8d5 bl 8016210 8015066: e76c b.n 8014f42 } } else { /* The timeout has expired. */ prvUnlockQueue( pxQueue ); 8015068: 6b38 ldr r0, [r7, #48] @ 0x30 801506a: f000 fbc3 bl 80157f4 ( void ) xTaskResumeAll(); 801506e: f001 f8cf bl 8016210 traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 8015072: 2300 movs r3, #0 } } /*lint -restore */ } 8015074: 4618 mov r0, r3 8015076: 3738 adds r7, #56 @ 0x38 8015078: 46bd mov sp, r7 801507a: bd80 pop {r7, pc} 801507c: e000ed04 .word 0xe000ed04 08015080 : /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) { 8015080: b580 push {r7, lr} 8015082: b090 sub sp, #64 @ 0x40 8015084: af00 add r7, sp, #0 8015086: 60f8 str r0, [r7, #12] 8015088: 60b9 str r1, [r7, #8] 801508a: 607a str r2, [r7, #4] 801508c: 603b str r3, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 801508e: 68fb ldr r3, [r7, #12] 8015090: 63bb str r3, [r7, #56] @ 0x38 configASSERT( pxQueue ); 8015092: 6bbb ldr r3, [r7, #56] @ 0x38 8015094: 2b00 cmp r3, #0 8015096: d10b bne.n 80150b0 __asm volatile 8015098: f04f 0350 mov.w r3, #80 @ 0x50 801509c: f383 8811 msr BASEPRI, r3 80150a0: f3bf 8f6f isb sy 80150a4: f3bf 8f4f dsb sy 80150a8: 62bb str r3, [r7, #40] @ 0x28 } 80150aa: bf00 nop 80150ac: bf00 nop 80150ae: e7fd b.n 80150ac configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 80150b0: 68bb ldr r3, [r7, #8] 80150b2: 2b00 cmp r3, #0 80150b4: d103 bne.n 80150be 80150b6: 6bbb ldr r3, [r7, #56] @ 0x38 80150b8: 6c1b ldr r3, [r3, #64] @ 0x40 80150ba: 2b00 cmp r3, #0 80150bc: d101 bne.n 80150c2 80150be: 2301 movs r3, #1 80150c0: e000 b.n 80150c4 80150c2: 2300 movs r3, #0 80150c4: 2b00 cmp r3, #0 80150c6: d10b bne.n 80150e0 __asm volatile 80150c8: f04f 0350 mov.w r3, #80 @ 0x50 80150cc: f383 8811 msr BASEPRI, r3 80150d0: f3bf 8f6f isb sy 80150d4: f3bf 8f4f dsb sy 80150d8: 627b str r3, [r7, #36] @ 0x24 } 80150da: bf00 nop 80150dc: bf00 nop 80150de: e7fd b.n 80150dc configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 80150e0: 683b ldr r3, [r7, #0] 80150e2: 2b02 cmp r3, #2 80150e4: d103 bne.n 80150ee 80150e6: 6bbb ldr r3, [r7, #56] @ 0x38 80150e8: 6bdb ldr r3, [r3, #60] @ 0x3c 80150ea: 2b01 cmp r3, #1 80150ec: d101 bne.n 80150f2 80150ee: 2301 movs r3, #1 80150f0: e000 b.n 80150f4 80150f2: 2300 movs r3, #0 80150f4: 2b00 cmp r3, #0 80150f6: d10b bne.n 8015110 __asm volatile 80150f8: f04f 0350 mov.w r3, #80 @ 0x50 80150fc: f383 8811 msr BASEPRI, r3 8015100: f3bf 8f6f isb sy 8015104: f3bf 8f4f dsb sy 8015108: 623b str r3, [r7, #32] } 801510a: bf00 nop 801510c: bf00 nop 801510e: e7fd b.n 801510c that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8015110: f002 ff12 bl 8017f38 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile 8015114: f3ef 8211 mrs r2, BASEPRI 8015118: f04f 0350 mov.w r3, #80 @ 0x50 801511c: f383 8811 msr BASEPRI, r3 8015120: f3bf 8f6f isb sy 8015124: f3bf 8f4f dsb sy 8015128: 61fa str r2, [r7, #28] 801512a: 61bb str r3, [r7, #24] :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; 801512c: 69fb ldr r3, [r7, #28] /* Similar to xQueueGenericSend, except without blocking if there is no room in the queue. Also don't directly wake a task that was blocked on a queue read, instead return a flag to say whether a context switch is required or not (i.e. has a task with a higher priority than us been woken by this post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 801512e: 637b str r3, [r7, #52] @ 0x34 { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 8015130: 6bbb ldr r3, [r7, #56] @ 0x38 8015132: 6b9a ldr r2, [r3, #56] @ 0x38 8015134: 6bbb ldr r3, [r7, #56] @ 0x38 8015136: 6bdb ldr r3, [r3, #60] @ 0x3c 8015138: 429a cmp r2, r3 801513a: d302 bcc.n 8015142 801513c: 683b ldr r3, [r7, #0] 801513e: 2b02 cmp r3, #2 8015140: d12f bne.n 80151a2 { const int8_t cTxLock = pxQueue->cTxLock; 8015142: 6bbb ldr r3, [r7, #56] @ 0x38 8015144: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8015148: f887 3033 strb.w r3, [r7, #51] @ 0x33 const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; 801514c: 6bbb ldr r3, [r7, #56] @ 0x38 801514e: 6b9b ldr r3, [r3, #56] @ 0x38 8015150: 62fb str r3, [r7, #44] @ 0x2c /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a semaphore or mutex. That means prvCopyDataToQueue() cannot result in a task disinheriting a priority and prvCopyDataToQueue() can be called here even though the disinherit function does not check if the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 8015152: 683a ldr r2, [r7, #0] 8015154: 68b9 ldr r1, [r7, #8] 8015156: 6bb8 ldr r0, [r7, #56] @ 0x38 8015158: f000 fabc bl 80156d4 /* The event list is not altered if the queue is locked. This will be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 801515c: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33 8015160: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015164: d112 bne.n 801518c } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8015166: 6bbb ldr r3, [r7, #56] @ 0x38 8015168: 6a5b ldr r3, [r3, #36] @ 0x24 801516a: 2b00 cmp r3, #0 801516c: d016 beq.n 801519c { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 801516e: 6bbb ldr r3, [r7, #56] @ 0x38 8015170: 3324 adds r3, #36 @ 0x24 8015172: 4618 mov r0, r3 8015174: f001 fa7a bl 801666c 8015178: 4603 mov r3, r0 801517a: 2b00 cmp r3, #0 801517c: d00e beq.n 801519c { /* The task waiting has a higher priority so record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 801517e: 687b ldr r3, [r7, #4] 8015180: 2b00 cmp r3, #0 8015182: d00b beq.n 801519c { *pxHigherPriorityTaskWoken = pdTRUE; 8015184: 687b ldr r3, [r7, #4] 8015186: 2201 movs r2, #1 8015188: 601a str r2, [r3, #0] 801518a: e007 b.n 801519c } else { /* Increment the lock count so the task that unlocks the queue knows that data was posted while it was locked. */ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); 801518c: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 8015190: 3301 adds r3, #1 8015192: b2db uxtb r3, r3 8015194: b25a sxtb r2, r3 8015196: 6bbb ldr r3, [r7, #56] @ 0x38 8015198: f883 2045 strb.w r2, [r3, #69] @ 0x45 } xReturn = pdPASS; 801519c: 2301 movs r3, #1 801519e: 63fb str r3, [r7, #60] @ 0x3c { 80151a0: e001 b.n 80151a6 } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 80151a2: 2300 movs r3, #0 80151a4: 63fb str r3, [r7, #60] @ 0x3c 80151a6: 6b7b ldr r3, [r7, #52] @ 0x34 80151a8: 617b str r3, [r7, #20] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile 80151aa: 697b ldr r3, [r7, #20] 80151ac: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } 80151b0: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 80151b2: 6bfb ldr r3, [r7, #60] @ 0x3c } 80151b4: 4618 mov r0, r3 80151b6: 3740 adds r7, #64 @ 0x40 80151b8: 46bd mov sp, r7 80151ba: bd80 pop {r7, pc} 080151bc : return xReturn; } /*-----------------------------------------------------------*/ BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) { 80151bc: b580 push {r7, lr} 80151be: b08c sub sp, #48 @ 0x30 80151c0: af00 add r7, sp, #0 80151c2: 60f8 str r0, [r7, #12] 80151c4: 60b9 str r1, [r7, #8] 80151c6: 607a str r2, [r7, #4] BaseType_t xEntryTimeSet = pdFALSE; 80151c8: 2300 movs r3, #0 80151ca: 62fb str r3, [r7, #44] @ 0x2c TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 80151cc: 68fb ldr r3, [r7, #12] 80151ce: 62bb str r3, [r7, #40] @ 0x28 /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); 80151d0: 6abb ldr r3, [r7, #40] @ 0x28 80151d2: 2b00 cmp r3, #0 80151d4: d10b bne.n 80151ee __asm volatile 80151d6: f04f 0350 mov.w r3, #80 @ 0x50 80151da: f383 8811 msr BASEPRI, r3 80151de: f3bf 8f6f isb sy 80151e2: f3bf 8f4f dsb sy 80151e6: 623b str r3, [r7, #32] } 80151e8: bf00 nop 80151ea: bf00 nop 80151ec: e7fd b.n 80151ea /* The buffer into which data is received can only be NULL if the data size is zero (so no data is copied into the buffer. */ configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); 80151ee: 68bb ldr r3, [r7, #8] 80151f0: 2b00 cmp r3, #0 80151f2: d103 bne.n 80151fc 80151f4: 6abb ldr r3, [r7, #40] @ 0x28 80151f6: 6c1b ldr r3, [r3, #64] @ 0x40 80151f8: 2b00 cmp r3, #0 80151fa: d101 bne.n 8015200 80151fc: 2301 movs r3, #1 80151fe: e000 b.n 8015202 8015200: 2300 movs r3, #0 8015202: 2b00 cmp r3, #0 8015204: d10b bne.n 801521e __asm volatile 8015206: f04f 0350 mov.w r3, #80 @ 0x50 801520a: f383 8811 msr BASEPRI, r3 801520e: f3bf 8f6f isb sy 8015212: f3bf 8f4f dsb sy 8015216: 61fb str r3, [r7, #28] } 8015218: bf00 nop 801521a: bf00 nop 801521c: e7fd b.n 801521a /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 801521e: f001 fc23 bl 8016a68 8015222: 4603 mov r3, r0 8015224: 2b00 cmp r3, #0 8015226: d102 bne.n 801522e 8015228: 687b ldr r3, [r7, #4] 801522a: 2b00 cmp r3, #0 801522c: d101 bne.n 8015232 801522e: 2301 movs r3, #1 8015230: e000 b.n 8015234 8015232: 2300 movs r3, #0 8015234: 2b00 cmp r3, #0 8015236: d10b bne.n 8015250 __asm volatile 8015238: f04f 0350 mov.w r3, #80 @ 0x50 801523c: f383 8811 msr BASEPRI, r3 8015240: f3bf 8f6f isb sy 8015244: f3bf 8f4f dsb sy 8015248: 61bb str r3, [r7, #24] } 801524a: bf00 nop 801524c: bf00 nop 801524e: e7fd b.n 801524c /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 8015250: f002 fd92 bl 8017d78 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8015254: 6abb ldr r3, [r7, #40] @ 0x28 8015256: 6b9b ldr r3, [r3, #56] @ 0x38 8015258: 627b str r3, [r7, #36] @ 0x24 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 801525a: 6a7b ldr r3, [r7, #36] @ 0x24 801525c: 2b00 cmp r3, #0 801525e: d01f beq.n 80152a0 { /* Data available, remove one item. */ prvCopyDataFromQueue( pxQueue, pvBuffer ); 8015260: 68b9 ldr r1, [r7, #8] 8015262: 6ab8 ldr r0, [r7, #40] @ 0x28 8015264: f000 faa0 bl 80157a8 traceQUEUE_RECEIVE( pxQueue ); pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 8015268: 6a7b ldr r3, [r7, #36] @ 0x24 801526a: 1e5a subs r2, r3, #1 801526c: 6abb ldr r3, [r7, #40] @ 0x28 801526e: 639a str r2, [r3, #56] @ 0x38 /* There is now space in the queue, were any tasks waiting to post to the queue? If so, unblock the highest priority waiting task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8015270: 6abb ldr r3, [r7, #40] @ 0x28 8015272: 691b ldr r3, [r3, #16] 8015274: 2b00 cmp r3, #0 8015276: d00f beq.n 8015298 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8015278: 6abb ldr r3, [r7, #40] @ 0x28 801527a: 3310 adds r3, #16 801527c: 4618 mov r0, r3 801527e: f001 f9f5 bl 801666c 8015282: 4603 mov r3, r0 8015284: 2b00 cmp r3, #0 8015286: d007 beq.n 8015298 { queueYIELD_IF_USING_PREEMPTION(); 8015288: 4b3c ldr r3, [pc, #240] @ (801537c ) 801528a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801528e: 601a str r2, [r3, #0] 8015290: f3bf 8f4f dsb sy 8015294: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 8015298: f002 fda0 bl 8017ddc return pdPASS; 801529c: 2301 movs r3, #1 801529e: e069 b.n 8015374 } else { if( xTicksToWait == ( TickType_t ) 0 ) 80152a0: 687b ldr r3, [r7, #4] 80152a2: 2b00 cmp r3, #0 80152a4: d103 bne.n 80152ae { /* The queue was empty and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 80152a6: f002 fd99 bl 8017ddc traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 80152aa: 2300 movs r3, #0 80152ac: e062 b.n 8015374 } else if( xEntryTimeSet == pdFALSE ) 80152ae: 6afb ldr r3, [r7, #44] @ 0x2c 80152b0: 2b00 cmp r3, #0 80152b2: d106 bne.n 80152c2 { /* The queue was empty and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 80152b4: f107 0310 add.w r3, r7, #16 80152b8: 4618 mov r0, r3 80152ba: f001 fa63 bl 8016784 xEntryTimeSet = pdTRUE; 80152be: 2301 movs r3, #1 80152c0: 62fb str r3, [r7, #44] @ 0x2c /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 80152c2: f002 fd8b bl 8017ddc /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 80152c6: f000 ff95 bl 80161f4 prvLockQueue( pxQueue ); 80152ca: f002 fd55 bl 8017d78 80152ce: 6abb ldr r3, [r7, #40] @ 0x28 80152d0: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80152d4: b25b sxtb r3, r3 80152d6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80152da: d103 bne.n 80152e4 80152dc: 6abb ldr r3, [r7, #40] @ 0x28 80152de: 2200 movs r2, #0 80152e0: f883 2044 strb.w r2, [r3, #68] @ 0x44 80152e4: 6abb ldr r3, [r7, #40] @ 0x28 80152e6: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80152ea: b25b sxtb r3, r3 80152ec: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80152f0: d103 bne.n 80152fa 80152f2: 6abb ldr r3, [r7, #40] @ 0x28 80152f4: 2200 movs r2, #0 80152f6: f883 2045 strb.w r2, [r3, #69] @ 0x45 80152fa: f002 fd6f bl 8017ddc /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 80152fe: 1d3a adds r2, r7, #4 8015300: f107 0310 add.w r3, r7, #16 8015304: 4611 mov r1, r2 8015306: 4618 mov r0, r3 8015308: f001 fa52 bl 80167b0 801530c: 4603 mov r3, r0 801530e: 2b00 cmp r3, #0 8015310: d123 bne.n 801535a { /* The timeout has not expired. If the queue is still empty place the task on the list of tasks waiting to receive from the queue. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8015312: 6ab8 ldr r0, [r7, #40] @ 0x28 8015314: f000 fac0 bl 8015898 8015318: 4603 mov r3, r0 801531a: 2b00 cmp r3, #0 801531c: d017 beq.n 801534e { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 801531e: 6abb ldr r3, [r7, #40] @ 0x28 8015320: 3324 adds r3, #36 @ 0x24 8015322: 687a ldr r2, [r7, #4] 8015324: 4611 mov r1, r2 8015326: 4618 mov r0, r3 8015328: f001 f94e bl 80165c8 prvUnlockQueue( pxQueue ); 801532c: 6ab8 ldr r0, [r7, #40] @ 0x28 801532e: f000 fa61 bl 80157f4 if( xTaskResumeAll() == pdFALSE ) 8015332: f000 ff6d bl 8016210 8015336: 4603 mov r3, r0 8015338: 2b00 cmp r3, #0 801533a: d189 bne.n 8015250 { portYIELD_WITHIN_API(); 801533c: 4b0f ldr r3, [pc, #60] @ (801537c ) 801533e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015342: 601a str r2, [r3, #0] 8015344: f3bf 8f4f dsb sy 8015348: f3bf 8f6f isb sy 801534c: e780 b.n 8015250 } else { /* The queue contains data again. Loop back to try and read the data. */ prvUnlockQueue( pxQueue ); 801534e: 6ab8 ldr r0, [r7, #40] @ 0x28 8015350: f000 fa50 bl 80157f4 ( void ) xTaskResumeAll(); 8015354: f000 ff5c bl 8016210 8015358: e77a b.n 8015250 } else { /* Timed out. If there is no data in the queue exit, otherwise loop back and attempt to read the data. */ prvUnlockQueue( pxQueue ); 801535a: 6ab8 ldr r0, [r7, #40] @ 0x28 801535c: f000 fa4a bl 80157f4 ( void ) xTaskResumeAll(); 8015360: f000 ff56 bl 8016210 if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8015364: 6ab8 ldr r0, [r7, #40] @ 0x28 8015366: f000 fa97 bl 8015898 801536a: 4603 mov r3, r0 801536c: 2b00 cmp r3, #0 801536e: f43f af6f beq.w 8015250 { traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8015372: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 8015374: 4618 mov r0, r3 8015376: 3730 adds r7, #48 @ 0x30 8015378: 46bd mov sp, r7 801537a: bd80 pop {r7, pc} 801537c: e000ed04 .word 0xe000ed04 08015380 : /*-----------------------------------------------------------*/ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) { 8015380: b580 push {r7, lr} 8015382: b08e sub sp, #56 @ 0x38 8015384: af00 add r7, sp, #0 8015386: 6078 str r0, [r7, #4] 8015388: 6039 str r1, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE; 801538a: 2300 movs r3, #0 801538c: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 801538e: 687b ldr r3, [r7, #4] 8015390: 62fb str r3, [r7, #44] @ 0x2c #if( configUSE_MUTEXES == 1 ) BaseType_t xInheritanceOccurred = pdFALSE; 8015392: 2300 movs r3, #0 8015394: 633b str r3, [r7, #48] @ 0x30 #endif /* Check the queue pointer is not NULL. */ configASSERT( ( pxQueue ) ); 8015396: 6afb ldr r3, [r7, #44] @ 0x2c 8015398: 2b00 cmp r3, #0 801539a: d10b bne.n 80153b4 __asm volatile 801539c: f04f 0350 mov.w r3, #80 @ 0x50 80153a0: f383 8811 msr BASEPRI, r3 80153a4: f3bf 8f6f isb sy 80153a8: f3bf 8f4f dsb sy 80153ac: 623b str r3, [r7, #32] } 80153ae: bf00 nop 80153b0: bf00 nop 80153b2: e7fd b.n 80153b0 /* Check this really is a semaphore, in which case the item size will be 0. */ configASSERT( pxQueue->uxItemSize == 0 ); 80153b4: 6afb ldr r3, [r7, #44] @ 0x2c 80153b6: 6c1b ldr r3, [r3, #64] @ 0x40 80153b8: 2b00 cmp r3, #0 80153ba: d00b beq.n 80153d4 __asm volatile 80153bc: f04f 0350 mov.w r3, #80 @ 0x50 80153c0: f383 8811 msr BASEPRI, r3 80153c4: f3bf 8f6f isb sy 80153c8: f3bf 8f4f dsb sy 80153cc: 61fb str r3, [r7, #28] } 80153ce: bf00 nop 80153d0: bf00 nop 80153d2: e7fd b.n 80153d0 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 80153d4: f001 fb48 bl 8016a68 80153d8: 4603 mov r3, r0 80153da: 2b00 cmp r3, #0 80153dc: d102 bne.n 80153e4 80153de: 683b ldr r3, [r7, #0] 80153e0: 2b00 cmp r3, #0 80153e2: d101 bne.n 80153e8 80153e4: 2301 movs r3, #1 80153e6: e000 b.n 80153ea 80153e8: 2300 movs r3, #0 80153ea: 2b00 cmp r3, #0 80153ec: d10b bne.n 8015406 __asm volatile 80153ee: f04f 0350 mov.w r3, #80 @ 0x50 80153f2: f383 8811 msr BASEPRI, r3 80153f6: f3bf 8f6f isb sy 80153fa: f3bf 8f4f dsb sy 80153fe: 61bb str r3, [r7, #24] } 8015400: bf00 nop 8015402: bf00 nop 8015404: e7fd b.n 8015402 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 8015406: f002 fcb7 bl 8017d78 { /* Semaphores are queues with an item size of 0, and where the number of messages in the queue is the semaphore's count value. */ const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; 801540a: 6afb ldr r3, [r7, #44] @ 0x2c 801540c: 6b9b ldr r3, [r3, #56] @ 0x38 801540e: 62bb str r3, [r7, #40] @ 0x28 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxSemaphoreCount > ( UBaseType_t ) 0 ) 8015410: 6abb ldr r3, [r7, #40] @ 0x28 8015412: 2b00 cmp r3, #0 8015414: d024 beq.n 8015460 { traceQUEUE_RECEIVE( pxQueue ); /* Semaphores are queues with a data size of zero and where the messages waiting is the semaphore's count. Reduce the count. */ pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; 8015416: 6abb ldr r3, [r7, #40] @ 0x28 8015418: 1e5a subs r2, r3, #1 801541a: 6afb ldr r3, [r7, #44] @ 0x2c 801541c: 639a str r2, [r3, #56] @ 0x38 #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 801541e: 6afb ldr r3, [r7, #44] @ 0x2c 8015420: 681b ldr r3, [r3, #0] 8015422: 2b00 cmp r3, #0 8015424: d104 bne.n 8015430 { /* Record the information required to implement priority inheritance should it become necessary. */ pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); 8015426: f001 fc99 bl 8016d5c 801542a: 4602 mov r2, r0 801542c: 6afb ldr r3, [r7, #44] @ 0x2c 801542e: 609a str r2, [r3, #8] } #endif /* configUSE_MUTEXES */ /* Check to see if other tasks are blocked waiting to give the semaphore, and if so, unblock the highest priority such task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8015430: 6afb ldr r3, [r7, #44] @ 0x2c 8015432: 691b ldr r3, [r3, #16] 8015434: 2b00 cmp r3, #0 8015436: d00f beq.n 8015458 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8015438: 6afb ldr r3, [r7, #44] @ 0x2c 801543a: 3310 adds r3, #16 801543c: 4618 mov r0, r3 801543e: f001 f915 bl 801666c 8015442: 4603 mov r3, r0 8015444: 2b00 cmp r3, #0 8015446: d007 beq.n 8015458 { queueYIELD_IF_USING_PREEMPTION(); 8015448: 4b54 ldr r3, [pc, #336] @ (801559c ) 801544a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801544e: 601a str r2, [r3, #0] 8015450: f3bf 8f4f dsb sy 8015454: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 8015458: f002 fcc0 bl 8017ddc return pdPASS; 801545c: 2301 movs r3, #1 801545e: e098 b.n 8015592 } else { if( xTicksToWait == ( TickType_t ) 0 ) 8015460: 683b ldr r3, [r7, #0] 8015462: 2b00 cmp r3, #0 8015464: d112 bne.n 801548c /* For inheritance to have occurred there must have been an initial timeout, and an adjusted timeout cannot become 0, as if it were 0 the function would have exited. */ #if( configUSE_MUTEXES == 1 ) { configASSERT( xInheritanceOccurred == pdFALSE ); 8015466: 6b3b ldr r3, [r7, #48] @ 0x30 8015468: 2b00 cmp r3, #0 801546a: d00b beq.n 8015484 __asm volatile 801546c: f04f 0350 mov.w r3, #80 @ 0x50 8015470: f383 8811 msr BASEPRI, r3 8015474: f3bf 8f6f isb sy 8015478: f3bf 8f4f dsb sy 801547c: 617b str r3, [r7, #20] } 801547e: bf00 nop 8015480: bf00 nop 8015482: e7fd b.n 8015480 } #endif /* configUSE_MUTEXES */ /* The semaphore count was 0 and no block time is specified (or the block time has expired) so exit now. */ taskEXIT_CRITICAL(); 8015484: f002 fcaa bl 8017ddc traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8015488: 2300 movs r3, #0 801548a: e082 b.n 8015592 } else if( xEntryTimeSet == pdFALSE ) 801548c: 6b7b ldr r3, [r7, #52] @ 0x34 801548e: 2b00 cmp r3, #0 8015490: d106 bne.n 80154a0 { /* The semaphore count was 0 and a block time was specified so configure the timeout structure ready to block. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8015492: f107 030c add.w r3, r7, #12 8015496: 4618 mov r0, r3 8015498: f001 f974 bl 8016784 xEntryTimeSet = pdTRUE; 801549c: 2301 movs r3, #1 801549e: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 80154a0: f002 fc9c bl 8017ddc /* Interrupts and other tasks can give to and take from the semaphore now the critical section has been exited. */ vTaskSuspendAll(); 80154a4: f000 fea6 bl 80161f4 prvLockQueue( pxQueue ); 80154a8: f002 fc66 bl 8017d78 80154ac: 6afb ldr r3, [r7, #44] @ 0x2c 80154ae: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80154b2: b25b sxtb r3, r3 80154b4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80154b8: d103 bne.n 80154c2 80154ba: 6afb ldr r3, [r7, #44] @ 0x2c 80154bc: 2200 movs r2, #0 80154be: f883 2044 strb.w r2, [r3, #68] @ 0x44 80154c2: 6afb ldr r3, [r7, #44] @ 0x2c 80154c4: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80154c8: b25b sxtb r3, r3 80154ca: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80154ce: d103 bne.n 80154d8 80154d0: 6afb ldr r3, [r7, #44] @ 0x2c 80154d2: 2200 movs r2, #0 80154d4: f883 2045 strb.w r2, [r3, #69] @ 0x45 80154d8: f002 fc80 bl 8017ddc /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 80154dc: 463a mov r2, r7 80154de: f107 030c add.w r3, r7, #12 80154e2: 4611 mov r1, r2 80154e4: 4618 mov r0, r3 80154e6: f001 f963 bl 80167b0 80154ea: 4603 mov r3, r0 80154ec: 2b00 cmp r3, #0 80154ee: d132 bne.n 8015556 { /* A block time is specified and not expired. If the semaphore count is 0 then enter the Blocked state to wait for a semaphore to become available. As semaphores are implemented with queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80154f0: 6af8 ldr r0, [r7, #44] @ 0x2c 80154f2: f000 f9d1 bl 8015898 80154f6: 4603 mov r3, r0 80154f8: 2b00 cmp r3, #0 80154fa: d026 beq.n 801554a { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 80154fc: 6afb ldr r3, [r7, #44] @ 0x2c 80154fe: 681b ldr r3, [r3, #0] 8015500: 2b00 cmp r3, #0 8015502: d109 bne.n 8015518 { taskENTER_CRITICAL(); 8015504: f002 fc38 bl 8017d78 { xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); 8015508: 6afb ldr r3, [r7, #44] @ 0x2c 801550a: 689b ldr r3, [r3, #8] 801550c: 4618 mov r0, r3 801550e: f001 fac9 bl 8016aa4 8015512: 6338 str r0, [r7, #48] @ 0x30 } taskEXIT_CRITICAL(); 8015514: f002 fc62 bl 8017ddc mtCOVERAGE_TEST_MARKER(); } } #endif vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 8015518: 6afb ldr r3, [r7, #44] @ 0x2c 801551a: 3324 adds r3, #36 @ 0x24 801551c: 683a ldr r2, [r7, #0] 801551e: 4611 mov r1, r2 8015520: 4618 mov r0, r3 8015522: f001 f851 bl 80165c8 prvUnlockQueue( pxQueue ); 8015526: 6af8 ldr r0, [r7, #44] @ 0x2c 8015528: f000 f964 bl 80157f4 if( xTaskResumeAll() == pdFALSE ) 801552c: f000 fe70 bl 8016210 8015530: 4603 mov r3, r0 8015532: 2b00 cmp r3, #0 8015534: f47f af67 bne.w 8015406 { portYIELD_WITHIN_API(); 8015538: 4b18 ldr r3, [pc, #96] @ (801559c ) 801553a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801553e: 601a str r2, [r3, #0] 8015540: f3bf 8f4f dsb sy 8015544: f3bf 8f6f isb sy 8015548: e75d b.n 8015406 } else { /* There was no timeout and the semaphore count was not 0, so attempt to take the semaphore again. */ prvUnlockQueue( pxQueue ); 801554a: 6af8 ldr r0, [r7, #44] @ 0x2c 801554c: f000 f952 bl 80157f4 ( void ) xTaskResumeAll(); 8015550: f000 fe5e bl 8016210 8015554: e757 b.n 8015406 } } else { /* Timed out. */ prvUnlockQueue( pxQueue ); 8015556: 6af8 ldr r0, [r7, #44] @ 0x2c 8015558: f000 f94c bl 80157f4 ( void ) xTaskResumeAll(); 801555c: f000 fe58 bl 8016210 /* If the semaphore count is 0 exit now as the timeout has expired. Otherwise return to attempt to take the semaphore that is known to be available. As semaphores are implemented by queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8015560: 6af8 ldr r0, [r7, #44] @ 0x2c 8015562: f000 f999 bl 8015898 8015566: 4603 mov r3, r0 8015568: 2b00 cmp r3, #0 801556a: f43f af4c beq.w 8015406 #if ( configUSE_MUTEXES == 1 ) { /* xInheritanceOccurred could only have be set if pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to test the mutex type again to check it is actually a mutex. */ if( xInheritanceOccurred != pdFALSE ) 801556e: 6b3b ldr r3, [r7, #48] @ 0x30 8015570: 2b00 cmp r3, #0 8015572: d00d beq.n 8015590 { taskENTER_CRITICAL(); 8015574: f002 fc00 bl 8017d78 /* This task blocking on the mutex caused another task to inherit this task's priority. Now this task has timed out the priority should be disinherited again, but only as low as the next highest priority task that is waiting for the same mutex. */ uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); 8015578: 6af8 ldr r0, [r7, #44] @ 0x2c 801557a: f000 f893 bl 80156a4 801557e: 6278 str r0, [r7, #36] @ 0x24 vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); 8015580: 6afb ldr r3, [r7, #44] @ 0x2c 8015582: 689b ldr r3, [r3, #8] 8015584: 6a79 ldr r1, [r7, #36] @ 0x24 8015586: 4618 mov r0, r3 8015588: f001 fb64 bl 8016c54 } taskEXIT_CRITICAL(); 801558c: f002 fc26 bl 8017ddc } } #endif /* configUSE_MUTEXES */ traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8015590: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 8015592: 4618 mov r0, r3 8015594: 3738 adds r7, #56 @ 0x38 8015596: 46bd mov sp, r7 8015598: bd80 pop {r7, pc} 801559a: bf00 nop 801559c: e000ed04 .word 0xe000ed04 080155a0 : } /*lint -restore */ } /*-----------------------------------------------------------*/ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) { 80155a0: b580 push {r7, lr} 80155a2: b08e sub sp, #56 @ 0x38 80155a4: af00 add r7, sp, #0 80155a6: 60f8 str r0, [r7, #12] 80155a8: 60b9 str r1, [r7, #8] 80155aa: 607a str r2, [r7, #4] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 80155ac: 68fb ldr r3, [r7, #12] 80155ae: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 80155b0: 6b3b ldr r3, [r7, #48] @ 0x30 80155b2: 2b00 cmp r3, #0 80155b4: d10b bne.n 80155ce __asm volatile 80155b6: f04f 0350 mov.w r3, #80 @ 0x50 80155ba: f383 8811 msr BASEPRI, r3 80155be: f3bf 8f6f isb sy 80155c2: f3bf 8f4f dsb sy 80155c6: 623b str r3, [r7, #32] } 80155c8: bf00 nop 80155ca: bf00 nop 80155cc: e7fd b.n 80155ca configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 80155ce: 68bb ldr r3, [r7, #8] 80155d0: 2b00 cmp r3, #0 80155d2: d103 bne.n 80155dc 80155d4: 6b3b ldr r3, [r7, #48] @ 0x30 80155d6: 6c1b ldr r3, [r3, #64] @ 0x40 80155d8: 2b00 cmp r3, #0 80155da: d101 bne.n 80155e0 80155dc: 2301 movs r3, #1 80155de: e000 b.n 80155e2 80155e0: 2300 movs r3, #0 80155e2: 2b00 cmp r3, #0 80155e4: d10b bne.n 80155fe __asm volatile 80155e6: f04f 0350 mov.w r3, #80 @ 0x50 80155ea: f383 8811 msr BASEPRI, r3 80155ee: f3bf 8f6f isb sy 80155f2: f3bf 8f4f dsb sy 80155f6: 61fb str r3, [r7, #28] } 80155f8: bf00 nop 80155fa: bf00 nop 80155fc: e7fd b.n 80155fa that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 80155fe: f002 fc9b bl 8017f38 __asm volatile 8015602: f3ef 8211 mrs r2, BASEPRI 8015606: f04f 0350 mov.w r3, #80 @ 0x50 801560a: f383 8811 msr BASEPRI, r3 801560e: f3bf 8f6f isb sy 8015612: f3bf 8f4f dsb sy 8015616: 61ba str r2, [r7, #24] 8015618: 617b str r3, [r7, #20] return ulOriginalBASEPRI; 801561a: 69bb ldr r3, [r7, #24] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 801561c: 62fb str r3, [r7, #44] @ 0x2c { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 801561e: 6b3b ldr r3, [r7, #48] @ 0x30 8015620: 6b9b ldr r3, [r3, #56] @ 0x38 8015622: 62bb str r3, [r7, #40] @ 0x28 /* Cannot block in an ISR, so check there is data available. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 8015624: 6abb ldr r3, [r7, #40] @ 0x28 8015626: 2b00 cmp r3, #0 8015628: d02f beq.n 801568a { const int8_t cRxLock = pxQueue->cRxLock; 801562a: 6b3b ldr r3, [r7, #48] @ 0x30 801562c: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8015630: f887 3027 strb.w r3, [r7, #39] @ 0x27 traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); prvCopyDataFromQueue( pxQueue, pvBuffer ); 8015634: 68b9 ldr r1, [r7, #8] 8015636: 6b38 ldr r0, [r7, #48] @ 0x30 8015638: f000 f8b6 bl 80157a8 pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 801563c: 6abb ldr r3, [r7, #40] @ 0x28 801563e: 1e5a subs r2, r3, #1 8015640: 6b3b ldr r3, [r7, #48] @ 0x30 8015642: 639a str r2, [r3, #56] @ 0x38 /* If the queue is locked the event list will not be modified. Instead update the lock count so the task that unlocks the queue will know that an ISR has removed data while the queue was locked. */ if( cRxLock == queueUNLOCKED ) 8015644: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27 8015648: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801564c: d112 bne.n 8015674 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 801564e: 6b3b ldr r3, [r7, #48] @ 0x30 8015650: 691b ldr r3, [r3, #16] 8015652: 2b00 cmp r3, #0 8015654: d016 beq.n 8015684 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8015656: 6b3b ldr r3, [r7, #48] @ 0x30 8015658: 3310 adds r3, #16 801565a: 4618 mov r0, r3 801565c: f001 f806 bl 801666c 8015660: 4603 mov r3, r0 8015662: 2b00 cmp r3, #0 8015664: d00e beq.n 8015684 { /* The task waiting has a higher priority than us so force a context switch. */ if( pxHigherPriorityTaskWoken != NULL ) 8015666: 687b ldr r3, [r7, #4] 8015668: 2b00 cmp r3, #0 801566a: d00b beq.n 8015684 { *pxHigherPriorityTaskWoken = pdTRUE; 801566c: 687b ldr r3, [r7, #4] 801566e: 2201 movs r2, #1 8015670: 601a str r2, [r3, #0] 8015672: e007 b.n 8015684 } else { /* Increment the lock count so the task that unlocks the queue knows that data was removed while it was locked. */ pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 ); 8015674: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8015678: 3301 adds r3, #1 801567a: b2db uxtb r3, r3 801567c: b25a sxtb r2, r3 801567e: 6b3b ldr r3, [r7, #48] @ 0x30 8015680: f883 2044 strb.w r2, [r3, #68] @ 0x44 } xReturn = pdPASS; 8015684: 2301 movs r3, #1 8015686: 637b str r3, [r7, #52] @ 0x34 8015688: e001 b.n 801568e } else { xReturn = pdFAIL; 801568a: 2300 movs r3, #0 801568c: 637b str r3, [r7, #52] @ 0x34 801568e: 6afb ldr r3, [r7, #44] @ 0x2c 8015690: 613b str r3, [r7, #16] __asm volatile 8015692: 693b ldr r3, [r7, #16] 8015694: f383 8811 msr BASEPRI, r3 } 8015698: bf00 nop traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 801569a: 6b7b ldr r3, [r7, #52] @ 0x34 } 801569c: 4618 mov r0, r3 801569e: 3738 adds r7, #56 @ 0x38 80156a0: 46bd mov sp, r7 80156a2: bd80 pop {r7, pc} 080156a4 : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) { 80156a4: b480 push {r7} 80156a6: b085 sub sp, #20 80156a8: af00 add r7, sp, #0 80156aa: 6078 str r0, [r7, #4] priority, but the waiting task times out, then the holder should disinherit the priority - but only down to the highest priority of any other tasks that are waiting for the same mutex. For this purpose, return the priority of the highest priority task that is waiting for the mutex. */ if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) 80156ac: 687b ldr r3, [r7, #4] 80156ae: 6a5b ldr r3, [r3, #36] @ 0x24 80156b0: 2b00 cmp r3, #0 80156b2: d006 beq.n 80156c2 { uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); 80156b4: 687b ldr r3, [r7, #4] 80156b6: 6b1b ldr r3, [r3, #48] @ 0x30 80156b8: 681b ldr r3, [r3, #0] 80156ba: f1c3 0338 rsb r3, r3, #56 @ 0x38 80156be: 60fb str r3, [r7, #12] 80156c0: e001 b.n 80156c6 } else { uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; 80156c2: 2300 movs r3, #0 80156c4: 60fb str r3, [r7, #12] } return uxHighestPriorityOfWaitingTasks; 80156c6: 68fb ldr r3, [r7, #12] } 80156c8: 4618 mov r0, r3 80156ca: 3714 adds r7, #20 80156cc: 46bd mov sp, r7 80156ce: f85d 7b04 ldr.w r7, [sp], #4 80156d2: 4770 bx lr 080156d4 : #endif /* configUSE_MUTEXES */ /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) { 80156d4: b580 push {r7, lr} 80156d6: b086 sub sp, #24 80156d8: af00 add r7, sp, #0 80156da: 60f8 str r0, [r7, #12] 80156dc: 60b9 str r1, [r7, #8] 80156de: 607a str r2, [r7, #4] BaseType_t xReturn = pdFALSE; 80156e0: 2300 movs r3, #0 80156e2: 617b str r3, [r7, #20] UBaseType_t uxMessagesWaiting; /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; 80156e4: 68fb ldr r3, [r7, #12] 80156e6: 6b9b ldr r3, [r3, #56] @ 0x38 80156e8: 613b str r3, [r7, #16] if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) 80156ea: 68fb ldr r3, [r7, #12] 80156ec: 6c1b ldr r3, [r3, #64] @ 0x40 80156ee: 2b00 cmp r3, #0 80156f0: d10d bne.n 801570e { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 80156f2: 68fb ldr r3, [r7, #12] 80156f4: 681b ldr r3, [r3, #0] 80156f6: 2b00 cmp r3, #0 80156f8: d14d bne.n 8015796 { /* The mutex is no longer being held. */ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); 80156fa: 68fb ldr r3, [r7, #12] 80156fc: 689b ldr r3, [r3, #8] 80156fe: 4618 mov r0, r3 8015700: f001 fa38 bl 8016b74 8015704: 6178 str r0, [r7, #20] pxQueue->u.xSemaphore.xMutexHolder = NULL; 8015706: 68fb ldr r3, [r7, #12] 8015708: 2200 movs r2, #0 801570a: 609a str r2, [r3, #8] 801570c: e043 b.n 8015796 mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_MUTEXES */ } else if( xPosition == queueSEND_TO_BACK ) 801570e: 687b ldr r3, [r7, #4] 8015710: 2b00 cmp r3, #0 8015712: d119 bne.n 8015748 { ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 8015714: 68fb ldr r3, [r7, #12] 8015716: 6858 ldr r0, [r3, #4] 8015718: 68fb ldr r3, [r7, #12] 801571a: 6c1b ldr r3, [r3, #64] @ 0x40 801571c: 461a mov r2, r3 801571e: 68b9 ldr r1, [r7, #8] 8015720: f002 fec4 bl 80184ac pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 8015724: 68fb ldr r3, [r7, #12] 8015726: 685a ldr r2, [r3, #4] 8015728: 68fb ldr r3, [r7, #12] 801572a: 6c1b ldr r3, [r3, #64] @ 0x40 801572c: 441a add r2, r3 801572e: 68fb ldr r3, [r7, #12] 8015730: 605a str r2, [r3, #4] if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 8015732: 68fb ldr r3, [r7, #12] 8015734: 685a ldr r2, [r3, #4] 8015736: 68fb ldr r3, [r7, #12] 8015738: 689b ldr r3, [r3, #8] 801573a: 429a cmp r2, r3 801573c: d32b bcc.n 8015796 { pxQueue->pcWriteTo = pxQueue->pcHead; 801573e: 68fb ldr r3, [r7, #12] 8015740: 681a ldr r2, [r3, #0] 8015742: 68fb ldr r3, [r7, #12] 8015744: 605a str r2, [r3, #4] 8015746: e026 b.n 8015796 mtCOVERAGE_TEST_MARKER(); } } else { ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ 8015748: 68fb ldr r3, [r7, #12] 801574a: 68d8 ldr r0, [r3, #12] 801574c: 68fb ldr r3, [r7, #12] 801574e: 6c1b ldr r3, [r3, #64] @ 0x40 8015750: 461a mov r2, r3 8015752: 68b9 ldr r1, [r7, #8] 8015754: f002 feaa bl 80184ac pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; 8015758: 68fb ldr r3, [r7, #12] 801575a: 68da ldr r2, [r3, #12] 801575c: 68fb ldr r3, [r7, #12] 801575e: 6c1b ldr r3, [r3, #64] @ 0x40 8015760: 425b negs r3, r3 8015762: 441a add r2, r3 8015764: 68fb ldr r3, [r7, #12] 8015766: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 8015768: 68fb ldr r3, [r7, #12] 801576a: 68da ldr r2, [r3, #12] 801576c: 68fb ldr r3, [r7, #12] 801576e: 681b ldr r3, [r3, #0] 8015770: 429a cmp r2, r3 8015772: d207 bcs.n 8015784 { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); 8015774: 68fb ldr r3, [r7, #12] 8015776: 689a ldr r2, [r3, #8] 8015778: 68fb ldr r3, [r7, #12] 801577a: 6c1b ldr r3, [r3, #64] @ 0x40 801577c: 425b negs r3, r3 801577e: 441a add r2, r3 8015780: 68fb ldr r3, [r7, #12] 8015782: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } if( xPosition == queueOVERWRITE ) 8015784: 687b ldr r3, [r7, #4] 8015786: 2b02 cmp r3, #2 8015788: d105 bne.n 8015796 { if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 801578a: 693b ldr r3, [r7, #16] 801578c: 2b00 cmp r3, #0 801578e: d002 beq.n 8015796 { /* An item is not being added but overwritten, so subtract one from the recorded number of items in the queue so when one is added again below the number of recorded items remains correct. */ --uxMessagesWaiting; 8015790: 693b ldr r3, [r7, #16] 8015792: 3b01 subs r3, #1 8015794: 613b str r3, [r7, #16] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 8015796: 693b ldr r3, [r7, #16] 8015798: 1c5a adds r2, r3, #1 801579a: 68fb ldr r3, [r7, #12] 801579c: 639a str r2, [r3, #56] @ 0x38 return xReturn; 801579e: 697b ldr r3, [r7, #20] } 80157a0: 4618 mov r0, r3 80157a2: 3718 adds r7, #24 80157a4: 46bd mov sp, r7 80157a6: bd80 pop {r7, pc} 080157a8 : /*-----------------------------------------------------------*/ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) { 80157a8: b580 push {r7, lr} 80157aa: b082 sub sp, #8 80157ac: af00 add r7, sp, #0 80157ae: 6078 str r0, [r7, #4] 80157b0: 6039 str r1, [r7, #0] if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) 80157b2: 687b ldr r3, [r7, #4] 80157b4: 6c1b ldr r3, [r3, #64] @ 0x40 80157b6: 2b00 cmp r3, #0 80157b8: d018 beq.n 80157ec { pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 80157ba: 687b ldr r3, [r7, #4] 80157bc: 68da ldr r2, [r3, #12] 80157be: 687b ldr r3, [r7, #4] 80157c0: 6c1b ldr r3, [r3, #64] @ 0x40 80157c2: 441a add r2, r3 80157c4: 687b ldr r3, [r7, #4] 80157c6: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 80157c8: 687b ldr r3, [r7, #4] 80157ca: 68da ldr r2, [r3, #12] 80157cc: 687b ldr r3, [r7, #4] 80157ce: 689b ldr r3, [r3, #8] 80157d0: 429a cmp r2, r3 80157d2: d303 bcc.n 80157dc { pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; 80157d4: 687b ldr r3, [r7, #4] 80157d6: 681a ldr r2, [r3, #0] 80157d8: 687b ldr r3, [r7, #4] 80157da: 60da str r2, [r3, #12] } else { mtCOVERAGE_TEST_MARKER(); } ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 80157dc: 687b ldr r3, [r7, #4] 80157de: 68d9 ldr r1, [r3, #12] 80157e0: 687b ldr r3, [r7, #4] 80157e2: 6c1b ldr r3, [r3, #64] @ 0x40 80157e4: 461a mov r2, r3 80157e6: 6838 ldr r0, [r7, #0] 80157e8: f002 fe60 bl 80184ac } } 80157ec: bf00 nop 80157ee: 3708 adds r7, #8 80157f0: 46bd mov sp, r7 80157f2: bd80 pop {r7, pc} 080157f4 : /*-----------------------------------------------------------*/ static void prvUnlockQueue( Queue_t * const pxQueue ) { 80157f4: b580 push {r7, lr} 80157f6: b084 sub sp, #16 80157f8: af00 add r7, sp, #0 80157fa: 6078 str r0, [r7, #4] /* The lock counts contains the number of extra data items placed or removed from the queue while the queue was locked. When a queue is locked items can be added or removed, but the event lists cannot be updated. */ taskENTER_CRITICAL(); 80157fc: f002 fabc bl 8017d78 { int8_t cTxLock = pxQueue->cTxLock; 8015800: 687b ldr r3, [r7, #4] 8015802: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8015806: 73fb strb r3, [r7, #15] /* See if data was added to the queue while it was locked. */ while( cTxLock > queueLOCKED_UNMODIFIED ) 8015808: e011 b.n 801582e } #else /* configUSE_QUEUE_SETS */ { /* Tasks that are removed from the event list will get added to the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 801580a: 687b ldr r3, [r7, #4] 801580c: 6a5b ldr r3, [r3, #36] @ 0x24 801580e: 2b00 cmp r3, #0 8015810: d012 beq.n 8015838 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8015812: 687b ldr r3, [r7, #4] 8015814: 3324 adds r3, #36 @ 0x24 8015816: 4618 mov r0, r3 8015818: f000 ff28 bl 801666c 801581c: 4603 mov r3, r0 801581e: 2b00 cmp r3, #0 8015820: d001 beq.n 8015826 { /* The task waiting has a higher priority so record that a context switch is required. */ vTaskMissedYield(); 8015822: f001 f829 bl 8016878 break; } } #endif /* configUSE_QUEUE_SETS */ --cTxLock; 8015826: 7bfb ldrb r3, [r7, #15] 8015828: 3b01 subs r3, #1 801582a: b2db uxtb r3, r3 801582c: 73fb strb r3, [r7, #15] while( cTxLock > queueLOCKED_UNMODIFIED ) 801582e: f997 300f ldrsb.w r3, [r7, #15] 8015832: 2b00 cmp r3, #0 8015834: dce9 bgt.n 801580a 8015836: e000 b.n 801583a break; 8015838: bf00 nop } pxQueue->cTxLock = queueUNLOCKED; 801583a: 687b ldr r3, [r7, #4] 801583c: 22ff movs r2, #255 @ 0xff 801583e: f883 2045 strb.w r2, [r3, #69] @ 0x45 } taskEXIT_CRITICAL(); 8015842: f002 facb bl 8017ddc /* Do the same for the Rx lock. */ taskENTER_CRITICAL(); 8015846: f002 fa97 bl 8017d78 { int8_t cRxLock = pxQueue->cRxLock; 801584a: 687b ldr r3, [r7, #4] 801584c: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8015850: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 8015852: e011 b.n 8015878 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8015854: 687b ldr r3, [r7, #4] 8015856: 691b ldr r3, [r3, #16] 8015858: 2b00 cmp r3, #0 801585a: d012 beq.n 8015882 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 801585c: 687b ldr r3, [r7, #4] 801585e: 3310 adds r3, #16 8015860: 4618 mov r0, r3 8015862: f000 ff03 bl 801666c 8015866: 4603 mov r3, r0 8015868: 2b00 cmp r3, #0 801586a: d001 beq.n 8015870 { vTaskMissedYield(); 801586c: f001 f804 bl 8016878 else { mtCOVERAGE_TEST_MARKER(); } --cRxLock; 8015870: 7bbb ldrb r3, [r7, #14] 8015872: 3b01 subs r3, #1 8015874: b2db uxtb r3, r3 8015876: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 8015878: f997 300e ldrsb.w r3, [r7, #14] 801587c: 2b00 cmp r3, #0 801587e: dce9 bgt.n 8015854 8015880: e000 b.n 8015884 } else { break; 8015882: bf00 nop } } pxQueue->cRxLock = queueUNLOCKED; 8015884: 687b ldr r3, [r7, #4] 8015886: 22ff movs r2, #255 @ 0xff 8015888: f883 2044 strb.w r2, [r3, #68] @ 0x44 } taskEXIT_CRITICAL(); 801588c: f002 faa6 bl 8017ddc } 8015890: bf00 nop 8015892: 3710 adds r7, #16 8015894: 46bd mov sp, r7 8015896: bd80 pop {r7, pc} 08015898 : /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) { 8015898: b580 push {r7, lr} 801589a: b084 sub sp, #16 801589c: af00 add r7, sp, #0 801589e: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 80158a0: f002 fa6a bl 8017d78 { if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) 80158a4: 687b ldr r3, [r7, #4] 80158a6: 6b9b ldr r3, [r3, #56] @ 0x38 80158a8: 2b00 cmp r3, #0 80158aa: d102 bne.n 80158b2 { xReturn = pdTRUE; 80158ac: 2301 movs r3, #1 80158ae: 60fb str r3, [r7, #12] 80158b0: e001 b.n 80158b6 } else { xReturn = pdFALSE; 80158b2: 2300 movs r3, #0 80158b4: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 80158b6: f002 fa91 bl 8017ddc return xReturn; 80158ba: 68fb ldr r3, [r7, #12] } 80158bc: 4618 mov r0, r3 80158be: 3710 adds r7, #16 80158c0: 46bd mov sp, r7 80158c2: bd80 pop {r7, pc} 080158c4 : return xReturn; } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) { 80158c4: b580 push {r7, lr} 80158c6: b084 sub sp, #16 80158c8: af00 add r7, sp, #0 80158ca: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 80158cc: f002 fa54 bl 8017d78 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) 80158d0: 687b ldr r3, [r7, #4] 80158d2: 6b9a ldr r2, [r3, #56] @ 0x38 80158d4: 687b ldr r3, [r7, #4] 80158d6: 6bdb ldr r3, [r3, #60] @ 0x3c 80158d8: 429a cmp r2, r3 80158da: d102 bne.n 80158e2 { xReturn = pdTRUE; 80158dc: 2301 movs r3, #1 80158de: 60fb str r3, [r7, #12] 80158e0: e001 b.n 80158e6 } else { xReturn = pdFALSE; 80158e2: 2300 movs r3, #0 80158e4: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 80158e6: f002 fa79 bl 8017ddc return xReturn; 80158ea: 68fb ldr r3, [r7, #12] } 80158ec: 4618 mov r0, r3 80158ee: 3710 adds r7, #16 80158f0: 46bd mov sp, r7 80158f2: bd80 pop {r7, pc} 080158f4 : /*-----------------------------------------------------------*/ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ { 80158f4: b480 push {r7} 80158f6: b085 sub sp, #20 80158f8: af00 add r7, sp, #0 80158fa: 6078 str r0, [r7, #4] 80158fc: 6039 str r1, [r7, #0] UBaseType_t ux; /* See if there is an empty space in the registry. A NULL name denotes a free slot. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 80158fe: 2300 movs r3, #0 8015900: 60fb str r3, [r7, #12] 8015902: e014 b.n 801592e { if( xQueueRegistry[ ux ].pcQueueName == NULL ) 8015904: 4a0f ldr r2, [pc, #60] @ (8015944 ) 8015906: 68fb ldr r3, [r7, #12] 8015908: f852 3033 ldr.w r3, [r2, r3, lsl #3] 801590c: 2b00 cmp r3, #0 801590e: d10b bne.n 8015928 { /* Store the information on this queue. */ xQueueRegistry[ ux ].pcQueueName = pcQueueName; 8015910: 490c ldr r1, [pc, #48] @ (8015944 ) 8015912: 68fb ldr r3, [r7, #12] 8015914: 683a ldr r2, [r7, #0] 8015916: f841 2033 str.w r2, [r1, r3, lsl #3] xQueueRegistry[ ux ].xHandle = xQueue; 801591a: 4a0a ldr r2, [pc, #40] @ (8015944 ) 801591c: 68fb ldr r3, [r7, #12] 801591e: 00db lsls r3, r3, #3 8015920: 4413 add r3, r2 8015922: 687a ldr r2, [r7, #4] 8015924: 605a str r2, [r3, #4] traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); break; 8015926: e006 b.n 8015936 for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8015928: 68fb ldr r3, [r7, #12] 801592a: 3301 adds r3, #1 801592c: 60fb str r3, [r7, #12] 801592e: 68fb ldr r3, [r7, #12] 8015930: 2b07 cmp r3, #7 8015932: d9e7 bls.n 8015904 else { mtCOVERAGE_TEST_MARKER(); } } } 8015934: bf00 nop 8015936: bf00 nop 8015938: 3714 adds r7, #20 801593a: 46bd mov sp, r7 801593c: f85d 7b04 ldr.w r7, [sp], #4 8015940: 4770 bx lr 8015942: bf00 nop 8015944: 240029b8 .word 0x240029b8 08015948 : /*-----------------------------------------------------------*/ #if ( configUSE_TIMERS == 1 ) void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 8015948: b580 push {r7, lr} 801594a: b086 sub sp, #24 801594c: af00 add r7, sp, #0 801594e: 60f8 str r0, [r7, #12] 8015950: 60b9 str r1, [r7, #8] 8015952: 607a str r2, [r7, #4] Queue_t * const pxQueue = xQueue; 8015954: 68fb ldr r3, [r7, #12] 8015956: 617b str r3, [r7, #20] will not actually cause the task to block, just place it on a blocked list. It will not block until the scheduler is unlocked - at which time a yield will be performed. If an item is added to the queue while the queue is locked, and the calling task blocks on the queue, then the calling task will be immediately unblocked when the queue is unlocked. */ prvLockQueue( pxQueue ); 8015958: f002 fa0e bl 8017d78 801595c: 697b ldr r3, [r7, #20] 801595e: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8015962: b25b sxtb r3, r3 8015964: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015968: d103 bne.n 8015972 801596a: 697b ldr r3, [r7, #20] 801596c: 2200 movs r2, #0 801596e: f883 2044 strb.w r2, [r3, #68] @ 0x44 8015972: 697b ldr r3, [r7, #20] 8015974: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8015978: b25b sxtb r3, r3 801597a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801597e: d103 bne.n 8015988 8015980: 697b ldr r3, [r7, #20] 8015982: 2200 movs r2, #0 8015984: f883 2045 strb.w r2, [r3, #69] @ 0x45 8015988: f002 fa28 bl 8017ddc if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) 801598c: 697b ldr r3, [r7, #20] 801598e: 6b9b ldr r3, [r3, #56] @ 0x38 8015990: 2b00 cmp r3, #0 8015992: d106 bne.n 80159a2 { /* There is nothing in the queue, block for the specified period. */ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); 8015994: 697b ldr r3, [r7, #20] 8015996: 3324 adds r3, #36 @ 0x24 8015998: 687a ldr r2, [r7, #4] 801599a: 68b9 ldr r1, [r7, #8] 801599c: 4618 mov r0, r3 801599e: f000 fe39 bl 8016614 } else { mtCOVERAGE_TEST_MARKER(); } prvUnlockQueue( pxQueue ); 80159a2: 6978 ldr r0, [r7, #20] 80159a4: f7ff ff26 bl 80157f4 } 80159a8: bf00 nop 80159aa: 3718 adds r7, #24 80159ac: 46bd mov sp, r7 80159ae: bd80 pop {r7, pc} 080159b0 : return xReturn; } /*-----------------------------------------------------------*/ size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) { 80159b0: b480 push {r7} 80159b2: b087 sub sp, #28 80159b4: af00 add r7, sp, #0 80159b6: 6078 str r0, [r7, #4] const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 80159b8: 687b ldr r3, [r7, #4] 80159ba: 613b str r3, [r7, #16] size_t xSpace; configASSERT( pxStreamBuffer ); 80159bc: 693b ldr r3, [r7, #16] 80159be: 2b00 cmp r3, #0 80159c0: d10b bne.n 80159da __asm volatile 80159c2: f04f 0350 mov.w r3, #80 @ 0x50 80159c6: f383 8811 msr BASEPRI, r3 80159ca: f3bf 8f6f isb sy 80159ce: f3bf 8f4f dsb sy 80159d2: 60fb str r3, [r7, #12] } 80159d4: bf00 nop 80159d6: bf00 nop 80159d8: e7fd b.n 80159d6 xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; 80159da: 693b ldr r3, [r7, #16] 80159dc: 689a ldr r2, [r3, #8] 80159de: 693b ldr r3, [r7, #16] 80159e0: 681b ldr r3, [r3, #0] 80159e2: 4413 add r3, r2 80159e4: 617b str r3, [r7, #20] xSpace -= pxStreamBuffer->xHead; 80159e6: 693b ldr r3, [r7, #16] 80159e8: 685b ldr r3, [r3, #4] 80159ea: 697a ldr r2, [r7, #20] 80159ec: 1ad3 subs r3, r2, r3 80159ee: 617b str r3, [r7, #20] xSpace -= ( size_t ) 1; 80159f0: 697b ldr r3, [r7, #20] 80159f2: 3b01 subs r3, #1 80159f4: 617b str r3, [r7, #20] if( xSpace >= pxStreamBuffer->xLength ) 80159f6: 693b ldr r3, [r7, #16] 80159f8: 689b ldr r3, [r3, #8] 80159fa: 697a ldr r2, [r7, #20] 80159fc: 429a cmp r2, r3 80159fe: d304 bcc.n 8015a0a { xSpace -= pxStreamBuffer->xLength; 8015a00: 693b ldr r3, [r7, #16] 8015a02: 689b ldr r3, [r3, #8] 8015a04: 697a ldr r2, [r7, #20] 8015a06: 1ad3 subs r3, r2, r3 8015a08: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xSpace; 8015a0a: 697b ldr r3, [r7, #20] } 8015a0c: 4618 mov r0, r3 8015a0e: 371c adds r7, #28 8015a10: 46bd mov sp, r7 8015a12: f85d 7b04 ldr.w r7, [sp], #4 8015a16: 4770 bx lr 08015a18 : size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) { 8015a18: b580 push {r7, lr} 8015a1a: b090 sub sp, #64 @ 0x40 8015a1c: af02 add r7, sp, #8 8015a1e: 60f8 str r0, [r7, #12] 8015a20: 60b9 str r1, [r7, #8] 8015a22: 607a str r2, [r7, #4] 8015a24: 603b str r3, [r7, #0] StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 8015a26: 68fb ldr r3, [r7, #12] 8015a28: 62fb str r3, [r7, #44] @ 0x2c size_t xReturn, xSpace = 0; 8015a2a: 2300 movs r3, #0 8015a2c: 637b str r3, [r7, #52] @ 0x34 size_t xRequiredSpace = xDataLengthBytes; 8015a2e: 687b ldr r3, [r7, #4] 8015a30: 633b str r3, [r7, #48] @ 0x30 TimeOut_t xTimeOut; configASSERT( pvTxData ); 8015a32: 68bb ldr r3, [r7, #8] 8015a34: 2b00 cmp r3, #0 8015a36: d10b bne.n 8015a50 __asm volatile 8015a38: f04f 0350 mov.w r3, #80 @ 0x50 8015a3c: f383 8811 msr BASEPRI, r3 8015a40: f3bf 8f6f isb sy 8015a44: f3bf 8f4f dsb sy 8015a48: 627b str r3, [r7, #36] @ 0x24 } 8015a4a: bf00 nop 8015a4c: bf00 nop 8015a4e: e7fd b.n 8015a4c configASSERT( pxStreamBuffer ); 8015a50: 6afb ldr r3, [r7, #44] @ 0x2c 8015a52: 2b00 cmp r3, #0 8015a54: d10b bne.n 8015a6e __asm volatile 8015a56: f04f 0350 mov.w r3, #80 @ 0x50 8015a5a: f383 8811 msr BASEPRI, r3 8015a5e: f3bf 8f6f isb sy 8015a62: f3bf 8f4f dsb sy 8015a66: 623b str r3, [r7, #32] } 8015a68: bf00 nop 8015a6a: bf00 nop 8015a6c: e7fd b.n 8015a6a /* This send function is used to write to both message buffers and stream buffers. If this is a message buffer then the space needed must be increased by the amount of bytes needed to store the length of the message. */ if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) 8015a6e: 6afb ldr r3, [r7, #44] @ 0x2c 8015a70: 7f1b ldrb r3, [r3, #28] 8015a72: f003 0301 and.w r3, r3, #1 8015a76: 2b00 cmp r3, #0 8015a78: d012 beq.n 8015aa0 { xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; 8015a7a: 6b3b ldr r3, [r7, #48] @ 0x30 8015a7c: 3304 adds r3, #4 8015a7e: 633b str r3, [r7, #48] @ 0x30 /* Overflow? */ configASSERT( xRequiredSpace > xDataLengthBytes ); 8015a80: 6b3a ldr r2, [r7, #48] @ 0x30 8015a82: 687b ldr r3, [r7, #4] 8015a84: 429a cmp r2, r3 8015a86: d80b bhi.n 8015aa0 __asm volatile 8015a88: f04f 0350 mov.w r3, #80 @ 0x50 8015a8c: f383 8811 msr BASEPRI, r3 8015a90: f3bf 8f6f isb sy 8015a94: f3bf 8f4f dsb sy 8015a98: 61fb str r3, [r7, #28] } 8015a9a: bf00 nop 8015a9c: bf00 nop 8015a9e: e7fd b.n 8015a9c else { mtCOVERAGE_TEST_MARKER(); } if( xTicksToWait != ( TickType_t ) 0 ) 8015aa0: 683b ldr r3, [r7, #0] 8015aa2: 2b00 cmp r3, #0 8015aa4: d03f beq.n 8015b26 { vTaskSetTimeOutState( &xTimeOut ); 8015aa6: f107 0310 add.w r3, r7, #16 8015aaa: 4618 mov r0, r3 8015aac: f000 fe42 bl 8016734 do { /* Wait until the required number of bytes are free in the message buffer. */ taskENTER_CRITICAL(); 8015ab0: f002 f962 bl 8017d78 { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 8015ab4: 6af8 ldr r0, [r7, #44] @ 0x2c 8015ab6: f7ff ff7b bl 80159b0 8015aba: 6378 str r0, [r7, #52] @ 0x34 if( xSpace < xRequiredSpace ) 8015abc: 6b7a ldr r2, [r7, #52] @ 0x34 8015abe: 6b3b ldr r3, [r7, #48] @ 0x30 8015ac0: 429a cmp r2, r3 8015ac2: d218 bcs.n 8015af6 { /* Clear notification state as going to wait for space. */ ( void ) xTaskNotifyStateClear( NULL ); 8015ac4: 2000 movs r0, #0 8015ac6: f001 fb65 bl 8017194 /* Should only be one writer. */ configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL ); 8015aca: 6afb ldr r3, [r7, #44] @ 0x2c 8015acc: 695b ldr r3, [r3, #20] 8015ace: 2b00 cmp r3, #0 8015ad0: d00b beq.n 8015aea __asm volatile 8015ad2: f04f 0350 mov.w r3, #80 @ 0x50 8015ad6: f383 8811 msr BASEPRI, r3 8015ada: f3bf 8f6f isb sy 8015ade: f3bf 8f4f dsb sy 8015ae2: 61bb str r3, [r7, #24] } 8015ae4: bf00 nop 8015ae6: bf00 nop 8015ae8: e7fd b.n 8015ae6 pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle(); 8015aea: f000 ffad bl 8016a48 8015aee: 4602 mov r2, r0 8015af0: 6afb ldr r3, [r7, #44] @ 0x2c 8015af2: 615a str r2, [r3, #20] 8015af4: e002 b.n 8015afc } else { taskEXIT_CRITICAL(); 8015af6: f002 f971 bl 8017ddc break; 8015afa: e014 b.n 8015b26 } } taskEXIT_CRITICAL(); 8015afc: f002 f96e bl 8017ddc traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ); ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); 8015b00: 683b ldr r3, [r7, #0] 8015b02: 2200 movs r2, #0 8015b04: 2100 movs r1, #0 8015b06: 2000 movs r0, #0 8015b08: f001 f93c bl 8016d84 pxStreamBuffer->xTaskWaitingToSend = NULL; 8015b0c: 6afb ldr r3, [r7, #44] @ 0x2c 8015b0e: 2200 movs r2, #0 8015b10: 615a str r2, [r3, #20] } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); 8015b12: 463a mov r2, r7 8015b14: f107 0310 add.w r3, r7, #16 8015b18: 4611 mov r1, r2 8015b1a: 4618 mov r0, r3 8015b1c: f000 fe48 bl 80167b0 8015b20: 4603 mov r3, r0 8015b22: 2b00 cmp r3, #0 8015b24: d0c4 beq.n 8015ab0 else { mtCOVERAGE_TEST_MARKER(); } if( xSpace == ( size_t ) 0 ) 8015b26: 6b7b ldr r3, [r7, #52] @ 0x34 8015b28: 2b00 cmp r3, #0 8015b2a: d103 bne.n 8015b34 { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 8015b2c: 6af8 ldr r0, [r7, #44] @ 0x2c 8015b2e: f7ff ff3f bl 80159b0 8015b32: 6378 str r0, [r7, #52] @ 0x34 else { mtCOVERAGE_TEST_MARKER(); } xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); 8015b34: 6b3b ldr r3, [r7, #48] @ 0x30 8015b36: 9300 str r3, [sp, #0] 8015b38: 6b7b ldr r3, [r7, #52] @ 0x34 8015b3a: 687a ldr r2, [r7, #4] 8015b3c: 68b9 ldr r1, [r7, #8] 8015b3e: 6af8 ldr r0, [r7, #44] @ 0x2c 8015b40: f000 f823 bl 8015b8a 8015b44: 62b8 str r0, [r7, #40] @ 0x28 if( xReturn > ( size_t ) 0 ) 8015b46: 6abb ldr r3, [r7, #40] @ 0x28 8015b48: 2b00 cmp r3, #0 8015b4a: d019 beq.n 8015b80 { traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn ); /* Was a task waiting for the data? */ if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) 8015b4c: 6af8 ldr r0, [r7, #44] @ 0x2c 8015b4e: f000 f8ce bl 8015cee 8015b52: 4602 mov r2, r0 8015b54: 6afb ldr r3, [r7, #44] @ 0x2c 8015b56: 68db ldr r3, [r3, #12] 8015b58: 429a cmp r2, r3 8015b5a: d311 bcc.n 8015b80 { sbSEND_COMPLETED( pxStreamBuffer ); 8015b5c: f000 fb4a bl 80161f4 8015b60: 6afb ldr r3, [r7, #44] @ 0x2c 8015b62: 691b ldr r3, [r3, #16] 8015b64: 2b00 cmp r3, #0 8015b66: d009 beq.n 8015b7c 8015b68: 6afb ldr r3, [r7, #44] @ 0x2c 8015b6a: 6918 ldr r0, [r3, #16] 8015b6c: 2300 movs r3, #0 8015b6e: 2200 movs r2, #0 8015b70: 2100 movs r1, #0 8015b72: f001 f967 bl 8016e44 8015b76: 6afb ldr r3, [r7, #44] @ 0x2c 8015b78: 2200 movs r2, #0 8015b7a: 611a str r2, [r3, #16] 8015b7c: f000 fb48 bl 8016210 { mtCOVERAGE_TEST_MARKER(); traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ); } return xReturn; 8015b80: 6abb ldr r3, [r7, #40] @ 0x28 } 8015b82: 4618 mov r0, r3 8015b84: 3738 adds r7, #56 @ 0x38 8015b86: 46bd mov sp, r7 8015b88: bd80 pop {r7, pc} 08015b8a : static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, const void * pvTxData, size_t xDataLengthBytes, size_t xSpace, size_t xRequiredSpace ) { 8015b8a: b580 push {r7, lr} 8015b8c: b086 sub sp, #24 8015b8e: af00 add r7, sp, #0 8015b90: 60f8 str r0, [r7, #12] 8015b92: 60b9 str r1, [r7, #8] 8015b94: 607a str r2, [r7, #4] 8015b96: 603b str r3, [r7, #0] BaseType_t xShouldWrite; size_t xReturn; if( xSpace == ( size_t ) 0 ) 8015b98: 683b ldr r3, [r7, #0] 8015b9a: 2b00 cmp r3, #0 8015b9c: d102 bne.n 8015ba4 { /* Doesn't matter if this is a stream buffer or a message buffer, there is no space to write. */ xShouldWrite = pdFALSE; 8015b9e: 2300 movs r3, #0 8015ba0: 617b str r3, [r7, #20] 8015ba2: e01d b.n 8015be0 } else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 ) 8015ba4: 68fb ldr r3, [r7, #12] 8015ba6: 7f1b ldrb r3, [r3, #28] 8015ba8: f003 0301 and.w r3, r3, #1 8015bac: 2b00 cmp r3, #0 8015bae: d108 bne.n 8015bc2 { /* This is a stream buffer, as opposed to a message buffer, so writing a stream of bytes rather than discrete messages. Write as many bytes as possible. */ xShouldWrite = pdTRUE; 8015bb0: 2301 movs r3, #1 8015bb2: 617b str r3, [r7, #20] xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); 8015bb4: 687a ldr r2, [r7, #4] 8015bb6: 683b ldr r3, [r7, #0] 8015bb8: 4293 cmp r3, r2 8015bba: bf28 it cs 8015bbc: 4613 movcs r3, r2 8015bbe: 607b str r3, [r7, #4] 8015bc0: e00e b.n 8015be0 } else if( xSpace >= xRequiredSpace ) 8015bc2: 683a ldr r2, [r7, #0] 8015bc4: 6a3b ldr r3, [r7, #32] 8015bc6: 429a cmp r2, r3 8015bc8: d308 bcc.n 8015bdc { /* This is a message buffer, as opposed to a stream buffer, and there is enough space to write both the message length and the message itself into the buffer. Start by writing the length of the data, the data itself will be written later in this function. */ xShouldWrite = pdTRUE; 8015bca: 2301 movs r3, #1 8015bcc: 617b str r3, [r7, #20] ( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH ); 8015bce: 1d3b adds r3, r7, #4 8015bd0: 2204 movs r2, #4 8015bd2: 4619 mov r1, r3 8015bd4: 68f8 ldr r0, [r7, #12] 8015bd6: f000 f815 bl 8015c04 8015bda: e001 b.n 8015be0 } else { /* There is space available, but not enough space. */ xShouldWrite = pdFALSE; 8015bdc: 2300 movs r3, #0 8015bde: 617b str r3, [r7, #20] } if( xShouldWrite != pdFALSE ) 8015be0: 697b ldr r3, [r7, #20] 8015be2: 2b00 cmp r3, #0 8015be4: d007 beq.n 8015bf6 { /* Writes the data itself. */ xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */ 8015be6: 687b ldr r3, [r7, #4] 8015be8: 461a mov r2, r3 8015bea: 68b9 ldr r1, [r7, #8] 8015bec: 68f8 ldr r0, [r7, #12] 8015bee: f000 f809 bl 8015c04 8015bf2: 6138 str r0, [r7, #16] 8015bf4: e001 b.n 8015bfa } else { xReturn = 0; 8015bf6: 2300 movs r3, #0 8015bf8: 613b str r3, [r7, #16] } return xReturn; 8015bfa: 693b ldr r3, [r7, #16] } 8015bfc: 4618 mov r0, r3 8015bfe: 3718 adds r7, #24 8015c00: 46bd mov sp, r7 8015c02: bd80 pop {r7, pc} 08015c04 : return xReturn; } /*-----------------------------------------------------------*/ static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) { 8015c04: b580 push {r7, lr} 8015c06: b08a sub sp, #40 @ 0x28 8015c08: af00 add r7, sp, #0 8015c0a: 60f8 str r0, [r7, #12] 8015c0c: 60b9 str r1, [r7, #8] 8015c0e: 607a str r2, [r7, #4] size_t xNextHead, xFirstLength; configASSERT( xCount > ( size_t ) 0 ); 8015c10: 687b ldr r3, [r7, #4] 8015c12: 2b00 cmp r3, #0 8015c14: d10b bne.n 8015c2e __asm volatile 8015c16: f04f 0350 mov.w r3, #80 @ 0x50 8015c1a: f383 8811 msr BASEPRI, r3 8015c1e: f3bf 8f6f isb sy 8015c22: f3bf 8f4f dsb sy 8015c26: 61fb str r3, [r7, #28] } 8015c28: bf00 nop 8015c2a: bf00 nop 8015c2c: e7fd b.n 8015c2a xNextHead = pxStreamBuffer->xHead; 8015c2e: 68fb ldr r3, [r7, #12] 8015c30: 685b ldr r3, [r3, #4] 8015c32: 627b str r3, [r7, #36] @ 0x24 /* Calculate the number of bytes that can be added in the first write - which may be less than the total number of bytes that need to be added if the buffer will wrap back to the beginning. */ xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount ); 8015c34: 68fb ldr r3, [r7, #12] 8015c36: 689a ldr r2, [r3, #8] 8015c38: 6a7b ldr r3, [r7, #36] @ 0x24 8015c3a: 1ad3 subs r3, r2, r3 8015c3c: 687a ldr r2, [r7, #4] 8015c3e: 4293 cmp r3, r2 8015c40: bf28 it cs 8015c42: 4613 movcs r3, r2 8015c44: 623b str r3, [r7, #32] /* Write as many bytes as can be written in the first write. */ configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength ); 8015c46: 6a7a ldr r2, [r7, #36] @ 0x24 8015c48: 6a3b ldr r3, [r7, #32] 8015c4a: 441a add r2, r3 8015c4c: 68fb ldr r3, [r7, #12] 8015c4e: 689b ldr r3, [r3, #8] 8015c50: 429a cmp r2, r3 8015c52: d90b bls.n 8015c6c __asm volatile 8015c54: f04f 0350 mov.w r3, #80 @ 0x50 8015c58: f383 8811 msr BASEPRI, r3 8015c5c: f3bf 8f6f isb sy 8015c60: f3bf 8f4f dsb sy 8015c64: 61bb str r3, [r7, #24] } 8015c66: bf00 nop 8015c68: bf00 nop 8015c6a: e7fd b.n 8015c68 ( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 8015c6c: 68fb ldr r3, [r7, #12] 8015c6e: 699a ldr r2, [r3, #24] 8015c70: 6a7b ldr r3, [r7, #36] @ 0x24 8015c72: 4413 add r3, r2 8015c74: 6a3a ldr r2, [r7, #32] 8015c76: 68b9 ldr r1, [r7, #8] 8015c78: 4618 mov r0, r3 8015c7a: f002 fc17 bl 80184ac /* If the number of bytes written was less than the number that could be written in the first write... */ if( xCount > xFirstLength ) 8015c7e: 687a ldr r2, [r7, #4] 8015c80: 6a3b ldr r3, [r7, #32] 8015c82: 429a cmp r2, r3 8015c84: d91d bls.n 8015cc2 { /* ...then write the remaining bytes to the start of the buffer. */ configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength ); 8015c86: 687a ldr r2, [r7, #4] 8015c88: 6a3b ldr r3, [r7, #32] 8015c8a: 1ad2 subs r2, r2, r3 8015c8c: 68fb ldr r3, [r7, #12] 8015c8e: 689b ldr r3, [r3, #8] 8015c90: 429a cmp r2, r3 8015c92: d90b bls.n 8015cac __asm volatile 8015c94: f04f 0350 mov.w r3, #80 @ 0x50 8015c98: f383 8811 msr BASEPRI, r3 8015c9c: f3bf 8f6f isb sy 8015ca0: f3bf 8f4f dsb sy 8015ca4: 617b str r3, [r7, #20] } 8015ca6: bf00 nop 8015ca8: bf00 nop 8015caa: e7fd b.n 8015ca8 ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 8015cac: 68fb ldr r3, [r7, #12] 8015cae: 6998 ldr r0, [r3, #24] 8015cb0: 68ba ldr r2, [r7, #8] 8015cb2: 6a3b ldr r3, [r7, #32] 8015cb4: 18d1 adds r1, r2, r3 8015cb6: 687a ldr r2, [r7, #4] 8015cb8: 6a3b ldr r3, [r7, #32] 8015cba: 1ad3 subs r3, r2, r3 8015cbc: 461a mov r2, r3 8015cbe: f002 fbf5 bl 80184ac else { mtCOVERAGE_TEST_MARKER(); } xNextHead += xCount; 8015cc2: 6a7a ldr r2, [r7, #36] @ 0x24 8015cc4: 687b ldr r3, [r7, #4] 8015cc6: 4413 add r3, r2 8015cc8: 627b str r3, [r7, #36] @ 0x24 if( xNextHead >= pxStreamBuffer->xLength ) 8015cca: 68fb ldr r3, [r7, #12] 8015ccc: 689b ldr r3, [r3, #8] 8015cce: 6a7a ldr r2, [r7, #36] @ 0x24 8015cd0: 429a cmp r2, r3 8015cd2: d304 bcc.n 8015cde { xNextHead -= pxStreamBuffer->xLength; 8015cd4: 68fb ldr r3, [r7, #12] 8015cd6: 689b ldr r3, [r3, #8] 8015cd8: 6a7a ldr r2, [r7, #36] @ 0x24 8015cda: 1ad3 subs r3, r2, r3 8015cdc: 627b str r3, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } pxStreamBuffer->xHead = xNextHead; 8015cde: 68fb ldr r3, [r7, #12] 8015ce0: 6a7a ldr r2, [r7, #36] @ 0x24 8015ce2: 605a str r2, [r3, #4] return xCount; 8015ce4: 687b ldr r3, [r7, #4] } 8015ce6: 4618 mov r0, r3 8015ce8: 3728 adds r7, #40 @ 0x28 8015cea: 46bd mov sp, r7 8015cec: bd80 pop {r7, pc} 08015cee : return xCount; } /*-----------------------------------------------------------*/ static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) { 8015cee: b480 push {r7} 8015cf0: b085 sub sp, #20 8015cf2: af00 add r7, sp, #0 8015cf4: 6078 str r0, [r7, #4] /* Returns the distance between xTail and xHead. */ size_t xCount; xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead; 8015cf6: 687b ldr r3, [r7, #4] 8015cf8: 689a ldr r2, [r3, #8] 8015cfa: 687b ldr r3, [r7, #4] 8015cfc: 685b ldr r3, [r3, #4] 8015cfe: 4413 add r3, r2 8015d00: 60fb str r3, [r7, #12] xCount -= pxStreamBuffer->xTail; 8015d02: 687b ldr r3, [r7, #4] 8015d04: 681b ldr r3, [r3, #0] 8015d06: 68fa ldr r2, [r7, #12] 8015d08: 1ad3 subs r3, r2, r3 8015d0a: 60fb str r3, [r7, #12] if ( xCount >= pxStreamBuffer->xLength ) 8015d0c: 687b ldr r3, [r7, #4] 8015d0e: 689b ldr r3, [r3, #8] 8015d10: 68fa ldr r2, [r7, #12] 8015d12: 429a cmp r2, r3 8015d14: d304 bcc.n 8015d20 { xCount -= pxStreamBuffer->xLength; 8015d16: 687b ldr r3, [r7, #4] 8015d18: 689b ldr r3, [r3, #8] 8015d1a: 68fa ldr r2, [r7, #12] 8015d1c: 1ad3 subs r3, r2, r3 8015d1e: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xCount; 8015d20: 68fb ldr r3, [r7, #12] } 8015d22: 4618 mov r0, r3 8015d24: 3714 adds r7, #20 8015d26: 46bd mov sp, r7 8015d28: f85d 7b04 ldr.w r7, [sp], #4 8015d2c: 4770 bx lr 08015d2e : const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) { 8015d2e: b580 push {r7, lr} 8015d30: b08e sub sp, #56 @ 0x38 8015d32: af04 add r7, sp, #16 8015d34: 60f8 str r0, [r7, #12] 8015d36: 60b9 str r1, [r7, #8] 8015d38: 607a str r2, [r7, #4] 8015d3a: 603b str r3, [r7, #0] TCB_t *pxNewTCB; TaskHandle_t xReturn; configASSERT( puxStackBuffer != NULL ); 8015d3c: 6b7b ldr r3, [r7, #52] @ 0x34 8015d3e: 2b00 cmp r3, #0 8015d40: d10b bne.n 8015d5a __asm volatile 8015d42: f04f 0350 mov.w r3, #80 @ 0x50 8015d46: f383 8811 msr BASEPRI, r3 8015d4a: f3bf 8f6f isb sy 8015d4e: f3bf 8f4f dsb sy 8015d52: 623b str r3, [r7, #32] } 8015d54: bf00 nop 8015d56: bf00 nop 8015d58: e7fd b.n 8015d56 configASSERT( pxTaskBuffer != NULL ); 8015d5a: 6bbb ldr r3, [r7, #56] @ 0x38 8015d5c: 2b00 cmp r3, #0 8015d5e: d10b bne.n 8015d78 __asm volatile 8015d60: f04f 0350 mov.w r3, #80 @ 0x50 8015d64: f383 8811 msr BASEPRI, r3 8015d68: f3bf 8f6f isb sy 8015d6c: f3bf 8f4f dsb sy 8015d70: 61fb str r3, [r7, #28] } 8015d72: bf00 nop 8015d74: bf00 nop 8015d76: e7fd b.n 8015d74 #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTask_t equals the size of the real task structure. */ volatile size_t xSize = sizeof( StaticTask_t ); 8015d78: 23a8 movs r3, #168 @ 0xa8 8015d7a: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( TCB_t ) ); 8015d7c: 693b ldr r3, [r7, #16] 8015d7e: 2ba8 cmp r3, #168 @ 0xa8 8015d80: d00b beq.n 8015d9a __asm volatile 8015d82: f04f 0350 mov.w r3, #80 @ 0x50 8015d86: f383 8811 msr BASEPRI, r3 8015d8a: f3bf 8f6f isb sy 8015d8e: f3bf 8f4f dsb sy 8015d92: 61bb str r3, [r7, #24] } 8015d94: bf00 nop 8015d96: bf00 nop 8015d98: e7fd b.n 8015d96 ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ 8015d9a: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) 8015d9c: 6bbb ldr r3, [r7, #56] @ 0x38 8015d9e: 2b00 cmp r3, #0 8015da0: d01e beq.n 8015de0 8015da2: 6b7b ldr r3, [r7, #52] @ 0x34 8015da4: 2b00 cmp r3, #0 8015da6: d01b beq.n 8015de0 { /* The memory used for the task's TCB and stack are passed into this function - use them. */ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8015da8: 6bbb ldr r3, [r7, #56] @ 0x38 8015daa: 627b str r3, [r7, #36] @ 0x24 pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; 8015dac: 6a7b ldr r3, [r7, #36] @ 0x24 8015dae: 6b7a ldr r2, [r7, #52] @ 0x34 8015db0: 631a str r2, [r3, #48] @ 0x30 #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created statically in case the task is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; 8015db2: 6a7b ldr r3, [r7, #36] @ 0x24 8015db4: 2202 movs r2, #2 8015db6: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 8015dba: 2300 movs r3, #0 8015dbc: 9303 str r3, [sp, #12] 8015dbe: 6a7b ldr r3, [r7, #36] @ 0x24 8015dc0: 9302 str r3, [sp, #8] 8015dc2: f107 0314 add.w r3, r7, #20 8015dc6: 9301 str r3, [sp, #4] 8015dc8: 6b3b ldr r3, [r7, #48] @ 0x30 8015dca: 9300 str r3, [sp, #0] 8015dcc: 683b ldr r3, [r7, #0] 8015dce: 687a ldr r2, [r7, #4] 8015dd0: 68b9 ldr r1, [r7, #8] 8015dd2: 68f8 ldr r0, [r7, #12] 8015dd4: f000 f850 bl 8015e78 prvAddNewTaskToReadyList( pxNewTCB ); 8015dd8: 6a78 ldr r0, [r7, #36] @ 0x24 8015dda: f000 f8f5 bl 8015fc8 8015dde: e001 b.n 8015de4 } else { xReturn = NULL; 8015de0: 2300 movs r3, #0 8015de2: 617b str r3, [r7, #20] } return xReturn; 8015de4: 697b ldr r3, [r7, #20] } 8015de6: 4618 mov r0, r3 8015de8: 3728 adds r7, #40 @ 0x28 8015dea: 46bd mov sp, r7 8015dec: bd80 pop {r7, pc} 08015dee : const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const configSTACK_DEPTH_TYPE usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) { 8015dee: b580 push {r7, lr} 8015df0: b08c sub sp, #48 @ 0x30 8015df2: af04 add r7, sp, #16 8015df4: 60f8 str r0, [r7, #12] 8015df6: 60b9 str r1, [r7, #8] 8015df8: 603b str r3, [r7, #0] 8015dfa: 4613 mov r3, r2 8015dfc: 80fb strh r3, [r7, #6] #else /* portSTACK_GROWTH */ { StackType_t *pxStack; /* Allocate space for the stack used by the task being created. */ pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ 8015dfe: 88fb ldrh r3, [r7, #6] 8015e00: 009b lsls r3, r3, #2 8015e02: 4618 mov r0, r3 8015e04: f002 f8da bl 8017fbc 8015e08: 6178 str r0, [r7, #20] if( pxStack != NULL ) 8015e0a: 697b ldr r3, [r7, #20] 8015e0c: 2b00 cmp r3, #0 8015e0e: d00e beq.n 8015e2e { /* Allocate space for the TCB. */ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ 8015e10: 20a8 movs r0, #168 @ 0xa8 8015e12: f002 f8d3 bl 8017fbc 8015e16: 61f8 str r0, [r7, #28] if( pxNewTCB != NULL ) 8015e18: 69fb ldr r3, [r7, #28] 8015e1a: 2b00 cmp r3, #0 8015e1c: d003 beq.n 8015e26 { /* Store the stack location in the TCB. */ pxNewTCB->pxStack = pxStack; 8015e1e: 69fb ldr r3, [r7, #28] 8015e20: 697a ldr r2, [r7, #20] 8015e22: 631a str r2, [r3, #48] @ 0x30 8015e24: e005 b.n 8015e32 } else { /* The stack cannot be used as the TCB was not created. Free it again. */ vPortFree( pxStack ); 8015e26: 6978 ldr r0, [r7, #20] 8015e28: f002 f996 bl 8018158 8015e2c: e001 b.n 8015e32 } } else { pxNewTCB = NULL; 8015e2e: 2300 movs r3, #0 8015e30: 61fb str r3, [r7, #28] } } #endif /* portSTACK_GROWTH */ if( pxNewTCB != NULL ) 8015e32: 69fb ldr r3, [r7, #28] 8015e34: 2b00 cmp r3, #0 8015e36: d017 beq.n 8015e68 { #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; 8015e38: 69fb ldr r3, [r7, #28] 8015e3a: 2200 movs r2, #0 8015e3c: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); 8015e40: 88fa ldrh r2, [r7, #6] 8015e42: 2300 movs r3, #0 8015e44: 9303 str r3, [sp, #12] 8015e46: 69fb ldr r3, [r7, #28] 8015e48: 9302 str r3, [sp, #8] 8015e4a: 6afb ldr r3, [r7, #44] @ 0x2c 8015e4c: 9301 str r3, [sp, #4] 8015e4e: 6abb ldr r3, [r7, #40] @ 0x28 8015e50: 9300 str r3, [sp, #0] 8015e52: 683b ldr r3, [r7, #0] 8015e54: 68b9 ldr r1, [r7, #8] 8015e56: 68f8 ldr r0, [r7, #12] 8015e58: f000 f80e bl 8015e78 prvAddNewTaskToReadyList( pxNewTCB ); 8015e5c: 69f8 ldr r0, [r7, #28] 8015e5e: f000 f8b3 bl 8015fc8 xReturn = pdPASS; 8015e62: 2301 movs r3, #1 8015e64: 61bb str r3, [r7, #24] 8015e66: e002 b.n 8015e6e } else { xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; 8015e68: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8015e6c: 61bb str r3, [r7, #24] } return xReturn; 8015e6e: 69bb ldr r3, [r7, #24] } 8015e70: 4618 mov r0, r3 8015e72: 3720 adds r7, #32 8015e74: 46bd mov sp, r7 8015e76: bd80 pop {r7, pc} 08015e78 : void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, TCB_t *pxNewTCB, const MemoryRegion_t * const xRegions ) { 8015e78: b580 push {r7, lr} 8015e7a: b088 sub sp, #32 8015e7c: af00 add r7, sp, #0 8015e7e: 60f8 str r0, [r7, #12] 8015e80: 60b9 str r1, [r7, #8] 8015e82: 607a str r2, [r7, #4] 8015e84: 603b str r3, [r7, #0] /* Avoid dependency on memset() if it is not required. */ #if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) { /* Fill the stack with a known value to assist debugging. */ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); 8015e86: 6b3b ldr r3, [r7, #48] @ 0x30 8015e88: 6b18 ldr r0, [r3, #48] @ 0x30 8015e8a: 687b ldr r3, [r7, #4] 8015e8c: 009b lsls r3, r3, #2 8015e8e: 461a mov r2, r3 8015e90: 21a5 movs r1, #165 @ 0xa5 8015e92: f002 fa81 bl 8018398 grows from high memory to low (as per the 80x86) or vice versa. portSTACK_GROWTH is used to make the result positive or negative as required by the port. */ #if( portSTACK_GROWTH < 0 ) { pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); 8015e96: 6b3b ldr r3, [r7, #48] @ 0x30 8015e98: 6b1a ldr r2, [r3, #48] @ 0x30 8015e9a: 6879 ldr r1, [r7, #4] 8015e9c: f06f 4340 mvn.w r3, #3221225472 @ 0xc0000000 8015ea0: 440b add r3, r1 8015ea2: 009b lsls r3, r3, #2 8015ea4: 4413 add r3, r2 8015ea6: 61bb str r3, [r7, #24] pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ 8015ea8: 69bb ldr r3, [r7, #24] 8015eaa: f023 0307 bic.w r3, r3, #7 8015eae: 61bb str r3, [r7, #24] /* Check the alignment of the calculated top of stack is correct. */ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); 8015eb0: 69bb ldr r3, [r7, #24] 8015eb2: f003 0307 and.w r3, r3, #7 8015eb6: 2b00 cmp r3, #0 8015eb8: d00b beq.n 8015ed2 __asm volatile 8015eba: f04f 0350 mov.w r3, #80 @ 0x50 8015ebe: f383 8811 msr BASEPRI, r3 8015ec2: f3bf 8f6f isb sy 8015ec6: f3bf 8f4f dsb sy 8015eca: 617b str r3, [r7, #20] } 8015ecc: bf00 nop 8015ece: bf00 nop 8015ed0: e7fd b.n 8015ece pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); } #endif /* portSTACK_GROWTH */ /* Store the task name in the TCB. */ if( pcName != NULL ) 8015ed2: 68bb ldr r3, [r7, #8] 8015ed4: 2b00 cmp r3, #0 8015ed6: d01f beq.n 8015f18 { for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8015ed8: 2300 movs r3, #0 8015eda: 61fb str r3, [r7, #28] 8015edc: e012 b.n 8015f04 { pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 8015ede: 68ba ldr r2, [r7, #8] 8015ee0: 69fb ldr r3, [r7, #28] 8015ee2: 4413 add r3, r2 8015ee4: 7819 ldrb r1, [r3, #0] 8015ee6: 6b3a ldr r2, [r7, #48] @ 0x30 8015ee8: 69fb ldr r3, [r7, #28] 8015eea: 4413 add r3, r2 8015eec: 3334 adds r3, #52 @ 0x34 8015eee: 460a mov r2, r1 8015ef0: 701a strb r2, [r3, #0] /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than configMAX_TASK_NAME_LEN characters just in case the memory after the string is not accessible (extremely unlikely). */ if( pcName[ x ] == ( char ) 0x00 ) 8015ef2: 68ba ldr r2, [r7, #8] 8015ef4: 69fb ldr r3, [r7, #28] 8015ef6: 4413 add r3, r2 8015ef8: 781b ldrb r3, [r3, #0] 8015efa: 2b00 cmp r3, #0 8015efc: d006 beq.n 8015f0c for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8015efe: 69fb ldr r3, [r7, #28] 8015f00: 3301 adds r3, #1 8015f02: 61fb str r3, [r7, #28] 8015f04: 69fb ldr r3, [r7, #28] 8015f06: 2b0f cmp r3, #15 8015f08: d9e9 bls.n 8015ede 8015f0a: e000 b.n 8015f0e { break; 8015f0c: bf00 nop } } /* Ensure the name string is terminated in the case that the string length was greater or equal to configMAX_TASK_NAME_LEN. */ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; 8015f0e: 6b3b ldr r3, [r7, #48] @ 0x30 8015f10: 2200 movs r2, #0 8015f12: f883 2043 strb.w r2, [r3, #67] @ 0x43 8015f16: e003 b.n 8015f20 } else { /* The task has not been given a name, so just ensure there is a NULL terminator when it is read out. */ pxNewTCB->pcTaskName[ 0 ] = 0x00; 8015f18: 6b3b ldr r3, [r7, #48] @ 0x30 8015f1a: 2200 movs r2, #0 8015f1c: f883 2034 strb.w r2, [r3, #52] @ 0x34 } /* This is used as an array index so must ensure it's not too large. First remove the privilege bit if one is present. */ if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) 8015f20: 6abb ldr r3, [r7, #40] @ 0x28 8015f22: 2b37 cmp r3, #55 @ 0x37 8015f24: d901 bls.n 8015f2a { uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; 8015f26: 2337 movs r3, #55 @ 0x37 8015f28: 62bb str r3, [r7, #40] @ 0x28 else { mtCOVERAGE_TEST_MARKER(); } pxNewTCB->uxPriority = uxPriority; 8015f2a: 6b3b ldr r3, [r7, #48] @ 0x30 8015f2c: 6aba ldr r2, [r7, #40] @ 0x28 8015f2e: 62da str r2, [r3, #44] @ 0x2c #if ( configUSE_MUTEXES == 1 ) { pxNewTCB->uxBasePriority = uxPriority; 8015f30: 6b3b ldr r3, [r7, #48] @ 0x30 8015f32: 6aba ldr r2, [r7, #40] @ 0x28 8015f34: 64da str r2, [r3, #76] @ 0x4c pxNewTCB->uxMutexesHeld = 0; 8015f36: 6b3b ldr r3, [r7, #48] @ 0x30 8015f38: 2200 movs r2, #0 8015f3a: 651a str r2, [r3, #80] @ 0x50 } #endif /* configUSE_MUTEXES */ vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); 8015f3c: 6b3b ldr r3, [r7, #48] @ 0x30 8015f3e: 3304 adds r3, #4 8015f40: 4618 mov r0, r3 8015f42: f7fe fd09 bl 8014958 vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); 8015f46: 6b3b ldr r3, [r7, #48] @ 0x30 8015f48: 3318 adds r3, #24 8015f4a: 4618 mov r0, r3 8015f4c: f7fe fd04 bl 8014958 /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get back to the containing TCB from a generic item in a list. */ listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); 8015f50: 6b3b ldr r3, [r7, #48] @ 0x30 8015f52: 6b3a ldr r2, [r7, #48] @ 0x30 8015f54: 611a str r2, [r3, #16] /* Event lists are always in priority order. */ listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8015f56: 6abb ldr r3, [r7, #40] @ 0x28 8015f58: f1c3 0238 rsb r2, r3, #56 @ 0x38 8015f5c: 6b3b ldr r3, [r7, #48] @ 0x30 8015f5e: 619a str r2, [r3, #24] listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); 8015f60: 6b3b ldr r3, [r7, #48] @ 0x30 8015f62: 6b3a ldr r2, [r7, #48] @ 0x30 8015f64: 625a str r2, [r3, #36] @ 0x24 } #endif #if ( configUSE_TASK_NOTIFICATIONS == 1 ) { pxNewTCB->ulNotifiedValue = 0; 8015f66: 6b3b ldr r3, [r7, #48] @ 0x30 8015f68: 2200 movs r2, #0 8015f6a: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8015f6e: 6b3b ldr r3, [r7, #48] @ 0x30 8015f70: 2200 movs r2, #0 8015f72: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 #if ( configUSE_NEWLIB_REENTRANT == 1 ) { /* Initialise this task's Newlib reent structure. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); 8015f76: 6b3b ldr r3, [r7, #48] @ 0x30 8015f78: 3354 adds r3, #84 @ 0x54 8015f7a: 224c movs r2, #76 @ 0x4c 8015f7c: 2100 movs r1, #0 8015f7e: 4618 mov r0, r3 8015f80: f002 fa0a bl 8018398 8015f84: 6b3b ldr r3, [r7, #48] @ 0x30 8015f86: 4a0d ldr r2, [pc, #52] @ (8015fbc ) 8015f88: 659a str r2, [r3, #88] @ 0x58 8015f8a: 6b3b ldr r3, [r7, #48] @ 0x30 8015f8c: 4a0c ldr r2, [pc, #48] @ (8015fc0 ) 8015f8e: 65da str r2, [r3, #92] @ 0x5c 8015f90: 6b3b ldr r3, [r7, #48] @ 0x30 8015f92: 4a0c ldr r2, [pc, #48] @ (8015fc4 ) 8015f94: 661a str r2, [r3, #96] @ 0x60 } #endif /* portSTACK_GROWTH */ } #else /* portHAS_STACK_OVERFLOW_CHECKING */ { pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); 8015f96: 683a ldr r2, [r7, #0] 8015f98: 68f9 ldr r1, [r7, #12] 8015f9a: 69b8 ldr r0, [r7, #24] 8015f9c: f001 fdb8 bl 8017b10 8015fa0: 4602 mov r2, r0 8015fa2: 6b3b ldr r3, [r7, #48] @ 0x30 8015fa4: 601a str r2, [r3, #0] } #endif /* portHAS_STACK_OVERFLOW_CHECKING */ } #endif /* portUSING_MPU_WRAPPERS */ if( pxCreatedTask != NULL ) 8015fa6: 6afb ldr r3, [r7, #44] @ 0x2c 8015fa8: 2b00 cmp r3, #0 8015faa: d002 beq.n 8015fb2 { /* Pass the handle out in an anonymous way. The handle can be used to change the created task's priority, delete the created task, etc.*/ *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; 8015fac: 6afb ldr r3, [r7, #44] @ 0x2c 8015fae: 6b3a ldr r2, [r7, #48] @ 0x30 8015fb0: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 8015fb2: bf00 nop 8015fb4: 3720 adds r7, #32 8015fb6: 46bd mov sp, r7 8015fb8: bd80 pop {r7, pc} 8015fba: bf00 nop 8015fbc: 2401304c .word 0x2401304c 8015fc0: 240130b4 .word 0x240130b4 8015fc4: 2401311c .word 0x2401311c 08015fc8 : /*-----------------------------------------------------------*/ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) { 8015fc8: b580 push {r7, lr} 8015fca: b082 sub sp, #8 8015fcc: af00 add r7, sp, #0 8015fce: 6078 str r0, [r7, #4] /* Ensure interrupts don't access the task lists while the lists are being updated. */ taskENTER_CRITICAL(); 8015fd0: f001 fed2 bl 8017d78 { uxCurrentNumberOfTasks++; 8015fd4: 4b2d ldr r3, [pc, #180] @ (801608c ) 8015fd6: 681b ldr r3, [r3, #0] 8015fd8: 3301 adds r3, #1 8015fda: 4a2c ldr r2, [pc, #176] @ (801608c ) 8015fdc: 6013 str r3, [r2, #0] if( pxCurrentTCB == NULL ) 8015fde: 4b2c ldr r3, [pc, #176] @ (8016090 ) 8015fe0: 681b ldr r3, [r3, #0] 8015fe2: 2b00 cmp r3, #0 8015fe4: d109 bne.n 8015ffa { /* There are no other tasks, or all the other tasks are in the suspended state - make this the current task. */ pxCurrentTCB = pxNewTCB; 8015fe6: 4a2a ldr r2, [pc, #168] @ (8016090 ) 8015fe8: 687b ldr r3, [r7, #4] 8015fea: 6013 str r3, [r2, #0] if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) 8015fec: 4b27 ldr r3, [pc, #156] @ (801608c ) 8015fee: 681b ldr r3, [r3, #0] 8015ff0: 2b01 cmp r3, #1 8015ff2: d110 bne.n 8016016 { /* This is the first task to be created so do the preliminary initialisation required. We will not recover if this call fails, but we will report the failure. */ prvInitialiseTaskLists(); 8015ff4: f000 fc64 bl 80168c0 8015ff8: e00d b.n 8016016 else { /* If the scheduler is not already running, make this task the current task if it is the highest priority task to be created so far. */ if( xSchedulerRunning == pdFALSE ) 8015ffa: 4b26 ldr r3, [pc, #152] @ (8016094 ) 8015ffc: 681b ldr r3, [r3, #0] 8015ffe: 2b00 cmp r3, #0 8016000: d109 bne.n 8016016 { if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) 8016002: 4b23 ldr r3, [pc, #140] @ (8016090 ) 8016004: 681b ldr r3, [r3, #0] 8016006: 6ada ldr r2, [r3, #44] @ 0x2c 8016008: 687b ldr r3, [r7, #4] 801600a: 6adb ldr r3, [r3, #44] @ 0x2c 801600c: 429a cmp r2, r3 801600e: d802 bhi.n 8016016 { pxCurrentTCB = pxNewTCB; 8016010: 4a1f ldr r2, [pc, #124] @ (8016090 ) 8016012: 687b ldr r3, [r7, #4] 8016014: 6013 str r3, [r2, #0] { mtCOVERAGE_TEST_MARKER(); } } uxTaskNumber++; 8016016: 4b20 ldr r3, [pc, #128] @ (8016098 ) 8016018: 681b ldr r3, [r3, #0] 801601a: 3301 adds r3, #1 801601c: 4a1e ldr r2, [pc, #120] @ (8016098 ) 801601e: 6013 str r3, [r2, #0] #if ( configUSE_TRACE_FACILITY == 1 ) { /* Add a counter into the TCB for tracing only. */ pxNewTCB->uxTCBNumber = uxTaskNumber; 8016020: 4b1d ldr r3, [pc, #116] @ (8016098 ) 8016022: 681a ldr r2, [r3, #0] 8016024: 687b ldr r3, [r7, #4] 8016026: 645a str r2, [r3, #68] @ 0x44 } #endif /* configUSE_TRACE_FACILITY */ traceTASK_CREATE( pxNewTCB ); prvAddTaskToReadyList( pxNewTCB ); 8016028: 687b ldr r3, [r7, #4] 801602a: 6ada ldr r2, [r3, #44] @ 0x2c 801602c: 4b1b ldr r3, [pc, #108] @ (801609c ) 801602e: 681b ldr r3, [r3, #0] 8016030: 429a cmp r2, r3 8016032: d903 bls.n 801603c 8016034: 687b ldr r3, [r7, #4] 8016036: 6adb ldr r3, [r3, #44] @ 0x2c 8016038: 4a18 ldr r2, [pc, #96] @ (801609c ) 801603a: 6013 str r3, [r2, #0] 801603c: 687b ldr r3, [r7, #4] 801603e: 6ada ldr r2, [r3, #44] @ 0x2c 8016040: 4613 mov r3, r2 8016042: 009b lsls r3, r3, #2 8016044: 4413 add r3, r2 8016046: 009b lsls r3, r3, #2 8016048: 4a15 ldr r2, [pc, #84] @ (80160a0 ) 801604a: 441a add r2, r3 801604c: 687b ldr r3, [r7, #4] 801604e: 3304 adds r3, #4 8016050: 4619 mov r1, r3 8016052: 4610 mov r0, r2 8016054: f7fe fc8d bl 8014972 portSETUP_TCB( pxNewTCB ); } taskEXIT_CRITICAL(); 8016058: f001 fec0 bl 8017ddc if( xSchedulerRunning != pdFALSE ) 801605c: 4b0d ldr r3, [pc, #52] @ (8016094 ) 801605e: 681b ldr r3, [r3, #0] 8016060: 2b00 cmp r3, #0 8016062: d00e beq.n 8016082 { /* If the created task is of a higher priority than the current task then it should run now. */ if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) 8016064: 4b0a ldr r3, [pc, #40] @ (8016090 ) 8016066: 681b ldr r3, [r3, #0] 8016068: 6ada ldr r2, [r3, #44] @ 0x2c 801606a: 687b ldr r3, [r7, #4] 801606c: 6adb ldr r3, [r3, #44] @ 0x2c 801606e: 429a cmp r2, r3 8016070: d207 bcs.n 8016082 { taskYIELD_IF_USING_PREEMPTION(); 8016072: 4b0c ldr r3, [pc, #48] @ (80160a4 ) 8016074: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016078: 601a str r2, [r3, #0] 801607a: f3bf 8f4f dsb sy 801607e: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 8016082: bf00 nop 8016084: 3708 adds r7, #8 8016086: 46bd mov sp, r7 8016088: bd80 pop {r7, pc} 801608a: bf00 nop 801608c: 24002ecc .word 0x24002ecc 8016090: 240029f8 .word 0x240029f8 8016094: 24002ed8 .word 0x24002ed8 8016098: 24002ee8 .word 0x24002ee8 801609c: 24002ed4 .word 0x24002ed4 80160a0: 240029fc .word 0x240029fc 80160a4: e000ed04 .word 0xe000ed04 080160a8 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelay == 1 ) void vTaskDelay( const TickType_t xTicksToDelay ) { 80160a8: b580 push {r7, lr} 80160aa: b084 sub sp, #16 80160ac: af00 add r7, sp, #0 80160ae: 6078 str r0, [r7, #4] BaseType_t xAlreadyYielded = pdFALSE; 80160b0: 2300 movs r3, #0 80160b2: 60fb str r3, [r7, #12] /* A delay time of zero just forces a reschedule. */ if( xTicksToDelay > ( TickType_t ) 0U ) 80160b4: 687b ldr r3, [r7, #4] 80160b6: 2b00 cmp r3, #0 80160b8: d018 beq.n 80160ec { configASSERT( uxSchedulerSuspended == 0 ); 80160ba: 4b14 ldr r3, [pc, #80] @ (801610c ) 80160bc: 681b ldr r3, [r3, #0] 80160be: 2b00 cmp r3, #0 80160c0: d00b beq.n 80160da __asm volatile 80160c2: f04f 0350 mov.w r3, #80 @ 0x50 80160c6: f383 8811 msr BASEPRI, r3 80160ca: f3bf 8f6f isb sy 80160ce: f3bf 8f4f dsb sy 80160d2: 60bb str r3, [r7, #8] } 80160d4: bf00 nop 80160d6: bf00 nop 80160d8: e7fd b.n 80160d6 vTaskSuspendAll(); 80160da: f000 f88b bl 80161f4 list or removed from the blocked list until the scheduler is resumed. This task cannot be in an event list as it is the currently executing task. */ prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); 80160de: 2100 movs r1, #0 80160e0: 6878 ldr r0, [r7, #4] 80160e2: f001 f87d bl 80171e0 } xAlreadyYielded = xTaskResumeAll(); 80160e6: f000 f893 bl 8016210 80160ea: 60f8 str r0, [r7, #12] mtCOVERAGE_TEST_MARKER(); } /* Force a reschedule if xTaskResumeAll has not already done so, we may have put ourselves to sleep. */ if( xAlreadyYielded == pdFALSE ) 80160ec: 68fb ldr r3, [r7, #12] 80160ee: 2b00 cmp r3, #0 80160f0: d107 bne.n 8016102 { portYIELD_WITHIN_API(); 80160f2: 4b07 ldr r3, [pc, #28] @ (8016110 ) 80160f4: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80160f8: 601a str r2, [r3, #0] 80160fa: f3bf 8f4f dsb sy 80160fe: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 8016102: bf00 nop 8016104: 3710 adds r7, #16 8016106: 46bd mov sp, r7 8016108: bd80 pop {r7, pc} 801610a: bf00 nop 801610c: 24002ef4 .word 0x24002ef4 8016110: e000ed04 .word 0xe000ed04 08016114 : #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ /*-----------------------------------------------------------*/ void vTaskStartScheduler( void ) { 8016114: b580 push {r7, lr} 8016116: b08a sub sp, #40 @ 0x28 8016118: af04 add r7, sp, #16 BaseType_t xReturn; /* Add the idle task at the lowest priority. */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxIdleTaskTCBBuffer = NULL; 801611a: 2300 movs r3, #0 801611c: 60bb str r3, [r7, #8] StackType_t *pxIdleTaskStackBuffer = NULL; 801611e: 2300 movs r3, #0 8016120: 607b str r3, [r7, #4] uint32_t ulIdleTaskStackSize; /* The Idle task is created using user provided RAM - obtain the address of the RAM then create the idle task. */ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); 8016122: 463a mov r2, r7 8016124: 1d39 adds r1, r7, #4 8016126: f107 0308 add.w r3, r7, #8 801612a: 4618 mov r0, r3 801612c: f7fe fbc0 bl 80148b0 xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, 8016130: 6839 ldr r1, [r7, #0] 8016132: 687b ldr r3, [r7, #4] 8016134: 68ba ldr r2, [r7, #8] 8016136: 9202 str r2, [sp, #8] 8016138: 9301 str r3, [sp, #4] 801613a: 2300 movs r3, #0 801613c: 9300 str r3, [sp, #0] 801613e: 2300 movs r3, #0 8016140: 460a mov r2, r1 8016142: 4924 ldr r1, [pc, #144] @ (80161d4 ) 8016144: 4824 ldr r0, [pc, #144] @ (80161d8 ) 8016146: f7ff fdf2 bl 8015d2e 801614a: 4603 mov r3, r0 801614c: 4a23 ldr r2, [pc, #140] @ (80161dc ) 801614e: 6013 str r3, [r2, #0] ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ pxIdleTaskStackBuffer, pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ if( xIdleTaskHandle != NULL ) 8016150: 4b22 ldr r3, [pc, #136] @ (80161dc ) 8016152: 681b ldr r3, [r3, #0] 8016154: 2b00 cmp r3, #0 8016156: d002 beq.n 801615e { xReturn = pdPASS; 8016158: 2301 movs r3, #1 801615a: 617b str r3, [r7, #20] 801615c: e001 b.n 8016162 } else { xReturn = pdFAIL; 801615e: 2300 movs r3, #0 8016160: 617b str r3, [r7, #20] } #endif /* configSUPPORT_STATIC_ALLOCATION */ #if ( configUSE_TIMERS == 1 ) { if( xReturn == pdPASS ) 8016162: 697b ldr r3, [r7, #20] 8016164: 2b01 cmp r3, #1 8016166: d102 bne.n 801616e { xReturn = xTimerCreateTimerTask(); 8016168: f001 f88e bl 8017288 801616c: 6178 str r0, [r7, #20] mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_TIMERS */ if( xReturn == pdPASS ) 801616e: 697b ldr r3, [r7, #20] 8016170: 2b01 cmp r3, #1 8016172: d11b bne.n 80161ac __asm volatile 8016174: f04f 0350 mov.w r3, #80 @ 0x50 8016178: f383 8811 msr BASEPRI, r3 801617c: f3bf 8f6f isb sy 8016180: f3bf 8f4f dsb sy 8016184: 613b str r3, [r7, #16] } 8016186: bf00 nop { /* Switch Newlib's _impure_ptr variable to point to the _reent structure specific to the task that will run first. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 8016188: 4b15 ldr r3, [pc, #84] @ (80161e0 ) 801618a: 681b ldr r3, [r3, #0] 801618c: 3354 adds r3, #84 @ 0x54 801618e: 4a15 ldr r2, [pc, #84] @ (80161e4 ) 8016190: 6013 str r3, [r2, #0] } #endif /* configUSE_NEWLIB_REENTRANT */ xNextTaskUnblockTime = portMAX_DELAY; 8016192: 4b15 ldr r3, [pc, #84] @ (80161e8 ) 8016194: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8016198: 601a str r2, [r3, #0] xSchedulerRunning = pdTRUE; 801619a: 4b14 ldr r3, [pc, #80] @ (80161ec ) 801619c: 2201 movs r2, #1 801619e: 601a str r2, [r3, #0] xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; 80161a0: 4b13 ldr r3, [pc, #76] @ (80161f0 ) 80161a2: 2200 movs r2, #0 80161a4: 601a str r2, [r3, #0] traceTASK_SWITCHED_IN(); /* Setting up the timer tick is hardware specific and thus in the portable interface. */ if( xPortStartScheduler() != pdFALSE ) 80161a6: f001 fd43 bl 8017c30 } /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, meaning xIdleTaskHandle is not used anywhere else. */ ( void ) xIdleTaskHandle; } 80161aa: e00f b.n 80161cc configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); 80161ac: 697b ldr r3, [r7, #20] 80161ae: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80161b2: d10b bne.n 80161cc __asm volatile 80161b4: f04f 0350 mov.w r3, #80 @ 0x50 80161b8: f383 8811 msr BASEPRI, r3 80161bc: f3bf 8f6f isb sy 80161c0: f3bf 8f4f dsb sy 80161c4: 60fb str r3, [r7, #12] } 80161c6: bf00 nop 80161c8: bf00 nop 80161ca: e7fd b.n 80161c8 } 80161cc: bf00 nop 80161ce: 3718 adds r7, #24 80161d0: 46bd mov sp, r7 80161d2: bd80 pop {r7, pc} 80161d4: 08018710 .word 0x08018710 80161d8: 08016891 .word 0x08016891 80161dc: 24002ef0 .word 0x24002ef0 80161e0: 240029f8 .word 0x240029f8 80161e4: 24000048 .word 0x24000048 80161e8: 24002eec .word 0x24002eec 80161ec: 24002ed8 .word 0x24002ed8 80161f0: 24002ed0 .word 0x24002ed0 080161f4 : vPortEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { 80161f4: b480 push {r7} 80161f6: af00 add r7, sp, #0 do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER(); /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; 80161f8: 4b04 ldr r3, [pc, #16] @ (801620c ) 80161fa: 681b ldr r3, [r3, #0] 80161fc: 3301 adds r3, #1 80161fe: 4a03 ldr r2, [pc, #12] @ (801620c ) 8016200: 6013 str r3, [r2, #0] /* Enforces ordering for ports and optimised compilers that may otherwise place the above increment elsewhere. */ portMEMORY_BARRIER(); } 8016202: bf00 nop 8016204: 46bd mov sp, r7 8016206: f85d 7b04 ldr.w r7, [sp], #4 801620a: 4770 bx lr 801620c: 24002ef4 .word 0x24002ef4 08016210 : #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ BaseType_t xTaskResumeAll( void ) { 8016210: b580 push {r7, lr} 8016212: b084 sub sp, #16 8016214: af00 add r7, sp, #0 TCB_t *pxTCB = NULL; 8016216: 2300 movs r3, #0 8016218: 60fb str r3, [r7, #12] BaseType_t xAlreadyYielded = pdFALSE; 801621a: 2300 movs r3, #0 801621c: 60bb str r3, [r7, #8] /* If uxSchedulerSuspended is zero then this function does not match a previous call to vTaskSuspendAll(). */ configASSERT( uxSchedulerSuspended ); 801621e: 4b42 ldr r3, [pc, #264] @ (8016328 ) 8016220: 681b ldr r3, [r3, #0] 8016222: 2b00 cmp r3, #0 8016224: d10b bne.n 801623e __asm volatile 8016226: f04f 0350 mov.w r3, #80 @ 0x50 801622a: f383 8811 msr BASEPRI, r3 801622e: f3bf 8f6f isb sy 8016232: f3bf 8f4f dsb sy 8016236: 603b str r3, [r7, #0] } 8016238: bf00 nop 801623a: bf00 nop 801623c: e7fd b.n 801623a /* It is possible that an ISR caused a task to be removed from an event list while the scheduler was suspended. If this was the case then the removed task will have been added to the xPendingReadyList. Once the scheduler has been resumed it is safe to move all the pending ready tasks from this list into their appropriate ready list. */ taskENTER_CRITICAL(); 801623e: f001 fd9b bl 8017d78 { --uxSchedulerSuspended; 8016242: 4b39 ldr r3, [pc, #228] @ (8016328 ) 8016244: 681b ldr r3, [r3, #0] 8016246: 3b01 subs r3, #1 8016248: 4a37 ldr r2, [pc, #220] @ (8016328 ) 801624a: 6013 str r3, [r2, #0] if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 801624c: 4b36 ldr r3, [pc, #216] @ (8016328 ) 801624e: 681b ldr r3, [r3, #0] 8016250: 2b00 cmp r3, #0 8016252: d162 bne.n 801631a { if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) 8016254: 4b35 ldr r3, [pc, #212] @ (801632c ) 8016256: 681b ldr r3, [r3, #0] 8016258: 2b00 cmp r3, #0 801625a: d05e beq.n 801631a { /* Move any readied tasks from the pending list into the appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 801625c: e02f b.n 80162be { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 801625e: 4b34 ldr r3, [pc, #208] @ (8016330 ) 8016260: 68db ldr r3, [r3, #12] 8016262: 68db ldr r3, [r3, #12] 8016264: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 8016266: 68fb ldr r3, [r7, #12] 8016268: 3318 adds r3, #24 801626a: 4618 mov r0, r3 801626c: f7fe fbde bl 8014a2c ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8016270: 68fb ldr r3, [r7, #12] 8016272: 3304 adds r3, #4 8016274: 4618 mov r0, r3 8016276: f7fe fbd9 bl 8014a2c prvAddTaskToReadyList( pxTCB ); 801627a: 68fb ldr r3, [r7, #12] 801627c: 6ada ldr r2, [r3, #44] @ 0x2c 801627e: 4b2d ldr r3, [pc, #180] @ (8016334 ) 8016280: 681b ldr r3, [r3, #0] 8016282: 429a cmp r2, r3 8016284: d903 bls.n 801628e 8016286: 68fb ldr r3, [r7, #12] 8016288: 6adb ldr r3, [r3, #44] @ 0x2c 801628a: 4a2a ldr r2, [pc, #168] @ (8016334 ) 801628c: 6013 str r3, [r2, #0] 801628e: 68fb ldr r3, [r7, #12] 8016290: 6ada ldr r2, [r3, #44] @ 0x2c 8016292: 4613 mov r3, r2 8016294: 009b lsls r3, r3, #2 8016296: 4413 add r3, r2 8016298: 009b lsls r3, r3, #2 801629a: 4a27 ldr r2, [pc, #156] @ (8016338 ) 801629c: 441a add r2, r3 801629e: 68fb ldr r3, [r7, #12] 80162a0: 3304 adds r3, #4 80162a2: 4619 mov r1, r3 80162a4: 4610 mov r0, r2 80162a6: f7fe fb64 bl 8014972 /* If the moved task has a priority higher than the current task then a yield must be performed. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 80162aa: 68fb ldr r3, [r7, #12] 80162ac: 6ada ldr r2, [r3, #44] @ 0x2c 80162ae: 4b23 ldr r3, [pc, #140] @ (801633c ) 80162b0: 681b ldr r3, [r3, #0] 80162b2: 6adb ldr r3, [r3, #44] @ 0x2c 80162b4: 429a cmp r2, r3 80162b6: d302 bcc.n 80162be { xYieldPending = pdTRUE; 80162b8: 4b21 ldr r3, [pc, #132] @ (8016340 ) 80162ba: 2201 movs r2, #1 80162bc: 601a str r2, [r3, #0] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 80162be: 4b1c ldr r3, [pc, #112] @ (8016330 ) 80162c0: 681b ldr r3, [r3, #0] 80162c2: 2b00 cmp r3, #0 80162c4: d1cb bne.n 801625e { mtCOVERAGE_TEST_MARKER(); } } if( pxTCB != NULL ) 80162c6: 68fb ldr r3, [r7, #12] 80162c8: 2b00 cmp r3, #0 80162ca: d001 beq.n 80162d0 which may have prevented the next unblock time from being re-calculated, in which case re-calculate it now. Mainly important for low power tickless implementations, where this can prevent an unnecessary exit from low power state. */ prvResetNextTaskUnblockTime(); 80162cc: f000 fb9c bl 8016a08 /* If any ticks occurred while the scheduler was suspended then they should be processed now. This ensures the tick count does not slip, and that any delayed tasks are resumed at the correct time. */ { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ 80162d0: 4b1c ldr r3, [pc, #112] @ (8016344 ) 80162d2: 681b ldr r3, [r3, #0] 80162d4: 607b str r3, [r7, #4] if( xPendedCounts > ( TickType_t ) 0U ) 80162d6: 687b ldr r3, [r7, #4] 80162d8: 2b00 cmp r3, #0 80162da: d010 beq.n 80162fe { do { if( xTaskIncrementTick() != pdFALSE ) 80162dc: f000 f846 bl 801636c 80162e0: 4603 mov r3, r0 80162e2: 2b00 cmp r3, #0 80162e4: d002 beq.n 80162ec { xYieldPending = pdTRUE; 80162e6: 4b16 ldr r3, [pc, #88] @ (8016340 ) 80162e8: 2201 movs r2, #1 80162ea: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } --xPendedCounts; 80162ec: 687b ldr r3, [r7, #4] 80162ee: 3b01 subs r3, #1 80162f0: 607b str r3, [r7, #4] } while( xPendedCounts > ( TickType_t ) 0U ); 80162f2: 687b ldr r3, [r7, #4] 80162f4: 2b00 cmp r3, #0 80162f6: d1f1 bne.n 80162dc xPendedTicks = 0; 80162f8: 4b12 ldr r3, [pc, #72] @ (8016344 ) 80162fa: 2200 movs r2, #0 80162fc: 601a str r2, [r3, #0] { mtCOVERAGE_TEST_MARKER(); } } if( xYieldPending != pdFALSE ) 80162fe: 4b10 ldr r3, [pc, #64] @ (8016340 ) 8016300: 681b ldr r3, [r3, #0] 8016302: 2b00 cmp r3, #0 8016304: d009 beq.n 801631a { #if( configUSE_PREEMPTION != 0 ) { xAlreadyYielded = pdTRUE; 8016306: 2301 movs r3, #1 8016308: 60bb str r3, [r7, #8] } #endif taskYIELD_IF_USING_PREEMPTION(); 801630a: 4b0f ldr r3, [pc, #60] @ (8016348 ) 801630c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016310: 601a str r2, [r3, #0] 8016312: f3bf 8f4f dsb sy 8016316: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 801631a: f001 fd5f bl 8017ddc return xAlreadyYielded; 801631e: 68bb ldr r3, [r7, #8] } 8016320: 4618 mov r0, r3 8016322: 3710 adds r7, #16 8016324: 46bd mov sp, r7 8016326: bd80 pop {r7, pc} 8016328: 24002ef4 .word 0x24002ef4 801632c: 24002ecc .word 0x24002ecc 8016330: 24002e8c .word 0x24002e8c 8016334: 24002ed4 .word 0x24002ed4 8016338: 240029fc .word 0x240029fc 801633c: 240029f8 .word 0x240029f8 8016340: 24002ee0 .word 0x24002ee0 8016344: 24002edc .word 0x24002edc 8016348: e000ed04 .word 0xe000ed04 0801634c : /*-----------------------------------------------------------*/ TickType_t xTaskGetTickCount( void ) { 801634c: b480 push {r7} 801634e: b083 sub sp, #12 8016350: af00 add r7, sp, #0 TickType_t xTicks; /* Critical section required if running on a 16 bit processor. */ portTICK_TYPE_ENTER_CRITICAL(); { xTicks = xTickCount; 8016352: 4b05 ldr r3, [pc, #20] @ (8016368 ) 8016354: 681b ldr r3, [r3, #0] 8016356: 607b str r3, [r7, #4] } portTICK_TYPE_EXIT_CRITICAL(); return xTicks; 8016358: 687b ldr r3, [r7, #4] } 801635a: 4618 mov r0, r3 801635c: 370c adds r7, #12 801635e: 46bd mov sp, r7 8016360: f85d 7b04 ldr.w r7, [sp], #4 8016364: 4770 bx lr 8016366: bf00 nop 8016368: 24002ed0 .word 0x24002ed0 0801636c : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { 801636c: b580 push {r7, lr} 801636e: b086 sub sp, #24 8016370: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; 8016372: 2300 movs r3, #0 8016374: 617b str r3, [r7, #20] /* Called by the portable layer each time a tick interrupt occurs. Increments the tick then checks to see if the new tick value will cause any tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8016376: 4b4f ldr r3, [pc, #316] @ (80164b4 ) 8016378: 681b ldr r3, [r3, #0] 801637a: 2b00 cmp r3, #0 801637c: f040 8090 bne.w 80164a0 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 8016380: 4b4d ldr r3, [pc, #308] @ (80164b8 ) 8016382: 681b ldr r3, [r3, #0] 8016384: 3301 adds r3, #1 8016386: 613b str r3, [r7, #16] /* Increment the RTOS tick, switching the delayed and overflowed delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; 8016388: 4a4b ldr r2, [pc, #300] @ (80164b8 ) 801638a: 693b ldr r3, [r7, #16] 801638c: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ 801638e: 693b ldr r3, [r7, #16] 8016390: 2b00 cmp r3, #0 8016392: d121 bne.n 80163d8 { taskSWITCH_DELAYED_LISTS(); 8016394: 4b49 ldr r3, [pc, #292] @ (80164bc ) 8016396: 681b ldr r3, [r3, #0] 8016398: 681b ldr r3, [r3, #0] 801639a: 2b00 cmp r3, #0 801639c: d00b beq.n 80163b6 __asm volatile 801639e: f04f 0350 mov.w r3, #80 @ 0x50 80163a2: f383 8811 msr BASEPRI, r3 80163a6: f3bf 8f6f isb sy 80163aa: f3bf 8f4f dsb sy 80163ae: 603b str r3, [r7, #0] } 80163b0: bf00 nop 80163b2: bf00 nop 80163b4: e7fd b.n 80163b2 80163b6: 4b41 ldr r3, [pc, #260] @ (80164bc ) 80163b8: 681b ldr r3, [r3, #0] 80163ba: 60fb str r3, [r7, #12] 80163bc: 4b40 ldr r3, [pc, #256] @ (80164c0 ) 80163be: 681b ldr r3, [r3, #0] 80163c0: 4a3e ldr r2, [pc, #248] @ (80164bc ) 80163c2: 6013 str r3, [r2, #0] 80163c4: 4a3e ldr r2, [pc, #248] @ (80164c0 ) 80163c6: 68fb ldr r3, [r7, #12] 80163c8: 6013 str r3, [r2, #0] 80163ca: 4b3e ldr r3, [pc, #248] @ (80164c4 ) 80163cc: 681b ldr r3, [r3, #0] 80163ce: 3301 adds r3, #1 80163d0: 4a3c ldr r2, [pc, #240] @ (80164c4 ) 80163d2: 6013 str r3, [r2, #0] 80163d4: f000 fb18 bl 8016a08 /* See if this tick has made a timeout expire. Tasks are stored in the queue in the order of their wake time - meaning once one task has been found whose block time has not expired there is no need to look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) 80163d8: 4b3b ldr r3, [pc, #236] @ (80164c8 ) 80163da: 681b ldr r3, [r3, #0] 80163dc: 693a ldr r2, [r7, #16] 80163de: 429a cmp r2, r3 80163e0: d349 bcc.n 8016476 { for( ;; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 80163e2: 4b36 ldr r3, [pc, #216] @ (80164bc ) 80163e4: 681b ldr r3, [r3, #0] 80163e6: 681b ldr r3, [r3, #0] 80163e8: 2b00 cmp r3, #0 80163ea: d104 bne.n 80163f6 /* The delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 80163ec: 4b36 ldr r3, [pc, #216] @ (80164c8 ) 80163ee: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80163f2: 601a str r2, [r3, #0] break; 80163f4: e03f b.n 8016476 { /* The delayed list is not empty, get the value of the item at the head of the delayed list. This is the time at which the task at the head of the delayed list must be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80163f6: 4b31 ldr r3, [pc, #196] @ (80164bc ) 80163f8: 681b ldr r3, [r3, #0] 80163fa: 68db ldr r3, [r3, #12] 80163fc: 68db ldr r3, [r3, #12] 80163fe: 60bb str r3, [r7, #8] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); 8016400: 68bb ldr r3, [r7, #8] 8016402: 685b ldr r3, [r3, #4] 8016404: 607b str r3, [r7, #4] if( xConstTickCount < xItemValue ) 8016406: 693a ldr r2, [r7, #16] 8016408: 687b ldr r3, [r7, #4] 801640a: 429a cmp r2, r3 801640c: d203 bcs.n 8016416 /* It is not time to unblock this item yet, but the item value is the time at which the task at the head of the blocked list must be removed from the Blocked state - so record the item value in xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; 801640e: 4a2e ldr r2, [pc, #184] @ (80164c8 ) 8016410: 687b ldr r3, [r7, #4] 8016412: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ 8016414: e02f b.n 8016476 { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8016416: 68bb ldr r3, [r7, #8] 8016418: 3304 adds r3, #4 801641a: 4618 mov r0, r3 801641c: f7fe fb06 bl 8014a2c /* Is the task waiting on an event also? If so remove it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 8016420: 68bb ldr r3, [r7, #8] 8016422: 6a9b ldr r3, [r3, #40] @ 0x28 8016424: 2b00 cmp r3, #0 8016426: d004 beq.n 8016432 { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 8016428: 68bb ldr r3, [r7, #8] 801642a: 3318 adds r3, #24 801642c: 4618 mov r0, r3 801642e: f7fe fafd bl 8014a2c mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready list. */ prvAddTaskToReadyList( pxTCB ); 8016432: 68bb ldr r3, [r7, #8] 8016434: 6ada ldr r2, [r3, #44] @ 0x2c 8016436: 4b25 ldr r3, [pc, #148] @ (80164cc ) 8016438: 681b ldr r3, [r3, #0] 801643a: 429a cmp r2, r3 801643c: d903 bls.n 8016446 801643e: 68bb ldr r3, [r7, #8] 8016440: 6adb ldr r3, [r3, #44] @ 0x2c 8016442: 4a22 ldr r2, [pc, #136] @ (80164cc ) 8016444: 6013 str r3, [r2, #0] 8016446: 68bb ldr r3, [r7, #8] 8016448: 6ada ldr r2, [r3, #44] @ 0x2c 801644a: 4613 mov r3, r2 801644c: 009b lsls r3, r3, #2 801644e: 4413 add r3, r2 8016450: 009b lsls r3, r3, #2 8016452: 4a1f ldr r2, [pc, #124] @ (80164d0 ) 8016454: 441a add r2, r3 8016456: 68bb ldr r3, [r7, #8] 8016458: 3304 adds r3, #4 801645a: 4619 mov r1, r3 801645c: 4610 mov r0, r2 801645e: f7fe fa88 bl 8014972 { /* Preemption is on, but a context switch should only be performed if the unblocked task has a priority that is equal to or higher than the currently executing task. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 8016462: 68bb ldr r3, [r7, #8] 8016464: 6ada ldr r2, [r3, #44] @ 0x2c 8016466: 4b1b ldr r3, [pc, #108] @ (80164d4 ) 8016468: 681b ldr r3, [r3, #0] 801646a: 6adb ldr r3, [r3, #44] @ 0x2c 801646c: 429a cmp r2, r3 801646e: d3b8 bcc.n 80163e2 { xSwitchRequired = pdTRUE; 8016470: 2301 movs r3, #1 8016472: 617b str r3, [r7, #20] if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8016474: e7b5 b.n 80163e2 /* Tasks of equal priority to the currently running task will share processing time (time slice) if preemption is on, and the application writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 8016476: 4b17 ldr r3, [pc, #92] @ (80164d4 ) 8016478: 681b ldr r3, [r3, #0] 801647a: 6ada ldr r2, [r3, #44] @ 0x2c 801647c: 4914 ldr r1, [pc, #80] @ (80164d0 ) 801647e: 4613 mov r3, r2 8016480: 009b lsls r3, r3, #2 8016482: 4413 add r3, r2 8016484: 009b lsls r3, r3, #2 8016486: 440b add r3, r1 8016488: 681b ldr r3, [r3, #0] 801648a: 2b01 cmp r3, #1 801648c: d901 bls.n 8016492 { xSwitchRequired = pdTRUE; 801648e: 2301 movs r3, #1 8016490: 617b str r3, [r7, #20] } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) 8016492: 4b11 ldr r3, [pc, #68] @ (80164d8 ) 8016494: 681b ldr r3, [r3, #0] 8016496: 2b00 cmp r3, #0 8016498: d007 beq.n 80164aa { xSwitchRequired = pdTRUE; 801649a: 2301 movs r3, #1 801649c: 617b str r3, [r7, #20] 801649e: e004 b.n 80164aa } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; 80164a0: 4b0e ldr r3, [pc, #56] @ (80164dc ) 80164a2: 681b ldr r3, [r3, #0] 80164a4: 3301 adds r3, #1 80164a6: 4a0d ldr r2, [pc, #52] @ (80164dc ) 80164a8: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; 80164aa: 697b ldr r3, [r7, #20] } 80164ac: 4618 mov r0, r3 80164ae: 3718 adds r7, #24 80164b0: 46bd mov sp, r7 80164b2: bd80 pop {r7, pc} 80164b4: 24002ef4 .word 0x24002ef4 80164b8: 24002ed0 .word 0x24002ed0 80164bc: 24002e84 .word 0x24002e84 80164c0: 24002e88 .word 0x24002e88 80164c4: 24002ee4 .word 0x24002ee4 80164c8: 24002eec .word 0x24002eec 80164cc: 24002ed4 .word 0x24002ed4 80164d0: 240029fc .word 0x240029fc 80164d4: 240029f8 .word 0x240029f8 80164d8: 24002ee0 .word 0x24002ee0 80164dc: 24002edc .word 0x24002edc 080164e0 : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { 80164e0: b580 push {r7, lr} 80164e2: b084 sub sp, #16 80164e4: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) 80164e6: 4b32 ldr r3, [pc, #200] @ (80165b0 ) 80164e8: 681b ldr r3, [r3, #0] 80164ea: 2b00 cmp r3, #0 80164ec: d003 beq.n 80164f6 { /* The scheduler is currently suspended - do not allow a context switch. */ xYieldPending = pdTRUE; 80164ee: 4b31 ldr r3, [pc, #196] @ (80165b4 ) 80164f0: 2201 movs r2, #1 80164f2: 601a str r2, [r3, #0] for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ } } 80164f4: e058 b.n 80165a8 xYieldPending = pdFALSE; 80164f6: 4b2f ldr r3, [pc, #188] @ (80165b4 ) 80164f8: 2200 movs r2, #0 80164fa: 601a str r2, [r3, #0] taskCHECK_FOR_STACK_OVERFLOW(); 80164fc: 4b2e ldr r3, [pc, #184] @ (80165b8 ) 80164fe: 681b ldr r3, [r3, #0] 8016500: 681a ldr r2, [r3, #0] 8016502: 4b2d ldr r3, [pc, #180] @ (80165b8 ) 8016504: 681b ldr r3, [r3, #0] 8016506: 6b1b ldr r3, [r3, #48] @ 0x30 8016508: 429a cmp r2, r3 801650a: d808 bhi.n 801651e 801650c: 4b2a ldr r3, [pc, #168] @ (80165b8 ) 801650e: 681a ldr r2, [r3, #0] 8016510: 4b29 ldr r3, [pc, #164] @ (80165b8 ) 8016512: 681b ldr r3, [r3, #0] 8016514: 3334 adds r3, #52 @ 0x34 8016516: 4619 mov r1, r3 8016518: 4610 mov r0, r2 801651a: f7ea f859 bl 80005d0 taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 801651e: 4b27 ldr r3, [pc, #156] @ (80165bc ) 8016520: 681b ldr r3, [r3, #0] 8016522: 60fb str r3, [r7, #12] 8016524: e011 b.n 801654a 8016526: 68fb ldr r3, [r7, #12] 8016528: 2b00 cmp r3, #0 801652a: d10b bne.n 8016544 __asm volatile 801652c: f04f 0350 mov.w r3, #80 @ 0x50 8016530: f383 8811 msr BASEPRI, r3 8016534: f3bf 8f6f isb sy 8016538: f3bf 8f4f dsb sy 801653c: 607b str r3, [r7, #4] } 801653e: bf00 nop 8016540: bf00 nop 8016542: e7fd b.n 8016540 8016544: 68fb ldr r3, [r7, #12] 8016546: 3b01 subs r3, #1 8016548: 60fb str r3, [r7, #12] 801654a: 491d ldr r1, [pc, #116] @ (80165c0 ) 801654c: 68fa ldr r2, [r7, #12] 801654e: 4613 mov r3, r2 8016550: 009b lsls r3, r3, #2 8016552: 4413 add r3, r2 8016554: 009b lsls r3, r3, #2 8016556: 440b add r3, r1 8016558: 681b ldr r3, [r3, #0] 801655a: 2b00 cmp r3, #0 801655c: d0e3 beq.n 8016526 801655e: 68fa ldr r2, [r7, #12] 8016560: 4613 mov r3, r2 8016562: 009b lsls r3, r3, #2 8016564: 4413 add r3, r2 8016566: 009b lsls r3, r3, #2 8016568: 4a15 ldr r2, [pc, #84] @ (80165c0 ) 801656a: 4413 add r3, r2 801656c: 60bb str r3, [r7, #8] 801656e: 68bb ldr r3, [r7, #8] 8016570: 685b ldr r3, [r3, #4] 8016572: 685a ldr r2, [r3, #4] 8016574: 68bb ldr r3, [r7, #8] 8016576: 605a str r2, [r3, #4] 8016578: 68bb ldr r3, [r7, #8] 801657a: 685a ldr r2, [r3, #4] 801657c: 68bb ldr r3, [r7, #8] 801657e: 3308 adds r3, #8 8016580: 429a cmp r2, r3 8016582: d104 bne.n 801658e 8016584: 68bb ldr r3, [r7, #8] 8016586: 685b ldr r3, [r3, #4] 8016588: 685a ldr r2, [r3, #4] 801658a: 68bb ldr r3, [r7, #8] 801658c: 605a str r2, [r3, #4] 801658e: 68bb ldr r3, [r7, #8] 8016590: 685b ldr r3, [r3, #4] 8016592: 68db ldr r3, [r3, #12] 8016594: 4a08 ldr r2, [pc, #32] @ (80165b8 ) 8016596: 6013 str r3, [r2, #0] 8016598: 4a08 ldr r2, [pc, #32] @ (80165bc ) 801659a: 68fb ldr r3, [r7, #12] 801659c: 6013 str r3, [r2, #0] _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 801659e: 4b06 ldr r3, [pc, #24] @ (80165b8 ) 80165a0: 681b ldr r3, [r3, #0] 80165a2: 3354 adds r3, #84 @ 0x54 80165a4: 4a07 ldr r2, [pc, #28] @ (80165c4 ) 80165a6: 6013 str r3, [r2, #0] } 80165a8: bf00 nop 80165aa: 3710 adds r7, #16 80165ac: 46bd mov sp, r7 80165ae: bd80 pop {r7, pc} 80165b0: 24002ef4 .word 0x24002ef4 80165b4: 24002ee0 .word 0x24002ee0 80165b8: 240029f8 .word 0x240029f8 80165bc: 24002ed4 .word 0x24002ed4 80165c0: 240029fc .word 0x240029fc 80165c4: 24000048 .word 0x24000048 080165c8 : /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { 80165c8: b580 push {r7, lr} 80165ca: b084 sub sp, #16 80165cc: af00 add r7, sp, #0 80165ce: 6078 str r0, [r7, #4] 80165d0: 6039 str r1, [r7, #0] configASSERT( pxEventList ); 80165d2: 687b ldr r3, [r7, #4] 80165d4: 2b00 cmp r3, #0 80165d6: d10b bne.n 80165f0 __asm volatile 80165d8: f04f 0350 mov.w r3, #80 @ 0x50 80165dc: f383 8811 msr BASEPRI, r3 80165e0: f3bf 8f6f isb sy 80165e4: f3bf 8f4f dsb sy 80165e8: 60fb str r3, [r7, #12] } 80165ea: bf00 nop 80165ec: bf00 nop 80165ee: e7fd b.n 80165ec /* Place the event list item of the TCB in the appropriate event list. This is placed in the list in priority order so the highest priority task is the first to be woken by the event. The queue that contains the event list is locked, preventing simultaneous access from interrupts. */ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 80165f0: 4b07 ldr r3, [pc, #28] @ (8016610 ) 80165f2: 681b ldr r3, [r3, #0] 80165f4: 3318 adds r3, #24 80165f6: 4619 mov r1, r3 80165f8: 6878 ldr r0, [r7, #4] 80165fa: f7fe f9de bl 80149ba prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 80165fe: 2101 movs r1, #1 8016600: 6838 ldr r0, [r7, #0] 8016602: f000 fded bl 80171e0 } 8016606: bf00 nop 8016608: 3710 adds r7, #16 801660a: 46bd mov sp, r7 801660c: bd80 pop {r7, pc} 801660e: bf00 nop 8016610: 240029f8 .word 0x240029f8 08016614 : /*-----------------------------------------------------------*/ #if( configUSE_TIMERS == 1 ) void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 8016614: b580 push {r7, lr} 8016616: b086 sub sp, #24 8016618: af00 add r7, sp, #0 801661a: 60f8 str r0, [r7, #12] 801661c: 60b9 str r1, [r7, #8] 801661e: 607a str r2, [r7, #4] configASSERT( pxEventList ); 8016620: 68fb ldr r3, [r7, #12] 8016622: 2b00 cmp r3, #0 8016624: d10b bne.n 801663e __asm volatile 8016626: f04f 0350 mov.w r3, #80 @ 0x50 801662a: f383 8811 msr BASEPRI, r3 801662e: f3bf 8f6f isb sy 8016632: f3bf 8f4f dsb sy 8016636: 617b str r3, [r7, #20] } 8016638: bf00 nop 801663a: bf00 nop 801663c: e7fd b.n 801663a /* Place the event list item of the TCB in the appropriate event list. In this case it is assume that this is the only task that is going to be waiting on this event list, so the faster vListInsertEnd() function can be used in place of vListInsert. */ vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 801663e: 4b0a ldr r3, [pc, #40] @ (8016668 ) 8016640: 681b ldr r3, [r3, #0] 8016642: 3318 adds r3, #24 8016644: 4619 mov r1, r3 8016646: 68f8 ldr r0, [r7, #12] 8016648: f7fe f993 bl 8014972 /* If the task should block indefinitely then set the block time to a value that will be recognised as an indefinite delay inside the prvAddCurrentTaskToDelayedList() function. */ if( xWaitIndefinitely != pdFALSE ) 801664c: 687b ldr r3, [r7, #4] 801664e: 2b00 cmp r3, #0 8016650: d002 beq.n 8016658 { xTicksToWait = portMAX_DELAY; 8016652: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8016656: 60bb str r3, [r7, #8] } traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); 8016658: 6879 ldr r1, [r7, #4] 801665a: 68b8 ldr r0, [r7, #8] 801665c: f000 fdc0 bl 80171e0 } 8016660: bf00 nop 8016662: 3718 adds r7, #24 8016664: 46bd mov sp, r7 8016666: bd80 pop {r7, pc} 8016668: 240029f8 .word 0x240029f8 0801666c : #endif /* configUSE_TIMERS */ /*-----------------------------------------------------------*/ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { 801666c: b580 push {r7, lr} 801666e: b086 sub sp, #24 8016670: af00 add r7, sp, #0 8016672: 6078 str r0, [r7, #4] get called - the lock count on the queue will get modified instead. This means exclusive access to the event list is guaranteed here. This function assumes that a check has already been made to ensure that pxEventList is not empty. */ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8016674: 687b ldr r3, [r7, #4] 8016676: 68db ldr r3, [r3, #12] 8016678: 68db ldr r3, [r3, #12] 801667a: 613b str r3, [r7, #16] configASSERT( pxUnblockedTCB ); 801667c: 693b ldr r3, [r7, #16] 801667e: 2b00 cmp r3, #0 8016680: d10b bne.n 801669a __asm volatile 8016682: f04f 0350 mov.w r3, #80 @ 0x50 8016686: f383 8811 msr BASEPRI, r3 801668a: f3bf 8f6f isb sy 801668e: f3bf 8f4f dsb sy 8016692: 60fb str r3, [r7, #12] } 8016694: bf00 nop 8016696: bf00 nop 8016698: e7fd b.n 8016696 ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); 801669a: 693b ldr r3, [r7, #16] 801669c: 3318 adds r3, #24 801669e: 4618 mov r0, r3 80166a0: f7fe f9c4 bl 8014a2c if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80166a4: 4b1d ldr r3, [pc, #116] @ (801671c ) 80166a6: 681b ldr r3, [r3, #0] 80166a8: 2b00 cmp r3, #0 80166aa: d11d bne.n 80166e8 { ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); 80166ac: 693b ldr r3, [r7, #16] 80166ae: 3304 adds r3, #4 80166b0: 4618 mov r0, r3 80166b2: f7fe f9bb bl 8014a2c prvAddTaskToReadyList( pxUnblockedTCB ); 80166b6: 693b ldr r3, [r7, #16] 80166b8: 6ada ldr r2, [r3, #44] @ 0x2c 80166ba: 4b19 ldr r3, [pc, #100] @ (8016720 ) 80166bc: 681b ldr r3, [r3, #0] 80166be: 429a cmp r2, r3 80166c0: d903 bls.n 80166ca 80166c2: 693b ldr r3, [r7, #16] 80166c4: 6adb ldr r3, [r3, #44] @ 0x2c 80166c6: 4a16 ldr r2, [pc, #88] @ (8016720 ) 80166c8: 6013 str r3, [r2, #0] 80166ca: 693b ldr r3, [r7, #16] 80166cc: 6ada ldr r2, [r3, #44] @ 0x2c 80166ce: 4613 mov r3, r2 80166d0: 009b lsls r3, r3, #2 80166d2: 4413 add r3, r2 80166d4: 009b lsls r3, r3, #2 80166d6: 4a13 ldr r2, [pc, #76] @ (8016724 ) 80166d8: 441a add r2, r3 80166da: 693b ldr r3, [r7, #16] 80166dc: 3304 adds r3, #4 80166de: 4619 mov r1, r3 80166e0: 4610 mov r0, r2 80166e2: f7fe f946 bl 8014972 80166e6: e005 b.n 80166f4 } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); 80166e8: 693b ldr r3, [r7, #16] 80166ea: 3318 adds r3, #24 80166ec: 4619 mov r1, r3 80166ee: 480e ldr r0, [pc, #56] @ (8016728 ) 80166f0: f7fe f93f bl 8014972 } if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) 80166f4: 693b ldr r3, [r7, #16] 80166f6: 6ada ldr r2, [r3, #44] @ 0x2c 80166f8: 4b0c ldr r3, [pc, #48] @ (801672c ) 80166fa: 681b ldr r3, [r3, #0] 80166fc: 6adb ldr r3, [r3, #44] @ 0x2c 80166fe: 429a cmp r2, r3 8016700: d905 bls.n 801670e { /* Return true if the task removed from the event list has a higher priority than the calling task. This allows the calling task to know if it should force a context switch now. */ xReturn = pdTRUE; 8016702: 2301 movs r3, #1 8016704: 617b str r3, [r7, #20] /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 8016706: 4b0a ldr r3, [pc, #40] @ (8016730 ) 8016708: 2201 movs r2, #1 801670a: 601a str r2, [r3, #0] 801670c: e001 b.n 8016712 } else { xReturn = pdFALSE; 801670e: 2300 movs r3, #0 8016710: 617b str r3, [r7, #20] } return xReturn; 8016712: 697b ldr r3, [r7, #20] } 8016714: 4618 mov r0, r3 8016716: 3718 adds r7, #24 8016718: 46bd mov sp, r7 801671a: bd80 pop {r7, pc} 801671c: 24002ef4 .word 0x24002ef4 8016720: 24002ed4 .word 0x24002ed4 8016724: 240029fc .word 0x240029fc 8016728: 24002e8c .word 0x24002e8c 801672c: 240029f8 .word 0x240029f8 8016730: 24002ee0 .word 0x24002ee0 08016734 : } } /*-----------------------------------------------------------*/ void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) { 8016734: b580 push {r7, lr} 8016736: b084 sub sp, #16 8016738: af00 add r7, sp, #0 801673a: 6078 str r0, [r7, #4] configASSERT( pxTimeOut ); 801673c: 687b ldr r3, [r7, #4] 801673e: 2b00 cmp r3, #0 8016740: d10b bne.n 801675a __asm volatile 8016742: f04f 0350 mov.w r3, #80 @ 0x50 8016746: f383 8811 msr BASEPRI, r3 801674a: f3bf 8f6f isb sy 801674e: f3bf 8f4f dsb sy 8016752: 60fb str r3, [r7, #12] } 8016754: bf00 nop 8016756: bf00 nop 8016758: e7fd b.n 8016756 taskENTER_CRITICAL(); 801675a: f001 fb0d bl 8017d78 { pxTimeOut->xOverflowCount = xNumOfOverflows; 801675e: 4b07 ldr r3, [pc, #28] @ (801677c ) 8016760: 681a ldr r2, [r3, #0] 8016762: 687b ldr r3, [r7, #4] 8016764: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 8016766: 4b06 ldr r3, [pc, #24] @ (8016780 ) 8016768: 681a ldr r2, [r3, #0] 801676a: 687b ldr r3, [r7, #4] 801676c: 605a str r2, [r3, #4] } taskEXIT_CRITICAL(); 801676e: f001 fb35 bl 8017ddc } 8016772: bf00 nop 8016774: 3710 adds r7, #16 8016776: 46bd mov sp, r7 8016778: bd80 pop {r7, pc} 801677a: bf00 nop 801677c: 24002ee4 .word 0x24002ee4 8016780: 24002ed0 .word 0x24002ed0 08016784 : /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { 8016784: b480 push {r7} 8016786: b083 sub sp, #12 8016788: af00 add r7, sp, #0 801678a: 6078 str r0, [r7, #4] /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; 801678c: 4b06 ldr r3, [pc, #24] @ (80167a8 ) 801678e: 681a ldr r2, [r3, #0] 8016790: 687b ldr r3, [r7, #4] 8016792: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 8016794: 4b05 ldr r3, [pc, #20] @ (80167ac ) 8016796: 681a ldr r2, [r3, #0] 8016798: 687b ldr r3, [r7, #4] 801679a: 605a str r2, [r3, #4] } 801679c: bf00 nop 801679e: 370c adds r7, #12 80167a0: 46bd mov sp, r7 80167a2: f85d 7b04 ldr.w r7, [sp], #4 80167a6: 4770 bx lr 80167a8: 24002ee4 .word 0x24002ee4 80167ac: 24002ed0 .word 0x24002ed0 080167b0 : /*-----------------------------------------------------------*/ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) { 80167b0: b580 push {r7, lr} 80167b2: b088 sub sp, #32 80167b4: af00 add r7, sp, #0 80167b6: 6078 str r0, [r7, #4] 80167b8: 6039 str r1, [r7, #0] BaseType_t xReturn; configASSERT( pxTimeOut ); 80167ba: 687b ldr r3, [r7, #4] 80167bc: 2b00 cmp r3, #0 80167be: d10b bne.n 80167d8 __asm volatile 80167c0: f04f 0350 mov.w r3, #80 @ 0x50 80167c4: f383 8811 msr BASEPRI, r3 80167c8: f3bf 8f6f isb sy 80167cc: f3bf 8f4f dsb sy 80167d0: 613b str r3, [r7, #16] } 80167d2: bf00 nop 80167d4: bf00 nop 80167d6: e7fd b.n 80167d4 configASSERT( pxTicksToWait ); 80167d8: 683b ldr r3, [r7, #0] 80167da: 2b00 cmp r3, #0 80167dc: d10b bne.n 80167f6 __asm volatile 80167de: f04f 0350 mov.w r3, #80 @ 0x50 80167e2: f383 8811 msr BASEPRI, r3 80167e6: f3bf 8f6f isb sy 80167ea: f3bf 8f4f dsb sy 80167ee: 60fb str r3, [r7, #12] } 80167f0: bf00 nop 80167f2: bf00 nop 80167f4: e7fd b.n 80167f2 taskENTER_CRITICAL(); 80167f6: f001 fabf bl 8017d78 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; 80167fa: 4b1d ldr r3, [pc, #116] @ (8016870 ) 80167fc: 681b ldr r3, [r3, #0] 80167fe: 61bb str r3, [r7, #24] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; 8016800: 687b ldr r3, [r7, #4] 8016802: 685b ldr r3, [r3, #4] 8016804: 69ba ldr r2, [r7, #24] 8016806: 1ad3 subs r3, r2, r3 8016808: 617b str r3, [r7, #20] } else #endif #if ( INCLUDE_vTaskSuspend == 1 ) if( *pxTicksToWait == portMAX_DELAY ) 801680a: 683b ldr r3, [r7, #0] 801680c: 681b ldr r3, [r3, #0] 801680e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8016812: d102 bne.n 801681a { /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is the maximum block time then the task should block indefinitely, and therefore never time out. */ xReturn = pdFALSE; 8016814: 2300 movs r3, #0 8016816: 61fb str r3, [r7, #28] 8016818: e023 b.n 8016862 } else #endif if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ 801681a: 687b ldr r3, [r7, #4] 801681c: 681a ldr r2, [r3, #0] 801681e: 4b15 ldr r3, [pc, #84] @ (8016874 ) 8016820: 681b ldr r3, [r3, #0] 8016822: 429a cmp r2, r3 8016824: d007 beq.n 8016836 8016826: 687b ldr r3, [r7, #4] 8016828: 685b ldr r3, [r3, #4] 801682a: 69ba ldr r2, [r7, #24] 801682c: 429a cmp r2, r3 801682e: d302 bcc.n 8016836 /* The tick count is greater than the time at which vTaskSetTimeout() was called, but has also overflowed since vTaskSetTimeOut() was called. It must have wrapped all the way around and gone past again. This passed since vTaskSetTimeout() was called. */ xReturn = pdTRUE; 8016830: 2301 movs r3, #1 8016832: 61fb str r3, [r7, #28] 8016834: e015 b.n 8016862 } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ 8016836: 683b ldr r3, [r7, #0] 8016838: 681b ldr r3, [r3, #0] 801683a: 697a ldr r2, [r7, #20] 801683c: 429a cmp r2, r3 801683e: d20b bcs.n 8016858 { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; 8016840: 683b ldr r3, [r7, #0] 8016842: 681a ldr r2, [r3, #0] 8016844: 697b ldr r3, [r7, #20] 8016846: 1ad2 subs r2, r2, r3 8016848: 683b ldr r3, [r7, #0] 801684a: 601a str r2, [r3, #0] vTaskInternalSetTimeOutState( pxTimeOut ); 801684c: 6878 ldr r0, [r7, #4] 801684e: f7ff ff99 bl 8016784 xReturn = pdFALSE; 8016852: 2300 movs r3, #0 8016854: 61fb str r3, [r7, #28] 8016856: e004 b.n 8016862 } else { *pxTicksToWait = 0; 8016858: 683b ldr r3, [r7, #0] 801685a: 2200 movs r2, #0 801685c: 601a str r2, [r3, #0] xReturn = pdTRUE; 801685e: 2301 movs r3, #1 8016860: 61fb str r3, [r7, #28] } } taskEXIT_CRITICAL(); 8016862: f001 fabb bl 8017ddc return xReturn; 8016866: 69fb ldr r3, [r7, #28] } 8016868: 4618 mov r0, r3 801686a: 3720 adds r7, #32 801686c: 46bd mov sp, r7 801686e: bd80 pop {r7, pc} 8016870: 24002ed0 .word 0x24002ed0 8016874: 24002ee4 .word 0x24002ee4 08016878 : /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { 8016878: b480 push {r7} 801687a: af00 add r7, sp, #0 xYieldPending = pdTRUE; 801687c: 4b03 ldr r3, [pc, #12] @ (801688c ) 801687e: 2201 movs r2, #1 8016880: 601a str r2, [r3, #0] } 8016882: bf00 nop 8016884: 46bd mov sp, r7 8016886: f85d 7b04 ldr.w r7, [sp], #4 801688a: 4770 bx lr 801688c: 24002ee0 .word 0x24002ee0 08016890 : * * void prvIdleTask( void *pvParameters ); * */ static portTASK_FUNCTION( prvIdleTask, pvParameters ) { 8016890: b580 push {r7, lr} 8016892: b082 sub sp, #8 8016894: af00 add r7, sp, #0 8016896: 6078 str r0, [r7, #4] for( ;; ) { /* See if any tasks have deleted themselves - if so then the idle task is responsible for freeing the deleted task's TCB and stack. */ prvCheckTasksWaitingTermination(); 8016898: f000 f852 bl 8016940 A critical region is not required here as we are just reading from the list, and an occasional incorrect value will not matter. If the ready list at the idle priority contains more than one task then a task other than the idle task is ready to execute. */ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) 801689c: 4b06 ldr r3, [pc, #24] @ (80168b8 ) 801689e: 681b ldr r3, [r3, #0] 80168a0: 2b01 cmp r3, #1 80168a2: d9f9 bls.n 8016898 { taskYIELD(); 80168a4: 4b05 ldr r3, [pc, #20] @ (80168bc ) 80168a6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80168aa: 601a str r2, [r3, #0] 80168ac: f3bf 8f4f dsb sy 80168b0: f3bf 8f6f isb sy prvCheckTasksWaitingTermination(); 80168b4: e7f0 b.n 8016898 80168b6: bf00 nop 80168b8: 240029fc .word 0x240029fc 80168bc: e000ed04 .word 0xe000ed04 080168c0 : #endif /* portUSING_MPU_WRAPPERS */ /*-----------------------------------------------------------*/ static void prvInitialiseTaskLists( void ) { 80168c0: b580 push {r7, lr} 80168c2: b082 sub sp, #8 80168c4: af00 add r7, sp, #0 UBaseType_t uxPriority; for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 80168c6: 2300 movs r3, #0 80168c8: 607b str r3, [r7, #4] 80168ca: e00c b.n 80168e6 { vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); 80168cc: 687a ldr r2, [r7, #4] 80168ce: 4613 mov r3, r2 80168d0: 009b lsls r3, r3, #2 80168d2: 4413 add r3, r2 80168d4: 009b lsls r3, r3, #2 80168d6: 4a12 ldr r2, [pc, #72] @ (8016920 ) 80168d8: 4413 add r3, r2 80168da: 4618 mov r0, r3 80168dc: f7fe f81c bl 8014918 for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 80168e0: 687b ldr r3, [r7, #4] 80168e2: 3301 adds r3, #1 80168e4: 607b str r3, [r7, #4] 80168e6: 687b ldr r3, [r7, #4] 80168e8: 2b37 cmp r3, #55 @ 0x37 80168ea: d9ef bls.n 80168cc } vListInitialise( &xDelayedTaskList1 ); 80168ec: 480d ldr r0, [pc, #52] @ (8016924 ) 80168ee: f7fe f813 bl 8014918 vListInitialise( &xDelayedTaskList2 ); 80168f2: 480d ldr r0, [pc, #52] @ (8016928 ) 80168f4: f7fe f810 bl 8014918 vListInitialise( &xPendingReadyList ); 80168f8: 480c ldr r0, [pc, #48] @ (801692c ) 80168fa: f7fe f80d bl 8014918 #if ( INCLUDE_vTaskDelete == 1 ) { vListInitialise( &xTasksWaitingTermination ); 80168fe: 480c ldr r0, [pc, #48] @ (8016930 ) 8016900: f7fe f80a bl 8014918 } #endif /* INCLUDE_vTaskDelete */ #if ( INCLUDE_vTaskSuspend == 1 ) { vListInitialise( &xSuspendedTaskList ); 8016904: 480b ldr r0, [pc, #44] @ (8016934 ) 8016906: f7fe f807 bl 8014918 } #endif /* INCLUDE_vTaskSuspend */ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList using list2. */ pxDelayedTaskList = &xDelayedTaskList1; 801690a: 4b0b ldr r3, [pc, #44] @ (8016938 ) 801690c: 4a05 ldr r2, [pc, #20] @ (8016924 ) 801690e: 601a str r2, [r3, #0] pxOverflowDelayedTaskList = &xDelayedTaskList2; 8016910: 4b0a ldr r3, [pc, #40] @ (801693c ) 8016912: 4a05 ldr r2, [pc, #20] @ (8016928 ) 8016914: 601a str r2, [r3, #0] } 8016916: bf00 nop 8016918: 3708 adds r7, #8 801691a: 46bd mov sp, r7 801691c: bd80 pop {r7, pc} 801691e: bf00 nop 8016920: 240029fc .word 0x240029fc 8016924: 24002e5c .word 0x24002e5c 8016928: 24002e70 .word 0x24002e70 801692c: 24002e8c .word 0x24002e8c 8016930: 24002ea0 .word 0x24002ea0 8016934: 24002eb8 .word 0x24002eb8 8016938: 24002e84 .word 0x24002e84 801693c: 24002e88 .word 0x24002e88 08016940 : /*-----------------------------------------------------------*/ static void prvCheckTasksWaitingTermination( void ) { 8016940: b580 push {r7, lr} 8016942: b082 sub sp, #8 8016944: af00 add r7, sp, #0 { TCB_t *pxTCB; /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 8016946: e019 b.n 801697c { taskENTER_CRITICAL(); 8016948: f001 fa16 bl 8017d78 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 801694c: 4b10 ldr r3, [pc, #64] @ (8016990 ) 801694e: 68db ldr r3, [r3, #12] 8016950: 68db ldr r3, [r3, #12] 8016952: 607b str r3, [r7, #4] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8016954: 687b ldr r3, [r7, #4] 8016956: 3304 adds r3, #4 8016958: 4618 mov r0, r3 801695a: f7fe f867 bl 8014a2c --uxCurrentNumberOfTasks; 801695e: 4b0d ldr r3, [pc, #52] @ (8016994 ) 8016960: 681b ldr r3, [r3, #0] 8016962: 3b01 subs r3, #1 8016964: 4a0b ldr r2, [pc, #44] @ (8016994 ) 8016966: 6013 str r3, [r2, #0] --uxDeletedTasksWaitingCleanUp; 8016968: 4b0b ldr r3, [pc, #44] @ (8016998 ) 801696a: 681b ldr r3, [r3, #0] 801696c: 3b01 subs r3, #1 801696e: 4a0a ldr r2, [pc, #40] @ (8016998 ) 8016970: 6013 str r3, [r2, #0] } taskEXIT_CRITICAL(); 8016972: f001 fa33 bl 8017ddc prvDeleteTCB( pxTCB ); 8016976: 6878 ldr r0, [r7, #4] 8016978: f000 f810 bl 801699c while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 801697c: 4b06 ldr r3, [pc, #24] @ (8016998 ) 801697e: 681b ldr r3, [r3, #0] 8016980: 2b00 cmp r3, #0 8016982: d1e1 bne.n 8016948 } } #endif /* INCLUDE_vTaskDelete */ } 8016984: bf00 nop 8016986: bf00 nop 8016988: 3708 adds r7, #8 801698a: 46bd mov sp, r7 801698c: bd80 pop {r7, pc} 801698e: bf00 nop 8016990: 24002ea0 .word 0x24002ea0 8016994: 24002ecc .word 0x24002ecc 8016998: 24002eb4 .word 0x24002eb4 0801699c : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelete == 1 ) static void prvDeleteTCB( TCB_t *pxTCB ) { 801699c: b580 push {r7, lr} 801699e: b084 sub sp, #16 80169a0: af00 add r7, sp, #0 80169a2: 6078 str r0, [r7, #4] to the task to free any memory allocated at the application level. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ #if ( configUSE_NEWLIB_REENTRANT == 1 ) { _reclaim_reent( &( pxTCB->xNewLib_reent ) ); 80169a4: 687b ldr r3, [r7, #4] 80169a6: 3354 adds r3, #84 @ 0x54 80169a8: 4618 mov r0, r3 80169aa: f001 fcfd bl 80183a8 <_reclaim_reent> #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* The task could have been allocated statically or dynamically, so check what was statically allocated before trying to free the memory. */ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) 80169ae: 687b ldr r3, [r7, #4] 80169b0: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 80169b4: 2b00 cmp r3, #0 80169b6: d108 bne.n 80169ca { /* Both the stack and TCB were allocated dynamically, so both must be freed. */ vPortFree( pxTCB->pxStack ); 80169b8: 687b ldr r3, [r7, #4] 80169ba: 6b1b ldr r3, [r3, #48] @ 0x30 80169bc: 4618 mov r0, r3 80169be: f001 fbcb bl 8018158 vPortFree( pxTCB ); 80169c2: 6878 ldr r0, [r7, #4] 80169c4: f001 fbc8 bl 8018158 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); mtCOVERAGE_TEST_MARKER(); } } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } 80169c8: e019 b.n 80169fe else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) 80169ca: 687b ldr r3, [r7, #4] 80169cc: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 80169d0: 2b01 cmp r3, #1 80169d2: d103 bne.n 80169dc vPortFree( pxTCB ); 80169d4: 6878 ldr r0, [r7, #4] 80169d6: f001 fbbf bl 8018158 } 80169da: e010 b.n 80169fe configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); 80169dc: 687b ldr r3, [r7, #4] 80169de: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 80169e2: 2b02 cmp r3, #2 80169e4: d00b beq.n 80169fe __asm volatile 80169e6: f04f 0350 mov.w r3, #80 @ 0x50 80169ea: f383 8811 msr BASEPRI, r3 80169ee: f3bf 8f6f isb sy 80169f2: f3bf 8f4f dsb sy 80169f6: 60fb str r3, [r7, #12] } 80169f8: bf00 nop 80169fa: bf00 nop 80169fc: e7fd b.n 80169fa } 80169fe: bf00 nop 8016a00: 3710 adds r7, #16 8016a02: 46bd mov sp, r7 8016a04: bd80 pop {r7, pc} ... 08016a08 : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { 8016a08: b480 push {r7} 8016a0a: b083 sub sp, #12 8016a0c: af00 add r7, sp, #0 TCB_t *pxTCB; if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8016a0e: 4b0c ldr r3, [pc, #48] @ (8016a40 ) 8016a10: 681b ldr r3, [r3, #0] 8016a12: 681b ldr r3, [r3, #0] 8016a14: 2b00 cmp r3, #0 8016a16: d104 bne.n 8016a22 { /* The new current delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass until there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; 8016a18: 4b0a ldr r3, [pc, #40] @ (8016a44 ) 8016a1a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8016a1e: 601a str r2, [r3, #0] which the task at the head of the delayed list should be removed from the Blocked state. */ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); } } 8016a20: e008 b.n 8016a34 ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8016a22: 4b07 ldr r3, [pc, #28] @ (8016a40 ) 8016a24: 681b ldr r3, [r3, #0] 8016a26: 68db ldr r3, [r3, #12] 8016a28: 68db ldr r3, [r3, #12] 8016a2a: 607b str r3, [r7, #4] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 8016a2c: 687b ldr r3, [r7, #4] 8016a2e: 685b ldr r3, [r3, #4] 8016a30: 4a04 ldr r2, [pc, #16] @ (8016a44 ) 8016a32: 6013 str r3, [r2, #0] } 8016a34: bf00 nop 8016a36: 370c adds r7, #12 8016a38: 46bd mov sp, r7 8016a3a: f85d 7b04 ldr.w r7, [sp], #4 8016a3e: 4770 bx lr 8016a40: 24002e84 .word 0x24002e84 8016a44: 24002eec .word 0x24002eec 08016a48 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) TaskHandle_t xTaskGetCurrentTaskHandle( void ) { 8016a48: b480 push {r7} 8016a4a: b083 sub sp, #12 8016a4c: af00 add r7, sp, #0 TaskHandle_t xReturn; /* A critical section is not required as this is not called from an interrupt and the current TCB will always be the same for any individual execution thread. */ xReturn = pxCurrentTCB; 8016a4e: 4b05 ldr r3, [pc, #20] @ (8016a64 ) 8016a50: 681b ldr r3, [r3, #0] 8016a52: 607b str r3, [r7, #4] return xReturn; 8016a54: 687b ldr r3, [r7, #4] } 8016a56: 4618 mov r0, r3 8016a58: 370c adds r7, #12 8016a5a: 46bd mov sp, r7 8016a5c: f85d 7b04 ldr.w r7, [sp], #4 8016a60: 4770 bx lr 8016a62: bf00 nop 8016a64: 240029f8 .word 0x240029f8 08016a68 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) BaseType_t xTaskGetSchedulerState( void ) { 8016a68: b480 push {r7} 8016a6a: b083 sub sp, #12 8016a6c: af00 add r7, sp, #0 BaseType_t xReturn; if( xSchedulerRunning == pdFALSE ) 8016a6e: 4b0b ldr r3, [pc, #44] @ (8016a9c ) 8016a70: 681b ldr r3, [r3, #0] 8016a72: 2b00 cmp r3, #0 8016a74: d102 bne.n 8016a7c { xReturn = taskSCHEDULER_NOT_STARTED; 8016a76: 2301 movs r3, #1 8016a78: 607b str r3, [r7, #4] 8016a7a: e008 b.n 8016a8e } else { if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8016a7c: 4b08 ldr r3, [pc, #32] @ (8016aa0 ) 8016a7e: 681b ldr r3, [r3, #0] 8016a80: 2b00 cmp r3, #0 8016a82: d102 bne.n 8016a8a { xReturn = taskSCHEDULER_RUNNING; 8016a84: 2302 movs r3, #2 8016a86: 607b str r3, [r7, #4] 8016a88: e001 b.n 8016a8e } else { xReturn = taskSCHEDULER_SUSPENDED; 8016a8a: 2300 movs r3, #0 8016a8c: 607b str r3, [r7, #4] } } return xReturn; 8016a8e: 687b ldr r3, [r7, #4] } 8016a90: 4618 mov r0, r3 8016a92: 370c adds r7, #12 8016a94: 46bd mov sp, r7 8016a96: f85d 7b04 ldr.w r7, [sp], #4 8016a9a: 4770 bx lr 8016a9c: 24002ed8 .word 0x24002ed8 8016aa0: 24002ef4 .word 0x24002ef4 08016aa4 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) { 8016aa4: b580 push {r7, lr} 8016aa6: b084 sub sp, #16 8016aa8: af00 add r7, sp, #0 8016aaa: 6078 str r0, [r7, #4] TCB_t * const pxMutexHolderTCB = pxMutexHolder; 8016aac: 687b ldr r3, [r7, #4] 8016aae: 60bb str r3, [r7, #8] BaseType_t xReturn = pdFALSE; 8016ab0: 2300 movs r3, #0 8016ab2: 60fb str r3, [r7, #12] /* If the mutex was given back by an interrupt while the queue was locked then the mutex holder might now be NULL. _RB_ Is this still needed as interrupts can no longer use mutexes? */ if( pxMutexHolder != NULL ) 8016ab4: 687b ldr r3, [r7, #4] 8016ab6: 2b00 cmp r3, #0 8016ab8: d051 beq.n 8016b5e { /* If the holder of the mutex has a priority below the priority of the task attempting to obtain the mutex then it will temporarily inherit the priority of the task attempting to obtain the mutex. */ if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) 8016aba: 68bb ldr r3, [r7, #8] 8016abc: 6ada ldr r2, [r3, #44] @ 0x2c 8016abe: 4b2a ldr r3, [pc, #168] @ (8016b68 ) 8016ac0: 681b ldr r3, [r3, #0] 8016ac2: 6adb ldr r3, [r3, #44] @ 0x2c 8016ac4: 429a cmp r2, r3 8016ac6: d241 bcs.n 8016b4c { /* Adjust the mutex holder state to account for its new priority. Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 8016ac8: 68bb ldr r3, [r7, #8] 8016aca: 699b ldr r3, [r3, #24] 8016acc: 2b00 cmp r3, #0 8016ace: db06 blt.n 8016ade { listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016ad0: 4b25 ldr r3, [pc, #148] @ (8016b68 ) 8016ad2: 681b ldr r3, [r3, #0] 8016ad4: 6adb ldr r3, [r3, #44] @ 0x2c 8016ad6: f1c3 0238 rsb r2, r3, #56 @ 0x38 8016ada: 68bb ldr r3, [r7, #8] 8016adc: 619a str r2, [r3, #24] mtCOVERAGE_TEST_MARKER(); } /* If the task being modified is in the ready state it will need to be moved into a new list. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) 8016ade: 68bb ldr r3, [r7, #8] 8016ae0: 6959 ldr r1, [r3, #20] 8016ae2: 68bb ldr r3, [r7, #8] 8016ae4: 6ada ldr r2, [r3, #44] @ 0x2c 8016ae6: 4613 mov r3, r2 8016ae8: 009b lsls r3, r3, #2 8016aea: 4413 add r3, r2 8016aec: 009b lsls r3, r3, #2 8016aee: 4a1f ldr r2, [pc, #124] @ (8016b6c ) 8016af0: 4413 add r3, r2 8016af2: 4299 cmp r1, r3 8016af4: d122 bne.n 8016b3c { if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016af6: 68bb ldr r3, [r7, #8] 8016af8: 3304 adds r3, #4 8016afa: 4618 mov r0, r3 8016afc: f7fd ff96 bl 8014a2c { mtCOVERAGE_TEST_MARKER(); } /* Inherit the priority before being moved into the new list. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8016b00: 4b19 ldr r3, [pc, #100] @ (8016b68 ) 8016b02: 681b ldr r3, [r3, #0] 8016b04: 6ada ldr r2, [r3, #44] @ 0x2c 8016b06: 68bb ldr r3, [r7, #8] 8016b08: 62da str r2, [r3, #44] @ 0x2c prvAddTaskToReadyList( pxMutexHolderTCB ); 8016b0a: 68bb ldr r3, [r7, #8] 8016b0c: 6ada ldr r2, [r3, #44] @ 0x2c 8016b0e: 4b18 ldr r3, [pc, #96] @ (8016b70 ) 8016b10: 681b ldr r3, [r3, #0] 8016b12: 429a cmp r2, r3 8016b14: d903 bls.n 8016b1e 8016b16: 68bb ldr r3, [r7, #8] 8016b18: 6adb ldr r3, [r3, #44] @ 0x2c 8016b1a: 4a15 ldr r2, [pc, #84] @ (8016b70 ) 8016b1c: 6013 str r3, [r2, #0] 8016b1e: 68bb ldr r3, [r7, #8] 8016b20: 6ada ldr r2, [r3, #44] @ 0x2c 8016b22: 4613 mov r3, r2 8016b24: 009b lsls r3, r3, #2 8016b26: 4413 add r3, r2 8016b28: 009b lsls r3, r3, #2 8016b2a: 4a10 ldr r2, [pc, #64] @ (8016b6c ) 8016b2c: 441a add r2, r3 8016b2e: 68bb ldr r3, [r7, #8] 8016b30: 3304 adds r3, #4 8016b32: 4619 mov r1, r3 8016b34: 4610 mov r0, r2 8016b36: f7fd ff1c bl 8014972 8016b3a: e004 b.n 8016b46 } else { /* Just inherit the priority. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8016b3c: 4b0a ldr r3, [pc, #40] @ (8016b68 ) 8016b3e: 681b ldr r3, [r3, #0] 8016b40: 6ada ldr r2, [r3, #44] @ 0x2c 8016b42: 68bb ldr r3, [r7, #8] 8016b44: 62da str r2, [r3, #44] @ 0x2c } traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); /* Inheritance occurred. */ xReturn = pdTRUE; 8016b46: 2301 movs r3, #1 8016b48: 60fb str r3, [r7, #12] 8016b4a: e008 b.n 8016b5e } else { if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) 8016b4c: 68bb ldr r3, [r7, #8] 8016b4e: 6cda ldr r2, [r3, #76] @ 0x4c 8016b50: 4b05 ldr r3, [pc, #20] @ (8016b68 ) 8016b52: 681b ldr r3, [r3, #0] 8016b54: 6adb ldr r3, [r3, #44] @ 0x2c 8016b56: 429a cmp r2, r3 8016b58: d201 bcs.n 8016b5e current priority of the mutex holder is not lower than the priority of the task attempting to take the mutex. Therefore the mutex holder must have already inherited a priority, but inheritance would have occurred if that had not been the case. */ xReturn = pdTRUE; 8016b5a: 2301 movs r3, #1 8016b5c: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8016b5e: 68fb ldr r3, [r7, #12] } 8016b60: 4618 mov r0, r3 8016b62: 3710 adds r7, #16 8016b64: 46bd mov sp, r7 8016b66: bd80 pop {r7, pc} 8016b68: 240029f8 .word 0x240029f8 8016b6c: 240029fc .word 0x240029fc 8016b70: 24002ed4 .word 0x24002ed4 08016b74 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { 8016b74: b580 push {r7, lr} 8016b76: b086 sub sp, #24 8016b78: af00 add r7, sp, #0 8016b7a: 6078 str r0, [r7, #4] TCB_t * const pxTCB = pxMutexHolder; 8016b7c: 687b ldr r3, [r7, #4] 8016b7e: 613b str r3, [r7, #16] BaseType_t xReturn = pdFALSE; 8016b80: 2300 movs r3, #0 8016b82: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 8016b84: 687b ldr r3, [r7, #4] 8016b86: 2b00 cmp r3, #0 8016b88: d058 beq.n 8016c3c { /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. */ configASSERT( pxTCB == pxCurrentTCB ); 8016b8a: 4b2f ldr r3, [pc, #188] @ (8016c48 ) 8016b8c: 681b ldr r3, [r3, #0] 8016b8e: 693a ldr r2, [r7, #16] 8016b90: 429a cmp r2, r3 8016b92: d00b beq.n 8016bac __asm volatile 8016b94: f04f 0350 mov.w r3, #80 @ 0x50 8016b98: f383 8811 msr BASEPRI, r3 8016b9c: f3bf 8f6f isb sy 8016ba0: f3bf 8f4f dsb sy 8016ba4: 60fb str r3, [r7, #12] } 8016ba6: bf00 nop 8016ba8: bf00 nop 8016baa: e7fd b.n 8016ba8 configASSERT( pxTCB->uxMutexesHeld ); 8016bac: 693b ldr r3, [r7, #16] 8016bae: 6d1b ldr r3, [r3, #80] @ 0x50 8016bb0: 2b00 cmp r3, #0 8016bb2: d10b bne.n 8016bcc __asm volatile 8016bb4: f04f 0350 mov.w r3, #80 @ 0x50 8016bb8: f383 8811 msr BASEPRI, r3 8016bbc: f3bf 8f6f isb sy 8016bc0: f3bf 8f4f dsb sy 8016bc4: 60bb str r3, [r7, #8] } 8016bc6: bf00 nop 8016bc8: bf00 nop 8016bca: e7fd b.n 8016bc8 ( pxTCB->uxMutexesHeld )--; 8016bcc: 693b ldr r3, [r7, #16] 8016bce: 6d1b ldr r3, [r3, #80] @ 0x50 8016bd0: 1e5a subs r2, r3, #1 8016bd2: 693b ldr r3, [r7, #16] 8016bd4: 651a str r2, [r3, #80] @ 0x50 /* Has the holder of the mutex inherited the priority of another task? */ if( pxTCB->uxPriority != pxTCB->uxBasePriority ) 8016bd6: 693b ldr r3, [r7, #16] 8016bd8: 6ada ldr r2, [r3, #44] @ 0x2c 8016bda: 693b ldr r3, [r7, #16] 8016bdc: 6cdb ldr r3, [r3, #76] @ 0x4c 8016bde: 429a cmp r2, r3 8016be0: d02c beq.n 8016c3c { /* Only disinherit if no other mutexes are held. */ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) 8016be2: 693b ldr r3, [r7, #16] 8016be4: 6d1b ldr r3, [r3, #80] @ 0x50 8016be6: 2b00 cmp r3, #0 8016be8: d128 bne.n 8016c3c /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. Remove the holding task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016bea: 693b ldr r3, [r7, #16] 8016bec: 3304 adds r3, #4 8016bee: 4618 mov r0, r3 8016bf0: f7fd ff1c bl 8014a2c } /* Disinherit the priority before adding the task into the new ready list. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); pxTCB->uxPriority = pxTCB->uxBasePriority; 8016bf4: 693b ldr r3, [r7, #16] 8016bf6: 6cda ldr r2, [r3, #76] @ 0x4c 8016bf8: 693b ldr r3, [r7, #16] 8016bfa: 62da str r2, [r3, #44] @ 0x2c /* Reset the event list item value. It cannot be in use for any other purpose if this task is running, and it must be running to give back the mutex. */ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016bfc: 693b ldr r3, [r7, #16] 8016bfe: 6adb ldr r3, [r3, #44] @ 0x2c 8016c00: f1c3 0238 rsb r2, r3, #56 @ 0x38 8016c04: 693b ldr r3, [r7, #16] 8016c06: 619a str r2, [r3, #24] prvAddTaskToReadyList( pxTCB ); 8016c08: 693b ldr r3, [r7, #16] 8016c0a: 6ada ldr r2, [r3, #44] @ 0x2c 8016c0c: 4b0f ldr r3, [pc, #60] @ (8016c4c ) 8016c0e: 681b ldr r3, [r3, #0] 8016c10: 429a cmp r2, r3 8016c12: d903 bls.n 8016c1c 8016c14: 693b ldr r3, [r7, #16] 8016c16: 6adb ldr r3, [r3, #44] @ 0x2c 8016c18: 4a0c ldr r2, [pc, #48] @ (8016c4c ) 8016c1a: 6013 str r3, [r2, #0] 8016c1c: 693b ldr r3, [r7, #16] 8016c1e: 6ada ldr r2, [r3, #44] @ 0x2c 8016c20: 4613 mov r3, r2 8016c22: 009b lsls r3, r3, #2 8016c24: 4413 add r3, r2 8016c26: 009b lsls r3, r3, #2 8016c28: 4a09 ldr r2, [pc, #36] @ (8016c50 ) 8016c2a: 441a add r2, r3 8016c2c: 693b ldr r3, [r7, #16] 8016c2e: 3304 adds r3, #4 8016c30: 4619 mov r1, r3 8016c32: 4610 mov r0, r2 8016c34: f7fd fe9d bl 8014972 in an order different to that in which they were taken. If a context switch did not occur when the first mutex was returned, even if a task was waiting on it, then a context switch should occur when the last mutex is returned whether a task is waiting on it or not. */ xReturn = pdTRUE; 8016c38: 2301 movs r3, #1 8016c3a: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8016c3c: 697b ldr r3, [r7, #20] } 8016c3e: 4618 mov r0, r3 8016c40: 3718 adds r7, #24 8016c42: 46bd mov sp, r7 8016c44: bd80 pop {r7, pc} 8016c46: bf00 nop 8016c48: 240029f8 .word 0x240029f8 8016c4c: 24002ed4 .word 0x24002ed4 8016c50: 240029fc .word 0x240029fc 08016c54 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) { 8016c54: b580 push {r7, lr} 8016c56: b088 sub sp, #32 8016c58: af00 add r7, sp, #0 8016c5a: 6078 str r0, [r7, #4] 8016c5c: 6039 str r1, [r7, #0] TCB_t * const pxTCB = pxMutexHolder; 8016c5e: 687b ldr r3, [r7, #4] 8016c60: 61bb str r3, [r7, #24] UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; 8016c62: 2301 movs r3, #1 8016c64: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 8016c66: 687b ldr r3, [r7, #4] 8016c68: 2b00 cmp r3, #0 8016c6a: d06c beq.n 8016d46 { /* If pxMutexHolder is not NULL then the holder must hold at least one mutex. */ configASSERT( pxTCB->uxMutexesHeld ); 8016c6c: 69bb ldr r3, [r7, #24] 8016c6e: 6d1b ldr r3, [r3, #80] @ 0x50 8016c70: 2b00 cmp r3, #0 8016c72: d10b bne.n 8016c8c __asm volatile 8016c74: f04f 0350 mov.w r3, #80 @ 0x50 8016c78: f383 8811 msr BASEPRI, r3 8016c7c: f3bf 8f6f isb sy 8016c80: f3bf 8f4f dsb sy 8016c84: 60fb str r3, [r7, #12] } 8016c86: bf00 nop 8016c88: bf00 nop 8016c8a: e7fd b.n 8016c88 /* Determine the priority to which the priority of the task that holds the mutex should be set. This will be the greater of the holding task's base priority and the priority of the highest priority task that is waiting to obtain the mutex. */ if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) 8016c8c: 69bb ldr r3, [r7, #24] 8016c8e: 6cdb ldr r3, [r3, #76] @ 0x4c 8016c90: 683a ldr r2, [r7, #0] 8016c92: 429a cmp r2, r3 8016c94: d902 bls.n 8016c9c { uxPriorityToUse = uxHighestPriorityWaitingTask; 8016c96: 683b ldr r3, [r7, #0] 8016c98: 61fb str r3, [r7, #28] 8016c9a: e002 b.n 8016ca2 } else { uxPriorityToUse = pxTCB->uxBasePriority; 8016c9c: 69bb ldr r3, [r7, #24] 8016c9e: 6cdb ldr r3, [r3, #76] @ 0x4c 8016ca0: 61fb str r3, [r7, #28] } /* Does the priority need to change? */ if( pxTCB->uxPriority != uxPriorityToUse ) 8016ca2: 69bb ldr r3, [r7, #24] 8016ca4: 6adb ldr r3, [r3, #44] @ 0x2c 8016ca6: 69fa ldr r2, [r7, #28] 8016ca8: 429a cmp r2, r3 8016caa: d04c beq.n 8016d46 { /* Only disinherit if no other mutexes are held. This is a simplification in the priority inheritance implementation. If the task that holds the mutex is also holding other mutexes then the other mutexes may have caused the priority inheritance. */ if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) 8016cac: 69bb ldr r3, [r7, #24] 8016cae: 6d1b ldr r3, [r3, #80] @ 0x50 8016cb0: 697a ldr r2, [r7, #20] 8016cb2: 429a cmp r2, r3 8016cb4: d147 bne.n 8016d46 { /* If a task has timed out because it already holds the mutex it was trying to obtain then it cannot of inherited its own priority. */ configASSERT( pxTCB != pxCurrentTCB ); 8016cb6: 4b26 ldr r3, [pc, #152] @ (8016d50 ) 8016cb8: 681b ldr r3, [r3, #0] 8016cba: 69ba ldr r2, [r7, #24] 8016cbc: 429a cmp r2, r3 8016cbe: d10b bne.n 8016cd8 __asm volatile 8016cc0: f04f 0350 mov.w r3, #80 @ 0x50 8016cc4: f383 8811 msr BASEPRI, r3 8016cc8: f3bf 8f6f isb sy 8016ccc: f3bf 8f4f dsb sy 8016cd0: 60bb str r3, [r7, #8] } 8016cd2: bf00 nop 8016cd4: bf00 nop 8016cd6: e7fd b.n 8016cd4 /* Disinherit the priority, remembering the previous priority to facilitate determining the subject task's state. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); uxPriorityUsedOnEntry = pxTCB->uxPriority; 8016cd8: 69bb ldr r3, [r7, #24] 8016cda: 6adb ldr r3, [r3, #44] @ 0x2c 8016cdc: 613b str r3, [r7, #16] pxTCB->uxPriority = uxPriorityToUse; 8016cde: 69bb ldr r3, [r7, #24] 8016ce0: 69fa ldr r2, [r7, #28] 8016ce2: 62da str r2, [r3, #44] @ 0x2c /* Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 8016ce4: 69bb ldr r3, [r7, #24] 8016ce6: 699b ldr r3, [r3, #24] 8016ce8: 2b00 cmp r3, #0 8016cea: db04 blt.n 8016cf6 { listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016cec: 69fb ldr r3, [r7, #28] 8016cee: f1c3 0238 rsb r2, r3, #56 @ 0x38 8016cf2: 69bb ldr r3, [r7, #24] 8016cf4: 619a str r2, [r3, #24] then the task that holds the mutex could be in either the Ready, Blocked or Suspended states. Only remove the task from its current state list if it is in the Ready state as the task's priority is going to change and there is one Ready list per priority. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) 8016cf6: 69bb ldr r3, [r7, #24] 8016cf8: 6959 ldr r1, [r3, #20] 8016cfa: 693a ldr r2, [r7, #16] 8016cfc: 4613 mov r3, r2 8016cfe: 009b lsls r3, r3, #2 8016d00: 4413 add r3, r2 8016d02: 009b lsls r3, r3, #2 8016d04: 4a13 ldr r2, [pc, #76] @ (8016d54 ) 8016d06: 4413 add r3, r2 8016d08: 4299 cmp r1, r3 8016d0a: d11c bne.n 8016d46 { if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016d0c: 69bb ldr r3, [r7, #24] 8016d0e: 3304 adds r3, #4 8016d10: 4618 mov r0, r3 8016d12: f7fd fe8b bl 8014a2c else { mtCOVERAGE_TEST_MARKER(); } prvAddTaskToReadyList( pxTCB ); 8016d16: 69bb ldr r3, [r7, #24] 8016d18: 6ada ldr r2, [r3, #44] @ 0x2c 8016d1a: 4b0f ldr r3, [pc, #60] @ (8016d58 ) 8016d1c: 681b ldr r3, [r3, #0] 8016d1e: 429a cmp r2, r3 8016d20: d903 bls.n 8016d2a 8016d22: 69bb ldr r3, [r7, #24] 8016d24: 6adb ldr r3, [r3, #44] @ 0x2c 8016d26: 4a0c ldr r2, [pc, #48] @ (8016d58 ) 8016d28: 6013 str r3, [r2, #0] 8016d2a: 69bb ldr r3, [r7, #24] 8016d2c: 6ada ldr r2, [r3, #44] @ 0x2c 8016d2e: 4613 mov r3, r2 8016d30: 009b lsls r3, r3, #2 8016d32: 4413 add r3, r2 8016d34: 009b lsls r3, r3, #2 8016d36: 4a07 ldr r2, [pc, #28] @ (8016d54 ) 8016d38: 441a add r2, r3 8016d3a: 69bb ldr r3, [r7, #24] 8016d3c: 3304 adds r3, #4 8016d3e: 4619 mov r1, r3 8016d40: 4610 mov r0, r2 8016d42: f7fd fe16 bl 8014972 } else { mtCOVERAGE_TEST_MARKER(); } } 8016d46: bf00 nop 8016d48: 3720 adds r7, #32 8016d4a: 46bd mov sp, r7 8016d4c: bd80 pop {r7, pc} 8016d4e: bf00 nop 8016d50: 240029f8 .word 0x240029f8 8016d54: 240029fc .word 0x240029fc 8016d58: 24002ed4 .word 0x24002ed4 08016d5c : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) TaskHandle_t pvTaskIncrementMutexHeldCount( void ) { 8016d5c: b480 push {r7} 8016d5e: af00 add r7, sp, #0 /* If xSemaphoreCreateMutex() is called before any tasks have been created then pxCurrentTCB will be NULL. */ if( pxCurrentTCB != NULL ) 8016d60: 4b07 ldr r3, [pc, #28] @ (8016d80 ) 8016d62: 681b ldr r3, [r3, #0] 8016d64: 2b00 cmp r3, #0 8016d66: d004 beq.n 8016d72 { ( pxCurrentTCB->uxMutexesHeld )++; 8016d68: 4b05 ldr r3, [pc, #20] @ (8016d80 ) 8016d6a: 681b ldr r3, [r3, #0] 8016d6c: 6d1a ldr r2, [r3, #80] @ 0x50 8016d6e: 3201 adds r2, #1 8016d70: 651a str r2, [r3, #80] @ 0x50 } return pxCurrentTCB; 8016d72: 4b03 ldr r3, [pc, #12] @ (8016d80 ) 8016d74: 681b ldr r3, [r3, #0] } 8016d76: 4618 mov r0, r3 8016d78: 46bd mov sp, r7 8016d7a: f85d 7b04 ldr.w r7, [sp], #4 8016d7e: 4770 bx lr 8016d80: 240029f8 .word 0x240029f8 08016d84 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) { 8016d84: b580 push {r7, lr} 8016d86: b086 sub sp, #24 8016d88: af00 add r7, sp, #0 8016d8a: 60f8 str r0, [r7, #12] 8016d8c: 60b9 str r1, [r7, #8] 8016d8e: 607a str r2, [r7, #4] 8016d90: 603b str r3, [r7, #0] BaseType_t xReturn; taskENTER_CRITICAL(); 8016d92: f000 fff1 bl 8017d78 { /* Only block if a notification is not already pending. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 8016d96: 4b29 ldr r3, [pc, #164] @ (8016e3c ) 8016d98: 681b ldr r3, [r3, #0] 8016d9a: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016d9e: b2db uxtb r3, r3 8016da0: 2b02 cmp r3, #2 8016da2: d01c beq.n 8016dde { /* Clear bits in the task's notification value as bits may get set by the notifying task or interrupt. This can be used to clear the value to zero. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry; 8016da4: 4b25 ldr r3, [pc, #148] @ (8016e3c ) 8016da6: 681b ldr r3, [r3, #0] 8016da8: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 8016dac: 68fa ldr r2, [r7, #12] 8016dae: 43d2 mvns r2, r2 8016db0: 400a ands r2, r1 8016db2: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 /* Mark this task as waiting for a notification. */ pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION; 8016db6: 4b21 ldr r3, [pc, #132] @ (8016e3c ) 8016db8: 681b ldr r3, [r3, #0] 8016dba: 2201 movs r2, #1 8016dbc: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 if( xTicksToWait > ( TickType_t ) 0 ) 8016dc0: 683b ldr r3, [r7, #0] 8016dc2: 2b00 cmp r3, #0 8016dc4: d00b beq.n 8016dde { prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 8016dc6: 2101 movs r1, #1 8016dc8: 6838 ldr r0, [r7, #0] 8016dca: f000 fa09 bl 80171e0 /* All ports are written to allow a yield in a critical section (some will yield immediately, others wait until the critical section exits) - but it is not something that application code should ever do. */ portYIELD_WITHIN_API(); 8016dce: 4b1c ldr r3, [pc, #112] @ (8016e40 ) 8016dd0: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016dd4: 601a str r2, [r3, #0] 8016dd6: f3bf 8f4f dsb sy 8016dda: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016dde: f000 fffd bl 8017ddc taskENTER_CRITICAL(); 8016de2: f000 ffc9 bl 8017d78 { traceTASK_NOTIFY_WAIT(); if( pulNotificationValue != NULL ) 8016de6: 687b ldr r3, [r7, #4] 8016de8: 2b00 cmp r3, #0 8016dea: d005 beq.n 8016df8 { /* Output the current notification value, which may or may not have changed. */ *pulNotificationValue = pxCurrentTCB->ulNotifiedValue; 8016dec: 4b13 ldr r3, [pc, #76] @ (8016e3c ) 8016dee: 681b ldr r3, [r3, #0] 8016df0: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016df4: 687b ldr r3, [r7, #4] 8016df6: 601a str r2, [r3, #0] /* If ucNotifyValue is set then either the task never entered the blocked state (because a notification was already pending) or the task unblocked because of a notification. Otherwise the task unblocked because of a timeout. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 8016df8: 4b10 ldr r3, [pc, #64] @ (8016e3c ) 8016dfa: 681b ldr r3, [r3, #0] 8016dfc: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016e00: b2db uxtb r3, r3 8016e02: 2b02 cmp r3, #2 8016e04: d002 beq.n 8016e0c { /* A notification was not received. */ xReturn = pdFALSE; 8016e06: 2300 movs r3, #0 8016e08: 617b str r3, [r7, #20] 8016e0a: e00a b.n 8016e22 } else { /* A notification was already pending or a notification was received while the task was waiting. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit; 8016e0c: 4b0b ldr r3, [pc, #44] @ (8016e3c ) 8016e0e: 681b ldr r3, [r3, #0] 8016e10: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 8016e14: 68ba ldr r2, [r7, #8] 8016e16: 43d2 mvns r2, r2 8016e18: 400a ands r2, r1 8016e1a: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 xReturn = pdTRUE; 8016e1e: 2301 movs r3, #1 8016e20: 617b str r3, [r7, #20] } pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8016e22: 4b06 ldr r3, [pc, #24] @ (8016e3c ) 8016e24: 681b ldr r3, [r3, #0] 8016e26: 2200 movs r2, #0 8016e28: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 } taskEXIT_CRITICAL(); 8016e2c: f000 ffd6 bl 8017ddc return xReturn; 8016e30: 697b ldr r3, [r7, #20] } 8016e32: 4618 mov r0, r3 8016e34: 3718 adds r7, #24 8016e36: 46bd mov sp, r7 8016e38: bd80 pop {r7, pc} 8016e3a: bf00 nop 8016e3c: 240029f8 .word 0x240029f8 8016e40: e000ed04 .word 0xe000ed04 08016e44 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) { 8016e44: b580 push {r7, lr} 8016e46: b08a sub sp, #40 @ 0x28 8016e48: af00 add r7, sp, #0 8016e4a: 60f8 str r0, [r7, #12] 8016e4c: 60b9 str r1, [r7, #8] 8016e4e: 603b str r3, [r7, #0] 8016e50: 4613 mov r3, r2 8016e52: 71fb strb r3, [r7, #7] TCB_t * pxTCB; BaseType_t xReturn = pdPASS; 8016e54: 2301 movs r3, #1 8016e56: 627b str r3, [r7, #36] @ 0x24 uint8_t ucOriginalNotifyState; configASSERT( xTaskToNotify ); 8016e58: 68fb ldr r3, [r7, #12] 8016e5a: 2b00 cmp r3, #0 8016e5c: d10b bne.n 8016e76 __asm volatile 8016e5e: f04f 0350 mov.w r3, #80 @ 0x50 8016e62: f383 8811 msr BASEPRI, r3 8016e66: f3bf 8f6f isb sy 8016e6a: f3bf 8f4f dsb sy 8016e6e: 61bb str r3, [r7, #24] } 8016e70: bf00 nop 8016e72: bf00 nop 8016e74: e7fd b.n 8016e72 pxTCB = xTaskToNotify; 8016e76: 68fb ldr r3, [r7, #12] 8016e78: 623b str r3, [r7, #32] taskENTER_CRITICAL(); 8016e7a: f000 ff7d bl 8017d78 { if( pulPreviousNotificationValue != NULL ) 8016e7e: 683b ldr r3, [r7, #0] 8016e80: 2b00 cmp r3, #0 8016e82: d004 beq.n 8016e8e { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 8016e84: 6a3b ldr r3, [r7, #32] 8016e86: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016e8a: 683b ldr r3, [r7, #0] 8016e8c: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 8016e8e: 6a3b ldr r3, [r7, #32] 8016e90: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016e94: 77fb strb r3, [r7, #31] pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 8016e96: 6a3b ldr r3, [r7, #32] 8016e98: 2202 movs r2, #2 8016e9a: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 8016e9e: 79fb ldrb r3, [r7, #7] 8016ea0: 2b04 cmp r3, #4 8016ea2: d82e bhi.n 8016f02 8016ea4: a201 add r2, pc, #4 @ (adr r2, 8016eac ) 8016ea6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016eaa: bf00 nop 8016eac: 08016f27 .word 0x08016f27 8016eb0: 08016ec1 .word 0x08016ec1 8016eb4: 08016ed3 .word 0x08016ed3 8016eb8: 08016ee3 .word 0x08016ee3 8016ebc: 08016eed .word 0x08016eed { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 8016ec0: 6a3b ldr r3, [r7, #32] 8016ec2: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016ec6: 68bb ldr r3, [r7, #8] 8016ec8: 431a orrs r2, r3 8016eca: 6a3b ldr r3, [r7, #32] 8016ecc: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016ed0: e02c b.n 8016f2c case eIncrement : ( pxTCB->ulNotifiedValue )++; 8016ed2: 6a3b ldr r3, [r7, #32] 8016ed4: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016ed8: 1c5a adds r2, r3, #1 8016eda: 6a3b ldr r3, [r7, #32] 8016edc: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016ee0: e024 b.n 8016f2c case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 8016ee2: 6a3b ldr r3, [r7, #32] 8016ee4: 68ba ldr r2, [r7, #8] 8016ee6: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016eea: e01f b.n 8016f2c case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 8016eec: 7ffb ldrb r3, [r7, #31] 8016eee: 2b02 cmp r3, #2 8016ef0: d004 beq.n 8016efc { pxTCB->ulNotifiedValue = ulValue; 8016ef2: 6a3b ldr r3, [r7, #32] 8016ef4: 68ba ldr r2, [r7, #8] 8016ef6: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 8016efa: e017 b.n 8016f2c xReturn = pdFAIL; 8016efc: 2300 movs r3, #0 8016efe: 627b str r3, [r7, #36] @ 0x24 break; 8016f00: e014 b.n 8016f2c default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 8016f02: 6a3b ldr r3, [r7, #32] 8016f04: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016f08: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8016f0c: d00d beq.n 8016f2a __asm volatile 8016f0e: f04f 0350 mov.w r3, #80 @ 0x50 8016f12: f383 8811 msr BASEPRI, r3 8016f16: f3bf 8f6f isb sy 8016f1a: f3bf 8f4f dsb sy 8016f1e: 617b str r3, [r7, #20] } 8016f20: bf00 nop 8016f22: bf00 nop 8016f24: e7fd b.n 8016f22 break; 8016f26: bf00 nop 8016f28: e000 b.n 8016f2c break; 8016f2a: bf00 nop traceTASK_NOTIFY(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 8016f2c: 7ffb ldrb r3, [r7, #31] 8016f2e: 2b01 cmp r3, #1 8016f30: d13b bne.n 8016faa { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8016f32: 6a3b ldr r3, [r7, #32] 8016f34: 3304 adds r3, #4 8016f36: 4618 mov r0, r3 8016f38: f7fd fd78 bl 8014a2c prvAddTaskToReadyList( pxTCB ); 8016f3c: 6a3b ldr r3, [r7, #32] 8016f3e: 6ada ldr r2, [r3, #44] @ 0x2c 8016f40: 4b1d ldr r3, [pc, #116] @ (8016fb8 ) 8016f42: 681b ldr r3, [r3, #0] 8016f44: 429a cmp r2, r3 8016f46: d903 bls.n 8016f50 8016f48: 6a3b ldr r3, [r7, #32] 8016f4a: 6adb ldr r3, [r3, #44] @ 0x2c 8016f4c: 4a1a ldr r2, [pc, #104] @ (8016fb8 ) 8016f4e: 6013 str r3, [r2, #0] 8016f50: 6a3b ldr r3, [r7, #32] 8016f52: 6ada ldr r2, [r3, #44] @ 0x2c 8016f54: 4613 mov r3, r2 8016f56: 009b lsls r3, r3, #2 8016f58: 4413 add r3, r2 8016f5a: 009b lsls r3, r3, #2 8016f5c: 4a17 ldr r2, [pc, #92] @ (8016fbc ) 8016f5e: 441a add r2, r3 8016f60: 6a3b ldr r3, [r7, #32] 8016f62: 3304 adds r3, #4 8016f64: 4619 mov r1, r3 8016f66: 4610 mov r0, r2 8016f68: f7fd fd03 bl 8014972 /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 8016f6c: 6a3b ldr r3, [r7, #32] 8016f6e: 6a9b ldr r3, [r3, #40] @ 0x28 8016f70: 2b00 cmp r3, #0 8016f72: d00b beq.n 8016f8c __asm volatile 8016f74: f04f 0350 mov.w r3, #80 @ 0x50 8016f78: f383 8811 msr BASEPRI, r3 8016f7c: f3bf 8f6f isb sy 8016f80: f3bf 8f4f dsb sy 8016f84: 613b str r3, [r7, #16] } 8016f86: bf00 nop 8016f88: bf00 nop 8016f8a: e7fd b.n 8016f88 earliest possible time. */ prvResetNextTaskUnblockTime(); } #endif if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 8016f8c: 6a3b ldr r3, [r7, #32] 8016f8e: 6ada ldr r2, [r3, #44] @ 0x2c 8016f90: 4b0b ldr r3, [pc, #44] @ (8016fc0 ) 8016f92: 681b ldr r3, [r3, #0] 8016f94: 6adb ldr r3, [r3, #44] @ 0x2c 8016f96: 429a cmp r2, r3 8016f98: d907 bls.n 8016faa { /* The notified task has a priority above the currently executing task so a yield is required. */ taskYIELD_IF_USING_PREEMPTION(); 8016f9a: 4b0a ldr r3, [pc, #40] @ (8016fc4 ) 8016f9c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016fa0: 601a str r2, [r3, #0] 8016fa2: f3bf 8f4f dsb sy 8016fa6: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016faa: f000 ff17 bl 8017ddc return xReturn; 8016fae: 6a7b ldr r3, [r7, #36] @ 0x24 } 8016fb0: 4618 mov r0, r3 8016fb2: 3728 adds r7, #40 @ 0x28 8016fb4: 46bd mov sp, r7 8016fb6: bd80 pop {r7, pc} 8016fb8: 24002ed4 .word 0x24002ed4 8016fbc: 240029fc .word 0x240029fc 8016fc0: 240029f8 .word 0x240029f8 8016fc4: e000ed04 .word 0xe000ed04 08016fc8 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) { 8016fc8: b580 push {r7, lr} 8016fca: b08e sub sp, #56 @ 0x38 8016fcc: af00 add r7, sp, #0 8016fce: 60f8 str r0, [r7, #12] 8016fd0: 60b9 str r1, [r7, #8] 8016fd2: 603b str r3, [r7, #0] 8016fd4: 4613 mov r3, r2 8016fd6: 71fb strb r3, [r7, #7] TCB_t * pxTCB; uint8_t ucOriginalNotifyState; BaseType_t xReturn = pdPASS; 8016fd8: 2301 movs r3, #1 8016fda: 637b str r3, [r7, #52] @ 0x34 UBaseType_t uxSavedInterruptStatus; configASSERT( xTaskToNotify ); 8016fdc: 68fb ldr r3, [r7, #12] 8016fde: 2b00 cmp r3, #0 8016fe0: d10b bne.n 8016ffa __asm volatile 8016fe2: f04f 0350 mov.w r3, #80 @ 0x50 8016fe6: f383 8811 msr BASEPRI, r3 8016fea: f3bf 8f6f isb sy 8016fee: f3bf 8f4f dsb sy 8016ff2: 627b str r3, [r7, #36] @ 0x24 } 8016ff4: bf00 nop 8016ff6: bf00 nop 8016ff8: e7fd b.n 8016ff6 below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8016ffa: f000 ff9d bl 8017f38 pxTCB = xTaskToNotify; 8016ffe: 68fb ldr r3, [r7, #12] 8017000: 633b str r3, [r7, #48] @ 0x30 __asm volatile 8017002: f3ef 8211 mrs r2, BASEPRI 8017006: f04f 0350 mov.w r3, #80 @ 0x50 801700a: f383 8811 msr BASEPRI, r3 801700e: f3bf 8f6f isb sy 8017012: f3bf 8f4f dsb sy 8017016: 623a str r2, [r7, #32] 8017018: 61fb str r3, [r7, #28] return ulOriginalBASEPRI; 801701a: 6a3b ldr r3, [r7, #32] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 801701c: 62fb str r3, [r7, #44] @ 0x2c { if( pulPreviousNotificationValue != NULL ) 801701e: 683b ldr r3, [r7, #0] 8017020: 2b00 cmp r3, #0 8017022: d004 beq.n 801702e { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 8017024: 6b3b ldr r3, [r7, #48] @ 0x30 8017026: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 801702a: 683b ldr r3, [r7, #0] 801702c: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 801702e: 6b3b ldr r3, [r7, #48] @ 0x30 8017030: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8017034: f887 302b strb.w r3, [r7, #43] @ 0x2b pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 8017038: 6b3b ldr r3, [r7, #48] @ 0x30 801703a: 2202 movs r2, #2 801703c: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 8017040: 79fb ldrb r3, [r7, #7] 8017042: 2b04 cmp r3, #4 8017044: d82e bhi.n 80170a4 8017046: a201 add r2, pc, #4 @ (adr r2, 801704c ) 8017048: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801704c: 080170c9 .word 0x080170c9 8017050: 08017061 .word 0x08017061 8017054: 08017073 .word 0x08017073 8017058: 08017083 .word 0x08017083 801705c: 0801708d .word 0x0801708d { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 8017060: 6b3b ldr r3, [r7, #48] @ 0x30 8017062: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8017066: 68bb ldr r3, [r7, #8] 8017068: 431a orrs r2, r3 801706a: 6b3b ldr r3, [r7, #48] @ 0x30 801706c: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8017070: e02d b.n 80170ce case eIncrement : ( pxTCB->ulNotifiedValue )++; 8017072: 6b3b ldr r3, [r7, #48] @ 0x30 8017074: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8017078: 1c5a adds r2, r3, #1 801707a: 6b3b ldr r3, [r7, #48] @ 0x30 801707c: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8017080: e025 b.n 80170ce case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 8017082: 6b3b ldr r3, [r7, #48] @ 0x30 8017084: 68ba ldr r2, [r7, #8] 8017086: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 801708a: e020 b.n 80170ce case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 801708c: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8017090: 2b02 cmp r3, #2 8017092: d004 beq.n 801709e { pxTCB->ulNotifiedValue = ulValue; 8017094: 6b3b ldr r3, [r7, #48] @ 0x30 8017096: 68ba ldr r2, [r7, #8] 8017098: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 801709c: e017 b.n 80170ce xReturn = pdFAIL; 801709e: 2300 movs r3, #0 80170a0: 637b str r3, [r7, #52] @ 0x34 break; 80170a2: e014 b.n 80170ce default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 80170a4: 6b3b ldr r3, [r7, #48] @ 0x30 80170a6: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 80170aa: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80170ae: d00d beq.n 80170cc __asm volatile 80170b0: f04f 0350 mov.w r3, #80 @ 0x50 80170b4: f383 8811 msr BASEPRI, r3 80170b8: f3bf 8f6f isb sy 80170bc: f3bf 8f4f dsb sy 80170c0: 61bb str r3, [r7, #24] } 80170c2: bf00 nop 80170c4: bf00 nop 80170c6: e7fd b.n 80170c4 break; 80170c8: bf00 nop 80170ca: e000 b.n 80170ce break; 80170cc: bf00 nop traceTASK_NOTIFY_FROM_ISR(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 80170ce: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 80170d2: 2b01 cmp r3, #1 80170d4: d147 bne.n 8017166 { /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 80170d6: 6b3b ldr r3, [r7, #48] @ 0x30 80170d8: 6a9b ldr r3, [r3, #40] @ 0x28 80170da: 2b00 cmp r3, #0 80170dc: d00b beq.n 80170f6 __asm volatile 80170de: f04f 0350 mov.w r3, #80 @ 0x50 80170e2: f383 8811 msr BASEPRI, r3 80170e6: f3bf 8f6f isb sy 80170ea: f3bf 8f4f dsb sy 80170ee: 617b str r3, [r7, #20] } 80170f0: bf00 nop 80170f2: bf00 nop 80170f4: e7fd b.n 80170f2 if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80170f6: 4b21 ldr r3, [pc, #132] @ (801717c ) 80170f8: 681b ldr r3, [r3, #0] 80170fa: 2b00 cmp r3, #0 80170fc: d11d bne.n 801713a { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80170fe: 6b3b ldr r3, [r7, #48] @ 0x30 8017100: 3304 adds r3, #4 8017102: 4618 mov r0, r3 8017104: f7fd fc92 bl 8014a2c prvAddTaskToReadyList( pxTCB ); 8017108: 6b3b ldr r3, [r7, #48] @ 0x30 801710a: 6ada ldr r2, [r3, #44] @ 0x2c 801710c: 4b1c ldr r3, [pc, #112] @ (8017180 ) 801710e: 681b ldr r3, [r3, #0] 8017110: 429a cmp r2, r3 8017112: d903 bls.n 801711c 8017114: 6b3b ldr r3, [r7, #48] @ 0x30 8017116: 6adb ldr r3, [r3, #44] @ 0x2c 8017118: 4a19 ldr r2, [pc, #100] @ (8017180 ) 801711a: 6013 str r3, [r2, #0] 801711c: 6b3b ldr r3, [r7, #48] @ 0x30 801711e: 6ada ldr r2, [r3, #44] @ 0x2c 8017120: 4613 mov r3, r2 8017122: 009b lsls r3, r3, #2 8017124: 4413 add r3, r2 8017126: 009b lsls r3, r3, #2 8017128: 4a16 ldr r2, [pc, #88] @ (8017184 ) 801712a: 441a add r2, r3 801712c: 6b3b ldr r3, [r7, #48] @ 0x30 801712e: 3304 adds r3, #4 8017130: 4619 mov r1, r3 8017132: 4610 mov r0, r2 8017134: f7fd fc1d bl 8014972 8017138: e005 b.n 8017146 } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); 801713a: 6b3b ldr r3, [r7, #48] @ 0x30 801713c: 3318 adds r3, #24 801713e: 4619 mov r1, r3 8017140: 4811 ldr r0, [pc, #68] @ (8017188 ) 8017142: f7fd fc16 bl 8014972 } if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 8017146: 6b3b ldr r3, [r7, #48] @ 0x30 8017148: 6ada ldr r2, [r3, #44] @ 0x2c 801714a: 4b10 ldr r3, [pc, #64] @ (801718c ) 801714c: 681b ldr r3, [r3, #0] 801714e: 6adb ldr r3, [r3, #44] @ 0x2c 8017150: 429a cmp r2, r3 8017152: d908 bls.n 8017166 { /* The notified task has a priority above the currently executing task so a yield is required. */ if( pxHigherPriorityTaskWoken != NULL ) 8017154: 6c3b ldr r3, [r7, #64] @ 0x40 8017156: 2b00 cmp r3, #0 8017158: d002 beq.n 8017160 { *pxHigherPriorityTaskWoken = pdTRUE; 801715a: 6c3b ldr r3, [r7, #64] @ 0x40 801715c: 2201 movs r2, #1 801715e: 601a str r2, [r3, #0] } /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 8017160: 4b0b ldr r3, [pc, #44] @ (8017190 ) 8017162: 2201 movs r2, #1 8017164: 601a str r2, [r3, #0] 8017166: 6afb ldr r3, [r7, #44] @ 0x2c 8017168: 613b str r3, [r7, #16] __asm volatile 801716a: 693b ldr r3, [r7, #16] 801716c: f383 8811 msr BASEPRI, r3 } 8017170: bf00 nop } } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 8017172: 6b7b ldr r3, [r7, #52] @ 0x34 } 8017174: 4618 mov r0, r3 8017176: 3738 adds r7, #56 @ 0x38 8017178: 46bd mov sp, r7 801717a: bd80 pop {r7, pc} 801717c: 24002ef4 .word 0x24002ef4 8017180: 24002ed4 .word 0x24002ed4 8017184: 240029fc .word 0x240029fc 8017188: 24002e8c .word 0x24002e8c 801718c: 240029f8 .word 0x240029f8 8017190: 24002ee0 .word 0x24002ee0 08017194 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask ) { 8017194: b580 push {r7, lr} 8017196: b084 sub sp, #16 8017198: af00 add r7, sp, #0 801719a: 6078 str r0, [r7, #4] TCB_t *pxTCB; BaseType_t xReturn; /* If null is passed in here then it is the calling task that is having its notification state cleared. */ pxTCB = prvGetTCBFromHandle( xTask ); 801719c: 687b ldr r3, [r7, #4] 801719e: 2b00 cmp r3, #0 80171a0: d102 bne.n 80171a8 80171a2: 4b0e ldr r3, [pc, #56] @ (80171dc ) 80171a4: 681b ldr r3, [r3, #0] 80171a6: e000 b.n 80171aa 80171a8: 687b ldr r3, [r7, #4] 80171aa: 60bb str r3, [r7, #8] taskENTER_CRITICAL(); 80171ac: f000 fde4 bl 8017d78 { if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED ) 80171b0: 68bb ldr r3, [r7, #8] 80171b2: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 80171b6: b2db uxtb r3, r3 80171b8: 2b02 cmp r3, #2 80171ba: d106 bne.n 80171ca { pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 80171bc: 68bb ldr r3, [r7, #8] 80171be: 2200 movs r2, #0 80171c0: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 xReturn = pdPASS; 80171c4: 2301 movs r3, #1 80171c6: 60fb str r3, [r7, #12] 80171c8: e001 b.n 80171ce } else { xReturn = pdFAIL; 80171ca: 2300 movs r3, #0 80171cc: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 80171ce: f000 fe05 bl 8017ddc return xReturn; 80171d2: 68fb ldr r3, [r7, #12] } 80171d4: 4618 mov r0, r3 80171d6: 3710 adds r7, #16 80171d8: 46bd mov sp, r7 80171da: bd80 pop {r7, pc} 80171dc: 240029f8 .word 0x240029f8 080171e0 : #endif /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { 80171e0: b580 push {r7, lr} 80171e2: b084 sub sp, #16 80171e4: af00 add r7, sp, #0 80171e6: 6078 str r0, [r7, #4] 80171e8: 6039 str r1, [r7, #0] TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; 80171ea: 4b21 ldr r3, [pc, #132] @ (8017270 ) 80171ec: 681b ldr r3, [r3, #0] 80171ee: 60fb str r3, [r7, #12] } #endif /* Remove the task from the ready list before adding it to the blocked list as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 80171f0: 4b20 ldr r3, [pc, #128] @ (8017274 ) 80171f2: 681b ldr r3, [r3, #0] 80171f4: 3304 adds r3, #4 80171f6: 4618 mov r0, r3 80171f8: f7fd fc18 bl 8014a2c mtCOVERAGE_TEST_MARKER(); } #if ( INCLUDE_vTaskSuspend == 1 ) { if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) 80171fc: 687b ldr r3, [r7, #4] 80171fe: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8017202: d10a bne.n 801721a 8017204: 683b ldr r3, [r7, #0] 8017206: 2b00 cmp r3, #0 8017208: d007 beq.n 801721a { /* Add the task to the suspended task list instead of a delayed task list to ensure it is not woken by a timing event. It will block indefinitely. */ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 801720a: 4b1a ldr r3, [pc, #104] @ (8017274 ) 801720c: 681b ldr r3, [r3, #0] 801720e: 3304 adds r3, #4 8017210: 4619 mov r1, r3 8017212: 4819 ldr r0, [pc, #100] @ (8017278 ) 8017214: f7fd fbad bl 8014972 /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } 8017218: e026 b.n 8017268 xTimeToWake = xConstTickCount + xTicksToWait; 801721a: 68fa ldr r2, [r7, #12] 801721c: 687b ldr r3, [r7, #4] 801721e: 4413 add r3, r2 8017220: 60bb str r3, [r7, #8] listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 8017222: 4b14 ldr r3, [pc, #80] @ (8017274 ) 8017224: 681b ldr r3, [r3, #0] 8017226: 68ba ldr r2, [r7, #8] 8017228: 605a str r2, [r3, #4] if( xTimeToWake < xConstTickCount ) 801722a: 68ba ldr r2, [r7, #8] 801722c: 68fb ldr r3, [r7, #12] 801722e: 429a cmp r2, r3 8017230: d209 bcs.n 8017246 vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8017232: 4b12 ldr r3, [pc, #72] @ (801727c ) 8017234: 681a ldr r2, [r3, #0] 8017236: 4b0f ldr r3, [pc, #60] @ (8017274 ) 8017238: 681b ldr r3, [r3, #0] 801723a: 3304 adds r3, #4 801723c: 4619 mov r1, r3 801723e: 4610 mov r0, r2 8017240: f7fd fbbb bl 80149ba } 8017244: e010 b.n 8017268 vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8017246: 4b0e ldr r3, [pc, #56] @ (8017280 ) 8017248: 681a ldr r2, [r3, #0] 801724a: 4b0a ldr r3, [pc, #40] @ (8017274 ) 801724c: 681b ldr r3, [r3, #0] 801724e: 3304 adds r3, #4 8017250: 4619 mov r1, r3 8017252: 4610 mov r0, r2 8017254: f7fd fbb1 bl 80149ba if( xTimeToWake < xNextTaskUnblockTime ) 8017258: 4b0a ldr r3, [pc, #40] @ (8017284 ) 801725a: 681b ldr r3, [r3, #0] 801725c: 68ba ldr r2, [r7, #8] 801725e: 429a cmp r2, r3 8017260: d202 bcs.n 8017268 xNextTaskUnblockTime = xTimeToWake; 8017262: 4a08 ldr r2, [pc, #32] @ (8017284 ) 8017264: 68bb ldr r3, [r7, #8] 8017266: 6013 str r3, [r2, #0] } 8017268: bf00 nop 801726a: 3710 adds r7, #16 801726c: 46bd mov sp, r7 801726e: bd80 pop {r7, pc} 8017270: 24002ed0 .word 0x24002ed0 8017274: 240029f8 .word 0x240029f8 8017278: 24002eb8 .word 0x24002eb8 801727c: 24002e88 .word 0x24002e88 8017280: 24002e84 .word 0x24002e84 8017284: 24002eec .word 0x24002eec 08017288 : TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ BaseType_t xTimerCreateTimerTask( void ) { 8017288: b580 push {r7, lr} 801728a: b08a sub sp, #40 @ 0x28 801728c: af04 add r7, sp, #16 BaseType_t xReturn = pdFAIL; 801728e: 2300 movs r3, #0 8017290: 617b str r3, [r7, #20] /* This function is called when the scheduler is started if configUSE_TIMERS is set to 1. Check that the infrastructure used by the timer service task has been created/initialised. If timers have already been created then the initialisation will already have been performed. */ prvCheckForValidListAndQueue(); 8017292: f000 fbb1 bl 80179f8 if( xTimerQueue != NULL ) 8017296: 4b1d ldr r3, [pc, #116] @ (801730c ) 8017298: 681b ldr r3, [r3, #0] 801729a: 2b00 cmp r3, #0 801729c: d021 beq.n 80172e2 { #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxTimerTaskTCBBuffer = NULL; 801729e: 2300 movs r3, #0 80172a0: 60fb str r3, [r7, #12] StackType_t *pxTimerTaskStackBuffer = NULL; 80172a2: 2300 movs r3, #0 80172a4: 60bb str r3, [r7, #8] uint32_t ulTimerTaskStackSize; vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); 80172a6: 1d3a adds r2, r7, #4 80172a8: f107 0108 add.w r1, r7, #8 80172ac: f107 030c add.w r3, r7, #12 80172b0: 4618 mov r0, r3 80172b2: f7fd fb17 bl 80148e4 xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, 80172b6: 6879 ldr r1, [r7, #4] 80172b8: 68bb ldr r3, [r7, #8] 80172ba: 68fa ldr r2, [r7, #12] 80172bc: 9202 str r2, [sp, #8] 80172be: 9301 str r3, [sp, #4] 80172c0: 2302 movs r3, #2 80172c2: 9300 str r3, [sp, #0] 80172c4: 2300 movs r3, #0 80172c6: 460a mov r2, r1 80172c8: 4911 ldr r1, [pc, #68] @ (8017310 ) 80172ca: 4812 ldr r0, [pc, #72] @ (8017314 ) 80172cc: f7fe fd2f bl 8015d2e 80172d0: 4603 mov r3, r0 80172d2: 4a11 ldr r2, [pc, #68] @ (8017318 ) 80172d4: 6013 str r3, [r2, #0] NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, pxTimerTaskStackBuffer, pxTimerTaskTCBBuffer ); if( xTimerTaskHandle != NULL ) 80172d6: 4b10 ldr r3, [pc, #64] @ (8017318 ) 80172d8: 681b ldr r3, [r3, #0] 80172da: 2b00 cmp r3, #0 80172dc: d001 beq.n 80172e2 { xReturn = pdPASS; 80172de: 2301 movs r3, #1 80172e0: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } configASSERT( xReturn ); 80172e2: 697b ldr r3, [r7, #20] 80172e4: 2b00 cmp r3, #0 80172e6: d10b bne.n 8017300 __asm volatile 80172e8: f04f 0350 mov.w r3, #80 @ 0x50 80172ec: f383 8811 msr BASEPRI, r3 80172f0: f3bf 8f6f isb sy 80172f4: f3bf 8f4f dsb sy 80172f8: 613b str r3, [r7, #16] } 80172fa: bf00 nop 80172fc: bf00 nop 80172fe: e7fd b.n 80172fc return xReturn; 8017300: 697b ldr r3, [r7, #20] } 8017302: 4618 mov r0, r3 8017304: 3718 adds r7, #24 8017306: 46bd mov sp, r7 8017308: bd80 pop {r7, pc} 801730a: bf00 nop 801730c: 24002f28 .word 0x24002f28 8017310: 08018718 .word 0x08018718 8017314: 08017591 .word 0x08017591 8017318: 24002f2c .word 0x24002f2c 0801731c : TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) { 801731c: b580 push {r7, lr} 801731e: b088 sub sp, #32 8017320: af02 add r7, sp, #8 8017322: 60f8 str r0, [r7, #12] 8017324: 60b9 str r1, [r7, #8] 8017326: 607a str r2, [r7, #4] 8017328: 603b str r3, [r7, #0] Timer_t *pxNewTimer; pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */ 801732a: 202c movs r0, #44 @ 0x2c 801732c: f000 fe46 bl 8017fbc 8017330: 6178 str r0, [r7, #20] if( pxNewTimer != NULL ) 8017332: 697b ldr r3, [r7, #20] 8017334: 2b00 cmp r3, #0 8017336: d00d beq.n 8017354 { /* Status is thus far zero as the timer is not created statically and has not been started. The auto-reload bit may get set in prvInitialiseNewTimer. */ pxNewTimer->ucStatus = 0x00; 8017338: 697b ldr r3, [r7, #20] 801733a: 2200 movs r2, #0 801733c: f883 2028 strb.w r2, [r3, #40] @ 0x28 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); 8017340: 697b ldr r3, [r7, #20] 8017342: 9301 str r3, [sp, #4] 8017344: 6a3b ldr r3, [r7, #32] 8017346: 9300 str r3, [sp, #0] 8017348: 683b ldr r3, [r7, #0] 801734a: 687a ldr r2, [r7, #4] 801734c: 68b9 ldr r1, [r7, #8] 801734e: 68f8 ldr r0, [r7, #12] 8017350: f000 f845 bl 80173de } return pxNewTimer; 8017354: 697b ldr r3, [r7, #20] } 8017356: 4618 mov r0, r3 8017358: 3718 adds r7, #24 801735a: 46bd mov sp, r7 801735c: bd80 pop {r7, pc} 0801735e : const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) { 801735e: b580 push {r7, lr} 8017360: b08a sub sp, #40 @ 0x28 8017362: af02 add r7, sp, #8 8017364: 60f8 str r0, [r7, #12] 8017366: 60b9 str r1, [r7, #8] 8017368: 607a str r2, [r7, #4] 801736a: 603b str r3, [r7, #0] #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTimer_t equals the size of the real timer structure. */ volatile size_t xSize = sizeof( StaticTimer_t ); 801736c: 232c movs r3, #44 @ 0x2c 801736e: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( Timer_t ) ); 8017370: 693b ldr r3, [r7, #16] 8017372: 2b2c cmp r3, #44 @ 0x2c 8017374: d00b beq.n 801738e __asm volatile 8017376: f04f 0350 mov.w r3, #80 @ 0x50 801737a: f383 8811 msr BASEPRI, r3 801737e: f3bf 8f6f isb sy 8017382: f3bf 8f4f dsb sy 8017386: 61bb str r3, [r7, #24] } 8017388: bf00 nop 801738a: bf00 nop 801738c: e7fd b.n 801738a ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 801738e: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ /* A pointer to a StaticTimer_t structure MUST be provided, use it. */ configASSERT( pxTimerBuffer ); 8017390: 6afb ldr r3, [r7, #44] @ 0x2c 8017392: 2b00 cmp r3, #0 8017394: d10b bne.n 80173ae __asm volatile 8017396: f04f 0350 mov.w r3, #80 @ 0x50 801739a: f383 8811 msr BASEPRI, r3 801739e: f3bf 8f6f isb sy 80173a2: f3bf 8f4f dsb sy 80173a6: 617b str r3, [r7, #20] } 80173a8: bf00 nop 80173aa: bf00 nop 80173ac: e7fd b.n 80173aa pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */ 80173ae: 6afb ldr r3, [r7, #44] @ 0x2c 80173b0: 61fb str r3, [r7, #28] if( pxNewTimer != NULL ) 80173b2: 69fb ldr r3, [r7, #28] 80173b4: 2b00 cmp r3, #0 80173b6: d00d beq.n 80173d4 { /* Timers can be created statically or dynamically so note this timer was created statically in case it is later deleted. The auto-reload bit may get set in prvInitialiseNewTimer(). */ pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED; 80173b8: 69fb ldr r3, [r7, #28] 80173ba: 2202 movs r2, #2 80173bc: f883 2028 strb.w r2, [r3, #40] @ 0x28 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); 80173c0: 69fb ldr r3, [r7, #28] 80173c2: 9301 str r3, [sp, #4] 80173c4: 6abb ldr r3, [r7, #40] @ 0x28 80173c6: 9300 str r3, [sp, #0] 80173c8: 683b ldr r3, [r7, #0] 80173ca: 687a ldr r2, [r7, #4] 80173cc: 68b9 ldr r1, [r7, #8] 80173ce: 68f8 ldr r0, [r7, #12] 80173d0: f000 f805 bl 80173de } return pxNewTimer; 80173d4: 69fb ldr r3, [r7, #28] } 80173d6: 4618 mov r0, r3 80173d8: 3720 adds r7, #32 80173da: 46bd mov sp, r7 80173dc: bd80 pop {r7, pc} 080173de : const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) { 80173de: b580 push {r7, lr} 80173e0: b086 sub sp, #24 80173e2: af00 add r7, sp, #0 80173e4: 60f8 str r0, [r7, #12] 80173e6: 60b9 str r1, [r7, #8] 80173e8: 607a str r2, [r7, #4] 80173ea: 603b str r3, [r7, #0] /* 0 is not a valid value for xTimerPeriodInTicks. */ configASSERT( ( xTimerPeriodInTicks > 0 ) ); 80173ec: 68bb ldr r3, [r7, #8] 80173ee: 2b00 cmp r3, #0 80173f0: d10b bne.n 801740a __asm volatile 80173f2: f04f 0350 mov.w r3, #80 @ 0x50 80173f6: f383 8811 msr BASEPRI, r3 80173fa: f3bf 8f6f isb sy 80173fe: f3bf 8f4f dsb sy 8017402: 617b str r3, [r7, #20] } 8017404: bf00 nop 8017406: bf00 nop 8017408: e7fd b.n 8017406 if( pxNewTimer != NULL ) 801740a: 6a7b ldr r3, [r7, #36] @ 0x24 801740c: 2b00 cmp r3, #0 801740e: d01e beq.n 801744e { /* Ensure the infrastructure used by the timer service task has been created/initialised. */ prvCheckForValidListAndQueue(); 8017410: f000 faf2 bl 80179f8 /* Initialise the timer structure members using the function parameters. */ pxNewTimer->pcTimerName = pcTimerName; 8017414: 6a7b ldr r3, [r7, #36] @ 0x24 8017416: 68fa ldr r2, [r7, #12] 8017418: 601a str r2, [r3, #0] pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks; 801741a: 6a7b ldr r3, [r7, #36] @ 0x24 801741c: 68ba ldr r2, [r7, #8] 801741e: 619a str r2, [r3, #24] pxNewTimer->pvTimerID = pvTimerID; 8017420: 6a7b ldr r3, [r7, #36] @ 0x24 8017422: 683a ldr r2, [r7, #0] 8017424: 61da str r2, [r3, #28] pxNewTimer->pxCallbackFunction = pxCallbackFunction; 8017426: 6a7b ldr r3, [r7, #36] @ 0x24 8017428: 6a3a ldr r2, [r7, #32] 801742a: 621a str r2, [r3, #32] vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); 801742c: 6a7b ldr r3, [r7, #36] @ 0x24 801742e: 3304 adds r3, #4 8017430: 4618 mov r0, r3 8017432: f7fd fa91 bl 8014958 if( uxAutoReload != pdFALSE ) 8017436: 687b ldr r3, [r7, #4] 8017438: 2b00 cmp r3, #0 801743a: d008 beq.n 801744e { pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; 801743c: 6a7b ldr r3, [r7, #36] @ 0x24 801743e: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017442: f043 0304 orr.w r3, r3, #4 8017446: b2da uxtb r2, r3 8017448: 6a7b ldr r3, [r7, #36] @ 0x24 801744a: f883 2028 strb.w r2, [r3, #40] @ 0x28 } traceTIMER_CREATE( pxNewTimer ); } } 801744e: bf00 nop 8017450: 3718 adds r7, #24 8017452: 46bd mov sp, r7 8017454: bd80 pop {r7, pc} ... 08017458 : /*-----------------------------------------------------------*/ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) { 8017458: b580 push {r7, lr} 801745a: b08a sub sp, #40 @ 0x28 801745c: af00 add r7, sp, #0 801745e: 60f8 str r0, [r7, #12] 8017460: 60b9 str r1, [r7, #8] 8017462: 607a str r2, [r7, #4] 8017464: 603b str r3, [r7, #0] BaseType_t xReturn = pdFAIL; 8017466: 2300 movs r3, #0 8017468: 627b str r3, [r7, #36] @ 0x24 DaemonTaskMessage_t xMessage; configASSERT( xTimer ); 801746a: 68fb ldr r3, [r7, #12] 801746c: 2b00 cmp r3, #0 801746e: d10b bne.n 8017488 __asm volatile 8017470: f04f 0350 mov.w r3, #80 @ 0x50 8017474: f383 8811 msr BASEPRI, r3 8017478: f3bf 8f6f isb sy 801747c: f3bf 8f4f dsb sy 8017480: 623b str r3, [r7, #32] } 8017482: bf00 nop 8017484: bf00 nop 8017486: e7fd b.n 8017484 /* Send a message to the timer service task to perform a particular action on a particular timer definition. */ if( xTimerQueue != NULL ) 8017488: 4b19 ldr r3, [pc, #100] @ (80174f0 ) 801748a: 681b ldr r3, [r3, #0] 801748c: 2b00 cmp r3, #0 801748e: d02a beq.n 80174e6 { /* Send a command to the timer service task to start the xTimer timer. */ xMessage.xMessageID = xCommandID; 8017490: 68bb ldr r3, [r7, #8] 8017492: 613b str r3, [r7, #16] xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; 8017494: 687b ldr r3, [r7, #4] 8017496: 617b str r3, [r7, #20] xMessage.u.xTimerParameters.pxTimer = xTimer; 8017498: 68fb ldr r3, [r7, #12] 801749a: 61bb str r3, [r7, #24] if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) 801749c: 68bb ldr r3, [r7, #8] 801749e: 2b05 cmp r3, #5 80174a0: dc18 bgt.n 80174d4 { if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) 80174a2: f7ff fae1 bl 8016a68 80174a6: 4603 mov r3, r0 80174a8: 2b02 cmp r3, #2 80174aa: d109 bne.n 80174c0 { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); 80174ac: 4b10 ldr r3, [pc, #64] @ (80174f0 ) 80174ae: 6818 ldr r0, [r3, #0] 80174b0: f107 0110 add.w r1, r7, #16 80174b4: 2300 movs r3, #0 80174b6: 6b3a ldr r2, [r7, #48] @ 0x30 80174b8: f7fd fce0 bl 8014e7c 80174bc: 6278 str r0, [r7, #36] @ 0x24 80174be: e012 b.n 80174e6 } else { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); 80174c0: 4b0b ldr r3, [pc, #44] @ (80174f0 ) 80174c2: 6818 ldr r0, [r3, #0] 80174c4: f107 0110 add.w r1, r7, #16 80174c8: 2300 movs r3, #0 80174ca: 2200 movs r2, #0 80174cc: f7fd fcd6 bl 8014e7c 80174d0: 6278 str r0, [r7, #36] @ 0x24 80174d2: e008 b.n 80174e6 } } else { xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); 80174d4: 4b06 ldr r3, [pc, #24] @ (80174f0 ) 80174d6: 6818 ldr r0, [r3, #0] 80174d8: f107 0110 add.w r1, r7, #16 80174dc: 2300 movs r3, #0 80174de: 683a ldr r2, [r7, #0] 80174e0: f7fd fdce bl 8015080 80174e4: 6278 str r0, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 80174e6: 6a7b ldr r3, [r7, #36] @ 0x24 } 80174e8: 4618 mov r0, r3 80174ea: 3728 adds r7, #40 @ 0x28 80174ec: 46bd mov sp, r7 80174ee: bd80 pop {r7, pc} 80174f0: 24002f28 .word 0x24002f28 080174f4 : return pxTimer->pcTimerName; } /*-----------------------------------------------------------*/ static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) { 80174f4: b580 push {r7, lr} 80174f6: b088 sub sp, #32 80174f8: af02 add r7, sp, #8 80174fa: 6078 str r0, [r7, #4] 80174fc: 6039 str r1, [r7, #0] BaseType_t xResult; Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80174fe: 4b23 ldr r3, [pc, #140] @ (801758c ) 8017500: 681b ldr r3, [r3, #0] 8017502: 68db ldr r3, [r3, #12] 8017504: 68db ldr r3, [r3, #12] 8017506: 617b str r3, [r7, #20] /* Remove the timer from the list of active timers. A check has already been performed to ensure the list is not empty. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8017508: 697b ldr r3, [r7, #20] 801750a: 3304 adds r3, #4 801750c: 4618 mov r0, r3 801750e: f7fd fa8d bl 8014a2c traceTIMER_EXPIRED( pxTimer ); /* If the timer is an auto-reload timer then calculate the next expiry time and re-insert the timer in the list of active timers. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 8017512: 697b ldr r3, [r7, #20] 8017514: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017518: f003 0304 and.w r3, r3, #4 801751c: 2b00 cmp r3, #0 801751e: d023 beq.n 8017568 { /* The timer is inserted into a list using a time relative to anything other than the current time. It will therefore be inserted into the correct list relative to the time this task thinks it is now. */ if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) 8017520: 697b ldr r3, [r7, #20] 8017522: 699a ldr r2, [r3, #24] 8017524: 687b ldr r3, [r7, #4] 8017526: 18d1 adds r1, r2, r3 8017528: 687b ldr r3, [r7, #4] 801752a: 683a ldr r2, [r7, #0] 801752c: 6978 ldr r0, [r7, #20] 801752e: f000 f8d5 bl 80176dc 8017532: 4603 mov r3, r0 8017534: 2b00 cmp r3, #0 8017536: d020 beq.n 801757a { /* The timer expired before it was added to the active timer list. Reload it now. */ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 8017538: 2300 movs r3, #0 801753a: 9300 str r3, [sp, #0] 801753c: 2300 movs r3, #0 801753e: 687a ldr r2, [r7, #4] 8017540: 2100 movs r1, #0 8017542: 6978 ldr r0, [r7, #20] 8017544: f7ff ff88 bl 8017458 8017548: 6138 str r0, [r7, #16] configASSERT( xResult ); 801754a: 693b ldr r3, [r7, #16] 801754c: 2b00 cmp r3, #0 801754e: d114 bne.n 801757a __asm volatile 8017550: f04f 0350 mov.w r3, #80 @ 0x50 8017554: f383 8811 msr BASEPRI, r3 8017558: f3bf 8f6f isb sy 801755c: f3bf 8f4f dsb sy 8017560: 60fb str r3, [r7, #12] } 8017562: bf00 nop 8017564: bf00 nop 8017566: e7fd b.n 8017564 mtCOVERAGE_TEST_MARKER(); } } else { pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8017568: 697b ldr r3, [r7, #20] 801756a: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 801756e: f023 0301 bic.w r3, r3, #1 8017572: b2da uxtb r2, r3 8017574: 697b ldr r3, [r7, #20] 8017576: f883 2028 strb.w r2, [r3, #40] @ 0x28 mtCOVERAGE_TEST_MARKER(); } /* Call the timer callback. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 801757a: 697b ldr r3, [r7, #20] 801757c: 6a1b ldr r3, [r3, #32] 801757e: 6978 ldr r0, [r7, #20] 8017580: 4798 blx r3 } 8017582: bf00 nop 8017584: 3718 adds r7, #24 8017586: 46bd mov sp, r7 8017588: bd80 pop {r7, pc} 801758a: bf00 nop 801758c: 24002f20 .word 0x24002f20 08017590 : /*-----------------------------------------------------------*/ static portTASK_FUNCTION( prvTimerTask, pvParameters ) { 8017590: b580 push {r7, lr} 8017592: b084 sub sp, #16 8017594: af00 add r7, sp, #0 8017596: 6078 str r0, [r7, #4] for( ;; ) { /* Query the timers list to see if it contains any timers, and if so, obtain the time at which the next timer will expire. */ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8017598: f107 0308 add.w r3, r7, #8 801759c: 4618 mov r0, r3 801759e: f000 f859 bl 8017654 80175a2: 60f8 str r0, [r7, #12] /* If a timer has expired, process it. Otherwise, block this task until either a timer does expire, or a command is received. */ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); 80175a4: 68bb ldr r3, [r7, #8] 80175a6: 4619 mov r1, r3 80175a8: 68f8 ldr r0, [r7, #12] 80175aa: f000 f805 bl 80175b8 /* Empty the command queue. */ prvProcessReceivedCommands(); 80175ae: f000 f8d7 bl 8017760 xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 80175b2: bf00 nop 80175b4: e7f0 b.n 8017598 ... 080175b8 : } } /*-----------------------------------------------------------*/ static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) { 80175b8: b580 push {r7, lr} 80175ba: b084 sub sp, #16 80175bc: af00 add r7, sp, #0 80175be: 6078 str r0, [r7, #4] 80175c0: 6039 str r1, [r7, #0] TickType_t xTimeNow; BaseType_t xTimerListsWereSwitched; vTaskSuspendAll(); 80175c2: f7fe fe17 bl 80161f4 /* Obtain the time now to make an assessment as to whether the timer has expired or not. If obtaining the time causes the lists to switch then don't process this timer as any timers that remained in the list when the lists were switched will have been processed within the prvSampleTimeNow() function. */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 80175c6: f107 0308 add.w r3, r7, #8 80175ca: 4618 mov r0, r3 80175cc: f000 f866 bl 801769c 80175d0: 60f8 str r0, [r7, #12] if( xTimerListsWereSwitched == pdFALSE ) 80175d2: 68bb ldr r3, [r7, #8] 80175d4: 2b00 cmp r3, #0 80175d6: d130 bne.n 801763a { /* The tick count has not overflowed, has the timer expired? */ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) 80175d8: 683b ldr r3, [r7, #0] 80175da: 2b00 cmp r3, #0 80175dc: d10a bne.n 80175f4 80175de: 687a ldr r2, [r7, #4] 80175e0: 68fb ldr r3, [r7, #12] 80175e2: 429a cmp r2, r3 80175e4: d806 bhi.n 80175f4 { ( void ) xTaskResumeAll(); 80175e6: f7fe fe13 bl 8016210 prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); 80175ea: 68f9 ldr r1, [r7, #12] 80175ec: 6878 ldr r0, [r7, #4] 80175ee: f7ff ff81 bl 80174f4 else { ( void ) xTaskResumeAll(); } } } 80175f2: e024 b.n 801763e if( xListWasEmpty != pdFALSE ) 80175f4: 683b ldr r3, [r7, #0] 80175f6: 2b00 cmp r3, #0 80175f8: d008 beq.n 801760c xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); 80175fa: 4b13 ldr r3, [pc, #76] @ (8017648 ) 80175fc: 681b ldr r3, [r3, #0] 80175fe: 681b ldr r3, [r3, #0] 8017600: 2b00 cmp r3, #0 8017602: d101 bne.n 8017608 8017604: 2301 movs r3, #1 8017606: e000 b.n 801760a 8017608: 2300 movs r3, #0 801760a: 603b str r3, [r7, #0] vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); 801760c: 4b0f ldr r3, [pc, #60] @ (801764c ) 801760e: 6818 ldr r0, [r3, #0] 8017610: 687a ldr r2, [r7, #4] 8017612: 68fb ldr r3, [r7, #12] 8017614: 1ad3 subs r3, r2, r3 8017616: 683a ldr r2, [r7, #0] 8017618: 4619 mov r1, r3 801761a: f7fe f995 bl 8015948 if( xTaskResumeAll() == pdFALSE ) 801761e: f7fe fdf7 bl 8016210 8017622: 4603 mov r3, r0 8017624: 2b00 cmp r3, #0 8017626: d10a bne.n 801763e portYIELD_WITHIN_API(); 8017628: 4b09 ldr r3, [pc, #36] @ (8017650 ) 801762a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801762e: 601a str r2, [r3, #0] 8017630: f3bf 8f4f dsb sy 8017634: f3bf 8f6f isb sy } 8017638: e001 b.n 801763e ( void ) xTaskResumeAll(); 801763a: f7fe fde9 bl 8016210 } 801763e: bf00 nop 8017640: 3710 adds r7, #16 8017642: 46bd mov sp, r7 8017644: bd80 pop {r7, pc} 8017646: bf00 nop 8017648: 24002f24 .word 0x24002f24 801764c: 24002f28 .word 0x24002f28 8017650: e000ed04 .word 0xe000ed04 08017654 : /*-----------------------------------------------------------*/ static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) { 8017654: b480 push {r7} 8017656: b085 sub sp, #20 8017658: af00 add r7, sp, #0 801765a: 6078 str r0, [r7, #4] the timer with the nearest expiry time will expire. If there are no active timers then just set the next expire time to 0. That will cause this task to unblock when the tick count overflows, at which point the timer lists will be switched and the next expiry time can be re-assessed. */ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); 801765c: 4b0e ldr r3, [pc, #56] @ (8017698 ) 801765e: 681b ldr r3, [r3, #0] 8017660: 681b ldr r3, [r3, #0] 8017662: 2b00 cmp r3, #0 8017664: d101 bne.n 801766a 8017666: 2201 movs r2, #1 8017668: e000 b.n 801766c 801766a: 2200 movs r2, #0 801766c: 687b ldr r3, [r7, #4] 801766e: 601a str r2, [r3, #0] if( *pxListWasEmpty == pdFALSE ) 8017670: 687b ldr r3, [r7, #4] 8017672: 681b ldr r3, [r3, #0] 8017674: 2b00 cmp r3, #0 8017676: d105 bne.n 8017684 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 8017678: 4b07 ldr r3, [pc, #28] @ (8017698 ) 801767a: 681b ldr r3, [r3, #0] 801767c: 68db ldr r3, [r3, #12] 801767e: 681b ldr r3, [r3, #0] 8017680: 60fb str r3, [r7, #12] 8017682: e001 b.n 8017688 } else { /* Ensure the task unblocks when the tick count rolls over. */ xNextExpireTime = ( TickType_t ) 0U; 8017684: 2300 movs r3, #0 8017686: 60fb str r3, [r7, #12] } return xNextExpireTime; 8017688: 68fb ldr r3, [r7, #12] } 801768a: 4618 mov r0, r3 801768c: 3714 adds r7, #20 801768e: 46bd mov sp, r7 8017690: f85d 7b04 ldr.w r7, [sp], #4 8017694: 4770 bx lr 8017696: bf00 nop 8017698: 24002f20 .word 0x24002f20 0801769c : /*-----------------------------------------------------------*/ static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) { 801769c: b580 push {r7, lr} 801769e: b084 sub sp, #16 80176a0: af00 add r7, sp, #0 80176a2: 6078 str r0, [r7, #4] TickType_t xTimeNow; PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ xTimeNow = xTaskGetTickCount(); 80176a4: f7fe fe52 bl 801634c 80176a8: 60f8 str r0, [r7, #12] if( xTimeNow < xLastTime ) 80176aa: 4b0b ldr r3, [pc, #44] @ (80176d8 ) 80176ac: 681b ldr r3, [r3, #0] 80176ae: 68fa ldr r2, [r7, #12] 80176b0: 429a cmp r2, r3 80176b2: d205 bcs.n 80176c0 { prvSwitchTimerLists(); 80176b4: f000 f93a bl 801792c *pxTimerListsWereSwitched = pdTRUE; 80176b8: 687b ldr r3, [r7, #4] 80176ba: 2201 movs r2, #1 80176bc: 601a str r2, [r3, #0] 80176be: e002 b.n 80176c6 } else { *pxTimerListsWereSwitched = pdFALSE; 80176c0: 687b ldr r3, [r7, #4] 80176c2: 2200 movs r2, #0 80176c4: 601a str r2, [r3, #0] } xLastTime = xTimeNow; 80176c6: 4a04 ldr r2, [pc, #16] @ (80176d8 ) 80176c8: 68fb ldr r3, [r7, #12] 80176ca: 6013 str r3, [r2, #0] return xTimeNow; 80176cc: 68fb ldr r3, [r7, #12] } 80176ce: 4618 mov r0, r3 80176d0: 3710 adds r7, #16 80176d2: 46bd mov sp, r7 80176d4: bd80 pop {r7, pc} 80176d6: bf00 nop 80176d8: 24002f30 .word 0x24002f30 080176dc : /*-----------------------------------------------------------*/ static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) { 80176dc: b580 push {r7, lr} 80176de: b086 sub sp, #24 80176e0: af00 add r7, sp, #0 80176e2: 60f8 str r0, [r7, #12] 80176e4: 60b9 str r1, [r7, #8] 80176e6: 607a str r2, [r7, #4] 80176e8: 603b str r3, [r7, #0] BaseType_t xProcessTimerNow = pdFALSE; 80176ea: 2300 movs r3, #0 80176ec: 617b str r3, [r7, #20] listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); 80176ee: 68fb ldr r3, [r7, #12] 80176f0: 68ba ldr r2, [r7, #8] 80176f2: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 80176f4: 68fb ldr r3, [r7, #12] 80176f6: 68fa ldr r2, [r7, #12] 80176f8: 611a str r2, [r3, #16] if( xNextExpiryTime <= xTimeNow ) 80176fa: 68ba ldr r2, [r7, #8] 80176fc: 687b ldr r3, [r7, #4] 80176fe: 429a cmp r2, r3 8017700: d812 bhi.n 8017728 { /* Has the expiry time elapsed between the command to start/reset a timer was issued, and the time the command was processed? */ if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8017702: 687a ldr r2, [r7, #4] 8017704: 683b ldr r3, [r7, #0] 8017706: 1ad2 subs r2, r2, r3 8017708: 68fb ldr r3, [r7, #12] 801770a: 699b ldr r3, [r3, #24] 801770c: 429a cmp r2, r3 801770e: d302 bcc.n 8017716 { /* The time between a command being issued and the command being processed actually exceeds the timers period. */ xProcessTimerNow = pdTRUE; 8017710: 2301 movs r3, #1 8017712: 617b str r3, [r7, #20] 8017714: e01b b.n 801774e } else { vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); 8017716: 4b10 ldr r3, [pc, #64] @ (8017758 ) 8017718: 681a ldr r2, [r3, #0] 801771a: 68fb ldr r3, [r7, #12] 801771c: 3304 adds r3, #4 801771e: 4619 mov r1, r3 8017720: 4610 mov r0, r2 8017722: f7fd f94a bl 80149ba 8017726: e012 b.n 801774e } } else { if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) 8017728: 687a ldr r2, [r7, #4] 801772a: 683b ldr r3, [r7, #0] 801772c: 429a cmp r2, r3 801772e: d206 bcs.n 801773e 8017730: 68ba ldr r2, [r7, #8] 8017732: 683b ldr r3, [r7, #0] 8017734: 429a cmp r2, r3 8017736: d302 bcc.n 801773e { /* If, since the command was issued, the tick count has overflowed but the expiry time has not, then the timer must have already passed its expiry time and should be processed immediately. */ xProcessTimerNow = pdTRUE; 8017738: 2301 movs r3, #1 801773a: 617b str r3, [r7, #20] 801773c: e007 b.n 801774e } else { vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 801773e: 4b07 ldr r3, [pc, #28] @ (801775c ) 8017740: 681a ldr r2, [r3, #0] 8017742: 68fb ldr r3, [r7, #12] 8017744: 3304 adds r3, #4 8017746: 4619 mov r1, r3 8017748: 4610 mov r0, r2 801774a: f7fd f936 bl 80149ba } } return xProcessTimerNow; 801774e: 697b ldr r3, [r7, #20] } 8017750: 4618 mov r0, r3 8017752: 3718 adds r7, #24 8017754: 46bd mov sp, r7 8017756: bd80 pop {r7, pc} 8017758: 24002f24 .word 0x24002f24 801775c: 24002f20 .word 0x24002f20 08017760 : /*-----------------------------------------------------------*/ static void prvProcessReceivedCommands( void ) { 8017760: b580 push {r7, lr} 8017762: b08e sub sp, #56 @ 0x38 8017764: af02 add r7, sp, #8 DaemonTaskMessage_t xMessage; Timer_t *pxTimer; BaseType_t xTimerListsWereSwitched, xResult; TickType_t xTimeNow; while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 8017766: e0ce b.n 8017906 { #if ( INCLUDE_xTimerPendFunctionCall == 1 ) { /* Negative commands are pended function calls rather than timer commands. */ if( xMessage.xMessageID < ( BaseType_t ) 0 ) 8017768: 687b ldr r3, [r7, #4] 801776a: 2b00 cmp r3, #0 801776c: da19 bge.n 80177a2 { const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); 801776e: 1d3b adds r3, r7, #4 8017770: 3304 adds r3, #4 8017772: 62fb str r3, [r7, #44] @ 0x2c /* The timer uses the xCallbackParameters member to request a callback be executed. Check the callback is not NULL. */ configASSERT( pxCallback ); 8017774: 6afb ldr r3, [r7, #44] @ 0x2c 8017776: 2b00 cmp r3, #0 8017778: d10b bne.n 8017792 __asm volatile 801777a: f04f 0350 mov.w r3, #80 @ 0x50 801777e: f383 8811 msr BASEPRI, r3 8017782: f3bf 8f6f isb sy 8017786: f3bf 8f4f dsb sy 801778a: 61fb str r3, [r7, #28] } 801778c: bf00 nop 801778e: bf00 nop 8017790: e7fd b.n 801778e /* Call the function. */ pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); 8017792: 6afb ldr r3, [r7, #44] @ 0x2c 8017794: 681b ldr r3, [r3, #0] 8017796: 6afa ldr r2, [r7, #44] @ 0x2c 8017798: 6850 ldr r0, [r2, #4] 801779a: 6afa ldr r2, [r7, #44] @ 0x2c 801779c: 6892 ldr r2, [r2, #8] 801779e: 4611 mov r1, r2 80177a0: 4798 blx r3 } #endif /* INCLUDE_xTimerPendFunctionCall */ /* Commands that are positive are timer commands rather than pended function calls. */ if( xMessage.xMessageID >= ( BaseType_t ) 0 ) 80177a2: 687b ldr r3, [r7, #4] 80177a4: 2b00 cmp r3, #0 80177a6: f2c0 80ae blt.w 8017906 { /* The messages uses the xTimerParameters member to work on a software timer. */ pxTimer = xMessage.u.xTimerParameters.pxTimer; 80177aa: 68fb ldr r3, [r7, #12] 80177ac: 62bb str r3, [r7, #40] @ 0x28 if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ 80177ae: 6abb ldr r3, [r7, #40] @ 0x28 80177b0: 695b ldr r3, [r3, #20] 80177b2: 2b00 cmp r3, #0 80177b4: d004 beq.n 80177c0 { /* The timer is in a list, remove it. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 80177b6: 6abb ldr r3, [r7, #40] @ 0x28 80177b8: 3304 adds r3, #4 80177ba: 4618 mov r0, r3 80177bc: f7fd f936 bl 8014a2c it must be present in the function call. prvSampleTimeNow() must be called after the message is received from xTimerQueue so there is no possibility of a higher priority task adding a message to the message queue with a time that is ahead of the timer daemon task (because it pre-empted the timer daemon task after the xTimeNow value was set). */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 80177c0: 463b mov r3, r7 80177c2: 4618 mov r0, r3 80177c4: f7ff ff6a bl 801769c 80177c8: 6278 str r0, [r7, #36] @ 0x24 switch( xMessage.xMessageID ) 80177ca: 687b ldr r3, [r7, #4] 80177cc: 2b09 cmp r3, #9 80177ce: f200 8097 bhi.w 8017900 80177d2: a201 add r2, pc, #4 @ (adr r2, 80177d8 ) 80177d4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80177d8: 08017801 .word 0x08017801 80177dc: 08017801 .word 0x08017801 80177e0: 08017801 .word 0x08017801 80177e4: 08017877 .word 0x08017877 80177e8: 0801788b .word 0x0801788b 80177ec: 080178d7 .word 0x080178d7 80177f0: 08017801 .word 0x08017801 80177f4: 08017801 .word 0x08017801 80177f8: 08017877 .word 0x08017877 80177fc: 0801788b .word 0x0801788b case tmrCOMMAND_START_FROM_ISR : case tmrCOMMAND_RESET : case tmrCOMMAND_RESET_FROM_ISR : case tmrCOMMAND_START_DONT_TRACE : /* Start or restart a timer. */ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8017800: 6abb ldr r3, [r7, #40] @ 0x28 8017802: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017806: f043 0301 orr.w r3, r3, #1 801780a: b2da uxtb r2, r3 801780c: 6abb ldr r3, [r7, #40] @ 0x28 801780e: f883 2028 strb.w r2, [r3, #40] @ 0x28 if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) 8017812: 68ba ldr r2, [r7, #8] 8017814: 6abb ldr r3, [r7, #40] @ 0x28 8017816: 699b ldr r3, [r3, #24] 8017818: 18d1 adds r1, r2, r3 801781a: 68bb ldr r3, [r7, #8] 801781c: 6a7a ldr r2, [r7, #36] @ 0x24 801781e: 6ab8 ldr r0, [r7, #40] @ 0x28 8017820: f7ff ff5c bl 80176dc 8017824: 4603 mov r3, r0 8017826: 2b00 cmp r3, #0 8017828: d06c beq.n 8017904 { /* The timer expired before it was added to the active timer list. Process it now. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 801782a: 6abb ldr r3, [r7, #40] @ 0x28 801782c: 6a1b ldr r3, [r3, #32] 801782e: 6ab8 ldr r0, [r7, #40] @ 0x28 8017830: 4798 blx r3 traceTIMER_EXPIRED( pxTimer ); if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 8017832: 6abb ldr r3, [r7, #40] @ 0x28 8017834: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017838: f003 0304 and.w r3, r3, #4 801783c: 2b00 cmp r3, #0 801783e: d061 beq.n 8017904 { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); 8017840: 68ba ldr r2, [r7, #8] 8017842: 6abb ldr r3, [r7, #40] @ 0x28 8017844: 699b ldr r3, [r3, #24] 8017846: 441a add r2, r3 8017848: 2300 movs r3, #0 801784a: 9300 str r3, [sp, #0] 801784c: 2300 movs r3, #0 801784e: 2100 movs r1, #0 8017850: 6ab8 ldr r0, [r7, #40] @ 0x28 8017852: f7ff fe01 bl 8017458 8017856: 6238 str r0, [r7, #32] configASSERT( xResult ); 8017858: 6a3b ldr r3, [r7, #32] 801785a: 2b00 cmp r3, #0 801785c: d152 bne.n 8017904 __asm volatile 801785e: f04f 0350 mov.w r3, #80 @ 0x50 8017862: f383 8811 msr BASEPRI, r3 8017866: f3bf 8f6f isb sy 801786a: f3bf 8f4f dsb sy 801786e: 61bb str r3, [r7, #24] } 8017870: bf00 nop 8017872: bf00 nop 8017874: e7fd b.n 8017872 break; case tmrCOMMAND_STOP : case tmrCOMMAND_STOP_FROM_ISR : /* The timer has already been removed from the active list. */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8017876: 6abb ldr r3, [r7, #40] @ 0x28 8017878: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 801787c: f023 0301 bic.w r3, r3, #1 8017880: b2da uxtb r2, r3 8017882: 6abb ldr r3, [r7, #40] @ 0x28 8017884: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8017888: e03d b.n 8017906 case tmrCOMMAND_CHANGE_PERIOD : case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR : pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 801788a: 6abb ldr r3, [r7, #40] @ 0x28 801788c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017890: f043 0301 orr.w r3, r3, #1 8017894: b2da uxtb r2, r3 8017896: 6abb ldr r3, [r7, #40] @ 0x28 8017898: f883 2028 strb.w r2, [r3, #40] @ 0x28 pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; 801789c: 68ba ldr r2, [r7, #8] 801789e: 6abb ldr r3, [r7, #40] @ 0x28 80178a0: 619a str r2, [r3, #24] configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); 80178a2: 6abb ldr r3, [r7, #40] @ 0x28 80178a4: 699b ldr r3, [r3, #24] 80178a6: 2b00 cmp r3, #0 80178a8: d10b bne.n 80178c2 __asm volatile 80178aa: f04f 0350 mov.w r3, #80 @ 0x50 80178ae: f383 8811 msr BASEPRI, r3 80178b2: f3bf 8f6f isb sy 80178b6: f3bf 8f4f dsb sy 80178ba: 617b str r3, [r7, #20] } 80178bc: bf00 nop 80178be: bf00 nop 80178c0: e7fd b.n 80178be be longer or shorter than the old one. The command time is therefore set to the current time, and as the period cannot be zero the next expiry time can only be in the future, meaning (unlike for the xTimerStart() case above) there is no fail case that needs to be handled here. */ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); 80178c2: 6abb ldr r3, [r7, #40] @ 0x28 80178c4: 699a ldr r2, [r3, #24] 80178c6: 6a7b ldr r3, [r7, #36] @ 0x24 80178c8: 18d1 adds r1, r2, r3 80178ca: 6a7b ldr r3, [r7, #36] @ 0x24 80178cc: 6a7a ldr r2, [r7, #36] @ 0x24 80178ce: 6ab8 ldr r0, [r7, #40] @ 0x28 80178d0: f7ff ff04 bl 80176dc break; 80178d4: e017 b.n 8017906 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* The timer has already been removed from the active list, just free up the memory if the memory was dynamically allocated. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) 80178d6: 6abb ldr r3, [r7, #40] @ 0x28 80178d8: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80178dc: f003 0302 and.w r3, r3, #2 80178e0: 2b00 cmp r3, #0 80178e2: d103 bne.n 80178ec { vPortFree( pxTimer ); 80178e4: 6ab8 ldr r0, [r7, #40] @ 0x28 80178e6: f000 fc37 bl 8018158 no need to free the memory - just mark the timer as "not active". */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ break; 80178ea: e00c b.n 8017906 pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 80178ec: 6abb ldr r3, [r7, #40] @ 0x28 80178ee: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80178f2: f023 0301 bic.w r3, r3, #1 80178f6: b2da uxtb r2, r3 80178f8: 6abb ldr r3, [r7, #40] @ 0x28 80178fa: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 80178fe: e002 b.n 8017906 default : /* Don't expect to get here. */ break; 8017900: bf00 nop 8017902: e000 b.n 8017906 break; 8017904: bf00 nop while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 8017906: 4b08 ldr r3, [pc, #32] @ (8017928 ) 8017908: 681b ldr r3, [r3, #0] 801790a: 1d39 adds r1, r7, #4 801790c: 2200 movs r2, #0 801790e: 4618 mov r0, r3 8017910: f7fd fc54 bl 80151bc 8017914: 4603 mov r3, r0 8017916: 2b00 cmp r3, #0 8017918: f47f af26 bne.w 8017768 } } } } 801791c: bf00 nop 801791e: bf00 nop 8017920: 3730 adds r7, #48 @ 0x30 8017922: 46bd mov sp, r7 8017924: bd80 pop {r7, pc} 8017926: bf00 nop 8017928: 24002f28 .word 0x24002f28 0801792c : /*-----------------------------------------------------------*/ static void prvSwitchTimerLists( void ) { 801792c: b580 push {r7, lr} 801792e: b088 sub sp, #32 8017930: af02 add r7, sp, #8 /* The tick count has overflowed. The timer lists must be switched. If there are any timers still referenced from the current timer list then they must have expired and should be processed before the lists are switched. */ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 8017932: e049 b.n 80179c8 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 8017934: 4b2e ldr r3, [pc, #184] @ (80179f0 ) 8017936: 681b ldr r3, [r3, #0] 8017938: 68db ldr r3, [r3, #12] 801793a: 681b ldr r3, [r3, #0] 801793c: 613b str r3, [r7, #16] /* Remove the timer from the list. */ pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 801793e: 4b2c ldr r3, [pc, #176] @ (80179f0 ) 8017940: 681b ldr r3, [r3, #0] 8017942: 68db ldr r3, [r3, #12] 8017944: 68db ldr r3, [r3, #12] 8017946: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8017948: 68fb ldr r3, [r7, #12] 801794a: 3304 adds r3, #4 801794c: 4618 mov r0, r3 801794e: f7fd f86d bl 8014a2c traceTIMER_EXPIRED( pxTimer ); /* Execute its callback, then send a command to restart the timer if it is an auto-reload timer. It cannot be restarted here as the lists have not yet been switched. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8017952: 68fb ldr r3, [r7, #12] 8017954: 6a1b ldr r3, [r3, #32] 8017956: 68f8 ldr r0, [r7, #12] 8017958: 4798 blx r3 if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 801795a: 68fb ldr r3, [r7, #12] 801795c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017960: f003 0304 and.w r3, r3, #4 8017964: 2b00 cmp r3, #0 8017966: d02f beq.n 80179c8 the timer going into the same timer list then it has already expired and the timer should be re-inserted into the current list so it is processed again within this loop. Otherwise a command should be sent to restart the timer to ensure it is only inserted into a list after the lists have been swapped. */ xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); 8017968: 68fb ldr r3, [r7, #12] 801796a: 699b ldr r3, [r3, #24] 801796c: 693a ldr r2, [r7, #16] 801796e: 4413 add r3, r2 8017970: 60bb str r3, [r7, #8] if( xReloadTime > xNextExpireTime ) 8017972: 68ba ldr r2, [r7, #8] 8017974: 693b ldr r3, [r7, #16] 8017976: 429a cmp r2, r3 8017978: d90e bls.n 8017998 { listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); 801797a: 68fb ldr r3, [r7, #12] 801797c: 68ba ldr r2, [r7, #8] 801797e: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 8017980: 68fb ldr r3, [r7, #12] 8017982: 68fa ldr r2, [r7, #12] 8017984: 611a str r2, [r3, #16] vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 8017986: 4b1a ldr r3, [pc, #104] @ (80179f0 ) 8017988: 681a ldr r2, [r3, #0] 801798a: 68fb ldr r3, [r7, #12] 801798c: 3304 adds r3, #4 801798e: 4619 mov r1, r3 8017990: 4610 mov r0, r2 8017992: f7fd f812 bl 80149ba 8017996: e017 b.n 80179c8 } else { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 8017998: 2300 movs r3, #0 801799a: 9300 str r3, [sp, #0] 801799c: 2300 movs r3, #0 801799e: 693a ldr r2, [r7, #16] 80179a0: 2100 movs r1, #0 80179a2: 68f8 ldr r0, [r7, #12] 80179a4: f7ff fd58 bl 8017458 80179a8: 6078 str r0, [r7, #4] configASSERT( xResult ); 80179aa: 687b ldr r3, [r7, #4] 80179ac: 2b00 cmp r3, #0 80179ae: d10b bne.n 80179c8 __asm volatile 80179b0: f04f 0350 mov.w r3, #80 @ 0x50 80179b4: f383 8811 msr BASEPRI, r3 80179b8: f3bf 8f6f isb sy 80179bc: f3bf 8f4f dsb sy 80179c0: 603b str r3, [r7, #0] } 80179c2: bf00 nop 80179c4: bf00 nop 80179c6: e7fd b.n 80179c4 while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 80179c8: 4b09 ldr r3, [pc, #36] @ (80179f0 ) 80179ca: 681b ldr r3, [r3, #0] 80179cc: 681b ldr r3, [r3, #0] 80179ce: 2b00 cmp r3, #0 80179d0: d1b0 bne.n 8017934 { mtCOVERAGE_TEST_MARKER(); } } pxTemp = pxCurrentTimerList; 80179d2: 4b07 ldr r3, [pc, #28] @ (80179f0 ) 80179d4: 681b ldr r3, [r3, #0] 80179d6: 617b str r3, [r7, #20] pxCurrentTimerList = pxOverflowTimerList; 80179d8: 4b06 ldr r3, [pc, #24] @ (80179f4 ) 80179da: 681b ldr r3, [r3, #0] 80179dc: 4a04 ldr r2, [pc, #16] @ (80179f0 ) 80179de: 6013 str r3, [r2, #0] pxOverflowTimerList = pxTemp; 80179e0: 4a04 ldr r2, [pc, #16] @ (80179f4 ) 80179e2: 697b ldr r3, [r7, #20] 80179e4: 6013 str r3, [r2, #0] } 80179e6: bf00 nop 80179e8: 3718 adds r7, #24 80179ea: 46bd mov sp, r7 80179ec: bd80 pop {r7, pc} 80179ee: bf00 nop 80179f0: 24002f20 .word 0x24002f20 80179f4: 24002f24 .word 0x24002f24 080179f8 : /*-----------------------------------------------------------*/ static void prvCheckForValidListAndQueue( void ) { 80179f8: b580 push {r7, lr} 80179fa: b082 sub sp, #8 80179fc: af02 add r7, sp, #8 /* Check that the list from which active timers are referenced, and the queue used to communicate with the timer service, have been initialised. */ taskENTER_CRITICAL(); 80179fe: f000 f9bb bl 8017d78 { if( xTimerQueue == NULL ) 8017a02: 4b15 ldr r3, [pc, #84] @ (8017a58 ) 8017a04: 681b ldr r3, [r3, #0] 8017a06: 2b00 cmp r3, #0 8017a08: d120 bne.n 8017a4c { vListInitialise( &xActiveTimerList1 ); 8017a0a: 4814 ldr r0, [pc, #80] @ (8017a5c ) 8017a0c: f7fc ff84 bl 8014918 vListInitialise( &xActiveTimerList2 ); 8017a10: 4813 ldr r0, [pc, #76] @ (8017a60 ) 8017a12: f7fc ff81 bl 8014918 pxCurrentTimerList = &xActiveTimerList1; 8017a16: 4b13 ldr r3, [pc, #76] @ (8017a64 ) 8017a18: 4a10 ldr r2, [pc, #64] @ (8017a5c ) 8017a1a: 601a str r2, [r3, #0] pxOverflowTimerList = &xActiveTimerList2; 8017a1c: 4b12 ldr r3, [pc, #72] @ (8017a68 ) 8017a1e: 4a10 ldr r2, [pc, #64] @ (8017a60 ) 8017a20: 601a str r2, [r3, #0] /* The timer queue is allocated statically in case configSUPPORT_DYNAMIC_ALLOCATION is 0. */ static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 8017a22: 2300 movs r3, #0 8017a24: 9300 str r3, [sp, #0] 8017a26: 4b11 ldr r3, [pc, #68] @ (8017a6c ) 8017a28: 4a11 ldr r2, [pc, #68] @ (8017a70 ) 8017a2a: 2110 movs r1, #16 8017a2c: 200a movs r0, #10 8017a2e: f7fd f891 bl 8014b54 8017a32: 4603 mov r3, r0 8017a34: 4a08 ldr r2, [pc, #32] @ (8017a58 ) 8017a36: 6013 str r3, [r2, #0] } #endif #if ( configQUEUE_REGISTRY_SIZE > 0 ) { if( xTimerQueue != NULL ) 8017a38: 4b07 ldr r3, [pc, #28] @ (8017a58 ) 8017a3a: 681b ldr r3, [r3, #0] 8017a3c: 2b00 cmp r3, #0 8017a3e: d005 beq.n 8017a4c { vQueueAddToRegistry( xTimerQueue, "TmrQ" ); 8017a40: 4b05 ldr r3, [pc, #20] @ (8017a58 ) 8017a42: 681b ldr r3, [r3, #0] 8017a44: 490b ldr r1, [pc, #44] @ (8017a74 ) 8017a46: 4618 mov r0, r3 8017a48: f7fd ff54 bl 80158f4 else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8017a4c: f000 f9c6 bl 8017ddc } 8017a50: bf00 nop 8017a52: 46bd mov sp, r7 8017a54: bd80 pop {r7, pc} 8017a56: bf00 nop 8017a58: 24002f28 .word 0x24002f28 8017a5c: 24002ef8 .word 0x24002ef8 8017a60: 24002f0c .word 0x24002f0c 8017a64: 24002f20 .word 0x24002f20 8017a68: 24002f24 .word 0x24002f24 8017a6c: 24002fd4 .word 0x24002fd4 8017a70: 24002f34 .word 0x24002f34 8017a74: 08018720 .word 0x08018720 08017a78 : /*-----------------------------------------------------------*/ BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) { 8017a78: b580 push {r7, lr} 8017a7a: b086 sub sp, #24 8017a7c: af00 add r7, sp, #0 8017a7e: 6078 str r0, [r7, #4] BaseType_t xReturn; Timer_t *pxTimer = xTimer; 8017a80: 687b ldr r3, [r7, #4] 8017a82: 613b str r3, [r7, #16] configASSERT( xTimer ); 8017a84: 687b ldr r3, [r7, #4] 8017a86: 2b00 cmp r3, #0 8017a88: d10b bne.n 8017aa2 __asm volatile 8017a8a: f04f 0350 mov.w r3, #80 @ 0x50 8017a8e: f383 8811 msr BASEPRI, r3 8017a92: f3bf 8f6f isb sy 8017a96: f3bf 8f4f dsb sy 8017a9a: 60fb str r3, [r7, #12] } 8017a9c: bf00 nop 8017a9e: bf00 nop 8017aa0: e7fd b.n 8017a9e /* Is the timer in the list of active timers? */ taskENTER_CRITICAL(); 8017aa2: f000 f969 bl 8017d78 { if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 ) 8017aa6: 693b ldr r3, [r7, #16] 8017aa8: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017aac: f003 0301 and.w r3, r3, #1 8017ab0: 2b00 cmp r3, #0 8017ab2: d102 bne.n 8017aba { xReturn = pdFALSE; 8017ab4: 2300 movs r3, #0 8017ab6: 617b str r3, [r7, #20] 8017ab8: e001 b.n 8017abe } else { xReturn = pdTRUE; 8017aba: 2301 movs r3, #1 8017abc: 617b str r3, [r7, #20] } } taskEXIT_CRITICAL(); 8017abe: f000 f98d bl 8017ddc return xReturn; 8017ac2: 697b ldr r3, [r7, #20] } /*lint !e818 Can't be pointer to const due to the typedef. */ 8017ac4: 4618 mov r0, r3 8017ac6: 3718 adds r7, #24 8017ac8: 46bd mov sp, r7 8017aca: bd80 pop {r7, pc} 08017acc : /*-----------------------------------------------------------*/ void *pvTimerGetTimerID( const TimerHandle_t xTimer ) { 8017acc: b580 push {r7, lr} 8017ace: b086 sub sp, #24 8017ad0: af00 add r7, sp, #0 8017ad2: 6078 str r0, [r7, #4] Timer_t * const pxTimer = xTimer; 8017ad4: 687b ldr r3, [r7, #4] 8017ad6: 617b str r3, [r7, #20] void *pvReturn; configASSERT( xTimer ); 8017ad8: 687b ldr r3, [r7, #4] 8017ada: 2b00 cmp r3, #0 8017adc: d10b bne.n 8017af6 __asm volatile 8017ade: f04f 0350 mov.w r3, #80 @ 0x50 8017ae2: f383 8811 msr BASEPRI, r3 8017ae6: f3bf 8f6f isb sy 8017aea: f3bf 8f4f dsb sy 8017aee: 60fb str r3, [r7, #12] } 8017af0: bf00 nop 8017af2: bf00 nop 8017af4: e7fd b.n 8017af2 taskENTER_CRITICAL(); 8017af6: f000 f93f bl 8017d78 { pvReturn = pxTimer->pvTimerID; 8017afa: 697b ldr r3, [r7, #20] 8017afc: 69db ldr r3, [r3, #28] 8017afe: 613b str r3, [r7, #16] } taskEXIT_CRITICAL(); 8017b00: f000 f96c bl 8017ddc return pvReturn; 8017b04: 693b ldr r3, [r7, #16] } 8017b06: 4618 mov r0, r3 8017b08: 3718 adds r7, #24 8017b0a: 46bd mov sp, r7 8017b0c: bd80 pop {r7, pc} ... 08017b10 : /* * See header file for description. */ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) { 8017b10: b480 push {r7} 8017b12: b085 sub sp, #20 8017b14: af00 add r7, sp, #0 8017b16: 60f8 str r0, [r7, #12] 8017b18: 60b9 str r1, [r7, #8] 8017b1a: 607a str r2, [r7, #4] /* Simulate the stack frame as it would be created by a context switch interrupt. */ /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts, and to ensure alignment. */ pxTopOfStack--; 8017b1c: 68fb ldr r3, [r7, #12] 8017b1e: 3b04 subs r3, #4 8017b20: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ 8017b22: 68fb ldr r3, [r7, #12] 8017b24: f04f 7280 mov.w r2, #16777216 @ 0x1000000 8017b28: 601a str r2, [r3, #0] pxTopOfStack--; 8017b2a: 68fb ldr r3, [r7, #12] 8017b2c: 3b04 subs r3, #4 8017b2e: 60fb str r3, [r7, #12] *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ 8017b30: 68bb ldr r3, [r7, #8] 8017b32: f023 0201 bic.w r2, r3, #1 8017b36: 68fb ldr r3, [r7, #12] 8017b38: 601a str r2, [r3, #0] pxTopOfStack--; 8017b3a: 68fb ldr r3, [r7, #12] 8017b3c: 3b04 subs r3, #4 8017b3e: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ 8017b40: 4a0c ldr r2, [pc, #48] @ (8017b74 ) 8017b42: 68fb ldr r3, [r7, #12] 8017b44: 601a str r2, [r3, #0] /* Save code space by skipping register initialisation. */ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ 8017b46: 68fb ldr r3, [r7, #12] 8017b48: 3b14 subs r3, #20 8017b4a: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ 8017b4c: 687a ldr r2, [r7, #4] 8017b4e: 68fb ldr r3, [r7, #12] 8017b50: 601a str r2, [r3, #0] /* A save method is being used that requires each task to maintain its own exec return value. */ pxTopOfStack--; 8017b52: 68fb ldr r3, [r7, #12] 8017b54: 3b04 subs r3, #4 8017b56: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_EXC_RETURN; 8017b58: 68fb ldr r3, [r7, #12] 8017b5a: f06f 0202 mvn.w r2, #2 8017b5e: 601a str r2, [r3, #0] pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ 8017b60: 68fb ldr r3, [r7, #12] 8017b62: 3b20 subs r3, #32 8017b64: 60fb str r3, [r7, #12] return pxTopOfStack; 8017b66: 68fb ldr r3, [r7, #12] } 8017b68: 4618 mov r0, r3 8017b6a: 3714 adds r7, #20 8017b6c: 46bd mov sp, r7 8017b6e: f85d 7b04 ldr.w r7, [sp], #4 8017b72: 4770 bx lr 8017b74: 08017b79 .word 0x08017b79 08017b78 : /*-----------------------------------------------------------*/ static void prvTaskExitError( void ) { 8017b78: b480 push {r7} 8017b7a: b085 sub sp, #20 8017b7c: af00 add r7, sp, #0 volatile uint32_t ulDummy = 0; 8017b7e: 2300 movs r3, #0 8017b80: 607b str r3, [r7, #4] its caller as there is nothing to return to. If a task wants to exit it should instead call vTaskDelete( NULL ). Artificially force an assert() to be triggered if configASSERT() is defined, then stop here so application writers can catch the error. */ configASSERT( uxCriticalNesting == ~0UL ); 8017b82: 4b13 ldr r3, [pc, #76] @ (8017bd0 ) 8017b84: 681b ldr r3, [r3, #0] 8017b86: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8017b8a: d00b beq.n 8017ba4 __asm volatile 8017b8c: f04f 0350 mov.w r3, #80 @ 0x50 8017b90: f383 8811 msr BASEPRI, r3 8017b94: f3bf 8f6f isb sy 8017b98: f3bf 8f4f dsb sy 8017b9c: 60fb str r3, [r7, #12] } 8017b9e: bf00 nop 8017ba0: bf00 nop 8017ba2: e7fd b.n 8017ba0 __asm volatile 8017ba4: f04f 0350 mov.w r3, #80 @ 0x50 8017ba8: f383 8811 msr BASEPRI, r3 8017bac: f3bf 8f6f isb sy 8017bb0: f3bf 8f4f dsb sy 8017bb4: 60bb str r3, [r7, #8] } 8017bb6: bf00 nop portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) 8017bb8: bf00 nop 8017bba: 687b ldr r3, [r7, #4] 8017bbc: 2b00 cmp r3, #0 8017bbe: d0fc beq.n 8017bba about code appearing after this function is called - making ulDummy volatile makes the compiler think the function could return and therefore not output an 'unreachable code' warning for code that appears after it. */ } } 8017bc0: bf00 nop 8017bc2: bf00 nop 8017bc4: 3714 adds r7, #20 8017bc6: 46bd mov sp, r7 8017bc8: f85d 7b04 ldr.w r7, [sp], #4 8017bcc: 4770 bx lr 8017bce: bf00 nop 8017bd0: 24000044 .word 0x24000044 ... 08017be0 : /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( 8017be0: 4b07 ldr r3, [pc, #28] @ (8017c00 ) 8017be2: 6819 ldr r1, [r3, #0] 8017be4: 6808 ldr r0, [r1, #0] 8017be6: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017bea: f380 8809 msr PSP, r0 8017bee: f3bf 8f6f isb sy 8017bf2: f04f 0000 mov.w r0, #0 8017bf6: f380 8811 msr BASEPRI, r0 8017bfa: 4770 bx lr 8017bfc: f3af 8000 nop.w 08017c00 : 8017c00: 240029f8 .word 0x240029f8 " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } 8017c04: bf00 nop 8017c06: bf00 nop 08017c08 : { /* Start the first task. This also clears the bit that indicates the FPU is in use in case the FPU was used before the scheduler was started - which would otherwise result in the unnecessary leaving of space in the SVC stack for lazy saving of FPU registers. */ __asm volatile( 8017c08: 4808 ldr r0, [pc, #32] @ (8017c2c ) 8017c0a: 6800 ldr r0, [r0, #0] 8017c0c: 6800 ldr r0, [r0, #0] 8017c0e: f380 8808 msr MSP, r0 8017c12: f04f 0000 mov.w r0, #0 8017c16: f380 8814 msr CONTROL, r0 8017c1a: b662 cpsie i 8017c1c: b661 cpsie f 8017c1e: f3bf 8f4f dsb sy 8017c22: f3bf 8f6f isb sy 8017c26: df00 svc 0 8017c28: bf00 nop " dsb \n" " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n" ); } 8017c2a: bf00 nop 8017c2c: e000ed08 .word 0xe000ed08 08017c30 : /* * See header file for description. */ BaseType_t xPortStartScheduler( void ) { 8017c30: b580 push {r7, lr} 8017c32: b086 sub sp, #24 8017c34: af00 add r7, sp, #0 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); /* This port can be used on all revisions of the Cortex-M7 core other than the r0p1 parts. r0p1 parts should use the port from the /source/portable/GCC/ARM_CM7/r0p1 directory. */ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); 8017c36: 4b47 ldr r3, [pc, #284] @ (8017d54 ) 8017c38: 681b ldr r3, [r3, #0] 8017c3a: 4a47 ldr r2, [pc, #284] @ (8017d58 ) 8017c3c: 4293 cmp r3, r2 8017c3e: d10b bne.n 8017c58 __asm volatile 8017c40: f04f 0350 mov.w r3, #80 @ 0x50 8017c44: f383 8811 msr BASEPRI, r3 8017c48: f3bf 8f6f isb sy 8017c4c: f3bf 8f4f dsb sy 8017c50: 613b str r3, [r7, #16] } 8017c52: bf00 nop 8017c54: bf00 nop 8017c56: e7fd b.n 8017c54 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); 8017c58: 4b3e ldr r3, [pc, #248] @ (8017d54 ) 8017c5a: 681b ldr r3, [r3, #0] 8017c5c: 4a3f ldr r2, [pc, #252] @ (8017d5c ) 8017c5e: 4293 cmp r3, r2 8017c60: d10b bne.n 8017c7a __asm volatile 8017c62: f04f 0350 mov.w r3, #80 @ 0x50 8017c66: f383 8811 msr BASEPRI, r3 8017c6a: f3bf 8f6f isb sy 8017c6e: f3bf 8f4f dsb sy 8017c72: 60fb str r3, [r7, #12] } 8017c74: bf00 nop 8017c76: bf00 nop 8017c78: e7fd b.n 8017c76 #if( configASSERT_DEFINED == 1 ) { volatile uint32_t ulOriginalPriority; volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); 8017c7a: 4b39 ldr r3, [pc, #228] @ (8017d60 ) 8017c7c: 617b str r3, [r7, #20] functions can be called. ISR safe functions are those that end in "FromISR". FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. Save the interrupt priority value that is about to be clobbered. */ ulOriginalPriority = *pucFirstUserPriorityRegister; 8017c7e: 697b ldr r3, [r7, #20] 8017c80: 781b ldrb r3, [r3, #0] 8017c82: b2db uxtb r3, r3 8017c84: 607b str r3, [r7, #4] /* Determine the number of priority bits available. First write to all possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; 8017c86: 697b ldr r3, [r7, #20] 8017c88: 22ff movs r2, #255 @ 0xff 8017c8a: 701a strb r2, [r3, #0] /* Read the value back to see how many bits stuck. */ ucMaxPriorityValue = *pucFirstUserPriorityRegister; 8017c8c: 697b ldr r3, [r7, #20] 8017c8e: 781b ldrb r3, [r3, #0] 8017c90: b2db uxtb r3, r3 8017c92: 70fb strb r3, [r7, #3] /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; 8017c94: 78fb ldrb r3, [r7, #3] 8017c96: b2db uxtb r3, r3 8017c98: f003 0350 and.w r3, r3, #80 @ 0x50 8017c9c: b2da uxtb r2, r3 8017c9e: 4b31 ldr r3, [pc, #196] @ (8017d64 ) 8017ca0: 701a strb r2, [r3, #0] /* Calculate the maximum acceptable priority group value for the number of bits read back. */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; 8017ca2: 4b31 ldr r3, [pc, #196] @ (8017d68 ) 8017ca4: 2207 movs r2, #7 8017ca6: 601a str r2, [r3, #0] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 8017ca8: e009 b.n 8017cbe { ulMaxPRIGROUPValue--; 8017caa: 4b2f ldr r3, [pc, #188] @ (8017d68 ) 8017cac: 681b ldr r3, [r3, #0] 8017cae: 3b01 subs r3, #1 8017cb0: 4a2d ldr r2, [pc, #180] @ (8017d68 ) 8017cb2: 6013 str r3, [r2, #0] ucMaxPriorityValue <<= ( uint8_t ) 0x01; 8017cb4: 78fb ldrb r3, [r7, #3] 8017cb6: b2db uxtb r3, r3 8017cb8: 005b lsls r3, r3, #1 8017cba: b2db uxtb r3, r3 8017cbc: 70fb strb r3, [r7, #3] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 8017cbe: 78fb ldrb r3, [r7, #3] 8017cc0: b2db uxtb r3, r3 8017cc2: f003 0380 and.w r3, r3, #128 @ 0x80 8017cc6: 2b80 cmp r3, #128 @ 0x80 8017cc8: d0ef beq.n 8017caa #ifdef configPRIO_BITS { /* Check the FreeRTOS configuration that defines the number of priority bits matches the number of priority bits actually queried from the hardware. */ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); 8017cca: 4b27 ldr r3, [pc, #156] @ (8017d68 ) 8017ccc: 681b ldr r3, [r3, #0] 8017cce: f1c3 0307 rsb r3, r3, #7 8017cd2: 2b04 cmp r3, #4 8017cd4: d00b beq.n 8017cee __asm volatile 8017cd6: f04f 0350 mov.w r3, #80 @ 0x50 8017cda: f383 8811 msr BASEPRI, r3 8017cde: f3bf 8f6f isb sy 8017ce2: f3bf 8f4f dsb sy 8017ce6: 60bb str r3, [r7, #8] } 8017ce8: bf00 nop 8017cea: bf00 nop 8017cec: e7fd b.n 8017cea } #endif /* Shift the priority group value back to its position within the AIRCR register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; 8017cee: 4b1e ldr r3, [pc, #120] @ (8017d68 ) 8017cf0: 681b ldr r3, [r3, #0] 8017cf2: 021b lsls r3, r3, #8 8017cf4: 4a1c ldr r2, [pc, #112] @ (8017d68 ) 8017cf6: 6013 str r3, [r2, #0] ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; 8017cf8: 4b1b ldr r3, [pc, #108] @ (8017d68 ) 8017cfa: 681b ldr r3, [r3, #0] 8017cfc: f403 63e0 and.w r3, r3, #1792 @ 0x700 8017d00: 4a19 ldr r2, [pc, #100] @ (8017d68 ) 8017d02: 6013 str r3, [r2, #0] /* Restore the clobbered interrupt priority register to its original value. */ *pucFirstUserPriorityRegister = ulOriginalPriority; 8017d04: 687b ldr r3, [r7, #4] 8017d06: b2da uxtb r2, r3 8017d08: 697b ldr r3, [r7, #20] 8017d0a: 701a strb r2, [r3, #0] } #endif /* conifgASSERT_DEFINED */ /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; 8017d0c: 4b17 ldr r3, [pc, #92] @ (8017d6c ) 8017d0e: 681b ldr r3, [r3, #0] 8017d10: 4a16 ldr r2, [pc, #88] @ (8017d6c ) 8017d12: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8017d16: 6013 str r3, [r2, #0] portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; 8017d18: 4b14 ldr r3, [pc, #80] @ (8017d6c ) 8017d1a: 681b ldr r3, [r3, #0] 8017d1c: 4a13 ldr r2, [pc, #76] @ (8017d6c ) 8017d1e: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000 8017d22: 6013 str r3, [r2, #0] /* Start the timer that generates the tick ISR. Interrupts are disabled here already. */ vPortSetupTimerInterrupt(); 8017d24: f000 f8da bl 8017edc /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; 8017d28: 4b11 ldr r3, [pc, #68] @ (8017d70 ) 8017d2a: 2200 movs r2, #0 8017d2c: 601a str r2, [r3, #0] /* Ensure the VFP is enabled - it should be anyway. */ vPortEnableVFP(); 8017d2e: f000 f8f9 bl 8017f24 /* Lazy save always. */ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; 8017d32: 4b10 ldr r3, [pc, #64] @ (8017d74 ) 8017d34: 681b ldr r3, [r3, #0] 8017d36: 4a0f ldr r2, [pc, #60] @ (8017d74 ) 8017d38: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000 8017d3c: 6013 str r3, [r2, #0] /* Start the first task. */ prvPortStartFirstTask(); 8017d3e: f7ff ff63 bl 8017c08 exit error function to prevent compiler warnings about a static function not being called in the case that the application writer overrides this functionality by defining configTASK_RETURN_ADDRESS. Call vTaskSwitchContext() so link time optimisation does not remove the symbol. */ vTaskSwitchContext(); 8017d42: f7fe fbcd bl 80164e0 prvTaskExitError(); 8017d46: f7ff ff17 bl 8017b78 /* Should not get here! */ return 0; 8017d4a: 2300 movs r3, #0 } 8017d4c: 4618 mov r0, r3 8017d4e: 3718 adds r7, #24 8017d50: 46bd mov sp, r7 8017d52: bd80 pop {r7, pc} 8017d54: e000ed00 .word 0xe000ed00 8017d58: 410fc271 .word 0x410fc271 8017d5c: 410fc270 .word 0x410fc270 8017d60: e000e400 .word 0xe000e400 8017d64: 24003024 .word 0x24003024 8017d68: 24003028 .word 0x24003028 8017d6c: e000ed20 .word 0xe000ed20 8017d70: 24000044 .word 0x24000044 8017d74: e000ef34 .word 0xe000ef34 08017d78 : configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) { 8017d78: b480 push {r7} 8017d7a: b083 sub sp, #12 8017d7c: af00 add r7, sp, #0 __asm volatile 8017d7e: f04f 0350 mov.w r3, #80 @ 0x50 8017d82: f383 8811 msr BASEPRI, r3 8017d86: f3bf 8f6f isb sy 8017d8a: f3bf 8f4f dsb sy 8017d8e: 607b str r3, [r7, #4] } 8017d90: bf00 nop portDISABLE_INTERRUPTS(); uxCriticalNesting++; 8017d92: 4b10 ldr r3, [pc, #64] @ (8017dd4 ) 8017d94: 681b ldr r3, [r3, #0] 8017d96: 3301 adds r3, #1 8017d98: 4a0e ldr r2, [pc, #56] @ (8017dd4 ) 8017d9a: 6013 str r3, [r2, #0] /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if( uxCriticalNesting == 1 ) 8017d9c: 4b0d ldr r3, [pc, #52] @ (8017dd4 ) 8017d9e: 681b ldr r3, [r3, #0] 8017da0: 2b01 cmp r3, #1 8017da2: d110 bne.n 8017dc6 { configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); 8017da4: 4b0c ldr r3, [pc, #48] @ (8017dd8 ) 8017da6: 681b ldr r3, [r3, #0] 8017da8: b2db uxtb r3, r3 8017daa: 2b00 cmp r3, #0 8017dac: d00b beq.n 8017dc6 __asm volatile 8017dae: f04f 0350 mov.w r3, #80 @ 0x50 8017db2: f383 8811 msr BASEPRI, r3 8017db6: f3bf 8f6f isb sy 8017dba: f3bf 8f4f dsb sy 8017dbe: 603b str r3, [r7, #0] } 8017dc0: bf00 nop 8017dc2: bf00 nop 8017dc4: e7fd b.n 8017dc2 } } 8017dc6: bf00 nop 8017dc8: 370c adds r7, #12 8017dca: 46bd mov sp, r7 8017dcc: f85d 7b04 ldr.w r7, [sp], #4 8017dd0: 4770 bx lr 8017dd2: bf00 nop 8017dd4: 24000044 .word 0x24000044 8017dd8: e000ed04 .word 0xe000ed04 08017ddc : /*-----------------------------------------------------------*/ void vPortExitCritical( void ) { 8017ddc: b480 push {r7} 8017dde: b083 sub sp, #12 8017de0: af00 add r7, sp, #0 configASSERT( uxCriticalNesting ); 8017de2: 4b12 ldr r3, [pc, #72] @ (8017e2c ) 8017de4: 681b ldr r3, [r3, #0] 8017de6: 2b00 cmp r3, #0 8017de8: d10b bne.n 8017e02 __asm volatile 8017dea: f04f 0350 mov.w r3, #80 @ 0x50 8017dee: f383 8811 msr BASEPRI, r3 8017df2: f3bf 8f6f isb sy 8017df6: f3bf 8f4f dsb sy 8017dfa: 607b str r3, [r7, #4] } 8017dfc: bf00 nop 8017dfe: bf00 nop 8017e00: e7fd b.n 8017dfe uxCriticalNesting--; 8017e02: 4b0a ldr r3, [pc, #40] @ (8017e2c ) 8017e04: 681b ldr r3, [r3, #0] 8017e06: 3b01 subs r3, #1 8017e08: 4a08 ldr r2, [pc, #32] @ (8017e2c ) 8017e0a: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) 8017e0c: 4b07 ldr r3, [pc, #28] @ (8017e2c ) 8017e0e: 681b ldr r3, [r3, #0] 8017e10: 2b00 cmp r3, #0 8017e12: d105 bne.n 8017e20 8017e14: 2300 movs r3, #0 8017e16: 603b str r3, [r7, #0] __asm volatile 8017e18: 683b ldr r3, [r7, #0] 8017e1a: f383 8811 msr BASEPRI, r3 } 8017e1e: bf00 nop { portENABLE_INTERRUPTS(); } } 8017e20: bf00 nop 8017e22: 370c adds r7, #12 8017e24: 46bd mov sp, r7 8017e26: f85d 7b04 ldr.w r7, [sp], #4 8017e2a: 4770 bx lr 8017e2c: 24000044 .word 0x24000044 08017e30 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile 8017e30: f3ef 8009 mrs r0, PSP 8017e34: f3bf 8f6f isb sy 8017e38: 4b15 ldr r3, [pc, #84] @ (8017e90 ) 8017e3a: 681a ldr r2, [r3, #0] 8017e3c: f01e 0f10 tst.w lr, #16 8017e40: bf08 it eq 8017e42: ed20 8a10 vstmdbeq r0!, {s16-s31} 8017e46: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017e4a: 6010 str r0, [r2, #0] 8017e4c: e92d 0009 stmdb sp!, {r0, r3} 8017e50: f04f 0050 mov.w r0, #80 @ 0x50 8017e54: f380 8811 msr BASEPRI, r0 8017e58: f3bf 8f4f dsb sy 8017e5c: f3bf 8f6f isb sy 8017e60: f7fe fb3e bl 80164e0 8017e64: f04f 0000 mov.w r0, #0 8017e68: f380 8811 msr BASEPRI, r0 8017e6c: bc09 pop {r0, r3} 8017e6e: 6819 ldr r1, [r3, #0] 8017e70: 6808 ldr r0, [r1, #0] 8017e72: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017e76: f01e 0f10 tst.w lr, #16 8017e7a: bf08 it eq 8017e7c: ecb0 8a10 vldmiaeq r0!, {s16-s31} 8017e80: f380 8809 msr PSP, r0 8017e84: f3bf 8f6f isb sy 8017e88: 4770 bx lr 8017e8a: bf00 nop 8017e8c: f3af 8000 nop.w 08017e90 : 8017e90: 240029f8 .word 0x240029f8 " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ); } 8017e94: bf00 nop 8017e96: bf00 nop 08017e98 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { 8017e98: b580 push {r7, lr} 8017e9a: b082 sub sp, #8 8017e9c: af00 add r7, sp, #0 __asm volatile 8017e9e: f04f 0350 mov.w r3, #80 @ 0x50 8017ea2: f383 8811 msr BASEPRI, r3 8017ea6: f3bf 8f6f isb sy 8017eaa: f3bf 8f4f dsb sy 8017eae: 607b str r3, [r7, #4] } 8017eb0: bf00 nop save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) 8017eb2: f7fe fa5b bl 801636c 8017eb6: 4603 mov r3, r0 8017eb8: 2b00 cmp r3, #0 8017eba: d003 beq.n 8017ec4 { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; 8017ebc: 4b06 ldr r3, [pc, #24] @ (8017ed8 ) 8017ebe: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8017ec2: 601a str r2, [r3, #0] 8017ec4: 2300 movs r3, #0 8017ec6: 603b str r3, [r7, #0] __asm volatile 8017ec8: 683b ldr r3, [r7, #0] 8017eca: f383 8811 msr BASEPRI, r3 } 8017ece: bf00 nop } } portENABLE_INTERRUPTS(); } 8017ed0: bf00 nop 8017ed2: 3708 adds r7, #8 8017ed4: 46bd mov sp, r7 8017ed6: bd80 pop {r7, pc} 8017ed8: e000ed04 .word 0xe000ed04 08017edc : /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) { 8017edc: b480 push {r7} 8017ede: af00 add r7, sp, #0 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and clear the SysTick. */ portNVIC_SYSTICK_CTRL_REG = 0UL; 8017ee0: 4b0b ldr r3, [pc, #44] @ (8017f10 ) 8017ee2: 2200 movs r2, #0 8017ee4: 601a str r2, [r3, #0] portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; 8017ee6: 4b0b ldr r3, [pc, #44] @ (8017f14 ) 8017ee8: 2200 movs r2, #0 8017eea: 601a str r2, [r3, #0] /* Configure SysTick to interrupt at the requested rate. */ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; 8017eec: 4b0a ldr r3, [pc, #40] @ (8017f18 ) 8017eee: 681b ldr r3, [r3, #0] 8017ef0: 4a0a ldr r2, [pc, #40] @ (8017f1c ) 8017ef2: fba2 2303 umull r2, r3, r2, r3 8017ef6: 099b lsrs r3, r3, #6 8017ef8: 4a09 ldr r2, [pc, #36] @ (8017f20 ) 8017efa: 3b01 subs r3, #1 8017efc: 6013 str r3, [r2, #0] portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); 8017efe: 4b04 ldr r3, [pc, #16] @ (8017f10 ) 8017f00: 2207 movs r2, #7 8017f02: 601a str r2, [r3, #0] } 8017f04: bf00 nop 8017f06: 46bd mov sp, r7 8017f08: f85d 7b04 ldr.w r7, [sp], #4 8017f0c: 4770 bx lr 8017f0e: bf00 nop 8017f10: e000e010 .word 0xe000e010 8017f14: e000e018 .word 0xe000e018 8017f18: 24000034 .word 0x24000034 8017f1c: 10624dd3 .word 0x10624dd3 8017f20: e000e014 .word 0xe000e014 08017f24 : /*-----------------------------------------------------------*/ /* This is a naked function. */ static void vPortEnableVFP( void ) { __asm volatile 8017f24: f8df 000c ldr.w r0, [pc, #12] @ 8017f34 8017f28: 6801 ldr r1, [r0, #0] 8017f2a: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 8017f2e: 6001 str r1, [r0, #0] 8017f30: 4770 bx lr " \n" " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ " str r1, [r0] \n" " bx r14 " ); } 8017f32: bf00 nop 8017f34: e000ed88 .word 0xe000ed88 08017f38 : /*-----------------------------------------------------------*/ #if( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { 8017f38: b480 push {r7} 8017f3a: b085 sub sp, #20 8017f3c: af00 add r7, sp, #0 uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); 8017f3e: f3ef 8305 mrs r3, IPSR 8017f42: 60fb str r3, [r7, #12] /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) 8017f44: 68fb ldr r3, [r7, #12] 8017f46: 2b0f cmp r3, #15 8017f48: d915 bls.n 8017f76 { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; 8017f4a: 4a18 ldr r2, [pc, #96] @ (8017fac ) 8017f4c: 68fb ldr r3, [r7, #12] 8017f4e: 4413 add r3, r2 8017f50: 781b ldrb r3, [r3, #0] 8017f52: 72fb strb r3, [r7, #11] interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); 8017f54: 4b16 ldr r3, [pc, #88] @ (8017fb0 ) 8017f56: 781b ldrb r3, [r3, #0] 8017f58: 7afa ldrb r2, [r7, #11] 8017f5a: 429a cmp r2, r3 8017f5c: d20b bcs.n 8017f76 __asm volatile 8017f5e: f04f 0350 mov.w r3, #80 @ 0x50 8017f62: f383 8811 msr BASEPRI, r3 8017f66: f3bf 8f6f isb sy 8017f6a: f3bf 8f4f dsb sy 8017f6e: 607b str r3, [r7, #4] } 8017f70: bf00 nop 8017f72: bf00 nop 8017f74: e7fd b.n 8017f72 configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); 8017f76: 4b0f ldr r3, [pc, #60] @ (8017fb4 ) 8017f78: 681b ldr r3, [r3, #0] 8017f7a: f403 62e0 and.w r2, r3, #1792 @ 0x700 8017f7e: 4b0e ldr r3, [pc, #56] @ (8017fb8 ) 8017f80: 681b ldr r3, [r3, #0] 8017f82: 429a cmp r2, r3 8017f84: d90b bls.n 8017f9e __asm volatile 8017f86: f04f 0350 mov.w r3, #80 @ 0x50 8017f8a: f383 8811 msr BASEPRI, r3 8017f8e: f3bf 8f6f isb sy 8017f92: f3bf 8f4f dsb sy 8017f96: 603b str r3, [r7, #0] } 8017f98: bf00 nop 8017f9a: bf00 nop 8017f9c: e7fd b.n 8017f9a } 8017f9e: bf00 nop 8017fa0: 3714 adds r7, #20 8017fa2: 46bd mov sp, r7 8017fa4: f85d 7b04 ldr.w r7, [sp], #4 8017fa8: 4770 bx lr 8017faa: bf00 nop 8017fac: e000e3f0 .word 0xe000e3f0 8017fb0: 24003024 .word 0x24003024 8017fb4: e000ed0c .word 0xe000ed0c 8017fb8: 24003028 .word 0x24003028 08017fbc : static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ void *pvPortMalloc( size_t xWantedSize ) { 8017fbc: b580 push {r7, lr} 8017fbe: b08a sub sp, #40 @ 0x28 8017fc0: af00 add r7, sp, #0 8017fc2: 6078 str r0, [r7, #4] BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; void *pvReturn = NULL; 8017fc4: 2300 movs r3, #0 8017fc6: 61fb str r3, [r7, #28] vTaskSuspendAll(); 8017fc8: f7fe f914 bl 80161f4 { /* If this is the first call to malloc then the heap will require initialisation to setup the list of free blocks. */ if( pxEnd == NULL ) 8017fcc: 4b5c ldr r3, [pc, #368] @ (8018140 ) 8017fce: 681b ldr r3, [r3, #0] 8017fd0: 2b00 cmp r3, #0 8017fd2: d101 bne.n 8017fd8 { prvHeapInit(); 8017fd4: f000 f924 bl 8018220 /* Check the requested block size is not so large that the top bit is set. The top bit of the block size member of the BlockLink_t structure is used to determine who owns the block - the application or the kernel, so it must be free. */ if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) 8017fd8: 4b5a ldr r3, [pc, #360] @ (8018144 ) 8017fda: 681a ldr r2, [r3, #0] 8017fdc: 687b ldr r3, [r7, #4] 8017fde: 4013 ands r3, r2 8017fe0: 2b00 cmp r3, #0 8017fe2: f040 8095 bne.w 8018110 { /* The wanted size is increased so it can contain a BlockLink_t structure in addition to the requested amount of bytes. */ if( xWantedSize > 0 ) 8017fe6: 687b ldr r3, [r7, #4] 8017fe8: 2b00 cmp r3, #0 8017fea: d01e beq.n 801802a { xWantedSize += xHeapStructSize; 8017fec: 2208 movs r2, #8 8017fee: 687b ldr r3, [r7, #4] 8017ff0: 4413 add r3, r2 8017ff2: 607b str r3, [r7, #4] /* Ensure that blocks are always aligned to the required number of bytes. */ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) 8017ff4: 687b ldr r3, [r7, #4] 8017ff6: f003 0307 and.w r3, r3, #7 8017ffa: 2b00 cmp r3, #0 8017ffc: d015 beq.n 801802a { /* Byte alignment required. */ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); 8017ffe: 687b ldr r3, [r7, #4] 8018000: f023 0307 bic.w r3, r3, #7 8018004: 3308 adds r3, #8 8018006: 607b str r3, [r7, #4] configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); 8018008: 687b ldr r3, [r7, #4] 801800a: f003 0307 and.w r3, r3, #7 801800e: 2b00 cmp r3, #0 8018010: d00b beq.n 801802a __asm volatile 8018012: f04f 0350 mov.w r3, #80 @ 0x50 8018016: f383 8811 msr BASEPRI, r3 801801a: f3bf 8f6f isb sy 801801e: f3bf 8f4f dsb sy 8018022: 617b str r3, [r7, #20] } 8018024: bf00 nop 8018026: bf00 nop 8018028: e7fd b.n 8018026 else { mtCOVERAGE_TEST_MARKER(); } if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) 801802a: 687b ldr r3, [r7, #4] 801802c: 2b00 cmp r3, #0 801802e: d06f beq.n 8018110 8018030: 4b45 ldr r3, [pc, #276] @ (8018148 ) 8018032: 681b ldr r3, [r3, #0] 8018034: 687a ldr r2, [r7, #4] 8018036: 429a cmp r2, r3 8018038: d86a bhi.n 8018110 { /* Traverse the list from the start (lowest address) block until one of adequate size is found. */ pxPreviousBlock = &xStart; 801803a: 4b44 ldr r3, [pc, #272] @ (801814c ) 801803c: 623b str r3, [r7, #32] pxBlock = xStart.pxNextFreeBlock; 801803e: 4b43 ldr r3, [pc, #268] @ (801814c ) 8018040: 681b ldr r3, [r3, #0] 8018042: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 8018044: e004 b.n 8018050 { pxPreviousBlock = pxBlock; 8018046: 6a7b ldr r3, [r7, #36] @ 0x24 8018048: 623b str r3, [r7, #32] pxBlock = pxBlock->pxNextFreeBlock; 801804a: 6a7b ldr r3, [r7, #36] @ 0x24 801804c: 681b ldr r3, [r3, #0] 801804e: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 8018050: 6a7b ldr r3, [r7, #36] @ 0x24 8018052: 685b ldr r3, [r3, #4] 8018054: 687a ldr r2, [r7, #4] 8018056: 429a cmp r2, r3 8018058: d903 bls.n 8018062 801805a: 6a7b ldr r3, [r7, #36] @ 0x24 801805c: 681b ldr r3, [r3, #0] 801805e: 2b00 cmp r3, #0 8018060: d1f1 bne.n 8018046 } /* If the end marker was reached then a block of adequate size was not found. */ if( pxBlock != pxEnd ) 8018062: 4b37 ldr r3, [pc, #220] @ (8018140 ) 8018064: 681b ldr r3, [r3, #0] 8018066: 6a7a ldr r2, [r7, #36] @ 0x24 8018068: 429a cmp r2, r3 801806a: d051 beq.n 8018110 { /* Return the memory space pointed to - jumping over the BlockLink_t structure at its start. */ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); 801806c: 6a3b ldr r3, [r7, #32] 801806e: 681b ldr r3, [r3, #0] 8018070: 2208 movs r2, #8 8018072: 4413 add r3, r2 8018074: 61fb str r3, [r7, #28] /* This block is being returned for use so must be taken out of the list of free blocks. */ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; 8018076: 6a7b ldr r3, [r7, #36] @ 0x24 8018078: 681a ldr r2, [r3, #0] 801807a: 6a3b ldr r3, [r7, #32] 801807c: 601a str r2, [r3, #0] /* If the block is larger than required it can be split into two. */ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) 801807e: 6a7b ldr r3, [r7, #36] @ 0x24 8018080: 685a ldr r2, [r3, #4] 8018082: 687b ldr r3, [r7, #4] 8018084: 1ad2 subs r2, r2, r3 8018086: 2308 movs r3, #8 8018088: 005b lsls r3, r3, #1 801808a: 429a cmp r2, r3 801808c: d920 bls.n 80180d0 { /* This block is to be split into two. Create a new block following the number of bytes requested. The void cast is used to prevent byte alignment warnings from the compiler. */ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); 801808e: 6a7a ldr r2, [r7, #36] @ 0x24 8018090: 687b ldr r3, [r7, #4] 8018092: 4413 add r3, r2 8018094: 61bb str r3, [r7, #24] configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); 8018096: 69bb ldr r3, [r7, #24] 8018098: f003 0307 and.w r3, r3, #7 801809c: 2b00 cmp r3, #0 801809e: d00b beq.n 80180b8 __asm volatile 80180a0: f04f 0350 mov.w r3, #80 @ 0x50 80180a4: f383 8811 msr BASEPRI, r3 80180a8: f3bf 8f6f isb sy 80180ac: f3bf 8f4f dsb sy 80180b0: 613b str r3, [r7, #16] } 80180b2: bf00 nop 80180b4: bf00 nop 80180b6: e7fd b.n 80180b4 /* Calculate the sizes of two blocks split from the single block. */ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; 80180b8: 6a7b ldr r3, [r7, #36] @ 0x24 80180ba: 685a ldr r2, [r3, #4] 80180bc: 687b ldr r3, [r7, #4] 80180be: 1ad2 subs r2, r2, r3 80180c0: 69bb ldr r3, [r7, #24] 80180c2: 605a str r2, [r3, #4] pxBlock->xBlockSize = xWantedSize; 80180c4: 6a7b ldr r3, [r7, #36] @ 0x24 80180c6: 687a ldr r2, [r7, #4] 80180c8: 605a str r2, [r3, #4] /* Insert the new block into the list of free blocks. */ prvInsertBlockIntoFreeList( pxNewBlockLink ); 80180ca: 69b8 ldr r0, [r7, #24] 80180cc: f000 f90a bl 80182e4 else { mtCOVERAGE_TEST_MARKER(); } xFreeBytesRemaining -= pxBlock->xBlockSize; 80180d0: 4b1d ldr r3, [pc, #116] @ (8018148 ) 80180d2: 681a ldr r2, [r3, #0] 80180d4: 6a7b ldr r3, [r7, #36] @ 0x24 80180d6: 685b ldr r3, [r3, #4] 80180d8: 1ad3 subs r3, r2, r3 80180da: 4a1b ldr r2, [pc, #108] @ (8018148 ) 80180dc: 6013 str r3, [r2, #0] if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) 80180de: 4b1a ldr r3, [pc, #104] @ (8018148 ) 80180e0: 681a ldr r2, [r3, #0] 80180e2: 4b1b ldr r3, [pc, #108] @ (8018150 ) 80180e4: 681b ldr r3, [r3, #0] 80180e6: 429a cmp r2, r3 80180e8: d203 bcs.n 80180f2 { xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; 80180ea: 4b17 ldr r3, [pc, #92] @ (8018148 ) 80180ec: 681b ldr r3, [r3, #0] 80180ee: 4a18 ldr r2, [pc, #96] @ (8018150 ) 80180f0: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } /* The block is being returned - it is allocated and owned by the application and has no "next" block. */ pxBlock->xBlockSize |= xBlockAllocatedBit; 80180f2: 6a7b ldr r3, [r7, #36] @ 0x24 80180f4: 685a ldr r2, [r3, #4] 80180f6: 4b13 ldr r3, [pc, #76] @ (8018144 ) 80180f8: 681b ldr r3, [r3, #0] 80180fa: 431a orrs r2, r3 80180fc: 6a7b ldr r3, [r7, #36] @ 0x24 80180fe: 605a str r2, [r3, #4] pxBlock->pxNextFreeBlock = NULL; 8018100: 6a7b ldr r3, [r7, #36] @ 0x24 8018102: 2200 movs r2, #0 8018104: 601a str r2, [r3, #0] xNumberOfSuccessfulAllocations++; 8018106: 4b13 ldr r3, [pc, #76] @ (8018154 ) 8018108: 681b ldr r3, [r3, #0] 801810a: 3301 adds r3, #1 801810c: 4a11 ldr r2, [pc, #68] @ (8018154 ) 801810e: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } traceMALLOC( pvReturn, xWantedSize ); } ( void ) xTaskResumeAll(); 8018110: f7fe f87e bl 8016210 mtCOVERAGE_TEST_MARKER(); } } #endif configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); 8018114: 69fb ldr r3, [r7, #28] 8018116: f003 0307 and.w r3, r3, #7 801811a: 2b00 cmp r3, #0 801811c: d00b beq.n 8018136 __asm volatile 801811e: f04f 0350 mov.w r3, #80 @ 0x50 8018122: f383 8811 msr BASEPRI, r3 8018126: f3bf 8f6f isb sy 801812a: f3bf 8f4f dsb sy 801812e: 60fb str r3, [r7, #12] } 8018130: bf00 nop 8018132: bf00 nop 8018134: e7fd b.n 8018132 return pvReturn; 8018136: 69fb ldr r3, [r7, #28] } 8018138: 4618 mov r0, r3 801813a: 3728 adds r7, #40 @ 0x28 801813c: 46bd mov sp, r7 801813e: bd80 pop {r7, pc} 8018140: 24013034 .word 0x24013034 8018144: 24013048 .word 0x24013048 8018148: 24013038 .word 0x24013038 801814c: 2401302c .word 0x2401302c 8018150: 2401303c .word 0x2401303c 8018154: 24013040 .word 0x24013040 08018158 : /*-----------------------------------------------------------*/ void vPortFree( void *pv ) { 8018158: b580 push {r7, lr} 801815a: b086 sub sp, #24 801815c: af00 add r7, sp, #0 801815e: 6078 str r0, [r7, #4] uint8_t *puc = ( uint8_t * ) pv; 8018160: 687b ldr r3, [r7, #4] 8018162: 617b str r3, [r7, #20] BlockLink_t *pxLink; if( pv != NULL ) 8018164: 687b ldr r3, [r7, #4] 8018166: 2b00 cmp r3, #0 8018168: d04f beq.n 801820a { /* The memory being freed will have an BlockLink_t structure immediately before it. */ puc -= xHeapStructSize; 801816a: 2308 movs r3, #8 801816c: 425b negs r3, r3 801816e: 697a ldr r2, [r7, #20] 8018170: 4413 add r3, r2 8018172: 617b str r3, [r7, #20] /* This casting is to keep the compiler from issuing warnings. */ pxLink = ( void * ) puc; 8018174: 697b ldr r3, [r7, #20] 8018176: 613b str r3, [r7, #16] /* Check the block is actually allocated. */ configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); 8018178: 693b ldr r3, [r7, #16] 801817a: 685a ldr r2, [r3, #4] 801817c: 4b25 ldr r3, [pc, #148] @ (8018214 ) 801817e: 681b ldr r3, [r3, #0] 8018180: 4013 ands r3, r2 8018182: 2b00 cmp r3, #0 8018184: d10b bne.n 801819e __asm volatile 8018186: f04f 0350 mov.w r3, #80 @ 0x50 801818a: f383 8811 msr BASEPRI, r3 801818e: f3bf 8f6f isb sy 8018192: f3bf 8f4f dsb sy 8018196: 60fb str r3, [r7, #12] } 8018198: bf00 nop 801819a: bf00 nop 801819c: e7fd b.n 801819a configASSERT( pxLink->pxNextFreeBlock == NULL ); 801819e: 693b ldr r3, [r7, #16] 80181a0: 681b ldr r3, [r3, #0] 80181a2: 2b00 cmp r3, #0 80181a4: d00b beq.n 80181be __asm volatile 80181a6: f04f 0350 mov.w r3, #80 @ 0x50 80181aa: f383 8811 msr BASEPRI, r3 80181ae: f3bf 8f6f isb sy 80181b2: f3bf 8f4f dsb sy 80181b6: 60bb str r3, [r7, #8] } 80181b8: bf00 nop 80181ba: bf00 nop 80181bc: e7fd b.n 80181ba if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) 80181be: 693b ldr r3, [r7, #16] 80181c0: 685a ldr r2, [r3, #4] 80181c2: 4b14 ldr r3, [pc, #80] @ (8018214 ) 80181c4: 681b ldr r3, [r3, #0] 80181c6: 4013 ands r3, r2 80181c8: 2b00 cmp r3, #0 80181ca: d01e beq.n 801820a { if( pxLink->pxNextFreeBlock == NULL ) 80181cc: 693b ldr r3, [r7, #16] 80181ce: 681b ldr r3, [r3, #0] 80181d0: 2b00 cmp r3, #0 80181d2: d11a bne.n 801820a { /* The block is being returned to the heap - it is no longer allocated. */ pxLink->xBlockSize &= ~xBlockAllocatedBit; 80181d4: 693b ldr r3, [r7, #16] 80181d6: 685a ldr r2, [r3, #4] 80181d8: 4b0e ldr r3, [pc, #56] @ (8018214 ) 80181da: 681b ldr r3, [r3, #0] 80181dc: 43db mvns r3, r3 80181de: 401a ands r2, r3 80181e0: 693b ldr r3, [r7, #16] 80181e2: 605a str r2, [r3, #4] vTaskSuspendAll(); 80181e4: f7fe f806 bl 80161f4 { /* Add this block to the list of free blocks. */ xFreeBytesRemaining += pxLink->xBlockSize; 80181e8: 693b ldr r3, [r7, #16] 80181ea: 685a ldr r2, [r3, #4] 80181ec: 4b0a ldr r3, [pc, #40] @ (8018218 ) 80181ee: 681b ldr r3, [r3, #0] 80181f0: 4413 add r3, r2 80181f2: 4a09 ldr r2, [pc, #36] @ (8018218 ) 80181f4: 6013 str r3, [r2, #0] traceFREE( pv, pxLink->xBlockSize ); prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); 80181f6: 6938 ldr r0, [r7, #16] 80181f8: f000 f874 bl 80182e4 xNumberOfSuccessfulFrees++; 80181fc: 4b07 ldr r3, [pc, #28] @ (801821c ) 80181fe: 681b ldr r3, [r3, #0] 8018200: 3301 adds r3, #1 8018202: 4a06 ldr r2, [pc, #24] @ (801821c ) 8018204: 6013 str r3, [r2, #0] } ( void ) xTaskResumeAll(); 8018206: f7fe f803 bl 8016210 else { mtCOVERAGE_TEST_MARKER(); } } } 801820a: bf00 nop 801820c: 3718 adds r7, #24 801820e: 46bd mov sp, r7 8018210: bd80 pop {r7, pc} 8018212: bf00 nop 8018214: 24013048 .word 0x24013048 8018218: 24013038 .word 0x24013038 801821c: 24013044 .word 0x24013044 08018220 : /* This just exists to keep the linker quiet. */ } /*-----------------------------------------------------------*/ static void prvHeapInit( void ) { 8018220: b480 push {r7} 8018222: b085 sub sp, #20 8018224: af00 add r7, sp, #0 BlockLink_t *pxFirstFreeBlock; uint8_t *pucAlignedHeap; size_t uxAddress; size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; 8018226: f44f 3380 mov.w r3, #65536 @ 0x10000 801822a: 60bb str r3, [r7, #8] /* Ensure the heap starts on a correctly aligned boundary. */ uxAddress = ( size_t ) ucHeap; 801822c: 4b27 ldr r3, [pc, #156] @ (80182cc ) 801822e: 60fb str r3, [r7, #12] if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) 8018230: 68fb ldr r3, [r7, #12] 8018232: f003 0307 and.w r3, r3, #7 8018236: 2b00 cmp r3, #0 8018238: d00c beq.n 8018254 { uxAddress += ( portBYTE_ALIGNMENT - 1 ); 801823a: 68fb ldr r3, [r7, #12] 801823c: 3307 adds r3, #7 801823e: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 8018240: 68fb ldr r3, [r7, #12] 8018242: f023 0307 bic.w r3, r3, #7 8018246: 60fb str r3, [r7, #12] xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; 8018248: 68ba ldr r2, [r7, #8] 801824a: 68fb ldr r3, [r7, #12] 801824c: 1ad3 subs r3, r2, r3 801824e: 4a1f ldr r2, [pc, #124] @ (80182cc ) 8018250: 4413 add r3, r2 8018252: 60bb str r3, [r7, #8] } pucAlignedHeap = ( uint8_t * ) uxAddress; 8018254: 68fb ldr r3, [r7, #12] 8018256: 607b str r3, [r7, #4] /* xStart is used to hold a pointer to the first item in the list of free blocks. The void cast is used to prevent compiler warnings. */ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; 8018258: 4a1d ldr r2, [pc, #116] @ (80182d0 ) 801825a: 687b ldr r3, [r7, #4] 801825c: 6013 str r3, [r2, #0] xStart.xBlockSize = ( size_t ) 0; 801825e: 4b1c ldr r3, [pc, #112] @ (80182d0 ) 8018260: 2200 movs r2, #0 8018262: 605a str r2, [r3, #4] /* pxEnd is used to mark the end of the list of free blocks and is inserted at the end of the heap space. */ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; 8018264: 687b ldr r3, [r7, #4] 8018266: 68ba ldr r2, [r7, #8] 8018268: 4413 add r3, r2 801826a: 60fb str r3, [r7, #12] uxAddress -= xHeapStructSize; 801826c: 2208 movs r2, #8 801826e: 68fb ldr r3, [r7, #12] 8018270: 1a9b subs r3, r3, r2 8018272: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 8018274: 68fb ldr r3, [r7, #12] 8018276: f023 0307 bic.w r3, r3, #7 801827a: 60fb str r3, [r7, #12] pxEnd = ( void * ) uxAddress; 801827c: 68fb ldr r3, [r7, #12] 801827e: 4a15 ldr r2, [pc, #84] @ (80182d4 ) 8018280: 6013 str r3, [r2, #0] pxEnd->xBlockSize = 0; 8018282: 4b14 ldr r3, [pc, #80] @ (80182d4 ) 8018284: 681b ldr r3, [r3, #0] 8018286: 2200 movs r2, #0 8018288: 605a str r2, [r3, #4] pxEnd->pxNextFreeBlock = NULL; 801828a: 4b12 ldr r3, [pc, #72] @ (80182d4 ) 801828c: 681b ldr r3, [r3, #0] 801828e: 2200 movs r2, #0 8018290: 601a str r2, [r3, #0] /* To start with there is a single free block that is sized to take up the entire heap space, minus the space taken by pxEnd. */ pxFirstFreeBlock = ( void * ) pucAlignedHeap; 8018292: 687b ldr r3, [r7, #4] 8018294: 603b str r3, [r7, #0] pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; 8018296: 683b ldr r3, [r7, #0] 8018298: 68fa ldr r2, [r7, #12] 801829a: 1ad2 subs r2, r2, r3 801829c: 683b ldr r3, [r7, #0] 801829e: 605a str r2, [r3, #4] pxFirstFreeBlock->pxNextFreeBlock = pxEnd; 80182a0: 4b0c ldr r3, [pc, #48] @ (80182d4 ) 80182a2: 681a ldr r2, [r3, #0] 80182a4: 683b ldr r3, [r7, #0] 80182a6: 601a str r2, [r3, #0] /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 80182a8: 683b ldr r3, [r7, #0] 80182aa: 685b ldr r3, [r3, #4] 80182ac: 4a0a ldr r2, [pc, #40] @ (80182d8 ) 80182ae: 6013 str r3, [r2, #0] xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 80182b0: 683b ldr r3, [r7, #0] 80182b2: 685b ldr r3, [r3, #4] 80182b4: 4a09 ldr r2, [pc, #36] @ (80182dc ) 80182b6: 6013 str r3, [r2, #0] /* Work out the position of the top bit in a size_t variable. */ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); 80182b8: 4b09 ldr r3, [pc, #36] @ (80182e0 ) 80182ba: f04f 4200 mov.w r2, #2147483648 @ 0x80000000 80182be: 601a str r2, [r3, #0] } 80182c0: bf00 nop 80182c2: 3714 adds r7, #20 80182c4: 46bd mov sp, r7 80182c6: f85d 7b04 ldr.w r7, [sp], #4 80182ca: 4770 bx lr 80182cc: 2400302c .word 0x2400302c 80182d0: 2401302c .word 0x2401302c 80182d4: 24013034 .word 0x24013034 80182d8: 2401303c .word 0x2401303c 80182dc: 24013038 .word 0x24013038 80182e0: 24013048 .word 0x24013048 080182e4 : /*-----------------------------------------------------------*/ static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) { 80182e4: b480 push {r7} 80182e6: b085 sub sp, #20 80182e8: af00 add r7, sp, #0 80182ea: 6078 str r0, [r7, #4] BlockLink_t *pxIterator; uint8_t *puc; /* Iterate through the list until a block is found that has a higher address than the block being inserted. */ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) 80182ec: 4b28 ldr r3, [pc, #160] @ (8018390 ) 80182ee: 60fb str r3, [r7, #12] 80182f0: e002 b.n 80182f8 80182f2: 68fb ldr r3, [r7, #12] 80182f4: 681b ldr r3, [r3, #0] 80182f6: 60fb str r3, [r7, #12] 80182f8: 68fb ldr r3, [r7, #12] 80182fa: 681b ldr r3, [r3, #0] 80182fc: 687a ldr r2, [r7, #4] 80182fe: 429a cmp r2, r3 8018300: d8f7 bhi.n 80182f2 /* Nothing to do here, just iterate to the right position. */ } /* Do the block being inserted, and the block it is being inserted after make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; 8018302: 68fb ldr r3, [r7, #12] 8018304: 60bb str r3, [r7, #8] if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) 8018306: 68fb ldr r3, [r7, #12] 8018308: 685b ldr r3, [r3, #4] 801830a: 68ba ldr r2, [r7, #8] 801830c: 4413 add r3, r2 801830e: 687a ldr r2, [r7, #4] 8018310: 429a cmp r2, r3 8018312: d108 bne.n 8018326 { pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 8018314: 68fb ldr r3, [r7, #12] 8018316: 685a ldr r2, [r3, #4] 8018318: 687b ldr r3, [r7, #4] 801831a: 685b ldr r3, [r3, #4] 801831c: 441a add r2, r3 801831e: 68fb ldr r3, [r7, #12] 8018320: 605a str r2, [r3, #4] pxBlockToInsert = pxIterator; 8018322: 68fb ldr r3, [r7, #12] 8018324: 607b str r3, [r7, #4] mtCOVERAGE_TEST_MARKER(); } /* Do the block being inserted, and the block it is being inserted before make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; 8018326: 687b ldr r3, [r7, #4] 8018328: 60bb str r3, [r7, #8] if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 801832a: 687b ldr r3, [r7, #4] 801832c: 685b ldr r3, [r3, #4] 801832e: 68ba ldr r2, [r7, #8] 8018330: 441a add r2, r3 8018332: 68fb ldr r3, [r7, #12] 8018334: 681b ldr r3, [r3, #0] 8018336: 429a cmp r2, r3 8018338: d118 bne.n 801836c { if( pxIterator->pxNextFreeBlock != pxEnd ) 801833a: 68fb ldr r3, [r7, #12] 801833c: 681a ldr r2, [r3, #0] 801833e: 4b15 ldr r3, [pc, #84] @ (8018394 ) 8018340: 681b ldr r3, [r3, #0] 8018342: 429a cmp r2, r3 8018344: d00d beq.n 8018362 { /* Form one big block from the two blocks. */ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; 8018346: 687b ldr r3, [r7, #4] 8018348: 685a ldr r2, [r3, #4] 801834a: 68fb ldr r3, [r7, #12] 801834c: 681b ldr r3, [r3, #0] 801834e: 685b ldr r3, [r3, #4] 8018350: 441a add r2, r3 8018352: 687b ldr r3, [r7, #4] 8018354: 605a str r2, [r3, #4] pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; 8018356: 68fb ldr r3, [r7, #12] 8018358: 681b ldr r3, [r3, #0] 801835a: 681a ldr r2, [r3, #0] 801835c: 687b ldr r3, [r7, #4] 801835e: 601a str r2, [r3, #0] 8018360: e008 b.n 8018374 } else { pxBlockToInsert->pxNextFreeBlock = pxEnd; 8018362: 4b0c ldr r3, [pc, #48] @ (8018394 ) 8018364: 681a ldr r2, [r3, #0] 8018366: 687b ldr r3, [r7, #4] 8018368: 601a str r2, [r3, #0] 801836a: e003 b.n 8018374 } } else { pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; 801836c: 68fb ldr r3, [r7, #12] 801836e: 681a ldr r2, [r3, #0] 8018370: 687b ldr r3, [r7, #4] 8018372: 601a str r2, [r3, #0] /* If the block being inserted plugged a gab, so was merged with the block before and the block after, then it's pxNextFreeBlock pointer will have already been set, and should not be set here as that would make it point to itself. */ if( pxIterator != pxBlockToInsert ) 8018374: 68fa ldr r2, [r7, #12] 8018376: 687b ldr r3, [r7, #4] 8018378: 429a cmp r2, r3 801837a: d002 beq.n 8018382 { pxIterator->pxNextFreeBlock = pxBlockToInsert; 801837c: 68fb ldr r3, [r7, #12] 801837e: 687a ldr r2, [r7, #4] 8018380: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 8018382: bf00 nop 8018384: 3714 adds r7, #20 8018386: 46bd mov sp, r7 8018388: f85d 7b04 ldr.w r7, [sp], #4 801838c: 4770 bx lr 801838e: bf00 nop 8018390: 2401302c .word 0x2401302c 8018394: 24013034 .word 0x24013034 08018398 : 8018398: 4402 add r2, r0 801839a: 4603 mov r3, r0 801839c: 4293 cmp r3, r2 801839e: d100 bne.n 80183a2 80183a0: 4770 bx lr 80183a2: f803 1b01 strb.w r1, [r3], #1 80183a6: e7f9 b.n 801839c 080183a8 <_reclaim_reent>: 80183a8: 4b29 ldr r3, [pc, #164] @ (8018450 <_reclaim_reent+0xa8>) 80183aa: 681b ldr r3, [r3, #0] 80183ac: 4283 cmp r3, r0 80183ae: b570 push {r4, r5, r6, lr} 80183b0: 4604 mov r4, r0 80183b2: d04b beq.n 801844c <_reclaim_reent+0xa4> 80183b4: 69c3 ldr r3, [r0, #28] 80183b6: b1ab cbz r3, 80183e4 <_reclaim_reent+0x3c> 80183b8: 68db ldr r3, [r3, #12] 80183ba: b16b cbz r3, 80183d8 <_reclaim_reent+0x30> 80183bc: 2500 movs r5, #0 80183be: 69e3 ldr r3, [r4, #28] 80183c0: 68db ldr r3, [r3, #12] 80183c2: 5959 ldr r1, [r3, r5] 80183c4: 2900 cmp r1, #0 80183c6: d13b bne.n 8018440 <_reclaim_reent+0x98> 80183c8: 3504 adds r5, #4 80183ca: 2d80 cmp r5, #128 @ 0x80 80183cc: d1f7 bne.n 80183be <_reclaim_reent+0x16> 80183ce: 69e3 ldr r3, [r4, #28] 80183d0: 4620 mov r0, r4 80183d2: 68d9 ldr r1, [r3, #12] 80183d4: f000 f878 bl 80184c8 <_free_r> 80183d8: 69e3 ldr r3, [r4, #28] 80183da: 6819 ldr r1, [r3, #0] 80183dc: b111 cbz r1, 80183e4 <_reclaim_reent+0x3c> 80183de: 4620 mov r0, r4 80183e0: f000 f872 bl 80184c8 <_free_r> 80183e4: 6961 ldr r1, [r4, #20] 80183e6: b111 cbz r1, 80183ee <_reclaim_reent+0x46> 80183e8: 4620 mov r0, r4 80183ea: f000 f86d bl 80184c8 <_free_r> 80183ee: 69e1 ldr r1, [r4, #28] 80183f0: b111 cbz r1, 80183f8 <_reclaim_reent+0x50> 80183f2: 4620 mov r0, r4 80183f4: f000 f868 bl 80184c8 <_free_r> 80183f8: 6b21 ldr r1, [r4, #48] @ 0x30 80183fa: b111 cbz r1, 8018402 <_reclaim_reent+0x5a> 80183fc: 4620 mov r0, r4 80183fe: f000 f863 bl 80184c8 <_free_r> 8018402: 6b61 ldr r1, [r4, #52] @ 0x34 8018404: b111 cbz r1, 801840c <_reclaim_reent+0x64> 8018406: 4620 mov r0, r4 8018408: f000 f85e bl 80184c8 <_free_r> 801840c: 6ba1 ldr r1, [r4, #56] @ 0x38 801840e: b111 cbz r1, 8018416 <_reclaim_reent+0x6e> 8018410: 4620 mov r0, r4 8018412: f000 f859 bl 80184c8 <_free_r> 8018416: 6ca1 ldr r1, [r4, #72] @ 0x48 8018418: b111 cbz r1, 8018420 <_reclaim_reent+0x78> 801841a: 4620 mov r0, r4 801841c: f000 f854 bl 80184c8 <_free_r> 8018420: 6c61 ldr r1, [r4, #68] @ 0x44 8018422: b111 cbz r1, 801842a <_reclaim_reent+0x82> 8018424: 4620 mov r0, r4 8018426: f000 f84f bl 80184c8 <_free_r> 801842a: 6ae1 ldr r1, [r4, #44] @ 0x2c 801842c: b111 cbz r1, 8018434 <_reclaim_reent+0x8c> 801842e: 4620 mov r0, r4 8018430: f000 f84a bl 80184c8 <_free_r> 8018434: 6a23 ldr r3, [r4, #32] 8018436: b14b cbz r3, 801844c <_reclaim_reent+0xa4> 8018438: 4620 mov r0, r4 801843a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} 801843e: 4718 bx r3 8018440: 680e ldr r6, [r1, #0] 8018442: 4620 mov r0, r4 8018444: f000 f840 bl 80184c8 <_free_r> 8018448: 4631 mov r1, r6 801844a: e7bb b.n 80183c4 <_reclaim_reent+0x1c> 801844c: bd70 pop {r4, r5, r6, pc} 801844e: bf00 nop 8018450: 24000048 .word 0x24000048 08018454 <__errno>: 8018454: 4b01 ldr r3, [pc, #4] @ (801845c <__errno+0x8>) 8018456: 6818 ldr r0, [r3, #0] 8018458: 4770 bx lr 801845a: bf00 nop 801845c: 24000048 .word 0x24000048 08018460 <__libc_init_array>: 8018460: b570 push {r4, r5, r6, lr} 8018462: 4d0d ldr r5, [pc, #52] @ (8018498 <__libc_init_array+0x38>) 8018464: 4c0d ldr r4, [pc, #52] @ (801849c <__libc_init_array+0x3c>) 8018466: 1b64 subs r4, r4, r5 8018468: 10a4 asrs r4, r4, #2 801846a: 2600 movs r6, #0 801846c: 42a6 cmp r6, r4 801846e: d109 bne.n 8018484 <__libc_init_array+0x24> 8018470: 4d0b ldr r5, [pc, #44] @ (80184a0 <__libc_init_array+0x40>) 8018472: 4c0c ldr r4, [pc, #48] @ (80184a4 <__libc_init_array+0x44>) 8018474: f000 f920 bl 80186b8 <_init> 8018478: 1b64 subs r4, r4, r5 801847a: 10a4 asrs r4, r4, #2 801847c: 2600 movs r6, #0 801847e: 42a6 cmp r6, r4 8018480: d105 bne.n 801848e <__libc_init_array+0x2e> 8018482: bd70 pop {r4, r5, r6, pc} 8018484: f855 3b04 ldr.w r3, [r5], #4 8018488: 4798 blx r3 801848a: 3601 adds r6, #1 801848c: e7ee b.n 801846c <__libc_init_array+0xc> 801848e: f855 3b04 ldr.w r3, [r5], #4 8018492: 4798 blx r3 8018494: 3601 adds r6, #1 8018496: e7f2 b.n 801847e <__libc_init_array+0x1e> 8018498: 080187dc .word 0x080187dc 801849c: 080187dc .word 0x080187dc 80184a0: 080187dc .word 0x080187dc 80184a4: 080187e0 .word 0x080187e0 080184a8 <__retarget_lock_acquire_recursive>: 80184a8: 4770 bx lr 080184aa <__retarget_lock_release_recursive>: 80184aa: 4770 bx lr 080184ac : 80184ac: 440a add r2, r1 80184ae: 4291 cmp r1, r2 80184b0: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 80184b4: d100 bne.n 80184b8 80184b6: 4770 bx lr 80184b8: b510 push {r4, lr} 80184ba: f811 4b01 ldrb.w r4, [r1], #1 80184be: f803 4f01 strb.w r4, [r3, #1]! 80184c2: 4291 cmp r1, r2 80184c4: d1f9 bne.n 80184ba 80184c6: bd10 pop {r4, pc} 080184c8 <_free_r>: 80184c8: b538 push {r3, r4, r5, lr} 80184ca: 4605 mov r5, r0 80184cc: 2900 cmp r1, #0 80184ce: d041 beq.n 8018554 <_free_r+0x8c> 80184d0: f851 3c04 ldr.w r3, [r1, #-4] 80184d4: 1f0c subs r4, r1, #4 80184d6: 2b00 cmp r3, #0 80184d8: bfb8 it lt 80184da: 18e4 addlt r4, r4, r3 80184dc: f000 f83e bl 801855c <__malloc_lock> 80184e0: 4a1d ldr r2, [pc, #116] @ (8018558 <_free_r+0x90>) 80184e2: 6813 ldr r3, [r2, #0] 80184e4: b933 cbnz r3, 80184f4 <_free_r+0x2c> 80184e6: 6063 str r3, [r4, #4] 80184e8: 6014 str r4, [r2, #0] 80184ea: 4628 mov r0, r5 80184ec: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 80184f0: f000 b83a b.w 8018568 <__malloc_unlock> 80184f4: 42a3 cmp r3, r4 80184f6: d908 bls.n 801850a <_free_r+0x42> 80184f8: 6820 ldr r0, [r4, #0] 80184fa: 1821 adds r1, r4, r0 80184fc: 428b cmp r3, r1 80184fe: bf01 itttt eq 8018500: 6819 ldreq r1, [r3, #0] 8018502: 685b ldreq r3, [r3, #4] 8018504: 1809 addeq r1, r1, r0 8018506: 6021 streq r1, [r4, #0] 8018508: e7ed b.n 80184e6 <_free_r+0x1e> 801850a: 461a mov r2, r3 801850c: 685b ldr r3, [r3, #4] 801850e: b10b cbz r3, 8018514 <_free_r+0x4c> 8018510: 42a3 cmp r3, r4 8018512: d9fa bls.n 801850a <_free_r+0x42> 8018514: 6811 ldr r1, [r2, #0] 8018516: 1850 adds r0, r2, r1 8018518: 42a0 cmp r0, r4 801851a: d10b bne.n 8018534 <_free_r+0x6c> 801851c: 6820 ldr r0, [r4, #0] 801851e: 4401 add r1, r0 8018520: 1850 adds r0, r2, r1 8018522: 4283 cmp r3, r0 8018524: 6011 str r1, [r2, #0] 8018526: d1e0 bne.n 80184ea <_free_r+0x22> 8018528: 6818 ldr r0, [r3, #0] 801852a: 685b ldr r3, [r3, #4] 801852c: 6053 str r3, [r2, #4] 801852e: 4408 add r0, r1 8018530: 6010 str r0, [r2, #0] 8018532: e7da b.n 80184ea <_free_r+0x22> 8018534: d902 bls.n 801853c <_free_r+0x74> 8018536: 230c movs r3, #12 8018538: 602b str r3, [r5, #0] 801853a: e7d6 b.n 80184ea <_free_r+0x22> 801853c: 6820 ldr r0, [r4, #0] 801853e: 1821 adds r1, r4, r0 8018540: 428b cmp r3, r1 8018542: bf04 itt eq 8018544: 6819 ldreq r1, [r3, #0] 8018546: 685b ldreq r3, [r3, #4] 8018548: 6063 str r3, [r4, #4] 801854a: bf04 itt eq 801854c: 1809 addeq r1, r1, r0 801854e: 6021 streq r1, [r4, #0] 8018550: 6054 str r4, [r2, #4] 8018552: e7ca b.n 80184ea <_free_r+0x22> 8018554: bd38 pop {r3, r4, r5, pc} 8018556: bf00 nop 8018558: 24013188 .word 0x24013188 0801855c <__malloc_lock>: 801855c: 4801 ldr r0, [pc, #4] @ (8018564 <__malloc_lock+0x8>) 801855e: f7ff bfa3 b.w 80184a8 <__retarget_lock_acquire_recursive> 8018562: bf00 nop 8018564: 24013184 .word 0x24013184 08018568 <__malloc_unlock>: 8018568: 4801 ldr r0, [pc, #4] @ (8018570 <__malloc_unlock+0x8>) 801856a: f7ff bf9e b.w 80184aa <__retarget_lock_release_recursive> 801856e: bf00 nop 8018570: 24013184 .word 0x24013184 08018574 : 8018574: b508 push {r3, lr} 8018576: ed2d 8b02 vpush {d8} 801857a: eef0 8a40 vmov.f32 s17, s0 801857e: eeb0 8a60 vmov.f32 s16, s1 8018582: f000 f817 bl 80185b4 <__ieee754_fmodf> 8018586: eef4 8a48 vcmp.f32 s17, s16 801858a: eef1 fa10 vmrs APSR_nzcv, fpscr 801858e: d60c bvs.n 80185aa 8018590: eddf 8a07 vldr s17, [pc, #28] @ 80185b0 8018594: eeb4 8a68 vcmp.f32 s16, s17 8018598: eef1 fa10 vmrs APSR_nzcv, fpscr 801859c: d105 bne.n 80185aa 801859e: f7ff ff59 bl 8018454 <__errno> 80185a2: ee88 0aa8 vdiv.f32 s0, s17, s17 80185a6: 2321 movs r3, #33 @ 0x21 80185a8: 6003 str r3, [r0, #0] 80185aa: ecbd 8b02 vpop {d8} 80185ae: bd08 pop {r3, pc} 80185b0: 00000000 .word 0x00000000 080185b4 <__ieee754_fmodf>: 80185b4: b5f0 push {r4, r5, r6, r7, lr} 80185b6: ee10 5a90 vmov r5, s1 80185ba: f025 4000 bic.w r0, r5, #2147483648 @ 0x80000000 80185be: 1e43 subs r3, r0, #1 80185c0: f1b3 4fff cmp.w r3, #2139095040 @ 0x7f800000 80185c4: d206 bcs.n 80185d4 <__ieee754_fmodf+0x20> 80185c6: ee10 3a10 vmov r3, s0 80185ca: f023 4600 bic.w r6, r3, #2147483648 @ 0x80000000 80185ce: f1b6 4fff cmp.w r6, #2139095040 @ 0x7f800000 80185d2: d304 bcc.n 80185de <__ieee754_fmodf+0x2a> 80185d4: ee60 0a20 vmul.f32 s1, s0, s1 80185d8: ee80 0aa0 vdiv.f32 s0, s1, s1 80185dc: bdf0 pop {r4, r5, r6, r7, pc} 80185de: 4286 cmp r6, r0 80185e0: dbfc blt.n 80185dc <__ieee754_fmodf+0x28> 80185e2: f003 4400 and.w r4, r3, #2147483648 @ 0x80000000 80185e6: d105 bne.n 80185f4 <__ieee754_fmodf+0x40> 80185e8: 4b32 ldr r3, [pc, #200] @ (80186b4 <__ieee754_fmodf+0x100>) 80185ea: eb03 7354 add.w r3, r3, r4, lsr #29 80185ee: ed93 0a00 vldr s0, [r3] 80185f2: e7f3 b.n 80185dc <__ieee754_fmodf+0x28> 80185f4: f013 4fff tst.w r3, #2139095040 @ 0x7f800000 80185f8: d140 bne.n 801867c <__ieee754_fmodf+0xc8> 80185fa: 0232 lsls r2, r6, #8 80185fc: f06f 017d mvn.w r1, #125 @ 0x7d 8018600: 2a00 cmp r2, #0 8018602: dc38 bgt.n 8018676 <__ieee754_fmodf+0xc2> 8018604: f015 4fff tst.w r5, #2139095040 @ 0x7f800000 8018608: d13e bne.n 8018688 <__ieee754_fmodf+0xd4> 801860a: 0207 lsls r7, r0, #8 801860c: f06f 027d mvn.w r2, #125 @ 0x7d 8018610: 2f00 cmp r7, #0 8018612: da36 bge.n 8018682 <__ieee754_fmodf+0xce> 8018614: f111 0f7e cmn.w r1, #126 @ 0x7e 8018618: bfb9 ittee lt 801861a: f06f 037d mvnlt.w r3, #125 @ 0x7d 801861e: 1a5b sublt r3, r3, r1 8018620: f3c3 0316 ubfxge r3, r3, #0, #23 8018624: f443 0300 orrge.w r3, r3, #8388608 @ 0x800000 8018628: bfb8 it lt 801862a: fa06 f303 lsllt.w r3, r6, r3 801862e: f112 0f7e cmn.w r2, #126 @ 0x7e 8018632: bfb5 itete lt 8018634: f06f 057d mvnlt.w r5, #125 @ 0x7d 8018638: f3c5 0516 ubfxge r5, r5, #0, #23 801863c: 1aad sublt r5, r5, r2 801863e: f445 0000 orrge.w r0, r5, #8388608 @ 0x800000 8018642: bfb8 it lt 8018644: 40a8 lsllt r0, r5 8018646: 1a89 subs r1, r1, r2 8018648: 1a1d subs r5, r3, r0 801864a: bb01 cbnz r1, 801868e <__ieee754_fmodf+0xda> 801864c: ea13 0325 ands.w r3, r3, r5, asr #32 8018650: bf38 it cc 8018652: 462b movcc r3, r5 8018654: 2b00 cmp r3, #0 8018656: d0c7 beq.n 80185e8 <__ieee754_fmodf+0x34> 8018658: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 801865c: db1f blt.n 801869e <__ieee754_fmodf+0xea> 801865e: f112 0f7e cmn.w r2, #126 @ 0x7e 8018662: db1f blt.n 80186a4 <__ieee754_fmodf+0xf0> 8018664: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 8018668: 327f adds r2, #127 @ 0x7f 801866a: 4323 orrs r3, r4 801866c: ea43 53c2 orr.w r3, r3, r2, lsl #23 8018670: ee00 3a10 vmov s0, r3 8018674: e7b2 b.n 80185dc <__ieee754_fmodf+0x28> 8018676: 3901 subs r1, #1 8018678: 0052 lsls r2, r2, #1 801867a: e7c1 b.n 8018600 <__ieee754_fmodf+0x4c> 801867c: 15f1 asrs r1, r6, #23 801867e: 397f subs r1, #127 @ 0x7f 8018680: e7c0 b.n 8018604 <__ieee754_fmodf+0x50> 8018682: 3a01 subs r2, #1 8018684: 007f lsls r7, r7, #1 8018686: e7c3 b.n 8018610 <__ieee754_fmodf+0x5c> 8018688: 15c2 asrs r2, r0, #23 801868a: 3a7f subs r2, #127 @ 0x7f 801868c: e7c2 b.n 8018614 <__ieee754_fmodf+0x60> 801868e: 2d00 cmp r5, #0 8018690: da02 bge.n 8018698 <__ieee754_fmodf+0xe4> 8018692: 005b lsls r3, r3, #1 8018694: 3901 subs r1, #1 8018696: e7d7 b.n 8018648 <__ieee754_fmodf+0x94> 8018698: d0a6 beq.n 80185e8 <__ieee754_fmodf+0x34> 801869a: 006b lsls r3, r5, #1 801869c: e7fa b.n 8018694 <__ieee754_fmodf+0xe0> 801869e: 005b lsls r3, r3, #1 80186a0: 3a01 subs r2, #1 80186a2: e7d9 b.n 8018658 <__ieee754_fmodf+0xa4> 80186a4: f1c2 22ff rsb r2, r2, #4278255360 @ 0xff00ff00 80186a8: f502 027f add.w r2, r2, #16711680 @ 0xff0000 80186ac: 3282 adds r2, #130 @ 0x82 80186ae: 4113 asrs r3, r2 80186b0: 4323 orrs r3, r4 80186b2: e7dd b.n 8018670 <__ieee754_fmodf+0xbc> 80186b4: 080187cc .word 0x080187cc 080186b8 <_init>: 80186b8: b5f8 push {r3, r4, r5, r6, r7, lr} 80186ba: bf00 nop 80186bc: bcf8 pop {r3, r4, r5, r6, r7} 80186be: bc08 pop {r3} 80186c0: 469e mov lr, r3 80186c2: 4770 bx lr 080186c4 <_fini>: 80186c4: b5f8 push {r3, r4, r5, r6, r7, lr} 80186c6: bf00 nop 80186c8: bcf8 pop {r3, r4, r5, r6, r7} 80186ca: bc08 pop {r3} 80186cc: 469e mov lr, r3 80186ce: 4770 bx lr