OZE_Sensor.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000298 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000171c8 080002a0 080002a0 000012a0 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 000001d4 08017468 08017468 00018468 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM 00000008 0801763c 0801763c 0001863c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .init_array 00000004 08017644 08017644 00018644 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .fini_array 00000004 08017648 08017648 00018648 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 6 .data 000000a4 24000000 0801764c 00019000 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .bss 00012c84 240000c0 080176f0 000190c0 2**5 ALLOC 8 ._user_heap_stack 00000604 24012d44 080176f0 00019d44 2**0 ALLOC 9 .ARM.attributes 0000002e 00000000 00000000 000190a4 2**0 CONTENTS, READONLY 10 .debug_info 00032953 00000000 00000000 000190d2 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_abbrev 00006060 00000000 00000000 0004ba25 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_aranges 00002410 00000000 00000000 00051a88 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_macro 0003ec89 00000000 00000000 00053e98 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_line 0002f2d3 00000000 00000000 00092b21 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_str 00185536 00000000 00000000 000c1df4 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .comment 00000043 00000000 00000000 0024732a 2**0 CONTENTS, READONLY 17 .debug_rnglists 00001bc5 00000000 00000000 0024736d 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_frame 00009fc8 00000000 00000000 00248f34 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_line_str 00000066 00000000 00000000 00252efc 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080002a0 <__do_global_dtors_aux>: 80002a0: b510 push {r4, lr} 80002a2: 4c05 ldr r4, [pc, #20] @ (80002b8 <__do_global_dtors_aux+0x18>) 80002a4: 7823 ldrb r3, [r4, #0] 80002a6: b933 cbnz r3, 80002b6 <__do_global_dtors_aux+0x16> 80002a8: 4b04 ldr r3, [pc, #16] @ (80002bc <__do_global_dtors_aux+0x1c>) 80002aa: b113 cbz r3, 80002b2 <__do_global_dtors_aux+0x12> 80002ac: 4804 ldr r0, [pc, #16] @ (80002c0 <__do_global_dtors_aux+0x20>) 80002ae: f3af 8000 nop.w 80002b2: 2301 movs r3, #1 80002b4: 7023 strb r3, [r4, #0] 80002b6: bd10 pop {r4, pc} 80002b8: 240000c0 .word 0x240000c0 80002bc: 00000000 .word 0x00000000 80002c0: 08017450 .word 0x08017450 080002c4 : 80002c4: b508 push {r3, lr} 80002c6: 4b03 ldr r3, [pc, #12] @ (80002d4 ) 80002c8: b11b cbz r3, 80002d2 80002ca: 4903 ldr r1, [pc, #12] @ (80002d8 ) 80002cc: 4803 ldr r0, [pc, #12] @ (80002dc ) 80002ce: f3af 8000 nop.w 80002d2: bd08 pop {r3, pc} 80002d4: 00000000 .word 0x00000000 80002d8: 240000c4 .word 0x240000c4 80002dc: 08017450 .word 0x08017450 080002e0 : 80002e0: f001 01ff and.w r1, r1, #255 @ 0xff 80002e4: 2a10 cmp r2, #16 80002e6: db2b blt.n 8000340 80002e8: f010 0f07 tst.w r0, #7 80002ec: d008 beq.n 8000300 80002ee: f810 3b01 ldrb.w r3, [r0], #1 80002f2: 3a01 subs r2, #1 80002f4: 428b cmp r3, r1 80002f6: d02d beq.n 8000354 80002f8: f010 0f07 tst.w r0, #7 80002fc: b342 cbz r2, 8000350 80002fe: d1f6 bne.n 80002ee 8000300: b4f0 push {r4, r5, r6, r7} 8000302: ea41 2101 orr.w r1, r1, r1, lsl #8 8000306: ea41 4101 orr.w r1, r1, r1, lsl #16 800030a: f022 0407 bic.w r4, r2, #7 800030e: f07f 0700 mvns.w r7, #0 8000312: 2300 movs r3, #0 8000314: e8f0 5602 ldrd r5, r6, [r0], #8 8000318: 3c08 subs r4, #8 800031a: ea85 0501 eor.w r5, r5, r1 800031e: ea86 0601 eor.w r6, r6, r1 8000322: fa85 f547 uadd8 r5, r5, r7 8000326: faa3 f587 sel r5, r3, r7 800032a: fa86 f647 uadd8 r6, r6, r7 800032e: faa5 f687 sel r6, r5, r7 8000332: b98e cbnz r6, 8000358 8000334: d1ee bne.n 8000314 8000336: bcf0 pop {r4, r5, r6, r7} 8000338: f001 01ff and.w r1, r1, #255 @ 0xff 800033c: f002 0207 and.w r2, r2, #7 8000340: b132 cbz r2, 8000350 8000342: f810 3b01 ldrb.w r3, [r0], #1 8000346: 3a01 subs r2, #1 8000348: ea83 0301 eor.w r3, r3, r1 800034c: b113 cbz r3, 8000354 800034e: d1f8 bne.n 8000342 8000350: 2000 movs r0, #0 8000352: 4770 bx lr 8000354: 3801 subs r0, #1 8000356: 4770 bx lr 8000358: 2d00 cmp r5, #0 800035a: bf06 itte eq 800035c: 4635 moveq r5, r6 800035e: 3803 subeq r0, #3 8000360: 3807 subne r0, #7 8000362: f015 0f01 tst.w r5, #1 8000366: d107 bne.n 8000378 8000368: 3001 adds r0, #1 800036a: f415 7f80 tst.w r5, #256 @ 0x100 800036e: bf02 ittt eq 8000370: 3001 addeq r0, #1 8000372: f415 3fc0 tsteq.w r5, #98304 @ 0x18000 8000376: 3001 addeq r0, #1 8000378: bcf0 pop {r4, r5, r6, r7} 800037a: 3801 subs r0, #1 800037c: 4770 bx lr 800037e: bf00 nop 08000380 <__aeabi_uldivmod>: 8000380: b953 cbnz r3, 8000398 <__aeabi_uldivmod+0x18> 8000382: b94a cbnz r2, 8000398 <__aeabi_uldivmod+0x18> 8000384: 2900 cmp r1, #0 8000386: bf08 it eq 8000388: 2800 cmpeq r0, #0 800038a: bf1c itt ne 800038c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8000390: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8000394: f000 b96a b.w 800066c <__aeabi_idiv0> 8000398: f1ad 0c08 sub.w ip, sp, #8 800039c: e96d ce04 strd ip, lr, [sp, #-16]! 80003a0: f000 f806 bl 80003b0 <__udivmoddi4> 80003a4: f8dd e004 ldr.w lr, [sp, #4] 80003a8: e9dd 2302 ldrd r2, r3, [sp, #8] 80003ac: b004 add sp, #16 80003ae: 4770 bx lr 080003b0 <__udivmoddi4>: 80003b0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80003b4: 9d08 ldr r5, [sp, #32] 80003b6: 460c mov r4, r1 80003b8: 2b00 cmp r3, #0 80003ba: d14e bne.n 800045a <__udivmoddi4+0xaa> 80003bc: 4694 mov ip, r2 80003be: 458c cmp ip, r1 80003c0: 4686 mov lr, r0 80003c2: fab2 f282 clz r2, r2 80003c6: d962 bls.n 800048e <__udivmoddi4+0xde> 80003c8: b14a cbz r2, 80003de <__udivmoddi4+0x2e> 80003ca: f1c2 0320 rsb r3, r2, #32 80003ce: 4091 lsls r1, r2 80003d0: fa20 f303 lsr.w r3, r0, r3 80003d4: fa0c fc02 lsl.w ip, ip, r2 80003d8: 4319 orrs r1, r3 80003da: fa00 fe02 lsl.w lr, r0, r2 80003de: ea4f 471c mov.w r7, ip, lsr #16 80003e2: fa1f f68c uxth.w r6, ip 80003e6: fbb1 f4f7 udiv r4, r1, r7 80003ea: ea4f 431e mov.w r3, lr, lsr #16 80003ee: fb07 1114 mls r1, r7, r4, r1 80003f2: ea43 4301 orr.w r3, r3, r1, lsl #16 80003f6: fb04 f106 mul.w r1, r4, r6 80003fa: 4299 cmp r1, r3 80003fc: d90a bls.n 8000414 <__udivmoddi4+0x64> 80003fe: eb1c 0303 adds.w r3, ip, r3 8000402: f104 30ff add.w r0, r4, #4294967295 @ 0xffffffff 8000406: f080 8112 bcs.w 800062e <__udivmoddi4+0x27e> 800040a: 4299 cmp r1, r3 800040c: f240 810f bls.w 800062e <__udivmoddi4+0x27e> 8000410: 3c02 subs r4, #2 8000412: 4463 add r3, ip 8000414: 1a59 subs r1, r3, r1 8000416: fa1f f38e uxth.w r3, lr 800041a: fbb1 f0f7 udiv r0, r1, r7 800041e: fb07 1110 mls r1, r7, r0, r1 8000422: ea43 4301 orr.w r3, r3, r1, lsl #16 8000426: fb00 f606 mul.w r6, r0, r6 800042a: 429e cmp r6, r3 800042c: d90a bls.n 8000444 <__udivmoddi4+0x94> 800042e: eb1c 0303 adds.w r3, ip, r3 8000432: f100 31ff add.w r1, r0, #4294967295 @ 0xffffffff 8000436: f080 80fc bcs.w 8000632 <__udivmoddi4+0x282> 800043a: 429e cmp r6, r3 800043c: f240 80f9 bls.w 8000632 <__udivmoddi4+0x282> 8000440: 4463 add r3, ip 8000442: 3802 subs r0, #2 8000444: 1b9b subs r3, r3, r6 8000446: ea40 4004 orr.w r0, r0, r4, lsl #16 800044a: 2100 movs r1, #0 800044c: b11d cbz r5, 8000456 <__udivmoddi4+0xa6> 800044e: 40d3 lsrs r3, r2 8000450: 2200 movs r2, #0 8000452: e9c5 3200 strd r3, r2, [r5] 8000456: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800045a: 428b cmp r3, r1 800045c: d905 bls.n 800046a <__udivmoddi4+0xba> 800045e: b10d cbz r5, 8000464 <__udivmoddi4+0xb4> 8000460: e9c5 0100 strd r0, r1, [r5] 8000464: 2100 movs r1, #0 8000466: 4608 mov r0, r1 8000468: e7f5 b.n 8000456 <__udivmoddi4+0xa6> 800046a: fab3 f183 clz r1, r3 800046e: 2900 cmp r1, #0 8000470: d146 bne.n 8000500 <__udivmoddi4+0x150> 8000472: 42a3 cmp r3, r4 8000474: d302 bcc.n 800047c <__udivmoddi4+0xcc> 8000476: 4290 cmp r0, r2 8000478: f0c0 80f0 bcc.w 800065c <__udivmoddi4+0x2ac> 800047c: 1a86 subs r6, r0, r2 800047e: eb64 0303 sbc.w r3, r4, r3 8000482: 2001 movs r0, #1 8000484: 2d00 cmp r5, #0 8000486: d0e6 beq.n 8000456 <__udivmoddi4+0xa6> 8000488: e9c5 6300 strd r6, r3, [r5] 800048c: e7e3 b.n 8000456 <__udivmoddi4+0xa6> 800048e: 2a00 cmp r2, #0 8000490: f040 8090 bne.w 80005b4 <__udivmoddi4+0x204> 8000494: eba1 040c sub.w r4, r1, ip 8000498: ea4f 481c mov.w r8, ip, lsr #16 800049c: fa1f f78c uxth.w r7, ip 80004a0: 2101 movs r1, #1 80004a2: fbb4 f6f8 udiv r6, r4, r8 80004a6: ea4f 431e mov.w r3, lr, lsr #16 80004aa: fb08 4416 mls r4, r8, r6, r4 80004ae: ea43 4304 orr.w r3, r3, r4, lsl #16 80004b2: fb07 f006 mul.w r0, r7, r6 80004b6: 4298 cmp r0, r3 80004b8: d908 bls.n 80004cc <__udivmoddi4+0x11c> 80004ba: eb1c 0303 adds.w r3, ip, r3 80004be: f106 34ff add.w r4, r6, #4294967295 @ 0xffffffff 80004c2: d202 bcs.n 80004ca <__udivmoddi4+0x11a> 80004c4: 4298 cmp r0, r3 80004c6: f200 80cd bhi.w 8000664 <__udivmoddi4+0x2b4> 80004ca: 4626 mov r6, r4 80004cc: 1a1c subs r4, r3, r0 80004ce: fa1f f38e uxth.w r3, lr 80004d2: fbb4 f0f8 udiv r0, r4, r8 80004d6: fb08 4410 mls r4, r8, r0, r4 80004da: ea43 4304 orr.w r3, r3, r4, lsl #16 80004de: fb00 f707 mul.w r7, r0, r7 80004e2: 429f cmp r7, r3 80004e4: d908 bls.n 80004f8 <__udivmoddi4+0x148> 80004e6: eb1c 0303 adds.w r3, ip, r3 80004ea: f100 34ff add.w r4, r0, #4294967295 @ 0xffffffff 80004ee: d202 bcs.n 80004f6 <__udivmoddi4+0x146> 80004f0: 429f cmp r7, r3 80004f2: f200 80b0 bhi.w 8000656 <__udivmoddi4+0x2a6> 80004f6: 4620 mov r0, r4 80004f8: 1bdb subs r3, r3, r7 80004fa: ea40 4006 orr.w r0, r0, r6, lsl #16 80004fe: e7a5 b.n 800044c <__udivmoddi4+0x9c> 8000500: f1c1 0620 rsb r6, r1, #32 8000504: 408b lsls r3, r1 8000506: fa22 f706 lsr.w r7, r2, r6 800050a: 431f orrs r7, r3 800050c: fa20 fc06 lsr.w ip, r0, r6 8000510: fa04 f301 lsl.w r3, r4, r1 8000514: ea43 030c orr.w r3, r3, ip 8000518: 40f4 lsrs r4, r6 800051a: fa00 f801 lsl.w r8, r0, r1 800051e: 0c38 lsrs r0, r7, #16 8000520: ea4f 4913 mov.w r9, r3, lsr #16 8000524: fbb4 fef0 udiv lr, r4, r0 8000528: fa1f fc87 uxth.w ip, r7 800052c: fb00 441e mls r4, r0, lr, r4 8000530: ea49 4404 orr.w r4, r9, r4, lsl #16 8000534: fb0e f90c mul.w r9, lr, ip 8000538: 45a1 cmp r9, r4 800053a: fa02 f201 lsl.w r2, r2, r1 800053e: d90a bls.n 8000556 <__udivmoddi4+0x1a6> 8000540: 193c adds r4, r7, r4 8000542: f10e 3aff add.w sl, lr, #4294967295 @ 0xffffffff 8000546: f080 8084 bcs.w 8000652 <__udivmoddi4+0x2a2> 800054a: 45a1 cmp r9, r4 800054c: f240 8081 bls.w 8000652 <__udivmoddi4+0x2a2> 8000550: f1ae 0e02 sub.w lr, lr, #2 8000554: 443c add r4, r7 8000556: eba4 0409 sub.w r4, r4, r9 800055a: fa1f f983 uxth.w r9, r3 800055e: fbb4 f3f0 udiv r3, r4, r0 8000562: fb00 4413 mls r4, r0, r3, r4 8000566: ea49 4404 orr.w r4, r9, r4, lsl #16 800056a: fb03 fc0c mul.w ip, r3, ip 800056e: 45a4 cmp ip, r4 8000570: d907 bls.n 8000582 <__udivmoddi4+0x1d2> 8000572: 193c adds r4, r7, r4 8000574: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 8000578: d267 bcs.n 800064a <__udivmoddi4+0x29a> 800057a: 45a4 cmp ip, r4 800057c: d965 bls.n 800064a <__udivmoddi4+0x29a> 800057e: 3b02 subs r3, #2 8000580: 443c add r4, r7 8000582: ea43 400e orr.w r0, r3, lr, lsl #16 8000586: fba0 9302 umull r9, r3, r0, r2 800058a: eba4 040c sub.w r4, r4, ip 800058e: 429c cmp r4, r3 8000590: 46ce mov lr, r9 8000592: 469c mov ip, r3 8000594: d351 bcc.n 800063a <__udivmoddi4+0x28a> 8000596: d04e beq.n 8000636 <__udivmoddi4+0x286> 8000598: b155 cbz r5, 80005b0 <__udivmoddi4+0x200> 800059a: ebb8 030e subs.w r3, r8, lr 800059e: eb64 040c sbc.w r4, r4, ip 80005a2: fa04 f606 lsl.w r6, r4, r6 80005a6: 40cb lsrs r3, r1 80005a8: 431e orrs r6, r3 80005aa: 40cc lsrs r4, r1 80005ac: e9c5 6400 strd r6, r4, [r5] 80005b0: 2100 movs r1, #0 80005b2: e750 b.n 8000456 <__udivmoddi4+0xa6> 80005b4: f1c2 0320 rsb r3, r2, #32 80005b8: fa20 f103 lsr.w r1, r0, r3 80005bc: fa0c fc02 lsl.w ip, ip, r2 80005c0: fa24 f303 lsr.w r3, r4, r3 80005c4: 4094 lsls r4, r2 80005c6: 430c orrs r4, r1 80005c8: ea4f 481c mov.w r8, ip, lsr #16 80005cc: fa00 fe02 lsl.w lr, r0, r2 80005d0: fa1f f78c uxth.w r7, ip 80005d4: fbb3 f0f8 udiv r0, r3, r8 80005d8: fb08 3110 mls r1, r8, r0, r3 80005dc: 0c23 lsrs r3, r4, #16 80005de: ea43 4301 orr.w r3, r3, r1, lsl #16 80005e2: fb00 f107 mul.w r1, r0, r7 80005e6: 4299 cmp r1, r3 80005e8: d908 bls.n 80005fc <__udivmoddi4+0x24c> 80005ea: eb1c 0303 adds.w r3, ip, r3 80005ee: f100 36ff add.w r6, r0, #4294967295 @ 0xffffffff 80005f2: d22c bcs.n 800064e <__udivmoddi4+0x29e> 80005f4: 4299 cmp r1, r3 80005f6: d92a bls.n 800064e <__udivmoddi4+0x29e> 80005f8: 3802 subs r0, #2 80005fa: 4463 add r3, ip 80005fc: 1a5b subs r3, r3, r1 80005fe: b2a4 uxth r4, r4 8000600: fbb3 f1f8 udiv r1, r3, r8 8000604: fb08 3311 mls r3, r8, r1, r3 8000608: ea44 4403 orr.w r4, r4, r3, lsl #16 800060c: fb01 f307 mul.w r3, r1, r7 8000610: 42a3 cmp r3, r4 8000612: d908 bls.n 8000626 <__udivmoddi4+0x276> 8000614: eb1c 0404 adds.w r4, ip, r4 8000618: f101 36ff add.w r6, r1, #4294967295 @ 0xffffffff 800061c: d213 bcs.n 8000646 <__udivmoddi4+0x296> 800061e: 42a3 cmp r3, r4 8000620: d911 bls.n 8000646 <__udivmoddi4+0x296> 8000622: 3902 subs r1, #2 8000624: 4464 add r4, ip 8000626: 1ae4 subs r4, r4, r3 8000628: ea41 4100 orr.w r1, r1, r0, lsl #16 800062c: e739 b.n 80004a2 <__udivmoddi4+0xf2> 800062e: 4604 mov r4, r0 8000630: e6f0 b.n 8000414 <__udivmoddi4+0x64> 8000632: 4608 mov r0, r1 8000634: e706 b.n 8000444 <__udivmoddi4+0x94> 8000636: 45c8 cmp r8, r9 8000638: d2ae bcs.n 8000598 <__udivmoddi4+0x1e8> 800063a: ebb9 0e02 subs.w lr, r9, r2 800063e: eb63 0c07 sbc.w ip, r3, r7 8000642: 3801 subs r0, #1 8000644: e7a8 b.n 8000598 <__udivmoddi4+0x1e8> 8000646: 4631 mov r1, r6 8000648: e7ed b.n 8000626 <__udivmoddi4+0x276> 800064a: 4603 mov r3, r0 800064c: e799 b.n 8000582 <__udivmoddi4+0x1d2> 800064e: 4630 mov r0, r6 8000650: e7d4 b.n 80005fc <__udivmoddi4+0x24c> 8000652: 46d6 mov lr, sl 8000654: e77f b.n 8000556 <__udivmoddi4+0x1a6> 8000656: 4463 add r3, ip 8000658: 3802 subs r0, #2 800065a: e74d b.n 80004f8 <__udivmoddi4+0x148> 800065c: 4606 mov r6, r0 800065e: 4623 mov r3, r4 8000660: 4608 mov r0, r1 8000662: e70f b.n 8000484 <__udivmoddi4+0xd4> 8000664: 3e02 subs r6, #2 8000666: 4463 add r3, ip 8000668: e730 b.n 80004cc <__udivmoddi4+0x11c> 800066a: bf00 nop 0800066c <__aeabi_idiv0>: 800066c: 4770 bx lr 800066e: bf00 nop 08000670 : /* Hook prototypes */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName); /* USER CODE BEGIN 4 */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName) { 8000670: b480 push {r7} 8000672: b083 sub sp, #12 8000674: af00 add r7, sp, #0 8000676: 6078 str r0, [r7, #4] 8000678: 6039 str r1, [r7, #0] /* Run time stack overflow checking is performed if configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is called if a stack overflow is detected. */ } 800067a: bf00 nop 800067c: 370c adds r7, #12 800067e: 46bd mov sp, r7 8000680: f85d 7b04 ldr.w r7, [sp], #4 8000684: 4770 bx lr ... 08000688 <__io_putchar>: /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ int __io_putchar(int ch) { 8000688: b580 push {r7, lr} 800068a: b082 sub sp, #8 800068c: af00 add r7, sp, #0 800068e: 6078 str r0, [r7, #4] HAL_UART_Transmit(&huart8, (uint8_t *)&ch, 1, 0xFFFF); // Use UART8 as debug interface 8000690: 1d39 adds r1, r7, #4 8000692: f64f 73ff movw r3, #65535 @ 0xffff 8000696: 2201 movs r2, #1 8000698: 4803 ldr r0, [pc, #12] @ (80006a8 <__io_putchar+0x20>) 800069a: f00e ff61 bl 800f560 // ITM_SendChar(ch); // Use SWV as debug interface return ch; 800069e: 687b ldr r3, [r7, #4] } 80006a0: 4618 mov r0, r3 80006a2: 3708 adds r7, #8 80006a4: 46bd mov sp, r7 80006a6: bd80 pop {r7, pc} 80006a8: 24000504 .word 0x24000504 080006ac : void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 80006ac: b580 push {r7, lr} 80006ae: b084 sub sp, #16 80006b0: af00 add r7, sp, #0 80006b2: 4603 mov r3, r0 80006b4: 80fb strh r3, [r7, #6] LimiterSwitchData limiterSwitchData = { 0 }; 80006b6: 2300 movs r3, #0 80006b8: 60fb str r3, [r7, #12] limiterSwitchData.gpioPin = GPIO_Pin; 80006ba: 88fb ldrh r3, [r7, #6] 80006bc: 81bb strh r3, [r7, #12] limiterSwitchData.pinState = HAL_GPIO_ReadPin(GPIOD, GPIO_Pin); 80006be: 88fb ldrh r3, [r7, #6] 80006c0: 4619 mov r1, r3 80006c2: 4808 ldr r0, [pc, #32] @ (80006e4 ) 80006c4: f009 fbc4 bl 8009e50 80006c8: 4603 mov r3, r0 80006ca: 73bb strb r3, [r7, #14] osMessageQueuePut(limiterSwitchDataQueue, &limiterSwitchData, 0, 0); 80006cc: 4b06 ldr r3, [pc, #24] @ (80006e8 ) 80006ce: 6818 ldr r0, [r3, #0] 80006d0: f107 010c add.w r1, r7, #12 80006d4: 2300 movs r3, #0 80006d6: 2200 movs r2, #0 80006d8: f012 f8f8 bl 80128cc } 80006dc: bf00 nop 80006de: 3710 adds r7, #16 80006e0: 46bd mov sp, r7 80006e2: bd80 pop {r7, pc} 80006e4: 58020c00 .word 0x58020c00 80006e8: 24000744 .word 0x24000744 080006ec
: /** * @brief The application entry point. * @retval int */ int main(void) { 80006ec: b580 push {r7, lr} 80006ee: b084 sub sp, #16 80006f0: af00 add r7, sp, #0 /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MPU Configuration--------------------------------------------------------*/ MPU_Config(); 80006f2: f001 f931 bl 8001958 \details Turns on I-Cache */ __STATIC_FORCEINLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 80006f6: 4b5c ldr r3, [pc, #368] @ (8000868 ) 80006f8: 695b ldr r3, [r3, #20] 80006fa: f403 3300 and.w r3, r3, #131072 @ 0x20000 80006fe: 2b00 cmp r3, #0 8000700: d11b bne.n 800073a \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 8000702: f3bf 8f4f dsb sy } 8000706: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000708: f3bf 8f6f isb sy } 800070c: bf00 nop __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 800070e: 4b56 ldr r3, [pc, #344] @ (8000868 ) 8000710: 2200 movs r2, #0 8000712: f8c3 2250 str.w r2, [r3, #592] @ 0x250 __ASM volatile ("dsb 0xF":::"memory"); 8000716: f3bf 8f4f dsb sy } 800071a: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 800071c: f3bf 8f6f isb sy } 8000720: bf00 nop __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 8000722: 4b51 ldr r3, [pc, #324] @ (8000868 ) 8000724: 695b ldr r3, [r3, #20] 8000726: 4a50 ldr r2, [pc, #320] @ (8000868 ) 8000728: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800072c: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 800072e: f3bf 8f4f dsb sy } 8000732: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000734: f3bf 8f6f isb sy } 8000738: e000 b.n 800073c if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 800073a: bf00 nop #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 800073c: 4b4a ldr r3, [pc, #296] @ (8000868 ) 800073e: 695b ldr r3, [r3, #20] 8000740: f403 3380 and.w r3, r3, #65536 @ 0x10000 8000744: 2b00 cmp r3, #0 8000746: d138 bne.n 80007ba SCB->CSSELR = 0U; /* select Level 1 data cache */ 8000748: 4b47 ldr r3, [pc, #284] @ (8000868 ) 800074a: 2200 movs r2, #0 800074c: f8c3 2084 str.w r2, [r3, #132] @ 0x84 __ASM volatile ("dsb 0xF":::"memory"); 8000750: f3bf 8f4f dsb sy } 8000754: bf00 nop __DSB(); ccsidr = SCB->CCSIDR; 8000756: 4b44 ldr r3, [pc, #272] @ (8000868 ) 8000758: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800075c: 60fb str r3, [r7, #12] /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 800075e: 68fb ldr r3, [r7, #12] 8000760: 0b5b lsrs r3, r3, #13 8000762: f3c3 030e ubfx r3, r3, #0, #15 8000766: 60bb str r3, [r7, #8] do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 8000768: 68fb ldr r3, [r7, #12] 800076a: 08db lsrs r3, r3, #3 800076c: f3c3 0309 ubfx r3, r3, #0, #10 8000770: 607b str r3, [r7, #4] do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 8000772: 68bb ldr r3, [r7, #8] 8000774: 015a lsls r2, r3, #5 8000776: f643 73e0 movw r3, #16352 @ 0x3fe0 800077a: 4013 ands r3, r2 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 800077c: 687a ldr r2, [r7, #4] 800077e: 0792 lsls r2, r2, #30 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 8000780: 4939 ldr r1, [pc, #228] @ (8000868 ) 8000782: 4313 orrs r3, r2 8000784: f8c1 3260 str.w r3, [r1, #608] @ 0x260 #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); 8000788: 687b ldr r3, [r7, #4] 800078a: 1e5a subs r2, r3, #1 800078c: 607a str r2, [r7, #4] 800078e: 2b00 cmp r3, #0 8000790: d1ef bne.n 8000772 } while(sets-- != 0U); 8000792: 68bb ldr r3, [r7, #8] 8000794: 1e5a subs r2, r3, #1 8000796: 60ba str r2, [r7, #8] 8000798: 2b00 cmp r3, #0 800079a: d1e5 bne.n 8000768 __ASM volatile ("dsb 0xF":::"memory"); 800079c: f3bf 8f4f dsb sy } 80007a0: bf00 nop __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 80007a2: 4b31 ldr r3, [pc, #196] @ (8000868 ) 80007a4: 695b ldr r3, [r3, #20] 80007a6: 4a30 ldr r2, [pc, #192] @ (8000868 ) 80007a8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80007ac: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 80007ae: f3bf 8f4f dsb sy } 80007b2: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80007b4: f3bf 8f6f isb sy } 80007b8: e000 b.n 80007bc if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 80007ba: bf00 nop SCB_EnableDCache(); /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80007bc: f004 f902 bl 80049c4 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80007c0: f000 f872 bl 80008a8 /* Configure the peripherals common clocks */ PeriphCommonClock_Config(); 80007c4: f000 f8ec bl 80009a0 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80007c8: f000 fe28 bl 800141c MX_DMA_Init(); 80007cc: f000 fdf6 bl 80013bc MX_RNG_Init(); 80007d0: f000 fbaa bl 8000f28 MX_USART1_UART_Init(); 80007d4: f000 fda2 bl 800131c MX_ADC1_Init(); 80007d8: f000 f912 bl 8000a00 MX_UART8_Init(); 80007dc: f000 fd52 bl 8001284 MX_CRC_Init(); 80007e0: f000 fb3c bl 8000e5c MX_ADC2_Init(); 80007e4: f000 f9f6 bl 8000bd4 MX_ADC3_Init(); 80007e8: f000 fa88 bl 8000cfc MX_TIM2_Init(); 80007ec: f000 fc4e bl 800108c MX_TIM1_Init(); 80007f0: f000 fbb0 bl 8000f54 MX_TIM3_Init(); 80007f4: f000 fc9a bl 800112c MX_DAC1_Init(); 80007f8: f000 fb5a bl 8000eb0 /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ /* Init scheduler */ osKernelInitialize(); 80007fc: f011 fcf6 bl 80121ec /* add semaphores, ... */ /* USER CODE END RTOS_SEMAPHORES */ /* Create the timer(s) */ /* creation of debugLedTimer */ debugLedTimerHandle = osTimerNew(debugLedTimerCallback, osTimerOnce, NULL, &debugLedTimer_attributes); 8000800: 4b1a ldr r3, [pc, #104] @ (800086c ) 8000802: 2200 movs r2, #0 8000804: 2100 movs r1, #0 8000806: 481a ldr r0, [pc, #104] @ (8000870 ) 8000808: f011 fdfe bl 8012408 800080c: 4603 mov r3, r0 800080e: 4a19 ldr r2, [pc, #100] @ (8000874 ) 8000810: 6013 str r3, [r2, #0] /* creation of fanTimer */ fanTimerHandle = osTimerNew(fanTimerCallback, osTimerOnce, NULL, &fanTimer_attributes); 8000812: 4b19 ldr r3, [pc, #100] @ (8000878 ) 8000814: 2200 movs r2, #0 8000816: 2100 movs r1, #0 8000818: 4818 ldr r0, [pc, #96] @ (800087c ) 800081a: f011 fdf5 bl 8012408 800081e: 4603 mov r3, r0 8000820: 4a17 ldr r2, [pc, #92] @ (8000880 ) 8000822: 6013 str r3, [r2, #0] /* creation of motorXTimer */ motorXTimerHandle = osTimerNew(motorXTimerCallback, osTimerPeriodic, NULL, &motorXTimer_attributes); 8000824: 4b17 ldr r3, [pc, #92] @ (8000884 ) 8000826: 2200 movs r2, #0 8000828: 2101 movs r1, #1 800082a: 4817 ldr r0, [pc, #92] @ (8000888 ) 800082c: f011 fdec bl 8012408 8000830: 4603 mov r3, r0 8000832: 4a16 ldr r2, [pc, #88] @ (800088c ) 8000834: 6013 str r3, [r2, #0] /* creation of motorYTimer */ motorYTimerHandle = osTimerNew(motorYTimerCallback, osTimerPeriodic, NULL, &motorYTimer_attributes); 8000836: 4b16 ldr r3, [pc, #88] @ (8000890 ) 8000838: 2200 movs r2, #0 800083a: 2101 movs r1, #1 800083c: 4815 ldr r0, [pc, #84] @ (8000894 ) 800083e: f011 fde3 bl 8012408 8000842: 4603 mov r3, r0 8000844: 4a14 ldr r2, [pc, #80] @ (8000898 ) 8000846: 6013 str r3, [r2, #0] /* add queues, ... */ /* USER CODE END RTOS_QUEUES */ /* Create the thread(s) */ /* creation of defaultTask */ defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); 8000848: 4a14 ldr r2, [pc, #80] @ (800089c ) 800084a: 2100 movs r1, #0 800084c: 4814 ldr r0, [pc, #80] @ (80008a0 ) 800084e: f011 fd17 bl 8012280 8000852: 4603 mov r3, r0 8000854: 4a13 ldr r2, [pc, #76] @ (80008a4 ) 8000856: 6013 str r3, [r2, #0] /* USER CODE BEGIN RTOS_THREADS */ /* add threads, ... */ // Uart8TasksInit(); UartTasksInit(); 8000858: f003 f96e bl 8003b38 #ifdef USER_MOCKS MockMeasurmetsTaskInit(); #else MeasTasksInit(); 800085c: f001 f8e6 bl 8001a2c /* USER CODE BEGIN RTOS_EVENTS */ /* add events, ... */ /* USER CODE END RTOS_EVENTS */ /* Start scheduler */ osKernelStart(); 8000860: f011 fce8 bl 8012234 /* We should never get here as control is now taken by the scheduler */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8000864: bf00 nop 8000866: e7fd b.n 8000864 8000868: e000ed00 .word 0xe000ed00 800086c: 08017588 .word 0x08017588 8000870: 080018ad .word 0x080018ad 8000874: 24000630 .word 0x24000630 8000878: 08017598 .word 0x08017598 800087c: 080018c5 .word 0x080018c5 8000880: 24000660 .word 0x24000660 8000884: 080175a8 .word 0x080175a8 8000888: 080018e1 .word 0x080018e1 800088c: 24000690 .word 0x24000690 8000890: 080175b8 .word 0x080175b8 8000894: 0800191d .word 0x0800191d 8000898: 240006c0 .word 0x240006c0 800089c: 08017564 .word 0x08017564 80008a0: 08001785 .word 0x08001785 80008a4: 2400062c .word 0x2400062c 080008a8 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80008a8: b580 push {r7, lr} 80008aa: b09c sub sp, #112 @ 0x70 80008ac: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80008ae: f107 0324 add.w r3, r7, #36 @ 0x24 80008b2: 224c movs r2, #76 @ 0x4c 80008b4: 2100 movs r1, #0 80008b6: 4618 mov r0, r3 80008b8: f015 ff4d bl 8016756 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 80008bc: 1d3b adds r3, r7, #4 80008be: 2220 movs r2, #32 80008c0: 2100 movs r1, #0 80008c2: 4618 mov r0, r3 80008c4: f015 ff47 bl 8016756 /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 80008c8: 2002 movs r0, #2 80008ca: f009 fbb1 bl 800a030 /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 80008ce: 2300 movs r3, #0 80008d0: 603b str r3, [r7, #0] 80008d2: 4b31 ldr r3, [pc, #196] @ (8000998 ) 80008d4: 6adb ldr r3, [r3, #44] @ 0x2c 80008d6: 4a30 ldr r2, [pc, #192] @ (8000998 ) 80008d8: f023 0301 bic.w r3, r3, #1 80008dc: 62d3 str r3, [r2, #44] @ 0x2c 80008de: 4b2e ldr r3, [pc, #184] @ (8000998 ) 80008e0: 6adb ldr r3, [r3, #44] @ 0x2c 80008e2: f003 0301 and.w r3, r3, #1 80008e6: 603b str r3, [r7, #0] 80008e8: 4b2c ldr r3, [pc, #176] @ (800099c ) 80008ea: 699b ldr r3, [r3, #24] 80008ec: 4a2b ldr r2, [pc, #172] @ (800099c ) 80008ee: f443 4340 orr.w r3, r3, #49152 @ 0xc000 80008f2: 6193 str r3, [r2, #24] 80008f4: 4b29 ldr r3, [pc, #164] @ (800099c ) 80008f6: 699b ldr r3, [r3, #24] 80008f8: f403 4340 and.w r3, r3, #49152 @ 0xc000 80008fc: 603b str r3, [r7, #0] 80008fe: 683b ldr r3, [r7, #0] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 8000900: bf00 nop 8000902: 4b26 ldr r3, [pc, #152] @ (800099c ) 8000904: 699b ldr r3, [r3, #24] 8000906: f403 5300 and.w r3, r3, #8192 @ 0x2000 800090a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800090e: d1f8 bne.n 8000902 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE; 8000910: 2321 movs r3, #33 @ 0x21 8000912: 627b str r3, [r7, #36] @ 0x24 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000914: f44f 3380 mov.w r3, #65536 @ 0x10000 8000918: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; 800091a: 2301 movs r3, #1 800091c: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800091e: 2302 movs r3, #2 8000920: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000922: 2302 movs r3, #2 8000924: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.PLL.PLLM = 5; 8000926: 2305 movs r3, #5 8000928: 653b str r3, [r7, #80] @ 0x50 RCC_OscInitStruct.PLL.PLLN = 160; 800092a: 23a0 movs r3, #160 @ 0xa0 800092c: 657b str r3, [r7, #84] @ 0x54 RCC_OscInitStruct.PLL.PLLP = 2; 800092e: 2302 movs r3, #2 8000930: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLQ = 2; 8000932: 2302 movs r3, #2 8000934: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLR = 2; 8000936: 2302 movs r3, #2 8000938: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 800093a: 2308 movs r3, #8 800093c: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 800093e: 2300 movs r3, #0 8000940: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL.PLLFRACN = 0; 8000942: 2300 movs r3, #0 8000944: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000946: f107 0324 add.w r3, r7, #36 @ 0x24 800094a: 4618 mov r0, r3 800094c: f009 fc30 bl 800a1b0 8000950: 4603 mov r3, r0 8000952: 2b00 cmp r3, #0 8000954: d001 beq.n 800095a { Error_Handler(); 8000956: f001 f863 bl 8001a20 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800095a: 233f movs r3, #63 @ 0x3f 800095c: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800095e: 2303 movs r3, #3 8000960: 60bb str r3, [r7, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 8000962: 2300 movs r3, #0 8000964: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 8000966: 2308 movs r3, #8 8000968: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 800096a: 2340 movs r3, #64 @ 0x40 800096c: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 800096e: 2340 movs r3, #64 @ 0x40 8000970: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 8000972: f44f 6380 mov.w r3, #1024 @ 0x400 8000976: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 8000978: 2340 movs r3, #64 @ 0x40 800097a: 623b str r3, [r7, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800097c: 1d3b adds r3, r7, #4 800097e: 2102 movs r1, #2 8000980: 4618 mov r0, r3 8000982: f00a f86f bl 800aa64 8000986: 4603 mov r3, r0 8000988: 2b00 cmp r3, #0 800098a: d001 beq.n 8000990 { Error_Handler(); 800098c: f001 f848 bl 8001a20 } } 8000990: bf00 nop 8000992: 3770 adds r7, #112 @ 0x70 8000994: 46bd mov sp, r7 8000996: bd80 pop {r7, pc} 8000998: 58000400 .word 0x58000400 800099c: 58024800 .word 0x58024800 080009a0 : /** * @brief Peripherals Common Clock Configuration * @retval None */ void PeriphCommonClock_Config(void) { 80009a0: b580 push {r7, lr} 80009a2: b0b0 sub sp, #192 @ 0xc0 80009a4: af00 add r7, sp, #0 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 80009a6: 463b mov r3, r7 80009a8: 22c0 movs r2, #192 @ 0xc0 80009aa: 2100 movs r1, #0 80009ac: 4618 mov r0, r3 80009ae: f015 fed2 bl 8016756 /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC; 80009b2: f44f 2200 mov.w r2, #524288 @ 0x80000 80009b6: f04f 0300 mov.w r3, #0 80009ba: e9c7 2300 strd r2, r3, [r7] PeriphClkInitStruct.PLL2.PLL2M = 5; 80009be: 2305 movs r3, #5 80009c0: 60bb str r3, [r7, #8] PeriphClkInitStruct.PLL2.PLL2N = 52; 80009c2: 2334 movs r3, #52 @ 0x34 80009c4: 60fb str r3, [r7, #12] PeriphClkInitStruct.PLL2.PLL2P = 26; 80009c6: 231a movs r3, #26 80009c8: 613b str r3, [r7, #16] PeriphClkInitStruct.PLL2.PLL2Q = 2; 80009ca: 2302 movs r3, #2 80009cc: 617b str r3, [r7, #20] PeriphClkInitStruct.PLL2.PLL2R = 2; 80009ce: 2302 movs r3, #2 80009d0: 61bb str r3, [r7, #24] PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2; 80009d2: 2380 movs r3, #128 @ 0x80 80009d4: 61fb str r3, [r7, #28] PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; 80009d6: 2300 movs r3, #0 80009d8: 623b str r3, [r7, #32] PeriphClkInitStruct.PLL2.PLL2FRACN = 0; 80009da: 2300 movs r3, #0 80009dc: 627b str r3, [r7, #36] @ 0x24 PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; 80009de: 2300 movs r3, #0 80009e0: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80009e4: 463b mov r3, r7 80009e6: 4618 mov r0, r3 80009e8: f00a fc0a bl 800b200 80009ec: 4603 mov r3, r0 80009ee: 2b00 cmp r3, #0 80009f0: d001 beq.n 80009f6 { Error_Handler(); 80009f2: f001 f815 bl 8001a20 } } 80009f6: bf00 nop 80009f8: 37c0 adds r7, #192 @ 0xc0 80009fa: 46bd mov sp, r7 80009fc: bd80 pop {r7, pc} ... 08000a00 : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 8000a00: b580 push {r7, lr} 8000a02: b08a sub sp, #40 @ 0x28 8000a04: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_MultiModeTypeDef multimode = {0}; 8000a06: f107 031c add.w r3, r7, #28 8000a0a: 2200 movs r2, #0 8000a0c: 601a str r2, [r3, #0] 8000a0e: 605a str r2, [r3, #4] 8000a10: 609a str r2, [r3, #8] ADC_ChannelConfTypeDef sConfig = {0}; 8000a12: 463b mov r3, r7 8000a14: 2200 movs r2, #0 8000a16: 601a str r2, [r3, #0] 8000a18: 605a str r2, [r3, #4] 8000a1a: 609a str r2, [r3, #8] 8000a1c: 60da str r2, [r3, #12] 8000a1e: 611a str r2, [r3, #16] 8000a20: 615a str r2, [r3, #20] 8000a22: 619a str r2, [r3, #24] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 8000a24: 4b62 ldr r3, [pc, #392] @ (8000bb0 ) 8000a26: 4a63 ldr r2, [pc, #396] @ (8000bb4 ) 8000a28: 601a str r2, [r3, #0] hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 8000a2a: 4b61 ldr r3, [pc, #388] @ (8000bb0 ) 8000a2c: 2200 movs r2, #0 8000a2e: 605a str r2, [r3, #4] hadc1.Init.Resolution = ADC_RESOLUTION_16B; 8000a30: 4b5f ldr r3, [pc, #380] @ (8000bb0 ) 8000a32: 2200 movs r2, #0 8000a34: 609a str r2, [r3, #8] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000a36: 4b5e ldr r3, [pc, #376] @ (8000bb0 ) 8000a38: 2201 movs r2, #1 8000a3a: 60da str r2, [r3, #12] hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000a3c: 4b5c ldr r3, [pc, #368] @ (8000bb0 ) 8000a3e: 2208 movs r2, #8 8000a40: 611a str r2, [r3, #16] hadc1.Init.LowPowerAutoWait = DISABLE; 8000a42: 4b5b ldr r3, [pc, #364] @ (8000bb0 ) 8000a44: 2200 movs r2, #0 8000a46: 751a strb r2, [r3, #20] hadc1.Init.ContinuousConvMode = ENABLE; 8000a48: 4b59 ldr r3, [pc, #356] @ (8000bb0 ) 8000a4a: 2201 movs r2, #1 8000a4c: 755a strb r2, [r3, #21] hadc1.Init.NbrOfConversion = 7; 8000a4e: 4b58 ldr r3, [pc, #352] @ (8000bb0 ) 8000a50: 2207 movs r2, #7 8000a52: 619a str r2, [r3, #24] hadc1.Init.DiscontinuousConvMode = DISABLE; 8000a54: 4b56 ldr r3, [pc, #344] @ (8000bb0 ) 8000a56: 2200 movs r2, #0 8000a58: 771a strb r2, [r3, #28] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO; 8000a5a: 4b55 ldr r3, [pc, #340] @ (8000bb0 ) 8000a5c: f44f 62ac mov.w r2, #1376 @ 0x560 8000a60: 625a str r2, [r3, #36] @ 0x24 hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000a62: 4b53 ldr r3, [pc, #332] @ (8000bb0 ) 8000a64: f44f 6280 mov.w r2, #1024 @ 0x400 8000a68: 629a str r2, [r3, #40] @ 0x28 hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000a6a: 4b51 ldr r3, [pc, #324] @ (8000bb0 ) 8000a6c: 2201 movs r2, #1 8000a6e: 62da str r2, [r3, #44] @ 0x2c hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000a70: 4b4f ldr r3, [pc, #316] @ (8000bb0 ) 8000a72: 2200 movs r2, #0 8000a74: 631a str r2, [r3, #48] @ 0x30 hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000a76: 4b4e ldr r3, [pc, #312] @ (8000bb0 ) 8000a78: 2200 movs r2, #0 8000a7a: 635a str r2, [r3, #52] @ 0x34 hadc1.Init.OversamplingMode = DISABLE; 8000a7c: 4b4c ldr r3, [pc, #304] @ (8000bb0 ) 8000a7e: 2200 movs r2, #0 8000a80: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc1) != HAL_OK) 8000a84: 484a ldr r0, [pc, #296] @ (8000bb0 ) 8000a86: f004 fa4d bl 8004f24 8000a8a: 4603 mov r3, r0 8000a8c: 2b00 cmp r3, #0 8000a8e: d001 beq.n 8000a94 { Error_Handler(); 8000a90: f000 ffc6 bl 8001a20 } /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; 8000a94: 2300 movs r3, #0 8000a96: 61fb str r3, [r7, #28] if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 8000a98: f107 031c add.w r3, r7, #28 8000a9c: 4619 mov r1, r3 8000a9e: 4844 ldr r0, [pc, #272] @ (8000bb0 ) 8000aa0: f005 fb5e bl 8006160 8000aa4: 4603 mov r3, r0 8000aa6: 2b00 cmp r3, #0 8000aa8: d001 beq.n 8000aae { Error_Handler(); 8000aaa: f000 ffb9 bl 8001a20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8000aae: 4b42 ldr r3, [pc, #264] @ (8000bb8 ) 8000ab0: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_1; 8000ab2: 2306 movs r3, #6 8000ab4: 607b str r3, [r7, #4] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000ab6: 2306 movs r3, #6 8000ab8: 60bb str r3, [r7, #8] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000aba: f240 73ff movw r3, #2047 @ 0x7ff 8000abe: 60fb str r3, [r7, #12] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000ac0: 2304 movs r3, #4 8000ac2: 613b str r3, [r7, #16] sConfig.Offset = 0; 8000ac4: 2300 movs r3, #0 8000ac6: 617b str r3, [r7, #20] sConfig.OffsetSignedSaturation = DISABLE; 8000ac8: 2300 movs r3, #0 8000aca: 767b strb r3, [r7, #25] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000acc: 463b mov r3, r7 8000ace: 4619 mov r1, r3 8000ad0: 4837 ldr r0, [pc, #220] @ (8000bb0 ) 8000ad2: f004 fca1 bl 8005418 8000ad6: 4603 mov r3, r0 8000ad8: 2b00 cmp r3, #0 8000ada: d001 beq.n 8000ae0 { Error_Handler(); 8000adc: f000 ffa0 bl 8001a20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_7; 8000ae0: 4b36 ldr r3, [pc, #216] @ (8000bbc ) 8000ae2: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_2; 8000ae4: 230c movs r3, #12 8000ae6: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000ae8: 463b mov r3, r7 8000aea: 4619 mov r1, r3 8000aec: 4830 ldr r0, [pc, #192] @ (8000bb0 ) 8000aee: f004 fc93 bl 8005418 8000af2: 4603 mov r3, r0 8000af4: 2b00 cmp r3, #0 8000af6: d001 beq.n 8000afc { Error_Handler(); 8000af8: f000 ff92 bl 8001a20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_9; 8000afc: 4b30 ldr r3, [pc, #192] @ (8000bc0 ) 8000afe: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_3; 8000b00: 2312 movs r3, #18 8000b02: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000b04: 463b mov r3, r7 8000b06: 4619 mov r1, r3 8000b08: 4829 ldr r0, [pc, #164] @ (8000bb0 ) 8000b0a: f004 fc85 bl 8005418 8000b0e: 4603 mov r3, r0 8000b10: 2b00 cmp r3, #0 8000b12: d001 beq.n 8000b18 { Error_Handler(); 8000b14: f000 ff84 bl 8001a20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_16; 8000b18: 4b2a ldr r3, [pc, #168] @ (8000bc4 ) 8000b1a: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_4; 8000b1c: 2318 movs r3, #24 8000b1e: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000b20: 463b mov r3, r7 8000b22: 4619 mov r1, r3 8000b24: 4822 ldr r0, [pc, #136] @ (8000bb0 ) 8000b26: f004 fc77 bl 8005418 8000b2a: 4603 mov r3, r0 8000b2c: 2b00 cmp r3, #0 8000b2e: d001 beq.n 8000b34 { Error_Handler(); 8000b30: f000 ff76 bl 8001a20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_17; 8000b34: 4b24 ldr r3, [pc, #144] @ (8000bc8 ) 8000b36: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_5; 8000b38: f44f 7380 mov.w r3, #256 @ 0x100 8000b3c: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000b3e: 463b mov r3, r7 8000b40: 4619 mov r1, r3 8000b42: 481b ldr r0, [pc, #108] @ (8000bb0 ) 8000b44: f004 fc68 bl 8005418 8000b48: 4603 mov r3, r0 8000b4a: 2b00 cmp r3, #0 8000b4c: d001 beq.n 8000b52 { Error_Handler(); 8000b4e: f000 ff67 bl 8001a20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_14; 8000b52: 4b1e ldr r3, [pc, #120] @ (8000bcc ) 8000b54: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_6; 8000b56: f44f 7383 mov.w r3, #262 @ 0x106 8000b5a: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000b5c: 463b mov r3, r7 8000b5e: 4619 mov r1, r3 8000b60: 4813 ldr r0, [pc, #76] @ (8000bb0 ) 8000b62: f004 fc59 bl 8005418 8000b66: 4603 mov r3, r0 8000b68: 2b00 cmp r3, #0 8000b6a: d001 beq.n 8000b70 { Error_Handler(); 8000b6c: f000 ff58 bl 8001a20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_15; 8000b70: 4b17 ldr r3, [pc, #92] @ (8000bd0 ) 8000b72: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_7; 8000b74: f44f 7386 mov.w r3, #268 @ 0x10c 8000b78: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000b7a: 463b mov r3, r7 8000b7c: 4619 mov r1, r3 8000b7e: 480c ldr r0, [pc, #48] @ (8000bb0 ) 8000b80: f004 fc4a bl 8005418 8000b84: 4603 mov r3, r0 8000b86: 2b00 cmp r3, #0 8000b88: d001 beq.n 8000b8e { Error_Handler(); 8000b8a: f000 ff49 bl 8001a20 } /* USER CODE BEGIN ADC1_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000b8e: f240 72ff movw r2, #2047 @ 0x7ff 8000b92: f04f 1101 mov.w r1, #65537 @ 0x10001 8000b96: 4806 ldr r0, [pc, #24] @ (8000bb0 ) 8000b98: f005 fa7e bl 8006098 8000b9c: 4603 mov r3, r0 8000b9e: 2b00 cmp r3, #0 8000ba0: d001 beq.n 8000ba6 { Error_Handler(); 8000ba2: f000 ff3d bl 8001a20 } /* USER CODE END ADC1_Init 2 */ } 8000ba6: bf00 nop 8000ba8: 3728 adds r7, #40 @ 0x28 8000baa: 46bd mov sp, r7 8000bac: bd80 pop {r7, pc} 8000bae: bf00 nop 8000bb0: 24000140 .word 0x24000140 8000bb4: 40022000 .word 0x40022000 8000bb8: 21800100 .word 0x21800100 8000bbc: 1d500080 .word 0x1d500080 8000bc0: 25b00200 .word 0x25b00200 8000bc4: 43210000 .word 0x43210000 8000bc8: 47520000 .word 0x47520000 8000bcc: 3ac04000 .word 0x3ac04000 8000bd0: 3ef08000 .word 0x3ef08000 08000bd4 : * @brief ADC2 Initialization Function * @param None * @retval None */ static void MX_ADC2_Init(void) { 8000bd4: b580 push {r7, lr} 8000bd6: b088 sub sp, #32 8000bd8: af00 add r7, sp, #0 /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000bda: 1d3b adds r3, r7, #4 8000bdc: 2200 movs r2, #0 8000bde: 601a str r2, [r3, #0] 8000be0: 605a str r2, [r3, #4] 8000be2: 609a str r2, [r3, #8] 8000be4: 60da str r2, [r3, #12] 8000be6: 611a str r2, [r3, #16] 8000be8: 615a str r2, [r3, #20] 8000bea: 619a str r2, [r3, #24] /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; 8000bec: 4b3e ldr r3, [pc, #248] @ (8000ce8 ) 8000bee: 4a3f ldr r2, [pc, #252] @ (8000cec ) 8000bf0: 601a str r2, [r3, #0] hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 8000bf2: 4b3d ldr r3, [pc, #244] @ (8000ce8 ) 8000bf4: 2200 movs r2, #0 8000bf6: 605a str r2, [r3, #4] hadc2.Init.Resolution = ADC_RESOLUTION_16B; 8000bf8: 4b3b ldr r3, [pc, #236] @ (8000ce8 ) 8000bfa: 2200 movs r2, #0 8000bfc: 609a str r2, [r3, #8] hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000bfe: 4b3a ldr r3, [pc, #232] @ (8000ce8 ) 8000c00: 2201 movs r2, #1 8000c02: 60da str r2, [r3, #12] hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000c04: 4b38 ldr r3, [pc, #224] @ (8000ce8 ) 8000c06: 2208 movs r2, #8 8000c08: 611a str r2, [r3, #16] hadc2.Init.LowPowerAutoWait = DISABLE; 8000c0a: 4b37 ldr r3, [pc, #220] @ (8000ce8 ) 8000c0c: 2200 movs r2, #0 8000c0e: 751a strb r2, [r3, #20] hadc2.Init.ContinuousConvMode = ENABLE; 8000c10: 4b35 ldr r3, [pc, #212] @ (8000ce8 ) 8000c12: 2201 movs r2, #1 8000c14: 755a strb r2, [r3, #21] hadc2.Init.NbrOfConversion = 3; 8000c16: 4b34 ldr r3, [pc, #208] @ (8000ce8 ) 8000c18: 2203 movs r2, #3 8000c1a: 619a str r2, [r3, #24] hadc2.Init.DiscontinuousConvMode = DISABLE; 8000c1c: 4b32 ldr r3, [pc, #200] @ (8000ce8 ) 8000c1e: 2200 movs r2, #0 8000c20: 771a strb r2, [r3, #28] hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO; 8000c22: 4b31 ldr r3, [pc, #196] @ (8000ce8 ) 8000c24: f44f 62ac mov.w r2, #1376 @ 0x560 8000c28: 625a str r2, [r3, #36] @ 0x24 hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000c2a: 4b2f ldr r3, [pc, #188] @ (8000ce8 ) 8000c2c: f44f 6280 mov.w r2, #1024 @ 0x400 8000c30: 629a str r2, [r3, #40] @ 0x28 hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000c32: 4b2d ldr r3, [pc, #180] @ (8000ce8 ) 8000c34: 2201 movs r2, #1 8000c36: 62da str r2, [r3, #44] @ 0x2c hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000c38: 4b2b ldr r3, [pc, #172] @ (8000ce8 ) 8000c3a: 2200 movs r2, #0 8000c3c: 631a str r2, [r3, #48] @ 0x30 hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000c3e: 4b2a ldr r3, [pc, #168] @ (8000ce8 ) 8000c40: 2200 movs r2, #0 8000c42: 635a str r2, [r3, #52] @ 0x34 hadc2.Init.OversamplingMode = DISABLE; 8000c44: 4b28 ldr r3, [pc, #160] @ (8000ce8 ) 8000c46: 2200 movs r2, #0 8000c48: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc2) != HAL_OK) 8000c4c: 4826 ldr r0, [pc, #152] @ (8000ce8 ) 8000c4e: f004 f969 bl 8004f24 8000c52: 4603 mov r3, r0 8000c54: 2b00 cmp r3, #0 8000c56: d001 beq.n 8000c5c { Error_Handler(); 8000c58: f000 fee2 bl 8001a20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 8000c5c: 4b24 ldr r3, [pc, #144] @ (8000cf0 ) 8000c5e: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8000c60: 2306 movs r3, #6 8000c62: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000c64: 2306 movs r3, #6 8000c66: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000c68: f240 73ff movw r3, #2047 @ 0x7ff 8000c6c: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000c6e: 2304 movs r3, #4 8000c70: 617b str r3, [r7, #20] sConfig.Offset = 0; 8000c72: 2300 movs r3, #0 8000c74: 61bb str r3, [r7, #24] sConfig.OffsetSignedSaturation = DISABLE; 8000c76: 2300 movs r3, #0 8000c78: 777b strb r3, [r7, #29] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000c7a: 1d3b adds r3, r7, #4 8000c7c: 4619 mov r1, r3 8000c7e: 481a ldr r0, [pc, #104] @ (8000ce8 ) 8000c80: f004 fbca bl 8005418 8000c84: 4603 mov r3, r0 8000c86: 2b00 cmp r3, #0 8000c88: d001 beq.n 8000c8e { Error_Handler(); 8000c8a: f000 fec9 bl 8001a20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8000c8e: 4b19 ldr r3, [pc, #100] @ (8000cf4 ) 8000c90: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 8000c92: 230c movs r3, #12 8000c94: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000c96: 1d3b adds r3, r7, #4 8000c98: 4619 mov r1, r3 8000c9a: 4813 ldr r0, [pc, #76] @ (8000ce8 ) 8000c9c: f004 fbbc bl 8005418 8000ca0: 4603 mov r3, r0 8000ca2: 2b00 cmp r3, #0 8000ca4: d001 beq.n 8000caa { Error_Handler(); 8000ca6: f000 febb bl 8001a20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_5; 8000caa: 4b13 ldr r3, [pc, #76] @ (8000cf8 ) 8000cac: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8000cae: 2312 movs r3, #18 8000cb0: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000cb2: 1d3b adds r3, r7, #4 8000cb4: 4619 mov r1, r3 8000cb6: 480c ldr r0, [pc, #48] @ (8000ce8 ) 8000cb8: f004 fbae bl 8005418 8000cbc: 4603 mov r3, r0 8000cbe: 2b00 cmp r3, #0 8000cc0: d001 beq.n 8000cc6 { Error_Handler(); 8000cc2: f000 fead bl 8001a20 } /* USER CODE BEGIN ADC2_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc2, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000cc6: f240 72ff movw r2, #2047 @ 0x7ff 8000cca: f04f 1101 mov.w r1, #65537 @ 0x10001 8000cce: 4806 ldr r0, [pc, #24] @ (8000ce8 ) 8000cd0: f005 f9e2 bl 8006098 8000cd4: 4603 mov r3, r0 8000cd6: 2b00 cmp r3, #0 8000cd8: d001 beq.n 8000cde { Error_Handler(); 8000cda: f000 fea1 bl 8001a20 } /* USER CODE END ADC2_Init 2 */ } 8000cde: bf00 nop 8000ce0: 3720 adds r7, #32 8000ce2: 46bd mov sp, r7 8000ce4: bd80 pop {r7, pc} 8000ce6: bf00 nop 8000ce8: 240001a4 .word 0x240001a4 8000cec: 40022100 .word 0x40022100 8000cf0: 0c900008 .word 0x0c900008 8000cf4: 10c00010 .word 0x10c00010 8000cf8: 14f00020 .word 0x14f00020 08000cfc : * @brief ADC3 Initialization Function * @param None * @retval None */ static void MX_ADC3_Init(void) { 8000cfc: b580 push {r7, lr} 8000cfe: b088 sub sp, #32 8000d00: af00 add r7, sp, #0 /* USER CODE BEGIN ADC3_Init 0 */ /* USER CODE END ADC3_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000d02: 1d3b adds r3, r7, #4 8000d04: 2200 movs r2, #0 8000d06: 601a str r2, [r3, #0] 8000d08: 605a str r2, [r3, #4] 8000d0a: 609a str r2, [r3, #8] 8000d0c: 60da str r2, [r3, #12] 8000d0e: 611a str r2, [r3, #16] 8000d10: 615a str r2, [r3, #20] 8000d12: 619a str r2, [r3, #24] /* USER CODE END ADC3_Init 1 */ /** Common config */ hadc3.Instance = ADC3; 8000d14: 4b4b ldr r3, [pc, #300] @ (8000e44 ) 8000d16: 4a4c ldr r2, [pc, #304] @ (8000e48 ) 8000d18: 601a str r2, [r3, #0] hadc3.Init.Resolution = ADC_RESOLUTION_16B; 8000d1a: 4b4a ldr r3, [pc, #296] @ (8000e44 ) 8000d1c: 2200 movs r2, #0 8000d1e: 609a str r2, [r3, #8] hadc3.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000d20: 4b48 ldr r3, [pc, #288] @ (8000e44 ) 8000d22: 2201 movs r2, #1 8000d24: 60da str r2, [r3, #12] hadc3.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000d26: 4b47 ldr r3, [pc, #284] @ (8000e44 ) 8000d28: 2208 movs r2, #8 8000d2a: 611a str r2, [r3, #16] hadc3.Init.LowPowerAutoWait = DISABLE; 8000d2c: 4b45 ldr r3, [pc, #276] @ (8000e44 ) 8000d2e: 2200 movs r2, #0 8000d30: 751a strb r2, [r3, #20] hadc3.Init.ContinuousConvMode = ENABLE; 8000d32: 4b44 ldr r3, [pc, #272] @ (8000e44 ) 8000d34: 2201 movs r2, #1 8000d36: 755a strb r2, [r3, #21] hadc3.Init.NbrOfConversion = 5; 8000d38: 4b42 ldr r3, [pc, #264] @ (8000e44 ) 8000d3a: 2205 movs r2, #5 8000d3c: 619a str r2, [r3, #24] hadc3.Init.DiscontinuousConvMode = DISABLE; 8000d3e: 4b41 ldr r3, [pc, #260] @ (8000e44 ) 8000d40: 2200 movs r2, #0 8000d42: 771a strb r2, [r3, #28] hadc3.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO; 8000d44: 4b3f ldr r3, [pc, #252] @ (8000e44 ) 8000d46: f44f 62ac mov.w r2, #1376 @ 0x560 8000d4a: 625a str r2, [r3, #36] @ 0x24 hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000d4c: 4b3d ldr r3, [pc, #244] @ (8000e44 ) 8000d4e: f44f 6280 mov.w r2, #1024 @ 0x400 8000d52: 629a str r2, [r3, #40] @ 0x28 hadc3.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000d54: 4b3b ldr r3, [pc, #236] @ (8000e44 ) 8000d56: 2201 movs r2, #1 8000d58: 62da str r2, [r3, #44] @ 0x2c hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000d5a: 4b3a ldr r3, [pc, #232] @ (8000e44 ) 8000d5c: 2200 movs r2, #0 8000d5e: 631a str r2, [r3, #48] @ 0x30 hadc3.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000d60: 4b38 ldr r3, [pc, #224] @ (8000e44 ) 8000d62: 2200 movs r2, #0 8000d64: 635a str r2, [r3, #52] @ 0x34 hadc3.Init.OversamplingMode = DISABLE; 8000d66: 4b37 ldr r3, [pc, #220] @ (8000e44 ) 8000d68: 2200 movs r2, #0 8000d6a: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc3) != HAL_OK) 8000d6e: 4835 ldr r0, [pc, #212] @ (8000e44 ) 8000d70: f004 f8d8 bl 8004f24 8000d74: 4603 mov r3, r0 8000d76: 2b00 cmp r3, #0 8000d78: d001 beq.n 8000d7e { Error_Handler(); 8000d7a: f000 fe51 bl 8001a20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_0; 8000d7e: 2301 movs r3, #1 8000d80: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8000d82: 2306 movs r3, #6 8000d84: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000d86: 2306 movs r3, #6 8000d88: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000d8a: f240 73ff movw r3, #2047 @ 0x7ff 8000d8e: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000d90: 2304 movs r3, #4 8000d92: 617b str r3, [r7, #20] sConfig.Offset = 0; 8000d94: 2300 movs r3, #0 8000d96: 61bb str r3, [r7, #24] sConfig.OffsetSignedSaturation = DISABLE; 8000d98: 2300 movs r3, #0 8000d9a: 777b strb r3, [r7, #29] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d9c: 1d3b adds r3, r7, #4 8000d9e: 4619 mov r1, r3 8000da0: 4828 ldr r0, [pc, #160] @ (8000e44 ) 8000da2: f004 fb39 bl 8005418 8000da6: 4603 mov r3, r0 8000da8: 2b00 cmp r3, #0 8000daa: d001 beq.n 8000db0 { Error_Handler(); 8000dac: f000 fe38 bl 8001a20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 8000db0: 4b26 ldr r3, [pc, #152] @ (8000e4c ) 8000db2: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 8000db4: 230c movs r3, #12 8000db6: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000db8: 1d3b adds r3, r7, #4 8000dba: 4619 mov r1, r3 8000dbc: 4821 ldr r0, [pc, #132] @ (8000e44 ) 8000dbe: f004 fb2b bl 8005418 8000dc2: 4603 mov r3, r0 8000dc4: 2b00 cmp r3, #0 8000dc6: d001 beq.n 8000dcc { Error_Handler(); 8000dc8: f000 fe2a bl 8001a20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_10; 8000dcc: 4b20 ldr r3, [pc, #128] @ (8000e50 ) 8000dce: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8000dd0: 2312 movs r3, #18 8000dd2: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000dd4: 1d3b adds r3, r7, #4 8000dd6: 4619 mov r1, r3 8000dd8: 481a ldr r0, [pc, #104] @ (8000e44 ) 8000dda: f004 fb1d bl 8005418 8000dde: 4603 mov r3, r0 8000de0: 2b00 cmp r3, #0 8000de2: d001 beq.n 8000de8 { Error_Handler(); 8000de4: f000 fe1c bl 8001a20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_11; 8000de8: 4b1a ldr r3, [pc, #104] @ (8000e54 ) 8000dea: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_4; 8000dec: 2318 movs r3, #24 8000dee: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000df0: 1d3b adds r3, r7, #4 8000df2: 4619 mov r1, r3 8000df4: 4813 ldr r0, [pc, #76] @ (8000e44 ) 8000df6: f004 fb0f bl 8005418 8000dfa: 4603 mov r3, r0 8000dfc: 2b00 cmp r3, #0 8000dfe: d001 beq.n 8000e04 { Error_Handler(); 8000e00: f000 fe0e bl 8001a20 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; 8000e04: 4b14 ldr r3, [pc, #80] @ (8000e58 ) 8000e06: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_5; 8000e08: f44f 7380 mov.w r3, #256 @ 0x100 8000e0c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000e0e: 1d3b adds r3, r7, #4 8000e10: 4619 mov r1, r3 8000e12: 480c ldr r0, [pc, #48] @ (8000e44 ) 8000e14: f004 fb00 bl 8005418 8000e18: 4603 mov r3, r0 8000e1a: 2b00 cmp r3, #0 8000e1c: d001 beq.n 8000e22 { Error_Handler(); 8000e1e: f000 fdff bl 8001a20 } /* USER CODE BEGIN ADC3_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc3, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000e22: f240 72ff movw r2, #2047 @ 0x7ff 8000e26: f04f 1101 mov.w r1, #65537 @ 0x10001 8000e2a: 4806 ldr r0, [pc, #24] @ (8000e44 ) 8000e2c: f005 f934 bl 8006098 8000e30: 4603 mov r3, r0 8000e32: 2b00 cmp r3, #0 8000e34: d001 beq.n 8000e3a { Error_Handler(); 8000e36: f000 fdf3 bl 8001a20 } /* USER CODE END ADC3_Init 2 */ } 8000e3a: bf00 nop 8000e3c: 3720 adds r7, #32 8000e3e: 46bd mov sp, r7 8000e40: bd80 pop {r7, pc} 8000e42: bf00 nop 8000e44: 24000208 .word 0x24000208 8000e48: 58026000 .word 0x58026000 8000e4c: 04300002 .word 0x04300002 8000e50: 2a000400 .word 0x2a000400 8000e54: 2e300800 .word 0x2e300800 8000e58: cfb80000 .word 0xcfb80000 08000e5c : * @brief CRC Initialization Function * @param None * @retval None */ static void MX_CRC_Init(void) { 8000e5c: b580 push {r7, lr} 8000e5e: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 8000e60: 4b11 ldr r3, [pc, #68] @ (8000ea8 ) 8000e62: 4a12 ldr r2, [pc, #72] @ (8000eac ) 8000e64: 601a str r2, [r3, #0] hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_DISABLE; 8000e66: 4b10 ldr r3, [pc, #64] @ (8000ea8 ) 8000e68: 2201 movs r2, #1 8000e6a: 711a strb r2, [r3, #4] hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE; 8000e6c: 4b0e ldr r3, [pc, #56] @ (8000ea8 ) 8000e6e: 2200 movs r2, #0 8000e70: 715a strb r2, [r3, #5] hcrc.Init.GeneratingPolynomial = 4129; 8000e72: 4b0d ldr r3, [pc, #52] @ (8000ea8 ) 8000e74: f241 0221 movw r2, #4129 @ 0x1021 8000e78: 609a str r2, [r3, #8] hcrc.Init.CRCLength = CRC_POLYLENGTH_16B; 8000e7a: 4b0b ldr r3, [pc, #44] @ (8000ea8 ) 8000e7c: 2208 movs r2, #8 8000e7e: 60da str r2, [r3, #12] hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE; 8000e80: 4b09 ldr r3, [pc, #36] @ (8000ea8 ) 8000e82: 2200 movs r2, #0 8000e84: 615a str r2, [r3, #20] hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE; 8000e86: 4b08 ldr r3, [pc, #32] @ (8000ea8 ) 8000e88: 2200 movs r2, #0 8000e8a: 619a str r2, [r3, #24] hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; 8000e8c: 4b06 ldr r3, [pc, #24] @ (8000ea8 ) 8000e8e: 2201 movs r2, #1 8000e90: 621a str r2, [r3, #32] if (HAL_CRC_Init(&hcrc) != HAL_OK) 8000e92: 4805 ldr r0, [pc, #20] @ (8000ea8 ) 8000e94: f005 fb9a bl 80065cc 8000e98: 4603 mov r3, r0 8000e9a: 2b00 cmp r3, #0 8000e9c: d001 beq.n 8000ea2 { Error_Handler(); 8000e9e: f000 fdbf bl 8001a20 } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 8000ea2: bf00 nop 8000ea4: bd80 pop {r7, pc} 8000ea6: bf00 nop 8000ea8: 240003d4 .word 0x240003d4 8000eac: 58024c00 .word 0x58024c00 08000eb0 : * @brief DAC1 Initialization Function * @param None * @retval None */ static void MX_DAC1_Init(void) { 8000eb0: b580 push {r7, lr} 8000eb2: b08a sub sp, #40 @ 0x28 8000eb4: af00 add r7, sp, #0 /* USER CODE BEGIN DAC1_Init 0 */ /* USER CODE END DAC1_Init 0 */ DAC_ChannelConfTypeDef sConfig = {0}; 8000eb6: 1d3b adds r3, r7, #4 8000eb8: 2224 movs r2, #36 @ 0x24 8000eba: 2100 movs r1, #0 8000ebc: 4618 mov r0, r3 8000ebe: f015 fc4a bl 8016756 /* USER CODE END DAC1_Init 1 */ /** DAC Initialization */ hdac1.Instance = DAC1; 8000ec2: 4b17 ldr r3, [pc, #92] @ (8000f20 ) 8000ec4: 4a17 ldr r2, [pc, #92] @ (8000f24 ) 8000ec6: 601a str r2, [r3, #0] if (HAL_DAC_Init(&hdac1) != HAL_OK) 8000ec8: 4815 ldr r0, [pc, #84] @ (8000f20 ) 8000eca: f005 fd85 bl 80069d8 8000ece: 4603 mov r3, r0 8000ed0: 2b00 cmp r3, #0 8000ed2: d001 beq.n 8000ed8 { Error_Handler(); 8000ed4: f000 fda4 bl 8001a20 } /** DAC channel OUT1 config */ sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; 8000ed8: 2300 movs r3, #0 8000eda: 607b str r3, [r7, #4] sConfig.DAC_Trigger = DAC_TRIGGER_NONE; 8000edc: 2300 movs r3, #0 8000ede: 60bb str r3, [r7, #8] sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; 8000ee0: 2300 movs r3, #0 8000ee2: 60fb str r3, [r7, #12] sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE; 8000ee4: 2301 movs r3, #1 8000ee6: 613b str r3, [r7, #16] sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; 8000ee8: 2300 movs r3, #0 8000eea: 617b str r3, [r7, #20] if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) 8000eec: 1d3b adds r3, r7, #4 8000eee: 2200 movs r2, #0 8000ef0: 4619 mov r1, r3 8000ef2: 480b ldr r0, [pc, #44] @ (8000f20 ) 8000ef4: f005 fe74 bl 8006be0 8000ef8: 4603 mov r3, r0 8000efa: 2b00 cmp r3, #0 8000efc: d001 beq.n 8000f02 { Error_Handler(); 8000efe: f000 fd8f bl 8001a20 } /** DAC channel OUT2 config */ if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK) 8000f02: 1d3b adds r3, r7, #4 8000f04: 2210 movs r2, #16 8000f06: 4619 mov r1, r3 8000f08: 4805 ldr r0, [pc, #20] @ (8000f20 ) 8000f0a: f005 fe69 bl 8006be0 8000f0e: 4603 mov r3, r0 8000f10: 2b00 cmp r3, #0 8000f12: d001 beq.n 8000f18 { Error_Handler(); 8000f14: f000 fd84 bl 8001a20 } /* USER CODE BEGIN DAC1_Init 2 */ /* USER CODE END DAC1_Init 2 */ } 8000f18: bf00 nop 8000f1a: 3728 adds r7, #40 @ 0x28 8000f1c: 46bd mov sp, r7 8000f1e: bd80 pop {r7, pc} 8000f20: 240003f8 .word 0x240003f8 8000f24: 40007400 .word 0x40007400 08000f28 : * @brief RNG Initialization Function * @param None * @retval None */ static void MX_RNG_Init(void) { 8000f28: b580 push {r7, lr} 8000f2a: af00 add r7, sp, #0 /* USER CODE END RNG_Init 0 */ /* USER CODE BEGIN RNG_Init 1 */ /* USER CODE END RNG_Init 1 */ hrng.Instance = RNG; 8000f2c: 4b07 ldr r3, [pc, #28] @ (8000f4c ) 8000f2e: 4a08 ldr r2, [pc, #32] @ (8000f50 ) 8000f30: 601a str r2, [r3, #0] hrng.Init.ClockErrorDetection = RNG_CED_ENABLE; 8000f32: 4b06 ldr r3, [pc, #24] @ (8000f4c ) 8000f34: 2200 movs r2, #0 8000f36: 605a str r2, [r3, #4] if (HAL_RNG_Init(&hrng) != HAL_OK) 8000f38: 4804 ldr r0, [pc, #16] @ (8000f4c ) 8000f3a: f00c fe43 bl 800dbc4 8000f3e: 4603 mov r3, r0 8000f40: 2b00 cmp r3, #0 8000f42: d001 beq.n 8000f48 { Error_Handler(); 8000f44: f000 fd6c bl 8001a20 } /* USER CODE BEGIN RNG_Init 2 */ /* USER CODE END RNG_Init 2 */ } 8000f48: bf00 nop 8000f4a: bd80 pop {r7, pc} 8000f4c: 2400040c .word 0x2400040c 8000f50: 48021800 .word 0x48021800 08000f54 : * @brief TIM1 Initialization Function * @param None * @retval None */ static void MX_TIM1_Init(void) { 8000f54: b5b0 push {r4, r5, r7, lr} 8000f56: b096 sub sp, #88 @ 0x58 8000f58: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000f5a: f107 034c add.w r3, r7, #76 @ 0x4c 8000f5e: 2200 movs r2, #0 8000f60: 601a str r2, [r3, #0] 8000f62: 605a str r2, [r3, #4] 8000f64: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 8000f66: f107 0330 add.w r3, r7, #48 @ 0x30 8000f6a: 2200 movs r2, #0 8000f6c: 601a str r2, [r3, #0] 8000f6e: 605a str r2, [r3, #4] 8000f70: 609a str r2, [r3, #8] 8000f72: 60da str r2, [r3, #12] 8000f74: 611a str r2, [r3, #16] 8000f76: 615a str r2, [r3, #20] 8000f78: 619a str r2, [r3, #24] TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 8000f7a: 1d3b adds r3, r7, #4 8000f7c: 222c movs r2, #44 @ 0x2c 8000f7e: 2100 movs r1, #0 8000f80: 4618 mov r0, r3 8000f82: f015 fbe8 bl 8016756 /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; 8000f86: 4b3e ldr r3, [pc, #248] @ (8001080 ) 8000f88: 4a3e ldr r2, [pc, #248] @ (8001084 ) 8000f8a: 601a str r2, [r3, #0] htim1.Init.Prescaler = 199; 8000f8c: 4b3c ldr r3, [pc, #240] @ (8001080 ) 8000f8e: 22c7 movs r2, #199 @ 0xc7 8000f90: 605a str r2, [r3, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 8000f92: 4b3b ldr r3, [pc, #236] @ (8001080 ) 8000f94: 2200 movs r2, #0 8000f96: 609a str r2, [r3, #8] htim1.Init.Period = 999; 8000f98: 4b39 ldr r3, [pc, #228] @ (8001080 ) 8000f9a: f240 32e7 movw r2, #999 @ 0x3e7 8000f9e: 60da str r2, [r3, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000fa0: 4b37 ldr r3, [pc, #220] @ (8001080 ) 8000fa2: 2200 movs r2, #0 8000fa4: 611a str r2, [r3, #16] htim1.Init.RepetitionCounter = 0; 8000fa6: 4b36 ldr r3, [pc, #216] @ (8001080 ) 8000fa8: 2200 movs r2, #0 8000faa: 615a str r2, [r3, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8000fac: 4b34 ldr r3, [pc, #208] @ (8001080 ) 8000fae: 2280 movs r2, #128 @ 0x80 8000fb0: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 8000fb2: 4833 ldr r0, [pc, #204] @ (8001080 ) 8000fb4: f00c ffa8 bl 800df08 8000fb8: 4603 mov r3, r0 8000fba: 2b00 cmp r3, #0 8000fbc: d001 beq.n 8000fc2 { Error_Handler(); 8000fbe: f000 fd2f bl 8001a20 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000fc2: 2300 movs r3, #0 8000fc4: 64fb str r3, [r7, #76] @ 0x4c sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 8000fc6: 2300 movs r3, #0 8000fc8: 653b str r3, [r7, #80] @ 0x50 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000fca: 2300 movs r3, #0 8000fcc: 657b str r3, [r7, #84] @ 0x54 if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 8000fce: f107 034c add.w r3, r7, #76 @ 0x4c 8000fd2: 4619 mov r1, r3 8000fd4: 482a ldr r0, [pc, #168] @ (8001080 ) 8000fd6: f00e f949 bl 800f26c 8000fda: 4603 mov r3, r0 8000fdc: 2b00 cmp r3, #0 8000fde: d001 beq.n 8000fe4 { Error_Handler(); 8000fe0: f000 fd1e bl 8001a20 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 8000fe4: 2360 movs r3, #96 @ 0x60 8000fe6: 633b str r3, [r7, #48] @ 0x30 sConfigOC.Pulse = 99; 8000fe8: 2363 movs r3, #99 @ 0x63 8000fea: 637b str r3, [r7, #52] @ 0x34 sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8000fec: 2300 movs r3, #0 8000fee: 63bb str r3, [r7, #56] @ 0x38 sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 8000ff0: 2300 movs r3, #0 8000ff2: 63fb str r3, [r7, #60] @ 0x3c sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8000ff4: 2300 movs r3, #0 8000ff6: 643b str r3, [r7, #64] @ 0x40 sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 8000ff8: 2300 movs r3, #0 8000ffa: 647b str r3, [r7, #68] @ 0x44 sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 8000ffc: 2300 movs r3, #0 8000ffe: 64bb str r3, [r7, #72] @ 0x48 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8001000: f107 0330 add.w r3, r7, #48 @ 0x30 8001004: 2204 movs r2, #4 8001006: 4619 mov r1, r3 8001008: 481d ldr r0, [pc, #116] @ (8001080 ) 800100a: f00d fa81 bl 800e510 800100e: 4603 mov r3, r0 8001010: 2b00 cmp r3, #0 8001012: d001 beq.n 8001018 { Error_Handler(); 8001014: f000 fd04 bl 8001a20 } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 8001018: 2300 movs r3, #0 800101a: 607b str r3, [r7, #4] sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 800101c: 2300 movs r3, #0 800101e: 60bb str r3, [r7, #8] sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 8001020: 2300 movs r3, #0 8001022: 60fb str r3, [r7, #12] sBreakDeadTimeConfig.DeadTime = 0; 8001024: 2300 movs r3, #0 8001026: 613b str r3, [r7, #16] sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 8001028: 2300 movs r3, #0 800102a: 617b str r3, [r7, #20] sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 800102c: f44f 5300 mov.w r3, #8192 @ 0x2000 8001030: 61bb str r3, [r7, #24] sBreakDeadTimeConfig.BreakFilter = 0; 8001032: 2300 movs r3, #0 8001034: 61fb str r3, [r7, #28] sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 8001036: 2300 movs r3, #0 8001038: 623b str r3, [r7, #32] sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 800103a: f04f 7300 mov.w r3, #33554432 @ 0x2000000 800103e: 627b str r3, [r7, #36] @ 0x24 sBreakDeadTimeConfig.Break2Filter = 0; 8001040: 2300 movs r3, #0 8001042: 62bb str r3, [r7, #40] @ 0x28 sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 8001044: 2300 movs r3, #0 8001046: 62fb str r3, [r7, #44] @ 0x2c if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 8001048: 1d3b adds r3, r7, #4 800104a: 4619 mov r1, r3 800104c: 480c ldr r0, [pc, #48] @ (8001080 ) 800104e: f00e f99b bl 800f388 8001052: 4603 mov r3, r0 8001054: 2b00 cmp r3, #0 8001056: d001 beq.n 800105c { Error_Handler(); 8001058: f000 fce2 bl 8001a20 } /* USER CODE BEGIN TIM1_Init 2 */ memcpy(&fanTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 800105c: 4b0a ldr r3, [pc, #40] @ (8001088 ) 800105e: 461d mov r5, r3 8001060: f107 0430 add.w r4, r7, #48 @ 0x30 8001064: cc0f ldmia r4!, {r0, r1, r2, r3} 8001066: c50f stmia r5!, {r0, r1, r2, r3} 8001068: e894 0007 ldmia.w r4, {r0, r1, r2} 800106c: e885 0007 stmia.w r5, {r0, r1, r2} /* USER CODE END TIM1_Init 2 */ HAL_TIM_MspPostInit(&htim1); 8001070: 4803 ldr r0, [pc, #12] @ (8001080 ) 8001072: f002 fa07 bl 8003484 } 8001076: bf00 nop 8001078: 3758 adds r7, #88 @ 0x58 800107a: 46bd mov sp, r7 800107c: bdb0 pop {r4, r5, r7, pc} 800107e: bf00 nop 8001080: 24000420 .word 0x24000420 8001084: 40010000 .word 0x40010000 8001088: 240006f0 .word 0x240006f0 0800108c : * @brief TIM2 Initialization Function * @param None * @retval None */ static void MX_TIM2_Init(void) { 800108c: b580 push {r7, lr} 800108e: b088 sub sp, #32 8001090: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8001092: f107 0310 add.w r3, r7, #16 8001096: 2200 movs r2, #0 8001098: 601a str r2, [r3, #0] 800109a: 605a str r2, [r3, #4] 800109c: 609a str r2, [r3, #8] 800109e: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 80010a0: 1d3b adds r3, r7, #4 80010a2: 2200 movs r2, #0 80010a4: 601a str r2, [r3, #0] 80010a6: 605a str r2, [r3, #4] 80010a8: 609a str r2, [r3, #8] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 80010aa: 4b1e ldr r3, [pc, #120] @ (8001124 ) 80010ac: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 80010b0: 601a str r2, [r3, #0] htim2.Init.Prescaler = 0; 80010b2: 4b1c ldr r3, [pc, #112] @ (8001124 ) 80010b4: 2200 movs r2, #0 80010b6: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 80010b8: 4b1a ldr r3, [pc, #104] @ (8001124 ) 80010ba: 2200 movs r2, #0 80010bc: 609a str r2, [r3, #8] htim2.Init.Period = 9999999; 80010be: 4b19 ldr r3, [pc, #100] @ (8001124 ) 80010c0: 4a19 ldr r2, [pc, #100] @ (8001128 ) 80010c2: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2; 80010c4: 4b17 ldr r3, [pc, #92] @ (8001124 ) 80010c6: f44f 7280 mov.w r2, #256 @ 0x100 80010ca: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 80010cc: 4b15 ldr r3, [pc, #84] @ (8001124 ) 80010ce: 2280 movs r2, #128 @ 0x80 80010d0: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 80010d2: 4814 ldr r0, [pc, #80] @ (8001124 ) 80010d4: f00c fdd8 bl 800dc88 80010d8: 4603 mov r3, r0 80010da: 2b00 cmp r3, #0 80010dc: d001 beq.n 80010e2 { Error_Handler(); 80010de: f000 fc9f bl 8001a20 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 80010e2: f44f 5380 mov.w r3, #4096 @ 0x1000 80010e6: 613b str r3, [r7, #16] if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 80010e8: f107 0310 add.w r3, r7, #16 80010ec: 4619 mov r1, r3 80010ee: 480d ldr r0, [pc, #52] @ (8001124 ) 80010f0: f00d fb22 bl 800e738 80010f4: 4603 mov r3, r0 80010f6: 2b00 cmp r3, #0 80010f8: d001 beq.n 80010fe { Error_Handler(); 80010fa: f000 fc91 bl 8001a20 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 80010fe: 2320 movs r3, #32 8001100: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; 8001102: 2380 movs r3, #128 @ 0x80 8001104: 60fb str r3, [r7, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 8001106: 1d3b adds r3, r7, #4 8001108: 4619 mov r1, r3 800110a: 4806 ldr r0, [pc, #24] @ (8001124 ) 800110c: f00e f8ae bl 800f26c 8001110: 4603 mov r3, r0 8001112: 2b00 cmp r3, #0 8001114: d001 beq.n 800111a { Error_Handler(); 8001116: f000 fc83 bl 8001a20 } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ } 800111a: bf00 nop 800111c: 3720 adds r7, #32 800111e: 46bd mov sp, r7 8001120: bd80 pop {r7, pc} 8001122: bf00 nop 8001124: 2400046c .word 0x2400046c 8001128: 0098967f .word 0x0098967f 0800112c : * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { 800112c: b5b0 push {r4, r5, r7, lr} 800112e: b08a sub sp, #40 @ 0x28 8001130: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001132: f107 031c add.w r3, r7, #28 8001136: 2200 movs r2, #0 8001138: 601a str r2, [r3, #0] 800113a: 605a str r2, [r3, #4] 800113c: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 800113e: 463b mov r3, r7 8001140: 2200 movs r2, #0 8001142: 601a str r2, [r3, #0] 8001144: 605a str r2, [r3, #4] 8001146: 609a str r2, [r3, #8] 8001148: 60da str r2, [r3, #12] 800114a: 611a str r2, [r3, #16] 800114c: 615a str r2, [r3, #20] 800114e: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 8001150: 4b48 ldr r3, [pc, #288] @ (8001274 ) 8001152: 4a49 ldr r2, [pc, #292] @ (8001278 ) 8001154: 601a str r2, [r3, #0] htim3.Init.Prescaler = 199; 8001156: 4b47 ldr r3, [pc, #284] @ (8001274 ) 8001158: 22c7 movs r2, #199 @ 0xc7 800115a: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 800115c: 4b45 ldr r3, [pc, #276] @ (8001274 ) 800115e: 2200 movs r2, #0 8001160: 609a str r2, [r3, #8] htim3.Init.Period = 999; 8001162: 4b44 ldr r3, [pc, #272] @ (8001274 ) 8001164: f240 32e7 movw r2, #999 @ 0x3e7 8001168: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800116a: 4b42 ldr r3, [pc, #264] @ (8001274 ) 800116c: 2200 movs r2, #0 800116e: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001170: 4b40 ldr r3, [pc, #256] @ (8001274 ) 8001172: 2280 movs r2, #128 @ 0x80 8001174: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 8001176: 483f ldr r0, [pc, #252] @ (8001274 ) 8001178: f00c fec6 bl 800df08 800117c: 4603 mov r3, r0 800117e: 2b00 cmp r3, #0 8001180: d001 beq.n 8001186 { Error_Handler(); 8001182: f000 fc4d bl 8001a20 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001186: 2300 movs r3, #0 8001188: 61fb str r3, [r7, #28] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800118a: 2300 movs r3, #0 800118c: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800118e: f107 031c add.w r3, r7, #28 8001192: 4619 mov r1, r3 8001194: 4837 ldr r0, [pc, #220] @ (8001274 ) 8001196: f00e f869 bl 800f26c 800119a: 4603 mov r3, r0 800119c: 2b00 cmp r3, #0 800119e: d001 beq.n 80011a4 { Error_Handler(); 80011a0: f000 fc3e bl 8001a20 } sConfigOC.OCMode = TIM_OCMODE_COMBINED_PWM1; 80011a4: 4b35 ldr r3, [pc, #212] @ (800127c ) 80011a6: 603b str r3, [r7, #0] sConfigOC.Pulse = 500; 80011a8: f44f 73fa mov.w r3, #500 @ 0x1f4 80011ac: 607b str r3, [r7, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 80011ae: 2300 movs r3, #0 80011b0: 60bb str r3, [r7, #8] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 80011b2: 2300 movs r3, #0 80011b4: 613b str r3, [r7, #16] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 80011b6: 463b mov r3, r7 80011b8: 2200 movs r2, #0 80011ba: 4619 mov r1, r3 80011bc: 482d ldr r0, [pc, #180] @ (8001274 ) 80011be: f00d f9a7 bl 800e510 80011c2: 4603 mov r3, r0 80011c4: 2b00 cmp r3, #0 80011c6: d001 beq.n 80011cc { Error_Handler(); 80011c8: f000 fc2a bl 8001a20 } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_1); 80011cc: 4b29 ldr r3, [pc, #164] @ (8001274 ) 80011ce: 681b ldr r3, [r3, #0] 80011d0: 699a ldr r2, [r3, #24] 80011d2: 4b28 ldr r3, [pc, #160] @ (8001274 ) 80011d4: 681b ldr r3, [r3, #0] 80011d6: f022 0208 bic.w r2, r2, #8 80011da: 619a str r2, [r3, #24] sConfigOC.OCMode = TIM_OCMODE_PWM1; 80011dc: 2360 movs r3, #96 @ 0x60 80011de: 603b str r3, [r7, #0] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 80011e0: 463b mov r3, r7 80011e2: 2204 movs r2, #4 80011e4: 4619 mov r1, r3 80011e6: 4823 ldr r0, [pc, #140] @ (8001274 ) 80011e8: f00d f992 bl 800e510 80011ec: 4603 mov r3, r0 80011ee: 2b00 cmp r3, #0 80011f0: d001 beq.n 80011f6 { Error_Handler(); 80011f2: f000 fc15 bl 8001a20 } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_2); 80011f6: 4b1f ldr r3, [pc, #124] @ (8001274 ) 80011f8: 681b ldr r3, [r3, #0] 80011fa: 699a ldr r2, [r3, #24] 80011fc: 4b1d ldr r3, [pc, #116] @ (8001274 ) 80011fe: 681b ldr r3, [r3, #0] 8001200: f422 6200 bic.w r2, r2, #2048 @ 0x800 8001204: 619a str r2, [r3, #24] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 8001206: 463b mov r3, r7 8001208: 2208 movs r2, #8 800120a: 4619 mov r1, r3 800120c: 4819 ldr r0, [pc, #100] @ (8001274 ) 800120e: f00d f97f bl 800e510 8001212: 4603 mov r3, r0 8001214: 2b00 cmp r3, #0 8001216: d001 beq.n 800121c { Error_Handler(); 8001218: f000 fc02 bl 8001a20 } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_3); 800121c: 4b15 ldr r3, [pc, #84] @ (8001274 ) 800121e: 681b ldr r3, [r3, #0] 8001220: 69da ldr r2, [r3, #28] 8001222: 4b14 ldr r3, [pc, #80] @ (8001274 ) 8001224: 681b ldr r3, [r3, #0] 8001226: f022 0208 bic.w r2, r2, #8 800122a: 61da str r2, [r3, #28] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 800122c: 463b mov r3, r7 800122e: 220c movs r2, #12 8001230: 4619 mov r1, r3 8001232: 4810 ldr r0, [pc, #64] @ (8001274 ) 8001234: f00d f96c bl 800e510 8001238: 4603 mov r3, r0 800123a: 2b00 cmp r3, #0 800123c: d001 beq.n 8001242 { Error_Handler(); 800123e: f000 fbef bl 8001a20 } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_4); 8001242: 4b0c ldr r3, [pc, #48] @ (8001274 ) 8001244: 681b ldr r3, [r3, #0] 8001246: 69da ldr r2, [r3, #28] 8001248: 4b0a ldr r3, [pc, #40] @ (8001274 ) 800124a: 681b ldr r3, [r3, #0] 800124c: f422 6200 bic.w r2, r2, #2048 @ 0x800 8001250: 61da str r2, [r3, #28] /* USER CODE BEGIN TIM3_Init 2 */ memcpy(&motorXYTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 8001252: 4b0b ldr r3, [pc, #44] @ (8001280 ) 8001254: 461d mov r5, r3 8001256: 463c mov r4, r7 8001258: cc0f ldmia r4!, {r0, r1, r2, r3} 800125a: c50f stmia r5!, {r0, r1, r2, r3} 800125c: e894 0007 ldmia.w r4, {r0, r1, r2} 8001260: e885 0007 stmia.w r5, {r0, r1, r2} /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 8001264: 4803 ldr r0, [pc, #12] @ (8001274 ) 8001266: f002 f90d bl 8003484 } 800126a: bf00 nop 800126c: 3728 adds r7, #40 @ 0x28 800126e: 46bd mov sp, r7 8001270: bdb0 pop {r4, r5, r7, pc} 8001272: bf00 nop 8001274: 240004b8 .word 0x240004b8 8001278: 40000400 .word 0x40000400 800127c: 00010040 .word 0x00010040 8001280: 2400070c .word 0x2400070c 08001284 : * @brief UART8 Initialization Function * @param None * @retval None */ static void MX_UART8_Init(void) { 8001284: b580 push {r7, lr} 8001286: af00 add r7, sp, #0 /* USER CODE END UART8_Init 0 */ /* USER CODE BEGIN UART8_Init 1 */ /* USER CODE END UART8_Init 1 */ huart8.Instance = UART8; 8001288: 4b22 ldr r3, [pc, #136] @ (8001314 ) 800128a: 4a23 ldr r2, [pc, #140] @ (8001318 ) 800128c: 601a str r2, [r3, #0] huart8.Init.BaudRate = 115200; 800128e: 4b21 ldr r3, [pc, #132] @ (8001314 ) 8001290: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001294: 605a str r2, [r3, #4] huart8.Init.WordLength = UART_WORDLENGTH_8B; 8001296: 4b1f ldr r3, [pc, #124] @ (8001314 ) 8001298: 2200 movs r2, #0 800129a: 609a str r2, [r3, #8] huart8.Init.StopBits = UART_STOPBITS_1; 800129c: 4b1d ldr r3, [pc, #116] @ (8001314 ) 800129e: 2200 movs r2, #0 80012a0: 60da str r2, [r3, #12] huart8.Init.Parity = UART_PARITY_NONE; 80012a2: 4b1c ldr r3, [pc, #112] @ (8001314 ) 80012a4: 2200 movs r2, #0 80012a6: 611a str r2, [r3, #16] huart8.Init.Mode = UART_MODE_TX_RX; 80012a8: 4b1a ldr r3, [pc, #104] @ (8001314 ) 80012aa: 220c movs r2, #12 80012ac: 615a str r2, [r3, #20] huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80012ae: 4b19 ldr r3, [pc, #100] @ (8001314 ) 80012b0: 2200 movs r2, #0 80012b2: 619a str r2, [r3, #24] huart8.Init.OverSampling = UART_OVERSAMPLING_16; 80012b4: 4b17 ldr r3, [pc, #92] @ (8001314 ) 80012b6: 2200 movs r2, #0 80012b8: 61da str r2, [r3, #28] huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 80012ba: 4b16 ldr r3, [pc, #88] @ (8001314 ) 80012bc: 2200 movs r2, #0 80012be: 621a str r2, [r3, #32] huart8.Init.ClockPrescaler = UART_PRESCALER_DIV1; 80012c0: 4b14 ldr r3, [pc, #80] @ (8001314 ) 80012c2: 2200 movs r2, #0 80012c4: 625a str r2, [r3, #36] @ 0x24 huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 80012c6: 4b13 ldr r3, [pc, #76] @ (8001314 ) 80012c8: 2200 movs r2, #0 80012ca: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart8) != HAL_OK) 80012cc: 4811 ldr r0, [pc, #68] @ (8001314 ) 80012ce: f00e f8f7 bl 800f4c0 80012d2: 4603 mov r3, r0 80012d4: 2b00 cmp r3, #0 80012d6: d001 beq.n 80012dc { Error_Handler(); 80012d8: f000 fba2 bl 8001a20 } if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 80012dc: 2100 movs r1, #0 80012de: 480d ldr r0, [pc, #52] @ (8001314 ) 80012e0: f010 fe25 bl 8011f2e 80012e4: 4603 mov r3, r0 80012e6: 2b00 cmp r3, #0 80012e8: d001 beq.n 80012ee { Error_Handler(); 80012ea: f000 fb99 bl 8001a20 } if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 80012ee: 2100 movs r1, #0 80012f0: 4808 ldr r0, [pc, #32] @ (8001314 ) 80012f2: f010 fe5a bl 8011faa 80012f6: 4603 mov r3, r0 80012f8: 2b00 cmp r3, #0 80012fa: d001 beq.n 8001300 { Error_Handler(); 80012fc: f000 fb90 bl 8001a20 } if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK) 8001300: 4804 ldr r0, [pc, #16] @ (8001314 ) 8001302: f010 fddb bl 8011ebc 8001306: 4603 mov r3, r0 8001308: 2b00 cmp r3, #0 800130a: d001 beq.n 8001310 { Error_Handler(); 800130c: f000 fb88 bl 8001a20 } /* USER CODE BEGIN UART8_Init 2 */ /* USER CODE END UART8_Init 2 */ } 8001310: bf00 nop 8001312: bd80 pop {r7, pc} 8001314: 24000504 .word 0x24000504 8001318: 40007c00 .word 0x40007c00 0800131c : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 800131c: b580 push {r7, lr} 800131e: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8001320: 4b24 ldr r3, [pc, #144] @ (80013b4 ) 8001322: 4a25 ldr r2, [pc, #148] @ (80013b8 ) 8001324: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 8001326: 4b23 ldr r3, [pc, #140] @ (80013b4 ) 8001328: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800132c: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800132e: 4b21 ldr r3, [pc, #132] @ (80013b4 ) 8001330: 2200 movs r2, #0 8001332: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8001334: 4b1f ldr r3, [pc, #124] @ (80013b4 ) 8001336: 2200 movs r2, #0 8001338: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800133a: 4b1e ldr r3, [pc, #120] @ (80013b4 ) 800133c: 2200 movs r2, #0 800133e: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8001340: 4b1c ldr r3, [pc, #112] @ (80013b4 ) 8001342: 220c movs r2, #12 8001344: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001346: 4b1b ldr r3, [pc, #108] @ (80013b4 ) 8001348: 2200 movs r2, #0 800134a: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800134c: 4b19 ldr r3, [pc, #100] @ (80013b4 ) 800134e: 2200 movs r2, #0 8001350: 61da str r2, [r3, #28] huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8001352: 4b18 ldr r3, [pc, #96] @ (80013b4 ) 8001354: 2200 movs r2, #0 8001356: 621a str r2, [r3, #32] huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8001358: 4b16 ldr r3, [pc, #88] @ (80013b4 ) 800135a: 2200 movs r2, #0 800135c: 625a str r2, [r3, #36] @ 0x24 huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_TXINVERT_INIT; 800135e: 4b15 ldr r3, [pc, #84] @ (80013b4 ) 8001360: 2201 movs r2, #1 8001362: 629a str r2, [r3, #40] @ 0x28 huart1.AdvancedInit.TxPinLevelInvert = UART_ADVFEATURE_TXINV_ENABLE; 8001364: 4b13 ldr r3, [pc, #76] @ (80013b4 ) 8001366: f44f 3200 mov.w r2, #131072 @ 0x20000 800136a: 62da str r2, [r3, #44] @ 0x2c if (HAL_UART_Init(&huart1) != HAL_OK) 800136c: 4811 ldr r0, [pc, #68] @ (80013b4 ) 800136e: f00e f8a7 bl 800f4c0 8001372: 4603 mov r3, r0 8001374: 2b00 cmp r3, #0 8001376: d001 beq.n 800137c { Error_Handler(); 8001378: f000 fb52 bl 8001a20 } if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 800137c: 2100 movs r1, #0 800137e: 480d ldr r0, [pc, #52] @ (80013b4 ) 8001380: f010 fdd5 bl 8011f2e 8001384: 4603 mov r3, r0 8001386: 2b00 cmp r3, #0 8001388: d001 beq.n 800138e { Error_Handler(); 800138a: f000 fb49 bl 8001a20 } if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 800138e: 2100 movs r1, #0 8001390: 4808 ldr r0, [pc, #32] @ (80013b4 ) 8001392: f010 fe0a bl 8011faa 8001396: 4603 mov r3, r0 8001398: 2b00 cmp r3, #0 800139a: d001 beq.n 80013a0 { Error_Handler(); 800139c: f000 fb40 bl 8001a20 } if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) 80013a0: 4804 ldr r0, [pc, #16] @ (80013b4 ) 80013a2: f010 fd8b bl 8011ebc 80013a6: 4603 mov r3, r0 80013a8: 2b00 cmp r3, #0 80013aa: d001 beq.n 80013b0 { Error_Handler(); 80013ac: f000 fb38 bl 8001a20 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 80013b0: bf00 nop 80013b2: bd80 pop {r7, pc} 80013b4: 24000598 .word 0x24000598 80013b8: 40011000 .word 0x40011000 080013bc : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 80013bc: b580 push {r7, lr} 80013be: b082 sub sp, #8 80013c0: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 80013c2: 4b15 ldr r3, [pc, #84] @ (8001418 ) 80013c4: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 80013c8: 4a13 ldr r2, [pc, #76] @ (8001418 ) 80013ca: f043 0301 orr.w r3, r3, #1 80013ce: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 80013d2: 4b11 ldr r3, [pc, #68] @ (8001418 ) 80013d4: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 80013d8: f003 0301 and.w r3, r3, #1 80013dc: 607b str r3, [r7, #4] 80013de: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0); 80013e0: 2200 movs r2, #0 80013e2: 2105 movs r1, #5 80013e4: 200b movs r0, #11 80013e6: f005 f851 bl 800648c HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 80013ea: 200b movs r0, #11 80013ec: f005 f868 bl 80064c0 /* DMA1_Stream1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0); 80013f0: 2200 movs r2, #0 80013f2: 2105 movs r1, #5 80013f4: 200c movs r0, #12 80013f6: f005 f849 bl 800648c HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn); 80013fa: 200c movs r0, #12 80013fc: f005 f860 bl 80064c0 /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0); 8001400: 2200 movs r2, #0 8001402: 2105 movs r1, #5 8001404: 200d movs r0, #13 8001406: f005 f841 bl 800648c HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 800140a: 200d movs r0, #13 800140c: f005 f858 bl 80064c0 } 8001410: bf00 nop 8001412: 3708 adds r7, #8 8001414: 46bd mov sp, r7 8001416: bd80 pop {r7, pc} 8001418: 58024400 .word 0x58024400 0800141c : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 800141c: b580 push {r7, lr} 800141e: b08c sub sp, #48 @ 0x30 8001420: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001422: f107 031c add.w r3, r7, #28 8001426: 2200 movs r2, #0 8001428: 601a str r2, [r3, #0] 800142a: 605a str r2, [r3, #4] 800142c: 609a str r2, [r3, #8] 800142e: 60da str r2, [r3, #12] 8001430: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 8001432: 4b58 ldr r3, [pc, #352] @ (8001594 ) 8001434: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001438: 4a56 ldr r2, [pc, #344] @ (8001594 ) 800143a: f043 0380 orr.w r3, r3, #128 @ 0x80 800143e: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001442: 4b54 ldr r3, [pc, #336] @ (8001594 ) 8001444: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001448: f003 0380 and.w r3, r3, #128 @ 0x80 800144c: 61bb str r3, [r7, #24] 800144e: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOC_CLK_ENABLE(); 8001450: 4b50 ldr r3, [pc, #320] @ (8001594 ) 8001452: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001456: 4a4f ldr r2, [pc, #316] @ (8001594 ) 8001458: f043 0304 orr.w r3, r3, #4 800145c: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001460: 4b4c ldr r3, [pc, #304] @ (8001594 ) 8001462: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001466: f003 0304 and.w r3, r3, #4 800146a: 617b str r3, [r7, #20] 800146c: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 800146e: 4b49 ldr r3, [pc, #292] @ (8001594 ) 8001470: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001474: 4a47 ldr r2, [pc, #284] @ (8001594 ) 8001476: f043 0301 orr.w r3, r3, #1 800147a: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800147e: 4b45 ldr r3, [pc, #276] @ (8001594 ) 8001480: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001484: f003 0301 and.w r3, r3, #1 8001488: 613b str r3, [r7, #16] 800148a: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 800148c: 4b41 ldr r3, [pc, #260] @ (8001594 ) 800148e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001492: 4a40 ldr r2, [pc, #256] @ (8001594 ) 8001494: f043 0302 orr.w r3, r3, #2 8001498: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800149c: 4b3d ldr r3, [pc, #244] @ (8001594 ) 800149e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80014a2: f003 0302 and.w r3, r3, #2 80014a6: 60fb str r3, [r7, #12] 80014a8: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 80014aa: 4b3a ldr r3, [pc, #232] @ (8001594 ) 80014ac: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80014b0: 4a38 ldr r2, [pc, #224] @ (8001594 ) 80014b2: f043 0310 orr.w r3, r3, #16 80014b6: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80014ba: 4b36 ldr r3, [pc, #216] @ (8001594 ) 80014bc: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80014c0: f003 0310 and.w r3, r3, #16 80014c4: 60bb str r3, [r7, #8] 80014c6: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 80014c8: 4b32 ldr r3, [pc, #200] @ (8001594 ) 80014ca: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80014ce: 4a31 ldr r2, [pc, #196] @ (8001594 ) 80014d0: f043 0308 orr.w r3, r3, #8 80014d4: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80014d8: 4b2e ldr r3, [pc, #184] @ (8001594 ) 80014da: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80014de: f003 0308 and.w r3, r3, #8 80014e2: 607b str r3, [r7, #4] 80014e4: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 80014e6: 2200 movs r2, #0 80014e8: f24e 7180 movw r1, #59264 @ 0xe780 80014ec: 482a ldr r0, [pc, #168] @ (8001598 ) 80014ee: f008 fcc7 bl 8009e80 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET); 80014f2: 2200 movs r2, #0 80014f4: 21f0 movs r1, #240 @ 0xf0 80014f6: 4829 ldr r0, [pc, #164] @ (800159c ) 80014f8: f008 fcc2 bl 8009e80 /*Configure GPIO pins : PE7 PE8 PE9 PE10 PE13 PE14 PE15 */ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 80014fc: f24e 7380 movw r3, #59264 @ 0xe780 8001500: 61fb str r3, [r7, #28] |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001502: 2301 movs r3, #1 8001504: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001506: 2300 movs r3, #0 8001508: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800150a: 2300 movs r3, #0 800150c: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800150e: f107 031c add.w r3, r7, #28 8001512: 4619 mov r1, r3 8001514: 4820 ldr r0, [pc, #128] @ (8001598 ) 8001516: f008 faeb bl 8009af0 /*Configure GPIO pins : PD8 PD9 PD10 PD11 PD12 PD13 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 800151a: f44f 537c mov.w r3, #16128 @ 0x3f00 800151e: 61fb str r3, [r7, #28] |GPIO_PIN_12|GPIO_PIN_13; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 8001520: f44f 1344 mov.w r3, #3211264 @ 0x310000 8001524: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001526: 2300 movs r3, #0 8001528: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800152a: f107 031c add.w r3, r7, #28 800152e: 4619 mov r1, r3 8001530: 481a ldr r0, [pc, #104] @ (800159c ) 8001532: f008 fadd bl 8009af0 /*Configure GPIO pin : PD3 */ GPIO_InitStruct.Pin = GPIO_PIN_3; 8001536: 2308 movs r3, #8 8001538: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800153a: 2300 movs r3, #0 800153c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800153e: 2300 movs r3, #0 8001540: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001542: f107 031c add.w r3, r7, #28 8001546: 4619 mov r1, r3 8001548: 4814 ldr r0, [pc, #80] @ (800159c ) 800154a: f008 fad1 bl 8009af0 /*Configure GPIO pins : PD4 PD5 PD6 PD7 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; 800154e: 23f0 movs r3, #240 @ 0xf0 8001550: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001552: 2301 movs r3, #1 8001554: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001556: 2300 movs r3, #0 8001558: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800155a: 2300 movs r3, #0 800155c: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800155e: f107 031c add.w r3, r7, #28 8001562: 4619 mov r1, r3 8001564: 480d ldr r0, [pc, #52] @ (800159c ) 8001566: f008 fac3 bl 8009af0 /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0); 800156a: 2200 movs r2, #0 800156c: 2105 movs r1, #5 800156e: 2017 movs r0, #23 8001570: f004 ff8c bl 800648c HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); 8001574: 2017 movs r0, #23 8001576: f004 ffa3 bl 80064c0 HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0); 800157a: 2200 movs r2, #0 800157c: 2105 movs r1, #5 800157e: 2028 movs r0, #40 @ 0x28 8001580: f004 ff84 bl 800648c HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); 8001584: 2028 movs r0, #40 @ 0x28 8001586: f004 ff9b bl 80064c0 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 800158a: bf00 nop 800158c: 3730 adds r7, #48 @ 0x30 800158e: 46bd mov sp, r7 8001590: bd80 pop {r7, pc} 8001592: bf00 nop 8001594: 58024400 .word 0x58024400 8001598: 58021000 .word 0x58021000 800159c: 58020c00 .word 0x58020c00 080015a0 : /* USER CODE BEGIN 4 */ void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { 80015a0: b580 push {r7, lr} 80015a2: b08e sub sp, #56 @ 0x38 80015a4: af00 add r7, sp, #0 80015a6: 6078 str r0, [r7, #4] if(hadc->Instance == ADC1) 80015a8: 687b ldr r3, [r7, #4] 80015aa: 681b ldr r3, [r3, #0] 80015ac: 4a67 ldr r2, [pc, #412] @ (800174c ) 80015ae: 4293 cmp r3, r2 80015b0: d13f bne.n 8001632 { DbgLEDToggle(DBG_LED4); 80015b2: 2080 movs r0, #128 @ 0x80 80015b4: f001 f916 bl 80027e4 SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc1Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 80015b8: 4b65 ldr r3, [pc, #404] @ (8001750 ) 80015ba: f023 031f bic.w r3, r3, #31 80015be: 637b str r3, [r7, #52] @ 0x34 80015c0: 2320 movs r3, #32 80015c2: 633b str r3, [r7, #48] @ 0x30 \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { 80015c4: 6b3b ldr r3, [r7, #48] @ 0x30 80015c6: 2b00 cmp r3, #0 80015c8: dd1d ble.n 8001606 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 80015ca: 6b7b ldr r3, [r7, #52] @ 0x34 80015cc: f003 021f and.w r2, r3, #31 80015d0: 6b3b ldr r3, [r7, #48] @ 0x30 80015d2: 4413 add r3, r2 80015d4: 62fb str r3, [r7, #44] @ 0x2c uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 80015d6: 6b7b ldr r3, [r7, #52] @ 0x34 80015d8: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("dsb 0xF":::"memory"); 80015da: f3bf 8f4f dsb sy } 80015de: bf00 nop __DSB(); do { SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 80015e0: 4a5c ldr r2, [pc, #368] @ (8001754 ) 80015e2: 6abb ldr r3, [r7, #40] @ 0x28 80015e4: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 80015e8: 6abb ldr r3, [r7, #40] @ 0x28 80015ea: 3320 adds r3, #32 80015ec: 62bb str r3, [r7, #40] @ 0x28 op_size -= __SCB_DCACHE_LINE_SIZE; 80015ee: 6afb ldr r3, [r7, #44] @ 0x2c 80015f0: 3b20 subs r3, #32 80015f2: 62fb str r3, [r7, #44] @ 0x2c } while ( op_size > 0 ); 80015f4: 6afb ldr r3, [r7, #44] @ 0x2c 80015f6: 2b00 cmp r3, #0 80015f8: dcf2 bgt.n 80015e0 __ASM volatile ("dsb 0xF":::"memory"); 80015fa: f3bf 8f4f dsb sy } 80015fe: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8001600: f3bf 8f6f isb sy } 8001604: bf00 nop __DSB(); __ISB(); } #endif } 8001606: bf00 nop if(adc1MeasDataQueue != NULL) 8001608: 4b53 ldr r3, [pc, #332] @ (8001758 ) 800160a: 681b ldr r3, [r3, #0] 800160c: 2b00 cmp r3, #0 800160e: d006 beq.n 800161e { osMessageQueuePut(adc1MeasDataQueue, &adc1Data, 0, 0); 8001610: 4b51 ldr r3, [pc, #324] @ (8001758 ) 8001612: 6818 ldr r0, [r3, #0] 8001614: 2300 movs r3, #0 8001616: 2200 movs r2, #0 8001618: 494d ldr r1, [pc, #308] @ (8001750 ) 800161a: f011 f957 bl 80128cc } if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK) 800161e: 2207 movs r2, #7 8001620: 494b ldr r1, [pc, #300] @ (8001750 ) 8001622: 484e ldr r0, [pc, #312] @ (800175c ) 8001624: f003 fe20 bl 8005268 8001628: 4603 mov r3, r0 800162a: 2b00 cmp r3, #0 800162c: d001 beq.n 8001632 { Error_Handler(); 800162e: f000 f9f7 bl 8001a20 } } if(hadc->Instance == ADC2) 8001632: 687b ldr r3, [r7, #4] 8001634: 681b ldr r3, [r3, #0] 8001636: 4a4a ldr r2, [pc, #296] @ (8001760 ) 8001638: 4293 cmp r3, r2 800163a: d13c bne.n 80016b6 { SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc2Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 800163c: 4b49 ldr r3, [pc, #292] @ (8001764 ) 800163e: f023 031f bic.w r3, r3, #31 8001642: 627b str r3, [r7, #36] @ 0x24 8001644: 2320 movs r3, #32 8001646: 623b str r3, [r7, #32] if ( dsize > 0 ) { 8001648: 6a3b ldr r3, [r7, #32] 800164a: 2b00 cmp r3, #0 800164c: dd1d ble.n 800168a int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 800164e: 6a7b ldr r3, [r7, #36] @ 0x24 8001650: f003 021f and.w r2, r3, #31 8001654: 6a3b ldr r3, [r7, #32] 8001656: 4413 add r3, r2 8001658: 61fb str r3, [r7, #28] uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 800165a: 6a7b ldr r3, [r7, #36] @ 0x24 800165c: 61bb str r3, [r7, #24] __ASM volatile ("dsb 0xF":::"memory"); 800165e: f3bf 8f4f dsb sy } 8001662: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 8001664: 4a3b ldr r2, [pc, #236] @ (8001754 ) 8001666: 69bb ldr r3, [r7, #24] 8001668: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 800166c: 69bb ldr r3, [r7, #24] 800166e: 3320 adds r3, #32 8001670: 61bb str r3, [r7, #24] op_size -= __SCB_DCACHE_LINE_SIZE; 8001672: 69fb ldr r3, [r7, #28] 8001674: 3b20 subs r3, #32 8001676: 61fb str r3, [r7, #28] } while ( op_size > 0 ); 8001678: 69fb ldr r3, [r7, #28] 800167a: 2b00 cmp r3, #0 800167c: dcf2 bgt.n 8001664 __ASM volatile ("dsb 0xF":::"memory"); 800167e: f3bf 8f4f dsb sy } 8001682: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8001684: f3bf 8f6f isb sy } 8001688: bf00 nop } 800168a: bf00 nop if(adc2MeasDataQueue != NULL) 800168c: 4b36 ldr r3, [pc, #216] @ (8001768 ) 800168e: 681b ldr r3, [r3, #0] 8001690: 2b00 cmp r3, #0 8001692: d006 beq.n 80016a2 { osMessageQueuePut(adc2MeasDataQueue, &adc2Data, 0, 0); 8001694: 4b34 ldr r3, [pc, #208] @ (8001768 ) 8001696: 6818 ldr r0, [r3, #0] 8001698: 2300 movs r3, #0 800169a: 2200 movs r2, #0 800169c: 4931 ldr r1, [pc, #196] @ (8001764 ) 800169e: f011 f915 bl 80128cc } if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK) 80016a2: 2203 movs r2, #3 80016a4: 492f ldr r1, [pc, #188] @ (8001764 ) 80016a6: 4831 ldr r0, [pc, #196] @ (800176c ) 80016a8: f003 fdde bl 8005268 80016ac: 4603 mov r3, r0 80016ae: 2b00 cmp r3, #0 80016b0: d001 beq.n 80016b6 { Error_Handler(); 80016b2: f000 f9b5 bl 8001a20 } } if(hadc->Instance == ADC3) 80016b6: 687b ldr r3, [r7, #4] 80016b8: 681b ldr r3, [r3, #0] 80016ba: 4a2d ldr r2, [pc, #180] @ (8001770 ) 80016bc: 4293 cmp r3, r2 80016be: d13c bne.n 800173a { SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc3Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 80016c0: 4b2c ldr r3, [pc, #176] @ (8001774 ) 80016c2: f023 031f bic.w r3, r3, #31 80016c6: 617b str r3, [r7, #20] 80016c8: 2320 movs r3, #32 80016ca: 613b str r3, [r7, #16] if ( dsize > 0 ) { 80016cc: 693b ldr r3, [r7, #16] 80016ce: 2b00 cmp r3, #0 80016d0: dd1d ble.n 800170e int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 80016d2: 697b ldr r3, [r7, #20] 80016d4: f003 021f and.w r2, r3, #31 80016d8: 693b ldr r3, [r7, #16] 80016da: 4413 add r3, r2 80016dc: 60fb str r3, [r7, #12] uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 80016de: 697b ldr r3, [r7, #20] 80016e0: 60bb str r3, [r7, #8] __ASM volatile ("dsb 0xF":::"memory"); 80016e2: f3bf 8f4f dsb sy } 80016e6: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 80016e8: 4a1a ldr r2, [pc, #104] @ (8001754 ) 80016ea: 68bb ldr r3, [r7, #8] 80016ec: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 80016f0: 68bb ldr r3, [r7, #8] 80016f2: 3320 adds r3, #32 80016f4: 60bb str r3, [r7, #8] op_size -= __SCB_DCACHE_LINE_SIZE; 80016f6: 68fb ldr r3, [r7, #12] 80016f8: 3b20 subs r3, #32 80016fa: 60fb str r3, [r7, #12] } while ( op_size > 0 ); 80016fc: 68fb ldr r3, [r7, #12] 80016fe: 2b00 cmp r3, #0 8001700: dcf2 bgt.n 80016e8 __ASM volatile ("dsb 0xF":::"memory"); 8001702: f3bf 8f4f dsb sy } 8001706: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8001708: f3bf 8f6f isb sy } 800170c: bf00 nop } 800170e: bf00 nop if(adc3MeasDataQueue != NULL) 8001710: 4b19 ldr r3, [pc, #100] @ (8001778 ) 8001712: 681b ldr r3, [r3, #0] 8001714: 2b00 cmp r3, #0 8001716: d006 beq.n 8001726 { osMessageQueuePut(adc3MeasDataQueue, &adc3Data, 0, 0); 8001718: 4b17 ldr r3, [pc, #92] @ (8001778 ) 800171a: 6818 ldr r0, [r3, #0] 800171c: 2300 movs r3, #0 800171e: 2200 movs r2, #0 8001720: 4914 ldr r1, [pc, #80] @ (8001774 ) 8001722: f011 f8d3 bl 80128cc } if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK) 8001726: 2205 movs r2, #5 8001728: 4912 ldr r1, [pc, #72] @ (8001774 ) 800172a: 4814 ldr r0, [pc, #80] @ (800177c ) 800172c: f003 fd9c bl 8005268 8001730: 4603 mov r3, r0 8001732: 2b00 cmp r3, #0 8001734: d001 beq.n 800173a { Error_Handler(); 8001736: f000 f973 bl 8001a20 } }osTimerStop (debugLedTimerHandle); 800173a: 4b11 ldr r3, [pc, #68] @ (8001780 ) 800173c: 681b ldr r3, [r3, #0] 800173e: 4618 mov r0, r3 8001740: f010 ff0c bl 801255c } 8001744: bf00 nop 8001746: 3738 adds r7, #56 @ 0x38 8001748: 46bd mov sp, r7 800174a: bd80 pop {r7, pc} 800174c: 40022000 .word 0x40022000 8001750: 240000e0 .word 0x240000e0 8001754: e000ed00 .word 0xe000ed00 8001758: 24000738 .word 0x24000738 800175c: 24000140 .word 0x24000140 8001760: 40022100 .word 0x40022100 8001764: 24000100 .word 0x24000100 8001768: 2400073c .word 0x2400073c 800176c: 240001a4 .word 0x240001a4 8001770: 58026000 .word 0x58026000 8001774: 24000120 .word 0x24000120 8001778: 24000740 .word 0x24000740 800177c: 24000208 .word 0x24000208 8001780: 24000630 .word 0x24000630 08001784 : * @param argument: Not used * @retval None */ /* USER CODE END Header_StartDefaultTask */ void StartDefaultTask(void *argument) { 8001784: b580 push {r7, lr} 8001786: b082 sub sp, #8 8001788: af00 add r7, sp, #0 800178a: 6078 str r0, [r7, #4] /* USER CODE BEGIN 5 */ SelectCurrentSensorGain(CurrentSensorL1, csGain3); 800178c: 2102 movs r1, #2 800178e: 2000 movs r0, #0 8001790: f001 f846 bl 8002820 SelectCurrentSensorGain(CurrentSensorL2, csGain3); 8001794: 2102 movs r1, #2 8001796: 2001 movs r0, #1 8001798: f001 f842 bl 8002820 SelectCurrentSensorGain(CurrentSensorL3, csGain3); 800179c: 2102 movs r1, #2 800179e: 2002 movs r0, #2 80017a0: f001 f83e bl 8002820 EnableCurrentSensors(); 80017a4: f001 f830 bl 8002808 osDelay(pdMS_TO_TICKS(1000)); 80017a8: f44f 707a mov.w r0, #1000 @ 0x3e8 80017ac: f010 fdfb bl 80123a6 if(HAL_TIM_Base_Start(&htim2) != HAL_OK) 80017b0: 4834 ldr r0, [pc, #208] @ (8001884 ) 80017b2: f00c fac1 bl 800dd38 80017b6: 4603 mov r3, r0 80017b8: 2b00 cmp r3, #0 80017ba: d001 beq.n 80017c0 { Error_Handler(); 80017bc: f000 f930 bl 8001a20 } // if(HAL_ADC_Start_IT(&hadc1) != HAL_OK) // { // Error_Handler(); // } if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK) 80017c0: 2207 movs r2, #7 80017c2: 4931 ldr r1, [pc, #196] @ (8001888 ) 80017c4: 4831 ldr r0, [pc, #196] @ (800188c ) 80017c6: f003 fd4f bl 8005268 80017ca: 4603 mov r3, r0 80017cc: 2b00 cmp r3, #0 80017ce: d001 beq.n 80017d4 { Error_Handler(); 80017d0: f000 f926 bl 8001a20 } if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK) 80017d4: 2203 movs r2, #3 80017d6: 492e ldr r1, [pc, #184] @ (8001890 ) 80017d8: 482e ldr r0, [pc, #184] @ (8001894 ) 80017da: f003 fd45 bl 8005268 80017de: 4603 mov r3, r0 80017e0: 2b00 cmp r3, #0 80017e2: d001 beq.n 80017e8 { Error_Handler(); 80017e4: f000 f91c bl 8001a20 } if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK) 80017e8: 2205 movs r2, #5 80017ea: 492b ldr r1, [pc, #172] @ (8001898 ) 80017ec: 482b ldr r0, [pc, #172] @ (800189c ) 80017ee: f003 fd3b bl 8005268 80017f2: 4603 mov r3, r0 80017f4: 2b00 cmp r3, #0 80017f6: d001 beq.n 80017fc { Error_Handler(); 80017f8: f000 f912 bl 8001a20 } /* Infinite loop */ for(;;) { osDelay(pdMS_TO_TICKS(100)); 80017fc: 2064 movs r0, #100 @ 0x64 80017fe: f010 fdd2 bl 80123a6 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 8001802: 2100 movs r1, #0 8001804: 4826 ldr r0, [pc, #152] @ (80018a0 ) 8001806: f00d f8b7 bl 800e978 800180a: 4603 mov r3, r0 800180c: 2b01 cmp r3, #1 800180e: d118 bne.n 8001842 HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_2) == HAL_TIM_CHANNEL_STATE_READY) 8001810: 2104 movs r1, #4 8001812: 4823 ldr r0, [pc, #140] @ (80018a0 ) 8001814: f00d f8b0 bl 800e978 8001818: 4603 mov r3, r0 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 800181a: 2b01 cmp r3, #1 800181c: d111 bne.n 8001842 { if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 800181e: 4b21 ldr r3, [pc, #132] @ (80018a4 ) 8001820: 681b ldr r3, [r3, #0] 8001822: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001826: 4618 mov r0, r3 8001828: f010 ff55 bl 80126d6 800182c: 4603 mov r3, r0 800182e: 2b00 cmp r3, #0 8001830: d107 bne.n 8001842 { sensorsInfo.motorXStatus = 0; 8001832: 4b1d ldr r3, [pc, #116] @ (80018a8 ) 8001834: 2200 movs r2, #0 8001836: 741a strb r2, [r3, #16] osMutexRelease(sensorsInfoMutex); 8001838: 4b1a ldr r3, [pc, #104] @ (80018a4 ) 800183a: 681b ldr r3, [r3, #0] 800183c: 4618 mov r0, r3 800183e: f010 ff95 bl 801276c } } if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 8001842: 2108 movs r1, #8 8001844: 4816 ldr r0, [pc, #88] @ (80018a0 ) 8001846: f00d f897 bl 800e978 800184a: 4603 mov r3, r0 800184c: 2b01 cmp r3, #1 800184e: d1d5 bne.n 80017fc HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_4) == HAL_TIM_CHANNEL_STATE_READY) 8001850: 210c movs r1, #12 8001852: 4813 ldr r0, [pc, #76] @ (80018a0 ) 8001854: f00d f890 bl 800e978 8001858: 4603 mov r3, r0 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 800185a: 2b01 cmp r3, #1 800185c: d1ce bne.n 80017fc { if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 800185e: 4b11 ldr r3, [pc, #68] @ (80018a4 ) 8001860: 681b ldr r3, [r3, #0] 8001862: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001866: 4618 mov r0, r3 8001868: f010 ff35 bl 80126d6 800186c: 4603 mov r3, r0 800186e: 2b00 cmp r3, #0 8001870: d1c4 bne.n 80017fc { sensorsInfo.motorYStatus = 0; 8001872: 4b0d ldr r3, [pc, #52] @ (80018a8 ) 8001874: 2200 movs r2, #0 8001876: 745a strb r2, [r3, #17] osMutexRelease(sensorsInfoMutex); 8001878: 4b0a ldr r3, [pc, #40] @ (80018a4 ) 800187a: 681b ldr r3, [r3, #0] 800187c: 4618 mov r0, r3 800187e: f010 ff75 bl 801276c osDelay(pdMS_TO_TICKS(100)); 8001882: e7bb b.n 80017fc 8001884: 2400046c .word 0x2400046c 8001888: 240000e0 .word 0x240000e0 800188c: 24000140 .word 0x24000140 8001890: 24000100 .word 0x24000100 8001894: 240001a4 .word 0x240001a4 8001898: 24000120 .word 0x24000120 800189c: 24000208 .word 0x24000208 80018a0: 240004b8 .word 0x240004b8 80018a4: 24000750 .word 0x24000750 80018a8: 24000794 .word 0x24000794 080018ac : /* USER CODE END 5 */ } /* debugLedTimerCallback function */ void debugLedTimerCallback(void *argument) { 80018ac: b580 push {r7, lr} 80018ae: b082 sub sp, #8 80018b0: af00 add r7, sp, #0 80018b2: 6078 str r0, [r7, #4] /* USER CODE BEGIN debugLedTimerCallback */ DbgLEDOff (DBG_LED1); 80018b4: 2010 movs r0, #16 80018b6: f000 ff83 bl 80027c0 /* USER CODE END debugLedTimerCallback */ } 80018ba: bf00 nop 80018bc: 3708 adds r7, #8 80018be: 46bd mov sp, r7 80018c0: bd80 pop {r7, pc} ... 080018c4 : /* fanTimerCallback function */ void fanTimerCallback(void *argument) { 80018c4: b580 push {r7, lr} 80018c6: b082 sub sp, #8 80018c8: af00 add r7, sp, #0 80018ca: 6078 str r0, [r7, #4] /* USER CODE BEGIN fanTimerCallback */ HAL_TIM_PWM_Stop(&htim1, TIM_CHANNEL_2); 80018cc: 2104 movs r1, #4 80018ce: 4803 ldr r0, [pc, #12] @ (80018dc ) 80018d0: f00c fc80 bl 800e1d4 /* USER CODE END fanTimerCallback */ } 80018d4: bf00 nop 80018d6: 3708 adds r7, #8 80018d8: 46bd mov sp, r7 80018da: bd80 pop {r7, pc} 80018dc: 24000420 .word 0x24000420 080018e0 : /* motorXTimerCallback function */ void motorXTimerCallback(void *argument) { 80018e0: b580 push {r7, lr} 80018e2: b084 sub sp, #16 80018e4: af02 add r7, sp, #8 80018e6: 6078 str r0, [r7, #4] /* USER CODE BEGIN motorXTimerCallback */ motorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, HiZ, 0); 80018e8: 2300 movs r3, #0 80018ea: 9301 str r3, [sp, #4] 80018ec: 2300 movs r3, #0 80018ee: 9300 str r3, [sp, #0] 80018f0: 2304 movs r3, #4 80018f2: 2200 movs r2, #0 80018f4: 4907 ldr r1, [pc, #28] @ (8001914 ) 80018f6: 4808 ldr r0, [pc, #32] @ (8001918 ) 80018f8: f001 f917 bl 8002b2a HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_1); 80018fc: 2100 movs r1, #0 80018fe: 4806 ldr r0, [pc, #24] @ (8001918 ) 8001900: f00c fc68 bl 800e1d4 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_2); 8001904: 2104 movs r1, #4 8001906: 4804 ldr r0, [pc, #16] @ (8001918 ) 8001908: f00c fc64 bl 800e1d4 /* USER CODE END motorXTimerCallback */ } 800190c: bf00 nop 800190e: 3708 adds r7, #8 8001910: 46bd mov sp, r7 8001912: bd80 pop {r7, pc} 8001914: 2400070c .word 0x2400070c 8001918: 240004b8 .word 0x240004b8 0800191c : /* motorYTimerCallback function */ void motorYTimerCallback(void *argument) { 800191c: b580 push {r7, lr} 800191e: b084 sub sp, #16 8001920: af02 add r7, sp, #8 8001922: 6078 str r0, [r7, #4] /* USER CODE BEGIN motorYTimerCallback */ motorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, HiZ, 0); 8001924: 2300 movs r3, #0 8001926: 9301 str r3, [sp, #4] 8001928: 2300 movs r3, #0 800192a: 9300 str r3, [sp, #0] 800192c: 230c movs r3, #12 800192e: 2208 movs r2, #8 8001930: 4907 ldr r1, [pc, #28] @ (8001950 ) 8001932: 4808 ldr r0, [pc, #32] @ (8001954 ) 8001934: f001 f8f9 bl 8002b2a HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_3); 8001938: 2108 movs r1, #8 800193a: 4806 ldr r0, [pc, #24] @ (8001954 ) 800193c: f00c fc4a bl 800e1d4 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_4); 8001940: 210c movs r1, #12 8001942: 4804 ldr r0, [pc, #16] @ (8001954 ) 8001944: f00c fc46 bl 800e1d4 /* USER CODE END motorYTimerCallback */ } 8001948: bf00 nop 800194a: 3708 adds r7, #8 800194c: 46bd mov sp, r7 800194e: bd80 pop {r7, pc} 8001950: 2400070c .word 0x2400070c 8001954: 240004b8 .word 0x240004b8 08001958 : /* MPU Configuration */ void MPU_Config(void) { 8001958: b580 push {r7, lr} 800195a: b084 sub sp, #16 800195c: af00 add r7, sp, #0 MPU_Region_InitTypeDef MPU_InitStruct = {0}; 800195e: 463b mov r3, r7 8001960: 2200 movs r2, #0 8001962: 601a str r2, [r3, #0] 8001964: 605a str r2, [r3, #4] 8001966: 609a str r2, [r3, #8] 8001968: 60da str r2, [r3, #12] /* Disables the MPU */ HAL_MPU_Disable(); 800196a: f004 fdb7 bl 80064dc /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; 800196e: 2301 movs r3, #1 8001970: 703b strb r3, [r7, #0] MPU_InitStruct.Number = MPU_REGION_NUMBER0; 8001972: 2300 movs r3, #0 8001974: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x0; 8001976: 2300 movs r3, #0 8001978: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; 800197a: 231f movs r3, #31 800197c: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x87; 800197e: 2387 movs r3, #135 @ 0x87 8001980: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8001982: 2300 movs r3, #0 8001984: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; 8001986: 2300 movs r3, #0 8001988: 72fb strb r3, [r7, #11] MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; 800198a: 2301 movs r3, #1 800198c: 733b strb r3, [r7, #12] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 800198e: 2301 movs r3, #1 8001990: 737b strb r3, [r7, #13] MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; 8001992: 2300 movs r3, #0 8001994: 73bb strb r3, [r7, #14] MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; 8001996: 2300 movs r3, #0 8001998: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 800199a: 463b mov r3, r7 800199c: 4618 mov r0, r3 800199e: f004 fdd5 bl 800654c /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER1; 80019a2: 2301 movs r3, #1 80019a4: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24020000; 80019a6: 4b13 ldr r3, [pc, #76] @ (80019f4 ) 80019a8: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_128KB; 80019aa: 2310 movs r3, #16 80019ac: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x0; 80019ae: 2300 movs r3, #0 80019b0: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; 80019b2: 2301 movs r3, #1 80019b4: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; 80019b6: 2303 movs r3, #3 80019b8: 72fb strb r3, [r7, #11] MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 80019ba: 2300 movs r3, #0 80019bc: 737b strb r3, [r7, #13] HAL_MPU_ConfigRegion(&MPU_InitStruct); 80019be: 463b mov r3, r7 80019c0: 4618 mov r0, r3 80019c2: f004 fdc3 bl 800654c /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER2; 80019c6: 2302 movs r3, #2 80019c8: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24040000; 80019ca: 4b0b ldr r3, [pc, #44] @ (80019f8 ) 80019cc: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_512B; 80019ce: 2308 movs r3, #8 80019d0: 723b strb r3, [r7, #8] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 80019d2: 2300 movs r3, #0 80019d4: 72bb strb r3, [r7, #10] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 80019d6: 2301 movs r3, #1 80019d8: 737b strb r3, [r7, #13] MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; 80019da: 2301 movs r3, #1 80019dc: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 80019de: 463b mov r3, r7 80019e0: 4618 mov r0, r3 80019e2: f004 fdb3 bl 800654c /* Enables the MPU */ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); 80019e6: 2004 movs r0, #4 80019e8: f004 fd90 bl 800650c } 80019ec: bf00 nop 80019ee: 3710 adds r7, #16 80019f0: 46bd mov sp, r7 80019f2: bd80 pop {r7, pc} 80019f4: 24020000 .word 0x24020000 80019f8: 24040000 .word 0x24040000 080019fc : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 80019fc: b580 push {r7, lr} 80019fe: b082 sub sp, #8 8001a00: af00 add r7, sp, #0 8001a02: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM6) { 8001a04: 687b ldr r3, [r7, #4] 8001a06: 681b ldr r3, [r3, #0] 8001a08: 4a04 ldr r2, [pc, #16] @ (8001a1c ) 8001a0a: 4293 cmp r3, r2 8001a0c: d101 bne.n 8001a12 HAL_IncTick(); 8001a0e: f003 f815 bl 8004a3c { } /* USER CODE END Callback 1 */ } 8001a12: bf00 nop 8001a14: 3708 adds r7, #8 8001a16: 46bd mov sp, r7 8001a18: bd80 pop {r7, pc} 8001a1a: bf00 nop 8001a1c: 40001000 .word 0x40001000 08001a20 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001a20: b480 push {r7} 8001a22: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 8001a24: b672 cpsid i } 8001a26: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8001a28: bf00 nop 8001a2a: e7fd b.n 8001a28 08001a2c : extern TIM_OC_InitTypeDef motorXYTimerConfigOC; extern osTimerId_t motorXTimerHandle; extern osTimerId_t motorYTimerHandle; void MeasTasksInit (void) { 8001a2c: b580 push {r7, lr} 8001a2e: b0a4 sub sp, #144 @ 0x90 8001a30: af00 add r7, sp, #0 vRefmVMutex = osMutexNew (NULL); 8001a32: 2000 movs r0, #0 8001a34: f010 fdc9 bl 80125ca 8001a38: 4603 mov r3, r0 8001a3a: 4a48 ldr r2, [pc, #288] @ (8001b5c ) 8001a3c: 6013 str r3, [r2, #0] resMeasurementsMutex = osMutexNew (NULL); 8001a3e: 2000 movs r0, #0 8001a40: f010 fdc3 bl 80125ca 8001a44: 4603 mov r3, r0 8001a46: 4a46 ldr r2, [pc, #280] @ (8001b60 ) 8001a48: 6013 str r3, [r2, #0] sensorsInfoMutex = osMutexNew (NULL); 8001a4a: 2000 movs r0, #0 8001a4c: f010 fdbd bl 80125ca 8001a50: 4603 mov r3, r0 8001a52: 4a44 ldr r2, [pc, #272] @ (8001b64 ) 8001a54: 6013 str r3, [r2, #0] ILxRefMutex = osMutexNew (NULL); 8001a56: 2000 movs r0, #0 8001a58: f010 fdb7 bl 80125ca 8001a5c: 4603 mov r3, r0 8001a5e: 4a42 ldr r2, [pc, #264] @ (8001b68 ) 8001a60: 6013 str r3, [r2, #0] adc1MeasDataQueue = osMessageQueueNew (8, sizeof (ADC1_Data), NULL); 8001a62: 2200 movs r2, #0 8001a64: 2120 movs r1, #32 8001a66: 2008 movs r0, #8 8001a68: f010 febd bl 80127e6 8001a6c: 4603 mov r3, r0 8001a6e: 4a3f ldr r2, [pc, #252] @ (8001b6c ) 8001a70: 6013 str r3, [r2, #0] adc2MeasDataQueue = osMessageQueueNew (8, sizeof (ADC2_Data), NULL); 8001a72: 2200 movs r2, #0 8001a74: 2120 movs r1, #32 8001a76: 2008 movs r0, #8 8001a78: f010 feb5 bl 80127e6 8001a7c: 4603 mov r3, r0 8001a7e: 4a3c ldr r2, [pc, #240] @ (8001b70 ) 8001a80: 6013 str r3, [r2, #0] adc3MeasDataQueue = osMessageQueueNew (8, sizeof (ADC3_Data), NULL); 8001a82: 2200 movs r2, #0 8001a84: 2120 movs r1, #32 8001a86: 2008 movs r0, #8 8001a88: f010 fead bl 80127e6 8001a8c: 4603 mov r3, r0 8001a8e: 4a39 ldr r2, [pc, #228] @ (8001b74 ) 8001a90: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttradc1MeasTask = { 0 }; 8001a92: f107 036c add.w r3, r7, #108 @ 0x6c 8001a96: 2224 movs r2, #36 @ 0x24 8001a98: 2100 movs r1, #0 8001a9a: 4618 mov r0, r3 8001a9c: f014 fe5b bl 8016756 osThreadAttr_t osThreadAttradc2MeasTask = { 0 }; 8001aa0: f107 0348 add.w r3, r7, #72 @ 0x48 8001aa4: 2224 movs r2, #36 @ 0x24 8001aa6: 2100 movs r1, #0 8001aa8: 4618 mov r0, r3 8001aaa: f014 fe54 bl 8016756 osThreadAttr_t osThreadAttradc3MeasTask = { 0 }; 8001aae: f107 0324 add.w r3, r7, #36 @ 0x24 8001ab2: 2224 movs r2, #36 @ 0x24 8001ab4: 2100 movs r1, #0 8001ab6: 4618 mov r0, r3 8001ab8: f014 fe4d bl 8016756 osThreadAttradc1MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001abc: f44f 6380 mov.w r3, #1024 @ 0x400 8001ac0: f8c7 3080 str.w r3, [r7, #128] @ 0x80 osThreadAttradc1MeasTask.priority = (osPriority_t)osPriorityRealtime; 8001ac4: 2330 movs r3, #48 @ 0x30 8001ac6: f8c7 3084 str.w r3, [r7, #132] @ 0x84 osThreadAttradc2MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001aca: f44f 6380 mov.w r3, #1024 @ 0x400 8001ace: 65fb str r3, [r7, #92] @ 0x5c osThreadAttradc2MeasTask.priority = (osPriority_t)osPriorityRealtime; 8001ad0: 2330 movs r3, #48 @ 0x30 8001ad2: 663b str r3, [r7, #96] @ 0x60 osThreadAttradc3MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001ad4: f44f 6380 mov.w r3, #1024 @ 0x400 8001ad8: 63bb str r3, [r7, #56] @ 0x38 osThreadAttradc3MeasTask.priority = (osPriority_t)osPriorityNormal; 8001ada: 2318 movs r3, #24 8001adc: 63fb str r3, [r7, #60] @ 0x3c adc1MeasTaskHandle = osThreadNew (ADC1MeasTask, NULL, &osThreadAttradc1MeasTask); 8001ade: f107 036c add.w r3, r7, #108 @ 0x6c 8001ae2: 461a mov r2, r3 8001ae4: 2100 movs r1, #0 8001ae6: 4824 ldr r0, [pc, #144] @ (8001b78 ) 8001ae8: f010 fbca bl 8012280 8001aec: 4603 mov r3, r0 8001aee: 4a23 ldr r2, [pc, #140] @ (8001b7c ) 8001af0: 6013 str r3, [r2, #0] adc2MeasTaskHandle = osThreadNew (ADC2MeasTask, NULL, &osThreadAttradc2MeasTask); 8001af2: f107 0348 add.w r3, r7, #72 @ 0x48 8001af6: 461a mov r2, r3 8001af8: 2100 movs r1, #0 8001afa: 4821 ldr r0, [pc, #132] @ (8001b80 ) 8001afc: f010 fbc0 bl 8012280 8001b00: 4603 mov r3, r0 8001b02: 4a20 ldr r2, [pc, #128] @ (8001b84 ) 8001b04: 6013 str r3, [r2, #0] adc3MeasTaskHandle = osThreadNew (ADC3MeasTask, NULL, &osThreadAttradc3MeasTask); 8001b06: f107 0324 add.w r3, r7, #36 @ 0x24 8001b0a: 461a mov r2, r3 8001b0c: 2100 movs r1, #0 8001b0e: 481e ldr r0, [pc, #120] @ (8001b88 ) 8001b10: f010 fbb6 bl 8012280 8001b14: 4603 mov r3, r0 8001b16: 4a1d ldr r2, [pc, #116] @ (8001b8c ) 8001b18: 6013 str r3, [r2, #0] limiterSwitchDataQueue = osMessageQueueNew (8, sizeof (LimiterSwitchData), NULL); 8001b1a: 2200 movs r2, #0 8001b1c: 2104 movs r1, #4 8001b1e: 2008 movs r0, #8 8001b20: f010 fe61 bl 80127e6 8001b24: 4603 mov r3, r0 8001b26: 4a1a ldr r2, [pc, #104] @ (8001b90 ) 8001b28: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttradc1LimiterSwitchTask = { 0 }; 8001b2a: 463b mov r3, r7 8001b2c: 2224 movs r2, #36 @ 0x24 8001b2e: 2100 movs r1, #0 8001b30: 4618 mov r0, r3 8001b32: f014 fe10 bl 8016756 osThreadAttradc1LimiterSwitchTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001b36: f44f 6380 mov.w r3, #1024 @ 0x400 8001b3a: 617b str r3, [r7, #20] osThreadAttradc1LimiterSwitchTask.priority = (osPriority_t)osPriorityNormal; 8001b3c: 2318 movs r3, #24 8001b3e: 61bb str r3, [r7, #24] limiterSwitchTaskHandle = osThreadNew (LimiterSwitchTask, NULL, &osThreadAttradc1LimiterSwitchTask); 8001b40: 463b mov r3, r7 8001b42: 461a mov r2, r3 8001b44: 2100 movs r1, #0 8001b46: 4813 ldr r0, [pc, #76] @ (8001b94 ) 8001b48: f010 fb9a bl 8012280 8001b4c: 4603 mov r3, r0 8001b4e: 4a12 ldr r2, [pc, #72] @ (8001b98 ) 8001b50: 6013 str r3, [r2, #0] } 8001b52: bf00 nop 8001b54: 3790 adds r7, #144 @ 0x90 8001b56: 46bd mov sp, r7 8001b58: bd80 pop {r7, pc} 8001b5a: bf00 nop 8001b5c: 24000748 .word 0x24000748 8001b60: 2400074c .word 0x2400074c 8001b64: 24000750 .word 0x24000750 8001b68: 24000754 .word 0x24000754 8001b6c: 24000738 .word 0x24000738 8001b70: 2400073c .word 0x2400073c 8001b74: 24000740 .word 0x24000740 8001b78: 08001ba1 .word 0x08001ba1 8001b7c: 24000728 .word 0x24000728 8001b80: 08001f29 .word 0x08001f29 8001b84: 2400072c .word 0x2400072c 8001b88: 08002231 .word 0x08002231 8001b8c: 24000730 .word 0x24000730 8001b90: 24000744 .word 0x24000744 8001b94: 080025ad .word 0x080025ad 8001b98: 24000734 .word 0x24000734 8001b9c: 00000000 .word 0x00000000 08001ba0 : void ADC1MeasTask (void* arg) { 8001ba0: b580 push {r7, lr} 8001ba2: b09a sub sp, #104 @ 0x68 8001ba4: af00 add r7, sp, #0 8001ba6: 6078 str r0, [r7, #4] float circBuffer[VOLTAGES_COUNT][CIRC_BUFF_LEN] = {0}; 8001ba8: f107 032c add.w r3, r7, #44 @ 0x2c 8001bac: 2228 movs r2, #40 @ 0x28 8001bae: 2100 movs r1, #0 8001bb0: 4618 mov r0, r3 8001bb2: f014 fdd0 bl 8016756 float rms[VOLTAGES_COUNT] = {0};; 8001bb6: f04f 0300 mov.w r3, #0 8001bba: 62bb str r3, [r7, #40] @ 0x28 ADC1_Data adcData = { 0 }; 8001bbc: f107 0308 add.w r3, r7, #8 8001bc0: 2220 movs r2, #32 8001bc2: 2100 movs r1, #0 8001bc4: 4618 mov r0, r3 8001bc6: f014 fdc6 bl 8016756 uint32_t circBuffPos = 0; 8001bca: 2300 movs r3, #0 8001bcc: 667b str r3, [r7, #100] @ 0x64 float gainCorrection = 1.0; 8001bce: f04f 537e mov.w r3, #1065353216 @ 0x3f800000 8001bd2: 663b str r3, [r7, #96] @ 0x60 while (pdTRUE) { osMessageQueueGet (adc1MeasDataQueue, &adcData, 0, osWaitForever); 8001bd4: 4bc8 ldr r3, [pc, #800] @ (8001ef8 ) 8001bd6: 6818 ldr r0, [r3, #0] 8001bd8: f107 0108 add.w r1, r7, #8 8001bdc: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8001be0: 2200 movs r2, #0 8001be2: f010 fed3 bl 801298c #ifdef GAIN_AUTO_CORRECTION if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 8001be6: 4bc5 ldr r3, [pc, #788] @ (8001efc ) 8001be8: 681b ldr r3, [r3, #0] 8001bea: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001bee: 4618 mov r0, r3 8001bf0: f010 fd71 bl 80126d6 8001bf4: 4603 mov r3, r0 8001bf6: 2b00 cmp r3, #0 8001bf8: d10c bne.n 8001c14 gainCorrection = (float)vRefmV; 8001bfa: 4bc1 ldr r3, [pc, #772] @ (8001f00 ) 8001bfc: 681b ldr r3, [r3, #0] 8001bfe: ee07 3a90 vmov s15, r3 8001c02: eef8 7a67 vcvt.f32.u32 s15, s15 8001c06: edc7 7a18 vstr s15, [r7, #96] @ 0x60 osMutexRelease (vRefmVMutex); 8001c0a: 4bbc ldr r3, [pc, #752] @ (8001efc ) 8001c0c: 681b ldr r3, [r3, #0] 8001c0e: 4618 mov r0, r3 8001c10: f010 fdac bl 801276c } gainCorrection = gainCorrection / EXT_VREF_mV; 8001c14: ed97 7a18 vldr s14, [r7, #96] @ 0x60 8001c18: eddf 6aba vldr s13, [pc, #744] @ 8001f04 8001c1c: eec7 7a26 vdiv.f32 s15, s14, s13 8001c20: edc7 7a18 vstr s15, [r7, #96] @ 0x60 #endif for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) { 8001c24: 2300 movs r3, #0 8001c26: f887 305f strb.w r3, [r7, #95] @ 0x5f 8001c2a: e0e7 b.n 8001dfc float val = adcData.adcDataBuffer[i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 8001c2c: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001c30: 005b lsls r3, r3, #1 8001c32: 3368 adds r3, #104 @ 0x68 8001c34: 443b add r3, r7 8001c36: f833 3c60 ldrh.w r3, [r3, #-96] 8001c3a: ee07 3a90 vmov s15, r3 8001c3e: eeb8 7be7 vcvt.f64.s32 d7, s15 8001c42: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8001c46: ee27 6b06 vmul.f64 d6, d7, d6 8001c4a: ed9f 5ba5 vldr d5, [pc, #660] @ 8001ee0 8001c4e: ee86 7b05 vdiv.f64 d7, d6, d5 8001c52: ed9f 6ba5 vldr d6, [pc, #660] @ 8001ee8 8001c56: ee27 6b06 vmul.f64 d6, d7, d6 8001c5a: edd7 7a18 vldr s15, [r7, #96] @ 0x60 8001c5e: eeb7 7ae7 vcvt.f64.f32 d7, s15 8001c62: ee26 6b07 vmul.f64 d6, d6, d7 8001c66: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001c6a: 4aa7 ldr r2, [pc, #668] @ (8001f08 ) 8001c6c: 00db lsls r3, r3, #3 8001c6e: 4413 add r3, r2 8001c70: edd3 7a00 vldr s15, [r3] 8001c74: eeb7 7ae7 vcvt.f64.f32 d7, s15 8001c78: ee26 6b07 vmul.f64 d6, d6, d7 8001c7c: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001c80: 4aa1 ldr r2, [pc, #644] @ (8001f08 ) 8001c82: 00db lsls r3, r3, #3 8001c84: 4413 add r3, r2 8001c86: 3304 adds r3, #4 8001c88: edd3 7a00 vldr s15, [r3] 8001c8c: eeb7 7ae7 vcvt.f64.f32 d7, s15 8001c90: ee36 7b07 vadd.f64 d7, d6, d7 8001c94: eef7 7bc7 vcvt.f32.f64 s15, d7 8001c98: edc7 7a15 vstr s15, [r7, #84] @ 0x54 circBuffer[i][circBuffPos] = val; 8001c9c: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 8001ca0: 4613 mov r3, r2 8001ca2: 009b lsls r3, r3, #2 8001ca4: 4413 add r3, r2 8001ca6: 005b lsls r3, r3, #1 8001ca8: 6e7a ldr r2, [r7, #100] @ 0x64 8001caa: 4413 add r3, r2 8001cac: 009b lsls r3, r3, #2 8001cae: 3368 adds r3, #104 @ 0x68 8001cb0: 443b add r3, r7 8001cb2: 3b3c subs r3, #60 @ 0x3c 8001cb4: 6d7a ldr r2, [r7, #84] @ 0x54 8001cb6: 601a str r2, [r3, #0] rms[i] = 0.0; 8001cb8: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001cbc: 009b lsls r3, r3, #2 8001cbe: 3368 adds r3, #104 @ 0x68 8001cc0: 443b add r3, r7 8001cc2: 3b40 subs r3, #64 @ 0x40 8001cc4: f04f 0200 mov.w r2, #0 8001cc8: 601a str r2, [r3, #0] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 8001cca: 2300 movs r3, #0 8001ccc: f887 305e strb.w r3, [r7, #94] @ 0x5e 8001cd0: e025 b.n 8001d1e rms[i] += circBuffer[i][c]; 8001cd2: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001cd6: 009b lsls r3, r3, #2 8001cd8: 3368 adds r3, #104 @ 0x68 8001cda: 443b add r3, r7 8001cdc: 3b40 subs r3, #64 @ 0x40 8001cde: ed93 7a00 vldr s14, [r3] 8001ce2: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 8001ce6: f897 105e ldrb.w r1, [r7, #94] @ 0x5e 8001cea: 4613 mov r3, r2 8001cec: 009b lsls r3, r3, #2 8001cee: 4413 add r3, r2 8001cf0: 005b lsls r3, r3, #1 8001cf2: 440b add r3, r1 8001cf4: 009b lsls r3, r3, #2 8001cf6: 3368 adds r3, #104 @ 0x68 8001cf8: 443b add r3, r7 8001cfa: 3b3c subs r3, #60 @ 0x3c 8001cfc: edd3 7a00 vldr s15, [r3] 8001d00: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001d04: ee77 7a27 vadd.f32 s15, s14, s15 8001d08: 009b lsls r3, r3, #2 8001d0a: 3368 adds r3, #104 @ 0x68 8001d0c: 443b add r3, r7 8001d0e: 3b40 subs r3, #64 @ 0x40 8001d10: edc3 7a00 vstr s15, [r3] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 8001d14: f897 305e ldrb.w r3, [r7, #94] @ 0x5e 8001d18: 3301 adds r3, #1 8001d1a: f887 305e strb.w r3, [r7, #94] @ 0x5e 8001d1e: f897 305e ldrb.w r3, [r7, #94] @ 0x5e 8001d22: 2b09 cmp r3, #9 8001d24: d9d5 bls.n 8001cd2 } rms[i] = rms[i] / CIRC_BUFF_LEN; 8001d26: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001d2a: 009b lsls r3, r3, #2 8001d2c: 3368 adds r3, #104 @ 0x68 8001d2e: 443b add r3, r7 8001d30: 3b40 subs r3, #64 @ 0x40 8001d32: ed93 7a00 vldr s14, [r3] 8001d36: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001d3a: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8001d3e: eec7 7a26 vdiv.f32 s15, s14, s13 8001d42: 009b lsls r3, r3, #2 8001d44: 3368 adds r3, #104 @ 0x68 8001d46: 443b add r3, r7 8001d48: 3b40 subs r3, #64 @ 0x40 8001d4a: edc3 7a00 vstr s15, [r3] if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8001d4e: 4b6f ldr r3, [pc, #444] @ (8001f0c ) 8001d50: 681b ldr r3, [r3, #0] 8001d52: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001d56: 4618 mov r0, r3 8001d58: f010 fcbd bl 80126d6 8001d5c: 4603 mov r3, r0 8001d5e: 2b00 cmp r3, #0 8001d60: d147 bne.n 8001df2 if (fabs(resMeasurements.voltagePeak[i]) < fabs(val)) { 8001d62: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001d66: 4a6a ldr r2, [pc, #424] @ (8001f10 ) 8001d68: 3302 adds r3, #2 8001d6a: 009b lsls r3, r3, #2 8001d6c: 4413 add r3, r2 8001d6e: 3304 adds r3, #4 8001d70: edd3 7a00 vldr s15, [r3] 8001d74: eeb0 7ae7 vabs.f32 s14, s15 8001d78: edd7 7a15 vldr s15, [r7, #84] @ 0x54 8001d7c: eef0 7ae7 vabs.f32 s15, s15 8001d80: eeb4 7ae7 vcmpe.f32 s14, s15 8001d84: eef1 fa10 vmrs APSR_nzcv, fpscr 8001d88: d508 bpl.n 8001d9c resMeasurements.voltagePeak[i] = val; 8001d8a: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001d8e: 4a60 ldr r2, [pc, #384] @ (8001f10 ) 8001d90: 3302 adds r3, #2 8001d92: 009b lsls r3, r3, #2 8001d94: 4413 add r3, r2 8001d96: 3304 adds r3, #4 8001d98: 6d7a ldr r2, [r7, #84] @ 0x54 8001d9a: 601a str r2, [r3, #0] } resMeasurements.voltageRMS[i] = rms[i]; 8001d9c: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 8001da0: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001da4: 0092 lsls r2, r2, #2 8001da6: 3268 adds r2, #104 @ 0x68 8001da8: 443a add r2, r7 8001daa: 3a40 subs r2, #64 @ 0x40 8001dac: 6812 ldr r2, [r2, #0] 8001dae: 4958 ldr r1, [pc, #352] @ (8001f10 ) 8001db0: 009b lsls r3, r3, #2 8001db2: 440b add r3, r1 8001db4: 601a str r2, [r3, #0] resMeasurements.power[i] = resMeasurements.voltageRMS[i] * resMeasurements.currentRMS[i]; 8001db6: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001dba: 4a55 ldr r2, [pc, #340] @ (8001f10 ) 8001dbc: 009b lsls r3, r3, #2 8001dbe: 4413 add r3, r2 8001dc0: ed93 7a00 vldr s14, [r3] 8001dc4: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001dc8: 4a51 ldr r2, [pc, #324] @ (8001f10 ) 8001dca: 3306 adds r3, #6 8001dcc: 009b lsls r3, r3, #2 8001dce: 4413 add r3, r2 8001dd0: edd3 7a00 vldr s15, [r3] 8001dd4: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001dd8: ee67 7a27 vmul.f32 s15, s14, s15 8001ddc: 4a4c ldr r2, [pc, #304] @ (8001f10 ) 8001dde: 330c adds r3, #12 8001de0: 009b lsls r3, r3, #2 8001de2: 4413 add r3, r2 8001de4: edc3 7a00 vstr s15, [r3] osMutexRelease (resMeasurementsMutex); 8001de8: 4b48 ldr r3, [pc, #288] @ (8001f0c ) 8001dea: 681b ldr r3, [r3, #0] 8001dec: 4618 mov r0, r3 8001dee: f010 fcbd bl 801276c for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) { 8001df2: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001df6: 3301 adds r3, #1 8001df8: f887 305f strb.w r3, [r7, #95] @ 0x5f 8001dfc: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8001e00: 2b00 cmp r3, #0 8001e02: f43f af13 beq.w 8001c2c } } ++circBuffPos; 8001e06: 6e7b ldr r3, [r7, #100] @ 0x64 8001e08: 3301 adds r3, #1 8001e0a: 667b str r3, [r7, #100] @ 0x64 circBuffPos = circBuffPos % CIRC_BUFF_LEN; 8001e0c: 6e7a ldr r2, [r7, #100] @ 0x64 8001e0e: 4b41 ldr r3, [pc, #260] @ (8001f14 ) 8001e10: fba3 1302 umull r1, r3, r3, r2 8001e14: 08d9 lsrs r1, r3, #3 8001e16: 460b mov r3, r1 8001e18: 009b lsls r3, r3, #2 8001e1a: 440b add r3, r1 8001e1c: 005b lsls r3, r3, #1 8001e1e: 1ad3 subs r3, r2, r3 8001e20: 667b str r3, [r7, #100] @ 0x64 if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) { 8001e22: 4b3d ldr r3, [pc, #244] @ (8001f18 ) 8001e24: 681b ldr r3, [r3, #0] 8001e26: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001e2a: 4618 mov r0, r3 8001e2c: f010 fc53 bl 80126d6 8001e30: 4603 mov r3, r0 8001e32: 2b00 cmp r3, #0 8001e34: d124 bne.n 8001e80 uint8_t refIdx = 0; 8001e36: 2300 movs r3, #0 8001e38: f887 305d strb.w r3, [r7, #93] @ 0x5d for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) { 8001e3c: 2303 movs r3, #3 8001e3e: f887 305c strb.w r3, [r7, #92] @ 0x5c 8001e42: e014 b.n 8001e6e ILxRef[refIdx++] = adcData.adcDataBuffer[i]; 8001e44: f897 205c ldrb.w r2, [r7, #92] @ 0x5c 8001e48: f897 305d ldrb.w r3, [r7, #93] @ 0x5d 8001e4c: 1c59 adds r1, r3, #1 8001e4e: f887 105d strb.w r1, [r7, #93] @ 0x5d 8001e52: 4619 mov r1, r3 8001e54: 0053 lsls r3, r2, #1 8001e56: 3368 adds r3, #104 @ 0x68 8001e58: 443b add r3, r7 8001e5a: f833 2c60 ldrh.w r2, [r3, #-96] 8001e5e: 4b2f ldr r3, [pc, #188] @ (8001f1c ) 8001e60: f823 2011 strh.w r2, [r3, r1, lsl #1] for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) { 8001e64: f897 305c ldrb.w r3, [r7, #92] @ 0x5c 8001e68: 3301 adds r3, #1 8001e6a: f887 305c strb.w r3, [r7, #92] @ 0x5c 8001e6e: f897 305c ldrb.w r3, [r7, #92] @ 0x5c 8001e72: 2b05 cmp r3, #5 8001e74: d9e6 bls.n 8001e44 } osMutexRelease (ILxRefMutex); 8001e76: 4b28 ldr r3, [pc, #160] @ (8001f18 ) 8001e78: 681b ldr r3, [r3, #0] 8001e7a: 4618 mov r0, r3 8001e7c: f010 fc76 bl 801276c } float fanFBVoltage = adcData.adcDataBuffer[FanFB] * deltaADC * -4.35 + 12; 8001e80: 8abb ldrh r3, [r7, #20] 8001e82: ee07 3a90 vmov s15, r3 8001e86: eeb8 7be7 vcvt.f64.s32 d7, s15 8001e8a: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8001e8e: ee27 6b06 vmul.f64 d6, d7, d6 8001e92: ed9f 5b13 vldr d5, [pc, #76] @ 8001ee0 8001e96: ee86 7b05 vdiv.f64 d7, d6, d5 8001e9a: ed9f 6b15 vldr d6, [pc, #84] @ 8001ef0 8001e9e: ee27 7b06 vmul.f64 d7, d7, d6 8001ea2: eeb2 6b08 vmov.f64 d6, #40 @ 0x41400000 12.0 8001ea6: ee37 7b06 vadd.f64 d7, d7, d6 8001eaa: eef7 7bc7 vcvt.f32.f64 s15, d7 8001eae: edc7 7a16 vstr s15, [r7, #88] @ 0x58 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8001eb2: 4b1b ldr r3, [pc, #108] @ (8001f20 ) 8001eb4: 681b ldr r3, [r3, #0] 8001eb6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001eba: 4618 mov r0, r3 8001ebc: f010 fc0b bl 80126d6 8001ec0: 4603 mov r3, r0 8001ec2: 2b00 cmp r3, #0 8001ec4: f47f ae86 bne.w 8001bd4 sensorsInfo.fanVoltage = fanFBVoltage; 8001ec8: 4a16 ldr r2, [pc, #88] @ (8001f24 ) 8001eca: 6dbb ldr r3, [r7, #88] @ 0x58 8001ecc: 6093 str r3, [r2, #8] osMutexRelease(sensorsInfoMutex); 8001ece: 4b14 ldr r3, [pc, #80] @ (8001f20 ) 8001ed0: 681b ldr r3, [r3, #0] 8001ed2: 4618 mov r0, r3 8001ed4: f010 fc4a bl 801276c while (pdTRUE) { 8001ed8: e67c b.n 8001bd4 8001eda: bf00 nop 8001edc: f3af 8000 nop.w 8001ee0: 00000000 .word 0x00000000 8001ee4: 40efffe0 .word 0x40efffe0 8001ee8: f5c28f5c .word 0xf5c28f5c 8001eec: 401e5c28 .word 0x401e5c28 8001ef0: 66666666 .word 0x66666666 8001ef4: c0116666 .word 0xc0116666 8001ef8: 24000738 .word 0x24000738 8001efc: 24000748 .word 0x24000748 8001f00: 24000030 .word 0x24000030 8001f04: 453b8000 .word 0x453b8000 8001f08: 24000000 .word 0x24000000 8001f0c: 2400074c .word 0x2400074c 8001f10: 24000758 .word 0x24000758 8001f14: cccccccd .word 0xcccccccd 8001f18: 24000754 .word 0x24000754 8001f1c: 240007c0 .word 0x240007c0 8001f20: 24000750 .word 0x24000750 8001f24: 24000794 .word 0x24000794 08001f28 : } } } void ADC2MeasTask (void* arg) { 8001f28: b580 push {r7, lr} 8001f2a: b09c sub sp, #112 @ 0x70 8001f2c: af00 add r7, sp, #0 8001f2e: 6078 str r0, [r7, #4] float circBuffer[CURRENTS_COUNT][CIRC_BUFF_LEN] = {0}; 8001f30: f107 0334 add.w r3, r7, #52 @ 0x34 8001f34: 2228 movs r2, #40 @ 0x28 8001f36: 2100 movs r1, #0 8001f38: 4618 mov r0, r3 8001f3a: f014 fc0c bl 8016756 float rms[CURRENTS_COUNT] = {0}; 8001f3e: f04f 0300 mov.w r3, #0 8001f42: 633b str r3, [r7, #48] @ 0x30 ADC2_Data adcData = { 0 }; 8001f44: f107 0310 add.w r3, r7, #16 8001f48: 2220 movs r2, #32 8001f4a: 2100 movs r1, #0 8001f4c: 4618 mov r0, r3 8001f4e: f014 fc02 bl 8016756 uint32_t circBuffPos = 0; 8001f52: 2300 movs r3, #0 8001f54: 66fb str r3, [r7, #108] @ 0x6c float gainCorrection = 1.0; 8001f56: f04f 537e mov.w r3, #1065353216 @ 0x3f800000 8001f5a: 66bb str r3, [r7, #104] @ 0x68 while (pdTRUE) { osMessageQueueGet (adc2MeasDataQueue, &adcData, 0, osWaitForever); 8001f5c: 4baa ldr r3, [pc, #680] @ (8002208 ) 8001f5e: 6818 ldr r0, [r3, #0] 8001f60: f107 0110 add.w r1, r7, #16 8001f64: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8001f68: 2200 movs r2, #0 8001f6a: f010 fd0f bl 801298c if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 8001f6e: 4ba7 ldr r3, [pc, #668] @ (800220c ) 8001f70: 681b ldr r3, [r3, #0] 8001f72: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001f76: 4618 mov r0, r3 8001f78: f010 fbad bl 80126d6 8001f7c: 4603 mov r3, r0 8001f7e: 2b00 cmp r3, #0 8001f80: d10c bne.n 8001f9c gainCorrection = (float)vRefmV; 8001f82: 4ba3 ldr r3, [pc, #652] @ (8002210 ) 8001f84: 681b ldr r3, [r3, #0] 8001f86: ee07 3a90 vmov s15, r3 8001f8a: eef8 7a67 vcvt.f32.u32 s15, s15 8001f8e: edc7 7a1a vstr s15, [r7, #104] @ 0x68 osMutexRelease (vRefmVMutex); 8001f92: 4b9e ldr r3, [pc, #632] @ (800220c ) 8001f94: 681b ldr r3, [r3, #0] 8001f96: 4618 mov r0, r3 8001f98: f010 fbe8 bl 801276c } gainCorrection = gainCorrection / EXT_VREF_mV; 8001f9c: ed97 7a1a vldr s14, [r7, #104] @ 0x68 8001fa0: eddf 6a9c vldr s13, [pc, #624] @ 8002214 8001fa4: eec7 7a26 vdiv.f32 s15, s14, s13 8001fa8: edc7 7a1a vstr s15, [r7, #104] @ 0x68 float ref[CURRENTS_COUNT] = { 0 }; 8001fac: f04f 0300 mov.w r3, #0 8001fb0: 60fb str r3, [r7, #12] if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) { 8001fb2: 4b99 ldr r3, [pc, #612] @ (8002218 ) 8001fb4: 681b ldr r3, [r3, #0] 8001fb6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001fba: 4618 mov r0, r3 8001fbc: f010 fb8b bl 80126d6 8001fc0: 4603 mov r3, r0 8001fc2: 2b00 cmp r3, #0 8001fc4: d122 bne.n 800200c for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 8001fc6: 2300 movs r3, #0 8001fc8: f887 3067 strb.w r3, [r7, #103] @ 0x67 8001fcc: e015 b.n 8001ffa ref[i] = (float)ILxRef[i]; 8001fce: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 8001fd2: 4a92 ldr r2, [pc, #584] @ (800221c ) 8001fd4: f832 2013 ldrh.w r2, [r2, r3, lsl #1] 8001fd8: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 8001fdc: ee07 2a90 vmov s15, r2 8001fe0: eef8 7a67 vcvt.f32.u32 s15, s15 8001fe4: 009b lsls r3, r3, #2 8001fe6: 3370 adds r3, #112 @ 0x70 8001fe8: 443b add r3, r7 8001fea: 3b64 subs r3, #100 @ 0x64 8001fec: edc3 7a00 vstr s15, [r3] for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 8001ff0: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 8001ff4: 3301 adds r3, #1 8001ff6: f887 3067 strb.w r3, [r7, #103] @ 0x67 8001ffa: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 8001ffe: 2b00 cmp r3, #0 8002000: d0e5 beq.n 8001fce } osMutexRelease (ILxRefMutex); 8002002: 4b85 ldr r3, [pc, #532] @ (8002218 ) 8002004: 681b ldr r3, [r3, #0] 8002006: 4618 mov r0, r3 8002008: f010 fbb0 bl 801276c } for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 800200c: 2300 movs r3, #0 800200e: f887 3066 strb.w r3, [r7, #102] @ 0x66 8002012: e0db b.n 80021cc float adcVal = (float)adcData.adcDataBuffer[i]; 8002014: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002018: 005b lsls r3, r3, #1 800201a: 3370 adds r3, #112 @ 0x70 800201c: 443b add r3, r7 800201e: f833 3c60 ldrh.w r3, [r3, #-96] 8002022: ee07 3a90 vmov s15, r3 8002026: eef8 7a67 vcvt.f32.u32 s15, s15 800202a: edc7 7a18 vstr s15, [r7, #96] @ 0x60 float val = (adcVal - ref[i]) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset; 800202e: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002032: 009b lsls r3, r3, #2 8002034: 3370 adds r3, #112 @ 0x70 8002036: 443b add r3, r7 8002038: 3b64 subs r3, #100 @ 0x64 800203a: edd3 7a00 vldr s15, [r3] 800203e: ed97 7a18 vldr s14, [r7, #96] @ 0x60 8002042: ee77 7a67 vsub.f32 s15, s14, s15 8002046: eeb7 7ae7 vcvt.f64.f32 d7, s15 800204a: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 800204e: ee27 6b06 vmul.f64 d6, d7, d6 8002052: ed9f 5b69 vldr d5, [pc, #420] @ 80021f8 8002056: ee86 7b05 vdiv.f64 d7, d6, d5 800205a: ed9f 6b69 vldr d6, [pc, #420] @ 8002200 800205e: ee27 6b06 vmul.f64 d6, d7, d6 8002062: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8002066: eeb7 7ae7 vcvt.f64.f32 d7, s15 800206a: ee26 6b07 vmul.f64 d6, d6, d7 800206e: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002072: 4a6b ldr r2, [pc, #428] @ (8002220 ) 8002074: 00db lsls r3, r3, #3 8002076: 4413 add r3, r2 8002078: edd3 7a00 vldr s15, [r3] 800207c: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002080: ee26 6b07 vmul.f64 d6, d6, d7 8002084: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002088: 4a65 ldr r2, [pc, #404] @ (8002220 ) 800208a: 00db lsls r3, r3, #3 800208c: 4413 add r3, r2 800208e: 3304 adds r3, #4 8002090: edd3 7a00 vldr s15, [r3] 8002094: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002098: ee36 7b07 vadd.f64 d7, d6, d7 800209c: eef7 7bc7 vcvt.f32.f64 s15, d7 80020a0: edc7 7a17 vstr s15, [r7, #92] @ 0x5c circBuffer[i][circBuffPos] = val; 80020a4: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 80020a8: 4613 mov r3, r2 80020aa: 009b lsls r3, r3, #2 80020ac: 4413 add r3, r2 80020ae: 005b lsls r3, r3, #1 80020b0: 6efa ldr r2, [r7, #108] @ 0x6c 80020b2: 4413 add r3, r2 80020b4: 009b lsls r3, r3, #2 80020b6: 3370 adds r3, #112 @ 0x70 80020b8: 443b add r3, r7 80020ba: 3b3c subs r3, #60 @ 0x3c 80020bc: 6dfa ldr r2, [r7, #92] @ 0x5c 80020be: 601a str r2, [r3, #0] rms[i] = 0.0; 80020c0: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80020c4: 009b lsls r3, r3, #2 80020c6: 3370 adds r3, #112 @ 0x70 80020c8: 443b add r3, r7 80020ca: 3b40 subs r3, #64 @ 0x40 80020cc: f04f 0200 mov.w r2, #0 80020d0: 601a str r2, [r3, #0] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 80020d2: 2300 movs r3, #0 80020d4: f887 3065 strb.w r3, [r7, #101] @ 0x65 80020d8: e025 b.n 8002126 rms[i] += circBuffer[i][c]; 80020da: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80020de: 009b lsls r3, r3, #2 80020e0: 3370 adds r3, #112 @ 0x70 80020e2: 443b add r3, r7 80020e4: 3b40 subs r3, #64 @ 0x40 80020e6: ed93 7a00 vldr s14, [r3] 80020ea: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 80020ee: f897 1065 ldrb.w r1, [r7, #101] @ 0x65 80020f2: 4613 mov r3, r2 80020f4: 009b lsls r3, r3, #2 80020f6: 4413 add r3, r2 80020f8: 005b lsls r3, r3, #1 80020fa: 440b add r3, r1 80020fc: 009b lsls r3, r3, #2 80020fe: 3370 adds r3, #112 @ 0x70 8002100: 443b add r3, r7 8002102: 3b3c subs r3, #60 @ 0x3c 8002104: edd3 7a00 vldr s15, [r3] 8002108: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800210c: ee77 7a27 vadd.f32 s15, s14, s15 8002110: 009b lsls r3, r3, #2 8002112: 3370 adds r3, #112 @ 0x70 8002114: 443b add r3, r7 8002116: 3b40 subs r3, #64 @ 0x40 8002118: edc3 7a00 vstr s15, [r3] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 800211c: f897 3065 ldrb.w r3, [r7, #101] @ 0x65 8002120: 3301 adds r3, #1 8002122: f887 3065 strb.w r3, [r7, #101] @ 0x65 8002126: f897 3065 ldrb.w r3, [r7, #101] @ 0x65 800212a: 2b09 cmp r3, #9 800212c: d9d5 bls.n 80020da } rms[i] = rms[i] / CIRC_BUFF_LEN; 800212e: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002132: 009b lsls r3, r3, #2 8002134: 3370 adds r3, #112 @ 0x70 8002136: 443b add r3, r7 8002138: 3b40 subs r3, #64 @ 0x40 800213a: ed93 7a00 vldr s14, [r3] 800213e: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002142: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002146: eec7 7a26 vdiv.f32 s15, s14, s13 800214a: 009b lsls r3, r3, #2 800214c: 3370 adds r3, #112 @ 0x70 800214e: 443b add r3, r7 8002150: 3b40 subs r3, #64 @ 0x40 8002152: edc3 7a00 vstr s15, [r3] if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8002156: 4b33 ldr r3, [pc, #204] @ (8002224 ) 8002158: 681b ldr r3, [r3, #0] 800215a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800215e: 4618 mov r0, r3 8002160: f010 fab9 bl 80126d6 8002164: 4603 mov r3, r0 8002166: 2b00 cmp r3, #0 8002168: d12b bne.n 80021c2 if (resMeasurements.currentPeak[i] < val) { 800216a: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800216e: 4a2e ldr r2, [pc, #184] @ (8002228 ) 8002170: 3308 adds r3, #8 8002172: 009b lsls r3, r3, #2 8002174: 4413 add r3, r2 8002176: 3304 adds r3, #4 8002178: edd3 7a00 vldr s15, [r3] 800217c: ed97 7a17 vldr s14, [r7, #92] @ 0x5c 8002180: eeb4 7ae7 vcmpe.f32 s14, s15 8002184: eef1 fa10 vmrs APSR_nzcv, fpscr 8002188: dd08 ble.n 800219c resMeasurements.currentPeak[i] = val; 800218a: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800218e: 4a26 ldr r2, [pc, #152] @ (8002228 ) 8002190: 3308 adds r3, #8 8002192: 009b lsls r3, r3, #2 8002194: 4413 add r3, r2 8002196: 3304 adds r3, #4 8002198: 6dfa ldr r2, [r7, #92] @ 0x5c 800219a: 601a str r2, [r3, #0] } resMeasurements.currentRMS[i] = rms[i]; 800219c: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 80021a0: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80021a4: 0092 lsls r2, r2, #2 80021a6: 3270 adds r2, #112 @ 0x70 80021a8: 443a add r2, r7 80021aa: 3a40 subs r2, #64 @ 0x40 80021ac: 6812 ldr r2, [r2, #0] 80021ae: 491e ldr r1, [pc, #120] @ (8002228 ) 80021b0: 3306 adds r3, #6 80021b2: 009b lsls r3, r3, #2 80021b4: 440b add r3, r1 80021b6: 601a str r2, [r3, #0] osMutexRelease (resMeasurementsMutex); 80021b8: 4b1a ldr r3, [pc, #104] @ (8002224 ) 80021ba: 681b ldr r3, [r3, #0] 80021bc: 4618 mov r0, r3 80021be: f010 fad5 bl 801276c for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 80021c2: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80021c6: 3301 adds r3, #1 80021c8: f887 3066 strb.w r3, [r7, #102] @ 0x66 80021cc: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80021d0: 2b00 cmp r3, #0 80021d2: f43f af1f beq.w 8002014 } } ++circBuffPos; 80021d6: 6efb ldr r3, [r7, #108] @ 0x6c 80021d8: 3301 adds r3, #1 80021da: 66fb str r3, [r7, #108] @ 0x6c circBuffPos = circBuffPos % CIRC_BUFF_LEN; 80021dc: 6efa ldr r2, [r7, #108] @ 0x6c 80021de: 4b13 ldr r3, [pc, #76] @ (800222c ) 80021e0: fba3 1302 umull r1, r3, r3, r2 80021e4: 08d9 lsrs r1, r3, #3 80021e6: 460b mov r3, r1 80021e8: 009b lsls r3, r3, #2 80021ea: 440b add r3, r1 80021ec: 005b lsls r3, r3, #1 80021ee: 1ad3 subs r3, r2, r3 80021f0: 66fb str r3, [r7, #108] @ 0x6c while (pdTRUE) { 80021f2: e6b3 b.n 8001f5c 80021f4: f3af 8000 nop.w 80021f8: 00000000 .word 0x00000000 80021fc: 40efffe0 .word 0x40efffe0 8002200: 83e425af .word 0x83e425af 8002204: 401e4d9e .word 0x401e4d9e 8002208: 2400073c .word 0x2400073c 800220c: 24000748 .word 0x24000748 8002210: 24000030 .word 0x24000030 8002214: 453b8000 .word 0x453b8000 8002218: 24000754 .word 0x24000754 800221c: 240007c0 .word 0x240007c0 8002220: 24000018 .word 0x24000018 8002224: 2400074c .word 0x2400074c 8002228: 24000758 .word 0x24000758 800222c: cccccccd .word 0xcccccccd 08002230 : } } void ADC3MeasTask (void* arg) { 8002230: b580 push {r7, lr} 8002232: b0bc sub sp, #240 @ 0xf0 8002234: af00 add r7, sp, #0 8002236: 6078 str r0, [r7, #4] float motorXSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 8002238: f107 03a4 add.w r3, r7, #164 @ 0xa4 800223c: 2228 movs r2, #40 @ 0x28 800223e: 2100 movs r1, #0 8002240: 4618 mov r0, r3 8002242: f014 fa88 bl 8016756 float motorYSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 8002246: f107 037c add.w r3, r7, #124 @ 0x7c 800224a: 2228 movs r2, #40 @ 0x28 800224c: 2100 movs r1, #0 800224e: 4618 mov r0, r3 8002250: f014 fa81 bl 8016756 float pvT1CircBuffer[CIRC_BUFF_LEN] = { 0 }; 8002254: f107 0354 add.w r3, r7, #84 @ 0x54 8002258: 2228 movs r2, #40 @ 0x28 800225a: 2100 movs r1, #0 800225c: 4618 mov r0, r3 800225e: f014 fa7a bl 8016756 float pvT2CircBuffer[CIRC_BUFF_LEN] = { 0 }; 8002262: f107 032c add.w r3, r7, #44 @ 0x2c 8002266: 2228 movs r2, #40 @ 0x28 8002268: 2100 movs r1, #0 800226a: 4618 mov r0, r3 800226c: f014 fa73 bl 8016756 uint32_t circBuffPos = 0; 8002270: 2300 movs r3, #0 8002272: f8c7 30ec str.w r3, [r7, #236] @ 0xec ADC3_Data adcData = { 0 }; 8002276: f107 030c add.w r3, r7, #12 800227a: 2220 movs r2, #32 800227c: 2100 movs r1, #0 800227e: 4618 mov r0, r3 8002280: f014 fa69 bl 8016756 while (pdTRUE) { osMessageQueueGet (adc3MeasDataQueue, &adcData, 0, osWaitForever); 8002284: 4bc2 ldr r3, [pc, #776] @ (8002590 ) 8002286: 6818 ldr r0, [r3, #0] 8002288: f107 010c add.w r1, r7, #12 800228c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002290: 2200 movs r2, #0 8002292: f010 fb7b bl 801298c uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B); 8002296: 4bbf ldr r3, [pc, #764] @ (8002594 ) 8002298: 881b ldrh r3, [r3, #0] 800229a: 461a mov r2, r3 800229c: f640 43e4 movw r3, #3300 @ 0xce4 80022a0: fb02 f303 mul.w r3, r2, r3 80022a4: 8aba ldrh r2, [r7, #20] 80022a6: fbb3 f3f2 udiv r3, r3, r2 80022aa: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 80022ae: 4bba ldr r3, [pc, #744] @ (8002598 ) 80022b0: 681b ldr r3, [r3, #0] 80022b2: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80022b6: 4618 mov r0, r3 80022b8: f010 fa0d bl 80126d6 80022bc: 4603 mov r3, r0 80022be: 2b00 cmp r3, #0 80022c0: d108 bne.n 80022d4 vRefmV = vRef; 80022c2: 4ab6 ldr r2, [pc, #728] @ (800259c ) 80022c4: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 80022c8: 6013 str r3, [r2, #0] osMutexRelease (vRefmVMutex); 80022ca: 4bb3 ldr r3, [pc, #716] @ (8002598 ) 80022cc: 681b ldr r3, [r3, #0] 80022ce: 4618 mov r0, r3 80022d0: f010 fa4c bl 801276c } float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333; 80022d4: 8a3b ldrh r3, [r7, #16] 80022d6: ee07 3a90 vmov s15, r3 80022da: eeb8 7be7 vcvt.f64.s32 d7, s15 80022de: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80022e2: ee27 6b06 vmul.f64 d6, d7, d6 80022e6: ed9f 5ba2 vldr d5, [pc, #648] @ 8002570 80022ea: ee86 7b05 vdiv.f64 d7, d6, d5 80022ee: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 80022f2: ee27 6b06 vmul.f64 d6, d7, d6 80022f6: ed9f 5ba0 vldr d5, [pc, #640] @ 8002578 80022fa: ee86 7b05 vdiv.f64 d7, d6, d5 80022fe: eef7 7bc7 vcvt.f32.f64 s15, d7 8002302: edc7 7a34 vstr s15, [r7, #208] @ 0xd0 float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333; 8002306: 8a7b ldrh r3, [r7, #18] 8002308: ee07 3a90 vmov s15, r3 800230c: eeb8 7be7 vcvt.f64.s32 d7, s15 8002310: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002314: ee27 6b06 vmul.f64 d6, d7, d6 8002318: ed9f 5b95 vldr d5, [pc, #596] @ 8002570 800231c: ee86 7b05 vdiv.f64 d7, d6, d5 8002320: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 8002324: ee27 6b06 vmul.f64 d6, d7, d6 8002328: ed9f 5b93 vldr d5, [pc, #588] @ 8002578 800232c: ee86 7b05 vdiv.f64 d7, d6, d5 8002330: eef7 7bc7 vcvt.f32.f64 s15, d7 8002334: edc7 7a33 vstr s15, [r7, #204] @ 0xcc motorXSensCircBuffer[circBuffPos] = motorXCurrentSense; 8002338: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 800233c: 009b lsls r3, r3, #2 800233e: 33f0 adds r3, #240 @ 0xf0 8002340: 443b add r3, r7 8002342: 3b4c subs r3, #76 @ 0x4c 8002344: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8002348: 601a str r2, [r3, #0] motorYSensCircBuffer[circBuffPos] = motorYCurrentSense; 800234a: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 800234e: 009b lsls r3, r3, #2 8002350: 33f0 adds r3, #240 @ 0xf0 8002352: 443b add r3, r7 8002354: 3b74 subs r3, #116 @ 0x74 8002356: f8d7 20cc ldr.w r2, [r7, #204] @ 0xcc 800235a: 601a str r2, [r3, #0] pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63; 800235c: 89bb ldrh r3, [r7, #12] 800235e: ee07 3a90 vmov s15, r3 8002362: eeb8 7be7 vcvt.f64.s32 d7, s15 8002366: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 800236a: ee27 6b06 vmul.f64 d6, d7, d6 800236e: ed9f 5b80 vldr d5, [pc, #512] @ 8002570 8002372: ee86 7b05 vdiv.f64 d7, d6, d5 8002376: ed9f 6b82 vldr d6, [pc, #520] @ 8002580 800237a: ee27 7b06 vmul.f64 d7, d7, d6 800237e: ed9f 6b82 vldr d6, [pc, #520] @ 8002588 8002382: ee37 7b46 vsub.f64 d7, d7, d6 8002386: eef7 7bc7 vcvt.f32.f64 s15, d7 800238a: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 800238e: 009b lsls r3, r3, #2 8002390: 33f0 adds r3, #240 @ 0xf0 8002392: 443b add r3, r7 8002394: 3b9c subs r3, #156 @ 0x9c 8002396: edc3 7a00 vstr s15, [r3] pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63; 800239a: 89fb ldrh r3, [r7, #14] 800239c: ee07 3a90 vmov s15, r3 80023a0: eeb8 7be7 vcvt.f64.s32 d7, s15 80023a4: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80023a8: ee27 6b06 vmul.f64 d6, d7, d6 80023ac: ed9f 5b70 vldr d5, [pc, #448] @ 8002570 80023b0: ee86 7b05 vdiv.f64 d7, d6, d5 80023b4: ed9f 6b72 vldr d6, [pc, #456] @ 8002580 80023b8: ee27 7b06 vmul.f64 d7, d7, d6 80023bc: ed9f 6b72 vldr d6, [pc, #456] @ 8002588 80023c0: ee37 7b46 vsub.f64 d7, d7, d6 80023c4: eef7 7bc7 vcvt.f32.f64 s15, d7 80023c8: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 80023cc: 009b lsls r3, r3, #2 80023ce: 33f0 adds r3, #240 @ 0xf0 80023d0: 443b add r3, r7 80023d2: 3bc4 subs r3, #196 @ 0xc4 80023d4: edc3 7a00 vstr s15, [r3] float motorXAveCurrent = 0; 80023d8: f04f 0300 mov.w r3, #0 80023dc: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 float motorYAveCurrent = 0; 80023e0: f04f 0300 mov.w r3, #0 80023e4: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 float pvT1AveTemp = 0; 80023e8: f04f 0300 mov.w r3, #0 80023ec: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 float pvT2AveTemp = 0; 80023f0: f04f 0300 mov.w r3, #0 80023f4: f8c7 30dc str.w r3, [r7, #220] @ 0xdc for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) { 80023f8: 2300 movs r3, #0 80023fa: f887 30db strb.w r3, [r7, #219] @ 0xdb 80023fe: e03c b.n 800247a motorXAveCurrent += motorXSensCircBuffer[i]; 8002400: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002404: 009b lsls r3, r3, #2 8002406: 33f0 adds r3, #240 @ 0xf0 8002408: 443b add r3, r7 800240a: 3b4c subs r3, #76 @ 0x4c 800240c: edd3 7a00 vldr s15, [r3] 8002410: ed97 7a3a vldr s14, [r7, #232] @ 0xe8 8002414: ee77 7a27 vadd.f32 s15, s14, s15 8002418: edc7 7a3a vstr s15, [r7, #232] @ 0xe8 motorYAveCurrent += motorYSensCircBuffer[i]; 800241c: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002420: 009b lsls r3, r3, #2 8002422: 33f0 adds r3, #240 @ 0xf0 8002424: 443b add r3, r7 8002426: 3b74 subs r3, #116 @ 0x74 8002428: edd3 7a00 vldr s15, [r3] 800242c: ed97 7a39 vldr s14, [r7, #228] @ 0xe4 8002430: ee77 7a27 vadd.f32 s15, s14, s15 8002434: edc7 7a39 vstr s15, [r7, #228] @ 0xe4 pvT1AveTemp += pvT1CircBuffer[i]; 8002438: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 800243c: 009b lsls r3, r3, #2 800243e: 33f0 adds r3, #240 @ 0xf0 8002440: 443b add r3, r7 8002442: 3b9c subs r3, #156 @ 0x9c 8002444: edd3 7a00 vldr s15, [r3] 8002448: ed97 7a38 vldr s14, [r7, #224] @ 0xe0 800244c: ee77 7a27 vadd.f32 s15, s14, s15 8002450: edc7 7a38 vstr s15, [r7, #224] @ 0xe0 pvT2AveTemp += pvT2CircBuffer[i]; 8002454: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002458: 009b lsls r3, r3, #2 800245a: 33f0 adds r3, #240 @ 0xf0 800245c: 443b add r3, r7 800245e: 3bc4 subs r3, #196 @ 0xc4 8002460: edd3 7a00 vldr s15, [r3] 8002464: ed97 7a37 vldr s14, [r7, #220] @ 0xdc 8002468: ee77 7a27 vadd.f32 s15, s14, s15 800246c: edc7 7a37 vstr s15, [r7, #220] @ 0xdc for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) { 8002470: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002474: 3301 adds r3, #1 8002476: f887 30db strb.w r3, [r7, #219] @ 0xdb 800247a: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 800247e: 2b09 cmp r3, #9 8002480: d9be bls.n 8002400 } motorXAveCurrent /= CIRC_BUFF_LEN; 8002482: ed97 7a3a vldr s14, [r7, #232] @ 0xe8 8002486: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 800248a: eec7 7a26 vdiv.f32 s15, s14, s13 800248e: edc7 7a3a vstr s15, [r7, #232] @ 0xe8 motorYAveCurrent /= CIRC_BUFF_LEN; 8002492: ed97 7a39 vldr s14, [r7, #228] @ 0xe4 8002496: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 800249a: eec7 7a26 vdiv.f32 s15, s14, s13 800249e: edc7 7a39 vstr s15, [r7, #228] @ 0xe4 pvT1AveTemp /= CIRC_BUFF_LEN; 80024a2: ed97 7a38 vldr s14, [r7, #224] @ 0xe0 80024a6: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 80024aa: eec7 7a26 vdiv.f32 s15, s14, s13 80024ae: edc7 7a38 vstr s15, [r7, #224] @ 0xe0 pvT2AveTemp /= CIRC_BUFF_LEN; 80024b2: ed97 7a37 vldr s14, [r7, #220] @ 0xdc 80024b6: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 80024ba: eec7 7a26 vdiv.f32 s15, s14, s13 80024be: edc7 7a37 vstr s15, [r7, #220] @ 0xdc if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80024c2: 4b37 ldr r3, [pc, #220] @ (80025a0 ) 80024c4: 681b ldr r3, [r3, #0] 80024c6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80024ca: 4618 mov r0, r3 80024cc: f010 f903 bl 80126d6 80024d0: 4603 mov r3, r0 80024d2: 2b00 cmp r3, #0 80024d4: d138 bne.n 8002548 if (sensorsInfo.motorXStatus == 1) { 80024d6: 4b33 ldr r3, [pc, #204] @ (80025a4 ) 80024d8: 7c1b ldrb r3, [r3, #16] 80024da: 2b01 cmp r3, #1 80024dc: d111 bne.n 8002502 sensorsInfo.motorXAveCurrent = motorXAveCurrent; 80024de: 4a31 ldr r2, [pc, #196] @ (80025a4 ) 80024e0: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8 80024e4: 6153 str r3, [r2, #20] if (sensorsInfo.motorXPeakCurrent < motorXCurrentSense) { 80024e6: 4b2f ldr r3, [pc, #188] @ (80025a4 ) 80024e8: edd3 7a07 vldr s15, [r3, #28] 80024ec: ed97 7a34 vldr s14, [r7, #208] @ 0xd0 80024f0: eeb4 7ae7 vcmpe.f32 s14, s15 80024f4: eef1 fa10 vmrs APSR_nzcv, fpscr 80024f8: dd03 ble.n 8002502 sensorsInfo.motorXPeakCurrent = motorXCurrentSense; 80024fa: 4a2a ldr r2, [pc, #168] @ (80025a4 ) 80024fc: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0 8002500: 61d3 str r3, [r2, #28] } } if (sensorsInfo.motorYStatus == 1) { 8002502: 4b28 ldr r3, [pc, #160] @ (80025a4 ) 8002504: 7c5b ldrb r3, [r3, #17] 8002506: 2b01 cmp r3, #1 8002508: d111 bne.n 800252e sensorsInfo.motorYAveCurrent = motorYAveCurrent; 800250a: 4a26 ldr r2, [pc, #152] @ (80025a4 ) 800250c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8002510: 6193 str r3, [r2, #24] if (sensorsInfo.motorYPeakCurrent < motorYCurrentSense) { 8002512: 4b24 ldr r3, [pc, #144] @ (80025a4 ) 8002514: edd3 7a08 vldr s15, [r3, #32] 8002518: ed97 7a33 vldr s14, [r7, #204] @ 0xcc 800251c: eeb4 7ae7 vcmpe.f32 s14, s15 8002520: eef1 fa10 vmrs APSR_nzcv, fpscr 8002524: dd03 ble.n 800252e sensorsInfo.motorYPeakCurrent = motorYCurrentSense; 8002526: 4a1f ldr r2, [pc, #124] @ (80025a4 ) 8002528: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc 800252c: 6213 str r3, [r2, #32] } } sensorsInfo.pvTemperature[0] = pvT1AveTemp; 800252e: 4a1d ldr r2, [pc, #116] @ (80025a4 ) 8002530: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8002534: 6013 str r3, [r2, #0] sensorsInfo.pvTemperature[1] = pvT2AveTemp; 8002536: 4a1b ldr r2, [pc, #108] @ (80025a4 ) 8002538: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 800253c: 6053 str r3, [r2, #4] osMutexRelease (sensorsInfoMutex); 800253e: 4b18 ldr r3, [pc, #96] @ (80025a0 ) 8002540: 681b ldr r3, [r3, #0] 8002542: 4618 mov r0, r3 8002544: f010 f912 bl 801276c } ++circBuffPos; 8002548: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 800254c: 3301 adds r3, #1 800254e: f8c7 30ec str.w r3, [r7, #236] @ 0xec circBuffPos = circBuffPos % CIRC_BUFF_LEN; 8002552: f8d7 20ec ldr.w r2, [r7, #236] @ 0xec 8002556: 4b14 ldr r3, [pc, #80] @ (80025a8 ) 8002558: fba3 1302 umull r1, r3, r3, r2 800255c: 08d9 lsrs r1, r3, #3 800255e: 460b mov r3, r1 8002560: 009b lsls r3, r3, #2 8002562: 440b add r3, r1 8002564: 005b lsls r3, r3, #1 8002566: 1ad3 subs r3, r2, r3 8002568: f8c7 30ec str.w r3, [r7, #236] @ 0xec while (pdTRUE) { 800256c: e68a b.n 8002284 800256e: bf00 nop 8002570: 00000000 .word 0x00000000 8002574: 40efffe0 .word 0x40efffe0 8002578: 3ad18d26 .word 0x3ad18d26 800257c: 4020aaaa .word 0x4020aaaa 8002580: aaa38226 .word 0xaaa38226 8002584: 4046aaaa .word 0x4046aaaa 8002588: 00000000 .word 0x00000000 800258c: 404f8000 .word 0x404f8000 8002590: 24000740 .word 0x24000740 8002594: 1ff1e860 .word 0x1ff1e860 8002598: 24000748 .word 0x24000748 800259c: 24000030 .word 0x24000030 80025a0: 24000750 .word 0x24000750 80025a4: 24000794 .word 0x24000794 80025a8: cccccccd .word 0xcccccccd 080025ac : } } void LimiterSwitchTask (void* arg) { 80025ac: b580 push {r7, lr} 80025ae: b08a sub sp, #40 @ 0x28 80025b0: af06 add r7, sp, #24 80025b2: 6078 str r0, [r7, #4] LimiterSwitchData limiterSwitchData = { 0 }; 80025b4: 2300 movs r3, #0 80025b6: 60bb str r3, [r7, #8] limiterSwitchData.gpioPin = GPIO_PIN_8; 80025b8: f44f 7380 mov.w r3, #256 @ 0x100 80025bc: 813b strh r3, [r7, #8] for(uint8_t i = 0; i < 6; i++) 80025be: 2300 movs r3, #0 80025c0: 73fb strb r3, [r7, #15] 80025c2: e015 b.n 80025f0 { limiterSwitchData.pinState = HAL_GPIO_ReadPin(GPIOD, limiterSwitchData.gpioPin); 80025c4: 893b ldrh r3, [r7, #8] 80025c6: 4619 mov r1, r3 80025c8: 486c ldr r0, [pc, #432] @ (800277c ) 80025ca: f007 fc41 bl 8009e50 80025ce: 4603 mov r3, r0 80025d0: 72bb strb r3, [r7, #10] osMessageQueuePut(limiterSwitchDataQueue, &limiterSwitchData, 0, 0); 80025d2: 4b6b ldr r3, [pc, #428] @ (8002780 ) 80025d4: 6818 ldr r0, [r3, #0] 80025d6: f107 0108 add.w r1, r7, #8 80025da: 2300 movs r3, #0 80025dc: 2200 movs r2, #0 80025de: f010 f975 bl 80128cc limiterSwitchData.gpioPin = limiterSwitchData.gpioPin << 1; 80025e2: 893b ldrh r3, [r7, #8] 80025e4: 005b lsls r3, r3, #1 80025e6: b29b uxth r3, r3 80025e8: 813b strh r3, [r7, #8] for(uint8_t i = 0; i < 6; i++) 80025ea: 7bfb ldrb r3, [r7, #15] 80025ec: 3301 adds r3, #1 80025ee: 73fb strb r3, [r7, #15] 80025f0: 7bfb ldrb r3, [r7, #15] 80025f2: 2b05 cmp r3, #5 80025f4: d9e6 bls.n 80025c4 } while (pdTRUE) { osMessageQueueGet (limiterSwitchDataQueue, &limiterSwitchData, 0, osWaitForever); 80025f6: 4b62 ldr r3, [pc, #392] @ (8002780 ) 80025f8: 6818 ldr r0, [r3, #0] 80025fa: f107 0108 add.w r1, r7, #8 80025fe: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002602: 2200 movs r2, #0 8002604: f010 f9c2 bl 801298c if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 8002608: 4b5e ldr r3, [pc, #376] @ (8002784 ) 800260a: 681b ldr r3, [r3, #0] 800260c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002610: 4618 mov r0, r3 8002612: f010 f860 bl 80126d6 8002616: 4603 mov r3, r0 8002618: 2b00 cmp r3, #0 800261a: d1ec bne.n 80025f6 { switch(limiterSwitchData.gpioPin) 800261c: 893b ldrh r3, [r7, #8] 800261e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8002622: d052 beq.n 80026ca 8002624: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8002628: dc5a bgt.n 80026e0 800262a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800262e: d041 beq.n 80026b4 8002630: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8002634: dc54 bgt.n 80026e0 8002636: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800263a: d030 beq.n 800269e 800263c: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8002640: dc4e bgt.n 80026e0 8002642: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8002646: d01f beq.n 8002688 8002648: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800264c: dc48 bgt.n 80026e0 800264e: f5b3 7f80 cmp.w r3, #256 @ 0x100 8002652: d003 beq.n 800265c 8002654: f5b3 7f00 cmp.w r3, #512 @ 0x200 8002658: d00b beq.n 8002672 break; case GPIO_PIN_13: sensorsInfo.limitXSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break; default: break; 800265a: e041 b.n 80026e0 sensorsInfo.limitYSwitchCenter = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; 800265c: 7abb ldrb r3, [r7, #10] 800265e: 2b01 cmp r3, #1 8002660: bf14 ite ne 8002662: 2301 movne r3, #1 8002664: 2300 moveq r3, #0 8002666: b2db uxtb r3, r3 8002668: 461a mov r2, r3 800266a: 4b47 ldr r3, [pc, #284] @ (8002788 ) 800266c: f883 2029 strb.w r2, [r3, #41] @ 0x29 break; 8002670: e037 b.n 80026e2 sensorsInfo.limitYSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; 8002672: 7abb ldrb r3, [r7, #10] 8002674: 2b01 cmp r3, #1 8002676: bf14 ite ne 8002678: 2301 movne r3, #1 800267a: 2300 moveq r3, #0 800267c: b2db uxtb r3, r3 800267e: 461a mov r2, r3 8002680: 4b41 ldr r3, [pc, #260] @ (8002788 ) 8002682: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8002686: e02c b.n 80026e2 sensorsInfo.limitXSwitchCenter = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; 8002688: 7abb ldrb r3, [r7, #10] 800268a: 2b01 cmp r3, #1 800268c: bf14 ite ne 800268e: 2301 movne r3, #1 8002690: 2300 moveq r3, #0 8002692: b2db uxtb r3, r3 8002694: 461a mov r2, r3 8002696: 4b3c ldr r3, [pc, #240] @ (8002788 ) 8002698: f883 2026 strb.w r2, [r3, #38] @ 0x26 break; 800269c: e021 b.n 80026e2 sensorsInfo.limitYSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; 800269e: 7abb ldrb r3, [r7, #10] 80026a0: 2b01 cmp r3, #1 80026a2: bf14 ite ne 80026a4: 2301 movne r3, #1 80026a6: 2300 moveq r3, #0 80026a8: b2db uxtb r3, r3 80026aa: 461a mov r2, r3 80026ac: 4b36 ldr r3, [pc, #216] @ (8002788 ) 80026ae: f883 2027 strb.w r2, [r3, #39] @ 0x27 break; 80026b2: e016 b.n 80026e2 sensorsInfo.limitXSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; 80026b4: 7abb ldrb r3, [r7, #10] 80026b6: 2b01 cmp r3, #1 80026b8: bf14 ite ne 80026ba: 2301 movne r3, #1 80026bc: 2300 moveq r3, #0 80026be: b2db uxtb r3, r3 80026c0: 461a mov r2, r3 80026c2: 4b31 ldr r3, [pc, #196] @ (8002788 ) 80026c4: f883 2024 strb.w r2, [r3, #36] @ 0x24 break; 80026c8: e00b b.n 80026e2 sensorsInfo.limitXSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; 80026ca: 7abb ldrb r3, [r7, #10] 80026cc: 2b01 cmp r3, #1 80026ce: bf14 ite ne 80026d0: 2301 movne r3, #1 80026d2: 2300 moveq r3, #0 80026d4: b2db uxtb r3, r3 80026d6: 461a mov r2, r3 80026d8: 4b2b ldr r3, [pc, #172] @ (8002788 ) 80026da: f883 2025 strb.w r2, [r3, #37] @ 0x25 break; 80026de: e000 b.n 80026e2 break; 80026e0: bf00 nop } if((sensorsInfo.limitXSwitchDown == 1) ||(sensorsInfo.limitXSwitchUp == 1)) 80026e2: 4b29 ldr r3, [pc, #164] @ (8002788 ) 80026e4: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 80026e8: 2b01 cmp r3, #1 80026ea: d004 beq.n 80026f6 80026ec: 4b26 ldr r3, [pc, #152] @ (8002788 ) 80026ee: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 80026f2: 2b01 cmp r3, #1 80026f4: d118 bne.n 8002728 { sensorsInfo.motorXStatus = motorControl(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, 0, 0, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 80026f6: 4b25 ldr r3, [pc, #148] @ (800278c ) 80026f8: 681b ldr r3, [r3, #0] 80026fa: 4a23 ldr r2, [pc, #140] @ (8002788 ) 80026fc: f892 2024 ldrb.w r2, [r2, #36] @ 0x24 8002700: 4921 ldr r1, [pc, #132] @ (8002788 ) 8002702: f891 1025 ldrb.w r1, [r1, #37] @ 0x25 8002706: 9104 str r1, [sp, #16] 8002708: 9203 str r2, [sp, #12] 800270a: 2200 movs r2, #0 800270c: 9202 str r2, [sp, #8] 800270e: 2200 movs r2, #0 8002710: 9201 str r2, [sp, #4] 8002712: 9300 str r3, [sp, #0] 8002714: 2304 movs r3, #4 8002716: 2200 movs r2, #0 8002718: 491d ldr r1, [pc, #116] @ (8002790 ) 800271a: 481e ldr r0, [pc, #120] @ (8002794 ) 800271c: f000 f8cc bl 80028b8 8002720: 4603 mov r3, r0 8002722: 461a mov r2, r3 8002724: 4b18 ldr r3, [pc, #96] @ (8002788 ) 8002726: 741a strb r2, [r3, #16] } if((sensorsInfo.limitYSwitchDown == 1) ||(sensorsInfo.limitYSwitchUp == 1)) 8002728: 4b17 ldr r3, [pc, #92] @ (8002788 ) 800272a: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 800272e: 2b01 cmp r3, #1 8002730: d004 beq.n 800273c 8002732: 4b15 ldr r3, [pc, #84] @ (8002788 ) 8002734: f893 3027 ldrb.w r3, [r3, #39] @ 0x27 8002738: 2b01 cmp r3, #1 800273a: d118 bne.n 800276e { sensorsInfo.motorYStatus = motorControl(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, 0, 0, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 800273c: 4b16 ldr r3, [pc, #88] @ (8002798 ) 800273e: 681b ldr r3, [r3, #0] 8002740: 4a11 ldr r2, [pc, #68] @ (8002788 ) 8002742: f892 2027 ldrb.w r2, [r2, #39] @ 0x27 8002746: 4910 ldr r1, [pc, #64] @ (8002788 ) 8002748: f891 1028 ldrb.w r1, [r1, #40] @ 0x28 800274c: 9104 str r1, [sp, #16] 800274e: 9203 str r2, [sp, #12] 8002750: 2200 movs r2, #0 8002752: 9202 str r2, [sp, #8] 8002754: 2200 movs r2, #0 8002756: 9201 str r2, [sp, #4] 8002758: 9300 str r3, [sp, #0] 800275a: 230c movs r3, #12 800275c: 2208 movs r2, #8 800275e: 490c ldr r1, [pc, #48] @ (8002790 ) 8002760: 480c ldr r0, [pc, #48] @ (8002794 ) 8002762: f000 f8a9 bl 80028b8 8002766: 4603 mov r3, r0 8002768: 461a mov r2, r3 800276a: 4b07 ldr r3, [pc, #28] @ (8002788 ) 800276c: 745a strb r2, [r3, #17] } // sensorsInfo.motorXStatus = motorControl(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, 0, 0, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); // sensorsInfo.motorYStatus = motorControl(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, 0, 0, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); osMutexRelease(sensorsInfoMutex); 800276e: 4b05 ldr r3, [pc, #20] @ (8002784 ) 8002770: 681b ldr r3, [r3, #0] 8002772: 4618 mov r0, r3 8002774: f00f fffa bl 801276c osMessageQueueGet (limiterSwitchDataQueue, &limiterSwitchData, 0, osWaitForever); 8002778: e73d b.n 80025f6 800277a: bf00 nop 800277c: 58020c00 .word 0x58020c00 8002780: 24000744 .word 0x24000744 8002784: 24000750 .word 0x24000750 8002788: 24000794 .word 0x24000794 800278c: 24000690 .word 0x24000690 8002790: 2400070c .word 0x2400070c 8002794: 240004b8 .word 0x240004b8 8002798: 240006c0 .word 0x240006c0 0800279c : #include #include "peripherial.h" void DbgLEDOn(uint8_t ledNumber) { 800279c: b580 push {r7, lr} 800279e: b082 sub sp, #8 80027a0: af00 add r7, sp, #0 80027a2: 4603 mov r3, r0 80027a4: 71fb strb r3, [r7, #7] HAL_GPIO_WritePin(GPIOD, ledNumber, GPIO_PIN_SET); 80027a6: 79fb ldrb r3, [r7, #7] 80027a8: b29b uxth r3, r3 80027aa: 2201 movs r2, #1 80027ac: 4619 mov r1, r3 80027ae: 4803 ldr r0, [pc, #12] @ (80027bc ) 80027b0: f007 fb66 bl 8009e80 } 80027b4: bf00 nop 80027b6: 3708 adds r7, #8 80027b8: 46bd mov sp, r7 80027ba: bd80 pop {r7, pc} 80027bc: 58020c00 .word 0x58020c00 080027c0 : void DbgLEDOff(uint8_t ledNumber) { 80027c0: b580 push {r7, lr} 80027c2: b082 sub sp, #8 80027c4: af00 add r7, sp, #0 80027c6: 4603 mov r3, r0 80027c8: 71fb strb r3, [r7, #7] HAL_GPIO_WritePin(GPIOD, ledNumber, GPIO_PIN_RESET); 80027ca: 79fb ldrb r3, [r7, #7] 80027cc: b29b uxth r3, r3 80027ce: 2200 movs r2, #0 80027d0: 4619 mov r1, r3 80027d2: 4803 ldr r0, [pc, #12] @ (80027e0 ) 80027d4: f007 fb54 bl 8009e80 } 80027d8: bf00 nop 80027da: 3708 adds r7, #8 80027dc: 46bd mov sp, r7 80027de: bd80 pop {r7, pc} 80027e0: 58020c00 .word 0x58020c00 080027e4 : void DbgLEDToggle(uint8_t ledNumber) { 80027e4: b580 push {r7, lr} 80027e6: b082 sub sp, #8 80027e8: af00 add r7, sp, #0 80027ea: 4603 mov r3, r0 80027ec: 71fb strb r3, [r7, #7] HAL_GPIO_TogglePin(GPIOD, ledNumber); 80027ee: 79fb ldrb r3, [r7, #7] 80027f0: b29b uxth r3, r3 80027f2: 4619 mov r1, r3 80027f4: 4803 ldr r0, [pc, #12] @ (8002804 ) 80027f6: f007 fb5c bl 8009eb2 } 80027fa: bf00 nop 80027fc: 3708 adds r7, #8 80027fe: 46bd mov sp, r7 8002800: bd80 pop {r7, pc} 8002802: bf00 nop 8002804: 58020c00 .word 0x58020c00 08002808 : void EnableCurrentSensors(void) { 8002808: b580 push {r7, lr} 800280a: af00 add r7, sp, #0 HAL_GPIO_WritePin(GPIOE, MCU_CS_PWR_EN, GPIO_PIN_SET); 800280c: 2201 movs r2, #1 800280e: f44f 4100 mov.w r1, #32768 @ 0x8000 8002812: 4802 ldr r0, [pc, #8] @ (800281c ) 8002814: f007 fb34 bl 8009e80 } 8002818: bf00 nop 800281a: bd80 pop {r7, pc} 800281c: 58021000 .word 0x58021000 08002820 : { HAL_GPIO_WritePin(GPIOE, MCU_CS_PWR_EN, GPIO_PIN_RESET); } void SelectCurrentSensorGain(CurrentSensor sensor, CurrentSensorGain gain) { 8002820: b580 push {r7, lr} 8002822: b084 sub sp, #16 8002824: af00 add r7, sp, #0 8002826: 4603 mov r3, r0 8002828: 460a mov r2, r1 800282a: 71fb strb r3, [r7, #7] 800282c: 4613 mov r3, r2 800282e: 71bb strb r3, [r7, #6] uint8_t gpioOffset = 0; 8002830: 2300 movs r3, #0 8002832: 73fb strb r3, [r7, #15] switch(sensor) 8002834: 79fb ldrb r3, [r7, #7] 8002836: 2b02 cmp r3, #2 8002838: d00c beq.n 8002854 800283a: 2b02 cmp r3, #2 800283c: dc0d bgt.n 800285a 800283e: 2b00 cmp r3, #0 8002840: d002 beq.n 8002848 8002842: 2b01 cmp r3, #1 8002844: d003 beq.n 800284e break; case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break; default: break; 8002846: e008 b.n 800285a gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET; 8002848: 2307 movs r3, #7 800284a: 73fb strb r3, [r7, #15] break; 800284c: e006 b.n 800285c gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; 800284e: 2309 movs r3, #9 8002850: 73fb strb r3, [r7, #15] break; 8002852: e003 b.n 800285c gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; 8002854: 230d movs r3, #13 8002856: 73fb strb r3, [r7, #15] break; 8002858: e000 b.n 800285c break; 800285a: bf00 nop } if(gpioOffset > 0) 800285c: 7bfb ldrb r3, [r7, #15] 800285e: 2b00 cmp r3, #0 8002860: d023 beq.n 80028aa { uint16_t gain0Gpio = 1 << gpioOffset; 8002862: 7bfb ldrb r3, [r7, #15] 8002864: 2201 movs r2, #1 8002866: fa02 f303 lsl.w r3, r2, r3 800286a: 81bb strh r3, [r7, #12] uint16_t gain1Gpio = 1 << (gpioOffset + 1); 800286c: 7bfb ldrb r3, [r7, #15] 800286e: 3301 adds r3, #1 8002870: 2201 movs r2, #1 8002872: fa02 f303 lsl.w r3, r2, r3 8002876: 817b strh r3, [r7, #10] uint16_t gpioState = ((uint16_t)gain) & 0x0001; 8002878: 79bb ldrb r3, [r7, #6] 800287a: b29b uxth r3, r3 800287c: f003 0301 and.w r3, r3, #1 8002880: 813b strh r3, [r7, #8] HAL_GPIO_WritePin(GPIOE, gain0Gpio, gpioState); 8002882: 893b ldrh r3, [r7, #8] 8002884: b2da uxtb r2, r3 8002886: 89bb ldrh r3, [r7, #12] 8002888: 4619 mov r1, r3 800288a: 480a ldr r0, [pc, #40] @ (80028b4 ) 800288c: f007 faf8 bl 8009e80 gpioState = (((uint16_t)gain) >> 1) & 0x0001; 8002890: 79bb ldrb r3, [r7, #6] 8002892: 085b lsrs r3, r3, #1 8002894: b2db uxtb r3, r3 8002896: f003 0301 and.w r3, r3, #1 800289a: 813b strh r3, [r7, #8] HAL_GPIO_WritePin(GPIOE, gain1Gpio, gpioState); 800289c: 893b ldrh r3, [r7, #8] 800289e: b2da uxtb r2, r3 80028a0: 897b ldrh r3, [r7, #10] 80028a2: 4619 mov r1, r3 80028a4: 4803 ldr r0, [pc, #12] @ (80028b4 ) 80028a6: f007 faeb bl 8009e80 } } 80028aa: bf00 nop 80028ac: 3710 adds r7, #16 80028ae: 46bd mov sp, r7 80028b0: bd80 pop {r7, pc} 80028b2: bf00 nop 80028b4: 58021000 .word 0x58021000 080028b8 : uint8_t motorControl (TIM_HandleTypeDef* htim, TIM_OC_InitTypeDef* motorTimerConfigOC, uint8_t channel1, uint8_t channel2, osTimerId_t motorTimerHandle, int32_t motorPWMPulse, int32_t motorTimerPeriod, uint8_t switchLimiterUpStat, uint8_t switchLimiterDownStat) { 80028b8: b580 push {r7, lr} 80028ba: b088 sub sp, #32 80028bc: af02 add r7, sp, #8 80028be: 60f8 str r0, [r7, #12] 80028c0: 60b9 str r1, [r7, #8] 80028c2: 4611 mov r1, r2 80028c4: 461a mov r2, r3 80028c6: 460b mov r3, r1 80028c8: 71fb strb r3, [r7, #7] 80028ca: 4613 mov r3, r2 80028cc: 71bb strb r3, [r7, #6] uint32_t motorStatus = 0; 80028ce: 2300 movs r3, #0 80028d0: 617b str r3, [r7, #20] MotorDriverState setMotorYState = HiZ; 80028d2: 2300 movs r3, #0 80028d4: 74fb strb r3, [r7, #19] HAL_TIM_PWM_Stop (htim, channel1); 80028d6: 79fb ldrb r3, [r7, #7] 80028d8: 4619 mov r1, r3 80028da: 68f8 ldr r0, [r7, #12] 80028dc: f00b fc7a bl 800e1d4 HAL_TIM_PWM_Stop (htim, channel2); 80028e0: 79bb ldrb r3, [r7, #6] 80028e2: 4619 mov r1, r3 80028e4: 68f8 ldr r0, [r7, #12] 80028e6: f00b fc75 bl 800e1d4 if (motorTimerPeriod > 0) { 80028ea: 6abb ldr r3, [r7, #40] @ 0x28 80028ec: 2b00 cmp r3, #0 80028ee: f340 808c ble.w 8002a0a if (motorPWMPulse > 0) { 80028f2: 6a7b ldr r3, [r7, #36] @ 0x24 80028f4: 2b00 cmp r3, #0 80028f6: dd2c ble.n 8002952 // Forward if (switchLimiterUpStat == 0) { 80028f8: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 80028fc: 2b00 cmp r3, #0 80028fe: d11d bne.n 800293c setMotorYState = Forward; 8002900: 2301 movs r3, #1 8002902: 74fb strb r3, [r7, #19] motorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorYState, abs (motorPWMPulse) * 10); 8002904: 79f9 ldrb r1, [r7, #7] 8002906: 79b8 ldrb r0, [r7, #6] 8002908: 6a7b ldr r3, [r7, #36] @ 0x24 800290a: ea83 72e3 eor.w r2, r3, r3, asr #31 800290e: eba2 72e3 sub.w r2, r2, r3, asr #31 8002912: 4613 mov r3, r2 8002914: 009b lsls r3, r3, #2 8002916: 4413 add r3, r2 8002918: 005b lsls r3, r3, #1 800291a: 9301 str r3, [sp, #4] 800291c: 7cfb ldrb r3, [r7, #19] 800291e: 9300 str r3, [sp, #0] 8002920: 4603 mov r3, r0 8002922: 460a mov r2, r1 8002924: 68b9 ldr r1, [r7, #8] 8002926: 68f8 ldr r0, [r7, #12] 8002928: f000 f8ff bl 8002b2a HAL_TIM_PWM_Start (htim, channel1); 800292c: 79fb ldrb r3, [r7, #7] 800292e: 4619 mov r1, r3 8002930: 68f8 ldr r0, [r7, #12] 8002932: f00b fb41 bl 800dfb8 // HAL_TIM_PWM_Stop (htim, channel2); motorStatus = 1; 8002936: 2301 movs r3, #1 8002938: 617b str r3, [r7, #20] 800293a: e004 b.n 8002946 } else { HAL_TIM_PWM_Stop (htim, channel1); 800293c: 79fb ldrb r3, [r7, #7] 800293e: 4619 mov r1, r3 8002940: 68f8 ldr r0, [r7, #12] 8002942: f00b fc47 bl 800e1d4 } HAL_TIM_PWM_Stop (htim, channel2); 8002946: 79bb ldrb r3, [r7, #6] 8002948: 4619 mov r1, r3 800294a: 68f8 ldr r0, [r7, #12] 800294c: f00b fc42 bl 800e1d4 8002950: e051 b.n 80029f6 } else if (motorPWMPulse < 0) { 8002952: 6a7b ldr r3, [r7, #36] @ 0x24 8002954: 2b00 cmp r3, #0 8002956: da2c bge.n 80029b2 // Reverse if (switchLimiterDownStat == 0) { 8002958: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 800295c: 2b00 cmp r3, #0 800295e: d11d bne.n 800299c setMotorYState = Reverse; 8002960: 2302 movs r3, #2 8002962: 74fb strb r3, [r7, #19] motorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorYState, abs (motorPWMPulse) * 10); 8002964: 79f9 ldrb r1, [r7, #7] 8002966: 79b8 ldrb r0, [r7, #6] 8002968: 6a7b ldr r3, [r7, #36] @ 0x24 800296a: ea83 72e3 eor.w r2, r3, r3, asr #31 800296e: eba2 72e3 sub.w r2, r2, r3, asr #31 8002972: 4613 mov r3, r2 8002974: 009b lsls r3, r3, #2 8002976: 4413 add r3, r2 8002978: 005b lsls r3, r3, #1 800297a: 9301 str r3, [sp, #4] 800297c: 7cfb ldrb r3, [r7, #19] 800297e: 9300 str r3, [sp, #0] 8002980: 4603 mov r3, r0 8002982: 460a mov r2, r1 8002984: 68b9 ldr r1, [r7, #8] 8002986: 68f8 ldr r0, [r7, #12] 8002988: f000 f8cf bl 8002b2a HAL_TIM_PWM_Start (htim, channel2); 800298c: 79bb ldrb r3, [r7, #6] 800298e: 4619 mov r1, r3 8002990: 68f8 ldr r0, [r7, #12] 8002992: f00b fb11 bl 800dfb8 motorStatus = 1; 8002996: 2301 movs r3, #1 8002998: 617b str r3, [r7, #20] 800299a: e004 b.n 80029a6 } else { HAL_TIM_PWM_Stop (htim, channel2); 800299c: 79bb ldrb r3, [r7, #6] 800299e: 4619 mov r1, r3 80029a0: 68f8 ldr r0, [r7, #12] 80029a2: f00b fc17 bl 800e1d4 } HAL_TIM_PWM_Stop (htim, channel1); 80029a6: 79fb ldrb r3, [r7, #7] 80029a8: 4619 mov r1, r3 80029aa: 68f8 ldr r0, [r7, #12] 80029ac: f00b fc12 bl 800e1d4 80029b0: e021 b.n 80029f6 } else { // Brake setMotorYState = Brake; 80029b2: 2303 movs r3, #3 80029b4: 74fb strb r3, [r7, #19] motorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorYState, abs (motorPWMPulse) * 10); 80029b6: 79f9 ldrb r1, [r7, #7] 80029b8: 79b8 ldrb r0, [r7, #6] 80029ba: 6a7b ldr r3, [r7, #36] @ 0x24 80029bc: ea83 72e3 eor.w r2, r3, r3, asr #31 80029c0: eba2 72e3 sub.w r2, r2, r3, asr #31 80029c4: 4613 mov r3, r2 80029c6: 009b lsls r3, r3, #2 80029c8: 4413 add r3, r2 80029ca: 005b lsls r3, r3, #1 80029cc: 9301 str r3, [sp, #4] 80029ce: 7cfb ldrb r3, [r7, #19] 80029d0: 9300 str r3, [sp, #0] 80029d2: 4603 mov r3, r0 80029d4: 460a mov r2, r1 80029d6: 68b9 ldr r1, [r7, #8] 80029d8: 68f8 ldr r0, [r7, #12] 80029da: f000 f8a6 bl 8002b2a HAL_TIM_PWM_Start (htim, channel1); 80029de: 79fb ldrb r3, [r7, #7] 80029e0: 4619 mov r1, r3 80029e2: 68f8 ldr r0, [r7, #12] 80029e4: f00b fae8 bl 800dfb8 HAL_TIM_PWM_Start (htim, channel2); 80029e8: 79bb ldrb r3, [r7, #6] 80029ea: 4619 mov r1, r3 80029ec: 68f8 ldr r0, [r7, #12] 80029ee: f00b fae3 bl 800dfb8 motorStatus = 0; 80029f2: 2300 movs r3, #0 80029f4: 617b str r3, [r7, #20] } osTimerStart (motorTimerHandle, motorTimerPeriod * 1000); 80029f6: 6abb ldr r3, [r7, #40] @ 0x28 80029f8: f44f 727a mov.w r2, #1000 @ 0x3e8 80029fc: fb02 f303 mul.w r3, r2, r3 8002a00: 4619 mov r1, r3 8002a02: 6a38 ldr r0, [r7, #32] 8002a04: f00f fd7c bl 8012500 8002a08: e089 b.n 8002b1e } else if ((motorTimerPeriod == 0) && (motorPWMPulse == 0)) { 8002a0a: 6abb ldr r3, [r7, #40] @ 0x28 8002a0c: 2b00 cmp r3, #0 8002a0e: d126 bne.n 8002a5e 8002a10: 6a7b ldr r3, [r7, #36] @ 0x24 8002a12: 2b00 cmp r3, #0 8002a14: d123 bne.n 8002a5e motorAction (htim, motorTimerConfigOC, channel1, channel2, HiZ, abs (motorPWMPulse) * 10); 8002a16: 79f9 ldrb r1, [r7, #7] 8002a18: 79b8 ldrb r0, [r7, #6] 8002a1a: 6a7b ldr r3, [r7, #36] @ 0x24 8002a1c: ea83 72e3 eor.w r2, r3, r3, asr #31 8002a20: eba2 72e3 sub.w r2, r2, r3, asr #31 8002a24: 4613 mov r3, r2 8002a26: 009b lsls r3, r3, #2 8002a28: 4413 add r3, r2 8002a2a: 005b lsls r3, r3, #1 8002a2c: 9301 str r3, [sp, #4] 8002a2e: 2300 movs r3, #0 8002a30: 9300 str r3, [sp, #0] 8002a32: 4603 mov r3, r0 8002a34: 460a mov r2, r1 8002a36: 68b9 ldr r1, [r7, #8] 8002a38: 68f8 ldr r0, [r7, #12] 8002a3a: f000 f876 bl 8002b2a HAL_TIM_PWM_Stop (htim, channel1); 8002a3e: 79fb ldrb r3, [r7, #7] 8002a40: 4619 mov r1, r3 8002a42: 68f8 ldr r0, [r7, #12] 8002a44: f00b fbc6 bl 800e1d4 HAL_TIM_PWM_Stop (htim, channel2); 8002a48: 79bb ldrb r3, [r7, #6] 8002a4a: 4619 mov r1, r3 8002a4c: 68f8 ldr r0, [r7, #12] 8002a4e: f00b fbc1 bl 800e1d4 osTimerStop (motorTimerHandle); 8002a52: 6a38 ldr r0, [r7, #32] 8002a54: f00f fd82 bl 801255c motorStatus = 0; 8002a58: 2300 movs r3, #0 8002a5a: 617b str r3, [r7, #20] 8002a5c: e05f b.n 8002b1e } else if (motorTimerPeriod == -1) { 8002a5e: 6abb ldr r3, [r7, #40] @ 0x28 8002a60: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8002a64: d15b bne.n 8002b1e if (motorPWMPulse > 0) { 8002a66: 6a7b ldr r3, [r7, #36] @ 0x24 8002a68: 2b00 cmp r3, #0 8002a6a: dd2c ble.n 8002ac6 // Forward if (switchLimiterUpStat == 0) { 8002a6c: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 8002a70: 2b00 cmp r3, #0 8002a72: d11d bne.n 8002ab0 setMotorYState = Forward; 8002a74: 2301 movs r3, #1 8002a76: 74fb strb r3, [r7, #19] motorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorYState, abs (motorPWMPulse) * 10); 8002a78: 79f9 ldrb r1, [r7, #7] 8002a7a: 79b8 ldrb r0, [r7, #6] 8002a7c: 6a7b ldr r3, [r7, #36] @ 0x24 8002a7e: ea83 72e3 eor.w r2, r3, r3, asr #31 8002a82: eba2 72e3 sub.w r2, r2, r3, asr #31 8002a86: 4613 mov r3, r2 8002a88: 009b lsls r3, r3, #2 8002a8a: 4413 add r3, r2 8002a8c: 005b lsls r3, r3, #1 8002a8e: 9301 str r3, [sp, #4] 8002a90: 7cfb ldrb r3, [r7, #19] 8002a92: 9300 str r3, [sp, #0] 8002a94: 4603 mov r3, r0 8002a96: 460a mov r2, r1 8002a98: 68b9 ldr r1, [r7, #8] 8002a9a: 68f8 ldr r0, [r7, #12] 8002a9c: f000 f845 bl 8002b2a HAL_TIM_PWM_Start (htim, channel1); 8002aa0: 79fb ldrb r3, [r7, #7] 8002aa2: 4619 mov r1, r3 8002aa4: 68f8 ldr r0, [r7, #12] 8002aa6: f00b fa87 bl 800dfb8 motorStatus = 1; 8002aaa: 2301 movs r3, #1 8002aac: 617b str r3, [r7, #20] 8002aae: e004 b.n 8002aba } else { HAL_TIM_PWM_Stop (htim, channel1); 8002ab0: 79fb ldrb r3, [r7, #7] 8002ab2: 4619 mov r1, r3 8002ab4: 68f8 ldr r0, [r7, #12] 8002ab6: f00b fb8d bl 800e1d4 } HAL_TIM_PWM_Stop (htim, channel2); 8002aba: 79bb ldrb r3, [r7, #6] 8002abc: 4619 mov r1, r3 8002abe: 68f8 ldr r0, [r7, #12] 8002ac0: f00b fb88 bl 800e1d4 8002ac4: e02b b.n 8002b1e } else { // Reverse if (switchLimiterDownStat == 0) { 8002ac6: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 8002aca: 2b00 cmp r3, #0 8002acc: d11d bne.n 8002b0a setMotorYState = Reverse; 8002ace: 2302 movs r3, #2 8002ad0: 74fb strb r3, [r7, #19] motorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorYState, abs (motorPWMPulse) * 10); 8002ad2: 79f9 ldrb r1, [r7, #7] 8002ad4: 79b8 ldrb r0, [r7, #6] 8002ad6: 6a7b ldr r3, [r7, #36] @ 0x24 8002ad8: ea83 72e3 eor.w r2, r3, r3, asr #31 8002adc: eba2 72e3 sub.w r2, r2, r3, asr #31 8002ae0: 4613 mov r3, r2 8002ae2: 009b lsls r3, r3, #2 8002ae4: 4413 add r3, r2 8002ae6: 005b lsls r3, r3, #1 8002ae8: 9301 str r3, [sp, #4] 8002aea: 7cfb ldrb r3, [r7, #19] 8002aec: 9300 str r3, [sp, #0] 8002aee: 4603 mov r3, r0 8002af0: 460a mov r2, r1 8002af2: 68b9 ldr r1, [r7, #8] 8002af4: 68f8 ldr r0, [r7, #12] 8002af6: f000 f818 bl 8002b2a HAL_TIM_PWM_Start (htim, channel2); 8002afa: 79bb ldrb r3, [r7, #6] 8002afc: 4619 mov r1, r3 8002afe: 68f8 ldr r0, [r7, #12] 8002b00: f00b fa5a bl 800dfb8 motorStatus = 1; 8002b04: 2301 movs r3, #1 8002b06: 617b str r3, [r7, #20] 8002b08: e004 b.n 8002b14 } else { HAL_TIM_PWM_Stop (htim, channel2); 8002b0a: 79bb ldrb r3, [r7, #6] 8002b0c: 4619 mov r1, r3 8002b0e: 68f8 ldr r0, [r7, #12] 8002b10: f00b fb60 bl 800e1d4 } HAL_TIM_PWM_Stop (htim, channel1); 8002b14: 79fb ldrb r3, [r7, #7] 8002b16: 4619 mov r1, r3 8002b18: 68f8 ldr r0, [r7, #12] 8002b1a: f00b fb5b bl 800e1d4 } } return motorStatus; 8002b1e: 697b ldr r3, [r7, #20] 8002b20: b2db uxtb r3, r3 } 8002b22: 4618 mov r0, r3 8002b24: 3718 adds r7, #24 8002b26: 46bd mov sp, r7 8002b28: bd80 pop {r7, pc} 08002b2a : void motorAction(TIM_HandleTypeDef *tim, TIM_OC_InitTypeDef *timerConf, uint32_t channel1, uint32_t channel2, MotorDriverState setState, uint32_t pulse) { 8002b2a: b580 push {r7, lr} 8002b2c: b084 sub sp, #16 8002b2e: af00 add r7, sp, #0 8002b30: 60f8 str r0, [r7, #12] 8002b32: 60b9 str r1, [r7, #8] 8002b34: 607a str r2, [r7, #4] 8002b36: 603b str r3, [r7, #0] timerConf->Pulse = pulse; 8002b38: 68bb ldr r3, [r7, #8] 8002b3a: 69fa ldr r2, [r7, #28] 8002b3c: 605a str r2, [r3, #4] switch(setState) 8002b3e: 7e3b ldrb r3, [r7, #24] 8002b40: 2b02 cmp r3, #2 8002b42: dc02 bgt.n 8002b4a 8002b44: 2b00 cmp r3, #0 8002b46: da03 bge.n 8002b50 8002b48: e038 b.n 8002bbc 8002b4a: 2b03 cmp r3, #3 8002b4c: d01b beq.n 8002b86 8002b4e: e035 b.n 8002bbc { case Forward: case Reverse: case HiZ: timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8002b50: 68bb ldr r3, [r7, #8] 8002b52: 2200 movs r2, #0 8002b54: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 8002b56: 687a ldr r2, [r7, #4] 8002b58: 68b9 ldr r1, [r7, #8] 8002b5a: 68f8 ldr r0, [r7, #12] 8002b5c: f00b fcd8 bl 800e510 8002b60: 4603 mov r3, r0 8002b62: 2b00 cmp r3, #0 8002b64: d001 beq.n 8002b6a Error_Handler (); 8002b66: f7fe ff5b bl 8001a20 } timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8002b6a: 68bb ldr r3, [r7, #8] 8002b6c: 2200 movs r2, #0 8002b6e: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 8002b70: 683a ldr r2, [r7, #0] 8002b72: 68b9 ldr r1, [r7, #8] 8002b74: 68f8 ldr r0, [r7, #12] 8002b76: f00b fccb bl 800e510 8002b7a: 4603 mov r3, r0 8002b7c: 2b00 cmp r3, #0 8002b7e: d038 beq.n 8002bf2 Error_Handler (); 8002b80: f7fe ff4e bl 8001a20 } break; 8002b84: e035 b.n 8002bf2 case Brake: timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 8002b86: 68bb ldr r3, [r7, #8] 8002b88: 2202 movs r2, #2 8002b8a: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 8002b8c: 687a ldr r2, [r7, #4] 8002b8e: 68b9 ldr r1, [r7, #8] 8002b90: 68f8 ldr r0, [r7, #12] 8002b92: f00b fcbd bl 800e510 8002b96: 4603 mov r3, r0 8002b98: 2b00 cmp r3, #0 8002b9a: d001 beq.n 8002ba0 Error_Handler (); 8002b9c: f7fe ff40 bl 8001a20 } timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 8002ba0: 68bb ldr r3, [r7, #8] 8002ba2: 2202 movs r2, #2 8002ba4: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 8002ba6: 683a ldr r2, [r7, #0] 8002ba8: 68b9 ldr r1, [r7, #8] 8002baa: 68f8 ldr r0, [r7, #12] 8002bac: f00b fcb0 bl 800e510 8002bb0: 4603 mov r3, r0 8002bb2: 2b00 cmp r3, #0 8002bb4: d01f beq.n 8002bf6 Error_Handler (); 8002bb6: f7fe ff33 bl 8001a20 } break; 8002bba: e01c b.n 8002bf6 default: timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8002bbc: 68bb ldr r3, [r7, #8] 8002bbe: 2200 movs r2, #0 8002bc0: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 8002bc2: 687a ldr r2, [r7, #4] 8002bc4: 68b9 ldr r1, [r7, #8] 8002bc6: 68f8 ldr r0, [r7, #12] 8002bc8: f00b fca2 bl 800e510 8002bcc: 4603 mov r3, r0 8002bce: 2b00 cmp r3, #0 8002bd0: d001 beq.n 8002bd6 Error_Handler (); 8002bd2: f7fe ff25 bl 8001a20 } timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8002bd6: 68bb ldr r3, [r7, #8] 8002bd8: 2200 movs r2, #0 8002bda: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 8002bdc: 683a ldr r2, [r7, #0] 8002bde: 68b9 ldr r1, [r7, #8] 8002be0: 68f8 ldr r0, [r7, #12] 8002be2: f00b fc95 bl 800e510 8002be6: 4603 mov r3, r0 8002be8: 2b00 cmp r3, #0 8002bea: d006 beq.n 8002bfa Error_Handler (); 8002bec: f7fe ff18 bl 8001a20 } break; 8002bf0: e003 b.n 8002bfa break; 8002bf2: bf00 nop 8002bf4: e002 b.n 8002bfc break; 8002bf6: bf00 nop 8002bf8: e000 b.n 8002bfc break; 8002bfa: bf00 nop } } 8002bfc: bf00 nop 8002bfe: 3710 adds r7, #16 8002c00: 46bd mov sp, r7 8002c02: bd80 pop {r7, pc} 08002c04 : buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); } *buffPos = newBuffPos; } void WriteDataToBuffer (uint8_t* buff, uint16_t* buffPos, void* data, uint8_t dataSize) { 8002c04: b480 push {r7} 8002c06: b089 sub sp, #36 @ 0x24 8002c08: af00 add r7, sp, #0 8002c0a: 60f8 str r0, [r7, #12] 8002c0c: 60b9 str r1, [r7, #8] 8002c0e: 607a str r2, [r7, #4] 8002c10: 70fb strb r3, [r7, #3] uint32_t* uDataPtr = data; 8002c12: 687b ldr r3, [r7, #4] 8002c14: 61bb str r3, [r7, #24] uint32_t uData = *uDataPtr; 8002c16: 69bb ldr r3, [r7, #24] 8002c18: 681b ldr r3, [r3, #0] 8002c1a: 617b str r3, [r7, #20] uint8_t i = 0; 8002c1c: 2300 movs r3, #0 8002c1e: 77fb strb r3, [r7, #31] uint8_t newBuffPos = *buffPos; 8002c20: 68bb ldr r3, [r7, #8] 8002c22: 881b ldrh r3, [r3, #0] 8002c24: 77bb strb r3, [r7, #30] for (i = 0; i < dataSize; i++) { 8002c26: 2300 movs r3, #0 8002c28: 77fb strb r3, [r7, #31] 8002c2a: e00e b.n 8002c4a buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); 8002c2c: 7ffb ldrb r3, [r7, #31] 8002c2e: 00db lsls r3, r3, #3 8002c30: 697a ldr r2, [r7, #20] 8002c32: 40da lsrs r2, r3 8002c34: 7fbb ldrb r3, [r7, #30] 8002c36: 1c59 adds r1, r3, #1 8002c38: 77b9 strb r1, [r7, #30] 8002c3a: 4619 mov r1, r3 8002c3c: 68fb ldr r3, [r7, #12] 8002c3e: 440b add r3, r1 8002c40: b2d2 uxtb r2, r2 8002c42: 701a strb r2, [r3, #0] for (i = 0; i < dataSize; i++) { 8002c44: 7ffb ldrb r3, [r7, #31] 8002c46: 3301 adds r3, #1 8002c48: 77fb strb r3, [r7, #31] 8002c4a: 7ffa ldrb r2, [r7, #31] 8002c4c: 78fb ldrb r3, [r7, #3] 8002c4e: 429a cmp r2, r3 8002c50: d3ec bcc.n 8002c2c } *buffPos = newBuffPos; 8002c52: 7fbb ldrb r3, [r7, #30] 8002c54: b29a uxth r2, r3 8002c56: 68bb ldr r3, [r7, #8] 8002c58: 801a strh r2, [r3, #0] } 8002c5a: bf00 nop 8002c5c: 3724 adds r7, #36 @ 0x24 8002c5e: 46bd mov sp, r7 8002c60: f85d 7b04 ldr.w r7, [sp], #4 8002c64: 4770 bx lr 08002c66 : *data = CONVERT_BYTES_TO_SHORT_WORD(&buff[*buffPos]); *buffPos += sizeof(uint16_t); } void ReadWordFromBufer(uint8_t* buff, uint16_t* buffPos, uint32_t* data) { 8002c66: b480 push {r7} 8002c68: b085 sub sp, #20 8002c6a: af00 add r7, sp, #0 8002c6c: 60f8 str r0, [r7, #12] 8002c6e: 60b9 str r1, [r7, #8] 8002c70: 607a str r2, [r7, #4] *data = CONVERT_BYTES_TO_WORD(&buff[*buffPos]); 8002c72: 68bb ldr r3, [r7, #8] 8002c74: 881b ldrh r3, [r3, #0] 8002c76: 3303 adds r3, #3 8002c78: 68fa ldr r2, [r7, #12] 8002c7a: 4413 add r3, r2 8002c7c: 781b ldrb r3, [r3, #0] 8002c7e: 061a lsls r2, r3, #24 8002c80: 68bb ldr r3, [r7, #8] 8002c82: 881b ldrh r3, [r3, #0] 8002c84: 3302 adds r3, #2 8002c86: 68f9 ldr r1, [r7, #12] 8002c88: 440b add r3, r1 8002c8a: 781b ldrb r3, [r3, #0] 8002c8c: 041b lsls r3, r3, #16 8002c8e: 431a orrs r2, r3 8002c90: 68bb ldr r3, [r7, #8] 8002c92: 881b ldrh r3, [r3, #0] 8002c94: 3301 adds r3, #1 8002c96: 68f9 ldr r1, [r7, #12] 8002c98: 440b add r3, r1 8002c9a: 781b ldrb r3, [r3, #0] 8002c9c: 021b lsls r3, r3, #8 8002c9e: 4313 orrs r3, r2 8002ca0: 68ba ldr r2, [r7, #8] 8002ca2: 8812 ldrh r2, [r2, #0] 8002ca4: 4611 mov r1, r2 8002ca6: 68fa ldr r2, [r7, #12] 8002ca8: 440a add r2, r1 8002caa: 7812 ldrb r2, [r2, #0] 8002cac: 4313 orrs r3, r2 8002cae: 461a mov r2, r3 8002cb0: 687b ldr r3, [r7, #4] 8002cb2: 601a str r2, [r3, #0] *buffPos += sizeof(uint32_t); 8002cb4: 68bb ldr r3, [r7, #8] 8002cb6: 881b ldrh r3, [r3, #0] 8002cb8: 3304 adds r3, #4 8002cba: b29a uxth r2, r3 8002cbc: 68bb ldr r3, [r7, #8] 8002cbe: 801a strh r2, [r3, #0] } 8002cc0: bf00 nop 8002cc2: 3714 adds r7, #20 8002cc4: 46bd mov sp, r7 8002cc6: f85d 7b04 ldr.w r7, [sp], #4 8002cca: 4770 bx lr 08002ccc : txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); return txBufferPos; } uint16_t PrepareRespFrame (uint8_t* txBuffer, uint16_t frameId, SerialProtocolCommands frameCommand, SerialProtocolRespStatus respStatus, uint8_t* dataBuffer, uint16_t dataLength) { 8002ccc: b580 push {r7, lr} 8002cce: b084 sub sp, #16 8002cd0: af00 add r7, sp, #0 8002cd2: 6078 str r0, [r7, #4] 8002cd4: 4608 mov r0, r1 8002cd6: 4611 mov r1, r2 8002cd8: 461a mov r2, r3 8002cda: 4603 mov r3, r0 8002cdc: 807b strh r3, [r7, #2] 8002cde: 460b mov r3, r1 8002ce0: 707b strb r3, [r7, #1] 8002ce2: 4613 mov r3, r2 8002ce4: 703b strb r3, [r7, #0] uint16_t crc = 0; 8002ce6: 2300 movs r3, #0 8002ce8: 81bb strh r3, [r7, #12] uint16_t txBufferPos = 0; 8002cea: 2300 movs r3, #0 8002cec: 81fb strh r3, [r7, #14] uint16_t frameCmd = ((uint16_t)frameCommand) | 0x8000; // MSB set means response 8002cee: 787b ldrb r3, [r7, #1] 8002cf0: b21a sxth r2, r3 8002cf2: 4b43 ldr r3, [pc, #268] @ (8002e00 ) 8002cf4: 4313 orrs r3, r2 8002cf6: b21b sxth r3, r3 8002cf8: 817b strh r3, [r7, #10] memset (txBuffer, 0x00, dataLength); 8002cfa: 8bbb ldrh r3, [r7, #28] 8002cfc: 461a mov r2, r3 8002cfe: 2100 movs r1, #0 8002d00: 6878 ldr r0, [r7, #4] 8002d02: f013 fd28 bl 8016756 txBuffer[txBufferPos++] = FRAME_INDICATOR; 8002d06: 89fb ldrh r3, [r7, #14] 8002d08: 1c5a adds r2, r3, #1 8002d0a: 81fa strh r2, [r7, #14] 8002d0c: 461a mov r2, r3 8002d0e: 687b ldr r3, [r7, #4] 8002d10: 4413 add r3, r2 8002d12: 22aa movs r2, #170 @ 0xaa 8002d14: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameId); 8002d16: 89fb ldrh r3, [r7, #14] 8002d18: 1c5a adds r2, r3, #1 8002d1a: 81fa strh r2, [r7, #14] 8002d1c: 461a mov r2, r3 8002d1e: 687b ldr r3, [r7, #4] 8002d20: 4413 add r3, r2 8002d22: 887a ldrh r2, [r7, #2] 8002d24: b2d2 uxtb r2, r2 8002d26: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameId); 8002d28: 887b ldrh r3, [r7, #2] 8002d2a: 0a1b lsrs r3, r3, #8 8002d2c: b29a uxth r2, r3 8002d2e: 89fb ldrh r3, [r7, #14] 8002d30: 1c59 adds r1, r3, #1 8002d32: 81f9 strh r1, [r7, #14] 8002d34: 4619 mov r1, r3 8002d36: 687b ldr r3, [r7, #4] 8002d38: 440b add r3, r1 8002d3a: b2d2 uxtb r2, r2 8002d3c: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameCmd); 8002d3e: 89fb ldrh r3, [r7, #14] 8002d40: 1c5a adds r2, r3, #1 8002d42: 81fa strh r2, [r7, #14] 8002d44: 461a mov r2, r3 8002d46: 687b ldr r3, [r7, #4] 8002d48: 4413 add r3, r2 8002d4a: 897a ldrh r2, [r7, #10] 8002d4c: b2d2 uxtb r2, r2 8002d4e: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameCmd); 8002d50: 897b ldrh r3, [r7, #10] 8002d52: 0a1b lsrs r3, r3, #8 8002d54: b29a uxth r2, r3 8002d56: 89fb ldrh r3, [r7, #14] 8002d58: 1c59 adds r1, r3, #1 8002d5a: 81f9 strh r1, [r7, #14] 8002d5c: 4619 mov r1, r3 8002d5e: 687b ldr r3, [r7, #4] 8002d60: 440b add r3, r1 8002d62: b2d2 uxtb r2, r2 8002d64: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (dataLength); 8002d66: 89fb ldrh r3, [r7, #14] 8002d68: 1c5a adds r2, r3, #1 8002d6a: 81fa strh r2, [r7, #14] 8002d6c: 461a mov r2, r3 8002d6e: 687b ldr r3, [r7, #4] 8002d70: 4413 add r3, r2 8002d72: 8bba ldrh r2, [r7, #28] 8002d74: b2d2 uxtb r2, r2 8002d76: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (dataLength); 8002d78: 8bbb ldrh r3, [r7, #28] 8002d7a: 0a1b lsrs r3, r3, #8 8002d7c: b29a uxth r2, r3 8002d7e: 89fb ldrh r3, [r7, #14] 8002d80: 1c59 adds r1, r3, #1 8002d82: 81f9 strh r1, [r7, #14] 8002d84: 4619 mov r1, r3 8002d86: 687b ldr r3, [r7, #4] 8002d88: 440b add r3, r1 8002d8a: b2d2 uxtb r2, r2 8002d8c: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = (uint8_t)respStatus; 8002d8e: 89fb ldrh r3, [r7, #14] 8002d90: 1c5a adds r2, r3, #1 8002d92: 81fa strh r2, [r7, #14] 8002d94: 461a mov r2, r3 8002d96: 687b ldr r3, [r7, #4] 8002d98: 4413 add r3, r2 8002d9a: 783a ldrb r2, [r7, #0] 8002d9c: 701a strb r2, [r3, #0] if (dataLength > 0) { 8002d9e: 8bbb ldrh r3, [r7, #28] 8002da0: 2b00 cmp r3, #0 8002da2: d00b beq.n 8002dbc memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength); 8002da4: 89fb ldrh r3, [r7, #14] 8002da6: 687a ldr r2, [r7, #4] 8002da8: 4413 add r3, r2 8002daa: 8bba ldrh r2, [r7, #28] 8002dac: 69b9 ldr r1, [r7, #24] 8002dae: 4618 mov r0, r3 8002db0: f013 fda3 bl 80168fa txBufferPos += dataLength; 8002db4: 89fa ldrh r2, [r7, #14] 8002db6: 8bbb ldrh r3, [r7, #28] 8002db8: 4413 add r3, r2 8002dba: 81fb strh r3, [r7, #14] } crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)txBuffer, txBufferPos); 8002dbc: 89fb ldrh r3, [r7, #14] 8002dbe: 461a mov r2, r3 8002dc0: 6879 ldr r1, [r7, #4] 8002dc2: 4810 ldr r0, [pc, #64] @ (8002e04 ) 8002dc4: f003 fc66 bl 8006694 8002dc8: 4603 mov r3, r0 8002dca: 81bb strh r3, [r7, #12] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (crc); 8002dcc: 89fb ldrh r3, [r7, #14] 8002dce: 1c5a adds r2, r3, #1 8002dd0: 81fa strh r2, [r7, #14] 8002dd2: 461a mov r2, r3 8002dd4: 687b ldr r3, [r7, #4] 8002dd6: 4413 add r3, r2 8002dd8: 89ba ldrh r2, [r7, #12] 8002dda: b2d2 uxtb r2, r2 8002ddc: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); 8002dde: 89bb ldrh r3, [r7, #12] 8002de0: 0a1b lsrs r3, r3, #8 8002de2: b29a uxth r2, r3 8002de4: 89fb ldrh r3, [r7, #14] 8002de6: 1c59 adds r1, r3, #1 8002de8: 81f9 strh r1, [r7, #14] 8002dea: 4619 mov r1, r3 8002dec: 687b ldr r3, [r7, #4] 8002dee: 440b add r3, r1 8002df0: b2d2 uxtb r2, r2 8002df2: 701a strb r2, [r3, #0] return txBufferPos; 8002df4: 89fb ldrh r3, [r7, #14] } 8002df6: 4618 mov r0, r3 8002df8: 3710 adds r7, #16 8002dfa: 46bd mov sp, r7 8002dfc: bd80 pop {r7, pc} 8002dfe: bf00 nop 8002e00: ffff8000 .word 0xffff8000 8002e04: 240003d4 .word 0x240003d4 08002e08 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8002e08: b580 push {r7, lr} 8002e0a: b086 sub sp, #24 8002e0c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ PWREx_AVDTypeDef sConfigAVD = {0}; 8002e0e: f107 0310 add.w r3, r7, #16 8002e12: 2200 movs r2, #0 8002e14: 601a str r2, [r3, #0] 8002e16: 605a str r2, [r3, #4] PWR_PVDTypeDef sConfigPVD = {0}; 8002e18: f107 0308 add.w r3, r7, #8 8002e1c: 2200 movs r2, #0 8002e1e: 601a str r2, [r3, #0] 8002e20: 605a str r2, [r3, #4] __HAL_RCC_SYSCFG_CLK_ENABLE(); 8002e22: 4b26 ldr r3, [pc, #152] @ (8002ebc ) 8002e24: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8002e28: 4a24 ldr r2, [pc, #144] @ (8002ebc ) 8002e2a: f043 0302 orr.w r3, r3, #2 8002e2e: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8002e32: 4b22 ldr r3, [pc, #136] @ (8002ebc ) 8002e34: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8002e38: f003 0302 and.w r3, r3, #2 8002e3c: 607b str r3, [r7, #4] 8002e3e: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 8002e40: 2200 movs r2, #0 8002e42: 210f movs r1, #15 8002e44: f06f 0001 mvn.w r0, #1 8002e48: f003 fb20 bl 800648c /* Peripheral interrupt init */ /* RCC_IRQn interrupt configuration */ HAL_NVIC_SetPriority(RCC_IRQn, 5, 0); 8002e4c: 2200 movs r2, #0 8002e4e: 2105 movs r1, #5 8002e50: 2005 movs r0, #5 8002e52: f003 fb1b bl 800648c HAL_NVIC_EnableIRQ(RCC_IRQn); 8002e56: 2005 movs r0, #5 8002e58: f003 fb32 bl 80064c0 /** AVD Configuration */ sConfigAVD.AVDLevel = PWR_AVDLEVEL_3; 8002e5c: f44f 23c0 mov.w r3, #393216 @ 0x60000 8002e60: 613b str r3, [r7, #16] sConfigAVD.Mode = PWR_AVD_MODE_NORMAL; 8002e62: 2300 movs r3, #0 8002e64: 617b str r3, [r7, #20] HAL_PWREx_ConfigAVD(&sConfigAVD); 8002e66: f107 0310 add.w r3, r7, #16 8002e6a: 4618 mov r0, r3 8002e6c: f007 f91a bl 800a0a4 /** Enable the AVD Output */ HAL_PWREx_EnableAVD(); 8002e70: f007 f98e bl 800a190 /** PVD Configuration */ sConfigPVD.PVDLevel = PWR_PVDLEVEL_6; 8002e74: 23c0 movs r3, #192 @ 0xc0 8002e76: 60bb str r3, [r7, #8] sConfigPVD.Mode = PWR_PVD_MODE_NORMAL; 8002e78: 2300 movs r3, #0 8002e7a: 60fb str r3, [r7, #12] HAL_PWR_ConfigPVD(&sConfigPVD); 8002e7c: f107 0308 add.w r3, r7, #8 8002e80: 4618 mov r0, r3 8002e82: f007 f84b bl 8009f1c /** Enable the PVD Output */ HAL_PWR_EnablePVD(); 8002e86: f007 f8c3 bl 800a010 /** Enable the VREF clock */ __HAL_RCC_VREF_CLK_ENABLE(); 8002e8a: 4b0c ldr r3, [pc, #48] @ (8002ebc ) 8002e8c: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8002e90: 4a0a ldr r2, [pc, #40] @ (8002ebc ) 8002e92: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8002e96: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8002e9a: 4b08 ldr r3, [pc, #32] @ (8002ebc ) 8002e9c: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8002ea0: f403 4300 and.w r3, r3, #32768 @ 0x8000 8002ea4: 603b str r3, [r7, #0] 8002ea6: 683b ldr r3, [r7, #0] /** Disable the Internal Voltage Reference buffer */ HAL_SYSCFG_DisableVREFBUF(); 8002ea8: f001 fe08 bl 8004abc /** Configure the internal voltage reference buffer high impedance mode */ HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE); 8002eac: 2002 movs r0, #2 8002eae: f001 fdf1 bl 8004a94 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8002eb2: bf00 nop 8002eb4: 3718 adds r7, #24 8002eb6: 46bd mov sp, r7 8002eb8: bd80 pop {r7, pc} 8002eba: bf00 nop 8002ebc: 58024400 .word 0x58024400 08002ec0 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8002ec0: b580 push {r7, lr} 8002ec2: b092 sub sp, #72 @ 0x48 8002ec4: af00 add r7, sp, #0 8002ec6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002ec8: f107 0334 add.w r3, r7, #52 @ 0x34 8002ecc: 2200 movs r2, #0 8002ece: 601a str r2, [r3, #0] 8002ed0: 605a str r2, [r3, #4] 8002ed2: 609a str r2, [r3, #8] 8002ed4: 60da str r2, [r3, #12] 8002ed6: 611a str r2, [r3, #16] if(hadc->Instance==ADC1) 8002ed8: 687b ldr r3, [r7, #4] 8002eda: 681b ldr r3, [r3, #0] 8002edc: 4a9d ldr r2, [pc, #628] @ (8003154 ) 8002ede: 4293 cmp r3, r2 8002ee0: f040 8099 bne.w 8003016 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; 8002ee4: 4b9c ldr r3, [pc, #624] @ (8003158 ) 8002ee6: 681b ldr r3, [r3, #0] 8002ee8: 3301 adds r3, #1 8002eea: 4a9b ldr r2, [pc, #620] @ (8003158 ) 8002eec: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8002eee: 4b9a ldr r3, [pc, #616] @ (8003158 ) 8002ef0: 681b ldr r3, [r3, #0] 8002ef2: 2b01 cmp r3, #1 8002ef4: d10e bne.n 8002f14 __HAL_RCC_ADC12_CLK_ENABLE(); 8002ef6: 4b99 ldr r3, [pc, #612] @ (800315c ) 8002ef8: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8002efc: 4a97 ldr r2, [pc, #604] @ (800315c ) 8002efe: f043 0320 orr.w r3, r3, #32 8002f02: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8002f06: 4b95 ldr r3, [pc, #596] @ (800315c ) 8002f08: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8002f0c: f003 0320 and.w r3, r3, #32 8002f10: 633b str r3, [r7, #48] @ 0x30 8002f12: 6b3b ldr r3, [r7, #48] @ 0x30 } __HAL_RCC_GPIOA_CLK_ENABLE(); 8002f14: 4b91 ldr r3, [pc, #580] @ (800315c ) 8002f16: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8002f1a: 4a90 ldr r2, [pc, #576] @ (800315c ) 8002f1c: f043 0301 orr.w r3, r3, #1 8002f20: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8002f24: 4b8d ldr r3, [pc, #564] @ (800315c ) 8002f26: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8002f2a: f003 0301 and.w r3, r3, #1 8002f2e: 62fb str r3, [r7, #44] @ 0x2c 8002f30: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 8002f32: 4b8a ldr r3, [pc, #552] @ (800315c ) 8002f34: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8002f38: 4a88 ldr r2, [pc, #544] @ (800315c ) 8002f3a: f043 0304 orr.w r3, r3, #4 8002f3e: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8002f42: 4b86 ldr r3, [pc, #536] @ (800315c ) 8002f44: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8002f48: f003 0304 and.w r3, r3, #4 8002f4c: 62bb str r3, [r7, #40] @ 0x28 8002f4e: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOB_CLK_ENABLE(); 8002f50: 4b82 ldr r3, [pc, #520] @ (800315c ) 8002f52: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8002f56: 4a81 ldr r2, [pc, #516] @ (800315c ) 8002f58: f043 0302 orr.w r3, r3, #2 8002f5c: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8002f60: 4b7e ldr r3, [pc, #504] @ (800315c ) 8002f62: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8002f66: f003 0302 and.w r3, r3, #2 8002f6a: 627b str r3, [r7, #36] @ 0x24 8002f6c: 6a7b ldr r3, [r7, #36] @ 0x24 PA3 ------> ADC1_INP15 PA7 ------> ADC1_INP7 PC5 ------> ADC1_INP8 PB0 ------> ADC1_INP9 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 8002f6e: 238f movs r3, #143 @ 0x8f 8002f70: 637b str r3, [r7, #52] @ 0x34 |GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8002f72: 2303 movs r3, #3 8002f74: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002f76: 2300 movs r3, #0 8002f78: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002f7a: f107 0334 add.w r3, r7, #52 @ 0x34 8002f7e: 4619 mov r1, r3 8002f80: 4877 ldr r0, [pc, #476] @ (8003160 ) 8002f82: f006 fdb5 bl 8009af0 GPIO_InitStruct.Pin = GPIO_PIN_5; 8002f86: 2320 movs r3, #32 8002f88: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8002f8a: 2303 movs r3, #3 8002f8c: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002f8e: 2300 movs r3, #0 8002f90: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8002f92: f107 0334 add.w r3, r7, #52 @ 0x34 8002f96: 4619 mov r1, r3 8002f98: 4872 ldr r0, [pc, #456] @ (8003164 ) 8002f9a: f006 fda9 bl 8009af0 GPIO_InitStruct.Pin = GPIO_PIN_0; 8002f9e: 2301 movs r3, #1 8002fa0: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8002fa2: 2303 movs r3, #3 8002fa4: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002fa6: 2300 movs r3, #0 8002fa8: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002faa: f107 0334 add.w r3, r7, #52 @ 0x34 8002fae: 4619 mov r1, r3 8002fb0: 486d ldr r0, [pc, #436] @ (8003168 ) 8002fb2: f006 fd9d bl 8009af0 /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Stream0; 8002fb6: 4b6d ldr r3, [pc, #436] @ (800316c ) 8002fb8: 4a6d ldr r2, [pc, #436] @ (8003170 ) 8002fba: 601a str r2, [r3, #0] hdma_adc1.Init.Request = DMA_REQUEST_ADC1; 8002fbc: 4b6b ldr r3, [pc, #428] @ (800316c ) 8002fbe: 2209 movs r2, #9 8002fc0: 605a str r2, [r3, #4] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 8002fc2: 4b6a ldr r3, [pc, #424] @ (800316c ) 8002fc4: 2200 movs r2, #0 8002fc6: 609a str r2, [r3, #8] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8002fc8: 4b68 ldr r3, [pc, #416] @ (800316c ) 8002fca: 2200 movs r2, #0 8002fcc: 60da str r2, [r3, #12] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8002fce: 4b67 ldr r3, [pc, #412] @ (800316c ) 8002fd0: f44f 6280 mov.w r2, #1024 @ 0x400 8002fd4: 611a str r2, [r3, #16] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8002fd6: 4b65 ldr r3, [pc, #404] @ (800316c ) 8002fd8: f44f 6200 mov.w r2, #2048 @ 0x800 8002fdc: 615a str r2, [r3, #20] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8002fde: 4b63 ldr r3, [pc, #396] @ (800316c ) 8002fe0: f44f 5200 mov.w r2, #8192 @ 0x2000 8002fe4: 619a str r2, [r3, #24] hdma_adc1.Init.Mode = DMA_NORMAL; 8002fe6: 4b61 ldr r3, [pc, #388] @ (800316c ) 8002fe8: 2200 movs r2, #0 8002fea: 61da str r2, [r3, #28] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; 8002fec: 4b5f ldr r3, [pc, #380] @ (800316c ) 8002fee: 2200 movs r2, #0 8002ff0: 621a str r2, [r3, #32] hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8002ff2: 4b5e ldr r3, [pc, #376] @ (800316c ) 8002ff4: 2200 movs r2, #0 8002ff6: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 8002ff8: 485c ldr r0, [pc, #368] @ (800316c ) 8002ffa: f003 ff3d bl 8006e78 8002ffe: 4603 mov r3, r0 8003000: 2b00 cmp r3, #0 8003002: d001 beq.n 8003008 { Error_Handler(); 8003004: f7fe fd0c bl 8001a20 } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); 8003008: 687b ldr r3, [r7, #4] 800300a: 4a58 ldr r2, [pc, #352] @ (800316c ) 800300c: 64da str r2, [r3, #76] @ 0x4c 800300e: 4a57 ldr r2, [pc, #348] @ (800316c ) 8003010: 687b ldr r3, [r7, #4] 8003012: 6393 str r3, [r2, #56] @ 0x38 /* USER CODE BEGIN ADC3_MspInit 1 */ /* USER CODE END ADC3_MspInit 1 */ } } 8003014: e11e b.n 8003254 else if(hadc->Instance==ADC2) 8003016: 687b ldr r3, [r7, #4] 8003018: 681b ldr r3, [r3, #0] 800301a: 4a56 ldr r2, [pc, #344] @ (8003174 ) 800301c: 4293 cmp r3, r2 800301e: f040 80af bne.w 8003180 HAL_RCC_ADC12_CLK_ENABLED++; 8003022: 4b4d ldr r3, [pc, #308] @ (8003158 ) 8003024: 681b ldr r3, [r3, #0] 8003026: 3301 adds r3, #1 8003028: 4a4b ldr r2, [pc, #300] @ (8003158 ) 800302a: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 800302c: 4b4a ldr r3, [pc, #296] @ (8003158 ) 800302e: 681b ldr r3, [r3, #0] 8003030: 2b01 cmp r3, #1 8003032: d10e bne.n 8003052 __HAL_RCC_ADC12_CLK_ENABLE(); 8003034: 4b49 ldr r3, [pc, #292] @ (800315c ) 8003036: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 800303a: 4a48 ldr r2, [pc, #288] @ (800315c ) 800303c: f043 0320 orr.w r3, r3, #32 8003040: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8003044: 4b45 ldr r3, [pc, #276] @ (800315c ) 8003046: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 800304a: f003 0320 and.w r3, r3, #32 800304e: 623b str r3, [r7, #32] 8003050: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 8003052: 4b42 ldr r3, [pc, #264] @ (800315c ) 8003054: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003058: 4a40 ldr r2, [pc, #256] @ (800315c ) 800305a: f043 0301 orr.w r3, r3, #1 800305e: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003062: 4b3e ldr r3, [pc, #248] @ (800315c ) 8003064: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003068: f003 0301 and.w r3, r3, #1 800306c: 61fb str r3, [r7, #28] 800306e: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOC_CLK_ENABLE(); 8003070: 4b3a ldr r3, [pc, #232] @ (800315c ) 8003072: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003076: 4a39 ldr r2, [pc, #228] @ (800315c ) 8003078: f043 0304 orr.w r3, r3, #4 800307c: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003080: 4b36 ldr r3, [pc, #216] @ (800315c ) 8003082: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003086: f003 0304 and.w r3, r3, #4 800308a: 61bb str r3, [r7, #24] 800308c: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 800308e: 4b33 ldr r3, [pc, #204] @ (800315c ) 8003090: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003094: 4a31 ldr r2, [pc, #196] @ (800315c ) 8003096: f043 0302 orr.w r3, r3, #2 800309a: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800309e: 4b2f ldr r3, [pc, #188] @ (800315c ) 80030a0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80030a4: f003 0302 and.w r3, r3, #2 80030a8: 617b str r3, [r7, #20] 80030aa: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_6; 80030ac: 2340 movs r3, #64 @ 0x40 80030ae: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80030b0: 2303 movs r3, #3 80030b2: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 80030b4: 2300 movs r3, #0 80030b6: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80030b8: f107 0334 add.w r3, r7, #52 @ 0x34 80030bc: 4619 mov r1, r3 80030be: 4828 ldr r0, [pc, #160] @ (8003160 ) 80030c0: f006 fd16 bl 8009af0 GPIO_InitStruct.Pin = GPIO_PIN_4; 80030c4: 2310 movs r3, #16 80030c6: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80030c8: 2303 movs r3, #3 80030ca: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 80030cc: 2300 movs r3, #0 80030ce: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80030d0: f107 0334 add.w r3, r7, #52 @ 0x34 80030d4: 4619 mov r1, r3 80030d6: 4823 ldr r0, [pc, #140] @ (8003164 ) 80030d8: f006 fd0a bl 8009af0 GPIO_InitStruct.Pin = GPIO_PIN_1; 80030dc: 2302 movs r3, #2 80030de: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80030e0: 2303 movs r3, #3 80030e2: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 80030e4: 2300 movs r3, #0 80030e6: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80030e8: f107 0334 add.w r3, r7, #52 @ 0x34 80030ec: 4619 mov r1, r3 80030ee: 481e ldr r0, [pc, #120] @ (8003168 ) 80030f0: f006 fcfe bl 8009af0 hdma_adc2.Instance = DMA1_Stream1; 80030f4: 4b20 ldr r3, [pc, #128] @ (8003178 ) 80030f6: 4a21 ldr r2, [pc, #132] @ (800317c ) 80030f8: 601a str r2, [r3, #0] hdma_adc2.Init.Request = DMA_REQUEST_ADC2; 80030fa: 4b1f ldr r3, [pc, #124] @ (8003178 ) 80030fc: 220a movs r2, #10 80030fe: 605a str r2, [r3, #4] hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003100: 4b1d ldr r3, [pc, #116] @ (8003178 ) 8003102: 2200 movs r2, #0 8003104: 609a str r2, [r3, #8] hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; 8003106: 4b1c ldr r3, [pc, #112] @ (8003178 ) 8003108: 2200 movs r2, #0 800310a: 60da str r2, [r3, #12] hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; 800310c: 4b1a ldr r3, [pc, #104] @ (8003178 ) 800310e: f44f 6280 mov.w r2, #1024 @ 0x400 8003112: 611a str r2, [r3, #16] hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8003114: 4b18 ldr r3, [pc, #96] @ (8003178 ) 8003116: f44f 6200 mov.w r2, #2048 @ 0x800 800311a: 615a str r2, [r3, #20] hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 800311c: 4b16 ldr r3, [pc, #88] @ (8003178 ) 800311e: f44f 5200 mov.w r2, #8192 @ 0x2000 8003122: 619a str r2, [r3, #24] hdma_adc2.Init.Mode = DMA_NORMAL; 8003124: 4b14 ldr r3, [pc, #80] @ (8003178 ) 8003126: 2200 movs r2, #0 8003128: 61da str r2, [r3, #28] hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; 800312a: 4b13 ldr r3, [pc, #76] @ (8003178 ) 800312c: 2200 movs r2, #0 800312e: 621a str r2, [r3, #32] hdma_adc2.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003130: 4b11 ldr r3, [pc, #68] @ (8003178 ) 8003132: 2200 movs r2, #0 8003134: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) 8003136: 4810 ldr r0, [pc, #64] @ (8003178 ) 8003138: f003 fe9e bl 8006e78 800313c: 4603 mov r3, r0 800313e: 2b00 cmp r3, #0 8003140: d001 beq.n 8003146 Error_Handler(); 8003142: f7fe fc6d bl 8001a20 __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2); 8003146: 687b ldr r3, [r7, #4] 8003148: 4a0b ldr r2, [pc, #44] @ (8003178 ) 800314a: 64da str r2, [r3, #76] @ 0x4c 800314c: 4a0a ldr r2, [pc, #40] @ (8003178 ) 800314e: 687b ldr r3, [r7, #4] 8003150: 6393 str r3, [r2, #56] @ 0x38 } 8003152: e07f b.n 8003254 8003154: 40022000 .word 0x40022000 8003158: 240007c4 .word 0x240007c4 800315c: 58024400 .word 0x58024400 8003160: 58020000 .word 0x58020000 8003164: 58020800 .word 0x58020800 8003168: 58020400 .word 0x58020400 800316c: 2400026c .word 0x2400026c 8003170: 40020010 .word 0x40020010 8003174: 40022100 .word 0x40022100 8003178: 240002e4 .word 0x240002e4 800317c: 40020028 .word 0x40020028 else if(hadc->Instance==ADC3) 8003180: 687b ldr r3, [r7, #4] 8003182: 681b ldr r3, [r3, #0] 8003184: 4a35 ldr r2, [pc, #212] @ (800325c ) 8003186: 4293 cmp r3, r2 8003188: d164 bne.n 8003254 __HAL_RCC_ADC3_CLK_ENABLE(); 800318a: 4b35 ldr r3, [pc, #212] @ (8003260 ) 800318c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003190: 4a33 ldr r2, [pc, #204] @ (8003260 ) 8003192: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8003196: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800319a: 4b31 ldr r3, [pc, #196] @ (8003260 ) 800319c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80031a0: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80031a4: 613b str r3, [r7, #16] 80031a6: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 80031a8: 4b2d ldr r3, [pc, #180] @ (8003260 ) 80031aa: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80031ae: 4a2c ldr r2, [pc, #176] @ (8003260 ) 80031b0: f043 0304 orr.w r3, r3, #4 80031b4: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80031b8: 4b29 ldr r3, [pc, #164] @ (8003260 ) 80031ba: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80031be: f003 0304 and.w r3, r3, #4 80031c2: 60fb str r3, [r7, #12] 80031c4: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 80031c6: 2303 movs r3, #3 80031c8: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80031ca: 2303 movs r3, #3 80031cc: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 80031ce: 2300 movs r3, #0 80031d0: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80031d2: f107 0334 add.w r3, r7, #52 @ 0x34 80031d6: 4619 mov r1, r3 80031d8: 4822 ldr r0, [pc, #136] @ (8003264 ) 80031da: f006 fc89 bl 8009af0 HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC2, SYSCFG_SWITCH_PC2_OPEN); 80031de: f04f 6180 mov.w r1, #67108864 @ 0x4000000 80031e2: f04f 6080 mov.w r0, #67108864 @ 0x4000000 80031e6: f001 fc79 bl 8004adc HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC3, SYSCFG_SWITCH_PC3_OPEN); 80031ea: f04f 6100 mov.w r1, #134217728 @ 0x8000000 80031ee: f04f 6000 mov.w r0, #134217728 @ 0x8000000 80031f2: f001 fc73 bl 8004adc hdma_adc3.Instance = DMA1_Stream2; 80031f6: 4b1c ldr r3, [pc, #112] @ (8003268 ) 80031f8: 4a1c ldr r2, [pc, #112] @ (800326c ) 80031fa: 601a str r2, [r3, #0] hdma_adc3.Init.Request = DMA_REQUEST_ADC3; 80031fc: 4b1a ldr r3, [pc, #104] @ (8003268 ) 80031fe: 2273 movs r2, #115 @ 0x73 8003200: 605a str r2, [r3, #4] hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003202: 4b19 ldr r3, [pc, #100] @ (8003268 ) 8003204: 2200 movs r2, #0 8003206: 609a str r2, [r3, #8] hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE; 8003208: 4b17 ldr r3, [pc, #92] @ (8003268 ) 800320a: 2200 movs r2, #0 800320c: 60da str r2, [r3, #12] hdma_adc3.Init.MemInc = DMA_MINC_ENABLE; 800320e: 4b16 ldr r3, [pc, #88] @ (8003268 ) 8003210: f44f 6280 mov.w r2, #1024 @ 0x400 8003214: 611a str r2, [r3, #16] hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8003216: 4b14 ldr r3, [pc, #80] @ (8003268 ) 8003218: f44f 6200 mov.w r2, #2048 @ 0x800 800321c: 615a str r2, [r3, #20] hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 800321e: 4b12 ldr r3, [pc, #72] @ (8003268 ) 8003220: f44f 5200 mov.w r2, #8192 @ 0x2000 8003224: 619a str r2, [r3, #24] hdma_adc3.Init.Mode = DMA_NORMAL; 8003226: 4b10 ldr r3, [pc, #64] @ (8003268 ) 8003228: 2200 movs r2, #0 800322a: 61da str r2, [r3, #28] hdma_adc3.Init.Priority = DMA_PRIORITY_LOW; 800322c: 4b0e ldr r3, [pc, #56] @ (8003268 ) 800322e: 2200 movs r2, #0 8003230: 621a str r2, [r3, #32] hdma_adc3.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003232: 4b0d ldr r3, [pc, #52] @ (8003268 ) 8003234: 2200 movs r2, #0 8003236: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc3) != HAL_OK) 8003238: 480b ldr r0, [pc, #44] @ (8003268 ) 800323a: f003 fe1d bl 8006e78 800323e: 4603 mov r3, r0 8003240: 2b00 cmp r3, #0 8003242: d001 beq.n 8003248 Error_Handler(); 8003244: f7fe fbec bl 8001a20 __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc3); 8003248: 687b ldr r3, [r7, #4] 800324a: 4a07 ldr r2, [pc, #28] @ (8003268 ) 800324c: 64da str r2, [r3, #76] @ 0x4c 800324e: 4a06 ldr r2, [pc, #24] @ (8003268 ) 8003250: 687b ldr r3, [r7, #4] 8003252: 6393 str r3, [r2, #56] @ 0x38 } 8003254: bf00 nop 8003256: 3748 adds r7, #72 @ 0x48 8003258: 46bd mov sp, r7 800325a: bd80 pop {r7, pc} 800325c: 58026000 .word 0x58026000 8003260: 58024400 .word 0x58024400 8003264: 58020800 .word 0x58020800 8003268: 2400035c .word 0x2400035c 800326c: 40020040 .word 0x40020040 08003270 : * This function configures the hardware resources used in this example * @param hcrc: CRC handle pointer * @retval None */ void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) { 8003270: b480 push {r7} 8003272: b085 sub sp, #20 8003274: af00 add r7, sp, #0 8003276: 6078 str r0, [r7, #4] if(hcrc->Instance==CRC) 8003278: 687b ldr r3, [r7, #4] 800327a: 681b ldr r3, [r3, #0] 800327c: 4a0b ldr r2, [pc, #44] @ (80032ac ) 800327e: 4293 cmp r3, r2 8003280: d10e bne.n 80032a0 { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 8003282: 4b0b ldr r3, [pc, #44] @ (80032b0 ) 8003284: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003288: 4a09 ldr r2, [pc, #36] @ (80032b0 ) 800328a: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800328e: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003292: 4b07 ldr r3, [pc, #28] @ (80032b0 ) 8003294: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003298: f403 2300 and.w r3, r3, #524288 @ 0x80000 800329c: 60fb str r3, [r7, #12] 800329e: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 80032a0: bf00 nop 80032a2: 3714 adds r7, #20 80032a4: 46bd mov sp, r7 80032a6: f85d 7b04 ldr.w r7, [sp], #4 80032aa: 4770 bx lr 80032ac: 58024c00 .word 0x58024c00 80032b0: 58024400 .word 0x58024400 080032b4 : * This function configures the hardware resources used in this example * @param hdac: DAC handle pointer * @retval None */ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) { 80032b4: b580 push {r7, lr} 80032b6: b08a sub sp, #40 @ 0x28 80032b8: af00 add r7, sp, #0 80032ba: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80032bc: f107 0314 add.w r3, r7, #20 80032c0: 2200 movs r2, #0 80032c2: 601a str r2, [r3, #0] 80032c4: 605a str r2, [r3, #4] 80032c6: 609a str r2, [r3, #8] 80032c8: 60da str r2, [r3, #12] 80032ca: 611a str r2, [r3, #16] if(hdac->Instance==DAC1) 80032cc: 687b ldr r3, [r7, #4] 80032ce: 681b ldr r3, [r3, #0] 80032d0: 4a1c ldr r2, [pc, #112] @ (8003344 ) 80032d2: 4293 cmp r3, r2 80032d4: d131 bne.n 800333a { /* USER CODE BEGIN DAC1_MspInit 0 */ /* USER CODE END DAC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DAC12_CLK_ENABLE(); 80032d6: 4b1c ldr r3, [pc, #112] @ (8003348 ) 80032d8: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80032dc: 4a1a ldr r2, [pc, #104] @ (8003348 ) 80032de: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 80032e2: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 80032e6: 4b18 ldr r3, [pc, #96] @ (8003348 ) 80032e8: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80032ec: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80032f0: 613b str r3, [r7, #16] 80032f2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 80032f4: 4b14 ldr r3, [pc, #80] @ (8003348 ) 80032f6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80032fa: 4a13 ldr r2, [pc, #76] @ (8003348 ) 80032fc: f043 0301 orr.w r3, r3, #1 8003300: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003304: 4b10 ldr r3, [pc, #64] @ (8003348 ) 8003306: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800330a: f003 0301 and.w r3, r3, #1 800330e: 60fb str r3, [r7, #12] 8003310: 68fb ldr r3, [r7, #12] /**DAC1 GPIO Configuration PA4 ------> DAC1_OUT1 PA5 ------> DAC1_OUT2 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 8003312: 2330 movs r3, #48 @ 0x30 8003314: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003316: 2303 movs r3, #3 8003318: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800331a: 2300 movs r3, #0 800331c: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800331e: f107 0314 add.w r3, r7, #20 8003322: 4619 mov r1, r3 8003324: 4809 ldr r0, [pc, #36] @ (800334c ) 8003326: f006 fbe3 bl 8009af0 /* DAC1 interrupt Init */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 5, 0); 800332a: 2200 movs r2, #0 800332c: 2105 movs r1, #5 800332e: 2036 movs r0, #54 @ 0x36 8003330: f003 f8ac bl 800648c HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 8003334: 2036 movs r0, #54 @ 0x36 8003336: f003 f8c3 bl 80064c0 /* USER CODE BEGIN DAC1_MspInit 1 */ /* USER CODE END DAC1_MspInit 1 */ } } 800333a: bf00 nop 800333c: 3728 adds r7, #40 @ 0x28 800333e: 46bd mov sp, r7 8003340: bd80 pop {r7, pc} 8003342: bf00 nop 8003344: 40007400 .word 0x40007400 8003348: 58024400 .word 0x58024400 800334c: 58020000 .word 0x58020000 08003350 : * This function configures the hardware resources used in this example * @param hrng: RNG handle pointer * @retval None */ void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) { 8003350: b580 push {r7, lr} 8003352: b0b4 sub sp, #208 @ 0xd0 8003354: af00 add r7, sp, #0 8003356: 6078 str r0, [r7, #4] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8003358: f107 0310 add.w r3, r7, #16 800335c: 22c0 movs r2, #192 @ 0xc0 800335e: 2100 movs r1, #0 8003360: 4618 mov r0, r3 8003362: f013 f9f8 bl 8016756 if(hrng->Instance==RNG) 8003366: 687b ldr r3, [r7, #4] 8003368: 681b ldr r3, [r3, #0] 800336a: 4a14 ldr r2, [pc, #80] @ (80033bc ) 800336c: 4293 cmp r3, r2 800336e: d121 bne.n 80033b4 /* USER CODE END RNG_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG; 8003370: f44f 3200 mov.w r2, #131072 @ 0x20000 8003374: f04f 0300 mov.w r3, #0 8003378: e9c7 2304 strd r2, r3, [r7, #16] PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48; 800337c: 2300 movs r3, #0 800337e: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8003382: f107 0310 add.w r3, r7, #16 8003386: 4618 mov r0, r3 8003388: f007 ff3a bl 800b200 800338c: 4603 mov r3, r0 800338e: 2b00 cmp r3, #0 8003390: d001 beq.n 8003396 { Error_Handler(); 8003392: f7fe fb45 bl 8001a20 } /* Peripheral clock enable */ __HAL_RCC_RNG_CLK_ENABLE(); 8003396: 4b0a ldr r3, [pc, #40] @ (80033c0 ) 8003398: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 800339c: 4a08 ldr r2, [pc, #32] @ (80033c0 ) 800339e: f043 0340 orr.w r3, r3, #64 @ 0x40 80033a2: f8c2 30dc str.w r3, [r2, #220] @ 0xdc 80033a6: 4b06 ldr r3, [pc, #24] @ (80033c0 ) 80033a8: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 80033ac: f003 0340 and.w r3, r3, #64 @ 0x40 80033b0: 60fb str r3, [r7, #12] 80033b2: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN RNG_MspInit 1 */ /* USER CODE END RNG_MspInit 1 */ } } 80033b4: bf00 nop 80033b6: 37d0 adds r7, #208 @ 0xd0 80033b8: 46bd mov sp, r7 80033ba: bd80 pop {r7, pc} 80033bc: 48021800 .word 0x48021800 80033c0: 58024400 .word 0x58024400 080033c4 : * This function configures the hardware resources used in this example * @param htim_pwm: TIM_PWM handle pointer * @retval None */ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) { 80033c4: b480 push {r7} 80033c6: b085 sub sp, #20 80033c8: af00 add r7, sp, #0 80033ca: 6078 str r0, [r7, #4] if(htim_pwm->Instance==TIM1) 80033cc: 687b ldr r3, [r7, #4] 80033ce: 681b ldr r3, [r3, #0] 80033d0: 4a16 ldr r2, [pc, #88] @ (800342c ) 80033d2: 4293 cmp r3, r2 80033d4: d10f bne.n 80033f6 { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 80033d6: 4b16 ldr r3, [pc, #88] @ (8003430 ) 80033d8: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80033dc: 4a14 ldr r2, [pc, #80] @ (8003430 ) 80033de: f043 0301 orr.w r3, r3, #1 80033e2: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 80033e6: 4b12 ldr r3, [pc, #72] @ (8003430 ) 80033e8: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80033ec: f003 0301 and.w r3, r3, #1 80033f0: 60fb str r3, [r7, #12] 80033f2: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 80033f4: e013 b.n 800341e else if(htim_pwm->Instance==TIM3) 80033f6: 687b ldr r3, [r7, #4] 80033f8: 681b ldr r3, [r3, #0] 80033fa: 4a0e ldr r2, [pc, #56] @ (8003434 ) 80033fc: 4293 cmp r3, r2 80033fe: d10e bne.n 800341e __HAL_RCC_TIM3_CLK_ENABLE(); 8003400: 4b0b ldr r3, [pc, #44] @ (8003430 ) 8003402: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003406: 4a0a ldr r2, [pc, #40] @ (8003430 ) 8003408: f043 0302 orr.w r3, r3, #2 800340c: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8003410: 4b07 ldr r3, [pc, #28] @ (8003430 ) 8003412: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003416: f003 0302 and.w r3, r3, #2 800341a: 60bb str r3, [r7, #8] 800341c: 68bb ldr r3, [r7, #8] } 800341e: bf00 nop 8003420: 3714 adds r7, #20 8003422: 46bd mov sp, r7 8003424: f85d 7b04 ldr.w r7, [sp], #4 8003428: 4770 bx lr 800342a: bf00 nop 800342c: 40010000 .word 0x40010000 8003430: 58024400 .word 0x58024400 8003434: 40000400 .word 0x40000400 08003438 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8003438: b580 push {r7, lr} 800343a: b084 sub sp, #16 800343c: af00 add r7, sp, #0 800343e: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM2) 8003440: 687b ldr r3, [r7, #4] 8003442: 681b ldr r3, [r3, #0] 8003444: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8003448: d116 bne.n 8003478 { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 800344a: 4b0d ldr r3, [pc, #52] @ (8003480 ) 800344c: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003450: 4a0b ldr r2, [pc, #44] @ (8003480 ) 8003452: f043 0301 orr.w r3, r3, #1 8003456: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 800345a: 4b09 ldr r3, [pc, #36] @ (8003480 ) 800345c: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003460: f003 0301 and.w r3, r3, #1 8003464: 60fb str r3, [r7, #12] 8003466: 68fb ldr r3, [r7, #12] /* TIM2 interrupt Init */ HAL_NVIC_SetPriority(TIM2_IRQn, 5, 0); 8003468: 2200 movs r2, #0 800346a: 2105 movs r1, #5 800346c: 201c movs r0, #28 800346e: f003 f80d bl 800648c HAL_NVIC_EnableIRQ(TIM2_IRQn); 8003472: 201c movs r0, #28 8003474: f003 f824 bl 80064c0 /* USER CODE BEGIN TIM2_MspInit 1 */ /* USER CODE END TIM2_MspInit 1 */ } } 8003478: bf00 nop 800347a: 3710 adds r7, #16 800347c: 46bd mov sp, r7 800347e: bd80 pop {r7, pc} 8003480: 58024400 .word 0x58024400 08003484 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 8003484: b580 push {r7, lr} 8003486: b08a sub sp, #40 @ 0x28 8003488: af00 add r7, sp, #0 800348a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800348c: f107 0314 add.w r3, r7, #20 8003490: 2200 movs r2, #0 8003492: 601a str r2, [r3, #0] 8003494: 605a str r2, [r3, #4] 8003496: 609a str r2, [r3, #8] 8003498: 60da str r2, [r3, #12] 800349a: 611a str r2, [r3, #16] if(htim->Instance==TIM1) 800349c: 687b ldr r3, [r7, #4] 800349e: 681b ldr r3, [r3, #0] 80034a0: 4a26 ldr r2, [pc, #152] @ (800353c ) 80034a2: 4293 cmp r3, r2 80034a4: d120 bne.n 80034e8 { /* USER CODE BEGIN TIM1_MspPostInit 0 */ /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 80034a6: 4b26 ldr r3, [pc, #152] @ (8003540 ) 80034a8: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80034ac: 4a24 ldr r2, [pc, #144] @ (8003540 ) 80034ae: f043 0301 orr.w r3, r3, #1 80034b2: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80034b6: 4b22 ldr r3, [pc, #136] @ (8003540 ) 80034b8: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80034bc: f003 0301 and.w r3, r3, #1 80034c0: 613b str r3, [r7, #16] 80034c2: 693b ldr r3, [r7, #16] /**TIM1 GPIO Configuration PA9 ------> TIM1_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_9; 80034c4: f44f 7300 mov.w r3, #512 @ 0x200 80034c8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80034ca: 2302 movs r3, #2 80034cc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80034ce: 2300 movs r3, #0 80034d0: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80034d2: 2300 movs r3, #0 80034d4: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; 80034d6: 2301 movs r3, #1 80034d8: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80034da: f107 0314 add.w r3, r7, #20 80034de: 4619 mov r1, r3 80034e0: 4818 ldr r0, [pc, #96] @ (8003544 ) 80034e2: f006 fb05 bl 8009af0 /* USER CODE BEGIN TIM3_MspPostInit 1 */ /* USER CODE END TIM3_MspPostInit 1 */ } } 80034e6: e024 b.n 8003532 else if(htim->Instance==TIM3) 80034e8: 687b ldr r3, [r7, #4] 80034ea: 681b ldr r3, [r3, #0] 80034ec: 4a16 ldr r2, [pc, #88] @ (8003548 ) 80034ee: 4293 cmp r3, r2 80034f0: d11f bne.n 8003532 __HAL_RCC_GPIOC_CLK_ENABLE(); 80034f2: 4b13 ldr r3, [pc, #76] @ (8003540 ) 80034f4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80034f8: 4a11 ldr r2, [pc, #68] @ (8003540 ) 80034fa: f043 0304 orr.w r3, r3, #4 80034fe: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003502: 4b0f ldr r3, [pc, #60] @ (8003540 ) 8003504: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003508: f003 0304 and.w r3, r3, #4 800350c: 60fb str r3, [r7, #12] 800350e: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 8003510: f44f 7370 mov.w r3, #960 @ 0x3c0 8003514: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003516: 2302 movs r3, #2 8003518: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800351a: 2300 movs r3, #0 800351c: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 800351e: 2301 movs r3, #1 8003520: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 8003522: 2302 movs r3, #2 8003524: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003526: f107 0314 add.w r3, r7, #20 800352a: 4619 mov r1, r3 800352c: 4807 ldr r0, [pc, #28] @ (800354c ) 800352e: f006 fadf bl 8009af0 } 8003532: bf00 nop 8003534: 3728 adds r7, #40 @ 0x28 8003536: 46bd mov sp, r7 8003538: bd80 pop {r7, pc} 800353a: bf00 nop 800353c: 40010000 .word 0x40010000 8003540: 58024400 .word 0x58024400 8003544: 58020000 .word 0x58020000 8003548: 40000400 .word 0x40000400 800354c: 58020800 .word 0x58020800 08003550 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8003550: b580 push {r7, lr} 8003552: b0bc sub sp, #240 @ 0xf0 8003554: af00 add r7, sp, #0 8003556: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003558: f107 03dc add.w r3, r7, #220 @ 0xdc 800355c: 2200 movs r2, #0 800355e: 601a str r2, [r3, #0] 8003560: 605a str r2, [r3, #4] 8003562: 609a str r2, [r3, #8] 8003564: 60da str r2, [r3, #12] 8003566: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8003568: f107 0318 add.w r3, r7, #24 800356c: 22c0 movs r2, #192 @ 0xc0 800356e: 2100 movs r1, #0 8003570: 4618 mov r0, r3 8003572: f013 f8f0 bl 8016756 if(huart->Instance==UART8) 8003576: 687b ldr r3, [r7, #4] 8003578: 681b ldr r3, [r3, #0] 800357a: 4a55 ldr r2, [pc, #340] @ (80036d0 ) 800357c: 4293 cmp r3, r2 800357e: d14e bne.n 800361e /* USER CODE END UART8_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8; 8003580: f04f 0202 mov.w r2, #2 8003584: f04f 0300 mov.w r3, #0 8003588: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 800358c: 2300 movs r3, #0 800358e: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8003592: f107 0318 add.w r3, r7, #24 8003596: 4618 mov r0, r3 8003598: f007 fe32 bl 800b200 800359c: 4603 mov r3, r0 800359e: 2b00 cmp r3, #0 80035a0: d001 beq.n 80035a6 { Error_Handler(); 80035a2: f7fe fa3d bl 8001a20 } /* Peripheral clock enable */ __HAL_RCC_UART8_CLK_ENABLE(); 80035a6: 4b4b ldr r3, [pc, #300] @ (80036d4 ) 80035a8: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80035ac: 4a49 ldr r2, [pc, #292] @ (80036d4 ) 80035ae: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80035b2: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 80035b6: 4b47 ldr r3, [pc, #284] @ (80036d4 ) 80035b8: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80035bc: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80035c0: 617b str r3, [r7, #20] 80035c2: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOE_CLK_ENABLE(); 80035c4: 4b43 ldr r3, [pc, #268] @ (80036d4 ) 80035c6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80035ca: 4a42 ldr r2, [pc, #264] @ (80036d4 ) 80035cc: f043 0310 orr.w r3, r3, #16 80035d0: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80035d4: 4b3f ldr r3, [pc, #252] @ (80036d4 ) 80035d6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80035da: f003 0310 and.w r3, r3, #16 80035de: 613b str r3, [r7, #16] 80035e0: 693b ldr r3, [r7, #16] /**UART8 GPIO Configuration PE0 ------> UART8_RX PE1 ------> UART8_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 80035e2: 2303 movs r3, #3 80035e4: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80035e8: 2302 movs r3, #2 80035ea: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 80035ee: 2300 movs r3, #0 80035f0: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80035f4: 2300 movs r3, #0 80035f6: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF8_UART8; 80035fa: 2308 movs r3, #8 80035fc: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8003600: f107 03dc add.w r3, r7, #220 @ 0xdc 8003604: 4619 mov r1, r3 8003606: 4834 ldr r0, [pc, #208] @ (80036d8 ) 8003608: f006 fa72 bl 8009af0 /* UART8 interrupt Init */ HAL_NVIC_SetPriority(UART8_IRQn, 5, 0); 800360c: 2200 movs r2, #0 800360e: 2105 movs r1, #5 8003610: 2053 movs r0, #83 @ 0x53 8003612: f002 ff3b bl 800648c HAL_NVIC_EnableIRQ(UART8_IRQn); 8003616: 2053 movs r0, #83 @ 0x53 8003618: f002 ff52 bl 80064c0 /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 800361c: e053 b.n 80036c6 else if(huart->Instance==USART1) 800361e: 687b ldr r3, [r7, #4] 8003620: 681b ldr r3, [r3, #0] 8003622: 4a2e ldr r2, [pc, #184] @ (80036dc ) 8003624: 4293 cmp r3, r2 8003626: d14e bne.n 80036c6 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; 8003628: f04f 0201 mov.w r2, #1 800362c: f04f 0300 mov.w r3, #0 8003630: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; 8003634: 2300 movs r3, #0 8003636: f8c7 3094 str.w r3, [r7, #148] @ 0x94 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800363a: f107 0318 add.w r3, r7, #24 800363e: 4618 mov r0, r3 8003640: f007 fdde bl 800b200 8003644: 4603 mov r3, r0 8003646: 2b00 cmp r3, #0 8003648: d001 beq.n 800364e Error_Handler(); 800364a: f7fe f9e9 bl 8001a20 __HAL_RCC_USART1_CLK_ENABLE(); 800364e: 4b21 ldr r3, [pc, #132] @ (80036d4 ) 8003650: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8003654: 4a1f ldr r2, [pc, #124] @ (80036d4 ) 8003656: f043 0310 orr.w r3, r3, #16 800365a: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 800365e: 4b1d ldr r3, [pc, #116] @ (80036d4 ) 8003660: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8003664: f003 0310 and.w r3, r3, #16 8003668: 60fb str r3, [r7, #12] 800366a: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 800366c: 4b19 ldr r3, [pc, #100] @ (80036d4 ) 800366e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003672: 4a18 ldr r2, [pc, #96] @ (80036d4 ) 8003674: f043 0302 orr.w r3, r3, #2 8003678: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800367c: 4b15 ldr r3, [pc, #84] @ (80036d4 ) 800367e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003682: f003 0302 and.w r3, r3, #2 8003686: 60bb str r3, [r7, #8] 8003688: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 800368a: f44f 4340 mov.w r3, #49152 @ 0xc000 800368e: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003692: 2302 movs r3, #2 8003694: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003698: 2300 movs r3, #0 800369a: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800369e: 2300 movs r3, #0 80036a0: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF4_USART1; 80036a4: 2304 movs r3, #4 80036a6: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80036aa: f107 03dc add.w r3, r7, #220 @ 0xdc 80036ae: 4619 mov r1, r3 80036b0: 480b ldr r0, [pc, #44] @ (80036e0 ) 80036b2: f006 fa1d bl 8009af0 HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 80036b6: 2200 movs r2, #0 80036b8: 2105 movs r1, #5 80036ba: 2025 movs r0, #37 @ 0x25 80036bc: f002 fee6 bl 800648c HAL_NVIC_EnableIRQ(USART1_IRQn); 80036c0: 2025 movs r0, #37 @ 0x25 80036c2: f002 fefd bl 80064c0 } 80036c6: bf00 nop 80036c8: 37f0 adds r7, #240 @ 0xf0 80036ca: 46bd mov sp, r7 80036cc: bd80 pop {r7, pc} 80036ce: bf00 nop 80036d0: 40007c00 .word 0x40007c00 80036d4: 58024400 .word 0x58024400 80036d8: 58021000 .word 0x58021000 80036dc: 40011000 .word 0x40011000 80036e0: 58020400 .word 0x58020400 080036e4 : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80036e4: b580 push {r7, lr} 80036e6: b090 sub sp, #64 @ 0x40 80036e8: af00 add r7, sp, #0 80036ea: 6078 str r0, [r7, #4] uint32_t uwTimclock, uwAPB1Prescaler; uint32_t uwPrescalerValue; uint32_t pFLatency; /*Configure the TIM6 IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80036ec: 687b ldr r3, [r7, #4] 80036ee: 2b0f cmp r3, #15 80036f0: d827 bhi.n 8003742 { HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U); 80036f2: 2200 movs r2, #0 80036f4: 6879 ldr r1, [r7, #4] 80036f6: 2036 movs r0, #54 @ 0x36 80036f8: f002 fec8 bl 800648c /* Enable the TIM6 global Interrupt */ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 80036fc: 2036 movs r0, #54 @ 0x36 80036fe: f002 fedf bl 80064c0 uwTickPrio = TickPriority; 8003702: 4a29 ldr r2, [pc, #164] @ (80037a8 ) 8003704: 687b ldr r3, [r7, #4] 8003706: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Enable TIM6 clock */ __HAL_RCC_TIM6_CLK_ENABLE(); 8003708: 4b28 ldr r3, [pc, #160] @ (80037ac ) 800370a: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800370e: 4a27 ldr r2, [pc, #156] @ (80037ac ) 8003710: f043 0310 orr.w r3, r3, #16 8003714: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8003718: 4b24 ldr r3, [pc, #144] @ (80037ac ) 800371a: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800371e: f003 0310 and.w r3, r3, #16 8003722: 60fb str r3, [r7, #12] 8003724: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 8003726: f107 0210 add.w r2, r7, #16 800372a: f107 0314 add.w r3, r7, #20 800372e: 4611 mov r1, r2 8003730: 4618 mov r0, r3 8003732: f007 fd23 bl 800b17c /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; 8003736: 6abb ldr r3, [r7, #40] @ 0x28 8003738: 63bb str r3, [r7, #56] @ 0x38 /* Compute TIM6 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) 800373a: 6bbb ldr r3, [r7, #56] @ 0x38 800373c: 2b00 cmp r3, #0 800373e: d106 bne.n 800374e 8003740: e001 b.n 8003746 return HAL_ERROR; 8003742: 2301 movs r3, #1 8003744: e02b b.n 800379e { uwTimclock = HAL_RCC_GetPCLK1Freq(); 8003746: f007 fced bl 800b124 800374a: 63f8 str r0, [r7, #60] @ 0x3c 800374c: e004 b.n 8003758 } else { uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); 800374e: f007 fce9 bl 800b124 8003752: 4603 mov r3, r0 8003754: 005b lsls r3, r3, #1 8003756: 63fb str r3, [r7, #60] @ 0x3c } /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 8003758: 6bfb ldr r3, [r7, #60] @ 0x3c 800375a: 4a15 ldr r2, [pc, #84] @ (80037b0 ) 800375c: fba2 2303 umull r2, r3, r2, r3 8003760: 0c9b lsrs r3, r3, #18 8003762: 3b01 subs r3, #1 8003764: 637b str r3, [r7, #52] @ 0x34 /* Initialize TIM6 */ htim6.Instance = TIM6; 8003766: 4b13 ldr r3, [pc, #76] @ (80037b4 ) 8003768: 4a13 ldr r2, [pc, #76] @ (80037b8 ) 800376a: 601a str r2, [r3, #0] + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up */ htim6.Init.Period = (1000000U / 1000U) - 1U; 800376c: 4b11 ldr r3, [pc, #68] @ (80037b4 ) 800376e: f240 32e7 movw r2, #999 @ 0x3e7 8003772: 60da str r2, [r3, #12] htim6.Init.Prescaler = uwPrescalerValue; 8003774: 4a0f ldr r2, [pc, #60] @ (80037b4 ) 8003776: 6b7b ldr r3, [r7, #52] @ 0x34 8003778: 6053 str r3, [r2, #4] htim6.Init.ClockDivision = 0; 800377a: 4b0e ldr r3, [pc, #56] @ (80037b4 ) 800377c: 2200 movs r2, #0 800377e: 611a str r2, [r3, #16] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 8003780: 4b0c ldr r3, [pc, #48] @ (80037b4 ) 8003782: 2200 movs r2, #0 8003784: 609a str r2, [r3, #8] if(HAL_TIM_Base_Init(&htim6) == HAL_OK) 8003786: 480b ldr r0, [pc, #44] @ (80037b4 ) 8003788: f00a fa7e bl 800dc88 800378c: 4603 mov r3, r0 800378e: 2b00 cmp r3, #0 8003790: d104 bne.n 800379c { /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&htim6); 8003792: 4808 ldr r0, [pc, #32] @ (80037b4 ) 8003794: f00a fb40 bl 800de18 8003798: 4603 mov r3, r0 800379a: e000 b.n 800379e } /* Return function status */ return HAL_ERROR; 800379c: 2301 movs r3, #1 } 800379e: 4618 mov r0, r3 80037a0: 3740 adds r7, #64 @ 0x40 80037a2: 46bd mov sp, r7 80037a4: bd80 pop {r7, pc} 80037a6: bf00 nop 80037a8: 2400003c .word 0x2400003c 80037ac: 58024400 .word 0x58024400 80037b0: 431bde83 .word 0x431bde83 80037b4: 240007c8 .word 0x240007c8 80037b8: 40001000 .word 0x40001000 080037bc : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80037bc: b480 push {r7} 80037be: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80037c0: bf00 nop 80037c2: e7fd b.n 80037c0 080037c4 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80037c4: b480 push {r7} 80037c6: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80037c8: bf00 nop 80037ca: e7fd b.n 80037c8 080037cc : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80037cc: b480 push {r7} 80037ce: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80037d0: bf00 nop 80037d2: e7fd b.n 80037d0 080037d4 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 80037d4: b480 push {r7} 80037d6: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80037d8: bf00 nop 80037da: e7fd b.n 80037d8 080037dc : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80037dc: b480 push {r7} 80037de: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80037e0: bf00 nop 80037e2: e7fd b.n 80037e0 080037e4 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80037e4: b480 push {r7} 80037e6: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 80037e8: bf00 nop 80037ea: 46bd mov sp, r7 80037ec: f85d 7b04 ldr.w r7, [sp], #4 80037f0: 4770 bx lr 080037f2 : /** * @brief This function handles RCC global interrupt. */ void RCC_IRQHandler(void) { 80037f2: b480 push {r7} 80037f4: af00 add r7, sp, #0 /* USER CODE END RCC_IRQn 0 */ /* USER CODE BEGIN RCC_IRQn 1 */ /* USER CODE END RCC_IRQn 1 */ } 80037f6: bf00 nop 80037f8: 46bd mov sp, r7 80037fa: f85d 7b04 ldr.w r7, [sp], #4 80037fe: 4770 bx lr 08003800 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 8003800: b580 push {r7, lr} 8003802: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 8003804: 4802 ldr r0, [pc, #8] @ (8003810 ) 8003806: f004 fe61 bl 80084cc /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 800380a: bf00 nop 800380c: bd80 pop {r7, pc} 800380e: bf00 nop 8003810: 2400026c .word 0x2400026c 08003814 : /** * @brief This function handles DMA1 stream1 global interrupt. */ void DMA1_Stream1_IRQHandler(void) { 8003814: b580 push {r7, lr} 8003816: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */ /* USER CODE END DMA1_Stream1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc2); 8003818: 4802 ldr r0, [pc, #8] @ (8003824 ) 800381a: f004 fe57 bl 80084cc /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */ /* USER CODE END DMA1_Stream1_IRQn 1 */ } 800381e: bf00 nop 8003820: bd80 pop {r7, pc} 8003822: bf00 nop 8003824: 240002e4 .word 0x240002e4 08003828 : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 8003828: b580 push {r7, lr} 800382a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc3); 800382c: 4802 ldr r0, [pc, #8] @ (8003838 ) 800382e: f004 fe4d bl 80084cc /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 8003832: bf00 nop 8003834: bd80 pop {r7, pc} 8003836: bf00 nop 8003838: 2400035c .word 0x2400035c 0800383c : /** * @brief This function handles EXTI line[9:5] interrupts. */ void EXTI9_5_IRQHandler(void) { 800383c: b580 push {r7, lr} 800383e: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI9_5_IRQn 0 */ /* USER CODE END EXTI9_5_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8); 8003840: f44f 7080 mov.w r0, #256 @ 0x100 8003844: f006 fb4f bl 8009ee6 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9); 8003848: f44f 7000 mov.w r0, #512 @ 0x200 800384c: f006 fb4b bl 8009ee6 /* USER CODE BEGIN EXTI9_5_IRQn 1 */ /* USER CODE END EXTI9_5_IRQn 1 */ } 8003850: bf00 nop 8003852: bd80 pop {r7, pc} 08003854 : /** * @brief This function handles TIM2 global interrupt. */ void TIM2_IRQHandler(void) { 8003854: b580 push {r7, lr} 8003856: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_IRQn 0 */ /* USER CODE END TIM2_IRQn 0 */ HAL_TIM_IRQHandler(&htim2); 8003858: 4802 ldr r0, [pc, #8] @ (8003864 ) 800385a: f00a fd51 bl 800e300 /* USER CODE BEGIN TIM2_IRQn 1 */ /* USER CODE END TIM2_IRQn 1 */ } 800385e: bf00 nop 8003860: bd80 pop {r7, pc} 8003862: bf00 nop 8003864: 2400046c .word 0x2400046c 08003868 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8003868: b580 push {r7, lr} 800386a: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 800386c: 4802 ldr r0, [pc, #8] @ (8003878 ) 800386e: f00b ff99 bl 800f7a4 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8003872: bf00 nop 8003874: bd80 pop {r7, pc} 8003876: bf00 nop 8003878: 24000598 .word 0x24000598 0800387c : /** * @brief This function handles EXTI line[15:10] interrupts. */ void EXTI15_10_IRQHandler(void) { 800387c: b580 push {r7, lr} 800387e: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI15_10_IRQn 0 */ /* USER CODE END EXTI15_10_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10); 8003880: f44f 6080 mov.w r0, #1024 @ 0x400 8003884: f006 fb2f bl 8009ee6 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); 8003888: f44f 6000 mov.w r0, #2048 @ 0x800 800388c: f006 fb2b bl 8009ee6 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); 8003890: f44f 5080 mov.w r0, #4096 @ 0x1000 8003894: f006 fb27 bl 8009ee6 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13); 8003898: f44f 5000 mov.w r0, #8192 @ 0x2000 800389c: f006 fb23 bl 8009ee6 /* USER CODE BEGIN EXTI15_10_IRQn 1 */ /* USER CODE END EXTI15_10_IRQn 1 */ } 80038a0: bf00 nop 80038a2: bd80 pop {r7, pc} 080038a4 : /** * @brief This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 80038a4: b580 push {r7, lr} 80038a6: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ if (hdac1.State != HAL_DAC_STATE_RESET) { 80038a8: 4b06 ldr r3, [pc, #24] @ (80038c4 ) 80038aa: 791b ldrb r3, [r3, #4] 80038ac: b2db uxtb r3, r3 80038ae: 2b00 cmp r3, #0 80038b0: d002 beq.n 80038b8 HAL_DAC_IRQHandler(&hdac1); 80038b2: 4804 ldr r0, [pc, #16] @ (80038c4 ) 80038b4: f003 f909 bl 8006aca } HAL_TIM_IRQHandler(&htim6); 80038b8: 4803 ldr r0, [pc, #12] @ (80038c8 ) 80038ba: f00a fd21 bl 800e300 /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 80038be: bf00 nop 80038c0: bd80 pop {r7, pc} 80038c2: bf00 nop 80038c4: 240003f8 .word 0x240003f8 80038c8: 240007c8 .word 0x240007c8 080038cc : /** * @brief This function handles UART8 global interrupt. */ void UART8_IRQHandler(void) { 80038cc: b580 push {r7, lr} 80038ce: af00 add r7, sp, #0 /* USER CODE BEGIN UART8_IRQn 0 */ /* USER CODE END UART8_IRQn 0 */ HAL_UART_IRQHandler(&huart8); 80038d0: 4802 ldr r0, [pc, #8] @ (80038dc ) 80038d2: f00b ff67 bl 800f7a4 /* USER CODE BEGIN UART8_IRQn 1 */ /* USER CODE END UART8_IRQn 1 */ } 80038d6: bf00 nop 80038d8: bd80 pop {r7, pc} 80038da: bf00 nop 80038dc: 24000504 .word 0x24000504 080038e0 <_read>: _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { 80038e0: b580 push {r7, lr} 80038e2: b086 sub sp, #24 80038e4: af00 add r7, sp, #0 80038e6: 60f8 str r0, [r7, #12] 80038e8: 60b9 str r1, [r7, #8] 80038ea: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 80038ec: 2300 movs r3, #0 80038ee: 617b str r3, [r7, #20] 80038f0: e00a b.n 8003908 <_read+0x28> { *ptr++ = __io_getchar(); 80038f2: f3af 8000 nop.w 80038f6: 4601 mov r1, r0 80038f8: 68bb ldr r3, [r7, #8] 80038fa: 1c5a adds r2, r3, #1 80038fc: 60ba str r2, [r7, #8] 80038fe: b2ca uxtb r2, r1 8003900: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 8003902: 697b ldr r3, [r7, #20] 8003904: 3301 adds r3, #1 8003906: 617b str r3, [r7, #20] 8003908: 697a ldr r2, [r7, #20] 800390a: 687b ldr r3, [r7, #4] 800390c: 429a cmp r2, r3 800390e: dbf0 blt.n 80038f2 <_read+0x12> } return len; 8003910: 687b ldr r3, [r7, #4] } 8003912: 4618 mov r0, r3 8003914: 3718 adds r7, #24 8003916: 46bd mov sp, r7 8003918: bd80 pop {r7, pc} 0800391a <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 800391a: b580 push {r7, lr} 800391c: b086 sub sp, #24 800391e: af00 add r7, sp, #0 8003920: 60f8 str r0, [r7, #12] 8003922: 60b9 str r1, [r7, #8] 8003924: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8003926: 2300 movs r3, #0 8003928: 617b str r3, [r7, #20] 800392a: e009 b.n 8003940 <_write+0x26> { __io_putchar(*ptr++); 800392c: 68bb ldr r3, [r7, #8] 800392e: 1c5a adds r2, r3, #1 8003930: 60ba str r2, [r7, #8] 8003932: 781b ldrb r3, [r3, #0] 8003934: 4618 mov r0, r3 8003936: f7fc fea7 bl 8000688 <__io_putchar> for (DataIdx = 0; DataIdx < len; DataIdx++) 800393a: 697b ldr r3, [r7, #20] 800393c: 3301 adds r3, #1 800393e: 617b str r3, [r7, #20] 8003940: 697a ldr r2, [r7, #20] 8003942: 687b ldr r3, [r7, #4] 8003944: 429a cmp r2, r3 8003946: dbf1 blt.n 800392c <_write+0x12> } return len; 8003948: 687b ldr r3, [r7, #4] } 800394a: 4618 mov r0, r3 800394c: 3718 adds r7, #24 800394e: 46bd mov sp, r7 8003950: bd80 pop {r7, pc} 08003952 <_close>: int _close(int file) { 8003952: b480 push {r7} 8003954: b083 sub sp, #12 8003956: af00 add r7, sp, #0 8003958: 6078 str r0, [r7, #4] (void)file; return -1; 800395a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800395e: 4618 mov r0, r3 8003960: 370c adds r7, #12 8003962: 46bd mov sp, r7 8003964: f85d 7b04 ldr.w r7, [sp], #4 8003968: 4770 bx lr 0800396a <_fstat>: int _fstat(int file, struct stat *st) { 800396a: b480 push {r7} 800396c: b083 sub sp, #12 800396e: af00 add r7, sp, #0 8003970: 6078 str r0, [r7, #4] 8003972: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 8003974: 683b ldr r3, [r7, #0] 8003976: f44f 5200 mov.w r2, #8192 @ 0x2000 800397a: 605a str r2, [r3, #4] return 0; 800397c: 2300 movs r3, #0 } 800397e: 4618 mov r0, r3 8003980: 370c adds r7, #12 8003982: 46bd mov sp, r7 8003984: f85d 7b04 ldr.w r7, [sp], #4 8003988: 4770 bx lr 0800398a <_isatty>: int _isatty(int file) { 800398a: b480 push {r7} 800398c: b083 sub sp, #12 800398e: af00 add r7, sp, #0 8003990: 6078 str r0, [r7, #4] (void)file; return 1; 8003992: 2301 movs r3, #1 } 8003994: 4618 mov r0, r3 8003996: 370c adds r7, #12 8003998: 46bd mov sp, r7 800399a: f85d 7b04 ldr.w r7, [sp], #4 800399e: 4770 bx lr 080039a0 <_lseek>: int _lseek(int file, int ptr, int dir) { 80039a0: b480 push {r7} 80039a2: b085 sub sp, #20 80039a4: af00 add r7, sp, #0 80039a6: 60f8 str r0, [r7, #12] 80039a8: 60b9 str r1, [r7, #8] 80039aa: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 80039ac: 2300 movs r3, #0 } 80039ae: 4618 mov r0, r3 80039b0: 3714 adds r7, #20 80039b2: 46bd mov sp, r7 80039b4: f85d 7b04 ldr.w r7, [sp], #4 80039b8: 4770 bx lr ... 080039bc <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 80039bc: b580 push {r7, lr} 80039be: b086 sub sp, #24 80039c0: af00 add r7, sp, #0 80039c2: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 80039c4: 4a14 ldr r2, [pc, #80] @ (8003a18 <_sbrk+0x5c>) 80039c6: 4b15 ldr r3, [pc, #84] @ (8003a1c <_sbrk+0x60>) 80039c8: 1ad3 subs r3, r2, r3 80039ca: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 80039cc: 697b ldr r3, [r7, #20] 80039ce: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 80039d0: 4b13 ldr r3, [pc, #76] @ (8003a20 <_sbrk+0x64>) 80039d2: 681b ldr r3, [r3, #0] 80039d4: 2b00 cmp r3, #0 80039d6: d102 bne.n 80039de <_sbrk+0x22> { __sbrk_heap_end = &_end; 80039d8: 4b11 ldr r3, [pc, #68] @ (8003a20 <_sbrk+0x64>) 80039da: 4a12 ldr r2, [pc, #72] @ (8003a24 <_sbrk+0x68>) 80039dc: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 80039de: 4b10 ldr r3, [pc, #64] @ (8003a20 <_sbrk+0x64>) 80039e0: 681a ldr r2, [r3, #0] 80039e2: 687b ldr r3, [r7, #4] 80039e4: 4413 add r3, r2 80039e6: 693a ldr r2, [r7, #16] 80039e8: 429a cmp r2, r3 80039ea: d207 bcs.n 80039fc <_sbrk+0x40> { errno = ENOMEM; 80039ec: f012 ff58 bl 80168a0 <__errno> 80039f0: 4603 mov r3, r0 80039f2: 220c movs r2, #12 80039f4: 601a str r2, [r3, #0] return (void *)-1; 80039f6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80039fa: e009 b.n 8003a10 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 80039fc: 4b08 ldr r3, [pc, #32] @ (8003a20 <_sbrk+0x64>) 80039fe: 681b ldr r3, [r3, #0] 8003a00: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 8003a02: 4b07 ldr r3, [pc, #28] @ (8003a20 <_sbrk+0x64>) 8003a04: 681a ldr r2, [r3, #0] 8003a06: 687b ldr r3, [r7, #4] 8003a08: 4413 add r3, r2 8003a0a: 4a05 ldr r2, [pc, #20] @ (8003a20 <_sbrk+0x64>) 8003a0c: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 8003a0e: 68fb ldr r3, [r7, #12] } 8003a10: 4618 mov r0, r3 8003a12: 3718 adds r7, #24 8003a14: 46bd mov sp, r7 8003a16: bd80 pop {r7, pc} 8003a18: 24060000 .word 0x24060000 8003a1c: 00000400 .word 0x00000400 8003a20: 24000814 .word 0x24000814 8003a24: 24012d48 .word 0x24012d48 08003a28 : * configuration. * @param None * @retval None */ void SystemInit (void) { 8003a28: b480 push {r7} 8003a2a: af00 add r7, sp, #0 __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8003a2c: 4b37 ldr r3, [pc, #220] @ (8003b0c ) 8003a2e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003a32: 4a36 ldr r2, [pc, #216] @ (8003b0c ) 8003a34: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8003a38: f8c2 3088 str.w r3, [r2, #136] @ 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8003a3c: 4b34 ldr r3, [pc, #208] @ (8003b10 ) 8003a3e: 681b ldr r3, [r3, #0] 8003a40: f003 030f and.w r3, r3, #15 8003a44: 2b06 cmp r3, #6 8003a46: d807 bhi.n 8003a58 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8003a48: 4b31 ldr r3, [pc, #196] @ (8003b10 ) 8003a4a: 681b ldr r3, [r3, #0] 8003a4c: f023 030f bic.w r3, r3, #15 8003a50: 4a2f ldr r2, [pc, #188] @ (8003b10 ) 8003a52: f043 0307 orr.w r3, r3, #7 8003a56: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 8003a58: 4b2e ldr r3, [pc, #184] @ (8003b14 ) 8003a5a: 681b ldr r3, [r3, #0] 8003a5c: 4a2d ldr r2, [pc, #180] @ (8003b14 ) 8003a5e: f043 0301 orr.w r3, r3, #1 8003a62: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 8003a64: 4b2b ldr r3, [pc, #172] @ (8003b14 ) 8003a66: 2200 movs r2, #0 8003a68: 611a str r2, [r3, #16] /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 8003a6a: 4b2a ldr r3, [pc, #168] @ (8003b14 ) 8003a6c: 681a ldr r2, [r3, #0] 8003a6e: 4929 ldr r1, [pc, #164] @ (8003b14 ) 8003a70: 4b29 ldr r3, [pc, #164] @ (8003b18 ) 8003a72: 4013 ands r3, r2 8003a74: 600b str r3, [r1, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8003a76: 4b26 ldr r3, [pc, #152] @ (8003b10 ) 8003a78: 681b ldr r3, [r3, #0] 8003a7a: f003 0308 and.w r3, r3, #8 8003a7e: 2b00 cmp r3, #0 8003a80: d007 beq.n 8003a92 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8003a82: 4b23 ldr r3, [pc, #140] @ (8003b10 ) 8003a84: 681b ldr r3, [r3, #0] 8003a86: f023 030f bic.w r3, r3, #15 8003a8a: 4a21 ldr r2, [pc, #132] @ (8003b10 ) 8003a8c: f043 0307 orr.w r3, r3, #7 8003a90: 6013 str r3, [r2, #0] } #if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; 8003a92: 4b20 ldr r3, [pc, #128] @ (8003b14 ) 8003a94: 2200 movs r2, #0 8003a96: 619a str r2, [r3, #24] /* Reset D2CFGR register */ RCC->D2CFGR = 0x00000000; 8003a98: 4b1e ldr r3, [pc, #120] @ (8003b14 ) 8003a9a: 2200 movs r2, #0 8003a9c: 61da str r2, [r3, #28] /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; 8003a9e: 4b1d ldr r3, [pc, #116] @ (8003b14 ) 8003aa0: 2200 movs r2, #0 8003aa2: 621a str r2, [r3, #32] /* Reset SRDCFGR register */ RCC->SRDCFGR = 0x00000000; #endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; 8003aa4: 4b1b ldr r3, [pc, #108] @ (8003b14 ) 8003aa6: 4a1d ldr r2, [pc, #116] @ (8003b1c ) 8003aa8: 629a str r2, [r3, #40] @ 0x28 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; 8003aaa: 4b1a ldr r3, [pc, #104] @ (8003b14 ) 8003aac: 4a1c ldr r2, [pc, #112] @ (8003b20 ) 8003aae: 62da str r2, [r3, #44] @ 0x2c /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 8003ab0: 4b18 ldr r3, [pc, #96] @ (8003b14 ) 8003ab2: 4a1c ldr r2, [pc, #112] @ (8003b24 ) 8003ab4: 631a str r2, [r3, #48] @ 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 8003ab6: 4b17 ldr r3, [pc, #92] @ (8003b14 ) 8003ab8: 2200 movs r2, #0 8003aba: 635a str r2, [r3, #52] @ 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 8003abc: 4b15 ldr r3, [pc, #84] @ (8003b14 ) 8003abe: 4a19 ldr r2, [pc, #100] @ (8003b24 ) 8003ac0: 639a str r2, [r3, #56] @ 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 8003ac2: 4b14 ldr r3, [pc, #80] @ (8003b14 ) 8003ac4: 2200 movs r2, #0 8003ac6: 63da str r2, [r3, #60] @ 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 8003ac8: 4b12 ldr r3, [pc, #72] @ (8003b14 ) 8003aca: 4a16 ldr r2, [pc, #88] @ (8003b24 ) 8003acc: 641a str r2, [r3, #64] @ 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 8003ace: 4b11 ldr r3, [pc, #68] @ (8003b14 ) 8003ad0: 2200 movs r2, #0 8003ad2: 645a str r2, [r3, #68] @ 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8003ad4: 4b0f ldr r3, [pc, #60] @ (8003b14 ) 8003ad6: 681b ldr r3, [r3, #0] 8003ad8: 4a0e ldr r2, [pc, #56] @ (8003b14 ) 8003ada: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8003ade: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 8003ae0: 4b0c ldr r3, [pc, #48] @ (8003b14 ) 8003ae2: 2200 movs r2, #0 8003ae4: 661a str r2, [r3, #96] @ 0x60 #if (STM32H7_DEV_ID == 0x450UL) /* dual core CM7 or single core line */ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) 8003ae6: 4b10 ldr r3, [pc, #64] @ (8003b28 ) 8003ae8: 681a ldr r2, [r3, #0] 8003aea: 4b10 ldr r3, [pc, #64] @ (8003b2c ) 8003aec: 4013 ands r3, r2 8003aee: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8003af2: d202 bcs.n 8003afa { /* if stm32h7 revY*/ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; 8003af4: 4b0e ldr r3, [pc, #56] @ (8003b30 ) 8003af6: 2201 movs r2, #1 8003af8: 601a str r2, [r3, #0] /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 8003afa: 4b0e ldr r3, [pc, #56] @ (8003b34 ) 8003afc: f243 02d2 movw r2, #12498 @ 0x30d2 8003b00: 601a str r2, [r3, #0] #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ } 8003b02: bf00 nop 8003b04: 46bd mov sp, r7 8003b06: f85d 7b04 ldr.w r7, [sp], #4 8003b0a: 4770 bx lr 8003b0c: e000ed00 .word 0xe000ed00 8003b10: 52002000 .word 0x52002000 8003b14: 58024400 .word 0x58024400 8003b18: eaf6ed7f .word 0xeaf6ed7f 8003b1c: 02020200 .word 0x02020200 8003b20: 01ff0000 .word 0x01ff0000 8003b24: 01010280 .word 0x01010280 8003b28: 5c001000 .word 0x5c001000 8003b2c: ffff0000 .word 0xffff0000 8003b30: 51008108 .word 0x51008108 8003b34: 52004000 .word 0x52004000 08003b38 : uint32_t slaveLastSeen[SLAVES_COUNT] = { 0 }; extern RNG_HandleTypeDef hrng; void UartTasksInit(void) { 8003b38: b580 push {r7, lr} 8003b3a: af00 add r7, sp, #0 uart1TaskData.uartRxBuffer = uart1RxBuffer; 8003b3c: 4b13 ldr r3, [pc, #76] @ (8003b8c ) 8003b3e: 4a14 ldr r2, [pc, #80] @ (8003b90 ) 8003b40: 601a str r2, [r3, #0] uart1TaskData.uartRxBufferLen = UART1_RX_BUFF_SIZE; 8003b42: 4b12 ldr r3, [pc, #72] @ (8003b8c ) 8003b44: f44f 7280 mov.w r2, #256 @ 0x100 8003b48: 809a strh r2, [r3, #4] uart1TaskData.uartTxBuffer = uart1TxBuffer; 8003b4a: 4b10 ldr r3, [pc, #64] @ (8003b8c ) 8003b4c: 4a11 ldr r2, [pc, #68] @ (8003b94 ) 8003b4e: 609a str r2, [r3, #8] uart1TaskData.uartRxBufferLen = UART1_TX_BUFF_SIZE; 8003b50: 4b0e ldr r3, [pc, #56] @ (8003b8c ) 8003b52: f44f 7280 mov.w r2, #256 @ 0x100 8003b56: 809a strh r2, [r3, #4] uart1TaskData.frameData = uart1TaskFrameData; 8003b58: 4b0c ldr r3, [pc, #48] @ (8003b8c ) 8003b5a: 4a0f ldr r2, [pc, #60] @ (8003b98 ) 8003b5c: 611a str r2, [r3, #16] uart1TaskData.frameDataLen = UART1_RX_BUFF_SIZE; 8003b5e: 4b0b ldr r3, [pc, #44] @ (8003b8c ) 8003b60: f44f 7280 mov.w r2, #256 @ 0x100 8003b64: 829a strh r2, [r3, #20] uart1TaskData.huart = &huart1; 8003b66: 4b09 ldr r3, [pc, #36] @ (8003b8c ) 8003b68: 4a0c ldr r2, [pc, #48] @ (8003b9c ) 8003b6a: 631a str r2, [r3, #48] @ 0x30 uart1TaskData.uartNumber = 1; 8003b6c: 4b07 ldr r3, [pc, #28] @ (8003b8c ) 8003b6e: 2201 movs r2, #1 8003b70: f883 2034 strb.w r2, [r3, #52] @ 0x34 uart1TaskData.processDataCb = Uart1ReceivedDataProcessCallback; 8003b74: 4b05 ldr r3, [pc, #20] @ (8003b8c ) 8003b76: 4a0a ldr r2, [pc, #40] @ (8003ba0 ) 8003b78: 629a str r2, [r3, #40] @ 0x28 uart1TaskData.processRxDataMsgBuffer = NULL; 8003b7a: 4b04 ldr r3, [pc, #16] @ (8003b8c ) 8003b7c: 2200 movs r2, #0 8003b7e: 625a str r2, [r3, #36] @ 0x24 UartTaskCreate(&uart1TaskData); 8003b80: 4802 ldr r0, [pc, #8] @ (8003b8c ) 8003b82: f000 f80f bl 8003ba4 } 8003b86: bf00 nop 8003b88: bd80 pop {r7, pc} 8003b8a: bf00 nop 8003b8c: 24000b18 .word 0x24000b18 8003b90: 24000818 .word 0x24000818 8003b94: 24000918 .word 0x24000918 8003b98: 24000a18 .word 0x24000a18 8003b9c: 24000598 .word 0x24000598 8003ba0: 080042a9 .word 0x080042a9 08003ba4 : void UartTaskCreate (UartTaskData* uartTaskData) { 8003ba4: b580 push {r7, lr} 8003ba6: b08c sub sp, #48 @ 0x30 8003ba8: af00 add r7, sp, #0 8003baa: 6078 str r0, [r7, #4] osThreadAttr_t osThreadAttrRxUart = { 0 }; 8003bac: f107 030c add.w r3, r7, #12 8003bb0: 2224 movs r2, #36 @ 0x24 8003bb2: 2100 movs r1, #0 8003bb4: 4618 mov r0, r3 8003bb6: f012 fdce bl 8016756 osThreadAttrRxUart.stack_size = configMINIMAL_STACK_SIZE * 2; 8003bba: f44f 6380 mov.w r3, #1024 @ 0x400 8003bbe: 623b str r3, [r7, #32] osThreadAttrRxUart.priority = (osPriority_t)osPriorityHigh; 8003bc0: 2328 movs r3, #40 @ 0x28 8003bc2: 627b str r3, [r7, #36] @ 0x24 uartTaskData->uartRecieveTaskHandle = osThreadNew (UartRxTask, uartTaskData, &osThreadAttrRxUart); 8003bc4: f107 030c add.w r3, r7, #12 8003bc8: 461a mov r2, r3 8003bca: 6879 ldr r1, [r7, #4] 8003bcc: 4804 ldr r0, [pc, #16] @ (8003be0 ) 8003bce: f00e fb57 bl 8012280 8003bd2: 4602 mov r2, r0 8003bd4: 687b ldr r3, [r7, #4] 8003bd6: 619a str r2, [r3, #24] } 8003bd8: bf00 nop 8003bda: 3730 adds r7, #48 @ 0x30 8003bdc: 46bd mov sp, r7 8003bde: bd80 pop {r7, pc} 8003be0: 08003cf9 .word 0x08003cf9 08003be4 : uart8TaskData.huart = &huart8; uart8TaskData.uartNumber = 8; uart8TaskData.uartRecieveTaskHandle = osThreadNew (UartRxTask, &uart8TaskData, &osThreadAttrRxUart); } void HAL_UART_RxCpltCallback (UART_HandleTypeDef* huart) { 8003be4: b480 push {r7} 8003be6: b083 sub sp, #12 8003be8: af00 add r7, sp, #0 8003bea: 6078 str r0, [r7, #4] } 8003bec: bf00 nop 8003bee: 370c adds r7, #12 8003bf0: 46bd mov sp, r7 8003bf2: f85d 7b04 ldr.w r7, [sp], #4 8003bf6: 4770 bx lr 08003bf8 : void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef* huart, uint16_t Size) { 8003bf8: b580 push {r7, lr} 8003bfa: b082 sub sp, #8 8003bfc: af00 add r7, sp, #0 8003bfe: 6078 str r0, [r7, #4] 8003c00: 460b mov r3, r1 8003c02: 807b strh r3, [r7, #2] if (huart->Instance == USART1) { 8003c04: 687b ldr r3, [r7, #4] 8003c06: 681b ldr r3, [r3, #0] 8003c08: 4a0c ldr r2, [pc, #48] @ (8003c3c ) 8003c0a: 4293 cmp r3, r2 8003c0c: d106 bne.n 8003c1c HandleUartRxCallback(&uart1TaskData, huart, Size); 8003c0e: 887b ldrh r3, [r7, #2] 8003c10: 461a mov r2, r3 8003c12: 6879 ldr r1, [r7, #4] 8003c14: 480a ldr r0, [pc, #40] @ (8003c40 ) 8003c16: f000 f823 bl 8003c60 } else if (huart->Instance == UART8) { HandleUartRxCallback(&uart8TaskData, huart, Size); } } 8003c1a: e00a b.n 8003c32 } else if (huart->Instance == UART8) { 8003c1c: 687b ldr r3, [r7, #4] 8003c1e: 681b ldr r3, [r3, #0] 8003c20: 4a08 ldr r2, [pc, #32] @ (8003c44 ) 8003c22: 4293 cmp r3, r2 8003c24: d105 bne.n 8003c32 HandleUartRxCallback(&uart8TaskData, huart, Size); 8003c26: 887b ldrh r3, [r7, #2] 8003c28: 461a mov r2, r3 8003c2a: 6879 ldr r1, [r7, #4] 8003c2c: 4806 ldr r0, [pc, #24] @ (8003c48 ) 8003c2e: f000 f817 bl 8003c60 } 8003c32: bf00 nop 8003c34: 3708 adds r7, #8 8003c36: 46bd mov sp, r7 8003c38: bd80 pop {r7, pc} 8003c3a: bf00 nop 8003c3c: 40011000 .word 0x40011000 8003c40: 24000b18 .word 0x24000b18 8003c44: 40007c00 .word 0x40007c00 8003c48: 24000b50 .word 0x24000b50 08003c4c : void HAL_UART_TxCpltCallback (UART_HandleTypeDef* huart) { 8003c4c: b480 push {r7} 8003c4e: b083 sub sp, #12 8003c50: af00 add r7, sp, #0 8003c52: 6078 str r0, [r7, #4] if (huart->Instance == UART8) { } } 8003c54: bf00 nop 8003c56: 370c adds r7, #12 8003c58: 46bd mov sp, r7 8003c5a: f85d 7b04 ldr.w r7, [sp], #4 8003c5e: 4770 bx lr 08003c60 : void HandleUartRxCallback (UartTaskData* uartTaskData, UART_HandleTypeDef* huart, uint16_t Size) { 8003c60: b580 push {r7, lr} 8003c62: b088 sub sp, #32 8003c64: af02 add r7, sp, #8 8003c66: 60f8 str r0, [r7, #12] 8003c68: 60b9 str r1, [r7, #8] 8003c6a: 4613 mov r3, r2 8003c6c: 80fb strh r3, [r7, #6] BaseType_t pxHigherPriorityTaskWoken = pdFALSE; 8003c6e: 2300 movs r3, #0 8003c70: 617b str r3, [r7, #20] osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8003c72: 68fb ldr r3, [r7, #12] 8003c74: 6a1b ldr r3, [r3, #32] 8003c76: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003c7a: 4618 mov r0, r3 8003c7c: f00e fd2b bl 80126d6 memcpy (&(uartTaskData->frameData[uartTaskData->frameBytesCount]), uartTaskData->uartRxBuffer, Size); 8003c80: 68fb ldr r3, [r7, #12] 8003c82: 691b ldr r3, [r3, #16] 8003c84: 68fa ldr r2, [r7, #12] 8003c86: 8ad2 ldrh r2, [r2, #22] 8003c88: 1898 adds r0, r3, r2 8003c8a: 68fb ldr r3, [r7, #12] 8003c8c: 681b ldr r3, [r3, #0] 8003c8e: 88fa ldrh r2, [r7, #6] 8003c90: 4619 mov r1, r3 8003c92: f012 fe32 bl 80168fa uartTaskData->frameBytesCount += Size; 8003c96: 68fb ldr r3, [r7, #12] 8003c98: 8ada ldrh r2, [r3, #22] 8003c9a: 88fb ldrh r3, [r7, #6] 8003c9c: 4413 add r3, r2 8003c9e: b29a uxth r2, r3 8003ca0: 68fb ldr r3, [r7, #12] 8003ca2: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 8003ca4: 68fb ldr r3, [r7, #12] 8003ca6: 6a1b ldr r3, [r3, #32] 8003ca8: 4618 mov r0, r3 8003caa: f00e fd5f bl 801276c xTaskNotifyFromISR (uartTaskData->uartRecieveTaskHandle, Size, eSetValueWithOverwrite, &pxHigherPriorityTaskWoken); 8003cae: 68fb ldr r3, [r7, #12] 8003cb0: 6998 ldr r0, [r3, #24] 8003cb2: 88f9 ldrh r1, [r7, #6] 8003cb4: f107 0314 add.w r3, r7, #20 8003cb8: 9300 str r3, [sp, #0] 8003cba: 2300 movs r3, #0 8003cbc: 2203 movs r2, #3 8003cbe: f011 fa4f bl 8015160 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8003cc2: 68fb ldr r3, [r7, #12] 8003cc4: 6b18 ldr r0, [r3, #48] @ 0x30 8003cc6: 68fb ldr r3, [r7, #12] 8003cc8: 6819 ldr r1, [r3, #0] 8003cca: 68fb ldr r3, [r7, #12] 8003ccc: 889b ldrh r3, [r3, #4] 8003cce: 461a mov r2, r3 8003cd0: f00e f9a9 bl 8012026 portEND_SWITCHING_ISR (pxHigherPriorityTaskWoken); 8003cd4: 697b ldr r3, [r7, #20] 8003cd6: 2b00 cmp r3, #0 8003cd8: d007 beq.n 8003cea 8003cda: 4b06 ldr r3, [pc, #24] @ (8003cf4 ) 8003cdc: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8003ce0: 601a str r2, [r3, #0] 8003ce2: f3bf 8f4f dsb sy 8003ce6: f3bf 8f6f isb sy } 8003cea: bf00 nop 8003cec: 3718 adds r7, #24 8003cee: 46bd mov sp, r7 8003cf0: bd80 pop {r7, pc} 8003cf2: bf00 nop 8003cf4: e000ed04 .word 0xe000ed04 08003cf8 : void UartRxTask (void* argument) { 8003cf8: b580 push {r7, lr} 8003cfa: b0d2 sub sp, #328 @ 0x148 8003cfc: af02 add r7, sp, #8 8003cfe: f507 73a0 add.w r3, r7, #320 @ 0x140 8003d02: f5a3 739e sub.w r3, r3, #316 @ 0x13c 8003d06: 6018 str r0, [r3, #0] UartTaskData* uartTaskData = (UartTaskData*)argument; 8003d08: f507 73a0 add.w r3, r7, #320 @ 0x140 8003d0c: f5a3 739e sub.w r3, r3, #316 @ 0x13c 8003d10: 681b ldr r3, [r3, #0] 8003d12: f8c7 312c str.w r3, [r7, #300] @ 0x12c SerialProtocolFrameData spFrameData = { 0 }; 8003d16: f507 73a0 add.w r3, r7, #320 @ 0x140 8003d1a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8003d1e: 4618 mov r0, r3 8003d20: f44f 7386 mov.w r3, #268 @ 0x10c 8003d24: 461a mov r2, r3 8003d26: 2100 movs r1, #0 8003d28: f012 fd15 bl 8016756 uint32_t bytesRec = 0; 8003d2c: f507 73a0 add.w r3, r7, #320 @ 0x140 8003d30: f5a3 739a sub.w r3, r3, #308 @ 0x134 8003d34: 2200 movs r2, #0 8003d36: 601a str r2, [r3, #0] uint32_t crc = 0; 8003d38: 2300 movs r3, #0 8003d3a: f8c7 3128 str.w r3, [r7, #296] @ 0x128 uint16_t frameCommandRaw = 0x0000; 8003d3e: 2300 movs r3, #0 8003d40: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 uint16_t frameBytesCount = 0; 8003d44: 2300 movs r3, #0 8003d46: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 uint16_t frameCrc = 0; 8003d4a: 2300 movs r3, #0 8003d4c: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 uint16_t frameTotalLength = 0; 8003d50: 2300 movs r3, #0 8003d52: f8a7 313e strh.w r3, [r7, #318] @ 0x13e uint16_t dataToSend = 0; 8003d56: 2300 movs r3, #0 8003d58: f8a7 313c strh.w r3, [r7, #316] @ 0x13c portBASE_TYPE crcPass = pdFAIL; 8003d5c: 2300 movs r3, #0 8003d5e: f8c7 3138 str.w r3, [r7, #312] @ 0x138 portBASE_TYPE proceed = pdFALSE; 8003d62: 2300 movs r3, #0 8003d64: f8c7 3134 str.w r3, [r7, #308] @ 0x134 portBASE_TYPE frameTimeout = pdFAIL; 8003d68: 2300 movs r3, #0 8003d6a: f8c7 311c str.w r3, [r7, #284] @ 0x11c enum SerialReceiverStates receverState = srWaitForHeader; 8003d6e: 2300 movs r3, #0 8003d70: f887 3133 strb.w r3, [r7, #307] @ 0x133 uartTaskData->rxDataBufferMutex = osMutexNew (NULL); 8003d74: 2000 movs r0, #0 8003d76: f00e fc28 bl 80125ca 8003d7a: 4602 mov r2, r0 8003d7c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003d80: 621a str r2, [r3, #32] HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8003d82: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003d86: 6b18 ldr r0, [r3, #48] @ 0x30 8003d88: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003d8c: 6819 ldr r1, [r3, #0] 8003d8e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003d92: 889b ldrh r3, [r3, #4] 8003d94: 461a mov r2, r3 8003d96: f00e f946 bl 8012026 while (pdTRUE) { frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8003d9a: f107 020c add.w r2, r7, #12 8003d9e: f44f 63fa mov.w r3, #2000 @ 0x7d0 8003da2: 2100 movs r1, #0 8003da4: 2000 movs r0, #0 8003da6: f011 f8b9 bl 8014f1c 8003daa: 4603 mov r3, r0 8003dac: 2b00 cmp r3, #0 8003dae: bf0c ite eq 8003db0: 2301 moveq r3, #1 8003db2: 2300 movne r3, #0 8003db4: b2db uxtb r3, r3 8003db6: f8c7 311c str.w r3, [r7, #284] @ 0x11c osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8003dba: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003dbe: 6a1b ldr r3, [r3, #32] 8003dc0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003dc4: 4618 mov r0, r3 8003dc6: f00e fc86 bl 80126d6 frameBytesCount = uartTaskData->frameBytesCount; 8003dca: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003dce: 8adb ldrh r3, [r3, #22] 8003dd0: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 osMutexRelease (uartTaskData->rxDataBufferMutex); 8003dd4: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003dd8: 6a1b ldr r3, [r3, #32] 8003dda: 4618 mov r0, r3 8003ddc: f00e fcc6 bl 801276c if ((frameTimeout == pdTRUE) && (frameBytesCount > 0)) { 8003de0: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8003de4: 2b01 cmp r3, #1 8003de6: d10a bne.n 8003dfe 8003de8: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8003dec: 2b00 cmp r3, #0 8003dee: d006 beq.n 8003dfe receverState = srFail; 8003df0: 2304 movs r3, #4 8003df2: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdTRUE; 8003df6: 2301 movs r3, #1 8003df8: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8003dfc: e029 b.n 8003e52 } else { if (frameTimeout == pdFALSE) { 8003dfe: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8003e02: 2b00 cmp r3, #0 8003e04: d111 bne.n 8003e2a proceed = pdTRUE; 8003e06: 2301 movs r3, #1 8003e08: f8c7 3134 str.w r3, [r7, #308] @ 0x134 #if UART_TASK_LOGS printf ("Uart%d: RX bytes received: %ld\n", uartTaskData->uartNumber, bytesRec); 8003e0c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003e10: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8003e14: 4619 mov r1, r3 8003e16: f507 73a0 add.w r3, r7, #320 @ 0x140 8003e1a: f5a3 739a sub.w r3, r3, #308 @ 0x134 8003e1e: 681b ldr r3, [r3, #0] 8003e20: 461a mov r2, r3 8003e22: 48c1 ldr r0, [pc, #772] @ (8004128 ) 8003e24: f012 fc42 bl 80166ac 8003e28: e22f b.n 800428a #endif } else { if (uartTaskData->huart->RxState == HAL_UART_STATE_READY) { 8003e2a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003e2e: 6b1b ldr r3, [r3, #48] @ 0x30 8003e30: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8003e34: 2b20 cmp r3, #32 8003e36: f040 8228 bne.w 800428a HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8003e3a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003e3e: 6b18 ldr r0, [r3, #48] @ 0x30 8003e40: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003e44: 6819 ldr r1, [r3, #0] 8003e46: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003e4a: 889b ldrh r3, [r3, #4] 8003e4c: 461a mov r2, r3 8003e4e: f00e f8ea bl 8012026 } } } while (proceed) { 8003e52: e21a b.n 800428a switch (receverState) { 8003e54: f897 3133 ldrb.w r3, [r7, #307] @ 0x133 8003e58: 2b04 cmp r3, #4 8003e5a: f200 81f1 bhi.w 8004240 8003e5e: a201 add r2, pc, #4 @ (adr r2, 8003e64 ) 8003e60: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003e64: 08003e79 .word 0x08003e79 8003e68: 08003fdb .word 0x08003fdb 8003e6c: 08003fbf .word 0x08003fbf 8003e70: 0800407b .word 0x0800407b 8003e74: 08004135 .word 0x08004135 case srWaitForHeader: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8003e78: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003e7c: 6a1b ldr r3, [r3, #32] 8003e7e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003e82: 4618 mov r0, r3 8003e84: f00e fc27 bl 80126d6 if (uartTaskData->frameData[0] == FRAME_INDICATOR) { 8003e88: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003e8c: 691b ldr r3, [r3, #16] 8003e8e: 781b ldrb r3, [r3, #0] 8003e90: 2baa cmp r3, #170 @ 0xaa 8003e92: f040 8082 bne.w 8003f9a if (frameBytesCount > FRAME_ID_LENGTH) { 8003e96: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8003e9a: 2b02 cmp r3, #2 8003e9c: d914 bls.n 8003ec8 spFrameData.frameHeader.frameId = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_ID_LENGTH - FRAME_COMMAND_LENGTH])); 8003e9e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003ea2: 691b ldr r3, [r3, #16] 8003ea4: 3302 adds r3, #2 8003ea6: 781b ldrb r3, [r3, #0] 8003ea8: 021b lsls r3, r3, #8 8003eaa: b21a sxth r2, r3 8003eac: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003eb0: 691b ldr r3, [r3, #16] 8003eb2: 3301 adds r3, #1 8003eb4: 781b ldrb r3, [r3, #0] 8003eb6: b21b sxth r3, r3 8003eb8: 4313 orrs r3, r2 8003eba: b21b sxth r3, r3 8003ebc: b29a uxth r2, r3 spFrameData.frameHeader.frameId = 8003ebe: f507 73a0 add.w r3, r7, #320 @ 0x140 8003ec2: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8003ec6: 801a strh r2, [r3, #0] } if (frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH) { 8003ec8: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8003ecc: 2b04 cmp r3, #4 8003ece: d923 bls.n 8003f18 frameCommandRaw = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_COMMAND_LENGTH])); 8003ed0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003ed4: 691b ldr r3, [r3, #16] 8003ed6: 3304 adds r3, #4 8003ed8: 781b ldrb r3, [r3, #0] 8003eda: 021b lsls r3, r3, #8 8003edc: b21a sxth r2, r3 8003ede: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003ee2: 691b ldr r3, [r3, #16] 8003ee4: 3303 adds r3, #3 8003ee6: 781b ldrb r3, [r3, #0] 8003ee8: b21b sxth r3, r3 8003eea: 4313 orrs r3, r2 8003eec: b21b sxth r3, r3 8003eee: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 spFrameData.frameHeader.frameCommand = (SerialProtocolCommands)(frameCommandRaw & 0x7FFF); 8003ef2: f8b7 3126 ldrh.w r3, [r7, #294] @ 0x126 8003ef6: b2da uxtb r2, r3 8003ef8: f507 73a0 add.w r3, r7, #320 @ 0x140 8003efc: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8003f00: 709a strb r2, [r3, #2] spFrameData.frameHeader.isResponseFrame = (frameCommandRaw & 0x8000) != 0 ? pdTRUE : pdFALSE; 8003f02: f9b7 3126 ldrsh.w r3, [r7, #294] @ 0x126 8003f06: 13db asrs r3, r3, #15 8003f08: b21b sxth r3, r3 8003f0a: f003 0201 and.w r2, r3, #1 8003f0e: f507 73a0 add.w r3, r7, #320 @ 0x140 8003f12: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8003f16: 609a str r2, [r3, #8] } if ((frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH) && ((spFrameData.frameHeader.frameCommand & 0x8000) != 0)) { 8003f18: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8003f1c: 2b05 cmp r3, #5 8003f1e: d913 bls.n 8003f48 8003f20: f507 73a0 add.w r3, r7, #320 @ 0x140 8003f24: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8003f28: 789b ldrb r3, [r3, #2] 8003f2a: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003f2e: 2b00 cmp r3, #0 8003f30: d00a beq.n 8003f48 spFrameData.frameHeader.respStatus = (SerialProtocolRespStatus)(uartTaskData->frameData[FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH]); 8003f32: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003f36: 691b ldr r3, [r3, #16] 8003f38: 3305 adds r3, #5 8003f3a: 781b ldrb r3, [r3, #0] 8003f3c: b25a sxtb r2, r3 8003f3e: f507 73a0 add.w r3, r7, #320 @ 0x140 8003f42: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8003f46: 70da strb r2, [r3, #3] } if (frameBytesCount >= FRAME_HEADER_LENGTH) { 8003f48: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8003f4c: 2b07 cmp r3, #7 8003f4e: d920 bls.n 8003f92 spFrameData.frameHeader.frameDataLength = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH])); 8003f50: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003f54: 691b ldr r3, [r3, #16] 8003f56: 3306 adds r3, #6 8003f58: 781b ldrb r3, [r3, #0] 8003f5a: 021b lsls r3, r3, #8 8003f5c: b21a sxth r2, r3 8003f5e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003f62: 691b ldr r3, [r3, #16] 8003f64: 3305 adds r3, #5 8003f66: 781b ldrb r3, [r3, #0] 8003f68: b21b sxth r3, r3 8003f6a: 4313 orrs r3, r2 8003f6c: b21b sxth r3, r3 8003f6e: b29a uxth r2, r3 8003f70: f507 73a0 add.w r3, r7, #320 @ 0x140 8003f74: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8003f78: 809a strh r2, [r3, #4] frameTotalLength = FRAME_HEADER_LENGTH + spFrameData.frameHeader.frameDataLength + FRAME_CRC_LENGTH; 8003f7a: f507 73a0 add.w r3, r7, #320 @ 0x140 8003f7e: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8003f82: 889b ldrh r3, [r3, #4] 8003f84: 330a adds r3, #10 8003f86: f8a7 313e strh.w r3, [r7, #318] @ 0x13e receverState = srRecieveData; 8003f8a: 2302 movs r3, #2 8003f8c: f887 3133 strb.w r3, [r7, #307] @ 0x133 8003f90: e00e b.n 8003fb0 } else { proceed = pdFALSE; 8003f92: 2300 movs r3, #0 8003f94: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8003f98: e00a b.n 8003fb0 } } else { if (frameBytesCount > 0) { 8003f9a: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8003f9e: 2b00 cmp r3, #0 8003fa0: d003 beq.n 8003faa receverState = srFail; 8003fa2: 2304 movs r3, #4 8003fa4: f887 3133 strb.w r3, [r7, #307] @ 0x133 8003fa8: e002 b.n 8003fb0 } else { proceed = pdFALSE; 8003faa: 2300 movs r3, #0 8003fac: f8c7 3134 str.w r3, [r7, #308] @ 0x134 } } osMutexRelease (uartTaskData->rxDataBufferMutex); 8003fb0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003fb4: 6a1b ldr r3, [r3, #32] 8003fb6: 4618 mov r0, r3 8003fb8: f00e fbd8 bl 801276c break; 8003fbc: e165 b.n 800428a case srRecieveData: if (frameBytesCount >= frameTotalLength) { 8003fbe: f8b7 2124 ldrh.w r2, [r7, #292] @ 0x124 8003fc2: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8003fc6: 429a cmp r2, r3 8003fc8: d303 bcc.n 8003fd2 receverState = srCheckCrc; 8003fca: 2301 movs r3, #1 8003fcc: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { proceed = pdFALSE; } break; 8003fd0: e15b b.n 800428a proceed = pdFALSE; 8003fd2: 2300 movs r3, #0 8003fd4: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 8003fd8: e157 b.n 800428a case srCheckCrc: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8003fda: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003fde: 6a1b ldr r3, [r3, #32] 8003fe0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003fe4: 4618 mov r0, r3 8003fe6: f00e fb76 bl 80126d6 frameCrc = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[frameTotalLength - FRAME_CRC_LENGTH])); 8003fea: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8003fee: 691a ldr r2, [r3, #16] 8003ff0: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8003ff4: 3b01 subs r3, #1 8003ff6: 4413 add r3, r2 8003ff8: 781b ldrb r3, [r3, #0] 8003ffa: 021b lsls r3, r3, #8 8003ffc: b21a sxth r2, r3 8003ffe: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004002: 6919 ldr r1, [r3, #16] 8004004: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004008: 3b02 subs r3, #2 800400a: 440b add r3, r1 800400c: 781b ldrb r3, [r3, #0] 800400e: b21b sxth r3, r3 8004010: 4313 orrs r3, r2 8004012: b21b sxth r3, r3 8004014: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)(uartTaskData->frameData), frameTotalLength - FRAME_CRC_LENGTH); 8004018: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800401c: 6919 ldr r1, [r3, #16] 800401e: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004022: 3b02 subs r3, #2 8004024: 461a mov r2, r3 8004026: 4841 ldr r0, [pc, #260] @ (800412c ) 8004028: f002 fb34 bl 8006694 800402c: f8c7 0128 str.w r0, [r7, #296] @ 0x128 osMutexRelease (uartTaskData->rxDataBufferMutex); 8004030: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004034: 6a1b ldr r3, [r3, #32] 8004036: 4618 mov r0, r3 8004038: f00e fb98 bl 801276c crcPass = frameCrc == crc; 800403c: f8b7 3122 ldrh.w r3, [r7, #290] @ 0x122 8004040: f8d7 2128 ldr.w r2, [r7, #296] @ 0x128 8004044: 429a cmp r2, r3 8004046: bf0c ite eq 8004048: 2301 moveq r3, #1 800404a: 2300 movne r3, #0 800404c: b2db uxtb r3, r3 800404e: f8c7 3138 str.w r3, [r7, #312] @ 0x138 if (crcPass) { 8004052: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 8004056: 2b00 cmp r3, #0 8004058: d00b beq.n 8004072 #if UART_TASK_LOGS printf ("Uart%d: Frame CRC PASS\n", uartTaskData->uartNumber); 800405a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800405e: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8004062: 4619 mov r1, r3 8004064: 4832 ldr r0, [pc, #200] @ (8004130 ) 8004066: f012 fb21 bl 80166ac #endif receverState = srExecuteCmd; 800406a: 2303 movs r3, #3 800406c: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { receverState = srFail; } break; 8004070: e10b b.n 800428a receverState = srFail; 8004072: 2304 movs r3, #4 8004074: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004078: e107 b.n 800428a case srExecuteCmd: if ((uartTaskData->processDataCb != NULL) || (uartTaskData->processRxDataMsgBuffer != NULL)) { 800407a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800407e: 6a9b ldr r3, [r3, #40] @ 0x28 8004080: 2b00 cmp r3, #0 8004082: d104 bne.n 800408e 8004084: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004088: 6a5b ldr r3, [r3, #36] @ 0x24 800408a: 2b00 cmp r3, #0 800408c: d01e beq.n 80040cc osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 800408e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004092: 6a1b ldr r3, [r3, #32] 8004094: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004098: 4618 mov r0, r3 800409a: f00e fb1c bl 80126d6 memcpy (spFrameData.dataBuffer, &(uartTaskData->frameData[FRAME_HEADER_LENGTH]), spFrameData.frameHeader.frameDataLength); 800409e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80040a2: 691b ldr r3, [r3, #16] 80040a4: f103 0108 add.w r1, r3, #8 80040a8: f507 73a0 add.w r3, r7, #320 @ 0x140 80040ac: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80040b0: 889b ldrh r3, [r3, #4] 80040b2: 461a mov r2, r3 80040b4: f107 0310 add.w r3, r7, #16 80040b8: 330c adds r3, #12 80040ba: 4618 mov r0, r3 80040bc: f012 fc1d bl 80168fa osMutexRelease (uartTaskData->rxDataBufferMutex); 80040c0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80040c4: 6a1b ldr r3, [r3, #32] 80040c6: 4618 mov r0, r3 80040c8: f00e fb50 bl 801276c } if (uartTaskData->processRxDataMsgBuffer != NULL) { 80040cc: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80040d0: 6a5b ldr r3, [r3, #36] @ 0x24 80040d2: 2b00 cmp r3, #0 80040d4: d015 beq.n 8004102 if(xMessageBufferSend (uartTaskData->processRxDataMsgBuffer, &spFrameData, sizeof (SerialProtocolFrameHeader) + spFrameData.frameHeader.frameDataLength, pdMS_TO_TICKS (200)) == pdFALSE) 80040d6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80040da: 6a58 ldr r0, [r3, #36] @ 0x24 80040dc: f507 73a0 add.w r3, r7, #320 @ 0x140 80040e0: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80040e4: 889b ldrh r3, [r3, #4] 80040e6: f103 020c add.w r2, r3, #12 80040ea: f107 0110 add.w r1, r7, #16 80040ee: 23c8 movs r3, #200 @ 0xc8 80040f0: f00f fd5e bl 8013bb0 80040f4: 4603 mov r3, r0 80040f6: 2b00 cmp r3, #0 80040f8: d103 bne.n 8004102 { receverState = srFail; 80040fa: 2304 movs r3, #4 80040fc: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004100: e0c3 b.n 800428a } } if (uartTaskData->processDataCb != NULL) { 8004102: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004106: 6a9b ldr r3, [r3, #40] @ 0x28 8004108: 2b00 cmp r3, #0 800410a: d008 beq.n 800411e uartTaskData->processDataCb (uartTaskData, &spFrameData); 800410c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004110: 6a9b ldr r3, [r3, #40] @ 0x28 8004112: f107 0210 add.w r2, r7, #16 8004116: 4611 mov r1, r2 8004118: f8d7 012c ldr.w r0, [r7, #300] @ 0x12c 800411c: 4798 blx r3 } receverState = srFinish; 800411e: 2305 movs r3, #5 8004120: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004124: e0b1 b.n 800428a 8004126: bf00 nop 8004128: 080174bc .word 0x080174bc 800412c: 240003d4 .word 0x240003d4 8004130: 080174dc .word 0x080174dc case srFail: dataToSend = 0; 8004134: 2300 movs r3, #0 8004136: f8a7 313c strh.w r3, [r7, #316] @ 0x13c if ((frameTimeout == pdTRUE) && (frameBytesCount > 2)) { 800413a: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 800413e: 2b01 cmp r3, #1 8004140: d124 bne.n 800418c 8004142: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004146: 2b02 cmp r3, #2 8004148: d920 bls.n 800418c dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0); 800414a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800414e: 6898 ldr r0, [r3, #8] 8004150: f507 73a0 add.w r3, r7, #320 @ 0x140 8004154: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004158: 8819 ldrh r1, [r3, #0] 800415a: f507 73a0 add.w r3, r7, #320 @ 0x140 800415e: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004162: 789a ldrb r2, [r3, #2] 8004164: 2300 movs r3, #0 8004166: 9301 str r3, [sp, #4] 8004168: 2300 movs r3, #0 800416a: 9300 str r3, [sp, #0] 800416c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8004170: f7fe fdac bl 8002ccc 8004174: 4603 mov r3, r0 8004176: f8a7 313c strh.w r3, [r7, #316] @ 0x13c #if UART_TASK_LOGS printf ("Uart%d: RX data receiver timeout!\n", uartTaskData->uartNumber); 800417a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800417e: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8004182: 4619 mov r1, r3 8004184: 4844 ldr r0, [pc, #272] @ (8004298 ) 8004186: f012 fa91 bl 80166ac 800418a: e03c b.n 8004206 #endif } else if (!crcPass) { 800418c: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 8004190: 2b00 cmp r3, #0 8004192: d120 bne.n 80041d6 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spCrcFail, NULL, 0); 8004194: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004198: 6898 ldr r0, [r3, #8] 800419a: f507 73a0 add.w r3, r7, #320 @ 0x140 800419e: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80041a2: 8819 ldrh r1, [r3, #0] 80041a4: f507 73a0 add.w r3, r7, #320 @ 0x140 80041a8: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80041ac: 789a ldrb r2, [r3, #2] 80041ae: 2300 movs r3, #0 80041b0: 9301 str r3, [sp, #4] 80041b2: 2300 movs r3, #0 80041b4: 9300 str r3, [sp, #0] 80041b6: f06f 0301 mvn.w r3, #1 80041ba: f7fe fd87 bl 8002ccc 80041be: 4603 mov r3, r0 80041c0: f8a7 313c strh.w r3, [r7, #316] @ 0x13c #if UART_TASK_LOGS printf ("Uart%d: Frame CRC FAIL\n", uartTaskData->uartNumber); 80041c4: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80041c8: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 80041cc: 4619 mov r1, r3 80041ce: 4833 ldr r0, [pc, #204] @ (800429c ) 80041d0: f012 fa6c bl 80166ac 80041d4: e017 b.n 8004206 #endif } else { dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spInternalError, NULL, 0); 80041d6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80041da: 6898 ldr r0, [r3, #8] 80041dc: f507 73a0 add.w r3, r7, #320 @ 0x140 80041e0: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80041e4: 8819 ldrh r1, [r3, #0] 80041e6: f507 73a0 add.w r3, r7, #320 @ 0x140 80041ea: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80041ee: 789a ldrb r2, [r3, #2] 80041f0: 2300 movs r3, #0 80041f2: 9301 str r3, [sp, #4] 80041f4: 2300 movs r3, #0 80041f6: 9300 str r3, [sp, #0] 80041f8: f06f 0303 mvn.w r3, #3 80041fc: f7fe fd66 bl 8002ccc 8004200: 4603 mov r3, r0 8004202: f8a7 313c strh.w r3, [r7, #316] @ 0x13c } if (dataToSend > 0) { 8004206: f8b7 313c ldrh.w r3, [r7, #316] @ 0x13c 800420a: 2b00 cmp r3, #0 800420c: d00a beq.n 8004224 HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 800420e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004212: 6b18 ldr r0, [r3, #48] @ 0x30 8004214: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004218: 689b ldr r3, [r3, #8] 800421a: f8b7 213c ldrh.w r2, [r7, #316] @ 0x13c 800421e: 4619 mov r1, r3 8004220: f00b fa2c bl 800f67c } #if UART_TASK_LOGS printf ("Uart%d: TX bytes sent: %d\n", dataToSend, uartTaskData->uartNumber); 8004224: f8b7 113c ldrh.w r1, [r7, #316] @ 0x13c 8004228: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800422c: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8004230: 461a mov r2, r3 8004232: 481b ldr r0, [pc, #108] @ (80042a0 ) 8004234: f012 fa3a bl 80166ac #endif receverState = srFinish; 8004238: 2305 movs r3, #5 800423a: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 800423e: e024 b.n 800428a case srFinish: default: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004240: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004244: 6a1b ldr r3, [r3, #32] 8004246: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800424a: 4618 mov r0, r3 800424c: f00e fa43 bl 80126d6 uartTaskData->frameBytesCount = 0; 8004250: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004254: 2200 movs r2, #0 8004256: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 8004258: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800425c: 6a1b ldr r3, [r3, #32] 800425e: 4618 mov r0, r3 8004260: f00e fa84 bl 801276c spFrameData.frameHeader.frameCommand = spUnknown; 8004264: f507 73a0 add.w r3, r7, #320 @ 0x140 8004268: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800426c: 2209 movs r2, #9 800426e: 709a strb r2, [r3, #2] frameTotalLength = 0; 8004270: 2300 movs r3, #0 8004272: f8a7 313e strh.w r3, [r7, #318] @ 0x13e outputDataBufferPos = 0; 8004276: 4b0b ldr r3, [pc, #44] @ (80042a4 ) 8004278: 2200 movs r2, #0 800427a: 801a strh r2, [r3, #0] receverState = srWaitForHeader; 800427c: 2300 movs r3, #0 800427e: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdFALSE; 8004282: 2300 movs r3, #0 8004284: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 8004288: bf00 nop while (proceed) { 800428a: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 800428e: 2b00 cmp r3, #0 8004290: f47f ade0 bne.w 8003e54 frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8004294: e581 b.n 8003d9a 8004296: bf00 nop 8004298: 080174f4 .word 0x080174f4 800429c: 08017518 .word 0x08017518 80042a0: 08017530 .word 0x08017530 80042a4: 24000c08 .word 0x24000c08 080042a8 : void Uart8ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { Uart1ReceivedDataProcessCallback(arg, spFrameData); } void Uart1ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 80042a8: b590 push {r4, r7, lr} 80042aa: b0a1 sub sp, #132 @ 0x84 80042ac: af06 add r7, sp, #24 80042ae: 6078 str r0, [r7, #4] 80042b0: 6039 str r1, [r7, #0] UartTaskData* uartTaskData = (UartTaskData*)arg; 80042b2: 687b ldr r3, [r7, #4] 80042b4: 64bb str r3, [r7, #72] @ 0x48 uint16_t dataToSend = 0; 80042b6: 2300 movs r3, #0 80042b8: f8a7 3046 strh.w r3, [r7, #70] @ 0x46 outputDataBufferPos = 0; 80042bc: 4baa ldr r3, [pc, #680] @ (8004568 ) 80042be: 2200 movs r2, #0 80042c0: 801a strh r2, [r3, #0] uint16_t inputDataBufferPos = 0; 80042c2: 2300 movs r3, #0 80042c4: 867b strh r3, [r7, #50] @ 0x32 SerialProtocolRespStatus respStatus = spUnknownCommand; 80042c6: 23fd movs r3, #253 @ 0xfd 80042c8: f887 3067 strb.w r3, [r7, #103] @ 0x67 switch (spFrameData->frameHeader.frameCommand) { 80042cc: 683b ldr r3, [r7, #0] 80042ce: 789b ldrb r3, [r3, #2] 80042d0: 2b08 cmp r3, #8 80042d2: f200 8311 bhi.w 80048f8 80042d6: a201 add r2, pc, #4 @ (adr r2, 80042dc ) 80042d8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80042dc: 08004301 .word 0x08004301 80042e0: 080043ef .word 0x080043ef 80042e4: 080044e9 .word 0x080044e9 80042e8: 080045ff .word 0x080045ff 80042ec: 080046a1 .word 0x080046a1 80042f0: 080047ab .word 0x080047ab 80042f4: 08004801 .word 0x08004801 80042f8: 08004743 .word 0x08004743 80042fc: 08004857 .word 0x08004857 case spGetElectricalMeasurments: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8004300: 4b9a ldr r3, [pc, #616] @ (800456c ) 8004302: 681b ldr r3, [r3, #0] 8004304: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004308: 4618 mov r0, r3 800430a: f00e f9e4 bl 80126d6 800430e: 4603 mov r3, r0 8004310: 2b00 cmp r3, #0 8004312: d168 bne.n 80043e6 for (int i = 0; i < 3; i++) { 8004314: 2300 movs r3, #0 8004316: 663b str r3, [r7, #96] @ 0x60 8004318: e00b b.n 8004332 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltageRMS[i], sizeof (float)); 800431a: 6e3b ldr r3, [r7, #96] @ 0x60 800431c: 009b lsls r3, r3, #2 800431e: 4a94 ldr r2, [pc, #592] @ (8004570 ) 8004320: 441a add r2, r3 8004322: 2304 movs r3, #4 8004324: 4990 ldr r1, [pc, #576] @ (8004568 ) 8004326: 4893 ldr r0, [pc, #588] @ (8004574 ) 8004328: f7fe fc6c bl 8002c04 for (int i = 0; i < 3; i++) { 800432c: 6e3b ldr r3, [r7, #96] @ 0x60 800432e: 3301 adds r3, #1 8004330: 663b str r3, [r7, #96] @ 0x60 8004332: 6e3b ldr r3, [r7, #96] @ 0x60 8004334: 2b02 cmp r3, #2 8004336: ddf0 ble.n 800431a } for (int i = 0; i < 3; i++) { 8004338: 2300 movs r3, #0 800433a: 65fb str r3, [r7, #92] @ 0x5c 800433c: e00d b.n 800435a WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltagePeak[i], sizeof (float)); 800433e: 6dfb ldr r3, [r7, #92] @ 0x5c 8004340: 3302 adds r3, #2 8004342: 009b lsls r3, r3, #2 8004344: 4a8a ldr r2, [pc, #552] @ (8004570 ) 8004346: 4413 add r3, r2 8004348: 1d1a adds r2, r3, #4 800434a: 2304 movs r3, #4 800434c: 4986 ldr r1, [pc, #536] @ (8004568 ) 800434e: 4889 ldr r0, [pc, #548] @ (8004574 ) 8004350: f7fe fc58 bl 8002c04 for (int i = 0; i < 3; i++) { 8004354: 6dfb ldr r3, [r7, #92] @ 0x5c 8004356: 3301 adds r3, #1 8004358: 65fb str r3, [r7, #92] @ 0x5c 800435a: 6dfb ldr r3, [r7, #92] @ 0x5c 800435c: 2b02 cmp r3, #2 800435e: ddee ble.n 800433e } for (int i = 0; i < 3; i++) { 8004360: 2300 movs r3, #0 8004362: 65bb str r3, [r7, #88] @ 0x58 8004364: e00c b.n 8004380 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentRMS[i], sizeof (float)); 8004366: 6dbb ldr r3, [r7, #88] @ 0x58 8004368: 3306 adds r3, #6 800436a: 009b lsls r3, r3, #2 800436c: 4a80 ldr r2, [pc, #512] @ (8004570 ) 800436e: 441a add r2, r3 8004370: 2304 movs r3, #4 8004372: 497d ldr r1, [pc, #500] @ (8004568 ) 8004374: 487f ldr r0, [pc, #508] @ (8004574 ) 8004376: f7fe fc45 bl 8002c04 for (int i = 0; i < 3; i++) { 800437a: 6dbb ldr r3, [r7, #88] @ 0x58 800437c: 3301 adds r3, #1 800437e: 65bb str r3, [r7, #88] @ 0x58 8004380: 6dbb ldr r3, [r7, #88] @ 0x58 8004382: 2b02 cmp r3, #2 8004384: ddef ble.n 8004366 } for (int i = 0; i < 3; i++) { 8004386: 2300 movs r3, #0 8004388: 657b str r3, [r7, #84] @ 0x54 800438a: e00d b.n 80043a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentPeak[i], sizeof (float)); 800438c: 6d7b ldr r3, [r7, #84] @ 0x54 800438e: 3308 adds r3, #8 8004390: 009b lsls r3, r3, #2 8004392: 4a77 ldr r2, [pc, #476] @ (8004570 ) 8004394: 4413 add r3, r2 8004396: 1d1a adds r2, r3, #4 8004398: 2304 movs r3, #4 800439a: 4973 ldr r1, [pc, #460] @ (8004568 ) 800439c: 4875 ldr r0, [pc, #468] @ (8004574 ) 800439e: f7fe fc31 bl 8002c04 for (int i = 0; i < 3; i++) { 80043a2: 6d7b ldr r3, [r7, #84] @ 0x54 80043a4: 3301 adds r3, #1 80043a6: 657b str r3, [r7, #84] @ 0x54 80043a8: 6d7b ldr r3, [r7, #84] @ 0x54 80043aa: 2b02 cmp r3, #2 80043ac: ddee ble.n 800438c } for (int i = 0; i < 3; i++) { 80043ae: 2300 movs r3, #0 80043b0: 653b str r3, [r7, #80] @ 0x50 80043b2: e00c b.n 80043ce WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.power[i], sizeof (float)); 80043b4: 6d3b ldr r3, [r7, #80] @ 0x50 80043b6: 330c adds r3, #12 80043b8: 009b lsls r3, r3, #2 80043ba: 4a6d ldr r2, [pc, #436] @ (8004570 ) 80043bc: 441a add r2, r3 80043be: 2304 movs r3, #4 80043c0: 4969 ldr r1, [pc, #420] @ (8004568 ) 80043c2: 486c ldr r0, [pc, #432] @ (8004574 ) 80043c4: f7fe fc1e bl 8002c04 for (int i = 0; i < 3; i++) { 80043c8: 6d3b ldr r3, [r7, #80] @ 0x50 80043ca: 3301 adds r3, #1 80043cc: 653b str r3, [r7, #80] @ 0x50 80043ce: 6d3b ldr r3, [r7, #80] @ 0x50 80043d0: 2b02 cmp r3, #2 80043d2: ddef ble.n 80043b4 } osMutexRelease (resMeasurementsMutex); 80043d4: 4b65 ldr r3, [pc, #404] @ (800456c ) 80043d6: 681b ldr r3, [r3, #0] 80043d8: 4618 mov r0, r3 80043da: f00e f9c7 bl 801276c respStatus = spOK; 80043de: 2300 movs r3, #0 80043e0: f887 3067 strb.w r3, [r7, #103] @ 0x67 } else { respStatus = spInternalError; } break; 80043e4: e28c b.n 8004900 respStatus = spInternalError; 80043e6: 23fc movs r3, #252 @ 0xfc 80043e8: f887 3067 strb.w r3, [r7, #103] @ 0x67 break; 80043ec: e288 b.n 8004900 case spGetSensorMeasurments: if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80043ee: 4b62 ldr r3, [pc, #392] @ (8004578 ) 80043f0: 681b ldr r3, [r3, #0] 80043f2: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80043f6: 4618 mov r0, r3 80043f8: f00e f96d bl 80126d6 80043fc: 4603 mov r3, r0 80043fe: 2b00 cmp r3, #0 8004400: d16e bne.n 80044e0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[0], sizeof (float)); 8004402: 2304 movs r3, #4 8004404: 4a5d ldr r2, [pc, #372] @ (800457c ) 8004406: 4958 ldr r1, [pc, #352] @ (8004568 ) 8004408: 485a ldr r0, [pc, #360] @ (8004574 ) 800440a: f7fe fbfb bl 8002c04 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[1], sizeof (float)); 800440e: 2304 movs r3, #4 8004410: 4a5b ldr r2, [pc, #364] @ (8004580 ) 8004412: 4955 ldr r1, [pc, #340] @ (8004568 ) 8004414: 4857 ldr r0, [pc, #348] @ (8004574 ) 8004416: f7fe fbf5 bl 8002c04 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.fanVoltage, sizeof (float)); 800441a: 2304 movs r3, #4 800441c: 4a59 ldr r2, [pc, #356] @ (8004584 ) 800441e: 4952 ldr r1, [pc, #328] @ (8004568 ) 8004420: 4854 ldr r0, [pc, #336] @ (8004574 ) 8004422: f7fe fbef bl 8002c04 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoder, sizeof (float)); 8004426: 2304 movs r3, #4 8004428: 4a57 ldr r2, [pc, #348] @ (8004588 ) 800442a: 494f ldr r1, [pc, #316] @ (8004568 ) 800442c: 4851 ldr r0, [pc, #324] @ (8004574 ) 800442e: f7fe fbe9 bl 8002c04 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXStatus, sizeof (uint8_t)); 8004432: 2301 movs r3, #1 8004434: 4a55 ldr r2, [pc, #340] @ (800458c ) 8004436: 494c ldr r1, [pc, #304] @ (8004568 ) 8004438: 484e ldr r0, [pc, #312] @ (8004574 ) 800443a: f7fe fbe3 bl 8002c04 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYStatus, sizeof (uint8_t)); 800443e: 2301 movs r3, #1 8004440: 4a53 ldr r2, [pc, #332] @ (8004590 ) 8004442: 4949 ldr r1, [pc, #292] @ (8004568 ) 8004444: 484b ldr r0, [pc, #300] @ (8004574 ) 8004446: f7fe fbdd bl 8002c04 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXAveCurrent, sizeof (float)); 800444a: 2304 movs r3, #4 800444c: 4a51 ldr r2, [pc, #324] @ (8004594 ) 800444e: 4946 ldr r1, [pc, #280] @ (8004568 ) 8004450: 4848 ldr r0, [pc, #288] @ (8004574 ) 8004452: f7fe fbd7 bl 8002c04 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYAveCurrent, sizeof (float)); 8004456: 2304 movs r3, #4 8004458: 4a4f ldr r2, [pc, #316] @ (8004598 ) 800445a: 4943 ldr r1, [pc, #268] @ (8004568 ) 800445c: 4845 ldr r0, [pc, #276] @ (8004574 ) 800445e: f7fe fbd1 bl 8002c04 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXPeakCurrent, sizeof (float)); 8004462: 2304 movs r3, #4 8004464: 4a4d ldr r2, [pc, #308] @ (800459c ) 8004466: 4940 ldr r1, [pc, #256] @ (8004568 ) 8004468: 4842 ldr r0, [pc, #264] @ (8004574 ) 800446a: f7fe fbcb bl 8002c04 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYPeakCurrent, sizeof (float)); 800446e: 2304 movs r3, #4 8004470: 4a4b ldr r2, [pc, #300] @ (80045a0 ) 8004472: 493d ldr r1, [pc, #244] @ (8004568 ) 8004474: 483f ldr r0, [pc, #252] @ (8004574 ) 8004476: f7fe fbc5 bl 8002c04 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchUp, sizeof (uint8_t)); 800447a: 2301 movs r3, #1 800447c: 4a49 ldr r2, [pc, #292] @ (80045a4 ) 800447e: 493a ldr r1, [pc, #232] @ (8004568 ) 8004480: 483c ldr r0, [pc, #240] @ (8004574 ) 8004482: f7fe fbbf bl 8002c04 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchDown, sizeof (uint8_t)); 8004486: 2301 movs r3, #1 8004488: 4a47 ldr r2, [pc, #284] @ (80045a8 ) 800448a: 4937 ldr r1, [pc, #220] @ (8004568 ) 800448c: 4839 ldr r0, [pc, #228] @ (8004574 ) 800448e: f7fe fbb9 bl 8002c04 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchCenter, sizeof (uint8_t)); 8004492: 2301 movs r3, #1 8004494: 4a45 ldr r2, [pc, #276] @ (80045ac ) 8004496: 4934 ldr r1, [pc, #208] @ (8004568 ) 8004498: 4836 ldr r0, [pc, #216] @ (8004574 ) 800449a: f7fe fbb3 bl 8002c04 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchUp, sizeof (uint8_t)); 800449e: 2301 movs r3, #1 80044a0: 4a43 ldr r2, [pc, #268] @ (80045b0 ) 80044a2: 4931 ldr r1, [pc, #196] @ (8004568 ) 80044a4: 4833 ldr r0, [pc, #204] @ (8004574 ) 80044a6: f7fe fbad bl 8002c04 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchDown, sizeof (uint8_t)); 80044aa: 2301 movs r3, #1 80044ac: 4a41 ldr r2, [pc, #260] @ (80045b4 ) 80044ae: 492e ldr r1, [pc, #184] @ (8004568 ) 80044b0: 4830 ldr r0, [pc, #192] @ (8004574 ) 80044b2: f7fe fba7 bl 8002c04 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchCenter, sizeof (uint8_t)); 80044b6: 2301 movs r3, #1 80044b8: 4a3f ldr r2, [pc, #252] @ (80045b8 ) 80044ba: 492b ldr r1, [pc, #172] @ (8004568 ) 80044bc: 482d ldr r0, [pc, #180] @ (8004574 ) 80044be: f7fe fba1 bl 8002c04 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.powerSupplyFailMask, sizeof (uint8_t)); 80044c2: 2301 movs r3, #1 80044c4: 4a3d ldr r2, [pc, #244] @ (80045bc ) 80044c6: 4928 ldr r1, [pc, #160] @ (8004568 ) 80044c8: 482a ldr r0, [pc, #168] @ (8004574 ) 80044ca: f7fe fb9b bl 8002c04 osMutexRelease (sensorsInfoMutex); 80044ce: 4b2a ldr r3, [pc, #168] @ (8004578 ) 80044d0: 681b ldr r3, [r3, #0] 80044d2: 4618 mov r0, r3 80044d4: f00e f94a bl 801276c respStatus = spOK; 80044d8: 2300 movs r3, #0 80044da: f887 3067 strb.w r3, [r7, #103] @ 0x67 } else { respStatus = spInternalError; } break; 80044de: e20f b.n 8004900 respStatus = spInternalError; 80044e0: 23fc movs r3, #252 @ 0xfc 80044e2: f887 3067 strb.w r3, [r7, #103] @ 0x67 break; 80044e6: e20b b.n 8004900 case spSetFanSpeed: osTimerStop (fanTimerHandle); 80044e8: 4b35 ldr r3, [pc, #212] @ (80045c0 ) 80044ea: 681b ldr r3, [r3, #0] 80044ec: 4618 mov r0, r3 80044ee: f00e f835 bl 801255c int32_t fanTimerPeriod = 0; 80044f2: 2300 movs r3, #0 80044f4: 62fb str r3, [r7, #44] @ 0x2c uint32_t pulse = 0; 80044f6: 2300 movs r3, #0 80044f8: 62bb str r3, [r7, #40] @ 0x28 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse); 80044fa: 683b ldr r3, [r7, #0] 80044fc: 330c adds r3, #12 80044fe: f107 0228 add.w r2, r7, #40 @ 0x28 8004502: f107 0132 add.w r1, r7, #50 @ 0x32 8004506: 4618 mov r0, r3 8004508: f7fe fbad bl 8002c66 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&fanTimerPeriod); 800450c: 683b ldr r3, [r7, #0] 800450e: 330c adds r3, #12 8004510: f107 022c add.w r2, r7, #44 @ 0x2c 8004514: f107 0132 add.w r1, r7, #50 @ 0x32 8004518: 4618 mov r0, r3 800451a: f7fe fba4 bl 8002c66 fanTimerConfigOC.Pulse = pulse * 10; 800451e: 6aba ldr r2, [r7, #40] @ 0x28 8004520: 4613 mov r3, r2 8004522: 009b lsls r3, r3, #2 8004524: 4413 add r3, r2 8004526: 005b lsls r3, r3, #1 8004528: 461a mov r2, r3 800452a: 4b26 ldr r3, [pc, #152] @ (80045c4 ) 800452c: 605a str r2, [r3, #4] if (HAL_TIM_PWM_ConfigChannel (&htim1, &fanTimerConfigOC, TIM_CHANNEL_2) != HAL_OK) { 800452e: 2204 movs r2, #4 8004530: 4924 ldr r1, [pc, #144] @ (80045c4 ) 8004532: 4825 ldr r0, [pc, #148] @ (80045c8 ) 8004534: f009 ffec bl 800e510 8004538: 4603 mov r3, r0 800453a: 2b00 cmp r3, #0 800453c: d001 beq.n 8004542 Error_Handler (); 800453e: f7fd fa6f bl 8001a20 } if (fanTimerPeriod > 0) { 8004542: 6afb ldr r3, [r7, #44] @ 0x2c 8004544: 2b00 cmp r3, #0 8004546: dd41 ble.n 80045cc osTimerStart (fanTimerHandle, fanTimerPeriod * 1000); 8004548: 4b1d ldr r3, [pc, #116] @ (80045c0 ) 800454a: 681a ldr r2, [r3, #0] 800454c: 6afb ldr r3, [r7, #44] @ 0x2c 800454e: f44f 717a mov.w r1, #1000 @ 0x3e8 8004552: fb01 f303 mul.w r3, r1, r3 8004556: 4619 mov r1, r3 8004558: 4610 mov r0, r2 800455a: f00d ffd1 bl 8012500 HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 800455e: 2104 movs r1, #4 8004560: 4819 ldr r0, [pc, #100] @ (80045c8 ) 8004562: f009 fd29 bl 800dfb8 8004566: e046 b.n 80045f6 8004568: 24000c08 .word 0x24000c08 800456c: 2400074c .word 0x2400074c 8004570: 24000758 .word 0x24000758 8004574: 24000b88 .word 0x24000b88 8004578: 24000750 .word 0x24000750 800457c: 24000794 .word 0x24000794 8004580: 24000798 .word 0x24000798 8004584: 2400079c .word 0x2400079c 8004588: 240007a0 .word 0x240007a0 800458c: 240007a4 .word 0x240007a4 8004590: 240007a5 .word 0x240007a5 8004594: 240007a8 .word 0x240007a8 8004598: 240007ac .word 0x240007ac 800459c: 240007b0 .word 0x240007b0 80045a0: 240007b4 .word 0x240007b4 80045a4: 240007b8 .word 0x240007b8 80045a8: 240007b9 .word 0x240007b9 80045ac: 240007ba .word 0x240007ba 80045b0: 240007bb .word 0x240007bb 80045b4: 240007bc .word 0x240007bc 80045b8: 240007bd .word 0x240007bd 80045bc: 240007be .word 0x240007be 80045c0: 24000660 .word 0x24000660 80045c4: 240006f0 .word 0x240006f0 80045c8: 24000420 .word 0x24000420 } else if (fanTimerPeriod == 0) { 80045cc: 6afb ldr r3, [r7, #44] @ 0x2c 80045ce: 2b00 cmp r3, #0 80045d0: d109 bne.n 80045e6 osTimerStop (fanTimerHandle); 80045d2: 4ba7 ldr r3, [pc, #668] @ (8004870 ) 80045d4: 681b ldr r3, [r3, #0] 80045d6: 4618 mov r0, r3 80045d8: f00d ffc0 bl 801255c HAL_TIM_PWM_Stop (&htim1, TIM_CHANNEL_2); 80045dc: 2104 movs r1, #4 80045de: 48a5 ldr r0, [pc, #660] @ (8004874 ) 80045e0: f009 fdf8 bl 800e1d4 80045e4: e007 b.n 80045f6 } else if (fanTimerPeriod == -1) { 80045e6: 6afb ldr r3, [r7, #44] @ 0x2c 80045e8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80045ec: d103 bne.n 80045f6 HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 80045ee: 2104 movs r1, #4 80045f0: 48a0 ldr r0, [pc, #640] @ (8004874 ) 80045f2: f009 fce1 bl 800dfb8 } respStatus = spOK; 80045f6: 2300 movs r3, #0 80045f8: f887 3067 strb.w r3, [r7, #103] @ 0x67 break; 80045fc: e180 b.n 8004900 case spSetMotorXOn: int32_t motorXPWMPulse = 0; 80045fe: 2300 movs r3, #0 8004600: 627b str r3, [r7, #36] @ 0x24 int32_t motorXTimerPeriod = 0; 8004602: 2300 movs r3, #0 8004604: 623b str r3, [r7, #32] uint32_t motorXStatus = 0; 8004606: 2300 movs r3, #0 8004608: 637b str r3, [r7, #52] @ 0x34 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXPWMPulse); 800460a: 683b ldr r3, [r7, #0] 800460c: 330c adds r3, #12 800460e: f107 0224 add.w r2, r7, #36 @ 0x24 8004612: f107 0132 add.w r1, r7, #50 @ 0x32 8004616: 4618 mov r0, r3 8004618: f7fe fb25 bl 8002c66 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXTimerPeriod); 800461c: 683b ldr r3, [r7, #0] 800461e: 330c adds r3, #12 8004620: f107 0220 add.w r2, r7, #32 8004624: f107 0132 add.w r1, r7, #50 @ 0x32 8004628: 4618 mov r0, r3 800462a: f7fe fb1c bl 8002c66 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800462e: 4b92 ldr r3, [pc, #584] @ (8004878 ) 8004630: 681b ldr r3, [r3, #0] 8004632: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004636: 4618 mov r0, r3 8004638: f00e f84d bl 80126d6 800463c: 4603 mov r3, r0 800463e: 2b00 cmp r3, #0 8004640: d12a bne.n 8004698 motorXStatus = motorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, motorXPWMPulse, motorXTimerPeriod, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 8004642: 4b8e ldr r3, [pc, #568] @ (800487c ) 8004644: 681b ldr r3, [r3, #0] 8004646: 6a7a ldr r2, [r7, #36] @ 0x24 8004648: 6a39 ldr r1, [r7, #32] 800464a: 488d ldr r0, [pc, #564] @ (8004880 ) 800464c: f890 0024 ldrb.w r0, [r0, #36] @ 0x24 8004650: 4c8b ldr r4, [pc, #556] @ (8004880 ) 8004652: f894 4025 ldrb.w r4, [r4, #37] @ 0x25 8004656: 9404 str r4, [sp, #16] 8004658: 9003 str r0, [sp, #12] 800465a: 9102 str r1, [sp, #8] 800465c: 9201 str r2, [sp, #4] 800465e: 9300 str r3, [sp, #0] 8004660: 2304 movs r3, #4 8004662: 2200 movs r2, #0 8004664: 4987 ldr r1, [pc, #540] @ (8004884 ) 8004666: 4888 ldr r0, [pc, #544] @ (8004888 ) 8004668: f7fe f926 bl 80028b8 800466c: 4603 mov r3, r0 motorXStatus = 800466e: 637b str r3, [r7, #52] @ 0x34 sensorsInfo.motorXStatus = motorXStatus; 8004670: 6b7b ldr r3, [r7, #52] @ 0x34 8004672: b2da uxtb r2, r3 8004674: 4b82 ldr r3, [pc, #520] @ (8004880 ) 8004676: 741a strb r2, [r3, #16] if (motorXStatus == 1) { 8004678: 6b7b ldr r3, [r7, #52] @ 0x34 800467a: 2b01 cmp r3, #1 800467c: d103 bne.n 8004686 sensorsInfo.motorXPeakCurrent = 0.0; 800467e: 4b80 ldr r3, [pc, #512] @ (8004880 ) 8004680: f04f 0200 mov.w r2, #0 8004684: 61da str r2, [r3, #28] } osMutexRelease (sensorsInfoMutex); 8004686: 4b7c ldr r3, [pc, #496] @ (8004878 ) 8004688: 681b ldr r3, [r3, #0] 800468a: 4618 mov r0, r3 800468c: f00e f86e bl 801276c respStatus = spOK; 8004690: 2300 movs r3, #0 8004692: f887 3067 strb.w r3, [r7, #103] @ 0x67 } else { respStatus = spInternalError; } break; 8004696: e133 b.n 8004900 respStatus = spInternalError; 8004698: 23fc movs r3, #252 @ 0xfc 800469a: f887 3067 strb.w r3, [r7, #103] @ 0x67 break; 800469e: e12f b.n 8004900 case spSetMotorYOn: int32_t motorYPWMPulse = 0; 80046a0: 2300 movs r3, #0 80046a2: 61fb str r3, [r7, #28] int32_t motorYTimerPeriod = 0; 80046a4: 2300 movs r3, #0 80046a6: 61bb str r3, [r7, #24] uint32_t motorYStatus = 0; 80046a8: 2300 movs r3, #0 80046aa: 63bb str r3, [r7, #56] @ 0x38 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYPWMPulse); 80046ac: 683b ldr r3, [r7, #0] 80046ae: 330c adds r3, #12 80046b0: f107 021c add.w r2, r7, #28 80046b4: f107 0132 add.w r1, r7, #50 @ 0x32 80046b8: 4618 mov r0, r3 80046ba: f7fe fad4 bl 8002c66 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYTimerPeriod); 80046be: 683b ldr r3, [r7, #0] 80046c0: 330c adds r3, #12 80046c2: f107 0218 add.w r2, r7, #24 80046c6: f107 0132 add.w r1, r7, #50 @ 0x32 80046ca: 4618 mov r0, r3 80046cc: f7fe facb bl 8002c66 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80046d0: 4b69 ldr r3, [pc, #420] @ (8004878 ) 80046d2: 681b ldr r3, [r3, #0] 80046d4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80046d8: 4618 mov r0, r3 80046da: f00d fffc bl 80126d6 80046de: 4603 mov r3, r0 80046e0: 2b00 cmp r3, #0 80046e2: d12a bne.n 800473a motorYStatus = motorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, motorYPWMPulse, motorYTimerPeriod, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 80046e4: 4b69 ldr r3, [pc, #420] @ (800488c ) 80046e6: 681b ldr r3, [r3, #0] 80046e8: 69fa ldr r2, [r7, #28] 80046ea: 69b9 ldr r1, [r7, #24] 80046ec: 4864 ldr r0, [pc, #400] @ (8004880 ) 80046ee: f890 0027 ldrb.w r0, [r0, #39] @ 0x27 80046f2: 4c63 ldr r4, [pc, #396] @ (8004880 ) 80046f4: f894 4028 ldrb.w r4, [r4, #40] @ 0x28 80046f8: 9404 str r4, [sp, #16] 80046fa: 9003 str r0, [sp, #12] 80046fc: 9102 str r1, [sp, #8] 80046fe: 9201 str r2, [sp, #4] 8004700: 9300 str r3, [sp, #0] 8004702: 230c movs r3, #12 8004704: 2208 movs r2, #8 8004706: 495f ldr r1, [pc, #380] @ (8004884 ) 8004708: 485f ldr r0, [pc, #380] @ (8004888 ) 800470a: f7fe f8d5 bl 80028b8 800470e: 4603 mov r3, r0 motorYStatus = 8004710: 63bb str r3, [r7, #56] @ 0x38 sensorsInfo.motorYStatus = motorYStatus; 8004712: 6bbb ldr r3, [r7, #56] @ 0x38 8004714: b2da uxtb r2, r3 8004716: 4b5a ldr r3, [pc, #360] @ (8004880 ) 8004718: 745a strb r2, [r3, #17] if (motorYStatus == 1) { 800471a: 6bbb ldr r3, [r7, #56] @ 0x38 800471c: 2b01 cmp r3, #1 800471e: d103 bne.n 8004728 sensorsInfo.motorYPeakCurrent = 0.0; 8004720: 4b57 ldr r3, [pc, #348] @ (8004880 ) 8004722: f04f 0200 mov.w r2, #0 8004726: 621a str r2, [r3, #32] } osMutexRelease (sensorsInfoMutex); 8004728: 4b53 ldr r3, [pc, #332] @ (8004878 ) 800472a: 681b ldr r3, [r3, #0] 800472c: 4618 mov r0, r3 800472e: f00e f81d bl 801276c respStatus = spOK; 8004732: 2300 movs r3, #0 8004734: f887 3067 strb.w r3, [r7, #103] @ 0x67 } else { respStatus = spInternalError; } break; 8004738: e0e2 b.n 8004900 respStatus = spInternalError; 800473a: 23fc movs r3, #252 @ 0xfc 800473c: f887 3067 strb.w r3, [r7, #103] @ 0x67 break; 8004740: e0de b.n 8004900 case spSetDiodeOn: osTimerStop (debugLedTimerHandle); 8004742: 4b53 ldr r3, [pc, #332] @ (8004890 ) 8004744: 681b ldr r3, [r3, #0] 8004746: 4618 mov r0, r3 8004748: f00d ff08 bl 801255c int32_t dbgLedTimerPeriod = 0; 800474c: 2300 movs r3, #0 800474e: 617b str r3, [r7, #20] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&dbgLedTimerPeriod); 8004750: 683b ldr r3, [r7, #0] 8004752: 330c adds r3, #12 8004754: f107 0214 add.w r2, r7, #20 8004758: f107 0132 add.w r1, r7, #50 @ 0x32 800475c: 4618 mov r0, r3 800475e: f7fe fa82 bl 8002c66 if (dbgLedTimerPeriod > 0) { 8004762: 697b ldr r3, [r7, #20] 8004764: 2b00 cmp r3, #0 8004766: dd0e ble.n 8004786 osTimerStart (debugLedTimerHandle, dbgLedTimerPeriod * 1000); 8004768: 4b49 ldr r3, [pc, #292] @ (8004890 ) 800476a: 681a ldr r2, [r3, #0] 800476c: 697b ldr r3, [r7, #20] 800476e: f44f 717a mov.w r1, #1000 @ 0x3e8 8004772: fb01 f303 mul.w r3, r1, r3 8004776: 4619 mov r1, r3 8004778: 4610 mov r0, r2 800477a: f00d fec1 bl 8012500 DbgLEDOn (DBG_LED1); 800477e: 2010 movs r0, #16 8004780: f7fe f80c bl 800279c 8004784: e00d b.n 80047a2 } else if (dbgLedTimerPeriod == 0) { 8004786: 697b ldr r3, [r7, #20] 8004788: 2b00 cmp r3, #0 800478a: d103 bne.n 8004794 DbgLEDOff (DBG_LED1); 800478c: 2010 movs r0, #16 800478e: f7fe f817 bl 80027c0 8004792: e006 b.n 80047a2 } else if (dbgLedTimerPeriod == -1) { 8004794: 697b ldr r3, [r7, #20] 8004796: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800479a: d102 bne.n 80047a2 DbgLEDOn (DBG_LED1); 800479c: 2010 movs r0, #16 800479e: f7fd fffd bl 800279c } respStatus = spOK; 80047a2: 2300 movs r3, #0 80047a4: f887 3067 strb.w r3, [r7, #103] @ 0x67 break; 80047a8: e0aa b.n 8004900 case spSetmotorXMaxCurrent: float motorXMaxCurrent = 0; 80047aa: f04f 0300 mov.w r3, #0 80047ae: 613b str r3, [r7, #16] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXMaxCurrent); 80047b0: 683b ldr r3, [r7, #0] 80047b2: 330c adds r3, #12 80047b4: f107 0210 add.w r2, r7, #16 80047b8: f107 0132 add.w r1, r7, #50 @ 0x32 80047bc: 4618 mov r0, r3 80047be: f7fe fa52 bl 8002c66 uint32_t dacDataCh1 = (uint32_t)(4095 * motorXMaxCurrent / (EXT_VREF_mV * 0.001)); 80047c2: edd7 7a04 vldr s15, [r7, #16] 80047c6: ed9f 7a33 vldr s14, [pc, #204] @ 8004894 80047ca: ee67 7a87 vmul.f32 s15, s15, s14 80047ce: eeb7 6ae7 vcvt.f64.f32 d6, s15 80047d2: eeb0 5b08 vmov.f64 d5, #8 @ 0x40400000 3.0 80047d6: ee86 7b05 vdiv.f64 d7, d6, d5 80047da: eefc 7bc7 vcvt.u32.f64 s15, d7 80047de: ee17 3a90 vmov r3, s15 80047e2: 63fb str r3, [r7, #60] @ 0x3c HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, dacDataCh1); 80047e4: 6bfb ldr r3, [r7, #60] @ 0x3c 80047e6: 2200 movs r2, #0 80047e8: 2100 movs r1, #0 80047ea: 482b ldr r0, [pc, #172] @ (8004898 ) 80047ec: f002 f9c3 bl 8006b76 HAL_DAC_Start (&hdac1, DAC_CHANNEL_1); 80047f0: 2100 movs r1, #0 80047f2: 4829 ldr r0, [pc, #164] @ (8004898 ) 80047f4: f002 f912 bl 8006a1c respStatus = spOK; 80047f8: 2300 movs r3, #0 80047fa: f887 3067 strb.w r3, [r7, #103] @ 0x67 break; 80047fe: e07f b.n 8004900 case spSetmotorYMaxCurrent: float motorYMaxCurrent = 0; 8004800: f04f 0300 mov.w r3, #0 8004804: 60fb str r3, [r7, #12] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYMaxCurrent); 8004806: 683b ldr r3, [r7, #0] 8004808: 330c adds r3, #12 800480a: f107 020c add.w r2, r7, #12 800480e: f107 0132 add.w r1, r7, #50 @ 0x32 8004812: 4618 mov r0, r3 8004814: f7fe fa27 bl 8002c66 uint32_t dacDataCh2 = (uint32_t)(4095 * motorYMaxCurrent / (EXT_VREF_mV * 0.001)); 8004818: edd7 7a03 vldr s15, [r7, #12] 800481c: ed9f 7a1d vldr s14, [pc, #116] @ 8004894 8004820: ee67 7a87 vmul.f32 s15, s15, s14 8004824: eeb7 6ae7 vcvt.f64.f32 d6, s15 8004828: eeb0 5b08 vmov.f64 d5, #8 @ 0x40400000 3.0 800482c: ee86 7b05 vdiv.f64 d7, d6, d5 8004830: eefc 7bc7 vcvt.u32.f64 s15, d7 8004834: ee17 3a90 vmov r3, s15 8004838: 643b str r3, [r7, #64] @ 0x40 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, dacDataCh2); 800483a: 6c3b ldr r3, [r7, #64] @ 0x40 800483c: 2200 movs r2, #0 800483e: 2110 movs r1, #16 8004840: 4815 ldr r0, [pc, #84] @ (8004898 ) 8004842: f002 f998 bl 8006b76 HAL_DAC_Start (&hdac1, DAC_CHANNEL_2); 8004846: 2110 movs r1, #16 8004848: 4813 ldr r0, [pc, #76] @ (8004898 ) 800484a: f002 f8e7 bl 8006a1c respStatus = spOK; 800484e: 2300 movs r3, #0 8004850: f887 3067 strb.w r3, [r7, #103] @ 0x67 break; 8004854: e054 b.n 8004900 case spClearPeakMeasurments: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8004856: 4b11 ldr r3, [pc, #68] @ (800489c ) 8004858: 681b ldr r3, [r3, #0] 800485a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800485e: 4618 mov r0, r3 8004860: f00d ff39 bl 80126d6 8004864: 4603 mov r3, r0 8004866: 2b00 cmp r3, #0 8004868: d142 bne.n 80048f0 for (int i = 0; i < 3; i++) { 800486a: 2300 movs r3, #0 800486c: 64fb str r3, [r7, #76] @ 0x4c 800486e: e033 b.n 80048d8 8004870: 24000660 .word 0x24000660 8004874: 24000420 .word 0x24000420 8004878: 24000750 .word 0x24000750 800487c: 24000690 .word 0x24000690 8004880: 24000794 .word 0x24000794 8004884: 2400070c .word 0x2400070c 8004888: 240004b8 .word 0x240004b8 800488c: 240006c0 .word 0x240006c0 8004890: 24000630 .word 0x24000630 8004894: 457ff000 .word 0x457ff000 8004898: 240003f8 .word 0x240003f8 800489c: 2400074c .word 0x2400074c resMeasurements.voltagePeak[i] = resMeasurements.voltageRMS[i]; 80048a0: 4a2e ldr r2, [pc, #184] @ (800495c ) 80048a2: 6cfb ldr r3, [r7, #76] @ 0x4c 80048a4: 009b lsls r3, r3, #2 80048a6: 4413 add r3, r2 80048a8: 681a ldr r2, [r3, #0] 80048aa: 492c ldr r1, [pc, #176] @ (800495c ) 80048ac: 6cfb ldr r3, [r7, #76] @ 0x4c 80048ae: 3302 adds r3, #2 80048b0: 009b lsls r3, r3, #2 80048b2: 440b add r3, r1 80048b4: 3304 adds r3, #4 80048b6: 601a str r2, [r3, #0] resMeasurements.currentPeak[i] = resMeasurements.currentRMS[i]; 80048b8: 4a28 ldr r2, [pc, #160] @ (800495c ) 80048ba: 6cfb ldr r3, [r7, #76] @ 0x4c 80048bc: 3306 adds r3, #6 80048be: 009b lsls r3, r3, #2 80048c0: 4413 add r3, r2 80048c2: 681a ldr r2, [r3, #0] 80048c4: 4925 ldr r1, [pc, #148] @ (800495c ) 80048c6: 6cfb ldr r3, [r7, #76] @ 0x4c 80048c8: 3308 adds r3, #8 80048ca: 009b lsls r3, r3, #2 80048cc: 440b add r3, r1 80048ce: 3304 adds r3, #4 80048d0: 601a str r2, [r3, #0] for (int i = 0; i < 3; i++) { 80048d2: 6cfb ldr r3, [r7, #76] @ 0x4c 80048d4: 3301 adds r3, #1 80048d6: 64fb str r3, [r7, #76] @ 0x4c 80048d8: 6cfb ldr r3, [r7, #76] @ 0x4c 80048da: 2b02 cmp r3, #2 80048dc: dde0 ble.n 80048a0 } osMutexRelease (resMeasurementsMutex); 80048de: 4b20 ldr r3, [pc, #128] @ (8004960 ) 80048e0: 681b ldr r3, [r3, #0] 80048e2: 4618 mov r0, r3 80048e4: f00d ff42 bl 801276c respStatus = spOK; 80048e8: 2300 movs r3, #0 80048ea: f887 3067 strb.w r3, [r7, #103] @ 0x67 } else { respStatus = spInternalError; } break; 80048ee: e007 b.n 8004900 respStatus = spInternalError; 80048f0: 23fc movs r3, #252 @ 0xfc 80048f2: f887 3067 strb.w r3, [r7, #103] @ 0x67 break; 80048f6: e003 b.n 8004900 default: respStatus = spUnknownCommand; break; 80048f8: 23fd movs r3, #253 @ 0xfd 80048fa: f887 3067 strb.w r3, [r7, #103] @ 0x67 80048fe: bf00 nop } dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8004900: 6cbb ldr r3, [r7, #72] @ 0x48 8004902: 6898 ldr r0, [r3, #8] 8004904: 683b ldr r3, [r7, #0] 8004906: 8819 ldrh r1, [r3, #0] 8004908: 683b ldr r3, [r7, #0] 800490a: 789a ldrb r2, [r3, #2] 800490c: 4b15 ldr r3, [pc, #84] @ (8004964 ) 800490e: 881b ldrh r3, [r3, #0] 8004910: f997 4067 ldrsb.w r4, [r7, #103] @ 0x67 8004914: 9301 str r3, [sp, #4] 8004916: 4b14 ldr r3, [pc, #80] @ (8004968 ) 8004918: 9300 str r3, [sp, #0] 800491a: 4623 mov r3, r4 800491c: f7fe f9d6 bl 8002ccc 8004920: 4603 mov r3, r0 8004922: f8a7 3046 strh.w r3, [r7, #70] @ 0x46 if (dataToSend > 0) { 8004926: f8b7 3046 ldrh.w r3, [r7, #70] @ 0x46 800492a: 2b00 cmp r3, #0 800492c: d008 beq.n 8004940 HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 800492e: 6cbb ldr r3, [r7, #72] @ 0x48 8004930: 6b18 ldr r0, [r3, #48] @ 0x30 8004932: 6cbb ldr r3, [r7, #72] @ 0x48 8004934: 689b ldr r3, [r3, #8] 8004936: f8b7 2046 ldrh.w r2, [r7, #70] @ 0x46 800493a: 4619 mov r1, r3 800493c: f00a fe9e bl 800f67c } #if UART_TASK_LOGS printf ("Uart%d: TX bytes sent: %d\n", uartTaskData->uartNumber, dataToSend); 8004940: 6cbb ldr r3, [r7, #72] @ 0x48 8004942: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8004946: 4619 mov r1, r3 8004948: f8b7 3046 ldrh.w r3, [r7, #70] @ 0x46 800494c: 461a mov r2, r3 800494e: 4807 ldr r0, [pc, #28] @ (800496c ) 8004950: f011 feac bl 80166ac #endif } 8004954: bf00 nop 8004956: 376c adds r7, #108 @ 0x6c 8004958: 46bd mov sp, r7 800495a: bd90 pop {r4, r7, pc} 800495c: 24000758 .word 0x24000758 8004960: 2400074c .word 0x2400074c 8004964: 24000c08 .word 0x24000c08 8004968: 24000b88 .word 0x24000b88 800496c: 08017530 .word 0x08017530 08004970 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8004970: f8df d034 ldr.w sp, [pc, #52] @ 80049a8 /* Call the clock system initialization function.*/ bl SystemInit 8004974: f7ff f858 bl 8003a28 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8004978: 480c ldr r0, [pc, #48] @ (80049ac ) ldr r1, =_edata 800497a: 490d ldr r1, [pc, #52] @ (80049b0 ) ldr r2, =_sidata 800497c: 4a0d ldr r2, [pc, #52] @ (80049b4 ) movs r3, #0 800497e: 2300 movs r3, #0 b LoopCopyDataInit 8004980: e002 b.n 8004988 08004982 : CopyDataInit: ldr r4, [r2, r3] 8004982: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8004984: 50c4 str r4, [r0, r3] adds r3, r3, #4 8004986: 3304 adds r3, #4 08004988 : LoopCopyDataInit: adds r4, r0, r3 8004988: 18c4 adds r4, r0, r3 cmp r4, r1 800498a: 428c cmp r4, r1 bcc CopyDataInit 800498c: d3f9 bcc.n 8004982 /* Zero fill the bss segment. */ ldr r2, =_sbss 800498e: 4a0a ldr r2, [pc, #40] @ (80049b8 ) ldr r4, =_ebss 8004990: 4c0a ldr r4, [pc, #40] @ (80049bc ) movs r3, #0 8004992: 2300 movs r3, #0 b LoopFillZerobss 8004994: e001 b.n 800499a 08004996 : FillZerobss: str r3, [r2] 8004996: 6013 str r3, [r2, #0] adds r2, r2, #4 8004998: 3204 adds r2, #4 0800499a : LoopFillZerobss: cmp r2, r4 800499a: 42a2 cmp r2, r4 bcc FillZerobss 800499c: d3fb bcc.n 8004996 /* Call static constructors */ bl __libc_init_array 800499e: f011 ff85 bl 80168ac <__libc_init_array> /* Call the application's entry point.*/ bl main 80049a2: f7fb fea3 bl 80006ec
bx lr 80049a6: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 80049a8: 24060000 .word 0x24060000 ldr r0, =_sdata 80049ac: 24000000 .word 0x24000000 ldr r1, =_edata 80049b0: 240000a4 .word 0x240000a4 ldr r2, =_sidata 80049b4: 0801764c .word 0x0801764c ldr r2, =_sbss 80049b8: 240000c0 .word 0x240000c0 ldr r4, =_ebss 80049bc: 24012d44 .word 0x24012d44 080049c0 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80049c0: e7fe b.n 80049c0 ... 080049c4 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80049c4: b580 push {r7, lr} 80049c6: b082 sub sp, #8 80049c8: af00 add r7, sp, #0 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ #endif /* DUAL_CORE && CORE_CM4 */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80049ca: 2003 movs r0, #3 80049cc: f001 fd53 bl 8006476 /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 80049d0: f006 f9fe bl 800add0 80049d4: 4602 mov r2, r0 80049d6: 4b15 ldr r3, [pc, #84] @ (8004a2c ) 80049d8: 699b ldr r3, [r3, #24] 80049da: 0a1b lsrs r3, r3, #8 80049dc: f003 030f and.w r3, r3, #15 80049e0: 4913 ldr r1, [pc, #76] @ (8004a30 ) 80049e2: 5ccb ldrb r3, [r1, r3] 80049e4: f003 031f and.w r3, r3, #31 80049e8: fa22 f303 lsr.w r3, r2, r3 80049ec: 607b str r3, [r7, #4] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 80049ee: 4b0f ldr r3, [pc, #60] @ (8004a2c ) 80049f0: 699b ldr r3, [r3, #24] 80049f2: f003 030f and.w r3, r3, #15 80049f6: 4a0e ldr r2, [pc, #56] @ (8004a30 ) 80049f8: 5cd3 ldrb r3, [r2, r3] 80049fa: f003 031f and.w r3, r3, #31 80049fe: 687a ldr r2, [r7, #4] 8004a00: fa22 f303 lsr.w r3, r2, r3 8004a04: 4a0b ldr r2, [pc, #44] @ (8004a34 ) 8004a06: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8004a08: 4a0b ldr r2, [pc, #44] @ (8004a38 ) 8004a0a: 687b ldr r3, [r7, #4] 8004a0c: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8004a0e: 2005 movs r0, #5 8004a10: f7fe fe68 bl 80036e4 8004a14: 4603 mov r3, r0 8004a16: 2b00 cmp r3, #0 8004a18: d001 beq.n 8004a1e { return HAL_ERROR; 8004a1a: 2301 movs r3, #1 8004a1c: e002 b.n 8004a24 } /* Init the low level hardware */ HAL_MspInit(); 8004a1e: f7fe f9f3 bl 8002e08 /* Return function status */ return HAL_OK; 8004a22: 2300 movs r3, #0 } 8004a24: 4618 mov r0, r3 8004a26: 3708 adds r7, #8 8004a28: 46bd mov sp, r7 8004a2a: bd80 pop {r7, pc} 8004a2c: 58024400 .word 0x58024400 8004a30: 080175c8 .word 0x080175c8 8004a34: 24000038 .word 0x24000038 8004a38: 24000034 .word 0x24000034 08004a3c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8004a3c: b480 push {r7} 8004a3e: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 8004a40: 4b06 ldr r3, [pc, #24] @ (8004a5c ) 8004a42: 781b ldrb r3, [r3, #0] 8004a44: 461a mov r2, r3 8004a46: 4b06 ldr r3, [pc, #24] @ (8004a60 ) 8004a48: 681b ldr r3, [r3, #0] 8004a4a: 4413 add r3, r2 8004a4c: 4a04 ldr r2, [pc, #16] @ (8004a60 ) 8004a4e: 6013 str r3, [r2, #0] } 8004a50: bf00 nop 8004a52: 46bd mov sp, r7 8004a54: f85d 7b04 ldr.w r7, [sp], #4 8004a58: 4770 bx lr 8004a5a: bf00 nop 8004a5c: 24000040 .word 0x24000040 8004a60: 24000c0c .word 0x24000c0c 08004a64 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8004a64: b480 push {r7} 8004a66: af00 add r7, sp, #0 return uwTick; 8004a68: 4b03 ldr r3, [pc, #12] @ (8004a78 ) 8004a6a: 681b ldr r3, [r3, #0] } 8004a6c: 4618 mov r0, r3 8004a6e: 46bd mov sp, r7 8004a70: f85d 7b04 ldr.w r7, [sp], #4 8004a74: 4770 bx lr 8004a76: bf00 nop 8004a78: 24000c0c .word 0x24000c0c 08004a7c : /** * @brief Returns the device revision identifier. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { 8004a7c: b480 push {r7} 8004a7e: af00 add r7, sp, #0 return((DBGMCU->IDCODE) >> 16); 8004a80: 4b03 ldr r3, [pc, #12] @ (8004a90 ) 8004a82: 681b ldr r3, [r3, #0] 8004a84: 0c1b lsrs r3, r3, #16 } 8004a86: 4618 mov r0, r3 8004a88: 46bd mov sp, r7 8004a8a: f85d 7b04 ldr.w r7, [sp], #4 8004a8e: 4770 bx lr 8004a90: 5c001000 .word 0x5c001000 08004a94 : * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. * @retval None */ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) { 8004a94: b480 push {r7} 8004a96: b083 sub sp, #12 8004a98: af00 add r7, sp, #0 8004a9a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); 8004a9c: 4b06 ldr r3, [pc, #24] @ (8004ab8 ) 8004a9e: 681b ldr r3, [r3, #0] 8004aa0: f023 0202 bic.w r2, r3, #2 8004aa4: 4904 ldr r1, [pc, #16] @ (8004ab8 ) 8004aa6: 687b ldr r3, [r7, #4] 8004aa8: 4313 orrs r3, r2 8004aaa: 600b str r3, [r1, #0] } 8004aac: bf00 nop 8004aae: 370c adds r7, #12 8004ab0: 46bd mov sp, r7 8004ab2: f85d 7b04 ldr.w r7, [sp], #4 8004ab6: 4770 bx lr 8004ab8: 58003c00 .word 0x58003c00 08004abc : * @brief Disable the Internal Voltage Reference buffer (VREFBUF). * * @retval None */ void HAL_SYSCFG_DisableVREFBUF(void) { 8004abc: b480 push {r7} 8004abe: af00 add r7, sp, #0 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); 8004ac0: 4b05 ldr r3, [pc, #20] @ (8004ad8 ) 8004ac2: 681b ldr r3, [r3, #0] 8004ac4: 4a04 ldr r2, [pc, #16] @ (8004ad8 ) 8004ac6: f023 0301 bic.w r3, r3, #1 8004aca: 6013 str r3, [r2, #0] } 8004acc: bf00 nop 8004ace: 46bd mov sp, r7 8004ad0: f85d 7b04 ldr.w r7, [sp], #4 8004ad4: 4770 bx lr 8004ad6: bf00 nop 8004ad8: 58003c00 .word 0x58003c00 08004adc : * @arg SYSCFG_SWITCH_PC3_CLOSE * @retval None */ void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ) { 8004adc: b480 push {r7} 8004ade: b083 sub sp, #12 8004ae0: af00 add r7, sp, #0 8004ae2: 6078 str r0, [r7, #4] 8004ae4: 6039 str r1, [r7, #0] /* Check the parameter */ assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch)); assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState)); MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState)); 8004ae6: 4b07 ldr r3, [pc, #28] @ (8004b04 ) 8004ae8: 685a ldr r2, [r3, #4] 8004aea: 687b ldr r3, [r7, #4] 8004aec: 43db mvns r3, r3 8004aee: 401a ands r2, r3 8004af0: 4904 ldr r1, [pc, #16] @ (8004b04 ) 8004af2: 683b ldr r3, [r7, #0] 8004af4: 4313 orrs r3, r2 8004af6: 604b str r3, [r1, #4] } 8004af8: bf00 nop 8004afa: 370c adds r7, #12 8004afc: 46bd mov sp, r7 8004afe: f85d 7b04 ldr.w r7, [sp], #4 8004b02: 4770 bx lr 8004b04: 58000400 .word 0x58000400 08004b08 : * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) { 8004b08: b480 push {r7} 8004b0a: b083 sub sp, #12 8004b0c: af00 add r7, sp, #0 8004b0e: 6078 str r0, [r7, #4] 8004b10: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); 8004b12: 687b ldr r3, [r7, #4] 8004b14: 689b ldr r3, [r3, #8] 8004b16: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000 8004b1a: 683b ldr r3, [r7, #0] 8004b1c: 431a orrs r2, r3 8004b1e: 687b ldr r3, [r7, #4] 8004b20: 609a str r2, [r3, #8] } 8004b22: bf00 nop 8004b24: 370c adds r7, #12 8004b26: 46bd mov sp, r7 8004b28: f85d 7b04 ldr.w r7, [sp], #4 8004b2c: 4770 bx lr 08004b2e : * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { 8004b2e: b480 push {r7} 8004b30: b083 sub sp, #12 8004b32: af00 add r7, sp, #0 8004b34: 6078 str r0, [r7, #4] 8004b36: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); 8004b38: 687b ldr r3, [r7, #4] 8004b3a: 689b ldr r3, [r3, #8] 8004b3c: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000 8004b40: 683b ldr r3, [r7, #0] 8004b42: 431a orrs r2, r3 8004b44: 687b ldr r3, [r7, #4] 8004b46: 609a str r2, [r3, #8] } 8004b48: bf00 nop 8004b4a: 370c adds r7, #12 8004b4c: 46bd mov sp, r7 8004b4e: f85d 7b04 ldr.w r7, [sp], #4 8004b52: 4770 bx lr 08004b54 : * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) { 8004b54: b480 push {r7} 8004b56: b083 sub sp, #12 8004b58: af00 add r7, sp, #0 8004b5a: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 8004b5c: 687b ldr r3, [r7, #4] 8004b5e: 689b ldr r3, [r3, #8] 8004b60: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000 } 8004b64: 4618 mov r0, r3 8004b66: 370c adds r7, #12 8004b68: 46bd mov sp, r7 8004b6a: f85d 7b04 ldr.w r7, [sp], #4 8004b6e: 4770 bx lr 08004b70 : * Other channels are slow channels (conversion rate: refer to reference manual). * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x3FFFFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { 8004b70: b480 push {r7} 8004b72: b087 sub sp, #28 8004b74: af00 add r7, sp, #0 8004b76: 60f8 str r0, [r7, #12] 8004b78: 60b9 str r1, [r7, #8] 8004b7a: 607a str r2, [r7, #4] 8004b7c: 603b str r3, [r7, #0] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8004b7e: 68fb ldr r3, [r7, #12] 8004b80: 3360 adds r3, #96 @ 0x60 8004b82: 461a mov r2, r3 8004b84: 68bb ldr r3, [r7, #8] 8004b86: 009b lsls r3, r3, #2 8004b88: 4413 add r3, r2 8004b8a: 617b str r3, [r7, #20] ADC3_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } else #endif /* ADC_VER_V5_V90 */ { MODIFY_REG(*preg, 8004b8c: 697b ldr r3, [r7, #20] 8004b8e: 681b ldr r3, [r3, #0] 8004b90: f003 4200 and.w r2, r3, #2147483648 @ 0x80000000 8004b94: 687b ldr r3, [r7, #4] 8004b96: f003 41f8 and.w r1, r3, #2080374784 @ 0x7c000000 8004b9a: 683b ldr r3, [r7, #0] 8004b9c: 430b orrs r3, r1 8004b9e: 431a orrs r2, r3 8004ba0: 697b ldr r3, [r7, #20] 8004ba2: 601a str r2, [r3, #0] ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } } 8004ba4: bf00 nop 8004ba6: 371c adds r7, #28 8004ba8: 46bd mov sp, r7 8004baa: f85d 7b04 ldr.w r7, [sp], #4 8004bae: 4770 bx lr 08004bb0 : * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift) { 8004bb0: b480 push {r7} 8004bb2: b085 sub sp, #20 8004bb4: af00 add r7, sp, #0 8004bb6: 60f8 str r0, [r7, #12] 8004bb8: 60b9 str r1, [r7, #8] 8004bba: 607a str r2, [r7, #4] MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL)); 8004bbc: 68fb ldr r3, [r7, #12] 8004bbe: 691b ldr r3, [r3, #16] 8004bc0: f423 42f0 bic.w r2, r3, #30720 @ 0x7800 8004bc4: 68bb ldr r3, [r7, #8] 8004bc6: f003 031f and.w r3, r3, #31 8004bca: 6879 ldr r1, [r7, #4] 8004bcc: fa01 f303 lsl.w r3, r1, r3 8004bd0: 431a orrs r2, r3 8004bd2: 68fb ldr r3, [r7, #12] 8004bd4: 611a str r2, [r3, #16] } 8004bd6: bf00 nop 8004bd8: 3714 adds r7, #20 8004bda: 46bd mov sp, r7 8004bdc: f85d 7b04 ldr.w r7, [sp], #4 8004be0: 4770 bx lr 08004be2 : * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation) { 8004be2: b480 push {r7} 8004be4: b087 sub sp, #28 8004be6: af00 add r7, sp, #0 8004be8: 60f8 str r0, [r7, #12] 8004bea: 60b9 str r1, [r7, #8] 8004bec: 607a str r2, [r7, #4] /* Function not available on this instance */ } else #endif /* ADC_VER_V5_V90 */ { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8004bee: 68fb ldr r3, [r7, #12] 8004bf0: 3360 adds r3, #96 @ 0x60 8004bf2: 461a mov r2, r3 8004bf4: 68bb ldr r3, [r7, #8] 8004bf6: 009b lsls r3, r3, #2 8004bf8: 4413 add r3, r2 8004bfa: 617b str r3, [r7, #20] MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation); 8004bfc: 697b ldr r3, [r7, #20] 8004bfe: 681b ldr r3, [r3, #0] 8004c00: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 8004c04: 687b ldr r3, [r7, #4] 8004c06: 431a orrs r2, r3 8004c08: 697b ldr r3, [r7, #20] 8004c0a: 601a str r2, [r3, #0] } } 8004c0c: bf00 nop 8004c0e: 371c adds r7, #28 8004c10: 46bd mov sp, r7 8004c12: f85d 7b04 ldr.w r7, [sp], #4 8004c16: 4770 bx lr 08004c18 : * @param ADCx ADC instance * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { 8004c18: b480 push {r7} 8004c1a: b083 sub sp, #12 8004c1c: af00 add r7, sp, #0 8004c1e: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); 8004c20: 687b ldr r3, [r7, #4] 8004c22: 68db ldr r3, [r3, #12] 8004c24: f403 6340 and.w r3, r3, #3072 @ 0xc00 8004c28: 2b00 cmp r3, #0 8004c2a: d101 bne.n 8004c30 8004c2c: 2301 movs r3, #1 8004c2e: e000 b.n 8004c32 8004c30: 2300 movs r3, #0 } 8004c32: 4618 mov r0, r3 8004c34: 370c adds r7, #12 8004c36: 46bd mov sp, r7 8004c38: f85d 7b04 ldr.w r7, [sp], #4 8004c3c: 4770 bx lr 08004c3e : * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { 8004c3e: b480 push {r7} 8004c40: b087 sub sp, #28 8004c42: af00 add r7, sp, #0 8004c44: 60f8 str r0, [r7, #12] 8004c46: 60b9 str r1, [r7, #8] 8004c48: 607a str r2, [r7, #4] /* Set bits with content of parameter "Channel" with bits position */ /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); 8004c4a: 68fb ldr r3, [r7, #12] 8004c4c: 3330 adds r3, #48 @ 0x30 8004c4e: 461a mov r2, r3 8004c50: 68bb ldr r3, [r7, #8] 8004c52: 0a1b lsrs r3, r3, #8 8004c54: 009b lsls r3, r3, #2 8004c56: f003 030c and.w r3, r3, #12 8004c5a: 4413 add r3, r2 8004c5c: 617b str r3, [r7, #20] MODIFY_REG(*preg, 8004c5e: 697b ldr r3, [r7, #20] 8004c60: 681a ldr r2, [r3, #0] 8004c62: 68bb ldr r3, [r7, #8] 8004c64: f003 031f and.w r3, r3, #31 8004c68: 211f movs r1, #31 8004c6a: fa01 f303 lsl.w r3, r1, r3 8004c6e: 43db mvns r3, r3 8004c70: 401a ands r2, r3 8004c72: 687b ldr r3, [r7, #4] 8004c74: 0e9b lsrs r3, r3, #26 8004c76: f003 011f and.w r1, r3, #31 8004c7a: 68bb ldr r3, [r7, #8] 8004c7c: f003 031f and.w r3, r3, #31 8004c80: fa01 f303 lsl.w r3, r1, r3 8004c84: 431a orrs r2, r3 8004c86: 697b ldr r3, [r7, #20] 8004c88: 601a str r2, [r3, #0] ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } 8004c8a: bf00 nop 8004c8c: 371c adds r7, #28 8004c8e: 46bd mov sp, r7 8004c90: f85d 7b04 ldr.w r7, [sp], #4 8004c94: 4770 bx lr 08004c96 : * @param ADCx ADC instance * @param DataTransferMode Select Data Management configuration * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode) { 8004c96: b480 push {r7} 8004c98: b083 sub sp, #12 8004c9a: af00 add r7, sp, #0 8004c9c: 6078 str r0, [r7, #4] 8004c9e: 6039 str r1, [r7, #0] MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode); 8004ca0: 687b ldr r3, [r7, #4] 8004ca2: 68db ldr r3, [r3, #12] 8004ca4: f023 0203 bic.w r2, r3, #3 8004ca8: 683b ldr r3, [r7, #0] 8004caa: 431a orrs r2, r3 8004cac: 687b ldr r3, [r7, #4] 8004cae: 60da str r2, [r3, #12] } 8004cb0: bf00 nop 8004cb2: 370c adds r7, #12 8004cb4: 46bd mov sp, r7 8004cb6: f85d 7b04 ldr.w r7, [sp], #4 8004cba: 4770 bx lr 08004cbc : * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5 * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) { 8004cbc: b480 push {r7} 8004cbe: b087 sub sp, #28 8004cc0: af00 add r7, sp, #0 8004cc2: 60f8 str r0, [r7, #12] 8004cc4: 60b9 str r1, [r7, #8] 8004cc6: 607a str r2, [r7, #4] /* Set bits with content of parameter "SamplingTime" with bits position */ /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 8004cc8: 68fb ldr r3, [r7, #12] 8004cca: 3314 adds r3, #20 8004ccc: 461a mov r2, r3 8004cce: 68bb ldr r3, [r7, #8] 8004cd0: 0e5b lsrs r3, r3, #25 8004cd2: 009b lsls r3, r3, #2 8004cd4: f003 0304 and.w r3, r3, #4 8004cd8: 4413 add r3, r2 8004cda: 617b str r3, [r7, #20] MODIFY_REG(*preg, 8004cdc: 697b ldr r3, [r7, #20] 8004cde: 681a ldr r2, [r3, #0] 8004ce0: 68bb ldr r3, [r7, #8] 8004ce2: 0d1b lsrs r3, r3, #20 8004ce4: f003 031f and.w r3, r3, #31 8004ce8: 2107 movs r1, #7 8004cea: fa01 f303 lsl.w r3, r1, r3 8004cee: 43db mvns r3, r3 8004cf0: 401a ands r2, r3 8004cf2: 68bb ldr r3, [r7, #8] 8004cf4: 0d1b lsrs r3, r3, #20 8004cf6: f003 031f and.w r3, r3, #31 8004cfa: 6879 ldr r1, [r7, #4] 8004cfc: fa01 f303 lsl.w r3, r1, r3 8004d00: 431a orrs r2, r3 8004d02: 697b ldr r3, [r7, #20] 8004d04: 601a str r2, [r3, #0] ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); } 8004d06: bf00 nop 8004d08: 371c adds r7, #28 8004d0a: 46bd mov sp, r7 8004d0c: f85d 7b04 ldr.w r7, [sp], #4 8004d10: 4770 bx lr ... 08004d14 : * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) { 8004d14: b480 push {r7} 8004d16: b085 sub sp, #20 8004d18: af00 add r7, sp, #0 8004d1a: 60f8 str r0, [r7, #12] 8004d1c: 60b9 str r1, [r7, #8] 8004d1e: 607a str r2, [r7, #4] } #else /* ADC_VER_V5_V90 */ /* Bits of channels in single or differential mode are set only for */ /* differential mode (for single mode, mask of bits allowed to be set is */ /* shifted out of range of bits of channels in single or differential mode. */ MODIFY_REG(ADCx->DIFSEL, 8004d20: 68fb ldr r3, [r7, #12] 8004d22: f8d3 20c0 ldr.w r2, [r3, #192] @ 0xc0 8004d26: 68bb ldr r3, [r7, #8] 8004d28: f3c3 0313 ubfx r3, r3, #0, #20 8004d2c: 43db mvns r3, r3 8004d2e: 401a ands r2, r3 8004d30: 687b ldr r3, [r7, #4] 8004d32: f003 0318 and.w r3, r3, #24 8004d36: 4908 ldr r1, [pc, #32] @ (8004d58 ) 8004d38: 40d9 lsrs r1, r3 8004d3a: 68bb ldr r3, [r7, #8] 8004d3c: 400b ands r3, r1 8004d3e: f3c3 0313 ubfx r3, r3, #0, #20 8004d42: 431a orrs r2, r3 8004d44: 68fb ldr r3, [r7, #12] 8004d46: f8c3 20c0 str.w r2, [r3, #192] @ 0xc0 Channel & ADC_SINGLEDIFF_CHANNEL_MASK, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); #endif /* ADC_VER_V5_V90 */ } 8004d4a: bf00 nop 8004d4c: 3714 adds r7, #20 8004d4e: 46bd mov sp, r7 8004d50: f85d 7b04 ldr.w r7, [sp], #4 8004d54: 4770 bx lr 8004d56: bf00 nop 8004d58: 000fffff .word 0x000fffff 08004d5c : * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) { 8004d5c: b480 push {r7} 8004d5e: b083 sub sp, #12 8004d60: af00 add r7, sp, #0 8004d62: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 8004d64: 687b ldr r3, [r7, #4] 8004d66: 689b ldr r3, [r3, #8] 8004d68: f003 031f and.w r3, r3, #31 } 8004d6c: 4618 mov r0, r3 8004d6e: 370c adds r7, #12 8004d70: 46bd mov sp, r7 8004d72: f85d 7b04 ldr.w r7, [sp], #4 8004d76: 4770 bx lr 08004d78 : * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) { 8004d78: b480 push {r7} 8004d7a: b083 sub sp, #12 8004d7c: af00 add r7, sp, #0 8004d7e: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); 8004d80: 687b ldr r3, [r7, #4] 8004d82: 689a ldr r2, [r3, #8] 8004d84: 4b04 ldr r3, [pc, #16] @ (8004d98 ) 8004d86: 4013 ands r3, r2 8004d88: 687a ldr r2, [r7, #4] 8004d8a: 6093 str r3, [r2, #8] } 8004d8c: bf00 nop 8004d8e: 370c adds r7, #12 8004d90: 46bd mov sp, r7 8004d92: f85d 7b04 ldr.w r7, [sp], #4 8004d96: 4770 bx lr 8004d98: 5fffffc0 .word 0x5fffffc0 08004d9c : * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) { 8004d9c: b480 push {r7} 8004d9e: b083 sub sp, #12 8004da0: af00 add r7, sp, #0 8004da2: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); 8004da4: 687b ldr r3, [r7, #4] 8004da6: 689b ldr r3, [r3, #8] 8004da8: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004dac: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004db0: d101 bne.n 8004db6 8004db2: 2301 movs r3, #1 8004db4: e000 b.n 8004db8 8004db6: 2300 movs r3, #0 } 8004db8: 4618 mov r0, r3 8004dba: 370c adds r7, #12 8004dbc: 46bd mov sp, r7 8004dbe: f85d 7b04 ldr.w r7, [sp], #4 8004dc2: 4770 bx lr 08004dc4 : * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) { 8004dc4: b480 push {r7} 8004dc6: b083 sub sp, #12 8004dc8: af00 add r7, sp, #0 8004dca: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8004dcc: 687b ldr r3, [r7, #4] 8004dce: 689a ldr r2, [r3, #8] 8004dd0: 4b05 ldr r3, [pc, #20] @ (8004de8 ) 8004dd2: 4013 ands r3, r2 8004dd4: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000 8004dd8: 687b ldr r3, [r7, #4] 8004dda: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); } 8004ddc: bf00 nop 8004dde: 370c adds r7, #12 8004de0: 46bd mov sp, r7 8004de2: f85d 7b04 ldr.w r7, [sp], #4 8004de6: 4770 bx lr 8004de8: 6fffffc0 .word 0x6fffffc0 08004dec : * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) { 8004dec: b480 push {r7} 8004dee: b083 sub sp, #12 8004df0: af00 add r7, sp, #0 8004df2: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 8004df4: 687b ldr r3, [r7, #4] 8004df6: 689b ldr r3, [r3, #8] 8004df8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8004dfc: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8004e00: d101 bne.n 8004e06 8004e02: 2301 movs r3, #1 8004e04: e000 b.n 8004e08 8004e06: 2300 movs r3, #0 } 8004e08: 4618 mov r0, r3 8004e0a: 370c adds r7, #12 8004e0c: 46bd mov sp, r7 8004e0e: f85d 7b04 ldr.w r7, [sp], #4 8004e12: 4770 bx lr 08004e14 : * @rmtoll CR ADEN LL_ADC_Enable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) { 8004e14: b480 push {r7} 8004e16: b083 sub sp, #12 8004e18: af00 add r7, sp, #0 8004e1a: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8004e1c: 687b ldr r3, [r7, #4] 8004e1e: 689a ldr r2, [r3, #8] 8004e20: 4b05 ldr r3, [pc, #20] @ (8004e38 ) 8004e22: 4013 ands r3, r2 8004e24: f043 0201 orr.w r2, r3, #1 8004e28: 687b ldr r3, [r7, #4] 8004e2a: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN); } 8004e2c: bf00 nop 8004e2e: 370c adds r7, #12 8004e30: 46bd mov sp, r7 8004e32: f85d 7b04 ldr.w r7, [sp], #4 8004e36: 4770 bx lr 8004e38: 7fffffc0 .word 0x7fffffc0 08004e3c : * @rmtoll CR ADDIS LL_ADC_Disable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) { 8004e3c: b480 push {r7} 8004e3e: b083 sub sp, #12 8004e40: af00 add r7, sp, #0 8004e42: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8004e44: 687b ldr r3, [r7, #4] 8004e46: 689a ldr r2, [r3, #8] 8004e48: 4b05 ldr r3, [pc, #20] @ (8004e60 ) 8004e4a: 4013 ands r3, r2 8004e4c: f043 0202 orr.w r2, r3, #2 8004e50: 687b ldr r3, [r7, #4] 8004e52: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS); } 8004e54: bf00 nop 8004e56: 370c adds r7, #12 8004e58: 46bd mov sp, r7 8004e5a: f85d 7b04 ldr.w r7, [sp], #4 8004e5e: 4770 bx lr 8004e60: 7fffffc0 .word 0x7fffffc0 08004e64 : * @rmtoll CR ADEN LL_ADC_IsEnabled * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) { 8004e64: b480 push {r7} 8004e66: b083 sub sp, #12 8004e68: af00 add r7, sp, #0 8004e6a: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8004e6c: 687b ldr r3, [r7, #4] 8004e6e: 689b ldr r3, [r3, #8] 8004e70: f003 0301 and.w r3, r3, #1 8004e74: 2b01 cmp r3, #1 8004e76: d101 bne.n 8004e7c 8004e78: 2301 movs r3, #1 8004e7a: e000 b.n 8004e7e 8004e7c: 2300 movs r3, #0 } 8004e7e: 4618 mov r0, r3 8004e80: 370c adds r7, #12 8004e82: 46bd mov sp, r7 8004e84: f85d 7b04 ldr.w r7, [sp], #4 8004e88: 4770 bx lr 08004e8a : * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) { 8004e8a: b480 push {r7} 8004e8c: b083 sub sp, #12 8004e8e: af00 add r7, sp, #0 8004e90: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); 8004e92: 687b ldr r3, [r7, #4] 8004e94: 689b ldr r3, [r3, #8] 8004e96: f003 0302 and.w r3, r3, #2 8004e9a: 2b02 cmp r3, #2 8004e9c: d101 bne.n 8004ea2 8004e9e: 2301 movs r3, #1 8004ea0: e000 b.n 8004ea4 8004ea2: 2300 movs r3, #0 } 8004ea4: 4618 mov r0, r3 8004ea6: 370c adds r7, #12 8004ea8: 46bd mov sp, r7 8004eaa: f85d 7b04 ldr.w r7, [sp], #4 8004eae: 4770 bx lr 08004eb0 : * @rmtoll CR ADSTART LL_ADC_REG_StartConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) { 8004eb0: b480 push {r7} 8004eb2: b083 sub sp, #12 8004eb4: af00 add r7, sp, #0 8004eb6: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8004eb8: 687b ldr r3, [r7, #4] 8004eba: 689a ldr r2, [r3, #8] 8004ebc: 4b05 ldr r3, [pc, #20] @ (8004ed4 ) 8004ebe: 4013 ands r3, r2 8004ec0: f043 0204 orr.w r2, r3, #4 8004ec4: 687b ldr r3, [r7, #4] 8004ec6: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART); } 8004ec8: bf00 nop 8004eca: 370c adds r7, #12 8004ecc: 46bd mov sp, r7 8004ece: f85d 7b04 ldr.w r7, [sp], #4 8004ed2: 4770 bx lr 8004ed4: 7fffffc0 .word 0x7fffffc0 08004ed8 : * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) { 8004ed8: b480 push {r7} 8004eda: b083 sub sp, #12 8004edc: af00 add r7, sp, #0 8004ede: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8004ee0: 687b ldr r3, [r7, #4] 8004ee2: 689b ldr r3, [r3, #8] 8004ee4: f003 0304 and.w r3, r3, #4 8004ee8: 2b04 cmp r3, #4 8004eea: d101 bne.n 8004ef0 8004eec: 2301 movs r3, #1 8004eee: e000 b.n 8004ef2 8004ef0: 2300 movs r3, #0 } 8004ef2: 4618 mov r0, r3 8004ef4: 370c adds r7, #12 8004ef6: 46bd mov sp, r7 8004ef8: f85d 7b04 ldr.w r7, [sp], #4 8004efc: 4770 bx lr 08004efe : * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) { 8004efe: b480 push {r7} 8004f00: b083 sub sp, #12 8004f02: af00 add r7, sp, #0 8004f04: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 8004f06: 687b ldr r3, [r7, #4] 8004f08: 689b ldr r3, [r3, #8] 8004f0a: f003 0308 and.w r3, r3, #8 8004f0e: 2b08 cmp r3, #8 8004f10: d101 bne.n 8004f16 8004f12: 2301 movs r3, #1 8004f14: e000 b.n 8004f18 8004f16: 2300 movs r3, #0 } 8004f18: 4618 mov r0, r3 8004f1a: 370c adds r7, #12 8004f1c: 46bd mov sp, r7 8004f1e: f85d 7b04 ldr.w r7, [sp], #4 8004f22: 4770 bx lr 08004f24 : * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { 8004f24: b590 push {r4, r7, lr} 8004f26: b089 sub sp, #36 @ 0x24 8004f28: af00 add r7, sp, #0 8004f2a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8004f2c: 2300 movs r3, #0 8004f2e: 77fb strb r3, [r7, #31] uint32_t tmpCFGR; uint32_t tmp_adc_reg_is_conversion_on_going; __IO uint32_t wait_loop_index = 0UL; 8004f30: 2300 movs r3, #0 8004f32: 60bb str r3, [r7, #8] uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check ADC handle */ if (hadc == NULL) 8004f34: 687b ldr r3, [r7, #4] 8004f36: 2b00 cmp r3, #0 8004f38: d101 bne.n 8004f3e { return HAL_ERROR; 8004f3a: 2301 movs r3, #1 8004f3c: e18f b.n 800525e assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 8004f3e: 687b ldr r3, [r7, #4] 8004f40: 68db ldr r3, [r3, #12] 8004f42: 2b00 cmp r3, #0 /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8004f44: 687b ldr r3, [r7, #4] 8004f46: 6d5b ldr r3, [r3, #84] @ 0x54 8004f48: 2b00 cmp r3, #0 8004f4a: d109 bne.n 8004f60 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8004f4c: 6878 ldr r0, [r7, #4] 8004f4e: f7fd ffb7 bl 8002ec0 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8004f52: 687b ldr r3, [r7, #4] 8004f54: 2200 movs r2, #0 8004f56: 659a str r2, [r3, #88] @ 0x58 /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; 8004f58: 687b ldr r3, [r7, #4] 8004f5a: 2200 movs r2, #0 8004f5c: f883 2050 strb.w r2, [r3, #80] @ 0x50 } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) 8004f60: 687b ldr r3, [r7, #4] 8004f62: 681b ldr r3, [r3, #0] 8004f64: 4618 mov r0, r3 8004f66: f7ff ff19 bl 8004d9c 8004f6a: 4603 mov r3, r0 8004f6c: 2b00 cmp r3, #0 8004f6e: d004 beq.n 8004f7a { /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); 8004f70: 687b ldr r3, [r7, #4] 8004f72: 681b ldr r3, [r3, #0] 8004f74: 4618 mov r0, r3 8004f76: f7ff feff bl 8004d78 /* System was in deep power down mode, calibration must be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 8004f7a: 687b ldr r3, [r7, #4] 8004f7c: 681b ldr r3, [r3, #0] 8004f7e: 4618 mov r0, r3 8004f80: f7ff ff34 bl 8004dec 8004f84: 4603 mov r3, r0 8004f86: 2b00 cmp r3, #0 8004f88: d114 bne.n 8004fb4 { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); 8004f8a: 687b ldr r3, [r7, #4] 8004f8c: 681b ldr r3, [r3, #0] 8004f8e: 4618 mov r0, r3 8004f90: f7ff ff18 bl 8004dc4 /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8004f94: 4b87 ldr r3, [pc, #540] @ (80051b4 ) 8004f96: 681b ldr r3, [r3, #0] 8004f98: 099b lsrs r3, r3, #6 8004f9a: 4a87 ldr r2, [pc, #540] @ (80051b8 ) 8004f9c: fba2 2303 umull r2, r3, r2, r3 8004fa0: 099b lsrs r3, r3, #6 8004fa2: 3301 adds r3, #1 8004fa4: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8004fa6: e002 b.n 8004fae { wait_loop_index--; 8004fa8: 68bb ldr r3, [r7, #8] 8004faa: 3b01 subs r3, #1 8004fac: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8004fae: 68bb ldr r3, [r7, #8] 8004fb0: 2b00 cmp r3, #0 8004fb2: d1f9 bne.n 8004fa8 } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 8004fb4: 687b ldr r3, [r7, #4] 8004fb6: 681b ldr r3, [r3, #0] 8004fb8: 4618 mov r0, r3 8004fba: f7ff ff17 bl 8004dec 8004fbe: 4603 mov r3, r0 8004fc0: 2b00 cmp r3, #0 8004fc2: d10d bne.n 8004fe0 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8004fc4: 687b ldr r3, [r7, #4] 8004fc6: 6d5b ldr r3, [r3, #84] @ 0x54 8004fc8: f043 0210 orr.w r2, r3, #16 8004fcc: 687b ldr r3, [r7, #4] 8004fce: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8004fd0: 687b ldr r3, [r7, #4] 8004fd2: 6d9b ldr r3, [r3, #88] @ 0x58 8004fd4: f043 0201 orr.w r2, r3, #1 8004fd8: 687b ldr r3, [r7, #4] 8004fda: 659a str r2, [r3, #88] @ 0x58 tmp_hal_status = HAL_ERROR; 8004fdc: 2301 movs r3, #1 8004fde: 77fb strb r3, [r7, #31] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8004fe0: 687b ldr r3, [r7, #4] 8004fe2: 681b ldr r3, [r3, #0] 8004fe4: 4618 mov r0, r3 8004fe6: f7ff ff77 bl 8004ed8 8004fea: 6178 str r0, [r7, #20] if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 8004fec: 687b ldr r3, [r7, #4] 8004fee: 6d5b ldr r3, [r3, #84] @ 0x54 8004ff0: f003 0310 and.w r3, r3, #16 8004ff4: 2b00 cmp r3, #0 8004ff6: f040 8129 bne.w 800524c && (tmp_adc_reg_is_conversion_on_going == 0UL) 8004ffa: 697b ldr r3, [r7, #20] 8004ffc: 2b00 cmp r3, #0 8004ffe: f040 8125 bne.w 800524c ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8005002: 687b ldr r3, [r7, #4] 8005004: 6d5b ldr r3, [r3, #84] @ 0x54 8005006: f423 7381 bic.w r3, r3, #258 @ 0x102 800500a: f043 0202 orr.w r2, r3, #2 800500e: 687b ldr r3, [r7, #4] 8005010: 655a str r2, [r3, #84] @ 0x54 /* Configuration of common ADC parameters */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8005012: 687b ldr r3, [r7, #4] 8005014: 681b ldr r3, [r3, #0] 8005016: 4618 mov r0, r3 8005018: f7ff ff24 bl 8004e64 800501c: 4603 mov r3, r0 800501e: 2b00 cmp r3, #0 8005020: d136 bne.n 8005090 { if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8005022: 687b ldr r3, [r7, #4] 8005024: 681b ldr r3, [r3, #0] 8005026: 4a65 ldr r2, [pc, #404] @ (80051bc ) 8005028: 4293 cmp r3, r2 800502a: d004 beq.n 8005036 800502c: 687b ldr r3, [r7, #4] 800502e: 681b ldr r3, [r3, #0] 8005030: 4a63 ldr r2, [pc, #396] @ (80051c0 ) 8005032: 4293 cmp r3, r2 8005034: d10e bne.n 8005054 8005036: 4861 ldr r0, [pc, #388] @ (80051bc ) 8005038: f7ff ff14 bl 8004e64 800503c: 4604 mov r4, r0 800503e: 4860 ldr r0, [pc, #384] @ (80051c0 ) 8005040: f7ff ff10 bl 8004e64 8005044: 4603 mov r3, r0 8005046: 4323 orrs r3, r4 8005048: 2b00 cmp r3, #0 800504a: bf0c ite eq 800504c: 2301 moveq r3, #1 800504e: 2300 movne r3, #0 8005050: b2db uxtb r3, r3 8005052: e008 b.n 8005066 8005054: 485b ldr r0, [pc, #364] @ (80051c4 ) 8005056: f7ff ff05 bl 8004e64 800505a: 4603 mov r3, r0 800505c: 2b00 cmp r3, #0 800505e: bf0c ite eq 8005060: 2301 moveq r3, #1 8005062: 2300 movne r3, #0 8005064: b2db uxtb r3, r3 8005066: 2b00 cmp r3, #0 8005068: d012 beq.n 8005090 /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ /* HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); 800506a: 687b ldr r3, [r7, #4] 800506c: 681b ldr r3, [r3, #0] 800506e: 4a53 ldr r2, [pc, #332] @ (80051bc ) 8005070: 4293 cmp r3, r2 8005072: d004 beq.n 800507e 8005074: 687b ldr r3, [r7, #4] 8005076: 681b ldr r3, [r3, #0] 8005078: 4a51 ldr r2, [pc, #324] @ (80051c0 ) 800507a: 4293 cmp r3, r2 800507c: d101 bne.n 8005082 800507e: 4a52 ldr r2, [pc, #328] @ (80051c8 ) 8005080: e000 b.n 8005084 8005082: 4a52 ldr r2, [pc, #328] @ (80051cc ) 8005084: 687b ldr r3, [r7, #4] 8005086: 685b ldr r3, [r3, #4] 8005088: 4619 mov r1, r3 800508a: 4610 mov r0, r2 800508c: f7ff fd3c bl 8004b08 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); } #else if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution)) 8005090: f7ff fcf4 bl 8004a7c 8005094: 4603 mov r3, r0 8005096: f241 0203 movw r2, #4099 @ 0x1003 800509a: 4293 cmp r3, r2 800509c: d914 bls.n 80050c8 800509e: 687b ldr r3, [r7, #4] 80050a0: 689b ldr r3, [r3, #8] 80050a2: 2b10 cmp r3, #16 80050a4: d110 bne.n 80050c8 { /* for STM32H7 silicon rev.B and above , ADC_CFGR_RES value for 8bits resolution is : b111 */ tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 80050a6: 687b ldr r3, [r7, #4] 80050a8: 7d5b ldrb r3, [r3, #21] 80050aa: 035a lsls r2, r3, #13 hadc->Init.Overrun | 80050ac: 687b ldr r3, [r7, #4] 80050ae: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 80050b0: 431a orrs r2, r3 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 80050b2: 687b ldr r3, [r7, #4] 80050b4: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 80050b6: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 80050b8: 687b ldr r3, [r7, #4] 80050ba: 7f1b ldrb r3, [r3, #28] 80050bc: 041b lsls r3, r3, #16 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 80050be: 4313 orrs r3, r2 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 80050c0: f043 030c orr.w r3, r3, #12 80050c4: 61bb str r3, [r7, #24] 80050c6: e00d b.n 80050e4 } else { tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 80050c8: 687b ldr r3, [r7, #4] 80050ca: 7d5b ldrb r3, [r3, #21] 80050cc: 035a lsls r2, r3, #13 hadc->Init.Overrun | 80050ce: 687b ldr r3, [r7, #4] 80050d0: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 80050d2: 431a orrs r2, r3 hadc->Init.Resolution | 80050d4: 687b ldr r3, [r7, #4] 80050d6: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 80050d8: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 80050da: 687b ldr r3, [r7, #4] 80050dc: 7f1b ldrb r3, [r3, #28] 80050de: 041b lsls r3, r3, #16 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 80050e0: 4313 orrs r3, r2 80050e2: 61bb str r3, [r7, #24] } #endif /* ADC_VER_V5_3 */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 80050e4: 687b ldr r3, [r7, #4] 80050e6: 7f1b ldrb r3, [r3, #28] 80050e8: 2b01 cmp r3, #1 80050ea: d106 bne.n 80050fa { tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); 80050ec: 687b ldr r3, [r7, #4] 80050ee: 6a1b ldr r3, [r3, #32] 80050f0: 3b01 subs r3, #1 80050f2: 045b lsls r3, r3, #17 80050f4: 69ba ldr r2, [r7, #24] 80050f6: 4313 orrs r3, r2 80050f8: 61bb str r3, [r7, #24] /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 80050fa: 687b ldr r3, [r7, #4] 80050fc: 6a5b ldr r3, [r3, #36] @ 0x24 80050fe: 2b00 cmp r3, #0 8005100: d009 beq.n 8005116 { tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8005102: 687b ldr r3, [r7, #4] 8005104: 6a5b ldr r3, [r3, #36] @ 0x24 8005106: f403 7278 and.w r2, r3, #992 @ 0x3e0 | hadc->Init.ExternalTrigConvEdge 800510a: 687b ldr r3, [r7, #4] 800510c: 6a9b ldr r3, [r3, #40] @ 0x28 800510e: 4313 orrs r3, r2 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8005110: 69ba ldr r2, [r7, #24] 8005112: 4313 orrs r3, r2 8005114: 61bb str r3, [r7, #24] /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); } #else /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); 8005116: 687b ldr r3, [r7, #4] 8005118: 681b ldr r3, [r3, #0] 800511a: 68da ldr r2, [r3, #12] 800511c: 4b2c ldr r3, [pc, #176] @ (80051d0 ) 800511e: 4013 ands r3, r2 8005120: 687a ldr r2, [r7, #4] 8005122: 6812 ldr r2, [r2, #0] 8005124: 69b9 ldr r1, [r7, #24] 8005126: 430b orrs r3, r1 8005128: 60d3 str r3, [r2, #12] /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - Conversion data management Init.ConversionDataManagement */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 800512a: 687b ldr r3, [r7, #4] 800512c: 681b ldr r3, [r3, #0] 800512e: 4618 mov r0, r3 8005130: f7ff fed2 bl 8004ed8 8005134: 6138 str r0, [r7, #16] tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 8005136: 687b ldr r3, [r7, #4] 8005138: 681b ldr r3, [r3, #0] 800513a: 4618 mov r0, r3 800513c: f7ff fedf bl 8004efe 8005140: 60f8 str r0, [r7, #12] if ((tmp_adc_is_conversion_on_going_regular == 0UL) 8005142: 693b ldr r3, [r7, #16] 8005144: 2b00 cmp r3, #0 8005146: d15f bne.n 8005208 && (tmp_adc_is_conversion_on_going_injected == 0UL) 8005148: 68fb ldr r3, [r7, #12] 800514a: 2b00 cmp r3, #0 800514c: d15c bne.n 8005208 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); } #else tmpCFGR = ( ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 800514e: 687b ldr r3, [r7, #4] 8005150: 7d1b ldrb r3, [r3, #20] 8005152: 039a lsls r2, r3, #14 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); 8005154: 687b ldr r3, [r7, #4] 8005156: 6adb ldr r3, [r3, #44] @ 0x2c tmpCFGR = ( 8005158: 4313 orrs r3, r2 800515a: 61bb str r3, [r7, #24] #endif MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 800515c: 687b ldr r3, [r7, #4] 800515e: 681b ldr r3, [r3, #0] 8005160: 68da ldr r2, [r3, #12] 8005162: 4b1c ldr r3, [pc, #112] @ (80051d4 ) 8005164: 4013 ands r3, r2 8005166: 687a ldr r2, [r7, #4] 8005168: 6812 ldr r2, [r2, #0] 800516a: 69b9 ldr r1, [r7, #24] 800516c: 430b orrs r3, r1 800516e: 60d3 str r3, [r2, #12] if (hadc->Init.OversamplingMode == ENABLE) 8005170: 687b ldr r3, [r7, #4] 8005172: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 8005176: 2b01 cmp r3, #1 8005178: d130 bne.n 80051dc #endif assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START) 800517a: 687b ldr r3, [r7, #4] 800517c: 6a5b ldr r3, [r3, #36] @ 0x24 800517e: 2b00 cmp r3, #0 /* - Oversampling Ratio */ /* - Right bit shift */ /* - Left bit shift */ /* - Triggered mode */ /* - Oversampling mode (continued/resumed) */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, 8005180: 687b ldr r3, [r7, #4] 8005182: 681b ldr r3, [r3, #0] 8005184: 691a ldr r2, [r3, #16] 8005186: 4b14 ldr r3, [pc, #80] @ (80051d8 ) 8005188: 4013 ands r3, r2 800518a: 687a ldr r2, [r7, #4] 800518c: 6bd2 ldr r2, [r2, #60] @ 0x3c 800518e: 3a01 subs r2, #1 8005190: 0411 lsls r1, r2, #16 8005192: 687a ldr r2, [r7, #4] 8005194: 6c12 ldr r2, [r2, #64] @ 0x40 8005196: 4311 orrs r1, r2 8005198: 687a ldr r2, [r7, #4] 800519a: 6c52 ldr r2, [r2, #68] @ 0x44 800519c: 4311 orrs r1, r2 800519e: 687a ldr r2, [r7, #4] 80051a0: 6c92 ldr r2, [r2, #72] @ 0x48 80051a2: 430a orrs r2, r1 80051a4: 431a orrs r2, r3 80051a6: 687b ldr r3, [r7, #4] 80051a8: 681b ldr r3, [r3, #0] 80051aa: f042 0201 orr.w r2, r2, #1 80051ae: 611a str r2, [r3, #16] 80051b0: e01c b.n 80051ec 80051b2: bf00 nop 80051b4: 24000034 .word 0x24000034 80051b8: 053e2d63 .word 0x053e2d63 80051bc: 40022000 .word 0x40022000 80051c0: 40022100 .word 0x40022100 80051c4: 58026000 .word 0x58026000 80051c8: 40022300 .word 0x40022300 80051cc: 58026300 .word 0x58026300 80051d0: fff0c003 .word 0xfff0c003 80051d4: ffffbffc .word 0xffffbffc 80051d8: fc00f81e .word 0xfc00f81e } else { /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); 80051dc: 687b ldr r3, [r7, #4] 80051de: 681b ldr r3, [r3, #0] 80051e0: 691a ldr r2, [r3, #16] 80051e2: 687b ldr r3, [r7, #4] 80051e4: 681b ldr r3, [r3, #0] 80051e6: f022 0201 bic.w r2, r2, #1 80051ea: 611a str r2, [r3, #16] } /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift); 80051ec: 687b ldr r3, [r7, #4] 80051ee: 681b ldr r3, [r3, #0] 80051f0: 691b ldr r3, [r3, #16] 80051f2: f023 4170 bic.w r1, r3, #4026531840 @ 0xf0000000 80051f6: 687b ldr r3, [r7, #4] 80051f8: 6b5a ldr r2, [r3, #52] @ 0x34 80051fa: 687b ldr r3, [r7, #4] 80051fc: 681b ldr r3, [r3, #0] 80051fe: 430a orrs r2, r1 8005200: 611a str r2, [r3, #16] /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); } #else /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); 8005202: 6878 ldr r0, [r7, #4] 8005204: f000 fde2 bl 8005dcc /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 8005208: 687b ldr r3, [r7, #4] 800520a: 68db ldr r3, [r3, #12] 800520c: 2b01 cmp r3, #1 800520e: d10c bne.n 800522a { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); 8005210: 687b ldr r3, [r7, #4] 8005212: 681b ldr r3, [r3, #0] 8005214: 6b1b ldr r3, [r3, #48] @ 0x30 8005216: f023 010f bic.w r1, r3, #15 800521a: 687b ldr r3, [r7, #4] 800521c: 699b ldr r3, [r3, #24] 800521e: 1e5a subs r2, r3, #1 8005220: 687b ldr r3, [r7, #4] 8005222: 681b ldr r3, [r3, #0] 8005224: 430a orrs r2, r1 8005226: 631a str r2, [r3, #48] @ 0x30 8005228: e007 b.n 800523a } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 800522a: 687b ldr r3, [r7, #4] 800522c: 681b ldr r3, [r3, #0] 800522e: 6b1a ldr r2, [r3, #48] @ 0x30 8005230: 687b ldr r3, [r7, #4] 8005232: 681b ldr r3, [r3, #0] 8005234: f022 020f bic.w r2, r2, #15 8005238: 631a str r2, [r3, #48] @ 0x30 } /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); 800523a: 687b ldr r3, [r7, #4] 800523c: 6d5b ldr r3, [r3, #84] @ 0x54 800523e: f023 0303 bic.w r3, r3, #3 8005242: f043 0201 orr.w r2, r3, #1 8005246: 687b ldr r3, [r7, #4] 8005248: 655a str r2, [r3, #84] @ 0x54 800524a: e007 b.n 800525c } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800524c: 687b ldr r3, [r7, #4] 800524e: 6d5b ldr r3, [r3, #84] @ 0x54 8005250: f043 0210 orr.w r2, r3, #16 8005254: 687b ldr r3, [r7, #4] 8005256: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8005258: 2301 movs r3, #1 800525a: 77fb strb r3, [r7, #31] } /* Return function status */ return tmp_hal_status; 800525c: 7ffb ldrb r3, [r7, #31] } 800525e: 4618 mov r0, r3 8005260: 3724 adds r7, #36 @ 0x24 8005262: 46bd mov sp, r7 8005264: bd90 pop {r4, r7, pc} 8005266: bf00 nop 08005268 : * @param pData Destination Buffer address. * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { 8005268: b580 push {r7, lr} 800526a: b086 sub sp, #24 800526c: af00 add r7, sp, #0 800526e: 60f8 str r0, [r7, #12] 8005270: 60b9 str r1, [r7, #8] 8005272: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8005274: 68fb ldr r3, [r7, #12] 8005276: 681b ldr r3, [r3, #0] 8005278: 4a55 ldr r2, [pc, #340] @ (80053d0 ) 800527a: 4293 cmp r3, r2 800527c: d004 beq.n 8005288 800527e: 68fb ldr r3, [r7, #12] 8005280: 681b ldr r3, [r3, #0] 8005282: 4a54 ldr r2, [pc, #336] @ (80053d4 ) 8005284: 4293 cmp r3, r2 8005286: d101 bne.n 800528c 8005288: 4b53 ldr r3, [pc, #332] @ (80053d8 ) 800528a: e000 b.n 800528e 800528c: 4b53 ldr r3, [pc, #332] @ (80053dc ) 800528e: 4618 mov r0, r3 8005290: f7ff fd64 bl 8004d5c 8005294: 6138 str r0, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8005296: 68fb ldr r3, [r7, #12] 8005298: 681b ldr r3, [r3, #0] 800529a: 4618 mov r0, r3 800529c: f7ff fe1c bl 8004ed8 80052a0: 4603 mov r3, r0 80052a2: 2b00 cmp r3, #0 80052a4: f040 808c bne.w 80053c0 { /* Process locked */ __HAL_LOCK(hadc); 80052a8: 68fb ldr r3, [r7, #12] 80052aa: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 80052ae: 2b01 cmp r3, #1 80052b0: d101 bne.n 80052b6 80052b2: 2302 movs r3, #2 80052b4: e087 b.n 80053c6 80052b6: 68fb ldr r3, [r7, #12] 80052b8: 2201 movs r2, #1 80052ba: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Ensure that multimode regular conversions are not enabled. */ /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 80052be: 693b ldr r3, [r7, #16] 80052c0: 2b00 cmp r3, #0 80052c2: d005 beq.n 80052d0 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) 80052c4: 693b ldr r3, [r7, #16] 80052c6: 2b05 cmp r3, #5 80052c8: d002 beq.n 80052d0 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) 80052ca: 693b ldr r3, [r7, #16] 80052cc: 2b09 cmp r3, #9 80052ce: d170 bne.n 80053b2 ) { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 80052d0: 68f8 ldr r0, [r7, #12] 80052d2: f000 fbfd bl 8005ad0 80052d6: 4603 mov r3, r0 80052d8: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 80052da: 7dfb ldrb r3, [r7, #23] 80052dc: 2b00 cmp r3, #0 80052de: d163 bne.n 80053a8 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 80052e0: 68fb ldr r3, [r7, #12] 80052e2: 6d5a ldr r2, [r3, #84] @ 0x54 80052e4: 4b3e ldr r3, [pc, #248] @ (80053e0 ) 80052e6: 4013 ands r3, r2 80052e8: f443 7280 orr.w r2, r3, #256 @ 0x100 80052ec: 68fb ldr r3, [r7, #12] 80052ee: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_REG_BUSY); /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 80052f0: 68fb ldr r3, [r7, #12] 80052f2: 681b ldr r3, [r3, #0] 80052f4: 4a37 ldr r2, [pc, #220] @ (80053d4 ) 80052f6: 4293 cmp r3, r2 80052f8: d002 beq.n 8005300 80052fa: 68fb ldr r3, [r7, #12] 80052fc: 681b ldr r3, [r3, #0] 80052fe: e000 b.n 8005302 8005300: 4b33 ldr r3, [pc, #204] @ (80053d0 ) 8005302: 68fa ldr r2, [r7, #12] 8005304: 6812 ldr r2, [r2, #0] 8005306: 4293 cmp r3, r2 8005308: d002 beq.n 8005310 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 800530a: 693b ldr r3, [r7, #16] 800530c: 2b00 cmp r3, #0 800530e: d105 bne.n 800531c ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8005310: 68fb ldr r3, [r7, #12] 8005312: 6d5b ldr r3, [r3, #84] @ 0x54 8005314: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 8005318: 68fb ldr r3, [r7, #12] 800531a: 655a str r2, [r3, #84] @ 0x54 } /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) 800531c: 68fb ldr r3, [r7, #12] 800531e: 6d5b ldr r3, [r3, #84] @ 0x54 8005320: f403 5380 and.w r3, r3, #4096 @ 0x1000 8005324: 2b00 cmp r3, #0 8005326: d006 beq.n 8005336 { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8005328: 68fb ldr r3, [r7, #12] 800532a: 6d9b ldr r3, [r3, #88] @ 0x58 800532c: f023 0206 bic.w r2, r3, #6 8005330: 68fb ldr r3, [r7, #12] 8005332: 659a str r2, [r3, #88] @ 0x58 8005334: e002 b.n 800533c } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8005336: 68fb ldr r3, [r7, #12] 8005338: 2200 movs r2, #0 800533a: 659a str r2, [r3, #88] @ 0x58 } /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 800533c: 68fb ldr r3, [r7, #12] 800533e: 6cdb ldr r3, [r3, #76] @ 0x4c 8005340: 4a28 ldr r2, [pc, #160] @ (80053e4 ) 8005342: 63da str r2, [r3, #60] @ 0x3c /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 8005344: 68fb ldr r3, [r7, #12] 8005346: 6cdb ldr r3, [r3, #76] @ 0x4c 8005348: 4a27 ldr r2, [pc, #156] @ (80053e8 ) 800534a: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 800534c: 68fb ldr r3, [r7, #12] 800534e: 6cdb ldr r3, [r3, #76] @ 0x4c 8005350: 4a26 ldr r2, [pc, #152] @ (80053ec ) 8005352: 64da str r2, [r3, #76] @ 0x4c /* ADC start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 8005354: 68fb ldr r3, [r7, #12] 8005356: 681b ldr r3, [r3, #0] 8005358: 221c movs r2, #28 800535a: 601a str r2, [r3, #0] /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 800535c: 68fb ldr r3, [r7, #12] 800535e: 2200 movs r2, #0 8005360: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* With DMA, overrun event is always considered as an error even if hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, ADC_IT_OVR is enabled. */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 8005364: 68fb ldr r3, [r7, #12] 8005366: 681b ldr r3, [r3, #0] 8005368: 685a ldr r2, [r3, #4] 800536a: 68fb ldr r3, [r7, #12] 800536c: 681b ldr r3, [r3, #0] 800536e: f042 0210 orr.w r2, r2, #16 8005372: 605a str r2, [r3, #4] { LL_ADC_REG_SetDataTransferMode(hadc->Instance, ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); } #else LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement); 8005374: 68fb ldr r3, [r7, #12] 8005376: 681a ldr r2, [r3, #0] 8005378: 68fb ldr r3, [r7, #12] 800537a: 6adb ldr r3, [r3, #44] @ 0x2c 800537c: 4619 mov r1, r3 800537e: 4610 mov r0, r2 8005380: f7ff fc89 bl 8004c96 #endif /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 8005384: 68fb ldr r3, [r7, #12] 8005386: 6cd8 ldr r0, [r3, #76] @ 0x4c 8005388: 68fb ldr r3, [r7, #12] 800538a: 681b ldr r3, [r3, #0] 800538c: 3340 adds r3, #64 @ 0x40 800538e: 4619 mov r1, r3 8005390: 68ba ldr r2, [r7, #8] 8005392: 687b ldr r3, [r7, #4] 8005394: f002 f8cc bl 8007530 8005398: 4603 mov r3, r0 800539a: 75fb strb r3, [r7, #23] /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); 800539c: 68fb ldr r3, [r7, #12] 800539e: 681b ldr r3, [r3, #0] 80053a0: 4618 mov r0, r3 80053a2: f7ff fd85 bl 8004eb0 if (tmp_hal_status == HAL_OK) 80053a6: e00d b.n 80053c4 } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 80053a8: 68fb ldr r3, [r7, #12] 80053aa: 2200 movs r2, #0 80053ac: f883 2050 strb.w r2, [r3, #80] @ 0x50 if (tmp_hal_status == HAL_OK) 80053b0: e008 b.n 80053c4 } } else { tmp_hal_status = HAL_ERROR; 80053b2: 2301 movs r3, #1 80053b4: 75fb strb r3, [r7, #23] /* Process unlocked */ __HAL_UNLOCK(hadc); 80053b6: 68fb ldr r3, [r7, #12] 80053b8: 2200 movs r2, #0 80053ba: f883 2050 strb.w r2, [r3, #80] @ 0x50 80053be: e001 b.n 80053c4 } } else { tmp_hal_status = HAL_BUSY; 80053c0: 2302 movs r3, #2 80053c2: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 80053c4: 7dfb ldrb r3, [r7, #23] } 80053c6: 4618 mov r0, r3 80053c8: 3718 adds r7, #24 80053ca: 46bd mov sp, r7 80053cc: bd80 pop {r7, pc} 80053ce: bf00 nop 80053d0: 40022000 .word 0x40022000 80053d4: 40022100 .word 0x40022100 80053d8: 40022300 .word 0x40022300 80053dc: 58026300 .word 0x58026300 80053e0: fffff0fe .word 0xfffff0fe 80053e4: 08005ca3 .word 0x08005ca3 80053e8: 08005d7b .word 0x08005d7b 80053ec: 08005d97 .word 0x08005d97 080053f0 : * @brief Conversion DMA half-transfer callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { 80053f0: b480 push {r7} 80053f2: b083 sub sp, #12 80053f4: af00 add r7, sp, #0 80053f6: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 80053f8: bf00 nop 80053fa: 370c adds r7, #12 80053fc: 46bd mov sp, r7 80053fe: f85d 7b04 ldr.w r7, [sp], #4 8005402: 4770 bx lr 08005404 : * (this function is also clearing overrun flag) * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 8005404: b480 push {r7} 8005406: b083 sub sp, #12 8005408: af00 add r7, sp, #0 800540a: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 800540c: bf00 nop 800540e: 370c adds r7, #12 8005410: 46bd mov sp, r7 8005412: f85d 7b04 ldr.w r7, [sp], #4 8005416: 4770 bx lr 08005418 : * @param hadc ADC handle * @param sConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { 8005418: b590 push {r4, r7, lr} 800541a: b0a1 sub sp, #132 @ 0x84 800541c: af00 add r7, sp, #0 800541e: 6078 str r0, [r7, #4] 8005420: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8005422: 2300 movs r3, #0 8005424: f887 307f strb.w r3, [r7, #127] @ 0x7f uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0; 8005428: 2300 movs r3, #0 800542a: 60bb str r3, [r7, #8] /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); /* Verification of channel number */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) 800542c: 683b ldr r3, [r7, #0] 800542e: 68db ldr r3, [r3, #12] 8005430: 4a65 ldr r2, [pc, #404] @ (80055c8 ) 8005432: 4293 cmp r3, r2 } #endif } /* Process locked */ __HAL_LOCK(hadc); 8005434: 687b ldr r3, [r7, #4] 8005436: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 800543a: 2b01 cmp r3, #1 800543c: d101 bne.n 8005442 800543e: 2302 movs r3, #2 8005440: e32e b.n 8005aa0 8005442: 687b ldr r3, [r7, #4] 8005444: 2201 movs r2, #1 8005446: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 800544a: 687b ldr r3, [r7, #4] 800544c: 681b ldr r3, [r3, #0] 800544e: 4618 mov r0, r3 8005450: f7ff fd42 bl 8004ed8 8005454: 4603 mov r3, r0 8005456: 2b00 cmp r3, #0 8005458: f040 8313 bne.w 8005a82 { if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))) 800545c: 683b ldr r3, [r7, #0] 800545e: 681b ldr r3, [r3, #0] 8005460: 2b00 cmp r3, #0 8005462: db2c blt.n 80054be /* ADC channels preselection */ hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); } #else /* ADC channels preselection */ hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); 8005464: 683b ldr r3, [r7, #0] 8005466: 681b ldr r3, [r3, #0] 8005468: f3c3 0313 ubfx r3, r3, #0, #20 800546c: 2b00 cmp r3, #0 800546e: d108 bne.n 8005482 8005470: 683b ldr r3, [r7, #0] 8005472: 681b ldr r3, [r3, #0] 8005474: 0e9b lsrs r3, r3, #26 8005476: f003 031f and.w r3, r3, #31 800547a: 2201 movs r2, #1 800547c: fa02 f303 lsl.w r3, r2, r3 8005480: e016 b.n 80054b0 8005482: 683b ldr r3, [r7, #0] 8005484: 681b ldr r3, [r3, #0] 8005486: 667b str r3, [r7, #100] @ 0x64 uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005488: 6e7b ldr r3, [r7, #100] @ 0x64 800548a: fa93 f3a3 rbit r3, r3 800548e: 663b str r3, [r7, #96] @ 0x60 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 8005490: 6e3b ldr r3, [r7, #96] @ 0x60 8005492: 66bb str r3, [r7, #104] @ 0x68 optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 8005494: 6ebb ldr r3, [r7, #104] @ 0x68 8005496: 2b00 cmp r3, #0 8005498: d101 bne.n 800549e { return 32U; 800549a: 2320 movs r3, #32 800549c: e003 b.n 80054a6 } return __builtin_clz(value); 800549e: 6ebb ldr r3, [r7, #104] @ 0x68 80054a0: fab3 f383 clz r3, r3 80054a4: b2db uxtb r3, r3 80054a6: f003 031f and.w r3, r3, #31 80054aa: 2201 movs r2, #1 80054ac: fa02 f303 lsl.w r3, r2, r3 80054b0: 687a ldr r2, [r7, #4] 80054b2: 6812 ldr r2, [r2, #0] 80054b4: 69d1 ldr r1, [r2, #28] 80054b6: 687a ldr r2, [r7, #4] 80054b8: 6812 ldr r2, [r2, #0] 80054ba: 430b orrs r3, r1 80054bc: 61d3 str r3, [r2, #28] #endif /* ADC_VER_V5_V90 */ } /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); 80054be: 687b ldr r3, [r7, #4] 80054c0: 6818 ldr r0, [r3, #0] 80054c2: 683b ldr r3, [r7, #0] 80054c4: 6859 ldr r1, [r3, #4] 80054c6: 683b ldr r3, [r7, #0] 80054c8: 681b ldr r3, [r3, #0] 80054ca: 461a mov r2, r3 80054cc: f7ff fbb7 bl 8004c3e /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 80054d0: 687b ldr r3, [r7, #4] 80054d2: 681b ldr r3, [r3, #0] 80054d4: 4618 mov r0, r3 80054d6: f7ff fcff bl 8004ed8 80054da: 67b8 str r0, [r7, #120] @ 0x78 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 80054dc: 687b ldr r3, [r7, #4] 80054de: 681b ldr r3, [r3, #0] 80054e0: 4618 mov r0, r3 80054e2: f7ff fd0c bl 8004efe 80054e6: 6778 str r0, [r7, #116] @ 0x74 if ((tmp_adc_is_conversion_on_going_regular == 0UL) 80054e8: 6fbb ldr r3, [r7, #120] @ 0x78 80054ea: 2b00 cmp r3, #0 80054ec: f040 80b8 bne.w 8005660 && (tmp_adc_is_conversion_on_going_injected == 0UL) 80054f0: 6f7b ldr r3, [r7, #116] @ 0x74 80054f2: 2b00 cmp r3, #0 80054f4: f040 80b4 bne.w 8005660 ) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); 80054f8: 687b ldr r3, [r7, #4] 80054fa: 6818 ldr r0, [r3, #0] 80054fc: 683b ldr r3, [r7, #0] 80054fe: 6819 ldr r1, [r3, #0] 8005500: 683b ldr r3, [r7, #0] 8005502: 689b ldr r3, [r3, #8] 8005504: 461a mov r2, r3 8005506: f7ff fbd9 bl 8004cbc tmpOffsetShifted = ADC3_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); } else #endif /* ADC_VER_V5_V90 */ { tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); 800550a: 4b30 ldr r3, [pc, #192] @ (80055cc ) 800550c: 681b ldr r3, [r3, #0] 800550e: f003 4370 and.w r3, r3, #4026531840 @ 0xf0000000 8005512: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8005516: d10b bne.n 8005530 8005518: 683b ldr r3, [r7, #0] 800551a: 695a ldr r2, [r3, #20] 800551c: 687b ldr r3, [r7, #4] 800551e: 681b ldr r3, [r3, #0] 8005520: 68db ldr r3, [r3, #12] 8005522: 089b lsrs r3, r3, #2 8005524: f003 0307 and.w r3, r3, #7 8005528: 005b lsls r3, r3, #1 800552a: fa02 f303 lsl.w r3, r2, r3 800552e: e01d b.n 800556c 8005530: 687b ldr r3, [r7, #4] 8005532: 681b ldr r3, [r3, #0] 8005534: 68db ldr r3, [r3, #12] 8005536: f003 0310 and.w r3, r3, #16 800553a: 2b00 cmp r3, #0 800553c: d10b bne.n 8005556 800553e: 683b ldr r3, [r7, #0] 8005540: 695a ldr r2, [r3, #20] 8005542: 687b ldr r3, [r7, #4] 8005544: 681b ldr r3, [r3, #0] 8005546: 68db ldr r3, [r3, #12] 8005548: 089b lsrs r3, r3, #2 800554a: f003 0307 and.w r3, r3, #7 800554e: 005b lsls r3, r3, #1 8005550: fa02 f303 lsl.w r3, r2, r3 8005554: e00a b.n 800556c 8005556: 683b ldr r3, [r7, #0] 8005558: 695a ldr r2, [r3, #20] 800555a: 687b ldr r3, [r7, #4] 800555c: 681b ldr r3, [r3, #0] 800555e: 68db ldr r3, [r3, #12] 8005560: 089b lsrs r3, r3, #2 8005562: f003 0304 and.w r3, r3, #4 8005566: 005b lsls r3, r3, #1 8005568: fa02 f303 lsl.w r3, r2, r3 800556c: 673b str r3, [r7, #112] @ 0x70 } if (sConfig->OffsetNumber != ADC_OFFSET_NONE) 800556e: 683b ldr r3, [r7, #0] 8005570: 691b ldr r3, [r3, #16] 8005572: 2b04 cmp r3, #4 8005574: d02c beq.n 80055d0 { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); 8005576: 687b ldr r3, [r7, #4] 8005578: 6818 ldr r0, [r3, #0] 800557a: 683b ldr r3, [r7, #0] 800557c: 6919 ldr r1, [r3, #16] 800557e: 683b ldr r3, [r7, #0] 8005580: 681a ldr r2, [r3, #0] 8005582: 6f3b ldr r3, [r7, #112] @ 0x70 8005584: f7ff faf4 bl 8004b70 else #endif /* ADC_VER_V5_V90 */ { assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation)); /* Set ADC selected offset signed saturation */ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); 8005588: 687b ldr r3, [r7, #4] 800558a: 6818 ldr r0, [r3, #0] 800558c: 683b ldr r3, [r7, #0] 800558e: 6919 ldr r1, [r3, #16] 8005590: 683b ldr r3, [r7, #0] 8005592: 7e5b ldrb r3, [r3, #25] 8005594: 2b01 cmp r3, #1 8005596: d102 bne.n 800559e 8005598: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 800559c: e000 b.n 80055a0 800559e: 2300 movs r3, #0 80055a0: 461a mov r2, r3 80055a2: f7ff fb1e bl 8004be2 assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift)); /* Set ADC selected offset right shift */ LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); 80055a6: 687b ldr r3, [r7, #4] 80055a8: 6818 ldr r0, [r3, #0] 80055aa: 683b ldr r3, [r7, #0] 80055ac: 6919 ldr r1, [r3, #16] 80055ae: 683b ldr r3, [r7, #0] 80055b0: 7e1b ldrb r3, [r3, #24] 80055b2: 2b01 cmp r3, #1 80055b4: d102 bne.n 80055bc 80055b6: f44f 6300 mov.w r3, #2048 @ 0x800 80055ba: e000 b.n 80055be 80055bc: 2300 movs r3, #0 80055be: 461a mov r2, r3 80055c0: f7ff faf6 bl 8004bb0 80055c4: e04c b.n 8005660 80055c6: bf00 nop 80055c8: 47ff0000 .word 0x47ff0000 80055cc: 5c001000 .word 0x5c001000 } } else #endif /* ADC_VER_V5_V90 */ { if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 80055d0: 687b ldr r3, [r7, #4] 80055d2: 681b ldr r3, [r3, #0] 80055d4: 6e1b ldr r3, [r3, #96] @ 0x60 80055d6: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 80055da: 683b ldr r3, [r7, #0] 80055dc: 681b ldr r3, [r3, #0] 80055de: 069b lsls r3, r3, #26 80055e0: 429a cmp r2, r3 80055e2: d107 bne.n 80055f4 { CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE); 80055e4: 687b ldr r3, [r7, #4] 80055e6: 681b ldr r3, [r3, #0] 80055e8: 6e1a ldr r2, [r3, #96] @ 0x60 80055ea: 687b ldr r3, [r7, #4] 80055ec: 681b ldr r3, [r3, #0] 80055ee: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 80055f2: 661a str r2, [r3, #96] @ 0x60 } if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 80055f4: 687b ldr r3, [r7, #4] 80055f6: 681b ldr r3, [r3, #0] 80055f8: 6e5b ldr r3, [r3, #100] @ 0x64 80055fa: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 80055fe: 683b ldr r3, [r7, #0] 8005600: 681b ldr r3, [r3, #0] 8005602: 069b lsls r3, r3, #26 8005604: 429a cmp r2, r3 8005606: d107 bne.n 8005618 { CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE); 8005608: 687b ldr r3, [r7, #4] 800560a: 681b ldr r3, [r3, #0] 800560c: 6e5a ldr r2, [r3, #100] @ 0x64 800560e: 687b ldr r3, [r7, #4] 8005610: 681b ldr r3, [r3, #0] 8005612: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8005616: 665a str r2, [r3, #100] @ 0x64 } if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8005618: 687b ldr r3, [r7, #4] 800561a: 681b ldr r3, [r3, #0] 800561c: 6e9b ldr r3, [r3, #104] @ 0x68 800561e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8005622: 683b ldr r3, [r7, #0] 8005624: 681b ldr r3, [r3, #0] 8005626: 069b lsls r3, r3, #26 8005628: 429a cmp r2, r3 800562a: d107 bne.n 800563c { CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE); 800562c: 687b ldr r3, [r7, #4] 800562e: 681b ldr r3, [r3, #0] 8005630: 6e9a ldr r2, [r3, #104] @ 0x68 8005632: 687b ldr r3, [r7, #4] 8005634: 681b ldr r3, [r3, #0] 8005636: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 800563a: 669a str r2, [r3, #104] @ 0x68 } if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 800563c: 687b ldr r3, [r7, #4] 800563e: 681b ldr r3, [r3, #0] 8005640: 6edb ldr r3, [r3, #108] @ 0x6c 8005642: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8005646: 683b ldr r3, [r7, #0] 8005648: 681b ldr r3, [r3, #0] 800564a: 069b lsls r3, r3, #26 800564c: 429a cmp r2, r3 800564e: d107 bne.n 8005660 { CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE); 8005650: 687b ldr r3, [r7, #4] 8005652: 681b ldr r3, [r3, #0] 8005654: 6eda ldr r2, [r3, #108] @ 0x6c 8005656: 687b ldr r3, [r7, #4] 8005658: 681b ldr r3, [r3, #0] 800565a: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 800565e: 66da str r2, [r3, #108] @ 0x6c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8005660: 687b ldr r3, [r7, #4] 8005662: 681b ldr r3, [r3, #0] 8005664: 4618 mov r0, r3 8005666: f7ff fbfd bl 8004e64 800566a: 4603 mov r3, r0 800566c: 2b00 cmp r3, #0 800566e: f040 8211 bne.w 8005a94 { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); 8005672: 687b ldr r3, [r7, #4] 8005674: 6818 ldr r0, [r3, #0] 8005676: 683b ldr r3, [r7, #0] 8005678: 6819 ldr r1, [r3, #0] 800567a: 683b ldr r3, [r7, #0] 800567c: 68db ldr r3, [r3, #12] 800567e: 461a mov r2, r3 8005680: f7ff fb48 bl 8004d14 /* Configuration of differential mode */ if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) 8005684: 683b ldr r3, [r7, #0] 8005686: 68db ldr r3, [r3, #12] 8005688: 4aa1 ldr r2, [pc, #644] @ (8005910 ) 800568a: 4293 cmp r3, r2 800568c: f040 812e bne.w 80058ec { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ LL_ADC_SetChannelSamplingTime(hadc->Instance, 8005690: 687b ldr r3, [r7, #4] 8005692: 6818 ldr r0, [r3, #0] (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8005694: 683b ldr r3, [r7, #0] 8005696: 681b ldr r3, [r3, #0] 8005698: f3c3 0313 ubfx r3, r3, #0, #20 800569c: 2b00 cmp r3, #0 800569e: d10b bne.n 80056b8 80056a0: 683b ldr r3, [r7, #0] 80056a2: 681b ldr r3, [r3, #0] 80056a4: 0e9b lsrs r3, r3, #26 80056a6: 3301 adds r3, #1 80056a8: f003 031f and.w r3, r3, #31 80056ac: 2b09 cmp r3, #9 80056ae: bf94 ite ls 80056b0: 2301 movls r3, #1 80056b2: 2300 movhi r3, #0 80056b4: b2db uxtb r3, r3 80056b6: e019 b.n 80056ec 80056b8: 683b ldr r3, [r7, #0] 80056ba: 681b ldr r3, [r3, #0] 80056bc: 65bb str r3, [r7, #88] @ 0x58 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80056be: 6dbb ldr r3, [r7, #88] @ 0x58 80056c0: fa93 f3a3 rbit r3, r3 80056c4: 657b str r3, [r7, #84] @ 0x54 return result; 80056c6: 6d7b ldr r3, [r7, #84] @ 0x54 80056c8: 65fb str r3, [r7, #92] @ 0x5c if (value == 0U) 80056ca: 6dfb ldr r3, [r7, #92] @ 0x5c 80056cc: 2b00 cmp r3, #0 80056ce: d101 bne.n 80056d4 return 32U; 80056d0: 2320 movs r3, #32 80056d2: e003 b.n 80056dc return __builtin_clz(value); 80056d4: 6dfb ldr r3, [r7, #92] @ 0x5c 80056d6: fab3 f383 clz r3, r3 80056da: b2db uxtb r3, r3 80056dc: 3301 adds r3, #1 80056de: f003 031f and.w r3, r3, #31 80056e2: 2b09 cmp r3, #9 80056e4: bf94 ite ls 80056e6: 2301 movls r3, #1 80056e8: 2300 movhi r3, #0 80056ea: b2db uxtb r3, r3 LL_ADC_SetChannelSamplingTime(hadc->Instance, 80056ec: 2b00 cmp r3, #0 80056ee: d079 beq.n 80057e4 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 80056f0: 683b ldr r3, [r7, #0] 80056f2: 681b ldr r3, [r3, #0] 80056f4: f3c3 0313 ubfx r3, r3, #0, #20 80056f8: 2b00 cmp r3, #0 80056fa: d107 bne.n 800570c 80056fc: 683b ldr r3, [r7, #0] 80056fe: 681b ldr r3, [r3, #0] 8005700: 0e9b lsrs r3, r3, #26 8005702: 3301 adds r3, #1 8005704: 069b lsls r3, r3, #26 8005706: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 800570a: e015 b.n 8005738 800570c: 683b ldr r3, [r7, #0] 800570e: 681b ldr r3, [r3, #0] 8005710: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005712: 6cfb ldr r3, [r7, #76] @ 0x4c 8005714: fa93 f3a3 rbit r3, r3 8005718: 64bb str r3, [r7, #72] @ 0x48 return result; 800571a: 6cbb ldr r3, [r7, #72] @ 0x48 800571c: 653b str r3, [r7, #80] @ 0x50 if (value == 0U) 800571e: 6d3b ldr r3, [r7, #80] @ 0x50 8005720: 2b00 cmp r3, #0 8005722: d101 bne.n 8005728 return 32U; 8005724: 2320 movs r3, #32 8005726: e003 b.n 8005730 return __builtin_clz(value); 8005728: 6d3b ldr r3, [r7, #80] @ 0x50 800572a: fab3 f383 clz r3, r3 800572e: b2db uxtb r3, r3 8005730: 3301 adds r3, #1 8005732: 069b lsls r3, r3, #26 8005734: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8005738: 683b ldr r3, [r7, #0] 800573a: 681b ldr r3, [r3, #0] 800573c: f3c3 0313 ubfx r3, r3, #0, #20 8005740: 2b00 cmp r3, #0 8005742: d109 bne.n 8005758 8005744: 683b ldr r3, [r7, #0] 8005746: 681b ldr r3, [r3, #0] 8005748: 0e9b lsrs r3, r3, #26 800574a: 3301 adds r3, #1 800574c: f003 031f and.w r3, r3, #31 8005750: 2101 movs r1, #1 8005752: fa01 f303 lsl.w r3, r1, r3 8005756: e017 b.n 8005788 8005758: 683b ldr r3, [r7, #0] 800575a: 681b ldr r3, [r3, #0] 800575c: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800575e: 6c3b ldr r3, [r7, #64] @ 0x40 8005760: fa93 f3a3 rbit r3, r3 8005764: 63fb str r3, [r7, #60] @ 0x3c return result; 8005766: 6bfb ldr r3, [r7, #60] @ 0x3c 8005768: 647b str r3, [r7, #68] @ 0x44 if (value == 0U) 800576a: 6c7b ldr r3, [r7, #68] @ 0x44 800576c: 2b00 cmp r3, #0 800576e: d101 bne.n 8005774 return 32U; 8005770: 2320 movs r3, #32 8005772: e003 b.n 800577c return __builtin_clz(value); 8005774: 6c7b ldr r3, [r7, #68] @ 0x44 8005776: fab3 f383 clz r3, r3 800577a: b2db uxtb r3, r3 800577c: 3301 adds r3, #1 800577e: f003 031f and.w r3, r3, #31 8005782: 2101 movs r1, #1 8005784: fa01 f303 lsl.w r3, r1, r3 8005788: ea42 0103 orr.w r1, r2, r3 800578c: 683b ldr r3, [r7, #0] 800578e: 681b ldr r3, [r3, #0] 8005790: f3c3 0313 ubfx r3, r3, #0, #20 8005794: 2b00 cmp r3, #0 8005796: d10a bne.n 80057ae 8005798: 683b ldr r3, [r7, #0] 800579a: 681b ldr r3, [r3, #0] 800579c: 0e9b lsrs r3, r3, #26 800579e: 3301 adds r3, #1 80057a0: f003 021f and.w r2, r3, #31 80057a4: 4613 mov r3, r2 80057a6: 005b lsls r3, r3, #1 80057a8: 4413 add r3, r2 80057aa: 051b lsls r3, r3, #20 80057ac: e018 b.n 80057e0 80057ae: 683b ldr r3, [r7, #0] 80057b0: 681b ldr r3, [r3, #0] 80057b2: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80057b4: 6b7b ldr r3, [r7, #52] @ 0x34 80057b6: fa93 f3a3 rbit r3, r3 80057ba: 633b str r3, [r7, #48] @ 0x30 return result; 80057bc: 6b3b ldr r3, [r7, #48] @ 0x30 80057be: 63bb str r3, [r7, #56] @ 0x38 if (value == 0U) 80057c0: 6bbb ldr r3, [r7, #56] @ 0x38 80057c2: 2b00 cmp r3, #0 80057c4: d101 bne.n 80057ca return 32U; 80057c6: 2320 movs r3, #32 80057c8: e003 b.n 80057d2 return __builtin_clz(value); 80057ca: 6bbb ldr r3, [r7, #56] @ 0x38 80057cc: fab3 f383 clz r3, r3 80057d0: b2db uxtb r3, r3 80057d2: 3301 adds r3, #1 80057d4: f003 021f and.w r2, r3, #31 80057d8: 4613 mov r3, r2 80057da: 005b lsls r3, r3, #1 80057dc: 4413 add r3, r2 80057de: 051b lsls r3, r3, #20 LL_ADC_SetChannelSamplingTime(hadc->Instance, 80057e0: 430b orrs r3, r1 80057e2: e07e b.n 80058e2 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 80057e4: 683b ldr r3, [r7, #0] 80057e6: 681b ldr r3, [r3, #0] 80057e8: f3c3 0313 ubfx r3, r3, #0, #20 80057ec: 2b00 cmp r3, #0 80057ee: d107 bne.n 8005800 80057f0: 683b ldr r3, [r7, #0] 80057f2: 681b ldr r3, [r3, #0] 80057f4: 0e9b lsrs r3, r3, #26 80057f6: 3301 adds r3, #1 80057f8: 069b lsls r3, r3, #26 80057fa: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 80057fe: e015 b.n 800582c 8005800: 683b ldr r3, [r7, #0] 8005802: 681b ldr r3, [r3, #0] 8005804: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005806: 6abb ldr r3, [r7, #40] @ 0x28 8005808: fa93 f3a3 rbit r3, r3 800580c: 627b str r3, [r7, #36] @ 0x24 return result; 800580e: 6a7b ldr r3, [r7, #36] @ 0x24 8005810: 62fb str r3, [r7, #44] @ 0x2c if (value == 0U) 8005812: 6afb ldr r3, [r7, #44] @ 0x2c 8005814: 2b00 cmp r3, #0 8005816: d101 bne.n 800581c return 32U; 8005818: 2320 movs r3, #32 800581a: e003 b.n 8005824 return __builtin_clz(value); 800581c: 6afb ldr r3, [r7, #44] @ 0x2c 800581e: fab3 f383 clz r3, r3 8005822: b2db uxtb r3, r3 8005824: 3301 adds r3, #1 8005826: 069b lsls r3, r3, #26 8005828: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 800582c: 683b ldr r3, [r7, #0] 800582e: 681b ldr r3, [r3, #0] 8005830: f3c3 0313 ubfx r3, r3, #0, #20 8005834: 2b00 cmp r3, #0 8005836: d109 bne.n 800584c 8005838: 683b ldr r3, [r7, #0] 800583a: 681b ldr r3, [r3, #0] 800583c: 0e9b lsrs r3, r3, #26 800583e: 3301 adds r3, #1 8005840: f003 031f and.w r3, r3, #31 8005844: 2101 movs r1, #1 8005846: fa01 f303 lsl.w r3, r1, r3 800584a: e017 b.n 800587c 800584c: 683b ldr r3, [r7, #0] 800584e: 681b ldr r3, [r3, #0] 8005850: 61fb str r3, [r7, #28] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005852: 69fb ldr r3, [r7, #28] 8005854: fa93 f3a3 rbit r3, r3 8005858: 61bb str r3, [r7, #24] return result; 800585a: 69bb ldr r3, [r7, #24] 800585c: 623b str r3, [r7, #32] if (value == 0U) 800585e: 6a3b ldr r3, [r7, #32] 8005860: 2b00 cmp r3, #0 8005862: d101 bne.n 8005868 return 32U; 8005864: 2320 movs r3, #32 8005866: e003 b.n 8005870 return __builtin_clz(value); 8005868: 6a3b ldr r3, [r7, #32] 800586a: fab3 f383 clz r3, r3 800586e: b2db uxtb r3, r3 8005870: 3301 adds r3, #1 8005872: f003 031f and.w r3, r3, #31 8005876: 2101 movs r1, #1 8005878: fa01 f303 lsl.w r3, r1, r3 800587c: ea42 0103 orr.w r1, r2, r3 8005880: 683b ldr r3, [r7, #0] 8005882: 681b ldr r3, [r3, #0] 8005884: f3c3 0313 ubfx r3, r3, #0, #20 8005888: 2b00 cmp r3, #0 800588a: d10d bne.n 80058a8 800588c: 683b ldr r3, [r7, #0] 800588e: 681b ldr r3, [r3, #0] 8005890: 0e9b lsrs r3, r3, #26 8005892: 3301 adds r3, #1 8005894: f003 021f and.w r2, r3, #31 8005898: 4613 mov r3, r2 800589a: 005b lsls r3, r3, #1 800589c: 4413 add r3, r2 800589e: 3b1e subs r3, #30 80058a0: 051b lsls r3, r3, #20 80058a2: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 80058a6: e01b b.n 80058e0 80058a8: 683b ldr r3, [r7, #0] 80058aa: 681b ldr r3, [r3, #0] 80058ac: 613b str r3, [r7, #16] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80058ae: 693b ldr r3, [r7, #16] 80058b0: fa93 f3a3 rbit r3, r3 80058b4: 60fb str r3, [r7, #12] return result; 80058b6: 68fb ldr r3, [r7, #12] 80058b8: 617b str r3, [r7, #20] if (value == 0U) 80058ba: 697b ldr r3, [r7, #20] 80058bc: 2b00 cmp r3, #0 80058be: d101 bne.n 80058c4 return 32U; 80058c0: 2320 movs r3, #32 80058c2: e003 b.n 80058cc return __builtin_clz(value); 80058c4: 697b ldr r3, [r7, #20] 80058c6: fab3 f383 clz r3, r3 80058ca: b2db uxtb r3, r3 80058cc: 3301 adds r3, #1 80058ce: f003 021f and.w r2, r3, #31 80058d2: 4613 mov r3, r2 80058d4: 005b lsls r3, r3, #1 80058d6: 4413 add r3, r2 80058d8: 3b1e subs r3, #30 80058da: 051b lsls r3, r3, #20 80058dc: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 LL_ADC_SetChannelSamplingTime(hadc->Instance, 80058e0: 430b orrs r3, r1 80058e2: 683a ldr r2, [r7, #0] 80058e4: 6892 ldr r2, [r2, #8] 80058e6: 4619 mov r1, r3 80058e8: f7ff f9e8 bl 8004cbc /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 80058ec: 683b ldr r3, [r7, #0] 80058ee: 681b ldr r3, [r3, #0] 80058f0: 2b00 cmp r3, #0 80058f2: f280 80cf bge.w 8005a94 { /* Configuration of common ADC parameters */ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 80058f6: 687b ldr r3, [r7, #4] 80058f8: 681b ldr r3, [r3, #0] 80058fa: 4a06 ldr r2, [pc, #24] @ (8005914 ) 80058fc: 4293 cmp r3, r2 80058fe: d004 beq.n 800590a 8005900: 687b ldr r3, [r7, #4] 8005902: 681b ldr r3, [r3, #0] 8005904: 4a04 ldr r2, [pc, #16] @ (8005918 ) 8005906: 4293 cmp r3, r2 8005908: d10a bne.n 8005920 800590a: 4b04 ldr r3, [pc, #16] @ (800591c ) 800590c: e009 b.n 8005922 800590e: bf00 nop 8005910: 47ff0000 .word 0x47ff0000 8005914: 40022000 .word 0x40022000 8005918: 40022100 .word 0x40022100 800591c: 40022300 .word 0x40022300 8005920: 4b61 ldr r3, [pc, #388] @ (8005aa8 ) 8005922: 4618 mov r0, r3 8005924: f7ff f916 bl 8004b54 8005928: 66f8 str r0, [r7, #108] @ 0x6c /* Software is allowed to change common parameters only when all ADCs */ /* of the common group are disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 800592a: 687b ldr r3, [r7, #4] 800592c: 681b ldr r3, [r3, #0] 800592e: 4a5f ldr r2, [pc, #380] @ (8005aac ) 8005930: 4293 cmp r3, r2 8005932: d004 beq.n 800593e 8005934: 687b ldr r3, [r7, #4] 8005936: 681b ldr r3, [r3, #0] 8005938: 4a5d ldr r2, [pc, #372] @ (8005ab0 ) 800593a: 4293 cmp r3, r2 800593c: d10e bne.n 800595c 800593e: 485b ldr r0, [pc, #364] @ (8005aac ) 8005940: f7ff fa90 bl 8004e64 8005944: 4604 mov r4, r0 8005946: 485a ldr r0, [pc, #360] @ (8005ab0 ) 8005948: f7ff fa8c bl 8004e64 800594c: 4603 mov r3, r0 800594e: 4323 orrs r3, r4 8005950: 2b00 cmp r3, #0 8005952: bf0c ite eq 8005954: 2301 moveq r3, #1 8005956: 2300 movne r3, #0 8005958: b2db uxtb r3, r3 800595a: e008 b.n 800596e 800595c: 4855 ldr r0, [pc, #340] @ (8005ab4 ) 800595e: f7ff fa81 bl 8004e64 8005962: 4603 mov r3, r0 8005964: 2b00 cmp r3, #0 8005966: bf0c ite eq 8005968: 2301 moveq r3, #1 800596a: 2300 movne r3, #0 800596c: b2db uxtb r3, r3 800596e: 2b00 cmp r3, #0 8005970: d07d beq.n 8005a6e { /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 8005972: 683b ldr r3, [r7, #0] 8005974: 681b ldr r3, [r3, #0] 8005976: 4a50 ldr r2, [pc, #320] @ (8005ab8 ) 8005978: 4293 cmp r3, r2 800597a: d130 bne.n 80059de 800597c: 6efb ldr r3, [r7, #108] @ 0x6c 800597e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8005982: 2b00 cmp r3, #0 8005984: d12b bne.n 80059de { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8005986: 687b ldr r3, [r7, #4] 8005988: 681b ldr r3, [r3, #0] 800598a: 4a4a ldr r2, [pc, #296] @ (8005ab4 ) 800598c: 4293 cmp r3, r2 800598e: f040 8081 bne.w 8005a94 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); 8005992: 687b ldr r3, [r7, #4] 8005994: 681b ldr r3, [r3, #0] 8005996: 4a45 ldr r2, [pc, #276] @ (8005aac ) 8005998: 4293 cmp r3, r2 800599a: d004 beq.n 80059a6 800599c: 687b ldr r3, [r7, #4] 800599e: 681b ldr r3, [r3, #0] 80059a0: 4a43 ldr r2, [pc, #268] @ (8005ab0 ) 80059a2: 4293 cmp r3, r2 80059a4: d101 bne.n 80059aa 80059a6: 4a45 ldr r2, [pc, #276] @ (8005abc ) 80059a8: e000 b.n 80059ac 80059aa: 4a3f ldr r2, [pc, #252] @ (8005aa8 ) 80059ac: 6efb ldr r3, [r7, #108] @ 0x6c 80059ae: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 80059b2: 4619 mov r1, r3 80059b4: 4610 mov r0, r2 80059b6: f7ff f8ba bl 8004b2e /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 80059ba: 4b41 ldr r3, [pc, #260] @ (8005ac0 ) 80059bc: 681b ldr r3, [r3, #0] 80059be: 099b lsrs r3, r3, #6 80059c0: 4a40 ldr r2, [pc, #256] @ (8005ac4 ) 80059c2: fba2 2303 umull r2, r3, r2, r3 80059c6: 099b lsrs r3, r3, #6 80059c8: 3301 adds r3, #1 80059ca: 005b lsls r3, r3, #1 80059cc: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 80059ce: e002 b.n 80059d6 { wait_loop_index--; 80059d0: 68bb ldr r3, [r7, #8] 80059d2: 3b01 subs r3, #1 80059d4: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 80059d6: 68bb ldr r3, [r7, #8] 80059d8: 2b00 cmp r3, #0 80059da: d1f9 bne.n 80059d0 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 80059dc: e05a b.n 8005a94 } } } else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 80059de: 683b ldr r3, [r7, #0] 80059e0: 681b ldr r3, [r3, #0] 80059e2: 4a39 ldr r2, [pc, #228] @ (8005ac8 ) 80059e4: 4293 cmp r3, r2 80059e6: d11e bne.n 8005a26 80059e8: 6efb ldr r3, [r7, #108] @ 0x6c 80059ea: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80059ee: 2b00 cmp r3, #0 80059f0: d119 bne.n 8005a26 { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 80059f2: 687b ldr r3, [r7, #4] 80059f4: 681b ldr r3, [r3, #0] 80059f6: 4a2f ldr r2, [pc, #188] @ (8005ab4 ) 80059f8: 4293 cmp r3, r2 80059fa: d14b bne.n 8005a94 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); 80059fc: 687b ldr r3, [r7, #4] 80059fe: 681b ldr r3, [r3, #0] 8005a00: 4a2a ldr r2, [pc, #168] @ (8005aac ) 8005a02: 4293 cmp r3, r2 8005a04: d004 beq.n 8005a10 8005a06: 687b ldr r3, [r7, #4] 8005a08: 681b ldr r3, [r3, #0] 8005a0a: 4a29 ldr r2, [pc, #164] @ (8005ab0 ) 8005a0c: 4293 cmp r3, r2 8005a0e: d101 bne.n 8005a14 8005a10: 4a2a ldr r2, [pc, #168] @ (8005abc ) 8005a12: e000 b.n 8005a16 8005a14: 4a24 ldr r2, [pc, #144] @ (8005aa8 ) 8005a16: 6efb ldr r3, [r7, #108] @ 0x6c 8005a18: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8005a1c: 4619 mov r1, r3 8005a1e: 4610 mov r0, r2 8005a20: f7ff f885 bl 8004b2e if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 8005a24: e036 b.n 8005a94 } } else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) 8005a26: 683b ldr r3, [r7, #0] 8005a28: 681b ldr r3, [r3, #0] 8005a2a: 4a28 ldr r2, [pc, #160] @ (8005acc ) 8005a2c: 4293 cmp r3, r2 8005a2e: d131 bne.n 8005a94 8005a30: 6efb ldr r3, [r7, #108] @ 0x6c 8005a32: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8005a36: 2b00 cmp r3, #0 8005a38: d12c bne.n 8005a94 { if (ADC_VREFINT_INSTANCE(hadc)) 8005a3a: 687b ldr r3, [r7, #4] 8005a3c: 681b ldr r3, [r3, #0] 8005a3e: 4a1d ldr r2, [pc, #116] @ (8005ab4 ) 8005a40: 4293 cmp r3, r2 8005a42: d127 bne.n 8005a94 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); 8005a44: 687b ldr r3, [r7, #4] 8005a46: 681b ldr r3, [r3, #0] 8005a48: 4a18 ldr r2, [pc, #96] @ (8005aac ) 8005a4a: 4293 cmp r3, r2 8005a4c: d004 beq.n 8005a58 8005a4e: 687b ldr r3, [r7, #4] 8005a50: 681b ldr r3, [r3, #0] 8005a52: 4a17 ldr r2, [pc, #92] @ (8005ab0 ) 8005a54: 4293 cmp r3, r2 8005a56: d101 bne.n 8005a5c 8005a58: 4a18 ldr r2, [pc, #96] @ (8005abc ) 8005a5a: e000 b.n 8005a5e 8005a5c: 4a12 ldr r2, [pc, #72] @ (8005aa8 ) 8005a5e: 6efb ldr r3, [r7, #108] @ 0x6c 8005a60: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8005a64: 4619 mov r1, r3 8005a66: 4610 mov r0, r2 8005a68: f7ff f861 bl 8004b2e 8005a6c: e012 b.n 8005a94 /* enabled and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8005a6e: 687b ldr r3, [r7, #4] 8005a70: 6d5b ldr r3, [r3, #84] @ 0x54 8005a72: f043 0220 orr.w r2, r3, #32 8005a76: 687b ldr r3, [r7, #4] 8005a78: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8005a7a: 2301 movs r3, #1 8005a7c: f887 307f strb.w r3, [r7, #127] @ 0x7f 8005a80: e008 b.n 8005a94 /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8005a82: 687b ldr r3, [r7, #4] 8005a84: 6d5b ldr r3, [r3, #84] @ 0x54 8005a86: f043 0220 orr.w r2, r3, #32 8005a8a: 687b ldr r3, [r7, #4] 8005a8c: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8005a8e: 2301 movs r3, #1 8005a90: f887 307f strb.w r3, [r7, #127] @ 0x7f } /* Process unlocked */ __HAL_UNLOCK(hadc); 8005a94: 687b ldr r3, [r7, #4] 8005a96: 2200 movs r2, #0 8005a98: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 8005a9c: f897 307f ldrb.w r3, [r7, #127] @ 0x7f } 8005aa0: 4618 mov r0, r3 8005aa2: 3784 adds r7, #132 @ 0x84 8005aa4: 46bd mov sp, r7 8005aa6: bd90 pop {r4, r7, pc} 8005aa8: 58026300 .word 0x58026300 8005aac: 40022000 .word 0x40022000 8005ab0: 40022100 .word 0x40022100 8005ab4: 58026000 .word 0x58026000 8005ab8: cb840000 .word 0xcb840000 8005abc: 40022300 .word 0x40022300 8005ac0: 24000034 .word 0x24000034 8005ac4: 053e2d63 .word 0x053e2d63 8005ac8: c7520000 .word 0xc7520000 8005acc: cfb80000 .word 0xcfb80000 08005ad0 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { 8005ad0: b580 push {r7, lr} 8005ad2: b084 sub sp, #16 8005ad4: af00 add r7, sp, #0 8005ad6: 6078 str r0, [r7, #4] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8005ad8: 687b ldr r3, [r7, #4] 8005ada: 681b ldr r3, [r3, #0] 8005adc: 4618 mov r0, r3 8005ade: f7ff f9c1 bl 8004e64 8005ae2: 4603 mov r3, r0 8005ae4: 2b00 cmp r3, #0 8005ae6: d16e bne.n 8005bc6 { /* Check if conditions to enable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) 8005ae8: 687b ldr r3, [r7, #4] 8005aea: 681b ldr r3, [r3, #0] 8005aec: 689a ldr r2, [r3, #8] 8005aee: 4b38 ldr r3, [pc, #224] @ (8005bd0 ) 8005af0: 4013 ands r3, r2 8005af2: 2b00 cmp r3, #0 8005af4: d00d beq.n 8005b12 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8005af6: 687b ldr r3, [r7, #4] 8005af8: 6d5b ldr r3, [r3, #84] @ 0x54 8005afa: f043 0210 orr.w r2, r3, #16 8005afe: 687b ldr r3, [r7, #4] 8005b00: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8005b02: 687b ldr r3, [r7, #4] 8005b04: 6d9b ldr r3, [r3, #88] @ 0x58 8005b06: f043 0201 orr.w r2, r3, #1 8005b0a: 687b ldr r3, [r7, #4] 8005b0c: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8005b0e: 2301 movs r3, #1 8005b10: e05a b.n 8005bc8 } /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); 8005b12: 687b ldr r3, [r7, #4] 8005b14: 681b ldr r3, [r3, #0] 8005b16: 4618 mov r0, r3 8005b18: f7ff f97c bl 8004e14 /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); 8005b1c: f7fe ffa2 bl 8004a64 8005b20: 60f8 str r0, [r7, #12] /* Poll for ADC ready flag raised except case of multimode enabled and ADC slave selected. */ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8005b22: 687b ldr r3, [r7, #4] 8005b24: 681b ldr r3, [r3, #0] 8005b26: 4a2b ldr r2, [pc, #172] @ (8005bd4 ) 8005b28: 4293 cmp r3, r2 8005b2a: d004 beq.n 8005b36 8005b2c: 687b ldr r3, [r7, #4] 8005b2e: 681b ldr r3, [r3, #0] 8005b30: 4a29 ldr r2, [pc, #164] @ (8005bd8 ) 8005b32: 4293 cmp r3, r2 8005b34: d101 bne.n 8005b3a 8005b36: 4b29 ldr r3, [pc, #164] @ (8005bdc ) 8005b38: e000 b.n 8005b3c 8005b3a: 4b29 ldr r3, [pc, #164] @ (8005be0 ) 8005b3c: 4618 mov r0, r3 8005b3e: f7ff f90d bl 8004d5c 8005b42: 60b8 str r0, [r7, #8] if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8005b44: 687b ldr r3, [r7, #4] 8005b46: 681b ldr r3, [r3, #0] 8005b48: 4a23 ldr r2, [pc, #140] @ (8005bd8 ) 8005b4a: 4293 cmp r3, r2 8005b4c: d002 beq.n 8005b54 8005b4e: 687b ldr r3, [r7, #4] 8005b50: 681b ldr r3, [r3, #0] 8005b52: e000 b.n 8005b56 8005b54: 4b1f ldr r3, [pc, #124] @ (8005bd4 ) 8005b56: 687a ldr r2, [r7, #4] 8005b58: 6812 ldr r2, [r2, #0] 8005b5a: 4293 cmp r3, r2 8005b5c: d02c beq.n 8005bb8 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8005b5e: 68bb ldr r3, [r7, #8] 8005b60: 2b00 cmp r3, #0 8005b62: d130 bne.n 8005bc6 ) { while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8005b64: e028 b.n 8005bb8 The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ /* Note: Test of ADC enabled required due to hardware constraint to */ /* not enable ADC if already enabled. */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8005b66: 687b ldr r3, [r7, #4] 8005b68: 681b ldr r3, [r3, #0] 8005b6a: 4618 mov r0, r3 8005b6c: f7ff f97a bl 8004e64 8005b70: 4603 mov r3, r0 8005b72: 2b00 cmp r3, #0 8005b74: d104 bne.n 8005b80 { LL_ADC_Enable(hadc->Instance); 8005b76: 687b ldr r3, [r7, #4] 8005b78: 681b ldr r3, [r3, #0] 8005b7a: 4618 mov r0, r3 8005b7c: f7ff f94a bl 8004e14 } if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8005b80: f7fe ff70 bl 8004a64 8005b84: 4602 mov r2, r0 8005b86: 68fb ldr r3, [r7, #12] 8005b88: 1ad3 subs r3, r2, r3 8005b8a: 2b02 cmp r3, #2 8005b8c: d914 bls.n 8005bb8 { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8005b8e: 687b ldr r3, [r7, #4] 8005b90: 681b ldr r3, [r3, #0] 8005b92: 681b ldr r3, [r3, #0] 8005b94: f003 0301 and.w r3, r3, #1 8005b98: 2b01 cmp r3, #1 8005b9a: d00d beq.n 8005bb8 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8005b9c: 687b ldr r3, [r7, #4] 8005b9e: 6d5b ldr r3, [r3, #84] @ 0x54 8005ba0: f043 0210 orr.w r2, r3, #16 8005ba4: 687b ldr r3, [r7, #4] 8005ba6: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8005ba8: 687b ldr r3, [r7, #4] 8005baa: 6d9b ldr r3, [r3, #88] @ 0x58 8005bac: f043 0201 orr.w r2, r3, #1 8005bb0: 687b ldr r3, [r7, #4] 8005bb2: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8005bb4: 2301 movs r3, #1 8005bb6: e007 b.n 8005bc8 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8005bb8: 687b ldr r3, [r7, #4] 8005bba: 681b ldr r3, [r3, #0] 8005bbc: 681b ldr r3, [r3, #0] 8005bbe: f003 0301 and.w r3, r3, #1 8005bc2: 2b01 cmp r3, #1 8005bc4: d1cf bne.n 8005b66 } } } /* Return HAL status */ return HAL_OK; 8005bc6: 2300 movs r3, #0 } 8005bc8: 4618 mov r0, r3 8005bca: 3710 adds r7, #16 8005bcc: 46bd mov sp, r7 8005bce: bd80 pop {r7, pc} 8005bd0: 8000003f .word 0x8000003f 8005bd4: 40022000 .word 0x40022000 8005bd8: 40022100 .word 0x40022100 8005bdc: 40022300 .word 0x40022300 8005be0: 58026300 .word 0x58026300 08005be4 : * stopped. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { 8005be4: b580 push {r7, lr} 8005be6: b084 sub sp, #16 8005be8: af00 add r7, sp, #0 8005bea: 6078 str r0, [r7, #4] uint32_t tickstart; const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); 8005bec: 687b ldr r3, [r7, #4] 8005bee: 681b ldr r3, [r3, #0] 8005bf0: 4618 mov r0, r3 8005bf2: f7ff f94a bl 8004e8a 8005bf6: 60f8 str r0, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) 8005bf8: 687b ldr r3, [r7, #4] 8005bfa: 681b ldr r3, [r3, #0] 8005bfc: 4618 mov r0, r3 8005bfe: f7ff f931 bl 8004e64 8005c02: 4603 mov r3, r0 8005c04: 2b00 cmp r3, #0 8005c06: d047 beq.n 8005c98 && (tmp_adc_is_disable_on_going == 0UL) 8005c08: 68fb ldr r3, [r7, #12] 8005c0a: 2b00 cmp r3, #0 8005c0c: d144 bne.n 8005c98 ) { /* Check if conditions to disable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) 8005c0e: 687b ldr r3, [r7, #4] 8005c10: 681b ldr r3, [r3, #0] 8005c12: 689b ldr r3, [r3, #8] 8005c14: f003 030d and.w r3, r3, #13 8005c18: 2b01 cmp r3, #1 8005c1a: d10c bne.n 8005c36 { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); 8005c1c: 687b ldr r3, [r7, #4] 8005c1e: 681b ldr r3, [r3, #0] 8005c20: 4618 mov r0, r3 8005c22: f7ff f90b bl 8004e3c __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); 8005c26: 687b ldr r3, [r7, #4] 8005c28: 681b ldr r3, [r3, #0] 8005c2a: 2203 movs r2, #3 8005c2c: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); 8005c2e: f7fe ff19 bl 8004a64 8005c32: 60b8 str r0, [r7, #8] while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8005c34: e029 b.n 8005c8a SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8005c36: 687b ldr r3, [r7, #4] 8005c38: 6d5b ldr r3, [r3, #84] @ 0x54 8005c3a: f043 0210 orr.w r2, r3, #16 8005c3e: 687b ldr r3, [r7, #4] 8005c40: 655a str r2, [r3, #84] @ 0x54 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8005c42: 687b ldr r3, [r7, #4] 8005c44: 6d9b ldr r3, [r3, #88] @ 0x58 8005c46: f043 0201 orr.w r2, r3, #1 8005c4a: 687b ldr r3, [r7, #4] 8005c4c: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8005c4e: 2301 movs r3, #1 8005c50: e023 b.n 8005c9a { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8005c52: f7fe ff07 bl 8004a64 8005c56: 4602 mov r2, r0 8005c58: 68bb ldr r3, [r7, #8] 8005c5a: 1ad3 subs r3, r2, r3 8005c5c: 2b02 cmp r3, #2 8005c5e: d914 bls.n 8005c8a { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8005c60: 687b ldr r3, [r7, #4] 8005c62: 681b ldr r3, [r3, #0] 8005c64: 689b ldr r3, [r3, #8] 8005c66: f003 0301 and.w r3, r3, #1 8005c6a: 2b00 cmp r3, #0 8005c6c: d00d beq.n 8005c8a { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8005c6e: 687b ldr r3, [r7, #4] 8005c70: 6d5b ldr r3, [r3, #84] @ 0x54 8005c72: f043 0210 orr.w r2, r3, #16 8005c76: 687b ldr r3, [r7, #4] 8005c78: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8005c7a: 687b ldr r3, [r7, #4] 8005c7c: 6d9b ldr r3, [r3, #88] @ 0x58 8005c7e: f043 0201 orr.w r2, r3, #1 8005c82: 687b ldr r3, [r7, #4] 8005c84: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8005c86: 2301 movs r3, #1 8005c88: e007 b.n 8005c9a while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8005c8a: 687b ldr r3, [r7, #4] 8005c8c: 681b ldr r3, [r3, #0] 8005c8e: 689b ldr r3, [r3, #8] 8005c90: f003 0301 and.w r3, r3, #1 8005c94: 2b00 cmp r3, #0 8005c96: d1dc bne.n 8005c52 } } } /* Return HAL status */ return HAL_OK; 8005c98: 2300 movs r3, #0 } 8005c9a: 4618 mov r0, r3 8005c9c: 3710 adds r7, #16 8005c9e: 46bd mov sp, r7 8005ca0: bd80 pop {r7, pc} 08005ca2 : * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 8005ca2: b580 push {r7, lr} 8005ca4: b084 sub sp, #16 8005ca6: af00 add r7, sp, #0 8005ca8: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8005caa: 687b ldr r3, [r7, #4] 8005cac: 6b9b ldr r3, [r3, #56] @ 0x38 8005cae: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) 8005cb0: 68fb ldr r3, [r7, #12] 8005cb2: 6d5b ldr r3, [r3, #84] @ 0x54 8005cb4: f003 0350 and.w r3, r3, #80 @ 0x50 8005cb8: 2b00 cmp r3, #0 8005cba: d14b bne.n 8005d54 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8005cbc: 68fb ldr r3, [r7, #12] 8005cbe: 6d5b ldr r3, [r3, #84] @ 0x54 8005cc0: f443 7200 orr.w r2, r3, #512 @ 0x200 8005cc4: 68fb ldr r3, [r7, #12] 8005cc6: 655a str r2, [r3, #84] @ 0x54 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ /* Is it the end of the regular sequence ? */ if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) 8005cc8: 68fb ldr r3, [r7, #12] 8005cca: 681b ldr r3, [r3, #0] 8005ccc: 681b ldr r3, [r3, #0] 8005cce: f003 0308 and.w r3, r3, #8 8005cd2: 2b00 cmp r3, #0 8005cd4: d021 beq.n 8005d1a { /* Are conversions software-triggered ? */ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) 8005cd6: 68fb ldr r3, [r7, #12] 8005cd8: 681b ldr r3, [r3, #0] 8005cda: 4618 mov r0, r3 8005cdc: f7fe ff9c bl 8004c18 8005ce0: 4603 mov r3, r0 8005ce2: 2b00 cmp r3, #0 8005ce4: d032 beq.n 8005d4c { /* Is CONT bit set ? */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) 8005ce6: 68fb ldr r3, [r7, #12] 8005ce8: 681b ldr r3, [r3, #0] 8005cea: 68db ldr r3, [r3, #12] 8005cec: f403 5300 and.w r3, r3, #8192 @ 0x2000 8005cf0: 2b00 cmp r3, #0 8005cf2: d12b bne.n 8005d4c { /* CONT bit is not set, no more conversions expected */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8005cf4: 68fb ldr r3, [r7, #12] 8005cf6: 6d5b ldr r3, [r3, #84] @ 0x54 8005cf8: f423 7280 bic.w r2, r3, #256 @ 0x100 8005cfc: 68fb ldr r3, [r7, #12] 8005cfe: 655a str r2, [r3, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 8005d00: 68fb ldr r3, [r7, #12] 8005d02: 6d5b ldr r3, [r3, #84] @ 0x54 8005d04: f403 5380 and.w r3, r3, #4096 @ 0x1000 8005d08: 2b00 cmp r3, #0 8005d0a: d11f bne.n 8005d4c { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8005d0c: 68fb ldr r3, [r7, #12] 8005d0e: 6d5b ldr r3, [r3, #84] @ 0x54 8005d10: f043 0201 orr.w r2, r3, #1 8005d14: 68fb ldr r3, [r7, #12] 8005d16: 655a str r2, [r3, #84] @ 0x54 8005d18: e018 b.n 8005d4c } else { /* DMA End of Transfer interrupt was triggered but conversions sequence is not over. If DMACFG is set to 0, conversions are stopped. */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL) 8005d1a: 68fb ldr r3, [r7, #12] 8005d1c: 681b ldr r3, [r3, #0] 8005d1e: 68db ldr r3, [r3, #12] 8005d20: f003 0303 and.w r3, r3, #3 8005d24: 2b00 cmp r3, #0 8005d26: d111 bne.n 8005d4c { /* DMACFG bit is not set, conversions are stopped. */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8005d28: 68fb ldr r3, [r7, #12] 8005d2a: 6d5b ldr r3, [r3, #84] @ 0x54 8005d2c: f423 7280 bic.w r2, r3, #256 @ 0x100 8005d30: 68fb ldr r3, [r7, #12] 8005d32: 655a str r2, [r3, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 8005d34: 68fb ldr r3, [r7, #12] 8005d36: 6d5b ldr r3, [r3, #84] @ 0x54 8005d38: f403 5380 and.w r3, r3, #4096 @ 0x1000 8005d3c: 2b00 cmp r3, #0 8005d3e: d105 bne.n 8005d4c { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8005d40: 68fb ldr r3, [r7, #12] 8005d42: 6d5b ldr r3, [r3, #84] @ 0x54 8005d44: f043 0201 orr.w r2, r3, #1 8005d48: 68fb ldr r3, [r7, #12] 8005d4a: 655a str r2, [r3, #84] @ 0x54 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 8005d4c: 68f8 ldr r0, [r7, #12] 8005d4e: f7fb fc27 bl 80015a0 { /* Call ADC DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } } 8005d52: e00e b.n 8005d72 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) 8005d54: 68fb ldr r3, [r7, #12] 8005d56: 6d5b ldr r3, [r3, #84] @ 0x54 8005d58: f003 0310 and.w r3, r3, #16 8005d5c: 2b00 cmp r3, #0 8005d5e: d003 beq.n 8005d68 HAL_ADC_ErrorCallback(hadc); 8005d60: 68f8 ldr r0, [r7, #12] 8005d62: f7ff fb4f bl 8005404 } 8005d66: e004 b.n 8005d72 hadc->DMA_Handle->XferErrorCallback(hdma); 8005d68: 68fb ldr r3, [r7, #12] 8005d6a: 6cdb ldr r3, [r3, #76] @ 0x4c 8005d6c: 6cdb ldr r3, [r3, #76] @ 0x4c 8005d6e: 6878 ldr r0, [r7, #4] 8005d70: 4798 blx r3 } 8005d72: bf00 nop 8005d74: 3710 adds r7, #16 8005d76: 46bd mov sp, r7 8005d78: bd80 pop {r7, pc} 08005d7a : * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 8005d7a: b580 push {r7, lr} 8005d7c: b084 sub sp, #16 8005d7e: af00 add r7, sp, #0 8005d80: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8005d82: 687b ldr r3, [r7, #4] 8005d84: 6b9b ldr r3, [r3, #56] @ 0x38 8005d86: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 8005d88: 68f8 ldr r0, [r7, #12] 8005d8a: f7ff fb31 bl 80053f0 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8005d8e: bf00 nop 8005d90: 3710 adds r7, #16 8005d92: 46bd mov sp, r7 8005d94: bd80 pop {r7, pc} 08005d96 : * @brief DMA error callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 8005d96: b580 push {r7, lr} 8005d98: b084 sub sp, #16 8005d9a: af00 add r7, sp, #0 8005d9c: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8005d9e: 687b ldr r3, [r7, #4] 8005da0: 6b9b ldr r3, [r3, #56] @ 0x38 8005da2: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 8005da4: 68fb ldr r3, [r7, #12] 8005da6: 6d5b ldr r3, [r3, #84] @ 0x54 8005da8: f043 0240 orr.w r2, r3, #64 @ 0x40 8005dac: 68fb ldr r3, [r7, #12] 8005dae: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 8005db0: 68fb ldr r3, [r7, #12] 8005db2: 6d9b ldr r3, [r3, #88] @ 0x58 8005db4: f043 0204 orr.w r2, r3, #4 8005db8: 68fb ldr r3, [r7, #12] 8005dba: 659a str r2, [r3, #88] @ 0x58 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 8005dbc: 68f8 ldr r0, [r7, #12] 8005dbe: f7ff fb21 bl 8005404 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8005dc2: bf00 nop 8005dc4: 3710 adds r7, #16 8005dc6: 46bd mov sp, r7 8005dc8: bd80 pop {r7, pc} ... 08005dcc : * stopped. * @param hadc ADC handle * @retval None. */ void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc) { 8005dcc: b580 push {r7, lr} 8005dce: b084 sub sp, #16 8005dd0: af00 add r7, sp, #0 8005dd2: 6078 str r0, [r7, #4] uint32_t freq; if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc)) 8005dd4: 687b ldr r3, [r7, #4] 8005dd6: 681b ldr r3, [r3, #0] 8005dd8: 4a7a ldr r2, [pc, #488] @ (8005fc4 ) 8005dda: 4293 cmp r3, r2 8005ddc: d004 beq.n 8005de8 8005dde: 687b ldr r3, [r7, #4] 8005de0: 681b ldr r3, [r3, #0] 8005de2: 4a79 ldr r2, [pc, #484] @ (8005fc8 ) 8005de4: 4293 cmp r3, r2 8005de6: d109 bne.n 8005dfc 8005de8: 4b78 ldr r3, [pc, #480] @ (8005fcc ) 8005dea: 689b ldr r3, [r3, #8] 8005dec: f403 3340 and.w r3, r3, #196608 @ 0x30000 8005df0: 2b00 cmp r3, #0 8005df2: bf14 ite ne 8005df4: 2301 movne r3, #1 8005df6: 2300 moveq r3, #0 8005df8: b2db uxtb r3, r3 8005dfa: e008 b.n 8005e0e 8005dfc: 4b74 ldr r3, [pc, #464] @ (8005fd0 ) 8005dfe: 689b ldr r3, [r3, #8] 8005e00: f403 3340 and.w r3, r3, #196608 @ 0x30000 8005e04: 2b00 cmp r3, #0 8005e06: bf14 ite ne 8005e08: 2301 movne r3, #1 8005e0a: 2300 moveq r3, #0 8005e0c: b2db uxtb r3, r3 8005e0e: 2b00 cmp r3, #0 8005e10: d01c beq.n 8005e4c { freq = HAL_RCC_GetHCLKFreq(); 8005e12: f005 f957 bl 800b0c4 8005e16: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 8005e18: 687b ldr r3, [r7, #4] 8005e1a: 685b ldr r3, [r3, #4] 8005e1c: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8005e20: d010 beq.n 8005e44 8005e22: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8005e26: d873 bhi.n 8005f10 8005e28: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8005e2c: d002 beq.n 8005e34 8005e2e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8005e32: d16d bne.n 8005f10 { case ADC_CLOCK_SYNC_PCLK_DIV1: case ADC_CLOCK_SYNC_PCLK_DIV2: freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos); 8005e34: 687b ldr r3, [r7, #4] 8005e36: 685b ldr r3, [r3, #4] 8005e38: 0c1b lsrs r3, r3, #16 8005e3a: 68fa ldr r2, [r7, #12] 8005e3c: fbb2 f3f3 udiv r3, r2, r3 8005e40: 60fb str r3, [r7, #12] break; 8005e42: e068 b.n 8005f16 case ADC_CLOCK_SYNC_PCLK_DIV4: freq /= 4UL; 8005e44: 68fb ldr r3, [r7, #12] 8005e46: 089b lsrs r3, r3, #2 8005e48: 60fb str r3, [r7, #12] break; 8005e4a: e064 b.n 8005f16 break; } } else { freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC); 8005e4c: f44f 2000 mov.w r0, #524288 @ 0x80000 8005e50: f04f 0100 mov.w r1, #0 8005e54: f006 fbc2 bl 800c5dc 8005e58: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 8005e5a: 687b ldr r3, [r7, #4] 8005e5c: 685b ldr r3, [r3, #4] 8005e5e: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 8005e62: d051 beq.n 8005f08 8005e64: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 8005e68: d854 bhi.n 8005f14 8005e6a: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 8005e6e: d047 beq.n 8005f00 8005e70: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 8005e74: d84e bhi.n 8005f14 8005e76: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 8005e7a: d03d beq.n 8005ef8 8005e7c: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 8005e80: d848 bhi.n 8005f14 8005e82: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8005e86: d033 beq.n 8005ef0 8005e88: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8005e8c: d842 bhi.n 8005f14 8005e8e: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 8005e92: d029 beq.n 8005ee8 8005e94: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 8005e98: d83c bhi.n 8005f14 8005e9a: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 8005e9e: d01a beq.n 8005ed6 8005ea0: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 8005ea4: d836 bhi.n 8005f14 8005ea6: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 8005eaa: d014 beq.n 8005ed6 8005eac: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 8005eb0: d830 bhi.n 8005f14 8005eb2: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8005eb6: d00e beq.n 8005ed6 8005eb8: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8005ebc: d82a bhi.n 8005f14 8005ebe: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8005ec2: d008 beq.n 8005ed6 8005ec4: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8005ec8: d824 bhi.n 8005f14 8005eca: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8005ece: d002 beq.n 8005ed6 8005ed0: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 8005ed4: d11e bne.n 8005f14 case ADC_CLOCK_ASYNC_DIV4: case ADC_CLOCK_ASYNC_DIV6: case ADC_CLOCK_ASYNC_DIV8: case ADC_CLOCK_ASYNC_DIV10: case ADC_CLOCK_ASYNC_DIV12: freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL); 8005ed6: 687b ldr r3, [r7, #4] 8005ed8: 685b ldr r3, [r3, #4] 8005eda: 0c9b lsrs r3, r3, #18 8005edc: 005b lsls r3, r3, #1 8005ede: 68fa ldr r2, [r7, #12] 8005ee0: fbb2 f3f3 udiv r3, r2, r3 8005ee4: 60fb str r3, [r7, #12] break; 8005ee6: e016 b.n 8005f16 case ADC_CLOCK_ASYNC_DIV16: freq /= 16UL; 8005ee8: 68fb ldr r3, [r7, #12] 8005eea: 091b lsrs r3, r3, #4 8005eec: 60fb str r3, [r7, #12] break; 8005eee: e012 b.n 8005f16 case ADC_CLOCK_ASYNC_DIV32: freq /= 32UL; 8005ef0: 68fb ldr r3, [r7, #12] 8005ef2: 095b lsrs r3, r3, #5 8005ef4: 60fb str r3, [r7, #12] break; 8005ef6: e00e b.n 8005f16 case ADC_CLOCK_ASYNC_DIV64: freq /= 64UL; 8005ef8: 68fb ldr r3, [r7, #12] 8005efa: 099b lsrs r3, r3, #6 8005efc: 60fb str r3, [r7, #12] break; 8005efe: e00a b.n 8005f16 case ADC_CLOCK_ASYNC_DIV128: freq /= 128UL; 8005f00: 68fb ldr r3, [r7, #12] 8005f02: 09db lsrs r3, r3, #7 8005f04: 60fb str r3, [r7, #12] break; 8005f06: e006 b.n 8005f16 case ADC_CLOCK_ASYNC_DIV256: freq /= 256UL; 8005f08: 68fb ldr r3, [r7, #12] 8005f0a: 0a1b lsrs r3, r3, #8 8005f0c: 60fb str r3, [r7, #12] break; 8005f0e: e002 b.n 8005f16 break; 8005f10: bf00 nop 8005f12: e000 b.n 8005f16 default: break; 8005f14: bf00 nop else /* if(freq > 25000000UL) */ { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } #else if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */ 8005f16: f7fe fdb1 bl 8004a7c 8005f1a: 4603 mov r3, r0 8005f1c: f241 0203 movw r2, #4099 @ 0x1003 8005f20: 4293 cmp r3, r2 8005f22: d815 bhi.n 8005f50 { if (freq > 20000000UL) 8005f24: 68fb ldr r3, [r7, #12] 8005f26: 4a2b ldr r2, [pc, #172] @ (8005fd4 ) 8005f28: 4293 cmp r3, r2 8005f2a: d908 bls.n 8005f3e { SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 8005f2c: 687b ldr r3, [r7, #4] 8005f2e: 681b ldr r3, [r3, #0] 8005f30: 689a ldr r2, [r3, #8] 8005f32: 687b ldr r3, [r7, #4] 8005f34: 681b ldr r3, [r3, #0] 8005f36: f442 7280 orr.w r2, r2, #256 @ 0x100 8005f3a: 609a str r2, [r3, #8] { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } } #endif /* ADC_VER_V5_3 */ } 8005f3c: e03e b.n 8005fbc CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 8005f3e: 687b ldr r3, [r7, #4] 8005f40: 681b ldr r3, [r3, #0] 8005f42: 689a ldr r2, [r3, #8] 8005f44: 687b ldr r3, [r7, #4] 8005f46: 681b ldr r3, [r3, #0] 8005f48: f422 7280 bic.w r2, r2, #256 @ 0x100 8005f4c: 609a str r2, [r3, #8] } 8005f4e: e035 b.n 8005fbc freq /= 2U; /* divider by 2 for Rev.V */ 8005f50: 68fb ldr r3, [r7, #12] 8005f52: 085b lsrs r3, r3, #1 8005f54: 60fb str r3, [r7, #12] if (freq <= 6250000UL) 8005f56: 68fb ldr r3, [r7, #12] 8005f58: 4a1f ldr r2, [pc, #124] @ (8005fd8 ) 8005f5a: 4293 cmp r3, r2 8005f5c: d808 bhi.n 8005f70 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL); 8005f5e: 687b ldr r3, [r7, #4] 8005f60: 681b ldr r3, [r3, #0] 8005f62: 689a ldr r2, [r3, #8] 8005f64: 687b ldr r3, [r7, #4] 8005f66: 681b ldr r3, [r3, #0] 8005f68: f422 7240 bic.w r2, r2, #768 @ 0x300 8005f6c: 609a str r2, [r3, #8] } 8005f6e: e025 b.n 8005fbc else if (freq <= 12500000UL) 8005f70: 68fb ldr r3, [r7, #12] 8005f72: 4a1a ldr r2, [pc, #104] @ (8005fdc ) 8005f74: 4293 cmp r3, r2 8005f76: d80a bhi.n 8005f8e MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0); 8005f78: 687b ldr r3, [r7, #4] 8005f7a: 681b ldr r3, [r3, #0] 8005f7c: 689b ldr r3, [r3, #8] 8005f7e: f423 7240 bic.w r2, r3, #768 @ 0x300 8005f82: 687b ldr r3, [r7, #4] 8005f84: 681b ldr r3, [r3, #0] 8005f86: f442 7280 orr.w r2, r2, #256 @ 0x100 8005f8a: 609a str r2, [r3, #8] } 8005f8c: e016 b.n 8005fbc else if (freq <= 25000000UL) 8005f8e: 68fb ldr r3, [r7, #12] 8005f90: 4a13 ldr r2, [pc, #76] @ (8005fe0 ) 8005f92: 4293 cmp r3, r2 8005f94: d80a bhi.n 8005fac MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1); 8005f96: 687b ldr r3, [r7, #4] 8005f98: 681b ldr r3, [r3, #0] 8005f9a: 689b ldr r3, [r3, #8] 8005f9c: f423 7240 bic.w r2, r3, #768 @ 0x300 8005fa0: 687b ldr r3, [r7, #4] 8005fa2: 681b ldr r3, [r3, #0] 8005fa4: f442 7200 orr.w r2, r2, #512 @ 0x200 8005fa8: 609a str r2, [r3, #8] } 8005faa: e007 b.n 8005fbc MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); 8005fac: 687b ldr r3, [r7, #4] 8005fae: 681b ldr r3, [r3, #0] 8005fb0: 689a ldr r2, [r3, #8] 8005fb2: 687b ldr r3, [r7, #4] 8005fb4: 681b ldr r3, [r3, #0] 8005fb6: f442 7240 orr.w r2, r2, #768 @ 0x300 8005fba: 609a str r2, [r3, #8] } 8005fbc: bf00 nop 8005fbe: 3710 adds r7, #16 8005fc0: 46bd mov sp, r7 8005fc2: bd80 pop {r7, pc} 8005fc4: 40022000 .word 0x40022000 8005fc8: 40022100 .word 0x40022100 8005fcc: 40022300 .word 0x40022300 8005fd0: 58026300 .word 0x58026300 8005fd4: 01312d00 .word 0x01312d00 8005fd8: 005f5e10 .word 0x005f5e10 8005fdc: 00bebc20 .word 0x00bebc20 8005fe0: 017d7840 .word 0x017d7840 08005fe4 : { 8005fe4: b480 push {r7} 8005fe6: b083 sub sp, #12 8005fe8: af00 add r7, sp, #0 8005fea: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8005fec: 687b ldr r3, [r7, #4] 8005fee: 689b ldr r3, [r3, #8] 8005ff0: f003 0301 and.w r3, r3, #1 8005ff4: 2b01 cmp r3, #1 8005ff6: d101 bne.n 8005ffc 8005ff8: 2301 movs r3, #1 8005ffa: e000 b.n 8005ffe 8005ffc: 2300 movs r3, #0 } 8005ffe: 4618 mov r0, r3 8006000: 370c adds r7, #12 8006002: 46bd mov sp, r7 8006004: f85d 7b04 ldr.w r7, [sp], #4 8006008: 4770 bx lr ... 0800600c : { 800600c: b480 push {r7} 800600e: b085 sub sp, #20 8006010: af00 add r7, sp, #0 8006012: 60f8 str r0, [r7, #12] 8006014: 60b9 str r1, [r7, #8] 8006016: 607a str r2, [r7, #4] MODIFY_REG(ADCx->CR, 8006018: 68fb ldr r3, [r7, #12] 800601a: 689a ldr r2, [r3, #8] 800601c: 4b09 ldr r3, [pc, #36] @ (8006044 ) 800601e: 4013 ands r3, r2 8006020: 68ba ldr r2, [r7, #8] 8006022: f402 3180 and.w r1, r2, #65536 @ 0x10000 8006026: 687a ldr r2, [r7, #4] 8006028: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 800602c: 430a orrs r2, r1 800602e: 4313 orrs r3, r2 8006030: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 8006034: 68fb ldr r3, [r7, #12] 8006036: 609a str r2, [r3, #8] } 8006038: bf00 nop 800603a: 3714 adds r7, #20 800603c: 46bd mov sp, r7 800603e: f85d 7b04 ldr.w r7, [sp], #4 8006042: 4770 bx lr 8006044: 3ffeffc0 .word 0x3ffeffc0 08006048 : { 8006048: b480 push {r7} 800604a: b083 sub sp, #12 800604c: af00 add r7, sp, #0 800604e: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); 8006050: 687b ldr r3, [r7, #4] 8006052: 689b ldr r3, [r3, #8] 8006054: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8006058: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800605c: d101 bne.n 8006062 800605e: 2301 movs r3, #1 8006060: e000 b.n 8006064 8006062: 2300 movs r3, #0 } 8006064: 4618 mov r0, r3 8006066: 370c adds r7, #12 8006068: 46bd mov sp, r7 800606a: f85d 7b04 ldr.w r7, [sp], #4 800606e: 4770 bx lr 08006070 : { 8006070: b480 push {r7} 8006072: b083 sub sp, #12 8006074: af00 add r7, sp, #0 8006076: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8006078: 687b ldr r3, [r7, #4] 800607a: 689b ldr r3, [r3, #8] 800607c: f003 0304 and.w r3, r3, #4 8006080: 2b04 cmp r3, #4 8006082: d101 bne.n 8006088 8006084: 2301 movs r3, #1 8006086: e000 b.n 800608a 8006088: 2300 movs r3, #0 } 800608a: 4618 mov r0, r3 800608c: 370c adds r7, #12 800608e: 46bd mov sp, r7 8006090: f85d 7b04 ldr.w r7, [sp], #4 8006094: 4770 bx lr ... 08006098 : * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff) { 8006098: b580 push {r7, lr} 800609a: b086 sub sp, #24 800609c: af00 add r7, sp, #0 800609e: 60f8 str r0, [r7, #12] 80060a0: 60b9 str r1, [r7, #8] 80060a2: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; 80060a4: 2300 movs r3, #0 80060a6: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Process locked */ __HAL_LOCK(hadc); 80060a8: 68fb ldr r3, [r7, #12] 80060aa: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 80060ae: 2b01 cmp r3, #1 80060b0: d101 bne.n 80060b6 80060b2: 2302 movs r3, #2 80060b4: e04c b.n 8006150 80060b6: 68fb ldr r3, [r7, #12] 80060b8: 2201 movs r2, #1 80060ba: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Calibration prerequisite: ADC must be disabled. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); 80060be: 68f8 ldr r0, [r7, #12] 80060c0: f7ff fd90 bl 8005be4 80060c4: 4603 mov r3, r0 80060c6: 75fb strb r3, [r7, #23] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 80060c8: 7dfb ldrb r3, [r7, #23] 80060ca: 2b00 cmp r3, #0 80060cc: d135 bne.n 800613a { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80060ce: 68fb ldr r3, [r7, #12] 80060d0: 6d5a ldr r2, [r3, #84] @ 0x54 80060d2: 4b21 ldr r3, [pc, #132] @ (8006158 ) 80060d4: 4013 ands r3, r2 80060d6: f043 0202 orr.w r2, r3, #2 80060da: 68fb ldr r3, [r7, #12] 80060dc: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Start ADC calibration in mode single-ended or differential */ LL_ADC_StartCalibration(hadc->Instance, CalibrationMode, SingleDiff); 80060de: 68fb ldr r3, [r7, #12] 80060e0: 681b ldr r3, [r3, #0] 80060e2: 687a ldr r2, [r7, #4] 80060e4: 68b9 ldr r1, [r7, #8] 80060e6: 4618 mov r0, r3 80060e8: f7ff ff90 bl 800600c /* Wait for calibration completion */ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 80060ec: e014 b.n 8006118 { wait_loop_index++; 80060ee: 693b ldr r3, [r7, #16] 80060f0: 3301 adds r3, #1 80060f2: 613b str r3, [r7, #16] if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) 80060f4: 693b ldr r3, [r7, #16] 80060f6: 4a19 ldr r2, [pc, #100] @ (800615c ) 80060f8: 4293 cmp r3, r2 80060fa: d30d bcc.n 8006118 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 80060fc: 68fb ldr r3, [r7, #12] 80060fe: 6d5b ldr r3, [r3, #84] @ 0x54 8006100: f023 0312 bic.w r3, r3, #18 8006104: f043 0210 orr.w r2, r3, #16 8006108: 68fb ldr r3, [r7, #12] 800610a: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800610c: 68fb ldr r3, [r7, #12] 800610e: 2200 movs r2, #0 8006110: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 8006114: 2301 movs r3, #1 8006116: e01b b.n 8006150 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 8006118: 68fb ldr r3, [r7, #12] 800611a: 681b ldr r3, [r3, #0] 800611c: 4618 mov r0, r3 800611e: f7ff ff93 bl 8006048 8006122: 4603 mov r3, r0 8006124: 2b00 cmp r3, #0 8006126: d1e2 bne.n 80060ee } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8006128: 68fb ldr r3, [r7, #12] 800612a: 6d5b ldr r3, [r3, #84] @ 0x54 800612c: f023 0303 bic.w r3, r3, #3 8006130: f043 0201 orr.w r2, r3, #1 8006134: 68fb ldr r3, [r7, #12] 8006136: 655a str r2, [r3, #84] @ 0x54 8006138: e005 b.n 8006146 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800613a: 68fb ldr r3, [r7, #12] 800613c: 6d5b ldr r3, [r3, #84] @ 0x54 800613e: f043 0210 orr.w r2, r3, #16 8006142: 68fb ldr r3, [r7, #12] 8006144: 655a str r2, [r3, #84] @ 0x54 /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } /* Process unlocked */ __HAL_UNLOCK(hadc); 8006146: 68fb ldr r3, [r7, #12] 8006148: 2200 movs r2, #0 800614a: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 800614e: 7dfb ldrb r3, [r7, #23] } 8006150: 4618 mov r0, r3 8006152: 3718 adds r7, #24 8006154: 46bd mov sp, r7 8006156: bd80 pop {r7, pc} 8006158: ffffeefd .word 0xffffeefd 800615c: 25c3f800 .word 0x25c3f800 08006160 : * @param hadc Master ADC handle * @param multimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { 8006160: b590 push {r4, r7, lr} 8006162: b09f sub sp, #124 @ 0x7c 8006164: af00 add r7, sp, #0 8006166: 6078 str r0, [r7, #4] 8006168: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800616a: 2300 movs r3, #0 800616c: f887 3077 strb.w r3, [r7, #119] @ 0x77 assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); 8006170: 687b ldr r3, [r7, #4] 8006172: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8006176: 2b01 cmp r3, #1 8006178: d101 bne.n 800617e 800617a: 2302 movs r3, #2 800617c: e0be b.n 80062fc 800617e: 687b ldr r3, [r7, #4] 8006180: 2201 movs r2, #1 8006182: f883 2050 strb.w r2, [r3, #80] @ 0x50 tmphadcSlave.State = HAL_ADC_STATE_RESET; 8006186: 2300 movs r3, #0 8006188: 65fb str r3, [r7, #92] @ 0x5c tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; 800618a: 2300 movs r3, #0 800618c: 663b str r3, [r7, #96] @ 0x60 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 800618e: 687b ldr r3, [r7, #4] 8006190: 681b ldr r3, [r3, #0] 8006192: 4a5c ldr r2, [pc, #368] @ (8006304 ) 8006194: 4293 cmp r3, r2 8006196: d102 bne.n 800619e 8006198: 4b5b ldr r3, [pc, #364] @ (8006308 ) 800619a: 60bb str r3, [r7, #8] 800619c: e001 b.n 80061a2 800619e: 2300 movs r3, #0 80061a0: 60bb str r3, [r7, #8] if (tmphadcSlave.Instance == NULL) 80061a2: 68bb ldr r3, [r7, #8] 80061a4: 2b00 cmp r3, #0 80061a6: d10b bne.n 80061c0 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80061a8: 687b ldr r3, [r7, #4] 80061aa: 6d5b ldr r3, [r3, #84] @ 0x54 80061ac: f043 0220 orr.w r2, r3, #32 80061b0: 687b ldr r3, [r7, #4] 80061b2: 655a str r2, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hadc); 80061b4: 687b ldr r3, [r7, #4] 80061b6: 2200 movs r2, #0 80061b8: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 80061bc: 2301 movs r3, #1 80061be: e09d b.n 80062fc /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DATA Format configuration */ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); 80061c0: 68bb ldr r3, [r7, #8] 80061c2: 4618 mov r0, r3 80061c4: f7ff ff54 bl 8006070 80061c8: 6738 str r0, [r7, #112] @ 0x70 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 80061ca: 687b ldr r3, [r7, #4] 80061cc: 681b ldr r3, [r3, #0] 80061ce: 4618 mov r0, r3 80061d0: f7ff ff4e bl 8006070 80061d4: 4603 mov r3, r0 80061d6: 2b00 cmp r3, #0 80061d8: d17f bne.n 80062da && (tmphadcSlave_conversion_on_going == 0UL)) 80061da: 6f3b ldr r3, [r7, #112] @ 0x70 80061dc: 2b00 cmp r3, #0 80061de: d17c bne.n 80062da { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); 80061e0: 687b ldr r3, [r7, #4] 80061e2: 681b ldr r3, [r3, #0] 80061e4: 4a47 ldr r2, [pc, #284] @ (8006304 ) 80061e6: 4293 cmp r3, r2 80061e8: d004 beq.n 80061f4 80061ea: 687b ldr r3, [r7, #4] 80061ec: 681b ldr r3, [r3, #0] 80061ee: 4a46 ldr r2, [pc, #280] @ (8006308 ) 80061f0: 4293 cmp r3, r2 80061f2: d101 bne.n 80061f8 80061f4: 4b45 ldr r3, [pc, #276] @ (800630c ) 80061f6: e000 b.n 80061fa 80061f8: 4b45 ldr r3, [pc, #276] @ (8006310 ) 80061fa: 66fb str r3, [r7, #108] @ 0x6c /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if (multimode->Mode != ADC_MODE_INDEPENDENT) 80061fc: 683b ldr r3, [r7, #0] 80061fe: 681b ldr r3, [r3, #0] 8006200: 2b00 cmp r3, #0 8006202: d039 beq.n 8006278 { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData); 8006204: 6efb ldr r3, [r7, #108] @ 0x6c 8006206: 689b ldr r3, [r3, #8] 8006208: f423 4240 bic.w r2, r3, #49152 @ 0xc000 800620c: 683b ldr r3, [r7, #0] 800620e: 685b ldr r3, [r3, #4] 8006210: 431a orrs r2, r3 8006212: 6efb ldr r3, [r7, #108] @ 0x6c 8006214: 609a str r2, [r3, #8] /* from 1 to 8 clock cycles for 12 bits */ /* from 1 to 6 clock cycles for 10 and 8 bits */ /* If a higher delay is selected, it will be clipped to maximum delay */ /* range */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8006216: 687b ldr r3, [r7, #4] 8006218: 681b ldr r3, [r3, #0] 800621a: 4a3a ldr r2, [pc, #232] @ (8006304 ) 800621c: 4293 cmp r3, r2 800621e: d004 beq.n 800622a 8006220: 687b ldr r3, [r7, #4] 8006222: 681b ldr r3, [r3, #0] 8006224: 4a38 ldr r2, [pc, #224] @ (8006308 ) 8006226: 4293 cmp r3, r2 8006228: d10e bne.n 8006248 800622a: 4836 ldr r0, [pc, #216] @ (8006304 ) 800622c: f7ff feda bl 8005fe4 8006230: 4604 mov r4, r0 8006232: 4835 ldr r0, [pc, #212] @ (8006308 ) 8006234: f7ff fed6 bl 8005fe4 8006238: 4603 mov r3, r0 800623a: 4323 orrs r3, r4 800623c: 2b00 cmp r3, #0 800623e: bf0c ite eq 8006240: 2301 moveq r3, #1 8006242: 2300 movne r3, #0 8006244: b2db uxtb r3, r3 8006246: e008 b.n 800625a 8006248: 4832 ldr r0, [pc, #200] @ (8006314 ) 800624a: f7ff fecb bl 8005fe4 800624e: 4603 mov r3, r0 8006250: 2b00 cmp r3, #0 8006252: bf0c ite eq 8006254: 2301 moveq r3, #1 8006256: 2300 movne r3, #0 8006258: b2db uxtb r3, r3 800625a: 2b00 cmp r3, #0 800625c: d047 beq.n 80062ee { MODIFY_REG(tmpADC_Common->CCR, 800625e: 6efb ldr r3, [r7, #108] @ 0x6c 8006260: 689a ldr r2, [r3, #8] 8006262: 4b2d ldr r3, [pc, #180] @ (8006318 ) 8006264: 4013 ands r3, r2 8006266: 683a ldr r2, [r7, #0] 8006268: 6811 ldr r1, [r2, #0] 800626a: 683a ldr r2, [r7, #0] 800626c: 6892 ldr r2, [r2, #8] 800626e: 430a orrs r2, r1 8006270: 431a orrs r2, r3 8006272: 6efb ldr r3, [r7, #108] @ 0x6c 8006274: 609a str r2, [r3, #8] if (multimode->Mode != ADC_MODE_INDEPENDENT) 8006276: e03a b.n 80062ee ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF); 8006278: 6efb ldr r3, [r7, #108] @ 0x6c 800627a: 689b ldr r3, [r3, #8] 800627c: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8006280: 6efb ldr r3, [r7, #108] @ 0x6c 8006282: 609a str r2, [r3, #8] /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8006284: 687b ldr r3, [r7, #4] 8006286: 681b ldr r3, [r3, #0] 8006288: 4a1e ldr r2, [pc, #120] @ (8006304 ) 800628a: 4293 cmp r3, r2 800628c: d004 beq.n 8006298 800628e: 687b ldr r3, [r7, #4] 8006290: 681b ldr r3, [r3, #0] 8006292: 4a1d ldr r2, [pc, #116] @ (8006308 ) 8006294: 4293 cmp r3, r2 8006296: d10e bne.n 80062b6 8006298: 481a ldr r0, [pc, #104] @ (8006304 ) 800629a: f7ff fea3 bl 8005fe4 800629e: 4604 mov r4, r0 80062a0: 4819 ldr r0, [pc, #100] @ (8006308 ) 80062a2: f7ff fe9f bl 8005fe4 80062a6: 4603 mov r3, r0 80062a8: 4323 orrs r3, r4 80062aa: 2b00 cmp r3, #0 80062ac: bf0c ite eq 80062ae: 2301 moveq r3, #1 80062b0: 2300 movne r3, #0 80062b2: b2db uxtb r3, r3 80062b4: e008 b.n 80062c8 80062b6: 4817 ldr r0, [pc, #92] @ (8006314 ) 80062b8: f7ff fe94 bl 8005fe4 80062bc: 4603 mov r3, r0 80062be: 2b00 cmp r3, #0 80062c0: bf0c ite eq 80062c2: 2301 moveq r3, #1 80062c4: 2300 movne r3, #0 80062c6: b2db uxtb r3, r3 80062c8: 2b00 cmp r3, #0 80062ca: d010 beq.n 80062ee { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); 80062cc: 6efb ldr r3, [r7, #108] @ 0x6c 80062ce: 689a ldr r2, [r3, #8] 80062d0: 4b11 ldr r3, [pc, #68] @ (8006318 ) 80062d2: 4013 ands r3, r2 80062d4: 6efa ldr r2, [r7, #108] @ 0x6c 80062d6: 6093 str r3, [r2, #8] if (multimode->Mode != ADC_MODE_INDEPENDENT) 80062d8: e009 b.n 80062ee /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80062da: 687b ldr r3, [r7, #4] 80062dc: 6d5b ldr r3, [r3, #84] @ 0x54 80062de: f043 0220 orr.w r2, r3, #32 80062e2: 687b ldr r3, [r7, #4] 80062e4: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 80062e6: 2301 movs r3, #1 80062e8: f887 3077 strb.w r3, [r7, #119] @ 0x77 80062ec: e000 b.n 80062f0 if (multimode->Mode != ADC_MODE_INDEPENDENT) 80062ee: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); 80062f0: 687b ldr r3, [r7, #4] 80062f2: 2200 movs r2, #0 80062f4: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 80062f8: f897 3077 ldrb.w r3, [r7, #119] @ 0x77 } 80062fc: 4618 mov r0, r3 80062fe: 377c adds r7, #124 @ 0x7c 8006300: 46bd mov sp, r7 8006302: bd90 pop {r4, r7, pc} 8006304: 40022000 .word 0x40022000 8006308: 40022100 .word 0x40022100 800630c: 40022300 .word 0x40022300 8006310: 58026300 .word 0x58026300 8006314: 58026000 .word 0x58026000 8006318: fffff0e0 .word 0xfffff0e0 0800631c <__NVIC_SetPriorityGrouping>: { 800631c: b480 push {r7} 800631e: b085 sub sp, #20 8006320: af00 add r7, sp, #0 8006322: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8006324: 687b ldr r3, [r7, #4] 8006326: f003 0307 and.w r3, r3, #7 800632a: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 800632c: 4b0b ldr r3, [pc, #44] @ (800635c <__NVIC_SetPriorityGrouping+0x40>) 800632e: 68db ldr r3, [r3, #12] 8006330: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8006332: 68ba ldr r2, [r7, #8] 8006334: f64f 03ff movw r3, #63743 @ 0xf8ff 8006338: 4013 ands r3, r2 800633a: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800633c: 68fb ldr r3, [r7, #12] 800633e: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8006340: 68bb ldr r3, [r7, #8] 8006342: 431a orrs r2, r3 reg_value = (reg_value | 8006344: 4b06 ldr r3, [pc, #24] @ (8006360 <__NVIC_SetPriorityGrouping+0x44>) 8006346: 4313 orrs r3, r2 8006348: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800634a: 4a04 ldr r2, [pc, #16] @ (800635c <__NVIC_SetPriorityGrouping+0x40>) 800634c: 68bb ldr r3, [r7, #8] 800634e: 60d3 str r3, [r2, #12] } 8006350: bf00 nop 8006352: 3714 adds r7, #20 8006354: 46bd mov sp, r7 8006356: f85d 7b04 ldr.w r7, [sp], #4 800635a: 4770 bx lr 800635c: e000ed00 .word 0xe000ed00 8006360: 05fa0000 .word 0x05fa0000 08006364 <__NVIC_GetPriorityGrouping>: { 8006364: b480 push {r7} 8006366: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8006368: 4b04 ldr r3, [pc, #16] @ (800637c <__NVIC_GetPriorityGrouping+0x18>) 800636a: 68db ldr r3, [r3, #12] 800636c: 0a1b lsrs r3, r3, #8 800636e: f003 0307 and.w r3, r3, #7 } 8006372: 4618 mov r0, r3 8006374: 46bd mov sp, r7 8006376: f85d 7b04 ldr.w r7, [sp], #4 800637a: 4770 bx lr 800637c: e000ed00 .word 0xe000ed00 08006380 <__NVIC_EnableIRQ>: { 8006380: b480 push {r7} 8006382: b083 sub sp, #12 8006384: af00 add r7, sp, #0 8006386: 4603 mov r3, r0 8006388: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 800638a: f9b7 3006 ldrsh.w r3, [r7, #6] 800638e: 2b00 cmp r3, #0 8006390: db0b blt.n 80063aa <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8006392: 88fb ldrh r3, [r7, #6] 8006394: f003 021f and.w r2, r3, #31 8006398: 4907 ldr r1, [pc, #28] @ (80063b8 <__NVIC_EnableIRQ+0x38>) 800639a: f9b7 3006 ldrsh.w r3, [r7, #6] 800639e: 095b lsrs r3, r3, #5 80063a0: 2001 movs r0, #1 80063a2: fa00 f202 lsl.w r2, r0, r2 80063a6: f841 2023 str.w r2, [r1, r3, lsl #2] } 80063aa: bf00 nop 80063ac: 370c adds r7, #12 80063ae: 46bd mov sp, r7 80063b0: f85d 7b04 ldr.w r7, [sp], #4 80063b4: 4770 bx lr 80063b6: bf00 nop 80063b8: e000e100 .word 0xe000e100 080063bc <__NVIC_SetPriority>: { 80063bc: b480 push {r7} 80063be: b083 sub sp, #12 80063c0: af00 add r7, sp, #0 80063c2: 4603 mov r3, r0 80063c4: 6039 str r1, [r7, #0] 80063c6: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 80063c8: f9b7 3006 ldrsh.w r3, [r7, #6] 80063cc: 2b00 cmp r3, #0 80063ce: db0a blt.n 80063e6 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80063d0: 683b ldr r3, [r7, #0] 80063d2: b2da uxtb r2, r3 80063d4: 490c ldr r1, [pc, #48] @ (8006408 <__NVIC_SetPriority+0x4c>) 80063d6: f9b7 3006 ldrsh.w r3, [r7, #6] 80063da: 0112 lsls r2, r2, #4 80063dc: b2d2 uxtb r2, r2 80063de: 440b add r3, r1 80063e0: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 80063e4: e00a b.n 80063fc <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80063e6: 683b ldr r3, [r7, #0] 80063e8: b2da uxtb r2, r3 80063ea: 4908 ldr r1, [pc, #32] @ (800640c <__NVIC_SetPriority+0x50>) 80063ec: 88fb ldrh r3, [r7, #6] 80063ee: f003 030f and.w r3, r3, #15 80063f2: 3b04 subs r3, #4 80063f4: 0112 lsls r2, r2, #4 80063f6: b2d2 uxtb r2, r2 80063f8: 440b add r3, r1 80063fa: 761a strb r2, [r3, #24] } 80063fc: bf00 nop 80063fe: 370c adds r7, #12 8006400: 46bd mov sp, r7 8006402: f85d 7b04 ldr.w r7, [sp], #4 8006406: 4770 bx lr 8006408: e000e100 .word 0xe000e100 800640c: e000ed00 .word 0xe000ed00 08006410 : { 8006410: b480 push {r7} 8006412: b089 sub sp, #36 @ 0x24 8006414: af00 add r7, sp, #0 8006416: 60f8 str r0, [r7, #12] 8006418: 60b9 str r1, [r7, #8] 800641a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800641c: 68fb ldr r3, [r7, #12] 800641e: f003 0307 and.w r3, r3, #7 8006422: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8006424: 69fb ldr r3, [r7, #28] 8006426: f1c3 0307 rsb r3, r3, #7 800642a: 2b04 cmp r3, #4 800642c: bf28 it cs 800642e: 2304 movcs r3, #4 8006430: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8006432: 69fb ldr r3, [r7, #28] 8006434: 3304 adds r3, #4 8006436: 2b06 cmp r3, #6 8006438: d902 bls.n 8006440 800643a: 69fb ldr r3, [r7, #28] 800643c: 3b03 subs r3, #3 800643e: e000 b.n 8006442 8006440: 2300 movs r3, #0 8006442: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8006444: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8006448: 69bb ldr r3, [r7, #24] 800644a: fa02 f303 lsl.w r3, r2, r3 800644e: 43da mvns r2, r3 8006450: 68bb ldr r3, [r7, #8] 8006452: 401a ands r2, r3 8006454: 697b ldr r3, [r7, #20] 8006456: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8006458: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800645c: 697b ldr r3, [r7, #20] 800645e: fa01 f303 lsl.w r3, r1, r3 8006462: 43d9 mvns r1, r3 8006464: 687b ldr r3, [r7, #4] 8006466: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8006468: 4313 orrs r3, r2 } 800646a: 4618 mov r0, r3 800646c: 3724 adds r7, #36 @ 0x24 800646e: 46bd mov sp, r7 8006470: f85d 7b04 ldr.w r7, [sp], #4 8006474: 4770 bx lr 08006476 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8006476: b580 push {r7, lr} 8006478: b082 sub sp, #8 800647a: af00 add r7, sp, #0 800647c: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800647e: 6878 ldr r0, [r7, #4] 8006480: f7ff ff4c bl 800631c <__NVIC_SetPriorityGrouping> } 8006484: bf00 nop 8006486: 3708 adds r7, #8 8006488: 46bd mov sp, r7 800648a: bd80 pop {r7, pc} 0800648c : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800648c: b580 push {r7, lr} 800648e: b086 sub sp, #24 8006490: af00 add r7, sp, #0 8006492: 4603 mov r3, r0 8006494: 60b9 str r1, [r7, #8] 8006496: 607a str r2, [r7, #4] 8006498: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800649a: f7ff ff63 bl 8006364 <__NVIC_GetPriorityGrouping> 800649e: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80064a0: 687a ldr r2, [r7, #4] 80064a2: 68b9 ldr r1, [r7, #8] 80064a4: 6978 ldr r0, [r7, #20] 80064a6: f7ff ffb3 bl 8006410 80064aa: 4602 mov r2, r0 80064ac: f9b7 300e ldrsh.w r3, [r7, #14] 80064b0: 4611 mov r1, r2 80064b2: 4618 mov r0, r3 80064b4: f7ff ff82 bl 80063bc <__NVIC_SetPriority> } 80064b8: bf00 nop 80064ba: 3718 adds r7, #24 80064bc: 46bd mov sp, r7 80064be: bd80 pop {r7, pc} 080064c0 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80064c0: b580 push {r7, lr} 80064c2: b082 sub sp, #8 80064c4: af00 add r7, sp, #0 80064c6: 4603 mov r3, r0 80064c8: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80064ca: f9b7 3006 ldrsh.w r3, [r7, #6] 80064ce: 4618 mov r0, r3 80064d0: f7ff ff56 bl 8006380 <__NVIC_EnableIRQ> } 80064d4: bf00 nop 80064d6: 3708 adds r7, #8 80064d8: 46bd mov sp, r7 80064da: bd80 pop {r7, pc} 080064dc : /** * @brief Disables the MPU * @retval None */ void HAL_MPU_Disable(void) { 80064dc: b480 push {r7} 80064de: af00 add r7, sp, #0 __ASM volatile ("dmb 0xF":::"memory"); 80064e0: f3bf 8f5f dmb sy } 80064e4: bf00 nop /* Make sure outstanding transfers are done */ __DMB(); /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 80064e6: 4b07 ldr r3, [pc, #28] @ (8006504 ) 80064e8: 6a5b ldr r3, [r3, #36] @ 0x24 80064ea: 4a06 ldr r2, [pc, #24] @ (8006504 ) 80064ec: f423 3380 bic.w r3, r3, #65536 @ 0x10000 80064f0: 6253 str r3, [r2, #36] @ 0x24 /* Disable the MPU and clear the control register*/ MPU->CTRL = 0; 80064f2: 4b05 ldr r3, [pc, #20] @ (8006508 ) 80064f4: 2200 movs r2, #0 80064f6: 605a str r2, [r3, #4] } 80064f8: bf00 nop 80064fa: 46bd mov sp, r7 80064fc: f85d 7b04 ldr.w r7, [sp], #4 8006500: 4770 bx lr 8006502: bf00 nop 8006504: e000ed00 .word 0xe000ed00 8006508: e000ed90 .word 0xe000ed90 0800650c : * @arg MPU_PRIVILEGED_DEFAULT * @arg MPU_HFNMI_PRIVDEF * @retval None */ void HAL_MPU_Enable(uint32_t MPU_Control) { 800650c: b480 push {r7} 800650e: b083 sub sp, #12 8006510: af00 add r7, sp, #0 8006512: 6078 str r0, [r7, #4] /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 8006514: 4a0b ldr r2, [pc, #44] @ (8006544 ) 8006516: 687b ldr r3, [r7, #4] 8006518: f043 0301 orr.w r3, r3, #1 800651c: 6053 str r3, [r2, #4] /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 800651e: 4b0a ldr r3, [pc, #40] @ (8006548 ) 8006520: 6a5b ldr r3, [r3, #36] @ 0x24 8006522: 4a09 ldr r2, [pc, #36] @ (8006548 ) 8006524: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8006528: 6253 str r3, [r2, #36] @ 0x24 __ASM volatile ("dsb 0xF":::"memory"); 800652a: f3bf 8f4f dsb sy } 800652e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8006530: f3bf 8f6f isb sy } 8006534: bf00 nop /* Ensure MPU setting take effects */ __DSB(); __ISB(); } 8006536: bf00 nop 8006538: 370c adds r7, #12 800653a: 46bd mov sp, r7 800653c: f85d 7b04 ldr.w r7, [sp], #4 8006540: 4770 bx lr 8006542: bf00 nop 8006544: e000ed90 .word 0xe000ed90 8006548: e000ed00 .word 0xe000ed00 0800654c : * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) { 800654c: b480 push {r7} 800654e: b083 sub sp, #12 8006550: af00 add r7, sp, #0 8006552: 6078 str r0, [r7, #4] assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; 8006554: 687b ldr r3, [r7, #4] 8006556: 785a ldrb r2, [r3, #1] 8006558: 4b1b ldr r3, [pc, #108] @ (80065c8 ) 800655a: 609a str r2, [r3, #8] /* Disable the Region */ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 800655c: 4b1a ldr r3, [pc, #104] @ (80065c8 ) 800655e: 691b ldr r3, [r3, #16] 8006560: 4a19 ldr r2, [pc, #100] @ (80065c8 ) 8006562: f023 0301 bic.w r3, r3, #1 8006566: 6113 str r3, [r2, #16] /* Apply configuration */ MPU->RBAR = MPU_Init->BaseAddress; 8006568: 4a17 ldr r2, [pc, #92] @ (80065c8 ) 800656a: 687b ldr r3, [r7, #4] 800656c: 685b ldr r3, [r3, #4] 800656e: 60d3 str r3, [r2, #12] MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8006570: 687b ldr r3, [r7, #4] 8006572: 7b1b ldrb r3, [r3, #12] 8006574: 071a lsls r2, r3, #28 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 8006576: 687b ldr r3, [r7, #4] 8006578: 7adb ldrb r3, [r3, #11] 800657a: 061b lsls r3, r3, #24 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 800657c: 431a orrs r2, r3 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 800657e: 687b ldr r3, [r7, #4] 8006580: 7a9b ldrb r3, [r3, #10] 8006582: 04db lsls r3, r3, #19 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 8006584: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8006586: 687b ldr r3, [r7, #4] 8006588: 7b5b ldrb r3, [r3, #13] 800658a: 049b lsls r3, r3, #18 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 800658c: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 800658e: 687b ldr r3, [r7, #4] 8006590: 7b9b ldrb r3, [r3, #14] 8006592: 045b lsls r3, r3, #17 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8006594: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8006596: 687b ldr r3, [r7, #4] 8006598: 7bdb ldrb r3, [r3, #15] 800659a: 041b lsls r3, r3, #16 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 800659c: 431a orrs r2, r3 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 800659e: 687b ldr r3, [r7, #4] 80065a0: 7a5b ldrb r3, [r3, #9] 80065a2: 021b lsls r3, r3, #8 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 80065a4: 431a orrs r2, r3 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 80065a6: 687b ldr r3, [r7, #4] 80065a8: 7a1b ldrb r3, [r3, #8] 80065aa: 005b lsls r3, r3, #1 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 80065ac: 4313 orrs r3, r2 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); 80065ae: 687a ldr r2, [r7, #4] 80065b0: 7812 ldrb r2, [r2, #0] 80065b2: 4611 mov r1, r2 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 80065b4: 4a04 ldr r2, [pc, #16] @ (80065c8 ) ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 80065b6: 430b orrs r3, r1 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 80065b8: 6113 str r3, [r2, #16] } 80065ba: bf00 nop 80065bc: 370c adds r7, #12 80065be: 46bd mov sp, r7 80065c0: f85d 7b04 ldr.w r7, [sp], #4 80065c4: 4770 bx lr 80065c6: bf00 nop 80065c8: e000ed90 .word 0xe000ed90 080065cc : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 80065cc: b580 push {r7, lr} 80065ce: b082 sub sp, #8 80065d0: af00 add r7, sp, #0 80065d2: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 80065d4: 687b ldr r3, [r7, #4] 80065d6: 2b00 cmp r3, #0 80065d8: d101 bne.n 80065de { return HAL_ERROR; 80065da: 2301 movs r3, #1 80065dc: e054 b.n 8006688 } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 80065de: 687b ldr r3, [r7, #4] 80065e0: 7f5b ldrb r3, [r3, #29] 80065e2: b2db uxtb r3, r3 80065e4: 2b00 cmp r3, #0 80065e6: d105 bne.n 80065f4 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 80065e8: 687b ldr r3, [r7, #4] 80065ea: 2200 movs r2, #0 80065ec: 771a strb r2, [r3, #28] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 80065ee: 6878 ldr r0, [r7, #4] 80065f0: f7fc fe3e bl 8003270 } hcrc->State = HAL_CRC_STATE_BUSY; 80065f4: 687b ldr r3, [r7, #4] 80065f6: 2202 movs r2, #2 80065f8: 775a strb r2, [r3, #29] /* check whether or not non-default generating polynomial has been * picked up by user */ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) 80065fa: 687b ldr r3, [r7, #4] 80065fc: 791b ldrb r3, [r3, #4] 80065fe: 2b00 cmp r3, #0 8006600: d10c bne.n 800661c { /* initialize peripheral with default generating polynomial */ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); 8006602: 687b ldr r3, [r7, #4] 8006604: 681b ldr r3, [r3, #0] 8006606: 4a22 ldr r2, [pc, #136] @ (8006690 ) 8006608: 615a str r2, [r3, #20] MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); 800660a: 687b ldr r3, [r7, #4] 800660c: 681b ldr r3, [r3, #0] 800660e: 689a ldr r2, [r3, #8] 8006610: 687b ldr r3, [r7, #4] 8006612: 681b ldr r3, [r3, #0] 8006614: f022 0218 bic.w r2, r2, #24 8006618: 609a str r2, [r3, #8] 800661a: e00c b.n 8006636 } else { /* initialize CRC peripheral with generating polynomial defined by user */ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) 800661c: 687b ldr r3, [r7, #4] 800661e: 6899 ldr r1, [r3, #8] 8006620: 687b ldr r3, [r7, #4] 8006622: 68db ldr r3, [r3, #12] 8006624: 461a mov r2, r3 8006626: 6878 ldr r0, [r7, #4] 8006628: f000 f948 bl 80068bc 800662c: 4603 mov r3, r0 800662e: 2b00 cmp r3, #0 8006630: d001 beq.n 8006636 { return HAL_ERROR; 8006632: 2301 movs r3, #1 8006634: e028 b.n 8006688 } /* check whether or not non-default CRC initial value has been * picked up by user */ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) 8006636: 687b ldr r3, [r7, #4] 8006638: 795b ldrb r3, [r3, #5] 800663a: 2b00 cmp r3, #0 800663c: d105 bne.n 800664a { WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); 800663e: 687b ldr r3, [r7, #4] 8006640: 681b ldr r3, [r3, #0] 8006642: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8006646: 611a str r2, [r3, #16] 8006648: e004 b.n 8006654 } else { WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); 800664a: 687b ldr r3, [r7, #4] 800664c: 681b ldr r3, [r3, #0] 800664e: 687a ldr r2, [r7, #4] 8006650: 6912 ldr r2, [r2, #16] 8006652: 611a str r2, [r3, #16] } /* set input data inversion mode */ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); 8006654: 687b ldr r3, [r7, #4] 8006656: 681b ldr r3, [r3, #0] 8006658: 689b ldr r3, [r3, #8] 800665a: f023 0160 bic.w r1, r3, #96 @ 0x60 800665e: 687b ldr r3, [r7, #4] 8006660: 695a ldr r2, [r3, #20] 8006662: 687b ldr r3, [r7, #4] 8006664: 681b ldr r3, [r3, #0] 8006666: 430a orrs r2, r1 8006668: 609a str r2, [r3, #8] /* set output data inversion mode */ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); 800666a: 687b ldr r3, [r7, #4] 800666c: 681b ldr r3, [r3, #0] 800666e: 689b ldr r3, [r3, #8] 8006670: f023 0180 bic.w r1, r3, #128 @ 0x80 8006674: 687b ldr r3, [r7, #4] 8006676: 699a ldr r2, [r3, #24] 8006678: 687b ldr r3, [r7, #4] 800667a: 681b ldr r3, [r3, #0] 800667c: 430a orrs r2, r1 800667e: 609a str r2, [r3, #8] /* makes sure the input data format (bytes, halfwords or words stream) * is properly specified by user */ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 8006680: 687b ldr r3, [r7, #4] 8006682: 2201 movs r2, #1 8006684: 775a strb r2, [r3, #29] /* Return function status */ return HAL_OK; 8006686: 2300 movs r3, #0 } 8006688: 4618 mov r0, r3 800668a: 3708 adds r7, #8 800668c: 46bd mov sp, r7 800668e: bd80 pop {r7, pc} 8006690: 04c11db7 .word 0x04c11db7 08006694 : * and the API will internally adjust its input data processing based on the * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { 8006694: b580 push {r7, lr} 8006696: b086 sub sp, #24 8006698: af00 add r7, sp, #0 800669a: 60f8 str r0, [r7, #12] 800669c: 60b9 str r1, [r7, #8] 800669e: 607a str r2, [r7, #4] uint32_t index; /* CRC input data buffer index */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ 80066a0: 2300 movs r3, #0 80066a2: 613b str r3, [r7, #16] /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; 80066a4: 68fb ldr r3, [r7, #12] 80066a6: 2202 movs r2, #2 80066a8: 775a strb r2, [r3, #29] /* Reset CRC Calculation Unit (hcrc->Instance->INIT is * written in hcrc->Instance->DR) */ __HAL_CRC_DR_RESET(hcrc); 80066aa: 68fb ldr r3, [r7, #12] 80066ac: 681b ldr r3, [r3, #0] 80066ae: 689a ldr r2, [r3, #8] 80066b0: 68fb ldr r3, [r7, #12] 80066b2: 681b ldr r3, [r3, #0] 80066b4: f042 0201 orr.w r2, r2, #1 80066b8: 609a str r2, [r3, #8] switch (hcrc->InputDataFormat) 80066ba: 68fb ldr r3, [r7, #12] 80066bc: 6a1b ldr r3, [r3, #32] 80066be: 2b03 cmp r3, #3 80066c0: d006 beq.n 80066d0 80066c2: 2b03 cmp r3, #3 80066c4: d829 bhi.n 800671a 80066c6: 2b01 cmp r3, #1 80066c8: d019 beq.n 80066fe 80066ca: 2b02 cmp r3, #2 80066cc: d01e beq.n 800670c /* Specific 16-bit input data handling */ temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: break; 80066ce: e024 b.n 800671a for (index = 0U; index < BufferLength; index++) 80066d0: 2300 movs r3, #0 80066d2: 617b str r3, [r7, #20] 80066d4: e00a b.n 80066ec hcrc->Instance->DR = pBuffer[index]; 80066d6: 697b ldr r3, [r7, #20] 80066d8: 009b lsls r3, r3, #2 80066da: 68ba ldr r2, [r7, #8] 80066dc: 441a add r2, r3 80066de: 68fb ldr r3, [r7, #12] 80066e0: 681b ldr r3, [r3, #0] 80066e2: 6812 ldr r2, [r2, #0] 80066e4: 601a str r2, [r3, #0] for (index = 0U; index < BufferLength; index++) 80066e6: 697b ldr r3, [r7, #20] 80066e8: 3301 adds r3, #1 80066ea: 617b str r3, [r7, #20] 80066ec: 697a ldr r2, [r7, #20] 80066ee: 687b ldr r3, [r7, #4] 80066f0: 429a cmp r2, r3 80066f2: d3f0 bcc.n 80066d6 temp = hcrc->Instance->DR; 80066f4: 68fb ldr r3, [r7, #12] 80066f6: 681b ldr r3, [r3, #0] 80066f8: 681b ldr r3, [r3, #0] 80066fa: 613b str r3, [r7, #16] break; 80066fc: e00e b.n 800671c temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); 80066fe: 687a ldr r2, [r7, #4] 8006700: 68b9 ldr r1, [r7, #8] 8006702: 68f8 ldr r0, [r7, #12] 8006704: f000 f812 bl 800672c 8006708: 6138 str r0, [r7, #16] break; 800670a: e007 b.n 800671c temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ 800670c: 687a ldr r2, [r7, #4] 800670e: 68b9 ldr r1, [r7, #8] 8006710: 68f8 ldr r0, [r7, #12] 8006712: f000 f899 bl 8006848 8006716: 6138 str r0, [r7, #16] break; 8006718: e000 b.n 800671c break; 800671a: bf00 nop } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 800671c: 68fb ldr r3, [r7, #12] 800671e: 2201 movs r2, #1 8006720: 775a strb r2, [r3, #29] /* Return the CRC computed value */ return temp; 8006722: 693b ldr r3, [r7, #16] } 8006724: 4618 mov r0, r3 8006726: 3718 adds r7, #24 8006728: 46bd mov sp, r7 800672a: bd80 pop {r7, pc} 0800672c : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { 800672c: b480 push {r7} 800672e: b089 sub sp, #36 @ 0x24 8006730: af00 add r7, sp, #0 8006732: 60f8 str r0, [r7, #12] 8006734: 60b9 str r1, [r7, #8] 8006736: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 4 bytes are entered in a row with a single word write, * last bytes must be carefully fed to the CRC calculator to ensure a correct type * handling by the peripheral */ for (i = 0U; i < (BufferLength / 4U); i++) 8006738: 2300 movs r3, #0 800673a: 61fb str r3, [r7, #28] 800673c: e023 b.n 8006786 { hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 800673e: 69fb ldr r3, [r7, #28] 8006740: 009b lsls r3, r3, #2 8006742: 68ba ldr r2, [r7, #8] 8006744: 4413 add r3, r2 8006746: 781b ldrb r3, [r3, #0] 8006748: 061a lsls r2, r3, #24 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 800674a: 69fb ldr r3, [r7, #28] 800674c: 009b lsls r3, r3, #2 800674e: 3301 adds r3, #1 8006750: 68b9 ldr r1, [r7, #8] 8006752: 440b add r3, r1 8006754: 781b ldrb r3, [r3, #0] 8006756: 041b lsls r3, r3, #16 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8006758: 431a orrs r2, r3 ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 800675a: 69fb ldr r3, [r7, #28] 800675c: 009b lsls r3, r3, #2 800675e: 3302 adds r3, #2 8006760: 68b9 ldr r1, [r7, #8] 8006762: 440b add r3, r1 8006764: 781b ldrb r3, [r3, #0] 8006766: 021b lsls r3, r3, #8 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8006768: 431a orrs r2, r3 (uint32_t)pBuffer[(4U * i) + 3U]; 800676a: 69fb ldr r3, [r7, #28] 800676c: 009b lsls r3, r3, #2 800676e: 3303 adds r3, #3 8006770: 68b9 ldr r1, [r7, #8] 8006772: 440b add r3, r1 8006774: 781b ldrb r3, [r3, #0] 8006776: 4619 mov r1, r3 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8006778: 68fb ldr r3, [r7, #12] 800677a: 681b ldr r3, [r3, #0] ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 800677c: 430a orrs r2, r1 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 800677e: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 4U); i++) 8006780: 69fb ldr r3, [r7, #28] 8006782: 3301 adds r3, #1 8006784: 61fb str r3, [r7, #28] 8006786: 687b ldr r3, [r7, #4] 8006788: 089b lsrs r3, r3, #2 800678a: 69fa ldr r2, [r7, #28] 800678c: 429a cmp r2, r3 800678e: d3d6 bcc.n 800673e } /* last bytes specific handling */ if ((BufferLength % 4U) != 0U) 8006790: 687b ldr r3, [r7, #4] 8006792: f003 0303 and.w r3, r3, #3 8006796: 2b00 cmp r3, #0 8006798: d04d beq.n 8006836 { if ((BufferLength % 4U) == 1U) 800679a: 687b ldr r3, [r7, #4] 800679c: f003 0303 and.w r3, r3, #3 80067a0: 2b01 cmp r3, #1 80067a2: d107 bne.n 80067b4 { *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ 80067a4: 69fb ldr r3, [r7, #28] 80067a6: 009b lsls r3, r3, #2 80067a8: 68ba ldr r2, [r7, #8] 80067aa: 4413 add r3, r2 80067ac: 68fa ldr r2, [r7, #12] 80067ae: 6812 ldr r2, [r2, #0] 80067b0: 781b ldrb r3, [r3, #0] 80067b2: 7013 strb r3, [r2, #0] } if ((BufferLength % 4U) == 2U) 80067b4: 687b ldr r3, [r7, #4] 80067b6: f003 0303 and.w r3, r3, #3 80067ba: 2b02 cmp r3, #2 80067bc: d116 bne.n 80067ec { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 80067be: 69fb ldr r3, [r7, #28] 80067c0: 009b lsls r3, r3, #2 80067c2: 68ba ldr r2, [r7, #8] 80067c4: 4413 add r3, r2 80067c6: 781b ldrb r3, [r3, #0] 80067c8: 021b lsls r3, r3, #8 80067ca: b21a sxth r2, r3 80067cc: 69fb ldr r3, [r7, #28] 80067ce: 009b lsls r3, r3, #2 80067d0: 3301 adds r3, #1 80067d2: 68b9 ldr r1, [r7, #8] 80067d4: 440b add r3, r1 80067d6: 781b ldrb r3, [r3, #0] 80067d8: b21b sxth r3, r3 80067da: 4313 orrs r3, r2 80067dc: b21b sxth r3, r3 80067de: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 80067e0: 68fb ldr r3, [r7, #12] 80067e2: 681b ldr r3, [r3, #0] 80067e4: 617b str r3, [r7, #20] *pReg = data; 80067e6: 697b ldr r3, [r7, #20] 80067e8: 8b7a ldrh r2, [r7, #26] 80067ea: 801a strh r2, [r3, #0] } if ((BufferLength % 4U) == 3U) 80067ec: 687b ldr r3, [r7, #4] 80067ee: f003 0303 and.w r3, r3, #3 80067f2: 2b03 cmp r3, #3 80067f4: d11f bne.n 8006836 { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 80067f6: 69fb ldr r3, [r7, #28] 80067f8: 009b lsls r3, r3, #2 80067fa: 68ba ldr r2, [r7, #8] 80067fc: 4413 add r3, r2 80067fe: 781b ldrb r3, [r3, #0] 8006800: 021b lsls r3, r3, #8 8006802: b21a sxth r2, r3 8006804: 69fb ldr r3, [r7, #28] 8006806: 009b lsls r3, r3, #2 8006808: 3301 adds r3, #1 800680a: 68b9 ldr r1, [r7, #8] 800680c: 440b add r3, r1 800680e: 781b ldrb r3, [r3, #0] 8006810: b21b sxth r3, r3 8006812: 4313 orrs r3, r2 8006814: b21b sxth r3, r3 8006816: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8006818: 68fb ldr r3, [r7, #12] 800681a: 681b ldr r3, [r3, #0] 800681c: 617b str r3, [r7, #20] *pReg = data; 800681e: 697b ldr r3, [r7, #20] 8006820: 8b7a ldrh r2, [r7, #26] 8006822: 801a strh r2, [r3, #0] *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ 8006824: 69fb ldr r3, [r7, #28] 8006826: 009b lsls r3, r3, #2 8006828: 3302 adds r3, #2 800682a: 68ba ldr r2, [r7, #8] 800682c: 4413 add r3, r2 800682e: 68fa ldr r2, [r7, #12] 8006830: 6812 ldr r2, [r2, #0] 8006832: 781b ldrb r3, [r3, #0] 8006834: 7013 strb r3, [r2, #0] } } /* Return the CRC computed value */ return hcrc->Instance->DR; 8006836: 68fb ldr r3, [r7, #12] 8006838: 681b ldr r3, [r3, #0] 800683a: 681b ldr r3, [r3, #0] } 800683c: 4618 mov r0, r3 800683e: 3724 adds r7, #36 @ 0x24 8006840: 46bd mov sp, r7 8006842: f85d 7b04 ldr.w r7, [sp], #4 8006846: 4770 bx lr 08006848 : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { 8006848: b480 push {r7} 800684a: b087 sub sp, #28 800684c: af00 add r7, sp, #0 800684e: 60f8 str r0, [r7, #12] 8006850: 60b9 str r1, [r7, #8] 8006852: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the peripheral */ for (i = 0U; i < (BufferLength / 2U); i++) 8006854: 2300 movs r3, #0 8006856: 617b str r3, [r7, #20] 8006858: e013 b.n 8006882 { hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; 800685a: 697b ldr r3, [r7, #20] 800685c: 009b lsls r3, r3, #2 800685e: 68ba ldr r2, [r7, #8] 8006860: 4413 add r3, r2 8006862: 881b ldrh r3, [r3, #0] 8006864: 041a lsls r2, r3, #16 8006866: 697b ldr r3, [r7, #20] 8006868: 009b lsls r3, r3, #2 800686a: 3302 adds r3, #2 800686c: 68b9 ldr r1, [r7, #8] 800686e: 440b add r3, r1 8006870: 881b ldrh r3, [r3, #0] 8006872: 4619 mov r1, r3 8006874: 68fb ldr r3, [r7, #12] 8006876: 681b ldr r3, [r3, #0] 8006878: 430a orrs r2, r1 800687a: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 2U); i++) 800687c: 697b ldr r3, [r7, #20] 800687e: 3301 adds r3, #1 8006880: 617b str r3, [r7, #20] 8006882: 687b ldr r3, [r7, #4] 8006884: 085b lsrs r3, r3, #1 8006886: 697a ldr r2, [r7, #20] 8006888: 429a cmp r2, r3 800688a: d3e6 bcc.n 800685a } if ((BufferLength % 2U) != 0U) 800688c: 687b ldr r3, [r7, #4] 800688e: f003 0301 and.w r3, r3, #1 8006892: 2b00 cmp r3, #0 8006894: d009 beq.n 80068aa { pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8006896: 68fb ldr r3, [r7, #12] 8006898: 681b ldr r3, [r3, #0] 800689a: 613b str r3, [r7, #16] *pReg = pBuffer[2U * i]; 800689c: 697b ldr r3, [r7, #20] 800689e: 009b lsls r3, r3, #2 80068a0: 68ba ldr r2, [r7, #8] 80068a2: 4413 add r3, r2 80068a4: 881a ldrh r2, [r3, #0] 80068a6: 693b ldr r3, [r7, #16] 80068a8: 801a strh r2, [r3, #0] } /* Return the CRC computed value */ return hcrc->Instance->DR; 80068aa: 68fb ldr r3, [r7, #12] 80068ac: 681b ldr r3, [r3, #0] 80068ae: 681b ldr r3, [r3, #0] } 80068b0: 4618 mov r0, r3 80068b2: 371c adds r7, #28 80068b4: 46bd mov sp, r7 80068b6: f85d 7b04 ldr.w r7, [sp], #4 80068ba: 4770 bx lr 080068bc : * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) { 80068bc: b480 push {r7} 80068be: b087 sub sp, #28 80068c0: af00 add r7, sp, #0 80068c2: 60f8 str r0, [r7, #12] 80068c4: 60b9 str r1, [r7, #8] 80068c6: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80068c8: 2300 movs r3, #0 80068ca: 75fb strb r3, [r7, #23] uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ 80068cc: 231f movs r3, #31 80068ce: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); /* Ensure that the generating polynomial is odd */ if ((Pol & (uint32_t)(0x1U)) == 0U) 80068d0: 68bb ldr r3, [r7, #8] 80068d2: f003 0301 and.w r3, r3, #1 80068d6: 2b00 cmp r3, #0 80068d8: d102 bne.n 80068e0 { status = HAL_ERROR; 80068da: 2301 movs r3, #1 80068dc: 75fb strb r3, [r7, #23] 80068de: e063 b.n 80069a8 * definition. HAL_ERROR is reported if Pol degree is * larger than that indicated by PolyLength. * Look for MSB position: msb will contain the degree of * the second to the largest polynomial member. E.g., for * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) 80068e0: bf00 nop 80068e2: 693b ldr r3, [r7, #16] 80068e4: 1e5a subs r2, r3, #1 80068e6: 613a str r2, [r7, #16] 80068e8: 2b00 cmp r3, #0 80068ea: d009 beq.n 8006900 80068ec: 693b ldr r3, [r7, #16] 80068ee: f003 031f and.w r3, r3, #31 80068f2: 68ba ldr r2, [r7, #8] 80068f4: fa22 f303 lsr.w r3, r2, r3 80068f8: f003 0301 and.w r3, r3, #1 80068fc: 2b00 cmp r3, #0 80068fe: d0f0 beq.n 80068e2 { } switch (PolyLength) 8006900: 687b ldr r3, [r7, #4] 8006902: 2b18 cmp r3, #24 8006904: d846 bhi.n 8006994 8006906: a201 add r2, pc, #4 @ (adr r2, 800690c ) 8006908: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800690c: 0800699b .word 0x0800699b 8006910: 08006995 .word 0x08006995 8006914: 08006995 .word 0x08006995 8006918: 08006995 .word 0x08006995 800691c: 08006995 .word 0x08006995 8006920: 08006995 .word 0x08006995 8006924: 08006995 .word 0x08006995 8006928: 08006995 .word 0x08006995 800692c: 08006989 .word 0x08006989 8006930: 08006995 .word 0x08006995 8006934: 08006995 .word 0x08006995 8006938: 08006995 .word 0x08006995 800693c: 08006995 .word 0x08006995 8006940: 08006995 .word 0x08006995 8006944: 08006995 .word 0x08006995 8006948: 08006995 .word 0x08006995 800694c: 0800697d .word 0x0800697d 8006950: 08006995 .word 0x08006995 8006954: 08006995 .word 0x08006995 8006958: 08006995 .word 0x08006995 800695c: 08006995 .word 0x08006995 8006960: 08006995 .word 0x08006995 8006964: 08006995 .word 0x08006995 8006968: 08006995 .word 0x08006995 800696c: 08006971 .word 0x08006971 { case CRC_POLYLENGTH_7B: if (msb >= HAL_CRC_LENGTH_7B) 8006970: 693b ldr r3, [r7, #16] 8006972: 2b06 cmp r3, #6 8006974: d913 bls.n 800699e { status = HAL_ERROR; 8006976: 2301 movs r3, #1 8006978: 75fb strb r3, [r7, #23] } break; 800697a: e010 b.n 800699e case CRC_POLYLENGTH_8B: if (msb >= HAL_CRC_LENGTH_8B) 800697c: 693b ldr r3, [r7, #16] 800697e: 2b07 cmp r3, #7 8006980: d90f bls.n 80069a2 { status = HAL_ERROR; 8006982: 2301 movs r3, #1 8006984: 75fb strb r3, [r7, #23] } break; 8006986: e00c b.n 80069a2 case CRC_POLYLENGTH_16B: if (msb >= HAL_CRC_LENGTH_16B) 8006988: 693b ldr r3, [r7, #16] 800698a: 2b0f cmp r3, #15 800698c: d90b bls.n 80069a6 { status = HAL_ERROR; 800698e: 2301 movs r3, #1 8006990: 75fb strb r3, [r7, #23] } break; 8006992: e008 b.n 80069a6 case CRC_POLYLENGTH_32B: /* no polynomial definition vs. polynomial length issue possible */ break; default: status = HAL_ERROR; 8006994: 2301 movs r3, #1 8006996: 75fb strb r3, [r7, #23] break; 8006998: e006 b.n 80069a8 break; 800699a: bf00 nop 800699c: e004 b.n 80069a8 break; 800699e: bf00 nop 80069a0: e002 b.n 80069a8 break; 80069a2: bf00 nop 80069a4: e000 b.n 80069a8 break; 80069a6: bf00 nop } } if (status == HAL_OK) 80069a8: 7dfb ldrb r3, [r7, #23] 80069aa: 2b00 cmp r3, #0 80069ac: d10d bne.n 80069ca { /* set generating polynomial */ WRITE_REG(hcrc->Instance->POL, Pol); 80069ae: 68fb ldr r3, [r7, #12] 80069b0: 681b ldr r3, [r3, #0] 80069b2: 68ba ldr r2, [r7, #8] 80069b4: 615a str r2, [r3, #20] /* set generating polynomial size */ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); 80069b6: 68fb ldr r3, [r7, #12] 80069b8: 681b ldr r3, [r3, #0] 80069ba: 689b ldr r3, [r3, #8] 80069bc: f023 0118 bic.w r1, r3, #24 80069c0: 68fb ldr r3, [r7, #12] 80069c2: 681b ldr r3, [r3, #0] 80069c4: 687a ldr r2, [r7, #4] 80069c6: 430a orrs r2, r1 80069c8: 609a str r2, [r3, #8] } /* Return function status */ return status; 80069ca: 7dfb ldrb r3, [r7, #23] } 80069cc: 4618 mov r0, r3 80069ce: 371c adds r7, #28 80069d0: 46bd mov sp, r7 80069d2: f85d 7b04 ldr.w r7, [sp], #4 80069d6: 4770 bx lr 080069d8 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { 80069d8: b580 push {r7, lr} 80069da: b082 sub sp, #8 80069dc: af00 add r7, sp, #0 80069de: 6078 str r0, [r7, #4] /* Check the DAC peripheral handle */ if (hdac == NULL) 80069e0: 687b ldr r3, [r7, #4] 80069e2: 2b00 cmp r3, #0 80069e4: d101 bne.n 80069ea { return HAL_ERROR; 80069e6: 2301 movs r3, #1 80069e8: e014 b.n 8006a14 } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); if (hdac->State == HAL_DAC_STATE_RESET) 80069ea: 687b ldr r3, [r7, #4] 80069ec: 791b ldrb r3, [r3, #4] 80069ee: b2db uxtb r3, r3 80069f0: 2b00 cmp r3, #0 80069f2: d105 bne.n 8006a00 hdac->MspInitCallback = HAL_DAC_MspInit; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /* Allocate lock resource and initialize it */ hdac->Lock = HAL_UNLOCKED; 80069f4: 687b ldr r3, [r7, #4] 80069f6: 2200 movs r2, #0 80069f8: 715a strb r2, [r3, #5] #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* Init the low level hardware */ hdac->MspInitCallback(hdac); #else /* Init the low level hardware */ HAL_DAC_MspInit(hdac); 80069fa: 6878 ldr r0, [r7, #4] 80069fc: f7fc fc5a bl 80032b4 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; 8006a00: 687b ldr r3, [r7, #4] 8006a02: 2202 movs r2, #2 8006a04: 711a strb r2, [r3, #4] /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; 8006a06: 687b ldr r3, [r7, #4] 8006a08: 2200 movs r2, #0 8006a0a: 611a str r2, [r3, #16] /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; 8006a0c: 687b ldr r3, [r7, #4] 8006a0e: 2201 movs r2, #1 8006a10: 711a strb r2, [r3, #4] /* Return function status */ return HAL_OK; 8006a12: 2300 movs r3, #0 } 8006a14: 4618 mov r0, r3 8006a16: 3708 adds r7, #8 8006a18: 46bd mov sp, r7 8006a1a: bd80 pop {r7, pc} 08006a1c : * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { 8006a1c: b480 push {r7} 8006a1e: b083 sub sp, #12 8006a20: af00 add r7, sp, #0 8006a22: 6078 str r0, [r7, #4] 8006a24: 6039 str r1, [r7, #0] /* Check the DAC peripheral handle */ if (hdac == NULL) 8006a26: 687b ldr r3, [r7, #4] 8006a28: 2b00 cmp r3, #0 8006a2a: d101 bne.n 8006a30 { return HAL_ERROR; 8006a2c: 2301 movs r3, #1 8006a2e: e046 b.n 8006abe /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 8006a30: 687b ldr r3, [r7, #4] 8006a32: 795b ldrb r3, [r3, #5] 8006a34: 2b01 cmp r3, #1 8006a36: d101 bne.n 8006a3c 8006a38: 2302 movs r3, #2 8006a3a: e040 b.n 8006abe 8006a3c: 687b ldr r3, [r7, #4] 8006a3e: 2201 movs r2, #1 8006a40: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 8006a42: 687b ldr r3, [r7, #4] 8006a44: 2202 movs r2, #2 8006a46: 711a strb r2, [r3, #4] /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); 8006a48: 687b ldr r3, [r7, #4] 8006a4a: 681b ldr r3, [r3, #0] 8006a4c: 6819 ldr r1, [r3, #0] 8006a4e: 683b ldr r3, [r7, #0] 8006a50: f003 0310 and.w r3, r3, #16 8006a54: 2201 movs r2, #1 8006a56: 409a lsls r2, r3 8006a58: 687b ldr r3, [r7, #4] 8006a5a: 681b ldr r3, [r3, #0] 8006a5c: 430a orrs r2, r1 8006a5e: 601a str r2, [r3, #0] if (Channel == DAC_CHANNEL_1) 8006a60: 683b ldr r3, [r7, #0] 8006a62: 2b00 cmp r3, #0 8006a64: d10f bne.n 8006a86 { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) 8006a66: 687b ldr r3, [r7, #4] 8006a68: 681b ldr r3, [r3, #0] 8006a6a: 681b ldr r3, [r3, #0] 8006a6c: f003 033e and.w r3, r3, #62 @ 0x3e 8006a70: 2b02 cmp r3, #2 8006a72: d11d bne.n 8006ab0 { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); 8006a74: 687b ldr r3, [r7, #4] 8006a76: 681b ldr r3, [r3, #0] 8006a78: 685a ldr r2, [r3, #4] 8006a7a: 687b ldr r3, [r7, #4] 8006a7c: 681b ldr r3, [r3, #0] 8006a7e: f042 0201 orr.w r2, r2, #1 8006a82: 605a str r2, [r3, #4] 8006a84: e014 b.n 8006ab0 } else { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) 8006a86: 687b ldr r3, [r7, #4] 8006a88: 681b ldr r3, [r3, #0] 8006a8a: 681b ldr r3, [r3, #0] 8006a8c: f403 1278 and.w r2, r3, #4063232 @ 0x3e0000 8006a90: 683b ldr r3, [r7, #0] 8006a92: f003 0310 and.w r3, r3, #16 8006a96: 2102 movs r1, #2 8006a98: fa01 f303 lsl.w r3, r1, r3 8006a9c: 429a cmp r2, r3 8006a9e: d107 bne.n 8006ab0 { /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); 8006aa0: 687b ldr r3, [r7, #4] 8006aa2: 681b ldr r3, [r3, #0] 8006aa4: 685a ldr r2, [r3, #4] 8006aa6: 687b ldr r3, [r7, #4] 8006aa8: 681b ldr r3, [r3, #0] 8006aaa: f042 0202 orr.w r2, r2, #2 8006aae: 605a str r2, [r3, #4] } } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 8006ab0: 687b ldr r3, [r7, #4] 8006ab2: 2201 movs r2, #1 8006ab4: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 8006ab6: 687b ldr r3, [r7, #4] 8006ab8: 2200 movs r2, #0 8006aba: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 8006abc: 2300 movs r3, #0 } 8006abe: 4618 mov r0, r3 8006ac0: 370c adds r7, #12 8006ac2: 46bd mov sp, r7 8006ac4: f85d 7b04 ldr.w r7, [sp], #4 8006ac8: 4770 bx lr 08006aca : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { 8006aca: b580 push {r7, lr} 8006acc: b084 sub sp, #16 8006ace: af00 add r7, sp, #0 8006ad0: 6078 str r0, [r7, #4] uint32_t itsource = hdac->Instance->CR; 8006ad2: 687b ldr r3, [r7, #4] 8006ad4: 681b ldr r3, [r3, #0] 8006ad6: 681b ldr r3, [r3, #0] 8006ad8: 60fb str r3, [r7, #12] uint32_t itflag = hdac->Instance->SR; 8006ada: 687b ldr r3, [r7, #4] 8006adc: 681b ldr r3, [r3, #0] 8006ade: 6b5b ldr r3, [r3, #52] @ 0x34 8006ae0: 60bb str r3, [r7, #8] if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1) 8006ae2: 68fb ldr r3, [r7, #12] 8006ae4: f403 5300 and.w r3, r3, #8192 @ 0x2000 8006ae8: 2b00 cmp r3, #0 8006aea: d01d beq.n 8006b28 { /* Check underrun flag of DAC channel 1 */ if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1) 8006aec: 68bb ldr r3, [r7, #8] 8006aee: f403 5300 and.w r3, r3, #8192 @ 0x2000 8006af2: 2b00 cmp r3, #0 8006af4: d018 beq.n 8006b28 { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; 8006af6: 687b ldr r3, [r7, #4] 8006af8: 2204 movs r2, #4 8006afa: 711a strb r2, [r3, #4] /* Set DAC error code to channel1 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); 8006afc: 687b ldr r3, [r7, #4] 8006afe: 691b ldr r3, [r3, #16] 8006b00: f043 0201 orr.w r2, r3, #1 8006b04: 687b ldr r3, [r7, #4] 8006b06: 611a str r2, [r3, #16] /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); 8006b08: 687b ldr r3, [r7, #4] 8006b0a: 681b ldr r3, [r3, #0] 8006b0c: f44f 5200 mov.w r2, #8192 @ 0x2000 8006b10: 635a str r2, [r3, #52] @ 0x34 /* Disable the selected DAC channel1 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1); 8006b12: 687b ldr r3, [r7, #4] 8006b14: 681b ldr r3, [r3, #0] 8006b16: 681a ldr r2, [r3, #0] 8006b18: 687b ldr r3, [r7, #4] 8006b1a: 681b ldr r3, [r3, #0] 8006b1c: f422 5280 bic.w r2, r2, #4096 @ 0x1000 8006b20: 601a str r2, [r3, #0] /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh1(hdac); #else HAL_DAC_DMAUnderrunCallbackCh1(hdac); 8006b22: 6878 ldr r0, [r7, #4] 8006b24: f000 f851 bl 8006bca #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2) 8006b28: 68fb ldr r3, [r7, #12] 8006b2a: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8006b2e: 2b00 cmp r3, #0 8006b30: d01d beq.n 8006b6e { /* Check underrun flag of DAC channel 2 */ if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2) 8006b32: 68bb ldr r3, [r7, #8] 8006b34: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8006b38: 2b00 cmp r3, #0 8006b3a: d018 beq.n 8006b6e { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; 8006b3c: 687b ldr r3, [r7, #4] 8006b3e: 2204 movs r2, #4 8006b40: 711a strb r2, [r3, #4] /* Set DAC error code to channel2 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); 8006b42: 687b ldr r3, [r7, #4] 8006b44: 691b ldr r3, [r3, #16] 8006b46: f043 0202 orr.w r2, r3, #2 8006b4a: 687b ldr r3, [r7, #4] 8006b4c: 611a str r2, [r3, #16] /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); 8006b4e: 687b ldr r3, [r7, #4] 8006b50: 681b ldr r3, [r3, #0] 8006b52: f04f 5200 mov.w r2, #536870912 @ 0x20000000 8006b56: 635a str r2, [r3, #52] @ 0x34 /* Disable the selected DAC channel2 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2); 8006b58: 687b ldr r3, [r7, #4] 8006b5a: 681b ldr r3, [r3, #0] 8006b5c: 681a ldr r2, [r3, #0] 8006b5e: 687b ldr r3, [r7, #4] 8006b60: 681b ldr r3, [r3, #0] 8006b62: f022 5280 bic.w r2, r2, #268435456 @ 0x10000000 8006b66: 601a str r2, [r3, #0] /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh2(hdac); #else HAL_DACEx_DMAUnderrunCallbackCh2(hdac); 8006b68: 6878 ldr r0, [r7, #4] 8006b6a: f000 f97b bl 8006e64 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } } 8006b6e: bf00 nop 8006b70: 3710 adds r7, #16 8006b72: 46bd mov sp, r7 8006b74: bd80 pop {r7, pc} 08006b76 : * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { 8006b76: b480 push {r7} 8006b78: b087 sub sp, #28 8006b7a: af00 add r7, sp, #0 8006b7c: 60f8 str r0, [r7, #12] 8006b7e: 60b9 str r1, [r7, #8] 8006b80: 607a str r2, [r7, #4] 8006b82: 603b str r3, [r7, #0] __IO uint32_t tmp = 0UL; 8006b84: 2300 movs r3, #0 8006b86: 617b str r3, [r7, #20] /* Check the DAC peripheral handle */ if (hdac == NULL) 8006b88: 68fb ldr r3, [r7, #12] 8006b8a: 2b00 cmp r3, #0 8006b8c: d101 bne.n 8006b92 { return HAL_ERROR; 8006b8e: 2301 movs r3, #1 8006b90: e015 b.n 8006bbe /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)hdac->Instance; 8006b92: 68fb ldr r3, [r7, #12] 8006b94: 681b ldr r3, [r3, #0] 8006b96: 617b str r3, [r7, #20] if (Channel == DAC_CHANNEL_1) 8006b98: 68bb ldr r3, [r7, #8] 8006b9a: 2b00 cmp r3, #0 8006b9c: d105 bne.n 8006baa { tmp += DAC_DHR12R1_ALIGNMENT(Alignment); 8006b9e: 697a ldr r2, [r7, #20] 8006ba0: 687b ldr r3, [r7, #4] 8006ba2: 4413 add r3, r2 8006ba4: 3308 adds r3, #8 8006ba6: 617b str r3, [r7, #20] 8006ba8: e004 b.n 8006bb4 } else { tmp += DAC_DHR12R2_ALIGNMENT(Alignment); 8006baa: 697a ldr r2, [r7, #20] 8006bac: 687b ldr r3, [r7, #4] 8006bae: 4413 add r3, r2 8006bb0: 3314 adds r3, #20 8006bb2: 617b str r3, [r7, #20] } /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; 8006bb4: 697b ldr r3, [r7, #20] 8006bb6: 461a mov r2, r3 8006bb8: 683b ldr r3, [r7, #0] 8006bba: 6013 str r3, [r2, #0] /* Return function status */ return HAL_OK; 8006bbc: 2300 movs r3, #0 } 8006bbe: 4618 mov r0, r3 8006bc0: 371c adds r7, #28 8006bc2: 46bd mov sp, r7 8006bc4: f85d 7b04 ldr.w r7, [sp], #4 8006bc8: 4770 bx lr 08006bca : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) { 8006bca: b480 push {r7} 8006bcc: b083 sub sp, #12 8006bce: af00 add r7, sp, #0 8006bd0: 6078 str r0, [r7, #4] UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file */ } 8006bd2: bf00 nop 8006bd4: 370c adds r7, #12 8006bd6: 46bd mov sp, r7 8006bd8: f85d 7b04 ldr.w r7, [sp], #4 8006bdc: 4770 bx lr ... 08006be0 : * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { 8006be0: b580 push {r7, lr} 8006be2: b08a sub sp, #40 @ 0x28 8006be4: af00 add r7, sp, #0 8006be6: 60f8 str r0, [r7, #12] 8006be8: 60b9 str r1, [r7, #8] 8006bea: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8006bec: 2300 movs r3, #0 8006bee: f887 3023 strb.w r3, [r7, #35] @ 0x23 uint32_t tmpreg2; uint32_t tickstart; uint32_t connectOnChip; /* Check the DAC peripheral handle and channel configuration struct */ if ((hdac == NULL) || (sConfig == NULL)) 8006bf2: 68fb ldr r3, [r7, #12] 8006bf4: 2b00 cmp r3, #0 8006bf6: d002 beq.n 8006bfe 8006bf8: 68bb ldr r3, [r7, #8] 8006bfa: 2b00 cmp r3, #0 8006bfc: d101 bne.n 8006c02 { return HAL_ERROR; 8006bfe: 2301 movs r3, #1 8006c00: e12a b.n 8006e58 assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 8006c02: 68fb ldr r3, [r7, #12] 8006c04: 795b ldrb r3, [r3, #5] 8006c06: 2b01 cmp r3, #1 8006c08: d101 bne.n 8006c0e 8006c0a: 2302 movs r3, #2 8006c0c: e124 b.n 8006e58 8006c0e: 68fb ldr r3, [r7, #12] 8006c10: 2201 movs r2, #1 8006c12: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 8006c14: 68fb ldr r3, [r7, #12] 8006c16: 2202 movs r2, #2 8006c18: 711a strb r2, [r3, #4] /* Sample and hold configuration */ if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) 8006c1a: 68bb ldr r3, [r7, #8] 8006c1c: 681b ldr r3, [r3, #0] 8006c1e: 2b04 cmp r3, #4 8006c20: d17a bne.n 8006d18 { /* Get timeout */ tickstart = HAL_GetTick(); 8006c22: f7fd ff1f bl 8004a64 8006c26: 61f8 str r0, [r7, #28] if (Channel == DAC_CHANNEL_1) 8006c28: 687b ldr r3, [r7, #4] 8006c2a: 2b00 cmp r3, #0 8006c2c: d13d bne.n 8006caa { /* SHSR1 can be written when BWST1 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 8006c2e: e018 b.n 8006c62 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8006c30: f7fd ff18 bl 8004a64 8006c34: 4602 mov r2, r0 8006c36: 69fb ldr r3, [r7, #28] 8006c38: 1ad3 subs r3, r2, r3 8006c3a: 2b01 cmp r3, #1 8006c3c: d911 bls.n 8006c62 { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 8006c3e: 68fb ldr r3, [r7, #12] 8006c40: 681b ldr r3, [r3, #0] 8006c42: 6b5a ldr r2, [r3, #52] @ 0x34 8006c44: 4b86 ldr r3, [pc, #536] @ (8006e60 ) 8006c46: 4013 ands r3, r2 8006c48: 2b00 cmp r3, #0 8006c4a: d00a beq.n 8006c62 { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 8006c4c: 68fb ldr r3, [r7, #12] 8006c4e: 691b ldr r3, [r3, #16] 8006c50: f043 0208 orr.w r2, r3, #8 8006c54: 68fb ldr r3, [r7, #12] 8006c56: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 8006c58: 68fb ldr r3, [r7, #12] 8006c5a: 2203 movs r2, #3 8006c5c: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 8006c5e: 2303 movs r3, #3 8006c60: e0fa b.n 8006e58 while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 8006c62: 68fb ldr r3, [r7, #12] 8006c64: 681b ldr r3, [r3, #0] 8006c66: 6b5a ldr r2, [r3, #52] @ 0x34 8006c68: 4b7d ldr r3, [pc, #500] @ (8006e60 ) 8006c6a: 4013 ands r3, r2 8006c6c: 2b00 cmp r3, #0 8006c6e: d1df bne.n 8006c30 } } } hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 8006c70: 68fb ldr r3, [r7, #12] 8006c72: 681b ldr r3, [r3, #0] 8006c74: 68ba ldr r2, [r7, #8] 8006c76: 6992 ldr r2, [r2, #24] 8006c78: 641a str r2, [r3, #64] @ 0x40 8006c7a: e020 b.n 8006cbe { /* SHSR2 can be written when BWST2 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8006c7c: f7fd fef2 bl 8004a64 8006c80: 4602 mov r2, r0 8006c82: 69fb ldr r3, [r7, #28] 8006c84: 1ad3 subs r3, r2, r3 8006c86: 2b01 cmp r3, #1 8006c88: d90f bls.n 8006caa { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 8006c8a: 68fb ldr r3, [r7, #12] 8006c8c: 681b ldr r3, [r3, #0] 8006c8e: 6b5b ldr r3, [r3, #52] @ 0x34 8006c90: 2b00 cmp r3, #0 8006c92: da0a bge.n 8006caa { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 8006c94: 68fb ldr r3, [r7, #12] 8006c96: 691b ldr r3, [r3, #16] 8006c98: f043 0208 orr.w r2, r3, #8 8006c9c: 68fb ldr r3, [r7, #12] 8006c9e: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 8006ca0: 68fb ldr r3, [r7, #12] 8006ca2: 2203 movs r2, #3 8006ca4: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 8006ca6: 2303 movs r3, #3 8006ca8: e0d6 b.n 8006e58 while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 8006caa: 68fb ldr r3, [r7, #12] 8006cac: 681b ldr r3, [r3, #0] 8006cae: 6b5b ldr r3, [r3, #52] @ 0x34 8006cb0: 2b00 cmp r3, #0 8006cb2: dbe3 blt.n 8006c7c } } } hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 8006cb4: 68fb ldr r3, [r7, #12] 8006cb6: 681b ldr r3, [r3, #0] 8006cb8: 68ba ldr r2, [r7, #8] 8006cba: 6992 ldr r2, [r2, #24] 8006cbc: 645a str r2, [r3, #68] @ 0x44 } /* HoldTime */ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), 8006cbe: 68fb ldr r3, [r7, #12] 8006cc0: 681b ldr r3, [r3, #0] 8006cc2: 6c9a ldr r2, [r3, #72] @ 0x48 8006cc4: 687b ldr r3, [r7, #4] 8006cc6: f003 0310 and.w r3, r3, #16 8006cca: f240 31ff movw r1, #1023 @ 0x3ff 8006cce: fa01 f303 lsl.w r3, r1, r3 8006cd2: 43db mvns r3, r3 8006cd4: ea02 0103 and.w r1, r2, r3 8006cd8: 68bb ldr r3, [r7, #8] 8006cda: 69da ldr r2, [r3, #28] 8006cdc: 687b ldr r3, [r7, #4] 8006cde: f003 0310 and.w r3, r3, #16 8006ce2: 409a lsls r2, r3 8006ce4: 68fb ldr r3, [r7, #12] 8006ce6: 681b ldr r3, [r3, #0] 8006ce8: 430a orrs r2, r1 8006cea: 649a str r2, [r3, #72] @ 0x48 (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); /* RefreshTime */ MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), 8006cec: 68fb ldr r3, [r7, #12] 8006cee: 681b ldr r3, [r3, #0] 8006cf0: 6cda ldr r2, [r3, #76] @ 0x4c 8006cf2: 687b ldr r3, [r7, #4] 8006cf4: f003 0310 and.w r3, r3, #16 8006cf8: 21ff movs r1, #255 @ 0xff 8006cfa: fa01 f303 lsl.w r3, r1, r3 8006cfe: 43db mvns r3, r3 8006d00: ea02 0103 and.w r1, r2, r3 8006d04: 68bb ldr r3, [r7, #8] 8006d06: 6a1a ldr r2, [r3, #32] 8006d08: 687b ldr r3, [r7, #4] 8006d0a: f003 0310 and.w r3, r3, #16 8006d0e: 409a lsls r2, r3 8006d10: 68fb ldr r3, [r7, #12] 8006d12: 681b ldr r3, [r3, #0] 8006d14: 430a orrs r2, r1 8006d16: 64da str r2, [r3, #76] @ 0x4c (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); } if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) 8006d18: 68bb ldr r3, [r7, #8] 8006d1a: 691b ldr r3, [r3, #16] 8006d1c: 2b01 cmp r3, #1 8006d1e: d11d bne.n 8006d5c /* USER TRIMMING */ { /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; 8006d20: 68fb ldr r3, [r7, #12] 8006d22: 681b ldr r3, [r3, #0] 8006d24: 6b9b ldr r3, [r3, #56] @ 0x38 8006d26: 61bb str r3, [r7, #24] /* Clear trimming value */ tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); 8006d28: 687b ldr r3, [r7, #4] 8006d2a: f003 0310 and.w r3, r3, #16 8006d2e: 221f movs r2, #31 8006d30: fa02 f303 lsl.w r3, r2, r3 8006d34: 43db mvns r3, r3 8006d36: 69ba ldr r2, [r7, #24] 8006d38: 4013 ands r3, r2 8006d3a: 61bb str r3, [r7, #24] /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; 8006d3c: 68bb ldr r3, [r7, #8] 8006d3e: 695b ldr r3, [r3, #20] 8006d40: 617b str r3, [r7, #20] /* Calculate CCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8006d42: 687b ldr r3, [r7, #4] 8006d44: f003 0310 and.w r3, r3, #16 8006d48: 697a ldr r2, [r7, #20] 8006d4a: fa02 f303 lsl.w r3, r2, r3 8006d4e: 69ba ldr r2, [r7, #24] 8006d50: 4313 orrs r3, r2 8006d52: 61bb str r3, [r7, #24] /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; 8006d54: 68fb ldr r3, [r7, #12] 8006d56: 681b ldr r3, [r3, #0] 8006d58: 69ba ldr r2, [r7, #24] 8006d5a: 639a str r2, [r3, #56] @ 0x38 } /* else factory trimming is used (factory setting are available at reset)*/ /* SW Nothing has nothing to do */ /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; 8006d5c: 68fb ldr r3, [r7, #12] 8006d5e: 681b ldr r3, [r3, #0] 8006d60: 6bdb ldr r3, [r3, #60] @ 0x3c 8006d62: 61bb str r3, [r7, #24] /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); 8006d64: 687b ldr r3, [r7, #4] 8006d66: f003 0310 and.w r3, r3, #16 8006d6a: 2207 movs r2, #7 8006d6c: fa02 f303 lsl.w r3, r2, r3 8006d70: 43db mvns r3, r3 8006d72: 69ba ldr r2, [r7, #24] 8006d74: 4013 ands r3, r2 8006d76: 61bb str r3, [r7, #24] /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) 8006d78: 68bb ldr r3, [r7, #8] 8006d7a: 68db ldr r3, [r3, #12] 8006d7c: 2b01 cmp r3, #1 8006d7e: d102 bne.n 8006d86 { connectOnChip = 0x00000000UL; 8006d80: 2300 movs r3, #0 8006d82: 627b str r3, [r7, #36] @ 0x24 8006d84: e00f b.n 8006da6 } else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL) 8006d86: 68bb ldr r3, [r7, #8] 8006d88: 68db ldr r3, [r3, #12] 8006d8a: 2b02 cmp r3, #2 8006d8c: d102 bne.n 8006d94 { connectOnChip = DAC_MCR_MODE1_0; 8006d8e: 2301 movs r3, #1 8006d90: 627b str r3, [r7, #36] @ 0x24 8006d92: e008 b.n 8006da6 } else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */ { if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) 8006d94: 68bb ldr r3, [r7, #8] 8006d96: 689b ldr r3, [r3, #8] 8006d98: 2b00 cmp r3, #0 8006d9a: d102 bne.n 8006da2 { connectOnChip = DAC_MCR_MODE1_0; 8006d9c: 2301 movs r3, #1 8006d9e: 627b str r3, [r7, #36] @ 0x24 8006da0: e001 b.n 8006da6 } else { connectOnChip = 0x00000000UL; 8006da2: 2300 movs r3, #0 8006da4: 627b str r3, [r7, #36] @ 0x24 } } tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); 8006da6: 68bb ldr r3, [r7, #8] 8006da8: 681a ldr r2, [r3, #0] 8006daa: 68bb ldr r3, [r7, #8] 8006dac: 689b ldr r3, [r3, #8] 8006dae: 4313 orrs r3, r2 8006db0: 6a7a ldr r2, [r7, #36] @ 0x24 8006db2: 4313 orrs r3, r2 8006db4: 617b str r3, [r7, #20] /* Calculate MCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8006db6: 687b ldr r3, [r7, #4] 8006db8: f003 0310 and.w r3, r3, #16 8006dbc: 697a ldr r2, [r7, #20] 8006dbe: fa02 f303 lsl.w r3, r2, r3 8006dc2: 69ba ldr r2, [r7, #24] 8006dc4: 4313 orrs r3, r2 8006dc6: 61bb str r3, [r7, #24] /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; 8006dc8: 68fb ldr r3, [r7, #12] 8006dca: 681b ldr r3, [r3, #0] 8006dcc: 69ba ldr r2, [r7, #24] 8006dce: 63da str r2, [r3, #60] @ 0x3c /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); 8006dd0: 68fb ldr r3, [r7, #12] 8006dd2: 681b ldr r3, [r3, #0] 8006dd4: 6819 ldr r1, [r3, #0] 8006dd6: 687b ldr r3, [r7, #4] 8006dd8: f003 0310 and.w r3, r3, #16 8006ddc: f44f 4280 mov.w r2, #16384 @ 0x4000 8006de0: fa02 f303 lsl.w r3, r2, r3 8006de4: 43da mvns r2, r3 8006de6: 68fb ldr r3, [r7, #12] 8006de8: 681b ldr r3, [r3, #0] 8006dea: 400a ands r2, r1 8006dec: 601a str r2, [r3, #0] /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; 8006dee: 68fb ldr r3, [r7, #12] 8006df0: 681b ldr r3, [r3, #0] 8006df2: 681b ldr r3, [r3, #0] 8006df4: 61bb str r3, [r7, #24] /* Clear TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); 8006df6: 687b ldr r3, [r7, #4] 8006df8: f003 0310 and.w r3, r3, #16 8006dfc: f640 72fe movw r2, #4094 @ 0xffe 8006e00: fa02 f303 lsl.w r3, r2, r3 8006e04: 43db mvns r3, r3 8006e06: 69ba ldr r2, [r7, #24] 8006e08: 4013 ands r3, r2 8006e0a: 61bb str r3, [r7, #24] /* Configure for the selected DAC channel: trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ tmpreg2 = sConfig->DAC_Trigger; 8006e0c: 68bb ldr r3, [r7, #8] 8006e0e: 685b ldr r3, [r3, #4] 8006e10: 617b str r3, [r7, #20] /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8006e12: 687b ldr r3, [r7, #4] 8006e14: f003 0310 and.w r3, r3, #16 8006e18: 697a ldr r2, [r7, #20] 8006e1a: fa02 f303 lsl.w r3, r2, r3 8006e1e: 69ba ldr r2, [r7, #24] 8006e20: 4313 orrs r3, r2 8006e22: 61bb str r3, [r7, #24] /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; 8006e24: 68fb ldr r3, [r7, #12] 8006e26: 681b ldr r3, [r3, #0] 8006e28: 69ba ldr r2, [r7, #24] 8006e2a: 601a str r2, [r3, #0] /* Disable wave generation */ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); 8006e2c: 68fb ldr r3, [r7, #12] 8006e2e: 681b ldr r3, [r3, #0] 8006e30: 6819 ldr r1, [r3, #0] 8006e32: 687b ldr r3, [r7, #4] 8006e34: f003 0310 and.w r3, r3, #16 8006e38: 22c0 movs r2, #192 @ 0xc0 8006e3a: fa02 f303 lsl.w r3, r2, r3 8006e3e: 43da mvns r2, r3 8006e40: 68fb ldr r3, [r7, #12] 8006e42: 681b ldr r3, [r3, #0] 8006e44: 400a ands r2, r1 8006e46: 601a str r2, [r3, #0] /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 8006e48: 68fb ldr r3, [r7, #12] 8006e4a: 2201 movs r2, #1 8006e4c: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 8006e4e: 68fb ldr r3, [r7, #12] 8006e50: 2200 movs r2, #0 8006e52: 715a strb r2, [r3, #5] /* Return function status */ return status; 8006e54: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 } 8006e58: 4618 mov r0, r3 8006e5a: 3728 adds r7, #40 @ 0x28 8006e5c: 46bd mov sp, r7 8006e5e: bd80 pop {r7, pc} 8006e60: 20008000 .word 0x20008000 08006e64 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) { 8006e64: b480 push {r7} 8006e66: b083 sub sp, #12 8006e68: af00 add r7, sp, #0 8006e6a: 6078 str r0, [r7, #4] UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file */ } 8006e6c: bf00 nop 8006e6e: 370c adds r7, #12 8006e70: 46bd mov sp, r7 8006e72: f85d 7b04 ldr.w r7, [sp], #4 8006e76: 4770 bx lr 08006e78 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8006e78: b580 push {r7, lr} 8006e7a: b086 sub sp, #24 8006e7c: af00 add r7, sp, #0 8006e7e: 6078 str r0, [r7, #4] uint32_t registerValue; uint32_t tickstart = HAL_GetTick(); 8006e80: f7fd fdf0 bl 8004a64 8006e84: 6138 str r0, [r7, #16] DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 8006e86: 687b ldr r3, [r7, #4] 8006e88: 2b00 cmp r3, #0 8006e8a: d101 bne.n 8006e90 { return HAL_ERROR; 8006e8c: 2301 movs r3, #1 8006e8e: e316 b.n 80074be assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8006e90: 687b ldr r3, [r7, #4] 8006e92: 681b ldr r3, [r3, #0] 8006e94: 4a66 ldr r2, [pc, #408] @ (8007030 ) 8006e96: 4293 cmp r3, r2 8006e98: d04a beq.n 8006f30 8006e9a: 687b ldr r3, [r7, #4] 8006e9c: 681b ldr r3, [r3, #0] 8006e9e: 4a65 ldr r2, [pc, #404] @ (8007034 ) 8006ea0: 4293 cmp r3, r2 8006ea2: d045 beq.n 8006f30 8006ea4: 687b ldr r3, [r7, #4] 8006ea6: 681b ldr r3, [r3, #0] 8006ea8: 4a63 ldr r2, [pc, #396] @ (8007038 ) 8006eaa: 4293 cmp r3, r2 8006eac: d040 beq.n 8006f30 8006eae: 687b ldr r3, [r7, #4] 8006eb0: 681b ldr r3, [r3, #0] 8006eb2: 4a62 ldr r2, [pc, #392] @ (800703c ) 8006eb4: 4293 cmp r3, r2 8006eb6: d03b beq.n 8006f30 8006eb8: 687b ldr r3, [r7, #4] 8006eba: 681b ldr r3, [r3, #0] 8006ebc: 4a60 ldr r2, [pc, #384] @ (8007040 ) 8006ebe: 4293 cmp r3, r2 8006ec0: d036 beq.n 8006f30 8006ec2: 687b ldr r3, [r7, #4] 8006ec4: 681b ldr r3, [r3, #0] 8006ec6: 4a5f ldr r2, [pc, #380] @ (8007044 ) 8006ec8: 4293 cmp r3, r2 8006eca: d031 beq.n 8006f30 8006ecc: 687b ldr r3, [r7, #4] 8006ece: 681b ldr r3, [r3, #0] 8006ed0: 4a5d ldr r2, [pc, #372] @ (8007048 ) 8006ed2: 4293 cmp r3, r2 8006ed4: d02c beq.n 8006f30 8006ed6: 687b ldr r3, [r7, #4] 8006ed8: 681b ldr r3, [r3, #0] 8006eda: 4a5c ldr r2, [pc, #368] @ (800704c ) 8006edc: 4293 cmp r3, r2 8006ede: d027 beq.n 8006f30 8006ee0: 687b ldr r3, [r7, #4] 8006ee2: 681b ldr r3, [r3, #0] 8006ee4: 4a5a ldr r2, [pc, #360] @ (8007050 ) 8006ee6: 4293 cmp r3, r2 8006ee8: d022 beq.n 8006f30 8006eea: 687b ldr r3, [r7, #4] 8006eec: 681b ldr r3, [r3, #0] 8006eee: 4a59 ldr r2, [pc, #356] @ (8007054 ) 8006ef0: 4293 cmp r3, r2 8006ef2: d01d beq.n 8006f30 8006ef4: 687b ldr r3, [r7, #4] 8006ef6: 681b ldr r3, [r3, #0] 8006ef8: 4a57 ldr r2, [pc, #348] @ (8007058 ) 8006efa: 4293 cmp r3, r2 8006efc: d018 beq.n 8006f30 8006efe: 687b ldr r3, [r7, #4] 8006f00: 681b ldr r3, [r3, #0] 8006f02: 4a56 ldr r2, [pc, #344] @ (800705c ) 8006f04: 4293 cmp r3, r2 8006f06: d013 beq.n 8006f30 8006f08: 687b ldr r3, [r7, #4] 8006f0a: 681b ldr r3, [r3, #0] 8006f0c: 4a54 ldr r2, [pc, #336] @ (8007060 ) 8006f0e: 4293 cmp r3, r2 8006f10: d00e beq.n 8006f30 8006f12: 687b ldr r3, [r7, #4] 8006f14: 681b ldr r3, [r3, #0] 8006f16: 4a53 ldr r2, [pc, #332] @ (8007064 ) 8006f18: 4293 cmp r3, r2 8006f1a: d009 beq.n 8006f30 8006f1c: 687b ldr r3, [r7, #4] 8006f1e: 681b ldr r3, [r3, #0] 8006f20: 4a51 ldr r2, [pc, #324] @ (8007068 ) 8006f22: 4293 cmp r3, r2 8006f24: d004 beq.n 8006f30 8006f26: 687b ldr r3, [r7, #4] 8006f28: 681b ldr r3, [r3, #0] 8006f2a: 4a50 ldr r2, [pc, #320] @ (800706c ) 8006f2c: 4293 cmp r3, r2 8006f2e: d101 bne.n 8006f34 8006f30: 2301 movs r3, #1 8006f32: e000 b.n 8006f36 8006f34: 2300 movs r3, #0 8006f36: 2b00 cmp r3, #0 8006f38: f000 813b beq.w 80071b2 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8006f3c: 687b ldr r3, [r7, #4] 8006f3e: 2202 movs r2, #2 8006f40: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8006f44: 687b ldr r3, [r7, #4] 8006f46: 2200 movs r2, #0 8006f48: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8006f4c: 687b ldr r3, [r7, #4] 8006f4e: 681b ldr r3, [r3, #0] 8006f50: 4a37 ldr r2, [pc, #220] @ (8007030 ) 8006f52: 4293 cmp r3, r2 8006f54: d04a beq.n 8006fec 8006f56: 687b ldr r3, [r7, #4] 8006f58: 681b ldr r3, [r3, #0] 8006f5a: 4a36 ldr r2, [pc, #216] @ (8007034 ) 8006f5c: 4293 cmp r3, r2 8006f5e: d045 beq.n 8006fec 8006f60: 687b ldr r3, [r7, #4] 8006f62: 681b ldr r3, [r3, #0] 8006f64: 4a34 ldr r2, [pc, #208] @ (8007038 ) 8006f66: 4293 cmp r3, r2 8006f68: d040 beq.n 8006fec 8006f6a: 687b ldr r3, [r7, #4] 8006f6c: 681b ldr r3, [r3, #0] 8006f6e: 4a33 ldr r2, [pc, #204] @ (800703c ) 8006f70: 4293 cmp r3, r2 8006f72: d03b beq.n 8006fec 8006f74: 687b ldr r3, [r7, #4] 8006f76: 681b ldr r3, [r3, #0] 8006f78: 4a31 ldr r2, [pc, #196] @ (8007040 ) 8006f7a: 4293 cmp r3, r2 8006f7c: d036 beq.n 8006fec 8006f7e: 687b ldr r3, [r7, #4] 8006f80: 681b ldr r3, [r3, #0] 8006f82: 4a30 ldr r2, [pc, #192] @ (8007044 ) 8006f84: 4293 cmp r3, r2 8006f86: d031 beq.n 8006fec 8006f88: 687b ldr r3, [r7, #4] 8006f8a: 681b ldr r3, [r3, #0] 8006f8c: 4a2e ldr r2, [pc, #184] @ (8007048 ) 8006f8e: 4293 cmp r3, r2 8006f90: d02c beq.n 8006fec 8006f92: 687b ldr r3, [r7, #4] 8006f94: 681b ldr r3, [r3, #0] 8006f96: 4a2d ldr r2, [pc, #180] @ (800704c ) 8006f98: 4293 cmp r3, r2 8006f9a: d027 beq.n 8006fec 8006f9c: 687b ldr r3, [r7, #4] 8006f9e: 681b ldr r3, [r3, #0] 8006fa0: 4a2b ldr r2, [pc, #172] @ (8007050 ) 8006fa2: 4293 cmp r3, r2 8006fa4: d022 beq.n 8006fec 8006fa6: 687b ldr r3, [r7, #4] 8006fa8: 681b ldr r3, [r3, #0] 8006faa: 4a2a ldr r2, [pc, #168] @ (8007054 ) 8006fac: 4293 cmp r3, r2 8006fae: d01d beq.n 8006fec 8006fb0: 687b ldr r3, [r7, #4] 8006fb2: 681b ldr r3, [r3, #0] 8006fb4: 4a28 ldr r2, [pc, #160] @ (8007058 ) 8006fb6: 4293 cmp r3, r2 8006fb8: d018 beq.n 8006fec 8006fba: 687b ldr r3, [r7, #4] 8006fbc: 681b ldr r3, [r3, #0] 8006fbe: 4a27 ldr r2, [pc, #156] @ (800705c ) 8006fc0: 4293 cmp r3, r2 8006fc2: d013 beq.n 8006fec 8006fc4: 687b ldr r3, [r7, #4] 8006fc6: 681b ldr r3, [r3, #0] 8006fc8: 4a25 ldr r2, [pc, #148] @ (8007060 ) 8006fca: 4293 cmp r3, r2 8006fcc: d00e beq.n 8006fec 8006fce: 687b ldr r3, [r7, #4] 8006fd0: 681b ldr r3, [r3, #0] 8006fd2: 4a24 ldr r2, [pc, #144] @ (8007064 ) 8006fd4: 4293 cmp r3, r2 8006fd6: d009 beq.n 8006fec 8006fd8: 687b ldr r3, [r7, #4] 8006fda: 681b ldr r3, [r3, #0] 8006fdc: 4a22 ldr r2, [pc, #136] @ (8007068 ) 8006fde: 4293 cmp r3, r2 8006fe0: d004 beq.n 8006fec 8006fe2: 687b ldr r3, [r7, #4] 8006fe4: 681b ldr r3, [r3, #0] 8006fe6: 4a21 ldr r2, [pc, #132] @ (800706c ) 8006fe8: 4293 cmp r3, r2 8006fea: d108 bne.n 8006ffe 8006fec: 687b ldr r3, [r7, #4] 8006fee: 681b ldr r3, [r3, #0] 8006ff0: 681a ldr r2, [r3, #0] 8006ff2: 687b ldr r3, [r7, #4] 8006ff4: 681b ldr r3, [r3, #0] 8006ff6: f022 0201 bic.w r2, r2, #1 8006ffa: 601a str r2, [r3, #0] 8006ffc: e007 b.n 800700e 8006ffe: 687b ldr r3, [r7, #4] 8007000: 681b ldr r3, [r3, #0] 8007002: 681a ldr r2, [r3, #0] 8007004: 687b ldr r3, [r7, #4] 8007006: 681b ldr r3, [r3, #0] 8007008: f022 0201 bic.w r2, r2, #1 800700c: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 800700e: e02f b.n 8007070 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8007010: f7fd fd28 bl 8004a64 8007014: 4602 mov r2, r0 8007016: 693b ldr r3, [r7, #16] 8007018: 1ad3 subs r3, r2, r3 800701a: 2b05 cmp r3, #5 800701c: d928 bls.n 8007070 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 800701e: 687b ldr r3, [r7, #4] 8007020: 2220 movs r2, #32 8007022: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 8007024: 687b ldr r3, [r7, #4] 8007026: 2203 movs r2, #3 8007028: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 800702c: 2301 movs r3, #1 800702e: e246 b.n 80074be 8007030: 40020010 .word 0x40020010 8007034: 40020028 .word 0x40020028 8007038: 40020040 .word 0x40020040 800703c: 40020058 .word 0x40020058 8007040: 40020070 .word 0x40020070 8007044: 40020088 .word 0x40020088 8007048: 400200a0 .word 0x400200a0 800704c: 400200b8 .word 0x400200b8 8007050: 40020410 .word 0x40020410 8007054: 40020428 .word 0x40020428 8007058: 40020440 .word 0x40020440 800705c: 40020458 .word 0x40020458 8007060: 40020470 .word 0x40020470 8007064: 40020488 .word 0x40020488 8007068: 400204a0 .word 0x400204a0 800706c: 400204b8 .word 0x400204b8 while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 8007070: 687b ldr r3, [r7, #4] 8007072: 681b ldr r3, [r3, #0] 8007074: 681b ldr r3, [r3, #0] 8007076: f003 0301 and.w r3, r3, #1 800707a: 2b00 cmp r3, #0 800707c: d1c8 bne.n 8007010 } } /* Get the CR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; 800707e: 687b ldr r3, [r7, #4] 8007080: 681b ldr r3, [r3, #0] 8007082: 681b ldr r3, [r3, #0] 8007084: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 8007086: 697a ldr r2, [r7, #20] 8007088: 4b83 ldr r3, [pc, #524] @ (8007298 ) 800708a: 4013 ands r3, r2 800708c: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ registerValue |= hdma->Init.Direction | 800708e: 687b ldr r3, [r7, #4] 8007090: 689a ldr r2, [r3, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 8007092: 687b ldr r3, [r7, #4] 8007094: 68db ldr r3, [r3, #12] registerValue |= hdma->Init.Direction | 8007096: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8007098: 687b ldr r3, [r7, #4] 800709a: 691b ldr r3, [r3, #16] 800709c: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800709e: 687b ldr r3, [r7, #4] 80070a0: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 80070a2: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80070a4: 687b ldr r3, [r7, #4] 80070a6: 699b ldr r3, [r3, #24] 80070a8: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 80070aa: 687b ldr r3, [r7, #4] 80070ac: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80070ae: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 80070b0: 687b ldr r3, [r7, #4] 80070b2: 6a1b ldr r3, [r3, #32] 80070b4: 4313 orrs r3, r2 registerValue |= hdma->Init.Direction | 80070b6: 697a ldr r2, [r7, #20] 80070b8: 4313 orrs r3, r2 80070ba: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 80070bc: 687b ldr r3, [r7, #4] 80070be: 6a5b ldr r3, [r3, #36] @ 0x24 80070c0: 2b04 cmp r3, #4 80070c2: d107 bne.n 80070d4 { /* Get memory burst and peripheral burst */ registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 80070c4: 687b ldr r3, [r7, #4] 80070c6: 6ada ldr r2, [r3, #44] @ 0x2c 80070c8: 687b ldr r3, [r7, #4] 80070ca: 6b1b ldr r3, [r3, #48] @ 0x30 80070cc: 4313 orrs r3, r2 80070ce: 697a ldr r2, [r7, #20] 80070d0: 4313 orrs r3, r2 80070d2: 617b str r3, [r7, #20] } /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be lock when transferring data to/from USART/UART */ #if (STM32H7_DEV_ID == 0x450UL) if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) 80070d4: 4b71 ldr r3, [pc, #452] @ (800729c ) 80070d6: 681a ldr r2, [r3, #0] 80070d8: 4b71 ldr r3, [pc, #452] @ (80072a0 ) 80070da: 4013 ands r3, r2 80070dc: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80070e0: d328 bcc.n 8007134 { #endif /* STM32H7_DEV_ID == 0x450UL */ if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) 80070e2: 687b ldr r3, [r7, #4] 80070e4: 685b ldr r3, [r3, #4] 80070e6: 2b28 cmp r3, #40 @ 0x28 80070e8: d903 bls.n 80070f2 80070ea: 687b ldr r3, [r7, #4] 80070ec: 685b ldr r3, [r3, #4] 80070ee: 2b2e cmp r3, #46 @ 0x2e 80070f0: d917 bls.n 8007122 80070f2: 687b ldr r3, [r7, #4] 80070f4: 685b ldr r3, [r3, #4] 80070f6: 2b3e cmp r3, #62 @ 0x3e 80070f8: d903 bls.n 8007102 80070fa: 687b ldr r3, [r7, #4] 80070fc: 685b ldr r3, [r3, #4] 80070fe: 2b42 cmp r3, #66 @ 0x42 8007100: d90f bls.n 8007122 8007102: 687b ldr r3, [r7, #4] 8007104: 685b ldr r3, [r3, #4] 8007106: 2b46 cmp r3, #70 @ 0x46 8007108: d903 bls.n 8007112 800710a: 687b ldr r3, [r7, #4] 800710c: 685b ldr r3, [r3, #4] 800710e: 2b48 cmp r3, #72 @ 0x48 8007110: d907 bls.n 8007122 8007112: 687b ldr r3, [r7, #4] 8007114: 685b ldr r3, [r3, #4] 8007116: 2b4e cmp r3, #78 @ 0x4e 8007118: d905 bls.n 8007126 800711a: 687b ldr r3, [r7, #4] 800711c: 685b ldr r3, [r3, #4] 800711e: 2b52 cmp r3, #82 @ 0x52 8007120: d801 bhi.n 8007126 8007122: 2301 movs r3, #1 8007124: e000 b.n 8007128 8007126: 2300 movs r3, #0 8007128: 2b00 cmp r3, #0 800712a: d003 beq.n 8007134 { registerValue |= DMA_SxCR_TRBUFF; 800712c: 697b ldr r3, [r7, #20] 800712e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8007132: 617b str r3, [r7, #20] #if (STM32H7_DEV_ID == 0x450UL) } #endif /* STM32H7_DEV_ID == 0x450UL */ /* Write to DMA Stream CR register */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; 8007134: 687b ldr r3, [r7, #4] 8007136: 681b ldr r3, [r3, #0] 8007138: 697a ldr r2, [r7, #20] 800713a: 601a str r2, [r3, #0] /* Get the FCR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; 800713c: 687b ldr r3, [r7, #4] 800713e: 681b ldr r3, [r3, #0] 8007140: 695b ldr r3, [r3, #20] 8007142: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8007144: 697b ldr r3, [r7, #20] 8007146: f023 0307 bic.w r3, r3, #7 800714a: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ registerValue |= hdma->Init.FIFOMode; 800714c: 687b ldr r3, [r7, #4] 800714e: 6a5b ldr r3, [r3, #36] @ 0x24 8007150: 697a ldr r2, [r7, #20] 8007152: 4313 orrs r3, r2 8007154: 617b str r3, [r7, #20] /* the FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8007156: 687b ldr r3, [r7, #4] 8007158: 6a5b ldr r3, [r3, #36] @ 0x24 800715a: 2b04 cmp r3, #4 800715c: d117 bne.n 800718e { /* Get the FIFO threshold */ registerValue |= hdma->Init.FIFOThreshold; 800715e: 687b ldr r3, [r7, #4] 8007160: 6a9b ldr r3, [r3, #40] @ 0x28 8007162: 697a ldr r2, [r7, #20] 8007164: 4313 orrs r3, r2 8007166: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 */ if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) 8007168: 687b ldr r3, [r7, #4] 800716a: 6adb ldr r3, [r3, #44] @ 0x2c 800716c: 2b00 cmp r3, #0 800716e: d00e beq.n 800718e { if (DMA_CheckFifoParam(hdma) != HAL_OK) 8007170: 6878 ldr r0, [r7, #4] 8007172: f002 fb33 bl 80097dc 8007176: 4603 mov r3, r0 8007178: 2b00 cmp r3, #0 800717a: d008 beq.n 800718e { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 800717c: 687b ldr r3, [r7, #4] 800717e: 2240 movs r2, #64 @ 0x40 8007180: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8007182: 687b ldr r3, [r7, #4] 8007184: 2201 movs r2, #1 8007186: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 800718a: 2301 movs r3, #1 800718c: e197 b.n 80074be } } } /* Write to DMA Stream FCR */ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; 800718e: 687b ldr r3, [r7, #4] 8007190: 681b ldr r3, [r3, #0] 8007192: 697a ldr r2, [r7, #20] 8007194: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8007196: 6878 ldr r0, [r7, #4] 8007198: f002 fa6e bl 8009678 800719c: 4603 mov r3, r0 800719e: 60bb str r3, [r7, #8] /* Clear all interrupt flags */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 80071a0: 687b ldr r3, [r7, #4] 80071a2: 6ddb ldr r3, [r3, #92] @ 0x5c 80071a4: f003 031f and.w r3, r3, #31 80071a8: 223f movs r2, #63 @ 0x3f 80071aa: 409a lsls r2, r3 80071ac: 68bb ldr r3, [r7, #8] 80071ae: 609a str r2, [r3, #8] 80071b0: e0cd b.n 800734e } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 80071b2: 687b ldr r3, [r7, #4] 80071b4: 681b ldr r3, [r3, #0] 80071b6: 4a3b ldr r2, [pc, #236] @ (80072a4 ) 80071b8: 4293 cmp r3, r2 80071ba: d022 beq.n 8007202 80071bc: 687b ldr r3, [r7, #4] 80071be: 681b ldr r3, [r3, #0] 80071c0: 4a39 ldr r2, [pc, #228] @ (80072a8 ) 80071c2: 4293 cmp r3, r2 80071c4: d01d beq.n 8007202 80071c6: 687b ldr r3, [r7, #4] 80071c8: 681b ldr r3, [r3, #0] 80071ca: 4a38 ldr r2, [pc, #224] @ (80072ac ) 80071cc: 4293 cmp r3, r2 80071ce: d018 beq.n 8007202 80071d0: 687b ldr r3, [r7, #4] 80071d2: 681b ldr r3, [r3, #0] 80071d4: 4a36 ldr r2, [pc, #216] @ (80072b0 ) 80071d6: 4293 cmp r3, r2 80071d8: d013 beq.n 8007202 80071da: 687b ldr r3, [r7, #4] 80071dc: 681b ldr r3, [r3, #0] 80071de: 4a35 ldr r2, [pc, #212] @ (80072b4 ) 80071e0: 4293 cmp r3, r2 80071e2: d00e beq.n 8007202 80071e4: 687b ldr r3, [r7, #4] 80071e6: 681b ldr r3, [r3, #0] 80071e8: 4a33 ldr r2, [pc, #204] @ (80072b8 ) 80071ea: 4293 cmp r3, r2 80071ec: d009 beq.n 8007202 80071ee: 687b ldr r3, [r7, #4] 80071f0: 681b ldr r3, [r3, #0] 80071f2: 4a32 ldr r2, [pc, #200] @ (80072bc ) 80071f4: 4293 cmp r3, r2 80071f6: d004 beq.n 8007202 80071f8: 687b ldr r3, [r7, #4] 80071fa: 681b ldr r3, [r3, #0] 80071fc: 4a30 ldr r2, [pc, #192] @ (80072c0 ) 80071fe: 4293 cmp r3, r2 8007200: d101 bne.n 8007206 8007202: 2301 movs r3, #1 8007204: e000 b.n 8007208 8007206: 2300 movs r3, #0 8007208: 2b00 cmp r3, #0 800720a: f000 8097 beq.w 800733c { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 800720e: 687b ldr r3, [r7, #4] 8007210: 681b ldr r3, [r3, #0] 8007212: 4a24 ldr r2, [pc, #144] @ (80072a4 ) 8007214: 4293 cmp r3, r2 8007216: d021 beq.n 800725c 8007218: 687b ldr r3, [r7, #4] 800721a: 681b ldr r3, [r3, #0] 800721c: 4a22 ldr r2, [pc, #136] @ (80072a8 ) 800721e: 4293 cmp r3, r2 8007220: d01c beq.n 800725c 8007222: 687b ldr r3, [r7, #4] 8007224: 681b ldr r3, [r3, #0] 8007226: 4a21 ldr r2, [pc, #132] @ (80072ac ) 8007228: 4293 cmp r3, r2 800722a: d017 beq.n 800725c 800722c: 687b ldr r3, [r7, #4] 800722e: 681b ldr r3, [r3, #0] 8007230: 4a1f ldr r2, [pc, #124] @ (80072b0 ) 8007232: 4293 cmp r3, r2 8007234: d012 beq.n 800725c 8007236: 687b ldr r3, [r7, #4] 8007238: 681b ldr r3, [r3, #0] 800723a: 4a1e ldr r2, [pc, #120] @ (80072b4 ) 800723c: 4293 cmp r3, r2 800723e: d00d beq.n 800725c 8007240: 687b ldr r3, [r7, #4] 8007242: 681b ldr r3, [r3, #0] 8007244: 4a1c ldr r2, [pc, #112] @ (80072b8 ) 8007246: 4293 cmp r3, r2 8007248: d008 beq.n 800725c 800724a: 687b ldr r3, [r7, #4] 800724c: 681b ldr r3, [r3, #0] 800724e: 4a1b ldr r2, [pc, #108] @ (80072bc ) 8007250: 4293 cmp r3, r2 8007252: d003 beq.n 800725c 8007254: 687b ldr r3, [r7, #4] 8007256: 681b ldr r3, [r3, #0] 8007258: 4a19 ldr r2, [pc, #100] @ (80072c0 ) 800725a: 4293 cmp r3, r2 /* Check the request parameter */ assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 800725c: 687b ldr r3, [r7, #4] 800725e: 2202 movs r2, #2 8007260: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8007264: 687b ldr r3, [r7, #4] 8007266: 2200 movs r2, #0 8007268: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Get the CR register value */ registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; 800726c: 687b ldr r3, [r7, #4] 800726e: 681b ldr r3, [r3, #0] 8007270: 681b ldr r3, [r3, #0] 8007272: 617b str r3, [r7, #20] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */ registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ 8007274: 697a ldr r2, [r7, #20] 8007276: 4b13 ldr r3, [pc, #76] @ (80072c4 ) 8007278: 4013 ands r3, r2 800727a: 617b str r3, [r7, #20] BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \ BDMA_CCR_CT)); /* Prepare the DMA Channel configuration */ registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 800727c: 687b ldr r3, [r7, #4] 800727e: 689b ldr r3, [r3, #8] 8007280: 2b40 cmp r3, #64 @ 0x40 8007282: d021 beq.n 80072c8 8007284: 687b ldr r3, [r7, #4] 8007286: 689b ldr r3, [r3, #8] 8007288: 2b80 cmp r3, #128 @ 0x80 800728a: d102 bne.n 8007292 800728c: f44f 4380 mov.w r3, #16384 @ 0x4000 8007290: e01b b.n 80072ca 8007292: 2300 movs r3, #0 8007294: e019 b.n 80072ca 8007296: bf00 nop 8007298: fe10803f .word 0xfe10803f 800729c: 5c001000 .word 0x5c001000 80072a0: ffff0000 .word 0xffff0000 80072a4: 58025408 .word 0x58025408 80072a8: 5802541c .word 0x5802541c 80072ac: 58025430 .word 0x58025430 80072b0: 58025444 .word 0x58025444 80072b4: 58025458 .word 0x58025458 80072b8: 5802546c .word 0x5802546c 80072bc: 58025480 .word 0x58025480 80072c0: 58025494 .word 0x58025494 80072c4: fffe000f .word 0xfffe000f 80072c8: 2310 movs r3, #16 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 80072ca: 687a ldr r2, [r7, #4] 80072cc: 68d2 ldr r2, [r2, #12] 80072ce: 08d2 lsrs r2, r2, #3 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 80072d0: 431a orrs r2, r3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 80072d2: 687b ldr r3, [r7, #4] 80072d4: 691b ldr r3, [r3, #16] 80072d6: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 80072d8: 431a orrs r2, r3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 80072da: 687b ldr r3, [r7, #4] 80072dc: 695b ldr r3, [r3, #20] 80072de: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 80072e0: 431a orrs r2, r3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 80072e2: 687b ldr r3, [r7, #4] 80072e4: 699b ldr r3, [r3, #24] 80072e6: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 80072e8: 431a orrs r2, r3 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 80072ea: 687b ldr r3, [r7, #4] 80072ec: 69db ldr r3, [r3, #28] 80072ee: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 80072f0: 431a orrs r2, r3 DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); 80072f2: 687b ldr r3, [r7, #4] 80072f4: 6a1b ldr r3, [r3, #32] 80072f6: 091b lsrs r3, r3, #4 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 80072f8: 4313 orrs r3, r2 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 80072fa: 697a ldr r2, [r7, #20] 80072fc: 4313 orrs r3, r2 80072fe: 617b str r3, [r7, #20] /* Write to DMA Channel CR register */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; 8007300: 687b ldr r3, [r7, #4] 8007302: 681b ldr r3, [r3, #0] 8007304: 697a ldr r2, [r7, #20] 8007306: 601a str r2, [r3, #0] /* calculation of the channel index */ hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; 8007308: 687b ldr r3, [r7, #4] 800730a: 681b ldr r3, [r3, #0] 800730c: 461a mov r2, r3 800730e: 4b6e ldr r3, [pc, #440] @ (80074c8 ) 8007310: 4413 add r3, r2 8007312: 4a6e ldr r2, [pc, #440] @ (80074cc ) 8007314: fba2 2303 umull r2, r3, r2, r3 8007318: 091b lsrs r3, r3, #4 800731a: 009a lsls r2, r3, #2 800731c: 687b ldr r3, [r7, #4] 800731e: 65da str r2, [r3, #92] @ 0x5c /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8007320: 6878 ldr r0, [r7, #4] 8007322: f002 f9a9 bl 8009678 8007326: 4603 mov r3, r0 8007328: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 800732a: 687b ldr r3, [r7, #4] 800732c: 6ddb ldr r3, [r3, #92] @ 0x5c 800732e: f003 031f and.w r3, r3, #31 8007332: 2201 movs r2, #1 8007334: 409a lsls r2, r3 8007336: 68fb ldr r3, [r7, #12] 8007338: 605a str r2, [r3, #4] 800733a: e008 b.n 800734e } else { hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 800733c: 687b ldr r3, [r7, #4] 800733e: 2240 movs r2, #64 @ 0x40 8007340: 655a str r2, [r3, #84] @ 0x54 hdma->State = HAL_DMA_STATE_ERROR; 8007342: 687b ldr r3, [r7, #4] 8007344: 2203 movs r2, #3 8007346: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 800734a: 2301 movs r3, #1 800734c: e0b7 b.n 80074be } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800734e: 687b ldr r3, [r7, #4] 8007350: 681b ldr r3, [r3, #0] 8007352: 4a5f ldr r2, [pc, #380] @ (80074d0 ) 8007354: 4293 cmp r3, r2 8007356: d072 beq.n 800743e 8007358: 687b ldr r3, [r7, #4] 800735a: 681b ldr r3, [r3, #0] 800735c: 4a5d ldr r2, [pc, #372] @ (80074d4 ) 800735e: 4293 cmp r3, r2 8007360: d06d beq.n 800743e 8007362: 687b ldr r3, [r7, #4] 8007364: 681b ldr r3, [r3, #0] 8007366: 4a5c ldr r2, [pc, #368] @ (80074d8 ) 8007368: 4293 cmp r3, r2 800736a: d068 beq.n 800743e 800736c: 687b ldr r3, [r7, #4] 800736e: 681b ldr r3, [r3, #0] 8007370: 4a5a ldr r2, [pc, #360] @ (80074dc ) 8007372: 4293 cmp r3, r2 8007374: d063 beq.n 800743e 8007376: 687b ldr r3, [r7, #4] 8007378: 681b ldr r3, [r3, #0] 800737a: 4a59 ldr r2, [pc, #356] @ (80074e0 ) 800737c: 4293 cmp r3, r2 800737e: d05e beq.n 800743e 8007380: 687b ldr r3, [r7, #4] 8007382: 681b ldr r3, [r3, #0] 8007384: 4a57 ldr r2, [pc, #348] @ (80074e4 ) 8007386: 4293 cmp r3, r2 8007388: d059 beq.n 800743e 800738a: 687b ldr r3, [r7, #4] 800738c: 681b ldr r3, [r3, #0] 800738e: 4a56 ldr r2, [pc, #344] @ (80074e8 ) 8007390: 4293 cmp r3, r2 8007392: d054 beq.n 800743e 8007394: 687b ldr r3, [r7, #4] 8007396: 681b ldr r3, [r3, #0] 8007398: 4a54 ldr r2, [pc, #336] @ (80074ec ) 800739a: 4293 cmp r3, r2 800739c: d04f beq.n 800743e 800739e: 687b ldr r3, [r7, #4] 80073a0: 681b ldr r3, [r3, #0] 80073a2: 4a53 ldr r2, [pc, #332] @ (80074f0 ) 80073a4: 4293 cmp r3, r2 80073a6: d04a beq.n 800743e 80073a8: 687b ldr r3, [r7, #4] 80073aa: 681b ldr r3, [r3, #0] 80073ac: 4a51 ldr r2, [pc, #324] @ (80074f4 ) 80073ae: 4293 cmp r3, r2 80073b0: d045 beq.n 800743e 80073b2: 687b ldr r3, [r7, #4] 80073b4: 681b ldr r3, [r3, #0] 80073b6: 4a50 ldr r2, [pc, #320] @ (80074f8 ) 80073b8: 4293 cmp r3, r2 80073ba: d040 beq.n 800743e 80073bc: 687b ldr r3, [r7, #4] 80073be: 681b ldr r3, [r3, #0] 80073c0: 4a4e ldr r2, [pc, #312] @ (80074fc ) 80073c2: 4293 cmp r3, r2 80073c4: d03b beq.n 800743e 80073c6: 687b ldr r3, [r7, #4] 80073c8: 681b ldr r3, [r3, #0] 80073ca: 4a4d ldr r2, [pc, #308] @ (8007500 ) 80073cc: 4293 cmp r3, r2 80073ce: d036 beq.n 800743e 80073d0: 687b ldr r3, [r7, #4] 80073d2: 681b ldr r3, [r3, #0] 80073d4: 4a4b ldr r2, [pc, #300] @ (8007504 ) 80073d6: 4293 cmp r3, r2 80073d8: d031 beq.n 800743e 80073da: 687b ldr r3, [r7, #4] 80073dc: 681b ldr r3, [r3, #0] 80073de: 4a4a ldr r2, [pc, #296] @ (8007508 ) 80073e0: 4293 cmp r3, r2 80073e2: d02c beq.n 800743e 80073e4: 687b ldr r3, [r7, #4] 80073e6: 681b ldr r3, [r3, #0] 80073e8: 4a48 ldr r2, [pc, #288] @ (800750c ) 80073ea: 4293 cmp r3, r2 80073ec: d027 beq.n 800743e 80073ee: 687b ldr r3, [r7, #4] 80073f0: 681b ldr r3, [r3, #0] 80073f2: 4a47 ldr r2, [pc, #284] @ (8007510 ) 80073f4: 4293 cmp r3, r2 80073f6: d022 beq.n 800743e 80073f8: 687b ldr r3, [r7, #4] 80073fa: 681b ldr r3, [r3, #0] 80073fc: 4a45 ldr r2, [pc, #276] @ (8007514 ) 80073fe: 4293 cmp r3, r2 8007400: d01d beq.n 800743e 8007402: 687b ldr r3, [r7, #4] 8007404: 681b ldr r3, [r3, #0] 8007406: 4a44 ldr r2, [pc, #272] @ (8007518 ) 8007408: 4293 cmp r3, r2 800740a: d018 beq.n 800743e 800740c: 687b ldr r3, [r7, #4] 800740e: 681b ldr r3, [r3, #0] 8007410: 4a42 ldr r2, [pc, #264] @ (800751c ) 8007412: 4293 cmp r3, r2 8007414: d013 beq.n 800743e 8007416: 687b ldr r3, [r7, #4] 8007418: 681b ldr r3, [r3, #0] 800741a: 4a41 ldr r2, [pc, #260] @ (8007520 ) 800741c: 4293 cmp r3, r2 800741e: d00e beq.n 800743e 8007420: 687b ldr r3, [r7, #4] 8007422: 681b ldr r3, [r3, #0] 8007424: 4a3f ldr r2, [pc, #252] @ (8007524 ) 8007426: 4293 cmp r3, r2 8007428: d009 beq.n 800743e 800742a: 687b ldr r3, [r7, #4] 800742c: 681b ldr r3, [r3, #0] 800742e: 4a3e ldr r2, [pc, #248] @ (8007528 ) 8007430: 4293 cmp r3, r2 8007432: d004 beq.n 800743e 8007434: 687b ldr r3, [r7, #4] 8007436: 681b ldr r3, [r3, #0] 8007438: 4a3c ldr r2, [pc, #240] @ (800752c ) 800743a: 4293 cmp r3, r2 800743c: d101 bne.n 8007442 800743e: 2301 movs r3, #1 8007440: e000 b.n 8007444 8007442: 2300 movs r3, #0 8007444: 2b00 cmp r3, #0 8007446: d032 beq.n 80074ae { /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 8007448: 6878 ldr r0, [r7, #4] 800744a: f002 fa43 bl 80098d4 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 800744e: 687b ldr r3, [r7, #4] 8007450: 689b ldr r3, [r3, #8] 8007452: 2b80 cmp r3, #128 @ 0x80 8007454: d102 bne.n 800745c { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 8007456: 687b ldr r3, [r7, #4] 8007458: 2200 movs r2, #0 800745a: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 800745c: 687b ldr r3, [r7, #4] 800745e: 685a ldr r2, [r3, #4] 8007460: 687b ldr r3, [r7, #4] 8007462: 6e1b ldr r3, [r3, #96] @ 0x60 8007464: b2d2 uxtb r2, r2 8007466: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8007468: 687b ldr r3, [r7, #4] 800746a: 6e5b ldr r3, [r3, #100] @ 0x64 800746c: 687a ldr r2, [r7, #4] 800746e: 6e92 ldr r2, [r2, #104] @ 0x68 8007470: 605a str r2, [r3, #4] /* Initialize parameters for DMAMUX request generator : if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 */ if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) 8007472: 687b ldr r3, [r7, #4] 8007474: 685b ldr r3, [r3, #4] 8007476: 2b00 cmp r3, #0 8007478: d010 beq.n 800749c 800747a: 687b ldr r3, [r7, #4] 800747c: 685b ldr r3, [r3, #4] 800747e: 2b08 cmp r3, #8 8007480: d80c bhi.n 800749c { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 8007482: 6878 ldr r0, [r7, #4] 8007484: f002 fac0 bl 8009a08 /* Reset the DMAMUX request generator register */ hdma->DMAmuxRequestGen->RGCR = 0U; 8007488: 687b ldr r3, [r7, #4] 800748a: 6edb ldr r3, [r3, #108] @ 0x6c 800748c: 2200 movs r2, #0 800748e: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8007490: 687b ldr r3, [r7, #4] 8007492: 6f1b ldr r3, [r3, #112] @ 0x70 8007494: 687a ldr r2, [r7, #4] 8007496: 6f52 ldr r2, [r2, #116] @ 0x74 8007498: 605a str r2, [r3, #4] 800749a: e008 b.n 80074ae } else { hdma->DMAmuxRequestGen = 0U; 800749c: 687b ldr r3, [r7, #4] 800749e: 2200 movs r2, #0 80074a0: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = 0U; 80074a2: 687b ldr r3, [r7, #4] 80074a4: 2200 movs r2, #0 80074a6: 671a str r2, [r3, #112] @ 0x70 hdma->DMAmuxRequestGenStatusMask = 0U; 80074a8: 687b ldr r3, [r7, #4] 80074aa: 2200 movs r2, #0 80074ac: 675a str r2, [r3, #116] @ 0x74 } } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 80074ae: 687b ldr r3, [r7, #4] 80074b0: 2200 movs r2, #0 80074b2: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80074b4: 687b ldr r3, [r7, #4] 80074b6: 2201 movs r2, #1 80074b8: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 80074bc: 2300 movs r3, #0 } 80074be: 4618 mov r0, r3 80074c0: 3718 adds r7, #24 80074c2: 46bd mov sp, r7 80074c4: bd80 pop {r7, pc} 80074c6: bf00 nop 80074c8: a7fdabf8 .word 0xa7fdabf8 80074cc: cccccccd .word 0xcccccccd 80074d0: 40020010 .word 0x40020010 80074d4: 40020028 .word 0x40020028 80074d8: 40020040 .word 0x40020040 80074dc: 40020058 .word 0x40020058 80074e0: 40020070 .word 0x40020070 80074e4: 40020088 .word 0x40020088 80074e8: 400200a0 .word 0x400200a0 80074ec: 400200b8 .word 0x400200b8 80074f0: 40020410 .word 0x40020410 80074f4: 40020428 .word 0x40020428 80074f8: 40020440 .word 0x40020440 80074fc: 40020458 .word 0x40020458 8007500: 40020470 .word 0x40020470 8007504: 40020488 .word 0x40020488 8007508: 400204a0 .word 0x400204a0 800750c: 400204b8 .word 0x400204b8 8007510: 58025408 .word 0x58025408 8007514: 5802541c .word 0x5802541c 8007518: 58025430 .word 0x58025430 800751c: 58025444 .word 0x58025444 8007520: 58025458 .word 0x58025458 8007524: 5802546c .word 0x5802546c 8007528: 58025480 .word 0x58025480 800752c: 58025494 .word 0x58025494 08007530 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8007530: b580 push {r7, lr} 8007532: b086 sub sp, #24 8007534: af00 add r7, sp, #0 8007536: 60f8 str r0, [r7, #12] 8007538: 60b9 str r1, [r7, #8] 800753a: 607a str r2, [r7, #4] 800753c: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800753e: 2300 movs r3, #0 8007540: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Check the DMA peripheral handle */ if(hdma == NULL) 8007542: 68fb ldr r3, [r7, #12] 8007544: 2b00 cmp r3, #0 8007546: d101 bne.n 800754c { return HAL_ERROR; 8007548: 2301 movs r3, #1 800754a: e226 b.n 800799a } /* Process locked */ __HAL_LOCK(hdma); 800754c: 68fb ldr r3, [r7, #12] 800754e: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8007552: 2b01 cmp r3, #1 8007554: d101 bne.n 800755a 8007556: 2302 movs r3, #2 8007558: e21f b.n 800799a 800755a: 68fb ldr r3, [r7, #12] 800755c: 2201 movs r2, #1 800755e: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 8007562: 68fb ldr r3, [r7, #12] 8007564: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8007568: b2db uxtb r3, r3 800756a: 2b01 cmp r3, #1 800756c: f040 820a bne.w 8007984 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8007570: 68fb ldr r3, [r7, #12] 8007572: 2202 movs r2, #2 8007574: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8007578: 68fb ldr r3, [r7, #12] 800757a: 2200 movs r2, #0 800757c: 655a str r2, [r3, #84] @ 0x54 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 800757e: 68fb ldr r3, [r7, #12] 8007580: 681b ldr r3, [r3, #0] 8007582: 4a68 ldr r2, [pc, #416] @ (8007724 ) 8007584: 4293 cmp r3, r2 8007586: d04a beq.n 800761e 8007588: 68fb ldr r3, [r7, #12] 800758a: 681b ldr r3, [r3, #0] 800758c: 4a66 ldr r2, [pc, #408] @ (8007728 ) 800758e: 4293 cmp r3, r2 8007590: d045 beq.n 800761e 8007592: 68fb ldr r3, [r7, #12] 8007594: 681b ldr r3, [r3, #0] 8007596: 4a65 ldr r2, [pc, #404] @ (800772c ) 8007598: 4293 cmp r3, r2 800759a: d040 beq.n 800761e 800759c: 68fb ldr r3, [r7, #12] 800759e: 681b ldr r3, [r3, #0] 80075a0: 4a63 ldr r2, [pc, #396] @ (8007730 ) 80075a2: 4293 cmp r3, r2 80075a4: d03b beq.n 800761e 80075a6: 68fb ldr r3, [r7, #12] 80075a8: 681b ldr r3, [r3, #0] 80075aa: 4a62 ldr r2, [pc, #392] @ (8007734 ) 80075ac: 4293 cmp r3, r2 80075ae: d036 beq.n 800761e 80075b0: 68fb ldr r3, [r7, #12] 80075b2: 681b ldr r3, [r3, #0] 80075b4: 4a60 ldr r2, [pc, #384] @ (8007738 ) 80075b6: 4293 cmp r3, r2 80075b8: d031 beq.n 800761e 80075ba: 68fb ldr r3, [r7, #12] 80075bc: 681b ldr r3, [r3, #0] 80075be: 4a5f ldr r2, [pc, #380] @ (800773c ) 80075c0: 4293 cmp r3, r2 80075c2: d02c beq.n 800761e 80075c4: 68fb ldr r3, [r7, #12] 80075c6: 681b ldr r3, [r3, #0] 80075c8: 4a5d ldr r2, [pc, #372] @ (8007740 ) 80075ca: 4293 cmp r3, r2 80075cc: d027 beq.n 800761e 80075ce: 68fb ldr r3, [r7, #12] 80075d0: 681b ldr r3, [r3, #0] 80075d2: 4a5c ldr r2, [pc, #368] @ (8007744 ) 80075d4: 4293 cmp r3, r2 80075d6: d022 beq.n 800761e 80075d8: 68fb ldr r3, [r7, #12] 80075da: 681b ldr r3, [r3, #0] 80075dc: 4a5a ldr r2, [pc, #360] @ (8007748 ) 80075de: 4293 cmp r3, r2 80075e0: d01d beq.n 800761e 80075e2: 68fb ldr r3, [r7, #12] 80075e4: 681b ldr r3, [r3, #0] 80075e6: 4a59 ldr r2, [pc, #356] @ (800774c ) 80075e8: 4293 cmp r3, r2 80075ea: d018 beq.n 800761e 80075ec: 68fb ldr r3, [r7, #12] 80075ee: 681b ldr r3, [r3, #0] 80075f0: 4a57 ldr r2, [pc, #348] @ (8007750 ) 80075f2: 4293 cmp r3, r2 80075f4: d013 beq.n 800761e 80075f6: 68fb ldr r3, [r7, #12] 80075f8: 681b ldr r3, [r3, #0] 80075fa: 4a56 ldr r2, [pc, #344] @ (8007754 ) 80075fc: 4293 cmp r3, r2 80075fe: d00e beq.n 800761e 8007600: 68fb ldr r3, [r7, #12] 8007602: 681b ldr r3, [r3, #0] 8007604: 4a54 ldr r2, [pc, #336] @ (8007758 ) 8007606: 4293 cmp r3, r2 8007608: d009 beq.n 800761e 800760a: 68fb ldr r3, [r7, #12] 800760c: 681b ldr r3, [r3, #0] 800760e: 4a53 ldr r2, [pc, #332] @ (800775c ) 8007610: 4293 cmp r3, r2 8007612: d004 beq.n 800761e 8007614: 68fb ldr r3, [r7, #12] 8007616: 681b ldr r3, [r3, #0] 8007618: 4a51 ldr r2, [pc, #324] @ (8007760 ) 800761a: 4293 cmp r3, r2 800761c: d108 bne.n 8007630 800761e: 68fb ldr r3, [r7, #12] 8007620: 681b ldr r3, [r3, #0] 8007622: 681a ldr r2, [r3, #0] 8007624: 68fb ldr r3, [r7, #12] 8007626: 681b ldr r3, [r3, #0] 8007628: f022 0201 bic.w r2, r2, #1 800762c: 601a str r2, [r3, #0] 800762e: e007 b.n 8007640 8007630: 68fb ldr r3, [r7, #12] 8007632: 681b ldr r3, [r3, #0] 8007634: 681a ldr r2, [r3, #0] 8007636: 68fb ldr r3, [r7, #12] 8007638: 681b ldr r3, [r3, #0] 800763a: f022 0201 bic.w r2, r2, #1 800763e: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8007640: 683b ldr r3, [r7, #0] 8007642: 687a ldr r2, [r7, #4] 8007644: 68b9 ldr r1, [r7, #8] 8007646: 68f8 ldr r0, [r7, #12] 8007648: f001 fe6a bl 8009320 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800764c: 68fb ldr r3, [r7, #12] 800764e: 681b ldr r3, [r3, #0] 8007650: 4a34 ldr r2, [pc, #208] @ (8007724 ) 8007652: 4293 cmp r3, r2 8007654: d04a beq.n 80076ec 8007656: 68fb ldr r3, [r7, #12] 8007658: 681b ldr r3, [r3, #0] 800765a: 4a33 ldr r2, [pc, #204] @ (8007728 ) 800765c: 4293 cmp r3, r2 800765e: d045 beq.n 80076ec 8007660: 68fb ldr r3, [r7, #12] 8007662: 681b ldr r3, [r3, #0] 8007664: 4a31 ldr r2, [pc, #196] @ (800772c ) 8007666: 4293 cmp r3, r2 8007668: d040 beq.n 80076ec 800766a: 68fb ldr r3, [r7, #12] 800766c: 681b ldr r3, [r3, #0] 800766e: 4a30 ldr r2, [pc, #192] @ (8007730 ) 8007670: 4293 cmp r3, r2 8007672: d03b beq.n 80076ec 8007674: 68fb ldr r3, [r7, #12] 8007676: 681b ldr r3, [r3, #0] 8007678: 4a2e ldr r2, [pc, #184] @ (8007734 ) 800767a: 4293 cmp r3, r2 800767c: d036 beq.n 80076ec 800767e: 68fb ldr r3, [r7, #12] 8007680: 681b ldr r3, [r3, #0] 8007682: 4a2d ldr r2, [pc, #180] @ (8007738 ) 8007684: 4293 cmp r3, r2 8007686: d031 beq.n 80076ec 8007688: 68fb ldr r3, [r7, #12] 800768a: 681b ldr r3, [r3, #0] 800768c: 4a2b ldr r2, [pc, #172] @ (800773c ) 800768e: 4293 cmp r3, r2 8007690: d02c beq.n 80076ec 8007692: 68fb ldr r3, [r7, #12] 8007694: 681b ldr r3, [r3, #0] 8007696: 4a2a ldr r2, [pc, #168] @ (8007740 ) 8007698: 4293 cmp r3, r2 800769a: d027 beq.n 80076ec 800769c: 68fb ldr r3, [r7, #12] 800769e: 681b ldr r3, [r3, #0] 80076a0: 4a28 ldr r2, [pc, #160] @ (8007744 ) 80076a2: 4293 cmp r3, r2 80076a4: d022 beq.n 80076ec 80076a6: 68fb ldr r3, [r7, #12] 80076a8: 681b ldr r3, [r3, #0] 80076aa: 4a27 ldr r2, [pc, #156] @ (8007748 ) 80076ac: 4293 cmp r3, r2 80076ae: d01d beq.n 80076ec 80076b0: 68fb ldr r3, [r7, #12] 80076b2: 681b ldr r3, [r3, #0] 80076b4: 4a25 ldr r2, [pc, #148] @ (800774c ) 80076b6: 4293 cmp r3, r2 80076b8: d018 beq.n 80076ec 80076ba: 68fb ldr r3, [r7, #12] 80076bc: 681b ldr r3, [r3, #0] 80076be: 4a24 ldr r2, [pc, #144] @ (8007750 ) 80076c0: 4293 cmp r3, r2 80076c2: d013 beq.n 80076ec 80076c4: 68fb ldr r3, [r7, #12] 80076c6: 681b ldr r3, [r3, #0] 80076c8: 4a22 ldr r2, [pc, #136] @ (8007754 ) 80076ca: 4293 cmp r3, r2 80076cc: d00e beq.n 80076ec 80076ce: 68fb ldr r3, [r7, #12] 80076d0: 681b ldr r3, [r3, #0] 80076d2: 4a21 ldr r2, [pc, #132] @ (8007758 ) 80076d4: 4293 cmp r3, r2 80076d6: d009 beq.n 80076ec 80076d8: 68fb ldr r3, [r7, #12] 80076da: 681b ldr r3, [r3, #0] 80076dc: 4a1f ldr r2, [pc, #124] @ (800775c ) 80076de: 4293 cmp r3, r2 80076e0: d004 beq.n 80076ec 80076e2: 68fb ldr r3, [r7, #12] 80076e4: 681b ldr r3, [r3, #0] 80076e6: 4a1e ldr r2, [pc, #120] @ (8007760 ) 80076e8: 4293 cmp r3, r2 80076ea: d101 bne.n 80076f0 80076ec: 2301 movs r3, #1 80076ee: e000 b.n 80076f2 80076f0: 2300 movs r3, #0 80076f2: 2b00 cmp r3, #0 80076f4: d036 beq.n 8007764 { /* Enable Common interrupts*/ MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 80076f6: 68fb ldr r3, [r7, #12] 80076f8: 681b ldr r3, [r3, #0] 80076fa: 681b ldr r3, [r3, #0] 80076fc: f023 021e bic.w r2, r3, #30 8007700: 68fb ldr r3, [r7, #12] 8007702: 681b ldr r3, [r3, #0] 8007704: f042 0216 orr.w r2, r2, #22 8007708: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 800770a: 68fb ldr r3, [r7, #12] 800770c: 6c1b ldr r3, [r3, #64] @ 0x40 800770e: 2b00 cmp r3, #0 8007710: d03e beq.n 8007790 { /* Enable Half Transfer IT if corresponding Callback is set */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; 8007712: 68fb ldr r3, [r7, #12] 8007714: 681b ldr r3, [r3, #0] 8007716: 681a ldr r2, [r3, #0] 8007718: 68fb ldr r3, [r7, #12] 800771a: 681b ldr r3, [r3, #0] 800771c: f042 0208 orr.w r2, r2, #8 8007720: 601a str r2, [r3, #0] 8007722: e035 b.n 8007790 8007724: 40020010 .word 0x40020010 8007728: 40020028 .word 0x40020028 800772c: 40020040 .word 0x40020040 8007730: 40020058 .word 0x40020058 8007734: 40020070 .word 0x40020070 8007738: 40020088 .word 0x40020088 800773c: 400200a0 .word 0x400200a0 8007740: 400200b8 .word 0x400200b8 8007744: 40020410 .word 0x40020410 8007748: 40020428 .word 0x40020428 800774c: 40020440 .word 0x40020440 8007750: 40020458 .word 0x40020458 8007754: 40020470 .word 0x40020470 8007758: 40020488 .word 0x40020488 800775c: 400204a0 .word 0x400204a0 8007760: 400204b8 .word 0x400204b8 } } else /* BDMA channel */ { /* Enable Common interrupts */ MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE)); 8007764: 68fb ldr r3, [r7, #12] 8007766: 681b ldr r3, [r3, #0] 8007768: 681b ldr r3, [r3, #0] 800776a: f023 020e bic.w r2, r3, #14 800776e: 68fb ldr r3, [r7, #12] 8007770: 681b ldr r3, [r3, #0] 8007772: f042 020a orr.w r2, r2, #10 8007776: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8007778: 68fb ldr r3, [r7, #12] 800777a: 6c1b ldr r3, [r3, #64] @ 0x40 800777c: 2b00 cmp r3, #0 800777e: d007 beq.n 8007790 { /*Enable Half Transfer IT if corresponding Callback is set */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; 8007780: 68fb ldr r3, [r7, #12] 8007782: 681b ldr r3, [r3, #0] 8007784: 681a ldr r2, [r3, #0] 8007786: 68fb ldr r3, [r7, #12] 8007788: 681b ldr r3, [r3, #0] 800778a: f042 0204 orr.w r2, r2, #4 800778e: 601a str r2, [r3, #0] } } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8007790: 68fb ldr r3, [r7, #12] 8007792: 681b ldr r3, [r3, #0] 8007794: 4a83 ldr r2, [pc, #524] @ (80079a4 ) 8007796: 4293 cmp r3, r2 8007798: d072 beq.n 8007880 800779a: 68fb ldr r3, [r7, #12] 800779c: 681b ldr r3, [r3, #0] 800779e: 4a82 ldr r2, [pc, #520] @ (80079a8 ) 80077a0: 4293 cmp r3, r2 80077a2: d06d beq.n 8007880 80077a4: 68fb ldr r3, [r7, #12] 80077a6: 681b ldr r3, [r3, #0] 80077a8: 4a80 ldr r2, [pc, #512] @ (80079ac ) 80077aa: 4293 cmp r3, r2 80077ac: d068 beq.n 8007880 80077ae: 68fb ldr r3, [r7, #12] 80077b0: 681b ldr r3, [r3, #0] 80077b2: 4a7f ldr r2, [pc, #508] @ (80079b0 ) 80077b4: 4293 cmp r3, r2 80077b6: d063 beq.n 8007880 80077b8: 68fb ldr r3, [r7, #12] 80077ba: 681b ldr r3, [r3, #0] 80077bc: 4a7d ldr r2, [pc, #500] @ (80079b4 ) 80077be: 4293 cmp r3, r2 80077c0: d05e beq.n 8007880 80077c2: 68fb ldr r3, [r7, #12] 80077c4: 681b ldr r3, [r3, #0] 80077c6: 4a7c ldr r2, [pc, #496] @ (80079b8 ) 80077c8: 4293 cmp r3, r2 80077ca: d059 beq.n 8007880 80077cc: 68fb ldr r3, [r7, #12] 80077ce: 681b ldr r3, [r3, #0] 80077d0: 4a7a ldr r2, [pc, #488] @ (80079bc ) 80077d2: 4293 cmp r3, r2 80077d4: d054 beq.n 8007880 80077d6: 68fb ldr r3, [r7, #12] 80077d8: 681b ldr r3, [r3, #0] 80077da: 4a79 ldr r2, [pc, #484] @ (80079c0 ) 80077dc: 4293 cmp r3, r2 80077de: d04f beq.n 8007880 80077e0: 68fb ldr r3, [r7, #12] 80077e2: 681b ldr r3, [r3, #0] 80077e4: 4a77 ldr r2, [pc, #476] @ (80079c4 ) 80077e6: 4293 cmp r3, r2 80077e8: d04a beq.n 8007880 80077ea: 68fb ldr r3, [r7, #12] 80077ec: 681b ldr r3, [r3, #0] 80077ee: 4a76 ldr r2, [pc, #472] @ (80079c8 ) 80077f0: 4293 cmp r3, r2 80077f2: d045 beq.n 8007880 80077f4: 68fb ldr r3, [r7, #12] 80077f6: 681b ldr r3, [r3, #0] 80077f8: 4a74 ldr r2, [pc, #464] @ (80079cc ) 80077fa: 4293 cmp r3, r2 80077fc: d040 beq.n 8007880 80077fe: 68fb ldr r3, [r7, #12] 8007800: 681b ldr r3, [r3, #0] 8007802: 4a73 ldr r2, [pc, #460] @ (80079d0 ) 8007804: 4293 cmp r3, r2 8007806: d03b beq.n 8007880 8007808: 68fb ldr r3, [r7, #12] 800780a: 681b ldr r3, [r3, #0] 800780c: 4a71 ldr r2, [pc, #452] @ (80079d4 ) 800780e: 4293 cmp r3, r2 8007810: d036 beq.n 8007880 8007812: 68fb ldr r3, [r7, #12] 8007814: 681b ldr r3, [r3, #0] 8007816: 4a70 ldr r2, [pc, #448] @ (80079d8 ) 8007818: 4293 cmp r3, r2 800781a: d031 beq.n 8007880 800781c: 68fb ldr r3, [r7, #12] 800781e: 681b ldr r3, [r3, #0] 8007820: 4a6e ldr r2, [pc, #440] @ (80079dc ) 8007822: 4293 cmp r3, r2 8007824: d02c beq.n 8007880 8007826: 68fb ldr r3, [r7, #12] 8007828: 681b ldr r3, [r3, #0] 800782a: 4a6d ldr r2, [pc, #436] @ (80079e0 ) 800782c: 4293 cmp r3, r2 800782e: d027 beq.n 8007880 8007830: 68fb ldr r3, [r7, #12] 8007832: 681b ldr r3, [r3, #0] 8007834: 4a6b ldr r2, [pc, #428] @ (80079e4 ) 8007836: 4293 cmp r3, r2 8007838: d022 beq.n 8007880 800783a: 68fb ldr r3, [r7, #12] 800783c: 681b ldr r3, [r3, #0] 800783e: 4a6a ldr r2, [pc, #424] @ (80079e8 ) 8007840: 4293 cmp r3, r2 8007842: d01d beq.n 8007880 8007844: 68fb ldr r3, [r7, #12] 8007846: 681b ldr r3, [r3, #0] 8007848: 4a68 ldr r2, [pc, #416] @ (80079ec ) 800784a: 4293 cmp r3, r2 800784c: d018 beq.n 8007880 800784e: 68fb ldr r3, [r7, #12] 8007850: 681b ldr r3, [r3, #0] 8007852: 4a67 ldr r2, [pc, #412] @ (80079f0 ) 8007854: 4293 cmp r3, r2 8007856: d013 beq.n 8007880 8007858: 68fb ldr r3, [r7, #12] 800785a: 681b ldr r3, [r3, #0] 800785c: 4a65 ldr r2, [pc, #404] @ (80079f4 ) 800785e: 4293 cmp r3, r2 8007860: d00e beq.n 8007880 8007862: 68fb ldr r3, [r7, #12] 8007864: 681b ldr r3, [r3, #0] 8007866: 4a64 ldr r2, [pc, #400] @ (80079f8 ) 8007868: 4293 cmp r3, r2 800786a: d009 beq.n 8007880 800786c: 68fb ldr r3, [r7, #12] 800786e: 681b ldr r3, [r3, #0] 8007870: 4a62 ldr r2, [pc, #392] @ (80079fc ) 8007872: 4293 cmp r3, r2 8007874: d004 beq.n 8007880 8007876: 68fb ldr r3, [r7, #12] 8007878: 681b ldr r3, [r3, #0] 800787a: 4a61 ldr r2, [pc, #388] @ (8007a00 ) 800787c: 4293 cmp r3, r2 800787e: d101 bne.n 8007884 8007880: 2301 movs r3, #1 8007882: e000 b.n 8007886 8007884: 2300 movs r3, #0 8007886: 2b00 cmp r3, #0 8007888: d01a beq.n 80078c0 { /* Check if DMAMUX Synchronization is enabled */ if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) 800788a: 68fb ldr r3, [r7, #12] 800788c: 6e1b ldr r3, [r3, #96] @ 0x60 800788e: 681b ldr r3, [r3, #0] 8007890: f403 3380 and.w r3, r3, #65536 @ 0x10000 8007894: 2b00 cmp r3, #0 8007896: d007 beq.n 80078a8 { /* Enable DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; 8007898: 68fb ldr r3, [r7, #12] 800789a: 6e1b ldr r3, [r3, #96] @ 0x60 800789c: 681a ldr r2, [r3, #0] 800789e: 68fb ldr r3, [r7, #12] 80078a0: 6e1b ldr r3, [r3, #96] @ 0x60 80078a2: f442 7280 orr.w r2, r2, #256 @ 0x100 80078a6: 601a str r2, [r3, #0] } if(hdma->DMAmuxRequestGen != 0U) 80078a8: 68fb ldr r3, [r7, #12] 80078aa: 6edb ldr r3, [r3, #108] @ 0x6c 80078ac: 2b00 cmp r3, #0 80078ae: d007 beq.n 80078c0 { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 80078b0: 68fb ldr r3, [r7, #12] 80078b2: 6edb ldr r3, [r3, #108] @ 0x6c 80078b4: 681a ldr r2, [r3, #0] 80078b6: 68fb ldr r3, [r7, #12] 80078b8: 6edb ldr r3, [r3, #108] @ 0x6c 80078ba: f442 7280 orr.w r2, r2, #256 @ 0x100 80078be: 601a str r2, [r3, #0] } } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 80078c0: 68fb ldr r3, [r7, #12] 80078c2: 681b ldr r3, [r3, #0] 80078c4: 4a37 ldr r2, [pc, #220] @ (80079a4 ) 80078c6: 4293 cmp r3, r2 80078c8: d04a beq.n 8007960 80078ca: 68fb ldr r3, [r7, #12] 80078cc: 681b ldr r3, [r3, #0] 80078ce: 4a36 ldr r2, [pc, #216] @ (80079a8 ) 80078d0: 4293 cmp r3, r2 80078d2: d045 beq.n 8007960 80078d4: 68fb ldr r3, [r7, #12] 80078d6: 681b ldr r3, [r3, #0] 80078d8: 4a34 ldr r2, [pc, #208] @ (80079ac ) 80078da: 4293 cmp r3, r2 80078dc: d040 beq.n 8007960 80078de: 68fb ldr r3, [r7, #12] 80078e0: 681b ldr r3, [r3, #0] 80078e2: 4a33 ldr r2, [pc, #204] @ (80079b0 ) 80078e4: 4293 cmp r3, r2 80078e6: d03b beq.n 8007960 80078e8: 68fb ldr r3, [r7, #12] 80078ea: 681b ldr r3, [r3, #0] 80078ec: 4a31 ldr r2, [pc, #196] @ (80079b4 ) 80078ee: 4293 cmp r3, r2 80078f0: d036 beq.n 8007960 80078f2: 68fb ldr r3, [r7, #12] 80078f4: 681b ldr r3, [r3, #0] 80078f6: 4a30 ldr r2, [pc, #192] @ (80079b8 ) 80078f8: 4293 cmp r3, r2 80078fa: d031 beq.n 8007960 80078fc: 68fb ldr r3, [r7, #12] 80078fe: 681b ldr r3, [r3, #0] 8007900: 4a2e ldr r2, [pc, #184] @ (80079bc ) 8007902: 4293 cmp r3, r2 8007904: d02c beq.n 8007960 8007906: 68fb ldr r3, [r7, #12] 8007908: 681b ldr r3, [r3, #0] 800790a: 4a2d ldr r2, [pc, #180] @ (80079c0 ) 800790c: 4293 cmp r3, r2 800790e: d027 beq.n 8007960 8007910: 68fb ldr r3, [r7, #12] 8007912: 681b ldr r3, [r3, #0] 8007914: 4a2b ldr r2, [pc, #172] @ (80079c4 ) 8007916: 4293 cmp r3, r2 8007918: d022 beq.n 8007960 800791a: 68fb ldr r3, [r7, #12] 800791c: 681b ldr r3, [r3, #0] 800791e: 4a2a ldr r2, [pc, #168] @ (80079c8 ) 8007920: 4293 cmp r3, r2 8007922: d01d beq.n 8007960 8007924: 68fb ldr r3, [r7, #12] 8007926: 681b ldr r3, [r3, #0] 8007928: 4a28 ldr r2, [pc, #160] @ (80079cc ) 800792a: 4293 cmp r3, r2 800792c: d018 beq.n 8007960 800792e: 68fb ldr r3, [r7, #12] 8007930: 681b ldr r3, [r3, #0] 8007932: 4a27 ldr r2, [pc, #156] @ (80079d0 ) 8007934: 4293 cmp r3, r2 8007936: d013 beq.n 8007960 8007938: 68fb ldr r3, [r7, #12] 800793a: 681b ldr r3, [r3, #0] 800793c: 4a25 ldr r2, [pc, #148] @ (80079d4 ) 800793e: 4293 cmp r3, r2 8007940: d00e beq.n 8007960 8007942: 68fb ldr r3, [r7, #12] 8007944: 681b ldr r3, [r3, #0] 8007946: 4a24 ldr r2, [pc, #144] @ (80079d8 ) 8007948: 4293 cmp r3, r2 800794a: d009 beq.n 8007960 800794c: 68fb ldr r3, [r7, #12] 800794e: 681b ldr r3, [r3, #0] 8007950: 4a22 ldr r2, [pc, #136] @ (80079dc ) 8007952: 4293 cmp r3, r2 8007954: d004 beq.n 8007960 8007956: 68fb ldr r3, [r7, #12] 8007958: 681b ldr r3, [r3, #0] 800795a: 4a21 ldr r2, [pc, #132] @ (80079e0 ) 800795c: 4293 cmp r3, r2 800795e: d108 bne.n 8007972 8007960: 68fb ldr r3, [r7, #12] 8007962: 681b ldr r3, [r3, #0] 8007964: 681a ldr r2, [r3, #0] 8007966: 68fb ldr r3, [r7, #12] 8007968: 681b ldr r3, [r3, #0] 800796a: f042 0201 orr.w r2, r2, #1 800796e: 601a str r2, [r3, #0] 8007970: e012 b.n 8007998 8007972: 68fb ldr r3, [r7, #12] 8007974: 681b ldr r3, [r3, #0] 8007976: 681a ldr r2, [r3, #0] 8007978: 68fb ldr r3, [r7, #12] 800797a: 681b ldr r3, [r3, #0] 800797c: f042 0201 orr.w r2, r2, #1 8007980: 601a str r2, [r3, #0] 8007982: e009 b.n 8007998 } else { /* Set the error code to busy */ hdma->ErrorCode = HAL_DMA_ERROR_BUSY; 8007984: 68fb ldr r3, [r7, #12] 8007986: f44f 6200 mov.w r2, #2048 @ 0x800 800798a: 655a str r2, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hdma); 800798c: 68fb ldr r3, [r7, #12] 800798e: 2200 movs r2, #0 8007990: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Return error status */ status = HAL_ERROR; 8007994: 2301 movs r3, #1 8007996: 75fb strb r3, [r7, #23] } return status; 8007998: 7dfb ldrb r3, [r7, #23] } 800799a: 4618 mov r0, r3 800799c: 3718 adds r7, #24 800799e: 46bd mov sp, r7 80079a0: bd80 pop {r7, pc} 80079a2: bf00 nop 80079a4: 40020010 .word 0x40020010 80079a8: 40020028 .word 0x40020028 80079ac: 40020040 .word 0x40020040 80079b0: 40020058 .word 0x40020058 80079b4: 40020070 .word 0x40020070 80079b8: 40020088 .word 0x40020088 80079bc: 400200a0 .word 0x400200a0 80079c0: 400200b8 .word 0x400200b8 80079c4: 40020410 .word 0x40020410 80079c8: 40020428 .word 0x40020428 80079cc: 40020440 .word 0x40020440 80079d0: 40020458 .word 0x40020458 80079d4: 40020470 .word 0x40020470 80079d8: 40020488 .word 0x40020488 80079dc: 400204a0 .word 0x400204a0 80079e0: 400204b8 .word 0x400204b8 80079e4: 58025408 .word 0x58025408 80079e8: 5802541c .word 0x5802541c 80079ec: 58025430 .word 0x58025430 80079f0: 58025444 .word 0x58025444 80079f4: 58025458 .word 0x58025458 80079f8: 5802546c .word 0x5802546c 80079fc: 58025480 .word 0x58025480 8007a00: 58025494 .word 0x58025494 08007a04 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8007a04: b580 push {r7, lr} 8007a06: b086 sub sp, #24 8007a08: af00 add r7, sp, #0 8007a0a: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; const __IO uint32_t *enableRegister; uint32_t tickstart = HAL_GetTick(); 8007a0c: f7fd f82a bl 8004a64 8007a10: 6138 str r0, [r7, #16] /* Check the DMA peripheral handle */ if(hdma == NULL) 8007a12: 687b ldr r3, [r7, #4] 8007a14: 2b00 cmp r3, #0 8007a16: d101 bne.n 8007a1c { return HAL_ERROR; 8007a18: 2301 movs r3, #1 8007a1a: e2dc b.n 8007fd6 } /* Check the DMA peripheral state */ if(hdma->State != HAL_DMA_STATE_BUSY) 8007a1c: 687b ldr r3, [r7, #4] 8007a1e: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8007a22: b2db uxtb r3, r3 8007a24: 2b02 cmp r3, #2 8007a26: d008 beq.n 8007a3a { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8007a28: 687b ldr r3, [r7, #4] 8007a2a: 2280 movs r2, #128 @ 0x80 8007a2c: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8007a2e: 687b ldr r3, [r7, #4] 8007a30: 2200 movs r2, #0 8007a32: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8007a36: 2301 movs r3, #1 8007a38: e2cd b.n 8007fd6 } else { /* Disable all the transfer interrupts */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8007a3a: 687b ldr r3, [r7, #4] 8007a3c: 681b ldr r3, [r3, #0] 8007a3e: 4a76 ldr r2, [pc, #472] @ (8007c18 ) 8007a40: 4293 cmp r3, r2 8007a42: d04a beq.n 8007ada 8007a44: 687b ldr r3, [r7, #4] 8007a46: 681b ldr r3, [r3, #0] 8007a48: 4a74 ldr r2, [pc, #464] @ (8007c1c ) 8007a4a: 4293 cmp r3, r2 8007a4c: d045 beq.n 8007ada 8007a4e: 687b ldr r3, [r7, #4] 8007a50: 681b ldr r3, [r3, #0] 8007a52: 4a73 ldr r2, [pc, #460] @ (8007c20 ) 8007a54: 4293 cmp r3, r2 8007a56: d040 beq.n 8007ada 8007a58: 687b ldr r3, [r7, #4] 8007a5a: 681b ldr r3, [r3, #0] 8007a5c: 4a71 ldr r2, [pc, #452] @ (8007c24 ) 8007a5e: 4293 cmp r3, r2 8007a60: d03b beq.n 8007ada 8007a62: 687b ldr r3, [r7, #4] 8007a64: 681b ldr r3, [r3, #0] 8007a66: 4a70 ldr r2, [pc, #448] @ (8007c28 ) 8007a68: 4293 cmp r3, r2 8007a6a: d036 beq.n 8007ada 8007a6c: 687b ldr r3, [r7, #4] 8007a6e: 681b ldr r3, [r3, #0] 8007a70: 4a6e ldr r2, [pc, #440] @ (8007c2c ) 8007a72: 4293 cmp r3, r2 8007a74: d031 beq.n 8007ada 8007a76: 687b ldr r3, [r7, #4] 8007a78: 681b ldr r3, [r3, #0] 8007a7a: 4a6d ldr r2, [pc, #436] @ (8007c30 ) 8007a7c: 4293 cmp r3, r2 8007a7e: d02c beq.n 8007ada 8007a80: 687b ldr r3, [r7, #4] 8007a82: 681b ldr r3, [r3, #0] 8007a84: 4a6b ldr r2, [pc, #428] @ (8007c34 ) 8007a86: 4293 cmp r3, r2 8007a88: d027 beq.n 8007ada 8007a8a: 687b ldr r3, [r7, #4] 8007a8c: 681b ldr r3, [r3, #0] 8007a8e: 4a6a ldr r2, [pc, #424] @ (8007c38 ) 8007a90: 4293 cmp r3, r2 8007a92: d022 beq.n 8007ada 8007a94: 687b ldr r3, [r7, #4] 8007a96: 681b ldr r3, [r3, #0] 8007a98: 4a68 ldr r2, [pc, #416] @ (8007c3c ) 8007a9a: 4293 cmp r3, r2 8007a9c: d01d beq.n 8007ada 8007a9e: 687b ldr r3, [r7, #4] 8007aa0: 681b ldr r3, [r3, #0] 8007aa2: 4a67 ldr r2, [pc, #412] @ (8007c40 ) 8007aa4: 4293 cmp r3, r2 8007aa6: d018 beq.n 8007ada 8007aa8: 687b ldr r3, [r7, #4] 8007aaa: 681b ldr r3, [r3, #0] 8007aac: 4a65 ldr r2, [pc, #404] @ (8007c44 ) 8007aae: 4293 cmp r3, r2 8007ab0: d013 beq.n 8007ada 8007ab2: 687b ldr r3, [r7, #4] 8007ab4: 681b ldr r3, [r3, #0] 8007ab6: 4a64 ldr r2, [pc, #400] @ (8007c48 ) 8007ab8: 4293 cmp r3, r2 8007aba: d00e beq.n 8007ada 8007abc: 687b ldr r3, [r7, #4] 8007abe: 681b ldr r3, [r3, #0] 8007ac0: 4a62 ldr r2, [pc, #392] @ (8007c4c ) 8007ac2: 4293 cmp r3, r2 8007ac4: d009 beq.n 8007ada 8007ac6: 687b ldr r3, [r7, #4] 8007ac8: 681b ldr r3, [r3, #0] 8007aca: 4a61 ldr r2, [pc, #388] @ (8007c50 ) 8007acc: 4293 cmp r3, r2 8007ace: d004 beq.n 8007ada 8007ad0: 687b ldr r3, [r7, #4] 8007ad2: 681b ldr r3, [r3, #0] 8007ad4: 4a5f ldr r2, [pc, #380] @ (8007c54 ) 8007ad6: 4293 cmp r3, r2 8007ad8: d101 bne.n 8007ade 8007ada: 2301 movs r3, #1 8007adc: e000 b.n 8007ae0 8007ade: 2300 movs r3, #0 8007ae0: 2b00 cmp r3, #0 8007ae2: d013 beq.n 8007b0c { /* Disable DMA All Interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 8007ae4: 687b ldr r3, [r7, #4] 8007ae6: 681b ldr r3, [r3, #0] 8007ae8: 681a ldr r2, [r3, #0] 8007aea: 687b ldr r3, [r7, #4] 8007aec: 681b ldr r3, [r3, #0] 8007aee: f022 021e bic.w r2, r2, #30 8007af2: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 8007af4: 687b ldr r3, [r7, #4] 8007af6: 681b ldr r3, [r3, #0] 8007af8: 695a ldr r2, [r3, #20] 8007afa: 687b ldr r3, [r7, #4] 8007afc: 681b ldr r3, [r3, #0] 8007afe: f022 0280 bic.w r2, r2, #128 @ 0x80 8007b02: 615a str r2, [r3, #20] enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); 8007b04: 687b ldr r3, [r7, #4] 8007b06: 681b ldr r3, [r3, #0] 8007b08: 617b str r3, [r7, #20] 8007b0a: e00a b.n 8007b22 } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 8007b0c: 687b ldr r3, [r7, #4] 8007b0e: 681b ldr r3, [r3, #0] 8007b10: 681a ldr r2, [r3, #0] 8007b12: 687b ldr r3, [r7, #4] 8007b14: 681b ldr r3, [r3, #0] 8007b16: f022 020e bic.w r2, r2, #14 8007b1a: 601a str r2, [r3, #0] enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); 8007b1c: 687b ldr r3, [r7, #4] 8007b1e: 681b ldr r3, [r3, #0] 8007b20: 617b str r3, [r7, #20] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8007b22: 687b ldr r3, [r7, #4] 8007b24: 681b ldr r3, [r3, #0] 8007b26: 4a3c ldr r2, [pc, #240] @ (8007c18 ) 8007b28: 4293 cmp r3, r2 8007b2a: d072 beq.n 8007c12 8007b2c: 687b ldr r3, [r7, #4] 8007b2e: 681b ldr r3, [r3, #0] 8007b30: 4a3a ldr r2, [pc, #232] @ (8007c1c ) 8007b32: 4293 cmp r3, r2 8007b34: d06d beq.n 8007c12 8007b36: 687b ldr r3, [r7, #4] 8007b38: 681b ldr r3, [r3, #0] 8007b3a: 4a39 ldr r2, [pc, #228] @ (8007c20 ) 8007b3c: 4293 cmp r3, r2 8007b3e: d068 beq.n 8007c12 8007b40: 687b ldr r3, [r7, #4] 8007b42: 681b ldr r3, [r3, #0] 8007b44: 4a37 ldr r2, [pc, #220] @ (8007c24 ) 8007b46: 4293 cmp r3, r2 8007b48: d063 beq.n 8007c12 8007b4a: 687b ldr r3, [r7, #4] 8007b4c: 681b ldr r3, [r3, #0] 8007b4e: 4a36 ldr r2, [pc, #216] @ (8007c28 ) 8007b50: 4293 cmp r3, r2 8007b52: d05e beq.n 8007c12 8007b54: 687b ldr r3, [r7, #4] 8007b56: 681b ldr r3, [r3, #0] 8007b58: 4a34 ldr r2, [pc, #208] @ (8007c2c ) 8007b5a: 4293 cmp r3, r2 8007b5c: d059 beq.n 8007c12 8007b5e: 687b ldr r3, [r7, #4] 8007b60: 681b ldr r3, [r3, #0] 8007b62: 4a33 ldr r2, [pc, #204] @ (8007c30 ) 8007b64: 4293 cmp r3, r2 8007b66: d054 beq.n 8007c12 8007b68: 687b ldr r3, [r7, #4] 8007b6a: 681b ldr r3, [r3, #0] 8007b6c: 4a31 ldr r2, [pc, #196] @ (8007c34 ) 8007b6e: 4293 cmp r3, r2 8007b70: d04f beq.n 8007c12 8007b72: 687b ldr r3, [r7, #4] 8007b74: 681b ldr r3, [r3, #0] 8007b76: 4a30 ldr r2, [pc, #192] @ (8007c38 ) 8007b78: 4293 cmp r3, r2 8007b7a: d04a beq.n 8007c12 8007b7c: 687b ldr r3, [r7, #4] 8007b7e: 681b ldr r3, [r3, #0] 8007b80: 4a2e ldr r2, [pc, #184] @ (8007c3c ) 8007b82: 4293 cmp r3, r2 8007b84: d045 beq.n 8007c12 8007b86: 687b ldr r3, [r7, #4] 8007b88: 681b ldr r3, [r3, #0] 8007b8a: 4a2d ldr r2, [pc, #180] @ (8007c40 ) 8007b8c: 4293 cmp r3, r2 8007b8e: d040 beq.n 8007c12 8007b90: 687b ldr r3, [r7, #4] 8007b92: 681b ldr r3, [r3, #0] 8007b94: 4a2b ldr r2, [pc, #172] @ (8007c44 ) 8007b96: 4293 cmp r3, r2 8007b98: d03b beq.n 8007c12 8007b9a: 687b ldr r3, [r7, #4] 8007b9c: 681b ldr r3, [r3, #0] 8007b9e: 4a2a ldr r2, [pc, #168] @ (8007c48 ) 8007ba0: 4293 cmp r3, r2 8007ba2: d036 beq.n 8007c12 8007ba4: 687b ldr r3, [r7, #4] 8007ba6: 681b ldr r3, [r3, #0] 8007ba8: 4a28 ldr r2, [pc, #160] @ (8007c4c ) 8007baa: 4293 cmp r3, r2 8007bac: d031 beq.n 8007c12 8007bae: 687b ldr r3, [r7, #4] 8007bb0: 681b ldr r3, [r3, #0] 8007bb2: 4a27 ldr r2, [pc, #156] @ (8007c50 ) 8007bb4: 4293 cmp r3, r2 8007bb6: d02c beq.n 8007c12 8007bb8: 687b ldr r3, [r7, #4] 8007bba: 681b ldr r3, [r3, #0] 8007bbc: 4a25 ldr r2, [pc, #148] @ (8007c54 ) 8007bbe: 4293 cmp r3, r2 8007bc0: d027 beq.n 8007c12 8007bc2: 687b ldr r3, [r7, #4] 8007bc4: 681b ldr r3, [r3, #0] 8007bc6: 4a24 ldr r2, [pc, #144] @ (8007c58 ) 8007bc8: 4293 cmp r3, r2 8007bca: d022 beq.n 8007c12 8007bcc: 687b ldr r3, [r7, #4] 8007bce: 681b ldr r3, [r3, #0] 8007bd0: 4a22 ldr r2, [pc, #136] @ (8007c5c ) 8007bd2: 4293 cmp r3, r2 8007bd4: d01d beq.n 8007c12 8007bd6: 687b ldr r3, [r7, #4] 8007bd8: 681b ldr r3, [r3, #0] 8007bda: 4a21 ldr r2, [pc, #132] @ (8007c60 ) 8007bdc: 4293 cmp r3, r2 8007bde: d018 beq.n 8007c12 8007be0: 687b ldr r3, [r7, #4] 8007be2: 681b ldr r3, [r3, #0] 8007be4: 4a1f ldr r2, [pc, #124] @ (8007c64 ) 8007be6: 4293 cmp r3, r2 8007be8: d013 beq.n 8007c12 8007bea: 687b ldr r3, [r7, #4] 8007bec: 681b ldr r3, [r3, #0] 8007bee: 4a1e ldr r2, [pc, #120] @ (8007c68 ) 8007bf0: 4293 cmp r3, r2 8007bf2: d00e beq.n 8007c12 8007bf4: 687b ldr r3, [r7, #4] 8007bf6: 681b ldr r3, [r3, #0] 8007bf8: 4a1c ldr r2, [pc, #112] @ (8007c6c ) 8007bfa: 4293 cmp r3, r2 8007bfc: d009 beq.n 8007c12 8007bfe: 687b ldr r3, [r7, #4] 8007c00: 681b ldr r3, [r3, #0] 8007c02: 4a1b ldr r2, [pc, #108] @ (8007c70 ) 8007c04: 4293 cmp r3, r2 8007c06: d004 beq.n 8007c12 8007c08: 687b ldr r3, [r7, #4] 8007c0a: 681b ldr r3, [r3, #0] 8007c0c: 4a19 ldr r2, [pc, #100] @ (8007c74 ) 8007c0e: 4293 cmp r3, r2 8007c10: d132 bne.n 8007c78 8007c12: 2301 movs r3, #1 8007c14: e031 b.n 8007c7a 8007c16: bf00 nop 8007c18: 40020010 .word 0x40020010 8007c1c: 40020028 .word 0x40020028 8007c20: 40020040 .word 0x40020040 8007c24: 40020058 .word 0x40020058 8007c28: 40020070 .word 0x40020070 8007c2c: 40020088 .word 0x40020088 8007c30: 400200a0 .word 0x400200a0 8007c34: 400200b8 .word 0x400200b8 8007c38: 40020410 .word 0x40020410 8007c3c: 40020428 .word 0x40020428 8007c40: 40020440 .word 0x40020440 8007c44: 40020458 .word 0x40020458 8007c48: 40020470 .word 0x40020470 8007c4c: 40020488 .word 0x40020488 8007c50: 400204a0 .word 0x400204a0 8007c54: 400204b8 .word 0x400204b8 8007c58: 58025408 .word 0x58025408 8007c5c: 5802541c .word 0x5802541c 8007c60: 58025430 .word 0x58025430 8007c64: 58025444 .word 0x58025444 8007c68: 58025458 .word 0x58025458 8007c6c: 5802546c .word 0x5802546c 8007c70: 58025480 .word 0x58025480 8007c74: 58025494 .word 0x58025494 8007c78: 2300 movs r3, #0 8007c7a: 2b00 cmp r3, #0 8007c7c: d007 beq.n 8007c8e { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8007c7e: 687b ldr r3, [r7, #4] 8007c80: 6e1b ldr r3, [r3, #96] @ 0x60 8007c82: 681a ldr r2, [r3, #0] 8007c84: 687b ldr r3, [r7, #4] 8007c86: 6e1b ldr r3, [r3, #96] @ 0x60 8007c88: f422 7280 bic.w r2, r2, #256 @ 0x100 8007c8c: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8007c8e: 687b ldr r3, [r7, #4] 8007c90: 681b ldr r3, [r3, #0] 8007c92: 4a6d ldr r2, [pc, #436] @ (8007e48 ) 8007c94: 4293 cmp r3, r2 8007c96: d04a beq.n 8007d2e 8007c98: 687b ldr r3, [r7, #4] 8007c9a: 681b ldr r3, [r3, #0] 8007c9c: 4a6b ldr r2, [pc, #428] @ (8007e4c ) 8007c9e: 4293 cmp r3, r2 8007ca0: d045 beq.n 8007d2e 8007ca2: 687b ldr r3, [r7, #4] 8007ca4: 681b ldr r3, [r3, #0] 8007ca6: 4a6a ldr r2, [pc, #424] @ (8007e50 ) 8007ca8: 4293 cmp r3, r2 8007caa: d040 beq.n 8007d2e 8007cac: 687b ldr r3, [r7, #4] 8007cae: 681b ldr r3, [r3, #0] 8007cb0: 4a68 ldr r2, [pc, #416] @ (8007e54 ) 8007cb2: 4293 cmp r3, r2 8007cb4: d03b beq.n 8007d2e 8007cb6: 687b ldr r3, [r7, #4] 8007cb8: 681b ldr r3, [r3, #0] 8007cba: 4a67 ldr r2, [pc, #412] @ (8007e58 ) 8007cbc: 4293 cmp r3, r2 8007cbe: d036 beq.n 8007d2e 8007cc0: 687b ldr r3, [r7, #4] 8007cc2: 681b ldr r3, [r3, #0] 8007cc4: 4a65 ldr r2, [pc, #404] @ (8007e5c ) 8007cc6: 4293 cmp r3, r2 8007cc8: d031 beq.n 8007d2e 8007cca: 687b ldr r3, [r7, #4] 8007ccc: 681b ldr r3, [r3, #0] 8007cce: 4a64 ldr r2, [pc, #400] @ (8007e60 ) 8007cd0: 4293 cmp r3, r2 8007cd2: d02c beq.n 8007d2e 8007cd4: 687b ldr r3, [r7, #4] 8007cd6: 681b ldr r3, [r3, #0] 8007cd8: 4a62 ldr r2, [pc, #392] @ (8007e64 ) 8007cda: 4293 cmp r3, r2 8007cdc: d027 beq.n 8007d2e 8007cde: 687b ldr r3, [r7, #4] 8007ce0: 681b ldr r3, [r3, #0] 8007ce2: 4a61 ldr r2, [pc, #388] @ (8007e68 ) 8007ce4: 4293 cmp r3, r2 8007ce6: d022 beq.n 8007d2e 8007ce8: 687b ldr r3, [r7, #4] 8007cea: 681b ldr r3, [r3, #0] 8007cec: 4a5f ldr r2, [pc, #380] @ (8007e6c ) 8007cee: 4293 cmp r3, r2 8007cf0: d01d beq.n 8007d2e 8007cf2: 687b ldr r3, [r7, #4] 8007cf4: 681b ldr r3, [r3, #0] 8007cf6: 4a5e ldr r2, [pc, #376] @ (8007e70 ) 8007cf8: 4293 cmp r3, r2 8007cfa: d018 beq.n 8007d2e 8007cfc: 687b ldr r3, [r7, #4] 8007cfe: 681b ldr r3, [r3, #0] 8007d00: 4a5c ldr r2, [pc, #368] @ (8007e74 ) 8007d02: 4293 cmp r3, r2 8007d04: d013 beq.n 8007d2e 8007d06: 687b ldr r3, [r7, #4] 8007d08: 681b ldr r3, [r3, #0] 8007d0a: 4a5b ldr r2, [pc, #364] @ (8007e78 ) 8007d0c: 4293 cmp r3, r2 8007d0e: d00e beq.n 8007d2e 8007d10: 687b ldr r3, [r7, #4] 8007d12: 681b ldr r3, [r3, #0] 8007d14: 4a59 ldr r2, [pc, #356] @ (8007e7c ) 8007d16: 4293 cmp r3, r2 8007d18: d009 beq.n 8007d2e 8007d1a: 687b ldr r3, [r7, #4] 8007d1c: 681b ldr r3, [r3, #0] 8007d1e: 4a58 ldr r2, [pc, #352] @ (8007e80 ) 8007d20: 4293 cmp r3, r2 8007d22: d004 beq.n 8007d2e 8007d24: 687b ldr r3, [r7, #4] 8007d26: 681b ldr r3, [r3, #0] 8007d28: 4a56 ldr r2, [pc, #344] @ (8007e84 ) 8007d2a: 4293 cmp r3, r2 8007d2c: d108 bne.n 8007d40 8007d2e: 687b ldr r3, [r7, #4] 8007d30: 681b ldr r3, [r3, #0] 8007d32: 681a ldr r2, [r3, #0] 8007d34: 687b ldr r3, [r7, #4] 8007d36: 681b ldr r3, [r3, #0] 8007d38: f022 0201 bic.w r2, r2, #1 8007d3c: 601a str r2, [r3, #0] 8007d3e: e007 b.n 8007d50 8007d40: 687b ldr r3, [r7, #4] 8007d42: 681b ldr r3, [r3, #0] 8007d44: 681a ldr r2, [r3, #0] 8007d46: 687b ldr r3, [r7, #4] 8007d48: 681b ldr r3, [r3, #0] 8007d4a: f022 0201 bic.w r2, r2, #1 8007d4e: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while(((*enableRegister) & DMA_SxCR_EN) != 0U) 8007d50: e013 b.n 8007d7a { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8007d52: f7fc fe87 bl 8004a64 8007d56: 4602 mov r2, r0 8007d58: 693b ldr r3, [r7, #16] 8007d5a: 1ad3 subs r3, r2, r3 8007d5c: 2b05 cmp r3, #5 8007d5e: d90c bls.n 8007d7a { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8007d60: 687b ldr r3, [r7, #4] 8007d62: 2220 movs r2, #32 8007d64: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 8007d66: 687b ldr r3, [r7, #4] 8007d68: 2203 movs r2, #3 8007d6a: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8007d6e: 687b ldr r3, [r7, #4] 8007d70: 2200 movs r2, #0 8007d72: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8007d76: 2301 movs r3, #1 8007d78: e12d b.n 8007fd6 while(((*enableRegister) & DMA_SxCR_EN) != 0U) 8007d7a: 697b ldr r3, [r7, #20] 8007d7c: 681b ldr r3, [r3, #0] 8007d7e: f003 0301 and.w r3, r3, #1 8007d82: 2b00 cmp r3, #0 8007d84: d1e5 bne.n 8007d52 } } /* Clear all interrupt flags at correct offset within the register */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8007d86: 687b ldr r3, [r7, #4] 8007d88: 681b ldr r3, [r3, #0] 8007d8a: 4a2f ldr r2, [pc, #188] @ (8007e48 ) 8007d8c: 4293 cmp r3, r2 8007d8e: d04a beq.n 8007e26 8007d90: 687b ldr r3, [r7, #4] 8007d92: 681b ldr r3, [r3, #0] 8007d94: 4a2d ldr r2, [pc, #180] @ (8007e4c ) 8007d96: 4293 cmp r3, r2 8007d98: d045 beq.n 8007e26 8007d9a: 687b ldr r3, [r7, #4] 8007d9c: 681b ldr r3, [r3, #0] 8007d9e: 4a2c ldr r2, [pc, #176] @ (8007e50 ) 8007da0: 4293 cmp r3, r2 8007da2: d040 beq.n 8007e26 8007da4: 687b ldr r3, [r7, #4] 8007da6: 681b ldr r3, [r3, #0] 8007da8: 4a2a ldr r2, [pc, #168] @ (8007e54 ) 8007daa: 4293 cmp r3, r2 8007dac: d03b beq.n 8007e26 8007dae: 687b ldr r3, [r7, #4] 8007db0: 681b ldr r3, [r3, #0] 8007db2: 4a29 ldr r2, [pc, #164] @ (8007e58 ) 8007db4: 4293 cmp r3, r2 8007db6: d036 beq.n 8007e26 8007db8: 687b ldr r3, [r7, #4] 8007dba: 681b ldr r3, [r3, #0] 8007dbc: 4a27 ldr r2, [pc, #156] @ (8007e5c ) 8007dbe: 4293 cmp r3, r2 8007dc0: d031 beq.n 8007e26 8007dc2: 687b ldr r3, [r7, #4] 8007dc4: 681b ldr r3, [r3, #0] 8007dc6: 4a26 ldr r2, [pc, #152] @ (8007e60 ) 8007dc8: 4293 cmp r3, r2 8007dca: d02c beq.n 8007e26 8007dcc: 687b ldr r3, [r7, #4] 8007dce: 681b ldr r3, [r3, #0] 8007dd0: 4a24 ldr r2, [pc, #144] @ (8007e64 ) 8007dd2: 4293 cmp r3, r2 8007dd4: d027 beq.n 8007e26 8007dd6: 687b ldr r3, [r7, #4] 8007dd8: 681b ldr r3, [r3, #0] 8007dda: 4a23 ldr r2, [pc, #140] @ (8007e68 ) 8007ddc: 4293 cmp r3, r2 8007dde: d022 beq.n 8007e26 8007de0: 687b ldr r3, [r7, #4] 8007de2: 681b ldr r3, [r3, #0] 8007de4: 4a21 ldr r2, [pc, #132] @ (8007e6c ) 8007de6: 4293 cmp r3, r2 8007de8: d01d beq.n 8007e26 8007dea: 687b ldr r3, [r7, #4] 8007dec: 681b ldr r3, [r3, #0] 8007dee: 4a20 ldr r2, [pc, #128] @ (8007e70 ) 8007df0: 4293 cmp r3, r2 8007df2: d018 beq.n 8007e26 8007df4: 687b ldr r3, [r7, #4] 8007df6: 681b ldr r3, [r3, #0] 8007df8: 4a1e ldr r2, [pc, #120] @ (8007e74 ) 8007dfa: 4293 cmp r3, r2 8007dfc: d013 beq.n 8007e26 8007dfe: 687b ldr r3, [r7, #4] 8007e00: 681b ldr r3, [r3, #0] 8007e02: 4a1d ldr r2, [pc, #116] @ (8007e78 ) 8007e04: 4293 cmp r3, r2 8007e06: d00e beq.n 8007e26 8007e08: 687b ldr r3, [r7, #4] 8007e0a: 681b ldr r3, [r3, #0] 8007e0c: 4a1b ldr r2, [pc, #108] @ (8007e7c ) 8007e0e: 4293 cmp r3, r2 8007e10: d009 beq.n 8007e26 8007e12: 687b ldr r3, [r7, #4] 8007e14: 681b ldr r3, [r3, #0] 8007e16: 4a1a ldr r2, [pc, #104] @ (8007e80 ) 8007e18: 4293 cmp r3, r2 8007e1a: d004 beq.n 8007e26 8007e1c: 687b ldr r3, [r7, #4] 8007e1e: 681b ldr r3, [r3, #0] 8007e20: 4a18 ldr r2, [pc, #96] @ (8007e84 ) 8007e22: 4293 cmp r3, r2 8007e24: d101 bne.n 8007e2a 8007e26: 2301 movs r3, #1 8007e28: e000 b.n 8007e2c 8007e2a: 2300 movs r3, #0 8007e2c: 2b00 cmp r3, #0 8007e2e: d02b beq.n 8007e88 { regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8007e30: 687b ldr r3, [r7, #4] 8007e32: 6d9b ldr r3, [r3, #88] @ 0x58 8007e34: 60bb str r3, [r7, #8] regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8007e36: 687b ldr r3, [r7, #4] 8007e38: 6ddb ldr r3, [r3, #92] @ 0x5c 8007e3a: f003 031f and.w r3, r3, #31 8007e3e: 223f movs r2, #63 @ 0x3f 8007e40: 409a lsls r2, r3 8007e42: 68bb ldr r3, [r7, #8] 8007e44: 609a str r2, [r3, #8] 8007e46: e02a b.n 8007e9e 8007e48: 40020010 .word 0x40020010 8007e4c: 40020028 .word 0x40020028 8007e50: 40020040 .word 0x40020040 8007e54: 40020058 .word 0x40020058 8007e58: 40020070 .word 0x40020070 8007e5c: 40020088 .word 0x40020088 8007e60: 400200a0 .word 0x400200a0 8007e64: 400200b8 .word 0x400200b8 8007e68: 40020410 .word 0x40020410 8007e6c: 40020428 .word 0x40020428 8007e70: 40020440 .word 0x40020440 8007e74: 40020458 .word 0x40020458 8007e78: 40020470 .word 0x40020470 8007e7c: 40020488 .word 0x40020488 8007e80: 400204a0 .word 0x400204a0 8007e84: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8007e88: 687b ldr r3, [r7, #4] 8007e8a: 6d9b ldr r3, [r3, #88] @ 0x58 8007e8c: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8007e8e: 687b ldr r3, [r7, #4] 8007e90: 6ddb ldr r3, [r3, #92] @ 0x5c 8007e92: f003 031f and.w r3, r3, #31 8007e96: 2201 movs r2, #1 8007e98: 409a lsls r2, r3 8007e9a: 68fb ldr r3, [r7, #12] 8007e9c: 605a str r2, [r3, #4] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8007e9e: 687b ldr r3, [r7, #4] 8007ea0: 681b ldr r3, [r3, #0] 8007ea2: 4a4f ldr r2, [pc, #316] @ (8007fe0 ) 8007ea4: 4293 cmp r3, r2 8007ea6: d072 beq.n 8007f8e 8007ea8: 687b ldr r3, [r7, #4] 8007eaa: 681b ldr r3, [r3, #0] 8007eac: 4a4d ldr r2, [pc, #308] @ (8007fe4 ) 8007eae: 4293 cmp r3, r2 8007eb0: d06d beq.n 8007f8e 8007eb2: 687b ldr r3, [r7, #4] 8007eb4: 681b ldr r3, [r3, #0] 8007eb6: 4a4c ldr r2, [pc, #304] @ (8007fe8 ) 8007eb8: 4293 cmp r3, r2 8007eba: d068 beq.n 8007f8e 8007ebc: 687b ldr r3, [r7, #4] 8007ebe: 681b ldr r3, [r3, #0] 8007ec0: 4a4a ldr r2, [pc, #296] @ (8007fec ) 8007ec2: 4293 cmp r3, r2 8007ec4: d063 beq.n 8007f8e 8007ec6: 687b ldr r3, [r7, #4] 8007ec8: 681b ldr r3, [r3, #0] 8007eca: 4a49 ldr r2, [pc, #292] @ (8007ff0 ) 8007ecc: 4293 cmp r3, r2 8007ece: d05e beq.n 8007f8e 8007ed0: 687b ldr r3, [r7, #4] 8007ed2: 681b ldr r3, [r3, #0] 8007ed4: 4a47 ldr r2, [pc, #284] @ (8007ff4 ) 8007ed6: 4293 cmp r3, r2 8007ed8: d059 beq.n 8007f8e 8007eda: 687b ldr r3, [r7, #4] 8007edc: 681b ldr r3, [r3, #0] 8007ede: 4a46 ldr r2, [pc, #280] @ (8007ff8 ) 8007ee0: 4293 cmp r3, r2 8007ee2: d054 beq.n 8007f8e 8007ee4: 687b ldr r3, [r7, #4] 8007ee6: 681b ldr r3, [r3, #0] 8007ee8: 4a44 ldr r2, [pc, #272] @ (8007ffc ) 8007eea: 4293 cmp r3, r2 8007eec: d04f beq.n 8007f8e 8007eee: 687b ldr r3, [r7, #4] 8007ef0: 681b ldr r3, [r3, #0] 8007ef2: 4a43 ldr r2, [pc, #268] @ (8008000 ) 8007ef4: 4293 cmp r3, r2 8007ef6: d04a beq.n 8007f8e 8007ef8: 687b ldr r3, [r7, #4] 8007efa: 681b ldr r3, [r3, #0] 8007efc: 4a41 ldr r2, [pc, #260] @ (8008004 ) 8007efe: 4293 cmp r3, r2 8007f00: d045 beq.n 8007f8e 8007f02: 687b ldr r3, [r7, #4] 8007f04: 681b ldr r3, [r3, #0] 8007f06: 4a40 ldr r2, [pc, #256] @ (8008008 ) 8007f08: 4293 cmp r3, r2 8007f0a: d040 beq.n 8007f8e 8007f0c: 687b ldr r3, [r7, #4] 8007f0e: 681b ldr r3, [r3, #0] 8007f10: 4a3e ldr r2, [pc, #248] @ (800800c ) 8007f12: 4293 cmp r3, r2 8007f14: d03b beq.n 8007f8e 8007f16: 687b ldr r3, [r7, #4] 8007f18: 681b ldr r3, [r3, #0] 8007f1a: 4a3d ldr r2, [pc, #244] @ (8008010 ) 8007f1c: 4293 cmp r3, r2 8007f1e: d036 beq.n 8007f8e 8007f20: 687b ldr r3, [r7, #4] 8007f22: 681b ldr r3, [r3, #0] 8007f24: 4a3b ldr r2, [pc, #236] @ (8008014 ) 8007f26: 4293 cmp r3, r2 8007f28: d031 beq.n 8007f8e 8007f2a: 687b ldr r3, [r7, #4] 8007f2c: 681b ldr r3, [r3, #0] 8007f2e: 4a3a ldr r2, [pc, #232] @ (8008018 ) 8007f30: 4293 cmp r3, r2 8007f32: d02c beq.n 8007f8e 8007f34: 687b ldr r3, [r7, #4] 8007f36: 681b ldr r3, [r3, #0] 8007f38: 4a38 ldr r2, [pc, #224] @ (800801c ) 8007f3a: 4293 cmp r3, r2 8007f3c: d027 beq.n 8007f8e 8007f3e: 687b ldr r3, [r7, #4] 8007f40: 681b ldr r3, [r3, #0] 8007f42: 4a37 ldr r2, [pc, #220] @ (8008020 ) 8007f44: 4293 cmp r3, r2 8007f46: d022 beq.n 8007f8e 8007f48: 687b ldr r3, [r7, #4] 8007f4a: 681b ldr r3, [r3, #0] 8007f4c: 4a35 ldr r2, [pc, #212] @ (8008024 ) 8007f4e: 4293 cmp r3, r2 8007f50: d01d beq.n 8007f8e 8007f52: 687b ldr r3, [r7, #4] 8007f54: 681b ldr r3, [r3, #0] 8007f56: 4a34 ldr r2, [pc, #208] @ (8008028 ) 8007f58: 4293 cmp r3, r2 8007f5a: d018 beq.n 8007f8e 8007f5c: 687b ldr r3, [r7, #4] 8007f5e: 681b ldr r3, [r3, #0] 8007f60: 4a32 ldr r2, [pc, #200] @ (800802c ) 8007f62: 4293 cmp r3, r2 8007f64: d013 beq.n 8007f8e 8007f66: 687b ldr r3, [r7, #4] 8007f68: 681b ldr r3, [r3, #0] 8007f6a: 4a31 ldr r2, [pc, #196] @ (8008030 ) 8007f6c: 4293 cmp r3, r2 8007f6e: d00e beq.n 8007f8e 8007f70: 687b ldr r3, [r7, #4] 8007f72: 681b ldr r3, [r3, #0] 8007f74: 4a2f ldr r2, [pc, #188] @ (8008034 ) 8007f76: 4293 cmp r3, r2 8007f78: d009 beq.n 8007f8e 8007f7a: 687b ldr r3, [r7, #4] 8007f7c: 681b ldr r3, [r3, #0] 8007f7e: 4a2e ldr r2, [pc, #184] @ (8008038 ) 8007f80: 4293 cmp r3, r2 8007f82: d004 beq.n 8007f8e 8007f84: 687b ldr r3, [r7, #4] 8007f86: 681b ldr r3, [r3, #0] 8007f88: 4a2c ldr r2, [pc, #176] @ (800803c ) 8007f8a: 4293 cmp r3, r2 8007f8c: d101 bne.n 8007f92 8007f8e: 2301 movs r3, #1 8007f90: e000 b.n 8007f94 8007f92: 2300 movs r3, #0 8007f94: 2b00 cmp r3, #0 8007f96: d015 beq.n 8007fc4 { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8007f98: 687b ldr r3, [r7, #4] 8007f9a: 6e5b ldr r3, [r3, #100] @ 0x64 8007f9c: 687a ldr r2, [r7, #4] 8007f9e: 6e92 ldr r2, [r2, #104] @ 0x68 8007fa0: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 8007fa2: 687b ldr r3, [r7, #4] 8007fa4: 6edb ldr r3, [r3, #108] @ 0x6c 8007fa6: 2b00 cmp r3, #0 8007fa8: d00c beq.n 8007fc4 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8007faa: 687b ldr r3, [r7, #4] 8007fac: 6edb ldr r3, [r3, #108] @ 0x6c 8007fae: 681a ldr r2, [r3, #0] 8007fb0: 687b ldr r3, [r7, #4] 8007fb2: 6edb ldr r3, [r3, #108] @ 0x6c 8007fb4: f422 7280 bic.w r2, r2, #256 @ 0x100 8007fb8: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8007fba: 687b ldr r3, [r7, #4] 8007fbc: 6f1b ldr r3, [r3, #112] @ 0x70 8007fbe: 687a ldr r2, [r7, #4] 8007fc0: 6f52 ldr r2, [r2, #116] @ 0x74 8007fc2: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8007fc4: 687b ldr r3, [r7, #4] 8007fc6: 2201 movs r2, #1 8007fc8: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8007fcc: 687b ldr r3, [r7, #4] 8007fce: 2200 movs r2, #0 8007fd0: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 8007fd4: 2300 movs r3, #0 } 8007fd6: 4618 mov r0, r3 8007fd8: 3718 adds r7, #24 8007fda: 46bd mov sp, r7 8007fdc: bd80 pop {r7, pc} 8007fde: bf00 nop 8007fe0: 40020010 .word 0x40020010 8007fe4: 40020028 .word 0x40020028 8007fe8: 40020040 .word 0x40020040 8007fec: 40020058 .word 0x40020058 8007ff0: 40020070 .word 0x40020070 8007ff4: 40020088 .word 0x40020088 8007ff8: 400200a0 .word 0x400200a0 8007ffc: 400200b8 .word 0x400200b8 8008000: 40020410 .word 0x40020410 8008004: 40020428 .word 0x40020428 8008008: 40020440 .word 0x40020440 800800c: 40020458 .word 0x40020458 8008010: 40020470 .word 0x40020470 8008014: 40020488 .word 0x40020488 8008018: 400204a0 .word 0x400204a0 800801c: 400204b8 .word 0x400204b8 8008020: 58025408 .word 0x58025408 8008024: 5802541c .word 0x5802541c 8008028: 58025430 .word 0x58025430 800802c: 58025444 .word 0x58025444 8008030: 58025458 .word 0x58025458 8008034: 5802546c .word 0x5802546c 8008038: 58025480 .word 0x58025480 800803c: 58025494 .word 0x58025494 08008040 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8008040: b580 push {r7, lr} 8008042: b084 sub sp, #16 8008044: af00 add r7, sp, #0 8008046: 6078 str r0, [r7, #4] BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 8008048: 687b ldr r3, [r7, #4] 800804a: 2b00 cmp r3, #0 800804c: d101 bne.n 8008052 { return HAL_ERROR; 800804e: 2301 movs r3, #1 8008050: e237 b.n 80084c2 } if(hdma->State != HAL_DMA_STATE_BUSY) 8008052: 687b ldr r3, [r7, #4] 8008054: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8008058: b2db uxtb r3, r3 800805a: 2b02 cmp r3, #2 800805c: d004 beq.n 8008068 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800805e: 687b ldr r3, [r7, #4] 8008060: 2280 movs r2, #128 @ 0x80 8008062: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 8008064: 2301 movs r3, #1 8008066: e22c b.n 80084c2 } else { if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8008068: 687b ldr r3, [r7, #4] 800806a: 681b ldr r3, [r3, #0] 800806c: 4a5c ldr r2, [pc, #368] @ (80081e0 ) 800806e: 4293 cmp r3, r2 8008070: d04a beq.n 8008108 8008072: 687b ldr r3, [r7, #4] 8008074: 681b ldr r3, [r3, #0] 8008076: 4a5b ldr r2, [pc, #364] @ (80081e4 ) 8008078: 4293 cmp r3, r2 800807a: d045 beq.n 8008108 800807c: 687b ldr r3, [r7, #4] 800807e: 681b ldr r3, [r3, #0] 8008080: 4a59 ldr r2, [pc, #356] @ (80081e8 ) 8008082: 4293 cmp r3, r2 8008084: d040 beq.n 8008108 8008086: 687b ldr r3, [r7, #4] 8008088: 681b ldr r3, [r3, #0] 800808a: 4a58 ldr r2, [pc, #352] @ (80081ec ) 800808c: 4293 cmp r3, r2 800808e: d03b beq.n 8008108 8008090: 687b ldr r3, [r7, #4] 8008092: 681b ldr r3, [r3, #0] 8008094: 4a56 ldr r2, [pc, #344] @ (80081f0 ) 8008096: 4293 cmp r3, r2 8008098: d036 beq.n 8008108 800809a: 687b ldr r3, [r7, #4] 800809c: 681b ldr r3, [r3, #0] 800809e: 4a55 ldr r2, [pc, #340] @ (80081f4 ) 80080a0: 4293 cmp r3, r2 80080a2: d031 beq.n 8008108 80080a4: 687b ldr r3, [r7, #4] 80080a6: 681b ldr r3, [r3, #0] 80080a8: 4a53 ldr r2, [pc, #332] @ (80081f8 ) 80080aa: 4293 cmp r3, r2 80080ac: d02c beq.n 8008108 80080ae: 687b ldr r3, [r7, #4] 80080b0: 681b ldr r3, [r3, #0] 80080b2: 4a52 ldr r2, [pc, #328] @ (80081fc ) 80080b4: 4293 cmp r3, r2 80080b6: d027 beq.n 8008108 80080b8: 687b ldr r3, [r7, #4] 80080ba: 681b ldr r3, [r3, #0] 80080bc: 4a50 ldr r2, [pc, #320] @ (8008200 ) 80080be: 4293 cmp r3, r2 80080c0: d022 beq.n 8008108 80080c2: 687b ldr r3, [r7, #4] 80080c4: 681b ldr r3, [r3, #0] 80080c6: 4a4f ldr r2, [pc, #316] @ (8008204 ) 80080c8: 4293 cmp r3, r2 80080ca: d01d beq.n 8008108 80080cc: 687b ldr r3, [r7, #4] 80080ce: 681b ldr r3, [r3, #0] 80080d0: 4a4d ldr r2, [pc, #308] @ (8008208 ) 80080d2: 4293 cmp r3, r2 80080d4: d018 beq.n 8008108 80080d6: 687b ldr r3, [r7, #4] 80080d8: 681b ldr r3, [r3, #0] 80080da: 4a4c ldr r2, [pc, #304] @ (800820c ) 80080dc: 4293 cmp r3, r2 80080de: d013 beq.n 8008108 80080e0: 687b ldr r3, [r7, #4] 80080e2: 681b ldr r3, [r3, #0] 80080e4: 4a4a ldr r2, [pc, #296] @ (8008210 ) 80080e6: 4293 cmp r3, r2 80080e8: d00e beq.n 8008108 80080ea: 687b ldr r3, [r7, #4] 80080ec: 681b ldr r3, [r3, #0] 80080ee: 4a49 ldr r2, [pc, #292] @ (8008214 ) 80080f0: 4293 cmp r3, r2 80080f2: d009 beq.n 8008108 80080f4: 687b ldr r3, [r7, #4] 80080f6: 681b ldr r3, [r3, #0] 80080f8: 4a47 ldr r2, [pc, #284] @ (8008218 ) 80080fa: 4293 cmp r3, r2 80080fc: d004 beq.n 8008108 80080fe: 687b ldr r3, [r7, #4] 8008100: 681b ldr r3, [r3, #0] 8008102: 4a46 ldr r2, [pc, #280] @ (800821c ) 8008104: 4293 cmp r3, r2 8008106: d101 bne.n 800810c 8008108: 2301 movs r3, #1 800810a: e000 b.n 800810e 800810c: 2300 movs r3, #0 800810e: 2b00 cmp r3, #0 8008110: f000 8086 beq.w 8008220 { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 8008114: 687b ldr r3, [r7, #4] 8008116: 2204 movs r2, #4 8008118: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800811c: 687b ldr r3, [r7, #4] 800811e: 681b ldr r3, [r3, #0] 8008120: 4a2f ldr r2, [pc, #188] @ (80081e0 ) 8008122: 4293 cmp r3, r2 8008124: d04a beq.n 80081bc 8008126: 687b ldr r3, [r7, #4] 8008128: 681b ldr r3, [r3, #0] 800812a: 4a2e ldr r2, [pc, #184] @ (80081e4 ) 800812c: 4293 cmp r3, r2 800812e: d045 beq.n 80081bc 8008130: 687b ldr r3, [r7, #4] 8008132: 681b ldr r3, [r3, #0] 8008134: 4a2c ldr r2, [pc, #176] @ (80081e8 ) 8008136: 4293 cmp r3, r2 8008138: d040 beq.n 80081bc 800813a: 687b ldr r3, [r7, #4] 800813c: 681b ldr r3, [r3, #0] 800813e: 4a2b ldr r2, [pc, #172] @ (80081ec ) 8008140: 4293 cmp r3, r2 8008142: d03b beq.n 80081bc 8008144: 687b ldr r3, [r7, #4] 8008146: 681b ldr r3, [r3, #0] 8008148: 4a29 ldr r2, [pc, #164] @ (80081f0 ) 800814a: 4293 cmp r3, r2 800814c: d036 beq.n 80081bc 800814e: 687b ldr r3, [r7, #4] 8008150: 681b ldr r3, [r3, #0] 8008152: 4a28 ldr r2, [pc, #160] @ (80081f4 ) 8008154: 4293 cmp r3, r2 8008156: d031 beq.n 80081bc 8008158: 687b ldr r3, [r7, #4] 800815a: 681b ldr r3, [r3, #0] 800815c: 4a26 ldr r2, [pc, #152] @ (80081f8 ) 800815e: 4293 cmp r3, r2 8008160: d02c beq.n 80081bc 8008162: 687b ldr r3, [r7, #4] 8008164: 681b ldr r3, [r3, #0] 8008166: 4a25 ldr r2, [pc, #148] @ (80081fc ) 8008168: 4293 cmp r3, r2 800816a: d027 beq.n 80081bc 800816c: 687b ldr r3, [r7, #4] 800816e: 681b ldr r3, [r3, #0] 8008170: 4a23 ldr r2, [pc, #140] @ (8008200 ) 8008172: 4293 cmp r3, r2 8008174: d022 beq.n 80081bc 8008176: 687b ldr r3, [r7, #4] 8008178: 681b ldr r3, [r3, #0] 800817a: 4a22 ldr r2, [pc, #136] @ (8008204 ) 800817c: 4293 cmp r3, r2 800817e: d01d beq.n 80081bc 8008180: 687b ldr r3, [r7, #4] 8008182: 681b ldr r3, [r3, #0] 8008184: 4a20 ldr r2, [pc, #128] @ (8008208 ) 8008186: 4293 cmp r3, r2 8008188: d018 beq.n 80081bc 800818a: 687b ldr r3, [r7, #4] 800818c: 681b ldr r3, [r3, #0] 800818e: 4a1f ldr r2, [pc, #124] @ (800820c ) 8008190: 4293 cmp r3, r2 8008192: d013 beq.n 80081bc 8008194: 687b ldr r3, [r7, #4] 8008196: 681b ldr r3, [r3, #0] 8008198: 4a1d ldr r2, [pc, #116] @ (8008210 ) 800819a: 4293 cmp r3, r2 800819c: d00e beq.n 80081bc 800819e: 687b ldr r3, [r7, #4] 80081a0: 681b ldr r3, [r3, #0] 80081a2: 4a1c ldr r2, [pc, #112] @ (8008214 ) 80081a4: 4293 cmp r3, r2 80081a6: d009 beq.n 80081bc 80081a8: 687b ldr r3, [r7, #4] 80081aa: 681b ldr r3, [r3, #0] 80081ac: 4a1a ldr r2, [pc, #104] @ (8008218 ) 80081ae: 4293 cmp r3, r2 80081b0: d004 beq.n 80081bc 80081b2: 687b ldr r3, [r7, #4] 80081b4: 681b ldr r3, [r3, #0] 80081b6: 4a19 ldr r2, [pc, #100] @ (800821c ) 80081b8: 4293 cmp r3, r2 80081ba: d108 bne.n 80081ce 80081bc: 687b ldr r3, [r7, #4] 80081be: 681b ldr r3, [r3, #0] 80081c0: 681a ldr r2, [r3, #0] 80081c2: 687b ldr r3, [r7, #4] 80081c4: 681b ldr r3, [r3, #0] 80081c6: f022 0201 bic.w r2, r2, #1 80081ca: 601a str r2, [r3, #0] 80081cc: e178 b.n 80084c0 80081ce: 687b ldr r3, [r7, #4] 80081d0: 681b ldr r3, [r3, #0] 80081d2: 681a ldr r2, [r3, #0] 80081d4: 687b ldr r3, [r7, #4] 80081d6: 681b ldr r3, [r3, #0] 80081d8: f022 0201 bic.w r2, r2, #1 80081dc: 601a str r2, [r3, #0] 80081de: e16f b.n 80084c0 80081e0: 40020010 .word 0x40020010 80081e4: 40020028 .word 0x40020028 80081e8: 40020040 .word 0x40020040 80081ec: 40020058 .word 0x40020058 80081f0: 40020070 .word 0x40020070 80081f4: 40020088 .word 0x40020088 80081f8: 400200a0 .word 0x400200a0 80081fc: 400200b8 .word 0x400200b8 8008200: 40020410 .word 0x40020410 8008204: 40020428 .word 0x40020428 8008208: 40020440 .word 0x40020440 800820c: 40020458 .word 0x40020458 8008210: 40020470 .word 0x40020470 8008214: 40020488 .word 0x40020488 8008218: 400204a0 .word 0x400204a0 800821c: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 8008220: 687b ldr r3, [r7, #4] 8008222: 681b ldr r3, [r3, #0] 8008224: 681a ldr r2, [r3, #0] 8008226: 687b ldr r3, [r7, #4] 8008228: 681b ldr r3, [r3, #0] 800822a: f022 020e bic.w r2, r2, #14 800822e: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8008230: 687b ldr r3, [r7, #4] 8008232: 681b ldr r3, [r3, #0] 8008234: 4a6c ldr r2, [pc, #432] @ (80083e8 ) 8008236: 4293 cmp r3, r2 8008238: d04a beq.n 80082d0 800823a: 687b ldr r3, [r7, #4] 800823c: 681b ldr r3, [r3, #0] 800823e: 4a6b ldr r2, [pc, #428] @ (80083ec ) 8008240: 4293 cmp r3, r2 8008242: d045 beq.n 80082d0 8008244: 687b ldr r3, [r7, #4] 8008246: 681b ldr r3, [r3, #0] 8008248: 4a69 ldr r2, [pc, #420] @ (80083f0 ) 800824a: 4293 cmp r3, r2 800824c: d040 beq.n 80082d0 800824e: 687b ldr r3, [r7, #4] 8008250: 681b ldr r3, [r3, #0] 8008252: 4a68 ldr r2, [pc, #416] @ (80083f4 ) 8008254: 4293 cmp r3, r2 8008256: d03b beq.n 80082d0 8008258: 687b ldr r3, [r7, #4] 800825a: 681b ldr r3, [r3, #0] 800825c: 4a66 ldr r2, [pc, #408] @ (80083f8 ) 800825e: 4293 cmp r3, r2 8008260: d036 beq.n 80082d0 8008262: 687b ldr r3, [r7, #4] 8008264: 681b ldr r3, [r3, #0] 8008266: 4a65 ldr r2, [pc, #404] @ (80083fc ) 8008268: 4293 cmp r3, r2 800826a: d031 beq.n 80082d0 800826c: 687b ldr r3, [r7, #4] 800826e: 681b ldr r3, [r3, #0] 8008270: 4a63 ldr r2, [pc, #396] @ (8008400 ) 8008272: 4293 cmp r3, r2 8008274: d02c beq.n 80082d0 8008276: 687b ldr r3, [r7, #4] 8008278: 681b ldr r3, [r3, #0] 800827a: 4a62 ldr r2, [pc, #392] @ (8008404 ) 800827c: 4293 cmp r3, r2 800827e: d027 beq.n 80082d0 8008280: 687b ldr r3, [r7, #4] 8008282: 681b ldr r3, [r3, #0] 8008284: 4a60 ldr r2, [pc, #384] @ (8008408 ) 8008286: 4293 cmp r3, r2 8008288: d022 beq.n 80082d0 800828a: 687b ldr r3, [r7, #4] 800828c: 681b ldr r3, [r3, #0] 800828e: 4a5f ldr r2, [pc, #380] @ (800840c ) 8008290: 4293 cmp r3, r2 8008292: d01d beq.n 80082d0 8008294: 687b ldr r3, [r7, #4] 8008296: 681b ldr r3, [r3, #0] 8008298: 4a5d ldr r2, [pc, #372] @ (8008410 ) 800829a: 4293 cmp r3, r2 800829c: d018 beq.n 80082d0 800829e: 687b ldr r3, [r7, #4] 80082a0: 681b ldr r3, [r3, #0] 80082a2: 4a5c ldr r2, [pc, #368] @ (8008414 ) 80082a4: 4293 cmp r3, r2 80082a6: d013 beq.n 80082d0 80082a8: 687b ldr r3, [r7, #4] 80082aa: 681b ldr r3, [r3, #0] 80082ac: 4a5a ldr r2, [pc, #360] @ (8008418 ) 80082ae: 4293 cmp r3, r2 80082b0: d00e beq.n 80082d0 80082b2: 687b ldr r3, [r7, #4] 80082b4: 681b ldr r3, [r3, #0] 80082b6: 4a59 ldr r2, [pc, #356] @ (800841c ) 80082b8: 4293 cmp r3, r2 80082ba: d009 beq.n 80082d0 80082bc: 687b ldr r3, [r7, #4] 80082be: 681b ldr r3, [r3, #0] 80082c0: 4a57 ldr r2, [pc, #348] @ (8008420 ) 80082c2: 4293 cmp r3, r2 80082c4: d004 beq.n 80082d0 80082c6: 687b ldr r3, [r7, #4] 80082c8: 681b ldr r3, [r3, #0] 80082ca: 4a56 ldr r2, [pc, #344] @ (8008424 ) 80082cc: 4293 cmp r3, r2 80082ce: d108 bne.n 80082e2 80082d0: 687b ldr r3, [r7, #4] 80082d2: 681b ldr r3, [r3, #0] 80082d4: 681a ldr r2, [r3, #0] 80082d6: 687b ldr r3, [r7, #4] 80082d8: 681b ldr r3, [r3, #0] 80082da: f022 0201 bic.w r2, r2, #1 80082de: 601a str r2, [r3, #0] 80082e0: e007 b.n 80082f2 80082e2: 687b ldr r3, [r7, #4] 80082e4: 681b ldr r3, [r3, #0] 80082e6: 681a ldr r2, [r3, #0] 80082e8: 687b ldr r3, [r7, #4] 80082ea: 681b ldr r3, [r3, #0] 80082ec: f022 0201 bic.w r2, r2, #1 80082f0: 601a str r2, [r3, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80082f2: 687b ldr r3, [r7, #4] 80082f4: 681b ldr r3, [r3, #0] 80082f6: 4a3c ldr r2, [pc, #240] @ (80083e8 ) 80082f8: 4293 cmp r3, r2 80082fa: d072 beq.n 80083e2 80082fc: 687b ldr r3, [r7, #4] 80082fe: 681b ldr r3, [r3, #0] 8008300: 4a3a ldr r2, [pc, #232] @ (80083ec ) 8008302: 4293 cmp r3, r2 8008304: d06d beq.n 80083e2 8008306: 687b ldr r3, [r7, #4] 8008308: 681b ldr r3, [r3, #0] 800830a: 4a39 ldr r2, [pc, #228] @ (80083f0 ) 800830c: 4293 cmp r3, r2 800830e: d068 beq.n 80083e2 8008310: 687b ldr r3, [r7, #4] 8008312: 681b ldr r3, [r3, #0] 8008314: 4a37 ldr r2, [pc, #220] @ (80083f4 ) 8008316: 4293 cmp r3, r2 8008318: d063 beq.n 80083e2 800831a: 687b ldr r3, [r7, #4] 800831c: 681b ldr r3, [r3, #0] 800831e: 4a36 ldr r2, [pc, #216] @ (80083f8 ) 8008320: 4293 cmp r3, r2 8008322: d05e beq.n 80083e2 8008324: 687b ldr r3, [r7, #4] 8008326: 681b ldr r3, [r3, #0] 8008328: 4a34 ldr r2, [pc, #208] @ (80083fc ) 800832a: 4293 cmp r3, r2 800832c: d059 beq.n 80083e2 800832e: 687b ldr r3, [r7, #4] 8008330: 681b ldr r3, [r3, #0] 8008332: 4a33 ldr r2, [pc, #204] @ (8008400 ) 8008334: 4293 cmp r3, r2 8008336: d054 beq.n 80083e2 8008338: 687b ldr r3, [r7, #4] 800833a: 681b ldr r3, [r3, #0] 800833c: 4a31 ldr r2, [pc, #196] @ (8008404 ) 800833e: 4293 cmp r3, r2 8008340: d04f beq.n 80083e2 8008342: 687b ldr r3, [r7, #4] 8008344: 681b ldr r3, [r3, #0] 8008346: 4a30 ldr r2, [pc, #192] @ (8008408 ) 8008348: 4293 cmp r3, r2 800834a: d04a beq.n 80083e2 800834c: 687b ldr r3, [r7, #4] 800834e: 681b ldr r3, [r3, #0] 8008350: 4a2e ldr r2, [pc, #184] @ (800840c ) 8008352: 4293 cmp r3, r2 8008354: d045 beq.n 80083e2 8008356: 687b ldr r3, [r7, #4] 8008358: 681b ldr r3, [r3, #0] 800835a: 4a2d ldr r2, [pc, #180] @ (8008410 ) 800835c: 4293 cmp r3, r2 800835e: d040 beq.n 80083e2 8008360: 687b ldr r3, [r7, #4] 8008362: 681b ldr r3, [r3, #0] 8008364: 4a2b ldr r2, [pc, #172] @ (8008414 ) 8008366: 4293 cmp r3, r2 8008368: d03b beq.n 80083e2 800836a: 687b ldr r3, [r7, #4] 800836c: 681b ldr r3, [r3, #0] 800836e: 4a2a ldr r2, [pc, #168] @ (8008418 ) 8008370: 4293 cmp r3, r2 8008372: d036 beq.n 80083e2 8008374: 687b ldr r3, [r7, #4] 8008376: 681b ldr r3, [r3, #0] 8008378: 4a28 ldr r2, [pc, #160] @ (800841c ) 800837a: 4293 cmp r3, r2 800837c: d031 beq.n 80083e2 800837e: 687b ldr r3, [r7, #4] 8008380: 681b ldr r3, [r3, #0] 8008382: 4a27 ldr r2, [pc, #156] @ (8008420 ) 8008384: 4293 cmp r3, r2 8008386: d02c beq.n 80083e2 8008388: 687b ldr r3, [r7, #4] 800838a: 681b ldr r3, [r3, #0] 800838c: 4a25 ldr r2, [pc, #148] @ (8008424 ) 800838e: 4293 cmp r3, r2 8008390: d027 beq.n 80083e2 8008392: 687b ldr r3, [r7, #4] 8008394: 681b ldr r3, [r3, #0] 8008396: 4a24 ldr r2, [pc, #144] @ (8008428 ) 8008398: 4293 cmp r3, r2 800839a: d022 beq.n 80083e2 800839c: 687b ldr r3, [r7, #4] 800839e: 681b ldr r3, [r3, #0] 80083a0: 4a22 ldr r2, [pc, #136] @ (800842c ) 80083a2: 4293 cmp r3, r2 80083a4: d01d beq.n 80083e2 80083a6: 687b ldr r3, [r7, #4] 80083a8: 681b ldr r3, [r3, #0] 80083aa: 4a21 ldr r2, [pc, #132] @ (8008430 ) 80083ac: 4293 cmp r3, r2 80083ae: d018 beq.n 80083e2 80083b0: 687b ldr r3, [r7, #4] 80083b2: 681b ldr r3, [r3, #0] 80083b4: 4a1f ldr r2, [pc, #124] @ (8008434 ) 80083b6: 4293 cmp r3, r2 80083b8: d013 beq.n 80083e2 80083ba: 687b ldr r3, [r7, #4] 80083bc: 681b ldr r3, [r3, #0] 80083be: 4a1e ldr r2, [pc, #120] @ (8008438 ) 80083c0: 4293 cmp r3, r2 80083c2: d00e beq.n 80083e2 80083c4: 687b ldr r3, [r7, #4] 80083c6: 681b ldr r3, [r3, #0] 80083c8: 4a1c ldr r2, [pc, #112] @ (800843c ) 80083ca: 4293 cmp r3, r2 80083cc: d009 beq.n 80083e2 80083ce: 687b ldr r3, [r7, #4] 80083d0: 681b ldr r3, [r3, #0] 80083d2: 4a1b ldr r2, [pc, #108] @ (8008440 ) 80083d4: 4293 cmp r3, r2 80083d6: d004 beq.n 80083e2 80083d8: 687b ldr r3, [r7, #4] 80083da: 681b ldr r3, [r3, #0] 80083dc: 4a19 ldr r2, [pc, #100] @ (8008444 ) 80083de: 4293 cmp r3, r2 80083e0: d132 bne.n 8008448 80083e2: 2301 movs r3, #1 80083e4: e031 b.n 800844a 80083e6: bf00 nop 80083e8: 40020010 .word 0x40020010 80083ec: 40020028 .word 0x40020028 80083f0: 40020040 .word 0x40020040 80083f4: 40020058 .word 0x40020058 80083f8: 40020070 .word 0x40020070 80083fc: 40020088 .word 0x40020088 8008400: 400200a0 .word 0x400200a0 8008404: 400200b8 .word 0x400200b8 8008408: 40020410 .word 0x40020410 800840c: 40020428 .word 0x40020428 8008410: 40020440 .word 0x40020440 8008414: 40020458 .word 0x40020458 8008418: 40020470 .word 0x40020470 800841c: 40020488 .word 0x40020488 8008420: 400204a0 .word 0x400204a0 8008424: 400204b8 .word 0x400204b8 8008428: 58025408 .word 0x58025408 800842c: 5802541c .word 0x5802541c 8008430: 58025430 .word 0x58025430 8008434: 58025444 .word 0x58025444 8008438: 58025458 .word 0x58025458 800843c: 5802546c .word 0x5802546c 8008440: 58025480 .word 0x58025480 8008444: 58025494 .word 0x58025494 8008448: 2300 movs r3, #0 800844a: 2b00 cmp r3, #0 800844c: d028 beq.n 80084a0 { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 800844e: 687b ldr r3, [r7, #4] 8008450: 6e1b ldr r3, [r3, #96] @ 0x60 8008452: 681a ldr r2, [r3, #0] 8008454: 687b ldr r3, [r7, #4] 8008456: 6e1b ldr r3, [r3, #96] @ 0x60 8008458: f422 7280 bic.w r2, r2, #256 @ 0x100 800845c: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 800845e: 687b ldr r3, [r7, #4] 8008460: 6d9b ldr r3, [r3, #88] @ 0x58 8008462: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8008464: 687b ldr r3, [r7, #4] 8008466: 6ddb ldr r3, [r3, #92] @ 0x5c 8008468: f003 031f and.w r3, r3, #31 800846c: 2201 movs r2, #1 800846e: 409a lsls r2, r3 8008470: 68fb ldr r3, [r7, #12] 8008472: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8008474: 687b ldr r3, [r7, #4] 8008476: 6e5b ldr r3, [r3, #100] @ 0x64 8008478: 687a ldr r2, [r7, #4] 800847a: 6e92 ldr r2, [r2, #104] @ 0x68 800847c: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 800847e: 687b ldr r3, [r7, #4] 8008480: 6edb ldr r3, [r3, #108] @ 0x6c 8008482: 2b00 cmp r3, #0 8008484: d00c beq.n 80084a0 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8008486: 687b ldr r3, [r7, #4] 8008488: 6edb ldr r3, [r3, #108] @ 0x6c 800848a: 681a ldr r2, [r3, #0] 800848c: 687b ldr r3, [r7, #4] 800848e: 6edb ldr r3, [r3, #108] @ 0x6c 8008490: f422 7280 bic.w r2, r2, #256 @ 0x100 8008494: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8008496: 687b ldr r3, [r7, #4] 8008498: 6f1b ldr r3, [r3, #112] @ 0x70 800849a: 687a ldr r2, [r7, #4] 800849c: 6f52 ldr r2, [r2, #116] @ 0x74 800849e: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80084a0: 687b ldr r3, [r7, #4] 80084a2: 2201 movs r2, #1 80084a4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80084a8: 687b ldr r3, [r7, #4] 80084aa: 2200 movs r2, #0 80084ac: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 80084b0: 687b ldr r3, [r7, #4] 80084b2: 6d1b ldr r3, [r3, #80] @ 0x50 80084b4: 2b00 cmp r3, #0 80084b6: d003 beq.n 80084c0 { hdma->XferAbortCallback(hdma); 80084b8: 687b ldr r3, [r7, #4] 80084ba: 6d1b ldr r3, [r3, #80] @ 0x50 80084bc: 6878 ldr r0, [r7, #4] 80084be: 4798 blx r3 } } } return HAL_OK; 80084c0: 2300 movs r3, #0 } 80084c2: 4618 mov r0, r3 80084c4: 3710 adds r7, #16 80084c6: 46bd mov sp, r7 80084c8: bd80 pop {r7, pc} 80084ca: bf00 nop 080084cc : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 80084cc: b580 push {r7, lr} 80084ce: b08a sub sp, #40 @ 0x28 80084d0: af00 add r7, sp, #0 80084d2: 6078 str r0, [r7, #4] uint32_t tmpisr_dma, tmpisr_bdma; uint32_t ccr_reg; __IO uint32_t count = 0U; 80084d4: 2300 movs r3, #0 80084d6: 60fb str r3, [r7, #12] uint32_t timeout = SystemCoreClock / 9600U; 80084d8: 4b67 ldr r3, [pc, #412] @ (8008678 ) 80084da: 681b ldr r3, [r3, #0] 80084dc: 4a67 ldr r2, [pc, #412] @ (800867c ) 80084de: fba2 2303 umull r2, r3, r2, r3 80084e2: 0a9b lsrs r3, r3, #10 80084e4: 627b str r3, [r7, #36] @ 0x24 /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 80084e6: 687b ldr r3, [r7, #4] 80084e8: 6d9b ldr r3, [r3, #88] @ 0x58 80084ea: 623b str r3, [r7, #32] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 80084ec: 687b ldr r3, [r7, #4] 80084ee: 6d9b ldr r3, [r3, #88] @ 0x58 80084f0: 61fb str r3, [r7, #28] tmpisr_dma = regs_dma->ISR; 80084f2: 6a3b ldr r3, [r7, #32] 80084f4: 681b ldr r3, [r3, #0] 80084f6: 61bb str r3, [r7, #24] tmpisr_bdma = regs_bdma->ISR; 80084f8: 69fb ldr r3, [r7, #28] 80084fa: 681b ldr r3, [r3, #0] 80084fc: 617b str r3, [r7, #20] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80084fe: 687b ldr r3, [r7, #4] 8008500: 681b ldr r3, [r3, #0] 8008502: 4a5f ldr r2, [pc, #380] @ (8008680 ) 8008504: 4293 cmp r3, r2 8008506: d04a beq.n 800859e 8008508: 687b ldr r3, [r7, #4] 800850a: 681b ldr r3, [r3, #0] 800850c: 4a5d ldr r2, [pc, #372] @ (8008684 ) 800850e: 4293 cmp r3, r2 8008510: d045 beq.n 800859e 8008512: 687b ldr r3, [r7, #4] 8008514: 681b ldr r3, [r3, #0] 8008516: 4a5c ldr r2, [pc, #368] @ (8008688 ) 8008518: 4293 cmp r3, r2 800851a: d040 beq.n 800859e 800851c: 687b ldr r3, [r7, #4] 800851e: 681b ldr r3, [r3, #0] 8008520: 4a5a ldr r2, [pc, #360] @ (800868c ) 8008522: 4293 cmp r3, r2 8008524: d03b beq.n 800859e 8008526: 687b ldr r3, [r7, #4] 8008528: 681b ldr r3, [r3, #0] 800852a: 4a59 ldr r2, [pc, #356] @ (8008690 ) 800852c: 4293 cmp r3, r2 800852e: d036 beq.n 800859e 8008530: 687b ldr r3, [r7, #4] 8008532: 681b ldr r3, [r3, #0] 8008534: 4a57 ldr r2, [pc, #348] @ (8008694 ) 8008536: 4293 cmp r3, r2 8008538: d031 beq.n 800859e 800853a: 687b ldr r3, [r7, #4] 800853c: 681b ldr r3, [r3, #0] 800853e: 4a56 ldr r2, [pc, #344] @ (8008698 ) 8008540: 4293 cmp r3, r2 8008542: d02c beq.n 800859e 8008544: 687b ldr r3, [r7, #4] 8008546: 681b ldr r3, [r3, #0] 8008548: 4a54 ldr r2, [pc, #336] @ (800869c ) 800854a: 4293 cmp r3, r2 800854c: d027 beq.n 800859e 800854e: 687b ldr r3, [r7, #4] 8008550: 681b ldr r3, [r3, #0] 8008552: 4a53 ldr r2, [pc, #332] @ (80086a0 ) 8008554: 4293 cmp r3, r2 8008556: d022 beq.n 800859e 8008558: 687b ldr r3, [r7, #4] 800855a: 681b ldr r3, [r3, #0] 800855c: 4a51 ldr r2, [pc, #324] @ (80086a4 ) 800855e: 4293 cmp r3, r2 8008560: d01d beq.n 800859e 8008562: 687b ldr r3, [r7, #4] 8008564: 681b ldr r3, [r3, #0] 8008566: 4a50 ldr r2, [pc, #320] @ (80086a8 ) 8008568: 4293 cmp r3, r2 800856a: d018 beq.n 800859e 800856c: 687b ldr r3, [r7, #4] 800856e: 681b ldr r3, [r3, #0] 8008570: 4a4e ldr r2, [pc, #312] @ (80086ac ) 8008572: 4293 cmp r3, r2 8008574: d013 beq.n 800859e 8008576: 687b ldr r3, [r7, #4] 8008578: 681b ldr r3, [r3, #0] 800857a: 4a4d ldr r2, [pc, #308] @ (80086b0 ) 800857c: 4293 cmp r3, r2 800857e: d00e beq.n 800859e 8008580: 687b ldr r3, [r7, #4] 8008582: 681b ldr r3, [r3, #0] 8008584: 4a4b ldr r2, [pc, #300] @ (80086b4 ) 8008586: 4293 cmp r3, r2 8008588: d009 beq.n 800859e 800858a: 687b ldr r3, [r7, #4] 800858c: 681b ldr r3, [r3, #0] 800858e: 4a4a ldr r2, [pc, #296] @ (80086b8 ) 8008590: 4293 cmp r3, r2 8008592: d004 beq.n 800859e 8008594: 687b ldr r3, [r7, #4] 8008596: 681b ldr r3, [r3, #0] 8008598: 4a48 ldr r2, [pc, #288] @ (80086bc ) 800859a: 4293 cmp r3, r2 800859c: d101 bne.n 80085a2 800859e: 2301 movs r3, #1 80085a0: e000 b.n 80085a4 80085a2: 2300 movs r3, #0 80085a4: 2b00 cmp r3, #0 80085a6: f000 842b beq.w 8008e00 { /* Transfer Error Interrupt management ***************************************/ if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 80085aa: 687b ldr r3, [r7, #4] 80085ac: 6ddb ldr r3, [r3, #92] @ 0x5c 80085ae: f003 031f and.w r3, r3, #31 80085b2: 2208 movs r2, #8 80085b4: 409a lsls r2, r3 80085b6: 69bb ldr r3, [r7, #24] 80085b8: 4013 ands r3, r2 80085ba: 2b00 cmp r3, #0 80085bc: f000 80a2 beq.w 8008704 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) 80085c0: 687b ldr r3, [r7, #4] 80085c2: 681b ldr r3, [r3, #0] 80085c4: 4a2e ldr r2, [pc, #184] @ (8008680 ) 80085c6: 4293 cmp r3, r2 80085c8: d04a beq.n 8008660 80085ca: 687b ldr r3, [r7, #4] 80085cc: 681b ldr r3, [r3, #0] 80085ce: 4a2d ldr r2, [pc, #180] @ (8008684 ) 80085d0: 4293 cmp r3, r2 80085d2: d045 beq.n 8008660 80085d4: 687b ldr r3, [r7, #4] 80085d6: 681b ldr r3, [r3, #0] 80085d8: 4a2b ldr r2, [pc, #172] @ (8008688 ) 80085da: 4293 cmp r3, r2 80085dc: d040 beq.n 8008660 80085de: 687b ldr r3, [r7, #4] 80085e0: 681b ldr r3, [r3, #0] 80085e2: 4a2a ldr r2, [pc, #168] @ (800868c ) 80085e4: 4293 cmp r3, r2 80085e6: d03b beq.n 8008660 80085e8: 687b ldr r3, [r7, #4] 80085ea: 681b ldr r3, [r3, #0] 80085ec: 4a28 ldr r2, [pc, #160] @ (8008690 ) 80085ee: 4293 cmp r3, r2 80085f0: d036 beq.n 8008660 80085f2: 687b ldr r3, [r7, #4] 80085f4: 681b ldr r3, [r3, #0] 80085f6: 4a27 ldr r2, [pc, #156] @ (8008694 ) 80085f8: 4293 cmp r3, r2 80085fa: d031 beq.n 8008660 80085fc: 687b ldr r3, [r7, #4] 80085fe: 681b ldr r3, [r3, #0] 8008600: 4a25 ldr r2, [pc, #148] @ (8008698 ) 8008602: 4293 cmp r3, r2 8008604: d02c beq.n 8008660 8008606: 687b ldr r3, [r7, #4] 8008608: 681b ldr r3, [r3, #0] 800860a: 4a24 ldr r2, [pc, #144] @ (800869c ) 800860c: 4293 cmp r3, r2 800860e: d027 beq.n 8008660 8008610: 687b ldr r3, [r7, #4] 8008612: 681b ldr r3, [r3, #0] 8008614: 4a22 ldr r2, [pc, #136] @ (80086a0 ) 8008616: 4293 cmp r3, r2 8008618: d022 beq.n 8008660 800861a: 687b ldr r3, [r7, #4] 800861c: 681b ldr r3, [r3, #0] 800861e: 4a21 ldr r2, [pc, #132] @ (80086a4 ) 8008620: 4293 cmp r3, r2 8008622: d01d beq.n 8008660 8008624: 687b ldr r3, [r7, #4] 8008626: 681b ldr r3, [r3, #0] 8008628: 4a1f ldr r2, [pc, #124] @ (80086a8 ) 800862a: 4293 cmp r3, r2 800862c: d018 beq.n 8008660 800862e: 687b ldr r3, [r7, #4] 8008630: 681b ldr r3, [r3, #0] 8008632: 4a1e ldr r2, [pc, #120] @ (80086ac ) 8008634: 4293 cmp r3, r2 8008636: d013 beq.n 8008660 8008638: 687b ldr r3, [r7, #4] 800863a: 681b ldr r3, [r3, #0] 800863c: 4a1c ldr r2, [pc, #112] @ (80086b0 ) 800863e: 4293 cmp r3, r2 8008640: d00e beq.n 8008660 8008642: 687b ldr r3, [r7, #4] 8008644: 681b ldr r3, [r3, #0] 8008646: 4a1b ldr r2, [pc, #108] @ (80086b4 ) 8008648: 4293 cmp r3, r2 800864a: d009 beq.n 8008660 800864c: 687b ldr r3, [r7, #4] 800864e: 681b ldr r3, [r3, #0] 8008650: 4a19 ldr r2, [pc, #100] @ (80086b8 ) 8008652: 4293 cmp r3, r2 8008654: d004 beq.n 8008660 8008656: 687b ldr r3, [r7, #4] 8008658: 681b ldr r3, [r3, #0] 800865a: 4a18 ldr r2, [pc, #96] @ (80086bc ) 800865c: 4293 cmp r3, r2 800865e: d12f bne.n 80086c0 8008660: 687b ldr r3, [r7, #4] 8008662: 681b ldr r3, [r3, #0] 8008664: 681b ldr r3, [r3, #0] 8008666: f003 0304 and.w r3, r3, #4 800866a: 2b00 cmp r3, #0 800866c: bf14 ite ne 800866e: 2301 movne r3, #1 8008670: 2300 moveq r3, #0 8008672: b2db uxtb r3, r3 8008674: e02e b.n 80086d4 8008676: bf00 nop 8008678: 24000034 .word 0x24000034 800867c: 1b4e81b5 .word 0x1b4e81b5 8008680: 40020010 .word 0x40020010 8008684: 40020028 .word 0x40020028 8008688: 40020040 .word 0x40020040 800868c: 40020058 .word 0x40020058 8008690: 40020070 .word 0x40020070 8008694: 40020088 .word 0x40020088 8008698: 400200a0 .word 0x400200a0 800869c: 400200b8 .word 0x400200b8 80086a0: 40020410 .word 0x40020410 80086a4: 40020428 .word 0x40020428 80086a8: 40020440 .word 0x40020440 80086ac: 40020458 .word 0x40020458 80086b0: 40020470 .word 0x40020470 80086b4: 40020488 .word 0x40020488 80086b8: 400204a0 .word 0x400204a0 80086bc: 400204b8 .word 0x400204b8 80086c0: 687b ldr r3, [r7, #4] 80086c2: 681b ldr r3, [r3, #0] 80086c4: 681b ldr r3, [r3, #0] 80086c6: f003 0308 and.w r3, r3, #8 80086ca: 2b00 cmp r3, #0 80086cc: bf14 ite ne 80086ce: 2301 movne r3, #1 80086d0: 2300 moveq r3, #0 80086d2: b2db uxtb r3, r3 80086d4: 2b00 cmp r3, #0 80086d6: d015 beq.n 8008704 { /* Disable the transfer error interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); 80086d8: 687b ldr r3, [r7, #4] 80086da: 681b ldr r3, [r3, #0] 80086dc: 681a ldr r2, [r3, #0] 80086de: 687b ldr r3, [r7, #4] 80086e0: 681b ldr r3, [r3, #0] 80086e2: f022 0204 bic.w r2, r2, #4 80086e6: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); 80086e8: 687b ldr r3, [r7, #4] 80086ea: 6ddb ldr r3, [r3, #92] @ 0x5c 80086ec: f003 031f and.w r3, r3, #31 80086f0: 2208 movs r2, #8 80086f2: 409a lsls r2, r3 80086f4: 6a3b ldr r3, [r7, #32] 80086f6: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 80086f8: 687b ldr r3, [r7, #4] 80086fa: 6d5b ldr r3, [r3, #84] @ 0x54 80086fc: f043 0201 orr.w r2, r3, #1 8008700: 687b ldr r3, [r7, #4] 8008702: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8008704: 687b ldr r3, [r7, #4] 8008706: 6ddb ldr r3, [r3, #92] @ 0x5c 8008708: f003 031f and.w r3, r3, #31 800870c: 69ba ldr r2, [r7, #24] 800870e: fa22 f303 lsr.w r3, r2, r3 8008712: f003 0301 and.w r3, r3, #1 8008716: 2b00 cmp r3, #0 8008718: d06e beq.n 80087f8 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) 800871a: 687b ldr r3, [r7, #4] 800871c: 681b ldr r3, [r3, #0] 800871e: 4a69 ldr r2, [pc, #420] @ (80088c4 ) 8008720: 4293 cmp r3, r2 8008722: d04a beq.n 80087ba 8008724: 687b ldr r3, [r7, #4] 8008726: 681b ldr r3, [r3, #0] 8008728: 4a67 ldr r2, [pc, #412] @ (80088c8 ) 800872a: 4293 cmp r3, r2 800872c: d045 beq.n 80087ba 800872e: 687b ldr r3, [r7, #4] 8008730: 681b ldr r3, [r3, #0] 8008732: 4a66 ldr r2, [pc, #408] @ (80088cc ) 8008734: 4293 cmp r3, r2 8008736: d040 beq.n 80087ba 8008738: 687b ldr r3, [r7, #4] 800873a: 681b ldr r3, [r3, #0] 800873c: 4a64 ldr r2, [pc, #400] @ (80088d0 ) 800873e: 4293 cmp r3, r2 8008740: d03b beq.n 80087ba 8008742: 687b ldr r3, [r7, #4] 8008744: 681b ldr r3, [r3, #0] 8008746: 4a63 ldr r2, [pc, #396] @ (80088d4 ) 8008748: 4293 cmp r3, r2 800874a: d036 beq.n 80087ba 800874c: 687b ldr r3, [r7, #4] 800874e: 681b ldr r3, [r3, #0] 8008750: 4a61 ldr r2, [pc, #388] @ (80088d8 ) 8008752: 4293 cmp r3, r2 8008754: d031 beq.n 80087ba 8008756: 687b ldr r3, [r7, #4] 8008758: 681b ldr r3, [r3, #0] 800875a: 4a60 ldr r2, [pc, #384] @ (80088dc ) 800875c: 4293 cmp r3, r2 800875e: d02c beq.n 80087ba 8008760: 687b ldr r3, [r7, #4] 8008762: 681b ldr r3, [r3, #0] 8008764: 4a5e ldr r2, [pc, #376] @ (80088e0 ) 8008766: 4293 cmp r3, r2 8008768: d027 beq.n 80087ba 800876a: 687b ldr r3, [r7, #4] 800876c: 681b ldr r3, [r3, #0] 800876e: 4a5d ldr r2, [pc, #372] @ (80088e4 ) 8008770: 4293 cmp r3, r2 8008772: d022 beq.n 80087ba 8008774: 687b ldr r3, [r7, #4] 8008776: 681b ldr r3, [r3, #0] 8008778: 4a5b ldr r2, [pc, #364] @ (80088e8 ) 800877a: 4293 cmp r3, r2 800877c: d01d beq.n 80087ba 800877e: 687b ldr r3, [r7, #4] 8008780: 681b ldr r3, [r3, #0] 8008782: 4a5a ldr r2, [pc, #360] @ (80088ec ) 8008784: 4293 cmp r3, r2 8008786: d018 beq.n 80087ba 8008788: 687b ldr r3, [r7, #4] 800878a: 681b ldr r3, [r3, #0] 800878c: 4a58 ldr r2, [pc, #352] @ (80088f0 ) 800878e: 4293 cmp r3, r2 8008790: d013 beq.n 80087ba 8008792: 687b ldr r3, [r7, #4] 8008794: 681b ldr r3, [r3, #0] 8008796: 4a57 ldr r2, [pc, #348] @ (80088f4 ) 8008798: 4293 cmp r3, r2 800879a: d00e beq.n 80087ba 800879c: 687b ldr r3, [r7, #4] 800879e: 681b ldr r3, [r3, #0] 80087a0: 4a55 ldr r2, [pc, #340] @ (80088f8 ) 80087a2: 4293 cmp r3, r2 80087a4: d009 beq.n 80087ba 80087a6: 687b ldr r3, [r7, #4] 80087a8: 681b ldr r3, [r3, #0] 80087aa: 4a54 ldr r2, [pc, #336] @ (80088fc ) 80087ac: 4293 cmp r3, r2 80087ae: d004 beq.n 80087ba 80087b0: 687b ldr r3, [r7, #4] 80087b2: 681b ldr r3, [r3, #0] 80087b4: 4a52 ldr r2, [pc, #328] @ (8008900 ) 80087b6: 4293 cmp r3, r2 80087b8: d10a bne.n 80087d0 80087ba: 687b ldr r3, [r7, #4] 80087bc: 681b ldr r3, [r3, #0] 80087be: 695b ldr r3, [r3, #20] 80087c0: f003 0380 and.w r3, r3, #128 @ 0x80 80087c4: 2b00 cmp r3, #0 80087c6: bf14 ite ne 80087c8: 2301 movne r3, #1 80087ca: 2300 moveq r3, #0 80087cc: b2db uxtb r3, r3 80087ce: e003 b.n 80087d8 80087d0: 687b ldr r3, [r7, #4] 80087d2: 681b ldr r3, [r3, #0] 80087d4: 681b ldr r3, [r3, #0] 80087d6: 2300 movs r3, #0 80087d8: 2b00 cmp r3, #0 80087da: d00d beq.n 80087f8 { /* Clear the FIFO error flag */ regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); 80087dc: 687b ldr r3, [r7, #4] 80087de: 6ddb ldr r3, [r3, #92] @ 0x5c 80087e0: f003 031f and.w r3, r3, #31 80087e4: 2201 movs r2, #1 80087e6: 409a lsls r2, r3 80087e8: 6a3b ldr r3, [r7, #32] 80087ea: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 80087ec: 687b ldr r3, [r7, #4] 80087ee: 6d5b ldr r3, [r3, #84] @ 0x54 80087f0: f043 0202 orr.w r2, r3, #2 80087f4: 687b ldr r3, [r7, #4] 80087f6: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 80087f8: 687b ldr r3, [r7, #4] 80087fa: 6ddb ldr r3, [r3, #92] @ 0x5c 80087fc: f003 031f and.w r3, r3, #31 8008800: 2204 movs r2, #4 8008802: 409a lsls r2, r3 8008804: 69bb ldr r3, [r7, #24] 8008806: 4013 ands r3, r2 8008808: 2b00 cmp r3, #0 800880a: f000 808f beq.w 800892c { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) 800880e: 687b ldr r3, [r7, #4] 8008810: 681b ldr r3, [r3, #0] 8008812: 4a2c ldr r2, [pc, #176] @ (80088c4 ) 8008814: 4293 cmp r3, r2 8008816: d04a beq.n 80088ae 8008818: 687b ldr r3, [r7, #4] 800881a: 681b ldr r3, [r3, #0] 800881c: 4a2a ldr r2, [pc, #168] @ (80088c8 ) 800881e: 4293 cmp r3, r2 8008820: d045 beq.n 80088ae 8008822: 687b ldr r3, [r7, #4] 8008824: 681b ldr r3, [r3, #0] 8008826: 4a29 ldr r2, [pc, #164] @ (80088cc ) 8008828: 4293 cmp r3, r2 800882a: d040 beq.n 80088ae 800882c: 687b ldr r3, [r7, #4] 800882e: 681b ldr r3, [r3, #0] 8008830: 4a27 ldr r2, [pc, #156] @ (80088d0 ) 8008832: 4293 cmp r3, r2 8008834: d03b beq.n 80088ae 8008836: 687b ldr r3, [r7, #4] 8008838: 681b ldr r3, [r3, #0] 800883a: 4a26 ldr r2, [pc, #152] @ (80088d4 ) 800883c: 4293 cmp r3, r2 800883e: d036 beq.n 80088ae 8008840: 687b ldr r3, [r7, #4] 8008842: 681b ldr r3, [r3, #0] 8008844: 4a24 ldr r2, [pc, #144] @ (80088d8 ) 8008846: 4293 cmp r3, r2 8008848: d031 beq.n 80088ae 800884a: 687b ldr r3, [r7, #4] 800884c: 681b ldr r3, [r3, #0] 800884e: 4a23 ldr r2, [pc, #140] @ (80088dc ) 8008850: 4293 cmp r3, r2 8008852: d02c beq.n 80088ae 8008854: 687b ldr r3, [r7, #4] 8008856: 681b ldr r3, [r3, #0] 8008858: 4a21 ldr r2, [pc, #132] @ (80088e0 ) 800885a: 4293 cmp r3, r2 800885c: d027 beq.n 80088ae 800885e: 687b ldr r3, [r7, #4] 8008860: 681b ldr r3, [r3, #0] 8008862: 4a20 ldr r2, [pc, #128] @ (80088e4 ) 8008864: 4293 cmp r3, r2 8008866: d022 beq.n 80088ae 8008868: 687b ldr r3, [r7, #4] 800886a: 681b ldr r3, [r3, #0] 800886c: 4a1e ldr r2, [pc, #120] @ (80088e8 ) 800886e: 4293 cmp r3, r2 8008870: d01d beq.n 80088ae 8008872: 687b ldr r3, [r7, #4] 8008874: 681b ldr r3, [r3, #0] 8008876: 4a1d ldr r2, [pc, #116] @ (80088ec ) 8008878: 4293 cmp r3, r2 800887a: d018 beq.n 80088ae 800887c: 687b ldr r3, [r7, #4] 800887e: 681b ldr r3, [r3, #0] 8008880: 4a1b ldr r2, [pc, #108] @ (80088f0 ) 8008882: 4293 cmp r3, r2 8008884: d013 beq.n 80088ae 8008886: 687b ldr r3, [r7, #4] 8008888: 681b ldr r3, [r3, #0] 800888a: 4a1a ldr r2, [pc, #104] @ (80088f4 ) 800888c: 4293 cmp r3, r2 800888e: d00e beq.n 80088ae 8008890: 687b ldr r3, [r7, #4] 8008892: 681b ldr r3, [r3, #0] 8008894: 4a18 ldr r2, [pc, #96] @ (80088f8 ) 8008896: 4293 cmp r3, r2 8008898: d009 beq.n 80088ae 800889a: 687b ldr r3, [r7, #4] 800889c: 681b ldr r3, [r3, #0] 800889e: 4a17 ldr r2, [pc, #92] @ (80088fc ) 80088a0: 4293 cmp r3, r2 80088a2: d004 beq.n 80088ae 80088a4: 687b ldr r3, [r7, #4] 80088a6: 681b ldr r3, [r3, #0] 80088a8: 4a15 ldr r2, [pc, #84] @ (8008900 ) 80088aa: 4293 cmp r3, r2 80088ac: d12a bne.n 8008904 80088ae: 687b ldr r3, [r7, #4] 80088b0: 681b ldr r3, [r3, #0] 80088b2: 681b ldr r3, [r3, #0] 80088b4: f003 0302 and.w r3, r3, #2 80088b8: 2b00 cmp r3, #0 80088ba: bf14 ite ne 80088bc: 2301 movne r3, #1 80088be: 2300 moveq r3, #0 80088c0: b2db uxtb r3, r3 80088c2: e023 b.n 800890c 80088c4: 40020010 .word 0x40020010 80088c8: 40020028 .word 0x40020028 80088cc: 40020040 .word 0x40020040 80088d0: 40020058 .word 0x40020058 80088d4: 40020070 .word 0x40020070 80088d8: 40020088 .word 0x40020088 80088dc: 400200a0 .word 0x400200a0 80088e0: 400200b8 .word 0x400200b8 80088e4: 40020410 .word 0x40020410 80088e8: 40020428 .word 0x40020428 80088ec: 40020440 .word 0x40020440 80088f0: 40020458 .word 0x40020458 80088f4: 40020470 .word 0x40020470 80088f8: 40020488 .word 0x40020488 80088fc: 400204a0 .word 0x400204a0 8008900: 400204b8 .word 0x400204b8 8008904: 687b ldr r3, [r7, #4] 8008906: 681b ldr r3, [r3, #0] 8008908: 681b ldr r3, [r3, #0] 800890a: 2300 movs r3, #0 800890c: 2b00 cmp r3, #0 800890e: d00d beq.n 800892c { /* Clear the direct mode error flag */ regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); 8008910: 687b ldr r3, [r7, #4] 8008912: 6ddb ldr r3, [r3, #92] @ 0x5c 8008914: f003 031f and.w r3, r3, #31 8008918: 2204 movs r2, #4 800891a: 409a lsls r2, r3 800891c: 6a3b ldr r3, [r7, #32] 800891e: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 8008920: 687b ldr r3, [r7, #4] 8008922: 6d5b ldr r3, [r3, #84] @ 0x54 8008924: f043 0204 orr.w r2, r3, #4 8008928: 687b ldr r3, [r7, #4] 800892a: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 800892c: 687b ldr r3, [r7, #4] 800892e: 6ddb ldr r3, [r3, #92] @ 0x5c 8008930: f003 031f and.w r3, r3, #31 8008934: 2210 movs r2, #16 8008936: 409a lsls r2, r3 8008938: 69bb ldr r3, [r7, #24] 800893a: 4013 ands r3, r2 800893c: 2b00 cmp r3, #0 800893e: f000 80a6 beq.w 8008a8e { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) 8008942: 687b ldr r3, [r7, #4] 8008944: 681b ldr r3, [r3, #0] 8008946: 4a85 ldr r2, [pc, #532] @ (8008b5c ) 8008948: 4293 cmp r3, r2 800894a: d04a beq.n 80089e2 800894c: 687b ldr r3, [r7, #4] 800894e: 681b ldr r3, [r3, #0] 8008950: 4a83 ldr r2, [pc, #524] @ (8008b60 ) 8008952: 4293 cmp r3, r2 8008954: d045 beq.n 80089e2 8008956: 687b ldr r3, [r7, #4] 8008958: 681b ldr r3, [r3, #0] 800895a: 4a82 ldr r2, [pc, #520] @ (8008b64 ) 800895c: 4293 cmp r3, r2 800895e: d040 beq.n 80089e2 8008960: 687b ldr r3, [r7, #4] 8008962: 681b ldr r3, [r3, #0] 8008964: 4a80 ldr r2, [pc, #512] @ (8008b68 ) 8008966: 4293 cmp r3, r2 8008968: d03b beq.n 80089e2 800896a: 687b ldr r3, [r7, #4] 800896c: 681b ldr r3, [r3, #0] 800896e: 4a7f ldr r2, [pc, #508] @ (8008b6c ) 8008970: 4293 cmp r3, r2 8008972: d036 beq.n 80089e2 8008974: 687b ldr r3, [r7, #4] 8008976: 681b ldr r3, [r3, #0] 8008978: 4a7d ldr r2, [pc, #500] @ (8008b70 ) 800897a: 4293 cmp r3, r2 800897c: d031 beq.n 80089e2 800897e: 687b ldr r3, [r7, #4] 8008980: 681b ldr r3, [r3, #0] 8008982: 4a7c ldr r2, [pc, #496] @ (8008b74 ) 8008984: 4293 cmp r3, r2 8008986: d02c beq.n 80089e2 8008988: 687b ldr r3, [r7, #4] 800898a: 681b ldr r3, [r3, #0] 800898c: 4a7a ldr r2, [pc, #488] @ (8008b78 ) 800898e: 4293 cmp r3, r2 8008990: d027 beq.n 80089e2 8008992: 687b ldr r3, [r7, #4] 8008994: 681b ldr r3, [r3, #0] 8008996: 4a79 ldr r2, [pc, #484] @ (8008b7c ) 8008998: 4293 cmp r3, r2 800899a: d022 beq.n 80089e2 800899c: 687b ldr r3, [r7, #4] 800899e: 681b ldr r3, [r3, #0] 80089a0: 4a77 ldr r2, [pc, #476] @ (8008b80 ) 80089a2: 4293 cmp r3, r2 80089a4: d01d beq.n 80089e2 80089a6: 687b ldr r3, [r7, #4] 80089a8: 681b ldr r3, [r3, #0] 80089aa: 4a76 ldr r2, [pc, #472] @ (8008b84 ) 80089ac: 4293 cmp r3, r2 80089ae: d018 beq.n 80089e2 80089b0: 687b ldr r3, [r7, #4] 80089b2: 681b ldr r3, [r3, #0] 80089b4: 4a74 ldr r2, [pc, #464] @ (8008b88 ) 80089b6: 4293 cmp r3, r2 80089b8: d013 beq.n 80089e2 80089ba: 687b ldr r3, [r7, #4] 80089bc: 681b ldr r3, [r3, #0] 80089be: 4a73 ldr r2, [pc, #460] @ (8008b8c ) 80089c0: 4293 cmp r3, r2 80089c2: d00e beq.n 80089e2 80089c4: 687b ldr r3, [r7, #4] 80089c6: 681b ldr r3, [r3, #0] 80089c8: 4a71 ldr r2, [pc, #452] @ (8008b90 ) 80089ca: 4293 cmp r3, r2 80089cc: d009 beq.n 80089e2 80089ce: 687b ldr r3, [r7, #4] 80089d0: 681b ldr r3, [r3, #0] 80089d2: 4a70 ldr r2, [pc, #448] @ (8008b94 ) 80089d4: 4293 cmp r3, r2 80089d6: d004 beq.n 80089e2 80089d8: 687b ldr r3, [r7, #4] 80089da: 681b ldr r3, [r3, #0] 80089dc: 4a6e ldr r2, [pc, #440] @ (8008b98 ) 80089de: 4293 cmp r3, r2 80089e0: d10a bne.n 80089f8 80089e2: 687b ldr r3, [r7, #4] 80089e4: 681b ldr r3, [r3, #0] 80089e6: 681b ldr r3, [r3, #0] 80089e8: f003 0308 and.w r3, r3, #8 80089ec: 2b00 cmp r3, #0 80089ee: bf14 ite ne 80089f0: 2301 movne r3, #1 80089f2: 2300 moveq r3, #0 80089f4: b2db uxtb r3, r3 80089f6: e009 b.n 8008a0c 80089f8: 687b ldr r3, [r7, #4] 80089fa: 681b ldr r3, [r3, #0] 80089fc: 681b ldr r3, [r3, #0] 80089fe: f003 0304 and.w r3, r3, #4 8008a02: 2b00 cmp r3, #0 8008a04: bf14 ite ne 8008a06: 2301 movne r3, #1 8008a08: 2300 moveq r3, #0 8008a0a: b2db uxtb r3, r3 8008a0c: 2b00 cmp r3, #0 8008a0e: d03e beq.n 8008a8e { /* Clear the half transfer complete flag */ regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); 8008a10: 687b ldr r3, [r7, #4] 8008a12: 6ddb ldr r3, [r3, #92] @ 0x5c 8008a14: f003 031f and.w r3, r3, #31 8008a18: 2210 movs r2, #16 8008a1a: 409a lsls r2, r3 8008a1c: 6a3b ldr r3, [r7, #32] 8008a1e: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 8008a20: 687b ldr r3, [r7, #4] 8008a22: 681b ldr r3, [r3, #0] 8008a24: 681b ldr r3, [r3, #0] 8008a26: f403 2380 and.w r3, r3, #262144 @ 0x40000 8008a2a: 2b00 cmp r3, #0 8008a2c: d018 beq.n 8008a60 { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 8008a2e: 687b ldr r3, [r7, #4] 8008a30: 681b ldr r3, [r3, #0] 8008a32: 681b ldr r3, [r3, #0] 8008a34: f403 2300 and.w r3, r3, #524288 @ 0x80000 8008a38: 2b00 cmp r3, #0 8008a3a: d108 bne.n 8008a4e { if(hdma->XferHalfCpltCallback != NULL) 8008a3c: 687b ldr r3, [r7, #4] 8008a3e: 6c1b ldr r3, [r3, #64] @ 0x40 8008a40: 2b00 cmp r3, #0 8008a42: d024 beq.n 8008a8e { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8008a44: 687b ldr r3, [r7, #4] 8008a46: 6c1b ldr r3, [r3, #64] @ 0x40 8008a48: 6878 ldr r0, [r7, #4] 8008a4a: 4798 blx r3 8008a4c: e01f b.n 8008a8e } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 8008a4e: 687b ldr r3, [r7, #4] 8008a50: 6c9b ldr r3, [r3, #72] @ 0x48 8008a52: 2b00 cmp r3, #0 8008a54: d01b beq.n 8008a8e { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 8008a56: 687b ldr r3, [r7, #4] 8008a58: 6c9b ldr r3, [r3, #72] @ 0x48 8008a5a: 6878 ldr r0, [r7, #4] 8008a5c: 4798 blx r3 8008a5e: e016 b.n 8008a8e } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 8008a60: 687b ldr r3, [r7, #4] 8008a62: 681b ldr r3, [r3, #0] 8008a64: 681b ldr r3, [r3, #0] 8008a66: f403 7380 and.w r3, r3, #256 @ 0x100 8008a6a: 2b00 cmp r3, #0 8008a6c: d107 bne.n 8008a7e { /* Disable the half transfer interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 8008a6e: 687b ldr r3, [r7, #4] 8008a70: 681b ldr r3, [r3, #0] 8008a72: 681a ldr r2, [r3, #0] 8008a74: 687b ldr r3, [r7, #4] 8008a76: 681b ldr r3, [r3, #0] 8008a78: f022 0208 bic.w r2, r2, #8 8008a7c: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 8008a7e: 687b ldr r3, [r7, #4] 8008a80: 6c1b ldr r3, [r3, #64] @ 0x40 8008a82: 2b00 cmp r3, #0 8008a84: d003 beq.n 8008a8e { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8008a86: 687b ldr r3, [r7, #4] 8008a88: 6c1b ldr r3, [r3, #64] @ 0x40 8008a8a: 6878 ldr r0, [r7, #4] 8008a8c: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8008a8e: 687b ldr r3, [r7, #4] 8008a90: 6ddb ldr r3, [r3, #92] @ 0x5c 8008a92: f003 031f and.w r3, r3, #31 8008a96: 2220 movs r2, #32 8008a98: 409a lsls r2, r3 8008a9a: 69bb ldr r3, [r7, #24] 8008a9c: 4013 ands r3, r2 8008a9e: 2b00 cmp r3, #0 8008aa0: f000 8110 beq.w 8008cc4 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) 8008aa4: 687b ldr r3, [r7, #4] 8008aa6: 681b ldr r3, [r3, #0] 8008aa8: 4a2c ldr r2, [pc, #176] @ (8008b5c ) 8008aaa: 4293 cmp r3, r2 8008aac: d04a beq.n 8008b44 8008aae: 687b ldr r3, [r7, #4] 8008ab0: 681b ldr r3, [r3, #0] 8008ab2: 4a2b ldr r2, [pc, #172] @ (8008b60 ) 8008ab4: 4293 cmp r3, r2 8008ab6: d045 beq.n 8008b44 8008ab8: 687b ldr r3, [r7, #4] 8008aba: 681b ldr r3, [r3, #0] 8008abc: 4a29 ldr r2, [pc, #164] @ (8008b64 ) 8008abe: 4293 cmp r3, r2 8008ac0: d040 beq.n 8008b44 8008ac2: 687b ldr r3, [r7, #4] 8008ac4: 681b ldr r3, [r3, #0] 8008ac6: 4a28 ldr r2, [pc, #160] @ (8008b68 ) 8008ac8: 4293 cmp r3, r2 8008aca: d03b beq.n 8008b44 8008acc: 687b ldr r3, [r7, #4] 8008ace: 681b ldr r3, [r3, #0] 8008ad0: 4a26 ldr r2, [pc, #152] @ (8008b6c ) 8008ad2: 4293 cmp r3, r2 8008ad4: d036 beq.n 8008b44 8008ad6: 687b ldr r3, [r7, #4] 8008ad8: 681b ldr r3, [r3, #0] 8008ada: 4a25 ldr r2, [pc, #148] @ (8008b70 ) 8008adc: 4293 cmp r3, r2 8008ade: d031 beq.n 8008b44 8008ae0: 687b ldr r3, [r7, #4] 8008ae2: 681b ldr r3, [r3, #0] 8008ae4: 4a23 ldr r2, [pc, #140] @ (8008b74 ) 8008ae6: 4293 cmp r3, r2 8008ae8: d02c beq.n 8008b44 8008aea: 687b ldr r3, [r7, #4] 8008aec: 681b ldr r3, [r3, #0] 8008aee: 4a22 ldr r2, [pc, #136] @ (8008b78 ) 8008af0: 4293 cmp r3, r2 8008af2: d027 beq.n 8008b44 8008af4: 687b ldr r3, [r7, #4] 8008af6: 681b ldr r3, [r3, #0] 8008af8: 4a20 ldr r2, [pc, #128] @ (8008b7c ) 8008afa: 4293 cmp r3, r2 8008afc: d022 beq.n 8008b44 8008afe: 687b ldr r3, [r7, #4] 8008b00: 681b ldr r3, [r3, #0] 8008b02: 4a1f ldr r2, [pc, #124] @ (8008b80 ) 8008b04: 4293 cmp r3, r2 8008b06: d01d beq.n 8008b44 8008b08: 687b ldr r3, [r7, #4] 8008b0a: 681b ldr r3, [r3, #0] 8008b0c: 4a1d ldr r2, [pc, #116] @ (8008b84 ) 8008b0e: 4293 cmp r3, r2 8008b10: d018 beq.n 8008b44 8008b12: 687b ldr r3, [r7, #4] 8008b14: 681b ldr r3, [r3, #0] 8008b16: 4a1c ldr r2, [pc, #112] @ (8008b88 ) 8008b18: 4293 cmp r3, r2 8008b1a: d013 beq.n 8008b44 8008b1c: 687b ldr r3, [r7, #4] 8008b1e: 681b ldr r3, [r3, #0] 8008b20: 4a1a ldr r2, [pc, #104] @ (8008b8c ) 8008b22: 4293 cmp r3, r2 8008b24: d00e beq.n 8008b44 8008b26: 687b ldr r3, [r7, #4] 8008b28: 681b ldr r3, [r3, #0] 8008b2a: 4a19 ldr r2, [pc, #100] @ (8008b90 ) 8008b2c: 4293 cmp r3, r2 8008b2e: d009 beq.n 8008b44 8008b30: 687b ldr r3, [r7, #4] 8008b32: 681b ldr r3, [r3, #0] 8008b34: 4a17 ldr r2, [pc, #92] @ (8008b94 ) 8008b36: 4293 cmp r3, r2 8008b38: d004 beq.n 8008b44 8008b3a: 687b ldr r3, [r7, #4] 8008b3c: 681b ldr r3, [r3, #0] 8008b3e: 4a16 ldr r2, [pc, #88] @ (8008b98 ) 8008b40: 4293 cmp r3, r2 8008b42: d12b bne.n 8008b9c 8008b44: 687b ldr r3, [r7, #4] 8008b46: 681b ldr r3, [r3, #0] 8008b48: 681b ldr r3, [r3, #0] 8008b4a: f003 0310 and.w r3, r3, #16 8008b4e: 2b00 cmp r3, #0 8008b50: bf14 ite ne 8008b52: 2301 movne r3, #1 8008b54: 2300 moveq r3, #0 8008b56: b2db uxtb r3, r3 8008b58: e02a b.n 8008bb0 8008b5a: bf00 nop 8008b5c: 40020010 .word 0x40020010 8008b60: 40020028 .word 0x40020028 8008b64: 40020040 .word 0x40020040 8008b68: 40020058 .word 0x40020058 8008b6c: 40020070 .word 0x40020070 8008b70: 40020088 .word 0x40020088 8008b74: 400200a0 .word 0x400200a0 8008b78: 400200b8 .word 0x400200b8 8008b7c: 40020410 .word 0x40020410 8008b80: 40020428 .word 0x40020428 8008b84: 40020440 .word 0x40020440 8008b88: 40020458 .word 0x40020458 8008b8c: 40020470 .word 0x40020470 8008b90: 40020488 .word 0x40020488 8008b94: 400204a0 .word 0x400204a0 8008b98: 400204b8 .word 0x400204b8 8008b9c: 687b ldr r3, [r7, #4] 8008b9e: 681b ldr r3, [r3, #0] 8008ba0: 681b ldr r3, [r3, #0] 8008ba2: f003 0302 and.w r3, r3, #2 8008ba6: 2b00 cmp r3, #0 8008ba8: bf14 ite ne 8008baa: 2301 movne r3, #1 8008bac: 2300 moveq r3, #0 8008bae: b2db uxtb r3, r3 8008bb0: 2b00 cmp r3, #0 8008bb2: f000 8087 beq.w 8008cc4 { /* Clear the transfer complete flag */ regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); 8008bb6: 687b ldr r3, [r7, #4] 8008bb8: 6ddb ldr r3, [r3, #92] @ 0x5c 8008bba: f003 031f and.w r3, r3, #31 8008bbe: 2220 movs r2, #32 8008bc0: 409a lsls r2, r3 8008bc2: 6a3b ldr r3, [r7, #32] 8008bc4: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 8008bc6: 687b ldr r3, [r7, #4] 8008bc8: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8008bcc: b2db uxtb r3, r3 8008bce: 2b04 cmp r3, #4 8008bd0: d139 bne.n 8008c46 { /* Disable all the transfer interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 8008bd2: 687b ldr r3, [r7, #4] 8008bd4: 681b ldr r3, [r3, #0] 8008bd6: 681a ldr r2, [r3, #0] 8008bd8: 687b ldr r3, [r7, #4] 8008bda: 681b ldr r3, [r3, #0] 8008bdc: f022 0216 bic.w r2, r2, #22 8008be0: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 8008be2: 687b ldr r3, [r7, #4] 8008be4: 681b ldr r3, [r3, #0] 8008be6: 695a ldr r2, [r3, #20] 8008be8: 687b ldr r3, [r7, #4] 8008bea: 681b ldr r3, [r3, #0] 8008bec: f022 0280 bic.w r2, r2, #128 @ 0x80 8008bf0: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 8008bf2: 687b ldr r3, [r7, #4] 8008bf4: 6c1b ldr r3, [r3, #64] @ 0x40 8008bf6: 2b00 cmp r3, #0 8008bf8: d103 bne.n 8008c02 8008bfa: 687b ldr r3, [r7, #4] 8008bfc: 6c9b ldr r3, [r3, #72] @ 0x48 8008bfe: 2b00 cmp r3, #0 8008c00: d007 beq.n 8008c12 { ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 8008c02: 687b ldr r3, [r7, #4] 8008c04: 681b ldr r3, [r3, #0] 8008c06: 681a ldr r2, [r3, #0] 8008c08: 687b ldr r3, [r7, #4] 8008c0a: 681b ldr r3, [r3, #0] 8008c0c: f022 0208 bic.w r2, r2, #8 8008c10: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8008c12: 687b ldr r3, [r7, #4] 8008c14: 6ddb ldr r3, [r3, #92] @ 0x5c 8008c16: f003 031f and.w r3, r3, #31 8008c1a: 223f movs r2, #63 @ 0x3f 8008c1c: 409a lsls r2, r3 8008c1e: 6a3b ldr r3, [r7, #32] 8008c20: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8008c22: 687b ldr r3, [r7, #4] 8008c24: 2201 movs r2, #1 8008c26: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8008c2a: 687b ldr r3, [r7, #4] 8008c2c: 2200 movs r2, #0 8008c2e: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 8008c32: 687b ldr r3, [r7, #4] 8008c34: 6d1b ldr r3, [r3, #80] @ 0x50 8008c36: 2b00 cmp r3, #0 8008c38: f000 834a beq.w 80092d0 { hdma->XferAbortCallback(hdma); 8008c3c: 687b ldr r3, [r7, #4] 8008c3e: 6d1b ldr r3, [r3, #80] @ 0x50 8008c40: 6878 ldr r0, [r7, #4] 8008c42: 4798 blx r3 } return; 8008c44: e344 b.n 80092d0 } if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 8008c46: 687b ldr r3, [r7, #4] 8008c48: 681b ldr r3, [r3, #0] 8008c4a: 681b ldr r3, [r3, #0] 8008c4c: f403 2380 and.w r3, r3, #262144 @ 0x40000 8008c50: 2b00 cmp r3, #0 8008c52: d018 beq.n 8008c86 { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 8008c54: 687b ldr r3, [r7, #4] 8008c56: 681b ldr r3, [r3, #0] 8008c58: 681b ldr r3, [r3, #0] 8008c5a: f403 2300 and.w r3, r3, #524288 @ 0x80000 8008c5e: 2b00 cmp r3, #0 8008c60: d108 bne.n 8008c74 { if(hdma->XferM1CpltCallback != NULL) 8008c62: 687b ldr r3, [r7, #4] 8008c64: 6c5b ldr r3, [r3, #68] @ 0x44 8008c66: 2b00 cmp r3, #0 8008c68: d02c beq.n 8008cc4 { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 8008c6a: 687b ldr r3, [r7, #4] 8008c6c: 6c5b ldr r3, [r3, #68] @ 0x44 8008c6e: 6878 ldr r0, [r7, #4] 8008c70: 4798 blx r3 8008c72: e027 b.n 8008cc4 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 8008c74: 687b ldr r3, [r7, #4] 8008c76: 6bdb ldr r3, [r3, #60] @ 0x3c 8008c78: 2b00 cmp r3, #0 8008c7a: d023 beq.n 8008cc4 { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 8008c7c: 687b ldr r3, [r7, #4] 8008c7e: 6bdb ldr r3, [r3, #60] @ 0x3c 8008c80: 6878 ldr r0, [r7, #4] 8008c82: 4798 blx r3 8008c84: e01e b.n 8008cc4 } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 8008c86: 687b ldr r3, [r7, #4] 8008c88: 681b ldr r3, [r3, #0] 8008c8a: 681b ldr r3, [r3, #0] 8008c8c: f403 7380 and.w r3, r3, #256 @ 0x100 8008c90: 2b00 cmp r3, #0 8008c92: d10f bne.n 8008cb4 { /* Disable the transfer complete interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); 8008c94: 687b ldr r3, [r7, #4] 8008c96: 681b ldr r3, [r3, #0] 8008c98: 681a ldr r2, [r3, #0] 8008c9a: 687b ldr r3, [r7, #4] 8008c9c: 681b ldr r3, [r3, #0] 8008c9e: f022 0210 bic.w r2, r2, #16 8008ca2: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8008ca4: 687b ldr r3, [r7, #4] 8008ca6: 2201 movs r2, #1 8008ca8: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8008cac: 687b ldr r3, [r7, #4] 8008cae: 2200 movs r2, #0 8008cb0: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 8008cb4: 687b ldr r3, [r7, #4] 8008cb6: 6bdb ldr r3, [r3, #60] @ 0x3c 8008cb8: 2b00 cmp r3, #0 8008cba: d003 beq.n 8008cc4 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8008cbc: 687b ldr r3, [r7, #4] 8008cbe: 6bdb ldr r3, [r3, #60] @ 0x3c 8008cc0: 6878 ldr r0, [r7, #4] 8008cc2: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 8008cc4: 687b ldr r3, [r7, #4] 8008cc6: 6d5b ldr r3, [r3, #84] @ 0x54 8008cc8: 2b00 cmp r3, #0 8008cca: f000 8306 beq.w 80092da { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) 8008cce: 687b ldr r3, [r7, #4] 8008cd0: 6d5b ldr r3, [r3, #84] @ 0x54 8008cd2: f003 0301 and.w r3, r3, #1 8008cd6: 2b00 cmp r3, #0 8008cd8: f000 8088 beq.w 8008dec { hdma->State = HAL_DMA_STATE_ABORT; 8008cdc: 687b ldr r3, [r7, #4] 8008cde: 2204 movs r2, #4 8008ce0: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8008ce4: 687b ldr r3, [r7, #4] 8008ce6: 681b ldr r3, [r3, #0] 8008ce8: 4a7a ldr r2, [pc, #488] @ (8008ed4 ) 8008cea: 4293 cmp r3, r2 8008cec: d04a beq.n 8008d84 8008cee: 687b ldr r3, [r7, #4] 8008cf0: 681b ldr r3, [r3, #0] 8008cf2: 4a79 ldr r2, [pc, #484] @ (8008ed8 ) 8008cf4: 4293 cmp r3, r2 8008cf6: d045 beq.n 8008d84 8008cf8: 687b ldr r3, [r7, #4] 8008cfa: 681b ldr r3, [r3, #0] 8008cfc: 4a77 ldr r2, [pc, #476] @ (8008edc ) 8008cfe: 4293 cmp r3, r2 8008d00: d040 beq.n 8008d84 8008d02: 687b ldr r3, [r7, #4] 8008d04: 681b ldr r3, [r3, #0] 8008d06: 4a76 ldr r2, [pc, #472] @ (8008ee0 ) 8008d08: 4293 cmp r3, r2 8008d0a: d03b beq.n 8008d84 8008d0c: 687b ldr r3, [r7, #4] 8008d0e: 681b ldr r3, [r3, #0] 8008d10: 4a74 ldr r2, [pc, #464] @ (8008ee4 ) 8008d12: 4293 cmp r3, r2 8008d14: d036 beq.n 8008d84 8008d16: 687b ldr r3, [r7, #4] 8008d18: 681b ldr r3, [r3, #0] 8008d1a: 4a73 ldr r2, [pc, #460] @ (8008ee8 ) 8008d1c: 4293 cmp r3, r2 8008d1e: d031 beq.n 8008d84 8008d20: 687b ldr r3, [r7, #4] 8008d22: 681b ldr r3, [r3, #0] 8008d24: 4a71 ldr r2, [pc, #452] @ (8008eec ) 8008d26: 4293 cmp r3, r2 8008d28: d02c beq.n 8008d84 8008d2a: 687b ldr r3, [r7, #4] 8008d2c: 681b ldr r3, [r3, #0] 8008d2e: 4a70 ldr r2, [pc, #448] @ (8008ef0 ) 8008d30: 4293 cmp r3, r2 8008d32: d027 beq.n 8008d84 8008d34: 687b ldr r3, [r7, #4] 8008d36: 681b ldr r3, [r3, #0] 8008d38: 4a6e ldr r2, [pc, #440] @ (8008ef4 ) 8008d3a: 4293 cmp r3, r2 8008d3c: d022 beq.n 8008d84 8008d3e: 687b ldr r3, [r7, #4] 8008d40: 681b ldr r3, [r3, #0] 8008d42: 4a6d ldr r2, [pc, #436] @ (8008ef8 ) 8008d44: 4293 cmp r3, r2 8008d46: d01d beq.n 8008d84 8008d48: 687b ldr r3, [r7, #4] 8008d4a: 681b ldr r3, [r3, #0] 8008d4c: 4a6b ldr r2, [pc, #428] @ (8008efc ) 8008d4e: 4293 cmp r3, r2 8008d50: d018 beq.n 8008d84 8008d52: 687b ldr r3, [r7, #4] 8008d54: 681b ldr r3, [r3, #0] 8008d56: 4a6a ldr r2, [pc, #424] @ (8008f00 ) 8008d58: 4293 cmp r3, r2 8008d5a: d013 beq.n 8008d84 8008d5c: 687b ldr r3, [r7, #4] 8008d5e: 681b ldr r3, [r3, #0] 8008d60: 4a68 ldr r2, [pc, #416] @ (8008f04 ) 8008d62: 4293 cmp r3, r2 8008d64: d00e beq.n 8008d84 8008d66: 687b ldr r3, [r7, #4] 8008d68: 681b ldr r3, [r3, #0] 8008d6a: 4a67 ldr r2, [pc, #412] @ (8008f08 ) 8008d6c: 4293 cmp r3, r2 8008d6e: d009 beq.n 8008d84 8008d70: 687b ldr r3, [r7, #4] 8008d72: 681b ldr r3, [r3, #0] 8008d74: 4a65 ldr r2, [pc, #404] @ (8008f0c ) 8008d76: 4293 cmp r3, r2 8008d78: d004 beq.n 8008d84 8008d7a: 687b ldr r3, [r7, #4] 8008d7c: 681b ldr r3, [r3, #0] 8008d7e: 4a64 ldr r2, [pc, #400] @ (8008f10 ) 8008d80: 4293 cmp r3, r2 8008d82: d108 bne.n 8008d96 8008d84: 687b ldr r3, [r7, #4] 8008d86: 681b ldr r3, [r3, #0] 8008d88: 681a ldr r2, [r3, #0] 8008d8a: 687b ldr r3, [r7, #4] 8008d8c: 681b ldr r3, [r3, #0] 8008d8e: f022 0201 bic.w r2, r2, #1 8008d92: 601a str r2, [r3, #0] 8008d94: e007 b.n 8008da6 8008d96: 687b ldr r3, [r7, #4] 8008d98: 681b ldr r3, [r3, #0] 8008d9a: 681a ldr r2, [r3, #0] 8008d9c: 687b ldr r3, [r7, #4] 8008d9e: 681b ldr r3, [r3, #0] 8008da0: f022 0201 bic.w r2, r2, #1 8008da4: 601a str r2, [r3, #0] do { if (++count > timeout) 8008da6: 68fb ldr r3, [r7, #12] 8008da8: 3301 adds r3, #1 8008daa: 60fb str r3, [r7, #12] 8008dac: 6a7a ldr r2, [r7, #36] @ 0x24 8008dae: 429a cmp r2, r3 8008db0: d307 bcc.n 8008dc2 { break; } } while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); 8008db2: 687b ldr r3, [r7, #4] 8008db4: 681b ldr r3, [r3, #0] 8008db6: 681b ldr r3, [r3, #0] 8008db8: f003 0301 and.w r3, r3, #1 8008dbc: 2b00 cmp r3, #0 8008dbe: d1f2 bne.n 8008da6 8008dc0: e000 b.n 8008dc4 break; 8008dc2: bf00 nop if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 8008dc4: 687b ldr r3, [r7, #4] 8008dc6: 681b ldr r3, [r3, #0] 8008dc8: 681b ldr r3, [r3, #0] 8008dca: f003 0301 and.w r3, r3, #1 8008dce: 2b00 cmp r3, #0 8008dd0: d004 beq.n 8008ddc { /* Change the DMA state to error if DMA disable fails */ hdma->State = HAL_DMA_STATE_ERROR; 8008dd2: 687b ldr r3, [r7, #4] 8008dd4: 2203 movs r2, #3 8008dd6: f883 2035 strb.w r2, [r3, #53] @ 0x35 8008dda: e003 b.n 8008de4 } else { /* Change the DMA state to Ready if DMA disable success */ hdma->State = HAL_DMA_STATE_READY; 8008ddc: 687b ldr r3, [r7, #4] 8008dde: 2201 movs r2, #1 8008de0: f883 2035 strb.w r2, [r3, #53] @ 0x35 } /* Process Unlocked */ __HAL_UNLOCK(hdma); 8008de4: 687b ldr r3, [r7, #4] 8008de6: 2200 movs r2, #0 8008de8: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 8008dec: 687b ldr r3, [r7, #4] 8008dee: 6cdb ldr r3, [r3, #76] @ 0x4c 8008df0: 2b00 cmp r3, #0 8008df2: f000 8272 beq.w 80092da { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8008df6: 687b ldr r3, [r7, #4] 8008df8: 6cdb ldr r3, [r3, #76] @ 0x4c 8008dfa: 6878 ldr r0, [r7, #4] 8008dfc: 4798 blx r3 8008dfe: e26c b.n 80092da } } } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 8008e00: 687b ldr r3, [r7, #4] 8008e02: 681b ldr r3, [r3, #0] 8008e04: 4a43 ldr r2, [pc, #268] @ (8008f14 ) 8008e06: 4293 cmp r3, r2 8008e08: d022 beq.n 8008e50 8008e0a: 687b ldr r3, [r7, #4] 8008e0c: 681b ldr r3, [r3, #0] 8008e0e: 4a42 ldr r2, [pc, #264] @ (8008f18 ) 8008e10: 4293 cmp r3, r2 8008e12: d01d beq.n 8008e50 8008e14: 687b ldr r3, [r7, #4] 8008e16: 681b ldr r3, [r3, #0] 8008e18: 4a40 ldr r2, [pc, #256] @ (8008f1c ) 8008e1a: 4293 cmp r3, r2 8008e1c: d018 beq.n 8008e50 8008e1e: 687b ldr r3, [r7, #4] 8008e20: 681b ldr r3, [r3, #0] 8008e22: 4a3f ldr r2, [pc, #252] @ (8008f20 ) 8008e24: 4293 cmp r3, r2 8008e26: d013 beq.n 8008e50 8008e28: 687b ldr r3, [r7, #4] 8008e2a: 681b ldr r3, [r3, #0] 8008e2c: 4a3d ldr r2, [pc, #244] @ (8008f24 ) 8008e2e: 4293 cmp r3, r2 8008e30: d00e beq.n 8008e50 8008e32: 687b ldr r3, [r7, #4] 8008e34: 681b ldr r3, [r3, #0] 8008e36: 4a3c ldr r2, [pc, #240] @ (8008f28 ) 8008e38: 4293 cmp r3, r2 8008e3a: d009 beq.n 8008e50 8008e3c: 687b ldr r3, [r7, #4] 8008e3e: 681b ldr r3, [r3, #0] 8008e40: 4a3a ldr r2, [pc, #232] @ (8008f2c ) 8008e42: 4293 cmp r3, r2 8008e44: d004 beq.n 8008e50 8008e46: 687b ldr r3, [r7, #4] 8008e48: 681b ldr r3, [r3, #0] 8008e4a: 4a39 ldr r2, [pc, #228] @ (8008f30 ) 8008e4c: 4293 cmp r3, r2 8008e4e: d101 bne.n 8008e54 8008e50: 2301 movs r3, #1 8008e52: e000 b.n 8008e56 8008e54: 2300 movs r3, #0 8008e56: 2b00 cmp r3, #0 8008e58: f000 823f beq.w 80092da { ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); 8008e5c: 687b ldr r3, [r7, #4] 8008e5e: 681b ldr r3, [r3, #0] 8008e60: 681b ldr r3, [r3, #0] 8008e62: 613b str r3, [r7, #16] /* Half Transfer Complete Interrupt management ******************************/ if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) 8008e64: 687b ldr r3, [r7, #4] 8008e66: 6ddb ldr r3, [r3, #92] @ 0x5c 8008e68: f003 031f and.w r3, r3, #31 8008e6c: 2204 movs r2, #4 8008e6e: 409a lsls r2, r3 8008e70: 697b ldr r3, [r7, #20] 8008e72: 4013 ands r3, r2 8008e74: 2b00 cmp r3, #0 8008e76: f000 80cd beq.w 8009014 8008e7a: 693b ldr r3, [r7, #16] 8008e7c: f003 0304 and.w r3, r3, #4 8008e80: 2b00 cmp r3, #0 8008e82: f000 80c7 beq.w 8009014 { /* Clear the half transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); 8008e86: 687b ldr r3, [r7, #4] 8008e88: 6ddb ldr r3, [r3, #92] @ 0x5c 8008e8a: f003 031f and.w r3, r3, #31 8008e8e: 2204 movs r2, #4 8008e90: 409a lsls r2, r3 8008e92: 69fb ldr r3, [r7, #28] 8008e94: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 8008e96: 693b ldr r3, [r7, #16] 8008e98: f403 4300 and.w r3, r3, #32768 @ 0x8000 8008e9c: 2b00 cmp r3, #0 8008e9e: d049 beq.n 8008f34 { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 8008ea0: 693b ldr r3, [r7, #16] 8008ea2: f403 3380 and.w r3, r3, #65536 @ 0x10000 8008ea6: 2b00 cmp r3, #0 8008ea8: d109 bne.n 8008ebe { if(hdma->XferM1HalfCpltCallback != NULL) 8008eaa: 687b ldr r3, [r7, #4] 8008eac: 6c9b ldr r3, [r3, #72] @ 0x48 8008eae: 2b00 cmp r3, #0 8008eb0: f000 8210 beq.w 80092d4 { /* Half transfer Callback for Memory 1 */ hdma->XferM1HalfCpltCallback(hdma); 8008eb4: 687b ldr r3, [r7, #4] 8008eb6: 6c9b ldr r3, [r3, #72] @ 0x48 8008eb8: 6878 ldr r0, [r7, #4] 8008eba: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8008ebc: e20a b.n 80092d4 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferHalfCpltCallback != NULL) 8008ebe: 687b ldr r3, [r7, #4] 8008ec0: 6c1b ldr r3, [r3, #64] @ 0x40 8008ec2: 2b00 cmp r3, #0 8008ec4: f000 8206 beq.w 80092d4 { /* Half transfer Callback for Memory 0 */ hdma->XferHalfCpltCallback(hdma); 8008ec8: 687b ldr r3, [r7, #4] 8008eca: 6c1b ldr r3, [r3, #64] @ 0x40 8008ecc: 6878 ldr r0, [r7, #4] 8008ece: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8008ed0: e200 b.n 80092d4 8008ed2: bf00 nop 8008ed4: 40020010 .word 0x40020010 8008ed8: 40020028 .word 0x40020028 8008edc: 40020040 .word 0x40020040 8008ee0: 40020058 .word 0x40020058 8008ee4: 40020070 .word 0x40020070 8008ee8: 40020088 .word 0x40020088 8008eec: 400200a0 .word 0x400200a0 8008ef0: 400200b8 .word 0x400200b8 8008ef4: 40020410 .word 0x40020410 8008ef8: 40020428 .word 0x40020428 8008efc: 40020440 .word 0x40020440 8008f00: 40020458 .word 0x40020458 8008f04: 40020470 .word 0x40020470 8008f08: 40020488 .word 0x40020488 8008f0c: 400204a0 .word 0x400204a0 8008f10: 400204b8 .word 0x400204b8 8008f14: 58025408 .word 0x58025408 8008f18: 5802541c .word 0x5802541c 8008f1c: 58025430 .word 0x58025430 8008f20: 58025444 .word 0x58025444 8008f24: 58025458 .word 0x58025458 8008f28: 5802546c .word 0x5802546c 8008f2c: 58025480 .word 0x58025480 8008f30: 58025494 .word 0x58025494 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 8008f34: 693b ldr r3, [r7, #16] 8008f36: f003 0320 and.w r3, r3, #32 8008f3a: 2b00 cmp r3, #0 8008f3c: d160 bne.n 8009000 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8008f3e: 687b ldr r3, [r7, #4] 8008f40: 681b ldr r3, [r3, #0] 8008f42: 4a7f ldr r2, [pc, #508] @ (8009140 ) 8008f44: 4293 cmp r3, r2 8008f46: d04a beq.n 8008fde 8008f48: 687b ldr r3, [r7, #4] 8008f4a: 681b ldr r3, [r3, #0] 8008f4c: 4a7d ldr r2, [pc, #500] @ (8009144 ) 8008f4e: 4293 cmp r3, r2 8008f50: d045 beq.n 8008fde 8008f52: 687b ldr r3, [r7, #4] 8008f54: 681b ldr r3, [r3, #0] 8008f56: 4a7c ldr r2, [pc, #496] @ (8009148 ) 8008f58: 4293 cmp r3, r2 8008f5a: d040 beq.n 8008fde 8008f5c: 687b ldr r3, [r7, #4] 8008f5e: 681b ldr r3, [r3, #0] 8008f60: 4a7a ldr r2, [pc, #488] @ (800914c ) 8008f62: 4293 cmp r3, r2 8008f64: d03b beq.n 8008fde 8008f66: 687b ldr r3, [r7, #4] 8008f68: 681b ldr r3, [r3, #0] 8008f6a: 4a79 ldr r2, [pc, #484] @ (8009150 ) 8008f6c: 4293 cmp r3, r2 8008f6e: d036 beq.n 8008fde 8008f70: 687b ldr r3, [r7, #4] 8008f72: 681b ldr r3, [r3, #0] 8008f74: 4a77 ldr r2, [pc, #476] @ (8009154 ) 8008f76: 4293 cmp r3, r2 8008f78: d031 beq.n 8008fde 8008f7a: 687b ldr r3, [r7, #4] 8008f7c: 681b ldr r3, [r3, #0] 8008f7e: 4a76 ldr r2, [pc, #472] @ (8009158 ) 8008f80: 4293 cmp r3, r2 8008f82: d02c beq.n 8008fde 8008f84: 687b ldr r3, [r7, #4] 8008f86: 681b ldr r3, [r3, #0] 8008f88: 4a74 ldr r2, [pc, #464] @ (800915c ) 8008f8a: 4293 cmp r3, r2 8008f8c: d027 beq.n 8008fde 8008f8e: 687b ldr r3, [r7, #4] 8008f90: 681b ldr r3, [r3, #0] 8008f92: 4a73 ldr r2, [pc, #460] @ (8009160 ) 8008f94: 4293 cmp r3, r2 8008f96: d022 beq.n 8008fde 8008f98: 687b ldr r3, [r7, #4] 8008f9a: 681b ldr r3, [r3, #0] 8008f9c: 4a71 ldr r2, [pc, #452] @ (8009164 ) 8008f9e: 4293 cmp r3, r2 8008fa0: d01d beq.n 8008fde 8008fa2: 687b ldr r3, [r7, #4] 8008fa4: 681b ldr r3, [r3, #0] 8008fa6: 4a70 ldr r2, [pc, #448] @ (8009168 ) 8008fa8: 4293 cmp r3, r2 8008faa: d018 beq.n 8008fde 8008fac: 687b ldr r3, [r7, #4] 8008fae: 681b ldr r3, [r3, #0] 8008fb0: 4a6e ldr r2, [pc, #440] @ (800916c ) 8008fb2: 4293 cmp r3, r2 8008fb4: d013 beq.n 8008fde 8008fb6: 687b ldr r3, [r7, #4] 8008fb8: 681b ldr r3, [r3, #0] 8008fba: 4a6d ldr r2, [pc, #436] @ (8009170 ) 8008fbc: 4293 cmp r3, r2 8008fbe: d00e beq.n 8008fde 8008fc0: 687b ldr r3, [r7, #4] 8008fc2: 681b ldr r3, [r3, #0] 8008fc4: 4a6b ldr r2, [pc, #428] @ (8009174 ) 8008fc6: 4293 cmp r3, r2 8008fc8: d009 beq.n 8008fde 8008fca: 687b ldr r3, [r7, #4] 8008fcc: 681b ldr r3, [r3, #0] 8008fce: 4a6a ldr r2, [pc, #424] @ (8009178 ) 8008fd0: 4293 cmp r3, r2 8008fd2: d004 beq.n 8008fde 8008fd4: 687b ldr r3, [r7, #4] 8008fd6: 681b ldr r3, [r3, #0] 8008fd8: 4a68 ldr r2, [pc, #416] @ (800917c ) 8008fda: 4293 cmp r3, r2 8008fdc: d108 bne.n 8008ff0 8008fde: 687b ldr r3, [r7, #4] 8008fe0: 681b ldr r3, [r3, #0] 8008fe2: 681a ldr r2, [r3, #0] 8008fe4: 687b ldr r3, [r7, #4] 8008fe6: 681b ldr r3, [r3, #0] 8008fe8: f022 0208 bic.w r2, r2, #8 8008fec: 601a str r2, [r3, #0] 8008fee: e007 b.n 8009000 8008ff0: 687b ldr r3, [r7, #4] 8008ff2: 681b ldr r3, [r3, #0] 8008ff4: 681a ldr r2, [r3, #0] 8008ff6: 687b ldr r3, [r7, #4] 8008ff8: 681b ldr r3, [r3, #0] 8008ffa: f022 0204 bic.w r2, r2, #4 8008ffe: 601a str r2, [r3, #0] } /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 8009000: 687b ldr r3, [r7, #4] 8009002: 6c1b ldr r3, [r3, #64] @ 0x40 8009004: 2b00 cmp r3, #0 8009006: f000 8165 beq.w 80092d4 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800900a: 687b ldr r3, [r7, #4] 800900c: 6c1b ldr r3, [r3, #64] @ 0x40 800900e: 6878 ldr r0, [r7, #4] 8009010: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8009012: e15f b.n 80092d4 } } } /* Transfer Complete Interrupt management ***********************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) 8009014: 687b ldr r3, [r7, #4] 8009016: 6ddb ldr r3, [r3, #92] @ 0x5c 8009018: f003 031f and.w r3, r3, #31 800901c: 2202 movs r2, #2 800901e: 409a lsls r2, r3 8009020: 697b ldr r3, [r7, #20] 8009022: 4013 ands r3, r2 8009024: 2b00 cmp r3, #0 8009026: f000 80c5 beq.w 80091b4 800902a: 693b ldr r3, [r7, #16] 800902c: f003 0302 and.w r3, r3, #2 8009030: 2b00 cmp r3, #0 8009032: f000 80bf beq.w 80091b4 { /* Clear the transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); 8009036: 687b ldr r3, [r7, #4] 8009038: 6ddb ldr r3, [r3, #92] @ 0x5c 800903a: f003 031f and.w r3, r3, #31 800903e: 2202 movs r2, #2 8009040: 409a lsls r2, r3 8009042: 69fb ldr r3, [r7, #28] 8009044: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 8009046: 693b ldr r3, [r7, #16] 8009048: f403 4300 and.w r3, r3, #32768 @ 0x8000 800904c: 2b00 cmp r3, #0 800904e: d018 beq.n 8009082 { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 8009050: 693b ldr r3, [r7, #16] 8009052: f403 3380 and.w r3, r3, #65536 @ 0x10000 8009056: 2b00 cmp r3, #0 8009058: d109 bne.n 800906e { if(hdma->XferM1CpltCallback != NULL) 800905a: 687b ldr r3, [r7, #4] 800905c: 6c5b ldr r3, [r3, #68] @ 0x44 800905e: 2b00 cmp r3, #0 8009060: f000 813a beq.w 80092d8 { /* Transfer complete Callback for Memory 1 */ hdma->XferM1CpltCallback(hdma); 8009064: 687b ldr r3, [r7, #4] 8009066: 6c5b ldr r3, [r3, #68] @ 0x44 8009068: 6878 ldr r0, [r7, #4] 800906a: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800906c: e134 b.n 80092d8 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800906e: 687b ldr r3, [r7, #4] 8009070: 6bdb ldr r3, [r3, #60] @ 0x3c 8009072: 2b00 cmp r3, #0 8009074: f000 8130 beq.w 80092d8 { /* Transfer complete Callback for Memory 0 */ hdma->XferCpltCallback(hdma); 8009078: 687b ldr r3, [r7, #4] 800907a: 6bdb ldr r3, [r3, #60] @ 0x3c 800907c: 6878 ldr r0, [r7, #4] 800907e: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8009080: e12a b.n 80092d8 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 8009082: 693b ldr r3, [r7, #16] 8009084: f003 0320 and.w r3, r3, #32 8009088: 2b00 cmp r3, #0 800908a: f040 8089 bne.w 80091a0 { /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 800908e: 687b ldr r3, [r7, #4] 8009090: 681b ldr r3, [r3, #0] 8009092: 4a2b ldr r2, [pc, #172] @ (8009140 ) 8009094: 4293 cmp r3, r2 8009096: d04a beq.n 800912e 8009098: 687b ldr r3, [r7, #4] 800909a: 681b ldr r3, [r3, #0] 800909c: 4a29 ldr r2, [pc, #164] @ (8009144 ) 800909e: 4293 cmp r3, r2 80090a0: d045 beq.n 800912e 80090a2: 687b ldr r3, [r7, #4] 80090a4: 681b ldr r3, [r3, #0] 80090a6: 4a28 ldr r2, [pc, #160] @ (8009148 ) 80090a8: 4293 cmp r3, r2 80090aa: d040 beq.n 800912e 80090ac: 687b ldr r3, [r7, #4] 80090ae: 681b ldr r3, [r3, #0] 80090b0: 4a26 ldr r2, [pc, #152] @ (800914c ) 80090b2: 4293 cmp r3, r2 80090b4: d03b beq.n 800912e 80090b6: 687b ldr r3, [r7, #4] 80090b8: 681b ldr r3, [r3, #0] 80090ba: 4a25 ldr r2, [pc, #148] @ (8009150 ) 80090bc: 4293 cmp r3, r2 80090be: d036 beq.n 800912e 80090c0: 687b ldr r3, [r7, #4] 80090c2: 681b ldr r3, [r3, #0] 80090c4: 4a23 ldr r2, [pc, #140] @ (8009154 ) 80090c6: 4293 cmp r3, r2 80090c8: d031 beq.n 800912e 80090ca: 687b ldr r3, [r7, #4] 80090cc: 681b ldr r3, [r3, #0] 80090ce: 4a22 ldr r2, [pc, #136] @ (8009158 ) 80090d0: 4293 cmp r3, r2 80090d2: d02c beq.n 800912e 80090d4: 687b ldr r3, [r7, #4] 80090d6: 681b ldr r3, [r3, #0] 80090d8: 4a20 ldr r2, [pc, #128] @ (800915c ) 80090da: 4293 cmp r3, r2 80090dc: d027 beq.n 800912e 80090de: 687b ldr r3, [r7, #4] 80090e0: 681b ldr r3, [r3, #0] 80090e2: 4a1f ldr r2, [pc, #124] @ (8009160 ) 80090e4: 4293 cmp r3, r2 80090e6: d022 beq.n 800912e 80090e8: 687b ldr r3, [r7, #4] 80090ea: 681b ldr r3, [r3, #0] 80090ec: 4a1d ldr r2, [pc, #116] @ (8009164 ) 80090ee: 4293 cmp r3, r2 80090f0: d01d beq.n 800912e 80090f2: 687b ldr r3, [r7, #4] 80090f4: 681b ldr r3, [r3, #0] 80090f6: 4a1c ldr r2, [pc, #112] @ (8009168 ) 80090f8: 4293 cmp r3, r2 80090fa: d018 beq.n 800912e 80090fc: 687b ldr r3, [r7, #4] 80090fe: 681b ldr r3, [r3, #0] 8009100: 4a1a ldr r2, [pc, #104] @ (800916c ) 8009102: 4293 cmp r3, r2 8009104: d013 beq.n 800912e 8009106: 687b ldr r3, [r7, #4] 8009108: 681b ldr r3, [r3, #0] 800910a: 4a19 ldr r2, [pc, #100] @ (8009170 ) 800910c: 4293 cmp r3, r2 800910e: d00e beq.n 800912e 8009110: 687b ldr r3, [r7, #4] 8009112: 681b ldr r3, [r3, #0] 8009114: 4a17 ldr r2, [pc, #92] @ (8009174 ) 8009116: 4293 cmp r3, r2 8009118: d009 beq.n 800912e 800911a: 687b ldr r3, [r7, #4] 800911c: 681b ldr r3, [r3, #0] 800911e: 4a16 ldr r2, [pc, #88] @ (8009178 ) 8009120: 4293 cmp r3, r2 8009122: d004 beq.n 800912e 8009124: 687b ldr r3, [r7, #4] 8009126: 681b ldr r3, [r3, #0] 8009128: 4a14 ldr r2, [pc, #80] @ (800917c ) 800912a: 4293 cmp r3, r2 800912c: d128 bne.n 8009180 800912e: 687b ldr r3, [r7, #4] 8009130: 681b ldr r3, [r3, #0] 8009132: 681a ldr r2, [r3, #0] 8009134: 687b ldr r3, [r7, #4] 8009136: 681b ldr r3, [r3, #0] 8009138: f022 0214 bic.w r2, r2, #20 800913c: 601a str r2, [r3, #0] 800913e: e027 b.n 8009190 8009140: 40020010 .word 0x40020010 8009144: 40020028 .word 0x40020028 8009148: 40020040 .word 0x40020040 800914c: 40020058 .word 0x40020058 8009150: 40020070 .word 0x40020070 8009154: 40020088 .word 0x40020088 8009158: 400200a0 .word 0x400200a0 800915c: 400200b8 .word 0x400200b8 8009160: 40020410 .word 0x40020410 8009164: 40020428 .word 0x40020428 8009168: 40020440 .word 0x40020440 800916c: 40020458 .word 0x40020458 8009170: 40020470 .word 0x40020470 8009174: 40020488 .word 0x40020488 8009178: 400204a0 .word 0x400204a0 800917c: 400204b8 .word 0x400204b8 8009180: 687b ldr r3, [r7, #4] 8009182: 681b ldr r3, [r3, #0] 8009184: 681a ldr r2, [r3, #0] 8009186: 687b ldr r3, [r7, #4] 8009188: 681b ldr r3, [r3, #0] 800918a: f022 020a bic.w r2, r2, #10 800918e: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8009190: 687b ldr r3, [r7, #4] 8009192: 2201 movs r2, #1 8009194: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009198: 687b ldr r3, [r7, #4] 800919a: 2200 movs r2, #0 800919c: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 80091a0: 687b ldr r3, [r7, #4] 80091a2: 6bdb ldr r3, [r3, #60] @ 0x3c 80091a4: 2b00 cmp r3, #0 80091a6: f000 8097 beq.w 80092d8 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 80091aa: 687b ldr r3, [r7, #4] 80091ac: 6bdb ldr r3, [r3, #60] @ 0x3c 80091ae: 6878 ldr r0, [r7, #4] 80091b0: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 80091b2: e091 b.n 80092d8 } } } /* Transfer Error Interrupt management **************************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) 80091b4: 687b ldr r3, [r7, #4] 80091b6: 6ddb ldr r3, [r3, #92] @ 0x5c 80091b8: f003 031f and.w r3, r3, #31 80091bc: 2208 movs r2, #8 80091be: 409a lsls r2, r3 80091c0: 697b ldr r3, [r7, #20] 80091c2: 4013 ands r3, r2 80091c4: 2b00 cmp r3, #0 80091c6: f000 8088 beq.w 80092da 80091ca: 693b ldr r3, [r7, #16] 80091cc: f003 0308 and.w r3, r3, #8 80091d0: 2b00 cmp r3, #0 80091d2: f000 8082 beq.w 80092da { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80091d6: 687b ldr r3, [r7, #4] 80091d8: 681b ldr r3, [r3, #0] 80091da: 4a41 ldr r2, [pc, #260] @ (80092e0 ) 80091dc: 4293 cmp r3, r2 80091de: d04a beq.n 8009276 80091e0: 687b ldr r3, [r7, #4] 80091e2: 681b ldr r3, [r3, #0] 80091e4: 4a3f ldr r2, [pc, #252] @ (80092e4 ) 80091e6: 4293 cmp r3, r2 80091e8: d045 beq.n 8009276 80091ea: 687b ldr r3, [r7, #4] 80091ec: 681b ldr r3, [r3, #0] 80091ee: 4a3e ldr r2, [pc, #248] @ (80092e8 ) 80091f0: 4293 cmp r3, r2 80091f2: d040 beq.n 8009276 80091f4: 687b ldr r3, [r7, #4] 80091f6: 681b ldr r3, [r3, #0] 80091f8: 4a3c ldr r2, [pc, #240] @ (80092ec ) 80091fa: 4293 cmp r3, r2 80091fc: d03b beq.n 8009276 80091fe: 687b ldr r3, [r7, #4] 8009200: 681b ldr r3, [r3, #0] 8009202: 4a3b ldr r2, [pc, #236] @ (80092f0 ) 8009204: 4293 cmp r3, r2 8009206: d036 beq.n 8009276 8009208: 687b ldr r3, [r7, #4] 800920a: 681b ldr r3, [r3, #0] 800920c: 4a39 ldr r2, [pc, #228] @ (80092f4 ) 800920e: 4293 cmp r3, r2 8009210: d031 beq.n 8009276 8009212: 687b ldr r3, [r7, #4] 8009214: 681b ldr r3, [r3, #0] 8009216: 4a38 ldr r2, [pc, #224] @ (80092f8 ) 8009218: 4293 cmp r3, r2 800921a: d02c beq.n 8009276 800921c: 687b ldr r3, [r7, #4] 800921e: 681b ldr r3, [r3, #0] 8009220: 4a36 ldr r2, [pc, #216] @ (80092fc ) 8009222: 4293 cmp r3, r2 8009224: d027 beq.n 8009276 8009226: 687b ldr r3, [r7, #4] 8009228: 681b ldr r3, [r3, #0] 800922a: 4a35 ldr r2, [pc, #212] @ (8009300 ) 800922c: 4293 cmp r3, r2 800922e: d022 beq.n 8009276 8009230: 687b ldr r3, [r7, #4] 8009232: 681b ldr r3, [r3, #0] 8009234: 4a33 ldr r2, [pc, #204] @ (8009304 ) 8009236: 4293 cmp r3, r2 8009238: d01d beq.n 8009276 800923a: 687b ldr r3, [r7, #4] 800923c: 681b ldr r3, [r3, #0] 800923e: 4a32 ldr r2, [pc, #200] @ (8009308 ) 8009240: 4293 cmp r3, r2 8009242: d018 beq.n 8009276 8009244: 687b ldr r3, [r7, #4] 8009246: 681b ldr r3, [r3, #0] 8009248: 4a30 ldr r2, [pc, #192] @ (800930c ) 800924a: 4293 cmp r3, r2 800924c: d013 beq.n 8009276 800924e: 687b ldr r3, [r7, #4] 8009250: 681b ldr r3, [r3, #0] 8009252: 4a2f ldr r2, [pc, #188] @ (8009310 ) 8009254: 4293 cmp r3, r2 8009256: d00e beq.n 8009276 8009258: 687b ldr r3, [r7, #4] 800925a: 681b ldr r3, [r3, #0] 800925c: 4a2d ldr r2, [pc, #180] @ (8009314 ) 800925e: 4293 cmp r3, r2 8009260: d009 beq.n 8009276 8009262: 687b ldr r3, [r7, #4] 8009264: 681b ldr r3, [r3, #0] 8009266: 4a2c ldr r2, [pc, #176] @ (8009318 ) 8009268: 4293 cmp r3, r2 800926a: d004 beq.n 8009276 800926c: 687b ldr r3, [r7, #4] 800926e: 681b ldr r3, [r3, #0] 8009270: 4a2a ldr r2, [pc, #168] @ (800931c ) 8009272: 4293 cmp r3, r2 8009274: d108 bne.n 8009288 8009276: 687b ldr r3, [r7, #4] 8009278: 681b ldr r3, [r3, #0] 800927a: 681a ldr r2, [r3, #0] 800927c: 687b ldr r3, [r7, #4] 800927e: 681b ldr r3, [r3, #0] 8009280: f022 021c bic.w r2, r2, #28 8009284: 601a str r2, [r3, #0] 8009286: e007 b.n 8009298 8009288: 687b ldr r3, [r7, #4] 800928a: 681b ldr r3, [r3, #0] 800928c: 681a ldr r2, [r3, #0] 800928e: 687b ldr r3, [r7, #4] 8009290: 681b ldr r3, [r3, #0] 8009292: f022 020e bic.w r2, r2, #14 8009296: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 8009298: 687b ldr r3, [r7, #4] 800929a: 6ddb ldr r3, [r3, #92] @ 0x5c 800929c: f003 031f and.w r3, r3, #31 80092a0: 2201 movs r2, #1 80092a2: 409a lsls r2, r3 80092a4: 69fb ldr r3, [r7, #28] 80092a6: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 80092a8: 687b ldr r3, [r7, #4] 80092aa: 2201 movs r2, #1 80092ac: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80092ae: 687b ldr r3, [r7, #4] 80092b0: 2201 movs r2, #1 80092b2: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80092b6: 687b ldr r3, [r7, #4] 80092b8: 2200 movs r2, #0 80092ba: f883 2034 strb.w r2, [r3, #52] @ 0x34 if (hdma->XferErrorCallback != NULL) 80092be: 687b ldr r3, [r7, #4] 80092c0: 6cdb ldr r3, [r3, #76] @ 0x4c 80092c2: 2b00 cmp r3, #0 80092c4: d009 beq.n 80092da { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 80092c6: 687b ldr r3, [r7, #4] 80092c8: 6cdb ldr r3, [r3, #76] @ 0x4c 80092ca: 6878 ldr r0, [r7, #4] 80092cc: 4798 blx r3 80092ce: e004 b.n 80092da return; 80092d0: bf00 nop 80092d2: e002 b.n 80092da if((ccr_reg & BDMA_CCR_DBM) != 0U) 80092d4: bf00 nop 80092d6: e000 b.n 80092da if((ccr_reg & BDMA_CCR_DBM) != 0U) 80092d8: bf00 nop } else { /* Nothing To Do */ } } 80092da: 3728 adds r7, #40 @ 0x28 80092dc: 46bd mov sp, r7 80092de: bd80 pop {r7, pc} 80092e0: 40020010 .word 0x40020010 80092e4: 40020028 .word 0x40020028 80092e8: 40020040 .word 0x40020040 80092ec: 40020058 .word 0x40020058 80092f0: 40020070 .word 0x40020070 80092f4: 40020088 .word 0x40020088 80092f8: 400200a0 .word 0x400200a0 80092fc: 400200b8 .word 0x400200b8 8009300: 40020410 .word 0x40020410 8009304: 40020428 .word 0x40020428 8009308: 40020440 .word 0x40020440 800930c: 40020458 .word 0x40020458 8009310: 40020470 .word 0x40020470 8009314: 40020488 .word 0x40020488 8009318: 400204a0 .word 0x400204a0 800931c: 400204b8 .word 0x400204b8 08009320 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval None */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8009320: b480 push {r7} 8009322: b087 sub sp, #28 8009324: af00 add r7, sp, #0 8009326: 60f8 str r0, [r7, #12] 8009328: 60b9 str r1, [r7, #8] 800932a: 607a str r2, [r7, #4] 800932c: 603b str r3, [r7, #0] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 800932e: 68fb ldr r3, [r7, #12] 8009330: 6d9b ldr r3, [r3, #88] @ 0x58 8009332: 617b str r3, [r7, #20] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8009334: 68fb ldr r3, [r7, #12] 8009336: 6d9b ldr r3, [r3, #88] @ 0x58 8009338: 613b str r3, [r7, #16] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800933a: 68fb ldr r3, [r7, #12] 800933c: 681b ldr r3, [r3, #0] 800933e: 4a7f ldr r2, [pc, #508] @ (800953c ) 8009340: 4293 cmp r3, r2 8009342: d072 beq.n 800942a 8009344: 68fb ldr r3, [r7, #12] 8009346: 681b ldr r3, [r3, #0] 8009348: 4a7d ldr r2, [pc, #500] @ (8009540 ) 800934a: 4293 cmp r3, r2 800934c: d06d beq.n 800942a 800934e: 68fb ldr r3, [r7, #12] 8009350: 681b ldr r3, [r3, #0] 8009352: 4a7c ldr r2, [pc, #496] @ (8009544 ) 8009354: 4293 cmp r3, r2 8009356: d068 beq.n 800942a 8009358: 68fb ldr r3, [r7, #12] 800935a: 681b ldr r3, [r3, #0] 800935c: 4a7a ldr r2, [pc, #488] @ (8009548 ) 800935e: 4293 cmp r3, r2 8009360: d063 beq.n 800942a 8009362: 68fb ldr r3, [r7, #12] 8009364: 681b ldr r3, [r3, #0] 8009366: 4a79 ldr r2, [pc, #484] @ (800954c ) 8009368: 4293 cmp r3, r2 800936a: d05e beq.n 800942a 800936c: 68fb ldr r3, [r7, #12] 800936e: 681b ldr r3, [r3, #0] 8009370: 4a77 ldr r2, [pc, #476] @ (8009550 ) 8009372: 4293 cmp r3, r2 8009374: d059 beq.n 800942a 8009376: 68fb ldr r3, [r7, #12] 8009378: 681b ldr r3, [r3, #0] 800937a: 4a76 ldr r2, [pc, #472] @ (8009554 ) 800937c: 4293 cmp r3, r2 800937e: d054 beq.n 800942a 8009380: 68fb ldr r3, [r7, #12] 8009382: 681b ldr r3, [r3, #0] 8009384: 4a74 ldr r2, [pc, #464] @ (8009558 ) 8009386: 4293 cmp r3, r2 8009388: d04f beq.n 800942a 800938a: 68fb ldr r3, [r7, #12] 800938c: 681b ldr r3, [r3, #0] 800938e: 4a73 ldr r2, [pc, #460] @ (800955c ) 8009390: 4293 cmp r3, r2 8009392: d04a beq.n 800942a 8009394: 68fb ldr r3, [r7, #12] 8009396: 681b ldr r3, [r3, #0] 8009398: 4a71 ldr r2, [pc, #452] @ (8009560 ) 800939a: 4293 cmp r3, r2 800939c: d045 beq.n 800942a 800939e: 68fb ldr r3, [r7, #12] 80093a0: 681b ldr r3, [r3, #0] 80093a2: 4a70 ldr r2, [pc, #448] @ (8009564 ) 80093a4: 4293 cmp r3, r2 80093a6: d040 beq.n 800942a 80093a8: 68fb ldr r3, [r7, #12] 80093aa: 681b ldr r3, [r3, #0] 80093ac: 4a6e ldr r2, [pc, #440] @ (8009568 ) 80093ae: 4293 cmp r3, r2 80093b0: d03b beq.n 800942a 80093b2: 68fb ldr r3, [r7, #12] 80093b4: 681b ldr r3, [r3, #0] 80093b6: 4a6d ldr r2, [pc, #436] @ (800956c ) 80093b8: 4293 cmp r3, r2 80093ba: d036 beq.n 800942a 80093bc: 68fb ldr r3, [r7, #12] 80093be: 681b ldr r3, [r3, #0] 80093c0: 4a6b ldr r2, [pc, #428] @ (8009570 ) 80093c2: 4293 cmp r3, r2 80093c4: d031 beq.n 800942a 80093c6: 68fb ldr r3, [r7, #12] 80093c8: 681b ldr r3, [r3, #0] 80093ca: 4a6a ldr r2, [pc, #424] @ (8009574 ) 80093cc: 4293 cmp r3, r2 80093ce: d02c beq.n 800942a 80093d0: 68fb ldr r3, [r7, #12] 80093d2: 681b ldr r3, [r3, #0] 80093d4: 4a68 ldr r2, [pc, #416] @ (8009578 ) 80093d6: 4293 cmp r3, r2 80093d8: d027 beq.n 800942a 80093da: 68fb ldr r3, [r7, #12] 80093dc: 681b ldr r3, [r3, #0] 80093de: 4a67 ldr r2, [pc, #412] @ (800957c ) 80093e0: 4293 cmp r3, r2 80093e2: d022 beq.n 800942a 80093e4: 68fb ldr r3, [r7, #12] 80093e6: 681b ldr r3, [r3, #0] 80093e8: 4a65 ldr r2, [pc, #404] @ (8009580 ) 80093ea: 4293 cmp r3, r2 80093ec: d01d beq.n 800942a 80093ee: 68fb ldr r3, [r7, #12] 80093f0: 681b ldr r3, [r3, #0] 80093f2: 4a64 ldr r2, [pc, #400] @ (8009584 ) 80093f4: 4293 cmp r3, r2 80093f6: d018 beq.n 800942a 80093f8: 68fb ldr r3, [r7, #12] 80093fa: 681b ldr r3, [r3, #0] 80093fc: 4a62 ldr r2, [pc, #392] @ (8009588 ) 80093fe: 4293 cmp r3, r2 8009400: d013 beq.n 800942a 8009402: 68fb ldr r3, [r7, #12] 8009404: 681b ldr r3, [r3, #0] 8009406: 4a61 ldr r2, [pc, #388] @ (800958c ) 8009408: 4293 cmp r3, r2 800940a: d00e beq.n 800942a 800940c: 68fb ldr r3, [r7, #12] 800940e: 681b ldr r3, [r3, #0] 8009410: 4a5f ldr r2, [pc, #380] @ (8009590 ) 8009412: 4293 cmp r3, r2 8009414: d009 beq.n 800942a 8009416: 68fb ldr r3, [r7, #12] 8009418: 681b ldr r3, [r3, #0] 800941a: 4a5e ldr r2, [pc, #376] @ (8009594 ) 800941c: 4293 cmp r3, r2 800941e: d004 beq.n 800942a 8009420: 68fb ldr r3, [r7, #12] 8009422: 681b ldr r3, [r3, #0] 8009424: 4a5c ldr r2, [pc, #368] @ (8009598 ) 8009426: 4293 cmp r3, r2 8009428: d101 bne.n 800942e 800942a: 2301 movs r3, #1 800942c: e000 b.n 8009430 800942e: 2300 movs r3, #0 8009430: 2b00 cmp r3, #0 8009432: d00d beq.n 8009450 { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8009434: 68fb ldr r3, [r7, #12] 8009436: 6e5b ldr r3, [r3, #100] @ 0x64 8009438: 68fa ldr r2, [r7, #12] 800943a: 6e92 ldr r2, [r2, #104] @ 0x68 800943c: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 800943e: 68fb ldr r3, [r7, #12] 8009440: 6edb ldr r3, [r3, #108] @ 0x6c 8009442: 2b00 cmp r3, #0 8009444: d004 beq.n 8009450 { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8009446: 68fb ldr r3, [r7, #12] 8009448: 6f1b ldr r3, [r3, #112] @ 0x70 800944a: 68fa ldr r2, [r7, #12] 800944c: 6f52 ldr r2, [r2, #116] @ 0x74 800944e: 605a str r2, [r3, #4] } } if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8009450: 68fb ldr r3, [r7, #12] 8009452: 681b ldr r3, [r3, #0] 8009454: 4a39 ldr r2, [pc, #228] @ (800953c ) 8009456: 4293 cmp r3, r2 8009458: d04a beq.n 80094f0 800945a: 68fb ldr r3, [r7, #12] 800945c: 681b ldr r3, [r3, #0] 800945e: 4a38 ldr r2, [pc, #224] @ (8009540 ) 8009460: 4293 cmp r3, r2 8009462: d045 beq.n 80094f0 8009464: 68fb ldr r3, [r7, #12] 8009466: 681b ldr r3, [r3, #0] 8009468: 4a36 ldr r2, [pc, #216] @ (8009544 ) 800946a: 4293 cmp r3, r2 800946c: d040 beq.n 80094f0 800946e: 68fb ldr r3, [r7, #12] 8009470: 681b ldr r3, [r3, #0] 8009472: 4a35 ldr r2, [pc, #212] @ (8009548 ) 8009474: 4293 cmp r3, r2 8009476: d03b beq.n 80094f0 8009478: 68fb ldr r3, [r7, #12] 800947a: 681b ldr r3, [r3, #0] 800947c: 4a33 ldr r2, [pc, #204] @ (800954c ) 800947e: 4293 cmp r3, r2 8009480: d036 beq.n 80094f0 8009482: 68fb ldr r3, [r7, #12] 8009484: 681b ldr r3, [r3, #0] 8009486: 4a32 ldr r2, [pc, #200] @ (8009550 ) 8009488: 4293 cmp r3, r2 800948a: d031 beq.n 80094f0 800948c: 68fb ldr r3, [r7, #12] 800948e: 681b ldr r3, [r3, #0] 8009490: 4a30 ldr r2, [pc, #192] @ (8009554 ) 8009492: 4293 cmp r3, r2 8009494: d02c beq.n 80094f0 8009496: 68fb ldr r3, [r7, #12] 8009498: 681b ldr r3, [r3, #0] 800949a: 4a2f ldr r2, [pc, #188] @ (8009558 ) 800949c: 4293 cmp r3, r2 800949e: d027 beq.n 80094f0 80094a0: 68fb ldr r3, [r7, #12] 80094a2: 681b ldr r3, [r3, #0] 80094a4: 4a2d ldr r2, [pc, #180] @ (800955c ) 80094a6: 4293 cmp r3, r2 80094a8: d022 beq.n 80094f0 80094aa: 68fb ldr r3, [r7, #12] 80094ac: 681b ldr r3, [r3, #0] 80094ae: 4a2c ldr r2, [pc, #176] @ (8009560 ) 80094b0: 4293 cmp r3, r2 80094b2: d01d beq.n 80094f0 80094b4: 68fb ldr r3, [r7, #12] 80094b6: 681b ldr r3, [r3, #0] 80094b8: 4a2a ldr r2, [pc, #168] @ (8009564 ) 80094ba: 4293 cmp r3, r2 80094bc: d018 beq.n 80094f0 80094be: 68fb ldr r3, [r7, #12] 80094c0: 681b ldr r3, [r3, #0] 80094c2: 4a29 ldr r2, [pc, #164] @ (8009568 ) 80094c4: 4293 cmp r3, r2 80094c6: d013 beq.n 80094f0 80094c8: 68fb ldr r3, [r7, #12] 80094ca: 681b ldr r3, [r3, #0] 80094cc: 4a27 ldr r2, [pc, #156] @ (800956c ) 80094ce: 4293 cmp r3, r2 80094d0: d00e beq.n 80094f0 80094d2: 68fb ldr r3, [r7, #12] 80094d4: 681b ldr r3, [r3, #0] 80094d6: 4a26 ldr r2, [pc, #152] @ (8009570 ) 80094d8: 4293 cmp r3, r2 80094da: d009 beq.n 80094f0 80094dc: 68fb ldr r3, [r7, #12] 80094de: 681b ldr r3, [r3, #0] 80094e0: 4a24 ldr r2, [pc, #144] @ (8009574 ) 80094e2: 4293 cmp r3, r2 80094e4: d004 beq.n 80094f0 80094e6: 68fb ldr r3, [r7, #12] 80094e8: 681b ldr r3, [r3, #0] 80094ea: 4a23 ldr r2, [pc, #140] @ (8009578 ) 80094ec: 4293 cmp r3, r2 80094ee: d101 bne.n 80094f4 80094f0: 2301 movs r3, #1 80094f2: e000 b.n 80094f6 80094f4: 2300 movs r3, #0 80094f6: 2b00 cmp r3, #0 80094f8: d059 beq.n 80095ae { /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 80094fa: 68fb ldr r3, [r7, #12] 80094fc: 6ddb ldr r3, [r3, #92] @ 0x5c 80094fe: f003 031f and.w r3, r3, #31 8009502: 223f movs r2, #63 @ 0x3f 8009504: 409a lsls r2, r3 8009506: 697b ldr r3, [r7, #20] 8009508: 609a str r2, [r3, #8] /* Clear DBM bit */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM); 800950a: 68fb ldr r3, [r7, #12] 800950c: 681b ldr r3, [r3, #0] 800950e: 681a ldr r2, [r3, #0] 8009510: 68fb ldr r3, [r7, #12] 8009512: 681b ldr r3, [r3, #0] 8009514: f422 2280 bic.w r2, r2, #262144 @ 0x40000 8009518: 601a str r2, [r3, #0] /* Configure DMA Stream data length */ ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; 800951a: 68fb ldr r3, [r7, #12] 800951c: 681b ldr r3, [r3, #0] 800951e: 683a ldr r2, [r7, #0] 8009520: 605a str r2, [r3, #4] /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8009522: 68fb ldr r3, [r7, #12] 8009524: 689b ldr r3, [r3, #8] 8009526: 2b40 cmp r3, #64 @ 0x40 8009528: d138 bne.n 800959c { /* Configure DMA Stream destination address */ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; 800952a: 68fb ldr r3, [r7, #12] 800952c: 681b ldr r3, [r3, #0] 800952e: 687a ldr r2, [r7, #4] 8009530: 609a str r2, [r3, #8] /* Configure DMA Stream source address */ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; 8009532: 68fb ldr r3, [r7, #12] 8009534: 681b ldr r3, [r3, #0] 8009536: 68ba ldr r2, [r7, #8] 8009538: 60da str r2, [r3, #12] } else { /* Nothing To Do */ } } 800953a: e086 b.n 800964a 800953c: 40020010 .word 0x40020010 8009540: 40020028 .word 0x40020028 8009544: 40020040 .word 0x40020040 8009548: 40020058 .word 0x40020058 800954c: 40020070 .word 0x40020070 8009550: 40020088 .word 0x40020088 8009554: 400200a0 .word 0x400200a0 8009558: 400200b8 .word 0x400200b8 800955c: 40020410 .word 0x40020410 8009560: 40020428 .word 0x40020428 8009564: 40020440 .word 0x40020440 8009568: 40020458 .word 0x40020458 800956c: 40020470 .word 0x40020470 8009570: 40020488 .word 0x40020488 8009574: 400204a0 .word 0x400204a0 8009578: 400204b8 .word 0x400204b8 800957c: 58025408 .word 0x58025408 8009580: 5802541c .word 0x5802541c 8009584: 58025430 .word 0x58025430 8009588: 58025444 .word 0x58025444 800958c: 58025458 .word 0x58025458 8009590: 5802546c .word 0x5802546c 8009594: 58025480 .word 0x58025480 8009598: 58025494 .word 0x58025494 ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; 800959c: 68fb ldr r3, [r7, #12] 800959e: 681b ldr r3, [r3, #0] 80095a0: 68ba ldr r2, [r7, #8] 80095a2: 609a str r2, [r3, #8] ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; 80095a4: 68fb ldr r3, [r7, #12] 80095a6: 681b ldr r3, [r3, #0] 80095a8: 687a ldr r2, [r7, #4] 80095aa: 60da str r2, [r3, #12] } 80095ac: e04d b.n 800964a else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 80095ae: 68fb ldr r3, [r7, #12] 80095b0: 681b ldr r3, [r3, #0] 80095b2: 4a29 ldr r2, [pc, #164] @ (8009658 ) 80095b4: 4293 cmp r3, r2 80095b6: d022 beq.n 80095fe 80095b8: 68fb ldr r3, [r7, #12] 80095ba: 681b ldr r3, [r3, #0] 80095bc: 4a27 ldr r2, [pc, #156] @ (800965c ) 80095be: 4293 cmp r3, r2 80095c0: d01d beq.n 80095fe 80095c2: 68fb ldr r3, [r7, #12] 80095c4: 681b ldr r3, [r3, #0] 80095c6: 4a26 ldr r2, [pc, #152] @ (8009660 ) 80095c8: 4293 cmp r3, r2 80095ca: d018 beq.n 80095fe 80095cc: 68fb ldr r3, [r7, #12] 80095ce: 681b ldr r3, [r3, #0] 80095d0: 4a24 ldr r2, [pc, #144] @ (8009664 ) 80095d2: 4293 cmp r3, r2 80095d4: d013 beq.n 80095fe 80095d6: 68fb ldr r3, [r7, #12] 80095d8: 681b ldr r3, [r3, #0] 80095da: 4a23 ldr r2, [pc, #140] @ (8009668 ) 80095dc: 4293 cmp r3, r2 80095de: d00e beq.n 80095fe 80095e0: 68fb ldr r3, [r7, #12] 80095e2: 681b ldr r3, [r3, #0] 80095e4: 4a21 ldr r2, [pc, #132] @ (800966c ) 80095e6: 4293 cmp r3, r2 80095e8: d009 beq.n 80095fe 80095ea: 68fb ldr r3, [r7, #12] 80095ec: 681b ldr r3, [r3, #0] 80095ee: 4a20 ldr r2, [pc, #128] @ (8009670 ) 80095f0: 4293 cmp r3, r2 80095f2: d004 beq.n 80095fe 80095f4: 68fb ldr r3, [r7, #12] 80095f6: 681b ldr r3, [r3, #0] 80095f8: 4a1e ldr r2, [pc, #120] @ (8009674 ) 80095fa: 4293 cmp r3, r2 80095fc: d101 bne.n 8009602 80095fe: 2301 movs r3, #1 8009600: e000 b.n 8009604 8009602: 2300 movs r3, #0 8009604: 2b00 cmp r3, #0 8009606: d020 beq.n 800964a regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 8009608: 68fb ldr r3, [r7, #12] 800960a: 6ddb ldr r3, [r3, #92] @ 0x5c 800960c: f003 031f and.w r3, r3, #31 8009610: 2201 movs r2, #1 8009612: 409a lsls r2, r3 8009614: 693b ldr r3, [r7, #16] 8009616: 605a str r2, [r3, #4] ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; 8009618: 68fb ldr r3, [r7, #12] 800961a: 681b ldr r3, [r3, #0] 800961c: 683a ldr r2, [r7, #0] 800961e: 605a str r2, [r3, #4] if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8009620: 68fb ldr r3, [r7, #12] 8009622: 689b ldr r3, [r3, #8] 8009624: 2b40 cmp r3, #64 @ 0x40 8009626: d108 bne.n 800963a ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; 8009628: 68fb ldr r3, [r7, #12] 800962a: 681b ldr r3, [r3, #0] 800962c: 687a ldr r2, [r7, #4] 800962e: 609a str r2, [r3, #8] ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; 8009630: 68fb ldr r3, [r7, #12] 8009632: 681b ldr r3, [r3, #0] 8009634: 68ba ldr r2, [r7, #8] 8009636: 60da str r2, [r3, #12] } 8009638: e007 b.n 800964a ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; 800963a: 68fb ldr r3, [r7, #12] 800963c: 681b ldr r3, [r3, #0] 800963e: 68ba ldr r2, [r7, #8] 8009640: 609a str r2, [r3, #8] ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; 8009642: 68fb ldr r3, [r7, #12] 8009644: 681b ldr r3, [r3, #0] 8009646: 687a ldr r2, [r7, #4] 8009648: 60da str r2, [r3, #12] } 800964a: bf00 nop 800964c: 371c adds r7, #28 800964e: 46bd mov sp, r7 8009650: f85d 7b04 ldr.w r7, [sp], #4 8009654: 4770 bx lr 8009656: bf00 nop 8009658: 58025408 .word 0x58025408 800965c: 5802541c .word 0x5802541c 8009660: 58025430 .word 0x58025430 8009664: 58025444 .word 0x58025444 8009668: 58025458 .word 0x58025458 800966c: 5802546c .word 0x5802546c 8009670: 58025480 .word 0x58025480 8009674: 58025494 .word 0x58025494 08009678 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 8009678: b480 push {r7} 800967a: b085 sub sp, #20 800967c: af00 add r7, sp, #0 800967e: 6078 str r0, [r7, #4] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8009680: 687b ldr r3, [r7, #4] 8009682: 681b ldr r3, [r3, #0] 8009684: 4a42 ldr r2, [pc, #264] @ (8009790 ) 8009686: 4293 cmp r3, r2 8009688: d04a beq.n 8009720 800968a: 687b ldr r3, [r7, #4] 800968c: 681b ldr r3, [r3, #0] 800968e: 4a41 ldr r2, [pc, #260] @ (8009794 ) 8009690: 4293 cmp r3, r2 8009692: d045 beq.n 8009720 8009694: 687b ldr r3, [r7, #4] 8009696: 681b ldr r3, [r3, #0] 8009698: 4a3f ldr r2, [pc, #252] @ (8009798 ) 800969a: 4293 cmp r3, r2 800969c: d040 beq.n 8009720 800969e: 687b ldr r3, [r7, #4] 80096a0: 681b ldr r3, [r3, #0] 80096a2: 4a3e ldr r2, [pc, #248] @ (800979c ) 80096a4: 4293 cmp r3, r2 80096a6: d03b beq.n 8009720 80096a8: 687b ldr r3, [r7, #4] 80096aa: 681b ldr r3, [r3, #0] 80096ac: 4a3c ldr r2, [pc, #240] @ (80097a0 ) 80096ae: 4293 cmp r3, r2 80096b0: d036 beq.n 8009720 80096b2: 687b ldr r3, [r7, #4] 80096b4: 681b ldr r3, [r3, #0] 80096b6: 4a3b ldr r2, [pc, #236] @ (80097a4 ) 80096b8: 4293 cmp r3, r2 80096ba: d031 beq.n 8009720 80096bc: 687b ldr r3, [r7, #4] 80096be: 681b ldr r3, [r3, #0] 80096c0: 4a39 ldr r2, [pc, #228] @ (80097a8 ) 80096c2: 4293 cmp r3, r2 80096c4: d02c beq.n 8009720 80096c6: 687b ldr r3, [r7, #4] 80096c8: 681b ldr r3, [r3, #0] 80096ca: 4a38 ldr r2, [pc, #224] @ (80097ac ) 80096cc: 4293 cmp r3, r2 80096ce: d027 beq.n 8009720 80096d0: 687b ldr r3, [r7, #4] 80096d2: 681b ldr r3, [r3, #0] 80096d4: 4a36 ldr r2, [pc, #216] @ (80097b0 ) 80096d6: 4293 cmp r3, r2 80096d8: d022 beq.n 8009720 80096da: 687b ldr r3, [r7, #4] 80096dc: 681b ldr r3, [r3, #0] 80096de: 4a35 ldr r2, [pc, #212] @ (80097b4 ) 80096e0: 4293 cmp r3, r2 80096e2: d01d beq.n 8009720 80096e4: 687b ldr r3, [r7, #4] 80096e6: 681b ldr r3, [r3, #0] 80096e8: 4a33 ldr r2, [pc, #204] @ (80097b8 ) 80096ea: 4293 cmp r3, r2 80096ec: d018 beq.n 8009720 80096ee: 687b ldr r3, [r7, #4] 80096f0: 681b ldr r3, [r3, #0] 80096f2: 4a32 ldr r2, [pc, #200] @ (80097bc ) 80096f4: 4293 cmp r3, r2 80096f6: d013 beq.n 8009720 80096f8: 687b ldr r3, [r7, #4] 80096fa: 681b ldr r3, [r3, #0] 80096fc: 4a30 ldr r2, [pc, #192] @ (80097c0 ) 80096fe: 4293 cmp r3, r2 8009700: d00e beq.n 8009720 8009702: 687b ldr r3, [r7, #4] 8009704: 681b ldr r3, [r3, #0] 8009706: 4a2f ldr r2, [pc, #188] @ (80097c4 ) 8009708: 4293 cmp r3, r2 800970a: d009 beq.n 8009720 800970c: 687b ldr r3, [r7, #4] 800970e: 681b ldr r3, [r3, #0] 8009710: 4a2d ldr r2, [pc, #180] @ (80097c8 ) 8009712: 4293 cmp r3, r2 8009714: d004 beq.n 8009720 8009716: 687b ldr r3, [r7, #4] 8009718: 681b ldr r3, [r3, #0] 800971a: 4a2c ldr r2, [pc, #176] @ (80097cc ) 800971c: 4293 cmp r3, r2 800971e: d101 bne.n 8009724 8009720: 2301 movs r3, #1 8009722: e000 b.n 8009726 8009724: 2300 movs r3, #0 8009726: 2b00 cmp r3, #0 8009728: d024 beq.n 8009774 { uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800972a: 687b ldr r3, [r7, #4] 800972c: 681b ldr r3, [r3, #0] 800972e: b2db uxtb r3, r3 8009730: 3b10 subs r3, #16 8009732: 4a27 ldr r2, [pc, #156] @ (80097d0 ) 8009734: fba2 2303 umull r2, r3, r2, r3 8009738: 091b lsrs r3, r3, #4 800973a: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; 800973c: 68fb ldr r3, [r7, #12] 800973e: f003 0307 and.w r3, r3, #7 8009742: 4a24 ldr r2, [pc, #144] @ (80097d4 ) 8009744: 5cd3 ldrb r3, [r2, r3] 8009746: 461a mov r2, r3 8009748: 687b ldr r3, [r7, #4] 800974a: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 800974c: 68fb ldr r3, [r7, #12] 800974e: 2b03 cmp r3, #3 8009750: d908 bls.n 8009764 { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); 8009752: 687b ldr r3, [r7, #4] 8009754: 681b ldr r3, [r3, #0] 8009756: 461a mov r2, r3 8009758: 4b1f ldr r3, [pc, #124] @ (80097d8 ) 800975a: 4013 ands r3, r2 800975c: 1d1a adds r2, r3, #4 800975e: 687b ldr r3, [r7, #4] 8009760: 659a str r2, [r3, #88] @ 0x58 8009762: e00d b.n 8009780 } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); 8009764: 687b ldr r3, [r7, #4] 8009766: 681b ldr r3, [r3, #0] 8009768: 461a mov r2, r3 800976a: 4b1b ldr r3, [pc, #108] @ (80097d8 ) 800976c: 4013 ands r3, r2 800976e: 687a ldr r2, [r7, #4] 8009770: 6593 str r3, [r2, #88] @ 0x58 8009772: e005 b.n 8009780 } } else /* BDMA instance(s) */ { /* return pointer to ISR and IFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); 8009774: 687b ldr r3, [r7, #4] 8009776: 681b ldr r3, [r3, #0] 8009778: f023 02ff bic.w r2, r3, #255 @ 0xff 800977c: 687b ldr r3, [r7, #4] 800977e: 659a str r2, [r3, #88] @ 0x58 } return hdma->StreamBaseAddress; 8009780: 687b ldr r3, [r7, #4] 8009782: 6d9b ldr r3, [r3, #88] @ 0x58 } 8009784: 4618 mov r0, r3 8009786: 3714 adds r7, #20 8009788: 46bd mov sp, r7 800978a: f85d 7b04 ldr.w r7, [sp], #4 800978e: 4770 bx lr 8009790: 40020010 .word 0x40020010 8009794: 40020028 .word 0x40020028 8009798: 40020040 .word 0x40020040 800979c: 40020058 .word 0x40020058 80097a0: 40020070 .word 0x40020070 80097a4: 40020088 .word 0x40020088 80097a8: 400200a0 .word 0x400200a0 80097ac: 400200b8 .word 0x400200b8 80097b0: 40020410 .word 0x40020410 80097b4: 40020428 .word 0x40020428 80097b8: 40020440 .word 0x40020440 80097bc: 40020458 .word 0x40020458 80097c0: 40020470 .word 0x40020470 80097c4: 40020488 .word 0x40020488 80097c8: 400204a0 .word 0x400204a0 80097cc: 400204b8 .word 0x400204b8 80097d0: aaaaaaab .word 0xaaaaaaab 80097d4: 080175d8 .word 0x080175d8 80097d8: fffffc00 .word 0xfffffc00 080097dc : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 80097dc: b480 push {r7} 80097de: b085 sub sp, #20 80097e0: af00 add r7, sp, #0 80097e2: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80097e4: 2300 movs r3, #0 80097e6: 73fb strb r3, [r7, #15] /* Memory Data size equal to Byte */ if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 80097e8: 687b ldr r3, [r7, #4] 80097ea: 699b ldr r3, [r3, #24] 80097ec: 2b00 cmp r3, #0 80097ee: d120 bne.n 8009832 { switch (hdma->Init.FIFOThreshold) 80097f0: 687b ldr r3, [r7, #4] 80097f2: 6a9b ldr r3, [r3, #40] @ 0x28 80097f4: 2b03 cmp r3, #3 80097f6: d858 bhi.n 80098aa 80097f8: a201 add r2, pc, #4 @ (adr r2, 8009800 ) 80097fa: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80097fe: bf00 nop 8009800: 08009811 .word 0x08009811 8009804: 08009823 .word 0x08009823 8009808: 08009811 .word 0x08009811 800980c: 080098ab .word 0x080098ab { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8009810: 687b ldr r3, [r7, #4] 8009812: 6adb ldr r3, [r3, #44] @ 0x2c 8009814: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8009818: 2b00 cmp r3, #0 800981a: d048 beq.n 80098ae { status = HAL_ERROR; 800981c: 2301 movs r3, #1 800981e: 73fb strb r3, [r7, #15] } break; 8009820: e045 b.n 80098ae case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8009822: 687b ldr r3, [r7, #4] 8009824: 6adb ldr r3, [r3, #44] @ 0x2c 8009826: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800982a: d142 bne.n 80098b2 { status = HAL_ERROR; 800982c: 2301 movs r3, #1 800982e: 73fb strb r3, [r7, #15] } break; 8009830: e03f b.n 80098b2 break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 8009832: 687b ldr r3, [r7, #4] 8009834: 699b ldr r3, [r3, #24] 8009836: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800983a: d123 bne.n 8009884 { switch (hdma->Init.FIFOThreshold) 800983c: 687b ldr r3, [r7, #4] 800983e: 6a9b ldr r3, [r3, #40] @ 0x28 8009840: 2b03 cmp r3, #3 8009842: d838 bhi.n 80098b6 8009844: a201 add r2, pc, #4 @ (adr r2, 800984c ) 8009846: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800984a: bf00 nop 800984c: 0800985d .word 0x0800985d 8009850: 08009863 .word 0x08009863 8009854: 0800985d .word 0x0800985d 8009858: 08009875 .word 0x08009875 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 800985c: 2301 movs r3, #1 800985e: 73fb strb r3, [r7, #15] break; 8009860: e030 b.n 80098c4 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8009862: 687b ldr r3, [r7, #4] 8009864: 6adb ldr r3, [r3, #44] @ 0x2c 8009866: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800986a: 2b00 cmp r3, #0 800986c: d025 beq.n 80098ba { status = HAL_ERROR; 800986e: 2301 movs r3, #1 8009870: 73fb strb r3, [r7, #15] } break; 8009872: e022 b.n 80098ba case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8009874: 687b ldr r3, [r7, #4] 8009876: 6adb ldr r3, [r3, #44] @ 0x2c 8009878: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800987c: d11f bne.n 80098be { status = HAL_ERROR; 800987e: 2301 movs r3, #1 8009880: 73fb strb r3, [r7, #15] } break; 8009882: e01c b.n 80098be } /* Memory Data size equal to Word */ else { switch (hdma->Init.FIFOThreshold) 8009884: 687b ldr r3, [r7, #4] 8009886: 6a9b ldr r3, [r3, #40] @ 0x28 8009888: 2b02 cmp r3, #2 800988a: d902 bls.n 8009892 800988c: 2b03 cmp r3, #3 800988e: d003 beq.n 8009898 status = HAL_ERROR; } break; default: break; 8009890: e018 b.n 80098c4 status = HAL_ERROR; 8009892: 2301 movs r3, #1 8009894: 73fb strb r3, [r7, #15] break; 8009896: e015 b.n 80098c4 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8009898: 687b ldr r3, [r7, #4] 800989a: 6adb ldr r3, [r3, #44] @ 0x2c 800989c: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80098a0: 2b00 cmp r3, #0 80098a2: d00e beq.n 80098c2 status = HAL_ERROR; 80098a4: 2301 movs r3, #1 80098a6: 73fb strb r3, [r7, #15] break; 80098a8: e00b b.n 80098c2 break; 80098aa: bf00 nop 80098ac: e00a b.n 80098c4 break; 80098ae: bf00 nop 80098b0: e008 b.n 80098c4 break; 80098b2: bf00 nop 80098b4: e006 b.n 80098c4 break; 80098b6: bf00 nop 80098b8: e004 b.n 80098c4 break; 80098ba: bf00 nop 80098bc: e002 b.n 80098c4 break; 80098be: bf00 nop 80098c0: e000 b.n 80098c4 break; 80098c2: bf00 nop } } return status; 80098c4: 7bfb ldrb r3, [r7, #15] } 80098c6: 4618 mov r0, r3 80098c8: 3714 adds r7, #20 80098ca: 46bd mov sp, r7 80098cc: f85d 7b04 ldr.w r7, [sp], #4 80098d0: 4770 bx lr 80098d2: bf00 nop 080098d4 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 80098d4: b480 push {r7} 80098d6: b085 sub sp, #20 80098d8: af00 add r7, sp, #0 80098da: 6078 str r0, [r7, #4] uint32_t stream_number; uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); 80098dc: 687b ldr r3, [r7, #4] 80098de: 681b ldr r3, [r3, #0] 80098e0: 60bb str r3, [r7, #8] if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 80098e2: 687b ldr r3, [r7, #4] 80098e4: 681b ldr r3, [r3, #0] 80098e6: 4a38 ldr r2, [pc, #224] @ (80099c8 ) 80098e8: 4293 cmp r3, r2 80098ea: d022 beq.n 8009932 80098ec: 687b ldr r3, [r7, #4] 80098ee: 681b ldr r3, [r3, #0] 80098f0: 4a36 ldr r2, [pc, #216] @ (80099cc ) 80098f2: 4293 cmp r3, r2 80098f4: d01d beq.n 8009932 80098f6: 687b ldr r3, [r7, #4] 80098f8: 681b ldr r3, [r3, #0] 80098fa: 4a35 ldr r2, [pc, #212] @ (80099d0 ) 80098fc: 4293 cmp r3, r2 80098fe: d018 beq.n 8009932 8009900: 687b ldr r3, [r7, #4] 8009902: 681b ldr r3, [r3, #0] 8009904: 4a33 ldr r2, [pc, #204] @ (80099d4 ) 8009906: 4293 cmp r3, r2 8009908: d013 beq.n 8009932 800990a: 687b ldr r3, [r7, #4] 800990c: 681b ldr r3, [r3, #0] 800990e: 4a32 ldr r2, [pc, #200] @ (80099d8 ) 8009910: 4293 cmp r3, r2 8009912: d00e beq.n 8009932 8009914: 687b ldr r3, [r7, #4] 8009916: 681b ldr r3, [r3, #0] 8009918: 4a30 ldr r2, [pc, #192] @ (80099dc ) 800991a: 4293 cmp r3, r2 800991c: d009 beq.n 8009932 800991e: 687b ldr r3, [r7, #4] 8009920: 681b ldr r3, [r3, #0] 8009922: 4a2f ldr r2, [pc, #188] @ (80099e0 ) 8009924: 4293 cmp r3, r2 8009926: d004 beq.n 8009932 8009928: 687b ldr r3, [r7, #4] 800992a: 681b ldr r3, [r3, #0] 800992c: 4a2d ldr r2, [pc, #180] @ (80099e4 ) 800992e: 4293 cmp r3, r2 8009930: d101 bne.n 8009936 8009932: 2301 movs r3, #1 8009934: e000 b.n 8009938 8009936: 2300 movs r3, #0 8009938: 2b00 cmp r3, #0 800993a: d01a beq.n 8009972 { /* BDMA Channels are connected to DMAMUX2 channels */ stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; 800993c: 687b ldr r3, [r7, #4] 800993e: 681b ldr r3, [r3, #0] 8009940: b2db uxtb r3, r3 8009942: 3b08 subs r3, #8 8009944: 4a28 ldr r2, [pc, #160] @ (80099e8 ) 8009946: fba2 2303 umull r2, r3, r2, r3 800994a: 091b lsrs r3, r3, #4 800994c: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); 800994e: 68fa ldr r2, [r7, #12] 8009950: 4b26 ldr r3, [pc, #152] @ (80099ec ) 8009952: 4413 add r3, r2 8009954: 009b lsls r3, r3, #2 8009956: 461a mov r2, r3 8009958: 687b ldr r3, [r7, #4] 800995a: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; 800995c: 687b ldr r3, [r7, #4] 800995e: 4a24 ldr r2, [pc, #144] @ (80099f0 ) 8009960: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 8009962: 68fb ldr r3, [r7, #12] 8009964: f003 031f and.w r3, r3, #31 8009968: 2201 movs r2, #1 800996a: 409a lsls r2, r3 800996c: 687b ldr r3, [r7, #4] 800996e: 669a str r2, [r3, #104] @ 0x68 } hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); } } 8009970: e024 b.n 80099bc stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 8009972: 687b ldr r3, [r7, #4] 8009974: 681b ldr r3, [r3, #0] 8009976: b2db uxtb r3, r3 8009978: 3b10 subs r3, #16 800997a: 4a1e ldr r2, [pc, #120] @ (80099f4 ) 800997c: fba2 2303 umull r2, r3, r2, r3 8009980: 091b lsrs r3, r3, #4 8009982: 60fb str r3, [r7, #12] if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ 8009984: 68bb ldr r3, [r7, #8] 8009986: 4a1c ldr r2, [pc, #112] @ (80099f8 ) 8009988: 4293 cmp r3, r2 800998a: d806 bhi.n 800999a 800998c: 68bb ldr r3, [r7, #8] 800998e: 4a1b ldr r2, [pc, #108] @ (80099fc ) 8009990: 4293 cmp r3, r2 8009992: d902 bls.n 800999a stream_number += 8U; 8009994: 68fb ldr r3, [r7, #12] 8009996: 3308 adds r3, #8 8009998: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); 800999a: 68fa ldr r2, [r7, #12] 800999c: 4b18 ldr r3, [pc, #96] @ (8009a00 ) 800999e: 4413 add r3, r2 80099a0: 009b lsls r3, r3, #2 80099a2: 461a mov r2, r3 80099a4: 687b ldr r3, [r7, #4] 80099a6: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 80099a8: 687b ldr r3, [r7, #4] 80099aa: 4a16 ldr r2, [pc, #88] @ (8009a04 ) 80099ac: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 80099ae: 68fb ldr r3, [r7, #12] 80099b0: f003 031f and.w r3, r3, #31 80099b4: 2201 movs r2, #1 80099b6: 409a lsls r2, r3 80099b8: 687b ldr r3, [r7, #4] 80099ba: 669a str r2, [r3, #104] @ 0x68 } 80099bc: bf00 nop 80099be: 3714 adds r7, #20 80099c0: 46bd mov sp, r7 80099c2: f85d 7b04 ldr.w r7, [sp], #4 80099c6: 4770 bx lr 80099c8: 58025408 .word 0x58025408 80099cc: 5802541c .word 0x5802541c 80099d0: 58025430 .word 0x58025430 80099d4: 58025444 .word 0x58025444 80099d8: 58025458 .word 0x58025458 80099dc: 5802546c .word 0x5802546c 80099e0: 58025480 .word 0x58025480 80099e4: 58025494 .word 0x58025494 80099e8: cccccccd .word 0xcccccccd 80099ec: 16009600 .word 0x16009600 80099f0: 58025880 .word 0x58025880 80099f4: aaaaaaab .word 0xaaaaaaab 80099f8: 400204b8 .word 0x400204b8 80099fc: 4002040f .word 0x4002040f 8009a00: 10008200 .word 0x10008200 8009a04: 40020880 .word 0x40020880 08009a08 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 8009a08: b480 push {r7} 8009a0a: b085 sub sp, #20 8009a0c: af00 add r7, sp, #0 8009a0e: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 8009a10: 687b ldr r3, [r7, #4] 8009a12: 685b ldr r3, [r3, #4] 8009a14: b2db uxtb r3, r3 8009a16: 60fb str r3, [r7, #12] if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) 8009a18: 68fb ldr r3, [r7, #12] 8009a1a: 2b00 cmp r3, #0 8009a1c: d04a beq.n 8009ab4 8009a1e: 68fb ldr r3, [r7, #12] 8009a20: 2b08 cmp r3, #8 8009a22: d847 bhi.n 8009ab4 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 8009a24: 687b ldr r3, [r7, #4] 8009a26: 681b ldr r3, [r3, #0] 8009a28: 4a25 ldr r2, [pc, #148] @ (8009ac0 ) 8009a2a: 4293 cmp r3, r2 8009a2c: d022 beq.n 8009a74 8009a2e: 687b ldr r3, [r7, #4] 8009a30: 681b ldr r3, [r3, #0] 8009a32: 4a24 ldr r2, [pc, #144] @ (8009ac4 ) 8009a34: 4293 cmp r3, r2 8009a36: d01d beq.n 8009a74 8009a38: 687b ldr r3, [r7, #4] 8009a3a: 681b ldr r3, [r3, #0] 8009a3c: 4a22 ldr r2, [pc, #136] @ (8009ac8 ) 8009a3e: 4293 cmp r3, r2 8009a40: d018 beq.n 8009a74 8009a42: 687b ldr r3, [r7, #4] 8009a44: 681b ldr r3, [r3, #0] 8009a46: 4a21 ldr r2, [pc, #132] @ (8009acc ) 8009a48: 4293 cmp r3, r2 8009a4a: d013 beq.n 8009a74 8009a4c: 687b ldr r3, [r7, #4] 8009a4e: 681b ldr r3, [r3, #0] 8009a50: 4a1f ldr r2, [pc, #124] @ (8009ad0 ) 8009a52: 4293 cmp r3, r2 8009a54: d00e beq.n 8009a74 8009a56: 687b ldr r3, [r7, #4] 8009a58: 681b ldr r3, [r3, #0] 8009a5a: 4a1e ldr r2, [pc, #120] @ (8009ad4 ) 8009a5c: 4293 cmp r3, r2 8009a5e: d009 beq.n 8009a74 8009a60: 687b ldr r3, [r7, #4] 8009a62: 681b ldr r3, [r3, #0] 8009a64: 4a1c ldr r2, [pc, #112] @ (8009ad8 ) 8009a66: 4293 cmp r3, r2 8009a68: d004 beq.n 8009a74 8009a6a: 687b ldr r3, [r7, #4] 8009a6c: 681b ldr r3, [r3, #0] 8009a6e: 4a1b ldr r2, [pc, #108] @ (8009adc ) 8009a70: 4293 cmp r3, r2 8009a72: d101 bne.n 8009a78 8009a74: 2301 movs r3, #1 8009a76: e000 b.n 8009a7a 8009a78: 2300 movs r3, #0 8009a7a: 2b00 cmp r3, #0 8009a7c: d00a beq.n 8009a94 { /* BDMA Channels are connected to DMAMUX2 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); 8009a7e: 68fa ldr r2, [r7, #12] 8009a80: 4b17 ldr r3, [pc, #92] @ (8009ae0 ) 8009a82: 4413 add r3, r2 8009a84: 009b lsls r3, r3, #2 8009a86: 461a mov r2, r3 8009a88: 687b ldr r3, [r7, #4] 8009a8a: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; 8009a8c: 687b ldr r3, [r7, #4] 8009a8e: 4a15 ldr r2, [pc, #84] @ (8009ae4 ) 8009a90: 671a str r2, [r3, #112] @ 0x70 8009a92: e009 b.n 8009aa8 } else { /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 8009a94: 68fa ldr r2, [r7, #12] 8009a96: 4b14 ldr r3, [pc, #80] @ (8009ae8 ) 8009a98: 4413 add r3, r2 8009a9a: 009b lsls r3, r3, #2 8009a9c: 461a mov r2, r3 8009a9e: 687b ldr r3, [r7, #4] 8009aa0: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 8009aa2: 687b ldr r3, [r7, #4] 8009aa4: 4a11 ldr r2, [pc, #68] @ (8009aec ) 8009aa6: 671a str r2, [r3, #112] @ 0x70 } hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); 8009aa8: 68fb ldr r3, [r7, #12] 8009aaa: 3b01 subs r3, #1 8009aac: 2201 movs r2, #1 8009aae: 409a lsls r2, r3 8009ab0: 687b ldr r3, [r7, #4] 8009ab2: 675a str r2, [r3, #116] @ 0x74 } } 8009ab4: bf00 nop 8009ab6: 3714 adds r7, #20 8009ab8: 46bd mov sp, r7 8009aba: f85d 7b04 ldr.w r7, [sp], #4 8009abe: 4770 bx lr 8009ac0: 58025408 .word 0x58025408 8009ac4: 5802541c .word 0x5802541c 8009ac8: 58025430 .word 0x58025430 8009acc: 58025444 .word 0x58025444 8009ad0: 58025458 .word 0x58025458 8009ad4: 5802546c .word 0x5802546c 8009ad8: 58025480 .word 0x58025480 8009adc: 58025494 .word 0x58025494 8009ae0: 1600963f .word 0x1600963f 8009ae4: 58025940 .word 0x58025940 8009ae8: 1000823f .word 0x1000823f 8009aec: 40020940 .word 0x40020940 08009af0 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8009af0: b480 push {r7} 8009af2: b089 sub sp, #36 @ 0x24 8009af4: af00 add r7, sp, #0 8009af6: 6078 str r0, [r7, #4] 8009af8: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 8009afa: 2300 movs r3, #0 8009afc: 61fb str r3, [r7, #28] EXTI_Core_TypeDef *EXTI_CurrentCPU; #if defined(DUAL_CORE) && defined(CORE_CM4) EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ #else EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ 8009afe: 4b89 ldr r3, [pc, #548] @ (8009d24 ) 8009b00: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 8009b02: e194 b.n 8009e2e { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 8009b04: 683b ldr r3, [r7, #0] 8009b06: 681a ldr r2, [r3, #0] 8009b08: 2101 movs r1, #1 8009b0a: 69fb ldr r3, [r7, #28] 8009b0c: fa01 f303 lsl.w r3, r1, r3 8009b10: 4013 ands r3, r2 8009b12: 613b str r3, [r7, #16] if (iocurrent != 0x00U) 8009b14: 693b ldr r3, [r7, #16] 8009b16: 2b00 cmp r3, #0 8009b18: f000 8186 beq.w 8009e28 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8009b1c: 683b ldr r3, [r7, #0] 8009b1e: 685b ldr r3, [r3, #4] 8009b20: f003 0303 and.w r3, r3, #3 8009b24: 2b01 cmp r3, #1 8009b26: d005 beq.n 8009b34 8009b28: 683b ldr r3, [r7, #0] 8009b2a: 685b ldr r3, [r3, #4] 8009b2c: f003 0303 and.w r3, r3, #3 8009b30: 2b02 cmp r3, #2 8009b32: d130 bne.n 8009b96 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8009b34: 687b ldr r3, [r7, #4] 8009b36: 689b ldr r3, [r3, #8] 8009b38: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8009b3a: 69fb ldr r3, [r7, #28] 8009b3c: 005b lsls r3, r3, #1 8009b3e: 2203 movs r2, #3 8009b40: fa02 f303 lsl.w r3, r2, r3 8009b44: 43db mvns r3, r3 8009b46: 69ba ldr r2, [r7, #24] 8009b48: 4013 ands r3, r2 8009b4a: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 8009b4c: 683b ldr r3, [r7, #0] 8009b4e: 68da ldr r2, [r3, #12] 8009b50: 69fb ldr r3, [r7, #28] 8009b52: 005b lsls r3, r3, #1 8009b54: fa02 f303 lsl.w r3, r2, r3 8009b58: 69ba ldr r2, [r7, #24] 8009b5a: 4313 orrs r3, r2 8009b5c: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8009b5e: 687b ldr r3, [r7, #4] 8009b60: 69ba ldr r2, [r7, #24] 8009b62: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8009b64: 687b ldr r3, [r7, #4] 8009b66: 685b ldr r3, [r3, #4] 8009b68: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT0 << position) ; 8009b6a: 2201 movs r2, #1 8009b6c: 69fb ldr r3, [r7, #28] 8009b6e: fa02 f303 lsl.w r3, r2, r3 8009b72: 43db mvns r3, r3 8009b74: 69ba ldr r2, [r7, #24] 8009b76: 4013 ands r3, r2 8009b78: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8009b7a: 683b ldr r3, [r7, #0] 8009b7c: 685b ldr r3, [r3, #4] 8009b7e: 091b lsrs r3, r3, #4 8009b80: f003 0201 and.w r2, r3, #1 8009b84: 69fb ldr r3, [r7, #28] 8009b86: fa02 f303 lsl.w r3, r2, r3 8009b8a: 69ba ldr r2, [r7, #24] 8009b8c: 4313 orrs r3, r2 8009b8e: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8009b90: 687b ldr r3, [r7, #4] 8009b92: 69ba ldr r2, [r7, #24] 8009b94: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8009b96: 683b ldr r3, [r7, #0] 8009b98: 685b ldr r3, [r3, #4] 8009b9a: f003 0303 and.w r3, r3, #3 8009b9e: 2b03 cmp r3, #3 8009ba0: d017 beq.n 8009bd2 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8009ba2: 687b ldr r3, [r7, #4] 8009ba4: 68db ldr r3, [r3, #12] 8009ba6: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8009ba8: 69fb ldr r3, [r7, #28] 8009baa: 005b lsls r3, r3, #1 8009bac: 2203 movs r2, #3 8009bae: fa02 f303 lsl.w r3, r2, r3 8009bb2: 43db mvns r3, r3 8009bb4: 69ba ldr r2, [r7, #24] 8009bb6: 4013 ands r3, r2 8009bb8: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8009bba: 683b ldr r3, [r7, #0] 8009bbc: 689a ldr r2, [r3, #8] 8009bbe: 69fb ldr r3, [r7, #28] 8009bc0: 005b lsls r3, r3, #1 8009bc2: fa02 f303 lsl.w r3, r2, r3 8009bc6: 69ba ldr r2, [r7, #24] 8009bc8: 4313 orrs r3, r2 8009bca: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 8009bcc: 687b ldr r3, [r7, #4] 8009bce: 69ba ldr r2, [r7, #24] 8009bd0: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8009bd2: 683b ldr r3, [r7, #0] 8009bd4: 685b ldr r3, [r3, #4] 8009bd6: f003 0303 and.w r3, r3, #3 8009bda: 2b02 cmp r3, #2 8009bdc: d123 bne.n 8009c26 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8009bde: 69fb ldr r3, [r7, #28] 8009be0: 08da lsrs r2, r3, #3 8009be2: 687b ldr r3, [r7, #4] 8009be4: 3208 adds r2, #8 8009be6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009bea: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 8009bec: 69fb ldr r3, [r7, #28] 8009bee: f003 0307 and.w r3, r3, #7 8009bf2: 009b lsls r3, r3, #2 8009bf4: 220f movs r2, #15 8009bf6: fa02 f303 lsl.w r3, r2, r3 8009bfa: 43db mvns r3, r3 8009bfc: 69ba ldr r2, [r7, #24] 8009bfe: 4013 ands r3, r2 8009c00: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 8009c02: 683b ldr r3, [r7, #0] 8009c04: 691a ldr r2, [r3, #16] 8009c06: 69fb ldr r3, [r7, #28] 8009c08: f003 0307 and.w r3, r3, #7 8009c0c: 009b lsls r3, r3, #2 8009c0e: fa02 f303 lsl.w r3, r2, r3 8009c12: 69ba ldr r2, [r7, #24] 8009c14: 4313 orrs r3, r2 8009c16: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8009c18: 69fb ldr r3, [r7, #28] 8009c1a: 08da lsrs r2, r3, #3 8009c1c: 687b ldr r3, [r7, #4] 8009c1e: 3208 adds r2, #8 8009c20: 69b9 ldr r1, [r7, #24] 8009c22: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8009c26: 687b ldr r3, [r7, #4] 8009c28: 681b ldr r3, [r3, #0] 8009c2a: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 8009c2c: 69fb ldr r3, [r7, #28] 8009c2e: 005b lsls r3, r3, #1 8009c30: 2203 movs r2, #3 8009c32: fa02 f303 lsl.w r3, r2, r3 8009c36: 43db mvns r3, r3 8009c38: 69ba ldr r2, [r7, #24] 8009c3a: 4013 ands r3, r2 8009c3c: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8009c3e: 683b ldr r3, [r7, #0] 8009c40: 685b ldr r3, [r3, #4] 8009c42: f003 0203 and.w r2, r3, #3 8009c46: 69fb ldr r3, [r7, #28] 8009c48: 005b lsls r3, r3, #1 8009c4a: fa02 f303 lsl.w r3, r2, r3 8009c4e: 69ba ldr r2, [r7, #24] 8009c50: 4313 orrs r3, r2 8009c52: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8009c54: 687b ldr r3, [r7, #4] 8009c56: 69ba ldr r2, [r7, #24] 8009c58: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8009c5a: 683b ldr r3, [r7, #0] 8009c5c: 685b ldr r3, [r3, #4] 8009c5e: f403 3340 and.w r3, r3, #196608 @ 0x30000 8009c62: 2b00 cmp r3, #0 8009c64: f000 80e0 beq.w 8009e28 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8009c68: 4b2f ldr r3, [pc, #188] @ (8009d28 ) 8009c6a: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8009c6e: 4a2e ldr r2, [pc, #184] @ (8009d28 ) 8009c70: f043 0302 orr.w r3, r3, #2 8009c74: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8009c78: 4b2b ldr r3, [pc, #172] @ (8009d28 ) 8009c7a: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8009c7e: f003 0302 and.w r3, r3, #2 8009c82: 60fb str r3, [r7, #12] 8009c84: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8009c86: 4a29 ldr r2, [pc, #164] @ (8009d2c ) 8009c88: 69fb ldr r3, [r7, #28] 8009c8a: 089b lsrs r3, r3, #2 8009c8c: 3302 adds r3, #2 8009c8e: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8009c92: 61bb str r3, [r7, #24] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8009c94: 69fb ldr r3, [r7, #28] 8009c96: f003 0303 and.w r3, r3, #3 8009c9a: 009b lsls r3, r3, #2 8009c9c: 220f movs r2, #15 8009c9e: fa02 f303 lsl.w r3, r2, r3 8009ca2: 43db mvns r3, r3 8009ca4: 69ba ldr r2, [r7, #24] 8009ca6: 4013 ands r3, r2 8009ca8: 61bb str r3, [r7, #24] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8009caa: 687b ldr r3, [r7, #4] 8009cac: 4a20 ldr r2, [pc, #128] @ (8009d30 ) 8009cae: 4293 cmp r3, r2 8009cb0: d052 beq.n 8009d58 8009cb2: 687b ldr r3, [r7, #4] 8009cb4: 4a1f ldr r2, [pc, #124] @ (8009d34 ) 8009cb6: 4293 cmp r3, r2 8009cb8: d031 beq.n 8009d1e 8009cba: 687b ldr r3, [r7, #4] 8009cbc: 4a1e ldr r2, [pc, #120] @ (8009d38 ) 8009cbe: 4293 cmp r3, r2 8009cc0: d02b beq.n 8009d1a 8009cc2: 687b ldr r3, [r7, #4] 8009cc4: 4a1d ldr r2, [pc, #116] @ (8009d3c ) 8009cc6: 4293 cmp r3, r2 8009cc8: d025 beq.n 8009d16 8009cca: 687b ldr r3, [r7, #4] 8009ccc: 4a1c ldr r2, [pc, #112] @ (8009d40 ) 8009cce: 4293 cmp r3, r2 8009cd0: d01f beq.n 8009d12 8009cd2: 687b ldr r3, [r7, #4] 8009cd4: 4a1b ldr r2, [pc, #108] @ (8009d44 ) 8009cd6: 4293 cmp r3, r2 8009cd8: d019 beq.n 8009d0e 8009cda: 687b ldr r3, [r7, #4] 8009cdc: 4a1a ldr r2, [pc, #104] @ (8009d48 ) 8009cde: 4293 cmp r3, r2 8009ce0: d013 beq.n 8009d0a 8009ce2: 687b ldr r3, [r7, #4] 8009ce4: 4a19 ldr r2, [pc, #100] @ (8009d4c ) 8009ce6: 4293 cmp r3, r2 8009ce8: d00d beq.n 8009d06 8009cea: 687b ldr r3, [r7, #4] 8009cec: 4a18 ldr r2, [pc, #96] @ (8009d50 ) 8009cee: 4293 cmp r3, r2 8009cf0: d007 beq.n 8009d02 8009cf2: 687b ldr r3, [r7, #4] 8009cf4: 4a17 ldr r2, [pc, #92] @ (8009d54 ) 8009cf6: 4293 cmp r3, r2 8009cf8: d101 bne.n 8009cfe 8009cfa: 2309 movs r3, #9 8009cfc: e02d b.n 8009d5a 8009cfe: 230a movs r3, #10 8009d00: e02b b.n 8009d5a 8009d02: 2308 movs r3, #8 8009d04: e029 b.n 8009d5a 8009d06: 2307 movs r3, #7 8009d08: e027 b.n 8009d5a 8009d0a: 2306 movs r3, #6 8009d0c: e025 b.n 8009d5a 8009d0e: 2305 movs r3, #5 8009d10: e023 b.n 8009d5a 8009d12: 2304 movs r3, #4 8009d14: e021 b.n 8009d5a 8009d16: 2303 movs r3, #3 8009d18: e01f b.n 8009d5a 8009d1a: 2302 movs r3, #2 8009d1c: e01d b.n 8009d5a 8009d1e: 2301 movs r3, #1 8009d20: e01b b.n 8009d5a 8009d22: bf00 nop 8009d24: 58000080 .word 0x58000080 8009d28: 58024400 .word 0x58024400 8009d2c: 58000400 .word 0x58000400 8009d30: 58020000 .word 0x58020000 8009d34: 58020400 .word 0x58020400 8009d38: 58020800 .word 0x58020800 8009d3c: 58020c00 .word 0x58020c00 8009d40: 58021000 .word 0x58021000 8009d44: 58021400 .word 0x58021400 8009d48: 58021800 .word 0x58021800 8009d4c: 58021c00 .word 0x58021c00 8009d50: 58022000 .word 0x58022000 8009d54: 58022400 .word 0x58022400 8009d58: 2300 movs r3, #0 8009d5a: 69fa ldr r2, [r7, #28] 8009d5c: f002 0203 and.w r2, r2, #3 8009d60: 0092 lsls r2, r2, #2 8009d62: 4093 lsls r3, r2 8009d64: 69ba ldr r2, [r7, #24] 8009d66: 4313 orrs r3, r2 8009d68: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 8009d6a: 4938 ldr r1, [pc, #224] @ (8009e4c ) 8009d6c: 69fb ldr r3, [r7, #28] 8009d6e: 089b lsrs r3, r3, #2 8009d70: 3302 adds r3, #2 8009d72: 69ba ldr r2, [r7, #24] 8009d74: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8009d78: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8009d7c: 681b ldr r3, [r3, #0] 8009d7e: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8009d80: 693b ldr r3, [r7, #16] 8009d82: 43db mvns r3, r3 8009d84: 69ba ldr r2, [r7, #24] 8009d86: 4013 ands r3, r2 8009d88: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8009d8a: 683b ldr r3, [r7, #0] 8009d8c: 685b ldr r3, [r3, #4] 8009d8e: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8009d92: 2b00 cmp r3, #0 8009d94: d003 beq.n 8009d9e { temp |= iocurrent; 8009d96: 69ba ldr r2, [r7, #24] 8009d98: 693b ldr r3, [r7, #16] 8009d9a: 4313 orrs r3, r2 8009d9c: 61bb str r3, [r7, #24] } EXTI->RTSR1 = temp; 8009d9e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8009da2: 69bb ldr r3, [r7, #24] 8009da4: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 8009da6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8009daa: 685b ldr r3, [r3, #4] 8009dac: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8009dae: 693b ldr r3, [r7, #16] 8009db0: 43db mvns r3, r3 8009db2: 69ba ldr r2, [r7, #24] 8009db4: 4013 ands r3, r2 8009db6: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8009db8: 683b ldr r3, [r7, #0] 8009dba: 685b ldr r3, [r3, #4] 8009dbc: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8009dc0: 2b00 cmp r3, #0 8009dc2: d003 beq.n 8009dcc { temp |= iocurrent; 8009dc4: 69ba ldr r2, [r7, #24] 8009dc6: 693b ldr r3, [r7, #16] 8009dc8: 4313 orrs r3, r2 8009dca: 61bb str r3, [r7, #24] } EXTI->FTSR1 = temp; 8009dcc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8009dd0: 69bb ldr r3, [r7, #24] 8009dd2: 6053 str r3, [r2, #4] temp = EXTI_CurrentCPU->EMR1; 8009dd4: 697b ldr r3, [r7, #20] 8009dd6: 685b ldr r3, [r3, #4] 8009dd8: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8009dda: 693b ldr r3, [r7, #16] 8009ddc: 43db mvns r3, r3 8009dde: 69ba ldr r2, [r7, #24] 8009de0: 4013 ands r3, r2 8009de2: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8009de4: 683b ldr r3, [r7, #0] 8009de6: 685b ldr r3, [r3, #4] 8009de8: f403 3300 and.w r3, r3, #131072 @ 0x20000 8009dec: 2b00 cmp r3, #0 8009dee: d003 beq.n 8009df8 { temp |= iocurrent; 8009df0: 69ba ldr r2, [r7, #24] 8009df2: 693b ldr r3, [r7, #16] 8009df4: 4313 orrs r3, r2 8009df6: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->EMR1 = temp; 8009df8: 697b ldr r3, [r7, #20] 8009dfa: 69ba ldr r2, [r7, #24] 8009dfc: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 8009dfe: 697b ldr r3, [r7, #20] 8009e00: 681b ldr r3, [r3, #0] 8009e02: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8009e04: 693b ldr r3, [r7, #16] 8009e06: 43db mvns r3, r3 8009e08: 69ba ldr r2, [r7, #24] 8009e0a: 4013 ands r3, r2 8009e0c: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8009e0e: 683b ldr r3, [r7, #0] 8009e10: 685b ldr r3, [r3, #4] 8009e12: f403 3380 and.w r3, r3, #65536 @ 0x10000 8009e16: 2b00 cmp r3, #0 8009e18: d003 beq.n 8009e22 { temp |= iocurrent; 8009e1a: 69ba ldr r2, [r7, #24] 8009e1c: 693b ldr r3, [r7, #16] 8009e1e: 4313 orrs r3, r2 8009e20: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->IMR1 = temp; 8009e22: 697b ldr r3, [r7, #20] 8009e24: 69ba ldr r2, [r7, #24] 8009e26: 601a str r2, [r3, #0] } } position++; 8009e28: 69fb ldr r3, [r7, #28] 8009e2a: 3301 adds r3, #1 8009e2c: 61fb str r3, [r7, #28] while (((GPIO_Init->Pin) >> position) != 0x00U) 8009e2e: 683b ldr r3, [r7, #0] 8009e30: 681a ldr r2, [r3, #0] 8009e32: 69fb ldr r3, [r7, #28] 8009e34: fa22 f303 lsr.w r3, r2, r3 8009e38: 2b00 cmp r3, #0 8009e3a: f47f ae63 bne.w 8009b04 } } 8009e3e: bf00 nop 8009e40: bf00 nop 8009e42: 3724 adds r7, #36 @ 0x24 8009e44: 46bd mov sp, r7 8009e46: f85d 7b04 ldr.w r7, [sp], #4 8009e4a: 4770 bx lr 8009e4c: 58000400 .word 0x58000400 08009e50 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8009e50: b480 push {r7} 8009e52: b085 sub sp, #20 8009e54: af00 add r7, sp, #0 8009e56: 6078 str r0, [r7, #4] 8009e58: 460b mov r3, r1 8009e5a: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0x00U) 8009e5c: 687b ldr r3, [r7, #4] 8009e5e: 691a ldr r2, [r3, #16] 8009e60: 887b ldrh r3, [r7, #2] 8009e62: 4013 ands r3, r2 8009e64: 2b00 cmp r3, #0 8009e66: d002 beq.n 8009e6e { bitstatus = GPIO_PIN_SET; 8009e68: 2301 movs r3, #1 8009e6a: 73fb strb r3, [r7, #15] 8009e6c: e001 b.n 8009e72 } else { bitstatus = GPIO_PIN_RESET; 8009e6e: 2300 movs r3, #0 8009e70: 73fb strb r3, [r7, #15] } return bitstatus; 8009e72: 7bfb ldrb r3, [r7, #15] } 8009e74: 4618 mov r0, r3 8009e76: 3714 adds r7, #20 8009e78: 46bd mov sp, r7 8009e7a: f85d 7b04 ldr.w r7, [sp], #4 8009e7e: 4770 bx lr 08009e80 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8009e80: b480 push {r7} 8009e82: b083 sub sp, #12 8009e84: af00 add r7, sp, #0 8009e86: 6078 str r0, [r7, #4] 8009e88: 460b mov r3, r1 8009e8a: 807b strh r3, [r7, #2] 8009e8c: 4613 mov r3, r2 8009e8e: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8009e90: 787b ldrb r3, [r7, #1] 8009e92: 2b00 cmp r3, #0 8009e94: d003 beq.n 8009e9e { GPIOx->BSRR = GPIO_Pin; 8009e96: 887a ldrh r2, [r7, #2] 8009e98: 687b ldr r3, [r7, #4] 8009e9a: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; } } 8009e9c: e003 b.n 8009ea6 GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 8009e9e: 887b ldrh r3, [r7, #2] 8009ea0: 041a lsls r2, r3, #16 8009ea2: 687b ldr r3, [r7, #4] 8009ea4: 619a str r2, [r3, #24] } 8009ea6: bf00 nop 8009ea8: 370c adds r7, #12 8009eaa: 46bd mov sp, r7 8009eac: f85d 7b04 ldr.w r7, [sp], #4 8009eb0: 4770 bx lr 08009eb2 : * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral. * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8009eb2: b480 push {r7} 8009eb4: b085 sub sp, #20 8009eb6: af00 add r7, sp, #0 8009eb8: 6078 str r0, [r7, #4] 8009eba: 460b mov r3, r1 8009ebc: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; 8009ebe: 687b ldr r3, [r7, #4] 8009ec0: 695b ldr r3, [r3, #20] 8009ec2: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 8009ec4: 887a ldrh r2, [r7, #2] 8009ec6: 68fb ldr r3, [r7, #12] 8009ec8: 4013 ands r3, r2 8009eca: 041a lsls r2, r3, #16 8009ecc: 68fb ldr r3, [r7, #12] 8009ece: 43d9 mvns r1, r3 8009ed0: 887b ldrh r3, [r7, #2] 8009ed2: 400b ands r3, r1 8009ed4: 431a orrs r2, r3 8009ed6: 687b ldr r3, [r7, #4] 8009ed8: 619a str r2, [r3, #24] } 8009eda: bf00 nop 8009edc: 3714 adds r7, #20 8009ede: 46bd mov sp, r7 8009ee0: f85d 7b04 ldr.w r7, [sp], #4 8009ee4: 4770 bx lr 08009ee6 : * @brief Handle EXTI interrupt request. * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 8009ee6: b580 push {r7, lr} 8009ee8: b082 sub sp, #8 8009eea: af00 add r7, sp, #0 8009eec: 4603 mov r3, r0 8009eee: 80fb strh r3, [r7, #6] __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); } #else /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U) 8009ef0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8009ef4: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 8009ef8: 88fb ldrh r3, [r7, #6] 8009efa: 4013 ands r3, r2 8009efc: 2b00 cmp r3, #0 8009efe: d008 beq.n 8009f12 { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 8009f00: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8009f04: 88fb ldrh r3, [r7, #6] 8009f06: f8c2 3088 str.w r3, [r2, #136] @ 0x88 HAL_GPIO_EXTI_Callback(GPIO_Pin); 8009f0a: 88fb ldrh r3, [r7, #6] 8009f0c: 4618 mov r0, r3 8009f0e: f7f6 fbcd bl 80006ac } #endif } 8009f12: bf00 nop 8009f14: 3708 adds r7, #8 8009f16: 46bd mov sp, r7 8009f18: bd80 pop {r7, pc} ... 08009f1c : * driver. All combination are allowed: wake up only Cortex-M7, wake up * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4. * @retval None. */ void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD) { 8009f1c: b480 push {r7} 8009f1e: b083 sub sp, #12 8009f20: af00 add r7, sp, #0 8009f22: 6078 str r0, [r7, #4] /* Check the PVD configuration parameter */ if (sConfigPVD == NULL) 8009f24: 687b ldr r3, [r7, #4] 8009f26: 2b00 cmp r3, #0 8009f28: d069 beq.n 8009ffe /* Check the parameters */ assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel)); assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode)); /* Set PLS[7:5] bits according to PVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); 8009f2a: 4b38 ldr r3, [pc, #224] @ (800a00c ) 8009f2c: 681b ldr r3, [r3, #0] 8009f2e: f023 02e0 bic.w r2, r3, #224 @ 0xe0 8009f32: 687b ldr r3, [r7, #4] 8009f34: 681b ldr r3, [r3, #0] 8009f36: 4935 ldr r1, [pc, #212] @ (800a00c ) 8009f38: 4313 orrs r3, r2 8009f3a: 600b str r3, [r1, #0] /* Clear previous config */ #if !defined (DUAL_CORE) __HAL_PWR_PVD_EXTI_DISABLE_EVENT (); 8009f3c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8009f40: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8009f44: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8009f48: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8009f4c: f8c2 3084 str.w r3, [r2, #132] @ 0x84 __HAL_PWR_PVD_EXTI_DISABLE_IT (); 8009f50: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8009f54: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8009f58: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8009f5c: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8009f60: f8c2 3080 str.w r3, [r2, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE (); 8009f64: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8009f68: 681b ldr r3, [r3, #0] 8009f6a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8009f6e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8009f72: 6013 str r3, [r2, #0] __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE (); 8009f74: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8009f78: 685b ldr r3, [r3, #4] 8009f7a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8009f7e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8009f82: 6053 str r3, [r2, #4] #if !defined (DUAL_CORE) /* Interrupt mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 8009f84: 687b ldr r3, [r7, #4] 8009f86: 685b ldr r3, [r3, #4] 8009f88: f403 3380 and.w r3, r3, #65536 @ 0x10000 8009f8c: 2b00 cmp r3, #0 8009f8e: d009 beq.n 8009fa4 { __HAL_PWR_PVD_EXTI_ENABLE_IT (); 8009f90: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8009f94: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8009f98: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8009f9c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8009fa0: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } /* Event mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 8009fa4: 687b ldr r3, [r7, #4] 8009fa6: 685b ldr r3, [r3, #4] 8009fa8: f403 3300 and.w r3, r3, #131072 @ 0x20000 8009fac: 2b00 cmp r3, #0 8009fae: d009 beq.n 8009fc4 { __HAL_PWR_PVD_EXTI_ENABLE_EVENT (); 8009fb0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8009fb4: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8009fb8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8009fbc: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8009fc0: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 8009fc4: 687b ldr r3, [r7, #4] 8009fc6: 685b ldr r3, [r3, #4] 8009fc8: f003 0301 and.w r3, r3, #1 8009fcc: 2b00 cmp r3, #0 8009fce: d007 beq.n 8009fe0 { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE (); 8009fd0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8009fd4: 681b ldr r3, [r3, #0] 8009fd6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8009fda: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8009fde: 6013 str r3, [r2, #0] } /* Falling edge configuration */ if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 8009fe0: 687b ldr r3, [r7, #4] 8009fe2: 685b ldr r3, [r3, #4] 8009fe4: f003 0302 and.w r3, r3, #2 8009fe8: 2b00 cmp r3, #0 8009fea: d009 beq.n 800a000 { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE (); 8009fec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8009ff0: 685b ldr r3, [r3, #4] 8009ff2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8009ff6: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8009ffa: 6053 str r3, [r2, #4] 8009ffc: e000 b.n 800a000 return; 8009ffe: bf00 nop } } 800a000: 370c adds r7, #12 800a002: 46bd mov sp, r7 800a004: f85d 7b04 ldr.w r7, [sp], #4 800a008: 4770 bx lr 800a00a: bf00 nop 800a00c: 58024800 .word 0x58024800 0800a010 : /** * @brief Enable the Programmable Voltage Detector (PVD). * @retval None. */ void HAL_PWR_EnablePVD (void) { 800a010: b480 push {r7} 800a012: af00 add r7, sp, #0 /* Enable the power voltage detector */ SET_BIT (PWR->CR1, PWR_CR1_PVDEN); 800a014: 4b05 ldr r3, [pc, #20] @ (800a02c ) 800a016: 681b ldr r3, [r3, #0] 800a018: 4a04 ldr r2, [pc, #16] @ (800a02c ) 800a01a: f043 0310 orr.w r3, r3, #16 800a01e: 6013 str r3, [r2, #0] } 800a020: bf00 nop 800a022: 46bd mov sp, r7 800a024: f85d 7b04 ldr.w r7, [sp], #4 800a028: 4770 bx lr 800a02a: bf00 nop 800a02c: 58024800 .word 0x58024800 0800a030 : * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { 800a030: b580 push {r7, lr} 800a032: b084 sub sp, #16 800a034: af00 add r7, sp, #0 800a036: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_SUPPLY (SupplySource)); /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) 800a038: 4b19 ldr r3, [pc, #100] @ (800a0a0 ) 800a03a: 68db ldr r3, [r3, #12] 800a03c: f003 0304 and.w r3, r3, #4 800a040: 2b04 cmp r3, #4 800a042: d00a beq.n 800a05a #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 800a044: 4b16 ldr r3, [pc, #88] @ (800a0a0 ) 800a046: 68db ldr r3, [r3, #12] 800a048: f003 0307 and.w r3, r3, #7 800a04c: 687a ldr r2, [r7, #4] 800a04e: 429a cmp r2, r3 800a050: d001 beq.n 800a056 { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 800a052: 2301 movs r3, #1 800a054: e01f b.n 800a096 else { /* Supply configuration update locked, but new supply configuration matches with old supply configuration : nothing to do */ return HAL_OK; 800a056: 2300 movs r3, #0 800a058: e01d b.n 800a096 } } /* Set the power supply configuration */ MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 800a05a: 4b11 ldr r3, [pc, #68] @ (800a0a0 ) 800a05c: 68db ldr r3, [r3, #12] 800a05e: f023 0207 bic.w r2, r3, #7 800a062: 490f ldr r1, [pc, #60] @ (800a0a0 ) 800a064: 687b ldr r3, [r7, #4] 800a066: 4313 orrs r3, r2 800a068: 60cb str r3, [r1, #12] /* Get tick */ tickstart = HAL_GetTick (); 800a06a: f7fa fcfb bl 8004a64 800a06e: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800a070: e009 b.n 800a086 { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 800a072: f7fa fcf7 bl 8004a64 800a076: 4602 mov r2, r0 800a078: 68fb ldr r3, [r7, #12] 800a07a: 1ad3 subs r3, r2, r3 800a07c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800a080: d901 bls.n 800a086 { return HAL_ERROR; 800a082: 2301 movs r3, #1 800a084: e007 b.n 800a096 while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800a086: 4b06 ldr r3, [pc, #24] @ (800a0a0 ) 800a088: 685b ldr r3, [r3, #4] 800a08a: f403 5300 and.w r3, r3, #8192 @ 0x2000 800a08e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800a092: d1ee bne.n 800a072 } } } #endif /* defined (SMPS) */ return HAL_OK; 800a094: 2300 movs r3, #0 } 800a096: 4618 mov r0, r3 800a098: 3710 adds r7, #16 800a09a: 46bd mov sp, r7 800a09c: bd80 pop {r7, pc} 800a09e: bf00 nop 800a0a0: 58024800 .word 0x58024800 0800a0a4 : * driver. All combination are allowed: wake up only Cortex-M7, wake up * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4. * @retval None. */ void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD) { 800a0a4: b480 push {r7} 800a0a6: b083 sub sp, #12 800a0a8: af00 add r7, sp, #0 800a0aa: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode)); /* Set the ALS[18:17] bits according to AVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); 800a0ac: 4b37 ldr r3, [pc, #220] @ (800a18c ) 800a0ae: 681b ldr r3, [r3, #0] 800a0b0: f423 22c0 bic.w r2, r3, #393216 @ 0x60000 800a0b4: 687b ldr r3, [r7, #4] 800a0b6: 681b ldr r3, [r3, #0] 800a0b8: 4934 ldr r1, [pc, #208] @ (800a18c ) 800a0ba: 4313 orrs r3, r2 800a0bc: 600b str r3, [r1, #0] /* Clear any previous config */ #if !defined (DUAL_CORE) __HAL_PWR_AVD_EXTI_DISABLE_EVENT (); 800a0be: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800a0c2: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800a0c6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800a0ca: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800a0ce: f8c2 3084 str.w r3, [r2, #132] @ 0x84 __HAL_PWR_AVD_EXTI_DISABLE_IT (); 800a0d2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800a0d6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800a0da: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800a0de: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800a0e2: f8c2 3080 str.w r3, [r2, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE (); 800a0e6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800a0ea: 681b ldr r3, [r3, #0] 800a0ec: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800a0f0: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800a0f4: 6013 str r3, [r2, #0] __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE (); 800a0f6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800a0fa: 685b ldr r3, [r3, #4] 800a0fc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800a100: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800a104: 6053 str r3, [r2, #4] #if !defined (DUAL_CORE) /* Configure the interrupt mode */ if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT) 800a106: 687b ldr r3, [r7, #4] 800a108: 685b ldr r3, [r3, #4] 800a10a: f403 3380 and.w r3, r3, #65536 @ 0x10000 800a10e: 2b00 cmp r3, #0 800a110: d009 beq.n 800a126 { __HAL_PWR_AVD_EXTI_ENABLE_IT (); 800a112: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800a116: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800a11a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800a11e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800a122: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } /* Configure the event mode */ if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT) 800a126: 687b ldr r3, [r7, #4] 800a128: 685b ldr r3, [r3, #4] 800a12a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800a12e: 2b00 cmp r3, #0 800a130: d009 beq.n 800a146 { __HAL_PWR_AVD_EXTI_ENABLE_EVENT (); 800a132: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800a136: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800a13a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800a13e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800a142: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE) 800a146: 687b ldr r3, [r7, #4] 800a148: 685b ldr r3, [r3, #4] 800a14a: f003 0301 and.w r3, r3, #1 800a14e: 2b00 cmp r3, #0 800a150: d007 beq.n 800a162 { __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE (); 800a152: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800a156: 681b ldr r3, [r3, #0] 800a158: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800a15c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800a160: 6013 str r3, [r2, #0] } /* Falling edge configuration */ if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE) 800a162: 687b ldr r3, [r7, #4] 800a164: 685b ldr r3, [r3, #4] 800a166: f003 0302 and.w r3, r3, #2 800a16a: 2b00 cmp r3, #0 800a16c: d007 beq.n 800a17e { __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE (); 800a16e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800a172: 685b ldr r3, [r3, #4] 800a174: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800a178: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800a17c: 6053 str r3, [r2, #4] } } 800a17e: bf00 nop 800a180: 370c adds r7, #12 800a182: 46bd mov sp, r7 800a184: f85d 7b04 ldr.w r7, [sp], #4 800a188: 4770 bx lr 800a18a: bf00 nop 800a18c: 58024800 .word 0x58024800 0800a190 : /** * @brief Enable the Analog Voltage Detector (AVD). * @retval None. */ void HAL_PWREx_EnableAVD (void) { 800a190: b480 push {r7} 800a192: af00 add r7, sp, #0 /* Enable the Analog Voltage Detector */ SET_BIT (PWR->CR1, PWR_CR1_AVDEN); 800a194: 4b05 ldr r3, [pc, #20] @ (800a1ac ) 800a196: 681b ldr r3, [r3, #0] 800a198: 4a04 ldr r2, [pc, #16] @ (800a1ac ) 800a19a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800a19e: 6013 str r3, [r2, #0] } 800a1a0: bf00 nop 800a1a2: 46bd mov sp, r7 800a1a4: f85d 7b04 ldr.w r7, [sp], #4 800a1a8: 4770 bx lr 800a1aa: bf00 nop 800a1ac: 58024800 .word 0x58024800 0800a1b0 : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800a1b0: b580 push {r7, lr} 800a1b2: b08c sub sp, #48 @ 0x30 800a1b4: af00 add r7, sp, #0 800a1b6: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 800a1b8: 687b ldr r3, [r7, #4] 800a1ba: 2b00 cmp r3, #0 800a1bc: d102 bne.n 800a1c4 { return HAL_ERROR; 800a1be: 2301 movs r3, #1 800a1c0: f000 bc48 b.w 800aa54 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800a1c4: 687b ldr r3, [r7, #4] 800a1c6: 681b ldr r3, [r3, #0] 800a1c8: f003 0301 and.w r3, r3, #1 800a1cc: 2b00 cmp r3, #0 800a1ce: f000 8088 beq.w 800a2e2 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800a1d2: 4b99 ldr r3, [pc, #612] @ (800a438 ) 800a1d4: 691b ldr r3, [r3, #16] 800a1d6: f003 0338 and.w r3, r3, #56 @ 0x38 800a1da: 62fb str r3, [r7, #44] @ 0x2c const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800a1dc: 4b96 ldr r3, [pc, #600] @ (800a438 ) 800a1de: 6a9b ldr r3, [r3, #40] @ 0x28 800a1e0: 62bb str r3, [r7, #40] @ 0x28 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 800a1e2: 6afb ldr r3, [r7, #44] @ 0x2c 800a1e4: 2b10 cmp r3, #16 800a1e6: d007 beq.n 800a1f8 800a1e8: 6afb ldr r3, [r7, #44] @ 0x2c 800a1ea: 2b18 cmp r3, #24 800a1ec: d111 bne.n 800a212 800a1ee: 6abb ldr r3, [r7, #40] @ 0x28 800a1f0: f003 0303 and.w r3, r3, #3 800a1f4: 2b02 cmp r3, #2 800a1f6: d10c bne.n 800a212 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800a1f8: 4b8f ldr r3, [pc, #572] @ (800a438 ) 800a1fa: 681b ldr r3, [r3, #0] 800a1fc: f403 3300 and.w r3, r3, #131072 @ 0x20000 800a200: 2b00 cmp r3, #0 800a202: d06d beq.n 800a2e0 800a204: 687b ldr r3, [r7, #4] 800a206: 685b ldr r3, [r3, #4] 800a208: 2b00 cmp r3, #0 800a20a: d169 bne.n 800a2e0 { return HAL_ERROR; 800a20c: 2301 movs r3, #1 800a20e: f000 bc21 b.w 800aa54 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800a212: 687b ldr r3, [r7, #4] 800a214: 685b ldr r3, [r3, #4] 800a216: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800a21a: d106 bne.n 800a22a 800a21c: 4b86 ldr r3, [pc, #536] @ (800a438 ) 800a21e: 681b ldr r3, [r3, #0] 800a220: 4a85 ldr r2, [pc, #532] @ (800a438 ) 800a222: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800a226: 6013 str r3, [r2, #0] 800a228: e02e b.n 800a288 800a22a: 687b ldr r3, [r7, #4] 800a22c: 685b ldr r3, [r3, #4] 800a22e: 2b00 cmp r3, #0 800a230: d10c bne.n 800a24c 800a232: 4b81 ldr r3, [pc, #516] @ (800a438 ) 800a234: 681b ldr r3, [r3, #0] 800a236: 4a80 ldr r2, [pc, #512] @ (800a438 ) 800a238: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800a23c: 6013 str r3, [r2, #0] 800a23e: 4b7e ldr r3, [pc, #504] @ (800a438 ) 800a240: 681b ldr r3, [r3, #0] 800a242: 4a7d ldr r2, [pc, #500] @ (800a438 ) 800a244: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800a248: 6013 str r3, [r2, #0] 800a24a: e01d b.n 800a288 800a24c: 687b ldr r3, [r7, #4] 800a24e: 685b ldr r3, [r3, #4] 800a250: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800a254: d10c bne.n 800a270 800a256: 4b78 ldr r3, [pc, #480] @ (800a438 ) 800a258: 681b ldr r3, [r3, #0] 800a25a: 4a77 ldr r2, [pc, #476] @ (800a438 ) 800a25c: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800a260: 6013 str r3, [r2, #0] 800a262: 4b75 ldr r3, [pc, #468] @ (800a438 ) 800a264: 681b ldr r3, [r3, #0] 800a266: 4a74 ldr r2, [pc, #464] @ (800a438 ) 800a268: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800a26c: 6013 str r3, [r2, #0] 800a26e: e00b b.n 800a288 800a270: 4b71 ldr r3, [pc, #452] @ (800a438 ) 800a272: 681b ldr r3, [r3, #0] 800a274: 4a70 ldr r2, [pc, #448] @ (800a438 ) 800a276: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800a27a: 6013 str r3, [r2, #0] 800a27c: 4b6e ldr r3, [pc, #440] @ (800a438 ) 800a27e: 681b ldr r3, [r3, #0] 800a280: 4a6d ldr r2, [pc, #436] @ (800a438 ) 800a282: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800a286: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 800a288: 687b ldr r3, [r7, #4] 800a28a: 685b ldr r3, [r3, #4] 800a28c: 2b00 cmp r3, #0 800a28e: d013 beq.n 800a2b8 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a290: f7fa fbe8 bl 8004a64 800a294: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800a296: e008 b.n 800a2aa { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800a298: f7fa fbe4 bl 8004a64 800a29c: 4602 mov r2, r0 800a29e: 6a7b ldr r3, [r7, #36] @ 0x24 800a2a0: 1ad3 subs r3, r2, r3 800a2a2: 2b64 cmp r3, #100 @ 0x64 800a2a4: d901 bls.n 800a2aa { return HAL_TIMEOUT; 800a2a6: 2303 movs r3, #3 800a2a8: e3d4 b.n 800aa54 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800a2aa: 4b63 ldr r3, [pc, #396] @ (800a438 ) 800a2ac: 681b ldr r3, [r3, #0] 800a2ae: f403 3300 and.w r3, r3, #131072 @ 0x20000 800a2b2: 2b00 cmp r3, #0 800a2b4: d0f0 beq.n 800a298 800a2b6: e014 b.n 800a2e2 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a2b8: f7fa fbd4 bl 8004a64 800a2bc: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800a2be: e008 b.n 800a2d2 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800a2c0: f7fa fbd0 bl 8004a64 800a2c4: 4602 mov r2, r0 800a2c6: 6a7b ldr r3, [r7, #36] @ 0x24 800a2c8: 1ad3 subs r3, r2, r3 800a2ca: 2b64 cmp r3, #100 @ 0x64 800a2cc: d901 bls.n 800a2d2 { return HAL_TIMEOUT; 800a2ce: 2303 movs r3, #3 800a2d0: e3c0 b.n 800aa54 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800a2d2: 4b59 ldr r3, [pc, #356] @ (800a438 ) 800a2d4: 681b ldr r3, [r3, #0] 800a2d6: f403 3300 and.w r3, r3, #131072 @ 0x20000 800a2da: 2b00 cmp r3, #0 800a2dc: d1f0 bne.n 800a2c0 800a2de: e000 b.n 800a2e2 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800a2e0: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800a2e2: 687b ldr r3, [r7, #4] 800a2e4: 681b ldr r3, [r3, #0] 800a2e6: f003 0302 and.w r3, r3, #2 800a2ea: 2b00 cmp r3, #0 800a2ec: f000 80ca beq.w 800a484 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800a2f0: 4b51 ldr r3, [pc, #324] @ (800a438 ) 800a2f2: 691b ldr r3, [r3, #16] 800a2f4: f003 0338 and.w r3, r3, #56 @ 0x38 800a2f8: 623b str r3, [r7, #32] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800a2fa: 4b4f ldr r3, [pc, #316] @ (800a438 ) 800a2fc: 6a9b ldr r3, [r3, #40] @ 0x28 800a2fe: 61fb str r3, [r7, #28] if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 800a300: 6a3b ldr r3, [r7, #32] 800a302: 2b00 cmp r3, #0 800a304: d007 beq.n 800a316 800a306: 6a3b ldr r3, [r7, #32] 800a308: 2b18 cmp r3, #24 800a30a: d156 bne.n 800a3ba 800a30c: 69fb ldr r3, [r7, #28] 800a30e: f003 0303 and.w r3, r3, #3 800a312: 2b00 cmp r3, #0 800a314: d151 bne.n 800a3ba { /* When HSI is used as system clock it will not be disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800a316: 4b48 ldr r3, [pc, #288] @ (800a438 ) 800a318: 681b ldr r3, [r3, #0] 800a31a: f003 0304 and.w r3, r3, #4 800a31e: 2b00 cmp r3, #0 800a320: d005 beq.n 800a32e 800a322: 687b ldr r3, [r7, #4] 800a324: 68db ldr r3, [r3, #12] 800a326: 2b00 cmp r3, #0 800a328: d101 bne.n 800a32e { return HAL_ERROR; 800a32a: 2301 movs r3, #1 800a32c: e392 b.n 800aa54 } /* Otherwise, only HSI division and calibration are allowed */ else { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800a32e: 4b42 ldr r3, [pc, #264] @ (800a438 ) 800a330: 681b ldr r3, [r3, #0] 800a332: f023 0219 bic.w r2, r3, #25 800a336: 687b ldr r3, [r7, #4] 800a338: 68db ldr r3, [r3, #12] 800a33a: 493f ldr r1, [pc, #252] @ (800a438 ) 800a33c: 4313 orrs r3, r2 800a33e: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a340: f7fa fb90 bl 8004a64 800a344: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800a346: e008 b.n 800a35a { if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800a348: f7fa fb8c bl 8004a64 800a34c: 4602 mov r2, r0 800a34e: 6a7b ldr r3, [r7, #36] @ 0x24 800a350: 1ad3 subs r3, r2, r3 800a352: 2b02 cmp r3, #2 800a354: d901 bls.n 800a35a { return HAL_TIMEOUT; 800a356: 2303 movs r3, #3 800a358: e37c b.n 800aa54 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800a35a: 4b37 ldr r3, [pc, #220] @ (800a438 ) 800a35c: 681b ldr r3, [r3, #0] 800a35e: f003 0304 and.w r3, r3, #4 800a362: 2b00 cmp r3, #0 800a364: d0f0 beq.n 800a348 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800a366: f7fa fb89 bl 8004a7c 800a36a: 4603 mov r3, r0 800a36c: f241 0203 movw r2, #4099 @ 0x1003 800a370: 4293 cmp r3, r2 800a372: d817 bhi.n 800a3a4 800a374: 687b ldr r3, [r7, #4] 800a376: 691b ldr r3, [r3, #16] 800a378: 2b40 cmp r3, #64 @ 0x40 800a37a: d108 bne.n 800a38e 800a37c: 4b2e ldr r3, [pc, #184] @ (800a438 ) 800a37e: 685b ldr r3, [r3, #4] 800a380: f423 337c bic.w r3, r3, #258048 @ 0x3f000 800a384: 4a2c ldr r2, [pc, #176] @ (800a438 ) 800a386: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800a38a: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800a38c: e07a b.n 800a484 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800a38e: 4b2a ldr r3, [pc, #168] @ (800a438 ) 800a390: 685b ldr r3, [r3, #4] 800a392: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800a396: 687b ldr r3, [r7, #4] 800a398: 691b ldr r3, [r3, #16] 800a39a: 031b lsls r3, r3, #12 800a39c: 4926 ldr r1, [pc, #152] @ (800a438 ) 800a39e: 4313 orrs r3, r2 800a3a0: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800a3a2: e06f b.n 800a484 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800a3a4: 4b24 ldr r3, [pc, #144] @ (800a438 ) 800a3a6: 685b ldr r3, [r3, #4] 800a3a8: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800a3ac: 687b ldr r3, [r7, #4] 800a3ae: 691b ldr r3, [r3, #16] 800a3b0: 061b lsls r3, r3, #24 800a3b2: 4921 ldr r1, [pc, #132] @ (800a438 ) 800a3b4: 4313 orrs r3, r2 800a3b6: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800a3b8: e064 b.n 800a484 } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 800a3ba: 687b ldr r3, [r7, #4] 800a3bc: 68db ldr r3, [r3, #12] 800a3be: 2b00 cmp r3, #0 800a3c0: d047 beq.n 800a452 { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800a3c2: 4b1d ldr r3, [pc, #116] @ (800a438 ) 800a3c4: 681b ldr r3, [r3, #0] 800a3c6: f023 0219 bic.w r2, r3, #25 800a3ca: 687b ldr r3, [r7, #4] 800a3cc: 68db ldr r3, [r3, #12] 800a3ce: 491a ldr r1, [pc, #104] @ (800a438 ) 800a3d0: 4313 orrs r3, r2 800a3d2: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a3d4: f7fa fb46 bl 8004a64 800a3d8: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800a3da: e008 b.n 800a3ee { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800a3dc: f7fa fb42 bl 8004a64 800a3e0: 4602 mov r2, r0 800a3e2: 6a7b ldr r3, [r7, #36] @ 0x24 800a3e4: 1ad3 subs r3, r2, r3 800a3e6: 2b02 cmp r3, #2 800a3e8: d901 bls.n 800a3ee { return HAL_TIMEOUT; 800a3ea: 2303 movs r3, #3 800a3ec: e332 b.n 800aa54 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800a3ee: 4b12 ldr r3, [pc, #72] @ (800a438 ) 800a3f0: 681b ldr r3, [r3, #0] 800a3f2: f003 0304 and.w r3, r3, #4 800a3f6: 2b00 cmp r3, #0 800a3f8: d0f0 beq.n 800a3dc } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800a3fa: f7fa fb3f bl 8004a7c 800a3fe: 4603 mov r3, r0 800a400: f241 0203 movw r2, #4099 @ 0x1003 800a404: 4293 cmp r3, r2 800a406: d819 bhi.n 800a43c 800a408: 687b ldr r3, [r7, #4] 800a40a: 691b ldr r3, [r3, #16] 800a40c: 2b40 cmp r3, #64 @ 0x40 800a40e: d108 bne.n 800a422 800a410: 4b09 ldr r3, [pc, #36] @ (800a438 ) 800a412: 685b ldr r3, [r3, #4] 800a414: f423 337c bic.w r3, r3, #258048 @ 0x3f000 800a418: 4a07 ldr r2, [pc, #28] @ (800a438 ) 800a41a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800a41e: 6053 str r3, [r2, #4] 800a420: e030 b.n 800a484 800a422: 4b05 ldr r3, [pc, #20] @ (800a438 ) 800a424: 685b ldr r3, [r3, #4] 800a426: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800a42a: 687b ldr r3, [r7, #4] 800a42c: 691b ldr r3, [r3, #16] 800a42e: 031b lsls r3, r3, #12 800a430: 4901 ldr r1, [pc, #4] @ (800a438 ) 800a432: 4313 orrs r3, r2 800a434: 604b str r3, [r1, #4] 800a436: e025 b.n 800a484 800a438: 58024400 .word 0x58024400 800a43c: 4b9a ldr r3, [pc, #616] @ (800a6a8 ) 800a43e: 685b ldr r3, [r3, #4] 800a440: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800a444: 687b ldr r3, [r7, #4] 800a446: 691b ldr r3, [r3, #16] 800a448: 061b lsls r3, r3, #24 800a44a: 4997 ldr r1, [pc, #604] @ (800a6a8 ) 800a44c: 4313 orrs r3, r2 800a44e: 604b str r3, [r1, #4] 800a450: e018 b.n 800a484 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800a452: 4b95 ldr r3, [pc, #596] @ (800a6a8 ) 800a454: 681b ldr r3, [r3, #0] 800a456: 4a94 ldr r2, [pc, #592] @ (800a6a8 ) 800a458: f023 0301 bic.w r3, r3, #1 800a45c: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a45e: f7fa fb01 bl 8004a64 800a462: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800a464: e008 b.n 800a478 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800a466: f7fa fafd bl 8004a64 800a46a: 4602 mov r2, r0 800a46c: 6a7b ldr r3, [r7, #36] @ 0x24 800a46e: 1ad3 subs r3, r2, r3 800a470: 2b02 cmp r3, #2 800a472: d901 bls.n 800a478 { return HAL_TIMEOUT; 800a474: 2303 movs r3, #3 800a476: e2ed b.n 800aa54 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800a478: 4b8b ldr r3, [pc, #556] @ (800a6a8 ) 800a47a: 681b ldr r3, [r3, #0] 800a47c: f003 0304 and.w r3, r3, #4 800a480: 2b00 cmp r3, #0 800a482: d1f0 bne.n 800a466 } } } } /*----------------------------- CSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 800a484: 687b ldr r3, [r7, #4] 800a486: 681b ldr r3, [r3, #0] 800a488: f003 0310 and.w r3, r3, #16 800a48c: 2b00 cmp r3, #0 800a48e: f000 80a9 beq.w 800a5e4 /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800a492: 4b85 ldr r3, [pc, #532] @ (800a6a8 ) 800a494: 691b ldr r3, [r3, #16] 800a496: f003 0338 and.w r3, r3, #56 @ 0x38 800a49a: 61bb str r3, [r7, #24] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800a49c: 4b82 ldr r3, [pc, #520] @ (800a6a8 ) 800a49e: 6a9b ldr r3, [r3, #40] @ 0x28 800a4a0: 617b str r3, [r7, #20] if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 800a4a2: 69bb ldr r3, [r7, #24] 800a4a4: 2b08 cmp r3, #8 800a4a6: d007 beq.n 800a4b8 800a4a8: 69bb ldr r3, [r7, #24] 800a4aa: 2b18 cmp r3, #24 800a4ac: d13a bne.n 800a524 800a4ae: 697b ldr r3, [r7, #20] 800a4b0: f003 0303 and.w r3, r3, #3 800a4b4: 2b01 cmp r3, #1 800a4b6: d135 bne.n 800a524 { /* When CSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800a4b8: 4b7b ldr r3, [pc, #492] @ (800a6a8 ) 800a4ba: 681b ldr r3, [r3, #0] 800a4bc: f403 7380 and.w r3, r3, #256 @ 0x100 800a4c0: 2b00 cmp r3, #0 800a4c2: d005 beq.n 800a4d0 800a4c4: 687b ldr r3, [r7, #4] 800a4c6: 69db ldr r3, [r3, #28] 800a4c8: 2b80 cmp r3, #128 @ 0x80 800a4ca: d001 beq.n 800a4d0 { return HAL_ERROR; 800a4cc: 2301 movs r3, #1 800a4ce: e2c1 b.n 800aa54 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800a4d0: f7fa fad4 bl 8004a7c 800a4d4: 4603 mov r3, r0 800a4d6: f241 0203 movw r2, #4099 @ 0x1003 800a4da: 4293 cmp r3, r2 800a4dc: d817 bhi.n 800a50e 800a4de: 687b ldr r3, [r7, #4] 800a4e0: 6a1b ldr r3, [r3, #32] 800a4e2: 2b20 cmp r3, #32 800a4e4: d108 bne.n 800a4f8 800a4e6: 4b70 ldr r3, [pc, #448] @ (800a6a8 ) 800a4e8: 685b ldr r3, [r3, #4] 800a4ea: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 800a4ee: 4a6e ldr r2, [pc, #440] @ (800a6a8 ) 800a4f0: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800a4f4: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800a4f6: e075 b.n 800a5e4 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800a4f8: 4b6b ldr r3, [pc, #428] @ (800a6a8 ) 800a4fa: 685b ldr r3, [r3, #4] 800a4fc: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800a500: 687b ldr r3, [r7, #4] 800a502: 6a1b ldr r3, [r3, #32] 800a504: 069b lsls r3, r3, #26 800a506: 4968 ldr r1, [pc, #416] @ (800a6a8 ) 800a508: 4313 orrs r3, r2 800a50a: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800a50c: e06a b.n 800a5e4 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800a50e: 4b66 ldr r3, [pc, #408] @ (800a6a8 ) 800a510: 68db ldr r3, [r3, #12] 800a512: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 800a516: 687b ldr r3, [r7, #4] 800a518: 6a1b ldr r3, [r3, #32] 800a51a: 061b lsls r3, r3, #24 800a51c: 4962 ldr r1, [pc, #392] @ (800a6a8 ) 800a51e: 4313 orrs r3, r2 800a520: 60cb str r3, [r1, #12] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800a522: e05f b.n 800a5e4 } } else { /* Check the CSI State */ if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) 800a524: 687b ldr r3, [r7, #4] 800a526: 69db ldr r3, [r3, #28] 800a528: 2b00 cmp r3, #0 800a52a: d042 beq.n 800a5b2 { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 800a52c: 4b5e ldr r3, [pc, #376] @ (800a6a8 ) 800a52e: 681b ldr r3, [r3, #0] 800a530: 4a5d ldr r2, [pc, #372] @ (800a6a8 ) 800a532: f043 0380 orr.w r3, r3, #128 @ 0x80 800a536: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a538: f7fa fa94 bl 8004a64 800a53c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800a53e: e008 b.n 800a552 { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 800a540: f7fa fa90 bl 8004a64 800a544: 4602 mov r2, r0 800a546: 6a7b ldr r3, [r7, #36] @ 0x24 800a548: 1ad3 subs r3, r2, r3 800a54a: 2b02 cmp r3, #2 800a54c: d901 bls.n 800a552 { return HAL_TIMEOUT; 800a54e: 2303 movs r3, #3 800a550: e280 b.n 800aa54 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800a552: 4b55 ldr r3, [pc, #340] @ (800a6a8 ) 800a554: 681b ldr r3, [r3, #0] 800a556: f403 7380 and.w r3, r3, #256 @ 0x100 800a55a: 2b00 cmp r3, #0 800a55c: d0f0 beq.n 800a540 } } /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800a55e: f7fa fa8d bl 8004a7c 800a562: 4603 mov r3, r0 800a564: f241 0203 movw r2, #4099 @ 0x1003 800a568: 4293 cmp r3, r2 800a56a: d817 bhi.n 800a59c 800a56c: 687b ldr r3, [r7, #4] 800a56e: 6a1b ldr r3, [r3, #32] 800a570: 2b20 cmp r3, #32 800a572: d108 bne.n 800a586 800a574: 4b4c ldr r3, [pc, #304] @ (800a6a8 ) 800a576: 685b ldr r3, [r3, #4] 800a578: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 800a57c: 4a4a ldr r2, [pc, #296] @ (800a6a8 ) 800a57e: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800a582: 6053 str r3, [r2, #4] 800a584: e02e b.n 800a5e4 800a586: 4b48 ldr r3, [pc, #288] @ (800a6a8 ) 800a588: 685b ldr r3, [r3, #4] 800a58a: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800a58e: 687b ldr r3, [r7, #4] 800a590: 6a1b ldr r3, [r3, #32] 800a592: 069b lsls r3, r3, #26 800a594: 4944 ldr r1, [pc, #272] @ (800a6a8 ) 800a596: 4313 orrs r3, r2 800a598: 604b str r3, [r1, #4] 800a59a: e023 b.n 800a5e4 800a59c: 4b42 ldr r3, [pc, #264] @ (800a6a8 ) 800a59e: 68db ldr r3, [r3, #12] 800a5a0: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 800a5a4: 687b ldr r3, [r7, #4] 800a5a6: 6a1b ldr r3, [r3, #32] 800a5a8: 061b lsls r3, r3, #24 800a5aa: 493f ldr r1, [pc, #252] @ (800a6a8 ) 800a5ac: 4313 orrs r3, r2 800a5ae: 60cb str r3, [r1, #12] 800a5b0: e018 b.n 800a5e4 } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 800a5b2: 4b3d ldr r3, [pc, #244] @ (800a6a8 ) 800a5b4: 681b ldr r3, [r3, #0] 800a5b6: 4a3c ldr r2, [pc, #240] @ (800a6a8 ) 800a5b8: f023 0380 bic.w r3, r3, #128 @ 0x80 800a5bc: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a5be: f7fa fa51 bl 8004a64 800a5c2: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800a5c4: e008 b.n 800a5d8 { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 800a5c6: f7fa fa4d bl 8004a64 800a5ca: 4602 mov r2, r0 800a5cc: 6a7b ldr r3, [r7, #36] @ 0x24 800a5ce: 1ad3 subs r3, r2, r3 800a5d0: 2b02 cmp r3, #2 800a5d2: d901 bls.n 800a5d8 { return HAL_TIMEOUT; 800a5d4: 2303 movs r3, #3 800a5d6: e23d b.n 800aa54 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800a5d8: 4b33 ldr r3, [pc, #204] @ (800a6a8 ) 800a5da: 681b ldr r3, [r3, #0] 800a5dc: f403 7380 and.w r3, r3, #256 @ 0x100 800a5e0: 2b00 cmp r3, #0 800a5e2: d1f0 bne.n 800a5c6 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800a5e4: 687b ldr r3, [r7, #4] 800a5e6: 681b ldr r3, [r3, #0] 800a5e8: f003 0308 and.w r3, r3, #8 800a5ec: 2b00 cmp r3, #0 800a5ee: d036 beq.n 800a65e { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 800a5f0: 687b ldr r3, [r7, #4] 800a5f2: 695b ldr r3, [r3, #20] 800a5f4: 2b00 cmp r3, #0 800a5f6: d019 beq.n 800a62c { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800a5f8: 4b2b ldr r3, [pc, #172] @ (800a6a8 ) 800a5fa: 6f5b ldr r3, [r3, #116] @ 0x74 800a5fc: 4a2a ldr r2, [pc, #168] @ (800a6a8 ) 800a5fe: f043 0301 orr.w r3, r3, #1 800a602: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a604: f7fa fa2e bl 8004a64 800a608: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800a60a: e008 b.n 800a61e { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800a60c: f7fa fa2a bl 8004a64 800a610: 4602 mov r2, r0 800a612: 6a7b ldr r3, [r7, #36] @ 0x24 800a614: 1ad3 subs r3, r2, r3 800a616: 2b02 cmp r3, #2 800a618: d901 bls.n 800a61e { return HAL_TIMEOUT; 800a61a: 2303 movs r3, #3 800a61c: e21a b.n 800aa54 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800a61e: 4b22 ldr r3, [pc, #136] @ (800a6a8 ) 800a620: 6f5b ldr r3, [r3, #116] @ 0x74 800a622: f003 0302 and.w r3, r3, #2 800a626: 2b00 cmp r3, #0 800a628: d0f0 beq.n 800a60c 800a62a: e018 b.n 800a65e } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800a62c: 4b1e ldr r3, [pc, #120] @ (800a6a8 ) 800a62e: 6f5b ldr r3, [r3, #116] @ 0x74 800a630: 4a1d ldr r2, [pc, #116] @ (800a6a8 ) 800a632: f023 0301 bic.w r3, r3, #1 800a636: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a638: f7fa fa14 bl 8004a64 800a63c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800a63e: e008 b.n 800a652 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800a640: f7fa fa10 bl 8004a64 800a644: 4602 mov r2, r0 800a646: 6a7b ldr r3, [r7, #36] @ 0x24 800a648: 1ad3 subs r3, r2, r3 800a64a: 2b02 cmp r3, #2 800a64c: d901 bls.n 800a652 { return HAL_TIMEOUT; 800a64e: 2303 movs r3, #3 800a650: e200 b.n 800aa54 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800a652: 4b15 ldr r3, [pc, #84] @ (800a6a8 ) 800a654: 6f5b ldr r3, [r3, #116] @ 0x74 800a656: f003 0302 and.w r3, r3, #2 800a65a: 2b00 cmp r3, #0 800a65c: d1f0 bne.n 800a640 } } } /*------------------------------ HSI48 Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 800a65e: 687b ldr r3, [r7, #4] 800a660: 681b ldr r3, [r3, #0] 800a662: f003 0320 and.w r3, r3, #32 800a666: 2b00 cmp r3, #0 800a668: d039 beq.n 800a6de { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) 800a66a: 687b ldr r3, [r7, #4] 800a66c: 699b ldr r3, [r3, #24] 800a66e: 2b00 cmp r3, #0 800a670: d01c beq.n 800a6ac { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 800a672: 4b0d ldr r3, [pc, #52] @ (800a6a8 ) 800a674: 681b ldr r3, [r3, #0] 800a676: 4a0c ldr r2, [pc, #48] @ (800a6a8 ) 800a678: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800a67c: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800a67e: f7fa f9f1 bl 8004a64 800a682: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 800a684: e008 b.n 800a698 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800a686: f7fa f9ed bl 8004a64 800a68a: 4602 mov r2, r0 800a68c: 6a7b ldr r3, [r7, #36] @ 0x24 800a68e: 1ad3 subs r3, r2, r3 800a690: 2b02 cmp r3, #2 800a692: d901 bls.n 800a698 { return HAL_TIMEOUT; 800a694: 2303 movs r3, #3 800a696: e1dd b.n 800aa54 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 800a698: 4b03 ldr r3, [pc, #12] @ (800a6a8 ) 800a69a: 681b ldr r3, [r3, #0] 800a69c: f403 5300 and.w r3, r3, #8192 @ 0x2000 800a6a0: 2b00 cmp r3, #0 800a6a2: d0f0 beq.n 800a686 800a6a4: e01b b.n 800a6de 800a6a6: bf00 nop 800a6a8: 58024400 .word 0x58024400 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 800a6ac: 4b9b ldr r3, [pc, #620] @ (800a91c ) 800a6ae: 681b ldr r3, [r3, #0] 800a6b0: 4a9a ldr r2, [pc, #616] @ (800a91c ) 800a6b2: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800a6b6: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800a6b8: f7fa f9d4 bl 8004a64 800a6bc: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800a6be: e008 b.n 800a6d2 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800a6c0: f7fa f9d0 bl 8004a64 800a6c4: 4602 mov r2, r0 800a6c6: 6a7b ldr r3, [r7, #36] @ 0x24 800a6c8: 1ad3 subs r3, r2, r3 800a6ca: 2b02 cmp r3, #2 800a6cc: d901 bls.n 800a6d2 { return HAL_TIMEOUT; 800a6ce: 2303 movs r3, #3 800a6d0: e1c0 b.n 800aa54 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800a6d2: 4b92 ldr r3, [pc, #584] @ (800a91c ) 800a6d4: 681b ldr r3, [r3, #0] 800a6d6: f403 5300 and.w r3, r3, #8192 @ 0x2000 800a6da: 2b00 cmp r3, #0 800a6dc: d1f0 bne.n 800a6c0 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800a6de: 687b ldr r3, [r7, #4] 800a6e0: 681b ldr r3, [r3, #0] 800a6e2: f003 0304 and.w r3, r3, #4 800a6e6: 2b00 cmp r3, #0 800a6e8: f000 8081 beq.w 800a7ee { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 800a6ec: 4b8c ldr r3, [pc, #560] @ (800a920 ) 800a6ee: 681b ldr r3, [r3, #0] 800a6f0: 4a8b ldr r2, [pc, #556] @ (800a920 ) 800a6f2: f443 7380 orr.w r3, r3, #256 @ 0x100 800a6f6: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800a6f8: f7fa f9b4 bl 8004a64 800a6fc: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800a6fe: e008 b.n 800a712 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800a700: f7fa f9b0 bl 8004a64 800a704: 4602 mov r2, r0 800a706: 6a7b ldr r3, [r7, #36] @ 0x24 800a708: 1ad3 subs r3, r2, r3 800a70a: 2b64 cmp r3, #100 @ 0x64 800a70c: d901 bls.n 800a712 { return HAL_TIMEOUT; 800a70e: 2303 movs r3, #3 800a710: e1a0 b.n 800aa54 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800a712: 4b83 ldr r3, [pc, #524] @ (800a920 ) 800a714: 681b ldr r3, [r3, #0] 800a716: f403 7380 and.w r3, r3, #256 @ 0x100 800a71a: 2b00 cmp r3, #0 800a71c: d0f0 beq.n 800a700 } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800a71e: 687b ldr r3, [r7, #4] 800a720: 689b ldr r3, [r3, #8] 800a722: 2b01 cmp r3, #1 800a724: d106 bne.n 800a734 800a726: 4b7d ldr r3, [pc, #500] @ (800a91c ) 800a728: 6f1b ldr r3, [r3, #112] @ 0x70 800a72a: 4a7c ldr r2, [pc, #496] @ (800a91c ) 800a72c: f043 0301 orr.w r3, r3, #1 800a730: 6713 str r3, [r2, #112] @ 0x70 800a732: e02d b.n 800a790 800a734: 687b ldr r3, [r7, #4] 800a736: 689b ldr r3, [r3, #8] 800a738: 2b00 cmp r3, #0 800a73a: d10c bne.n 800a756 800a73c: 4b77 ldr r3, [pc, #476] @ (800a91c ) 800a73e: 6f1b ldr r3, [r3, #112] @ 0x70 800a740: 4a76 ldr r2, [pc, #472] @ (800a91c ) 800a742: f023 0301 bic.w r3, r3, #1 800a746: 6713 str r3, [r2, #112] @ 0x70 800a748: 4b74 ldr r3, [pc, #464] @ (800a91c ) 800a74a: 6f1b ldr r3, [r3, #112] @ 0x70 800a74c: 4a73 ldr r2, [pc, #460] @ (800a91c ) 800a74e: f023 0304 bic.w r3, r3, #4 800a752: 6713 str r3, [r2, #112] @ 0x70 800a754: e01c b.n 800a790 800a756: 687b ldr r3, [r7, #4] 800a758: 689b ldr r3, [r3, #8] 800a75a: 2b05 cmp r3, #5 800a75c: d10c bne.n 800a778 800a75e: 4b6f ldr r3, [pc, #444] @ (800a91c ) 800a760: 6f1b ldr r3, [r3, #112] @ 0x70 800a762: 4a6e ldr r2, [pc, #440] @ (800a91c ) 800a764: f043 0304 orr.w r3, r3, #4 800a768: 6713 str r3, [r2, #112] @ 0x70 800a76a: 4b6c ldr r3, [pc, #432] @ (800a91c ) 800a76c: 6f1b ldr r3, [r3, #112] @ 0x70 800a76e: 4a6b ldr r2, [pc, #428] @ (800a91c ) 800a770: f043 0301 orr.w r3, r3, #1 800a774: 6713 str r3, [r2, #112] @ 0x70 800a776: e00b b.n 800a790 800a778: 4b68 ldr r3, [pc, #416] @ (800a91c ) 800a77a: 6f1b ldr r3, [r3, #112] @ 0x70 800a77c: 4a67 ldr r2, [pc, #412] @ (800a91c ) 800a77e: f023 0301 bic.w r3, r3, #1 800a782: 6713 str r3, [r2, #112] @ 0x70 800a784: 4b65 ldr r3, [pc, #404] @ (800a91c ) 800a786: 6f1b ldr r3, [r3, #112] @ 0x70 800a788: 4a64 ldr r2, [pc, #400] @ (800a91c ) 800a78a: f023 0304 bic.w r3, r3, #4 800a78e: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 800a790: 687b ldr r3, [r7, #4] 800a792: 689b ldr r3, [r3, #8] 800a794: 2b00 cmp r3, #0 800a796: d015 beq.n 800a7c4 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a798: f7fa f964 bl 8004a64 800a79c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800a79e: e00a b.n 800a7b6 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800a7a0: f7fa f960 bl 8004a64 800a7a4: 4602 mov r2, r0 800a7a6: 6a7b ldr r3, [r7, #36] @ 0x24 800a7a8: 1ad3 subs r3, r2, r3 800a7aa: f241 3288 movw r2, #5000 @ 0x1388 800a7ae: 4293 cmp r3, r2 800a7b0: d901 bls.n 800a7b6 { return HAL_TIMEOUT; 800a7b2: 2303 movs r3, #3 800a7b4: e14e b.n 800aa54 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800a7b6: 4b59 ldr r3, [pc, #356] @ (800a91c ) 800a7b8: 6f1b ldr r3, [r3, #112] @ 0x70 800a7ba: f003 0302 and.w r3, r3, #2 800a7be: 2b00 cmp r3, #0 800a7c0: d0ee beq.n 800a7a0 800a7c2: e014 b.n 800a7ee } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a7c4: f7fa f94e bl 8004a64 800a7c8: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800a7ca: e00a b.n 800a7e2 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800a7cc: f7fa f94a bl 8004a64 800a7d0: 4602 mov r2, r0 800a7d2: 6a7b ldr r3, [r7, #36] @ 0x24 800a7d4: 1ad3 subs r3, r2, r3 800a7d6: f241 3288 movw r2, #5000 @ 0x1388 800a7da: 4293 cmp r3, r2 800a7dc: d901 bls.n 800a7e2 { return HAL_TIMEOUT; 800a7de: 2303 movs r3, #3 800a7e0: e138 b.n 800aa54 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800a7e2: 4b4e ldr r3, [pc, #312] @ (800a91c ) 800a7e4: 6f1b ldr r3, [r3, #112] @ 0x70 800a7e6: f003 0302 and.w r3, r3, #2 800a7ea: 2b00 cmp r3, #0 800a7ec: d1ee bne.n 800a7cc } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800a7ee: 687b ldr r3, [r7, #4] 800a7f0: 6a5b ldr r3, [r3, #36] @ 0x24 800a7f2: 2b00 cmp r3, #0 800a7f4: f000 812d beq.w 800aa52 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 800a7f8: 4b48 ldr r3, [pc, #288] @ (800a91c ) 800a7fa: 691b ldr r3, [r3, #16] 800a7fc: f003 0338 and.w r3, r3, #56 @ 0x38 800a800: 2b18 cmp r3, #24 800a802: f000 80bd beq.w 800a980 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 800a806: 687b ldr r3, [r7, #4] 800a808: 6a5b ldr r3, [r3, #36] @ 0x24 800a80a: 2b02 cmp r3, #2 800a80c: f040 809e bne.w 800a94c assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800a810: 4b42 ldr r3, [pc, #264] @ (800a91c ) 800a812: 681b ldr r3, [r3, #0] 800a814: 4a41 ldr r2, [pc, #260] @ (800a91c ) 800a816: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800a81a: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a81c: f7fa f922 bl 8004a64 800a820: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800a822: e008 b.n 800a836 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800a824: f7fa f91e bl 8004a64 800a828: 4602 mov r2, r0 800a82a: 6a7b ldr r3, [r7, #36] @ 0x24 800a82c: 1ad3 subs r3, r2, r3 800a82e: 2b02 cmp r3, #2 800a830: d901 bls.n 800a836 { return HAL_TIMEOUT; 800a832: 2303 movs r3, #3 800a834: e10e b.n 800aa54 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800a836: 4b39 ldr r3, [pc, #228] @ (800a91c ) 800a838: 681b ldr r3, [r3, #0] 800a83a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800a83e: 2b00 cmp r3, #0 800a840: d1f0 bne.n 800a824 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 800a842: 4b36 ldr r3, [pc, #216] @ (800a91c ) 800a844: 6a9a ldr r2, [r3, #40] @ 0x28 800a846: 4b37 ldr r3, [pc, #220] @ (800a924 ) 800a848: 4013 ands r3, r2 800a84a: 687a ldr r2, [r7, #4] 800a84c: 6a91 ldr r1, [r2, #40] @ 0x28 800a84e: 687a ldr r2, [r7, #4] 800a850: 6ad2 ldr r2, [r2, #44] @ 0x2c 800a852: 0112 lsls r2, r2, #4 800a854: 430a orrs r2, r1 800a856: 4931 ldr r1, [pc, #196] @ (800a91c ) 800a858: 4313 orrs r3, r2 800a85a: 628b str r3, [r1, #40] @ 0x28 800a85c: 687b ldr r3, [r7, #4] 800a85e: 6b1b ldr r3, [r3, #48] @ 0x30 800a860: 3b01 subs r3, #1 800a862: f3c3 0208 ubfx r2, r3, #0, #9 800a866: 687b ldr r3, [r7, #4] 800a868: 6b5b ldr r3, [r3, #52] @ 0x34 800a86a: 3b01 subs r3, #1 800a86c: 025b lsls r3, r3, #9 800a86e: b29b uxth r3, r3 800a870: 431a orrs r2, r3 800a872: 687b ldr r3, [r7, #4] 800a874: 6b9b ldr r3, [r3, #56] @ 0x38 800a876: 3b01 subs r3, #1 800a878: 041b lsls r3, r3, #16 800a87a: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800a87e: 431a orrs r2, r3 800a880: 687b ldr r3, [r7, #4] 800a882: 6bdb ldr r3, [r3, #60] @ 0x3c 800a884: 3b01 subs r3, #1 800a886: 061b lsls r3, r3, #24 800a888: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800a88c: 4923 ldr r1, [pc, #140] @ (800a91c ) 800a88e: 4313 orrs r3, r2 800a890: 630b str r3, [r1, #48] @ 0x30 RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Disable PLLFRACN . */ __HAL_RCC_PLLFRACN_DISABLE(); 800a892: 4b22 ldr r3, [pc, #136] @ (800a91c ) 800a894: 6adb ldr r3, [r3, #44] @ 0x2c 800a896: 4a21 ldr r2, [pc, #132] @ (800a91c ) 800a898: f023 0301 bic.w r3, r3, #1 800a89c: 62d3 str r3, [r2, #44] @ 0x2c /* Configure PLL PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800a89e: 4b1f ldr r3, [pc, #124] @ (800a91c ) 800a8a0: 6b5a ldr r2, [r3, #52] @ 0x34 800a8a2: 4b21 ldr r3, [pc, #132] @ (800a928 ) 800a8a4: 4013 ands r3, r2 800a8a6: 687a ldr r2, [r7, #4] 800a8a8: 6c92 ldr r2, [r2, #72] @ 0x48 800a8aa: 00d2 lsls r2, r2, #3 800a8ac: 491b ldr r1, [pc, #108] @ (800a91c ) 800a8ae: 4313 orrs r3, r2 800a8b0: 634b str r3, [r1, #52] @ 0x34 /* Select PLL1 input reference frequency range: VCI */ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 800a8b2: 4b1a ldr r3, [pc, #104] @ (800a91c ) 800a8b4: 6adb ldr r3, [r3, #44] @ 0x2c 800a8b6: f023 020c bic.w r2, r3, #12 800a8ba: 687b ldr r3, [r7, #4] 800a8bc: 6c1b ldr r3, [r3, #64] @ 0x40 800a8be: 4917 ldr r1, [pc, #92] @ (800a91c ) 800a8c0: 4313 orrs r3, r2 800a8c2: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL1 output frequency range : VCO */ __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 800a8c4: 4b15 ldr r3, [pc, #84] @ (800a91c ) 800a8c6: 6adb ldr r3, [r3, #44] @ 0x2c 800a8c8: f023 0202 bic.w r2, r3, #2 800a8cc: 687b ldr r3, [r7, #4] 800a8ce: 6c5b ldr r3, [r3, #68] @ 0x44 800a8d0: 4912 ldr r1, [pc, #72] @ (800a91c ) 800a8d2: 4313 orrs r3, r2 800a8d4: 62cb str r3, [r1, #44] @ 0x2c /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 800a8d6: 4b11 ldr r3, [pc, #68] @ (800a91c ) 800a8d8: 6adb ldr r3, [r3, #44] @ 0x2c 800a8da: 4a10 ldr r2, [pc, #64] @ (800a91c ) 800a8dc: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800a8e0: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1Q Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800a8e2: 4b0e ldr r3, [pc, #56] @ (800a91c ) 800a8e4: 6adb ldr r3, [r3, #44] @ 0x2c 800a8e6: 4a0d ldr r2, [pc, #52] @ (800a91c ) 800a8e8: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800a8ec: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1R Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 800a8ee: 4b0b ldr r3, [pc, #44] @ (800a91c ) 800a8f0: 6adb ldr r3, [r3, #44] @ 0x2c 800a8f2: 4a0a ldr r2, [pc, #40] @ (800a91c ) 800a8f4: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800a8f8: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1FRACN . */ __HAL_RCC_PLLFRACN_ENABLE(); 800a8fa: 4b08 ldr r3, [pc, #32] @ (800a91c ) 800a8fc: 6adb ldr r3, [r3, #44] @ 0x2c 800a8fe: 4a07 ldr r2, [pc, #28] @ (800a91c ) 800a900: f043 0301 orr.w r3, r3, #1 800a904: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800a906: 4b05 ldr r3, [pc, #20] @ (800a91c ) 800a908: 681b ldr r3, [r3, #0] 800a90a: 4a04 ldr r2, [pc, #16] @ (800a91c ) 800a90c: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800a910: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a912: f7fa f8a7 bl 8004a64 800a916: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800a918: e011 b.n 800a93e 800a91a: bf00 nop 800a91c: 58024400 .word 0x58024400 800a920: 58024800 .word 0x58024800 800a924: fffffc0c .word 0xfffffc0c 800a928: ffff0007 .word 0xffff0007 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800a92c: f7fa f89a bl 8004a64 800a930: 4602 mov r2, r0 800a932: 6a7b ldr r3, [r7, #36] @ 0x24 800a934: 1ad3 subs r3, r2, r3 800a936: 2b02 cmp r3, #2 800a938: d901 bls.n 800a93e { return HAL_TIMEOUT; 800a93a: 2303 movs r3, #3 800a93c: e08a b.n 800aa54 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800a93e: 4b47 ldr r3, [pc, #284] @ (800aa5c ) 800a940: 681b ldr r3, [r3, #0] 800a942: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800a946: 2b00 cmp r3, #0 800a948: d0f0 beq.n 800a92c 800a94a: e082 b.n 800aa52 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800a94c: 4b43 ldr r3, [pc, #268] @ (800aa5c ) 800a94e: 681b ldr r3, [r3, #0] 800a950: 4a42 ldr r2, [pc, #264] @ (800aa5c ) 800a952: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800a956: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800a958: f7fa f884 bl 8004a64 800a95c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800a95e: e008 b.n 800a972 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800a960: f7fa f880 bl 8004a64 800a964: 4602 mov r2, r0 800a966: 6a7b ldr r3, [r7, #36] @ 0x24 800a968: 1ad3 subs r3, r2, r3 800a96a: 2b02 cmp r3, #2 800a96c: d901 bls.n 800a972 { return HAL_TIMEOUT; 800a96e: 2303 movs r3, #3 800a970: e070 b.n 800aa54 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800a972: 4b3a ldr r3, [pc, #232] @ (800aa5c ) 800a974: 681b ldr r3, [r3, #0] 800a976: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800a97a: 2b00 cmp r3, #0 800a97c: d1f0 bne.n 800a960 800a97e: e068 b.n 800aa52 } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp1_pllckcfg = RCC->PLLCKSELR; 800a980: 4b36 ldr r3, [pc, #216] @ (800aa5c ) 800a982: 6a9b ldr r3, [r3, #40] @ 0x28 800a984: 613b str r3, [r7, #16] temp2_pllckcfg = RCC->PLL1DIVR; 800a986: 4b35 ldr r3, [pc, #212] @ (800aa5c ) 800a988: 6b1b ldr r3, [r3, #48] @ 0x30 800a98a: 60fb str r3, [r7, #12] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800a98c: 687b ldr r3, [r7, #4] 800a98e: 6a5b ldr r3, [r3, #36] @ 0x24 800a990: 2b01 cmp r3, #1 800a992: d031 beq.n 800a9f8 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800a994: 693b ldr r3, [r7, #16] 800a996: f003 0203 and.w r2, r3, #3 800a99a: 687b ldr r3, [r7, #4] 800a99c: 6a9b ldr r3, [r3, #40] @ 0x28 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800a99e: 429a cmp r2, r3 800a9a0: d12a bne.n 800a9f8 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800a9a2: 693b ldr r3, [r7, #16] 800a9a4: 091b lsrs r3, r3, #4 800a9a6: f003 023f and.w r2, r3, #63 @ 0x3f 800a9aa: 687b ldr r3, [r7, #4] 800a9ac: 6adb ldr r3, [r3, #44] @ 0x2c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800a9ae: 429a cmp r2, r3 800a9b0: d122 bne.n 800a9f8 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800a9b2: 68fb ldr r3, [r7, #12] 800a9b4: f3c3 0208 ubfx r2, r3, #0, #9 800a9b8: 687b ldr r3, [r7, #4] 800a9ba: 6b1b ldr r3, [r3, #48] @ 0x30 800a9bc: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800a9be: 429a cmp r2, r3 800a9c0: d11a bne.n 800a9f8 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800a9c2: 68fb ldr r3, [r7, #12] 800a9c4: 0a5b lsrs r3, r3, #9 800a9c6: f003 027f and.w r2, r3, #127 @ 0x7f 800a9ca: 687b ldr r3, [r7, #4] 800a9cc: 6b5b ldr r3, [r3, #52] @ 0x34 800a9ce: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800a9d0: 429a cmp r2, r3 800a9d2: d111 bne.n 800a9f8 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 800a9d4: 68fb ldr r3, [r7, #12] 800a9d6: 0c1b lsrs r3, r3, #16 800a9d8: f003 027f and.w r2, r3, #127 @ 0x7f 800a9dc: 687b ldr r3, [r7, #4] 800a9de: 6b9b ldr r3, [r3, #56] @ 0x38 800a9e0: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800a9e2: 429a cmp r2, r3 800a9e4: d108 bne.n 800a9f8 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 800a9e6: 68fb ldr r3, [r7, #12] 800a9e8: 0e1b lsrs r3, r3, #24 800a9ea: f003 027f and.w r2, r3, #127 @ 0x7f 800a9ee: 687b ldr r3, [r7, #4] 800a9f0: 6bdb ldr r3, [r3, #60] @ 0x3c 800a9f2: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 800a9f4: 429a cmp r2, r3 800a9f6: d001 beq.n 800a9fc { return HAL_ERROR; 800a9f8: 2301 movs r3, #1 800a9fa: e02b b.n 800aa54 } else { /* Check if only fractional part needs to be updated */ temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); 800a9fc: 4b17 ldr r3, [pc, #92] @ (800aa5c ) 800a9fe: 6b5b ldr r3, [r3, #52] @ 0x34 800aa00: 08db lsrs r3, r3, #3 800aa02: f3c3 030c ubfx r3, r3, #0, #13 800aa06: 613b str r3, [r7, #16] if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) 800aa08: 687b ldr r3, [r7, #4] 800aa0a: 6c9b ldr r3, [r3, #72] @ 0x48 800aa0c: 693a ldr r2, [r7, #16] 800aa0e: 429a cmp r2, r3 800aa10: d01f beq.n 800aa52 { assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable PLL1FRACEN */ __HAL_RCC_PLLFRACN_DISABLE(); 800aa12: 4b12 ldr r3, [pc, #72] @ (800aa5c ) 800aa14: 6adb ldr r3, [r3, #44] @ 0x2c 800aa16: 4a11 ldr r2, [pc, #68] @ (800aa5c ) 800aa18: f023 0301 bic.w r3, r3, #1 800aa1c: 62d3 str r3, [r2, #44] @ 0x2c /* Get Start Tick*/ tickstart = HAL_GetTick(); 800aa1e: f7fa f821 bl 8004a64 800aa22: 6278 str r0, [r7, #36] @ 0x24 /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) 800aa24: bf00 nop 800aa26: f7fa f81d bl 8004a64 800aa2a: 4602 mov r2, r0 800aa2c: 6a7b ldr r3, [r7, #36] @ 0x24 800aa2e: 4293 cmp r3, r2 800aa30: d0f9 beq.n 800aa26 { } /* Configure PLL1 PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800aa32: 4b0a ldr r3, [pc, #40] @ (800aa5c ) 800aa34: 6b5a ldr r2, [r3, #52] @ 0x34 800aa36: 4b0a ldr r3, [pc, #40] @ (800aa60 ) 800aa38: 4013 ands r3, r2 800aa3a: 687a ldr r2, [r7, #4] 800aa3c: 6c92 ldr r2, [r2, #72] @ 0x48 800aa3e: 00d2 lsls r2, r2, #3 800aa40: 4906 ldr r1, [pc, #24] @ (800aa5c ) 800aa42: 4313 orrs r3, r2 800aa44: 634b str r3, [r1, #52] @ 0x34 /* Enable PLL1FRACEN to latch new value. */ __HAL_RCC_PLLFRACN_ENABLE(); 800aa46: 4b05 ldr r3, [pc, #20] @ (800aa5c ) 800aa48: 6adb ldr r3, [r3, #44] @ 0x2c 800aa4a: 4a04 ldr r2, [pc, #16] @ (800aa5c ) 800aa4c: f043 0301 orr.w r3, r3, #1 800aa50: 62d3 str r3, [r2, #44] @ 0x2c } } } } return HAL_OK; 800aa52: 2300 movs r3, #0 } 800aa54: 4618 mov r0, r3 800aa56: 3730 adds r7, #48 @ 0x30 800aa58: 46bd mov sp, r7 800aa5a: bd80 pop {r7, pc} 800aa5c: 58024400 .word 0x58024400 800aa60: ffff0007 .word 0xffff0007 0800aa64 : * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800aa64: b580 push {r7, lr} 800aa66: b086 sub sp, #24 800aa68: af00 add r7, sp, #0 800aa6a: 6078 str r0, [r7, #4] 800aa6c: 6039 str r1, [r7, #0] HAL_StatusTypeDef halstatus; uint32_t tickstart; uint32_t common_system_clock; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800aa6e: 687b ldr r3, [r7, #4] 800aa70: 2b00 cmp r3, #0 800aa72: d101 bne.n 800aa78 { return HAL_ERROR; 800aa74: 2301 movs r3, #1 800aa76: e19c b.n 800adb2 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 800aa78: 4b8a ldr r3, [pc, #552] @ (800aca4 ) 800aa7a: 681b ldr r3, [r3, #0] 800aa7c: f003 030f and.w r3, r3, #15 800aa80: 683a ldr r2, [r7, #0] 800aa82: 429a cmp r2, r3 800aa84: d910 bls.n 800aaa8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800aa86: 4b87 ldr r3, [pc, #540] @ (800aca4 ) 800aa88: 681b ldr r3, [r3, #0] 800aa8a: f023 020f bic.w r2, r3, #15 800aa8e: 4985 ldr r1, [pc, #532] @ (800aca4 ) 800aa90: 683b ldr r3, [r7, #0] 800aa92: 4313 orrs r3, r2 800aa94: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800aa96: 4b83 ldr r3, [pc, #524] @ (800aca4 ) 800aa98: 681b ldr r3, [r3, #0] 800aa9a: f003 030f and.w r3, r3, #15 800aa9e: 683a ldr r2, [r7, #0] 800aaa0: 429a cmp r2, r3 800aaa2: d001 beq.n 800aaa8 { return HAL_ERROR; 800aaa4: 2301 movs r3, #1 800aaa6: e184 b.n 800adb2 } /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 800aaa8: 687b ldr r3, [r7, #4] 800aaaa: 681b ldr r3, [r3, #0] 800aaac: f003 0304 and.w r3, r3, #4 800aab0: 2b00 cmp r3, #0 800aab2: d010 beq.n 800aad6 { #if defined (RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 800aab4: 687b ldr r3, [r7, #4] 800aab6: 691a ldr r2, [r3, #16] 800aab8: 4b7b ldr r3, [pc, #492] @ (800aca8 ) 800aaba: 699b ldr r3, [r3, #24] 800aabc: f003 0370 and.w r3, r3, #112 @ 0x70 800aac0: 429a cmp r2, r3 800aac2: d908 bls.n 800aad6 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 800aac4: 4b78 ldr r3, [pc, #480] @ (800aca8 ) 800aac6: 699b ldr r3, [r3, #24] 800aac8: f023 0270 bic.w r2, r3, #112 @ 0x70 800aacc: 687b ldr r3, [r7, #4] 800aace: 691b ldr r3, [r3, #16] 800aad0: 4975 ldr r1, [pc, #468] @ (800aca8 ) 800aad2: 4313 orrs r3, r2 800aad4: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800aad6: 687b ldr r3, [r7, #4] 800aad8: 681b ldr r3, [r3, #0] 800aada: f003 0308 and.w r3, r3, #8 800aade: 2b00 cmp r3, #0 800aae0: d010 beq.n 800ab04 { #if defined (RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800aae2: 687b ldr r3, [r7, #4] 800aae4: 695a ldr r2, [r3, #20] 800aae6: 4b70 ldr r3, [pc, #448] @ (800aca8 ) 800aae8: 69db ldr r3, [r3, #28] 800aaea: f003 0370 and.w r3, r3, #112 @ 0x70 800aaee: 429a cmp r2, r3 800aaf0: d908 bls.n 800ab04 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800aaf2: 4b6d ldr r3, [pc, #436] @ (800aca8 ) 800aaf4: 69db ldr r3, [r3, #28] 800aaf6: f023 0270 bic.w r2, r3, #112 @ 0x70 800aafa: 687b ldr r3, [r7, #4] 800aafc: 695b ldr r3, [r3, #20] 800aafe: 496a ldr r1, [pc, #424] @ (800aca8 ) 800ab00: 4313 orrs r3, r2 800ab02: 61cb str r3, [r1, #28] MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800ab04: 687b ldr r3, [r7, #4] 800ab06: 681b ldr r3, [r3, #0] 800ab08: f003 0310 and.w r3, r3, #16 800ab0c: 2b00 cmp r3, #0 800ab0e: d010 beq.n 800ab32 { #if defined(RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800ab10: 687b ldr r3, [r7, #4] 800ab12: 699a ldr r2, [r3, #24] 800ab14: 4b64 ldr r3, [pc, #400] @ (800aca8 ) 800ab16: 69db ldr r3, [r3, #28] 800ab18: f403 63e0 and.w r3, r3, #1792 @ 0x700 800ab1c: 429a cmp r2, r3 800ab1e: d908 bls.n 800ab32 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800ab20: 4b61 ldr r3, [pc, #388] @ (800aca8 ) 800ab22: 69db ldr r3, [r3, #28] 800ab24: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800ab28: 687b ldr r3, [r7, #4] 800ab2a: 699b ldr r3, [r3, #24] 800ab2c: 495e ldr r1, [pc, #376] @ (800aca8 ) 800ab2e: 4313 orrs r3, r2 800ab30: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800ab32: 687b ldr r3, [r7, #4] 800ab34: 681b ldr r3, [r3, #0] 800ab36: f003 0320 and.w r3, r3, #32 800ab3a: 2b00 cmp r3, #0 800ab3c: d010 beq.n 800ab60 { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800ab3e: 687b ldr r3, [r7, #4] 800ab40: 69da ldr r2, [r3, #28] 800ab42: 4b59 ldr r3, [pc, #356] @ (800aca8 ) 800ab44: 6a1b ldr r3, [r3, #32] 800ab46: f003 0370 and.w r3, r3, #112 @ 0x70 800ab4a: 429a cmp r2, r3 800ab4c: d908 bls.n 800ab60 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800ab4e: 4b56 ldr r3, [pc, #344] @ (800aca8 ) 800ab50: 6a1b ldr r3, [r3, #32] 800ab52: f023 0270 bic.w r2, r3, #112 @ 0x70 800ab56: 687b ldr r3, [r7, #4] 800ab58: 69db ldr r3, [r3, #28] 800ab5a: 4953 ldr r1, [pc, #332] @ (800aca8 ) 800ab5c: 4313 orrs r3, r2 800ab5e: 620b str r3, [r1, #32] } #endif } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800ab60: 687b ldr r3, [r7, #4] 800ab62: 681b ldr r3, [r3, #0] 800ab64: f003 0302 and.w r3, r3, #2 800ab68: 2b00 cmp r3, #0 800ab6a: d010 beq.n 800ab8e { #if defined (RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800ab6c: 687b ldr r3, [r7, #4] 800ab6e: 68da ldr r2, [r3, #12] 800ab70: 4b4d ldr r3, [pc, #308] @ (800aca8 ) 800ab72: 699b ldr r3, [r3, #24] 800ab74: f003 030f and.w r3, r3, #15 800ab78: 429a cmp r2, r3 800ab7a: d908 bls.n 800ab8e { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800ab7c: 4b4a ldr r3, [pc, #296] @ (800aca8 ) 800ab7e: 699b ldr r3, [r3, #24] 800ab80: f023 020f bic.w r2, r3, #15 800ab84: 687b ldr r3, [r7, #4] 800ab86: 68db ldr r3, [r3, #12] 800ab88: 4947 ldr r1, [pc, #284] @ (800aca8 ) 800ab8a: 4313 orrs r3, r2 800ab8c: 618b str r3, [r1, #24] } #endif } /*------------------------- SYSCLK Configuration -------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800ab8e: 687b ldr r3, [r7, #4] 800ab90: 681b ldr r3, [r3, #0] 800ab92: f003 0301 and.w r3, r3, #1 800ab96: 2b00 cmp r3, #0 800ab98: d055 beq.n 800ac46 { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_D1CFGR_D1CPRE) MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); 800ab9a: 4b43 ldr r3, [pc, #268] @ (800aca8 ) 800ab9c: 699b ldr r3, [r3, #24] 800ab9e: f423 6270 bic.w r2, r3, #3840 @ 0xf00 800aba2: 687b ldr r3, [r7, #4] 800aba4: 689b ldr r3, [r3, #8] 800aba6: 4940 ldr r1, [pc, #256] @ (800aca8 ) 800aba8: 4313 orrs r3, r2 800abaa: 618b str r3, [r1, #24] #else MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); #endif /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800abac: 687b ldr r3, [r7, #4] 800abae: 685b ldr r3, [r3, #4] 800abb0: 2b02 cmp r3, #2 800abb2: d107 bne.n 800abc4 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800abb4: 4b3c ldr r3, [pc, #240] @ (800aca8 ) 800abb6: 681b ldr r3, [r3, #0] 800abb8: f403 3300 and.w r3, r3, #131072 @ 0x20000 800abbc: 2b00 cmp r3, #0 800abbe: d121 bne.n 800ac04 { return HAL_ERROR; 800abc0: 2301 movs r3, #1 800abc2: e0f6 b.n 800adb2 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800abc4: 687b ldr r3, [r7, #4] 800abc6: 685b ldr r3, [r3, #4] 800abc8: 2b03 cmp r3, #3 800abca: d107 bne.n 800abdc { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800abcc: 4b36 ldr r3, [pc, #216] @ (800aca8 ) 800abce: 681b ldr r3, [r3, #0] 800abd0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800abd4: 2b00 cmp r3, #0 800abd6: d115 bne.n 800ac04 { return HAL_ERROR; 800abd8: 2301 movs r3, #1 800abda: e0ea b.n 800adb2 } } /* CSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 800abdc: 687b ldr r3, [r7, #4] 800abde: 685b ldr r3, [r3, #4] 800abe0: 2b01 cmp r3, #1 800abe2: d107 bne.n 800abf4 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800abe4: 4b30 ldr r3, [pc, #192] @ (800aca8 ) 800abe6: 681b ldr r3, [r3, #0] 800abe8: f403 7380 and.w r3, r3, #256 @ 0x100 800abec: 2b00 cmp r3, #0 800abee: d109 bne.n 800ac04 { return HAL_ERROR; 800abf0: 2301 movs r3, #1 800abf2: e0de b.n 800adb2 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800abf4: 4b2c ldr r3, [pc, #176] @ (800aca8 ) 800abf6: 681b ldr r3, [r3, #0] 800abf8: f003 0304 and.w r3, r3, #4 800abfc: 2b00 cmp r3, #0 800abfe: d101 bne.n 800ac04 { return HAL_ERROR; 800ac00: 2301 movs r3, #1 800ac02: e0d6 b.n 800adb2 } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 800ac04: 4b28 ldr r3, [pc, #160] @ (800aca8 ) 800ac06: 691b ldr r3, [r3, #16] 800ac08: f023 0207 bic.w r2, r3, #7 800ac0c: 687b ldr r3, [r7, #4] 800ac0e: 685b ldr r3, [r3, #4] 800ac10: 4925 ldr r1, [pc, #148] @ (800aca8 ) 800ac12: 4313 orrs r3, r2 800ac14: 610b str r3, [r1, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ac16: f7f9 ff25 bl 8004a64 800ac1a: 6178 str r0, [r7, #20] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800ac1c: e00a b.n 800ac34 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800ac1e: f7f9 ff21 bl 8004a64 800ac22: 4602 mov r2, r0 800ac24: 697b ldr r3, [r7, #20] 800ac26: 1ad3 subs r3, r2, r3 800ac28: f241 3288 movw r2, #5000 @ 0x1388 800ac2c: 4293 cmp r3, r2 800ac2e: d901 bls.n 800ac34 { return HAL_TIMEOUT; 800ac30: 2303 movs r3, #3 800ac32: e0be b.n 800adb2 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800ac34: 4b1c ldr r3, [pc, #112] @ (800aca8 ) 800ac36: 691b ldr r3, [r3, #16] 800ac38: f003 0238 and.w r2, r3, #56 @ 0x38 800ac3c: 687b ldr r3, [r7, #4] 800ac3e: 685b ldr r3, [r3, #4] 800ac40: 00db lsls r3, r3, #3 800ac42: 429a cmp r2, r3 800ac44: d1eb bne.n 800ac1e } /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800ac46: 687b ldr r3, [r7, #4] 800ac48: 681b ldr r3, [r3, #0] 800ac4a: f003 0302 and.w r3, r3, #2 800ac4e: 2b00 cmp r3, #0 800ac50: d010 beq.n 800ac74 { #if defined(RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800ac52: 687b ldr r3, [r7, #4] 800ac54: 68da ldr r2, [r3, #12] 800ac56: 4b14 ldr r3, [pc, #80] @ (800aca8 ) 800ac58: 699b ldr r3, [r3, #24] 800ac5a: f003 030f and.w r3, r3, #15 800ac5e: 429a cmp r2, r3 800ac60: d208 bcs.n 800ac74 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800ac62: 4b11 ldr r3, [pc, #68] @ (800aca8 ) 800ac64: 699b ldr r3, [r3, #24] 800ac66: f023 020f bic.w r2, r3, #15 800ac6a: 687b ldr r3, [r7, #4] 800ac6c: 68db ldr r3, [r3, #12] 800ac6e: 490e ldr r1, [pc, #56] @ (800aca8 ) 800ac70: 4313 orrs r3, r2 800ac72: 618b str r3, [r1, #24] } #endif } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 800ac74: 4b0b ldr r3, [pc, #44] @ (800aca4 ) 800ac76: 681b ldr r3, [r3, #0] 800ac78: f003 030f and.w r3, r3, #15 800ac7c: 683a ldr r2, [r7, #0] 800ac7e: 429a cmp r2, r3 800ac80: d214 bcs.n 800acac { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800ac82: 4b08 ldr r3, [pc, #32] @ (800aca4 ) 800ac84: 681b ldr r3, [r3, #0] 800ac86: f023 020f bic.w r2, r3, #15 800ac8a: 4906 ldr r1, [pc, #24] @ (800aca4 ) 800ac8c: 683b ldr r3, [r7, #0] 800ac8e: 4313 orrs r3, r2 800ac90: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800ac92: 4b04 ldr r3, [pc, #16] @ (800aca4 ) 800ac94: 681b ldr r3, [r3, #0] 800ac96: f003 030f and.w r3, r3, #15 800ac9a: 683a ldr r2, [r7, #0] 800ac9c: 429a cmp r2, r3 800ac9e: d005 beq.n 800acac { return HAL_ERROR; 800aca0: 2301 movs r3, #1 800aca2: e086 b.n 800adb2 800aca4: 52002000 .word 0x52002000 800aca8: 58024400 .word 0x58024400 } } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 800acac: 687b ldr r3, [r7, #4] 800acae: 681b ldr r3, [r3, #0] 800acb0: f003 0304 and.w r3, r3, #4 800acb4: 2b00 cmp r3, #0 800acb6: d010 beq.n 800acda { #if defined(RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 800acb8: 687b ldr r3, [r7, #4] 800acba: 691a ldr r2, [r3, #16] 800acbc: 4b3f ldr r3, [pc, #252] @ (800adbc ) 800acbe: 699b ldr r3, [r3, #24] 800acc0: f003 0370 and.w r3, r3, #112 @ 0x70 800acc4: 429a cmp r2, r3 800acc6: d208 bcs.n 800acda { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 800acc8: 4b3c ldr r3, [pc, #240] @ (800adbc ) 800acca: 699b ldr r3, [r3, #24] 800accc: f023 0270 bic.w r2, r3, #112 @ 0x70 800acd0: 687b ldr r3, [r7, #4] 800acd2: 691b ldr r3, [r3, #16] 800acd4: 4939 ldr r1, [pc, #228] @ (800adbc ) 800acd6: 4313 orrs r3, r2 800acd8: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800acda: 687b ldr r3, [r7, #4] 800acdc: 681b ldr r3, [r3, #0] 800acde: f003 0308 and.w r3, r3, #8 800ace2: 2b00 cmp r3, #0 800ace4: d010 beq.n 800ad08 { #if defined(RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800ace6: 687b ldr r3, [r7, #4] 800ace8: 695a ldr r2, [r3, #20] 800acea: 4b34 ldr r3, [pc, #208] @ (800adbc ) 800acec: 69db ldr r3, [r3, #28] 800acee: f003 0370 and.w r3, r3, #112 @ 0x70 800acf2: 429a cmp r2, r3 800acf4: d208 bcs.n 800ad08 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800acf6: 4b31 ldr r3, [pc, #196] @ (800adbc ) 800acf8: 69db ldr r3, [r3, #28] 800acfa: f023 0270 bic.w r2, r3, #112 @ 0x70 800acfe: 687b ldr r3, [r7, #4] 800ad00: 695b ldr r3, [r3, #20] 800ad02: 492e ldr r1, [pc, #184] @ (800adbc ) 800ad04: 4313 orrs r3, r2 800ad06: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800ad08: 687b ldr r3, [r7, #4] 800ad0a: 681b ldr r3, [r3, #0] 800ad0c: f003 0310 and.w r3, r3, #16 800ad10: 2b00 cmp r3, #0 800ad12: d010 beq.n 800ad36 { #if defined (RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800ad14: 687b ldr r3, [r7, #4] 800ad16: 699a ldr r2, [r3, #24] 800ad18: 4b28 ldr r3, [pc, #160] @ (800adbc ) 800ad1a: 69db ldr r3, [r3, #28] 800ad1c: f403 63e0 and.w r3, r3, #1792 @ 0x700 800ad20: 429a cmp r2, r3 800ad22: d208 bcs.n 800ad36 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800ad24: 4b25 ldr r3, [pc, #148] @ (800adbc ) 800ad26: 69db ldr r3, [r3, #28] 800ad28: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800ad2c: 687b ldr r3, [r7, #4] 800ad2e: 699b ldr r3, [r3, #24] 800ad30: 4922 ldr r1, [pc, #136] @ (800adbc ) 800ad32: 4313 orrs r3, r2 800ad34: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800ad36: 687b ldr r3, [r7, #4] 800ad38: 681b ldr r3, [r3, #0] 800ad3a: f003 0320 and.w r3, r3, #32 800ad3e: 2b00 cmp r3, #0 800ad40: d010 beq.n 800ad64 { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800ad42: 687b ldr r3, [r7, #4] 800ad44: 69da ldr r2, [r3, #28] 800ad46: 4b1d ldr r3, [pc, #116] @ (800adbc ) 800ad48: 6a1b ldr r3, [r3, #32] 800ad4a: f003 0370 and.w r3, r3, #112 @ 0x70 800ad4e: 429a cmp r2, r3 800ad50: d208 bcs.n 800ad64 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800ad52: 4b1a ldr r3, [pc, #104] @ (800adbc ) 800ad54: 6a1b ldr r3, [r3, #32] 800ad56: f023 0270 bic.w r2, r3, #112 @ 0x70 800ad5a: 687b ldr r3, [r7, #4] 800ad5c: 69db ldr r3, [r3, #28] 800ad5e: 4917 ldr r1, [pc, #92] @ (800adbc ) 800ad60: 4313 orrs r3, r2 800ad62: 620b str r3, [r1, #32] #endif } /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 800ad64: f000 f834 bl 800add0 800ad68: 4602 mov r2, r0 800ad6a: 4b14 ldr r3, [pc, #80] @ (800adbc ) 800ad6c: 699b ldr r3, [r3, #24] 800ad6e: 0a1b lsrs r3, r3, #8 800ad70: f003 030f and.w r3, r3, #15 800ad74: 4912 ldr r1, [pc, #72] @ (800adc0 ) 800ad76: 5ccb ldrb r3, [r1, r3] 800ad78: f003 031f and.w r3, r3, #31 800ad7c: fa22 f303 lsr.w r3, r2, r3 800ad80: 613b str r3, [r7, #16] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800ad82: 4b0e ldr r3, [pc, #56] @ (800adbc ) 800ad84: 699b ldr r3, [r3, #24] 800ad86: f003 030f and.w r3, r3, #15 800ad8a: 4a0d ldr r2, [pc, #52] @ (800adc0 ) 800ad8c: 5cd3 ldrb r3, [r2, r3] 800ad8e: f003 031f and.w r3, r3, #31 800ad92: 693a ldr r2, [r7, #16] 800ad94: fa22 f303 lsr.w r3, r2, r3 800ad98: 4a0a ldr r2, [pc, #40] @ (800adc4 ) 800ad9a: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 800ad9c: 4a0a ldr r2, [pc, #40] @ (800adc8 ) 800ad9e: 693b ldr r3, [r7, #16] 800ada0: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick(uwTickPrio); 800ada2: 4b0a ldr r3, [pc, #40] @ (800adcc ) 800ada4: 681b ldr r3, [r3, #0] 800ada6: 4618 mov r0, r3 800ada8: f7f8 fc9c bl 80036e4 800adac: 4603 mov r3, r0 800adae: 73fb strb r3, [r7, #15] return halstatus; 800adb0: 7bfb ldrb r3, [r7, #15] } 800adb2: 4618 mov r0, r3 800adb4: 3718 adds r7, #24 800adb6: 46bd mov sp, r7 800adb8: bd80 pop {r7, pc} 800adba: bf00 nop 800adbc: 58024400 .word 0x58024400 800adc0: 080175c8 .word 0x080175c8 800adc4: 24000038 .word 0x24000038 800adc8: 24000034 .word 0x24000034 800adcc: 2400003c .word 0x2400003c 0800add0 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800add0: b480 push {r7} 800add2: b089 sub sp, #36 @ 0x24 800add4: af00 add r7, sp, #0 float_t fracn1, pllvco; uint32_t sysclockfreq; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 800add6: 4bb3 ldr r3, [pc, #716] @ (800b0a4 ) 800add8: 691b ldr r3, [r3, #16] 800adda: f003 0338 and.w r3, r3, #56 @ 0x38 800adde: 2b18 cmp r3, #24 800ade0: f200 8155 bhi.w 800b08e 800ade4: a201 add r2, pc, #4 @ (adr r2, 800adec ) 800ade6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800adea: bf00 nop 800adec: 0800ae51 .word 0x0800ae51 800adf0: 0800b08f .word 0x0800b08f 800adf4: 0800b08f .word 0x0800b08f 800adf8: 0800b08f .word 0x0800b08f 800adfc: 0800b08f .word 0x0800b08f 800ae00: 0800b08f .word 0x0800b08f 800ae04: 0800b08f .word 0x0800b08f 800ae08: 0800b08f .word 0x0800b08f 800ae0c: 0800ae77 .word 0x0800ae77 800ae10: 0800b08f .word 0x0800b08f 800ae14: 0800b08f .word 0x0800b08f 800ae18: 0800b08f .word 0x0800b08f 800ae1c: 0800b08f .word 0x0800b08f 800ae20: 0800b08f .word 0x0800b08f 800ae24: 0800b08f .word 0x0800b08f 800ae28: 0800b08f .word 0x0800b08f 800ae2c: 0800ae7d .word 0x0800ae7d 800ae30: 0800b08f .word 0x0800b08f 800ae34: 0800b08f .word 0x0800b08f 800ae38: 0800b08f .word 0x0800b08f 800ae3c: 0800b08f .word 0x0800b08f 800ae40: 0800b08f .word 0x0800b08f 800ae44: 0800b08f .word 0x0800b08f 800ae48: 0800b08f .word 0x0800b08f 800ae4c: 0800ae83 .word 0x0800ae83 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800ae50: 4b94 ldr r3, [pc, #592] @ (800b0a4 ) 800ae52: 681b ldr r3, [r3, #0] 800ae54: f003 0320 and.w r3, r3, #32 800ae58: 2b00 cmp r3, #0 800ae5a: d009 beq.n 800ae70 { sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800ae5c: 4b91 ldr r3, [pc, #580] @ (800b0a4 ) 800ae5e: 681b ldr r3, [r3, #0] 800ae60: 08db lsrs r3, r3, #3 800ae62: f003 0303 and.w r3, r3, #3 800ae66: 4a90 ldr r2, [pc, #576] @ (800b0a8 ) 800ae68: fa22 f303 lsr.w r3, r2, r3 800ae6c: 61bb str r3, [r7, #24] else { sysclockfreq = (uint32_t) HSI_VALUE; } break; 800ae6e: e111 b.n 800b094 sysclockfreq = (uint32_t) HSI_VALUE; 800ae70: 4b8d ldr r3, [pc, #564] @ (800b0a8 ) 800ae72: 61bb str r3, [r7, #24] break; 800ae74: e10e b.n 800b094 case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ sysclockfreq = CSI_VALUE; 800ae76: 4b8d ldr r3, [pc, #564] @ (800b0ac ) 800ae78: 61bb str r3, [r7, #24] break; 800ae7a: e10b b.n 800b094 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 800ae7c: 4b8c ldr r3, [pc, #560] @ (800b0b0 ) 800ae7e: 61bb str r3, [r7, #24] break; 800ae80: e108 b.n 800b094 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800ae82: 4b88 ldr r3, [pc, #544] @ (800b0a4 ) 800ae84: 6a9b ldr r3, [r3, #40] @ 0x28 800ae86: f003 0303 and.w r3, r3, #3 800ae8a: 617b str r3, [r7, #20] pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; 800ae8c: 4b85 ldr r3, [pc, #532] @ (800b0a4 ) 800ae8e: 6a9b ldr r3, [r3, #40] @ 0x28 800ae90: 091b lsrs r3, r3, #4 800ae92: f003 033f and.w r3, r3, #63 @ 0x3f 800ae96: 613b str r3, [r7, #16] pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); 800ae98: 4b82 ldr r3, [pc, #520] @ (800b0a4 ) 800ae9a: 6adb ldr r3, [r3, #44] @ 0x2c 800ae9c: f003 0301 and.w r3, r3, #1 800aea0: 60fb str r3, [r7, #12] fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800aea2: 4b80 ldr r3, [pc, #512] @ (800b0a4 ) 800aea4: 6b5b ldr r3, [r3, #52] @ 0x34 800aea6: 08db lsrs r3, r3, #3 800aea8: f3c3 030c ubfx r3, r3, #0, #13 800aeac: 68fa ldr r2, [r7, #12] 800aeae: fb02 f303 mul.w r3, r2, r3 800aeb2: ee07 3a90 vmov s15, r3 800aeb6: eef8 7a67 vcvt.f32.u32 s15, s15 800aeba: edc7 7a02 vstr s15, [r7, #8] if (pllm != 0U) 800aebe: 693b ldr r3, [r7, #16] 800aec0: 2b00 cmp r3, #0 800aec2: f000 80e1 beq.w 800b088 800aec6: 697b ldr r3, [r7, #20] 800aec8: 2b02 cmp r3, #2 800aeca: f000 8083 beq.w 800afd4 800aece: 697b ldr r3, [r7, #20] 800aed0: 2b02 cmp r3, #2 800aed2: f200 80a1 bhi.w 800b018 800aed6: 697b ldr r3, [r7, #20] 800aed8: 2b00 cmp r3, #0 800aeda: d003 beq.n 800aee4 800aedc: 697b ldr r3, [r7, #20] 800aede: 2b01 cmp r3, #1 800aee0: d056 beq.n 800af90 800aee2: e099 b.n 800b018 { switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800aee4: 4b6f ldr r3, [pc, #444] @ (800b0a4 ) 800aee6: 681b ldr r3, [r3, #0] 800aee8: f003 0320 and.w r3, r3, #32 800aeec: 2b00 cmp r3, #0 800aeee: d02d beq.n 800af4c { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800aef0: 4b6c ldr r3, [pc, #432] @ (800b0a4 ) 800aef2: 681b ldr r3, [r3, #0] 800aef4: 08db lsrs r3, r3, #3 800aef6: f003 0303 and.w r3, r3, #3 800aefa: 4a6b ldr r2, [pc, #428] @ (800b0a8 ) 800aefc: fa22 f303 lsr.w r3, r2, r3 800af00: 607b str r3, [r7, #4] pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800af02: 687b ldr r3, [r7, #4] 800af04: ee07 3a90 vmov s15, r3 800af08: eef8 6a67 vcvt.f32.u32 s13, s15 800af0c: 693b ldr r3, [r7, #16] 800af0e: ee07 3a90 vmov s15, r3 800af12: eef8 7a67 vcvt.f32.u32 s15, s15 800af16: ee86 7aa7 vdiv.f32 s14, s13, s15 800af1a: 4b62 ldr r3, [pc, #392] @ (800b0a4 ) 800af1c: 6b1b ldr r3, [r3, #48] @ 0x30 800af1e: f3c3 0308 ubfx r3, r3, #0, #9 800af22: ee07 3a90 vmov s15, r3 800af26: eef8 6a67 vcvt.f32.u32 s13, s15 800af2a: ed97 6a02 vldr s12, [r7, #8] 800af2e: eddf 5a61 vldr s11, [pc, #388] @ 800b0b4 800af32: eec6 7a25 vdiv.f32 s15, s12, s11 800af36: ee76 7aa7 vadd.f32 s15, s13, s15 800af3a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800af3e: ee77 7aa6 vadd.f32 s15, s15, s13 800af42: ee67 7a27 vmul.f32 s15, s14, s15 800af46: edc7 7a07 vstr s15, [r7, #28] } else { pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 800af4a: e087 b.n 800b05c pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800af4c: 693b ldr r3, [r7, #16] 800af4e: ee07 3a90 vmov s15, r3 800af52: eef8 7a67 vcvt.f32.u32 s15, s15 800af56: eddf 6a58 vldr s13, [pc, #352] @ 800b0b8 800af5a: ee86 7aa7 vdiv.f32 s14, s13, s15 800af5e: 4b51 ldr r3, [pc, #324] @ (800b0a4 ) 800af60: 6b1b ldr r3, [r3, #48] @ 0x30 800af62: f3c3 0308 ubfx r3, r3, #0, #9 800af66: ee07 3a90 vmov s15, r3 800af6a: eef8 6a67 vcvt.f32.u32 s13, s15 800af6e: ed97 6a02 vldr s12, [r7, #8] 800af72: eddf 5a50 vldr s11, [pc, #320] @ 800b0b4 800af76: eec6 7a25 vdiv.f32 s15, s12, s11 800af7a: ee76 7aa7 vadd.f32 s15, s13, s15 800af7e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800af82: ee77 7aa6 vadd.f32 s15, s15, s13 800af86: ee67 7a27 vmul.f32 s15, s14, s15 800af8a: edc7 7a07 vstr s15, [r7, #28] break; 800af8e: e065 b.n 800b05c case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800af90: 693b ldr r3, [r7, #16] 800af92: ee07 3a90 vmov s15, r3 800af96: eef8 7a67 vcvt.f32.u32 s15, s15 800af9a: eddf 6a48 vldr s13, [pc, #288] @ 800b0bc 800af9e: ee86 7aa7 vdiv.f32 s14, s13, s15 800afa2: 4b40 ldr r3, [pc, #256] @ (800b0a4 ) 800afa4: 6b1b ldr r3, [r3, #48] @ 0x30 800afa6: f3c3 0308 ubfx r3, r3, #0, #9 800afaa: ee07 3a90 vmov s15, r3 800afae: eef8 6a67 vcvt.f32.u32 s13, s15 800afb2: ed97 6a02 vldr s12, [r7, #8] 800afb6: eddf 5a3f vldr s11, [pc, #252] @ 800b0b4 800afba: eec6 7a25 vdiv.f32 s15, s12, s11 800afbe: ee76 7aa7 vadd.f32 s15, s13, s15 800afc2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800afc6: ee77 7aa6 vadd.f32 s15, s15, s13 800afca: ee67 7a27 vmul.f32 s15, s14, s15 800afce: edc7 7a07 vstr s15, [r7, #28] break; 800afd2: e043 b.n 800b05c case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800afd4: 693b ldr r3, [r7, #16] 800afd6: ee07 3a90 vmov s15, r3 800afda: eef8 7a67 vcvt.f32.u32 s15, s15 800afde: eddf 6a38 vldr s13, [pc, #224] @ 800b0c0 800afe2: ee86 7aa7 vdiv.f32 s14, s13, s15 800afe6: 4b2f ldr r3, [pc, #188] @ (800b0a4 ) 800afe8: 6b1b ldr r3, [r3, #48] @ 0x30 800afea: f3c3 0308 ubfx r3, r3, #0, #9 800afee: ee07 3a90 vmov s15, r3 800aff2: eef8 6a67 vcvt.f32.u32 s13, s15 800aff6: ed97 6a02 vldr s12, [r7, #8] 800affa: eddf 5a2e vldr s11, [pc, #184] @ 800b0b4 800affe: eec6 7a25 vdiv.f32 s15, s12, s11 800b002: ee76 7aa7 vadd.f32 s15, s13, s15 800b006: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800b00a: ee77 7aa6 vadd.f32 s15, s15, s13 800b00e: ee67 7a27 vmul.f32 s15, s14, s15 800b012: edc7 7a07 vstr s15, [r7, #28] break; 800b016: e021 b.n 800b05c default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800b018: 693b ldr r3, [r7, #16] 800b01a: ee07 3a90 vmov s15, r3 800b01e: eef8 7a67 vcvt.f32.u32 s15, s15 800b022: eddf 6a26 vldr s13, [pc, #152] @ 800b0bc 800b026: ee86 7aa7 vdiv.f32 s14, s13, s15 800b02a: 4b1e ldr r3, [pc, #120] @ (800b0a4 ) 800b02c: 6b1b ldr r3, [r3, #48] @ 0x30 800b02e: f3c3 0308 ubfx r3, r3, #0, #9 800b032: ee07 3a90 vmov s15, r3 800b036: eef8 6a67 vcvt.f32.u32 s13, s15 800b03a: ed97 6a02 vldr s12, [r7, #8] 800b03e: eddf 5a1d vldr s11, [pc, #116] @ 800b0b4 800b042: eec6 7a25 vdiv.f32 s15, s12, s11 800b046: ee76 7aa7 vadd.f32 s15, s13, s15 800b04a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800b04e: ee77 7aa6 vadd.f32 s15, s15, s13 800b052: ee67 7a27 vmul.f32 s15, s14, s15 800b056: edc7 7a07 vstr s15, [r7, #28] break; 800b05a: bf00 nop } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; 800b05c: 4b11 ldr r3, [pc, #68] @ (800b0a4 ) 800b05e: 6b1b ldr r3, [r3, #48] @ 0x30 800b060: 0a5b lsrs r3, r3, #9 800b062: f003 037f and.w r3, r3, #127 @ 0x7f 800b066: 3301 adds r3, #1 800b068: 603b str r3, [r7, #0] sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); 800b06a: 683b ldr r3, [r7, #0] 800b06c: ee07 3a90 vmov s15, r3 800b070: eeb8 7a67 vcvt.f32.u32 s14, s15 800b074: edd7 6a07 vldr s13, [r7, #28] 800b078: eec6 7a87 vdiv.f32 s15, s13, s14 800b07c: eefc 7ae7 vcvt.u32.f32 s15, s15 800b080: ee17 3a90 vmov r3, s15 800b084: 61bb str r3, [r7, #24] } else { sysclockfreq = 0U; } break; 800b086: e005 b.n 800b094 sysclockfreq = 0U; 800b088: 2300 movs r3, #0 800b08a: 61bb str r3, [r7, #24] break; 800b08c: e002 b.n 800b094 default: sysclockfreq = CSI_VALUE; 800b08e: 4b07 ldr r3, [pc, #28] @ (800b0ac ) 800b090: 61bb str r3, [r7, #24] break; 800b092: bf00 nop } return sysclockfreq; 800b094: 69bb ldr r3, [r7, #24] } 800b096: 4618 mov r0, r3 800b098: 3724 adds r7, #36 @ 0x24 800b09a: 46bd mov sp, r7 800b09c: f85d 7b04 ldr.w r7, [sp], #4 800b0a0: 4770 bx lr 800b0a2: bf00 nop 800b0a4: 58024400 .word 0x58024400 800b0a8: 03d09000 .word 0x03d09000 800b0ac: 003d0900 .word 0x003d0900 800b0b0: 017d7840 .word 0x017d7840 800b0b4: 46000000 .word 0x46000000 800b0b8: 4c742400 .word 0x4c742400 800b0bc: 4a742400 .word 0x4a742400 800b0c0: 4bbebc20 .word 0x4bbebc20 0800b0c4 : * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 800b0c4: b580 push {r7, lr} 800b0c6: b082 sub sp, #8 800b0c8: af00 add r7, sp, #0 uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 800b0ca: f7ff fe81 bl 800add0 800b0ce: 4602 mov r2, r0 800b0d0: 4b10 ldr r3, [pc, #64] @ (800b114 ) 800b0d2: 699b ldr r3, [r3, #24] 800b0d4: 0a1b lsrs r3, r3, #8 800b0d6: f003 030f and.w r3, r3, #15 800b0da: 490f ldr r1, [pc, #60] @ (800b118 ) 800b0dc: 5ccb ldrb r3, [r1, r3] 800b0de: f003 031f and.w r3, r3, #31 800b0e2: fa22 f303 lsr.w r3, r2, r3 800b0e6: 607b str r3, [r7, #4] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800b0e8: 4b0a ldr r3, [pc, #40] @ (800b114 ) 800b0ea: 699b ldr r3, [r3, #24] 800b0ec: f003 030f and.w r3, r3, #15 800b0f0: 4a09 ldr r2, [pc, #36] @ (800b118 ) 800b0f2: 5cd3 ldrb r3, [r2, r3] 800b0f4: f003 031f and.w r3, r3, #31 800b0f8: 687a ldr r2, [r7, #4] 800b0fa: fa22 f303 lsr.w r3, r2, r3 800b0fe: 4a07 ldr r2, [pc, #28] @ (800b11c ) 800b100: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 800b102: 4a07 ldr r2, [pc, #28] @ (800b120 ) 800b104: 687b ldr r3, [r7, #4] 800b106: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ return SystemD2Clock; 800b108: 4b04 ldr r3, [pc, #16] @ (800b11c ) 800b10a: 681b ldr r3, [r3, #0] } 800b10c: 4618 mov r0, r3 800b10e: 3708 adds r7, #8 800b110: 46bd mov sp, r7 800b112: bd80 pop {r7, pc} 800b114: 58024400 .word 0x58024400 800b118: 080175c8 .word 0x080175c8 800b11c: 24000038 .word 0x24000038 800b120: 24000034 .word 0x24000034 0800b124 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 800b124: b580 push {r7, lr} 800b126: af00 add r7, sp, #0 #if defined (RCC_D2CFGR_D2PPRE1) /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); 800b128: f7ff ffcc bl 800b0c4 800b12c: 4602 mov r2, r0 800b12e: 4b06 ldr r3, [pc, #24] @ (800b148 ) 800b130: 69db ldr r3, [r3, #28] 800b132: 091b lsrs r3, r3, #4 800b134: f003 0307 and.w r3, r3, #7 800b138: 4904 ldr r1, [pc, #16] @ (800b14c ) 800b13a: 5ccb ldrb r3, [r1, r3] 800b13c: f003 031f and.w r3, r3, #31 800b140: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); #endif } 800b144: 4618 mov r0, r3 800b146: bd80 pop {r7, pc} 800b148: 58024400 .word 0x58024400 800b14c: 080175c8 .word 0x080175c8 0800b150 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 800b150: b580 push {r7, lr} 800b152: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ #if defined(RCC_D2CFGR_D2PPRE2) return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); 800b154: f7ff ffb6 bl 800b0c4 800b158: 4602 mov r2, r0 800b15a: 4b06 ldr r3, [pc, #24] @ (800b174 ) 800b15c: 69db ldr r3, [r3, #28] 800b15e: 0a1b lsrs r3, r3, #8 800b160: f003 0307 and.w r3, r3, #7 800b164: 4904 ldr r1, [pc, #16] @ (800b178 ) 800b166: 5ccb ldrb r3, [r1, r3] 800b168: f003 031f and.w r3, r3, #31 800b16c: fa22 f303 lsr.w r3, r2, r3 #else return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); #endif } 800b170: 4618 mov r0, r3 800b172: bd80 pop {r7, pc} 800b174: 58024400 .word 0x58024400 800b178: 080175c8 .word 0x080175c8 0800b17c : * will be configured. * @param pFLatency: Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 800b17c: b480 push {r7} 800b17e: b083 sub sp, #12 800b180: af00 add r7, sp, #0 800b182: 6078 str r0, [r7, #4] 800b184: 6039 str r1, [r7, #0] /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | 800b186: 687b ldr r3, [r7, #4] 800b188: 223f movs r2, #63 @ 0x3f 800b18a: 601a str r2, [r3, #0] RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ; /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 800b18c: 4b1a ldr r3, [pc, #104] @ (800b1f8 ) 800b18e: 691b ldr r3, [r3, #16] 800b190: f003 0207 and.w r2, r3, #7 800b194: 687b ldr r3, [r7, #4] 800b196: 605a str r2, [r3, #4] #if defined(RCC_D1CFGR_D1CPRE) /* Get the SYSCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE); 800b198: 4b17 ldr r3, [pc, #92] @ (800b1f8 ) 800b19a: 699b ldr r3, [r3, #24] 800b19c: f403 6270 and.w r2, r3, #3840 @ 0xf00 800b1a0: 687b ldr r3, [r7, #4] 800b1a2: 609a str r2, [r3, #8] /* Get the D1HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE); 800b1a4: 4b14 ldr r3, [pc, #80] @ (800b1f8 ) 800b1a6: 699b ldr r3, [r3, #24] 800b1a8: f003 020f and.w r2, r3, #15 800b1ac: 687b ldr r3, [r7, #4] 800b1ae: 60da str r2, [r3, #12] /* Get the APB3 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE); 800b1b0: 4b11 ldr r3, [pc, #68] @ (800b1f8 ) 800b1b2: 699b ldr r3, [r3, #24] 800b1b4: f003 0270 and.w r2, r3, #112 @ 0x70 800b1b8: 687b ldr r3, [r7, #4] 800b1ba: 611a str r2, [r3, #16] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1); 800b1bc: 4b0e ldr r3, [pc, #56] @ (800b1f8 ) 800b1be: 69db ldr r3, [r3, #28] 800b1c0: f003 0270 and.w r2, r3, #112 @ 0x70 800b1c4: 687b ldr r3, [r7, #4] 800b1c6: 615a str r2, [r3, #20] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2); 800b1c8: 4b0b ldr r3, [pc, #44] @ (800b1f8 ) 800b1ca: 69db ldr r3, [r3, #28] 800b1cc: f403 62e0 and.w r2, r3, #1792 @ 0x700 800b1d0: 687b ldr r3, [r7, #4] 800b1d2: 619a str r2, [r3, #24] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); 800b1d4: 4b08 ldr r3, [pc, #32] @ (800b1f8 ) 800b1d6: 6a1b ldr r3, [r3, #32] 800b1d8: f003 0270 and.w r2, r3, #112 @ 0x70 800b1dc: 687b ldr r3, [r7, #4] 800b1de: 61da str r2, [r3, #28] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE); #endif /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 800b1e0: 4b06 ldr r3, [pc, #24] @ (800b1fc ) 800b1e2: 681b ldr r3, [r3, #0] 800b1e4: f003 020f and.w r2, r3, #15 800b1e8: 683b ldr r3, [r7, #0] 800b1ea: 601a str r2, [r3, #0] } 800b1ec: bf00 nop 800b1ee: 370c adds r7, #12 800b1f0: 46bd mov sp, r7 800b1f2: f85d 7b04 ldr.w r7, [sp], #4 800b1f6: 4770 bx lr 800b1f8: 58024400 .word 0x58024400 800b1fc: 52002000 .word 0x52002000 0800b200 : * (*) : Available on some STM32H7 lines only. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 800b200: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 800b204: b0c8 sub sp, #288 @ 0x120 800b206: af00 add r7, sp, #0 800b208: f8c7 010c str.w r0, [r7, #268] @ 0x10c uint32_t tmpreg; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 800b20c: 2300 movs r3, #0 800b20e: f887 311f strb.w r3, [r7, #287] @ 0x11f HAL_StatusTypeDef status = HAL_OK; /* Final status */ 800b212: 2300 movs r3, #0 800b214: f887 311e strb.w r3, [r7, #286] @ 0x11e /*---------------------------- SPDIFRX configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 800b218: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b21c: e9d3 2300 ldrd r2, r3, [r3] 800b220: f002 6400 and.w r4, r2, #134217728 @ 0x8000000 800b224: 2500 movs r5, #0 800b226: ea54 0305 orrs.w r3, r4, r5 800b22a: d049 beq.n 800b2c0 { switch (PeriphClkInit->SpdifrxClockSelection) 800b22c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b230: 6e9b ldr r3, [r3, #104] @ 0x68 800b232: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800b236: d02f beq.n 800b298 800b238: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800b23c: d828 bhi.n 800b290 800b23e: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800b242: d01a beq.n 800b27a 800b244: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800b248: d822 bhi.n 800b290 800b24a: 2b00 cmp r3, #0 800b24c: d003 beq.n 800b256 800b24e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800b252: d007 beq.n 800b264 800b254: e01c b.n 800b290 { case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800b256: 4bb8 ldr r3, [pc, #736] @ (800b538 ) 800b258: 6adb ldr r3, [r3, #44] @ 0x2c 800b25a: 4ab7 ldr r2, [pc, #732] @ (800b538 ) 800b25c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800b260: 62d3 str r3, [r2, #44] @ 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 800b262: e01a b.n 800b29a case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800b264: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b268: 3308 adds r3, #8 800b26a: 2102 movs r1, #2 800b26c: 4618 mov r0, r3 800b26e: f002 fb45 bl 800d8fc 800b272: 4603 mov r3, r0 800b274: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 800b278: e00f b.n 800b29a case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800b27a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b27e: 3328 adds r3, #40 @ 0x28 800b280: 2102 movs r1, #2 800b282: 4618 mov r0, r3 800b284: f002 fbec bl 800da60 800b288: 4603 mov r3, r0 800b28a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 800b28e: e004 b.n 800b29a /* Internal OSC clock is used as source of SPDIFRX clock*/ /* SPDIFRX clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800b290: 2301 movs r3, #1 800b292: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800b296: e000 b.n 800b29a break; 800b298: bf00 nop } if (ret == HAL_OK) 800b29a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b29e: 2b00 cmp r3, #0 800b2a0: d10a bne.n 800b2b8 { /* Set the source of SPDIFRX clock*/ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 800b2a2: 4ba5 ldr r3, [pc, #660] @ (800b538 ) 800b2a4: 6d1b ldr r3, [r3, #80] @ 0x50 800b2a6: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800b2aa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b2ae: 6e9b ldr r3, [r3, #104] @ 0x68 800b2b0: 4aa1 ldr r2, [pc, #644] @ (800b538 ) 800b2b2: 430b orrs r3, r1 800b2b4: 6513 str r3, [r2, #80] @ 0x50 800b2b6: e003 b.n 800b2c0 } else { /* set overall return value */ status = ret; 800b2b8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b2bc: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 800b2c0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b2c4: e9d3 2300 ldrd r2, r3, [r3] 800b2c8: f402 7880 and.w r8, r2, #256 @ 0x100 800b2cc: f04f 0900 mov.w r9, #0 800b2d0: ea58 0309 orrs.w r3, r8, r9 800b2d4: d047 beq.n 800b366 { switch (PeriphClkInit->Sai1ClockSelection) 800b2d6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b2da: 6d9b ldr r3, [r3, #88] @ 0x58 800b2dc: 2b04 cmp r3, #4 800b2de: d82a bhi.n 800b336 800b2e0: a201 add r2, pc, #4 @ (adr r2, 800b2e8 ) 800b2e2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b2e6: bf00 nop 800b2e8: 0800b2fd .word 0x0800b2fd 800b2ec: 0800b30b .word 0x0800b30b 800b2f0: 0800b321 .word 0x0800b321 800b2f4: 0800b33f .word 0x0800b33f 800b2f8: 0800b33f .word 0x0800b33f { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800b2fc: 4b8e ldr r3, [pc, #568] @ (800b538 ) 800b2fe: 6adb ldr r3, [r3, #44] @ 0x2c 800b300: 4a8d ldr r2, [pc, #564] @ (800b538 ) 800b302: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800b306: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800b308: e01a b.n 800b340 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800b30a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b30e: 3308 adds r3, #8 800b310: 2100 movs r1, #0 800b312: 4618 mov r0, r3 800b314: f002 faf2 bl 800d8fc 800b318: 4603 mov r3, r0 800b31a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800b31e: e00f b.n 800b340 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800b320: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b324: 3328 adds r3, #40 @ 0x28 800b326: 2100 movs r1, #0 800b328: 4618 mov r0, r3 800b32a: f002 fb99 bl 800da60 800b32e: 4603 mov r3, r0 800b330: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800b334: e004 b.n 800b340 /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800b336: 2301 movs r3, #1 800b338: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800b33c: e000 b.n 800b340 break; 800b33e: bf00 nop } if (ret == HAL_OK) 800b340: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b344: 2b00 cmp r3, #0 800b346: d10a bne.n 800b35e { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 800b348: 4b7b ldr r3, [pc, #492] @ (800b538 ) 800b34a: 6d1b ldr r3, [r3, #80] @ 0x50 800b34c: f023 0107 bic.w r1, r3, #7 800b350: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b354: 6d9b ldr r3, [r3, #88] @ 0x58 800b356: 4a78 ldr r2, [pc, #480] @ (800b538 ) 800b358: 430b orrs r3, r1 800b35a: 6513 str r3, [r2, #80] @ 0x50 800b35c: e003 b.n 800b366 } else { /* set overall return value */ status = ret; 800b35e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b362: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #if defined(SAI3) /*---------------------------- SAI2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) 800b366: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b36a: e9d3 2300 ldrd r2, r3, [r3] 800b36e: f402 7a00 and.w sl, r2, #512 @ 0x200 800b372: f04f 0b00 mov.w fp, #0 800b376: ea5a 030b orrs.w r3, sl, fp 800b37a: d04c beq.n 800b416 { switch (PeriphClkInit->Sai23ClockSelection) 800b37c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b380: 6ddb ldr r3, [r3, #92] @ 0x5c 800b382: f5b3 7f80 cmp.w r3, #256 @ 0x100 800b386: d030 beq.n 800b3ea 800b388: f5b3 7f80 cmp.w r3, #256 @ 0x100 800b38c: d829 bhi.n 800b3e2 800b38e: 2bc0 cmp r3, #192 @ 0xc0 800b390: d02d beq.n 800b3ee 800b392: 2bc0 cmp r3, #192 @ 0xc0 800b394: d825 bhi.n 800b3e2 800b396: 2b80 cmp r3, #128 @ 0x80 800b398: d018 beq.n 800b3cc 800b39a: 2b80 cmp r3, #128 @ 0x80 800b39c: d821 bhi.n 800b3e2 800b39e: 2b00 cmp r3, #0 800b3a0: d002 beq.n 800b3a8 800b3a2: 2b40 cmp r3, #64 @ 0x40 800b3a4: d007 beq.n 800b3b6 800b3a6: e01c b.n 800b3e2 { case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800b3a8: 4b63 ldr r3, [pc, #396] @ (800b538 ) 800b3aa: 6adb ldr r3, [r3, #44] @ 0x2c 800b3ac: 4a62 ldr r2, [pc, #392] @ (800b538 ) 800b3ae: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800b3b2: 62d3 str r3, [r2, #44] @ 0x2c /* SAI2/3 clock source configuration done later after clock selection check */ break; 800b3b4: e01c b.n 800b3f0 case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800b3b6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b3ba: 3308 adds r3, #8 800b3bc: 2100 movs r1, #0 800b3be: 4618 mov r0, r3 800b3c0: f002 fa9c bl 800d8fc 800b3c4: 4603 mov r3, r0 800b3c6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 800b3ca: e011 b.n 800b3f0 case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800b3cc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b3d0: 3328 adds r3, #40 @ 0x28 800b3d2: 2100 movs r1, #0 800b3d4: 4618 mov r0, r3 800b3d6: f002 fb43 bl 800da60 800b3da: 4603 mov r3, r0 800b3dc: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 800b3e0: e006 b.n 800b3f0 /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ /* SAI2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800b3e2: 2301 movs r3, #1 800b3e4: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800b3e8: e002 b.n 800b3f0 break; 800b3ea: bf00 nop 800b3ec: e000 b.n 800b3f0 break; 800b3ee: bf00 nop } if (ret == HAL_OK) 800b3f0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b3f4: 2b00 cmp r3, #0 800b3f6: d10a bne.n 800b40e { /* Set the source of SAI2/3 clock*/ __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); 800b3f8: 4b4f ldr r3, [pc, #316] @ (800b538 ) 800b3fa: 6d1b ldr r3, [r3, #80] @ 0x50 800b3fc: f423 71e0 bic.w r1, r3, #448 @ 0x1c0 800b400: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b404: 6ddb ldr r3, [r3, #92] @ 0x5c 800b406: 4a4c ldr r2, [pc, #304] @ (800b538 ) 800b408: 430b orrs r3, r1 800b40a: 6513 str r3, [r2, #80] @ 0x50 800b40c: e003 b.n 800b416 } else { /* set overall return value */ status = ret; 800b40e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b412: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI2B*/ #if defined(SAI4) /*---------------------------- SAI4A configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 800b416: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b41a: e9d3 2300 ldrd r2, r3, [r3] 800b41e: f402 6380 and.w r3, r2, #1024 @ 0x400 800b422: f8c7 3100 str.w r3, [r7, #256] @ 0x100 800b426: 2300 movs r3, #0 800b428: f8c7 3104 str.w r3, [r7, #260] @ 0x104 800b42c: e9d7 1240 ldrd r1, r2, [r7, #256] @ 0x100 800b430: 460b mov r3, r1 800b432: 4313 orrs r3, r2 800b434: d053 beq.n 800b4de { switch (PeriphClkInit->Sai4AClockSelection) 800b436: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b43a: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 800b43e: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800b442: d035 beq.n 800b4b0 800b444: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800b448: d82e bhi.n 800b4a8 800b44a: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800b44e: d031 beq.n 800b4b4 800b450: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800b454: d828 bhi.n 800b4a8 800b456: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800b45a: d01a beq.n 800b492 800b45c: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800b460: d822 bhi.n 800b4a8 800b462: 2b00 cmp r3, #0 800b464: d003 beq.n 800b46e 800b466: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800b46a: d007 beq.n 800b47c 800b46c: e01c b.n 800b4a8 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800b46e: 4b32 ldr r3, [pc, #200] @ (800b538 ) 800b470: 6adb ldr r3, [r3, #44] @ 0x2c 800b472: 4a31 ldr r2, [pc, #196] @ (800b538 ) 800b474: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800b478: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800b47a: e01c b.n 800b4b6 case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800b47c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b480: 3308 adds r3, #8 800b482: 2100 movs r1, #0 800b484: 4618 mov r0, r3 800b486: f002 fa39 bl 800d8fc 800b48a: 4603 mov r3, r0 800b48c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800b490: e011 b.n 800b4b6 case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800b492: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b496: 3328 adds r3, #40 @ 0x28 800b498: 2100 movs r1, #0 800b49a: 4618 mov r0, r3 800b49c: f002 fae0 bl 800da60 800b4a0: 4603 mov r3, r0 800b4a2: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800b4a6: e006 b.n 800b4b6 /* SAI4A clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800b4a8: 2301 movs r3, #1 800b4aa: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800b4ae: e002 b.n 800b4b6 break; 800b4b0: bf00 nop 800b4b2: e000 b.n 800b4b6 break; 800b4b4: bf00 nop } if (ret == HAL_OK) 800b4b6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b4ba: 2b00 cmp r3, #0 800b4bc: d10b bne.n 800b4d6 { /* Set the source of SAI4A clock*/ __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); 800b4be: 4b1e ldr r3, [pc, #120] @ (800b538 ) 800b4c0: 6d9b ldr r3, [r3, #88] @ 0x58 800b4c2: f423 0160 bic.w r1, r3, #14680064 @ 0xe00000 800b4c6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b4ca: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 800b4ce: 4a1a ldr r2, [pc, #104] @ (800b538 ) 800b4d0: 430b orrs r3, r1 800b4d2: 6593 str r3, [r2, #88] @ 0x58 800b4d4: e003 b.n 800b4de } else { /* set overall return value */ status = ret; 800b4d6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b4da: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI4B configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 800b4de: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b4e2: e9d3 2300 ldrd r2, r3, [r3] 800b4e6: f402 6300 and.w r3, r2, #2048 @ 0x800 800b4ea: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 800b4ee: 2300 movs r3, #0 800b4f0: f8c7 30fc str.w r3, [r7, #252] @ 0xfc 800b4f4: e9d7 123e ldrd r1, r2, [r7, #248] @ 0xf8 800b4f8: 460b mov r3, r1 800b4fa: 4313 orrs r3, r2 800b4fc: d056 beq.n 800b5ac { switch (PeriphClkInit->Sai4BClockSelection) 800b4fe: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b502: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 800b506: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800b50a: d038 beq.n 800b57e 800b50c: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800b510: d831 bhi.n 800b576 800b512: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800b516: d034 beq.n 800b582 800b518: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800b51c: d82b bhi.n 800b576 800b51e: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800b522: d01d beq.n 800b560 800b524: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800b528: d825 bhi.n 800b576 800b52a: 2b00 cmp r3, #0 800b52c: d006 beq.n 800b53c 800b52e: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800b532: d00a beq.n 800b54a 800b534: e01f b.n 800b576 800b536: bf00 nop 800b538: 58024400 .word 0x58024400 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800b53c: 4ba2 ldr r3, [pc, #648] @ (800b7c8 ) 800b53e: 6adb ldr r3, [r3, #44] @ 0x2c 800b540: 4aa1 ldr r2, [pc, #644] @ (800b7c8 ) 800b542: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800b546: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800b548: e01c b.n 800b584 case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800b54a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b54e: 3308 adds r3, #8 800b550: 2100 movs r1, #0 800b552: 4618 mov r0, r3 800b554: f002 f9d2 bl 800d8fc 800b558: 4603 mov r3, r0 800b55a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800b55e: e011 b.n 800b584 case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800b560: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b564: 3328 adds r3, #40 @ 0x28 800b566: 2100 movs r1, #0 800b568: 4618 mov r0, r3 800b56a: f002 fa79 bl 800da60 800b56e: 4603 mov r3, r0 800b570: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800b574: e006 b.n 800b584 /* SAI4B clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800b576: 2301 movs r3, #1 800b578: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800b57c: e002 b.n 800b584 break; 800b57e: bf00 nop 800b580: e000 b.n 800b584 break; 800b582: bf00 nop } if (ret == HAL_OK) 800b584: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b588: 2b00 cmp r3, #0 800b58a: d10b bne.n 800b5a4 { /* Set the source of SAI4B clock*/ __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); 800b58c: 4b8e ldr r3, [pc, #568] @ (800b7c8 ) 800b58e: 6d9b ldr r3, [r3, #88] @ 0x58 800b590: f023 61e0 bic.w r1, r3, #117440512 @ 0x7000000 800b594: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b598: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 800b59c: 4a8a ldr r2, [pc, #552] @ (800b7c8 ) 800b59e: 430b orrs r3, r1 800b5a0: 6593 str r3, [r2, #88] @ 0x58 800b5a2: e003 b.n 800b5ac } else { /* set overall return value */ status = ret; 800b5a4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b5a8: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI4*/ #if defined(QUADSPI) /*---------------------------- QSPI configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) 800b5ac: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b5b0: e9d3 2300 ldrd r2, r3, [r3] 800b5b4: f002 7300 and.w r3, r2, #33554432 @ 0x2000000 800b5b8: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0 800b5bc: 2300 movs r3, #0 800b5be: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4 800b5c2: e9d7 123c ldrd r1, r2, [r7, #240] @ 0xf0 800b5c6: 460b mov r3, r1 800b5c8: 4313 orrs r3, r2 800b5ca: d03a beq.n 800b642 { switch (PeriphClkInit->QspiClockSelection) 800b5cc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b5d0: 6cdb ldr r3, [r3, #76] @ 0x4c 800b5d2: 2b30 cmp r3, #48 @ 0x30 800b5d4: d01f beq.n 800b616 800b5d6: 2b30 cmp r3, #48 @ 0x30 800b5d8: d819 bhi.n 800b60e 800b5da: 2b20 cmp r3, #32 800b5dc: d00c beq.n 800b5f8 800b5de: 2b20 cmp r3, #32 800b5e0: d815 bhi.n 800b60e 800b5e2: 2b00 cmp r3, #0 800b5e4: d019 beq.n 800b61a 800b5e6: 2b10 cmp r3, #16 800b5e8: d111 bne.n 800b60e { case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ /* Enable QSPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800b5ea: 4b77 ldr r3, [pc, #476] @ (800b7c8 ) 800b5ec: 6adb ldr r3, [r3, #44] @ 0x2c 800b5ee: 4a76 ldr r2, [pc, #472] @ (800b7c8 ) 800b5f0: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800b5f4: 62d3 str r3, [r2, #44] @ 0x2c /* QSPI clock source configuration done later after clock selection check */ break; 800b5f6: e011 b.n 800b61c case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800b5f8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b5fc: 3308 adds r3, #8 800b5fe: 2102 movs r1, #2 800b600: 4618 mov r0, r3 800b602: f002 f97b bl 800d8fc 800b606: 4603 mov r3, r0 800b608: f887 311f strb.w r3, [r7, #287] @ 0x11f /* QSPI clock source configuration done later after clock selection check */ break; 800b60c: e006 b.n 800b61c case RCC_QSPICLKSOURCE_D1HCLK: /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ break; default: ret = HAL_ERROR; 800b60e: 2301 movs r3, #1 800b610: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800b614: e002 b.n 800b61c break; 800b616: bf00 nop 800b618: e000 b.n 800b61c break; 800b61a: bf00 nop } if (ret == HAL_OK) 800b61c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b620: 2b00 cmp r3, #0 800b622: d10a bne.n 800b63a { /* Set the source of QSPI clock*/ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); 800b624: 4b68 ldr r3, [pc, #416] @ (800b7c8 ) 800b626: 6cdb ldr r3, [r3, #76] @ 0x4c 800b628: f023 0130 bic.w r1, r3, #48 @ 0x30 800b62c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b630: 6cdb ldr r3, [r3, #76] @ 0x4c 800b632: 4a65 ldr r2, [pc, #404] @ (800b7c8 ) 800b634: 430b orrs r3, r1 800b636: 64d3 str r3, [r2, #76] @ 0x4c 800b638: e003 b.n 800b642 } else { /* set overall return value */ status = ret; 800b63a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b63e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 800b642: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b646: e9d3 2300 ldrd r2, r3, [r3] 800b64a: f402 5380 and.w r3, r2, #4096 @ 0x1000 800b64e: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 800b652: 2300 movs r3, #0 800b654: f8c7 30ec str.w r3, [r7, #236] @ 0xec 800b658: e9d7 123a ldrd r1, r2, [r7, #232] @ 0xe8 800b65c: 460b mov r3, r1 800b65e: 4313 orrs r3, r2 800b660: d051 beq.n 800b706 { switch (PeriphClkInit->Spi123ClockSelection) 800b662: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b666: 6e1b ldr r3, [r3, #96] @ 0x60 800b668: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800b66c: d035 beq.n 800b6da 800b66e: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800b672: d82e bhi.n 800b6d2 800b674: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800b678: d031 beq.n 800b6de 800b67a: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800b67e: d828 bhi.n 800b6d2 800b680: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800b684: d01a beq.n 800b6bc 800b686: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800b68a: d822 bhi.n 800b6d2 800b68c: 2b00 cmp r3, #0 800b68e: d003 beq.n 800b698 800b690: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800b694: d007 beq.n 800b6a6 800b696: e01c b.n 800b6d2 { case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800b698: 4b4b ldr r3, [pc, #300] @ (800b7c8 ) 800b69a: 6adb ldr r3, [r3, #44] @ 0x2c 800b69c: 4a4a ldr r2, [pc, #296] @ (800b7c8 ) 800b69e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800b6a2: 62d3 str r3, [r2, #44] @ 0x2c /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800b6a4: e01c b.n 800b6e0 case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800b6a6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b6aa: 3308 adds r3, #8 800b6ac: 2100 movs r1, #0 800b6ae: 4618 mov r0, r3 800b6b0: f002 f924 bl 800d8fc 800b6b4: 4603 mov r3, r0 800b6b6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800b6ba: e011 b.n 800b6e0 case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800b6bc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b6c0: 3328 adds r3, #40 @ 0x28 800b6c2: 2100 movs r1, #0 800b6c4: 4618 mov r0, r3 800b6c6: f002 f9cb bl 800da60 800b6ca: 4603 mov r3, r0 800b6cc: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800b6d0: e006 b.n 800b6e0 /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ /* SPI1/2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800b6d2: 2301 movs r3, #1 800b6d4: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800b6d8: e002 b.n 800b6e0 break; 800b6da: bf00 nop 800b6dc: e000 b.n 800b6e0 break; 800b6de: bf00 nop } if (ret == HAL_OK) 800b6e0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b6e4: 2b00 cmp r3, #0 800b6e6: d10a bne.n 800b6fe { /* Set the source of SPI1/2/3 clock*/ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 800b6e8: 4b37 ldr r3, [pc, #220] @ (800b7c8 ) 800b6ea: 6d1b ldr r3, [r3, #80] @ 0x50 800b6ec: f423 41e0 bic.w r1, r3, #28672 @ 0x7000 800b6f0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b6f4: 6e1b ldr r3, [r3, #96] @ 0x60 800b6f6: 4a34 ldr r2, [pc, #208] @ (800b7c8 ) 800b6f8: 430b orrs r3, r1 800b6fa: 6513 str r3, [r2, #80] @ 0x50 800b6fc: e003 b.n 800b706 } else { /* set overall return value */ status = ret; 800b6fe: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b702: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI4/5 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 800b706: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b70a: e9d3 2300 ldrd r2, r3, [r3] 800b70e: f402 5300 and.w r3, r2, #8192 @ 0x2000 800b712: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 800b716: 2300 movs r3, #0 800b718: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 800b71c: e9d7 1238 ldrd r1, r2, [r7, #224] @ 0xe0 800b720: 460b mov r3, r1 800b722: 4313 orrs r3, r2 800b724: d056 beq.n 800b7d4 { switch (PeriphClkInit->Spi45ClockSelection) 800b726: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b72a: 6e5b ldr r3, [r3, #100] @ 0x64 800b72c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800b730: d033 beq.n 800b79a 800b732: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800b736: d82c bhi.n 800b792 800b738: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800b73c: d02f beq.n 800b79e 800b73e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800b742: d826 bhi.n 800b792 800b744: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800b748: d02b beq.n 800b7a2 800b74a: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800b74e: d820 bhi.n 800b792 800b750: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800b754: d012 beq.n 800b77c 800b756: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800b75a: d81a bhi.n 800b792 800b75c: 2b00 cmp r3, #0 800b75e: d022 beq.n 800b7a6 800b760: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800b764: d115 bne.n 800b792 /* SPI4/5 clock source configuration done later after clock selection check */ break; case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800b766: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b76a: 3308 adds r3, #8 800b76c: 2101 movs r1, #1 800b76e: 4618 mov r0, r3 800b770: f002 f8c4 bl 800d8fc 800b774: 4603 mov r3, r0 800b776: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 800b77a: e015 b.n 800b7a8 case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800b77c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b780: 3328 adds r3, #40 @ 0x28 800b782: 2101 movs r1, #1 800b784: 4618 mov r0, r3 800b786: f002 f96b bl 800da60 800b78a: 4603 mov r3, r0 800b78c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 800b790: e00a b.n 800b7a8 /* HSE, oscillator is used as source of SPI4/5 clock */ /* SPI4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800b792: 2301 movs r3, #1 800b794: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800b798: e006 b.n 800b7a8 break; 800b79a: bf00 nop 800b79c: e004 b.n 800b7a8 break; 800b79e: bf00 nop 800b7a0: e002 b.n 800b7a8 break; 800b7a2: bf00 nop 800b7a4: e000 b.n 800b7a8 break; 800b7a6: bf00 nop } if (ret == HAL_OK) 800b7a8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b7ac: 2b00 cmp r3, #0 800b7ae: d10d bne.n 800b7cc { /* Set the source of SPI4/5 clock*/ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 800b7b0: 4b05 ldr r3, [pc, #20] @ (800b7c8 ) 800b7b2: 6d1b ldr r3, [r3, #80] @ 0x50 800b7b4: f423 21e0 bic.w r1, r3, #458752 @ 0x70000 800b7b8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b7bc: 6e5b ldr r3, [r3, #100] @ 0x64 800b7be: 4a02 ldr r2, [pc, #8] @ (800b7c8 ) 800b7c0: 430b orrs r3, r1 800b7c2: 6513 str r3, [r2, #80] @ 0x50 800b7c4: e006 b.n 800b7d4 800b7c6: bf00 nop 800b7c8: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800b7cc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b7d0: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI6 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 800b7d4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b7d8: e9d3 2300 ldrd r2, r3, [r3] 800b7dc: f402 4380 and.w r3, r2, #16384 @ 0x4000 800b7e0: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 800b7e4: 2300 movs r3, #0 800b7e6: f8c7 30dc str.w r3, [r7, #220] @ 0xdc 800b7ea: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 800b7ee: 460b mov r3, r1 800b7f0: 4313 orrs r3, r2 800b7f2: d055 beq.n 800b8a0 { switch (PeriphClkInit->Spi6ClockSelection) 800b7f4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b7f8: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 800b7fc: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800b800: d033 beq.n 800b86a 800b802: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800b806: d82c bhi.n 800b862 800b808: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800b80c: d02f beq.n 800b86e 800b80e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800b812: d826 bhi.n 800b862 800b814: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800b818: d02b beq.n 800b872 800b81a: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800b81e: d820 bhi.n 800b862 800b820: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800b824: d012 beq.n 800b84c 800b826: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800b82a: d81a bhi.n 800b862 800b82c: 2b00 cmp r3, #0 800b82e: d022 beq.n 800b876 800b830: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800b834: d115 bne.n 800b862 /* SPI6 clock source configuration done later after clock selection check */ break; case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800b836: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b83a: 3308 adds r3, #8 800b83c: 2101 movs r1, #1 800b83e: 4618 mov r0, r3 800b840: f002 f85c bl 800d8fc 800b844: 4603 mov r3, r0 800b846: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 800b84a: e015 b.n 800b878 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800b84c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b850: 3328 adds r3, #40 @ 0x28 800b852: 2101 movs r1, #1 800b854: 4618 mov r0, r3 800b856: f002 f903 bl 800da60 800b85a: 4603 mov r3, r0 800b85c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 800b860: e00a b.n 800b878 /* SPI6 clock source configuration done later after clock selection check */ break; #endif default: ret = HAL_ERROR; 800b862: 2301 movs r3, #1 800b864: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800b868: e006 b.n 800b878 break; 800b86a: bf00 nop 800b86c: e004 b.n 800b878 break; 800b86e: bf00 nop 800b870: e002 b.n 800b878 break; 800b872: bf00 nop 800b874: e000 b.n 800b878 break; 800b876: bf00 nop } if (ret == HAL_OK) 800b878: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b87c: 2b00 cmp r3, #0 800b87e: d10b bne.n 800b898 { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 800b880: 4ba3 ldr r3, [pc, #652] @ (800bb10 ) 800b882: 6d9b ldr r3, [r3, #88] @ 0x58 800b884: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 800b888: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b88c: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 800b890: 4a9f ldr r2, [pc, #636] @ (800bb10 ) 800b892: 430b orrs r3, r1 800b894: 6593 str r3, [r2, #88] @ 0x58 800b896: e003 b.n 800b8a0 } else { /* set overall return value */ status = ret; 800b898: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b89c: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*DSI*/ #if defined(FDCAN1) || defined(FDCAN2) /*---------------------------- FDCAN configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 800b8a0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b8a4: e9d3 2300 ldrd r2, r3, [r3] 800b8a8: f402 4300 and.w r3, r2, #32768 @ 0x8000 800b8ac: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 800b8b0: 2300 movs r3, #0 800b8b2: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 800b8b6: e9d7 1234 ldrd r1, r2, [r7, #208] @ 0xd0 800b8ba: 460b mov r3, r1 800b8bc: 4313 orrs r3, r2 800b8be: d037 beq.n 800b930 { switch (PeriphClkInit->FdcanClockSelection) 800b8c0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b8c4: 6f1b ldr r3, [r3, #112] @ 0x70 800b8c6: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800b8ca: d00e beq.n 800b8ea 800b8cc: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800b8d0: d816 bhi.n 800b900 800b8d2: 2b00 cmp r3, #0 800b8d4: d018 beq.n 800b908 800b8d6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800b8da: d111 bne.n 800b900 { case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ /* Enable FDCAN Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800b8dc: 4b8c ldr r3, [pc, #560] @ (800bb10 ) 800b8de: 6adb ldr r3, [r3, #44] @ 0x2c 800b8e0: 4a8b ldr r2, [pc, #556] @ (800bb10 ) 800b8e2: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800b8e6: 62d3 str r3, [r2, #44] @ 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 800b8e8: e00f b.n 800b90a case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800b8ea: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b8ee: 3308 adds r3, #8 800b8f0: 2101 movs r1, #1 800b8f2: 4618 mov r0, r3 800b8f4: f002 f802 bl 800d8fc 800b8f8: 4603 mov r3, r0 800b8fa: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FDCAN clock source configuration done later after clock selection check */ break; 800b8fe: e004 b.n 800b90a /* HSE is used as clock source for FDCAN*/ /* FDCAN clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800b900: 2301 movs r3, #1 800b902: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800b906: e000 b.n 800b90a break; 800b908: bf00 nop } if (ret == HAL_OK) 800b90a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b90e: 2b00 cmp r3, #0 800b910: d10a bne.n 800b928 { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 800b912: 4b7f ldr r3, [pc, #508] @ (800bb10 ) 800b914: 6d1b ldr r3, [r3, #80] @ 0x50 800b916: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 800b91a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b91e: 6f1b ldr r3, [r3, #112] @ 0x70 800b920: 4a7b ldr r2, [pc, #492] @ (800bb10 ) 800b922: 430b orrs r3, r1 800b924: 6513 str r3, [r2, #80] @ 0x50 800b926: e003 b.n 800b930 } else { /* set overall return value */ status = ret; 800b928: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b92c: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*FDCAN1 || FDCAN2*/ /*---------------------------- FMC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 800b930: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b934: e9d3 2300 ldrd r2, r3, [r3] 800b938: f002 7380 and.w r3, r2, #16777216 @ 0x1000000 800b93c: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 800b940: 2300 movs r3, #0 800b942: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 800b946: e9d7 1232 ldrd r1, r2, [r7, #200] @ 0xc8 800b94a: 460b mov r3, r1 800b94c: 4313 orrs r3, r2 800b94e: d039 beq.n 800b9c4 { switch (PeriphClkInit->FmcClockSelection) 800b950: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b954: 6c9b ldr r3, [r3, #72] @ 0x48 800b956: 2b03 cmp r3, #3 800b958: d81c bhi.n 800b994 800b95a: a201 add r2, pc, #4 @ (adr r2, 800b960 ) 800b95c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b960: 0800b99d .word 0x0800b99d 800b964: 0800b971 .word 0x0800b971 800b968: 0800b97f .word 0x0800b97f 800b96c: 0800b99d .word 0x0800b99d { case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ /* Enable FMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800b970: 4b67 ldr r3, [pc, #412] @ (800bb10 ) 800b972: 6adb ldr r3, [r3, #44] @ 0x2c 800b974: 4a66 ldr r2, [pc, #408] @ (800bb10 ) 800b976: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800b97a: 62d3 str r3, [r2, #44] @ 0x2c /* FMC clock source configuration done later after clock selection check */ break; 800b97c: e00f b.n 800b99e case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800b97e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b982: 3308 adds r3, #8 800b984: 2102 movs r1, #2 800b986: 4618 mov r0, r3 800b988: f001 ffb8 bl 800d8fc 800b98c: 4603 mov r3, r0 800b98e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FMC clock source configuration done later after clock selection check */ break; 800b992: e004 b.n 800b99e case RCC_FMCCLKSOURCE_HCLK: /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ break; default: ret = HAL_ERROR; 800b994: 2301 movs r3, #1 800b996: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800b99a: e000 b.n 800b99e break; 800b99c: bf00 nop } if (ret == HAL_OK) 800b99e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b9a2: 2b00 cmp r3, #0 800b9a4: d10a bne.n 800b9bc { /* Set the source of FMC clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 800b9a6: 4b5a ldr r3, [pc, #360] @ (800bb10 ) 800b9a8: 6cdb ldr r3, [r3, #76] @ 0x4c 800b9aa: f023 0103 bic.w r1, r3, #3 800b9ae: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b9b2: 6c9b ldr r3, [r3, #72] @ 0x48 800b9b4: 4a56 ldr r2, [pc, #344] @ (800bb10 ) 800b9b6: 430b orrs r3, r1 800b9b8: 64d3 str r3, [r2, #76] @ 0x4c 800b9ba: e003 b.n 800b9c4 } else { /* set overall return value */ status = ret; 800b9bc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800b9c0: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- RTC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 800b9c4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800b9c8: e9d3 2300 ldrd r2, r3, [r3] 800b9cc: f402 0380 and.w r3, r2, #4194304 @ 0x400000 800b9d0: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 800b9d4: 2300 movs r3, #0 800b9d6: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 800b9da: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 800b9de: 460b mov r3, r1 800b9e0: 4313 orrs r3, r2 800b9e2: f000 809f beq.w 800bb24 { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 800b9e6: 4b4b ldr r3, [pc, #300] @ (800bb14 ) 800b9e8: 681b ldr r3, [r3, #0] 800b9ea: 4a4a ldr r2, [pc, #296] @ (800bb14 ) 800b9ec: f443 7380 orr.w r3, r3, #256 @ 0x100 800b9f0: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800b9f2: f7f9 f837 bl 8004a64 800b9f6: f8c7 0118 str.w r0, [r7, #280] @ 0x118 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800b9fa: e00b b.n 800ba14 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800b9fc: f7f9 f832 bl 8004a64 800ba00: 4602 mov r2, r0 800ba02: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 800ba06: 1ad3 subs r3, r2, r3 800ba08: 2b64 cmp r3, #100 @ 0x64 800ba0a: d903 bls.n 800ba14 { ret = HAL_TIMEOUT; 800ba0c: 2303 movs r3, #3 800ba0e: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ba12: e005 b.n 800ba20 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800ba14: 4b3f ldr r3, [pc, #252] @ (800bb14 ) 800ba16: 681b ldr r3, [r3, #0] 800ba18: f403 7380 and.w r3, r3, #256 @ 0x100 800ba1c: 2b00 cmp r3, #0 800ba1e: d0ed beq.n 800b9fc } } if (ret == HAL_OK) 800ba20: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ba24: 2b00 cmp r3, #0 800ba26: d179 bne.n 800bb1c { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 800ba28: 4b39 ldr r3, [pc, #228] @ (800bb10 ) 800ba2a: 6f1a ldr r2, [r3, #112] @ 0x70 800ba2c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ba30: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800ba34: 4053 eors r3, r2 800ba36: f403 7340 and.w r3, r3, #768 @ 0x300 800ba3a: 2b00 cmp r3, #0 800ba3c: d015 beq.n 800ba6a { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800ba3e: 4b34 ldr r3, [pc, #208] @ (800bb10 ) 800ba40: 6f1b ldr r3, [r3, #112] @ 0x70 800ba42: f423 7340 bic.w r3, r3, #768 @ 0x300 800ba46: f8c7 3114 str.w r3, [r7, #276] @ 0x114 /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 800ba4a: 4b31 ldr r3, [pc, #196] @ (800bb10 ) 800ba4c: 6f1b ldr r3, [r3, #112] @ 0x70 800ba4e: 4a30 ldr r2, [pc, #192] @ (800bb10 ) 800ba50: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800ba54: 6713 str r3, [r2, #112] @ 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 800ba56: 4b2e ldr r3, [pc, #184] @ (800bb10 ) 800ba58: 6f1b ldr r3, [r3, #112] @ 0x70 800ba5a: 4a2d ldr r2, [pc, #180] @ (800bb10 ) 800ba5c: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ba60: 6713 str r3, [r2, #112] @ 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg; 800ba62: 4a2b ldr r2, [pc, #172] @ (800bb10 ) 800ba64: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800ba68: 6713 str r3, [r2, #112] @ 0x70 } /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 800ba6a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ba6e: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800ba72: f5b3 7f80 cmp.w r3, #256 @ 0x100 800ba76: d118 bne.n 800baaa { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ba78: f7f8 fff4 bl 8004a64 800ba7c: f8c7 0118 str.w r0, [r7, #280] @ 0x118 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800ba80: e00d b.n 800ba9e { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800ba82: f7f8 ffef bl 8004a64 800ba86: 4602 mov r2, r0 800ba88: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 800ba8c: 1ad2 subs r2, r2, r3 800ba8e: f241 3388 movw r3, #5000 @ 0x1388 800ba92: 429a cmp r2, r3 800ba94: d903 bls.n 800ba9e { ret = HAL_TIMEOUT; 800ba96: 2303 movs r3, #3 800ba98: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ba9c: e005 b.n 800baaa while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800ba9e: 4b1c ldr r3, [pc, #112] @ (800bb10 ) 800baa0: 6f1b ldr r3, [r3, #112] @ 0x70 800baa2: f003 0302 and.w r3, r3, #2 800baa6: 2b00 cmp r3, #0 800baa8: d0eb beq.n 800ba82 } } } if (ret == HAL_OK) 800baaa: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800baae: 2b00 cmp r3, #0 800bab0: d129 bne.n 800bb06 { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 800bab2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bab6: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800baba: f403 7340 and.w r3, r3, #768 @ 0x300 800babe: f5b3 7f40 cmp.w r3, #768 @ 0x300 800bac2: d10e bne.n 800bae2 800bac4: 4b12 ldr r3, [pc, #72] @ (800bb10 ) 800bac6: 691b ldr r3, [r3, #16] 800bac8: f423 517c bic.w r1, r3, #16128 @ 0x3f00 800bacc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bad0: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800bad4: 091a lsrs r2, r3, #4 800bad6: 4b10 ldr r3, [pc, #64] @ (800bb18 ) 800bad8: 4013 ands r3, r2 800bada: 4a0d ldr r2, [pc, #52] @ (800bb10 ) 800badc: 430b orrs r3, r1 800bade: 6113 str r3, [r2, #16] 800bae0: e005 b.n 800baee 800bae2: 4b0b ldr r3, [pc, #44] @ (800bb10 ) 800bae4: 691b ldr r3, [r3, #16] 800bae6: 4a0a ldr r2, [pc, #40] @ (800bb10 ) 800bae8: f423 537c bic.w r3, r3, #16128 @ 0x3f00 800baec: 6113 str r3, [r2, #16] 800baee: 4b08 ldr r3, [pc, #32] @ (800bb10 ) 800baf0: 6f19 ldr r1, [r3, #112] @ 0x70 800baf2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800baf6: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800bafa: f3c3 030b ubfx r3, r3, #0, #12 800bafe: 4a04 ldr r2, [pc, #16] @ (800bb10 ) 800bb00: 430b orrs r3, r1 800bb02: 6713 str r3, [r2, #112] @ 0x70 800bb04: e00e b.n 800bb24 } else { /* set overall return value */ status = ret; 800bb06: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800bb0a: f887 311e strb.w r3, [r7, #286] @ 0x11e 800bb0e: e009 b.n 800bb24 800bb10: 58024400 .word 0x58024400 800bb14: 58024800 .word 0x58024800 800bb18: 00ffffcf .word 0x00ffffcf } } else { /* set overall return value */ status = ret; 800bb1c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800bb20: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART1/6 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 800bb24: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bb28: e9d3 2300 ldrd r2, r3, [r3] 800bb2c: f002 0301 and.w r3, r2, #1 800bb30: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 800bb34: 2300 movs r3, #0 800bb36: f8c7 30bc str.w r3, [r7, #188] @ 0xbc 800bb3a: e9d7 122e ldrd r1, r2, [r7, #184] @ 0xb8 800bb3e: 460b mov r3, r1 800bb40: 4313 orrs r3, r2 800bb42: f000 8089 beq.w 800bc58 { switch (PeriphClkInit->Usart16ClockSelection) 800bb46: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bb4a: 6fdb ldr r3, [r3, #124] @ 0x7c 800bb4c: 2b28 cmp r3, #40 @ 0x28 800bb4e: d86b bhi.n 800bc28 800bb50: a201 add r2, pc, #4 @ (adr r2, 800bb58 ) 800bb52: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800bb56: bf00 nop 800bb58: 0800bc31 .word 0x0800bc31 800bb5c: 0800bc29 .word 0x0800bc29 800bb60: 0800bc29 .word 0x0800bc29 800bb64: 0800bc29 .word 0x0800bc29 800bb68: 0800bc29 .word 0x0800bc29 800bb6c: 0800bc29 .word 0x0800bc29 800bb70: 0800bc29 .word 0x0800bc29 800bb74: 0800bc29 .word 0x0800bc29 800bb78: 0800bbfd .word 0x0800bbfd 800bb7c: 0800bc29 .word 0x0800bc29 800bb80: 0800bc29 .word 0x0800bc29 800bb84: 0800bc29 .word 0x0800bc29 800bb88: 0800bc29 .word 0x0800bc29 800bb8c: 0800bc29 .word 0x0800bc29 800bb90: 0800bc29 .word 0x0800bc29 800bb94: 0800bc29 .word 0x0800bc29 800bb98: 0800bc13 .word 0x0800bc13 800bb9c: 0800bc29 .word 0x0800bc29 800bba0: 0800bc29 .word 0x0800bc29 800bba4: 0800bc29 .word 0x0800bc29 800bba8: 0800bc29 .word 0x0800bc29 800bbac: 0800bc29 .word 0x0800bc29 800bbb0: 0800bc29 .word 0x0800bc29 800bbb4: 0800bc29 .word 0x0800bc29 800bbb8: 0800bc31 .word 0x0800bc31 800bbbc: 0800bc29 .word 0x0800bc29 800bbc0: 0800bc29 .word 0x0800bc29 800bbc4: 0800bc29 .word 0x0800bc29 800bbc8: 0800bc29 .word 0x0800bc29 800bbcc: 0800bc29 .word 0x0800bc29 800bbd0: 0800bc29 .word 0x0800bc29 800bbd4: 0800bc29 .word 0x0800bc29 800bbd8: 0800bc31 .word 0x0800bc31 800bbdc: 0800bc29 .word 0x0800bc29 800bbe0: 0800bc29 .word 0x0800bc29 800bbe4: 0800bc29 .word 0x0800bc29 800bbe8: 0800bc29 .word 0x0800bc29 800bbec: 0800bc29 .word 0x0800bc29 800bbf0: 0800bc29 .word 0x0800bc29 800bbf4: 0800bc29 .word 0x0800bc29 800bbf8: 0800bc31 .word 0x0800bc31 case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ /* USART1/6 clock source configuration done later after clock selection check */ break; case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800bbfc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bc00: 3308 adds r3, #8 800bc02: 2101 movs r1, #1 800bc04: 4618 mov r0, r3 800bc06: f001 fe79 bl 800d8fc 800bc0a: 4603 mov r3, r0 800bc0c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 800bc10: e00f b.n 800bc32 case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800bc12: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bc16: 3328 adds r3, #40 @ 0x28 800bc18: 2101 movs r1, #1 800bc1a: 4618 mov r0, r3 800bc1c: f001 ff20 bl 800da60 800bc20: 4603 mov r3, r0 800bc22: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 800bc26: e004 b.n 800bc32 /* LSE, oscillator is used as source of USART1/6 clock */ /* USART1/6 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800bc28: 2301 movs r3, #1 800bc2a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800bc2e: e000 b.n 800bc32 break; 800bc30: bf00 nop } if (ret == HAL_OK) 800bc32: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800bc36: 2b00 cmp r3, #0 800bc38: d10a bne.n 800bc50 { /* Set the source of USART1/6 clock */ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 800bc3a: 4bbf ldr r3, [pc, #764] @ (800bf38 ) 800bc3c: 6d5b ldr r3, [r3, #84] @ 0x54 800bc3e: f023 0138 bic.w r1, r3, #56 @ 0x38 800bc42: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bc46: 6fdb ldr r3, [r3, #124] @ 0x7c 800bc48: 4abb ldr r2, [pc, #748] @ (800bf38 ) 800bc4a: 430b orrs r3, r1 800bc4c: 6553 str r3, [r2, #84] @ 0x54 800bc4e: e003 b.n 800bc58 } else { /* set overall return value */ status = ret; 800bc50: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800bc54: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 800bc58: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bc5c: e9d3 2300 ldrd r2, r3, [r3] 800bc60: f002 0302 and.w r3, r2, #2 800bc64: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 800bc68: 2300 movs r3, #0 800bc6a: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 800bc6e: e9d7 122c ldrd r1, r2, [r7, #176] @ 0xb0 800bc72: 460b mov r3, r1 800bc74: 4313 orrs r3, r2 800bc76: d041 beq.n 800bcfc { switch (PeriphClkInit->Usart234578ClockSelection) 800bc78: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bc7c: 6f9b ldr r3, [r3, #120] @ 0x78 800bc7e: 2b05 cmp r3, #5 800bc80: d824 bhi.n 800bccc 800bc82: a201 add r2, pc, #4 @ (adr r2, 800bc88 ) 800bc84: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800bc88: 0800bcd5 .word 0x0800bcd5 800bc8c: 0800bca1 .word 0x0800bca1 800bc90: 0800bcb7 .word 0x0800bcb7 800bc94: 0800bcd5 .word 0x0800bcd5 800bc98: 0800bcd5 .word 0x0800bcd5 800bc9c: 0800bcd5 .word 0x0800bcd5 case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800bca0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bca4: 3308 adds r3, #8 800bca6: 2101 movs r1, #1 800bca8: 4618 mov r0, r3 800bcaa: f001 fe27 bl 800d8fc 800bcae: 4603 mov r3, r0 800bcb0: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 800bcb4: e00f b.n 800bcd6 case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800bcb6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bcba: 3328 adds r3, #40 @ 0x28 800bcbc: 2101 movs r1, #1 800bcbe: 4618 mov r0, r3 800bcc0: f001 fece bl 800da60 800bcc4: 4603 mov r3, r0 800bcc6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 800bcca: e004 b.n 800bcd6 /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800bccc: 2301 movs r3, #1 800bcce: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800bcd2: e000 b.n 800bcd6 break; 800bcd4: bf00 nop } if (ret == HAL_OK) 800bcd6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800bcda: 2b00 cmp r3, #0 800bcdc: d10a bne.n 800bcf4 { /* Set the source of USART2/3/4/5/7/8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 800bcde: 4b96 ldr r3, [pc, #600] @ (800bf38 ) 800bce0: 6d5b ldr r3, [r3, #84] @ 0x54 800bce2: f023 0107 bic.w r1, r3, #7 800bce6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bcea: 6f9b ldr r3, [r3, #120] @ 0x78 800bcec: 4a92 ldr r2, [pc, #584] @ (800bf38 ) 800bcee: 430b orrs r3, r1 800bcf0: 6553 str r3, [r2, #84] @ 0x54 800bcf2: e003 b.n 800bcfc } else { /* set overall return value */ status = ret; 800bcf4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800bcf8: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- LPUART1 Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 800bcfc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bd00: e9d3 2300 ldrd r2, r3, [r3] 800bd04: f002 0304 and.w r3, r2, #4 800bd08: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 800bd0c: 2300 movs r3, #0 800bd0e: f8c7 30ac str.w r3, [r7, #172] @ 0xac 800bd12: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 800bd16: 460b mov r3, r1 800bd18: 4313 orrs r3, r2 800bd1a: d044 beq.n 800bda6 { switch (PeriphClkInit->Lpuart1ClockSelection) 800bd1c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bd20: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800bd24: 2b05 cmp r3, #5 800bd26: d825 bhi.n 800bd74 800bd28: a201 add r2, pc, #4 @ (adr r2, 800bd30 ) 800bd2a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800bd2e: bf00 nop 800bd30: 0800bd7d .word 0x0800bd7d 800bd34: 0800bd49 .word 0x0800bd49 800bd38: 0800bd5f .word 0x0800bd5f 800bd3c: 0800bd7d .word 0x0800bd7d 800bd40: 0800bd7d .word 0x0800bd7d 800bd44: 0800bd7d .word 0x0800bd7d case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800bd48: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bd4c: 3308 adds r3, #8 800bd4e: 2101 movs r1, #1 800bd50: 4618 mov r0, r3 800bd52: f001 fdd3 bl 800d8fc 800bd56: 4603 mov r3, r0 800bd58: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 800bd5c: e00f b.n 800bd7e case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800bd5e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bd62: 3328 adds r3, #40 @ 0x28 800bd64: 2101 movs r1, #1 800bd66: 4618 mov r0, r3 800bd68: f001 fe7a bl 800da60 800bd6c: 4603 mov r3, r0 800bd6e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 800bd72: e004 b.n 800bd7e /* LSE, oscillator is used as source of LPUART1 clock */ /* LPUART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800bd74: 2301 movs r3, #1 800bd76: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800bd7a: e000 b.n 800bd7e break; 800bd7c: bf00 nop } if (ret == HAL_OK) 800bd7e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800bd82: 2b00 cmp r3, #0 800bd84: d10b bne.n 800bd9e { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 800bd86: 4b6c ldr r3, [pc, #432] @ (800bf38 ) 800bd88: 6d9b ldr r3, [r3, #88] @ 0x58 800bd8a: f023 0107 bic.w r1, r3, #7 800bd8e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bd92: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800bd96: 4a68 ldr r2, [pc, #416] @ (800bf38 ) 800bd98: 430b orrs r3, r1 800bd9a: 6593 str r3, [r2, #88] @ 0x58 800bd9c: e003 b.n 800bda6 } else { /* set overall return value */ status = ret; 800bd9e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800bda2: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 800bda6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bdaa: e9d3 2300 ldrd r2, r3, [r3] 800bdae: f002 0320 and.w r3, r2, #32 800bdb2: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 800bdb6: 2300 movs r3, #0 800bdb8: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 800bdbc: e9d7 1228 ldrd r1, r2, [r7, #160] @ 0xa0 800bdc0: 460b mov r3, r1 800bdc2: 4313 orrs r3, r2 800bdc4: d055 beq.n 800be72 { switch (PeriphClkInit->Lptim1ClockSelection) 800bdc6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bdca: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800bdce: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800bdd2: d033 beq.n 800be3c 800bdd4: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800bdd8: d82c bhi.n 800be34 800bdda: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800bdde: d02f beq.n 800be40 800bde0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800bde4: d826 bhi.n 800be34 800bde6: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800bdea: d02b beq.n 800be44 800bdec: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800bdf0: d820 bhi.n 800be34 800bdf2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800bdf6: d012 beq.n 800be1e 800bdf8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800bdfc: d81a bhi.n 800be34 800bdfe: 2b00 cmp r3, #0 800be00: d022 beq.n 800be48 800be02: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800be06: d115 bne.n 800be34 /* LPTIM1 clock source configuration done later after clock selection check */ break; case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800be08: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800be0c: 3308 adds r3, #8 800be0e: 2100 movs r1, #0 800be10: 4618 mov r0, r3 800be12: f001 fd73 bl 800d8fc 800be16: 4603 mov r3, r0 800be18: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 800be1c: e015 b.n 800be4a case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800be1e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800be22: 3328 adds r3, #40 @ 0x28 800be24: 2102 movs r1, #2 800be26: 4618 mov r0, r3 800be28: f001 fe1a bl 800da60 800be2c: 4603 mov r3, r0 800be2e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 800be32: e00a b.n 800be4a /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ /* LPTIM1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800be34: 2301 movs r3, #1 800be36: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800be3a: e006 b.n 800be4a break; 800be3c: bf00 nop 800be3e: e004 b.n 800be4a break; 800be40: bf00 nop 800be42: e002 b.n 800be4a break; 800be44: bf00 nop 800be46: e000 b.n 800be4a break; 800be48: bf00 nop } if (ret == HAL_OK) 800be4a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800be4e: 2b00 cmp r3, #0 800be50: d10b bne.n 800be6a { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 800be52: 4b39 ldr r3, [pc, #228] @ (800bf38 ) 800be54: 6d5b ldr r3, [r3, #84] @ 0x54 800be56: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 800be5a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800be5e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800be62: 4a35 ldr r2, [pc, #212] @ (800bf38 ) 800be64: 430b orrs r3, r1 800be66: 6553 str r3, [r2, #84] @ 0x54 800be68: e003 b.n 800be72 } else { /* set overall return value */ status = ret; 800be6a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800be6e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 800be72: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800be76: e9d3 2300 ldrd r2, r3, [r3] 800be7a: f002 0340 and.w r3, r2, #64 @ 0x40 800be7e: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800be82: 2300 movs r3, #0 800be84: f8c7 309c str.w r3, [r7, #156] @ 0x9c 800be88: e9d7 1226 ldrd r1, r2, [r7, #152] @ 0x98 800be8c: 460b mov r3, r1 800be8e: 4313 orrs r3, r2 800be90: d058 beq.n 800bf44 { switch (PeriphClkInit->Lptim2ClockSelection) 800be92: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800be96: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800be9a: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800be9e: d033 beq.n 800bf08 800bea0: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800bea4: d82c bhi.n 800bf00 800bea6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800beaa: d02f beq.n 800bf0c 800beac: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800beb0: d826 bhi.n 800bf00 800beb2: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 800beb6: d02b beq.n 800bf10 800beb8: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 800bebc: d820 bhi.n 800bf00 800bebe: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800bec2: d012 beq.n 800beea 800bec4: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800bec8: d81a bhi.n 800bf00 800beca: 2b00 cmp r3, #0 800becc: d022 beq.n 800bf14 800bece: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800bed2: d115 bne.n 800bf00 /* LPTIM2 clock source configuration done later after clock selection check */ break; case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800bed4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bed8: 3308 adds r3, #8 800beda: 2100 movs r1, #0 800bedc: 4618 mov r0, r3 800bede: f001 fd0d bl 800d8fc 800bee2: 4603 mov r3, r0 800bee4: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 800bee8: e015 b.n 800bf16 case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800beea: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800beee: 3328 adds r3, #40 @ 0x28 800bef0: 2102 movs r1, #2 800bef2: 4618 mov r0, r3 800bef4: f001 fdb4 bl 800da60 800bef8: 4603 mov r3, r0 800befa: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 800befe: e00a b.n 800bf16 /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ /* LPTIM2 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800bf00: 2301 movs r3, #1 800bf02: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800bf06: e006 b.n 800bf16 break; 800bf08: bf00 nop 800bf0a: e004 b.n 800bf16 break; 800bf0c: bf00 nop 800bf0e: e002 b.n 800bf16 break; 800bf10: bf00 nop 800bf12: e000 b.n 800bf16 break; 800bf14: bf00 nop } if (ret == HAL_OK) 800bf16: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800bf1a: 2b00 cmp r3, #0 800bf1c: d10e bne.n 800bf3c { /* Set the source of LPTIM2 clock*/ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 800bf1e: 4b06 ldr r3, [pc, #24] @ (800bf38 ) 800bf20: 6d9b ldr r3, [r3, #88] @ 0x58 800bf22: f423 51e0 bic.w r1, r3, #7168 @ 0x1c00 800bf26: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bf2a: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800bf2e: 4a02 ldr r2, [pc, #8] @ (800bf38 ) 800bf30: 430b orrs r3, r1 800bf32: 6593 str r3, [r2, #88] @ 0x58 800bf34: e006 b.n 800bf44 800bf36: bf00 nop 800bf38: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800bf3c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800bf40: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM345 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 800bf44: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bf48: e9d3 2300 ldrd r2, r3, [r3] 800bf4c: f002 0380 and.w r3, r2, #128 @ 0x80 800bf50: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800bf54: 2300 movs r3, #0 800bf56: f8c7 3094 str.w r3, [r7, #148] @ 0x94 800bf5a: e9d7 1224 ldrd r1, r2, [r7, #144] @ 0x90 800bf5e: 460b mov r3, r1 800bf60: 4313 orrs r3, r2 800bf62: d055 beq.n 800c010 { switch (PeriphClkInit->Lptim345ClockSelection) 800bf64: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bf68: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800bf6c: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 800bf70: d033 beq.n 800bfda 800bf72: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 800bf76: d82c bhi.n 800bfd2 800bf78: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800bf7c: d02f beq.n 800bfde 800bf7e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800bf82: d826 bhi.n 800bfd2 800bf84: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800bf88: d02b beq.n 800bfe2 800bf8a: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800bf8e: d820 bhi.n 800bfd2 800bf90: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800bf94: d012 beq.n 800bfbc 800bf96: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800bf9a: d81a bhi.n 800bfd2 800bf9c: 2b00 cmp r3, #0 800bf9e: d022 beq.n 800bfe6 800bfa0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800bfa4: d115 bne.n 800bfd2 case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800bfa6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bfaa: 3308 adds r3, #8 800bfac: 2100 movs r1, #0 800bfae: 4618 mov r0, r3 800bfb0: f001 fca4 bl 800d8fc 800bfb4: 4603 mov r3, r0 800bfb6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800bfba: e015 b.n 800bfe8 case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800bfbc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bfc0: 3328 adds r3, #40 @ 0x28 800bfc2: 2102 movs r1, #2 800bfc4: 4618 mov r0, r3 800bfc6: f001 fd4b bl 800da60 800bfca: 4603 mov r3, r0 800bfcc: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800bfd0: e00a b.n 800bfe8 /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800bfd2: 2301 movs r3, #1 800bfd4: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800bfd8: e006 b.n 800bfe8 break; 800bfda: bf00 nop 800bfdc: e004 b.n 800bfe8 break; 800bfde: bf00 nop 800bfe0: e002 b.n 800bfe8 break; 800bfe2: bf00 nop 800bfe4: e000 b.n 800bfe8 break; 800bfe6: bf00 nop } if (ret == HAL_OK) 800bfe8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800bfec: 2b00 cmp r3, #0 800bfee: d10b bne.n 800c008 { /* Set the source of LPTIM3/4/5 clock */ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 800bff0: 4bbb ldr r3, [pc, #748] @ (800c2e0 ) 800bff2: 6d9b ldr r3, [r3, #88] @ 0x58 800bff4: f423 4160 bic.w r1, r3, #57344 @ 0xe000 800bff8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bffc: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800c000: 4ab7 ldr r2, [pc, #732] @ (800c2e0 ) 800c002: 430b orrs r3, r1 800c004: 6593 str r3, [r2, #88] @ 0x58 800c006: e003 b.n 800c010 } else { /* set overall return value */ status = ret; 800c008: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c00c: f887 311e strb.w r3, [r7, #286] @ 0x11e __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); } #else if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 800c010: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c014: e9d3 2300 ldrd r2, r3, [r3] 800c018: f002 0308 and.w r3, r2, #8 800c01c: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800c020: 2300 movs r3, #0 800c022: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800c026: e9d7 1222 ldrd r1, r2, [r7, #136] @ 0x88 800c02a: 460b mov r3, r1 800c02c: 4313 orrs r3, r2 800c02e: d01e beq.n 800c06e { /* Check the parameters */ assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3) 800c030: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c034: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800c038: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800c03c: d10c bne.n 800c058 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800c03e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c042: 3328 adds r3, #40 @ 0x28 800c044: 2102 movs r1, #2 800c046: 4618 mov r0, r3 800c048: f001 fd0a bl 800da60 800c04c: 4603 mov r3, r0 800c04e: 2b00 cmp r3, #0 800c050: d002 beq.n 800c058 { status = HAL_ERROR; 800c052: 2301 movs r3, #1 800c054: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 800c058: 4ba1 ldr r3, [pc, #644] @ (800c2e0 ) 800c05a: 6d5b ldr r3, [r3, #84] @ 0x54 800c05c: f423 5140 bic.w r1, r3, #12288 @ 0x3000 800c060: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c064: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800c068: 4a9d ldr r2, [pc, #628] @ (800c2e0 ) 800c06a: 430b orrs r3, r1 800c06c: 6553 str r3, [r2, #84] @ 0x54 } #endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 800c06e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c072: e9d3 2300 ldrd r2, r3, [r3] 800c076: f002 0310 and.w r3, r2, #16 800c07a: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800c07e: 2300 movs r3, #0 800c080: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800c084: e9d7 1220 ldrd r1, r2, [r7, #128] @ 0x80 800c088: 460b mov r3, r1 800c08a: 4313 orrs r3, r2 800c08c: d01e beq.n 800c0cc { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) 800c08e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c092: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800c096: f5b3 7f80 cmp.w r3, #256 @ 0x100 800c09a: d10c bne.n 800c0b6 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800c09c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c0a0: 3328 adds r3, #40 @ 0x28 800c0a2: 2102 movs r1, #2 800c0a4: 4618 mov r0, r3 800c0a6: f001 fcdb bl 800da60 800c0aa: 4603 mov r3, r0 800c0ac: 2b00 cmp r3, #0 800c0ae: d002 beq.n 800c0b6 { status = HAL_ERROR; 800c0b0: 2301 movs r3, #1 800c0b2: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 800c0b6: 4b8a ldr r3, [pc, #552] @ (800c2e0 ) 800c0b8: 6d9b ldr r3, [r3, #88] @ 0x58 800c0ba: f423 7140 bic.w r1, r3, #768 @ 0x300 800c0be: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c0c2: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800c0c6: 4a86 ldr r2, [pc, #536] @ (800c2e0 ) 800c0c8: 430b orrs r3, r1 800c0ca: 6593 str r3, [r2, #88] @ 0x58 } /*---------------------------- ADC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 800c0cc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c0d0: e9d3 2300 ldrd r2, r3, [r3] 800c0d4: f402 2300 and.w r3, r2, #524288 @ 0x80000 800c0d8: 67bb str r3, [r7, #120] @ 0x78 800c0da: 2300 movs r3, #0 800c0dc: 67fb str r3, [r7, #124] @ 0x7c 800c0de: e9d7 121e ldrd r1, r2, [r7, #120] @ 0x78 800c0e2: 460b mov r3, r1 800c0e4: 4313 orrs r3, r2 800c0e6: d03e beq.n 800c166 { switch (PeriphClkInit->AdcClockSelection) 800c0e8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c0ec: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 800c0f0: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800c0f4: d022 beq.n 800c13c 800c0f6: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800c0fa: d81b bhi.n 800c134 800c0fc: 2b00 cmp r3, #0 800c0fe: d003 beq.n 800c108 800c100: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800c104: d00b beq.n 800c11e 800c106: e015 b.n 800c134 { case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800c108: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c10c: 3308 adds r3, #8 800c10e: 2100 movs r1, #0 800c110: 4618 mov r0, r3 800c112: f001 fbf3 bl 800d8fc 800c116: 4603 mov r3, r0 800c118: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 800c11c: e00f b.n 800c13e case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800c11e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c122: 3328 adds r3, #40 @ 0x28 800c124: 2102 movs r1, #2 800c126: 4618 mov r0, r3 800c128: f001 fc9a bl 800da60 800c12c: 4603 mov r3, r0 800c12e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 800c132: e004 b.n 800c13e /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ /* ADC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800c134: 2301 movs r3, #1 800c136: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c13a: e000 b.n 800c13e break; 800c13c: bf00 nop } if (ret == HAL_OK) 800c13e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c142: 2b00 cmp r3, #0 800c144: d10b bne.n 800c15e { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 800c146: 4b66 ldr r3, [pc, #408] @ (800c2e0 ) 800c148: 6d9b ldr r3, [r3, #88] @ 0x58 800c14a: f423 3140 bic.w r1, r3, #196608 @ 0x30000 800c14e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c152: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 800c156: 4a62 ldr r2, [pc, #392] @ (800c2e0 ) 800c158: 430b orrs r3, r1 800c15a: 6593 str r3, [r2, #88] @ 0x58 800c15c: e003 b.n 800c166 } else { /* set overall return value */ status = ret; 800c15e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c162: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ USB Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 800c166: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c16a: e9d3 2300 ldrd r2, r3, [r3] 800c16e: f402 2380 and.w r3, r2, #262144 @ 0x40000 800c172: 673b str r3, [r7, #112] @ 0x70 800c174: 2300 movs r3, #0 800c176: 677b str r3, [r7, #116] @ 0x74 800c178: e9d7 121c ldrd r1, r2, [r7, #112] @ 0x70 800c17c: 460b mov r3, r1 800c17e: 4313 orrs r3, r2 800c180: d03b beq.n 800c1fa { switch (PeriphClkInit->UsbClockSelection) 800c182: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c186: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800c18a: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800c18e: d01f beq.n 800c1d0 800c190: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800c194: d818 bhi.n 800c1c8 800c196: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800c19a: d003 beq.n 800c1a4 800c19c: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800c1a0: d007 beq.n 800c1b2 800c1a2: e011 b.n 800c1c8 { case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ /* Enable USB Clock output generated form System USB . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c1a4: 4b4e ldr r3, [pc, #312] @ (800c2e0 ) 800c1a6: 6adb ldr r3, [r3, #44] @ 0x2c 800c1a8: 4a4d ldr r2, [pc, #308] @ (800c2e0 ) 800c1aa: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c1ae: 62d3 str r3, [r2, #44] @ 0x2c /* USB clock source configuration done later after clock selection check */ break; 800c1b0: e00f b.n 800c1d2 case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800c1b2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c1b6: 3328 adds r3, #40 @ 0x28 800c1b8: 2101 movs r1, #1 800c1ba: 4618 mov r0, r3 800c1bc: f001 fc50 bl 800da60 800c1c0: 4603 mov r3, r0 800c1c2: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USB clock source configuration done later after clock selection check */ break; 800c1c6: e004 b.n 800c1d2 /* HSI48 oscillator is used as source of USB clock */ /* USB clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800c1c8: 2301 movs r3, #1 800c1ca: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c1ce: e000 b.n 800c1d2 break; 800c1d0: bf00 nop } if (ret == HAL_OK) 800c1d2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c1d6: 2b00 cmp r3, #0 800c1d8: d10b bne.n 800c1f2 { /* Set the source of USB clock*/ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 800c1da: 4b41 ldr r3, [pc, #260] @ (800c2e0 ) 800c1dc: 6d5b ldr r3, [r3, #84] @ 0x54 800c1de: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800c1e2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c1e6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800c1ea: 4a3d ldr r2, [pc, #244] @ (800c2e0 ) 800c1ec: 430b orrs r3, r1 800c1ee: 6553 str r3, [r2, #84] @ 0x54 800c1f0: e003 b.n 800c1fa } else { /* set overall return value */ status = ret; 800c1f2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c1f6: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------------- SDMMC Configuration ------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 800c1fa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c1fe: e9d3 2300 ldrd r2, r3, [r3] 800c202: f402 3380 and.w r3, r2, #65536 @ 0x10000 800c206: 66bb str r3, [r7, #104] @ 0x68 800c208: 2300 movs r3, #0 800c20a: 66fb str r3, [r7, #108] @ 0x6c 800c20c: e9d7 121a ldrd r1, r2, [r7, #104] @ 0x68 800c210: 460b mov r3, r1 800c212: 4313 orrs r3, r2 800c214: d031 beq.n 800c27a { /* Check the parameters */ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); switch (PeriphClkInit->SdmmcClockSelection) 800c216: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c21a: 6d1b ldr r3, [r3, #80] @ 0x50 800c21c: 2b00 cmp r3, #0 800c21e: d003 beq.n 800c228 800c220: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800c224: d007 beq.n 800c236 800c226: e011 b.n 800c24c { case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ /* Enable SDMMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c228: 4b2d ldr r3, [pc, #180] @ (800c2e0 ) 800c22a: 6adb ldr r3, [r3, #44] @ 0x2c 800c22c: 4a2c ldr r2, [pc, #176] @ (800c2e0 ) 800c22e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c232: 62d3 str r3, [r2, #44] @ 0x2c /* SDMMC clock source configuration done later after clock selection check */ break; 800c234: e00e b.n 800c254 case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800c236: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c23a: 3308 adds r3, #8 800c23c: 2102 movs r1, #2 800c23e: 4618 mov r0, r3 800c240: f001 fb5c bl 800d8fc 800c244: 4603 mov r3, r0 800c246: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SDMMC clock source configuration done later after clock selection check */ break; 800c24a: e003 b.n 800c254 default: ret = HAL_ERROR; 800c24c: 2301 movs r3, #1 800c24e: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c252: bf00 nop } if (ret == HAL_OK) 800c254: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c258: 2b00 cmp r3, #0 800c25a: d10a bne.n 800c272 { /* Set the source of SDMMC clock*/ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 800c25c: 4b20 ldr r3, [pc, #128] @ (800c2e0 ) 800c25e: 6cdb ldr r3, [r3, #76] @ 0x4c 800c260: f423 3180 bic.w r1, r3, #65536 @ 0x10000 800c264: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c268: 6d1b ldr r3, [r3, #80] @ 0x50 800c26a: 4a1d ldr r2, [pc, #116] @ (800c2e0 ) 800c26c: 430b orrs r3, r1 800c26e: 64d3 str r3, [r2, #76] @ 0x4c 800c270: e003 b.n 800c27a } else { /* set overall return value */ status = ret; 800c272: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c276: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /* LTDC */ /*------------------------------ RNG Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 800c27a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c27e: e9d3 2300 ldrd r2, r3, [r3] 800c282: f402 3300 and.w r3, r2, #131072 @ 0x20000 800c286: 663b str r3, [r7, #96] @ 0x60 800c288: 2300 movs r3, #0 800c28a: 667b str r3, [r7, #100] @ 0x64 800c28c: e9d7 1218 ldrd r1, r2, [r7, #96] @ 0x60 800c290: 460b mov r3, r1 800c292: 4313 orrs r3, r2 800c294: d03b beq.n 800c30e { switch (PeriphClkInit->RngClockSelection) 800c296: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c29a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800c29e: f5b3 7f40 cmp.w r3, #768 @ 0x300 800c2a2: d018 beq.n 800c2d6 800c2a4: f5b3 7f40 cmp.w r3, #768 @ 0x300 800c2a8: d811 bhi.n 800c2ce 800c2aa: f5b3 7f00 cmp.w r3, #512 @ 0x200 800c2ae: d014 beq.n 800c2da 800c2b0: f5b3 7f00 cmp.w r3, #512 @ 0x200 800c2b4: d80b bhi.n 800c2ce 800c2b6: 2b00 cmp r3, #0 800c2b8: d014 beq.n 800c2e4 800c2ba: f5b3 7f80 cmp.w r3, #256 @ 0x100 800c2be: d106 bne.n 800c2ce { case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ /* Enable RNG Clock output generated form System RNG . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c2c0: 4b07 ldr r3, [pc, #28] @ (800c2e0 ) 800c2c2: 6adb ldr r3, [r3, #44] @ 0x2c 800c2c4: 4a06 ldr r2, [pc, #24] @ (800c2e0 ) 800c2c6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c2ca: 62d3 str r3, [r2, #44] @ 0x2c /* RNG clock source configuration done later after clock selection check */ break; 800c2cc: e00b b.n 800c2e6 /* HSI48 oscillator is used as source of RNG clock */ /* RNG clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800c2ce: 2301 movs r3, #1 800c2d0: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c2d4: e007 b.n 800c2e6 break; 800c2d6: bf00 nop 800c2d8: e005 b.n 800c2e6 break; 800c2da: bf00 nop 800c2dc: e003 b.n 800c2e6 800c2de: bf00 nop 800c2e0: 58024400 .word 0x58024400 break; 800c2e4: bf00 nop } if (ret == HAL_OK) 800c2e6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c2ea: 2b00 cmp r3, #0 800c2ec: d10b bne.n 800c306 { /* Set the source of RNG clock*/ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 800c2ee: 4bba ldr r3, [pc, #744] @ (800c5d8 ) 800c2f0: 6d5b ldr r3, [r3, #84] @ 0x54 800c2f2: f423 7140 bic.w r1, r3, #768 @ 0x300 800c2f6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c2fa: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800c2fe: 4ab6 ldr r2, [pc, #728] @ (800c5d8 ) 800c300: 430b orrs r3, r1 800c302: 6553 str r3, [r2, #84] @ 0x54 800c304: e003 b.n 800c30e } else { /* set overall return value */ status = ret; 800c306: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c30a: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ SWPMI1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 800c30e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c312: e9d3 2300 ldrd r2, r3, [r3] 800c316: f402 1380 and.w r3, r2, #1048576 @ 0x100000 800c31a: 65bb str r3, [r7, #88] @ 0x58 800c31c: 2300 movs r3, #0 800c31e: 65fb str r3, [r7, #92] @ 0x5c 800c320: e9d7 1216 ldrd r1, r2, [r7, #88] @ 0x58 800c324: 460b mov r3, r1 800c326: 4313 orrs r3, r2 800c328: d009 beq.n 800c33e { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 800c32a: 4bab ldr r3, [pc, #684] @ (800c5d8 ) 800c32c: 6d1b ldr r3, [r3, #80] @ 0x50 800c32e: f023 4100 bic.w r1, r3, #2147483648 @ 0x80000000 800c332: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c336: 6f5b ldr r3, [r3, #116] @ 0x74 800c338: 4aa7 ldr r2, [pc, #668] @ (800c5d8 ) 800c33a: 430b orrs r3, r1 800c33c: 6513 str r3, [r2, #80] @ 0x50 } #if defined(HRTIM1) /*------------------------------ HRTIM1 clock Configuration ----------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) 800c33e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c342: e9d3 2300 ldrd r2, r3, [r3] 800c346: f002 5380 and.w r3, r2, #268435456 @ 0x10000000 800c34a: 653b str r3, [r7, #80] @ 0x50 800c34c: 2300 movs r3, #0 800c34e: 657b str r3, [r7, #84] @ 0x54 800c350: e9d7 1214 ldrd r1, r2, [r7, #80] @ 0x50 800c354: 460b mov r3, r1 800c356: 4313 orrs r3, r2 800c358: d00a beq.n 800c370 { /* Check the parameters */ assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); 800c35a: 4b9f ldr r3, [pc, #636] @ (800c5d8 ) 800c35c: 691b ldr r3, [r3, #16] 800c35e: f423 4180 bic.w r1, r3, #16384 @ 0x4000 800c362: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c366: f8d3 30b8 ldr.w r3, [r3, #184] @ 0xb8 800c36a: 4a9b ldr r2, [pc, #620] @ (800c5d8 ) 800c36c: 430b orrs r3, r1 800c36e: 6113 str r3, [r2, #16] } #endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 800c370: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c374: e9d3 2300 ldrd r2, r3, [r3] 800c378: f402 1300 and.w r3, r2, #2097152 @ 0x200000 800c37c: 64bb str r3, [r7, #72] @ 0x48 800c37e: 2300 movs r3, #0 800c380: 64fb str r3, [r7, #76] @ 0x4c 800c382: e9d7 1212 ldrd r1, r2, [r7, #72] @ 0x48 800c386: 460b mov r3, r1 800c388: 4313 orrs r3, r2 800c38a: d009 beq.n 800c3a0 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 800c38c: 4b92 ldr r3, [pc, #584] @ (800c5d8 ) 800c38e: 6d1b ldr r3, [r3, #80] @ 0x50 800c390: f023 7180 bic.w r1, r3, #16777216 @ 0x1000000 800c394: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c398: 6edb ldr r3, [r3, #108] @ 0x6c 800c39a: 4a8f ldr r2, [pc, #572] @ (800c5d8 ) 800c39c: 430b orrs r3, r1 800c39e: 6513 str r3, [r2, #80] @ 0x50 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); } #endif /* DFSDM2 */ /*------------------------------------ TIM configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 800c3a0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c3a4: e9d3 2300 ldrd r2, r3, [r3] 800c3a8: f002 4380 and.w r3, r2, #1073741824 @ 0x40000000 800c3ac: 643b str r3, [r7, #64] @ 0x40 800c3ae: 2300 movs r3, #0 800c3b0: 647b str r3, [r7, #68] @ 0x44 800c3b2: e9d7 1210 ldrd r1, r2, [r7, #64] @ 0x40 800c3b6: 460b mov r3, r1 800c3b8: 4313 orrs r3, r2 800c3ba: d00e beq.n 800c3da { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 800c3bc: 4b86 ldr r3, [pc, #536] @ (800c5d8 ) 800c3be: 691b ldr r3, [r3, #16] 800c3c0: 4a85 ldr r2, [pc, #532] @ (800c5d8 ) 800c3c2: f423 4300 bic.w r3, r3, #32768 @ 0x8000 800c3c6: 6113 str r3, [r2, #16] 800c3c8: 4b83 ldr r3, [pc, #524] @ (800c5d8 ) 800c3ca: 6919 ldr r1, [r3, #16] 800c3cc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c3d0: f8d3 30bc ldr.w r3, [r3, #188] @ 0xbc 800c3d4: 4a80 ldr r2, [pc, #512] @ (800c5d8 ) 800c3d6: 430b orrs r3, r1 800c3d8: 6113 str r3, [r2, #16] } /*------------------------------------ CKPER configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 800c3da: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c3de: e9d3 2300 ldrd r2, r3, [r3] 800c3e2: f002 4300 and.w r3, r2, #2147483648 @ 0x80000000 800c3e6: 63bb str r3, [r7, #56] @ 0x38 800c3e8: 2300 movs r3, #0 800c3ea: 63fb str r3, [r7, #60] @ 0x3c 800c3ec: e9d7 120e ldrd r1, r2, [r7, #56] @ 0x38 800c3f0: 460b mov r3, r1 800c3f2: 4313 orrs r3, r2 800c3f4: d009 beq.n 800c40a { /* Check the parameters */ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); /* Configure the CKPER clock source */ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 800c3f6: 4b78 ldr r3, [pc, #480] @ (800c5d8 ) 800c3f8: 6cdb ldr r3, [r3, #76] @ 0x4c 800c3fa: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 800c3fe: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c402: 6d5b ldr r3, [r3, #84] @ 0x54 800c404: 4a74 ldr r2, [pc, #464] @ (800c5d8 ) 800c406: 430b orrs r3, r1 800c408: 64d3 str r3, [r2, #76] @ 0x4c } /*------------------------------ CEC Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 800c40a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c40e: e9d3 2300 ldrd r2, r3, [r3] 800c412: f402 0300 and.w r3, r2, #8388608 @ 0x800000 800c416: 633b str r3, [r7, #48] @ 0x30 800c418: 2300 movs r3, #0 800c41a: 637b str r3, [r7, #52] @ 0x34 800c41c: e9d7 120c ldrd r1, r2, [r7, #48] @ 0x30 800c420: 460b mov r3, r1 800c422: 4313 orrs r3, r2 800c424: d00a beq.n 800c43c { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC interface clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 800c426: 4b6c ldr r3, [pc, #432] @ (800c5d8 ) 800c428: 6d5b ldr r3, [r3, #84] @ 0x54 800c42a: f423 0140 bic.w r1, r3, #12582912 @ 0xc00000 800c42e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c432: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800c436: 4a68 ldr r2, [pc, #416] @ (800c5d8 ) 800c438: 430b orrs r3, r1 800c43a: 6553 str r3, [r2, #84] @ 0x54 } /*---------------------------- PLL2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) 800c43c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c440: e9d3 2300 ldrd r2, r3, [r3] 800c444: 2100 movs r1, #0 800c446: 62b9 str r1, [r7, #40] @ 0x28 800c448: f003 0301 and.w r3, r3, #1 800c44c: 62fb str r3, [r7, #44] @ 0x2c 800c44e: e9d7 120a ldrd r1, r2, [r7, #40] @ 0x28 800c452: 460b mov r3, r1 800c454: 4313 orrs r3, r2 800c456: d011 beq.n 800c47c { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800c458: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c45c: 3308 adds r3, #8 800c45e: 2100 movs r1, #0 800c460: 4618 mov r0, r3 800c462: f001 fa4b bl 800d8fc 800c466: 4603 mov r3, r0 800c468: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800c46c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c470: 2b00 cmp r3, #0 800c472: d003 beq.n 800c47c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800c474: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c478: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) 800c47c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c480: e9d3 2300 ldrd r2, r3, [r3] 800c484: 2100 movs r1, #0 800c486: 6239 str r1, [r7, #32] 800c488: f003 0302 and.w r3, r3, #2 800c48c: 627b str r3, [r7, #36] @ 0x24 800c48e: e9d7 1208 ldrd r1, r2, [r7, #32] 800c492: 460b mov r3, r1 800c494: 4313 orrs r3, r2 800c496: d011 beq.n 800c4bc { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800c498: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c49c: 3308 adds r3, #8 800c49e: 2101 movs r1, #1 800c4a0: 4618 mov r0, r3 800c4a2: f001 fa2b bl 800d8fc 800c4a6: 4603 mov r3, r0 800c4a8: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800c4ac: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c4b0: 2b00 cmp r3, #0 800c4b2: d003 beq.n 800c4bc /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800c4b4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c4b8: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) 800c4bc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c4c0: e9d3 2300 ldrd r2, r3, [r3] 800c4c4: 2100 movs r1, #0 800c4c6: 61b9 str r1, [r7, #24] 800c4c8: f003 0304 and.w r3, r3, #4 800c4cc: 61fb str r3, [r7, #28] 800c4ce: e9d7 1206 ldrd r1, r2, [r7, #24] 800c4d2: 460b mov r3, r1 800c4d4: 4313 orrs r3, r2 800c4d6: d011 beq.n 800c4fc { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800c4d8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c4dc: 3308 adds r3, #8 800c4de: 2102 movs r1, #2 800c4e0: 4618 mov r0, r3 800c4e2: f001 fa0b bl 800d8fc 800c4e6: 4603 mov r3, r0 800c4e8: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800c4ec: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c4f0: 2b00 cmp r3, #0 800c4f2: d003 beq.n 800c4fc /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800c4f4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c4f8: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- PLL3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) 800c4fc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c500: e9d3 2300 ldrd r2, r3, [r3] 800c504: 2100 movs r1, #0 800c506: 6139 str r1, [r7, #16] 800c508: f003 0308 and.w r3, r3, #8 800c50c: 617b str r3, [r7, #20] 800c50e: e9d7 1204 ldrd r1, r2, [r7, #16] 800c512: 460b mov r3, r1 800c514: 4313 orrs r3, r2 800c516: d011 beq.n 800c53c { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800c518: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c51c: 3328 adds r3, #40 @ 0x28 800c51e: 2100 movs r1, #0 800c520: 4618 mov r0, r3 800c522: f001 fa9d bl 800da60 800c526: 4603 mov r3, r0 800c528: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800c52c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c530: 2b00 cmp r3, #0 800c532: d003 beq.n 800c53c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800c534: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c538: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) 800c53c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c540: e9d3 2300 ldrd r2, r3, [r3] 800c544: 2100 movs r1, #0 800c546: 60b9 str r1, [r7, #8] 800c548: f003 0310 and.w r3, r3, #16 800c54c: 60fb str r3, [r7, #12] 800c54e: e9d7 1202 ldrd r1, r2, [r7, #8] 800c552: 460b mov r3, r1 800c554: 4313 orrs r3, r2 800c556: d011 beq.n 800c57c { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800c558: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c55c: 3328 adds r3, #40 @ 0x28 800c55e: 2101 movs r1, #1 800c560: 4618 mov r0, r3 800c562: f001 fa7d bl 800da60 800c566: 4603 mov r3, r0 800c568: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800c56c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c570: 2b00 cmp r3, #0 800c572: d003 beq.n 800c57c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800c574: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c578: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) 800c57c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c580: e9d3 2300 ldrd r2, r3, [r3] 800c584: 2100 movs r1, #0 800c586: 6039 str r1, [r7, #0] 800c588: f003 0320 and.w r3, r3, #32 800c58c: 607b str r3, [r7, #4] 800c58e: e9d7 1200 ldrd r1, r2, [r7] 800c592: 460b mov r3, r1 800c594: 4313 orrs r3, r2 800c596: d011 beq.n 800c5bc { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800c598: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c59c: 3328 adds r3, #40 @ 0x28 800c59e: 2102 movs r1, #2 800c5a0: 4618 mov r0, r3 800c5a2: f001 fa5d bl 800da60 800c5a6: 4603 mov r3, r0 800c5a8: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800c5ac: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c5b0: 2b00 cmp r3, #0 800c5b2: d003 beq.n 800c5bc /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800c5b4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c5b8: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (status == HAL_OK) 800c5bc: f897 311e ldrb.w r3, [r7, #286] @ 0x11e 800c5c0: 2b00 cmp r3, #0 800c5c2: d101 bne.n 800c5c8 { return HAL_OK; 800c5c4: 2300 movs r3, #0 800c5c6: e000 b.n 800c5ca } return HAL_ERROR; 800c5c8: 2301 movs r3, #1 } 800c5ca: 4618 mov r0, r3 800c5cc: f507 7790 add.w r7, r7, #288 @ 0x120 800c5d0: 46bd mov sp, r7 800c5d2: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 800c5d6: bf00 nop 800c5d8: 58024400 .word 0x58024400 0800c5dc : * @retval Frequency in KHz * * (*) : Available on some STM32H7 lines only. */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) { 800c5dc: b580 push {r7, lr} 800c5de: b090 sub sp, #64 @ 0x40 800c5e0: af00 add r7, sp, #0 800c5e2: e9c7 0100 strd r0, r1, [r7] /* This variable is used to store the SAI and CKP clock source */ uint32_t saiclocksource; uint32_t ckpclocksource; uint32_t srcclk; if (PeriphClk == RCC_PERIPHCLK_SAI1) 800c5e6: e9d7 2300 ldrd r2, r3, [r7] 800c5ea: f5a2 7180 sub.w r1, r2, #256 @ 0x100 800c5ee: 430b orrs r3, r1 800c5f0: f040 8094 bne.w 800c71c { saiclocksource = __HAL_RCC_GET_SAI1_SOURCE(); 800c5f4: 4b9e ldr r3, [pc, #632] @ (800c870 ) 800c5f6: 6d1b ldr r3, [r3, #80] @ 0x50 800c5f8: f003 0307 and.w r3, r3, #7 800c5fc: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800c5fe: 6b3b ldr r3, [r7, #48] @ 0x30 800c600: 2b04 cmp r3, #4 800c602: f200 8087 bhi.w 800c714 800c606: a201 add r2, pc, #4 @ (adr r2, 800c60c ) 800c608: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c60c: 0800c621 .word 0x0800c621 800c610: 0800c649 .word 0x0800c649 800c614: 0800c671 .word 0x0800c671 800c618: 0800c70d .word 0x0800c70d 800c61c: 0800c699 .word 0x0800c699 { case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800c620: 4b93 ldr r3, [pc, #588] @ (800c870 ) 800c622: 681b ldr r3, [r3, #0] 800c624: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800c628: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800c62c: d108 bne.n 800c640 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800c62e: f107 0324 add.w r3, r7, #36 @ 0x24 800c632: 4618 mov r0, r3 800c634: f001 f810 bl 800d658 frequency = pll1_clocks.PLL1_Q_Frequency; 800c638: 6abb ldr r3, [r7, #40] @ 0x28 800c63a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800c63c: f000 bd45 b.w 800d0ca frequency = 0; 800c640: 2300 movs r3, #0 800c642: 63fb str r3, [r7, #60] @ 0x3c break; 800c644: f000 bd41 b.w 800d0ca } case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800c648: 4b89 ldr r3, [pc, #548] @ (800c870 ) 800c64a: 681b ldr r3, [r3, #0] 800c64c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800c650: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800c654: d108 bne.n 800c668 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800c656: f107 0318 add.w r3, r7, #24 800c65a: 4618 mov r0, r3 800c65c: f000 fd54 bl 800d108 frequency = pll2_clocks.PLL2_P_Frequency; 800c660: 69bb ldr r3, [r7, #24] 800c662: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800c664: f000 bd31 b.w 800d0ca frequency = 0; 800c668: 2300 movs r3, #0 800c66a: 63fb str r3, [r7, #60] @ 0x3c break; 800c66c: f000 bd2d b.w 800d0ca } case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800c670: 4b7f ldr r3, [pc, #508] @ (800c870 ) 800c672: 681b ldr r3, [r3, #0] 800c674: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800c678: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800c67c: d108 bne.n 800c690 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800c67e: f107 030c add.w r3, r7, #12 800c682: 4618 mov r0, r3 800c684: f000 fe94 bl 800d3b0 frequency = pll3_clocks.PLL3_P_Frequency; 800c688: 68fb ldr r3, [r7, #12] 800c68a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800c68c: f000 bd1d b.w 800d0ca frequency = 0; 800c690: 2300 movs r3, #0 800c692: 63fb str r3, [r7, #60] @ 0x3c break; 800c694: f000 bd19 b.w 800d0ca } case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800c698: 4b75 ldr r3, [pc, #468] @ (800c870 ) 800c69a: 6cdb ldr r3, [r3, #76] @ 0x4c 800c69c: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800c6a0: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800c6a2: 4b73 ldr r3, [pc, #460] @ (800c870 ) 800c6a4: 681b ldr r3, [r3, #0] 800c6a6: f003 0304 and.w r3, r3, #4 800c6aa: 2b04 cmp r3, #4 800c6ac: d10c bne.n 800c6c8 800c6ae: 6b7b ldr r3, [r7, #52] @ 0x34 800c6b0: 2b00 cmp r3, #0 800c6b2: d109 bne.n 800c6c8 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800c6b4: 4b6e ldr r3, [pc, #440] @ (800c870 ) 800c6b6: 681b ldr r3, [r3, #0] 800c6b8: 08db lsrs r3, r3, #3 800c6ba: f003 0303 and.w r3, r3, #3 800c6be: 4a6d ldr r2, [pc, #436] @ (800c874 ) 800c6c0: fa22 f303 lsr.w r3, r2, r3 800c6c4: 63fb str r3, [r7, #60] @ 0x3c 800c6c6: e01f b.n 800c708 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800c6c8: 4b69 ldr r3, [pc, #420] @ (800c870 ) 800c6ca: 681b ldr r3, [r3, #0] 800c6cc: f403 7380 and.w r3, r3, #256 @ 0x100 800c6d0: f5b3 7f80 cmp.w r3, #256 @ 0x100 800c6d4: d106 bne.n 800c6e4 800c6d6: 6b7b ldr r3, [r7, #52] @ 0x34 800c6d8: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800c6dc: d102 bne.n 800c6e4 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800c6de: 4b66 ldr r3, [pc, #408] @ (800c878 ) 800c6e0: 63fb str r3, [r7, #60] @ 0x3c 800c6e2: e011 b.n 800c708 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800c6e4: 4b62 ldr r3, [pc, #392] @ (800c870 ) 800c6e6: 681b ldr r3, [r3, #0] 800c6e8: f403 3300 and.w r3, r3, #131072 @ 0x20000 800c6ec: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800c6f0: d106 bne.n 800c700 800c6f2: 6b7b ldr r3, [r7, #52] @ 0x34 800c6f4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800c6f8: d102 bne.n 800c700 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800c6fa: 4b60 ldr r3, [pc, #384] @ (800c87c ) 800c6fc: 63fb str r3, [r7, #60] @ 0x3c 800c6fe: e003 b.n 800c708 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800c700: 2300 movs r3, #0 800c702: 63fb str r3, [r7, #60] @ 0x3c } break; 800c704: f000 bce1 b.w 800d0ca 800c708: f000 bcdf b.w 800d0ca } case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ { frequency = EXTERNAL_CLOCK_VALUE; 800c70c: 4b5c ldr r3, [pc, #368] @ (800c880 ) 800c70e: 63fb str r3, [r7, #60] @ 0x3c break; 800c710: f000 bcdb b.w 800d0ca } default : { frequency = 0; 800c714: 2300 movs r3, #0 800c716: 63fb str r3, [r7, #60] @ 0x3c break; 800c718: f000 bcd7 b.w 800d0ca } } } #if defined(SAI3) else if (PeriphClk == RCC_PERIPHCLK_SAI23) 800c71c: e9d7 2300 ldrd r2, r3, [r7] 800c720: f5a2 7100 sub.w r1, r2, #512 @ 0x200 800c724: 430b orrs r3, r1 800c726: f040 80ad bne.w 800c884 { saiclocksource = __HAL_RCC_GET_SAI23_SOURCE(); 800c72a: 4b51 ldr r3, [pc, #324] @ (800c870 ) 800c72c: 6d1b ldr r3, [r3, #80] @ 0x50 800c72e: f403 73e0 and.w r3, r3, #448 @ 0x1c0 800c732: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800c734: 6b3b ldr r3, [r7, #48] @ 0x30 800c736: f5b3 7f80 cmp.w r3, #256 @ 0x100 800c73a: d056 beq.n 800c7ea 800c73c: 6b3b ldr r3, [r7, #48] @ 0x30 800c73e: f5b3 7f80 cmp.w r3, #256 @ 0x100 800c742: f200 8090 bhi.w 800c866 800c746: 6b3b ldr r3, [r7, #48] @ 0x30 800c748: 2bc0 cmp r3, #192 @ 0xc0 800c74a: f000 8088 beq.w 800c85e 800c74e: 6b3b ldr r3, [r7, #48] @ 0x30 800c750: 2bc0 cmp r3, #192 @ 0xc0 800c752: f200 8088 bhi.w 800c866 800c756: 6b3b ldr r3, [r7, #48] @ 0x30 800c758: 2b80 cmp r3, #128 @ 0x80 800c75a: d032 beq.n 800c7c2 800c75c: 6b3b ldr r3, [r7, #48] @ 0x30 800c75e: 2b80 cmp r3, #128 @ 0x80 800c760: f200 8081 bhi.w 800c866 800c764: 6b3b ldr r3, [r7, #48] @ 0x30 800c766: 2b00 cmp r3, #0 800c768: d003 beq.n 800c772 800c76a: 6b3b ldr r3, [r7, #48] @ 0x30 800c76c: 2b40 cmp r3, #64 @ 0x40 800c76e: d014 beq.n 800c79a 800c770: e079 b.n 800c866 { case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800c772: 4b3f ldr r3, [pc, #252] @ (800c870 ) 800c774: 681b ldr r3, [r3, #0] 800c776: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800c77a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800c77e: d108 bne.n 800c792 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800c780: f107 0324 add.w r3, r7, #36 @ 0x24 800c784: 4618 mov r0, r3 800c786: f000 ff67 bl 800d658 frequency = pll1_clocks.PLL1_Q_Frequency; 800c78a: 6abb ldr r3, [r7, #40] @ 0x28 800c78c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800c78e: f000 bc9c b.w 800d0ca frequency = 0; 800c792: 2300 movs r3, #0 800c794: 63fb str r3, [r7, #60] @ 0x3c break; 800c796: f000 bc98 b.w 800d0ca } case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800c79a: 4b35 ldr r3, [pc, #212] @ (800c870 ) 800c79c: 681b ldr r3, [r3, #0] 800c79e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800c7a2: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800c7a6: d108 bne.n 800c7ba { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800c7a8: f107 0318 add.w r3, r7, #24 800c7ac: 4618 mov r0, r3 800c7ae: f000 fcab bl 800d108 frequency = pll2_clocks.PLL2_P_Frequency; 800c7b2: 69bb ldr r3, [r7, #24] 800c7b4: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800c7b6: f000 bc88 b.w 800d0ca frequency = 0; 800c7ba: 2300 movs r3, #0 800c7bc: 63fb str r3, [r7, #60] @ 0x3c break; 800c7be: f000 bc84 b.w 800d0ca } case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800c7c2: 4b2b ldr r3, [pc, #172] @ (800c870 ) 800c7c4: 681b ldr r3, [r3, #0] 800c7c6: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800c7ca: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800c7ce: d108 bne.n 800c7e2 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800c7d0: f107 030c add.w r3, r7, #12 800c7d4: 4618 mov r0, r3 800c7d6: f000 fdeb bl 800d3b0 frequency = pll3_clocks.PLL3_P_Frequency; 800c7da: 68fb ldr r3, [r7, #12] 800c7dc: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800c7de: f000 bc74 b.w 800d0ca frequency = 0; 800c7e2: 2300 movs r3, #0 800c7e4: 63fb str r3, [r7, #60] @ 0x3c break; 800c7e6: f000 bc70 b.w 800d0ca } case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800c7ea: 4b21 ldr r3, [pc, #132] @ (800c870 ) 800c7ec: 6cdb ldr r3, [r3, #76] @ 0x4c 800c7ee: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800c7f2: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800c7f4: 4b1e ldr r3, [pc, #120] @ (800c870 ) 800c7f6: 681b ldr r3, [r3, #0] 800c7f8: f003 0304 and.w r3, r3, #4 800c7fc: 2b04 cmp r3, #4 800c7fe: d10c bne.n 800c81a 800c800: 6b7b ldr r3, [r7, #52] @ 0x34 800c802: 2b00 cmp r3, #0 800c804: d109 bne.n 800c81a { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800c806: 4b1a ldr r3, [pc, #104] @ (800c870 ) 800c808: 681b ldr r3, [r3, #0] 800c80a: 08db lsrs r3, r3, #3 800c80c: f003 0303 and.w r3, r3, #3 800c810: 4a18 ldr r2, [pc, #96] @ (800c874 ) 800c812: fa22 f303 lsr.w r3, r2, r3 800c816: 63fb str r3, [r7, #60] @ 0x3c 800c818: e01f b.n 800c85a } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800c81a: 4b15 ldr r3, [pc, #84] @ (800c870 ) 800c81c: 681b ldr r3, [r3, #0] 800c81e: f403 7380 and.w r3, r3, #256 @ 0x100 800c822: f5b3 7f80 cmp.w r3, #256 @ 0x100 800c826: d106 bne.n 800c836 800c828: 6b7b ldr r3, [r7, #52] @ 0x34 800c82a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800c82e: d102 bne.n 800c836 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800c830: 4b11 ldr r3, [pc, #68] @ (800c878 ) 800c832: 63fb str r3, [r7, #60] @ 0x3c 800c834: e011 b.n 800c85a } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800c836: 4b0e ldr r3, [pc, #56] @ (800c870 ) 800c838: 681b ldr r3, [r3, #0] 800c83a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800c83e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800c842: d106 bne.n 800c852 800c844: 6b7b ldr r3, [r7, #52] @ 0x34 800c846: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800c84a: d102 bne.n 800c852 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800c84c: 4b0b ldr r3, [pc, #44] @ (800c87c ) 800c84e: 63fb str r3, [r7, #60] @ 0x3c 800c850: e003 b.n 800c85a } else { /* In Case the CKPER is disabled*/ frequency = 0; 800c852: 2300 movs r3, #0 800c854: 63fb str r3, [r7, #60] @ 0x3c } break; 800c856: f000 bc38 b.w 800d0ca 800c85a: f000 bc36 b.w 800d0ca } case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ { frequency = EXTERNAL_CLOCK_VALUE; 800c85e: 4b08 ldr r3, [pc, #32] @ (800c880 ) 800c860: 63fb str r3, [r7, #60] @ 0x3c break; 800c862: f000 bc32 b.w 800d0ca } default : { frequency = 0; 800c866: 2300 movs r3, #0 800c868: 63fb str r3, [r7, #60] @ 0x3c break; 800c86a: f000 bc2e b.w 800d0ca 800c86e: bf00 nop 800c870: 58024400 .word 0x58024400 800c874: 03d09000 .word 0x03d09000 800c878: 003d0900 .word 0x003d0900 800c87c: 017d7840 .word 0x017d7840 800c880: 00bb8000 .word 0x00bb8000 } } #endif #if defined(SAI4) else if (PeriphClk == RCC_PERIPHCLK_SAI4A) 800c884: e9d7 2300 ldrd r2, r3, [r7] 800c888: f5a2 6180 sub.w r1, r2, #1024 @ 0x400 800c88c: 430b orrs r3, r1 800c88e: f040 809c bne.w 800c9ca { saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE(); 800c892: 4b9e ldr r3, [pc, #632] @ (800cb0c ) 800c894: 6d9b ldr r3, [r3, #88] @ 0x58 800c896: f403 0360 and.w r3, r3, #14680064 @ 0xe00000 800c89a: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800c89c: 6b3b ldr r3, [r7, #48] @ 0x30 800c89e: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800c8a2: d054 beq.n 800c94e 800c8a4: 6b3b ldr r3, [r7, #48] @ 0x30 800c8a6: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800c8aa: f200 808b bhi.w 800c9c4 800c8ae: 6b3b ldr r3, [r7, #48] @ 0x30 800c8b0: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800c8b4: f000 8083 beq.w 800c9be 800c8b8: 6b3b ldr r3, [r7, #48] @ 0x30 800c8ba: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800c8be: f200 8081 bhi.w 800c9c4 800c8c2: 6b3b ldr r3, [r7, #48] @ 0x30 800c8c4: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800c8c8: d02f beq.n 800c92a 800c8ca: 6b3b ldr r3, [r7, #48] @ 0x30 800c8cc: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800c8d0: d878 bhi.n 800c9c4 800c8d2: 6b3b ldr r3, [r7, #48] @ 0x30 800c8d4: 2b00 cmp r3, #0 800c8d6: d004 beq.n 800c8e2 800c8d8: 6b3b ldr r3, [r7, #48] @ 0x30 800c8da: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800c8de: d012 beq.n 800c906 800c8e0: e070 b.n 800c9c4 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800c8e2: 4b8a ldr r3, [pc, #552] @ (800cb0c ) 800c8e4: 681b ldr r3, [r3, #0] 800c8e6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800c8ea: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800c8ee: d107 bne.n 800c900 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800c8f0: f107 0324 add.w r3, r7, #36 @ 0x24 800c8f4: 4618 mov r0, r3 800c8f6: f000 feaf bl 800d658 frequency = pll1_clocks.PLL1_Q_Frequency; 800c8fa: 6abb ldr r3, [r7, #40] @ 0x28 800c8fc: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800c8fe: e3e4 b.n 800d0ca frequency = 0; 800c900: 2300 movs r3, #0 800c902: 63fb str r3, [r7, #60] @ 0x3c break; 800c904: e3e1 b.n 800d0ca } case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800c906: 4b81 ldr r3, [pc, #516] @ (800cb0c ) 800c908: 681b ldr r3, [r3, #0] 800c90a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800c90e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800c912: d107 bne.n 800c924 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800c914: f107 0318 add.w r3, r7, #24 800c918: 4618 mov r0, r3 800c91a: f000 fbf5 bl 800d108 frequency = pll2_clocks.PLL2_P_Frequency; 800c91e: 69bb ldr r3, [r7, #24] 800c920: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800c922: e3d2 b.n 800d0ca frequency = 0; 800c924: 2300 movs r3, #0 800c926: 63fb str r3, [r7, #60] @ 0x3c break; 800c928: e3cf b.n 800d0ca } case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800c92a: 4b78 ldr r3, [pc, #480] @ (800cb0c ) 800c92c: 681b ldr r3, [r3, #0] 800c92e: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800c932: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800c936: d107 bne.n 800c948 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800c938: f107 030c add.w r3, r7, #12 800c93c: 4618 mov r0, r3 800c93e: f000 fd37 bl 800d3b0 frequency = pll3_clocks.PLL3_P_Frequency; 800c942: 68fb ldr r3, [r7, #12] 800c944: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800c946: e3c0 b.n 800d0ca frequency = 0; 800c948: 2300 movs r3, #0 800c94a: 63fb str r3, [r7, #60] @ 0x3c break; 800c94c: e3bd b.n 800d0ca } case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800c94e: 4b6f ldr r3, [pc, #444] @ (800cb0c ) 800c950: 6cdb ldr r3, [r3, #76] @ 0x4c 800c952: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800c956: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800c958: 4b6c ldr r3, [pc, #432] @ (800cb0c ) 800c95a: 681b ldr r3, [r3, #0] 800c95c: f003 0304 and.w r3, r3, #4 800c960: 2b04 cmp r3, #4 800c962: d10c bne.n 800c97e 800c964: 6b7b ldr r3, [r7, #52] @ 0x34 800c966: 2b00 cmp r3, #0 800c968: d109 bne.n 800c97e { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800c96a: 4b68 ldr r3, [pc, #416] @ (800cb0c ) 800c96c: 681b ldr r3, [r3, #0] 800c96e: 08db lsrs r3, r3, #3 800c970: f003 0303 and.w r3, r3, #3 800c974: 4a66 ldr r2, [pc, #408] @ (800cb10 ) 800c976: fa22 f303 lsr.w r3, r2, r3 800c97a: 63fb str r3, [r7, #60] @ 0x3c 800c97c: e01e b.n 800c9bc } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800c97e: 4b63 ldr r3, [pc, #396] @ (800cb0c ) 800c980: 681b ldr r3, [r3, #0] 800c982: f403 7380 and.w r3, r3, #256 @ 0x100 800c986: f5b3 7f80 cmp.w r3, #256 @ 0x100 800c98a: d106 bne.n 800c99a 800c98c: 6b7b ldr r3, [r7, #52] @ 0x34 800c98e: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800c992: d102 bne.n 800c99a { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800c994: 4b5f ldr r3, [pc, #380] @ (800cb14 ) 800c996: 63fb str r3, [r7, #60] @ 0x3c 800c998: e010 b.n 800c9bc } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800c99a: 4b5c ldr r3, [pc, #368] @ (800cb0c ) 800c99c: 681b ldr r3, [r3, #0] 800c99e: f403 3300 and.w r3, r3, #131072 @ 0x20000 800c9a2: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800c9a6: d106 bne.n 800c9b6 800c9a8: 6b7b ldr r3, [r7, #52] @ 0x34 800c9aa: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800c9ae: d102 bne.n 800c9b6 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800c9b0: 4b59 ldr r3, [pc, #356] @ (800cb18 ) 800c9b2: 63fb str r3, [r7, #60] @ 0x3c 800c9b4: e002 b.n 800c9bc } else { /* In Case the CKPER is disabled*/ frequency = 0; 800c9b6: 2300 movs r3, #0 800c9b8: 63fb str r3, [r7, #60] @ 0x3c } break; 800c9ba: e386 b.n 800d0ca 800c9bc: e385 b.n 800d0ca } case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ { frequency = EXTERNAL_CLOCK_VALUE; 800c9be: 4b57 ldr r3, [pc, #348] @ (800cb1c ) 800c9c0: 63fb str r3, [r7, #60] @ 0x3c break; 800c9c2: e382 b.n 800d0ca } default : { frequency = 0; 800c9c4: 2300 movs r3, #0 800c9c6: 63fb str r3, [r7, #60] @ 0x3c break; 800c9c8: e37f b.n 800d0ca } } } else if (PeriphClk == RCC_PERIPHCLK_SAI4B) 800c9ca: e9d7 2300 ldrd r2, r3, [r7] 800c9ce: f5a2 6100 sub.w r1, r2, #2048 @ 0x800 800c9d2: 430b orrs r3, r1 800c9d4: f040 80a7 bne.w 800cb26 { saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE(); 800c9d8: 4b4c ldr r3, [pc, #304] @ (800cb0c ) 800c9da: 6d9b ldr r3, [r3, #88] @ 0x58 800c9dc: f003 63e0 and.w r3, r3, #117440512 @ 0x7000000 800c9e0: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800c9e2: 6b3b ldr r3, [r7, #48] @ 0x30 800c9e4: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800c9e8: d055 beq.n 800ca96 800c9ea: 6b3b ldr r3, [r7, #48] @ 0x30 800c9ec: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800c9f0: f200 8096 bhi.w 800cb20 800c9f4: 6b3b ldr r3, [r7, #48] @ 0x30 800c9f6: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800c9fa: f000 8084 beq.w 800cb06 800c9fe: 6b3b ldr r3, [r7, #48] @ 0x30 800ca00: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800ca04: f200 808c bhi.w 800cb20 800ca08: 6b3b ldr r3, [r7, #48] @ 0x30 800ca0a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800ca0e: d030 beq.n 800ca72 800ca10: 6b3b ldr r3, [r7, #48] @ 0x30 800ca12: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800ca16: f200 8083 bhi.w 800cb20 800ca1a: 6b3b ldr r3, [r7, #48] @ 0x30 800ca1c: 2b00 cmp r3, #0 800ca1e: d004 beq.n 800ca2a 800ca20: 6b3b ldr r3, [r7, #48] @ 0x30 800ca22: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800ca26: d012 beq.n 800ca4e 800ca28: e07a b.n 800cb20 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800ca2a: 4b38 ldr r3, [pc, #224] @ (800cb0c ) 800ca2c: 681b ldr r3, [r3, #0] 800ca2e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800ca32: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800ca36: d107 bne.n 800ca48 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800ca38: f107 0324 add.w r3, r7, #36 @ 0x24 800ca3c: 4618 mov r0, r3 800ca3e: f000 fe0b bl 800d658 frequency = pll1_clocks.PLL1_Q_Frequency; 800ca42: 6abb ldr r3, [r7, #40] @ 0x28 800ca44: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800ca46: e340 b.n 800d0ca frequency = 0; 800ca48: 2300 movs r3, #0 800ca4a: 63fb str r3, [r7, #60] @ 0x3c break; 800ca4c: e33d b.n 800d0ca } case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800ca4e: 4b2f ldr r3, [pc, #188] @ (800cb0c ) 800ca50: 681b ldr r3, [r3, #0] 800ca52: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800ca56: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800ca5a: d107 bne.n 800ca6c { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800ca5c: f107 0318 add.w r3, r7, #24 800ca60: 4618 mov r0, r3 800ca62: f000 fb51 bl 800d108 frequency = pll2_clocks.PLL2_P_Frequency; 800ca66: 69bb ldr r3, [r7, #24] 800ca68: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800ca6a: e32e b.n 800d0ca frequency = 0; 800ca6c: 2300 movs r3, #0 800ca6e: 63fb str r3, [r7, #60] @ 0x3c break; 800ca70: e32b b.n 800d0ca } case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800ca72: 4b26 ldr r3, [pc, #152] @ (800cb0c ) 800ca74: 681b ldr r3, [r3, #0] 800ca76: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800ca7a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800ca7e: d107 bne.n 800ca90 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800ca80: f107 030c add.w r3, r7, #12 800ca84: 4618 mov r0, r3 800ca86: f000 fc93 bl 800d3b0 frequency = pll3_clocks.PLL3_P_Frequency; 800ca8a: 68fb ldr r3, [r7, #12] 800ca8c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800ca8e: e31c b.n 800d0ca frequency = 0; 800ca90: 2300 movs r3, #0 800ca92: 63fb str r3, [r7, #60] @ 0x3c break; 800ca94: e319 b.n 800d0ca } case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800ca96: 4b1d ldr r3, [pc, #116] @ (800cb0c ) 800ca98: 6cdb ldr r3, [r3, #76] @ 0x4c 800ca9a: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800ca9e: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800caa0: 4b1a ldr r3, [pc, #104] @ (800cb0c ) 800caa2: 681b ldr r3, [r3, #0] 800caa4: f003 0304 and.w r3, r3, #4 800caa8: 2b04 cmp r3, #4 800caaa: d10c bne.n 800cac6 800caac: 6b7b ldr r3, [r7, #52] @ 0x34 800caae: 2b00 cmp r3, #0 800cab0: d109 bne.n 800cac6 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800cab2: 4b16 ldr r3, [pc, #88] @ (800cb0c ) 800cab4: 681b ldr r3, [r3, #0] 800cab6: 08db lsrs r3, r3, #3 800cab8: f003 0303 and.w r3, r3, #3 800cabc: 4a14 ldr r2, [pc, #80] @ (800cb10 ) 800cabe: fa22 f303 lsr.w r3, r2, r3 800cac2: 63fb str r3, [r7, #60] @ 0x3c 800cac4: e01e b.n 800cb04 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800cac6: 4b11 ldr r3, [pc, #68] @ (800cb0c ) 800cac8: 681b ldr r3, [r3, #0] 800caca: f403 7380 and.w r3, r3, #256 @ 0x100 800cace: f5b3 7f80 cmp.w r3, #256 @ 0x100 800cad2: d106 bne.n 800cae2 800cad4: 6b7b ldr r3, [r7, #52] @ 0x34 800cad6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800cada: d102 bne.n 800cae2 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800cadc: 4b0d ldr r3, [pc, #52] @ (800cb14 ) 800cade: 63fb str r3, [r7, #60] @ 0x3c 800cae0: e010 b.n 800cb04 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800cae2: 4b0a ldr r3, [pc, #40] @ (800cb0c ) 800cae4: 681b ldr r3, [r3, #0] 800cae6: f403 3300 and.w r3, r3, #131072 @ 0x20000 800caea: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800caee: d106 bne.n 800cafe 800caf0: 6b7b ldr r3, [r7, #52] @ 0x34 800caf2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800caf6: d102 bne.n 800cafe { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800caf8: 4b07 ldr r3, [pc, #28] @ (800cb18 ) 800cafa: 63fb str r3, [r7, #60] @ 0x3c 800cafc: e002 b.n 800cb04 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800cafe: 2300 movs r3, #0 800cb00: 63fb str r3, [r7, #60] @ 0x3c } break; 800cb02: e2e2 b.n 800d0ca 800cb04: e2e1 b.n 800d0ca } case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ { frequency = EXTERNAL_CLOCK_VALUE; 800cb06: 4b05 ldr r3, [pc, #20] @ (800cb1c ) 800cb08: 63fb str r3, [r7, #60] @ 0x3c break; 800cb0a: e2de b.n 800d0ca 800cb0c: 58024400 .word 0x58024400 800cb10: 03d09000 .word 0x03d09000 800cb14: 003d0900 .word 0x003d0900 800cb18: 017d7840 .word 0x017d7840 800cb1c: 00bb8000 .word 0x00bb8000 } default : { frequency = 0; 800cb20: 2300 movs r3, #0 800cb22: 63fb str r3, [r7, #60] @ 0x3c break; 800cb24: e2d1 b.n 800d0ca } } } #endif /*SAI4*/ else if (PeriphClk == RCC_PERIPHCLK_SPI123) 800cb26: e9d7 2300 ldrd r2, r3, [r7] 800cb2a: f5a2 5180 sub.w r1, r2, #4096 @ 0x1000 800cb2e: 430b orrs r3, r1 800cb30: f040 809c bne.w 800cc6c { /* Get SPI1/2/3 clock source */ srcclk = __HAL_RCC_GET_SPI123_SOURCE(); 800cb34: 4b93 ldr r3, [pc, #588] @ (800cd84 ) 800cb36: 6d1b ldr r3, [r3, #80] @ 0x50 800cb38: f403 43e0 and.w r3, r3, #28672 @ 0x7000 800cb3c: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800cb3e: 6bbb ldr r3, [r7, #56] @ 0x38 800cb40: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800cb44: d054 beq.n 800cbf0 800cb46: 6bbb ldr r3, [r7, #56] @ 0x38 800cb48: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800cb4c: f200 808b bhi.w 800cc66 800cb50: 6bbb ldr r3, [r7, #56] @ 0x38 800cb52: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800cb56: f000 8083 beq.w 800cc60 800cb5a: 6bbb ldr r3, [r7, #56] @ 0x38 800cb5c: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800cb60: f200 8081 bhi.w 800cc66 800cb64: 6bbb ldr r3, [r7, #56] @ 0x38 800cb66: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800cb6a: d02f beq.n 800cbcc 800cb6c: 6bbb ldr r3, [r7, #56] @ 0x38 800cb6e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800cb72: d878 bhi.n 800cc66 800cb74: 6bbb ldr r3, [r7, #56] @ 0x38 800cb76: 2b00 cmp r3, #0 800cb78: d004 beq.n 800cb84 800cb7a: 6bbb ldr r3, [r7, #56] @ 0x38 800cb7c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800cb80: d012 beq.n 800cba8 800cb82: e070 b.n 800cc66 { case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800cb84: 4b7f ldr r3, [pc, #508] @ (800cd84 ) 800cb86: 681b ldr r3, [r3, #0] 800cb88: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800cb8c: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800cb90: d107 bne.n 800cba2 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800cb92: f107 0324 add.w r3, r7, #36 @ 0x24 800cb96: 4618 mov r0, r3 800cb98: f000 fd5e bl 800d658 frequency = pll1_clocks.PLL1_Q_Frequency; 800cb9c: 6abb ldr r3, [r7, #40] @ 0x28 800cb9e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800cba0: e293 b.n 800d0ca frequency = 0; 800cba2: 2300 movs r3, #0 800cba4: 63fb str r3, [r7, #60] @ 0x3c break; 800cba6: e290 b.n 800d0ca } case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800cba8: 4b76 ldr r3, [pc, #472] @ (800cd84 ) 800cbaa: 681b ldr r3, [r3, #0] 800cbac: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800cbb0: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800cbb4: d107 bne.n 800cbc6 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800cbb6: f107 0318 add.w r3, r7, #24 800cbba: 4618 mov r0, r3 800cbbc: f000 faa4 bl 800d108 frequency = pll2_clocks.PLL2_P_Frequency; 800cbc0: 69bb ldr r3, [r7, #24] 800cbc2: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800cbc4: e281 b.n 800d0ca frequency = 0; 800cbc6: 2300 movs r3, #0 800cbc8: 63fb str r3, [r7, #60] @ 0x3c break; 800cbca: e27e b.n 800d0ca } case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800cbcc: 4b6d ldr r3, [pc, #436] @ (800cd84 ) 800cbce: 681b ldr r3, [r3, #0] 800cbd0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800cbd4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cbd8: d107 bne.n 800cbea { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800cbda: f107 030c add.w r3, r7, #12 800cbde: 4618 mov r0, r3 800cbe0: f000 fbe6 bl 800d3b0 frequency = pll3_clocks.PLL3_P_Frequency; 800cbe4: 68fb ldr r3, [r7, #12] 800cbe6: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800cbe8: e26f b.n 800d0ca frequency = 0; 800cbea: 2300 movs r3, #0 800cbec: 63fb str r3, [r7, #60] @ 0x3c break; 800cbee: e26c b.n 800d0ca } case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800cbf0: 4b64 ldr r3, [pc, #400] @ (800cd84 ) 800cbf2: 6cdb ldr r3, [r3, #76] @ 0x4c 800cbf4: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800cbf8: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800cbfa: 4b62 ldr r3, [pc, #392] @ (800cd84 ) 800cbfc: 681b ldr r3, [r3, #0] 800cbfe: f003 0304 and.w r3, r3, #4 800cc02: 2b04 cmp r3, #4 800cc04: d10c bne.n 800cc20 800cc06: 6b7b ldr r3, [r7, #52] @ 0x34 800cc08: 2b00 cmp r3, #0 800cc0a: d109 bne.n 800cc20 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800cc0c: 4b5d ldr r3, [pc, #372] @ (800cd84 ) 800cc0e: 681b ldr r3, [r3, #0] 800cc10: 08db lsrs r3, r3, #3 800cc12: f003 0303 and.w r3, r3, #3 800cc16: 4a5c ldr r2, [pc, #368] @ (800cd88 ) 800cc18: fa22 f303 lsr.w r3, r2, r3 800cc1c: 63fb str r3, [r7, #60] @ 0x3c 800cc1e: e01e b.n 800cc5e } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800cc20: 4b58 ldr r3, [pc, #352] @ (800cd84 ) 800cc22: 681b ldr r3, [r3, #0] 800cc24: f403 7380 and.w r3, r3, #256 @ 0x100 800cc28: f5b3 7f80 cmp.w r3, #256 @ 0x100 800cc2c: d106 bne.n 800cc3c 800cc2e: 6b7b ldr r3, [r7, #52] @ 0x34 800cc30: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800cc34: d102 bne.n 800cc3c { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800cc36: 4b55 ldr r3, [pc, #340] @ (800cd8c ) 800cc38: 63fb str r3, [r7, #60] @ 0x3c 800cc3a: e010 b.n 800cc5e } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800cc3c: 4b51 ldr r3, [pc, #324] @ (800cd84 ) 800cc3e: 681b ldr r3, [r3, #0] 800cc40: f403 3300 and.w r3, r3, #131072 @ 0x20000 800cc44: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800cc48: d106 bne.n 800cc58 800cc4a: 6b7b ldr r3, [r7, #52] @ 0x34 800cc4c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cc50: d102 bne.n 800cc58 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800cc52: 4b4f ldr r3, [pc, #316] @ (800cd90 ) 800cc54: 63fb str r3, [r7, #60] @ 0x3c 800cc56: e002 b.n 800cc5e } else { /* In Case the CKPER is disabled*/ frequency = 0; 800cc58: 2300 movs r3, #0 800cc5a: 63fb str r3, [r7, #60] @ 0x3c } break; 800cc5c: e235 b.n 800d0ca 800cc5e: e234 b.n 800d0ca } case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ { frequency = EXTERNAL_CLOCK_VALUE; 800cc60: 4b4c ldr r3, [pc, #304] @ (800cd94 ) 800cc62: 63fb str r3, [r7, #60] @ 0x3c break; 800cc64: e231 b.n 800d0ca } default : { frequency = 0; 800cc66: 2300 movs r3, #0 800cc68: 63fb str r3, [r7, #60] @ 0x3c break; 800cc6a: e22e b.n 800d0ca } } } else if (PeriphClk == RCC_PERIPHCLK_SPI45) 800cc6c: e9d7 2300 ldrd r2, r3, [r7] 800cc70: f5a2 5100 sub.w r1, r2, #8192 @ 0x2000 800cc74: 430b orrs r3, r1 800cc76: f040 808f bne.w 800cd98 { /* Get SPI45 clock source */ srcclk = __HAL_RCC_GET_SPI45_SOURCE(); 800cc7a: 4b42 ldr r3, [pc, #264] @ (800cd84 ) 800cc7c: 6d1b ldr r3, [r3, #80] @ 0x50 800cc7e: f403 23e0 and.w r3, r3, #458752 @ 0x70000 800cc82: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800cc84: 6bbb ldr r3, [r7, #56] @ 0x38 800cc86: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800cc8a: d06b beq.n 800cd64 800cc8c: 6bbb ldr r3, [r7, #56] @ 0x38 800cc8e: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800cc92: d874 bhi.n 800cd7e 800cc94: 6bbb ldr r3, [r7, #56] @ 0x38 800cc96: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800cc9a: d056 beq.n 800cd4a 800cc9c: 6bbb ldr r3, [r7, #56] @ 0x38 800cc9e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800cca2: d86c bhi.n 800cd7e 800cca4: 6bbb ldr r3, [r7, #56] @ 0x38 800cca6: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800ccaa: d03b beq.n 800cd24 800ccac: 6bbb ldr r3, [r7, #56] @ 0x38 800ccae: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800ccb2: d864 bhi.n 800cd7e 800ccb4: 6bbb ldr r3, [r7, #56] @ 0x38 800ccb6: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800ccba: d021 beq.n 800cd00 800ccbc: 6bbb ldr r3, [r7, #56] @ 0x38 800ccbe: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800ccc2: d85c bhi.n 800cd7e 800ccc4: 6bbb ldr r3, [r7, #56] @ 0x38 800ccc6: 2b00 cmp r3, #0 800ccc8: d004 beq.n 800ccd4 800ccca: 6bbb ldr r3, [r7, #56] @ 0x38 800cccc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800ccd0: d004 beq.n 800ccdc 800ccd2: e054 b.n 800cd7e { case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */ { frequency = HAL_RCC_GetPCLK1Freq(); 800ccd4: f7fe fa26 bl 800b124 800ccd8: 63f8 str r0, [r7, #60] @ 0x3c break; 800ccda: e1f6 b.n 800d0ca } case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800ccdc: 4b29 ldr r3, [pc, #164] @ (800cd84 ) 800ccde: 681b ldr r3, [r3, #0] 800cce0: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800cce4: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800cce8: d107 bne.n 800ccfa { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800ccea: f107 0318 add.w r3, r7, #24 800ccee: 4618 mov r0, r3 800ccf0: f000 fa0a bl 800d108 frequency = pll2_clocks.PLL2_Q_Frequency; 800ccf4: 69fb ldr r3, [r7, #28] 800ccf6: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800ccf8: e1e7 b.n 800d0ca frequency = 0; 800ccfa: 2300 movs r3, #0 800ccfc: 63fb str r3, [r7, #60] @ 0x3c break; 800ccfe: e1e4 b.n 800d0ca } case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800cd00: 4b20 ldr r3, [pc, #128] @ (800cd84 ) 800cd02: 681b ldr r3, [r3, #0] 800cd04: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800cd08: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cd0c: d107 bne.n 800cd1e { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800cd0e: f107 030c add.w r3, r7, #12 800cd12: 4618 mov r0, r3 800cd14: f000 fb4c bl 800d3b0 frequency = pll3_clocks.PLL3_Q_Frequency; 800cd18: 693b ldr r3, [r7, #16] 800cd1a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800cd1c: e1d5 b.n 800d0ca frequency = 0; 800cd1e: 2300 movs r3, #0 800cd20: 63fb str r3, [r7, #60] @ 0x3c break; 800cd22: e1d2 b.n 800d0ca } case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800cd24: 4b17 ldr r3, [pc, #92] @ (800cd84 ) 800cd26: 681b ldr r3, [r3, #0] 800cd28: f003 0304 and.w r3, r3, #4 800cd2c: 2b04 cmp r3, #4 800cd2e: d109 bne.n 800cd44 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800cd30: 4b14 ldr r3, [pc, #80] @ (800cd84 ) 800cd32: 681b ldr r3, [r3, #0] 800cd34: 08db lsrs r3, r3, #3 800cd36: f003 0303 and.w r3, r3, #3 800cd3a: 4a13 ldr r2, [pc, #76] @ (800cd88 ) 800cd3c: fa22 f303 lsr.w r3, r2, r3 800cd40: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800cd42: e1c2 b.n 800d0ca frequency = 0; 800cd44: 2300 movs r3, #0 800cd46: 63fb str r3, [r7, #60] @ 0x3c break; 800cd48: e1bf b.n 800d0ca } case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 800cd4a: 4b0e ldr r3, [pc, #56] @ (800cd84 ) 800cd4c: 681b ldr r3, [r3, #0] 800cd4e: f403 7380 and.w r3, r3, #256 @ 0x100 800cd52: f5b3 7f80 cmp.w r3, #256 @ 0x100 800cd56: d102 bne.n 800cd5e { frequency = CSI_VALUE; 800cd58: 4b0c ldr r3, [pc, #48] @ (800cd8c ) 800cd5a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800cd5c: e1b5 b.n 800d0ca frequency = 0; 800cd5e: 2300 movs r3, #0 800cd60: 63fb str r3, [r7, #60] @ 0x3c break; 800cd62: e1b2 b.n 800d0ca } case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800cd64: 4b07 ldr r3, [pc, #28] @ (800cd84 ) 800cd66: 681b ldr r3, [r3, #0] 800cd68: f403 3300 and.w r3, r3, #131072 @ 0x20000 800cd6c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800cd70: d102 bne.n 800cd78 { frequency = HSE_VALUE; 800cd72: 4b07 ldr r3, [pc, #28] @ (800cd90 ) 800cd74: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800cd76: e1a8 b.n 800d0ca frequency = 0; 800cd78: 2300 movs r3, #0 800cd7a: 63fb str r3, [r7, #60] @ 0x3c break; 800cd7c: e1a5 b.n 800d0ca } default : { frequency = 0; 800cd7e: 2300 movs r3, #0 800cd80: 63fb str r3, [r7, #60] @ 0x3c break; 800cd82: e1a2 b.n 800d0ca 800cd84: 58024400 .word 0x58024400 800cd88: 03d09000 .word 0x03d09000 800cd8c: 003d0900 .word 0x003d0900 800cd90: 017d7840 .word 0x017d7840 800cd94: 00bb8000 .word 0x00bb8000 } } } else if (PeriphClk == RCC_PERIPHCLK_ADC) 800cd98: e9d7 2300 ldrd r2, r3, [r7] 800cd9c: f5a2 2100 sub.w r1, r2, #524288 @ 0x80000 800cda0: 430b orrs r3, r1 800cda2: d173 bne.n 800ce8c { /* Get ADC clock source */ srcclk = __HAL_RCC_GET_ADC_SOURCE(); 800cda4: 4b9c ldr r3, [pc, #624] @ (800d018 ) 800cda6: 6d9b ldr r3, [r3, #88] @ 0x58 800cda8: f403 3340 and.w r3, r3, #196608 @ 0x30000 800cdac: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800cdae: 6bbb ldr r3, [r7, #56] @ 0x38 800cdb0: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800cdb4: d02f beq.n 800ce16 800cdb6: 6bbb ldr r3, [r7, #56] @ 0x38 800cdb8: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800cdbc: d863 bhi.n 800ce86 800cdbe: 6bbb ldr r3, [r7, #56] @ 0x38 800cdc0: 2b00 cmp r3, #0 800cdc2: d004 beq.n 800cdce 800cdc4: 6bbb ldr r3, [r7, #56] @ 0x38 800cdc6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800cdca: d012 beq.n 800cdf2 800cdcc: e05b b.n 800ce86 { case RCC_ADCCLKSOURCE_PLL2: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800cdce: 4b92 ldr r3, [pc, #584] @ (800d018 ) 800cdd0: 681b ldr r3, [r3, #0] 800cdd2: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800cdd6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800cdda: d107 bne.n 800cdec { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800cddc: f107 0318 add.w r3, r7, #24 800cde0: 4618 mov r0, r3 800cde2: f000 f991 bl 800d108 frequency = pll2_clocks.PLL2_P_Frequency; 800cde6: 69bb ldr r3, [r7, #24] 800cde8: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800cdea: e16e b.n 800d0ca frequency = 0; 800cdec: 2300 movs r3, #0 800cdee: 63fb str r3, [r7, #60] @ 0x3c break; 800cdf0: e16b b.n 800d0ca } case RCC_ADCCLKSOURCE_PLL3: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800cdf2: 4b89 ldr r3, [pc, #548] @ (800d018 ) 800cdf4: 681b ldr r3, [r3, #0] 800cdf6: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800cdfa: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cdfe: d107 bne.n 800ce10 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800ce00: f107 030c add.w r3, r7, #12 800ce04: 4618 mov r0, r3 800ce06: f000 fad3 bl 800d3b0 frequency = pll3_clocks.PLL3_R_Frequency; 800ce0a: 697b ldr r3, [r7, #20] 800ce0c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800ce0e: e15c b.n 800d0ca frequency = 0; 800ce10: 2300 movs r3, #0 800ce12: 63fb str r3, [r7, #60] @ 0x3c break; 800ce14: e159 b.n 800d0ca } case RCC_ADCCLKSOURCE_CLKP: { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800ce16: 4b80 ldr r3, [pc, #512] @ (800d018 ) 800ce18: 6cdb ldr r3, [r3, #76] @ 0x4c 800ce1a: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800ce1e: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800ce20: 4b7d ldr r3, [pc, #500] @ (800d018 ) 800ce22: 681b ldr r3, [r3, #0] 800ce24: f003 0304 and.w r3, r3, #4 800ce28: 2b04 cmp r3, #4 800ce2a: d10c bne.n 800ce46 800ce2c: 6b7b ldr r3, [r7, #52] @ 0x34 800ce2e: 2b00 cmp r3, #0 800ce30: d109 bne.n 800ce46 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800ce32: 4b79 ldr r3, [pc, #484] @ (800d018 ) 800ce34: 681b ldr r3, [r3, #0] 800ce36: 08db lsrs r3, r3, #3 800ce38: f003 0303 and.w r3, r3, #3 800ce3c: 4a77 ldr r2, [pc, #476] @ (800d01c ) 800ce3e: fa22 f303 lsr.w r3, r2, r3 800ce42: 63fb str r3, [r7, #60] @ 0x3c 800ce44: e01e b.n 800ce84 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800ce46: 4b74 ldr r3, [pc, #464] @ (800d018 ) 800ce48: 681b ldr r3, [r3, #0] 800ce4a: f403 7380 and.w r3, r3, #256 @ 0x100 800ce4e: f5b3 7f80 cmp.w r3, #256 @ 0x100 800ce52: d106 bne.n 800ce62 800ce54: 6b7b ldr r3, [r7, #52] @ 0x34 800ce56: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800ce5a: d102 bne.n 800ce62 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800ce5c: 4b70 ldr r3, [pc, #448] @ (800d020 ) 800ce5e: 63fb str r3, [r7, #60] @ 0x3c 800ce60: e010 b.n 800ce84 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800ce62: 4b6d ldr r3, [pc, #436] @ (800d018 ) 800ce64: 681b ldr r3, [r3, #0] 800ce66: f403 3300 and.w r3, r3, #131072 @ 0x20000 800ce6a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800ce6e: d106 bne.n 800ce7e 800ce70: 6b7b ldr r3, [r7, #52] @ 0x34 800ce72: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800ce76: d102 bne.n 800ce7e { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800ce78: 4b6a ldr r3, [pc, #424] @ (800d024 ) 800ce7a: 63fb str r3, [r7, #60] @ 0x3c 800ce7c: e002 b.n 800ce84 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800ce7e: 2300 movs r3, #0 800ce80: 63fb str r3, [r7, #60] @ 0x3c } break; 800ce82: e122 b.n 800d0ca 800ce84: e121 b.n 800d0ca } default : { frequency = 0; 800ce86: 2300 movs r3, #0 800ce88: 63fb str r3, [r7, #60] @ 0x3c break; 800ce8a: e11e b.n 800d0ca } } } else if (PeriphClk == RCC_PERIPHCLK_SDMMC) 800ce8c: e9d7 2300 ldrd r2, r3, [r7] 800ce90: f5a2 3180 sub.w r1, r2, #65536 @ 0x10000 800ce94: 430b orrs r3, r1 800ce96: d133 bne.n 800cf00 { /* Get SDMMC clock source */ srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); 800ce98: 4b5f ldr r3, [pc, #380] @ (800d018 ) 800ce9a: 6cdb ldr r3, [r3, #76] @ 0x4c 800ce9c: f403 3380 and.w r3, r3, #65536 @ 0x10000 800cea0: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800cea2: 6bbb ldr r3, [r7, #56] @ 0x38 800cea4: 2b00 cmp r3, #0 800cea6: d004 beq.n 800ceb2 800cea8: 6bbb ldr r3, [r7, #56] @ 0x38 800ceaa: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800ceae: d012 beq.n 800ced6 800ceb0: e023 b.n 800cefa { case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800ceb2: 4b59 ldr r3, [pc, #356] @ (800d018 ) 800ceb4: 681b ldr r3, [r3, #0] 800ceb6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800ceba: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800cebe: d107 bne.n 800ced0 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800cec0: f107 0324 add.w r3, r7, #36 @ 0x24 800cec4: 4618 mov r0, r3 800cec6: f000 fbc7 bl 800d658 frequency = pll1_clocks.PLL1_Q_Frequency; 800ceca: 6abb ldr r3, [r7, #40] @ 0x28 800cecc: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800cece: e0fc b.n 800d0ca frequency = 0; 800ced0: 2300 movs r3, #0 800ced2: 63fb str r3, [r7, #60] @ 0x3c break; 800ced4: e0f9 b.n 800d0ca } case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800ced6: 4b50 ldr r3, [pc, #320] @ (800d018 ) 800ced8: 681b ldr r3, [r3, #0] 800ceda: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800cede: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800cee2: d107 bne.n 800cef4 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800cee4: f107 0318 add.w r3, r7, #24 800cee8: 4618 mov r0, r3 800ceea: f000 f90d bl 800d108 frequency = pll2_clocks.PLL2_R_Frequency; 800ceee: 6a3b ldr r3, [r7, #32] 800cef0: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800cef2: e0ea b.n 800d0ca frequency = 0; 800cef4: 2300 movs r3, #0 800cef6: 63fb str r3, [r7, #60] @ 0x3c break; 800cef8: e0e7 b.n 800d0ca } default : { frequency = 0; 800cefa: 2300 movs r3, #0 800cefc: 63fb str r3, [r7, #60] @ 0x3c break; 800cefe: e0e4 b.n 800d0ca } } } else if (PeriphClk == RCC_PERIPHCLK_SPI6) 800cf00: e9d7 2300 ldrd r2, r3, [r7] 800cf04: f5a2 4180 sub.w r1, r2, #16384 @ 0x4000 800cf08: 430b orrs r3, r1 800cf0a: f040 808d bne.w 800d028 { /* Get SPI6 clock source */ srcclk = __HAL_RCC_GET_SPI6_SOURCE(); 800cf0e: 4b42 ldr r3, [pc, #264] @ (800d018 ) 800cf10: 6d9b ldr r3, [r3, #88] @ 0x58 800cf12: f003 43e0 and.w r3, r3, #1879048192 @ 0x70000000 800cf16: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800cf18: 6bbb ldr r3, [r7, #56] @ 0x38 800cf1a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800cf1e: d06b beq.n 800cff8 800cf20: 6bbb ldr r3, [r7, #56] @ 0x38 800cf22: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800cf26: d874 bhi.n 800d012 800cf28: 6bbb ldr r3, [r7, #56] @ 0x38 800cf2a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800cf2e: d056 beq.n 800cfde 800cf30: 6bbb ldr r3, [r7, #56] @ 0x38 800cf32: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800cf36: d86c bhi.n 800d012 800cf38: 6bbb ldr r3, [r7, #56] @ 0x38 800cf3a: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800cf3e: d03b beq.n 800cfb8 800cf40: 6bbb ldr r3, [r7, #56] @ 0x38 800cf42: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800cf46: d864 bhi.n 800d012 800cf48: 6bbb ldr r3, [r7, #56] @ 0x38 800cf4a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cf4e: d021 beq.n 800cf94 800cf50: 6bbb ldr r3, [r7, #56] @ 0x38 800cf52: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cf56: d85c bhi.n 800d012 800cf58: 6bbb ldr r3, [r7, #56] @ 0x38 800cf5a: 2b00 cmp r3, #0 800cf5c: d004 beq.n 800cf68 800cf5e: 6bbb ldr r3, [r7, #56] @ 0x38 800cf60: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800cf64: d004 beq.n 800cf70 800cf66: e054 b.n 800d012 { case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ { frequency = HAL_RCCEx_GetD3PCLK1Freq(); 800cf68: f000 f8b8 bl 800d0dc 800cf6c: 63f8 str r0, [r7, #60] @ 0x3c break; 800cf6e: e0ac b.n 800d0ca } case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800cf70: 4b29 ldr r3, [pc, #164] @ (800d018 ) 800cf72: 681b ldr r3, [r3, #0] 800cf74: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800cf78: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800cf7c: d107 bne.n 800cf8e { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800cf7e: f107 0318 add.w r3, r7, #24 800cf82: 4618 mov r0, r3 800cf84: f000 f8c0 bl 800d108 frequency = pll2_clocks.PLL2_Q_Frequency; 800cf88: 69fb ldr r3, [r7, #28] 800cf8a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800cf8c: e09d b.n 800d0ca frequency = 0; 800cf8e: 2300 movs r3, #0 800cf90: 63fb str r3, [r7, #60] @ 0x3c break; 800cf92: e09a b.n 800d0ca } case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800cf94: 4b20 ldr r3, [pc, #128] @ (800d018 ) 800cf96: 681b ldr r3, [r3, #0] 800cf98: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800cf9c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cfa0: d107 bne.n 800cfb2 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800cfa2: f107 030c add.w r3, r7, #12 800cfa6: 4618 mov r0, r3 800cfa8: f000 fa02 bl 800d3b0 frequency = pll3_clocks.PLL3_Q_Frequency; 800cfac: 693b ldr r3, [r7, #16] 800cfae: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800cfb0: e08b b.n 800d0ca frequency = 0; 800cfb2: 2300 movs r3, #0 800cfb4: 63fb str r3, [r7, #60] @ 0x3c break; 800cfb6: e088 b.n 800d0ca } case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800cfb8: 4b17 ldr r3, [pc, #92] @ (800d018 ) 800cfba: 681b ldr r3, [r3, #0] 800cfbc: f003 0304 and.w r3, r3, #4 800cfc0: 2b04 cmp r3, #4 800cfc2: d109 bne.n 800cfd8 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800cfc4: 4b14 ldr r3, [pc, #80] @ (800d018 ) 800cfc6: 681b ldr r3, [r3, #0] 800cfc8: 08db lsrs r3, r3, #3 800cfca: f003 0303 and.w r3, r3, #3 800cfce: 4a13 ldr r2, [pc, #76] @ (800d01c ) 800cfd0: fa22 f303 lsr.w r3, r2, r3 800cfd4: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800cfd6: e078 b.n 800d0ca frequency = 0; 800cfd8: 2300 movs r3, #0 800cfda: 63fb str r3, [r7, #60] @ 0x3c break; 800cfdc: e075 b.n 800d0ca } case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 800cfde: 4b0e ldr r3, [pc, #56] @ (800d018 ) 800cfe0: 681b ldr r3, [r3, #0] 800cfe2: f403 7380 and.w r3, r3, #256 @ 0x100 800cfe6: f5b3 7f80 cmp.w r3, #256 @ 0x100 800cfea: d102 bne.n 800cff2 { frequency = CSI_VALUE; 800cfec: 4b0c ldr r3, [pc, #48] @ (800d020 ) 800cfee: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800cff0: e06b b.n 800d0ca frequency = 0; 800cff2: 2300 movs r3, #0 800cff4: 63fb str r3, [r7, #60] @ 0x3c break; 800cff6: e068 b.n 800d0ca } case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800cff8: 4b07 ldr r3, [pc, #28] @ (800d018 ) 800cffa: 681b ldr r3, [r3, #0] 800cffc: f403 3300 and.w r3, r3, #131072 @ 0x20000 800d000: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d004: d102 bne.n 800d00c { frequency = HSE_VALUE; 800d006: 4b07 ldr r3, [pc, #28] @ (800d024 ) 800d008: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d00a: e05e b.n 800d0ca frequency = 0; 800d00c: 2300 movs r3, #0 800d00e: 63fb str r3, [r7, #60] @ 0x3c break; 800d010: e05b b.n 800d0ca break; } #endif /* RCC_SPI6CLKSOURCE_PIN */ default : { frequency = 0; 800d012: 2300 movs r3, #0 800d014: 63fb str r3, [r7, #60] @ 0x3c break; 800d016: e058 b.n 800d0ca 800d018: 58024400 .word 0x58024400 800d01c: 03d09000 .word 0x03d09000 800d020: 003d0900 .word 0x003d0900 800d024: 017d7840 .word 0x017d7840 } } } else if (PeriphClk == RCC_PERIPHCLK_FDCAN) 800d028: e9d7 2300 ldrd r2, r3, [r7] 800d02c: f5a2 4100 sub.w r1, r2, #32768 @ 0x8000 800d030: 430b orrs r3, r1 800d032: d148 bne.n 800d0c6 { /* Get FDCAN clock source */ srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); 800d034: 4b27 ldr r3, [pc, #156] @ (800d0d4 ) 800d036: 6d1b ldr r3, [r3, #80] @ 0x50 800d038: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800d03c: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800d03e: 6bbb ldr r3, [r7, #56] @ 0x38 800d040: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d044: d02a beq.n 800d09c 800d046: 6bbb ldr r3, [r7, #56] @ 0x38 800d048: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d04c: d838 bhi.n 800d0c0 800d04e: 6bbb ldr r3, [r7, #56] @ 0x38 800d050: 2b00 cmp r3, #0 800d052: d004 beq.n 800d05e 800d054: 6bbb ldr r3, [r7, #56] @ 0x38 800d056: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800d05a: d00d beq.n 800d078 800d05c: e030 b.n 800d0c0 { case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800d05e: 4b1d ldr r3, [pc, #116] @ (800d0d4 ) 800d060: 681b ldr r3, [r3, #0] 800d062: f403 3300 and.w r3, r3, #131072 @ 0x20000 800d066: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d06a: d102 bne.n 800d072 { frequency = HSE_VALUE; 800d06c: 4b1a ldr r3, [pc, #104] @ (800d0d8 ) 800d06e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d070: e02b b.n 800d0ca frequency = 0; 800d072: 2300 movs r3, #0 800d074: 63fb str r3, [r7, #60] @ 0x3c break; 800d076: e028 b.n 800d0ca } case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800d078: 4b16 ldr r3, [pc, #88] @ (800d0d4 ) 800d07a: 681b ldr r3, [r3, #0] 800d07c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800d080: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800d084: d107 bne.n 800d096 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800d086: f107 0324 add.w r3, r7, #36 @ 0x24 800d08a: 4618 mov r0, r3 800d08c: f000 fae4 bl 800d658 frequency = pll1_clocks.PLL1_Q_Frequency; 800d090: 6abb ldr r3, [r7, #40] @ 0x28 800d092: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d094: e019 b.n 800d0ca frequency = 0; 800d096: 2300 movs r3, #0 800d098: 63fb str r3, [r7, #60] @ 0x3c break; 800d09a: e016 b.n 800d0ca } case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800d09c: 4b0d ldr r3, [pc, #52] @ (800d0d4 ) 800d09e: 681b ldr r3, [r3, #0] 800d0a0: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800d0a4: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800d0a8: d107 bne.n 800d0ba { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800d0aa: f107 0318 add.w r3, r7, #24 800d0ae: 4618 mov r0, r3 800d0b0: f000 f82a bl 800d108 frequency = pll2_clocks.PLL2_Q_Frequency; 800d0b4: 69fb ldr r3, [r7, #28] 800d0b6: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d0b8: e007 b.n 800d0ca frequency = 0; 800d0ba: 2300 movs r3, #0 800d0bc: 63fb str r3, [r7, #60] @ 0x3c break; 800d0be: e004 b.n 800d0ca } default : { frequency = 0; 800d0c0: 2300 movs r3, #0 800d0c2: 63fb str r3, [r7, #60] @ 0x3c break; 800d0c4: e001 b.n 800d0ca } } } else { frequency = 0; 800d0c6: 2300 movs r3, #0 800d0c8: 63fb str r3, [r7, #60] @ 0x3c } return frequency; 800d0ca: 6bfb ldr r3, [r7, #60] @ 0x3c } 800d0cc: 4618 mov r0, r3 800d0ce: 3740 adds r7, #64 @ 0x40 800d0d0: 46bd mov sp, r7 800d0d2: bd80 pop {r7, pc} 800d0d4: 58024400 .word 0x58024400 800d0d8: 017d7840 .word 0x017d7840 0800d0dc : * @note Each time D3PCLK1 changes, this function must be called to update the * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval D3PCLK1 frequency */ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) { 800d0dc: b580 push {r7, lr} 800d0de: af00 add r7, sp, #0 #if defined(RCC_D3CFGR_D3PPRE) /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); 800d0e0: f7fd fff0 bl 800b0c4 800d0e4: 4602 mov r2, r0 800d0e6: 4b06 ldr r3, [pc, #24] @ (800d100 ) 800d0e8: 6a1b ldr r3, [r3, #32] 800d0ea: 091b lsrs r3, r3, #4 800d0ec: f003 0307 and.w r3, r3, #7 800d0f0: 4904 ldr r1, [pc, #16] @ (800d104 ) 800d0f2: 5ccb ldrb r3, [r1, r3] 800d0f4: f003 031f and.w r3, r3, #31 800d0f8: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); #endif } 800d0fc: 4618 mov r0, r3 800d0fe: bd80 pop {r7, pc} 800d100: 58024400 .word 0x58024400 800d104: 080175c8 .word 0x080175c8 0800d108 : * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL2_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) { 800d108: b480 push {r7} 800d10a: b089 sub sp, #36 @ 0x24 800d10c: af00 add r7, sp, #0 800d10e: 6078 str r0, [r7, #4] float_t fracn2, pll2vco; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N PLL2xCLK = PLL2_VCO / PLL2x */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800d110: 4ba1 ldr r3, [pc, #644] @ (800d398 ) 800d112: 6a9b ldr r3, [r3, #40] @ 0x28 800d114: f003 0303 and.w r3, r3, #3 800d118: 61bb str r3, [r7, #24] pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); 800d11a: 4b9f ldr r3, [pc, #636] @ (800d398 ) 800d11c: 6a9b ldr r3, [r3, #40] @ 0x28 800d11e: 0b1b lsrs r3, r3, #12 800d120: f003 033f and.w r3, r3, #63 @ 0x3f 800d124: 617b str r3, [r7, #20] pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; 800d126: 4b9c ldr r3, [pc, #624] @ (800d398 ) 800d128: 6adb ldr r3, [r3, #44] @ 0x2c 800d12a: 091b lsrs r3, r3, #4 800d12c: f003 0301 and.w r3, r3, #1 800d130: 613b str r3, [r7, #16] fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); 800d132: 4b99 ldr r3, [pc, #612] @ (800d398 ) 800d134: 6bdb ldr r3, [r3, #60] @ 0x3c 800d136: 08db lsrs r3, r3, #3 800d138: f3c3 030c ubfx r3, r3, #0, #13 800d13c: 693a ldr r2, [r7, #16] 800d13e: fb02 f303 mul.w r3, r2, r3 800d142: ee07 3a90 vmov s15, r3 800d146: eef8 7a67 vcvt.f32.u32 s15, s15 800d14a: edc7 7a03 vstr s15, [r7, #12] if (pll2m != 0U) 800d14e: 697b ldr r3, [r7, #20] 800d150: 2b00 cmp r3, #0 800d152: f000 8111 beq.w 800d378 { switch (pllsource) 800d156: 69bb ldr r3, [r7, #24] 800d158: 2b02 cmp r3, #2 800d15a: f000 8083 beq.w 800d264 800d15e: 69bb ldr r3, [r7, #24] 800d160: 2b02 cmp r3, #2 800d162: f200 80a1 bhi.w 800d2a8 800d166: 69bb ldr r3, [r7, #24] 800d168: 2b00 cmp r3, #0 800d16a: d003 beq.n 800d174 800d16c: 69bb ldr r3, [r7, #24] 800d16e: 2b01 cmp r3, #1 800d170: d056 beq.n 800d220 800d172: e099 b.n 800d2a8 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800d174: 4b88 ldr r3, [pc, #544] @ (800d398 ) 800d176: 681b ldr r3, [r3, #0] 800d178: f003 0320 and.w r3, r3, #32 800d17c: 2b00 cmp r3, #0 800d17e: d02d beq.n 800d1dc { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800d180: 4b85 ldr r3, [pc, #532] @ (800d398 ) 800d182: 681b ldr r3, [r3, #0] 800d184: 08db lsrs r3, r3, #3 800d186: f003 0303 and.w r3, r3, #3 800d18a: 4a84 ldr r2, [pc, #528] @ (800d39c ) 800d18c: fa22 f303 lsr.w r3, r2, r3 800d190: 60bb str r3, [r7, #8] pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800d192: 68bb ldr r3, [r7, #8] 800d194: ee07 3a90 vmov s15, r3 800d198: eef8 6a67 vcvt.f32.u32 s13, s15 800d19c: 697b ldr r3, [r7, #20] 800d19e: ee07 3a90 vmov s15, r3 800d1a2: eef8 7a67 vcvt.f32.u32 s15, s15 800d1a6: ee86 7aa7 vdiv.f32 s14, s13, s15 800d1aa: 4b7b ldr r3, [pc, #492] @ (800d398 ) 800d1ac: 6b9b ldr r3, [r3, #56] @ 0x38 800d1ae: f3c3 0308 ubfx r3, r3, #0, #9 800d1b2: ee07 3a90 vmov s15, r3 800d1b6: eef8 6a67 vcvt.f32.u32 s13, s15 800d1ba: ed97 6a03 vldr s12, [r7, #12] 800d1be: eddf 5a78 vldr s11, [pc, #480] @ 800d3a0 800d1c2: eec6 7a25 vdiv.f32 s15, s12, s11 800d1c6: ee76 7aa7 vadd.f32 s15, s13, s15 800d1ca: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800d1ce: ee77 7aa6 vadd.f32 s15, s15, s13 800d1d2: ee67 7a27 vmul.f32 s15, s14, s15 800d1d6: edc7 7a07 vstr s15, [r7, #28] } else { pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); } break; 800d1da: e087 b.n 800d2ec pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800d1dc: 697b ldr r3, [r7, #20] 800d1de: ee07 3a90 vmov s15, r3 800d1e2: eef8 7a67 vcvt.f32.u32 s15, s15 800d1e6: eddf 6a6f vldr s13, [pc, #444] @ 800d3a4 800d1ea: ee86 7aa7 vdiv.f32 s14, s13, s15 800d1ee: 4b6a ldr r3, [pc, #424] @ (800d398 ) 800d1f0: 6b9b ldr r3, [r3, #56] @ 0x38 800d1f2: f3c3 0308 ubfx r3, r3, #0, #9 800d1f6: ee07 3a90 vmov s15, r3 800d1fa: eef8 6a67 vcvt.f32.u32 s13, s15 800d1fe: ed97 6a03 vldr s12, [r7, #12] 800d202: eddf 5a67 vldr s11, [pc, #412] @ 800d3a0 800d206: eec6 7a25 vdiv.f32 s15, s12, s11 800d20a: ee76 7aa7 vadd.f32 s15, s13, s15 800d20e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800d212: ee77 7aa6 vadd.f32 s15, s15, s13 800d216: ee67 7a27 vmul.f32 s15, s14, s15 800d21a: edc7 7a07 vstr s15, [r7, #28] break; 800d21e: e065 b.n 800d2ec case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800d220: 697b ldr r3, [r7, #20] 800d222: ee07 3a90 vmov s15, r3 800d226: eef8 7a67 vcvt.f32.u32 s15, s15 800d22a: eddf 6a5f vldr s13, [pc, #380] @ 800d3a8 800d22e: ee86 7aa7 vdiv.f32 s14, s13, s15 800d232: 4b59 ldr r3, [pc, #356] @ (800d398 ) 800d234: 6b9b ldr r3, [r3, #56] @ 0x38 800d236: f3c3 0308 ubfx r3, r3, #0, #9 800d23a: ee07 3a90 vmov s15, r3 800d23e: eef8 6a67 vcvt.f32.u32 s13, s15 800d242: ed97 6a03 vldr s12, [r7, #12] 800d246: eddf 5a56 vldr s11, [pc, #344] @ 800d3a0 800d24a: eec6 7a25 vdiv.f32 s15, s12, s11 800d24e: ee76 7aa7 vadd.f32 s15, s13, s15 800d252: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800d256: ee77 7aa6 vadd.f32 s15, s15, s13 800d25a: ee67 7a27 vmul.f32 s15, s14, s15 800d25e: edc7 7a07 vstr s15, [r7, #28] break; 800d262: e043 b.n 800d2ec case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800d264: 697b ldr r3, [r7, #20] 800d266: ee07 3a90 vmov s15, r3 800d26a: eef8 7a67 vcvt.f32.u32 s15, s15 800d26e: eddf 6a4f vldr s13, [pc, #316] @ 800d3ac 800d272: ee86 7aa7 vdiv.f32 s14, s13, s15 800d276: 4b48 ldr r3, [pc, #288] @ (800d398 ) 800d278: 6b9b ldr r3, [r3, #56] @ 0x38 800d27a: f3c3 0308 ubfx r3, r3, #0, #9 800d27e: ee07 3a90 vmov s15, r3 800d282: eef8 6a67 vcvt.f32.u32 s13, s15 800d286: ed97 6a03 vldr s12, [r7, #12] 800d28a: eddf 5a45 vldr s11, [pc, #276] @ 800d3a0 800d28e: eec6 7a25 vdiv.f32 s15, s12, s11 800d292: ee76 7aa7 vadd.f32 s15, s13, s15 800d296: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800d29a: ee77 7aa6 vadd.f32 s15, s15, s13 800d29e: ee67 7a27 vmul.f32 s15, s14, s15 800d2a2: edc7 7a07 vstr s15, [r7, #28] break; 800d2a6: e021 b.n 800d2ec default: pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800d2a8: 697b ldr r3, [r7, #20] 800d2aa: ee07 3a90 vmov s15, r3 800d2ae: eef8 7a67 vcvt.f32.u32 s15, s15 800d2b2: eddf 6a3d vldr s13, [pc, #244] @ 800d3a8 800d2b6: ee86 7aa7 vdiv.f32 s14, s13, s15 800d2ba: 4b37 ldr r3, [pc, #220] @ (800d398 ) 800d2bc: 6b9b ldr r3, [r3, #56] @ 0x38 800d2be: f3c3 0308 ubfx r3, r3, #0, #9 800d2c2: ee07 3a90 vmov s15, r3 800d2c6: eef8 6a67 vcvt.f32.u32 s13, s15 800d2ca: ed97 6a03 vldr s12, [r7, #12] 800d2ce: eddf 5a34 vldr s11, [pc, #208] @ 800d3a0 800d2d2: eec6 7a25 vdiv.f32 s15, s12, s11 800d2d6: ee76 7aa7 vadd.f32 s15, s13, s15 800d2da: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800d2de: ee77 7aa6 vadd.f32 s15, s15, s13 800d2e2: ee67 7a27 vmul.f32 s15, s14, s15 800d2e6: edc7 7a07 vstr s15, [r7, #28] break; 800d2ea: bf00 nop } PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; 800d2ec: 4b2a ldr r3, [pc, #168] @ (800d398 ) 800d2ee: 6b9b ldr r3, [r3, #56] @ 0x38 800d2f0: 0a5b lsrs r3, r3, #9 800d2f2: f003 037f and.w r3, r3, #127 @ 0x7f 800d2f6: ee07 3a90 vmov s15, r3 800d2fa: eef8 7a67 vcvt.f32.u32 s15, s15 800d2fe: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800d302: ee37 7a87 vadd.f32 s14, s15, s14 800d306: edd7 6a07 vldr s13, [r7, #28] 800d30a: eec6 7a87 vdiv.f32 s15, s13, s14 800d30e: eefc 7ae7 vcvt.u32.f32 s15, s15 800d312: ee17 2a90 vmov r2, s15 800d316: 687b ldr r3, [r7, #4] 800d318: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; 800d31a: 4b1f ldr r3, [pc, #124] @ (800d398 ) 800d31c: 6b9b ldr r3, [r3, #56] @ 0x38 800d31e: 0c1b lsrs r3, r3, #16 800d320: f003 037f and.w r3, r3, #127 @ 0x7f 800d324: ee07 3a90 vmov s15, r3 800d328: eef8 7a67 vcvt.f32.u32 s15, s15 800d32c: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800d330: ee37 7a87 vadd.f32 s14, s15, s14 800d334: edd7 6a07 vldr s13, [r7, #28] 800d338: eec6 7a87 vdiv.f32 s15, s13, s14 800d33c: eefc 7ae7 vcvt.u32.f32 s15, s15 800d340: ee17 2a90 vmov r2, s15 800d344: 687b ldr r3, [r7, #4] 800d346: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; 800d348: 4b13 ldr r3, [pc, #76] @ (800d398 ) 800d34a: 6b9b ldr r3, [r3, #56] @ 0x38 800d34c: 0e1b lsrs r3, r3, #24 800d34e: f003 037f and.w r3, r3, #127 @ 0x7f 800d352: ee07 3a90 vmov s15, r3 800d356: eef8 7a67 vcvt.f32.u32 s15, s15 800d35a: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800d35e: ee37 7a87 vadd.f32 s14, s15, s14 800d362: edd7 6a07 vldr s13, [r7, #28] 800d366: eec6 7a87 vdiv.f32 s15, s13, s14 800d36a: eefc 7ae7 vcvt.u32.f32 s15, s15 800d36e: ee17 2a90 vmov r2, s15 800d372: 687b ldr r3, [r7, #4] 800d374: 609a str r2, [r3, #8] { PLL2_Clocks->PLL2_P_Frequency = 0U; PLL2_Clocks->PLL2_Q_Frequency = 0U; PLL2_Clocks->PLL2_R_Frequency = 0U; } } 800d376: e008 b.n 800d38a PLL2_Clocks->PLL2_P_Frequency = 0U; 800d378: 687b ldr r3, [r7, #4] 800d37a: 2200 movs r2, #0 800d37c: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = 0U; 800d37e: 687b ldr r3, [r7, #4] 800d380: 2200 movs r2, #0 800d382: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = 0U; 800d384: 687b ldr r3, [r7, #4] 800d386: 2200 movs r2, #0 800d388: 609a str r2, [r3, #8] } 800d38a: bf00 nop 800d38c: 3724 adds r7, #36 @ 0x24 800d38e: 46bd mov sp, r7 800d390: f85d 7b04 ldr.w r7, [sp], #4 800d394: 4770 bx lr 800d396: bf00 nop 800d398: 58024400 .word 0x58024400 800d39c: 03d09000 .word 0x03d09000 800d3a0: 46000000 .word 0x46000000 800d3a4: 4c742400 .word 0x4c742400 800d3a8: 4a742400 .word 0x4a742400 800d3ac: 4bbebc20 .word 0x4bbebc20 0800d3b0 : * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL3_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) { 800d3b0: b480 push {r7} 800d3b2: b089 sub sp, #36 @ 0x24 800d3b4: af00 add r7, sp, #0 800d3b6: 6078 str r0, [r7, #4] float_t fracn3, pll3vco; /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N PLL3xCLK = PLL3_VCO / PLLxR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800d3b8: 4ba1 ldr r3, [pc, #644] @ (800d640 ) 800d3ba: 6a9b ldr r3, [r3, #40] @ 0x28 800d3bc: f003 0303 and.w r3, r3, #3 800d3c0: 61bb str r3, [r7, #24] pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; 800d3c2: 4b9f ldr r3, [pc, #636] @ (800d640 ) 800d3c4: 6a9b ldr r3, [r3, #40] @ 0x28 800d3c6: 0d1b lsrs r3, r3, #20 800d3c8: f003 033f and.w r3, r3, #63 @ 0x3f 800d3cc: 617b str r3, [r7, #20] pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; 800d3ce: 4b9c ldr r3, [pc, #624] @ (800d640 ) 800d3d0: 6adb ldr r3, [r3, #44] @ 0x2c 800d3d2: 0a1b lsrs r3, r3, #8 800d3d4: f003 0301 and.w r3, r3, #1 800d3d8: 613b str r3, [r7, #16] fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); 800d3da: 4b99 ldr r3, [pc, #612] @ (800d640 ) 800d3dc: 6c5b ldr r3, [r3, #68] @ 0x44 800d3de: 08db lsrs r3, r3, #3 800d3e0: f3c3 030c ubfx r3, r3, #0, #13 800d3e4: 693a ldr r2, [r7, #16] 800d3e6: fb02 f303 mul.w r3, r2, r3 800d3ea: ee07 3a90 vmov s15, r3 800d3ee: eef8 7a67 vcvt.f32.u32 s15, s15 800d3f2: edc7 7a03 vstr s15, [r7, #12] if (pll3m != 0U) 800d3f6: 697b ldr r3, [r7, #20] 800d3f8: 2b00 cmp r3, #0 800d3fa: f000 8111 beq.w 800d620 { switch (pllsource) 800d3fe: 69bb ldr r3, [r7, #24] 800d400: 2b02 cmp r3, #2 800d402: f000 8083 beq.w 800d50c 800d406: 69bb ldr r3, [r7, #24] 800d408: 2b02 cmp r3, #2 800d40a: f200 80a1 bhi.w 800d550 800d40e: 69bb ldr r3, [r7, #24] 800d410: 2b00 cmp r3, #0 800d412: d003 beq.n 800d41c 800d414: 69bb ldr r3, [r7, #24] 800d416: 2b01 cmp r3, #1 800d418: d056 beq.n 800d4c8 800d41a: e099 b.n 800d550 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800d41c: 4b88 ldr r3, [pc, #544] @ (800d640 ) 800d41e: 681b ldr r3, [r3, #0] 800d420: f003 0320 and.w r3, r3, #32 800d424: 2b00 cmp r3, #0 800d426: d02d beq.n 800d484 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800d428: 4b85 ldr r3, [pc, #532] @ (800d640 ) 800d42a: 681b ldr r3, [r3, #0] 800d42c: 08db lsrs r3, r3, #3 800d42e: f003 0303 and.w r3, r3, #3 800d432: 4a84 ldr r2, [pc, #528] @ (800d644 ) 800d434: fa22 f303 lsr.w r3, r2, r3 800d438: 60bb str r3, [r7, #8] pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800d43a: 68bb ldr r3, [r7, #8] 800d43c: ee07 3a90 vmov s15, r3 800d440: eef8 6a67 vcvt.f32.u32 s13, s15 800d444: 697b ldr r3, [r7, #20] 800d446: ee07 3a90 vmov s15, r3 800d44a: eef8 7a67 vcvt.f32.u32 s15, s15 800d44e: ee86 7aa7 vdiv.f32 s14, s13, s15 800d452: 4b7b ldr r3, [pc, #492] @ (800d640 ) 800d454: 6c1b ldr r3, [r3, #64] @ 0x40 800d456: f3c3 0308 ubfx r3, r3, #0, #9 800d45a: ee07 3a90 vmov s15, r3 800d45e: eef8 6a67 vcvt.f32.u32 s13, s15 800d462: ed97 6a03 vldr s12, [r7, #12] 800d466: eddf 5a78 vldr s11, [pc, #480] @ 800d648 800d46a: eec6 7a25 vdiv.f32 s15, s12, s11 800d46e: ee76 7aa7 vadd.f32 s15, s13, s15 800d472: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800d476: ee77 7aa6 vadd.f32 s15, s15, s13 800d47a: ee67 7a27 vmul.f32 s15, s14, s15 800d47e: edc7 7a07 vstr s15, [r7, #28] } else { pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); } break; 800d482: e087 b.n 800d594 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800d484: 697b ldr r3, [r7, #20] 800d486: ee07 3a90 vmov s15, r3 800d48a: eef8 7a67 vcvt.f32.u32 s15, s15 800d48e: eddf 6a6f vldr s13, [pc, #444] @ 800d64c 800d492: ee86 7aa7 vdiv.f32 s14, s13, s15 800d496: 4b6a ldr r3, [pc, #424] @ (800d640 ) 800d498: 6c1b ldr r3, [r3, #64] @ 0x40 800d49a: f3c3 0308 ubfx r3, r3, #0, #9 800d49e: ee07 3a90 vmov s15, r3 800d4a2: eef8 6a67 vcvt.f32.u32 s13, s15 800d4a6: ed97 6a03 vldr s12, [r7, #12] 800d4aa: eddf 5a67 vldr s11, [pc, #412] @ 800d648 800d4ae: eec6 7a25 vdiv.f32 s15, s12, s11 800d4b2: ee76 7aa7 vadd.f32 s15, s13, s15 800d4b6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800d4ba: ee77 7aa6 vadd.f32 s15, s15, s13 800d4be: ee67 7a27 vmul.f32 s15, s14, s15 800d4c2: edc7 7a07 vstr s15, [r7, #28] break; 800d4c6: e065 b.n 800d594 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800d4c8: 697b ldr r3, [r7, #20] 800d4ca: ee07 3a90 vmov s15, r3 800d4ce: eef8 7a67 vcvt.f32.u32 s15, s15 800d4d2: eddf 6a5f vldr s13, [pc, #380] @ 800d650 800d4d6: ee86 7aa7 vdiv.f32 s14, s13, s15 800d4da: 4b59 ldr r3, [pc, #356] @ (800d640 ) 800d4dc: 6c1b ldr r3, [r3, #64] @ 0x40 800d4de: f3c3 0308 ubfx r3, r3, #0, #9 800d4e2: ee07 3a90 vmov s15, r3 800d4e6: eef8 6a67 vcvt.f32.u32 s13, s15 800d4ea: ed97 6a03 vldr s12, [r7, #12] 800d4ee: eddf 5a56 vldr s11, [pc, #344] @ 800d648 800d4f2: eec6 7a25 vdiv.f32 s15, s12, s11 800d4f6: ee76 7aa7 vadd.f32 s15, s13, s15 800d4fa: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800d4fe: ee77 7aa6 vadd.f32 s15, s15, s13 800d502: ee67 7a27 vmul.f32 s15, s14, s15 800d506: edc7 7a07 vstr s15, [r7, #28] break; 800d50a: e043 b.n 800d594 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800d50c: 697b ldr r3, [r7, #20] 800d50e: ee07 3a90 vmov s15, r3 800d512: eef8 7a67 vcvt.f32.u32 s15, s15 800d516: eddf 6a4f vldr s13, [pc, #316] @ 800d654 800d51a: ee86 7aa7 vdiv.f32 s14, s13, s15 800d51e: 4b48 ldr r3, [pc, #288] @ (800d640 ) 800d520: 6c1b ldr r3, [r3, #64] @ 0x40 800d522: f3c3 0308 ubfx r3, r3, #0, #9 800d526: ee07 3a90 vmov s15, r3 800d52a: eef8 6a67 vcvt.f32.u32 s13, s15 800d52e: ed97 6a03 vldr s12, [r7, #12] 800d532: eddf 5a45 vldr s11, [pc, #276] @ 800d648 800d536: eec6 7a25 vdiv.f32 s15, s12, s11 800d53a: ee76 7aa7 vadd.f32 s15, s13, s15 800d53e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800d542: ee77 7aa6 vadd.f32 s15, s15, s13 800d546: ee67 7a27 vmul.f32 s15, s14, s15 800d54a: edc7 7a07 vstr s15, [r7, #28] break; 800d54e: e021 b.n 800d594 default: pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800d550: 697b ldr r3, [r7, #20] 800d552: ee07 3a90 vmov s15, r3 800d556: eef8 7a67 vcvt.f32.u32 s15, s15 800d55a: eddf 6a3d vldr s13, [pc, #244] @ 800d650 800d55e: ee86 7aa7 vdiv.f32 s14, s13, s15 800d562: 4b37 ldr r3, [pc, #220] @ (800d640 ) 800d564: 6c1b ldr r3, [r3, #64] @ 0x40 800d566: f3c3 0308 ubfx r3, r3, #0, #9 800d56a: ee07 3a90 vmov s15, r3 800d56e: eef8 6a67 vcvt.f32.u32 s13, s15 800d572: ed97 6a03 vldr s12, [r7, #12] 800d576: eddf 5a34 vldr s11, [pc, #208] @ 800d648 800d57a: eec6 7a25 vdiv.f32 s15, s12, s11 800d57e: ee76 7aa7 vadd.f32 s15, s13, s15 800d582: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800d586: ee77 7aa6 vadd.f32 s15, s15, s13 800d58a: ee67 7a27 vmul.f32 s15, s14, s15 800d58e: edc7 7a07 vstr s15, [r7, #28] break; 800d592: bf00 nop } PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; 800d594: 4b2a ldr r3, [pc, #168] @ (800d640 ) 800d596: 6c1b ldr r3, [r3, #64] @ 0x40 800d598: 0a5b lsrs r3, r3, #9 800d59a: f003 037f and.w r3, r3, #127 @ 0x7f 800d59e: ee07 3a90 vmov s15, r3 800d5a2: eef8 7a67 vcvt.f32.u32 s15, s15 800d5a6: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800d5aa: ee37 7a87 vadd.f32 s14, s15, s14 800d5ae: edd7 6a07 vldr s13, [r7, #28] 800d5b2: eec6 7a87 vdiv.f32 s15, s13, s14 800d5b6: eefc 7ae7 vcvt.u32.f32 s15, s15 800d5ba: ee17 2a90 vmov r2, s15 800d5be: 687b ldr r3, [r7, #4] 800d5c0: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; 800d5c2: 4b1f ldr r3, [pc, #124] @ (800d640 ) 800d5c4: 6c1b ldr r3, [r3, #64] @ 0x40 800d5c6: 0c1b lsrs r3, r3, #16 800d5c8: f003 037f and.w r3, r3, #127 @ 0x7f 800d5cc: ee07 3a90 vmov s15, r3 800d5d0: eef8 7a67 vcvt.f32.u32 s15, s15 800d5d4: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800d5d8: ee37 7a87 vadd.f32 s14, s15, s14 800d5dc: edd7 6a07 vldr s13, [r7, #28] 800d5e0: eec6 7a87 vdiv.f32 s15, s13, s14 800d5e4: eefc 7ae7 vcvt.u32.f32 s15, s15 800d5e8: ee17 2a90 vmov r2, s15 800d5ec: 687b ldr r3, [r7, #4] 800d5ee: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; 800d5f0: 4b13 ldr r3, [pc, #76] @ (800d640 ) 800d5f2: 6c1b ldr r3, [r3, #64] @ 0x40 800d5f4: 0e1b lsrs r3, r3, #24 800d5f6: f003 037f and.w r3, r3, #127 @ 0x7f 800d5fa: ee07 3a90 vmov s15, r3 800d5fe: eef8 7a67 vcvt.f32.u32 s15, s15 800d602: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800d606: ee37 7a87 vadd.f32 s14, s15, s14 800d60a: edd7 6a07 vldr s13, [r7, #28] 800d60e: eec6 7a87 vdiv.f32 s15, s13, s14 800d612: eefc 7ae7 vcvt.u32.f32 s15, s15 800d616: ee17 2a90 vmov r2, s15 800d61a: 687b ldr r3, [r7, #4] 800d61c: 609a str r2, [r3, #8] PLL3_Clocks->PLL3_P_Frequency = 0U; PLL3_Clocks->PLL3_Q_Frequency = 0U; PLL3_Clocks->PLL3_R_Frequency = 0U; } } 800d61e: e008 b.n 800d632 PLL3_Clocks->PLL3_P_Frequency = 0U; 800d620: 687b ldr r3, [r7, #4] 800d622: 2200 movs r2, #0 800d624: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = 0U; 800d626: 687b ldr r3, [r7, #4] 800d628: 2200 movs r2, #0 800d62a: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = 0U; 800d62c: 687b ldr r3, [r7, #4] 800d62e: 2200 movs r2, #0 800d630: 609a str r2, [r3, #8] } 800d632: bf00 nop 800d634: 3724 adds r7, #36 @ 0x24 800d636: 46bd mov sp, r7 800d638: f85d 7b04 ldr.w r7, [sp], #4 800d63c: 4770 bx lr 800d63e: bf00 nop 800d640: 58024400 .word 0x58024400 800d644: 03d09000 .word 0x03d09000 800d648: 46000000 .word 0x46000000 800d64c: 4c742400 .word 0x4c742400 800d650: 4a742400 .word 0x4a742400 800d654: 4bbebc20 .word 0x4bbebc20 0800d658 : * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL1_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) { 800d658: b480 push {r7} 800d65a: b089 sub sp, #36 @ 0x24 800d65c: af00 add r7, sp, #0 800d65e: 6078 str r0, [r7, #4] uint32_t pllsource, pll1m, pll1fracen, hsivalue; float_t fracn1, pll1vco; pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800d660: 4ba0 ldr r3, [pc, #640] @ (800d8e4 ) 800d662: 6a9b ldr r3, [r3, #40] @ 0x28 800d664: f003 0303 and.w r3, r3, #3 800d668: 61bb str r3, [r7, #24] pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); 800d66a: 4b9e ldr r3, [pc, #632] @ (800d8e4 ) 800d66c: 6a9b ldr r3, [r3, #40] @ 0x28 800d66e: 091b lsrs r3, r3, #4 800d670: f003 033f and.w r3, r3, #63 @ 0x3f 800d674: 617b str r3, [r7, #20] pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; 800d676: 4b9b ldr r3, [pc, #620] @ (800d8e4 ) 800d678: 6adb ldr r3, [r3, #44] @ 0x2c 800d67a: f003 0301 and.w r3, r3, #1 800d67e: 613b str r3, [r7, #16] fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800d680: 4b98 ldr r3, [pc, #608] @ (800d8e4 ) 800d682: 6b5b ldr r3, [r3, #52] @ 0x34 800d684: 08db lsrs r3, r3, #3 800d686: f3c3 030c ubfx r3, r3, #0, #13 800d68a: 693a ldr r2, [r7, #16] 800d68c: fb02 f303 mul.w r3, r2, r3 800d690: ee07 3a90 vmov s15, r3 800d694: eef8 7a67 vcvt.f32.u32 s15, s15 800d698: edc7 7a03 vstr s15, [r7, #12] if (pll1m != 0U) 800d69c: 697b ldr r3, [r7, #20] 800d69e: 2b00 cmp r3, #0 800d6a0: f000 8111 beq.w 800d8c6 { switch (pllsource) 800d6a4: 69bb ldr r3, [r7, #24] 800d6a6: 2b02 cmp r3, #2 800d6a8: f000 8083 beq.w 800d7b2 800d6ac: 69bb ldr r3, [r7, #24] 800d6ae: 2b02 cmp r3, #2 800d6b0: f200 80a1 bhi.w 800d7f6 800d6b4: 69bb ldr r3, [r7, #24] 800d6b6: 2b00 cmp r3, #0 800d6b8: d003 beq.n 800d6c2 800d6ba: 69bb ldr r3, [r7, #24] 800d6bc: 2b01 cmp r3, #1 800d6be: d056 beq.n 800d76e 800d6c0: e099 b.n 800d7f6 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800d6c2: 4b88 ldr r3, [pc, #544] @ (800d8e4 ) 800d6c4: 681b ldr r3, [r3, #0] 800d6c6: f003 0320 and.w r3, r3, #32 800d6ca: 2b00 cmp r3, #0 800d6cc: d02d beq.n 800d72a { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800d6ce: 4b85 ldr r3, [pc, #532] @ (800d8e4 ) 800d6d0: 681b ldr r3, [r3, #0] 800d6d2: 08db lsrs r3, r3, #3 800d6d4: f003 0303 and.w r3, r3, #3 800d6d8: 4a83 ldr r2, [pc, #524] @ (800d8e8 ) 800d6da: fa22 f303 lsr.w r3, r2, r3 800d6de: 60bb str r3, [r7, #8] pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800d6e0: 68bb ldr r3, [r7, #8] 800d6e2: ee07 3a90 vmov s15, r3 800d6e6: eef8 6a67 vcvt.f32.u32 s13, s15 800d6ea: 697b ldr r3, [r7, #20] 800d6ec: ee07 3a90 vmov s15, r3 800d6f0: eef8 7a67 vcvt.f32.u32 s15, s15 800d6f4: ee86 7aa7 vdiv.f32 s14, s13, s15 800d6f8: 4b7a ldr r3, [pc, #488] @ (800d8e4 ) 800d6fa: 6b1b ldr r3, [r3, #48] @ 0x30 800d6fc: f3c3 0308 ubfx r3, r3, #0, #9 800d700: ee07 3a90 vmov s15, r3 800d704: eef8 6a67 vcvt.f32.u32 s13, s15 800d708: ed97 6a03 vldr s12, [r7, #12] 800d70c: eddf 5a77 vldr s11, [pc, #476] @ 800d8ec 800d710: eec6 7a25 vdiv.f32 s15, s12, s11 800d714: ee76 7aa7 vadd.f32 s15, s13, s15 800d718: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800d71c: ee77 7aa6 vadd.f32 s15, s15, s13 800d720: ee67 7a27 vmul.f32 s15, s14, s15 800d724: edc7 7a07 vstr s15, [r7, #28] } else { pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 800d728: e087 b.n 800d83a pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800d72a: 697b ldr r3, [r7, #20] 800d72c: ee07 3a90 vmov s15, r3 800d730: eef8 7a67 vcvt.f32.u32 s15, s15 800d734: eddf 6a6e vldr s13, [pc, #440] @ 800d8f0 800d738: ee86 7aa7 vdiv.f32 s14, s13, s15 800d73c: 4b69 ldr r3, [pc, #420] @ (800d8e4 ) 800d73e: 6b1b ldr r3, [r3, #48] @ 0x30 800d740: f3c3 0308 ubfx r3, r3, #0, #9 800d744: ee07 3a90 vmov s15, r3 800d748: eef8 6a67 vcvt.f32.u32 s13, s15 800d74c: ed97 6a03 vldr s12, [r7, #12] 800d750: eddf 5a66 vldr s11, [pc, #408] @ 800d8ec 800d754: eec6 7a25 vdiv.f32 s15, s12, s11 800d758: ee76 7aa7 vadd.f32 s15, s13, s15 800d75c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800d760: ee77 7aa6 vadd.f32 s15, s15, s13 800d764: ee67 7a27 vmul.f32 s15, s14, s15 800d768: edc7 7a07 vstr s15, [r7, #28] break; 800d76c: e065 b.n 800d83a case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800d76e: 697b ldr r3, [r7, #20] 800d770: ee07 3a90 vmov s15, r3 800d774: eef8 7a67 vcvt.f32.u32 s15, s15 800d778: eddf 6a5e vldr s13, [pc, #376] @ 800d8f4 800d77c: ee86 7aa7 vdiv.f32 s14, s13, s15 800d780: 4b58 ldr r3, [pc, #352] @ (800d8e4 ) 800d782: 6b1b ldr r3, [r3, #48] @ 0x30 800d784: f3c3 0308 ubfx r3, r3, #0, #9 800d788: ee07 3a90 vmov s15, r3 800d78c: eef8 6a67 vcvt.f32.u32 s13, s15 800d790: ed97 6a03 vldr s12, [r7, #12] 800d794: eddf 5a55 vldr s11, [pc, #340] @ 800d8ec 800d798: eec6 7a25 vdiv.f32 s15, s12, s11 800d79c: ee76 7aa7 vadd.f32 s15, s13, s15 800d7a0: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800d7a4: ee77 7aa6 vadd.f32 s15, s15, s13 800d7a8: ee67 7a27 vmul.f32 s15, s14, s15 800d7ac: edc7 7a07 vstr s15, [r7, #28] break; 800d7b0: e043 b.n 800d83a case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800d7b2: 697b ldr r3, [r7, #20] 800d7b4: ee07 3a90 vmov s15, r3 800d7b8: eef8 7a67 vcvt.f32.u32 s15, s15 800d7bc: eddf 6a4e vldr s13, [pc, #312] @ 800d8f8 800d7c0: ee86 7aa7 vdiv.f32 s14, s13, s15 800d7c4: 4b47 ldr r3, [pc, #284] @ (800d8e4 ) 800d7c6: 6b1b ldr r3, [r3, #48] @ 0x30 800d7c8: f3c3 0308 ubfx r3, r3, #0, #9 800d7cc: ee07 3a90 vmov s15, r3 800d7d0: eef8 6a67 vcvt.f32.u32 s13, s15 800d7d4: ed97 6a03 vldr s12, [r7, #12] 800d7d8: eddf 5a44 vldr s11, [pc, #272] @ 800d8ec 800d7dc: eec6 7a25 vdiv.f32 s15, s12, s11 800d7e0: ee76 7aa7 vadd.f32 s15, s13, s15 800d7e4: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800d7e8: ee77 7aa6 vadd.f32 s15, s15, s13 800d7ec: ee67 7a27 vmul.f32 s15, s14, s15 800d7f0: edc7 7a07 vstr s15, [r7, #28] break; 800d7f4: e021 b.n 800d83a default: pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800d7f6: 697b ldr r3, [r7, #20] 800d7f8: ee07 3a90 vmov s15, r3 800d7fc: eef8 7a67 vcvt.f32.u32 s15, s15 800d800: eddf 6a3b vldr s13, [pc, #236] @ 800d8f0 800d804: ee86 7aa7 vdiv.f32 s14, s13, s15 800d808: 4b36 ldr r3, [pc, #216] @ (800d8e4 ) 800d80a: 6b1b ldr r3, [r3, #48] @ 0x30 800d80c: f3c3 0308 ubfx r3, r3, #0, #9 800d810: ee07 3a90 vmov s15, r3 800d814: eef8 6a67 vcvt.f32.u32 s13, s15 800d818: ed97 6a03 vldr s12, [r7, #12] 800d81c: eddf 5a33 vldr s11, [pc, #204] @ 800d8ec 800d820: eec6 7a25 vdiv.f32 s15, s12, s11 800d824: ee76 7aa7 vadd.f32 s15, s13, s15 800d828: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800d82c: ee77 7aa6 vadd.f32 s15, s15, s13 800d830: ee67 7a27 vmul.f32 s15, s14, s15 800d834: edc7 7a07 vstr s15, [r7, #28] break; 800d838: bf00 nop } PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; 800d83a: 4b2a ldr r3, [pc, #168] @ (800d8e4 ) 800d83c: 6b1b ldr r3, [r3, #48] @ 0x30 800d83e: 0a5b lsrs r3, r3, #9 800d840: f003 037f and.w r3, r3, #127 @ 0x7f 800d844: ee07 3a90 vmov s15, r3 800d848: eef8 7a67 vcvt.f32.u32 s15, s15 800d84c: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800d850: ee37 7a87 vadd.f32 s14, s15, s14 800d854: edd7 6a07 vldr s13, [r7, #28] 800d858: eec6 7a87 vdiv.f32 s15, s13, s14 800d85c: eefc 7ae7 vcvt.u32.f32 s15, s15 800d860: ee17 2a90 vmov r2, s15 800d864: 687b ldr r3, [r7, #4] 800d866: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ; 800d868: 4b1e ldr r3, [pc, #120] @ (800d8e4 ) 800d86a: 6b1b ldr r3, [r3, #48] @ 0x30 800d86c: 0c1b lsrs r3, r3, #16 800d86e: f003 037f and.w r3, r3, #127 @ 0x7f 800d872: ee07 3a90 vmov s15, r3 800d876: eef8 7a67 vcvt.f32.u32 s15, s15 800d87a: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800d87e: ee37 7a87 vadd.f32 s14, s15, s14 800d882: edd7 6a07 vldr s13, [r7, #28] 800d886: eec6 7a87 vdiv.f32 s15, s13, s14 800d88a: eefc 7ae7 vcvt.u32.f32 s15, s15 800d88e: ee17 2a90 vmov r2, s15 800d892: 687b ldr r3, [r7, #4] 800d894: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; 800d896: 4b13 ldr r3, [pc, #76] @ (800d8e4 ) 800d898: 6b1b ldr r3, [r3, #48] @ 0x30 800d89a: 0e1b lsrs r3, r3, #24 800d89c: f003 037f and.w r3, r3, #127 @ 0x7f 800d8a0: ee07 3a90 vmov s15, r3 800d8a4: eef8 7a67 vcvt.f32.u32 s15, s15 800d8a8: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800d8ac: ee37 7a87 vadd.f32 s14, s15, s14 800d8b0: edd7 6a07 vldr s13, [r7, #28] 800d8b4: eec6 7a87 vdiv.f32 s15, s13, s14 800d8b8: eefc 7ae7 vcvt.u32.f32 s15, s15 800d8bc: ee17 2a90 vmov r2, s15 800d8c0: 687b ldr r3, [r7, #4] 800d8c2: 609a str r2, [r3, #8] PLL1_Clocks->PLL1_P_Frequency = 0U; PLL1_Clocks->PLL1_Q_Frequency = 0U; PLL1_Clocks->PLL1_R_Frequency = 0U; } } 800d8c4: e008 b.n 800d8d8 PLL1_Clocks->PLL1_P_Frequency = 0U; 800d8c6: 687b ldr r3, [r7, #4] 800d8c8: 2200 movs r2, #0 800d8ca: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = 0U; 800d8cc: 687b ldr r3, [r7, #4] 800d8ce: 2200 movs r2, #0 800d8d0: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = 0U; 800d8d2: 687b ldr r3, [r7, #4] 800d8d4: 2200 movs r2, #0 800d8d6: 609a str r2, [r3, #8] } 800d8d8: bf00 nop 800d8da: 3724 adds r7, #36 @ 0x24 800d8dc: 46bd mov sp, r7 800d8de: f85d 7b04 ldr.w r7, [sp], #4 800d8e2: 4770 bx lr 800d8e4: 58024400 .word 0x58024400 800d8e8: 03d09000 .word 0x03d09000 800d8ec: 46000000 .word 0x46000000 800d8f0: 4c742400 .word 0x4c742400 800d8f4: 4a742400 .word 0x4a742400 800d8f8: 4bbebc20 .word 0x4bbebc20 0800d8fc : * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { 800d8fc: b580 push {r7, lr} 800d8fe: b084 sub sp, #16 800d900: af00 add r7, sp, #0 800d902: 6078 str r0, [r7, #4] 800d904: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800d906: 2300 movs r3, #0 800d908: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800d90a: 4b53 ldr r3, [pc, #332] @ (800da58 ) 800d90c: 6a9b ldr r3, [r3, #40] @ 0x28 800d90e: f003 0303 and.w r3, r3, #3 800d912: 2b03 cmp r3, #3 800d914: d101 bne.n 800d91a { return HAL_ERROR; 800d916: 2301 movs r3, #1 800d918: e099 b.n 800da4e else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 800d91a: 4b4f ldr r3, [pc, #316] @ (800da58 ) 800d91c: 681b ldr r3, [r3, #0] 800d91e: 4a4e ldr r2, [pc, #312] @ (800da58 ) 800d920: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800d924: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800d926: f7f7 f89d bl 8004a64 800d92a: 60b8 str r0, [r7, #8] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800d92c: e008 b.n 800d940 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800d92e: f7f7 f899 bl 8004a64 800d932: 4602 mov r2, r0 800d934: 68bb ldr r3, [r7, #8] 800d936: 1ad3 subs r3, r2, r3 800d938: 2b02 cmp r3, #2 800d93a: d901 bls.n 800d940 { return HAL_TIMEOUT; 800d93c: 2303 movs r3, #3 800d93e: e086 b.n 800da4e while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800d940: 4b45 ldr r3, [pc, #276] @ (800da58 ) 800d942: 681b ldr r3, [r3, #0] 800d944: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800d948: 2b00 cmp r3, #0 800d94a: d1f0 bne.n 800d92e } } /* Configure PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 800d94c: 4b42 ldr r3, [pc, #264] @ (800da58 ) 800d94e: 6a9b ldr r3, [r3, #40] @ 0x28 800d950: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800d954: 687b ldr r3, [r7, #4] 800d956: 681b ldr r3, [r3, #0] 800d958: 031b lsls r3, r3, #12 800d95a: 493f ldr r1, [pc, #252] @ (800da58 ) 800d95c: 4313 orrs r3, r2 800d95e: 628b str r3, [r1, #40] @ 0x28 800d960: 687b ldr r3, [r7, #4] 800d962: 685b ldr r3, [r3, #4] 800d964: 3b01 subs r3, #1 800d966: f3c3 0208 ubfx r2, r3, #0, #9 800d96a: 687b ldr r3, [r7, #4] 800d96c: 689b ldr r3, [r3, #8] 800d96e: 3b01 subs r3, #1 800d970: 025b lsls r3, r3, #9 800d972: b29b uxth r3, r3 800d974: 431a orrs r2, r3 800d976: 687b ldr r3, [r7, #4] 800d978: 68db ldr r3, [r3, #12] 800d97a: 3b01 subs r3, #1 800d97c: 041b lsls r3, r3, #16 800d97e: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800d982: 431a orrs r2, r3 800d984: 687b ldr r3, [r7, #4] 800d986: 691b ldr r3, [r3, #16] 800d988: 3b01 subs r3, #1 800d98a: 061b lsls r3, r3, #24 800d98c: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800d990: 4931 ldr r1, [pc, #196] @ (800da58 ) 800d992: 4313 orrs r3, r2 800d994: 638b str r3, [r1, #56] @ 0x38 pll2->PLL2P, pll2->PLL2Q, pll2->PLL2R); /* Select PLL2 input reference frequency range: VCI */ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 800d996: 4b30 ldr r3, [pc, #192] @ (800da58 ) 800d998: 6adb ldr r3, [r3, #44] @ 0x2c 800d99a: f023 02c0 bic.w r2, r3, #192 @ 0xc0 800d99e: 687b ldr r3, [r7, #4] 800d9a0: 695b ldr r3, [r3, #20] 800d9a2: 492d ldr r1, [pc, #180] @ (800da58 ) 800d9a4: 4313 orrs r3, r2 800d9a6: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL2 output frequency range : VCO */ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 800d9a8: 4b2b ldr r3, [pc, #172] @ (800da58 ) 800d9aa: 6adb ldr r3, [r3, #44] @ 0x2c 800d9ac: f023 0220 bic.w r2, r3, #32 800d9b0: 687b ldr r3, [r7, #4] 800d9b2: 699b ldr r3, [r3, #24] 800d9b4: 4928 ldr r1, [pc, #160] @ (800da58 ) 800d9b6: 4313 orrs r3, r2 800d9b8: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_DISABLE(); 800d9ba: 4b27 ldr r3, [pc, #156] @ (800da58 ) 800d9bc: 6adb ldr r3, [r3, #44] @ 0x2c 800d9be: 4a26 ldr r2, [pc, #152] @ (800da58 ) 800d9c0: f023 0310 bic.w r3, r3, #16 800d9c4: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 800d9c6: 4b24 ldr r3, [pc, #144] @ (800da58 ) 800d9c8: 6bda ldr r2, [r3, #60] @ 0x3c 800d9ca: 4b24 ldr r3, [pc, #144] @ (800da5c ) 800d9cc: 4013 ands r3, r2 800d9ce: 687a ldr r2, [r7, #4] 800d9d0: 69d2 ldr r2, [r2, #28] 800d9d2: 00d2 lsls r2, r2, #3 800d9d4: 4920 ldr r1, [pc, #128] @ (800da58 ) 800d9d6: 4313 orrs r3, r2 800d9d8: 63cb str r3, [r1, #60] @ 0x3c /* Enable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_ENABLE(); 800d9da: 4b1f ldr r3, [pc, #124] @ (800da58 ) 800d9dc: 6adb ldr r3, [r3, #44] @ 0x2c 800d9de: 4a1e ldr r2, [pc, #120] @ (800da58 ) 800d9e0: f043 0310 orr.w r3, r3, #16 800d9e4: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL2 clock output */ if (Divider == DIVIDER_P_UPDATE) 800d9e6: 683b ldr r3, [r7, #0] 800d9e8: 2b00 cmp r3, #0 800d9ea: d106 bne.n 800d9fa { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 800d9ec: 4b1a ldr r3, [pc, #104] @ (800da58 ) 800d9ee: 6adb ldr r3, [r3, #44] @ 0x2c 800d9f0: 4a19 ldr r2, [pc, #100] @ (800da58 ) 800d9f2: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800d9f6: 62d3 str r3, [r2, #44] @ 0x2c 800d9f8: e00f b.n 800da1a } else if (Divider == DIVIDER_Q_UPDATE) 800d9fa: 683b ldr r3, [r7, #0] 800d9fc: 2b01 cmp r3, #1 800d9fe: d106 bne.n 800da0e { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 800da00: 4b15 ldr r3, [pc, #84] @ (800da58 ) 800da02: 6adb ldr r3, [r3, #44] @ 0x2c 800da04: 4a14 ldr r2, [pc, #80] @ (800da58 ) 800da06: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800da0a: 62d3 str r3, [r2, #44] @ 0x2c 800da0c: e005 b.n 800da1a } else { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 800da0e: 4b12 ldr r3, [pc, #72] @ (800da58 ) 800da10: 6adb ldr r3, [r3, #44] @ 0x2c 800da12: 4a11 ldr r2, [pc, #68] @ (800da58 ) 800da14: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 800da18: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL2. */ __HAL_RCC_PLL2_ENABLE(); 800da1a: 4b0f ldr r3, [pc, #60] @ (800da58 ) 800da1c: 681b ldr r3, [r3, #0] 800da1e: 4a0e ldr r2, [pc, #56] @ (800da58 ) 800da20: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 800da24: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800da26: f7f7 f81d bl 8004a64 800da2a: 60b8 str r0, [r7, #8] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800da2c: e008 b.n 800da40 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800da2e: f7f7 f819 bl 8004a64 800da32: 4602 mov r2, r0 800da34: 68bb ldr r3, [r7, #8] 800da36: 1ad3 subs r3, r2, r3 800da38: 2b02 cmp r3, #2 800da3a: d901 bls.n 800da40 { return HAL_TIMEOUT; 800da3c: 2303 movs r3, #3 800da3e: e006 b.n 800da4e while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800da40: 4b05 ldr r3, [pc, #20] @ (800da58 ) 800da42: 681b ldr r3, [r3, #0] 800da44: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800da48: 2b00 cmp r3, #0 800da4a: d0f0 beq.n 800da2e } } return status; 800da4c: 7bfb ldrb r3, [r7, #15] } 800da4e: 4618 mov r0, r3 800da50: 3710 adds r7, #16 800da52: 46bd mov sp, r7 800da54: bd80 pop {r7, pc} 800da56: bf00 nop 800da58: 58024400 .word 0x58024400 800da5c: ffff0007 .word 0xffff0007 0800da60 : * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { 800da60: b580 push {r7, lr} 800da62: b084 sub sp, #16 800da64: af00 add r7, sp, #0 800da66: 6078 str r0, [r7, #4] 800da68: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800da6a: 2300 movs r3, #0 800da6c: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800da6e: 4b53 ldr r3, [pc, #332] @ (800dbbc ) 800da70: 6a9b ldr r3, [r3, #40] @ 0x28 800da72: f003 0303 and.w r3, r3, #3 800da76: 2b03 cmp r3, #3 800da78: d101 bne.n 800da7e { return HAL_ERROR; 800da7a: 2301 movs r3, #1 800da7c: e099 b.n 800dbb2 else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 800da7e: 4b4f ldr r3, [pc, #316] @ (800dbbc ) 800da80: 681b ldr r3, [r3, #0] 800da82: 4a4e ldr r2, [pc, #312] @ (800dbbc ) 800da84: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800da88: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800da8a: f7f6 ffeb bl 8004a64 800da8e: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800da90: e008 b.n 800daa4 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800da92: f7f6 ffe7 bl 8004a64 800da96: 4602 mov r2, r0 800da98: 68bb ldr r3, [r7, #8] 800da9a: 1ad3 subs r3, r2, r3 800da9c: 2b02 cmp r3, #2 800da9e: d901 bls.n 800daa4 { return HAL_TIMEOUT; 800daa0: 2303 movs r3, #3 800daa2: e086 b.n 800dbb2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800daa4: 4b45 ldr r3, [pc, #276] @ (800dbbc ) 800daa6: 681b ldr r3, [r3, #0] 800daa8: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800daac: 2b00 cmp r3, #0 800daae: d1f0 bne.n 800da92 } } /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 800dab0: 4b42 ldr r3, [pc, #264] @ (800dbbc ) 800dab2: 6a9b ldr r3, [r3, #40] @ 0x28 800dab4: f023 727c bic.w r2, r3, #66060288 @ 0x3f00000 800dab8: 687b ldr r3, [r7, #4] 800daba: 681b ldr r3, [r3, #0] 800dabc: 051b lsls r3, r3, #20 800dabe: 493f ldr r1, [pc, #252] @ (800dbbc ) 800dac0: 4313 orrs r3, r2 800dac2: 628b str r3, [r1, #40] @ 0x28 800dac4: 687b ldr r3, [r7, #4] 800dac6: 685b ldr r3, [r3, #4] 800dac8: 3b01 subs r3, #1 800daca: f3c3 0208 ubfx r2, r3, #0, #9 800dace: 687b ldr r3, [r7, #4] 800dad0: 689b ldr r3, [r3, #8] 800dad2: 3b01 subs r3, #1 800dad4: 025b lsls r3, r3, #9 800dad6: b29b uxth r3, r3 800dad8: 431a orrs r2, r3 800dada: 687b ldr r3, [r7, #4] 800dadc: 68db ldr r3, [r3, #12] 800dade: 3b01 subs r3, #1 800dae0: 041b lsls r3, r3, #16 800dae2: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800dae6: 431a orrs r2, r3 800dae8: 687b ldr r3, [r7, #4] 800daea: 691b ldr r3, [r3, #16] 800daec: 3b01 subs r3, #1 800daee: 061b lsls r3, r3, #24 800daf0: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800daf4: 4931 ldr r1, [pc, #196] @ (800dbbc ) 800daf6: 4313 orrs r3, r2 800daf8: 640b str r3, [r1, #64] @ 0x40 pll3->PLL3P, pll3->PLL3Q, pll3->PLL3R); /* Select PLL3 input reference frequency range: VCI */ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 800dafa: 4b30 ldr r3, [pc, #192] @ (800dbbc ) 800dafc: 6adb ldr r3, [r3, #44] @ 0x2c 800dafe: f423 6240 bic.w r2, r3, #3072 @ 0xc00 800db02: 687b ldr r3, [r7, #4] 800db04: 695b ldr r3, [r3, #20] 800db06: 492d ldr r1, [pc, #180] @ (800dbbc ) 800db08: 4313 orrs r3, r2 800db0a: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL3 output frequency range : VCO */ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 800db0c: 4b2b ldr r3, [pc, #172] @ (800dbbc ) 800db0e: 6adb ldr r3, [r3, #44] @ 0x2c 800db10: f423 7200 bic.w r2, r3, #512 @ 0x200 800db14: 687b ldr r3, [r7, #4] 800db16: 699b ldr r3, [r3, #24] 800db18: 4928 ldr r1, [pc, #160] @ (800dbbc ) 800db1a: 4313 orrs r3, r2 800db1c: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_DISABLE(); 800db1e: 4b27 ldr r3, [pc, #156] @ (800dbbc ) 800db20: 6adb ldr r3, [r3, #44] @ 0x2c 800db22: 4a26 ldr r2, [pc, #152] @ (800dbbc ) 800db24: f423 7380 bic.w r3, r3, #256 @ 0x100 800db28: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 800db2a: 4b24 ldr r3, [pc, #144] @ (800dbbc ) 800db2c: 6c5a ldr r2, [r3, #68] @ 0x44 800db2e: 4b24 ldr r3, [pc, #144] @ (800dbc0 ) 800db30: 4013 ands r3, r2 800db32: 687a ldr r2, [r7, #4] 800db34: 69d2 ldr r2, [r2, #28] 800db36: 00d2 lsls r2, r2, #3 800db38: 4920 ldr r1, [pc, #128] @ (800dbbc ) 800db3a: 4313 orrs r3, r2 800db3c: 644b str r3, [r1, #68] @ 0x44 /* Enable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_ENABLE(); 800db3e: 4b1f ldr r3, [pc, #124] @ (800dbbc ) 800db40: 6adb ldr r3, [r3, #44] @ 0x2c 800db42: 4a1e ldr r2, [pc, #120] @ (800dbbc ) 800db44: f443 7380 orr.w r3, r3, #256 @ 0x100 800db48: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL3 clock output */ if (Divider == DIVIDER_P_UPDATE) 800db4a: 683b ldr r3, [r7, #0] 800db4c: 2b00 cmp r3, #0 800db4e: d106 bne.n 800db5e { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 800db50: 4b1a ldr r3, [pc, #104] @ (800dbbc ) 800db52: 6adb ldr r3, [r3, #44] @ 0x2c 800db54: 4a19 ldr r2, [pc, #100] @ (800dbbc ) 800db56: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 800db5a: 62d3 str r3, [r2, #44] @ 0x2c 800db5c: e00f b.n 800db7e } else if (Divider == DIVIDER_Q_UPDATE) 800db5e: 683b ldr r3, [r7, #0] 800db60: 2b01 cmp r3, #1 800db62: d106 bne.n 800db72 { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 800db64: 4b15 ldr r3, [pc, #84] @ (800dbbc ) 800db66: 6adb ldr r3, [r3, #44] @ 0x2c 800db68: 4a14 ldr r2, [pc, #80] @ (800dbbc ) 800db6a: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 800db6e: 62d3 str r3, [r2, #44] @ 0x2c 800db70: e005 b.n 800db7e } else { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 800db72: 4b12 ldr r3, [pc, #72] @ (800dbbc ) 800db74: 6adb ldr r3, [r3, #44] @ 0x2c 800db76: 4a11 ldr r2, [pc, #68] @ (800dbbc ) 800db78: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800db7c: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL3. */ __HAL_RCC_PLL3_ENABLE(); 800db7e: 4b0f ldr r3, [pc, #60] @ (800dbbc ) 800db80: 681b ldr r3, [r3, #0] 800db82: 4a0e ldr r2, [pc, #56] @ (800dbbc ) 800db84: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800db88: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800db8a: f7f6 ff6b bl 8004a64 800db8e: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800db90: e008 b.n 800dba4 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800db92: f7f6 ff67 bl 8004a64 800db96: 4602 mov r2, r0 800db98: 68bb ldr r3, [r7, #8] 800db9a: 1ad3 subs r3, r2, r3 800db9c: 2b02 cmp r3, #2 800db9e: d901 bls.n 800dba4 { return HAL_TIMEOUT; 800dba0: 2303 movs r3, #3 800dba2: e006 b.n 800dbb2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800dba4: 4b05 ldr r3, [pc, #20] @ (800dbbc ) 800dba6: 681b ldr r3, [r3, #0] 800dba8: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800dbac: 2b00 cmp r3, #0 800dbae: d0f0 beq.n 800db92 } } return status; 800dbb0: 7bfb ldrb r3, [r7, #15] } 800dbb2: 4618 mov r0, r3 800dbb4: 3710 adds r7, #16 800dbb6: 46bd mov sp, r7 800dbb8: bd80 pop {r7, pc} 800dbba: bf00 nop 800dbbc: 58024400 .word 0x58024400 800dbc0: ffff0007 .word 0xffff0007 0800dbc4 : * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL status */ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { 800dbc4: b580 push {r7, lr} 800dbc6: b084 sub sp, #16 800dbc8: af00 add r7, sp, #0 800dbca: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the RNG handle allocation */ if (hrng == NULL) 800dbcc: 687b ldr r3, [r7, #4] 800dbce: 2b00 cmp r3, #0 800dbd0: d101 bne.n 800dbd6 { return HAL_ERROR; 800dbd2: 2301 movs r3, #1 800dbd4: e054 b.n 800dc80 /* Init the low level hardware */ hrng->MspInitCallback(hrng); } #else if (hrng->State == HAL_RNG_STATE_RESET) 800dbd6: 687b ldr r3, [r7, #4] 800dbd8: 7a5b ldrb r3, [r3, #9] 800dbda: b2db uxtb r3, r3 800dbdc: 2b00 cmp r3, #0 800dbde: d105 bne.n 800dbec { /* Allocate lock resource and initialize it */ hrng->Lock = HAL_UNLOCKED; 800dbe0: 687b ldr r3, [r7, #4] 800dbe2: 2200 movs r2, #0 800dbe4: 721a strb r2, [r3, #8] /* Init the low level hardware */ HAL_RNG_MspInit(hrng); 800dbe6: 6878 ldr r0, [r7, #4] 800dbe8: f7f5 fbb2 bl 8003350 } #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; 800dbec: 687b ldr r3, [r7, #4] 800dbee: 2202 movs r2, #2 800dbf0: 725a strb r2, [r3, #9] } } } #else /* Clock Error Detection Configuration */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection); 800dbf2: 687b ldr r3, [r7, #4] 800dbf4: 681b ldr r3, [r3, #0] 800dbf6: 681b ldr r3, [r3, #0] 800dbf8: f023 0120 bic.w r1, r3, #32 800dbfc: 687b ldr r3, [r7, #4] 800dbfe: 685a ldr r2, [r3, #4] 800dc00: 687b ldr r3, [r7, #4] 800dc02: 681b ldr r3, [r3, #0] 800dc04: 430a orrs r2, r1 800dc06: 601a str r2, [r3, #0] #endif /* RNG_CR_CONDRST */ /* Enable the RNG Peripheral */ __HAL_RNG_ENABLE(hrng); 800dc08: 687b ldr r3, [r7, #4] 800dc0a: 681b ldr r3, [r3, #0] 800dc0c: 681a ldr r2, [r3, #0] 800dc0e: 687b ldr r3, [r7, #4] 800dc10: 681b ldr r3, [r3, #0] 800dc12: f042 0204 orr.w r2, r2, #4 800dc16: 601a str r2, [r3, #0] /* verify that no seed error */ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) 800dc18: 687b ldr r3, [r7, #4] 800dc1a: 681b ldr r3, [r3, #0] 800dc1c: 685b ldr r3, [r3, #4] 800dc1e: f003 0340 and.w r3, r3, #64 @ 0x40 800dc22: 2b40 cmp r3, #64 @ 0x40 800dc24: d104 bne.n 800dc30 { hrng->State = HAL_RNG_STATE_ERROR; 800dc26: 687b ldr r3, [r7, #4] 800dc28: 2204 movs r2, #4 800dc2a: 725a strb r2, [r3, #9] return HAL_ERROR; 800dc2c: 2301 movs r3, #1 800dc2e: e027 b.n 800dc80 } /* Get tick */ tickstart = HAL_GetTick(); 800dc30: f7f6 ff18 bl 8004a64 800dc34: 60f8 str r0, [r7, #12] /* Check if data register contains valid random data */ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800dc36: e015 b.n 800dc64 { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) 800dc38: f7f6 ff14 bl 8004a64 800dc3c: 4602 mov r2, r0 800dc3e: 68fb ldr r3, [r7, #12] 800dc40: 1ad3 subs r3, r2, r3 800dc42: 2b02 cmp r3, #2 800dc44: d90e bls.n 800dc64 { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800dc46: 687b ldr r3, [r7, #4] 800dc48: 681b ldr r3, [r3, #0] 800dc4a: 685b ldr r3, [r3, #4] 800dc4c: f003 0304 and.w r3, r3, #4 800dc50: 2b04 cmp r3, #4 800dc52: d107 bne.n 800dc64 { hrng->State = HAL_RNG_STATE_ERROR; 800dc54: 687b ldr r3, [r7, #4] 800dc56: 2204 movs r2, #4 800dc58: 725a strb r2, [r3, #9] hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; 800dc5a: 687b ldr r3, [r7, #4] 800dc5c: 2202 movs r2, #2 800dc5e: 60da str r2, [r3, #12] return HAL_ERROR; 800dc60: 2301 movs r3, #1 800dc62: e00d b.n 800dc80 while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800dc64: 687b ldr r3, [r7, #4] 800dc66: 681b ldr r3, [r3, #0] 800dc68: 685b ldr r3, [r3, #4] 800dc6a: f003 0304 and.w r3, r3, #4 800dc6e: 2b04 cmp r3, #4 800dc70: d0e2 beq.n 800dc38 } } } /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; 800dc72: 687b ldr r3, [r7, #4] 800dc74: 2201 movs r2, #1 800dc76: 725a strb r2, [r3, #9] /* Initialise the error code */ hrng->ErrorCode = HAL_RNG_ERROR_NONE; 800dc78: 687b ldr r3, [r7, #4] 800dc7a: 2200 movs r2, #0 800dc7c: 60da str r2, [r3, #12] /* Return function status */ return HAL_OK; 800dc7e: 2300 movs r3, #0 } 800dc80: 4618 mov r0, r3 800dc82: 3710 adds r7, #16 800dc84: 46bd mov sp, r7 800dc86: bd80 pop {r7, pc} 0800dc88 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 800dc88: b580 push {r7, lr} 800dc8a: b082 sub sp, #8 800dc8c: af00 add r7, sp, #0 800dc8e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800dc90: 687b ldr r3, [r7, #4] 800dc92: 2b00 cmp r3, #0 800dc94: d101 bne.n 800dc9a { return HAL_ERROR; 800dc96: 2301 movs r3, #1 800dc98: e049 b.n 800dd2e assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800dc9a: 687b ldr r3, [r7, #4] 800dc9c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800dca0: b2db uxtb r3, r3 800dca2: 2b00 cmp r3, #0 800dca4: d106 bne.n 800dcb4 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800dca6: 687b ldr r3, [r7, #4] 800dca8: 2200 movs r2, #0 800dcaa: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800dcae: 6878 ldr r0, [r7, #4] 800dcb0: f7f5 fbc2 bl 8003438 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800dcb4: 687b ldr r3, [r7, #4] 800dcb6: 2202 movs r2, #2 800dcb8: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800dcbc: 687b ldr r3, [r7, #4] 800dcbe: 681a ldr r2, [r3, #0] 800dcc0: 687b ldr r3, [r7, #4] 800dcc2: 3304 adds r3, #4 800dcc4: 4619 mov r1, r3 800dcc6: 4610 mov r0, r2 800dcc8: f000 fe90 bl 800e9ec /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800dccc: 687b ldr r3, [r7, #4] 800dcce: 2201 movs r2, #1 800dcd0: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800dcd4: 687b ldr r3, [r7, #4] 800dcd6: 2201 movs r2, #1 800dcd8: f883 203e strb.w r2, [r3, #62] @ 0x3e 800dcdc: 687b ldr r3, [r7, #4] 800dcde: 2201 movs r2, #1 800dce0: f883 203f strb.w r2, [r3, #63] @ 0x3f 800dce4: 687b ldr r3, [r7, #4] 800dce6: 2201 movs r2, #1 800dce8: f883 2040 strb.w r2, [r3, #64] @ 0x40 800dcec: 687b ldr r3, [r7, #4] 800dcee: 2201 movs r2, #1 800dcf0: f883 2041 strb.w r2, [r3, #65] @ 0x41 800dcf4: 687b ldr r3, [r7, #4] 800dcf6: 2201 movs r2, #1 800dcf8: f883 2042 strb.w r2, [r3, #66] @ 0x42 800dcfc: 687b ldr r3, [r7, #4] 800dcfe: 2201 movs r2, #1 800dd00: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800dd04: 687b ldr r3, [r7, #4] 800dd06: 2201 movs r2, #1 800dd08: f883 2044 strb.w r2, [r3, #68] @ 0x44 800dd0c: 687b ldr r3, [r7, #4] 800dd0e: 2201 movs r2, #1 800dd10: f883 2045 strb.w r2, [r3, #69] @ 0x45 800dd14: 687b ldr r3, [r7, #4] 800dd16: 2201 movs r2, #1 800dd18: f883 2046 strb.w r2, [r3, #70] @ 0x46 800dd1c: 687b ldr r3, [r7, #4] 800dd1e: 2201 movs r2, #1 800dd20: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800dd24: 687b ldr r3, [r7, #4] 800dd26: 2201 movs r2, #1 800dd28: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800dd2c: 2300 movs r3, #0 } 800dd2e: 4618 mov r0, r3 800dd30: 3708 adds r7, #8 800dd32: 46bd mov sp, r7 800dd34: bd80 pop {r7, pc} ... 0800dd38 : * @brief Starts the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { 800dd38: b480 push {r7} 800dd3a: b085 sub sp, #20 800dd3c: af00 add r7, sp, #0 800dd3e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800dd40: 687b ldr r3, [r7, #4] 800dd42: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800dd46: b2db uxtb r3, r3 800dd48: 2b01 cmp r3, #1 800dd4a: d001 beq.n 800dd50 { return HAL_ERROR; 800dd4c: 2301 movs r3, #1 800dd4e: e04c b.n 800ddea } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800dd50: 687b ldr r3, [r7, #4] 800dd52: 2202 movs r2, #2 800dd54: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800dd58: 687b ldr r3, [r7, #4] 800dd5a: 681b ldr r3, [r3, #0] 800dd5c: 4a26 ldr r2, [pc, #152] @ (800ddf8 ) 800dd5e: 4293 cmp r3, r2 800dd60: d022 beq.n 800dda8 800dd62: 687b ldr r3, [r7, #4] 800dd64: 681b ldr r3, [r3, #0] 800dd66: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800dd6a: d01d beq.n 800dda8 800dd6c: 687b ldr r3, [r7, #4] 800dd6e: 681b ldr r3, [r3, #0] 800dd70: 4a22 ldr r2, [pc, #136] @ (800ddfc ) 800dd72: 4293 cmp r3, r2 800dd74: d018 beq.n 800dda8 800dd76: 687b ldr r3, [r7, #4] 800dd78: 681b ldr r3, [r3, #0] 800dd7a: 4a21 ldr r2, [pc, #132] @ (800de00 ) 800dd7c: 4293 cmp r3, r2 800dd7e: d013 beq.n 800dda8 800dd80: 687b ldr r3, [r7, #4] 800dd82: 681b ldr r3, [r3, #0] 800dd84: 4a1f ldr r2, [pc, #124] @ (800de04 ) 800dd86: 4293 cmp r3, r2 800dd88: d00e beq.n 800dda8 800dd8a: 687b ldr r3, [r7, #4] 800dd8c: 681b ldr r3, [r3, #0] 800dd8e: 4a1e ldr r2, [pc, #120] @ (800de08 ) 800dd90: 4293 cmp r3, r2 800dd92: d009 beq.n 800dda8 800dd94: 687b ldr r3, [r7, #4] 800dd96: 681b ldr r3, [r3, #0] 800dd98: 4a1c ldr r2, [pc, #112] @ (800de0c ) 800dd9a: 4293 cmp r3, r2 800dd9c: d004 beq.n 800dda8 800dd9e: 687b ldr r3, [r7, #4] 800dda0: 681b ldr r3, [r3, #0] 800dda2: 4a1b ldr r2, [pc, #108] @ (800de10 ) 800dda4: 4293 cmp r3, r2 800dda6: d115 bne.n 800ddd4 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800dda8: 687b ldr r3, [r7, #4] 800ddaa: 681b ldr r3, [r3, #0] 800ddac: 689a ldr r2, [r3, #8] 800ddae: 4b19 ldr r3, [pc, #100] @ (800de14 ) 800ddb0: 4013 ands r3, r2 800ddb2: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800ddb4: 68fb ldr r3, [r7, #12] 800ddb6: 2b06 cmp r3, #6 800ddb8: d015 beq.n 800dde6 800ddba: 68fb ldr r3, [r7, #12] 800ddbc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800ddc0: d011 beq.n 800dde6 { __HAL_TIM_ENABLE(htim); 800ddc2: 687b ldr r3, [r7, #4] 800ddc4: 681b ldr r3, [r3, #0] 800ddc6: 681a ldr r2, [r3, #0] 800ddc8: 687b ldr r3, [r7, #4] 800ddca: 681b ldr r3, [r3, #0] 800ddcc: f042 0201 orr.w r2, r2, #1 800ddd0: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800ddd2: e008 b.n 800dde6 } } else { __HAL_TIM_ENABLE(htim); 800ddd4: 687b ldr r3, [r7, #4] 800ddd6: 681b ldr r3, [r3, #0] 800ddd8: 681a ldr r2, [r3, #0] 800ddda: 687b ldr r3, [r7, #4] 800dddc: 681b ldr r3, [r3, #0] 800ddde: f042 0201 orr.w r2, r2, #1 800dde2: 601a str r2, [r3, #0] 800dde4: e000 b.n 800dde8 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800dde6: bf00 nop } /* Return function status */ return HAL_OK; 800dde8: 2300 movs r3, #0 } 800ddea: 4618 mov r0, r3 800ddec: 3714 adds r7, #20 800ddee: 46bd mov sp, r7 800ddf0: f85d 7b04 ldr.w r7, [sp], #4 800ddf4: 4770 bx lr 800ddf6: bf00 nop 800ddf8: 40010000 .word 0x40010000 800ddfc: 40000400 .word 0x40000400 800de00: 40000800 .word 0x40000800 800de04: 40000c00 .word 0x40000c00 800de08: 40010400 .word 0x40010400 800de0c: 40001800 .word 0x40001800 800de10: 40014000 .word 0x40014000 800de14: 00010007 .word 0x00010007 0800de18 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 800de18: b480 push {r7} 800de1a: b085 sub sp, #20 800de1c: af00 add r7, sp, #0 800de1e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800de20: 687b ldr r3, [r7, #4] 800de22: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800de26: b2db uxtb r3, r3 800de28: 2b01 cmp r3, #1 800de2a: d001 beq.n 800de30 { return HAL_ERROR; 800de2c: 2301 movs r3, #1 800de2e: e054 b.n 800deda } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800de30: 687b ldr r3, [r7, #4] 800de32: 2202 movs r2, #2 800de34: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 800de38: 687b ldr r3, [r7, #4] 800de3a: 681b ldr r3, [r3, #0] 800de3c: 68da ldr r2, [r3, #12] 800de3e: 687b ldr r3, [r7, #4] 800de40: 681b ldr r3, [r3, #0] 800de42: f042 0201 orr.w r2, r2, #1 800de46: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800de48: 687b ldr r3, [r7, #4] 800de4a: 681b ldr r3, [r3, #0] 800de4c: 4a26 ldr r2, [pc, #152] @ (800dee8 ) 800de4e: 4293 cmp r3, r2 800de50: d022 beq.n 800de98 800de52: 687b ldr r3, [r7, #4] 800de54: 681b ldr r3, [r3, #0] 800de56: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800de5a: d01d beq.n 800de98 800de5c: 687b ldr r3, [r7, #4] 800de5e: 681b ldr r3, [r3, #0] 800de60: 4a22 ldr r2, [pc, #136] @ (800deec ) 800de62: 4293 cmp r3, r2 800de64: d018 beq.n 800de98 800de66: 687b ldr r3, [r7, #4] 800de68: 681b ldr r3, [r3, #0] 800de6a: 4a21 ldr r2, [pc, #132] @ (800def0 ) 800de6c: 4293 cmp r3, r2 800de6e: d013 beq.n 800de98 800de70: 687b ldr r3, [r7, #4] 800de72: 681b ldr r3, [r3, #0] 800de74: 4a1f ldr r2, [pc, #124] @ (800def4 ) 800de76: 4293 cmp r3, r2 800de78: d00e beq.n 800de98 800de7a: 687b ldr r3, [r7, #4] 800de7c: 681b ldr r3, [r3, #0] 800de7e: 4a1e ldr r2, [pc, #120] @ (800def8 ) 800de80: 4293 cmp r3, r2 800de82: d009 beq.n 800de98 800de84: 687b ldr r3, [r7, #4] 800de86: 681b ldr r3, [r3, #0] 800de88: 4a1c ldr r2, [pc, #112] @ (800defc ) 800de8a: 4293 cmp r3, r2 800de8c: d004 beq.n 800de98 800de8e: 687b ldr r3, [r7, #4] 800de90: 681b ldr r3, [r3, #0] 800de92: 4a1b ldr r2, [pc, #108] @ (800df00 ) 800de94: 4293 cmp r3, r2 800de96: d115 bne.n 800dec4 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800de98: 687b ldr r3, [r7, #4] 800de9a: 681b ldr r3, [r3, #0] 800de9c: 689a ldr r2, [r3, #8] 800de9e: 4b19 ldr r3, [pc, #100] @ (800df04 ) 800dea0: 4013 ands r3, r2 800dea2: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800dea4: 68fb ldr r3, [r7, #12] 800dea6: 2b06 cmp r3, #6 800dea8: d015 beq.n 800ded6 800deaa: 68fb ldr r3, [r7, #12] 800deac: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800deb0: d011 beq.n 800ded6 { __HAL_TIM_ENABLE(htim); 800deb2: 687b ldr r3, [r7, #4] 800deb4: 681b ldr r3, [r3, #0] 800deb6: 681a ldr r2, [r3, #0] 800deb8: 687b ldr r3, [r7, #4] 800deba: 681b ldr r3, [r3, #0] 800debc: f042 0201 orr.w r2, r2, #1 800dec0: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800dec2: e008 b.n 800ded6 } } else { __HAL_TIM_ENABLE(htim); 800dec4: 687b ldr r3, [r7, #4] 800dec6: 681b ldr r3, [r3, #0] 800dec8: 681a ldr r2, [r3, #0] 800deca: 687b ldr r3, [r7, #4] 800decc: 681b ldr r3, [r3, #0] 800dece: f042 0201 orr.w r2, r2, #1 800ded2: 601a str r2, [r3, #0] 800ded4: e000 b.n 800ded8 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800ded6: bf00 nop } /* Return function status */ return HAL_OK; 800ded8: 2300 movs r3, #0 } 800deda: 4618 mov r0, r3 800dedc: 3714 adds r7, #20 800dede: 46bd mov sp, r7 800dee0: f85d 7b04 ldr.w r7, [sp], #4 800dee4: 4770 bx lr 800dee6: bf00 nop 800dee8: 40010000 .word 0x40010000 800deec: 40000400 .word 0x40000400 800def0: 40000800 .word 0x40000800 800def4: 40000c00 .word 0x40000c00 800def8: 40010400 .word 0x40010400 800defc: 40001800 .word 0x40001800 800df00: 40014000 .word 0x40014000 800df04: 00010007 .word 0x00010007 0800df08 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 800df08: b580 push {r7, lr} 800df0a: b082 sub sp, #8 800df0c: af00 add r7, sp, #0 800df0e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800df10: 687b ldr r3, [r7, #4] 800df12: 2b00 cmp r3, #0 800df14: d101 bne.n 800df1a { return HAL_ERROR; 800df16: 2301 movs r3, #1 800df18: e049 b.n 800dfae assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800df1a: 687b ldr r3, [r7, #4] 800df1c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800df20: b2db uxtb r3, r3 800df22: 2b00 cmp r3, #0 800df24: d106 bne.n 800df34 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800df26: 687b ldr r3, [r7, #4] 800df28: 2200 movs r2, #0 800df2a: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 800df2e: 6878 ldr r0, [r7, #4] 800df30: f7f5 fa48 bl 80033c4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800df34: 687b ldr r3, [r7, #4] 800df36: 2202 movs r2, #2 800df38: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800df3c: 687b ldr r3, [r7, #4] 800df3e: 681a ldr r2, [r3, #0] 800df40: 687b ldr r3, [r7, #4] 800df42: 3304 adds r3, #4 800df44: 4619 mov r1, r3 800df46: 4610 mov r0, r2 800df48: f000 fd50 bl 800e9ec /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800df4c: 687b ldr r3, [r7, #4] 800df4e: 2201 movs r2, #1 800df50: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800df54: 687b ldr r3, [r7, #4] 800df56: 2201 movs r2, #1 800df58: f883 203e strb.w r2, [r3, #62] @ 0x3e 800df5c: 687b ldr r3, [r7, #4] 800df5e: 2201 movs r2, #1 800df60: f883 203f strb.w r2, [r3, #63] @ 0x3f 800df64: 687b ldr r3, [r7, #4] 800df66: 2201 movs r2, #1 800df68: f883 2040 strb.w r2, [r3, #64] @ 0x40 800df6c: 687b ldr r3, [r7, #4] 800df6e: 2201 movs r2, #1 800df70: f883 2041 strb.w r2, [r3, #65] @ 0x41 800df74: 687b ldr r3, [r7, #4] 800df76: 2201 movs r2, #1 800df78: f883 2042 strb.w r2, [r3, #66] @ 0x42 800df7c: 687b ldr r3, [r7, #4] 800df7e: 2201 movs r2, #1 800df80: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800df84: 687b ldr r3, [r7, #4] 800df86: 2201 movs r2, #1 800df88: f883 2044 strb.w r2, [r3, #68] @ 0x44 800df8c: 687b ldr r3, [r7, #4] 800df8e: 2201 movs r2, #1 800df90: f883 2045 strb.w r2, [r3, #69] @ 0x45 800df94: 687b ldr r3, [r7, #4] 800df96: 2201 movs r2, #1 800df98: f883 2046 strb.w r2, [r3, #70] @ 0x46 800df9c: 687b ldr r3, [r7, #4] 800df9e: 2201 movs r2, #1 800dfa0: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800dfa4: 687b ldr r3, [r7, #4] 800dfa6: 2201 movs r2, #1 800dfa8: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800dfac: 2300 movs r3, #0 } 800dfae: 4618 mov r0, r3 800dfb0: 3708 adds r7, #8 800dfb2: 46bd mov sp, r7 800dfb4: bd80 pop {r7, pc} ... 0800dfb8 : * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 800dfb8: b580 push {r7, lr} 800dfba: b084 sub sp, #16 800dfbc: af00 add r7, sp, #0 800dfbe: 6078 str r0, [r7, #4] 800dfc0: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 800dfc2: 683b ldr r3, [r7, #0] 800dfc4: 2b00 cmp r3, #0 800dfc6: d109 bne.n 800dfdc 800dfc8: 687b ldr r3, [r7, #4] 800dfca: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800dfce: b2db uxtb r3, r3 800dfd0: 2b01 cmp r3, #1 800dfd2: bf14 ite ne 800dfd4: 2301 movne r3, #1 800dfd6: 2300 moveq r3, #0 800dfd8: b2db uxtb r3, r3 800dfda: e03c b.n 800e056 800dfdc: 683b ldr r3, [r7, #0] 800dfde: 2b04 cmp r3, #4 800dfe0: d109 bne.n 800dff6 800dfe2: 687b ldr r3, [r7, #4] 800dfe4: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800dfe8: b2db uxtb r3, r3 800dfea: 2b01 cmp r3, #1 800dfec: bf14 ite ne 800dfee: 2301 movne r3, #1 800dff0: 2300 moveq r3, #0 800dff2: b2db uxtb r3, r3 800dff4: e02f b.n 800e056 800dff6: 683b ldr r3, [r7, #0] 800dff8: 2b08 cmp r3, #8 800dffa: d109 bne.n 800e010 800dffc: 687b ldr r3, [r7, #4] 800dffe: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800e002: b2db uxtb r3, r3 800e004: 2b01 cmp r3, #1 800e006: bf14 ite ne 800e008: 2301 movne r3, #1 800e00a: 2300 moveq r3, #0 800e00c: b2db uxtb r3, r3 800e00e: e022 b.n 800e056 800e010: 683b ldr r3, [r7, #0] 800e012: 2b0c cmp r3, #12 800e014: d109 bne.n 800e02a 800e016: 687b ldr r3, [r7, #4] 800e018: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800e01c: b2db uxtb r3, r3 800e01e: 2b01 cmp r3, #1 800e020: bf14 ite ne 800e022: 2301 movne r3, #1 800e024: 2300 moveq r3, #0 800e026: b2db uxtb r3, r3 800e028: e015 b.n 800e056 800e02a: 683b ldr r3, [r7, #0] 800e02c: 2b10 cmp r3, #16 800e02e: d109 bne.n 800e044 800e030: 687b ldr r3, [r7, #4] 800e032: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800e036: b2db uxtb r3, r3 800e038: 2b01 cmp r3, #1 800e03a: bf14 ite ne 800e03c: 2301 movne r3, #1 800e03e: 2300 moveq r3, #0 800e040: b2db uxtb r3, r3 800e042: e008 b.n 800e056 800e044: 687b ldr r3, [r7, #4] 800e046: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800e04a: b2db uxtb r3, r3 800e04c: 2b01 cmp r3, #1 800e04e: bf14 ite ne 800e050: 2301 movne r3, #1 800e052: 2300 moveq r3, #0 800e054: b2db uxtb r3, r3 800e056: 2b00 cmp r3, #0 800e058: d001 beq.n 800e05e { return HAL_ERROR; 800e05a: 2301 movs r3, #1 800e05c: e0a1 b.n 800e1a2 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800e05e: 683b ldr r3, [r7, #0] 800e060: 2b00 cmp r3, #0 800e062: d104 bne.n 800e06e 800e064: 687b ldr r3, [r7, #4] 800e066: 2202 movs r2, #2 800e068: f883 203e strb.w r2, [r3, #62] @ 0x3e 800e06c: e023 b.n 800e0b6 800e06e: 683b ldr r3, [r7, #0] 800e070: 2b04 cmp r3, #4 800e072: d104 bne.n 800e07e 800e074: 687b ldr r3, [r7, #4] 800e076: 2202 movs r2, #2 800e078: f883 203f strb.w r2, [r3, #63] @ 0x3f 800e07c: e01b b.n 800e0b6 800e07e: 683b ldr r3, [r7, #0] 800e080: 2b08 cmp r3, #8 800e082: d104 bne.n 800e08e 800e084: 687b ldr r3, [r7, #4] 800e086: 2202 movs r2, #2 800e088: f883 2040 strb.w r2, [r3, #64] @ 0x40 800e08c: e013 b.n 800e0b6 800e08e: 683b ldr r3, [r7, #0] 800e090: 2b0c cmp r3, #12 800e092: d104 bne.n 800e09e 800e094: 687b ldr r3, [r7, #4] 800e096: 2202 movs r2, #2 800e098: f883 2041 strb.w r2, [r3, #65] @ 0x41 800e09c: e00b b.n 800e0b6 800e09e: 683b ldr r3, [r7, #0] 800e0a0: 2b10 cmp r3, #16 800e0a2: d104 bne.n 800e0ae 800e0a4: 687b ldr r3, [r7, #4] 800e0a6: 2202 movs r2, #2 800e0a8: f883 2042 strb.w r2, [r3, #66] @ 0x42 800e0ac: e003 b.n 800e0b6 800e0ae: 687b ldr r3, [r7, #4] 800e0b0: 2202 movs r2, #2 800e0b2: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 800e0b6: 687b ldr r3, [r7, #4] 800e0b8: 681b ldr r3, [r3, #0] 800e0ba: 2201 movs r2, #1 800e0bc: 6839 ldr r1, [r7, #0] 800e0be: 4618 mov r0, r3 800e0c0: f001 f8ae bl 800f220 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800e0c4: 687b ldr r3, [r7, #4] 800e0c6: 681b ldr r3, [r3, #0] 800e0c8: 4a38 ldr r2, [pc, #224] @ (800e1ac ) 800e0ca: 4293 cmp r3, r2 800e0cc: d013 beq.n 800e0f6 800e0ce: 687b ldr r3, [r7, #4] 800e0d0: 681b ldr r3, [r3, #0] 800e0d2: 4a37 ldr r2, [pc, #220] @ (800e1b0 ) 800e0d4: 4293 cmp r3, r2 800e0d6: d00e beq.n 800e0f6 800e0d8: 687b ldr r3, [r7, #4] 800e0da: 681b ldr r3, [r3, #0] 800e0dc: 4a35 ldr r2, [pc, #212] @ (800e1b4 ) 800e0de: 4293 cmp r3, r2 800e0e0: d009 beq.n 800e0f6 800e0e2: 687b ldr r3, [r7, #4] 800e0e4: 681b ldr r3, [r3, #0] 800e0e6: 4a34 ldr r2, [pc, #208] @ (800e1b8 ) 800e0e8: 4293 cmp r3, r2 800e0ea: d004 beq.n 800e0f6 800e0ec: 687b ldr r3, [r7, #4] 800e0ee: 681b ldr r3, [r3, #0] 800e0f0: 4a32 ldr r2, [pc, #200] @ (800e1bc ) 800e0f2: 4293 cmp r3, r2 800e0f4: d101 bne.n 800e0fa 800e0f6: 2301 movs r3, #1 800e0f8: e000 b.n 800e0fc 800e0fa: 2300 movs r3, #0 800e0fc: 2b00 cmp r3, #0 800e0fe: d007 beq.n 800e110 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 800e100: 687b ldr r3, [r7, #4] 800e102: 681b ldr r3, [r3, #0] 800e104: 6c5a ldr r2, [r3, #68] @ 0x44 800e106: 687b ldr r3, [r7, #4] 800e108: 681b ldr r3, [r3, #0] 800e10a: f442 4200 orr.w r2, r2, #32768 @ 0x8000 800e10e: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800e110: 687b ldr r3, [r7, #4] 800e112: 681b ldr r3, [r3, #0] 800e114: 4a25 ldr r2, [pc, #148] @ (800e1ac ) 800e116: 4293 cmp r3, r2 800e118: d022 beq.n 800e160 800e11a: 687b ldr r3, [r7, #4] 800e11c: 681b ldr r3, [r3, #0] 800e11e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800e122: d01d beq.n 800e160 800e124: 687b ldr r3, [r7, #4] 800e126: 681b ldr r3, [r3, #0] 800e128: 4a25 ldr r2, [pc, #148] @ (800e1c0 ) 800e12a: 4293 cmp r3, r2 800e12c: d018 beq.n 800e160 800e12e: 687b ldr r3, [r7, #4] 800e130: 681b ldr r3, [r3, #0] 800e132: 4a24 ldr r2, [pc, #144] @ (800e1c4 ) 800e134: 4293 cmp r3, r2 800e136: d013 beq.n 800e160 800e138: 687b ldr r3, [r7, #4] 800e13a: 681b ldr r3, [r3, #0] 800e13c: 4a22 ldr r2, [pc, #136] @ (800e1c8 ) 800e13e: 4293 cmp r3, r2 800e140: d00e beq.n 800e160 800e142: 687b ldr r3, [r7, #4] 800e144: 681b ldr r3, [r3, #0] 800e146: 4a1a ldr r2, [pc, #104] @ (800e1b0 ) 800e148: 4293 cmp r3, r2 800e14a: d009 beq.n 800e160 800e14c: 687b ldr r3, [r7, #4] 800e14e: 681b ldr r3, [r3, #0] 800e150: 4a1e ldr r2, [pc, #120] @ (800e1cc ) 800e152: 4293 cmp r3, r2 800e154: d004 beq.n 800e160 800e156: 687b ldr r3, [r7, #4] 800e158: 681b ldr r3, [r3, #0] 800e15a: 4a16 ldr r2, [pc, #88] @ (800e1b4 ) 800e15c: 4293 cmp r3, r2 800e15e: d115 bne.n 800e18c { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800e160: 687b ldr r3, [r7, #4] 800e162: 681b ldr r3, [r3, #0] 800e164: 689a ldr r2, [r3, #8] 800e166: 4b1a ldr r3, [pc, #104] @ (800e1d0 ) 800e168: 4013 ands r3, r2 800e16a: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800e16c: 68fb ldr r3, [r7, #12] 800e16e: 2b06 cmp r3, #6 800e170: d015 beq.n 800e19e 800e172: 68fb ldr r3, [r7, #12] 800e174: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e178: d011 beq.n 800e19e { __HAL_TIM_ENABLE(htim); 800e17a: 687b ldr r3, [r7, #4] 800e17c: 681b ldr r3, [r3, #0] 800e17e: 681a ldr r2, [r3, #0] 800e180: 687b ldr r3, [r7, #4] 800e182: 681b ldr r3, [r3, #0] 800e184: f042 0201 orr.w r2, r2, #1 800e188: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800e18a: e008 b.n 800e19e } } else { __HAL_TIM_ENABLE(htim); 800e18c: 687b ldr r3, [r7, #4] 800e18e: 681b ldr r3, [r3, #0] 800e190: 681a ldr r2, [r3, #0] 800e192: 687b ldr r3, [r7, #4] 800e194: 681b ldr r3, [r3, #0] 800e196: f042 0201 orr.w r2, r2, #1 800e19a: 601a str r2, [r3, #0] 800e19c: e000 b.n 800e1a0 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800e19e: bf00 nop } /* Return function status */ return HAL_OK; 800e1a0: 2300 movs r3, #0 } 800e1a2: 4618 mov r0, r3 800e1a4: 3710 adds r7, #16 800e1a6: 46bd mov sp, r7 800e1a8: bd80 pop {r7, pc} 800e1aa: bf00 nop 800e1ac: 40010000 .word 0x40010000 800e1b0: 40010400 .word 0x40010400 800e1b4: 40014000 .word 0x40014000 800e1b8: 40014400 .word 0x40014400 800e1bc: 40014800 .word 0x40014800 800e1c0: 40000400 .word 0x40000400 800e1c4: 40000800 .word 0x40000800 800e1c8: 40000c00 .word 0x40000c00 800e1cc: 40001800 .word 0x40001800 800e1d0: 00010007 .word 0x00010007 0800e1d4 : * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { 800e1d4: b580 push {r7, lr} 800e1d6: b082 sub sp, #8 800e1d8: af00 add r7, sp, #0 800e1da: 6078 str r0, [r7, #4] 800e1dc: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 800e1de: 687b ldr r3, [r7, #4] 800e1e0: 681b ldr r3, [r3, #0] 800e1e2: 2200 movs r2, #0 800e1e4: 6839 ldr r1, [r7, #0] 800e1e6: 4618 mov r0, r3 800e1e8: f001 f81a bl 800f220 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800e1ec: 687b ldr r3, [r7, #4] 800e1ee: 681b ldr r3, [r3, #0] 800e1f0: 4a3e ldr r2, [pc, #248] @ (800e2ec ) 800e1f2: 4293 cmp r3, r2 800e1f4: d013 beq.n 800e21e 800e1f6: 687b ldr r3, [r7, #4] 800e1f8: 681b ldr r3, [r3, #0] 800e1fa: 4a3d ldr r2, [pc, #244] @ (800e2f0 ) 800e1fc: 4293 cmp r3, r2 800e1fe: d00e beq.n 800e21e 800e200: 687b ldr r3, [r7, #4] 800e202: 681b ldr r3, [r3, #0] 800e204: 4a3b ldr r2, [pc, #236] @ (800e2f4 ) 800e206: 4293 cmp r3, r2 800e208: d009 beq.n 800e21e 800e20a: 687b ldr r3, [r7, #4] 800e20c: 681b ldr r3, [r3, #0] 800e20e: 4a3a ldr r2, [pc, #232] @ (800e2f8 ) 800e210: 4293 cmp r3, r2 800e212: d004 beq.n 800e21e 800e214: 687b ldr r3, [r7, #4] 800e216: 681b ldr r3, [r3, #0] 800e218: 4a38 ldr r2, [pc, #224] @ (800e2fc ) 800e21a: 4293 cmp r3, r2 800e21c: d101 bne.n 800e222 800e21e: 2301 movs r3, #1 800e220: e000 b.n 800e224 800e222: 2300 movs r3, #0 800e224: 2b00 cmp r3, #0 800e226: d017 beq.n 800e258 { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); 800e228: 687b ldr r3, [r7, #4] 800e22a: 681b ldr r3, [r3, #0] 800e22c: 6a1a ldr r2, [r3, #32] 800e22e: f241 1311 movw r3, #4369 @ 0x1111 800e232: 4013 ands r3, r2 800e234: 2b00 cmp r3, #0 800e236: d10f bne.n 800e258 800e238: 687b ldr r3, [r7, #4] 800e23a: 681b ldr r3, [r3, #0] 800e23c: 6a1a ldr r2, [r3, #32] 800e23e: f240 4344 movw r3, #1092 @ 0x444 800e242: 4013 ands r3, r2 800e244: 2b00 cmp r3, #0 800e246: d107 bne.n 800e258 800e248: 687b ldr r3, [r7, #4] 800e24a: 681b ldr r3, [r3, #0] 800e24c: 6c5a ldr r2, [r3, #68] @ 0x44 800e24e: 687b ldr r3, [r7, #4] 800e250: 681b ldr r3, [r3, #0] 800e252: f422 4200 bic.w r2, r2, #32768 @ 0x8000 800e256: 645a str r2, [r3, #68] @ 0x44 } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); 800e258: 687b ldr r3, [r7, #4] 800e25a: 681b ldr r3, [r3, #0] 800e25c: 6a1a ldr r2, [r3, #32] 800e25e: f241 1311 movw r3, #4369 @ 0x1111 800e262: 4013 ands r3, r2 800e264: 2b00 cmp r3, #0 800e266: d10f bne.n 800e288 800e268: 687b ldr r3, [r7, #4] 800e26a: 681b ldr r3, [r3, #0] 800e26c: 6a1a ldr r2, [r3, #32] 800e26e: f240 4344 movw r3, #1092 @ 0x444 800e272: 4013 ands r3, r2 800e274: 2b00 cmp r3, #0 800e276: d107 bne.n 800e288 800e278: 687b ldr r3, [r7, #4] 800e27a: 681b ldr r3, [r3, #0] 800e27c: 681a ldr r2, [r3, #0] 800e27e: 687b ldr r3, [r7, #4] 800e280: 681b ldr r3, [r3, #0] 800e282: f022 0201 bic.w r2, r2, #1 800e286: 601a str r2, [r3, #0] /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); 800e288: 683b ldr r3, [r7, #0] 800e28a: 2b00 cmp r3, #0 800e28c: d104 bne.n 800e298 800e28e: 687b ldr r3, [r7, #4] 800e290: 2201 movs r2, #1 800e292: f883 203e strb.w r2, [r3, #62] @ 0x3e 800e296: e023 b.n 800e2e0 800e298: 683b ldr r3, [r7, #0] 800e29a: 2b04 cmp r3, #4 800e29c: d104 bne.n 800e2a8 800e29e: 687b ldr r3, [r7, #4] 800e2a0: 2201 movs r2, #1 800e2a2: f883 203f strb.w r2, [r3, #63] @ 0x3f 800e2a6: e01b b.n 800e2e0 800e2a8: 683b ldr r3, [r7, #0] 800e2aa: 2b08 cmp r3, #8 800e2ac: d104 bne.n 800e2b8 800e2ae: 687b ldr r3, [r7, #4] 800e2b0: 2201 movs r2, #1 800e2b2: f883 2040 strb.w r2, [r3, #64] @ 0x40 800e2b6: e013 b.n 800e2e0 800e2b8: 683b ldr r3, [r7, #0] 800e2ba: 2b0c cmp r3, #12 800e2bc: d104 bne.n 800e2c8 800e2be: 687b ldr r3, [r7, #4] 800e2c0: 2201 movs r2, #1 800e2c2: f883 2041 strb.w r2, [r3, #65] @ 0x41 800e2c6: e00b b.n 800e2e0 800e2c8: 683b ldr r3, [r7, #0] 800e2ca: 2b10 cmp r3, #16 800e2cc: d104 bne.n 800e2d8 800e2ce: 687b ldr r3, [r7, #4] 800e2d0: 2201 movs r2, #1 800e2d2: f883 2042 strb.w r2, [r3, #66] @ 0x42 800e2d6: e003 b.n 800e2e0 800e2d8: 687b ldr r3, [r7, #4] 800e2da: 2201 movs r2, #1 800e2dc: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Return function status */ return HAL_OK; 800e2e0: 2300 movs r3, #0 } 800e2e2: 4618 mov r0, r3 800e2e4: 3708 adds r7, #8 800e2e6: 46bd mov sp, r7 800e2e8: bd80 pop {r7, pc} 800e2ea: bf00 nop 800e2ec: 40010000 .word 0x40010000 800e2f0: 40010400 .word 0x40010400 800e2f4: 40014000 .word 0x40014000 800e2f8: 40014400 .word 0x40014400 800e2fc: 40014800 .word 0x40014800 0800e300 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 800e300: b580 push {r7, lr} 800e302: b084 sub sp, #16 800e304: af00 add r7, sp, #0 800e306: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 800e308: 687b ldr r3, [r7, #4] 800e30a: 681b ldr r3, [r3, #0] 800e30c: 68db ldr r3, [r3, #12] 800e30e: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 800e310: 687b ldr r3, [r7, #4] 800e312: 681b ldr r3, [r3, #0] 800e314: 691b ldr r3, [r3, #16] 800e316: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 800e318: 68bb ldr r3, [r7, #8] 800e31a: f003 0302 and.w r3, r3, #2 800e31e: 2b00 cmp r3, #0 800e320: d020 beq.n 800e364 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 800e322: 68fb ldr r3, [r7, #12] 800e324: f003 0302 and.w r3, r3, #2 800e328: 2b00 cmp r3, #0 800e32a: d01b beq.n 800e364 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 800e32c: 687b ldr r3, [r7, #4] 800e32e: 681b ldr r3, [r3, #0] 800e330: f06f 0202 mvn.w r2, #2 800e334: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800e336: 687b ldr r3, [r7, #4] 800e338: 2201 movs r2, #1 800e33a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 800e33c: 687b ldr r3, [r7, #4] 800e33e: 681b ldr r3, [r3, #0] 800e340: 699b ldr r3, [r3, #24] 800e342: f003 0303 and.w r3, r3, #3 800e346: 2b00 cmp r3, #0 800e348: d003 beq.n 800e352 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800e34a: 6878 ldr r0, [r7, #4] 800e34c: f000 faf6 bl 800e93c 800e350: e005 b.n 800e35e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800e352: 6878 ldr r0, [r7, #4] 800e354: f000 fae8 bl 800e928 HAL_TIM_PWM_PulseFinishedCallback(htim); 800e358: 6878 ldr r0, [r7, #4] 800e35a: f000 faf9 bl 800e950 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800e35e: 687b ldr r3, [r7, #4] 800e360: 2200 movs r2, #0 800e362: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 800e364: 68bb ldr r3, [r7, #8] 800e366: f003 0304 and.w r3, r3, #4 800e36a: 2b00 cmp r3, #0 800e36c: d020 beq.n 800e3b0 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 800e36e: 68fb ldr r3, [r7, #12] 800e370: f003 0304 and.w r3, r3, #4 800e374: 2b00 cmp r3, #0 800e376: d01b beq.n 800e3b0 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 800e378: 687b ldr r3, [r7, #4] 800e37a: 681b ldr r3, [r3, #0] 800e37c: f06f 0204 mvn.w r2, #4 800e380: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800e382: 687b ldr r3, [r7, #4] 800e384: 2202 movs r2, #2 800e386: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 800e388: 687b ldr r3, [r7, #4] 800e38a: 681b ldr r3, [r3, #0] 800e38c: 699b ldr r3, [r3, #24] 800e38e: f403 7340 and.w r3, r3, #768 @ 0x300 800e392: 2b00 cmp r3, #0 800e394: d003 beq.n 800e39e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800e396: 6878 ldr r0, [r7, #4] 800e398: f000 fad0 bl 800e93c 800e39c: e005 b.n 800e3aa { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800e39e: 6878 ldr r0, [r7, #4] 800e3a0: f000 fac2 bl 800e928 HAL_TIM_PWM_PulseFinishedCallback(htim); 800e3a4: 6878 ldr r0, [r7, #4] 800e3a6: f000 fad3 bl 800e950 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800e3aa: 687b ldr r3, [r7, #4] 800e3ac: 2200 movs r2, #0 800e3ae: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 800e3b0: 68bb ldr r3, [r7, #8] 800e3b2: f003 0308 and.w r3, r3, #8 800e3b6: 2b00 cmp r3, #0 800e3b8: d020 beq.n 800e3fc { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 800e3ba: 68fb ldr r3, [r7, #12] 800e3bc: f003 0308 and.w r3, r3, #8 800e3c0: 2b00 cmp r3, #0 800e3c2: d01b beq.n 800e3fc { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 800e3c4: 687b ldr r3, [r7, #4] 800e3c6: 681b ldr r3, [r3, #0] 800e3c8: f06f 0208 mvn.w r2, #8 800e3cc: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800e3ce: 687b ldr r3, [r7, #4] 800e3d0: 2204 movs r2, #4 800e3d2: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800e3d4: 687b ldr r3, [r7, #4] 800e3d6: 681b ldr r3, [r3, #0] 800e3d8: 69db ldr r3, [r3, #28] 800e3da: f003 0303 and.w r3, r3, #3 800e3de: 2b00 cmp r3, #0 800e3e0: d003 beq.n 800e3ea { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800e3e2: 6878 ldr r0, [r7, #4] 800e3e4: f000 faaa bl 800e93c 800e3e8: e005 b.n 800e3f6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800e3ea: 6878 ldr r0, [r7, #4] 800e3ec: f000 fa9c bl 800e928 HAL_TIM_PWM_PulseFinishedCallback(htim); 800e3f0: 6878 ldr r0, [r7, #4] 800e3f2: f000 faad bl 800e950 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800e3f6: 687b ldr r3, [r7, #4] 800e3f8: 2200 movs r2, #0 800e3fa: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 800e3fc: 68bb ldr r3, [r7, #8] 800e3fe: f003 0310 and.w r3, r3, #16 800e402: 2b00 cmp r3, #0 800e404: d020 beq.n 800e448 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 800e406: 68fb ldr r3, [r7, #12] 800e408: f003 0310 and.w r3, r3, #16 800e40c: 2b00 cmp r3, #0 800e40e: d01b beq.n 800e448 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 800e410: 687b ldr r3, [r7, #4] 800e412: 681b ldr r3, [r3, #0] 800e414: f06f 0210 mvn.w r2, #16 800e418: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800e41a: 687b ldr r3, [r7, #4] 800e41c: 2208 movs r2, #8 800e41e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 800e420: 687b ldr r3, [r7, #4] 800e422: 681b ldr r3, [r3, #0] 800e424: 69db ldr r3, [r3, #28] 800e426: f403 7340 and.w r3, r3, #768 @ 0x300 800e42a: 2b00 cmp r3, #0 800e42c: d003 beq.n 800e436 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800e42e: 6878 ldr r0, [r7, #4] 800e430: f000 fa84 bl 800e93c 800e434: e005 b.n 800e442 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800e436: 6878 ldr r0, [r7, #4] 800e438: f000 fa76 bl 800e928 HAL_TIM_PWM_PulseFinishedCallback(htim); 800e43c: 6878 ldr r0, [r7, #4] 800e43e: f000 fa87 bl 800e950 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800e442: 687b ldr r3, [r7, #4] 800e444: 2200 movs r2, #0 800e446: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 800e448: 68bb ldr r3, [r7, #8] 800e44a: f003 0301 and.w r3, r3, #1 800e44e: 2b00 cmp r3, #0 800e450: d00c beq.n 800e46c { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 800e452: 68fb ldr r3, [r7, #12] 800e454: f003 0301 and.w r3, r3, #1 800e458: 2b00 cmp r3, #0 800e45a: d007 beq.n 800e46c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 800e45c: 687b ldr r3, [r7, #4] 800e45e: 681b ldr r3, [r3, #0] 800e460: f06f 0201 mvn.w r2, #1 800e464: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 800e466: 6878 ldr r0, [r7, #4] 800e468: f7f3 fac8 bl 80019fc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800e46c: 68bb ldr r3, [r7, #8] 800e46e: f003 0380 and.w r3, r3, #128 @ 0x80 800e472: 2b00 cmp r3, #0 800e474: d104 bne.n 800e480 ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) 800e476: 68bb ldr r3, [r7, #8] 800e478: f403 5300 and.w r3, r3, #8192 @ 0x2000 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800e47c: 2b00 cmp r3, #0 800e47e: d00c beq.n 800e49a { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800e480: 68fb ldr r3, [r7, #12] 800e482: f003 0380 and.w r3, r3, #128 @ 0x80 800e486: 2b00 cmp r3, #0 800e488: d007 beq.n 800e49a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 800e48a: 687b ldr r3, [r7, #4] 800e48c: 681b ldr r3, [r3, #0] 800e48e: f46f 5202 mvn.w r2, #8320 @ 0x2080 800e492: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 800e494: 6878 ldr r0, [r7, #4] 800e496: f000 ffff bl 800f498 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 800e49a: 68bb ldr r3, [r7, #8] 800e49c: f403 7380 and.w r3, r3, #256 @ 0x100 800e4a0: 2b00 cmp r3, #0 800e4a2: d00c beq.n 800e4be { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800e4a4: 68fb ldr r3, [r7, #12] 800e4a6: f003 0380 and.w r3, r3, #128 @ 0x80 800e4aa: 2b00 cmp r3, #0 800e4ac: d007 beq.n 800e4be { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 800e4ae: 687b ldr r3, [r7, #4] 800e4b0: 681b ldr r3, [r3, #0] 800e4b2: f46f 7280 mvn.w r2, #256 @ 0x100 800e4b6: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 800e4b8: 6878 ldr r0, [r7, #4] 800e4ba: f000 fff7 bl 800f4ac #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 800e4be: 68bb ldr r3, [r7, #8] 800e4c0: f003 0340 and.w r3, r3, #64 @ 0x40 800e4c4: 2b00 cmp r3, #0 800e4c6: d00c beq.n 800e4e2 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 800e4c8: 68fb ldr r3, [r7, #12] 800e4ca: f003 0340 and.w r3, r3, #64 @ 0x40 800e4ce: 2b00 cmp r3, #0 800e4d0: d007 beq.n 800e4e2 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 800e4d2: 687b ldr r3, [r7, #4] 800e4d4: 681b ldr r3, [r3, #0] 800e4d6: f06f 0240 mvn.w r2, #64 @ 0x40 800e4da: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 800e4dc: 6878 ldr r0, [r7, #4] 800e4de: f000 fa41 bl 800e964 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 800e4e2: 68bb ldr r3, [r7, #8] 800e4e4: f003 0320 and.w r3, r3, #32 800e4e8: 2b00 cmp r3, #0 800e4ea: d00c beq.n 800e506 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 800e4ec: 68fb ldr r3, [r7, #12] 800e4ee: f003 0320 and.w r3, r3, #32 800e4f2: 2b00 cmp r3, #0 800e4f4: d007 beq.n 800e506 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 800e4f6: 687b ldr r3, [r7, #4] 800e4f8: 681b ldr r3, [r3, #0] 800e4fa: f06f 0220 mvn.w r2, #32 800e4fe: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 800e500: 6878 ldr r0, [r7, #4] 800e502: f000 ffbf bl 800f484 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 800e506: bf00 nop 800e508: 3710 adds r7, #16 800e50a: 46bd mov sp, r7 800e50c: bd80 pop {r7, pc} ... 0800e510 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 800e510: b580 push {r7, lr} 800e512: b086 sub sp, #24 800e514: af00 add r7, sp, #0 800e516: 60f8 str r0, [r7, #12] 800e518: 60b9 str r1, [r7, #8] 800e51a: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800e51c: 2300 movs r3, #0 800e51e: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 800e520: 68fb ldr r3, [r7, #12] 800e522: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800e526: 2b01 cmp r3, #1 800e528: d101 bne.n 800e52e 800e52a: 2302 movs r3, #2 800e52c: e0ff b.n 800e72e 800e52e: 68fb ldr r3, [r7, #12] 800e530: 2201 movs r2, #1 800e532: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 800e536: 687b ldr r3, [r7, #4] 800e538: 2b14 cmp r3, #20 800e53a: f200 80f0 bhi.w 800e71e 800e53e: a201 add r2, pc, #4 @ (adr r2, 800e544 ) 800e540: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800e544: 0800e599 .word 0x0800e599 800e548: 0800e71f .word 0x0800e71f 800e54c: 0800e71f .word 0x0800e71f 800e550: 0800e71f .word 0x0800e71f 800e554: 0800e5d9 .word 0x0800e5d9 800e558: 0800e71f .word 0x0800e71f 800e55c: 0800e71f .word 0x0800e71f 800e560: 0800e71f .word 0x0800e71f 800e564: 0800e61b .word 0x0800e61b 800e568: 0800e71f .word 0x0800e71f 800e56c: 0800e71f .word 0x0800e71f 800e570: 0800e71f .word 0x0800e71f 800e574: 0800e65b .word 0x0800e65b 800e578: 0800e71f .word 0x0800e71f 800e57c: 0800e71f .word 0x0800e71f 800e580: 0800e71f .word 0x0800e71f 800e584: 0800e69d .word 0x0800e69d 800e588: 0800e71f .word 0x0800e71f 800e58c: 0800e71f .word 0x0800e71f 800e590: 0800e71f .word 0x0800e71f 800e594: 0800e6dd .word 0x0800e6dd { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 800e598: 68fb ldr r3, [r7, #12] 800e59a: 681b ldr r3, [r3, #0] 800e59c: 68b9 ldr r1, [r7, #8] 800e59e: 4618 mov r0, r3 800e5a0: f000 faca bl 800eb38 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 800e5a4: 68fb ldr r3, [r7, #12] 800e5a6: 681b ldr r3, [r3, #0] 800e5a8: 699a ldr r2, [r3, #24] 800e5aa: 68fb ldr r3, [r7, #12] 800e5ac: 681b ldr r3, [r3, #0] 800e5ae: f042 0208 orr.w r2, r2, #8 800e5b2: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 800e5b4: 68fb ldr r3, [r7, #12] 800e5b6: 681b ldr r3, [r3, #0] 800e5b8: 699a ldr r2, [r3, #24] 800e5ba: 68fb ldr r3, [r7, #12] 800e5bc: 681b ldr r3, [r3, #0] 800e5be: f022 0204 bic.w r2, r2, #4 800e5c2: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 800e5c4: 68fb ldr r3, [r7, #12] 800e5c6: 681b ldr r3, [r3, #0] 800e5c8: 6999 ldr r1, [r3, #24] 800e5ca: 68bb ldr r3, [r7, #8] 800e5cc: 691a ldr r2, [r3, #16] 800e5ce: 68fb ldr r3, [r7, #12] 800e5d0: 681b ldr r3, [r3, #0] 800e5d2: 430a orrs r2, r1 800e5d4: 619a str r2, [r3, #24] break; 800e5d6: e0a5 b.n 800e724 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 800e5d8: 68fb ldr r3, [r7, #12] 800e5da: 681b ldr r3, [r3, #0] 800e5dc: 68b9 ldr r1, [r7, #8] 800e5de: 4618 mov r0, r3 800e5e0: f000 fb3a bl 800ec58 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 800e5e4: 68fb ldr r3, [r7, #12] 800e5e6: 681b ldr r3, [r3, #0] 800e5e8: 699a ldr r2, [r3, #24] 800e5ea: 68fb ldr r3, [r7, #12] 800e5ec: 681b ldr r3, [r3, #0] 800e5ee: f442 6200 orr.w r2, r2, #2048 @ 0x800 800e5f2: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 800e5f4: 68fb ldr r3, [r7, #12] 800e5f6: 681b ldr r3, [r3, #0] 800e5f8: 699a ldr r2, [r3, #24] 800e5fa: 68fb ldr r3, [r7, #12] 800e5fc: 681b ldr r3, [r3, #0] 800e5fe: f422 6280 bic.w r2, r2, #1024 @ 0x400 800e602: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 800e604: 68fb ldr r3, [r7, #12] 800e606: 681b ldr r3, [r3, #0] 800e608: 6999 ldr r1, [r3, #24] 800e60a: 68bb ldr r3, [r7, #8] 800e60c: 691b ldr r3, [r3, #16] 800e60e: 021a lsls r2, r3, #8 800e610: 68fb ldr r3, [r7, #12] 800e612: 681b ldr r3, [r3, #0] 800e614: 430a orrs r2, r1 800e616: 619a str r2, [r3, #24] break; 800e618: e084 b.n 800e724 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 800e61a: 68fb ldr r3, [r7, #12] 800e61c: 681b ldr r3, [r3, #0] 800e61e: 68b9 ldr r1, [r7, #8] 800e620: 4618 mov r0, r3 800e622: f000 fba3 bl 800ed6c /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 800e626: 68fb ldr r3, [r7, #12] 800e628: 681b ldr r3, [r3, #0] 800e62a: 69da ldr r2, [r3, #28] 800e62c: 68fb ldr r3, [r7, #12] 800e62e: 681b ldr r3, [r3, #0] 800e630: f042 0208 orr.w r2, r2, #8 800e634: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 800e636: 68fb ldr r3, [r7, #12] 800e638: 681b ldr r3, [r3, #0] 800e63a: 69da ldr r2, [r3, #28] 800e63c: 68fb ldr r3, [r7, #12] 800e63e: 681b ldr r3, [r3, #0] 800e640: f022 0204 bic.w r2, r2, #4 800e644: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 800e646: 68fb ldr r3, [r7, #12] 800e648: 681b ldr r3, [r3, #0] 800e64a: 69d9 ldr r1, [r3, #28] 800e64c: 68bb ldr r3, [r7, #8] 800e64e: 691a ldr r2, [r3, #16] 800e650: 68fb ldr r3, [r7, #12] 800e652: 681b ldr r3, [r3, #0] 800e654: 430a orrs r2, r1 800e656: 61da str r2, [r3, #28] break; 800e658: e064 b.n 800e724 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 800e65a: 68fb ldr r3, [r7, #12] 800e65c: 681b ldr r3, [r3, #0] 800e65e: 68b9 ldr r1, [r7, #8] 800e660: 4618 mov r0, r3 800e662: f000 fc0b bl 800ee7c /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 800e666: 68fb ldr r3, [r7, #12] 800e668: 681b ldr r3, [r3, #0] 800e66a: 69da ldr r2, [r3, #28] 800e66c: 68fb ldr r3, [r7, #12] 800e66e: 681b ldr r3, [r3, #0] 800e670: f442 6200 orr.w r2, r2, #2048 @ 0x800 800e674: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 800e676: 68fb ldr r3, [r7, #12] 800e678: 681b ldr r3, [r3, #0] 800e67a: 69da ldr r2, [r3, #28] 800e67c: 68fb ldr r3, [r7, #12] 800e67e: 681b ldr r3, [r3, #0] 800e680: f422 6280 bic.w r2, r2, #1024 @ 0x400 800e684: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 800e686: 68fb ldr r3, [r7, #12] 800e688: 681b ldr r3, [r3, #0] 800e68a: 69d9 ldr r1, [r3, #28] 800e68c: 68bb ldr r3, [r7, #8] 800e68e: 691b ldr r3, [r3, #16] 800e690: 021a lsls r2, r3, #8 800e692: 68fb ldr r3, [r7, #12] 800e694: 681b ldr r3, [r3, #0] 800e696: 430a orrs r2, r1 800e698: 61da str r2, [r3, #28] break; 800e69a: e043 b.n 800e724 { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); 800e69c: 68fb ldr r3, [r7, #12] 800e69e: 681b ldr r3, [r3, #0] 800e6a0: 68b9 ldr r1, [r7, #8] 800e6a2: 4618 mov r0, r3 800e6a4: f000 fc54 bl 800ef50 /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 800e6a8: 68fb ldr r3, [r7, #12] 800e6aa: 681b ldr r3, [r3, #0] 800e6ac: 6d5a ldr r2, [r3, #84] @ 0x54 800e6ae: 68fb ldr r3, [r7, #12] 800e6b0: 681b ldr r3, [r3, #0] 800e6b2: f042 0208 orr.w r2, r2, #8 800e6b6: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 800e6b8: 68fb ldr r3, [r7, #12] 800e6ba: 681b ldr r3, [r3, #0] 800e6bc: 6d5a ldr r2, [r3, #84] @ 0x54 800e6be: 68fb ldr r3, [r7, #12] 800e6c0: 681b ldr r3, [r3, #0] 800e6c2: f022 0204 bic.w r2, r2, #4 800e6c6: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; 800e6c8: 68fb ldr r3, [r7, #12] 800e6ca: 681b ldr r3, [r3, #0] 800e6cc: 6d59 ldr r1, [r3, #84] @ 0x54 800e6ce: 68bb ldr r3, [r7, #8] 800e6d0: 691a ldr r2, [r3, #16] 800e6d2: 68fb ldr r3, [r7, #12] 800e6d4: 681b ldr r3, [r3, #0] 800e6d6: 430a orrs r2, r1 800e6d8: 655a str r2, [r3, #84] @ 0x54 break; 800e6da: e023 b.n 800e724 { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); 800e6dc: 68fb ldr r3, [r7, #12] 800e6de: 681b ldr r3, [r3, #0] 800e6e0: 68b9 ldr r1, [r7, #8] 800e6e2: 4618 mov r0, r3 800e6e4: f000 fc98 bl 800f018 /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 800e6e8: 68fb ldr r3, [r7, #12] 800e6ea: 681b ldr r3, [r3, #0] 800e6ec: 6d5a ldr r2, [r3, #84] @ 0x54 800e6ee: 68fb ldr r3, [r7, #12] 800e6f0: 681b ldr r3, [r3, #0] 800e6f2: f442 6200 orr.w r2, r2, #2048 @ 0x800 800e6f6: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 800e6f8: 68fb ldr r3, [r7, #12] 800e6fa: 681b ldr r3, [r3, #0] 800e6fc: 6d5a ldr r2, [r3, #84] @ 0x54 800e6fe: 68fb ldr r3, [r7, #12] 800e700: 681b ldr r3, [r3, #0] 800e702: f422 6280 bic.w r2, r2, #1024 @ 0x400 800e706: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 800e708: 68fb ldr r3, [r7, #12] 800e70a: 681b ldr r3, [r3, #0] 800e70c: 6d59 ldr r1, [r3, #84] @ 0x54 800e70e: 68bb ldr r3, [r7, #8] 800e710: 691b ldr r3, [r3, #16] 800e712: 021a lsls r2, r3, #8 800e714: 68fb ldr r3, [r7, #12] 800e716: 681b ldr r3, [r3, #0] 800e718: 430a orrs r2, r1 800e71a: 655a str r2, [r3, #84] @ 0x54 break; 800e71c: e002 b.n 800e724 } default: status = HAL_ERROR; 800e71e: 2301 movs r3, #1 800e720: 75fb strb r3, [r7, #23] break; 800e722: bf00 nop } __HAL_UNLOCK(htim); 800e724: 68fb ldr r3, [r7, #12] 800e726: 2200 movs r2, #0 800e728: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 800e72c: 7dfb ldrb r3, [r7, #23] } 800e72e: 4618 mov r0, r3 800e730: 3718 adds r7, #24 800e732: 46bd mov sp, r7 800e734: bd80 pop {r7, pc} 800e736: bf00 nop 0800e738 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 800e738: b580 push {r7, lr} 800e73a: b084 sub sp, #16 800e73c: af00 add r7, sp, #0 800e73e: 6078 str r0, [r7, #4] 800e740: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800e742: 2300 movs r3, #0 800e744: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 800e746: 687b ldr r3, [r7, #4] 800e748: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800e74c: 2b01 cmp r3, #1 800e74e: d101 bne.n 800e754 800e750: 2302 movs r3, #2 800e752: e0dc b.n 800e90e 800e754: 687b ldr r3, [r7, #4] 800e756: 2201 movs r2, #1 800e758: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 800e75c: 687b ldr r3, [r7, #4] 800e75e: 2202 movs r2, #2 800e760: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 800e764: 687b ldr r3, [r7, #4] 800e766: 681b ldr r3, [r3, #0] 800e768: 689b ldr r3, [r3, #8] 800e76a: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 800e76c: 68ba ldr r2, [r7, #8] 800e76e: 4b6a ldr r3, [pc, #424] @ (800e918 ) 800e770: 4013 ands r3, r2 800e772: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 800e774: 68bb ldr r3, [r7, #8] 800e776: f423 437f bic.w r3, r3, #65280 @ 0xff00 800e77a: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 800e77c: 687b ldr r3, [r7, #4] 800e77e: 681b ldr r3, [r3, #0] 800e780: 68ba ldr r2, [r7, #8] 800e782: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 800e784: 683b ldr r3, [r7, #0] 800e786: 681b ldr r3, [r3, #0] 800e788: 4a64 ldr r2, [pc, #400] @ (800e91c ) 800e78a: 4293 cmp r3, r2 800e78c: f000 80a9 beq.w 800e8e2 800e790: 4a62 ldr r2, [pc, #392] @ (800e91c ) 800e792: 4293 cmp r3, r2 800e794: f200 80ae bhi.w 800e8f4 800e798: 4a61 ldr r2, [pc, #388] @ (800e920 ) 800e79a: 4293 cmp r3, r2 800e79c: f000 80a1 beq.w 800e8e2 800e7a0: 4a5f ldr r2, [pc, #380] @ (800e920 ) 800e7a2: 4293 cmp r3, r2 800e7a4: f200 80a6 bhi.w 800e8f4 800e7a8: 4a5e ldr r2, [pc, #376] @ (800e924 ) 800e7aa: 4293 cmp r3, r2 800e7ac: f000 8099 beq.w 800e8e2 800e7b0: 4a5c ldr r2, [pc, #368] @ (800e924 ) 800e7b2: 4293 cmp r3, r2 800e7b4: f200 809e bhi.w 800e8f4 800e7b8: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 800e7bc: f000 8091 beq.w 800e8e2 800e7c0: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 800e7c4: f200 8096 bhi.w 800e8f4 800e7c8: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800e7cc: f000 8089 beq.w 800e8e2 800e7d0: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800e7d4: f200 808e bhi.w 800e8f4 800e7d8: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800e7dc: d03e beq.n 800e85c 800e7de: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800e7e2: f200 8087 bhi.w 800e8f4 800e7e6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800e7ea: f000 8086 beq.w 800e8fa 800e7ee: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800e7f2: d87f bhi.n 800e8f4 800e7f4: 2b70 cmp r3, #112 @ 0x70 800e7f6: d01a beq.n 800e82e 800e7f8: 2b70 cmp r3, #112 @ 0x70 800e7fa: d87b bhi.n 800e8f4 800e7fc: 2b60 cmp r3, #96 @ 0x60 800e7fe: d050 beq.n 800e8a2 800e800: 2b60 cmp r3, #96 @ 0x60 800e802: d877 bhi.n 800e8f4 800e804: 2b50 cmp r3, #80 @ 0x50 800e806: d03c beq.n 800e882 800e808: 2b50 cmp r3, #80 @ 0x50 800e80a: d873 bhi.n 800e8f4 800e80c: 2b40 cmp r3, #64 @ 0x40 800e80e: d058 beq.n 800e8c2 800e810: 2b40 cmp r3, #64 @ 0x40 800e812: d86f bhi.n 800e8f4 800e814: 2b30 cmp r3, #48 @ 0x30 800e816: d064 beq.n 800e8e2 800e818: 2b30 cmp r3, #48 @ 0x30 800e81a: d86b bhi.n 800e8f4 800e81c: 2b20 cmp r3, #32 800e81e: d060 beq.n 800e8e2 800e820: 2b20 cmp r3, #32 800e822: d867 bhi.n 800e8f4 800e824: 2b00 cmp r3, #0 800e826: d05c beq.n 800e8e2 800e828: 2b10 cmp r3, #16 800e82a: d05a beq.n 800e8e2 800e82c: e062 b.n 800e8f4 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 800e82e: 687b ldr r3, [r7, #4] 800e830: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 800e832: 683b ldr r3, [r7, #0] 800e834: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 800e836: 683b ldr r3, [r7, #0] 800e838: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 800e83a: 683b ldr r3, [r7, #0] 800e83c: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 800e83e: f000 fccf bl 800f1e0 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 800e842: 687b ldr r3, [r7, #4] 800e844: 681b ldr r3, [r3, #0] 800e846: 689b ldr r3, [r3, #8] 800e848: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 800e84a: 68bb ldr r3, [r7, #8] 800e84c: f043 0377 orr.w r3, r3, #119 @ 0x77 800e850: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800e852: 687b ldr r3, [r7, #4] 800e854: 681b ldr r3, [r3, #0] 800e856: 68ba ldr r2, [r7, #8] 800e858: 609a str r2, [r3, #8] break; 800e85a: e04f b.n 800e8fc assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 800e85c: 687b ldr r3, [r7, #4] 800e85e: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 800e860: 683b ldr r3, [r7, #0] 800e862: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 800e864: 683b ldr r3, [r7, #0] 800e866: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 800e868: 683b ldr r3, [r7, #0] 800e86a: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 800e86c: f000 fcb8 bl 800f1e0 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 800e870: 687b ldr r3, [r7, #4] 800e872: 681b ldr r3, [r3, #0] 800e874: 689a ldr r2, [r3, #8] 800e876: 687b ldr r3, [r7, #4] 800e878: 681b ldr r3, [r3, #0] 800e87a: f442 4280 orr.w r2, r2, #16384 @ 0x4000 800e87e: 609a str r2, [r3, #8] break; 800e880: e03c b.n 800e8fc /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 800e882: 687b ldr r3, [r7, #4] 800e884: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800e886: 683b ldr r3, [r7, #0] 800e888: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800e88a: 683b ldr r3, [r7, #0] 800e88c: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 800e88e: 461a mov r2, r3 800e890: f000 fc28 bl 800f0e4 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 800e894: 687b ldr r3, [r7, #4] 800e896: 681b ldr r3, [r3, #0] 800e898: 2150 movs r1, #80 @ 0x50 800e89a: 4618 mov r0, r3 800e89c: f000 fc82 bl 800f1a4 break; 800e8a0: e02c b.n 800e8fc /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 800e8a2: 687b ldr r3, [r7, #4] 800e8a4: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800e8a6: 683b ldr r3, [r7, #0] 800e8a8: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800e8aa: 683b ldr r3, [r7, #0] 800e8ac: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 800e8ae: 461a mov r2, r3 800e8b0: f000 fc47 bl 800f142 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 800e8b4: 687b ldr r3, [r7, #4] 800e8b6: 681b ldr r3, [r3, #0] 800e8b8: 2160 movs r1, #96 @ 0x60 800e8ba: 4618 mov r0, r3 800e8bc: f000 fc72 bl 800f1a4 break; 800e8c0: e01c b.n 800e8fc /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 800e8c2: 687b ldr r3, [r7, #4] 800e8c4: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800e8c6: 683b ldr r3, [r7, #0] 800e8c8: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800e8ca: 683b ldr r3, [r7, #0] 800e8cc: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 800e8ce: 461a mov r2, r3 800e8d0: f000 fc08 bl 800f0e4 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 800e8d4: 687b ldr r3, [r7, #4] 800e8d6: 681b ldr r3, [r3, #0] 800e8d8: 2140 movs r1, #64 @ 0x40 800e8da: 4618 mov r0, r3 800e8dc: f000 fc62 bl 800f1a4 break; 800e8e0: e00c b.n 800e8fc case TIM_CLOCKSOURCE_ITR8: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 800e8e2: 687b ldr r3, [r7, #4] 800e8e4: 681a ldr r2, [r3, #0] 800e8e6: 683b ldr r3, [r7, #0] 800e8e8: 681b ldr r3, [r3, #0] 800e8ea: 4619 mov r1, r3 800e8ec: 4610 mov r0, r2 800e8ee: f000 fc59 bl 800f1a4 break; 800e8f2: e003 b.n 800e8fc } default: status = HAL_ERROR; 800e8f4: 2301 movs r3, #1 800e8f6: 73fb strb r3, [r7, #15] break; 800e8f8: e000 b.n 800e8fc break; 800e8fa: bf00 nop } htim->State = HAL_TIM_STATE_READY; 800e8fc: 687b ldr r3, [r7, #4] 800e8fe: 2201 movs r2, #1 800e900: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 800e904: 687b ldr r3, [r7, #4] 800e906: 2200 movs r2, #0 800e908: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 800e90c: 7bfb ldrb r3, [r7, #15] } 800e90e: 4618 mov r0, r3 800e910: 3710 adds r7, #16 800e912: 46bd mov sp, r7 800e914: bd80 pop {r7, pc} 800e916: bf00 nop 800e918: ffceff88 .word 0xffceff88 800e91c: 00100040 .word 0x00100040 800e920: 00100030 .word 0x00100030 800e924: 00100020 .word 0x00100020 0800e928 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 800e928: b480 push {r7} 800e92a: b083 sub sp, #12 800e92c: af00 add r7, sp, #0 800e92e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 800e930: bf00 nop 800e932: 370c adds r7, #12 800e934: 46bd mov sp, r7 800e936: f85d 7b04 ldr.w r7, [sp], #4 800e93a: 4770 bx lr 0800e93c : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 800e93c: b480 push {r7} 800e93e: b083 sub sp, #12 800e940: af00 add r7, sp, #0 800e942: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 800e944: bf00 nop 800e946: 370c adds r7, #12 800e948: 46bd mov sp, r7 800e94a: f85d 7b04 ldr.w r7, [sp], #4 800e94e: 4770 bx lr 0800e950 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 800e950: b480 push {r7} 800e952: b083 sub sp, #12 800e954: af00 add r7, sp, #0 800e956: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 800e958: bf00 nop 800e95a: 370c adds r7, #12 800e95c: 46bd mov sp, r7 800e95e: f85d 7b04 ldr.w r7, [sp], #4 800e962: 4770 bx lr 0800e964 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 800e964: b480 push {r7} 800e966: b083 sub sp, #12 800e968: af00 add r7, sp, #0 800e96a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 800e96c: bf00 nop 800e96e: 370c adds r7, #12 800e970: 46bd mov sp, r7 800e972: f85d 7b04 ldr.w r7, [sp], #4 800e976: 4770 bx lr 0800e978 : * @arg TIM_CHANNEL_5: TIM Channel 5 * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) { 800e978: b480 push {r7} 800e97a: b085 sub sp, #20 800e97c: af00 add r7, sp, #0 800e97e: 6078 str r0, [r7, #4] 800e980: 6039 str r1, [r7, #0] HAL_TIM_ChannelStateTypeDef channel_state; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); 800e982: 683b ldr r3, [r7, #0] 800e984: 2b00 cmp r3, #0 800e986: d104 bne.n 800e992 800e988: 687b ldr r3, [r7, #4] 800e98a: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800e98e: b2db uxtb r3, r3 800e990: e023 b.n 800e9da 800e992: 683b ldr r3, [r7, #0] 800e994: 2b04 cmp r3, #4 800e996: d104 bne.n 800e9a2 800e998: 687b ldr r3, [r7, #4] 800e99a: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800e99e: b2db uxtb r3, r3 800e9a0: e01b b.n 800e9da 800e9a2: 683b ldr r3, [r7, #0] 800e9a4: 2b08 cmp r3, #8 800e9a6: d104 bne.n 800e9b2 800e9a8: 687b ldr r3, [r7, #4] 800e9aa: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800e9ae: b2db uxtb r3, r3 800e9b0: e013 b.n 800e9da 800e9b2: 683b ldr r3, [r7, #0] 800e9b4: 2b0c cmp r3, #12 800e9b6: d104 bne.n 800e9c2 800e9b8: 687b ldr r3, [r7, #4] 800e9ba: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800e9be: b2db uxtb r3, r3 800e9c0: e00b b.n 800e9da 800e9c2: 683b ldr r3, [r7, #0] 800e9c4: 2b10 cmp r3, #16 800e9c6: d104 bne.n 800e9d2 800e9c8: 687b ldr r3, [r7, #4] 800e9ca: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800e9ce: b2db uxtb r3, r3 800e9d0: e003 b.n 800e9da 800e9d2: 687b ldr r3, [r7, #4] 800e9d4: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800e9d8: b2db uxtb r3, r3 800e9da: 73fb strb r3, [r7, #15] return channel_state; 800e9dc: 7bfb ldrb r3, [r7, #15] } 800e9de: 4618 mov r0, r3 800e9e0: 3714 adds r7, #20 800e9e2: 46bd mov sp, r7 800e9e4: f85d 7b04 ldr.w r7, [sp], #4 800e9e8: 4770 bx lr ... 0800e9ec : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 800e9ec: b480 push {r7} 800e9ee: b085 sub sp, #20 800e9f0: af00 add r7, sp, #0 800e9f2: 6078 str r0, [r7, #4] 800e9f4: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 800e9f6: 687b ldr r3, [r7, #4] 800e9f8: 681b ldr r3, [r3, #0] 800e9fa: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 800e9fc: 687b ldr r3, [r7, #4] 800e9fe: 4a46 ldr r2, [pc, #280] @ (800eb18 ) 800ea00: 4293 cmp r3, r2 800ea02: d013 beq.n 800ea2c 800ea04: 687b ldr r3, [r7, #4] 800ea06: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800ea0a: d00f beq.n 800ea2c 800ea0c: 687b ldr r3, [r7, #4] 800ea0e: 4a43 ldr r2, [pc, #268] @ (800eb1c ) 800ea10: 4293 cmp r3, r2 800ea12: d00b beq.n 800ea2c 800ea14: 687b ldr r3, [r7, #4] 800ea16: 4a42 ldr r2, [pc, #264] @ (800eb20 ) 800ea18: 4293 cmp r3, r2 800ea1a: d007 beq.n 800ea2c 800ea1c: 687b ldr r3, [r7, #4] 800ea1e: 4a41 ldr r2, [pc, #260] @ (800eb24 ) 800ea20: 4293 cmp r3, r2 800ea22: d003 beq.n 800ea2c 800ea24: 687b ldr r3, [r7, #4] 800ea26: 4a40 ldr r2, [pc, #256] @ (800eb28 ) 800ea28: 4293 cmp r3, r2 800ea2a: d108 bne.n 800ea3e { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 800ea2c: 68fb ldr r3, [r7, #12] 800ea2e: f023 0370 bic.w r3, r3, #112 @ 0x70 800ea32: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 800ea34: 683b ldr r3, [r7, #0] 800ea36: 685b ldr r3, [r3, #4] 800ea38: 68fa ldr r2, [r7, #12] 800ea3a: 4313 orrs r3, r2 800ea3c: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800ea3e: 687b ldr r3, [r7, #4] 800ea40: 4a35 ldr r2, [pc, #212] @ (800eb18 ) 800ea42: 4293 cmp r3, r2 800ea44: d01f beq.n 800ea86 800ea46: 687b ldr r3, [r7, #4] 800ea48: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800ea4c: d01b beq.n 800ea86 800ea4e: 687b ldr r3, [r7, #4] 800ea50: 4a32 ldr r2, [pc, #200] @ (800eb1c ) 800ea52: 4293 cmp r3, r2 800ea54: d017 beq.n 800ea86 800ea56: 687b ldr r3, [r7, #4] 800ea58: 4a31 ldr r2, [pc, #196] @ (800eb20 ) 800ea5a: 4293 cmp r3, r2 800ea5c: d013 beq.n 800ea86 800ea5e: 687b ldr r3, [r7, #4] 800ea60: 4a30 ldr r2, [pc, #192] @ (800eb24 ) 800ea62: 4293 cmp r3, r2 800ea64: d00f beq.n 800ea86 800ea66: 687b ldr r3, [r7, #4] 800ea68: 4a2f ldr r2, [pc, #188] @ (800eb28 ) 800ea6a: 4293 cmp r3, r2 800ea6c: d00b beq.n 800ea86 800ea6e: 687b ldr r3, [r7, #4] 800ea70: 4a2e ldr r2, [pc, #184] @ (800eb2c ) 800ea72: 4293 cmp r3, r2 800ea74: d007 beq.n 800ea86 800ea76: 687b ldr r3, [r7, #4] 800ea78: 4a2d ldr r2, [pc, #180] @ (800eb30 ) 800ea7a: 4293 cmp r3, r2 800ea7c: d003 beq.n 800ea86 800ea7e: 687b ldr r3, [r7, #4] 800ea80: 4a2c ldr r2, [pc, #176] @ (800eb34 ) 800ea82: 4293 cmp r3, r2 800ea84: d108 bne.n 800ea98 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800ea86: 68fb ldr r3, [r7, #12] 800ea88: f423 7340 bic.w r3, r3, #768 @ 0x300 800ea8c: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 800ea8e: 683b ldr r3, [r7, #0] 800ea90: 68db ldr r3, [r3, #12] 800ea92: 68fa ldr r2, [r7, #12] 800ea94: 4313 orrs r3, r2 800ea96: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 800ea98: 68fb ldr r3, [r7, #12] 800ea9a: f023 0280 bic.w r2, r3, #128 @ 0x80 800ea9e: 683b ldr r3, [r7, #0] 800eaa0: 695b ldr r3, [r3, #20] 800eaa2: 4313 orrs r3, r2 800eaa4: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 800eaa6: 687b ldr r3, [r7, #4] 800eaa8: 68fa ldr r2, [r7, #12] 800eaaa: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 800eaac: 683b ldr r3, [r7, #0] 800eaae: 689a ldr r2, [r3, #8] 800eab0: 687b ldr r3, [r7, #4] 800eab2: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 800eab4: 683b ldr r3, [r7, #0] 800eab6: 681a ldr r2, [r3, #0] 800eab8: 687b ldr r3, [r7, #4] 800eaba: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800eabc: 687b ldr r3, [r7, #4] 800eabe: 4a16 ldr r2, [pc, #88] @ (800eb18 ) 800eac0: 4293 cmp r3, r2 800eac2: d00f beq.n 800eae4 800eac4: 687b ldr r3, [r7, #4] 800eac6: 4a18 ldr r2, [pc, #96] @ (800eb28 ) 800eac8: 4293 cmp r3, r2 800eaca: d00b beq.n 800eae4 800eacc: 687b ldr r3, [r7, #4] 800eace: 4a17 ldr r2, [pc, #92] @ (800eb2c ) 800ead0: 4293 cmp r3, r2 800ead2: d007 beq.n 800eae4 800ead4: 687b ldr r3, [r7, #4] 800ead6: 4a16 ldr r2, [pc, #88] @ (800eb30 ) 800ead8: 4293 cmp r3, r2 800eada: d003 beq.n 800eae4 800eadc: 687b ldr r3, [r7, #4] 800eade: 4a15 ldr r2, [pc, #84] @ (800eb34 ) 800eae0: 4293 cmp r3, r2 800eae2: d103 bne.n 800eaec { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 800eae4: 683b ldr r3, [r7, #0] 800eae6: 691a ldr r2, [r3, #16] 800eae8: 687b ldr r3, [r7, #4] 800eaea: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 800eaec: 687b ldr r3, [r7, #4] 800eaee: 2201 movs r2, #1 800eaf0: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 800eaf2: 687b ldr r3, [r7, #4] 800eaf4: 691b ldr r3, [r3, #16] 800eaf6: f003 0301 and.w r3, r3, #1 800eafa: 2b01 cmp r3, #1 800eafc: d105 bne.n 800eb0a { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 800eafe: 687b ldr r3, [r7, #4] 800eb00: 691b ldr r3, [r3, #16] 800eb02: f023 0201 bic.w r2, r3, #1 800eb06: 687b ldr r3, [r7, #4] 800eb08: 611a str r2, [r3, #16] } } 800eb0a: bf00 nop 800eb0c: 3714 adds r7, #20 800eb0e: 46bd mov sp, r7 800eb10: f85d 7b04 ldr.w r7, [sp], #4 800eb14: 4770 bx lr 800eb16: bf00 nop 800eb18: 40010000 .word 0x40010000 800eb1c: 40000400 .word 0x40000400 800eb20: 40000800 .word 0x40000800 800eb24: 40000c00 .word 0x40000c00 800eb28: 40010400 .word 0x40010400 800eb2c: 40014000 .word 0x40014000 800eb30: 40014400 .word 0x40014400 800eb34: 40014800 .word 0x40014800 0800eb38 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800eb38: b480 push {r7} 800eb3a: b087 sub sp, #28 800eb3c: af00 add r7, sp, #0 800eb3e: 6078 str r0, [r7, #4] 800eb40: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800eb42: 687b ldr r3, [r7, #4] 800eb44: 6a1b ldr r3, [r3, #32] 800eb46: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 800eb48: 687b ldr r3, [r7, #4] 800eb4a: 6a1b ldr r3, [r3, #32] 800eb4c: f023 0201 bic.w r2, r3, #1 800eb50: 687b ldr r3, [r7, #4] 800eb52: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800eb54: 687b ldr r3, [r7, #4] 800eb56: 685b ldr r3, [r3, #4] 800eb58: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 800eb5a: 687b ldr r3, [r7, #4] 800eb5c: 699b ldr r3, [r3, #24] 800eb5e: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 800eb60: 68fa ldr r2, [r7, #12] 800eb62: 4b37 ldr r3, [pc, #220] @ (800ec40 ) 800eb64: 4013 ands r3, r2 800eb66: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 800eb68: 68fb ldr r3, [r7, #12] 800eb6a: f023 0303 bic.w r3, r3, #3 800eb6e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800eb70: 683b ldr r3, [r7, #0] 800eb72: 681b ldr r3, [r3, #0] 800eb74: 68fa ldr r2, [r7, #12] 800eb76: 4313 orrs r3, r2 800eb78: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 800eb7a: 697b ldr r3, [r7, #20] 800eb7c: f023 0302 bic.w r3, r3, #2 800eb80: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 800eb82: 683b ldr r3, [r7, #0] 800eb84: 689b ldr r3, [r3, #8] 800eb86: 697a ldr r2, [r7, #20] 800eb88: 4313 orrs r3, r2 800eb8a: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 800eb8c: 687b ldr r3, [r7, #4] 800eb8e: 4a2d ldr r2, [pc, #180] @ (800ec44 ) 800eb90: 4293 cmp r3, r2 800eb92: d00f beq.n 800ebb4 800eb94: 687b ldr r3, [r7, #4] 800eb96: 4a2c ldr r2, [pc, #176] @ (800ec48 ) 800eb98: 4293 cmp r3, r2 800eb9a: d00b beq.n 800ebb4 800eb9c: 687b ldr r3, [r7, #4] 800eb9e: 4a2b ldr r2, [pc, #172] @ (800ec4c ) 800eba0: 4293 cmp r3, r2 800eba2: d007 beq.n 800ebb4 800eba4: 687b ldr r3, [r7, #4] 800eba6: 4a2a ldr r2, [pc, #168] @ (800ec50 ) 800eba8: 4293 cmp r3, r2 800ebaa: d003 beq.n 800ebb4 800ebac: 687b ldr r3, [r7, #4] 800ebae: 4a29 ldr r2, [pc, #164] @ (800ec54 ) 800ebb0: 4293 cmp r3, r2 800ebb2: d10c bne.n 800ebce { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 800ebb4: 697b ldr r3, [r7, #20] 800ebb6: f023 0308 bic.w r3, r3, #8 800ebba: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 800ebbc: 683b ldr r3, [r7, #0] 800ebbe: 68db ldr r3, [r3, #12] 800ebc0: 697a ldr r2, [r7, #20] 800ebc2: 4313 orrs r3, r2 800ebc4: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 800ebc6: 697b ldr r3, [r7, #20] 800ebc8: f023 0304 bic.w r3, r3, #4 800ebcc: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800ebce: 687b ldr r3, [r7, #4] 800ebd0: 4a1c ldr r2, [pc, #112] @ (800ec44 ) 800ebd2: 4293 cmp r3, r2 800ebd4: d00f beq.n 800ebf6 800ebd6: 687b ldr r3, [r7, #4] 800ebd8: 4a1b ldr r2, [pc, #108] @ (800ec48 ) 800ebda: 4293 cmp r3, r2 800ebdc: d00b beq.n 800ebf6 800ebde: 687b ldr r3, [r7, #4] 800ebe0: 4a1a ldr r2, [pc, #104] @ (800ec4c ) 800ebe2: 4293 cmp r3, r2 800ebe4: d007 beq.n 800ebf6 800ebe6: 687b ldr r3, [r7, #4] 800ebe8: 4a19 ldr r2, [pc, #100] @ (800ec50 ) 800ebea: 4293 cmp r3, r2 800ebec: d003 beq.n 800ebf6 800ebee: 687b ldr r3, [r7, #4] 800ebf0: 4a18 ldr r2, [pc, #96] @ (800ec54 ) 800ebf2: 4293 cmp r3, r2 800ebf4: d111 bne.n 800ec1a /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 800ebf6: 693b ldr r3, [r7, #16] 800ebf8: f423 7380 bic.w r3, r3, #256 @ 0x100 800ebfc: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 800ebfe: 693b ldr r3, [r7, #16] 800ec00: f423 7300 bic.w r3, r3, #512 @ 0x200 800ec04: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 800ec06: 683b ldr r3, [r7, #0] 800ec08: 695b ldr r3, [r3, #20] 800ec0a: 693a ldr r2, [r7, #16] 800ec0c: 4313 orrs r3, r2 800ec0e: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 800ec10: 683b ldr r3, [r7, #0] 800ec12: 699b ldr r3, [r3, #24] 800ec14: 693a ldr r2, [r7, #16] 800ec16: 4313 orrs r3, r2 800ec18: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800ec1a: 687b ldr r3, [r7, #4] 800ec1c: 693a ldr r2, [r7, #16] 800ec1e: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800ec20: 687b ldr r3, [r7, #4] 800ec22: 68fa ldr r2, [r7, #12] 800ec24: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 800ec26: 683b ldr r3, [r7, #0] 800ec28: 685a ldr r2, [r3, #4] 800ec2a: 687b ldr r3, [r7, #4] 800ec2c: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800ec2e: 687b ldr r3, [r7, #4] 800ec30: 697a ldr r2, [r7, #20] 800ec32: 621a str r2, [r3, #32] } 800ec34: bf00 nop 800ec36: 371c adds r7, #28 800ec38: 46bd mov sp, r7 800ec3a: f85d 7b04 ldr.w r7, [sp], #4 800ec3e: 4770 bx lr 800ec40: fffeff8f .word 0xfffeff8f 800ec44: 40010000 .word 0x40010000 800ec48: 40010400 .word 0x40010400 800ec4c: 40014000 .word 0x40014000 800ec50: 40014400 .word 0x40014400 800ec54: 40014800 .word 0x40014800 0800ec58 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800ec58: b480 push {r7} 800ec5a: b087 sub sp, #28 800ec5c: af00 add r7, sp, #0 800ec5e: 6078 str r0, [r7, #4] 800ec60: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800ec62: 687b ldr r3, [r7, #4] 800ec64: 6a1b ldr r3, [r3, #32] 800ec66: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 800ec68: 687b ldr r3, [r7, #4] 800ec6a: 6a1b ldr r3, [r3, #32] 800ec6c: f023 0210 bic.w r2, r3, #16 800ec70: 687b ldr r3, [r7, #4] 800ec72: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800ec74: 687b ldr r3, [r7, #4] 800ec76: 685b ldr r3, [r3, #4] 800ec78: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 800ec7a: 687b ldr r3, [r7, #4] 800ec7c: 699b ldr r3, [r3, #24] 800ec7e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 800ec80: 68fa ldr r2, [r7, #12] 800ec82: 4b34 ldr r3, [pc, #208] @ (800ed54 ) 800ec84: 4013 ands r3, r2 800ec86: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 800ec88: 68fb ldr r3, [r7, #12] 800ec8a: f423 7340 bic.w r3, r3, #768 @ 0x300 800ec8e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 800ec90: 683b ldr r3, [r7, #0] 800ec92: 681b ldr r3, [r3, #0] 800ec94: 021b lsls r3, r3, #8 800ec96: 68fa ldr r2, [r7, #12] 800ec98: 4313 orrs r3, r2 800ec9a: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 800ec9c: 697b ldr r3, [r7, #20] 800ec9e: f023 0320 bic.w r3, r3, #32 800eca2: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 800eca4: 683b ldr r3, [r7, #0] 800eca6: 689b ldr r3, [r3, #8] 800eca8: 011b lsls r3, r3, #4 800ecaa: 697a ldr r2, [r7, #20] 800ecac: 4313 orrs r3, r2 800ecae: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 800ecb0: 687b ldr r3, [r7, #4] 800ecb2: 4a29 ldr r2, [pc, #164] @ (800ed58 ) 800ecb4: 4293 cmp r3, r2 800ecb6: d003 beq.n 800ecc0 800ecb8: 687b ldr r3, [r7, #4] 800ecba: 4a28 ldr r2, [pc, #160] @ (800ed5c ) 800ecbc: 4293 cmp r3, r2 800ecbe: d10d bne.n 800ecdc { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 800ecc0: 697b ldr r3, [r7, #20] 800ecc2: f023 0380 bic.w r3, r3, #128 @ 0x80 800ecc6: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 800ecc8: 683b ldr r3, [r7, #0] 800ecca: 68db ldr r3, [r3, #12] 800eccc: 011b lsls r3, r3, #4 800ecce: 697a ldr r2, [r7, #20] 800ecd0: 4313 orrs r3, r2 800ecd2: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 800ecd4: 697b ldr r3, [r7, #20] 800ecd6: f023 0340 bic.w r3, r3, #64 @ 0x40 800ecda: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800ecdc: 687b ldr r3, [r7, #4] 800ecde: 4a1e ldr r2, [pc, #120] @ (800ed58 ) 800ece0: 4293 cmp r3, r2 800ece2: d00f beq.n 800ed04 800ece4: 687b ldr r3, [r7, #4] 800ece6: 4a1d ldr r2, [pc, #116] @ (800ed5c ) 800ece8: 4293 cmp r3, r2 800ecea: d00b beq.n 800ed04 800ecec: 687b ldr r3, [r7, #4] 800ecee: 4a1c ldr r2, [pc, #112] @ (800ed60 ) 800ecf0: 4293 cmp r3, r2 800ecf2: d007 beq.n 800ed04 800ecf4: 687b ldr r3, [r7, #4] 800ecf6: 4a1b ldr r2, [pc, #108] @ (800ed64 ) 800ecf8: 4293 cmp r3, r2 800ecfa: d003 beq.n 800ed04 800ecfc: 687b ldr r3, [r7, #4] 800ecfe: 4a1a ldr r2, [pc, #104] @ (800ed68 ) 800ed00: 4293 cmp r3, r2 800ed02: d113 bne.n 800ed2c /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 800ed04: 693b ldr r3, [r7, #16] 800ed06: f423 6380 bic.w r3, r3, #1024 @ 0x400 800ed0a: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 800ed0c: 693b ldr r3, [r7, #16] 800ed0e: f423 6300 bic.w r3, r3, #2048 @ 0x800 800ed12: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 800ed14: 683b ldr r3, [r7, #0] 800ed16: 695b ldr r3, [r3, #20] 800ed18: 009b lsls r3, r3, #2 800ed1a: 693a ldr r2, [r7, #16] 800ed1c: 4313 orrs r3, r2 800ed1e: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 800ed20: 683b ldr r3, [r7, #0] 800ed22: 699b ldr r3, [r3, #24] 800ed24: 009b lsls r3, r3, #2 800ed26: 693a ldr r2, [r7, #16] 800ed28: 4313 orrs r3, r2 800ed2a: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800ed2c: 687b ldr r3, [r7, #4] 800ed2e: 693a ldr r2, [r7, #16] 800ed30: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800ed32: 687b ldr r3, [r7, #4] 800ed34: 68fa ldr r2, [r7, #12] 800ed36: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 800ed38: 683b ldr r3, [r7, #0] 800ed3a: 685a ldr r2, [r3, #4] 800ed3c: 687b ldr r3, [r7, #4] 800ed3e: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800ed40: 687b ldr r3, [r7, #4] 800ed42: 697a ldr r2, [r7, #20] 800ed44: 621a str r2, [r3, #32] } 800ed46: bf00 nop 800ed48: 371c adds r7, #28 800ed4a: 46bd mov sp, r7 800ed4c: f85d 7b04 ldr.w r7, [sp], #4 800ed50: 4770 bx lr 800ed52: bf00 nop 800ed54: feff8fff .word 0xfeff8fff 800ed58: 40010000 .word 0x40010000 800ed5c: 40010400 .word 0x40010400 800ed60: 40014000 .word 0x40014000 800ed64: 40014400 .word 0x40014400 800ed68: 40014800 .word 0x40014800 0800ed6c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800ed6c: b480 push {r7} 800ed6e: b087 sub sp, #28 800ed70: af00 add r7, sp, #0 800ed72: 6078 str r0, [r7, #4] 800ed74: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800ed76: 687b ldr r3, [r7, #4] 800ed78: 6a1b ldr r3, [r3, #32] 800ed7a: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 800ed7c: 687b ldr r3, [r7, #4] 800ed7e: 6a1b ldr r3, [r3, #32] 800ed80: f423 7280 bic.w r2, r3, #256 @ 0x100 800ed84: 687b ldr r3, [r7, #4] 800ed86: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800ed88: 687b ldr r3, [r7, #4] 800ed8a: 685b ldr r3, [r3, #4] 800ed8c: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 800ed8e: 687b ldr r3, [r7, #4] 800ed90: 69db ldr r3, [r3, #28] 800ed92: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 800ed94: 68fa ldr r2, [r7, #12] 800ed96: 4b33 ldr r3, [pc, #204] @ (800ee64 ) 800ed98: 4013 ands r3, r2 800ed9a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 800ed9c: 68fb ldr r3, [r7, #12] 800ed9e: f023 0303 bic.w r3, r3, #3 800eda2: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800eda4: 683b ldr r3, [r7, #0] 800eda6: 681b ldr r3, [r3, #0] 800eda8: 68fa ldr r2, [r7, #12] 800edaa: 4313 orrs r3, r2 800edac: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 800edae: 697b ldr r3, [r7, #20] 800edb0: f423 7300 bic.w r3, r3, #512 @ 0x200 800edb4: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 800edb6: 683b ldr r3, [r7, #0] 800edb8: 689b ldr r3, [r3, #8] 800edba: 021b lsls r3, r3, #8 800edbc: 697a ldr r2, [r7, #20] 800edbe: 4313 orrs r3, r2 800edc0: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 800edc2: 687b ldr r3, [r7, #4] 800edc4: 4a28 ldr r2, [pc, #160] @ (800ee68 ) 800edc6: 4293 cmp r3, r2 800edc8: d003 beq.n 800edd2 800edca: 687b ldr r3, [r7, #4] 800edcc: 4a27 ldr r2, [pc, #156] @ (800ee6c ) 800edce: 4293 cmp r3, r2 800edd0: d10d bne.n 800edee { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 800edd2: 697b ldr r3, [r7, #20] 800edd4: f423 6300 bic.w r3, r3, #2048 @ 0x800 800edd8: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 800edda: 683b ldr r3, [r7, #0] 800eddc: 68db ldr r3, [r3, #12] 800edde: 021b lsls r3, r3, #8 800ede0: 697a ldr r2, [r7, #20] 800ede2: 4313 orrs r3, r2 800ede4: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 800ede6: 697b ldr r3, [r7, #20] 800ede8: f423 6380 bic.w r3, r3, #1024 @ 0x400 800edec: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800edee: 687b ldr r3, [r7, #4] 800edf0: 4a1d ldr r2, [pc, #116] @ (800ee68 ) 800edf2: 4293 cmp r3, r2 800edf4: d00f beq.n 800ee16 800edf6: 687b ldr r3, [r7, #4] 800edf8: 4a1c ldr r2, [pc, #112] @ (800ee6c ) 800edfa: 4293 cmp r3, r2 800edfc: d00b beq.n 800ee16 800edfe: 687b ldr r3, [r7, #4] 800ee00: 4a1b ldr r2, [pc, #108] @ (800ee70 ) 800ee02: 4293 cmp r3, r2 800ee04: d007 beq.n 800ee16 800ee06: 687b ldr r3, [r7, #4] 800ee08: 4a1a ldr r2, [pc, #104] @ (800ee74 ) 800ee0a: 4293 cmp r3, r2 800ee0c: d003 beq.n 800ee16 800ee0e: 687b ldr r3, [r7, #4] 800ee10: 4a19 ldr r2, [pc, #100] @ (800ee78 ) 800ee12: 4293 cmp r3, r2 800ee14: d113 bne.n 800ee3e /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 800ee16: 693b ldr r3, [r7, #16] 800ee18: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800ee1c: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 800ee1e: 693b ldr r3, [r7, #16] 800ee20: f423 5300 bic.w r3, r3, #8192 @ 0x2000 800ee24: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 800ee26: 683b ldr r3, [r7, #0] 800ee28: 695b ldr r3, [r3, #20] 800ee2a: 011b lsls r3, r3, #4 800ee2c: 693a ldr r2, [r7, #16] 800ee2e: 4313 orrs r3, r2 800ee30: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 800ee32: 683b ldr r3, [r7, #0] 800ee34: 699b ldr r3, [r3, #24] 800ee36: 011b lsls r3, r3, #4 800ee38: 693a ldr r2, [r7, #16] 800ee3a: 4313 orrs r3, r2 800ee3c: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800ee3e: 687b ldr r3, [r7, #4] 800ee40: 693a ldr r2, [r7, #16] 800ee42: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 800ee44: 687b ldr r3, [r7, #4] 800ee46: 68fa ldr r2, [r7, #12] 800ee48: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 800ee4a: 683b ldr r3, [r7, #0] 800ee4c: 685a ldr r2, [r3, #4] 800ee4e: 687b ldr r3, [r7, #4] 800ee50: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800ee52: 687b ldr r3, [r7, #4] 800ee54: 697a ldr r2, [r7, #20] 800ee56: 621a str r2, [r3, #32] } 800ee58: bf00 nop 800ee5a: 371c adds r7, #28 800ee5c: 46bd mov sp, r7 800ee5e: f85d 7b04 ldr.w r7, [sp], #4 800ee62: 4770 bx lr 800ee64: fffeff8f .word 0xfffeff8f 800ee68: 40010000 .word 0x40010000 800ee6c: 40010400 .word 0x40010400 800ee70: 40014000 .word 0x40014000 800ee74: 40014400 .word 0x40014400 800ee78: 40014800 .word 0x40014800 0800ee7c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800ee7c: b480 push {r7} 800ee7e: b087 sub sp, #28 800ee80: af00 add r7, sp, #0 800ee82: 6078 str r0, [r7, #4] 800ee84: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800ee86: 687b ldr r3, [r7, #4] 800ee88: 6a1b ldr r3, [r3, #32] 800ee8a: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 800ee8c: 687b ldr r3, [r7, #4] 800ee8e: 6a1b ldr r3, [r3, #32] 800ee90: f423 5280 bic.w r2, r3, #4096 @ 0x1000 800ee94: 687b ldr r3, [r7, #4] 800ee96: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800ee98: 687b ldr r3, [r7, #4] 800ee9a: 685b ldr r3, [r3, #4] 800ee9c: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 800ee9e: 687b ldr r3, [r7, #4] 800eea0: 69db ldr r3, [r3, #28] 800eea2: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 800eea4: 68fa ldr r2, [r7, #12] 800eea6: 4b24 ldr r3, [pc, #144] @ (800ef38 ) 800eea8: 4013 ands r3, r2 800eeaa: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 800eeac: 68fb ldr r3, [r7, #12] 800eeae: f423 7340 bic.w r3, r3, #768 @ 0x300 800eeb2: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 800eeb4: 683b ldr r3, [r7, #0] 800eeb6: 681b ldr r3, [r3, #0] 800eeb8: 021b lsls r3, r3, #8 800eeba: 68fa ldr r2, [r7, #12] 800eebc: 4313 orrs r3, r2 800eebe: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 800eec0: 693b ldr r3, [r7, #16] 800eec2: f423 5300 bic.w r3, r3, #8192 @ 0x2000 800eec6: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 800eec8: 683b ldr r3, [r7, #0] 800eeca: 689b ldr r3, [r3, #8] 800eecc: 031b lsls r3, r3, #12 800eece: 693a ldr r2, [r7, #16] 800eed0: 4313 orrs r3, r2 800eed2: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 800eed4: 687b ldr r3, [r7, #4] 800eed6: 4a19 ldr r2, [pc, #100] @ (800ef3c ) 800eed8: 4293 cmp r3, r2 800eeda: d00f beq.n 800eefc 800eedc: 687b ldr r3, [r7, #4] 800eede: 4a18 ldr r2, [pc, #96] @ (800ef40 ) 800eee0: 4293 cmp r3, r2 800eee2: d00b beq.n 800eefc 800eee4: 687b ldr r3, [r7, #4] 800eee6: 4a17 ldr r2, [pc, #92] @ (800ef44 ) 800eee8: 4293 cmp r3, r2 800eeea: d007 beq.n 800eefc 800eeec: 687b ldr r3, [r7, #4] 800eeee: 4a16 ldr r2, [pc, #88] @ (800ef48 ) 800eef0: 4293 cmp r3, r2 800eef2: d003 beq.n 800eefc 800eef4: 687b ldr r3, [r7, #4] 800eef6: 4a15 ldr r2, [pc, #84] @ (800ef4c ) 800eef8: 4293 cmp r3, r2 800eefa: d109 bne.n 800ef10 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 800eefc: 697b ldr r3, [r7, #20] 800eefe: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800ef02: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 800ef04: 683b ldr r3, [r7, #0] 800ef06: 695b ldr r3, [r3, #20] 800ef08: 019b lsls r3, r3, #6 800ef0a: 697a ldr r2, [r7, #20] 800ef0c: 4313 orrs r3, r2 800ef0e: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800ef10: 687b ldr r3, [r7, #4] 800ef12: 697a ldr r2, [r7, #20] 800ef14: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 800ef16: 687b ldr r3, [r7, #4] 800ef18: 68fa ldr r2, [r7, #12] 800ef1a: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 800ef1c: 683b ldr r3, [r7, #0] 800ef1e: 685a ldr r2, [r3, #4] 800ef20: 687b ldr r3, [r7, #4] 800ef22: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800ef24: 687b ldr r3, [r7, #4] 800ef26: 693a ldr r2, [r7, #16] 800ef28: 621a str r2, [r3, #32] } 800ef2a: bf00 nop 800ef2c: 371c adds r7, #28 800ef2e: 46bd mov sp, r7 800ef30: f85d 7b04 ldr.w r7, [sp], #4 800ef34: 4770 bx lr 800ef36: bf00 nop 800ef38: feff8fff .word 0xfeff8fff 800ef3c: 40010000 .word 0x40010000 800ef40: 40010400 .word 0x40010400 800ef44: 40014000 .word 0x40014000 800ef48: 40014400 .word 0x40014400 800ef4c: 40014800 .word 0x40014800 0800ef50 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800ef50: b480 push {r7} 800ef52: b087 sub sp, #28 800ef54: af00 add r7, sp, #0 800ef56: 6078 str r0, [r7, #4] 800ef58: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800ef5a: 687b ldr r3, [r7, #4] 800ef5c: 6a1b ldr r3, [r3, #32] 800ef5e: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; 800ef60: 687b ldr r3, [r7, #4] 800ef62: 6a1b ldr r3, [r3, #32] 800ef64: f423 3280 bic.w r2, r3, #65536 @ 0x10000 800ef68: 687b ldr r3, [r7, #4] 800ef6a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800ef6c: 687b ldr r3, [r7, #4] 800ef6e: 685b ldr r3, [r3, #4] 800ef70: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 800ef72: 687b ldr r3, [r7, #4] 800ef74: 6d5b ldr r3, [r3, #84] @ 0x54 800ef76: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); 800ef78: 68fa ldr r2, [r7, #12] 800ef7a: 4b21 ldr r3, [pc, #132] @ (800f000 ) 800ef7c: 4013 ands r3, r2 800ef7e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800ef80: 683b ldr r3, [r7, #0] 800ef82: 681b ldr r3, [r3, #0] 800ef84: 68fa ldr r2, [r7, #12] 800ef86: 4313 orrs r3, r2 800ef88: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; 800ef8a: 693b ldr r3, [r7, #16] 800ef8c: f423 3300 bic.w r3, r3, #131072 @ 0x20000 800ef90: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); 800ef92: 683b ldr r3, [r7, #0] 800ef94: 689b ldr r3, [r3, #8] 800ef96: 041b lsls r3, r3, #16 800ef98: 693a ldr r2, [r7, #16] 800ef9a: 4313 orrs r3, r2 800ef9c: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 800ef9e: 687b ldr r3, [r7, #4] 800efa0: 4a18 ldr r2, [pc, #96] @ (800f004 ) 800efa2: 4293 cmp r3, r2 800efa4: d00f beq.n 800efc6 800efa6: 687b ldr r3, [r7, #4] 800efa8: 4a17 ldr r2, [pc, #92] @ (800f008 ) 800efaa: 4293 cmp r3, r2 800efac: d00b beq.n 800efc6 800efae: 687b ldr r3, [r7, #4] 800efb0: 4a16 ldr r2, [pc, #88] @ (800f00c ) 800efb2: 4293 cmp r3, r2 800efb4: d007 beq.n 800efc6 800efb6: 687b ldr r3, [r7, #4] 800efb8: 4a15 ldr r2, [pc, #84] @ (800f010 ) 800efba: 4293 cmp r3, r2 800efbc: d003 beq.n 800efc6 800efbe: 687b ldr r3, [r7, #4] 800efc0: 4a14 ldr r2, [pc, #80] @ (800f014 ) 800efc2: 4293 cmp r3, r2 800efc4: d109 bne.n 800efda { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; 800efc6: 697b ldr r3, [r7, #20] 800efc8: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800efcc: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); 800efce: 683b ldr r3, [r7, #0] 800efd0: 695b ldr r3, [r3, #20] 800efd2: 021b lsls r3, r3, #8 800efd4: 697a ldr r2, [r7, #20] 800efd6: 4313 orrs r3, r2 800efd8: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800efda: 687b ldr r3, [r7, #4] 800efdc: 697a ldr r2, [r7, #20] 800efde: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 800efe0: 687b ldr r3, [r7, #4] 800efe2: 68fa ldr r2, [r7, #12] 800efe4: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; 800efe6: 683b ldr r3, [r7, #0] 800efe8: 685a ldr r2, [r3, #4] 800efea: 687b ldr r3, [r7, #4] 800efec: 659a str r2, [r3, #88] @ 0x58 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800efee: 687b ldr r3, [r7, #4] 800eff0: 693a ldr r2, [r7, #16] 800eff2: 621a str r2, [r3, #32] } 800eff4: bf00 nop 800eff6: 371c adds r7, #28 800eff8: 46bd mov sp, r7 800effa: f85d 7b04 ldr.w r7, [sp], #4 800effe: 4770 bx lr 800f000: fffeff8f .word 0xfffeff8f 800f004: 40010000 .word 0x40010000 800f008: 40010400 .word 0x40010400 800f00c: 40014000 .word 0x40014000 800f010: 40014400 .word 0x40014400 800f014: 40014800 .word 0x40014800 0800f018 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800f018: b480 push {r7} 800f01a: b087 sub sp, #28 800f01c: af00 add r7, sp, #0 800f01e: 6078 str r0, [r7, #4] 800f020: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800f022: 687b ldr r3, [r7, #4] 800f024: 6a1b ldr r3, [r3, #32] 800f026: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; 800f028: 687b ldr r3, [r7, #4] 800f02a: 6a1b ldr r3, [r3, #32] 800f02c: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 800f030: 687b ldr r3, [r7, #4] 800f032: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800f034: 687b ldr r3, [r7, #4] 800f036: 685b ldr r3, [r3, #4] 800f038: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 800f03a: 687b ldr r3, [r7, #4] 800f03c: 6d5b ldr r3, [r3, #84] @ 0x54 800f03e: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); 800f040: 68fa ldr r2, [r7, #12] 800f042: 4b22 ldr r3, [pc, #136] @ (800f0cc ) 800f044: 4013 ands r3, r2 800f046: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 800f048: 683b ldr r3, [r7, #0] 800f04a: 681b ldr r3, [r3, #0] 800f04c: 021b lsls r3, r3, #8 800f04e: 68fa ldr r2, [r7, #12] 800f050: 4313 orrs r3, r2 800f052: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; 800f054: 693b ldr r3, [r7, #16] 800f056: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 800f05a: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); 800f05c: 683b ldr r3, [r7, #0] 800f05e: 689b ldr r3, [r3, #8] 800f060: 051b lsls r3, r3, #20 800f062: 693a ldr r2, [r7, #16] 800f064: 4313 orrs r3, r2 800f066: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 800f068: 687b ldr r3, [r7, #4] 800f06a: 4a19 ldr r2, [pc, #100] @ (800f0d0 ) 800f06c: 4293 cmp r3, r2 800f06e: d00f beq.n 800f090 800f070: 687b ldr r3, [r7, #4] 800f072: 4a18 ldr r2, [pc, #96] @ (800f0d4 ) 800f074: 4293 cmp r3, r2 800f076: d00b beq.n 800f090 800f078: 687b ldr r3, [r7, #4] 800f07a: 4a17 ldr r2, [pc, #92] @ (800f0d8 ) 800f07c: 4293 cmp r3, r2 800f07e: d007 beq.n 800f090 800f080: 687b ldr r3, [r7, #4] 800f082: 4a16 ldr r2, [pc, #88] @ (800f0dc ) 800f084: 4293 cmp r3, r2 800f086: d003 beq.n 800f090 800f088: 687b ldr r3, [r7, #4] 800f08a: 4a15 ldr r2, [pc, #84] @ (800f0e0 ) 800f08c: 4293 cmp r3, r2 800f08e: d109 bne.n 800f0a4 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; 800f090: 697b ldr r3, [r7, #20] 800f092: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800f096: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); 800f098: 683b ldr r3, [r7, #0] 800f09a: 695b ldr r3, [r3, #20] 800f09c: 029b lsls r3, r3, #10 800f09e: 697a ldr r2, [r7, #20] 800f0a0: 4313 orrs r3, r2 800f0a2: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800f0a4: 687b ldr r3, [r7, #4] 800f0a6: 697a ldr r2, [r7, #20] 800f0a8: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 800f0aa: 687b ldr r3, [r7, #4] 800f0ac: 68fa ldr r2, [r7, #12] 800f0ae: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; 800f0b0: 683b ldr r3, [r7, #0] 800f0b2: 685a ldr r2, [r3, #4] 800f0b4: 687b ldr r3, [r7, #4] 800f0b6: 65da str r2, [r3, #92] @ 0x5c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800f0b8: 687b ldr r3, [r7, #4] 800f0ba: 693a ldr r2, [r7, #16] 800f0bc: 621a str r2, [r3, #32] } 800f0be: bf00 nop 800f0c0: 371c adds r7, #28 800f0c2: 46bd mov sp, r7 800f0c4: f85d 7b04 ldr.w r7, [sp], #4 800f0c8: 4770 bx lr 800f0ca: bf00 nop 800f0cc: feff8fff .word 0xfeff8fff 800f0d0: 40010000 .word 0x40010000 800f0d4: 40010400 .word 0x40010400 800f0d8: 40014000 .word 0x40014000 800f0dc: 40014400 .word 0x40014400 800f0e0: 40014800 .word 0x40014800 0800f0e4 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 800f0e4: b480 push {r7} 800f0e6: b087 sub sp, #28 800f0e8: af00 add r7, sp, #0 800f0ea: 60f8 str r0, [r7, #12] 800f0ec: 60b9 str r1, [r7, #8] 800f0ee: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 800f0f0: 68fb ldr r3, [r7, #12] 800f0f2: 6a1b ldr r3, [r3, #32] 800f0f4: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 800f0f6: 68fb ldr r3, [r7, #12] 800f0f8: 6a1b ldr r3, [r3, #32] 800f0fa: f023 0201 bic.w r2, r3, #1 800f0fe: 68fb ldr r3, [r7, #12] 800f100: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 800f102: 68fb ldr r3, [r7, #12] 800f104: 699b ldr r3, [r3, #24] 800f106: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 800f108: 693b ldr r3, [r7, #16] 800f10a: f023 03f0 bic.w r3, r3, #240 @ 0xf0 800f10e: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 800f110: 687b ldr r3, [r7, #4] 800f112: 011b lsls r3, r3, #4 800f114: 693a ldr r2, [r7, #16] 800f116: 4313 orrs r3, r2 800f118: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 800f11a: 697b ldr r3, [r7, #20] 800f11c: f023 030a bic.w r3, r3, #10 800f120: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 800f122: 697a ldr r2, [r7, #20] 800f124: 68bb ldr r3, [r7, #8] 800f126: 4313 orrs r3, r2 800f128: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 800f12a: 68fb ldr r3, [r7, #12] 800f12c: 693a ldr r2, [r7, #16] 800f12e: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 800f130: 68fb ldr r3, [r7, #12] 800f132: 697a ldr r2, [r7, #20] 800f134: 621a str r2, [r3, #32] } 800f136: bf00 nop 800f138: 371c adds r7, #28 800f13a: 46bd mov sp, r7 800f13c: f85d 7b04 ldr.w r7, [sp], #4 800f140: 4770 bx lr 0800f142 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 800f142: b480 push {r7} 800f144: b087 sub sp, #28 800f146: af00 add r7, sp, #0 800f148: 60f8 str r0, [r7, #12] 800f14a: 60b9 str r1, [r7, #8] 800f14c: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 800f14e: 68fb ldr r3, [r7, #12] 800f150: 6a1b ldr r3, [r3, #32] 800f152: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 800f154: 68fb ldr r3, [r7, #12] 800f156: 6a1b ldr r3, [r3, #32] 800f158: f023 0210 bic.w r2, r3, #16 800f15c: 68fb ldr r3, [r7, #12] 800f15e: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 800f160: 68fb ldr r3, [r7, #12] 800f162: 699b ldr r3, [r3, #24] 800f164: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 800f166: 693b ldr r3, [r7, #16] 800f168: f423 4370 bic.w r3, r3, #61440 @ 0xf000 800f16c: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 800f16e: 687b ldr r3, [r7, #4] 800f170: 031b lsls r3, r3, #12 800f172: 693a ldr r2, [r7, #16] 800f174: 4313 orrs r3, r2 800f176: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 800f178: 697b ldr r3, [r7, #20] 800f17a: f023 03a0 bic.w r3, r3, #160 @ 0xa0 800f17e: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 800f180: 68bb ldr r3, [r7, #8] 800f182: 011b lsls r3, r3, #4 800f184: 697a ldr r2, [r7, #20] 800f186: 4313 orrs r3, r2 800f188: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 800f18a: 68fb ldr r3, [r7, #12] 800f18c: 693a ldr r2, [r7, #16] 800f18e: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 800f190: 68fb ldr r3, [r7, #12] 800f192: 697a ldr r2, [r7, #20] 800f194: 621a str r2, [r3, #32] } 800f196: bf00 nop 800f198: 371c adds r7, #28 800f19a: 46bd mov sp, r7 800f19c: f85d 7b04 ldr.w r7, [sp], #4 800f1a0: 4770 bx lr ... 0800f1a4 : * (*) Value not defined in all devices. * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 800f1a4: b480 push {r7} 800f1a6: b085 sub sp, #20 800f1a8: af00 add r7, sp, #0 800f1aa: 6078 str r0, [r7, #4] 800f1ac: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 800f1ae: 687b ldr r3, [r7, #4] 800f1b0: 689b ldr r3, [r3, #8] 800f1b2: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 800f1b4: 68fa ldr r2, [r7, #12] 800f1b6: 4b09 ldr r3, [pc, #36] @ (800f1dc ) 800f1b8: 4013 ands r3, r2 800f1ba: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 800f1bc: 683a ldr r2, [r7, #0] 800f1be: 68fb ldr r3, [r7, #12] 800f1c0: 4313 orrs r3, r2 800f1c2: f043 0307 orr.w r3, r3, #7 800f1c6: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 800f1c8: 687b ldr r3, [r7, #4] 800f1ca: 68fa ldr r2, [r7, #12] 800f1cc: 609a str r2, [r3, #8] } 800f1ce: bf00 nop 800f1d0: 3714 adds r7, #20 800f1d2: 46bd mov sp, r7 800f1d4: f85d 7b04 ldr.w r7, [sp], #4 800f1d8: 4770 bx lr 800f1da: bf00 nop 800f1dc: ffcfff8f .word 0xffcfff8f 0800f1e0 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 800f1e0: b480 push {r7} 800f1e2: b087 sub sp, #28 800f1e4: af00 add r7, sp, #0 800f1e6: 60f8 str r0, [r7, #12] 800f1e8: 60b9 str r1, [r7, #8] 800f1ea: 607a str r2, [r7, #4] 800f1ec: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 800f1ee: 68fb ldr r3, [r7, #12] 800f1f0: 689b ldr r3, [r3, #8] 800f1f2: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 800f1f4: 697b ldr r3, [r7, #20] 800f1f6: f423 437f bic.w r3, r3, #65280 @ 0xff00 800f1fa: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 800f1fc: 683b ldr r3, [r7, #0] 800f1fe: 021a lsls r2, r3, #8 800f200: 687b ldr r3, [r7, #4] 800f202: 431a orrs r2, r3 800f204: 68bb ldr r3, [r7, #8] 800f206: 4313 orrs r3, r2 800f208: 697a ldr r2, [r7, #20] 800f20a: 4313 orrs r3, r2 800f20c: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 800f20e: 68fb ldr r3, [r7, #12] 800f210: 697a ldr r2, [r7, #20] 800f212: 609a str r2, [r3, #8] } 800f214: bf00 nop 800f216: 371c adds r7, #28 800f218: 46bd mov sp, r7 800f21a: f85d 7b04 ldr.w r7, [sp], #4 800f21e: 4770 bx lr 0800f220 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 800f220: b480 push {r7} 800f222: b087 sub sp, #28 800f224: af00 add r7, sp, #0 800f226: 60f8 str r0, [r7, #12] 800f228: 60b9 str r1, [r7, #8] 800f22a: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 800f22c: 68bb ldr r3, [r7, #8] 800f22e: f003 031f and.w r3, r3, #31 800f232: 2201 movs r2, #1 800f234: fa02 f303 lsl.w r3, r2, r3 800f238: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 800f23a: 68fb ldr r3, [r7, #12] 800f23c: 6a1a ldr r2, [r3, #32] 800f23e: 697b ldr r3, [r7, #20] 800f240: 43db mvns r3, r3 800f242: 401a ands r2, r3 800f244: 68fb ldr r3, [r7, #12] 800f246: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 800f248: 68fb ldr r3, [r7, #12] 800f24a: 6a1a ldr r2, [r3, #32] 800f24c: 68bb ldr r3, [r7, #8] 800f24e: f003 031f and.w r3, r3, #31 800f252: 6879 ldr r1, [r7, #4] 800f254: fa01 f303 lsl.w r3, r1, r3 800f258: 431a orrs r2, r3 800f25a: 68fb ldr r3, [r7, #12] 800f25c: 621a str r2, [r3, #32] } 800f25e: bf00 nop 800f260: 371c adds r7, #28 800f262: 46bd mov sp, r7 800f264: f85d 7b04 ldr.w r7, [sp], #4 800f268: 4770 bx lr ... 0800f26c : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 800f26c: b480 push {r7} 800f26e: b085 sub sp, #20 800f270: af00 add r7, sp, #0 800f272: 6078 str r0, [r7, #4] 800f274: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 800f276: 687b ldr r3, [r7, #4] 800f278: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800f27c: 2b01 cmp r3, #1 800f27e: d101 bne.n 800f284 800f280: 2302 movs r3, #2 800f282: e06d b.n 800f360 800f284: 687b ldr r3, [r7, #4] 800f286: 2201 movs r2, #1 800f288: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 800f28c: 687b ldr r3, [r7, #4] 800f28e: 2202 movs r2, #2 800f290: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 800f294: 687b ldr r3, [r7, #4] 800f296: 681b ldr r3, [r3, #0] 800f298: 685b ldr r3, [r3, #4] 800f29a: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 800f29c: 687b ldr r3, [r7, #4] 800f29e: 681b ldr r3, [r3, #0] 800f2a0: 689b ldr r3, [r3, #8] 800f2a2: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 800f2a4: 687b ldr r3, [r7, #4] 800f2a6: 681b ldr r3, [r3, #0] 800f2a8: 4a30 ldr r2, [pc, #192] @ (800f36c ) 800f2aa: 4293 cmp r3, r2 800f2ac: d004 beq.n 800f2b8 800f2ae: 687b ldr r3, [r7, #4] 800f2b0: 681b ldr r3, [r3, #0] 800f2b2: 4a2f ldr r2, [pc, #188] @ (800f370 ) 800f2b4: 4293 cmp r3, r2 800f2b6: d108 bne.n 800f2ca { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 800f2b8: 68fb ldr r3, [r7, #12] 800f2ba: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 800f2be: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 800f2c0: 683b ldr r3, [r7, #0] 800f2c2: 685b ldr r3, [r3, #4] 800f2c4: 68fa ldr r2, [r7, #12] 800f2c6: 4313 orrs r3, r2 800f2c8: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 800f2ca: 68fb ldr r3, [r7, #12] 800f2cc: f023 0370 bic.w r3, r3, #112 @ 0x70 800f2d0: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 800f2d2: 683b ldr r3, [r7, #0] 800f2d4: 681b ldr r3, [r3, #0] 800f2d6: 68fa ldr r2, [r7, #12] 800f2d8: 4313 orrs r3, r2 800f2da: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 800f2dc: 687b ldr r3, [r7, #4] 800f2de: 681b ldr r3, [r3, #0] 800f2e0: 68fa ldr r2, [r7, #12] 800f2e2: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f2e4: 687b ldr r3, [r7, #4] 800f2e6: 681b ldr r3, [r3, #0] 800f2e8: 4a20 ldr r2, [pc, #128] @ (800f36c ) 800f2ea: 4293 cmp r3, r2 800f2ec: d022 beq.n 800f334 800f2ee: 687b ldr r3, [r7, #4] 800f2f0: 681b ldr r3, [r3, #0] 800f2f2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f2f6: d01d beq.n 800f334 800f2f8: 687b ldr r3, [r7, #4] 800f2fa: 681b ldr r3, [r3, #0] 800f2fc: 4a1d ldr r2, [pc, #116] @ (800f374 ) 800f2fe: 4293 cmp r3, r2 800f300: d018 beq.n 800f334 800f302: 687b ldr r3, [r7, #4] 800f304: 681b ldr r3, [r3, #0] 800f306: 4a1c ldr r2, [pc, #112] @ (800f378 ) 800f308: 4293 cmp r3, r2 800f30a: d013 beq.n 800f334 800f30c: 687b ldr r3, [r7, #4] 800f30e: 681b ldr r3, [r3, #0] 800f310: 4a1a ldr r2, [pc, #104] @ (800f37c ) 800f312: 4293 cmp r3, r2 800f314: d00e beq.n 800f334 800f316: 687b ldr r3, [r7, #4] 800f318: 681b ldr r3, [r3, #0] 800f31a: 4a15 ldr r2, [pc, #84] @ (800f370 ) 800f31c: 4293 cmp r3, r2 800f31e: d009 beq.n 800f334 800f320: 687b ldr r3, [r7, #4] 800f322: 681b ldr r3, [r3, #0] 800f324: 4a16 ldr r2, [pc, #88] @ (800f380 ) 800f326: 4293 cmp r3, r2 800f328: d004 beq.n 800f334 800f32a: 687b ldr r3, [r7, #4] 800f32c: 681b ldr r3, [r3, #0] 800f32e: 4a15 ldr r2, [pc, #84] @ (800f384 ) 800f330: 4293 cmp r3, r2 800f332: d10c bne.n 800f34e { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 800f334: 68bb ldr r3, [r7, #8] 800f336: f023 0380 bic.w r3, r3, #128 @ 0x80 800f33a: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 800f33c: 683b ldr r3, [r7, #0] 800f33e: 689b ldr r3, [r3, #8] 800f340: 68ba ldr r2, [r7, #8] 800f342: 4313 orrs r3, r2 800f344: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800f346: 687b ldr r3, [r7, #4] 800f348: 681b ldr r3, [r3, #0] 800f34a: 68ba ldr r2, [r7, #8] 800f34c: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 800f34e: 687b ldr r3, [r7, #4] 800f350: 2201 movs r2, #1 800f352: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 800f356: 687b ldr r3, [r7, #4] 800f358: 2200 movs r2, #0 800f35a: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 800f35e: 2300 movs r3, #0 } 800f360: 4618 mov r0, r3 800f362: 3714 adds r7, #20 800f364: 46bd mov sp, r7 800f366: f85d 7b04 ldr.w r7, [sp], #4 800f36a: 4770 bx lr 800f36c: 40010000 .word 0x40010000 800f370: 40010400 .word 0x40010400 800f374: 40000400 .word 0x40000400 800f378: 40000800 .word 0x40000800 800f37c: 40000c00 .word 0x40000c00 800f380: 40001800 .word 0x40001800 800f384: 40014000 .word 0x40014000 0800f388 : * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { 800f388: b480 push {r7} 800f38a: b085 sub sp, #20 800f38c: af00 add r7, sp, #0 800f38e: 6078 str r0, [r7, #4] 800f390: 6039 str r1, [r7, #0] /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; 800f392: 2300 movs r3, #0 800f394: 60fb str r3, [r7, #12] #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); #endif /* TIM_BDTR_BKBID */ /* Check input state */ __HAL_LOCK(htim); 800f396: 687b ldr r3, [r7, #4] 800f398: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800f39c: 2b01 cmp r3, #1 800f39e: d101 bne.n 800f3a4 800f3a0: 2302 movs r3, #2 800f3a2: e065 b.n 800f470 800f3a4: 687b ldr r3, [r7, #4] 800f3a6: 2201 movs r2, #1 800f3a8: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); 800f3ac: 68fb ldr r3, [r7, #12] 800f3ae: f023 02ff bic.w r2, r3, #255 @ 0xff 800f3b2: 683b ldr r3, [r7, #0] 800f3b4: 68db ldr r3, [r3, #12] 800f3b6: 4313 orrs r3, r2 800f3b8: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); 800f3ba: 68fb ldr r3, [r7, #12] 800f3bc: f423 7240 bic.w r2, r3, #768 @ 0x300 800f3c0: 683b ldr r3, [r7, #0] 800f3c2: 689b ldr r3, [r3, #8] 800f3c4: 4313 orrs r3, r2 800f3c6: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 800f3c8: 68fb ldr r3, [r7, #12] 800f3ca: f423 6280 bic.w r2, r3, #1024 @ 0x400 800f3ce: 683b ldr r3, [r7, #0] 800f3d0: 685b ldr r3, [r3, #4] 800f3d2: 4313 orrs r3, r2 800f3d4: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 800f3d6: 68fb ldr r3, [r7, #12] 800f3d8: f423 6200 bic.w r2, r3, #2048 @ 0x800 800f3dc: 683b ldr r3, [r7, #0] 800f3de: 681b ldr r3, [r3, #0] 800f3e0: 4313 orrs r3, r2 800f3e2: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 800f3e4: 68fb ldr r3, [r7, #12] 800f3e6: f423 5280 bic.w r2, r3, #4096 @ 0x1000 800f3ea: 683b ldr r3, [r7, #0] 800f3ec: 691b ldr r3, [r3, #16] 800f3ee: 4313 orrs r3, r2 800f3f0: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 800f3f2: 68fb ldr r3, [r7, #12] 800f3f4: f423 5200 bic.w r2, r3, #8192 @ 0x2000 800f3f8: 683b ldr r3, [r7, #0] 800f3fa: 695b ldr r3, [r3, #20] 800f3fc: 4313 orrs r3, r2 800f3fe: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 800f400: 68fb ldr r3, [r7, #12] 800f402: f423 4280 bic.w r2, r3, #16384 @ 0x4000 800f406: 683b ldr r3, [r7, #0] 800f408: 6a9b ldr r3, [r3, #40] @ 0x28 800f40a: 4313 orrs r3, r2 800f40c: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 800f40e: 68fb ldr r3, [r7, #12] 800f410: f423 2270 bic.w r2, r3, #983040 @ 0xf0000 800f414: 683b ldr r3, [r7, #0] 800f416: 699b ldr r3, [r3, #24] 800f418: 041b lsls r3, r3, #16 800f41a: 4313 orrs r3, r2 800f41c: 60fb str r3, [r7, #12] #if defined(TIM_BDTR_BKBID) MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); #endif /* TIM_BDTR_BKBID */ if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) 800f41e: 687b ldr r3, [r7, #4] 800f420: 681b ldr r3, [r3, #0] 800f422: 4a16 ldr r2, [pc, #88] @ (800f47c ) 800f424: 4293 cmp r3, r2 800f426: d004 beq.n 800f432 800f428: 687b ldr r3, [r7, #4] 800f42a: 681b ldr r3, [r3, #0] 800f42c: 4a14 ldr r2, [pc, #80] @ (800f480 ) 800f42e: 4293 cmp r3, r2 800f430: d115 bne.n 800f45e #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); #endif /* TIM_BDTR_BKBID */ /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); 800f432: 68fb ldr r3, [r7, #12] 800f434: f423 0270 bic.w r2, r3, #15728640 @ 0xf00000 800f438: 683b ldr r3, [r7, #0] 800f43a: 6a5b ldr r3, [r3, #36] @ 0x24 800f43c: 051b lsls r3, r3, #20 800f43e: 4313 orrs r3, r2 800f440: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); 800f442: 68fb ldr r3, [r7, #12] 800f444: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000 800f448: 683b ldr r3, [r7, #0] 800f44a: 69db ldr r3, [r3, #28] 800f44c: 4313 orrs r3, r2 800f44e: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); 800f450: 68fb ldr r3, [r7, #12] 800f452: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000 800f456: 683b ldr r3, [r7, #0] 800f458: 6a1b ldr r3, [r3, #32] 800f45a: 4313 orrs r3, r2 800f45c: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); #endif /* TIM_BDTR_BKBID */ } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; 800f45e: 687b ldr r3, [r7, #4] 800f460: 681b ldr r3, [r3, #0] 800f462: 68fa ldr r2, [r7, #12] 800f464: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(htim); 800f466: 687b ldr r3, [r7, #4] 800f468: 2200 movs r2, #0 800f46a: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 800f46e: 2300 movs r3, #0 } 800f470: 4618 mov r0, r3 800f472: 3714 adds r7, #20 800f474: 46bd mov sp, r7 800f476: f85d 7b04 ldr.w r7, [sp], #4 800f47a: 4770 bx lr 800f47c: 40010000 .word 0x40010000 800f480: 40010400 .word 0x40010400 0800f484 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 800f484: b480 push {r7} 800f486: b083 sub sp, #12 800f488: af00 add r7, sp, #0 800f48a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 800f48c: bf00 nop 800f48e: 370c adds r7, #12 800f490: 46bd mov sp, r7 800f492: f85d 7b04 ldr.w r7, [sp], #4 800f496: 4770 bx lr 0800f498 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 800f498: b480 push {r7} 800f49a: b083 sub sp, #12 800f49c: af00 add r7, sp, #0 800f49e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 800f4a0: bf00 nop 800f4a2: 370c adds r7, #12 800f4a4: 46bd mov sp, r7 800f4a6: f85d 7b04 ldr.w r7, [sp], #4 800f4aa: 4770 bx lr 0800f4ac : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 800f4ac: b480 push {r7} 800f4ae: b083 sub sp, #12 800f4b0: af00 add r7, sp, #0 800f4b2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 800f4b4: bf00 nop 800f4b6: 370c adds r7, #12 800f4b8: 46bd mov sp, r7 800f4ba: f85d 7b04 ldr.w r7, [sp], #4 800f4be: 4770 bx lr 0800f4c0 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 800f4c0: b580 push {r7, lr} 800f4c2: b082 sub sp, #8 800f4c4: af00 add r7, sp, #0 800f4c6: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 800f4c8: 687b ldr r3, [r7, #4] 800f4ca: 2b00 cmp r3, #0 800f4cc: d101 bne.n 800f4d2 { return HAL_ERROR; 800f4ce: 2301 movs r3, #1 800f4d0: e042 b.n 800f558 { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 800f4d2: 687b ldr r3, [r7, #4] 800f4d4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800f4d8: 2b00 cmp r3, #0 800f4da: d106 bne.n 800f4ea { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 800f4dc: 687b ldr r3, [r7, #4] 800f4de: 2200 movs r2, #0 800f4e0: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 800f4e4: 6878 ldr r0, [r7, #4] 800f4e6: f7f4 f833 bl 8003550 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 800f4ea: 687b ldr r3, [r7, #4] 800f4ec: 2224 movs r2, #36 @ 0x24 800f4ee: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UART_DISABLE(huart); 800f4f2: 687b ldr r3, [r7, #4] 800f4f4: 681b ldr r3, [r3, #0] 800f4f6: 681a ldr r2, [r3, #0] 800f4f8: 687b ldr r3, [r7, #4] 800f4fa: 681b ldr r3, [r3, #0] 800f4fc: f022 0201 bic.w r2, r2, #1 800f500: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 800f502: 687b ldr r3, [r7, #4] 800f504: 6a9b ldr r3, [r3, #40] @ 0x28 800f506: 2b00 cmp r3, #0 800f508: d002 beq.n 800f510 { UART_AdvFeatureConfig(huart); 800f50a: 6878 ldr r0, [r7, #4] 800f50c: f001 fa76 bl 80109fc } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 800f510: 6878 ldr r0, [r7, #4] 800f512: f000 fd0b bl 800ff2c 800f516: 4603 mov r3, r0 800f518: 2b01 cmp r3, #1 800f51a: d101 bne.n 800f520 { return HAL_ERROR; 800f51c: 2301 movs r3, #1 800f51e: e01b b.n 800f558 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 800f520: 687b ldr r3, [r7, #4] 800f522: 681b ldr r3, [r3, #0] 800f524: 685a ldr r2, [r3, #4] 800f526: 687b ldr r3, [r7, #4] 800f528: 681b ldr r3, [r3, #0] 800f52a: f422 4290 bic.w r2, r2, #18432 @ 0x4800 800f52e: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 800f530: 687b ldr r3, [r7, #4] 800f532: 681b ldr r3, [r3, #0] 800f534: 689a ldr r2, [r3, #8] 800f536: 687b ldr r3, [r7, #4] 800f538: 681b ldr r3, [r3, #0] 800f53a: f022 022a bic.w r2, r2, #42 @ 0x2a 800f53e: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 800f540: 687b ldr r3, [r7, #4] 800f542: 681b ldr r3, [r3, #0] 800f544: 681a ldr r2, [r3, #0] 800f546: 687b ldr r3, [r7, #4] 800f548: 681b ldr r3, [r3, #0] 800f54a: f042 0201 orr.w r2, r2, #1 800f54e: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 800f550: 6878 ldr r0, [r7, #4] 800f552: f001 faf5 bl 8010b40 800f556: 4603 mov r3, r0 } 800f558: 4618 mov r0, r3 800f55a: 3708 adds r7, #8 800f55c: 46bd mov sp, r7 800f55e: bd80 pop {r7, pc} 0800f560 : * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 800f560: b580 push {r7, lr} 800f562: b08a sub sp, #40 @ 0x28 800f564: af02 add r7, sp, #8 800f566: 60f8 str r0, [r7, #12] 800f568: 60b9 str r1, [r7, #8] 800f56a: 603b str r3, [r7, #0] 800f56c: 4613 mov r3, r2 800f56e: 80fb strh r3, [r7, #6] const uint8_t *pdata8bits; const uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 800f570: 68fb ldr r3, [r7, #12] 800f572: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800f576: 2b20 cmp r3, #32 800f578: d17b bne.n 800f672 { if ((pData == NULL) || (Size == 0U)) 800f57a: 68bb ldr r3, [r7, #8] 800f57c: 2b00 cmp r3, #0 800f57e: d002 beq.n 800f586 800f580: 88fb ldrh r3, [r7, #6] 800f582: 2b00 cmp r3, #0 800f584: d101 bne.n 800f58a { return HAL_ERROR; 800f586: 2301 movs r3, #1 800f588: e074 b.n 800f674 } huart->ErrorCode = HAL_UART_ERROR_NONE; 800f58a: 68fb ldr r3, [r7, #12] 800f58c: 2200 movs r2, #0 800f58e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->gState = HAL_UART_STATE_BUSY_TX; 800f592: 68fb ldr r3, [r7, #12] 800f594: 2221 movs r2, #33 @ 0x21 800f596: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 800f59a: f7f5 fa63 bl 8004a64 800f59e: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 800f5a0: 68fb ldr r3, [r7, #12] 800f5a2: 88fa ldrh r2, [r7, #6] 800f5a4: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 huart->TxXferCount = Size; 800f5a8: 68fb ldr r3, [r7, #12] 800f5aa: 88fa ldrh r2, [r7, #6] 800f5ac: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800f5b0: 68fb ldr r3, [r7, #12] 800f5b2: 689b ldr r3, [r3, #8] 800f5b4: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800f5b8: d108 bne.n 800f5cc 800f5ba: 68fb ldr r3, [r7, #12] 800f5bc: 691b ldr r3, [r3, #16] 800f5be: 2b00 cmp r3, #0 800f5c0: d104 bne.n 800f5cc { pdata8bits = NULL; 800f5c2: 2300 movs r3, #0 800f5c4: 61fb str r3, [r7, #28] pdata16bits = (const uint16_t *) pData; 800f5c6: 68bb ldr r3, [r7, #8] 800f5c8: 61bb str r3, [r7, #24] 800f5ca: e003 b.n 800f5d4 } else { pdata8bits = pData; 800f5cc: 68bb ldr r3, [r7, #8] 800f5ce: 61fb str r3, [r7, #28] pdata16bits = NULL; 800f5d0: 2300 movs r3, #0 800f5d2: 61bb str r3, [r7, #24] } while (huart->TxXferCount > 0U) 800f5d4: e030 b.n 800f638 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 800f5d6: 683b ldr r3, [r7, #0] 800f5d8: 9300 str r3, [sp, #0] 800f5da: 697b ldr r3, [r7, #20] 800f5dc: 2200 movs r2, #0 800f5de: 2180 movs r1, #128 @ 0x80 800f5e0: 68f8 ldr r0, [r7, #12] 800f5e2: f001 fb57 bl 8010c94 800f5e6: 4603 mov r3, r0 800f5e8: 2b00 cmp r3, #0 800f5ea: d005 beq.n 800f5f8 { huart->gState = HAL_UART_STATE_READY; 800f5ec: 68fb ldr r3, [r7, #12] 800f5ee: 2220 movs r2, #32 800f5f0: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_TIMEOUT; 800f5f4: 2303 movs r3, #3 800f5f6: e03d b.n 800f674 } if (pdata8bits == NULL) 800f5f8: 69fb ldr r3, [r7, #28] 800f5fa: 2b00 cmp r3, #0 800f5fc: d10b bne.n 800f616 { huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); 800f5fe: 69bb ldr r3, [r7, #24] 800f600: 881b ldrh r3, [r3, #0] 800f602: 461a mov r2, r3 800f604: 68fb ldr r3, [r7, #12] 800f606: 681b ldr r3, [r3, #0] 800f608: f3c2 0208 ubfx r2, r2, #0, #9 800f60c: 629a str r2, [r3, #40] @ 0x28 pdata16bits++; 800f60e: 69bb ldr r3, [r7, #24] 800f610: 3302 adds r3, #2 800f612: 61bb str r3, [r7, #24] 800f614: e007 b.n 800f626 } else { huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); 800f616: 69fb ldr r3, [r7, #28] 800f618: 781a ldrb r2, [r3, #0] 800f61a: 68fb ldr r3, [r7, #12] 800f61c: 681b ldr r3, [r3, #0] 800f61e: 629a str r2, [r3, #40] @ 0x28 pdata8bits++; 800f620: 69fb ldr r3, [r7, #28] 800f622: 3301 adds r3, #1 800f624: 61fb str r3, [r7, #28] } huart->TxXferCount--; 800f626: 68fb ldr r3, [r7, #12] 800f628: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 800f62c: b29b uxth r3, r3 800f62e: 3b01 subs r3, #1 800f630: b29a uxth r2, r3 800f632: 68fb ldr r3, [r7, #12] 800f634: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 while (huart->TxXferCount > 0U) 800f638: 68fb ldr r3, [r7, #12] 800f63a: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 800f63e: b29b uxth r3, r3 800f640: 2b00 cmp r3, #0 800f642: d1c8 bne.n 800f5d6 } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 800f644: 683b ldr r3, [r7, #0] 800f646: 9300 str r3, [sp, #0] 800f648: 697b ldr r3, [r7, #20] 800f64a: 2200 movs r2, #0 800f64c: 2140 movs r1, #64 @ 0x40 800f64e: 68f8 ldr r0, [r7, #12] 800f650: f001 fb20 bl 8010c94 800f654: 4603 mov r3, r0 800f656: 2b00 cmp r3, #0 800f658: d005 beq.n 800f666 { huart->gState = HAL_UART_STATE_READY; 800f65a: 68fb ldr r3, [r7, #12] 800f65c: 2220 movs r2, #32 800f65e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_TIMEOUT; 800f662: 2303 movs r3, #3 800f664: e006 b.n 800f674 } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 800f666: 68fb ldr r3, [r7, #12] 800f668: 2220 movs r2, #32 800f66a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_OK; 800f66e: 2300 movs r3, #0 800f670: e000 b.n 800f674 } else { return HAL_BUSY; 800f672: 2302 movs r3, #2 } } 800f674: 4618 mov r0, r3 800f676: 3720 adds r7, #32 800f678: 46bd mov sp, r7 800f67a: bd80 pop {r7, pc} 0800f67c : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 800f67c: b480 push {r7} 800f67e: b091 sub sp, #68 @ 0x44 800f680: af00 add r7, sp, #0 800f682: 60f8 str r0, [r7, #12] 800f684: 60b9 str r1, [r7, #8] 800f686: 4613 mov r3, r2 800f688: 80fb strh r3, [r7, #6] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 800f68a: 68fb ldr r3, [r7, #12] 800f68c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800f690: 2b20 cmp r3, #32 800f692: d178 bne.n 800f786 { if ((pData == NULL) || (Size == 0U)) 800f694: 68bb ldr r3, [r7, #8] 800f696: 2b00 cmp r3, #0 800f698: d002 beq.n 800f6a0 800f69a: 88fb ldrh r3, [r7, #6] 800f69c: 2b00 cmp r3, #0 800f69e: d101 bne.n 800f6a4 { return HAL_ERROR; 800f6a0: 2301 movs r3, #1 800f6a2: e071 b.n 800f788 } huart->pTxBuffPtr = pData; 800f6a4: 68fb ldr r3, [r7, #12] 800f6a6: 68ba ldr r2, [r7, #8] 800f6a8: 651a str r2, [r3, #80] @ 0x50 huart->TxXferSize = Size; 800f6aa: 68fb ldr r3, [r7, #12] 800f6ac: 88fa ldrh r2, [r7, #6] 800f6ae: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 huart->TxXferCount = Size; 800f6b2: 68fb ldr r3, [r7, #12] 800f6b4: 88fa ldrh r2, [r7, #6] 800f6b6: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 huart->TxISR = NULL; 800f6ba: 68fb ldr r3, [r7, #12] 800f6bc: 2200 movs r2, #0 800f6be: 679a str r2, [r3, #120] @ 0x78 huart->ErrorCode = HAL_UART_ERROR_NONE; 800f6c0: 68fb ldr r3, [r7, #12] 800f6c2: 2200 movs r2, #0 800f6c4: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->gState = HAL_UART_STATE_BUSY_TX; 800f6c8: 68fb ldr r3, [r7, #12] 800f6ca: 2221 movs r2, #33 @ 0x21 800f6cc: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Configure Tx interrupt processing */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) 800f6d0: 68fb ldr r3, [r7, #12] 800f6d2: 6e5b ldr r3, [r3, #100] @ 0x64 800f6d4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800f6d8: d12a bne.n 800f730 { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800f6da: 68fb ldr r3, [r7, #12] 800f6dc: 689b ldr r3, [r3, #8] 800f6de: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800f6e2: d107 bne.n 800f6f4 800f6e4: 68fb ldr r3, [r7, #12] 800f6e6: 691b ldr r3, [r3, #16] 800f6e8: 2b00 cmp r3, #0 800f6ea: d103 bne.n 800f6f4 { huart->TxISR = UART_TxISR_16BIT_FIFOEN; 800f6ec: 68fb ldr r3, [r7, #12] 800f6ee: 4a29 ldr r2, [pc, #164] @ (800f794 ) 800f6f0: 679a str r2, [r3, #120] @ 0x78 800f6f2: e002 b.n 800f6fa } else { huart->TxISR = UART_TxISR_8BIT_FIFOEN; 800f6f4: 68fb ldr r3, [r7, #12] 800f6f6: 4a28 ldr r2, [pc, #160] @ (800f798 ) 800f6f8: 679a str r2, [r3, #120] @ 0x78 } /* Enable the TX FIFO threshold interrupt */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 800f6fa: 68fb ldr r3, [r7, #12] 800f6fc: 681b ldr r3, [r3, #0] 800f6fe: 3308 adds r3, #8 800f700: 62bb str r3, [r7, #40] @ 0x28 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800f702: 6abb ldr r3, [r7, #40] @ 0x28 800f704: e853 3f00 ldrex r3, [r3] 800f708: 627b str r3, [r7, #36] @ 0x24 return(result); 800f70a: 6a7b ldr r3, [r7, #36] @ 0x24 800f70c: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 800f710: 63bb str r3, [r7, #56] @ 0x38 800f712: 68fb ldr r3, [r7, #12] 800f714: 681b ldr r3, [r3, #0] 800f716: 3308 adds r3, #8 800f718: 6bba ldr r2, [r7, #56] @ 0x38 800f71a: 637a str r2, [r7, #52] @ 0x34 800f71c: 633b str r3, [r7, #48] @ 0x30 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800f71e: 6b39 ldr r1, [r7, #48] @ 0x30 800f720: 6b7a ldr r2, [r7, #52] @ 0x34 800f722: e841 2300 strex r3, r2, [r1] 800f726: 62fb str r3, [r7, #44] @ 0x2c return(result); 800f728: 6afb ldr r3, [r7, #44] @ 0x2c 800f72a: 2b00 cmp r3, #0 800f72c: d1e5 bne.n 800f6fa 800f72e: e028 b.n 800f782 } else { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800f730: 68fb ldr r3, [r7, #12] 800f732: 689b ldr r3, [r3, #8] 800f734: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800f738: d107 bne.n 800f74a 800f73a: 68fb ldr r3, [r7, #12] 800f73c: 691b ldr r3, [r3, #16] 800f73e: 2b00 cmp r3, #0 800f740: d103 bne.n 800f74a { huart->TxISR = UART_TxISR_16BIT; 800f742: 68fb ldr r3, [r7, #12] 800f744: 4a15 ldr r2, [pc, #84] @ (800f79c ) 800f746: 679a str r2, [r3, #120] @ 0x78 800f748: e002 b.n 800f750 } else { huart->TxISR = UART_TxISR_8BIT; 800f74a: 68fb ldr r3, [r7, #12] 800f74c: 4a14 ldr r2, [pc, #80] @ (800f7a0 ) 800f74e: 679a str r2, [r3, #120] @ 0x78 } /* Enable the Transmit Data Register Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 800f750: 68fb ldr r3, [r7, #12] 800f752: 681b ldr r3, [r3, #0] 800f754: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800f756: 697b ldr r3, [r7, #20] 800f758: e853 3f00 ldrex r3, [r3] 800f75c: 613b str r3, [r7, #16] return(result); 800f75e: 693b ldr r3, [r7, #16] 800f760: f043 0380 orr.w r3, r3, #128 @ 0x80 800f764: 63fb str r3, [r7, #60] @ 0x3c 800f766: 68fb ldr r3, [r7, #12] 800f768: 681b ldr r3, [r3, #0] 800f76a: 461a mov r2, r3 800f76c: 6bfb ldr r3, [r7, #60] @ 0x3c 800f76e: 623b str r3, [r7, #32] 800f770: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800f772: 69f9 ldr r1, [r7, #28] 800f774: 6a3a ldr r2, [r7, #32] 800f776: e841 2300 strex r3, r2, [r1] 800f77a: 61bb str r3, [r7, #24] return(result); 800f77c: 69bb ldr r3, [r7, #24] 800f77e: 2b00 cmp r3, #0 800f780: d1e6 bne.n 800f750 } return HAL_OK; 800f782: 2300 movs r3, #0 800f784: e000 b.n 800f788 } else { return HAL_BUSY; 800f786: 2302 movs r3, #2 } } 800f788: 4618 mov r0, r3 800f78a: 3744 adds r7, #68 @ 0x44 800f78c: 46bd mov sp, r7 800f78e: f85d 7b04 ldr.w r7, [sp], #4 800f792: 4770 bx lr 800f794: 08011307 .word 0x08011307 800f798: 08011227 .word 0x08011227 800f79c: 08011165 .word 0x08011165 800f7a0: 080110ad .word 0x080110ad 0800f7a4 : * @brief Handle UART interrupt request. * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 800f7a4: b580 push {r7, lr} 800f7a6: b0ba sub sp, #232 @ 0xe8 800f7a8: af00 add r7, sp, #0 800f7aa: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->ISR); 800f7ac: 687b ldr r3, [r7, #4] 800f7ae: 681b ldr r3, [r3, #0] 800f7b0: 69db ldr r3, [r3, #28] 800f7b2: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 800f7b6: 687b ldr r3, [r7, #4] 800f7b8: 681b ldr r3, [r3, #0] 800f7ba: 681b ldr r3, [r3, #0] 800f7bc: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 800f7c0: 687b ldr r3, [r7, #4] 800f7c2: 681b ldr r3, [r3, #0] 800f7c4: 689b ldr r3, [r3, #8] 800f7c6: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags; uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); 800f7ca: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4 800f7ce: f640 030f movw r3, #2063 @ 0x80f 800f7d2: 4013 ands r3, r2 800f7d4: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == 0U) 800f7d8: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 800f7dc: 2b00 cmp r3, #0 800f7de: d11b bne.n 800f818 { /* UART in mode Receiver ---------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 800f7e0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800f7e4: f003 0320 and.w r3, r3, #32 800f7e8: 2b00 cmp r3, #0 800f7ea: d015 beq.n 800f818 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 800f7ec: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800f7f0: f003 0320 and.w r3, r3, #32 800f7f4: 2b00 cmp r3, #0 800f7f6: d105 bne.n 800f804 || ((cr3its & USART_CR3_RXFTIE) != 0U))) 800f7f8: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 800f7fc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800f800: 2b00 cmp r3, #0 800f802: d009 beq.n 800f818 { if (huart->RxISR != NULL) 800f804: 687b ldr r3, [r7, #4] 800f806: 6f5b ldr r3, [r3, #116] @ 0x74 800f808: 2b00 cmp r3, #0 800f80a: f000 8377 beq.w 800fefc { huart->RxISR(huart); 800f80e: 687b ldr r3, [r7, #4] 800f810: 6f5b ldr r3, [r3, #116] @ 0x74 800f812: 6878 ldr r0, [r7, #4] 800f814: 4798 blx r3 } return; 800f816: e371 b.n 800fefc } } /* If some errors occur */ if ((errorflags != 0U) 800f818: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 800f81c: 2b00 cmp r3, #0 800f81e: f000 8123 beq.w 800fa68 && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) 800f822: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 800f826: 4b8d ldr r3, [pc, #564] @ (800fa5c ) 800f828: 4013 ands r3, r2 800f82a: 2b00 cmp r3, #0 800f82c: d106 bne.n 800f83c || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) 800f82e: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0 800f832: 4b8b ldr r3, [pc, #556] @ (800fa60 ) 800f834: 4013 ands r3, r2 800f836: 2b00 cmp r3, #0 800f838: f000 8116 beq.w 800fa68 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 800f83c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800f840: f003 0301 and.w r3, r3, #1 800f844: 2b00 cmp r3, #0 800f846: d011 beq.n 800f86c 800f848: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800f84c: f403 7380 and.w r3, r3, #256 @ 0x100 800f850: 2b00 cmp r3, #0 800f852: d00b beq.n 800f86c { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 800f854: 687b ldr r3, [r7, #4] 800f856: 681b ldr r3, [r3, #0] 800f858: 2201 movs r2, #1 800f85a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 800f85c: 687b ldr r3, [r7, #4] 800f85e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800f862: f043 0201 orr.w r2, r3, #1 800f866: 687b ldr r3, [r7, #4] 800f868: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800f86c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800f870: f003 0302 and.w r3, r3, #2 800f874: 2b00 cmp r3, #0 800f876: d011 beq.n 800f89c 800f878: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 800f87c: f003 0301 and.w r3, r3, #1 800f880: 2b00 cmp r3, #0 800f882: d00b beq.n 800f89c { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 800f884: 687b ldr r3, [r7, #4] 800f886: 681b ldr r3, [r3, #0] 800f888: 2202 movs r2, #2 800f88a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 800f88c: 687b ldr r3, [r7, #4] 800f88e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800f892: f043 0204 orr.w r2, r3, #4 800f896: 687b ldr r3, [r7, #4] 800f898: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800f89c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800f8a0: f003 0304 and.w r3, r3, #4 800f8a4: 2b00 cmp r3, #0 800f8a6: d011 beq.n 800f8cc 800f8a8: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 800f8ac: f003 0301 and.w r3, r3, #1 800f8b0: 2b00 cmp r3, #0 800f8b2: d00b beq.n 800f8cc { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 800f8b4: 687b ldr r3, [r7, #4] 800f8b6: 681b ldr r3, [r3, #0] 800f8b8: 2204 movs r2, #4 800f8ba: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 800f8bc: 687b ldr r3, [r7, #4] 800f8be: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800f8c2: f043 0202 orr.w r2, r3, #2 800f8c6: 687b ldr r3, [r7, #4] 800f8c8: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Over-Run interrupt occurred -----------------------------------------*/ if (((isrflags & USART_ISR_ORE) != 0U) 800f8cc: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800f8d0: f003 0308 and.w r3, r3, #8 800f8d4: 2b00 cmp r3, #0 800f8d6: d017 beq.n 800f908 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 800f8d8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800f8dc: f003 0320 and.w r3, r3, #32 800f8e0: 2b00 cmp r3, #0 800f8e2: d105 bne.n 800f8f0 ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) 800f8e4: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 800f8e8: 4b5c ldr r3, [pc, #368] @ (800fa5c ) 800f8ea: 4013 ands r3, r2 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 800f8ec: 2b00 cmp r3, #0 800f8ee: d00b beq.n 800f908 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 800f8f0: 687b ldr r3, [r7, #4] 800f8f2: 681b ldr r3, [r3, #0] 800f8f4: 2208 movs r2, #8 800f8f6: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_ORE; 800f8f8: 687b ldr r3, [r7, #4] 800f8fa: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800f8fe: f043 0208 orr.w r2, r3, #8 800f902: 687b ldr r3, [r7, #4] 800f904: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Receiver Timeout interrupt occurred ---------------------------------*/ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) 800f908: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800f90c: f403 6300 and.w r3, r3, #2048 @ 0x800 800f910: 2b00 cmp r3, #0 800f912: d012 beq.n 800f93a 800f914: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800f918: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800f91c: 2b00 cmp r3, #0 800f91e: d00c beq.n 800f93a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 800f920: 687b ldr r3, [r7, #4] 800f922: 681b ldr r3, [r3, #0] 800f924: f44f 6200 mov.w r2, #2048 @ 0x800 800f928: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_RTO; 800f92a: 687b ldr r3, [r7, #4] 800f92c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800f930: f043 0220 orr.w r2, r3, #32 800f934: 687b ldr r3, [r7, #4] 800f936: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 800f93a: 687b ldr r3, [r7, #4] 800f93c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800f940: 2b00 cmp r3, #0 800f942: f000 82dd beq.w 800ff00 { /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 800f946: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800f94a: f003 0320 and.w r3, r3, #32 800f94e: 2b00 cmp r3, #0 800f950: d013 beq.n 800f97a && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 800f952: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800f956: f003 0320 and.w r3, r3, #32 800f95a: 2b00 cmp r3, #0 800f95c: d105 bne.n 800f96a || ((cr3its & USART_CR3_RXFTIE) != 0U))) 800f95e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 800f962: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800f966: 2b00 cmp r3, #0 800f968: d007 beq.n 800f97a { if (huart->RxISR != NULL) 800f96a: 687b ldr r3, [r7, #4] 800f96c: 6f5b ldr r3, [r3, #116] @ 0x74 800f96e: 2b00 cmp r3, #0 800f970: d003 beq.n 800f97a { huart->RxISR(huart); 800f972: 687b ldr r3, [r7, #4] 800f974: 6f5b ldr r3, [r3, #116] @ 0x74 800f976: 6878 ldr r0, [r7, #4] 800f978: 4798 blx r3 /* If Error is to be considered as blocking : - Receiver Timeout error in Reception - Overrun error in Reception - any error occurs in DMA mode reception */ errorcode = huart->ErrorCode; 800f97a: 687b ldr r3, [r7, #4] 800f97c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800f980: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 800f984: 687b ldr r3, [r7, #4] 800f986: 681b ldr r3, [r3, #0] 800f988: 689b ldr r3, [r3, #8] 800f98a: f003 0340 and.w r3, r3, #64 @ 0x40 800f98e: 2b40 cmp r3, #64 @ 0x40 800f990: d005 beq.n 800f99e ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) 800f992: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 800f996: f003 0328 and.w r3, r3, #40 @ 0x28 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 800f99a: 2b00 cmp r3, #0 800f99c: d054 beq.n 800fa48 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 800f99e: 6878 ldr r0, [r7, #4] 800f9a0: f001 fb08 bl 8010fb4 /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800f9a4: 687b ldr r3, [r7, #4] 800f9a6: 681b ldr r3, [r3, #0] 800f9a8: 689b ldr r3, [r3, #8] 800f9aa: f003 0340 and.w r3, r3, #64 @ 0x40 800f9ae: 2b40 cmp r3, #64 @ 0x40 800f9b0: d146 bne.n 800fa40 { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 800f9b2: 687b ldr r3, [r7, #4] 800f9b4: 681b ldr r3, [r3, #0] 800f9b6: 3308 adds r3, #8 800f9b8: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800f9bc: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 800f9c0: e853 3f00 ldrex r3, [r3] 800f9c4: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 800f9c8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 800f9cc: f023 0340 bic.w r3, r3, #64 @ 0x40 800f9d0: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 800f9d4: 687b ldr r3, [r7, #4] 800f9d6: 681b ldr r3, [r3, #0] 800f9d8: 3308 adds r3, #8 800f9da: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 800f9de: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 800f9e2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800f9e6: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 800f9ea: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 800f9ee: e841 2300 strex r3, r2, [r1] 800f9f2: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 800f9f6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 800f9fa: 2b00 cmp r3, #0 800f9fc: d1d9 bne.n 800f9b2 /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 800f9fe: 687b ldr r3, [r7, #4] 800fa00: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fa04: 2b00 cmp r3, #0 800fa06: d017 beq.n 800fa38 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 800fa08: 687b ldr r3, [r7, #4] 800fa0a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fa0e: 4a15 ldr r2, [pc, #84] @ (800fa64 ) 800fa10: 651a str r2, [r3, #80] @ 0x50 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 800fa12: 687b ldr r3, [r7, #4] 800fa14: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fa18: 4618 mov r0, r3 800fa1a: f7f8 fb11 bl 8008040 800fa1e: 4603 mov r3, r0 800fa20: 2b00 cmp r3, #0 800fa22: d019 beq.n 800fa58 { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 800fa24: 687b ldr r3, [r7, #4] 800fa26: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fa2a: 6d1b ldr r3, [r3, #80] @ 0x50 800fa2c: 687a ldr r2, [r7, #4] 800fa2e: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80 800fa32: 4610 mov r0, r2 800fa34: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800fa36: e00f b.n 800fa58 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800fa38: 6878 ldr r0, [r7, #4] 800fa3a: f000 fa6d bl 800ff18 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800fa3e: e00b b.n 800fa58 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800fa40: 6878 ldr r0, [r7, #4] 800fa42: f000 fa69 bl 800ff18 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800fa46: e007 b.n 800fa58 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800fa48: 6878 ldr r0, [r7, #4] 800fa4a: f000 fa65 bl 800ff18 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 800fa4e: 687b ldr r3, [r7, #4] 800fa50: 2200 movs r2, #0 800fa52: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } return; 800fa56: e253 b.n 800ff00 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800fa58: bf00 nop return; 800fa5a: e251 b.n 800ff00 800fa5c: 10000001 .word 0x10000001 800fa60: 04000120 .word 0x04000120 800fa64: 08011081 .word 0x08011081 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800fa68: 687b ldr r3, [r7, #4] 800fa6a: 6edb ldr r3, [r3, #108] @ 0x6c 800fa6c: 2b01 cmp r3, #1 800fa6e: f040 81e7 bne.w 800fe40 && ((isrflags & USART_ISR_IDLE) != 0U) 800fa72: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800fa76: f003 0310 and.w r3, r3, #16 800fa7a: 2b00 cmp r3, #0 800fa7c: f000 81e0 beq.w 800fe40 && ((cr1its & USART_ISR_IDLE) != 0U)) 800fa80: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800fa84: f003 0310 and.w r3, r3, #16 800fa88: 2b00 cmp r3, #0 800fa8a: f000 81d9 beq.w 800fe40 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 800fa8e: 687b ldr r3, [r7, #4] 800fa90: 681b ldr r3, [r3, #0] 800fa92: 2210 movs r2, #16 800fa94: 621a str r2, [r3, #32] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800fa96: 687b ldr r3, [r7, #4] 800fa98: 681b ldr r3, [r3, #0] 800fa9a: 689b ldr r3, [r3, #8] 800fa9c: f003 0340 and.w r3, r3, #64 @ 0x40 800faa0: 2b40 cmp r3, #64 @ 0x40 800faa2: f040 8151 bne.w 800fd48 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 800faa6: 687b ldr r3, [r7, #4] 800faa8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800faac: 681b ldr r3, [r3, #0] 800faae: 4a96 ldr r2, [pc, #600] @ (800fd08 ) 800fab0: 4293 cmp r3, r2 800fab2: d068 beq.n 800fb86 800fab4: 687b ldr r3, [r7, #4] 800fab6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800faba: 681b ldr r3, [r3, #0] 800fabc: 4a93 ldr r2, [pc, #588] @ (800fd0c ) 800fabe: 4293 cmp r3, r2 800fac0: d061 beq.n 800fb86 800fac2: 687b ldr r3, [r7, #4] 800fac4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fac8: 681b ldr r3, [r3, #0] 800faca: 4a91 ldr r2, [pc, #580] @ (800fd10 ) 800facc: 4293 cmp r3, r2 800face: d05a beq.n 800fb86 800fad0: 687b ldr r3, [r7, #4] 800fad2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fad6: 681b ldr r3, [r3, #0] 800fad8: 4a8e ldr r2, [pc, #568] @ (800fd14 ) 800fada: 4293 cmp r3, r2 800fadc: d053 beq.n 800fb86 800fade: 687b ldr r3, [r7, #4] 800fae0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fae4: 681b ldr r3, [r3, #0] 800fae6: 4a8c ldr r2, [pc, #560] @ (800fd18 ) 800fae8: 4293 cmp r3, r2 800faea: d04c beq.n 800fb86 800faec: 687b ldr r3, [r7, #4] 800faee: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800faf2: 681b ldr r3, [r3, #0] 800faf4: 4a89 ldr r2, [pc, #548] @ (800fd1c ) 800faf6: 4293 cmp r3, r2 800faf8: d045 beq.n 800fb86 800fafa: 687b ldr r3, [r7, #4] 800fafc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fb00: 681b ldr r3, [r3, #0] 800fb02: 4a87 ldr r2, [pc, #540] @ (800fd20 ) 800fb04: 4293 cmp r3, r2 800fb06: d03e beq.n 800fb86 800fb08: 687b ldr r3, [r7, #4] 800fb0a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fb0e: 681b ldr r3, [r3, #0] 800fb10: 4a84 ldr r2, [pc, #528] @ (800fd24 ) 800fb12: 4293 cmp r3, r2 800fb14: d037 beq.n 800fb86 800fb16: 687b ldr r3, [r7, #4] 800fb18: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fb1c: 681b ldr r3, [r3, #0] 800fb1e: 4a82 ldr r2, [pc, #520] @ (800fd28 ) 800fb20: 4293 cmp r3, r2 800fb22: d030 beq.n 800fb86 800fb24: 687b ldr r3, [r7, #4] 800fb26: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fb2a: 681b ldr r3, [r3, #0] 800fb2c: 4a7f ldr r2, [pc, #508] @ (800fd2c ) 800fb2e: 4293 cmp r3, r2 800fb30: d029 beq.n 800fb86 800fb32: 687b ldr r3, [r7, #4] 800fb34: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fb38: 681b ldr r3, [r3, #0] 800fb3a: 4a7d ldr r2, [pc, #500] @ (800fd30 ) 800fb3c: 4293 cmp r3, r2 800fb3e: d022 beq.n 800fb86 800fb40: 687b ldr r3, [r7, #4] 800fb42: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fb46: 681b ldr r3, [r3, #0] 800fb48: 4a7a ldr r2, [pc, #488] @ (800fd34 ) 800fb4a: 4293 cmp r3, r2 800fb4c: d01b beq.n 800fb86 800fb4e: 687b ldr r3, [r7, #4] 800fb50: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fb54: 681b ldr r3, [r3, #0] 800fb56: 4a78 ldr r2, [pc, #480] @ (800fd38 ) 800fb58: 4293 cmp r3, r2 800fb5a: d014 beq.n 800fb86 800fb5c: 687b ldr r3, [r7, #4] 800fb5e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fb62: 681b ldr r3, [r3, #0] 800fb64: 4a75 ldr r2, [pc, #468] @ (800fd3c ) 800fb66: 4293 cmp r3, r2 800fb68: d00d beq.n 800fb86 800fb6a: 687b ldr r3, [r7, #4] 800fb6c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fb70: 681b ldr r3, [r3, #0] 800fb72: 4a73 ldr r2, [pc, #460] @ (800fd40 ) 800fb74: 4293 cmp r3, r2 800fb76: d006 beq.n 800fb86 800fb78: 687b ldr r3, [r7, #4] 800fb7a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fb7e: 681b ldr r3, [r3, #0] 800fb80: 4a70 ldr r2, [pc, #448] @ (800fd44 ) 800fb82: 4293 cmp r3, r2 800fb84: d106 bne.n 800fb94 800fb86: 687b ldr r3, [r7, #4] 800fb88: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fb8c: 681b ldr r3, [r3, #0] 800fb8e: 685b ldr r3, [r3, #4] 800fb90: b29b uxth r3, r3 800fb92: e005 b.n 800fba0 800fb94: 687b ldr r3, [r7, #4] 800fb96: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fb9a: 681b ldr r3, [r3, #0] 800fb9c: 685b ldr r3, [r3, #4] 800fb9e: b29b uxth r3, r3 800fba0: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 800fba4: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 800fba8: 2b00 cmp r3, #0 800fbaa: f000 81ab beq.w 800ff04 && (nb_remaining_rx_data < huart->RxXferSize)) 800fbae: 687b ldr r3, [r7, #4] 800fbb0: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 800fbb4: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 800fbb8: 429a cmp r2, r3 800fbba: f080 81a3 bcs.w 800ff04 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 800fbbe: 687b ldr r3, [r7, #4] 800fbc0: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 800fbc4: f8a3 205e strh.w r2, [r3, #94] @ 0x5e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 800fbc8: 687b ldr r3, [r7, #4] 800fbca: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fbce: 69db ldr r3, [r3, #28] 800fbd0: f5b3 7f80 cmp.w r3, #256 @ 0x100 800fbd4: f000 8087 beq.w 800fce6 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 800fbd8: 687b ldr r3, [r7, #4] 800fbda: 681b ldr r3, [r3, #0] 800fbdc: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800fbe0: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800fbe4: e853 3f00 ldrex r3, [r3] 800fbe8: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 800fbec: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 800fbf0: f423 7380 bic.w r3, r3, #256 @ 0x100 800fbf4: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 800fbf8: 687b ldr r3, [r7, #4] 800fbfa: 681b ldr r3, [r3, #0] 800fbfc: 461a mov r2, r3 800fbfe: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 800fc02: f8c7 3094 str.w r3, [r7, #148] @ 0x94 800fc06: f8c7 2090 str.w r2, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800fc0a: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 800fc0e: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 800fc12: e841 2300 strex r3, r2, [r1] 800fc16: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 800fc1a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800fc1e: 2b00 cmp r3, #0 800fc20: d1da bne.n 800fbd8 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800fc22: 687b ldr r3, [r7, #4] 800fc24: 681b ldr r3, [r3, #0] 800fc26: 3308 adds r3, #8 800fc28: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800fc2a: 6f7b ldr r3, [r7, #116] @ 0x74 800fc2c: e853 3f00 ldrex r3, [r3] 800fc30: 673b str r3, [r7, #112] @ 0x70 return(result); 800fc32: 6f3b ldr r3, [r7, #112] @ 0x70 800fc34: f023 0301 bic.w r3, r3, #1 800fc38: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 800fc3c: 687b ldr r3, [r7, #4] 800fc3e: 681b ldr r3, [r3, #0] 800fc40: 3308 adds r3, #8 800fc42: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 800fc46: f8c7 2080 str.w r2, [r7, #128] @ 0x80 800fc4a: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800fc4c: 6ff9 ldr r1, [r7, #124] @ 0x7c 800fc4e: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 800fc52: e841 2300 strex r3, r2, [r1] 800fc56: 67bb str r3, [r7, #120] @ 0x78 return(result); 800fc58: 6fbb ldr r3, [r7, #120] @ 0x78 800fc5a: 2b00 cmp r3, #0 800fc5c: d1e1 bne.n 800fc22 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 800fc5e: 687b ldr r3, [r7, #4] 800fc60: 681b ldr r3, [r3, #0] 800fc62: 3308 adds r3, #8 800fc64: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800fc66: 6e3b ldr r3, [r7, #96] @ 0x60 800fc68: e853 3f00 ldrex r3, [r3] 800fc6c: 65fb str r3, [r7, #92] @ 0x5c return(result); 800fc6e: 6dfb ldr r3, [r7, #92] @ 0x5c 800fc70: f023 0340 bic.w r3, r3, #64 @ 0x40 800fc74: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 800fc78: 687b ldr r3, [r7, #4] 800fc7a: 681b ldr r3, [r3, #0] 800fc7c: 3308 adds r3, #8 800fc7e: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 800fc82: 66fa str r2, [r7, #108] @ 0x6c 800fc84: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800fc86: 6eb9 ldr r1, [r7, #104] @ 0x68 800fc88: 6efa ldr r2, [r7, #108] @ 0x6c 800fc8a: e841 2300 strex r3, r2, [r1] 800fc8e: 667b str r3, [r7, #100] @ 0x64 return(result); 800fc90: 6e7b ldr r3, [r7, #100] @ 0x64 800fc92: 2b00 cmp r3, #0 800fc94: d1e3 bne.n 800fc5e /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800fc96: 687b ldr r3, [r7, #4] 800fc98: 2220 movs r2, #32 800fc9a: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800fc9e: 687b ldr r3, [r7, #4] 800fca0: 2200 movs r2, #0 800fca2: 66da str r2, [r3, #108] @ 0x6c ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800fca4: 687b ldr r3, [r7, #4] 800fca6: 681b ldr r3, [r3, #0] 800fca8: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800fcaa: 6cfb ldr r3, [r7, #76] @ 0x4c 800fcac: e853 3f00 ldrex r3, [r3] 800fcb0: 64bb str r3, [r7, #72] @ 0x48 return(result); 800fcb2: 6cbb ldr r3, [r7, #72] @ 0x48 800fcb4: f023 0310 bic.w r3, r3, #16 800fcb8: f8c7 30ac str.w r3, [r7, #172] @ 0xac 800fcbc: 687b ldr r3, [r7, #4] 800fcbe: 681b ldr r3, [r3, #0] 800fcc0: 461a mov r2, r3 800fcc2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fcc6: 65bb str r3, [r7, #88] @ 0x58 800fcc8: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800fcca: 6d79 ldr r1, [r7, #84] @ 0x54 800fccc: 6dba ldr r2, [r7, #88] @ 0x58 800fcce: e841 2300 strex r3, r2, [r1] 800fcd2: 653b str r3, [r7, #80] @ 0x50 return(result); 800fcd4: 6d3b ldr r3, [r7, #80] @ 0x50 800fcd6: 2b00 cmp r3, #0 800fcd8: d1e4 bne.n 800fca4 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 800fcda: 687b ldr r3, [r7, #4] 800fcdc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800fce0: 4618 mov r0, r3 800fce2: f7f7 fe8f bl 8007a04 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 800fce6: 687b ldr r3, [r7, #4] 800fce8: 2202 movs r2, #2 800fcea: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 800fcec: 687b ldr r3, [r7, #4] 800fcee: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 800fcf2: 687b ldr r3, [r7, #4] 800fcf4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800fcf8: b29b uxth r3, r3 800fcfa: 1ad3 subs r3, r2, r3 800fcfc: b29b uxth r3, r3 800fcfe: 4619 mov r1, r3 800fd00: 6878 ldr r0, [r7, #4] 800fd02: f7f3 ff79 bl 8003bf8 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 800fd06: e0fd b.n 800ff04 800fd08: 40020010 .word 0x40020010 800fd0c: 40020028 .word 0x40020028 800fd10: 40020040 .word 0x40020040 800fd14: 40020058 .word 0x40020058 800fd18: 40020070 .word 0x40020070 800fd1c: 40020088 .word 0x40020088 800fd20: 400200a0 .word 0x400200a0 800fd24: 400200b8 .word 0x400200b8 800fd28: 40020410 .word 0x40020410 800fd2c: 40020428 .word 0x40020428 800fd30: 40020440 .word 0x40020440 800fd34: 40020458 .word 0x40020458 800fd38: 40020470 .word 0x40020470 800fd3c: 40020488 .word 0x40020488 800fd40: 400204a0 .word 0x400204a0 800fd44: 400204b8 .word 0x400204b8 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 800fd48: 687b ldr r3, [r7, #4] 800fd4a: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 800fd4e: 687b ldr r3, [r7, #4] 800fd50: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800fd54: b29b uxth r3, r3 800fd56: 1ad3 subs r3, r2, r3 800fd58: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 800fd5c: 687b ldr r3, [r7, #4] 800fd5e: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800fd62: b29b uxth r3, r3 800fd64: 2b00 cmp r3, #0 800fd66: f000 80cf beq.w 800ff08 && (nb_rx_data > 0U)) 800fd6a: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 800fd6e: 2b00 cmp r3, #0 800fd70: f000 80ca beq.w 800ff08 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800fd74: 687b ldr r3, [r7, #4] 800fd76: 681b ldr r3, [r3, #0] 800fd78: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800fd7a: 6bbb ldr r3, [r7, #56] @ 0x38 800fd7c: e853 3f00 ldrex r3, [r3] 800fd80: 637b str r3, [r7, #52] @ 0x34 return(result); 800fd82: 6b7b ldr r3, [r7, #52] @ 0x34 800fd84: f423 7390 bic.w r3, r3, #288 @ 0x120 800fd88: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 800fd8c: 687b ldr r3, [r7, #4] 800fd8e: 681b ldr r3, [r3, #0] 800fd90: 461a mov r2, r3 800fd92: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 800fd96: 647b str r3, [r7, #68] @ 0x44 800fd98: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800fd9a: 6c39 ldr r1, [r7, #64] @ 0x40 800fd9c: 6c7a ldr r2, [r7, #68] @ 0x44 800fd9e: e841 2300 strex r3, r2, [r1] 800fda2: 63fb str r3, [r7, #60] @ 0x3c return(result); 800fda4: 6bfb ldr r3, [r7, #60] @ 0x3c 800fda6: 2b00 cmp r3, #0 800fda8: d1e4 bne.n 800fd74 /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800fdaa: 687b ldr r3, [r7, #4] 800fdac: 681b ldr r3, [r3, #0] 800fdae: 3308 adds r3, #8 800fdb0: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800fdb2: 6a7b ldr r3, [r7, #36] @ 0x24 800fdb4: e853 3f00 ldrex r3, [r3] 800fdb8: 623b str r3, [r7, #32] return(result); 800fdba: 6a3a ldr r2, [r7, #32] 800fdbc: 4b55 ldr r3, [pc, #340] @ (800ff14 ) 800fdbe: 4013 ands r3, r2 800fdc0: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 800fdc4: 687b ldr r3, [r7, #4] 800fdc6: 681b ldr r3, [r3, #0] 800fdc8: 3308 adds r3, #8 800fdca: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 800fdce: 633a str r2, [r7, #48] @ 0x30 800fdd0: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800fdd2: 6af9 ldr r1, [r7, #44] @ 0x2c 800fdd4: 6b3a ldr r2, [r7, #48] @ 0x30 800fdd6: e841 2300 strex r3, r2, [r1] 800fdda: 62bb str r3, [r7, #40] @ 0x28 return(result); 800fddc: 6abb ldr r3, [r7, #40] @ 0x28 800fdde: 2b00 cmp r3, #0 800fde0: d1e3 bne.n 800fdaa /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800fde2: 687b ldr r3, [r7, #4] 800fde4: 2220 movs r2, #32 800fde6: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800fdea: 687b ldr r3, [r7, #4] 800fdec: 2200 movs r2, #0 800fdee: 66da str r2, [r3, #108] @ 0x6c /* Clear RxISR function pointer */ huart->RxISR = NULL; 800fdf0: 687b ldr r3, [r7, #4] 800fdf2: 2200 movs r2, #0 800fdf4: 675a str r2, [r3, #116] @ 0x74 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800fdf6: 687b ldr r3, [r7, #4] 800fdf8: 681b ldr r3, [r3, #0] 800fdfa: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800fdfc: 693b ldr r3, [r7, #16] 800fdfe: e853 3f00 ldrex r3, [r3] 800fe02: 60fb str r3, [r7, #12] return(result); 800fe04: 68fb ldr r3, [r7, #12] 800fe06: f023 0310 bic.w r3, r3, #16 800fe0a: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 800fe0e: 687b ldr r3, [r7, #4] 800fe10: 681b ldr r3, [r3, #0] 800fe12: 461a mov r2, r3 800fe14: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 800fe18: 61fb str r3, [r7, #28] 800fe1a: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800fe1c: 69b9 ldr r1, [r7, #24] 800fe1e: 69fa ldr r2, [r7, #28] 800fe20: e841 2300 strex r3, r2, [r1] 800fe24: 617b str r3, [r7, #20] return(result); 800fe26: 697b ldr r3, [r7, #20] 800fe28: 2b00 cmp r3, #0 800fe2a: d1e4 bne.n 800fdf6 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 800fe2c: 687b ldr r3, [r7, #4] 800fe2e: 2202 movs r2, #2 800fe30: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 800fe32: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 800fe36: 4619 mov r1, r3 800fe38: 6878 ldr r0, [r7, #4] 800fe3a: f7f3 fedd bl 8003bf8 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 800fe3e: e063 b.n 800ff08 } } /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) 800fe40: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800fe44: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800fe48: 2b00 cmp r3, #0 800fe4a: d00e beq.n 800fe6a 800fe4c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 800fe50: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800fe54: 2b00 cmp r3, #0 800fe56: d008 beq.n 800fe6a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); 800fe58: 687b ldr r3, [r7, #4] 800fe5a: 681b ldr r3, [r3, #0] 800fe5c: f44f 1280 mov.w r2, #1048576 @ 0x100000 800fe60: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Wakeup Callback */ huart->WakeupCallback(huart); #else /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); 800fe62: 6878 ldr r0, [r7, #4] 800fe64: f002 f80c bl 8011e80 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 800fe68: e051 b.n 800ff0e } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) 800fe6a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800fe6e: f003 0380 and.w r3, r3, #128 @ 0x80 800fe72: 2b00 cmp r3, #0 800fe74: d014 beq.n 800fea0 && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) 800fe76: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800fe7a: f003 0380 and.w r3, r3, #128 @ 0x80 800fe7e: 2b00 cmp r3, #0 800fe80: d105 bne.n 800fe8e || ((cr3its & USART_CR3_TXFTIE) != 0U))) 800fe82: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 800fe86: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800fe8a: 2b00 cmp r3, #0 800fe8c: d008 beq.n 800fea0 { if (huart->TxISR != NULL) 800fe8e: 687b ldr r3, [r7, #4] 800fe90: 6f9b ldr r3, [r3, #120] @ 0x78 800fe92: 2b00 cmp r3, #0 800fe94: d03a beq.n 800ff0c { huart->TxISR(huart); 800fe96: 687b ldr r3, [r7, #4] 800fe98: 6f9b ldr r3, [r3, #120] @ 0x78 800fe9a: 6878 ldr r0, [r7, #4] 800fe9c: 4798 blx r3 } return; 800fe9e: e035 b.n 800ff0c } /* UART in mode Transmitter (transmission end) -----------------------------*/ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) 800fea0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800fea4: f003 0340 and.w r3, r3, #64 @ 0x40 800fea8: 2b00 cmp r3, #0 800feaa: d009 beq.n 800fec0 800feac: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800feb0: f003 0340 and.w r3, r3, #64 @ 0x40 800feb4: 2b00 cmp r3, #0 800feb6: d003 beq.n 800fec0 { UART_EndTransmit_IT(huart); 800feb8: 6878 ldr r0, [r7, #4] 800feba: f001 fa99 bl 80113f0 return; 800febe: e026 b.n 800ff0e } /* UART TX Fifo Empty occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) 800fec0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800fec4: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800fec8: 2b00 cmp r3, #0 800feca: d009 beq.n 800fee0 800fecc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800fed0: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 800fed4: 2b00 cmp r3, #0 800fed6: d003 beq.n 800fee0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ huart->TxFifoEmptyCallback(huart); #else /* Call legacy weak Tx Fifo Empty Callback */ HAL_UARTEx_TxFifoEmptyCallback(huart); 800fed8: 6878 ldr r0, [r7, #4] 800feda: f001 ffe5 bl 8011ea8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 800fede: e016 b.n 800ff0e } /* UART RX Fifo Full occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) 800fee0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800fee4: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800fee8: 2b00 cmp r3, #0 800feea: d010 beq.n 800ff0e 800feec: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800fef0: 2b00 cmp r3, #0 800fef2: da0c bge.n 800ff0e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ huart->RxFifoFullCallback(huart); #else /* Call legacy weak Rx Fifo Full Callback */ HAL_UARTEx_RxFifoFullCallback(huart); 800fef4: 6878 ldr r0, [r7, #4] 800fef6: f001 ffcd bl 8011e94 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 800fefa: e008 b.n 800ff0e return; 800fefc: bf00 nop 800fefe: e006 b.n 800ff0e return; 800ff00: bf00 nop 800ff02: e004 b.n 800ff0e return; 800ff04: bf00 nop 800ff06: e002 b.n 800ff0e return; 800ff08: bf00 nop 800ff0a: e000 b.n 800ff0e return; 800ff0c: bf00 nop } } 800ff0e: 37e8 adds r7, #232 @ 0xe8 800ff10: 46bd mov sp, r7 800ff12: bd80 pop {r7, pc} 800ff14: effffffe .word 0xeffffffe 0800ff18 : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 800ff18: b480 push {r7} 800ff1a: b083 sub sp, #12 800ff1c: af00 add r7, sp, #0 800ff1e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } 800ff20: bf00 nop 800ff22: 370c adds r7, #12 800ff24: 46bd mov sp, r7 800ff26: f85d 7b04 ldr.w r7, [sp], #4 800ff2a: 4770 bx lr 0800ff2c : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 800ff2c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 800ff30: b092 sub sp, #72 @ 0x48 800ff32: af00 add r7, sp, #0 800ff34: 6178 str r0, [r7, #20] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 800ff36: 2300 movs r3, #0 800ff38: f887 3042 strb.w r3, [r7, #66] @ 0x42 * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 800ff3c: 697b ldr r3, [r7, #20] 800ff3e: 689a ldr r2, [r3, #8] 800ff40: 697b ldr r3, [r7, #20] 800ff42: 691b ldr r3, [r3, #16] 800ff44: 431a orrs r2, r3 800ff46: 697b ldr r3, [r7, #20] 800ff48: 695b ldr r3, [r3, #20] 800ff4a: 431a orrs r2, r3 800ff4c: 697b ldr r3, [r7, #20] 800ff4e: 69db ldr r3, [r3, #28] 800ff50: 4313 orrs r3, r2 800ff52: 647b str r3, [r7, #68] @ 0x44 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 800ff54: 697b ldr r3, [r7, #20] 800ff56: 681b ldr r3, [r3, #0] 800ff58: 681a ldr r2, [r3, #0] 800ff5a: 4bbe ldr r3, [pc, #760] @ (8010254 ) 800ff5c: 4013 ands r3, r2 800ff5e: 697a ldr r2, [r7, #20] 800ff60: 6812 ldr r2, [r2, #0] 800ff62: 6c79 ldr r1, [r7, #68] @ 0x44 800ff64: 430b orrs r3, r1 800ff66: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 800ff68: 697b ldr r3, [r7, #20] 800ff6a: 681b ldr r3, [r3, #0] 800ff6c: 685b ldr r3, [r3, #4] 800ff6e: f423 5140 bic.w r1, r3, #12288 @ 0x3000 800ff72: 697b ldr r3, [r7, #20] 800ff74: 68da ldr r2, [r3, #12] 800ff76: 697b ldr r3, [r7, #20] 800ff78: 681b ldr r3, [r3, #0] 800ff7a: 430a orrs r2, r1 800ff7c: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 800ff7e: 697b ldr r3, [r7, #20] 800ff80: 699b ldr r3, [r3, #24] 800ff82: 647b str r3, [r7, #68] @ 0x44 if (!(UART_INSTANCE_LOWPOWER(huart))) 800ff84: 697b ldr r3, [r7, #20] 800ff86: 681b ldr r3, [r3, #0] 800ff88: 4ab3 ldr r2, [pc, #716] @ (8010258 ) 800ff8a: 4293 cmp r3, r2 800ff8c: d004 beq.n 800ff98 { tmpreg |= huart->Init.OneBitSampling; 800ff8e: 697b ldr r3, [r7, #20] 800ff90: 6a1b ldr r3, [r3, #32] 800ff92: 6c7a ldr r2, [r7, #68] @ 0x44 800ff94: 4313 orrs r3, r2 800ff96: 647b str r3, [r7, #68] @ 0x44 } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 800ff98: 697b ldr r3, [r7, #20] 800ff9a: 681b ldr r3, [r3, #0] 800ff9c: 689a ldr r2, [r3, #8] 800ff9e: 4baf ldr r3, [pc, #700] @ (801025c ) 800ffa0: 4013 ands r3, r2 800ffa2: 697a ldr r2, [r7, #20] 800ffa4: 6812 ldr r2, [r2, #0] 800ffa6: 6c79 ldr r1, [r7, #68] @ 0x44 800ffa8: 430b orrs r3, r1 800ffaa: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 800ffac: 697b ldr r3, [r7, #20] 800ffae: 681b ldr r3, [r3, #0] 800ffb0: 6adb ldr r3, [r3, #44] @ 0x2c 800ffb2: f023 010f bic.w r1, r3, #15 800ffb6: 697b ldr r3, [r7, #20] 800ffb8: 6a5a ldr r2, [r3, #36] @ 0x24 800ffba: 697b ldr r3, [r7, #20] 800ffbc: 681b ldr r3, [r3, #0] 800ffbe: 430a orrs r2, r1 800ffc0: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 800ffc2: 697b ldr r3, [r7, #20] 800ffc4: 681b ldr r3, [r3, #0] 800ffc6: 4aa6 ldr r2, [pc, #664] @ (8010260 ) 800ffc8: 4293 cmp r3, r2 800ffca: d177 bne.n 80100bc 800ffcc: 4ba5 ldr r3, [pc, #660] @ (8010264 ) 800ffce: 6d5b ldr r3, [r3, #84] @ 0x54 800ffd0: f003 0338 and.w r3, r3, #56 @ 0x38 800ffd4: 2b28 cmp r3, #40 @ 0x28 800ffd6: d86d bhi.n 80100b4 800ffd8: a201 add r2, pc, #4 @ (adr r2, 800ffe0 ) 800ffda: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ffde: bf00 nop 800ffe0: 08010085 .word 0x08010085 800ffe4: 080100b5 .word 0x080100b5 800ffe8: 080100b5 .word 0x080100b5 800ffec: 080100b5 .word 0x080100b5 800fff0: 080100b5 .word 0x080100b5 800fff4: 080100b5 .word 0x080100b5 800fff8: 080100b5 .word 0x080100b5 800fffc: 080100b5 .word 0x080100b5 8010000: 0801008d .word 0x0801008d 8010004: 080100b5 .word 0x080100b5 8010008: 080100b5 .word 0x080100b5 801000c: 080100b5 .word 0x080100b5 8010010: 080100b5 .word 0x080100b5 8010014: 080100b5 .word 0x080100b5 8010018: 080100b5 .word 0x080100b5 801001c: 080100b5 .word 0x080100b5 8010020: 08010095 .word 0x08010095 8010024: 080100b5 .word 0x080100b5 8010028: 080100b5 .word 0x080100b5 801002c: 080100b5 .word 0x080100b5 8010030: 080100b5 .word 0x080100b5 8010034: 080100b5 .word 0x080100b5 8010038: 080100b5 .word 0x080100b5 801003c: 080100b5 .word 0x080100b5 8010040: 0801009d .word 0x0801009d 8010044: 080100b5 .word 0x080100b5 8010048: 080100b5 .word 0x080100b5 801004c: 080100b5 .word 0x080100b5 8010050: 080100b5 .word 0x080100b5 8010054: 080100b5 .word 0x080100b5 8010058: 080100b5 .word 0x080100b5 801005c: 080100b5 .word 0x080100b5 8010060: 080100a5 .word 0x080100a5 8010064: 080100b5 .word 0x080100b5 8010068: 080100b5 .word 0x080100b5 801006c: 080100b5 .word 0x080100b5 8010070: 080100b5 .word 0x080100b5 8010074: 080100b5 .word 0x080100b5 8010078: 080100b5 .word 0x080100b5 801007c: 080100b5 .word 0x080100b5 8010080: 080100ad .word 0x080100ad 8010084: 2301 movs r3, #1 8010086: f887 3043 strb.w r3, [r7, #67] @ 0x43 801008a: e222 b.n 80104d2 801008c: 2304 movs r3, #4 801008e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010092: e21e b.n 80104d2 8010094: 2308 movs r3, #8 8010096: f887 3043 strb.w r3, [r7, #67] @ 0x43 801009a: e21a b.n 80104d2 801009c: 2310 movs r3, #16 801009e: f887 3043 strb.w r3, [r7, #67] @ 0x43 80100a2: e216 b.n 80104d2 80100a4: 2320 movs r3, #32 80100a6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80100aa: e212 b.n 80104d2 80100ac: 2340 movs r3, #64 @ 0x40 80100ae: f887 3043 strb.w r3, [r7, #67] @ 0x43 80100b2: e20e b.n 80104d2 80100b4: 2380 movs r3, #128 @ 0x80 80100b6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80100ba: e20a b.n 80104d2 80100bc: 697b ldr r3, [r7, #20] 80100be: 681b ldr r3, [r3, #0] 80100c0: 4a69 ldr r2, [pc, #420] @ (8010268 ) 80100c2: 4293 cmp r3, r2 80100c4: d130 bne.n 8010128 80100c6: 4b67 ldr r3, [pc, #412] @ (8010264 ) 80100c8: 6d5b ldr r3, [r3, #84] @ 0x54 80100ca: f003 0307 and.w r3, r3, #7 80100ce: 2b05 cmp r3, #5 80100d0: d826 bhi.n 8010120 80100d2: a201 add r2, pc, #4 @ (adr r2, 80100d8 ) 80100d4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80100d8: 080100f1 .word 0x080100f1 80100dc: 080100f9 .word 0x080100f9 80100e0: 08010101 .word 0x08010101 80100e4: 08010109 .word 0x08010109 80100e8: 08010111 .word 0x08010111 80100ec: 08010119 .word 0x08010119 80100f0: 2300 movs r3, #0 80100f2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80100f6: e1ec b.n 80104d2 80100f8: 2304 movs r3, #4 80100fa: f887 3043 strb.w r3, [r7, #67] @ 0x43 80100fe: e1e8 b.n 80104d2 8010100: 2308 movs r3, #8 8010102: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010106: e1e4 b.n 80104d2 8010108: 2310 movs r3, #16 801010a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801010e: e1e0 b.n 80104d2 8010110: 2320 movs r3, #32 8010112: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010116: e1dc b.n 80104d2 8010118: 2340 movs r3, #64 @ 0x40 801011a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801011e: e1d8 b.n 80104d2 8010120: 2380 movs r3, #128 @ 0x80 8010122: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010126: e1d4 b.n 80104d2 8010128: 697b ldr r3, [r7, #20] 801012a: 681b ldr r3, [r3, #0] 801012c: 4a4f ldr r2, [pc, #316] @ (801026c ) 801012e: 4293 cmp r3, r2 8010130: d130 bne.n 8010194 8010132: 4b4c ldr r3, [pc, #304] @ (8010264 ) 8010134: 6d5b ldr r3, [r3, #84] @ 0x54 8010136: f003 0307 and.w r3, r3, #7 801013a: 2b05 cmp r3, #5 801013c: d826 bhi.n 801018c 801013e: a201 add r2, pc, #4 @ (adr r2, 8010144 ) 8010140: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8010144: 0801015d .word 0x0801015d 8010148: 08010165 .word 0x08010165 801014c: 0801016d .word 0x0801016d 8010150: 08010175 .word 0x08010175 8010154: 0801017d .word 0x0801017d 8010158: 08010185 .word 0x08010185 801015c: 2300 movs r3, #0 801015e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010162: e1b6 b.n 80104d2 8010164: 2304 movs r3, #4 8010166: f887 3043 strb.w r3, [r7, #67] @ 0x43 801016a: e1b2 b.n 80104d2 801016c: 2308 movs r3, #8 801016e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010172: e1ae b.n 80104d2 8010174: 2310 movs r3, #16 8010176: f887 3043 strb.w r3, [r7, #67] @ 0x43 801017a: e1aa b.n 80104d2 801017c: 2320 movs r3, #32 801017e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010182: e1a6 b.n 80104d2 8010184: 2340 movs r3, #64 @ 0x40 8010186: f887 3043 strb.w r3, [r7, #67] @ 0x43 801018a: e1a2 b.n 80104d2 801018c: 2380 movs r3, #128 @ 0x80 801018e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010192: e19e b.n 80104d2 8010194: 697b ldr r3, [r7, #20] 8010196: 681b ldr r3, [r3, #0] 8010198: 4a35 ldr r2, [pc, #212] @ (8010270 ) 801019a: 4293 cmp r3, r2 801019c: d130 bne.n 8010200 801019e: 4b31 ldr r3, [pc, #196] @ (8010264 ) 80101a0: 6d5b ldr r3, [r3, #84] @ 0x54 80101a2: f003 0307 and.w r3, r3, #7 80101a6: 2b05 cmp r3, #5 80101a8: d826 bhi.n 80101f8 80101aa: a201 add r2, pc, #4 @ (adr r2, 80101b0 ) 80101ac: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80101b0: 080101c9 .word 0x080101c9 80101b4: 080101d1 .word 0x080101d1 80101b8: 080101d9 .word 0x080101d9 80101bc: 080101e1 .word 0x080101e1 80101c0: 080101e9 .word 0x080101e9 80101c4: 080101f1 .word 0x080101f1 80101c8: 2300 movs r3, #0 80101ca: f887 3043 strb.w r3, [r7, #67] @ 0x43 80101ce: e180 b.n 80104d2 80101d0: 2304 movs r3, #4 80101d2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80101d6: e17c b.n 80104d2 80101d8: 2308 movs r3, #8 80101da: f887 3043 strb.w r3, [r7, #67] @ 0x43 80101de: e178 b.n 80104d2 80101e0: 2310 movs r3, #16 80101e2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80101e6: e174 b.n 80104d2 80101e8: 2320 movs r3, #32 80101ea: f887 3043 strb.w r3, [r7, #67] @ 0x43 80101ee: e170 b.n 80104d2 80101f0: 2340 movs r3, #64 @ 0x40 80101f2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80101f6: e16c b.n 80104d2 80101f8: 2380 movs r3, #128 @ 0x80 80101fa: f887 3043 strb.w r3, [r7, #67] @ 0x43 80101fe: e168 b.n 80104d2 8010200: 697b ldr r3, [r7, #20] 8010202: 681b ldr r3, [r3, #0] 8010204: 4a1b ldr r2, [pc, #108] @ (8010274 ) 8010206: 4293 cmp r3, r2 8010208: d142 bne.n 8010290 801020a: 4b16 ldr r3, [pc, #88] @ (8010264 ) 801020c: 6d5b ldr r3, [r3, #84] @ 0x54 801020e: f003 0307 and.w r3, r3, #7 8010212: 2b05 cmp r3, #5 8010214: d838 bhi.n 8010288 8010216: a201 add r2, pc, #4 @ (adr r2, 801021c ) 8010218: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801021c: 08010235 .word 0x08010235 8010220: 0801023d .word 0x0801023d 8010224: 08010245 .word 0x08010245 8010228: 0801024d .word 0x0801024d 801022c: 08010279 .word 0x08010279 8010230: 08010281 .word 0x08010281 8010234: 2300 movs r3, #0 8010236: f887 3043 strb.w r3, [r7, #67] @ 0x43 801023a: e14a b.n 80104d2 801023c: 2304 movs r3, #4 801023e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010242: e146 b.n 80104d2 8010244: 2308 movs r3, #8 8010246: f887 3043 strb.w r3, [r7, #67] @ 0x43 801024a: e142 b.n 80104d2 801024c: 2310 movs r3, #16 801024e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010252: e13e b.n 80104d2 8010254: cfff69f3 .word 0xcfff69f3 8010258: 58000c00 .word 0x58000c00 801025c: 11fff4ff .word 0x11fff4ff 8010260: 40011000 .word 0x40011000 8010264: 58024400 .word 0x58024400 8010268: 40004400 .word 0x40004400 801026c: 40004800 .word 0x40004800 8010270: 40004c00 .word 0x40004c00 8010274: 40005000 .word 0x40005000 8010278: 2320 movs r3, #32 801027a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801027e: e128 b.n 80104d2 8010280: 2340 movs r3, #64 @ 0x40 8010282: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010286: e124 b.n 80104d2 8010288: 2380 movs r3, #128 @ 0x80 801028a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801028e: e120 b.n 80104d2 8010290: 697b ldr r3, [r7, #20] 8010292: 681b ldr r3, [r3, #0] 8010294: 4acb ldr r2, [pc, #812] @ (80105c4 ) 8010296: 4293 cmp r3, r2 8010298: d176 bne.n 8010388 801029a: 4bcb ldr r3, [pc, #812] @ (80105c8 ) 801029c: 6d5b ldr r3, [r3, #84] @ 0x54 801029e: f003 0338 and.w r3, r3, #56 @ 0x38 80102a2: 2b28 cmp r3, #40 @ 0x28 80102a4: d86c bhi.n 8010380 80102a6: a201 add r2, pc, #4 @ (adr r2, 80102ac ) 80102a8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80102ac: 08010351 .word 0x08010351 80102b0: 08010381 .word 0x08010381 80102b4: 08010381 .word 0x08010381 80102b8: 08010381 .word 0x08010381 80102bc: 08010381 .word 0x08010381 80102c0: 08010381 .word 0x08010381 80102c4: 08010381 .word 0x08010381 80102c8: 08010381 .word 0x08010381 80102cc: 08010359 .word 0x08010359 80102d0: 08010381 .word 0x08010381 80102d4: 08010381 .word 0x08010381 80102d8: 08010381 .word 0x08010381 80102dc: 08010381 .word 0x08010381 80102e0: 08010381 .word 0x08010381 80102e4: 08010381 .word 0x08010381 80102e8: 08010381 .word 0x08010381 80102ec: 08010361 .word 0x08010361 80102f0: 08010381 .word 0x08010381 80102f4: 08010381 .word 0x08010381 80102f8: 08010381 .word 0x08010381 80102fc: 08010381 .word 0x08010381 8010300: 08010381 .word 0x08010381 8010304: 08010381 .word 0x08010381 8010308: 08010381 .word 0x08010381 801030c: 08010369 .word 0x08010369 8010310: 08010381 .word 0x08010381 8010314: 08010381 .word 0x08010381 8010318: 08010381 .word 0x08010381 801031c: 08010381 .word 0x08010381 8010320: 08010381 .word 0x08010381 8010324: 08010381 .word 0x08010381 8010328: 08010381 .word 0x08010381 801032c: 08010371 .word 0x08010371 8010330: 08010381 .word 0x08010381 8010334: 08010381 .word 0x08010381 8010338: 08010381 .word 0x08010381 801033c: 08010381 .word 0x08010381 8010340: 08010381 .word 0x08010381 8010344: 08010381 .word 0x08010381 8010348: 08010381 .word 0x08010381 801034c: 08010379 .word 0x08010379 8010350: 2301 movs r3, #1 8010352: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010356: e0bc b.n 80104d2 8010358: 2304 movs r3, #4 801035a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801035e: e0b8 b.n 80104d2 8010360: 2308 movs r3, #8 8010362: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010366: e0b4 b.n 80104d2 8010368: 2310 movs r3, #16 801036a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801036e: e0b0 b.n 80104d2 8010370: 2320 movs r3, #32 8010372: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010376: e0ac b.n 80104d2 8010378: 2340 movs r3, #64 @ 0x40 801037a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801037e: e0a8 b.n 80104d2 8010380: 2380 movs r3, #128 @ 0x80 8010382: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010386: e0a4 b.n 80104d2 8010388: 697b ldr r3, [r7, #20] 801038a: 681b ldr r3, [r3, #0] 801038c: 4a8f ldr r2, [pc, #572] @ (80105cc ) 801038e: 4293 cmp r3, r2 8010390: d130 bne.n 80103f4 8010392: 4b8d ldr r3, [pc, #564] @ (80105c8 ) 8010394: 6d5b ldr r3, [r3, #84] @ 0x54 8010396: f003 0307 and.w r3, r3, #7 801039a: 2b05 cmp r3, #5 801039c: d826 bhi.n 80103ec 801039e: a201 add r2, pc, #4 @ (adr r2, 80103a4 ) 80103a0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80103a4: 080103bd .word 0x080103bd 80103a8: 080103c5 .word 0x080103c5 80103ac: 080103cd .word 0x080103cd 80103b0: 080103d5 .word 0x080103d5 80103b4: 080103dd .word 0x080103dd 80103b8: 080103e5 .word 0x080103e5 80103bc: 2300 movs r3, #0 80103be: f887 3043 strb.w r3, [r7, #67] @ 0x43 80103c2: e086 b.n 80104d2 80103c4: 2304 movs r3, #4 80103c6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80103ca: e082 b.n 80104d2 80103cc: 2308 movs r3, #8 80103ce: f887 3043 strb.w r3, [r7, #67] @ 0x43 80103d2: e07e b.n 80104d2 80103d4: 2310 movs r3, #16 80103d6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80103da: e07a b.n 80104d2 80103dc: 2320 movs r3, #32 80103de: f887 3043 strb.w r3, [r7, #67] @ 0x43 80103e2: e076 b.n 80104d2 80103e4: 2340 movs r3, #64 @ 0x40 80103e6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80103ea: e072 b.n 80104d2 80103ec: 2380 movs r3, #128 @ 0x80 80103ee: f887 3043 strb.w r3, [r7, #67] @ 0x43 80103f2: e06e b.n 80104d2 80103f4: 697b ldr r3, [r7, #20] 80103f6: 681b ldr r3, [r3, #0] 80103f8: 4a75 ldr r2, [pc, #468] @ (80105d0 ) 80103fa: 4293 cmp r3, r2 80103fc: d130 bne.n 8010460 80103fe: 4b72 ldr r3, [pc, #456] @ (80105c8 ) 8010400: 6d5b ldr r3, [r3, #84] @ 0x54 8010402: f003 0307 and.w r3, r3, #7 8010406: 2b05 cmp r3, #5 8010408: d826 bhi.n 8010458 801040a: a201 add r2, pc, #4 @ (adr r2, 8010410 ) 801040c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8010410: 08010429 .word 0x08010429 8010414: 08010431 .word 0x08010431 8010418: 08010439 .word 0x08010439 801041c: 08010441 .word 0x08010441 8010420: 08010449 .word 0x08010449 8010424: 08010451 .word 0x08010451 8010428: 2300 movs r3, #0 801042a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801042e: e050 b.n 80104d2 8010430: 2304 movs r3, #4 8010432: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010436: e04c b.n 80104d2 8010438: 2308 movs r3, #8 801043a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801043e: e048 b.n 80104d2 8010440: 2310 movs r3, #16 8010442: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010446: e044 b.n 80104d2 8010448: 2320 movs r3, #32 801044a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801044e: e040 b.n 80104d2 8010450: 2340 movs r3, #64 @ 0x40 8010452: f887 3043 strb.w r3, [r7, #67] @ 0x43 8010456: e03c b.n 80104d2 8010458: 2380 movs r3, #128 @ 0x80 801045a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801045e: e038 b.n 80104d2 8010460: 697b ldr r3, [r7, #20] 8010462: 681b ldr r3, [r3, #0] 8010464: 4a5b ldr r2, [pc, #364] @ (80105d4 ) 8010466: 4293 cmp r3, r2 8010468: d130 bne.n 80104cc 801046a: 4b57 ldr r3, [pc, #348] @ (80105c8 ) 801046c: 6d9b ldr r3, [r3, #88] @ 0x58 801046e: f003 0307 and.w r3, r3, #7 8010472: 2b05 cmp r3, #5 8010474: d826 bhi.n 80104c4 8010476: a201 add r2, pc, #4 @ (adr r2, 801047c ) 8010478: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801047c: 08010495 .word 0x08010495 8010480: 0801049d .word 0x0801049d 8010484: 080104a5 .word 0x080104a5 8010488: 080104ad .word 0x080104ad 801048c: 080104b5 .word 0x080104b5 8010490: 080104bd .word 0x080104bd 8010494: 2302 movs r3, #2 8010496: f887 3043 strb.w r3, [r7, #67] @ 0x43 801049a: e01a b.n 80104d2 801049c: 2304 movs r3, #4 801049e: f887 3043 strb.w r3, [r7, #67] @ 0x43 80104a2: e016 b.n 80104d2 80104a4: 2308 movs r3, #8 80104a6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80104aa: e012 b.n 80104d2 80104ac: 2310 movs r3, #16 80104ae: f887 3043 strb.w r3, [r7, #67] @ 0x43 80104b2: e00e b.n 80104d2 80104b4: 2320 movs r3, #32 80104b6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80104ba: e00a b.n 80104d2 80104bc: 2340 movs r3, #64 @ 0x40 80104be: f887 3043 strb.w r3, [r7, #67] @ 0x43 80104c2: e006 b.n 80104d2 80104c4: 2380 movs r3, #128 @ 0x80 80104c6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80104ca: e002 b.n 80104d2 80104cc: 2380 movs r3, #128 @ 0x80 80104ce: f887 3043 strb.w r3, [r7, #67] @ 0x43 /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 80104d2: 697b ldr r3, [r7, #20] 80104d4: 681b ldr r3, [r3, #0] 80104d6: 4a3f ldr r2, [pc, #252] @ (80105d4 ) 80104d8: 4293 cmp r3, r2 80104da: f040 80f8 bne.w 80106ce { /* Retrieve frequency clock */ switch (clocksource) 80104de: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 80104e2: 2b20 cmp r3, #32 80104e4: dc46 bgt.n 8010574 80104e6: 2b02 cmp r3, #2 80104e8: f2c0 8082 blt.w 80105f0 80104ec: 3b02 subs r3, #2 80104ee: 2b1e cmp r3, #30 80104f0: d87e bhi.n 80105f0 80104f2: a201 add r2, pc, #4 @ (adr r2, 80104f8 ) 80104f4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80104f8: 0801057b .word 0x0801057b 80104fc: 080105f1 .word 0x080105f1 8010500: 08010583 .word 0x08010583 8010504: 080105f1 .word 0x080105f1 8010508: 080105f1 .word 0x080105f1 801050c: 080105f1 .word 0x080105f1 8010510: 08010593 .word 0x08010593 8010514: 080105f1 .word 0x080105f1 8010518: 080105f1 .word 0x080105f1 801051c: 080105f1 .word 0x080105f1 8010520: 080105f1 .word 0x080105f1 8010524: 080105f1 .word 0x080105f1 8010528: 080105f1 .word 0x080105f1 801052c: 080105f1 .word 0x080105f1 8010530: 080105a3 .word 0x080105a3 8010534: 080105f1 .word 0x080105f1 8010538: 080105f1 .word 0x080105f1 801053c: 080105f1 .word 0x080105f1 8010540: 080105f1 .word 0x080105f1 8010544: 080105f1 .word 0x080105f1 8010548: 080105f1 .word 0x080105f1 801054c: 080105f1 .word 0x080105f1 8010550: 080105f1 .word 0x080105f1 8010554: 080105f1 .word 0x080105f1 8010558: 080105f1 .word 0x080105f1 801055c: 080105f1 .word 0x080105f1 8010560: 080105f1 .word 0x080105f1 8010564: 080105f1 .word 0x080105f1 8010568: 080105f1 .word 0x080105f1 801056c: 080105f1 .word 0x080105f1 8010570: 080105e3 .word 0x080105e3 8010574: 2b40 cmp r3, #64 @ 0x40 8010576: d037 beq.n 80105e8 8010578: e03a b.n 80105f0 { case UART_CLOCKSOURCE_D3PCLK1: pclk = HAL_RCCEx_GetD3PCLK1Freq(); 801057a: f7fc fdaf bl 800d0dc 801057e: 63f8 str r0, [r7, #60] @ 0x3c break; 8010580: e03c b.n 80105fc case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8010582: f107 0324 add.w r3, r7, #36 @ 0x24 8010586: 4618 mov r0, r3 8010588: f7fc fdbe bl 800d108 pclk = pll2_clocks.PLL2_Q_Frequency; 801058c: 6abb ldr r3, [r7, #40] @ 0x28 801058e: 63fb str r3, [r7, #60] @ 0x3c break; 8010590: e034 b.n 80105fc case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8010592: f107 0318 add.w r3, r7, #24 8010596: 4618 mov r0, r3 8010598: f7fc ff0a bl 800d3b0 pclk = pll3_clocks.PLL3_Q_Frequency; 801059c: 69fb ldr r3, [r7, #28] 801059e: 63fb str r3, [r7, #60] @ 0x3c break; 80105a0: e02c b.n 80105fc case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 80105a2: 4b09 ldr r3, [pc, #36] @ (80105c8 ) 80105a4: 681b ldr r3, [r3, #0] 80105a6: f003 0320 and.w r3, r3, #32 80105aa: 2b00 cmp r3, #0 80105ac: d016 beq.n 80105dc { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 80105ae: 4b06 ldr r3, [pc, #24] @ (80105c8 ) 80105b0: 681b ldr r3, [r3, #0] 80105b2: 08db lsrs r3, r3, #3 80105b4: f003 0303 and.w r3, r3, #3 80105b8: 4a07 ldr r2, [pc, #28] @ (80105d8 ) 80105ba: fa22 f303 lsr.w r3, r2, r3 80105be: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 80105c0: e01c b.n 80105fc 80105c2: bf00 nop 80105c4: 40011400 .word 0x40011400 80105c8: 58024400 .word 0x58024400 80105cc: 40007800 .word 0x40007800 80105d0: 40007c00 .word 0x40007c00 80105d4: 58000c00 .word 0x58000c00 80105d8: 03d09000 .word 0x03d09000 pclk = (uint32_t) HSI_VALUE; 80105dc: 4b9d ldr r3, [pc, #628] @ (8010854 ) 80105de: 63fb str r3, [r7, #60] @ 0x3c break; 80105e0: e00c b.n 80105fc case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 80105e2: 4b9d ldr r3, [pc, #628] @ (8010858 ) 80105e4: 63fb str r3, [r7, #60] @ 0x3c break; 80105e6: e009 b.n 80105fc case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 80105e8: f44f 4300 mov.w r3, #32768 @ 0x8000 80105ec: 63fb str r3, [r7, #60] @ 0x3c break; 80105ee: e005 b.n 80105fc default: pclk = 0U; 80105f0: 2300 movs r3, #0 80105f2: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 80105f4: 2301 movs r3, #1 80105f6: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 80105fa: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 80105fc: 6bfb ldr r3, [r7, #60] @ 0x3c 80105fe: 2b00 cmp r3, #0 8010600: f000 81de beq.w 80109c0 { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 8010604: 697b ldr r3, [r7, #20] 8010606: 6a5b ldr r3, [r3, #36] @ 0x24 8010608: 4a94 ldr r2, [pc, #592] @ (801085c ) 801060a: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 801060e: 461a mov r2, r3 8010610: 6bfb ldr r3, [r7, #60] @ 0x3c 8010612: fbb3 f3f2 udiv r3, r3, r2 8010616: 633b str r3, [r7, #48] @ 0x30 /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 8010618: 697b ldr r3, [r7, #20] 801061a: 685a ldr r2, [r3, #4] 801061c: 4613 mov r3, r2 801061e: 005b lsls r3, r3, #1 8010620: 4413 add r3, r2 8010622: 6b3a ldr r2, [r7, #48] @ 0x30 8010624: 429a cmp r2, r3 8010626: d305 bcc.n 8010634 (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) 8010628: 697b ldr r3, [r7, #20] 801062a: 685b ldr r3, [r3, #4] 801062c: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 801062e: 6b3a ldr r2, [r7, #48] @ 0x30 8010630: 429a cmp r2, r3 8010632: d903 bls.n 801063c { ret = HAL_ERROR; 8010634: 2301 movs r3, #1 8010636: f887 3042 strb.w r3, [r7, #66] @ 0x42 801063a: e1c1 b.n 80109c0 } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 801063c: 6bfb ldr r3, [r7, #60] @ 0x3c 801063e: 2200 movs r2, #0 8010640: 60bb str r3, [r7, #8] 8010642: 60fa str r2, [r7, #12] 8010644: 697b ldr r3, [r7, #20] 8010646: 6a5b ldr r3, [r3, #36] @ 0x24 8010648: 4a84 ldr r2, [pc, #528] @ (801085c ) 801064a: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 801064e: b29b uxth r3, r3 8010650: 2200 movs r2, #0 8010652: 603b str r3, [r7, #0] 8010654: 607a str r2, [r7, #4] 8010656: e9d7 2300 ldrd r2, r3, [r7] 801065a: e9d7 0102 ldrd r0, r1, [r7, #8] 801065e: f7ef fe8f bl 8000380 <__aeabi_uldivmod> 8010662: 4602 mov r2, r0 8010664: 460b mov r3, r1 8010666: 4610 mov r0, r2 8010668: 4619 mov r1, r3 801066a: f04f 0200 mov.w r2, #0 801066e: f04f 0300 mov.w r3, #0 8010672: 020b lsls r3, r1, #8 8010674: ea43 6310 orr.w r3, r3, r0, lsr #24 8010678: 0202 lsls r2, r0, #8 801067a: 6979 ldr r1, [r7, #20] 801067c: 6849 ldr r1, [r1, #4] 801067e: 0849 lsrs r1, r1, #1 8010680: 2000 movs r0, #0 8010682: 460c mov r4, r1 8010684: 4605 mov r5, r0 8010686: eb12 0804 adds.w r8, r2, r4 801068a: eb43 0905 adc.w r9, r3, r5 801068e: 697b ldr r3, [r7, #20] 8010690: 685b ldr r3, [r3, #4] 8010692: 2200 movs r2, #0 8010694: 469a mov sl, r3 8010696: 4693 mov fp, r2 8010698: 4652 mov r2, sl 801069a: 465b mov r3, fp 801069c: 4640 mov r0, r8 801069e: 4649 mov r1, r9 80106a0: f7ef fe6e bl 8000380 <__aeabi_uldivmod> 80106a4: 4602 mov r2, r0 80106a6: 460b mov r3, r1 80106a8: 4613 mov r3, r2 80106aa: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 80106ac: 6bbb ldr r3, [r7, #56] @ 0x38 80106ae: f5b3 7f40 cmp.w r3, #768 @ 0x300 80106b2: d308 bcc.n 80106c6 80106b4: 6bbb ldr r3, [r7, #56] @ 0x38 80106b6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80106ba: d204 bcs.n 80106c6 { huart->Instance->BRR = usartdiv; 80106bc: 697b ldr r3, [r7, #20] 80106be: 681b ldr r3, [r3, #0] 80106c0: 6bba ldr r2, [r7, #56] @ 0x38 80106c2: 60da str r2, [r3, #12] 80106c4: e17c b.n 80109c0 } else { ret = HAL_ERROR; 80106c6: 2301 movs r3, #1 80106c8: f887 3042 strb.w r3, [r7, #66] @ 0x42 80106cc: e178 b.n 80109c0 } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 80106ce: 697b ldr r3, [r7, #20] 80106d0: 69db ldr r3, [r3, #28] 80106d2: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 80106d6: f040 80c5 bne.w 8010864 { switch (clocksource) 80106da: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 80106de: 2b20 cmp r3, #32 80106e0: dc48 bgt.n 8010774 80106e2: 2b00 cmp r3, #0 80106e4: db7b blt.n 80107de 80106e6: 2b20 cmp r3, #32 80106e8: d879 bhi.n 80107de 80106ea: a201 add r2, pc, #4 @ (adr r2, 80106f0 ) 80106ec: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80106f0: 0801077b .word 0x0801077b 80106f4: 08010783 .word 0x08010783 80106f8: 080107df .word 0x080107df 80106fc: 080107df .word 0x080107df 8010700: 0801078b .word 0x0801078b 8010704: 080107df .word 0x080107df 8010708: 080107df .word 0x080107df 801070c: 080107df .word 0x080107df 8010710: 0801079b .word 0x0801079b 8010714: 080107df .word 0x080107df 8010718: 080107df .word 0x080107df 801071c: 080107df .word 0x080107df 8010720: 080107df .word 0x080107df 8010724: 080107df .word 0x080107df 8010728: 080107df .word 0x080107df 801072c: 080107df .word 0x080107df 8010730: 080107ab .word 0x080107ab 8010734: 080107df .word 0x080107df 8010738: 080107df .word 0x080107df 801073c: 080107df .word 0x080107df 8010740: 080107df .word 0x080107df 8010744: 080107df .word 0x080107df 8010748: 080107df .word 0x080107df 801074c: 080107df .word 0x080107df 8010750: 080107df .word 0x080107df 8010754: 080107df .word 0x080107df 8010758: 080107df .word 0x080107df 801075c: 080107df .word 0x080107df 8010760: 080107df .word 0x080107df 8010764: 080107df .word 0x080107df 8010768: 080107df .word 0x080107df 801076c: 080107df .word 0x080107df 8010770: 080107d1 .word 0x080107d1 8010774: 2b40 cmp r3, #64 @ 0x40 8010776: d02e beq.n 80107d6 8010778: e031 b.n 80107de { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 801077a: f7fa fcd3 bl 800b124 801077e: 63f8 str r0, [r7, #60] @ 0x3c break; 8010780: e033 b.n 80107ea case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8010782: f7fa fce5 bl 800b150 8010786: 63f8 str r0, [r7, #60] @ 0x3c break; 8010788: e02f b.n 80107ea case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 801078a: f107 0324 add.w r3, r7, #36 @ 0x24 801078e: 4618 mov r0, r3 8010790: f7fc fcba bl 800d108 pclk = pll2_clocks.PLL2_Q_Frequency; 8010794: 6abb ldr r3, [r7, #40] @ 0x28 8010796: 63fb str r3, [r7, #60] @ 0x3c break; 8010798: e027 b.n 80107ea case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 801079a: f107 0318 add.w r3, r7, #24 801079e: 4618 mov r0, r3 80107a0: f7fc fe06 bl 800d3b0 pclk = pll3_clocks.PLL3_Q_Frequency; 80107a4: 69fb ldr r3, [r7, #28] 80107a6: 63fb str r3, [r7, #60] @ 0x3c break; 80107a8: e01f b.n 80107ea case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 80107aa: 4b2d ldr r3, [pc, #180] @ (8010860 ) 80107ac: 681b ldr r3, [r3, #0] 80107ae: f003 0320 and.w r3, r3, #32 80107b2: 2b00 cmp r3, #0 80107b4: d009 beq.n 80107ca { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 80107b6: 4b2a ldr r3, [pc, #168] @ (8010860 ) 80107b8: 681b ldr r3, [r3, #0] 80107ba: 08db lsrs r3, r3, #3 80107bc: f003 0303 and.w r3, r3, #3 80107c0: 4a24 ldr r2, [pc, #144] @ (8010854 ) 80107c2: fa22 f303 lsr.w r3, r2, r3 80107c6: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 80107c8: e00f b.n 80107ea pclk = (uint32_t) HSI_VALUE; 80107ca: 4b22 ldr r3, [pc, #136] @ (8010854 ) 80107cc: 63fb str r3, [r7, #60] @ 0x3c break; 80107ce: e00c b.n 80107ea case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 80107d0: 4b21 ldr r3, [pc, #132] @ (8010858 ) 80107d2: 63fb str r3, [r7, #60] @ 0x3c break; 80107d4: e009 b.n 80107ea case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 80107d6: f44f 4300 mov.w r3, #32768 @ 0x8000 80107da: 63fb str r3, [r7, #60] @ 0x3c break; 80107dc: e005 b.n 80107ea default: pclk = 0U; 80107de: 2300 movs r3, #0 80107e0: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 80107e2: 2301 movs r3, #1 80107e4: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 80107e8: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 80107ea: 6bfb ldr r3, [r7, #60] @ 0x3c 80107ec: 2b00 cmp r3, #0 80107ee: f000 80e7 beq.w 80109c0 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 80107f2: 697b ldr r3, [r7, #20] 80107f4: 6a5b ldr r3, [r3, #36] @ 0x24 80107f6: 4a19 ldr r2, [pc, #100] @ (801085c ) 80107f8: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80107fc: 461a mov r2, r3 80107fe: 6bfb ldr r3, [r7, #60] @ 0x3c 8010800: fbb3 f3f2 udiv r3, r3, r2 8010804: 005a lsls r2, r3, #1 8010806: 697b ldr r3, [r7, #20] 8010808: 685b ldr r3, [r3, #4] 801080a: 085b lsrs r3, r3, #1 801080c: 441a add r2, r3 801080e: 697b ldr r3, [r7, #20] 8010810: 685b ldr r3, [r3, #4] 8010812: fbb2 f3f3 udiv r3, r2, r3 8010816: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8010818: 6bbb ldr r3, [r7, #56] @ 0x38 801081a: 2b0f cmp r3, #15 801081c: d916 bls.n 801084c 801081e: 6bbb ldr r3, [r7, #56] @ 0x38 8010820: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010824: d212 bcs.n 801084c { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 8010826: 6bbb ldr r3, [r7, #56] @ 0x38 8010828: b29b uxth r3, r3 801082a: f023 030f bic.w r3, r3, #15 801082e: 86fb strh r3, [r7, #54] @ 0x36 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8010830: 6bbb ldr r3, [r7, #56] @ 0x38 8010832: 085b lsrs r3, r3, #1 8010834: b29b uxth r3, r3 8010836: f003 0307 and.w r3, r3, #7 801083a: b29a uxth r2, r3 801083c: 8efb ldrh r3, [r7, #54] @ 0x36 801083e: 4313 orrs r3, r2 8010840: 86fb strh r3, [r7, #54] @ 0x36 huart->Instance->BRR = brrtemp; 8010842: 697b ldr r3, [r7, #20] 8010844: 681b ldr r3, [r3, #0] 8010846: 8efa ldrh r2, [r7, #54] @ 0x36 8010848: 60da str r2, [r3, #12] 801084a: e0b9 b.n 80109c0 } else { ret = HAL_ERROR; 801084c: 2301 movs r3, #1 801084e: f887 3042 strb.w r3, [r7, #66] @ 0x42 8010852: e0b5 b.n 80109c0 8010854: 03d09000 .word 0x03d09000 8010858: 003d0900 .word 0x003d0900 801085c: 080175e0 .word 0x080175e0 8010860: 58024400 .word 0x58024400 } } } else { switch (clocksource) 8010864: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 8010868: 2b20 cmp r3, #32 801086a: dc49 bgt.n 8010900 801086c: 2b00 cmp r3, #0 801086e: db7c blt.n 801096a 8010870: 2b20 cmp r3, #32 8010872: d87a bhi.n 801096a 8010874: a201 add r2, pc, #4 @ (adr r2, 801087c ) 8010876: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801087a: bf00 nop 801087c: 08010907 .word 0x08010907 8010880: 0801090f .word 0x0801090f 8010884: 0801096b .word 0x0801096b 8010888: 0801096b .word 0x0801096b 801088c: 08010917 .word 0x08010917 8010890: 0801096b .word 0x0801096b 8010894: 0801096b .word 0x0801096b 8010898: 0801096b .word 0x0801096b 801089c: 08010927 .word 0x08010927 80108a0: 0801096b .word 0x0801096b 80108a4: 0801096b .word 0x0801096b 80108a8: 0801096b .word 0x0801096b 80108ac: 0801096b .word 0x0801096b 80108b0: 0801096b .word 0x0801096b 80108b4: 0801096b .word 0x0801096b 80108b8: 0801096b .word 0x0801096b 80108bc: 08010937 .word 0x08010937 80108c0: 0801096b .word 0x0801096b 80108c4: 0801096b .word 0x0801096b 80108c8: 0801096b .word 0x0801096b 80108cc: 0801096b .word 0x0801096b 80108d0: 0801096b .word 0x0801096b 80108d4: 0801096b .word 0x0801096b 80108d8: 0801096b .word 0x0801096b 80108dc: 0801096b .word 0x0801096b 80108e0: 0801096b .word 0x0801096b 80108e4: 0801096b .word 0x0801096b 80108e8: 0801096b .word 0x0801096b 80108ec: 0801096b .word 0x0801096b 80108f0: 0801096b .word 0x0801096b 80108f4: 0801096b .word 0x0801096b 80108f8: 0801096b .word 0x0801096b 80108fc: 0801095d .word 0x0801095d 8010900: 2b40 cmp r3, #64 @ 0x40 8010902: d02e beq.n 8010962 8010904: e031 b.n 801096a { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8010906: f7fa fc0d bl 800b124 801090a: 63f8 str r0, [r7, #60] @ 0x3c break; 801090c: e033 b.n 8010976 case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 801090e: f7fa fc1f bl 800b150 8010912: 63f8 str r0, [r7, #60] @ 0x3c break; 8010914: e02f b.n 8010976 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8010916: f107 0324 add.w r3, r7, #36 @ 0x24 801091a: 4618 mov r0, r3 801091c: f7fc fbf4 bl 800d108 pclk = pll2_clocks.PLL2_Q_Frequency; 8010920: 6abb ldr r3, [r7, #40] @ 0x28 8010922: 63fb str r3, [r7, #60] @ 0x3c break; 8010924: e027 b.n 8010976 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8010926: f107 0318 add.w r3, r7, #24 801092a: 4618 mov r0, r3 801092c: f7fc fd40 bl 800d3b0 pclk = pll3_clocks.PLL3_Q_Frequency; 8010930: 69fb ldr r3, [r7, #28] 8010932: 63fb str r3, [r7, #60] @ 0x3c break; 8010934: e01f b.n 8010976 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8010936: 4b2d ldr r3, [pc, #180] @ (80109ec ) 8010938: 681b ldr r3, [r3, #0] 801093a: f003 0320 and.w r3, r3, #32 801093e: 2b00 cmp r3, #0 8010940: d009 beq.n 8010956 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8010942: 4b2a ldr r3, [pc, #168] @ (80109ec ) 8010944: 681b ldr r3, [r3, #0] 8010946: 08db lsrs r3, r3, #3 8010948: f003 0303 and.w r3, r3, #3 801094c: 4a28 ldr r2, [pc, #160] @ (80109f0 ) 801094e: fa22 f303 lsr.w r3, r2, r3 8010952: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8010954: e00f b.n 8010976 pclk = (uint32_t) HSI_VALUE; 8010956: 4b26 ldr r3, [pc, #152] @ (80109f0 ) 8010958: 63fb str r3, [r7, #60] @ 0x3c break; 801095a: e00c b.n 8010976 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 801095c: 4b25 ldr r3, [pc, #148] @ (80109f4 ) 801095e: 63fb str r3, [r7, #60] @ 0x3c break; 8010960: e009 b.n 8010976 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8010962: f44f 4300 mov.w r3, #32768 @ 0x8000 8010966: 63fb str r3, [r7, #60] @ 0x3c break; 8010968: e005 b.n 8010976 default: pclk = 0U; 801096a: 2300 movs r3, #0 801096c: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 801096e: 2301 movs r3, #1 8010970: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 8010974: bf00 nop } if (pclk != 0U) 8010976: 6bfb ldr r3, [r7, #60] @ 0x3c 8010978: 2b00 cmp r3, #0 801097a: d021 beq.n 80109c0 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 801097c: 697b ldr r3, [r7, #20] 801097e: 6a5b ldr r3, [r3, #36] @ 0x24 8010980: 4a1d ldr r2, [pc, #116] @ (80109f8 ) 8010982: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8010986: 461a mov r2, r3 8010988: 6bfb ldr r3, [r7, #60] @ 0x3c 801098a: fbb3 f2f2 udiv r2, r3, r2 801098e: 697b ldr r3, [r7, #20] 8010990: 685b ldr r3, [r3, #4] 8010992: 085b lsrs r3, r3, #1 8010994: 441a add r2, r3 8010996: 697b ldr r3, [r7, #20] 8010998: 685b ldr r3, [r3, #4] 801099a: fbb2 f3f3 udiv r3, r2, r3 801099e: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 80109a0: 6bbb ldr r3, [r7, #56] @ 0x38 80109a2: 2b0f cmp r3, #15 80109a4: d909 bls.n 80109ba 80109a6: 6bbb ldr r3, [r7, #56] @ 0x38 80109a8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80109ac: d205 bcs.n 80109ba { huart->Instance->BRR = (uint16_t)usartdiv; 80109ae: 6bbb ldr r3, [r7, #56] @ 0x38 80109b0: b29a uxth r2, r3 80109b2: 697b ldr r3, [r7, #20] 80109b4: 681b ldr r3, [r3, #0] 80109b6: 60da str r2, [r3, #12] 80109b8: e002 b.n 80109c0 } else { ret = HAL_ERROR; 80109ba: 2301 movs r3, #1 80109bc: f887 3042 strb.w r3, [r7, #66] @ 0x42 } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 80109c0: 697b ldr r3, [r7, #20] 80109c2: 2201 movs r2, #1 80109c4: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1; 80109c8: 697b ldr r3, [r7, #20] 80109ca: 2201 movs r2, #1 80109cc: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; 80109d0: 697b ldr r3, [r7, #20] 80109d2: 2200 movs r2, #0 80109d4: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 80109d6: 697b ldr r3, [r7, #20] 80109d8: 2200 movs r2, #0 80109da: 679a str r2, [r3, #120] @ 0x78 return ret; 80109dc: f897 3042 ldrb.w r3, [r7, #66] @ 0x42 } 80109e0: 4618 mov r0, r3 80109e2: 3748 adds r7, #72 @ 0x48 80109e4: 46bd mov sp, r7 80109e6: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 80109ea: bf00 nop 80109ec: 58024400 .word 0x58024400 80109f0: 03d09000 .word 0x03d09000 80109f4: 003d0900 .word 0x003d0900 80109f8: 080175e0 .word 0x080175e0 080109fc : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 80109fc: b480 push {r7} 80109fe: b083 sub sp, #12 8010a00: af00 add r7, sp, #0 8010a02: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 8010a04: 687b ldr r3, [r7, #4] 8010a06: 6a9b ldr r3, [r3, #40] @ 0x28 8010a08: f003 0308 and.w r3, r3, #8 8010a0c: 2b00 cmp r3, #0 8010a0e: d00a beq.n 8010a26 { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 8010a10: 687b ldr r3, [r7, #4] 8010a12: 681b ldr r3, [r3, #0] 8010a14: 685b ldr r3, [r3, #4] 8010a16: f423 4100 bic.w r1, r3, #32768 @ 0x8000 8010a1a: 687b ldr r3, [r7, #4] 8010a1c: 6b9a ldr r2, [r3, #56] @ 0x38 8010a1e: 687b ldr r3, [r7, #4] 8010a20: 681b ldr r3, [r3, #0] 8010a22: 430a orrs r2, r1 8010a24: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 8010a26: 687b ldr r3, [r7, #4] 8010a28: 6a9b ldr r3, [r3, #40] @ 0x28 8010a2a: f003 0301 and.w r3, r3, #1 8010a2e: 2b00 cmp r3, #0 8010a30: d00a beq.n 8010a48 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 8010a32: 687b ldr r3, [r7, #4] 8010a34: 681b ldr r3, [r3, #0] 8010a36: 685b ldr r3, [r3, #4] 8010a38: f423 3100 bic.w r1, r3, #131072 @ 0x20000 8010a3c: 687b ldr r3, [r7, #4] 8010a3e: 6ada ldr r2, [r3, #44] @ 0x2c 8010a40: 687b ldr r3, [r7, #4] 8010a42: 681b ldr r3, [r3, #0] 8010a44: 430a orrs r2, r1 8010a46: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 8010a48: 687b ldr r3, [r7, #4] 8010a4a: 6a9b ldr r3, [r3, #40] @ 0x28 8010a4c: f003 0302 and.w r3, r3, #2 8010a50: 2b00 cmp r3, #0 8010a52: d00a beq.n 8010a6a { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 8010a54: 687b ldr r3, [r7, #4] 8010a56: 681b ldr r3, [r3, #0] 8010a58: 685b ldr r3, [r3, #4] 8010a5a: f423 3180 bic.w r1, r3, #65536 @ 0x10000 8010a5e: 687b ldr r3, [r7, #4] 8010a60: 6b1a ldr r2, [r3, #48] @ 0x30 8010a62: 687b ldr r3, [r7, #4] 8010a64: 681b ldr r3, [r3, #0] 8010a66: 430a orrs r2, r1 8010a68: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 8010a6a: 687b ldr r3, [r7, #4] 8010a6c: 6a9b ldr r3, [r3, #40] @ 0x28 8010a6e: f003 0304 and.w r3, r3, #4 8010a72: 2b00 cmp r3, #0 8010a74: d00a beq.n 8010a8c { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 8010a76: 687b ldr r3, [r7, #4] 8010a78: 681b ldr r3, [r3, #0] 8010a7a: 685b ldr r3, [r3, #4] 8010a7c: f423 2180 bic.w r1, r3, #262144 @ 0x40000 8010a80: 687b ldr r3, [r7, #4] 8010a82: 6b5a ldr r2, [r3, #52] @ 0x34 8010a84: 687b ldr r3, [r7, #4] 8010a86: 681b ldr r3, [r3, #0] 8010a88: 430a orrs r2, r1 8010a8a: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 8010a8c: 687b ldr r3, [r7, #4] 8010a8e: 6a9b ldr r3, [r3, #40] @ 0x28 8010a90: f003 0310 and.w r3, r3, #16 8010a94: 2b00 cmp r3, #0 8010a96: d00a beq.n 8010aae { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 8010a98: 687b ldr r3, [r7, #4] 8010a9a: 681b ldr r3, [r3, #0] 8010a9c: 689b ldr r3, [r3, #8] 8010a9e: f423 5180 bic.w r1, r3, #4096 @ 0x1000 8010aa2: 687b ldr r3, [r7, #4] 8010aa4: 6bda ldr r2, [r3, #60] @ 0x3c 8010aa6: 687b ldr r3, [r7, #4] 8010aa8: 681b ldr r3, [r3, #0] 8010aaa: 430a orrs r2, r1 8010aac: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 8010aae: 687b ldr r3, [r7, #4] 8010ab0: 6a9b ldr r3, [r3, #40] @ 0x28 8010ab2: f003 0320 and.w r3, r3, #32 8010ab6: 2b00 cmp r3, #0 8010ab8: d00a beq.n 8010ad0 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 8010aba: 687b ldr r3, [r7, #4] 8010abc: 681b ldr r3, [r3, #0] 8010abe: 689b ldr r3, [r3, #8] 8010ac0: f423 5100 bic.w r1, r3, #8192 @ 0x2000 8010ac4: 687b ldr r3, [r7, #4] 8010ac6: 6c1a ldr r2, [r3, #64] @ 0x40 8010ac8: 687b ldr r3, [r7, #4] 8010aca: 681b ldr r3, [r3, #0] 8010acc: 430a orrs r2, r1 8010ace: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 8010ad0: 687b ldr r3, [r7, #4] 8010ad2: 6a9b ldr r3, [r3, #40] @ 0x28 8010ad4: f003 0340 and.w r3, r3, #64 @ 0x40 8010ad8: 2b00 cmp r3, #0 8010ada: d01a beq.n 8010b12 { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 8010adc: 687b ldr r3, [r7, #4] 8010ade: 681b ldr r3, [r3, #0] 8010ae0: 685b ldr r3, [r3, #4] 8010ae2: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 8010ae6: 687b ldr r3, [r7, #4] 8010ae8: 6c5a ldr r2, [r3, #68] @ 0x44 8010aea: 687b ldr r3, [r7, #4] 8010aec: 681b ldr r3, [r3, #0] 8010aee: 430a orrs r2, r1 8010af0: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 8010af2: 687b ldr r3, [r7, #4] 8010af4: 6c5b ldr r3, [r3, #68] @ 0x44 8010af6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8010afa: d10a bne.n 8010b12 { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 8010afc: 687b ldr r3, [r7, #4] 8010afe: 681b ldr r3, [r3, #0] 8010b00: 685b ldr r3, [r3, #4] 8010b02: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 8010b06: 687b ldr r3, [r7, #4] 8010b08: 6c9a ldr r2, [r3, #72] @ 0x48 8010b0a: 687b ldr r3, [r7, #4] 8010b0c: 681b ldr r3, [r3, #0] 8010b0e: 430a orrs r2, r1 8010b10: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 8010b12: 687b ldr r3, [r7, #4] 8010b14: 6a9b ldr r3, [r3, #40] @ 0x28 8010b16: f003 0380 and.w r3, r3, #128 @ 0x80 8010b1a: 2b00 cmp r3, #0 8010b1c: d00a beq.n 8010b34 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 8010b1e: 687b ldr r3, [r7, #4] 8010b20: 681b ldr r3, [r3, #0] 8010b22: 685b ldr r3, [r3, #4] 8010b24: f423 2100 bic.w r1, r3, #524288 @ 0x80000 8010b28: 687b ldr r3, [r7, #4] 8010b2a: 6cda ldr r2, [r3, #76] @ 0x4c 8010b2c: 687b ldr r3, [r7, #4] 8010b2e: 681b ldr r3, [r3, #0] 8010b30: 430a orrs r2, r1 8010b32: 605a str r2, [r3, #4] } } 8010b34: bf00 nop 8010b36: 370c adds r7, #12 8010b38: 46bd mov sp, r7 8010b3a: f85d 7b04 ldr.w r7, [sp], #4 8010b3e: 4770 bx lr 08010b40 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 8010b40: b580 push {r7, lr} 8010b42: b098 sub sp, #96 @ 0x60 8010b44: af02 add r7, sp, #8 8010b46: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8010b48: 687b ldr r3, [r7, #4] 8010b4a: 2200 movs r2, #0 8010b4c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8010b50: f7f3 ff88 bl 8004a64 8010b54: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 8010b56: 687b ldr r3, [r7, #4] 8010b58: 681b ldr r3, [r3, #0] 8010b5a: 681b ldr r3, [r3, #0] 8010b5c: f003 0308 and.w r3, r3, #8 8010b60: 2b08 cmp r3, #8 8010b62: d12f bne.n 8010bc4 { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8010b64: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8010b68: 9300 str r3, [sp, #0] 8010b6a: 6d7b ldr r3, [r7, #84] @ 0x54 8010b6c: 2200 movs r2, #0 8010b6e: f44f 1100 mov.w r1, #2097152 @ 0x200000 8010b72: 6878 ldr r0, [r7, #4] 8010b74: f000 f88e bl 8010c94 8010b78: 4603 mov r3, r0 8010b7a: 2b00 cmp r3, #0 8010b7c: d022 beq.n 8010bc4 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 8010b7e: 687b ldr r3, [r7, #4] 8010b80: 681b ldr r3, [r3, #0] 8010b82: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010b84: 6bbb ldr r3, [r7, #56] @ 0x38 8010b86: e853 3f00 ldrex r3, [r3] 8010b8a: 637b str r3, [r7, #52] @ 0x34 return(result); 8010b8c: 6b7b ldr r3, [r7, #52] @ 0x34 8010b8e: f023 0380 bic.w r3, r3, #128 @ 0x80 8010b92: 653b str r3, [r7, #80] @ 0x50 8010b94: 687b ldr r3, [r7, #4] 8010b96: 681b ldr r3, [r3, #0] 8010b98: 461a mov r2, r3 8010b9a: 6d3b ldr r3, [r7, #80] @ 0x50 8010b9c: 647b str r3, [r7, #68] @ 0x44 8010b9e: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010ba0: 6c39 ldr r1, [r7, #64] @ 0x40 8010ba2: 6c7a ldr r2, [r7, #68] @ 0x44 8010ba4: e841 2300 strex r3, r2, [r1] 8010ba8: 63fb str r3, [r7, #60] @ 0x3c return(result); 8010baa: 6bfb ldr r3, [r7, #60] @ 0x3c 8010bac: 2b00 cmp r3, #0 8010bae: d1e6 bne.n 8010b7e huart->gState = HAL_UART_STATE_READY; 8010bb0: 687b ldr r3, [r7, #4] 8010bb2: 2220 movs r2, #32 8010bb4: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); 8010bb8: 687b ldr r3, [r7, #4] 8010bba: 2200 movs r2, #0 8010bbc: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8010bc0: 2303 movs r3, #3 8010bc2: e063 b.n 8010c8c } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 8010bc4: 687b ldr r3, [r7, #4] 8010bc6: 681b ldr r3, [r3, #0] 8010bc8: 681b ldr r3, [r3, #0] 8010bca: f003 0304 and.w r3, r3, #4 8010bce: 2b04 cmp r3, #4 8010bd0: d149 bne.n 8010c66 { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8010bd2: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8010bd6: 9300 str r3, [sp, #0] 8010bd8: 6d7b ldr r3, [r7, #84] @ 0x54 8010bda: 2200 movs r2, #0 8010bdc: f44f 0180 mov.w r1, #4194304 @ 0x400000 8010be0: 6878 ldr r0, [r7, #4] 8010be2: f000 f857 bl 8010c94 8010be6: 4603 mov r3, r0 8010be8: 2b00 cmp r3, #0 8010bea: d03c beq.n 8010c66 { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8010bec: 687b ldr r3, [r7, #4] 8010bee: 681b ldr r3, [r3, #0] 8010bf0: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010bf2: 6a7b ldr r3, [r7, #36] @ 0x24 8010bf4: e853 3f00 ldrex r3, [r3] 8010bf8: 623b str r3, [r7, #32] return(result); 8010bfa: 6a3b ldr r3, [r7, #32] 8010bfc: f423 7390 bic.w r3, r3, #288 @ 0x120 8010c00: 64fb str r3, [r7, #76] @ 0x4c 8010c02: 687b ldr r3, [r7, #4] 8010c04: 681b ldr r3, [r3, #0] 8010c06: 461a mov r2, r3 8010c08: 6cfb ldr r3, [r7, #76] @ 0x4c 8010c0a: 633b str r3, [r7, #48] @ 0x30 8010c0c: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010c0e: 6af9 ldr r1, [r7, #44] @ 0x2c 8010c10: 6b3a ldr r2, [r7, #48] @ 0x30 8010c12: e841 2300 strex r3, r2, [r1] 8010c16: 62bb str r3, [r7, #40] @ 0x28 return(result); 8010c18: 6abb ldr r3, [r7, #40] @ 0x28 8010c1a: 2b00 cmp r3, #0 8010c1c: d1e6 bne.n 8010bec ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8010c1e: 687b ldr r3, [r7, #4] 8010c20: 681b ldr r3, [r3, #0] 8010c22: 3308 adds r3, #8 8010c24: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010c26: 693b ldr r3, [r7, #16] 8010c28: e853 3f00 ldrex r3, [r3] 8010c2c: 60fb str r3, [r7, #12] return(result); 8010c2e: 68fb ldr r3, [r7, #12] 8010c30: f023 0301 bic.w r3, r3, #1 8010c34: 64bb str r3, [r7, #72] @ 0x48 8010c36: 687b ldr r3, [r7, #4] 8010c38: 681b ldr r3, [r3, #0] 8010c3a: 3308 adds r3, #8 8010c3c: 6cba ldr r2, [r7, #72] @ 0x48 8010c3e: 61fa str r2, [r7, #28] 8010c40: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010c42: 69b9 ldr r1, [r7, #24] 8010c44: 69fa ldr r2, [r7, #28] 8010c46: e841 2300 strex r3, r2, [r1] 8010c4a: 617b str r3, [r7, #20] return(result); 8010c4c: 697b ldr r3, [r7, #20] 8010c4e: 2b00 cmp r3, #0 8010c50: d1e5 bne.n 8010c1e huart->RxState = HAL_UART_STATE_READY; 8010c52: 687b ldr r3, [r7, #4] 8010c54: 2220 movs r2, #32 8010c56: f8c3 208c str.w r2, [r3, #140] @ 0x8c __HAL_UNLOCK(huart); 8010c5a: 687b ldr r3, [r7, #4] 8010c5c: 2200 movs r2, #0 8010c5e: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8010c62: 2303 movs r3, #3 8010c64: e012 b.n 8010c8c } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 8010c66: 687b ldr r3, [r7, #4] 8010c68: 2220 movs r2, #32 8010c6a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 huart->RxState = HAL_UART_STATE_READY; 8010c6e: 687b ldr r3, [r7, #4] 8010c70: 2220 movs r2, #32 8010c72: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8010c76: 687b ldr r3, [r7, #4] 8010c78: 2200 movs r2, #0 8010c7a: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8010c7c: 687b ldr r3, [r7, #4] 8010c7e: 2200 movs r2, #0 8010c80: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 8010c82: 687b ldr r3, [r7, #4] 8010c84: 2200 movs r2, #0 8010c86: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8010c8a: 2300 movs r3, #0 } 8010c8c: 4618 mov r0, r3 8010c8e: 3758 adds r7, #88 @ 0x58 8010c90: 46bd mov sp, r7 8010c92: bd80 pop {r7, pc} 08010c94 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8010c94: b580 push {r7, lr} 8010c96: b084 sub sp, #16 8010c98: af00 add r7, sp, #0 8010c9a: 60f8 str r0, [r7, #12] 8010c9c: 60b9 str r1, [r7, #8] 8010c9e: 603b str r3, [r7, #0] 8010ca0: 4613 mov r3, r2 8010ca2: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8010ca4: e04f b.n 8010d46 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8010ca6: 69bb ldr r3, [r7, #24] 8010ca8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8010cac: d04b beq.n 8010d46 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8010cae: f7f3 fed9 bl 8004a64 8010cb2: 4602 mov r2, r0 8010cb4: 683b ldr r3, [r7, #0] 8010cb6: 1ad3 subs r3, r2, r3 8010cb8: 69ba ldr r2, [r7, #24] 8010cba: 429a cmp r2, r3 8010cbc: d302 bcc.n 8010cc4 8010cbe: 69bb ldr r3, [r7, #24] 8010cc0: 2b00 cmp r3, #0 8010cc2: d101 bne.n 8010cc8 { return HAL_TIMEOUT; 8010cc4: 2303 movs r3, #3 8010cc6: e04e b.n 8010d66 } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 8010cc8: 68fb ldr r3, [r7, #12] 8010cca: 681b ldr r3, [r3, #0] 8010ccc: 681b ldr r3, [r3, #0] 8010cce: f003 0304 and.w r3, r3, #4 8010cd2: 2b00 cmp r3, #0 8010cd4: d037 beq.n 8010d46 8010cd6: 68bb ldr r3, [r7, #8] 8010cd8: 2b80 cmp r3, #128 @ 0x80 8010cda: d034 beq.n 8010d46 8010cdc: 68bb ldr r3, [r7, #8] 8010cde: 2b40 cmp r3, #64 @ 0x40 8010ce0: d031 beq.n 8010d46 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8010ce2: 68fb ldr r3, [r7, #12] 8010ce4: 681b ldr r3, [r3, #0] 8010ce6: 69db ldr r3, [r3, #28] 8010ce8: f003 0308 and.w r3, r3, #8 8010cec: 2b08 cmp r3, #8 8010cee: d110 bne.n 8010d12 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8010cf0: 68fb ldr r3, [r7, #12] 8010cf2: 681b ldr r3, [r3, #0] 8010cf4: 2208 movs r2, #8 8010cf6: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8010cf8: 68f8 ldr r0, [r7, #12] 8010cfa: f000 f95b bl 8010fb4 huart->ErrorCode = HAL_UART_ERROR_ORE; 8010cfe: 68fb ldr r3, [r7, #12] 8010d00: 2208 movs r2, #8 8010d02: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8010d06: 68fb ldr r3, [r7, #12] 8010d08: 2200 movs r2, #0 8010d0a: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_ERROR; 8010d0e: 2301 movs r3, #1 8010d10: e029 b.n 8010d66 } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8010d12: 68fb ldr r3, [r7, #12] 8010d14: 681b ldr r3, [r3, #0] 8010d16: 69db ldr r3, [r3, #28] 8010d18: f403 6300 and.w r3, r3, #2048 @ 0x800 8010d1c: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8010d20: d111 bne.n 8010d46 { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8010d22: 68fb ldr r3, [r7, #12] 8010d24: 681b ldr r3, [r3, #0] 8010d26: f44f 6200 mov.w r2, #2048 @ 0x800 8010d2a: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8010d2c: 68f8 ldr r0, [r7, #12] 8010d2e: f000 f941 bl 8010fb4 huart->ErrorCode = HAL_UART_ERROR_RTO; 8010d32: 68fb ldr r3, [r7, #12] 8010d34: 2220 movs r2, #32 8010d36: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8010d3a: 68fb ldr r3, [r7, #12] 8010d3c: 2200 movs r2, #0 8010d3e: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_TIMEOUT; 8010d42: 2303 movs r3, #3 8010d44: e00f b.n 8010d66 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8010d46: 68fb ldr r3, [r7, #12] 8010d48: 681b ldr r3, [r3, #0] 8010d4a: 69da ldr r2, [r3, #28] 8010d4c: 68bb ldr r3, [r7, #8] 8010d4e: 4013 ands r3, r2 8010d50: 68ba ldr r2, [r7, #8] 8010d52: 429a cmp r2, r3 8010d54: bf0c ite eq 8010d56: 2301 moveq r3, #1 8010d58: 2300 movne r3, #0 8010d5a: b2db uxtb r3, r3 8010d5c: 461a mov r2, r3 8010d5e: 79fb ldrb r3, [r7, #7] 8010d60: 429a cmp r2, r3 8010d62: d0a0 beq.n 8010ca6 } } } } return HAL_OK; 8010d64: 2300 movs r3, #0 } 8010d66: 4618 mov r0, r3 8010d68: 3710 adds r7, #16 8010d6a: 46bd mov sp, r7 8010d6c: bd80 pop {r7, pc} ... 08010d70 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8010d70: b480 push {r7} 8010d72: b0a3 sub sp, #140 @ 0x8c 8010d74: af00 add r7, sp, #0 8010d76: 60f8 str r0, [r7, #12] 8010d78: 60b9 str r1, [r7, #8] 8010d7a: 4613 mov r3, r2 8010d7c: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 8010d7e: 68fb ldr r3, [r7, #12] 8010d80: 68ba ldr r2, [r7, #8] 8010d82: 659a str r2, [r3, #88] @ 0x58 huart->RxXferSize = Size; 8010d84: 68fb ldr r3, [r7, #12] 8010d86: 88fa ldrh r2, [r7, #6] 8010d88: f8a3 205c strh.w r2, [r3, #92] @ 0x5c huart->RxXferCount = Size; 8010d8c: 68fb ldr r3, [r7, #12] 8010d8e: 88fa ldrh r2, [r7, #6] 8010d90: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->RxISR = NULL; 8010d94: 68fb ldr r3, [r7, #12] 8010d96: 2200 movs r2, #0 8010d98: 675a str r2, [r3, #116] @ 0x74 /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); 8010d9a: 68fb ldr r3, [r7, #12] 8010d9c: 689b ldr r3, [r3, #8] 8010d9e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8010da2: d10e bne.n 8010dc2 8010da4: 68fb ldr r3, [r7, #12] 8010da6: 691b ldr r3, [r3, #16] 8010da8: 2b00 cmp r3, #0 8010daa: d105 bne.n 8010db8 8010dac: 68fb ldr r3, [r7, #12] 8010dae: f240 12ff movw r2, #511 @ 0x1ff 8010db2: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8010db6: e02d b.n 8010e14 8010db8: 68fb ldr r3, [r7, #12] 8010dba: 22ff movs r2, #255 @ 0xff 8010dbc: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8010dc0: e028 b.n 8010e14 8010dc2: 68fb ldr r3, [r7, #12] 8010dc4: 689b ldr r3, [r3, #8] 8010dc6: 2b00 cmp r3, #0 8010dc8: d10d bne.n 8010de6 8010dca: 68fb ldr r3, [r7, #12] 8010dcc: 691b ldr r3, [r3, #16] 8010dce: 2b00 cmp r3, #0 8010dd0: d104 bne.n 8010ddc 8010dd2: 68fb ldr r3, [r7, #12] 8010dd4: 22ff movs r2, #255 @ 0xff 8010dd6: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8010dda: e01b b.n 8010e14 8010ddc: 68fb ldr r3, [r7, #12] 8010dde: 227f movs r2, #127 @ 0x7f 8010de0: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8010de4: e016 b.n 8010e14 8010de6: 68fb ldr r3, [r7, #12] 8010de8: 689b ldr r3, [r3, #8] 8010dea: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8010dee: d10d bne.n 8010e0c 8010df0: 68fb ldr r3, [r7, #12] 8010df2: 691b ldr r3, [r3, #16] 8010df4: 2b00 cmp r3, #0 8010df6: d104 bne.n 8010e02 8010df8: 68fb ldr r3, [r7, #12] 8010dfa: 227f movs r2, #127 @ 0x7f 8010dfc: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8010e00: e008 b.n 8010e14 8010e02: 68fb ldr r3, [r7, #12] 8010e04: 223f movs r2, #63 @ 0x3f 8010e06: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8010e0a: e003 b.n 8010e14 8010e0c: 68fb ldr r3, [r7, #12] 8010e0e: 2200 movs r2, #0 8010e10: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 huart->ErrorCode = HAL_UART_ERROR_NONE; 8010e14: 68fb ldr r3, [r7, #12] 8010e16: 2200 movs r2, #0 8010e18: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->RxState = HAL_UART_STATE_BUSY_RX; 8010e1c: 68fb ldr r3, [r7, #12] 8010e1e: 2222 movs r2, #34 @ 0x22 8010e20: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8010e24: 68fb ldr r3, [r7, #12] 8010e26: 681b ldr r3, [r3, #0] 8010e28: 3308 adds r3, #8 8010e2a: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010e2c: 6e7b ldr r3, [r7, #100] @ 0x64 8010e2e: e853 3f00 ldrex r3, [r3] 8010e32: 663b str r3, [r7, #96] @ 0x60 return(result); 8010e34: 6e3b ldr r3, [r7, #96] @ 0x60 8010e36: f043 0301 orr.w r3, r3, #1 8010e3a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8010e3e: 68fb ldr r3, [r7, #12] 8010e40: 681b ldr r3, [r3, #0] 8010e42: 3308 adds r3, #8 8010e44: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 8010e48: 673a str r2, [r7, #112] @ 0x70 8010e4a: 66fb str r3, [r7, #108] @ 0x6c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010e4c: 6ef9 ldr r1, [r7, #108] @ 0x6c 8010e4e: 6f3a ldr r2, [r7, #112] @ 0x70 8010e50: e841 2300 strex r3, r2, [r1] 8010e54: 66bb str r3, [r7, #104] @ 0x68 return(result); 8010e56: 6ebb ldr r3, [r7, #104] @ 0x68 8010e58: 2b00 cmp r3, #0 8010e5a: d1e3 bne.n 8010e24 /* Configure Rx interrupt processing */ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) 8010e5c: 68fb ldr r3, [r7, #12] 8010e5e: 6e5b ldr r3, [r3, #100] @ 0x64 8010e60: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8010e64: d14f bne.n 8010f06 8010e66: 68fb ldr r3, [r7, #12] 8010e68: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8010e6c: 88fa ldrh r2, [r7, #6] 8010e6e: 429a cmp r2, r3 8010e70: d349 bcc.n 8010f06 { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8010e72: 68fb ldr r3, [r7, #12] 8010e74: 689b ldr r3, [r3, #8] 8010e76: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8010e7a: d107 bne.n 8010e8c 8010e7c: 68fb ldr r3, [r7, #12] 8010e7e: 691b ldr r3, [r3, #16] 8010e80: 2b00 cmp r3, #0 8010e82: d103 bne.n 8010e8c { huart->RxISR = UART_RxISR_16BIT_FIFOEN; 8010e84: 68fb ldr r3, [r7, #12] 8010e86: 4a47 ldr r2, [pc, #284] @ (8010fa4 ) 8010e88: 675a str r2, [r3, #116] @ 0x74 8010e8a: e002 b.n 8010e92 } else { huart->RxISR = UART_RxISR_8BIT_FIFOEN; 8010e8c: 68fb ldr r3, [r7, #12] 8010e8e: 4a46 ldr r2, [pc, #280] @ (8010fa8 ) 8010e90: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8010e92: 68fb ldr r3, [r7, #12] 8010e94: 691b ldr r3, [r3, #16] 8010e96: 2b00 cmp r3, #0 8010e98: d01a beq.n 8010ed0 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8010e9a: 68fb ldr r3, [r7, #12] 8010e9c: 681b ldr r3, [r3, #0] 8010e9e: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010ea0: 6d3b ldr r3, [r7, #80] @ 0x50 8010ea2: e853 3f00 ldrex r3, [r3] 8010ea6: 64fb str r3, [r7, #76] @ 0x4c return(result); 8010ea8: 6cfb ldr r3, [r7, #76] @ 0x4c 8010eaa: f443 7380 orr.w r3, r3, #256 @ 0x100 8010eae: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8010eb2: 68fb ldr r3, [r7, #12] 8010eb4: 681b ldr r3, [r3, #0] 8010eb6: 461a mov r2, r3 8010eb8: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8010ebc: 65fb str r3, [r7, #92] @ 0x5c 8010ebe: 65ba str r2, [r7, #88] @ 0x58 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010ec0: 6db9 ldr r1, [r7, #88] @ 0x58 8010ec2: 6dfa ldr r2, [r7, #92] @ 0x5c 8010ec4: e841 2300 strex r3, r2, [r1] 8010ec8: 657b str r3, [r7, #84] @ 0x54 return(result); 8010eca: 6d7b ldr r3, [r7, #84] @ 0x54 8010ecc: 2b00 cmp r3, #0 8010ece: d1e4 bne.n 8010e9a } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8010ed0: 68fb ldr r3, [r7, #12] 8010ed2: 681b ldr r3, [r3, #0] 8010ed4: 3308 adds r3, #8 8010ed6: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010ed8: 6bfb ldr r3, [r7, #60] @ 0x3c 8010eda: e853 3f00 ldrex r3, [r3] 8010ede: 63bb str r3, [r7, #56] @ 0x38 return(result); 8010ee0: 6bbb ldr r3, [r7, #56] @ 0x38 8010ee2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8010ee6: 67fb str r3, [r7, #124] @ 0x7c 8010ee8: 68fb ldr r3, [r7, #12] 8010eea: 681b ldr r3, [r3, #0] 8010eec: 3308 adds r3, #8 8010eee: 6ffa ldr r2, [r7, #124] @ 0x7c 8010ef0: 64ba str r2, [r7, #72] @ 0x48 8010ef2: 647b str r3, [r7, #68] @ 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010ef4: 6c79 ldr r1, [r7, #68] @ 0x44 8010ef6: 6cba ldr r2, [r7, #72] @ 0x48 8010ef8: e841 2300 strex r3, r2, [r1] 8010efc: 643b str r3, [r7, #64] @ 0x40 return(result); 8010efe: 6c3b ldr r3, [r7, #64] @ 0x40 8010f00: 2b00 cmp r3, #0 8010f02: d1e5 bne.n 8010ed0 8010f04: e046 b.n 8010f94 } else { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8010f06: 68fb ldr r3, [r7, #12] 8010f08: 689b ldr r3, [r3, #8] 8010f0a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8010f0e: d107 bne.n 8010f20 8010f10: 68fb ldr r3, [r7, #12] 8010f12: 691b ldr r3, [r3, #16] 8010f14: 2b00 cmp r3, #0 8010f16: d103 bne.n 8010f20 { huart->RxISR = UART_RxISR_16BIT; 8010f18: 68fb ldr r3, [r7, #12] 8010f1a: 4a24 ldr r2, [pc, #144] @ (8010fac ) 8010f1c: 675a str r2, [r3, #116] @ 0x74 8010f1e: e002 b.n 8010f26 } else { huart->RxISR = UART_RxISR_8BIT; 8010f20: 68fb ldr r3, [r7, #12] 8010f22: 4a23 ldr r2, [pc, #140] @ (8010fb0 ) 8010f24: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8010f26: 68fb ldr r3, [r7, #12] 8010f28: 691b ldr r3, [r3, #16] 8010f2a: 2b00 cmp r3, #0 8010f2c: d019 beq.n 8010f62 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); 8010f2e: 68fb ldr r3, [r7, #12] 8010f30: 681b ldr r3, [r3, #0] 8010f32: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010f34: 6abb ldr r3, [r7, #40] @ 0x28 8010f36: e853 3f00 ldrex r3, [r3] 8010f3a: 627b str r3, [r7, #36] @ 0x24 return(result); 8010f3c: 6a7b ldr r3, [r7, #36] @ 0x24 8010f3e: f443 7390 orr.w r3, r3, #288 @ 0x120 8010f42: 677b str r3, [r7, #116] @ 0x74 8010f44: 68fb ldr r3, [r7, #12] 8010f46: 681b ldr r3, [r3, #0] 8010f48: 461a mov r2, r3 8010f4a: 6f7b ldr r3, [r7, #116] @ 0x74 8010f4c: 637b str r3, [r7, #52] @ 0x34 8010f4e: 633a str r2, [r7, #48] @ 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010f50: 6b39 ldr r1, [r7, #48] @ 0x30 8010f52: 6b7a ldr r2, [r7, #52] @ 0x34 8010f54: e841 2300 strex r3, r2, [r1] 8010f58: 62fb str r3, [r7, #44] @ 0x2c return(result); 8010f5a: 6afb ldr r3, [r7, #44] @ 0x2c 8010f5c: 2b00 cmp r3, #0 8010f5e: d1e6 bne.n 8010f2e 8010f60: e018 b.n 8010f94 } else { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8010f62: 68fb ldr r3, [r7, #12] 8010f64: 681b ldr r3, [r3, #0] 8010f66: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010f68: 697b ldr r3, [r7, #20] 8010f6a: e853 3f00 ldrex r3, [r3] 8010f6e: 613b str r3, [r7, #16] return(result); 8010f70: 693b ldr r3, [r7, #16] 8010f72: f043 0320 orr.w r3, r3, #32 8010f76: 67bb str r3, [r7, #120] @ 0x78 8010f78: 68fb ldr r3, [r7, #12] 8010f7a: 681b ldr r3, [r3, #0] 8010f7c: 461a mov r2, r3 8010f7e: 6fbb ldr r3, [r7, #120] @ 0x78 8010f80: 623b str r3, [r7, #32] 8010f82: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010f84: 69f9 ldr r1, [r7, #28] 8010f86: 6a3a ldr r2, [r7, #32] 8010f88: e841 2300 strex r3, r2, [r1] 8010f8c: 61bb str r3, [r7, #24] return(result); 8010f8e: 69bb ldr r3, [r7, #24] 8010f90: 2b00 cmp r3, #0 8010f92: d1e6 bne.n 8010f62 } } return HAL_OK; 8010f94: 2300 movs r3, #0 } 8010f96: 4618 mov r0, r3 8010f98: 378c adds r7, #140 @ 0x8c 8010f9a: 46bd mov sp, r7 8010f9c: f85d 7b04 ldr.w r7, [sp], #4 8010fa0: 4770 bx lr 8010fa2: bf00 nop 8010fa4: 08011b19 .word 0x08011b19 8010fa8: 080117b9 .word 0x080117b9 8010fac: 08011601 .word 0x08011601 8010fb0: 08011449 .word 0x08011449 08010fb4 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8010fb4: b480 push {r7} 8010fb6: b095 sub sp, #84 @ 0x54 8010fb8: af00 add r7, sp, #0 8010fba: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8010fbc: 687b ldr r3, [r7, #4] 8010fbe: 681b ldr r3, [r3, #0] 8010fc0: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010fc2: 6b7b ldr r3, [r7, #52] @ 0x34 8010fc4: e853 3f00 ldrex r3, [r3] 8010fc8: 633b str r3, [r7, #48] @ 0x30 return(result); 8010fca: 6b3b ldr r3, [r7, #48] @ 0x30 8010fcc: f423 7390 bic.w r3, r3, #288 @ 0x120 8010fd0: 64fb str r3, [r7, #76] @ 0x4c 8010fd2: 687b ldr r3, [r7, #4] 8010fd4: 681b ldr r3, [r3, #0] 8010fd6: 461a mov r2, r3 8010fd8: 6cfb ldr r3, [r7, #76] @ 0x4c 8010fda: 643b str r3, [r7, #64] @ 0x40 8010fdc: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010fde: 6bf9 ldr r1, [r7, #60] @ 0x3c 8010fe0: 6c3a ldr r2, [r7, #64] @ 0x40 8010fe2: e841 2300 strex r3, r2, [r1] 8010fe6: 63bb str r3, [r7, #56] @ 0x38 return(result); 8010fe8: 6bbb ldr r3, [r7, #56] @ 0x38 8010fea: 2b00 cmp r3, #0 8010fec: d1e6 bne.n 8010fbc ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8010fee: 687b ldr r3, [r7, #4] 8010ff0: 681b ldr r3, [r3, #0] 8010ff2: 3308 adds r3, #8 8010ff4: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010ff6: 6a3b ldr r3, [r7, #32] 8010ff8: e853 3f00 ldrex r3, [r3] 8010ffc: 61fb str r3, [r7, #28] return(result); 8010ffe: 69fa ldr r2, [r7, #28] 8011000: 4b1e ldr r3, [pc, #120] @ (801107c ) 8011002: 4013 ands r3, r2 8011004: 64bb str r3, [r7, #72] @ 0x48 8011006: 687b ldr r3, [r7, #4] 8011008: 681b ldr r3, [r3, #0] 801100a: 3308 adds r3, #8 801100c: 6cba ldr r2, [r7, #72] @ 0x48 801100e: 62fa str r2, [r7, #44] @ 0x2c 8011010: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011012: 6ab9 ldr r1, [r7, #40] @ 0x28 8011014: 6afa ldr r2, [r7, #44] @ 0x2c 8011016: e841 2300 strex r3, r2, [r1] 801101a: 627b str r3, [r7, #36] @ 0x24 return(result); 801101c: 6a7b ldr r3, [r7, #36] @ 0x24 801101e: 2b00 cmp r3, #0 8011020: d1e5 bne.n 8010fee /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8011022: 687b ldr r3, [r7, #4] 8011024: 6edb ldr r3, [r3, #108] @ 0x6c 8011026: 2b01 cmp r3, #1 8011028: d118 bne.n 801105c { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801102a: 687b ldr r3, [r7, #4] 801102c: 681b ldr r3, [r3, #0] 801102e: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011030: 68fb ldr r3, [r7, #12] 8011032: e853 3f00 ldrex r3, [r3] 8011036: 60bb str r3, [r7, #8] return(result); 8011038: 68bb ldr r3, [r7, #8] 801103a: f023 0310 bic.w r3, r3, #16 801103e: 647b str r3, [r7, #68] @ 0x44 8011040: 687b ldr r3, [r7, #4] 8011042: 681b ldr r3, [r3, #0] 8011044: 461a mov r2, r3 8011046: 6c7b ldr r3, [r7, #68] @ 0x44 8011048: 61bb str r3, [r7, #24] 801104a: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801104c: 6979 ldr r1, [r7, #20] 801104e: 69ba ldr r2, [r7, #24] 8011050: e841 2300 strex r3, r2, [r1] 8011054: 613b str r3, [r7, #16] return(result); 8011056: 693b ldr r3, [r7, #16] 8011058: 2b00 cmp r3, #0 801105a: d1e6 bne.n 801102a } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 801105c: 687b ldr r3, [r7, #4] 801105e: 2220 movs r2, #32 8011060: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8011064: 687b ldr r3, [r7, #4] 8011066: 2200 movs r2, #0 8011068: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 801106a: 687b ldr r3, [r7, #4] 801106c: 2200 movs r2, #0 801106e: 675a str r2, [r3, #116] @ 0x74 } 8011070: bf00 nop 8011072: 3754 adds r7, #84 @ 0x54 8011074: 46bd mov sp, r7 8011076: f85d 7b04 ldr.w r7, [sp], #4 801107a: 4770 bx lr 801107c: effffffe .word 0xeffffffe 08011080 : * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8011080: b580 push {r7, lr} 8011082: b084 sub sp, #16 8011084: af00 add r7, sp, #0 8011086: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8011088: 687b ldr r3, [r7, #4] 801108a: 6b9b ldr r3, [r3, #56] @ 0x38 801108c: 60fb str r3, [r7, #12] huart->RxXferCount = 0U; 801108e: 68fb ldr r3, [r7, #12] 8011090: 2200 movs r2, #0 8011092: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->TxXferCount = 0U; 8011096: 68fb ldr r3, [r7, #12] 8011098: 2200 movs r2, #0 801109a: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 801109e: 68f8 ldr r0, [r7, #12] 80110a0: f7fe ff3a bl 800ff18 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80110a4: bf00 nop 80110a6: 3710 adds r7, #16 80110a8: 46bd mov sp, r7 80110aa: bd80 pop {r7, pc} 080110ac : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) { 80110ac: b480 push {r7} 80110ae: b08f sub sp, #60 @ 0x3c 80110b0: af00 add r7, sp, #0 80110b2: 6078 str r0, [r7, #4] /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 80110b4: 687b ldr r3, [r7, #4] 80110b6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80110ba: 2b21 cmp r3, #33 @ 0x21 80110bc: d14c bne.n 8011158 { if (huart->TxXferCount == 0U) 80110be: 687b ldr r3, [r7, #4] 80110c0: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80110c4: b29b uxth r3, r3 80110c6: 2b00 cmp r3, #0 80110c8: d132 bne.n 8011130 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 80110ca: 687b ldr r3, [r7, #4] 80110cc: 681b ldr r3, [r3, #0] 80110ce: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80110d0: 6a3b ldr r3, [r7, #32] 80110d2: e853 3f00 ldrex r3, [r3] 80110d6: 61fb str r3, [r7, #28] return(result); 80110d8: 69fb ldr r3, [r7, #28] 80110da: f023 0380 bic.w r3, r3, #128 @ 0x80 80110de: 637b str r3, [r7, #52] @ 0x34 80110e0: 687b ldr r3, [r7, #4] 80110e2: 681b ldr r3, [r3, #0] 80110e4: 461a mov r2, r3 80110e6: 6b7b ldr r3, [r7, #52] @ 0x34 80110e8: 62fb str r3, [r7, #44] @ 0x2c 80110ea: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80110ec: 6ab9 ldr r1, [r7, #40] @ 0x28 80110ee: 6afa ldr r2, [r7, #44] @ 0x2c 80110f0: e841 2300 strex r3, r2, [r1] 80110f4: 627b str r3, [r7, #36] @ 0x24 return(result); 80110f6: 6a7b ldr r3, [r7, #36] @ 0x24 80110f8: 2b00 cmp r3, #0 80110fa: d1e6 bne.n 80110ca /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80110fc: 687b ldr r3, [r7, #4] 80110fe: 681b ldr r3, [r3, #0] 8011100: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011102: 68fb ldr r3, [r7, #12] 8011104: e853 3f00 ldrex r3, [r3] 8011108: 60bb str r3, [r7, #8] return(result); 801110a: 68bb ldr r3, [r7, #8] 801110c: f043 0340 orr.w r3, r3, #64 @ 0x40 8011110: 633b str r3, [r7, #48] @ 0x30 8011112: 687b ldr r3, [r7, #4] 8011114: 681b ldr r3, [r3, #0] 8011116: 461a mov r2, r3 8011118: 6b3b ldr r3, [r7, #48] @ 0x30 801111a: 61bb str r3, [r7, #24] 801111c: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801111e: 6979 ldr r1, [r7, #20] 8011120: 69ba ldr r2, [r7, #24] 8011122: e841 2300 strex r3, r2, [r1] 8011126: 613b str r3, [r7, #16] return(result); 8011128: 693b ldr r3, [r7, #16] 801112a: 2b00 cmp r3, #0 801112c: d1e6 bne.n 80110fc huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); huart->pTxBuffPtr++; huart->TxXferCount--; } } } 801112e: e013 b.n 8011158 huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 8011130: 687b ldr r3, [r7, #4] 8011132: 6d1b ldr r3, [r3, #80] @ 0x50 8011134: 781a ldrb r2, [r3, #0] 8011136: 687b ldr r3, [r7, #4] 8011138: 681b ldr r3, [r3, #0] 801113a: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 801113c: 687b ldr r3, [r7, #4] 801113e: 6d1b ldr r3, [r3, #80] @ 0x50 8011140: 1c5a adds r2, r3, #1 8011142: 687b ldr r3, [r7, #4] 8011144: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 8011146: 687b ldr r3, [r7, #4] 8011148: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 801114c: b29b uxth r3, r3 801114e: 3b01 subs r3, #1 8011150: b29a uxth r2, r3 8011152: 687b ldr r3, [r7, #4] 8011154: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 8011158: bf00 nop 801115a: 373c adds r7, #60 @ 0x3c 801115c: 46bd mov sp, r7 801115e: f85d 7b04 ldr.w r7, [sp], #4 8011162: 4770 bx lr 08011164 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { 8011164: b480 push {r7} 8011166: b091 sub sp, #68 @ 0x44 8011168: af00 add r7, sp, #0 801116a: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 801116c: 687b ldr r3, [r7, #4] 801116e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8011172: 2b21 cmp r3, #33 @ 0x21 8011174: d151 bne.n 801121a { if (huart->TxXferCount == 0U) 8011176: 687b ldr r3, [r7, #4] 8011178: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 801117c: b29b uxth r3, r3 801117e: 2b00 cmp r3, #0 8011180: d132 bne.n 80111e8 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8011182: 687b ldr r3, [r7, #4] 8011184: 681b ldr r3, [r3, #0] 8011186: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011188: 6a7b ldr r3, [r7, #36] @ 0x24 801118a: e853 3f00 ldrex r3, [r3] 801118e: 623b str r3, [r7, #32] return(result); 8011190: 6a3b ldr r3, [r7, #32] 8011192: f023 0380 bic.w r3, r3, #128 @ 0x80 8011196: 63bb str r3, [r7, #56] @ 0x38 8011198: 687b ldr r3, [r7, #4] 801119a: 681b ldr r3, [r3, #0] 801119c: 461a mov r2, r3 801119e: 6bbb ldr r3, [r7, #56] @ 0x38 80111a0: 633b str r3, [r7, #48] @ 0x30 80111a2: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80111a4: 6af9 ldr r1, [r7, #44] @ 0x2c 80111a6: 6b3a ldr r2, [r7, #48] @ 0x30 80111a8: e841 2300 strex r3, r2, [r1] 80111ac: 62bb str r3, [r7, #40] @ 0x28 return(result); 80111ae: 6abb ldr r3, [r7, #40] @ 0x28 80111b0: 2b00 cmp r3, #0 80111b2: d1e6 bne.n 8011182 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80111b4: 687b ldr r3, [r7, #4] 80111b6: 681b ldr r3, [r3, #0] 80111b8: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80111ba: 693b ldr r3, [r7, #16] 80111bc: e853 3f00 ldrex r3, [r3] 80111c0: 60fb str r3, [r7, #12] return(result); 80111c2: 68fb ldr r3, [r7, #12] 80111c4: f043 0340 orr.w r3, r3, #64 @ 0x40 80111c8: 637b str r3, [r7, #52] @ 0x34 80111ca: 687b ldr r3, [r7, #4] 80111cc: 681b ldr r3, [r3, #0] 80111ce: 461a mov r2, r3 80111d0: 6b7b ldr r3, [r7, #52] @ 0x34 80111d2: 61fb str r3, [r7, #28] 80111d4: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80111d6: 69b9 ldr r1, [r7, #24] 80111d8: 69fa ldr r2, [r7, #28] 80111da: e841 2300 strex r3, r2, [r1] 80111de: 617b str r3, [r7, #20] return(result); 80111e0: 697b ldr r3, [r7, #20] 80111e2: 2b00 cmp r3, #0 80111e4: d1e6 bne.n 80111b4 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; } } } 80111e6: e018 b.n 801121a tmp = (const uint16_t *) huart->pTxBuffPtr; 80111e8: 687b ldr r3, [r7, #4] 80111ea: 6d1b ldr r3, [r3, #80] @ 0x50 80111ec: 63fb str r3, [r7, #60] @ 0x3c huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 80111ee: 6bfb ldr r3, [r7, #60] @ 0x3c 80111f0: 881b ldrh r3, [r3, #0] 80111f2: 461a mov r2, r3 80111f4: 687b ldr r3, [r7, #4] 80111f6: 681b ldr r3, [r3, #0] 80111f8: f3c2 0208 ubfx r2, r2, #0, #9 80111fc: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 80111fe: 687b ldr r3, [r7, #4] 8011200: 6d1b ldr r3, [r3, #80] @ 0x50 8011202: 1c9a adds r2, r3, #2 8011204: 687b ldr r3, [r7, #4] 8011206: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 8011208: 687b ldr r3, [r7, #4] 801120a: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 801120e: b29b uxth r3, r3 8011210: 3b01 subs r3, #1 8011212: b29a uxth r2, r3 8011214: 687b ldr r3, [r7, #4] 8011216: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 801121a: bf00 nop 801121c: 3744 adds r7, #68 @ 0x44 801121e: 46bd mov sp, r7 8011220: f85d 7b04 ldr.w r7, [sp], #4 8011224: 4770 bx lr 08011226 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 8011226: b480 push {r7} 8011228: b091 sub sp, #68 @ 0x44 801122a: af00 add r7, sp, #0 801122c: 6078 str r0, [r7, #4] uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 801122e: 687b ldr r3, [r7, #4] 8011230: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8011234: 2b21 cmp r3, #33 @ 0x21 8011236: d160 bne.n 80112fa { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 8011238: 687b ldr r3, [r7, #4] 801123a: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 801123e: 87fb strh r3, [r7, #62] @ 0x3e 8011240: e057 b.n 80112f2 { if (huart->TxXferCount == 0U) 8011242: 687b ldr r3, [r7, #4] 8011244: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8011248: b29b uxth r3, r3 801124a: 2b00 cmp r3, #0 801124c: d133 bne.n 80112b6 { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 801124e: 687b ldr r3, [r7, #4] 8011250: 681b ldr r3, [r3, #0] 8011252: 3308 adds r3, #8 8011254: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011256: 6a7b ldr r3, [r7, #36] @ 0x24 8011258: e853 3f00 ldrex r3, [r3] 801125c: 623b str r3, [r7, #32] return(result); 801125e: 6a3b ldr r3, [r7, #32] 8011260: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 8011264: 63bb str r3, [r7, #56] @ 0x38 8011266: 687b ldr r3, [r7, #4] 8011268: 681b ldr r3, [r3, #0] 801126a: 3308 adds r3, #8 801126c: 6bba ldr r2, [r7, #56] @ 0x38 801126e: 633a str r2, [r7, #48] @ 0x30 8011270: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011272: 6af9 ldr r1, [r7, #44] @ 0x2c 8011274: 6b3a ldr r2, [r7, #48] @ 0x30 8011276: e841 2300 strex r3, r2, [r1] 801127a: 62bb str r3, [r7, #40] @ 0x28 return(result); 801127c: 6abb ldr r3, [r7, #40] @ 0x28 801127e: 2b00 cmp r3, #0 8011280: d1e5 bne.n 801124e /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8011282: 687b ldr r3, [r7, #4] 8011284: 681b ldr r3, [r3, #0] 8011286: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011288: 693b ldr r3, [r7, #16] 801128a: e853 3f00 ldrex r3, [r3] 801128e: 60fb str r3, [r7, #12] return(result); 8011290: 68fb ldr r3, [r7, #12] 8011292: f043 0340 orr.w r3, r3, #64 @ 0x40 8011296: 637b str r3, [r7, #52] @ 0x34 8011298: 687b ldr r3, [r7, #4] 801129a: 681b ldr r3, [r3, #0] 801129c: 461a mov r2, r3 801129e: 6b7b ldr r3, [r7, #52] @ 0x34 80112a0: 61fb str r3, [r7, #28] 80112a2: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80112a4: 69b9 ldr r1, [r7, #24] 80112a6: 69fa ldr r2, [r7, #28] 80112a8: e841 2300 strex r3, r2, [r1] 80112ac: 617b str r3, [r7, #20] return(result); 80112ae: 697b ldr r3, [r7, #20] 80112b0: 2b00 cmp r3, #0 80112b2: d1e6 bne.n 8011282 break; /* force exit loop */ 80112b4: e021 b.n 80112fa } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 80112b6: 687b ldr r3, [r7, #4] 80112b8: 681b ldr r3, [r3, #0] 80112ba: 69db ldr r3, [r3, #28] 80112bc: f003 0380 and.w r3, r3, #128 @ 0x80 80112c0: 2b00 cmp r3, #0 80112c2: d013 beq.n 80112ec { huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 80112c4: 687b ldr r3, [r7, #4] 80112c6: 6d1b ldr r3, [r3, #80] @ 0x50 80112c8: 781a ldrb r2, [r3, #0] 80112ca: 687b ldr r3, [r7, #4] 80112cc: 681b ldr r3, [r3, #0] 80112ce: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 80112d0: 687b ldr r3, [r7, #4] 80112d2: 6d1b ldr r3, [r3, #80] @ 0x50 80112d4: 1c5a adds r2, r3, #1 80112d6: 687b ldr r3, [r7, #4] 80112d8: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 80112da: 687b ldr r3, [r7, #4] 80112dc: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80112e0: b29b uxth r3, r3 80112e2: 3b01 subs r3, #1 80112e4: b29a uxth r2, r3 80112e6: 687b ldr r3, [r7, #4] 80112e8: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80112ec: 8ffb ldrh r3, [r7, #62] @ 0x3e 80112ee: 3b01 subs r3, #1 80112f0: 87fb strh r3, [r7, #62] @ 0x3e 80112f2: 8ffb ldrh r3, [r7, #62] @ 0x3e 80112f4: 2b00 cmp r3, #0 80112f6: d1a4 bne.n 8011242 { /* Nothing to do */ } } } } 80112f8: e7ff b.n 80112fa 80112fa: bf00 nop 80112fc: 3744 adds r7, #68 @ 0x44 80112fe: 46bd mov sp, r7 8011300: f85d 7b04 ldr.w r7, [sp], #4 8011304: 4770 bx lr 08011306 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 8011306: b480 push {r7} 8011308: b091 sub sp, #68 @ 0x44 801130a: af00 add r7, sp, #0 801130c: 6078 str r0, [r7, #4] const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 801130e: 687b ldr r3, [r7, #4] 8011310: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8011314: 2b21 cmp r3, #33 @ 0x21 8011316: d165 bne.n 80113e4 { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 8011318: 687b ldr r3, [r7, #4] 801131a: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 801131e: 87fb strh r3, [r7, #62] @ 0x3e 8011320: e05c b.n 80113dc { if (huart->TxXferCount == 0U) 8011322: 687b ldr r3, [r7, #4] 8011324: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8011328: b29b uxth r3, r3 801132a: 2b00 cmp r3, #0 801132c: d133 bne.n 8011396 { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 801132e: 687b ldr r3, [r7, #4] 8011330: 681b ldr r3, [r3, #0] 8011332: 3308 adds r3, #8 8011334: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011336: 6a3b ldr r3, [r7, #32] 8011338: e853 3f00 ldrex r3, [r3] 801133c: 61fb str r3, [r7, #28] return(result); 801133e: 69fb ldr r3, [r7, #28] 8011340: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 8011344: 637b str r3, [r7, #52] @ 0x34 8011346: 687b ldr r3, [r7, #4] 8011348: 681b ldr r3, [r3, #0] 801134a: 3308 adds r3, #8 801134c: 6b7a ldr r2, [r7, #52] @ 0x34 801134e: 62fa str r2, [r7, #44] @ 0x2c 8011350: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011352: 6ab9 ldr r1, [r7, #40] @ 0x28 8011354: 6afa ldr r2, [r7, #44] @ 0x2c 8011356: e841 2300 strex r3, r2, [r1] 801135a: 627b str r3, [r7, #36] @ 0x24 return(result); 801135c: 6a7b ldr r3, [r7, #36] @ 0x24 801135e: 2b00 cmp r3, #0 8011360: d1e5 bne.n 801132e /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8011362: 687b ldr r3, [r7, #4] 8011364: 681b ldr r3, [r3, #0] 8011366: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011368: 68fb ldr r3, [r7, #12] 801136a: e853 3f00 ldrex r3, [r3] 801136e: 60bb str r3, [r7, #8] return(result); 8011370: 68bb ldr r3, [r7, #8] 8011372: f043 0340 orr.w r3, r3, #64 @ 0x40 8011376: 633b str r3, [r7, #48] @ 0x30 8011378: 687b ldr r3, [r7, #4] 801137a: 681b ldr r3, [r3, #0] 801137c: 461a mov r2, r3 801137e: 6b3b ldr r3, [r7, #48] @ 0x30 8011380: 61bb str r3, [r7, #24] 8011382: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011384: 6979 ldr r1, [r7, #20] 8011386: 69ba ldr r2, [r7, #24] 8011388: e841 2300 strex r3, r2, [r1] 801138c: 613b str r3, [r7, #16] return(result); 801138e: 693b ldr r3, [r7, #16] 8011390: 2b00 cmp r3, #0 8011392: d1e6 bne.n 8011362 break; /* force exit loop */ 8011394: e026 b.n 80113e4 } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 8011396: 687b ldr r3, [r7, #4] 8011398: 681b ldr r3, [r3, #0] 801139a: 69db ldr r3, [r3, #28] 801139c: f003 0380 and.w r3, r3, #128 @ 0x80 80113a0: 2b00 cmp r3, #0 80113a2: d018 beq.n 80113d6 { tmp = (const uint16_t *) huart->pTxBuffPtr; 80113a4: 687b ldr r3, [r7, #4] 80113a6: 6d1b ldr r3, [r3, #80] @ 0x50 80113a8: 63bb str r3, [r7, #56] @ 0x38 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 80113aa: 6bbb ldr r3, [r7, #56] @ 0x38 80113ac: 881b ldrh r3, [r3, #0] 80113ae: 461a mov r2, r3 80113b0: 687b ldr r3, [r7, #4] 80113b2: 681b ldr r3, [r3, #0] 80113b4: f3c2 0208 ubfx r2, r2, #0, #9 80113b8: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 80113ba: 687b ldr r3, [r7, #4] 80113bc: 6d1b ldr r3, [r3, #80] @ 0x50 80113be: 1c9a adds r2, r3, #2 80113c0: 687b ldr r3, [r7, #4] 80113c2: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 80113c4: 687b ldr r3, [r7, #4] 80113c6: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80113ca: b29b uxth r3, r3 80113cc: 3b01 subs r3, #1 80113ce: b29a uxth r2, r3 80113d0: 687b ldr r3, [r7, #4] 80113d2: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80113d6: 8ffb ldrh r3, [r7, #62] @ 0x3e 80113d8: 3b01 subs r3, #1 80113da: 87fb strh r3, [r7, #62] @ 0x3e 80113dc: 8ffb ldrh r3, [r7, #62] @ 0x3e 80113de: 2b00 cmp r3, #0 80113e0: d19f bne.n 8011322 { /* Nothing to do */ } } } } 80113e2: e7ff b.n 80113e4 80113e4: bf00 nop 80113e6: 3744 adds r7, #68 @ 0x44 80113e8: 46bd mov sp, r7 80113ea: f85d 7b04 ldr.w r7, [sp], #4 80113ee: 4770 bx lr 080113f0 : * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 80113f0: b580 push {r7, lr} 80113f2: b088 sub sp, #32 80113f4: af00 add r7, sp, #0 80113f6: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80113f8: 687b ldr r3, [r7, #4] 80113fa: 681b ldr r3, [r3, #0] 80113fc: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80113fe: 68fb ldr r3, [r7, #12] 8011400: e853 3f00 ldrex r3, [r3] 8011404: 60bb str r3, [r7, #8] return(result); 8011406: 68bb ldr r3, [r7, #8] 8011408: f023 0340 bic.w r3, r3, #64 @ 0x40 801140c: 61fb str r3, [r7, #28] 801140e: 687b ldr r3, [r7, #4] 8011410: 681b ldr r3, [r3, #0] 8011412: 461a mov r2, r3 8011414: 69fb ldr r3, [r7, #28] 8011416: 61bb str r3, [r7, #24] 8011418: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801141a: 6979 ldr r1, [r7, #20] 801141c: 69ba ldr r2, [r7, #24] 801141e: e841 2300 strex r3, r2, [r1] 8011422: 613b str r3, [r7, #16] return(result); 8011424: 693b ldr r3, [r7, #16] 8011426: 2b00 cmp r3, #0 8011428: d1e6 bne.n 80113f8 /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 801142a: 687b ldr r3, [r7, #4] 801142c: 2220 movs r2, #32 801142e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Cleat TxISR function pointer */ huart->TxISR = NULL; 8011432: 687b ldr r3, [r7, #4] 8011434: 2200 movs r2, #0 8011436: 679a str r2, [r3, #120] @ 0x78 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8011438: 6878 ldr r0, [r7, #4] 801143a: f7f2 fc07 bl 8003c4c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 801143e: bf00 nop 8011440: 3720 adds r7, #32 8011442: 46bd mov sp, r7 8011444: bd80 pop {r7, pc} ... 08011448 : * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) { 8011448: b580 push {r7, lr} 801144a: b09c sub sp, #112 @ 0x70 801144c: af00 add r7, sp, #0 801144e: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 8011450: 687b ldr r3, [r7, #4] 8011452: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8011456: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 801145a: 687b ldr r3, [r7, #4] 801145c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8011460: 2b22 cmp r3, #34 @ 0x22 8011462: f040 80be bne.w 80115e2 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8011466: 687b ldr r3, [r7, #4] 8011468: 681b ldr r3, [r3, #0] 801146a: 6a5b ldr r3, [r3, #36] @ 0x24 801146c: f8a7 306c strh.w r3, [r7, #108] @ 0x6c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 8011470: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 8011474: b2d9 uxtb r1, r3 8011476: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 801147a: b2da uxtb r2, r3 801147c: 687b ldr r3, [r7, #4] 801147e: 6d9b ldr r3, [r3, #88] @ 0x58 8011480: 400a ands r2, r1 8011482: b2d2 uxtb r2, r2 8011484: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8011486: 687b ldr r3, [r7, #4] 8011488: 6d9b ldr r3, [r3, #88] @ 0x58 801148a: 1c5a adds r2, r3, #1 801148c: 687b ldr r3, [r7, #4] 801148e: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8011490: 687b ldr r3, [r7, #4] 8011492: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011496: b29b uxth r3, r3 8011498: 3b01 subs r3, #1 801149a: b29a uxth r2, r3 801149c: 687b ldr r3, [r7, #4] 801149e: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 80114a2: 687b ldr r3, [r7, #4] 80114a4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80114a8: b29b uxth r3, r3 80114aa: 2b00 cmp r3, #0 80114ac: f040 80a1 bne.w 80115f2 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 80114b0: 687b ldr r3, [r7, #4] 80114b2: 681b ldr r3, [r3, #0] 80114b4: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80114b6: 6cfb ldr r3, [r7, #76] @ 0x4c 80114b8: e853 3f00 ldrex r3, [r3] 80114bc: 64bb str r3, [r7, #72] @ 0x48 return(result); 80114be: 6cbb ldr r3, [r7, #72] @ 0x48 80114c0: f423 7390 bic.w r3, r3, #288 @ 0x120 80114c4: 66bb str r3, [r7, #104] @ 0x68 80114c6: 687b ldr r3, [r7, #4] 80114c8: 681b ldr r3, [r3, #0] 80114ca: 461a mov r2, r3 80114cc: 6ebb ldr r3, [r7, #104] @ 0x68 80114ce: 65bb str r3, [r7, #88] @ 0x58 80114d0: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80114d2: 6d79 ldr r1, [r7, #84] @ 0x54 80114d4: 6dba ldr r2, [r7, #88] @ 0x58 80114d6: e841 2300 strex r3, r2, [r1] 80114da: 653b str r3, [r7, #80] @ 0x50 return(result); 80114dc: 6d3b ldr r3, [r7, #80] @ 0x50 80114de: 2b00 cmp r3, #0 80114e0: d1e6 bne.n 80114b0 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80114e2: 687b ldr r3, [r7, #4] 80114e4: 681b ldr r3, [r3, #0] 80114e6: 3308 adds r3, #8 80114e8: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80114ea: 6bbb ldr r3, [r7, #56] @ 0x38 80114ec: e853 3f00 ldrex r3, [r3] 80114f0: 637b str r3, [r7, #52] @ 0x34 return(result); 80114f2: 6b7b ldr r3, [r7, #52] @ 0x34 80114f4: f023 0301 bic.w r3, r3, #1 80114f8: 667b str r3, [r7, #100] @ 0x64 80114fa: 687b ldr r3, [r7, #4] 80114fc: 681b ldr r3, [r3, #0] 80114fe: 3308 adds r3, #8 8011500: 6e7a ldr r2, [r7, #100] @ 0x64 8011502: 647a str r2, [r7, #68] @ 0x44 8011504: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011506: 6c39 ldr r1, [r7, #64] @ 0x40 8011508: 6c7a ldr r2, [r7, #68] @ 0x44 801150a: e841 2300 strex r3, r2, [r1] 801150e: 63fb str r3, [r7, #60] @ 0x3c return(result); 8011510: 6bfb ldr r3, [r7, #60] @ 0x3c 8011512: 2b00 cmp r3, #0 8011514: d1e5 bne.n 80114e2 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8011516: 687b ldr r3, [r7, #4] 8011518: 2220 movs r2, #32 801151a: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 801151e: 687b ldr r3, [r7, #4] 8011520: 2200 movs r2, #0 8011522: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8011524: 687b ldr r3, [r7, #4] 8011526: 2200 movs r2, #0 8011528: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 801152a: 687b ldr r3, [r7, #4] 801152c: 681b ldr r3, [r3, #0] 801152e: 4a33 ldr r2, [pc, #204] @ (80115fc ) 8011530: 4293 cmp r3, r2 8011532: d01f beq.n 8011574 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8011534: 687b ldr r3, [r7, #4] 8011536: 681b ldr r3, [r3, #0] 8011538: 685b ldr r3, [r3, #4] 801153a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 801153e: 2b00 cmp r3, #0 8011540: d018 beq.n 8011574 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8011542: 687b ldr r3, [r7, #4] 8011544: 681b ldr r3, [r3, #0] 8011546: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011548: 6a7b ldr r3, [r7, #36] @ 0x24 801154a: e853 3f00 ldrex r3, [r3] 801154e: 623b str r3, [r7, #32] return(result); 8011550: 6a3b ldr r3, [r7, #32] 8011552: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8011556: 663b str r3, [r7, #96] @ 0x60 8011558: 687b ldr r3, [r7, #4] 801155a: 681b ldr r3, [r3, #0] 801155c: 461a mov r2, r3 801155e: 6e3b ldr r3, [r7, #96] @ 0x60 8011560: 633b str r3, [r7, #48] @ 0x30 8011562: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011564: 6af9 ldr r1, [r7, #44] @ 0x2c 8011566: 6b3a ldr r2, [r7, #48] @ 0x30 8011568: e841 2300 strex r3, r2, [r1] 801156c: 62bb str r3, [r7, #40] @ 0x28 return(result); 801156e: 6abb ldr r3, [r7, #40] @ 0x28 8011570: 2b00 cmp r3, #0 8011572: d1e6 bne.n 8011542 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8011574: 687b ldr r3, [r7, #4] 8011576: 6edb ldr r3, [r3, #108] @ 0x6c 8011578: 2b01 cmp r3, #1 801157a: d12e bne.n 80115da { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801157c: 687b ldr r3, [r7, #4] 801157e: 2200 movs r2, #0 8011580: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8011582: 687b ldr r3, [r7, #4] 8011584: 681b ldr r3, [r3, #0] 8011586: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011588: 693b ldr r3, [r7, #16] 801158a: e853 3f00 ldrex r3, [r3] 801158e: 60fb str r3, [r7, #12] return(result); 8011590: 68fb ldr r3, [r7, #12] 8011592: f023 0310 bic.w r3, r3, #16 8011596: 65fb str r3, [r7, #92] @ 0x5c 8011598: 687b ldr r3, [r7, #4] 801159a: 681b ldr r3, [r3, #0] 801159c: 461a mov r2, r3 801159e: 6dfb ldr r3, [r7, #92] @ 0x5c 80115a0: 61fb str r3, [r7, #28] 80115a2: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80115a4: 69b9 ldr r1, [r7, #24] 80115a6: 69fa ldr r2, [r7, #28] 80115a8: e841 2300 strex r3, r2, [r1] 80115ac: 617b str r3, [r7, #20] return(result); 80115ae: 697b ldr r3, [r7, #20] 80115b0: 2b00 cmp r3, #0 80115b2: d1e6 bne.n 8011582 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 80115b4: 687b ldr r3, [r7, #4] 80115b6: 681b ldr r3, [r3, #0] 80115b8: 69db ldr r3, [r3, #28] 80115ba: f003 0310 and.w r3, r3, #16 80115be: 2b10 cmp r3, #16 80115c0: d103 bne.n 80115ca { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 80115c2: 687b ldr r3, [r7, #4] 80115c4: 681b ldr r3, [r3, #0] 80115c6: 2210 movs r2, #16 80115c8: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 80115ca: 687b ldr r3, [r7, #4] 80115cc: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 80115d0: 4619 mov r1, r3 80115d2: 6878 ldr r0, [r7, #4] 80115d4: f7f2 fb10 bl 8003bf8 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 80115d8: e00b b.n 80115f2 HAL_UART_RxCpltCallback(huart); 80115da: 6878 ldr r0, [r7, #4] 80115dc: f7f2 fb02 bl 8003be4 } 80115e0: e007 b.n 80115f2 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 80115e2: 687b ldr r3, [r7, #4] 80115e4: 681b ldr r3, [r3, #0] 80115e6: 699a ldr r2, [r3, #24] 80115e8: 687b ldr r3, [r7, #4] 80115ea: 681b ldr r3, [r3, #0] 80115ec: f042 0208 orr.w r2, r2, #8 80115f0: 619a str r2, [r3, #24] } 80115f2: bf00 nop 80115f4: 3770 adds r7, #112 @ 0x70 80115f6: 46bd mov sp, r7 80115f8: bd80 pop {r7, pc} 80115fa: bf00 nop 80115fc: 58000c00 .word 0x58000c00 08011600 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { 8011600: b580 push {r7, lr} 8011602: b09c sub sp, #112 @ 0x70 8011604: af00 add r7, sp, #0 8011606: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 8011608: 687b ldr r3, [r7, #4] 801160a: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 801160e: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8011612: 687b ldr r3, [r7, #4] 8011614: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8011618: 2b22 cmp r3, #34 @ 0x22 801161a: f040 80be bne.w 801179a { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 801161e: 687b ldr r3, [r7, #4] 8011620: 681b ldr r3, [r3, #0] 8011622: 6a5b ldr r3, [r3, #36] @ 0x24 8011624: f8a7 306c strh.w r3, [r7, #108] @ 0x6c tmp = (uint16_t *) huart->pRxBuffPtr ; 8011628: 687b ldr r3, [r7, #4] 801162a: 6d9b ldr r3, [r3, #88] @ 0x58 801162c: 66bb str r3, [r7, #104] @ 0x68 *tmp = (uint16_t)(uhdata & uhMask); 801162e: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c 8011632: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 8011636: 4013 ands r3, r2 8011638: b29a uxth r2, r3 801163a: 6ebb ldr r3, [r7, #104] @ 0x68 801163c: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 801163e: 687b ldr r3, [r7, #4] 8011640: 6d9b ldr r3, [r3, #88] @ 0x58 8011642: 1c9a adds r2, r3, #2 8011644: 687b ldr r3, [r7, #4] 8011646: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8011648: 687b ldr r3, [r7, #4] 801164a: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 801164e: b29b uxth r3, r3 8011650: 3b01 subs r3, #1 8011652: b29a uxth r2, r3 8011654: 687b ldr r3, [r7, #4] 8011656: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 801165a: 687b ldr r3, [r7, #4] 801165c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011660: b29b uxth r3, r3 8011662: 2b00 cmp r3, #0 8011664: f040 80a1 bne.w 80117aa { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8011668: 687b ldr r3, [r7, #4] 801166a: 681b ldr r3, [r3, #0] 801166c: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801166e: 6cbb ldr r3, [r7, #72] @ 0x48 8011670: e853 3f00 ldrex r3, [r3] 8011674: 647b str r3, [r7, #68] @ 0x44 return(result); 8011676: 6c7b ldr r3, [r7, #68] @ 0x44 8011678: f423 7390 bic.w r3, r3, #288 @ 0x120 801167c: 667b str r3, [r7, #100] @ 0x64 801167e: 687b ldr r3, [r7, #4] 8011680: 681b ldr r3, [r3, #0] 8011682: 461a mov r2, r3 8011684: 6e7b ldr r3, [r7, #100] @ 0x64 8011686: 657b str r3, [r7, #84] @ 0x54 8011688: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801168a: 6d39 ldr r1, [r7, #80] @ 0x50 801168c: 6d7a ldr r2, [r7, #84] @ 0x54 801168e: e841 2300 strex r3, r2, [r1] 8011692: 64fb str r3, [r7, #76] @ 0x4c return(result); 8011694: 6cfb ldr r3, [r7, #76] @ 0x4c 8011696: 2b00 cmp r3, #0 8011698: d1e6 bne.n 8011668 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 801169a: 687b ldr r3, [r7, #4] 801169c: 681b ldr r3, [r3, #0] 801169e: 3308 adds r3, #8 80116a0: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80116a2: 6b7b ldr r3, [r7, #52] @ 0x34 80116a4: e853 3f00 ldrex r3, [r3] 80116a8: 633b str r3, [r7, #48] @ 0x30 return(result); 80116aa: 6b3b ldr r3, [r7, #48] @ 0x30 80116ac: f023 0301 bic.w r3, r3, #1 80116b0: 663b str r3, [r7, #96] @ 0x60 80116b2: 687b ldr r3, [r7, #4] 80116b4: 681b ldr r3, [r3, #0] 80116b6: 3308 adds r3, #8 80116b8: 6e3a ldr r2, [r7, #96] @ 0x60 80116ba: 643a str r2, [r7, #64] @ 0x40 80116bc: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80116be: 6bf9 ldr r1, [r7, #60] @ 0x3c 80116c0: 6c3a ldr r2, [r7, #64] @ 0x40 80116c2: e841 2300 strex r3, r2, [r1] 80116c6: 63bb str r3, [r7, #56] @ 0x38 return(result); 80116c8: 6bbb ldr r3, [r7, #56] @ 0x38 80116ca: 2b00 cmp r3, #0 80116cc: d1e5 bne.n 801169a /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80116ce: 687b ldr r3, [r7, #4] 80116d0: 2220 movs r2, #32 80116d2: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 80116d6: 687b ldr r3, [r7, #4] 80116d8: 2200 movs r2, #0 80116da: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80116dc: 687b ldr r3, [r7, #4] 80116de: 2200 movs r2, #0 80116e0: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 80116e2: 687b ldr r3, [r7, #4] 80116e4: 681b ldr r3, [r3, #0] 80116e6: 4a33 ldr r2, [pc, #204] @ (80117b4 ) 80116e8: 4293 cmp r3, r2 80116ea: d01f beq.n 801172c { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 80116ec: 687b ldr r3, [r7, #4] 80116ee: 681b ldr r3, [r3, #0] 80116f0: 685b ldr r3, [r3, #4] 80116f2: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80116f6: 2b00 cmp r3, #0 80116f8: d018 beq.n 801172c { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 80116fa: 687b ldr r3, [r7, #4] 80116fc: 681b ldr r3, [r3, #0] 80116fe: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011700: 6a3b ldr r3, [r7, #32] 8011702: e853 3f00 ldrex r3, [r3] 8011706: 61fb str r3, [r7, #28] return(result); 8011708: 69fb ldr r3, [r7, #28] 801170a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 801170e: 65fb str r3, [r7, #92] @ 0x5c 8011710: 687b ldr r3, [r7, #4] 8011712: 681b ldr r3, [r3, #0] 8011714: 461a mov r2, r3 8011716: 6dfb ldr r3, [r7, #92] @ 0x5c 8011718: 62fb str r3, [r7, #44] @ 0x2c 801171a: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801171c: 6ab9 ldr r1, [r7, #40] @ 0x28 801171e: 6afa ldr r2, [r7, #44] @ 0x2c 8011720: e841 2300 strex r3, r2, [r1] 8011724: 627b str r3, [r7, #36] @ 0x24 return(result); 8011726: 6a7b ldr r3, [r7, #36] @ 0x24 8011728: 2b00 cmp r3, #0 801172a: d1e6 bne.n 80116fa } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 801172c: 687b ldr r3, [r7, #4] 801172e: 6edb ldr r3, [r3, #108] @ 0x6c 8011730: 2b01 cmp r3, #1 8011732: d12e bne.n 8011792 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8011734: 687b ldr r3, [r7, #4] 8011736: 2200 movs r2, #0 8011738: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801173a: 687b ldr r3, [r7, #4] 801173c: 681b ldr r3, [r3, #0] 801173e: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011740: 68fb ldr r3, [r7, #12] 8011742: e853 3f00 ldrex r3, [r3] 8011746: 60bb str r3, [r7, #8] return(result); 8011748: 68bb ldr r3, [r7, #8] 801174a: f023 0310 bic.w r3, r3, #16 801174e: 65bb str r3, [r7, #88] @ 0x58 8011750: 687b ldr r3, [r7, #4] 8011752: 681b ldr r3, [r3, #0] 8011754: 461a mov r2, r3 8011756: 6dbb ldr r3, [r7, #88] @ 0x58 8011758: 61bb str r3, [r7, #24] 801175a: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801175c: 6979 ldr r1, [r7, #20] 801175e: 69ba ldr r2, [r7, #24] 8011760: e841 2300 strex r3, r2, [r1] 8011764: 613b str r3, [r7, #16] return(result); 8011766: 693b ldr r3, [r7, #16] 8011768: 2b00 cmp r3, #0 801176a: d1e6 bne.n 801173a if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 801176c: 687b ldr r3, [r7, #4] 801176e: 681b ldr r3, [r3, #0] 8011770: 69db ldr r3, [r3, #28] 8011772: f003 0310 and.w r3, r3, #16 8011776: 2b10 cmp r3, #16 8011778: d103 bne.n 8011782 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 801177a: 687b ldr r3, [r7, #4] 801177c: 681b ldr r3, [r3, #0] 801177e: 2210 movs r2, #16 8011780: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8011782: 687b ldr r3, [r7, #4] 8011784: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8011788: 4619 mov r1, r3 801178a: 6878 ldr r0, [r7, #4] 801178c: f7f2 fa34 bl 8003bf8 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8011790: e00b b.n 80117aa HAL_UART_RxCpltCallback(huart); 8011792: 6878 ldr r0, [r7, #4] 8011794: f7f2 fa26 bl 8003be4 } 8011798: e007 b.n 80117aa __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 801179a: 687b ldr r3, [r7, #4] 801179c: 681b ldr r3, [r3, #0] 801179e: 699a ldr r2, [r3, #24] 80117a0: 687b ldr r3, [r7, #4] 80117a2: 681b ldr r3, [r3, #0] 80117a4: f042 0208 orr.w r2, r2, #8 80117a8: 619a str r2, [r3, #24] } 80117aa: bf00 nop 80117ac: 3770 adds r7, #112 @ 0x70 80117ae: 46bd mov sp, r7 80117b0: bd80 pop {r7, pc} 80117b2: bf00 nop 80117b4: 58000c00 .word 0x58000c00 080117b8 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 80117b8: b580 push {r7, lr} 80117ba: b0ac sub sp, #176 @ 0xb0 80117bc: af00 add r7, sp, #0 80117be: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 80117c0: 687b ldr r3, [r7, #4] 80117c2: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 80117c6: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 80117ca: 687b ldr r3, [r7, #4] 80117cc: 681b ldr r3, [r3, #0] 80117ce: 69db ldr r3, [r3, #28] 80117d0: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr1its = READ_REG(huart->Instance->CR1); 80117d4: 687b ldr r3, [r7, #4] 80117d6: 681b ldr r3, [r3, #0] 80117d8: 681b ldr r3, [r3, #0] 80117da: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t cr3its = READ_REG(huart->Instance->CR3); 80117de: 687b ldr r3, [r7, #4] 80117e0: 681b ldr r3, [r3, #0] 80117e2: 689b ldr r3, [r3, #8] 80117e4: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80117e8: 687b ldr r3, [r7, #4] 80117ea: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80117ee: 2b22 cmp r3, #34 @ 0x22 80117f0: f040 8180 bne.w 8011af4 { nb_rx_data = huart->NbRxDataToProcess; 80117f4: 687b ldr r3, [r7, #4] 80117f6: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 80117fa: f8a7 309e strh.w r3, [r7, #158] @ 0x9e while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 80117fe: e123 b.n 8011a48 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8011800: 687b ldr r3, [r7, #4] 8011802: 681b ldr r3, [r3, #0] 8011804: 6a5b ldr r3, [r3, #36] @ 0x24 8011806: f8a7 309c strh.w r3, [r7, #156] @ 0x9c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 801180a: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c 801180e: b2d9 uxtb r1, r3 8011810: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa 8011814: b2da uxtb r2, r3 8011816: 687b ldr r3, [r7, #4] 8011818: 6d9b ldr r3, [r3, #88] @ 0x58 801181a: 400a ands r2, r1 801181c: b2d2 uxtb r2, r2 801181e: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8011820: 687b ldr r3, [r7, #4] 8011822: 6d9b ldr r3, [r3, #88] @ 0x58 8011824: 1c5a adds r2, r3, #1 8011826: 687b ldr r3, [r7, #4] 8011828: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 801182a: 687b ldr r3, [r7, #4] 801182c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011830: b29b uxth r3, r3 8011832: 3b01 subs r3, #1 8011834: b29a uxth r2, r3 8011836: 687b ldr r3, [r7, #4] 8011838: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 801183c: 687b ldr r3, [r7, #4] 801183e: 681b ldr r3, [r3, #0] 8011840: 69db ldr r3, [r3, #28] 8011842: f8c7 30ac str.w r3, [r7, #172] @ 0xac /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8011846: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801184a: f003 0307 and.w r3, r3, #7 801184e: 2b00 cmp r3, #0 8011850: d053 beq.n 80118fa { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8011852: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8011856: f003 0301 and.w r3, r3, #1 801185a: 2b00 cmp r3, #0 801185c: d011 beq.n 8011882 801185e: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 8011862: f403 7380 and.w r3, r3, #256 @ 0x100 8011866: 2b00 cmp r3, #0 8011868: d00b beq.n 8011882 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 801186a: 687b ldr r3, [r7, #4] 801186c: 681b ldr r3, [r3, #0] 801186e: 2201 movs r2, #1 8011870: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8011872: 687b ldr r3, [r7, #4] 8011874: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011878: f043 0201 orr.w r2, r3, #1 801187c: 687b ldr r3, [r7, #4] 801187e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8011882: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8011886: f003 0302 and.w r3, r3, #2 801188a: 2b00 cmp r3, #0 801188c: d011 beq.n 80118b2 801188e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8011892: f003 0301 and.w r3, r3, #1 8011896: 2b00 cmp r3, #0 8011898: d00b beq.n 80118b2 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 801189a: 687b ldr r3, [r7, #4] 801189c: 681b ldr r3, [r3, #0] 801189e: 2202 movs r2, #2 80118a0: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 80118a2: 687b ldr r3, [r7, #4] 80118a4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80118a8: f043 0204 orr.w r2, r3, #4 80118ac: 687b ldr r3, [r7, #4] 80118ae: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 80118b2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80118b6: f003 0304 and.w r3, r3, #4 80118ba: 2b00 cmp r3, #0 80118bc: d011 beq.n 80118e2 80118be: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80118c2: f003 0301 and.w r3, r3, #1 80118c6: 2b00 cmp r3, #0 80118c8: d00b beq.n 80118e2 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 80118ca: 687b ldr r3, [r7, #4] 80118cc: 681b ldr r3, [r3, #0] 80118ce: 2204 movs r2, #4 80118d0: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 80118d2: 687b ldr r3, [r7, #4] 80118d4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80118d8: f043 0202 orr.w r2, r3, #2 80118dc: 687b ldr r3, [r7, #4] 80118de: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 80118e2: 687b ldr r3, [r7, #4] 80118e4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80118e8: 2b00 cmp r3, #0 80118ea: d006 beq.n 80118fa #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80118ec: 6878 ldr r0, [r7, #4] 80118ee: f7fe fb13 bl 800ff18 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80118f2: 687b ldr r3, [r7, #4] 80118f4: 2200 movs r2, #0 80118f6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 80118fa: 687b ldr r3, [r7, #4] 80118fc: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011900: b29b uxth r3, r3 8011902: 2b00 cmp r3, #0 8011904: f040 80a0 bne.w 8011a48 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8011908: 687b ldr r3, [r7, #4] 801190a: 681b ldr r3, [r3, #0] 801190c: 673b str r3, [r7, #112] @ 0x70 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801190e: 6f3b ldr r3, [r7, #112] @ 0x70 8011910: e853 3f00 ldrex r3, [r3] 8011914: 66fb str r3, [r7, #108] @ 0x6c return(result); 8011916: 6efb ldr r3, [r7, #108] @ 0x6c 8011918: f423 7380 bic.w r3, r3, #256 @ 0x100 801191c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8011920: 687b ldr r3, [r7, #4] 8011922: 681b ldr r3, [r3, #0] 8011924: 461a mov r2, r3 8011926: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 801192a: 67fb str r3, [r7, #124] @ 0x7c 801192c: 67ba str r2, [r7, #120] @ 0x78 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801192e: 6fb9 ldr r1, [r7, #120] @ 0x78 8011930: 6ffa ldr r2, [r7, #124] @ 0x7c 8011932: e841 2300 strex r3, r2, [r1] 8011936: 677b str r3, [r7, #116] @ 0x74 return(result); 8011938: 6f7b ldr r3, [r7, #116] @ 0x74 801193a: 2b00 cmp r3, #0 801193c: d1e4 bne.n 8011908 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 801193e: 687b ldr r3, [r7, #4] 8011940: 681b ldr r3, [r3, #0] 8011942: 3308 adds r3, #8 8011944: 65fb str r3, [r7, #92] @ 0x5c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011946: 6dfb ldr r3, [r7, #92] @ 0x5c 8011948: e853 3f00 ldrex r3, [r3] 801194c: 65bb str r3, [r7, #88] @ 0x58 return(result); 801194e: 6dba ldr r2, [r7, #88] @ 0x58 8011950: 4b6e ldr r3, [pc, #440] @ (8011b0c ) 8011952: 4013 ands r3, r2 8011954: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8011958: 687b ldr r3, [r7, #4] 801195a: 681b ldr r3, [r3, #0] 801195c: 3308 adds r3, #8 801195e: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8011962: 66ba str r2, [r7, #104] @ 0x68 8011964: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011966: 6e79 ldr r1, [r7, #100] @ 0x64 8011968: 6eba ldr r2, [r7, #104] @ 0x68 801196a: e841 2300 strex r3, r2, [r1] 801196e: 663b str r3, [r7, #96] @ 0x60 return(result); 8011970: 6e3b ldr r3, [r7, #96] @ 0x60 8011972: 2b00 cmp r3, #0 8011974: d1e3 bne.n 801193e /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8011976: 687b ldr r3, [r7, #4] 8011978: 2220 movs r2, #32 801197a: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 801197e: 687b ldr r3, [r7, #4] 8011980: 2200 movs r2, #0 8011982: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8011984: 687b ldr r3, [r7, #4] 8011986: 2200 movs r2, #0 8011988: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 801198a: 687b ldr r3, [r7, #4] 801198c: 681b ldr r3, [r3, #0] 801198e: 4a60 ldr r2, [pc, #384] @ (8011b10 ) 8011990: 4293 cmp r3, r2 8011992: d021 beq.n 80119d8 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8011994: 687b ldr r3, [r7, #4] 8011996: 681b ldr r3, [r3, #0] 8011998: 685b ldr r3, [r3, #4] 801199a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 801199e: 2b00 cmp r3, #0 80119a0: d01a beq.n 80119d8 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 80119a2: 687b ldr r3, [r7, #4] 80119a4: 681b ldr r3, [r3, #0] 80119a6: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80119a8: 6cbb ldr r3, [r7, #72] @ 0x48 80119aa: e853 3f00 ldrex r3, [r3] 80119ae: 647b str r3, [r7, #68] @ 0x44 return(result); 80119b0: 6c7b ldr r3, [r7, #68] @ 0x44 80119b2: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 80119b6: f8c7 3090 str.w r3, [r7, #144] @ 0x90 80119ba: 687b ldr r3, [r7, #4] 80119bc: 681b ldr r3, [r3, #0] 80119be: 461a mov r2, r3 80119c0: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 80119c4: 657b str r3, [r7, #84] @ 0x54 80119c6: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80119c8: 6d39 ldr r1, [r7, #80] @ 0x50 80119ca: 6d7a ldr r2, [r7, #84] @ 0x54 80119cc: e841 2300 strex r3, r2, [r1] 80119d0: 64fb str r3, [r7, #76] @ 0x4c return(result); 80119d2: 6cfb ldr r3, [r7, #76] @ 0x4c 80119d4: 2b00 cmp r3, #0 80119d6: d1e4 bne.n 80119a2 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80119d8: 687b ldr r3, [r7, #4] 80119da: 6edb ldr r3, [r3, #108] @ 0x6c 80119dc: 2b01 cmp r3, #1 80119de: d130 bne.n 8011a42 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80119e0: 687b ldr r3, [r7, #4] 80119e2: 2200 movs r2, #0 80119e4: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80119e6: 687b ldr r3, [r7, #4] 80119e8: 681b ldr r3, [r3, #0] 80119ea: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80119ec: 6b7b ldr r3, [r7, #52] @ 0x34 80119ee: e853 3f00 ldrex r3, [r3] 80119f2: 633b str r3, [r7, #48] @ 0x30 return(result); 80119f4: 6b3b ldr r3, [r7, #48] @ 0x30 80119f6: f023 0310 bic.w r3, r3, #16 80119fa: f8c7 308c str.w r3, [r7, #140] @ 0x8c 80119fe: 687b ldr r3, [r7, #4] 8011a00: 681b ldr r3, [r3, #0] 8011a02: 461a mov r2, r3 8011a04: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8011a08: 643b str r3, [r7, #64] @ 0x40 8011a0a: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011a0c: 6bf9 ldr r1, [r7, #60] @ 0x3c 8011a0e: 6c3a ldr r2, [r7, #64] @ 0x40 8011a10: e841 2300 strex r3, r2, [r1] 8011a14: 63bb str r3, [r7, #56] @ 0x38 return(result); 8011a16: 6bbb ldr r3, [r7, #56] @ 0x38 8011a18: 2b00 cmp r3, #0 8011a1a: d1e4 bne.n 80119e6 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8011a1c: 687b ldr r3, [r7, #4] 8011a1e: 681b ldr r3, [r3, #0] 8011a20: 69db ldr r3, [r3, #28] 8011a22: f003 0310 and.w r3, r3, #16 8011a26: 2b10 cmp r3, #16 8011a28: d103 bne.n 8011a32 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8011a2a: 687b ldr r3, [r7, #4] 8011a2c: 681b ldr r3, [r3, #0] 8011a2e: 2210 movs r2, #16 8011a30: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8011a32: 687b ldr r3, [r7, #4] 8011a34: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8011a38: 4619 mov r1, r3 8011a3a: 6878 ldr r0, [r7, #4] 8011a3c: f7f2 f8dc bl 8003bf8 8011a40: e002 b.n 8011a48 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8011a42: 6878 ldr r0, [r7, #4] 8011a44: f7f2 f8ce bl 8003be4 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8011a48: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e 8011a4c: 2b00 cmp r3, #0 8011a4e: d006 beq.n 8011a5e 8011a50: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8011a54: f003 0320 and.w r3, r3, #32 8011a58: 2b00 cmp r3, #0 8011a5a: f47f aed1 bne.w 8011800 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 8011a5e: 687b ldr r3, [r7, #4] 8011a60: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011a64: f8a7 308a strh.w r3, [r7, #138] @ 0x8a if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 8011a68: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 8011a6c: 2b00 cmp r3, #0 8011a6e: d049 beq.n 8011b04 8011a70: 687b ldr r3, [r7, #4] 8011a72: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8011a76: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a 8011a7a: 429a cmp r2, r3 8011a7c: d242 bcs.n 8011b04 { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8011a7e: 687b ldr r3, [r7, #4] 8011a80: 681b ldr r3, [r3, #0] 8011a82: 3308 adds r3, #8 8011a84: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011a86: 6a3b ldr r3, [r7, #32] 8011a88: e853 3f00 ldrex r3, [r3] 8011a8c: 61fb str r3, [r7, #28] return(result); 8011a8e: 69fb ldr r3, [r7, #28] 8011a90: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8011a94: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8011a98: 687b ldr r3, [r7, #4] 8011a9a: 681b ldr r3, [r3, #0] 8011a9c: 3308 adds r3, #8 8011a9e: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 8011aa2: 62fa str r2, [r7, #44] @ 0x2c 8011aa4: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011aa6: 6ab9 ldr r1, [r7, #40] @ 0x28 8011aa8: 6afa ldr r2, [r7, #44] @ 0x2c 8011aaa: e841 2300 strex r3, r2, [r1] 8011aae: 627b str r3, [r7, #36] @ 0x24 return(result); 8011ab0: 6a7b ldr r3, [r7, #36] @ 0x24 8011ab2: 2b00 cmp r3, #0 8011ab4: d1e3 bne.n 8011a7e /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; 8011ab6: 687b ldr r3, [r7, #4] 8011ab8: 4a16 ldr r2, [pc, #88] @ (8011b14 ) 8011aba: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8011abc: 687b ldr r3, [r7, #4] 8011abe: 681b ldr r3, [r3, #0] 8011ac0: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011ac2: 68fb ldr r3, [r7, #12] 8011ac4: e853 3f00 ldrex r3, [r3] 8011ac8: 60bb str r3, [r7, #8] return(result); 8011aca: 68bb ldr r3, [r7, #8] 8011acc: f043 0320 orr.w r3, r3, #32 8011ad0: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8011ad4: 687b ldr r3, [r7, #4] 8011ad6: 681b ldr r3, [r3, #0] 8011ad8: 461a mov r2, r3 8011ada: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8011ade: 61bb str r3, [r7, #24] 8011ae0: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011ae2: 6979 ldr r1, [r7, #20] 8011ae4: 69ba ldr r2, [r7, #24] 8011ae6: e841 2300 strex r3, r2, [r1] 8011aea: 613b str r3, [r7, #16] return(result); 8011aec: 693b ldr r3, [r7, #16] 8011aee: 2b00 cmp r3, #0 8011af0: d1e4 bne.n 8011abc else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8011af2: e007 b.n 8011b04 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8011af4: 687b ldr r3, [r7, #4] 8011af6: 681b ldr r3, [r3, #0] 8011af8: 699a ldr r2, [r3, #24] 8011afa: 687b ldr r3, [r7, #4] 8011afc: 681b ldr r3, [r3, #0] 8011afe: f042 0208 orr.w r2, r2, #8 8011b02: 619a str r2, [r3, #24] } 8011b04: bf00 nop 8011b06: 37b0 adds r7, #176 @ 0xb0 8011b08: 46bd mov sp, r7 8011b0a: bd80 pop {r7, pc} 8011b0c: effffffe .word 0xeffffffe 8011b10: 58000c00 .word 0x58000c00 8011b14: 08011449 .word 0x08011449 08011b18 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 8011b18: b580 push {r7, lr} 8011b1a: b0ae sub sp, #184 @ 0xb8 8011b1c: af00 add r7, sp, #0 8011b1e: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 8011b20: 687b ldr r3, [r7, #4] 8011b22: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8011b26: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2 uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 8011b2a: 687b ldr r3, [r7, #4] 8011b2c: 681b ldr r3, [r3, #0] 8011b2e: 69db ldr r3, [r3, #28] 8011b30: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8011b34: 687b ldr r3, [r7, #4] 8011b36: 681b ldr r3, [r3, #0] 8011b38: 681b ldr r3, [r3, #0] 8011b3a: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr3its = READ_REG(huart->Instance->CR3); 8011b3e: 687b ldr r3, [r7, #4] 8011b40: 681b ldr r3, [r3, #0] 8011b42: 689b ldr r3, [r3, #8] 8011b44: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8011b48: 687b ldr r3, [r7, #4] 8011b4a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8011b4e: 2b22 cmp r3, #34 @ 0x22 8011b50: f040 8184 bne.w 8011e5c { nb_rx_data = huart->NbRxDataToProcess; 8011b54: 687b ldr r3, [r7, #4] 8011b56: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8011b5a: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8011b5e: e127 b.n 8011db0 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8011b60: 687b ldr r3, [r7, #4] 8011b62: 681b ldr r3, [r3, #0] 8011b64: 6a5b ldr r3, [r3, #36] @ 0x24 8011b66: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4 tmp = (uint16_t *) huart->pRxBuffPtr ; 8011b6a: 687b ldr r3, [r7, #4] 8011b6c: 6d9b ldr r3, [r3, #88] @ 0x58 8011b6e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 *tmp = (uint16_t)(uhdata & uhMask); 8011b72: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4 8011b76: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2 8011b7a: 4013 ands r3, r2 8011b7c: b29a uxth r2, r3 8011b7e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8011b82: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8011b84: 687b ldr r3, [r7, #4] 8011b86: 6d9b ldr r3, [r3, #88] @ 0x58 8011b88: 1c9a adds r2, r3, #2 8011b8a: 687b ldr r3, [r7, #4] 8011b8c: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8011b8e: 687b ldr r3, [r7, #4] 8011b90: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011b94: b29b uxth r3, r3 8011b96: 3b01 subs r3, #1 8011b98: b29a uxth r2, r3 8011b9a: 687b ldr r3, [r7, #4] 8011b9c: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 8011ba0: 687b ldr r3, [r7, #4] 8011ba2: 681b ldr r3, [r3, #0] 8011ba4: 69db ldr r3, [r3, #28] 8011ba6: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8011baa: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8011bae: f003 0307 and.w r3, r3, #7 8011bb2: 2b00 cmp r3, #0 8011bb4: d053 beq.n 8011c5e { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8011bb6: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8011bba: f003 0301 and.w r3, r3, #1 8011bbe: 2b00 cmp r3, #0 8011bc0: d011 beq.n 8011be6 8011bc2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8011bc6: f403 7380 and.w r3, r3, #256 @ 0x100 8011bca: 2b00 cmp r3, #0 8011bcc: d00b beq.n 8011be6 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8011bce: 687b ldr r3, [r7, #4] 8011bd0: 681b ldr r3, [r3, #0] 8011bd2: 2201 movs r2, #1 8011bd4: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8011bd6: 687b ldr r3, [r7, #4] 8011bd8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011bdc: f043 0201 orr.w r2, r3, #1 8011be0: 687b ldr r3, [r7, #4] 8011be2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8011be6: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8011bea: f003 0302 and.w r3, r3, #2 8011bee: 2b00 cmp r3, #0 8011bf0: d011 beq.n 8011c16 8011bf2: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8011bf6: f003 0301 and.w r3, r3, #1 8011bfa: 2b00 cmp r3, #0 8011bfc: d00b beq.n 8011c16 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8011bfe: 687b ldr r3, [r7, #4] 8011c00: 681b ldr r3, [r3, #0] 8011c02: 2202 movs r2, #2 8011c04: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8011c06: 687b ldr r3, [r7, #4] 8011c08: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011c0c: f043 0204 orr.w r2, r3, #4 8011c10: 687b ldr r3, [r7, #4] 8011c12: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8011c16: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8011c1a: f003 0304 and.w r3, r3, #4 8011c1e: 2b00 cmp r3, #0 8011c20: d011 beq.n 8011c46 8011c22: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8011c26: f003 0301 and.w r3, r3, #1 8011c2a: 2b00 cmp r3, #0 8011c2c: d00b beq.n 8011c46 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8011c2e: 687b ldr r3, [r7, #4] 8011c30: 681b ldr r3, [r3, #0] 8011c32: 2204 movs r2, #4 8011c34: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8011c36: 687b ldr r3, [r7, #4] 8011c38: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011c3c: f043 0202 orr.w r2, r3, #2 8011c40: 687b ldr r3, [r7, #4] 8011c42: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8011c46: 687b ldr r3, [r7, #4] 8011c48: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011c4c: 2b00 cmp r3, #0 8011c4e: d006 beq.n 8011c5e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8011c50: 6878 ldr r0, [r7, #4] 8011c52: f7fe f961 bl 800ff18 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8011c56: 687b ldr r3, [r7, #4] 8011c58: 2200 movs r2, #0 8011c5a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 8011c5e: 687b ldr r3, [r7, #4] 8011c60: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011c64: b29b uxth r3, r3 8011c66: 2b00 cmp r3, #0 8011c68: f040 80a2 bne.w 8011db0 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8011c6c: 687b ldr r3, [r7, #4] 8011c6e: 681b ldr r3, [r3, #0] 8011c70: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011c72: 6f7b ldr r3, [r7, #116] @ 0x74 8011c74: e853 3f00 ldrex r3, [r3] 8011c78: 673b str r3, [r7, #112] @ 0x70 return(result); 8011c7a: 6f3b ldr r3, [r7, #112] @ 0x70 8011c7c: f423 7380 bic.w r3, r3, #256 @ 0x100 8011c80: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8011c84: 687b ldr r3, [r7, #4] 8011c86: 681b ldr r3, [r3, #0] 8011c88: 461a mov r2, r3 8011c8a: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8011c8e: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8011c92: 67fa str r2, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011c94: 6ff9 ldr r1, [r7, #124] @ 0x7c 8011c96: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8011c9a: e841 2300 strex r3, r2, [r1] 8011c9e: 67bb str r3, [r7, #120] @ 0x78 return(result); 8011ca0: 6fbb ldr r3, [r7, #120] @ 0x78 8011ca2: 2b00 cmp r3, #0 8011ca4: d1e2 bne.n 8011c6c /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8011ca6: 687b ldr r3, [r7, #4] 8011ca8: 681b ldr r3, [r3, #0] 8011caa: 3308 adds r3, #8 8011cac: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011cae: 6e3b ldr r3, [r7, #96] @ 0x60 8011cb0: e853 3f00 ldrex r3, [r3] 8011cb4: 65fb str r3, [r7, #92] @ 0x5c return(result); 8011cb6: 6dfa ldr r2, [r7, #92] @ 0x5c 8011cb8: 4b6e ldr r3, [pc, #440] @ (8011e74 ) 8011cba: 4013 ands r3, r2 8011cbc: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8011cc0: 687b ldr r3, [r7, #4] 8011cc2: 681b ldr r3, [r3, #0] 8011cc4: 3308 adds r3, #8 8011cc6: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98 8011cca: 66fa str r2, [r7, #108] @ 0x6c 8011ccc: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011cce: 6eb9 ldr r1, [r7, #104] @ 0x68 8011cd0: 6efa ldr r2, [r7, #108] @ 0x6c 8011cd2: e841 2300 strex r3, r2, [r1] 8011cd6: 667b str r3, [r7, #100] @ 0x64 return(result); 8011cd8: 6e7b ldr r3, [r7, #100] @ 0x64 8011cda: 2b00 cmp r3, #0 8011cdc: d1e3 bne.n 8011ca6 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8011cde: 687b ldr r3, [r7, #4] 8011ce0: 2220 movs r2, #32 8011ce2: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8011ce6: 687b ldr r3, [r7, #4] 8011ce8: 2200 movs r2, #0 8011cea: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8011cec: 687b ldr r3, [r7, #4] 8011cee: 2200 movs r2, #0 8011cf0: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8011cf2: 687b ldr r3, [r7, #4] 8011cf4: 681b ldr r3, [r3, #0] 8011cf6: 4a60 ldr r2, [pc, #384] @ (8011e78 ) 8011cf8: 4293 cmp r3, r2 8011cfa: d021 beq.n 8011d40 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8011cfc: 687b ldr r3, [r7, #4] 8011cfe: 681b ldr r3, [r3, #0] 8011d00: 685b ldr r3, [r3, #4] 8011d02: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8011d06: 2b00 cmp r3, #0 8011d08: d01a beq.n 8011d40 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8011d0a: 687b ldr r3, [r7, #4] 8011d0c: 681b ldr r3, [r3, #0] 8011d0e: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011d10: 6cfb ldr r3, [r7, #76] @ 0x4c 8011d12: e853 3f00 ldrex r3, [r3] 8011d16: 64bb str r3, [r7, #72] @ 0x48 return(result); 8011d18: 6cbb ldr r3, [r7, #72] @ 0x48 8011d1a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8011d1e: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8011d22: 687b ldr r3, [r7, #4] 8011d24: 681b ldr r3, [r3, #0] 8011d26: 461a mov r2, r3 8011d28: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 8011d2c: 65bb str r3, [r7, #88] @ 0x58 8011d2e: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011d30: 6d79 ldr r1, [r7, #84] @ 0x54 8011d32: 6dba ldr r2, [r7, #88] @ 0x58 8011d34: e841 2300 strex r3, r2, [r1] 8011d38: 653b str r3, [r7, #80] @ 0x50 return(result); 8011d3a: 6d3b ldr r3, [r7, #80] @ 0x50 8011d3c: 2b00 cmp r3, #0 8011d3e: d1e4 bne.n 8011d0a } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8011d40: 687b ldr r3, [r7, #4] 8011d42: 6edb ldr r3, [r3, #108] @ 0x6c 8011d44: 2b01 cmp r3, #1 8011d46: d130 bne.n 8011daa { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8011d48: 687b ldr r3, [r7, #4] 8011d4a: 2200 movs r2, #0 8011d4c: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8011d4e: 687b ldr r3, [r7, #4] 8011d50: 681b ldr r3, [r3, #0] 8011d52: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011d54: 6bbb ldr r3, [r7, #56] @ 0x38 8011d56: e853 3f00 ldrex r3, [r3] 8011d5a: 637b str r3, [r7, #52] @ 0x34 return(result); 8011d5c: 6b7b ldr r3, [r7, #52] @ 0x34 8011d5e: f023 0310 bic.w r3, r3, #16 8011d62: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8011d66: 687b ldr r3, [r7, #4] 8011d68: 681b ldr r3, [r3, #0] 8011d6a: 461a mov r2, r3 8011d6c: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8011d70: 647b str r3, [r7, #68] @ 0x44 8011d72: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011d74: 6c39 ldr r1, [r7, #64] @ 0x40 8011d76: 6c7a ldr r2, [r7, #68] @ 0x44 8011d78: e841 2300 strex r3, r2, [r1] 8011d7c: 63fb str r3, [r7, #60] @ 0x3c return(result); 8011d7e: 6bfb ldr r3, [r7, #60] @ 0x3c 8011d80: 2b00 cmp r3, #0 8011d82: d1e4 bne.n 8011d4e if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8011d84: 687b ldr r3, [r7, #4] 8011d86: 681b ldr r3, [r3, #0] 8011d88: 69db ldr r3, [r3, #28] 8011d8a: f003 0310 and.w r3, r3, #16 8011d8e: 2b10 cmp r3, #16 8011d90: d103 bne.n 8011d9a { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8011d92: 687b ldr r3, [r7, #4] 8011d94: 681b ldr r3, [r3, #0] 8011d96: 2210 movs r2, #16 8011d98: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8011d9a: 687b ldr r3, [r7, #4] 8011d9c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8011da0: 4619 mov r1, r3 8011da2: 6878 ldr r0, [r7, #4] 8011da4: f7f1 ff28 bl 8003bf8 8011da8: e002 b.n 8011db0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8011daa: 6878 ldr r0, [r7, #4] 8011dac: f7f1 ff1a bl 8003be4 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8011db0: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6 8011db4: 2b00 cmp r3, #0 8011db6: d006 beq.n 8011dc6 8011db8: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8011dbc: f003 0320 and.w r3, r3, #32 8011dc0: 2b00 cmp r3, #0 8011dc2: f47f aecd bne.w 8011b60 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 8011dc6: 687b ldr r3, [r7, #4] 8011dc8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011dcc: f8a7 308e strh.w r3, [r7, #142] @ 0x8e if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 8011dd0: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e 8011dd4: 2b00 cmp r3, #0 8011dd6: d049 beq.n 8011e6c 8011dd8: 687b ldr r3, [r7, #4] 8011dda: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8011dde: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e 8011de2: 429a cmp r2, r3 8011de4: d242 bcs.n 8011e6c { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8011de6: 687b ldr r3, [r7, #4] 8011de8: 681b ldr r3, [r3, #0] 8011dea: 3308 adds r3, #8 8011dec: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011dee: 6a7b ldr r3, [r7, #36] @ 0x24 8011df0: e853 3f00 ldrex r3, [r3] 8011df4: 623b str r3, [r7, #32] return(result); 8011df6: 6a3b ldr r3, [r7, #32] 8011df8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8011dfc: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8011e00: 687b ldr r3, [r7, #4] 8011e02: 681b ldr r3, [r3, #0] 8011e04: 3308 adds r3, #8 8011e06: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88 8011e0a: 633a str r2, [r7, #48] @ 0x30 8011e0c: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011e0e: 6af9 ldr r1, [r7, #44] @ 0x2c 8011e10: 6b3a ldr r2, [r7, #48] @ 0x30 8011e12: e841 2300 strex r3, r2, [r1] 8011e16: 62bb str r3, [r7, #40] @ 0x28 return(result); 8011e18: 6abb ldr r3, [r7, #40] @ 0x28 8011e1a: 2b00 cmp r3, #0 8011e1c: d1e3 bne.n 8011de6 /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; 8011e1e: 687b ldr r3, [r7, #4] 8011e20: 4a16 ldr r2, [pc, #88] @ (8011e7c ) 8011e22: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8011e24: 687b ldr r3, [r7, #4] 8011e26: 681b ldr r3, [r3, #0] 8011e28: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011e2a: 693b ldr r3, [r7, #16] 8011e2c: e853 3f00 ldrex r3, [r3] 8011e30: 60fb str r3, [r7, #12] return(result); 8011e32: 68fb ldr r3, [r7, #12] 8011e34: f043 0320 orr.w r3, r3, #32 8011e38: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8011e3c: 687b ldr r3, [r7, #4] 8011e3e: 681b ldr r3, [r3, #0] 8011e40: 461a mov r2, r3 8011e42: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8011e46: 61fb str r3, [r7, #28] 8011e48: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011e4a: 69b9 ldr r1, [r7, #24] 8011e4c: 69fa ldr r2, [r7, #28] 8011e4e: e841 2300 strex r3, r2, [r1] 8011e52: 617b str r3, [r7, #20] return(result); 8011e54: 697b ldr r3, [r7, #20] 8011e56: 2b00 cmp r3, #0 8011e58: d1e4 bne.n 8011e24 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8011e5a: e007 b.n 8011e6c __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8011e5c: 687b ldr r3, [r7, #4] 8011e5e: 681b ldr r3, [r3, #0] 8011e60: 699a ldr r2, [r3, #24] 8011e62: 687b ldr r3, [r7, #4] 8011e64: 681b ldr r3, [r3, #0] 8011e66: f042 0208 orr.w r2, r2, #8 8011e6a: 619a str r2, [r3, #24] } 8011e6c: bf00 nop 8011e6e: 37b8 adds r7, #184 @ 0xb8 8011e70: 46bd mov sp, r7 8011e72: bd80 pop {r7, pc} 8011e74: effffffe .word 0xeffffffe 8011e78: 58000c00 .word 0x58000c00 8011e7c: 08011601 .word 0x08011601 08011e80 : * @brief UART wakeup from Stop mode callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { 8011e80: b480 push {r7} 8011e82: b083 sub sp, #12 8011e84: af00 add r7, sp, #0 8011e86: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } 8011e88: bf00 nop 8011e8a: 370c adds r7, #12 8011e8c: 46bd mov sp, r7 8011e8e: f85d 7b04 ldr.w r7, [sp], #4 8011e92: 4770 bx lr 08011e94 : * @brief UART RX Fifo full callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { 8011e94: b480 push {r7} 8011e96: b083 sub sp, #12 8011e98: af00 add r7, sp, #0 8011e9a: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. */ } 8011e9c: bf00 nop 8011e9e: 370c adds r7, #12 8011ea0: 46bd mov sp, r7 8011ea2: f85d 7b04 ldr.w r7, [sp], #4 8011ea6: 4770 bx lr 08011ea8 : * @brief UART TX Fifo empty callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { 8011ea8: b480 push {r7} 8011eaa: b083 sub sp, #12 8011eac: af00 add r7, sp, #0 8011eae: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } 8011eb0: bf00 nop 8011eb2: 370c adds r7, #12 8011eb4: 46bd mov sp, r7 8011eb6: f85d 7b04 ldr.w r7, [sp], #4 8011eba: 4770 bx lr 08011ebc : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 8011ebc: b480 push {r7} 8011ebe: b085 sub sp, #20 8011ec0: af00 add r7, sp, #0 8011ec2: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 8011ec4: 687b ldr r3, [r7, #4] 8011ec6: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8011eca: 2b01 cmp r3, #1 8011ecc: d101 bne.n 8011ed2 8011ece: 2302 movs r3, #2 8011ed0: e027 b.n 8011f22 8011ed2: 687b ldr r3, [r7, #4] 8011ed4: 2201 movs r2, #1 8011ed6: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8011eda: 687b ldr r3, [r7, #4] 8011edc: 2224 movs r2, #36 @ 0x24 8011ede: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8011ee2: 687b ldr r3, [r7, #4] 8011ee4: 681b ldr r3, [r3, #0] 8011ee6: 681b ldr r3, [r3, #0] 8011ee8: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8011eea: 687b ldr r3, [r7, #4] 8011eec: 681b ldr r3, [r3, #0] 8011eee: 681a ldr r2, [r3, #0] 8011ef0: 687b ldr r3, [r7, #4] 8011ef2: 681b ldr r3, [r3, #0] 8011ef4: f022 0201 bic.w r2, r2, #1 8011ef8: 601a str r2, [r3, #0] /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 8011efa: 68fb ldr r3, [r7, #12] 8011efc: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000 8011f00: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 8011f02: 687b ldr r3, [r7, #4] 8011f04: 2200 movs r2, #0 8011f06: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8011f08: 687b ldr r3, [r7, #4] 8011f0a: 681b ldr r3, [r3, #0] 8011f0c: 68fa ldr r2, [r7, #12] 8011f0e: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8011f10: 687b ldr r3, [r7, #4] 8011f12: 2220 movs r2, #32 8011f14: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8011f18: 687b ldr r3, [r7, #4] 8011f1a: 2200 movs r2, #0 8011f1c: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8011f20: 2300 movs r3, #0 } 8011f22: 4618 mov r0, r3 8011f24: 3714 adds r7, #20 8011f26: 46bd mov sp, r7 8011f28: f85d 7b04 ldr.w r7, [sp], #4 8011f2c: 4770 bx lr 08011f2e : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8011f2e: b580 push {r7, lr} 8011f30: b084 sub sp, #16 8011f32: af00 add r7, sp, #0 8011f34: 6078 str r0, [r7, #4] 8011f36: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8011f38: 687b ldr r3, [r7, #4] 8011f3a: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8011f3e: 2b01 cmp r3, #1 8011f40: d101 bne.n 8011f46 8011f42: 2302 movs r3, #2 8011f44: e02d b.n 8011fa2 8011f46: 687b ldr r3, [r7, #4] 8011f48: 2201 movs r2, #1 8011f4a: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8011f4e: 687b ldr r3, [r7, #4] 8011f50: 2224 movs r2, #36 @ 0x24 8011f52: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8011f56: 687b ldr r3, [r7, #4] 8011f58: 681b ldr r3, [r3, #0] 8011f5a: 681b ldr r3, [r3, #0] 8011f5c: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8011f5e: 687b ldr r3, [r7, #4] 8011f60: 681b ldr r3, [r3, #0] 8011f62: 681a ldr r2, [r3, #0] 8011f64: 687b ldr r3, [r7, #4] 8011f66: 681b ldr r3, [r3, #0] 8011f68: f022 0201 bic.w r2, r2, #1 8011f6c: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 8011f6e: 687b ldr r3, [r7, #4] 8011f70: 681b ldr r3, [r3, #0] 8011f72: 689b ldr r3, [r3, #8] 8011f74: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 8011f78: 687b ldr r3, [r7, #4] 8011f7a: 681b ldr r3, [r3, #0] 8011f7c: 683a ldr r2, [r7, #0] 8011f7e: 430a orrs r2, r1 8011f80: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8011f82: 6878 ldr r0, [r7, #4] 8011f84: f000 f8a0 bl 80120c8 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8011f88: 687b ldr r3, [r7, #4] 8011f8a: 681b ldr r3, [r3, #0] 8011f8c: 68fa ldr r2, [r7, #12] 8011f8e: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8011f90: 687b ldr r3, [r7, #4] 8011f92: 2220 movs r2, #32 8011f94: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8011f98: 687b ldr r3, [r7, #4] 8011f9a: 2200 movs r2, #0 8011f9c: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8011fa0: 2300 movs r3, #0 } 8011fa2: 4618 mov r0, r3 8011fa4: 3710 adds r7, #16 8011fa6: 46bd mov sp, r7 8011fa8: bd80 pop {r7, pc} 08011faa : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8011faa: b580 push {r7, lr} 8011fac: b084 sub sp, #16 8011fae: af00 add r7, sp, #0 8011fb0: 6078 str r0, [r7, #4] 8011fb2: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8011fb4: 687b ldr r3, [r7, #4] 8011fb6: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8011fba: 2b01 cmp r3, #1 8011fbc: d101 bne.n 8011fc2 8011fbe: 2302 movs r3, #2 8011fc0: e02d b.n 801201e 8011fc2: 687b ldr r3, [r7, #4] 8011fc4: 2201 movs r2, #1 8011fc6: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8011fca: 687b ldr r3, [r7, #4] 8011fcc: 2224 movs r2, #36 @ 0x24 8011fce: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8011fd2: 687b ldr r3, [r7, #4] 8011fd4: 681b ldr r3, [r3, #0] 8011fd6: 681b ldr r3, [r3, #0] 8011fd8: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8011fda: 687b ldr r3, [r7, #4] 8011fdc: 681b ldr r3, [r3, #0] 8011fde: 681a ldr r2, [r3, #0] 8011fe0: 687b ldr r3, [r7, #4] 8011fe2: 681b ldr r3, [r3, #0] 8011fe4: f022 0201 bic.w r2, r2, #1 8011fe8: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 8011fea: 687b ldr r3, [r7, #4] 8011fec: 681b ldr r3, [r3, #0] 8011fee: 689b ldr r3, [r3, #8] 8011ff0: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 8011ff4: 687b ldr r3, [r7, #4] 8011ff6: 681b ldr r3, [r3, #0] 8011ff8: 683a ldr r2, [r7, #0] 8011ffa: 430a orrs r2, r1 8011ffc: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8011ffe: 6878 ldr r0, [r7, #4] 8012000: f000 f862 bl 80120c8 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8012004: 687b ldr r3, [r7, #4] 8012006: 681b ldr r3, [r3, #0] 8012008: 68fa ldr r2, [r7, #12] 801200a: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 801200c: 687b ldr r3, [r7, #4] 801200e: 2220 movs r2, #32 8012010: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8012014: 687b ldr r3, [r7, #4] 8012016: 2200 movs r2, #0 8012018: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 801201c: 2300 movs r3, #0 } 801201e: 4618 mov r0, r3 8012020: 3710 adds r7, #16 8012022: 46bd mov sp, r7 8012024: bd80 pop {r7, pc} 08012026 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8012026: b580 push {r7, lr} 8012028: b08c sub sp, #48 @ 0x30 801202a: af00 add r7, sp, #0 801202c: 60f8 str r0, [r7, #12] 801202e: 60b9 str r1, [r7, #8] 8012030: 4613 mov r3, r2 8012032: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status = HAL_OK; 8012034: 2300 movs r3, #0 8012036: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 801203a: 68fb ldr r3, [r7, #12] 801203c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8012040: 2b20 cmp r3, #32 8012042: d13b bne.n 80120bc { if ((pData == NULL) || (Size == 0U)) 8012044: 68bb ldr r3, [r7, #8] 8012046: 2b00 cmp r3, #0 8012048: d002 beq.n 8012050 801204a: 88fb ldrh r3, [r7, #6] 801204c: 2b00 cmp r3, #0 801204e: d101 bne.n 8012054 { return HAL_ERROR; 8012050: 2301 movs r3, #1 8012052: e034 b.n 80120be } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8012054: 68fb ldr r3, [r7, #12] 8012056: 2201 movs r2, #1 8012058: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 801205a: 68fb ldr r3, [r7, #12] 801205c: 2200 movs r2, #0 801205e: 671a str r2, [r3, #112] @ 0x70 (void)UART_Start_Receive_IT(huart, pData, Size); 8012060: 88fb ldrh r3, [r7, #6] 8012062: 461a mov r2, r3 8012064: 68b9 ldr r1, [r7, #8] 8012066: 68f8 ldr r0, [r7, #12] 8012068: f7fe fe82 bl 8010d70 if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 801206c: 68fb ldr r3, [r7, #12] 801206e: 6edb ldr r3, [r3, #108] @ 0x6c 8012070: 2b01 cmp r3, #1 8012072: d11d bne.n 80120b0 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8012074: 68fb ldr r3, [r7, #12] 8012076: 681b ldr r3, [r3, #0] 8012078: 2210 movs r2, #16 801207a: 621a str r2, [r3, #32] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801207c: 68fb ldr r3, [r7, #12] 801207e: 681b ldr r3, [r3, #0] 8012080: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012082: 69bb ldr r3, [r7, #24] 8012084: e853 3f00 ldrex r3, [r3] 8012088: 617b str r3, [r7, #20] return(result); 801208a: 697b ldr r3, [r7, #20] 801208c: f043 0310 orr.w r3, r3, #16 8012090: 62bb str r3, [r7, #40] @ 0x28 8012092: 68fb ldr r3, [r7, #12] 8012094: 681b ldr r3, [r3, #0] 8012096: 461a mov r2, r3 8012098: 6abb ldr r3, [r7, #40] @ 0x28 801209a: 627b str r3, [r7, #36] @ 0x24 801209c: 623a str r2, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801209e: 6a39 ldr r1, [r7, #32] 80120a0: 6a7a ldr r2, [r7, #36] @ 0x24 80120a2: e841 2300 strex r3, r2, [r1] 80120a6: 61fb str r3, [r7, #28] return(result); 80120a8: 69fb ldr r3, [r7, #28] 80120aa: 2b00 cmp r3, #0 80120ac: d1e6 bne.n 801207c 80120ae: e002 b.n 80120b6 { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 80120b0: 2301 movs r3, #1 80120b2: f887 302f strb.w r3, [r7, #47] @ 0x2f } return status; 80120b6: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 80120ba: e000 b.n 80120be } else { return HAL_BUSY; 80120bc: 2302 movs r3, #2 } } 80120be: 4618 mov r0, r3 80120c0: 3730 adds r7, #48 @ 0x30 80120c2: 46bd mov sp, r7 80120c4: bd80 pop {r7, pc} ... 080120c8 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 80120c8: b480 push {r7} 80120ca: b085 sub sp, #20 80120cc: af00 add r7, sp, #0 80120ce: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 80120d0: 687b ldr r3, [r7, #4] 80120d2: 6e5b ldr r3, [r3, #100] @ 0x64 80120d4: 2b00 cmp r3, #0 80120d6: d108 bne.n 80120ea { huart->NbTxDataToProcess = 1U; 80120d8: 687b ldr r3, [r7, #4] 80120da: 2201 movs r2, #1 80120dc: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1U; 80120e0: 687b ldr r3, [r7, #4] 80120e2: 2201 movs r2, #1 80120e4: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 80120e8: e031 b.n 801214e rx_fifo_depth = RX_FIFO_DEPTH; 80120ea: 2310 movs r3, #16 80120ec: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 80120ee: 2310 movs r3, #16 80120f0: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 80120f2: 687b ldr r3, [r7, #4] 80120f4: 681b ldr r3, [r3, #0] 80120f6: 689b ldr r3, [r3, #8] 80120f8: 0e5b lsrs r3, r3, #25 80120fa: b2db uxtb r3, r3 80120fc: f003 0307 and.w r3, r3, #7 8012100: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 8012102: 687b ldr r3, [r7, #4] 8012104: 681b ldr r3, [r3, #0] 8012106: 689b ldr r3, [r3, #8] 8012108: 0f5b lsrs r3, r3, #29 801210a: b2db uxtb r3, r3 801210c: f003 0307 and.w r3, r3, #7 8012110: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8012112: 7bbb ldrb r3, [r7, #14] 8012114: 7b3a ldrb r2, [r7, #12] 8012116: 4911 ldr r1, [pc, #68] @ (801215c ) 8012118: 5c8a ldrb r2, [r1, r2] 801211a: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 801211e: 7b3a ldrb r2, [r7, #12] 8012120: 490f ldr r1, [pc, #60] @ (8012160 ) 8012122: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8012124: fb93 f3f2 sdiv r3, r3, r2 8012128: b29a uxth r2, r3 801212a: 687b ldr r3, [r7, #4] 801212c: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8012130: 7bfb ldrb r3, [r7, #15] 8012132: 7b7a ldrb r2, [r7, #13] 8012134: 4909 ldr r1, [pc, #36] @ (801215c ) 8012136: 5c8a ldrb r2, [r1, r2] 8012138: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 801213c: 7b7a ldrb r2, [r7, #13] 801213e: 4908 ldr r1, [pc, #32] @ (8012160 ) 8012140: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8012142: fb93 f3f2 sdiv r3, r3, r2 8012146: b29a uxth r2, r3 8012148: 687b ldr r3, [r7, #4] 801214a: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 } 801214e: bf00 nop 8012150: 3714 adds r7, #20 8012152: 46bd mov sp, r7 8012154: f85d 7b04 ldr.w r7, [sp], #4 8012158: 4770 bx lr 801215a: bf00 nop 801215c: 080175f8 .word 0x080175f8 8012160: 08017600 .word 0x08017600 08012164 <__NVIC_SetPriority>: { 8012164: b480 push {r7} 8012166: b083 sub sp, #12 8012168: af00 add r7, sp, #0 801216a: 4603 mov r3, r0 801216c: 6039 str r1, [r7, #0] 801216e: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8012170: f9b7 3006 ldrsh.w r3, [r7, #6] 8012174: 2b00 cmp r3, #0 8012176: db0a blt.n 801218e <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8012178: 683b ldr r3, [r7, #0] 801217a: b2da uxtb r2, r3 801217c: 490c ldr r1, [pc, #48] @ (80121b0 <__NVIC_SetPriority+0x4c>) 801217e: f9b7 3006 ldrsh.w r3, [r7, #6] 8012182: 0112 lsls r2, r2, #4 8012184: b2d2 uxtb r2, r2 8012186: 440b add r3, r1 8012188: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 801218c: e00a b.n 80121a4 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 801218e: 683b ldr r3, [r7, #0] 8012190: b2da uxtb r2, r3 8012192: 4908 ldr r1, [pc, #32] @ (80121b4 <__NVIC_SetPriority+0x50>) 8012194: 88fb ldrh r3, [r7, #6] 8012196: f003 030f and.w r3, r3, #15 801219a: 3b04 subs r3, #4 801219c: 0112 lsls r2, r2, #4 801219e: b2d2 uxtb r2, r2 80121a0: 440b add r3, r1 80121a2: 761a strb r2, [r3, #24] } 80121a4: bf00 nop 80121a6: 370c adds r7, #12 80121a8: 46bd mov sp, r7 80121aa: f85d 7b04 ldr.w r7, [sp], #4 80121ae: 4770 bx lr 80121b0: e000e100 .word 0xe000e100 80121b4: e000ed00 .word 0xe000ed00 080121b8 : /* SysTick handler implementation that also clears overflow flag. */ #if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) void SysTick_Handler (void) { 80121b8: b580 push {r7, lr} 80121ba: af00 add r7, sp, #0 /* Clear overflow flag */ SysTick->CTRL; 80121bc: 4b05 ldr r3, [pc, #20] @ (80121d4 ) 80121be: 681b ldr r3, [r3, #0] if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { 80121c0: f002 fd1e bl 8014c00 80121c4: 4603 mov r3, r0 80121c6: 2b01 cmp r3, #1 80121c8: d001 beq.n 80121ce /* Call tick handler */ xPortSysTickHandler(); 80121ca: f003 ff2d bl 8016028 } } 80121ce: bf00 nop 80121d0: bd80 pop {r7, pc} 80121d2: bf00 nop 80121d4: e000e010 .word 0xe000e010 080121d8 : #endif /* SysTick */ /* Setup SVC to reset value. */ __STATIC_INLINE void SVC_Setup (void) { 80121d8: b580 push {r7, lr} 80121da: af00 add r7, sp, #0 #if (__ARM_ARCH_7A__ == 0U) /* Service Call interrupt might be configured before kernel start */ /* and when its priority is lower or equal to BASEPRI, svc intruction */ /* causes a Hard Fault. */ NVIC_SetPriority (SVCall_IRQ_NBR, 0U); 80121dc: 2100 movs r1, #0 80121de: f06f 0004 mvn.w r0, #4 80121e2: f7ff ffbf bl 8012164 <__NVIC_SetPriority> #endif } 80121e6: bf00 nop 80121e8: bd80 pop {r7, pc} ... 080121ec : static uint32_t OS_Tick_GetOverflow (void); /* Get OS Tick interval */ static uint32_t OS_Tick_GetInterval (void); /*---------------------------------------------------------------------------*/ osStatus_t osKernelInitialize (void) { 80121ec: b480 push {r7} 80121ee: b083 sub sp, #12 80121f0: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80121f2: f3ef 8305 mrs r3, IPSR 80121f6: 603b str r3, [r7, #0] return(result); 80121f8: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 80121fa: 2b00 cmp r3, #0 80121fc: d003 beq.n 8012206 stat = osErrorISR; 80121fe: f06f 0305 mvn.w r3, #5 8012202: 607b str r3, [r7, #4] 8012204: e00c b.n 8012220 } else { if (KernelState == osKernelInactive) { 8012206: 4b0a ldr r3, [pc, #40] @ (8012230 ) 8012208: 681b ldr r3, [r3, #0] 801220a: 2b00 cmp r3, #0 801220c: d105 bne.n 801221a EvrFreeRTOSSetup(0U); #endif #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) vPortDefineHeapRegions (configHEAP_5_REGIONS); #endif KernelState = osKernelReady; 801220e: 4b08 ldr r3, [pc, #32] @ (8012230 ) 8012210: 2201 movs r2, #1 8012212: 601a str r2, [r3, #0] stat = osOK; 8012214: 2300 movs r3, #0 8012216: 607b str r3, [r7, #4] 8012218: e002 b.n 8012220 } else { stat = osError; 801221a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801221e: 607b str r3, [r7, #4] } } return (stat); 8012220: 687b ldr r3, [r7, #4] } 8012222: 4618 mov r0, r3 8012224: 370c adds r7, #12 8012226: 46bd mov sp, r7 8012228: f85d 7b04 ldr.w r7, [sp], #4 801222c: 4770 bx lr 801222e: bf00 nop 8012230: 24000c10 .word 0x24000c10 08012234 : } return (state); } osStatus_t osKernelStart (void) { 8012234: b580 push {r7, lr} 8012236: b082 sub sp, #8 8012238: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801223a: f3ef 8305 mrs r3, IPSR 801223e: 603b str r3, [r7, #0] return(result); 8012240: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 8012242: 2b00 cmp r3, #0 8012244: d003 beq.n 801224e stat = osErrorISR; 8012246: f06f 0305 mvn.w r3, #5 801224a: 607b str r3, [r7, #4] 801224c: e010 b.n 8012270 } else { if (KernelState == osKernelReady) { 801224e: 4b0b ldr r3, [pc, #44] @ (801227c ) 8012250: 681b ldr r3, [r3, #0] 8012252: 2b01 cmp r3, #1 8012254: d109 bne.n 801226a /* Ensure SVC priority is at the reset value */ SVC_Setup(); 8012256: f7ff ffbf bl 80121d8 /* Change state to enable IRQ masking check */ KernelState = osKernelRunning; 801225a: 4b08 ldr r3, [pc, #32] @ (801227c ) 801225c: 2202 movs r2, #2 801225e: 601a str r2, [r3, #0] /* Start the kernel scheduler */ vTaskStartScheduler(); 8012260: f002 f824 bl 80142ac stat = osOK; 8012264: 2300 movs r3, #0 8012266: 607b str r3, [r7, #4] 8012268: e002 b.n 8012270 } else { stat = osError; 801226a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801226e: 607b str r3, [r7, #4] } } return (stat); 8012270: 687b ldr r3, [r7, #4] } 8012272: 4618 mov r0, r3 8012274: 3708 adds r7, #8 8012276: 46bd mov sp, r7 8012278: bd80 pop {r7, pc} 801227a: bf00 nop 801227c: 24000c10 .word 0x24000c10 08012280 : return (configCPU_CLOCK_HZ); } /*---------------------------------------------------------------------------*/ osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { 8012280: b580 push {r7, lr} 8012282: b08e sub sp, #56 @ 0x38 8012284: af04 add r7, sp, #16 8012286: 60f8 str r0, [r7, #12] 8012288: 60b9 str r1, [r7, #8] 801228a: 607a str r2, [r7, #4] uint32_t stack; TaskHandle_t hTask; UBaseType_t prio; int32_t mem; hTask = NULL; 801228c: 2300 movs r3, #0 801228e: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8012290: f3ef 8305 mrs r3, IPSR 8012294: 617b str r3, [r7, #20] return(result); 8012296: 697b ldr r3, [r7, #20] if (!IS_IRQ() && (func != NULL)) { 8012298: 2b00 cmp r3, #0 801229a: d17f bne.n 801239c 801229c: 68fb ldr r3, [r7, #12] 801229e: 2b00 cmp r3, #0 80122a0: d07c beq.n 801239c stack = configMINIMAL_STACK_SIZE; 80122a2: f44f 7300 mov.w r3, #512 @ 0x200 80122a6: 623b str r3, [r7, #32] prio = (UBaseType_t)osPriorityNormal; 80122a8: 2318 movs r3, #24 80122aa: 61fb str r3, [r7, #28] name = NULL; 80122ac: 2300 movs r3, #0 80122ae: 627b str r3, [r7, #36] @ 0x24 mem = -1; 80122b0: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80122b4: 61bb str r3, [r7, #24] if (attr != NULL) { 80122b6: 687b ldr r3, [r7, #4] 80122b8: 2b00 cmp r3, #0 80122ba: d045 beq.n 8012348 if (attr->name != NULL) { 80122bc: 687b ldr r3, [r7, #4] 80122be: 681b ldr r3, [r3, #0] 80122c0: 2b00 cmp r3, #0 80122c2: d002 beq.n 80122ca name = attr->name; 80122c4: 687b ldr r3, [r7, #4] 80122c6: 681b ldr r3, [r3, #0] 80122c8: 627b str r3, [r7, #36] @ 0x24 } if (attr->priority != osPriorityNone) { 80122ca: 687b ldr r3, [r7, #4] 80122cc: 699b ldr r3, [r3, #24] 80122ce: 2b00 cmp r3, #0 80122d0: d002 beq.n 80122d8 prio = (UBaseType_t)attr->priority; 80122d2: 687b ldr r3, [r7, #4] 80122d4: 699b ldr r3, [r3, #24] 80122d6: 61fb str r3, [r7, #28] } if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { 80122d8: 69fb ldr r3, [r7, #28] 80122da: 2b00 cmp r3, #0 80122dc: d008 beq.n 80122f0 80122de: 69fb ldr r3, [r7, #28] 80122e0: 2b38 cmp r3, #56 @ 0x38 80122e2: d805 bhi.n 80122f0 80122e4: 687b ldr r3, [r7, #4] 80122e6: 685b ldr r3, [r3, #4] 80122e8: f003 0301 and.w r3, r3, #1 80122ec: 2b00 cmp r3, #0 80122ee: d001 beq.n 80122f4 return (NULL); 80122f0: 2300 movs r3, #0 80122f2: e054 b.n 801239e } if (attr->stack_size > 0U) { 80122f4: 687b ldr r3, [r7, #4] 80122f6: 695b ldr r3, [r3, #20] 80122f8: 2b00 cmp r3, #0 80122fa: d003 beq.n 8012304 /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ stack = attr->stack_size / sizeof(StackType_t); 80122fc: 687b ldr r3, [r7, #4] 80122fe: 695b ldr r3, [r3, #20] 8012300: 089b lsrs r3, r3, #2 8012302: 623b str r3, [r7, #32] } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 8012304: 687b ldr r3, [r7, #4] 8012306: 689b ldr r3, [r3, #8] 8012308: 2b00 cmp r3, #0 801230a: d00e beq.n 801232a 801230c: 687b ldr r3, [r7, #4] 801230e: 68db ldr r3, [r3, #12] 8012310: 2ba7 cmp r3, #167 @ 0xa7 8012312: d90a bls.n 801232a (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 8012314: 687b ldr r3, [r7, #4] 8012316: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 8012318: 2b00 cmp r3, #0 801231a: d006 beq.n 801232a (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 801231c: 687b ldr r3, [r7, #4] 801231e: 695b ldr r3, [r3, #20] 8012320: 2b00 cmp r3, #0 8012322: d002 beq.n 801232a mem = 1; 8012324: 2301 movs r3, #1 8012326: 61bb str r3, [r7, #24] 8012328: e010 b.n 801234c } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { 801232a: 687b ldr r3, [r7, #4] 801232c: 689b ldr r3, [r3, #8] 801232e: 2b00 cmp r3, #0 8012330: d10c bne.n 801234c 8012332: 687b ldr r3, [r7, #4] 8012334: 68db ldr r3, [r3, #12] 8012336: 2b00 cmp r3, #0 8012338: d108 bne.n 801234c 801233a: 687b ldr r3, [r7, #4] 801233c: 691b ldr r3, [r3, #16] 801233e: 2b00 cmp r3, #0 8012340: d104 bne.n 801234c mem = 0; 8012342: 2300 movs r3, #0 8012344: 61bb str r3, [r7, #24] 8012346: e001 b.n 801234c } } } else { mem = 0; 8012348: 2300 movs r3, #0 801234a: 61bb str r3, [r7, #24] } if (mem == 1) { 801234c: 69bb ldr r3, [r7, #24] 801234e: 2b01 cmp r3, #1 8012350: d110 bne.n 8012374 #if (configSUPPORT_STATIC_ALLOCATION == 1) hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 8012352: 687b ldr r3, [r7, #4] 8012354: 691b ldr r3, [r3, #16] (StaticTask_t *)attr->cb_mem); 8012356: 687a ldr r2, [r7, #4] 8012358: 6892 ldr r2, [r2, #8] hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 801235a: 9202 str r2, [sp, #8] 801235c: 9301 str r3, [sp, #4] 801235e: 69fb ldr r3, [r7, #28] 8012360: 9300 str r3, [sp, #0] 8012362: 68bb ldr r3, [r7, #8] 8012364: 6a3a ldr r2, [r7, #32] 8012366: 6a79 ldr r1, [r7, #36] @ 0x24 8012368: 68f8 ldr r0, [r7, #12] 801236a: f001 fdac bl 8013ec6 801236e: 4603 mov r3, r0 8012370: 613b str r3, [r7, #16] 8012372: e013 b.n 801239c #endif } else { if (mem == 0) { 8012374: 69bb ldr r3, [r7, #24] 8012376: 2b00 cmp r3, #0 8012378: d110 bne.n 801239c #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { 801237a: 6a3b ldr r3, [r7, #32] 801237c: b29a uxth r2, r3 801237e: f107 0310 add.w r3, r7, #16 8012382: 9301 str r3, [sp, #4] 8012384: 69fb ldr r3, [r7, #28] 8012386: 9300 str r3, [sp, #0] 8012388: 68bb ldr r3, [r7, #8] 801238a: 6a79 ldr r1, [r7, #36] @ 0x24 801238c: 68f8 ldr r0, [r7, #12] 801238e: f001 fdfa bl 8013f86 8012392: 4603 mov r3, r0 8012394: 2b01 cmp r3, #1 8012396: d001 beq.n 801239c hTask = NULL; 8012398: 2300 movs r3, #0 801239a: 613b str r3, [r7, #16] #endif } } } return ((osThreadId_t)hTask); 801239c: 693b ldr r3, [r7, #16] } 801239e: 4618 mov r0, r3 80123a0: 3728 adds r7, #40 @ 0x28 80123a2: 46bd mov sp, r7 80123a4: bd80 pop {r7, pc} 080123a6 : /* Return flags before clearing */ return (rflags); } #endif /* (configUSE_OS2_THREAD_FLAGS == 1) */ osStatus_t osDelay (uint32_t ticks) { 80123a6: b580 push {r7, lr} 80123a8: b084 sub sp, #16 80123aa: af00 add r7, sp, #0 80123ac: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80123ae: f3ef 8305 mrs r3, IPSR 80123b2: 60bb str r3, [r7, #8] return(result); 80123b4: 68bb ldr r3, [r7, #8] osStatus_t stat; if (IS_IRQ()) { 80123b6: 2b00 cmp r3, #0 80123b8: d003 beq.n 80123c2 stat = osErrorISR; 80123ba: f06f 0305 mvn.w r3, #5 80123be: 60fb str r3, [r7, #12] 80123c0: e007 b.n 80123d2 } else { stat = osOK; 80123c2: 2300 movs r3, #0 80123c4: 60fb str r3, [r7, #12] if (ticks != 0U) { 80123c6: 687b ldr r3, [r7, #4] 80123c8: 2b00 cmp r3, #0 80123ca: d002 beq.n 80123d2 vTaskDelay(ticks); 80123cc: 6878 ldr r0, [r7, #4] 80123ce: f001 ff37 bl 8014240 } } return (stat); 80123d2: 68fb ldr r3, [r7, #12] } 80123d4: 4618 mov r0, r3 80123d6: 3710 adds r7, #16 80123d8: 46bd mov sp, r7 80123da: bd80 pop {r7, pc} 080123dc : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_TIMER == 1) static void TimerCallback (TimerHandle_t hTimer) { 80123dc: b580 push {r7, lr} 80123de: b084 sub sp, #16 80123e0: af00 add r7, sp, #0 80123e2: 6078 str r0, [r7, #4] TimerCallback_t *callb; callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); 80123e4: 6878 ldr r0, [r7, #4] 80123e6: f003 fc3d bl 8015c64 80123ea: 60f8 str r0, [r7, #12] if (callb != NULL) { 80123ec: 68fb ldr r3, [r7, #12] 80123ee: 2b00 cmp r3, #0 80123f0: d005 beq.n 80123fe callb->func (callb->arg); 80123f2: 68fb ldr r3, [r7, #12] 80123f4: 681b ldr r3, [r3, #0] 80123f6: 68fa ldr r2, [r7, #12] 80123f8: 6852 ldr r2, [r2, #4] 80123fa: 4610 mov r0, r2 80123fc: 4798 blx r3 } } 80123fe: bf00 nop 8012400: 3710 adds r7, #16 8012402: 46bd mov sp, r7 8012404: bd80 pop {r7, pc} ... 08012408 : osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { 8012408: b580 push {r7, lr} 801240a: b08c sub sp, #48 @ 0x30 801240c: af02 add r7, sp, #8 801240e: 60f8 str r0, [r7, #12] 8012410: 607a str r2, [r7, #4] 8012412: 603b str r3, [r7, #0] 8012414: 460b mov r3, r1 8012416: 72fb strb r3, [r7, #11] TimerHandle_t hTimer; TimerCallback_t *callb; UBaseType_t reload; int32_t mem; hTimer = NULL; 8012418: 2300 movs r3, #0 801241a: 623b str r3, [r7, #32] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801241c: f3ef 8305 mrs r3, IPSR 8012420: 613b str r3, [r7, #16] return(result); 8012422: 693b ldr r3, [r7, #16] if (!IS_IRQ() && (func != NULL)) { 8012424: 2b00 cmp r3, #0 8012426: d163 bne.n 80124f0 8012428: 68fb ldr r3, [r7, #12] 801242a: 2b00 cmp r3, #0 801242c: d060 beq.n 80124f0 /* Allocate memory to store callback function and argument */ callb = pvPortMalloc (sizeof(TimerCallback_t)); 801242e: 2008 movs r0, #8 8012430: f003 fe8c bl 801614c 8012434: 6178 str r0, [r7, #20] if (callb != NULL) { 8012436: 697b ldr r3, [r7, #20] 8012438: 2b00 cmp r3, #0 801243a: d059 beq.n 80124f0 callb->func = func; 801243c: 697b ldr r3, [r7, #20] 801243e: 68fa ldr r2, [r7, #12] 8012440: 601a str r2, [r3, #0] callb->arg = argument; 8012442: 697b ldr r3, [r7, #20] 8012444: 687a ldr r2, [r7, #4] 8012446: 605a str r2, [r3, #4] if (type == osTimerOnce) { 8012448: 7afb ldrb r3, [r7, #11] 801244a: 2b00 cmp r3, #0 801244c: d102 bne.n 8012454 reload = pdFALSE; 801244e: 2300 movs r3, #0 8012450: 61fb str r3, [r7, #28] 8012452: e001 b.n 8012458 } else { reload = pdTRUE; 8012454: 2301 movs r3, #1 8012456: 61fb str r3, [r7, #28] } mem = -1; 8012458: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801245c: 61bb str r3, [r7, #24] name = NULL; 801245e: 2300 movs r3, #0 8012460: 627b str r3, [r7, #36] @ 0x24 if (attr != NULL) { 8012462: 683b ldr r3, [r7, #0] 8012464: 2b00 cmp r3, #0 8012466: d01c beq.n 80124a2 if (attr->name != NULL) { 8012468: 683b ldr r3, [r7, #0] 801246a: 681b ldr r3, [r3, #0] 801246c: 2b00 cmp r3, #0 801246e: d002 beq.n 8012476 name = attr->name; 8012470: 683b ldr r3, [r7, #0] 8012472: 681b ldr r3, [r3, #0] 8012474: 627b str r3, [r7, #36] @ 0x24 } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) { 8012476: 683b ldr r3, [r7, #0] 8012478: 689b ldr r3, [r3, #8] 801247a: 2b00 cmp r3, #0 801247c: d006 beq.n 801248c 801247e: 683b ldr r3, [r7, #0] 8012480: 68db ldr r3, [r3, #12] 8012482: 2b2b cmp r3, #43 @ 0x2b 8012484: d902 bls.n 801248c mem = 1; 8012486: 2301 movs r3, #1 8012488: 61bb str r3, [r7, #24] 801248a: e00c b.n 80124a6 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 801248c: 683b ldr r3, [r7, #0] 801248e: 689b ldr r3, [r3, #8] 8012490: 2b00 cmp r3, #0 8012492: d108 bne.n 80124a6 8012494: 683b ldr r3, [r7, #0] 8012496: 68db ldr r3, [r3, #12] 8012498: 2b00 cmp r3, #0 801249a: d104 bne.n 80124a6 mem = 0; 801249c: 2300 movs r3, #0 801249e: 61bb str r3, [r7, #24] 80124a0: e001 b.n 80124a6 } } } else { mem = 0; 80124a2: 2300 movs r3, #0 80124a4: 61bb str r3, [r7, #24] } if (mem == 1) { 80124a6: 69bb ldr r3, [r7, #24] 80124a8: 2b01 cmp r3, #1 80124aa: d10c bne.n 80124c6 #if (configSUPPORT_STATIC_ALLOCATION == 1) hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem); 80124ac: 683b ldr r3, [r7, #0] 80124ae: 689b ldr r3, [r3, #8] 80124b0: 9301 str r3, [sp, #4] 80124b2: 4b12 ldr r3, [pc, #72] @ (80124fc ) 80124b4: 9300 str r3, [sp, #0] 80124b6: 697b ldr r3, [r7, #20] 80124b8: 69fa ldr r2, [r7, #28] 80124ba: 2101 movs r1, #1 80124bc: 6a78 ldr r0, [r7, #36] @ 0x24 80124be: f003 f81a bl 80154f6 80124c2: 6238 str r0, [r7, #32] 80124c4: e00b b.n 80124de #endif } else { if (mem == 0) { 80124c6: 69bb ldr r3, [r7, #24] 80124c8: 2b00 cmp r3, #0 80124ca: d108 bne.n 80124de #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback); 80124cc: 4b0b ldr r3, [pc, #44] @ (80124fc ) 80124ce: 9300 str r3, [sp, #0] 80124d0: 697b ldr r3, [r7, #20] 80124d2: 69fa ldr r2, [r7, #28] 80124d4: 2101 movs r1, #1 80124d6: 6a78 ldr r0, [r7, #36] @ 0x24 80124d8: f002 ffec bl 80154b4 80124dc: 6238 str r0, [r7, #32] #endif } } if ((hTimer == NULL) && (callb != NULL)) { 80124de: 6a3b ldr r3, [r7, #32] 80124e0: 2b00 cmp r3, #0 80124e2: d105 bne.n 80124f0 80124e4: 697b ldr r3, [r7, #20] 80124e6: 2b00 cmp r3, #0 80124e8: d002 beq.n 80124f0 vPortFree (callb); 80124ea: 6978 ldr r0, [r7, #20] 80124ec: f003 fefc bl 80162e8 } } } return ((osTimerId_t)hTimer); 80124f0: 6a3b ldr r3, [r7, #32] } 80124f2: 4618 mov r0, r3 80124f4: 3728 adds r7, #40 @ 0x28 80124f6: 46bd mov sp, r7 80124f8: bd80 pop {r7, pc} 80124fa: bf00 nop 80124fc: 080123dd .word 0x080123dd 08012500 : } return (p); } osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) { 8012500: b580 push {r7, lr} 8012502: b088 sub sp, #32 8012504: af02 add r7, sp, #8 8012506: 6078 str r0, [r7, #4] 8012508: 6039 str r1, [r7, #0] TimerHandle_t hTimer = (TimerHandle_t)timer_id; 801250a: 687b ldr r3, [r7, #4] 801250c: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801250e: f3ef 8305 mrs r3, IPSR 8012512: 60fb str r3, [r7, #12] return(result); 8012514: 68fb ldr r3, [r7, #12] osStatus_t stat; if (IS_IRQ()) { 8012516: 2b00 cmp r3, #0 8012518: d003 beq.n 8012522 stat = osErrorISR; 801251a: f06f 0305 mvn.w r3, #5 801251e: 617b str r3, [r7, #20] 8012520: e017 b.n 8012552 } else if (hTimer == NULL) { 8012522: 693b ldr r3, [r7, #16] 8012524: 2b00 cmp r3, #0 8012526: d103 bne.n 8012530 stat = osErrorParameter; 8012528: f06f 0303 mvn.w r3, #3 801252c: 617b str r3, [r7, #20] 801252e: e010 b.n 8012552 } else { if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) { 8012530: 2300 movs r3, #0 8012532: 9300 str r3, [sp, #0] 8012534: 2300 movs r3, #0 8012536: 683a ldr r2, [r7, #0] 8012538: 2104 movs r1, #4 801253a: 6938 ldr r0, [r7, #16] 801253c: f003 f858 bl 80155f0 8012540: 4603 mov r3, r0 8012542: 2b01 cmp r3, #1 8012544: d102 bne.n 801254c stat = osOK; 8012546: 2300 movs r3, #0 8012548: 617b str r3, [r7, #20] 801254a: e002 b.n 8012552 } else { stat = osErrorResource; 801254c: f06f 0302 mvn.w r3, #2 8012550: 617b str r3, [r7, #20] } } return (stat); 8012552: 697b ldr r3, [r7, #20] } 8012554: 4618 mov r0, r3 8012556: 3718 adds r7, #24 8012558: 46bd mov sp, r7 801255a: bd80 pop {r7, pc} 0801255c : osStatus_t osTimerStop (osTimerId_t timer_id) { 801255c: b580 push {r7, lr} 801255e: b088 sub sp, #32 8012560: af02 add r7, sp, #8 8012562: 6078 str r0, [r7, #4] TimerHandle_t hTimer = (TimerHandle_t)timer_id; 8012564: 687b ldr r3, [r7, #4] 8012566: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8012568: f3ef 8305 mrs r3, IPSR 801256c: 60fb str r3, [r7, #12] return(result); 801256e: 68fb ldr r3, [r7, #12] osStatus_t stat; if (IS_IRQ()) { 8012570: 2b00 cmp r3, #0 8012572: d003 beq.n 801257c stat = osErrorISR; 8012574: f06f 0305 mvn.w r3, #5 8012578: 617b str r3, [r7, #20] 801257a: e021 b.n 80125c0 } else if (hTimer == NULL) { 801257c: 693b ldr r3, [r7, #16] 801257e: 2b00 cmp r3, #0 8012580: d103 bne.n 801258a stat = osErrorParameter; 8012582: f06f 0303 mvn.w r3, #3 8012586: 617b str r3, [r7, #20] 8012588: e01a b.n 80125c0 } else { if (xTimerIsTimerActive (hTimer) == pdFALSE) { 801258a: 6938 ldr r0, [r7, #16] 801258c: f003 fb40 bl 8015c10 8012590: 4603 mov r3, r0 8012592: 2b00 cmp r3, #0 8012594: d103 bne.n 801259e stat = osErrorResource; 8012596: f06f 0302 mvn.w r3, #2 801259a: 617b str r3, [r7, #20] 801259c: e010 b.n 80125c0 } else { if (xTimerStop (hTimer, 0) == pdPASS) { 801259e: 2300 movs r3, #0 80125a0: 9300 str r3, [sp, #0] 80125a2: 2300 movs r3, #0 80125a4: 2200 movs r2, #0 80125a6: 2103 movs r1, #3 80125a8: 6938 ldr r0, [r7, #16] 80125aa: f003 f821 bl 80155f0 80125ae: 4603 mov r3, r0 80125b0: 2b01 cmp r3, #1 80125b2: d102 bne.n 80125ba stat = osOK; 80125b4: 2300 movs r3, #0 80125b6: 617b str r3, [r7, #20] 80125b8: e002 b.n 80125c0 } else { stat = osError; 80125ba: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80125be: 617b str r3, [r7, #20] } } } return (stat); 80125c0: 697b ldr r3, [r7, #20] } 80125c2: 4618 mov r0, r3 80125c4: 3718 adds r7, #24 80125c6: 46bd mov sp, r7 80125c8: bd80 pop {r7, pc} 080125ca : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_MUTEX == 1) osMutexId_t osMutexNew (const osMutexAttr_t *attr) { 80125ca: b580 push {r7, lr} 80125cc: b088 sub sp, #32 80125ce: af00 add r7, sp, #0 80125d0: 6078 str r0, [r7, #4] int32_t mem; #if (configQUEUE_REGISTRY_SIZE > 0) const char *name; #endif hMutex = NULL; 80125d2: 2300 movs r3, #0 80125d4: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80125d6: f3ef 8305 mrs r3, IPSR 80125da: 60bb str r3, [r7, #8] return(result); 80125dc: 68bb ldr r3, [r7, #8] if (!IS_IRQ()) { 80125de: 2b00 cmp r3, #0 80125e0: d174 bne.n 80126cc if (attr != NULL) { 80125e2: 687b ldr r3, [r7, #4] 80125e4: 2b00 cmp r3, #0 80125e6: d003 beq.n 80125f0 type = attr->attr_bits; 80125e8: 687b ldr r3, [r7, #4] 80125ea: 685b ldr r3, [r3, #4] 80125ec: 61bb str r3, [r7, #24] 80125ee: e001 b.n 80125f4 } else { type = 0U; 80125f0: 2300 movs r3, #0 80125f2: 61bb str r3, [r7, #24] } if ((type & osMutexRecursive) == osMutexRecursive) { 80125f4: 69bb ldr r3, [r7, #24] 80125f6: f003 0301 and.w r3, r3, #1 80125fa: 2b00 cmp r3, #0 80125fc: d002 beq.n 8012604 rmtx = 1U; 80125fe: 2301 movs r3, #1 8012600: 617b str r3, [r7, #20] 8012602: e001 b.n 8012608 } else { rmtx = 0U; 8012604: 2300 movs r3, #0 8012606: 617b str r3, [r7, #20] } if ((type & osMutexRobust) != osMutexRobust) { 8012608: 69bb ldr r3, [r7, #24] 801260a: f003 0308 and.w r3, r3, #8 801260e: 2b00 cmp r3, #0 8012610: d15c bne.n 80126cc mem = -1; 8012612: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8012616: 613b str r3, [r7, #16] if (attr != NULL) { 8012618: 687b ldr r3, [r7, #4] 801261a: 2b00 cmp r3, #0 801261c: d015 beq.n 801264a if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { 801261e: 687b ldr r3, [r7, #4] 8012620: 689b ldr r3, [r3, #8] 8012622: 2b00 cmp r3, #0 8012624: d006 beq.n 8012634 8012626: 687b ldr r3, [r7, #4] 8012628: 68db ldr r3, [r3, #12] 801262a: 2b4f cmp r3, #79 @ 0x4f 801262c: d902 bls.n 8012634 mem = 1; 801262e: 2301 movs r3, #1 8012630: 613b str r3, [r7, #16] 8012632: e00c b.n 801264e } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 8012634: 687b ldr r3, [r7, #4] 8012636: 689b ldr r3, [r3, #8] 8012638: 2b00 cmp r3, #0 801263a: d108 bne.n 801264e 801263c: 687b ldr r3, [r7, #4] 801263e: 68db ldr r3, [r3, #12] 8012640: 2b00 cmp r3, #0 8012642: d104 bne.n 801264e mem = 0; 8012644: 2300 movs r3, #0 8012646: 613b str r3, [r7, #16] 8012648: e001 b.n 801264e } } } else { mem = 0; 801264a: 2300 movs r3, #0 801264c: 613b str r3, [r7, #16] } if (mem == 1) { 801264e: 693b ldr r3, [r7, #16] 8012650: 2b01 cmp r3, #1 8012652: d112 bne.n 801267a #if (configSUPPORT_STATIC_ALLOCATION == 1) if (rmtx != 0U) { 8012654: 697b ldr r3, [r7, #20] 8012656: 2b00 cmp r3, #0 8012658: d007 beq.n 801266a #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem); 801265a: 687b ldr r3, [r7, #4] 801265c: 689b ldr r3, [r3, #8] 801265e: 4619 mov r1, r3 8012660: 2004 movs r0, #4 8012662: f000 fc50 bl 8012f06 8012666: 61f8 str r0, [r7, #28] 8012668: e016 b.n 8012698 #endif } else { hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem); 801266a: 687b ldr r3, [r7, #4] 801266c: 689b ldr r3, [r3, #8] 801266e: 4619 mov r1, r3 8012670: 2001 movs r0, #1 8012672: f000 fc48 bl 8012f06 8012676: 61f8 str r0, [r7, #28] 8012678: e00e b.n 8012698 } #endif } else { if (mem == 0) { 801267a: 693b ldr r3, [r7, #16] 801267c: 2b00 cmp r3, #0 801267e: d10b bne.n 8012698 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (rmtx != 0U) { 8012680: 697b ldr r3, [r7, #20] 8012682: 2b00 cmp r3, #0 8012684: d004 beq.n 8012690 #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutex (); 8012686: 2004 movs r0, #4 8012688: f000 fc25 bl 8012ed6 801268c: 61f8 str r0, [r7, #28] 801268e: e003 b.n 8012698 #endif } else { hMutex = xSemaphoreCreateMutex (); 8012690: 2001 movs r0, #1 8012692: f000 fc20 bl 8012ed6 8012696: 61f8 str r0, [r7, #28] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hMutex != NULL) { 8012698: 69fb ldr r3, [r7, #28] 801269a: 2b00 cmp r3, #0 801269c: d00c beq.n 80126b8 if (attr != NULL) { 801269e: 687b ldr r3, [r7, #4] 80126a0: 2b00 cmp r3, #0 80126a2: d003 beq.n 80126ac name = attr->name; 80126a4: 687b ldr r3, [r7, #4] 80126a6: 681b ldr r3, [r3, #0] 80126a8: 60fb str r3, [r7, #12] 80126aa: e001 b.n 80126b0 } else { name = NULL; 80126ac: 2300 movs r3, #0 80126ae: 60fb str r3, [r7, #12] } vQueueAddToRegistry (hMutex, name); 80126b0: 68f9 ldr r1, [r7, #12] 80126b2: 69f8 ldr r0, [r7, #28] 80126b4: f001 f9ea bl 8013a8c } #endif if ((hMutex != NULL) && (rmtx != 0U)) { 80126b8: 69fb ldr r3, [r7, #28] 80126ba: 2b00 cmp r3, #0 80126bc: d006 beq.n 80126cc 80126be: 697b ldr r3, [r7, #20] 80126c0: 2b00 cmp r3, #0 80126c2: d003 beq.n 80126cc hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U); 80126c4: 69fb ldr r3, [r7, #28] 80126c6: f043 0301 orr.w r3, r3, #1 80126ca: 61fb str r3, [r7, #28] } } } return ((osMutexId_t)hMutex); 80126cc: 69fb ldr r3, [r7, #28] } 80126ce: 4618 mov r0, r3 80126d0: 3720 adds r7, #32 80126d2: 46bd mov sp, r7 80126d4: bd80 pop {r7, pc} 080126d6 : osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { 80126d6: b580 push {r7, lr} 80126d8: b086 sub sp, #24 80126da: af00 add r7, sp, #0 80126dc: 6078 str r0, [r7, #4] 80126de: 6039 str r1, [r7, #0] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 80126e0: 687b ldr r3, [r7, #4] 80126e2: f023 0301 bic.w r3, r3, #1 80126e6: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 80126e8: 687b ldr r3, [r7, #4] 80126ea: f003 0301 and.w r3, r3, #1 80126ee: 60fb str r3, [r7, #12] stat = osOK; 80126f0: 2300 movs r3, #0 80126f2: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80126f4: f3ef 8305 mrs r3, IPSR 80126f8: 60bb str r3, [r7, #8] return(result); 80126fa: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 80126fc: 2b00 cmp r3, #0 80126fe: d003 beq.n 8012708 stat = osErrorISR; 8012700: f06f 0305 mvn.w r3, #5 8012704: 617b str r3, [r7, #20] 8012706: e02c b.n 8012762 } else if (hMutex == NULL) { 8012708: 693b ldr r3, [r7, #16] 801270a: 2b00 cmp r3, #0 801270c: d103 bne.n 8012716 stat = osErrorParameter; 801270e: f06f 0303 mvn.w r3, #3 8012712: 617b str r3, [r7, #20] 8012714: e025 b.n 8012762 } else { if (rmtx != 0U) { 8012716: 68fb ldr r3, [r7, #12] 8012718: 2b00 cmp r3, #0 801271a: d011 beq.n 8012740 #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) { 801271c: 6839 ldr r1, [r7, #0] 801271e: 6938 ldr r0, [r7, #16] 8012720: f000 fc41 bl 8012fa6 8012724: 4603 mov r3, r0 8012726: 2b01 cmp r3, #1 8012728: d01b beq.n 8012762 if (timeout != 0U) { 801272a: 683b ldr r3, [r7, #0] 801272c: 2b00 cmp r3, #0 801272e: d003 beq.n 8012738 stat = osErrorTimeout; 8012730: f06f 0301 mvn.w r3, #1 8012734: 617b str r3, [r7, #20] 8012736: e014 b.n 8012762 } else { stat = osErrorResource; 8012738: f06f 0302 mvn.w r3, #2 801273c: 617b str r3, [r7, #20] 801273e: e010 b.n 8012762 } } #endif } else { if (xSemaphoreTake (hMutex, timeout) != pdPASS) { 8012740: 6839 ldr r1, [r7, #0] 8012742: 6938 ldr r0, [r7, #16] 8012744: f000 fee8 bl 8013518 8012748: 4603 mov r3, r0 801274a: 2b01 cmp r3, #1 801274c: d009 beq.n 8012762 if (timeout != 0U) { 801274e: 683b ldr r3, [r7, #0] 8012750: 2b00 cmp r3, #0 8012752: d003 beq.n 801275c stat = osErrorTimeout; 8012754: f06f 0301 mvn.w r3, #1 8012758: 617b str r3, [r7, #20] 801275a: e002 b.n 8012762 } else { stat = osErrorResource; 801275c: f06f 0302 mvn.w r3, #2 8012760: 617b str r3, [r7, #20] } } } } return (stat); 8012762: 697b ldr r3, [r7, #20] } 8012764: 4618 mov r0, r3 8012766: 3718 adds r7, #24 8012768: 46bd mov sp, r7 801276a: bd80 pop {r7, pc} 0801276c : osStatus_t osMutexRelease (osMutexId_t mutex_id) { 801276c: b580 push {r7, lr} 801276e: b086 sub sp, #24 8012770: af00 add r7, sp, #0 8012772: 6078 str r0, [r7, #4] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 8012774: 687b ldr r3, [r7, #4] 8012776: f023 0301 bic.w r3, r3, #1 801277a: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 801277c: 687b ldr r3, [r7, #4] 801277e: f003 0301 and.w r3, r3, #1 8012782: 60fb str r3, [r7, #12] stat = osOK; 8012784: 2300 movs r3, #0 8012786: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8012788: f3ef 8305 mrs r3, IPSR 801278c: 60bb str r3, [r7, #8] return(result); 801278e: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 8012790: 2b00 cmp r3, #0 8012792: d003 beq.n 801279c stat = osErrorISR; 8012794: f06f 0305 mvn.w r3, #5 8012798: 617b str r3, [r7, #20] 801279a: e01f b.n 80127dc } else if (hMutex == NULL) { 801279c: 693b ldr r3, [r7, #16] 801279e: 2b00 cmp r3, #0 80127a0: d103 bne.n 80127aa stat = osErrorParameter; 80127a2: f06f 0303 mvn.w r3, #3 80127a6: 617b str r3, [r7, #20] 80127a8: e018 b.n 80127dc } else { if (rmtx != 0U) { 80127aa: 68fb ldr r3, [r7, #12] 80127ac: 2b00 cmp r3, #0 80127ae: d009 beq.n 80127c4 #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreGiveRecursive (hMutex) != pdPASS) { 80127b0: 6938 ldr r0, [r7, #16] 80127b2: f000 fbc3 bl 8012f3c 80127b6: 4603 mov r3, r0 80127b8: 2b01 cmp r3, #1 80127ba: d00f beq.n 80127dc stat = osErrorResource; 80127bc: f06f 0302 mvn.w r3, #2 80127c0: 617b str r3, [r7, #20] 80127c2: e00b b.n 80127dc } #endif } else { if (xSemaphoreGive (hMutex) != pdPASS) { 80127c4: 2300 movs r3, #0 80127c6: 2200 movs r2, #0 80127c8: 2100 movs r1, #0 80127ca: 6938 ldr r0, [r7, #16] 80127cc: f000 fc22 bl 8013014 80127d0: 4603 mov r3, r0 80127d2: 2b01 cmp r3, #1 80127d4: d002 beq.n 80127dc stat = osErrorResource; 80127d6: f06f 0302 mvn.w r3, #2 80127da: 617b str r3, [r7, #20] } } } return (stat); 80127dc: 697b ldr r3, [r7, #20] } 80127de: 4618 mov r0, r3 80127e0: 3718 adds r7, #24 80127e2: 46bd mov sp, r7 80127e4: bd80 pop {r7, pc} 080127e6 : return (stat); } /*---------------------------------------------------------------------------*/ osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { 80127e6: b580 push {r7, lr} 80127e8: b08a sub sp, #40 @ 0x28 80127ea: af02 add r7, sp, #8 80127ec: 60f8 str r0, [r7, #12] 80127ee: 60b9 str r1, [r7, #8] 80127f0: 607a str r2, [r7, #4] int32_t mem; #if (configQUEUE_REGISTRY_SIZE > 0) const char *name; #endif hQueue = NULL; 80127f2: 2300 movs r3, #0 80127f4: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80127f6: f3ef 8305 mrs r3, IPSR 80127fa: 613b str r3, [r7, #16] return(result); 80127fc: 693b ldr r3, [r7, #16] if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) { 80127fe: 2b00 cmp r3, #0 8012800: d15f bne.n 80128c2 8012802: 68fb ldr r3, [r7, #12] 8012804: 2b00 cmp r3, #0 8012806: d05c beq.n 80128c2 8012808: 68bb ldr r3, [r7, #8] 801280a: 2b00 cmp r3, #0 801280c: d059 beq.n 80128c2 mem = -1; 801280e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8012812: 61bb str r3, [r7, #24] if (attr != NULL) { 8012814: 687b ldr r3, [r7, #4] 8012816: 2b00 cmp r3, #0 8012818: d029 beq.n 801286e if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 801281a: 687b ldr r3, [r7, #4] 801281c: 689b ldr r3, [r3, #8] 801281e: 2b00 cmp r3, #0 8012820: d012 beq.n 8012848 8012822: 687b ldr r3, [r7, #4] 8012824: 68db ldr r3, [r3, #12] 8012826: 2b4f cmp r3, #79 @ 0x4f 8012828: d90e bls.n 8012848 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 801282a: 687b ldr r3, [r7, #4] 801282c: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 801282e: 2b00 cmp r3, #0 8012830: d00a beq.n 8012848 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 8012832: 687b ldr r3, [r7, #4] 8012834: 695a ldr r2, [r3, #20] 8012836: 68fb ldr r3, [r7, #12] 8012838: 68b9 ldr r1, [r7, #8] 801283a: fb01 f303 mul.w r3, r1, r3 801283e: 429a cmp r2, r3 8012840: d302 bcc.n 8012848 mem = 1; 8012842: 2301 movs r3, #1 8012844: 61bb str r3, [r7, #24] 8012846: e014 b.n 8012872 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 8012848: 687b ldr r3, [r7, #4] 801284a: 689b ldr r3, [r3, #8] 801284c: 2b00 cmp r3, #0 801284e: d110 bne.n 8012872 8012850: 687b ldr r3, [r7, #4] 8012852: 68db ldr r3, [r3, #12] 8012854: 2b00 cmp r3, #0 8012856: d10c bne.n 8012872 (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 8012858: 687b ldr r3, [r7, #4] 801285a: 691b ldr r3, [r3, #16] if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 801285c: 2b00 cmp r3, #0 801285e: d108 bne.n 8012872 (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 8012860: 687b ldr r3, [r7, #4] 8012862: 695b ldr r3, [r3, #20] 8012864: 2b00 cmp r3, #0 8012866: d104 bne.n 8012872 mem = 0; 8012868: 2300 movs r3, #0 801286a: 61bb str r3, [r7, #24] 801286c: e001 b.n 8012872 } } } else { mem = 0; 801286e: 2300 movs r3, #0 8012870: 61bb str r3, [r7, #24] } if (mem == 1) { 8012872: 69bb ldr r3, [r7, #24] 8012874: 2b01 cmp r3, #1 8012876: d10b bne.n 8012890 #if (configSUPPORT_STATIC_ALLOCATION == 1) hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem); 8012878: 687b ldr r3, [r7, #4] 801287a: 691a ldr r2, [r3, #16] 801287c: 687b ldr r3, [r7, #4] 801287e: 689b ldr r3, [r3, #8] 8012880: 2100 movs r1, #0 8012882: 9100 str r1, [sp, #0] 8012884: 68b9 ldr r1, [r7, #8] 8012886: 68f8 ldr r0, [r7, #12] 8012888: f000 fa30 bl 8012cec 801288c: 61f8 str r0, [r7, #28] 801288e: e008 b.n 80128a2 #endif } else { if (mem == 0) { 8012890: 69bb ldr r3, [r7, #24] 8012892: 2b00 cmp r3, #0 8012894: d105 bne.n 80128a2 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hQueue = xQueueCreate (msg_count, msg_size); 8012896: 2200 movs r2, #0 8012898: 68b9 ldr r1, [r7, #8] 801289a: 68f8 ldr r0, [r7, #12] 801289c: f000 faa3 bl 8012de6 80128a0: 61f8 str r0, [r7, #28] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hQueue != NULL) { 80128a2: 69fb ldr r3, [r7, #28] 80128a4: 2b00 cmp r3, #0 80128a6: d00c beq.n 80128c2 if (attr != NULL) { 80128a8: 687b ldr r3, [r7, #4] 80128aa: 2b00 cmp r3, #0 80128ac: d003 beq.n 80128b6 name = attr->name; 80128ae: 687b ldr r3, [r7, #4] 80128b0: 681b ldr r3, [r3, #0] 80128b2: 617b str r3, [r7, #20] 80128b4: e001 b.n 80128ba } else { name = NULL; 80128b6: 2300 movs r3, #0 80128b8: 617b str r3, [r7, #20] } vQueueAddToRegistry (hQueue, name); 80128ba: 6979 ldr r1, [r7, #20] 80128bc: 69f8 ldr r0, [r7, #28] 80128be: f001 f8e5 bl 8013a8c } #endif } return ((osMessageQueueId_t)hQueue); 80128c2: 69fb ldr r3, [r7, #28] } 80128c4: 4618 mov r0, r3 80128c6: 3720 adds r7, #32 80128c8: 46bd mov sp, r7 80128ca: bd80 pop {r7, pc} 080128cc : osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { 80128cc: b580 push {r7, lr} 80128ce: b088 sub sp, #32 80128d0: af00 add r7, sp, #0 80128d2: 60f8 str r0, [r7, #12] 80128d4: 60b9 str r1, [r7, #8] 80128d6: 603b str r3, [r7, #0] 80128d8: 4613 mov r3, r2 80128da: 71fb strb r3, [r7, #7] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 80128dc: 68fb ldr r3, [r7, #12] 80128de: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 80128e0: 2300 movs r3, #0 80128e2: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80128e4: f3ef 8305 mrs r3, IPSR 80128e8: 617b str r3, [r7, #20] return(result); 80128ea: 697b ldr r3, [r7, #20] if (IS_IRQ()) { 80128ec: 2b00 cmp r3, #0 80128ee: d028 beq.n 8012942 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 80128f0: 69bb ldr r3, [r7, #24] 80128f2: 2b00 cmp r3, #0 80128f4: d005 beq.n 8012902 80128f6: 68bb ldr r3, [r7, #8] 80128f8: 2b00 cmp r3, #0 80128fa: d002 beq.n 8012902 80128fc: 683b ldr r3, [r7, #0] 80128fe: 2b00 cmp r3, #0 8012900: d003 beq.n 801290a stat = osErrorParameter; 8012902: f06f 0303 mvn.w r3, #3 8012906: 61fb str r3, [r7, #28] 8012908: e038 b.n 801297c } else { yield = pdFALSE; 801290a: 2300 movs r3, #0 801290c: 613b str r3, [r7, #16] if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { 801290e: f107 0210 add.w r2, r7, #16 8012912: 2300 movs r3, #0 8012914: 68b9 ldr r1, [r7, #8] 8012916: 69b8 ldr r0, [r7, #24] 8012918: f000 fc7e bl 8013218 801291c: 4603 mov r3, r0 801291e: 2b01 cmp r3, #1 8012920: d003 beq.n 801292a stat = osErrorResource; 8012922: f06f 0302 mvn.w r3, #2 8012926: 61fb str r3, [r7, #28] 8012928: e028 b.n 801297c } else { portYIELD_FROM_ISR (yield); 801292a: 693b ldr r3, [r7, #16] 801292c: 2b00 cmp r3, #0 801292e: d025 beq.n 801297c 8012930: 4b15 ldr r3, [pc, #84] @ (8012988 ) 8012932: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8012936: 601a str r2, [r3, #0] 8012938: f3bf 8f4f dsb sy 801293c: f3bf 8f6f isb sy 8012940: e01c b.n 801297c } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 8012942: 69bb ldr r3, [r7, #24] 8012944: 2b00 cmp r3, #0 8012946: d002 beq.n 801294e 8012948: 68bb ldr r3, [r7, #8] 801294a: 2b00 cmp r3, #0 801294c: d103 bne.n 8012956 stat = osErrorParameter; 801294e: f06f 0303 mvn.w r3, #3 8012952: 61fb str r3, [r7, #28] 8012954: e012 b.n 801297c } else { if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 8012956: 2300 movs r3, #0 8012958: 683a ldr r2, [r7, #0] 801295a: 68b9 ldr r1, [r7, #8] 801295c: 69b8 ldr r0, [r7, #24] 801295e: f000 fb59 bl 8013014 8012962: 4603 mov r3, r0 8012964: 2b01 cmp r3, #1 8012966: d009 beq.n 801297c if (timeout != 0U) { 8012968: 683b ldr r3, [r7, #0] 801296a: 2b00 cmp r3, #0 801296c: d003 beq.n 8012976 stat = osErrorTimeout; 801296e: f06f 0301 mvn.w r3, #1 8012972: 61fb str r3, [r7, #28] 8012974: e002 b.n 801297c } else { stat = osErrorResource; 8012976: f06f 0302 mvn.w r3, #2 801297a: 61fb str r3, [r7, #28] } } } } return (stat); 801297c: 69fb ldr r3, [r7, #28] } 801297e: 4618 mov r0, r3 8012980: 3720 adds r7, #32 8012982: 46bd mov sp, r7 8012984: bd80 pop {r7, pc} 8012986: bf00 nop 8012988: e000ed04 .word 0xe000ed04 0801298c : osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { 801298c: b580 push {r7, lr} 801298e: b088 sub sp, #32 8012990: af00 add r7, sp, #0 8012992: 60f8 str r0, [r7, #12] 8012994: 60b9 str r1, [r7, #8] 8012996: 607a str r2, [r7, #4] 8012998: 603b str r3, [r7, #0] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 801299a: 68fb ldr r3, [r7, #12] 801299c: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 801299e: 2300 movs r3, #0 80129a0: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80129a2: f3ef 8305 mrs r3, IPSR 80129a6: 617b str r3, [r7, #20] return(result); 80129a8: 697b ldr r3, [r7, #20] if (IS_IRQ()) { 80129aa: 2b00 cmp r3, #0 80129ac: d028 beq.n 8012a00 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 80129ae: 69bb ldr r3, [r7, #24] 80129b0: 2b00 cmp r3, #0 80129b2: d005 beq.n 80129c0 80129b4: 68bb ldr r3, [r7, #8] 80129b6: 2b00 cmp r3, #0 80129b8: d002 beq.n 80129c0 80129ba: 683b ldr r3, [r7, #0] 80129bc: 2b00 cmp r3, #0 80129be: d003 beq.n 80129c8 stat = osErrorParameter; 80129c0: f06f 0303 mvn.w r3, #3 80129c4: 61fb str r3, [r7, #28] 80129c6: e037 b.n 8012a38 } else { yield = pdFALSE; 80129c8: 2300 movs r3, #0 80129ca: 613b str r3, [r7, #16] if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) { 80129cc: f107 0310 add.w r3, r7, #16 80129d0: 461a mov r2, r3 80129d2: 68b9 ldr r1, [r7, #8] 80129d4: 69b8 ldr r0, [r7, #24] 80129d6: f000 feaf bl 8013738 80129da: 4603 mov r3, r0 80129dc: 2b01 cmp r3, #1 80129de: d003 beq.n 80129e8 stat = osErrorResource; 80129e0: f06f 0302 mvn.w r3, #2 80129e4: 61fb str r3, [r7, #28] 80129e6: e027 b.n 8012a38 } else { portYIELD_FROM_ISR (yield); 80129e8: 693b ldr r3, [r7, #16] 80129ea: 2b00 cmp r3, #0 80129ec: d024 beq.n 8012a38 80129ee: 4b15 ldr r3, [pc, #84] @ (8012a44 ) 80129f0: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80129f4: 601a str r2, [r3, #0] 80129f6: f3bf 8f4f dsb sy 80129fa: f3bf 8f6f isb sy 80129fe: e01b b.n 8012a38 } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 8012a00: 69bb ldr r3, [r7, #24] 8012a02: 2b00 cmp r3, #0 8012a04: d002 beq.n 8012a0c 8012a06: 68bb ldr r3, [r7, #8] 8012a08: 2b00 cmp r3, #0 8012a0a: d103 bne.n 8012a14 stat = osErrorParameter; 8012a0c: f06f 0303 mvn.w r3, #3 8012a10: 61fb str r3, [r7, #28] 8012a12: e011 b.n 8012a38 } else { if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 8012a14: 683a ldr r2, [r7, #0] 8012a16: 68b9 ldr r1, [r7, #8] 8012a18: 69b8 ldr r0, [r7, #24] 8012a1a: f000 fc9b bl 8013354 8012a1e: 4603 mov r3, r0 8012a20: 2b01 cmp r3, #1 8012a22: d009 beq.n 8012a38 if (timeout != 0U) { 8012a24: 683b ldr r3, [r7, #0] 8012a26: 2b00 cmp r3, #0 8012a28: d003 beq.n 8012a32 stat = osErrorTimeout; 8012a2a: f06f 0301 mvn.w r3, #1 8012a2e: 61fb str r3, [r7, #28] 8012a30: e002 b.n 8012a38 } else { stat = osErrorResource; 8012a32: f06f 0302 mvn.w r3, #2 8012a36: 61fb str r3, [r7, #28] } } } } return (stat); 8012a38: 69fb ldr r3, [r7, #28] } 8012a3a: 4618 mov r0, r3 8012a3c: 3720 adds r7, #32 8012a3e: 46bd mov sp, r7 8012a40: bd80 pop {r7, pc} 8012a42: bf00 nop 8012a44: e000ed04 .word 0xe000ed04 08012a48 : /* vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { 8012a48: b480 push {r7} 8012a4a: b085 sub sp, #20 8012a4c: af00 add r7, sp, #0 8012a4e: 60f8 str r0, [r7, #12] 8012a50: 60b9 str r1, [r7, #8] 8012a52: 607a str r2, [r7, #4] /* Idle task control block and stack */ static StaticTask_t Idle_TCB; static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; *ppxIdleTaskTCBBuffer = &Idle_TCB; 8012a54: 68fb ldr r3, [r7, #12] 8012a56: 4a07 ldr r2, [pc, #28] @ (8012a74 ) 8012a58: 601a str r2, [r3, #0] *ppxIdleTaskStackBuffer = &Idle_Stack[0]; 8012a5a: 68bb ldr r3, [r7, #8] 8012a5c: 4a06 ldr r2, [pc, #24] @ (8012a78 ) 8012a5e: 601a str r2, [r3, #0] *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; 8012a60: 687b ldr r3, [r7, #4] 8012a62: f44f 7200 mov.w r2, #512 @ 0x200 8012a66: 601a str r2, [r3, #0] } 8012a68: bf00 nop 8012a6a: 3714 adds r7, #20 8012a6c: 46bd mov sp, r7 8012a6e: f85d 7b04 ldr.w r7, [sp], #4 8012a72: 4770 bx lr 8012a74: 24000c14 .word 0x24000c14 8012a78: 24000cbc .word 0x24000cbc 08012a7c : /* vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { 8012a7c: b480 push {r7} 8012a7e: b085 sub sp, #20 8012a80: af00 add r7, sp, #0 8012a82: 60f8 str r0, [r7, #12] 8012a84: 60b9 str r1, [r7, #8] 8012a86: 607a str r2, [r7, #4] /* Timer task control block and stack */ static StaticTask_t Timer_TCB; static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; *ppxTimerTaskTCBBuffer = &Timer_TCB; 8012a88: 68fb ldr r3, [r7, #12] 8012a8a: 4a07 ldr r2, [pc, #28] @ (8012aa8 ) 8012a8c: 601a str r2, [r3, #0] *ppxTimerTaskStackBuffer = &Timer_Stack[0]; 8012a8e: 68bb ldr r3, [r7, #8] 8012a90: 4a06 ldr r2, [pc, #24] @ (8012aac ) 8012a92: 601a str r2, [r3, #0] *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; 8012a94: 687b ldr r3, [r7, #4] 8012a96: f44f 6280 mov.w r2, #1024 @ 0x400 8012a9a: 601a str r2, [r3, #0] } 8012a9c: bf00 nop 8012a9e: 3714 adds r7, #20 8012aa0: 46bd mov sp, r7 8012aa2: f85d 7b04 ldr.w r7, [sp], #4 8012aa6: 4770 bx lr 8012aa8: 240014bc .word 0x240014bc 8012aac: 24001564 .word 0x24001564 08012ab0 : /*----------------------------------------------------------- * PUBLIC LIST API documented in list.h *----------------------------------------------------------*/ void vListInitialise( List_t * const pxList ) { 8012ab0: b480 push {r7} 8012ab2: b083 sub sp, #12 8012ab4: af00 add r7, sp, #0 8012ab6: 6078 str r0, [r7, #4] /* The list structure contains a list item which is used to mark the end of the list. To initialise the list the list end is inserted as the only list entry. */ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8012ab8: 687b ldr r3, [r7, #4] 8012aba: f103 0208 add.w r2, r3, #8 8012abe: 687b ldr r3, [r7, #4] 8012ac0: 605a str r2, [r3, #4] /* The list end value is the highest possible value in the list to ensure it remains at the end of the list. */ pxList->xListEnd.xItemValue = portMAX_DELAY; 8012ac2: 687b ldr r3, [r7, #4] 8012ac4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8012ac8: 609a str r2, [r3, #8] /* The list end next and previous pointers point to itself so we know when the list is empty. */ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8012aca: 687b ldr r3, [r7, #4] 8012acc: f103 0208 add.w r2, r3, #8 8012ad0: 687b ldr r3, [r7, #4] 8012ad2: 60da str r2, [r3, #12] pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8012ad4: 687b ldr r3, [r7, #4] 8012ad6: f103 0208 add.w r2, r3, #8 8012ada: 687b ldr r3, [r7, #4] 8012adc: 611a str r2, [r3, #16] pxList->uxNumberOfItems = ( UBaseType_t ) 0U; 8012ade: 687b ldr r3, [r7, #4] 8012ae0: 2200 movs r2, #0 8012ae2: 601a str r2, [r3, #0] /* Write known values into the list if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); } 8012ae4: bf00 nop 8012ae6: 370c adds r7, #12 8012ae8: 46bd mov sp, r7 8012aea: f85d 7b04 ldr.w r7, [sp], #4 8012aee: 4770 bx lr 08012af0 : /*-----------------------------------------------------------*/ void vListInitialiseItem( ListItem_t * const pxItem ) { 8012af0: b480 push {r7} 8012af2: b083 sub sp, #12 8012af4: af00 add r7, sp, #0 8012af6: 6078 str r0, [r7, #4] /* Make sure the list item is not recorded as being on a list. */ pxItem->pxContainer = NULL; 8012af8: 687b ldr r3, [r7, #4] 8012afa: 2200 movs r2, #0 8012afc: 611a str r2, [r3, #16] /* Write known values into the list item if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } 8012afe: bf00 nop 8012b00: 370c adds r7, #12 8012b02: 46bd mov sp, r7 8012b04: f85d 7b04 ldr.w r7, [sp], #4 8012b08: 4770 bx lr 08012b0a : /*-----------------------------------------------------------*/ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8012b0a: b480 push {r7} 8012b0c: b085 sub sp, #20 8012b0e: af00 add r7, sp, #0 8012b10: 6078 str r0, [r7, #4] 8012b12: 6039 str r1, [r7, #0] ListItem_t * const pxIndex = pxList->pxIndex; 8012b14: 687b ldr r3, [r7, #4] 8012b16: 685b ldr r3, [r3, #4] 8012b18: 60fb str r3, [r7, #12] listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); /* Insert a new list item into pxList, but rather than sort the list, makes the new list item the last item to be removed by a call to listGET_OWNER_OF_NEXT_ENTRY(). */ pxNewListItem->pxNext = pxIndex; 8012b1a: 683b ldr r3, [r7, #0] 8012b1c: 68fa ldr r2, [r7, #12] 8012b1e: 605a str r2, [r3, #4] pxNewListItem->pxPrevious = pxIndex->pxPrevious; 8012b20: 68fb ldr r3, [r7, #12] 8012b22: 689a ldr r2, [r3, #8] 8012b24: 683b ldr r3, [r7, #0] 8012b26: 609a str r2, [r3, #8] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); pxIndex->pxPrevious->pxNext = pxNewListItem; 8012b28: 68fb ldr r3, [r7, #12] 8012b2a: 689b ldr r3, [r3, #8] 8012b2c: 683a ldr r2, [r7, #0] 8012b2e: 605a str r2, [r3, #4] pxIndex->pxPrevious = pxNewListItem; 8012b30: 68fb ldr r3, [r7, #12] 8012b32: 683a ldr r2, [r7, #0] 8012b34: 609a str r2, [r3, #8] /* Remember which list the item is in. */ pxNewListItem->pxContainer = pxList; 8012b36: 683b ldr r3, [r7, #0] 8012b38: 687a ldr r2, [r7, #4] 8012b3a: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8012b3c: 687b ldr r3, [r7, #4] 8012b3e: 681b ldr r3, [r3, #0] 8012b40: 1c5a adds r2, r3, #1 8012b42: 687b ldr r3, [r7, #4] 8012b44: 601a str r2, [r3, #0] } 8012b46: bf00 nop 8012b48: 3714 adds r7, #20 8012b4a: 46bd mov sp, r7 8012b4c: f85d 7b04 ldr.w r7, [sp], #4 8012b50: 4770 bx lr 08012b52 : /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8012b52: b480 push {r7} 8012b54: b085 sub sp, #20 8012b56: af00 add r7, sp, #0 8012b58: 6078 str r0, [r7, #4] 8012b5a: 6039 str r1, [r7, #0] ListItem_t *pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; 8012b5c: 683b ldr r3, [r7, #0] 8012b5e: 681b ldr r3, [r3, #0] 8012b60: 60bb str r3, [r7, #8] new list item should be placed after it. This ensures that TCBs which are stored in ready lists (all of which have the same xItemValue value) get a share of the CPU. However, if the xItemValue is the same as the back marker the iteration loop below will not end. Therefore the value is checked first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) 8012b62: 68bb ldr r3, [r7, #8] 8012b64: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8012b68: d103 bne.n 8012b72 { pxIterator = pxList->xListEnd.pxPrevious; 8012b6a: 687b ldr r3, [r7, #4] 8012b6c: 691b ldr r3, [r3, #16] 8012b6e: 60fb str r3, [r7, #12] 8012b70: e00c b.n 8012b8c 4) Using a queue or semaphore before it has been initialised or before the scheduler has been started (are interrupts firing before vTaskStartScheduler() has been called?). **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ 8012b72: 687b ldr r3, [r7, #4] 8012b74: 3308 adds r3, #8 8012b76: 60fb str r3, [r7, #12] 8012b78: e002 b.n 8012b80 8012b7a: 68fb ldr r3, [r7, #12] 8012b7c: 685b ldr r3, [r3, #4] 8012b7e: 60fb str r3, [r7, #12] 8012b80: 68fb ldr r3, [r7, #12] 8012b82: 685b ldr r3, [r3, #4] 8012b84: 681b ldr r3, [r3, #0] 8012b86: 68ba ldr r2, [r7, #8] 8012b88: 429a cmp r2, r3 8012b8a: d2f6 bcs.n 8012b7a /* There is nothing to do here, just iterating to the wanted insertion position. */ } } pxNewListItem->pxNext = pxIterator->pxNext; 8012b8c: 68fb ldr r3, [r7, #12] 8012b8e: 685a ldr r2, [r3, #4] 8012b90: 683b ldr r3, [r7, #0] 8012b92: 605a str r2, [r3, #4] pxNewListItem->pxNext->pxPrevious = pxNewListItem; 8012b94: 683b ldr r3, [r7, #0] 8012b96: 685b ldr r3, [r3, #4] 8012b98: 683a ldr r2, [r7, #0] 8012b9a: 609a str r2, [r3, #8] pxNewListItem->pxPrevious = pxIterator; 8012b9c: 683b ldr r3, [r7, #0] 8012b9e: 68fa ldr r2, [r7, #12] 8012ba0: 609a str r2, [r3, #8] pxIterator->pxNext = pxNewListItem; 8012ba2: 68fb ldr r3, [r7, #12] 8012ba4: 683a ldr r2, [r7, #0] 8012ba6: 605a str r2, [r3, #4] /* Remember which list the item is in. This allows fast removal of the item later. */ pxNewListItem->pxContainer = pxList; 8012ba8: 683b ldr r3, [r7, #0] 8012baa: 687a ldr r2, [r7, #4] 8012bac: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8012bae: 687b ldr r3, [r7, #4] 8012bb0: 681b ldr r3, [r3, #0] 8012bb2: 1c5a adds r2, r3, #1 8012bb4: 687b ldr r3, [r7, #4] 8012bb6: 601a str r2, [r3, #0] } 8012bb8: bf00 nop 8012bba: 3714 adds r7, #20 8012bbc: 46bd mov sp, r7 8012bbe: f85d 7b04 ldr.w r7, [sp], #4 8012bc2: 4770 bx lr 08012bc4 : /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { 8012bc4: b480 push {r7} 8012bc6: b085 sub sp, #20 8012bc8: af00 add r7, sp, #0 8012bca: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list item. */ List_t * const pxList = pxItemToRemove->pxContainer; 8012bcc: 687b ldr r3, [r7, #4] 8012bce: 691b ldr r3, [r3, #16] 8012bd0: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 8012bd2: 687b ldr r3, [r7, #4] 8012bd4: 685b ldr r3, [r3, #4] 8012bd6: 687a ldr r2, [r7, #4] 8012bd8: 6892 ldr r2, [r2, #8] 8012bda: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; 8012bdc: 687b ldr r3, [r7, #4] 8012bde: 689b ldr r3, [r3, #8] 8012be0: 687a ldr r2, [r7, #4] 8012be2: 6852 ldr r2, [r2, #4] 8012be4: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) 8012be6: 68fb ldr r3, [r7, #12] 8012be8: 685b ldr r3, [r3, #4] 8012bea: 687a ldr r2, [r7, #4] 8012bec: 429a cmp r2, r3 8012bee: d103 bne.n 8012bf8 { pxList->pxIndex = pxItemToRemove->pxPrevious; 8012bf0: 687b ldr r3, [r7, #4] 8012bf2: 689a ldr r2, [r3, #8] 8012bf4: 68fb ldr r3, [r7, #12] 8012bf6: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; 8012bf8: 687b ldr r3, [r7, #4] 8012bfa: 2200 movs r2, #0 8012bfc: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; 8012bfe: 68fb ldr r3, [r7, #12] 8012c00: 681b ldr r3, [r3, #0] 8012c02: 1e5a subs r2, r3, #1 8012c04: 68fb ldr r3, [r7, #12] 8012c06: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; 8012c08: 68fb ldr r3, [r7, #12] 8012c0a: 681b ldr r3, [r3, #0] } 8012c0c: 4618 mov r0, r3 8012c0e: 3714 adds r7, #20 8012c10: 46bd mov sp, r7 8012c12: f85d 7b04 ldr.w r7, [sp], #4 8012c16: 4770 bx lr 08012c18 : } \ taskEXIT_CRITICAL() /*-----------------------------------------------------------*/ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) { 8012c18: b580 push {r7, lr} 8012c1a: b084 sub sp, #16 8012c1c: af00 add r7, sp, #0 8012c1e: 6078 str r0, [r7, #4] 8012c20: 6039 str r1, [r7, #0] Queue_t * const pxQueue = xQueue; 8012c22: 687b ldr r3, [r7, #4] 8012c24: 60fb str r3, [r7, #12] configASSERT( pxQueue ); 8012c26: 68fb ldr r3, [r7, #12] 8012c28: 2b00 cmp r3, #0 8012c2a: d10b bne.n 8012c44 portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile 8012c2c: f04f 0350 mov.w r3, #80 @ 0x50 8012c30: f383 8811 msr BASEPRI, r3 8012c34: f3bf 8f6f isb sy 8012c38: f3bf 8f4f dsb sy 8012c3c: 60bb str r3, [r7, #8] " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } 8012c3e: bf00 nop 8012c40: bf00 nop 8012c42: e7fd b.n 8012c40 taskENTER_CRITICAL(); 8012c44: f003 f960 bl 8015f08 { pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8012c48: 68fb ldr r3, [r7, #12] 8012c4a: 681a ldr r2, [r3, #0] 8012c4c: 68fb ldr r3, [r7, #12] 8012c4e: 6bdb ldr r3, [r3, #60] @ 0x3c 8012c50: 68f9 ldr r1, [r7, #12] 8012c52: 6c09 ldr r1, [r1, #64] @ 0x40 8012c54: fb01 f303 mul.w r3, r1, r3 8012c58: 441a add r2, r3 8012c5a: 68fb ldr r3, [r7, #12] 8012c5c: 609a str r2, [r3, #8] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 8012c5e: 68fb ldr r3, [r7, #12] 8012c60: 2200 movs r2, #0 8012c62: 639a str r2, [r3, #56] @ 0x38 pxQueue->pcWriteTo = pxQueue->pcHead; 8012c64: 68fb ldr r3, [r7, #12] 8012c66: 681a ldr r2, [r3, #0] 8012c68: 68fb ldr r3, [r7, #12] 8012c6a: 605a str r2, [r3, #4] pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8012c6c: 68fb ldr r3, [r7, #12] 8012c6e: 681a ldr r2, [r3, #0] 8012c70: 68fb ldr r3, [r7, #12] 8012c72: 6bdb ldr r3, [r3, #60] @ 0x3c 8012c74: 3b01 subs r3, #1 8012c76: 68f9 ldr r1, [r7, #12] 8012c78: 6c09 ldr r1, [r1, #64] @ 0x40 8012c7a: fb01 f303 mul.w r3, r1, r3 8012c7e: 441a add r2, r3 8012c80: 68fb ldr r3, [r7, #12] 8012c82: 60da str r2, [r3, #12] pxQueue->cRxLock = queueUNLOCKED; 8012c84: 68fb ldr r3, [r7, #12] 8012c86: 22ff movs r2, #255 @ 0xff 8012c88: f883 2044 strb.w r2, [r3, #68] @ 0x44 pxQueue->cTxLock = queueUNLOCKED; 8012c8c: 68fb ldr r3, [r7, #12] 8012c8e: 22ff movs r2, #255 @ 0xff 8012c90: f883 2045 strb.w r2, [r3, #69] @ 0x45 if( xNewQueue == pdFALSE ) 8012c94: 683b ldr r3, [r7, #0] 8012c96: 2b00 cmp r3, #0 8012c98: d114 bne.n 8012cc4 /* If there are tasks blocked waiting to read from the queue, then the tasks will remain blocked as after this function exits the queue will still be empty. If there are tasks blocked waiting to write to the queue, then one should be unblocked as after this function exits it will be possible to write to it. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8012c9a: 68fb ldr r3, [r7, #12] 8012c9c: 691b ldr r3, [r3, #16] 8012c9e: 2b00 cmp r3, #0 8012ca0: d01a beq.n 8012cd8 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8012ca2: 68fb ldr r3, [r7, #12] 8012ca4: 3310 adds r3, #16 8012ca6: 4618 mov r0, r3 8012ca8: f001 fdac bl 8014804 8012cac: 4603 mov r3, r0 8012cae: 2b00 cmp r3, #0 8012cb0: d012 beq.n 8012cd8 { queueYIELD_IF_USING_PREEMPTION(); 8012cb2: 4b0d ldr r3, [pc, #52] @ (8012ce8 ) 8012cb4: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8012cb8: 601a str r2, [r3, #0] 8012cba: f3bf 8f4f dsb sy 8012cbe: f3bf 8f6f isb sy 8012cc2: e009 b.n 8012cd8 } } else { /* Ensure the event queues start in the correct state. */ vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 8012cc4: 68fb ldr r3, [r7, #12] 8012cc6: 3310 adds r3, #16 8012cc8: 4618 mov r0, r3 8012cca: f7ff fef1 bl 8012ab0 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); 8012cce: 68fb ldr r3, [r7, #12] 8012cd0: 3324 adds r3, #36 @ 0x24 8012cd2: 4618 mov r0, r3 8012cd4: f7ff feec bl 8012ab0 } } taskEXIT_CRITICAL(); 8012cd8: f003 f948 bl 8015f6c /* A value is returned for calling semantic consistency with previous versions. */ return pdPASS; 8012cdc: 2301 movs r3, #1 } 8012cde: 4618 mov r0, r3 8012ce0: 3710 adds r7, #16 8012ce2: 46bd mov sp, r7 8012ce4: bd80 pop {r7, pc} 8012ce6: bf00 nop 8012ce8: e000ed04 .word 0xe000ed04 08012cec : /*-----------------------------------------------------------*/ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) { 8012cec: b580 push {r7, lr} 8012cee: b08e sub sp, #56 @ 0x38 8012cf0: af02 add r7, sp, #8 8012cf2: 60f8 str r0, [r7, #12] 8012cf4: 60b9 str r1, [r7, #8] 8012cf6: 607a str r2, [r7, #4] 8012cf8: 603b str r3, [r7, #0] Queue_t *pxNewQueue; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 8012cfa: 68fb ldr r3, [r7, #12] 8012cfc: 2b00 cmp r3, #0 8012cfe: d10b bne.n 8012d18 __asm volatile 8012d00: f04f 0350 mov.w r3, #80 @ 0x50 8012d04: f383 8811 msr BASEPRI, r3 8012d08: f3bf 8f6f isb sy 8012d0c: f3bf 8f4f dsb sy 8012d10: 62bb str r3, [r7, #40] @ 0x28 } 8012d12: bf00 nop 8012d14: bf00 nop 8012d16: e7fd b.n 8012d14 /* The StaticQueue_t structure and the queue storage area must be supplied. */ configASSERT( pxStaticQueue != NULL ); 8012d18: 683b ldr r3, [r7, #0] 8012d1a: 2b00 cmp r3, #0 8012d1c: d10b bne.n 8012d36 __asm volatile 8012d1e: f04f 0350 mov.w r3, #80 @ 0x50 8012d22: f383 8811 msr BASEPRI, r3 8012d26: f3bf 8f6f isb sy 8012d2a: f3bf 8f4f dsb sy 8012d2e: 627b str r3, [r7, #36] @ 0x24 } 8012d30: bf00 nop 8012d32: bf00 nop 8012d34: e7fd b.n 8012d32 /* A queue storage area should be provided if the item size is not 0, and should not be provided if the item size is 0. */ configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); 8012d36: 687b ldr r3, [r7, #4] 8012d38: 2b00 cmp r3, #0 8012d3a: d002 beq.n 8012d42 8012d3c: 68bb ldr r3, [r7, #8] 8012d3e: 2b00 cmp r3, #0 8012d40: d001 beq.n 8012d46 8012d42: 2301 movs r3, #1 8012d44: e000 b.n 8012d48 8012d46: 2300 movs r3, #0 8012d48: 2b00 cmp r3, #0 8012d4a: d10b bne.n 8012d64 __asm volatile 8012d4c: f04f 0350 mov.w r3, #80 @ 0x50 8012d50: f383 8811 msr BASEPRI, r3 8012d54: f3bf 8f6f isb sy 8012d58: f3bf 8f4f dsb sy 8012d5c: 623b str r3, [r7, #32] } 8012d5e: bf00 nop 8012d60: bf00 nop 8012d62: e7fd b.n 8012d60 configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); 8012d64: 687b ldr r3, [r7, #4] 8012d66: 2b00 cmp r3, #0 8012d68: d102 bne.n 8012d70 8012d6a: 68bb ldr r3, [r7, #8] 8012d6c: 2b00 cmp r3, #0 8012d6e: d101 bne.n 8012d74 8012d70: 2301 movs r3, #1 8012d72: e000 b.n 8012d76 8012d74: 2300 movs r3, #0 8012d76: 2b00 cmp r3, #0 8012d78: d10b bne.n 8012d92 __asm volatile 8012d7a: f04f 0350 mov.w r3, #80 @ 0x50 8012d7e: f383 8811 msr BASEPRI, r3 8012d82: f3bf 8f6f isb sy 8012d86: f3bf 8f4f dsb sy 8012d8a: 61fb str r3, [r7, #28] } 8012d8c: bf00 nop 8012d8e: bf00 nop 8012d90: e7fd b.n 8012d8e #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticQueue_t or StaticSemaphore_t equals the size of the real queue and semaphore structures. */ volatile size_t xSize = sizeof( StaticQueue_t ); 8012d92: 2350 movs r3, #80 @ 0x50 8012d94: 617b str r3, [r7, #20] configASSERT( xSize == sizeof( Queue_t ) ); 8012d96: 697b ldr r3, [r7, #20] 8012d98: 2b50 cmp r3, #80 @ 0x50 8012d9a: d00b beq.n 8012db4 __asm volatile 8012d9c: f04f 0350 mov.w r3, #80 @ 0x50 8012da0: f383 8811 msr BASEPRI, r3 8012da4: f3bf 8f6f isb sy 8012da8: f3bf 8f4f dsb sy 8012dac: 61bb str r3, [r7, #24] } 8012dae: bf00 nop 8012db0: bf00 nop 8012db2: e7fd b.n 8012db0 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 8012db4: 697b ldr r3, [r7, #20] #endif /* configASSERT_DEFINED */ /* The address of a statically allocated queue was passed in, use it. The address of a statically allocated storage area was also passed in but is already set. */ pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8012db6: 683b ldr r3, [r7, #0] 8012db8: 62fb str r3, [r7, #44] @ 0x2c if( pxNewQueue != NULL ) 8012dba: 6afb ldr r3, [r7, #44] @ 0x2c 8012dbc: 2b00 cmp r3, #0 8012dbe: d00d beq.n 8012ddc #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* Queues can be allocated wither statically or dynamically, so note this queue was allocated statically in case the queue is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdTRUE; 8012dc0: 6afb ldr r3, [r7, #44] @ 0x2c 8012dc2: 2201 movs r2, #1 8012dc4: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8012dc8: f897 2038 ldrb.w r2, [r7, #56] @ 0x38 8012dcc: 6afb ldr r3, [r7, #44] @ 0x2c 8012dce: 9300 str r3, [sp, #0] 8012dd0: 4613 mov r3, r2 8012dd2: 687a ldr r2, [r7, #4] 8012dd4: 68b9 ldr r1, [r7, #8] 8012dd6: 68f8 ldr r0, [r7, #12] 8012dd8: f000 f840 bl 8012e5c { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 8012ddc: 6afb ldr r3, [r7, #44] @ 0x2c } 8012dde: 4618 mov r0, r3 8012de0: 3730 adds r7, #48 @ 0x30 8012de2: 46bd mov sp, r7 8012de4: bd80 pop {r7, pc} 08012de6 : /*-----------------------------------------------------------*/ #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) { 8012de6: b580 push {r7, lr} 8012de8: b08a sub sp, #40 @ 0x28 8012dea: af02 add r7, sp, #8 8012dec: 60f8 str r0, [r7, #12] 8012dee: 60b9 str r1, [r7, #8] 8012df0: 4613 mov r3, r2 8012df2: 71fb strb r3, [r7, #7] Queue_t *pxNewQueue; size_t xQueueSizeInBytes; uint8_t *pucQueueStorage; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 8012df4: 68fb ldr r3, [r7, #12] 8012df6: 2b00 cmp r3, #0 8012df8: d10b bne.n 8012e12 __asm volatile 8012dfa: f04f 0350 mov.w r3, #80 @ 0x50 8012dfe: f383 8811 msr BASEPRI, r3 8012e02: f3bf 8f6f isb sy 8012e06: f3bf 8f4f dsb sy 8012e0a: 613b str r3, [r7, #16] } 8012e0c: bf00 nop 8012e0e: bf00 nop 8012e10: e7fd b.n 8012e0e /* Allocate enough space to hold the maximum number of items that can be in the queue at any time. It is valid for uxItemSize to be zero in the case the queue is used as a semaphore. */ xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8012e12: 68fb ldr r3, [r7, #12] 8012e14: 68ba ldr r2, [r7, #8] 8012e16: fb02 f303 mul.w r3, r2, r3 8012e1a: 61fb str r3, [r7, #28] alignment requirements of the Queue_t structure - which in this case is an int8_t *. Therefore, whenever the stack alignment requirements are greater than or equal to the pointer to char requirements the cast is safe. In other cases alignment requirements are not strict (one or two bytes). */ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ 8012e1c: 69fb ldr r3, [r7, #28] 8012e1e: 3350 adds r3, #80 @ 0x50 8012e20: 4618 mov r0, r3 8012e22: f003 f993 bl 801614c 8012e26: 61b8 str r0, [r7, #24] if( pxNewQueue != NULL ) 8012e28: 69bb ldr r3, [r7, #24] 8012e2a: 2b00 cmp r3, #0 8012e2c: d011 beq.n 8012e52 { /* Jump past the queue structure to find the location of the queue storage area. */ pucQueueStorage = ( uint8_t * ) pxNewQueue; 8012e2e: 69bb ldr r3, [r7, #24] 8012e30: 617b str r3, [r7, #20] pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8012e32: 697b ldr r3, [r7, #20] 8012e34: 3350 adds r3, #80 @ 0x50 8012e36: 617b str r3, [r7, #20] #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { /* Queues can be created either statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdFALSE; 8012e38: 69bb ldr r3, [r7, #24] 8012e3a: 2200 movs r2, #0 8012e3c: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_STATIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8012e40: 79fa ldrb r2, [r7, #7] 8012e42: 69bb ldr r3, [r7, #24] 8012e44: 9300 str r3, [sp, #0] 8012e46: 4613 mov r3, r2 8012e48: 697a ldr r2, [r7, #20] 8012e4a: 68b9 ldr r1, [r7, #8] 8012e4c: 68f8 ldr r0, [r7, #12] 8012e4e: f000 f805 bl 8012e5c { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 8012e52: 69bb ldr r3, [r7, #24] } 8012e54: 4618 mov r0, r3 8012e56: 3720 adds r7, #32 8012e58: 46bd mov sp, r7 8012e5a: bd80 pop {r7, pc} 08012e5c : #endif /* configSUPPORT_STATIC_ALLOCATION */ /*-----------------------------------------------------------*/ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) { 8012e5c: b580 push {r7, lr} 8012e5e: b084 sub sp, #16 8012e60: af00 add r7, sp, #0 8012e62: 60f8 str r0, [r7, #12] 8012e64: 60b9 str r1, [r7, #8] 8012e66: 607a str r2, [r7, #4] 8012e68: 70fb strb r3, [r7, #3] /* Remove compiler warnings about unused parameters should configUSE_TRACE_FACILITY not be set to 1. */ ( void ) ucQueueType; if( uxItemSize == ( UBaseType_t ) 0 ) 8012e6a: 68bb ldr r3, [r7, #8] 8012e6c: 2b00 cmp r3, #0 8012e6e: d103 bne.n 8012e78 { /* No RAM was allocated for the queue storage area, but PC head cannot be set to NULL because NULL is used as a key to say the queue is used as a mutex. Therefore just set pcHead to point to the queue as a benign value that is known to be within the memory map. */ pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; 8012e70: 69bb ldr r3, [r7, #24] 8012e72: 69ba ldr r2, [r7, #24] 8012e74: 601a str r2, [r3, #0] 8012e76: e002 b.n 8012e7e } else { /* Set the head to the start of the queue storage area. */ pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; 8012e78: 69bb ldr r3, [r7, #24] 8012e7a: 687a ldr r2, [r7, #4] 8012e7c: 601a str r2, [r3, #0] } /* Initialise the queue members as described where the queue type is defined. */ pxNewQueue->uxLength = uxQueueLength; 8012e7e: 69bb ldr r3, [r7, #24] 8012e80: 68fa ldr r2, [r7, #12] 8012e82: 63da str r2, [r3, #60] @ 0x3c pxNewQueue->uxItemSize = uxItemSize; 8012e84: 69bb ldr r3, [r7, #24] 8012e86: 68ba ldr r2, [r7, #8] 8012e88: 641a str r2, [r3, #64] @ 0x40 ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); 8012e8a: 2101 movs r1, #1 8012e8c: 69b8 ldr r0, [r7, #24] 8012e8e: f7ff fec3 bl 8012c18 #if ( configUSE_TRACE_FACILITY == 1 ) { pxNewQueue->ucQueueType = ucQueueType; 8012e92: 69bb ldr r3, [r7, #24] 8012e94: 78fa ldrb r2, [r7, #3] 8012e96: f883 204c strb.w r2, [r3, #76] @ 0x4c pxNewQueue->pxQueueSetContainer = NULL; } #endif /* configUSE_QUEUE_SETS */ traceQUEUE_CREATE( pxNewQueue ); } 8012e9a: bf00 nop 8012e9c: 3710 adds r7, #16 8012e9e: 46bd mov sp, r7 8012ea0: bd80 pop {r7, pc} 08012ea2 : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static void prvInitialiseMutex( Queue_t *pxNewQueue ) { 8012ea2: b580 push {r7, lr} 8012ea4: b082 sub sp, #8 8012ea6: af00 add r7, sp, #0 8012ea8: 6078 str r0, [r7, #4] if( pxNewQueue != NULL ) 8012eaa: 687b ldr r3, [r7, #4] 8012eac: 2b00 cmp r3, #0 8012eae: d00e beq.n 8012ece { /* The queue create function will set all the queue structure members correctly for a generic queue, but this function is creating a mutex. Overwrite those members that need to be set differently - in particular the information required for priority inheritance. */ pxNewQueue->u.xSemaphore.xMutexHolder = NULL; 8012eb0: 687b ldr r3, [r7, #4] 8012eb2: 2200 movs r2, #0 8012eb4: 609a str r2, [r3, #8] pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; 8012eb6: 687b ldr r3, [r7, #4] 8012eb8: 2200 movs r2, #0 8012eba: 601a str r2, [r3, #0] /* In case this is a recursive mutex. */ pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; 8012ebc: 687b ldr r3, [r7, #4] 8012ebe: 2200 movs r2, #0 8012ec0: 60da str r2, [r3, #12] traceCREATE_MUTEX( pxNewQueue ); /* Start with the semaphore in the expected state. */ ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); 8012ec2: 2300 movs r3, #0 8012ec4: 2200 movs r2, #0 8012ec6: 2100 movs r1, #0 8012ec8: 6878 ldr r0, [r7, #4] 8012eca: f000 f8a3 bl 8013014 } else { traceCREATE_MUTEX_FAILED(); } } 8012ece: bf00 nop 8012ed0: 3708 adds r7, #8 8012ed2: 46bd mov sp, r7 8012ed4: bd80 pop {r7, pc} 08012ed6 : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) { 8012ed6: b580 push {r7, lr} 8012ed8: b086 sub sp, #24 8012eda: af00 add r7, sp, #0 8012edc: 4603 mov r3, r0 8012ede: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8012ee0: 2301 movs r3, #1 8012ee2: 617b str r3, [r7, #20] 8012ee4: 2300 movs r3, #0 8012ee6: 613b str r3, [r7, #16] xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); 8012ee8: 79fb ldrb r3, [r7, #7] 8012eea: 461a mov r2, r3 8012eec: 6939 ldr r1, [r7, #16] 8012eee: 6978 ldr r0, [r7, #20] 8012ef0: f7ff ff79 bl 8012de6 8012ef4: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 8012ef6: 68f8 ldr r0, [r7, #12] 8012ef8: f7ff ffd3 bl 8012ea2 return xNewQueue; 8012efc: 68fb ldr r3, [r7, #12] } 8012efe: 4618 mov r0, r3 8012f00: 3718 adds r7, #24 8012f02: 46bd mov sp, r7 8012f04: bd80 pop {r7, pc} 08012f06 : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) { 8012f06: b580 push {r7, lr} 8012f08: b088 sub sp, #32 8012f0a: af02 add r7, sp, #8 8012f0c: 4603 mov r3, r0 8012f0e: 6039 str r1, [r7, #0] 8012f10: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8012f12: 2301 movs r3, #1 8012f14: 617b str r3, [r7, #20] 8012f16: 2300 movs r3, #0 8012f18: 613b str r3, [r7, #16] /* Prevent compiler warnings about unused parameters if configUSE_TRACE_FACILITY does not equal 1. */ ( void ) ucQueueType; xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); 8012f1a: 79fb ldrb r3, [r7, #7] 8012f1c: 9300 str r3, [sp, #0] 8012f1e: 683b ldr r3, [r7, #0] 8012f20: 2200 movs r2, #0 8012f22: 6939 ldr r1, [r7, #16] 8012f24: 6978 ldr r0, [r7, #20] 8012f26: f7ff fee1 bl 8012cec 8012f2a: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 8012f2c: 68f8 ldr r0, [r7, #12] 8012f2e: f7ff ffb8 bl 8012ea2 return xNewQueue; 8012f32: 68fb ldr r3, [r7, #12] } 8012f34: 4618 mov r0, r3 8012f36: 3718 adds r7, #24 8012f38: 46bd mov sp, r7 8012f3a: bd80 pop {r7, pc} 08012f3c : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) { 8012f3c: b590 push {r4, r7, lr} 8012f3e: b087 sub sp, #28 8012f40: af00 add r7, sp, #0 8012f42: 6078 str r0, [r7, #4] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8012f44: 687b ldr r3, [r7, #4] 8012f46: 613b str r3, [r7, #16] configASSERT( pxMutex ); 8012f48: 693b ldr r3, [r7, #16] 8012f4a: 2b00 cmp r3, #0 8012f4c: d10b bne.n 8012f66 __asm volatile 8012f4e: f04f 0350 mov.w r3, #80 @ 0x50 8012f52: f383 8811 msr BASEPRI, r3 8012f56: f3bf 8f6f isb sy 8012f5a: f3bf 8f4f dsb sy 8012f5e: 60fb str r3, [r7, #12] } 8012f60: bf00 nop 8012f62: bf00 nop 8012f64: e7fd b.n 8012f62 change outside of this task. If this task does not hold the mutex then pxMutexHolder can never coincidentally equal the tasks handle, and as this is the only condition we are interested in it does not matter if pxMutexHolder is accessed simultaneously by another task. Therefore no mutual exclusion is required to test the pxMutexHolder variable. */ if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 8012f66: 693b ldr r3, [r7, #16] 8012f68: 689c ldr r4, [r3, #8] 8012f6a: f001 fe39 bl 8014be0 8012f6e: 4603 mov r3, r0 8012f70: 429c cmp r4, r3 8012f72: d111 bne.n 8012f98 /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to the task handle, therefore no underflow check is required. Also, uxRecursiveCallCount is only modified by the mutex holder, and as there can only be one, no mutual exclusion is required to modify the uxRecursiveCallCount member. */ ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; 8012f74: 693b ldr r3, [r7, #16] 8012f76: 68db ldr r3, [r3, #12] 8012f78: 1e5a subs r2, r3, #1 8012f7a: 693b ldr r3, [r7, #16] 8012f7c: 60da str r2, [r3, #12] /* Has the recursive call count unwound to 0? */ if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) 8012f7e: 693b ldr r3, [r7, #16] 8012f80: 68db ldr r3, [r3, #12] 8012f82: 2b00 cmp r3, #0 8012f84: d105 bne.n 8012f92 { /* Return the mutex. This will automatically unblock any other task that might be waiting to access the mutex. */ ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); 8012f86: 2300 movs r3, #0 8012f88: 2200 movs r2, #0 8012f8a: 2100 movs r1, #0 8012f8c: 6938 ldr r0, [r7, #16] 8012f8e: f000 f841 bl 8013014 else { mtCOVERAGE_TEST_MARKER(); } xReturn = pdPASS; 8012f92: 2301 movs r3, #1 8012f94: 617b str r3, [r7, #20] 8012f96: e001 b.n 8012f9c } else { /* The mutex cannot be given because the calling task is not the holder. */ xReturn = pdFAIL; 8012f98: 2300 movs r3, #0 8012f9a: 617b str r3, [r7, #20] traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); } return xReturn; 8012f9c: 697b ldr r3, [r7, #20] } 8012f9e: 4618 mov r0, r3 8012fa0: 371c adds r7, #28 8012fa2: 46bd mov sp, r7 8012fa4: bd90 pop {r4, r7, pc} 08012fa6 : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) { 8012fa6: b590 push {r4, r7, lr} 8012fa8: b087 sub sp, #28 8012faa: af00 add r7, sp, #0 8012fac: 6078 str r0, [r7, #4] 8012fae: 6039 str r1, [r7, #0] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8012fb0: 687b ldr r3, [r7, #4] 8012fb2: 613b str r3, [r7, #16] configASSERT( pxMutex ); 8012fb4: 693b ldr r3, [r7, #16] 8012fb6: 2b00 cmp r3, #0 8012fb8: d10b bne.n 8012fd2 __asm volatile 8012fba: f04f 0350 mov.w r3, #80 @ 0x50 8012fbe: f383 8811 msr BASEPRI, r3 8012fc2: f3bf 8f6f isb sy 8012fc6: f3bf 8f4f dsb sy 8012fca: 60fb str r3, [r7, #12] } 8012fcc: bf00 nop 8012fce: bf00 nop 8012fd0: e7fd b.n 8012fce /* Comments regarding mutual exclusion as per those within xQueueGiveMutexRecursive(). */ traceTAKE_MUTEX_RECURSIVE( pxMutex ); if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 8012fd2: 693b ldr r3, [r7, #16] 8012fd4: 689c ldr r4, [r3, #8] 8012fd6: f001 fe03 bl 8014be0 8012fda: 4603 mov r3, r0 8012fdc: 429c cmp r4, r3 8012fde: d107 bne.n 8012ff0 { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 8012fe0: 693b ldr r3, [r7, #16] 8012fe2: 68db ldr r3, [r3, #12] 8012fe4: 1c5a adds r2, r3, #1 8012fe6: 693b ldr r3, [r7, #16] 8012fe8: 60da str r2, [r3, #12] xReturn = pdPASS; 8012fea: 2301 movs r3, #1 8012fec: 617b str r3, [r7, #20] 8012fee: e00c b.n 801300a } else { xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait ); 8012ff0: 6839 ldr r1, [r7, #0] 8012ff2: 6938 ldr r0, [r7, #16] 8012ff4: f000 fa90 bl 8013518 8012ff8: 6178 str r0, [r7, #20] /* pdPASS will only be returned if the mutex was successfully obtained. The calling task may have entered the Blocked state before reaching here. */ if( xReturn != pdFAIL ) 8012ffa: 697b ldr r3, [r7, #20] 8012ffc: 2b00 cmp r3, #0 8012ffe: d004 beq.n 801300a { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 8013000: 693b ldr r3, [r7, #16] 8013002: 68db ldr r3, [r3, #12] 8013004: 1c5a adds r2, r3, #1 8013006: 693b ldr r3, [r7, #16] 8013008: 60da str r2, [r3, #12] { traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ); } } return xReturn; 801300a: 697b ldr r3, [r7, #20] } 801300c: 4618 mov r0, r3 801300e: 371c adds r7, #28 8013010: 46bd mov sp, r7 8013012: bd90 pop {r4, r7, pc} 08013014 : #endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) { 8013014: b580 push {r7, lr} 8013016: b08e sub sp, #56 @ 0x38 8013018: af00 add r7, sp, #0 801301a: 60f8 str r0, [r7, #12] 801301c: 60b9 str r1, [r7, #8] 801301e: 607a str r2, [r7, #4] 8013020: 603b str r3, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; 8013022: 2300 movs r3, #0 8013024: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8013026: 68fb ldr r3, [r7, #12] 8013028: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 801302a: 6b3b ldr r3, [r7, #48] @ 0x30 801302c: 2b00 cmp r3, #0 801302e: d10b bne.n 8013048 __asm volatile 8013030: f04f 0350 mov.w r3, #80 @ 0x50 8013034: f383 8811 msr BASEPRI, r3 8013038: f3bf 8f6f isb sy 801303c: f3bf 8f4f dsb sy 8013040: 62bb str r3, [r7, #40] @ 0x28 } 8013042: bf00 nop 8013044: bf00 nop 8013046: e7fd b.n 8013044 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8013048: 68bb ldr r3, [r7, #8] 801304a: 2b00 cmp r3, #0 801304c: d103 bne.n 8013056 801304e: 6b3b ldr r3, [r7, #48] @ 0x30 8013050: 6c1b ldr r3, [r3, #64] @ 0x40 8013052: 2b00 cmp r3, #0 8013054: d101 bne.n 801305a 8013056: 2301 movs r3, #1 8013058: e000 b.n 801305c 801305a: 2300 movs r3, #0 801305c: 2b00 cmp r3, #0 801305e: d10b bne.n 8013078 __asm volatile 8013060: f04f 0350 mov.w r3, #80 @ 0x50 8013064: f383 8811 msr BASEPRI, r3 8013068: f3bf 8f6f isb sy 801306c: f3bf 8f4f dsb sy 8013070: 627b str r3, [r7, #36] @ 0x24 } 8013072: bf00 nop 8013074: bf00 nop 8013076: e7fd b.n 8013074 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8013078: 683b ldr r3, [r7, #0] 801307a: 2b02 cmp r3, #2 801307c: d103 bne.n 8013086 801307e: 6b3b ldr r3, [r7, #48] @ 0x30 8013080: 6bdb ldr r3, [r3, #60] @ 0x3c 8013082: 2b01 cmp r3, #1 8013084: d101 bne.n 801308a 8013086: 2301 movs r3, #1 8013088: e000 b.n 801308c 801308a: 2300 movs r3, #0 801308c: 2b00 cmp r3, #0 801308e: d10b bne.n 80130a8 __asm volatile 8013090: f04f 0350 mov.w r3, #80 @ 0x50 8013094: f383 8811 msr BASEPRI, r3 8013098: f3bf 8f6f isb sy 801309c: f3bf 8f4f dsb sy 80130a0: 623b str r3, [r7, #32] } 80130a2: bf00 nop 80130a4: bf00 nop 80130a6: e7fd b.n 80130a4 #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 80130a8: f001 fdaa bl 8014c00 80130ac: 4603 mov r3, r0 80130ae: 2b00 cmp r3, #0 80130b0: d102 bne.n 80130b8 80130b2: 687b ldr r3, [r7, #4] 80130b4: 2b00 cmp r3, #0 80130b6: d101 bne.n 80130bc 80130b8: 2301 movs r3, #1 80130ba: e000 b.n 80130be 80130bc: 2300 movs r3, #0 80130be: 2b00 cmp r3, #0 80130c0: d10b bne.n 80130da __asm volatile 80130c2: f04f 0350 mov.w r3, #80 @ 0x50 80130c6: f383 8811 msr BASEPRI, r3 80130ca: f3bf 8f6f isb sy 80130ce: f3bf 8f4f dsb sy 80130d2: 61fb str r3, [r7, #28] } 80130d4: bf00 nop 80130d6: bf00 nop 80130d8: e7fd b.n 80130d6 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 80130da: f002 ff15 bl 8015f08 { /* Is there room on the queue now? The running task must be the highest priority task wanting to access the queue. If the head item in the queue is to be overwritten then it does not matter if the queue is full. */ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 80130de: 6b3b ldr r3, [r7, #48] @ 0x30 80130e0: 6b9a ldr r2, [r3, #56] @ 0x38 80130e2: 6b3b ldr r3, [r7, #48] @ 0x30 80130e4: 6bdb ldr r3, [r3, #60] @ 0x3c 80130e6: 429a cmp r2, r3 80130e8: d302 bcc.n 80130f0 80130ea: 683b ldr r3, [r7, #0] 80130ec: 2b02 cmp r3, #2 80130ee: d129 bne.n 8013144 } } } #else /* configUSE_QUEUE_SETS */ { xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 80130f0: 683a ldr r2, [r7, #0] 80130f2: 68b9 ldr r1, [r7, #8] 80130f4: 6b38 ldr r0, [r7, #48] @ 0x30 80130f6: f000 fbb9 bl 801386c 80130fa: 62f8 str r0, [r7, #44] @ 0x2c /* If there was a task waiting for data to arrive on the queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 80130fc: 6b3b ldr r3, [r7, #48] @ 0x30 80130fe: 6a5b ldr r3, [r3, #36] @ 0x24 8013100: 2b00 cmp r3, #0 8013102: d010 beq.n 8013126 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8013104: 6b3b ldr r3, [r7, #48] @ 0x30 8013106: 3324 adds r3, #36 @ 0x24 8013108: 4618 mov r0, r3 801310a: f001 fb7b bl 8014804 801310e: 4603 mov r3, r0 8013110: 2b00 cmp r3, #0 8013112: d013 beq.n 801313c { /* The unblocked task has a priority higher than our own so yield immediately. Yes it is ok to do this from within the critical section - the kernel takes care of that. */ queueYIELD_IF_USING_PREEMPTION(); 8013114: 4b3f ldr r3, [pc, #252] @ (8013214 ) 8013116: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801311a: 601a str r2, [r3, #0] 801311c: f3bf 8f4f dsb sy 8013120: f3bf 8f6f isb sy 8013124: e00a b.n 801313c else { mtCOVERAGE_TEST_MARKER(); } } else if( xYieldRequired != pdFALSE ) 8013126: 6afb ldr r3, [r7, #44] @ 0x2c 8013128: 2b00 cmp r3, #0 801312a: d007 beq.n 801313c { /* This path is a special case that will only get executed if the task was holding multiple mutexes and the mutexes were given back in an order that is different to that in which they were taken. */ queueYIELD_IF_USING_PREEMPTION(); 801312c: 4b39 ldr r3, [pc, #228] @ (8013214 ) 801312e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8013132: 601a str r2, [r3, #0] 8013134: f3bf 8f4f dsb sy 8013138: f3bf 8f6f isb sy mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); 801313c: f002 ff16 bl 8015f6c return pdPASS; 8013140: 2301 movs r3, #1 8013142: e063 b.n 801320c } else { if( xTicksToWait == ( TickType_t ) 0 ) 8013144: 687b ldr r3, [r7, #4] 8013146: 2b00 cmp r3, #0 8013148: d103 bne.n 8013152 { /* The queue was full and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 801314a: f002 ff0f bl 8015f6c /* Return to the original privilege level before exiting the function. */ traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 801314e: 2300 movs r3, #0 8013150: e05c b.n 801320c } else if( xEntryTimeSet == pdFALSE ) 8013152: 6b7b ldr r3, [r7, #52] @ 0x34 8013154: 2b00 cmp r3, #0 8013156: d106 bne.n 8013166 { /* The queue was full and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8013158: f107 0314 add.w r3, r7, #20 801315c: 4618 mov r0, r3 801315e: f001 fbdd bl 801491c xEntryTimeSet = pdTRUE; 8013162: 2301 movs r3, #1 8013164: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8013166: f002 ff01 bl 8015f6c /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 801316a: f001 f90f bl 801438c prvLockQueue( pxQueue ); 801316e: f002 fecb bl 8015f08 8013172: 6b3b ldr r3, [r7, #48] @ 0x30 8013174: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8013178: b25b sxtb r3, r3 801317a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801317e: d103 bne.n 8013188 8013180: 6b3b ldr r3, [r7, #48] @ 0x30 8013182: 2200 movs r2, #0 8013184: f883 2044 strb.w r2, [r3, #68] @ 0x44 8013188: 6b3b ldr r3, [r7, #48] @ 0x30 801318a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 801318e: b25b sxtb r3, r3 8013190: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8013194: d103 bne.n 801319e 8013196: 6b3b ldr r3, [r7, #48] @ 0x30 8013198: 2200 movs r2, #0 801319a: f883 2045 strb.w r2, [r3, #69] @ 0x45 801319e: f002 fee5 bl 8015f6c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 80131a2: 1d3a adds r2, r7, #4 80131a4: f107 0314 add.w r3, r7, #20 80131a8: 4611 mov r1, r2 80131aa: 4618 mov r0, r3 80131ac: f001 fbcc bl 8014948 80131b0: 4603 mov r3, r0 80131b2: 2b00 cmp r3, #0 80131b4: d124 bne.n 8013200 { if( prvIsQueueFull( pxQueue ) != pdFALSE ) 80131b6: 6b38 ldr r0, [r7, #48] @ 0x30 80131b8: f000 fc50 bl 8013a5c 80131bc: 4603 mov r3, r0 80131be: 2b00 cmp r3, #0 80131c0: d018 beq.n 80131f4 { traceBLOCKING_ON_QUEUE_SEND( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); 80131c2: 6b3b ldr r3, [r7, #48] @ 0x30 80131c4: 3310 adds r3, #16 80131c6: 687a ldr r2, [r7, #4] 80131c8: 4611 mov r1, r2 80131ca: 4618 mov r0, r3 80131cc: f001 fac8 bl 8014760 /* Unlocking the queue means queue events can effect the event list. It is possible that interrupts occurring now remove this task from the event list again - but as the scheduler is suspended the task will go onto the pending ready last instead of the actual ready list. */ prvUnlockQueue( pxQueue ); 80131d0: 6b38 ldr r0, [r7, #48] @ 0x30 80131d2: f000 fbdb bl 801398c /* Resuming the scheduler will move tasks from the pending ready list into the ready list - so it is feasible that this task is already in a ready list before it yields - in which case the yield will not cause a context switch unless there is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) 80131d6: f001 f8e7 bl 80143a8 80131da: 4603 mov r3, r0 80131dc: 2b00 cmp r3, #0 80131de: f47f af7c bne.w 80130da { portYIELD_WITHIN_API(); 80131e2: 4b0c ldr r3, [pc, #48] @ (8013214 ) 80131e4: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80131e8: 601a str r2, [r3, #0] 80131ea: f3bf 8f4f dsb sy 80131ee: f3bf 8f6f isb sy 80131f2: e772 b.n 80130da } } else { /* Try again. */ prvUnlockQueue( pxQueue ); 80131f4: 6b38 ldr r0, [r7, #48] @ 0x30 80131f6: f000 fbc9 bl 801398c ( void ) xTaskResumeAll(); 80131fa: f001 f8d5 bl 80143a8 80131fe: e76c b.n 80130da } } else { /* The timeout has expired. */ prvUnlockQueue( pxQueue ); 8013200: 6b38 ldr r0, [r7, #48] @ 0x30 8013202: f000 fbc3 bl 801398c ( void ) xTaskResumeAll(); 8013206: f001 f8cf bl 80143a8 traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 801320a: 2300 movs r3, #0 } } /*lint -restore */ } 801320c: 4618 mov r0, r3 801320e: 3738 adds r7, #56 @ 0x38 8013210: 46bd mov sp, r7 8013212: bd80 pop {r7, pc} 8013214: e000ed04 .word 0xe000ed04 08013218 : /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) { 8013218: b580 push {r7, lr} 801321a: b090 sub sp, #64 @ 0x40 801321c: af00 add r7, sp, #0 801321e: 60f8 str r0, [r7, #12] 8013220: 60b9 str r1, [r7, #8] 8013222: 607a str r2, [r7, #4] 8013224: 603b str r3, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8013226: 68fb ldr r3, [r7, #12] 8013228: 63bb str r3, [r7, #56] @ 0x38 configASSERT( pxQueue ); 801322a: 6bbb ldr r3, [r7, #56] @ 0x38 801322c: 2b00 cmp r3, #0 801322e: d10b bne.n 8013248 __asm volatile 8013230: f04f 0350 mov.w r3, #80 @ 0x50 8013234: f383 8811 msr BASEPRI, r3 8013238: f3bf 8f6f isb sy 801323c: f3bf 8f4f dsb sy 8013240: 62bb str r3, [r7, #40] @ 0x28 } 8013242: bf00 nop 8013244: bf00 nop 8013246: e7fd b.n 8013244 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8013248: 68bb ldr r3, [r7, #8] 801324a: 2b00 cmp r3, #0 801324c: d103 bne.n 8013256 801324e: 6bbb ldr r3, [r7, #56] @ 0x38 8013250: 6c1b ldr r3, [r3, #64] @ 0x40 8013252: 2b00 cmp r3, #0 8013254: d101 bne.n 801325a 8013256: 2301 movs r3, #1 8013258: e000 b.n 801325c 801325a: 2300 movs r3, #0 801325c: 2b00 cmp r3, #0 801325e: d10b bne.n 8013278 __asm volatile 8013260: f04f 0350 mov.w r3, #80 @ 0x50 8013264: f383 8811 msr BASEPRI, r3 8013268: f3bf 8f6f isb sy 801326c: f3bf 8f4f dsb sy 8013270: 627b str r3, [r7, #36] @ 0x24 } 8013272: bf00 nop 8013274: bf00 nop 8013276: e7fd b.n 8013274 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8013278: 683b ldr r3, [r7, #0] 801327a: 2b02 cmp r3, #2 801327c: d103 bne.n 8013286 801327e: 6bbb ldr r3, [r7, #56] @ 0x38 8013280: 6bdb ldr r3, [r3, #60] @ 0x3c 8013282: 2b01 cmp r3, #1 8013284: d101 bne.n 801328a 8013286: 2301 movs r3, #1 8013288: e000 b.n 801328c 801328a: 2300 movs r3, #0 801328c: 2b00 cmp r3, #0 801328e: d10b bne.n 80132a8 __asm volatile 8013290: f04f 0350 mov.w r3, #80 @ 0x50 8013294: f383 8811 msr BASEPRI, r3 8013298: f3bf 8f6f isb sy 801329c: f3bf 8f4f dsb sy 80132a0: 623b str r3, [r7, #32] } 80132a2: bf00 nop 80132a4: bf00 nop 80132a6: e7fd b.n 80132a4 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 80132a8: f002 ff0e bl 80160c8 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile 80132ac: f3ef 8211 mrs r2, BASEPRI 80132b0: f04f 0350 mov.w r3, #80 @ 0x50 80132b4: f383 8811 msr BASEPRI, r3 80132b8: f3bf 8f6f isb sy 80132bc: f3bf 8f4f dsb sy 80132c0: 61fa str r2, [r7, #28] 80132c2: 61bb str r3, [r7, #24] :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; 80132c4: 69fb ldr r3, [r7, #28] /* Similar to xQueueGenericSend, except without blocking if there is no room in the queue. Also don't directly wake a task that was blocked on a queue read, instead return a flag to say whether a context switch is required or not (i.e. has a task with a higher priority than us been woken by this post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 80132c6: 637b str r3, [r7, #52] @ 0x34 { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 80132c8: 6bbb ldr r3, [r7, #56] @ 0x38 80132ca: 6b9a ldr r2, [r3, #56] @ 0x38 80132cc: 6bbb ldr r3, [r7, #56] @ 0x38 80132ce: 6bdb ldr r3, [r3, #60] @ 0x3c 80132d0: 429a cmp r2, r3 80132d2: d302 bcc.n 80132da 80132d4: 683b ldr r3, [r7, #0] 80132d6: 2b02 cmp r3, #2 80132d8: d12f bne.n 801333a { const int8_t cTxLock = pxQueue->cTxLock; 80132da: 6bbb ldr r3, [r7, #56] @ 0x38 80132dc: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80132e0: f887 3033 strb.w r3, [r7, #51] @ 0x33 const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; 80132e4: 6bbb ldr r3, [r7, #56] @ 0x38 80132e6: 6b9b ldr r3, [r3, #56] @ 0x38 80132e8: 62fb str r3, [r7, #44] @ 0x2c /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a semaphore or mutex. That means prvCopyDataToQueue() cannot result in a task disinheriting a priority and prvCopyDataToQueue() can be called here even though the disinherit function does not check if the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 80132ea: 683a ldr r2, [r7, #0] 80132ec: 68b9 ldr r1, [r7, #8] 80132ee: 6bb8 ldr r0, [r7, #56] @ 0x38 80132f0: f000 fabc bl 801386c /* The event list is not altered if the queue is locked. This will be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 80132f4: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33 80132f8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80132fc: d112 bne.n 8013324 } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 80132fe: 6bbb ldr r3, [r7, #56] @ 0x38 8013300: 6a5b ldr r3, [r3, #36] @ 0x24 8013302: 2b00 cmp r3, #0 8013304: d016 beq.n 8013334 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8013306: 6bbb ldr r3, [r7, #56] @ 0x38 8013308: 3324 adds r3, #36 @ 0x24 801330a: 4618 mov r0, r3 801330c: f001 fa7a bl 8014804 8013310: 4603 mov r3, r0 8013312: 2b00 cmp r3, #0 8013314: d00e beq.n 8013334 { /* The task waiting has a higher priority so record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 8013316: 687b ldr r3, [r7, #4] 8013318: 2b00 cmp r3, #0 801331a: d00b beq.n 8013334 { *pxHigherPriorityTaskWoken = pdTRUE; 801331c: 687b ldr r3, [r7, #4] 801331e: 2201 movs r2, #1 8013320: 601a str r2, [r3, #0] 8013322: e007 b.n 8013334 } else { /* Increment the lock count so the task that unlocks the queue knows that data was posted while it was locked. */ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); 8013324: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 8013328: 3301 adds r3, #1 801332a: b2db uxtb r3, r3 801332c: b25a sxtb r2, r3 801332e: 6bbb ldr r3, [r7, #56] @ 0x38 8013330: f883 2045 strb.w r2, [r3, #69] @ 0x45 } xReturn = pdPASS; 8013334: 2301 movs r3, #1 8013336: 63fb str r3, [r7, #60] @ 0x3c { 8013338: e001 b.n 801333e } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 801333a: 2300 movs r3, #0 801333c: 63fb str r3, [r7, #60] @ 0x3c 801333e: 6b7b ldr r3, [r7, #52] @ 0x34 8013340: 617b str r3, [r7, #20] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile 8013342: 697b ldr r3, [r7, #20] 8013344: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } 8013348: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 801334a: 6bfb ldr r3, [r7, #60] @ 0x3c } 801334c: 4618 mov r0, r3 801334e: 3740 adds r7, #64 @ 0x40 8013350: 46bd mov sp, r7 8013352: bd80 pop {r7, pc} 08013354 : return xReturn; } /*-----------------------------------------------------------*/ BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) { 8013354: b580 push {r7, lr} 8013356: b08c sub sp, #48 @ 0x30 8013358: af00 add r7, sp, #0 801335a: 60f8 str r0, [r7, #12] 801335c: 60b9 str r1, [r7, #8] 801335e: 607a str r2, [r7, #4] BaseType_t xEntryTimeSet = pdFALSE; 8013360: 2300 movs r3, #0 8013362: 62fb str r3, [r7, #44] @ 0x2c TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8013364: 68fb ldr r3, [r7, #12] 8013366: 62bb str r3, [r7, #40] @ 0x28 /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); 8013368: 6abb ldr r3, [r7, #40] @ 0x28 801336a: 2b00 cmp r3, #0 801336c: d10b bne.n 8013386 __asm volatile 801336e: f04f 0350 mov.w r3, #80 @ 0x50 8013372: f383 8811 msr BASEPRI, r3 8013376: f3bf 8f6f isb sy 801337a: f3bf 8f4f dsb sy 801337e: 623b str r3, [r7, #32] } 8013380: bf00 nop 8013382: bf00 nop 8013384: e7fd b.n 8013382 /* The buffer into which data is received can only be NULL if the data size is zero (so no data is copied into the buffer. */ configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8013386: 68bb ldr r3, [r7, #8] 8013388: 2b00 cmp r3, #0 801338a: d103 bne.n 8013394 801338c: 6abb ldr r3, [r7, #40] @ 0x28 801338e: 6c1b ldr r3, [r3, #64] @ 0x40 8013390: 2b00 cmp r3, #0 8013392: d101 bne.n 8013398 8013394: 2301 movs r3, #1 8013396: e000 b.n 801339a 8013398: 2300 movs r3, #0 801339a: 2b00 cmp r3, #0 801339c: d10b bne.n 80133b6 __asm volatile 801339e: f04f 0350 mov.w r3, #80 @ 0x50 80133a2: f383 8811 msr BASEPRI, r3 80133a6: f3bf 8f6f isb sy 80133aa: f3bf 8f4f dsb sy 80133ae: 61fb str r3, [r7, #28] } 80133b0: bf00 nop 80133b2: bf00 nop 80133b4: e7fd b.n 80133b2 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 80133b6: f001 fc23 bl 8014c00 80133ba: 4603 mov r3, r0 80133bc: 2b00 cmp r3, #0 80133be: d102 bne.n 80133c6 80133c0: 687b ldr r3, [r7, #4] 80133c2: 2b00 cmp r3, #0 80133c4: d101 bne.n 80133ca 80133c6: 2301 movs r3, #1 80133c8: e000 b.n 80133cc 80133ca: 2300 movs r3, #0 80133cc: 2b00 cmp r3, #0 80133ce: d10b bne.n 80133e8 __asm volatile 80133d0: f04f 0350 mov.w r3, #80 @ 0x50 80133d4: f383 8811 msr BASEPRI, r3 80133d8: f3bf 8f6f isb sy 80133dc: f3bf 8f4f dsb sy 80133e0: 61bb str r3, [r7, #24] } 80133e2: bf00 nop 80133e4: bf00 nop 80133e6: e7fd b.n 80133e4 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 80133e8: f002 fd8e bl 8015f08 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 80133ec: 6abb ldr r3, [r7, #40] @ 0x28 80133ee: 6b9b ldr r3, [r3, #56] @ 0x38 80133f0: 627b str r3, [r7, #36] @ 0x24 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 80133f2: 6a7b ldr r3, [r7, #36] @ 0x24 80133f4: 2b00 cmp r3, #0 80133f6: d01f beq.n 8013438 { /* Data available, remove one item. */ prvCopyDataFromQueue( pxQueue, pvBuffer ); 80133f8: 68b9 ldr r1, [r7, #8] 80133fa: 6ab8 ldr r0, [r7, #40] @ 0x28 80133fc: f000 faa0 bl 8013940 traceQUEUE_RECEIVE( pxQueue ); pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 8013400: 6a7b ldr r3, [r7, #36] @ 0x24 8013402: 1e5a subs r2, r3, #1 8013404: 6abb ldr r3, [r7, #40] @ 0x28 8013406: 639a str r2, [r3, #56] @ 0x38 /* There is now space in the queue, were any tasks waiting to post to the queue? If so, unblock the highest priority waiting task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8013408: 6abb ldr r3, [r7, #40] @ 0x28 801340a: 691b ldr r3, [r3, #16] 801340c: 2b00 cmp r3, #0 801340e: d00f beq.n 8013430 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8013410: 6abb ldr r3, [r7, #40] @ 0x28 8013412: 3310 adds r3, #16 8013414: 4618 mov r0, r3 8013416: f001 f9f5 bl 8014804 801341a: 4603 mov r3, r0 801341c: 2b00 cmp r3, #0 801341e: d007 beq.n 8013430 { queueYIELD_IF_USING_PREEMPTION(); 8013420: 4b3c ldr r3, [pc, #240] @ (8013514 ) 8013422: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8013426: 601a str r2, [r3, #0] 8013428: f3bf 8f4f dsb sy 801342c: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 8013430: f002 fd9c bl 8015f6c return pdPASS; 8013434: 2301 movs r3, #1 8013436: e069 b.n 801350c } else { if( xTicksToWait == ( TickType_t ) 0 ) 8013438: 687b ldr r3, [r7, #4] 801343a: 2b00 cmp r3, #0 801343c: d103 bne.n 8013446 { /* The queue was empty and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 801343e: f002 fd95 bl 8015f6c traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8013442: 2300 movs r3, #0 8013444: e062 b.n 801350c } else if( xEntryTimeSet == pdFALSE ) 8013446: 6afb ldr r3, [r7, #44] @ 0x2c 8013448: 2b00 cmp r3, #0 801344a: d106 bne.n 801345a { /* The queue was empty and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 801344c: f107 0310 add.w r3, r7, #16 8013450: 4618 mov r0, r3 8013452: f001 fa63 bl 801491c xEntryTimeSet = pdTRUE; 8013456: 2301 movs r3, #1 8013458: 62fb str r3, [r7, #44] @ 0x2c /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 801345a: f002 fd87 bl 8015f6c /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 801345e: f000 ff95 bl 801438c prvLockQueue( pxQueue ); 8013462: f002 fd51 bl 8015f08 8013466: 6abb ldr r3, [r7, #40] @ 0x28 8013468: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 801346c: b25b sxtb r3, r3 801346e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8013472: d103 bne.n 801347c 8013474: 6abb ldr r3, [r7, #40] @ 0x28 8013476: 2200 movs r2, #0 8013478: f883 2044 strb.w r2, [r3, #68] @ 0x44 801347c: 6abb ldr r3, [r7, #40] @ 0x28 801347e: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8013482: b25b sxtb r3, r3 8013484: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8013488: d103 bne.n 8013492 801348a: 6abb ldr r3, [r7, #40] @ 0x28 801348c: 2200 movs r2, #0 801348e: f883 2045 strb.w r2, [r3, #69] @ 0x45 8013492: f002 fd6b bl 8015f6c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8013496: 1d3a adds r2, r7, #4 8013498: f107 0310 add.w r3, r7, #16 801349c: 4611 mov r1, r2 801349e: 4618 mov r0, r3 80134a0: f001 fa52 bl 8014948 80134a4: 4603 mov r3, r0 80134a6: 2b00 cmp r3, #0 80134a8: d123 bne.n 80134f2 { /* The timeout has not expired. If the queue is still empty place the task on the list of tasks waiting to receive from the queue. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80134aa: 6ab8 ldr r0, [r7, #40] @ 0x28 80134ac: f000 fac0 bl 8013a30 80134b0: 4603 mov r3, r0 80134b2: 2b00 cmp r3, #0 80134b4: d017 beq.n 80134e6 { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 80134b6: 6abb ldr r3, [r7, #40] @ 0x28 80134b8: 3324 adds r3, #36 @ 0x24 80134ba: 687a ldr r2, [r7, #4] 80134bc: 4611 mov r1, r2 80134be: 4618 mov r0, r3 80134c0: f001 f94e bl 8014760 prvUnlockQueue( pxQueue ); 80134c4: 6ab8 ldr r0, [r7, #40] @ 0x28 80134c6: f000 fa61 bl 801398c if( xTaskResumeAll() == pdFALSE ) 80134ca: f000 ff6d bl 80143a8 80134ce: 4603 mov r3, r0 80134d0: 2b00 cmp r3, #0 80134d2: d189 bne.n 80133e8 { portYIELD_WITHIN_API(); 80134d4: 4b0f ldr r3, [pc, #60] @ (8013514 ) 80134d6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80134da: 601a str r2, [r3, #0] 80134dc: f3bf 8f4f dsb sy 80134e0: f3bf 8f6f isb sy 80134e4: e780 b.n 80133e8 } else { /* The queue contains data again. Loop back to try and read the data. */ prvUnlockQueue( pxQueue ); 80134e6: 6ab8 ldr r0, [r7, #40] @ 0x28 80134e8: f000 fa50 bl 801398c ( void ) xTaskResumeAll(); 80134ec: f000 ff5c bl 80143a8 80134f0: e77a b.n 80133e8 } else { /* Timed out. If there is no data in the queue exit, otherwise loop back and attempt to read the data. */ prvUnlockQueue( pxQueue ); 80134f2: 6ab8 ldr r0, [r7, #40] @ 0x28 80134f4: f000 fa4a bl 801398c ( void ) xTaskResumeAll(); 80134f8: f000 ff56 bl 80143a8 if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80134fc: 6ab8 ldr r0, [r7, #40] @ 0x28 80134fe: f000 fa97 bl 8013a30 8013502: 4603 mov r3, r0 8013504: 2b00 cmp r3, #0 8013506: f43f af6f beq.w 80133e8 { traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 801350a: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 801350c: 4618 mov r0, r3 801350e: 3730 adds r7, #48 @ 0x30 8013510: 46bd mov sp, r7 8013512: bd80 pop {r7, pc} 8013514: e000ed04 .word 0xe000ed04 08013518 : /*-----------------------------------------------------------*/ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) { 8013518: b580 push {r7, lr} 801351a: b08e sub sp, #56 @ 0x38 801351c: af00 add r7, sp, #0 801351e: 6078 str r0, [r7, #4] 8013520: 6039 str r1, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE; 8013522: 2300 movs r3, #0 8013524: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8013526: 687b ldr r3, [r7, #4] 8013528: 62fb str r3, [r7, #44] @ 0x2c #if( configUSE_MUTEXES == 1 ) BaseType_t xInheritanceOccurred = pdFALSE; 801352a: 2300 movs r3, #0 801352c: 633b str r3, [r7, #48] @ 0x30 #endif /* Check the queue pointer is not NULL. */ configASSERT( ( pxQueue ) ); 801352e: 6afb ldr r3, [r7, #44] @ 0x2c 8013530: 2b00 cmp r3, #0 8013532: d10b bne.n 801354c __asm volatile 8013534: f04f 0350 mov.w r3, #80 @ 0x50 8013538: f383 8811 msr BASEPRI, r3 801353c: f3bf 8f6f isb sy 8013540: f3bf 8f4f dsb sy 8013544: 623b str r3, [r7, #32] } 8013546: bf00 nop 8013548: bf00 nop 801354a: e7fd b.n 8013548 /* Check this really is a semaphore, in which case the item size will be 0. */ configASSERT( pxQueue->uxItemSize == 0 ); 801354c: 6afb ldr r3, [r7, #44] @ 0x2c 801354e: 6c1b ldr r3, [r3, #64] @ 0x40 8013550: 2b00 cmp r3, #0 8013552: d00b beq.n 801356c __asm volatile 8013554: f04f 0350 mov.w r3, #80 @ 0x50 8013558: f383 8811 msr BASEPRI, r3 801355c: f3bf 8f6f isb sy 8013560: f3bf 8f4f dsb sy 8013564: 61fb str r3, [r7, #28] } 8013566: bf00 nop 8013568: bf00 nop 801356a: e7fd b.n 8013568 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 801356c: f001 fb48 bl 8014c00 8013570: 4603 mov r3, r0 8013572: 2b00 cmp r3, #0 8013574: d102 bne.n 801357c 8013576: 683b ldr r3, [r7, #0] 8013578: 2b00 cmp r3, #0 801357a: d101 bne.n 8013580 801357c: 2301 movs r3, #1 801357e: e000 b.n 8013582 8013580: 2300 movs r3, #0 8013582: 2b00 cmp r3, #0 8013584: d10b bne.n 801359e __asm volatile 8013586: f04f 0350 mov.w r3, #80 @ 0x50 801358a: f383 8811 msr BASEPRI, r3 801358e: f3bf 8f6f isb sy 8013592: f3bf 8f4f dsb sy 8013596: 61bb str r3, [r7, #24] } 8013598: bf00 nop 801359a: bf00 nop 801359c: e7fd b.n 801359a /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 801359e: f002 fcb3 bl 8015f08 { /* Semaphores are queues with an item size of 0, and where the number of messages in the queue is the semaphore's count value. */ const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; 80135a2: 6afb ldr r3, [r7, #44] @ 0x2c 80135a4: 6b9b ldr r3, [r3, #56] @ 0x38 80135a6: 62bb str r3, [r7, #40] @ 0x28 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxSemaphoreCount > ( UBaseType_t ) 0 ) 80135a8: 6abb ldr r3, [r7, #40] @ 0x28 80135aa: 2b00 cmp r3, #0 80135ac: d024 beq.n 80135f8 { traceQUEUE_RECEIVE( pxQueue ); /* Semaphores are queues with a data size of zero and where the messages waiting is the semaphore's count. Reduce the count. */ pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; 80135ae: 6abb ldr r3, [r7, #40] @ 0x28 80135b0: 1e5a subs r2, r3, #1 80135b2: 6afb ldr r3, [r7, #44] @ 0x2c 80135b4: 639a str r2, [r3, #56] @ 0x38 #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 80135b6: 6afb ldr r3, [r7, #44] @ 0x2c 80135b8: 681b ldr r3, [r3, #0] 80135ba: 2b00 cmp r3, #0 80135bc: d104 bne.n 80135c8 { /* Record the information required to implement priority inheritance should it become necessary. */ pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); 80135be: f001 fc99 bl 8014ef4 80135c2: 4602 mov r2, r0 80135c4: 6afb ldr r3, [r7, #44] @ 0x2c 80135c6: 609a str r2, [r3, #8] } #endif /* configUSE_MUTEXES */ /* Check to see if other tasks are blocked waiting to give the semaphore, and if so, unblock the highest priority such task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80135c8: 6afb ldr r3, [r7, #44] @ 0x2c 80135ca: 691b ldr r3, [r3, #16] 80135cc: 2b00 cmp r3, #0 80135ce: d00f beq.n 80135f0 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80135d0: 6afb ldr r3, [r7, #44] @ 0x2c 80135d2: 3310 adds r3, #16 80135d4: 4618 mov r0, r3 80135d6: f001 f915 bl 8014804 80135da: 4603 mov r3, r0 80135dc: 2b00 cmp r3, #0 80135de: d007 beq.n 80135f0 { queueYIELD_IF_USING_PREEMPTION(); 80135e0: 4b54 ldr r3, [pc, #336] @ (8013734 ) 80135e2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80135e6: 601a str r2, [r3, #0] 80135e8: f3bf 8f4f dsb sy 80135ec: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 80135f0: f002 fcbc bl 8015f6c return pdPASS; 80135f4: 2301 movs r3, #1 80135f6: e098 b.n 801372a } else { if( xTicksToWait == ( TickType_t ) 0 ) 80135f8: 683b ldr r3, [r7, #0] 80135fa: 2b00 cmp r3, #0 80135fc: d112 bne.n 8013624 /* For inheritance to have occurred there must have been an initial timeout, and an adjusted timeout cannot become 0, as if it were 0 the function would have exited. */ #if( configUSE_MUTEXES == 1 ) { configASSERT( xInheritanceOccurred == pdFALSE ); 80135fe: 6b3b ldr r3, [r7, #48] @ 0x30 8013600: 2b00 cmp r3, #0 8013602: d00b beq.n 801361c __asm volatile 8013604: f04f 0350 mov.w r3, #80 @ 0x50 8013608: f383 8811 msr BASEPRI, r3 801360c: f3bf 8f6f isb sy 8013610: f3bf 8f4f dsb sy 8013614: 617b str r3, [r7, #20] } 8013616: bf00 nop 8013618: bf00 nop 801361a: e7fd b.n 8013618 } #endif /* configUSE_MUTEXES */ /* The semaphore count was 0 and no block time is specified (or the block time has expired) so exit now. */ taskEXIT_CRITICAL(); 801361c: f002 fca6 bl 8015f6c traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8013620: 2300 movs r3, #0 8013622: e082 b.n 801372a } else if( xEntryTimeSet == pdFALSE ) 8013624: 6b7b ldr r3, [r7, #52] @ 0x34 8013626: 2b00 cmp r3, #0 8013628: d106 bne.n 8013638 { /* The semaphore count was 0 and a block time was specified so configure the timeout structure ready to block. */ vTaskInternalSetTimeOutState( &xTimeOut ); 801362a: f107 030c add.w r3, r7, #12 801362e: 4618 mov r0, r3 8013630: f001 f974 bl 801491c xEntryTimeSet = pdTRUE; 8013634: 2301 movs r3, #1 8013636: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8013638: f002 fc98 bl 8015f6c /* Interrupts and other tasks can give to and take from the semaphore now the critical section has been exited. */ vTaskSuspendAll(); 801363c: f000 fea6 bl 801438c prvLockQueue( pxQueue ); 8013640: f002 fc62 bl 8015f08 8013644: 6afb ldr r3, [r7, #44] @ 0x2c 8013646: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 801364a: b25b sxtb r3, r3 801364c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8013650: d103 bne.n 801365a 8013652: 6afb ldr r3, [r7, #44] @ 0x2c 8013654: 2200 movs r2, #0 8013656: f883 2044 strb.w r2, [r3, #68] @ 0x44 801365a: 6afb ldr r3, [r7, #44] @ 0x2c 801365c: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8013660: b25b sxtb r3, r3 8013662: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8013666: d103 bne.n 8013670 8013668: 6afb ldr r3, [r7, #44] @ 0x2c 801366a: 2200 movs r2, #0 801366c: f883 2045 strb.w r2, [r3, #69] @ 0x45 8013670: f002 fc7c bl 8015f6c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8013674: 463a mov r2, r7 8013676: f107 030c add.w r3, r7, #12 801367a: 4611 mov r1, r2 801367c: 4618 mov r0, r3 801367e: f001 f963 bl 8014948 8013682: 4603 mov r3, r0 8013684: 2b00 cmp r3, #0 8013686: d132 bne.n 80136ee { /* A block time is specified and not expired. If the semaphore count is 0 then enter the Blocked state to wait for a semaphore to become available. As semaphores are implemented with queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8013688: 6af8 ldr r0, [r7, #44] @ 0x2c 801368a: f000 f9d1 bl 8013a30 801368e: 4603 mov r3, r0 8013690: 2b00 cmp r3, #0 8013692: d026 beq.n 80136e2 { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8013694: 6afb ldr r3, [r7, #44] @ 0x2c 8013696: 681b ldr r3, [r3, #0] 8013698: 2b00 cmp r3, #0 801369a: d109 bne.n 80136b0 { taskENTER_CRITICAL(); 801369c: f002 fc34 bl 8015f08 { xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); 80136a0: 6afb ldr r3, [r7, #44] @ 0x2c 80136a2: 689b ldr r3, [r3, #8] 80136a4: 4618 mov r0, r3 80136a6: f001 fac9 bl 8014c3c 80136aa: 6338 str r0, [r7, #48] @ 0x30 } taskEXIT_CRITICAL(); 80136ac: f002 fc5e bl 8015f6c mtCOVERAGE_TEST_MARKER(); } } #endif vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 80136b0: 6afb ldr r3, [r7, #44] @ 0x2c 80136b2: 3324 adds r3, #36 @ 0x24 80136b4: 683a ldr r2, [r7, #0] 80136b6: 4611 mov r1, r2 80136b8: 4618 mov r0, r3 80136ba: f001 f851 bl 8014760 prvUnlockQueue( pxQueue ); 80136be: 6af8 ldr r0, [r7, #44] @ 0x2c 80136c0: f000 f964 bl 801398c if( xTaskResumeAll() == pdFALSE ) 80136c4: f000 fe70 bl 80143a8 80136c8: 4603 mov r3, r0 80136ca: 2b00 cmp r3, #0 80136cc: f47f af67 bne.w 801359e { portYIELD_WITHIN_API(); 80136d0: 4b18 ldr r3, [pc, #96] @ (8013734 ) 80136d2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80136d6: 601a str r2, [r3, #0] 80136d8: f3bf 8f4f dsb sy 80136dc: f3bf 8f6f isb sy 80136e0: e75d b.n 801359e } else { /* There was no timeout and the semaphore count was not 0, so attempt to take the semaphore again. */ prvUnlockQueue( pxQueue ); 80136e2: 6af8 ldr r0, [r7, #44] @ 0x2c 80136e4: f000 f952 bl 801398c ( void ) xTaskResumeAll(); 80136e8: f000 fe5e bl 80143a8 80136ec: e757 b.n 801359e } } else { /* Timed out. */ prvUnlockQueue( pxQueue ); 80136ee: 6af8 ldr r0, [r7, #44] @ 0x2c 80136f0: f000 f94c bl 801398c ( void ) xTaskResumeAll(); 80136f4: f000 fe58 bl 80143a8 /* If the semaphore count is 0 exit now as the timeout has expired. Otherwise return to attempt to take the semaphore that is known to be available. As semaphores are implemented by queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80136f8: 6af8 ldr r0, [r7, #44] @ 0x2c 80136fa: f000 f999 bl 8013a30 80136fe: 4603 mov r3, r0 8013700: 2b00 cmp r3, #0 8013702: f43f af4c beq.w 801359e #if ( configUSE_MUTEXES == 1 ) { /* xInheritanceOccurred could only have be set if pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to test the mutex type again to check it is actually a mutex. */ if( xInheritanceOccurred != pdFALSE ) 8013706: 6b3b ldr r3, [r7, #48] @ 0x30 8013708: 2b00 cmp r3, #0 801370a: d00d beq.n 8013728 { taskENTER_CRITICAL(); 801370c: f002 fbfc bl 8015f08 /* This task blocking on the mutex caused another task to inherit this task's priority. Now this task has timed out the priority should be disinherited again, but only as low as the next highest priority task that is waiting for the same mutex. */ uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); 8013710: 6af8 ldr r0, [r7, #44] @ 0x2c 8013712: f000 f893 bl 801383c 8013716: 6278 str r0, [r7, #36] @ 0x24 vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); 8013718: 6afb ldr r3, [r7, #44] @ 0x2c 801371a: 689b ldr r3, [r3, #8] 801371c: 6a79 ldr r1, [r7, #36] @ 0x24 801371e: 4618 mov r0, r3 8013720: f001 fb64 bl 8014dec } taskEXIT_CRITICAL(); 8013724: f002 fc22 bl 8015f6c } } #endif /* configUSE_MUTEXES */ traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8013728: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 801372a: 4618 mov r0, r3 801372c: 3738 adds r7, #56 @ 0x38 801372e: 46bd mov sp, r7 8013730: bd80 pop {r7, pc} 8013732: bf00 nop 8013734: e000ed04 .word 0xe000ed04 08013738 : } /*lint -restore */ } /*-----------------------------------------------------------*/ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) { 8013738: b580 push {r7, lr} 801373a: b08e sub sp, #56 @ 0x38 801373c: af00 add r7, sp, #0 801373e: 60f8 str r0, [r7, #12] 8013740: 60b9 str r1, [r7, #8] 8013742: 607a str r2, [r7, #4] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8013744: 68fb ldr r3, [r7, #12] 8013746: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 8013748: 6b3b ldr r3, [r7, #48] @ 0x30 801374a: 2b00 cmp r3, #0 801374c: d10b bne.n 8013766 __asm volatile 801374e: f04f 0350 mov.w r3, #80 @ 0x50 8013752: f383 8811 msr BASEPRI, r3 8013756: f3bf 8f6f isb sy 801375a: f3bf 8f4f dsb sy 801375e: 623b str r3, [r7, #32] } 8013760: bf00 nop 8013762: bf00 nop 8013764: e7fd b.n 8013762 configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8013766: 68bb ldr r3, [r7, #8] 8013768: 2b00 cmp r3, #0 801376a: d103 bne.n 8013774 801376c: 6b3b ldr r3, [r7, #48] @ 0x30 801376e: 6c1b ldr r3, [r3, #64] @ 0x40 8013770: 2b00 cmp r3, #0 8013772: d101 bne.n 8013778 8013774: 2301 movs r3, #1 8013776: e000 b.n 801377a 8013778: 2300 movs r3, #0 801377a: 2b00 cmp r3, #0 801377c: d10b bne.n 8013796 __asm volatile 801377e: f04f 0350 mov.w r3, #80 @ 0x50 8013782: f383 8811 msr BASEPRI, r3 8013786: f3bf 8f6f isb sy 801378a: f3bf 8f4f dsb sy 801378e: 61fb str r3, [r7, #28] } 8013790: bf00 nop 8013792: bf00 nop 8013794: e7fd b.n 8013792 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8013796: f002 fc97 bl 80160c8 __asm volatile 801379a: f3ef 8211 mrs r2, BASEPRI 801379e: f04f 0350 mov.w r3, #80 @ 0x50 80137a2: f383 8811 msr BASEPRI, r3 80137a6: f3bf 8f6f isb sy 80137aa: f3bf 8f4f dsb sy 80137ae: 61ba str r2, [r7, #24] 80137b0: 617b str r3, [r7, #20] return ulOriginalBASEPRI; 80137b2: 69bb ldr r3, [r7, #24] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 80137b4: 62fb str r3, [r7, #44] @ 0x2c { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 80137b6: 6b3b ldr r3, [r7, #48] @ 0x30 80137b8: 6b9b ldr r3, [r3, #56] @ 0x38 80137ba: 62bb str r3, [r7, #40] @ 0x28 /* Cannot block in an ISR, so check there is data available. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 80137bc: 6abb ldr r3, [r7, #40] @ 0x28 80137be: 2b00 cmp r3, #0 80137c0: d02f beq.n 8013822 { const int8_t cRxLock = pxQueue->cRxLock; 80137c2: 6b3b ldr r3, [r7, #48] @ 0x30 80137c4: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80137c8: f887 3027 strb.w r3, [r7, #39] @ 0x27 traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); prvCopyDataFromQueue( pxQueue, pvBuffer ); 80137cc: 68b9 ldr r1, [r7, #8] 80137ce: 6b38 ldr r0, [r7, #48] @ 0x30 80137d0: f000 f8b6 bl 8013940 pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 80137d4: 6abb ldr r3, [r7, #40] @ 0x28 80137d6: 1e5a subs r2, r3, #1 80137d8: 6b3b ldr r3, [r7, #48] @ 0x30 80137da: 639a str r2, [r3, #56] @ 0x38 /* If the queue is locked the event list will not be modified. Instead update the lock count so the task that unlocks the queue will know that an ISR has removed data while the queue was locked. */ if( cRxLock == queueUNLOCKED ) 80137dc: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27 80137e0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80137e4: d112 bne.n 801380c { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80137e6: 6b3b ldr r3, [r7, #48] @ 0x30 80137e8: 691b ldr r3, [r3, #16] 80137ea: 2b00 cmp r3, #0 80137ec: d016 beq.n 801381c { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80137ee: 6b3b ldr r3, [r7, #48] @ 0x30 80137f0: 3310 adds r3, #16 80137f2: 4618 mov r0, r3 80137f4: f001 f806 bl 8014804 80137f8: 4603 mov r3, r0 80137fa: 2b00 cmp r3, #0 80137fc: d00e beq.n 801381c { /* The task waiting has a higher priority than us so force a context switch. */ if( pxHigherPriorityTaskWoken != NULL ) 80137fe: 687b ldr r3, [r7, #4] 8013800: 2b00 cmp r3, #0 8013802: d00b beq.n 801381c { *pxHigherPriorityTaskWoken = pdTRUE; 8013804: 687b ldr r3, [r7, #4] 8013806: 2201 movs r2, #1 8013808: 601a str r2, [r3, #0] 801380a: e007 b.n 801381c } else { /* Increment the lock count so the task that unlocks the queue knows that data was removed while it was locked. */ pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 ); 801380c: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8013810: 3301 adds r3, #1 8013812: b2db uxtb r3, r3 8013814: b25a sxtb r2, r3 8013816: 6b3b ldr r3, [r7, #48] @ 0x30 8013818: f883 2044 strb.w r2, [r3, #68] @ 0x44 } xReturn = pdPASS; 801381c: 2301 movs r3, #1 801381e: 637b str r3, [r7, #52] @ 0x34 8013820: e001 b.n 8013826 } else { xReturn = pdFAIL; 8013822: 2300 movs r3, #0 8013824: 637b str r3, [r7, #52] @ 0x34 8013826: 6afb ldr r3, [r7, #44] @ 0x2c 8013828: 613b str r3, [r7, #16] __asm volatile 801382a: 693b ldr r3, [r7, #16] 801382c: f383 8811 msr BASEPRI, r3 } 8013830: bf00 nop traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 8013832: 6b7b ldr r3, [r7, #52] @ 0x34 } 8013834: 4618 mov r0, r3 8013836: 3738 adds r7, #56 @ 0x38 8013838: 46bd mov sp, r7 801383a: bd80 pop {r7, pc} 0801383c : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) { 801383c: b480 push {r7} 801383e: b085 sub sp, #20 8013840: af00 add r7, sp, #0 8013842: 6078 str r0, [r7, #4] priority, but the waiting task times out, then the holder should disinherit the priority - but only down to the highest priority of any other tasks that are waiting for the same mutex. For this purpose, return the priority of the highest priority task that is waiting for the mutex. */ if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) 8013844: 687b ldr r3, [r7, #4] 8013846: 6a5b ldr r3, [r3, #36] @ 0x24 8013848: 2b00 cmp r3, #0 801384a: d006 beq.n 801385a { uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); 801384c: 687b ldr r3, [r7, #4] 801384e: 6b1b ldr r3, [r3, #48] @ 0x30 8013850: 681b ldr r3, [r3, #0] 8013852: f1c3 0338 rsb r3, r3, #56 @ 0x38 8013856: 60fb str r3, [r7, #12] 8013858: e001 b.n 801385e } else { uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; 801385a: 2300 movs r3, #0 801385c: 60fb str r3, [r7, #12] } return uxHighestPriorityOfWaitingTasks; 801385e: 68fb ldr r3, [r7, #12] } 8013860: 4618 mov r0, r3 8013862: 3714 adds r7, #20 8013864: 46bd mov sp, r7 8013866: f85d 7b04 ldr.w r7, [sp], #4 801386a: 4770 bx lr 0801386c : #endif /* configUSE_MUTEXES */ /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) { 801386c: b580 push {r7, lr} 801386e: b086 sub sp, #24 8013870: af00 add r7, sp, #0 8013872: 60f8 str r0, [r7, #12] 8013874: 60b9 str r1, [r7, #8] 8013876: 607a str r2, [r7, #4] BaseType_t xReturn = pdFALSE; 8013878: 2300 movs r3, #0 801387a: 617b str r3, [r7, #20] UBaseType_t uxMessagesWaiting; /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; 801387c: 68fb ldr r3, [r7, #12] 801387e: 6b9b ldr r3, [r3, #56] @ 0x38 8013880: 613b str r3, [r7, #16] if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) 8013882: 68fb ldr r3, [r7, #12] 8013884: 6c1b ldr r3, [r3, #64] @ 0x40 8013886: 2b00 cmp r3, #0 8013888: d10d bne.n 80138a6 { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 801388a: 68fb ldr r3, [r7, #12] 801388c: 681b ldr r3, [r3, #0] 801388e: 2b00 cmp r3, #0 8013890: d14d bne.n 801392e { /* The mutex is no longer being held. */ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); 8013892: 68fb ldr r3, [r7, #12] 8013894: 689b ldr r3, [r3, #8] 8013896: 4618 mov r0, r3 8013898: f001 fa38 bl 8014d0c 801389c: 6178 str r0, [r7, #20] pxQueue->u.xSemaphore.xMutexHolder = NULL; 801389e: 68fb ldr r3, [r7, #12] 80138a0: 2200 movs r2, #0 80138a2: 609a str r2, [r3, #8] 80138a4: e043 b.n 801392e mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_MUTEXES */ } else if( xPosition == queueSEND_TO_BACK ) 80138a6: 687b ldr r3, [r7, #4] 80138a8: 2b00 cmp r3, #0 80138aa: d119 bne.n 80138e0 { ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 80138ac: 68fb ldr r3, [r7, #12] 80138ae: 6858 ldr r0, [r3, #4] 80138b0: 68fb ldr r3, [r7, #12] 80138b2: 6c1b ldr r3, [r3, #64] @ 0x40 80138b4: 461a mov r2, r3 80138b6: 68b9 ldr r1, [r7, #8] 80138b8: f003 f81f bl 80168fa pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 80138bc: 68fb ldr r3, [r7, #12] 80138be: 685a ldr r2, [r3, #4] 80138c0: 68fb ldr r3, [r7, #12] 80138c2: 6c1b ldr r3, [r3, #64] @ 0x40 80138c4: 441a add r2, r3 80138c6: 68fb ldr r3, [r7, #12] 80138c8: 605a str r2, [r3, #4] if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 80138ca: 68fb ldr r3, [r7, #12] 80138cc: 685a ldr r2, [r3, #4] 80138ce: 68fb ldr r3, [r7, #12] 80138d0: 689b ldr r3, [r3, #8] 80138d2: 429a cmp r2, r3 80138d4: d32b bcc.n 801392e { pxQueue->pcWriteTo = pxQueue->pcHead; 80138d6: 68fb ldr r3, [r7, #12] 80138d8: 681a ldr r2, [r3, #0] 80138da: 68fb ldr r3, [r7, #12] 80138dc: 605a str r2, [r3, #4] 80138de: e026 b.n 801392e mtCOVERAGE_TEST_MARKER(); } } else { ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ 80138e0: 68fb ldr r3, [r7, #12] 80138e2: 68d8 ldr r0, [r3, #12] 80138e4: 68fb ldr r3, [r7, #12] 80138e6: 6c1b ldr r3, [r3, #64] @ 0x40 80138e8: 461a mov r2, r3 80138ea: 68b9 ldr r1, [r7, #8] 80138ec: f003 f805 bl 80168fa pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; 80138f0: 68fb ldr r3, [r7, #12] 80138f2: 68da ldr r2, [r3, #12] 80138f4: 68fb ldr r3, [r7, #12] 80138f6: 6c1b ldr r3, [r3, #64] @ 0x40 80138f8: 425b negs r3, r3 80138fa: 441a add r2, r3 80138fc: 68fb ldr r3, [r7, #12] 80138fe: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 8013900: 68fb ldr r3, [r7, #12] 8013902: 68da ldr r2, [r3, #12] 8013904: 68fb ldr r3, [r7, #12] 8013906: 681b ldr r3, [r3, #0] 8013908: 429a cmp r2, r3 801390a: d207 bcs.n 801391c { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); 801390c: 68fb ldr r3, [r7, #12] 801390e: 689a ldr r2, [r3, #8] 8013910: 68fb ldr r3, [r7, #12] 8013912: 6c1b ldr r3, [r3, #64] @ 0x40 8013914: 425b negs r3, r3 8013916: 441a add r2, r3 8013918: 68fb ldr r3, [r7, #12] 801391a: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } if( xPosition == queueOVERWRITE ) 801391c: 687b ldr r3, [r7, #4] 801391e: 2b02 cmp r3, #2 8013920: d105 bne.n 801392e { if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 8013922: 693b ldr r3, [r7, #16] 8013924: 2b00 cmp r3, #0 8013926: d002 beq.n 801392e { /* An item is not being added but overwritten, so subtract one from the recorded number of items in the queue so when one is added again below the number of recorded items remains correct. */ --uxMessagesWaiting; 8013928: 693b ldr r3, [r7, #16] 801392a: 3b01 subs r3, #1 801392c: 613b str r3, [r7, #16] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 801392e: 693b ldr r3, [r7, #16] 8013930: 1c5a adds r2, r3, #1 8013932: 68fb ldr r3, [r7, #12] 8013934: 639a str r2, [r3, #56] @ 0x38 return xReturn; 8013936: 697b ldr r3, [r7, #20] } 8013938: 4618 mov r0, r3 801393a: 3718 adds r7, #24 801393c: 46bd mov sp, r7 801393e: bd80 pop {r7, pc} 08013940 : /*-----------------------------------------------------------*/ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) { 8013940: b580 push {r7, lr} 8013942: b082 sub sp, #8 8013944: af00 add r7, sp, #0 8013946: 6078 str r0, [r7, #4] 8013948: 6039 str r1, [r7, #0] if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) 801394a: 687b ldr r3, [r7, #4] 801394c: 6c1b ldr r3, [r3, #64] @ 0x40 801394e: 2b00 cmp r3, #0 8013950: d018 beq.n 8013984 { pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 8013952: 687b ldr r3, [r7, #4] 8013954: 68da ldr r2, [r3, #12] 8013956: 687b ldr r3, [r7, #4] 8013958: 6c1b ldr r3, [r3, #64] @ 0x40 801395a: 441a add r2, r3 801395c: 687b ldr r3, [r7, #4] 801395e: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 8013960: 687b ldr r3, [r7, #4] 8013962: 68da ldr r2, [r3, #12] 8013964: 687b ldr r3, [r7, #4] 8013966: 689b ldr r3, [r3, #8] 8013968: 429a cmp r2, r3 801396a: d303 bcc.n 8013974 { pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; 801396c: 687b ldr r3, [r7, #4] 801396e: 681a ldr r2, [r3, #0] 8013970: 687b ldr r3, [r7, #4] 8013972: 60da str r2, [r3, #12] } else { mtCOVERAGE_TEST_MARKER(); } ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 8013974: 687b ldr r3, [r7, #4] 8013976: 68d9 ldr r1, [r3, #12] 8013978: 687b ldr r3, [r7, #4] 801397a: 6c1b ldr r3, [r3, #64] @ 0x40 801397c: 461a mov r2, r3 801397e: 6838 ldr r0, [r7, #0] 8013980: f002 ffbb bl 80168fa } } 8013984: bf00 nop 8013986: 3708 adds r7, #8 8013988: 46bd mov sp, r7 801398a: bd80 pop {r7, pc} 0801398c : /*-----------------------------------------------------------*/ static void prvUnlockQueue( Queue_t * const pxQueue ) { 801398c: b580 push {r7, lr} 801398e: b084 sub sp, #16 8013990: af00 add r7, sp, #0 8013992: 6078 str r0, [r7, #4] /* The lock counts contains the number of extra data items placed or removed from the queue while the queue was locked. When a queue is locked items can be added or removed, but the event lists cannot be updated. */ taskENTER_CRITICAL(); 8013994: f002 fab8 bl 8015f08 { int8_t cTxLock = pxQueue->cTxLock; 8013998: 687b ldr r3, [r7, #4] 801399a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 801399e: 73fb strb r3, [r7, #15] /* See if data was added to the queue while it was locked. */ while( cTxLock > queueLOCKED_UNMODIFIED ) 80139a0: e011 b.n 80139c6 } #else /* configUSE_QUEUE_SETS */ { /* Tasks that are removed from the event list will get added to the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 80139a2: 687b ldr r3, [r7, #4] 80139a4: 6a5b ldr r3, [r3, #36] @ 0x24 80139a6: 2b00 cmp r3, #0 80139a8: d012 beq.n 80139d0 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 80139aa: 687b ldr r3, [r7, #4] 80139ac: 3324 adds r3, #36 @ 0x24 80139ae: 4618 mov r0, r3 80139b0: f000 ff28 bl 8014804 80139b4: 4603 mov r3, r0 80139b6: 2b00 cmp r3, #0 80139b8: d001 beq.n 80139be { /* The task waiting has a higher priority so record that a context switch is required. */ vTaskMissedYield(); 80139ba: f001 f829 bl 8014a10 break; } } #endif /* configUSE_QUEUE_SETS */ --cTxLock; 80139be: 7bfb ldrb r3, [r7, #15] 80139c0: 3b01 subs r3, #1 80139c2: b2db uxtb r3, r3 80139c4: 73fb strb r3, [r7, #15] while( cTxLock > queueLOCKED_UNMODIFIED ) 80139c6: f997 300f ldrsb.w r3, [r7, #15] 80139ca: 2b00 cmp r3, #0 80139cc: dce9 bgt.n 80139a2 80139ce: e000 b.n 80139d2 break; 80139d0: bf00 nop } pxQueue->cTxLock = queueUNLOCKED; 80139d2: 687b ldr r3, [r7, #4] 80139d4: 22ff movs r2, #255 @ 0xff 80139d6: f883 2045 strb.w r2, [r3, #69] @ 0x45 } taskEXIT_CRITICAL(); 80139da: f002 fac7 bl 8015f6c /* Do the same for the Rx lock. */ taskENTER_CRITICAL(); 80139de: f002 fa93 bl 8015f08 { int8_t cRxLock = pxQueue->cRxLock; 80139e2: 687b ldr r3, [r7, #4] 80139e4: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80139e8: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 80139ea: e011 b.n 8013a10 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80139ec: 687b ldr r3, [r7, #4] 80139ee: 691b ldr r3, [r3, #16] 80139f0: 2b00 cmp r3, #0 80139f2: d012 beq.n 8013a1a { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80139f4: 687b ldr r3, [r7, #4] 80139f6: 3310 adds r3, #16 80139f8: 4618 mov r0, r3 80139fa: f000 ff03 bl 8014804 80139fe: 4603 mov r3, r0 8013a00: 2b00 cmp r3, #0 8013a02: d001 beq.n 8013a08 { vTaskMissedYield(); 8013a04: f001 f804 bl 8014a10 else { mtCOVERAGE_TEST_MARKER(); } --cRxLock; 8013a08: 7bbb ldrb r3, [r7, #14] 8013a0a: 3b01 subs r3, #1 8013a0c: b2db uxtb r3, r3 8013a0e: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 8013a10: f997 300e ldrsb.w r3, [r7, #14] 8013a14: 2b00 cmp r3, #0 8013a16: dce9 bgt.n 80139ec 8013a18: e000 b.n 8013a1c } else { break; 8013a1a: bf00 nop } } pxQueue->cRxLock = queueUNLOCKED; 8013a1c: 687b ldr r3, [r7, #4] 8013a1e: 22ff movs r2, #255 @ 0xff 8013a20: f883 2044 strb.w r2, [r3, #68] @ 0x44 } taskEXIT_CRITICAL(); 8013a24: f002 faa2 bl 8015f6c } 8013a28: bf00 nop 8013a2a: 3710 adds r7, #16 8013a2c: 46bd mov sp, r7 8013a2e: bd80 pop {r7, pc} 08013a30 : /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) { 8013a30: b580 push {r7, lr} 8013a32: b084 sub sp, #16 8013a34: af00 add r7, sp, #0 8013a36: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8013a38: f002 fa66 bl 8015f08 { if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) 8013a3c: 687b ldr r3, [r7, #4] 8013a3e: 6b9b ldr r3, [r3, #56] @ 0x38 8013a40: 2b00 cmp r3, #0 8013a42: d102 bne.n 8013a4a { xReturn = pdTRUE; 8013a44: 2301 movs r3, #1 8013a46: 60fb str r3, [r7, #12] 8013a48: e001 b.n 8013a4e } else { xReturn = pdFALSE; 8013a4a: 2300 movs r3, #0 8013a4c: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8013a4e: f002 fa8d bl 8015f6c return xReturn; 8013a52: 68fb ldr r3, [r7, #12] } 8013a54: 4618 mov r0, r3 8013a56: 3710 adds r7, #16 8013a58: 46bd mov sp, r7 8013a5a: bd80 pop {r7, pc} 08013a5c : return xReturn; } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) { 8013a5c: b580 push {r7, lr} 8013a5e: b084 sub sp, #16 8013a60: af00 add r7, sp, #0 8013a62: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8013a64: f002 fa50 bl 8015f08 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) 8013a68: 687b ldr r3, [r7, #4] 8013a6a: 6b9a ldr r2, [r3, #56] @ 0x38 8013a6c: 687b ldr r3, [r7, #4] 8013a6e: 6bdb ldr r3, [r3, #60] @ 0x3c 8013a70: 429a cmp r2, r3 8013a72: d102 bne.n 8013a7a { xReturn = pdTRUE; 8013a74: 2301 movs r3, #1 8013a76: 60fb str r3, [r7, #12] 8013a78: e001 b.n 8013a7e } else { xReturn = pdFALSE; 8013a7a: 2300 movs r3, #0 8013a7c: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8013a7e: f002 fa75 bl 8015f6c return xReturn; 8013a82: 68fb ldr r3, [r7, #12] } 8013a84: 4618 mov r0, r3 8013a86: 3710 adds r7, #16 8013a88: 46bd mov sp, r7 8013a8a: bd80 pop {r7, pc} 08013a8c : /*-----------------------------------------------------------*/ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ { 8013a8c: b480 push {r7} 8013a8e: b085 sub sp, #20 8013a90: af00 add r7, sp, #0 8013a92: 6078 str r0, [r7, #4] 8013a94: 6039 str r1, [r7, #0] UBaseType_t ux; /* See if there is an empty space in the registry. A NULL name denotes a free slot. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8013a96: 2300 movs r3, #0 8013a98: 60fb str r3, [r7, #12] 8013a9a: e014 b.n 8013ac6 { if( xQueueRegistry[ ux ].pcQueueName == NULL ) 8013a9c: 4a0f ldr r2, [pc, #60] @ (8013adc ) 8013a9e: 68fb ldr r3, [r7, #12] 8013aa0: f852 3033 ldr.w r3, [r2, r3, lsl #3] 8013aa4: 2b00 cmp r3, #0 8013aa6: d10b bne.n 8013ac0 { /* Store the information on this queue. */ xQueueRegistry[ ux ].pcQueueName = pcQueueName; 8013aa8: 490c ldr r1, [pc, #48] @ (8013adc ) 8013aaa: 68fb ldr r3, [r7, #12] 8013aac: 683a ldr r2, [r7, #0] 8013aae: f841 2033 str.w r2, [r1, r3, lsl #3] xQueueRegistry[ ux ].xHandle = xQueue; 8013ab2: 4a0a ldr r2, [pc, #40] @ (8013adc ) 8013ab4: 68fb ldr r3, [r7, #12] 8013ab6: 00db lsls r3, r3, #3 8013ab8: 4413 add r3, r2 8013aba: 687a ldr r2, [r7, #4] 8013abc: 605a str r2, [r3, #4] traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); break; 8013abe: e006 b.n 8013ace for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8013ac0: 68fb ldr r3, [r7, #12] 8013ac2: 3301 adds r3, #1 8013ac4: 60fb str r3, [r7, #12] 8013ac6: 68fb ldr r3, [r7, #12] 8013ac8: 2b07 cmp r3, #7 8013aca: d9e7 bls.n 8013a9c else { mtCOVERAGE_TEST_MARKER(); } } } 8013acc: bf00 nop 8013ace: bf00 nop 8013ad0: 3714 adds r7, #20 8013ad2: 46bd mov sp, r7 8013ad4: f85d 7b04 ldr.w r7, [sp], #4 8013ad8: 4770 bx lr 8013ada: bf00 nop 8013adc: 24002564 .word 0x24002564 08013ae0 : /*-----------------------------------------------------------*/ #if ( configUSE_TIMERS == 1 ) void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 8013ae0: b580 push {r7, lr} 8013ae2: b086 sub sp, #24 8013ae4: af00 add r7, sp, #0 8013ae6: 60f8 str r0, [r7, #12] 8013ae8: 60b9 str r1, [r7, #8] 8013aea: 607a str r2, [r7, #4] Queue_t * const pxQueue = xQueue; 8013aec: 68fb ldr r3, [r7, #12] 8013aee: 617b str r3, [r7, #20] will not actually cause the task to block, just place it on a blocked list. It will not block until the scheduler is unlocked - at which time a yield will be performed. If an item is added to the queue while the queue is locked, and the calling task blocks on the queue, then the calling task will be immediately unblocked when the queue is unlocked. */ prvLockQueue( pxQueue ); 8013af0: f002 fa0a bl 8015f08 8013af4: 697b ldr r3, [r7, #20] 8013af6: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8013afa: b25b sxtb r3, r3 8013afc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8013b00: d103 bne.n 8013b0a 8013b02: 697b ldr r3, [r7, #20] 8013b04: 2200 movs r2, #0 8013b06: f883 2044 strb.w r2, [r3, #68] @ 0x44 8013b0a: 697b ldr r3, [r7, #20] 8013b0c: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8013b10: b25b sxtb r3, r3 8013b12: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8013b16: d103 bne.n 8013b20 8013b18: 697b ldr r3, [r7, #20] 8013b1a: 2200 movs r2, #0 8013b1c: f883 2045 strb.w r2, [r3, #69] @ 0x45 8013b20: f002 fa24 bl 8015f6c if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) 8013b24: 697b ldr r3, [r7, #20] 8013b26: 6b9b ldr r3, [r3, #56] @ 0x38 8013b28: 2b00 cmp r3, #0 8013b2a: d106 bne.n 8013b3a { /* There is nothing in the queue, block for the specified period. */ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); 8013b2c: 697b ldr r3, [r7, #20] 8013b2e: 3324 adds r3, #36 @ 0x24 8013b30: 687a ldr r2, [r7, #4] 8013b32: 68b9 ldr r1, [r7, #8] 8013b34: 4618 mov r0, r3 8013b36: f000 fe39 bl 80147ac } else { mtCOVERAGE_TEST_MARKER(); } prvUnlockQueue( pxQueue ); 8013b3a: 6978 ldr r0, [r7, #20] 8013b3c: f7ff ff26 bl 801398c } 8013b40: bf00 nop 8013b42: 3718 adds r7, #24 8013b44: 46bd mov sp, r7 8013b46: bd80 pop {r7, pc} 08013b48 : return xReturn; } /*-----------------------------------------------------------*/ size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) { 8013b48: b480 push {r7} 8013b4a: b087 sub sp, #28 8013b4c: af00 add r7, sp, #0 8013b4e: 6078 str r0, [r7, #4] const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 8013b50: 687b ldr r3, [r7, #4] 8013b52: 613b str r3, [r7, #16] size_t xSpace; configASSERT( pxStreamBuffer ); 8013b54: 693b ldr r3, [r7, #16] 8013b56: 2b00 cmp r3, #0 8013b58: d10b bne.n 8013b72 __asm volatile 8013b5a: f04f 0350 mov.w r3, #80 @ 0x50 8013b5e: f383 8811 msr BASEPRI, r3 8013b62: f3bf 8f6f isb sy 8013b66: f3bf 8f4f dsb sy 8013b6a: 60fb str r3, [r7, #12] } 8013b6c: bf00 nop 8013b6e: bf00 nop 8013b70: e7fd b.n 8013b6e xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; 8013b72: 693b ldr r3, [r7, #16] 8013b74: 689a ldr r2, [r3, #8] 8013b76: 693b ldr r3, [r7, #16] 8013b78: 681b ldr r3, [r3, #0] 8013b7a: 4413 add r3, r2 8013b7c: 617b str r3, [r7, #20] xSpace -= pxStreamBuffer->xHead; 8013b7e: 693b ldr r3, [r7, #16] 8013b80: 685b ldr r3, [r3, #4] 8013b82: 697a ldr r2, [r7, #20] 8013b84: 1ad3 subs r3, r2, r3 8013b86: 617b str r3, [r7, #20] xSpace -= ( size_t ) 1; 8013b88: 697b ldr r3, [r7, #20] 8013b8a: 3b01 subs r3, #1 8013b8c: 617b str r3, [r7, #20] if( xSpace >= pxStreamBuffer->xLength ) 8013b8e: 693b ldr r3, [r7, #16] 8013b90: 689b ldr r3, [r3, #8] 8013b92: 697a ldr r2, [r7, #20] 8013b94: 429a cmp r2, r3 8013b96: d304 bcc.n 8013ba2 { xSpace -= pxStreamBuffer->xLength; 8013b98: 693b ldr r3, [r7, #16] 8013b9a: 689b ldr r3, [r3, #8] 8013b9c: 697a ldr r2, [r7, #20] 8013b9e: 1ad3 subs r3, r2, r3 8013ba0: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xSpace; 8013ba2: 697b ldr r3, [r7, #20] } 8013ba4: 4618 mov r0, r3 8013ba6: 371c adds r7, #28 8013ba8: 46bd mov sp, r7 8013baa: f85d 7b04 ldr.w r7, [sp], #4 8013bae: 4770 bx lr 08013bb0 : size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) { 8013bb0: b580 push {r7, lr} 8013bb2: b090 sub sp, #64 @ 0x40 8013bb4: af02 add r7, sp, #8 8013bb6: 60f8 str r0, [r7, #12] 8013bb8: 60b9 str r1, [r7, #8] 8013bba: 607a str r2, [r7, #4] 8013bbc: 603b str r3, [r7, #0] StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 8013bbe: 68fb ldr r3, [r7, #12] 8013bc0: 62fb str r3, [r7, #44] @ 0x2c size_t xReturn, xSpace = 0; 8013bc2: 2300 movs r3, #0 8013bc4: 637b str r3, [r7, #52] @ 0x34 size_t xRequiredSpace = xDataLengthBytes; 8013bc6: 687b ldr r3, [r7, #4] 8013bc8: 633b str r3, [r7, #48] @ 0x30 TimeOut_t xTimeOut; configASSERT( pvTxData ); 8013bca: 68bb ldr r3, [r7, #8] 8013bcc: 2b00 cmp r3, #0 8013bce: d10b bne.n 8013be8 __asm volatile 8013bd0: f04f 0350 mov.w r3, #80 @ 0x50 8013bd4: f383 8811 msr BASEPRI, r3 8013bd8: f3bf 8f6f isb sy 8013bdc: f3bf 8f4f dsb sy 8013be0: 627b str r3, [r7, #36] @ 0x24 } 8013be2: bf00 nop 8013be4: bf00 nop 8013be6: e7fd b.n 8013be4 configASSERT( pxStreamBuffer ); 8013be8: 6afb ldr r3, [r7, #44] @ 0x2c 8013bea: 2b00 cmp r3, #0 8013bec: d10b bne.n 8013c06 __asm volatile 8013bee: f04f 0350 mov.w r3, #80 @ 0x50 8013bf2: f383 8811 msr BASEPRI, r3 8013bf6: f3bf 8f6f isb sy 8013bfa: f3bf 8f4f dsb sy 8013bfe: 623b str r3, [r7, #32] } 8013c00: bf00 nop 8013c02: bf00 nop 8013c04: e7fd b.n 8013c02 /* This send function is used to write to both message buffers and stream buffers. If this is a message buffer then the space needed must be increased by the amount of bytes needed to store the length of the message. */ if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) 8013c06: 6afb ldr r3, [r7, #44] @ 0x2c 8013c08: 7f1b ldrb r3, [r3, #28] 8013c0a: f003 0301 and.w r3, r3, #1 8013c0e: 2b00 cmp r3, #0 8013c10: d012 beq.n 8013c38 { xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; 8013c12: 6b3b ldr r3, [r7, #48] @ 0x30 8013c14: 3304 adds r3, #4 8013c16: 633b str r3, [r7, #48] @ 0x30 /* Overflow? */ configASSERT( xRequiredSpace > xDataLengthBytes ); 8013c18: 6b3a ldr r2, [r7, #48] @ 0x30 8013c1a: 687b ldr r3, [r7, #4] 8013c1c: 429a cmp r2, r3 8013c1e: d80b bhi.n 8013c38 __asm volatile 8013c20: f04f 0350 mov.w r3, #80 @ 0x50 8013c24: f383 8811 msr BASEPRI, r3 8013c28: f3bf 8f6f isb sy 8013c2c: f3bf 8f4f dsb sy 8013c30: 61fb str r3, [r7, #28] } 8013c32: bf00 nop 8013c34: bf00 nop 8013c36: e7fd b.n 8013c34 else { mtCOVERAGE_TEST_MARKER(); } if( xTicksToWait != ( TickType_t ) 0 ) 8013c38: 683b ldr r3, [r7, #0] 8013c3a: 2b00 cmp r3, #0 8013c3c: d03f beq.n 8013cbe { vTaskSetTimeOutState( &xTimeOut ); 8013c3e: f107 0310 add.w r3, r7, #16 8013c42: 4618 mov r0, r3 8013c44: f000 fe42 bl 80148cc do { /* Wait until the required number of bytes are free in the message buffer. */ taskENTER_CRITICAL(); 8013c48: f002 f95e bl 8015f08 { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 8013c4c: 6af8 ldr r0, [r7, #44] @ 0x2c 8013c4e: f7ff ff7b bl 8013b48 8013c52: 6378 str r0, [r7, #52] @ 0x34 if( xSpace < xRequiredSpace ) 8013c54: 6b7a ldr r2, [r7, #52] @ 0x34 8013c56: 6b3b ldr r3, [r7, #48] @ 0x30 8013c58: 429a cmp r2, r3 8013c5a: d218 bcs.n 8013c8e { /* Clear notification state as going to wait for space. */ ( void ) xTaskNotifyStateClear( NULL ); 8013c5c: 2000 movs r0, #0 8013c5e: f001 fb65 bl 801532c /* Should only be one writer. */ configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL ); 8013c62: 6afb ldr r3, [r7, #44] @ 0x2c 8013c64: 695b ldr r3, [r3, #20] 8013c66: 2b00 cmp r3, #0 8013c68: d00b beq.n 8013c82 __asm volatile 8013c6a: f04f 0350 mov.w r3, #80 @ 0x50 8013c6e: f383 8811 msr BASEPRI, r3 8013c72: f3bf 8f6f isb sy 8013c76: f3bf 8f4f dsb sy 8013c7a: 61bb str r3, [r7, #24] } 8013c7c: bf00 nop 8013c7e: bf00 nop 8013c80: e7fd b.n 8013c7e pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle(); 8013c82: f000 ffad bl 8014be0 8013c86: 4602 mov r2, r0 8013c88: 6afb ldr r3, [r7, #44] @ 0x2c 8013c8a: 615a str r2, [r3, #20] 8013c8c: e002 b.n 8013c94 } else { taskEXIT_CRITICAL(); 8013c8e: f002 f96d bl 8015f6c break; 8013c92: e014 b.n 8013cbe } } taskEXIT_CRITICAL(); 8013c94: f002 f96a bl 8015f6c traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ); ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); 8013c98: 683b ldr r3, [r7, #0] 8013c9a: 2200 movs r2, #0 8013c9c: 2100 movs r1, #0 8013c9e: 2000 movs r0, #0 8013ca0: f001 f93c bl 8014f1c pxStreamBuffer->xTaskWaitingToSend = NULL; 8013ca4: 6afb ldr r3, [r7, #44] @ 0x2c 8013ca6: 2200 movs r2, #0 8013ca8: 615a str r2, [r3, #20] } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); 8013caa: 463a mov r2, r7 8013cac: f107 0310 add.w r3, r7, #16 8013cb0: 4611 mov r1, r2 8013cb2: 4618 mov r0, r3 8013cb4: f000 fe48 bl 8014948 8013cb8: 4603 mov r3, r0 8013cba: 2b00 cmp r3, #0 8013cbc: d0c4 beq.n 8013c48 else { mtCOVERAGE_TEST_MARKER(); } if( xSpace == ( size_t ) 0 ) 8013cbe: 6b7b ldr r3, [r7, #52] @ 0x34 8013cc0: 2b00 cmp r3, #0 8013cc2: d103 bne.n 8013ccc { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 8013cc4: 6af8 ldr r0, [r7, #44] @ 0x2c 8013cc6: f7ff ff3f bl 8013b48 8013cca: 6378 str r0, [r7, #52] @ 0x34 else { mtCOVERAGE_TEST_MARKER(); } xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); 8013ccc: 6b3b ldr r3, [r7, #48] @ 0x30 8013cce: 9300 str r3, [sp, #0] 8013cd0: 6b7b ldr r3, [r7, #52] @ 0x34 8013cd2: 687a ldr r2, [r7, #4] 8013cd4: 68b9 ldr r1, [r7, #8] 8013cd6: 6af8 ldr r0, [r7, #44] @ 0x2c 8013cd8: f000 f823 bl 8013d22 8013cdc: 62b8 str r0, [r7, #40] @ 0x28 if( xReturn > ( size_t ) 0 ) 8013cde: 6abb ldr r3, [r7, #40] @ 0x28 8013ce0: 2b00 cmp r3, #0 8013ce2: d019 beq.n 8013d18 { traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn ); /* Was a task waiting for the data? */ if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) 8013ce4: 6af8 ldr r0, [r7, #44] @ 0x2c 8013ce6: f000 f8ce bl 8013e86 8013cea: 4602 mov r2, r0 8013cec: 6afb ldr r3, [r7, #44] @ 0x2c 8013cee: 68db ldr r3, [r3, #12] 8013cf0: 429a cmp r2, r3 8013cf2: d311 bcc.n 8013d18 { sbSEND_COMPLETED( pxStreamBuffer ); 8013cf4: f000 fb4a bl 801438c 8013cf8: 6afb ldr r3, [r7, #44] @ 0x2c 8013cfa: 691b ldr r3, [r3, #16] 8013cfc: 2b00 cmp r3, #0 8013cfe: d009 beq.n 8013d14 8013d00: 6afb ldr r3, [r7, #44] @ 0x2c 8013d02: 6918 ldr r0, [r3, #16] 8013d04: 2300 movs r3, #0 8013d06: 2200 movs r2, #0 8013d08: 2100 movs r1, #0 8013d0a: f001 f967 bl 8014fdc 8013d0e: 6afb ldr r3, [r7, #44] @ 0x2c 8013d10: 2200 movs r2, #0 8013d12: 611a str r2, [r3, #16] 8013d14: f000 fb48 bl 80143a8 { mtCOVERAGE_TEST_MARKER(); traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ); } return xReturn; 8013d18: 6abb ldr r3, [r7, #40] @ 0x28 } 8013d1a: 4618 mov r0, r3 8013d1c: 3738 adds r7, #56 @ 0x38 8013d1e: 46bd mov sp, r7 8013d20: bd80 pop {r7, pc} 08013d22 : static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, const void * pvTxData, size_t xDataLengthBytes, size_t xSpace, size_t xRequiredSpace ) { 8013d22: b580 push {r7, lr} 8013d24: b086 sub sp, #24 8013d26: af00 add r7, sp, #0 8013d28: 60f8 str r0, [r7, #12] 8013d2a: 60b9 str r1, [r7, #8] 8013d2c: 607a str r2, [r7, #4] 8013d2e: 603b str r3, [r7, #0] BaseType_t xShouldWrite; size_t xReturn; if( xSpace == ( size_t ) 0 ) 8013d30: 683b ldr r3, [r7, #0] 8013d32: 2b00 cmp r3, #0 8013d34: d102 bne.n 8013d3c { /* Doesn't matter if this is a stream buffer or a message buffer, there is no space to write. */ xShouldWrite = pdFALSE; 8013d36: 2300 movs r3, #0 8013d38: 617b str r3, [r7, #20] 8013d3a: e01d b.n 8013d78 } else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 ) 8013d3c: 68fb ldr r3, [r7, #12] 8013d3e: 7f1b ldrb r3, [r3, #28] 8013d40: f003 0301 and.w r3, r3, #1 8013d44: 2b00 cmp r3, #0 8013d46: d108 bne.n 8013d5a { /* This is a stream buffer, as opposed to a message buffer, so writing a stream of bytes rather than discrete messages. Write as many bytes as possible. */ xShouldWrite = pdTRUE; 8013d48: 2301 movs r3, #1 8013d4a: 617b str r3, [r7, #20] xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); 8013d4c: 687a ldr r2, [r7, #4] 8013d4e: 683b ldr r3, [r7, #0] 8013d50: 4293 cmp r3, r2 8013d52: bf28 it cs 8013d54: 4613 movcs r3, r2 8013d56: 607b str r3, [r7, #4] 8013d58: e00e b.n 8013d78 } else if( xSpace >= xRequiredSpace ) 8013d5a: 683a ldr r2, [r7, #0] 8013d5c: 6a3b ldr r3, [r7, #32] 8013d5e: 429a cmp r2, r3 8013d60: d308 bcc.n 8013d74 { /* This is a message buffer, as opposed to a stream buffer, and there is enough space to write both the message length and the message itself into the buffer. Start by writing the length of the data, the data itself will be written later in this function. */ xShouldWrite = pdTRUE; 8013d62: 2301 movs r3, #1 8013d64: 617b str r3, [r7, #20] ( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH ); 8013d66: 1d3b adds r3, r7, #4 8013d68: 2204 movs r2, #4 8013d6a: 4619 mov r1, r3 8013d6c: 68f8 ldr r0, [r7, #12] 8013d6e: f000 f815 bl 8013d9c 8013d72: e001 b.n 8013d78 } else { /* There is space available, but not enough space. */ xShouldWrite = pdFALSE; 8013d74: 2300 movs r3, #0 8013d76: 617b str r3, [r7, #20] } if( xShouldWrite != pdFALSE ) 8013d78: 697b ldr r3, [r7, #20] 8013d7a: 2b00 cmp r3, #0 8013d7c: d007 beq.n 8013d8e { /* Writes the data itself. */ xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */ 8013d7e: 687b ldr r3, [r7, #4] 8013d80: 461a mov r2, r3 8013d82: 68b9 ldr r1, [r7, #8] 8013d84: 68f8 ldr r0, [r7, #12] 8013d86: f000 f809 bl 8013d9c 8013d8a: 6138 str r0, [r7, #16] 8013d8c: e001 b.n 8013d92 } else { xReturn = 0; 8013d8e: 2300 movs r3, #0 8013d90: 613b str r3, [r7, #16] } return xReturn; 8013d92: 693b ldr r3, [r7, #16] } 8013d94: 4618 mov r0, r3 8013d96: 3718 adds r7, #24 8013d98: 46bd mov sp, r7 8013d9a: bd80 pop {r7, pc} 08013d9c : return xReturn; } /*-----------------------------------------------------------*/ static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) { 8013d9c: b580 push {r7, lr} 8013d9e: b08a sub sp, #40 @ 0x28 8013da0: af00 add r7, sp, #0 8013da2: 60f8 str r0, [r7, #12] 8013da4: 60b9 str r1, [r7, #8] 8013da6: 607a str r2, [r7, #4] size_t xNextHead, xFirstLength; configASSERT( xCount > ( size_t ) 0 ); 8013da8: 687b ldr r3, [r7, #4] 8013daa: 2b00 cmp r3, #0 8013dac: d10b bne.n 8013dc6 __asm volatile 8013dae: f04f 0350 mov.w r3, #80 @ 0x50 8013db2: f383 8811 msr BASEPRI, r3 8013db6: f3bf 8f6f isb sy 8013dba: f3bf 8f4f dsb sy 8013dbe: 61fb str r3, [r7, #28] } 8013dc0: bf00 nop 8013dc2: bf00 nop 8013dc4: e7fd b.n 8013dc2 xNextHead = pxStreamBuffer->xHead; 8013dc6: 68fb ldr r3, [r7, #12] 8013dc8: 685b ldr r3, [r3, #4] 8013dca: 627b str r3, [r7, #36] @ 0x24 /* Calculate the number of bytes that can be added in the first write - which may be less than the total number of bytes that need to be added if the buffer will wrap back to the beginning. */ xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount ); 8013dcc: 68fb ldr r3, [r7, #12] 8013dce: 689a ldr r2, [r3, #8] 8013dd0: 6a7b ldr r3, [r7, #36] @ 0x24 8013dd2: 1ad3 subs r3, r2, r3 8013dd4: 687a ldr r2, [r7, #4] 8013dd6: 4293 cmp r3, r2 8013dd8: bf28 it cs 8013dda: 4613 movcs r3, r2 8013ddc: 623b str r3, [r7, #32] /* Write as many bytes as can be written in the first write. */ configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength ); 8013dde: 6a7a ldr r2, [r7, #36] @ 0x24 8013de0: 6a3b ldr r3, [r7, #32] 8013de2: 441a add r2, r3 8013de4: 68fb ldr r3, [r7, #12] 8013de6: 689b ldr r3, [r3, #8] 8013de8: 429a cmp r2, r3 8013dea: d90b bls.n 8013e04 __asm volatile 8013dec: f04f 0350 mov.w r3, #80 @ 0x50 8013df0: f383 8811 msr BASEPRI, r3 8013df4: f3bf 8f6f isb sy 8013df8: f3bf 8f4f dsb sy 8013dfc: 61bb str r3, [r7, #24] } 8013dfe: bf00 nop 8013e00: bf00 nop 8013e02: e7fd b.n 8013e00 ( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 8013e04: 68fb ldr r3, [r7, #12] 8013e06: 699a ldr r2, [r3, #24] 8013e08: 6a7b ldr r3, [r7, #36] @ 0x24 8013e0a: 4413 add r3, r2 8013e0c: 6a3a ldr r2, [r7, #32] 8013e0e: 68b9 ldr r1, [r7, #8] 8013e10: 4618 mov r0, r3 8013e12: f002 fd72 bl 80168fa /* If the number of bytes written was less than the number that could be written in the first write... */ if( xCount > xFirstLength ) 8013e16: 687a ldr r2, [r7, #4] 8013e18: 6a3b ldr r3, [r7, #32] 8013e1a: 429a cmp r2, r3 8013e1c: d91d bls.n 8013e5a { /* ...then write the remaining bytes to the start of the buffer. */ configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength ); 8013e1e: 687a ldr r2, [r7, #4] 8013e20: 6a3b ldr r3, [r7, #32] 8013e22: 1ad2 subs r2, r2, r3 8013e24: 68fb ldr r3, [r7, #12] 8013e26: 689b ldr r3, [r3, #8] 8013e28: 429a cmp r2, r3 8013e2a: d90b bls.n 8013e44 __asm volatile 8013e2c: f04f 0350 mov.w r3, #80 @ 0x50 8013e30: f383 8811 msr BASEPRI, r3 8013e34: f3bf 8f6f isb sy 8013e38: f3bf 8f4f dsb sy 8013e3c: 617b str r3, [r7, #20] } 8013e3e: bf00 nop 8013e40: bf00 nop 8013e42: e7fd b.n 8013e40 ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 8013e44: 68fb ldr r3, [r7, #12] 8013e46: 6998 ldr r0, [r3, #24] 8013e48: 68ba ldr r2, [r7, #8] 8013e4a: 6a3b ldr r3, [r7, #32] 8013e4c: 18d1 adds r1, r2, r3 8013e4e: 687a ldr r2, [r7, #4] 8013e50: 6a3b ldr r3, [r7, #32] 8013e52: 1ad3 subs r3, r2, r3 8013e54: 461a mov r2, r3 8013e56: f002 fd50 bl 80168fa else { mtCOVERAGE_TEST_MARKER(); } xNextHead += xCount; 8013e5a: 6a7a ldr r2, [r7, #36] @ 0x24 8013e5c: 687b ldr r3, [r7, #4] 8013e5e: 4413 add r3, r2 8013e60: 627b str r3, [r7, #36] @ 0x24 if( xNextHead >= pxStreamBuffer->xLength ) 8013e62: 68fb ldr r3, [r7, #12] 8013e64: 689b ldr r3, [r3, #8] 8013e66: 6a7a ldr r2, [r7, #36] @ 0x24 8013e68: 429a cmp r2, r3 8013e6a: d304 bcc.n 8013e76 { xNextHead -= pxStreamBuffer->xLength; 8013e6c: 68fb ldr r3, [r7, #12] 8013e6e: 689b ldr r3, [r3, #8] 8013e70: 6a7a ldr r2, [r7, #36] @ 0x24 8013e72: 1ad3 subs r3, r2, r3 8013e74: 627b str r3, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } pxStreamBuffer->xHead = xNextHead; 8013e76: 68fb ldr r3, [r7, #12] 8013e78: 6a7a ldr r2, [r7, #36] @ 0x24 8013e7a: 605a str r2, [r3, #4] return xCount; 8013e7c: 687b ldr r3, [r7, #4] } 8013e7e: 4618 mov r0, r3 8013e80: 3728 adds r7, #40 @ 0x28 8013e82: 46bd mov sp, r7 8013e84: bd80 pop {r7, pc} 08013e86 : return xCount; } /*-----------------------------------------------------------*/ static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) { 8013e86: b480 push {r7} 8013e88: b085 sub sp, #20 8013e8a: af00 add r7, sp, #0 8013e8c: 6078 str r0, [r7, #4] /* Returns the distance between xTail and xHead. */ size_t xCount; xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead; 8013e8e: 687b ldr r3, [r7, #4] 8013e90: 689a ldr r2, [r3, #8] 8013e92: 687b ldr r3, [r7, #4] 8013e94: 685b ldr r3, [r3, #4] 8013e96: 4413 add r3, r2 8013e98: 60fb str r3, [r7, #12] xCount -= pxStreamBuffer->xTail; 8013e9a: 687b ldr r3, [r7, #4] 8013e9c: 681b ldr r3, [r3, #0] 8013e9e: 68fa ldr r2, [r7, #12] 8013ea0: 1ad3 subs r3, r2, r3 8013ea2: 60fb str r3, [r7, #12] if ( xCount >= pxStreamBuffer->xLength ) 8013ea4: 687b ldr r3, [r7, #4] 8013ea6: 689b ldr r3, [r3, #8] 8013ea8: 68fa ldr r2, [r7, #12] 8013eaa: 429a cmp r2, r3 8013eac: d304 bcc.n 8013eb8 { xCount -= pxStreamBuffer->xLength; 8013eae: 687b ldr r3, [r7, #4] 8013eb0: 689b ldr r3, [r3, #8] 8013eb2: 68fa ldr r2, [r7, #12] 8013eb4: 1ad3 subs r3, r2, r3 8013eb6: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xCount; 8013eb8: 68fb ldr r3, [r7, #12] } 8013eba: 4618 mov r0, r3 8013ebc: 3714 adds r7, #20 8013ebe: 46bd mov sp, r7 8013ec0: f85d 7b04 ldr.w r7, [sp], #4 8013ec4: 4770 bx lr 08013ec6 : const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) { 8013ec6: b580 push {r7, lr} 8013ec8: b08e sub sp, #56 @ 0x38 8013eca: af04 add r7, sp, #16 8013ecc: 60f8 str r0, [r7, #12] 8013ece: 60b9 str r1, [r7, #8] 8013ed0: 607a str r2, [r7, #4] 8013ed2: 603b str r3, [r7, #0] TCB_t *pxNewTCB; TaskHandle_t xReturn; configASSERT( puxStackBuffer != NULL ); 8013ed4: 6b7b ldr r3, [r7, #52] @ 0x34 8013ed6: 2b00 cmp r3, #0 8013ed8: d10b bne.n 8013ef2 __asm volatile 8013eda: f04f 0350 mov.w r3, #80 @ 0x50 8013ede: f383 8811 msr BASEPRI, r3 8013ee2: f3bf 8f6f isb sy 8013ee6: f3bf 8f4f dsb sy 8013eea: 623b str r3, [r7, #32] } 8013eec: bf00 nop 8013eee: bf00 nop 8013ef0: e7fd b.n 8013eee configASSERT( pxTaskBuffer != NULL ); 8013ef2: 6bbb ldr r3, [r7, #56] @ 0x38 8013ef4: 2b00 cmp r3, #0 8013ef6: d10b bne.n 8013f10 __asm volatile 8013ef8: f04f 0350 mov.w r3, #80 @ 0x50 8013efc: f383 8811 msr BASEPRI, r3 8013f00: f3bf 8f6f isb sy 8013f04: f3bf 8f4f dsb sy 8013f08: 61fb str r3, [r7, #28] } 8013f0a: bf00 nop 8013f0c: bf00 nop 8013f0e: e7fd b.n 8013f0c #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTask_t equals the size of the real task structure. */ volatile size_t xSize = sizeof( StaticTask_t ); 8013f10: 23a8 movs r3, #168 @ 0xa8 8013f12: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( TCB_t ) ); 8013f14: 693b ldr r3, [r7, #16] 8013f16: 2ba8 cmp r3, #168 @ 0xa8 8013f18: d00b beq.n 8013f32 __asm volatile 8013f1a: f04f 0350 mov.w r3, #80 @ 0x50 8013f1e: f383 8811 msr BASEPRI, r3 8013f22: f3bf 8f6f isb sy 8013f26: f3bf 8f4f dsb sy 8013f2a: 61bb str r3, [r7, #24] } 8013f2c: bf00 nop 8013f2e: bf00 nop 8013f30: e7fd b.n 8013f2e ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ 8013f32: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) 8013f34: 6bbb ldr r3, [r7, #56] @ 0x38 8013f36: 2b00 cmp r3, #0 8013f38: d01e beq.n 8013f78 8013f3a: 6b7b ldr r3, [r7, #52] @ 0x34 8013f3c: 2b00 cmp r3, #0 8013f3e: d01b beq.n 8013f78 { /* The memory used for the task's TCB and stack are passed into this function - use them. */ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8013f40: 6bbb ldr r3, [r7, #56] @ 0x38 8013f42: 627b str r3, [r7, #36] @ 0x24 pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; 8013f44: 6a7b ldr r3, [r7, #36] @ 0x24 8013f46: 6b7a ldr r2, [r7, #52] @ 0x34 8013f48: 631a str r2, [r3, #48] @ 0x30 #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created statically in case the task is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; 8013f4a: 6a7b ldr r3, [r7, #36] @ 0x24 8013f4c: 2202 movs r2, #2 8013f4e: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 8013f52: 2300 movs r3, #0 8013f54: 9303 str r3, [sp, #12] 8013f56: 6a7b ldr r3, [r7, #36] @ 0x24 8013f58: 9302 str r3, [sp, #8] 8013f5a: f107 0314 add.w r3, r7, #20 8013f5e: 9301 str r3, [sp, #4] 8013f60: 6b3b ldr r3, [r7, #48] @ 0x30 8013f62: 9300 str r3, [sp, #0] 8013f64: 683b ldr r3, [r7, #0] 8013f66: 687a ldr r2, [r7, #4] 8013f68: 68b9 ldr r1, [r7, #8] 8013f6a: 68f8 ldr r0, [r7, #12] 8013f6c: f000 f850 bl 8014010 prvAddNewTaskToReadyList( pxNewTCB ); 8013f70: 6a78 ldr r0, [r7, #36] @ 0x24 8013f72: f000 f8f5 bl 8014160 8013f76: e001 b.n 8013f7c } else { xReturn = NULL; 8013f78: 2300 movs r3, #0 8013f7a: 617b str r3, [r7, #20] } return xReturn; 8013f7c: 697b ldr r3, [r7, #20] } 8013f7e: 4618 mov r0, r3 8013f80: 3728 adds r7, #40 @ 0x28 8013f82: 46bd mov sp, r7 8013f84: bd80 pop {r7, pc} 08013f86 : const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const configSTACK_DEPTH_TYPE usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) { 8013f86: b580 push {r7, lr} 8013f88: b08c sub sp, #48 @ 0x30 8013f8a: af04 add r7, sp, #16 8013f8c: 60f8 str r0, [r7, #12] 8013f8e: 60b9 str r1, [r7, #8] 8013f90: 603b str r3, [r7, #0] 8013f92: 4613 mov r3, r2 8013f94: 80fb strh r3, [r7, #6] #else /* portSTACK_GROWTH */ { StackType_t *pxStack; /* Allocate space for the stack used by the task being created. */ pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ 8013f96: 88fb ldrh r3, [r7, #6] 8013f98: 009b lsls r3, r3, #2 8013f9a: 4618 mov r0, r3 8013f9c: f002 f8d6 bl 801614c 8013fa0: 6178 str r0, [r7, #20] if( pxStack != NULL ) 8013fa2: 697b ldr r3, [r7, #20] 8013fa4: 2b00 cmp r3, #0 8013fa6: d00e beq.n 8013fc6 { /* Allocate space for the TCB. */ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ 8013fa8: 20a8 movs r0, #168 @ 0xa8 8013faa: f002 f8cf bl 801614c 8013fae: 61f8 str r0, [r7, #28] if( pxNewTCB != NULL ) 8013fb0: 69fb ldr r3, [r7, #28] 8013fb2: 2b00 cmp r3, #0 8013fb4: d003 beq.n 8013fbe { /* Store the stack location in the TCB. */ pxNewTCB->pxStack = pxStack; 8013fb6: 69fb ldr r3, [r7, #28] 8013fb8: 697a ldr r2, [r7, #20] 8013fba: 631a str r2, [r3, #48] @ 0x30 8013fbc: e005 b.n 8013fca } else { /* The stack cannot be used as the TCB was not created. Free it again. */ vPortFree( pxStack ); 8013fbe: 6978 ldr r0, [r7, #20] 8013fc0: f002 f992 bl 80162e8 8013fc4: e001 b.n 8013fca } } else { pxNewTCB = NULL; 8013fc6: 2300 movs r3, #0 8013fc8: 61fb str r3, [r7, #28] } } #endif /* portSTACK_GROWTH */ if( pxNewTCB != NULL ) 8013fca: 69fb ldr r3, [r7, #28] 8013fcc: 2b00 cmp r3, #0 8013fce: d017 beq.n 8014000 { #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; 8013fd0: 69fb ldr r3, [r7, #28] 8013fd2: 2200 movs r2, #0 8013fd4: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); 8013fd8: 88fa ldrh r2, [r7, #6] 8013fda: 2300 movs r3, #0 8013fdc: 9303 str r3, [sp, #12] 8013fde: 69fb ldr r3, [r7, #28] 8013fe0: 9302 str r3, [sp, #8] 8013fe2: 6afb ldr r3, [r7, #44] @ 0x2c 8013fe4: 9301 str r3, [sp, #4] 8013fe6: 6abb ldr r3, [r7, #40] @ 0x28 8013fe8: 9300 str r3, [sp, #0] 8013fea: 683b ldr r3, [r7, #0] 8013fec: 68b9 ldr r1, [r7, #8] 8013fee: 68f8 ldr r0, [r7, #12] 8013ff0: f000 f80e bl 8014010 prvAddNewTaskToReadyList( pxNewTCB ); 8013ff4: 69f8 ldr r0, [r7, #28] 8013ff6: f000 f8b3 bl 8014160 xReturn = pdPASS; 8013ffa: 2301 movs r3, #1 8013ffc: 61bb str r3, [r7, #24] 8013ffe: e002 b.n 8014006 } else { xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; 8014000: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8014004: 61bb str r3, [r7, #24] } return xReturn; 8014006: 69bb ldr r3, [r7, #24] } 8014008: 4618 mov r0, r3 801400a: 3720 adds r7, #32 801400c: 46bd mov sp, r7 801400e: bd80 pop {r7, pc} 08014010 : void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, TCB_t *pxNewTCB, const MemoryRegion_t * const xRegions ) { 8014010: b580 push {r7, lr} 8014012: b088 sub sp, #32 8014014: af00 add r7, sp, #0 8014016: 60f8 str r0, [r7, #12] 8014018: 60b9 str r1, [r7, #8] 801401a: 607a str r2, [r7, #4] 801401c: 603b str r3, [r7, #0] /* Avoid dependency on memset() if it is not required. */ #if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) { /* Fill the stack with a known value to assist debugging. */ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); 801401e: 6b3b ldr r3, [r7, #48] @ 0x30 8014020: 6b18 ldr r0, [r3, #48] @ 0x30 8014022: 687b ldr r3, [r7, #4] 8014024: 009b lsls r3, r3, #2 8014026: 461a mov r2, r3 8014028: 21a5 movs r1, #165 @ 0xa5 801402a: f002 fb94 bl 8016756 grows from high memory to low (as per the 80x86) or vice versa. portSTACK_GROWTH is used to make the result positive or negative as required by the port. */ #if( portSTACK_GROWTH < 0 ) { pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); 801402e: 6b3b ldr r3, [r7, #48] @ 0x30 8014030: 6b1a ldr r2, [r3, #48] @ 0x30 8014032: 6879 ldr r1, [r7, #4] 8014034: f06f 4340 mvn.w r3, #3221225472 @ 0xc0000000 8014038: 440b add r3, r1 801403a: 009b lsls r3, r3, #2 801403c: 4413 add r3, r2 801403e: 61bb str r3, [r7, #24] pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ 8014040: 69bb ldr r3, [r7, #24] 8014042: f023 0307 bic.w r3, r3, #7 8014046: 61bb str r3, [r7, #24] /* Check the alignment of the calculated top of stack is correct. */ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); 8014048: 69bb ldr r3, [r7, #24] 801404a: f003 0307 and.w r3, r3, #7 801404e: 2b00 cmp r3, #0 8014050: d00b beq.n 801406a __asm volatile 8014052: f04f 0350 mov.w r3, #80 @ 0x50 8014056: f383 8811 msr BASEPRI, r3 801405a: f3bf 8f6f isb sy 801405e: f3bf 8f4f dsb sy 8014062: 617b str r3, [r7, #20] } 8014064: bf00 nop 8014066: bf00 nop 8014068: e7fd b.n 8014066 pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); } #endif /* portSTACK_GROWTH */ /* Store the task name in the TCB. */ if( pcName != NULL ) 801406a: 68bb ldr r3, [r7, #8] 801406c: 2b00 cmp r3, #0 801406e: d01f beq.n 80140b0 { for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8014070: 2300 movs r3, #0 8014072: 61fb str r3, [r7, #28] 8014074: e012 b.n 801409c { pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 8014076: 68ba ldr r2, [r7, #8] 8014078: 69fb ldr r3, [r7, #28] 801407a: 4413 add r3, r2 801407c: 7819 ldrb r1, [r3, #0] 801407e: 6b3a ldr r2, [r7, #48] @ 0x30 8014080: 69fb ldr r3, [r7, #28] 8014082: 4413 add r3, r2 8014084: 3334 adds r3, #52 @ 0x34 8014086: 460a mov r2, r1 8014088: 701a strb r2, [r3, #0] /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than configMAX_TASK_NAME_LEN characters just in case the memory after the string is not accessible (extremely unlikely). */ if( pcName[ x ] == ( char ) 0x00 ) 801408a: 68ba ldr r2, [r7, #8] 801408c: 69fb ldr r3, [r7, #28] 801408e: 4413 add r3, r2 8014090: 781b ldrb r3, [r3, #0] 8014092: 2b00 cmp r3, #0 8014094: d006 beq.n 80140a4 for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8014096: 69fb ldr r3, [r7, #28] 8014098: 3301 adds r3, #1 801409a: 61fb str r3, [r7, #28] 801409c: 69fb ldr r3, [r7, #28] 801409e: 2b0f cmp r3, #15 80140a0: d9e9 bls.n 8014076 80140a2: e000 b.n 80140a6 { break; 80140a4: bf00 nop } } /* Ensure the name string is terminated in the case that the string length was greater or equal to configMAX_TASK_NAME_LEN. */ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; 80140a6: 6b3b ldr r3, [r7, #48] @ 0x30 80140a8: 2200 movs r2, #0 80140aa: f883 2043 strb.w r2, [r3, #67] @ 0x43 80140ae: e003 b.n 80140b8 } else { /* The task has not been given a name, so just ensure there is a NULL terminator when it is read out. */ pxNewTCB->pcTaskName[ 0 ] = 0x00; 80140b0: 6b3b ldr r3, [r7, #48] @ 0x30 80140b2: 2200 movs r2, #0 80140b4: f883 2034 strb.w r2, [r3, #52] @ 0x34 } /* This is used as an array index so must ensure it's not too large. First remove the privilege bit if one is present. */ if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) 80140b8: 6abb ldr r3, [r7, #40] @ 0x28 80140ba: 2b37 cmp r3, #55 @ 0x37 80140bc: d901 bls.n 80140c2 { uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; 80140be: 2337 movs r3, #55 @ 0x37 80140c0: 62bb str r3, [r7, #40] @ 0x28 else { mtCOVERAGE_TEST_MARKER(); } pxNewTCB->uxPriority = uxPriority; 80140c2: 6b3b ldr r3, [r7, #48] @ 0x30 80140c4: 6aba ldr r2, [r7, #40] @ 0x28 80140c6: 62da str r2, [r3, #44] @ 0x2c #if ( configUSE_MUTEXES == 1 ) { pxNewTCB->uxBasePriority = uxPriority; 80140c8: 6b3b ldr r3, [r7, #48] @ 0x30 80140ca: 6aba ldr r2, [r7, #40] @ 0x28 80140cc: 64da str r2, [r3, #76] @ 0x4c pxNewTCB->uxMutexesHeld = 0; 80140ce: 6b3b ldr r3, [r7, #48] @ 0x30 80140d0: 2200 movs r2, #0 80140d2: 651a str r2, [r3, #80] @ 0x50 } #endif /* configUSE_MUTEXES */ vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); 80140d4: 6b3b ldr r3, [r7, #48] @ 0x30 80140d6: 3304 adds r3, #4 80140d8: 4618 mov r0, r3 80140da: f7fe fd09 bl 8012af0 vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); 80140de: 6b3b ldr r3, [r7, #48] @ 0x30 80140e0: 3318 adds r3, #24 80140e2: 4618 mov r0, r3 80140e4: f7fe fd04 bl 8012af0 /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get back to the containing TCB from a generic item in a list. */ listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); 80140e8: 6b3b ldr r3, [r7, #48] @ 0x30 80140ea: 6b3a ldr r2, [r7, #48] @ 0x30 80140ec: 611a str r2, [r3, #16] /* Event lists are always in priority order. */ listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 80140ee: 6abb ldr r3, [r7, #40] @ 0x28 80140f0: f1c3 0238 rsb r2, r3, #56 @ 0x38 80140f4: 6b3b ldr r3, [r7, #48] @ 0x30 80140f6: 619a str r2, [r3, #24] listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); 80140f8: 6b3b ldr r3, [r7, #48] @ 0x30 80140fa: 6b3a ldr r2, [r7, #48] @ 0x30 80140fc: 625a str r2, [r3, #36] @ 0x24 } #endif #if ( configUSE_TASK_NOTIFICATIONS == 1 ) { pxNewTCB->ulNotifiedValue = 0; 80140fe: 6b3b ldr r3, [r7, #48] @ 0x30 8014100: 2200 movs r2, #0 8014102: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8014106: 6b3b ldr r3, [r7, #48] @ 0x30 8014108: 2200 movs r2, #0 801410a: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 #if ( configUSE_NEWLIB_REENTRANT == 1 ) { /* Initialise this task's Newlib reent structure. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); 801410e: 6b3b ldr r3, [r7, #48] @ 0x30 8014110: 3354 adds r3, #84 @ 0x54 8014112: 224c movs r2, #76 @ 0x4c 8014114: 2100 movs r1, #0 8014116: 4618 mov r0, r3 8014118: f002 fb1d bl 8016756 801411c: 6b3b ldr r3, [r7, #48] @ 0x30 801411e: 4a0d ldr r2, [pc, #52] @ (8014154 ) 8014120: 659a str r2, [r3, #88] @ 0x58 8014122: 6b3b ldr r3, [r7, #48] @ 0x30 8014124: 4a0c ldr r2, [pc, #48] @ (8014158 ) 8014126: 65da str r2, [r3, #92] @ 0x5c 8014128: 6b3b ldr r3, [r7, #48] @ 0x30 801412a: 4a0c ldr r2, [pc, #48] @ (801415c ) 801412c: 661a str r2, [r3, #96] @ 0x60 } #endif /* portSTACK_GROWTH */ } #else /* portHAS_STACK_OVERFLOW_CHECKING */ { pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); 801412e: 683a ldr r2, [r7, #0] 8014130: 68f9 ldr r1, [r7, #12] 8014132: 69b8 ldr r0, [r7, #24] 8014134: f001 fdb8 bl 8015ca8 8014138: 4602 mov r2, r0 801413a: 6b3b ldr r3, [r7, #48] @ 0x30 801413c: 601a str r2, [r3, #0] } #endif /* portHAS_STACK_OVERFLOW_CHECKING */ } #endif /* portUSING_MPU_WRAPPERS */ if( pxCreatedTask != NULL ) 801413e: 6afb ldr r3, [r7, #44] @ 0x2c 8014140: 2b00 cmp r3, #0 8014142: d002 beq.n 801414a { /* Pass the handle out in an anonymous way. The handle can be used to change the created task's priority, delete the created task, etc.*/ *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; 8014144: 6afb ldr r3, [r7, #44] @ 0x2c 8014146: 6b3a ldr r2, [r7, #48] @ 0x30 8014148: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 801414a: bf00 nop 801414c: 3720 adds r7, #32 801414e: 46bd mov sp, r7 8014150: bd80 pop {r7, pc} 8014152: bf00 nop 8014154: 24012bf8 .word 0x24012bf8 8014158: 24012c60 .word 0x24012c60 801415c: 24012cc8 .word 0x24012cc8 08014160 : /*-----------------------------------------------------------*/ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) { 8014160: b580 push {r7, lr} 8014162: b082 sub sp, #8 8014164: af00 add r7, sp, #0 8014166: 6078 str r0, [r7, #4] /* Ensure interrupts don't access the task lists while the lists are being updated. */ taskENTER_CRITICAL(); 8014168: f001 fece bl 8015f08 { uxCurrentNumberOfTasks++; 801416c: 4b2d ldr r3, [pc, #180] @ (8014224 ) 801416e: 681b ldr r3, [r3, #0] 8014170: 3301 adds r3, #1 8014172: 4a2c ldr r2, [pc, #176] @ (8014224 ) 8014174: 6013 str r3, [r2, #0] if( pxCurrentTCB == NULL ) 8014176: 4b2c ldr r3, [pc, #176] @ (8014228 ) 8014178: 681b ldr r3, [r3, #0] 801417a: 2b00 cmp r3, #0 801417c: d109 bne.n 8014192 { /* There are no other tasks, or all the other tasks are in the suspended state - make this the current task. */ pxCurrentTCB = pxNewTCB; 801417e: 4a2a ldr r2, [pc, #168] @ (8014228 ) 8014180: 687b ldr r3, [r7, #4] 8014182: 6013 str r3, [r2, #0] if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) 8014184: 4b27 ldr r3, [pc, #156] @ (8014224 ) 8014186: 681b ldr r3, [r3, #0] 8014188: 2b01 cmp r3, #1 801418a: d110 bne.n 80141ae { /* This is the first task to be created so do the preliminary initialisation required. We will not recover if this call fails, but we will report the failure. */ prvInitialiseTaskLists(); 801418c: f000 fc64 bl 8014a58 8014190: e00d b.n 80141ae else { /* If the scheduler is not already running, make this task the current task if it is the highest priority task to be created so far. */ if( xSchedulerRunning == pdFALSE ) 8014192: 4b26 ldr r3, [pc, #152] @ (801422c ) 8014194: 681b ldr r3, [r3, #0] 8014196: 2b00 cmp r3, #0 8014198: d109 bne.n 80141ae { if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) 801419a: 4b23 ldr r3, [pc, #140] @ (8014228 ) 801419c: 681b ldr r3, [r3, #0] 801419e: 6ada ldr r2, [r3, #44] @ 0x2c 80141a0: 687b ldr r3, [r7, #4] 80141a2: 6adb ldr r3, [r3, #44] @ 0x2c 80141a4: 429a cmp r2, r3 80141a6: d802 bhi.n 80141ae { pxCurrentTCB = pxNewTCB; 80141a8: 4a1f ldr r2, [pc, #124] @ (8014228 ) 80141aa: 687b ldr r3, [r7, #4] 80141ac: 6013 str r3, [r2, #0] { mtCOVERAGE_TEST_MARKER(); } } uxTaskNumber++; 80141ae: 4b20 ldr r3, [pc, #128] @ (8014230 ) 80141b0: 681b ldr r3, [r3, #0] 80141b2: 3301 adds r3, #1 80141b4: 4a1e ldr r2, [pc, #120] @ (8014230 ) 80141b6: 6013 str r3, [r2, #0] #if ( configUSE_TRACE_FACILITY == 1 ) { /* Add a counter into the TCB for tracing only. */ pxNewTCB->uxTCBNumber = uxTaskNumber; 80141b8: 4b1d ldr r3, [pc, #116] @ (8014230 ) 80141ba: 681a ldr r2, [r3, #0] 80141bc: 687b ldr r3, [r7, #4] 80141be: 645a str r2, [r3, #68] @ 0x44 } #endif /* configUSE_TRACE_FACILITY */ traceTASK_CREATE( pxNewTCB ); prvAddTaskToReadyList( pxNewTCB ); 80141c0: 687b ldr r3, [r7, #4] 80141c2: 6ada ldr r2, [r3, #44] @ 0x2c 80141c4: 4b1b ldr r3, [pc, #108] @ (8014234 ) 80141c6: 681b ldr r3, [r3, #0] 80141c8: 429a cmp r2, r3 80141ca: d903 bls.n 80141d4 80141cc: 687b ldr r3, [r7, #4] 80141ce: 6adb ldr r3, [r3, #44] @ 0x2c 80141d0: 4a18 ldr r2, [pc, #96] @ (8014234 ) 80141d2: 6013 str r3, [r2, #0] 80141d4: 687b ldr r3, [r7, #4] 80141d6: 6ada ldr r2, [r3, #44] @ 0x2c 80141d8: 4613 mov r3, r2 80141da: 009b lsls r3, r3, #2 80141dc: 4413 add r3, r2 80141de: 009b lsls r3, r3, #2 80141e0: 4a15 ldr r2, [pc, #84] @ (8014238 ) 80141e2: 441a add r2, r3 80141e4: 687b ldr r3, [r7, #4] 80141e6: 3304 adds r3, #4 80141e8: 4619 mov r1, r3 80141ea: 4610 mov r0, r2 80141ec: f7fe fc8d bl 8012b0a portSETUP_TCB( pxNewTCB ); } taskEXIT_CRITICAL(); 80141f0: f001 febc bl 8015f6c if( xSchedulerRunning != pdFALSE ) 80141f4: 4b0d ldr r3, [pc, #52] @ (801422c ) 80141f6: 681b ldr r3, [r3, #0] 80141f8: 2b00 cmp r3, #0 80141fa: d00e beq.n 801421a { /* If the created task is of a higher priority than the current task then it should run now. */ if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) 80141fc: 4b0a ldr r3, [pc, #40] @ (8014228 ) 80141fe: 681b ldr r3, [r3, #0] 8014200: 6ada ldr r2, [r3, #44] @ 0x2c 8014202: 687b ldr r3, [r7, #4] 8014204: 6adb ldr r3, [r3, #44] @ 0x2c 8014206: 429a cmp r2, r3 8014208: d207 bcs.n 801421a { taskYIELD_IF_USING_PREEMPTION(); 801420a: 4b0c ldr r3, [pc, #48] @ (801423c ) 801420c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014210: 601a str r2, [r3, #0] 8014212: f3bf 8f4f dsb sy 8014216: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 801421a: bf00 nop 801421c: 3708 adds r7, #8 801421e: 46bd mov sp, r7 8014220: bd80 pop {r7, pc} 8014222: bf00 nop 8014224: 24002a78 .word 0x24002a78 8014228: 240025a4 .word 0x240025a4 801422c: 24002a84 .word 0x24002a84 8014230: 24002a94 .word 0x24002a94 8014234: 24002a80 .word 0x24002a80 8014238: 240025a8 .word 0x240025a8 801423c: e000ed04 .word 0xe000ed04 08014240 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelay == 1 ) void vTaskDelay( const TickType_t xTicksToDelay ) { 8014240: b580 push {r7, lr} 8014242: b084 sub sp, #16 8014244: af00 add r7, sp, #0 8014246: 6078 str r0, [r7, #4] BaseType_t xAlreadyYielded = pdFALSE; 8014248: 2300 movs r3, #0 801424a: 60fb str r3, [r7, #12] /* A delay time of zero just forces a reschedule. */ if( xTicksToDelay > ( TickType_t ) 0U ) 801424c: 687b ldr r3, [r7, #4] 801424e: 2b00 cmp r3, #0 8014250: d018 beq.n 8014284 { configASSERT( uxSchedulerSuspended == 0 ); 8014252: 4b14 ldr r3, [pc, #80] @ (80142a4 ) 8014254: 681b ldr r3, [r3, #0] 8014256: 2b00 cmp r3, #0 8014258: d00b beq.n 8014272 __asm volatile 801425a: f04f 0350 mov.w r3, #80 @ 0x50 801425e: f383 8811 msr BASEPRI, r3 8014262: f3bf 8f6f isb sy 8014266: f3bf 8f4f dsb sy 801426a: 60bb str r3, [r7, #8] } 801426c: bf00 nop 801426e: bf00 nop 8014270: e7fd b.n 801426e vTaskSuspendAll(); 8014272: f000 f88b bl 801438c list or removed from the blocked list until the scheduler is resumed. This task cannot be in an event list as it is the currently executing task. */ prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); 8014276: 2100 movs r1, #0 8014278: 6878 ldr r0, [r7, #4] 801427a: f001 f87d bl 8015378 } xAlreadyYielded = xTaskResumeAll(); 801427e: f000 f893 bl 80143a8 8014282: 60f8 str r0, [r7, #12] mtCOVERAGE_TEST_MARKER(); } /* Force a reschedule if xTaskResumeAll has not already done so, we may have put ourselves to sleep. */ if( xAlreadyYielded == pdFALSE ) 8014284: 68fb ldr r3, [r7, #12] 8014286: 2b00 cmp r3, #0 8014288: d107 bne.n 801429a { portYIELD_WITHIN_API(); 801428a: 4b07 ldr r3, [pc, #28] @ (80142a8 ) 801428c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014290: 601a str r2, [r3, #0] 8014292: f3bf 8f4f dsb sy 8014296: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 801429a: bf00 nop 801429c: 3710 adds r7, #16 801429e: 46bd mov sp, r7 80142a0: bd80 pop {r7, pc} 80142a2: bf00 nop 80142a4: 24002aa0 .word 0x24002aa0 80142a8: e000ed04 .word 0xe000ed04 080142ac : #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ /*-----------------------------------------------------------*/ void vTaskStartScheduler( void ) { 80142ac: b580 push {r7, lr} 80142ae: b08a sub sp, #40 @ 0x28 80142b0: af04 add r7, sp, #16 BaseType_t xReturn; /* Add the idle task at the lowest priority. */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxIdleTaskTCBBuffer = NULL; 80142b2: 2300 movs r3, #0 80142b4: 60bb str r3, [r7, #8] StackType_t *pxIdleTaskStackBuffer = NULL; 80142b6: 2300 movs r3, #0 80142b8: 607b str r3, [r7, #4] uint32_t ulIdleTaskStackSize; /* The Idle task is created using user provided RAM - obtain the address of the RAM then create the idle task. */ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); 80142ba: 463a mov r2, r7 80142bc: 1d39 adds r1, r7, #4 80142be: f107 0308 add.w r3, r7, #8 80142c2: 4618 mov r0, r3 80142c4: f7fe fbc0 bl 8012a48 xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, 80142c8: 6839 ldr r1, [r7, #0] 80142ca: 687b ldr r3, [r7, #4] 80142cc: 68ba ldr r2, [r7, #8] 80142ce: 9202 str r2, [sp, #8] 80142d0: 9301 str r3, [sp, #4] 80142d2: 2300 movs r3, #0 80142d4: 9300 str r3, [sp, #0] 80142d6: 2300 movs r3, #0 80142d8: 460a mov r2, r1 80142da: 4924 ldr r1, [pc, #144] @ (801436c ) 80142dc: 4824 ldr r0, [pc, #144] @ (8014370 ) 80142de: f7ff fdf2 bl 8013ec6 80142e2: 4603 mov r3, r0 80142e4: 4a23 ldr r2, [pc, #140] @ (8014374 ) 80142e6: 6013 str r3, [r2, #0] ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ pxIdleTaskStackBuffer, pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ if( xIdleTaskHandle != NULL ) 80142e8: 4b22 ldr r3, [pc, #136] @ (8014374 ) 80142ea: 681b ldr r3, [r3, #0] 80142ec: 2b00 cmp r3, #0 80142ee: d002 beq.n 80142f6 { xReturn = pdPASS; 80142f0: 2301 movs r3, #1 80142f2: 617b str r3, [r7, #20] 80142f4: e001 b.n 80142fa } else { xReturn = pdFAIL; 80142f6: 2300 movs r3, #0 80142f8: 617b str r3, [r7, #20] } #endif /* configSUPPORT_STATIC_ALLOCATION */ #if ( configUSE_TIMERS == 1 ) { if( xReturn == pdPASS ) 80142fa: 697b ldr r3, [r7, #20] 80142fc: 2b01 cmp r3, #1 80142fe: d102 bne.n 8014306 { xReturn = xTimerCreateTimerTask(); 8014300: f001 f88e bl 8015420 8014304: 6178 str r0, [r7, #20] mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_TIMERS */ if( xReturn == pdPASS ) 8014306: 697b ldr r3, [r7, #20] 8014308: 2b01 cmp r3, #1 801430a: d11b bne.n 8014344 __asm volatile 801430c: f04f 0350 mov.w r3, #80 @ 0x50 8014310: f383 8811 msr BASEPRI, r3 8014314: f3bf 8f6f isb sy 8014318: f3bf 8f4f dsb sy 801431c: 613b str r3, [r7, #16] } 801431e: bf00 nop { /* Switch Newlib's _impure_ptr variable to point to the _reent structure specific to the task that will run first. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 8014320: 4b15 ldr r3, [pc, #84] @ (8014378 ) 8014322: 681b ldr r3, [r3, #0] 8014324: 3354 adds r3, #84 @ 0x54 8014326: 4a15 ldr r2, [pc, #84] @ (801437c ) 8014328: 6013 str r3, [r2, #0] } #endif /* configUSE_NEWLIB_REENTRANT */ xNextTaskUnblockTime = portMAX_DELAY; 801432a: 4b15 ldr r3, [pc, #84] @ (8014380 ) 801432c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8014330: 601a str r2, [r3, #0] xSchedulerRunning = pdTRUE; 8014332: 4b14 ldr r3, [pc, #80] @ (8014384 ) 8014334: 2201 movs r2, #1 8014336: 601a str r2, [r3, #0] xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; 8014338: 4b13 ldr r3, [pc, #76] @ (8014388 ) 801433a: 2200 movs r2, #0 801433c: 601a str r2, [r3, #0] traceTASK_SWITCHED_IN(); /* Setting up the timer tick is hardware specific and thus in the portable interface. */ if( xPortStartScheduler() != pdFALSE ) 801433e: f001 fd3f bl 8015dc0 } /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, meaning xIdleTaskHandle is not used anywhere else. */ ( void ) xIdleTaskHandle; } 8014342: e00f b.n 8014364 configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); 8014344: 697b ldr r3, [r7, #20] 8014346: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801434a: d10b bne.n 8014364 __asm volatile 801434c: f04f 0350 mov.w r3, #80 @ 0x50 8014350: f383 8811 msr BASEPRI, r3 8014354: f3bf 8f6f isb sy 8014358: f3bf 8f4f dsb sy 801435c: 60fb str r3, [r7, #12] } 801435e: bf00 nop 8014360: bf00 nop 8014362: e7fd b.n 8014360 } 8014364: bf00 nop 8014366: 3718 adds r7, #24 8014368: 46bd mov sp, r7 801436a: bd80 pop {r7, pc} 801436c: 0801754c .word 0x0801754c 8014370: 08014a29 .word 0x08014a29 8014374: 24002a9c .word 0x24002a9c 8014378: 240025a4 .word 0x240025a4 801437c: 24000054 .word 0x24000054 8014380: 24002a98 .word 0x24002a98 8014384: 24002a84 .word 0x24002a84 8014388: 24002a7c .word 0x24002a7c 0801438c : vPortEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { 801438c: b480 push {r7} 801438e: af00 add r7, sp, #0 do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER(); /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; 8014390: 4b04 ldr r3, [pc, #16] @ (80143a4 ) 8014392: 681b ldr r3, [r3, #0] 8014394: 3301 adds r3, #1 8014396: 4a03 ldr r2, [pc, #12] @ (80143a4 ) 8014398: 6013 str r3, [r2, #0] /* Enforces ordering for ports and optimised compilers that may otherwise place the above increment elsewhere. */ portMEMORY_BARRIER(); } 801439a: bf00 nop 801439c: 46bd mov sp, r7 801439e: f85d 7b04 ldr.w r7, [sp], #4 80143a2: 4770 bx lr 80143a4: 24002aa0 .word 0x24002aa0 080143a8 : #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ BaseType_t xTaskResumeAll( void ) { 80143a8: b580 push {r7, lr} 80143aa: b084 sub sp, #16 80143ac: af00 add r7, sp, #0 TCB_t *pxTCB = NULL; 80143ae: 2300 movs r3, #0 80143b0: 60fb str r3, [r7, #12] BaseType_t xAlreadyYielded = pdFALSE; 80143b2: 2300 movs r3, #0 80143b4: 60bb str r3, [r7, #8] /* If uxSchedulerSuspended is zero then this function does not match a previous call to vTaskSuspendAll(). */ configASSERT( uxSchedulerSuspended ); 80143b6: 4b42 ldr r3, [pc, #264] @ (80144c0 ) 80143b8: 681b ldr r3, [r3, #0] 80143ba: 2b00 cmp r3, #0 80143bc: d10b bne.n 80143d6 __asm volatile 80143be: f04f 0350 mov.w r3, #80 @ 0x50 80143c2: f383 8811 msr BASEPRI, r3 80143c6: f3bf 8f6f isb sy 80143ca: f3bf 8f4f dsb sy 80143ce: 603b str r3, [r7, #0] } 80143d0: bf00 nop 80143d2: bf00 nop 80143d4: e7fd b.n 80143d2 /* It is possible that an ISR caused a task to be removed from an event list while the scheduler was suspended. If this was the case then the removed task will have been added to the xPendingReadyList. Once the scheduler has been resumed it is safe to move all the pending ready tasks from this list into their appropriate ready list. */ taskENTER_CRITICAL(); 80143d6: f001 fd97 bl 8015f08 { --uxSchedulerSuspended; 80143da: 4b39 ldr r3, [pc, #228] @ (80144c0 ) 80143dc: 681b ldr r3, [r3, #0] 80143de: 3b01 subs r3, #1 80143e0: 4a37 ldr r2, [pc, #220] @ (80144c0 ) 80143e2: 6013 str r3, [r2, #0] if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80143e4: 4b36 ldr r3, [pc, #216] @ (80144c0 ) 80143e6: 681b ldr r3, [r3, #0] 80143e8: 2b00 cmp r3, #0 80143ea: d162 bne.n 80144b2 { if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) 80143ec: 4b35 ldr r3, [pc, #212] @ (80144c4 ) 80143ee: 681b ldr r3, [r3, #0] 80143f0: 2b00 cmp r3, #0 80143f2: d05e beq.n 80144b2 { /* Move any readied tasks from the pending list into the appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 80143f4: e02f b.n 8014456 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80143f6: 4b34 ldr r3, [pc, #208] @ (80144c8 ) 80143f8: 68db ldr r3, [r3, #12] 80143fa: 68db ldr r3, [r3, #12] 80143fc: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 80143fe: 68fb ldr r3, [r7, #12] 8014400: 3318 adds r3, #24 8014402: 4618 mov r0, r3 8014404: f7fe fbde bl 8012bc4 ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8014408: 68fb ldr r3, [r7, #12] 801440a: 3304 adds r3, #4 801440c: 4618 mov r0, r3 801440e: f7fe fbd9 bl 8012bc4 prvAddTaskToReadyList( pxTCB ); 8014412: 68fb ldr r3, [r7, #12] 8014414: 6ada ldr r2, [r3, #44] @ 0x2c 8014416: 4b2d ldr r3, [pc, #180] @ (80144cc ) 8014418: 681b ldr r3, [r3, #0] 801441a: 429a cmp r2, r3 801441c: d903 bls.n 8014426 801441e: 68fb ldr r3, [r7, #12] 8014420: 6adb ldr r3, [r3, #44] @ 0x2c 8014422: 4a2a ldr r2, [pc, #168] @ (80144cc ) 8014424: 6013 str r3, [r2, #0] 8014426: 68fb ldr r3, [r7, #12] 8014428: 6ada ldr r2, [r3, #44] @ 0x2c 801442a: 4613 mov r3, r2 801442c: 009b lsls r3, r3, #2 801442e: 4413 add r3, r2 8014430: 009b lsls r3, r3, #2 8014432: 4a27 ldr r2, [pc, #156] @ (80144d0 ) 8014434: 441a add r2, r3 8014436: 68fb ldr r3, [r7, #12] 8014438: 3304 adds r3, #4 801443a: 4619 mov r1, r3 801443c: 4610 mov r0, r2 801443e: f7fe fb64 bl 8012b0a /* If the moved task has a priority higher than the current task then a yield must be performed. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 8014442: 68fb ldr r3, [r7, #12] 8014444: 6ada ldr r2, [r3, #44] @ 0x2c 8014446: 4b23 ldr r3, [pc, #140] @ (80144d4 ) 8014448: 681b ldr r3, [r3, #0] 801444a: 6adb ldr r3, [r3, #44] @ 0x2c 801444c: 429a cmp r2, r3 801444e: d302 bcc.n 8014456 { xYieldPending = pdTRUE; 8014450: 4b21 ldr r3, [pc, #132] @ (80144d8 ) 8014452: 2201 movs r2, #1 8014454: 601a str r2, [r3, #0] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 8014456: 4b1c ldr r3, [pc, #112] @ (80144c8 ) 8014458: 681b ldr r3, [r3, #0] 801445a: 2b00 cmp r3, #0 801445c: d1cb bne.n 80143f6 { mtCOVERAGE_TEST_MARKER(); } } if( pxTCB != NULL ) 801445e: 68fb ldr r3, [r7, #12] 8014460: 2b00 cmp r3, #0 8014462: d001 beq.n 8014468 which may have prevented the next unblock time from being re-calculated, in which case re-calculate it now. Mainly important for low power tickless implementations, where this can prevent an unnecessary exit from low power state. */ prvResetNextTaskUnblockTime(); 8014464: f000 fb9c bl 8014ba0 /* If any ticks occurred while the scheduler was suspended then they should be processed now. This ensures the tick count does not slip, and that any delayed tasks are resumed at the correct time. */ { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ 8014468: 4b1c ldr r3, [pc, #112] @ (80144dc ) 801446a: 681b ldr r3, [r3, #0] 801446c: 607b str r3, [r7, #4] if( xPendedCounts > ( TickType_t ) 0U ) 801446e: 687b ldr r3, [r7, #4] 8014470: 2b00 cmp r3, #0 8014472: d010 beq.n 8014496 { do { if( xTaskIncrementTick() != pdFALSE ) 8014474: f000 f846 bl 8014504 8014478: 4603 mov r3, r0 801447a: 2b00 cmp r3, #0 801447c: d002 beq.n 8014484 { xYieldPending = pdTRUE; 801447e: 4b16 ldr r3, [pc, #88] @ (80144d8 ) 8014480: 2201 movs r2, #1 8014482: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } --xPendedCounts; 8014484: 687b ldr r3, [r7, #4] 8014486: 3b01 subs r3, #1 8014488: 607b str r3, [r7, #4] } while( xPendedCounts > ( TickType_t ) 0U ); 801448a: 687b ldr r3, [r7, #4] 801448c: 2b00 cmp r3, #0 801448e: d1f1 bne.n 8014474 xPendedTicks = 0; 8014490: 4b12 ldr r3, [pc, #72] @ (80144dc ) 8014492: 2200 movs r2, #0 8014494: 601a str r2, [r3, #0] { mtCOVERAGE_TEST_MARKER(); } } if( xYieldPending != pdFALSE ) 8014496: 4b10 ldr r3, [pc, #64] @ (80144d8 ) 8014498: 681b ldr r3, [r3, #0] 801449a: 2b00 cmp r3, #0 801449c: d009 beq.n 80144b2 { #if( configUSE_PREEMPTION != 0 ) { xAlreadyYielded = pdTRUE; 801449e: 2301 movs r3, #1 80144a0: 60bb str r3, [r7, #8] } #endif taskYIELD_IF_USING_PREEMPTION(); 80144a2: 4b0f ldr r3, [pc, #60] @ (80144e0 ) 80144a4: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80144a8: 601a str r2, [r3, #0] 80144aa: f3bf 8f4f dsb sy 80144ae: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 80144b2: f001 fd5b bl 8015f6c return xAlreadyYielded; 80144b6: 68bb ldr r3, [r7, #8] } 80144b8: 4618 mov r0, r3 80144ba: 3710 adds r7, #16 80144bc: 46bd mov sp, r7 80144be: bd80 pop {r7, pc} 80144c0: 24002aa0 .word 0x24002aa0 80144c4: 24002a78 .word 0x24002a78 80144c8: 24002a38 .word 0x24002a38 80144cc: 24002a80 .word 0x24002a80 80144d0: 240025a8 .word 0x240025a8 80144d4: 240025a4 .word 0x240025a4 80144d8: 24002a8c .word 0x24002a8c 80144dc: 24002a88 .word 0x24002a88 80144e0: e000ed04 .word 0xe000ed04 080144e4 : /*-----------------------------------------------------------*/ TickType_t xTaskGetTickCount( void ) { 80144e4: b480 push {r7} 80144e6: b083 sub sp, #12 80144e8: af00 add r7, sp, #0 TickType_t xTicks; /* Critical section required if running on a 16 bit processor. */ portTICK_TYPE_ENTER_CRITICAL(); { xTicks = xTickCount; 80144ea: 4b05 ldr r3, [pc, #20] @ (8014500 ) 80144ec: 681b ldr r3, [r3, #0] 80144ee: 607b str r3, [r7, #4] } portTICK_TYPE_EXIT_CRITICAL(); return xTicks; 80144f0: 687b ldr r3, [r7, #4] } 80144f2: 4618 mov r0, r3 80144f4: 370c adds r7, #12 80144f6: 46bd mov sp, r7 80144f8: f85d 7b04 ldr.w r7, [sp], #4 80144fc: 4770 bx lr 80144fe: bf00 nop 8014500: 24002a7c .word 0x24002a7c 08014504 : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { 8014504: b580 push {r7, lr} 8014506: b086 sub sp, #24 8014508: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; 801450a: 2300 movs r3, #0 801450c: 617b str r3, [r7, #20] /* Called by the portable layer each time a tick interrupt occurs. Increments the tick then checks to see if the new tick value will cause any tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 801450e: 4b4f ldr r3, [pc, #316] @ (801464c ) 8014510: 681b ldr r3, [r3, #0] 8014512: 2b00 cmp r3, #0 8014514: f040 8090 bne.w 8014638 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 8014518: 4b4d ldr r3, [pc, #308] @ (8014650 ) 801451a: 681b ldr r3, [r3, #0] 801451c: 3301 adds r3, #1 801451e: 613b str r3, [r7, #16] /* Increment the RTOS tick, switching the delayed and overflowed delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; 8014520: 4a4b ldr r2, [pc, #300] @ (8014650 ) 8014522: 693b ldr r3, [r7, #16] 8014524: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ 8014526: 693b ldr r3, [r7, #16] 8014528: 2b00 cmp r3, #0 801452a: d121 bne.n 8014570 { taskSWITCH_DELAYED_LISTS(); 801452c: 4b49 ldr r3, [pc, #292] @ (8014654 ) 801452e: 681b ldr r3, [r3, #0] 8014530: 681b ldr r3, [r3, #0] 8014532: 2b00 cmp r3, #0 8014534: d00b beq.n 801454e __asm volatile 8014536: f04f 0350 mov.w r3, #80 @ 0x50 801453a: f383 8811 msr BASEPRI, r3 801453e: f3bf 8f6f isb sy 8014542: f3bf 8f4f dsb sy 8014546: 603b str r3, [r7, #0] } 8014548: bf00 nop 801454a: bf00 nop 801454c: e7fd b.n 801454a 801454e: 4b41 ldr r3, [pc, #260] @ (8014654 ) 8014550: 681b ldr r3, [r3, #0] 8014552: 60fb str r3, [r7, #12] 8014554: 4b40 ldr r3, [pc, #256] @ (8014658 ) 8014556: 681b ldr r3, [r3, #0] 8014558: 4a3e ldr r2, [pc, #248] @ (8014654 ) 801455a: 6013 str r3, [r2, #0] 801455c: 4a3e ldr r2, [pc, #248] @ (8014658 ) 801455e: 68fb ldr r3, [r7, #12] 8014560: 6013 str r3, [r2, #0] 8014562: 4b3e ldr r3, [pc, #248] @ (801465c ) 8014564: 681b ldr r3, [r3, #0] 8014566: 3301 adds r3, #1 8014568: 4a3c ldr r2, [pc, #240] @ (801465c ) 801456a: 6013 str r3, [r2, #0] 801456c: f000 fb18 bl 8014ba0 /* See if this tick has made a timeout expire. Tasks are stored in the queue in the order of their wake time - meaning once one task has been found whose block time has not expired there is no need to look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) 8014570: 4b3b ldr r3, [pc, #236] @ (8014660 ) 8014572: 681b ldr r3, [r3, #0] 8014574: 693a ldr r2, [r7, #16] 8014576: 429a cmp r2, r3 8014578: d349 bcc.n 801460e { for( ;; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 801457a: 4b36 ldr r3, [pc, #216] @ (8014654 ) 801457c: 681b ldr r3, [r3, #0] 801457e: 681b ldr r3, [r3, #0] 8014580: 2b00 cmp r3, #0 8014582: d104 bne.n 801458e /* The delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8014584: 4b36 ldr r3, [pc, #216] @ (8014660 ) 8014586: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801458a: 601a str r2, [r3, #0] break; 801458c: e03f b.n 801460e { /* The delayed list is not empty, get the value of the item at the head of the delayed list. This is the time at which the task at the head of the delayed list must be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 801458e: 4b31 ldr r3, [pc, #196] @ (8014654 ) 8014590: 681b ldr r3, [r3, #0] 8014592: 68db ldr r3, [r3, #12] 8014594: 68db ldr r3, [r3, #12] 8014596: 60bb str r3, [r7, #8] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); 8014598: 68bb ldr r3, [r7, #8] 801459a: 685b ldr r3, [r3, #4] 801459c: 607b str r3, [r7, #4] if( xConstTickCount < xItemValue ) 801459e: 693a ldr r2, [r7, #16] 80145a0: 687b ldr r3, [r7, #4] 80145a2: 429a cmp r2, r3 80145a4: d203 bcs.n 80145ae /* It is not time to unblock this item yet, but the item value is the time at which the task at the head of the blocked list must be removed from the Blocked state - so record the item value in xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; 80145a6: 4a2e ldr r2, [pc, #184] @ (8014660 ) 80145a8: 687b ldr r3, [r7, #4] 80145aa: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ 80145ac: e02f b.n 801460e { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80145ae: 68bb ldr r3, [r7, #8] 80145b0: 3304 adds r3, #4 80145b2: 4618 mov r0, r3 80145b4: f7fe fb06 bl 8012bc4 /* Is the task waiting on an event also? If so remove it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 80145b8: 68bb ldr r3, [r7, #8] 80145ba: 6a9b ldr r3, [r3, #40] @ 0x28 80145bc: 2b00 cmp r3, #0 80145be: d004 beq.n 80145ca { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 80145c0: 68bb ldr r3, [r7, #8] 80145c2: 3318 adds r3, #24 80145c4: 4618 mov r0, r3 80145c6: f7fe fafd bl 8012bc4 mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready list. */ prvAddTaskToReadyList( pxTCB ); 80145ca: 68bb ldr r3, [r7, #8] 80145cc: 6ada ldr r2, [r3, #44] @ 0x2c 80145ce: 4b25 ldr r3, [pc, #148] @ (8014664 ) 80145d0: 681b ldr r3, [r3, #0] 80145d2: 429a cmp r2, r3 80145d4: d903 bls.n 80145de 80145d6: 68bb ldr r3, [r7, #8] 80145d8: 6adb ldr r3, [r3, #44] @ 0x2c 80145da: 4a22 ldr r2, [pc, #136] @ (8014664 ) 80145dc: 6013 str r3, [r2, #0] 80145de: 68bb ldr r3, [r7, #8] 80145e0: 6ada ldr r2, [r3, #44] @ 0x2c 80145e2: 4613 mov r3, r2 80145e4: 009b lsls r3, r3, #2 80145e6: 4413 add r3, r2 80145e8: 009b lsls r3, r3, #2 80145ea: 4a1f ldr r2, [pc, #124] @ (8014668 ) 80145ec: 441a add r2, r3 80145ee: 68bb ldr r3, [r7, #8] 80145f0: 3304 adds r3, #4 80145f2: 4619 mov r1, r3 80145f4: 4610 mov r0, r2 80145f6: f7fe fa88 bl 8012b0a { /* Preemption is on, but a context switch should only be performed if the unblocked task has a priority that is equal to or higher than the currently executing task. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 80145fa: 68bb ldr r3, [r7, #8] 80145fc: 6ada ldr r2, [r3, #44] @ 0x2c 80145fe: 4b1b ldr r3, [pc, #108] @ (801466c ) 8014600: 681b ldr r3, [r3, #0] 8014602: 6adb ldr r3, [r3, #44] @ 0x2c 8014604: 429a cmp r2, r3 8014606: d3b8 bcc.n 801457a { xSwitchRequired = pdTRUE; 8014608: 2301 movs r3, #1 801460a: 617b str r3, [r7, #20] if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 801460c: e7b5 b.n 801457a /* Tasks of equal priority to the currently running task will share processing time (time slice) if preemption is on, and the application writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 801460e: 4b17 ldr r3, [pc, #92] @ (801466c ) 8014610: 681b ldr r3, [r3, #0] 8014612: 6ada ldr r2, [r3, #44] @ 0x2c 8014614: 4914 ldr r1, [pc, #80] @ (8014668 ) 8014616: 4613 mov r3, r2 8014618: 009b lsls r3, r3, #2 801461a: 4413 add r3, r2 801461c: 009b lsls r3, r3, #2 801461e: 440b add r3, r1 8014620: 681b ldr r3, [r3, #0] 8014622: 2b01 cmp r3, #1 8014624: d901 bls.n 801462a { xSwitchRequired = pdTRUE; 8014626: 2301 movs r3, #1 8014628: 617b str r3, [r7, #20] } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) 801462a: 4b11 ldr r3, [pc, #68] @ (8014670 ) 801462c: 681b ldr r3, [r3, #0] 801462e: 2b00 cmp r3, #0 8014630: d007 beq.n 8014642 { xSwitchRequired = pdTRUE; 8014632: 2301 movs r3, #1 8014634: 617b str r3, [r7, #20] 8014636: e004 b.n 8014642 } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; 8014638: 4b0e ldr r3, [pc, #56] @ (8014674 ) 801463a: 681b ldr r3, [r3, #0] 801463c: 3301 adds r3, #1 801463e: 4a0d ldr r2, [pc, #52] @ (8014674 ) 8014640: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; 8014642: 697b ldr r3, [r7, #20] } 8014644: 4618 mov r0, r3 8014646: 3718 adds r7, #24 8014648: 46bd mov sp, r7 801464a: bd80 pop {r7, pc} 801464c: 24002aa0 .word 0x24002aa0 8014650: 24002a7c .word 0x24002a7c 8014654: 24002a30 .word 0x24002a30 8014658: 24002a34 .word 0x24002a34 801465c: 24002a90 .word 0x24002a90 8014660: 24002a98 .word 0x24002a98 8014664: 24002a80 .word 0x24002a80 8014668: 240025a8 .word 0x240025a8 801466c: 240025a4 .word 0x240025a4 8014670: 24002a8c .word 0x24002a8c 8014674: 24002a88 .word 0x24002a88 08014678 : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { 8014678: b580 push {r7, lr} 801467a: b084 sub sp, #16 801467c: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) 801467e: 4b32 ldr r3, [pc, #200] @ (8014748 ) 8014680: 681b ldr r3, [r3, #0] 8014682: 2b00 cmp r3, #0 8014684: d003 beq.n 801468e { /* The scheduler is currently suspended - do not allow a context switch. */ xYieldPending = pdTRUE; 8014686: 4b31 ldr r3, [pc, #196] @ (801474c ) 8014688: 2201 movs r2, #1 801468a: 601a str r2, [r3, #0] for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ } } 801468c: e058 b.n 8014740 xYieldPending = pdFALSE; 801468e: 4b2f ldr r3, [pc, #188] @ (801474c ) 8014690: 2200 movs r2, #0 8014692: 601a str r2, [r3, #0] taskCHECK_FOR_STACK_OVERFLOW(); 8014694: 4b2e ldr r3, [pc, #184] @ (8014750 ) 8014696: 681b ldr r3, [r3, #0] 8014698: 681a ldr r2, [r3, #0] 801469a: 4b2d ldr r3, [pc, #180] @ (8014750 ) 801469c: 681b ldr r3, [r3, #0] 801469e: 6b1b ldr r3, [r3, #48] @ 0x30 80146a0: 429a cmp r2, r3 80146a2: d808 bhi.n 80146b6 80146a4: 4b2a ldr r3, [pc, #168] @ (8014750 ) 80146a6: 681a ldr r2, [r3, #0] 80146a8: 4b29 ldr r3, [pc, #164] @ (8014750 ) 80146aa: 681b ldr r3, [r3, #0] 80146ac: 3334 adds r3, #52 @ 0x34 80146ae: 4619 mov r1, r3 80146b0: 4610 mov r0, r2 80146b2: f7eb ffdd bl 8000670 taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80146b6: 4b27 ldr r3, [pc, #156] @ (8014754 ) 80146b8: 681b ldr r3, [r3, #0] 80146ba: 60fb str r3, [r7, #12] 80146bc: e011 b.n 80146e2 80146be: 68fb ldr r3, [r7, #12] 80146c0: 2b00 cmp r3, #0 80146c2: d10b bne.n 80146dc __asm volatile 80146c4: f04f 0350 mov.w r3, #80 @ 0x50 80146c8: f383 8811 msr BASEPRI, r3 80146cc: f3bf 8f6f isb sy 80146d0: f3bf 8f4f dsb sy 80146d4: 607b str r3, [r7, #4] } 80146d6: bf00 nop 80146d8: bf00 nop 80146da: e7fd b.n 80146d8 80146dc: 68fb ldr r3, [r7, #12] 80146de: 3b01 subs r3, #1 80146e0: 60fb str r3, [r7, #12] 80146e2: 491d ldr r1, [pc, #116] @ (8014758 ) 80146e4: 68fa ldr r2, [r7, #12] 80146e6: 4613 mov r3, r2 80146e8: 009b lsls r3, r3, #2 80146ea: 4413 add r3, r2 80146ec: 009b lsls r3, r3, #2 80146ee: 440b add r3, r1 80146f0: 681b ldr r3, [r3, #0] 80146f2: 2b00 cmp r3, #0 80146f4: d0e3 beq.n 80146be 80146f6: 68fa ldr r2, [r7, #12] 80146f8: 4613 mov r3, r2 80146fa: 009b lsls r3, r3, #2 80146fc: 4413 add r3, r2 80146fe: 009b lsls r3, r3, #2 8014700: 4a15 ldr r2, [pc, #84] @ (8014758 ) 8014702: 4413 add r3, r2 8014704: 60bb str r3, [r7, #8] 8014706: 68bb ldr r3, [r7, #8] 8014708: 685b ldr r3, [r3, #4] 801470a: 685a ldr r2, [r3, #4] 801470c: 68bb ldr r3, [r7, #8] 801470e: 605a str r2, [r3, #4] 8014710: 68bb ldr r3, [r7, #8] 8014712: 685a ldr r2, [r3, #4] 8014714: 68bb ldr r3, [r7, #8] 8014716: 3308 adds r3, #8 8014718: 429a cmp r2, r3 801471a: d104 bne.n 8014726 801471c: 68bb ldr r3, [r7, #8] 801471e: 685b ldr r3, [r3, #4] 8014720: 685a ldr r2, [r3, #4] 8014722: 68bb ldr r3, [r7, #8] 8014724: 605a str r2, [r3, #4] 8014726: 68bb ldr r3, [r7, #8] 8014728: 685b ldr r3, [r3, #4] 801472a: 68db ldr r3, [r3, #12] 801472c: 4a08 ldr r2, [pc, #32] @ (8014750 ) 801472e: 6013 str r3, [r2, #0] 8014730: 4a08 ldr r2, [pc, #32] @ (8014754 ) 8014732: 68fb ldr r3, [r7, #12] 8014734: 6013 str r3, [r2, #0] _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 8014736: 4b06 ldr r3, [pc, #24] @ (8014750 ) 8014738: 681b ldr r3, [r3, #0] 801473a: 3354 adds r3, #84 @ 0x54 801473c: 4a07 ldr r2, [pc, #28] @ (801475c ) 801473e: 6013 str r3, [r2, #0] } 8014740: bf00 nop 8014742: 3710 adds r7, #16 8014744: 46bd mov sp, r7 8014746: bd80 pop {r7, pc} 8014748: 24002aa0 .word 0x24002aa0 801474c: 24002a8c .word 0x24002a8c 8014750: 240025a4 .word 0x240025a4 8014754: 24002a80 .word 0x24002a80 8014758: 240025a8 .word 0x240025a8 801475c: 24000054 .word 0x24000054 08014760 : /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { 8014760: b580 push {r7, lr} 8014762: b084 sub sp, #16 8014764: af00 add r7, sp, #0 8014766: 6078 str r0, [r7, #4] 8014768: 6039 str r1, [r7, #0] configASSERT( pxEventList ); 801476a: 687b ldr r3, [r7, #4] 801476c: 2b00 cmp r3, #0 801476e: d10b bne.n 8014788 __asm volatile 8014770: f04f 0350 mov.w r3, #80 @ 0x50 8014774: f383 8811 msr BASEPRI, r3 8014778: f3bf 8f6f isb sy 801477c: f3bf 8f4f dsb sy 8014780: 60fb str r3, [r7, #12] } 8014782: bf00 nop 8014784: bf00 nop 8014786: e7fd b.n 8014784 /* Place the event list item of the TCB in the appropriate event list. This is placed in the list in priority order so the highest priority task is the first to be woken by the event. The queue that contains the event list is locked, preventing simultaneous access from interrupts. */ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 8014788: 4b07 ldr r3, [pc, #28] @ (80147a8 ) 801478a: 681b ldr r3, [r3, #0] 801478c: 3318 adds r3, #24 801478e: 4619 mov r1, r3 8014790: 6878 ldr r0, [r7, #4] 8014792: f7fe f9de bl 8012b52 prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 8014796: 2101 movs r1, #1 8014798: 6838 ldr r0, [r7, #0] 801479a: f000 fded bl 8015378 } 801479e: bf00 nop 80147a0: 3710 adds r7, #16 80147a2: 46bd mov sp, r7 80147a4: bd80 pop {r7, pc} 80147a6: bf00 nop 80147a8: 240025a4 .word 0x240025a4 080147ac : /*-----------------------------------------------------------*/ #if( configUSE_TIMERS == 1 ) void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 80147ac: b580 push {r7, lr} 80147ae: b086 sub sp, #24 80147b0: af00 add r7, sp, #0 80147b2: 60f8 str r0, [r7, #12] 80147b4: 60b9 str r1, [r7, #8] 80147b6: 607a str r2, [r7, #4] configASSERT( pxEventList ); 80147b8: 68fb ldr r3, [r7, #12] 80147ba: 2b00 cmp r3, #0 80147bc: d10b bne.n 80147d6 __asm volatile 80147be: f04f 0350 mov.w r3, #80 @ 0x50 80147c2: f383 8811 msr BASEPRI, r3 80147c6: f3bf 8f6f isb sy 80147ca: f3bf 8f4f dsb sy 80147ce: 617b str r3, [r7, #20] } 80147d0: bf00 nop 80147d2: bf00 nop 80147d4: e7fd b.n 80147d2 /* Place the event list item of the TCB in the appropriate event list. In this case it is assume that this is the only task that is going to be waiting on this event list, so the faster vListInsertEnd() function can be used in place of vListInsert. */ vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 80147d6: 4b0a ldr r3, [pc, #40] @ (8014800 ) 80147d8: 681b ldr r3, [r3, #0] 80147da: 3318 adds r3, #24 80147dc: 4619 mov r1, r3 80147de: 68f8 ldr r0, [r7, #12] 80147e0: f7fe f993 bl 8012b0a /* If the task should block indefinitely then set the block time to a value that will be recognised as an indefinite delay inside the prvAddCurrentTaskToDelayedList() function. */ if( xWaitIndefinitely != pdFALSE ) 80147e4: 687b ldr r3, [r7, #4] 80147e6: 2b00 cmp r3, #0 80147e8: d002 beq.n 80147f0 { xTicksToWait = portMAX_DELAY; 80147ea: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80147ee: 60bb str r3, [r7, #8] } traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); 80147f0: 6879 ldr r1, [r7, #4] 80147f2: 68b8 ldr r0, [r7, #8] 80147f4: f000 fdc0 bl 8015378 } 80147f8: bf00 nop 80147fa: 3718 adds r7, #24 80147fc: 46bd mov sp, r7 80147fe: bd80 pop {r7, pc} 8014800: 240025a4 .word 0x240025a4 08014804 : #endif /* configUSE_TIMERS */ /*-----------------------------------------------------------*/ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { 8014804: b580 push {r7, lr} 8014806: b086 sub sp, #24 8014808: af00 add r7, sp, #0 801480a: 6078 str r0, [r7, #4] get called - the lock count on the queue will get modified instead. This means exclusive access to the event list is guaranteed here. This function assumes that a check has already been made to ensure that pxEventList is not empty. */ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 801480c: 687b ldr r3, [r7, #4] 801480e: 68db ldr r3, [r3, #12] 8014810: 68db ldr r3, [r3, #12] 8014812: 613b str r3, [r7, #16] configASSERT( pxUnblockedTCB ); 8014814: 693b ldr r3, [r7, #16] 8014816: 2b00 cmp r3, #0 8014818: d10b bne.n 8014832 __asm volatile 801481a: f04f 0350 mov.w r3, #80 @ 0x50 801481e: f383 8811 msr BASEPRI, r3 8014822: f3bf 8f6f isb sy 8014826: f3bf 8f4f dsb sy 801482a: 60fb str r3, [r7, #12] } 801482c: bf00 nop 801482e: bf00 nop 8014830: e7fd b.n 801482e ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); 8014832: 693b ldr r3, [r7, #16] 8014834: 3318 adds r3, #24 8014836: 4618 mov r0, r3 8014838: f7fe f9c4 bl 8012bc4 if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 801483c: 4b1d ldr r3, [pc, #116] @ (80148b4 ) 801483e: 681b ldr r3, [r3, #0] 8014840: 2b00 cmp r3, #0 8014842: d11d bne.n 8014880 { ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); 8014844: 693b ldr r3, [r7, #16] 8014846: 3304 adds r3, #4 8014848: 4618 mov r0, r3 801484a: f7fe f9bb bl 8012bc4 prvAddTaskToReadyList( pxUnblockedTCB ); 801484e: 693b ldr r3, [r7, #16] 8014850: 6ada ldr r2, [r3, #44] @ 0x2c 8014852: 4b19 ldr r3, [pc, #100] @ (80148b8 ) 8014854: 681b ldr r3, [r3, #0] 8014856: 429a cmp r2, r3 8014858: d903 bls.n 8014862 801485a: 693b ldr r3, [r7, #16] 801485c: 6adb ldr r3, [r3, #44] @ 0x2c 801485e: 4a16 ldr r2, [pc, #88] @ (80148b8 ) 8014860: 6013 str r3, [r2, #0] 8014862: 693b ldr r3, [r7, #16] 8014864: 6ada ldr r2, [r3, #44] @ 0x2c 8014866: 4613 mov r3, r2 8014868: 009b lsls r3, r3, #2 801486a: 4413 add r3, r2 801486c: 009b lsls r3, r3, #2 801486e: 4a13 ldr r2, [pc, #76] @ (80148bc ) 8014870: 441a add r2, r3 8014872: 693b ldr r3, [r7, #16] 8014874: 3304 adds r3, #4 8014876: 4619 mov r1, r3 8014878: 4610 mov r0, r2 801487a: f7fe f946 bl 8012b0a 801487e: e005 b.n 801488c } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); 8014880: 693b ldr r3, [r7, #16] 8014882: 3318 adds r3, #24 8014884: 4619 mov r1, r3 8014886: 480e ldr r0, [pc, #56] @ (80148c0 ) 8014888: f7fe f93f bl 8012b0a } if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) 801488c: 693b ldr r3, [r7, #16] 801488e: 6ada ldr r2, [r3, #44] @ 0x2c 8014890: 4b0c ldr r3, [pc, #48] @ (80148c4 ) 8014892: 681b ldr r3, [r3, #0] 8014894: 6adb ldr r3, [r3, #44] @ 0x2c 8014896: 429a cmp r2, r3 8014898: d905 bls.n 80148a6 { /* Return true if the task removed from the event list has a higher priority than the calling task. This allows the calling task to know if it should force a context switch now. */ xReturn = pdTRUE; 801489a: 2301 movs r3, #1 801489c: 617b str r3, [r7, #20] /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 801489e: 4b0a ldr r3, [pc, #40] @ (80148c8 ) 80148a0: 2201 movs r2, #1 80148a2: 601a str r2, [r3, #0] 80148a4: e001 b.n 80148aa } else { xReturn = pdFALSE; 80148a6: 2300 movs r3, #0 80148a8: 617b str r3, [r7, #20] } return xReturn; 80148aa: 697b ldr r3, [r7, #20] } 80148ac: 4618 mov r0, r3 80148ae: 3718 adds r7, #24 80148b0: 46bd mov sp, r7 80148b2: bd80 pop {r7, pc} 80148b4: 24002aa0 .word 0x24002aa0 80148b8: 24002a80 .word 0x24002a80 80148bc: 240025a8 .word 0x240025a8 80148c0: 24002a38 .word 0x24002a38 80148c4: 240025a4 .word 0x240025a4 80148c8: 24002a8c .word 0x24002a8c 080148cc : } } /*-----------------------------------------------------------*/ void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) { 80148cc: b580 push {r7, lr} 80148ce: b084 sub sp, #16 80148d0: af00 add r7, sp, #0 80148d2: 6078 str r0, [r7, #4] configASSERT( pxTimeOut ); 80148d4: 687b ldr r3, [r7, #4] 80148d6: 2b00 cmp r3, #0 80148d8: d10b bne.n 80148f2 __asm volatile 80148da: f04f 0350 mov.w r3, #80 @ 0x50 80148de: f383 8811 msr BASEPRI, r3 80148e2: f3bf 8f6f isb sy 80148e6: f3bf 8f4f dsb sy 80148ea: 60fb str r3, [r7, #12] } 80148ec: bf00 nop 80148ee: bf00 nop 80148f0: e7fd b.n 80148ee taskENTER_CRITICAL(); 80148f2: f001 fb09 bl 8015f08 { pxTimeOut->xOverflowCount = xNumOfOverflows; 80148f6: 4b07 ldr r3, [pc, #28] @ (8014914 ) 80148f8: 681a ldr r2, [r3, #0] 80148fa: 687b ldr r3, [r7, #4] 80148fc: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 80148fe: 4b06 ldr r3, [pc, #24] @ (8014918 ) 8014900: 681a ldr r2, [r3, #0] 8014902: 687b ldr r3, [r7, #4] 8014904: 605a str r2, [r3, #4] } taskEXIT_CRITICAL(); 8014906: f001 fb31 bl 8015f6c } 801490a: bf00 nop 801490c: 3710 adds r7, #16 801490e: 46bd mov sp, r7 8014910: bd80 pop {r7, pc} 8014912: bf00 nop 8014914: 24002a90 .word 0x24002a90 8014918: 24002a7c .word 0x24002a7c 0801491c : /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { 801491c: b480 push {r7} 801491e: b083 sub sp, #12 8014920: af00 add r7, sp, #0 8014922: 6078 str r0, [r7, #4] /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; 8014924: 4b06 ldr r3, [pc, #24] @ (8014940 ) 8014926: 681a ldr r2, [r3, #0] 8014928: 687b ldr r3, [r7, #4] 801492a: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 801492c: 4b05 ldr r3, [pc, #20] @ (8014944 ) 801492e: 681a ldr r2, [r3, #0] 8014930: 687b ldr r3, [r7, #4] 8014932: 605a str r2, [r3, #4] } 8014934: bf00 nop 8014936: 370c adds r7, #12 8014938: 46bd mov sp, r7 801493a: f85d 7b04 ldr.w r7, [sp], #4 801493e: 4770 bx lr 8014940: 24002a90 .word 0x24002a90 8014944: 24002a7c .word 0x24002a7c 08014948 : /*-----------------------------------------------------------*/ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) { 8014948: b580 push {r7, lr} 801494a: b088 sub sp, #32 801494c: af00 add r7, sp, #0 801494e: 6078 str r0, [r7, #4] 8014950: 6039 str r1, [r7, #0] BaseType_t xReturn; configASSERT( pxTimeOut ); 8014952: 687b ldr r3, [r7, #4] 8014954: 2b00 cmp r3, #0 8014956: d10b bne.n 8014970 __asm volatile 8014958: f04f 0350 mov.w r3, #80 @ 0x50 801495c: f383 8811 msr BASEPRI, r3 8014960: f3bf 8f6f isb sy 8014964: f3bf 8f4f dsb sy 8014968: 613b str r3, [r7, #16] } 801496a: bf00 nop 801496c: bf00 nop 801496e: e7fd b.n 801496c configASSERT( pxTicksToWait ); 8014970: 683b ldr r3, [r7, #0] 8014972: 2b00 cmp r3, #0 8014974: d10b bne.n 801498e __asm volatile 8014976: f04f 0350 mov.w r3, #80 @ 0x50 801497a: f383 8811 msr BASEPRI, r3 801497e: f3bf 8f6f isb sy 8014982: f3bf 8f4f dsb sy 8014986: 60fb str r3, [r7, #12] } 8014988: bf00 nop 801498a: bf00 nop 801498c: e7fd b.n 801498a taskENTER_CRITICAL(); 801498e: f001 fabb bl 8015f08 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; 8014992: 4b1d ldr r3, [pc, #116] @ (8014a08 ) 8014994: 681b ldr r3, [r3, #0] 8014996: 61bb str r3, [r7, #24] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; 8014998: 687b ldr r3, [r7, #4] 801499a: 685b ldr r3, [r3, #4] 801499c: 69ba ldr r2, [r7, #24] 801499e: 1ad3 subs r3, r2, r3 80149a0: 617b str r3, [r7, #20] } else #endif #if ( INCLUDE_vTaskSuspend == 1 ) if( *pxTicksToWait == portMAX_DELAY ) 80149a2: 683b ldr r3, [r7, #0] 80149a4: 681b ldr r3, [r3, #0] 80149a6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80149aa: d102 bne.n 80149b2 { /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is the maximum block time then the task should block indefinitely, and therefore never time out. */ xReturn = pdFALSE; 80149ac: 2300 movs r3, #0 80149ae: 61fb str r3, [r7, #28] 80149b0: e023 b.n 80149fa } else #endif if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ 80149b2: 687b ldr r3, [r7, #4] 80149b4: 681a ldr r2, [r3, #0] 80149b6: 4b15 ldr r3, [pc, #84] @ (8014a0c ) 80149b8: 681b ldr r3, [r3, #0] 80149ba: 429a cmp r2, r3 80149bc: d007 beq.n 80149ce 80149be: 687b ldr r3, [r7, #4] 80149c0: 685b ldr r3, [r3, #4] 80149c2: 69ba ldr r2, [r7, #24] 80149c4: 429a cmp r2, r3 80149c6: d302 bcc.n 80149ce /* The tick count is greater than the time at which vTaskSetTimeout() was called, but has also overflowed since vTaskSetTimeOut() was called. It must have wrapped all the way around and gone past again. This passed since vTaskSetTimeout() was called. */ xReturn = pdTRUE; 80149c8: 2301 movs r3, #1 80149ca: 61fb str r3, [r7, #28] 80149cc: e015 b.n 80149fa } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ 80149ce: 683b ldr r3, [r7, #0] 80149d0: 681b ldr r3, [r3, #0] 80149d2: 697a ldr r2, [r7, #20] 80149d4: 429a cmp r2, r3 80149d6: d20b bcs.n 80149f0 { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; 80149d8: 683b ldr r3, [r7, #0] 80149da: 681a ldr r2, [r3, #0] 80149dc: 697b ldr r3, [r7, #20] 80149de: 1ad2 subs r2, r2, r3 80149e0: 683b ldr r3, [r7, #0] 80149e2: 601a str r2, [r3, #0] vTaskInternalSetTimeOutState( pxTimeOut ); 80149e4: 6878 ldr r0, [r7, #4] 80149e6: f7ff ff99 bl 801491c xReturn = pdFALSE; 80149ea: 2300 movs r3, #0 80149ec: 61fb str r3, [r7, #28] 80149ee: e004 b.n 80149fa } else { *pxTicksToWait = 0; 80149f0: 683b ldr r3, [r7, #0] 80149f2: 2200 movs r2, #0 80149f4: 601a str r2, [r3, #0] xReturn = pdTRUE; 80149f6: 2301 movs r3, #1 80149f8: 61fb str r3, [r7, #28] } } taskEXIT_CRITICAL(); 80149fa: f001 fab7 bl 8015f6c return xReturn; 80149fe: 69fb ldr r3, [r7, #28] } 8014a00: 4618 mov r0, r3 8014a02: 3720 adds r7, #32 8014a04: 46bd mov sp, r7 8014a06: bd80 pop {r7, pc} 8014a08: 24002a7c .word 0x24002a7c 8014a0c: 24002a90 .word 0x24002a90 08014a10 : /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { 8014a10: b480 push {r7} 8014a12: af00 add r7, sp, #0 xYieldPending = pdTRUE; 8014a14: 4b03 ldr r3, [pc, #12] @ (8014a24 ) 8014a16: 2201 movs r2, #1 8014a18: 601a str r2, [r3, #0] } 8014a1a: bf00 nop 8014a1c: 46bd mov sp, r7 8014a1e: f85d 7b04 ldr.w r7, [sp], #4 8014a22: 4770 bx lr 8014a24: 24002a8c .word 0x24002a8c 08014a28 : * * void prvIdleTask( void *pvParameters ); * */ static portTASK_FUNCTION( prvIdleTask, pvParameters ) { 8014a28: b580 push {r7, lr} 8014a2a: b082 sub sp, #8 8014a2c: af00 add r7, sp, #0 8014a2e: 6078 str r0, [r7, #4] for( ;; ) { /* See if any tasks have deleted themselves - if so then the idle task is responsible for freeing the deleted task's TCB and stack. */ prvCheckTasksWaitingTermination(); 8014a30: f000 f852 bl 8014ad8 A critical region is not required here as we are just reading from the list, and an occasional incorrect value will not matter. If the ready list at the idle priority contains more than one task then a task other than the idle task is ready to execute. */ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) 8014a34: 4b06 ldr r3, [pc, #24] @ (8014a50 ) 8014a36: 681b ldr r3, [r3, #0] 8014a38: 2b01 cmp r3, #1 8014a3a: d9f9 bls.n 8014a30 { taskYIELD(); 8014a3c: 4b05 ldr r3, [pc, #20] @ (8014a54 ) 8014a3e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014a42: 601a str r2, [r3, #0] 8014a44: f3bf 8f4f dsb sy 8014a48: f3bf 8f6f isb sy prvCheckTasksWaitingTermination(); 8014a4c: e7f0 b.n 8014a30 8014a4e: bf00 nop 8014a50: 240025a8 .word 0x240025a8 8014a54: e000ed04 .word 0xe000ed04 08014a58 : #endif /* portUSING_MPU_WRAPPERS */ /*-----------------------------------------------------------*/ static void prvInitialiseTaskLists( void ) { 8014a58: b580 push {r7, lr} 8014a5a: b082 sub sp, #8 8014a5c: af00 add r7, sp, #0 UBaseType_t uxPriority; for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 8014a5e: 2300 movs r3, #0 8014a60: 607b str r3, [r7, #4] 8014a62: e00c b.n 8014a7e { vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); 8014a64: 687a ldr r2, [r7, #4] 8014a66: 4613 mov r3, r2 8014a68: 009b lsls r3, r3, #2 8014a6a: 4413 add r3, r2 8014a6c: 009b lsls r3, r3, #2 8014a6e: 4a12 ldr r2, [pc, #72] @ (8014ab8 ) 8014a70: 4413 add r3, r2 8014a72: 4618 mov r0, r3 8014a74: f7fe f81c bl 8012ab0 for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 8014a78: 687b ldr r3, [r7, #4] 8014a7a: 3301 adds r3, #1 8014a7c: 607b str r3, [r7, #4] 8014a7e: 687b ldr r3, [r7, #4] 8014a80: 2b37 cmp r3, #55 @ 0x37 8014a82: d9ef bls.n 8014a64 } vListInitialise( &xDelayedTaskList1 ); 8014a84: 480d ldr r0, [pc, #52] @ (8014abc ) 8014a86: f7fe f813 bl 8012ab0 vListInitialise( &xDelayedTaskList2 ); 8014a8a: 480d ldr r0, [pc, #52] @ (8014ac0 ) 8014a8c: f7fe f810 bl 8012ab0 vListInitialise( &xPendingReadyList ); 8014a90: 480c ldr r0, [pc, #48] @ (8014ac4 ) 8014a92: f7fe f80d bl 8012ab0 #if ( INCLUDE_vTaskDelete == 1 ) { vListInitialise( &xTasksWaitingTermination ); 8014a96: 480c ldr r0, [pc, #48] @ (8014ac8 ) 8014a98: f7fe f80a bl 8012ab0 } #endif /* INCLUDE_vTaskDelete */ #if ( INCLUDE_vTaskSuspend == 1 ) { vListInitialise( &xSuspendedTaskList ); 8014a9c: 480b ldr r0, [pc, #44] @ (8014acc ) 8014a9e: f7fe f807 bl 8012ab0 } #endif /* INCLUDE_vTaskSuspend */ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList using list2. */ pxDelayedTaskList = &xDelayedTaskList1; 8014aa2: 4b0b ldr r3, [pc, #44] @ (8014ad0 ) 8014aa4: 4a05 ldr r2, [pc, #20] @ (8014abc ) 8014aa6: 601a str r2, [r3, #0] pxOverflowDelayedTaskList = &xDelayedTaskList2; 8014aa8: 4b0a ldr r3, [pc, #40] @ (8014ad4 ) 8014aaa: 4a05 ldr r2, [pc, #20] @ (8014ac0 ) 8014aac: 601a str r2, [r3, #0] } 8014aae: bf00 nop 8014ab0: 3708 adds r7, #8 8014ab2: 46bd mov sp, r7 8014ab4: bd80 pop {r7, pc} 8014ab6: bf00 nop 8014ab8: 240025a8 .word 0x240025a8 8014abc: 24002a08 .word 0x24002a08 8014ac0: 24002a1c .word 0x24002a1c 8014ac4: 24002a38 .word 0x24002a38 8014ac8: 24002a4c .word 0x24002a4c 8014acc: 24002a64 .word 0x24002a64 8014ad0: 24002a30 .word 0x24002a30 8014ad4: 24002a34 .word 0x24002a34 08014ad8 : /*-----------------------------------------------------------*/ static void prvCheckTasksWaitingTermination( void ) { 8014ad8: b580 push {r7, lr} 8014ada: b082 sub sp, #8 8014adc: af00 add r7, sp, #0 { TCB_t *pxTCB; /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 8014ade: e019 b.n 8014b14 { taskENTER_CRITICAL(); 8014ae0: f001 fa12 bl 8015f08 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8014ae4: 4b10 ldr r3, [pc, #64] @ (8014b28 ) 8014ae6: 68db ldr r3, [r3, #12] 8014ae8: 68db ldr r3, [r3, #12] 8014aea: 607b str r3, [r7, #4] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8014aec: 687b ldr r3, [r7, #4] 8014aee: 3304 adds r3, #4 8014af0: 4618 mov r0, r3 8014af2: f7fe f867 bl 8012bc4 --uxCurrentNumberOfTasks; 8014af6: 4b0d ldr r3, [pc, #52] @ (8014b2c ) 8014af8: 681b ldr r3, [r3, #0] 8014afa: 3b01 subs r3, #1 8014afc: 4a0b ldr r2, [pc, #44] @ (8014b2c ) 8014afe: 6013 str r3, [r2, #0] --uxDeletedTasksWaitingCleanUp; 8014b00: 4b0b ldr r3, [pc, #44] @ (8014b30 ) 8014b02: 681b ldr r3, [r3, #0] 8014b04: 3b01 subs r3, #1 8014b06: 4a0a ldr r2, [pc, #40] @ (8014b30 ) 8014b08: 6013 str r3, [r2, #0] } taskEXIT_CRITICAL(); 8014b0a: f001 fa2f bl 8015f6c prvDeleteTCB( pxTCB ); 8014b0e: 6878 ldr r0, [r7, #4] 8014b10: f000 f810 bl 8014b34 while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 8014b14: 4b06 ldr r3, [pc, #24] @ (8014b30 ) 8014b16: 681b ldr r3, [r3, #0] 8014b18: 2b00 cmp r3, #0 8014b1a: d1e1 bne.n 8014ae0 } } #endif /* INCLUDE_vTaskDelete */ } 8014b1c: bf00 nop 8014b1e: bf00 nop 8014b20: 3708 adds r7, #8 8014b22: 46bd mov sp, r7 8014b24: bd80 pop {r7, pc} 8014b26: bf00 nop 8014b28: 24002a4c .word 0x24002a4c 8014b2c: 24002a78 .word 0x24002a78 8014b30: 24002a60 .word 0x24002a60 08014b34 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelete == 1 ) static void prvDeleteTCB( TCB_t *pxTCB ) { 8014b34: b580 push {r7, lr} 8014b36: b084 sub sp, #16 8014b38: af00 add r7, sp, #0 8014b3a: 6078 str r0, [r7, #4] to the task to free any memory allocated at the application level. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ #if ( configUSE_NEWLIB_REENTRANT == 1 ) { _reclaim_reent( &( pxTCB->xNewLib_reent ) ); 8014b3c: 687b ldr r3, [r7, #4] 8014b3e: 3354 adds r3, #84 @ 0x54 8014b40: 4618 mov r0, r3 8014b42: f001 fe21 bl 8016788 <_reclaim_reent> #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* The task could have been allocated statically or dynamically, so check what was statically allocated before trying to free the memory. */ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) 8014b46: 687b ldr r3, [r7, #4] 8014b48: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8014b4c: 2b00 cmp r3, #0 8014b4e: d108 bne.n 8014b62 { /* Both the stack and TCB were allocated dynamically, so both must be freed. */ vPortFree( pxTCB->pxStack ); 8014b50: 687b ldr r3, [r7, #4] 8014b52: 6b1b ldr r3, [r3, #48] @ 0x30 8014b54: 4618 mov r0, r3 8014b56: f001 fbc7 bl 80162e8 vPortFree( pxTCB ); 8014b5a: 6878 ldr r0, [r7, #4] 8014b5c: f001 fbc4 bl 80162e8 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); mtCOVERAGE_TEST_MARKER(); } } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } 8014b60: e019 b.n 8014b96 else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) 8014b62: 687b ldr r3, [r7, #4] 8014b64: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8014b68: 2b01 cmp r3, #1 8014b6a: d103 bne.n 8014b74 vPortFree( pxTCB ); 8014b6c: 6878 ldr r0, [r7, #4] 8014b6e: f001 fbbb bl 80162e8 } 8014b72: e010 b.n 8014b96 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); 8014b74: 687b ldr r3, [r7, #4] 8014b76: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8014b7a: 2b02 cmp r3, #2 8014b7c: d00b beq.n 8014b96 __asm volatile 8014b7e: f04f 0350 mov.w r3, #80 @ 0x50 8014b82: f383 8811 msr BASEPRI, r3 8014b86: f3bf 8f6f isb sy 8014b8a: f3bf 8f4f dsb sy 8014b8e: 60fb str r3, [r7, #12] } 8014b90: bf00 nop 8014b92: bf00 nop 8014b94: e7fd b.n 8014b92 } 8014b96: bf00 nop 8014b98: 3710 adds r7, #16 8014b9a: 46bd mov sp, r7 8014b9c: bd80 pop {r7, pc} ... 08014ba0 : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { 8014ba0: b480 push {r7} 8014ba2: b083 sub sp, #12 8014ba4: af00 add r7, sp, #0 TCB_t *pxTCB; if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8014ba6: 4b0c ldr r3, [pc, #48] @ (8014bd8 ) 8014ba8: 681b ldr r3, [r3, #0] 8014baa: 681b ldr r3, [r3, #0] 8014bac: 2b00 cmp r3, #0 8014bae: d104 bne.n 8014bba { /* The new current delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass until there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; 8014bb0: 4b0a ldr r3, [pc, #40] @ (8014bdc ) 8014bb2: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8014bb6: 601a str r2, [r3, #0] which the task at the head of the delayed list should be removed from the Blocked state. */ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); } } 8014bb8: e008 b.n 8014bcc ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8014bba: 4b07 ldr r3, [pc, #28] @ (8014bd8 ) 8014bbc: 681b ldr r3, [r3, #0] 8014bbe: 68db ldr r3, [r3, #12] 8014bc0: 68db ldr r3, [r3, #12] 8014bc2: 607b str r3, [r7, #4] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 8014bc4: 687b ldr r3, [r7, #4] 8014bc6: 685b ldr r3, [r3, #4] 8014bc8: 4a04 ldr r2, [pc, #16] @ (8014bdc ) 8014bca: 6013 str r3, [r2, #0] } 8014bcc: bf00 nop 8014bce: 370c adds r7, #12 8014bd0: 46bd mov sp, r7 8014bd2: f85d 7b04 ldr.w r7, [sp], #4 8014bd6: 4770 bx lr 8014bd8: 24002a30 .word 0x24002a30 8014bdc: 24002a98 .word 0x24002a98 08014be0 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) TaskHandle_t xTaskGetCurrentTaskHandle( void ) { 8014be0: b480 push {r7} 8014be2: b083 sub sp, #12 8014be4: af00 add r7, sp, #0 TaskHandle_t xReturn; /* A critical section is not required as this is not called from an interrupt and the current TCB will always be the same for any individual execution thread. */ xReturn = pxCurrentTCB; 8014be6: 4b05 ldr r3, [pc, #20] @ (8014bfc ) 8014be8: 681b ldr r3, [r3, #0] 8014bea: 607b str r3, [r7, #4] return xReturn; 8014bec: 687b ldr r3, [r7, #4] } 8014bee: 4618 mov r0, r3 8014bf0: 370c adds r7, #12 8014bf2: 46bd mov sp, r7 8014bf4: f85d 7b04 ldr.w r7, [sp], #4 8014bf8: 4770 bx lr 8014bfa: bf00 nop 8014bfc: 240025a4 .word 0x240025a4 08014c00 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) BaseType_t xTaskGetSchedulerState( void ) { 8014c00: b480 push {r7} 8014c02: b083 sub sp, #12 8014c04: af00 add r7, sp, #0 BaseType_t xReturn; if( xSchedulerRunning == pdFALSE ) 8014c06: 4b0b ldr r3, [pc, #44] @ (8014c34 ) 8014c08: 681b ldr r3, [r3, #0] 8014c0a: 2b00 cmp r3, #0 8014c0c: d102 bne.n 8014c14 { xReturn = taskSCHEDULER_NOT_STARTED; 8014c0e: 2301 movs r3, #1 8014c10: 607b str r3, [r7, #4] 8014c12: e008 b.n 8014c26 } else { if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8014c14: 4b08 ldr r3, [pc, #32] @ (8014c38 ) 8014c16: 681b ldr r3, [r3, #0] 8014c18: 2b00 cmp r3, #0 8014c1a: d102 bne.n 8014c22 { xReturn = taskSCHEDULER_RUNNING; 8014c1c: 2302 movs r3, #2 8014c1e: 607b str r3, [r7, #4] 8014c20: e001 b.n 8014c26 } else { xReturn = taskSCHEDULER_SUSPENDED; 8014c22: 2300 movs r3, #0 8014c24: 607b str r3, [r7, #4] } } return xReturn; 8014c26: 687b ldr r3, [r7, #4] } 8014c28: 4618 mov r0, r3 8014c2a: 370c adds r7, #12 8014c2c: 46bd mov sp, r7 8014c2e: f85d 7b04 ldr.w r7, [sp], #4 8014c32: 4770 bx lr 8014c34: 24002a84 .word 0x24002a84 8014c38: 24002aa0 .word 0x24002aa0 08014c3c : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) { 8014c3c: b580 push {r7, lr} 8014c3e: b084 sub sp, #16 8014c40: af00 add r7, sp, #0 8014c42: 6078 str r0, [r7, #4] TCB_t * const pxMutexHolderTCB = pxMutexHolder; 8014c44: 687b ldr r3, [r7, #4] 8014c46: 60bb str r3, [r7, #8] BaseType_t xReturn = pdFALSE; 8014c48: 2300 movs r3, #0 8014c4a: 60fb str r3, [r7, #12] /* If the mutex was given back by an interrupt while the queue was locked then the mutex holder might now be NULL. _RB_ Is this still needed as interrupts can no longer use mutexes? */ if( pxMutexHolder != NULL ) 8014c4c: 687b ldr r3, [r7, #4] 8014c4e: 2b00 cmp r3, #0 8014c50: d051 beq.n 8014cf6 { /* If the holder of the mutex has a priority below the priority of the task attempting to obtain the mutex then it will temporarily inherit the priority of the task attempting to obtain the mutex. */ if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) 8014c52: 68bb ldr r3, [r7, #8] 8014c54: 6ada ldr r2, [r3, #44] @ 0x2c 8014c56: 4b2a ldr r3, [pc, #168] @ (8014d00 ) 8014c58: 681b ldr r3, [r3, #0] 8014c5a: 6adb ldr r3, [r3, #44] @ 0x2c 8014c5c: 429a cmp r2, r3 8014c5e: d241 bcs.n 8014ce4 { /* Adjust the mutex holder state to account for its new priority. Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 8014c60: 68bb ldr r3, [r7, #8] 8014c62: 699b ldr r3, [r3, #24] 8014c64: 2b00 cmp r3, #0 8014c66: db06 blt.n 8014c76 { listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8014c68: 4b25 ldr r3, [pc, #148] @ (8014d00 ) 8014c6a: 681b ldr r3, [r3, #0] 8014c6c: 6adb ldr r3, [r3, #44] @ 0x2c 8014c6e: f1c3 0238 rsb r2, r3, #56 @ 0x38 8014c72: 68bb ldr r3, [r7, #8] 8014c74: 619a str r2, [r3, #24] mtCOVERAGE_TEST_MARKER(); } /* If the task being modified is in the ready state it will need to be moved into a new list. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) 8014c76: 68bb ldr r3, [r7, #8] 8014c78: 6959 ldr r1, [r3, #20] 8014c7a: 68bb ldr r3, [r7, #8] 8014c7c: 6ada ldr r2, [r3, #44] @ 0x2c 8014c7e: 4613 mov r3, r2 8014c80: 009b lsls r3, r3, #2 8014c82: 4413 add r3, r2 8014c84: 009b lsls r3, r3, #2 8014c86: 4a1f ldr r2, [pc, #124] @ (8014d04 ) 8014c88: 4413 add r3, r2 8014c8a: 4299 cmp r1, r3 8014c8c: d122 bne.n 8014cd4 { if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8014c8e: 68bb ldr r3, [r7, #8] 8014c90: 3304 adds r3, #4 8014c92: 4618 mov r0, r3 8014c94: f7fd ff96 bl 8012bc4 { mtCOVERAGE_TEST_MARKER(); } /* Inherit the priority before being moved into the new list. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8014c98: 4b19 ldr r3, [pc, #100] @ (8014d00 ) 8014c9a: 681b ldr r3, [r3, #0] 8014c9c: 6ada ldr r2, [r3, #44] @ 0x2c 8014c9e: 68bb ldr r3, [r7, #8] 8014ca0: 62da str r2, [r3, #44] @ 0x2c prvAddTaskToReadyList( pxMutexHolderTCB ); 8014ca2: 68bb ldr r3, [r7, #8] 8014ca4: 6ada ldr r2, [r3, #44] @ 0x2c 8014ca6: 4b18 ldr r3, [pc, #96] @ (8014d08 ) 8014ca8: 681b ldr r3, [r3, #0] 8014caa: 429a cmp r2, r3 8014cac: d903 bls.n 8014cb6 8014cae: 68bb ldr r3, [r7, #8] 8014cb0: 6adb ldr r3, [r3, #44] @ 0x2c 8014cb2: 4a15 ldr r2, [pc, #84] @ (8014d08 ) 8014cb4: 6013 str r3, [r2, #0] 8014cb6: 68bb ldr r3, [r7, #8] 8014cb8: 6ada ldr r2, [r3, #44] @ 0x2c 8014cba: 4613 mov r3, r2 8014cbc: 009b lsls r3, r3, #2 8014cbe: 4413 add r3, r2 8014cc0: 009b lsls r3, r3, #2 8014cc2: 4a10 ldr r2, [pc, #64] @ (8014d04 ) 8014cc4: 441a add r2, r3 8014cc6: 68bb ldr r3, [r7, #8] 8014cc8: 3304 adds r3, #4 8014cca: 4619 mov r1, r3 8014ccc: 4610 mov r0, r2 8014cce: f7fd ff1c bl 8012b0a 8014cd2: e004 b.n 8014cde } else { /* Just inherit the priority. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8014cd4: 4b0a ldr r3, [pc, #40] @ (8014d00 ) 8014cd6: 681b ldr r3, [r3, #0] 8014cd8: 6ada ldr r2, [r3, #44] @ 0x2c 8014cda: 68bb ldr r3, [r7, #8] 8014cdc: 62da str r2, [r3, #44] @ 0x2c } traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); /* Inheritance occurred. */ xReturn = pdTRUE; 8014cde: 2301 movs r3, #1 8014ce0: 60fb str r3, [r7, #12] 8014ce2: e008 b.n 8014cf6 } else { if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) 8014ce4: 68bb ldr r3, [r7, #8] 8014ce6: 6cda ldr r2, [r3, #76] @ 0x4c 8014ce8: 4b05 ldr r3, [pc, #20] @ (8014d00 ) 8014cea: 681b ldr r3, [r3, #0] 8014cec: 6adb ldr r3, [r3, #44] @ 0x2c 8014cee: 429a cmp r2, r3 8014cf0: d201 bcs.n 8014cf6 current priority of the mutex holder is not lower than the priority of the task attempting to take the mutex. Therefore the mutex holder must have already inherited a priority, but inheritance would have occurred if that had not been the case. */ xReturn = pdTRUE; 8014cf2: 2301 movs r3, #1 8014cf4: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8014cf6: 68fb ldr r3, [r7, #12] } 8014cf8: 4618 mov r0, r3 8014cfa: 3710 adds r7, #16 8014cfc: 46bd mov sp, r7 8014cfe: bd80 pop {r7, pc} 8014d00: 240025a4 .word 0x240025a4 8014d04: 240025a8 .word 0x240025a8 8014d08: 24002a80 .word 0x24002a80 08014d0c : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { 8014d0c: b580 push {r7, lr} 8014d0e: b086 sub sp, #24 8014d10: af00 add r7, sp, #0 8014d12: 6078 str r0, [r7, #4] TCB_t * const pxTCB = pxMutexHolder; 8014d14: 687b ldr r3, [r7, #4] 8014d16: 613b str r3, [r7, #16] BaseType_t xReturn = pdFALSE; 8014d18: 2300 movs r3, #0 8014d1a: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 8014d1c: 687b ldr r3, [r7, #4] 8014d1e: 2b00 cmp r3, #0 8014d20: d058 beq.n 8014dd4 { /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. */ configASSERT( pxTCB == pxCurrentTCB ); 8014d22: 4b2f ldr r3, [pc, #188] @ (8014de0 ) 8014d24: 681b ldr r3, [r3, #0] 8014d26: 693a ldr r2, [r7, #16] 8014d28: 429a cmp r2, r3 8014d2a: d00b beq.n 8014d44 __asm volatile 8014d2c: f04f 0350 mov.w r3, #80 @ 0x50 8014d30: f383 8811 msr BASEPRI, r3 8014d34: f3bf 8f6f isb sy 8014d38: f3bf 8f4f dsb sy 8014d3c: 60fb str r3, [r7, #12] } 8014d3e: bf00 nop 8014d40: bf00 nop 8014d42: e7fd b.n 8014d40 configASSERT( pxTCB->uxMutexesHeld ); 8014d44: 693b ldr r3, [r7, #16] 8014d46: 6d1b ldr r3, [r3, #80] @ 0x50 8014d48: 2b00 cmp r3, #0 8014d4a: d10b bne.n 8014d64 __asm volatile 8014d4c: f04f 0350 mov.w r3, #80 @ 0x50 8014d50: f383 8811 msr BASEPRI, r3 8014d54: f3bf 8f6f isb sy 8014d58: f3bf 8f4f dsb sy 8014d5c: 60bb str r3, [r7, #8] } 8014d5e: bf00 nop 8014d60: bf00 nop 8014d62: e7fd b.n 8014d60 ( pxTCB->uxMutexesHeld )--; 8014d64: 693b ldr r3, [r7, #16] 8014d66: 6d1b ldr r3, [r3, #80] @ 0x50 8014d68: 1e5a subs r2, r3, #1 8014d6a: 693b ldr r3, [r7, #16] 8014d6c: 651a str r2, [r3, #80] @ 0x50 /* Has the holder of the mutex inherited the priority of another task? */ if( pxTCB->uxPriority != pxTCB->uxBasePriority ) 8014d6e: 693b ldr r3, [r7, #16] 8014d70: 6ada ldr r2, [r3, #44] @ 0x2c 8014d72: 693b ldr r3, [r7, #16] 8014d74: 6cdb ldr r3, [r3, #76] @ 0x4c 8014d76: 429a cmp r2, r3 8014d78: d02c beq.n 8014dd4 { /* Only disinherit if no other mutexes are held. */ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) 8014d7a: 693b ldr r3, [r7, #16] 8014d7c: 6d1b ldr r3, [r3, #80] @ 0x50 8014d7e: 2b00 cmp r3, #0 8014d80: d128 bne.n 8014dd4 /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. Remove the holding task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8014d82: 693b ldr r3, [r7, #16] 8014d84: 3304 adds r3, #4 8014d86: 4618 mov r0, r3 8014d88: f7fd ff1c bl 8012bc4 } /* Disinherit the priority before adding the task into the new ready list. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); pxTCB->uxPriority = pxTCB->uxBasePriority; 8014d8c: 693b ldr r3, [r7, #16] 8014d8e: 6cda ldr r2, [r3, #76] @ 0x4c 8014d90: 693b ldr r3, [r7, #16] 8014d92: 62da str r2, [r3, #44] @ 0x2c /* Reset the event list item value. It cannot be in use for any other purpose if this task is running, and it must be running to give back the mutex. */ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8014d94: 693b ldr r3, [r7, #16] 8014d96: 6adb ldr r3, [r3, #44] @ 0x2c 8014d98: f1c3 0238 rsb r2, r3, #56 @ 0x38 8014d9c: 693b ldr r3, [r7, #16] 8014d9e: 619a str r2, [r3, #24] prvAddTaskToReadyList( pxTCB ); 8014da0: 693b ldr r3, [r7, #16] 8014da2: 6ada ldr r2, [r3, #44] @ 0x2c 8014da4: 4b0f ldr r3, [pc, #60] @ (8014de4 ) 8014da6: 681b ldr r3, [r3, #0] 8014da8: 429a cmp r2, r3 8014daa: d903 bls.n 8014db4 8014dac: 693b ldr r3, [r7, #16] 8014dae: 6adb ldr r3, [r3, #44] @ 0x2c 8014db0: 4a0c ldr r2, [pc, #48] @ (8014de4 ) 8014db2: 6013 str r3, [r2, #0] 8014db4: 693b ldr r3, [r7, #16] 8014db6: 6ada ldr r2, [r3, #44] @ 0x2c 8014db8: 4613 mov r3, r2 8014dba: 009b lsls r3, r3, #2 8014dbc: 4413 add r3, r2 8014dbe: 009b lsls r3, r3, #2 8014dc0: 4a09 ldr r2, [pc, #36] @ (8014de8 ) 8014dc2: 441a add r2, r3 8014dc4: 693b ldr r3, [r7, #16] 8014dc6: 3304 adds r3, #4 8014dc8: 4619 mov r1, r3 8014dca: 4610 mov r0, r2 8014dcc: f7fd fe9d bl 8012b0a in an order different to that in which they were taken. If a context switch did not occur when the first mutex was returned, even if a task was waiting on it, then a context switch should occur when the last mutex is returned whether a task is waiting on it or not. */ xReturn = pdTRUE; 8014dd0: 2301 movs r3, #1 8014dd2: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8014dd4: 697b ldr r3, [r7, #20] } 8014dd6: 4618 mov r0, r3 8014dd8: 3718 adds r7, #24 8014dda: 46bd mov sp, r7 8014ddc: bd80 pop {r7, pc} 8014dde: bf00 nop 8014de0: 240025a4 .word 0x240025a4 8014de4: 24002a80 .word 0x24002a80 8014de8: 240025a8 .word 0x240025a8 08014dec : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) { 8014dec: b580 push {r7, lr} 8014dee: b088 sub sp, #32 8014df0: af00 add r7, sp, #0 8014df2: 6078 str r0, [r7, #4] 8014df4: 6039 str r1, [r7, #0] TCB_t * const pxTCB = pxMutexHolder; 8014df6: 687b ldr r3, [r7, #4] 8014df8: 61bb str r3, [r7, #24] UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; 8014dfa: 2301 movs r3, #1 8014dfc: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 8014dfe: 687b ldr r3, [r7, #4] 8014e00: 2b00 cmp r3, #0 8014e02: d06c beq.n 8014ede { /* If pxMutexHolder is not NULL then the holder must hold at least one mutex. */ configASSERT( pxTCB->uxMutexesHeld ); 8014e04: 69bb ldr r3, [r7, #24] 8014e06: 6d1b ldr r3, [r3, #80] @ 0x50 8014e08: 2b00 cmp r3, #0 8014e0a: d10b bne.n 8014e24 __asm volatile 8014e0c: f04f 0350 mov.w r3, #80 @ 0x50 8014e10: f383 8811 msr BASEPRI, r3 8014e14: f3bf 8f6f isb sy 8014e18: f3bf 8f4f dsb sy 8014e1c: 60fb str r3, [r7, #12] } 8014e1e: bf00 nop 8014e20: bf00 nop 8014e22: e7fd b.n 8014e20 /* Determine the priority to which the priority of the task that holds the mutex should be set. This will be the greater of the holding task's base priority and the priority of the highest priority task that is waiting to obtain the mutex. */ if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) 8014e24: 69bb ldr r3, [r7, #24] 8014e26: 6cdb ldr r3, [r3, #76] @ 0x4c 8014e28: 683a ldr r2, [r7, #0] 8014e2a: 429a cmp r2, r3 8014e2c: d902 bls.n 8014e34 { uxPriorityToUse = uxHighestPriorityWaitingTask; 8014e2e: 683b ldr r3, [r7, #0] 8014e30: 61fb str r3, [r7, #28] 8014e32: e002 b.n 8014e3a } else { uxPriorityToUse = pxTCB->uxBasePriority; 8014e34: 69bb ldr r3, [r7, #24] 8014e36: 6cdb ldr r3, [r3, #76] @ 0x4c 8014e38: 61fb str r3, [r7, #28] } /* Does the priority need to change? */ if( pxTCB->uxPriority != uxPriorityToUse ) 8014e3a: 69bb ldr r3, [r7, #24] 8014e3c: 6adb ldr r3, [r3, #44] @ 0x2c 8014e3e: 69fa ldr r2, [r7, #28] 8014e40: 429a cmp r2, r3 8014e42: d04c beq.n 8014ede { /* Only disinherit if no other mutexes are held. This is a simplification in the priority inheritance implementation. If the task that holds the mutex is also holding other mutexes then the other mutexes may have caused the priority inheritance. */ if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) 8014e44: 69bb ldr r3, [r7, #24] 8014e46: 6d1b ldr r3, [r3, #80] @ 0x50 8014e48: 697a ldr r2, [r7, #20] 8014e4a: 429a cmp r2, r3 8014e4c: d147 bne.n 8014ede { /* If a task has timed out because it already holds the mutex it was trying to obtain then it cannot of inherited its own priority. */ configASSERT( pxTCB != pxCurrentTCB ); 8014e4e: 4b26 ldr r3, [pc, #152] @ (8014ee8 ) 8014e50: 681b ldr r3, [r3, #0] 8014e52: 69ba ldr r2, [r7, #24] 8014e54: 429a cmp r2, r3 8014e56: d10b bne.n 8014e70 __asm volatile 8014e58: f04f 0350 mov.w r3, #80 @ 0x50 8014e5c: f383 8811 msr BASEPRI, r3 8014e60: f3bf 8f6f isb sy 8014e64: f3bf 8f4f dsb sy 8014e68: 60bb str r3, [r7, #8] } 8014e6a: bf00 nop 8014e6c: bf00 nop 8014e6e: e7fd b.n 8014e6c /* Disinherit the priority, remembering the previous priority to facilitate determining the subject task's state. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); uxPriorityUsedOnEntry = pxTCB->uxPriority; 8014e70: 69bb ldr r3, [r7, #24] 8014e72: 6adb ldr r3, [r3, #44] @ 0x2c 8014e74: 613b str r3, [r7, #16] pxTCB->uxPriority = uxPriorityToUse; 8014e76: 69bb ldr r3, [r7, #24] 8014e78: 69fa ldr r2, [r7, #28] 8014e7a: 62da str r2, [r3, #44] @ 0x2c /* Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 8014e7c: 69bb ldr r3, [r7, #24] 8014e7e: 699b ldr r3, [r3, #24] 8014e80: 2b00 cmp r3, #0 8014e82: db04 blt.n 8014e8e { listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8014e84: 69fb ldr r3, [r7, #28] 8014e86: f1c3 0238 rsb r2, r3, #56 @ 0x38 8014e8a: 69bb ldr r3, [r7, #24] 8014e8c: 619a str r2, [r3, #24] then the task that holds the mutex could be in either the Ready, Blocked or Suspended states. Only remove the task from its current state list if it is in the Ready state as the task's priority is going to change and there is one Ready list per priority. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) 8014e8e: 69bb ldr r3, [r7, #24] 8014e90: 6959 ldr r1, [r3, #20] 8014e92: 693a ldr r2, [r7, #16] 8014e94: 4613 mov r3, r2 8014e96: 009b lsls r3, r3, #2 8014e98: 4413 add r3, r2 8014e9a: 009b lsls r3, r3, #2 8014e9c: 4a13 ldr r2, [pc, #76] @ (8014eec ) 8014e9e: 4413 add r3, r2 8014ea0: 4299 cmp r1, r3 8014ea2: d11c bne.n 8014ede { if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8014ea4: 69bb ldr r3, [r7, #24] 8014ea6: 3304 adds r3, #4 8014ea8: 4618 mov r0, r3 8014eaa: f7fd fe8b bl 8012bc4 else { mtCOVERAGE_TEST_MARKER(); } prvAddTaskToReadyList( pxTCB ); 8014eae: 69bb ldr r3, [r7, #24] 8014eb0: 6ada ldr r2, [r3, #44] @ 0x2c 8014eb2: 4b0f ldr r3, [pc, #60] @ (8014ef0 ) 8014eb4: 681b ldr r3, [r3, #0] 8014eb6: 429a cmp r2, r3 8014eb8: d903 bls.n 8014ec2 8014eba: 69bb ldr r3, [r7, #24] 8014ebc: 6adb ldr r3, [r3, #44] @ 0x2c 8014ebe: 4a0c ldr r2, [pc, #48] @ (8014ef0 ) 8014ec0: 6013 str r3, [r2, #0] 8014ec2: 69bb ldr r3, [r7, #24] 8014ec4: 6ada ldr r2, [r3, #44] @ 0x2c 8014ec6: 4613 mov r3, r2 8014ec8: 009b lsls r3, r3, #2 8014eca: 4413 add r3, r2 8014ecc: 009b lsls r3, r3, #2 8014ece: 4a07 ldr r2, [pc, #28] @ (8014eec ) 8014ed0: 441a add r2, r3 8014ed2: 69bb ldr r3, [r7, #24] 8014ed4: 3304 adds r3, #4 8014ed6: 4619 mov r1, r3 8014ed8: 4610 mov r0, r2 8014eda: f7fd fe16 bl 8012b0a } else { mtCOVERAGE_TEST_MARKER(); } } 8014ede: bf00 nop 8014ee0: 3720 adds r7, #32 8014ee2: 46bd mov sp, r7 8014ee4: bd80 pop {r7, pc} 8014ee6: bf00 nop 8014ee8: 240025a4 .word 0x240025a4 8014eec: 240025a8 .word 0x240025a8 8014ef0: 24002a80 .word 0x24002a80 08014ef4 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) TaskHandle_t pvTaskIncrementMutexHeldCount( void ) { 8014ef4: b480 push {r7} 8014ef6: af00 add r7, sp, #0 /* If xSemaphoreCreateMutex() is called before any tasks have been created then pxCurrentTCB will be NULL. */ if( pxCurrentTCB != NULL ) 8014ef8: 4b07 ldr r3, [pc, #28] @ (8014f18 ) 8014efa: 681b ldr r3, [r3, #0] 8014efc: 2b00 cmp r3, #0 8014efe: d004 beq.n 8014f0a { ( pxCurrentTCB->uxMutexesHeld )++; 8014f00: 4b05 ldr r3, [pc, #20] @ (8014f18 ) 8014f02: 681b ldr r3, [r3, #0] 8014f04: 6d1a ldr r2, [r3, #80] @ 0x50 8014f06: 3201 adds r2, #1 8014f08: 651a str r2, [r3, #80] @ 0x50 } return pxCurrentTCB; 8014f0a: 4b03 ldr r3, [pc, #12] @ (8014f18 ) 8014f0c: 681b ldr r3, [r3, #0] } 8014f0e: 4618 mov r0, r3 8014f10: 46bd mov sp, r7 8014f12: f85d 7b04 ldr.w r7, [sp], #4 8014f16: 4770 bx lr 8014f18: 240025a4 .word 0x240025a4 08014f1c : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) { 8014f1c: b580 push {r7, lr} 8014f1e: b086 sub sp, #24 8014f20: af00 add r7, sp, #0 8014f22: 60f8 str r0, [r7, #12] 8014f24: 60b9 str r1, [r7, #8] 8014f26: 607a str r2, [r7, #4] 8014f28: 603b str r3, [r7, #0] BaseType_t xReturn; taskENTER_CRITICAL(); 8014f2a: f000 ffed bl 8015f08 { /* Only block if a notification is not already pending. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 8014f2e: 4b29 ldr r3, [pc, #164] @ (8014fd4 ) 8014f30: 681b ldr r3, [r3, #0] 8014f32: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8014f36: b2db uxtb r3, r3 8014f38: 2b02 cmp r3, #2 8014f3a: d01c beq.n 8014f76 { /* Clear bits in the task's notification value as bits may get set by the notifying task or interrupt. This can be used to clear the value to zero. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry; 8014f3c: 4b25 ldr r3, [pc, #148] @ (8014fd4 ) 8014f3e: 681b ldr r3, [r3, #0] 8014f40: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 8014f44: 68fa ldr r2, [r7, #12] 8014f46: 43d2 mvns r2, r2 8014f48: 400a ands r2, r1 8014f4a: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 /* Mark this task as waiting for a notification. */ pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION; 8014f4e: 4b21 ldr r3, [pc, #132] @ (8014fd4 ) 8014f50: 681b ldr r3, [r3, #0] 8014f52: 2201 movs r2, #1 8014f54: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 if( xTicksToWait > ( TickType_t ) 0 ) 8014f58: 683b ldr r3, [r7, #0] 8014f5a: 2b00 cmp r3, #0 8014f5c: d00b beq.n 8014f76 { prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 8014f5e: 2101 movs r1, #1 8014f60: 6838 ldr r0, [r7, #0] 8014f62: f000 fa09 bl 8015378 /* All ports are written to allow a yield in a critical section (some will yield immediately, others wait until the critical section exits) - but it is not something that application code should ever do. */ portYIELD_WITHIN_API(); 8014f66: 4b1c ldr r3, [pc, #112] @ (8014fd8 ) 8014f68: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014f6c: 601a str r2, [r3, #0] 8014f6e: f3bf 8f4f dsb sy 8014f72: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8014f76: f000 fff9 bl 8015f6c taskENTER_CRITICAL(); 8014f7a: f000 ffc5 bl 8015f08 { traceTASK_NOTIFY_WAIT(); if( pulNotificationValue != NULL ) 8014f7e: 687b ldr r3, [r7, #4] 8014f80: 2b00 cmp r3, #0 8014f82: d005 beq.n 8014f90 { /* Output the current notification value, which may or may not have changed. */ *pulNotificationValue = pxCurrentTCB->ulNotifiedValue; 8014f84: 4b13 ldr r3, [pc, #76] @ (8014fd4 ) 8014f86: 681b ldr r3, [r3, #0] 8014f88: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8014f8c: 687b ldr r3, [r7, #4] 8014f8e: 601a str r2, [r3, #0] /* If ucNotifyValue is set then either the task never entered the blocked state (because a notification was already pending) or the task unblocked because of a notification. Otherwise the task unblocked because of a timeout. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 8014f90: 4b10 ldr r3, [pc, #64] @ (8014fd4 ) 8014f92: 681b ldr r3, [r3, #0] 8014f94: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8014f98: b2db uxtb r3, r3 8014f9a: 2b02 cmp r3, #2 8014f9c: d002 beq.n 8014fa4 { /* A notification was not received. */ xReturn = pdFALSE; 8014f9e: 2300 movs r3, #0 8014fa0: 617b str r3, [r7, #20] 8014fa2: e00a b.n 8014fba } else { /* A notification was already pending or a notification was received while the task was waiting. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit; 8014fa4: 4b0b ldr r3, [pc, #44] @ (8014fd4 ) 8014fa6: 681b ldr r3, [r3, #0] 8014fa8: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 8014fac: 68ba ldr r2, [r7, #8] 8014fae: 43d2 mvns r2, r2 8014fb0: 400a ands r2, r1 8014fb2: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 xReturn = pdTRUE; 8014fb6: 2301 movs r3, #1 8014fb8: 617b str r3, [r7, #20] } pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8014fba: 4b06 ldr r3, [pc, #24] @ (8014fd4 ) 8014fbc: 681b ldr r3, [r3, #0] 8014fbe: 2200 movs r2, #0 8014fc0: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 } taskEXIT_CRITICAL(); 8014fc4: f000 ffd2 bl 8015f6c return xReturn; 8014fc8: 697b ldr r3, [r7, #20] } 8014fca: 4618 mov r0, r3 8014fcc: 3718 adds r7, #24 8014fce: 46bd mov sp, r7 8014fd0: bd80 pop {r7, pc} 8014fd2: bf00 nop 8014fd4: 240025a4 .word 0x240025a4 8014fd8: e000ed04 .word 0xe000ed04 08014fdc : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) { 8014fdc: b580 push {r7, lr} 8014fde: b08a sub sp, #40 @ 0x28 8014fe0: af00 add r7, sp, #0 8014fe2: 60f8 str r0, [r7, #12] 8014fe4: 60b9 str r1, [r7, #8] 8014fe6: 603b str r3, [r7, #0] 8014fe8: 4613 mov r3, r2 8014fea: 71fb strb r3, [r7, #7] TCB_t * pxTCB; BaseType_t xReturn = pdPASS; 8014fec: 2301 movs r3, #1 8014fee: 627b str r3, [r7, #36] @ 0x24 uint8_t ucOriginalNotifyState; configASSERT( xTaskToNotify ); 8014ff0: 68fb ldr r3, [r7, #12] 8014ff2: 2b00 cmp r3, #0 8014ff4: d10b bne.n 801500e __asm volatile 8014ff6: f04f 0350 mov.w r3, #80 @ 0x50 8014ffa: f383 8811 msr BASEPRI, r3 8014ffe: f3bf 8f6f isb sy 8015002: f3bf 8f4f dsb sy 8015006: 61bb str r3, [r7, #24] } 8015008: bf00 nop 801500a: bf00 nop 801500c: e7fd b.n 801500a pxTCB = xTaskToNotify; 801500e: 68fb ldr r3, [r7, #12] 8015010: 623b str r3, [r7, #32] taskENTER_CRITICAL(); 8015012: f000 ff79 bl 8015f08 { if( pulPreviousNotificationValue != NULL ) 8015016: 683b ldr r3, [r7, #0] 8015018: 2b00 cmp r3, #0 801501a: d004 beq.n 8015026 { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 801501c: 6a3b ldr r3, [r7, #32] 801501e: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8015022: 683b ldr r3, [r7, #0] 8015024: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 8015026: 6a3b ldr r3, [r7, #32] 8015028: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 801502c: 77fb strb r3, [r7, #31] pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 801502e: 6a3b ldr r3, [r7, #32] 8015030: 2202 movs r2, #2 8015032: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 8015036: 79fb ldrb r3, [r7, #7] 8015038: 2b04 cmp r3, #4 801503a: d82e bhi.n 801509a 801503c: a201 add r2, pc, #4 @ (adr r2, 8015044 ) 801503e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8015042: bf00 nop 8015044: 080150bf .word 0x080150bf 8015048: 08015059 .word 0x08015059 801504c: 0801506b .word 0x0801506b 8015050: 0801507b .word 0x0801507b 8015054: 08015085 .word 0x08015085 { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 8015058: 6a3b ldr r3, [r7, #32] 801505a: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 801505e: 68bb ldr r3, [r7, #8] 8015060: 431a orrs r2, r3 8015062: 6a3b ldr r3, [r7, #32] 8015064: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8015068: e02c b.n 80150c4 case eIncrement : ( pxTCB->ulNotifiedValue )++; 801506a: 6a3b ldr r3, [r7, #32] 801506c: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8015070: 1c5a adds r2, r3, #1 8015072: 6a3b ldr r3, [r7, #32] 8015074: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8015078: e024 b.n 80150c4 case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 801507a: 6a3b ldr r3, [r7, #32] 801507c: 68ba ldr r2, [r7, #8] 801507e: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8015082: e01f b.n 80150c4 case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 8015084: 7ffb ldrb r3, [r7, #31] 8015086: 2b02 cmp r3, #2 8015088: d004 beq.n 8015094 { pxTCB->ulNotifiedValue = ulValue; 801508a: 6a3b ldr r3, [r7, #32] 801508c: 68ba ldr r2, [r7, #8] 801508e: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 8015092: e017 b.n 80150c4 xReturn = pdFAIL; 8015094: 2300 movs r3, #0 8015096: 627b str r3, [r7, #36] @ 0x24 break; 8015098: e014 b.n 80150c4 default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 801509a: 6a3b ldr r3, [r7, #32] 801509c: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 80150a0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80150a4: d00d beq.n 80150c2 __asm volatile 80150a6: f04f 0350 mov.w r3, #80 @ 0x50 80150aa: f383 8811 msr BASEPRI, r3 80150ae: f3bf 8f6f isb sy 80150b2: f3bf 8f4f dsb sy 80150b6: 617b str r3, [r7, #20] } 80150b8: bf00 nop 80150ba: bf00 nop 80150bc: e7fd b.n 80150ba break; 80150be: bf00 nop 80150c0: e000 b.n 80150c4 break; 80150c2: bf00 nop traceTASK_NOTIFY(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 80150c4: 7ffb ldrb r3, [r7, #31] 80150c6: 2b01 cmp r3, #1 80150c8: d13b bne.n 8015142 { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80150ca: 6a3b ldr r3, [r7, #32] 80150cc: 3304 adds r3, #4 80150ce: 4618 mov r0, r3 80150d0: f7fd fd78 bl 8012bc4 prvAddTaskToReadyList( pxTCB ); 80150d4: 6a3b ldr r3, [r7, #32] 80150d6: 6ada ldr r2, [r3, #44] @ 0x2c 80150d8: 4b1d ldr r3, [pc, #116] @ (8015150 ) 80150da: 681b ldr r3, [r3, #0] 80150dc: 429a cmp r2, r3 80150de: d903 bls.n 80150e8 80150e0: 6a3b ldr r3, [r7, #32] 80150e2: 6adb ldr r3, [r3, #44] @ 0x2c 80150e4: 4a1a ldr r2, [pc, #104] @ (8015150 ) 80150e6: 6013 str r3, [r2, #0] 80150e8: 6a3b ldr r3, [r7, #32] 80150ea: 6ada ldr r2, [r3, #44] @ 0x2c 80150ec: 4613 mov r3, r2 80150ee: 009b lsls r3, r3, #2 80150f0: 4413 add r3, r2 80150f2: 009b lsls r3, r3, #2 80150f4: 4a17 ldr r2, [pc, #92] @ (8015154 ) 80150f6: 441a add r2, r3 80150f8: 6a3b ldr r3, [r7, #32] 80150fa: 3304 adds r3, #4 80150fc: 4619 mov r1, r3 80150fe: 4610 mov r0, r2 8015100: f7fd fd03 bl 8012b0a /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 8015104: 6a3b ldr r3, [r7, #32] 8015106: 6a9b ldr r3, [r3, #40] @ 0x28 8015108: 2b00 cmp r3, #0 801510a: d00b beq.n 8015124 __asm volatile 801510c: f04f 0350 mov.w r3, #80 @ 0x50 8015110: f383 8811 msr BASEPRI, r3 8015114: f3bf 8f6f isb sy 8015118: f3bf 8f4f dsb sy 801511c: 613b str r3, [r7, #16] } 801511e: bf00 nop 8015120: bf00 nop 8015122: e7fd b.n 8015120 earliest possible time. */ prvResetNextTaskUnblockTime(); } #endif if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 8015124: 6a3b ldr r3, [r7, #32] 8015126: 6ada ldr r2, [r3, #44] @ 0x2c 8015128: 4b0b ldr r3, [pc, #44] @ (8015158 ) 801512a: 681b ldr r3, [r3, #0] 801512c: 6adb ldr r3, [r3, #44] @ 0x2c 801512e: 429a cmp r2, r3 8015130: d907 bls.n 8015142 { /* The notified task has a priority above the currently executing task so a yield is required. */ taskYIELD_IF_USING_PREEMPTION(); 8015132: 4b0a ldr r3, [pc, #40] @ (801515c ) 8015134: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015138: 601a str r2, [r3, #0] 801513a: f3bf 8f4f dsb sy 801513e: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8015142: f000 ff13 bl 8015f6c return xReturn; 8015146: 6a7b ldr r3, [r7, #36] @ 0x24 } 8015148: 4618 mov r0, r3 801514a: 3728 adds r7, #40 @ 0x28 801514c: 46bd mov sp, r7 801514e: bd80 pop {r7, pc} 8015150: 24002a80 .word 0x24002a80 8015154: 240025a8 .word 0x240025a8 8015158: 240025a4 .word 0x240025a4 801515c: e000ed04 .word 0xe000ed04 08015160 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) { 8015160: b580 push {r7, lr} 8015162: b08e sub sp, #56 @ 0x38 8015164: af00 add r7, sp, #0 8015166: 60f8 str r0, [r7, #12] 8015168: 60b9 str r1, [r7, #8] 801516a: 603b str r3, [r7, #0] 801516c: 4613 mov r3, r2 801516e: 71fb strb r3, [r7, #7] TCB_t * pxTCB; uint8_t ucOriginalNotifyState; BaseType_t xReturn = pdPASS; 8015170: 2301 movs r3, #1 8015172: 637b str r3, [r7, #52] @ 0x34 UBaseType_t uxSavedInterruptStatus; configASSERT( xTaskToNotify ); 8015174: 68fb ldr r3, [r7, #12] 8015176: 2b00 cmp r3, #0 8015178: d10b bne.n 8015192 __asm volatile 801517a: f04f 0350 mov.w r3, #80 @ 0x50 801517e: f383 8811 msr BASEPRI, r3 8015182: f3bf 8f6f isb sy 8015186: f3bf 8f4f dsb sy 801518a: 627b str r3, [r7, #36] @ 0x24 } 801518c: bf00 nop 801518e: bf00 nop 8015190: e7fd b.n 801518e below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8015192: f000 ff99 bl 80160c8 pxTCB = xTaskToNotify; 8015196: 68fb ldr r3, [r7, #12] 8015198: 633b str r3, [r7, #48] @ 0x30 __asm volatile 801519a: f3ef 8211 mrs r2, BASEPRI 801519e: f04f 0350 mov.w r3, #80 @ 0x50 80151a2: f383 8811 msr BASEPRI, r3 80151a6: f3bf 8f6f isb sy 80151aa: f3bf 8f4f dsb sy 80151ae: 623a str r2, [r7, #32] 80151b0: 61fb str r3, [r7, #28] return ulOriginalBASEPRI; 80151b2: 6a3b ldr r3, [r7, #32] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 80151b4: 62fb str r3, [r7, #44] @ 0x2c { if( pulPreviousNotificationValue != NULL ) 80151b6: 683b ldr r3, [r7, #0] 80151b8: 2b00 cmp r3, #0 80151ba: d004 beq.n 80151c6 { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 80151bc: 6b3b ldr r3, [r7, #48] @ 0x30 80151be: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 80151c2: 683b ldr r3, [r7, #0] 80151c4: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 80151c6: 6b3b ldr r3, [r7, #48] @ 0x30 80151c8: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 80151cc: f887 302b strb.w r3, [r7, #43] @ 0x2b pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 80151d0: 6b3b ldr r3, [r7, #48] @ 0x30 80151d2: 2202 movs r2, #2 80151d4: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 80151d8: 79fb ldrb r3, [r7, #7] 80151da: 2b04 cmp r3, #4 80151dc: d82e bhi.n 801523c 80151de: a201 add r2, pc, #4 @ (adr r2, 80151e4 ) 80151e0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80151e4: 08015261 .word 0x08015261 80151e8: 080151f9 .word 0x080151f9 80151ec: 0801520b .word 0x0801520b 80151f0: 0801521b .word 0x0801521b 80151f4: 08015225 .word 0x08015225 { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 80151f8: 6b3b ldr r3, [r7, #48] @ 0x30 80151fa: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 80151fe: 68bb ldr r3, [r7, #8] 8015200: 431a orrs r2, r3 8015202: 6b3b ldr r3, [r7, #48] @ 0x30 8015204: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8015208: e02d b.n 8015266 case eIncrement : ( pxTCB->ulNotifiedValue )++; 801520a: 6b3b ldr r3, [r7, #48] @ 0x30 801520c: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8015210: 1c5a adds r2, r3, #1 8015212: 6b3b ldr r3, [r7, #48] @ 0x30 8015214: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8015218: e025 b.n 8015266 case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 801521a: 6b3b ldr r3, [r7, #48] @ 0x30 801521c: 68ba ldr r2, [r7, #8] 801521e: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8015222: e020 b.n 8015266 case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 8015224: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8015228: 2b02 cmp r3, #2 801522a: d004 beq.n 8015236 { pxTCB->ulNotifiedValue = ulValue; 801522c: 6b3b ldr r3, [r7, #48] @ 0x30 801522e: 68ba ldr r2, [r7, #8] 8015230: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 8015234: e017 b.n 8015266 xReturn = pdFAIL; 8015236: 2300 movs r3, #0 8015238: 637b str r3, [r7, #52] @ 0x34 break; 801523a: e014 b.n 8015266 default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 801523c: 6b3b ldr r3, [r7, #48] @ 0x30 801523e: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8015242: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015246: d00d beq.n 8015264 __asm volatile 8015248: f04f 0350 mov.w r3, #80 @ 0x50 801524c: f383 8811 msr BASEPRI, r3 8015250: f3bf 8f6f isb sy 8015254: f3bf 8f4f dsb sy 8015258: 61bb str r3, [r7, #24] } 801525a: bf00 nop 801525c: bf00 nop 801525e: e7fd b.n 801525c break; 8015260: bf00 nop 8015262: e000 b.n 8015266 break; 8015264: bf00 nop traceTASK_NOTIFY_FROM_ISR(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 8015266: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 801526a: 2b01 cmp r3, #1 801526c: d147 bne.n 80152fe { /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 801526e: 6b3b ldr r3, [r7, #48] @ 0x30 8015270: 6a9b ldr r3, [r3, #40] @ 0x28 8015272: 2b00 cmp r3, #0 8015274: d00b beq.n 801528e __asm volatile 8015276: f04f 0350 mov.w r3, #80 @ 0x50 801527a: f383 8811 msr BASEPRI, r3 801527e: f3bf 8f6f isb sy 8015282: f3bf 8f4f dsb sy 8015286: 617b str r3, [r7, #20] } 8015288: bf00 nop 801528a: bf00 nop 801528c: e7fd b.n 801528a if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 801528e: 4b21 ldr r3, [pc, #132] @ (8015314 ) 8015290: 681b ldr r3, [r3, #0] 8015292: 2b00 cmp r3, #0 8015294: d11d bne.n 80152d2 { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8015296: 6b3b ldr r3, [r7, #48] @ 0x30 8015298: 3304 adds r3, #4 801529a: 4618 mov r0, r3 801529c: f7fd fc92 bl 8012bc4 prvAddTaskToReadyList( pxTCB ); 80152a0: 6b3b ldr r3, [r7, #48] @ 0x30 80152a2: 6ada ldr r2, [r3, #44] @ 0x2c 80152a4: 4b1c ldr r3, [pc, #112] @ (8015318 ) 80152a6: 681b ldr r3, [r3, #0] 80152a8: 429a cmp r2, r3 80152aa: d903 bls.n 80152b4 80152ac: 6b3b ldr r3, [r7, #48] @ 0x30 80152ae: 6adb ldr r3, [r3, #44] @ 0x2c 80152b0: 4a19 ldr r2, [pc, #100] @ (8015318 ) 80152b2: 6013 str r3, [r2, #0] 80152b4: 6b3b ldr r3, [r7, #48] @ 0x30 80152b6: 6ada ldr r2, [r3, #44] @ 0x2c 80152b8: 4613 mov r3, r2 80152ba: 009b lsls r3, r3, #2 80152bc: 4413 add r3, r2 80152be: 009b lsls r3, r3, #2 80152c0: 4a16 ldr r2, [pc, #88] @ (801531c ) 80152c2: 441a add r2, r3 80152c4: 6b3b ldr r3, [r7, #48] @ 0x30 80152c6: 3304 adds r3, #4 80152c8: 4619 mov r1, r3 80152ca: 4610 mov r0, r2 80152cc: f7fd fc1d bl 8012b0a 80152d0: e005 b.n 80152de } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); 80152d2: 6b3b ldr r3, [r7, #48] @ 0x30 80152d4: 3318 adds r3, #24 80152d6: 4619 mov r1, r3 80152d8: 4811 ldr r0, [pc, #68] @ (8015320 ) 80152da: f7fd fc16 bl 8012b0a } if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 80152de: 6b3b ldr r3, [r7, #48] @ 0x30 80152e0: 6ada ldr r2, [r3, #44] @ 0x2c 80152e2: 4b10 ldr r3, [pc, #64] @ (8015324 ) 80152e4: 681b ldr r3, [r3, #0] 80152e6: 6adb ldr r3, [r3, #44] @ 0x2c 80152e8: 429a cmp r2, r3 80152ea: d908 bls.n 80152fe { /* The notified task has a priority above the currently executing task so a yield is required. */ if( pxHigherPriorityTaskWoken != NULL ) 80152ec: 6c3b ldr r3, [r7, #64] @ 0x40 80152ee: 2b00 cmp r3, #0 80152f0: d002 beq.n 80152f8 { *pxHigherPriorityTaskWoken = pdTRUE; 80152f2: 6c3b ldr r3, [r7, #64] @ 0x40 80152f4: 2201 movs r2, #1 80152f6: 601a str r2, [r3, #0] } /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 80152f8: 4b0b ldr r3, [pc, #44] @ (8015328 ) 80152fa: 2201 movs r2, #1 80152fc: 601a str r2, [r3, #0] 80152fe: 6afb ldr r3, [r7, #44] @ 0x2c 8015300: 613b str r3, [r7, #16] __asm volatile 8015302: 693b ldr r3, [r7, #16] 8015304: f383 8811 msr BASEPRI, r3 } 8015308: bf00 nop } } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 801530a: 6b7b ldr r3, [r7, #52] @ 0x34 } 801530c: 4618 mov r0, r3 801530e: 3738 adds r7, #56 @ 0x38 8015310: 46bd mov sp, r7 8015312: bd80 pop {r7, pc} 8015314: 24002aa0 .word 0x24002aa0 8015318: 24002a80 .word 0x24002a80 801531c: 240025a8 .word 0x240025a8 8015320: 24002a38 .word 0x24002a38 8015324: 240025a4 .word 0x240025a4 8015328: 24002a8c .word 0x24002a8c 0801532c : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask ) { 801532c: b580 push {r7, lr} 801532e: b084 sub sp, #16 8015330: af00 add r7, sp, #0 8015332: 6078 str r0, [r7, #4] TCB_t *pxTCB; BaseType_t xReturn; /* If null is passed in here then it is the calling task that is having its notification state cleared. */ pxTCB = prvGetTCBFromHandle( xTask ); 8015334: 687b ldr r3, [r7, #4] 8015336: 2b00 cmp r3, #0 8015338: d102 bne.n 8015340 801533a: 4b0e ldr r3, [pc, #56] @ (8015374 ) 801533c: 681b ldr r3, [r3, #0] 801533e: e000 b.n 8015342 8015340: 687b ldr r3, [r7, #4] 8015342: 60bb str r3, [r7, #8] taskENTER_CRITICAL(); 8015344: f000 fde0 bl 8015f08 { if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED ) 8015348: 68bb ldr r3, [r7, #8] 801534a: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 801534e: b2db uxtb r3, r3 8015350: 2b02 cmp r3, #2 8015352: d106 bne.n 8015362 { pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8015354: 68bb ldr r3, [r7, #8] 8015356: 2200 movs r2, #0 8015358: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 xReturn = pdPASS; 801535c: 2301 movs r3, #1 801535e: 60fb str r3, [r7, #12] 8015360: e001 b.n 8015366 } else { xReturn = pdFAIL; 8015362: 2300 movs r3, #0 8015364: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8015366: f000 fe01 bl 8015f6c return xReturn; 801536a: 68fb ldr r3, [r7, #12] } 801536c: 4618 mov r0, r3 801536e: 3710 adds r7, #16 8015370: 46bd mov sp, r7 8015372: bd80 pop {r7, pc} 8015374: 240025a4 .word 0x240025a4 08015378 : #endif /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { 8015378: b580 push {r7, lr} 801537a: b084 sub sp, #16 801537c: af00 add r7, sp, #0 801537e: 6078 str r0, [r7, #4] 8015380: 6039 str r1, [r7, #0] TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; 8015382: 4b21 ldr r3, [pc, #132] @ (8015408 ) 8015384: 681b ldr r3, [r3, #0] 8015386: 60fb str r3, [r7, #12] } #endif /* Remove the task from the ready list before adding it to the blocked list as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8015388: 4b20 ldr r3, [pc, #128] @ (801540c ) 801538a: 681b ldr r3, [r3, #0] 801538c: 3304 adds r3, #4 801538e: 4618 mov r0, r3 8015390: f7fd fc18 bl 8012bc4 mtCOVERAGE_TEST_MARKER(); } #if ( INCLUDE_vTaskSuspend == 1 ) { if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) 8015394: 687b ldr r3, [r7, #4] 8015396: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801539a: d10a bne.n 80153b2 801539c: 683b ldr r3, [r7, #0] 801539e: 2b00 cmp r3, #0 80153a0: d007 beq.n 80153b2 { /* Add the task to the suspended task list instead of a delayed task list to ensure it is not woken by a timing event. It will block indefinitely. */ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 80153a2: 4b1a ldr r3, [pc, #104] @ (801540c ) 80153a4: 681b ldr r3, [r3, #0] 80153a6: 3304 adds r3, #4 80153a8: 4619 mov r1, r3 80153aa: 4819 ldr r0, [pc, #100] @ (8015410 ) 80153ac: f7fd fbad bl 8012b0a /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } 80153b0: e026 b.n 8015400 xTimeToWake = xConstTickCount + xTicksToWait; 80153b2: 68fa ldr r2, [r7, #12] 80153b4: 687b ldr r3, [r7, #4] 80153b6: 4413 add r3, r2 80153b8: 60bb str r3, [r7, #8] listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 80153ba: 4b14 ldr r3, [pc, #80] @ (801540c ) 80153bc: 681b ldr r3, [r3, #0] 80153be: 68ba ldr r2, [r7, #8] 80153c0: 605a str r2, [r3, #4] if( xTimeToWake < xConstTickCount ) 80153c2: 68ba ldr r2, [r7, #8] 80153c4: 68fb ldr r3, [r7, #12] 80153c6: 429a cmp r2, r3 80153c8: d209 bcs.n 80153de vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 80153ca: 4b12 ldr r3, [pc, #72] @ (8015414 ) 80153cc: 681a ldr r2, [r3, #0] 80153ce: 4b0f ldr r3, [pc, #60] @ (801540c ) 80153d0: 681b ldr r3, [r3, #0] 80153d2: 3304 adds r3, #4 80153d4: 4619 mov r1, r3 80153d6: 4610 mov r0, r2 80153d8: f7fd fbbb bl 8012b52 } 80153dc: e010 b.n 8015400 vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 80153de: 4b0e ldr r3, [pc, #56] @ (8015418 ) 80153e0: 681a ldr r2, [r3, #0] 80153e2: 4b0a ldr r3, [pc, #40] @ (801540c ) 80153e4: 681b ldr r3, [r3, #0] 80153e6: 3304 adds r3, #4 80153e8: 4619 mov r1, r3 80153ea: 4610 mov r0, r2 80153ec: f7fd fbb1 bl 8012b52 if( xTimeToWake < xNextTaskUnblockTime ) 80153f0: 4b0a ldr r3, [pc, #40] @ (801541c ) 80153f2: 681b ldr r3, [r3, #0] 80153f4: 68ba ldr r2, [r7, #8] 80153f6: 429a cmp r2, r3 80153f8: d202 bcs.n 8015400 xNextTaskUnblockTime = xTimeToWake; 80153fa: 4a08 ldr r2, [pc, #32] @ (801541c ) 80153fc: 68bb ldr r3, [r7, #8] 80153fe: 6013 str r3, [r2, #0] } 8015400: bf00 nop 8015402: 3710 adds r7, #16 8015404: 46bd mov sp, r7 8015406: bd80 pop {r7, pc} 8015408: 24002a7c .word 0x24002a7c 801540c: 240025a4 .word 0x240025a4 8015410: 24002a64 .word 0x24002a64 8015414: 24002a34 .word 0x24002a34 8015418: 24002a30 .word 0x24002a30 801541c: 24002a98 .word 0x24002a98 08015420 : TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ BaseType_t xTimerCreateTimerTask( void ) { 8015420: b580 push {r7, lr} 8015422: b08a sub sp, #40 @ 0x28 8015424: af04 add r7, sp, #16 BaseType_t xReturn = pdFAIL; 8015426: 2300 movs r3, #0 8015428: 617b str r3, [r7, #20] /* This function is called when the scheduler is started if configUSE_TIMERS is set to 1. Check that the infrastructure used by the timer service task has been created/initialised. If timers have already been created then the initialisation will already have been performed. */ prvCheckForValidListAndQueue(); 801542a: f000 fbb1 bl 8015b90 if( xTimerQueue != NULL ) 801542e: 4b1d ldr r3, [pc, #116] @ (80154a4 ) 8015430: 681b ldr r3, [r3, #0] 8015432: 2b00 cmp r3, #0 8015434: d021 beq.n 801547a { #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxTimerTaskTCBBuffer = NULL; 8015436: 2300 movs r3, #0 8015438: 60fb str r3, [r7, #12] StackType_t *pxTimerTaskStackBuffer = NULL; 801543a: 2300 movs r3, #0 801543c: 60bb str r3, [r7, #8] uint32_t ulTimerTaskStackSize; vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); 801543e: 1d3a adds r2, r7, #4 8015440: f107 0108 add.w r1, r7, #8 8015444: f107 030c add.w r3, r7, #12 8015448: 4618 mov r0, r3 801544a: f7fd fb17 bl 8012a7c xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, 801544e: 6879 ldr r1, [r7, #4] 8015450: 68bb ldr r3, [r7, #8] 8015452: 68fa ldr r2, [r7, #12] 8015454: 9202 str r2, [sp, #8] 8015456: 9301 str r3, [sp, #4] 8015458: 2302 movs r3, #2 801545a: 9300 str r3, [sp, #0] 801545c: 2300 movs r3, #0 801545e: 460a mov r2, r1 8015460: 4911 ldr r1, [pc, #68] @ (80154a8 ) 8015462: 4812 ldr r0, [pc, #72] @ (80154ac ) 8015464: f7fe fd2f bl 8013ec6 8015468: 4603 mov r3, r0 801546a: 4a11 ldr r2, [pc, #68] @ (80154b0 ) 801546c: 6013 str r3, [r2, #0] NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, pxTimerTaskStackBuffer, pxTimerTaskTCBBuffer ); if( xTimerTaskHandle != NULL ) 801546e: 4b10 ldr r3, [pc, #64] @ (80154b0 ) 8015470: 681b ldr r3, [r3, #0] 8015472: 2b00 cmp r3, #0 8015474: d001 beq.n 801547a { xReturn = pdPASS; 8015476: 2301 movs r3, #1 8015478: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } configASSERT( xReturn ); 801547a: 697b ldr r3, [r7, #20] 801547c: 2b00 cmp r3, #0 801547e: d10b bne.n 8015498 __asm volatile 8015480: f04f 0350 mov.w r3, #80 @ 0x50 8015484: f383 8811 msr BASEPRI, r3 8015488: f3bf 8f6f isb sy 801548c: f3bf 8f4f dsb sy 8015490: 613b str r3, [r7, #16] } 8015492: bf00 nop 8015494: bf00 nop 8015496: e7fd b.n 8015494 return xReturn; 8015498: 697b ldr r3, [r7, #20] } 801549a: 4618 mov r0, r3 801549c: 3718 adds r7, #24 801549e: 46bd mov sp, r7 80154a0: bd80 pop {r7, pc} 80154a2: bf00 nop 80154a4: 24002ad4 .word 0x24002ad4 80154a8: 08017554 .word 0x08017554 80154ac: 08015729 .word 0x08015729 80154b0: 24002ad8 .word 0x24002ad8 080154b4 : TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) { 80154b4: b580 push {r7, lr} 80154b6: b088 sub sp, #32 80154b8: af02 add r7, sp, #8 80154ba: 60f8 str r0, [r7, #12] 80154bc: 60b9 str r1, [r7, #8] 80154be: 607a str r2, [r7, #4] 80154c0: 603b str r3, [r7, #0] Timer_t *pxNewTimer; pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */ 80154c2: 202c movs r0, #44 @ 0x2c 80154c4: f000 fe42 bl 801614c 80154c8: 6178 str r0, [r7, #20] if( pxNewTimer != NULL ) 80154ca: 697b ldr r3, [r7, #20] 80154cc: 2b00 cmp r3, #0 80154ce: d00d beq.n 80154ec { /* Status is thus far zero as the timer is not created statically and has not been started. The auto-reload bit may get set in prvInitialiseNewTimer. */ pxNewTimer->ucStatus = 0x00; 80154d0: 697b ldr r3, [r7, #20] 80154d2: 2200 movs r2, #0 80154d4: f883 2028 strb.w r2, [r3, #40] @ 0x28 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); 80154d8: 697b ldr r3, [r7, #20] 80154da: 9301 str r3, [sp, #4] 80154dc: 6a3b ldr r3, [r7, #32] 80154de: 9300 str r3, [sp, #0] 80154e0: 683b ldr r3, [r7, #0] 80154e2: 687a ldr r2, [r7, #4] 80154e4: 68b9 ldr r1, [r7, #8] 80154e6: 68f8 ldr r0, [r7, #12] 80154e8: f000 f845 bl 8015576 } return pxNewTimer; 80154ec: 697b ldr r3, [r7, #20] } 80154ee: 4618 mov r0, r3 80154f0: 3718 adds r7, #24 80154f2: 46bd mov sp, r7 80154f4: bd80 pop {r7, pc} 080154f6 : const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) { 80154f6: b580 push {r7, lr} 80154f8: b08a sub sp, #40 @ 0x28 80154fa: af02 add r7, sp, #8 80154fc: 60f8 str r0, [r7, #12] 80154fe: 60b9 str r1, [r7, #8] 8015500: 607a str r2, [r7, #4] 8015502: 603b str r3, [r7, #0] #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTimer_t equals the size of the real timer structure. */ volatile size_t xSize = sizeof( StaticTimer_t ); 8015504: 232c movs r3, #44 @ 0x2c 8015506: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( Timer_t ) ); 8015508: 693b ldr r3, [r7, #16] 801550a: 2b2c cmp r3, #44 @ 0x2c 801550c: d00b beq.n 8015526 __asm volatile 801550e: f04f 0350 mov.w r3, #80 @ 0x50 8015512: f383 8811 msr BASEPRI, r3 8015516: f3bf 8f6f isb sy 801551a: f3bf 8f4f dsb sy 801551e: 61bb str r3, [r7, #24] } 8015520: bf00 nop 8015522: bf00 nop 8015524: e7fd b.n 8015522 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 8015526: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ /* A pointer to a StaticTimer_t structure MUST be provided, use it. */ configASSERT( pxTimerBuffer ); 8015528: 6afb ldr r3, [r7, #44] @ 0x2c 801552a: 2b00 cmp r3, #0 801552c: d10b bne.n 8015546 __asm volatile 801552e: f04f 0350 mov.w r3, #80 @ 0x50 8015532: f383 8811 msr BASEPRI, r3 8015536: f3bf 8f6f isb sy 801553a: f3bf 8f4f dsb sy 801553e: 617b str r3, [r7, #20] } 8015540: bf00 nop 8015542: bf00 nop 8015544: e7fd b.n 8015542 pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */ 8015546: 6afb ldr r3, [r7, #44] @ 0x2c 8015548: 61fb str r3, [r7, #28] if( pxNewTimer != NULL ) 801554a: 69fb ldr r3, [r7, #28] 801554c: 2b00 cmp r3, #0 801554e: d00d beq.n 801556c { /* Timers can be created statically or dynamically so note this timer was created statically in case it is later deleted. The auto-reload bit may get set in prvInitialiseNewTimer(). */ pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED; 8015550: 69fb ldr r3, [r7, #28] 8015552: 2202 movs r2, #2 8015554: f883 2028 strb.w r2, [r3, #40] @ 0x28 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); 8015558: 69fb ldr r3, [r7, #28] 801555a: 9301 str r3, [sp, #4] 801555c: 6abb ldr r3, [r7, #40] @ 0x28 801555e: 9300 str r3, [sp, #0] 8015560: 683b ldr r3, [r7, #0] 8015562: 687a ldr r2, [r7, #4] 8015564: 68b9 ldr r1, [r7, #8] 8015566: 68f8 ldr r0, [r7, #12] 8015568: f000 f805 bl 8015576 } return pxNewTimer; 801556c: 69fb ldr r3, [r7, #28] } 801556e: 4618 mov r0, r3 8015570: 3720 adds r7, #32 8015572: 46bd mov sp, r7 8015574: bd80 pop {r7, pc} 08015576 : const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) { 8015576: b580 push {r7, lr} 8015578: b086 sub sp, #24 801557a: af00 add r7, sp, #0 801557c: 60f8 str r0, [r7, #12] 801557e: 60b9 str r1, [r7, #8] 8015580: 607a str r2, [r7, #4] 8015582: 603b str r3, [r7, #0] /* 0 is not a valid value for xTimerPeriodInTicks. */ configASSERT( ( xTimerPeriodInTicks > 0 ) ); 8015584: 68bb ldr r3, [r7, #8] 8015586: 2b00 cmp r3, #0 8015588: d10b bne.n 80155a2 __asm volatile 801558a: f04f 0350 mov.w r3, #80 @ 0x50 801558e: f383 8811 msr BASEPRI, r3 8015592: f3bf 8f6f isb sy 8015596: f3bf 8f4f dsb sy 801559a: 617b str r3, [r7, #20] } 801559c: bf00 nop 801559e: bf00 nop 80155a0: e7fd b.n 801559e if( pxNewTimer != NULL ) 80155a2: 6a7b ldr r3, [r7, #36] @ 0x24 80155a4: 2b00 cmp r3, #0 80155a6: d01e beq.n 80155e6 { /* Ensure the infrastructure used by the timer service task has been created/initialised. */ prvCheckForValidListAndQueue(); 80155a8: f000 faf2 bl 8015b90 /* Initialise the timer structure members using the function parameters. */ pxNewTimer->pcTimerName = pcTimerName; 80155ac: 6a7b ldr r3, [r7, #36] @ 0x24 80155ae: 68fa ldr r2, [r7, #12] 80155b0: 601a str r2, [r3, #0] pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks; 80155b2: 6a7b ldr r3, [r7, #36] @ 0x24 80155b4: 68ba ldr r2, [r7, #8] 80155b6: 619a str r2, [r3, #24] pxNewTimer->pvTimerID = pvTimerID; 80155b8: 6a7b ldr r3, [r7, #36] @ 0x24 80155ba: 683a ldr r2, [r7, #0] 80155bc: 61da str r2, [r3, #28] pxNewTimer->pxCallbackFunction = pxCallbackFunction; 80155be: 6a7b ldr r3, [r7, #36] @ 0x24 80155c0: 6a3a ldr r2, [r7, #32] 80155c2: 621a str r2, [r3, #32] vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); 80155c4: 6a7b ldr r3, [r7, #36] @ 0x24 80155c6: 3304 adds r3, #4 80155c8: 4618 mov r0, r3 80155ca: f7fd fa91 bl 8012af0 if( uxAutoReload != pdFALSE ) 80155ce: 687b ldr r3, [r7, #4] 80155d0: 2b00 cmp r3, #0 80155d2: d008 beq.n 80155e6 { pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; 80155d4: 6a7b ldr r3, [r7, #36] @ 0x24 80155d6: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80155da: f043 0304 orr.w r3, r3, #4 80155de: b2da uxtb r2, r3 80155e0: 6a7b ldr r3, [r7, #36] @ 0x24 80155e2: f883 2028 strb.w r2, [r3, #40] @ 0x28 } traceTIMER_CREATE( pxNewTimer ); } } 80155e6: bf00 nop 80155e8: 3718 adds r7, #24 80155ea: 46bd mov sp, r7 80155ec: bd80 pop {r7, pc} ... 080155f0 : /*-----------------------------------------------------------*/ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) { 80155f0: b580 push {r7, lr} 80155f2: b08a sub sp, #40 @ 0x28 80155f4: af00 add r7, sp, #0 80155f6: 60f8 str r0, [r7, #12] 80155f8: 60b9 str r1, [r7, #8] 80155fa: 607a str r2, [r7, #4] 80155fc: 603b str r3, [r7, #0] BaseType_t xReturn = pdFAIL; 80155fe: 2300 movs r3, #0 8015600: 627b str r3, [r7, #36] @ 0x24 DaemonTaskMessage_t xMessage; configASSERT( xTimer ); 8015602: 68fb ldr r3, [r7, #12] 8015604: 2b00 cmp r3, #0 8015606: d10b bne.n 8015620 __asm volatile 8015608: f04f 0350 mov.w r3, #80 @ 0x50 801560c: f383 8811 msr BASEPRI, r3 8015610: f3bf 8f6f isb sy 8015614: f3bf 8f4f dsb sy 8015618: 623b str r3, [r7, #32] } 801561a: bf00 nop 801561c: bf00 nop 801561e: e7fd b.n 801561c /* Send a message to the timer service task to perform a particular action on a particular timer definition. */ if( xTimerQueue != NULL ) 8015620: 4b19 ldr r3, [pc, #100] @ (8015688 ) 8015622: 681b ldr r3, [r3, #0] 8015624: 2b00 cmp r3, #0 8015626: d02a beq.n 801567e { /* Send a command to the timer service task to start the xTimer timer. */ xMessage.xMessageID = xCommandID; 8015628: 68bb ldr r3, [r7, #8] 801562a: 613b str r3, [r7, #16] xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; 801562c: 687b ldr r3, [r7, #4] 801562e: 617b str r3, [r7, #20] xMessage.u.xTimerParameters.pxTimer = xTimer; 8015630: 68fb ldr r3, [r7, #12] 8015632: 61bb str r3, [r7, #24] if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) 8015634: 68bb ldr r3, [r7, #8] 8015636: 2b05 cmp r3, #5 8015638: dc18 bgt.n 801566c { if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) 801563a: f7ff fae1 bl 8014c00 801563e: 4603 mov r3, r0 8015640: 2b02 cmp r3, #2 8015642: d109 bne.n 8015658 { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); 8015644: 4b10 ldr r3, [pc, #64] @ (8015688 ) 8015646: 6818 ldr r0, [r3, #0] 8015648: f107 0110 add.w r1, r7, #16 801564c: 2300 movs r3, #0 801564e: 6b3a ldr r2, [r7, #48] @ 0x30 8015650: f7fd fce0 bl 8013014 8015654: 6278 str r0, [r7, #36] @ 0x24 8015656: e012 b.n 801567e } else { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); 8015658: 4b0b ldr r3, [pc, #44] @ (8015688 ) 801565a: 6818 ldr r0, [r3, #0] 801565c: f107 0110 add.w r1, r7, #16 8015660: 2300 movs r3, #0 8015662: 2200 movs r2, #0 8015664: f7fd fcd6 bl 8013014 8015668: 6278 str r0, [r7, #36] @ 0x24 801566a: e008 b.n 801567e } } else { xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); 801566c: 4b06 ldr r3, [pc, #24] @ (8015688 ) 801566e: 6818 ldr r0, [r3, #0] 8015670: f107 0110 add.w r1, r7, #16 8015674: 2300 movs r3, #0 8015676: 683a ldr r2, [r7, #0] 8015678: f7fd fdce bl 8013218 801567c: 6278 str r0, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 801567e: 6a7b ldr r3, [r7, #36] @ 0x24 } 8015680: 4618 mov r0, r3 8015682: 3728 adds r7, #40 @ 0x28 8015684: 46bd mov sp, r7 8015686: bd80 pop {r7, pc} 8015688: 24002ad4 .word 0x24002ad4 0801568c : return pxTimer->pcTimerName; } /*-----------------------------------------------------------*/ static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) { 801568c: b580 push {r7, lr} 801568e: b088 sub sp, #32 8015690: af02 add r7, sp, #8 8015692: 6078 str r0, [r7, #4] 8015694: 6039 str r1, [r7, #0] BaseType_t xResult; Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015696: 4b23 ldr r3, [pc, #140] @ (8015724 ) 8015698: 681b ldr r3, [r3, #0] 801569a: 68db ldr r3, [r3, #12] 801569c: 68db ldr r3, [r3, #12] 801569e: 617b str r3, [r7, #20] /* Remove the timer from the list of active timers. A check has already been performed to ensure the list is not empty. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 80156a0: 697b ldr r3, [r7, #20] 80156a2: 3304 adds r3, #4 80156a4: 4618 mov r0, r3 80156a6: f7fd fa8d bl 8012bc4 traceTIMER_EXPIRED( pxTimer ); /* If the timer is an auto-reload timer then calculate the next expiry time and re-insert the timer in the list of active timers. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 80156aa: 697b ldr r3, [r7, #20] 80156ac: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80156b0: f003 0304 and.w r3, r3, #4 80156b4: 2b00 cmp r3, #0 80156b6: d023 beq.n 8015700 { /* The timer is inserted into a list using a time relative to anything other than the current time. It will therefore be inserted into the correct list relative to the time this task thinks it is now. */ if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) 80156b8: 697b ldr r3, [r7, #20] 80156ba: 699a ldr r2, [r3, #24] 80156bc: 687b ldr r3, [r7, #4] 80156be: 18d1 adds r1, r2, r3 80156c0: 687b ldr r3, [r7, #4] 80156c2: 683a ldr r2, [r7, #0] 80156c4: 6978 ldr r0, [r7, #20] 80156c6: f000 f8d5 bl 8015874 80156ca: 4603 mov r3, r0 80156cc: 2b00 cmp r3, #0 80156ce: d020 beq.n 8015712 { /* The timer expired before it was added to the active timer list. Reload it now. */ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 80156d0: 2300 movs r3, #0 80156d2: 9300 str r3, [sp, #0] 80156d4: 2300 movs r3, #0 80156d6: 687a ldr r2, [r7, #4] 80156d8: 2100 movs r1, #0 80156da: 6978 ldr r0, [r7, #20] 80156dc: f7ff ff88 bl 80155f0 80156e0: 6138 str r0, [r7, #16] configASSERT( xResult ); 80156e2: 693b ldr r3, [r7, #16] 80156e4: 2b00 cmp r3, #0 80156e6: d114 bne.n 8015712 __asm volatile 80156e8: f04f 0350 mov.w r3, #80 @ 0x50 80156ec: f383 8811 msr BASEPRI, r3 80156f0: f3bf 8f6f isb sy 80156f4: f3bf 8f4f dsb sy 80156f8: 60fb str r3, [r7, #12] } 80156fa: bf00 nop 80156fc: bf00 nop 80156fe: e7fd b.n 80156fc mtCOVERAGE_TEST_MARKER(); } } else { pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8015700: 697b ldr r3, [r7, #20] 8015702: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8015706: f023 0301 bic.w r3, r3, #1 801570a: b2da uxtb r2, r3 801570c: 697b ldr r3, [r7, #20] 801570e: f883 2028 strb.w r2, [r3, #40] @ 0x28 mtCOVERAGE_TEST_MARKER(); } /* Call the timer callback. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8015712: 697b ldr r3, [r7, #20] 8015714: 6a1b ldr r3, [r3, #32] 8015716: 6978 ldr r0, [r7, #20] 8015718: 4798 blx r3 } 801571a: bf00 nop 801571c: 3718 adds r7, #24 801571e: 46bd mov sp, r7 8015720: bd80 pop {r7, pc} 8015722: bf00 nop 8015724: 24002acc .word 0x24002acc 08015728 : /*-----------------------------------------------------------*/ static portTASK_FUNCTION( prvTimerTask, pvParameters ) { 8015728: b580 push {r7, lr} 801572a: b084 sub sp, #16 801572c: af00 add r7, sp, #0 801572e: 6078 str r0, [r7, #4] for( ;; ) { /* Query the timers list to see if it contains any timers, and if so, obtain the time at which the next timer will expire. */ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8015730: f107 0308 add.w r3, r7, #8 8015734: 4618 mov r0, r3 8015736: f000 f859 bl 80157ec 801573a: 60f8 str r0, [r7, #12] /* If a timer has expired, process it. Otherwise, block this task until either a timer does expire, or a command is received. */ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); 801573c: 68bb ldr r3, [r7, #8] 801573e: 4619 mov r1, r3 8015740: 68f8 ldr r0, [r7, #12] 8015742: f000 f805 bl 8015750 /* Empty the command queue. */ prvProcessReceivedCommands(); 8015746: f000 f8d7 bl 80158f8 xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 801574a: bf00 nop 801574c: e7f0 b.n 8015730 ... 08015750 : } } /*-----------------------------------------------------------*/ static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) { 8015750: b580 push {r7, lr} 8015752: b084 sub sp, #16 8015754: af00 add r7, sp, #0 8015756: 6078 str r0, [r7, #4] 8015758: 6039 str r1, [r7, #0] TickType_t xTimeNow; BaseType_t xTimerListsWereSwitched; vTaskSuspendAll(); 801575a: f7fe fe17 bl 801438c /* Obtain the time now to make an assessment as to whether the timer has expired or not. If obtaining the time causes the lists to switch then don't process this timer as any timers that remained in the list when the lists were switched will have been processed within the prvSampleTimeNow() function. */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 801575e: f107 0308 add.w r3, r7, #8 8015762: 4618 mov r0, r3 8015764: f000 f866 bl 8015834 8015768: 60f8 str r0, [r7, #12] if( xTimerListsWereSwitched == pdFALSE ) 801576a: 68bb ldr r3, [r7, #8] 801576c: 2b00 cmp r3, #0 801576e: d130 bne.n 80157d2 { /* The tick count has not overflowed, has the timer expired? */ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) 8015770: 683b ldr r3, [r7, #0] 8015772: 2b00 cmp r3, #0 8015774: d10a bne.n 801578c 8015776: 687a ldr r2, [r7, #4] 8015778: 68fb ldr r3, [r7, #12] 801577a: 429a cmp r2, r3 801577c: d806 bhi.n 801578c { ( void ) xTaskResumeAll(); 801577e: f7fe fe13 bl 80143a8 prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); 8015782: 68f9 ldr r1, [r7, #12] 8015784: 6878 ldr r0, [r7, #4] 8015786: f7ff ff81 bl 801568c else { ( void ) xTaskResumeAll(); } } } 801578a: e024 b.n 80157d6 if( xListWasEmpty != pdFALSE ) 801578c: 683b ldr r3, [r7, #0] 801578e: 2b00 cmp r3, #0 8015790: d008 beq.n 80157a4 xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); 8015792: 4b13 ldr r3, [pc, #76] @ (80157e0 ) 8015794: 681b ldr r3, [r3, #0] 8015796: 681b ldr r3, [r3, #0] 8015798: 2b00 cmp r3, #0 801579a: d101 bne.n 80157a0 801579c: 2301 movs r3, #1 801579e: e000 b.n 80157a2 80157a0: 2300 movs r3, #0 80157a2: 603b str r3, [r7, #0] vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); 80157a4: 4b0f ldr r3, [pc, #60] @ (80157e4 ) 80157a6: 6818 ldr r0, [r3, #0] 80157a8: 687a ldr r2, [r7, #4] 80157aa: 68fb ldr r3, [r7, #12] 80157ac: 1ad3 subs r3, r2, r3 80157ae: 683a ldr r2, [r7, #0] 80157b0: 4619 mov r1, r3 80157b2: f7fe f995 bl 8013ae0 if( xTaskResumeAll() == pdFALSE ) 80157b6: f7fe fdf7 bl 80143a8 80157ba: 4603 mov r3, r0 80157bc: 2b00 cmp r3, #0 80157be: d10a bne.n 80157d6 portYIELD_WITHIN_API(); 80157c0: 4b09 ldr r3, [pc, #36] @ (80157e8 ) 80157c2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80157c6: 601a str r2, [r3, #0] 80157c8: f3bf 8f4f dsb sy 80157cc: f3bf 8f6f isb sy } 80157d0: e001 b.n 80157d6 ( void ) xTaskResumeAll(); 80157d2: f7fe fde9 bl 80143a8 } 80157d6: bf00 nop 80157d8: 3710 adds r7, #16 80157da: 46bd mov sp, r7 80157dc: bd80 pop {r7, pc} 80157de: bf00 nop 80157e0: 24002ad0 .word 0x24002ad0 80157e4: 24002ad4 .word 0x24002ad4 80157e8: e000ed04 .word 0xe000ed04 080157ec : /*-----------------------------------------------------------*/ static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) { 80157ec: b480 push {r7} 80157ee: b085 sub sp, #20 80157f0: af00 add r7, sp, #0 80157f2: 6078 str r0, [r7, #4] the timer with the nearest expiry time will expire. If there are no active timers then just set the next expire time to 0. That will cause this task to unblock when the tick count overflows, at which point the timer lists will be switched and the next expiry time can be re-assessed. */ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); 80157f4: 4b0e ldr r3, [pc, #56] @ (8015830 ) 80157f6: 681b ldr r3, [r3, #0] 80157f8: 681b ldr r3, [r3, #0] 80157fa: 2b00 cmp r3, #0 80157fc: d101 bne.n 8015802 80157fe: 2201 movs r2, #1 8015800: e000 b.n 8015804 8015802: 2200 movs r2, #0 8015804: 687b ldr r3, [r7, #4] 8015806: 601a str r2, [r3, #0] if( *pxListWasEmpty == pdFALSE ) 8015808: 687b ldr r3, [r7, #4] 801580a: 681b ldr r3, [r3, #0] 801580c: 2b00 cmp r3, #0 801580e: d105 bne.n 801581c { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 8015810: 4b07 ldr r3, [pc, #28] @ (8015830 ) 8015812: 681b ldr r3, [r3, #0] 8015814: 68db ldr r3, [r3, #12] 8015816: 681b ldr r3, [r3, #0] 8015818: 60fb str r3, [r7, #12] 801581a: e001 b.n 8015820 } else { /* Ensure the task unblocks when the tick count rolls over. */ xNextExpireTime = ( TickType_t ) 0U; 801581c: 2300 movs r3, #0 801581e: 60fb str r3, [r7, #12] } return xNextExpireTime; 8015820: 68fb ldr r3, [r7, #12] } 8015822: 4618 mov r0, r3 8015824: 3714 adds r7, #20 8015826: 46bd mov sp, r7 8015828: f85d 7b04 ldr.w r7, [sp], #4 801582c: 4770 bx lr 801582e: bf00 nop 8015830: 24002acc .word 0x24002acc 08015834 : /*-----------------------------------------------------------*/ static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) { 8015834: b580 push {r7, lr} 8015836: b084 sub sp, #16 8015838: af00 add r7, sp, #0 801583a: 6078 str r0, [r7, #4] TickType_t xTimeNow; PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ xTimeNow = xTaskGetTickCount(); 801583c: f7fe fe52 bl 80144e4 8015840: 60f8 str r0, [r7, #12] if( xTimeNow < xLastTime ) 8015842: 4b0b ldr r3, [pc, #44] @ (8015870 ) 8015844: 681b ldr r3, [r3, #0] 8015846: 68fa ldr r2, [r7, #12] 8015848: 429a cmp r2, r3 801584a: d205 bcs.n 8015858 { prvSwitchTimerLists(); 801584c: f000 f93a bl 8015ac4 *pxTimerListsWereSwitched = pdTRUE; 8015850: 687b ldr r3, [r7, #4] 8015852: 2201 movs r2, #1 8015854: 601a str r2, [r3, #0] 8015856: e002 b.n 801585e } else { *pxTimerListsWereSwitched = pdFALSE; 8015858: 687b ldr r3, [r7, #4] 801585a: 2200 movs r2, #0 801585c: 601a str r2, [r3, #0] } xLastTime = xTimeNow; 801585e: 4a04 ldr r2, [pc, #16] @ (8015870 ) 8015860: 68fb ldr r3, [r7, #12] 8015862: 6013 str r3, [r2, #0] return xTimeNow; 8015864: 68fb ldr r3, [r7, #12] } 8015866: 4618 mov r0, r3 8015868: 3710 adds r7, #16 801586a: 46bd mov sp, r7 801586c: bd80 pop {r7, pc} 801586e: bf00 nop 8015870: 24002adc .word 0x24002adc 08015874 : /*-----------------------------------------------------------*/ static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) { 8015874: b580 push {r7, lr} 8015876: b086 sub sp, #24 8015878: af00 add r7, sp, #0 801587a: 60f8 str r0, [r7, #12] 801587c: 60b9 str r1, [r7, #8] 801587e: 607a str r2, [r7, #4] 8015880: 603b str r3, [r7, #0] BaseType_t xProcessTimerNow = pdFALSE; 8015882: 2300 movs r3, #0 8015884: 617b str r3, [r7, #20] listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); 8015886: 68fb ldr r3, [r7, #12] 8015888: 68ba ldr r2, [r7, #8] 801588a: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 801588c: 68fb ldr r3, [r7, #12] 801588e: 68fa ldr r2, [r7, #12] 8015890: 611a str r2, [r3, #16] if( xNextExpiryTime <= xTimeNow ) 8015892: 68ba ldr r2, [r7, #8] 8015894: 687b ldr r3, [r7, #4] 8015896: 429a cmp r2, r3 8015898: d812 bhi.n 80158c0 { /* Has the expiry time elapsed between the command to start/reset a timer was issued, and the time the command was processed? */ if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 801589a: 687a ldr r2, [r7, #4] 801589c: 683b ldr r3, [r7, #0] 801589e: 1ad2 subs r2, r2, r3 80158a0: 68fb ldr r3, [r7, #12] 80158a2: 699b ldr r3, [r3, #24] 80158a4: 429a cmp r2, r3 80158a6: d302 bcc.n 80158ae { /* The time between a command being issued and the command being processed actually exceeds the timers period. */ xProcessTimerNow = pdTRUE; 80158a8: 2301 movs r3, #1 80158aa: 617b str r3, [r7, #20] 80158ac: e01b b.n 80158e6 } else { vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); 80158ae: 4b10 ldr r3, [pc, #64] @ (80158f0 ) 80158b0: 681a ldr r2, [r3, #0] 80158b2: 68fb ldr r3, [r7, #12] 80158b4: 3304 adds r3, #4 80158b6: 4619 mov r1, r3 80158b8: 4610 mov r0, r2 80158ba: f7fd f94a bl 8012b52 80158be: e012 b.n 80158e6 } } else { if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) 80158c0: 687a ldr r2, [r7, #4] 80158c2: 683b ldr r3, [r7, #0] 80158c4: 429a cmp r2, r3 80158c6: d206 bcs.n 80158d6 80158c8: 68ba ldr r2, [r7, #8] 80158ca: 683b ldr r3, [r7, #0] 80158cc: 429a cmp r2, r3 80158ce: d302 bcc.n 80158d6 { /* If, since the command was issued, the tick count has overflowed but the expiry time has not, then the timer must have already passed its expiry time and should be processed immediately. */ xProcessTimerNow = pdTRUE; 80158d0: 2301 movs r3, #1 80158d2: 617b str r3, [r7, #20] 80158d4: e007 b.n 80158e6 } else { vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 80158d6: 4b07 ldr r3, [pc, #28] @ (80158f4 ) 80158d8: 681a ldr r2, [r3, #0] 80158da: 68fb ldr r3, [r7, #12] 80158dc: 3304 adds r3, #4 80158de: 4619 mov r1, r3 80158e0: 4610 mov r0, r2 80158e2: f7fd f936 bl 8012b52 } } return xProcessTimerNow; 80158e6: 697b ldr r3, [r7, #20] } 80158e8: 4618 mov r0, r3 80158ea: 3718 adds r7, #24 80158ec: 46bd mov sp, r7 80158ee: bd80 pop {r7, pc} 80158f0: 24002ad0 .word 0x24002ad0 80158f4: 24002acc .word 0x24002acc 080158f8 : /*-----------------------------------------------------------*/ static void prvProcessReceivedCommands( void ) { 80158f8: b580 push {r7, lr} 80158fa: b08e sub sp, #56 @ 0x38 80158fc: af02 add r7, sp, #8 DaemonTaskMessage_t xMessage; Timer_t *pxTimer; BaseType_t xTimerListsWereSwitched, xResult; TickType_t xTimeNow; while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 80158fe: e0ce b.n 8015a9e { #if ( INCLUDE_xTimerPendFunctionCall == 1 ) { /* Negative commands are pended function calls rather than timer commands. */ if( xMessage.xMessageID < ( BaseType_t ) 0 ) 8015900: 687b ldr r3, [r7, #4] 8015902: 2b00 cmp r3, #0 8015904: da19 bge.n 801593a { const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); 8015906: 1d3b adds r3, r7, #4 8015908: 3304 adds r3, #4 801590a: 62fb str r3, [r7, #44] @ 0x2c /* The timer uses the xCallbackParameters member to request a callback be executed. Check the callback is not NULL. */ configASSERT( pxCallback ); 801590c: 6afb ldr r3, [r7, #44] @ 0x2c 801590e: 2b00 cmp r3, #0 8015910: d10b bne.n 801592a __asm volatile 8015912: f04f 0350 mov.w r3, #80 @ 0x50 8015916: f383 8811 msr BASEPRI, r3 801591a: f3bf 8f6f isb sy 801591e: f3bf 8f4f dsb sy 8015922: 61fb str r3, [r7, #28] } 8015924: bf00 nop 8015926: bf00 nop 8015928: e7fd b.n 8015926 /* Call the function. */ pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); 801592a: 6afb ldr r3, [r7, #44] @ 0x2c 801592c: 681b ldr r3, [r3, #0] 801592e: 6afa ldr r2, [r7, #44] @ 0x2c 8015930: 6850 ldr r0, [r2, #4] 8015932: 6afa ldr r2, [r7, #44] @ 0x2c 8015934: 6892 ldr r2, [r2, #8] 8015936: 4611 mov r1, r2 8015938: 4798 blx r3 } #endif /* INCLUDE_xTimerPendFunctionCall */ /* Commands that are positive are timer commands rather than pended function calls. */ if( xMessage.xMessageID >= ( BaseType_t ) 0 ) 801593a: 687b ldr r3, [r7, #4] 801593c: 2b00 cmp r3, #0 801593e: f2c0 80ae blt.w 8015a9e { /* The messages uses the xTimerParameters member to work on a software timer. */ pxTimer = xMessage.u.xTimerParameters.pxTimer; 8015942: 68fb ldr r3, [r7, #12] 8015944: 62bb str r3, [r7, #40] @ 0x28 if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ 8015946: 6abb ldr r3, [r7, #40] @ 0x28 8015948: 695b ldr r3, [r3, #20] 801594a: 2b00 cmp r3, #0 801594c: d004 beq.n 8015958 { /* The timer is in a list, remove it. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 801594e: 6abb ldr r3, [r7, #40] @ 0x28 8015950: 3304 adds r3, #4 8015952: 4618 mov r0, r3 8015954: f7fd f936 bl 8012bc4 it must be present in the function call. prvSampleTimeNow() must be called after the message is received from xTimerQueue so there is no possibility of a higher priority task adding a message to the message queue with a time that is ahead of the timer daemon task (because it pre-empted the timer daemon task after the xTimeNow value was set). */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8015958: 463b mov r3, r7 801595a: 4618 mov r0, r3 801595c: f7ff ff6a bl 8015834 8015960: 6278 str r0, [r7, #36] @ 0x24 switch( xMessage.xMessageID ) 8015962: 687b ldr r3, [r7, #4] 8015964: 2b09 cmp r3, #9 8015966: f200 8097 bhi.w 8015a98 801596a: a201 add r2, pc, #4 @ (adr r2, 8015970 ) 801596c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8015970: 08015999 .word 0x08015999 8015974: 08015999 .word 0x08015999 8015978: 08015999 .word 0x08015999 801597c: 08015a0f .word 0x08015a0f 8015980: 08015a23 .word 0x08015a23 8015984: 08015a6f .word 0x08015a6f 8015988: 08015999 .word 0x08015999 801598c: 08015999 .word 0x08015999 8015990: 08015a0f .word 0x08015a0f 8015994: 08015a23 .word 0x08015a23 case tmrCOMMAND_START_FROM_ISR : case tmrCOMMAND_RESET : case tmrCOMMAND_RESET_FROM_ISR : case tmrCOMMAND_START_DONT_TRACE : /* Start or restart a timer. */ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8015998: 6abb ldr r3, [r7, #40] @ 0x28 801599a: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 801599e: f043 0301 orr.w r3, r3, #1 80159a2: b2da uxtb r2, r3 80159a4: 6abb ldr r3, [r7, #40] @ 0x28 80159a6: f883 2028 strb.w r2, [r3, #40] @ 0x28 if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) 80159aa: 68ba ldr r2, [r7, #8] 80159ac: 6abb ldr r3, [r7, #40] @ 0x28 80159ae: 699b ldr r3, [r3, #24] 80159b0: 18d1 adds r1, r2, r3 80159b2: 68bb ldr r3, [r7, #8] 80159b4: 6a7a ldr r2, [r7, #36] @ 0x24 80159b6: 6ab8 ldr r0, [r7, #40] @ 0x28 80159b8: f7ff ff5c bl 8015874 80159bc: 4603 mov r3, r0 80159be: 2b00 cmp r3, #0 80159c0: d06c beq.n 8015a9c { /* The timer expired before it was added to the active timer list. Process it now. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 80159c2: 6abb ldr r3, [r7, #40] @ 0x28 80159c4: 6a1b ldr r3, [r3, #32] 80159c6: 6ab8 ldr r0, [r7, #40] @ 0x28 80159c8: 4798 blx r3 traceTIMER_EXPIRED( pxTimer ); if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 80159ca: 6abb ldr r3, [r7, #40] @ 0x28 80159cc: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80159d0: f003 0304 and.w r3, r3, #4 80159d4: 2b00 cmp r3, #0 80159d6: d061 beq.n 8015a9c { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); 80159d8: 68ba ldr r2, [r7, #8] 80159da: 6abb ldr r3, [r7, #40] @ 0x28 80159dc: 699b ldr r3, [r3, #24] 80159de: 441a add r2, r3 80159e0: 2300 movs r3, #0 80159e2: 9300 str r3, [sp, #0] 80159e4: 2300 movs r3, #0 80159e6: 2100 movs r1, #0 80159e8: 6ab8 ldr r0, [r7, #40] @ 0x28 80159ea: f7ff fe01 bl 80155f0 80159ee: 6238 str r0, [r7, #32] configASSERT( xResult ); 80159f0: 6a3b ldr r3, [r7, #32] 80159f2: 2b00 cmp r3, #0 80159f4: d152 bne.n 8015a9c __asm volatile 80159f6: f04f 0350 mov.w r3, #80 @ 0x50 80159fa: f383 8811 msr BASEPRI, r3 80159fe: f3bf 8f6f isb sy 8015a02: f3bf 8f4f dsb sy 8015a06: 61bb str r3, [r7, #24] } 8015a08: bf00 nop 8015a0a: bf00 nop 8015a0c: e7fd b.n 8015a0a break; case tmrCOMMAND_STOP : case tmrCOMMAND_STOP_FROM_ISR : /* The timer has already been removed from the active list. */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8015a0e: 6abb ldr r3, [r7, #40] @ 0x28 8015a10: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8015a14: f023 0301 bic.w r3, r3, #1 8015a18: b2da uxtb r2, r3 8015a1a: 6abb ldr r3, [r7, #40] @ 0x28 8015a1c: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8015a20: e03d b.n 8015a9e case tmrCOMMAND_CHANGE_PERIOD : case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR : pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8015a22: 6abb ldr r3, [r7, #40] @ 0x28 8015a24: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8015a28: f043 0301 orr.w r3, r3, #1 8015a2c: b2da uxtb r2, r3 8015a2e: 6abb ldr r3, [r7, #40] @ 0x28 8015a30: f883 2028 strb.w r2, [r3, #40] @ 0x28 pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; 8015a34: 68ba ldr r2, [r7, #8] 8015a36: 6abb ldr r3, [r7, #40] @ 0x28 8015a38: 619a str r2, [r3, #24] configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); 8015a3a: 6abb ldr r3, [r7, #40] @ 0x28 8015a3c: 699b ldr r3, [r3, #24] 8015a3e: 2b00 cmp r3, #0 8015a40: d10b bne.n 8015a5a __asm volatile 8015a42: f04f 0350 mov.w r3, #80 @ 0x50 8015a46: f383 8811 msr BASEPRI, r3 8015a4a: f3bf 8f6f isb sy 8015a4e: f3bf 8f4f dsb sy 8015a52: 617b str r3, [r7, #20] } 8015a54: bf00 nop 8015a56: bf00 nop 8015a58: e7fd b.n 8015a56 be longer or shorter than the old one. The command time is therefore set to the current time, and as the period cannot be zero the next expiry time can only be in the future, meaning (unlike for the xTimerStart() case above) there is no fail case that needs to be handled here. */ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); 8015a5a: 6abb ldr r3, [r7, #40] @ 0x28 8015a5c: 699a ldr r2, [r3, #24] 8015a5e: 6a7b ldr r3, [r7, #36] @ 0x24 8015a60: 18d1 adds r1, r2, r3 8015a62: 6a7b ldr r3, [r7, #36] @ 0x24 8015a64: 6a7a ldr r2, [r7, #36] @ 0x24 8015a66: 6ab8 ldr r0, [r7, #40] @ 0x28 8015a68: f7ff ff04 bl 8015874 break; 8015a6c: e017 b.n 8015a9e #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* The timer has already been removed from the active list, just free up the memory if the memory was dynamically allocated. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) 8015a6e: 6abb ldr r3, [r7, #40] @ 0x28 8015a70: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8015a74: f003 0302 and.w r3, r3, #2 8015a78: 2b00 cmp r3, #0 8015a7a: d103 bne.n 8015a84 { vPortFree( pxTimer ); 8015a7c: 6ab8 ldr r0, [r7, #40] @ 0x28 8015a7e: f000 fc33 bl 80162e8 no need to free the memory - just mark the timer as "not active". */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ break; 8015a82: e00c b.n 8015a9e pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8015a84: 6abb ldr r3, [r7, #40] @ 0x28 8015a86: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8015a8a: f023 0301 bic.w r3, r3, #1 8015a8e: b2da uxtb r2, r3 8015a90: 6abb ldr r3, [r7, #40] @ 0x28 8015a92: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8015a96: e002 b.n 8015a9e default : /* Don't expect to get here. */ break; 8015a98: bf00 nop 8015a9a: e000 b.n 8015a9e break; 8015a9c: bf00 nop while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 8015a9e: 4b08 ldr r3, [pc, #32] @ (8015ac0 ) 8015aa0: 681b ldr r3, [r3, #0] 8015aa2: 1d39 adds r1, r7, #4 8015aa4: 2200 movs r2, #0 8015aa6: 4618 mov r0, r3 8015aa8: f7fd fc54 bl 8013354 8015aac: 4603 mov r3, r0 8015aae: 2b00 cmp r3, #0 8015ab0: f47f af26 bne.w 8015900 } } } } 8015ab4: bf00 nop 8015ab6: bf00 nop 8015ab8: 3730 adds r7, #48 @ 0x30 8015aba: 46bd mov sp, r7 8015abc: bd80 pop {r7, pc} 8015abe: bf00 nop 8015ac0: 24002ad4 .word 0x24002ad4 08015ac4 : /*-----------------------------------------------------------*/ static void prvSwitchTimerLists( void ) { 8015ac4: b580 push {r7, lr} 8015ac6: b088 sub sp, #32 8015ac8: af02 add r7, sp, #8 /* The tick count has overflowed. The timer lists must be switched. If there are any timers still referenced from the current timer list then they must have expired and should be processed before the lists are switched. */ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 8015aca: e049 b.n 8015b60 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 8015acc: 4b2e ldr r3, [pc, #184] @ (8015b88 ) 8015ace: 681b ldr r3, [r3, #0] 8015ad0: 68db ldr r3, [r3, #12] 8015ad2: 681b ldr r3, [r3, #0] 8015ad4: 613b str r3, [r7, #16] /* Remove the timer from the list. */ pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015ad6: 4b2c ldr r3, [pc, #176] @ (8015b88 ) 8015ad8: 681b ldr r3, [r3, #0] 8015ada: 68db ldr r3, [r3, #12] 8015adc: 68db ldr r3, [r3, #12] 8015ade: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8015ae0: 68fb ldr r3, [r7, #12] 8015ae2: 3304 adds r3, #4 8015ae4: 4618 mov r0, r3 8015ae6: f7fd f86d bl 8012bc4 traceTIMER_EXPIRED( pxTimer ); /* Execute its callback, then send a command to restart the timer if it is an auto-reload timer. It cannot be restarted here as the lists have not yet been switched. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8015aea: 68fb ldr r3, [r7, #12] 8015aec: 6a1b ldr r3, [r3, #32] 8015aee: 68f8 ldr r0, [r7, #12] 8015af0: 4798 blx r3 if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 8015af2: 68fb ldr r3, [r7, #12] 8015af4: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8015af8: f003 0304 and.w r3, r3, #4 8015afc: 2b00 cmp r3, #0 8015afe: d02f beq.n 8015b60 the timer going into the same timer list then it has already expired and the timer should be re-inserted into the current list so it is processed again within this loop. Otherwise a command should be sent to restart the timer to ensure it is only inserted into a list after the lists have been swapped. */ xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); 8015b00: 68fb ldr r3, [r7, #12] 8015b02: 699b ldr r3, [r3, #24] 8015b04: 693a ldr r2, [r7, #16] 8015b06: 4413 add r3, r2 8015b08: 60bb str r3, [r7, #8] if( xReloadTime > xNextExpireTime ) 8015b0a: 68ba ldr r2, [r7, #8] 8015b0c: 693b ldr r3, [r7, #16] 8015b0e: 429a cmp r2, r3 8015b10: d90e bls.n 8015b30 { listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); 8015b12: 68fb ldr r3, [r7, #12] 8015b14: 68ba ldr r2, [r7, #8] 8015b16: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 8015b18: 68fb ldr r3, [r7, #12] 8015b1a: 68fa ldr r2, [r7, #12] 8015b1c: 611a str r2, [r3, #16] vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 8015b1e: 4b1a ldr r3, [pc, #104] @ (8015b88 ) 8015b20: 681a ldr r2, [r3, #0] 8015b22: 68fb ldr r3, [r7, #12] 8015b24: 3304 adds r3, #4 8015b26: 4619 mov r1, r3 8015b28: 4610 mov r0, r2 8015b2a: f7fd f812 bl 8012b52 8015b2e: e017 b.n 8015b60 } else { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 8015b30: 2300 movs r3, #0 8015b32: 9300 str r3, [sp, #0] 8015b34: 2300 movs r3, #0 8015b36: 693a ldr r2, [r7, #16] 8015b38: 2100 movs r1, #0 8015b3a: 68f8 ldr r0, [r7, #12] 8015b3c: f7ff fd58 bl 80155f0 8015b40: 6078 str r0, [r7, #4] configASSERT( xResult ); 8015b42: 687b ldr r3, [r7, #4] 8015b44: 2b00 cmp r3, #0 8015b46: d10b bne.n 8015b60 __asm volatile 8015b48: f04f 0350 mov.w r3, #80 @ 0x50 8015b4c: f383 8811 msr BASEPRI, r3 8015b50: f3bf 8f6f isb sy 8015b54: f3bf 8f4f dsb sy 8015b58: 603b str r3, [r7, #0] } 8015b5a: bf00 nop 8015b5c: bf00 nop 8015b5e: e7fd b.n 8015b5c while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 8015b60: 4b09 ldr r3, [pc, #36] @ (8015b88 ) 8015b62: 681b ldr r3, [r3, #0] 8015b64: 681b ldr r3, [r3, #0] 8015b66: 2b00 cmp r3, #0 8015b68: d1b0 bne.n 8015acc { mtCOVERAGE_TEST_MARKER(); } } pxTemp = pxCurrentTimerList; 8015b6a: 4b07 ldr r3, [pc, #28] @ (8015b88 ) 8015b6c: 681b ldr r3, [r3, #0] 8015b6e: 617b str r3, [r7, #20] pxCurrentTimerList = pxOverflowTimerList; 8015b70: 4b06 ldr r3, [pc, #24] @ (8015b8c ) 8015b72: 681b ldr r3, [r3, #0] 8015b74: 4a04 ldr r2, [pc, #16] @ (8015b88 ) 8015b76: 6013 str r3, [r2, #0] pxOverflowTimerList = pxTemp; 8015b78: 4a04 ldr r2, [pc, #16] @ (8015b8c ) 8015b7a: 697b ldr r3, [r7, #20] 8015b7c: 6013 str r3, [r2, #0] } 8015b7e: bf00 nop 8015b80: 3718 adds r7, #24 8015b82: 46bd mov sp, r7 8015b84: bd80 pop {r7, pc} 8015b86: bf00 nop 8015b88: 24002acc .word 0x24002acc 8015b8c: 24002ad0 .word 0x24002ad0 08015b90 : /*-----------------------------------------------------------*/ static void prvCheckForValidListAndQueue( void ) { 8015b90: b580 push {r7, lr} 8015b92: b082 sub sp, #8 8015b94: af02 add r7, sp, #8 /* Check that the list from which active timers are referenced, and the queue used to communicate with the timer service, have been initialised. */ taskENTER_CRITICAL(); 8015b96: f000 f9b7 bl 8015f08 { if( xTimerQueue == NULL ) 8015b9a: 4b15 ldr r3, [pc, #84] @ (8015bf0 ) 8015b9c: 681b ldr r3, [r3, #0] 8015b9e: 2b00 cmp r3, #0 8015ba0: d120 bne.n 8015be4 { vListInitialise( &xActiveTimerList1 ); 8015ba2: 4814 ldr r0, [pc, #80] @ (8015bf4 ) 8015ba4: f7fc ff84 bl 8012ab0 vListInitialise( &xActiveTimerList2 ); 8015ba8: 4813 ldr r0, [pc, #76] @ (8015bf8 ) 8015baa: f7fc ff81 bl 8012ab0 pxCurrentTimerList = &xActiveTimerList1; 8015bae: 4b13 ldr r3, [pc, #76] @ (8015bfc ) 8015bb0: 4a10 ldr r2, [pc, #64] @ (8015bf4 ) 8015bb2: 601a str r2, [r3, #0] pxOverflowTimerList = &xActiveTimerList2; 8015bb4: 4b12 ldr r3, [pc, #72] @ (8015c00 ) 8015bb6: 4a10 ldr r2, [pc, #64] @ (8015bf8 ) 8015bb8: 601a str r2, [r3, #0] /* The timer queue is allocated statically in case configSUPPORT_DYNAMIC_ALLOCATION is 0. */ static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 8015bba: 2300 movs r3, #0 8015bbc: 9300 str r3, [sp, #0] 8015bbe: 4b11 ldr r3, [pc, #68] @ (8015c04 ) 8015bc0: 4a11 ldr r2, [pc, #68] @ (8015c08 ) 8015bc2: 2110 movs r1, #16 8015bc4: 200a movs r0, #10 8015bc6: f7fd f891 bl 8012cec 8015bca: 4603 mov r3, r0 8015bcc: 4a08 ldr r2, [pc, #32] @ (8015bf0 ) 8015bce: 6013 str r3, [r2, #0] } #endif #if ( configQUEUE_REGISTRY_SIZE > 0 ) { if( xTimerQueue != NULL ) 8015bd0: 4b07 ldr r3, [pc, #28] @ (8015bf0 ) 8015bd2: 681b ldr r3, [r3, #0] 8015bd4: 2b00 cmp r3, #0 8015bd6: d005 beq.n 8015be4 { vQueueAddToRegistry( xTimerQueue, "TmrQ" ); 8015bd8: 4b05 ldr r3, [pc, #20] @ (8015bf0 ) 8015bda: 681b ldr r3, [r3, #0] 8015bdc: 490b ldr r1, [pc, #44] @ (8015c0c ) 8015bde: 4618 mov r0, r3 8015be0: f7fd ff54 bl 8013a8c else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8015be4: f000 f9c2 bl 8015f6c } 8015be8: bf00 nop 8015bea: 46bd mov sp, r7 8015bec: bd80 pop {r7, pc} 8015bee: bf00 nop 8015bf0: 24002ad4 .word 0x24002ad4 8015bf4: 24002aa4 .word 0x24002aa4 8015bf8: 24002ab8 .word 0x24002ab8 8015bfc: 24002acc .word 0x24002acc 8015c00: 24002ad0 .word 0x24002ad0 8015c04: 24002b80 .word 0x24002b80 8015c08: 24002ae0 .word 0x24002ae0 8015c0c: 0801755c .word 0x0801755c 08015c10 : /*-----------------------------------------------------------*/ BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) { 8015c10: b580 push {r7, lr} 8015c12: b086 sub sp, #24 8015c14: af00 add r7, sp, #0 8015c16: 6078 str r0, [r7, #4] BaseType_t xReturn; Timer_t *pxTimer = xTimer; 8015c18: 687b ldr r3, [r7, #4] 8015c1a: 613b str r3, [r7, #16] configASSERT( xTimer ); 8015c1c: 687b ldr r3, [r7, #4] 8015c1e: 2b00 cmp r3, #0 8015c20: d10b bne.n 8015c3a __asm volatile 8015c22: f04f 0350 mov.w r3, #80 @ 0x50 8015c26: f383 8811 msr BASEPRI, r3 8015c2a: f3bf 8f6f isb sy 8015c2e: f3bf 8f4f dsb sy 8015c32: 60fb str r3, [r7, #12] } 8015c34: bf00 nop 8015c36: bf00 nop 8015c38: e7fd b.n 8015c36 /* Is the timer in the list of active timers? */ taskENTER_CRITICAL(); 8015c3a: f000 f965 bl 8015f08 { if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 ) 8015c3e: 693b ldr r3, [r7, #16] 8015c40: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8015c44: f003 0301 and.w r3, r3, #1 8015c48: 2b00 cmp r3, #0 8015c4a: d102 bne.n 8015c52 { xReturn = pdFALSE; 8015c4c: 2300 movs r3, #0 8015c4e: 617b str r3, [r7, #20] 8015c50: e001 b.n 8015c56 } else { xReturn = pdTRUE; 8015c52: 2301 movs r3, #1 8015c54: 617b str r3, [r7, #20] } } taskEXIT_CRITICAL(); 8015c56: f000 f989 bl 8015f6c return xReturn; 8015c5a: 697b ldr r3, [r7, #20] } /*lint !e818 Can't be pointer to const due to the typedef. */ 8015c5c: 4618 mov r0, r3 8015c5e: 3718 adds r7, #24 8015c60: 46bd mov sp, r7 8015c62: bd80 pop {r7, pc} 08015c64 : /*-----------------------------------------------------------*/ void *pvTimerGetTimerID( const TimerHandle_t xTimer ) { 8015c64: b580 push {r7, lr} 8015c66: b086 sub sp, #24 8015c68: af00 add r7, sp, #0 8015c6a: 6078 str r0, [r7, #4] Timer_t * const pxTimer = xTimer; 8015c6c: 687b ldr r3, [r7, #4] 8015c6e: 617b str r3, [r7, #20] void *pvReturn; configASSERT( xTimer ); 8015c70: 687b ldr r3, [r7, #4] 8015c72: 2b00 cmp r3, #0 8015c74: d10b bne.n 8015c8e __asm volatile 8015c76: f04f 0350 mov.w r3, #80 @ 0x50 8015c7a: f383 8811 msr BASEPRI, r3 8015c7e: f3bf 8f6f isb sy 8015c82: f3bf 8f4f dsb sy 8015c86: 60fb str r3, [r7, #12] } 8015c88: bf00 nop 8015c8a: bf00 nop 8015c8c: e7fd b.n 8015c8a taskENTER_CRITICAL(); 8015c8e: f000 f93b bl 8015f08 { pvReturn = pxTimer->pvTimerID; 8015c92: 697b ldr r3, [r7, #20] 8015c94: 69db ldr r3, [r3, #28] 8015c96: 613b str r3, [r7, #16] } taskEXIT_CRITICAL(); 8015c98: f000 f968 bl 8015f6c return pvReturn; 8015c9c: 693b ldr r3, [r7, #16] } 8015c9e: 4618 mov r0, r3 8015ca0: 3718 adds r7, #24 8015ca2: 46bd mov sp, r7 8015ca4: bd80 pop {r7, pc} ... 08015ca8 : /* * See header file for description. */ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) { 8015ca8: b480 push {r7} 8015caa: b085 sub sp, #20 8015cac: af00 add r7, sp, #0 8015cae: 60f8 str r0, [r7, #12] 8015cb0: 60b9 str r1, [r7, #8] 8015cb2: 607a str r2, [r7, #4] /* Simulate the stack frame as it would be created by a context switch interrupt. */ /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts, and to ensure alignment. */ pxTopOfStack--; 8015cb4: 68fb ldr r3, [r7, #12] 8015cb6: 3b04 subs r3, #4 8015cb8: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ 8015cba: 68fb ldr r3, [r7, #12] 8015cbc: f04f 7280 mov.w r2, #16777216 @ 0x1000000 8015cc0: 601a str r2, [r3, #0] pxTopOfStack--; 8015cc2: 68fb ldr r3, [r7, #12] 8015cc4: 3b04 subs r3, #4 8015cc6: 60fb str r3, [r7, #12] *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ 8015cc8: 68bb ldr r3, [r7, #8] 8015cca: f023 0201 bic.w r2, r3, #1 8015cce: 68fb ldr r3, [r7, #12] 8015cd0: 601a str r2, [r3, #0] pxTopOfStack--; 8015cd2: 68fb ldr r3, [r7, #12] 8015cd4: 3b04 subs r3, #4 8015cd6: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ 8015cd8: 4a0c ldr r2, [pc, #48] @ (8015d0c ) 8015cda: 68fb ldr r3, [r7, #12] 8015cdc: 601a str r2, [r3, #0] /* Save code space by skipping register initialisation. */ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ 8015cde: 68fb ldr r3, [r7, #12] 8015ce0: 3b14 subs r3, #20 8015ce2: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ 8015ce4: 687a ldr r2, [r7, #4] 8015ce6: 68fb ldr r3, [r7, #12] 8015ce8: 601a str r2, [r3, #0] /* A save method is being used that requires each task to maintain its own exec return value. */ pxTopOfStack--; 8015cea: 68fb ldr r3, [r7, #12] 8015cec: 3b04 subs r3, #4 8015cee: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_EXC_RETURN; 8015cf0: 68fb ldr r3, [r7, #12] 8015cf2: f06f 0202 mvn.w r2, #2 8015cf6: 601a str r2, [r3, #0] pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ 8015cf8: 68fb ldr r3, [r7, #12] 8015cfa: 3b20 subs r3, #32 8015cfc: 60fb str r3, [r7, #12] return pxTopOfStack; 8015cfe: 68fb ldr r3, [r7, #12] } 8015d00: 4618 mov r0, r3 8015d02: 3714 adds r7, #20 8015d04: 46bd mov sp, r7 8015d06: f85d 7b04 ldr.w r7, [sp], #4 8015d0a: 4770 bx lr 8015d0c: 08015d11 .word 0x08015d11 08015d10 : /*-----------------------------------------------------------*/ static void prvTaskExitError( void ) { 8015d10: b480 push {r7} 8015d12: b085 sub sp, #20 8015d14: af00 add r7, sp, #0 volatile uint32_t ulDummy = 0; 8015d16: 2300 movs r3, #0 8015d18: 607b str r3, [r7, #4] its caller as there is nothing to return to. If a task wants to exit it should instead call vTaskDelete( NULL ). Artificially force an assert() to be triggered if configASSERT() is defined, then stop here so application writers can catch the error. */ configASSERT( uxCriticalNesting == ~0UL ); 8015d1a: 4b13 ldr r3, [pc, #76] @ (8015d68 ) 8015d1c: 681b ldr r3, [r3, #0] 8015d1e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015d22: d00b beq.n 8015d3c __asm volatile 8015d24: f04f 0350 mov.w r3, #80 @ 0x50 8015d28: f383 8811 msr BASEPRI, r3 8015d2c: f3bf 8f6f isb sy 8015d30: f3bf 8f4f dsb sy 8015d34: 60fb str r3, [r7, #12] } 8015d36: bf00 nop 8015d38: bf00 nop 8015d3a: e7fd b.n 8015d38 __asm volatile 8015d3c: f04f 0350 mov.w r3, #80 @ 0x50 8015d40: f383 8811 msr BASEPRI, r3 8015d44: f3bf 8f6f isb sy 8015d48: f3bf 8f4f dsb sy 8015d4c: 60bb str r3, [r7, #8] } 8015d4e: bf00 nop portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) 8015d50: bf00 nop 8015d52: 687b ldr r3, [r7, #4] 8015d54: 2b00 cmp r3, #0 8015d56: d0fc beq.n 8015d52 about code appearing after this function is called - making ulDummy volatile makes the compiler think the function could return and therefore not output an 'unreachable code' warning for code that appears after it. */ } } 8015d58: bf00 nop 8015d5a: bf00 nop 8015d5c: 3714 adds r7, #20 8015d5e: 46bd mov sp, r7 8015d60: f85d 7b04 ldr.w r7, [sp], #4 8015d64: 4770 bx lr 8015d66: bf00 nop 8015d68: 24000044 .word 0x24000044 8015d6c: 00000000 .word 0x00000000 08015d70 : /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( 8015d70: 4b07 ldr r3, [pc, #28] @ (8015d90 ) 8015d72: 6819 ldr r1, [r3, #0] 8015d74: 6808 ldr r0, [r1, #0] 8015d76: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8015d7a: f380 8809 msr PSP, r0 8015d7e: f3bf 8f6f isb sy 8015d82: f04f 0000 mov.w r0, #0 8015d86: f380 8811 msr BASEPRI, r0 8015d8a: 4770 bx lr 8015d8c: f3af 8000 nop.w 08015d90 : 8015d90: 240025a4 .word 0x240025a4 " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } 8015d94: bf00 nop 8015d96: bf00 nop 08015d98 : { /* Start the first task. This also clears the bit that indicates the FPU is in use in case the FPU was used before the scheduler was started - which would otherwise result in the unnecessary leaving of space in the SVC stack for lazy saving of FPU registers. */ __asm volatile( 8015d98: 4808 ldr r0, [pc, #32] @ (8015dbc ) 8015d9a: 6800 ldr r0, [r0, #0] 8015d9c: 6800 ldr r0, [r0, #0] 8015d9e: f380 8808 msr MSP, r0 8015da2: f04f 0000 mov.w r0, #0 8015da6: f380 8814 msr CONTROL, r0 8015daa: b662 cpsie i 8015dac: b661 cpsie f 8015dae: f3bf 8f4f dsb sy 8015db2: f3bf 8f6f isb sy 8015db6: df00 svc 0 8015db8: bf00 nop " dsb \n" " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n" ); } 8015dba: bf00 nop 8015dbc: e000ed08 .word 0xe000ed08 08015dc0 : /* * See header file for description. */ BaseType_t xPortStartScheduler( void ) { 8015dc0: b580 push {r7, lr} 8015dc2: b086 sub sp, #24 8015dc4: af00 add r7, sp, #0 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); /* This port can be used on all revisions of the Cortex-M7 core other than the r0p1 parts. r0p1 parts should use the port from the /source/portable/GCC/ARM_CM7/r0p1 directory. */ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); 8015dc6: 4b47 ldr r3, [pc, #284] @ (8015ee4 ) 8015dc8: 681b ldr r3, [r3, #0] 8015dca: 4a47 ldr r2, [pc, #284] @ (8015ee8 ) 8015dcc: 4293 cmp r3, r2 8015dce: d10b bne.n 8015de8 __asm volatile 8015dd0: f04f 0350 mov.w r3, #80 @ 0x50 8015dd4: f383 8811 msr BASEPRI, r3 8015dd8: f3bf 8f6f isb sy 8015ddc: f3bf 8f4f dsb sy 8015de0: 613b str r3, [r7, #16] } 8015de2: bf00 nop 8015de4: bf00 nop 8015de6: e7fd b.n 8015de4 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); 8015de8: 4b3e ldr r3, [pc, #248] @ (8015ee4 ) 8015dea: 681b ldr r3, [r3, #0] 8015dec: 4a3f ldr r2, [pc, #252] @ (8015eec ) 8015dee: 4293 cmp r3, r2 8015df0: d10b bne.n 8015e0a __asm volatile 8015df2: f04f 0350 mov.w r3, #80 @ 0x50 8015df6: f383 8811 msr BASEPRI, r3 8015dfa: f3bf 8f6f isb sy 8015dfe: f3bf 8f4f dsb sy 8015e02: 60fb str r3, [r7, #12] } 8015e04: bf00 nop 8015e06: bf00 nop 8015e08: e7fd b.n 8015e06 #if( configASSERT_DEFINED == 1 ) { volatile uint32_t ulOriginalPriority; volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); 8015e0a: 4b39 ldr r3, [pc, #228] @ (8015ef0 ) 8015e0c: 617b str r3, [r7, #20] functions can be called. ISR safe functions are those that end in "FromISR". FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. Save the interrupt priority value that is about to be clobbered. */ ulOriginalPriority = *pucFirstUserPriorityRegister; 8015e0e: 697b ldr r3, [r7, #20] 8015e10: 781b ldrb r3, [r3, #0] 8015e12: b2db uxtb r3, r3 8015e14: 607b str r3, [r7, #4] /* Determine the number of priority bits available. First write to all possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; 8015e16: 697b ldr r3, [r7, #20] 8015e18: 22ff movs r2, #255 @ 0xff 8015e1a: 701a strb r2, [r3, #0] /* Read the value back to see how many bits stuck. */ ucMaxPriorityValue = *pucFirstUserPriorityRegister; 8015e1c: 697b ldr r3, [r7, #20] 8015e1e: 781b ldrb r3, [r3, #0] 8015e20: b2db uxtb r3, r3 8015e22: 70fb strb r3, [r7, #3] /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; 8015e24: 78fb ldrb r3, [r7, #3] 8015e26: b2db uxtb r3, r3 8015e28: f003 0350 and.w r3, r3, #80 @ 0x50 8015e2c: b2da uxtb r2, r3 8015e2e: 4b31 ldr r3, [pc, #196] @ (8015ef4 ) 8015e30: 701a strb r2, [r3, #0] /* Calculate the maximum acceptable priority group value for the number of bits read back. */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; 8015e32: 4b31 ldr r3, [pc, #196] @ (8015ef8 ) 8015e34: 2207 movs r2, #7 8015e36: 601a str r2, [r3, #0] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 8015e38: e009 b.n 8015e4e { ulMaxPRIGROUPValue--; 8015e3a: 4b2f ldr r3, [pc, #188] @ (8015ef8 ) 8015e3c: 681b ldr r3, [r3, #0] 8015e3e: 3b01 subs r3, #1 8015e40: 4a2d ldr r2, [pc, #180] @ (8015ef8 ) 8015e42: 6013 str r3, [r2, #0] ucMaxPriorityValue <<= ( uint8_t ) 0x01; 8015e44: 78fb ldrb r3, [r7, #3] 8015e46: b2db uxtb r3, r3 8015e48: 005b lsls r3, r3, #1 8015e4a: b2db uxtb r3, r3 8015e4c: 70fb strb r3, [r7, #3] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 8015e4e: 78fb ldrb r3, [r7, #3] 8015e50: b2db uxtb r3, r3 8015e52: f003 0380 and.w r3, r3, #128 @ 0x80 8015e56: 2b80 cmp r3, #128 @ 0x80 8015e58: d0ef beq.n 8015e3a #ifdef configPRIO_BITS { /* Check the FreeRTOS configuration that defines the number of priority bits matches the number of priority bits actually queried from the hardware. */ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); 8015e5a: 4b27 ldr r3, [pc, #156] @ (8015ef8 ) 8015e5c: 681b ldr r3, [r3, #0] 8015e5e: f1c3 0307 rsb r3, r3, #7 8015e62: 2b04 cmp r3, #4 8015e64: d00b beq.n 8015e7e __asm volatile 8015e66: f04f 0350 mov.w r3, #80 @ 0x50 8015e6a: f383 8811 msr BASEPRI, r3 8015e6e: f3bf 8f6f isb sy 8015e72: f3bf 8f4f dsb sy 8015e76: 60bb str r3, [r7, #8] } 8015e78: bf00 nop 8015e7a: bf00 nop 8015e7c: e7fd b.n 8015e7a } #endif /* Shift the priority group value back to its position within the AIRCR register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; 8015e7e: 4b1e ldr r3, [pc, #120] @ (8015ef8 ) 8015e80: 681b ldr r3, [r3, #0] 8015e82: 021b lsls r3, r3, #8 8015e84: 4a1c ldr r2, [pc, #112] @ (8015ef8 ) 8015e86: 6013 str r3, [r2, #0] ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; 8015e88: 4b1b ldr r3, [pc, #108] @ (8015ef8 ) 8015e8a: 681b ldr r3, [r3, #0] 8015e8c: f403 63e0 and.w r3, r3, #1792 @ 0x700 8015e90: 4a19 ldr r2, [pc, #100] @ (8015ef8 ) 8015e92: 6013 str r3, [r2, #0] /* Restore the clobbered interrupt priority register to its original value. */ *pucFirstUserPriorityRegister = ulOriginalPriority; 8015e94: 687b ldr r3, [r7, #4] 8015e96: b2da uxtb r2, r3 8015e98: 697b ldr r3, [r7, #20] 8015e9a: 701a strb r2, [r3, #0] } #endif /* conifgASSERT_DEFINED */ /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; 8015e9c: 4b17 ldr r3, [pc, #92] @ (8015efc ) 8015e9e: 681b ldr r3, [r3, #0] 8015ea0: 4a16 ldr r2, [pc, #88] @ (8015efc ) 8015ea2: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8015ea6: 6013 str r3, [r2, #0] portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; 8015ea8: 4b14 ldr r3, [pc, #80] @ (8015efc ) 8015eaa: 681b ldr r3, [r3, #0] 8015eac: 4a13 ldr r2, [pc, #76] @ (8015efc ) 8015eae: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000 8015eb2: 6013 str r3, [r2, #0] /* Start the timer that generates the tick ISR. Interrupts are disabled here already. */ vPortSetupTimerInterrupt(); 8015eb4: f000 f8da bl 801606c /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; 8015eb8: 4b11 ldr r3, [pc, #68] @ (8015f00 ) 8015eba: 2200 movs r2, #0 8015ebc: 601a str r2, [r3, #0] /* Ensure the VFP is enabled - it should be anyway. */ vPortEnableVFP(); 8015ebe: f000 f8f9 bl 80160b4 /* Lazy save always. */ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; 8015ec2: 4b10 ldr r3, [pc, #64] @ (8015f04 ) 8015ec4: 681b ldr r3, [r3, #0] 8015ec6: 4a0f ldr r2, [pc, #60] @ (8015f04 ) 8015ec8: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000 8015ecc: 6013 str r3, [r2, #0] /* Start the first task. */ prvPortStartFirstTask(); 8015ece: f7ff ff63 bl 8015d98 exit error function to prevent compiler warnings about a static function not being called in the case that the application writer overrides this functionality by defining configTASK_RETURN_ADDRESS. Call vTaskSwitchContext() so link time optimisation does not remove the symbol. */ vTaskSwitchContext(); 8015ed2: f7fe fbd1 bl 8014678 prvTaskExitError(); 8015ed6: f7ff ff1b bl 8015d10 /* Should not get here! */ return 0; 8015eda: 2300 movs r3, #0 } 8015edc: 4618 mov r0, r3 8015ede: 3718 adds r7, #24 8015ee0: 46bd mov sp, r7 8015ee2: bd80 pop {r7, pc} 8015ee4: e000ed00 .word 0xe000ed00 8015ee8: 410fc271 .word 0x410fc271 8015eec: 410fc270 .word 0x410fc270 8015ef0: e000e400 .word 0xe000e400 8015ef4: 24002bd0 .word 0x24002bd0 8015ef8: 24002bd4 .word 0x24002bd4 8015efc: e000ed20 .word 0xe000ed20 8015f00: 24000044 .word 0x24000044 8015f04: e000ef34 .word 0xe000ef34 08015f08 : configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) { 8015f08: b480 push {r7} 8015f0a: b083 sub sp, #12 8015f0c: af00 add r7, sp, #0 __asm volatile 8015f0e: f04f 0350 mov.w r3, #80 @ 0x50 8015f12: f383 8811 msr BASEPRI, r3 8015f16: f3bf 8f6f isb sy 8015f1a: f3bf 8f4f dsb sy 8015f1e: 607b str r3, [r7, #4] } 8015f20: bf00 nop portDISABLE_INTERRUPTS(); uxCriticalNesting++; 8015f22: 4b10 ldr r3, [pc, #64] @ (8015f64 ) 8015f24: 681b ldr r3, [r3, #0] 8015f26: 3301 adds r3, #1 8015f28: 4a0e ldr r2, [pc, #56] @ (8015f64 ) 8015f2a: 6013 str r3, [r2, #0] /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if( uxCriticalNesting == 1 ) 8015f2c: 4b0d ldr r3, [pc, #52] @ (8015f64 ) 8015f2e: 681b ldr r3, [r3, #0] 8015f30: 2b01 cmp r3, #1 8015f32: d110 bne.n 8015f56 { configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); 8015f34: 4b0c ldr r3, [pc, #48] @ (8015f68 ) 8015f36: 681b ldr r3, [r3, #0] 8015f38: b2db uxtb r3, r3 8015f3a: 2b00 cmp r3, #0 8015f3c: d00b beq.n 8015f56 __asm volatile 8015f3e: f04f 0350 mov.w r3, #80 @ 0x50 8015f42: f383 8811 msr BASEPRI, r3 8015f46: f3bf 8f6f isb sy 8015f4a: f3bf 8f4f dsb sy 8015f4e: 603b str r3, [r7, #0] } 8015f50: bf00 nop 8015f52: bf00 nop 8015f54: e7fd b.n 8015f52 } } 8015f56: bf00 nop 8015f58: 370c adds r7, #12 8015f5a: 46bd mov sp, r7 8015f5c: f85d 7b04 ldr.w r7, [sp], #4 8015f60: 4770 bx lr 8015f62: bf00 nop 8015f64: 24000044 .word 0x24000044 8015f68: e000ed04 .word 0xe000ed04 08015f6c : /*-----------------------------------------------------------*/ void vPortExitCritical( void ) { 8015f6c: b480 push {r7} 8015f6e: b083 sub sp, #12 8015f70: af00 add r7, sp, #0 configASSERT( uxCriticalNesting ); 8015f72: 4b12 ldr r3, [pc, #72] @ (8015fbc ) 8015f74: 681b ldr r3, [r3, #0] 8015f76: 2b00 cmp r3, #0 8015f78: d10b bne.n 8015f92 __asm volatile 8015f7a: f04f 0350 mov.w r3, #80 @ 0x50 8015f7e: f383 8811 msr BASEPRI, r3 8015f82: f3bf 8f6f isb sy 8015f86: f3bf 8f4f dsb sy 8015f8a: 607b str r3, [r7, #4] } 8015f8c: bf00 nop 8015f8e: bf00 nop 8015f90: e7fd b.n 8015f8e uxCriticalNesting--; 8015f92: 4b0a ldr r3, [pc, #40] @ (8015fbc ) 8015f94: 681b ldr r3, [r3, #0] 8015f96: 3b01 subs r3, #1 8015f98: 4a08 ldr r2, [pc, #32] @ (8015fbc ) 8015f9a: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) 8015f9c: 4b07 ldr r3, [pc, #28] @ (8015fbc ) 8015f9e: 681b ldr r3, [r3, #0] 8015fa0: 2b00 cmp r3, #0 8015fa2: d105 bne.n 8015fb0 8015fa4: 2300 movs r3, #0 8015fa6: 603b str r3, [r7, #0] __asm volatile 8015fa8: 683b ldr r3, [r7, #0] 8015faa: f383 8811 msr BASEPRI, r3 } 8015fae: bf00 nop { portENABLE_INTERRUPTS(); } } 8015fb0: bf00 nop 8015fb2: 370c adds r7, #12 8015fb4: 46bd mov sp, r7 8015fb6: f85d 7b04 ldr.w r7, [sp], #4 8015fba: 4770 bx lr 8015fbc: 24000044 .word 0x24000044 08015fc0 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile 8015fc0: f3ef 8009 mrs r0, PSP 8015fc4: f3bf 8f6f isb sy 8015fc8: 4b15 ldr r3, [pc, #84] @ (8016020 ) 8015fca: 681a ldr r2, [r3, #0] 8015fcc: f01e 0f10 tst.w lr, #16 8015fd0: bf08 it eq 8015fd2: ed20 8a10 vstmdbeq r0!, {s16-s31} 8015fd6: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8015fda: 6010 str r0, [r2, #0] 8015fdc: e92d 0009 stmdb sp!, {r0, r3} 8015fe0: f04f 0050 mov.w r0, #80 @ 0x50 8015fe4: f380 8811 msr BASEPRI, r0 8015fe8: f3bf 8f4f dsb sy 8015fec: f3bf 8f6f isb sy 8015ff0: f7fe fb42 bl 8014678 8015ff4: f04f 0000 mov.w r0, #0 8015ff8: f380 8811 msr BASEPRI, r0 8015ffc: bc09 pop {r0, r3} 8015ffe: 6819 ldr r1, [r3, #0] 8016000: 6808 ldr r0, [r1, #0] 8016002: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8016006: f01e 0f10 tst.w lr, #16 801600a: bf08 it eq 801600c: ecb0 8a10 vldmiaeq r0!, {s16-s31} 8016010: f380 8809 msr PSP, r0 8016014: f3bf 8f6f isb sy 8016018: 4770 bx lr 801601a: bf00 nop 801601c: f3af 8000 nop.w 08016020 : 8016020: 240025a4 .word 0x240025a4 " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ); } 8016024: bf00 nop 8016026: bf00 nop 08016028 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { 8016028: b580 push {r7, lr} 801602a: b082 sub sp, #8 801602c: af00 add r7, sp, #0 __asm volatile 801602e: f04f 0350 mov.w r3, #80 @ 0x50 8016032: f383 8811 msr BASEPRI, r3 8016036: f3bf 8f6f isb sy 801603a: f3bf 8f4f dsb sy 801603e: 607b str r3, [r7, #4] } 8016040: bf00 nop save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) 8016042: f7fe fa5f bl 8014504 8016046: 4603 mov r3, r0 8016048: 2b00 cmp r3, #0 801604a: d003 beq.n 8016054 { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; 801604c: 4b06 ldr r3, [pc, #24] @ (8016068 ) 801604e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016052: 601a str r2, [r3, #0] 8016054: 2300 movs r3, #0 8016056: 603b str r3, [r7, #0] __asm volatile 8016058: 683b ldr r3, [r7, #0] 801605a: f383 8811 msr BASEPRI, r3 } 801605e: bf00 nop } } portENABLE_INTERRUPTS(); } 8016060: bf00 nop 8016062: 3708 adds r7, #8 8016064: 46bd mov sp, r7 8016066: bd80 pop {r7, pc} 8016068: e000ed04 .word 0xe000ed04 0801606c : /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) { 801606c: b480 push {r7} 801606e: af00 add r7, sp, #0 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and clear the SysTick. */ portNVIC_SYSTICK_CTRL_REG = 0UL; 8016070: 4b0b ldr r3, [pc, #44] @ (80160a0 ) 8016072: 2200 movs r2, #0 8016074: 601a str r2, [r3, #0] portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; 8016076: 4b0b ldr r3, [pc, #44] @ (80160a4 ) 8016078: 2200 movs r2, #0 801607a: 601a str r2, [r3, #0] /* Configure SysTick to interrupt at the requested rate. */ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; 801607c: 4b0a ldr r3, [pc, #40] @ (80160a8 ) 801607e: 681b ldr r3, [r3, #0] 8016080: 4a0a ldr r2, [pc, #40] @ (80160ac ) 8016082: fba2 2303 umull r2, r3, r2, r3 8016086: 099b lsrs r3, r3, #6 8016088: 4a09 ldr r2, [pc, #36] @ (80160b0 ) 801608a: 3b01 subs r3, #1 801608c: 6013 str r3, [r2, #0] portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); 801608e: 4b04 ldr r3, [pc, #16] @ (80160a0 ) 8016090: 2207 movs r2, #7 8016092: 601a str r2, [r3, #0] } 8016094: bf00 nop 8016096: 46bd mov sp, r7 8016098: f85d 7b04 ldr.w r7, [sp], #4 801609c: 4770 bx lr 801609e: bf00 nop 80160a0: e000e010 .word 0xe000e010 80160a4: e000e018 .word 0xe000e018 80160a8: 24000034 .word 0x24000034 80160ac: 10624dd3 .word 0x10624dd3 80160b0: e000e014 .word 0xe000e014 080160b4 : /*-----------------------------------------------------------*/ /* This is a naked function. */ static void vPortEnableVFP( void ) { __asm volatile 80160b4: f8df 000c ldr.w r0, [pc, #12] @ 80160c4 80160b8: 6801 ldr r1, [r0, #0] 80160ba: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 80160be: 6001 str r1, [r0, #0] 80160c0: 4770 bx lr " \n" " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ " str r1, [r0] \n" " bx r14 " ); } 80160c2: bf00 nop 80160c4: e000ed88 .word 0xe000ed88 080160c8 : /*-----------------------------------------------------------*/ #if( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { 80160c8: b480 push {r7} 80160ca: b085 sub sp, #20 80160cc: af00 add r7, sp, #0 uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); 80160ce: f3ef 8305 mrs r3, IPSR 80160d2: 60fb str r3, [r7, #12] /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) 80160d4: 68fb ldr r3, [r7, #12] 80160d6: 2b0f cmp r3, #15 80160d8: d915 bls.n 8016106 { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; 80160da: 4a18 ldr r2, [pc, #96] @ (801613c ) 80160dc: 68fb ldr r3, [r7, #12] 80160de: 4413 add r3, r2 80160e0: 781b ldrb r3, [r3, #0] 80160e2: 72fb strb r3, [r7, #11] interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); 80160e4: 4b16 ldr r3, [pc, #88] @ (8016140 ) 80160e6: 781b ldrb r3, [r3, #0] 80160e8: 7afa ldrb r2, [r7, #11] 80160ea: 429a cmp r2, r3 80160ec: d20b bcs.n 8016106 __asm volatile 80160ee: f04f 0350 mov.w r3, #80 @ 0x50 80160f2: f383 8811 msr BASEPRI, r3 80160f6: f3bf 8f6f isb sy 80160fa: f3bf 8f4f dsb sy 80160fe: 607b str r3, [r7, #4] } 8016100: bf00 nop 8016102: bf00 nop 8016104: e7fd b.n 8016102 configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); 8016106: 4b0f ldr r3, [pc, #60] @ (8016144 ) 8016108: 681b ldr r3, [r3, #0] 801610a: f403 62e0 and.w r2, r3, #1792 @ 0x700 801610e: 4b0e ldr r3, [pc, #56] @ (8016148 ) 8016110: 681b ldr r3, [r3, #0] 8016112: 429a cmp r2, r3 8016114: d90b bls.n 801612e __asm volatile 8016116: f04f 0350 mov.w r3, #80 @ 0x50 801611a: f383 8811 msr BASEPRI, r3 801611e: f3bf 8f6f isb sy 8016122: f3bf 8f4f dsb sy 8016126: 603b str r3, [r7, #0] } 8016128: bf00 nop 801612a: bf00 nop 801612c: e7fd b.n 801612a } 801612e: bf00 nop 8016130: 3714 adds r7, #20 8016132: 46bd mov sp, r7 8016134: f85d 7b04 ldr.w r7, [sp], #4 8016138: 4770 bx lr 801613a: bf00 nop 801613c: e000e3f0 .word 0xe000e3f0 8016140: 24002bd0 .word 0x24002bd0 8016144: e000ed0c .word 0xe000ed0c 8016148: 24002bd4 .word 0x24002bd4 0801614c : static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ void *pvPortMalloc( size_t xWantedSize ) { 801614c: b580 push {r7, lr} 801614e: b08a sub sp, #40 @ 0x28 8016150: af00 add r7, sp, #0 8016152: 6078 str r0, [r7, #4] BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; void *pvReturn = NULL; 8016154: 2300 movs r3, #0 8016156: 61fb str r3, [r7, #28] vTaskSuspendAll(); 8016158: f7fe f918 bl 801438c { /* If this is the first call to malloc then the heap will require initialisation to setup the list of free blocks. */ if( pxEnd == NULL ) 801615c: 4b5c ldr r3, [pc, #368] @ (80162d0 ) 801615e: 681b ldr r3, [r3, #0] 8016160: 2b00 cmp r3, #0 8016162: d101 bne.n 8016168 { prvHeapInit(); 8016164: f000 f924 bl 80163b0 /* Check the requested block size is not so large that the top bit is set. The top bit of the block size member of the BlockLink_t structure is used to determine who owns the block - the application or the kernel, so it must be free. */ if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) 8016168: 4b5a ldr r3, [pc, #360] @ (80162d4 ) 801616a: 681a ldr r2, [r3, #0] 801616c: 687b ldr r3, [r7, #4] 801616e: 4013 ands r3, r2 8016170: 2b00 cmp r3, #0 8016172: f040 8095 bne.w 80162a0 { /* The wanted size is increased so it can contain a BlockLink_t structure in addition to the requested amount of bytes. */ if( xWantedSize > 0 ) 8016176: 687b ldr r3, [r7, #4] 8016178: 2b00 cmp r3, #0 801617a: d01e beq.n 80161ba { xWantedSize += xHeapStructSize; 801617c: 2208 movs r2, #8 801617e: 687b ldr r3, [r7, #4] 8016180: 4413 add r3, r2 8016182: 607b str r3, [r7, #4] /* Ensure that blocks are always aligned to the required number of bytes. */ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) 8016184: 687b ldr r3, [r7, #4] 8016186: f003 0307 and.w r3, r3, #7 801618a: 2b00 cmp r3, #0 801618c: d015 beq.n 80161ba { /* Byte alignment required. */ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); 801618e: 687b ldr r3, [r7, #4] 8016190: f023 0307 bic.w r3, r3, #7 8016194: 3308 adds r3, #8 8016196: 607b str r3, [r7, #4] configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); 8016198: 687b ldr r3, [r7, #4] 801619a: f003 0307 and.w r3, r3, #7 801619e: 2b00 cmp r3, #0 80161a0: d00b beq.n 80161ba __asm volatile 80161a2: f04f 0350 mov.w r3, #80 @ 0x50 80161a6: f383 8811 msr BASEPRI, r3 80161aa: f3bf 8f6f isb sy 80161ae: f3bf 8f4f dsb sy 80161b2: 617b str r3, [r7, #20] } 80161b4: bf00 nop 80161b6: bf00 nop 80161b8: e7fd b.n 80161b6 else { mtCOVERAGE_TEST_MARKER(); } if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) 80161ba: 687b ldr r3, [r7, #4] 80161bc: 2b00 cmp r3, #0 80161be: d06f beq.n 80162a0 80161c0: 4b45 ldr r3, [pc, #276] @ (80162d8 ) 80161c2: 681b ldr r3, [r3, #0] 80161c4: 687a ldr r2, [r7, #4] 80161c6: 429a cmp r2, r3 80161c8: d86a bhi.n 80162a0 { /* Traverse the list from the start (lowest address) block until one of adequate size is found. */ pxPreviousBlock = &xStart; 80161ca: 4b44 ldr r3, [pc, #272] @ (80162dc ) 80161cc: 623b str r3, [r7, #32] pxBlock = xStart.pxNextFreeBlock; 80161ce: 4b43 ldr r3, [pc, #268] @ (80162dc ) 80161d0: 681b ldr r3, [r3, #0] 80161d2: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 80161d4: e004 b.n 80161e0 { pxPreviousBlock = pxBlock; 80161d6: 6a7b ldr r3, [r7, #36] @ 0x24 80161d8: 623b str r3, [r7, #32] pxBlock = pxBlock->pxNextFreeBlock; 80161da: 6a7b ldr r3, [r7, #36] @ 0x24 80161dc: 681b ldr r3, [r3, #0] 80161de: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 80161e0: 6a7b ldr r3, [r7, #36] @ 0x24 80161e2: 685b ldr r3, [r3, #4] 80161e4: 687a ldr r2, [r7, #4] 80161e6: 429a cmp r2, r3 80161e8: d903 bls.n 80161f2 80161ea: 6a7b ldr r3, [r7, #36] @ 0x24 80161ec: 681b ldr r3, [r3, #0] 80161ee: 2b00 cmp r3, #0 80161f0: d1f1 bne.n 80161d6 } /* If the end marker was reached then a block of adequate size was not found. */ if( pxBlock != pxEnd ) 80161f2: 4b37 ldr r3, [pc, #220] @ (80162d0 ) 80161f4: 681b ldr r3, [r3, #0] 80161f6: 6a7a ldr r2, [r7, #36] @ 0x24 80161f8: 429a cmp r2, r3 80161fa: d051 beq.n 80162a0 { /* Return the memory space pointed to - jumping over the BlockLink_t structure at its start. */ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); 80161fc: 6a3b ldr r3, [r7, #32] 80161fe: 681b ldr r3, [r3, #0] 8016200: 2208 movs r2, #8 8016202: 4413 add r3, r2 8016204: 61fb str r3, [r7, #28] /* This block is being returned for use so must be taken out of the list of free blocks. */ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; 8016206: 6a7b ldr r3, [r7, #36] @ 0x24 8016208: 681a ldr r2, [r3, #0] 801620a: 6a3b ldr r3, [r7, #32] 801620c: 601a str r2, [r3, #0] /* If the block is larger than required it can be split into two. */ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) 801620e: 6a7b ldr r3, [r7, #36] @ 0x24 8016210: 685a ldr r2, [r3, #4] 8016212: 687b ldr r3, [r7, #4] 8016214: 1ad2 subs r2, r2, r3 8016216: 2308 movs r3, #8 8016218: 005b lsls r3, r3, #1 801621a: 429a cmp r2, r3 801621c: d920 bls.n 8016260 { /* This block is to be split into two. Create a new block following the number of bytes requested. The void cast is used to prevent byte alignment warnings from the compiler. */ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); 801621e: 6a7a ldr r2, [r7, #36] @ 0x24 8016220: 687b ldr r3, [r7, #4] 8016222: 4413 add r3, r2 8016224: 61bb str r3, [r7, #24] configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); 8016226: 69bb ldr r3, [r7, #24] 8016228: f003 0307 and.w r3, r3, #7 801622c: 2b00 cmp r3, #0 801622e: d00b beq.n 8016248 __asm volatile 8016230: f04f 0350 mov.w r3, #80 @ 0x50 8016234: f383 8811 msr BASEPRI, r3 8016238: f3bf 8f6f isb sy 801623c: f3bf 8f4f dsb sy 8016240: 613b str r3, [r7, #16] } 8016242: bf00 nop 8016244: bf00 nop 8016246: e7fd b.n 8016244 /* Calculate the sizes of two blocks split from the single block. */ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; 8016248: 6a7b ldr r3, [r7, #36] @ 0x24 801624a: 685a ldr r2, [r3, #4] 801624c: 687b ldr r3, [r7, #4] 801624e: 1ad2 subs r2, r2, r3 8016250: 69bb ldr r3, [r7, #24] 8016252: 605a str r2, [r3, #4] pxBlock->xBlockSize = xWantedSize; 8016254: 6a7b ldr r3, [r7, #36] @ 0x24 8016256: 687a ldr r2, [r7, #4] 8016258: 605a str r2, [r3, #4] /* Insert the new block into the list of free blocks. */ prvInsertBlockIntoFreeList( pxNewBlockLink ); 801625a: 69b8 ldr r0, [r7, #24] 801625c: f000 f90a bl 8016474 else { mtCOVERAGE_TEST_MARKER(); } xFreeBytesRemaining -= pxBlock->xBlockSize; 8016260: 4b1d ldr r3, [pc, #116] @ (80162d8 ) 8016262: 681a ldr r2, [r3, #0] 8016264: 6a7b ldr r3, [r7, #36] @ 0x24 8016266: 685b ldr r3, [r3, #4] 8016268: 1ad3 subs r3, r2, r3 801626a: 4a1b ldr r2, [pc, #108] @ (80162d8 ) 801626c: 6013 str r3, [r2, #0] if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) 801626e: 4b1a ldr r3, [pc, #104] @ (80162d8 ) 8016270: 681a ldr r2, [r3, #0] 8016272: 4b1b ldr r3, [pc, #108] @ (80162e0 ) 8016274: 681b ldr r3, [r3, #0] 8016276: 429a cmp r2, r3 8016278: d203 bcs.n 8016282 { xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; 801627a: 4b17 ldr r3, [pc, #92] @ (80162d8 ) 801627c: 681b ldr r3, [r3, #0] 801627e: 4a18 ldr r2, [pc, #96] @ (80162e0 ) 8016280: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } /* The block is being returned - it is allocated and owned by the application and has no "next" block. */ pxBlock->xBlockSize |= xBlockAllocatedBit; 8016282: 6a7b ldr r3, [r7, #36] @ 0x24 8016284: 685a ldr r2, [r3, #4] 8016286: 4b13 ldr r3, [pc, #76] @ (80162d4 ) 8016288: 681b ldr r3, [r3, #0] 801628a: 431a orrs r2, r3 801628c: 6a7b ldr r3, [r7, #36] @ 0x24 801628e: 605a str r2, [r3, #4] pxBlock->pxNextFreeBlock = NULL; 8016290: 6a7b ldr r3, [r7, #36] @ 0x24 8016292: 2200 movs r2, #0 8016294: 601a str r2, [r3, #0] xNumberOfSuccessfulAllocations++; 8016296: 4b13 ldr r3, [pc, #76] @ (80162e4 ) 8016298: 681b ldr r3, [r3, #0] 801629a: 3301 adds r3, #1 801629c: 4a11 ldr r2, [pc, #68] @ (80162e4 ) 801629e: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } traceMALLOC( pvReturn, xWantedSize ); } ( void ) xTaskResumeAll(); 80162a0: f7fe f882 bl 80143a8 mtCOVERAGE_TEST_MARKER(); } } #endif configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); 80162a4: 69fb ldr r3, [r7, #28] 80162a6: f003 0307 and.w r3, r3, #7 80162aa: 2b00 cmp r3, #0 80162ac: d00b beq.n 80162c6 __asm volatile 80162ae: f04f 0350 mov.w r3, #80 @ 0x50 80162b2: f383 8811 msr BASEPRI, r3 80162b6: f3bf 8f6f isb sy 80162ba: f3bf 8f4f dsb sy 80162be: 60fb str r3, [r7, #12] } 80162c0: bf00 nop 80162c2: bf00 nop 80162c4: e7fd b.n 80162c2 return pvReturn; 80162c6: 69fb ldr r3, [r7, #28] } 80162c8: 4618 mov r0, r3 80162ca: 3728 adds r7, #40 @ 0x28 80162cc: 46bd mov sp, r7 80162ce: bd80 pop {r7, pc} 80162d0: 24012be0 .word 0x24012be0 80162d4: 24012bf4 .word 0x24012bf4 80162d8: 24012be4 .word 0x24012be4 80162dc: 24012bd8 .word 0x24012bd8 80162e0: 24012be8 .word 0x24012be8 80162e4: 24012bec .word 0x24012bec 080162e8 : /*-----------------------------------------------------------*/ void vPortFree( void *pv ) { 80162e8: b580 push {r7, lr} 80162ea: b086 sub sp, #24 80162ec: af00 add r7, sp, #0 80162ee: 6078 str r0, [r7, #4] uint8_t *puc = ( uint8_t * ) pv; 80162f0: 687b ldr r3, [r7, #4] 80162f2: 617b str r3, [r7, #20] BlockLink_t *pxLink; if( pv != NULL ) 80162f4: 687b ldr r3, [r7, #4] 80162f6: 2b00 cmp r3, #0 80162f8: d04f beq.n 801639a { /* The memory being freed will have an BlockLink_t structure immediately before it. */ puc -= xHeapStructSize; 80162fa: 2308 movs r3, #8 80162fc: 425b negs r3, r3 80162fe: 697a ldr r2, [r7, #20] 8016300: 4413 add r3, r2 8016302: 617b str r3, [r7, #20] /* This casting is to keep the compiler from issuing warnings. */ pxLink = ( void * ) puc; 8016304: 697b ldr r3, [r7, #20] 8016306: 613b str r3, [r7, #16] /* Check the block is actually allocated. */ configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); 8016308: 693b ldr r3, [r7, #16] 801630a: 685a ldr r2, [r3, #4] 801630c: 4b25 ldr r3, [pc, #148] @ (80163a4 ) 801630e: 681b ldr r3, [r3, #0] 8016310: 4013 ands r3, r2 8016312: 2b00 cmp r3, #0 8016314: d10b bne.n 801632e __asm volatile 8016316: f04f 0350 mov.w r3, #80 @ 0x50 801631a: f383 8811 msr BASEPRI, r3 801631e: f3bf 8f6f isb sy 8016322: f3bf 8f4f dsb sy 8016326: 60fb str r3, [r7, #12] } 8016328: bf00 nop 801632a: bf00 nop 801632c: e7fd b.n 801632a configASSERT( pxLink->pxNextFreeBlock == NULL ); 801632e: 693b ldr r3, [r7, #16] 8016330: 681b ldr r3, [r3, #0] 8016332: 2b00 cmp r3, #0 8016334: d00b beq.n 801634e __asm volatile 8016336: f04f 0350 mov.w r3, #80 @ 0x50 801633a: f383 8811 msr BASEPRI, r3 801633e: f3bf 8f6f isb sy 8016342: f3bf 8f4f dsb sy 8016346: 60bb str r3, [r7, #8] } 8016348: bf00 nop 801634a: bf00 nop 801634c: e7fd b.n 801634a if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) 801634e: 693b ldr r3, [r7, #16] 8016350: 685a ldr r2, [r3, #4] 8016352: 4b14 ldr r3, [pc, #80] @ (80163a4 ) 8016354: 681b ldr r3, [r3, #0] 8016356: 4013 ands r3, r2 8016358: 2b00 cmp r3, #0 801635a: d01e beq.n 801639a { if( pxLink->pxNextFreeBlock == NULL ) 801635c: 693b ldr r3, [r7, #16] 801635e: 681b ldr r3, [r3, #0] 8016360: 2b00 cmp r3, #0 8016362: d11a bne.n 801639a { /* The block is being returned to the heap - it is no longer allocated. */ pxLink->xBlockSize &= ~xBlockAllocatedBit; 8016364: 693b ldr r3, [r7, #16] 8016366: 685a ldr r2, [r3, #4] 8016368: 4b0e ldr r3, [pc, #56] @ (80163a4 ) 801636a: 681b ldr r3, [r3, #0] 801636c: 43db mvns r3, r3 801636e: 401a ands r2, r3 8016370: 693b ldr r3, [r7, #16] 8016372: 605a str r2, [r3, #4] vTaskSuspendAll(); 8016374: f7fe f80a bl 801438c { /* Add this block to the list of free blocks. */ xFreeBytesRemaining += pxLink->xBlockSize; 8016378: 693b ldr r3, [r7, #16] 801637a: 685a ldr r2, [r3, #4] 801637c: 4b0a ldr r3, [pc, #40] @ (80163a8 ) 801637e: 681b ldr r3, [r3, #0] 8016380: 4413 add r3, r2 8016382: 4a09 ldr r2, [pc, #36] @ (80163a8 ) 8016384: 6013 str r3, [r2, #0] traceFREE( pv, pxLink->xBlockSize ); prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); 8016386: 6938 ldr r0, [r7, #16] 8016388: f000 f874 bl 8016474 xNumberOfSuccessfulFrees++; 801638c: 4b07 ldr r3, [pc, #28] @ (80163ac ) 801638e: 681b ldr r3, [r3, #0] 8016390: 3301 adds r3, #1 8016392: 4a06 ldr r2, [pc, #24] @ (80163ac ) 8016394: 6013 str r3, [r2, #0] } ( void ) xTaskResumeAll(); 8016396: f7fe f807 bl 80143a8 else { mtCOVERAGE_TEST_MARKER(); } } } 801639a: bf00 nop 801639c: 3718 adds r7, #24 801639e: 46bd mov sp, r7 80163a0: bd80 pop {r7, pc} 80163a2: bf00 nop 80163a4: 24012bf4 .word 0x24012bf4 80163a8: 24012be4 .word 0x24012be4 80163ac: 24012bf0 .word 0x24012bf0 080163b0 : /* This just exists to keep the linker quiet. */ } /*-----------------------------------------------------------*/ static void prvHeapInit( void ) { 80163b0: b480 push {r7} 80163b2: b085 sub sp, #20 80163b4: af00 add r7, sp, #0 BlockLink_t *pxFirstFreeBlock; uint8_t *pucAlignedHeap; size_t uxAddress; size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; 80163b6: f44f 3380 mov.w r3, #65536 @ 0x10000 80163ba: 60bb str r3, [r7, #8] /* Ensure the heap starts on a correctly aligned boundary. */ uxAddress = ( size_t ) ucHeap; 80163bc: 4b27 ldr r3, [pc, #156] @ (801645c ) 80163be: 60fb str r3, [r7, #12] if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) 80163c0: 68fb ldr r3, [r7, #12] 80163c2: f003 0307 and.w r3, r3, #7 80163c6: 2b00 cmp r3, #0 80163c8: d00c beq.n 80163e4 { uxAddress += ( portBYTE_ALIGNMENT - 1 ); 80163ca: 68fb ldr r3, [r7, #12] 80163cc: 3307 adds r3, #7 80163ce: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 80163d0: 68fb ldr r3, [r7, #12] 80163d2: f023 0307 bic.w r3, r3, #7 80163d6: 60fb str r3, [r7, #12] xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; 80163d8: 68ba ldr r2, [r7, #8] 80163da: 68fb ldr r3, [r7, #12] 80163dc: 1ad3 subs r3, r2, r3 80163de: 4a1f ldr r2, [pc, #124] @ (801645c ) 80163e0: 4413 add r3, r2 80163e2: 60bb str r3, [r7, #8] } pucAlignedHeap = ( uint8_t * ) uxAddress; 80163e4: 68fb ldr r3, [r7, #12] 80163e6: 607b str r3, [r7, #4] /* xStart is used to hold a pointer to the first item in the list of free blocks. The void cast is used to prevent compiler warnings. */ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; 80163e8: 4a1d ldr r2, [pc, #116] @ (8016460 ) 80163ea: 687b ldr r3, [r7, #4] 80163ec: 6013 str r3, [r2, #0] xStart.xBlockSize = ( size_t ) 0; 80163ee: 4b1c ldr r3, [pc, #112] @ (8016460 ) 80163f0: 2200 movs r2, #0 80163f2: 605a str r2, [r3, #4] /* pxEnd is used to mark the end of the list of free blocks and is inserted at the end of the heap space. */ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; 80163f4: 687b ldr r3, [r7, #4] 80163f6: 68ba ldr r2, [r7, #8] 80163f8: 4413 add r3, r2 80163fa: 60fb str r3, [r7, #12] uxAddress -= xHeapStructSize; 80163fc: 2208 movs r2, #8 80163fe: 68fb ldr r3, [r7, #12] 8016400: 1a9b subs r3, r3, r2 8016402: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 8016404: 68fb ldr r3, [r7, #12] 8016406: f023 0307 bic.w r3, r3, #7 801640a: 60fb str r3, [r7, #12] pxEnd = ( void * ) uxAddress; 801640c: 68fb ldr r3, [r7, #12] 801640e: 4a15 ldr r2, [pc, #84] @ (8016464 ) 8016410: 6013 str r3, [r2, #0] pxEnd->xBlockSize = 0; 8016412: 4b14 ldr r3, [pc, #80] @ (8016464 ) 8016414: 681b ldr r3, [r3, #0] 8016416: 2200 movs r2, #0 8016418: 605a str r2, [r3, #4] pxEnd->pxNextFreeBlock = NULL; 801641a: 4b12 ldr r3, [pc, #72] @ (8016464 ) 801641c: 681b ldr r3, [r3, #0] 801641e: 2200 movs r2, #0 8016420: 601a str r2, [r3, #0] /* To start with there is a single free block that is sized to take up the entire heap space, minus the space taken by pxEnd. */ pxFirstFreeBlock = ( void * ) pucAlignedHeap; 8016422: 687b ldr r3, [r7, #4] 8016424: 603b str r3, [r7, #0] pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; 8016426: 683b ldr r3, [r7, #0] 8016428: 68fa ldr r2, [r7, #12] 801642a: 1ad2 subs r2, r2, r3 801642c: 683b ldr r3, [r7, #0] 801642e: 605a str r2, [r3, #4] pxFirstFreeBlock->pxNextFreeBlock = pxEnd; 8016430: 4b0c ldr r3, [pc, #48] @ (8016464 ) 8016432: 681a ldr r2, [r3, #0] 8016434: 683b ldr r3, [r7, #0] 8016436: 601a str r2, [r3, #0] /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8016438: 683b ldr r3, [r7, #0] 801643a: 685b ldr r3, [r3, #4] 801643c: 4a0a ldr r2, [pc, #40] @ (8016468 ) 801643e: 6013 str r3, [r2, #0] xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8016440: 683b ldr r3, [r7, #0] 8016442: 685b ldr r3, [r3, #4] 8016444: 4a09 ldr r2, [pc, #36] @ (801646c ) 8016446: 6013 str r3, [r2, #0] /* Work out the position of the top bit in a size_t variable. */ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); 8016448: 4b09 ldr r3, [pc, #36] @ (8016470 ) 801644a: f04f 4200 mov.w r2, #2147483648 @ 0x80000000 801644e: 601a str r2, [r3, #0] } 8016450: bf00 nop 8016452: 3714 adds r7, #20 8016454: 46bd mov sp, r7 8016456: f85d 7b04 ldr.w r7, [sp], #4 801645a: 4770 bx lr 801645c: 24002bd8 .word 0x24002bd8 8016460: 24012bd8 .word 0x24012bd8 8016464: 24012be0 .word 0x24012be0 8016468: 24012be8 .word 0x24012be8 801646c: 24012be4 .word 0x24012be4 8016470: 24012bf4 .word 0x24012bf4 08016474 : /*-----------------------------------------------------------*/ static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) { 8016474: b480 push {r7} 8016476: b085 sub sp, #20 8016478: af00 add r7, sp, #0 801647a: 6078 str r0, [r7, #4] BlockLink_t *pxIterator; uint8_t *puc; /* Iterate through the list until a block is found that has a higher address than the block being inserted. */ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) 801647c: 4b28 ldr r3, [pc, #160] @ (8016520 ) 801647e: 60fb str r3, [r7, #12] 8016480: e002 b.n 8016488 8016482: 68fb ldr r3, [r7, #12] 8016484: 681b ldr r3, [r3, #0] 8016486: 60fb str r3, [r7, #12] 8016488: 68fb ldr r3, [r7, #12] 801648a: 681b ldr r3, [r3, #0] 801648c: 687a ldr r2, [r7, #4] 801648e: 429a cmp r2, r3 8016490: d8f7 bhi.n 8016482 /* Nothing to do here, just iterate to the right position. */ } /* Do the block being inserted, and the block it is being inserted after make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; 8016492: 68fb ldr r3, [r7, #12] 8016494: 60bb str r3, [r7, #8] if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) 8016496: 68fb ldr r3, [r7, #12] 8016498: 685b ldr r3, [r3, #4] 801649a: 68ba ldr r2, [r7, #8] 801649c: 4413 add r3, r2 801649e: 687a ldr r2, [r7, #4] 80164a0: 429a cmp r2, r3 80164a2: d108 bne.n 80164b6 { pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 80164a4: 68fb ldr r3, [r7, #12] 80164a6: 685a ldr r2, [r3, #4] 80164a8: 687b ldr r3, [r7, #4] 80164aa: 685b ldr r3, [r3, #4] 80164ac: 441a add r2, r3 80164ae: 68fb ldr r3, [r7, #12] 80164b0: 605a str r2, [r3, #4] pxBlockToInsert = pxIterator; 80164b2: 68fb ldr r3, [r7, #12] 80164b4: 607b str r3, [r7, #4] mtCOVERAGE_TEST_MARKER(); } /* Do the block being inserted, and the block it is being inserted before make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; 80164b6: 687b ldr r3, [r7, #4] 80164b8: 60bb str r3, [r7, #8] if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 80164ba: 687b ldr r3, [r7, #4] 80164bc: 685b ldr r3, [r3, #4] 80164be: 68ba ldr r2, [r7, #8] 80164c0: 441a add r2, r3 80164c2: 68fb ldr r3, [r7, #12] 80164c4: 681b ldr r3, [r3, #0] 80164c6: 429a cmp r2, r3 80164c8: d118 bne.n 80164fc { if( pxIterator->pxNextFreeBlock != pxEnd ) 80164ca: 68fb ldr r3, [r7, #12] 80164cc: 681a ldr r2, [r3, #0] 80164ce: 4b15 ldr r3, [pc, #84] @ (8016524 ) 80164d0: 681b ldr r3, [r3, #0] 80164d2: 429a cmp r2, r3 80164d4: d00d beq.n 80164f2 { /* Form one big block from the two blocks. */ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; 80164d6: 687b ldr r3, [r7, #4] 80164d8: 685a ldr r2, [r3, #4] 80164da: 68fb ldr r3, [r7, #12] 80164dc: 681b ldr r3, [r3, #0] 80164de: 685b ldr r3, [r3, #4] 80164e0: 441a add r2, r3 80164e2: 687b ldr r3, [r7, #4] 80164e4: 605a str r2, [r3, #4] pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; 80164e6: 68fb ldr r3, [r7, #12] 80164e8: 681b ldr r3, [r3, #0] 80164ea: 681a ldr r2, [r3, #0] 80164ec: 687b ldr r3, [r7, #4] 80164ee: 601a str r2, [r3, #0] 80164f0: e008 b.n 8016504 } else { pxBlockToInsert->pxNextFreeBlock = pxEnd; 80164f2: 4b0c ldr r3, [pc, #48] @ (8016524 ) 80164f4: 681a ldr r2, [r3, #0] 80164f6: 687b ldr r3, [r7, #4] 80164f8: 601a str r2, [r3, #0] 80164fa: e003 b.n 8016504 } } else { pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; 80164fc: 68fb ldr r3, [r7, #12] 80164fe: 681a ldr r2, [r3, #0] 8016500: 687b ldr r3, [r7, #4] 8016502: 601a str r2, [r3, #0] /* If the block being inserted plugged a gab, so was merged with the block before and the block after, then it's pxNextFreeBlock pointer will have already been set, and should not be set here as that would make it point to itself. */ if( pxIterator != pxBlockToInsert ) 8016504: 68fa ldr r2, [r7, #12] 8016506: 687b ldr r3, [r7, #4] 8016508: 429a cmp r2, r3 801650a: d002 beq.n 8016512 { pxIterator->pxNextFreeBlock = pxBlockToInsert; 801650c: 68fb ldr r3, [r7, #12] 801650e: 687a ldr r2, [r7, #4] 8016510: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 8016512: bf00 nop 8016514: 3714 adds r7, #20 8016516: 46bd mov sp, r7 8016518: f85d 7b04 ldr.w r7, [sp], #4 801651c: 4770 bx lr 801651e: bf00 nop 8016520: 24012bd8 .word 0x24012bd8 8016524: 24012be0 .word 0x24012be0 08016528 : 8016528: 2300 movs r3, #0 801652a: b510 push {r4, lr} 801652c: 4604 mov r4, r0 801652e: e9c0 3300 strd r3, r3, [r0] 8016532: e9c0 3304 strd r3, r3, [r0, #16] 8016536: 6083 str r3, [r0, #8] 8016538: 8181 strh r1, [r0, #12] 801653a: 6643 str r3, [r0, #100] @ 0x64 801653c: 81c2 strh r2, [r0, #14] 801653e: 6183 str r3, [r0, #24] 8016540: 4619 mov r1, r3 8016542: 2208 movs r2, #8 8016544: 305c adds r0, #92 @ 0x5c 8016546: f000 f906 bl 8016756 801654a: 4b0d ldr r3, [pc, #52] @ (8016580 ) 801654c: 6263 str r3, [r4, #36] @ 0x24 801654e: 4b0d ldr r3, [pc, #52] @ (8016584 ) 8016550: 62a3 str r3, [r4, #40] @ 0x28 8016552: 4b0d ldr r3, [pc, #52] @ (8016588 ) 8016554: 62e3 str r3, [r4, #44] @ 0x2c 8016556: 4b0d ldr r3, [pc, #52] @ (801658c ) 8016558: 6323 str r3, [r4, #48] @ 0x30 801655a: 4b0d ldr r3, [pc, #52] @ (8016590 ) 801655c: 6224 str r4, [r4, #32] 801655e: 429c cmp r4, r3 8016560: d006 beq.n 8016570 8016562: f103 0268 add.w r2, r3, #104 @ 0x68 8016566: 4294 cmp r4, r2 8016568: d002 beq.n 8016570 801656a: 33d0 adds r3, #208 @ 0xd0 801656c: 429c cmp r4, r3 801656e: d105 bne.n 801657c 8016570: f104 0058 add.w r0, r4, #88 @ 0x58 8016574: e8bd 4010 ldmia.w sp!, {r4, lr} 8016578: f000 b9bc b.w 80168f4 <__retarget_lock_init_recursive> 801657c: bd10 pop {r4, pc} 801657e: bf00 nop 8016580: 080166d1 .word 0x080166d1 8016584: 080166f3 .word 0x080166f3 8016588: 0801672b .word 0x0801672b 801658c: 0801674f .word 0x0801674f 8016590: 24012bf8 .word 0x24012bf8 08016594 : 8016594: 4a02 ldr r2, [pc, #8] @ (80165a0 ) 8016596: 4903 ldr r1, [pc, #12] @ (80165a4 ) 8016598: 4803 ldr r0, [pc, #12] @ (80165a8 ) 801659a: f000 b869 b.w 8016670 <_fwalk_sglue> 801659e: bf00 nop 80165a0: 24000048 .word 0x24000048 80165a4: 080171b1 .word 0x080171b1 80165a8: 24000058 .word 0x24000058 080165ac : 80165ac: 6841 ldr r1, [r0, #4] 80165ae: 4b0c ldr r3, [pc, #48] @ (80165e0 ) 80165b0: 4299 cmp r1, r3 80165b2: b510 push {r4, lr} 80165b4: 4604 mov r4, r0 80165b6: d001 beq.n 80165bc 80165b8: f000 fdfa bl 80171b0 <_fflush_r> 80165bc: 68a1 ldr r1, [r4, #8] 80165be: 4b09 ldr r3, [pc, #36] @ (80165e4 ) 80165c0: 4299 cmp r1, r3 80165c2: d002 beq.n 80165ca 80165c4: 4620 mov r0, r4 80165c6: f000 fdf3 bl 80171b0 <_fflush_r> 80165ca: 68e1 ldr r1, [r4, #12] 80165cc: 4b06 ldr r3, [pc, #24] @ (80165e8 ) 80165ce: 4299 cmp r1, r3 80165d0: d004 beq.n 80165dc 80165d2: 4620 mov r0, r4 80165d4: e8bd 4010 ldmia.w sp!, {r4, lr} 80165d8: f000 bdea b.w 80171b0 <_fflush_r> 80165dc: bd10 pop {r4, pc} 80165de: bf00 nop 80165e0: 24012bf8 .word 0x24012bf8 80165e4: 24012c60 .word 0x24012c60 80165e8: 24012cc8 .word 0x24012cc8 080165ec : 80165ec: b510 push {r4, lr} 80165ee: 4b0b ldr r3, [pc, #44] @ (801661c ) 80165f0: 4c0b ldr r4, [pc, #44] @ (8016620 ) 80165f2: 4a0c ldr r2, [pc, #48] @ (8016624 ) 80165f4: 601a str r2, [r3, #0] 80165f6: 4620 mov r0, r4 80165f8: 2200 movs r2, #0 80165fa: 2104 movs r1, #4 80165fc: f7ff ff94 bl 8016528 8016600: f104 0068 add.w r0, r4, #104 @ 0x68 8016604: 2201 movs r2, #1 8016606: 2109 movs r1, #9 8016608: f7ff ff8e bl 8016528 801660c: f104 00d0 add.w r0, r4, #208 @ 0xd0 8016610: 2202 movs r2, #2 8016612: e8bd 4010 ldmia.w sp!, {r4, lr} 8016616: 2112 movs r1, #18 8016618: f7ff bf86 b.w 8016528 801661c: 24012d30 .word 0x24012d30 8016620: 24012bf8 .word 0x24012bf8 8016624: 08016595 .word 0x08016595 08016628 <__sfp_lock_acquire>: 8016628: 4801 ldr r0, [pc, #4] @ (8016630 <__sfp_lock_acquire+0x8>) 801662a: f000 b964 b.w 80168f6 <__retarget_lock_acquire_recursive> 801662e: bf00 nop 8016630: 24012d39 .word 0x24012d39 08016634 <__sfp_lock_release>: 8016634: 4801 ldr r0, [pc, #4] @ (801663c <__sfp_lock_release+0x8>) 8016636: f000 b95f b.w 80168f8 <__retarget_lock_release_recursive> 801663a: bf00 nop 801663c: 24012d39 .word 0x24012d39 08016640 <__sinit>: 8016640: b510 push {r4, lr} 8016642: 4604 mov r4, r0 8016644: f7ff fff0 bl 8016628 <__sfp_lock_acquire> 8016648: 6a23 ldr r3, [r4, #32] 801664a: b11b cbz r3, 8016654 <__sinit+0x14> 801664c: e8bd 4010 ldmia.w sp!, {r4, lr} 8016650: f7ff bff0 b.w 8016634 <__sfp_lock_release> 8016654: 4b04 ldr r3, [pc, #16] @ (8016668 <__sinit+0x28>) 8016656: 6223 str r3, [r4, #32] 8016658: 4b04 ldr r3, [pc, #16] @ (801666c <__sinit+0x2c>) 801665a: 681b ldr r3, [r3, #0] 801665c: 2b00 cmp r3, #0 801665e: d1f5 bne.n 801664c <__sinit+0xc> 8016660: f7ff ffc4 bl 80165ec 8016664: e7f2 b.n 801664c <__sinit+0xc> 8016666: bf00 nop 8016668: 080165ad .word 0x080165ad 801666c: 24012d30 .word 0x24012d30 08016670 <_fwalk_sglue>: 8016670: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8016674: 4607 mov r7, r0 8016676: 4688 mov r8, r1 8016678: 4614 mov r4, r2 801667a: 2600 movs r6, #0 801667c: e9d4 9501 ldrd r9, r5, [r4, #4] 8016680: f1b9 0901 subs.w r9, r9, #1 8016684: d505 bpl.n 8016692 <_fwalk_sglue+0x22> 8016686: 6824 ldr r4, [r4, #0] 8016688: 2c00 cmp r4, #0 801668a: d1f7 bne.n 801667c <_fwalk_sglue+0xc> 801668c: 4630 mov r0, r6 801668e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8016692: 89ab ldrh r3, [r5, #12] 8016694: 2b01 cmp r3, #1 8016696: d907 bls.n 80166a8 <_fwalk_sglue+0x38> 8016698: f9b5 300e ldrsh.w r3, [r5, #14] 801669c: 3301 adds r3, #1 801669e: d003 beq.n 80166a8 <_fwalk_sglue+0x38> 80166a0: 4629 mov r1, r5 80166a2: 4638 mov r0, r7 80166a4: 47c0 blx r8 80166a6: 4306 orrs r6, r0 80166a8: 3568 adds r5, #104 @ 0x68 80166aa: e7e9 b.n 8016680 <_fwalk_sglue+0x10> 080166ac : 80166ac: b40f push {r0, r1, r2, r3} 80166ae: b507 push {r0, r1, r2, lr} 80166b0: 4906 ldr r1, [pc, #24] @ (80166cc ) 80166b2: ab04 add r3, sp, #16 80166b4: 6808 ldr r0, [r1, #0] 80166b6: f853 2b04 ldr.w r2, [r3], #4 80166ba: 6881 ldr r1, [r0, #8] 80166bc: 9301 str r3, [sp, #4] 80166be: f000 fa4d bl 8016b5c <_vfiprintf_r> 80166c2: b003 add sp, #12 80166c4: f85d eb04 ldr.w lr, [sp], #4 80166c8: b004 add sp, #16 80166ca: 4770 bx lr 80166cc: 24000054 .word 0x24000054 080166d0 <__sread>: 80166d0: b510 push {r4, lr} 80166d2: 460c mov r4, r1 80166d4: f9b1 100e ldrsh.w r1, [r1, #14] 80166d8: f000 f8be bl 8016858 <_read_r> 80166dc: 2800 cmp r0, #0 80166de: bfab itete ge 80166e0: 6d63 ldrge r3, [r4, #84] @ 0x54 80166e2: 89a3 ldrhlt r3, [r4, #12] 80166e4: 181b addge r3, r3, r0 80166e6: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 80166ea: bfac ite ge 80166ec: 6563 strge r3, [r4, #84] @ 0x54 80166ee: 81a3 strhlt r3, [r4, #12] 80166f0: bd10 pop {r4, pc} 080166f2 <__swrite>: 80166f2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80166f6: 461f mov r7, r3 80166f8: 898b ldrh r3, [r1, #12] 80166fa: 05db lsls r3, r3, #23 80166fc: 4605 mov r5, r0 80166fe: 460c mov r4, r1 8016700: 4616 mov r6, r2 8016702: d505 bpl.n 8016710 <__swrite+0x1e> 8016704: f9b1 100e ldrsh.w r1, [r1, #14] 8016708: 2302 movs r3, #2 801670a: 2200 movs r2, #0 801670c: f000 f892 bl 8016834 <_lseek_r> 8016710: 89a3 ldrh r3, [r4, #12] 8016712: f9b4 100e ldrsh.w r1, [r4, #14] 8016716: f423 5380 bic.w r3, r3, #4096 @ 0x1000 801671a: 81a3 strh r3, [r4, #12] 801671c: 4632 mov r2, r6 801671e: 463b mov r3, r7 8016720: 4628 mov r0, r5 8016722: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8016726: f000 b8a9 b.w 801687c <_write_r> 0801672a <__sseek>: 801672a: b510 push {r4, lr} 801672c: 460c mov r4, r1 801672e: f9b1 100e ldrsh.w r1, [r1, #14] 8016732: f000 f87f bl 8016834 <_lseek_r> 8016736: 1c43 adds r3, r0, #1 8016738: 89a3 ldrh r3, [r4, #12] 801673a: bf15 itete ne 801673c: 6560 strne r0, [r4, #84] @ 0x54 801673e: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 8016742: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 8016746: 81a3 strheq r3, [r4, #12] 8016748: bf18 it ne 801674a: 81a3 strhne r3, [r4, #12] 801674c: bd10 pop {r4, pc} 0801674e <__sclose>: 801674e: f9b1 100e ldrsh.w r1, [r1, #14] 8016752: f000 b809 b.w 8016768 <_close_r> 08016756 : 8016756: 4402 add r2, r0 8016758: 4603 mov r3, r0 801675a: 4293 cmp r3, r2 801675c: d100 bne.n 8016760 801675e: 4770 bx lr 8016760: f803 1b01 strb.w r1, [r3], #1 8016764: e7f9 b.n 801675a ... 08016768 <_close_r>: 8016768: b538 push {r3, r4, r5, lr} 801676a: 4d06 ldr r5, [pc, #24] @ (8016784 <_close_r+0x1c>) 801676c: 2300 movs r3, #0 801676e: 4604 mov r4, r0 8016770: 4608 mov r0, r1 8016772: 602b str r3, [r5, #0] 8016774: f7ed f8ed bl 8003952 <_close> 8016778: 1c43 adds r3, r0, #1 801677a: d102 bne.n 8016782 <_close_r+0x1a> 801677c: 682b ldr r3, [r5, #0] 801677e: b103 cbz r3, 8016782 <_close_r+0x1a> 8016780: 6023 str r3, [r4, #0] 8016782: bd38 pop {r3, r4, r5, pc} 8016784: 24012d34 .word 0x24012d34 08016788 <_reclaim_reent>: 8016788: 4b29 ldr r3, [pc, #164] @ (8016830 <_reclaim_reent+0xa8>) 801678a: 681b ldr r3, [r3, #0] 801678c: 4283 cmp r3, r0 801678e: b570 push {r4, r5, r6, lr} 8016790: 4604 mov r4, r0 8016792: d04b beq.n 801682c <_reclaim_reent+0xa4> 8016794: 69c3 ldr r3, [r0, #28] 8016796: b1ab cbz r3, 80167c4 <_reclaim_reent+0x3c> 8016798: 68db ldr r3, [r3, #12] 801679a: b16b cbz r3, 80167b8 <_reclaim_reent+0x30> 801679c: 2500 movs r5, #0 801679e: 69e3 ldr r3, [r4, #28] 80167a0: 68db ldr r3, [r3, #12] 80167a2: 5959 ldr r1, [r3, r5] 80167a4: 2900 cmp r1, #0 80167a6: d13b bne.n 8016820 <_reclaim_reent+0x98> 80167a8: 3504 adds r5, #4 80167aa: 2d80 cmp r5, #128 @ 0x80 80167ac: d1f7 bne.n 801679e <_reclaim_reent+0x16> 80167ae: 69e3 ldr r3, [r4, #28] 80167b0: 4620 mov r0, r4 80167b2: 68d9 ldr r1, [r3, #12] 80167b4: f000 f8b0 bl 8016918 <_free_r> 80167b8: 69e3 ldr r3, [r4, #28] 80167ba: 6819 ldr r1, [r3, #0] 80167bc: b111 cbz r1, 80167c4 <_reclaim_reent+0x3c> 80167be: 4620 mov r0, r4 80167c0: f000 f8aa bl 8016918 <_free_r> 80167c4: 6961 ldr r1, [r4, #20] 80167c6: b111 cbz r1, 80167ce <_reclaim_reent+0x46> 80167c8: 4620 mov r0, r4 80167ca: f000 f8a5 bl 8016918 <_free_r> 80167ce: 69e1 ldr r1, [r4, #28] 80167d0: b111 cbz r1, 80167d8 <_reclaim_reent+0x50> 80167d2: 4620 mov r0, r4 80167d4: f000 f8a0 bl 8016918 <_free_r> 80167d8: 6b21 ldr r1, [r4, #48] @ 0x30 80167da: b111 cbz r1, 80167e2 <_reclaim_reent+0x5a> 80167dc: 4620 mov r0, r4 80167de: f000 f89b bl 8016918 <_free_r> 80167e2: 6b61 ldr r1, [r4, #52] @ 0x34 80167e4: b111 cbz r1, 80167ec <_reclaim_reent+0x64> 80167e6: 4620 mov r0, r4 80167e8: f000 f896 bl 8016918 <_free_r> 80167ec: 6ba1 ldr r1, [r4, #56] @ 0x38 80167ee: b111 cbz r1, 80167f6 <_reclaim_reent+0x6e> 80167f0: 4620 mov r0, r4 80167f2: f000 f891 bl 8016918 <_free_r> 80167f6: 6ca1 ldr r1, [r4, #72] @ 0x48 80167f8: b111 cbz r1, 8016800 <_reclaim_reent+0x78> 80167fa: 4620 mov r0, r4 80167fc: f000 f88c bl 8016918 <_free_r> 8016800: 6c61 ldr r1, [r4, #68] @ 0x44 8016802: b111 cbz r1, 801680a <_reclaim_reent+0x82> 8016804: 4620 mov r0, r4 8016806: f000 f887 bl 8016918 <_free_r> 801680a: 6ae1 ldr r1, [r4, #44] @ 0x2c 801680c: b111 cbz r1, 8016814 <_reclaim_reent+0x8c> 801680e: 4620 mov r0, r4 8016810: f000 f882 bl 8016918 <_free_r> 8016814: 6a23 ldr r3, [r4, #32] 8016816: b14b cbz r3, 801682c <_reclaim_reent+0xa4> 8016818: 4620 mov r0, r4 801681a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} 801681e: 4718 bx r3 8016820: 680e ldr r6, [r1, #0] 8016822: 4620 mov r0, r4 8016824: f000 f878 bl 8016918 <_free_r> 8016828: 4631 mov r1, r6 801682a: e7bb b.n 80167a4 <_reclaim_reent+0x1c> 801682c: bd70 pop {r4, r5, r6, pc} 801682e: bf00 nop 8016830: 24000054 .word 0x24000054 08016834 <_lseek_r>: 8016834: b538 push {r3, r4, r5, lr} 8016836: 4d07 ldr r5, [pc, #28] @ (8016854 <_lseek_r+0x20>) 8016838: 4604 mov r4, r0 801683a: 4608 mov r0, r1 801683c: 4611 mov r1, r2 801683e: 2200 movs r2, #0 8016840: 602a str r2, [r5, #0] 8016842: 461a mov r2, r3 8016844: f7ed f8ac bl 80039a0 <_lseek> 8016848: 1c43 adds r3, r0, #1 801684a: d102 bne.n 8016852 <_lseek_r+0x1e> 801684c: 682b ldr r3, [r5, #0] 801684e: b103 cbz r3, 8016852 <_lseek_r+0x1e> 8016850: 6023 str r3, [r4, #0] 8016852: bd38 pop {r3, r4, r5, pc} 8016854: 24012d34 .word 0x24012d34 08016858 <_read_r>: 8016858: b538 push {r3, r4, r5, lr} 801685a: 4d07 ldr r5, [pc, #28] @ (8016878 <_read_r+0x20>) 801685c: 4604 mov r4, r0 801685e: 4608 mov r0, r1 8016860: 4611 mov r1, r2 8016862: 2200 movs r2, #0 8016864: 602a str r2, [r5, #0] 8016866: 461a mov r2, r3 8016868: f7ed f83a bl 80038e0 <_read> 801686c: 1c43 adds r3, r0, #1 801686e: d102 bne.n 8016876 <_read_r+0x1e> 8016870: 682b ldr r3, [r5, #0] 8016872: b103 cbz r3, 8016876 <_read_r+0x1e> 8016874: 6023 str r3, [r4, #0] 8016876: bd38 pop {r3, r4, r5, pc} 8016878: 24012d34 .word 0x24012d34 0801687c <_write_r>: 801687c: b538 push {r3, r4, r5, lr} 801687e: 4d07 ldr r5, [pc, #28] @ (801689c <_write_r+0x20>) 8016880: 4604 mov r4, r0 8016882: 4608 mov r0, r1 8016884: 4611 mov r1, r2 8016886: 2200 movs r2, #0 8016888: 602a str r2, [r5, #0] 801688a: 461a mov r2, r3 801688c: f7ed f845 bl 800391a <_write> 8016890: 1c43 adds r3, r0, #1 8016892: d102 bne.n 801689a <_write_r+0x1e> 8016894: 682b ldr r3, [r5, #0] 8016896: b103 cbz r3, 801689a <_write_r+0x1e> 8016898: 6023 str r3, [r4, #0] 801689a: bd38 pop {r3, r4, r5, pc} 801689c: 24012d34 .word 0x24012d34 080168a0 <__errno>: 80168a0: 4b01 ldr r3, [pc, #4] @ (80168a8 <__errno+0x8>) 80168a2: 6818 ldr r0, [r3, #0] 80168a4: 4770 bx lr 80168a6: bf00 nop 80168a8: 24000054 .word 0x24000054 080168ac <__libc_init_array>: 80168ac: b570 push {r4, r5, r6, lr} 80168ae: 4d0d ldr r5, [pc, #52] @ (80168e4 <__libc_init_array+0x38>) 80168b0: 4c0d ldr r4, [pc, #52] @ (80168e8 <__libc_init_array+0x3c>) 80168b2: 1b64 subs r4, r4, r5 80168b4: 10a4 asrs r4, r4, #2 80168b6: 2600 movs r6, #0 80168b8: 42a6 cmp r6, r4 80168ba: d109 bne.n 80168d0 <__libc_init_array+0x24> 80168bc: 4d0b ldr r5, [pc, #44] @ (80168ec <__libc_init_array+0x40>) 80168be: 4c0c ldr r4, [pc, #48] @ (80168f0 <__libc_init_array+0x44>) 80168c0: f000 fdc6 bl 8017450 <_init> 80168c4: 1b64 subs r4, r4, r5 80168c6: 10a4 asrs r4, r4, #2 80168c8: 2600 movs r6, #0 80168ca: 42a6 cmp r6, r4 80168cc: d105 bne.n 80168da <__libc_init_array+0x2e> 80168ce: bd70 pop {r4, r5, r6, pc} 80168d0: f855 3b04 ldr.w r3, [r5], #4 80168d4: 4798 blx r3 80168d6: 3601 adds r6, #1 80168d8: e7ee b.n 80168b8 <__libc_init_array+0xc> 80168da: f855 3b04 ldr.w r3, [r5], #4 80168de: 4798 blx r3 80168e0: 3601 adds r6, #1 80168e2: e7f2 b.n 80168ca <__libc_init_array+0x1e> 80168e4: 08017644 .word 0x08017644 80168e8: 08017644 .word 0x08017644 80168ec: 08017644 .word 0x08017644 80168f0: 08017648 .word 0x08017648 080168f4 <__retarget_lock_init_recursive>: 80168f4: 4770 bx lr 080168f6 <__retarget_lock_acquire_recursive>: 80168f6: 4770 bx lr 080168f8 <__retarget_lock_release_recursive>: 80168f8: 4770 bx lr 080168fa : 80168fa: 440a add r2, r1 80168fc: 4291 cmp r1, r2 80168fe: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8016902: d100 bne.n 8016906 8016904: 4770 bx lr 8016906: b510 push {r4, lr} 8016908: f811 4b01 ldrb.w r4, [r1], #1 801690c: f803 4f01 strb.w r4, [r3, #1]! 8016910: 4291 cmp r1, r2 8016912: d1f9 bne.n 8016908 8016914: bd10 pop {r4, pc} ... 08016918 <_free_r>: 8016918: b538 push {r3, r4, r5, lr} 801691a: 4605 mov r5, r0 801691c: 2900 cmp r1, #0 801691e: d041 beq.n 80169a4 <_free_r+0x8c> 8016920: f851 3c04 ldr.w r3, [r1, #-4] 8016924: 1f0c subs r4, r1, #4 8016926: 2b00 cmp r3, #0 8016928: bfb8 it lt 801692a: 18e4 addlt r4, r4, r3 801692c: f000 f8e0 bl 8016af0 <__malloc_lock> 8016930: 4a1d ldr r2, [pc, #116] @ (80169a8 <_free_r+0x90>) 8016932: 6813 ldr r3, [r2, #0] 8016934: b933 cbnz r3, 8016944 <_free_r+0x2c> 8016936: 6063 str r3, [r4, #4] 8016938: 6014 str r4, [r2, #0] 801693a: 4628 mov r0, r5 801693c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8016940: f000 b8dc b.w 8016afc <__malloc_unlock> 8016944: 42a3 cmp r3, r4 8016946: d908 bls.n 801695a <_free_r+0x42> 8016948: 6820 ldr r0, [r4, #0] 801694a: 1821 adds r1, r4, r0 801694c: 428b cmp r3, r1 801694e: bf01 itttt eq 8016950: 6819 ldreq r1, [r3, #0] 8016952: 685b ldreq r3, [r3, #4] 8016954: 1809 addeq r1, r1, r0 8016956: 6021 streq r1, [r4, #0] 8016958: e7ed b.n 8016936 <_free_r+0x1e> 801695a: 461a mov r2, r3 801695c: 685b ldr r3, [r3, #4] 801695e: b10b cbz r3, 8016964 <_free_r+0x4c> 8016960: 42a3 cmp r3, r4 8016962: d9fa bls.n 801695a <_free_r+0x42> 8016964: 6811 ldr r1, [r2, #0] 8016966: 1850 adds r0, r2, r1 8016968: 42a0 cmp r0, r4 801696a: d10b bne.n 8016984 <_free_r+0x6c> 801696c: 6820 ldr r0, [r4, #0] 801696e: 4401 add r1, r0 8016970: 1850 adds r0, r2, r1 8016972: 4283 cmp r3, r0 8016974: 6011 str r1, [r2, #0] 8016976: d1e0 bne.n 801693a <_free_r+0x22> 8016978: 6818 ldr r0, [r3, #0] 801697a: 685b ldr r3, [r3, #4] 801697c: 6053 str r3, [r2, #4] 801697e: 4408 add r0, r1 8016980: 6010 str r0, [r2, #0] 8016982: e7da b.n 801693a <_free_r+0x22> 8016984: d902 bls.n 801698c <_free_r+0x74> 8016986: 230c movs r3, #12 8016988: 602b str r3, [r5, #0] 801698a: e7d6 b.n 801693a <_free_r+0x22> 801698c: 6820 ldr r0, [r4, #0] 801698e: 1821 adds r1, r4, r0 8016990: 428b cmp r3, r1 8016992: bf04 itt eq 8016994: 6819 ldreq r1, [r3, #0] 8016996: 685b ldreq r3, [r3, #4] 8016998: 6063 str r3, [r4, #4] 801699a: bf04 itt eq 801699c: 1809 addeq r1, r1, r0 801699e: 6021 streq r1, [r4, #0] 80169a0: 6054 str r4, [r2, #4] 80169a2: e7ca b.n 801693a <_free_r+0x22> 80169a4: bd38 pop {r3, r4, r5, pc} 80169a6: bf00 nop 80169a8: 24012d40 .word 0x24012d40 080169ac : 80169ac: b570 push {r4, r5, r6, lr} 80169ae: 4e0f ldr r6, [pc, #60] @ (80169ec ) 80169b0: 460c mov r4, r1 80169b2: 6831 ldr r1, [r6, #0] 80169b4: 4605 mov r5, r0 80169b6: b911 cbnz r1, 80169be 80169b8: f000 fcb6 bl 8017328 <_sbrk_r> 80169bc: 6030 str r0, [r6, #0] 80169be: 4621 mov r1, r4 80169c0: 4628 mov r0, r5 80169c2: f000 fcb1 bl 8017328 <_sbrk_r> 80169c6: 1c43 adds r3, r0, #1 80169c8: d103 bne.n 80169d2 80169ca: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 80169ce: 4620 mov r0, r4 80169d0: bd70 pop {r4, r5, r6, pc} 80169d2: 1cc4 adds r4, r0, #3 80169d4: f024 0403 bic.w r4, r4, #3 80169d8: 42a0 cmp r0, r4 80169da: d0f8 beq.n 80169ce 80169dc: 1a21 subs r1, r4, r0 80169de: 4628 mov r0, r5 80169e0: f000 fca2 bl 8017328 <_sbrk_r> 80169e4: 3001 adds r0, #1 80169e6: d1f2 bne.n 80169ce 80169e8: e7ef b.n 80169ca 80169ea: bf00 nop 80169ec: 24012d3c .word 0x24012d3c 080169f0 <_malloc_r>: 80169f0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 80169f4: 1ccd adds r5, r1, #3 80169f6: f025 0503 bic.w r5, r5, #3 80169fa: 3508 adds r5, #8 80169fc: 2d0c cmp r5, #12 80169fe: bf38 it cc 8016a00: 250c movcc r5, #12 8016a02: 2d00 cmp r5, #0 8016a04: 4606 mov r6, r0 8016a06: db01 blt.n 8016a0c <_malloc_r+0x1c> 8016a08: 42a9 cmp r1, r5 8016a0a: d904 bls.n 8016a16 <_malloc_r+0x26> 8016a0c: 230c movs r3, #12 8016a0e: 6033 str r3, [r6, #0] 8016a10: 2000 movs r0, #0 8016a12: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8016a16: f8df 80d4 ldr.w r8, [pc, #212] @ 8016aec <_malloc_r+0xfc> 8016a1a: f000 f869 bl 8016af0 <__malloc_lock> 8016a1e: f8d8 3000 ldr.w r3, [r8] 8016a22: 461c mov r4, r3 8016a24: bb44 cbnz r4, 8016a78 <_malloc_r+0x88> 8016a26: 4629 mov r1, r5 8016a28: 4630 mov r0, r6 8016a2a: f7ff ffbf bl 80169ac 8016a2e: 1c43 adds r3, r0, #1 8016a30: 4604 mov r4, r0 8016a32: d158 bne.n 8016ae6 <_malloc_r+0xf6> 8016a34: f8d8 4000 ldr.w r4, [r8] 8016a38: 4627 mov r7, r4 8016a3a: 2f00 cmp r7, #0 8016a3c: d143 bne.n 8016ac6 <_malloc_r+0xd6> 8016a3e: 2c00 cmp r4, #0 8016a40: d04b beq.n 8016ada <_malloc_r+0xea> 8016a42: 6823 ldr r3, [r4, #0] 8016a44: 4639 mov r1, r7 8016a46: 4630 mov r0, r6 8016a48: eb04 0903 add.w r9, r4, r3 8016a4c: f000 fc6c bl 8017328 <_sbrk_r> 8016a50: 4581 cmp r9, r0 8016a52: d142 bne.n 8016ada <_malloc_r+0xea> 8016a54: 6821 ldr r1, [r4, #0] 8016a56: 1a6d subs r5, r5, r1 8016a58: 4629 mov r1, r5 8016a5a: 4630 mov r0, r6 8016a5c: f7ff ffa6 bl 80169ac 8016a60: 3001 adds r0, #1 8016a62: d03a beq.n 8016ada <_malloc_r+0xea> 8016a64: 6823 ldr r3, [r4, #0] 8016a66: 442b add r3, r5 8016a68: 6023 str r3, [r4, #0] 8016a6a: f8d8 3000 ldr.w r3, [r8] 8016a6e: 685a ldr r2, [r3, #4] 8016a70: bb62 cbnz r2, 8016acc <_malloc_r+0xdc> 8016a72: f8c8 7000 str.w r7, [r8] 8016a76: e00f b.n 8016a98 <_malloc_r+0xa8> 8016a78: 6822 ldr r2, [r4, #0] 8016a7a: 1b52 subs r2, r2, r5 8016a7c: d420 bmi.n 8016ac0 <_malloc_r+0xd0> 8016a7e: 2a0b cmp r2, #11 8016a80: d917 bls.n 8016ab2 <_malloc_r+0xc2> 8016a82: 1961 adds r1, r4, r5 8016a84: 42a3 cmp r3, r4 8016a86: 6025 str r5, [r4, #0] 8016a88: bf18 it ne 8016a8a: 6059 strne r1, [r3, #4] 8016a8c: 6863 ldr r3, [r4, #4] 8016a8e: bf08 it eq 8016a90: f8c8 1000 streq.w r1, [r8] 8016a94: 5162 str r2, [r4, r5] 8016a96: 604b str r3, [r1, #4] 8016a98: 4630 mov r0, r6 8016a9a: f000 f82f bl 8016afc <__malloc_unlock> 8016a9e: f104 000b add.w r0, r4, #11 8016aa2: 1d23 adds r3, r4, #4 8016aa4: f020 0007 bic.w r0, r0, #7 8016aa8: 1ac2 subs r2, r0, r3 8016aaa: bf1c itt ne 8016aac: 1a1b subne r3, r3, r0 8016aae: 50a3 strne r3, [r4, r2] 8016ab0: e7af b.n 8016a12 <_malloc_r+0x22> 8016ab2: 6862 ldr r2, [r4, #4] 8016ab4: 42a3 cmp r3, r4 8016ab6: bf0c ite eq 8016ab8: f8c8 2000 streq.w r2, [r8] 8016abc: 605a strne r2, [r3, #4] 8016abe: e7eb b.n 8016a98 <_malloc_r+0xa8> 8016ac0: 4623 mov r3, r4 8016ac2: 6864 ldr r4, [r4, #4] 8016ac4: e7ae b.n 8016a24 <_malloc_r+0x34> 8016ac6: 463c mov r4, r7 8016ac8: 687f ldr r7, [r7, #4] 8016aca: e7b6 b.n 8016a3a <_malloc_r+0x4a> 8016acc: 461a mov r2, r3 8016ace: 685b ldr r3, [r3, #4] 8016ad0: 42a3 cmp r3, r4 8016ad2: d1fb bne.n 8016acc <_malloc_r+0xdc> 8016ad4: 2300 movs r3, #0 8016ad6: 6053 str r3, [r2, #4] 8016ad8: e7de b.n 8016a98 <_malloc_r+0xa8> 8016ada: 230c movs r3, #12 8016adc: 6033 str r3, [r6, #0] 8016ade: 4630 mov r0, r6 8016ae0: f000 f80c bl 8016afc <__malloc_unlock> 8016ae4: e794 b.n 8016a10 <_malloc_r+0x20> 8016ae6: 6005 str r5, [r0, #0] 8016ae8: e7d6 b.n 8016a98 <_malloc_r+0xa8> 8016aea: bf00 nop 8016aec: 24012d40 .word 0x24012d40 08016af0 <__malloc_lock>: 8016af0: 4801 ldr r0, [pc, #4] @ (8016af8 <__malloc_lock+0x8>) 8016af2: f7ff bf00 b.w 80168f6 <__retarget_lock_acquire_recursive> 8016af6: bf00 nop 8016af8: 24012d38 .word 0x24012d38 08016afc <__malloc_unlock>: 8016afc: 4801 ldr r0, [pc, #4] @ (8016b04 <__malloc_unlock+0x8>) 8016afe: f7ff befb b.w 80168f8 <__retarget_lock_release_recursive> 8016b02: bf00 nop 8016b04: 24012d38 .word 0x24012d38 08016b08 <__sfputc_r>: 8016b08: 6893 ldr r3, [r2, #8] 8016b0a: 3b01 subs r3, #1 8016b0c: 2b00 cmp r3, #0 8016b0e: b410 push {r4} 8016b10: 6093 str r3, [r2, #8] 8016b12: da08 bge.n 8016b26 <__sfputc_r+0x1e> 8016b14: 6994 ldr r4, [r2, #24] 8016b16: 42a3 cmp r3, r4 8016b18: db01 blt.n 8016b1e <__sfputc_r+0x16> 8016b1a: 290a cmp r1, #10 8016b1c: d103 bne.n 8016b26 <__sfputc_r+0x1e> 8016b1e: f85d 4b04 ldr.w r4, [sp], #4 8016b22: f000 bb6d b.w 8017200 <__swbuf_r> 8016b26: 6813 ldr r3, [r2, #0] 8016b28: 1c58 adds r0, r3, #1 8016b2a: 6010 str r0, [r2, #0] 8016b2c: 7019 strb r1, [r3, #0] 8016b2e: 4608 mov r0, r1 8016b30: f85d 4b04 ldr.w r4, [sp], #4 8016b34: 4770 bx lr 08016b36 <__sfputs_r>: 8016b36: b5f8 push {r3, r4, r5, r6, r7, lr} 8016b38: 4606 mov r6, r0 8016b3a: 460f mov r7, r1 8016b3c: 4614 mov r4, r2 8016b3e: 18d5 adds r5, r2, r3 8016b40: 42ac cmp r4, r5 8016b42: d101 bne.n 8016b48 <__sfputs_r+0x12> 8016b44: 2000 movs r0, #0 8016b46: e007 b.n 8016b58 <__sfputs_r+0x22> 8016b48: f814 1b01 ldrb.w r1, [r4], #1 8016b4c: 463a mov r2, r7 8016b4e: 4630 mov r0, r6 8016b50: f7ff ffda bl 8016b08 <__sfputc_r> 8016b54: 1c43 adds r3, r0, #1 8016b56: d1f3 bne.n 8016b40 <__sfputs_r+0xa> 8016b58: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 08016b5c <_vfiprintf_r>: 8016b5c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8016b60: 460d mov r5, r1 8016b62: b09d sub sp, #116 @ 0x74 8016b64: 4614 mov r4, r2 8016b66: 4698 mov r8, r3 8016b68: 4606 mov r6, r0 8016b6a: b118 cbz r0, 8016b74 <_vfiprintf_r+0x18> 8016b6c: 6a03 ldr r3, [r0, #32] 8016b6e: b90b cbnz r3, 8016b74 <_vfiprintf_r+0x18> 8016b70: f7ff fd66 bl 8016640 <__sinit> 8016b74: 6e6b ldr r3, [r5, #100] @ 0x64 8016b76: 07d9 lsls r1, r3, #31 8016b78: d405 bmi.n 8016b86 <_vfiprintf_r+0x2a> 8016b7a: 89ab ldrh r3, [r5, #12] 8016b7c: 059a lsls r2, r3, #22 8016b7e: d402 bmi.n 8016b86 <_vfiprintf_r+0x2a> 8016b80: 6da8 ldr r0, [r5, #88] @ 0x58 8016b82: f7ff feb8 bl 80168f6 <__retarget_lock_acquire_recursive> 8016b86: 89ab ldrh r3, [r5, #12] 8016b88: 071b lsls r3, r3, #28 8016b8a: d501 bpl.n 8016b90 <_vfiprintf_r+0x34> 8016b8c: 692b ldr r3, [r5, #16] 8016b8e: b99b cbnz r3, 8016bb8 <_vfiprintf_r+0x5c> 8016b90: 4629 mov r1, r5 8016b92: 4630 mov r0, r6 8016b94: f000 fb72 bl 801727c <__swsetup_r> 8016b98: b170 cbz r0, 8016bb8 <_vfiprintf_r+0x5c> 8016b9a: 6e6b ldr r3, [r5, #100] @ 0x64 8016b9c: 07dc lsls r4, r3, #31 8016b9e: d504 bpl.n 8016baa <_vfiprintf_r+0x4e> 8016ba0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016ba4: b01d add sp, #116 @ 0x74 8016ba6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8016baa: 89ab ldrh r3, [r5, #12] 8016bac: 0598 lsls r0, r3, #22 8016bae: d4f7 bmi.n 8016ba0 <_vfiprintf_r+0x44> 8016bb0: 6da8 ldr r0, [r5, #88] @ 0x58 8016bb2: f7ff fea1 bl 80168f8 <__retarget_lock_release_recursive> 8016bb6: e7f3 b.n 8016ba0 <_vfiprintf_r+0x44> 8016bb8: 2300 movs r3, #0 8016bba: 9309 str r3, [sp, #36] @ 0x24 8016bbc: 2320 movs r3, #32 8016bbe: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8016bc2: f8cd 800c str.w r8, [sp, #12] 8016bc6: 2330 movs r3, #48 @ 0x30 8016bc8: f8df 81ac ldr.w r8, [pc, #428] @ 8016d78 <_vfiprintf_r+0x21c> 8016bcc: f88d 302a strb.w r3, [sp, #42] @ 0x2a 8016bd0: f04f 0901 mov.w r9, #1 8016bd4: 4623 mov r3, r4 8016bd6: 469a mov sl, r3 8016bd8: f813 2b01 ldrb.w r2, [r3], #1 8016bdc: b10a cbz r2, 8016be2 <_vfiprintf_r+0x86> 8016bde: 2a25 cmp r2, #37 @ 0x25 8016be0: d1f9 bne.n 8016bd6 <_vfiprintf_r+0x7a> 8016be2: ebba 0b04 subs.w fp, sl, r4 8016be6: d00b beq.n 8016c00 <_vfiprintf_r+0xa4> 8016be8: 465b mov r3, fp 8016bea: 4622 mov r2, r4 8016bec: 4629 mov r1, r5 8016bee: 4630 mov r0, r6 8016bf0: f7ff ffa1 bl 8016b36 <__sfputs_r> 8016bf4: 3001 adds r0, #1 8016bf6: f000 80a7 beq.w 8016d48 <_vfiprintf_r+0x1ec> 8016bfa: 9a09 ldr r2, [sp, #36] @ 0x24 8016bfc: 445a add r2, fp 8016bfe: 9209 str r2, [sp, #36] @ 0x24 8016c00: f89a 3000 ldrb.w r3, [sl] 8016c04: 2b00 cmp r3, #0 8016c06: f000 809f beq.w 8016d48 <_vfiprintf_r+0x1ec> 8016c0a: 2300 movs r3, #0 8016c0c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8016c10: e9cd 2305 strd r2, r3, [sp, #20] 8016c14: f10a 0a01 add.w sl, sl, #1 8016c18: 9304 str r3, [sp, #16] 8016c1a: 9307 str r3, [sp, #28] 8016c1c: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8016c20: 931a str r3, [sp, #104] @ 0x68 8016c22: 4654 mov r4, sl 8016c24: 2205 movs r2, #5 8016c26: f814 1b01 ldrb.w r1, [r4], #1 8016c2a: 4853 ldr r0, [pc, #332] @ (8016d78 <_vfiprintf_r+0x21c>) 8016c2c: f7e9 fb58 bl 80002e0 8016c30: 9a04 ldr r2, [sp, #16] 8016c32: b9d8 cbnz r0, 8016c6c <_vfiprintf_r+0x110> 8016c34: 06d1 lsls r1, r2, #27 8016c36: bf44 itt mi 8016c38: 2320 movmi r3, #32 8016c3a: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8016c3e: 0713 lsls r3, r2, #28 8016c40: bf44 itt mi 8016c42: 232b movmi r3, #43 @ 0x2b 8016c44: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8016c48: f89a 3000 ldrb.w r3, [sl] 8016c4c: 2b2a cmp r3, #42 @ 0x2a 8016c4e: d015 beq.n 8016c7c <_vfiprintf_r+0x120> 8016c50: 9a07 ldr r2, [sp, #28] 8016c52: 4654 mov r4, sl 8016c54: 2000 movs r0, #0 8016c56: f04f 0c0a mov.w ip, #10 8016c5a: 4621 mov r1, r4 8016c5c: f811 3b01 ldrb.w r3, [r1], #1 8016c60: 3b30 subs r3, #48 @ 0x30 8016c62: 2b09 cmp r3, #9 8016c64: d94b bls.n 8016cfe <_vfiprintf_r+0x1a2> 8016c66: b1b0 cbz r0, 8016c96 <_vfiprintf_r+0x13a> 8016c68: 9207 str r2, [sp, #28] 8016c6a: e014 b.n 8016c96 <_vfiprintf_r+0x13a> 8016c6c: eba0 0308 sub.w r3, r0, r8 8016c70: fa09 f303 lsl.w r3, r9, r3 8016c74: 4313 orrs r3, r2 8016c76: 9304 str r3, [sp, #16] 8016c78: 46a2 mov sl, r4 8016c7a: e7d2 b.n 8016c22 <_vfiprintf_r+0xc6> 8016c7c: 9b03 ldr r3, [sp, #12] 8016c7e: 1d19 adds r1, r3, #4 8016c80: 681b ldr r3, [r3, #0] 8016c82: 9103 str r1, [sp, #12] 8016c84: 2b00 cmp r3, #0 8016c86: bfbb ittet lt 8016c88: 425b neglt r3, r3 8016c8a: f042 0202 orrlt.w r2, r2, #2 8016c8e: 9307 strge r3, [sp, #28] 8016c90: 9307 strlt r3, [sp, #28] 8016c92: bfb8 it lt 8016c94: 9204 strlt r2, [sp, #16] 8016c96: 7823 ldrb r3, [r4, #0] 8016c98: 2b2e cmp r3, #46 @ 0x2e 8016c9a: d10a bne.n 8016cb2 <_vfiprintf_r+0x156> 8016c9c: 7863 ldrb r3, [r4, #1] 8016c9e: 2b2a cmp r3, #42 @ 0x2a 8016ca0: d132 bne.n 8016d08 <_vfiprintf_r+0x1ac> 8016ca2: 9b03 ldr r3, [sp, #12] 8016ca4: 1d1a adds r2, r3, #4 8016ca6: 681b ldr r3, [r3, #0] 8016ca8: 9203 str r2, [sp, #12] 8016caa: ea43 73e3 orr.w r3, r3, r3, asr #31 8016cae: 3402 adds r4, #2 8016cb0: 9305 str r3, [sp, #20] 8016cb2: f8df a0d4 ldr.w sl, [pc, #212] @ 8016d88 <_vfiprintf_r+0x22c> 8016cb6: 7821 ldrb r1, [r4, #0] 8016cb8: 2203 movs r2, #3 8016cba: 4650 mov r0, sl 8016cbc: f7e9 fb10 bl 80002e0 8016cc0: b138 cbz r0, 8016cd2 <_vfiprintf_r+0x176> 8016cc2: 9b04 ldr r3, [sp, #16] 8016cc4: eba0 000a sub.w r0, r0, sl 8016cc8: 2240 movs r2, #64 @ 0x40 8016cca: 4082 lsls r2, r0 8016ccc: 4313 orrs r3, r2 8016cce: 3401 adds r4, #1 8016cd0: 9304 str r3, [sp, #16] 8016cd2: f814 1b01 ldrb.w r1, [r4], #1 8016cd6: 4829 ldr r0, [pc, #164] @ (8016d7c <_vfiprintf_r+0x220>) 8016cd8: f88d 1028 strb.w r1, [sp, #40] @ 0x28 8016cdc: 2206 movs r2, #6 8016cde: f7e9 faff bl 80002e0 8016ce2: 2800 cmp r0, #0 8016ce4: d03f beq.n 8016d66 <_vfiprintf_r+0x20a> 8016ce6: 4b26 ldr r3, [pc, #152] @ (8016d80 <_vfiprintf_r+0x224>) 8016ce8: bb1b cbnz r3, 8016d32 <_vfiprintf_r+0x1d6> 8016cea: 9b03 ldr r3, [sp, #12] 8016cec: 3307 adds r3, #7 8016cee: f023 0307 bic.w r3, r3, #7 8016cf2: 3308 adds r3, #8 8016cf4: 9303 str r3, [sp, #12] 8016cf6: 9b09 ldr r3, [sp, #36] @ 0x24 8016cf8: 443b add r3, r7 8016cfa: 9309 str r3, [sp, #36] @ 0x24 8016cfc: e76a b.n 8016bd4 <_vfiprintf_r+0x78> 8016cfe: fb0c 3202 mla r2, ip, r2, r3 8016d02: 460c mov r4, r1 8016d04: 2001 movs r0, #1 8016d06: e7a8 b.n 8016c5a <_vfiprintf_r+0xfe> 8016d08: 2300 movs r3, #0 8016d0a: 3401 adds r4, #1 8016d0c: 9305 str r3, [sp, #20] 8016d0e: 4619 mov r1, r3 8016d10: f04f 0c0a mov.w ip, #10 8016d14: 4620 mov r0, r4 8016d16: f810 2b01 ldrb.w r2, [r0], #1 8016d1a: 3a30 subs r2, #48 @ 0x30 8016d1c: 2a09 cmp r2, #9 8016d1e: d903 bls.n 8016d28 <_vfiprintf_r+0x1cc> 8016d20: 2b00 cmp r3, #0 8016d22: d0c6 beq.n 8016cb2 <_vfiprintf_r+0x156> 8016d24: 9105 str r1, [sp, #20] 8016d26: e7c4 b.n 8016cb2 <_vfiprintf_r+0x156> 8016d28: fb0c 2101 mla r1, ip, r1, r2 8016d2c: 4604 mov r4, r0 8016d2e: 2301 movs r3, #1 8016d30: e7f0 b.n 8016d14 <_vfiprintf_r+0x1b8> 8016d32: ab03 add r3, sp, #12 8016d34: 9300 str r3, [sp, #0] 8016d36: 462a mov r2, r5 8016d38: 4b12 ldr r3, [pc, #72] @ (8016d84 <_vfiprintf_r+0x228>) 8016d3a: a904 add r1, sp, #16 8016d3c: 4630 mov r0, r6 8016d3e: f3af 8000 nop.w 8016d42: 4607 mov r7, r0 8016d44: 1c78 adds r0, r7, #1 8016d46: d1d6 bne.n 8016cf6 <_vfiprintf_r+0x19a> 8016d48: 6e6b ldr r3, [r5, #100] @ 0x64 8016d4a: 07d9 lsls r1, r3, #31 8016d4c: d405 bmi.n 8016d5a <_vfiprintf_r+0x1fe> 8016d4e: 89ab ldrh r3, [r5, #12] 8016d50: 059a lsls r2, r3, #22 8016d52: d402 bmi.n 8016d5a <_vfiprintf_r+0x1fe> 8016d54: 6da8 ldr r0, [r5, #88] @ 0x58 8016d56: f7ff fdcf bl 80168f8 <__retarget_lock_release_recursive> 8016d5a: 89ab ldrh r3, [r5, #12] 8016d5c: 065b lsls r3, r3, #25 8016d5e: f53f af1f bmi.w 8016ba0 <_vfiprintf_r+0x44> 8016d62: 9809 ldr r0, [sp, #36] @ 0x24 8016d64: e71e b.n 8016ba4 <_vfiprintf_r+0x48> 8016d66: ab03 add r3, sp, #12 8016d68: 9300 str r3, [sp, #0] 8016d6a: 462a mov r2, r5 8016d6c: 4b05 ldr r3, [pc, #20] @ (8016d84 <_vfiprintf_r+0x228>) 8016d6e: a904 add r1, sp, #16 8016d70: 4630 mov r0, r6 8016d72: f000 f879 bl 8016e68 <_printf_i> 8016d76: e7e4 b.n 8016d42 <_vfiprintf_r+0x1e6> 8016d78: 08017608 .word 0x08017608 8016d7c: 08017612 .word 0x08017612 8016d80: 00000000 .word 0x00000000 8016d84: 08016b37 .word 0x08016b37 8016d88: 0801760e .word 0x0801760e 08016d8c <_printf_common>: 8016d8c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8016d90: 4616 mov r6, r2 8016d92: 4698 mov r8, r3 8016d94: 688a ldr r2, [r1, #8] 8016d96: 690b ldr r3, [r1, #16] 8016d98: f8dd 9020 ldr.w r9, [sp, #32] 8016d9c: 4293 cmp r3, r2 8016d9e: bfb8 it lt 8016da0: 4613 movlt r3, r2 8016da2: 6033 str r3, [r6, #0] 8016da4: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 8016da8: 4607 mov r7, r0 8016daa: 460c mov r4, r1 8016dac: b10a cbz r2, 8016db2 <_printf_common+0x26> 8016dae: 3301 adds r3, #1 8016db0: 6033 str r3, [r6, #0] 8016db2: 6823 ldr r3, [r4, #0] 8016db4: 0699 lsls r1, r3, #26 8016db6: bf42 ittt mi 8016db8: 6833 ldrmi r3, [r6, #0] 8016dba: 3302 addmi r3, #2 8016dbc: 6033 strmi r3, [r6, #0] 8016dbe: 6825 ldr r5, [r4, #0] 8016dc0: f015 0506 ands.w r5, r5, #6 8016dc4: d106 bne.n 8016dd4 <_printf_common+0x48> 8016dc6: f104 0a19 add.w sl, r4, #25 8016dca: 68e3 ldr r3, [r4, #12] 8016dcc: 6832 ldr r2, [r6, #0] 8016dce: 1a9b subs r3, r3, r2 8016dd0: 42ab cmp r3, r5 8016dd2: dc26 bgt.n 8016e22 <_printf_common+0x96> 8016dd4: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 8016dd8: 6822 ldr r2, [r4, #0] 8016dda: 3b00 subs r3, #0 8016ddc: bf18 it ne 8016dde: 2301 movne r3, #1 8016de0: 0692 lsls r2, r2, #26 8016de2: d42b bmi.n 8016e3c <_printf_common+0xb0> 8016de4: f104 0243 add.w r2, r4, #67 @ 0x43 8016de8: 4641 mov r1, r8 8016dea: 4638 mov r0, r7 8016dec: 47c8 blx r9 8016dee: 3001 adds r0, #1 8016df0: d01e beq.n 8016e30 <_printf_common+0xa4> 8016df2: 6823 ldr r3, [r4, #0] 8016df4: 6922 ldr r2, [r4, #16] 8016df6: f003 0306 and.w r3, r3, #6 8016dfa: 2b04 cmp r3, #4 8016dfc: bf02 ittt eq 8016dfe: 68e5 ldreq r5, [r4, #12] 8016e00: 6833 ldreq r3, [r6, #0] 8016e02: 1aed subeq r5, r5, r3 8016e04: 68a3 ldr r3, [r4, #8] 8016e06: bf0c ite eq 8016e08: ea25 75e5 biceq.w r5, r5, r5, asr #31 8016e0c: 2500 movne r5, #0 8016e0e: 4293 cmp r3, r2 8016e10: bfc4 itt gt 8016e12: 1a9b subgt r3, r3, r2 8016e14: 18ed addgt r5, r5, r3 8016e16: 2600 movs r6, #0 8016e18: 341a adds r4, #26 8016e1a: 42b5 cmp r5, r6 8016e1c: d11a bne.n 8016e54 <_printf_common+0xc8> 8016e1e: 2000 movs r0, #0 8016e20: e008 b.n 8016e34 <_printf_common+0xa8> 8016e22: 2301 movs r3, #1 8016e24: 4652 mov r2, sl 8016e26: 4641 mov r1, r8 8016e28: 4638 mov r0, r7 8016e2a: 47c8 blx r9 8016e2c: 3001 adds r0, #1 8016e2e: d103 bne.n 8016e38 <_printf_common+0xac> 8016e30: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016e34: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8016e38: 3501 adds r5, #1 8016e3a: e7c6 b.n 8016dca <_printf_common+0x3e> 8016e3c: 18e1 adds r1, r4, r3 8016e3e: 1c5a adds r2, r3, #1 8016e40: 2030 movs r0, #48 @ 0x30 8016e42: f881 0043 strb.w r0, [r1, #67] @ 0x43 8016e46: 4422 add r2, r4 8016e48: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 8016e4c: f882 1043 strb.w r1, [r2, #67] @ 0x43 8016e50: 3302 adds r3, #2 8016e52: e7c7 b.n 8016de4 <_printf_common+0x58> 8016e54: 2301 movs r3, #1 8016e56: 4622 mov r2, r4 8016e58: 4641 mov r1, r8 8016e5a: 4638 mov r0, r7 8016e5c: 47c8 blx r9 8016e5e: 3001 adds r0, #1 8016e60: d0e6 beq.n 8016e30 <_printf_common+0xa4> 8016e62: 3601 adds r6, #1 8016e64: e7d9 b.n 8016e1a <_printf_common+0x8e> ... 08016e68 <_printf_i>: 8016e68: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8016e6c: 7e0f ldrb r7, [r1, #24] 8016e6e: 9e0c ldr r6, [sp, #48] @ 0x30 8016e70: 2f78 cmp r7, #120 @ 0x78 8016e72: 4691 mov r9, r2 8016e74: 4680 mov r8, r0 8016e76: 460c mov r4, r1 8016e78: 469a mov sl, r3 8016e7a: f101 0243 add.w r2, r1, #67 @ 0x43 8016e7e: d807 bhi.n 8016e90 <_printf_i+0x28> 8016e80: 2f62 cmp r7, #98 @ 0x62 8016e82: d80a bhi.n 8016e9a <_printf_i+0x32> 8016e84: 2f00 cmp r7, #0 8016e86: f000 80d2 beq.w 801702e <_printf_i+0x1c6> 8016e8a: 2f58 cmp r7, #88 @ 0x58 8016e8c: f000 80b9 beq.w 8017002 <_printf_i+0x19a> 8016e90: f104 0642 add.w r6, r4, #66 @ 0x42 8016e94: f884 7042 strb.w r7, [r4, #66] @ 0x42 8016e98: e03a b.n 8016f10 <_printf_i+0xa8> 8016e9a: f1a7 0363 sub.w r3, r7, #99 @ 0x63 8016e9e: 2b15 cmp r3, #21 8016ea0: d8f6 bhi.n 8016e90 <_printf_i+0x28> 8016ea2: a101 add r1, pc, #4 @ (adr r1, 8016ea8 <_printf_i+0x40>) 8016ea4: f851 f023 ldr.w pc, [r1, r3, lsl #2] 8016ea8: 08016f01 .word 0x08016f01 8016eac: 08016f15 .word 0x08016f15 8016eb0: 08016e91 .word 0x08016e91 8016eb4: 08016e91 .word 0x08016e91 8016eb8: 08016e91 .word 0x08016e91 8016ebc: 08016e91 .word 0x08016e91 8016ec0: 08016f15 .word 0x08016f15 8016ec4: 08016e91 .word 0x08016e91 8016ec8: 08016e91 .word 0x08016e91 8016ecc: 08016e91 .word 0x08016e91 8016ed0: 08016e91 .word 0x08016e91 8016ed4: 08017015 .word 0x08017015 8016ed8: 08016f3f .word 0x08016f3f 8016edc: 08016fcf .word 0x08016fcf 8016ee0: 08016e91 .word 0x08016e91 8016ee4: 08016e91 .word 0x08016e91 8016ee8: 08017037 .word 0x08017037 8016eec: 08016e91 .word 0x08016e91 8016ef0: 08016f3f .word 0x08016f3f 8016ef4: 08016e91 .word 0x08016e91 8016ef8: 08016e91 .word 0x08016e91 8016efc: 08016fd7 .word 0x08016fd7 8016f00: 6833 ldr r3, [r6, #0] 8016f02: 1d1a adds r2, r3, #4 8016f04: 681b ldr r3, [r3, #0] 8016f06: 6032 str r2, [r6, #0] 8016f08: f104 0642 add.w r6, r4, #66 @ 0x42 8016f0c: f884 3042 strb.w r3, [r4, #66] @ 0x42 8016f10: 2301 movs r3, #1 8016f12: e09d b.n 8017050 <_printf_i+0x1e8> 8016f14: 6833 ldr r3, [r6, #0] 8016f16: 6820 ldr r0, [r4, #0] 8016f18: 1d19 adds r1, r3, #4 8016f1a: 6031 str r1, [r6, #0] 8016f1c: 0606 lsls r6, r0, #24 8016f1e: d501 bpl.n 8016f24 <_printf_i+0xbc> 8016f20: 681d ldr r5, [r3, #0] 8016f22: e003 b.n 8016f2c <_printf_i+0xc4> 8016f24: 0645 lsls r5, r0, #25 8016f26: d5fb bpl.n 8016f20 <_printf_i+0xb8> 8016f28: f9b3 5000 ldrsh.w r5, [r3] 8016f2c: 2d00 cmp r5, #0 8016f2e: da03 bge.n 8016f38 <_printf_i+0xd0> 8016f30: 232d movs r3, #45 @ 0x2d 8016f32: 426d negs r5, r5 8016f34: f884 3043 strb.w r3, [r4, #67] @ 0x43 8016f38: 4859 ldr r0, [pc, #356] @ (80170a0 <_printf_i+0x238>) 8016f3a: 230a movs r3, #10 8016f3c: e011 b.n 8016f62 <_printf_i+0xfa> 8016f3e: 6821 ldr r1, [r4, #0] 8016f40: 6833 ldr r3, [r6, #0] 8016f42: 0608 lsls r0, r1, #24 8016f44: f853 5b04 ldr.w r5, [r3], #4 8016f48: d402 bmi.n 8016f50 <_printf_i+0xe8> 8016f4a: 0649 lsls r1, r1, #25 8016f4c: bf48 it mi 8016f4e: b2ad uxthmi r5, r5 8016f50: 2f6f cmp r7, #111 @ 0x6f 8016f52: 4853 ldr r0, [pc, #332] @ (80170a0 <_printf_i+0x238>) 8016f54: 6033 str r3, [r6, #0] 8016f56: bf14 ite ne 8016f58: 230a movne r3, #10 8016f5a: 2308 moveq r3, #8 8016f5c: 2100 movs r1, #0 8016f5e: f884 1043 strb.w r1, [r4, #67] @ 0x43 8016f62: 6866 ldr r6, [r4, #4] 8016f64: 60a6 str r6, [r4, #8] 8016f66: 2e00 cmp r6, #0 8016f68: bfa2 ittt ge 8016f6a: 6821 ldrge r1, [r4, #0] 8016f6c: f021 0104 bicge.w r1, r1, #4 8016f70: 6021 strge r1, [r4, #0] 8016f72: b90d cbnz r5, 8016f78 <_printf_i+0x110> 8016f74: 2e00 cmp r6, #0 8016f76: d04b beq.n 8017010 <_printf_i+0x1a8> 8016f78: 4616 mov r6, r2 8016f7a: fbb5 f1f3 udiv r1, r5, r3 8016f7e: fb03 5711 mls r7, r3, r1, r5 8016f82: 5dc7 ldrb r7, [r0, r7] 8016f84: f806 7d01 strb.w r7, [r6, #-1]! 8016f88: 462f mov r7, r5 8016f8a: 42bb cmp r3, r7 8016f8c: 460d mov r5, r1 8016f8e: d9f4 bls.n 8016f7a <_printf_i+0x112> 8016f90: 2b08 cmp r3, #8 8016f92: d10b bne.n 8016fac <_printf_i+0x144> 8016f94: 6823 ldr r3, [r4, #0] 8016f96: 07df lsls r7, r3, #31 8016f98: d508 bpl.n 8016fac <_printf_i+0x144> 8016f9a: 6923 ldr r3, [r4, #16] 8016f9c: 6861 ldr r1, [r4, #4] 8016f9e: 4299 cmp r1, r3 8016fa0: bfde ittt le 8016fa2: 2330 movle r3, #48 @ 0x30 8016fa4: f806 3c01 strble.w r3, [r6, #-1] 8016fa8: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 8016fac: 1b92 subs r2, r2, r6 8016fae: 6122 str r2, [r4, #16] 8016fb0: f8cd a000 str.w sl, [sp] 8016fb4: 464b mov r3, r9 8016fb6: aa03 add r2, sp, #12 8016fb8: 4621 mov r1, r4 8016fba: 4640 mov r0, r8 8016fbc: f7ff fee6 bl 8016d8c <_printf_common> 8016fc0: 3001 adds r0, #1 8016fc2: d14a bne.n 801705a <_printf_i+0x1f2> 8016fc4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016fc8: b004 add sp, #16 8016fca: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8016fce: 6823 ldr r3, [r4, #0] 8016fd0: f043 0320 orr.w r3, r3, #32 8016fd4: 6023 str r3, [r4, #0] 8016fd6: 4833 ldr r0, [pc, #204] @ (80170a4 <_printf_i+0x23c>) 8016fd8: 2778 movs r7, #120 @ 0x78 8016fda: f884 7045 strb.w r7, [r4, #69] @ 0x45 8016fde: 6823 ldr r3, [r4, #0] 8016fe0: 6831 ldr r1, [r6, #0] 8016fe2: 061f lsls r7, r3, #24 8016fe4: f851 5b04 ldr.w r5, [r1], #4 8016fe8: d402 bmi.n 8016ff0 <_printf_i+0x188> 8016fea: 065f lsls r7, r3, #25 8016fec: bf48 it mi 8016fee: b2ad uxthmi r5, r5 8016ff0: 6031 str r1, [r6, #0] 8016ff2: 07d9 lsls r1, r3, #31 8016ff4: bf44 itt mi 8016ff6: f043 0320 orrmi.w r3, r3, #32 8016ffa: 6023 strmi r3, [r4, #0] 8016ffc: b11d cbz r5, 8017006 <_printf_i+0x19e> 8016ffe: 2310 movs r3, #16 8017000: e7ac b.n 8016f5c <_printf_i+0xf4> 8017002: 4827 ldr r0, [pc, #156] @ (80170a0 <_printf_i+0x238>) 8017004: e7e9 b.n 8016fda <_printf_i+0x172> 8017006: 6823 ldr r3, [r4, #0] 8017008: f023 0320 bic.w r3, r3, #32 801700c: 6023 str r3, [r4, #0] 801700e: e7f6 b.n 8016ffe <_printf_i+0x196> 8017010: 4616 mov r6, r2 8017012: e7bd b.n 8016f90 <_printf_i+0x128> 8017014: 6833 ldr r3, [r6, #0] 8017016: 6825 ldr r5, [r4, #0] 8017018: 6961 ldr r1, [r4, #20] 801701a: 1d18 adds r0, r3, #4 801701c: 6030 str r0, [r6, #0] 801701e: 062e lsls r6, r5, #24 8017020: 681b ldr r3, [r3, #0] 8017022: d501 bpl.n 8017028 <_printf_i+0x1c0> 8017024: 6019 str r1, [r3, #0] 8017026: e002 b.n 801702e <_printf_i+0x1c6> 8017028: 0668 lsls r0, r5, #25 801702a: d5fb bpl.n 8017024 <_printf_i+0x1bc> 801702c: 8019 strh r1, [r3, #0] 801702e: 2300 movs r3, #0 8017030: 6123 str r3, [r4, #16] 8017032: 4616 mov r6, r2 8017034: e7bc b.n 8016fb0 <_printf_i+0x148> 8017036: 6833 ldr r3, [r6, #0] 8017038: 1d1a adds r2, r3, #4 801703a: 6032 str r2, [r6, #0] 801703c: 681e ldr r6, [r3, #0] 801703e: 6862 ldr r2, [r4, #4] 8017040: 2100 movs r1, #0 8017042: 4630 mov r0, r6 8017044: f7e9 f94c bl 80002e0 8017048: b108 cbz r0, 801704e <_printf_i+0x1e6> 801704a: 1b80 subs r0, r0, r6 801704c: 6060 str r0, [r4, #4] 801704e: 6863 ldr r3, [r4, #4] 8017050: 6123 str r3, [r4, #16] 8017052: 2300 movs r3, #0 8017054: f884 3043 strb.w r3, [r4, #67] @ 0x43 8017058: e7aa b.n 8016fb0 <_printf_i+0x148> 801705a: 6923 ldr r3, [r4, #16] 801705c: 4632 mov r2, r6 801705e: 4649 mov r1, r9 8017060: 4640 mov r0, r8 8017062: 47d0 blx sl 8017064: 3001 adds r0, #1 8017066: d0ad beq.n 8016fc4 <_printf_i+0x15c> 8017068: 6823 ldr r3, [r4, #0] 801706a: 079b lsls r3, r3, #30 801706c: d413 bmi.n 8017096 <_printf_i+0x22e> 801706e: 68e0 ldr r0, [r4, #12] 8017070: 9b03 ldr r3, [sp, #12] 8017072: 4298 cmp r0, r3 8017074: bfb8 it lt 8017076: 4618 movlt r0, r3 8017078: e7a6 b.n 8016fc8 <_printf_i+0x160> 801707a: 2301 movs r3, #1 801707c: 4632 mov r2, r6 801707e: 4649 mov r1, r9 8017080: 4640 mov r0, r8 8017082: 47d0 blx sl 8017084: 3001 adds r0, #1 8017086: d09d beq.n 8016fc4 <_printf_i+0x15c> 8017088: 3501 adds r5, #1 801708a: 68e3 ldr r3, [r4, #12] 801708c: 9903 ldr r1, [sp, #12] 801708e: 1a5b subs r3, r3, r1 8017090: 42ab cmp r3, r5 8017092: dcf2 bgt.n 801707a <_printf_i+0x212> 8017094: e7eb b.n 801706e <_printf_i+0x206> 8017096: 2500 movs r5, #0 8017098: f104 0619 add.w r6, r4, #25 801709c: e7f5 b.n 801708a <_printf_i+0x222> 801709e: bf00 nop 80170a0: 08017619 .word 0x08017619 80170a4: 0801762a .word 0x0801762a 080170a8 <__sflush_r>: 80170a8: f9b1 200c ldrsh.w r2, [r1, #12] 80170ac: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80170b0: 0716 lsls r6, r2, #28 80170b2: 4605 mov r5, r0 80170b4: 460c mov r4, r1 80170b6: d454 bmi.n 8017162 <__sflush_r+0xba> 80170b8: 684b ldr r3, [r1, #4] 80170ba: 2b00 cmp r3, #0 80170bc: dc02 bgt.n 80170c4 <__sflush_r+0x1c> 80170be: 6c0b ldr r3, [r1, #64] @ 0x40 80170c0: 2b00 cmp r3, #0 80170c2: dd48 ble.n 8017156 <__sflush_r+0xae> 80170c4: 6ae6 ldr r6, [r4, #44] @ 0x2c 80170c6: 2e00 cmp r6, #0 80170c8: d045 beq.n 8017156 <__sflush_r+0xae> 80170ca: 2300 movs r3, #0 80170cc: f412 5280 ands.w r2, r2, #4096 @ 0x1000 80170d0: 682f ldr r7, [r5, #0] 80170d2: 6a21 ldr r1, [r4, #32] 80170d4: 602b str r3, [r5, #0] 80170d6: d030 beq.n 801713a <__sflush_r+0x92> 80170d8: 6d62 ldr r2, [r4, #84] @ 0x54 80170da: 89a3 ldrh r3, [r4, #12] 80170dc: 0759 lsls r1, r3, #29 80170de: d505 bpl.n 80170ec <__sflush_r+0x44> 80170e0: 6863 ldr r3, [r4, #4] 80170e2: 1ad2 subs r2, r2, r3 80170e4: 6b63 ldr r3, [r4, #52] @ 0x34 80170e6: b10b cbz r3, 80170ec <__sflush_r+0x44> 80170e8: 6c23 ldr r3, [r4, #64] @ 0x40 80170ea: 1ad2 subs r2, r2, r3 80170ec: 2300 movs r3, #0 80170ee: 6ae6 ldr r6, [r4, #44] @ 0x2c 80170f0: 6a21 ldr r1, [r4, #32] 80170f2: 4628 mov r0, r5 80170f4: 47b0 blx r6 80170f6: 1c43 adds r3, r0, #1 80170f8: 89a3 ldrh r3, [r4, #12] 80170fa: d106 bne.n 801710a <__sflush_r+0x62> 80170fc: 6829 ldr r1, [r5, #0] 80170fe: 291d cmp r1, #29 8017100: d82b bhi.n 801715a <__sflush_r+0xb2> 8017102: 4a2a ldr r2, [pc, #168] @ (80171ac <__sflush_r+0x104>) 8017104: 410a asrs r2, r1 8017106: 07d6 lsls r6, r2, #31 8017108: d427 bmi.n 801715a <__sflush_r+0xb2> 801710a: 2200 movs r2, #0 801710c: 6062 str r2, [r4, #4] 801710e: 04d9 lsls r1, r3, #19 8017110: 6922 ldr r2, [r4, #16] 8017112: 6022 str r2, [r4, #0] 8017114: d504 bpl.n 8017120 <__sflush_r+0x78> 8017116: 1c42 adds r2, r0, #1 8017118: d101 bne.n 801711e <__sflush_r+0x76> 801711a: 682b ldr r3, [r5, #0] 801711c: b903 cbnz r3, 8017120 <__sflush_r+0x78> 801711e: 6560 str r0, [r4, #84] @ 0x54 8017120: 6b61 ldr r1, [r4, #52] @ 0x34 8017122: 602f str r7, [r5, #0] 8017124: b1b9 cbz r1, 8017156 <__sflush_r+0xae> 8017126: f104 0344 add.w r3, r4, #68 @ 0x44 801712a: 4299 cmp r1, r3 801712c: d002 beq.n 8017134 <__sflush_r+0x8c> 801712e: 4628 mov r0, r5 8017130: f7ff fbf2 bl 8016918 <_free_r> 8017134: 2300 movs r3, #0 8017136: 6363 str r3, [r4, #52] @ 0x34 8017138: e00d b.n 8017156 <__sflush_r+0xae> 801713a: 2301 movs r3, #1 801713c: 4628 mov r0, r5 801713e: 47b0 blx r6 8017140: 4602 mov r2, r0 8017142: 1c50 adds r0, r2, #1 8017144: d1c9 bne.n 80170da <__sflush_r+0x32> 8017146: 682b ldr r3, [r5, #0] 8017148: 2b00 cmp r3, #0 801714a: d0c6 beq.n 80170da <__sflush_r+0x32> 801714c: 2b1d cmp r3, #29 801714e: d001 beq.n 8017154 <__sflush_r+0xac> 8017150: 2b16 cmp r3, #22 8017152: d11e bne.n 8017192 <__sflush_r+0xea> 8017154: 602f str r7, [r5, #0] 8017156: 2000 movs r0, #0 8017158: e022 b.n 80171a0 <__sflush_r+0xf8> 801715a: f043 0340 orr.w r3, r3, #64 @ 0x40 801715e: b21b sxth r3, r3 8017160: e01b b.n 801719a <__sflush_r+0xf2> 8017162: 690f ldr r7, [r1, #16] 8017164: 2f00 cmp r7, #0 8017166: d0f6 beq.n 8017156 <__sflush_r+0xae> 8017168: 0793 lsls r3, r2, #30 801716a: 680e ldr r6, [r1, #0] 801716c: bf08 it eq 801716e: 694b ldreq r3, [r1, #20] 8017170: 600f str r7, [r1, #0] 8017172: bf18 it ne 8017174: 2300 movne r3, #0 8017176: eba6 0807 sub.w r8, r6, r7 801717a: 608b str r3, [r1, #8] 801717c: f1b8 0f00 cmp.w r8, #0 8017180: dde9 ble.n 8017156 <__sflush_r+0xae> 8017182: 6a21 ldr r1, [r4, #32] 8017184: 6aa6 ldr r6, [r4, #40] @ 0x28 8017186: 4643 mov r3, r8 8017188: 463a mov r2, r7 801718a: 4628 mov r0, r5 801718c: 47b0 blx r6 801718e: 2800 cmp r0, #0 8017190: dc08 bgt.n 80171a4 <__sflush_r+0xfc> 8017192: f9b4 300c ldrsh.w r3, [r4, #12] 8017196: f043 0340 orr.w r3, r3, #64 @ 0x40 801719a: 81a3 strh r3, [r4, #12] 801719c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80171a0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80171a4: 4407 add r7, r0 80171a6: eba8 0800 sub.w r8, r8, r0 80171aa: e7e7 b.n 801717c <__sflush_r+0xd4> 80171ac: dfbffffe .word 0xdfbffffe 080171b0 <_fflush_r>: 80171b0: b538 push {r3, r4, r5, lr} 80171b2: 690b ldr r3, [r1, #16] 80171b4: 4605 mov r5, r0 80171b6: 460c mov r4, r1 80171b8: b913 cbnz r3, 80171c0 <_fflush_r+0x10> 80171ba: 2500 movs r5, #0 80171bc: 4628 mov r0, r5 80171be: bd38 pop {r3, r4, r5, pc} 80171c0: b118 cbz r0, 80171ca <_fflush_r+0x1a> 80171c2: 6a03 ldr r3, [r0, #32] 80171c4: b90b cbnz r3, 80171ca <_fflush_r+0x1a> 80171c6: f7ff fa3b bl 8016640 <__sinit> 80171ca: f9b4 300c ldrsh.w r3, [r4, #12] 80171ce: 2b00 cmp r3, #0 80171d0: d0f3 beq.n 80171ba <_fflush_r+0xa> 80171d2: 6e62 ldr r2, [r4, #100] @ 0x64 80171d4: 07d0 lsls r0, r2, #31 80171d6: d404 bmi.n 80171e2 <_fflush_r+0x32> 80171d8: 0599 lsls r1, r3, #22 80171da: d402 bmi.n 80171e2 <_fflush_r+0x32> 80171dc: 6da0 ldr r0, [r4, #88] @ 0x58 80171de: f7ff fb8a bl 80168f6 <__retarget_lock_acquire_recursive> 80171e2: 4628 mov r0, r5 80171e4: 4621 mov r1, r4 80171e6: f7ff ff5f bl 80170a8 <__sflush_r> 80171ea: 6e63 ldr r3, [r4, #100] @ 0x64 80171ec: 07da lsls r2, r3, #31 80171ee: 4605 mov r5, r0 80171f0: d4e4 bmi.n 80171bc <_fflush_r+0xc> 80171f2: 89a3 ldrh r3, [r4, #12] 80171f4: 059b lsls r3, r3, #22 80171f6: d4e1 bmi.n 80171bc <_fflush_r+0xc> 80171f8: 6da0 ldr r0, [r4, #88] @ 0x58 80171fa: f7ff fb7d bl 80168f8 <__retarget_lock_release_recursive> 80171fe: e7dd b.n 80171bc <_fflush_r+0xc> 08017200 <__swbuf_r>: 8017200: b5f8 push {r3, r4, r5, r6, r7, lr} 8017202: 460e mov r6, r1 8017204: 4614 mov r4, r2 8017206: 4605 mov r5, r0 8017208: b118 cbz r0, 8017212 <__swbuf_r+0x12> 801720a: 6a03 ldr r3, [r0, #32] 801720c: b90b cbnz r3, 8017212 <__swbuf_r+0x12> 801720e: f7ff fa17 bl 8016640 <__sinit> 8017212: 69a3 ldr r3, [r4, #24] 8017214: 60a3 str r3, [r4, #8] 8017216: 89a3 ldrh r3, [r4, #12] 8017218: 071a lsls r2, r3, #28 801721a: d501 bpl.n 8017220 <__swbuf_r+0x20> 801721c: 6923 ldr r3, [r4, #16] 801721e: b943 cbnz r3, 8017232 <__swbuf_r+0x32> 8017220: 4621 mov r1, r4 8017222: 4628 mov r0, r5 8017224: f000 f82a bl 801727c <__swsetup_r> 8017228: b118 cbz r0, 8017232 <__swbuf_r+0x32> 801722a: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff 801722e: 4638 mov r0, r7 8017230: bdf8 pop {r3, r4, r5, r6, r7, pc} 8017232: 6823 ldr r3, [r4, #0] 8017234: 6922 ldr r2, [r4, #16] 8017236: 1a98 subs r0, r3, r2 8017238: 6963 ldr r3, [r4, #20] 801723a: b2f6 uxtb r6, r6 801723c: 4283 cmp r3, r0 801723e: 4637 mov r7, r6 8017240: dc05 bgt.n 801724e <__swbuf_r+0x4e> 8017242: 4621 mov r1, r4 8017244: 4628 mov r0, r5 8017246: f7ff ffb3 bl 80171b0 <_fflush_r> 801724a: 2800 cmp r0, #0 801724c: d1ed bne.n 801722a <__swbuf_r+0x2a> 801724e: 68a3 ldr r3, [r4, #8] 8017250: 3b01 subs r3, #1 8017252: 60a3 str r3, [r4, #8] 8017254: 6823 ldr r3, [r4, #0] 8017256: 1c5a adds r2, r3, #1 8017258: 6022 str r2, [r4, #0] 801725a: 701e strb r6, [r3, #0] 801725c: 6962 ldr r2, [r4, #20] 801725e: 1c43 adds r3, r0, #1 8017260: 429a cmp r2, r3 8017262: d004 beq.n 801726e <__swbuf_r+0x6e> 8017264: 89a3 ldrh r3, [r4, #12] 8017266: 07db lsls r3, r3, #31 8017268: d5e1 bpl.n 801722e <__swbuf_r+0x2e> 801726a: 2e0a cmp r6, #10 801726c: d1df bne.n 801722e <__swbuf_r+0x2e> 801726e: 4621 mov r1, r4 8017270: 4628 mov r0, r5 8017272: f7ff ff9d bl 80171b0 <_fflush_r> 8017276: 2800 cmp r0, #0 8017278: d0d9 beq.n 801722e <__swbuf_r+0x2e> 801727a: e7d6 b.n 801722a <__swbuf_r+0x2a> 0801727c <__swsetup_r>: 801727c: b538 push {r3, r4, r5, lr} 801727e: 4b29 ldr r3, [pc, #164] @ (8017324 <__swsetup_r+0xa8>) 8017280: 4605 mov r5, r0 8017282: 6818 ldr r0, [r3, #0] 8017284: 460c mov r4, r1 8017286: b118 cbz r0, 8017290 <__swsetup_r+0x14> 8017288: 6a03 ldr r3, [r0, #32] 801728a: b90b cbnz r3, 8017290 <__swsetup_r+0x14> 801728c: f7ff f9d8 bl 8016640 <__sinit> 8017290: f9b4 300c ldrsh.w r3, [r4, #12] 8017294: 0719 lsls r1, r3, #28 8017296: d422 bmi.n 80172de <__swsetup_r+0x62> 8017298: 06da lsls r2, r3, #27 801729a: d407 bmi.n 80172ac <__swsetup_r+0x30> 801729c: 2209 movs r2, #9 801729e: 602a str r2, [r5, #0] 80172a0: f043 0340 orr.w r3, r3, #64 @ 0x40 80172a4: 81a3 strh r3, [r4, #12] 80172a6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80172aa: e033 b.n 8017314 <__swsetup_r+0x98> 80172ac: 0758 lsls r0, r3, #29 80172ae: d512 bpl.n 80172d6 <__swsetup_r+0x5a> 80172b0: 6b61 ldr r1, [r4, #52] @ 0x34 80172b2: b141 cbz r1, 80172c6 <__swsetup_r+0x4a> 80172b4: f104 0344 add.w r3, r4, #68 @ 0x44 80172b8: 4299 cmp r1, r3 80172ba: d002 beq.n 80172c2 <__swsetup_r+0x46> 80172bc: 4628 mov r0, r5 80172be: f7ff fb2b bl 8016918 <_free_r> 80172c2: 2300 movs r3, #0 80172c4: 6363 str r3, [r4, #52] @ 0x34 80172c6: 89a3 ldrh r3, [r4, #12] 80172c8: f023 0324 bic.w r3, r3, #36 @ 0x24 80172cc: 81a3 strh r3, [r4, #12] 80172ce: 2300 movs r3, #0 80172d0: 6063 str r3, [r4, #4] 80172d2: 6923 ldr r3, [r4, #16] 80172d4: 6023 str r3, [r4, #0] 80172d6: 89a3 ldrh r3, [r4, #12] 80172d8: f043 0308 orr.w r3, r3, #8 80172dc: 81a3 strh r3, [r4, #12] 80172de: 6923 ldr r3, [r4, #16] 80172e0: b94b cbnz r3, 80172f6 <__swsetup_r+0x7a> 80172e2: 89a3 ldrh r3, [r4, #12] 80172e4: f403 7320 and.w r3, r3, #640 @ 0x280 80172e8: f5b3 7f00 cmp.w r3, #512 @ 0x200 80172ec: d003 beq.n 80172f6 <__swsetup_r+0x7a> 80172ee: 4621 mov r1, r4 80172f0: 4628 mov r0, r5 80172f2: f000 f84f bl 8017394 <__smakebuf_r> 80172f6: f9b4 300c ldrsh.w r3, [r4, #12] 80172fa: f013 0201 ands.w r2, r3, #1 80172fe: d00a beq.n 8017316 <__swsetup_r+0x9a> 8017300: 2200 movs r2, #0 8017302: 60a2 str r2, [r4, #8] 8017304: 6962 ldr r2, [r4, #20] 8017306: 4252 negs r2, r2 8017308: 61a2 str r2, [r4, #24] 801730a: 6922 ldr r2, [r4, #16] 801730c: b942 cbnz r2, 8017320 <__swsetup_r+0xa4> 801730e: f013 0080 ands.w r0, r3, #128 @ 0x80 8017312: d1c5 bne.n 80172a0 <__swsetup_r+0x24> 8017314: bd38 pop {r3, r4, r5, pc} 8017316: 0799 lsls r1, r3, #30 8017318: bf58 it pl 801731a: 6962 ldrpl r2, [r4, #20] 801731c: 60a2 str r2, [r4, #8] 801731e: e7f4 b.n 801730a <__swsetup_r+0x8e> 8017320: 2000 movs r0, #0 8017322: e7f7 b.n 8017314 <__swsetup_r+0x98> 8017324: 24000054 .word 0x24000054 08017328 <_sbrk_r>: 8017328: b538 push {r3, r4, r5, lr} 801732a: 4d06 ldr r5, [pc, #24] @ (8017344 <_sbrk_r+0x1c>) 801732c: 2300 movs r3, #0 801732e: 4604 mov r4, r0 8017330: 4608 mov r0, r1 8017332: 602b str r3, [r5, #0] 8017334: f7ec fb42 bl 80039bc <_sbrk> 8017338: 1c43 adds r3, r0, #1 801733a: d102 bne.n 8017342 <_sbrk_r+0x1a> 801733c: 682b ldr r3, [r5, #0] 801733e: b103 cbz r3, 8017342 <_sbrk_r+0x1a> 8017340: 6023 str r3, [r4, #0] 8017342: bd38 pop {r3, r4, r5, pc} 8017344: 24012d34 .word 0x24012d34 08017348 <__swhatbuf_r>: 8017348: b570 push {r4, r5, r6, lr} 801734a: 460c mov r4, r1 801734c: f9b1 100e ldrsh.w r1, [r1, #14] 8017350: 2900 cmp r1, #0 8017352: b096 sub sp, #88 @ 0x58 8017354: 4615 mov r5, r2 8017356: 461e mov r6, r3 8017358: da0d bge.n 8017376 <__swhatbuf_r+0x2e> 801735a: 89a3 ldrh r3, [r4, #12] 801735c: f013 0f80 tst.w r3, #128 @ 0x80 8017360: f04f 0100 mov.w r1, #0 8017364: bf14 ite ne 8017366: 2340 movne r3, #64 @ 0x40 8017368: f44f 6380 moveq.w r3, #1024 @ 0x400 801736c: 2000 movs r0, #0 801736e: 6031 str r1, [r6, #0] 8017370: 602b str r3, [r5, #0] 8017372: b016 add sp, #88 @ 0x58 8017374: bd70 pop {r4, r5, r6, pc} 8017376: 466a mov r2, sp 8017378: f000 f848 bl 801740c <_fstat_r> 801737c: 2800 cmp r0, #0 801737e: dbec blt.n 801735a <__swhatbuf_r+0x12> 8017380: 9901 ldr r1, [sp, #4] 8017382: f401 4170 and.w r1, r1, #61440 @ 0xf000 8017386: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 801738a: 4259 negs r1, r3 801738c: 4159 adcs r1, r3 801738e: f44f 6380 mov.w r3, #1024 @ 0x400 8017392: e7eb b.n 801736c <__swhatbuf_r+0x24> 08017394 <__smakebuf_r>: 8017394: 898b ldrh r3, [r1, #12] 8017396: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8017398: 079d lsls r5, r3, #30 801739a: 4606 mov r6, r0 801739c: 460c mov r4, r1 801739e: d507 bpl.n 80173b0 <__smakebuf_r+0x1c> 80173a0: f104 0347 add.w r3, r4, #71 @ 0x47 80173a4: 6023 str r3, [r4, #0] 80173a6: 6123 str r3, [r4, #16] 80173a8: 2301 movs r3, #1 80173aa: 6163 str r3, [r4, #20] 80173ac: b003 add sp, #12 80173ae: bdf0 pop {r4, r5, r6, r7, pc} 80173b0: ab01 add r3, sp, #4 80173b2: 466a mov r2, sp 80173b4: f7ff ffc8 bl 8017348 <__swhatbuf_r> 80173b8: 9f00 ldr r7, [sp, #0] 80173ba: 4605 mov r5, r0 80173bc: 4639 mov r1, r7 80173be: 4630 mov r0, r6 80173c0: f7ff fb16 bl 80169f0 <_malloc_r> 80173c4: b948 cbnz r0, 80173da <__smakebuf_r+0x46> 80173c6: f9b4 300c ldrsh.w r3, [r4, #12] 80173ca: 059a lsls r2, r3, #22 80173cc: d4ee bmi.n 80173ac <__smakebuf_r+0x18> 80173ce: f023 0303 bic.w r3, r3, #3 80173d2: f043 0302 orr.w r3, r3, #2 80173d6: 81a3 strh r3, [r4, #12] 80173d8: e7e2 b.n 80173a0 <__smakebuf_r+0xc> 80173da: 89a3 ldrh r3, [r4, #12] 80173dc: 6020 str r0, [r4, #0] 80173de: f043 0380 orr.w r3, r3, #128 @ 0x80 80173e2: 81a3 strh r3, [r4, #12] 80173e4: 9b01 ldr r3, [sp, #4] 80173e6: e9c4 0704 strd r0, r7, [r4, #16] 80173ea: b15b cbz r3, 8017404 <__smakebuf_r+0x70> 80173ec: f9b4 100e ldrsh.w r1, [r4, #14] 80173f0: 4630 mov r0, r6 80173f2: f000 f81d bl 8017430 <_isatty_r> 80173f6: b128 cbz r0, 8017404 <__smakebuf_r+0x70> 80173f8: 89a3 ldrh r3, [r4, #12] 80173fa: f023 0303 bic.w r3, r3, #3 80173fe: f043 0301 orr.w r3, r3, #1 8017402: 81a3 strh r3, [r4, #12] 8017404: 89a3 ldrh r3, [r4, #12] 8017406: 431d orrs r5, r3 8017408: 81a5 strh r5, [r4, #12] 801740a: e7cf b.n 80173ac <__smakebuf_r+0x18> 0801740c <_fstat_r>: 801740c: b538 push {r3, r4, r5, lr} 801740e: 4d07 ldr r5, [pc, #28] @ (801742c <_fstat_r+0x20>) 8017410: 2300 movs r3, #0 8017412: 4604 mov r4, r0 8017414: 4608 mov r0, r1 8017416: 4611 mov r1, r2 8017418: 602b str r3, [r5, #0] 801741a: f7ec faa6 bl 800396a <_fstat> 801741e: 1c43 adds r3, r0, #1 8017420: d102 bne.n 8017428 <_fstat_r+0x1c> 8017422: 682b ldr r3, [r5, #0] 8017424: b103 cbz r3, 8017428 <_fstat_r+0x1c> 8017426: 6023 str r3, [r4, #0] 8017428: bd38 pop {r3, r4, r5, pc} 801742a: bf00 nop 801742c: 24012d34 .word 0x24012d34 08017430 <_isatty_r>: 8017430: b538 push {r3, r4, r5, lr} 8017432: 4d06 ldr r5, [pc, #24] @ (801744c <_isatty_r+0x1c>) 8017434: 2300 movs r3, #0 8017436: 4604 mov r4, r0 8017438: 4608 mov r0, r1 801743a: 602b str r3, [r5, #0] 801743c: f7ec faa5 bl 800398a <_isatty> 8017440: 1c43 adds r3, r0, #1 8017442: d102 bne.n 801744a <_isatty_r+0x1a> 8017444: 682b ldr r3, [r5, #0] 8017446: b103 cbz r3, 801744a <_isatty_r+0x1a> 8017448: 6023 str r3, [r4, #0] 801744a: bd38 pop {r3, r4, r5, pc} 801744c: 24012d34 .word 0x24012d34 08017450 <_init>: 8017450: b5f8 push {r3, r4, r5, r6, r7, lr} 8017452: bf00 nop 8017454: bcf8 pop {r3, r4, r5, r6, r7} 8017456: bc08 pop {r3} 8017458: 469e mov lr, r3 801745a: 4770 bx lr 0801745c <_fini>: 801745c: b5f8 push {r3, r4, r5, r6, r7, lr} 801745e: bf00 nop 8017460: bcf8 pop {r3, r4, r5, r6, r7} 8017462: bc08 pop {r3} 8017464: 469e mov lr, r3 8017466: 4770 bx lr