OZE_Sensor.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000298 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00018380 080002a0 080002a0 000012a0 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000104 08018620 08018620 00019620 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM 00000008 08018724 08018724 00019724 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .init_array 00000004 0801872c 0801872c 0001972c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .fini_array 00000004 08018730 08018730 00019730 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 6 .data 00000098 24000000 08018734 0001a000 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .bss 000130ec 240000a0 080187cc 0001a0a0 2**5 ALLOC 8 ._user_heap_stack 00000604 2401318c 080187cc 0001a18c 2**0 ALLOC 9 .ARM.attributes 0000002e 00000000 00000000 0001a098 2**0 CONTENTS, READONLY 10 .debug_info 0003512f 00000000 00000000 0001a0c6 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_abbrev 00006447 00000000 00000000 0004f1f5 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_aranges 00002478 00000000 00000000 00055640 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_macro 0003ef04 00000000 00000000 00057ab8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_line 000317a8 00000000 00000000 000969bc 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_str 00186a01 00000000 00000000 000c8164 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .comment 00000043 00000000 00000000 0024eb65 2**0 CONTENTS, READONLY 17 .debug_rnglists 00001c1d 00000000 00000000 0024eba8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_frame 00009d14 00000000 00000000 002507c8 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_line_str 00000066 00000000 00000000 0025a4dc 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080002a0 <__do_global_dtors_aux>: 80002a0: b510 push {r4, lr} 80002a2: 4c05 ldr r4, [pc, #20] @ (80002b8 <__do_global_dtors_aux+0x18>) 80002a4: 7823 ldrb r3, [r4, #0] 80002a6: b933 cbnz r3, 80002b6 <__do_global_dtors_aux+0x16> 80002a8: 4b04 ldr r3, [pc, #16] @ (80002bc <__do_global_dtors_aux+0x1c>) 80002aa: b113 cbz r3, 80002b2 <__do_global_dtors_aux+0x12> 80002ac: 4804 ldr r0, [pc, #16] @ (80002c0 <__do_global_dtors_aux+0x20>) 80002ae: f3af 8000 nop.w 80002b2: 2301 movs r3, #1 80002b4: 7023 strb r3, [r4, #0] 80002b6: bd10 pop {r4, pc} 80002b8: 240000a0 .word 0x240000a0 80002bc: 00000000 .word 0x00000000 80002c0: 08018608 .word 0x08018608 080002c4 : 80002c4: b508 push {r3, lr} 80002c6: 4b03 ldr r3, [pc, #12] @ (80002d4 ) 80002c8: b11b cbz r3, 80002d2 80002ca: 4903 ldr r1, [pc, #12] @ (80002d8 ) 80002cc: 4803 ldr r0, [pc, #12] @ (80002dc ) 80002ce: f3af 8000 nop.w 80002d2: bd08 pop {r3, pc} 80002d4: 00000000 .word 0x00000000 80002d8: 240000a4 .word 0x240000a4 80002dc: 08018608 .word 0x08018608 080002e0 <__aeabi_uldivmod>: 80002e0: b953 cbnz r3, 80002f8 <__aeabi_uldivmod+0x18> 80002e2: b94a cbnz r2, 80002f8 <__aeabi_uldivmod+0x18> 80002e4: 2900 cmp r1, #0 80002e6: bf08 it eq 80002e8: 2800 cmpeq r0, #0 80002ea: bf1c itt ne 80002ec: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 80002f0: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 80002f4: f000 b96a b.w 80005cc <__aeabi_idiv0> 80002f8: f1ad 0c08 sub.w ip, sp, #8 80002fc: e96d ce04 strd ip, lr, [sp, #-16]! 8000300: f000 f806 bl 8000310 <__udivmoddi4> 8000304: f8dd e004 ldr.w lr, [sp, #4] 8000308: e9dd 2302 ldrd r2, r3, [sp, #8] 800030c: b004 add sp, #16 800030e: 4770 bx lr 08000310 <__udivmoddi4>: 8000310: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000314: 9d08 ldr r5, [sp, #32] 8000316: 460c mov r4, r1 8000318: 2b00 cmp r3, #0 800031a: d14e bne.n 80003ba <__udivmoddi4+0xaa> 800031c: 4694 mov ip, r2 800031e: 458c cmp ip, r1 8000320: 4686 mov lr, r0 8000322: fab2 f282 clz r2, r2 8000326: d962 bls.n 80003ee <__udivmoddi4+0xde> 8000328: b14a cbz r2, 800033e <__udivmoddi4+0x2e> 800032a: f1c2 0320 rsb r3, r2, #32 800032e: 4091 lsls r1, r2 8000330: fa20 f303 lsr.w r3, r0, r3 8000334: fa0c fc02 lsl.w ip, ip, r2 8000338: 4319 orrs r1, r3 800033a: fa00 fe02 lsl.w lr, r0, r2 800033e: ea4f 471c mov.w r7, ip, lsr #16 8000342: fa1f f68c uxth.w r6, ip 8000346: fbb1 f4f7 udiv r4, r1, r7 800034a: ea4f 431e mov.w r3, lr, lsr #16 800034e: fb07 1114 mls r1, r7, r4, r1 8000352: ea43 4301 orr.w r3, r3, r1, lsl #16 8000356: fb04 f106 mul.w r1, r4, r6 800035a: 4299 cmp r1, r3 800035c: d90a bls.n 8000374 <__udivmoddi4+0x64> 800035e: eb1c 0303 adds.w r3, ip, r3 8000362: f104 30ff add.w r0, r4, #4294967295 @ 0xffffffff 8000366: f080 8112 bcs.w 800058e <__udivmoddi4+0x27e> 800036a: 4299 cmp r1, r3 800036c: f240 810f bls.w 800058e <__udivmoddi4+0x27e> 8000370: 3c02 subs r4, #2 8000372: 4463 add r3, ip 8000374: 1a59 subs r1, r3, r1 8000376: fa1f f38e uxth.w r3, lr 800037a: fbb1 f0f7 udiv r0, r1, r7 800037e: fb07 1110 mls r1, r7, r0, r1 8000382: ea43 4301 orr.w r3, r3, r1, lsl #16 8000386: fb00 f606 mul.w r6, r0, r6 800038a: 429e cmp r6, r3 800038c: d90a bls.n 80003a4 <__udivmoddi4+0x94> 800038e: eb1c 0303 adds.w r3, ip, r3 8000392: f100 31ff add.w r1, r0, #4294967295 @ 0xffffffff 8000396: f080 80fc bcs.w 8000592 <__udivmoddi4+0x282> 800039a: 429e cmp r6, r3 800039c: f240 80f9 bls.w 8000592 <__udivmoddi4+0x282> 80003a0: 4463 add r3, ip 80003a2: 3802 subs r0, #2 80003a4: 1b9b subs r3, r3, r6 80003a6: ea40 4004 orr.w r0, r0, r4, lsl #16 80003aa: 2100 movs r1, #0 80003ac: b11d cbz r5, 80003b6 <__udivmoddi4+0xa6> 80003ae: 40d3 lsrs r3, r2 80003b0: 2200 movs r2, #0 80003b2: e9c5 3200 strd r3, r2, [r5] 80003b6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80003ba: 428b cmp r3, r1 80003bc: d905 bls.n 80003ca <__udivmoddi4+0xba> 80003be: b10d cbz r5, 80003c4 <__udivmoddi4+0xb4> 80003c0: e9c5 0100 strd r0, r1, [r5] 80003c4: 2100 movs r1, #0 80003c6: 4608 mov r0, r1 80003c8: e7f5 b.n 80003b6 <__udivmoddi4+0xa6> 80003ca: fab3 f183 clz r1, r3 80003ce: 2900 cmp r1, #0 80003d0: d146 bne.n 8000460 <__udivmoddi4+0x150> 80003d2: 42a3 cmp r3, r4 80003d4: d302 bcc.n 80003dc <__udivmoddi4+0xcc> 80003d6: 4290 cmp r0, r2 80003d8: f0c0 80f0 bcc.w 80005bc <__udivmoddi4+0x2ac> 80003dc: 1a86 subs r6, r0, r2 80003de: eb64 0303 sbc.w r3, r4, r3 80003e2: 2001 movs r0, #1 80003e4: 2d00 cmp r5, #0 80003e6: d0e6 beq.n 80003b6 <__udivmoddi4+0xa6> 80003e8: e9c5 6300 strd r6, r3, [r5] 80003ec: e7e3 b.n 80003b6 <__udivmoddi4+0xa6> 80003ee: 2a00 cmp r2, #0 80003f0: f040 8090 bne.w 8000514 <__udivmoddi4+0x204> 80003f4: eba1 040c sub.w r4, r1, ip 80003f8: ea4f 481c mov.w r8, ip, lsr #16 80003fc: fa1f f78c uxth.w r7, ip 8000400: 2101 movs r1, #1 8000402: fbb4 f6f8 udiv r6, r4, r8 8000406: ea4f 431e mov.w r3, lr, lsr #16 800040a: fb08 4416 mls r4, r8, r6, r4 800040e: ea43 4304 orr.w r3, r3, r4, lsl #16 8000412: fb07 f006 mul.w r0, r7, r6 8000416: 4298 cmp r0, r3 8000418: d908 bls.n 800042c <__udivmoddi4+0x11c> 800041a: eb1c 0303 adds.w r3, ip, r3 800041e: f106 34ff add.w r4, r6, #4294967295 @ 0xffffffff 8000422: d202 bcs.n 800042a <__udivmoddi4+0x11a> 8000424: 4298 cmp r0, r3 8000426: f200 80cd bhi.w 80005c4 <__udivmoddi4+0x2b4> 800042a: 4626 mov r6, r4 800042c: 1a1c subs r4, r3, r0 800042e: fa1f f38e uxth.w r3, lr 8000432: fbb4 f0f8 udiv r0, r4, r8 8000436: fb08 4410 mls r4, r8, r0, r4 800043a: ea43 4304 orr.w r3, r3, r4, lsl #16 800043e: fb00 f707 mul.w r7, r0, r7 8000442: 429f cmp r7, r3 8000444: d908 bls.n 8000458 <__udivmoddi4+0x148> 8000446: eb1c 0303 adds.w r3, ip, r3 800044a: f100 34ff add.w r4, r0, #4294967295 @ 0xffffffff 800044e: d202 bcs.n 8000456 <__udivmoddi4+0x146> 8000450: 429f cmp r7, r3 8000452: f200 80b0 bhi.w 80005b6 <__udivmoddi4+0x2a6> 8000456: 4620 mov r0, r4 8000458: 1bdb subs r3, r3, r7 800045a: ea40 4006 orr.w r0, r0, r6, lsl #16 800045e: e7a5 b.n 80003ac <__udivmoddi4+0x9c> 8000460: f1c1 0620 rsb r6, r1, #32 8000464: 408b lsls r3, r1 8000466: fa22 f706 lsr.w r7, r2, r6 800046a: 431f orrs r7, r3 800046c: fa20 fc06 lsr.w ip, r0, r6 8000470: fa04 f301 lsl.w r3, r4, r1 8000474: ea43 030c orr.w r3, r3, ip 8000478: 40f4 lsrs r4, r6 800047a: fa00 f801 lsl.w r8, r0, r1 800047e: 0c38 lsrs r0, r7, #16 8000480: ea4f 4913 mov.w r9, r3, lsr #16 8000484: fbb4 fef0 udiv lr, r4, r0 8000488: fa1f fc87 uxth.w ip, r7 800048c: fb00 441e mls r4, r0, lr, r4 8000490: ea49 4404 orr.w r4, r9, r4, lsl #16 8000494: fb0e f90c mul.w r9, lr, ip 8000498: 45a1 cmp r9, r4 800049a: fa02 f201 lsl.w r2, r2, r1 800049e: d90a bls.n 80004b6 <__udivmoddi4+0x1a6> 80004a0: 193c adds r4, r7, r4 80004a2: f10e 3aff add.w sl, lr, #4294967295 @ 0xffffffff 80004a6: f080 8084 bcs.w 80005b2 <__udivmoddi4+0x2a2> 80004aa: 45a1 cmp r9, r4 80004ac: f240 8081 bls.w 80005b2 <__udivmoddi4+0x2a2> 80004b0: f1ae 0e02 sub.w lr, lr, #2 80004b4: 443c add r4, r7 80004b6: eba4 0409 sub.w r4, r4, r9 80004ba: fa1f f983 uxth.w r9, r3 80004be: fbb4 f3f0 udiv r3, r4, r0 80004c2: fb00 4413 mls r4, r0, r3, r4 80004c6: ea49 4404 orr.w r4, r9, r4, lsl #16 80004ca: fb03 fc0c mul.w ip, r3, ip 80004ce: 45a4 cmp ip, r4 80004d0: d907 bls.n 80004e2 <__udivmoddi4+0x1d2> 80004d2: 193c adds r4, r7, r4 80004d4: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 80004d8: d267 bcs.n 80005aa <__udivmoddi4+0x29a> 80004da: 45a4 cmp ip, r4 80004dc: d965 bls.n 80005aa <__udivmoddi4+0x29a> 80004de: 3b02 subs r3, #2 80004e0: 443c add r4, r7 80004e2: ea43 400e orr.w r0, r3, lr, lsl #16 80004e6: fba0 9302 umull r9, r3, r0, r2 80004ea: eba4 040c sub.w r4, r4, ip 80004ee: 429c cmp r4, r3 80004f0: 46ce mov lr, r9 80004f2: 469c mov ip, r3 80004f4: d351 bcc.n 800059a <__udivmoddi4+0x28a> 80004f6: d04e beq.n 8000596 <__udivmoddi4+0x286> 80004f8: b155 cbz r5, 8000510 <__udivmoddi4+0x200> 80004fa: ebb8 030e subs.w r3, r8, lr 80004fe: eb64 040c sbc.w r4, r4, ip 8000502: fa04 f606 lsl.w r6, r4, r6 8000506: 40cb lsrs r3, r1 8000508: 431e orrs r6, r3 800050a: 40cc lsrs r4, r1 800050c: e9c5 6400 strd r6, r4, [r5] 8000510: 2100 movs r1, #0 8000512: e750 b.n 80003b6 <__udivmoddi4+0xa6> 8000514: f1c2 0320 rsb r3, r2, #32 8000518: fa20 f103 lsr.w r1, r0, r3 800051c: fa0c fc02 lsl.w ip, ip, r2 8000520: fa24 f303 lsr.w r3, r4, r3 8000524: 4094 lsls r4, r2 8000526: 430c orrs r4, r1 8000528: ea4f 481c mov.w r8, ip, lsr #16 800052c: fa00 fe02 lsl.w lr, r0, r2 8000530: fa1f f78c uxth.w r7, ip 8000534: fbb3 f0f8 udiv r0, r3, r8 8000538: fb08 3110 mls r1, r8, r0, r3 800053c: 0c23 lsrs r3, r4, #16 800053e: ea43 4301 orr.w r3, r3, r1, lsl #16 8000542: fb00 f107 mul.w r1, r0, r7 8000546: 4299 cmp r1, r3 8000548: d908 bls.n 800055c <__udivmoddi4+0x24c> 800054a: eb1c 0303 adds.w r3, ip, r3 800054e: f100 36ff add.w r6, r0, #4294967295 @ 0xffffffff 8000552: d22c bcs.n 80005ae <__udivmoddi4+0x29e> 8000554: 4299 cmp r1, r3 8000556: d92a bls.n 80005ae <__udivmoddi4+0x29e> 8000558: 3802 subs r0, #2 800055a: 4463 add r3, ip 800055c: 1a5b subs r3, r3, r1 800055e: b2a4 uxth r4, r4 8000560: fbb3 f1f8 udiv r1, r3, r8 8000564: fb08 3311 mls r3, r8, r1, r3 8000568: ea44 4403 orr.w r4, r4, r3, lsl #16 800056c: fb01 f307 mul.w r3, r1, r7 8000570: 42a3 cmp r3, r4 8000572: d908 bls.n 8000586 <__udivmoddi4+0x276> 8000574: eb1c 0404 adds.w r4, ip, r4 8000578: f101 36ff add.w r6, r1, #4294967295 @ 0xffffffff 800057c: d213 bcs.n 80005a6 <__udivmoddi4+0x296> 800057e: 42a3 cmp r3, r4 8000580: d911 bls.n 80005a6 <__udivmoddi4+0x296> 8000582: 3902 subs r1, #2 8000584: 4464 add r4, ip 8000586: 1ae4 subs r4, r4, r3 8000588: ea41 4100 orr.w r1, r1, r0, lsl #16 800058c: e739 b.n 8000402 <__udivmoddi4+0xf2> 800058e: 4604 mov r4, r0 8000590: e6f0 b.n 8000374 <__udivmoddi4+0x64> 8000592: 4608 mov r0, r1 8000594: e706 b.n 80003a4 <__udivmoddi4+0x94> 8000596: 45c8 cmp r8, r9 8000598: d2ae bcs.n 80004f8 <__udivmoddi4+0x1e8> 800059a: ebb9 0e02 subs.w lr, r9, r2 800059e: eb63 0c07 sbc.w ip, r3, r7 80005a2: 3801 subs r0, #1 80005a4: e7a8 b.n 80004f8 <__udivmoddi4+0x1e8> 80005a6: 4631 mov r1, r6 80005a8: e7ed b.n 8000586 <__udivmoddi4+0x276> 80005aa: 4603 mov r3, r0 80005ac: e799 b.n 80004e2 <__udivmoddi4+0x1d2> 80005ae: 4630 mov r0, r6 80005b0: e7d4 b.n 800055c <__udivmoddi4+0x24c> 80005b2: 46d6 mov lr, sl 80005b4: e77f b.n 80004b6 <__udivmoddi4+0x1a6> 80005b6: 4463 add r3, ip 80005b8: 3802 subs r0, #2 80005ba: e74d b.n 8000458 <__udivmoddi4+0x148> 80005bc: 4606 mov r6, r0 80005be: 4623 mov r3, r4 80005c0: 4608 mov r0, r1 80005c2: e70f b.n 80003e4 <__udivmoddi4+0xd4> 80005c4: 3e02 subs r6, #2 80005c6: 4463 add r3, ip 80005c8: e730 b.n 800042c <__udivmoddi4+0x11c> 80005ca: bf00 nop 080005cc <__aeabi_idiv0>: 80005cc: 4770 bx lr 80005ce: bf00 nop 080005d0 : /* Hook prototypes */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName); /* USER CODE BEGIN 4 */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName) { 80005d0: b480 push {r7} 80005d2: b083 sub sp, #12 80005d4: af00 add r7, sp, #0 80005d6: 6078 str r0, [r7, #4] 80005d8: 6039 str r1, [r7, #0] /* Run time stack overflow checking is performed if configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is called if a stack overflow is detected. */ } 80005da: bf00 nop 80005dc: 370c adds r7, #12 80005de: 46bd mov sp, r7 80005e0: f85d 7b04 ldr.w r7, [sp], #4 80005e4: 4770 bx lr ... 080005e8 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 80005e8: b480 push {r7} 80005ea: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 80005ec: f3bf 8f4f dsb sy } 80005f0: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 80005f2: 4b06 ldr r3, [pc, #24] @ (800060c <__NVIC_SystemReset+0x24>) 80005f4: 68db ldr r3, [r3, #12] 80005f6: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80005fa: 4904 ldr r1, [pc, #16] @ (800060c <__NVIC_SystemReset+0x24>) 80005fc: 4b04 ldr r3, [pc, #16] @ (8000610 <__NVIC_SystemReset+0x28>) 80005fe: 4313 orrs r3, r2 8000600: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 8000602: f3bf 8f4f dsb sy } 8000606: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 8000608: bf00 nop 800060a: e7fd b.n 8000608 <__NVIC_SystemReset+0x20> 800060c: e000ed00 .word 0xe000ed00 8000610: 05fa0004 .word 0x05fa0004 08000614 : #endif return ch; } void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 8000614: b580 push {r7, lr} 8000616: b084 sub sp, #16 8000618: af00 add r7, sp, #0 800061a: 4603 mov r3, r0 800061c: 80fb strh r3, [r7, #6] LimiterSwitchData limiterSwitchData = { 0 }; 800061e: 2300 movs r3, #0 8000620: 60fb str r3, [r7, #12] limiterSwitchData.gpioPin = GPIO_Pin; 8000622: 88fb ldrh r3, [r7, #6] 8000624: 81bb strh r3, [r7, #12] limiterSwitchData.pinState = HAL_GPIO_ReadPin(GPIOD, GPIO_Pin); 8000626: 88fb ldrh r3, [r7, #6] 8000628: 4619 mov r1, r3 800062a: 4808 ldr r0, [pc, #32] @ (800064c ) 800062c: f00a ff6e bl 800b50c 8000630: 4603 mov r3, r0 8000632: 73bb strb r3, [r7, #14] osMessageQueuePut(limiterSwitchDataQueue, &limiterSwitchData, 0, 0); 8000634: 4b06 ldr r3, [pc, #24] @ (8000650 ) 8000636: 6818 ldr r0, [r3, #0] 8000638: f107 010c add.w r1, r7, #12 800063c: 2300 movs r3, #0 800063e: 2200 movs r2, #0 8000640: f014 f824 bl 801468c } 8000644: bf00 nop 8000646: 3710 adds r7, #16 8000648: 46bd mov sp, r7 800064a: bd80 pop {r7, pc} 800064c: 58020c00 .word 0x58020c00 8000650: 2400080c .word 0x2400080c 08000654
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000654: b580 push {r7, lr} 8000656: b084 sub sp, #16 8000658: af00 add r7, sp, #0 /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MPU Configuration--------------------------------------------------------*/ MPU_Config(); 800065a: f001 fbb1 bl 8001dc0 \details Turns on I-Cache */ __STATIC_FORCEINLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 800065e: 4b64 ldr r3, [pc, #400] @ (80007f0 ) 8000660: 695b ldr r3, [r3, #20] 8000662: f403 3300 and.w r3, r3, #131072 @ 0x20000 8000666: 2b00 cmp r3, #0 8000668: d11b bne.n 80006a2 __ASM volatile ("dsb 0xF":::"memory"); 800066a: f3bf 8f4f dsb sy } 800066e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000670: f3bf 8f6f isb sy } 8000674: bf00 nop __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 8000676: 4b5e ldr r3, [pc, #376] @ (80007f0 ) 8000678: 2200 movs r2, #0 800067a: f8c3 2250 str.w r2, [r3, #592] @ 0x250 __ASM volatile ("dsb 0xF":::"memory"); 800067e: f3bf 8f4f dsb sy } 8000682: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000684: f3bf 8f6f isb sy } 8000688: bf00 nop __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 800068a: 4b59 ldr r3, [pc, #356] @ (80007f0 ) 800068c: 695b ldr r3, [r3, #20] 800068e: 4a58 ldr r2, [pc, #352] @ (80007f0 ) 8000690: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8000694: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 8000696: f3bf 8f4f dsb sy } 800069a: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 800069c: f3bf 8f6f isb sy } 80006a0: e000 b.n 80006a4 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 80006a2: bf00 nop #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 80006a4: 4b52 ldr r3, [pc, #328] @ (80007f0 ) 80006a6: 695b ldr r3, [r3, #20] 80006a8: f403 3380 and.w r3, r3, #65536 @ 0x10000 80006ac: 2b00 cmp r3, #0 80006ae: d138 bne.n 8000722 SCB->CSSELR = 0U; /* select Level 1 data cache */ 80006b0: 4b4f ldr r3, [pc, #316] @ (80007f0 ) 80006b2: 2200 movs r2, #0 80006b4: f8c3 2084 str.w r2, [r3, #132] @ 0x84 __ASM volatile ("dsb 0xF":::"memory"); 80006b8: f3bf 8f4f dsb sy } 80006bc: bf00 nop __DSB(); ccsidr = SCB->CCSIDR; 80006be: 4b4c ldr r3, [pc, #304] @ (80007f0 ) 80006c0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80006c4: 60fb str r3, [r7, #12] /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 80006c6: 68fb ldr r3, [r7, #12] 80006c8: 0b5b lsrs r3, r3, #13 80006ca: f3c3 030e ubfx r3, r3, #0, #15 80006ce: 60bb str r3, [r7, #8] do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 80006d0: 68fb ldr r3, [r7, #12] 80006d2: 08db lsrs r3, r3, #3 80006d4: f3c3 0309 ubfx r3, r3, #0, #10 80006d8: 607b str r3, [r7, #4] do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 80006da: 68bb ldr r3, [r7, #8] 80006dc: 015a lsls r2, r3, #5 80006de: f643 73e0 movw r3, #16352 @ 0x3fe0 80006e2: 4013 ands r3, r2 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 80006e4: 687a ldr r2, [r7, #4] 80006e6: 0792 lsls r2, r2, #30 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 80006e8: 4941 ldr r1, [pc, #260] @ (80007f0 ) 80006ea: 4313 orrs r3, r2 80006ec: f8c1 3260 str.w r3, [r1, #608] @ 0x260 #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); 80006f0: 687b ldr r3, [r7, #4] 80006f2: 1e5a subs r2, r3, #1 80006f4: 607a str r2, [r7, #4] 80006f6: 2b00 cmp r3, #0 80006f8: d1ef bne.n 80006da } while(sets-- != 0U); 80006fa: 68bb ldr r3, [r7, #8] 80006fc: 1e5a subs r2, r3, #1 80006fe: 60ba str r2, [r7, #8] 8000700: 2b00 cmp r3, #0 8000702: d1e5 bne.n 80006d0 __ASM volatile ("dsb 0xF":::"memory"); 8000704: f3bf 8f4f dsb sy } 8000708: bf00 nop __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 800070a: 4b39 ldr r3, [pc, #228] @ (80007f0 ) 800070c: 695b ldr r3, [r3, #20] 800070e: 4a38 ldr r2, [pc, #224] @ (80007f0 ) 8000710: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8000714: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 8000716: f3bf 8f4f dsb sy } 800071a: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 800071c: f3bf 8f6f isb sy } 8000720: e000 b.n 8000724 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 8000722: bf00 nop SCB_EnableDCache(); /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000724: f005 fb1a bl 8005d5c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000728: f000 f884 bl 8000834 /* Configure the peripherals common clocks */ PeriphCommonClock_Config(); 800072c: f000 f900 bl 8000930 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000730: f000 ff88 bl 8001644 MX_DMA_Init(); 8000734: f000 ff56 bl 80015e4 MX_RNG_Init(); 8000738: f000 fc08 bl 8000f4c MX_USART1_UART_Init(); 800073c: f000 ff02 bl 8001544 MX_ADC1_Init(); 8000740: f000 f926 bl 8000990 MX_UART8_Init(); 8000744: f000 feb2 bl 80014ac MX_CRC_Init(); 8000748: f000 fb7e bl 8000e48 MX_ADC2_Init(); 800074c: f000 fa0a bl 8000b64 MX_ADC3_Init(); 8000750: f000 fa9c bl 8000c8c MX_TIM2_Init(); 8000754: f000 fcac bl 80010b0 MX_TIM1_Init(); 8000758: f000 fc0e bl 8000f78 MX_TIM3_Init(); 800075c: f000 fd26 bl 80011ac MX_DAC1_Init(); 8000760: f000 fb9c bl 8000e9c MX_COMP1_Init(); 8000764: f000 fb42 bl 8000dec MX_TIM4_Init(); 8000768: f000 fdcc bl 8001304 MX_TIM8_Init(); 800076c: f000 fe48 bl 8001400 #ifdef WATCHDOG_ENABLED MX_IWDG1_Init(); 8000770: f000 fbd0 bl 8000f14 #endif /* USER CODE BEGIN 2 */ #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8000774: 481f ldr r0, [pc, #124] @ (80007f4 ) 8000776: f00a ff7d bl 800b674 #endif /* USER CODE END 2 */ /* Init scheduler */ osKernelInitialize(); 800077a: f013 fc17 bl 8013fac /* add semaphores, ... */ /* USER CODE END RTOS_SEMAPHORES */ /* Create the timer(s) */ /* creation of debugLedTimer */ debugLedTimerHandle = osTimerNew(debugLedTimerCallback, osTimerOnce, NULL, &debugLedTimer_attributes); 800077e: 4b1e ldr r3, [pc, #120] @ (80007f8 ) 8000780: 2200 movs r2, #0 8000782: 2100 movs r1, #0 8000784: 481d ldr r0, [pc, #116] @ (80007fc ) 8000786: f013 fd1f bl 80141c8 800078a: 4603 mov r3, r0 800078c: 4a1c ldr r2, [pc, #112] @ (8000800 ) 800078e: 6013 str r3, [r2, #0] /* creation of fanTimer */ fanTimerHandle = osTimerNew(fanTimerCallback, osTimerOnce, NULL, &fanTimer_attributes); 8000790: 4b1c ldr r3, [pc, #112] @ (8000804 ) 8000792: 2200 movs r2, #0 8000794: 2100 movs r1, #0 8000796: 481c ldr r0, [pc, #112] @ (8000808 ) 8000798: f013 fd16 bl 80141c8 800079c: 4603 mov r3, r0 800079e: 4a1b ldr r2, [pc, #108] @ (800080c ) 80007a0: 6013 str r3, [r2, #0] /* creation of motorXTimer */ motorXTimerHandle = osTimerNew(motorXTimerCallback, osTimerPeriodic, NULL, &motorXTimer_attributes); 80007a2: 4b1b ldr r3, [pc, #108] @ (8000810 ) 80007a4: 2200 movs r2, #0 80007a6: 2101 movs r1, #1 80007a8: 481a ldr r0, [pc, #104] @ (8000814 ) 80007aa: f013 fd0d bl 80141c8 80007ae: 4603 mov r3, r0 80007b0: 4a19 ldr r2, [pc, #100] @ (8000818 ) 80007b2: 6013 str r3, [r2, #0] /* creation of motorYTimer */ motorYTimerHandle = osTimerNew(motorYTimerCallback, osTimerPeriodic, NULL, &motorYTimer_attributes); 80007b4: 4b19 ldr r3, [pc, #100] @ (800081c ) 80007b6: 2200 movs r2, #0 80007b8: 2101 movs r1, #1 80007ba: 4819 ldr r0, [pc, #100] @ (8000820 ) 80007bc: f013 fd04 bl 80141c8 80007c0: 4603 mov r3, r0 80007c2: 4a18 ldr r2, [pc, #96] @ (8000824 ) 80007c4: 6013 str r3, [r2, #0] /* add queues, ... */ /* USER CODE END RTOS_QUEUES */ /* Create the thread(s) */ /* creation of defaultTask */ defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); 80007c6: 4a18 ldr r2, [pc, #96] @ (8000828 ) 80007c8: 2100 movs r1, #0 80007ca: 4818 ldr r0, [pc, #96] @ (800082c ) 80007cc: f013 fc38 bl 8014040 80007d0: 4603 mov r3, r0 80007d2: 4a17 ldr r2, [pc, #92] @ (8000830 ) 80007d4: 6013 str r3, [r2, #0] /* USER CODE BEGIN RTOS_THREADS */ /* add threads, ... */ #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 80007d6: 4807 ldr r0, [pc, #28] @ (80007f4 ) 80007d8: f00a ff4c bl 800b674 #endif UartTasksInit(); 80007dc: f004 f8e4 bl 80049a8 #ifdef USER_MOCKS MockMeasurmetsTaskInit(); #else MeasTasksInit(); 80007e0: f001 fb7a bl 8001ed8 #endif PositionControlTaskInit(); 80007e4: f002 fdb2 bl 800334c /* USER CODE BEGIN RTOS_EVENTS */ /* add events, ... */ /* USER CODE END RTOS_EVENTS */ /* Start scheduler */ osKernelStart(); 80007e8: f013 fc04 bl 8013ff4 /* We should never get here as control is now taken by the scheduler */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 80007ec: bf00 nop 80007ee: e7fd b.n 80007ec 80007f0: e000ed00 .word 0xe000ed00 80007f4: 24000418 .word 0x24000418 80007f8: 0801869c .word 0x0801869c 80007fc: 08001d15 .word 0x08001d15 8000800: 240006e4 .word 0x240006e4 8000804: 080186ac .word 0x080186ac 8000808: 08001d2d .word 0x08001d2d 800080c: 24000714 .word 0x24000714 8000810: 080186bc .word 0x080186bc 8000814: 08001d49 .word 0x08001d49 8000818: 24000744 .word 0x24000744 800081c: 080186cc .word 0x080186cc 8000820: 08001d85 .word 0x08001d85 8000824: 24000774 .word 0x24000774 8000828: 08018678 .word 0x08018678 800082c: 08001b59 .word 0x08001b59 8000830: 240006e0 .word 0x240006e0 08000834 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000834: b580 push {r7, lr} 8000836: b09c sub sp, #112 @ 0x70 8000838: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800083a: f107 0324 add.w r3, r7, #36 @ 0x24 800083e: 224c movs r2, #76 @ 0x4c 8000840: 2100 movs r1, #0 8000842: 4618 mov r0, r3 8000844: f017 fd50 bl 80182e8 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000848: 1d3b adds r3, r7, #4 800084a: 2220 movs r2, #32 800084c: 2100 movs r1, #0 800084e: 4618 mov r0, r3 8000850: f017 fd4a bl 80182e8 /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 8000854: 2002 movs r0, #2 8000856: f00a ffa7 bl 800b7a8 /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 800085a: 2300 movs r3, #0 800085c: 603b str r3, [r7, #0] 800085e: 4b32 ldr r3, [pc, #200] @ (8000928 ) 8000860: 6adb ldr r3, [r3, #44] @ 0x2c 8000862: 4a31 ldr r2, [pc, #196] @ (8000928 ) 8000864: f023 0301 bic.w r3, r3, #1 8000868: 62d3 str r3, [r2, #44] @ 0x2c 800086a: 4b2f ldr r3, [pc, #188] @ (8000928 ) 800086c: 6adb ldr r3, [r3, #44] @ 0x2c 800086e: f003 0301 and.w r3, r3, #1 8000872: 603b str r3, [r7, #0] 8000874: 4b2d ldr r3, [pc, #180] @ (800092c ) 8000876: 699b ldr r3, [r3, #24] 8000878: 4a2c ldr r2, [pc, #176] @ (800092c ) 800087a: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800087e: 6193 str r3, [r2, #24] 8000880: 4b2a ldr r3, [pc, #168] @ (800092c ) 8000882: 699b ldr r3, [r3, #24] 8000884: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000888: 603b str r3, [r7, #0] 800088a: 683b ldr r3, [r7, #0] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 800088c: bf00 nop 800088e: 4b27 ldr r3, [pc, #156] @ (800092c ) 8000890: 699b ldr r3, [r3, #24] 8000892: f403 5300 and.w r3, r3, #8192 @ 0x2000 8000896: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800089a: d1f8 bne.n 800088e /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_LSI 800089c: 2329 movs r3, #41 @ 0x29 800089e: 627b str r3, [r7, #36] @ 0x24 |RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; 80008a0: f44f 3380 mov.w r3, #65536 @ 0x10000 80008a4: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.LSIState = RCC_LSI_ON; 80008a6: 2301 movs r3, #1 80008a8: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; 80008aa: 2301 movs r3, #1 80008ac: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80008ae: 2302 movs r3, #2 80008b0: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 80008b2: 2302 movs r3, #2 80008b4: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.PLL.PLLM = 5; 80008b6: 2305 movs r3, #5 80008b8: 653b str r3, [r7, #80] @ 0x50 RCC_OscInitStruct.PLL.PLLN = 160; 80008ba: 23a0 movs r3, #160 @ 0xa0 80008bc: 657b str r3, [r7, #84] @ 0x54 RCC_OscInitStruct.PLL.PLLP = 2; 80008be: 2302 movs r3, #2 80008c0: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLQ = 2; 80008c2: 2302 movs r3, #2 80008c4: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLR = 2; 80008c6: 2302 movs r3, #2 80008c8: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 80008ca: 2308 movs r3, #8 80008cc: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 80008ce: 2300 movs r3, #0 80008d0: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL.PLLFRACN = 0; 80008d2: 2300 movs r3, #0 80008d4: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80008d6: f107 0324 add.w r3, r7, #36 @ 0x24 80008da: 4618 mov r0, r3 80008dc: f00b f824 bl 800b928 80008e0: 4603 mov r3, r0 80008e2: 2b00 cmp r3, #0 80008e4: d001 beq.n 80008ea { Error_Handler(); 80008e6: f001 faf1 bl 8001ecc } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80008ea: 233f movs r3, #63 @ 0x3f 80008ec: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80008ee: 2303 movs r3, #3 80008f0: 60bb str r3, [r7, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 80008f2: 2300 movs r3, #0 80008f4: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 80008f6: 2308 movs r3, #8 80008f8: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 80008fa: 2340 movs r3, #64 @ 0x40 80008fc: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 80008fe: 2340 movs r3, #64 @ 0x40 8000900: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 8000902: f44f 6380 mov.w r3, #1024 @ 0x400 8000906: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 8000908: 2340 movs r3, #64 @ 0x40 800090a: 623b str r3, [r7, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800090c: 1d3b adds r3, r7, #4 800090e: 2102 movs r1, #2 8000910: 4618 mov r0, r3 8000912: f00b fc63 bl 800c1dc 8000916: 4603 mov r3, r0 8000918: 2b00 cmp r3, #0 800091a: d001 beq.n 8000920 { Error_Handler(); 800091c: f001 fad6 bl 8001ecc } } 8000920: bf00 nop 8000922: 3770 adds r7, #112 @ 0x70 8000924: 46bd mov sp, r7 8000926: bd80 pop {r7, pc} 8000928: 58000400 .word 0x58000400 800092c: 58024800 .word 0x58024800 08000930 : /** * @brief Peripherals Common Clock Configuration * @retval None */ void PeriphCommonClock_Config(void) { 8000930: b580 push {r7, lr} 8000932: b0b0 sub sp, #192 @ 0xc0 8000934: af00 add r7, sp, #0 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8000936: 463b mov r3, r7 8000938: 22c0 movs r2, #192 @ 0xc0 800093a: 2100 movs r1, #0 800093c: 4618 mov r0, r3 800093e: f017 fcd3 bl 80182e8 /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC; 8000942: f44f 2200 mov.w r2, #524288 @ 0x80000 8000946: f04f 0300 mov.w r3, #0 800094a: e9c7 2300 strd r2, r3, [r7] PeriphClkInitStruct.PLL2.PLL2M = 5; 800094e: 2305 movs r3, #5 8000950: 60bb str r3, [r7, #8] PeriphClkInitStruct.PLL2.PLL2N = 52; 8000952: 2334 movs r3, #52 @ 0x34 8000954: 60fb str r3, [r7, #12] PeriphClkInitStruct.PLL2.PLL2P = 26; 8000956: 231a movs r3, #26 8000958: 613b str r3, [r7, #16] PeriphClkInitStruct.PLL2.PLL2Q = 2; 800095a: 2302 movs r3, #2 800095c: 617b str r3, [r7, #20] PeriphClkInitStruct.PLL2.PLL2R = 2; 800095e: 2302 movs r3, #2 8000960: 61bb str r3, [r7, #24] PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2; 8000962: 2380 movs r3, #128 @ 0x80 8000964: 61fb str r3, [r7, #28] PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; 8000966: 2300 movs r3, #0 8000968: 623b str r3, [r7, #32] PeriphClkInitStruct.PLL2.PLL2FRACN = 0; 800096a: 2300 movs r3, #0 800096c: 627b str r3, [r7, #36] @ 0x24 PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; 800096e: 2300 movs r3, #0 8000970: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8000974: 463b mov r3, r7 8000976: 4618 mov r0, r3 8000978: f00b fffe bl 800c978 800097c: 4603 mov r3, r0 800097e: 2b00 cmp r3, #0 8000980: d001 beq.n 8000986 { Error_Handler(); 8000982: f001 faa3 bl 8001ecc } } 8000986: bf00 nop 8000988: 37c0 adds r7, #192 @ 0xc0 800098a: 46bd mov sp, r7 800098c: bd80 pop {r7, pc} ... 08000990 : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 8000990: b580 push {r7, lr} 8000992: b08a sub sp, #40 @ 0x28 8000994: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_MultiModeTypeDef multimode = {0}; 8000996: f107 031c add.w r3, r7, #28 800099a: 2200 movs r2, #0 800099c: 601a str r2, [r3, #0] 800099e: 605a str r2, [r3, #4] 80009a0: 609a str r2, [r3, #8] ADC_ChannelConfTypeDef sConfig = {0}; 80009a2: 463b mov r3, r7 80009a4: 2200 movs r2, #0 80009a6: 601a str r2, [r3, #0] 80009a8: 605a str r2, [r3, #4] 80009aa: 609a str r2, [r3, #8] 80009ac: 60da str r2, [r3, #12] 80009ae: 611a str r2, [r3, #16] 80009b0: 615a str r2, [r3, #20] 80009b2: 619a str r2, [r3, #24] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 80009b4: 4b62 ldr r3, [pc, #392] @ (8000b40 ) 80009b6: 4a63 ldr r2, [pc, #396] @ (8000b44 ) 80009b8: 601a str r2, [r3, #0] hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 80009ba: 4b61 ldr r3, [pc, #388] @ (8000b40 ) 80009bc: 2200 movs r2, #0 80009be: 605a str r2, [r3, #4] hadc1.Init.Resolution = ADC_RESOLUTION_16B; 80009c0: 4b5f ldr r3, [pc, #380] @ (8000b40 ) 80009c2: 2200 movs r2, #0 80009c4: 609a str r2, [r3, #8] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 80009c6: 4b5e ldr r3, [pc, #376] @ (8000b40 ) 80009c8: 2201 movs r2, #1 80009ca: 60da str r2, [r3, #12] hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; 80009cc: 4b5c ldr r3, [pc, #368] @ (8000b40 ) 80009ce: 2208 movs r2, #8 80009d0: 611a str r2, [r3, #16] hadc1.Init.LowPowerAutoWait = DISABLE; 80009d2: 4b5b ldr r3, [pc, #364] @ (8000b40 ) 80009d4: 2200 movs r2, #0 80009d6: 751a strb r2, [r3, #20] hadc1.Init.ContinuousConvMode = ENABLE; 80009d8: 4b59 ldr r3, [pc, #356] @ (8000b40 ) 80009da: 2201 movs r2, #1 80009dc: 755a strb r2, [r3, #21] hadc1.Init.NbrOfConversion = 7; 80009de: 4b58 ldr r3, [pc, #352] @ (8000b40 ) 80009e0: 2207 movs r2, #7 80009e2: 619a str r2, [r3, #24] hadc1.Init.DiscontinuousConvMode = DISABLE; 80009e4: 4b56 ldr r3, [pc, #344] @ (8000b40 ) 80009e6: 2200 movs r2, #0 80009e8: 771a strb r2, [r3, #28] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T8_TRGO; 80009ea: 4b55 ldr r3, [pc, #340] @ (8000b40 ) 80009ec: f44f 629c mov.w r2, #1248 @ 0x4e0 80009f0: 625a str r2, [r3, #36] @ 0x24 hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 80009f2: 4b53 ldr r3, [pc, #332] @ (8000b40 ) 80009f4: f44f 6280 mov.w r2, #1024 @ 0x400 80009f8: 629a str r2, [r3, #40] @ 0x28 hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 80009fa: 4b51 ldr r3, [pc, #324] @ (8000b40 ) 80009fc: 2201 movs r2, #1 80009fe: 62da str r2, [r3, #44] @ 0x2c hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000a00: 4b4f ldr r3, [pc, #316] @ (8000b40 ) 8000a02: 2200 movs r2, #0 8000a04: 631a str r2, [r3, #48] @ 0x30 hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000a06: 4b4e ldr r3, [pc, #312] @ (8000b40 ) 8000a08: 2200 movs r2, #0 8000a0a: 635a str r2, [r3, #52] @ 0x34 hadc1.Init.OversamplingMode = DISABLE; 8000a0c: 4b4c ldr r3, [pc, #304] @ (8000b40 ) 8000a0e: 2200 movs r2, #0 8000a10: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc1) != HAL_OK) 8000a14: 484a ldr r0, [pc, #296] @ (8000b40 ) 8000a16: f005 fc51 bl 80062bc 8000a1a: 4603 mov r3, r0 8000a1c: 2b00 cmp r3, #0 8000a1e: d001 beq.n 8000a24 { Error_Handler(); 8000a20: f001 fa54 bl 8001ecc } /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; 8000a24: 2300 movs r3, #0 8000a26: 61fb str r3, [r7, #28] if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 8000a28: f107 031c add.w r3, r7, #28 8000a2c: 4619 mov r1, r3 8000a2e: 4844 ldr r0, [pc, #272] @ (8000b40 ) 8000a30: f006 fd62 bl 80074f8 8000a34: 4603 mov r3, r0 8000a36: 2b00 cmp r3, #0 8000a38: d001 beq.n 8000a3e { Error_Handler(); 8000a3a: f001 fa47 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8000a3e: 4b42 ldr r3, [pc, #264] @ (8000b48 ) 8000a40: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_1; 8000a42: 2306 movs r3, #6 8000a44: 607b str r3, [r7, #4] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000a46: 2306 movs r3, #6 8000a48: 60bb str r3, [r7, #8] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000a4a: f240 73ff movw r3, #2047 @ 0x7ff 8000a4e: 60fb str r3, [r7, #12] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000a50: 2304 movs r3, #4 8000a52: 613b str r3, [r7, #16] sConfig.Offset = 0; 8000a54: 2300 movs r3, #0 8000a56: 617b str r3, [r7, #20] sConfig.OffsetSignedSaturation = DISABLE; 8000a58: 2300 movs r3, #0 8000a5a: 767b strb r3, [r7, #25] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000a5c: 463b mov r3, r7 8000a5e: 4619 mov r1, r3 8000a60: 4837 ldr r0, [pc, #220] @ (8000b40 ) 8000a62: f005 fea5 bl 80067b0 8000a66: 4603 mov r3, r0 8000a68: 2b00 cmp r3, #0 8000a6a: d001 beq.n 8000a70 { Error_Handler(); 8000a6c: f001 fa2e bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_7; 8000a70: 4b36 ldr r3, [pc, #216] @ (8000b4c ) 8000a72: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_2; 8000a74: 230c movs r3, #12 8000a76: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000a78: 463b mov r3, r7 8000a7a: 4619 mov r1, r3 8000a7c: 4830 ldr r0, [pc, #192] @ (8000b40 ) 8000a7e: f005 fe97 bl 80067b0 8000a82: 4603 mov r3, r0 8000a84: 2b00 cmp r3, #0 8000a86: d001 beq.n 8000a8c { Error_Handler(); 8000a88: f001 fa20 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_9; 8000a8c: 4b30 ldr r3, [pc, #192] @ (8000b50 ) 8000a8e: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_3; 8000a90: 2312 movs r3, #18 8000a92: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000a94: 463b mov r3, r7 8000a96: 4619 mov r1, r3 8000a98: 4829 ldr r0, [pc, #164] @ (8000b40 ) 8000a9a: f005 fe89 bl 80067b0 8000a9e: 4603 mov r3, r0 8000aa0: 2b00 cmp r3, #0 8000aa2: d001 beq.n 8000aa8 { Error_Handler(); 8000aa4: f001 fa12 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_16; 8000aa8: 4b2a ldr r3, [pc, #168] @ (8000b54 ) 8000aaa: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_4; 8000aac: 2318 movs r3, #24 8000aae: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000ab0: 463b mov r3, r7 8000ab2: 4619 mov r1, r3 8000ab4: 4822 ldr r0, [pc, #136] @ (8000b40 ) 8000ab6: f005 fe7b bl 80067b0 8000aba: 4603 mov r3, r0 8000abc: 2b00 cmp r3, #0 8000abe: d001 beq.n 8000ac4 { Error_Handler(); 8000ac0: f001 fa04 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_17; 8000ac4: 4b24 ldr r3, [pc, #144] @ (8000b58 ) 8000ac6: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_5; 8000ac8: f44f 7380 mov.w r3, #256 @ 0x100 8000acc: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000ace: 463b mov r3, r7 8000ad0: 4619 mov r1, r3 8000ad2: 481b ldr r0, [pc, #108] @ (8000b40 ) 8000ad4: f005 fe6c bl 80067b0 8000ad8: 4603 mov r3, r0 8000ada: 2b00 cmp r3, #0 8000adc: d001 beq.n 8000ae2 { Error_Handler(); 8000ade: f001 f9f5 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_14; 8000ae2: 4b1e ldr r3, [pc, #120] @ (8000b5c ) 8000ae4: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_6; 8000ae6: f44f 7383 mov.w r3, #262 @ 0x106 8000aea: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000aec: 463b mov r3, r7 8000aee: 4619 mov r1, r3 8000af0: 4813 ldr r0, [pc, #76] @ (8000b40 ) 8000af2: f005 fe5d bl 80067b0 8000af6: 4603 mov r3, r0 8000af8: 2b00 cmp r3, #0 8000afa: d001 beq.n 8000b00 { Error_Handler(); 8000afc: f001 f9e6 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_15; 8000b00: 4b17 ldr r3, [pc, #92] @ (8000b60 ) 8000b02: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_7; 8000b04: f44f 7386 mov.w r3, #268 @ 0x10c 8000b08: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000b0a: 463b mov r3, r7 8000b0c: 4619 mov r1, r3 8000b0e: 480c ldr r0, [pc, #48] @ (8000b40 ) 8000b10: f005 fe4e bl 80067b0 8000b14: 4603 mov r3, r0 8000b16: 2b00 cmp r3, #0 8000b18: d001 beq.n 8000b1e { Error_Handler(); 8000b1a: f001 f9d7 bl 8001ecc } /* USER CODE BEGIN ADC1_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000b1e: f240 72ff movw r2, #2047 @ 0x7ff 8000b22: f04f 1101 mov.w r1, #65537 @ 0x10001 8000b26: 4806 ldr r0, [pc, #24] @ (8000b40 ) 8000b28: f006 fc82 bl 8007430 8000b2c: 4603 mov r3, r0 8000b2e: 2b00 cmp r3, #0 8000b30: d001 beq.n 8000b36 { Error_Handler(); 8000b32: f001 f9cb bl 8001ecc } /* USER CODE END ADC1_Init 2 */ } 8000b36: bf00 nop 8000b38: 3728 adds r7, #40 @ 0x28 8000b3a: 46bd mov sp, r7 8000b3c: bd80 pop {r7, pc} 8000b3e: bf00 nop 8000b40: 24000120 .word 0x24000120 8000b44: 40022000 .word 0x40022000 8000b48: 21800100 .word 0x21800100 8000b4c: 1d500080 .word 0x1d500080 8000b50: 25b00200 .word 0x25b00200 8000b54: 43210000 .word 0x43210000 8000b58: 47520000 .word 0x47520000 8000b5c: 3ac04000 .word 0x3ac04000 8000b60: 3ef08000 .word 0x3ef08000 08000b64 : * @brief ADC2 Initialization Function * @param None * @retval None */ static void MX_ADC2_Init(void) { 8000b64: b580 push {r7, lr} 8000b66: b088 sub sp, #32 8000b68: af00 add r7, sp, #0 /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000b6a: 1d3b adds r3, r7, #4 8000b6c: 2200 movs r2, #0 8000b6e: 601a str r2, [r3, #0] 8000b70: 605a str r2, [r3, #4] 8000b72: 609a str r2, [r3, #8] 8000b74: 60da str r2, [r3, #12] 8000b76: 611a str r2, [r3, #16] 8000b78: 615a str r2, [r3, #20] 8000b7a: 619a str r2, [r3, #24] /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; 8000b7c: 4b3e ldr r3, [pc, #248] @ (8000c78 ) 8000b7e: 4a3f ldr r2, [pc, #252] @ (8000c7c ) 8000b80: 601a str r2, [r3, #0] hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 8000b82: 4b3d ldr r3, [pc, #244] @ (8000c78 ) 8000b84: 2200 movs r2, #0 8000b86: 605a str r2, [r3, #4] hadc2.Init.Resolution = ADC_RESOLUTION_16B; 8000b88: 4b3b ldr r3, [pc, #236] @ (8000c78 ) 8000b8a: 2200 movs r2, #0 8000b8c: 609a str r2, [r3, #8] hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000b8e: 4b3a ldr r3, [pc, #232] @ (8000c78 ) 8000b90: 2201 movs r2, #1 8000b92: 60da str r2, [r3, #12] hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000b94: 4b38 ldr r3, [pc, #224] @ (8000c78 ) 8000b96: 2208 movs r2, #8 8000b98: 611a str r2, [r3, #16] hadc2.Init.LowPowerAutoWait = DISABLE; 8000b9a: 4b37 ldr r3, [pc, #220] @ (8000c78 ) 8000b9c: 2200 movs r2, #0 8000b9e: 751a strb r2, [r3, #20] hadc2.Init.ContinuousConvMode = ENABLE; 8000ba0: 4b35 ldr r3, [pc, #212] @ (8000c78 ) 8000ba2: 2201 movs r2, #1 8000ba4: 755a strb r2, [r3, #21] hadc2.Init.NbrOfConversion = 3; 8000ba6: 4b34 ldr r3, [pc, #208] @ (8000c78 ) 8000ba8: 2203 movs r2, #3 8000baa: 619a str r2, [r3, #24] hadc2.Init.DiscontinuousConvMode = DISABLE; 8000bac: 4b32 ldr r3, [pc, #200] @ (8000c78 ) 8000bae: 2200 movs r2, #0 8000bb0: 771a strb r2, [r3, #28] hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T8_TRGO; 8000bb2: 4b31 ldr r3, [pc, #196] @ (8000c78 ) 8000bb4: f44f 629c mov.w r2, #1248 @ 0x4e0 8000bb8: 625a str r2, [r3, #36] @ 0x24 hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000bba: 4b2f ldr r3, [pc, #188] @ (8000c78 ) 8000bbc: f44f 6280 mov.w r2, #1024 @ 0x400 8000bc0: 629a str r2, [r3, #40] @ 0x28 hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000bc2: 4b2d ldr r3, [pc, #180] @ (8000c78 ) 8000bc4: 2201 movs r2, #1 8000bc6: 62da str r2, [r3, #44] @ 0x2c hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000bc8: 4b2b ldr r3, [pc, #172] @ (8000c78 ) 8000bca: 2200 movs r2, #0 8000bcc: 631a str r2, [r3, #48] @ 0x30 hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000bce: 4b2a ldr r3, [pc, #168] @ (8000c78 ) 8000bd0: 2200 movs r2, #0 8000bd2: 635a str r2, [r3, #52] @ 0x34 hadc2.Init.OversamplingMode = DISABLE; 8000bd4: 4b28 ldr r3, [pc, #160] @ (8000c78 ) 8000bd6: 2200 movs r2, #0 8000bd8: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc2) != HAL_OK) 8000bdc: 4826 ldr r0, [pc, #152] @ (8000c78 ) 8000bde: f005 fb6d bl 80062bc 8000be2: 4603 mov r3, r0 8000be4: 2b00 cmp r3, #0 8000be6: d001 beq.n 8000bec { Error_Handler(); 8000be8: f001 f970 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 8000bec: 4b24 ldr r3, [pc, #144] @ (8000c80 ) 8000bee: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8000bf0: 2306 movs r3, #6 8000bf2: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000bf4: 2306 movs r3, #6 8000bf6: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000bf8: f240 73ff movw r3, #2047 @ 0x7ff 8000bfc: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000bfe: 2304 movs r3, #4 8000c00: 617b str r3, [r7, #20] sConfig.Offset = 0; 8000c02: 2300 movs r3, #0 8000c04: 61bb str r3, [r7, #24] sConfig.OffsetSignedSaturation = DISABLE; 8000c06: 2300 movs r3, #0 8000c08: 777b strb r3, [r7, #29] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000c0a: 1d3b adds r3, r7, #4 8000c0c: 4619 mov r1, r3 8000c0e: 481a ldr r0, [pc, #104] @ (8000c78 ) 8000c10: f005 fdce bl 80067b0 8000c14: 4603 mov r3, r0 8000c16: 2b00 cmp r3, #0 8000c18: d001 beq.n 8000c1e { Error_Handler(); 8000c1a: f001 f957 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8000c1e: 4b19 ldr r3, [pc, #100] @ (8000c84 ) 8000c20: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 8000c22: 230c movs r3, #12 8000c24: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000c26: 1d3b adds r3, r7, #4 8000c28: 4619 mov r1, r3 8000c2a: 4813 ldr r0, [pc, #76] @ (8000c78 ) 8000c2c: f005 fdc0 bl 80067b0 8000c30: 4603 mov r3, r0 8000c32: 2b00 cmp r3, #0 8000c34: d001 beq.n 8000c3a { Error_Handler(); 8000c36: f001 f949 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_5; 8000c3a: 4b13 ldr r3, [pc, #76] @ (8000c88 ) 8000c3c: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8000c3e: 2312 movs r3, #18 8000c40: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000c42: 1d3b adds r3, r7, #4 8000c44: 4619 mov r1, r3 8000c46: 480c ldr r0, [pc, #48] @ (8000c78 ) 8000c48: f005 fdb2 bl 80067b0 8000c4c: 4603 mov r3, r0 8000c4e: 2b00 cmp r3, #0 8000c50: d001 beq.n 8000c56 { Error_Handler(); 8000c52: f001 f93b bl 8001ecc } /* USER CODE BEGIN ADC2_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc2, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000c56: f240 72ff movw r2, #2047 @ 0x7ff 8000c5a: f04f 1101 mov.w r1, #65537 @ 0x10001 8000c5e: 4806 ldr r0, [pc, #24] @ (8000c78 ) 8000c60: f006 fbe6 bl 8007430 8000c64: 4603 mov r3, r0 8000c66: 2b00 cmp r3, #0 8000c68: d001 beq.n 8000c6e { Error_Handler(); 8000c6a: f001 f92f bl 8001ecc } /* USER CODE END ADC2_Init 2 */ } 8000c6e: bf00 nop 8000c70: 3720 adds r7, #32 8000c72: 46bd mov sp, r7 8000c74: bd80 pop {r7, pc} 8000c76: bf00 nop 8000c78: 24000184 .word 0x24000184 8000c7c: 40022100 .word 0x40022100 8000c80: 0c900008 .word 0x0c900008 8000c84: 10c00010 .word 0x10c00010 8000c88: 14f00020 .word 0x14f00020 08000c8c : * @brief ADC3 Initialization Function * @param None * @retval None */ static void MX_ADC3_Init(void) { 8000c8c: b580 push {r7, lr} 8000c8e: b088 sub sp, #32 8000c90: af00 add r7, sp, #0 /* USER CODE BEGIN ADC3_Init 0 */ /* USER CODE END ADC3_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000c92: 1d3b adds r3, r7, #4 8000c94: 2200 movs r2, #0 8000c96: 601a str r2, [r3, #0] 8000c98: 605a str r2, [r3, #4] 8000c9a: 609a str r2, [r3, #8] 8000c9c: 60da str r2, [r3, #12] 8000c9e: 611a str r2, [r3, #16] 8000ca0: 615a str r2, [r3, #20] 8000ca2: 619a str r2, [r3, #24] /* USER CODE END ADC3_Init 1 */ /** Common config */ hadc3.Instance = ADC3; 8000ca4: 4b4b ldr r3, [pc, #300] @ (8000dd4 ) 8000ca6: 4a4c ldr r2, [pc, #304] @ (8000dd8 ) 8000ca8: 601a str r2, [r3, #0] hadc3.Init.Resolution = ADC_RESOLUTION_16B; 8000caa: 4b4a ldr r3, [pc, #296] @ (8000dd4 ) 8000cac: 2200 movs r2, #0 8000cae: 609a str r2, [r3, #8] hadc3.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000cb0: 4b48 ldr r3, [pc, #288] @ (8000dd4 ) 8000cb2: 2201 movs r2, #1 8000cb4: 60da str r2, [r3, #12] hadc3.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000cb6: 4b47 ldr r3, [pc, #284] @ (8000dd4 ) 8000cb8: 2208 movs r2, #8 8000cba: 611a str r2, [r3, #16] hadc3.Init.LowPowerAutoWait = DISABLE; 8000cbc: 4b45 ldr r3, [pc, #276] @ (8000dd4 ) 8000cbe: 2200 movs r2, #0 8000cc0: 751a strb r2, [r3, #20] hadc3.Init.ContinuousConvMode = ENABLE; 8000cc2: 4b44 ldr r3, [pc, #272] @ (8000dd4 ) 8000cc4: 2201 movs r2, #1 8000cc6: 755a strb r2, [r3, #21] hadc3.Init.NbrOfConversion = 5; 8000cc8: 4b42 ldr r3, [pc, #264] @ (8000dd4 ) 8000cca: 2205 movs r2, #5 8000ccc: 619a str r2, [r3, #24] hadc3.Init.DiscontinuousConvMode = DISABLE; 8000cce: 4b41 ldr r3, [pc, #260] @ (8000dd4 ) 8000cd0: 2200 movs r2, #0 8000cd2: 771a strb r2, [r3, #28] hadc3.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T8_TRGO; 8000cd4: 4b3f ldr r3, [pc, #252] @ (8000dd4 ) 8000cd6: f44f 629c mov.w r2, #1248 @ 0x4e0 8000cda: 625a str r2, [r3, #36] @ 0x24 hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000cdc: 4b3d ldr r3, [pc, #244] @ (8000dd4 ) 8000cde: f44f 6280 mov.w r2, #1024 @ 0x400 8000ce2: 629a str r2, [r3, #40] @ 0x28 hadc3.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000ce4: 4b3b ldr r3, [pc, #236] @ (8000dd4 ) 8000ce6: 2201 movs r2, #1 8000ce8: 62da str r2, [r3, #44] @ 0x2c hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000cea: 4b3a ldr r3, [pc, #232] @ (8000dd4 ) 8000cec: 2200 movs r2, #0 8000cee: 631a str r2, [r3, #48] @ 0x30 hadc3.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000cf0: 4b38 ldr r3, [pc, #224] @ (8000dd4 ) 8000cf2: 2200 movs r2, #0 8000cf4: 635a str r2, [r3, #52] @ 0x34 hadc3.Init.OversamplingMode = DISABLE; 8000cf6: 4b37 ldr r3, [pc, #220] @ (8000dd4 ) 8000cf8: 2200 movs r2, #0 8000cfa: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc3) != HAL_OK) 8000cfe: 4835 ldr r0, [pc, #212] @ (8000dd4 ) 8000d00: f005 fadc bl 80062bc 8000d04: 4603 mov r3, r0 8000d06: 2b00 cmp r3, #0 8000d08: d001 beq.n 8000d0e { Error_Handler(); 8000d0a: f001 f8df bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_0; 8000d0e: 2301 movs r3, #1 8000d10: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8000d12: 2306 movs r3, #6 8000d14: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000d16: 2306 movs r3, #6 8000d18: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000d1a: f240 73ff movw r3, #2047 @ 0x7ff 8000d1e: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000d20: 2304 movs r3, #4 8000d22: 617b str r3, [r7, #20] sConfig.Offset = 0; 8000d24: 2300 movs r3, #0 8000d26: 61bb str r3, [r7, #24] sConfig.OffsetSignedSaturation = DISABLE; 8000d28: 2300 movs r3, #0 8000d2a: 777b strb r3, [r7, #29] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d2c: 1d3b adds r3, r7, #4 8000d2e: 4619 mov r1, r3 8000d30: 4828 ldr r0, [pc, #160] @ (8000dd4 ) 8000d32: f005 fd3d bl 80067b0 8000d36: 4603 mov r3, r0 8000d38: 2b00 cmp r3, #0 8000d3a: d001 beq.n 8000d40 { Error_Handler(); 8000d3c: f001 f8c6 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 8000d40: 4b26 ldr r3, [pc, #152] @ (8000ddc ) 8000d42: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 8000d44: 230c movs r3, #12 8000d46: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d48: 1d3b adds r3, r7, #4 8000d4a: 4619 mov r1, r3 8000d4c: 4821 ldr r0, [pc, #132] @ (8000dd4 ) 8000d4e: f005 fd2f bl 80067b0 8000d52: 4603 mov r3, r0 8000d54: 2b00 cmp r3, #0 8000d56: d001 beq.n 8000d5c { Error_Handler(); 8000d58: f001 f8b8 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_10; 8000d5c: 4b20 ldr r3, [pc, #128] @ (8000de0 ) 8000d5e: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8000d60: 2312 movs r3, #18 8000d62: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d64: 1d3b adds r3, r7, #4 8000d66: 4619 mov r1, r3 8000d68: 481a ldr r0, [pc, #104] @ (8000dd4 ) 8000d6a: f005 fd21 bl 80067b0 8000d6e: 4603 mov r3, r0 8000d70: 2b00 cmp r3, #0 8000d72: d001 beq.n 8000d78 { Error_Handler(); 8000d74: f001 f8aa bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_11; 8000d78: 4b1a ldr r3, [pc, #104] @ (8000de4 ) 8000d7a: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_4; 8000d7c: 2318 movs r3, #24 8000d7e: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d80: 1d3b adds r3, r7, #4 8000d82: 4619 mov r1, r3 8000d84: 4813 ldr r0, [pc, #76] @ (8000dd4 ) 8000d86: f005 fd13 bl 80067b0 8000d8a: 4603 mov r3, r0 8000d8c: 2b00 cmp r3, #0 8000d8e: d001 beq.n 8000d94 { Error_Handler(); 8000d90: f001 f89c bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; 8000d94: 4b14 ldr r3, [pc, #80] @ (8000de8 ) 8000d96: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_5; 8000d98: f44f 7380 mov.w r3, #256 @ 0x100 8000d9c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d9e: 1d3b adds r3, r7, #4 8000da0: 4619 mov r1, r3 8000da2: 480c ldr r0, [pc, #48] @ (8000dd4 ) 8000da4: f005 fd04 bl 80067b0 8000da8: 4603 mov r3, r0 8000daa: 2b00 cmp r3, #0 8000dac: d001 beq.n 8000db2 { Error_Handler(); 8000dae: f001 f88d bl 8001ecc } /* USER CODE BEGIN ADC3_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc3, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000db2: f240 72ff movw r2, #2047 @ 0x7ff 8000db6: f04f 1101 mov.w r1, #65537 @ 0x10001 8000dba: 4806 ldr r0, [pc, #24] @ (8000dd4 ) 8000dbc: f006 fb38 bl 8007430 8000dc0: 4603 mov r3, r0 8000dc2: 2b00 cmp r3, #0 8000dc4: d001 beq.n 8000dca { Error_Handler(); 8000dc6: f001 f881 bl 8001ecc } /* USER CODE END ADC3_Init 2 */ } 8000dca: bf00 nop 8000dcc: 3720 adds r7, #32 8000dce: 46bd mov sp, r7 8000dd0: bd80 pop {r7, pc} 8000dd2: bf00 nop 8000dd4: 240001e8 .word 0x240001e8 8000dd8: 58026000 .word 0x58026000 8000ddc: 04300002 .word 0x04300002 8000de0: 2a000400 .word 0x2a000400 8000de4: 2e300800 .word 0x2e300800 8000de8: cfb80000 .word 0xcfb80000 08000dec : * @brief COMP1 Initialization Function * @param None * @retval None */ static void MX_COMP1_Init(void) { 8000dec: b580 push {r7, lr} 8000dee: af00 add r7, sp, #0 /* USER CODE END COMP1_Init 0 */ /* USER CODE BEGIN COMP1_Init 1 */ /* USER CODE END COMP1_Init 1 */ hcomp1.Instance = COMP1; 8000df0: 4b12 ldr r3, [pc, #72] @ (8000e3c ) 8000df2: 4a13 ldr r2, [pc, #76] @ (8000e40 ) 8000df4: 601a str r2, [r3, #0] hcomp1.Init.InvertingInput = COMP_INPUT_MINUS_3_4VREFINT; 8000df6: 4b11 ldr r3, [pc, #68] @ (8000e3c ) 8000df8: 4a12 ldr r2, [pc, #72] @ (8000e44 ) 8000dfa: 611a str r2, [r3, #16] hcomp1.Init.NonInvertingInput = COMP_INPUT_PLUS_IO2; 8000dfc: 4b0f ldr r3, [pc, #60] @ (8000e3c ) 8000dfe: f44f 1280 mov.w r2, #1048576 @ 0x100000 8000e02: 60da str r2, [r3, #12] hcomp1.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED; 8000e04: 4b0d ldr r3, [pc, #52] @ (8000e3c ) 8000e06: 2200 movs r2, #0 8000e08: 619a str r2, [r3, #24] hcomp1.Init.Hysteresis = COMP_HYSTERESIS_NONE; 8000e0a: 4b0c ldr r3, [pc, #48] @ (8000e3c ) 8000e0c: 2200 movs r2, #0 8000e0e: 615a str r2, [r3, #20] hcomp1.Init.BlankingSrce = COMP_BLANKINGSRC_NONE; 8000e10: 4b0a ldr r3, [pc, #40] @ (8000e3c ) 8000e12: 2200 movs r2, #0 8000e14: 61da str r2, [r3, #28] hcomp1.Init.Mode = COMP_POWERMODE_HIGHSPEED; 8000e16: 4b09 ldr r3, [pc, #36] @ (8000e3c ) 8000e18: 2200 movs r2, #0 8000e1a: 609a str r2, [r3, #8] hcomp1.Init.WindowMode = COMP_WINDOWMODE_DISABLE; 8000e1c: 4b07 ldr r3, [pc, #28] @ (8000e3c ) 8000e1e: 2200 movs r2, #0 8000e20: 605a str r2, [r3, #4] hcomp1.Init.TriggerMode = COMP_TRIGGERMODE_NONE; 8000e22: 4b06 ldr r3, [pc, #24] @ (8000e3c ) 8000e24: 2200 movs r2, #0 8000e26: 621a str r2, [r3, #32] if (HAL_COMP_Init(&hcomp1) != HAL_OK) 8000e28: 4804 ldr r0, [pc, #16] @ (8000e3c ) 8000e2a: f006 fc43 bl 80076b4 8000e2e: 4603 mov r3, r0 8000e30: 2b00 cmp r3, #0 8000e32: d001 beq.n 8000e38 { Error_Handler(); 8000e34: f001 f84a bl 8001ecc } /* USER CODE BEGIN COMP1_Init 2 */ /* USER CODE END COMP1_Init 2 */ } 8000e38: bf00 nop 8000e3a: bd80 pop {r7, pc} 8000e3c: 240003b4 .word 0x240003b4 8000e40: 5800380c .word 0x5800380c 8000e44: 00020006 .word 0x00020006 08000e48 : * @brief CRC Initialization Function * @param None * @retval None */ static void MX_CRC_Init(void) { 8000e48: b580 push {r7, lr} 8000e4a: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 8000e4c: 4b11 ldr r3, [pc, #68] @ (8000e94 ) 8000e4e: 4a12 ldr r2, [pc, #72] @ (8000e98 ) 8000e50: 601a str r2, [r3, #0] hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_DISABLE; 8000e52: 4b10 ldr r3, [pc, #64] @ (8000e94 ) 8000e54: 2201 movs r2, #1 8000e56: 711a strb r2, [r3, #4] hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE; 8000e58: 4b0e ldr r3, [pc, #56] @ (8000e94 ) 8000e5a: 2200 movs r2, #0 8000e5c: 715a strb r2, [r3, #5] hcrc.Init.GeneratingPolynomial = 4129; 8000e5e: 4b0d ldr r3, [pc, #52] @ (8000e94 ) 8000e60: f241 0221 movw r2, #4129 @ 0x1021 8000e64: 609a str r2, [r3, #8] hcrc.Init.CRCLength = CRC_POLYLENGTH_16B; 8000e66: 4b0b ldr r3, [pc, #44] @ (8000e94 ) 8000e68: 2208 movs r2, #8 8000e6a: 60da str r2, [r3, #12] hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE; 8000e6c: 4b09 ldr r3, [pc, #36] @ (8000e94 ) 8000e6e: 2200 movs r2, #0 8000e70: 615a str r2, [r3, #20] hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE; 8000e72: 4b08 ldr r3, [pc, #32] @ (8000e94 ) 8000e74: 2200 movs r2, #0 8000e76: 619a str r2, [r3, #24] hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; 8000e78: 4b06 ldr r3, [pc, #24] @ (8000e94 ) 8000e7a: 2201 movs r2, #1 8000e7c: 621a str r2, [r3, #32] if (HAL_CRC_Init(&hcrc) != HAL_OK) 8000e7e: 4805 ldr r0, [pc, #20] @ (8000e94 ) 8000e80: f006 ff02 bl 8007c88 8000e84: 4603 mov r3, r0 8000e86: 2b00 cmp r3, #0 8000e88: d001 beq.n 8000e8e { Error_Handler(); 8000e8a: f001 f81f bl 8001ecc } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 8000e8e: bf00 nop 8000e90: bd80 pop {r7, pc} 8000e92: bf00 nop 8000e94: 240003e0 .word 0x240003e0 8000e98: 58024c00 .word 0x58024c00 08000e9c : * @brief DAC1 Initialization Function * @param None * @retval None */ static void MX_DAC1_Init(void) { 8000e9c: b580 push {r7, lr} 8000e9e: b08a sub sp, #40 @ 0x28 8000ea0: af00 add r7, sp, #0 /* USER CODE BEGIN DAC1_Init 0 */ /* USER CODE END DAC1_Init 0 */ DAC_ChannelConfTypeDef sConfig = {0}; 8000ea2: 1d3b adds r3, r7, #4 8000ea4: 2224 movs r2, #36 @ 0x24 8000ea6: 2100 movs r1, #0 8000ea8: 4618 mov r0, r3 8000eaa: f017 fa1d bl 80182e8 /* USER CODE END DAC1_Init 1 */ /** DAC Initialization */ hdac1.Instance = DAC1; 8000eae: 4b17 ldr r3, [pc, #92] @ (8000f0c ) 8000eb0: 4a17 ldr r2, [pc, #92] @ (8000f10 ) 8000eb2: 601a str r2, [r3, #0] if (HAL_DAC_Init(&hdac1) != HAL_OK) 8000eb4: 4815 ldr r0, [pc, #84] @ (8000f0c ) 8000eb6: f007 f8ed bl 8008094 8000eba: 4603 mov r3, r0 8000ebc: 2b00 cmp r3, #0 8000ebe: d001 beq.n 8000ec4 { Error_Handler(); 8000ec0: f001 f804 bl 8001ecc } /** DAC channel OUT1 config */ sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; 8000ec4: 2300 movs r3, #0 8000ec6: 607b str r3, [r7, #4] sConfig.DAC_Trigger = DAC_TRIGGER_NONE; 8000ec8: 2300 movs r3, #0 8000eca: 60bb str r3, [r7, #8] sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; 8000ecc: 2300 movs r3, #0 8000ece: 60fb str r3, [r7, #12] sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE; 8000ed0: 2301 movs r3, #1 8000ed2: 613b str r3, [r7, #16] sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; 8000ed4: 2300 movs r3, #0 8000ed6: 617b str r3, [r7, #20] if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) 8000ed8: 1d3b adds r3, r7, #4 8000eda: 2200 movs r2, #0 8000edc: 4619 mov r1, r3 8000ede: 480b ldr r0, [pc, #44] @ (8000f0c ) 8000ee0: f007 f9dc bl 800829c 8000ee4: 4603 mov r3, r0 8000ee6: 2b00 cmp r3, #0 8000ee8: d001 beq.n 8000eee { Error_Handler(); 8000eea: f000 ffef bl 8001ecc } /** DAC channel OUT2 config */ if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK) 8000eee: 1d3b adds r3, r7, #4 8000ef0: 2210 movs r2, #16 8000ef2: 4619 mov r1, r3 8000ef4: 4805 ldr r0, [pc, #20] @ (8000f0c ) 8000ef6: f007 f9d1 bl 800829c 8000efa: 4603 mov r3, r0 8000efc: 2b00 cmp r3, #0 8000efe: d001 beq.n 8000f04 { Error_Handler(); 8000f00: f000 ffe4 bl 8001ecc } /* USER CODE BEGIN DAC1_Init 2 */ /* USER CODE END DAC1_Init 2 */ } 8000f04: bf00 nop 8000f06: 3728 adds r7, #40 @ 0x28 8000f08: 46bd mov sp, r7 8000f0a: bd80 pop {r7, pc} 8000f0c: 24000404 .word 0x24000404 8000f10: 40007400 .word 0x40007400 08000f14 : * @brief IWDG1 Initialization Function * @param None * @retval None */ static void MX_IWDG1_Init(void) { 8000f14: b580 push {r7, lr} 8000f16: af00 add r7, sp, #0 /* USER CODE END IWDG1_Init 0 */ /* USER CODE BEGIN IWDG1_Init 1 */ /* USER CODE END IWDG1_Init 1 */ hiwdg1.Instance = IWDG1; 8000f18: 4b0a ldr r3, [pc, #40] @ (8000f44 ) 8000f1a: 4a0b ldr r2, [pc, #44] @ (8000f48 ) 8000f1c: 601a str r2, [r3, #0] hiwdg1.Init.Prescaler = IWDG_PRESCALER_64; 8000f1e: 4b09 ldr r3, [pc, #36] @ (8000f44 ) 8000f20: 2204 movs r2, #4 8000f22: 605a str r2, [r3, #4] hiwdg1.Init.Window = 249; 8000f24: 4b07 ldr r3, [pc, #28] @ (8000f44 ) 8000f26: 22f9 movs r2, #249 @ 0xf9 8000f28: 60da str r2, [r3, #12] hiwdg1.Init.Reload = 249; 8000f2a: 4b06 ldr r3, [pc, #24] @ (8000f44 ) 8000f2c: 22f9 movs r2, #249 @ 0xf9 8000f2e: 609a str r2, [r3, #8] if (HAL_IWDG_Init(&hiwdg1) != HAL_OK) 8000f30: 4804 ldr r0, [pc, #16] @ (8000f44 ) 8000f32: f00a fb50 bl 800b5d6 8000f36: 4603 mov r3, r0 8000f38: 2b00 cmp r3, #0 8000f3a: d001 beq.n 8000f40 { Error_Handler(); 8000f3c: f000 ffc6 bl 8001ecc } /* USER CODE BEGIN IWDG1_Init 2 */ /* USER CODE END IWDG1_Init 2 */ } 8000f40: bf00 nop 8000f42: bd80 pop {r7, pc} 8000f44: 24000418 .word 0x24000418 8000f48: 58004800 .word 0x58004800 08000f4c : * @brief RNG Initialization Function * @param None * @retval None */ static void MX_RNG_Init(void) { 8000f4c: b580 push {r7, lr} 8000f4e: af00 add r7, sp, #0 /* USER CODE END RNG_Init 0 */ /* USER CODE BEGIN RNG_Init 1 */ /* USER CODE END RNG_Init 1 */ hrng.Instance = RNG; 8000f50: 4b07 ldr r3, [pc, #28] @ (8000f70 ) 8000f52: 4a08 ldr r2, [pc, #32] @ (8000f74 ) 8000f54: 601a str r2, [r3, #0] hrng.Init.ClockErrorDetection = RNG_CED_ENABLE; 8000f56: 4b06 ldr r3, [pc, #24] @ (8000f70 ) 8000f58: 2200 movs r2, #0 8000f5a: 605a str r2, [r3, #4] if (HAL_RNG_Init(&hrng) != HAL_OK) 8000f5c: 4804 ldr r0, [pc, #16] @ (8000f70 ) 8000f5e: f00e f9ed bl 800f33c 8000f62: 4603 mov r3, r0 8000f64: 2b00 cmp r3, #0 8000f66: d001 beq.n 8000f6c { Error_Handler(); 8000f68: f000 ffb0 bl 8001ecc } /* USER CODE BEGIN RNG_Init 2 */ /* USER CODE END RNG_Init 2 */ } 8000f6c: bf00 nop 8000f6e: bd80 pop {r7, pc} 8000f70: 24000428 .word 0x24000428 8000f74: 48021800 .word 0x48021800 08000f78 : * @brief TIM1 Initialization Function * @param None * @retval None */ static void MX_TIM1_Init(void) { 8000f78: b5b0 push {r4, r5, r7, lr} 8000f7a: b096 sub sp, #88 @ 0x58 8000f7c: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000f7e: f107 034c add.w r3, r7, #76 @ 0x4c 8000f82: 2200 movs r2, #0 8000f84: 601a str r2, [r3, #0] 8000f86: 605a str r2, [r3, #4] 8000f88: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 8000f8a: f107 0330 add.w r3, r7, #48 @ 0x30 8000f8e: 2200 movs r2, #0 8000f90: 601a str r2, [r3, #0] 8000f92: 605a str r2, [r3, #4] 8000f94: 609a str r2, [r3, #8] 8000f96: 60da str r2, [r3, #12] 8000f98: 611a str r2, [r3, #16] 8000f9a: 615a str r2, [r3, #20] 8000f9c: 619a str r2, [r3, #24] TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 8000f9e: 1d3b adds r3, r7, #4 8000fa0: 222c movs r2, #44 @ 0x2c 8000fa2: 2100 movs r1, #0 8000fa4: 4618 mov r0, r3 8000fa6: f017 f99f bl 80182e8 /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; 8000faa: 4b3e ldr r3, [pc, #248] @ (80010a4 ) 8000fac: 4a3e ldr r2, [pc, #248] @ (80010a8 ) 8000fae: 601a str r2, [r3, #0] htim1.Init.Prescaler = 199; 8000fb0: 4b3c ldr r3, [pc, #240] @ (80010a4 ) 8000fb2: 22c7 movs r2, #199 @ 0xc7 8000fb4: 605a str r2, [r3, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 8000fb6: 4b3b ldr r3, [pc, #236] @ (80010a4 ) 8000fb8: 2200 movs r2, #0 8000fba: 609a str r2, [r3, #8] htim1.Init.Period = 999; 8000fbc: 4b39 ldr r3, [pc, #228] @ (80010a4 ) 8000fbe: f240 32e7 movw r2, #999 @ 0x3e7 8000fc2: 60da str r2, [r3, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000fc4: 4b37 ldr r3, [pc, #220] @ (80010a4 ) 8000fc6: 2200 movs r2, #0 8000fc8: 611a str r2, [r3, #16] htim1.Init.RepetitionCounter = 0; 8000fca: 4b36 ldr r3, [pc, #216] @ (80010a4 ) 8000fcc: 2200 movs r2, #0 8000fce: 615a str r2, [r3, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8000fd0: 4b34 ldr r3, [pc, #208] @ (80010a4 ) 8000fd2: 2280 movs r2, #128 @ 0x80 8000fd4: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 8000fd6: 4833 ldr r0, [pc, #204] @ (80010a4 ) 8000fd8: f00e fb52 bl 800f680 8000fdc: 4603 mov r3, r0 8000fde: 2b00 cmp r3, #0 8000fe0: d001 beq.n 8000fe6 { Error_Handler(); 8000fe2: f000 ff73 bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000fe6: 2300 movs r3, #0 8000fe8: 64fb str r3, [r7, #76] @ 0x4c sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 8000fea: 2300 movs r3, #0 8000fec: 653b str r3, [r7, #80] @ 0x50 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000fee: 2300 movs r3, #0 8000ff0: 657b str r3, [r7, #84] @ 0x54 if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 8000ff2: f107 034c add.w r3, r7, #76 @ 0x4c 8000ff6: 4619 mov r1, r3 8000ff8: 482a ldr r0, [pc, #168] @ (80010a4 ) 8000ffa: f010 f8a5 bl 8011148 8000ffe: 4603 mov r3, r0 8001000: 2b00 cmp r3, #0 8001002: d001 beq.n 8001008 { Error_Handler(); 8001004: f000 ff62 bl 8001ecc } sConfigOC.OCMode = TIM_OCMODE_PWM1; 8001008: 2360 movs r3, #96 @ 0x60 800100a: 633b str r3, [r7, #48] @ 0x30 sConfigOC.Pulse = 99; 800100c: 2363 movs r3, #99 @ 0x63 800100e: 637b str r3, [r7, #52] @ 0x34 sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8001010: 2300 movs r3, #0 8001012: 63bb str r3, [r7, #56] @ 0x38 sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 8001014: 2300 movs r3, #0 8001016: 63fb str r3, [r7, #60] @ 0x3c sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001018: 2300 movs r3, #0 800101a: 643b str r3, [r7, #64] @ 0x40 sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 800101c: 2300 movs r3, #0 800101e: 647b str r3, [r7, #68] @ 0x44 sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 8001020: 2300 movs r3, #0 8001022: 64bb str r3, [r7, #72] @ 0x48 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8001024: f107 0330 add.w r3, r7, #48 @ 0x30 8001028: 2204 movs r2, #4 800102a: 4619 mov r1, r3 800102c: 481d ldr r0, [pc, #116] @ (80010a4 ) 800102e: f00f f879 bl 8010124 8001032: 4603 mov r3, r0 8001034: 2b00 cmp r3, #0 8001036: d001 beq.n 800103c { Error_Handler(); 8001038: f000 ff48 bl 8001ecc } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 800103c: 2300 movs r3, #0 800103e: 607b str r3, [r7, #4] sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 8001040: 2300 movs r3, #0 8001042: 60bb str r3, [r7, #8] sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 8001044: 2300 movs r3, #0 8001046: 60fb str r3, [r7, #12] sBreakDeadTimeConfig.DeadTime = 0; 8001048: 2300 movs r3, #0 800104a: 613b str r3, [r7, #16] sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 800104c: 2300 movs r3, #0 800104e: 617b str r3, [r7, #20] sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 8001050: f44f 5300 mov.w r3, #8192 @ 0x2000 8001054: 61bb str r3, [r7, #24] sBreakDeadTimeConfig.BreakFilter = 0; 8001056: 2300 movs r3, #0 8001058: 61fb str r3, [r7, #28] sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 800105a: 2300 movs r3, #0 800105c: 623b str r3, [r7, #32] sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 800105e: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8001062: 627b str r3, [r7, #36] @ 0x24 sBreakDeadTimeConfig.Break2Filter = 0; 8001064: 2300 movs r3, #0 8001066: 62bb str r3, [r7, #40] @ 0x28 sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 8001068: 2300 movs r3, #0 800106a: 62fb str r3, [r7, #44] @ 0x2c if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 800106c: 1d3b adds r3, r7, #4 800106e: 4619 mov r1, r3 8001070: 480c ldr r0, [pc, #48] @ (80010a4 ) 8001072: f010 f8f7 bl 8011264 8001076: 4603 mov r3, r0 8001078: 2b00 cmp r3, #0 800107a: d001 beq.n 8001080 { Error_Handler(); 800107c: f000 ff26 bl 8001ecc } /* USER CODE BEGIN TIM1_Init 2 */ memcpy(&fanTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 8001080: 4b0a ldr r3, [pc, #40] @ (80010ac ) 8001082: 461d mov r5, r3 8001084: f107 0430 add.w r4, r7, #48 @ 0x30 8001088: cc0f ldmia r4!, {r0, r1, r2, r3} 800108a: c50f stmia r5!, {r0, r1, r2, r3} 800108c: e894 0007 ldmia.w r4, {r0, r1, r2} 8001090: e885 0007 stmia.w r5, {r0, r1, r2} /* USER CODE END TIM1_Init 2 */ HAL_TIM_MspPostInit(&htim1); 8001094: 4803 ldr r0, [pc, #12] @ (80010a4 ) 8001096: f003 f9b1 bl 80043fc } 800109a: bf00 nop 800109c: 3758 adds r7, #88 @ 0x58 800109e: 46bd mov sp, r7 80010a0: bdb0 pop {r4, r5, r7, pc} 80010a2: bf00 nop 80010a4: 2400043c .word 0x2400043c 80010a8: 40010000 .word 0x40010000 80010ac: 240007a4 .word 0x240007a4 080010b0 : * @brief TIM2 Initialization Function * @param None * @retval None */ static void MX_TIM2_Init(void) { 80010b0: b580 push {r7, lr} 80010b2: b08c sub sp, #48 @ 0x30 80010b4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80010b6: f107 0320 add.w r3, r7, #32 80010ba: 2200 movs r2, #0 80010bc: 601a str r2, [r3, #0] 80010be: 605a str r2, [r3, #4] 80010c0: 609a str r2, [r3, #8] 80010c2: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 80010c4: f107 0314 add.w r3, r7, #20 80010c8: 2200 movs r2, #0 80010ca: 601a str r2, [r3, #0] 80010cc: 605a str r2, [r3, #4] 80010ce: 609a str r2, [r3, #8] TIM_IC_InitTypeDef sConfigIC = {0}; 80010d0: 1d3b adds r3, r7, #4 80010d2: 2200 movs r2, #0 80010d4: 601a str r2, [r3, #0] 80010d6: 605a str r2, [r3, #4] 80010d8: 609a str r2, [r3, #8] 80010da: 60da str r2, [r3, #12] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 80010dc: 4b32 ldr r3, [pc, #200] @ (80011a8 ) 80010de: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 80010e2: 601a str r2, [r3, #0] htim2.Init.Prescaler = 9999; 80010e4: 4b30 ldr r3, [pc, #192] @ (80011a8 ) 80010e6: f242 720f movw r2, #9999 @ 0x270f 80010ea: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 80010ec: 4b2e ldr r3, [pc, #184] @ (80011a8 ) 80010ee: 2200 movs r2, #0 80010f0: 609a str r2, [r3, #8] htim2.Init.Period = 2999; 80010f2: 4b2d ldr r3, [pc, #180] @ (80011a8 ) 80010f4: f640 32b7 movw r2, #2999 @ 0xbb7 80010f8: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2; 80010fa: 4b2b ldr r3, [pc, #172] @ (80011a8 ) 80010fc: f44f 7280 mov.w r2, #256 @ 0x100 8001100: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001102: 4b29 ldr r3, [pc, #164] @ (80011a8 ) 8001104: 2280 movs r2, #128 @ 0x80 8001106: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 8001108: 4827 ldr r0, [pc, #156] @ (80011a8 ) 800110a: f00e f979 bl 800f400 800110e: 4603 mov r3, r0 8001110: 2b00 cmp r3, #0 8001112: d001 beq.n 8001118 { Error_Handler(); 8001114: f000 feda bl 8001ecc } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8001118: f44f 5380 mov.w r3, #4096 @ 0x1000 800111c: 623b str r3, [r7, #32] if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 800111e: f107 0320 add.w r3, r7, #32 8001122: 4619 mov r1, r3 8001124: 4820 ldr r0, [pc, #128] @ (80011a8 ) 8001126: f00f f911 bl 801034c 800112a: 4603 mov r3, r0 800112c: 2b00 cmp r3, #0 800112e: d001 beq.n 8001134 { Error_Handler(); 8001130: f000 fecc bl 8001ecc } if (HAL_TIM_IC_Init(&htim2) != HAL_OK) 8001134: 481c ldr r0, [pc, #112] @ (80011a8 ) 8001136: f00e fc9f bl 800fa78 800113a: 4603 mov r3, r0 800113c: 2b00 cmp r3, #0 800113e: d001 beq.n 8001144 { Error_Handler(); 8001140: f000 fec4 bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 8001144: 2320 movs r3, #32 8001146: 617b str r3, [r7, #20] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; 8001148: 2380 movs r3, #128 @ 0x80 800114a: 61fb str r3, [r7, #28] if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 800114c: f107 0314 add.w r3, r7, #20 8001150: 4619 mov r1, r3 8001152: 4815 ldr r0, [pc, #84] @ (80011a8 ) 8001154: f00f fff8 bl 8011148 8001158: 4603 mov r3, r0 800115a: 2b00 cmp r3, #0 800115c: d001 beq.n 8001162 { Error_Handler(); 800115e: f000 feb5 bl 8001ecc } sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING; 8001162: 2300 movs r3, #0 8001164: 607b str r3, [r7, #4] sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI; 8001166: 2301 movs r3, #1 8001168: 60bb str r3, [r7, #8] sConfigIC.ICPrescaler = TIM_ICPSC_DIV1; 800116a: 2300 movs r3, #0 800116c: 60fb str r3, [r7, #12] sConfigIC.ICFilter = 0; 800116e: 2300 movs r3, #0 8001170: 613b str r3, [r7, #16] if (HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_3) != HAL_OK) 8001172: 1d3b adds r3, r7, #4 8001174: 2208 movs r2, #8 8001176: 4619 mov r1, r3 8001178: 480b ldr r0, [pc, #44] @ (80011a8 ) 800117a: f00e ff36 bl 800ffea 800117e: 4603 mov r3, r0 8001180: 2b00 cmp r3, #0 8001182: d001 beq.n 8001188 { Error_Handler(); 8001184: f000 fea2 bl 8001ecc } if (HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_4) != HAL_OK) 8001188: 1d3b adds r3, r7, #4 800118a: 220c movs r2, #12 800118c: 4619 mov r1, r3 800118e: 4806 ldr r0, [pc, #24] @ (80011a8 ) 8001190: f00e ff2b bl 800ffea 8001194: 4603 mov r3, r0 8001196: 2b00 cmp r3, #0 8001198: d001 beq.n 800119e { Error_Handler(); 800119a: f000 fe97 bl 8001ecc } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ } 800119e: bf00 nop 80011a0: 3730 adds r7, #48 @ 0x30 80011a2: 46bd mov sp, r7 80011a4: bd80 pop {r7, pc} 80011a6: bf00 nop 80011a8: 24000488 .word 0x24000488 080011ac : * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { 80011ac: b5b0 push {r4, r5, r7, lr} 80011ae: b08a sub sp, #40 @ 0x28 80011b0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 80011b2: f107 031c add.w r3, r7, #28 80011b6: 2200 movs r2, #0 80011b8: 601a str r2, [r3, #0] 80011ba: 605a str r2, [r3, #4] 80011bc: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 80011be: 463b mov r3, r7 80011c0: 2200 movs r2, #0 80011c2: 601a str r2, [r3, #0] 80011c4: 605a str r2, [r3, #4] 80011c6: 609a str r2, [r3, #8] 80011c8: 60da str r2, [r3, #12] 80011ca: 611a str r2, [r3, #16] 80011cc: 615a str r2, [r3, #20] 80011ce: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 80011d0: 4b48 ldr r3, [pc, #288] @ (80012f4 ) 80011d2: 4a49 ldr r2, [pc, #292] @ (80012f8 ) 80011d4: 601a str r2, [r3, #0] htim3.Init.Prescaler = 199; 80011d6: 4b47 ldr r3, [pc, #284] @ (80012f4 ) 80011d8: 22c7 movs r2, #199 @ 0xc7 80011da: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 80011dc: 4b45 ldr r3, [pc, #276] @ (80012f4 ) 80011de: 2200 movs r2, #0 80011e0: 609a str r2, [r3, #8] htim3.Init.Period = 999; 80011e2: 4b44 ldr r3, [pc, #272] @ (80012f4 ) 80011e4: f240 32e7 movw r2, #999 @ 0x3e7 80011e8: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80011ea: 4b42 ldr r3, [pc, #264] @ (80012f4 ) 80011ec: 2200 movs r2, #0 80011ee: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 80011f0: 4b40 ldr r3, [pc, #256] @ (80012f4 ) 80011f2: 2280 movs r2, #128 @ 0x80 80011f4: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 80011f6: 483f ldr r0, [pc, #252] @ (80012f4 ) 80011f8: f00e fa42 bl 800f680 80011fc: 4603 mov r3, r0 80011fe: 2b00 cmp r3, #0 8001200: d001 beq.n 8001206 { Error_Handler(); 8001202: f000 fe63 bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001206: 2300 movs r3, #0 8001208: 61fb str r3, [r7, #28] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800120a: 2300 movs r3, #0 800120c: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800120e: f107 031c add.w r3, r7, #28 8001212: 4619 mov r1, r3 8001214: 4837 ldr r0, [pc, #220] @ (80012f4 ) 8001216: f00f ff97 bl 8011148 800121a: 4603 mov r3, r0 800121c: 2b00 cmp r3, #0 800121e: d001 beq.n 8001224 { Error_Handler(); 8001220: f000 fe54 bl 8001ecc } sConfigOC.OCMode = TIM_OCMODE_COMBINED_PWM1; 8001224: 4b35 ldr r3, [pc, #212] @ (80012fc ) 8001226: 603b str r3, [r7, #0] sConfigOC.Pulse = 500; 8001228: f44f 73fa mov.w r3, #500 @ 0x1f4 800122c: 607b str r3, [r7, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800122e: 2300 movs r3, #0 8001230: 60bb str r3, [r7, #8] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001232: 2300 movs r3, #0 8001234: 613b str r3, [r7, #16] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8001236: 463b mov r3, r7 8001238: 2200 movs r2, #0 800123a: 4619 mov r1, r3 800123c: 482d ldr r0, [pc, #180] @ (80012f4 ) 800123e: f00e ff71 bl 8010124 8001242: 4603 mov r3, r0 8001244: 2b00 cmp r3, #0 8001246: d001 beq.n 800124c { Error_Handler(); 8001248: f000 fe40 bl 8001ecc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_1); 800124c: 4b29 ldr r3, [pc, #164] @ (80012f4 ) 800124e: 681b ldr r3, [r3, #0] 8001250: 699a ldr r2, [r3, #24] 8001252: 4b28 ldr r3, [pc, #160] @ (80012f4 ) 8001254: 681b ldr r3, [r3, #0] 8001256: f022 0208 bic.w r2, r2, #8 800125a: 619a str r2, [r3, #24] sConfigOC.OCMode = TIM_OCMODE_PWM1; 800125c: 2360 movs r3, #96 @ 0x60 800125e: 603b str r3, [r7, #0] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8001260: 463b mov r3, r7 8001262: 2204 movs r2, #4 8001264: 4619 mov r1, r3 8001266: 4823 ldr r0, [pc, #140] @ (80012f4 ) 8001268: f00e ff5c bl 8010124 800126c: 4603 mov r3, r0 800126e: 2b00 cmp r3, #0 8001270: d001 beq.n 8001276 { Error_Handler(); 8001272: f000 fe2b bl 8001ecc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_2); 8001276: 4b1f ldr r3, [pc, #124] @ (80012f4 ) 8001278: 681b ldr r3, [r3, #0] 800127a: 699a ldr r2, [r3, #24] 800127c: 4b1d ldr r3, [pc, #116] @ (80012f4 ) 800127e: 681b ldr r3, [r3, #0] 8001280: f422 6200 bic.w r2, r2, #2048 @ 0x800 8001284: 619a str r2, [r3, #24] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 8001286: 463b mov r3, r7 8001288: 2208 movs r2, #8 800128a: 4619 mov r1, r3 800128c: 4819 ldr r0, [pc, #100] @ (80012f4 ) 800128e: f00e ff49 bl 8010124 8001292: 4603 mov r3, r0 8001294: 2b00 cmp r3, #0 8001296: d001 beq.n 800129c { Error_Handler(); 8001298: f000 fe18 bl 8001ecc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_3); 800129c: 4b15 ldr r3, [pc, #84] @ (80012f4 ) 800129e: 681b ldr r3, [r3, #0] 80012a0: 69da ldr r2, [r3, #28] 80012a2: 4b14 ldr r3, [pc, #80] @ (80012f4 ) 80012a4: 681b ldr r3, [r3, #0] 80012a6: f022 0208 bic.w r2, r2, #8 80012aa: 61da str r2, [r3, #28] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 80012ac: 463b mov r3, r7 80012ae: 220c movs r2, #12 80012b0: 4619 mov r1, r3 80012b2: 4810 ldr r0, [pc, #64] @ (80012f4 ) 80012b4: f00e ff36 bl 8010124 80012b8: 4603 mov r3, r0 80012ba: 2b00 cmp r3, #0 80012bc: d001 beq.n 80012c2 { Error_Handler(); 80012be: f000 fe05 bl 8001ecc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_4); 80012c2: 4b0c ldr r3, [pc, #48] @ (80012f4 ) 80012c4: 681b ldr r3, [r3, #0] 80012c6: 69da ldr r2, [r3, #28] 80012c8: 4b0a ldr r3, [pc, #40] @ (80012f4 ) 80012ca: 681b ldr r3, [r3, #0] 80012cc: f422 6200 bic.w r2, r2, #2048 @ 0x800 80012d0: 61da str r2, [r3, #28] /* USER CODE BEGIN TIM3_Init 2 */ memcpy(&motorXYTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 80012d2: 4b0b ldr r3, [pc, #44] @ (8001300 ) 80012d4: 461d mov r5, r3 80012d6: 463c mov r4, r7 80012d8: cc0f ldmia r4!, {r0, r1, r2, r3} 80012da: c50f stmia r5!, {r0, r1, r2, r3} 80012dc: e894 0007 ldmia.w r4, {r0, r1, r2} 80012e0: e885 0007 stmia.w r5, {r0, r1, r2} /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 80012e4: 4803 ldr r0, [pc, #12] @ (80012f4 ) 80012e6: f003 f889 bl 80043fc } 80012ea: bf00 nop 80012ec: 3728 adds r7, #40 @ 0x28 80012ee: 46bd mov sp, r7 80012f0: bdb0 pop {r4, r5, r7, pc} 80012f2: bf00 nop 80012f4: 240004d4 .word 0x240004d4 80012f8: 40000400 .word 0x40000400 80012fc: 00010040 .word 0x00010040 8001300: 240007c0 .word 0x240007c0 08001304 : * @brief TIM4 Initialization Function * @param None * @retval None */ static void MX_TIM4_Init(void) { 8001304: b580 push {r7, lr} 8001306: b08c sub sp, #48 @ 0x30 8001308: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800130a: f107 0320 add.w r3, r7, #32 800130e: 2200 movs r2, #0 8001310: 601a str r2, [r3, #0] 8001312: 605a str r2, [r3, #4] 8001314: 609a str r2, [r3, #8] 8001316: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001318: f107 0314 add.w r3, r7, #20 800131c: 2200 movs r2, #0 800131e: 601a str r2, [r3, #0] 8001320: 605a str r2, [r3, #4] 8001322: 609a str r2, [r3, #8] TIM_IC_InitTypeDef sConfigIC = {0}; 8001324: 1d3b adds r3, r7, #4 8001326: 2200 movs r2, #0 8001328: 601a str r2, [r3, #0] 800132a: 605a str r2, [r3, #4] 800132c: 609a str r2, [r3, #8] 800132e: 60da str r2, [r3, #12] /* USER CODE BEGIN TIM4_Init 1 */ /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; 8001330: 4b31 ldr r3, [pc, #196] @ (80013f8 ) 8001332: 4a32 ldr r2, [pc, #200] @ (80013fc ) 8001334: 601a str r2, [r3, #0] htim4.Init.Prescaler = 9999; 8001336: 4b30 ldr r3, [pc, #192] @ (80013f8 ) 8001338: f242 720f movw r2, #9999 @ 0x270f 800133c: 605a str r2, [r3, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 800133e: 4b2e ldr r3, [pc, #184] @ (80013f8 ) 8001340: 2200 movs r2, #0 8001342: 609a str r2, [r3, #8] htim4.Init.Period = 2999; 8001344: 4b2c ldr r3, [pc, #176] @ (80013f8 ) 8001346: f640 32b7 movw r2, #2999 @ 0xbb7 800134a: 60da str r2, [r3, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2; 800134c: 4b2a ldr r3, [pc, #168] @ (80013f8 ) 800134e: f44f 7280 mov.w r2, #256 @ 0x100 8001352: 611a str r2, [r3, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001354: 4b28 ldr r3, [pc, #160] @ (80013f8 ) 8001356: 2280 movs r2, #128 @ 0x80 8001358: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 800135a: 4827 ldr r0, [pc, #156] @ (80013f8 ) 800135c: f00e f850 bl 800f400 8001360: 4603 mov r3, r0 8001362: 2b00 cmp r3, #0 8001364: d001 beq.n 800136a { Error_Handler(); 8001366: f000 fdb1 bl 8001ecc } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800136a: f44f 5380 mov.w r3, #4096 @ 0x1000 800136e: 623b str r3, [r7, #32] if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 8001370: f107 0320 add.w r3, r7, #32 8001374: 4619 mov r1, r3 8001376: 4820 ldr r0, [pc, #128] @ (80013f8 ) 8001378: f00e ffe8 bl 801034c 800137c: 4603 mov r3, r0 800137e: 2b00 cmp r3, #0 8001380: d001 beq.n 8001386 { Error_Handler(); 8001382: f000 fda3 bl 8001ecc } if (HAL_TIM_IC_Init(&htim4) != HAL_OK) 8001386: 481c ldr r0, [pc, #112] @ (80013f8 ) 8001388: f00e fb76 bl 800fa78 800138c: 4603 mov r3, r0 800138e: 2b00 cmp r3, #0 8001390: d001 beq.n 8001396 { Error_Handler(); 8001392: f000 fd9b bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001396: 2300 movs r3, #0 8001398: 617b str r3, [r7, #20] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800139a: 2300 movs r3, #0 800139c: 61fb str r3, [r7, #28] if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 800139e: f107 0314 add.w r3, r7, #20 80013a2: 4619 mov r1, r3 80013a4: 4814 ldr r0, [pc, #80] @ (80013f8 ) 80013a6: f00f fecf bl 8011148 80013aa: 4603 mov r3, r0 80013ac: 2b00 cmp r3, #0 80013ae: d001 beq.n 80013b4 { Error_Handler(); 80013b0: f000 fd8c bl 8001ecc } sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING; 80013b4: 2300 movs r3, #0 80013b6: 607b str r3, [r7, #4] sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI; 80013b8: 2301 movs r3, #1 80013ba: 60bb str r3, [r7, #8] sConfigIC.ICPrescaler = TIM_ICPSC_DIV1; 80013bc: 2300 movs r3, #0 80013be: 60fb str r3, [r7, #12] sConfigIC.ICFilter = 0; 80013c0: 2300 movs r3, #0 80013c2: 613b str r3, [r7, #16] if (HAL_TIM_IC_ConfigChannel(&htim4, &sConfigIC, TIM_CHANNEL_3) != HAL_OK) 80013c4: 1d3b adds r3, r7, #4 80013c6: 2208 movs r2, #8 80013c8: 4619 mov r1, r3 80013ca: 480b ldr r0, [pc, #44] @ (80013f8 ) 80013cc: f00e fe0d bl 800ffea 80013d0: 4603 mov r3, r0 80013d2: 2b00 cmp r3, #0 80013d4: d001 beq.n 80013da { Error_Handler(); 80013d6: f000 fd79 bl 8001ecc } if (HAL_TIM_IC_ConfigChannel(&htim4, &sConfigIC, TIM_CHANNEL_4) != HAL_OK) 80013da: 1d3b adds r3, r7, #4 80013dc: 220c movs r2, #12 80013de: 4619 mov r1, r3 80013e0: 4805 ldr r0, [pc, #20] @ (80013f8 ) 80013e2: f00e fe02 bl 800ffea 80013e6: 4603 mov r3, r0 80013e8: 2b00 cmp r3, #0 80013ea: d001 beq.n 80013f0 { Error_Handler(); 80013ec: f000 fd6e bl 8001ecc } /* USER CODE BEGIN TIM4_Init 2 */ /* USER CODE END TIM4_Init 2 */ } 80013f0: bf00 nop 80013f2: 3730 adds r7, #48 @ 0x30 80013f4: 46bd mov sp, r7 80013f6: bd80 pop {r7, pc} 80013f8: 24000520 .word 0x24000520 80013fc: 40000800 .word 0x40000800 08001400 : * @brief TIM8 Initialization Function * @param None * @retval None */ static void MX_TIM8_Init(void) { 8001400: b580 push {r7, lr} 8001402: b088 sub sp, #32 8001404: af00 add r7, sp, #0 /* USER CODE BEGIN TIM8_Init 0 */ /* USER CODE END TIM8_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8001406: f107 0310 add.w r3, r7, #16 800140a: 2200 movs r2, #0 800140c: 601a str r2, [r3, #0] 800140e: 605a str r2, [r3, #4] 8001410: 609a str r2, [r3, #8] 8001412: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001414: 1d3b adds r3, r7, #4 8001416: 2200 movs r2, #0 8001418: 601a str r2, [r3, #0] 800141a: 605a str r2, [r3, #4] 800141c: 609a str r2, [r3, #8] /* USER CODE BEGIN TIM8_Init 1 */ /* USER CODE END TIM8_Init 1 */ htim8.Instance = TIM8; 800141e: 4b21 ldr r3, [pc, #132] @ (80014a4 ) 8001420: 4a21 ldr r2, [pc, #132] @ (80014a8 ) 8001422: 601a str r2, [r3, #0] htim8.Init.Prescaler = 9999; 8001424: 4b1f ldr r3, [pc, #124] @ (80014a4 ) 8001426: f242 720f movw r2, #9999 @ 0x270f 800142a: 605a str r2, [r3, #4] htim8.Init.CounterMode = TIM_COUNTERMODE_UP; 800142c: 4b1d ldr r3, [pc, #116] @ (80014a4 ) 800142e: 2200 movs r2, #0 8001430: 609a str r2, [r3, #8] htim8.Init.Period = 999; 8001432: 4b1c ldr r3, [pc, #112] @ (80014a4 ) 8001434: f240 32e7 movw r2, #999 @ 0x3e7 8001438: 60da str r2, [r3, #12] htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2; 800143a: 4b1a ldr r3, [pc, #104] @ (80014a4 ) 800143c: f44f 7280 mov.w r2, #256 @ 0x100 8001440: 611a str r2, [r3, #16] htim8.Init.RepetitionCounter = 0; 8001442: 4b18 ldr r3, [pc, #96] @ (80014a4 ) 8001444: 2200 movs r2, #0 8001446: 615a str r2, [r3, #20] htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001448: 4b16 ldr r3, [pc, #88] @ (80014a4 ) 800144a: 2280 movs r2, #128 @ 0x80 800144c: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim8) != HAL_OK) 800144e: 4815 ldr r0, [pc, #84] @ (80014a4 ) 8001450: f00d ffd6 bl 800f400 8001454: 4603 mov r3, r0 8001456: 2b00 cmp r3, #0 8001458: d001 beq.n 800145e { Error_Handler(); 800145a: f000 fd37 bl 8001ecc } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800145e: f44f 5380 mov.w r3, #4096 @ 0x1000 8001462: 613b str r3, [r7, #16] if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) 8001464: f107 0310 add.w r3, r7, #16 8001468: 4619 mov r1, r3 800146a: 480e ldr r0, [pc, #56] @ (80014a4 ) 800146c: f00e ff6e bl 801034c 8001470: 4603 mov r3, r0 8001472: 2b00 cmp r3, #0 8001474: d001 beq.n 800147a { Error_Handler(); 8001476: f000 fd29 bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 800147a: 2320 movs r3, #32 800147c: 607b str r3, [r7, #4] sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 800147e: 2300 movs r3, #0 8001480: 60bb str r3, [r7, #8] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; 8001482: 2380 movs r3, #128 @ 0x80 8001484: 60fb str r3, [r7, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 8001486: 1d3b adds r3, r7, #4 8001488: 4619 mov r1, r3 800148a: 4806 ldr r0, [pc, #24] @ (80014a4 ) 800148c: f00f fe5c bl 8011148 8001490: 4603 mov r3, r0 8001492: 2b00 cmp r3, #0 8001494: d001 beq.n 800149a { Error_Handler(); 8001496: f000 fd19 bl 8001ecc } /* USER CODE BEGIN TIM8_Init 2 */ /* USER CODE END TIM8_Init 2 */ } 800149a: bf00 nop 800149c: 3720 adds r7, #32 800149e: 46bd mov sp, r7 80014a0: bd80 pop {r7, pc} 80014a2: bf00 nop 80014a4: 2400056c .word 0x2400056c 80014a8: 40010400 .word 0x40010400 080014ac : * @brief UART8 Initialization Function * @param None * @retval None */ static void MX_UART8_Init(void) { 80014ac: b580 push {r7, lr} 80014ae: af00 add r7, sp, #0 /* USER CODE END UART8_Init 0 */ /* USER CODE BEGIN UART8_Init 1 */ /* USER CODE END UART8_Init 1 */ huart8.Instance = UART8; 80014b0: 4b22 ldr r3, [pc, #136] @ (800153c ) 80014b2: 4a23 ldr r2, [pc, #140] @ (8001540 ) 80014b4: 601a str r2, [r3, #0] huart8.Init.BaudRate = 115200; 80014b6: 4b21 ldr r3, [pc, #132] @ (800153c ) 80014b8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80014bc: 605a str r2, [r3, #4] huart8.Init.WordLength = UART_WORDLENGTH_8B; 80014be: 4b1f ldr r3, [pc, #124] @ (800153c ) 80014c0: 2200 movs r2, #0 80014c2: 609a str r2, [r3, #8] huart8.Init.StopBits = UART_STOPBITS_1; 80014c4: 4b1d ldr r3, [pc, #116] @ (800153c ) 80014c6: 2200 movs r2, #0 80014c8: 60da str r2, [r3, #12] huart8.Init.Parity = UART_PARITY_NONE; 80014ca: 4b1c ldr r3, [pc, #112] @ (800153c ) 80014cc: 2200 movs r2, #0 80014ce: 611a str r2, [r3, #16] huart8.Init.Mode = UART_MODE_TX_RX; 80014d0: 4b1a ldr r3, [pc, #104] @ (800153c ) 80014d2: 220c movs r2, #12 80014d4: 615a str r2, [r3, #20] huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80014d6: 4b19 ldr r3, [pc, #100] @ (800153c ) 80014d8: 2200 movs r2, #0 80014da: 619a str r2, [r3, #24] huart8.Init.OverSampling = UART_OVERSAMPLING_16; 80014dc: 4b17 ldr r3, [pc, #92] @ (800153c ) 80014de: 2200 movs r2, #0 80014e0: 61da str r2, [r3, #28] huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 80014e2: 4b16 ldr r3, [pc, #88] @ (800153c ) 80014e4: 2200 movs r2, #0 80014e6: 621a str r2, [r3, #32] huart8.Init.ClockPrescaler = UART_PRESCALER_DIV1; 80014e8: 4b14 ldr r3, [pc, #80] @ (800153c ) 80014ea: 2200 movs r2, #0 80014ec: 625a str r2, [r3, #36] @ 0x24 huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 80014ee: 4b13 ldr r3, [pc, #76] @ (800153c ) 80014f0: 2200 movs r2, #0 80014f2: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart8) != HAL_OK) 80014f4: 4811 ldr r0, [pc, #68] @ (800153c ) 80014f6: f00f ff51 bl 801139c 80014fa: 4603 mov r3, r0 80014fc: 2b00 cmp r3, #0 80014fe: d001 beq.n 8001504 { Error_Handler(); 8001500: f000 fce4 bl 8001ecc } if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8001504: 2100 movs r1, #0 8001506: 480d ldr r0, [pc, #52] @ (800153c ) 8001508: f012 fbf1 bl 8013cee 800150c: 4603 mov r3, r0 800150e: 2b00 cmp r3, #0 8001510: d001 beq.n 8001516 { Error_Handler(); 8001512: f000 fcdb bl 8001ecc } if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8001516: 2100 movs r1, #0 8001518: 4808 ldr r0, [pc, #32] @ (800153c ) 800151a: f012 fc26 bl 8013d6a 800151e: 4603 mov r3, r0 8001520: 2b00 cmp r3, #0 8001522: d001 beq.n 8001528 { Error_Handler(); 8001524: f000 fcd2 bl 8001ecc } if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK) 8001528: 4804 ldr r0, [pc, #16] @ (800153c ) 800152a: f012 fba7 bl 8013c7c 800152e: 4603 mov r3, r0 8001530: 2b00 cmp r3, #0 8001532: d001 beq.n 8001538 { Error_Handler(); 8001534: f000 fcca bl 8001ecc } /* USER CODE BEGIN UART8_Init 2 */ /* USER CODE END UART8_Init 2 */ } 8001538: bf00 nop 800153a: bd80 pop {r7, pc} 800153c: 240005b8 .word 0x240005b8 8001540: 40007c00 .word 0x40007c00 08001544 : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 8001544: b580 push {r7, lr} 8001546: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8001548: 4b24 ldr r3, [pc, #144] @ (80015dc ) 800154a: 4a25 ldr r2, [pc, #148] @ (80015e0 ) 800154c: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800154e: 4b23 ldr r3, [pc, #140] @ (80015dc ) 8001550: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001554: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8001556: 4b21 ldr r3, [pc, #132] @ (80015dc ) 8001558: 2200 movs r2, #0 800155a: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 800155c: 4b1f ldr r3, [pc, #124] @ (80015dc ) 800155e: 2200 movs r2, #0 8001560: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8001562: 4b1e ldr r3, [pc, #120] @ (80015dc ) 8001564: 2200 movs r2, #0 8001566: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8001568: 4b1c ldr r3, [pc, #112] @ (80015dc ) 800156a: 220c movs r2, #12 800156c: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800156e: 4b1b ldr r3, [pc, #108] @ (80015dc ) 8001570: 2200 movs r2, #0 8001572: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8001574: 4b19 ldr r3, [pc, #100] @ (80015dc ) 8001576: 2200 movs r2, #0 8001578: 61da str r2, [r3, #28] huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 800157a: 4b18 ldr r3, [pc, #96] @ (80015dc ) 800157c: 2200 movs r2, #0 800157e: 621a str r2, [r3, #32] huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8001580: 4b16 ldr r3, [pc, #88] @ (80015dc ) 8001582: 2200 movs r2, #0 8001584: 625a str r2, [r3, #36] @ 0x24 huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_TXINVERT_INIT; 8001586: 4b15 ldr r3, [pc, #84] @ (80015dc ) 8001588: 2201 movs r2, #1 800158a: 629a str r2, [r3, #40] @ 0x28 huart1.AdvancedInit.TxPinLevelInvert = UART_ADVFEATURE_TXINV_ENABLE; 800158c: 4b13 ldr r3, [pc, #76] @ (80015dc ) 800158e: f44f 3200 mov.w r2, #131072 @ 0x20000 8001592: 62da str r2, [r3, #44] @ 0x2c if (HAL_UART_Init(&huart1) != HAL_OK) 8001594: 4811 ldr r0, [pc, #68] @ (80015dc ) 8001596: f00f ff01 bl 801139c 800159a: 4603 mov r3, r0 800159c: 2b00 cmp r3, #0 800159e: d001 beq.n 80015a4 { Error_Handler(); 80015a0: f000 fc94 bl 8001ecc } if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 80015a4: 2100 movs r1, #0 80015a6: 480d ldr r0, [pc, #52] @ (80015dc ) 80015a8: f012 fba1 bl 8013cee 80015ac: 4603 mov r3, r0 80015ae: 2b00 cmp r3, #0 80015b0: d001 beq.n 80015b6 { Error_Handler(); 80015b2: f000 fc8b bl 8001ecc } if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 80015b6: 2100 movs r1, #0 80015b8: 4808 ldr r0, [pc, #32] @ (80015dc ) 80015ba: f012 fbd6 bl 8013d6a 80015be: 4603 mov r3, r0 80015c0: 2b00 cmp r3, #0 80015c2: d001 beq.n 80015c8 { Error_Handler(); 80015c4: f000 fc82 bl 8001ecc } if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) 80015c8: 4804 ldr r0, [pc, #16] @ (80015dc ) 80015ca: f012 fb57 bl 8013c7c 80015ce: 4603 mov r3, r0 80015d0: 2b00 cmp r3, #0 80015d2: d001 beq.n 80015d8 { Error_Handler(); 80015d4: f000 fc7a bl 8001ecc } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 80015d8: bf00 nop 80015da: bd80 pop {r7, pc} 80015dc: 2400064c .word 0x2400064c 80015e0: 40011000 .word 0x40011000 080015e4 : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 80015e4: b580 push {r7, lr} 80015e6: b082 sub sp, #8 80015e8: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 80015ea: 4b15 ldr r3, [pc, #84] @ (8001640 ) 80015ec: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 80015f0: 4a13 ldr r2, [pc, #76] @ (8001640 ) 80015f2: f043 0301 orr.w r3, r3, #1 80015f6: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 80015fa: 4b11 ldr r3, [pc, #68] @ (8001640 ) 80015fc: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8001600: f003 0301 and.w r3, r3, #1 8001604: 607b str r3, [r7, #4] 8001606: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0); 8001608: 2200 movs r2, #0 800160a: 2105 movs r1, #5 800160c: 200b movs r0, #11 800160e: f006 fa9b bl 8007b48 HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 8001612: 200b movs r0, #11 8001614: f006 fab2 bl 8007b7c /* DMA1_Stream1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0); 8001618: 2200 movs r2, #0 800161a: 2105 movs r1, #5 800161c: 200c movs r0, #12 800161e: f006 fa93 bl 8007b48 HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn); 8001622: 200c movs r0, #12 8001624: f006 faaa bl 8007b7c /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0); 8001628: 2200 movs r2, #0 800162a: 2105 movs r1, #5 800162c: 200d movs r0, #13 800162e: f006 fa8b bl 8007b48 HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 8001632: 200d movs r0, #13 8001634: f006 faa2 bl 8007b7c } 8001638: bf00 nop 800163a: 3708 adds r7, #8 800163c: 46bd mov sp, r7 800163e: bd80 pop {r7, pc} 8001640: 58024400 .word 0x58024400 08001644 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8001644: b580 push {r7, lr} 8001646: b08c sub sp, #48 @ 0x30 8001648: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800164a: f107 031c add.w r3, r7, #28 800164e: 2200 movs r2, #0 8001650: 601a str r2, [r3, #0] 8001652: 605a str r2, [r3, #4] 8001654: 609a str r2, [r3, #8] 8001656: 60da str r2, [r3, #12] 8001658: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 800165a: 4b58 ldr r3, [pc, #352] @ (80017bc ) 800165c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001660: 4a56 ldr r2, [pc, #344] @ (80017bc ) 8001662: f043 0380 orr.w r3, r3, #128 @ 0x80 8001666: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800166a: 4b54 ldr r3, [pc, #336] @ (80017bc ) 800166c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001670: f003 0380 and.w r3, r3, #128 @ 0x80 8001674: 61bb str r3, [r7, #24] 8001676: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOC_CLK_ENABLE(); 8001678: 4b50 ldr r3, [pc, #320] @ (80017bc ) 800167a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800167e: 4a4f ldr r2, [pc, #316] @ (80017bc ) 8001680: f043 0304 orr.w r3, r3, #4 8001684: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001688: 4b4c ldr r3, [pc, #304] @ (80017bc ) 800168a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800168e: f003 0304 and.w r3, r3, #4 8001692: 617b str r3, [r7, #20] 8001694: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001696: 4b49 ldr r3, [pc, #292] @ (80017bc ) 8001698: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800169c: 4a47 ldr r2, [pc, #284] @ (80017bc ) 800169e: f043 0301 orr.w r3, r3, #1 80016a2: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80016a6: 4b45 ldr r3, [pc, #276] @ (80017bc ) 80016a8: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016ac: f003 0301 and.w r3, r3, #1 80016b0: 613b str r3, [r7, #16] 80016b2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80016b4: 4b41 ldr r3, [pc, #260] @ (80017bc ) 80016b6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016ba: 4a40 ldr r2, [pc, #256] @ (80017bc ) 80016bc: f043 0302 orr.w r3, r3, #2 80016c0: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80016c4: 4b3d ldr r3, [pc, #244] @ (80017bc ) 80016c6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016ca: f003 0302 and.w r3, r3, #2 80016ce: 60fb str r3, [r7, #12] 80016d0: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 80016d2: 4b3a ldr r3, [pc, #232] @ (80017bc ) 80016d4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016d8: 4a38 ldr r2, [pc, #224] @ (80017bc ) 80016da: f043 0310 orr.w r3, r3, #16 80016de: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80016e2: 4b36 ldr r3, [pc, #216] @ (80017bc ) 80016e4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016e8: f003 0310 and.w r3, r3, #16 80016ec: 60bb str r3, [r7, #8] 80016ee: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 80016f0: 4b32 ldr r3, [pc, #200] @ (80017bc ) 80016f2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016f6: 4a31 ldr r2, [pc, #196] @ (80017bc ) 80016f8: f043 0308 orr.w r3, r3, #8 80016fc: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001700: 4b2e ldr r3, [pc, #184] @ (80017bc ) 8001702: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001706: f003 0308 and.w r3, r3, #8 800170a: 607b str r3, [r7, #4] 800170c: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 800170e: 2200 movs r2, #0 8001710: f24e 7180 movw r1, #59264 @ 0xe780 8001714: 482a ldr r0, [pc, #168] @ (80017c0 ) 8001716: f009 ff11 bl 800b53c |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET); 800171a: 2200 movs r2, #0 800171c: 21f0 movs r1, #240 @ 0xf0 800171e: 4829 ldr r0, [pc, #164] @ (80017c4 ) 8001720: f009 ff0c bl 800b53c /*Configure GPIO pins : PE7 PE8 PE9 PE10 PE13 PE14 PE15 */ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 8001724: f24e 7380 movw r3, #59264 @ 0xe780 8001728: 61fb str r3, [r7, #28] |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800172a: 2301 movs r3, #1 800172c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800172e: 2300 movs r3, #0 8001730: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001732: 2300 movs r3, #0 8001734: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8001736: f107 031c add.w r3, r7, #28 800173a: 4619 mov r1, r3 800173c: 4820 ldr r0, [pc, #128] @ (80017c0 ) 800173e: f009 fd35 bl 800b1ac /*Configure GPIO pins : PD8 PD9 PD10 PD11 PD12 PD13 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 8001742: f44f 537c mov.w r3, #16128 @ 0x3f00 8001746: 61fb str r3, [r7, #28] |GPIO_PIN_12|GPIO_PIN_13; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 8001748: f44f 1344 mov.w r3, #3211264 @ 0x310000 800174c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800174e: 2300 movs r3, #0 8001750: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001752: f107 031c add.w r3, r7, #28 8001756: 4619 mov r1, r3 8001758: 481a ldr r0, [pc, #104] @ (80017c4 ) 800175a: f009 fd27 bl 800b1ac /*Configure GPIO pin : PD3 */ GPIO_InitStruct.Pin = GPIO_PIN_3; 800175e: 2308 movs r3, #8 8001760: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001762: 2300 movs r3, #0 8001764: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001766: 2300 movs r3, #0 8001768: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800176a: f107 031c add.w r3, r7, #28 800176e: 4619 mov r1, r3 8001770: 4814 ldr r0, [pc, #80] @ (80017c4 ) 8001772: f009 fd1b bl 800b1ac /*Configure GPIO pins : PD4 PD5 PD6 PD7 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; 8001776: 23f0 movs r3, #240 @ 0xf0 8001778: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800177a: 2301 movs r3, #1 800177c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800177e: 2300 movs r3, #0 8001780: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001782: 2300 movs r3, #0 8001784: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001786: f107 031c add.w r3, r7, #28 800178a: 4619 mov r1, r3 800178c: 480d ldr r0, [pc, #52] @ (80017c4 ) 800178e: f009 fd0d bl 800b1ac /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0); 8001792: 2200 movs r2, #0 8001794: 2105 movs r1, #5 8001796: 2017 movs r0, #23 8001798: f006 f9d6 bl 8007b48 HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); 800179c: 2017 movs r0, #23 800179e: f006 f9ed bl 8007b7c HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0); 80017a2: 2200 movs r2, #0 80017a4: 2105 movs r1, #5 80017a6: 2028 movs r0, #40 @ 0x28 80017a8: f006 f9ce bl 8007b48 HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); 80017ac: 2028 movs r0, #40 @ 0x28 80017ae: f006 f9e5 bl 8007b7c /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 80017b2: bf00 nop 80017b4: 3730 adds r7, #48 @ 0x30 80017b6: 46bd mov sp, r7 80017b8: bd80 pop {r7, pc} 80017ba: bf00 nop 80017bc: 58024400 .word 0x58024400 80017c0: 58021000 .word 0x58021000 80017c4: 58020c00 .word 0x58020c00 080017c8 : /* USER CODE BEGIN 4 */ void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { 80017c8: b580 push {r7, lr} 80017ca: b08e sub sp, #56 @ 0x38 80017cc: af00 add r7, sp, #0 80017ce: 6078 str r0, [r7, #4] if(hadc->Instance == ADC1) 80017d0: 687b ldr r3, [r7, #4] 80017d2: 681b ldr r3, [r3, #0] 80017d4: 4a67 ldr r2, [pc, #412] @ (8001974 ) 80017d6: 4293 cmp r3, r2 80017d8: d13f bne.n 800185a { DbgLEDToggle(DBG_LED4); 80017da: 2080 movs r0, #128 @ 0x80 80017dc: f001 fba6 bl 8002f2c SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc1Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 80017e0: 4b65 ldr r3, [pc, #404] @ (8001978 ) 80017e2: f023 031f bic.w r3, r3, #31 80017e6: 637b str r3, [r7, #52] @ 0x34 80017e8: 2320 movs r3, #32 80017ea: 633b str r3, [r7, #48] @ 0x30 \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { 80017ec: 6b3b ldr r3, [r7, #48] @ 0x30 80017ee: 2b00 cmp r3, #0 80017f0: dd1d ble.n 800182e int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 80017f2: 6b7b ldr r3, [r7, #52] @ 0x34 80017f4: f003 021f and.w r2, r3, #31 80017f8: 6b3b ldr r3, [r7, #48] @ 0x30 80017fa: 4413 add r3, r2 80017fc: 62fb str r3, [r7, #44] @ 0x2c uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 80017fe: 6b7b ldr r3, [r7, #52] @ 0x34 8001800: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("dsb 0xF":::"memory"); 8001802: f3bf 8f4f dsb sy } 8001806: bf00 nop __DSB(); do { SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 8001808: 4a5c ldr r2, [pc, #368] @ (800197c ) 800180a: 6abb ldr r3, [r7, #40] @ 0x28 800180c: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 8001810: 6abb ldr r3, [r7, #40] @ 0x28 8001812: 3320 adds r3, #32 8001814: 62bb str r3, [r7, #40] @ 0x28 op_size -= __SCB_DCACHE_LINE_SIZE; 8001816: 6afb ldr r3, [r7, #44] @ 0x2c 8001818: 3b20 subs r3, #32 800181a: 62fb str r3, [r7, #44] @ 0x2c } while ( op_size > 0 ); 800181c: 6afb ldr r3, [r7, #44] @ 0x2c 800181e: 2b00 cmp r3, #0 8001820: dcf2 bgt.n 8001808 __ASM volatile ("dsb 0xF":::"memory"); 8001822: f3bf 8f4f dsb sy } 8001826: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8001828: f3bf 8f6f isb sy } 800182c: bf00 nop __DSB(); __ISB(); } #endif } 800182e: bf00 nop if(adc1MeasDataQueue != NULL) 8001830: 4b53 ldr r3, [pc, #332] @ (8001980 ) 8001832: 681b ldr r3, [r3, #0] 8001834: 2b00 cmp r3, #0 8001836: d006 beq.n 8001846 { osMessageQueuePut(adc1MeasDataQueue, &adc1Data, 0, 0); 8001838: 4b51 ldr r3, [pc, #324] @ (8001980 ) 800183a: 6818 ldr r0, [r3, #0] 800183c: 2300 movs r3, #0 800183e: 2200 movs r2, #0 8001840: 494d ldr r1, [pc, #308] @ (8001978 ) 8001842: f012 ff23 bl 801468c } if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK) 8001846: 2207 movs r2, #7 8001848: 494b ldr r1, [pc, #300] @ (8001978 ) 800184a: 484e ldr r0, [pc, #312] @ (8001984 ) 800184c: f004 fed8 bl 8006600 8001850: 4603 mov r3, r0 8001852: 2b00 cmp r3, #0 8001854: d001 beq.n 800185a { Error_Handler(); 8001856: f000 fb39 bl 8001ecc } } if(hadc->Instance == ADC2) 800185a: 687b ldr r3, [r7, #4] 800185c: 681b ldr r3, [r3, #0] 800185e: 4a4a ldr r2, [pc, #296] @ (8001988 ) 8001860: 4293 cmp r3, r2 8001862: d13c bne.n 80018de { SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc2Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 8001864: 4b49 ldr r3, [pc, #292] @ (800198c ) 8001866: f023 031f bic.w r3, r3, #31 800186a: 627b str r3, [r7, #36] @ 0x24 800186c: 2320 movs r3, #32 800186e: 623b str r3, [r7, #32] if ( dsize > 0 ) { 8001870: 6a3b ldr r3, [r7, #32] 8001872: 2b00 cmp r3, #0 8001874: dd1d ble.n 80018b2 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 8001876: 6a7b ldr r3, [r7, #36] @ 0x24 8001878: f003 021f and.w r2, r3, #31 800187c: 6a3b ldr r3, [r7, #32] 800187e: 4413 add r3, r2 8001880: 61fb str r3, [r7, #28] uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 8001882: 6a7b ldr r3, [r7, #36] @ 0x24 8001884: 61bb str r3, [r7, #24] __ASM volatile ("dsb 0xF":::"memory"); 8001886: f3bf 8f4f dsb sy } 800188a: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 800188c: 4a3b ldr r2, [pc, #236] @ (800197c ) 800188e: 69bb ldr r3, [r7, #24] 8001890: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 8001894: 69bb ldr r3, [r7, #24] 8001896: 3320 adds r3, #32 8001898: 61bb str r3, [r7, #24] op_size -= __SCB_DCACHE_LINE_SIZE; 800189a: 69fb ldr r3, [r7, #28] 800189c: 3b20 subs r3, #32 800189e: 61fb str r3, [r7, #28] } while ( op_size > 0 ); 80018a0: 69fb ldr r3, [r7, #28] 80018a2: 2b00 cmp r3, #0 80018a4: dcf2 bgt.n 800188c __ASM volatile ("dsb 0xF":::"memory"); 80018a6: f3bf 8f4f dsb sy } 80018aa: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80018ac: f3bf 8f6f isb sy } 80018b0: bf00 nop } 80018b2: bf00 nop if(adc2MeasDataQueue != NULL) 80018b4: 4b36 ldr r3, [pc, #216] @ (8001990 ) 80018b6: 681b ldr r3, [r3, #0] 80018b8: 2b00 cmp r3, #0 80018ba: d006 beq.n 80018ca { osMessageQueuePut(adc2MeasDataQueue, &adc2Data, 0, 0); 80018bc: 4b34 ldr r3, [pc, #208] @ (8001990 ) 80018be: 6818 ldr r0, [r3, #0] 80018c0: 2300 movs r3, #0 80018c2: 2200 movs r2, #0 80018c4: 4931 ldr r1, [pc, #196] @ (800198c ) 80018c6: f012 fee1 bl 801468c } if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK) 80018ca: 2203 movs r2, #3 80018cc: 492f ldr r1, [pc, #188] @ (800198c ) 80018ce: 4831 ldr r0, [pc, #196] @ (8001994 ) 80018d0: f004 fe96 bl 8006600 80018d4: 4603 mov r3, r0 80018d6: 2b00 cmp r3, #0 80018d8: d001 beq.n 80018de { Error_Handler(); 80018da: f000 faf7 bl 8001ecc } } if(hadc->Instance == ADC3) 80018de: 687b ldr r3, [r7, #4] 80018e0: 681b ldr r3, [r3, #0] 80018e2: 4a2d ldr r2, [pc, #180] @ (8001998 ) 80018e4: 4293 cmp r3, r2 80018e6: d13c bne.n 8001962 { SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc3Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 80018e8: 4b2c ldr r3, [pc, #176] @ (800199c ) 80018ea: f023 031f bic.w r3, r3, #31 80018ee: 617b str r3, [r7, #20] 80018f0: 2320 movs r3, #32 80018f2: 613b str r3, [r7, #16] if ( dsize > 0 ) { 80018f4: 693b ldr r3, [r7, #16] 80018f6: 2b00 cmp r3, #0 80018f8: dd1d ble.n 8001936 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 80018fa: 697b ldr r3, [r7, #20] 80018fc: f003 021f and.w r2, r3, #31 8001900: 693b ldr r3, [r7, #16] 8001902: 4413 add r3, r2 8001904: 60fb str r3, [r7, #12] uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 8001906: 697b ldr r3, [r7, #20] 8001908: 60bb str r3, [r7, #8] __ASM volatile ("dsb 0xF":::"memory"); 800190a: f3bf 8f4f dsb sy } 800190e: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 8001910: 4a1a ldr r2, [pc, #104] @ (800197c ) 8001912: 68bb ldr r3, [r7, #8] 8001914: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 8001918: 68bb ldr r3, [r7, #8] 800191a: 3320 adds r3, #32 800191c: 60bb str r3, [r7, #8] op_size -= __SCB_DCACHE_LINE_SIZE; 800191e: 68fb ldr r3, [r7, #12] 8001920: 3b20 subs r3, #32 8001922: 60fb str r3, [r7, #12] } while ( op_size > 0 ); 8001924: 68fb ldr r3, [r7, #12] 8001926: 2b00 cmp r3, #0 8001928: dcf2 bgt.n 8001910 __ASM volatile ("dsb 0xF":::"memory"); 800192a: f3bf 8f4f dsb sy } 800192e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8001930: f3bf 8f6f isb sy } 8001934: bf00 nop } 8001936: bf00 nop if(adc3MeasDataQueue != NULL) 8001938: 4b19 ldr r3, [pc, #100] @ (80019a0 ) 800193a: 681b ldr r3, [r3, #0] 800193c: 2b00 cmp r3, #0 800193e: d006 beq.n 800194e { osMessageQueuePut(adc3MeasDataQueue, &adc3Data, 0, 0); 8001940: 4b17 ldr r3, [pc, #92] @ (80019a0 ) 8001942: 6818 ldr r0, [r3, #0] 8001944: 2300 movs r3, #0 8001946: 2200 movs r2, #0 8001948: 4914 ldr r1, [pc, #80] @ (800199c ) 800194a: f012 fe9f bl 801468c } if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK) 800194e: 2205 movs r2, #5 8001950: 4912 ldr r1, [pc, #72] @ (800199c ) 8001952: 4814 ldr r0, [pc, #80] @ (80019a4 ) 8001954: f004 fe54 bl 8006600 8001958: 4603 mov r3, r0 800195a: 2b00 cmp r3, #0 800195c: d001 beq.n 8001962 { Error_Handler(); 800195e: f000 fab5 bl 8001ecc } }osTimerStop (debugLedTimerHandle); 8001962: 4b11 ldr r3, [pc, #68] @ (80019a8 ) 8001964: 681b ldr r3, [r3, #0] 8001966: 4618 mov r0, r3 8001968: f012 fcd8 bl 801431c } 800196c: bf00 nop 800196e: 3738 adds r7, #56 @ 0x38 8001970: 46bd mov sp, r7 8001972: bd80 pop {r7, pc} 8001974: 40022000 .word 0x40022000 8001978: 240000c0 .word 0x240000c0 800197c: e000ed00 .word 0xe000ed00 8001980: 24000800 .word 0x24000800 8001984: 24000120 .word 0x24000120 8001988: 40022100 .word 0x40022100 800198c: 240000e0 .word 0x240000e0 8001990: 24000804 .word 0x24000804 8001994: 24000184 .word 0x24000184 8001998: 58026000 .word 0x58026000 800199c: 24000100 .word 0x24000100 80019a0: 24000808 .word 0x24000808 80019a4: 240001e8 .word 0x240001e8 80019a8: 240006e4 .word 0x240006e4 080019ac : void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 80019ac: b580 push {r7, lr} 80019ae: b084 sub sp, #16 80019b0: af00 add r7, sp, #0 80019b2: 6078 str r0, [r7, #4] if (htim->Instance == TIM4) 80019b4: 687b ldr r3, [r7, #4] 80019b6: 681b ldr r3, [r3, #0] 80019b8: 4a61 ldr r2, [pc, #388] @ (8001b40 ) 80019ba: 4293 cmp r3, r2 80019bc: d15a bne.n 8001a74 { if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_3) 80019be: 687b ldr r3, [r7, #4] 80019c0: 7f1b ldrb r3, [r3, #28] 80019c2: 2b04 cmp r3, #4 80019c4: d114 bne.n 80019f0 { if(encoderXChannelB > 0) 80019c6: 4b5f ldr r3, [pc, #380] @ (8001b44 ) 80019c8: 681b ldr r3, [r3, #0] 80019ca: 2b00 cmp r3, #0 80019cc: dd08 ble.n 80019e0 { encoderXChannelA = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_3); 80019ce: 2108 movs r1, #8 80019d0: 6878 ldr r0, [r7, #4] 80019d2: f00e fdb3 bl 801053c 80019d6: 4603 mov r3, r0 80019d8: 461a mov r2, r3 80019da: 4b5b ldr r3, [pc, #364] @ (8001b48 ) 80019dc: 601a str r2, [r3, #0] 80019de: e01f b.n 8001a20 } else { encoderXChannelA = 1; 80019e0: 4b59 ldr r3, [pc, #356] @ (8001b48 ) 80019e2: 2201 movs r2, #1 80019e4: 601a str r2, [r3, #0] __HAL_TIM_SET_COUNTER(htim,0); 80019e6: 687b ldr r3, [r7, #4] 80019e8: 681b ldr r3, [r3, #0] 80019ea: 2200 movs r2, #0 80019ec: 625a str r2, [r3, #36] @ 0x24 80019ee: e017 b.n 8001a20 } } else if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4) 80019f0: 687b ldr r3, [r7, #4] 80019f2: 7f1b ldrb r3, [r3, #28] 80019f4: 2b08 cmp r3, #8 80019f6: d113 bne.n 8001a20 { if(encoderXChannelA > 0) 80019f8: 4b53 ldr r3, [pc, #332] @ (8001b48 ) 80019fa: 681b ldr r3, [r3, #0] 80019fc: 2b00 cmp r3, #0 80019fe: dd08 ble.n 8001a12 { encoderXChannelB = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_4); 8001a00: 210c movs r1, #12 8001a02: 6878 ldr r0, [r7, #4] 8001a04: f00e fd9a bl 801053c 8001a08: 4603 mov r3, r0 8001a0a: 461a mov r2, r3 8001a0c: 4b4d ldr r3, [pc, #308] @ (8001b44 ) 8001a0e: 601a str r2, [r3, #0] 8001a10: e006 b.n 8001a20 } else { encoderXChannelB = 1; 8001a12: 4b4c ldr r3, [pc, #304] @ (8001b44 ) 8001a14: 2201 movs r2, #1 8001a16: 601a str r2, [r3, #0] __HAL_TIM_SET_COUNTER(htim,0); 8001a18: 687b ldr r3, [r7, #4] 8001a1a: 681b ldr r3, [r3, #0] 8001a1c: 2200 movs r2, #0 8001a1e: 625a str r2, [r3, #36] @ 0x24 } } if((encoderXChannelA != 0) && (encoderXChannelB != 0)) 8001a20: 4b49 ldr r3, [pc, #292] @ (8001b48 ) 8001a22: 681b ldr r3, [r3, #0] 8001a24: 2b00 cmp r3, #0 8001a26: f000 8086 beq.w 8001b36 8001a2a: 4b46 ldr r3, [pc, #280] @ (8001b44 ) 8001a2c: 681b ldr r3, [r3, #0] 8001a2e: 2b00 cmp r3, #0 8001a30: f000 8081 beq.w 8001b36 { EncoderData encoderData = { 0 }; 8001a34: 2300 movs r3, #0 8001a36: 81bb strh r3, [r7, #12] encoderData.axe = encoderAxeX; 8001a38: 2300 movs r3, #0 8001a3a: 733b strb r3, [r7, #12] encoderData.direction = encoderXChannelA - encoderXChannelB < 0 ? encoderCW : encoderCCW; 8001a3c: 4b42 ldr r3, [pc, #264] @ (8001b48 ) 8001a3e: 681a ldr r2, [r3, #0] 8001a40: 4b40 ldr r3, [pc, #256] @ (8001b44 ) 8001a42: 681b ldr r3, [r3, #0] 8001a44: 1ad3 subs r3, r2, r3 8001a46: 43db mvns r3, r3 8001a48: 0fdb lsrs r3, r3, #31 8001a4a: b2db uxtb r3, r3 8001a4c: 737b strb r3, [r7, #13] if (encoderData.direction == encoderCCW) 8001a4e: 7b7b ldrb r3, [r7, #13] 8001a50: 2b01 cmp r3, #1 8001a52: d100 bne.n 8001a56 { asm("nop;"); 8001a54: bf00 nop } osMessageQueuePut(encoderDataQueue, &encoderData, 0, 0); 8001a56: 4b3d ldr r3, [pc, #244] @ (8001b4c ) 8001a58: 6818 ldr r0, [r3, #0] 8001a5a: f107 010c add.w r1, r7, #12 8001a5e: 2300 movs r3, #0 8001a60: 2200 movs r2, #0 8001a62: f012 fe13 bl 801468c encoderXChannelA = 0; 8001a66: 4b38 ldr r3, [pc, #224] @ (8001b48 ) 8001a68: 2200 movs r2, #0 8001a6a: 601a str r2, [r3, #0] encoderXChannelB = 0; 8001a6c: 4b35 ldr r3, [pc, #212] @ (8001b44 ) 8001a6e: 2200 movs r2, #0 8001a70: 601a str r2, [r3, #0] osMessageQueuePut(encoderDataQueue, &encoderData, 0, 0); encoderYChannelA = 0; encoderYChannelB = 0; } } } 8001a72: e060 b.n 8001b36 } else if (htim->Instance == TIM2) 8001a74: 687b ldr r3, [r7, #4] 8001a76: 681b ldr r3, [r3, #0] 8001a78: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001a7c: d15b bne.n 8001b36 if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_3) 8001a7e: 687b ldr r3, [r7, #4] 8001a80: 7f1b ldrb r3, [r3, #28] 8001a82: 2b04 cmp r3, #4 8001a84: d114 bne.n 8001ab0 if(encoderYChannelB > 0) 8001a86: 4b32 ldr r3, [pc, #200] @ (8001b50 ) 8001a88: 681b ldr r3, [r3, #0] 8001a8a: 2b00 cmp r3, #0 8001a8c: dd08 ble.n 8001aa0 encoderYChannelA = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_3); 8001a8e: 2108 movs r1, #8 8001a90: 6878 ldr r0, [r7, #4] 8001a92: f00e fd53 bl 801053c 8001a96: 4603 mov r3, r0 8001a98: 461a mov r2, r3 8001a9a: 4b2e ldr r3, [pc, #184] @ (8001b54 ) 8001a9c: 601a str r2, [r3, #0] 8001a9e: e01f b.n 8001ae0 encoderYChannelA = 1; 8001aa0: 4b2c ldr r3, [pc, #176] @ (8001b54 ) 8001aa2: 2201 movs r2, #1 8001aa4: 601a str r2, [r3, #0] __HAL_TIM_SET_COUNTER(htim,0); 8001aa6: 687b ldr r3, [r7, #4] 8001aa8: 681b ldr r3, [r3, #0] 8001aaa: 2200 movs r2, #0 8001aac: 625a str r2, [r3, #36] @ 0x24 8001aae: e017 b.n 8001ae0 } else if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4) 8001ab0: 687b ldr r3, [r7, #4] 8001ab2: 7f1b ldrb r3, [r3, #28] 8001ab4: 2b08 cmp r3, #8 8001ab6: d113 bne.n 8001ae0 if(encoderYChannelA > 0) 8001ab8: 4b26 ldr r3, [pc, #152] @ (8001b54 ) 8001aba: 681b ldr r3, [r3, #0] 8001abc: 2b00 cmp r3, #0 8001abe: dd08 ble.n 8001ad2 encoderYChannelB = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_4); 8001ac0: 210c movs r1, #12 8001ac2: 6878 ldr r0, [r7, #4] 8001ac4: f00e fd3a bl 801053c 8001ac8: 4603 mov r3, r0 8001aca: 461a mov r2, r3 8001acc: 4b20 ldr r3, [pc, #128] @ (8001b50 ) 8001ace: 601a str r2, [r3, #0] 8001ad0: e006 b.n 8001ae0 encoderYChannelB = 1; 8001ad2: 4b1f ldr r3, [pc, #124] @ (8001b50 ) 8001ad4: 2201 movs r2, #1 8001ad6: 601a str r2, [r3, #0] __HAL_TIM_SET_COUNTER(htim,0); 8001ad8: 687b ldr r3, [r7, #4] 8001ada: 681b ldr r3, [r3, #0] 8001adc: 2200 movs r2, #0 8001ade: 625a str r2, [r3, #36] @ 0x24 if((encoderYChannelA != 0) && (encoderYChannelB != 0)) 8001ae0: 4b1c ldr r3, [pc, #112] @ (8001b54 ) 8001ae2: 681b ldr r3, [r3, #0] 8001ae4: 2b00 cmp r3, #0 8001ae6: d026 beq.n 8001b36 8001ae8: 4b19 ldr r3, [pc, #100] @ (8001b50 ) 8001aea: 681b ldr r3, [r3, #0] 8001aec: 2b00 cmp r3, #0 8001aee: d022 beq.n 8001b36 EncoderData encoderData = { 0 }; 8001af0: 2300 movs r3, #0 8001af2: 813b strh r3, [r7, #8] encoderData.axe = encoderAxeY; 8001af4: 2301 movs r3, #1 8001af6: 723b strb r3, [r7, #8] encoderData.direction = encoderYChannelA - encoderYChannelB < 0 ? encoderCW : encoderCCW; 8001af8: 4b16 ldr r3, [pc, #88] @ (8001b54 ) 8001afa: 681a ldr r2, [r3, #0] 8001afc: 4b14 ldr r3, [pc, #80] @ (8001b50 ) 8001afe: 681b ldr r3, [r3, #0] 8001b00: 1ad3 subs r3, r2, r3 8001b02: 43db mvns r3, r3 8001b04: 0fdb lsrs r3, r3, #31 8001b06: b2db uxtb r3, r3 8001b08: 727b strb r3, [r7, #9] if (encoderData.direction == encoderCCW) 8001b0a: 7a7b ldrb r3, [r7, #9] 8001b0c: 2b01 cmp r3, #1 8001b0e: d100 bne.n 8001b12 asm("nop;"); 8001b10: bf00 nop if (encoderData.direction == encoderCW) 8001b12: 7a7b ldrb r3, [r7, #9] 8001b14: 2b00 cmp r3, #0 8001b16: d100 bne.n 8001b1a asm("nop;"); 8001b18: bf00 nop osMessageQueuePut(encoderDataQueue, &encoderData, 0, 0); 8001b1a: 4b0c ldr r3, [pc, #48] @ (8001b4c ) 8001b1c: 6818 ldr r0, [r3, #0] 8001b1e: f107 0108 add.w r1, r7, #8 8001b22: 2300 movs r3, #0 8001b24: 2200 movs r2, #0 8001b26: f012 fdb1 bl 801468c encoderYChannelA = 0; 8001b2a: 4b0a ldr r3, [pc, #40] @ (8001b54 ) 8001b2c: 2200 movs r2, #0 8001b2e: 601a str r2, [r3, #0] encoderYChannelB = 0; 8001b30: 4b07 ldr r3, [pc, #28] @ (8001b50 ) 8001b32: 2200 movs r2, #0 8001b34: 601a str r2, [r3, #0] } 8001b36: bf00 nop 8001b38: 3710 adds r7, #16 8001b3a: 46bd mov sp, r7 8001b3c: bd80 pop {r7, pc} 8001b3e: bf00 nop 8001b40: 40000800 .word 0x40000800 8001b44: 240007e0 .word 0x240007e0 8001b48: 240007dc .word 0x240007dc 8001b4c: 24000810 .word 0x24000810 8001b50: 240007e8 .word 0x240007e8 8001b54: 240007e4 .word 0x240007e4 08001b58 : * @param argument: Not used * @retval None */ /* USER CODE END Header_StartDefaultTask */ void StartDefaultTask(void *argument) { 8001b58: b580 push {r7, lr} 8001b5a: b082 sub sp, #8 8001b5c: af00 add r7, sp, #0 8001b5e: 6078 str r0, [r7, #4] /* USER CODE BEGIN 5 */ #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001b60: 485e ldr r0, [pc, #376] @ (8001cdc ) 8001b62: f009 fd87 bl 800b674 #endif SelectCurrentSensorGain(CurrentSensorL1, csGain3); 8001b66: 2102 movs r1, #2 8001b68: 2000 movs r0, #0 8001b6a: f001 f9fd bl 8002f68 SelectCurrentSensorGain(CurrentSensorL2, csGain3); 8001b6e: 2102 movs r1, #2 8001b70: 2001 movs r0, #1 8001b72: f001 f9f9 bl 8002f68 SelectCurrentSensorGain(CurrentSensorL3, csGain3); 8001b76: 2102 movs r1, #2 8001b78: 2002 movs r0, #2 8001b7a: f001 f9f5 bl 8002f68 EnableCurrentSensors(); 8001b7e: f001 f9e7 bl 8002f50 osDelay(pdMS_TO_TICKS(100)); 8001b82: 2064 movs r0, #100 @ 0x64 8001b84: f012 faef bl 8014166 #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001b88: 4854 ldr r0, [pc, #336] @ (8001cdc ) 8001b8a: f009 fd73 bl 800b674 #endif if(HAL_TIM_Base_Start(&htim8) != HAL_OK) 8001b8e: 4854 ldr r0, [pc, #336] @ (8001ce0 ) 8001b90: f00d fc8e bl 800f4b0 8001b94: 4603 mov r3, r0 8001b96: 2b00 cmp r3, #0 8001b98: d001 beq.n 8001b9e { Error_Handler(); 8001b9a: f000 f997 bl 8001ecc } if(HAL_TIM_Base_Start_IT(&htim2) != HAL_OK) 8001b9e: 4851 ldr r0, [pc, #324] @ (8001ce4 ) 8001ba0: f00d fcf6 bl 800f590 8001ba4: 4603 mov r3, r0 8001ba6: 2b00 cmp r3, #0 8001ba8: d001 beq.n 8001bae { Error_Handler(); 8001baa: f000 f98f bl 8001ecc } if(HAL_TIM_Base_Start_IT(&htim4) != HAL_OK) 8001bae: 484e ldr r0, [pc, #312] @ (8001ce8 ) 8001bb0: f00d fcee bl 800f590 8001bb4: 4603 mov r3, r0 8001bb6: 2b00 cmp r3, #0 8001bb8: d001 beq.n 8001bbe { Error_Handler(); 8001bba: f000 f987 bl 8001ecc } if(HAL_TIM_IC_Start_IT(&htim4, TIM_CHANNEL_3) != HAL_OK) 8001bbe: 2108 movs r1, #8 8001bc0: 4849 ldr r0, [pc, #292] @ (8001ce8 ) 8001bc2: f00d ffbb bl 800fb3c 8001bc6: 4603 mov r3, r0 8001bc8: 2b00 cmp r3, #0 8001bca: d001 beq.n 8001bd0 { Error_Handler(); 8001bcc: f000 f97e bl 8001ecc } if(HAL_TIM_IC_Start_IT(&htim4, TIM_CHANNEL_4) != HAL_OK) 8001bd0: 210c movs r1, #12 8001bd2: 4845 ldr r0, [pc, #276] @ (8001ce8 ) 8001bd4: f00d ffb2 bl 800fb3c 8001bd8: 4603 mov r3, r0 8001bda: 2b00 cmp r3, #0 8001bdc: d001 beq.n 8001be2 { Error_Handler(); 8001bde: f000 f975 bl 8001ecc } if(HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_3) != HAL_OK) 8001be2: 2108 movs r1, #8 8001be4: 483f ldr r0, [pc, #252] @ (8001ce4 ) 8001be6: f00d ffa9 bl 800fb3c 8001bea: 4603 mov r3, r0 8001bec: 2b00 cmp r3, #0 8001bee: d001 beq.n 8001bf4 { Error_Handler(); 8001bf0: f000 f96c bl 8001ecc } if(HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_4) != HAL_OK) 8001bf4: 210c movs r1, #12 8001bf6: 483b ldr r0, [pc, #236] @ (8001ce4 ) 8001bf8: f00d ffa0 bl 800fb3c 8001bfc: 4603 mov r3, r0 8001bfe: 2b00 cmp r3, #0 8001c00: d001 beq.n 8001c06 { Error_Handler(); 8001c02: f000 f963 bl 8001ecc } if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK) 8001c06: 2207 movs r2, #7 8001c08: 4938 ldr r1, [pc, #224] @ (8001cec ) 8001c0a: 4839 ldr r0, [pc, #228] @ (8001cf0 ) 8001c0c: f004 fcf8 bl 8006600 8001c10: 4603 mov r3, r0 8001c12: 2b00 cmp r3, #0 8001c14: d001 beq.n 8001c1a { Error_Handler(); 8001c16: f000 f959 bl 8001ecc } if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK) 8001c1a: 2203 movs r2, #3 8001c1c: 4935 ldr r1, [pc, #212] @ (8001cf4 ) 8001c1e: 4836 ldr r0, [pc, #216] @ (8001cf8 ) 8001c20: f004 fcee bl 8006600 8001c24: 4603 mov r3, r0 8001c26: 2b00 cmp r3, #0 8001c28: d001 beq.n 8001c2e { Error_Handler(); 8001c2a: f000 f94f bl 8001ecc } if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK) 8001c2e: 2205 movs r2, #5 8001c30: 4932 ldr r1, [pc, #200] @ (8001cfc ) 8001c32: 4833 ldr r0, [pc, #204] @ (8001d00 ) 8001c34: f004 fce4 bl 8006600 8001c38: 4603 mov r3, r0 8001c3a: 2b00 cmp r3, #0 8001c3c: d001 beq.n 8001c42 { Error_Handler(); 8001c3e: f000 f945 bl 8001ecc } HAL_COMP_Start(&hcomp1); 8001c42: 4830 ldr r0, [pc, #192] @ (8001d04 ) 8001c44: f005 fe60 bl 8007908 #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001c48: 4824 ldr r0, [pc, #144] @ (8001cdc ) 8001c4a: f009 fd13 bl 800b674 #endif /* Infinite loop */ for(;;) { osDelay(pdMS_TO_TICKS(100)); 8001c4e: 2064 movs r0, #100 @ 0x64 8001c50: f012 fa89 bl 8014166 #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001c54: 4821 ldr r0, [pc, #132] @ (8001cdc ) 8001c56: f009 fd0d bl 800b674 #endif if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 8001c5a: 2100 movs r1, #0 8001c5c: 482a ldr r0, [pc, #168] @ (8001d08 ) 8001c5e: f00e fccf bl 8010600 8001c62: 4603 mov r3, r0 8001c64: 2b01 cmp r3, #1 8001c66: d118 bne.n 8001c9a HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_2) == HAL_TIM_CHANNEL_STATE_READY) 8001c68: 2104 movs r1, #4 8001c6a: 4827 ldr r0, [pc, #156] @ (8001d08 ) 8001c6c: f00e fcc8 bl 8010600 8001c70: 4603 mov r3, r0 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 8001c72: 2b01 cmp r3, #1 8001c74: d111 bne.n 8001c9a { if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 8001c76: 4b25 ldr r3, [pc, #148] @ (8001d0c ) 8001c78: 681b ldr r3, [r3, #0] 8001c7a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001c7e: 4618 mov r0, r3 8001c80: f012 fc09 bl 8014496 8001c84: 4603 mov r3, r0 8001c86: 2b00 cmp r3, #0 8001c88: d107 bne.n 8001c9a { sensorsInfo.motorXStatus = 0; 8001c8a: 4b21 ldr r3, [pc, #132] @ (8001d10 ) 8001c8c: 2200 movs r2, #0 8001c8e: 751a strb r2, [r3, #20] osMutexRelease(sensorsInfoMutex); 8001c90: 4b1e ldr r3, [pc, #120] @ (8001d0c ) 8001c92: 681b ldr r3, [r3, #0] 8001c94: 4618 mov r0, r3 8001c96: f012 fc49 bl 801452c } } if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 8001c9a: 2108 movs r1, #8 8001c9c: 481a ldr r0, [pc, #104] @ (8001d08 ) 8001c9e: f00e fcaf bl 8010600 8001ca2: 4603 mov r3, r0 8001ca4: 2b01 cmp r3, #1 8001ca6: d1d2 bne.n 8001c4e HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_4) == HAL_TIM_CHANNEL_STATE_READY) 8001ca8: 210c movs r1, #12 8001caa: 4817 ldr r0, [pc, #92] @ (8001d08 ) 8001cac: f00e fca8 bl 8010600 8001cb0: 4603 mov r3, r0 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 8001cb2: 2b01 cmp r3, #1 8001cb4: d1cb bne.n 8001c4e { if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 8001cb6: 4b15 ldr r3, [pc, #84] @ (8001d0c ) 8001cb8: 681b ldr r3, [r3, #0] 8001cba: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001cbe: 4618 mov r0, r3 8001cc0: f012 fbe9 bl 8014496 8001cc4: 4603 mov r3, r0 8001cc6: 2b00 cmp r3, #0 8001cc8: d1c1 bne.n 8001c4e { sensorsInfo.motorYStatus = 0; 8001cca: 4b11 ldr r3, [pc, #68] @ (8001d10 ) 8001ccc: 2200 movs r2, #0 8001cce: 755a strb r2, [r3, #21] osMutexRelease(sensorsInfoMutex); 8001cd0: 4b0e ldr r3, [pc, #56] @ (8001d0c ) 8001cd2: 681b ldr r3, [r3, #0] 8001cd4: 4618 mov r0, r3 8001cd6: f012 fc29 bl 801452c osDelay(pdMS_TO_TICKS(100)); 8001cda: e7b8 b.n 8001c4e 8001cdc: 24000418 .word 0x24000418 8001ce0: 2400056c .word 0x2400056c 8001ce4: 24000488 .word 0x24000488 8001ce8: 24000520 .word 0x24000520 8001cec: 240000c0 .word 0x240000c0 8001cf0: 24000120 .word 0x24000120 8001cf4: 240000e0 .word 0x240000e0 8001cf8: 24000184 .word 0x24000184 8001cfc: 24000100 .word 0x24000100 8001d00: 240001e8 .word 0x240001e8 8001d04: 240003b4 .word 0x240003b4 8001d08: 240004d4 .word 0x240004d4 8001d0c: 2400081c .word 0x2400081c 8001d10: 24000860 .word 0x24000860 08001d14 : /* USER CODE END 5 */ } /* debugLedTimerCallback function */ void debugLedTimerCallback(void *argument) { 8001d14: b580 push {r7, lr} 8001d16: b082 sub sp, #8 8001d18: af00 add r7, sp, #0 8001d1a: 6078 str r0, [r7, #4] /* USER CODE BEGIN debugLedTimerCallback */ DbgLEDOff (DBG_LED1); 8001d1c: 2010 movs r0, #16 8001d1e: f001 f8f3 bl 8002f08 /* USER CODE END debugLedTimerCallback */ } 8001d22: bf00 nop 8001d24: 3708 adds r7, #8 8001d26: 46bd mov sp, r7 8001d28: bd80 pop {r7, pc} ... 08001d2c : /* fanTimerCallback function */ void fanTimerCallback(void *argument) { 8001d2c: b580 push {r7, lr} 8001d2e: b082 sub sp, #8 8001d30: af00 add r7, sp, #0 8001d32: 6078 str r0, [r7, #4] /* USER CODE BEGIN fanTimerCallback */ HAL_TIM_PWM_Stop(&htim1, TIM_CHANNEL_2); 8001d34: 2104 movs r1, #4 8001d36: 4803 ldr r0, [pc, #12] @ (8001d44 ) 8001d38: f00d fe08 bl 800f94c /* USER CODE END fanTimerCallback */ } 8001d3c: bf00 nop 8001d3e: 3708 adds r7, #8 8001d40: 46bd mov sp, r7 8001d42: bd80 pop {r7, pc} 8001d44: 2400043c .word 0x2400043c 08001d48 : /* motorXTimerCallback function */ void motorXTimerCallback(void *argument) { 8001d48: b580 push {r7, lr} 8001d4a: b084 sub sp, #16 8001d4c: af02 add r7, sp, #8 8001d4e: 6078 str r0, [r7, #4] /* USER CODE BEGIN motorXTimerCallback */ MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, HiZ, 0); 8001d50: 2300 movs r3, #0 8001d52: 9301 str r3, [sp, #4] 8001d54: 2300 movs r3, #0 8001d56: 9300 str r3, [sp, #0] 8001d58: 2304 movs r3, #4 8001d5a: 2200 movs r2, #0 8001d5c: 4907 ldr r1, [pc, #28] @ (8001d7c ) 8001d5e: 4808 ldr r0, [pc, #32] @ (8001d80 ) 8001d60: f001 fa87 bl 8003272 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_1); 8001d64: 2100 movs r1, #0 8001d66: 4806 ldr r0, [pc, #24] @ (8001d80 ) 8001d68: f00d fdf0 bl 800f94c HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_2); 8001d6c: 2104 movs r1, #4 8001d6e: 4804 ldr r0, [pc, #16] @ (8001d80 ) 8001d70: f00d fdec bl 800f94c /* USER CODE END motorXTimerCallback */ } 8001d74: bf00 nop 8001d76: 3708 adds r7, #8 8001d78: 46bd mov sp, r7 8001d7a: bd80 pop {r7, pc} 8001d7c: 240007c0 .word 0x240007c0 8001d80: 240004d4 .word 0x240004d4 08001d84 : /* motorYTimerCallback function */ void motorYTimerCallback(void *argument) { 8001d84: b580 push {r7, lr} 8001d86: b084 sub sp, #16 8001d88: af02 add r7, sp, #8 8001d8a: 6078 str r0, [r7, #4] /* USER CODE BEGIN motorYTimerCallback */ MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, HiZ, 0); 8001d8c: 2300 movs r3, #0 8001d8e: 9301 str r3, [sp, #4] 8001d90: 2300 movs r3, #0 8001d92: 9300 str r3, [sp, #0] 8001d94: 230c movs r3, #12 8001d96: 2208 movs r2, #8 8001d98: 4907 ldr r1, [pc, #28] @ (8001db8 ) 8001d9a: 4808 ldr r0, [pc, #32] @ (8001dbc ) 8001d9c: f001 fa69 bl 8003272 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_3); 8001da0: 2108 movs r1, #8 8001da2: 4806 ldr r0, [pc, #24] @ (8001dbc ) 8001da4: f00d fdd2 bl 800f94c HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_4); 8001da8: 210c movs r1, #12 8001daa: 4804 ldr r0, [pc, #16] @ (8001dbc ) 8001dac: f00d fdce bl 800f94c /* USER CODE END motorYTimerCallback */ } 8001db0: bf00 nop 8001db2: 3708 adds r7, #8 8001db4: 46bd mov sp, r7 8001db6: bd80 pop {r7, pc} 8001db8: 240007c0 .word 0x240007c0 8001dbc: 240004d4 .word 0x240004d4 08001dc0 : /* MPU Configuration */ void MPU_Config(void) { 8001dc0: b580 push {r7, lr} 8001dc2: b084 sub sp, #16 8001dc4: af00 add r7, sp, #0 MPU_Region_InitTypeDef MPU_InitStruct = {0}; 8001dc6: 463b mov r3, r7 8001dc8: 2200 movs r2, #0 8001dca: 601a str r2, [r3, #0] 8001dcc: 605a str r2, [r3, #4] 8001dce: 609a str r2, [r3, #8] 8001dd0: 60da str r2, [r3, #12] /* Disables the MPU */ HAL_MPU_Disable(); 8001dd2: f005 fee1 bl 8007b98 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; 8001dd6: 2301 movs r3, #1 8001dd8: 703b strb r3, [r7, #0] MPU_InitStruct.Number = MPU_REGION_NUMBER0; 8001dda: 2300 movs r3, #0 8001ddc: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x0; 8001dde: 2300 movs r3, #0 8001de0: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; 8001de2: 231f movs r3, #31 8001de4: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x87; 8001de6: 2387 movs r3, #135 @ 0x87 8001de8: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8001dea: 2300 movs r3, #0 8001dec: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; 8001dee: 2300 movs r3, #0 8001df0: 72fb strb r3, [r7, #11] MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; 8001df2: 2301 movs r3, #1 8001df4: 733b strb r3, [r7, #12] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8001df6: 2301 movs r3, #1 8001df8: 737b strb r3, [r7, #13] MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; 8001dfa: 2300 movs r3, #0 8001dfc: 73bb strb r3, [r7, #14] MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; 8001dfe: 2300 movs r3, #0 8001e00: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001e02: 463b mov r3, r7 8001e04: 4618 mov r0, r3 8001e06: f005 feff bl 8007c08 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER1; 8001e0a: 2301 movs r3, #1 8001e0c: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24020000; 8001e0e: 4b13 ldr r3, [pc, #76] @ (8001e5c ) 8001e10: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_128KB; 8001e12: 2310 movs r3, #16 8001e14: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x0; 8001e16: 2300 movs r3, #0 8001e18: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; 8001e1a: 2301 movs r3, #1 8001e1c: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; 8001e1e: 2303 movs r3, #3 8001e20: 72fb strb r3, [r7, #11] MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 8001e22: 2300 movs r3, #0 8001e24: 737b strb r3, [r7, #13] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001e26: 463b mov r3, r7 8001e28: 4618 mov r0, r3 8001e2a: f005 feed bl 8007c08 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER2; 8001e2e: 2302 movs r3, #2 8001e30: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24040000; 8001e32: 4b0b ldr r3, [pc, #44] @ (8001e60 ) 8001e34: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_512B; 8001e36: 2308 movs r3, #8 8001e38: 723b strb r3, [r7, #8] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8001e3a: 2300 movs r3, #0 8001e3c: 72bb strb r3, [r7, #10] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8001e3e: 2301 movs r3, #1 8001e40: 737b strb r3, [r7, #13] MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; 8001e42: 2301 movs r3, #1 8001e44: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001e46: 463b mov r3, r7 8001e48: 4618 mov r0, r3 8001e4a: f005 fedd bl 8007c08 /* Enables the MPU */ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); 8001e4e: 2004 movs r0, #4 8001e50: f005 feba bl 8007bc8 } 8001e54: bf00 nop 8001e56: 3710 adds r7, #16 8001e58: 46bd mov sp, r7 8001e5a: bd80 pop {r7, pc} 8001e5c: 24020000 .word 0x24020000 8001e60: 24040000 .word 0x24040000 08001e64 : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8001e64: b580 push {r7, lr} 8001e66: b082 sub sp, #8 8001e68: af00 add r7, sp, #0 8001e6a: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM6) { 8001e6c: 687b ldr r3, [r7, #4] 8001e6e: 681b ldr r3, [r3, #0] 8001e70: 4a10 ldr r2, [pc, #64] @ (8001eb4 ) 8001e72: 4293 cmp r3, r2 8001e74: d102 bne.n 8001e7c HAL_IncTick(); 8001e76: f003 ffad bl 8005dd4 { encoderYChannelA = 0; encoderYChannelB = 0; } /* USER CODE END Callback 1 */ } 8001e7a: e016 b.n 8001eaa else if (htim->Instance == TIM4) 8001e7c: 687b ldr r3, [r7, #4] 8001e7e: 681b ldr r3, [r3, #0] 8001e80: 4a0d ldr r2, [pc, #52] @ (8001eb8 ) 8001e82: 4293 cmp r3, r2 8001e84: d106 bne.n 8001e94 encoderXChannelA = 0; 8001e86: 4b0d ldr r3, [pc, #52] @ (8001ebc ) 8001e88: 2200 movs r2, #0 8001e8a: 601a str r2, [r3, #0] encoderXChannelB = 0; 8001e8c: 4b0c ldr r3, [pc, #48] @ (8001ec0 ) 8001e8e: 2200 movs r2, #0 8001e90: 601a str r2, [r3, #0] } 8001e92: e00a b.n 8001eaa else if (htim->Instance == TIM2) 8001e94: 687b ldr r3, [r7, #4] 8001e96: 681b ldr r3, [r3, #0] 8001e98: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001e9c: d105 bne.n 8001eaa encoderYChannelA = 0; 8001e9e: 4b09 ldr r3, [pc, #36] @ (8001ec4 ) 8001ea0: 2200 movs r2, #0 8001ea2: 601a str r2, [r3, #0] encoderYChannelB = 0; 8001ea4: 4b08 ldr r3, [pc, #32] @ (8001ec8 ) 8001ea6: 2200 movs r2, #0 8001ea8: 601a str r2, [r3, #0] } 8001eaa: bf00 nop 8001eac: 3708 adds r7, #8 8001eae: 46bd mov sp, r7 8001eb0: bd80 pop {r7, pc} 8001eb2: bf00 nop 8001eb4: 40001000 .word 0x40001000 8001eb8: 40000800 .word 0x40000800 8001ebc: 240007dc .word 0x240007dc 8001ec0: 240007e0 .word 0x240007e0 8001ec4: 240007e4 .word 0x240007e4 8001ec8: 240007e8 .word 0x240007e8 08001ecc : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001ecc: b580 push {r7, lr} 8001ece: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 8001ed0: b672 cpsid i } 8001ed2: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); NVIC_SystemReset(); 8001ed4: f7fe fb88 bl 80005e8 <__NVIC_SystemReset> 08001ed8 : extern osTimerId_t motorXTimerHandle; extern osTimerId_t motorYTimerHandle; //extern osMutexId_t positionSettingMutex; void MeasTasksInit (void) { 8001ed8: b580 push {r7, lr} 8001eda: b0ae sub sp, #184 @ 0xb8 8001edc: af00 add r7, sp, #0 vRefmVMutex = osMutexNew (NULL); 8001ede: 2000 movs r0, #0 8001ee0: f012 fa53 bl 801438a 8001ee4: 4603 mov r3, r0 8001ee6: 4a58 ldr r2, [pc, #352] @ (8002048 ) 8001ee8: 6013 str r3, [r2, #0] resMeasurementsMutex = osMutexNew (NULL); 8001eea: 2000 movs r0, #0 8001eec: f012 fa4d bl 801438a 8001ef0: 4603 mov r3, r0 8001ef2: 4a56 ldr r2, [pc, #344] @ (800204c ) 8001ef4: 6013 str r3, [r2, #0] sensorsInfoMutex = osMutexNew (NULL); 8001ef6: 2000 movs r0, #0 8001ef8: f012 fa47 bl 801438a 8001efc: 4603 mov r3, r0 8001efe: 4a54 ldr r2, [pc, #336] @ (8002050 ) 8001f00: 6013 str r3, [r2, #0] ILxRefMutex = osMutexNew (NULL); 8001f02: 2000 movs r0, #0 8001f04: f012 fa41 bl 801438a 8001f08: 4603 mov r3, r0 8001f0a: 4a52 ldr r2, [pc, #328] @ (8002054 ) 8001f0c: 6013 str r3, [r2, #0] adc1MeasDataQueue = osMessageQueueNew (8, sizeof (ADC1_Data), NULL); 8001f0e: 2200 movs r2, #0 8001f10: 2120 movs r1, #32 8001f12: 2008 movs r0, #8 8001f14: f012 fb47 bl 80145a6 8001f18: 4603 mov r3, r0 8001f1a: 4a4f ldr r2, [pc, #316] @ (8002058 ) 8001f1c: 6013 str r3, [r2, #0] adc2MeasDataQueue = osMessageQueueNew (8, sizeof (ADC2_Data), NULL); 8001f1e: 2200 movs r2, #0 8001f20: 2120 movs r1, #32 8001f22: 2008 movs r0, #8 8001f24: f012 fb3f bl 80145a6 8001f28: 4603 mov r3, r0 8001f2a: 4a4c ldr r2, [pc, #304] @ (800205c ) 8001f2c: 6013 str r3, [r2, #0] adc3MeasDataQueue = osMessageQueueNew (8, sizeof (ADC3_Data), NULL); 8001f2e: 2200 movs r2, #0 8001f30: 2120 movs r1, #32 8001f32: 2008 movs r0, #8 8001f34: f012 fb37 bl 80145a6 8001f38: 4603 mov r3, r0 8001f3a: 4a49 ldr r2, [pc, #292] @ (8002060 ) 8001f3c: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttradc1MeasTask = { 0 }; 8001f3e: f107 0394 add.w r3, r7, #148 @ 0x94 8001f42: 2224 movs r2, #36 @ 0x24 8001f44: 2100 movs r1, #0 8001f46: 4618 mov r0, r3 8001f48: f016 f9ce bl 80182e8 osThreadAttr_t osThreadAttradc2MeasTask = { 0 }; 8001f4c: f107 0370 add.w r3, r7, #112 @ 0x70 8001f50: 2224 movs r2, #36 @ 0x24 8001f52: 2100 movs r1, #0 8001f54: 4618 mov r0, r3 8001f56: f016 f9c7 bl 80182e8 osThreadAttr_t osThreadAttradc3MeasTask = { 0 }; 8001f5a: f107 034c add.w r3, r7, #76 @ 0x4c 8001f5e: 2224 movs r2, #36 @ 0x24 8001f60: 2100 movs r1, #0 8001f62: 4618 mov r0, r3 8001f64: f016 f9c0 bl 80182e8 osThreadAttradc1MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001f68: f44f 6380 mov.w r3, #1024 @ 0x400 8001f6c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 osThreadAttradc1MeasTask.priority = (osPriority_t)osPriorityRealtime; 8001f70: 2330 movs r3, #48 @ 0x30 8001f72: f8c7 30ac str.w r3, [r7, #172] @ 0xac osThreadAttradc2MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001f76: f44f 6380 mov.w r3, #1024 @ 0x400 8001f7a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 osThreadAttradc2MeasTask.priority = (osPriority_t)osPriorityRealtime; 8001f7e: 2330 movs r3, #48 @ 0x30 8001f80: f8c7 3088 str.w r3, [r7, #136] @ 0x88 osThreadAttradc3MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001f84: f44f 6380 mov.w r3, #1024 @ 0x400 8001f88: 663b str r3, [r7, #96] @ 0x60 osThreadAttradc3MeasTask.priority = (osPriority_t)osPriorityNormal; 8001f8a: 2318 movs r3, #24 8001f8c: 667b str r3, [r7, #100] @ 0x64 adc1MeasTaskHandle = osThreadNew (ADC1MeasTask, NULL, &osThreadAttradc1MeasTask); 8001f8e: f107 0394 add.w r3, r7, #148 @ 0x94 8001f92: 461a mov r2, r3 8001f94: 2100 movs r1, #0 8001f96: 4833 ldr r0, [pc, #204] @ (8002064 ) 8001f98: f012 f852 bl 8014040 8001f9c: 4603 mov r3, r0 8001f9e: 4a32 ldr r2, [pc, #200] @ (8002068 ) 8001fa0: 6013 str r3, [r2, #0] adc2MeasTaskHandle = osThreadNew (ADC2MeasTask, NULL, &osThreadAttradc2MeasTask); 8001fa2: f107 0370 add.w r3, r7, #112 @ 0x70 8001fa6: 461a mov r2, r3 8001fa8: 2100 movs r1, #0 8001faa: 4830 ldr r0, [pc, #192] @ (800206c ) 8001fac: f012 f848 bl 8014040 8001fb0: 4603 mov r3, r0 8001fb2: 4a2f ldr r2, [pc, #188] @ (8002070 ) 8001fb4: 6013 str r3, [r2, #0] adc3MeasTaskHandle = osThreadNew (ADC3MeasTask, NULL, &osThreadAttradc3MeasTask); 8001fb6: f107 034c add.w r3, r7, #76 @ 0x4c 8001fba: 461a mov r2, r3 8001fbc: 2100 movs r1, #0 8001fbe: 482d ldr r0, [pc, #180] @ (8002074 ) 8001fc0: f012 f83e bl 8014040 8001fc4: 4603 mov r3, r0 8001fc6: 4a2c ldr r2, [pc, #176] @ (8002078 ) 8001fc8: 6013 str r3, [r2, #0] limiterSwitchDataQueue = osMessageQueueNew (8, sizeof (LimiterSwitchData), NULL); 8001fca: 2200 movs r2, #0 8001fcc: 2104 movs r1, #4 8001fce: 2008 movs r0, #8 8001fd0: f012 fae9 bl 80145a6 8001fd4: 4603 mov r3, r0 8001fd6: 4a29 ldr r2, [pc, #164] @ (800207c ) 8001fd8: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttradc1LimiterSwitchTask = { 0 }; 8001fda: f107 0328 add.w r3, r7, #40 @ 0x28 8001fde: 2224 movs r2, #36 @ 0x24 8001fe0: 2100 movs r1, #0 8001fe2: 4618 mov r0, r3 8001fe4: f016 f980 bl 80182e8 osThreadAttradc1LimiterSwitchTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001fe8: f44f 6380 mov.w r3, #1024 @ 0x400 8001fec: 63fb str r3, [r7, #60] @ 0x3c osThreadAttradc1LimiterSwitchTask.priority = (osPriority_t)osPriorityNormal; 8001fee: 2318 movs r3, #24 8001ff0: 643b str r3, [r7, #64] @ 0x40 limiterSwitchTaskHandle = osThreadNew (LimiterSwitchTask, NULL, &osThreadAttradc1LimiterSwitchTask); 8001ff2: f107 0328 add.w r3, r7, #40 @ 0x28 8001ff6: 461a mov r2, r3 8001ff8: 2100 movs r1, #0 8001ffa: 4821 ldr r0, [pc, #132] @ (8002080 ) 8001ffc: f012 f820 bl 8014040 8002000: 4603 mov r3, r0 8002002: 4a20 ldr r2, [pc, #128] @ (8002084 ) 8002004: 6013 str r3, [r2, #0] encoderDataQueue = osMessageQueueNew (16, sizeof (EncoderData), NULL); 8002006: 2200 movs r2, #0 8002008: 2102 movs r1, #2 800200a: 2010 movs r0, #16 800200c: f012 facb bl 80145a6 8002010: 4603 mov r3, r0 8002012: 4a1d ldr r2, [pc, #116] @ (8002088 ) 8002014: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttrEncoderTask = { 0 }; 8002016: 1d3b adds r3, r7, #4 8002018: 2224 movs r2, #36 @ 0x24 800201a: 2100 movs r1, #0 800201c: 4618 mov r0, r3 800201e: f016 f963 bl 80182e8 osThreadAttrEncoderTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8002022: f44f 6380 mov.w r3, #1024 @ 0x400 8002026: 61bb str r3, [r7, #24] osThreadAttrEncoderTask.priority = (osPriority_t)osPriorityNormal; 8002028: 2318 movs r3, #24 800202a: 61fb str r3, [r7, #28] encoderTaskHandle = osThreadNew (EncoderTask, encoderDataQueue, &osThreadAttrEncoderTask); 800202c: 4b16 ldr r3, [pc, #88] @ (8002088 ) 800202e: 681b ldr r3, [r3, #0] 8002030: 1d3a adds r2, r7, #4 8002032: 4619 mov r1, r3 8002034: 4815 ldr r0, [pc, #84] @ (800208c ) 8002036: f012 f803 bl 8014040 800203a: 4603 mov r3, r0 800203c: 4a14 ldr r2, [pc, #80] @ (8002090 ) 800203e: 6013 str r3, [r2, #0] } 8002040: bf00 nop 8002042: 37b8 adds r7, #184 @ 0xb8 8002044: 46bd mov sp, r7 8002046: bd80 pop {r7, pc} 8002048: 24000814 .word 0x24000814 800204c: 24000818 .word 0x24000818 8002050: 2400081c .word 0x2400081c 8002054: 24000820 .word 0x24000820 8002058: 24000800 .word 0x24000800 800205c: 24000804 .word 0x24000804 8002060: 24000808 .word 0x24000808 8002064: 08002099 .word 0x08002099 8002068: 240007ec .word 0x240007ec 800206c: 08002421 .word 0x08002421 8002070: 240007f0 .word 0x240007f0 8002074: 08002729 .word 0x08002729 8002078: 240007f4 .word 0x240007f4 800207c: 2400080c .word 0x2400080c 8002080: 08002aa5 .word 0x08002aa5 8002084: 240007f8 .word 0x240007f8 8002088: 24000810 .word 0x24000810 800208c: 08002d81 .word 0x08002d81 8002090: 240007fc .word 0x240007fc 8002094: 00000000 .word 0x00000000 08002098 : void ADC1MeasTask (void* arg) { 8002098: b580 push {r7, lr} 800209a: b09a sub sp, #104 @ 0x68 800209c: af00 add r7, sp, #0 800209e: 6078 str r0, [r7, #4] float circBuffer[VOLTAGES_COUNT][CIRC_BUFF_LEN] = { 0 }; 80020a0: f107 032c add.w r3, r7, #44 @ 0x2c 80020a4: 2228 movs r2, #40 @ 0x28 80020a6: 2100 movs r1, #0 80020a8: 4618 mov r0, r3 80020aa: f016 f91d bl 80182e8 float rms[VOLTAGES_COUNT] = { 0 }; 80020ae: f04f 0300 mov.w r3, #0 80020b2: 62bb str r3, [r7, #40] @ 0x28 ; ADC1_Data adcData = { 0 }; 80020b4: f107 0308 add.w r3, r7, #8 80020b8: 2220 movs r2, #32 80020ba: 2100 movs r1, #0 80020bc: 4618 mov r0, r3 80020be: f016 f913 bl 80182e8 uint32_t circBuffPos = 0; 80020c2: 2300 movs r3, #0 80020c4: 667b str r3, [r7, #100] @ 0x64 float gainCorrection = 1.0; 80020c6: f04f 537e mov.w r3, #1065353216 @ 0x3f800000 80020ca: 663b str r3, [r7, #96] @ 0x60 while (pdTRUE) { osMessageQueueGet (adc1MeasDataQueue, &adcData, 0, osWaitForever); 80020cc: 4bc8 ldr r3, [pc, #800] @ (80023f0 ) 80020ce: 6818 ldr r0, [r3, #0] 80020d0: f107 0108 add.w r1, r7, #8 80020d4: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80020d8: 2200 movs r2, #0 80020da: f012 fb37 bl 801474c #ifdef GAIN_AUTO_CORRECTION if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 80020de: 4bc5 ldr r3, [pc, #788] @ (80023f4 ) 80020e0: 681b ldr r3, [r3, #0] 80020e2: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80020e6: 4618 mov r0, r3 80020e8: f012 f9d5 bl 8014496 80020ec: 4603 mov r3, r0 80020ee: 2b00 cmp r3, #0 80020f0: d10c bne.n 800210c gainCorrection = (float)vRefmV; 80020f2: 4bc1 ldr r3, [pc, #772] @ (80023f8 ) 80020f4: 681b ldr r3, [r3, #0] 80020f6: ee07 3a90 vmov s15, r3 80020fa: eef8 7a67 vcvt.f32.u32 s15, s15 80020fe: edc7 7a18 vstr s15, [r7, #96] @ 0x60 osMutexRelease (vRefmVMutex); 8002102: 4bbc ldr r3, [pc, #752] @ (80023f4 ) 8002104: 681b ldr r3, [r3, #0] 8002106: 4618 mov r0, r3 8002108: f012 fa10 bl 801452c } gainCorrection = gainCorrection / EXT_VREF_mV; 800210c: ed97 7a18 vldr s14, [r7, #96] @ 0x60 8002110: eddf 6aba vldr s13, [pc, #744] @ 80023fc 8002114: eec7 7a26 vdiv.f32 s15, s14, s13 8002118: edc7 7a18 vstr s15, [r7, #96] @ 0x60 #endif for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) { 800211c: 2300 movs r3, #0 800211e: f887 305f strb.w r3, [r7, #95] @ 0x5f 8002122: e0e7 b.n 80022f4 float val = adcData.adcDataBuffer[i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 8002124: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002128: 005b lsls r3, r3, #1 800212a: 3368 adds r3, #104 @ 0x68 800212c: 443b add r3, r7 800212e: f833 3c60 ldrh.w r3, [r3, #-96] 8002132: ee07 3a90 vmov s15, r3 8002136: eeb8 7be7 vcvt.f64.s32 d7, s15 800213a: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 800213e: ee27 6b06 vmul.f64 d6, d7, d6 8002142: ed9f 5ba5 vldr d5, [pc, #660] @ 80023d8 8002146: ee86 7b05 vdiv.f64 d7, d6, d5 800214a: ed9f 6ba5 vldr d6, [pc, #660] @ 80023e0 800214e: ee27 6b06 vmul.f64 d6, d7, d6 8002152: edd7 7a18 vldr s15, [r7, #96] @ 0x60 8002156: eeb7 7ae7 vcvt.f64.f32 d7, s15 800215a: ee26 6b07 vmul.f64 d6, d6, d7 800215e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002162: 4aa7 ldr r2, [pc, #668] @ (8002400 ) 8002164: 00db lsls r3, r3, #3 8002166: 4413 add r3, r2 8002168: edd3 7a00 vldr s15, [r3] 800216c: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002170: ee26 6b07 vmul.f64 d6, d6, d7 8002174: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002178: 4aa1 ldr r2, [pc, #644] @ (8002400 ) 800217a: 00db lsls r3, r3, #3 800217c: 4413 add r3, r2 800217e: 3304 adds r3, #4 8002180: edd3 7a00 vldr s15, [r3] 8002184: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002188: ee36 7b07 vadd.f64 d7, d6, d7 800218c: eef7 7bc7 vcvt.f32.f64 s15, d7 8002190: edc7 7a15 vstr s15, [r7, #84] @ 0x54 circBuffer[i][circBuffPos] = val; 8002194: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 8002198: 4613 mov r3, r2 800219a: 009b lsls r3, r3, #2 800219c: 4413 add r3, r2 800219e: 005b lsls r3, r3, #1 80021a0: 6e7a ldr r2, [r7, #100] @ 0x64 80021a2: 4413 add r3, r2 80021a4: 009b lsls r3, r3, #2 80021a6: 3368 adds r3, #104 @ 0x68 80021a8: 443b add r3, r7 80021aa: 3b3c subs r3, #60 @ 0x3c 80021ac: 6d7a ldr r2, [r7, #84] @ 0x54 80021ae: 601a str r2, [r3, #0] rms[i] = 0.0; 80021b0: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80021b4: 009b lsls r3, r3, #2 80021b6: 3368 adds r3, #104 @ 0x68 80021b8: 443b add r3, r7 80021ba: 3b40 subs r3, #64 @ 0x40 80021bc: f04f 0200 mov.w r2, #0 80021c0: 601a str r2, [r3, #0] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 80021c2: 2300 movs r3, #0 80021c4: f887 305e strb.w r3, [r7, #94] @ 0x5e 80021c8: e025 b.n 8002216 rms[i] += circBuffer[i][c]; 80021ca: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80021ce: 009b lsls r3, r3, #2 80021d0: 3368 adds r3, #104 @ 0x68 80021d2: 443b add r3, r7 80021d4: 3b40 subs r3, #64 @ 0x40 80021d6: ed93 7a00 vldr s14, [r3] 80021da: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 80021de: f897 105e ldrb.w r1, [r7, #94] @ 0x5e 80021e2: 4613 mov r3, r2 80021e4: 009b lsls r3, r3, #2 80021e6: 4413 add r3, r2 80021e8: 005b lsls r3, r3, #1 80021ea: 440b add r3, r1 80021ec: 009b lsls r3, r3, #2 80021ee: 3368 adds r3, #104 @ 0x68 80021f0: 443b add r3, r7 80021f2: 3b3c subs r3, #60 @ 0x3c 80021f4: edd3 7a00 vldr s15, [r3] 80021f8: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80021fc: ee77 7a27 vadd.f32 s15, s14, s15 8002200: 009b lsls r3, r3, #2 8002202: 3368 adds r3, #104 @ 0x68 8002204: 443b add r3, r7 8002206: 3b40 subs r3, #64 @ 0x40 8002208: edc3 7a00 vstr s15, [r3] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 800220c: f897 305e ldrb.w r3, [r7, #94] @ 0x5e 8002210: 3301 adds r3, #1 8002212: f887 305e strb.w r3, [r7, #94] @ 0x5e 8002216: f897 305e ldrb.w r3, [r7, #94] @ 0x5e 800221a: 2b09 cmp r3, #9 800221c: d9d5 bls.n 80021ca } rms[i] = rms[i] / CIRC_BUFF_LEN; 800221e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002222: 009b lsls r3, r3, #2 8002224: 3368 adds r3, #104 @ 0x68 8002226: 443b add r3, r7 8002228: 3b40 subs r3, #64 @ 0x40 800222a: ed93 7a00 vldr s14, [r3] 800222e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002232: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002236: eec7 7a26 vdiv.f32 s15, s14, s13 800223a: 009b lsls r3, r3, #2 800223c: 3368 adds r3, #104 @ 0x68 800223e: 443b add r3, r7 8002240: 3b40 subs r3, #64 @ 0x40 8002242: edc3 7a00 vstr s15, [r3] if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8002246: 4b6f ldr r3, [pc, #444] @ (8002404 ) 8002248: 681b ldr r3, [r3, #0] 800224a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800224e: 4618 mov r0, r3 8002250: f012 f921 bl 8014496 8002254: 4603 mov r3, r0 8002256: 2b00 cmp r3, #0 8002258: d147 bne.n 80022ea if (fabs (resMeasurements.voltagePeak[i]) < fabs (val)) { 800225a: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800225e: 4a6a ldr r2, [pc, #424] @ (8002408 ) 8002260: 3302 adds r3, #2 8002262: 009b lsls r3, r3, #2 8002264: 4413 add r3, r2 8002266: 3304 adds r3, #4 8002268: edd3 7a00 vldr s15, [r3] 800226c: eeb0 7ae7 vabs.f32 s14, s15 8002270: edd7 7a15 vldr s15, [r7, #84] @ 0x54 8002274: eef0 7ae7 vabs.f32 s15, s15 8002278: eeb4 7ae7 vcmpe.f32 s14, s15 800227c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002280: d508 bpl.n 8002294 resMeasurements.voltagePeak[i] = val; 8002282: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002286: 4a60 ldr r2, [pc, #384] @ (8002408 ) 8002288: 3302 adds r3, #2 800228a: 009b lsls r3, r3, #2 800228c: 4413 add r3, r2 800228e: 3304 adds r3, #4 8002290: 6d7a ldr r2, [r7, #84] @ 0x54 8002292: 601a str r2, [r3, #0] } resMeasurements.voltageRMS[i] = rms[i]; 8002294: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 8002298: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800229c: 0092 lsls r2, r2, #2 800229e: 3268 adds r2, #104 @ 0x68 80022a0: 443a add r2, r7 80022a2: 3a40 subs r2, #64 @ 0x40 80022a4: 6812 ldr r2, [r2, #0] 80022a6: 4958 ldr r1, [pc, #352] @ (8002408 ) 80022a8: 009b lsls r3, r3, #2 80022aa: 440b add r3, r1 80022ac: 601a str r2, [r3, #0] resMeasurements.power[i] = resMeasurements.voltageRMS[i] * resMeasurements.currentRMS[i]; 80022ae: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022b2: 4a55 ldr r2, [pc, #340] @ (8002408 ) 80022b4: 009b lsls r3, r3, #2 80022b6: 4413 add r3, r2 80022b8: ed93 7a00 vldr s14, [r3] 80022bc: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022c0: 4a51 ldr r2, [pc, #324] @ (8002408 ) 80022c2: 3306 adds r3, #6 80022c4: 009b lsls r3, r3, #2 80022c6: 4413 add r3, r2 80022c8: edd3 7a00 vldr s15, [r3] 80022cc: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022d0: ee67 7a27 vmul.f32 s15, s14, s15 80022d4: 4a4c ldr r2, [pc, #304] @ (8002408 ) 80022d6: 330c adds r3, #12 80022d8: 009b lsls r3, r3, #2 80022da: 4413 add r3, r2 80022dc: edc3 7a00 vstr s15, [r3] osMutexRelease (resMeasurementsMutex); 80022e0: 4b48 ldr r3, [pc, #288] @ (8002404 ) 80022e2: 681b ldr r3, [r3, #0] 80022e4: 4618 mov r0, r3 80022e6: f012 f921 bl 801452c for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) { 80022ea: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022ee: 3301 adds r3, #1 80022f0: f887 305f strb.w r3, [r7, #95] @ 0x5f 80022f4: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022f8: 2b00 cmp r3, #0 80022fa: f43f af13 beq.w 8002124 } } ++circBuffPos; 80022fe: 6e7b ldr r3, [r7, #100] @ 0x64 8002300: 3301 adds r3, #1 8002302: 667b str r3, [r7, #100] @ 0x64 circBuffPos = circBuffPos % CIRC_BUFF_LEN; 8002304: 6e7a ldr r2, [r7, #100] @ 0x64 8002306: 4b41 ldr r3, [pc, #260] @ (800240c ) 8002308: fba3 1302 umull r1, r3, r3, r2 800230c: 08d9 lsrs r1, r3, #3 800230e: 460b mov r3, r1 8002310: 009b lsls r3, r3, #2 8002312: 440b add r3, r1 8002314: 005b lsls r3, r3, #1 8002316: 1ad3 subs r3, r2, r3 8002318: 667b str r3, [r7, #100] @ 0x64 if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) { 800231a: 4b3d ldr r3, [pc, #244] @ (8002410 ) 800231c: 681b ldr r3, [r3, #0] 800231e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002322: 4618 mov r0, r3 8002324: f012 f8b7 bl 8014496 8002328: 4603 mov r3, r0 800232a: 2b00 cmp r3, #0 800232c: d124 bne.n 8002378 uint8_t refIdx = 0; 800232e: 2300 movs r3, #0 8002330: f887 305d strb.w r3, [r7, #93] @ 0x5d for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) { 8002334: 2303 movs r3, #3 8002336: f887 305c strb.w r3, [r7, #92] @ 0x5c 800233a: e014 b.n 8002366 ILxRef[refIdx++] = adcData.adcDataBuffer[i]; 800233c: f897 205c ldrb.w r2, [r7, #92] @ 0x5c 8002340: f897 305d ldrb.w r3, [r7, #93] @ 0x5d 8002344: 1c59 adds r1, r3, #1 8002346: f887 105d strb.w r1, [r7, #93] @ 0x5d 800234a: 4619 mov r1, r3 800234c: 0053 lsls r3, r2, #1 800234e: 3368 adds r3, #104 @ 0x68 8002350: 443b add r3, r7 8002352: f833 2c60 ldrh.w r2, [r3, #-96] 8002356: 4b2f ldr r3, [pc, #188] @ (8002414 ) 8002358: f823 2011 strh.w r2, [r3, r1, lsl #1] for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) { 800235c: f897 305c ldrb.w r3, [r7, #92] @ 0x5c 8002360: 3301 adds r3, #1 8002362: f887 305c strb.w r3, [r7, #92] @ 0x5c 8002366: f897 305c ldrb.w r3, [r7, #92] @ 0x5c 800236a: 2b05 cmp r3, #5 800236c: d9e6 bls.n 800233c } osMutexRelease (ILxRefMutex); 800236e: 4b28 ldr r3, [pc, #160] @ (8002410 ) 8002370: 681b ldr r3, [r3, #0] 8002372: 4618 mov r0, r3 8002374: f012 f8da bl 801452c } float fanFBVoltage = adcData.adcDataBuffer[FanFB] * deltaADC * -4.35 + 12; 8002378: 8abb ldrh r3, [r7, #20] 800237a: ee07 3a90 vmov s15, r3 800237e: eeb8 7be7 vcvt.f64.s32 d7, s15 8002382: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002386: ee27 6b06 vmul.f64 d6, d7, d6 800238a: ed9f 5b13 vldr d5, [pc, #76] @ 80023d8 800238e: ee86 7b05 vdiv.f64 d7, d6, d5 8002392: ed9f 6b15 vldr d6, [pc, #84] @ 80023e8 8002396: ee27 7b06 vmul.f64 d7, d7, d6 800239a: eeb2 6b08 vmov.f64 d6, #40 @ 0x41400000 12.0 800239e: ee37 7b06 vadd.f64 d7, d7, d6 80023a2: eef7 7bc7 vcvt.f32.f64 s15, d7 80023a6: edc7 7a16 vstr s15, [r7, #88] @ 0x58 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80023aa: 4b1b ldr r3, [pc, #108] @ (8002418 ) 80023ac: 681b ldr r3, [r3, #0] 80023ae: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80023b2: 4618 mov r0, r3 80023b4: f012 f86f bl 8014496 80023b8: 4603 mov r3, r0 80023ba: 2b00 cmp r3, #0 80023bc: f47f ae86 bne.w 80020cc sensorsInfo.fanVoltage = fanFBVoltage; 80023c0: 4a16 ldr r2, [pc, #88] @ (800241c ) 80023c2: 6dbb ldr r3, [r7, #88] @ 0x58 80023c4: 6093 str r3, [r2, #8] osMutexRelease (sensorsInfoMutex); 80023c6: 4b14 ldr r3, [pc, #80] @ (8002418 ) 80023c8: 681b ldr r3, [r3, #0] 80023ca: 4618 mov r0, r3 80023cc: f012 f8ae bl 801452c while (pdTRUE) { 80023d0: e67c b.n 80020cc 80023d2: bf00 nop 80023d4: f3af 8000 nop.w 80023d8: 00000000 .word 0x00000000 80023dc: 40efffe0 .word 0x40efffe0 80023e0: f5c28f5c .word 0xf5c28f5c 80023e4: 401e5c28 .word 0x401e5c28 80023e8: 66666666 .word 0x66666666 80023ec: c0116666 .word 0xc0116666 80023f0: 24000800 .word 0x24000800 80023f4: 24000814 .word 0x24000814 80023f8: 24000030 .word 0x24000030 80023fc: 453b8000 .word 0x453b8000 8002400: 24000000 .word 0x24000000 8002404: 24000818 .word 0x24000818 8002408: 24000824 .word 0x24000824 800240c: cccccccd .word 0xcccccccd 8002410: 24000820 .word 0x24000820 8002414: 2400089c .word 0x2400089c 8002418: 2400081c .word 0x2400081c 800241c: 24000860 .word 0x24000860 08002420 : } } } void ADC2MeasTask (void* arg) { 8002420: b580 push {r7, lr} 8002422: b09c sub sp, #112 @ 0x70 8002424: af00 add r7, sp, #0 8002426: 6078 str r0, [r7, #4] float circBuffer[CURRENTS_COUNT][CIRC_BUFF_LEN] = { 0 }; 8002428: f107 0334 add.w r3, r7, #52 @ 0x34 800242c: 2228 movs r2, #40 @ 0x28 800242e: 2100 movs r1, #0 8002430: 4618 mov r0, r3 8002432: f015 ff59 bl 80182e8 float rms[CURRENTS_COUNT] = { 0 }; 8002436: f04f 0300 mov.w r3, #0 800243a: 633b str r3, [r7, #48] @ 0x30 ADC2_Data adcData = { 0 }; 800243c: f107 0310 add.w r3, r7, #16 8002440: 2220 movs r2, #32 8002442: 2100 movs r1, #0 8002444: 4618 mov r0, r3 8002446: f015 ff4f bl 80182e8 uint32_t circBuffPos = 0; 800244a: 2300 movs r3, #0 800244c: 66fb str r3, [r7, #108] @ 0x6c float gainCorrection = 1.0; 800244e: f04f 537e mov.w r3, #1065353216 @ 0x3f800000 8002452: 66bb str r3, [r7, #104] @ 0x68 while (pdTRUE) { osMessageQueueGet (adc2MeasDataQueue, &adcData, 0, osWaitForever); 8002454: 4baa ldr r3, [pc, #680] @ (8002700 ) 8002456: 6818 ldr r0, [r3, #0] 8002458: f107 0110 add.w r1, r7, #16 800245c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002460: 2200 movs r2, #0 8002462: f012 f973 bl 801474c if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 8002466: 4ba7 ldr r3, [pc, #668] @ (8002704 ) 8002468: 681b ldr r3, [r3, #0] 800246a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800246e: 4618 mov r0, r3 8002470: f012 f811 bl 8014496 8002474: 4603 mov r3, r0 8002476: 2b00 cmp r3, #0 8002478: d10c bne.n 8002494 gainCorrection = (float)vRefmV; 800247a: 4ba3 ldr r3, [pc, #652] @ (8002708 ) 800247c: 681b ldr r3, [r3, #0] 800247e: ee07 3a90 vmov s15, r3 8002482: eef8 7a67 vcvt.f32.u32 s15, s15 8002486: edc7 7a1a vstr s15, [r7, #104] @ 0x68 osMutexRelease (vRefmVMutex); 800248a: 4b9e ldr r3, [pc, #632] @ (8002704 ) 800248c: 681b ldr r3, [r3, #0] 800248e: 4618 mov r0, r3 8002490: f012 f84c bl 801452c } gainCorrection = gainCorrection / EXT_VREF_mV; 8002494: ed97 7a1a vldr s14, [r7, #104] @ 0x68 8002498: eddf 6a9c vldr s13, [pc, #624] @ 800270c 800249c: eec7 7a26 vdiv.f32 s15, s14, s13 80024a0: edc7 7a1a vstr s15, [r7, #104] @ 0x68 float ref[CURRENTS_COUNT] = { 0 }; 80024a4: f04f 0300 mov.w r3, #0 80024a8: 60fb str r3, [r7, #12] if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) { 80024aa: 4b99 ldr r3, [pc, #612] @ (8002710 ) 80024ac: 681b ldr r3, [r3, #0] 80024ae: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80024b2: 4618 mov r0, r3 80024b4: f011 ffef bl 8014496 80024b8: 4603 mov r3, r0 80024ba: 2b00 cmp r3, #0 80024bc: d122 bne.n 8002504 for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 80024be: 2300 movs r3, #0 80024c0: f887 3067 strb.w r3, [r7, #103] @ 0x67 80024c4: e015 b.n 80024f2 ref[i] = (float)ILxRef[i]; 80024c6: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80024ca: 4a92 ldr r2, [pc, #584] @ (8002714 ) 80024cc: f832 2013 ldrh.w r2, [r2, r3, lsl #1] 80024d0: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80024d4: ee07 2a90 vmov s15, r2 80024d8: eef8 7a67 vcvt.f32.u32 s15, s15 80024dc: 009b lsls r3, r3, #2 80024de: 3370 adds r3, #112 @ 0x70 80024e0: 443b add r3, r7 80024e2: 3b64 subs r3, #100 @ 0x64 80024e4: edc3 7a00 vstr s15, [r3] for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 80024e8: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80024ec: 3301 adds r3, #1 80024ee: f887 3067 strb.w r3, [r7, #103] @ 0x67 80024f2: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80024f6: 2b00 cmp r3, #0 80024f8: d0e5 beq.n 80024c6 } osMutexRelease (ILxRefMutex); 80024fa: 4b85 ldr r3, [pc, #532] @ (8002710 ) 80024fc: 681b ldr r3, [r3, #0] 80024fe: 4618 mov r0, r3 8002500: f012 f814 bl 801452c } for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 8002504: 2300 movs r3, #0 8002506: f887 3066 strb.w r3, [r7, #102] @ 0x66 800250a: e0db b.n 80026c4 float adcVal = (float)adcData.adcDataBuffer[i]; 800250c: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002510: 005b lsls r3, r3, #1 8002512: 3370 adds r3, #112 @ 0x70 8002514: 443b add r3, r7 8002516: f833 3c60 ldrh.w r3, [r3, #-96] 800251a: ee07 3a90 vmov s15, r3 800251e: eef8 7a67 vcvt.f32.u32 s15, s15 8002522: edc7 7a18 vstr s15, [r7, #96] @ 0x60 float val = (adcVal - ref[i]) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset; 8002526: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800252a: 009b lsls r3, r3, #2 800252c: 3370 adds r3, #112 @ 0x70 800252e: 443b add r3, r7 8002530: 3b64 subs r3, #100 @ 0x64 8002532: edd3 7a00 vldr s15, [r3] 8002536: ed97 7a18 vldr s14, [r7, #96] @ 0x60 800253a: ee77 7a67 vsub.f32 s15, s14, s15 800253e: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002542: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002546: ee27 6b06 vmul.f64 d6, d7, d6 800254a: ed9f 5b69 vldr d5, [pc, #420] @ 80026f0 800254e: ee86 7b05 vdiv.f64 d7, d6, d5 8002552: ed9f 6b69 vldr d6, [pc, #420] @ 80026f8 8002556: ee27 6b06 vmul.f64 d6, d7, d6 800255a: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800255e: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002562: ee26 6b07 vmul.f64 d6, d6, d7 8002566: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800256a: 4a6b ldr r2, [pc, #428] @ (8002718 ) 800256c: 00db lsls r3, r3, #3 800256e: 4413 add r3, r2 8002570: edd3 7a00 vldr s15, [r3] 8002574: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002578: ee26 6b07 vmul.f64 d6, d6, d7 800257c: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002580: 4a65 ldr r2, [pc, #404] @ (8002718 ) 8002582: 00db lsls r3, r3, #3 8002584: 4413 add r3, r2 8002586: 3304 adds r3, #4 8002588: edd3 7a00 vldr s15, [r3] 800258c: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002590: ee36 7b07 vadd.f64 d7, d6, d7 8002594: eef7 7bc7 vcvt.f32.f64 s15, d7 8002598: edc7 7a17 vstr s15, [r7, #92] @ 0x5c circBuffer[i][circBuffPos] = val; 800259c: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 80025a0: 4613 mov r3, r2 80025a2: 009b lsls r3, r3, #2 80025a4: 4413 add r3, r2 80025a6: 005b lsls r3, r3, #1 80025a8: 6efa ldr r2, [r7, #108] @ 0x6c 80025aa: 4413 add r3, r2 80025ac: 009b lsls r3, r3, #2 80025ae: 3370 adds r3, #112 @ 0x70 80025b0: 443b add r3, r7 80025b2: 3b3c subs r3, #60 @ 0x3c 80025b4: 6dfa ldr r2, [r7, #92] @ 0x5c 80025b6: 601a str r2, [r3, #0] rms[i] = 0.0; 80025b8: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80025bc: 009b lsls r3, r3, #2 80025be: 3370 adds r3, #112 @ 0x70 80025c0: 443b add r3, r7 80025c2: 3b40 subs r3, #64 @ 0x40 80025c4: f04f 0200 mov.w r2, #0 80025c8: 601a str r2, [r3, #0] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 80025ca: 2300 movs r3, #0 80025cc: f887 3065 strb.w r3, [r7, #101] @ 0x65 80025d0: e025 b.n 800261e rms[i] += circBuffer[i][c]; 80025d2: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80025d6: 009b lsls r3, r3, #2 80025d8: 3370 adds r3, #112 @ 0x70 80025da: 443b add r3, r7 80025dc: 3b40 subs r3, #64 @ 0x40 80025de: ed93 7a00 vldr s14, [r3] 80025e2: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 80025e6: f897 1065 ldrb.w r1, [r7, #101] @ 0x65 80025ea: 4613 mov r3, r2 80025ec: 009b lsls r3, r3, #2 80025ee: 4413 add r3, r2 80025f0: 005b lsls r3, r3, #1 80025f2: 440b add r3, r1 80025f4: 009b lsls r3, r3, #2 80025f6: 3370 adds r3, #112 @ 0x70 80025f8: 443b add r3, r7 80025fa: 3b3c subs r3, #60 @ 0x3c 80025fc: edd3 7a00 vldr s15, [r3] 8002600: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002604: ee77 7a27 vadd.f32 s15, s14, s15 8002608: 009b lsls r3, r3, #2 800260a: 3370 adds r3, #112 @ 0x70 800260c: 443b add r3, r7 800260e: 3b40 subs r3, #64 @ 0x40 8002610: edc3 7a00 vstr s15, [r3] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 8002614: f897 3065 ldrb.w r3, [r7, #101] @ 0x65 8002618: 3301 adds r3, #1 800261a: f887 3065 strb.w r3, [r7, #101] @ 0x65 800261e: f897 3065 ldrb.w r3, [r7, #101] @ 0x65 8002622: 2b09 cmp r3, #9 8002624: d9d5 bls.n 80025d2 } rms[i] = rms[i] / CIRC_BUFF_LEN; 8002626: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800262a: 009b lsls r3, r3, #2 800262c: 3370 adds r3, #112 @ 0x70 800262e: 443b add r3, r7 8002630: 3b40 subs r3, #64 @ 0x40 8002632: ed93 7a00 vldr s14, [r3] 8002636: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800263a: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 800263e: eec7 7a26 vdiv.f32 s15, s14, s13 8002642: 009b lsls r3, r3, #2 8002644: 3370 adds r3, #112 @ 0x70 8002646: 443b add r3, r7 8002648: 3b40 subs r3, #64 @ 0x40 800264a: edc3 7a00 vstr s15, [r3] if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 800264e: 4b33 ldr r3, [pc, #204] @ (800271c ) 8002650: 681b ldr r3, [r3, #0] 8002652: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002656: 4618 mov r0, r3 8002658: f011 ff1d bl 8014496 800265c: 4603 mov r3, r0 800265e: 2b00 cmp r3, #0 8002660: d12b bne.n 80026ba if (resMeasurements.currentPeak[i] < val) { 8002662: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002666: 4a2e ldr r2, [pc, #184] @ (8002720 ) 8002668: 3308 adds r3, #8 800266a: 009b lsls r3, r3, #2 800266c: 4413 add r3, r2 800266e: 3304 adds r3, #4 8002670: edd3 7a00 vldr s15, [r3] 8002674: ed97 7a17 vldr s14, [r7, #92] @ 0x5c 8002678: eeb4 7ae7 vcmpe.f32 s14, s15 800267c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002680: dd08 ble.n 8002694 resMeasurements.currentPeak[i] = val; 8002682: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002686: 4a26 ldr r2, [pc, #152] @ (8002720 ) 8002688: 3308 adds r3, #8 800268a: 009b lsls r3, r3, #2 800268c: 4413 add r3, r2 800268e: 3304 adds r3, #4 8002690: 6dfa ldr r2, [r7, #92] @ 0x5c 8002692: 601a str r2, [r3, #0] } resMeasurements.currentRMS[i] = rms[i]; 8002694: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 8002698: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800269c: 0092 lsls r2, r2, #2 800269e: 3270 adds r2, #112 @ 0x70 80026a0: 443a add r2, r7 80026a2: 3a40 subs r2, #64 @ 0x40 80026a4: 6812 ldr r2, [r2, #0] 80026a6: 491e ldr r1, [pc, #120] @ (8002720 ) 80026a8: 3306 adds r3, #6 80026aa: 009b lsls r3, r3, #2 80026ac: 440b add r3, r1 80026ae: 601a str r2, [r3, #0] osMutexRelease (resMeasurementsMutex); 80026b0: 4b1a ldr r3, [pc, #104] @ (800271c ) 80026b2: 681b ldr r3, [r3, #0] 80026b4: 4618 mov r0, r3 80026b6: f011 ff39 bl 801452c for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 80026ba: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80026be: 3301 adds r3, #1 80026c0: f887 3066 strb.w r3, [r7, #102] @ 0x66 80026c4: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80026c8: 2b00 cmp r3, #0 80026ca: f43f af1f beq.w 800250c } } ++circBuffPos; 80026ce: 6efb ldr r3, [r7, #108] @ 0x6c 80026d0: 3301 adds r3, #1 80026d2: 66fb str r3, [r7, #108] @ 0x6c circBuffPos = circBuffPos % CIRC_BUFF_LEN; 80026d4: 6efa ldr r2, [r7, #108] @ 0x6c 80026d6: 4b13 ldr r3, [pc, #76] @ (8002724 ) 80026d8: fba3 1302 umull r1, r3, r3, r2 80026dc: 08d9 lsrs r1, r3, #3 80026de: 460b mov r3, r1 80026e0: 009b lsls r3, r3, #2 80026e2: 440b add r3, r1 80026e4: 005b lsls r3, r3, #1 80026e6: 1ad3 subs r3, r2, r3 80026e8: 66fb str r3, [r7, #108] @ 0x6c while (pdTRUE) { 80026ea: e6b3 b.n 8002454 80026ec: f3af 8000 nop.w 80026f0: 00000000 .word 0x00000000 80026f4: 40efffe0 .word 0x40efffe0 80026f8: 83e425af .word 0x83e425af 80026fc: 401e4d9e .word 0x401e4d9e 8002700: 24000804 .word 0x24000804 8002704: 24000814 .word 0x24000814 8002708: 24000030 .word 0x24000030 800270c: 453b8000 .word 0x453b8000 8002710: 24000820 .word 0x24000820 8002714: 2400089c .word 0x2400089c 8002718: 24000018 .word 0x24000018 800271c: 24000818 .word 0x24000818 8002720: 24000824 .word 0x24000824 8002724: cccccccd .word 0xcccccccd 08002728 : } } void ADC3MeasTask (void* arg) { 8002728: b580 push {r7, lr} 800272a: b0bc sub sp, #240 @ 0xf0 800272c: af00 add r7, sp, #0 800272e: 6078 str r0, [r7, #4] float motorXSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 8002730: f107 03a4 add.w r3, r7, #164 @ 0xa4 8002734: 2228 movs r2, #40 @ 0x28 8002736: 2100 movs r1, #0 8002738: 4618 mov r0, r3 800273a: f015 fdd5 bl 80182e8 float motorYSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 800273e: f107 037c add.w r3, r7, #124 @ 0x7c 8002742: 2228 movs r2, #40 @ 0x28 8002744: 2100 movs r1, #0 8002746: 4618 mov r0, r3 8002748: f015 fdce bl 80182e8 float pvT1CircBuffer[CIRC_BUFF_LEN] = { 0 }; 800274c: f107 0354 add.w r3, r7, #84 @ 0x54 8002750: 2228 movs r2, #40 @ 0x28 8002752: 2100 movs r1, #0 8002754: 4618 mov r0, r3 8002756: f015 fdc7 bl 80182e8 float pvT2CircBuffer[CIRC_BUFF_LEN] = { 0 }; 800275a: f107 032c add.w r3, r7, #44 @ 0x2c 800275e: 2228 movs r2, #40 @ 0x28 8002760: 2100 movs r1, #0 8002762: 4618 mov r0, r3 8002764: f015 fdc0 bl 80182e8 uint32_t circBuffPos = 0; 8002768: 2300 movs r3, #0 800276a: f8c7 30ec str.w r3, [r7, #236] @ 0xec ADC3_Data adcData = { 0 }; 800276e: f107 030c add.w r3, r7, #12 8002772: 2220 movs r2, #32 8002774: 2100 movs r1, #0 8002776: 4618 mov r0, r3 8002778: f015 fdb6 bl 80182e8 while (pdTRUE) { osMessageQueueGet (adc3MeasDataQueue, &adcData, 0, osWaitForever); 800277c: 4bc2 ldr r3, [pc, #776] @ (8002a88 ) 800277e: 6818 ldr r0, [r3, #0] 8002780: f107 010c add.w r1, r7, #12 8002784: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002788: 2200 movs r2, #0 800278a: f011 ffdf bl 801474c uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B); 800278e: 4bbf ldr r3, [pc, #764] @ (8002a8c ) 8002790: 881b ldrh r3, [r3, #0] 8002792: 461a mov r2, r3 8002794: f640 43e4 movw r3, #3300 @ 0xce4 8002798: fb02 f303 mul.w r3, r2, r3 800279c: 8aba ldrh r2, [r7, #20] 800279e: fbb3 f3f2 udiv r3, r3, r2 80027a2: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 80027a6: 4bba ldr r3, [pc, #744] @ (8002a90 ) 80027a8: 681b ldr r3, [r3, #0] 80027aa: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80027ae: 4618 mov r0, r3 80027b0: f011 fe71 bl 8014496 80027b4: 4603 mov r3, r0 80027b6: 2b00 cmp r3, #0 80027b8: d108 bne.n 80027cc vRefmV = vRef; 80027ba: 4ab6 ldr r2, [pc, #728] @ (8002a94 ) 80027bc: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 80027c0: 6013 str r3, [r2, #0] osMutexRelease (vRefmVMutex); 80027c2: 4bb3 ldr r3, [pc, #716] @ (8002a90 ) 80027c4: 681b ldr r3, [r3, #0] 80027c6: 4618 mov r0, r3 80027c8: f011 feb0 bl 801452c } float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333; 80027cc: 8a3b ldrh r3, [r7, #16] 80027ce: ee07 3a90 vmov s15, r3 80027d2: eeb8 7be7 vcvt.f64.s32 d7, s15 80027d6: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80027da: ee27 6b06 vmul.f64 d6, d7, d6 80027de: ed9f 5ba2 vldr d5, [pc, #648] @ 8002a68 80027e2: ee86 7b05 vdiv.f64 d7, d6, d5 80027e6: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 80027ea: ee27 6b06 vmul.f64 d6, d7, d6 80027ee: ed9f 5ba0 vldr d5, [pc, #640] @ 8002a70 80027f2: ee86 7b05 vdiv.f64 d7, d6, d5 80027f6: eef7 7bc7 vcvt.f32.f64 s15, d7 80027fa: edc7 7a34 vstr s15, [r7, #208] @ 0xd0 float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333; 80027fe: 8a7b ldrh r3, [r7, #18] 8002800: ee07 3a90 vmov s15, r3 8002804: eeb8 7be7 vcvt.f64.s32 d7, s15 8002808: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 800280c: ee27 6b06 vmul.f64 d6, d7, d6 8002810: ed9f 5b95 vldr d5, [pc, #596] @ 8002a68 8002814: ee86 7b05 vdiv.f64 d7, d6, d5 8002818: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 800281c: ee27 6b06 vmul.f64 d6, d7, d6 8002820: ed9f 5b93 vldr d5, [pc, #588] @ 8002a70 8002824: ee86 7b05 vdiv.f64 d7, d6, d5 8002828: eef7 7bc7 vcvt.f32.f64 s15, d7 800282c: edc7 7a33 vstr s15, [r7, #204] @ 0xcc motorXSensCircBuffer[circBuffPos] = motorXCurrentSense; 8002830: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002834: 009b lsls r3, r3, #2 8002836: 33f0 adds r3, #240 @ 0xf0 8002838: 443b add r3, r7 800283a: 3b4c subs r3, #76 @ 0x4c 800283c: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8002840: 601a str r2, [r3, #0] motorYSensCircBuffer[circBuffPos] = motorYCurrentSense; 8002842: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002846: 009b lsls r3, r3, #2 8002848: 33f0 adds r3, #240 @ 0xf0 800284a: 443b add r3, r7 800284c: 3b74 subs r3, #116 @ 0x74 800284e: f8d7 20cc ldr.w r2, [r7, #204] @ 0xcc 8002852: 601a str r2, [r3, #0] pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63; 8002854: 89bb ldrh r3, [r7, #12] 8002856: ee07 3a90 vmov s15, r3 800285a: eeb8 7be7 vcvt.f64.s32 d7, s15 800285e: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002862: ee27 6b06 vmul.f64 d6, d7, d6 8002866: ed9f 5b80 vldr d5, [pc, #512] @ 8002a68 800286a: ee86 7b05 vdiv.f64 d7, d6, d5 800286e: ed9f 6b82 vldr d6, [pc, #520] @ 8002a78 8002872: ee27 7b06 vmul.f64 d7, d7, d6 8002876: ed9f 6b82 vldr d6, [pc, #520] @ 8002a80 800287a: ee37 7b46 vsub.f64 d7, d7, d6 800287e: eef7 7bc7 vcvt.f32.f64 s15, d7 8002882: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002886: 009b lsls r3, r3, #2 8002888: 33f0 adds r3, #240 @ 0xf0 800288a: 443b add r3, r7 800288c: 3b9c subs r3, #156 @ 0x9c 800288e: edc3 7a00 vstr s15, [r3] pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63; 8002892: 89fb ldrh r3, [r7, #14] 8002894: ee07 3a90 vmov s15, r3 8002898: eeb8 7be7 vcvt.f64.s32 d7, s15 800289c: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80028a0: ee27 6b06 vmul.f64 d6, d7, d6 80028a4: ed9f 5b70 vldr d5, [pc, #448] @ 8002a68 80028a8: ee86 7b05 vdiv.f64 d7, d6, d5 80028ac: ed9f 6b72 vldr d6, [pc, #456] @ 8002a78 80028b0: ee27 7b06 vmul.f64 d7, d7, d6 80028b4: ed9f 6b72 vldr d6, [pc, #456] @ 8002a80 80028b8: ee37 7b46 vsub.f64 d7, d7, d6 80028bc: eef7 7bc7 vcvt.f32.f64 s15, d7 80028c0: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 80028c4: 009b lsls r3, r3, #2 80028c6: 33f0 adds r3, #240 @ 0xf0 80028c8: 443b add r3, r7 80028ca: 3bc4 subs r3, #196 @ 0xc4 80028cc: edc3 7a00 vstr s15, [r3] float motorXAveCurrent = 0; 80028d0: f04f 0300 mov.w r3, #0 80028d4: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 float motorYAveCurrent = 0; 80028d8: f04f 0300 mov.w r3, #0 80028dc: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 float pvT1AveTemp = 0; 80028e0: f04f 0300 mov.w r3, #0 80028e4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 float pvT2AveTemp = 0; 80028e8: f04f 0300 mov.w r3, #0 80028ec: f8c7 30dc str.w r3, [r7, #220] @ 0xdc for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) { 80028f0: 2300 movs r3, #0 80028f2: f887 30db strb.w r3, [r7, #219] @ 0xdb 80028f6: e03c b.n 8002972 motorXAveCurrent += motorXSensCircBuffer[i]; 80028f8: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 80028fc: 009b lsls r3, r3, #2 80028fe: 33f0 adds r3, #240 @ 0xf0 8002900: 443b add r3, r7 8002902: 3b4c subs r3, #76 @ 0x4c 8002904: edd3 7a00 vldr s15, [r3] 8002908: ed97 7a3a vldr s14, [r7, #232] @ 0xe8 800290c: ee77 7a27 vadd.f32 s15, s14, s15 8002910: edc7 7a3a vstr s15, [r7, #232] @ 0xe8 motorYAveCurrent += motorYSensCircBuffer[i]; 8002914: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002918: 009b lsls r3, r3, #2 800291a: 33f0 adds r3, #240 @ 0xf0 800291c: 443b add r3, r7 800291e: 3b74 subs r3, #116 @ 0x74 8002920: edd3 7a00 vldr s15, [r3] 8002924: ed97 7a39 vldr s14, [r7, #228] @ 0xe4 8002928: ee77 7a27 vadd.f32 s15, s14, s15 800292c: edc7 7a39 vstr s15, [r7, #228] @ 0xe4 #ifdef PV_BOARD pvT1AveTemp += pvT1CircBuffer[i]; 8002930: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002934: 009b lsls r3, r3, #2 8002936: 33f0 adds r3, #240 @ 0xf0 8002938: 443b add r3, r7 800293a: 3b9c subs r3, #156 @ 0x9c 800293c: edd3 7a00 vldr s15, [r3] 8002940: ed97 7a38 vldr s14, [r7, #224] @ 0xe0 8002944: ee77 7a27 vadd.f32 s15, s14, s15 8002948: edc7 7a38 vstr s15, [r7, #224] @ 0xe0 pvT2AveTemp += pvT2CircBuffer[i]; 800294c: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002950: 009b lsls r3, r3, #2 8002952: 33f0 adds r3, #240 @ 0xf0 8002954: 443b add r3, r7 8002956: 3bc4 subs r3, #196 @ 0xc4 8002958: edd3 7a00 vldr s15, [r3] 800295c: ed97 7a37 vldr s14, [r7, #220] @ 0xdc 8002960: ee77 7a27 vadd.f32 s15, s14, s15 8002964: edc7 7a37 vstr s15, [r7, #220] @ 0xdc for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) { 8002968: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 800296c: 3301 adds r3, #1 800296e: f887 30db strb.w r3, [r7, #219] @ 0xdb 8002972: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002976: 2b09 cmp r3, #9 8002978: d9be bls.n 80028f8 #endif } motorXAveCurrent /= CIRC_BUFF_LEN; 800297a: ed97 7a3a vldr s14, [r7, #232] @ 0xe8 800297e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002982: eec7 7a26 vdiv.f32 s15, s14, s13 8002986: edc7 7a3a vstr s15, [r7, #232] @ 0xe8 motorYAveCurrent /= CIRC_BUFF_LEN; 800298a: ed97 7a39 vldr s14, [r7, #228] @ 0xe4 800298e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002992: eec7 7a26 vdiv.f32 s15, s14, s13 8002996: edc7 7a39 vstr s15, [r7, #228] @ 0xe4 pvT1AveTemp /= CIRC_BUFF_LEN; 800299a: ed97 7a38 vldr s14, [r7, #224] @ 0xe0 800299e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 80029a2: eec7 7a26 vdiv.f32 s15, s14, s13 80029a6: edc7 7a38 vstr s15, [r7, #224] @ 0xe0 pvT2AveTemp /= CIRC_BUFF_LEN; 80029aa: ed97 7a37 vldr s14, [r7, #220] @ 0xdc 80029ae: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 80029b2: eec7 7a26 vdiv.f32 s15, s14, s13 80029b6: edc7 7a37 vstr s15, [r7, #220] @ 0xdc if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80029ba: 4b37 ldr r3, [pc, #220] @ (8002a98 ) 80029bc: 681b ldr r3, [r3, #0] 80029be: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80029c2: 4618 mov r0, r3 80029c4: f011 fd67 bl 8014496 80029c8: 4603 mov r3, r0 80029ca: 2b00 cmp r3, #0 80029cc: d138 bne.n 8002a40 if (sensorsInfo.motorXStatus == 1) { 80029ce: 4b33 ldr r3, [pc, #204] @ (8002a9c ) 80029d0: 7d1b ldrb r3, [r3, #20] 80029d2: 2b01 cmp r3, #1 80029d4: d111 bne.n 80029fa sensorsInfo.motorXAveCurrent = motorXAveCurrent; 80029d6: 4a31 ldr r2, [pc, #196] @ (8002a9c ) 80029d8: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8 80029dc: 6193 str r3, [r2, #24] if (sensorsInfo.motorXPeakCurrent < motorXCurrentSense) { 80029de: 4b2f ldr r3, [pc, #188] @ (8002a9c ) 80029e0: edd3 7a08 vldr s15, [r3, #32] 80029e4: ed97 7a34 vldr s14, [r7, #208] @ 0xd0 80029e8: eeb4 7ae7 vcmpe.f32 s14, s15 80029ec: eef1 fa10 vmrs APSR_nzcv, fpscr 80029f0: dd03 ble.n 80029fa sensorsInfo.motorXPeakCurrent = motorXCurrentSense; 80029f2: 4a2a ldr r2, [pc, #168] @ (8002a9c ) 80029f4: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0 80029f8: 6213 str r3, [r2, #32] } } if (sensorsInfo.motorYStatus == 1) { 80029fa: 4b28 ldr r3, [pc, #160] @ (8002a9c ) 80029fc: 7d5b ldrb r3, [r3, #21] 80029fe: 2b01 cmp r3, #1 8002a00: d111 bne.n 8002a26 sensorsInfo.motorYAveCurrent = motorYAveCurrent; 8002a02: 4a26 ldr r2, [pc, #152] @ (8002a9c ) 8002a04: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8002a08: 61d3 str r3, [r2, #28] if (sensorsInfo.motorYPeakCurrent < motorYCurrentSense) { 8002a0a: 4b24 ldr r3, [pc, #144] @ (8002a9c ) 8002a0c: edd3 7a09 vldr s15, [r3, #36] @ 0x24 8002a10: ed97 7a33 vldr s14, [r7, #204] @ 0xcc 8002a14: eeb4 7ae7 vcmpe.f32 s14, s15 8002a18: eef1 fa10 vmrs APSR_nzcv, fpscr 8002a1c: dd03 ble.n 8002a26 sensorsInfo.motorYPeakCurrent = motorYCurrentSense; 8002a1e: 4a1f ldr r2, [pc, #124] @ (8002a9c ) 8002a20: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc 8002a24: 6253 str r3, [r2, #36] @ 0x24 } } sensorsInfo.pvTemperature[0] = pvT1AveTemp; 8002a26: 4a1d ldr r2, [pc, #116] @ (8002a9c ) 8002a28: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8002a2c: 6013 str r3, [r2, #0] sensorsInfo.pvTemperature[1] = pvT2AveTemp; 8002a2e: 4a1b ldr r2, [pc, #108] @ (8002a9c ) 8002a30: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8002a34: 6053 str r3, [r2, #4] osMutexRelease (sensorsInfoMutex); 8002a36: 4b18 ldr r3, [pc, #96] @ (8002a98 ) 8002a38: 681b ldr r3, [r3, #0] 8002a3a: 4618 mov r0, r3 8002a3c: f011 fd76 bl 801452c } ++circBuffPos; 8002a40: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002a44: 3301 adds r3, #1 8002a46: f8c7 30ec str.w r3, [r7, #236] @ 0xec circBuffPos = circBuffPos % CIRC_BUFF_LEN; 8002a4a: f8d7 20ec ldr.w r2, [r7, #236] @ 0xec 8002a4e: 4b14 ldr r3, [pc, #80] @ (8002aa0 ) 8002a50: fba3 1302 umull r1, r3, r3, r2 8002a54: 08d9 lsrs r1, r3, #3 8002a56: 460b mov r3, r1 8002a58: 009b lsls r3, r3, #2 8002a5a: 440b add r3, r1 8002a5c: 005b lsls r3, r3, #1 8002a5e: 1ad3 subs r3, r2, r3 8002a60: f8c7 30ec str.w r3, [r7, #236] @ 0xec while (pdTRUE) { 8002a64: e68a b.n 800277c 8002a66: bf00 nop 8002a68: 00000000 .word 0x00000000 8002a6c: 40efffe0 .word 0x40efffe0 8002a70: 3ad18d26 .word 0x3ad18d26 8002a74: 4020aaaa .word 0x4020aaaa 8002a78: aaa38226 .word 0xaaa38226 8002a7c: 4046aaaa .word 0x4046aaaa 8002a80: 00000000 .word 0x00000000 8002a84: 404f8000 .word 0x404f8000 8002a88: 24000808 .word 0x24000808 8002a8c: 1ff1e860 .word 0x1ff1e860 8002a90: 24000814 .word 0x24000814 8002a94: 24000030 .word 0x24000030 8002a98: 2400081c .word 0x2400081c 8002a9c: 24000860 .word 0x24000860 8002aa0: cccccccd .word 0xcccccccd 08002aa4 : } } void LimiterSwitchTask (void* arg) { 8002aa4: b580 push {r7, lr} 8002aa6: b08a sub sp, #40 @ 0x28 8002aa8: af06 add r7, sp, #24 8002aaa: 6078 str r0, [r7, #4] LimiterSwitchData limiterSwitchData = { 0 }; 8002aac: 2300 movs r3, #0 8002aae: 60bb str r3, [r7, #8] limiterSwitchData.gpioPin = GPIO_PIN_8; 8002ab0: f44f 7380 mov.w r3, #256 @ 0x100 8002ab4: 813b strh r3, [r7, #8] for (uint8_t i = 0; i < 6; i++) { 8002ab6: 2300 movs r3, #0 8002ab8: 73fb strb r3, [r7, #15] 8002aba: e02c b.n 8002b16 limiterSwitchData.pinState = HAL_GPIO_ReadPin (GPIOD, limiterSwitchData.gpioPin); 8002abc: 893b ldrh r3, [r7, #8] 8002abe: 4619 mov r1, r3 8002ac0: 48a5 ldr r0, [pc, #660] @ (8002d58 ) 8002ac2: f008 fd23 bl 800b50c 8002ac6: 4603 mov r3, r0 8002ac8: 72bb strb r3, [r7, #10] osMessageQueuePut (limiterSwitchDataQueue, &limiterSwitchData, 0, 0); 8002aca: 4ba4 ldr r3, [pc, #656] @ (8002d5c ) 8002acc: 6818 ldr r0, [r3, #0] 8002ace: f107 0108 add.w r1, r7, #8 8002ad2: 2300 movs r3, #0 8002ad4: 2200 movs r2, #0 8002ad6: f011 fdd9 bl 801468c limiterSwitchData.gpioPin = limiterSwitchData.gpioPin << 1; 8002ada: 893b ldrh r3, [r7, #8] 8002adc: 005b lsls r3, r3, #1 8002ade: b29b uxth r3, r3 8002ae0: 813b strh r3, [r7, #8] if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8002ae2: 4b9f ldr r3, [pc, #636] @ (8002d60 ) 8002ae4: 681b ldr r3, [r3, #0] 8002ae6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002aea: 4618 mov r0, r3 8002aec: f011 fcd3 bl 8014496 8002af0: 4603 mov r3, r0 8002af2: 2b00 cmp r3, #0 8002af4: d10c bne.n 8002b10 sensorsInfo.positionXWeak = 1; 8002af6: 4b9b ldr r3, [pc, #620] @ (8002d64 ) 8002af8: 2201 movs r2, #1 8002afa: f883 2038 strb.w r2, [r3, #56] @ 0x38 sensorsInfo.positionYWeak = 1; 8002afe: 4b99 ldr r3, [pc, #612] @ (8002d64 ) 8002b00: 2201 movs r2, #1 8002b02: f883 2039 strb.w r2, [r3, #57] @ 0x39 osMutexRelease (sensorsInfoMutex); 8002b06: 4b96 ldr r3, [pc, #600] @ (8002d60 ) 8002b08: 681b ldr r3, [r3, #0] 8002b0a: 4618 mov r0, r3 8002b0c: f011 fd0e bl 801452c for (uint8_t i = 0; i < 6; i++) { 8002b10: 7bfb ldrb r3, [r7, #15] 8002b12: 3301 adds r3, #1 8002b14: 73fb strb r3, [r7, #15] 8002b16: 7bfb ldrb r3, [r7, #15] 8002b18: 2b05 cmp r3, #5 8002b1a: d9cf bls.n 8002abc } } while (pdTRUE) { osMessageQueueGet (limiterSwitchDataQueue, &limiterSwitchData, 0, osWaitForever); 8002b1c: 4b8f ldr r3, [pc, #572] @ (8002d5c ) 8002b1e: 6818 ldr r0, [r3, #0] 8002b20: f107 0108 add.w r1, r7, #8 8002b24: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002b28: 2200 movs r2, #0 8002b2a: f011 fe0f bl 801474c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8002b2e: 4b8c ldr r3, [pc, #560] @ (8002d60 ) 8002b30: 681b ldr r3, [r3, #0] 8002b32: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002b36: 4618 mov r0, r3 8002b38: f011 fcad bl 8014496 8002b3c: 4603 mov r3, r0 8002b3e: 2b00 cmp r3, #0 8002b40: d1ec bne.n 8002b1c switch (limiterSwitchData.gpioPin) { 8002b42: 893b ldrh r3, [r7, #8] 8002b44: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8002b48: f000 8094 beq.w 8002c74 8002b4c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8002b50: f300 80a8 bgt.w 8002ca4 8002b54: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8002b58: d075 beq.n 8002c46 8002b5a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8002b5e: f300 80a1 bgt.w 8002ca4 8002b62: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8002b66: d057 beq.n 8002c18 8002b68: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8002b6c: f300 809a bgt.w 8002ca4 8002b70: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8002b74: d039 beq.n 8002bea 8002b76: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8002b7a: f300 8093 bgt.w 8002ca4 8002b7e: f5b3 7f80 cmp.w r3, #256 @ 0x100 8002b82: d003 beq.n 8002b8c 8002b84: f5b3 7f00 cmp.w r3, #512 @ 0x200 8002b88: d017 beq.n 8002bba { sensorsInfo.currentXPosition = 0; sensorsInfo.positionXWeak = 0; } break; default: break; 8002b8a: e08b b.n 8002ca4 sensorsInfo.limitYSwitchCenter = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002b8c: 7abb ldrb r3, [r7, #10] 8002b8e: 2b01 cmp r3, #1 8002b90: bf0c ite eq 8002b92: 2301 moveq r3, #1 8002b94: 2300 movne r3, #0 8002b96: b2db uxtb r3, r3 8002b98: 461a mov r2, r3 8002b9a: 4b72 ldr r3, [pc, #456] @ (8002d64 ) 8002b9c: f883 202d strb.w r2, [r3, #45] @ 0x2d if (sensorsInfo.limitYSwitchCenter == 1) 8002ba0: 4b70 ldr r3, [pc, #448] @ (8002d64 ) 8002ba2: f893 302d ldrb.w r3, [r3, #45] @ 0x2d 8002ba6: 2b01 cmp r3, #1 8002ba8: d17e bne.n 8002ca8 sensorsInfo.currentYPosition = 50; 8002baa: 4b6e ldr r3, [pc, #440] @ (8002d64 ) 8002bac: 4a6e ldr r2, [pc, #440] @ (8002d68 ) 8002bae: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8002bb0: 4b6c ldr r3, [pc, #432] @ (8002d64 ) 8002bb2: 2200 movs r2, #0 8002bb4: f883 2039 strb.w r2, [r3, #57] @ 0x39 break; 8002bb8: e076 b.n 8002ca8 sensorsInfo.limitYSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002bba: 7abb ldrb r3, [r7, #10] 8002bbc: 2b01 cmp r3, #1 8002bbe: bf0c ite eq 8002bc0: 2301 moveq r3, #1 8002bc2: 2300 movne r3, #0 8002bc4: b2db uxtb r3, r3 8002bc6: 461a mov r2, r3 8002bc8: 4b66 ldr r3, [pc, #408] @ (8002d64 ) 8002bca: f883 202c strb.w r2, [r3, #44] @ 0x2c if (sensorsInfo.limitYSwitchDown == 1) 8002bce: 4b65 ldr r3, [pc, #404] @ (8002d64 ) 8002bd0: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 8002bd4: 2b01 cmp r3, #1 8002bd6: d169 bne.n 8002cac sensorsInfo.currentYPosition = 0; 8002bd8: 4b62 ldr r3, [pc, #392] @ (8002d64 ) 8002bda: f04f 0200 mov.w r2, #0 8002bde: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8002be0: 4b60 ldr r3, [pc, #384] @ (8002d64 ) 8002be2: 2200 movs r2, #0 8002be4: f883 2039 strb.w r2, [r3, #57] @ 0x39 break; 8002be8: e060 b.n 8002cac sensorsInfo.limitXSwitchCenter = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002bea: 7abb ldrb r3, [r7, #10] 8002bec: 2b01 cmp r3, #1 8002bee: bf0c ite eq 8002bf0: 2301 moveq r3, #1 8002bf2: 2300 movne r3, #0 8002bf4: b2db uxtb r3, r3 8002bf6: 461a mov r2, r3 8002bf8: 4b5a ldr r3, [pc, #360] @ (8002d64 ) 8002bfa: f883 202a strb.w r2, [r3, #42] @ 0x2a if (sensorsInfo.limitXSwitchCenter == 1) 8002bfe: 4b59 ldr r3, [pc, #356] @ (8002d64 ) 8002c00: f893 302a ldrb.w r3, [r3, #42] @ 0x2a 8002c04: 2b01 cmp r3, #1 8002c06: d153 bne.n 8002cb0 sensorsInfo.currentXPosition = 50; 8002c08: 4b56 ldr r3, [pc, #344] @ (8002d64 ) 8002c0a: 4a57 ldr r2, [pc, #348] @ (8002d68 ) 8002c0c: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8002c0e: 4b55 ldr r3, [pc, #340] @ (8002d64 ) 8002c10: 2200 movs r2, #0 8002c12: f883 2038 strb.w r2, [r3, #56] @ 0x38 break; 8002c16: e04b b.n 8002cb0 sensorsInfo.limitYSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002c18: 7abb ldrb r3, [r7, #10] 8002c1a: 2b01 cmp r3, #1 8002c1c: bf0c ite eq 8002c1e: 2301 moveq r3, #1 8002c20: 2300 movne r3, #0 8002c22: b2db uxtb r3, r3 8002c24: 461a mov r2, r3 8002c26: 4b4f ldr r3, [pc, #316] @ (8002d64 ) 8002c28: f883 202b strb.w r2, [r3, #43] @ 0x2b if (sensorsInfo.limitYSwitchUp == 1) 8002c2c: 4b4d ldr r3, [pc, #308] @ (8002d64 ) 8002c2e: f893 302b ldrb.w r3, [r3, #43] @ 0x2b 8002c32: 2b01 cmp r3, #1 8002c34: d13e bne.n 8002cb4 sensorsInfo.currentYPosition = 100; 8002c36: 4b4b ldr r3, [pc, #300] @ (8002d64 ) 8002c38: 4a4c ldr r2, [pc, #304] @ (8002d6c ) 8002c3a: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8002c3c: 4b49 ldr r3, [pc, #292] @ (8002d64 ) 8002c3e: 2200 movs r2, #0 8002c40: f883 2039 strb.w r2, [r3, #57] @ 0x39 break; 8002c44: e036 b.n 8002cb4 sensorsInfo.limitXSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002c46: 7abb ldrb r3, [r7, #10] 8002c48: 2b01 cmp r3, #1 8002c4a: bf0c ite eq 8002c4c: 2301 moveq r3, #1 8002c4e: 2300 movne r3, #0 8002c50: b2db uxtb r3, r3 8002c52: 461a mov r2, r3 8002c54: 4b43 ldr r3, [pc, #268] @ (8002d64 ) 8002c56: f883 2028 strb.w r2, [r3, #40] @ 0x28 if (sensorsInfo.limitXSwitchUp == 1) 8002c5a: 4b42 ldr r3, [pc, #264] @ (8002d64 ) 8002c5c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8002c60: 2b01 cmp r3, #1 8002c62: d129 bne.n 8002cb8 sensorsInfo.currentXPosition = 100; 8002c64: 4b3f ldr r3, [pc, #252] @ (8002d64 ) 8002c66: 4a41 ldr r2, [pc, #260] @ (8002d6c ) 8002c68: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8002c6a: 4b3e ldr r3, [pc, #248] @ (8002d64 ) 8002c6c: 2200 movs r2, #0 8002c6e: f883 2038 strb.w r2, [r3, #56] @ 0x38 break; 8002c72: e021 b.n 8002cb8 sensorsInfo.limitXSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002c74: 7abb ldrb r3, [r7, #10] 8002c76: 2b01 cmp r3, #1 8002c78: bf0c ite eq 8002c7a: 2301 moveq r3, #1 8002c7c: 2300 movne r3, #0 8002c7e: b2db uxtb r3, r3 8002c80: 461a mov r2, r3 8002c82: 4b38 ldr r3, [pc, #224] @ (8002d64 ) 8002c84: f883 2029 strb.w r2, [r3, #41] @ 0x29 if (sensorsInfo.limitXSwitchDown == 1) 8002c88: 4b36 ldr r3, [pc, #216] @ (8002d64 ) 8002c8a: f893 3029 ldrb.w r3, [r3, #41] @ 0x29 8002c8e: 2b01 cmp r3, #1 8002c90: d114 bne.n 8002cbc sensorsInfo.currentXPosition = 0; 8002c92: 4b34 ldr r3, [pc, #208] @ (8002d64 ) 8002c94: f04f 0200 mov.w r2, #0 8002c98: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8002c9a: 4b32 ldr r3, [pc, #200] @ (8002d64 ) 8002c9c: 2200 movs r2, #0 8002c9e: f883 2038 strb.w r2, [r3, #56] @ 0x38 break; 8002ca2: e00b b.n 8002cbc default: break; 8002ca4: bf00 nop 8002ca6: e00a b.n 8002cbe break; 8002ca8: bf00 nop 8002caa: e008 b.n 8002cbe break; 8002cac: bf00 nop 8002cae: e006 b.n 8002cbe break; 8002cb0: bf00 nop 8002cb2: e004 b.n 8002cbe break; 8002cb4: bf00 nop 8002cb6: e002 b.n 8002cbe break; 8002cb8: bf00 nop 8002cba: e000 b.n 8002cbe break; 8002cbc: bf00 nop } if ((sensorsInfo.limitXSwitchDown == 1) || (sensorsInfo.limitXSwitchUp == 1)) { 8002cbe: 4b29 ldr r3, [pc, #164] @ (8002d64 ) 8002cc0: f893 3029 ldrb.w r3, [r3, #41] @ 0x29 8002cc4: 2b01 cmp r3, #1 8002cc6: d004 beq.n 8002cd2 8002cc8: 4b26 ldr r3, [pc, #152] @ (8002d64 ) 8002cca: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8002cce: 2b01 cmp r3, #1 8002cd0: d118 bne.n 8002d04 sensorsInfo.motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, 0, 0, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 8002cd2: 4b27 ldr r3, [pc, #156] @ (8002d70 ) 8002cd4: 681b ldr r3, [r3, #0] 8002cd6: 4a23 ldr r2, [pc, #140] @ (8002d64 ) 8002cd8: f892 2028 ldrb.w r2, [r2, #40] @ 0x28 8002cdc: 4921 ldr r1, [pc, #132] @ (8002d64 ) 8002cde: f891 1029 ldrb.w r1, [r1, #41] @ 0x29 8002ce2: 9104 str r1, [sp, #16] 8002ce4: 9203 str r2, [sp, #12] 8002ce6: 2200 movs r2, #0 8002ce8: 9202 str r2, [sp, #8] 8002cea: 2200 movs r2, #0 8002cec: 9201 str r2, [sp, #4] 8002cee: 9300 str r3, [sp, #0] 8002cf0: 2304 movs r3, #4 8002cf2: 2200 movs r2, #0 8002cf4: 491f ldr r1, [pc, #124] @ (8002d74 ) 8002cf6: 4820 ldr r0, [pc, #128] @ (8002d78 ) 8002cf8: f000 f982 bl 8003000 8002cfc: 4603 mov r3, r0 8002cfe: 461a mov r2, r3 8002d00: 4b18 ldr r3, [pc, #96] @ (8002d64 ) 8002d02: 751a strb r2, [r3, #20] } if ((sensorsInfo.limitYSwitchDown == 1) || (sensorsInfo.limitYSwitchUp == 1)) { 8002d04: 4b17 ldr r3, [pc, #92] @ (8002d64 ) 8002d06: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 8002d0a: 2b01 cmp r3, #1 8002d0c: d004 beq.n 8002d18 8002d0e: 4b15 ldr r3, [pc, #84] @ (8002d64 ) 8002d10: f893 302b ldrb.w r3, [r3, #43] @ 0x2b 8002d14: 2b01 cmp r3, #1 8002d16: d118 bne.n 8002d4a sensorsInfo.motorYStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, 0, 0, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 8002d18: 4b18 ldr r3, [pc, #96] @ (8002d7c ) 8002d1a: 681b ldr r3, [r3, #0] 8002d1c: 4a11 ldr r2, [pc, #68] @ (8002d64 ) 8002d1e: f892 202b ldrb.w r2, [r2, #43] @ 0x2b 8002d22: 4910 ldr r1, [pc, #64] @ (8002d64 ) 8002d24: f891 102c ldrb.w r1, [r1, #44] @ 0x2c 8002d28: 9104 str r1, [sp, #16] 8002d2a: 9203 str r2, [sp, #12] 8002d2c: 2200 movs r2, #0 8002d2e: 9202 str r2, [sp, #8] 8002d30: 2200 movs r2, #0 8002d32: 9201 str r2, [sp, #4] 8002d34: 9300 str r3, [sp, #0] 8002d36: 230c movs r3, #12 8002d38: 2208 movs r2, #8 8002d3a: 490e ldr r1, [pc, #56] @ (8002d74 ) 8002d3c: 480e ldr r0, [pc, #56] @ (8002d78 ) 8002d3e: f000 f95f bl 8003000 8002d42: 4603 mov r3, r0 8002d44: 461a mov r2, r3 8002d46: 4b07 ldr r3, [pc, #28] @ (8002d64 ) 8002d48: 755a strb r2, [r3, #21] } osMutexRelease (sensorsInfoMutex); 8002d4a: 4b05 ldr r3, [pc, #20] @ (8002d60 ) 8002d4c: 681b ldr r3, [r3, #0] 8002d4e: 4618 mov r0, r3 8002d50: f011 fbec bl 801452c osMessageQueueGet (limiterSwitchDataQueue, &limiterSwitchData, 0, osWaitForever); 8002d54: e6e2 b.n 8002b1c 8002d56: bf00 nop 8002d58: 58020c00 .word 0x58020c00 8002d5c: 2400080c .word 0x2400080c 8002d60: 2400081c .word 0x2400081c 8002d64: 24000860 .word 0x24000860 8002d68: 42480000 .word 0x42480000 8002d6c: 42c80000 .word 0x42c80000 8002d70: 24000744 .word 0x24000744 8002d74: 240007c0 .word 0x240007c0 8002d78: 240004d4 .word 0x240004d4 8002d7c: 24000774 .word 0x24000774 08002d80 : } } } void EncoderTask (void* arg) { 8002d80: b580 push {r7, lr} 8002d82: b086 sub sp, #24 8002d84: af00 add r7, sp, #0 8002d86: 6078 str r0, [r7, #4] EncoderData encoderData = { 0 }; 8002d88: 2300 movs r3, #0 8002d8a: 813b strh r3, [r7, #8] osMessageQueueId_t encoderQueue = (osMessageQueueId_t)arg; 8002d8c: 687b ldr r3, [r7, #4] 8002d8e: 617b str r3, [r7, #20] while (pdTRUE) { osMessageQueueGet (encoderQueue, &encoderData, 0, osWaitForever); 8002d90: f107 0108 add.w r1, r7, #8 8002d94: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002d98: 2200 movs r2, #0 8002d9a: 6978 ldr r0, [r7, #20] 8002d9c: f011 fcd6 bl 801474c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8002da0: 4b4b ldr r3, [pc, #300] @ (8002ed0 ) 8002da2: 681b ldr r3, [r3, #0] 8002da4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002da8: 4618 mov r0, r3 8002daa: f011 fb74 bl 8014496 8002dae: 4603 mov r3, r0 8002db0: 2b00 cmp r3, #0 8002db2: d1ed bne.n 8002d90 if (encoderData.axe == encoderAxeX) { 8002db4: 7a3b ldrb r3, [r7, #8] 8002db6: 2b00 cmp r3, #0 8002db8: d142 bne.n 8002e40 if (encoderData.direction == encoderCW) { 8002dba: 7a7b ldrb r3, [r7, #9] 8002dbc: 2b00 cmp r3, #0 8002dbe: d10a bne.n 8002dd6 sensorsInfo.pvEncoderX += 360.0 / ENCODER_X_IMP_PER_TURN; 8002dc0: 4b44 ldr r3, [pc, #272] @ (8002ed4 ) 8002dc2: edd3 7a03 vldr s15, [r3, #12] 8002dc6: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002dca: ee77 7a87 vadd.f32 s15, s15, s14 8002dce: 4b41 ldr r3, [pc, #260] @ (8002ed4 ) 8002dd0: edc3 7a03 vstr s15, [r3, #12] 8002dd4: e009 b.n 8002dea } else { sensorsInfo.pvEncoderX -= 360.0 / ENCODER_X_IMP_PER_TURN; 8002dd6: 4b3f ldr r3, [pc, #252] @ (8002ed4 ) 8002dd8: edd3 7a03 vldr s15, [r3, #12] 8002ddc: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002de0: ee77 7ac7 vsub.f32 s15, s15, s14 8002de4: 4b3b ldr r3, [pc, #236] @ (8002ed4 ) 8002de6: edc3 7a03 vstr s15, [r3, #12] } float currentPercentPos = 100 * sensorsInfo.pvEncoderX / MAX_X_AXE_ANGLE; 8002dea: 4b3a ldr r3, [pc, #232] @ (8002ed4 ) 8002dec: edd3 7a03 vldr s15, [r3, #12] 8002df0: ed9f 7a39 vldr s14, [pc, #228] @ 8002ed8 8002df4: ee27 7a87 vmul.f32 s14, s15, s14 8002df8: eddf 6a38 vldr s13, [pc, #224] @ 8002edc 8002dfc: eec7 7a26 vdiv.f32 s15, s14, s13 8002e00: edc7 7a03 vstr s15, [r7, #12] currentPercentPos = currentPercentPos < 0 ? 0 : currentPercentPos; 8002e04: edd7 7a03 vldr s15, [r7, #12] 8002e08: eef5 7ac0 vcmpe.f32 s15, #0.0 8002e0c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002e10: d502 bpl.n 8002e18 8002e12: f04f 0300 mov.w r3, #0 8002e16: e000 b.n 8002e1a 8002e18: 68fb ldr r3, [r7, #12] 8002e1a: 60fb str r3, [r7, #12] sensorsInfo.currentXPosition = currentPercentPos > 100 ? 100 : currentPercentPos; 8002e1c: edd7 7a03 vldr s15, [r7, #12] 8002e20: ed9f 7a2d vldr s14, [pc, #180] @ 8002ed8 8002e24: eef4 7ac7 vcmpe.f32 s15, s14 8002e28: eef1 fa10 vmrs APSR_nzcv, fpscr 8002e2c: dd01 ble.n 8002e32 8002e2e: 4b2c ldr r3, [pc, #176] @ (8002ee0 ) 8002e30: e000 b.n 8002e34 8002e32: 68fb ldr r3, [r7, #12] 8002e34: 4a27 ldr r2, [pc, #156] @ (8002ed4 ) 8002e36: 6313 str r3, [r2, #48] @ 0x30 DbgLEDToggle(DBG_LED2); 8002e38: 2020 movs r0, #32 8002e3a: f000 f877 bl 8002f2c 8002e3e: e041 b.n 8002ec4 } else { if (encoderData.direction == encoderCW) { 8002e40: 7a7b ldrb r3, [r7, #9] 8002e42: 2b00 cmp r3, #0 8002e44: d10a bne.n 8002e5c sensorsInfo.pvEncoderY += 360.0 / ENCODER_Y_IMP_PER_TURN; 8002e46: 4b23 ldr r3, [pc, #140] @ (8002ed4 ) 8002e48: edd3 7a04 vldr s15, [r3, #16] 8002e4c: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002e50: ee77 7a87 vadd.f32 s15, s15, s14 8002e54: 4b1f ldr r3, [pc, #124] @ (8002ed4 ) 8002e56: edc3 7a04 vstr s15, [r3, #16] 8002e5a: e009 b.n 8002e70 } else { sensorsInfo.pvEncoderY -= 360.0 / ENCODER_Y_IMP_PER_TURN; 8002e5c: 4b1d ldr r3, [pc, #116] @ (8002ed4 ) 8002e5e: edd3 7a04 vldr s15, [r3, #16] 8002e62: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002e66: ee77 7ac7 vsub.f32 s15, s15, s14 8002e6a: 4b1a ldr r3, [pc, #104] @ (8002ed4 ) 8002e6c: edc3 7a04 vstr s15, [r3, #16] } float currentPercentPos = 100 * sensorsInfo.pvEncoderY / MAX_X_AXE_ANGLE; 8002e70: 4b18 ldr r3, [pc, #96] @ (8002ed4 ) 8002e72: edd3 7a04 vldr s15, [r3, #16] 8002e76: ed9f 7a18 vldr s14, [pc, #96] @ 8002ed8 8002e7a: ee27 7a87 vmul.f32 s14, s15, s14 8002e7e: eddf 6a17 vldr s13, [pc, #92] @ 8002edc 8002e82: eec7 7a26 vdiv.f32 s15, s14, s13 8002e86: edc7 7a04 vstr s15, [r7, #16] currentPercentPos = currentPercentPos < 0 ? 0 : currentPercentPos; 8002e8a: edd7 7a04 vldr s15, [r7, #16] 8002e8e: eef5 7ac0 vcmpe.f32 s15, #0.0 8002e92: eef1 fa10 vmrs APSR_nzcv, fpscr 8002e96: d502 bpl.n 8002e9e 8002e98: f04f 0300 mov.w r3, #0 8002e9c: e000 b.n 8002ea0 8002e9e: 693b ldr r3, [r7, #16] 8002ea0: 613b str r3, [r7, #16] sensorsInfo.currentXPosition = currentPercentPos > 100 ? 100 : currentPercentPos; 8002ea2: edd7 7a04 vldr s15, [r7, #16] 8002ea6: ed9f 7a0c vldr s14, [pc, #48] @ 8002ed8 8002eaa: eef4 7ac7 vcmpe.f32 s15, s14 8002eae: eef1 fa10 vmrs APSR_nzcv, fpscr 8002eb2: dd01 ble.n 8002eb8 8002eb4: 4b0a ldr r3, [pc, #40] @ (8002ee0 ) 8002eb6: e000 b.n 8002eba 8002eb8: 693b ldr r3, [r7, #16] 8002eba: 4a06 ldr r2, [pc, #24] @ (8002ed4 ) 8002ebc: 6313 str r3, [r2, #48] @ 0x30 DbgLEDToggle(DBG_LED3); 8002ebe: 2040 movs r0, #64 @ 0x40 8002ec0: f000 f834 bl 8002f2c } osMutexRelease (sensorsInfoMutex); 8002ec4: 4b02 ldr r3, [pc, #8] @ (8002ed0 ) 8002ec6: 681b ldr r3, [r3, #0] 8002ec8: 4618 mov r0, r3 8002eca: f011 fb2f bl 801452c osMessageQueueGet (encoderQueue, &encoderData, 0, osWaitForever); 8002ece: e75f b.n 8002d90 8002ed0: 2400081c .word 0x2400081c 8002ed4: 24000860 .word 0x24000860 8002ed8: 42c80000 .word 0x42c80000 8002edc: 43b40000 .word 0x43b40000 8002ee0: 42c80000 .word 0x42c80000 08002ee4 : #include #include "peripherial.h" void DbgLEDOn (uint8_t ledNumber) { 8002ee4: b580 push {r7, lr} 8002ee6: b082 sub sp, #8 8002ee8: af00 add r7, sp, #0 8002eea: 4603 mov r3, r0 8002eec: 71fb strb r3, [r7, #7] HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_SET); 8002eee: 79fb ldrb r3, [r7, #7] 8002ef0: b29b uxth r3, r3 8002ef2: 2201 movs r2, #1 8002ef4: 4619 mov r1, r3 8002ef6: 4803 ldr r0, [pc, #12] @ (8002f04 ) 8002ef8: f008 fb20 bl 800b53c } 8002efc: bf00 nop 8002efe: 3708 adds r7, #8 8002f00: 46bd mov sp, r7 8002f02: bd80 pop {r7, pc} 8002f04: 58020c00 .word 0x58020c00 08002f08 : void DbgLEDOff (uint8_t ledNumber) { 8002f08: b580 push {r7, lr} 8002f0a: b082 sub sp, #8 8002f0c: af00 add r7, sp, #0 8002f0e: 4603 mov r3, r0 8002f10: 71fb strb r3, [r7, #7] HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_RESET); 8002f12: 79fb ldrb r3, [r7, #7] 8002f14: b29b uxth r3, r3 8002f16: 2200 movs r2, #0 8002f18: 4619 mov r1, r3 8002f1a: 4803 ldr r0, [pc, #12] @ (8002f28 ) 8002f1c: f008 fb0e bl 800b53c } 8002f20: bf00 nop 8002f22: 3708 adds r7, #8 8002f24: 46bd mov sp, r7 8002f26: bd80 pop {r7, pc} 8002f28: 58020c00 .word 0x58020c00 08002f2c : void DbgLEDToggle (uint8_t ledNumber) { 8002f2c: b580 push {r7, lr} 8002f2e: b082 sub sp, #8 8002f30: af00 add r7, sp, #0 8002f32: 4603 mov r3, r0 8002f34: 71fb strb r3, [r7, #7] HAL_GPIO_TogglePin (GPIOD, ledNumber); 8002f36: 79fb ldrb r3, [r7, #7] 8002f38: b29b uxth r3, r3 8002f3a: 4619 mov r1, r3 8002f3c: 4803 ldr r0, [pc, #12] @ (8002f4c ) 8002f3e: f008 fb16 bl 800b56e } 8002f42: bf00 nop 8002f44: 3708 adds r7, #8 8002f46: 46bd mov sp, r7 8002f48: bd80 pop {r7, pc} 8002f4a: bf00 nop 8002f4c: 58020c00 .word 0x58020c00 08002f50 : void EnableCurrentSensors (void) { 8002f50: b580 push {r7, lr} 8002f52: af00 add r7, sp, #0 HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_SET); 8002f54: 2201 movs r2, #1 8002f56: f44f 4100 mov.w r1, #32768 @ 0x8000 8002f5a: 4802 ldr r0, [pc, #8] @ (8002f64 ) 8002f5c: f008 faee bl 800b53c } 8002f60: bf00 nop 8002f62: bd80 pop {r7, pc} 8002f64: 58021000 .word 0x58021000 08002f68 : void DisableCurrentSensors (void) { HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_RESET); } void SelectCurrentSensorGain (CurrentSensor sensor, CurrentSensorGain gain) { 8002f68: b580 push {r7, lr} 8002f6a: b084 sub sp, #16 8002f6c: af00 add r7, sp, #0 8002f6e: 4603 mov r3, r0 8002f70: 460a mov r2, r1 8002f72: 71fb strb r3, [r7, #7] 8002f74: 4613 mov r3, r2 8002f76: 71bb strb r3, [r7, #6] uint8_t gpioOffset = 0; 8002f78: 2300 movs r3, #0 8002f7a: 73fb strb r3, [r7, #15] switch (sensor) { 8002f7c: 79fb ldrb r3, [r7, #7] 8002f7e: 2b02 cmp r3, #2 8002f80: d00c beq.n 8002f9c 8002f82: 2b02 cmp r3, #2 8002f84: dc0d bgt.n 8002fa2 8002f86: 2b00 cmp r3, #0 8002f88: d002 beq.n 8002f90 8002f8a: 2b01 cmp r3, #1 8002f8c: d003 beq.n 8002f96 case CurrentSensorL1: gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET; break; case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break; case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break; default: break; 8002f8e: e008 b.n 8002fa2 case CurrentSensorL1: gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET; break; 8002f90: 2307 movs r3, #7 8002f92: 73fb strb r3, [r7, #15] 8002f94: e006 b.n 8002fa4 case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break; 8002f96: 2309 movs r3, #9 8002f98: 73fb strb r3, [r7, #15] 8002f9a: e003 b.n 8002fa4 case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break; 8002f9c: 230d movs r3, #13 8002f9e: 73fb strb r3, [r7, #15] 8002fa0: e000 b.n 8002fa4 default: break; 8002fa2: bf00 nop } if (gpioOffset > 0) { 8002fa4: 7bfb ldrb r3, [r7, #15] 8002fa6: 2b00 cmp r3, #0 8002fa8: d023 beq.n 8002ff2 uint16_t gain0Gpio = 1 << gpioOffset; 8002faa: 7bfb ldrb r3, [r7, #15] 8002fac: 2201 movs r2, #1 8002fae: fa02 f303 lsl.w r3, r2, r3 8002fb2: 81bb strh r3, [r7, #12] uint16_t gain1Gpio = 1 << (gpioOffset + 1); 8002fb4: 7bfb ldrb r3, [r7, #15] 8002fb6: 3301 adds r3, #1 8002fb8: 2201 movs r2, #1 8002fba: fa02 f303 lsl.w r3, r2, r3 8002fbe: 817b strh r3, [r7, #10] uint16_t gpioState = ((uint16_t)gain) & 0x0001; 8002fc0: 79bb ldrb r3, [r7, #6] 8002fc2: b29b uxth r3, r3 8002fc4: f003 0301 and.w r3, r3, #1 8002fc8: 813b strh r3, [r7, #8] HAL_GPIO_WritePin (GPIOE, gain0Gpio, gpioState); 8002fca: 893b ldrh r3, [r7, #8] 8002fcc: b2da uxtb r2, r3 8002fce: 89bb ldrh r3, [r7, #12] 8002fd0: 4619 mov r1, r3 8002fd2: 480a ldr r0, [pc, #40] @ (8002ffc ) 8002fd4: f008 fab2 bl 800b53c gpioState = (((uint16_t)gain) >> 1) & 0x0001; 8002fd8: 79bb ldrb r3, [r7, #6] 8002fda: 085b lsrs r3, r3, #1 8002fdc: b2db uxtb r3, r3 8002fde: f003 0301 and.w r3, r3, #1 8002fe2: 813b strh r3, [r7, #8] HAL_GPIO_WritePin (GPIOE, gain1Gpio, gpioState); 8002fe4: 893b ldrh r3, [r7, #8] 8002fe6: b2da uxtb r2, r3 8002fe8: 897b ldrh r3, [r7, #10] 8002fea: 4619 mov r1, r3 8002fec: 4803 ldr r0, [pc, #12] @ (8002ffc ) 8002fee: f008 faa5 bl 800b53c } } 8002ff2: bf00 nop 8002ff4: 3710 adds r7, #16 8002ff6: 46bd mov sp, r7 8002ff8: bd80 pop {r7, pc} 8002ffa: bf00 nop 8002ffc: 58021000 .word 0x58021000 08003000 : uint8_t MotorControl (TIM_HandleTypeDef* htim, TIM_OC_InitTypeDef* motorTimerConfigOC, uint8_t channel1, uint8_t channel2, osTimerId_t motorTimerHandle, int32_t motorPWMPulse, int32_t motorTimerPeriod, uint8_t switchLimiterUpStat, uint8_t switchLimiterDownStat) { 8003000: b580 push {r7, lr} 8003002: b088 sub sp, #32 8003004: af02 add r7, sp, #8 8003006: 60f8 str r0, [r7, #12] 8003008: 60b9 str r1, [r7, #8] 800300a: 4611 mov r1, r2 800300c: 461a mov r2, r3 800300e: 460b mov r3, r1 8003010: 71fb strb r3, [r7, #7] 8003012: 4613 mov r3, r2 8003014: 71bb strb r3, [r7, #6] uint32_t motorStatus = 0; 8003016: 2300 movs r3, #0 8003018: 617b str r3, [r7, #20] MotorDriverState setMotorState = HiZ; 800301a: 2300 movs r3, #0 800301c: 74fb strb r3, [r7, #19] HAL_TIM_PWM_Stop (htim, channel1); 800301e: 79fb ldrb r3, [r7, #7] 8003020: 4619 mov r1, r3 8003022: 68f8 ldr r0, [r7, #12] 8003024: f00c fc92 bl 800f94c HAL_TIM_PWM_Stop (htim, channel2); 8003028: 79bb ldrb r3, [r7, #6] 800302a: 4619 mov r1, r3 800302c: 68f8 ldr r0, [r7, #12] 800302e: f00c fc8d bl 800f94c if (motorTimerPeriod > 0) { 8003032: 6abb ldr r3, [r7, #40] @ 0x28 8003034: 2b00 cmp r3, #0 8003036: f340 808c ble.w 8003152 if (motorPWMPulse > 0) { 800303a: 6a7b ldr r3, [r7, #36] @ 0x24 800303c: 2b00 cmp r3, #0 800303e: dd2c ble.n 800309a // Forward if (switchLimiterUpStat == 0) { 8003040: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 8003044: 2b00 cmp r3, #0 8003046: d11d bne.n 8003084 setMotorState = Forward; 8003048: 2301 movs r3, #1 800304a: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 800304c: 79f9 ldrb r1, [r7, #7] 800304e: 79b8 ldrb r0, [r7, #6] 8003050: 6a7b ldr r3, [r7, #36] @ 0x24 8003052: ea83 72e3 eor.w r2, r3, r3, asr #31 8003056: eba2 72e3 sub.w r2, r2, r3, asr #31 800305a: 4613 mov r3, r2 800305c: 009b lsls r3, r3, #2 800305e: 4413 add r3, r2 8003060: 005b lsls r3, r3, #1 8003062: 9301 str r3, [sp, #4] 8003064: 7cfb ldrb r3, [r7, #19] 8003066: 9300 str r3, [sp, #0] 8003068: 4603 mov r3, r0 800306a: 460a mov r2, r1 800306c: 68b9 ldr r1, [r7, #8] 800306e: 68f8 ldr r0, [r7, #12] 8003070: f000 f8ff bl 8003272 HAL_TIM_PWM_Start (htim, channel1); 8003074: 79fb ldrb r3, [r7, #7] 8003076: 4619 mov r1, r3 8003078: 68f8 ldr r0, [r7, #12] 800307a: f00c fb59 bl 800f730 motorStatus = 1; 800307e: 2301 movs r3, #1 8003080: 617b str r3, [r7, #20] 8003082: e004 b.n 800308e } else { HAL_TIM_PWM_Stop (htim, channel1); 8003084: 79fb ldrb r3, [r7, #7] 8003086: 4619 mov r1, r3 8003088: 68f8 ldr r0, [r7, #12] 800308a: f00c fc5f bl 800f94c } HAL_TIM_PWM_Stop (htim, channel2); 800308e: 79bb ldrb r3, [r7, #6] 8003090: 4619 mov r1, r3 8003092: 68f8 ldr r0, [r7, #12] 8003094: f00c fc5a bl 800f94c 8003098: e051 b.n 800313e } else if (motorPWMPulse < 0) { 800309a: 6a7b ldr r3, [r7, #36] @ 0x24 800309c: 2b00 cmp r3, #0 800309e: da2c bge.n 80030fa // Reverse if (switchLimiterDownStat == 0) { 80030a0: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 80030a4: 2b00 cmp r3, #0 80030a6: d11d bne.n 80030e4 setMotorState = Reverse; 80030a8: 2302 movs r3, #2 80030aa: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 80030ac: 79f9 ldrb r1, [r7, #7] 80030ae: 79b8 ldrb r0, [r7, #6] 80030b0: 6a7b ldr r3, [r7, #36] @ 0x24 80030b2: ea83 72e3 eor.w r2, r3, r3, asr #31 80030b6: eba2 72e3 sub.w r2, r2, r3, asr #31 80030ba: 4613 mov r3, r2 80030bc: 009b lsls r3, r3, #2 80030be: 4413 add r3, r2 80030c0: 005b lsls r3, r3, #1 80030c2: 9301 str r3, [sp, #4] 80030c4: 7cfb ldrb r3, [r7, #19] 80030c6: 9300 str r3, [sp, #0] 80030c8: 4603 mov r3, r0 80030ca: 460a mov r2, r1 80030cc: 68b9 ldr r1, [r7, #8] 80030ce: 68f8 ldr r0, [r7, #12] 80030d0: f000 f8cf bl 8003272 HAL_TIM_PWM_Start (htim, channel2); 80030d4: 79bb ldrb r3, [r7, #6] 80030d6: 4619 mov r1, r3 80030d8: 68f8 ldr r0, [r7, #12] 80030da: f00c fb29 bl 800f730 motorStatus = 1; 80030de: 2301 movs r3, #1 80030e0: 617b str r3, [r7, #20] 80030e2: e004 b.n 80030ee } else { HAL_TIM_PWM_Stop (htim, channel2); 80030e4: 79bb ldrb r3, [r7, #6] 80030e6: 4619 mov r1, r3 80030e8: 68f8 ldr r0, [r7, #12] 80030ea: f00c fc2f bl 800f94c } HAL_TIM_PWM_Stop (htim, channel1); 80030ee: 79fb ldrb r3, [r7, #7] 80030f0: 4619 mov r1, r3 80030f2: 68f8 ldr r0, [r7, #12] 80030f4: f00c fc2a bl 800f94c 80030f8: e021 b.n 800313e } else { // Brake setMotorState = Brake; 80030fa: 2303 movs r3, #3 80030fc: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 80030fe: 79f9 ldrb r1, [r7, #7] 8003100: 79b8 ldrb r0, [r7, #6] 8003102: 6a7b ldr r3, [r7, #36] @ 0x24 8003104: ea83 72e3 eor.w r2, r3, r3, asr #31 8003108: eba2 72e3 sub.w r2, r2, r3, asr #31 800310c: 4613 mov r3, r2 800310e: 009b lsls r3, r3, #2 8003110: 4413 add r3, r2 8003112: 005b lsls r3, r3, #1 8003114: 9301 str r3, [sp, #4] 8003116: 7cfb ldrb r3, [r7, #19] 8003118: 9300 str r3, [sp, #0] 800311a: 4603 mov r3, r0 800311c: 460a mov r2, r1 800311e: 68b9 ldr r1, [r7, #8] 8003120: 68f8 ldr r0, [r7, #12] 8003122: f000 f8a6 bl 8003272 HAL_TIM_PWM_Start (htim, channel1); 8003126: 79fb ldrb r3, [r7, #7] 8003128: 4619 mov r1, r3 800312a: 68f8 ldr r0, [r7, #12] 800312c: f00c fb00 bl 800f730 HAL_TIM_PWM_Start (htim, channel2); 8003130: 79bb ldrb r3, [r7, #6] 8003132: 4619 mov r1, r3 8003134: 68f8 ldr r0, [r7, #12] 8003136: f00c fafb bl 800f730 motorStatus = 0; 800313a: 2300 movs r3, #0 800313c: 617b str r3, [r7, #20] } osTimerStart (motorTimerHandle, motorTimerPeriod * 1000); 800313e: 6abb ldr r3, [r7, #40] @ 0x28 8003140: f44f 727a mov.w r2, #1000 @ 0x3e8 8003144: fb02 f303 mul.w r3, r2, r3 8003148: 4619 mov r1, r3 800314a: 6a38 ldr r0, [r7, #32] 800314c: f011 f8b8 bl 80142c0 8003150: e089 b.n 8003266 } else if ((motorTimerPeriod == 0) && (motorPWMPulse == 0)) { 8003152: 6abb ldr r3, [r7, #40] @ 0x28 8003154: 2b00 cmp r3, #0 8003156: d126 bne.n 80031a6 8003158: 6a7b ldr r3, [r7, #36] @ 0x24 800315a: 2b00 cmp r3, #0 800315c: d123 bne.n 80031a6 MotorAction (htim, motorTimerConfigOC, channel1, channel2, HiZ, abs (motorPWMPulse) * 10); 800315e: 79f9 ldrb r1, [r7, #7] 8003160: 79b8 ldrb r0, [r7, #6] 8003162: 6a7b ldr r3, [r7, #36] @ 0x24 8003164: ea83 72e3 eor.w r2, r3, r3, asr #31 8003168: eba2 72e3 sub.w r2, r2, r3, asr #31 800316c: 4613 mov r3, r2 800316e: 009b lsls r3, r3, #2 8003170: 4413 add r3, r2 8003172: 005b lsls r3, r3, #1 8003174: 9301 str r3, [sp, #4] 8003176: 2300 movs r3, #0 8003178: 9300 str r3, [sp, #0] 800317a: 4603 mov r3, r0 800317c: 460a mov r2, r1 800317e: 68b9 ldr r1, [r7, #8] 8003180: 68f8 ldr r0, [r7, #12] 8003182: f000 f876 bl 8003272 HAL_TIM_PWM_Stop (htim, channel1); 8003186: 79fb ldrb r3, [r7, #7] 8003188: 4619 mov r1, r3 800318a: 68f8 ldr r0, [r7, #12] 800318c: f00c fbde bl 800f94c HAL_TIM_PWM_Stop (htim, channel2); 8003190: 79bb ldrb r3, [r7, #6] 8003192: 4619 mov r1, r3 8003194: 68f8 ldr r0, [r7, #12] 8003196: f00c fbd9 bl 800f94c osTimerStop (motorTimerHandle); 800319a: 6a38 ldr r0, [r7, #32] 800319c: f011 f8be bl 801431c motorStatus = 0; 80031a0: 2300 movs r3, #0 80031a2: 617b str r3, [r7, #20] 80031a4: e05f b.n 8003266 } else if (motorTimerPeriod == -1) { 80031a6: 6abb ldr r3, [r7, #40] @ 0x28 80031a8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80031ac: d15b bne.n 8003266 if (motorPWMPulse > 0) { 80031ae: 6a7b ldr r3, [r7, #36] @ 0x24 80031b0: 2b00 cmp r3, #0 80031b2: dd2c ble.n 800320e // Forward if (switchLimiterUpStat == 0) { 80031b4: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 80031b8: 2b00 cmp r3, #0 80031ba: d11d bne.n 80031f8 setMotorState = Forward; 80031bc: 2301 movs r3, #1 80031be: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 80031c0: 79f9 ldrb r1, [r7, #7] 80031c2: 79b8 ldrb r0, [r7, #6] 80031c4: 6a7b ldr r3, [r7, #36] @ 0x24 80031c6: ea83 72e3 eor.w r2, r3, r3, asr #31 80031ca: eba2 72e3 sub.w r2, r2, r3, asr #31 80031ce: 4613 mov r3, r2 80031d0: 009b lsls r3, r3, #2 80031d2: 4413 add r3, r2 80031d4: 005b lsls r3, r3, #1 80031d6: 9301 str r3, [sp, #4] 80031d8: 7cfb ldrb r3, [r7, #19] 80031da: 9300 str r3, [sp, #0] 80031dc: 4603 mov r3, r0 80031de: 460a mov r2, r1 80031e0: 68b9 ldr r1, [r7, #8] 80031e2: 68f8 ldr r0, [r7, #12] 80031e4: f000 f845 bl 8003272 HAL_TIM_PWM_Start (htim, channel1); 80031e8: 79fb ldrb r3, [r7, #7] 80031ea: 4619 mov r1, r3 80031ec: 68f8 ldr r0, [r7, #12] 80031ee: f00c fa9f bl 800f730 motorStatus = 1; 80031f2: 2301 movs r3, #1 80031f4: 617b str r3, [r7, #20] 80031f6: e004 b.n 8003202 } else { HAL_TIM_PWM_Stop (htim, channel1); 80031f8: 79fb ldrb r3, [r7, #7] 80031fa: 4619 mov r1, r3 80031fc: 68f8 ldr r0, [r7, #12] 80031fe: f00c fba5 bl 800f94c } HAL_TIM_PWM_Stop (htim, channel2); 8003202: 79bb ldrb r3, [r7, #6] 8003204: 4619 mov r1, r3 8003206: 68f8 ldr r0, [r7, #12] 8003208: f00c fba0 bl 800f94c 800320c: e02b b.n 8003266 } else { // Reverse if (switchLimiterDownStat == 0) { 800320e: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 8003212: 2b00 cmp r3, #0 8003214: d11d bne.n 8003252 setMotorState = Reverse; 8003216: 2302 movs r3, #2 8003218: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 800321a: 79f9 ldrb r1, [r7, #7] 800321c: 79b8 ldrb r0, [r7, #6] 800321e: 6a7b ldr r3, [r7, #36] @ 0x24 8003220: ea83 72e3 eor.w r2, r3, r3, asr #31 8003224: eba2 72e3 sub.w r2, r2, r3, asr #31 8003228: 4613 mov r3, r2 800322a: 009b lsls r3, r3, #2 800322c: 4413 add r3, r2 800322e: 005b lsls r3, r3, #1 8003230: 9301 str r3, [sp, #4] 8003232: 7cfb ldrb r3, [r7, #19] 8003234: 9300 str r3, [sp, #0] 8003236: 4603 mov r3, r0 8003238: 460a mov r2, r1 800323a: 68b9 ldr r1, [r7, #8] 800323c: 68f8 ldr r0, [r7, #12] 800323e: f000 f818 bl 8003272 HAL_TIM_PWM_Start (htim, channel2); 8003242: 79bb ldrb r3, [r7, #6] 8003244: 4619 mov r1, r3 8003246: 68f8 ldr r0, [r7, #12] 8003248: f00c fa72 bl 800f730 motorStatus = 1; 800324c: 2301 movs r3, #1 800324e: 617b str r3, [r7, #20] 8003250: e004 b.n 800325c } else { HAL_TIM_PWM_Stop (htim, channel2); 8003252: 79bb ldrb r3, [r7, #6] 8003254: 4619 mov r1, r3 8003256: 68f8 ldr r0, [r7, #12] 8003258: f00c fb78 bl 800f94c } HAL_TIM_PWM_Stop (htim, channel1); 800325c: 79fb ldrb r3, [r7, #7] 800325e: 4619 mov r1, r3 8003260: 68f8 ldr r0, [r7, #12] 8003262: f00c fb73 bl 800f94c } } return motorStatus; 8003266: 697b ldr r3, [r7, #20] 8003268: b2db uxtb r3, r3 } 800326a: 4618 mov r0, r3 800326c: 3718 adds r7, #24 800326e: 46bd mov sp, r7 8003270: bd80 pop {r7, pc} 08003272 : void MotorAction (TIM_HandleTypeDef* tim, TIM_OC_InitTypeDef* timerConf, uint32_t channel1, uint32_t channel2, MotorDriverState setState, uint32_t pulse) { 8003272: b580 push {r7, lr} 8003274: b084 sub sp, #16 8003276: af00 add r7, sp, #0 8003278: 60f8 str r0, [r7, #12] 800327a: 60b9 str r1, [r7, #8] 800327c: 607a str r2, [r7, #4] 800327e: 603b str r3, [r7, #0] timerConf->Pulse = pulse; 8003280: 68bb ldr r3, [r7, #8] 8003282: 69fa ldr r2, [r7, #28] 8003284: 605a str r2, [r3, #4] switch (setState) { 8003286: 7e3b ldrb r3, [r7, #24] 8003288: 2b02 cmp r3, #2 800328a: dc02 bgt.n 8003292 800328c: 2b00 cmp r3, #0 800328e: da03 bge.n 8003298 8003290: e038 b.n 8003304 8003292: 2b03 cmp r3, #3 8003294: d01b beq.n 80032ce 8003296: e035 b.n 8003304 case Forward: case Reverse: case HiZ: timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8003298: 68bb ldr r3, [r7, #8] 800329a: 2200 movs r2, #0 800329c: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 800329e: 687a ldr r2, [r7, #4] 80032a0: 68b9 ldr r1, [r7, #8] 80032a2: 68f8 ldr r0, [r7, #12] 80032a4: f00c ff3e bl 8010124 80032a8: 4603 mov r3, r0 80032aa: 2b00 cmp r3, #0 80032ac: d001 beq.n 80032b2 Error_Handler (); 80032ae: f7fe fe0d bl 8001ecc } timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 80032b2: 68bb ldr r3, [r7, #8] 80032b4: 2200 movs r2, #0 80032b6: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80032b8: 683a ldr r2, [r7, #0] 80032ba: 68b9 ldr r1, [r7, #8] 80032bc: 68f8 ldr r0, [r7, #12] 80032be: f00c ff31 bl 8010124 80032c2: 4603 mov r3, r0 80032c4: 2b00 cmp r3, #0 80032c6: d038 beq.n 800333a Error_Handler (); 80032c8: f7fe fe00 bl 8001ecc } break; 80032cc: e035 b.n 800333a case Brake: timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 80032ce: 68bb ldr r3, [r7, #8] 80032d0: 2202 movs r2, #2 80032d2: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 80032d4: 687a ldr r2, [r7, #4] 80032d6: 68b9 ldr r1, [r7, #8] 80032d8: 68f8 ldr r0, [r7, #12] 80032da: f00c ff23 bl 8010124 80032de: 4603 mov r3, r0 80032e0: 2b00 cmp r3, #0 80032e2: d001 beq.n 80032e8 Error_Handler (); 80032e4: f7fe fdf2 bl 8001ecc } timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 80032e8: 68bb ldr r3, [r7, #8] 80032ea: 2202 movs r2, #2 80032ec: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80032ee: 683a ldr r2, [r7, #0] 80032f0: 68b9 ldr r1, [r7, #8] 80032f2: 68f8 ldr r0, [r7, #12] 80032f4: f00c ff16 bl 8010124 80032f8: 4603 mov r3, r0 80032fa: 2b00 cmp r3, #0 80032fc: d01f beq.n 800333e Error_Handler (); 80032fe: f7fe fde5 bl 8001ecc } break; 8003302: e01c b.n 800333e default: timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8003304: 68bb ldr r3, [r7, #8] 8003306: 2200 movs r2, #0 8003308: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 800330a: 687a ldr r2, [r7, #4] 800330c: 68b9 ldr r1, [r7, #8] 800330e: 68f8 ldr r0, [r7, #12] 8003310: f00c ff08 bl 8010124 8003314: 4603 mov r3, r0 8003316: 2b00 cmp r3, #0 8003318: d001 beq.n 800331e Error_Handler (); 800331a: f7fe fdd7 bl 8001ecc } timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 800331e: 68bb ldr r3, [r7, #8] 8003320: 2200 movs r2, #0 8003322: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 8003324: 683a ldr r2, [r7, #0] 8003326: 68b9 ldr r1, [r7, #8] 8003328: 68f8 ldr r0, [r7, #12] 800332a: f00c fefb bl 8010124 800332e: 4603 mov r3, r0 8003330: 2b00 cmp r3, #0 8003332: d006 beq.n 8003342 Error_Handler (); 8003334: f7fe fdca bl 8001ecc } break; 8003338: e003 b.n 8003342 break; 800333a: bf00 nop 800333c: e002 b.n 8003344 break; 800333e: bf00 nop 8003340: e000 b.n 8003344 break; 8003342: bf00 nop } } 8003344: bf00 nop 8003346: 3710 adds r7, #16 8003348: 46bd mov sp, r7 800334a: bd80 pop {r7, pc} 0800334c : extern osTimerId_t motorXTimerHandle; extern osTimerId_t motorYTimerHandle; extern TIM_HandleTypeDef htim3; extern TIM_OC_InitTypeDef motorXYTimerConfigOC; void PositionControlTaskInit (void) { 800334c: b580 push {r7, lr} 800334e: b08a sub sp, #40 @ 0x28 8003350: af00 add r7, sp, #0 positionSettingMutex = osMutexNew (NULL); 8003352: 2000 movs r0, #0 8003354: f011 f819 bl 801438a 8003358: 4603 mov r3, r0 800335a: 4a42 ldr r2, [pc, #264] @ (8003464 ) 800335c: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttrPositionControlTask = { 0 }; 800335e: 1d3b adds r3, r7, #4 8003360: 2224 movs r2, #36 @ 0x24 8003362: 2100 movs r1, #0 8003364: 4618 mov r0, r3 8003366: f014 ffbf bl 80182e8 osThreadAttrPositionControlTask.stack_size = configMINIMAL_STACK_SIZE * 2; 800336a: f44f 6380 mov.w r3, #1024 @ 0x400 800336e: 61bb str r3, [r7, #24] osThreadAttrPositionControlTask.priority = (osPriority_t)osPriorityNormal; 8003370: 2318 movs r3, #24 8003372: 61fb str r3, [r7, #28] positionXControlTaskInitArg.channel1 = TIM_CHANNEL_1; 8003374: 4b3c ldr r3, [pc, #240] @ (8003468 ) 8003376: 2200 movs r2, #0 8003378: 721a strb r2, [r3, #8] positionXControlTaskInitArg.channel2 = TIM_CHANNEL_2; 800337a: 4b3b ldr r3, [pc, #236] @ (8003468 ) 800337c: 2204 movs r2, #4 800337e: 725a strb r2, [r3, #9] positionXControlTaskInitArg.htim = &htim3; 8003380: 4b39 ldr r3, [pc, #228] @ (8003468 ) 8003382: 4a3a ldr r2, [pc, #232] @ (800346c ) 8003384: 601a str r2, [r3, #0] positionXControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC; 8003386: 4b38 ldr r3, [pc, #224] @ (8003468 ) 8003388: 4a39 ldr r2, [pc, #228] @ (8003470 ) 800338a: 605a str r2, [r3, #4] positionXControlTaskInitArg.motorTimerHandle = motorXTimerHandle; 800338c: 4b39 ldr r3, [pc, #228] @ (8003474 ) 800338e: 681b ldr r3, [r3, #0] 8003390: 4a35 ldr r2, [pc, #212] @ (8003468 ) 8003392: 60d3 str r3, [r2, #12] positionXControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 8003394: 2200 movs r2, #0 8003396: 2104 movs r1, #4 8003398: 2010 movs r0, #16 800339a: f011 f904 bl 80145a6 800339e: 4603 mov r3, r0 80033a0: 4a31 ldr r2, [pc, #196] @ (8003468 ) 80033a2: 6113 str r3, [r2, #16] positionXControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitXSwitchCenter); 80033a4: 4b30 ldr r3, [pc, #192] @ (8003468 ) 80033a6: 4a34 ldr r2, [pc, #208] @ (8003478 ) 80033a8: 61da str r2, [r3, #28] positionXControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitXSwitchUp); 80033aa: 4b2f ldr r3, [pc, #188] @ (8003468 ) 80033ac: 4a33 ldr r2, [pc, #204] @ (800347c ) 80033ae: 615a str r2, [r3, #20] positionXControlTaskInitArg.switchLimiterDownStat = &(sensorsInfo.limitXSwitchDown); 80033b0: 4b2d ldr r3, [pc, #180] @ (8003468 ) 80033b2: 4a33 ldr r2, [pc, #204] @ (8003480 ) 80033b4: 619a str r2, [r3, #24] positionXControlTaskInitArg.currentPosition = &(sensorsInfo.currentXPosition); 80033b6: 4b2c ldr r3, [pc, #176] @ (8003468 ) 80033b8: 4a32 ldr r2, [pc, #200] @ (8003484 ) 80033ba: 621a str r2, [r3, #32] positionXControlTaskInitArg.motorStatus = &(sensorsInfo.motorXStatus); 80033bc: 4b2a ldr r3, [pc, #168] @ (8003468 ) 80033be: 4a32 ldr r2, [pc, #200] @ (8003488 ) 80033c0: 629a str r2, [r3, #40] @ 0x28 positionXControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorXPeakCurrent); 80033c2: 4b29 ldr r3, [pc, #164] @ (8003468 ) 80033c4: 4a31 ldr r2, [pc, #196] @ (800348c ) 80033c6: 62da str r2, [r3, #44] @ 0x2c positionXControlTaskInitArg.positionSetting = &positionXSetting; 80033c8: 4b27 ldr r3, [pc, #156] @ (8003468 ) 80033ca: 4a31 ldr r2, [pc, #196] @ (8003490 ) 80033cc: 625a str r2, [r3, #36] @ 0x24 positionXControlTaskInitArg.axe = 'X'; 80033ce: 4b26 ldr r3, [pc, #152] @ (8003468 ) 80033d0: 2258 movs r2, #88 @ 0x58 80033d2: f883 2030 strb.w r2, [r3, #48] @ 0x30 positionYControlTaskInitArg.channel1 = TIM_CHANNEL_3; 80033d6: 4b2f ldr r3, [pc, #188] @ (8003494 ) 80033d8: 2208 movs r2, #8 80033da: 721a strb r2, [r3, #8] positionYControlTaskInitArg.channel2 = TIM_CHANNEL_4; 80033dc: 4b2d ldr r3, [pc, #180] @ (8003494 ) 80033de: 220c movs r2, #12 80033e0: 725a strb r2, [r3, #9] positionYControlTaskInitArg.htim = &htim3; 80033e2: 4b2c ldr r3, [pc, #176] @ (8003494 ) 80033e4: 4a21 ldr r2, [pc, #132] @ (800346c ) 80033e6: 601a str r2, [r3, #0] positionYControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC; 80033e8: 4b2a ldr r3, [pc, #168] @ (8003494 ) 80033ea: 4a21 ldr r2, [pc, #132] @ (8003470 ) 80033ec: 605a str r2, [r3, #4] positionYControlTaskInitArg.motorTimerHandle = motorYTimerHandle; 80033ee: 4b2a ldr r3, [pc, #168] @ (8003498 ) 80033f0: 681b ldr r3, [r3, #0] 80033f2: 4a28 ldr r2, [pc, #160] @ (8003494 ) 80033f4: 60d3 str r3, [r2, #12] positionYControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 80033f6: 2200 movs r2, #0 80033f8: 2104 movs r1, #4 80033fa: 2010 movs r0, #16 80033fc: f011 f8d3 bl 80145a6 8003400: 4603 mov r3, r0 8003402: 4a24 ldr r2, [pc, #144] @ (8003494 ) 8003404: 6113 str r3, [r2, #16] positionYControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitYSwitchCenter); 8003406: 4b23 ldr r3, [pc, #140] @ (8003494 ) 8003408: 4a24 ldr r2, [pc, #144] @ (800349c ) 800340a: 61da str r2, [r3, #28] positionYControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitYSwitchUp); 800340c: 4b21 ldr r3, [pc, #132] @ (8003494 ) 800340e: 4a24 ldr r2, [pc, #144] @ (80034a0 ) 8003410: 615a str r2, [r3, #20] positionYControlTaskInitArg.switchLimiterDownStat = &(sensorsInfo.limitYSwitchDown); 8003412: 4b20 ldr r3, [pc, #128] @ (8003494 ) 8003414: 4a23 ldr r2, [pc, #140] @ (80034a4 ) 8003416: 619a str r2, [r3, #24] positionYControlTaskInitArg.currentPosition = &(sensorsInfo.currentYPosition); 8003418: 4b1e ldr r3, [pc, #120] @ (8003494 ) 800341a: 4a23 ldr r2, [pc, #140] @ (80034a8 ) 800341c: 621a str r2, [r3, #32] positionYControlTaskInitArg.motorStatus = &(sensorsInfo.motorYStatus); 800341e: 4b1d ldr r3, [pc, #116] @ (8003494 ) 8003420: 4a22 ldr r2, [pc, #136] @ (80034ac ) 8003422: 629a str r2, [r3, #40] @ 0x28 positionYControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorYPeakCurrent); 8003424: 4b1b ldr r3, [pc, #108] @ (8003494 ) 8003426: 4a22 ldr r2, [pc, #136] @ (80034b0 ) 8003428: 62da str r2, [r3, #44] @ 0x2c positionXControlTaskInitArg.positionSetting = &positionYSetting; 800342a: 4b0f ldr r3, [pc, #60] @ (8003468 ) 800342c: 4a21 ldr r2, [pc, #132] @ (80034b4 ) 800342e: 625a str r2, [r3, #36] @ 0x24 positionYControlTaskInitArg.axe = 'Y'; 8003430: 4b18 ldr r3, [pc, #96] @ (8003494 ) 8003432: 2259 movs r2, #89 @ 0x59 8003434: f883 2030 strb.w r2, [r3, #48] @ 0x30 positionXControlTaskHandle = osThreadNew (PositionControlTask, &positionXControlTaskInitArg, &osThreadAttrPositionControlTask); 8003438: 1d3b adds r3, r7, #4 800343a: 461a mov r2, r3 800343c: 490a ldr r1, [pc, #40] @ (8003468 ) 800343e: 481e ldr r0, [pc, #120] @ (80034b8 ) 8003440: f010 fdfe bl 8014040 8003444: 4603 mov r3, r0 8003446: 4a1d ldr r2, [pc, #116] @ (80034bc ) 8003448: 6013 str r3, [r2, #0] positionYControlTaskHandle = osThreadNew (PositionControlTask, &positionYControlTaskInitArg, &osThreadAttrPositionControlTask); 800344a: 1d3b adds r3, r7, #4 800344c: 461a mov r2, r3 800344e: 4911 ldr r1, [pc, #68] @ (8003494 ) 8003450: 4819 ldr r0, [pc, #100] @ (80034b8 ) 8003452: f010 fdf5 bl 8014040 8003456: 4603 mov r3, r0 8003458: 4a19 ldr r2, [pc, #100] @ (80034c0 ) 800345a: 6013 str r3, [r2, #0] } 800345c: bf00 nop 800345e: 3728 adds r7, #40 @ 0x28 8003460: 46bd mov sp, r7 8003462: bd80 pop {r7, pc} 8003464: 240008a8 .word 0x240008a8 8003468: 240008b4 .word 0x240008b4 800346c: 240004d4 .word 0x240004d4 8003470: 240007c0 .word 0x240007c0 8003474: 24000744 .word 0x24000744 8003478: 2400088a .word 0x2400088a 800347c: 24000888 .word 0x24000888 8003480: 24000889 .word 0x24000889 8003484: 24000890 .word 0x24000890 8003488: 24000874 .word 0x24000874 800348c: 24000880 .word 0x24000880 8003490: 240008a0 .word 0x240008a0 8003494: 240008e8 .word 0x240008e8 8003498: 24000774 .word 0x24000774 800349c: 2400088d .word 0x2400088d 80034a0: 2400088b .word 0x2400088b 80034a4: 2400088c .word 0x2400088c 80034a8: 24000894 .word 0x24000894 80034ac: 24000875 .word 0x24000875 80034b0: 24000884 .word 0x24000884 80034b4: 240008a4 .word 0x240008a4 80034b8: 080034c5 .word 0x080034c5 80034bc: 240008ac .word 0x240008ac 80034c0: 240008b0 .word 0x240008b0 080034c4 : void PositionControlTask (void* argument) { 80034c4: b5f0 push {r4, r5, r6, r7, lr} 80034c6: b097 sub sp, #92 @ 0x5c 80034c8: af06 add r7, sp, #24 80034ca: 6078 str r0, [r7, #4] const int32_t PositionControlTaskTimeOut = 100; 80034cc: 2364 movs r3, #100 @ 0x64 80034ce: 623b str r3, [r7, #32] PositionControlTaskInitArg* posCtrlTaskArg = (PositionControlTaskInitArg*)argument; 80034d0: 687b ldr r3, [r7, #4] 80034d2: 61fb str r3, [r7, #28] PositionControlTaskData posCtrlData = { 0 }; 80034d4: f04f 0300 mov.w r3, #0 80034d8: 60fb str r3, [r7, #12] uint32_t motorStatus = 0; 80034da: 2300 movs r3, #0 80034dc: 61bb str r3, [r7, #24] osStatus_t queueSatus; int32_t pwmValue = MOTOR_START_STOP_PWM_VALUE; 80034de: 233c movs r3, #60 @ 0x3c 80034e0: 63fb str r3, [r7, #60] @ 0x3c int32_t sign = 0; 80034e2: 2300 movs r3, #0 80034e4: 63bb str r3, [r7, #56] @ 0x38 MovementPhases movementPhase = idlePhase; 80034e6: 2300 movs r3, #0 80034e8: f887 3037 strb.w r3, [r7, #55] @ 0x37 float startPosition = 0; 80034ec: f04f 0300 mov.w r3, #0 80034f0: 633b str r3, [r7, #48] @ 0x30 float prevPosition = 0; 80034f2: f04f 0300 mov.w r3, #0 80034f6: 62fb str r3, [r7, #44] @ 0x2c int32_t timeLeftMS = 0; 80034f8: 2300 movs r3, #0 80034fa: 62bb str r3, [r7, #40] @ 0x28 int32_t moveCmdTimeoutCounter = 0; 80034fc: 2300 movs r3, #0 80034fe: 627b str r3, [r7, #36] @ 0x24 while (pdTRUE) { queueSatus = osMessageQueueGet (posCtrlTaskArg->positionSettingQueue, &posCtrlData, 0, pdMS_TO_TICKS (PositionControlTaskTimeOut)); 8003500: 69fb ldr r3, [r7, #28] 8003502: 6918 ldr r0, [r3, #16] 8003504: 6a3b ldr r3, [r7, #32] 8003506: f44f 727a mov.w r2, #1000 @ 0x3e8 800350a: fb02 f303 mul.w r3, r2, r3 800350e: 4aa0 ldr r2, [pc, #640] @ (8003790 ) 8003510: fba2 2303 umull r2, r3, r2, r3 8003514: 099b lsrs r3, r3, #6 8003516: f107 010c add.w r1, r7, #12 800351a: 2200 movs r2, #0 800351c: f011 f916 bl 801474c 8003520: 6178 str r0, [r7, #20] if (queueSatus == osOK) { 8003522: 697b ldr r3, [r7, #20] 8003524: 2b00 cmp r3, #0 8003526: d14a bne.n 80035be if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8003528: 4b9a ldr r3, [pc, #616] @ (8003794 ) 800352a: 681b ldr r3, [r3, #0] 800352c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003530: 4618 mov r0, r3 8003532: f010 ffb0 bl 8014496 8003536: 4603 mov r3, r0 8003538: 2b00 cmp r3, #0 800353a: d1e1 bne.n 8003500 float posDiff = posCtrlData.positionSettingValue - *posCtrlTaskArg->currentPosition; 800353c: ed97 7a03 vldr s14, [r7, #12] 8003540: 69fb ldr r3, [r7, #28] 8003542: 6a1b ldr r3, [r3, #32] 8003544: edd3 7a00 vldr s15, [r3] 8003548: ee77 7a67 vsub.f32 s15, s14, s15 800354c: edc7 7a04 vstr s15, [r7, #16] if (posDiff != 0) { 8003550: edd7 7a04 vldr s15, [r7, #16] 8003554: eef5 7a40 vcmp.f32 s15, #0.0 8003558: eef1 fa10 vmrs APSR_nzcv, fpscr 800355c: d016 beq.n 800358c sign = posDiff > 0 ? 1 : -1; 800355e: edd7 7a04 vldr s15, [r7, #16] 8003562: eef5 7ac0 vcmpe.f32 s15, #0.0 8003566: eef1 fa10 vmrs APSR_nzcv, fpscr 800356a: dd01 ble.n 8003570 800356c: 2301 movs r3, #1 800356e: e001 b.n 8003574 8003570: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8003574: 63bb str r3, [r7, #56] @ 0x38 startPosition = *posCtrlTaskArg->currentPosition; 8003576: 69fb ldr r3, [r7, #28] 8003578: 6a1b ldr r3, [r3, #32] 800357a: 681b ldr r3, [r3, #0] 800357c: 633b str r3, [r7, #48] @ 0x30 movementPhase = startPhase; 800357e: 2301 movs r3, #1 8003580: f887 3037 strb.w r3, [r7, #55] @ 0x37 moveCmdTimeoutCounter = 0; 8003584: 2300 movs r3, #0 8003586: 627b str r3, [r7, #36] @ 0x24 timeLeftMS = 0; 8003588: 2300 movs r3, #0 800358a: 62bb str r3, [r7, #40] @ 0x28 #ifdef DBG_POSITION printf ("Axe %c start phase\n", posCtrlTaskArg->axe); #endif } osMutexRelease (sensorsInfoMutex); 800358c: 4b81 ldr r3, [pc, #516] @ (8003794 ) 800358e: 681b ldr r3, [r3, #0] 8003590: 4618 mov r0, r3 8003592: f010 ffcb bl 801452c if (osMutexAcquire (positionSettingMutex, osWaitForever) == osOK) { 8003596: 4b80 ldr r3, [pc, #512] @ (8003798 ) 8003598: 681b ldr r3, [r3, #0] 800359a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800359e: 4618 mov r0, r3 80035a0: f010 ff79 bl 8014496 80035a4: 4603 mov r3, r0 80035a6: 2b00 cmp r3, #0 80035a8: d1aa bne.n 8003500 *positionXControlTaskInitArg.positionSetting = posCtrlData.positionSettingValue; 80035aa: 4b7c ldr r3, [pc, #496] @ (800379c ) 80035ac: 6a5b ldr r3, [r3, #36] @ 0x24 80035ae: 68fa ldr r2, [r7, #12] 80035b0: 601a str r2, [r3, #0] osMutexRelease (positionSettingMutex); 80035b2: 4b79 ldr r3, [pc, #484] @ (8003798 ) 80035b4: 681b ldr r3, [r3, #0] 80035b6: 4618 mov r0, r3 80035b8: f010 ffb8 bl 801452c 80035bc: e7a0 b.n 8003500 } } } else if (queueSatus == osErrorTimeout) { 80035be: 697b ldr r3, [r7, #20] 80035c0: f113 0f02 cmn.w r3, #2 80035c4: d19c bne.n 8003500 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80035c6: 4b73 ldr r3, [pc, #460] @ (8003794 ) 80035c8: 681b ldr r3, [r3, #0] 80035ca: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80035ce: 4618 mov r0, r3 80035d0: f010 ff61 bl 8014496 80035d4: 4603 mov r3, r0 80035d6: 2b00 cmp r3, #0 80035d8: d192 bne.n 8003500 if ((*posCtrlTaskArg->motorStatus != 0) || (movementPhase == startPhase)) { 80035da: 69fb ldr r3, [r7, #28] 80035dc: 6a9b ldr r3, [r3, #40] @ 0x28 80035de: 781b ldrb r3, [r3, #0] 80035e0: 2b00 cmp r3, #0 80035e2: d104 bne.n 80035ee 80035e4: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 80035e8: 2b01 cmp r3, #1 80035ea: f040 81b5 bne.w 8003958 if (((*posCtrlTaskArg->switchLimiterDownStat == 1) && (*posCtrlTaskArg->switchLimiterUpStat == 1)) || 80035ee: 69fb ldr r3, [r7, #28] 80035f0: 699b ldr r3, [r3, #24] 80035f2: 781b ldrb r3, [r3, #0] 80035f4: 2b01 cmp r3, #1 80035f6: d104 bne.n 8003602 80035f8: 69fb ldr r3, [r7, #28] 80035fa: 695b ldr r3, [r3, #20] 80035fc: 781b ldrb r3, [r3, #0] 80035fe: 2b01 cmp r3, #1 8003600: d009 beq.n 8003616 ((*posCtrlTaskArg->switchLimiterUpStat == 1) && (*posCtrlTaskArg->switchLimiterCenterStat == 1))) { 8003602: 69fb ldr r3, [r7, #28] 8003604: 695b ldr r3, [r3, #20] 8003606: 781b ldrb r3, [r3, #0] if (((*posCtrlTaskArg->switchLimiterDownStat == 1) && (*posCtrlTaskArg->switchLimiterUpStat == 1)) || 8003608: 2b01 cmp r3, #1 800360a: d12a bne.n 8003662 ((*posCtrlTaskArg->switchLimiterUpStat == 1) && (*posCtrlTaskArg->switchLimiterCenterStat == 1))) { 800360c: 69fb ldr r3, [r7, #28] 800360e: 69db ldr r3, [r3, #28] 8003610: 781b ldrb r3, [r3, #0] 8003612: 2b01 cmp r3, #1 8003614: d125 bne.n 8003662 movementPhase = idlePhase; 8003616: 2300 movs r3, #0 8003618: f887 3037 strb.w r3, [r7, #55] @ 0x37 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 800361c: 69fb ldr r3, [r7, #28] 800361e: 6818 ldr r0, [r3, #0] 8003620: 69fb ldr r3, [r7, #28] 8003622: 685c ldr r4, [r3, #4] 8003624: 69fb ldr r3, [r7, #28] 8003626: 7a1d ldrb r5, [r3, #8] 8003628: 69fb ldr r3, [r7, #28] 800362a: 7a5e ldrb r6, [r3, #9] 800362c: 69fb ldr r3, [r7, #28] 800362e: 68db ldr r3, [r3, #12] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003630: 69fa ldr r2, [r7, #28] 8003632: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 8003634: 7812 ldrb r2, [r2, #0] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003636: 69f9 ldr r1, [r7, #28] 8003638: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 800363a: 7809 ldrb r1, [r1, #0] 800363c: 9104 str r1, [sp, #16] 800363e: 9203 str r2, [sp, #12] 8003640: 2200 movs r2, #0 8003642: 9202 str r2, [sp, #8] 8003644: 2200 movs r2, #0 8003646: 9201 str r2, [sp, #4] 8003648: 9300 str r3, [sp, #0] 800364a: 4633 mov r3, r6 800364c: 462a mov r2, r5 800364e: 4621 mov r1, r4 8003650: f7ff fcd6 bl 8003000 8003654: 4603 mov r3, r0 8003656: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 8003658: 69fb ldr r3, [r7, #28] 800365a: 6a9b ldr r3, [r3, #40] @ 0x28 800365c: 69ba ldr r2, [r7, #24] 800365e: b2d2 uxtb r2, r2 8003660: 701a strb r2, [r3, #0] printf ("Axe %c limiters wrong state - idle phase\n", posCtrlTaskArg->axe); #endif } timeLeftMS += PositionControlTaskTimeOut; 8003662: 6aba ldr r2, [r7, #40] @ 0x28 8003664: 6a3b ldr r3, [r7, #32] 8003666: 4413 add r3, r2 8003668: 62bb str r3, [r7, #40] @ 0x28 if (prevPosition == *posCtrlTaskArg->currentPosition) { 800366a: 69fb ldr r3, [r7, #28] 800366c: 6a1b ldr r3, [r3, #32] 800366e: edd3 7a00 vldr s15, [r3] 8003672: ed97 7a0b vldr s14, [r7, #44] @ 0x2c 8003676: eeb4 7a67 vcmp.f32 s14, s15 800367a: eef1 fa10 vmrs APSR_nzcv, fpscr 800367e: d104 bne.n 800368a moveCmdTimeoutCounter += PositionControlTaskTimeOut; 8003680: 6a7a ldr r2, [r7, #36] @ 0x24 8003682: 6a3b ldr r3, [r7, #32] 8003684: 4413 add r3, r2 8003686: 627b str r3, [r7, #36] @ 0x24 8003688: e001 b.n 800368e } else { moveCmdTimeoutCounter = 0; 800368a: 2300 movs r3, #0 800368c: 627b str r3, [r7, #36] @ 0x24 } prevPosition = *posCtrlTaskArg->currentPosition; 800368e: 69fb ldr r3, [r7, #28] 8003690: 6a1b ldr r3, [r3, #32] 8003692: 681b ldr r3, [r3, #0] 8003694: 62fb str r3, [r7, #44] @ 0x2c if (moveCmdTimeoutCounter > NO_MOVE_TIMEOUT_MS) { 8003696: 6a7b ldr r3, [r7, #36] @ 0x24 8003698: f242 7210 movw r2, #10000 @ 0x2710 800369c: 4293 cmp r3, r2 800369e: dd25 ble.n 80036ec movementPhase = idlePhase; 80036a0: 2300 movs r3, #0 80036a2: f887 3037 strb.w r3, [r7, #55] @ 0x37 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 80036a6: 69fb ldr r3, [r7, #28] 80036a8: 6818 ldr r0, [r3, #0] 80036aa: 69fb ldr r3, [r7, #28] 80036ac: 685c ldr r4, [r3, #4] 80036ae: 69fb ldr r3, [r7, #28] 80036b0: 7a1d ldrb r5, [r3, #8] 80036b2: 69fb ldr r3, [r7, #28] 80036b4: 7a5e ldrb r6, [r3, #9] 80036b6: 69fb ldr r3, [r7, #28] 80036b8: 68db ldr r3, [r3, #12] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80036ba: 69fa ldr r2, [r7, #28] 80036bc: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 80036be: 7812 ldrb r2, [r2, #0] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80036c0: 69f9 ldr r1, [r7, #28] 80036c2: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 80036c4: 7809 ldrb r1, [r1, #0] 80036c6: 9104 str r1, [sp, #16] 80036c8: 9203 str r2, [sp, #12] 80036ca: 2200 movs r2, #0 80036cc: 9202 str r2, [sp, #8] 80036ce: 2200 movs r2, #0 80036d0: 9201 str r2, [sp, #4] 80036d2: 9300 str r3, [sp, #0] 80036d4: 4633 mov r3, r6 80036d6: 462a mov r2, r5 80036d8: 4621 mov r1, r4 80036da: f7ff fc91 bl 8003000 80036de: 4603 mov r3, r0 80036e0: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 80036e2: 69fb ldr r3, [r7, #28] 80036e4: 6a9b ldr r3, [r3, #40] @ 0x28 80036e6: 69ba ldr r2, [r7, #24] 80036e8: b2d2 uxtb r2, r2 80036ea: 701a strb r2, [r3, #0] #ifdef DBG_POSITION printf ("Axe %c no movement idle phase\n", posCtrlTaskArg->axe); #endif } switch (movementPhase) { 80036ec: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 80036f0: 3b01 subs r3, #1 80036f2: 2b04 cmp r3, #4 80036f4: f200 8128 bhi.w 8003948 80036f8: a201 add r2, pc, #4 @ (adr r2, 8003700 ) 80036fa: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80036fe: bf00 nop 8003700: 08003715 .word 0x08003715 8003704: 080037a1 .word 0x080037a1 8003708: 0800382b .word 0x0800382b 800370c: 08003877 .word 0x08003877 8003710: 080038d9 .word 0x080038d9 case startPhase: motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003714: 69fb ldr r3, [r7, #28] 8003716: 681c ldr r4, [r3, #0] 8003718: 69fb ldr r3, [r7, #28] 800371a: 685d ldr r5, [r3, #4] 800371c: 69fb ldr r3, [r7, #28] 800371e: 7a1e ldrb r6, [r3, #8] 8003720: 69fb ldr r3, [r7, #28] 8003722: f893 c009 ldrb.w ip, [r3, #9] 8003726: 69fb ldr r3, [r7, #28] 8003728: 68db ldr r3, [r3, #12] 800372a: 6bba ldr r2, [r7, #56] @ 0x38 800372c: 6bf9 ldr r1, [r7, #60] @ 0x3c 800372e: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003732: 69f9 ldr r1, [r7, #28] 8003734: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003736: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003738: 69f8 ldr r0, [r7, #28] 800373a: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 800373c: 7800 ldrb r0, [r0, #0] 800373e: 9004 str r0, [sp, #16] 8003740: 9103 str r1, [sp, #12] 8003742: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003746: 9102 str r1, [sp, #8] 8003748: 9201 str r2, [sp, #4] 800374a: 9300 str r3, [sp, #0] 800374c: 4663 mov r3, ip 800374e: 4632 mov r2, r6 8003750: 4629 mov r1, r5 8003752: 4620 mov r0, r4 8003754: f7ff fc54 bl 8003000 8003758: 4603 mov r3, r0 800375a: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 800375c: 69fb ldr r3, [r7, #28] 800375e: 6a9b ldr r3, [r3, #40] @ 0x28 8003760: 69ba ldr r2, [r7, #24] 8003762: b2d2 uxtb r2, r2 8003764: 701a strb r2, [r3, #0] if (motorStatus == 1) { 8003766: 69bb ldr r3, [r7, #24] 8003768: 2b01 cmp r3, #1 800376a: d10c bne.n 8003786 *posCtrlTaskArg->motorPeakCurrent = 0.0; 800376c: 69fb ldr r3, [r7, #28] 800376e: 6adb ldr r3, [r3, #44] @ 0x2c 8003770: f04f 0200 mov.w r2, #0 8003774: 601a str r2, [r3, #0] #ifdef DBG_POSITION printf ("Axe %c speed up phase\n", posCtrlTaskArg->axe); #endif movementPhase = speedUpPhase; 8003776: 2302 movs r3, #2 8003778: f887 3037 strb.w r3, [r7, #55] @ 0x37 timeLeftMS = 0; 800377c: 2300 movs r3, #0 800377e: 62bb str r3, [r7, #40] @ 0x28 moveCmdTimeoutCounter = 0; 8003780: 2300 movs r3, #0 8003782: 627b str r3, [r7, #36] @ 0x24 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); #endif } break; 8003784: e0e7 b.n 8003956 movementPhase = idlePhase; 8003786: 2300 movs r3, #0 8003788: f887 3037 strb.w r3, [r7, #55] @ 0x37 break; 800378c: e0e3 b.n 8003956 800378e: bf00 nop 8003790: 10624dd3 .word 0x10624dd3 8003794: 2400081c .word 0x2400081c 8003798: 240008a8 .word 0x240008a8 800379c: 240008b4 .word 0x240008b4 case speedUpPhase: if ((abs (*posCtrlTaskArg->currentPosition - startPosition) >= ANGLE_RANGE_FOR_MOTOR_SPEED_LIMIT) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) { 80037a0: 69fb ldr r3, [r7, #28] 80037a2: 6a1b ldr r3, [r3, #32] 80037a4: ed93 7a00 vldr s14, [r3] 80037a8: edd7 7a0c vldr s15, [r7, #48] @ 0x30 80037ac: ee77 7a67 vsub.f32 s15, s14, s15 80037b0: eefd 7ae7 vcvt.s32.f32 s15, s15 80037b4: ee17 3a90 vmov r3, s15 80037b8: 2b00 cmp r3, #0 80037ba: bfb8 it lt 80037bc: 425b neglt r3, r3 80037be: 2b04 cmp r3, #4 80037c0: dc04 bgt.n 80037cc 80037c2: 6abb ldr r3, [r7, #40] @ 0x28 80037c4: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 80037c8: f2c0 80c0 blt.w 800394c pwmValue = MOTOR_HIGH_SPEED_PWM_VALUE; 80037cc: 2364 movs r3, #100 @ 0x64 80037ce: 63fb str r3, [r7, #60] @ 0x3c motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80037d0: 69fb ldr r3, [r7, #28] 80037d2: 681c ldr r4, [r3, #0] 80037d4: 69fb ldr r3, [r7, #28] 80037d6: 685d ldr r5, [r3, #4] 80037d8: 69fb ldr r3, [r7, #28] 80037da: 7a1e ldrb r6, [r3, #8] 80037dc: 69fb ldr r3, [r7, #28] 80037de: f893 c009 ldrb.w ip, [r3, #9] 80037e2: 69fb ldr r3, [r7, #28] 80037e4: 68db ldr r3, [r3, #12] 80037e6: 6bba ldr r2, [r7, #56] @ 0x38 80037e8: 6bf9 ldr r1, [r7, #60] @ 0x3c 80037ea: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80037ee: 69f9 ldr r1, [r7, #28] 80037f0: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80037f2: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80037f4: 69f8 ldr r0, [r7, #28] 80037f6: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80037f8: 7800 ldrb r0, [r0, #0] 80037fa: 9004 str r0, [sp, #16] 80037fc: 9103 str r1, [sp, #12] 80037fe: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003802: 9102 str r1, [sp, #8] 8003804: 9201 str r2, [sp, #4] 8003806: 9300 str r3, [sp, #0] 8003808: 4663 mov r3, ip 800380a: 4632 mov r2, r6 800380c: 4629 mov r1, r5 800380e: 4620 mov r0, r4 8003810: f7ff fbf6 bl 8003000 8003814: 4603 mov r3, r0 8003816: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 8003818: 69fb ldr r3, [r7, #28] 800381a: 6a9b ldr r3, [r3, #40] @ 0x28 800381c: 69ba ldr r2, [r7, #24] 800381e: b2d2 uxtb r2, r2 8003820: 701a strb r2, [r3, #0] movementPhase = movePhase; 8003822: 2303 movs r3, #3 8003824: f887 3037 strb.w r3, [r7, #55] @ 0x37 #ifdef DBG_POSITION printf ("Axe %c move phase\n", posCtrlTaskArg->axe); #endif } break; 8003828: e090 b.n 800394c case movePhase: if (abs (*posCtrlTaskArg->currentPosition - *posCtrlTaskArg->positionSetting) <= ANGLE_RANGE_FOR_MOTOR_SPEED_LIMIT) { 800382a: 69fb ldr r3, [r7, #28] 800382c: 6a1b ldr r3, [r3, #32] 800382e: ed93 7a00 vldr s14, [r3] 8003832: 69fb ldr r3, [r7, #28] 8003834: 6a5b ldr r3, [r3, #36] @ 0x24 8003836: edd3 7a00 vldr s15, [r3] 800383a: ee77 7a67 vsub.f32 s15, s14, s15 800383e: eefd 7ae7 vcvt.s32.f32 s15, s15 8003842: ee17 3a90 vmov r3, s15 8003846: f113 0f05 cmn.w r3, #5 800384a: f2c0 8081 blt.w 8003950 800384e: 69fb ldr r3, [r7, #28] 8003850: 6a1b ldr r3, [r3, #32] 8003852: ed93 7a00 vldr s14, [r3] 8003856: 69fb ldr r3, [r7, #28] 8003858: 6a5b ldr r3, [r3, #36] @ 0x24 800385a: edd3 7a00 vldr s15, [r3] 800385e: ee77 7a67 vsub.f32 s15, s14, s15 8003862: eefd 7ae7 vcvt.s32.f32 s15, s15 8003866: ee17 3a90 vmov r3, s15 800386a: 2b05 cmp r3, #5 800386c: dc70 bgt.n 8003950 movementPhase = slowDownPhase; 800386e: 2304 movs r3, #4 8003870: f887 3037 strb.w r3, [r7, #55] @ 0x37 #ifdef DBG_POSITION printf ("Axe %c slow down phase\n", posCtrlTaskArg->axe); #endif } break; 8003874: e06c b.n 8003950 case slowDownPhase: pwmValue = MOTOR_START_STOP_PWM_VALUE; 8003876: 233c movs r3, #60 @ 0x3c 8003878: 63fb str r3, [r7, #60] @ 0x3c motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 800387a: 69fb ldr r3, [r7, #28] 800387c: 681c ldr r4, [r3, #0] 800387e: 69fb ldr r3, [r7, #28] 8003880: 685d ldr r5, [r3, #4] 8003882: 69fb ldr r3, [r7, #28] 8003884: 7a1e ldrb r6, [r3, #8] 8003886: 69fb ldr r3, [r7, #28] 8003888: f893 c009 ldrb.w ip, [r3, #9] 800388c: 69fb ldr r3, [r7, #28] 800388e: 68db ldr r3, [r3, #12] 8003890: 6bba ldr r2, [r7, #56] @ 0x38 8003892: 6bf9 ldr r1, [r7, #60] @ 0x3c 8003894: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003898: 69f9 ldr r1, [r7, #28] 800389a: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 800389c: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 800389e: 69f8 ldr r0, [r7, #28] 80038a0: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80038a2: 7800 ldrb r0, [r0, #0] 80038a4: 9004 str r0, [sp, #16] 80038a6: 9103 str r1, [sp, #12] 80038a8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80038ac: 9102 str r1, [sp, #8] 80038ae: 9201 str r2, [sp, #4] 80038b0: 9300 str r3, [sp, #0] 80038b2: 4663 mov r3, ip 80038b4: 4632 mov r2, r6 80038b6: 4629 mov r1, r5 80038b8: 4620 mov r0, r4 80038ba: f7ff fba1 bl 8003000 80038be: 4603 mov r3, r0 80038c0: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 80038c2: 69fb ldr r3, [r7, #28] 80038c4: 6a9b ldr r3, [r3, #40] @ 0x28 80038c6: 69ba ldr r2, [r7, #24] 80038c8: b2d2 uxtb r2, r2 80038ca: 701a strb r2, [r3, #0] movementPhase = stopPhase; 80038cc: 2305 movs r3, #5 80038ce: f887 3037 strb.w r3, [r7, #55] @ 0x37 timeLeftMS = 0; 80038d2: 2300 movs r3, #0 80038d4: 62bb str r3, [r7, #40] @ 0x28 #ifdef DBG_POSITION printf ("Axe %c stop phase\n", posCtrlTaskArg->axe); #endif break; 80038d6: e03e b.n 8003956 case stopPhase: if ((*posCtrlTaskArg->currentPosition == *posCtrlTaskArg->positionSetting) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) { 80038d8: 69fb ldr r3, [r7, #28] 80038da: 6a1b ldr r3, [r3, #32] 80038dc: ed93 7a00 vldr s14, [r3] 80038e0: 69fb ldr r3, [r7, #28] 80038e2: 6a5b ldr r3, [r3, #36] @ 0x24 80038e4: edd3 7a00 vldr s15, [r3] 80038e8: eeb4 7a67 vcmp.f32 s14, s15 80038ec: eef1 fa10 vmrs APSR_nzcv, fpscr 80038f0: d003 beq.n 80038fa 80038f2: 6abb ldr r3, [r7, #40] @ 0x28 80038f4: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 80038f8: db2c blt.n 8003954 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80038fa: 69fb ldr r3, [r7, #28] 80038fc: 6818 ldr r0, [r3, #0] 80038fe: 69fb ldr r3, [r7, #28] 8003900: 685c ldr r4, [r3, #4] 8003902: 69fb ldr r3, [r7, #28] 8003904: 7a1d ldrb r5, [r3, #8] 8003906: 69fb ldr r3, [r7, #28] 8003908: 7a5e ldrb r6, [r3, #9] 800390a: 69fb ldr r3, [r7, #28] 800390c: 68db ldr r3, [r3, #12] 0, 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 800390e: 69fa ldr r2, [r7, #28] 8003910: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003912: 7812 ldrb r2, [r2, #0] 0, 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003914: 69f9 ldr r1, [r7, #28] 8003916: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003918: 7809 ldrb r1, [r1, #0] 800391a: 9104 str r1, [sp, #16] 800391c: 9203 str r2, [sp, #12] 800391e: 2200 movs r2, #0 8003920: 9202 str r2, [sp, #8] 8003922: 2200 movs r2, #0 8003924: 9201 str r2, [sp, #4] 8003926: 9300 str r3, [sp, #0] 8003928: 4633 mov r3, r6 800392a: 462a mov r2, r5 800392c: 4621 mov r1, r4 800392e: f7ff fb67 bl 8003000 8003932: 4603 mov r3, r0 8003934: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 8003936: 69fb ldr r3, [r7, #28] 8003938: 6a9b ldr r3, [r3, #40] @ 0x28 800393a: 69ba ldr r2, [r7, #24] 800393c: b2d2 uxtb r2, r2 800393e: 701a strb r2, [r3, #0] movementPhase = idlePhase; 8003940: 2300 movs r3, #0 8003942: f887 3037 strb.w r3, [r7, #55] @ 0x37 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); #endif } break; 8003946: e005 b.n 8003954 default: break; 8003948: bf00 nop 800394a: e011 b.n 8003970 break; 800394c: bf00 nop 800394e: e00f b.n 8003970 break; 8003950: bf00 nop 8003952: e00d b.n 8003970 break; 8003954: bf00 nop switch (movementPhase) { 8003956: e00b b.n 8003970 } } else { if ((*posCtrlTaskArg->motorStatus == 0) && (movementPhase != idlePhase)) { 8003958: 69fb ldr r3, [r7, #28] 800395a: 6a9b ldr r3, [r3, #40] @ 0x28 800395c: 781b ldrb r3, [r3, #0] 800395e: 2b00 cmp r3, #0 8003960: d106 bne.n 8003970 8003962: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 8003966: 2b00 cmp r3, #0 8003968: d002 beq.n 8003970 movementPhase = idlePhase; 800396a: 2300 movs r3, #0 800396c: f887 3037 strb.w r3, [r7, #55] @ 0x37 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); #endif } } osMutexRelease (sensorsInfoMutex); 8003970: 4b02 ldr r3, [pc, #8] @ (800397c ) 8003972: 681b ldr r3, [r3, #0] 8003974: 4618 mov r0, r3 8003976: f010 fdd9 bl 801452c queueSatus = osMessageQueueGet (posCtrlTaskArg->positionSettingQueue, &posCtrlData, 0, pdMS_TO_TICKS (PositionControlTaskTimeOut)); 800397a: e5c1 b.n 8003500 800397c: 2400081c .word 0x2400081c 08003980 : buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); } *buffPos = newBuffPos; } void WriteDataToBuffer (uint8_t* buff, uint16_t* buffPos, void* data, uint8_t dataSize) { 8003980: b480 push {r7} 8003982: b089 sub sp, #36 @ 0x24 8003984: af00 add r7, sp, #0 8003986: 60f8 str r0, [r7, #12] 8003988: 60b9 str r1, [r7, #8] 800398a: 607a str r2, [r7, #4] 800398c: 70fb strb r3, [r7, #3] uint32_t* uDataPtr = data; 800398e: 687b ldr r3, [r7, #4] 8003990: 61bb str r3, [r7, #24] uint32_t uData = *uDataPtr; 8003992: 69bb ldr r3, [r7, #24] 8003994: 681b ldr r3, [r3, #0] 8003996: 617b str r3, [r7, #20] uint8_t i = 0; 8003998: 2300 movs r3, #0 800399a: 77fb strb r3, [r7, #31] uint8_t newBuffPos = *buffPos; 800399c: 68bb ldr r3, [r7, #8] 800399e: 881b ldrh r3, [r3, #0] 80039a0: 77bb strb r3, [r7, #30] for (i = 0; i < dataSize; i++) { 80039a2: 2300 movs r3, #0 80039a4: 77fb strb r3, [r7, #31] 80039a6: e00e b.n 80039c6 buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); 80039a8: 7ffb ldrb r3, [r7, #31] 80039aa: 00db lsls r3, r3, #3 80039ac: 697a ldr r2, [r7, #20] 80039ae: 40da lsrs r2, r3 80039b0: 7fbb ldrb r3, [r7, #30] 80039b2: 1c59 adds r1, r3, #1 80039b4: 77b9 strb r1, [r7, #30] 80039b6: 4619 mov r1, r3 80039b8: 68fb ldr r3, [r7, #12] 80039ba: 440b add r3, r1 80039bc: b2d2 uxtb r2, r2 80039be: 701a strb r2, [r3, #0] for (i = 0; i < dataSize; i++) { 80039c0: 7ffb ldrb r3, [r7, #31] 80039c2: 3301 adds r3, #1 80039c4: 77fb strb r3, [r7, #31] 80039c6: 7ffa ldrb r2, [r7, #31] 80039c8: 78fb ldrb r3, [r7, #3] 80039ca: 429a cmp r2, r3 80039cc: d3ec bcc.n 80039a8 } *buffPos = newBuffPos; 80039ce: 7fbb ldrb r3, [r7, #30] 80039d0: b29a uxth r2, r3 80039d2: 68bb ldr r3, [r7, #8] 80039d4: 801a strh r2, [r3, #0] } 80039d6: bf00 nop 80039d8: 3724 adds r7, #36 @ 0x24 80039da: 46bd mov sp, r7 80039dc: f85d 7b04 ldr.w r7, [sp], #4 80039e0: 4770 bx lr 080039e2 : void ReadFloatFromBuffer(uint8_t* buff, uint16_t* buffPos, float* data) { 80039e2: b480 push {r7} 80039e4: b087 sub sp, #28 80039e6: af00 add r7, sp, #0 80039e8: 60f8 str r0, [r7, #12] 80039ea: 60b9 str r1, [r7, #8] 80039ec: 607a str r2, [r7, #4] uint32_t* word = (uint32_t *)data; 80039ee: 687b ldr r3, [r7, #4] 80039f0: 617b str r3, [r7, #20] *word = CONVERT_BYTES_TO_WORD(&buff[*buffPos]); 80039f2: 68bb ldr r3, [r7, #8] 80039f4: 881b ldrh r3, [r3, #0] 80039f6: 3303 adds r3, #3 80039f8: 68fa ldr r2, [r7, #12] 80039fa: 4413 add r3, r2 80039fc: 781b ldrb r3, [r3, #0] 80039fe: 061a lsls r2, r3, #24 8003a00: 68bb ldr r3, [r7, #8] 8003a02: 881b ldrh r3, [r3, #0] 8003a04: 3302 adds r3, #2 8003a06: 68f9 ldr r1, [r7, #12] 8003a08: 440b add r3, r1 8003a0a: 781b ldrb r3, [r3, #0] 8003a0c: 041b lsls r3, r3, #16 8003a0e: 431a orrs r2, r3 8003a10: 68bb ldr r3, [r7, #8] 8003a12: 881b ldrh r3, [r3, #0] 8003a14: 3301 adds r3, #1 8003a16: 68f9 ldr r1, [r7, #12] 8003a18: 440b add r3, r1 8003a1a: 781b ldrb r3, [r3, #0] 8003a1c: 021b lsls r3, r3, #8 8003a1e: 4313 orrs r3, r2 8003a20: 68ba ldr r2, [r7, #8] 8003a22: 8812 ldrh r2, [r2, #0] 8003a24: 4611 mov r1, r2 8003a26: 68fa ldr r2, [r7, #12] 8003a28: 440a add r2, r1 8003a2a: 7812 ldrb r2, [r2, #0] 8003a2c: 4313 orrs r3, r2 8003a2e: 461a mov r2, r3 8003a30: 697b ldr r3, [r7, #20] 8003a32: 601a str r2, [r3, #0] *buffPos += sizeof(float); 8003a34: 68bb ldr r3, [r7, #8] 8003a36: 881b ldrh r3, [r3, #0] 8003a38: 3304 adds r3, #4 8003a3a: b29a uxth r2, r3 8003a3c: 68bb ldr r3, [r7, #8] 8003a3e: 801a strh r2, [r3, #0] } 8003a40: bf00 nop 8003a42: 371c adds r7, #28 8003a44: 46bd mov sp, r7 8003a46: f85d 7b04 ldr.w r7, [sp], #4 8003a4a: 4770 bx lr 08003a4c : *data = CONVERT_BYTES_TO_SHORT_WORD(&buff[*buffPos]); *buffPos += sizeof(uint16_t); } void ReadWordFromBufer(uint8_t* buff, uint16_t* buffPos, uint32_t* data) { 8003a4c: b480 push {r7} 8003a4e: b085 sub sp, #20 8003a50: af00 add r7, sp, #0 8003a52: 60f8 str r0, [r7, #12] 8003a54: 60b9 str r1, [r7, #8] 8003a56: 607a str r2, [r7, #4] *data = CONVERT_BYTES_TO_WORD(&buff[*buffPos]); 8003a58: 68bb ldr r3, [r7, #8] 8003a5a: 881b ldrh r3, [r3, #0] 8003a5c: 3303 adds r3, #3 8003a5e: 68fa ldr r2, [r7, #12] 8003a60: 4413 add r3, r2 8003a62: 781b ldrb r3, [r3, #0] 8003a64: 061a lsls r2, r3, #24 8003a66: 68bb ldr r3, [r7, #8] 8003a68: 881b ldrh r3, [r3, #0] 8003a6a: 3302 adds r3, #2 8003a6c: 68f9 ldr r1, [r7, #12] 8003a6e: 440b add r3, r1 8003a70: 781b ldrb r3, [r3, #0] 8003a72: 041b lsls r3, r3, #16 8003a74: 431a orrs r2, r3 8003a76: 68bb ldr r3, [r7, #8] 8003a78: 881b ldrh r3, [r3, #0] 8003a7a: 3301 adds r3, #1 8003a7c: 68f9 ldr r1, [r7, #12] 8003a7e: 440b add r3, r1 8003a80: 781b ldrb r3, [r3, #0] 8003a82: 021b lsls r3, r3, #8 8003a84: 4313 orrs r3, r2 8003a86: 68ba ldr r2, [r7, #8] 8003a88: 8812 ldrh r2, [r2, #0] 8003a8a: 4611 mov r1, r2 8003a8c: 68fa ldr r2, [r7, #12] 8003a8e: 440a add r2, r1 8003a90: 7812 ldrb r2, [r2, #0] 8003a92: 4313 orrs r3, r2 8003a94: 461a mov r2, r3 8003a96: 687b ldr r3, [r7, #4] 8003a98: 601a str r2, [r3, #0] *buffPos += sizeof(uint32_t); 8003a9a: 68bb ldr r3, [r7, #8] 8003a9c: 881b ldrh r3, [r3, #0] 8003a9e: 3304 adds r3, #4 8003aa0: b29a uxth r2, r3 8003aa2: 68bb ldr r3, [r7, #8] 8003aa4: 801a strh r2, [r3, #0] } 8003aa6: bf00 nop 8003aa8: 3714 adds r7, #20 8003aaa: 46bd mov sp, r7 8003aac: f85d 7b04 ldr.w r7, [sp], #4 8003ab0: 4770 bx lr ... 08003ab4 : txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); return txBufferPos; } uint16_t PrepareRespFrame (uint8_t* txBuffer, uint16_t frameId, SerialProtocolCommands frameCommand, SerialProtocolRespStatus respStatus, uint8_t* dataBuffer, uint16_t dataLength) { 8003ab4: b580 push {r7, lr} 8003ab6: b084 sub sp, #16 8003ab8: af00 add r7, sp, #0 8003aba: 6078 str r0, [r7, #4] 8003abc: 4608 mov r0, r1 8003abe: 4611 mov r1, r2 8003ac0: 461a mov r2, r3 8003ac2: 4603 mov r3, r0 8003ac4: 807b strh r3, [r7, #2] 8003ac6: 460b mov r3, r1 8003ac8: 707b strb r3, [r7, #1] 8003aca: 4613 mov r3, r2 8003acc: 703b strb r3, [r7, #0] uint16_t crc = 0; 8003ace: 2300 movs r3, #0 8003ad0: 81bb strh r3, [r7, #12] uint16_t txBufferPos = 0; 8003ad2: 2300 movs r3, #0 8003ad4: 81fb strh r3, [r7, #14] uint16_t frameCmd = ((uint16_t)frameCommand) | 0x8000; // MSB set means response 8003ad6: 787b ldrb r3, [r7, #1] 8003ad8: b21a sxth r2, r3 8003ada: 4b43 ldr r3, [pc, #268] @ (8003be8 ) 8003adc: 4313 orrs r3, r2 8003ade: b21b sxth r3, r3 8003ae0: 817b strh r3, [r7, #10] memset (txBuffer, 0x00, dataLength); 8003ae2: 8bbb ldrh r3, [r7, #28] 8003ae4: 461a mov r2, r3 8003ae6: 2100 movs r1, #0 8003ae8: 6878 ldr r0, [r7, #4] 8003aea: f014 fbfd bl 80182e8 txBuffer[txBufferPos++] = FRAME_INDICATOR; 8003aee: 89fb ldrh r3, [r7, #14] 8003af0: 1c5a adds r2, r3, #1 8003af2: 81fa strh r2, [r7, #14] 8003af4: 461a mov r2, r3 8003af6: 687b ldr r3, [r7, #4] 8003af8: 4413 add r3, r2 8003afa: 22aa movs r2, #170 @ 0xaa 8003afc: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameId); 8003afe: 89fb ldrh r3, [r7, #14] 8003b00: 1c5a adds r2, r3, #1 8003b02: 81fa strh r2, [r7, #14] 8003b04: 461a mov r2, r3 8003b06: 687b ldr r3, [r7, #4] 8003b08: 4413 add r3, r2 8003b0a: 887a ldrh r2, [r7, #2] 8003b0c: b2d2 uxtb r2, r2 8003b0e: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameId); 8003b10: 887b ldrh r3, [r7, #2] 8003b12: 0a1b lsrs r3, r3, #8 8003b14: b29a uxth r2, r3 8003b16: 89fb ldrh r3, [r7, #14] 8003b18: 1c59 adds r1, r3, #1 8003b1a: 81f9 strh r1, [r7, #14] 8003b1c: 4619 mov r1, r3 8003b1e: 687b ldr r3, [r7, #4] 8003b20: 440b add r3, r1 8003b22: b2d2 uxtb r2, r2 8003b24: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameCmd); 8003b26: 89fb ldrh r3, [r7, #14] 8003b28: 1c5a adds r2, r3, #1 8003b2a: 81fa strh r2, [r7, #14] 8003b2c: 461a mov r2, r3 8003b2e: 687b ldr r3, [r7, #4] 8003b30: 4413 add r3, r2 8003b32: 897a ldrh r2, [r7, #10] 8003b34: b2d2 uxtb r2, r2 8003b36: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameCmd); 8003b38: 897b ldrh r3, [r7, #10] 8003b3a: 0a1b lsrs r3, r3, #8 8003b3c: b29a uxth r2, r3 8003b3e: 89fb ldrh r3, [r7, #14] 8003b40: 1c59 adds r1, r3, #1 8003b42: 81f9 strh r1, [r7, #14] 8003b44: 4619 mov r1, r3 8003b46: 687b ldr r3, [r7, #4] 8003b48: 440b add r3, r1 8003b4a: b2d2 uxtb r2, r2 8003b4c: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (dataLength); 8003b4e: 89fb ldrh r3, [r7, #14] 8003b50: 1c5a adds r2, r3, #1 8003b52: 81fa strh r2, [r7, #14] 8003b54: 461a mov r2, r3 8003b56: 687b ldr r3, [r7, #4] 8003b58: 4413 add r3, r2 8003b5a: 8bba ldrh r2, [r7, #28] 8003b5c: b2d2 uxtb r2, r2 8003b5e: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (dataLength); 8003b60: 8bbb ldrh r3, [r7, #28] 8003b62: 0a1b lsrs r3, r3, #8 8003b64: b29a uxth r2, r3 8003b66: 89fb ldrh r3, [r7, #14] 8003b68: 1c59 adds r1, r3, #1 8003b6a: 81f9 strh r1, [r7, #14] 8003b6c: 4619 mov r1, r3 8003b6e: 687b ldr r3, [r7, #4] 8003b70: 440b add r3, r1 8003b72: b2d2 uxtb r2, r2 8003b74: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = (uint8_t)respStatus; 8003b76: 89fb ldrh r3, [r7, #14] 8003b78: 1c5a adds r2, r3, #1 8003b7a: 81fa strh r2, [r7, #14] 8003b7c: 461a mov r2, r3 8003b7e: 687b ldr r3, [r7, #4] 8003b80: 4413 add r3, r2 8003b82: 783a ldrb r2, [r7, #0] 8003b84: 701a strb r2, [r3, #0] if (dataLength > 0) { 8003b86: 8bbb ldrh r3, [r7, #28] 8003b88: 2b00 cmp r3, #0 8003b8a: d00b beq.n 8003ba4 memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength); 8003b8c: 89fb ldrh r3, [r7, #14] 8003b8e: 687a ldr r2, [r7, #4] 8003b90: 4413 add r3, r2 8003b92: 8bba ldrh r2, [r7, #28] 8003b94: 69b9 ldr r1, [r7, #24] 8003b96: 4618 mov r0, r3 8003b98: f014 fc30 bl 80183fc txBufferPos += dataLength; 8003b9c: 89fa ldrh r2, [r7, #14] 8003b9e: 8bbb ldrh r3, [r7, #28] 8003ba0: 4413 add r3, r2 8003ba2: 81fb strh r3, [r7, #14] } crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)txBuffer, txBufferPos); 8003ba4: 89fb ldrh r3, [r7, #14] 8003ba6: 461a mov r2, r3 8003ba8: 6879 ldr r1, [r7, #4] 8003baa: 4810 ldr r0, [pc, #64] @ (8003bec ) 8003bac: f004 f8d0 bl 8007d50 8003bb0: 4603 mov r3, r0 8003bb2: 81bb strh r3, [r7, #12] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (crc); 8003bb4: 89fb ldrh r3, [r7, #14] 8003bb6: 1c5a adds r2, r3, #1 8003bb8: 81fa strh r2, [r7, #14] 8003bba: 461a mov r2, r3 8003bbc: 687b ldr r3, [r7, #4] 8003bbe: 4413 add r3, r2 8003bc0: 89ba ldrh r2, [r7, #12] 8003bc2: b2d2 uxtb r2, r2 8003bc4: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); 8003bc6: 89bb ldrh r3, [r7, #12] 8003bc8: 0a1b lsrs r3, r3, #8 8003bca: b29a uxth r2, r3 8003bcc: 89fb ldrh r3, [r7, #14] 8003bce: 1c59 adds r1, r3, #1 8003bd0: 81f9 strh r1, [r7, #14] 8003bd2: 4619 mov r1, r3 8003bd4: 687b ldr r3, [r7, #4] 8003bd6: 440b add r3, r1 8003bd8: b2d2 uxtb r2, r2 8003bda: 701a strb r2, [r3, #0] return txBufferPos; 8003bdc: 89fb ldrh r3, [r7, #14] } 8003bde: 4618 mov r0, r3 8003be0: 3710 adds r7, #16 8003be2: 46bd mov sp, r7 8003be4: bd80 pop {r7, pc} 8003be6: bf00 nop 8003be8: ffff8000 .word 0xffff8000 8003bec: 240003e0 .word 0x240003e0 08003bf0 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8003bf0: b580 push {r7, lr} 8003bf2: b086 sub sp, #24 8003bf4: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ PWREx_AVDTypeDef sConfigAVD = {0}; 8003bf6: f107 0310 add.w r3, r7, #16 8003bfa: 2200 movs r2, #0 8003bfc: 601a str r2, [r3, #0] 8003bfe: 605a str r2, [r3, #4] PWR_PVDTypeDef sConfigPVD = {0}; 8003c00: f107 0308 add.w r3, r7, #8 8003c04: 2200 movs r2, #0 8003c06: 601a str r2, [r3, #0] 8003c08: 605a str r2, [r3, #4] __HAL_RCC_SYSCFG_CLK_ENABLE(); 8003c0a: 4b26 ldr r3, [pc, #152] @ (8003ca4 ) 8003c0c: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003c10: 4a24 ldr r2, [pc, #144] @ (8003ca4 ) 8003c12: f043 0302 orr.w r3, r3, #2 8003c16: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8003c1a: 4b22 ldr r3, [pc, #136] @ (8003ca4 ) 8003c1c: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003c20: f003 0302 and.w r3, r3, #2 8003c24: 607b str r3, [r7, #4] 8003c26: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 8003c28: 2200 movs r2, #0 8003c2a: 210f movs r1, #15 8003c2c: f06f 0001 mvn.w r0, #1 8003c30: f003 ff8a bl 8007b48 /* Peripheral interrupt init */ /* RCC_IRQn interrupt configuration */ HAL_NVIC_SetPriority(RCC_IRQn, 5, 0); 8003c34: 2200 movs r2, #0 8003c36: 2105 movs r1, #5 8003c38: 2005 movs r0, #5 8003c3a: f003 ff85 bl 8007b48 HAL_NVIC_EnableIRQ(RCC_IRQn); 8003c3e: 2005 movs r0, #5 8003c40: f003 ff9c bl 8007b7c /** AVD Configuration */ sConfigAVD.AVDLevel = PWR_AVDLEVEL_3; 8003c44: f44f 23c0 mov.w r3, #393216 @ 0x60000 8003c48: 613b str r3, [r7, #16] sConfigAVD.Mode = PWR_AVD_MODE_NORMAL; 8003c4a: 2300 movs r3, #0 8003c4c: 617b str r3, [r7, #20] HAL_PWREx_ConfigAVD(&sConfigAVD); 8003c4e: f107 0310 add.w r3, r7, #16 8003c52: 4618 mov r0, r3 8003c54: f007 fde2 bl 800b81c /** Enable the AVD Output */ HAL_PWREx_EnableAVD(); 8003c58: f007 fe56 bl 800b908 /** PVD Configuration */ sConfigPVD.PVDLevel = PWR_PVDLEVEL_6; 8003c5c: 23c0 movs r3, #192 @ 0xc0 8003c5e: 60bb str r3, [r7, #8] sConfigPVD.Mode = PWR_PVD_MODE_NORMAL; 8003c60: 2300 movs r3, #0 8003c62: 60fb str r3, [r7, #12] HAL_PWR_ConfigPVD(&sConfigPVD); 8003c64: f107 0308 add.w r3, r7, #8 8003c68: 4618 mov r0, r3 8003c6a: f007 fd13 bl 800b694 /** Enable the PVD Output */ HAL_PWR_EnablePVD(); 8003c6e: f007 fd8b bl 800b788 /** Enable the VREF clock */ __HAL_RCC_VREF_CLK_ENABLE(); 8003c72: 4b0c ldr r3, [pc, #48] @ (8003ca4 ) 8003c74: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003c78: 4a0a ldr r2, [pc, #40] @ (8003ca4 ) 8003c7a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8003c7e: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8003c82: 4b08 ldr r3, [pc, #32] @ (8003ca4 ) 8003c84: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003c88: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003c8c: 603b str r3, [r7, #0] 8003c8e: 683b ldr r3, [r7, #0] /** Disable the Internal Voltage Reference buffer */ HAL_SYSCFG_DisableVREFBUF(); 8003c90: f002 f8e0 bl 8005e54 /** Configure the internal voltage reference buffer high impedance mode */ HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE); 8003c94: 2002 movs r0, #2 8003c96: f002 f8c9 bl 8005e2c /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8003c9a: bf00 nop 8003c9c: 3718 adds r7, #24 8003c9e: 46bd mov sp, r7 8003ca0: bd80 pop {r7, pc} 8003ca2: bf00 nop 8003ca4: 58024400 .word 0x58024400 08003ca8 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8003ca8: b580 push {r7, lr} 8003caa: b092 sub sp, #72 @ 0x48 8003cac: af00 add r7, sp, #0 8003cae: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003cb0: f107 0334 add.w r3, r7, #52 @ 0x34 8003cb4: 2200 movs r2, #0 8003cb6: 601a str r2, [r3, #0] 8003cb8: 605a str r2, [r3, #4] 8003cba: 609a str r2, [r3, #8] 8003cbc: 60da str r2, [r3, #12] 8003cbe: 611a str r2, [r3, #16] if(hadc->Instance==ADC1) 8003cc0: 687b ldr r3, [r7, #4] 8003cc2: 681b ldr r3, [r3, #0] 8003cc4: 4a9d ldr r2, [pc, #628] @ (8003f3c ) 8003cc6: 4293 cmp r3, r2 8003cc8: f040 8099 bne.w 8003dfe { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; 8003ccc: 4b9c ldr r3, [pc, #624] @ (8003f40 ) 8003cce: 681b ldr r3, [r3, #0] 8003cd0: 3301 adds r3, #1 8003cd2: 4a9b ldr r2, [pc, #620] @ (8003f40 ) 8003cd4: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8003cd6: 4b9a ldr r3, [pc, #616] @ (8003f40 ) 8003cd8: 681b ldr r3, [r3, #0] 8003cda: 2b01 cmp r3, #1 8003cdc: d10e bne.n 8003cfc __HAL_RCC_ADC12_CLK_ENABLE(); 8003cde: 4b99 ldr r3, [pc, #612] @ (8003f44 ) 8003ce0: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003ce4: 4a97 ldr r2, [pc, #604] @ (8003f44 ) 8003ce6: f043 0320 orr.w r3, r3, #32 8003cea: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8003cee: 4b95 ldr r3, [pc, #596] @ (8003f44 ) 8003cf0: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003cf4: f003 0320 and.w r3, r3, #32 8003cf8: 633b str r3, [r7, #48] @ 0x30 8003cfa: 6b3b ldr r3, [r7, #48] @ 0x30 } __HAL_RCC_GPIOA_CLK_ENABLE(); 8003cfc: 4b91 ldr r3, [pc, #580] @ (8003f44 ) 8003cfe: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d02: 4a90 ldr r2, [pc, #576] @ (8003f44 ) 8003d04: f043 0301 orr.w r3, r3, #1 8003d08: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003d0c: 4b8d ldr r3, [pc, #564] @ (8003f44 ) 8003d0e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d12: f003 0301 and.w r3, r3, #1 8003d16: 62fb str r3, [r7, #44] @ 0x2c 8003d18: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 8003d1a: 4b8a ldr r3, [pc, #552] @ (8003f44 ) 8003d1c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d20: 4a88 ldr r2, [pc, #544] @ (8003f44 ) 8003d22: f043 0304 orr.w r3, r3, #4 8003d26: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003d2a: 4b86 ldr r3, [pc, #536] @ (8003f44 ) 8003d2c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d30: f003 0304 and.w r3, r3, #4 8003d34: 62bb str r3, [r7, #40] @ 0x28 8003d36: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOB_CLK_ENABLE(); 8003d38: 4b82 ldr r3, [pc, #520] @ (8003f44 ) 8003d3a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d3e: 4a81 ldr r2, [pc, #516] @ (8003f44 ) 8003d40: f043 0302 orr.w r3, r3, #2 8003d44: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003d48: 4b7e ldr r3, [pc, #504] @ (8003f44 ) 8003d4a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d4e: f003 0302 and.w r3, r3, #2 8003d52: 627b str r3, [r7, #36] @ 0x24 8003d54: 6a7b ldr r3, [r7, #36] @ 0x24 PA3 ------> ADC1_INP15 PA7 ------> ADC1_INP7 PC5 ------> ADC1_INP8 PB0 ------> ADC1_INP9 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 8003d56: 238f movs r3, #143 @ 0x8f 8003d58: 637b str r3, [r7, #52] @ 0x34 |GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003d5a: 2303 movs r3, #3 8003d5c: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003d5e: 2300 movs r3, #0 8003d60: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003d62: f107 0334 add.w r3, r7, #52 @ 0x34 8003d66: 4619 mov r1, r3 8003d68: 4877 ldr r0, [pc, #476] @ (8003f48 ) 8003d6a: f007 fa1f bl 800b1ac GPIO_InitStruct.Pin = GPIO_PIN_5; 8003d6e: 2320 movs r3, #32 8003d70: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003d72: 2303 movs r3, #3 8003d74: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003d76: 2300 movs r3, #0 8003d78: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003d7a: f107 0334 add.w r3, r7, #52 @ 0x34 8003d7e: 4619 mov r1, r3 8003d80: 4872 ldr r0, [pc, #456] @ (8003f4c ) 8003d82: f007 fa13 bl 800b1ac GPIO_InitStruct.Pin = GPIO_PIN_0; 8003d86: 2301 movs r3, #1 8003d88: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003d8a: 2303 movs r3, #3 8003d8c: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003d8e: 2300 movs r3, #0 8003d90: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003d92: f107 0334 add.w r3, r7, #52 @ 0x34 8003d96: 4619 mov r1, r3 8003d98: 486d ldr r0, [pc, #436] @ (8003f50 ) 8003d9a: f007 fa07 bl 800b1ac /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Stream0; 8003d9e: 4b6d ldr r3, [pc, #436] @ (8003f54 ) 8003da0: 4a6d ldr r2, [pc, #436] @ (8003f58 ) 8003da2: 601a str r2, [r3, #0] hdma_adc1.Init.Request = DMA_REQUEST_ADC1; 8003da4: 4b6b ldr r3, [pc, #428] @ (8003f54 ) 8003da6: 2209 movs r2, #9 8003da8: 605a str r2, [r3, #4] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003daa: 4b6a ldr r3, [pc, #424] @ (8003f54 ) 8003dac: 2200 movs r2, #0 8003dae: 609a str r2, [r3, #8] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8003db0: 4b68 ldr r3, [pc, #416] @ (8003f54 ) 8003db2: 2200 movs r2, #0 8003db4: 60da str r2, [r3, #12] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8003db6: 4b67 ldr r3, [pc, #412] @ (8003f54 ) 8003db8: f44f 6280 mov.w r2, #1024 @ 0x400 8003dbc: 611a str r2, [r3, #16] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8003dbe: 4b65 ldr r3, [pc, #404] @ (8003f54 ) 8003dc0: f44f 6200 mov.w r2, #2048 @ 0x800 8003dc4: 615a str r2, [r3, #20] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8003dc6: 4b63 ldr r3, [pc, #396] @ (8003f54 ) 8003dc8: f44f 5200 mov.w r2, #8192 @ 0x2000 8003dcc: 619a str r2, [r3, #24] hdma_adc1.Init.Mode = DMA_NORMAL; 8003dce: 4b61 ldr r3, [pc, #388] @ (8003f54 ) 8003dd0: 2200 movs r2, #0 8003dd2: 61da str r2, [r3, #28] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; 8003dd4: 4b5f ldr r3, [pc, #380] @ (8003f54 ) 8003dd6: 2200 movs r2, #0 8003dd8: 621a str r2, [r3, #32] hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003dda: 4b5e ldr r3, [pc, #376] @ (8003f54 ) 8003ddc: 2200 movs r2, #0 8003dde: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 8003de0: 485c ldr r0, [pc, #368] @ (8003f54 ) 8003de2: f004 fba7 bl 8008534 8003de6: 4603 mov r3, r0 8003de8: 2b00 cmp r3, #0 8003dea: d001 beq.n 8003df0 { Error_Handler(); 8003dec: f7fe f86e bl 8001ecc } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); 8003df0: 687b ldr r3, [r7, #4] 8003df2: 4a58 ldr r2, [pc, #352] @ (8003f54 ) 8003df4: 64da str r2, [r3, #76] @ 0x4c 8003df6: 4a57 ldr r2, [pc, #348] @ (8003f54 ) 8003df8: 687b ldr r3, [r7, #4] 8003dfa: 6393 str r3, [r2, #56] @ 0x38 /* USER CODE BEGIN ADC3_MspInit 1 */ /* USER CODE END ADC3_MspInit 1 */ } } 8003dfc: e11e b.n 800403c else if(hadc->Instance==ADC2) 8003dfe: 687b ldr r3, [r7, #4] 8003e00: 681b ldr r3, [r3, #0] 8003e02: 4a56 ldr r2, [pc, #344] @ (8003f5c ) 8003e04: 4293 cmp r3, r2 8003e06: f040 80af bne.w 8003f68 HAL_RCC_ADC12_CLK_ENABLED++; 8003e0a: 4b4d ldr r3, [pc, #308] @ (8003f40 ) 8003e0c: 681b ldr r3, [r3, #0] 8003e0e: 3301 adds r3, #1 8003e10: 4a4b ldr r2, [pc, #300] @ (8003f40 ) 8003e12: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8003e14: 4b4a ldr r3, [pc, #296] @ (8003f40 ) 8003e16: 681b ldr r3, [r3, #0] 8003e18: 2b01 cmp r3, #1 8003e1a: d10e bne.n 8003e3a __HAL_RCC_ADC12_CLK_ENABLE(); 8003e1c: 4b49 ldr r3, [pc, #292] @ (8003f44 ) 8003e1e: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003e22: 4a48 ldr r2, [pc, #288] @ (8003f44 ) 8003e24: f043 0320 orr.w r3, r3, #32 8003e28: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8003e2c: 4b45 ldr r3, [pc, #276] @ (8003f44 ) 8003e2e: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003e32: f003 0320 and.w r3, r3, #32 8003e36: 623b str r3, [r7, #32] 8003e38: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 8003e3a: 4b42 ldr r3, [pc, #264] @ (8003f44 ) 8003e3c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e40: 4a40 ldr r2, [pc, #256] @ (8003f44 ) 8003e42: f043 0301 orr.w r3, r3, #1 8003e46: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003e4a: 4b3e ldr r3, [pc, #248] @ (8003f44 ) 8003e4c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e50: f003 0301 and.w r3, r3, #1 8003e54: 61fb str r3, [r7, #28] 8003e56: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOC_CLK_ENABLE(); 8003e58: 4b3a ldr r3, [pc, #232] @ (8003f44 ) 8003e5a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e5e: 4a39 ldr r2, [pc, #228] @ (8003f44 ) 8003e60: f043 0304 orr.w r3, r3, #4 8003e64: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003e68: 4b36 ldr r3, [pc, #216] @ (8003f44 ) 8003e6a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e6e: f003 0304 and.w r3, r3, #4 8003e72: 61bb str r3, [r7, #24] 8003e74: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 8003e76: 4b33 ldr r3, [pc, #204] @ (8003f44 ) 8003e78: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e7c: 4a31 ldr r2, [pc, #196] @ (8003f44 ) 8003e7e: f043 0302 orr.w r3, r3, #2 8003e82: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003e86: 4b2f ldr r3, [pc, #188] @ (8003f44 ) 8003e88: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e8c: f003 0302 and.w r3, r3, #2 8003e90: 617b str r3, [r7, #20] 8003e92: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_6; 8003e94: 2340 movs r3, #64 @ 0x40 8003e96: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003e98: 2303 movs r3, #3 8003e9a: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003e9c: 2300 movs r3, #0 8003e9e: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003ea0: f107 0334 add.w r3, r7, #52 @ 0x34 8003ea4: 4619 mov r1, r3 8003ea6: 4828 ldr r0, [pc, #160] @ (8003f48 ) 8003ea8: f007 f980 bl 800b1ac GPIO_InitStruct.Pin = GPIO_PIN_4; 8003eac: 2310 movs r3, #16 8003eae: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003eb0: 2303 movs r3, #3 8003eb2: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003eb4: 2300 movs r3, #0 8003eb6: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003eb8: f107 0334 add.w r3, r7, #52 @ 0x34 8003ebc: 4619 mov r1, r3 8003ebe: 4823 ldr r0, [pc, #140] @ (8003f4c ) 8003ec0: f007 f974 bl 800b1ac GPIO_InitStruct.Pin = GPIO_PIN_1; 8003ec4: 2302 movs r3, #2 8003ec6: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003ec8: 2303 movs r3, #3 8003eca: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003ecc: 2300 movs r3, #0 8003ece: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003ed0: f107 0334 add.w r3, r7, #52 @ 0x34 8003ed4: 4619 mov r1, r3 8003ed6: 481e ldr r0, [pc, #120] @ (8003f50 ) 8003ed8: f007 f968 bl 800b1ac hdma_adc2.Instance = DMA1_Stream1; 8003edc: 4b20 ldr r3, [pc, #128] @ (8003f60 ) 8003ede: 4a21 ldr r2, [pc, #132] @ (8003f64 ) 8003ee0: 601a str r2, [r3, #0] hdma_adc2.Init.Request = DMA_REQUEST_ADC2; 8003ee2: 4b1f ldr r3, [pc, #124] @ (8003f60 ) 8003ee4: 220a movs r2, #10 8003ee6: 605a str r2, [r3, #4] hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003ee8: 4b1d ldr r3, [pc, #116] @ (8003f60 ) 8003eea: 2200 movs r2, #0 8003eec: 609a str r2, [r3, #8] hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; 8003eee: 4b1c ldr r3, [pc, #112] @ (8003f60 ) 8003ef0: 2200 movs r2, #0 8003ef2: 60da str r2, [r3, #12] hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; 8003ef4: 4b1a ldr r3, [pc, #104] @ (8003f60 ) 8003ef6: f44f 6280 mov.w r2, #1024 @ 0x400 8003efa: 611a str r2, [r3, #16] hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8003efc: 4b18 ldr r3, [pc, #96] @ (8003f60 ) 8003efe: f44f 6200 mov.w r2, #2048 @ 0x800 8003f02: 615a str r2, [r3, #20] hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8003f04: 4b16 ldr r3, [pc, #88] @ (8003f60 ) 8003f06: f44f 5200 mov.w r2, #8192 @ 0x2000 8003f0a: 619a str r2, [r3, #24] hdma_adc2.Init.Mode = DMA_NORMAL; 8003f0c: 4b14 ldr r3, [pc, #80] @ (8003f60 ) 8003f0e: 2200 movs r2, #0 8003f10: 61da str r2, [r3, #28] hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; 8003f12: 4b13 ldr r3, [pc, #76] @ (8003f60 ) 8003f14: 2200 movs r2, #0 8003f16: 621a str r2, [r3, #32] hdma_adc2.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003f18: 4b11 ldr r3, [pc, #68] @ (8003f60 ) 8003f1a: 2200 movs r2, #0 8003f1c: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) 8003f1e: 4810 ldr r0, [pc, #64] @ (8003f60 ) 8003f20: f004 fb08 bl 8008534 8003f24: 4603 mov r3, r0 8003f26: 2b00 cmp r3, #0 8003f28: d001 beq.n 8003f2e Error_Handler(); 8003f2a: f7fd ffcf bl 8001ecc __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2); 8003f2e: 687b ldr r3, [r7, #4] 8003f30: 4a0b ldr r2, [pc, #44] @ (8003f60 ) 8003f32: 64da str r2, [r3, #76] @ 0x4c 8003f34: 4a0a ldr r2, [pc, #40] @ (8003f60 ) 8003f36: 687b ldr r3, [r7, #4] 8003f38: 6393 str r3, [r2, #56] @ 0x38 } 8003f3a: e07f b.n 800403c 8003f3c: 40022000 .word 0x40022000 8003f40: 2400091c .word 0x2400091c 8003f44: 58024400 .word 0x58024400 8003f48: 58020000 .word 0x58020000 8003f4c: 58020800 .word 0x58020800 8003f50: 58020400 .word 0x58020400 8003f54: 2400024c .word 0x2400024c 8003f58: 40020010 .word 0x40020010 8003f5c: 40022100 .word 0x40022100 8003f60: 240002c4 .word 0x240002c4 8003f64: 40020028 .word 0x40020028 else if(hadc->Instance==ADC3) 8003f68: 687b ldr r3, [r7, #4] 8003f6a: 681b ldr r3, [r3, #0] 8003f6c: 4a35 ldr r2, [pc, #212] @ (8004044 ) 8003f6e: 4293 cmp r3, r2 8003f70: d164 bne.n 800403c __HAL_RCC_ADC3_CLK_ENABLE(); 8003f72: 4b35 ldr r3, [pc, #212] @ (8004048 ) 8003f74: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003f78: 4a33 ldr r2, [pc, #204] @ (8004048 ) 8003f7a: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8003f7e: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003f82: 4b31 ldr r3, [pc, #196] @ (8004048 ) 8003f84: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003f88: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8003f8c: 613b str r3, [r7, #16] 8003f8e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 8003f90: 4b2d ldr r3, [pc, #180] @ (8004048 ) 8003f92: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003f96: 4a2c ldr r2, [pc, #176] @ (8004048 ) 8003f98: f043 0304 orr.w r3, r3, #4 8003f9c: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003fa0: 4b29 ldr r3, [pc, #164] @ (8004048 ) 8003fa2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003fa6: f003 0304 and.w r3, r3, #4 8003faa: 60fb str r3, [r7, #12] 8003fac: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8003fae: 2303 movs r3, #3 8003fb0: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003fb2: 2303 movs r3, #3 8003fb4: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003fb6: 2300 movs r3, #0 8003fb8: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003fba: f107 0334 add.w r3, r7, #52 @ 0x34 8003fbe: 4619 mov r1, r3 8003fc0: 4822 ldr r0, [pc, #136] @ (800404c ) 8003fc2: f007 f8f3 bl 800b1ac HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC2, SYSCFG_SWITCH_PC2_OPEN); 8003fc6: f04f 6180 mov.w r1, #67108864 @ 0x4000000 8003fca: f04f 6080 mov.w r0, #67108864 @ 0x4000000 8003fce: f001 ff51 bl 8005e74 HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC3, SYSCFG_SWITCH_PC3_OPEN); 8003fd2: f04f 6100 mov.w r1, #134217728 @ 0x8000000 8003fd6: f04f 6000 mov.w r0, #134217728 @ 0x8000000 8003fda: f001 ff4b bl 8005e74 hdma_adc3.Instance = DMA1_Stream2; 8003fde: 4b1c ldr r3, [pc, #112] @ (8004050 ) 8003fe0: 4a1c ldr r2, [pc, #112] @ (8004054 ) 8003fe2: 601a str r2, [r3, #0] hdma_adc3.Init.Request = DMA_REQUEST_ADC3; 8003fe4: 4b1a ldr r3, [pc, #104] @ (8004050 ) 8003fe6: 2273 movs r2, #115 @ 0x73 8003fe8: 605a str r2, [r3, #4] hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003fea: 4b19 ldr r3, [pc, #100] @ (8004050 ) 8003fec: 2200 movs r2, #0 8003fee: 609a str r2, [r3, #8] hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE; 8003ff0: 4b17 ldr r3, [pc, #92] @ (8004050 ) 8003ff2: 2200 movs r2, #0 8003ff4: 60da str r2, [r3, #12] hdma_adc3.Init.MemInc = DMA_MINC_ENABLE; 8003ff6: 4b16 ldr r3, [pc, #88] @ (8004050 ) 8003ff8: f44f 6280 mov.w r2, #1024 @ 0x400 8003ffc: 611a str r2, [r3, #16] hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8003ffe: 4b14 ldr r3, [pc, #80] @ (8004050 ) 8004000: f44f 6200 mov.w r2, #2048 @ 0x800 8004004: 615a str r2, [r3, #20] hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8004006: 4b12 ldr r3, [pc, #72] @ (8004050 ) 8004008: f44f 5200 mov.w r2, #8192 @ 0x2000 800400c: 619a str r2, [r3, #24] hdma_adc3.Init.Mode = DMA_NORMAL; 800400e: 4b10 ldr r3, [pc, #64] @ (8004050 ) 8004010: 2200 movs r2, #0 8004012: 61da str r2, [r3, #28] hdma_adc3.Init.Priority = DMA_PRIORITY_LOW; 8004014: 4b0e ldr r3, [pc, #56] @ (8004050 ) 8004016: 2200 movs r2, #0 8004018: 621a str r2, [r3, #32] hdma_adc3.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 800401a: 4b0d ldr r3, [pc, #52] @ (8004050 ) 800401c: 2200 movs r2, #0 800401e: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc3) != HAL_OK) 8004020: 480b ldr r0, [pc, #44] @ (8004050 ) 8004022: f004 fa87 bl 8008534 8004026: 4603 mov r3, r0 8004028: 2b00 cmp r3, #0 800402a: d001 beq.n 8004030 Error_Handler(); 800402c: f7fd ff4e bl 8001ecc __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc3); 8004030: 687b ldr r3, [r7, #4] 8004032: 4a07 ldr r2, [pc, #28] @ (8004050 ) 8004034: 64da str r2, [r3, #76] @ 0x4c 8004036: 4a06 ldr r2, [pc, #24] @ (8004050 ) 8004038: 687b ldr r3, [r7, #4] 800403a: 6393 str r3, [r2, #56] @ 0x38 } 800403c: bf00 nop 800403e: 3748 adds r7, #72 @ 0x48 8004040: 46bd mov sp, r7 8004042: bd80 pop {r7, pc} 8004044: 58026000 .word 0x58026000 8004048: 58024400 .word 0x58024400 800404c: 58020800 .word 0x58020800 8004050: 2400033c .word 0x2400033c 8004054: 40020040 .word 0x40020040 08004058 : * This function configures the hardware resources used in this example * @param hcomp: COMP handle pointer * @retval None */ void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp) { 8004058: b580 push {r7, lr} 800405a: b08a sub sp, #40 @ 0x28 800405c: af00 add r7, sp, #0 800405e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004060: f107 0314 add.w r3, r7, #20 8004064: 2200 movs r2, #0 8004066: 601a str r2, [r3, #0] 8004068: 605a str r2, [r3, #4] 800406a: 609a str r2, [r3, #8] 800406c: 60da str r2, [r3, #12] 800406e: 611a str r2, [r3, #16] if(hcomp->Instance==COMP1) 8004070: 687b ldr r3, [r7, #4] 8004072: 681b ldr r3, [r3, #0] 8004074: 4a18 ldr r2, [pc, #96] @ (80040d8 ) 8004076: 4293 cmp r3, r2 8004078: d129 bne.n 80040ce { /* USER CODE BEGIN COMP1_MspInit 0 */ /* USER CODE END COMP1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_COMP12_CLK_ENABLE(); 800407a: 4b18 ldr r3, [pc, #96] @ (80040dc ) 800407c: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8004080: 4a16 ldr r2, [pc, #88] @ (80040dc ) 8004082: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8004086: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 800408a: 4b14 ldr r3, [pc, #80] @ (80040dc ) 800408c: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8004090: f403 4380 and.w r3, r3, #16384 @ 0x4000 8004094: 613b str r3, [r7, #16] 8004096: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8004098: 4b10 ldr r3, [pc, #64] @ (80040dc ) 800409a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800409e: 4a0f ldr r2, [pc, #60] @ (80040dc ) 80040a0: f043 0302 orr.w r3, r3, #2 80040a4: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80040a8: 4b0c ldr r3, [pc, #48] @ (80040dc ) 80040aa: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80040ae: f003 0302 and.w r3, r3, #2 80040b2: 60fb str r3, [r7, #12] 80040b4: 68fb ldr r3, [r7, #12] /**COMP1 GPIO Configuration PB2 ------> COMP1_INP */ GPIO_InitStruct.Pin = GPIO_PIN_2; 80040b6: 2304 movs r3, #4 80040b8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80040ba: 2303 movs r3, #3 80040bc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80040be: 2300 movs r3, #0 80040c0: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80040c2: f107 0314 add.w r3, r7, #20 80040c6: 4619 mov r1, r3 80040c8: 4805 ldr r0, [pc, #20] @ (80040e0 ) 80040ca: f007 f86f bl 800b1ac /* USER CODE BEGIN COMP1_MspInit 1 */ /* USER CODE END COMP1_MspInit 1 */ } } 80040ce: bf00 nop 80040d0: 3728 adds r7, #40 @ 0x28 80040d2: 46bd mov sp, r7 80040d4: bd80 pop {r7, pc} 80040d6: bf00 nop 80040d8: 5800380c .word 0x5800380c 80040dc: 58024400 .word 0x58024400 80040e0: 58020400 .word 0x58020400 080040e4 : * This function configures the hardware resources used in this example * @param hcrc: CRC handle pointer * @retval None */ void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) { 80040e4: b480 push {r7} 80040e6: b085 sub sp, #20 80040e8: af00 add r7, sp, #0 80040ea: 6078 str r0, [r7, #4] if(hcrc->Instance==CRC) 80040ec: 687b ldr r3, [r7, #4] 80040ee: 681b ldr r3, [r3, #0] 80040f0: 4a0b ldr r2, [pc, #44] @ (8004120 ) 80040f2: 4293 cmp r3, r2 80040f4: d10e bne.n 8004114 { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 80040f6: 4b0b ldr r3, [pc, #44] @ (8004124 ) 80040f8: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80040fc: 4a09 ldr r2, [pc, #36] @ (8004124 ) 80040fe: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8004102: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004106: 4b07 ldr r3, [pc, #28] @ (8004124 ) 8004108: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800410c: f403 2300 and.w r3, r3, #524288 @ 0x80000 8004110: 60fb str r3, [r7, #12] 8004112: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 8004114: bf00 nop 8004116: 3714 adds r7, #20 8004118: 46bd mov sp, r7 800411a: f85d 7b04 ldr.w r7, [sp], #4 800411e: 4770 bx lr 8004120: 58024c00 .word 0x58024c00 8004124: 58024400 .word 0x58024400 08004128 : * This function configures the hardware resources used in this example * @param hdac: DAC handle pointer * @retval None */ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) { 8004128: b580 push {r7, lr} 800412a: b08a sub sp, #40 @ 0x28 800412c: af00 add r7, sp, #0 800412e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004130: f107 0314 add.w r3, r7, #20 8004134: 2200 movs r2, #0 8004136: 601a str r2, [r3, #0] 8004138: 605a str r2, [r3, #4] 800413a: 609a str r2, [r3, #8] 800413c: 60da str r2, [r3, #12] 800413e: 611a str r2, [r3, #16] if(hdac->Instance==DAC1) 8004140: 687b ldr r3, [r7, #4] 8004142: 681b ldr r3, [r3, #0] 8004144: 4a1c ldr r2, [pc, #112] @ (80041b8 ) 8004146: 4293 cmp r3, r2 8004148: d131 bne.n 80041ae { /* USER CODE BEGIN DAC1_MspInit 0 */ /* USER CODE END DAC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DAC12_CLK_ENABLE(); 800414a: 4b1c ldr r3, [pc, #112] @ (80041bc ) 800414c: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004150: 4a1a ldr r2, [pc, #104] @ (80041bc ) 8004152: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8004156: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 800415a: 4b18 ldr r3, [pc, #96] @ (80041bc ) 800415c: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004160: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004164: 613b str r3, [r7, #16] 8004166: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8004168: 4b14 ldr r3, [pc, #80] @ (80041bc ) 800416a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800416e: 4a13 ldr r2, [pc, #76] @ (80041bc ) 8004170: f043 0301 orr.w r3, r3, #1 8004174: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004178: 4b10 ldr r3, [pc, #64] @ (80041bc ) 800417a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800417e: f003 0301 and.w r3, r3, #1 8004182: 60fb str r3, [r7, #12] 8004184: 68fb ldr r3, [r7, #12] /**DAC1 GPIO Configuration PA4 ------> DAC1_OUT1 PA5 ------> DAC1_OUT2 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 8004186: 2330 movs r3, #48 @ 0x30 8004188: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 800418a: 2303 movs r3, #3 800418c: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800418e: 2300 movs r3, #0 8004190: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8004192: f107 0314 add.w r3, r7, #20 8004196: 4619 mov r1, r3 8004198: 4809 ldr r0, [pc, #36] @ (80041c0 ) 800419a: f007 f807 bl 800b1ac /* DAC1 interrupt Init */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 5, 0); 800419e: 2200 movs r2, #0 80041a0: 2105 movs r1, #5 80041a2: 2036 movs r0, #54 @ 0x36 80041a4: f003 fcd0 bl 8007b48 HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 80041a8: 2036 movs r0, #54 @ 0x36 80041aa: f003 fce7 bl 8007b7c /* USER CODE BEGIN DAC1_MspInit 1 */ /* USER CODE END DAC1_MspInit 1 */ } } 80041ae: bf00 nop 80041b0: 3728 adds r7, #40 @ 0x28 80041b2: 46bd mov sp, r7 80041b4: bd80 pop {r7, pc} 80041b6: bf00 nop 80041b8: 40007400 .word 0x40007400 80041bc: 58024400 .word 0x58024400 80041c0: 58020000 .word 0x58020000 080041c4 : * This function configures the hardware resources used in this example * @param hrng: RNG handle pointer * @retval None */ void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) { 80041c4: b580 push {r7, lr} 80041c6: b0b4 sub sp, #208 @ 0xd0 80041c8: af00 add r7, sp, #0 80041ca: 6078 str r0, [r7, #4] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 80041cc: f107 0310 add.w r3, r7, #16 80041d0: 22c0 movs r2, #192 @ 0xc0 80041d2: 2100 movs r1, #0 80041d4: 4618 mov r0, r3 80041d6: f014 f887 bl 80182e8 if(hrng->Instance==RNG) 80041da: 687b ldr r3, [r7, #4] 80041dc: 681b ldr r3, [r3, #0] 80041de: 4a14 ldr r2, [pc, #80] @ (8004230 ) 80041e0: 4293 cmp r3, r2 80041e2: d121 bne.n 8004228 /* USER CODE END RNG_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG; 80041e4: f44f 3200 mov.w r2, #131072 @ 0x20000 80041e8: f04f 0300 mov.w r3, #0 80041ec: e9c7 2304 strd r2, r3, [r7, #16] PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48; 80041f0: 2300 movs r3, #0 80041f2: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80041f6: f107 0310 add.w r3, r7, #16 80041fa: 4618 mov r0, r3 80041fc: f008 fbbc bl 800c978 8004200: 4603 mov r3, r0 8004202: 2b00 cmp r3, #0 8004204: d001 beq.n 800420a { Error_Handler(); 8004206: f7fd fe61 bl 8001ecc } /* Peripheral clock enable */ __HAL_RCC_RNG_CLK_ENABLE(); 800420a: 4b0a ldr r3, [pc, #40] @ (8004234 ) 800420c: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 8004210: 4a08 ldr r2, [pc, #32] @ (8004234 ) 8004212: f043 0340 orr.w r3, r3, #64 @ 0x40 8004216: f8c2 30dc str.w r3, [r2, #220] @ 0xdc 800421a: 4b06 ldr r3, [pc, #24] @ (8004234 ) 800421c: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 8004220: f003 0340 and.w r3, r3, #64 @ 0x40 8004224: 60fb str r3, [r7, #12] 8004226: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN RNG_MspInit 1 */ /* USER CODE END RNG_MspInit 1 */ } } 8004228: bf00 nop 800422a: 37d0 adds r7, #208 @ 0xd0 800422c: 46bd mov sp, r7 800422e: bd80 pop {r7, pc} 8004230: 48021800 .word 0x48021800 8004234: 58024400 .word 0x58024400 08004238 : * This function configures the hardware resources used in this example * @param htim_pwm: TIM_PWM handle pointer * @retval None */ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) { 8004238: b480 push {r7} 800423a: b085 sub sp, #20 800423c: af00 add r7, sp, #0 800423e: 6078 str r0, [r7, #4] if(htim_pwm->Instance==TIM1) 8004240: 687b ldr r3, [r7, #4] 8004242: 681b ldr r3, [r3, #0] 8004244: 4a16 ldr r2, [pc, #88] @ (80042a0 ) 8004246: 4293 cmp r3, r2 8004248: d10f bne.n 800426a { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 800424a: 4b16 ldr r3, [pc, #88] @ (80042a4 ) 800424c: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8004250: 4a14 ldr r2, [pc, #80] @ (80042a4 ) 8004252: f043 0301 orr.w r3, r3, #1 8004256: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 800425a: 4b12 ldr r3, [pc, #72] @ (80042a4 ) 800425c: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8004260: f003 0301 and.w r3, r3, #1 8004264: 60fb str r3, [r7, #12] 8004266: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 8004268: e013 b.n 8004292 else if(htim_pwm->Instance==TIM3) 800426a: 687b ldr r3, [r7, #4] 800426c: 681b ldr r3, [r3, #0] 800426e: 4a0e ldr r2, [pc, #56] @ (80042a8 ) 8004270: 4293 cmp r3, r2 8004272: d10e bne.n 8004292 __HAL_RCC_TIM3_CLK_ENABLE(); 8004274: 4b0b ldr r3, [pc, #44] @ (80042a4 ) 8004276: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800427a: 4a0a ldr r2, [pc, #40] @ (80042a4 ) 800427c: f043 0302 orr.w r3, r3, #2 8004280: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8004284: 4b07 ldr r3, [pc, #28] @ (80042a4 ) 8004286: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800428a: f003 0302 and.w r3, r3, #2 800428e: 60bb str r3, [r7, #8] 8004290: 68bb ldr r3, [r7, #8] } 8004292: bf00 nop 8004294: 3714 adds r7, #20 8004296: 46bd mov sp, r7 8004298: f85d 7b04 ldr.w r7, [sp], #4 800429c: 4770 bx lr 800429e: bf00 nop 80042a0: 40010000 .word 0x40010000 80042a4: 58024400 .word 0x58024400 80042a8: 40000400 .word 0x40000400 080042ac : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 80042ac: b580 push {r7, lr} 80042ae: b08c sub sp, #48 @ 0x30 80042b0: af00 add r7, sp, #0 80042b2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80042b4: f107 031c add.w r3, r7, #28 80042b8: 2200 movs r2, #0 80042ba: 601a str r2, [r3, #0] 80042bc: 605a str r2, [r3, #4] 80042be: 609a str r2, [r3, #8] 80042c0: 60da str r2, [r3, #12] 80042c2: 611a str r2, [r3, #16] if(htim_base->Instance==TIM2) 80042c4: 687b ldr r3, [r7, #4] 80042c6: 681b ldr r3, [r3, #0] 80042c8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80042cc: d137 bne.n 800433e { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 80042ce: 4b46 ldr r3, [pc, #280] @ (80043e8 ) 80042d0: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80042d4: 4a44 ldr r2, [pc, #272] @ (80043e8 ) 80042d6: f043 0301 orr.w r3, r3, #1 80042da: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 80042de: 4b42 ldr r3, [pc, #264] @ (80043e8 ) 80042e0: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80042e4: f003 0301 and.w r3, r3, #1 80042e8: 61bb str r3, [r7, #24] 80042ea: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 80042ec: 4b3e ldr r3, [pc, #248] @ (80043e8 ) 80042ee: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80042f2: 4a3d ldr r2, [pc, #244] @ (80043e8 ) 80042f4: f043 0302 orr.w r3, r3, #2 80042f8: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80042fc: 4b3a ldr r3, [pc, #232] @ (80043e8 ) 80042fe: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004302: f003 0302 and.w r3, r3, #2 8004306: 617b str r3, [r7, #20] 8004308: 697b ldr r3, [r7, #20] /**TIM2 GPIO Configuration PB10 ------> TIM2_CH3 PB11 ------> TIM2_CH4 */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; 800430a: f44f 6340 mov.w r3, #3072 @ 0xc00 800430e: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004310: 2302 movs r3, #2 8004312: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004314: 2300 movs r3, #0 8004316: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8004318: 2300 movs r3, #0 800431a: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 800431c: 2301 movs r3, #1 800431e: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8004320: f107 031c add.w r3, r7, #28 8004324: 4619 mov r1, r3 8004326: 4831 ldr r0, [pc, #196] @ (80043ec ) 8004328: f006 ff40 bl 800b1ac /* TIM2 interrupt Init */ HAL_NVIC_SetPriority(TIM2_IRQn, 5, 0); 800432c: 2200 movs r2, #0 800432e: 2105 movs r1, #5 8004330: 201c movs r0, #28 8004332: f003 fc09 bl 8007b48 HAL_NVIC_EnableIRQ(TIM2_IRQn); 8004336: 201c movs r0, #28 8004338: f003 fc20 bl 8007b7c /* USER CODE BEGIN TIM8_MspInit 1 */ /* USER CODE END TIM8_MspInit 1 */ } } 800433c: e050 b.n 80043e0 else if(htim_base->Instance==TIM4) 800433e: 687b ldr r3, [r7, #4] 8004340: 681b ldr r3, [r3, #0] 8004342: 4a2b ldr r2, [pc, #172] @ (80043f0 ) 8004344: 4293 cmp r3, r2 8004346: d137 bne.n 80043b8 __HAL_RCC_TIM4_CLK_ENABLE(); 8004348: 4b27 ldr r3, [pc, #156] @ (80043e8 ) 800434a: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800434e: 4a26 ldr r2, [pc, #152] @ (80043e8 ) 8004350: f043 0304 orr.w r3, r3, #4 8004354: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8004358: 4b23 ldr r3, [pc, #140] @ (80043e8 ) 800435a: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800435e: f003 0304 and.w r3, r3, #4 8004362: 613b str r3, [r7, #16] 8004364: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOD_CLK_ENABLE(); 8004366: 4b20 ldr r3, [pc, #128] @ (80043e8 ) 8004368: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800436c: 4a1e ldr r2, [pc, #120] @ (80043e8 ) 800436e: f043 0308 orr.w r3, r3, #8 8004372: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004376: 4b1c ldr r3, [pc, #112] @ (80043e8 ) 8004378: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800437c: f003 0308 and.w r3, r3, #8 8004380: 60fb str r3, [r7, #12] 8004382: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 8004384: f44f 4340 mov.w r3, #49152 @ 0xc000 8004388: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800438a: 2302 movs r3, #2 800438c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800438e: 2300 movs r3, #0 8004390: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8004392: 2300 movs r3, #0 8004394: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; 8004396: 2302 movs r3, #2 8004398: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800439a: f107 031c add.w r3, r7, #28 800439e: 4619 mov r1, r3 80043a0: 4814 ldr r0, [pc, #80] @ (80043f4 ) 80043a2: f006 ff03 bl 800b1ac HAL_NVIC_SetPriority(TIM4_IRQn, 5, 0); 80043a6: 2200 movs r2, #0 80043a8: 2105 movs r1, #5 80043aa: 201e movs r0, #30 80043ac: f003 fbcc bl 8007b48 HAL_NVIC_EnableIRQ(TIM4_IRQn); 80043b0: 201e movs r0, #30 80043b2: f003 fbe3 bl 8007b7c } 80043b6: e013 b.n 80043e0 else if(htim_base->Instance==TIM8) 80043b8: 687b ldr r3, [r7, #4] 80043ba: 681b ldr r3, [r3, #0] 80043bc: 4a0e ldr r2, [pc, #56] @ (80043f8 ) 80043be: 4293 cmp r3, r2 80043c0: d10e bne.n 80043e0 __HAL_RCC_TIM8_CLK_ENABLE(); 80043c2: 4b09 ldr r3, [pc, #36] @ (80043e8 ) 80043c4: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80043c8: 4a07 ldr r2, [pc, #28] @ (80043e8 ) 80043ca: f043 0302 orr.w r3, r3, #2 80043ce: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 80043d2: 4b05 ldr r3, [pc, #20] @ (80043e8 ) 80043d4: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80043d8: f003 0302 and.w r3, r3, #2 80043dc: 60bb str r3, [r7, #8] 80043de: 68bb ldr r3, [r7, #8] } 80043e0: bf00 nop 80043e2: 3730 adds r7, #48 @ 0x30 80043e4: 46bd mov sp, r7 80043e6: bd80 pop {r7, pc} 80043e8: 58024400 .word 0x58024400 80043ec: 58020400 .word 0x58020400 80043f0: 40000800 .word 0x40000800 80043f4: 58020c00 .word 0x58020c00 80043f8: 40010400 .word 0x40010400 080043fc : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 80043fc: b580 push {r7, lr} 80043fe: b08a sub sp, #40 @ 0x28 8004400: af00 add r7, sp, #0 8004402: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004404: f107 0314 add.w r3, r7, #20 8004408: 2200 movs r2, #0 800440a: 601a str r2, [r3, #0] 800440c: 605a str r2, [r3, #4] 800440e: 609a str r2, [r3, #8] 8004410: 60da str r2, [r3, #12] 8004412: 611a str r2, [r3, #16] if(htim->Instance==TIM1) 8004414: 687b ldr r3, [r7, #4] 8004416: 681b ldr r3, [r3, #0] 8004418: 4a26 ldr r2, [pc, #152] @ (80044b4 ) 800441a: 4293 cmp r3, r2 800441c: d120 bne.n 8004460 { /* USER CODE BEGIN TIM1_MspPostInit 0 */ /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800441e: 4b26 ldr r3, [pc, #152] @ (80044b8 ) 8004420: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004424: 4a24 ldr r2, [pc, #144] @ (80044b8 ) 8004426: f043 0301 orr.w r3, r3, #1 800442a: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800442e: 4b22 ldr r3, [pc, #136] @ (80044b8 ) 8004430: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004434: f003 0301 and.w r3, r3, #1 8004438: 613b str r3, [r7, #16] 800443a: 693b ldr r3, [r7, #16] /**TIM1 GPIO Configuration PA9 ------> TIM1_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_9; 800443c: f44f 7300 mov.w r3, #512 @ 0x200 8004440: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004442: 2302 movs r3, #2 8004444: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004446: 2300 movs r3, #0 8004448: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800444a: 2300 movs r3, #0 800444c: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; 800444e: 2301 movs r3, #1 8004450: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8004452: f107 0314 add.w r3, r7, #20 8004456: 4619 mov r1, r3 8004458: 4818 ldr r0, [pc, #96] @ (80044bc ) 800445a: f006 fea7 bl 800b1ac /* USER CODE BEGIN TIM3_MspPostInit 1 */ /* USER CODE END TIM3_MspPostInit 1 */ } } 800445e: e024 b.n 80044aa else if(htim->Instance==TIM3) 8004460: 687b ldr r3, [r7, #4] 8004462: 681b ldr r3, [r3, #0] 8004464: 4a16 ldr r2, [pc, #88] @ (80044c0 ) 8004466: 4293 cmp r3, r2 8004468: d11f bne.n 80044aa __HAL_RCC_GPIOC_CLK_ENABLE(); 800446a: 4b13 ldr r3, [pc, #76] @ (80044b8 ) 800446c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004470: 4a11 ldr r2, [pc, #68] @ (80044b8 ) 8004472: f043 0304 orr.w r3, r3, #4 8004476: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800447a: 4b0f ldr r3, [pc, #60] @ (80044b8 ) 800447c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004480: f003 0304 and.w r3, r3, #4 8004484: 60fb str r3, [r7, #12] 8004486: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 8004488: f44f 7370 mov.w r3, #960 @ 0x3c0 800448c: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800448e: 2302 movs r3, #2 8004490: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004492: 2300 movs r3, #0 8004494: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 8004496: 2301 movs r3, #1 8004498: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 800449a: 2302 movs r3, #2 800449c: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800449e: f107 0314 add.w r3, r7, #20 80044a2: 4619 mov r1, r3 80044a4: 4807 ldr r0, [pc, #28] @ (80044c4 ) 80044a6: f006 fe81 bl 800b1ac } 80044aa: bf00 nop 80044ac: 3728 adds r7, #40 @ 0x28 80044ae: 46bd mov sp, r7 80044b0: bd80 pop {r7, pc} 80044b2: bf00 nop 80044b4: 40010000 .word 0x40010000 80044b8: 58024400 .word 0x58024400 80044bc: 58020000 .word 0x58020000 80044c0: 40000400 .word 0x40000400 80044c4: 58020800 .word 0x58020800 080044c8 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 80044c8: b580 push {r7, lr} 80044ca: b0bc sub sp, #240 @ 0xf0 80044cc: af00 add r7, sp, #0 80044ce: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80044d0: f107 03dc add.w r3, r7, #220 @ 0xdc 80044d4: 2200 movs r2, #0 80044d6: 601a str r2, [r3, #0] 80044d8: 605a str r2, [r3, #4] 80044da: 609a str r2, [r3, #8] 80044dc: 60da str r2, [r3, #12] 80044de: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 80044e0: f107 0318 add.w r3, r7, #24 80044e4: 22c0 movs r2, #192 @ 0xc0 80044e6: 2100 movs r1, #0 80044e8: 4618 mov r0, r3 80044ea: f013 fefd bl 80182e8 if(huart->Instance==UART8) 80044ee: 687b ldr r3, [r7, #4] 80044f0: 681b ldr r3, [r3, #0] 80044f2: 4a55 ldr r2, [pc, #340] @ (8004648 ) 80044f4: 4293 cmp r3, r2 80044f6: d14e bne.n 8004596 /* USER CODE END UART8_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8; 80044f8: f04f 0202 mov.w r2, #2 80044fc: f04f 0300 mov.w r3, #0 8004500: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 8004504: 2300 movs r3, #0 8004506: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800450a: f107 0318 add.w r3, r7, #24 800450e: 4618 mov r0, r3 8004510: f008 fa32 bl 800c978 8004514: 4603 mov r3, r0 8004516: 2b00 cmp r3, #0 8004518: d001 beq.n 800451e { Error_Handler(); 800451a: f7fd fcd7 bl 8001ecc } /* Peripheral clock enable */ __HAL_RCC_UART8_CLK_ENABLE(); 800451e: 4b4b ldr r3, [pc, #300] @ (800464c ) 8004520: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004524: 4a49 ldr r2, [pc, #292] @ (800464c ) 8004526: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 800452a: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 800452e: 4b47 ldr r3, [pc, #284] @ (800464c ) 8004530: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004534: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8004538: 617b str r3, [r7, #20] 800453a: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOE_CLK_ENABLE(); 800453c: 4b43 ldr r3, [pc, #268] @ (800464c ) 800453e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004542: 4a42 ldr r2, [pc, #264] @ (800464c ) 8004544: f043 0310 orr.w r3, r3, #16 8004548: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800454c: 4b3f ldr r3, [pc, #252] @ (800464c ) 800454e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004552: f003 0310 and.w r3, r3, #16 8004556: 613b str r3, [r7, #16] 8004558: 693b ldr r3, [r7, #16] /**UART8 GPIO Configuration PE0 ------> UART8_RX PE1 ------> UART8_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 800455a: 2303 movs r3, #3 800455c: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004560: 2302 movs r3, #2 8004562: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8004566: 2300 movs r3, #0 8004568: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800456c: 2300 movs r3, #0 800456e: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF8_UART8; 8004572: 2308 movs r3, #8 8004574: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8004578: f107 03dc add.w r3, r7, #220 @ 0xdc 800457c: 4619 mov r1, r3 800457e: 4834 ldr r0, [pc, #208] @ (8004650 ) 8004580: f006 fe14 bl 800b1ac /* UART8 interrupt Init */ HAL_NVIC_SetPriority(UART8_IRQn, 5, 0); 8004584: 2200 movs r2, #0 8004586: 2105 movs r1, #5 8004588: 2053 movs r0, #83 @ 0x53 800458a: f003 fadd bl 8007b48 HAL_NVIC_EnableIRQ(UART8_IRQn); 800458e: 2053 movs r0, #83 @ 0x53 8004590: f003 faf4 bl 8007b7c /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 8004594: e053 b.n 800463e else if(huart->Instance==USART1) 8004596: 687b ldr r3, [r7, #4] 8004598: 681b ldr r3, [r3, #0] 800459a: 4a2e ldr r2, [pc, #184] @ (8004654 ) 800459c: 4293 cmp r3, r2 800459e: d14e bne.n 800463e PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; 80045a0: f04f 0201 mov.w r2, #1 80045a4: f04f 0300 mov.w r3, #0 80045a8: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; 80045ac: 2300 movs r3, #0 80045ae: f8c7 3094 str.w r3, [r7, #148] @ 0x94 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80045b2: f107 0318 add.w r3, r7, #24 80045b6: 4618 mov r0, r3 80045b8: f008 f9de bl 800c978 80045bc: 4603 mov r3, r0 80045be: 2b00 cmp r3, #0 80045c0: d001 beq.n 80045c6 Error_Handler(); 80045c2: f7fd fc83 bl 8001ecc __HAL_RCC_USART1_CLK_ENABLE(); 80045c6: 4b21 ldr r3, [pc, #132] @ (800464c ) 80045c8: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80045cc: 4a1f ldr r2, [pc, #124] @ (800464c ) 80045ce: f043 0310 orr.w r3, r3, #16 80045d2: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 80045d6: 4b1d ldr r3, [pc, #116] @ (800464c ) 80045d8: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80045dc: f003 0310 and.w r3, r3, #16 80045e0: 60fb str r3, [r7, #12] 80045e2: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 80045e4: 4b19 ldr r3, [pc, #100] @ (800464c ) 80045e6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80045ea: 4a18 ldr r2, [pc, #96] @ (800464c ) 80045ec: f043 0302 orr.w r3, r3, #2 80045f0: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80045f4: 4b15 ldr r3, [pc, #84] @ (800464c ) 80045f6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80045fa: f003 0302 and.w r3, r3, #2 80045fe: 60bb str r3, [r7, #8] 8004600: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 8004602: f44f 4340 mov.w r3, #49152 @ 0xc000 8004606: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800460a: 2302 movs r3, #2 800460c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8004610: 2300 movs r3, #0 8004612: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8004616: 2300 movs r3, #0 8004618: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF4_USART1; 800461c: 2304 movs r3, #4 800461e: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8004622: f107 03dc add.w r3, r7, #220 @ 0xdc 8004626: 4619 mov r1, r3 8004628: 480b ldr r0, [pc, #44] @ (8004658 ) 800462a: f006 fdbf bl 800b1ac HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 800462e: 2200 movs r2, #0 8004630: 2105 movs r1, #5 8004632: 2025 movs r0, #37 @ 0x25 8004634: f003 fa88 bl 8007b48 HAL_NVIC_EnableIRQ(USART1_IRQn); 8004638: 2025 movs r0, #37 @ 0x25 800463a: f003 fa9f bl 8007b7c } 800463e: bf00 nop 8004640: 37f0 adds r7, #240 @ 0xf0 8004642: 46bd mov sp, r7 8004644: bd80 pop {r7, pc} 8004646: bf00 nop 8004648: 40007c00 .word 0x40007c00 800464c: 58024400 .word 0x58024400 8004650: 58021000 .word 0x58021000 8004654: 40011000 .word 0x40011000 8004658: 58020400 .word 0x58020400 0800465c : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800465c: b580 push {r7, lr} 800465e: b090 sub sp, #64 @ 0x40 8004660: af00 add r7, sp, #0 8004662: 6078 str r0, [r7, #4] uint32_t uwTimclock, uwAPB1Prescaler; uint32_t uwPrescalerValue; uint32_t pFLatency; /*Configure the TIM6 IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8004664: 687b ldr r3, [r7, #4] 8004666: 2b0f cmp r3, #15 8004668: d827 bhi.n 80046ba { HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U); 800466a: 2200 movs r2, #0 800466c: 6879 ldr r1, [r7, #4] 800466e: 2036 movs r0, #54 @ 0x36 8004670: f003 fa6a bl 8007b48 /* Enable the TIM6 global Interrupt */ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 8004674: 2036 movs r0, #54 @ 0x36 8004676: f003 fa81 bl 8007b7c uwTickPrio = TickPriority; 800467a: 4a29 ldr r2, [pc, #164] @ (8004720 ) 800467c: 687b ldr r3, [r7, #4] 800467e: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Enable TIM6 clock */ __HAL_RCC_TIM6_CLK_ENABLE(); 8004680: 4b28 ldr r3, [pc, #160] @ (8004724 ) 8004682: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004686: 4a27 ldr r2, [pc, #156] @ (8004724 ) 8004688: f043 0310 orr.w r3, r3, #16 800468c: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8004690: 4b24 ldr r3, [pc, #144] @ (8004724 ) 8004692: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004696: f003 0310 and.w r3, r3, #16 800469a: 60fb str r3, [r7, #12] 800469c: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 800469e: f107 0210 add.w r2, r7, #16 80046a2: f107 0314 add.w r3, r7, #20 80046a6: 4611 mov r1, r2 80046a8: 4618 mov r0, r3 80046aa: f008 f923 bl 800c8f4 /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; 80046ae: 6abb ldr r3, [r7, #40] @ 0x28 80046b0: 63bb str r3, [r7, #56] @ 0x38 /* Compute TIM6 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) 80046b2: 6bbb ldr r3, [r7, #56] @ 0x38 80046b4: 2b00 cmp r3, #0 80046b6: d106 bne.n 80046c6 80046b8: e001 b.n 80046be return HAL_ERROR; 80046ba: 2301 movs r3, #1 80046bc: e02b b.n 8004716 { uwTimclock = HAL_RCC_GetPCLK1Freq(); 80046be: f008 f8ed bl 800c89c 80046c2: 63f8 str r0, [r7, #60] @ 0x3c 80046c4: e004 b.n 80046d0 } else { uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); 80046c6: f008 f8e9 bl 800c89c 80046ca: 4603 mov r3, r0 80046cc: 005b lsls r3, r3, #1 80046ce: 63fb str r3, [r7, #60] @ 0x3c } /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 80046d0: 6bfb ldr r3, [r7, #60] @ 0x3c 80046d2: 4a15 ldr r2, [pc, #84] @ (8004728 ) 80046d4: fba2 2303 umull r2, r3, r2, r3 80046d8: 0c9b lsrs r3, r3, #18 80046da: 3b01 subs r3, #1 80046dc: 637b str r3, [r7, #52] @ 0x34 /* Initialize TIM6 */ htim6.Instance = TIM6; 80046de: 4b13 ldr r3, [pc, #76] @ (800472c ) 80046e0: 4a13 ldr r2, [pc, #76] @ (8004730 ) 80046e2: 601a str r2, [r3, #0] + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up */ htim6.Init.Period = (1000000U / 1000U) - 1U; 80046e4: 4b11 ldr r3, [pc, #68] @ (800472c ) 80046e6: f240 32e7 movw r2, #999 @ 0x3e7 80046ea: 60da str r2, [r3, #12] htim6.Init.Prescaler = uwPrescalerValue; 80046ec: 4a0f ldr r2, [pc, #60] @ (800472c ) 80046ee: 6b7b ldr r3, [r7, #52] @ 0x34 80046f0: 6053 str r3, [r2, #4] htim6.Init.ClockDivision = 0; 80046f2: 4b0e ldr r3, [pc, #56] @ (800472c ) 80046f4: 2200 movs r2, #0 80046f6: 611a str r2, [r3, #16] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 80046f8: 4b0c ldr r3, [pc, #48] @ (800472c ) 80046fa: 2200 movs r2, #0 80046fc: 609a str r2, [r3, #8] if(HAL_TIM_Base_Init(&htim6) == HAL_OK) 80046fe: 480b ldr r0, [pc, #44] @ (800472c ) 8004700: f00a fe7e bl 800f400 8004704: 4603 mov r3, r0 8004706: 2b00 cmp r3, #0 8004708: d104 bne.n 8004714 { /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&htim6); 800470a: 4808 ldr r0, [pc, #32] @ (800472c ) 800470c: f00a ff40 bl 800f590 8004710: 4603 mov r3, r0 8004712: e000 b.n 8004716 } /* Return function status */ return HAL_ERROR; 8004714: 2301 movs r3, #1 } 8004716: 4618 mov r0, r3 8004718: 3740 adds r7, #64 @ 0x40 800471a: 46bd mov sp, r7 800471c: bd80 pop {r7, pc} 800471e: bf00 nop 8004720: 2400003c .word 0x2400003c 8004724: 58024400 .word 0x58024400 8004728: 431bde83 .word 0x431bde83 800472c: 24000920 .word 0x24000920 8004730: 40001000 .word 0x40001000 08004734 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8004734: b480 push {r7} 8004736: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8004738: bf00 nop 800473a: e7fd b.n 8004738 0800473c : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800473c: b480 push {r7} 800473e: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8004740: bf00 nop 8004742: e7fd b.n 8004740 08004744 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8004744: b480 push {r7} 8004746: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8004748: bf00 nop 800474a: e7fd b.n 8004748 0800474c : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 800474c: b480 push {r7} 800474e: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8004750: bf00 nop 8004752: e7fd b.n 8004750 08004754 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8004754: b480 push {r7} 8004756: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8004758: bf00 nop 800475a: e7fd b.n 8004758 0800475c : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 800475c: b480 push {r7} 800475e: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8004760: bf00 nop 8004762: 46bd mov sp, r7 8004764: f85d 7b04 ldr.w r7, [sp], #4 8004768: 4770 bx lr 0800476a : /** * @brief This function handles RCC global interrupt. */ void RCC_IRQHandler(void) { 800476a: b480 push {r7} 800476c: af00 add r7, sp, #0 /* USER CODE END RCC_IRQn 0 */ /* USER CODE BEGIN RCC_IRQn 1 */ /* USER CODE END RCC_IRQn 1 */ } 800476e: bf00 nop 8004770: 46bd mov sp, r7 8004772: f85d 7b04 ldr.w r7, [sp], #4 8004776: 4770 bx lr 08004778 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 8004778: b580 push {r7, lr} 800477a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 800477c: 4802 ldr r0, [pc, #8] @ (8004788 ) 800477e: f005 fa03 bl 8009b88 /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 8004782: bf00 nop 8004784: bd80 pop {r7, pc} 8004786: bf00 nop 8004788: 2400024c .word 0x2400024c 0800478c : /** * @brief This function handles DMA1 stream1 global interrupt. */ void DMA1_Stream1_IRQHandler(void) { 800478c: b580 push {r7, lr} 800478e: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */ /* USER CODE END DMA1_Stream1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc2); 8004790: 4802 ldr r0, [pc, #8] @ (800479c ) 8004792: f005 f9f9 bl 8009b88 /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */ /* USER CODE END DMA1_Stream1_IRQn 1 */ } 8004796: bf00 nop 8004798: bd80 pop {r7, pc} 800479a: bf00 nop 800479c: 240002c4 .word 0x240002c4 080047a0 : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 80047a0: b580 push {r7, lr} 80047a2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc3); 80047a4: 4802 ldr r0, [pc, #8] @ (80047b0 ) 80047a6: f005 f9ef bl 8009b88 /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 80047aa: bf00 nop 80047ac: bd80 pop {r7, pc} 80047ae: bf00 nop 80047b0: 2400033c .word 0x2400033c 080047b4 : /** * @brief This function handles EXTI line[9:5] interrupts. */ void EXTI9_5_IRQHandler(void) { 80047b4: b580 push {r7, lr} 80047b6: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI9_5_IRQn 0 */ /* USER CODE END EXTI9_5_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8); 80047b8: f44f 7080 mov.w r0, #256 @ 0x100 80047bc: f006 fef1 bl 800b5a2 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9); 80047c0: f44f 7000 mov.w r0, #512 @ 0x200 80047c4: f006 feed bl 800b5a2 /* USER CODE BEGIN EXTI9_5_IRQn 1 */ /* USER CODE END EXTI9_5_IRQn 1 */ } 80047c8: bf00 nop 80047ca: bd80 pop {r7, pc} 080047cc : /** * @brief This function handles TIM2 global interrupt. */ void TIM2_IRQHandler(void) { 80047cc: b580 push {r7, lr} 80047ce: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_IRQn 0 */ /* USER CODE END TIM2_IRQn 0 */ HAL_TIM_IRQHandler(&htim2); 80047d0: 4802 ldr r0, [pc, #8] @ (80047dc ) 80047d2: f00b fb03 bl 800fddc /* USER CODE BEGIN TIM2_IRQn 1 */ /* USER CODE END TIM2_IRQn 1 */ } 80047d6: bf00 nop 80047d8: bd80 pop {r7, pc} 80047da: bf00 nop 80047dc: 24000488 .word 0x24000488 080047e0 : /** * @brief This function handles TIM4 global interrupt. */ void TIM4_IRQHandler(void) { 80047e0: b580 push {r7, lr} 80047e2: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_IRQn 0 */ /* USER CODE END TIM4_IRQn 0 */ HAL_TIM_IRQHandler(&htim4); 80047e4: 4802 ldr r0, [pc, #8] @ (80047f0 ) 80047e6: f00b faf9 bl 800fddc /* USER CODE BEGIN TIM4_IRQn 1 */ /* USER CODE END TIM4_IRQn 1 */ } 80047ea: bf00 nop 80047ec: bd80 pop {r7, pc} 80047ee: bf00 nop 80047f0: 24000520 .word 0x24000520 080047f4 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 80047f4: b580 push {r7, lr} 80047f6: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 80047f8: 4802 ldr r0, [pc, #8] @ (8004804 ) 80047fa: f00c feb3 bl 8011564 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 80047fe: bf00 nop 8004800: bd80 pop {r7, pc} 8004802: bf00 nop 8004804: 2400064c .word 0x2400064c 08004808 : /** * @brief This function handles EXTI line[15:10] interrupts. */ void EXTI15_10_IRQHandler(void) { 8004808: b580 push {r7, lr} 800480a: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI15_10_IRQn 0 */ /* USER CODE END EXTI15_10_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10); 800480c: f44f 6080 mov.w r0, #1024 @ 0x400 8004810: f006 fec7 bl 800b5a2 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); 8004814: f44f 6000 mov.w r0, #2048 @ 0x800 8004818: f006 fec3 bl 800b5a2 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); 800481c: f44f 5080 mov.w r0, #4096 @ 0x1000 8004820: f006 febf bl 800b5a2 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13); 8004824: f44f 5000 mov.w r0, #8192 @ 0x2000 8004828: f006 febb bl 800b5a2 /* USER CODE BEGIN EXTI15_10_IRQn 1 */ /* USER CODE END EXTI15_10_IRQn 1 */ } 800482c: bf00 nop 800482e: bd80 pop {r7, pc} 08004830 : /** * @brief This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 8004830: b580 push {r7, lr} 8004832: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ if (hdac1.State != HAL_DAC_STATE_RESET) { 8004834: 4b06 ldr r3, [pc, #24] @ (8004850 ) 8004836: 791b ldrb r3, [r3, #4] 8004838: b2db uxtb r3, r3 800483a: 2b00 cmp r3, #0 800483c: d002 beq.n 8004844 HAL_DAC_IRQHandler(&hdac1); 800483e: 4804 ldr r0, [pc, #16] @ (8004850 ) 8004840: f003 fca1 bl 8008186 } HAL_TIM_IRQHandler(&htim6); 8004844: 4803 ldr r0, [pc, #12] @ (8004854 ) 8004846: f00b fac9 bl 800fddc /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 800484a: bf00 nop 800484c: bd80 pop {r7, pc} 800484e: bf00 nop 8004850: 24000404 .word 0x24000404 8004854: 24000920 .word 0x24000920 08004858 : /** * @brief This function handles UART8 global interrupt. */ void UART8_IRQHandler(void) { 8004858: b580 push {r7, lr} 800485a: af00 add r7, sp, #0 /* USER CODE BEGIN UART8_IRQn 0 */ /* USER CODE END UART8_IRQn 0 */ HAL_UART_IRQHandler(&huart8); 800485c: 4802 ldr r0, [pc, #8] @ (8004868 ) 800485e: f00c fe81 bl 8011564 /* USER CODE BEGIN UART8_IRQn 1 */ /* USER CODE END UART8_IRQn 1 */ } 8004862: bf00 nop 8004864: bd80 pop {r7, pc} 8004866: bf00 nop 8004868: 240005b8 .word 0x240005b8 0800486c : * configuration. * @param None * @retval None */ void SystemInit (void) { 800486c: b480 push {r7} 800486e: af00 add r7, sp, #0 __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8004870: 4b37 ldr r3, [pc, #220] @ (8004950 ) 8004872: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004876: 4a36 ldr r2, [pc, #216] @ (8004950 ) 8004878: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 800487c: f8c2 3088 str.w r3, [r2, #136] @ 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8004880: 4b34 ldr r3, [pc, #208] @ (8004954 ) 8004882: 681b ldr r3, [r3, #0] 8004884: f003 030f and.w r3, r3, #15 8004888: 2b06 cmp r3, #6 800488a: d807 bhi.n 800489c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 800488c: 4b31 ldr r3, [pc, #196] @ (8004954 ) 800488e: 681b ldr r3, [r3, #0] 8004890: f023 030f bic.w r3, r3, #15 8004894: 4a2f ldr r2, [pc, #188] @ (8004954 ) 8004896: f043 0307 orr.w r3, r3, #7 800489a: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 800489c: 4b2e ldr r3, [pc, #184] @ (8004958 ) 800489e: 681b ldr r3, [r3, #0] 80048a0: 4a2d ldr r2, [pc, #180] @ (8004958 ) 80048a2: f043 0301 orr.w r3, r3, #1 80048a6: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 80048a8: 4b2b ldr r3, [pc, #172] @ (8004958 ) 80048aa: 2200 movs r2, #0 80048ac: 611a str r2, [r3, #16] /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 80048ae: 4b2a ldr r3, [pc, #168] @ (8004958 ) 80048b0: 681a ldr r2, [r3, #0] 80048b2: 4929 ldr r1, [pc, #164] @ (8004958 ) 80048b4: 4b29 ldr r3, [pc, #164] @ (800495c ) 80048b6: 4013 ands r3, r2 80048b8: 600b str r3, [r1, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 80048ba: 4b26 ldr r3, [pc, #152] @ (8004954 ) 80048bc: 681b ldr r3, [r3, #0] 80048be: f003 0308 and.w r3, r3, #8 80048c2: 2b00 cmp r3, #0 80048c4: d007 beq.n 80048d6 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 80048c6: 4b23 ldr r3, [pc, #140] @ (8004954 ) 80048c8: 681b ldr r3, [r3, #0] 80048ca: f023 030f bic.w r3, r3, #15 80048ce: 4a21 ldr r2, [pc, #132] @ (8004954 ) 80048d0: f043 0307 orr.w r3, r3, #7 80048d4: 6013 str r3, [r2, #0] } #if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; 80048d6: 4b20 ldr r3, [pc, #128] @ (8004958 ) 80048d8: 2200 movs r2, #0 80048da: 619a str r2, [r3, #24] /* Reset D2CFGR register */ RCC->D2CFGR = 0x00000000; 80048dc: 4b1e ldr r3, [pc, #120] @ (8004958 ) 80048de: 2200 movs r2, #0 80048e0: 61da str r2, [r3, #28] /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; 80048e2: 4b1d ldr r3, [pc, #116] @ (8004958 ) 80048e4: 2200 movs r2, #0 80048e6: 621a str r2, [r3, #32] /* Reset SRDCFGR register */ RCC->SRDCFGR = 0x00000000; #endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; 80048e8: 4b1b ldr r3, [pc, #108] @ (8004958 ) 80048ea: 4a1d ldr r2, [pc, #116] @ (8004960 ) 80048ec: 629a str r2, [r3, #40] @ 0x28 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; 80048ee: 4b1a ldr r3, [pc, #104] @ (8004958 ) 80048f0: 4a1c ldr r2, [pc, #112] @ (8004964 ) 80048f2: 62da str r2, [r3, #44] @ 0x2c /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 80048f4: 4b18 ldr r3, [pc, #96] @ (8004958 ) 80048f6: 4a1c ldr r2, [pc, #112] @ (8004968 ) 80048f8: 631a str r2, [r3, #48] @ 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 80048fa: 4b17 ldr r3, [pc, #92] @ (8004958 ) 80048fc: 2200 movs r2, #0 80048fe: 635a str r2, [r3, #52] @ 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 8004900: 4b15 ldr r3, [pc, #84] @ (8004958 ) 8004902: 4a19 ldr r2, [pc, #100] @ (8004968 ) 8004904: 639a str r2, [r3, #56] @ 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 8004906: 4b14 ldr r3, [pc, #80] @ (8004958 ) 8004908: 2200 movs r2, #0 800490a: 63da str r2, [r3, #60] @ 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 800490c: 4b12 ldr r3, [pc, #72] @ (8004958 ) 800490e: 4a16 ldr r2, [pc, #88] @ (8004968 ) 8004910: 641a str r2, [r3, #64] @ 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 8004912: 4b11 ldr r3, [pc, #68] @ (8004958 ) 8004914: 2200 movs r2, #0 8004916: 645a str r2, [r3, #68] @ 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8004918: 4b0f ldr r3, [pc, #60] @ (8004958 ) 800491a: 681b ldr r3, [r3, #0] 800491c: 4a0e ldr r2, [pc, #56] @ (8004958 ) 800491e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8004922: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 8004924: 4b0c ldr r3, [pc, #48] @ (8004958 ) 8004926: 2200 movs r2, #0 8004928: 661a str r2, [r3, #96] @ 0x60 #if (STM32H7_DEV_ID == 0x450UL) /* dual core CM7 or single core line */ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) 800492a: 4b10 ldr r3, [pc, #64] @ (800496c ) 800492c: 681a ldr r2, [r3, #0] 800492e: 4b10 ldr r3, [pc, #64] @ (8004970 ) 8004930: 4013 ands r3, r2 8004932: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004936: d202 bcs.n 800493e { /* if stm32h7 revY*/ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; 8004938: 4b0e ldr r3, [pc, #56] @ (8004974 ) 800493a: 2201 movs r2, #1 800493c: 601a str r2, [r3, #0] /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 800493e: 4b0e ldr r3, [pc, #56] @ (8004978 ) 8004940: f243 02d2 movw r2, #12498 @ 0x30d2 8004944: 601a str r2, [r3, #0] #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ } 8004946: bf00 nop 8004948: 46bd mov sp, r7 800494a: f85d 7b04 ldr.w r7, [sp], #4 800494e: 4770 bx lr 8004950: e000ed00 .word 0xe000ed00 8004954: 52002000 .word 0x52002000 8004958: 58024400 .word 0x58024400 800495c: eaf6ed7f .word 0xeaf6ed7f 8004960: 02020200 .word 0x02020200 8004964: 01ff0000 .word 0x01ff0000 8004968: 01010280 .word 0x01010280 800496c: 5c001000 .word 0x5c001000 8004970: ffff0000 .word 0xffff0000 8004974: 51008108 .word 0x51008108 8004978: 52004000 .word 0x52004000 0800497c <__NVIC_SystemReset>: { 800497c: b480 push {r7} 800497e: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 8004980: f3bf 8f4f dsb sy } 8004984: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 8004986: 4b06 ldr r3, [pc, #24] @ (80049a0 <__NVIC_SystemReset+0x24>) 8004988: 68db ldr r3, [r3, #12] 800498a: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800498e: 4904 ldr r1, [pc, #16] @ (80049a0 <__NVIC_SystemReset+0x24>) 8004990: 4b04 ldr r3, [pc, #16] @ (80049a4 <__NVIC_SystemReset+0x28>) 8004992: 4313 orrs r3, r2 8004994: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 8004996: f3bf 8f4f dsb sy } 800499a: bf00 nop __NOP(); 800499c: bf00 nop 800499e: e7fd b.n 800499c <__NVIC_SystemReset+0x20> 80049a0: e000ed00 .word 0xe000ed00 80049a4: 05fa0004 .word 0x05fa0004 080049a8 : uint8_t outputDataBuffer[OUTPUT_DATA_BUFF_SIZE]; uint16_t outputDataBufferPos = 0; extern RNG_HandleTypeDef hrng; void UartTasksInit (void) { 80049a8: b580 push {r7, lr} 80049aa: af00 add r7, sp, #0 uart1TaskData.uartRxBuffer = uart1RxBuffer; 80049ac: 4b24 ldr r3, [pc, #144] @ (8004a40 ) 80049ae: 4a25 ldr r2, [pc, #148] @ (8004a44 ) 80049b0: 601a str r2, [r3, #0] uart1TaskData.uartRxBufferLen = UART1_RX_BUFF_SIZE; 80049b2: 4b23 ldr r3, [pc, #140] @ (8004a40 ) 80049b4: f44f 7280 mov.w r2, #256 @ 0x100 80049b8: 809a strh r2, [r3, #4] uart1TaskData.uartTxBuffer = uart1TxBuffer; 80049ba: 4b21 ldr r3, [pc, #132] @ (8004a40 ) 80049bc: 4a22 ldr r2, [pc, #136] @ (8004a48 ) 80049be: 609a str r2, [r3, #8] uart1TaskData.uartRxBufferLen = UART1_TX_BUFF_SIZE; 80049c0: 4b1f ldr r3, [pc, #124] @ (8004a40 ) 80049c2: f44f 7280 mov.w r2, #256 @ 0x100 80049c6: 809a strh r2, [r3, #4] uart1TaskData.frameData = uart1TaskFrameData; 80049c8: 4b1d ldr r3, [pc, #116] @ (8004a40 ) 80049ca: 4a20 ldr r2, [pc, #128] @ (8004a4c ) 80049cc: 611a str r2, [r3, #16] uart1TaskData.frameDataLen = UART1_RX_BUFF_SIZE; 80049ce: 4b1c ldr r3, [pc, #112] @ (8004a40 ) 80049d0: f44f 7280 mov.w r2, #256 @ 0x100 80049d4: 829a strh r2, [r3, #20] uart1TaskData.huart = &huart1; 80049d6: 4b1a ldr r3, [pc, #104] @ (8004a40 ) 80049d8: 4a1d ldr r2, [pc, #116] @ (8004a50 ) 80049da: 631a str r2, [r3, #48] @ 0x30 uart1TaskData.uartNumber = 1; 80049dc: 4b18 ldr r3, [pc, #96] @ (8004a40 ) 80049de: 2201 movs r2, #1 80049e0: f883 2034 strb.w r2, [r3, #52] @ 0x34 uart1TaskData.processDataCb = Uart1ReceivedDataProcessCallback; 80049e4: 4b16 ldr r3, [pc, #88] @ (8004a40 ) 80049e6: 4a1b ldr r2, [pc, #108] @ (8004a54 ) 80049e8: 629a str r2, [r3, #40] @ 0x28 uart1TaskData.processRxDataMsgBuffer = NULL; 80049ea: 4b15 ldr r3, [pc, #84] @ (8004a40 ) 80049ec: 2200 movs r2, #0 80049ee: 625a str r2, [r3, #36] @ 0x24 uart8TaskData.uartRxBuffer = uart8RxBuffer; 80049f0: 4b19 ldr r3, [pc, #100] @ (8004a58 ) 80049f2: 4a1a ldr r2, [pc, #104] @ (8004a5c ) 80049f4: 601a str r2, [r3, #0] uart8TaskData.uartRxBufferLen = UART8_RX_BUFF_SIZE; 80049f6: 4b18 ldr r3, [pc, #96] @ (8004a58 ) 80049f8: f44f 7280 mov.w r2, #256 @ 0x100 80049fc: 809a strh r2, [r3, #4] uart8TaskData.uartTxBuffer = uart8TxBuffer; 80049fe: 4b16 ldr r3, [pc, #88] @ (8004a58 ) 8004a00: 4a17 ldr r2, [pc, #92] @ (8004a60 ) 8004a02: 609a str r2, [r3, #8] uart8TaskData.uartRxBufferLen = UART8_TX_BUFF_SIZE; 8004a04: 4b14 ldr r3, [pc, #80] @ (8004a58 ) 8004a06: f44f 7280 mov.w r2, #256 @ 0x100 8004a0a: 809a strh r2, [r3, #4] uart8TaskData.frameData = uart8TaskFrameData; 8004a0c: 4b12 ldr r3, [pc, #72] @ (8004a58 ) 8004a0e: 4a15 ldr r2, [pc, #84] @ (8004a64 ) 8004a10: 611a str r2, [r3, #16] uart8TaskData.frameDataLen = UART8_RX_BUFF_SIZE; 8004a12: 4b11 ldr r3, [pc, #68] @ (8004a58 ) 8004a14: f44f 7280 mov.w r2, #256 @ 0x100 8004a18: 829a strh r2, [r3, #20] uart8TaskData.huart = &huart8; 8004a1a: 4b0f ldr r3, [pc, #60] @ (8004a58 ) 8004a1c: 4a12 ldr r2, [pc, #72] @ (8004a68 ) 8004a1e: 631a str r2, [r3, #48] @ 0x30 uart8TaskData.uartNumber = 8; 8004a20: 4b0d ldr r3, [pc, #52] @ (8004a58 ) 8004a22: 2208 movs r2, #8 8004a24: f883 2034 strb.w r2, [r3, #52] @ 0x34 uart8TaskData.processDataCb = Uart8ReceivedDataProcessCallback; 8004a28: 4b0b ldr r3, [pc, #44] @ (8004a58 ) 8004a2a: 4a10 ldr r2, [pc, #64] @ (8004a6c ) 8004a2c: 629a str r2, [r3, #40] @ 0x28 uart8TaskData.processRxDataMsgBuffer = NULL; 8004a2e: 4b0a ldr r3, [pc, #40] @ (8004a58 ) 8004a30: 2200 movs r2, #0 8004a32: 625a str r2, [r3, #36] @ 0x24 #ifdef USE_UART8_INSTEAD_UART1 UartTaskCreate (&uart8TaskData); #else UartTaskCreate (&uart1TaskData); 8004a34: 4802 ldr r0, [pc, #8] @ (8004a40 ) 8004a36: f000 f81b bl 8004a70 #endif } 8004a3a: bf00 nop 8004a3c: bd80 pop {r7, pc} 8004a3e: bf00 nop 8004a40: 24000f6c .word 0x24000f6c 8004a44: 2400096c .word 0x2400096c 8004a48: 24000a6c .word 0x24000a6c 8004a4c: 24000b6c .word 0x24000b6c 8004a50: 2400064c .word 0x2400064c 8004a54: 08005119 .word 0x08005119 8004a58: 24000fa4 .word 0x24000fa4 8004a5c: 24000c6c .word 0x24000c6c 8004a60: 24000d6c .word 0x24000d6c 8004a64: 24000e6c .word 0x24000e6c 8004a68: 240005b8 .word 0x240005b8 8004a6c: 080050fd .word 0x080050fd 08004a70 : void UartTaskCreate (UartTaskData* uartTaskData) { 8004a70: b580 push {r7, lr} 8004a72: b08c sub sp, #48 @ 0x30 8004a74: af00 add r7, sp, #0 8004a76: 6078 str r0, [r7, #4] osThreadAttr_t osThreadAttrRxUart = { 0 }; 8004a78: f107 030c add.w r3, r7, #12 8004a7c: 2224 movs r2, #36 @ 0x24 8004a7e: 2100 movs r1, #0 8004a80: 4618 mov r0, r3 8004a82: f013 fc31 bl 80182e8 osThreadAttrRxUart.stack_size = configMINIMAL_STACK_SIZE * 2; 8004a86: f44f 6380 mov.w r3, #1024 @ 0x400 8004a8a: 623b str r3, [r7, #32] osThreadAttrRxUart.priority = (osPriority_t)osPriorityHigh; 8004a8c: 2328 movs r3, #40 @ 0x28 8004a8e: 627b str r3, [r7, #36] @ 0x24 uartTaskData->uartRecieveTaskHandle = osThreadNew (UartRxTask, uartTaskData, &osThreadAttrRxUart); 8004a90: f107 030c add.w r3, r7, #12 8004a94: 461a mov r2, r3 8004a96: 6879 ldr r1, [r7, #4] 8004a98: 4804 ldr r0, [pc, #16] @ (8004aac ) 8004a9a: f00f fad1 bl 8014040 8004a9e: 4602 mov r2, r0 8004aa0: 687b ldr r3, [r7, #4] 8004aa2: 619a str r2, [r3, #24] } 8004aa4: bf00 nop 8004aa6: 3730 adds r7, #48 @ 0x30 8004aa8: 46bd mov sp, r7 8004aaa: bd80 pop {r7, pc} 8004aac: 08004bc5 .word 0x08004bc5 08004ab0 : void HAL_UART_RxCpltCallback (UART_HandleTypeDef* huart) { 8004ab0: b480 push {r7} 8004ab2: b083 sub sp, #12 8004ab4: af00 add r7, sp, #0 8004ab6: 6078 str r0, [r7, #4] } 8004ab8: bf00 nop 8004aba: 370c adds r7, #12 8004abc: 46bd mov sp, r7 8004abe: f85d 7b04 ldr.w r7, [sp], #4 8004ac2: 4770 bx lr 08004ac4 : void HAL_UARTEx_RxEventCallback (UART_HandleTypeDef* huart, uint16_t Size) { 8004ac4: b580 push {r7, lr} 8004ac6: b082 sub sp, #8 8004ac8: af00 add r7, sp, #0 8004aca: 6078 str r0, [r7, #4] 8004acc: 460b mov r3, r1 8004ace: 807b strh r3, [r7, #2] if (huart->Instance == USART1) { 8004ad0: 687b ldr r3, [r7, #4] 8004ad2: 681b ldr r3, [r3, #0] 8004ad4: 4a0c ldr r2, [pc, #48] @ (8004b08 ) 8004ad6: 4293 cmp r3, r2 8004ad8: d106 bne.n 8004ae8 HandleUartRxCallback (&uart1TaskData, huart, Size); 8004ada: 887b ldrh r3, [r7, #2] 8004adc: 461a mov r2, r3 8004ade: 6879 ldr r1, [r7, #4] 8004ae0: 480a ldr r0, [pc, #40] @ (8004b0c ) 8004ae2: f000 f823 bl 8004b2c } else if (huart->Instance == UART8) { HandleUartRxCallback (&uart8TaskData, huart, Size); } } 8004ae6: e00a b.n 8004afe } else if (huart->Instance == UART8) { 8004ae8: 687b ldr r3, [r7, #4] 8004aea: 681b ldr r3, [r3, #0] 8004aec: 4a08 ldr r2, [pc, #32] @ (8004b10 ) 8004aee: 4293 cmp r3, r2 8004af0: d105 bne.n 8004afe HandleUartRxCallback (&uart8TaskData, huart, Size); 8004af2: 887b ldrh r3, [r7, #2] 8004af4: 461a mov r2, r3 8004af6: 6879 ldr r1, [r7, #4] 8004af8: 4806 ldr r0, [pc, #24] @ (8004b14 ) 8004afa: f000 f817 bl 8004b2c } 8004afe: bf00 nop 8004b00: 3708 adds r7, #8 8004b02: 46bd mov sp, r7 8004b04: bd80 pop {r7, pc} 8004b06: bf00 nop 8004b08: 40011000 .word 0x40011000 8004b0c: 24000f6c .word 0x24000f6c 8004b10: 40007c00 .word 0x40007c00 8004b14: 24000fa4 .word 0x24000fa4 08004b18 : void HAL_UART_TxCpltCallback (UART_HandleTypeDef* huart) { 8004b18: b480 push {r7} 8004b1a: b083 sub sp, #12 8004b1c: af00 add r7, sp, #0 8004b1e: 6078 str r0, [r7, #4] if (huart->Instance == UART8) { } } 8004b20: bf00 nop 8004b22: 370c adds r7, #12 8004b24: 46bd mov sp, r7 8004b26: f85d 7b04 ldr.w r7, [sp], #4 8004b2a: 4770 bx lr 08004b2c : void HandleUartRxCallback (UartTaskData* uartTaskData, UART_HandleTypeDef* huart, uint16_t Size) { 8004b2c: b580 push {r7, lr} 8004b2e: b088 sub sp, #32 8004b30: af02 add r7, sp, #8 8004b32: 60f8 str r0, [r7, #12] 8004b34: 60b9 str r1, [r7, #8] 8004b36: 4613 mov r3, r2 8004b38: 80fb strh r3, [r7, #6] BaseType_t pxHigherPriorityTaskWoken = pdFALSE; 8004b3a: 2300 movs r3, #0 8004b3c: 617b str r3, [r7, #20] osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004b3e: 68fb ldr r3, [r7, #12] 8004b40: 6a1b ldr r3, [r3, #32] 8004b42: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004b46: 4618 mov r0, r3 8004b48: f00f fca5 bl 8014496 memcpy (&(uartTaskData->frameData[uartTaskData->frameBytesCount]), uartTaskData->uartRxBuffer, Size); 8004b4c: 68fb ldr r3, [r7, #12] 8004b4e: 691b ldr r3, [r3, #16] 8004b50: 68fa ldr r2, [r7, #12] 8004b52: 8ad2 ldrh r2, [r2, #22] 8004b54: 1898 adds r0, r3, r2 8004b56: 68fb ldr r3, [r7, #12] 8004b58: 681b ldr r3, [r3, #0] 8004b5a: 88fa ldrh r2, [r7, #6] 8004b5c: 4619 mov r1, r3 8004b5e: f013 fc4d bl 80183fc uartTaskData->frameBytesCount += Size; 8004b62: 68fb ldr r3, [r7, #12] 8004b64: 8ada ldrh r2, [r3, #22] 8004b66: 88fb ldrh r3, [r7, #6] 8004b68: 4413 add r3, r2 8004b6a: b29a uxth r2, r3 8004b6c: 68fb ldr r3, [r7, #12] 8004b6e: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 8004b70: 68fb ldr r3, [r7, #12] 8004b72: 6a1b ldr r3, [r3, #32] 8004b74: 4618 mov r0, r3 8004b76: f00f fcd9 bl 801452c xTaskNotifyFromISR (uartTaskData->uartRecieveTaskHandle, Size, eSetValueWithOverwrite, &pxHigherPriorityTaskWoken); 8004b7a: 68fb ldr r3, [r7, #12] 8004b7c: 6998 ldr r0, [r3, #24] 8004b7e: 88f9 ldrh r1, [r7, #6] 8004b80: f107 0314 add.w r3, r7, #20 8004b84: 9300 str r3, [sp, #0] 8004b86: 2300 movs r3, #0 8004b88: 2203 movs r2, #3 8004b8a: f012 f9c9 bl 8016f20 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8004b8e: 68fb ldr r3, [r7, #12] 8004b90: 6b18 ldr r0, [r3, #48] @ 0x30 8004b92: 68fb ldr r3, [r7, #12] 8004b94: 6819 ldr r1, [r3, #0] 8004b96: 68fb ldr r3, [r7, #12] 8004b98: 889b ldrh r3, [r3, #4] 8004b9a: 461a mov r2, r3 8004b9c: f00f f923 bl 8013de6 portEND_SWITCHING_ISR (pxHigherPriorityTaskWoken); 8004ba0: 697b ldr r3, [r7, #20] 8004ba2: 2b00 cmp r3, #0 8004ba4: d007 beq.n 8004bb6 8004ba6: 4b06 ldr r3, [pc, #24] @ (8004bc0 ) 8004ba8: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8004bac: 601a str r2, [r3, #0] 8004bae: f3bf 8f4f dsb sy 8004bb2: f3bf 8f6f isb sy } 8004bb6: bf00 nop 8004bb8: 3718 adds r7, #24 8004bba: 46bd mov sp, r7 8004bbc: bd80 pop {r7, pc} 8004bbe: bf00 nop 8004bc0: e000ed04 .word 0xe000ed04 08004bc4 : void UartRxTask (void* argument) { 8004bc4: b580 push {r7, lr} 8004bc6: b0d2 sub sp, #328 @ 0x148 8004bc8: af02 add r7, sp, #8 8004bca: f507 73a0 add.w r3, r7, #320 @ 0x140 8004bce: f5a3 739e sub.w r3, r3, #316 @ 0x13c 8004bd2: 6018 str r0, [r3, #0] UartTaskData* uartTaskData = (UartTaskData*)argument; 8004bd4: f507 73a0 add.w r3, r7, #320 @ 0x140 8004bd8: f5a3 739e sub.w r3, r3, #316 @ 0x13c 8004bdc: 681b ldr r3, [r3, #0] 8004bde: f8c7 312c str.w r3, [r7, #300] @ 0x12c SerialProtocolFrameData spFrameData = { 0 }; 8004be2: f507 73a0 add.w r3, r7, #320 @ 0x140 8004be6: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004bea: 4618 mov r0, r3 8004bec: f44f 7386 mov.w r3, #268 @ 0x10c 8004bf0: 461a mov r2, r3 8004bf2: 2100 movs r1, #0 8004bf4: f013 fb78 bl 80182e8 uint32_t bytesRec = 0; 8004bf8: f507 73a0 add.w r3, r7, #320 @ 0x140 8004bfc: f5a3 739a sub.w r3, r3, #308 @ 0x134 8004c00: 2200 movs r2, #0 8004c02: 601a str r2, [r3, #0] uint32_t crc = 0; 8004c04: 2300 movs r3, #0 8004c06: f8c7 3128 str.w r3, [r7, #296] @ 0x128 uint16_t frameCommandRaw = 0x0000; 8004c0a: 2300 movs r3, #0 8004c0c: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 uint16_t frameBytesCount = 0; 8004c10: 2300 movs r3, #0 8004c12: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 uint16_t frameCrc = 0; 8004c16: 2300 movs r3, #0 8004c18: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 uint16_t frameTotalLength = 0; 8004c1c: 2300 movs r3, #0 8004c1e: f8a7 313e strh.w r3, [r7, #318] @ 0x13e uint16_t dataToSend = 0; 8004c22: 2300 movs r3, #0 8004c24: f8a7 313c strh.w r3, [r7, #316] @ 0x13c portBASE_TYPE crcPass = pdFAIL; 8004c28: 2300 movs r3, #0 8004c2a: f8c7 3138 str.w r3, [r7, #312] @ 0x138 portBASE_TYPE proceed = pdFALSE; 8004c2e: 2300 movs r3, #0 8004c30: f8c7 3134 str.w r3, [r7, #308] @ 0x134 portBASE_TYPE frameTimeout = pdFAIL; 8004c34: 2300 movs r3, #0 8004c36: f8c7 311c str.w r3, [r7, #284] @ 0x11c enum SerialReceiverStates receverState = srWaitForHeader; 8004c3a: 2300 movs r3, #0 8004c3c: f887 3133 strb.w r3, [r7, #307] @ 0x133 uartTaskData->rxDataBufferMutex = osMutexNew (NULL); 8004c40: 2000 movs r0, #0 8004c42: f00f fba2 bl 801438a 8004c46: 4602 mov r2, r0 8004c48: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c4c: 621a str r2, [r3, #32] HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8004c4e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c52: 6b18 ldr r0, [r3, #48] @ 0x30 8004c54: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c58: 6819 ldr r1, [r3, #0] 8004c5a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c5e: 889b ldrh r3, [r3, #4] 8004c60: 461a mov r2, r3 8004c62: f00f f8c0 bl 8013de6 while (pdTRUE) { frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8004c66: f107 020c add.w r2, r7, #12 8004c6a: f44f 63fa mov.w r3, #2000 @ 0x7d0 8004c6e: 2100 movs r1, #0 8004c70: 2000 movs r0, #0 8004c72: f012 f833 bl 8016cdc 8004c76: 4603 mov r3, r0 8004c78: 2b00 cmp r3, #0 8004c7a: bf0c ite eq 8004c7c: 2301 moveq r3, #1 8004c7e: 2300 movne r3, #0 8004c80: b2db uxtb r3, r3 8004c82: f8c7 311c str.w r3, [r7, #284] @ 0x11c osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004c86: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c8a: 6a1b ldr r3, [r3, #32] 8004c8c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004c90: 4618 mov r0, r3 8004c92: f00f fc00 bl 8014496 frameBytesCount = uartTaskData->frameBytesCount; 8004c96: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c9a: 8adb ldrh r3, [r3, #22] 8004c9c: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 osMutexRelease (uartTaskData->rxDataBufferMutex); 8004ca0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004ca4: 6a1b ldr r3, [r3, #32] 8004ca6: 4618 mov r0, r3 8004ca8: f00f fc40 bl 801452c if ((frameTimeout == pdTRUE) && (frameBytesCount > 0)) { 8004cac: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8004cb0: 2b01 cmp r3, #1 8004cb2: d10a bne.n 8004cca 8004cb4: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004cb8: 2b00 cmp r3, #0 8004cba: d006 beq.n 8004cca receverState = srFail; 8004cbc: 2304 movs r3, #4 8004cbe: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdTRUE; 8004cc2: 2301 movs r3, #1 8004cc4: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004cc8: e01b b.n 8004d02 } else { if (frameTimeout == pdFALSE) { 8004cca: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8004cce: 2b00 cmp r3, #0 8004cd0: d103 bne.n 8004cda proceed = pdTRUE; 8004cd2: 2301 movs r3, #1 8004cd4: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004cd8: e206 b.n 80050e8 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: RX bytes received: %ld\n", uartTaskData->uartNumber, bytesRec); #endif } else { if (uartTaskData->huart->RxState == HAL_UART_STATE_READY) { 8004cda: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004cde: 6b1b ldr r3, [r3, #48] @ 0x30 8004ce0: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004ce4: 2b20 cmp r3, #32 8004ce6: f040 81ff bne.w 80050e8 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8004cea: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004cee: 6b18 ldr r0, [r3, #48] @ 0x30 8004cf0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004cf4: 6819 ldr r1, [r3, #0] 8004cf6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004cfa: 889b ldrh r3, [r3, #4] 8004cfc: 461a mov r2, r3 8004cfe: f00f f872 bl 8013de6 } } } while (proceed) { 8004d02: e1f1 b.n 80050e8 switch (receverState) { 8004d04: f897 3133 ldrb.w r3, [r7, #307] @ 0x133 8004d08: 2b04 cmp r3, #4 8004d0a: f200 81c8 bhi.w 800509e 8004d0e: a201 add r2, pc, #4 @ (adr r2, 8004d14 ) 8004d10: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004d14: 08004d29 .word 0x08004d29 8004d18: 08004e8b .word 0x08004e8b 8004d1c: 08004e6f .word 0x08004e6f 8004d20: 08004f1b .word 0x08004f1b 8004d24: 08004fc7 .word 0x08004fc7 case srWaitForHeader: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004d28: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d2c: 6a1b ldr r3, [r3, #32] 8004d2e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004d32: 4618 mov r0, r3 8004d34: f00f fbaf bl 8014496 if (uartTaskData->frameData[0] == FRAME_INDICATOR) { 8004d38: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d3c: 691b ldr r3, [r3, #16] 8004d3e: 781b ldrb r3, [r3, #0] 8004d40: 2baa cmp r3, #170 @ 0xaa 8004d42: f040 8082 bne.w 8004e4a if (frameBytesCount > FRAME_ID_LENGTH) { 8004d46: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004d4a: 2b02 cmp r3, #2 8004d4c: d914 bls.n 8004d78 spFrameData.frameHeader.frameId = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_ID_LENGTH - FRAME_COMMAND_LENGTH])); 8004d4e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d52: 691b ldr r3, [r3, #16] 8004d54: 3302 adds r3, #2 8004d56: 781b ldrb r3, [r3, #0] 8004d58: 021b lsls r3, r3, #8 8004d5a: b21a sxth r2, r3 8004d5c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d60: 691b ldr r3, [r3, #16] 8004d62: 3301 adds r3, #1 8004d64: 781b ldrb r3, [r3, #0] 8004d66: b21b sxth r3, r3 8004d68: 4313 orrs r3, r2 8004d6a: b21b sxth r3, r3 8004d6c: b29a uxth r2, r3 spFrameData.frameHeader.frameId = 8004d6e: f507 73a0 add.w r3, r7, #320 @ 0x140 8004d72: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004d76: 801a strh r2, [r3, #0] } if (frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH) { 8004d78: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004d7c: 2b04 cmp r3, #4 8004d7e: d923 bls.n 8004dc8 frameCommandRaw = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_COMMAND_LENGTH])); 8004d80: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d84: 691b ldr r3, [r3, #16] 8004d86: 3304 adds r3, #4 8004d88: 781b ldrb r3, [r3, #0] 8004d8a: 021b lsls r3, r3, #8 8004d8c: b21a sxth r2, r3 8004d8e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d92: 691b ldr r3, [r3, #16] 8004d94: 3303 adds r3, #3 8004d96: 781b ldrb r3, [r3, #0] 8004d98: b21b sxth r3, r3 8004d9a: 4313 orrs r3, r2 8004d9c: b21b sxth r3, r3 8004d9e: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 spFrameData.frameHeader.frameCommand = (SerialProtocolCommands)(frameCommandRaw & 0x7FFF); 8004da2: f8b7 3126 ldrh.w r3, [r7, #294] @ 0x126 8004da6: b2da uxtb r2, r3 8004da8: f507 73a0 add.w r3, r7, #320 @ 0x140 8004dac: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004db0: 709a strb r2, [r3, #2] spFrameData.frameHeader.isResponseFrame = (frameCommandRaw & 0x8000) != 0 ? pdTRUE : pdFALSE; 8004db2: f9b7 3126 ldrsh.w r3, [r7, #294] @ 0x126 8004db6: 13db asrs r3, r3, #15 8004db8: b21b sxth r3, r3 8004dba: f003 0201 and.w r2, r3, #1 8004dbe: f507 73a0 add.w r3, r7, #320 @ 0x140 8004dc2: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004dc6: 609a str r2, [r3, #8] } if ((frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH) && ((spFrameData.frameHeader.frameCommand & 0x8000) != 0)) { 8004dc8: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004dcc: 2b05 cmp r3, #5 8004dce: d913 bls.n 8004df8 8004dd0: f507 73a0 add.w r3, r7, #320 @ 0x140 8004dd4: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004dd8: 789b ldrb r3, [r3, #2] 8004dda: f403 4300 and.w r3, r3, #32768 @ 0x8000 8004dde: 2b00 cmp r3, #0 8004de0: d00a beq.n 8004df8 spFrameData.frameHeader.respStatus = (SerialProtocolRespStatus)(uartTaskData->frameData[FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH]); 8004de2: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004de6: 691b ldr r3, [r3, #16] 8004de8: 3305 adds r3, #5 8004dea: 781b ldrb r3, [r3, #0] 8004dec: b25a sxtb r2, r3 8004dee: f507 73a0 add.w r3, r7, #320 @ 0x140 8004df2: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004df6: 70da strb r2, [r3, #3] } if (frameBytesCount >= FRAME_HEADER_LENGTH) { 8004df8: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004dfc: 2b07 cmp r3, #7 8004dfe: d920 bls.n 8004e42 spFrameData.frameHeader.frameDataLength = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH])); 8004e00: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e04: 691b ldr r3, [r3, #16] 8004e06: 3306 adds r3, #6 8004e08: 781b ldrb r3, [r3, #0] 8004e0a: 021b lsls r3, r3, #8 8004e0c: b21a sxth r2, r3 8004e0e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e12: 691b ldr r3, [r3, #16] 8004e14: 3305 adds r3, #5 8004e16: 781b ldrb r3, [r3, #0] 8004e18: b21b sxth r3, r3 8004e1a: 4313 orrs r3, r2 8004e1c: b21b sxth r3, r3 8004e1e: b29a uxth r2, r3 8004e20: f507 73a0 add.w r3, r7, #320 @ 0x140 8004e24: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004e28: 809a strh r2, [r3, #4] frameTotalLength = FRAME_HEADER_LENGTH + spFrameData.frameHeader.frameDataLength + FRAME_CRC_LENGTH; 8004e2a: f507 73a0 add.w r3, r7, #320 @ 0x140 8004e2e: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004e32: 889b ldrh r3, [r3, #4] 8004e34: 330a adds r3, #10 8004e36: f8a7 313e strh.w r3, [r7, #318] @ 0x13e receverState = srRecieveData; 8004e3a: 2302 movs r3, #2 8004e3c: f887 3133 strb.w r3, [r7, #307] @ 0x133 8004e40: e00e b.n 8004e60 } else { proceed = pdFALSE; 8004e42: 2300 movs r3, #0 8004e44: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004e48: e00a b.n 8004e60 } } else { if (frameBytesCount > 0) { 8004e4a: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004e4e: 2b00 cmp r3, #0 8004e50: d003 beq.n 8004e5a receverState = srFail; 8004e52: 2304 movs r3, #4 8004e54: f887 3133 strb.w r3, [r7, #307] @ 0x133 8004e58: e002 b.n 8004e60 } else { proceed = pdFALSE; 8004e5a: 2300 movs r3, #0 8004e5c: f8c7 3134 str.w r3, [r7, #308] @ 0x134 } } osMutexRelease (uartTaskData->rxDataBufferMutex); 8004e60: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e64: 6a1b ldr r3, [r3, #32] 8004e66: 4618 mov r0, r3 8004e68: f00f fb60 bl 801452c break; 8004e6c: e13c b.n 80050e8 case srRecieveData: if (frameBytesCount >= frameTotalLength) { 8004e6e: f8b7 2124 ldrh.w r2, [r7, #292] @ 0x124 8004e72: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004e76: 429a cmp r2, r3 8004e78: d303 bcc.n 8004e82 receverState = srCheckCrc; 8004e7a: 2301 movs r3, #1 8004e7c: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { proceed = pdFALSE; } break; 8004e80: e132 b.n 80050e8 proceed = pdFALSE; 8004e82: 2300 movs r3, #0 8004e84: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 8004e88: e12e b.n 80050e8 case srCheckCrc: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004e8a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e8e: 6a1b ldr r3, [r3, #32] 8004e90: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004e94: 4618 mov r0, r3 8004e96: f00f fafe bl 8014496 frameCrc = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[frameTotalLength - FRAME_CRC_LENGTH])); 8004e9a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e9e: 691a ldr r2, [r3, #16] 8004ea0: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004ea4: 3b01 subs r3, #1 8004ea6: 4413 add r3, r2 8004ea8: 781b ldrb r3, [r3, #0] 8004eaa: 021b lsls r3, r3, #8 8004eac: b21a sxth r2, r3 8004eae: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004eb2: 6919 ldr r1, [r3, #16] 8004eb4: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004eb8: 3b02 subs r3, #2 8004eba: 440b add r3, r1 8004ebc: 781b ldrb r3, [r3, #0] 8004ebe: b21b sxth r3, r3 8004ec0: 4313 orrs r3, r2 8004ec2: b21b sxth r3, r3 8004ec4: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)(uartTaskData->frameData), frameTotalLength - FRAME_CRC_LENGTH); 8004ec8: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004ecc: 6919 ldr r1, [r3, #16] 8004ece: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004ed2: 3b02 subs r3, #2 8004ed4: 461a mov r2, r3 8004ed6: 4887 ldr r0, [pc, #540] @ (80050f4 ) 8004ed8: f002 ff3a bl 8007d50 8004edc: f8c7 0128 str.w r0, [r7, #296] @ 0x128 osMutexRelease (uartTaskData->rxDataBufferMutex); 8004ee0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004ee4: 6a1b ldr r3, [r3, #32] 8004ee6: 4618 mov r0, r3 8004ee8: f00f fb20 bl 801452c crcPass = frameCrc == crc; 8004eec: f8b7 3122 ldrh.w r3, [r7, #290] @ 0x122 8004ef0: f8d7 2128 ldr.w r2, [r7, #296] @ 0x128 8004ef4: 429a cmp r2, r3 8004ef6: bf0c ite eq 8004ef8: 2301 moveq r3, #1 8004efa: 2300 movne r3, #0 8004efc: b2db uxtb r3, r3 8004efe: f8c7 3138 str.w r3, [r7, #312] @ 0x138 if (crcPass) { 8004f02: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 8004f06: 2b00 cmp r3, #0 8004f08: d003 beq.n 8004f12 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: Frame CRC PASS\n", uartTaskData->uartNumber); #endif receverState = srExecuteCmd; 8004f0a: 2303 movs r3, #3 8004f0c: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { receverState = srFail; } break; 8004f10: e0ea b.n 80050e8 receverState = srFail; 8004f12: 2304 movs r3, #4 8004f14: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004f18: e0e6 b.n 80050e8 case srExecuteCmd: if ((uartTaskData->processDataCb != NULL) || (uartTaskData->processRxDataMsgBuffer != NULL)) { 8004f1a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f1e: 6a9b ldr r3, [r3, #40] @ 0x28 8004f20: 2b00 cmp r3, #0 8004f22: d104 bne.n 8004f2e 8004f24: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f28: 6a5b ldr r3, [r3, #36] @ 0x24 8004f2a: 2b00 cmp r3, #0 8004f2c: d01e beq.n 8004f6c osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004f2e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f32: 6a1b ldr r3, [r3, #32] 8004f34: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004f38: 4618 mov r0, r3 8004f3a: f00f faac bl 8014496 memcpy (spFrameData.dataBuffer, &(uartTaskData->frameData[FRAME_HEADER_LENGTH]), spFrameData.frameHeader.frameDataLength); 8004f3e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f42: 691b ldr r3, [r3, #16] 8004f44: f103 0108 add.w r1, r3, #8 8004f48: f507 73a0 add.w r3, r7, #320 @ 0x140 8004f4c: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004f50: 889b ldrh r3, [r3, #4] 8004f52: 461a mov r2, r3 8004f54: f107 0310 add.w r3, r7, #16 8004f58: 330c adds r3, #12 8004f5a: 4618 mov r0, r3 8004f5c: f013 fa4e bl 80183fc osMutexRelease (uartTaskData->rxDataBufferMutex); 8004f60: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f64: 6a1b ldr r3, [r3, #32] 8004f66: 4618 mov r0, r3 8004f68: f00f fae0 bl 801452c } if (uartTaskData->processRxDataMsgBuffer != NULL) { 8004f6c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f70: 6a5b ldr r3, [r3, #36] @ 0x24 8004f72: 2b00 cmp r3, #0 8004f74: d015 beq.n 8004fa2 if (xMessageBufferSend (uartTaskData->processRxDataMsgBuffer, &spFrameData, sizeof (SerialProtocolFrameHeader) + spFrameData.frameHeader.frameDataLength, pdMS_TO_TICKS (200)) == pdFALSE) { 8004f76: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f7a: 6a58 ldr r0, [r3, #36] @ 0x24 8004f7c: f507 73a0 add.w r3, r7, #320 @ 0x140 8004f80: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004f84: 889b ldrh r3, [r3, #4] 8004f86: f103 020c add.w r2, r3, #12 8004f8a: f107 0110 add.w r1, r7, #16 8004f8e: 23c8 movs r3, #200 @ 0xc8 8004f90: f010 fcee bl 8015970 8004f94: 4603 mov r3, r0 8004f96: 2b00 cmp r3, #0 8004f98: d103 bne.n 8004fa2 receverState = srFail; 8004f9a: 2304 movs r3, #4 8004f9c: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004fa0: e0a2 b.n 80050e8 } } if (uartTaskData->processDataCb != NULL) { 8004fa2: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004fa6: 6a9b ldr r3, [r3, #40] @ 0x28 8004fa8: 2b00 cmp r3, #0 8004faa: d008 beq.n 8004fbe uartTaskData->processDataCb (uartTaskData, &spFrameData); 8004fac: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004fb0: 6a9b ldr r3, [r3, #40] @ 0x28 8004fb2: f107 0210 add.w r2, r7, #16 8004fb6: 4611 mov r1, r2 8004fb8: f8d7 012c ldr.w r0, [r7, #300] @ 0x12c 8004fbc: 4798 blx r3 } receverState = srFinish; 8004fbe: 2305 movs r3, #5 8004fc0: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004fc4: e090 b.n 80050e8 case srFail: dataToSend = 0; 8004fc6: 2300 movs r3, #0 8004fc8: f8a7 313c strh.w r3, [r7, #316] @ 0x13c if ((frameTimeout == pdTRUE) && (frameBytesCount > 2)) { 8004fcc: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8004fd0: 2b01 cmp r3, #1 8004fd2: d11c bne.n 800500e 8004fd4: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004fd8: 2b02 cmp r3, #2 8004fda: d918 bls.n 800500e dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0); 8004fdc: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004fe0: 6898 ldr r0, [r3, #8] 8004fe2: f507 73a0 add.w r3, r7, #320 @ 0x140 8004fe6: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004fea: 8819 ldrh r1, [r3, #0] 8004fec: f507 73a0 add.w r3, r7, #320 @ 0x140 8004ff0: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004ff4: 789a ldrb r2, [r3, #2] 8004ff6: 2300 movs r3, #0 8004ff8: 9301 str r3, [sp, #4] 8004ffa: 2300 movs r3, #0 8004ffc: 9300 str r3, [sp, #0] 8004ffe: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8005002: f7fe fd57 bl 8003ab4 8005006: 4603 mov r3, r0 8005008: f8a7 313c strh.w r3, [r7, #316] @ 0x13c 800500c: e034 b.n 8005078 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: RX data receiver timeout!\n", uartTaskData->uartNumber); #endif } else if (!crcPass) { 800500e: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 8005012: 2b00 cmp r3, #0 8005014: d118 bne.n 8005048 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spCrcFail, NULL, 0); 8005016: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800501a: 6898 ldr r0, [r3, #8] 800501c: f507 73a0 add.w r3, r7, #320 @ 0x140 8005020: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8005024: 8819 ldrh r1, [r3, #0] 8005026: f507 73a0 add.w r3, r7, #320 @ 0x140 800502a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800502e: 789a ldrb r2, [r3, #2] 8005030: 2300 movs r3, #0 8005032: 9301 str r3, [sp, #4] 8005034: 2300 movs r3, #0 8005036: 9300 str r3, [sp, #0] 8005038: f06f 0301 mvn.w r3, #1 800503c: f7fe fd3a bl 8003ab4 8005040: 4603 mov r3, r0 8005042: f8a7 313c strh.w r3, [r7, #316] @ 0x13c 8005046: e017 b.n 8005078 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: Frame CRC FAIL\n", uartTaskData->uartNumber); #endif } else { dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spInternalError, NULL, 0); 8005048: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800504c: 6898 ldr r0, [r3, #8] 800504e: f507 73a0 add.w r3, r7, #320 @ 0x140 8005052: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8005056: 8819 ldrh r1, [r3, #0] 8005058: f507 73a0 add.w r3, r7, #320 @ 0x140 800505c: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8005060: 789a ldrb r2, [r3, #2] 8005062: 2300 movs r3, #0 8005064: 9301 str r3, [sp, #4] 8005066: 2300 movs r3, #0 8005068: 9300 str r3, [sp, #0] 800506a: f06f 0303 mvn.w r3, #3 800506e: f7fe fd21 bl 8003ab4 8005072: 4603 mov r3, r0 8005074: f8a7 313c strh.w r3, [r7, #316] @ 0x13c } if (dataToSend > 0) { 8005078: f8b7 313c ldrh.w r3, [r7, #316] @ 0x13c 800507c: 2b00 cmp r3, #0 800507e: d00a beq.n 8005096 HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 8005080: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8005084: 6b18 ldr r0, [r3, #48] @ 0x30 8005086: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800508a: 689b ldr r3, [r3, #8] 800508c: f8b7 213c ldrh.w r2, [r7, #316] @ 0x13c 8005090: 4619 mov r1, r3 8005092: f00c f9d3 bl 801143c } #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: TX bytes sent: %d\n", dataToSend, uartTaskData->uartNumber); #endif receverState = srFinish; 8005096: 2305 movs r3, #5 8005098: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 800509c: e024 b.n 80050e8 case srFinish: default: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 800509e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80050a2: 6a1b ldr r3, [r3, #32] 80050a4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80050a8: 4618 mov r0, r3 80050aa: f00f f9f4 bl 8014496 uartTaskData->frameBytesCount = 0; 80050ae: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80050b2: 2200 movs r2, #0 80050b4: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 80050b6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80050ba: 6a1b ldr r3, [r3, #32] 80050bc: 4618 mov r0, r3 80050be: f00f fa35 bl 801452c spFrameData.frameHeader.frameCommand = spUnknown; 80050c2: f507 73a0 add.w r3, r7, #320 @ 0x140 80050c6: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80050ca: 2212 movs r2, #18 80050cc: 709a strb r2, [r3, #2] frameTotalLength = 0; 80050ce: 2300 movs r3, #0 80050d0: f8a7 313e strh.w r3, [r7, #318] @ 0x13e outputDataBufferPos = 0; 80050d4: 4b08 ldr r3, [pc, #32] @ (80050f8 ) 80050d6: 2200 movs r2, #0 80050d8: 801a strh r2, [r3, #0] receverState = srWaitForHeader; 80050da: 2300 movs r3, #0 80050dc: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdFALSE; 80050e0: 2300 movs r3, #0 80050e2: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 80050e6: bf00 nop while (proceed) { 80050e8: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 80050ec: 2b00 cmp r3, #0 80050ee: f47f ae09 bne.w 8004d04 frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 80050f2: e5b8 b.n 8004c66 80050f4: 240003e0 .word 0x240003e0 80050f8: 2400105c .word 0x2400105c 080050fc : } } } } void Uart8ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 80050fc: b580 push {r7, lr} 80050fe: b082 sub sp, #8 8005100: af00 add r7, sp, #0 8005102: 6078 str r0, [r7, #4] 8005104: 6039 str r1, [r7, #0] Uart1ReceivedDataProcessCallback (arg, spFrameData); 8005106: 6839 ldr r1, [r7, #0] 8005108: 6878 ldr r0, [r7, #4] 800510a: f000 f805 bl 8005118 } 800510e: bf00 nop 8005110: 3708 adds r7, #8 8005112: 46bd mov sp, r7 8005114: bd80 pop {r7, pc} ... 08005118 : void Uart1ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 8005118: b590 push {r4, r7, lr} 800511a: b0ad sub sp, #180 @ 0xb4 800511c: af06 add r7, sp, #24 800511e: 6078 str r0, [r7, #4] 8005120: 6039 str r1, [r7, #0] UartTaskData* uartTaskData = (UartTaskData*)arg; 8005122: 687b ldr r3, [r7, #4] 8005124: 677b str r3, [r7, #116] @ 0x74 uint16_t dataToSend = 0; 8005126: 2300 movs r3, #0 8005128: f8a7 3072 strh.w r3, [r7, #114] @ 0x72 outputDataBufferPos = 0; 800512c: 4b64 ldr r3, [pc, #400] @ (80052c0 ) 800512e: 2200 movs r2, #0 8005130: 801a strh r2, [r3, #0] uint16_t inputDataBufferPos = 0; 8005132: 2300 movs r3, #0 8005134: f8a7 3044 strh.w r3, [r7, #68] @ 0x44 SerialProtocolRespStatus respStatus = spUnknownCommand; 8005138: 23fd movs r3, #253 @ 0xfd 800513a: f887 3097 strb.w r3, [r7, #151] @ 0x97 switch (spFrameData->frameHeader.frameCommand) { 800513e: 683b ldr r3, [r7, #0] 8005140: 789b ldrb r3, [r3, #2] 8005142: 2b11 cmp r3, #17 8005144: f200 85a2 bhi.w 8005c8c 8005148: a201 add r2, pc, #4 @ (adr r2, 8005150 ) 800514a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800514e: bf00 nop 8005150: 08005199 .word 0x08005199 8005154: 080052d1 .word 0x080052d1 8005158: 0800544b .word 0x0800544b 800515c: 08005581 .word 0x08005581 8005160: 08005623 .word 0x08005623 8005164: 08005741 .word 0x08005741 8005168: 08005797 .word 0x08005797 800516c: 080056c5 .word 0x080056c5 8005170: 080057ed .word 0x080057ed 8005174: 0800588d .word 0x0800588d 8005178: 080058d9 .word 0x080058d9 800517c: 08005925 .word 0x08005925 8005180: 08005987 .word 0x08005987 8005184: 080059eb .word 0x080059eb 8005188: 08005a4d .word 0x08005a4d 800518c: 08005ab1 .word 0x08005ab1 8005190: 08005ab9 .word 0x08005ab9 8005194: 08005bbd .word 0x08005bbd case spGetElectricalMeasurments: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005198: 4b4a ldr r3, [pc, #296] @ (80052c4 ) 800519a: 681b ldr r3, [r3, #0] 800519c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80051a0: 4618 mov r0, r3 80051a2: f00f f978 bl 8014496 80051a6: 4603 mov r3, r0 80051a8: 2b00 cmp r3, #0 80051aa: f040 8083 bne.w 80052b4 for (int i = 0; i < 3; i++) { 80051ae: 2300 movs r3, #0 80051b0: f8c7 3090 str.w r3, [r7, #144] @ 0x90 80051b4: e00e b.n 80051d4 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltageRMS[i], sizeof (float)); 80051b6: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 80051ba: 009b lsls r3, r3, #2 80051bc: 4a42 ldr r2, [pc, #264] @ (80052c8 ) 80051be: 441a add r2, r3 80051c0: 2304 movs r3, #4 80051c2: 493f ldr r1, [pc, #252] @ (80052c0 ) 80051c4: 4841 ldr r0, [pc, #260] @ (80052cc ) 80051c6: f7fe fbdb bl 8003980 for (int i = 0; i < 3; i++) { 80051ca: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 80051ce: 3301 adds r3, #1 80051d0: f8c7 3090 str.w r3, [r7, #144] @ 0x90 80051d4: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 80051d8: 2b02 cmp r3, #2 80051da: ddec ble.n 80051b6 } for (int i = 0; i < 3; i++) { 80051dc: 2300 movs r3, #0 80051de: f8c7 308c str.w r3, [r7, #140] @ 0x8c 80051e2: e010 b.n 8005206 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltagePeak[i], sizeof (float)); 80051e4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 80051e8: 3302 adds r3, #2 80051ea: 009b lsls r3, r3, #2 80051ec: 4a36 ldr r2, [pc, #216] @ (80052c8 ) 80051ee: 4413 add r3, r2 80051f0: 1d1a adds r2, r3, #4 80051f2: 2304 movs r3, #4 80051f4: 4932 ldr r1, [pc, #200] @ (80052c0 ) 80051f6: 4835 ldr r0, [pc, #212] @ (80052cc ) 80051f8: f7fe fbc2 bl 8003980 for (int i = 0; i < 3; i++) { 80051fc: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8005200: 3301 adds r3, #1 8005202: f8c7 308c str.w r3, [r7, #140] @ 0x8c 8005206: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800520a: 2b02 cmp r3, #2 800520c: ddea ble.n 80051e4 } for (int i = 0; i < 3; i++) { 800520e: 2300 movs r3, #0 8005210: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8005214: e00f b.n 8005236 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentRMS[i], sizeof (float)); 8005216: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800521a: 3306 adds r3, #6 800521c: 009b lsls r3, r3, #2 800521e: 4a2a ldr r2, [pc, #168] @ (80052c8 ) 8005220: 441a add r2, r3 8005222: 2304 movs r3, #4 8005224: 4926 ldr r1, [pc, #152] @ (80052c0 ) 8005226: 4829 ldr r0, [pc, #164] @ (80052cc ) 8005228: f7fe fbaa bl 8003980 for (int i = 0; i < 3; i++) { 800522c: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8005230: 3301 adds r3, #1 8005232: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8005236: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800523a: 2b02 cmp r3, #2 800523c: ddeb ble.n 8005216 } for (int i = 0; i < 3; i++) { 800523e: 2300 movs r3, #0 8005240: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8005244: e010 b.n 8005268 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentPeak[i], sizeof (float)); 8005246: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 800524a: 3308 adds r3, #8 800524c: 009b lsls r3, r3, #2 800524e: 4a1e ldr r2, [pc, #120] @ (80052c8 ) 8005250: 4413 add r3, r2 8005252: 1d1a adds r2, r3, #4 8005254: 2304 movs r3, #4 8005256: 491a ldr r1, [pc, #104] @ (80052c0 ) 8005258: 481c ldr r0, [pc, #112] @ (80052cc ) 800525a: f7fe fb91 bl 8003980 for (int i = 0; i < 3; i++) { 800525e: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8005262: 3301 adds r3, #1 8005264: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8005268: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 800526c: 2b02 cmp r3, #2 800526e: ddea ble.n 8005246 } for (int i = 0; i < 3; i++) { 8005270: 2300 movs r3, #0 8005272: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8005276: e00f b.n 8005298 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.power[i], sizeof (float)); 8005278: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 800527c: 330c adds r3, #12 800527e: 009b lsls r3, r3, #2 8005280: 4a11 ldr r2, [pc, #68] @ (80052c8 ) 8005282: 441a add r2, r3 8005284: 2304 movs r3, #4 8005286: 490e ldr r1, [pc, #56] @ (80052c0 ) 8005288: 4810 ldr r0, [pc, #64] @ (80052cc ) 800528a: f7fe fb79 bl 8003980 for (int i = 0; i < 3; i++) { 800528e: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8005292: 3301 adds r3, #1 8005294: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8005298: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 800529c: 2b02 cmp r3, #2 800529e: ddeb ble.n 8005278 } osMutexRelease (resMeasurementsMutex); 80052a0: 4b08 ldr r3, [pc, #32] @ (80052c4 ) 80052a2: 681b ldr r3, [r3, #0] 80052a4: 4618 mov r0, r3 80052a6: f00f f941 bl 801452c respStatus = spOK; 80052aa: 2300 movs r3, #0 80052ac: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 80052b0: f000 bcf3 b.w 8005c9a respStatus = spInternalError; 80052b4: 23fc movs r3, #252 @ 0xfc 80052b6: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80052ba: f000 bcee b.w 8005c9a 80052be: bf00 nop 80052c0: 2400105c .word 0x2400105c 80052c4: 24000818 .word 0x24000818 80052c8: 24000824 .word 0x24000824 80052cc: 24000fdc .word 0x24000fdc case spGetSensorMeasurments: if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80052d0: 4b8d ldr r3, [pc, #564] @ (8005508 ) 80052d2: 681b ldr r3, [r3, #0] 80052d4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80052d8: 4618 mov r0, r3 80052da: f00f f8dc bl 8014496 80052de: 4603 mov r3, r0 80052e0: 2b00 cmp r3, #0 80052e2: f040 80ad bne.w 8005440 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[0], sizeof (float)); 80052e6: 2304 movs r3, #4 80052e8: 4a88 ldr r2, [pc, #544] @ (800550c ) 80052ea: 4989 ldr r1, [pc, #548] @ (8005510 ) 80052ec: 4889 ldr r0, [pc, #548] @ (8005514 ) 80052ee: f7fe fb47 bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[1], sizeof (float)); 80052f2: 2304 movs r3, #4 80052f4: 4a88 ldr r2, [pc, #544] @ (8005518 ) 80052f6: 4986 ldr r1, [pc, #536] @ (8005510 ) 80052f8: 4886 ldr r0, [pc, #536] @ (8005514 ) 80052fa: f7fe fb41 bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.fanVoltage, sizeof (float)); 80052fe: 2304 movs r3, #4 8005300: 4a86 ldr r2, [pc, #536] @ (800551c ) 8005302: 4983 ldr r1, [pc, #524] @ (8005510 ) 8005304: 4883 ldr r0, [pc, #524] @ (8005514 ) 8005306: f7fe fb3b bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderX, sizeof (float)); 800530a: 2304 movs r3, #4 800530c: 4a84 ldr r2, [pc, #528] @ (8005520 ) 800530e: 4980 ldr r1, [pc, #512] @ (8005510 ) 8005310: 4880 ldr r0, [pc, #512] @ (8005514 ) 8005312: f7fe fb35 bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderY, sizeof (float)); 8005316: 2304 movs r3, #4 8005318: 4a82 ldr r2, [pc, #520] @ (8005524 ) 800531a: 497d ldr r1, [pc, #500] @ (8005510 ) 800531c: 487d ldr r0, [pc, #500] @ (8005514 ) 800531e: f7fe fb2f bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXStatus, sizeof (uint8_t)); 8005322: 2301 movs r3, #1 8005324: 4a80 ldr r2, [pc, #512] @ (8005528 ) 8005326: 497a ldr r1, [pc, #488] @ (8005510 ) 8005328: 487a ldr r0, [pc, #488] @ (8005514 ) 800532a: f7fe fb29 bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYStatus, sizeof (uint8_t)); 800532e: 2301 movs r3, #1 8005330: 4a7e ldr r2, [pc, #504] @ (800552c ) 8005332: 4977 ldr r1, [pc, #476] @ (8005510 ) 8005334: 4877 ldr r0, [pc, #476] @ (8005514 ) 8005336: f7fe fb23 bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXAveCurrent, sizeof (float)); 800533a: 2304 movs r3, #4 800533c: 4a7c ldr r2, [pc, #496] @ (8005530 ) 800533e: 4974 ldr r1, [pc, #464] @ (8005510 ) 8005340: 4874 ldr r0, [pc, #464] @ (8005514 ) 8005342: f7fe fb1d bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYAveCurrent, sizeof (float)); 8005346: 2304 movs r3, #4 8005348: 4a7a ldr r2, [pc, #488] @ (8005534 ) 800534a: 4971 ldr r1, [pc, #452] @ (8005510 ) 800534c: 4871 ldr r0, [pc, #452] @ (8005514 ) 800534e: f7fe fb17 bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXPeakCurrent, sizeof (float)); 8005352: 2304 movs r3, #4 8005354: 4a78 ldr r2, [pc, #480] @ (8005538 ) 8005356: 496e ldr r1, [pc, #440] @ (8005510 ) 8005358: 486e ldr r0, [pc, #440] @ (8005514 ) 800535a: f7fe fb11 bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYPeakCurrent, sizeof (float)); 800535e: 2304 movs r3, #4 8005360: 4a76 ldr r2, [pc, #472] @ (800553c ) 8005362: 496b ldr r1, [pc, #428] @ (8005510 ) 8005364: 486b ldr r0, [pc, #428] @ (8005514 ) 8005366: f7fe fb0b bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchUp, sizeof (uint8_t)); 800536a: 2301 movs r3, #1 800536c: 4a74 ldr r2, [pc, #464] @ (8005540 ) 800536e: 4968 ldr r1, [pc, #416] @ (8005510 ) 8005370: 4868 ldr r0, [pc, #416] @ (8005514 ) 8005372: f7fe fb05 bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchDown, sizeof (uint8_t)); 8005376: 2301 movs r3, #1 8005378: 4a72 ldr r2, [pc, #456] @ (8005544 ) 800537a: 4965 ldr r1, [pc, #404] @ (8005510 ) 800537c: 4865 ldr r0, [pc, #404] @ (8005514 ) 800537e: f7fe faff bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchCenter, sizeof (uint8_t)); 8005382: 2301 movs r3, #1 8005384: 4a70 ldr r2, [pc, #448] @ (8005548 ) 8005386: 4962 ldr r1, [pc, #392] @ (8005510 ) 8005388: 4862 ldr r0, [pc, #392] @ (8005514 ) 800538a: f7fe faf9 bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchUp, sizeof (uint8_t)); 800538e: 2301 movs r3, #1 8005390: 4a6e ldr r2, [pc, #440] @ (800554c ) 8005392: 495f ldr r1, [pc, #380] @ (8005510 ) 8005394: 485f ldr r0, [pc, #380] @ (8005514 ) 8005396: f7fe faf3 bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchDown, sizeof (uint8_t)); 800539a: 2301 movs r3, #1 800539c: 4a6c ldr r2, [pc, #432] @ (8005550 ) 800539e: 495c ldr r1, [pc, #368] @ (8005510 ) 80053a0: 485c ldr r0, [pc, #368] @ (8005514 ) 80053a2: f7fe faed bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchCenter, sizeof (uint8_t)); 80053a6: 2301 movs r3, #1 80053a8: 4a6a ldr r2, [pc, #424] @ (8005554 ) 80053aa: 4959 ldr r1, [pc, #356] @ (8005510 ) 80053ac: 4859 ldr r0, [pc, #356] @ (8005514 ) 80053ae: f7fe fae7 bl 8003980 uint8_t comparatorOutput = HAL_COMP_GetOutputLevel (&hcomp1) == COMP_OUTPUT_LEVEL_HIGH ? 1 : 0; 80053b2: 4869 ldr r0, [pc, #420] @ (8005558 ) 80053b4: f002 faf2 bl 800799c 80053b8: 4603 mov r3, r0 80053ba: 2b01 cmp r3, #1 80053bc: bf0c ite eq 80053be: 2301 moveq r3, #1 80053c0: 2300 movne r3, #0 80053c2: b2db uxtb r3, r3 80053c4: f887 3047 strb.w r3, [r7, #71] @ 0x47 sensorsInfo.powerSupplyFailMask = ~((comparatorOutput << 1) | HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_3)) & 0x01; 80053c8: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 80053cc: 005c lsls r4, r3, #1 80053ce: 2108 movs r1, #8 80053d0: 4862 ldr r0, [pc, #392] @ (800555c ) 80053d2: f006 f89b bl 800b50c 80053d6: 4603 mov r3, r0 80053d8: 4323 orrs r3, r4 80053da: f003 0301 and.w r3, r3, #1 80053de: 2b00 cmp r3, #0 80053e0: bf0c ite eq 80053e2: 2301 moveq r3, #1 80053e4: 2300 movne r3, #0 80053e6: b2db uxtb r3, r3 80053e8: 461a mov r2, r3 80053ea: 4b48 ldr r3, [pc, #288] @ (800550c ) 80053ec: f883 202e strb.w r2, [r3, #46] @ 0x2e WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.powerSupplyFailMask, sizeof (uint8_t)); 80053f0: 2301 movs r3, #1 80053f2: 4a5b ldr r2, [pc, #364] @ (8005560 ) 80053f4: 4946 ldr r1, [pc, #280] @ (8005510 ) 80053f6: 4847 ldr r0, [pc, #284] @ (8005514 ) 80053f8: f7fe fac2 bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.currentXPosition, sizeof (float)); 80053fc: 2304 movs r3, #4 80053fe: 4a59 ldr r2, [pc, #356] @ (8005564 ) 8005400: 4943 ldr r1, [pc, #268] @ (8005510 ) 8005402: 4844 ldr r0, [pc, #272] @ (8005514 ) 8005404: f7fe fabc bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.currentYPosition, sizeof (float)); 8005408: 2304 movs r3, #4 800540a: 4a57 ldr r2, [pc, #348] @ (8005568 ) 800540c: 4940 ldr r1, [pc, #256] @ (8005510 ) 800540e: 4841 ldr r0, [pc, #260] @ (8005514 ) 8005410: f7fe fab6 bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.positionXWeak, sizeof (uint8_t)); 8005414: 2301 movs r3, #1 8005416: 4a55 ldr r2, [pc, #340] @ (800556c ) 8005418: 493d ldr r1, [pc, #244] @ (8005510 ) 800541a: 483e ldr r0, [pc, #248] @ (8005514 ) 800541c: f7fe fab0 bl 8003980 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.positionYWeak, sizeof (uint8_t)); 8005420: 2301 movs r3, #1 8005422: 4a53 ldr r2, [pc, #332] @ (8005570 ) 8005424: 493a ldr r1, [pc, #232] @ (8005510 ) 8005426: 483b ldr r0, [pc, #236] @ (8005514 ) 8005428: f7fe faaa bl 8003980 osMutexRelease (sensorsInfoMutex); 800542c: 4b36 ldr r3, [pc, #216] @ (8005508 ) 800542e: 681b ldr r3, [r3, #0] 8005430: 4618 mov r0, r3 8005432: f00f f87b bl 801452c respStatus = spOK; 8005436: 2300 movs r3, #0 8005438: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 800543c: f000 bc2d b.w 8005c9a respStatus = spInternalError; 8005440: 23fc movs r3, #252 @ 0xfc 8005442: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005446: f000 bc28 b.w 8005c9a case spSetFanSpeed: osTimerStop (fanTimerHandle); 800544a: 4b4a ldr r3, [pc, #296] @ (8005574 ) 800544c: 681b ldr r3, [r3, #0] 800544e: 4618 mov r0, r3 8005450: f00e ff64 bl 801431c int32_t fanTimerPeriod = 0; 8005454: 2300 movs r3, #0 8005456: 643b str r3, [r7, #64] @ 0x40 uint32_t pulse = 0; 8005458: 2300 movs r3, #0 800545a: 63fb str r3, [r7, #60] @ 0x3c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse); 800545c: 683b ldr r3, [r7, #0] 800545e: 330c adds r3, #12 8005460: f107 023c add.w r2, r7, #60 @ 0x3c 8005464: f107 0144 add.w r1, r7, #68 @ 0x44 8005468: 4618 mov r0, r3 800546a: f7fe faef bl 8003a4c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&fanTimerPeriod); 800546e: 683b ldr r3, [r7, #0] 8005470: 330c adds r3, #12 8005472: f107 0240 add.w r2, r7, #64 @ 0x40 8005476: f107 0144 add.w r1, r7, #68 @ 0x44 800547a: 4618 mov r0, r3 800547c: f7fe fae6 bl 8003a4c fanTimerConfigOC.Pulse = pulse * 10; 8005480: 6bfa ldr r2, [r7, #60] @ 0x3c 8005482: 4613 mov r3, r2 8005484: 009b lsls r3, r3, #2 8005486: 4413 add r3, r2 8005488: 005b lsls r3, r3, #1 800548a: 461a mov r2, r3 800548c: 4b3a ldr r3, [pc, #232] @ (8005578 ) 800548e: 605a str r2, [r3, #4] if (HAL_TIM_PWM_ConfigChannel (&htim1, &fanTimerConfigOC, TIM_CHANNEL_2) != HAL_OK) { 8005490: 2204 movs r2, #4 8005492: 4939 ldr r1, [pc, #228] @ (8005578 ) 8005494: 4839 ldr r0, [pc, #228] @ (800557c ) 8005496: f00a fe45 bl 8010124 800549a: 4603 mov r3, r0 800549c: 2b00 cmp r3, #0 800549e: d001 beq.n 80054a4 Error_Handler (); 80054a0: f7fc fd14 bl 8001ecc } if (fanTimerPeriod > 0) { 80054a4: 6c3b ldr r3, [r7, #64] @ 0x40 80054a6: 2b00 cmp r3, #0 80054a8: dd0f ble.n 80054ca osTimerStart (fanTimerHandle, fanTimerPeriod * 1000); 80054aa: 4b32 ldr r3, [pc, #200] @ (8005574 ) 80054ac: 681a ldr r2, [r3, #0] 80054ae: 6c3b ldr r3, [r7, #64] @ 0x40 80054b0: f44f 717a mov.w r1, #1000 @ 0x3e8 80054b4: fb01 f303 mul.w r3, r1, r3 80054b8: 4619 mov r1, r3 80054ba: 4610 mov r0, r2 80054bc: f00e ff00 bl 80142c0 HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 80054c0: 2104 movs r1, #4 80054c2: 482e ldr r0, [pc, #184] @ (800557c ) 80054c4: f00a f934 bl 800f730 80054c8: e019 b.n 80054fe } else if (fanTimerPeriod == 0) { 80054ca: 6c3b ldr r3, [r7, #64] @ 0x40 80054cc: 2b00 cmp r3, #0 80054ce: d109 bne.n 80054e4 osTimerStop (fanTimerHandle); 80054d0: 4b28 ldr r3, [pc, #160] @ (8005574 ) 80054d2: 681b ldr r3, [r3, #0] 80054d4: 4618 mov r0, r3 80054d6: f00e ff21 bl 801431c HAL_TIM_PWM_Stop (&htim1, TIM_CHANNEL_2); 80054da: 2104 movs r1, #4 80054dc: 4827 ldr r0, [pc, #156] @ (800557c ) 80054de: f00a fa35 bl 800f94c 80054e2: e00c b.n 80054fe } else if (fanTimerPeriod == -1) { 80054e4: 6c3b ldr r3, [r7, #64] @ 0x40 80054e6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80054ea: d108 bne.n 80054fe osTimerStop (fanTimerHandle); 80054ec: 4b21 ldr r3, [pc, #132] @ (8005574 ) 80054ee: 681b ldr r3, [r3, #0] 80054f0: 4618 mov r0, r3 80054f2: f00e ff13 bl 801431c HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 80054f6: 2104 movs r1, #4 80054f8: 4820 ldr r0, [pc, #128] @ (800557c ) 80054fa: f00a f919 bl 800f730 } respStatus = spOK; 80054fe: 2300 movs r3, #0 8005500: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005504: e3c9 b.n 8005c9a 8005506: bf00 nop 8005508: 2400081c .word 0x2400081c 800550c: 24000860 .word 0x24000860 8005510: 2400105c .word 0x2400105c 8005514: 24000fdc .word 0x24000fdc 8005518: 24000864 .word 0x24000864 800551c: 24000868 .word 0x24000868 8005520: 2400086c .word 0x2400086c 8005524: 24000870 .word 0x24000870 8005528: 24000874 .word 0x24000874 800552c: 24000875 .word 0x24000875 8005530: 24000878 .word 0x24000878 8005534: 2400087c .word 0x2400087c 8005538: 24000880 .word 0x24000880 800553c: 24000884 .word 0x24000884 8005540: 24000888 .word 0x24000888 8005544: 24000889 .word 0x24000889 8005548: 2400088a .word 0x2400088a 800554c: 2400088b .word 0x2400088b 8005550: 2400088c .word 0x2400088c 8005554: 2400088d .word 0x2400088d 8005558: 240003b4 .word 0x240003b4 800555c: 58020c00 .word 0x58020c00 8005560: 2400088e .word 0x2400088e 8005564: 24000890 .word 0x24000890 8005568: 24000894 .word 0x24000894 800556c: 24000898 .word 0x24000898 8005570: 24000899 .word 0x24000899 8005574: 24000714 .word 0x24000714 8005578: 240007a4 .word 0x240007a4 800557c: 2400043c .word 0x2400043c case spSetMotorXOn: int32_t motorXPWMPulse = 0; 8005580: 2300 movs r3, #0 8005582: 63bb str r3, [r7, #56] @ 0x38 int32_t motorXTimerPeriod = 0; 8005584: 2300 movs r3, #0 8005586: 637b str r3, [r7, #52] @ 0x34 uint32_t motorXStatus = 0; 8005588: 2300 movs r3, #0 800558a: 64bb str r3, [r7, #72] @ 0x48 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXPWMPulse); 800558c: 683b ldr r3, [r7, #0] 800558e: 330c adds r3, #12 8005590: f107 0238 add.w r2, r7, #56 @ 0x38 8005594: f107 0144 add.w r1, r7, #68 @ 0x44 8005598: 4618 mov r0, r3 800559a: f7fe fa57 bl 8003a4c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXTimerPeriod); 800559e: 683b ldr r3, [r7, #0] 80055a0: 330c adds r3, #12 80055a2: f107 0234 add.w r2, r7, #52 @ 0x34 80055a6: f107 0144 add.w r1, r7, #68 @ 0x44 80055aa: 4618 mov r0, r3 80055ac: f7fe fa4e bl 8003a4c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80055b0: 4bab ldr r3, [pc, #684] @ (8005860 ) 80055b2: 681b ldr r3, [r3, #0] 80055b4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80055b8: 4618 mov r0, r3 80055ba: f00e ff6c bl 8014496 80055be: 4603 mov r3, r0 80055c0: 2b00 cmp r3, #0 80055c2: d12a bne.n 800561a motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, motorXPWMPulse, motorXTimerPeriod, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 80055c4: 4ba7 ldr r3, [pc, #668] @ (8005864 ) 80055c6: 681b ldr r3, [r3, #0] 80055c8: 6bba ldr r2, [r7, #56] @ 0x38 80055ca: 6b79 ldr r1, [r7, #52] @ 0x34 80055cc: 48a6 ldr r0, [pc, #664] @ (8005868 ) 80055ce: f890 0028 ldrb.w r0, [r0, #40] @ 0x28 80055d2: 4ca5 ldr r4, [pc, #660] @ (8005868 ) 80055d4: f894 4029 ldrb.w r4, [r4, #41] @ 0x29 80055d8: 9404 str r4, [sp, #16] 80055da: 9003 str r0, [sp, #12] 80055dc: 9102 str r1, [sp, #8] 80055de: 9201 str r2, [sp, #4] 80055e0: 9300 str r3, [sp, #0] 80055e2: 2304 movs r3, #4 80055e4: 2200 movs r2, #0 80055e6: 49a1 ldr r1, [pc, #644] @ (800586c ) 80055e8: 48a1 ldr r0, [pc, #644] @ (8005870 ) 80055ea: f7fd fd09 bl 8003000 80055ee: 4603 mov r3, r0 motorXStatus = 80055f0: 64bb str r3, [r7, #72] @ 0x48 sensorsInfo.motorXStatus = motorXStatus; 80055f2: 6cbb ldr r3, [r7, #72] @ 0x48 80055f4: b2da uxtb r2, r3 80055f6: 4b9c ldr r3, [pc, #624] @ (8005868 ) 80055f8: 751a strb r2, [r3, #20] if (motorXStatus == 1) { 80055fa: 6cbb ldr r3, [r7, #72] @ 0x48 80055fc: 2b01 cmp r3, #1 80055fe: d103 bne.n 8005608 sensorsInfo.motorXPeakCurrent = 0.0; 8005600: 4b99 ldr r3, [pc, #612] @ (8005868 ) 8005602: f04f 0200 mov.w r2, #0 8005606: 621a str r2, [r3, #32] } osMutexRelease (sensorsInfoMutex); 8005608: 4b95 ldr r3, [pc, #596] @ (8005860 ) 800560a: 681b ldr r3, [r3, #0] 800560c: 4618 mov r0, r3 800560e: f00e ff8d bl 801452c respStatus = spOK; 8005612: 2300 movs r3, #0 8005614: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005618: e33f b.n 8005c9a respStatus = spInternalError; 800561a: 23fc movs r3, #252 @ 0xfc 800561c: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005620: e33b b.n 8005c9a case spSetMotorYOn: int32_t motorYPWMPulse = 0; 8005622: 2300 movs r3, #0 8005624: 633b str r3, [r7, #48] @ 0x30 int32_t motorYTimerPeriod = 0; 8005626: 2300 movs r3, #0 8005628: 62fb str r3, [r7, #44] @ 0x2c uint32_t motorYStatus = 0; 800562a: 2300 movs r3, #0 800562c: 64fb str r3, [r7, #76] @ 0x4c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYPWMPulse); 800562e: 683b ldr r3, [r7, #0] 8005630: 330c adds r3, #12 8005632: f107 0230 add.w r2, r7, #48 @ 0x30 8005636: f107 0144 add.w r1, r7, #68 @ 0x44 800563a: 4618 mov r0, r3 800563c: f7fe fa06 bl 8003a4c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYTimerPeriod); 8005640: 683b ldr r3, [r7, #0] 8005642: 330c adds r3, #12 8005644: f107 022c add.w r2, r7, #44 @ 0x2c 8005648: f107 0144 add.w r1, r7, #68 @ 0x44 800564c: 4618 mov r0, r3 800564e: f7fe f9fd bl 8003a4c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8005652: 4b83 ldr r3, [pc, #524] @ (8005860 ) 8005654: 681b ldr r3, [r3, #0] 8005656: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800565a: 4618 mov r0, r3 800565c: f00e ff1b bl 8014496 8005660: 4603 mov r3, r0 8005662: 2b00 cmp r3, #0 8005664: d12a bne.n 80056bc motorYStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, motorYPWMPulse, motorYTimerPeriod, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 8005666: 4b83 ldr r3, [pc, #524] @ (8005874 ) 8005668: 681b ldr r3, [r3, #0] 800566a: 6b3a ldr r2, [r7, #48] @ 0x30 800566c: 6af9 ldr r1, [r7, #44] @ 0x2c 800566e: 487e ldr r0, [pc, #504] @ (8005868 ) 8005670: f890 002b ldrb.w r0, [r0, #43] @ 0x2b 8005674: 4c7c ldr r4, [pc, #496] @ (8005868 ) 8005676: f894 402c ldrb.w r4, [r4, #44] @ 0x2c 800567a: 9404 str r4, [sp, #16] 800567c: 9003 str r0, [sp, #12] 800567e: 9102 str r1, [sp, #8] 8005680: 9201 str r2, [sp, #4] 8005682: 9300 str r3, [sp, #0] 8005684: 230c movs r3, #12 8005686: 2208 movs r2, #8 8005688: 4978 ldr r1, [pc, #480] @ (800586c ) 800568a: 4879 ldr r0, [pc, #484] @ (8005870 ) 800568c: f7fd fcb8 bl 8003000 8005690: 4603 mov r3, r0 motorYStatus = 8005692: 64fb str r3, [r7, #76] @ 0x4c sensorsInfo.motorYStatus = motorYStatus; 8005694: 6cfb ldr r3, [r7, #76] @ 0x4c 8005696: b2da uxtb r2, r3 8005698: 4b73 ldr r3, [pc, #460] @ (8005868 ) 800569a: 755a strb r2, [r3, #21] if (motorYStatus == 1) { 800569c: 6cfb ldr r3, [r7, #76] @ 0x4c 800569e: 2b01 cmp r3, #1 80056a0: d103 bne.n 80056aa sensorsInfo.motorYPeakCurrent = 0.0; 80056a2: 4b71 ldr r3, [pc, #452] @ (8005868 ) 80056a4: f04f 0200 mov.w r2, #0 80056a8: 625a str r2, [r3, #36] @ 0x24 } osMutexRelease (sensorsInfoMutex); 80056aa: 4b6d ldr r3, [pc, #436] @ (8005860 ) 80056ac: 681b ldr r3, [r3, #0] 80056ae: 4618 mov r0, r3 80056b0: f00e ff3c bl 801452c respStatus = spOK; 80056b4: 2300 movs r3, #0 80056b6: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 80056ba: e2ee b.n 8005c9a respStatus = spInternalError; 80056bc: 23fc movs r3, #252 @ 0xfc 80056be: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80056c2: e2ea b.n 8005c9a case spSetDiodeOn: osTimerStop (debugLedTimerHandle); 80056c4: 4b6c ldr r3, [pc, #432] @ (8005878 ) 80056c6: 681b ldr r3, [r3, #0] 80056c8: 4618 mov r0, r3 80056ca: f00e fe27 bl 801431c int32_t dbgLedTimerPeriod = 0; 80056ce: 2300 movs r3, #0 80056d0: 62bb str r3, [r7, #40] @ 0x28 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&dbgLedTimerPeriod); 80056d2: 683b ldr r3, [r7, #0] 80056d4: 330c adds r3, #12 80056d6: f107 0228 add.w r2, r7, #40 @ 0x28 80056da: f107 0144 add.w r1, r7, #68 @ 0x44 80056de: 4618 mov r0, r3 80056e0: f7fe f9b4 bl 8003a4c if (dbgLedTimerPeriod > 0) { 80056e4: 6abb ldr r3, [r7, #40] @ 0x28 80056e6: 2b00 cmp r3, #0 80056e8: dd0e ble.n 8005708 osTimerStart (debugLedTimerHandle, dbgLedTimerPeriod * 1000); 80056ea: 4b63 ldr r3, [pc, #396] @ (8005878 ) 80056ec: 681a ldr r2, [r3, #0] 80056ee: 6abb ldr r3, [r7, #40] @ 0x28 80056f0: f44f 717a mov.w r1, #1000 @ 0x3e8 80056f4: fb01 f303 mul.w r3, r1, r3 80056f8: 4619 mov r1, r3 80056fa: 4610 mov r0, r2 80056fc: f00e fde0 bl 80142c0 DbgLEDOn (DBG_LED1); 8005700: 2010 movs r0, #16 8005702: f7fd fbef bl 8002ee4 8005706: e017 b.n 8005738 } else if (dbgLedTimerPeriod == 0) { 8005708: 6abb ldr r3, [r7, #40] @ 0x28 800570a: 2b00 cmp r3, #0 800570c: d108 bne.n 8005720 osTimerStop (debugLedTimerHandle); 800570e: 4b5a ldr r3, [pc, #360] @ (8005878 ) 8005710: 681b ldr r3, [r3, #0] 8005712: 4618 mov r0, r3 8005714: f00e fe02 bl 801431c DbgLEDOff (DBG_LED1); 8005718: 2010 movs r0, #16 800571a: f7fd fbf5 bl 8002f08 800571e: e00b b.n 8005738 } else if (dbgLedTimerPeriod == -1) { 8005720: 6abb ldr r3, [r7, #40] @ 0x28 8005722: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8005726: d107 bne.n 8005738 osTimerStop (debugLedTimerHandle); 8005728: 4b53 ldr r3, [pc, #332] @ (8005878 ) 800572a: 681b ldr r3, [r3, #0] 800572c: 4618 mov r0, r3 800572e: f00e fdf5 bl 801431c DbgLEDOn (DBG_LED1); 8005732: 2010 movs r0, #16 8005734: f7fd fbd6 bl 8002ee4 } respStatus = spOK; 8005738: 2300 movs r3, #0 800573a: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 800573e: e2ac b.n 8005c9a case spSetmotorXMaxCurrent: float motorXMaxCurrent = 0; 8005740: f04f 0300 mov.w r3, #0 8005744: 627b str r3, [r7, #36] @ 0x24 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXMaxCurrent); 8005746: 683b ldr r3, [r7, #0] 8005748: 330c adds r3, #12 800574a: f107 0224 add.w r2, r7, #36 @ 0x24 800574e: f107 0144 add.w r1, r7, #68 @ 0x44 8005752: 4618 mov r0, r3 8005754: f7fe f97a bl 8003a4c uint32_t dacDataCh1 = (uint32_t)(4095 * motorXMaxCurrent / (EXT_VREF_mV * 0.001)); 8005758: edd7 7a09 vldr s15, [r7, #36] @ 0x24 800575c: ed9f 7a47 vldr s14, [pc, #284] @ 800587c 8005760: ee67 7a87 vmul.f32 s15, s15, s14 8005764: eeb7 6ae7 vcvt.f64.f32 d6, s15 8005768: eeb0 5b08 vmov.f64 d5, #8 @ 0x40400000 3.0 800576c: ee86 7b05 vdiv.f64 d7, d6, d5 8005770: eefc 7bc7 vcvt.u32.f64 s15, d7 8005774: ee17 3a90 vmov r3, s15 8005778: 653b str r3, [r7, #80] @ 0x50 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, dacDataCh1); 800577a: 6d3b ldr r3, [r7, #80] @ 0x50 800577c: 2200 movs r2, #0 800577e: 2100 movs r1, #0 8005780: 483f ldr r0, [pc, #252] @ (8005880 ) 8005782: f002 fd56 bl 8008232 HAL_DAC_Start (&hdac1, DAC_CHANNEL_1); 8005786: 2100 movs r1, #0 8005788: 483d ldr r0, [pc, #244] @ (8005880 ) 800578a: f002 fca5 bl 80080d8 respStatus = spOK; 800578e: 2300 movs r3, #0 8005790: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005794: e281 b.n 8005c9a case spSetmotorYMaxCurrent: float motorYMaxCurrent = 0; 8005796: f04f 0300 mov.w r3, #0 800579a: 623b str r3, [r7, #32] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYMaxCurrent); 800579c: 683b ldr r3, [r7, #0] 800579e: 330c adds r3, #12 80057a0: f107 0220 add.w r2, r7, #32 80057a4: f107 0144 add.w r1, r7, #68 @ 0x44 80057a8: 4618 mov r0, r3 80057aa: f7fe f94f bl 8003a4c uint32_t dacDataCh2 = (uint32_t)(4095 * motorYMaxCurrent / (EXT_VREF_mV * 0.001)); 80057ae: edd7 7a08 vldr s15, [r7, #32] 80057b2: ed9f 7a32 vldr s14, [pc, #200] @ 800587c 80057b6: ee67 7a87 vmul.f32 s15, s15, s14 80057ba: eeb7 6ae7 vcvt.f64.f32 d6, s15 80057be: eeb0 5b08 vmov.f64 d5, #8 @ 0x40400000 3.0 80057c2: ee86 7b05 vdiv.f64 d7, d6, d5 80057c6: eefc 7bc7 vcvt.u32.f64 s15, d7 80057ca: ee17 3a90 vmov r3, s15 80057ce: 657b str r3, [r7, #84] @ 0x54 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, dacDataCh2); 80057d0: 6d7b ldr r3, [r7, #84] @ 0x54 80057d2: 2200 movs r2, #0 80057d4: 2110 movs r1, #16 80057d6: 482a ldr r0, [pc, #168] @ (8005880 ) 80057d8: f002 fd2b bl 8008232 HAL_DAC_Start (&hdac1, DAC_CHANNEL_2); 80057dc: 2110 movs r1, #16 80057de: 4828 ldr r0, [pc, #160] @ (8005880 ) 80057e0: f002 fc7a bl 80080d8 respStatus = spOK; 80057e4: 2300 movs r3, #0 80057e6: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80057ea: e256 b.n 8005c9a case spClearPeakMeasurments: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 80057ec: 4b25 ldr r3, [pc, #148] @ (8005884 ) 80057ee: 681b ldr r3, [r3, #0] 80057f0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80057f4: 4618 mov r0, r3 80057f6: f00e fe4e bl 8014496 80057fa: 4603 mov r3, r0 80057fc: 2b00 cmp r3, #0 80057fe: d12a bne.n 8005856 for (int i = 0; i < 3; i++) { 8005800: 2300 movs r3, #0 8005802: 67fb str r3, [r7, #124] @ 0x7c 8005804: e01b b.n 800583e resMeasurements.voltagePeak[i] = resMeasurements.voltageRMS[i]; 8005806: 4a20 ldr r2, [pc, #128] @ (8005888 ) 8005808: 6ffb ldr r3, [r7, #124] @ 0x7c 800580a: 009b lsls r3, r3, #2 800580c: 4413 add r3, r2 800580e: 681a ldr r2, [r3, #0] 8005810: 491d ldr r1, [pc, #116] @ (8005888 ) 8005812: 6ffb ldr r3, [r7, #124] @ 0x7c 8005814: 3302 adds r3, #2 8005816: 009b lsls r3, r3, #2 8005818: 440b add r3, r1 800581a: 3304 adds r3, #4 800581c: 601a str r2, [r3, #0] resMeasurements.currentPeak[i] = resMeasurements.currentRMS[i]; 800581e: 4a1a ldr r2, [pc, #104] @ (8005888 ) 8005820: 6ffb ldr r3, [r7, #124] @ 0x7c 8005822: 3306 adds r3, #6 8005824: 009b lsls r3, r3, #2 8005826: 4413 add r3, r2 8005828: 681a ldr r2, [r3, #0] 800582a: 4917 ldr r1, [pc, #92] @ (8005888 ) 800582c: 6ffb ldr r3, [r7, #124] @ 0x7c 800582e: 3308 adds r3, #8 8005830: 009b lsls r3, r3, #2 8005832: 440b add r3, r1 8005834: 3304 adds r3, #4 8005836: 601a str r2, [r3, #0] for (int i = 0; i < 3; i++) { 8005838: 6ffb ldr r3, [r7, #124] @ 0x7c 800583a: 3301 adds r3, #1 800583c: 67fb str r3, [r7, #124] @ 0x7c 800583e: 6ffb ldr r3, [r7, #124] @ 0x7c 8005840: 2b02 cmp r3, #2 8005842: dde0 ble.n 8005806 } osMutexRelease (resMeasurementsMutex); 8005844: 4b0f ldr r3, [pc, #60] @ (8005884 ) 8005846: 681b ldr r3, [r3, #0] 8005848: 4618 mov r0, r3 800584a: f00e fe6f bl 801452c respStatus = spOK; 800584e: 2300 movs r3, #0 8005850: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005854: e221 b.n 8005c9a respStatus = spInternalError; 8005856: 23fc movs r3, #252 @ 0xfc 8005858: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 800585c: e21d b.n 8005c9a 800585e: bf00 nop 8005860: 2400081c .word 0x2400081c 8005864: 24000744 .word 0x24000744 8005868: 24000860 .word 0x24000860 800586c: 240007c0 .word 0x240007c0 8005870: 240004d4 .word 0x240004d4 8005874: 24000774 .word 0x24000774 8005878: 240006e4 .word 0x240006e4 800587c: 457ff000 .word 0x457ff000 8005880: 24000404 .word 0x24000404 8005884: 24000818 .word 0x24000818 8005888: 24000824 .word 0x24000824 case spSetEncoderXValue: float enocoderXValue = 0; 800588c: f04f 0300 mov.w r3, #0 8005890: 61fb str r3, [r7, #28] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderXValue); 8005892: 683b ldr r3, [r7, #0] 8005894: 330c adds r3, #12 8005896: f107 021c add.w r2, r7, #28 800589a: f107 0144 add.w r1, r7, #68 @ 0x44 800589e: 4618 mov r0, r3 80058a0: f7fe f8d4 bl 8003a4c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80058a4: 4bbc ldr r3, [pc, #752] @ (8005b98 ) 80058a6: 681b ldr r3, [r3, #0] 80058a8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80058ac: 4618 mov r0, r3 80058ae: f00e fdf2 bl 8014496 80058b2: 4603 mov r3, r0 80058b4: 2b00 cmp r3, #0 80058b6: d10b bne.n 80058d0 sensorsInfo.pvEncoderX = enocoderXValue; 80058b8: 69fb ldr r3, [r7, #28] 80058ba: 4ab8 ldr r2, [pc, #736] @ (8005b9c ) 80058bc: 60d3 str r3, [r2, #12] osMutexRelease (sensorsInfoMutex); 80058be: 4bb6 ldr r3, [pc, #728] @ (8005b98 ) 80058c0: 681b ldr r3, [r3, #0] 80058c2: 4618 mov r0, r3 80058c4: f00e fe32 bl 801452c respStatus = spOK; 80058c8: 2300 movs r3, #0 80058ca: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 80058ce: e1e4 b.n 8005c9a respStatus = spInternalError; 80058d0: 23fc movs r3, #252 @ 0xfc 80058d2: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80058d6: e1e0 b.n 8005c9a case spSetEncoderYValue: float enocoderYValue = 0; 80058d8: f04f 0300 mov.w r3, #0 80058dc: 61bb str r3, [r7, #24] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderYValue); 80058de: 683b ldr r3, [r7, #0] 80058e0: 330c adds r3, #12 80058e2: f107 0218 add.w r2, r7, #24 80058e6: f107 0144 add.w r1, r7, #68 @ 0x44 80058ea: 4618 mov r0, r3 80058ec: f7fe f8ae bl 8003a4c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80058f0: 4ba9 ldr r3, [pc, #676] @ (8005b98 ) 80058f2: 681b ldr r3, [r3, #0] 80058f4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80058f8: 4618 mov r0, r3 80058fa: f00e fdcc bl 8014496 80058fe: 4603 mov r3, r0 8005900: 2b00 cmp r3, #0 8005902: d10b bne.n 800591c sensorsInfo.pvEncoderY = enocoderYValue; 8005904: 69bb ldr r3, [r7, #24] 8005906: 4aa5 ldr r2, [pc, #660] @ (8005b9c ) 8005908: 6113 str r3, [r2, #16] osMutexRelease (sensorsInfoMutex); 800590a: 4ba3 ldr r3, [pc, #652] @ (8005b98 ) 800590c: 681b ldr r3, [r3, #0] 800590e: 4618 mov r0, r3 8005910: f00e fe0c bl 801452c respStatus = spOK; 8005914: 2300 movs r3, #0 8005916: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 800591a: e1be b.n 8005c9a respStatus = spInternalError; 800591c: 23fc movs r3, #252 @ 0xfc 800591e: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005922: e1ba b.n 8005c9a case spSetVoltageMeasGains: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005924: 4b9e ldr r3, [pc, #632] @ (8005ba0 ) 8005926: 681b ldr r3, [r3, #0] 8005928: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800592c: 4618 mov r0, r3 800592e: f00e fdb2 bl 8014496 8005932: 4603 mov r3, r0 8005934: 2b00 cmp r3, #0 8005936: d122 bne.n 800597e for (uint8_t i = 0; i < 3; i++) { 8005938: 2300 movs r3, #0 800593a: f887 307b strb.w r3, [r7, #123] @ 0x7b 800593e: e011 b.n 8005964 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].gain); 8005940: 683b ldr r3, [r7, #0] 8005942: f103 000c add.w r0, r3, #12 8005946: f897 307b ldrb.w r3, [r7, #123] @ 0x7b 800594a: 00db lsls r3, r3, #3 800594c: 4a95 ldr r2, [pc, #596] @ (8005ba4 ) 800594e: 441a add r2, r3 8005950: f107 0344 add.w r3, r7, #68 @ 0x44 8005954: 4619 mov r1, r3 8005956: f7fe f879 bl 8003a4c for (uint8_t i = 0; i < 3; i++) { 800595a: f897 307b ldrb.w r3, [r7, #123] @ 0x7b 800595e: 3301 adds r3, #1 8005960: f887 307b strb.w r3, [r7, #123] @ 0x7b 8005964: f897 307b ldrb.w r3, [r7, #123] @ 0x7b 8005968: 2b02 cmp r3, #2 800596a: d9e9 bls.n 8005940 } osMutexRelease (resMeasurementsMutex); 800596c: 4b8c ldr r3, [pc, #560] @ (8005ba0 ) 800596e: 681b ldr r3, [r3, #0] 8005970: 4618 mov r0, r3 8005972: f00e fddb bl 801452c respStatus = spOK; 8005976: 2300 movs r3, #0 8005978: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 800597c: e18d b.n 8005c9a respStatus = spInternalError; 800597e: 23fc movs r3, #252 @ 0xfc 8005980: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005984: e189 b.n 8005c9a case spSetVoltageMeasOffsets: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005986: 4b86 ldr r3, [pc, #536] @ (8005ba0 ) 8005988: 681b ldr r3, [r3, #0] 800598a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800598e: 4618 mov r0, r3 8005990: f00e fd81 bl 8014496 8005994: 4603 mov r3, r0 8005996: 2b00 cmp r3, #0 8005998: d123 bne.n 80059e2 for (uint8_t i = 0; i < 3; i++) { 800599a: 2300 movs r3, #0 800599c: f887 307a strb.w r3, [r7, #122] @ 0x7a 80059a0: e012 b.n 80059c8 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].offset); 80059a2: 683b ldr r3, [r7, #0] 80059a4: f103 000c add.w r0, r3, #12 80059a8: f897 307a ldrb.w r3, [r7, #122] @ 0x7a 80059ac: 00db lsls r3, r3, #3 80059ae: 4a7d ldr r2, [pc, #500] @ (8005ba4 ) 80059b0: 4413 add r3, r2 80059b2: 1d1a adds r2, r3, #4 80059b4: f107 0344 add.w r3, r7, #68 @ 0x44 80059b8: 4619 mov r1, r3 80059ba: f7fe f847 bl 8003a4c for (uint8_t i = 0; i < 3; i++) { 80059be: f897 307a ldrb.w r3, [r7, #122] @ 0x7a 80059c2: 3301 adds r3, #1 80059c4: f887 307a strb.w r3, [r7, #122] @ 0x7a 80059c8: f897 307a ldrb.w r3, [r7, #122] @ 0x7a 80059cc: 2b02 cmp r3, #2 80059ce: d9e8 bls.n 80059a2 } osMutexRelease (resMeasurementsMutex); 80059d0: 4b73 ldr r3, [pc, #460] @ (8005ba0 ) 80059d2: 681b ldr r3, [r3, #0] 80059d4: 4618 mov r0, r3 80059d6: f00e fda9 bl 801452c respStatus = spOK; 80059da: 2300 movs r3, #0 80059dc: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 80059e0: e15b b.n 8005c9a respStatus = spInternalError; 80059e2: 23fc movs r3, #252 @ 0xfc 80059e4: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80059e8: e157 b.n 8005c9a case spSetCurrentMeasGains: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 80059ea: 4b6d ldr r3, [pc, #436] @ (8005ba0 ) 80059ec: 681b ldr r3, [r3, #0] 80059ee: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80059f2: 4618 mov r0, r3 80059f4: f00e fd4f bl 8014496 80059f8: 4603 mov r3, r0 80059fa: 2b00 cmp r3, #0 80059fc: d122 bne.n 8005a44 for (uint8_t i = 0; i < 3; i++) { 80059fe: 2300 movs r3, #0 8005a00: f887 3079 strb.w r3, [r7, #121] @ 0x79 8005a04: e011 b.n 8005a2a ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].gain); 8005a06: 683b ldr r3, [r7, #0] 8005a08: f103 000c add.w r0, r3, #12 8005a0c: f897 3079 ldrb.w r3, [r7, #121] @ 0x79 8005a10: 00db lsls r3, r3, #3 8005a12: 4a65 ldr r2, [pc, #404] @ (8005ba8 ) 8005a14: 441a add r2, r3 8005a16: f107 0344 add.w r3, r7, #68 @ 0x44 8005a1a: 4619 mov r1, r3 8005a1c: f7fe f816 bl 8003a4c for (uint8_t i = 0; i < 3; i++) { 8005a20: f897 3079 ldrb.w r3, [r7, #121] @ 0x79 8005a24: 3301 adds r3, #1 8005a26: f887 3079 strb.w r3, [r7, #121] @ 0x79 8005a2a: f897 3079 ldrb.w r3, [r7, #121] @ 0x79 8005a2e: 2b02 cmp r3, #2 8005a30: d9e9 bls.n 8005a06 } osMutexRelease (resMeasurementsMutex); 8005a32: 4b5b ldr r3, [pc, #364] @ (8005ba0 ) 8005a34: 681b ldr r3, [r3, #0] 8005a36: 4618 mov r0, r3 8005a38: f00e fd78 bl 801452c respStatus = spOK; 8005a3c: 2300 movs r3, #0 8005a3e: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005a42: e12a b.n 8005c9a respStatus = spInternalError; 8005a44: 23fc movs r3, #252 @ 0xfc 8005a46: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005a4a: e126 b.n 8005c9a case spSetCurrentMeasOffsets: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005a4c: 4b54 ldr r3, [pc, #336] @ (8005ba0 ) 8005a4e: 681b ldr r3, [r3, #0] 8005a50: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005a54: 4618 mov r0, r3 8005a56: f00e fd1e bl 8014496 8005a5a: 4603 mov r3, r0 8005a5c: 2b00 cmp r3, #0 8005a5e: d123 bne.n 8005aa8 for (uint8_t i = 0; i < 3; i++) { 8005a60: 2300 movs r3, #0 8005a62: f887 3078 strb.w r3, [r7, #120] @ 0x78 8005a66: e012 b.n 8005a8e ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].offset); 8005a68: 683b ldr r3, [r7, #0] 8005a6a: f103 000c add.w r0, r3, #12 8005a6e: f897 3078 ldrb.w r3, [r7, #120] @ 0x78 8005a72: 00db lsls r3, r3, #3 8005a74: 4a4c ldr r2, [pc, #304] @ (8005ba8 ) 8005a76: 4413 add r3, r2 8005a78: 1d1a adds r2, r3, #4 8005a7a: f107 0344 add.w r3, r7, #68 @ 0x44 8005a7e: 4619 mov r1, r3 8005a80: f7fd ffe4 bl 8003a4c for (uint8_t i = 0; i < 3; i++) { 8005a84: f897 3078 ldrb.w r3, [r7, #120] @ 0x78 8005a88: 3301 adds r3, #1 8005a8a: f887 3078 strb.w r3, [r7, #120] @ 0x78 8005a8e: f897 3078 ldrb.w r3, [r7, #120] @ 0x78 8005a92: 2b02 cmp r3, #2 8005a94: d9e8 bls.n 8005a68 } osMutexRelease (resMeasurementsMutex); 8005a96: 4b42 ldr r3, [pc, #264] @ (8005ba0 ) 8005a98: 681b ldr r3, [r3, #0] 8005a9a: 4618 mov r0, r3 8005a9c: f00e fd46 bl 801452c respStatus = spOK; 8005aa0: 2300 movs r3, #0 8005aa2: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005aa6: e0f8 b.n 8005c9a respStatus = spInternalError; 8005aa8: 23fc movs r3, #252 @ 0xfc 8005aaa: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005aae: e0f4 b.n 8005c9a __ASM volatile ("cpsid i" : : : "memory"); 8005ab0: b672 cpsid i } 8005ab2: bf00 nop case spResetSystem: __disable_irq(); NVIC_SystemReset(); 8005ab4: f7fe ff62 bl 800497c <__NVIC_SystemReset> break; case spSetPositonX: PositionControlTaskData posXData = { 0 }; 8005ab8: f04f 0300 mov.w r3, #0 8005abc: 617b str r3, [r7, #20] if (positionXControlTaskInitArg.positionSettingQueue != NULL) 8005abe: 4b3b ldr r3, [pc, #236] @ (8005bac ) 8005ac0: 691b ldr r3, [r3, #16] 8005ac2: 2b00 cmp r3, #0 8005ac4: f000 80e6 beq.w 8005c94 { float posXPercent = 0; 8005ac8: f04f 0300 mov.w r3, #0 8005acc: 60fb str r3, [r7, #12] ReadFloatFromBuffer(spFrameData->dataBuffer, &inputDataBufferPos, &posXPercent); 8005ace: 683b ldr r3, [r7, #0] 8005ad0: 330c adds r3, #12 8005ad2: f107 020c add.w r2, r7, #12 8005ad6: f107 0144 add.w r1, r7, #68 @ 0x44 8005ada: 4618 mov r0, r3 8005adc: f7fd ff81 bl 80039e2 float posXDegress = MAX_X_AXE_ANGLE * posXPercent * 0.01; 8005ae0: edd7 7a03 vldr s15, [r7, #12] 8005ae4: ed9f 7a32 vldr s14, [pc, #200] @ 8005bb0 8005ae8: ee67 7a87 vmul.f32 s15, s15, s14 8005aec: eeb7 7ae7 vcvt.f64.f32 d7, s15 8005af0: ed9f 6b27 vldr d6, [pc, #156] @ 8005b90 8005af4: ee27 7b06 vmul.f64 d7, d7, d6 8005af8: eef7 7bc7 vcvt.f32.f64 s15, d7 8005afc: edc7 7a18 vstr s15, [r7, #96] @ 0x60 float angleDelta = 360 / ENCODER_X_IMP_PER_TURN; 8005b00: 4b2c ldr r3, [pc, #176] @ (8005bb4 ) 8005b02: 65fb str r3, [r7, #92] @ 0x5c float rest = fmodf(posXDegress, angleDelta); 8005b04: edd7 0a17 vldr s1, [r7, #92] @ 0x5c 8005b08: ed97 0a18 vldr s0, [r7, #96] @ 0x60 8005b0c: f012 fcda bl 80184c4 8005b10: ed87 0a16 vstr s0, [r7, #88] @ 0x58 if ( rest > (angleDelta/2)) 8005b14: ed97 7a17 vldr s14, [r7, #92] @ 0x5c 8005b18: eef0 6a00 vmov.f32 s13, #0 @ 0x40000000 2.0 8005b1c: eec7 7a26 vdiv.f32 s15, s14, s13 8005b20: ed97 7a16 vldr s14, [r7, #88] @ 0x58 8005b24: eeb4 7ae7 vcmpe.f32 s14, s15 8005b28: eef1 fa10 vmrs APSR_nzcv, fpscr 8005b2c: dd14 ble.n 8005b58 { posXData.positionSettingValue = 100 * (posXDegress - rest + angleDelta) / MAX_X_AXE_ANGLE; 8005b2e: ed97 7a18 vldr s14, [r7, #96] @ 0x60 8005b32: edd7 7a16 vldr s15, [r7, #88] @ 0x58 8005b36: ee37 7a67 vsub.f32 s14, s14, s15 8005b3a: edd7 7a17 vldr s15, [r7, #92] @ 0x5c 8005b3e: ee77 7a27 vadd.f32 s15, s14, s15 8005b42: ed9f 7a1d vldr s14, [pc, #116] @ 8005bb8 8005b46: ee27 7a87 vmul.f32 s14, s15, s14 8005b4a: eddf 6a19 vldr s13, [pc, #100] @ 8005bb0 8005b4e: eec7 7a26 vdiv.f32 s15, s14, s13 8005b52: edc7 7a05 vstr s15, [r7, #20] 8005b56: e00f b.n 8005b78 } else { posXData.positionSettingValue = 100 * (posXDegress - rest) / MAX_X_AXE_ANGLE; 8005b58: ed97 7a18 vldr s14, [r7, #96] @ 0x60 8005b5c: edd7 7a16 vldr s15, [r7, #88] @ 0x58 8005b60: ee77 7a67 vsub.f32 s15, s14, s15 8005b64: ed9f 7a14 vldr s14, [pc, #80] @ 8005bb8 8005b68: ee27 7a87 vmul.f32 s14, s15, s14 8005b6c: eddf 6a10 vldr s13, [pc, #64] @ 8005bb0 8005b70: eec7 7a26 vdiv.f32 s15, s14, s13 8005b74: edc7 7a05 vstr s15, [r7, #20] } osMessageQueuePut(positionXControlTaskInitArg.positionSettingQueue, &posXData, 0, 0); 8005b78: 4b0c ldr r3, [pc, #48] @ (8005bac ) 8005b7a: 6918 ldr r0, [r3, #16] 8005b7c: f107 0114 add.w r1, r7, #20 8005b80: 2300 movs r3, #0 8005b82: 2200 movs r2, #0 8005b84: f00e fd82 bl 801468c } break; 8005b88: e084 b.n 8005c94 8005b8a: bf00 nop 8005b8c: f3af 8000 nop.w 8005b90: 47ae147b .word 0x47ae147b 8005b94: 3f847ae1 .word 0x3f847ae1 8005b98: 2400081c .word 0x2400081c 8005b9c: 24000860 .word 0x24000860 8005ba0: 24000818 .word 0x24000818 8005ba4: 24000000 .word 0x24000000 8005ba8: 24000018 .word 0x24000018 8005bac: 240008b4 .word 0x240008b4 8005bb0: 43b40000 .word 0x43b40000 8005bb4: 41900000 .word 0x41900000 8005bb8: 42c80000 .word 0x42c80000 case spSetPositonY: PositionControlTaskData posYData = { 0 }; 8005bbc: f04f 0300 mov.w r3, #0 8005bc0: 613b str r3, [r7, #16] if (positionYControlTaskInitArg.positionSettingQueue != NULL) 8005bc2: 4b4b ldr r3, [pc, #300] @ (8005cf0 ) 8005bc4: 691b ldr r3, [r3, #16] 8005bc6: 2b00 cmp r3, #0 8005bc8: d066 beq.n 8005c98 { float posYPercent = 0; 8005bca: f04f 0300 mov.w r3, #0 8005bce: 60bb str r3, [r7, #8] ReadFloatFromBuffer(spFrameData->dataBuffer, &inputDataBufferPos, &posYPercent); 8005bd0: 683b ldr r3, [r7, #0] 8005bd2: 330c adds r3, #12 8005bd4: f107 0208 add.w r2, r7, #8 8005bd8: f107 0144 add.w r1, r7, #68 @ 0x44 8005bdc: 4618 mov r0, r3 8005bde: f7fd ff00 bl 80039e2 float posYDegress = MAX_Y_AXE_ANGLE * posYPercent * 0.01; 8005be2: edd7 7a02 vldr s15, [r7, #8] 8005be6: ed9f 7a43 vldr s14, [pc, #268] @ 8005cf4 8005bea: ee67 7a87 vmul.f32 s15, s15, s14 8005bee: eeb7 7ae7 vcvt.f64.f32 d7, s15 8005bf2: ed9f 6b3d vldr d6, [pc, #244] @ 8005ce8 8005bf6: ee27 7b06 vmul.f64 d7, d7, d6 8005bfa: eef7 7bc7 vcvt.f32.f64 s15, d7 8005bfe: edc7 7a1b vstr s15, [r7, #108] @ 0x6c float angleDelta = 360 / ENCODER_Y_IMP_PER_TURN; 8005c02: 4b3d ldr r3, [pc, #244] @ (8005cf8 ) 8005c04: 66bb str r3, [r7, #104] @ 0x68 float rest = fmodf(posYDegress, angleDelta); 8005c06: edd7 0a1a vldr s1, [r7, #104] @ 0x68 8005c0a: ed97 0a1b vldr s0, [r7, #108] @ 0x6c 8005c0e: f012 fc59 bl 80184c4 8005c12: ed87 0a19 vstr s0, [r7, #100] @ 0x64 if ( rest > (angleDelta/2)) 8005c16: ed97 7a1a vldr s14, [r7, #104] @ 0x68 8005c1a: eef0 6a00 vmov.f32 s13, #0 @ 0x40000000 2.0 8005c1e: eec7 7a26 vdiv.f32 s15, s14, s13 8005c22: ed97 7a19 vldr s14, [r7, #100] @ 0x64 8005c26: eeb4 7ae7 vcmpe.f32 s14, s15 8005c2a: eef1 fa10 vmrs APSR_nzcv, fpscr 8005c2e: dd14 ble.n 8005c5a { posYData.positionSettingValue = 100 * (posYDegress - rest + angleDelta) / MAX_Y_AXE_ANGLE; 8005c30: ed97 7a1b vldr s14, [r7, #108] @ 0x6c 8005c34: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8005c38: ee37 7a67 vsub.f32 s14, s14, s15 8005c3c: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8005c40: ee77 7a27 vadd.f32 s15, s14, s15 8005c44: ed9f 7a2d vldr s14, [pc, #180] @ 8005cfc 8005c48: ee27 7a87 vmul.f32 s14, s15, s14 8005c4c: eddf 6a29 vldr s13, [pc, #164] @ 8005cf4 8005c50: eec7 7a26 vdiv.f32 s15, s14, s13 8005c54: edc7 7a04 vstr s15, [r7, #16] 8005c58: e00f b.n 8005c7a } else { posYData.positionSettingValue = 100 * (posYDegress - rest) / MAX_Y_AXE_ANGLE; 8005c5a: ed97 7a1b vldr s14, [r7, #108] @ 0x6c 8005c5e: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8005c62: ee77 7a67 vsub.f32 s15, s14, s15 8005c66: ed9f 7a25 vldr s14, [pc, #148] @ 8005cfc 8005c6a: ee27 7a87 vmul.f32 s14, s15, s14 8005c6e: eddf 6a21 vldr s13, [pc, #132] @ 8005cf4 8005c72: eec7 7a26 vdiv.f32 s15, s14, s13 8005c76: edc7 7a04 vstr s15, [r7, #16] } osMessageQueuePut(positionYControlTaskInitArg.positionSettingQueue, &posYData, 0, 0); 8005c7a: 4b1d ldr r3, [pc, #116] @ (8005cf0 ) 8005c7c: 6918 ldr r0, [r3, #16] 8005c7e: f107 0110 add.w r1, r7, #16 8005c82: 2300 movs r3, #0 8005c84: 2200 movs r2, #0 8005c86: f00e fd01 bl 801468c } break; 8005c8a: e005 b.n 8005c98 default: respStatus = spUnknownCommand; break; 8005c8c: 23fd movs r3, #253 @ 0xfd 8005c8e: f887 3097 strb.w r3, [r7, #151] @ 0x97 8005c92: e002 b.n 8005c9a break; 8005c94: bf00 nop 8005c96: e000 b.n 8005c9a break; 8005c98: bf00 nop } dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8005c9a: 6f7b ldr r3, [r7, #116] @ 0x74 8005c9c: 6898 ldr r0, [r3, #8] 8005c9e: 683b ldr r3, [r7, #0] 8005ca0: 8819 ldrh r1, [r3, #0] 8005ca2: 683b ldr r3, [r7, #0] 8005ca4: 789a ldrb r2, [r3, #2] 8005ca6: 4b16 ldr r3, [pc, #88] @ (8005d00 ) 8005ca8: 881b ldrh r3, [r3, #0] 8005caa: f997 4097 ldrsb.w r4, [r7, #151] @ 0x97 8005cae: 9301 str r3, [sp, #4] 8005cb0: 4b14 ldr r3, [pc, #80] @ (8005d04 ) 8005cb2: 9300 str r3, [sp, #0] 8005cb4: 4623 mov r3, r4 8005cb6: f7fd fefd bl 8003ab4 8005cba: 4603 mov r3, r0 8005cbc: f8a7 3072 strh.w r3, [r7, #114] @ 0x72 if (dataToSend > 0) { 8005cc0: f8b7 3072 ldrh.w r3, [r7, #114] @ 0x72 8005cc4: 2b00 cmp r3, #0 8005cc6: d008 beq.n 8005cda HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 8005cc8: 6f7b ldr r3, [r7, #116] @ 0x74 8005cca: 6b18 ldr r0, [r3, #48] @ 0x30 8005ccc: 6f7b ldr r3, [r7, #116] @ 0x74 8005cce: 689b ldr r3, [r3, #8] 8005cd0: f8b7 2072 ldrh.w r2, [r7, #114] @ 0x72 8005cd4: 4619 mov r1, r3 8005cd6: f00b fbb1 bl 801143c } #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: TX bytes sent: %d\n", uartTaskData->uartNumber, dataToSend); #endif } 8005cda: bf00 nop 8005cdc: 379c adds r7, #156 @ 0x9c 8005cde: 46bd mov sp, r7 8005ce0: bd90 pop {r4, r7, pc} 8005ce2: bf00 nop 8005ce4: f3af 8000 nop.w 8005ce8: 47ae147b .word 0x47ae147b 8005cec: 3f847ae1 .word 0x3f847ae1 8005cf0: 240008e8 .word 0x240008e8 8005cf4: 43b40000 .word 0x43b40000 8005cf8: 41900000 .word 0x41900000 8005cfc: 42c80000 .word 0x42c80000 8005d00: 2400105c .word 0x2400105c 8005d04: 24000fdc .word 0x24000fdc 08005d08 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8005d08: f8df d034 ldr.w sp, [pc, #52] @ 8005d40 /* Call the clock system initialization function.*/ bl SystemInit 8005d0c: f7fe fdae bl 800486c /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8005d10: 480c ldr r0, [pc, #48] @ (8005d44 ) ldr r1, =_edata 8005d12: 490d ldr r1, [pc, #52] @ (8005d48 ) ldr r2, =_sidata 8005d14: 4a0d ldr r2, [pc, #52] @ (8005d4c ) movs r3, #0 8005d16: 2300 movs r3, #0 b LoopCopyDataInit 8005d18: e002 b.n 8005d20 08005d1a : CopyDataInit: ldr r4, [r2, r3] 8005d1a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8005d1c: 50c4 str r4, [r0, r3] adds r3, r3, #4 8005d1e: 3304 adds r3, #4 08005d20 : LoopCopyDataInit: adds r4, r0, r3 8005d20: 18c4 adds r4, r0, r3 cmp r4, r1 8005d22: 428c cmp r4, r1 bcc CopyDataInit 8005d24: d3f9 bcc.n 8005d1a /* Zero fill the bss segment. */ ldr r2, =_sbss 8005d26: 4a0a ldr r2, [pc, #40] @ (8005d50 ) ldr r4, =_ebss 8005d28: 4c0a ldr r4, [pc, #40] @ (8005d54 ) movs r3, #0 8005d2a: 2300 movs r3, #0 b LoopFillZerobss 8005d2c: e001 b.n 8005d32 08005d2e : FillZerobss: str r3, [r2] 8005d2e: 6013 str r3, [r2, #0] adds r2, r2, #4 8005d30: 3204 adds r2, #4 08005d32 : LoopFillZerobss: cmp r2, r4 8005d32: 42a2 cmp r2, r4 bcc FillZerobss 8005d34: d3fb bcc.n 8005d2e /* Call static constructors */ bl __libc_init_array 8005d36: f012 fb3b bl 80183b0 <__libc_init_array> /* Call the application's entry point.*/ bl main 8005d3a: f7fa fc8b bl 8000654
bx lr 8005d3e: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8005d40: 24060000 .word 0x24060000 ldr r0, =_sdata 8005d44: 24000000 .word 0x24000000 ldr r1, =_edata 8005d48: 24000098 .word 0x24000098 ldr r2, =_sidata 8005d4c: 08018734 .word 0x08018734 ldr r2, =_sbss 8005d50: 240000a0 .word 0x240000a0 ldr r4, =_ebss 8005d54: 2401318c .word 0x2401318c 08005d58 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8005d58: e7fe b.n 8005d58 ... 08005d5c : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8005d5c: b580 push {r7, lr} 8005d5e: b082 sub sp, #8 8005d60: af00 add r7, sp, #0 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ #endif /* DUAL_CORE && CORE_CM4 */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8005d62: 2003 movs r0, #3 8005d64: f001 fee5 bl 8007b32 /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8005d68: f006 fbee bl 800c548 8005d6c: 4602 mov r2, r0 8005d6e: 4b15 ldr r3, [pc, #84] @ (8005dc4 ) 8005d70: 699b ldr r3, [r3, #24] 8005d72: 0a1b lsrs r3, r3, #8 8005d74: f003 030f and.w r3, r3, #15 8005d78: 4913 ldr r1, [pc, #76] @ (8005dc8 ) 8005d7a: 5ccb ldrb r3, [r1, r3] 8005d7c: f003 031f and.w r3, r3, #31 8005d80: fa22 f303 lsr.w r3, r2, r3 8005d84: 607b str r3, [r7, #4] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8005d86: 4b0f ldr r3, [pc, #60] @ (8005dc4 ) 8005d88: 699b ldr r3, [r3, #24] 8005d8a: f003 030f and.w r3, r3, #15 8005d8e: 4a0e ldr r2, [pc, #56] @ (8005dc8 ) 8005d90: 5cd3 ldrb r3, [r2, r3] 8005d92: f003 031f and.w r3, r3, #31 8005d96: 687a ldr r2, [r7, #4] 8005d98: fa22 f303 lsr.w r3, r2, r3 8005d9c: 4a0b ldr r2, [pc, #44] @ (8005dcc ) 8005d9e: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8005da0: 4a0b ldr r2, [pc, #44] @ (8005dd0 ) 8005da2: 687b ldr r3, [r7, #4] 8005da4: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8005da6: 2005 movs r0, #5 8005da8: f7fe fc58 bl 800465c 8005dac: 4603 mov r3, r0 8005dae: 2b00 cmp r3, #0 8005db0: d001 beq.n 8005db6 { return HAL_ERROR; 8005db2: 2301 movs r3, #1 8005db4: e002 b.n 8005dbc } /* Init the low level hardware */ HAL_MspInit(); 8005db6: f7fd ff1b bl 8003bf0 /* Return function status */ return HAL_OK; 8005dba: 2300 movs r3, #0 } 8005dbc: 4618 mov r0, r3 8005dbe: 3708 adds r7, #8 8005dc0: 46bd mov sp, r7 8005dc2: bd80 pop {r7, pc} 8005dc4: 58024400 .word 0x58024400 8005dc8: 080186dc .word 0x080186dc 8005dcc: 24000038 .word 0x24000038 8005dd0: 24000034 .word 0x24000034 08005dd4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8005dd4: b480 push {r7} 8005dd6: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 8005dd8: 4b06 ldr r3, [pc, #24] @ (8005df4 ) 8005dda: 781b ldrb r3, [r3, #0] 8005ddc: 461a mov r2, r3 8005dde: 4b06 ldr r3, [pc, #24] @ (8005df8 ) 8005de0: 681b ldr r3, [r3, #0] 8005de2: 4413 add r3, r2 8005de4: 4a04 ldr r2, [pc, #16] @ (8005df8 ) 8005de6: 6013 str r3, [r2, #0] } 8005de8: bf00 nop 8005dea: 46bd mov sp, r7 8005dec: f85d 7b04 ldr.w r7, [sp], #4 8005df0: 4770 bx lr 8005df2: bf00 nop 8005df4: 24000040 .word 0x24000040 8005df8: 24001060 .word 0x24001060 08005dfc : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8005dfc: b480 push {r7} 8005dfe: af00 add r7, sp, #0 return uwTick; 8005e00: 4b03 ldr r3, [pc, #12] @ (8005e10 ) 8005e02: 681b ldr r3, [r3, #0] } 8005e04: 4618 mov r0, r3 8005e06: 46bd mov sp, r7 8005e08: f85d 7b04 ldr.w r7, [sp], #4 8005e0c: 4770 bx lr 8005e0e: bf00 nop 8005e10: 24001060 .word 0x24001060 08005e14 : /** * @brief Returns the device revision identifier. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { 8005e14: b480 push {r7} 8005e16: af00 add r7, sp, #0 return((DBGMCU->IDCODE) >> 16); 8005e18: 4b03 ldr r3, [pc, #12] @ (8005e28 ) 8005e1a: 681b ldr r3, [r3, #0] 8005e1c: 0c1b lsrs r3, r3, #16 } 8005e1e: 4618 mov r0, r3 8005e20: 46bd mov sp, r7 8005e22: f85d 7b04 ldr.w r7, [sp], #4 8005e26: 4770 bx lr 8005e28: 5c001000 .word 0x5c001000 08005e2c : * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. * @retval None */ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) { 8005e2c: b480 push {r7} 8005e2e: b083 sub sp, #12 8005e30: af00 add r7, sp, #0 8005e32: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); 8005e34: 4b06 ldr r3, [pc, #24] @ (8005e50 ) 8005e36: 681b ldr r3, [r3, #0] 8005e38: f023 0202 bic.w r2, r3, #2 8005e3c: 4904 ldr r1, [pc, #16] @ (8005e50 ) 8005e3e: 687b ldr r3, [r7, #4] 8005e40: 4313 orrs r3, r2 8005e42: 600b str r3, [r1, #0] } 8005e44: bf00 nop 8005e46: 370c adds r7, #12 8005e48: 46bd mov sp, r7 8005e4a: f85d 7b04 ldr.w r7, [sp], #4 8005e4e: 4770 bx lr 8005e50: 58003c00 .word 0x58003c00 08005e54 : * @brief Disable the Internal Voltage Reference buffer (VREFBUF). * * @retval None */ void HAL_SYSCFG_DisableVREFBUF(void) { 8005e54: b480 push {r7} 8005e56: af00 add r7, sp, #0 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); 8005e58: 4b05 ldr r3, [pc, #20] @ (8005e70 ) 8005e5a: 681b ldr r3, [r3, #0] 8005e5c: 4a04 ldr r2, [pc, #16] @ (8005e70 ) 8005e5e: f023 0301 bic.w r3, r3, #1 8005e62: 6013 str r3, [r2, #0] } 8005e64: bf00 nop 8005e66: 46bd mov sp, r7 8005e68: f85d 7b04 ldr.w r7, [sp], #4 8005e6c: 4770 bx lr 8005e6e: bf00 nop 8005e70: 58003c00 .word 0x58003c00 08005e74 : * @arg SYSCFG_SWITCH_PC3_CLOSE * @retval None */ void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ) { 8005e74: b480 push {r7} 8005e76: b083 sub sp, #12 8005e78: af00 add r7, sp, #0 8005e7a: 6078 str r0, [r7, #4] 8005e7c: 6039 str r1, [r7, #0] /* Check the parameter */ assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch)); assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState)); MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState)); 8005e7e: 4b07 ldr r3, [pc, #28] @ (8005e9c ) 8005e80: 685a ldr r2, [r3, #4] 8005e82: 687b ldr r3, [r7, #4] 8005e84: 43db mvns r3, r3 8005e86: 401a ands r2, r3 8005e88: 4904 ldr r1, [pc, #16] @ (8005e9c ) 8005e8a: 683b ldr r3, [r7, #0] 8005e8c: 4313 orrs r3, r2 8005e8e: 604b str r3, [r1, #4] } 8005e90: bf00 nop 8005e92: 370c adds r7, #12 8005e94: 46bd mov sp, r7 8005e96: f85d 7b04 ldr.w r7, [sp], #4 8005e9a: 4770 bx lr 8005e9c: 58000400 .word 0x58000400 08005ea0 : * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) { 8005ea0: b480 push {r7} 8005ea2: b083 sub sp, #12 8005ea4: af00 add r7, sp, #0 8005ea6: 6078 str r0, [r7, #4] 8005ea8: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); 8005eaa: 687b ldr r3, [r7, #4] 8005eac: 689b ldr r3, [r3, #8] 8005eae: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000 8005eb2: 683b ldr r3, [r7, #0] 8005eb4: 431a orrs r2, r3 8005eb6: 687b ldr r3, [r7, #4] 8005eb8: 609a str r2, [r3, #8] } 8005eba: bf00 nop 8005ebc: 370c adds r7, #12 8005ebe: 46bd mov sp, r7 8005ec0: f85d 7b04 ldr.w r7, [sp], #4 8005ec4: 4770 bx lr 08005ec6 : * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { 8005ec6: b480 push {r7} 8005ec8: b083 sub sp, #12 8005eca: af00 add r7, sp, #0 8005ecc: 6078 str r0, [r7, #4] 8005ece: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); 8005ed0: 687b ldr r3, [r7, #4] 8005ed2: 689b ldr r3, [r3, #8] 8005ed4: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000 8005ed8: 683b ldr r3, [r7, #0] 8005eda: 431a orrs r2, r3 8005edc: 687b ldr r3, [r7, #4] 8005ede: 609a str r2, [r3, #8] } 8005ee0: bf00 nop 8005ee2: 370c adds r7, #12 8005ee4: 46bd mov sp, r7 8005ee6: f85d 7b04 ldr.w r7, [sp], #4 8005eea: 4770 bx lr 08005eec : * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) { 8005eec: b480 push {r7} 8005eee: b083 sub sp, #12 8005ef0: af00 add r7, sp, #0 8005ef2: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 8005ef4: 687b ldr r3, [r7, #4] 8005ef6: 689b ldr r3, [r3, #8] 8005ef8: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000 } 8005efc: 4618 mov r0, r3 8005efe: 370c adds r7, #12 8005f00: 46bd mov sp, r7 8005f02: f85d 7b04 ldr.w r7, [sp], #4 8005f06: 4770 bx lr 08005f08 : * Other channels are slow channels (conversion rate: refer to reference manual). * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x3FFFFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { 8005f08: b480 push {r7} 8005f0a: b087 sub sp, #28 8005f0c: af00 add r7, sp, #0 8005f0e: 60f8 str r0, [r7, #12] 8005f10: 60b9 str r1, [r7, #8] 8005f12: 607a str r2, [r7, #4] 8005f14: 603b str r3, [r7, #0] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8005f16: 68fb ldr r3, [r7, #12] 8005f18: 3360 adds r3, #96 @ 0x60 8005f1a: 461a mov r2, r3 8005f1c: 68bb ldr r3, [r7, #8] 8005f1e: 009b lsls r3, r3, #2 8005f20: 4413 add r3, r2 8005f22: 617b str r3, [r7, #20] ADC3_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } else #endif /* ADC_VER_V5_V90 */ { MODIFY_REG(*preg, 8005f24: 697b ldr r3, [r7, #20] 8005f26: 681b ldr r3, [r3, #0] 8005f28: f003 4200 and.w r2, r3, #2147483648 @ 0x80000000 8005f2c: 687b ldr r3, [r7, #4] 8005f2e: f003 41f8 and.w r1, r3, #2080374784 @ 0x7c000000 8005f32: 683b ldr r3, [r7, #0] 8005f34: 430b orrs r3, r1 8005f36: 431a orrs r2, r3 8005f38: 697b ldr r3, [r7, #20] 8005f3a: 601a str r2, [r3, #0] ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } } 8005f3c: bf00 nop 8005f3e: 371c adds r7, #28 8005f40: 46bd mov sp, r7 8005f42: f85d 7b04 ldr.w r7, [sp], #4 8005f46: 4770 bx lr 08005f48 : * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift) { 8005f48: b480 push {r7} 8005f4a: b085 sub sp, #20 8005f4c: af00 add r7, sp, #0 8005f4e: 60f8 str r0, [r7, #12] 8005f50: 60b9 str r1, [r7, #8] 8005f52: 607a str r2, [r7, #4] MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL)); 8005f54: 68fb ldr r3, [r7, #12] 8005f56: 691b ldr r3, [r3, #16] 8005f58: f423 42f0 bic.w r2, r3, #30720 @ 0x7800 8005f5c: 68bb ldr r3, [r7, #8] 8005f5e: f003 031f and.w r3, r3, #31 8005f62: 6879 ldr r1, [r7, #4] 8005f64: fa01 f303 lsl.w r3, r1, r3 8005f68: 431a orrs r2, r3 8005f6a: 68fb ldr r3, [r7, #12] 8005f6c: 611a str r2, [r3, #16] } 8005f6e: bf00 nop 8005f70: 3714 adds r7, #20 8005f72: 46bd mov sp, r7 8005f74: f85d 7b04 ldr.w r7, [sp], #4 8005f78: 4770 bx lr 08005f7a : * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation) { 8005f7a: b480 push {r7} 8005f7c: b087 sub sp, #28 8005f7e: af00 add r7, sp, #0 8005f80: 60f8 str r0, [r7, #12] 8005f82: 60b9 str r1, [r7, #8] 8005f84: 607a str r2, [r7, #4] /* Function not available on this instance */ } else #endif /* ADC_VER_V5_V90 */ { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8005f86: 68fb ldr r3, [r7, #12] 8005f88: 3360 adds r3, #96 @ 0x60 8005f8a: 461a mov r2, r3 8005f8c: 68bb ldr r3, [r7, #8] 8005f8e: 009b lsls r3, r3, #2 8005f90: 4413 add r3, r2 8005f92: 617b str r3, [r7, #20] MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation); 8005f94: 697b ldr r3, [r7, #20] 8005f96: 681b ldr r3, [r3, #0] 8005f98: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 8005f9c: 687b ldr r3, [r7, #4] 8005f9e: 431a orrs r2, r3 8005fa0: 697b ldr r3, [r7, #20] 8005fa2: 601a str r2, [r3, #0] } } 8005fa4: bf00 nop 8005fa6: 371c adds r7, #28 8005fa8: 46bd mov sp, r7 8005faa: f85d 7b04 ldr.w r7, [sp], #4 8005fae: 4770 bx lr 08005fb0 : * @param ADCx ADC instance * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { 8005fb0: b480 push {r7} 8005fb2: b083 sub sp, #12 8005fb4: af00 add r7, sp, #0 8005fb6: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); 8005fb8: 687b ldr r3, [r7, #4] 8005fba: 68db ldr r3, [r3, #12] 8005fbc: f403 6340 and.w r3, r3, #3072 @ 0xc00 8005fc0: 2b00 cmp r3, #0 8005fc2: d101 bne.n 8005fc8 8005fc4: 2301 movs r3, #1 8005fc6: e000 b.n 8005fca 8005fc8: 2300 movs r3, #0 } 8005fca: 4618 mov r0, r3 8005fcc: 370c adds r7, #12 8005fce: 46bd mov sp, r7 8005fd0: f85d 7b04 ldr.w r7, [sp], #4 8005fd4: 4770 bx lr 08005fd6 : * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { 8005fd6: b480 push {r7} 8005fd8: b087 sub sp, #28 8005fda: af00 add r7, sp, #0 8005fdc: 60f8 str r0, [r7, #12] 8005fde: 60b9 str r1, [r7, #8] 8005fe0: 607a str r2, [r7, #4] /* Set bits with content of parameter "Channel" with bits position */ /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); 8005fe2: 68fb ldr r3, [r7, #12] 8005fe4: 3330 adds r3, #48 @ 0x30 8005fe6: 461a mov r2, r3 8005fe8: 68bb ldr r3, [r7, #8] 8005fea: 0a1b lsrs r3, r3, #8 8005fec: 009b lsls r3, r3, #2 8005fee: f003 030c and.w r3, r3, #12 8005ff2: 4413 add r3, r2 8005ff4: 617b str r3, [r7, #20] MODIFY_REG(*preg, 8005ff6: 697b ldr r3, [r7, #20] 8005ff8: 681a ldr r2, [r3, #0] 8005ffa: 68bb ldr r3, [r7, #8] 8005ffc: f003 031f and.w r3, r3, #31 8006000: 211f movs r1, #31 8006002: fa01 f303 lsl.w r3, r1, r3 8006006: 43db mvns r3, r3 8006008: 401a ands r2, r3 800600a: 687b ldr r3, [r7, #4] 800600c: 0e9b lsrs r3, r3, #26 800600e: f003 011f and.w r1, r3, #31 8006012: 68bb ldr r3, [r7, #8] 8006014: f003 031f and.w r3, r3, #31 8006018: fa01 f303 lsl.w r3, r1, r3 800601c: 431a orrs r2, r3 800601e: 697b ldr r3, [r7, #20] 8006020: 601a str r2, [r3, #0] ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } 8006022: bf00 nop 8006024: 371c adds r7, #28 8006026: 46bd mov sp, r7 8006028: f85d 7b04 ldr.w r7, [sp], #4 800602c: 4770 bx lr 0800602e : * @param ADCx ADC instance * @param DataTransferMode Select Data Management configuration * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode) { 800602e: b480 push {r7} 8006030: b083 sub sp, #12 8006032: af00 add r7, sp, #0 8006034: 6078 str r0, [r7, #4] 8006036: 6039 str r1, [r7, #0] MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode); 8006038: 687b ldr r3, [r7, #4] 800603a: 68db ldr r3, [r3, #12] 800603c: f023 0203 bic.w r2, r3, #3 8006040: 683b ldr r3, [r7, #0] 8006042: 431a orrs r2, r3 8006044: 687b ldr r3, [r7, #4] 8006046: 60da str r2, [r3, #12] } 8006048: bf00 nop 800604a: 370c adds r7, #12 800604c: 46bd mov sp, r7 800604e: f85d 7b04 ldr.w r7, [sp], #4 8006052: 4770 bx lr 08006054 : * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5 * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) { 8006054: b480 push {r7} 8006056: b087 sub sp, #28 8006058: af00 add r7, sp, #0 800605a: 60f8 str r0, [r7, #12] 800605c: 60b9 str r1, [r7, #8] 800605e: 607a str r2, [r7, #4] /* Set bits with content of parameter "SamplingTime" with bits position */ /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 8006060: 68fb ldr r3, [r7, #12] 8006062: 3314 adds r3, #20 8006064: 461a mov r2, r3 8006066: 68bb ldr r3, [r7, #8] 8006068: 0e5b lsrs r3, r3, #25 800606a: 009b lsls r3, r3, #2 800606c: f003 0304 and.w r3, r3, #4 8006070: 4413 add r3, r2 8006072: 617b str r3, [r7, #20] MODIFY_REG(*preg, 8006074: 697b ldr r3, [r7, #20] 8006076: 681a ldr r2, [r3, #0] 8006078: 68bb ldr r3, [r7, #8] 800607a: 0d1b lsrs r3, r3, #20 800607c: f003 031f and.w r3, r3, #31 8006080: 2107 movs r1, #7 8006082: fa01 f303 lsl.w r3, r1, r3 8006086: 43db mvns r3, r3 8006088: 401a ands r2, r3 800608a: 68bb ldr r3, [r7, #8] 800608c: 0d1b lsrs r3, r3, #20 800608e: f003 031f and.w r3, r3, #31 8006092: 6879 ldr r1, [r7, #4] 8006094: fa01 f303 lsl.w r3, r1, r3 8006098: 431a orrs r2, r3 800609a: 697b ldr r3, [r7, #20] 800609c: 601a str r2, [r3, #0] ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); } 800609e: bf00 nop 80060a0: 371c adds r7, #28 80060a2: 46bd mov sp, r7 80060a4: f85d 7b04 ldr.w r7, [sp], #4 80060a8: 4770 bx lr ... 080060ac : * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) { 80060ac: b480 push {r7} 80060ae: b085 sub sp, #20 80060b0: af00 add r7, sp, #0 80060b2: 60f8 str r0, [r7, #12] 80060b4: 60b9 str r1, [r7, #8] 80060b6: 607a str r2, [r7, #4] } #else /* ADC_VER_V5_V90 */ /* Bits of channels in single or differential mode are set only for */ /* differential mode (for single mode, mask of bits allowed to be set is */ /* shifted out of range of bits of channels in single or differential mode. */ MODIFY_REG(ADCx->DIFSEL, 80060b8: 68fb ldr r3, [r7, #12] 80060ba: f8d3 20c0 ldr.w r2, [r3, #192] @ 0xc0 80060be: 68bb ldr r3, [r7, #8] 80060c0: f3c3 0313 ubfx r3, r3, #0, #20 80060c4: 43db mvns r3, r3 80060c6: 401a ands r2, r3 80060c8: 687b ldr r3, [r7, #4] 80060ca: f003 0318 and.w r3, r3, #24 80060ce: 4908 ldr r1, [pc, #32] @ (80060f0 ) 80060d0: 40d9 lsrs r1, r3 80060d2: 68bb ldr r3, [r7, #8] 80060d4: 400b ands r3, r1 80060d6: f3c3 0313 ubfx r3, r3, #0, #20 80060da: 431a orrs r2, r3 80060dc: 68fb ldr r3, [r7, #12] 80060de: f8c3 20c0 str.w r2, [r3, #192] @ 0xc0 Channel & ADC_SINGLEDIFF_CHANNEL_MASK, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); #endif /* ADC_VER_V5_V90 */ } 80060e2: bf00 nop 80060e4: 3714 adds r7, #20 80060e6: 46bd mov sp, r7 80060e8: f85d 7b04 ldr.w r7, [sp], #4 80060ec: 4770 bx lr 80060ee: bf00 nop 80060f0: 000fffff .word 0x000fffff 080060f4 : * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) { 80060f4: b480 push {r7} 80060f6: b083 sub sp, #12 80060f8: af00 add r7, sp, #0 80060fa: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 80060fc: 687b ldr r3, [r7, #4] 80060fe: 689b ldr r3, [r3, #8] 8006100: f003 031f and.w r3, r3, #31 } 8006104: 4618 mov r0, r3 8006106: 370c adds r7, #12 8006108: 46bd mov sp, r7 800610a: f85d 7b04 ldr.w r7, [sp], #4 800610e: 4770 bx lr 08006110 : * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) { 8006110: b480 push {r7} 8006112: b083 sub sp, #12 8006114: af00 add r7, sp, #0 8006116: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); 8006118: 687b ldr r3, [r7, #4] 800611a: 689a ldr r2, [r3, #8] 800611c: 4b04 ldr r3, [pc, #16] @ (8006130 ) 800611e: 4013 ands r3, r2 8006120: 687a ldr r2, [r7, #4] 8006122: 6093 str r3, [r2, #8] } 8006124: bf00 nop 8006126: 370c adds r7, #12 8006128: 46bd mov sp, r7 800612a: f85d 7b04 ldr.w r7, [sp], #4 800612e: 4770 bx lr 8006130: 5fffffc0 .word 0x5fffffc0 08006134 : * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) { 8006134: b480 push {r7} 8006136: b083 sub sp, #12 8006138: af00 add r7, sp, #0 800613a: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); 800613c: 687b ldr r3, [r7, #4] 800613e: 689b ldr r3, [r3, #8] 8006140: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8006144: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8006148: d101 bne.n 800614e 800614a: 2301 movs r3, #1 800614c: e000 b.n 8006150 800614e: 2300 movs r3, #0 } 8006150: 4618 mov r0, r3 8006152: 370c adds r7, #12 8006154: 46bd mov sp, r7 8006156: f85d 7b04 ldr.w r7, [sp], #4 800615a: 4770 bx lr 0800615c : * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) { 800615c: b480 push {r7} 800615e: b083 sub sp, #12 8006160: af00 add r7, sp, #0 8006162: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8006164: 687b ldr r3, [r7, #4] 8006166: 689a ldr r2, [r3, #8] 8006168: 4b05 ldr r3, [pc, #20] @ (8006180 ) 800616a: 4013 ands r3, r2 800616c: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000 8006170: 687b ldr r3, [r7, #4] 8006172: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); } 8006174: bf00 nop 8006176: 370c adds r7, #12 8006178: 46bd mov sp, r7 800617a: f85d 7b04 ldr.w r7, [sp], #4 800617e: 4770 bx lr 8006180: 6fffffc0 .word 0x6fffffc0 08006184 : * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) { 8006184: b480 push {r7} 8006186: b083 sub sp, #12 8006188: af00 add r7, sp, #0 800618a: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 800618c: 687b ldr r3, [r7, #4] 800618e: 689b ldr r3, [r3, #8] 8006190: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8006194: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8006198: d101 bne.n 800619e 800619a: 2301 movs r3, #1 800619c: e000 b.n 80061a0 800619e: 2300 movs r3, #0 } 80061a0: 4618 mov r0, r3 80061a2: 370c adds r7, #12 80061a4: 46bd mov sp, r7 80061a6: f85d 7b04 ldr.w r7, [sp], #4 80061aa: 4770 bx lr 080061ac : * @rmtoll CR ADEN LL_ADC_Enable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) { 80061ac: b480 push {r7} 80061ae: b083 sub sp, #12 80061b0: af00 add r7, sp, #0 80061b2: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 80061b4: 687b ldr r3, [r7, #4] 80061b6: 689a ldr r2, [r3, #8] 80061b8: 4b05 ldr r3, [pc, #20] @ (80061d0 ) 80061ba: 4013 ands r3, r2 80061bc: f043 0201 orr.w r2, r3, #1 80061c0: 687b ldr r3, [r7, #4] 80061c2: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN); } 80061c4: bf00 nop 80061c6: 370c adds r7, #12 80061c8: 46bd mov sp, r7 80061ca: f85d 7b04 ldr.w r7, [sp], #4 80061ce: 4770 bx lr 80061d0: 7fffffc0 .word 0x7fffffc0 080061d4 : * @rmtoll CR ADDIS LL_ADC_Disable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) { 80061d4: b480 push {r7} 80061d6: b083 sub sp, #12 80061d8: af00 add r7, sp, #0 80061da: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 80061dc: 687b ldr r3, [r7, #4] 80061de: 689a ldr r2, [r3, #8] 80061e0: 4b05 ldr r3, [pc, #20] @ (80061f8 ) 80061e2: 4013 ands r3, r2 80061e4: f043 0202 orr.w r2, r3, #2 80061e8: 687b ldr r3, [r7, #4] 80061ea: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS); } 80061ec: bf00 nop 80061ee: 370c adds r7, #12 80061f0: 46bd mov sp, r7 80061f2: f85d 7b04 ldr.w r7, [sp], #4 80061f6: 4770 bx lr 80061f8: 7fffffc0 .word 0x7fffffc0 080061fc : * @rmtoll CR ADEN LL_ADC_IsEnabled * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) { 80061fc: b480 push {r7} 80061fe: b083 sub sp, #12 8006200: af00 add r7, sp, #0 8006202: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8006204: 687b ldr r3, [r7, #4] 8006206: 689b ldr r3, [r3, #8] 8006208: f003 0301 and.w r3, r3, #1 800620c: 2b01 cmp r3, #1 800620e: d101 bne.n 8006214 8006210: 2301 movs r3, #1 8006212: e000 b.n 8006216 8006214: 2300 movs r3, #0 } 8006216: 4618 mov r0, r3 8006218: 370c adds r7, #12 800621a: 46bd mov sp, r7 800621c: f85d 7b04 ldr.w r7, [sp], #4 8006220: 4770 bx lr 08006222 : * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) { 8006222: b480 push {r7} 8006224: b083 sub sp, #12 8006226: af00 add r7, sp, #0 8006228: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); 800622a: 687b ldr r3, [r7, #4] 800622c: 689b ldr r3, [r3, #8] 800622e: f003 0302 and.w r3, r3, #2 8006232: 2b02 cmp r3, #2 8006234: d101 bne.n 800623a 8006236: 2301 movs r3, #1 8006238: e000 b.n 800623c 800623a: 2300 movs r3, #0 } 800623c: 4618 mov r0, r3 800623e: 370c adds r7, #12 8006240: 46bd mov sp, r7 8006242: f85d 7b04 ldr.w r7, [sp], #4 8006246: 4770 bx lr 08006248 : * @rmtoll CR ADSTART LL_ADC_REG_StartConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) { 8006248: b480 push {r7} 800624a: b083 sub sp, #12 800624c: af00 add r7, sp, #0 800624e: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8006250: 687b ldr r3, [r7, #4] 8006252: 689a ldr r2, [r3, #8] 8006254: 4b05 ldr r3, [pc, #20] @ (800626c ) 8006256: 4013 ands r3, r2 8006258: f043 0204 orr.w r2, r3, #4 800625c: 687b ldr r3, [r7, #4] 800625e: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART); } 8006260: bf00 nop 8006262: 370c adds r7, #12 8006264: 46bd mov sp, r7 8006266: f85d 7b04 ldr.w r7, [sp], #4 800626a: 4770 bx lr 800626c: 7fffffc0 .word 0x7fffffc0 08006270 : * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) { 8006270: b480 push {r7} 8006272: b083 sub sp, #12 8006274: af00 add r7, sp, #0 8006276: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8006278: 687b ldr r3, [r7, #4] 800627a: 689b ldr r3, [r3, #8] 800627c: f003 0304 and.w r3, r3, #4 8006280: 2b04 cmp r3, #4 8006282: d101 bne.n 8006288 8006284: 2301 movs r3, #1 8006286: e000 b.n 800628a 8006288: 2300 movs r3, #0 } 800628a: 4618 mov r0, r3 800628c: 370c adds r7, #12 800628e: 46bd mov sp, r7 8006290: f85d 7b04 ldr.w r7, [sp], #4 8006294: 4770 bx lr 08006296 : * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) { 8006296: b480 push {r7} 8006298: b083 sub sp, #12 800629a: af00 add r7, sp, #0 800629c: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 800629e: 687b ldr r3, [r7, #4] 80062a0: 689b ldr r3, [r3, #8] 80062a2: f003 0308 and.w r3, r3, #8 80062a6: 2b08 cmp r3, #8 80062a8: d101 bne.n 80062ae 80062aa: 2301 movs r3, #1 80062ac: e000 b.n 80062b0 80062ae: 2300 movs r3, #0 } 80062b0: 4618 mov r0, r3 80062b2: 370c adds r7, #12 80062b4: 46bd mov sp, r7 80062b6: f85d 7b04 ldr.w r7, [sp], #4 80062ba: 4770 bx lr 080062bc : * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { 80062bc: b590 push {r4, r7, lr} 80062be: b089 sub sp, #36 @ 0x24 80062c0: af00 add r7, sp, #0 80062c2: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80062c4: 2300 movs r3, #0 80062c6: 77fb strb r3, [r7, #31] uint32_t tmpCFGR; uint32_t tmp_adc_reg_is_conversion_on_going; __IO uint32_t wait_loop_index = 0UL; 80062c8: 2300 movs r3, #0 80062ca: 60bb str r3, [r7, #8] uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check ADC handle */ if (hadc == NULL) 80062cc: 687b ldr r3, [r7, #4] 80062ce: 2b00 cmp r3, #0 80062d0: d101 bne.n 80062d6 { return HAL_ERROR; 80062d2: 2301 movs r3, #1 80062d4: e18f b.n 80065f6 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 80062d6: 687b ldr r3, [r7, #4] 80062d8: 68db ldr r3, [r3, #12] 80062da: 2b00 cmp r3, #0 /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 80062dc: 687b ldr r3, [r7, #4] 80062de: 6d5b ldr r3, [r3, #84] @ 0x54 80062e0: 2b00 cmp r3, #0 80062e2: d109 bne.n 80062f8 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 80062e4: 6878 ldr r0, [r7, #4] 80062e6: f7fd fcdf bl 8003ca8 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 80062ea: 687b ldr r3, [r7, #4] 80062ec: 2200 movs r2, #0 80062ee: 659a str r2, [r3, #88] @ 0x58 /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; 80062f0: 687b ldr r3, [r7, #4] 80062f2: 2200 movs r2, #0 80062f4: f883 2050 strb.w r2, [r3, #80] @ 0x50 } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) 80062f8: 687b ldr r3, [r7, #4] 80062fa: 681b ldr r3, [r3, #0] 80062fc: 4618 mov r0, r3 80062fe: f7ff ff19 bl 8006134 8006302: 4603 mov r3, r0 8006304: 2b00 cmp r3, #0 8006306: d004 beq.n 8006312 { /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); 8006308: 687b ldr r3, [r7, #4] 800630a: 681b ldr r3, [r3, #0] 800630c: 4618 mov r0, r3 800630e: f7ff feff bl 8006110 /* System was in deep power down mode, calibration must be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 8006312: 687b ldr r3, [r7, #4] 8006314: 681b ldr r3, [r3, #0] 8006316: 4618 mov r0, r3 8006318: f7ff ff34 bl 8006184 800631c: 4603 mov r3, r0 800631e: 2b00 cmp r3, #0 8006320: d114 bne.n 800634c { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); 8006322: 687b ldr r3, [r7, #4] 8006324: 681b ldr r3, [r3, #0] 8006326: 4618 mov r0, r3 8006328: f7ff ff18 bl 800615c /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 800632c: 4b87 ldr r3, [pc, #540] @ (800654c ) 800632e: 681b ldr r3, [r3, #0] 8006330: 099b lsrs r3, r3, #6 8006332: 4a87 ldr r2, [pc, #540] @ (8006550 ) 8006334: fba2 2303 umull r2, r3, r2, r3 8006338: 099b lsrs r3, r3, #6 800633a: 3301 adds r3, #1 800633c: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 800633e: e002 b.n 8006346 { wait_loop_index--; 8006340: 68bb ldr r3, [r7, #8] 8006342: 3b01 subs r3, #1 8006344: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8006346: 68bb ldr r3, [r7, #8] 8006348: 2b00 cmp r3, #0 800634a: d1f9 bne.n 8006340 } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 800634c: 687b ldr r3, [r7, #4] 800634e: 681b ldr r3, [r3, #0] 8006350: 4618 mov r0, r3 8006352: f7ff ff17 bl 8006184 8006356: 4603 mov r3, r0 8006358: 2b00 cmp r3, #0 800635a: d10d bne.n 8006378 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800635c: 687b ldr r3, [r7, #4] 800635e: 6d5b ldr r3, [r3, #84] @ 0x54 8006360: f043 0210 orr.w r2, r3, #16 8006364: 687b ldr r3, [r7, #4] 8006366: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006368: 687b ldr r3, [r7, #4] 800636a: 6d9b ldr r3, [r3, #88] @ 0x58 800636c: f043 0201 orr.w r2, r3, #1 8006370: 687b ldr r3, [r7, #4] 8006372: 659a str r2, [r3, #88] @ 0x58 tmp_hal_status = HAL_ERROR; 8006374: 2301 movs r3, #1 8006376: 77fb strb r3, [r7, #31] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8006378: 687b ldr r3, [r7, #4] 800637a: 681b ldr r3, [r3, #0] 800637c: 4618 mov r0, r3 800637e: f7ff ff77 bl 8006270 8006382: 6178 str r0, [r7, #20] if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 8006384: 687b ldr r3, [r7, #4] 8006386: 6d5b ldr r3, [r3, #84] @ 0x54 8006388: f003 0310 and.w r3, r3, #16 800638c: 2b00 cmp r3, #0 800638e: f040 8129 bne.w 80065e4 && (tmp_adc_reg_is_conversion_on_going == 0UL) 8006392: 697b ldr r3, [r7, #20] 8006394: 2b00 cmp r3, #0 8006396: f040 8125 bne.w 80065e4 ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800639a: 687b ldr r3, [r7, #4] 800639c: 6d5b ldr r3, [r3, #84] @ 0x54 800639e: f423 7381 bic.w r3, r3, #258 @ 0x102 80063a2: f043 0202 orr.w r2, r3, #2 80063a6: 687b ldr r3, [r7, #4] 80063a8: 655a str r2, [r3, #84] @ 0x54 /* Configuration of common ADC parameters */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 80063aa: 687b ldr r3, [r7, #4] 80063ac: 681b ldr r3, [r3, #0] 80063ae: 4618 mov r0, r3 80063b0: f7ff ff24 bl 80061fc 80063b4: 4603 mov r3, r0 80063b6: 2b00 cmp r3, #0 80063b8: d136 bne.n 8006428 { if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 80063ba: 687b ldr r3, [r7, #4] 80063bc: 681b ldr r3, [r3, #0] 80063be: 4a65 ldr r2, [pc, #404] @ (8006554 ) 80063c0: 4293 cmp r3, r2 80063c2: d004 beq.n 80063ce 80063c4: 687b ldr r3, [r7, #4] 80063c6: 681b ldr r3, [r3, #0] 80063c8: 4a63 ldr r2, [pc, #396] @ (8006558 ) 80063ca: 4293 cmp r3, r2 80063cc: d10e bne.n 80063ec 80063ce: 4861 ldr r0, [pc, #388] @ (8006554 ) 80063d0: f7ff ff14 bl 80061fc 80063d4: 4604 mov r4, r0 80063d6: 4860 ldr r0, [pc, #384] @ (8006558 ) 80063d8: f7ff ff10 bl 80061fc 80063dc: 4603 mov r3, r0 80063de: 4323 orrs r3, r4 80063e0: 2b00 cmp r3, #0 80063e2: bf0c ite eq 80063e4: 2301 moveq r3, #1 80063e6: 2300 movne r3, #0 80063e8: b2db uxtb r3, r3 80063ea: e008 b.n 80063fe 80063ec: 485b ldr r0, [pc, #364] @ (800655c ) 80063ee: f7ff ff05 bl 80061fc 80063f2: 4603 mov r3, r0 80063f4: 2b00 cmp r3, #0 80063f6: bf0c ite eq 80063f8: 2301 moveq r3, #1 80063fa: 2300 movne r3, #0 80063fc: b2db uxtb r3, r3 80063fe: 2b00 cmp r3, #0 8006400: d012 beq.n 8006428 /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ /* HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); 8006402: 687b ldr r3, [r7, #4] 8006404: 681b ldr r3, [r3, #0] 8006406: 4a53 ldr r2, [pc, #332] @ (8006554 ) 8006408: 4293 cmp r3, r2 800640a: d004 beq.n 8006416 800640c: 687b ldr r3, [r7, #4] 800640e: 681b ldr r3, [r3, #0] 8006410: 4a51 ldr r2, [pc, #324] @ (8006558 ) 8006412: 4293 cmp r3, r2 8006414: d101 bne.n 800641a 8006416: 4a52 ldr r2, [pc, #328] @ (8006560 ) 8006418: e000 b.n 800641c 800641a: 4a52 ldr r2, [pc, #328] @ (8006564 ) 800641c: 687b ldr r3, [r7, #4] 800641e: 685b ldr r3, [r3, #4] 8006420: 4619 mov r1, r3 8006422: 4610 mov r0, r2 8006424: f7ff fd3c bl 8005ea0 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); } #else if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution)) 8006428: f7ff fcf4 bl 8005e14 800642c: 4603 mov r3, r0 800642e: f241 0203 movw r2, #4099 @ 0x1003 8006432: 4293 cmp r3, r2 8006434: d914 bls.n 8006460 8006436: 687b ldr r3, [r7, #4] 8006438: 689b ldr r3, [r3, #8] 800643a: 2b10 cmp r3, #16 800643c: d110 bne.n 8006460 { /* for STM32H7 silicon rev.B and above , ADC_CFGR_RES value for 8bits resolution is : b111 */ tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 800643e: 687b ldr r3, [r7, #4] 8006440: 7d5b ldrb r3, [r3, #21] 8006442: 035a lsls r2, r3, #13 hadc->Init.Overrun | 8006444: 687b ldr r3, [r7, #4] 8006446: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006448: 431a orrs r2, r3 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 800644a: 687b ldr r3, [r7, #4] 800644c: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 800644e: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8006450: 687b ldr r3, [r7, #4] 8006452: 7f1b ldrb r3, [r3, #28] 8006454: 041b lsls r3, r3, #16 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 8006456: 4313 orrs r3, r2 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006458: f043 030c orr.w r3, r3, #12 800645c: 61bb str r3, [r7, #24] 800645e: e00d b.n 800647c } else { tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006460: 687b ldr r3, [r7, #4] 8006462: 7d5b ldrb r3, [r3, #21] 8006464: 035a lsls r2, r3, #13 hadc->Init.Overrun | 8006466: 687b ldr r3, [r7, #4] 8006468: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 800646a: 431a orrs r2, r3 hadc->Init.Resolution | 800646c: 687b ldr r3, [r7, #4] 800646e: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 8006470: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8006472: 687b ldr r3, [r7, #4] 8006474: 7f1b ldrb r3, [r3, #28] 8006476: 041b lsls r3, r3, #16 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006478: 4313 orrs r3, r2 800647a: 61bb str r3, [r7, #24] } #endif /* ADC_VER_V5_3 */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 800647c: 687b ldr r3, [r7, #4] 800647e: 7f1b ldrb r3, [r3, #28] 8006480: 2b01 cmp r3, #1 8006482: d106 bne.n 8006492 { tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); 8006484: 687b ldr r3, [r7, #4] 8006486: 6a1b ldr r3, [r3, #32] 8006488: 3b01 subs r3, #1 800648a: 045b lsls r3, r3, #17 800648c: 69ba ldr r2, [r7, #24] 800648e: 4313 orrs r3, r2 8006490: 61bb str r3, [r7, #24] /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 8006492: 687b ldr r3, [r7, #4] 8006494: 6a5b ldr r3, [r3, #36] @ 0x24 8006496: 2b00 cmp r3, #0 8006498: d009 beq.n 80064ae { tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 800649a: 687b ldr r3, [r7, #4] 800649c: 6a5b ldr r3, [r3, #36] @ 0x24 800649e: f403 7278 and.w r2, r3, #992 @ 0x3e0 | hadc->Init.ExternalTrigConvEdge 80064a2: 687b ldr r3, [r7, #4] 80064a4: 6a9b ldr r3, [r3, #40] @ 0x28 80064a6: 4313 orrs r3, r2 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 80064a8: 69ba ldr r2, [r7, #24] 80064aa: 4313 orrs r3, r2 80064ac: 61bb str r3, [r7, #24] /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); } #else /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); 80064ae: 687b ldr r3, [r7, #4] 80064b0: 681b ldr r3, [r3, #0] 80064b2: 68da ldr r2, [r3, #12] 80064b4: 4b2c ldr r3, [pc, #176] @ (8006568 ) 80064b6: 4013 ands r3, r2 80064b8: 687a ldr r2, [r7, #4] 80064ba: 6812 ldr r2, [r2, #0] 80064bc: 69b9 ldr r1, [r7, #24] 80064be: 430b orrs r3, r1 80064c0: 60d3 str r3, [r2, #12] /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - Conversion data management Init.ConversionDataManagement */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 80064c2: 687b ldr r3, [r7, #4] 80064c4: 681b ldr r3, [r3, #0] 80064c6: 4618 mov r0, r3 80064c8: f7ff fed2 bl 8006270 80064cc: 6138 str r0, [r7, #16] tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 80064ce: 687b ldr r3, [r7, #4] 80064d0: 681b ldr r3, [r3, #0] 80064d2: 4618 mov r0, r3 80064d4: f7ff fedf bl 8006296 80064d8: 60f8 str r0, [r7, #12] if ((tmp_adc_is_conversion_on_going_regular == 0UL) 80064da: 693b ldr r3, [r7, #16] 80064dc: 2b00 cmp r3, #0 80064de: d15f bne.n 80065a0 && (tmp_adc_is_conversion_on_going_injected == 0UL) 80064e0: 68fb ldr r3, [r7, #12] 80064e2: 2b00 cmp r3, #0 80064e4: d15c bne.n 80065a0 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); } #else tmpCFGR = ( ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 80064e6: 687b ldr r3, [r7, #4] 80064e8: 7d1b ldrb r3, [r3, #20] 80064ea: 039a lsls r2, r3, #14 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); 80064ec: 687b ldr r3, [r7, #4] 80064ee: 6adb ldr r3, [r3, #44] @ 0x2c tmpCFGR = ( 80064f0: 4313 orrs r3, r2 80064f2: 61bb str r3, [r7, #24] #endif MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 80064f4: 687b ldr r3, [r7, #4] 80064f6: 681b ldr r3, [r3, #0] 80064f8: 68da ldr r2, [r3, #12] 80064fa: 4b1c ldr r3, [pc, #112] @ (800656c ) 80064fc: 4013 ands r3, r2 80064fe: 687a ldr r2, [r7, #4] 8006500: 6812 ldr r2, [r2, #0] 8006502: 69b9 ldr r1, [r7, #24] 8006504: 430b orrs r3, r1 8006506: 60d3 str r3, [r2, #12] if (hadc->Init.OversamplingMode == ENABLE) 8006508: 687b ldr r3, [r7, #4] 800650a: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 800650e: 2b01 cmp r3, #1 8006510: d130 bne.n 8006574 #endif assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START) 8006512: 687b ldr r3, [r7, #4] 8006514: 6a5b ldr r3, [r3, #36] @ 0x24 8006516: 2b00 cmp r3, #0 /* - Oversampling Ratio */ /* - Right bit shift */ /* - Left bit shift */ /* - Triggered mode */ /* - Oversampling mode (continued/resumed) */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, 8006518: 687b ldr r3, [r7, #4] 800651a: 681b ldr r3, [r3, #0] 800651c: 691a ldr r2, [r3, #16] 800651e: 4b14 ldr r3, [pc, #80] @ (8006570 ) 8006520: 4013 ands r3, r2 8006522: 687a ldr r2, [r7, #4] 8006524: 6bd2 ldr r2, [r2, #60] @ 0x3c 8006526: 3a01 subs r2, #1 8006528: 0411 lsls r1, r2, #16 800652a: 687a ldr r2, [r7, #4] 800652c: 6c12 ldr r2, [r2, #64] @ 0x40 800652e: 4311 orrs r1, r2 8006530: 687a ldr r2, [r7, #4] 8006532: 6c52 ldr r2, [r2, #68] @ 0x44 8006534: 4311 orrs r1, r2 8006536: 687a ldr r2, [r7, #4] 8006538: 6c92 ldr r2, [r2, #72] @ 0x48 800653a: 430a orrs r2, r1 800653c: 431a orrs r2, r3 800653e: 687b ldr r3, [r7, #4] 8006540: 681b ldr r3, [r3, #0] 8006542: f042 0201 orr.w r2, r2, #1 8006546: 611a str r2, [r3, #16] 8006548: e01c b.n 8006584 800654a: bf00 nop 800654c: 24000034 .word 0x24000034 8006550: 053e2d63 .word 0x053e2d63 8006554: 40022000 .word 0x40022000 8006558: 40022100 .word 0x40022100 800655c: 58026000 .word 0x58026000 8006560: 40022300 .word 0x40022300 8006564: 58026300 .word 0x58026300 8006568: fff0c003 .word 0xfff0c003 800656c: ffffbffc .word 0xffffbffc 8006570: fc00f81e .word 0xfc00f81e } else { /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); 8006574: 687b ldr r3, [r7, #4] 8006576: 681b ldr r3, [r3, #0] 8006578: 691a ldr r2, [r3, #16] 800657a: 687b ldr r3, [r7, #4] 800657c: 681b ldr r3, [r3, #0] 800657e: f022 0201 bic.w r2, r2, #1 8006582: 611a str r2, [r3, #16] } /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift); 8006584: 687b ldr r3, [r7, #4] 8006586: 681b ldr r3, [r3, #0] 8006588: 691b ldr r3, [r3, #16] 800658a: f023 4170 bic.w r1, r3, #4026531840 @ 0xf0000000 800658e: 687b ldr r3, [r7, #4] 8006590: 6b5a ldr r2, [r3, #52] @ 0x34 8006592: 687b ldr r3, [r7, #4] 8006594: 681b ldr r3, [r3, #0] 8006596: 430a orrs r2, r1 8006598: 611a str r2, [r3, #16] /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); } #else /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); 800659a: 6878 ldr r0, [r7, #4] 800659c: f000 fde2 bl 8007164 /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 80065a0: 687b ldr r3, [r7, #4] 80065a2: 68db ldr r3, [r3, #12] 80065a4: 2b01 cmp r3, #1 80065a6: d10c bne.n 80065c2 { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); 80065a8: 687b ldr r3, [r7, #4] 80065aa: 681b ldr r3, [r3, #0] 80065ac: 6b1b ldr r3, [r3, #48] @ 0x30 80065ae: f023 010f bic.w r1, r3, #15 80065b2: 687b ldr r3, [r7, #4] 80065b4: 699b ldr r3, [r3, #24] 80065b6: 1e5a subs r2, r3, #1 80065b8: 687b ldr r3, [r7, #4] 80065ba: 681b ldr r3, [r3, #0] 80065bc: 430a orrs r2, r1 80065be: 631a str r2, [r3, #48] @ 0x30 80065c0: e007 b.n 80065d2 } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 80065c2: 687b ldr r3, [r7, #4] 80065c4: 681b ldr r3, [r3, #0] 80065c6: 6b1a ldr r2, [r3, #48] @ 0x30 80065c8: 687b ldr r3, [r7, #4] 80065ca: 681b ldr r3, [r3, #0] 80065cc: f022 020f bic.w r2, r2, #15 80065d0: 631a str r2, [r3, #48] @ 0x30 } /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); 80065d2: 687b ldr r3, [r7, #4] 80065d4: 6d5b ldr r3, [r3, #84] @ 0x54 80065d6: f023 0303 bic.w r3, r3, #3 80065da: f043 0201 orr.w r2, r3, #1 80065de: 687b ldr r3, [r7, #4] 80065e0: 655a str r2, [r3, #84] @ 0x54 80065e2: e007 b.n 80065f4 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80065e4: 687b ldr r3, [r7, #4] 80065e6: 6d5b ldr r3, [r3, #84] @ 0x54 80065e8: f043 0210 orr.w r2, r3, #16 80065ec: 687b ldr r3, [r7, #4] 80065ee: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 80065f0: 2301 movs r3, #1 80065f2: 77fb strb r3, [r7, #31] } /* Return function status */ return tmp_hal_status; 80065f4: 7ffb ldrb r3, [r7, #31] } 80065f6: 4618 mov r0, r3 80065f8: 3724 adds r7, #36 @ 0x24 80065fa: 46bd mov sp, r7 80065fc: bd90 pop {r4, r7, pc} 80065fe: bf00 nop 08006600 : * @param pData Destination Buffer address. * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { 8006600: b580 push {r7, lr} 8006602: b086 sub sp, #24 8006604: af00 add r7, sp, #0 8006606: 60f8 str r0, [r7, #12] 8006608: 60b9 str r1, [r7, #8] 800660a: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 800660c: 68fb ldr r3, [r7, #12] 800660e: 681b ldr r3, [r3, #0] 8006610: 4a55 ldr r2, [pc, #340] @ (8006768 ) 8006612: 4293 cmp r3, r2 8006614: d004 beq.n 8006620 8006616: 68fb ldr r3, [r7, #12] 8006618: 681b ldr r3, [r3, #0] 800661a: 4a54 ldr r2, [pc, #336] @ (800676c ) 800661c: 4293 cmp r3, r2 800661e: d101 bne.n 8006624 8006620: 4b53 ldr r3, [pc, #332] @ (8006770 ) 8006622: e000 b.n 8006626 8006624: 4b53 ldr r3, [pc, #332] @ (8006774 ) 8006626: 4618 mov r0, r3 8006628: f7ff fd64 bl 80060f4 800662c: 6138 str r0, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 800662e: 68fb ldr r3, [r7, #12] 8006630: 681b ldr r3, [r3, #0] 8006632: 4618 mov r0, r3 8006634: f7ff fe1c bl 8006270 8006638: 4603 mov r3, r0 800663a: 2b00 cmp r3, #0 800663c: f040 808c bne.w 8006758 { /* Process locked */ __HAL_LOCK(hadc); 8006640: 68fb ldr r3, [r7, #12] 8006642: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8006646: 2b01 cmp r3, #1 8006648: d101 bne.n 800664e 800664a: 2302 movs r3, #2 800664c: e087 b.n 800675e 800664e: 68fb ldr r3, [r7, #12] 8006650: 2201 movs r2, #1 8006652: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Ensure that multimode regular conversions are not enabled. */ /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8006656: 693b ldr r3, [r7, #16] 8006658: 2b00 cmp r3, #0 800665a: d005 beq.n 8006668 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) 800665c: 693b ldr r3, [r7, #16] 800665e: 2b05 cmp r3, #5 8006660: d002 beq.n 8006668 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) 8006662: 693b ldr r3, [r7, #16] 8006664: 2b09 cmp r3, #9 8006666: d170 bne.n 800674a ) { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8006668: 68f8 ldr r0, [r7, #12] 800666a: f000 fbfd bl 8006e68 800666e: 4603 mov r3, r0 8006670: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8006672: 7dfb ldrb r3, [r7, #23] 8006674: 2b00 cmp r3, #0 8006676: d163 bne.n 8006740 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8006678: 68fb ldr r3, [r7, #12] 800667a: 6d5a ldr r2, [r3, #84] @ 0x54 800667c: 4b3e ldr r3, [pc, #248] @ (8006778 ) 800667e: 4013 ands r3, r2 8006680: f443 7280 orr.w r2, r3, #256 @ 0x100 8006684: 68fb ldr r3, [r7, #12] 8006686: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_REG_BUSY); /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8006688: 68fb ldr r3, [r7, #12] 800668a: 681b ldr r3, [r3, #0] 800668c: 4a37 ldr r2, [pc, #220] @ (800676c ) 800668e: 4293 cmp r3, r2 8006690: d002 beq.n 8006698 8006692: 68fb ldr r3, [r7, #12] 8006694: 681b ldr r3, [r3, #0] 8006696: e000 b.n 800669a 8006698: 4b33 ldr r3, [pc, #204] @ (8006768 ) 800669a: 68fa ldr r2, [r7, #12] 800669c: 6812 ldr r2, [r2, #0] 800669e: 4293 cmp r3, r2 80066a0: d002 beq.n 80066a8 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 80066a2: 693b ldr r3, [r7, #16] 80066a4: 2b00 cmp r3, #0 80066a6: d105 bne.n 80066b4 ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 80066a8: 68fb ldr r3, [r7, #12] 80066aa: 6d5b ldr r3, [r3, #84] @ 0x54 80066ac: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 80066b0: 68fb ldr r3, [r7, #12] 80066b2: 655a str r2, [r3, #84] @ 0x54 } /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) 80066b4: 68fb ldr r3, [r7, #12] 80066b6: 6d5b ldr r3, [r3, #84] @ 0x54 80066b8: f403 5380 and.w r3, r3, #4096 @ 0x1000 80066bc: 2b00 cmp r3, #0 80066be: d006 beq.n 80066ce { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 80066c0: 68fb ldr r3, [r7, #12] 80066c2: 6d9b ldr r3, [r3, #88] @ 0x58 80066c4: f023 0206 bic.w r2, r3, #6 80066c8: 68fb ldr r3, [r7, #12] 80066ca: 659a str r2, [r3, #88] @ 0x58 80066cc: e002 b.n 80066d4 } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); 80066ce: 68fb ldr r3, [r7, #12] 80066d0: 2200 movs r2, #0 80066d2: 659a str r2, [r3, #88] @ 0x58 } /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 80066d4: 68fb ldr r3, [r7, #12] 80066d6: 6cdb ldr r3, [r3, #76] @ 0x4c 80066d8: 4a28 ldr r2, [pc, #160] @ (800677c ) 80066da: 63da str r2, [r3, #60] @ 0x3c /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 80066dc: 68fb ldr r3, [r7, #12] 80066de: 6cdb ldr r3, [r3, #76] @ 0x4c 80066e0: 4a27 ldr r2, [pc, #156] @ (8006780 ) 80066e2: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 80066e4: 68fb ldr r3, [r7, #12] 80066e6: 6cdb ldr r3, [r3, #76] @ 0x4c 80066e8: 4a26 ldr r2, [pc, #152] @ (8006784 ) 80066ea: 64da str r2, [r3, #76] @ 0x4c /* ADC start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 80066ec: 68fb ldr r3, [r7, #12] 80066ee: 681b ldr r3, [r3, #0] 80066f0: 221c movs r2, #28 80066f2: 601a str r2, [r3, #0] /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 80066f4: 68fb ldr r3, [r7, #12] 80066f6: 2200 movs r2, #0 80066f8: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* With DMA, overrun event is always considered as an error even if hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, ADC_IT_OVR is enabled. */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 80066fc: 68fb ldr r3, [r7, #12] 80066fe: 681b ldr r3, [r3, #0] 8006700: 685a ldr r2, [r3, #4] 8006702: 68fb ldr r3, [r7, #12] 8006704: 681b ldr r3, [r3, #0] 8006706: f042 0210 orr.w r2, r2, #16 800670a: 605a str r2, [r3, #4] { LL_ADC_REG_SetDataTransferMode(hadc->Instance, ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); } #else LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement); 800670c: 68fb ldr r3, [r7, #12] 800670e: 681a ldr r2, [r3, #0] 8006710: 68fb ldr r3, [r7, #12] 8006712: 6adb ldr r3, [r3, #44] @ 0x2c 8006714: 4619 mov r1, r3 8006716: 4610 mov r0, r2 8006718: f7ff fc89 bl 800602e #endif /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 800671c: 68fb ldr r3, [r7, #12] 800671e: 6cd8 ldr r0, [r3, #76] @ 0x4c 8006720: 68fb ldr r3, [r7, #12] 8006722: 681b ldr r3, [r3, #0] 8006724: 3340 adds r3, #64 @ 0x40 8006726: 4619 mov r1, r3 8006728: 68ba ldr r2, [r7, #8] 800672a: 687b ldr r3, [r7, #4] 800672c: f002 fa5e bl 8008bec 8006730: 4603 mov r3, r0 8006732: 75fb strb r3, [r7, #23] /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); 8006734: 68fb ldr r3, [r7, #12] 8006736: 681b ldr r3, [r3, #0] 8006738: 4618 mov r0, r3 800673a: f7ff fd85 bl 8006248 if (tmp_hal_status == HAL_OK) 800673e: e00d b.n 800675c } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 8006740: 68fb ldr r3, [r7, #12] 8006742: 2200 movs r2, #0 8006744: f883 2050 strb.w r2, [r3, #80] @ 0x50 if (tmp_hal_status == HAL_OK) 8006748: e008 b.n 800675c } } else { tmp_hal_status = HAL_ERROR; 800674a: 2301 movs r3, #1 800674c: 75fb strb r3, [r7, #23] /* Process unlocked */ __HAL_UNLOCK(hadc); 800674e: 68fb ldr r3, [r7, #12] 8006750: 2200 movs r2, #0 8006752: f883 2050 strb.w r2, [r3, #80] @ 0x50 8006756: e001 b.n 800675c } } else { tmp_hal_status = HAL_BUSY; 8006758: 2302 movs r3, #2 800675a: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800675c: 7dfb ldrb r3, [r7, #23] } 800675e: 4618 mov r0, r3 8006760: 3718 adds r7, #24 8006762: 46bd mov sp, r7 8006764: bd80 pop {r7, pc} 8006766: bf00 nop 8006768: 40022000 .word 0x40022000 800676c: 40022100 .word 0x40022100 8006770: 40022300 .word 0x40022300 8006774: 58026300 .word 0x58026300 8006778: fffff0fe .word 0xfffff0fe 800677c: 0800703b .word 0x0800703b 8006780: 08007113 .word 0x08007113 8006784: 0800712f .word 0x0800712f 08006788 : * @brief Conversion DMA half-transfer callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { 8006788: b480 push {r7} 800678a: b083 sub sp, #12 800678c: af00 add r7, sp, #0 800678e: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 8006790: bf00 nop 8006792: 370c adds r7, #12 8006794: 46bd mov sp, r7 8006796: f85d 7b04 ldr.w r7, [sp], #4 800679a: 4770 bx lr 0800679c : * (this function is also clearing overrun flag) * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 800679c: b480 push {r7} 800679e: b083 sub sp, #12 80067a0: af00 add r7, sp, #0 80067a2: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 80067a4: bf00 nop 80067a6: 370c adds r7, #12 80067a8: 46bd mov sp, r7 80067aa: f85d 7b04 ldr.w r7, [sp], #4 80067ae: 4770 bx lr 080067b0 : * @param hadc ADC handle * @param sConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { 80067b0: b590 push {r4, r7, lr} 80067b2: b0a1 sub sp, #132 @ 0x84 80067b4: af00 add r7, sp, #0 80067b6: 6078 str r0, [r7, #4] 80067b8: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80067ba: 2300 movs r3, #0 80067bc: f887 307f strb.w r3, [r7, #127] @ 0x7f uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0; 80067c0: 2300 movs r3, #0 80067c2: 60bb str r3, [r7, #8] /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); /* Verification of channel number */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) 80067c4: 683b ldr r3, [r7, #0] 80067c6: 68db ldr r3, [r3, #12] 80067c8: 4a65 ldr r2, [pc, #404] @ (8006960 ) 80067ca: 4293 cmp r3, r2 } #endif } /* Process locked */ __HAL_LOCK(hadc); 80067cc: 687b ldr r3, [r7, #4] 80067ce: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 80067d2: 2b01 cmp r3, #1 80067d4: d101 bne.n 80067da 80067d6: 2302 movs r3, #2 80067d8: e32e b.n 8006e38 80067da: 687b ldr r3, [r7, #4] 80067dc: 2201 movs r2, #1 80067de: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 80067e2: 687b ldr r3, [r7, #4] 80067e4: 681b ldr r3, [r3, #0] 80067e6: 4618 mov r0, r3 80067e8: f7ff fd42 bl 8006270 80067ec: 4603 mov r3, r0 80067ee: 2b00 cmp r3, #0 80067f0: f040 8313 bne.w 8006e1a { if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))) 80067f4: 683b ldr r3, [r7, #0] 80067f6: 681b ldr r3, [r3, #0] 80067f8: 2b00 cmp r3, #0 80067fa: db2c blt.n 8006856 /* ADC channels preselection */ hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); } #else /* ADC channels preselection */ hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); 80067fc: 683b ldr r3, [r7, #0] 80067fe: 681b ldr r3, [r3, #0] 8006800: f3c3 0313 ubfx r3, r3, #0, #20 8006804: 2b00 cmp r3, #0 8006806: d108 bne.n 800681a 8006808: 683b ldr r3, [r7, #0] 800680a: 681b ldr r3, [r3, #0] 800680c: 0e9b lsrs r3, r3, #26 800680e: f003 031f and.w r3, r3, #31 8006812: 2201 movs r2, #1 8006814: fa02 f303 lsl.w r3, r2, r3 8006818: e016 b.n 8006848 800681a: 683b ldr r3, [r7, #0] 800681c: 681b ldr r3, [r3, #0] 800681e: 667b str r3, [r7, #100] @ 0x64 uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006820: 6e7b ldr r3, [r7, #100] @ 0x64 8006822: fa93 f3a3 rbit r3, r3 8006826: 663b str r3, [r7, #96] @ 0x60 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 8006828: 6e3b ldr r3, [r7, #96] @ 0x60 800682a: 66bb str r3, [r7, #104] @ 0x68 optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 800682c: 6ebb ldr r3, [r7, #104] @ 0x68 800682e: 2b00 cmp r3, #0 8006830: d101 bne.n 8006836 { return 32U; 8006832: 2320 movs r3, #32 8006834: e003 b.n 800683e } return __builtin_clz(value); 8006836: 6ebb ldr r3, [r7, #104] @ 0x68 8006838: fab3 f383 clz r3, r3 800683c: b2db uxtb r3, r3 800683e: f003 031f and.w r3, r3, #31 8006842: 2201 movs r2, #1 8006844: fa02 f303 lsl.w r3, r2, r3 8006848: 687a ldr r2, [r7, #4] 800684a: 6812 ldr r2, [r2, #0] 800684c: 69d1 ldr r1, [r2, #28] 800684e: 687a ldr r2, [r7, #4] 8006850: 6812 ldr r2, [r2, #0] 8006852: 430b orrs r3, r1 8006854: 61d3 str r3, [r2, #28] #endif /* ADC_VER_V5_V90 */ } /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); 8006856: 687b ldr r3, [r7, #4] 8006858: 6818 ldr r0, [r3, #0] 800685a: 683b ldr r3, [r7, #0] 800685c: 6859 ldr r1, [r3, #4] 800685e: 683b ldr r3, [r7, #0] 8006860: 681b ldr r3, [r3, #0] 8006862: 461a mov r2, r3 8006864: f7ff fbb7 bl 8005fd6 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8006868: 687b ldr r3, [r7, #4] 800686a: 681b ldr r3, [r3, #0] 800686c: 4618 mov r0, r3 800686e: f7ff fcff bl 8006270 8006872: 67b8 str r0, [r7, #120] @ 0x78 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 8006874: 687b ldr r3, [r7, #4] 8006876: 681b ldr r3, [r3, #0] 8006878: 4618 mov r0, r3 800687a: f7ff fd0c bl 8006296 800687e: 6778 str r0, [r7, #116] @ 0x74 if ((tmp_adc_is_conversion_on_going_regular == 0UL) 8006880: 6fbb ldr r3, [r7, #120] @ 0x78 8006882: 2b00 cmp r3, #0 8006884: f040 80b8 bne.w 80069f8 && (tmp_adc_is_conversion_on_going_injected == 0UL) 8006888: 6f7b ldr r3, [r7, #116] @ 0x74 800688a: 2b00 cmp r3, #0 800688c: f040 80b4 bne.w 80069f8 ) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); 8006890: 687b ldr r3, [r7, #4] 8006892: 6818 ldr r0, [r3, #0] 8006894: 683b ldr r3, [r7, #0] 8006896: 6819 ldr r1, [r3, #0] 8006898: 683b ldr r3, [r7, #0] 800689a: 689b ldr r3, [r3, #8] 800689c: 461a mov r2, r3 800689e: f7ff fbd9 bl 8006054 tmpOffsetShifted = ADC3_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); } else #endif /* ADC_VER_V5_V90 */ { tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); 80068a2: 4b30 ldr r3, [pc, #192] @ (8006964 ) 80068a4: 681b ldr r3, [r3, #0] 80068a6: f003 4370 and.w r3, r3, #4026531840 @ 0xf0000000 80068aa: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80068ae: d10b bne.n 80068c8 80068b0: 683b ldr r3, [r7, #0] 80068b2: 695a ldr r2, [r3, #20] 80068b4: 687b ldr r3, [r7, #4] 80068b6: 681b ldr r3, [r3, #0] 80068b8: 68db ldr r3, [r3, #12] 80068ba: 089b lsrs r3, r3, #2 80068bc: f003 0307 and.w r3, r3, #7 80068c0: 005b lsls r3, r3, #1 80068c2: fa02 f303 lsl.w r3, r2, r3 80068c6: e01d b.n 8006904 80068c8: 687b ldr r3, [r7, #4] 80068ca: 681b ldr r3, [r3, #0] 80068cc: 68db ldr r3, [r3, #12] 80068ce: f003 0310 and.w r3, r3, #16 80068d2: 2b00 cmp r3, #0 80068d4: d10b bne.n 80068ee 80068d6: 683b ldr r3, [r7, #0] 80068d8: 695a ldr r2, [r3, #20] 80068da: 687b ldr r3, [r7, #4] 80068dc: 681b ldr r3, [r3, #0] 80068de: 68db ldr r3, [r3, #12] 80068e0: 089b lsrs r3, r3, #2 80068e2: f003 0307 and.w r3, r3, #7 80068e6: 005b lsls r3, r3, #1 80068e8: fa02 f303 lsl.w r3, r2, r3 80068ec: e00a b.n 8006904 80068ee: 683b ldr r3, [r7, #0] 80068f0: 695a ldr r2, [r3, #20] 80068f2: 687b ldr r3, [r7, #4] 80068f4: 681b ldr r3, [r3, #0] 80068f6: 68db ldr r3, [r3, #12] 80068f8: 089b lsrs r3, r3, #2 80068fa: f003 0304 and.w r3, r3, #4 80068fe: 005b lsls r3, r3, #1 8006900: fa02 f303 lsl.w r3, r2, r3 8006904: 673b str r3, [r7, #112] @ 0x70 } if (sConfig->OffsetNumber != ADC_OFFSET_NONE) 8006906: 683b ldr r3, [r7, #0] 8006908: 691b ldr r3, [r3, #16] 800690a: 2b04 cmp r3, #4 800690c: d02c beq.n 8006968 { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); 800690e: 687b ldr r3, [r7, #4] 8006910: 6818 ldr r0, [r3, #0] 8006912: 683b ldr r3, [r7, #0] 8006914: 6919 ldr r1, [r3, #16] 8006916: 683b ldr r3, [r7, #0] 8006918: 681a ldr r2, [r3, #0] 800691a: 6f3b ldr r3, [r7, #112] @ 0x70 800691c: f7ff faf4 bl 8005f08 else #endif /* ADC_VER_V5_V90 */ { assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation)); /* Set ADC selected offset signed saturation */ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); 8006920: 687b ldr r3, [r7, #4] 8006922: 6818 ldr r0, [r3, #0] 8006924: 683b ldr r3, [r7, #0] 8006926: 6919 ldr r1, [r3, #16] 8006928: 683b ldr r3, [r7, #0] 800692a: 7e5b ldrb r3, [r3, #25] 800692c: 2b01 cmp r3, #1 800692e: d102 bne.n 8006936 8006930: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 8006934: e000 b.n 8006938 8006936: 2300 movs r3, #0 8006938: 461a mov r2, r3 800693a: f7ff fb1e bl 8005f7a assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift)); /* Set ADC selected offset right shift */ LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); 800693e: 687b ldr r3, [r7, #4] 8006940: 6818 ldr r0, [r3, #0] 8006942: 683b ldr r3, [r7, #0] 8006944: 6919 ldr r1, [r3, #16] 8006946: 683b ldr r3, [r7, #0] 8006948: 7e1b ldrb r3, [r3, #24] 800694a: 2b01 cmp r3, #1 800694c: d102 bne.n 8006954 800694e: f44f 6300 mov.w r3, #2048 @ 0x800 8006952: e000 b.n 8006956 8006954: 2300 movs r3, #0 8006956: 461a mov r2, r3 8006958: f7ff faf6 bl 8005f48 800695c: e04c b.n 80069f8 800695e: bf00 nop 8006960: 47ff0000 .word 0x47ff0000 8006964: 5c001000 .word 0x5c001000 } } else #endif /* ADC_VER_V5_V90 */ { if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8006968: 687b ldr r3, [r7, #4] 800696a: 681b ldr r3, [r3, #0] 800696c: 6e1b ldr r3, [r3, #96] @ 0x60 800696e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006972: 683b ldr r3, [r7, #0] 8006974: 681b ldr r3, [r3, #0] 8006976: 069b lsls r3, r3, #26 8006978: 429a cmp r2, r3 800697a: d107 bne.n 800698c { CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE); 800697c: 687b ldr r3, [r7, #4] 800697e: 681b ldr r3, [r3, #0] 8006980: 6e1a ldr r2, [r3, #96] @ 0x60 8006982: 687b ldr r3, [r7, #4] 8006984: 681b ldr r3, [r3, #0] 8006986: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 800698a: 661a str r2, [r3, #96] @ 0x60 } if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 800698c: 687b ldr r3, [r7, #4] 800698e: 681b ldr r3, [r3, #0] 8006990: 6e5b ldr r3, [r3, #100] @ 0x64 8006992: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006996: 683b ldr r3, [r7, #0] 8006998: 681b ldr r3, [r3, #0] 800699a: 069b lsls r3, r3, #26 800699c: 429a cmp r2, r3 800699e: d107 bne.n 80069b0 { CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE); 80069a0: 687b ldr r3, [r7, #4] 80069a2: 681b ldr r3, [r3, #0] 80069a4: 6e5a ldr r2, [r3, #100] @ 0x64 80069a6: 687b ldr r3, [r7, #4] 80069a8: 681b ldr r3, [r3, #0] 80069aa: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 80069ae: 665a str r2, [r3, #100] @ 0x64 } if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 80069b0: 687b ldr r3, [r7, #4] 80069b2: 681b ldr r3, [r3, #0] 80069b4: 6e9b ldr r3, [r3, #104] @ 0x68 80069b6: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 80069ba: 683b ldr r3, [r7, #0] 80069bc: 681b ldr r3, [r3, #0] 80069be: 069b lsls r3, r3, #26 80069c0: 429a cmp r2, r3 80069c2: d107 bne.n 80069d4 { CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE); 80069c4: 687b ldr r3, [r7, #4] 80069c6: 681b ldr r3, [r3, #0] 80069c8: 6e9a ldr r2, [r3, #104] @ 0x68 80069ca: 687b ldr r3, [r7, #4] 80069cc: 681b ldr r3, [r3, #0] 80069ce: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 80069d2: 669a str r2, [r3, #104] @ 0x68 } if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 80069d4: 687b ldr r3, [r7, #4] 80069d6: 681b ldr r3, [r3, #0] 80069d8: 6edb ldr r3, [r3, #108] @ 0x6c 80069da: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 80069de: 683b ldr r3, [r7, #0] 80069e0: 681b ldr r3, [r3, #0] 80069e2: 069b lsls r3, r3, #26 80069e4: 429a cmp r2, r3 80069e6: d107 bne.n 80069f8 { CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE); 80069e8: 687b ldr r3, [r7, #4] 80069ea: 681b ldr r3, [r3, #0] 80069ec: 6eda ldr r2, [r3, #108] @ 0x6c 80069ee: 687b ldr r3, [r7, #4] 80069f0: 681b ldr r3, [r3, #0] 80069f2: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 80069f6: 66da str r2, [r3, #108] @ 0x6c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 80069f8: 687b ldr r3, [r7, #4] 80069fa: 681b ldr r3, [r3, #0] 80069fc: 4618 mov r0, r3 80069fe: f7ff fbfd bl 80061fc 8006a02: 4603 mov r3, r0 8006a04: 2b00 cmp r3, #0 8006a06: f040 8211 bne.w 8006e2c { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); 8006a0a: 687b ldr r3, [r7, #4] 8006a0c: 6818 ldr r0, [r3, #0] 8006a0e: 683b ldr r3, [r7, #0] 8006a10: 6819 ldr r1, [r3, #0] 8006a12: 683b ldr r3, [r7, #0] 8006a14: 68db ldr r3, [r3, #12] 8006a16: 461a mov r2, r3 8006a18: f7ff fb48 bl 80060ac /* Configuration of differential mode */ if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) 8006a1c: 683b ldr r3, [r7, #0] 8006a1e: 68db ldr r3, [r3, #12] 8006a20: 4aa1 ldr r2, [pc, #644] @ (8006ca8 ) 8006a22: 4293 cmp r3, r2 8006a24: f040 812e bne.w 8006c84 { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006a28: 687b ldr r3, [r7, #4] 8006a2a: 6818 ldr r0, [r3, #0] (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8006a2c: 683b ldr r3, [r7, #0] 8006a2e: 681b ldr r3, [r3, #0] 8006a30: f3c3 0313 ubfx r3, r3, #0, #20 8006a34: 2b00 cmp r3, #0 8006a36: d10b bne.n 8006a50 8006a38: 683b ldr r3, [r7, #0] 8006a3a: 681b ldr r3, [r3, #0] 8006a3c: 0e9b lsrs r3, r3, #26 8006a3e: 3301 adds r3, #1 8006a40: f003 031f and.w r3, r3, #31 8006a44: 2b09 cmp r3, #9 8006a46: bf94 ite ls 8006a48: 2301 movls r3, #1 8006a4a: 2300 movhi r3, #0 8006a4c: b2db uxtb r3, r3 8006a4e: e019 b.n 8006a84 8006a50: 683b ldr r3, [r7, #0] 8006a52: 681b ldr r3, [r3, #0] 8006a54: 65bb str r3, [r7, #88] @ 0x58 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006a56: 6dbb ldr r3, [r7, #88] @ 0x58 8006a58: fa93 f3a3 rbit r3, r3 8006a5c: 657b str r3, [r7, #84] @ 0x54 return result; 8006a5e: 6d7b ldr r3, [r7, #84] @ 0x54 8006a60: 65fb str r3, [r7, #92] @ 0x5c if (value == 0U) 8006a62: 6dfb ldr r3, [r7, #92] @ 0x5c 8006a64: 2b00 cmp r3, #0 8006a66: d101 bne.n 8006a6c return 32U; 8006a68: 2320 movs r3, #32 8006a6a: e003 b.n 8006a74 return __builtin_clz(value); 8006a6c: 6dfb ldr r3, [r7, #92] @ 0x5c 8006a6e: fab3 f383 clz r3, r3 8006a72: b2db uxtb r3, r3 8006a74: 3301 adds r3, #1 8006a76: f003 031f and.w r3, r3, #31 8006a7a: 2b09 cmp r3, #9 8006a7c: bf94 ite ls 8006a7e: 2301 movls r3, #1 8006a80: 2300 movhi r3, #0 8006a82: b2db uxtb r3, r3 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006a84: 2b00 cmp r3, #0 8006a86: d079 beq.n 8006b7c (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8006a88: 683b ldr r3, [r7, #0] 8006a8a: 681b ldr r3, [r3, #0] 8006a8c: f3c3 0313 ubfx r3, r3, #0, #20 8006a90: 2b00 cmp r3, #0 8006a92: d107 bne.n 8006aa4 8006a94: 683b ldr r3, [r7, #0] 8006a96: 681b ldr r3, [r3, #0] 8006a98: 0e9b lsrs r3, r3, #26 8006a9a: 3301 adds r3, #1 8006a9c: 069b lsls r3, r3, #26 8006a9e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006aa2: e015 b.n 8006ad0 8006aa4: 683b ldr r3, [r7, #0] 8006aa6: 681b ldr r3, [r3, #0] 8006aa8: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006aaa: 6cfb ldr r3, [r7, #76] @ 0x4c 8006aac: fa93 f3a3 rbit r3, r3 8006ab0: 64bb str r3, [r7, #72] @ 0x48 return result; 8006ab2: 6cbb ldr r3, [r7, #72] @ 0x48 8006ab4: 653b str r3, [r7, #80] @ 0x50 if (value == 0U) 8006ab6: 6d3b ldr r3, [r7, #80] @ 0x50 8006ab8: 2b00 cmp r3, #0 8006aba: d101 bne.n 8006ac0 return 32U; 8006abc: 2320 movs r3, #32 8006abe: e003 b.n 8006ac8 return __builtin_clz(value); 8006ac0: 6d3b ldr r3, [r7, #80] @ 0x50 8006ac2: fab3 f383 clz r3, r3 8006ac6: b2db uxtb r3, r3 8006ac8: 3301 adds r3, #1 8006aca: 069b lsls r3, r3, #26 8006acc: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006ad0: 683b ldr r3, [r7, #0] 8006ad2: 681b ldr r3, [r3, #0] 8006ad4: f3c3 0313 ubfx r3, r3, #0, #20 8006ad8: 2b00 cmp r3, #0 8006ada: d109 bne.n 8006af0 8006adc: 683b ldr r3, [r7, #0] 8006ade: 681b ldr r3, [r3, #0] 8006ae0: 0e9b lsrs r3, r3, #26 8006ae2: 3301 adds r3, #1 8006ae4: f003 031f and.w r3, r3, #31 8006ae8: 2101 movs r1, #1 8006aea: fa01 f303 lsl.w r3, r1, r3 8006aee: e017 b.n 8006b20 8006af0: 683b ldr r3, [r7, #0] 8006af2: 681b ldr r3, [r3, #0] 8006af4: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006af6: 6c3b ldr r3, [r7, #64] @ 0x40 8006af8: fa93 f3a3 rbit r3, r3 8006afc: 63fb str r3, [r7, #60] @ 0x3c return result; 8006afe: 6bfb ldr r3, [r7, #60] @ 0x3c 8006b00: 647b str r3, [r7, #68] @ 0x44 if (value == 0U) 8006b02: 6c7b ldr r3, [r7, #68] @ 0x44 8006b04: 2b00 cmp r3, #0 8006b06: d101 bne.n 8006b0c return 32U; 8006b08: 2320 movs r3, #32 8006b0a: e003 b.n 8006b14 return __builtin_clz(value); 8006b0c: 6c7b ldr r3, [r7, #68] @ 0x44 8006b0e: fab3 f383 clz r3, r3 8006b12: b2db uxtb r3, r3 8006b14: 3301 adds r3, #1 8006b16: f003 031f and.w r3, r3, #31 8006b1a: 2101 movs r1, #1 8006b1c: fa01 f303 lsl.w r3, r1, r3 8006b20: ea42 0103 orr.w r1, r2, r3 8006b24: 683b ldr r3, [r7, #0] 8006b26: 681b ldr r3, [r3, #0] 8006b28: f3c3 0313 ubfx r3, r3, #0, #20 8006b2c: 2b00 cmp r3, #0 8006b2e: d10a bne.n 8006b46 8006b30: 683b ldr r3, [r7, #0] 8006b32: 681b ldr r3, [r3, #0] 8006b34: 0e9b lsrs r3, r3, #26 8006b36: 3301 adds r3, #1 8006b38: f003 021f and.w r2, r3, #31 8006b3c: 4613 mov r3, r2 8006b3e: 005b lsls r3, r3, #1 8006b40: 4413 add r3, r2 8006b42: 051b lsls r3, r3, #20 8006b44: e018 b.n 8006b78 8006b46: 683b ldr r3, [r7, #0] 8006b48: 681b ldr r3, [r3, #0] 8006b4a: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006b4c: 6b7b ldr r3, [r7, #52] @ 0x34 8006b4e: fa93 f3a3 rbit r3, r3 8006b52: 633b str r3, [r7, #48] @ 0x30 return result; 8006b54: 6b3b ldr r3, [r7, #48] @ 0x30 8006b56: 63bb str r3, [r7, #56] @ 0x38 if (value == 0U) 8006b58: 6bbb ldr r3, [r7, #56] @ 0x38 8006b5a: 2b00 cmp r3, #0 8006b5c: d101 bne.n 8006b62 return 32U; 8006b5e: 2320 movs r3, #32 8006b60: e003 b.n 8006b6a return __builtin_clz(value); 8006b62: 6bbb ldr r3, [r7, #56] @ 0x38 8006b64: fab3 f383 clz r3, r3 8006b68: b2db uxtb r3, r3 8006b6a: 3301 adds r3, #1 8006b6c: f003 021f and.w r2, r3, #31 8006b70: 4613 mov r3, r2 8006b72: 005b lsls r3, r3, #1 8006b74: 4413 add r3, r2 8006b76: 051b lsls r3, r3, #20 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006b78: 430b orrs r3, r1 8006b7a: e07e b.n 8006c7a (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8006b7c: 683b ldr r3, [r7, #0] 8006b7e: 681b ldr r3, [r3, #0] 8006b80: f3c3 0313 ubfx r3, r3, #0, #20 8006b84: 2b00 cmp r3, #0 8006b86: d107 bne.n 8006b98 8006b88: 683b ldr r3, [r7, #0] 8006b8a: 681b ldr r3, [r3, #0] 8006b8c: 0e9b lsrs r3, r3, #26 8006b8e: 3301 adds r3, #1 8006b90: 069b lsls r3, r3, #26 8006b92: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006b96: e015 b.n 8006bc4 8006b98: 683b ldr r3, [r7, #0] 8006b9a: 681b ldr r3, [r3, #0] 8006b9c: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006b9e: 6abb ldr r3, [r7, #40] @ 0x28 8006ba0: fa93 f3a3 rbit r3, r3 8006ba4: 627b str r3, [r7, #36] @ 0x24 return result; 8006ba6: 6a7b ldr r3, [r7, #36] @ 0x24 8006ba8: 62fb str r3, [r7, #44] @ 0x2c if (value == 0U) 8006baa: 6afb ldr r3, [r7, #44] @ 0x2c 8006bac: 2b00 cmp r3, #0 8006bae: d101 bne.n 8006bb4 return 32U; 8006bb0: 2320 movs r3, #32 8006bb2: e003 b.n 8006bbc return __builtin_clz(value); 8006bb4: 6afb ldr r3, [r7, #44] @ 0x2c 8006bb6: fab3 f383 clz r3, r3 8006bba: b2db uxtb r3, r3 8006bbc: 3301 adds r3, #1 8006bbe: 069b lsls r3, r3, #26 8006bc0: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006bc4: 683b ldr r3, [r7, #0] 8006bc6: 681b ldr r3, [r3, #0] 8006bc8: f3c3 0313 ubfx r3, r3, #0, #20 8006bcc: 2b00 cmp r3, #0 8006bce: d109 bne.n 8006be4 8006bd0: 683b ldr r3, [r7, #0] 8006bd2: 681b ldr r3, [r3, #0] 8006bd4: 0e9b lsrs r3, r3, #26 8006bd6: 3301 adds r3, #1 8006bd8: f003 031f and.w r3, r3, #31 8006bdc: 2101 movs r1, #1 8006bde: fa01 f303 lsl.w r3, r1, r3 8006be2: e017 b.n 8006c14 8006be4: 683b ldr r3, [r7, #0] 8006be6: 681b ldr r3, [r3, #0] 8006be8: 61fb str r3, [r7, #28] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006bea: 69fb ldr r3, [r7, #28] 8006bec: fa93 f3a3 rbit r3, r3 8006bf0: 61bb str r3, [r7, #24] return result; 8006bf2: 69bb ldr r3, [r7, #24] 8006bf4: 623b str r3, [r7, #32] if (value == 0U) 8006bf6: 6a3b ldr r3, [r7, #32] 8006bf8: 2b00 cmp r3, #0 8006bfa: d101 bne.n 8006c00 return 32U; 8006bfc: 2320 movs r3, #32 8006bfe: e003 b.n 8006c08 return __builtin_clz(value); 8006c00: 6a3b ldr r3, [r7, #32] 8006c02: fab3 f383 clz r3, r3 8006c06: b2db uxtb r3, r3 8006c08: 3301 adds r3, #1 8006c0a: f003 031f and.w r3, r3, #31 8006c0e: 2101 movs r1, #1 8006c10: fa01 f303 lsl.w r3, r1, r3 8006c14: ea42 0103 orr.w r1, r2, r3 8006c18: 683b ldr r3, [r7, #0] 8006c1a: 681b ldr r3, [r3, #0] 8006c1c: f3c3 0313 ubfx r3, r3, #0, #20 8006c20: 2b00 cmp r3, #0 8006c22: d10d bne.n 8006c40 8006c24: 683b ldr r3, [r7, #0] 8006c26: 681b ldr r3, [r3, #0] 8006c28: 0e9b lsrs r3, r3, #26 8006c2a: 3301 adds r3, #1 8006c2c: f003 021f and.w r2, r3, #31 8006c30: 4613 mov r3, r2 8006c32: 005b lsls r3, r3, #1 8006c34: 4413 add r3, r2 8006c36: 3b1e subs r3, #30 8006c38: 051b lsls r3, r3, #20 8006c3a: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8006c3e: e01b b.n 8006c78 8006c40: 683b ldr r3, [r7, #0] 8006c42: 681b ldr r3, [r3, #0] 8006c44: 613b str r3, [r7, #16] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006c46: 693b ldr r3, [r7, #16] 8006c48: fa93 f3a3 rbit r3, r3 8006c4c: 60fb str r3, [r7, #12] return result; 8006c4e: 68fb ldr r3, [r7, #12] 8006c50: 617b str r3, [r7, #20] if (value == 0U) 8006c52: 697b ldr r3, [r7, #20] 8006c54: 2b00 cmp r3, #0 8006c56: d101 bne.n 8006c5c return 32U; 8006c58: 2320 movs r3, #32 8006c5a: e003 b.n 8006c64 return __builtin_clz(value); 8006c5c: 697b ldr r3, [r7, #20] 8006c5e: fab3 f383 clz r3, r3 8006c62: b2db uxtb r3, r3 8006c64: 3301 adds r3, #1 8006c66: f003 021f and.w r2, r3, #31 8006c6a: 4613 mov r3, r2 8006c6c: 005b lsls r3, r3, #1 8006c6e: 4413 add r3, r2 8006c70: 3b1e subs r3, #30 8006c72: 051b lsls r3, r3, #20 8006c74: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006c78: 430b orrs r3, r1 8006c7a: 683a ldr r2, [r7, #0] 8006c7c: 6892 ldr r2, [r2, #8] 8006c7e: 4619 mov r1, r3 8006c80: f7ff f9e8 bl 8006054 /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 8006c84: 683b ldr r3, [r7, #0] 8006c86: 681b ldr r3, [r3, #0] 8006c88: 2b00 cmp r3, #0 8006c8a: f280 80cf bge.w 8006e2c { /* Configuration of common ADC parameters */ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8006c8e: 687b ldr r3, [r7, #4] 8006c90: 681b ldr r3, [r3, #0] 8006c92: 4a06 ldr r2, [pc, #24] @ (8006cac ) 8006c94: 4293 cmp r3, r2 8006c96: d004 beq.n 8006ca2 8006c98: 687b ldr r3, [r7, #4] 8006c9a: 681b ldr r3, [r3, #0] 8006c9c: 4a04 ldr r2, [pc, #16] @ (8006cb0 ) 8006c9e: 4293 cmp r3, r2 8006ca0: d10a bne.n 8006cb8 8006ca2: 4b04 ldr r3, [pc, #16] @ (8006cb4 ) 8006ca4: e009 b.n 8006cba 8006ca6: bf00 nop 8006ca8: 47ff0000 .word 0x47ff0000 8006cac: 40022000 .word 0x40022000 8006cb0: 40022100 .word 0x40022100 8006cb4: 40022300 .word 0x40022300 8006cb8: 4b61 ldr r3, [pc, #388] @ (8006e40 ) 8006cba: 4618 mov r0, r3 8006cbc: f7ff f916 bl 8005eec 8006cc0: 66f8 str r0, [r7, #108] @ 0x6c /* Software is allowed to change common parameters only when all ADCs */ /* of the common group are disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8006cc2: 687b ldr r3, [r7, #4] 8006cc4: 681b ldr r3, [r3, #0] 8006cc6: 4a5f ldr r2, [pc, #380] @ (8006e44 ) 8006cc8: 4293 cmp r3, r2 8006cca: d004 beq.n 8006cd6 8006ccc: 687b ldr r3, [r7, #4] 8006cce: 681b ldr r3, [r3, #0] 8006cd0: 4a5d ldr r2, [pc, #372] @ (8006e48 ) 8006cd2: 4293 cmp r3, r2 8006cd4: d10e bne.n 8006cf4 8006cd6: 485b ldr r0, [pc, #364] @ (8006e44 ) 8006cd8: f7ff fa90 bl 80061fc 8006cdc: 4604 mov r4, r0 8006cde: 485a ldr r0, [pc, #360] @ (8006e48 ) 8006ce0: f7ff fa8c bl 80061fc 8006ce4: 4603 mov r3, r0 8006ce6: 4323 orrs r3, r4 8006ce8: 2b00 cmp r3, #0 8006cea: bf0c ite eq 8006cec: 2301 moveq r3, #1 8006cee: 2300 movne r3, #0 8006cf0: b2db uxtb r3, r3 8006cf2: e008 b.n 8006d06 8006cf4: 4855 ldr r0, [pc, #340] @ (8006e4c ) 8006cf6: f7ff fa81 bl 80061fc 8006cfa: 4603 mov r3, r0 8006cfc: 2b00 cmp r3, #0 8006cfe: bf0c ite eq 8006d00: 2301 moveq r3, #1 8006d02: 2300 movne r3, #0 8006d04: b2db uxtb r3, r3 8006d06: 2b00 cmp r3, #0 8006d08: d07d beq.n 8006e06 { /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 8006d0a: 683b ldr r3, [r7, #0] 8006d0c: 681b ldr r3, [r3, #0] 8006d0e: 4a50 ldr r2, [pc, #320] @ (8006e50 ) 8006d10: 4293 cmp r3, r2 8006d12: d130 bne.n 8006d76 8006d14: 6efb ldr r3, [r7, #108] @ 0x6c 8006d16: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8006d1a: 2b00 cmp r3, #0 8006d1c: d12b bne.n 8006d76 { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8006d1e: 687b ldr r3, [r7, #4] 8006d20: 681b ldr r3, [r3, #0] 8006d22: 4a4a ldr r2, [pc, #296] @ (8006e4c ) 8006d24: 4293 cmp r3, r2 8006d26: f040 8081 bne.w 8006e2c { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); 8006d2a: 687b ldr r3, [r7, #4] 8006d2c: 681b ldr r3, [r3, #0] 8006d2e: 4a45 ldr r2, [pc, #276] @ (8006e44 ) 8006d30: 4293 cmp r3, r2 8006d32: d004 beq.n 8006d3e 8006d34: 687b ldr r3, [r7, #4] 8006d36: 681b ldr r3, [r3, #0] 8006d38: 4a43 ldr r2, [pc, #268] @ (8006e48 ) 8006d3a: 4293 cmp r3, r2 8006d3c: d101 bne.n 8006d42 8006d3e: 4a45 ldr r2, [pc, #276] @ (8006e54 ) 8006d40: e000 b.n 8006d44 8006d42: 4a3f ldr r2, [pc, #252] @ (8006e40 ) 8006d44: 6efb ldr r3, [r7, #108] @ 0x6c 8006d46: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 8006d4a: 4619 mov r1, r3 8006d4c: 4610 mov r0, r2 8006d4e: f7ff f8ba bl 8005ec6 /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8006d52: 4b41 ldr r3, [pc, #260] @ (8006e58 ) 8006d54: 681b ldr r3, [r3, #0] 8006d56: 099b lsrs r3, r3, #6 8006d58: 4a40 ldr r2, [pc, #256] @ (8006e5c ) 8006d5a: fba2 2303 umull r2, r3, r2, r3 8006d5e: 099b lsrs r3, r3, #6 8006d60: 3301 adds r3, #1 8006d62: 005b lsls r3, r3, #1 8006d64: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8006d66: e002 b.n 8006d6e { wait_loop_index--; 8006d68: 68bb ldr r3, [r7, #8] 8006d6a: 3b01 subs r3, #1 8006d6c: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8006d6e: 68bb ldr r3, [r7, #8] 8006d70: 2b00 cmp r3, #0 8006d72: d1f9 bne.n 8006d68 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8006d74: e05a b.n 8006e2c } } } else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 8006d76: 683b ldr r3, [r7, #0] 8006d78: 681b ldr r3, [r3, #0] 8006d7a: 4a39 ldr r2, [pc, #228] @ (8006e60 ) 8006d7c: 4293 cmp r3, r2 8006d7e: d11e bne.n 8006dbe 8006d80: 6efb ldr r3, [r7, #108] @ 0x6c 8006d82: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8006d86: 2b00 cmp r3, #0 8006d88: d119 bne.n 8006dbe { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 8006d8a: 687b ldr r3, [r7, #4] 8006d8c: 681b ldr r3, [r3, #0] 8006d8e: 4a2f ldr r2, [pc, #188] @ (8006e4c ) 8006d90: 4293 cmp r3, r2 8006d92: d14b bne.n 8006e2c { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); 8006d94: 687b ldr r3, [r7, #4] 8006d96: 681b ldr r3, [r3, #0] 8006d98: 4a2a ldr r2, [pc, #168] @ (8006e44 ) 8006d9a: 4293 cmp r3, r2 8006d9c: d004 beq.n 8006da8 8006d9e: 687b ldr r3, [r7, #4] 8006da0: 681b ldr r3, [r3, #0] 8006da2: 4a29 ldr r2, [pc, #164] @ (8006e48 ) 8006da4: 4293 cmp r3, r2 8006da6: d101 bne.n 8006dac 8006da8: 4a2a ldr r2, [pc, #168] @ (8006e54 ) 8006daa: e000 b.n 8006dae 8006dac: 4a24 ldr r2, [pc, #144] @ (8006e40 ) 8006dae: 6efb ldr r3, [r7, #108] @ 0x6c 8006db0: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8006db4: 4619 mov r1, r3 8006db6: 4610 mov r0, r2 8006db8: f7ff f885 bl 8005ec6 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 8006dbc: e036 b.n 8006e2c } } else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) 8006dbe: 683b ldr r3, [r7, #0] 8006dc0: 681b ldr r3, [r3, #0] 8006dc2: 4a28 ldr r2, [pc, #160] @ (8006e64 ) 8006dc4: 4293 cmp r3, r2 8006dc6: d131 bne.n 8006e2c 8006dc8: 6efb ldr r3, [r7, #108] @ 0x6c 8006dca: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8006dce: 2b00 cmp r3, #0 8006dd0: d12c bne.n 8006e2c { if (ADC_VREFINT_INSTANCE(hadc)) 8006dd2: 687b ldr r3, [r7, #4] 8006dd4: 681b ldr r3, [r3, #0] 8006dd6: 4a1d ldr r2, [pc, #116] @ (8006e4c ) 8006dd8: 4293 cmp r3, r2 8006dda: d127 bne.n 8006e2c { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); 8006ddc: 687b ldr r3, [r7, #4] 8006dde: 681b ldr r3, [r3, #0] 8006de0: 4a18 ldr r2, [pc, #96] @ (8006e44 ) 8006de2: 4293 cmp r3, r2 8006de4: d004 beq.n 8006df0 8006de6: 687b ldr r3, [r7, #4] 8006de8: 681b ldr r3, [r3, #0] 8006dea: 4a17 ldr r2, [pc, #92] @ (8006e48 ) 8006dec: 4293 cmp r3, r2 8006dee: d101 bne.n 8006df4 8006df0: 4a18 ldr r2, [pc, #96] @ (8006e54 ) 8006df2: e000 b.n 8006df6 8006df4: 4a12 ldr r2, [pc, #72] @ (8006e40 ) 8006df6: 6efb ldr r3, [r7, #108] @ 0x6c 8006df8: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8006dfc: 4619 mov r1, r3 8006dfe: 4610 mov r0, r2 8006e00: f7ff f861 bl 8005ec6 8006e04: e012 b.n 8006e2c /* enabled and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8006e06: 687b ldr r3, [r7, #4] 8006e08: 6d5b ldr r3, [r3, #84] @ 0x54 8006e0a: f043 0220 orr.w r2, r3, #32 8006e0e: 687b ldr r3, [r7, #4] 8006e10: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8006e12: 2301 movs r3, #1 8006e14: f887 307f strb.w r3, [r7, #127] @ 0x7f 8006e18: e008 b.n 8006e2c /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8006e1a: 687b ldr r3, [r7, #4] 8006e1c: 6d5b ldr r3, [r3, #84] @ 0x54 8006e1e: f043 0220 orr.w r2, r3, #32 8006e22: 687b ldr r3, [r7, #4] 8006e24: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8006e26: 2301 movs r3, #1 8006e28: f887 307f strb.w r3, [r7, #127] @ 0x7f } /* Process unlocked */ __HAL_UNLOCK(hadc); 8006e2c: 687b ldr r3, [r7, #4] 8006e2e: 2200 movs r2, #0 8006e30: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 8006e34: f897 307f ldrb.w r3, [r7, #127] @ 0x7f } 8006e38: 4618 mov r0, r3 8006e3a: 3784 adds r7, #132 @ 0x84 8006e3c: 46bd mov sp, r7 8006e3e: bd90 pop {r4, r7, pc} 8006e40: 58026300 .word 0x58026300 8006e44: 40022000 .word 0x40022000 8006e48: 40022100 .word 0x40022100 8006e4c: 58026000 .word 0x58026000 8006e50: cb840000 .word 0xcb840000 8006e54: 40022300 .word 0x40022300 8006e58: 24000034 .word 0x24000034 8006e5c: 053e2d63 .word 0x053e2d63 8006e60: c7520000 .word 0xc7520000 8006e64: cfb80000 .word 0xcfb80000 08006e68 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { 8006e68: b580 push {r7, lr} 8006e6a: b084 sub sp, #16 8006e6c: af00 add r7, sp, #0 8006e6e: 6078 str r0, [r7, #4] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8006e70: 687b ldr r3, [r7, #4] 8006e72: 681b ldr r3, [r3, #0] 8006e74: 4618 mov r0, r3 8006e76: f7ff f9c1 bl 80061fc 8006e7a: 4603 mov r3, r0 8006e7c: 2b00 cmp r3, #0 8006e7e: d16e bne.n 8006f5e { /* Check if conditions to enable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) 8006e80: 687b ldr r3, [r7, #4] 8006e82: 681b ldr r3, [r3, #0] 8006e84: 689a ldr r2, [r3, #8] 8006e86: 4b38 ldr r3, [pc, #224] @ (8006f68 ) 8006e88: 4013 ands r3, r2 8006e8a: 2b00 cmp r3, #0 8006e8c: d00d beq.n 8006eaa { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006e8e: 687b ldr r3, [r7, #4] 8006e90: 6d5b ldr r3, [r3, #84] @ 0x54 8006e92: f043 0210 orr.w r2, r3, #16 8006e96: 687b ldr r3, [r7, #4] 8006e98: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006e9a: 687b ldr r3, [r7, #4] 8006e9c: 6d9b ldr r3, [r3, #88] @ 0x58 8006e9e: f043 0201 orr.w r2, r3, #1 8006ea2: 687b ldr r3, [r7, #4] 8006ea4: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006ea6: 2301 movs r3, #1 8006ea8: e05a b.n 8006f60 } /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); 8006eaa: 687b ldr r3, [r7, #4] 8006eac: 681b ldr r3, [r3, #0] 8006eae: 4618 mov r0, r3 8006eb0: f7ff f97c bl 80061ac /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); 8006eb4: f7fe ffa2 bl 8005dfc 8006eb8: 60f8 str r0, [r7, #12] /* Poll for ADC ready flag raised except case of multimode enabled and ADC slave selected. */ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8006eba: 687b ldr r3, [r7, #4] 8006ebc: 681b ldr r3, [r3, #0] 8006ebe: 4a2b ldr r2, [pc, #172] @ (8006f6c ) 8006ec0: 4293 cmp r3, r2 8006ec2: d004 beq.n 8006ece 8006ec4: 687b ldr r3, [r7, #4] 8006ec6: 681b ldr r3, [r3, #0] 8006ec8: 4a29 ldr r2, [pc, #164] @ (8006f70 ) 8006eca: 4293 cmp r3, r2 8006ecc: d101 bne.n 8006ed2 8006ece: 4b29 ldr r3, [pc, #164] @ (8006f74 ) 8006ed0: e000 b.n 8006ed4 8006ed2: 4b29 ldr r3, [pc, #164] @ (8006f78 ) 8006ed4: 4618 mov r0, r3 8006ed6: f7ff f90d bl 80060f4 8006eda: 60b8 str r0, [r7, #8] if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8006edc: 687b ldr r3, [r7, #4] 8006ede: 681b ldr r3, [r3, #0] 8006ee0: 4a23 ldr r2, [pc, #140] @ (8006f70 ) 8006ee2: 4293 cmp r3, r2 8006ee4: d002 beq.n 8006eec 8006ee6: 687b ldr r3, [r7, #4] 8006ee8: 681b ldr r3, [r3, #0] 8006eea: e000 b.n 8006eee 8006eec: 4b1f ldr r3, [pc, #124] @ (8006f6c ) 8006eee: 687a ldr r2, [r7, #4] 8006ef0: 6812 ldr r2, [r2, #0] 8006ef2: 4293 cmp r3, r2 8006ef4: d02c beq.n 8006f50 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8006ef6: 68bb ldr r3, [r7, #8] 8006ef8: 2b00 cmp r3, #0 8006efa: d130 bne.n 8006f5e ) { while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8006efc: e028 b.n 8006f50 The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ /* Note: Test of ADC enabled required due to hardware constraint to */ /* not enable ADC if already enabled. */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8006efe: 687b ldr r3, [r7, #4] 8006f00: 681b ldr r3, [r3, #0] 8006f02: 4618 mov r0, r3 8006f04: f7ff f97a bl 80061fc 8006f08: 4603 mov r3, r0 8006f0a: 2b00 cmp r3, #0 8006f0c: d104 bne.n 8006f18 { LL_ADC_Enable(hadc->Instance); 8006f0e: 687b ldr r3, [r7, #4] 8006f10: 681b ldr r3, [r3, #0] 8006f12: 4618 mov r0, r3 8006f14: f7ff f94a bl 80061ac } if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8006f18: f7fe ff70 bl 8005dfc 8006f1c: 4602 mov r2, r0 8006f1e: 68fb ldr r3, [r7, #12] 8006f20: 1ad3 subs r3, r2, r3 8006f22: 2b02 cmp r3, #2 8006f24: d914 bls.n 8006f50 { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8006f26: 687b ldr r3, [r7, #4] 8006f28: 681b ldr r3, [r3, #0] 8006f2a: 681b ldr r3, [r3, #0] 8006f2c: f003 0301 and.w r3, r3, #1 8006f30: 2b01 cmp r3, #1 8006f32: d00d beq.n 8006f50 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006f34: 687b ldr r3, [r7, #4] 8006f36: 6d5b ldr r3, [r3, #84] @ 0x54 8006f38: f043 0210 orr.w r2, r3, #16 8006f3c: 687b ldr r3, [r7, #4] 8006f3e: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006f40: 687b ldr r3, [r7, #4] 8006f42: 6d9b ldr r3, [r3, #88] @ 0x58 8006f44: f043 0201 orr.w r2, r3, #1 8006f48: 687b ldr r3, [r7, #4] 8006f4a: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006f4c: 2301 movs r3, #1 8006f4e: e007 b.n 8006f60 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8006f50: 687b ldr r3, [r7, #4] 8006f52: 681b ldr r3, [r3, #0] 8006f54: 681b ldr r3, [r3, #0] 8006f56: f003 0301 and.w r3, r3, #1 8006f5a: 2b01 cmp r3, #1 8006f5c: d1cf bne.n 8006efe } } } /* Return HAL status */ return HAL_OK; 8006f5e: 2300 movs r3, #0 } 8006f60: 4618 mov r0, r3 8006f62: 3710 adds r7, #16 8006f64: 46bd mov sp, r7 8006f66: bd80 pop {r7, pc} 8006f68: 8000003f .word 0x8000003f 8006f6c: 40022000 .word 0x40022000 8006f70: 40022100 .word 0x40022100 8006f74: 40022300 .word 0x40022300 8006f78: 58026300 .word 0x58026300 08006f7c : * stopped. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { 8006f7c: b580 push {r7, lr} 8006f7e: b084 sub sp, #16 8006f80: af00 add r7, sp, #0 8006f82: 6078 str r0, [r7, #4] uint32_t tickstart; const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); 8006f84: 687b ldr r3, [r7, #4] 8006f86: 681b ldr r3, [r3, #0] 8006f88: 4618 mov r0, r3 8006f8a: f7ff f94a bl 8006222 8006f8e: 60f8 str r0, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) 8006f90: 687b ldr r3, [r7, #4] 8006f92: 681b ldr r3, [r3, #0] 8006f94: 4618 mov r0, r3 8006f96: f7ff f931 bl 80061fc 8006f9a: 4603 mov r3, r0 8006f9c: 2b00 cmp r3, #0 8006f9e: d047 beq.n 8007030 && (tmp_adc_is_disable_on_going == 0UL) 8006fa0: 68fb ldr r3, [r7, #12] 8006fa2: 2b00 cmp r3, #0 8006fa4: d144 bne.n 8007030 ) { /* Check if conditions to disable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) 8006fa6: 687b ldr r3, [r7, #4] 8006fa8: 681b ldr r3, [r3, #0] 8006faa: 689b ldr r3, [r3, #8] 8006fac: f003 030d and.w r3, r3, #13 8006fb0: 2b01 cmp r3, #1 8006fb2: d10c bne.n 8006fce { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); 8006fb4: 687b ldr r3, [r7, #4] 8006fb6: 681b ldr r3, [r3, #0] 8006fb8: 4618 mov r0, r3 8006fba: f7ff f90b bl 80061d4 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); 8006fbe: 687b ldr r3, [r7, #4] 8006fc0: 681b ldr r3, [r3, #0] 8006fc2: 2203 movs r2, #3 8006fc4: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); 8006fc6: f7fe ff19 bl 8005dfc 8006fca: 60b8 str r0, [r7, #8] while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8006fcc: e029 b.n 8007022 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006fce: 687b ldr r3, [r7, #4] 8006fd0: 6d5b ldr r3, [r3, #84] @ 0x54 8006fd2: f043 0210 orr.w r2, r3, #16 8006fd6: 687b ldr r3, [r7, #4] 8006fd8: 655a str r2, [r3, #84] @ 0x54 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006fda: 687b ldr r3, [r7, #4] 8006fdc: 6d9b ldr r3, [r3, #88] @ 0x58 8006fde: f043 0201 orr.w r2, r3, #1 8006fe2: 687b ldr r3, [r7, #4] 8006fe4: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006fe6: 2301 movs r3, #1 8006fe8: e023 b.n 8007032 { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8006fea: f7fe ff07 bl 8005dfc 8006fee: 4602 mov r2, r0 8006ff0: 68bb ldr r3, [r7, #8] 8006ff2: 1ad3 subs r3, r2, r3 8006ff4: 2b02 cmp r3, #2 8006ff6: d914 bls.n 8007022 { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8006ff8: 687b ldr r3, [r7, #4] 8006ffa: 681b ldr r3, [r3, #0] 8006ffc: 689b ldr r3, [r3, #8] 8006ffe: f003 0301 and.w r3, r3, #1 8007002: 2b00 cmp r3, #0 8007004: d00d beq.n 8007022 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8007006: 687b ldr r3, [r7, #4] 8007008: 6d5b ldr r3, [r3, #84] @ 0x54 800700a: f043 0210 orr.w r2, r3, #16 800700e: 687b ldr r3, [r7, #4] 8007010: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8007012: 687b ldr r3, [r7, #4] 8007014: 6d9b ldr r3, [r3, #88] @ 0x58 8007016: f043 0201 orr.w r2, r3, #1 800701a: 687b ldr r3, [r7, #4] 800701c: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 800701e: 2301 movs r3, #1 8007020: e007 b.n 8007032 while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8007022: 687b ldr r3, [r7, #4] 8007024: 681b ldr r3, [r3, #0] 8007026: 689b ldr r3, [r3, #8] 8007028: f003 0301 and.w r3, r3, #1 800702c: 2b00 cmp r3, #0 800702e: d1dc bne.n 8006fea } } } /* Return HAL status */ return HAL_OK; 8007030: 2300 movs r3, #0 } 8007032: 4618 mov r0, r3 8007034: 3710 adds r7, #16 8007036: 46bd mov sp, r7 8007038: bd80 pop {r7, pc} 0800703a : * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 800703a: b580 push {r7, lr} 800703c: b084 sub sp, #16 800703e: af00 add r7, sp, #0 8007040: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8007042: 687b ldr r3, [r7, #4] 8007044: 6b9b ldr r3, [r3, #56] @ 0x38 8007046: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) 8007048: 68fb ldr r3, [r7, #12] 800704a: 6d5b ldr r3, [r3, #84] @ 0x54 800704c: f003 0350 and.w r3, r3, #80 @ 0x50 8007050: 2b00 cmp r3, #0 8007052: d14b bne.n 80070ec { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8007054: 68fb ldr r3, [r7, #12] 8007056: 6d5b ldr r3, [r3, #84] @ 0x54 8007058: f443 7200 orr.w r2, r3, #512 @ 0x200 800705c: 68fb ldr r3, [r7, #12] 800705e: 655a str r2, [r3, #84] @ 0x54 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ /* Is it the end of the regular sequence ? */ if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) 8007060: 68fb ldr r3, [r7, #12] 8007062: 681b ldr r3, [r3, #0] 8007064: 681b ldr r3, [r3, #0] 8007066: f003 0308 and.w r3, r3, #8 800706a: 2b00 cmp r3, #0 800706c: d021 beq.n 80070b2 { /* Are conversions software-triggered ? */ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) 800706e: 68fb ldr r3, [r7, #12] 8007070: 681b ldr r3, [r3, #0] 8007072: 4618 mov r0, r3 8007074: f7fe ff9c bl 8005fb0 8007078: 4603 mov r3, r0 800707a: 2b00 cmp r3, #0 800707c: d032 beq.n 80070e4 { /* Is CONT bit set ? */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) 800707e: 68fb ldr r3, [r7, #12] 8007080: 681b ldr r3, [r3, #0] 8007082: 68db ldr r3, [r3, #12] 8007084: f403 5300 and.w r3, r3, #8192 @ 0x2000 8007088: 2b00 cmp r3, #0 800708a: d12b bne.n 80070e4 { /* CONT bit is not set, no more conversions expected */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800708c: 68fb ldr r3, [r7, #12] 800708e: 6d5b ldr r3, [r3, #84] @ 0x54 8007090: f423 7280 bic.w r2, r3, #256 @ 0x100 8007094: 68fb ldr r3, [r7, #12] 8007096: 655a str r2, [r3, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 8007098: 68fb ldr r3, [r7, #12] 800709a: 6d5b ldr r3, [r3, #84] @ 0x54 800709c: f403 5380 and.w r3, r3, #4096 @ 0x1000 80070a0: 2b00 cmp r3, #0 80070a2: d11f bne.n 80070e4 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 80070a4: 68fb ldr r3, [r7, #12] 80070a6: 6d5b ldr r3, [r3, #84] @ 0x54 80070a8: f043 0201 orr.w r2, r3, #1 80070ac: 68fb ldr r3, [r7, #12] 80070ae: 655a str r2, [r3, #84] @ 0x54 80070b0: e018 b.n 80070e4 } else { /* DMA End of Transfer interrupt was triggered but conversions sequence is not over. If DMACFG is set to 0, conversions are stopped. */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL) 80070b2: 68fb ldr r3, [r7, #12] 80070b4: 681b ldr r3, [r3, #0] 80070b6: 68db ldr r3, [r3, #12] 80070b8: f003 0303 and.w r3, r3, #3 80070bc: 2b00 cmp r3, #0 80070be: d111 bne.n 80070e4 { /* DMACFG bit is not set, conversions are stopped. */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 80070c0: 68fb ldr r3, [r7, #12] 80070c2: 6d5b ldr r3, [r3, #84] @ 0x54 80070c4: f423 7280 bic.w r2, r3, #256 @ 0x100 80070c8: 68fb ldr r3, [r7, #12] 80070ca: 655a str r2, [r3, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 80070cc: 68fb ldr r3, [r7, #12] 80070ce: 6d5b ldr r3, [r3, #84] @ 0x54 80070d0: f403 5380 and.w r3, r3, #4096 @ 0x1000 80070d4: 2b00 cmp r3, #0 80070d6: d105 bne.n 80070e4 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 80070d8: 68fb ldr r3, [r7, #12] 80070da: 6d5b ldr r3, [r3, #84] @ 0x54 80070dc: f043 0201 orr.w r2, r3, #1 80070e0: 68fb ldr r3, [r7, #12] 80070e2: 655a str r2, [r3, #84] @ 0x54 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 80070e4: 68f8 ldr r0, [r7, #12] 80070e6: f7fa fb6f bl 80017c8 { /* Call ADC DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } } 80070ea: e00e b.n 800710a if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) 80070ec: 68fb ldr r3, [r7, #12] 80070ee: 6d5b ldr r3, [r3, #84] @ 0x54 80070f0: f003 0310 and.w r3, r3, #16 80070f4: 2b00 cmp r3, #0 80070f6: d003 beq.n 8007100 HAL_ADC_ErrorCallback(hadc); 80070f8: 68f8 ldr r0, [r7, #12] 80070fa: f7ff fb4f bl 800679c } 80070fe: e004 b.n 800710a hadc->DMA_Handle->XferErrorCallback(hdma); 8007100: 68fb ldr r3, [r7, #12] 8007102: 6cdb ldr r3, [r3, #76] @ 0x4c 8007104: 6cdb ldr r3, [r3, #76] @ 0x4c 8007106: 6878 ldr r0, [r7, #4] 8007108: 4798 blx r3 } 800710a: bf00 nop 800710c: 3710 adds r7, #16 800710e: 46bd mov sp, r7 8007110: bd80 pop {r7, pc} 08007112 : * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 8007112: b580 push {r7, lr} 8007114: b084 sub sp, #16 8007116: af00 add r7, sp, #0 8007118: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800711a: 687b ldr r3, [r7, #4] 800711c: 6b9b ldr r3, [r3, #56] @ 0x38 800711e: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 8007120: 68f8 ldr r0, [r7, #12] 8007122: f7ff fb31 bl 8006788 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8007126: bf00 nop 8007128: 3710 adds r7, #16 800712a: 46bd mov sp, r7 800712c: bd80 pop {r7, pc} 0800712e : * @brief DMA error callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 800712e: b580 push {r7, lr} 8007130: b084 sub sp, #16 8007132: af00 add r7, sp, #0 8007134: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8007136: 687b ldr r3, [r7, #4] 8007138: 6b9b ldr r3, [r3, #56] @ 0x38 800713a: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 800713c: 68fb ldr r3, [r7, #12] 800713e: 6d5b ldr r3, [r3, #84] @ 0x54 8007140: f043 0240 orr.w r2, r3, #64 @ 0x40 8007144: 68fb ldr r3, [r7, #12] 8007146: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 8007148: 68fb ldr r3, [r7, #12] 800714a: 6d9b ldr r3, [r3, #88] @ 0x58 800714c: f043 0204 orr.w r2, r3, #4 8007150: 68fb ldr r3, [r7, #12] 8007152: 659a str r2, [r3, #88] @ 0x58 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 8007154: 68f8 ldr r0, [r7, #12] 8007156: f7ff fb21 bl 800679c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800715a: bf00 nop 800715c: 3710 adds r7, #16 800715e: 46bd mov sp, r7 8007160: bd80 pop {r7, pc} ... 08007164 : * stopped. * @param hadc ADC handle * @retval None. */ void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc) { 8007164: b580 push {r7, lr} 8007166: b084 sub sp, #16 8007168: af00 add r7, sp, #0 800716a: 6078 str r0, [r7, #4] uint32_t freq; if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc)) 800716c: 687b ldr r3, [r7, #4] 800716e: 681b ldr r3, [r3, #0] 8007170: 4a7a ldr r2, [pc, #488] @ (800735c ) 8007172: 4293 cmp r3, r2 8007174: d004 beq.n 8007180 8007176: 687b ldr r3, [r7, #4] 8007178: 681b ldr r3, [r3, #0] 800717a: 4a79 ldr r2, [pc, #484] @ (8007360 ) 800717c: 4293 cmp r3, r2 800717e: d109 bne.n 8007194 8007180: 4b78 ldr r3, [pc, #480] @ (8007364 ) 8007182: 689b ldr r3, [r3, #8] 8007184: f403 3340 and.w r3, r3, #196608 @ 0x30000 8007188: 2b00 cmp r3, #0 800718a: bf14 ite ne 800718c: 2301 movne r3, #1 800718e: 2300 moveq r3, #0 8007190: b2db uxtb r3, r3 8007192: e008 b.n 80071a6 8007194: 4b74 ldr r3, [pc, #464] @ (8007368 ) 8007196: 689b ldr r3, [r3, #8] 8007198: f403 3340 and.w r3, r3, #196608 @ 0x30000 800719c: 2b00 cmp r3, #0 800719e: bf14 ite ne 80071a0: 2301 movne r3, #1 80071a2: 2300 moveq r3, #0 80071a4: b2db uxtb r3, r3 80071a6: 2b00 cmp r3, #0 80071a8: d01c beq.n 80071e4 { freq = HAL_RCC_GetHCLKFreq(); 80071aa: f005 fb47 bl 800c83c 80071ae: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 80071b0: 687b ldr r3, [r7, #4] 80071b2: 685b ldr r3, [r3, #4] 80071b4: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 80071b8: d010 beq.n 80071dc 80071ba: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 80071be: d873 bhi.n 80072a8 80071c0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80071c4: d002 beq.n 80071cc 80071c6: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 80071ca: d16d bne.n 80072a8 { case ADC_CLOCK_SYNC_PCLK_DIV1: case ADC_CLOCK_SYNC_PCLK_DIV2: freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos); 80071cc: 687b ldr r3, [r7, #4] 80071ce: 685b ldr r3, [r3, #4] 80071d0: 0c1b lsrs r3, r3, #16 80071d2: 68fa ldr r2, [r7, #12] 80071d4: fbb2 f3f3 udiv r3, r2, r3 80071d8: 60fb str r3, [r7, #12] break; 80071da: e068 b.n 80072ae case ADC_CLOCK_SYNC_PCLK_DIV4: freq /= 4UL; 80071dc: 68fb ldr r3, [r7, #12] 80071de: 089b lsrs r3, r3, #2 80071e0: 60fb str r3, [r7, #12] break; 80071e2: e064 b.n 80072ae break; } } else { freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC); 80071e4: f44f 2000 mov.w r0, #524288 @ 0x80000 80071e8: f04f 0100 mov.w r1, #0 80071ec: f006 fdb2 bl 800dd54 80071f0: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 80071f2: 687b ldr r3, [r7, #4] 80071f4: 685b ldr r3, [r3, #4] 80071f6: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 80071fa: d051 beq.n 80072a0 80071fc: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 8007200: d854 bhi.n 80072ac 8007202: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 8007206: d047 beq.n 8007298 8007208: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 800720c: d84e bhi.n 80072ac 800720e: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 8007212: d03d beq.n 8007290 8007214: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 8007218: d848 bhi.n 80072ac 800721a: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800721e: d033 beq.n 8007288 8007220: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8007224: d842 bhi.n 80072ac 8007226: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 800722a: d029 beq.n 8007280 800722c: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 8007230: d83c bhi.n 80072ac 8007232: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 8007236: d01a beq.n 800726e 8007238: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 800723c: d836 bhi.n 80072ac 800723e: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 8007242: d014 beq.n 800726e 8007244: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 8007248: d830 bhi.n 80072ac 800724a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800724e: d00e beq.n 800726e 8007250: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8007254: d82a bhi.n 80072ac 8007256: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 800725a: d008 beq.n 800726e 800725c: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8007260: d824 bhi.n 80072ac 8007262: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8007266: d002 beq.n 800726e 8007268: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 800726c: d11e bne.n 80072ac case ADC_CLOCK_ASYNC_DIV4: case ADC_CLOCK_ASYNC_DIV6: case ADC_CLOCK_ASYNC_DIV8: case ADC_CLOCK_ASYNC_DIV10: case ADC_CLOCK_ASYNC_DIV12: freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL); 800726e: 687b ldr r3, [r7, #4] 8007270: 685b ldr r3, [r3, #4] 8007272: 0c9b lsrs r3, r3, #18 8007274: 005b lsls r3, r3, #1 8007276: 68fa ldr r2, [r7, #12] 8007278: fbb2 f3f3 udiv r3, r2, r3 800727c: 60fb str r3, [r7, #12] break; 800727e: e016 b.n 80072ae case ADC_CLOCK_ASYNC_DIV16: freq /= 16UL; 8007280: 68fb ldr r3, [r7, #12] 8007282: 091b lsrs r3, r3, #4 8007284: 60fb str r3, [r7, #12] break; 8007286: e012 b.n 80072ae case ADC_CLOCK_ASYNC_DIV32: freq /= 32UL; 8007288: 68fb ldr r3, [r7, #12] 800728a: 095b lsrs r3, r3, #5 800728c: 60fb str r3, [r7, #12] break; 800728e: e00e b.n 80072ae case ADC_CLOCK_ASYNC_DIV64: freq /= 64UL; 8007290: 68fb ldr r3, [r7, #12] 8007292: 099b lsrs r3, r3, #6 8007294: 60fb str r3, [r7, #12] break; 8007296: e00a b.n 80072ae case ADC_CLOCK_ASYNC_DIV128: freq /= 128UL; 8007298: 68fb ldr r3, [r7, #12] 800729a: 09db lsrs r3, r3, #7 800729c: 60fb str r3, [r7, #12] break; 800729e: e006 b.n 80072ae case ADC_CLOCK_ASYNC_DIV256: freq /= 256UL; 80072a0: 68fb ldr r3, [r7, #12] 80072a2: 0a1b lsrs r3, r3, #8 80072a4: 60fb str r3, [r7, #12] break; 80072a6: e002 b.n 80072ae break; 80072a8: bf00 nop 80072aa: e000 b.n 80072ae default: break; 80072ac: bf00 nop else /* if(freq > 25000000UL) */ { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } #else if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */ 80072ae: f7fe fdb1 bl 8005e14 80072b2: 4603 mov r3, r0 80072b4: f241 0203 movw r2, #4099 @ 0x1003 80072b8: 4293 cmp r3, r2 80072ba: d815 bhi.n 80072e8 { if (freq > 20000000UL) 80072bc: 68fb ldr r3, [r7, #12] 80072be: 4a2b ldr r2, [pc, #172] @ (800736c ) 80072c0: 4293 cmp r3, r2 80072c2: d908 bls.n 80072d6 { SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 80072c4: 687b ldr r3, [r7, #4] 80072c6: 681b ldr r3, [r3, #0] 80072c8: 689a ldr r2, [r3, #8] 80072ca: 687b ldr r3, [r7, #4] 80072cc: 681b ldr r3, [r3, #0] 80072ce: f442 7280 orr.w r2, r2, #256 @ 0x100 80072d2: 609a str r2, [r3, #8] { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } } #endif /* ADC_VER_V5_3 */ } 80072d4: e03e b.n 8007354 CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 80072d6: 687b ldr r3, [r7, #4] 80072d8: 681b ldr r3, [r3, #0] 80072da: 689a ldr r2, [r3, #8] 80072dc: 687b ldr r3, [r7, #4] 80072de: 681b ldr r3, [r3, #0] 80072e0: f422 7280 bic.w r2, r2, #256 @ 0x100 80072e4: 609a str r2, [r3, #8] } 80072e6: e035 b.n 8007354 freq /= 2U; /* divider by 2 for Rev.V */ 80072e8: 68fb ldr r3, [r7, #12] 80072ea: 085b lsrs r3, r3, #1 80072ec: 60fb str r3, [r7, #12] if (freq <= 6250000UL) 80072ee: 68fb ldr r3, [r7, #12] 80072f0: 4a1f ldr r2, [pc, #124] @ (8007370 ) 80072f2: 4293 cmp r3, r2 80072f4: d808 bhi.n 8007308 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL); 80072f6: 687b ldr r3, [r7, #4] 80072f8: 681b ldr r3, [r3, #0] 80072fa: 689a ldr r2, [r3, #8] 80072fc: 687b ldr r3, [r7, #4] 80072fe: 681b ldr r3, [r3, #0] 8007300: f422 7240 bic.w r2, r2, #768 @ 0x300 8007304: 609a str r2, [r3, #8] } 8007306: e025 b.n 8007354 else if (freq <= 12500000UL) 8007308: 68fb ldr r3, [r7, #12] 800730a: 4a1a ldr r2, [pc, #104] @ (8007374 ) 800730c: 4293 cmp r3, r2 800730e: d80a bhi.n 8007326 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0); 8007310: 687b ldr r3, [r7, #4] 8007312: 681b ldr r3, [r3, #0] 8007314: 689b ldr r3, [r3, #8] 8007316: f423 7240 bic.w r2, r3, #768 @ 0x300 800731a: 687b ldr r3, [r7, #4] 800731c: 681b ldr r3, [r3, #0] 800731e: f442 7280 orr.w r2, r2, #256 @ 0x100 8007322: 609a str r2, [r3, #8] } 8007324: e016 b.n 8007354 else if (freq <= 25000000UL) 8007326: 68fb ldr r3, [r7, #12] 8007328: 4a13 ldr r2, [pc, #76] @ (8007378 ) 800732a: 4293 cmp r3, r2 800732c: d80a bhi.n 8007344 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1); 800732e: 687b ldr r3, [r7, #4] 8007330: 681b ldr r3, [r3, #0] 8007332: 689b ldr r3, [r3, #8] 8007334: f423 7240 bic.w r2, r3, #768 @ 0x300 8007338: 687b ldr r3, [r7, #4] 800733a: 681b ldr r3, [r3, #0] 800733c: f442 7200 orr.w r2, r2, #512 @ 0x200 8007340: 609a str r2, [r3, #8] } 8007342: e007 b.n 8007354 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); 8007344: 687b ldr r3, [r7, #4] 8007346: 681b ldr r3, [r3, #0] 8007348: 689a ldr r2, [r3, #8] 800734a: 687b ldr r3, [r7, #4] 800734c: 681b ldr r3, [r3, #0] 800734e: f442 7240 orr.w r2, r2, #768 @ 0x300 8007352: 609a str r2, [r3, #8] } 8007354: bf00 nop 8007356: 3710 adds r7, #16 8007358: 46bd mov sp, r7 800735a: bd80 pop {r7, pc} 800735c: 40022000 .word 0x40022000 8007360: 40022100 .word 0x40022100 8007364: 40022300 .word 0x40022300 8007368: 58026300 .word 0x58026300 800736c: 01312d00 .word 0x01312d00 8007370: 005f5e10 .word 0x005f5e10 8007374: 00bebc20 .word 0x00bebc20 8007378: 017d7840 .word 0x017d7840 0800737c : { 800737c: b480 push {r7} 800737e: b083 sub sp, #12 8007380: af00 add r7, sp, #0 8007382: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8007384: 687b ldr r3, [r7, #4] 8007386: 689b ldr r3, [r3, #8] 8007388: f003 0301 and.w r3, r3, #1 800738c: 2b01 cmp r3, #1 800738e: d101 bne.n 8007394 8007390: 2301 movs r3, #1 8007392: e000 b.n 8007396 8007394: 2300 movs r3, #0 } 8007396: 4618 mov r0, r3 8007398: 370c adds r7, #12 800739a: 46bd mov sp, r7 800739c: f85d 7b04 ldr.w r7, [sp], #4 80073a0: 4770 bx lr ... 080073a4 : { 80073a4: b480 push {r7} 80073a6: b085 sub sp, #20 80073a8: af00 add r7, sp, #0 80073aa: 60f8 str r0, [r7, #12] 80073ac: 60b9 str r1, [r7, #8] 80073ae: 607a str r2, [r7, #4] MODIFY_REG(ADCx->CR, 80073b0: 68fb ldr r3, [r7, #12] 80073b2: 689a ldr r2, [r3, #8] 80073b4: 4b09 ldr r3, [pc, #36] @ (80073dc ) 80073b6: 4013 ands r3, r2 80073b8: 68ba ldr r2, [r7, #8] 80073ba: f402 3180 and.w r1, r2, #65536 @ 0x10000 80073be: 687a ldr r2, [r7, #4] 80073c0: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 80073c4: 430a orrs r2, r1 80073c6: 4313 orrs r3, r2 80073c8: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 80073cc: 68fb ldr r3, [r7, #12] 80073ce: 609a str r2, [r3, #8] } 80073d0: bf00 nop 80073d2: 3714 adds r7, #20 80073d4: 46bd mov sp, r7 80073d6: f85d 7b04 ldr.w r7, [sp], #4 80073da: 4770 bx lr 80073dc: 3ffeffc0 .word 0x3ffeffc0 080073e0 : { 80073e0: b480 push {r7} 80073e2: b083 sub sp, #12 80073e4: af00 add r7, sp, #0 80073e6: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); 80073e8: 687b ldr r3, [r7, #4] 80073ea: 689b ldr r3, [r3, #8] 80073ec: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80073f0: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80073f4: d101 bne.n 80073fa 80073f6: 2301 movs r3, #1 80073f8: e000 b.n 80073fc 80073fa: 2300 movs r3, #0 } 80073fc: 4618 mov r0, r3 80073fe: 370c adds r7, #12 8007400: 46bd mov sp, r7 8007402: f85d 7b04 ldr.w r7, [sp], #4 8007406: 4770 bx lr 08007408 : { 8007408: b480 push {r7} 800740a: b083 sub sp, #12 800740c: af00 add r7, sp, #0 800740e: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8007410: 687b ldr r3, [r7, #4] 8007412: 689b ldr r3, [r3, #8] 8007414: f003 0304 and.w r3, r3, #4 8007418: 2b04 cmp r3, #4 800741a: d101 bne.n 8007420 800741c: 2301 movs r3, #1 800741e: e000 b.n 8007422 8007420: 2300 movs r3, #0 } 8007422: 4618 mov r0, r3 8007424: 370c adds r7, #12 8007426: 46bd mov sp, r7 8007428: f85d 7b04 ldr.w r7, [sp], #4 800742c: 4770 bx lr ... 08007430 : * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff) { 8007430: b580 push {r7, lr} 8007432: b086 sub sp, #24 8007434: af00 add r7, sp, #0 8007436: 60f8 str r0, [r7, #12] 8007438: 60b9 str r1, [r7, #8] 800743a: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; 800743c: 2300 movs r3, #0 800743e: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Process locked */ __HAL_LOCK(hadc); 8007440: 68fb ldr r3, [r7, #12] 8007442: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8007446: 2b01 cmp r3, #1 8007448: d101 bne.n 800744e 800744a: 2302 movs r3, #2 800744c: e04c b.n 80074e8 800744e: 68fb ldr r3, [r7, #12] 8007450: 2201 movs r2, #1 8007452: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Calibration prerequisite: ADC must be disabled. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); 8007456: 68f8 ldr r0, [r7, #12] 8007458: f7ff fd90 bl 8006f7c 800745c: 4603 mov r3, r0 800745e: 75fb strb r3, [r7, #23] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8007460: 7dfb ldrb r3, [r7, #23] 8007462: 2b00 cmp r3, #0 8007464: d135 bne.n 80074d2 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8007466: 68fb ldr r3, [r7, #12] 8007468: 6d5a ldr r2, [r3, #84] @ 0x54 800746a: 4b21 ldr r3, [pc, #132] @ (80074f0 ) 800746c: 4013 ands r3, r2 800746e: f043 0202 orr.w r2, r3, #2 8007472: 68fb ldr r3, [r7, #12] 8007474: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Start ADC calibration in mode single-ended or differential */ LL_ADC_StartCalibration(hadc->Instance, CalibrationMode, SingleDiff); 8007476: 68fb ldr r3, [r7, #12] 8007478: 681b ldr r3, [r3, #0] 800747a: 687a ldr r2, [r7, #4] 800747c: 68b9 ldr r1, [r7, #8] 800747e: 4618 mov r0, r3 8007480: f7ff ff90 bl 80073a4 /* Wait for calibration completion */ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 8007484: e014 b.n 80074b0 { wait_loop_index++; 8007486: 693b ldr r3, [r7, #16] 8007488: 3301 adds r3, #1 800748a: 613b str r3, [r7, #16] if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) 800748c: 693b ldr r3, [r7, #16] 800748e: 4a19 ldr r2, [pc, #100] @ (80074f4 ) 8007490: 4293 cmp r3, r2 8007492: d30d bcc.n 80074b0 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8007494: 68fb ldr r3, [r7, #12] 8007496: 6d5b ldr r3, [r3, #84] @ 0x54 8007498: f023 0312 bic.w r3, r3, #18 800749c: f043 0210 orr.w r2, r3, #16 80074a0: 68fb ldr r3, [r7, #12] 80074a2: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 80074a4: 68fb ldr r3, [r7, #12] 80074a6: 2200 movs r2, #0 80074a8: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 80074ac: 2301 movs r3, #1 80074ae: e01b b.n 80074e8 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 80074b0: 68fb ldr r3, [r7, #12] 80074b2: 681b ldr r3, [r3, #0] 80074b4: 4618 mov r0, r3 80074b6: f7ff ff93 bl 80073e0 80074ba: 4603 mov r3, r0 80074bc: 2b00 cmp r3, #0 80074be: d1e2 bne.n 8007486 } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80074c0: 68fb ldr r3, [r7, #12] 80074c2: 6d5b ldr r3, [r3, #84] @ 0x54 80074c4: f023 0303 bic.w r3, r3, #3 80074c8: f043 0201 orr.w r2, r3, #1 80074cc: 68fb ldr r3, [r7, #12] 80074ce: 655a str r2, [r3, #84] @ 0x54 80074d0: e005 b.n 80074de HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80074d2: 68fb ldr r3, [r7, #12] 80074d4: 6d5b ldr r3, [r3, #84] @ 0x54 80074d6: f043 0210 orr.w r2, r3, #16 80074da: 68fb ldr r3, [r7, #12] 80074dc: 655a str r2, [r3, #84] @ 0x54 /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } /* Process unlocked */ __HAL_UNLOCK(hadc); 80074de: 68fb ldr r3, [r7, #12] 80074e0: 2200 movs r2, #0 80074e2: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 80074e6: 7dfb ldrb r3, [r7, #23] } 80074e8: 4618 mov r0, r3 80074ea: 3718 adds r7, #24 80074ec: 46bd mov sp, r7 80074ee: bd80 pop {r7, pc} 80074f0: ffffeefd .word 0xffffeefd 80074f4: 25c3f800 .word 0x25c3f800 080074f8 : * @param hadc Master ADC handle * @param multimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { 80074f8: b590 push {r4, r7, lr} 80074fa: b09f sub sp, #124 @ 0x7c 80074fc: af00 add r7, sp, #0 80074fe: 6078 str r0, [r7, #4] 8007500: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8007502: 2300 movs r3, #0 8007504: f887 3077 strb.w r3, [r7, #119] @ 0x77 assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); 8007508: 687b ldr r3, [r7, #4] 800750a: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 800750e: 2b01 cmp r3, #1 8007510: d101 bne.n 8007516 8007512: 2302 movs r3, #2 8007514: e0be b.n 8007694 8007516: 687b ldr r3, [r7, #4] 8007518: 2201 movs r2, #1 800751a: f883 2050 strb.w r2, [r3, #80] @ 0x50 tmphadcSlave.State = HAL_ADC_STATE_RESET; 800751e: 2300 movs r3, #0 8007520: 65fb str r3, [r7, #92] @ 0x5c tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; 8007522: 2300 movs r3, #0 8007524: 663b str r3, [r7, #96] @ 0x60 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 8007526: 687b ldr r3, [r7, #4] 8007528: 681b ldr r3, [r3, #0] 800752a: 4a5c ldr r2, [pc, #368] @ (800769c ) 800752c: 4293 cmp r3, r2 800752e: d102 bne.n 8007536 8007530: 4b5b ldr r3, [pc, #364] @ (80076a0 ) 8007532: 60bb str r3, [r7, #8] 8007534: e001 b.n 800753a 8007536: 2300 movs r3, #0 8007538: 60bb str r3, [r7, #8] if (tmphadcSlave.Instance == NULL) 800753a: 68bb ldr r3, [r7, #8] 800753c: 2b00 cmp r3, #0 800753e: d10b bne.n 8007558 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8007540: 687b ldr r3, [r7, #4] 8007542: 6d5b ldr r3, [r3, #84] @ 0x54 8007544: f043 0220 orr.w r2, r3, #32 8007548: 687b ldr r3, [r7, #4] 800754a: 655a str r2, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hadc); 800754c: 687b ldr r3, [r7, #4] 800754e: 2200 movs r2, #0 8007550: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 8007554: 2301 movs r3, #1 8007556: e09d b.n 8007694 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DATA Format configuration */ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); 8007558: 68bb ldr r3, [r7, #8] 800755a: 4618 mov r0, r3 800755c: f7ff ff54 bl 8007408 8007560: 6738 str r0, [r7, #112] @ 0x70 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8007562: 687b ldr r3, [r7, #4] 8007564: 681b ldr r3, [r3, #0] 8007566: 4618 mov r0, r3 8007568: f7ff ff4e bl 8007408 800756c: 4603 mov r3, r0 800756e: 2b00 cmp r3, #0 8007570: d17f bne.n 8007672 && (tmphadcSlave_conversion_on_going == 0UL)) 8007572: 6f3b ldr r3, [r7, #112] @ 0x70 8007574: 2b00 cmp r3, #0 8007576: d17c bne.n 8007672 { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); 8007578: 687b ldr r3, [r7, #4] 800757a: 681b ldr r3, [r3, #0] 800757c: 4a47 ldr r2, [pc, #284] @ (800769c ) 800757e: 4293 cmp r3, r2 8007580: d004 beq.n 800758c 8007582: 687b ldr r3, [r7, #4] 8007584: 681b ldr r3, [r3, #0] 8007586: 4a46 ldr r2, [pc, #280] @ (80076a0 ) 8007588: 4293 cmp r3, r2 800758a: d101 bne.n 8007590 800758c: 4b45 ldr r3, [pc, #276] @ (80076a4 ) 800758e: e000 b.n 8007592 8007590: 4b45 ldr r3, [pc, #276] @ (80076a8 ) 8007592: 66fb str r3, [r7, #108] @ 0x6c /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if (multimode->Mode != ADC_MODE_INDEPENDENT) 8007594: 683b ldr r3, [r7, #0] 8007596: 681b ldr r3, [r3, #0] 8007598: 2b00 cmp r3, #0 800759a: d039 beq.n 8007610 { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData); 800759c: 6efb ldr r3, [r7, #108] @ 0x6c 800759e: 689b ldr r3, [r3, #8] 80075a0: f423 4240 bic.w r2, r3, #49152 @ 0xc000 80075a4: 683b ldr r3, [r7, #0] 80075a6: 685b ldr r3, [r3, #4] 80075a8: 431a orrs r2, r3 80075aa: 6efb ldr r3, [r7, #108] @ 0x6c 80075ac: 609a str r2, [r3, #8] /* from 1 to 8 clock cycles for 12 bits */ /* from 1 to 6 clock cycles for 10 and 8 bits */ /* If a higher delay is selected, it will be clipped to maximum delay */ /* range */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 80075ae: 687b ldr r3, [r7, #4] 80075b0: 681b ldr r3, [r3, #0] 80075b2: 4a3a ldr r2, [pc, #232] @ (800769c ) 80075b4: 4293 cmp r3, r2 80075b6: d004 beq.n 80075c2 80075b8: 687b ldr r3, [r7, #4] 80075ba: 681b ldr r3, [r3, #0] 80075bc: 4a38 ldr r2, [pc, #224] @ (80076a0 ) 80075be: 4293 cmp r3, r2 80075c0: d10e bne.n 80075e0 80075c2: 4836 ldr r0, [pc, #216] @ (800769c ) 80075c4: f7ff feda bl 800737c 80075c8: 4604 mov r4, r0 80075ca: 4835 ldr r0, [pc, #212] @ (80076a0 ) 80075cc: f7ff fed6 bl 800737c 80075d0: 4603 mov r3, r0 80075d2: 4323 orrs r3, r4 80075d4: 2b00 cmp r3, #0 80075d6: bf0c ite eq 80075d8: 2301 moveq r3, #1 80075da: 2300 movne r3, #0 80075dc: b2db uxtb r3, r3 80075de: e008 b.n 80075f2 80075e0: 4832 ldr r0, [pc, #200] @ (80076ac ) 80075e2: f7ff fecb bl 800737c 80075e6: 4603 mov r3, r0 80075e8: 2b00 cmp r3, #0 80075ea: bf0c ite eq 80075ec: 2301 moveq r3, #1 80075ee: 2300 movne r3, #0 80075f0: b2db uxtb r3, r3 80075f2: 2b00 cmp r3, #0 80075f4: d047 beq.n 8007686 { MODIFY_REG(tmpADC_Common->CCR, 80075f6: 6efb ldr r3, [r7, #108] @ 0x6c 80075f8: 689a ldr r2, [r3, #8] 80075fa: 4b2d ldr r3, [pc, #180] @ (80076b0 ) 80075fc: 4013 ands r3, r2 80075fe: 683a ldr r2, [r7, #0] 8007600: 6811 ldr r1, [r2, #0] 8007602: 683a ldr r2, [r7, #0] 8007604: 6892 ldr r2, [r2, #8] 8007606: 430a orrs r2, r1 8007608: 431a orrs r2, r3 800760a: 6efb ldr r3, [r7, #108] @ 0x6c 800760c: 609a str r2, [r3, #8] if (multimode->Mode != ADC_MODE_INDEPENDENT) 800760e: e03a b.n 8007686 ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF); 8007610: 6efb ldr r3, [r7, #108] @ 0x6c 8007612: 689b ldr r3, [r3, #8] 8007614: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8007618: 6efb ldr r3, [r7, #108] @ 0x6c 800761a: 609a str r2, [r3, #8] /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 800761c: 687b ldr r3, [r7, #4] 800761e: 681b ldr r3, [r3, #0] 8007620: 4a1e ldr r2, [pc, #120] @ (800769c ) 8007622: 4293 cmp r3, r2 8007624: d004 beq.n 8007630 8007626: 687b ldr r3, [r7, #4] 8007628: 681b ldr r3, [r3, #0] 800762a: 4a1d ldr r2, [pc, #116] @ (80076a0 ) 800762c: 4293 cmp r3, r2 800762e: d10e bne.n 800764e 8007630: 481a ldr r0, [pc, #104] @ (800769c ) 8007632: f7ff fea3 bl 800737c 8007636: 4604 mov r4, r0 8007638: 4819 ldr r0, [pc, #100] @ (80076a0 ) 800763a: f7ff fe9f bl 800737c 800763e: 4603 mov r3, r0 8007640: 4323 orrs r3, r4 8007642: 2b00 cmp r3, #0 8007644: bf0c ite eq 8007646: 2301 moveq r3, #1 8007648: 2300 movne r3, #0 800764a: b2db uxtb r3, r3 800764c: e008 b.n 8007660 800764e: 4817 ldr r0, [pc, #92] @ (80076ac ) 8007650: f7ff fe94 bl 800737c 8007654: 4603 mov r3, r0 8007656: 2b00 cmp r3, #0 8007658: bf0c ite eq 800765a: 2301 moveq r3, #1 800765c: 2300 movne r3, #0 800765e: b2db uxtb r3, r3 8007660: 2b00 cmp r3, #0 8007662: d010 beq.n 8007686 { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); 8007664: 6efb ldr r3, [r7, #108] @ 0x6c 8007666: 689a ldr r2, [r3, #8] 8007668: 4b11 ldr r3, [pc, #68] @ (80076b0 ) 800766a: 4013 ands r3, r2 800766c: 6efa ldr r2, [r7, #108] @ 0x6c 800766e: 6093 str r3, [r2, #8] if (multimode->Mode != ADC_MODE_INDEPENDENT) 8007670: e009 b.n 8007686 /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8007672: 687b ldr r3, [r7, #4] 8007674: 6d5b ldr r3, [r3, #84] @ 0x54 8007676: f043 0220 orr.w r2, r3, #32 800767a: 687b ldr r3, [r7, #4] 800767c: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 800767e: 2301 movs r3, #1 8007680: f887 3077 strb.w r3, [r7, #119] @ 0x77 8007684: e000 b.n 8007688 if (multimode->Mode != ADC_MODE_INDEPENDENT) 8007686: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); 8007688: 687b ldr r3, [r7, #4] 800768a: 2200 movs r2, #0 800768c: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 8007690: f897 3077 ldrb.w r3, [r7, #119] @ 0x77 } 8007694: 4618 mov r0, r3 8007696: 377c adds r7, #124 @ 0x7c 8007698: 46bd mov sp, r7 800769a: bd90 pop {r4, r7, pc} 800769c: 40022000 .word 0x40022000 80076a0: 40022100 .word 0x40022100 80076a4: 40022300 .word 0x40022300 80076a8: 58026300 .word 0x58026300 80076ac: 58026000 .word 0x58026000 80076b0: fffff0e0 .word 0xfffff0e0 080076b4 : * To unlock the configuration, perform a system reset. * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { 80076b4: b580 push {r7, lr} 80076b6: b088 sub sp, #32 80076b8: af00 add r7, sp, #0 80076ba: 6078 str r0, [r7, #4] uint32_t tmp_csr ; uint32_t exti_line ; uint32_t comp_voltage_scaler_initialized; /* Value "0" is comparator voltage scaler is not initialized */ __IO uint32_t wait_loop_index = 0UL; 80076bc: 2300 movs r3, #0 80076be: 60fb str r3, [r7, #12] HAL_StatusTypeDef status = HAL_OK; 80076c0: 2300 movs r3, #0 80076c2: 77fb strb r3, [r7, #31] /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) 80076c4: 687b ldr r3, [r7, #4] 80076c6: 2b00 cmp r3, #0 80076c8: d102 bne.n 80076d0 { status = HAL_ERROR; 80076ca: 2301 movs r3, #1 80076cc: 77fb strb r3, [r7, #31] 80076ce: e10e b.n 80078ee } else if(__HAL_COMP_IS_LOCKED(hcomp)) 80076d0: 687b ldr r3, [r7, #4] 80076d2: 681b ldr r3, [r3, #0] 80076d4: 681b ldr r3, [r3, #0] 80076d6: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80076da: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80076de: d102 bne.n 80076e6 { status = HAL_ERROR; 80076e0: 2301 movs r3, #1 80076e2: 77fb strb r3, [r7, #31] 80076e4: e103 b.n 80078ee assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); if(hcomp->State == HAL_COMP_STATE_RESET) 80076e6: 687b ldr r3, [r7, #4] 80076e8: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 80076ec: b2db uxtb r3, r3 80076ee: 2b00 cmp r3, #0 80076f0: d109 bne.n 8007706 { /* Allocate lock resource and initialize it */ hcomp->Lock = HAL_UNLOCKED; 80076f2: 687b ldr r3, [r7, #4] 80076f4: 2200 movs r2, #0 80076f6: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Set COMP error code to none */ COMP_CLEAR_ERRORCODE(hcomp); 80076fa: 687b ldr r3, [r7, #4] 80076fc: 2200 movs r2, #0 80076fe: 629a str r2, [r3, #40] @ 0x28 /* Init the low level hardware */ hcomp->MspInitCallback(hcomp); #else /* Init the low level hardware */ HAL_COMP_MspInit(hcomp); 8007700: 6878 ldr r0, [r7, #4] 8007702: f7fc fca9 bl 8004058 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } /* Memorize voltage scaler state before initialization */ comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN); 8007706: 687b ldr r3, [r7, #4] 8007708: 681b ldr r3, [r3, #0] 800770a: 681b ldr r3, [r3, #0] 800770c: f003 0304 and.w r3, r3, #4 8007710: 61bb str r3, [r7, #24] /* Set BLANKING bits according to hcomp->Init.BlankingSrce value */ /* Set HYST bits according to hcomp->Init.Hysteresis value */ /* Set POLARITY bit according to hcomp->Init.OutputPol value */ /* Set POWERMODE bits according to hcomp->Init.Mode value */ tmp_csr = (hcomp->Init.InvertingInput | \ 8007712: 687b ldr r3, [r7, #4] 8007714: 691a ldr r2, [r3, #16] hcomp->Init.NonInvertingInput | \ 8007716: 687b ldr r3, [r7, #4] 8007718: 68db ldr r3, [r3, #12] tmp_csr = (hcomp->Init.InvertingInput | \ 800771a: 431a orrs r2, r3 hcomp->Init.BlankingSrce | \ 800771c: 687b ldr r3, [r7, #4] 800771e: 69db ldr r3, [r3, #28] hcomp->Init.NonInvertingInput | \ 8007720: 431a orrs r2, r3 hcomp->Init.Hysteresis | \ 8007722: 687b ldr r3, [r7, #4] 8007724: 695b ldr r3, [r3, #20] hcomp->Init.BlankingSrce | \ 8007726: 431a orrs r2, r3 hcomp->Init.OutputPol | \ 8007728: 687b ldr r3, [r7, #4] 800772a: 699b ldr r3, [r3, #24] hcomp->Init.Hysteresis | \ 800772c: 431a orrs r2, r3 hcomp->Init.Mode ); 800772e: 687b ldr r3, [r7, #4] 8007730: 689b ldr r3, [r3, #8] tmp_csr = (hcomp->Init.InvertingInput | \ 8007732: 4313 orrs r3, r2 8007734: 617b str r3, [r7, #20] COMP_CFGRx_INP2SEL | COMP_CFGRx_WINMODE | COMP_CFGRx_POLARITY | COMP_CFGRx_HYST | COMP_CFGRx_BLANKING | COMP_CFGRx_BRGEN | COMP_CFGRx_SCALEN, tmp_csr ); #else MODIFY_REG(hcomp->Instance->CFGR, 8007736: 687b ldr r3, [r7, #4] 8007738: 681b ldr r3, [r3, #0] 800773a: 681a ldr r2, [r3, #0] 800773c: 4b6e ldr r3, [pc, #440] @ (80078f8 ) 800773e: 4013 ands r3, r2 8007740: 687a ldr r2, [r7, #4] 8007742: 6812 ldr r2, [r2, #0] 8007744: 6979 ldr r1, [r7, #20] 8007746: 430b orrs r3, r1 8007748: 6013 str r3, [r2, #0] #endif /* Set window mode */ /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ /* instances. Therefore, this function can update another COMP */ /* instance that the one currently selected. */ if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) 800774a: 687b ldr r3, [r7, #4] 800774c: 685b ldr r3, [r3, #4] 800774e: 2b10 cmp r3, #16 8007750: d108 bne.n 8007764 { SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE); 8007752: 687b ldr r3, [r7, #4] 8007754: 681b ldr r3, [r3, #0] 8007756: 681a ldr r2, [r3, #0] 8007758: 687b ldr r3, [r7, #4] 800775a: 681b ldr r3, [r3, #0] 800775c: f042 0210 orr.w r2, r2, #16 8007760: 601a str r2, [r3, #0] 8007762: e007 b.n 8007774 } else { CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE); 8007764: 687b ldr r3, [r7, #4] 8007766: 681b ldr r3, [r3, #0] 8007768: 681a ldr r2, [r3, #0] 800776a: 687b ldr r3, [r7, #4] 800776c: 681b ldr r3, [r3, #0] 800776e: f022 0210 bic.w r2, r2, #16 8007772: 601a str r2, [r3, #0] } /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is enabled for the first time */ if ((READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN) != 0UL) && 8007774: 687b ldr r3, [r7, #4] 8007776: 681b ldr r3, [r3, #0] 8007778: 681b ldr r3, [r3, #0] 800777a: f003 0304 and.w r3, r3, #4 800777e: 2b00 cmp r3, #0 8007780: d016 beq.n 80077b0 8007782: 69bb ldr r3, [r7, #24] 8007784: 2b00 cmp r3, #0 8007786: d013 beq.n 80077b0 { /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles.*/ wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8007788: 4b5c ldr r3, [pc, #368] @ (80078fc ) 800778a: 681b ldr r3, [r3, #0] 800778c: 099b lsrs r3, r3, #6 800778e: 4a5c ldr r2, [pc, #368] @ (8007900 ) 8007790: fba2 2303 umull r2, r3, r2, r3 8007794: 099b lsrs r3, r3, #6 8007796: 1c5a adds r2, r3, #1 8007798: 4613 mov r3, r2 800779a: 009b lsls r3, r3, #2 800779c: 4413 add r3, r2 800779e: 009b lsls r3, r3, #2 80077a0: 60fb str r3, [r7, #12] while(wait_loop_index != 0UL) 80077a2: e002 b.n 80077aa { wait_loop_index --; 80077a4: 68fb ldr r3, [r7, #12] 80077a6: 3b01 subs r3, #1 80077a8: 60fb str r3, [r7, #12] while(wait_loop_index != 0UL) 80077aa: 68fb ldr r3, [r7, #12] 80077ac: 2b00 cmp r3, #0 80077ae: d1f9 bne.n 80077a4 } } /* Get the EXTI line corresponding to the selected COMP instance */ exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); 80077b0: 687b ldr r3, [r7, #4] 80077b2: 681b ldr r3, [r3, #0] 80077b4: 4a53 ldr r2, [pc, #332] @ (8007904 ) 80077b6: 4293 cmp r3, r2 80077b8: d102 bne.n 80077c0 80077ba: f44f 1380 mov.w r3, #1048576 @ 0x100000 80077be: e001 b.n 80077c4 80077c0: f44f 1300 mov.w r3, #2097152 @ 0x200000 80077c4: 613b str r3, [r7, #16] /* Manage EXTI settings */ if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) 80077c6: 687b ldr r3, [r7, #4] 80077c8: 6a1b ldr r3, [r3, #32] 80077ca: f003 0303 and.w r3, r3, #3 80077ce: 2b00 cmp r3, #0 80077d0: d06d beq.n 80078ae { /* Configure EXTI rising edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) 80077d2: 687b ldr r3, [r7, #4] 80077d4: 6a1b ldr r3, [r3, #32] 80077d6: f003 0310 and.w r3, r3, #16 80077da: 2b00 cmp r3, #0 80077dc: d008 beq.n 80077f0 { SET_BIT(EXTI->RTSR1, exti_line); 80077de: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80077e2: 681a ldr r2, [r3, #0] 80077e4: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80077e8: 693b ldr r3, [r7, #16] 80077ea: 4313 orrs r3, r2 80077ec: 600b str r3, [r1, #0] 80077ee: e008 b.n 8007802 } else { CLEAR_BIT(EXTI->RTSR1, exti_line); 80077f0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80077f4: 681a ldr r2, [r3, #0] 80077f6: 693b ldr r3, [r7, #16] 80077f8: 43db mvns r3, r3 80077fa: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80077fe: 4013 ands r3, r2 8007800: 600b str r3, [r1, #0] } /* Configure EXTI falling edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) 8007802: 687b ldr r3, [r7, #4] 8007804: 6a1b ldr r3, [r3, #32] 8007806: f003 0320 and.w r3, r3, #32 800780a: 2b00 cmp r3, #0 800780c: d008 beq.n 8007820 { SET_BIT(EXTI->FTSR1, exti_line); 800780e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007812: 685a ldr r2, [r3, #4] 8007814: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007818: 693b ldr r3, [r7, #16] 800781a: 4313 orrs r3, r2 800781c: 604b str r3, [r1, #4] 800781e: e008 b.n 8007832 } else { CLEAR_BIT(EXTI->FTSR1, exti_line); 8007820: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007824: 685a ldr r2, [r3, #4] 8007826: 693b ldr r3, [r7, #16] 8007828: 43db mvns r3, r3 800782a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800782e: 4013 ands r3, r2 8007830: 604b str r3, [r1, #4] } #if !defined (CORE_CM4) /* Clear COMP EXTI pending bit (if any) */ WRITE_REG(EXTI->PR1, exti_line); 8007832: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8007836: 693b ldr r3, [r7, #16] 8007838: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure EXTI event mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) 800783c: 687b ldr r3, [r7, #4] 800783e: 6a1b ldr r3, [r3, #32] 8007840: f003 0302 and.w r3, r3, #2 8007844: 2b00 cmp r3, #0 8007846: d00a beq.n 800785e { SET_BIT(EXTI->EMR1, exti_line); 8007848: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800784c: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 8007850: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007854: 693b ldr r3, [r7, #16] 8007856: 4313 orrs r3, r2 8007858: f8c1 3084 str.w r3, [r1, #132] @ 0x84 800785c: e00a b.n 8007874 } else { CLEAR_BIT(EXTI->EMR1, exti_line); 800785e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007862: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 8007866: 693b ldr r3, [r7, #16] 8007868: 43db mvns r3, r3 800786a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800786e: 4013 ands r3, r2 8007870: f8c1 3084 str.w r3, [r1, #132] @ 0x84 } /* Configure EXTI interrupt mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) 8007874: 687b ldr r3, [r7, #4] 8007876: 6a1b ldr r3, [r3, #32] 8007878: f003 0301 and.w r3, r3, #1 800787c: 2b00 cmp r3, #0 800787e: d00a beq.n 8007896 { SET_BIT(EXTI->IMR1, exti_line); 8007880: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007884: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 8007888: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800788c: 693b ldr r3, [r7, #16] 800788e: 4313 orrs r3, r2 8007890: f8c1 3080 str.w r3, [r1, #128] @ 0x80 8007894: e021 b.n 80078da } else { CLEAR_BIT(EXTI->IMR1, exti_line); 8007896: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800789a: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 800789e: 693b ldr r3, [r7, #16] 80078a0: 43db mvns r3, r3 80078a2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80078a6: 4013 ands r3, r2 80078a8: f8c1 3080 str.w r3, [r1, #128] @ 0x80 80078ac: e015 b.n 80078da } } else { /* Disable EXTI event mode */ CLEAR_BIT(EXTI->EMR1, exti_line); 80078ae: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80078b2: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 80078b6: 693b ldr r3, [r7, #16] 80078b8: 43db mvns r3, r3 80078ba: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80078be: 4013 ands r3, r2 80078c0: f8c1 3084 str.w r3, [r1, #132] @ 0x84 /* Disable EXTI interrupt mode */ CLEAR_BIT(EXTI->IMR1, exti_line); 80078c4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80078c8: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 80078cc: 693b ldr r3, [r7, #16] 80078ce: 43db mvns r3, r3 80078d0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80078d4: 4013 ands r3, r2 80078d6: f8c1 3080 str.w r3, [r1, #128] @ 0x80 } #endif /* Set HAL COMP handle state */ /* Note: Transition from state reset to state ready, */ /* otherwise (coming from state ready or busy) no state update. */ if (hcomp->State == HAL_COMP_STATE_RESET) 80078da: 687b ldr r3, [r7, #4] 80078dc: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 80078e0: b2db uxtb r3, r3 80078e2: 2b00 cmp r3, #0 80078e4: d103 bne.n 80078ee { hcomp->State = HAL_COMP_STATE_READY; 80078e6: 687b ldr r3, [r7, #4] 80078e8: 2201 movs r2, #1 80078ea: f883 2025 strb.w r2, [r3, #37] @ 0x25 } } return status; 80078ee: 7ffb ldrb r3, [r7, #31] } 80078f0: 4618 mov r0, r3 80078f2: 3720 adds r7, #32 80078f4: 46bd mov sp, r7 80078f6: bd80 pop {r7, pc} 80078f8: f0e8cce1 .word 0xf0e8cce1 80078fc: 24000034 .word 0x24000034 8007900: 053e2d63 .word 0x053e2d63 8007904: 5800380c .word 0x5800380c 08007908 : * @brief Start the comparator. * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { 8007908: b480 push {r7} 800790a: b085 sub sp, #20 800790c: af00 add r7, sp, #0 800790e: 6078 str r0, [r7, #4] __IO uint32_t wait_loop_index = 0UL; 8007910: 2300 movs r3, #0 8007912: 60bb str r3, [r7, #8] HAL_StatusTypeDef status = HAL_OK; 8007914: 2300 movs r3, #0 8007916: 73fb strb r3, [r7, #15] /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) 8007918: 687b ldr r3, [r7, #4] 800791a: 2b00 cmp r3, #0 800791c: d102 bne.n 8007924 { status = HAL_ERROR; 800791e: 2301 movs r3, #1 8007920: 73fb strb r3, [r7, #15] 8007922: e030 b.n 8007986 } else if(__HAL_COMP_IS_LOCKED(hcomp)) 8007924: 687b ldr r3, [r7, #4] 8007926: 681b ldr r3, [r3, #0] 8007928: 681b ldr r3, [r3, #0] 800792a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 800792e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007932: d102 bne.n 800793a { status = HAL_ERROR; 8007934: 2301 movs r3, #1 8007936: 73fb strb r3, [r7, #15] 8007938: e025 b.n 8007986 else { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); if(hcomp->State == HAL_COMP_STATE_READY) 800793a: 687b ldr r3, [r7, #4] 800793c: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8007940: b2db uxtb r3, r3 8007942: 2b01 cmp r3, #1 8007944: d11d bne.n 8007982 { /* Enable the selected comparator */ SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN); 8007946: 687b ldr r3, [r7, #4] 8007948: 681b ldr r3, [r3, #0] 800794a: 681a ldr r2, [r3, #0] 800794c: 687b ldr r3, [r7, #4] 800794e: 681b ldr r3, [r3, #0] 8007950: f042 0201 orr.w r2, r2, #1 8007954: 601a str r2, [r3, #0] /* Set HAL COMP handle state */ hcomp->State = HAL_COMP_STATE_BUSY; 8007956: 687b ldr r3, [r7, #4] 8007958: 2202 movs r2, #2 800795a: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Delay for COMP startup time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 800795e: 4b0d ldr r3, [pc, #52] @ (8007994 ) 8007960: 681b ldr r3, [r3, #0] 8007962: 099b lsrs r3, r3, #6 8007964: 4a0c ldr r2, [pc, #48] @ (8007998 ) 8007966: fba2 2303 umull r2, r3, r2, r3 800796a: 099b lsrs r3, r3, #6 800796c: 3301 adds r3, #1 800796e: 00db lsls r3, r3, #3 8007970: 60bb str r3, [r7, #8] while(wait_loop_index != 0UL) 8007972: e002 b.n 800797a { wait_loop_index--; 8007974: 68bb ldr r3, [r7, #8] 8007976: 3b01 subs r3, #1 8007978: 60bb str r3, [r7, #8] while(wait_loop_index != 0UL) 800797a: 68bb ldr r3, [r7, #8] 800797c: 2b00 cmp r3, #0 800797e: d1f9 bne.n 8007974 8007980: e001 b.n 8007986 } } else { status = HAL_ERROR; 8007982: 2301 movs r3, #1 8007984: 73fb strb r3, [r7, #15] } } return status; 8007986: 7bfb ldrb r3, [r7, #15] } 8007988: 4618 mov r0, r3 800798a: 3714 adds r7, #20 800798c: 46bd mov sp, r7 800798e: f85d 7b04 ldr.w r7, [sp], #4 8007992: 4770 bx lr 8007994: 24000034 .word 0x24000034 8007998: 053e2d63 .word 0x053e2d63 0800799c : * @arg @ref COMP_OUTPUT_LEVEL_LOW * @arg @ref COMP_OUTPUT_LEVEL_HIGH * */ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) { 800799c: b480 push {r7} 800799e: b083 sub sp, #12 80079a0: af00 add r7, sp, #0 80079a2: 6078 str r0, [r7, #4] /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); if (hcomp->Instance == COMP1) 80079a4: 687b ldr r3, [r7, #4] 80079a6: 681b ldr r3, [r3, #0] 80079a8: 4a09 ldr r2, [pc, #36] @ (80079d0 ) 80079aa: 4293 cmp r3, r2 80079ac: d104 bne.n 80079b8 { return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL)); 80079ae: 4b09 ldr r3, [pc, #36] @ (80079d4 ) 80079b0: 681b ldr r3, [r3, #0] 80079b2: f003 0301 and.w r3, r3, #1 80079b6: e004 b.n 80079c2 } else { return (uint32_t)((READ_BIT(COMP12->SR, COMP_SR_C2VAL))>> 1UL); 80079b8: 4b06 ldr r3, [pc, #24] @ (80079d4 ) 80079ba: 681b ldr r3, [r3, #0] 80079bc: 085b lsrs r3, r3, #1 80079be: f003 0301 and.w r3, r3, #1 } } 80079c2: 4618 mov r0, r3 80079c4: 370c adds r7, #12 80079c6: 46bd mov sp, r7 80079c8: f85d 7b04 ldr.w r7, [sp], #4 80079cc: 4770 bx lr 80079ce: bf00 nop 80079d0: 5800380c .word 0x5800380c 80079d4: 58003800 .word 0x58003800 080079d8 <__NVIC_SetPriorityGrouping>: { 80079d8: b480 push {r7} 80079da: b085 sub sp, #20 80079dc: af00 add r7, sp, #0 80079de: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80079e0: 687b ldr r3, [r7, #4] 80079e2: f003 0307 and.w r3, r3, #7 80079e6: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80079e8: 4b0b ldr r3, [pc, #44] @ (8007a18 <__NVIC_SetPriorityGrouping+0x40>) 80079ea: 68db ldr r3, [r3, #12] 80079ec: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80079ee: 68ba ldr r2, [r7, #8] 80079f0: f64f 03ff movw r3, #63743 @ 0xf8ff 80079f4: 4013 ands r3, r2 80079f6: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80079f8: 68fb ldr r3, [r7, #12] 80079fa: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80079fc: 68bb ldr r3, [r7, #8] 80079fe: 431a orrs r2, r3 reg_value = (reg_value | 8007a00: 4b06 ldr r3, [pc, #24] @ (8007a1c <__NVIC_SetPriorityGrouping+0x44>) 8007a02: 4313 orrs r3, r2 8007a04: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8007a06: 4a04 ldr r2, [pc, #16] @ (8007a18 <__NVIC_SetPriorityGrouping+0x40>) 8007a08: 68bb ldr r3, [r7, #8] 8007a0a: 60d3 str r3, [r2, #12] } 8007a0c: bf00 nop 8007a0e: 3714 adds r7, #20 8007a10: 46bd mov sp, r7 8007a12: f85d 7b04 ldr.w r7, [sp], #4 8007a16: 4770 bx lr 8007a18: e000ed00 .word 0xe000ed00 8007a1c: 05fa0000 .word 0x05fa0000 08007a20 <__NVIC_GetPriorityGrouping>: { 8007a20: b480 push {r7} 8007a22: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8007a24: 4b04 ldr r3, [pc, #16] @ (8007a38 <__NVIC_GetPriorityGrouping+0x18>) 8007a26: 68db ldr r3, [r3, #12] 8007a28: 0a1b lsrs r3, r3, #8 8007a2a: f003 0307 and.w r3, r3, #7 } 8007a2e: 4618 mov r0, r3 8007a30: 46bd mov sp, r7 8007a32: f85d 7b04 ldr.w r7, [sp], #4 8007a36: 4770 bx lr 8007a38: e000ed00 .word 0xe000ed00 08007a3c <__NVIC_EnableIRQ>: { 8007a3c: b480 push {r7} 8007a3e: b083 sub sp, #12 8007a40: af00 add r7, sp, #0 8007a42: 4603 mov r3, r0 8007a44: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8007a46: f9b7 3006 ldrsh.w r3, [r7, #6] 8007a4a: 2b00 cmp r3, #0 8007a4c: db0b blt.n 8007a66 <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8007a4e: 88fb ldrh r3, [r7, #6] 8007a50: f003 021f and.w r2, r3, #31 8007a54: 4907 ldr r1, [pc, #28] @ (8007a74 <__NVIC_EnableIRQ+0x38>) 8007a56: f9b7 3006 ldrsh.w r3, [r7, #6] 8007a5a: 095b lsrs r3, r3, #5 8007a5c: 2001 movs r0, #1 8007a5e: fa00 f202 lsl.w r2, r0, r2 8007a62: f841 2023 str.w r2, [r1, r3, lsl #2] } 8007a66: bf00 nop 8007a68: 370c adds r7, #12 8007a6a: 46bd mov sp, r7 8007a6c: f85d 7b04 ldr.w r7, [sp], #4 8007a70: 4770 bx lr 8007a72: bf00 nop 8007a74: e000e100 .word 0xe000e100 08007a78 <__NVIC_SetPriority>: { 8007a78: b480 push {r7} 8007a7a: b083 sub sp, #12 8007a7c: af00 add r7, sp, #0 8007a7e: 4603 mov r3, r0 8007a80: 6039 str r1, [r7, #0] 8007a82: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8007a84: f9b7 3006 ldrsh.w r3, [r7, #6] 8007a88: 2b00 cmp r3, #0 8007a8a: db0a blt.n 8007aa2 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8007a8c: 683b ldr r3, [r7, #0] 8007a8e: b2da uxtb r2, r3 8007a90: 490c ldr r1, [pc, #48] @ (8007ac4 <__NVIC_SetPriority+0x4c>) 8007a92: f9b7 3006 ldrsh.w r3, [r7, #6] 8007a96: 0112 lsls r2, r2, #4 8007a98: b2d2 uxtb r2, r2 8007a9a: 440b add r3, r1 8007a9c: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 8007aa0: e00a b.n 8007ab8 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8007aa2: 683b ldr r3, [r7, #0] 8007aa4: b2da uxtb r2, r3 8007aa6: 4908 ldr r1, [pc, #32] @ (8007ac8 <__NVIC_SetPriority+0x50>) 8007aa8: 88fb ldrh r3, [r7, #6] 8007aaa: f003 030f and.w r3, r3, #15 8007aae: 3b04 subs r3, #4 8007ab0: 0112 lsls r2, r2, #4 8007ab2: b2d2 uxtb r2, r2 8007ab4: 440b add r3, r1 8007ab6: 761a strb r2, [r3, #24] } 8007ab8: bf00 nop 8007aba: 370c adds r7, #12 8007abc: 46bd mov sp, r7 8007abe: f85d 7b04 ldr.w r7, [sp], #4 8007ac2: 4770 bx lr 8007ac4: e000e100 .word 0xe000e100 8007ac8: e000ed00 .word 0xe000ed00 08007acc : { 8007acc: b480 push {r7} 8007ace: b089 sub sp, #36 @ 0x24 8007ad0: af00 add r7, sp, #0 8007ad2: 60f8 str r0, [r7, #12] 8007ad4: 60b9 str r1, [r7, #8] 8007ad6: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8007ad8: 68fb ldr r3, [r7, #12] 8007ada: f003 0307 and.w r3, r3, #7 8007ade: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8007ae0: 69fb ldr r3, [r7, #28] 8007ae2: f1c3 0307 rsb r3, r3, #7 8007ae6: 2b04 cmp r3, #4 8007ae8: bf28 it cs 8007aea: 2304 movcs r3, #4 8007aec: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8007aee: 69fb ldr r3, [r7, #28] 8007af0: 3304 adds r3, #4 8007af2: 2b06 cmp r3, #6 8007af4: d902 bls.n 8007afc 8007af6: 69fb ldr r3, [r7, #28] 8007af8: 3b03 subs r3, #3 8007afa: e000 b.n 8007afe 8007afc: 2300 movs r3, #0 8007afe: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8007b00: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007b04: 69bb ldr r3, [r7, #24] 8007b06: fa02 f303 lsl.w r3, r2, r3 8007b0a: 43da mvns r2, r3 8007b0c: 68bb ldr r3, [r7, #8] 8007b0e: 401a ands r2, r3 8007b10: 697b ldr r3, [r7, #20] 8007b12: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8007b14: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8007b18: 697b ldr r3, [r7, #20] 8007b1a: fa01 f303 lsl.w r3, r1, r3 8007b1e: 43d9 mvns r1, r3 8007b20: 687b ldr r3, [r7, #4] 8007b22: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8007b24: 4313 orrs r3, r2 } 8007b26: 4618 mov r0, r3 8007b28: 3724 adds r7, #36 @ 0x24 8007b2a: 46bd mov sp, r7 8007b2c: f85d 7b04 ldr.w r7, [sp], #4 8007b30: 4770 bx lr 08007b32 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8007b32: b580 push {r7, lr} 8007b34: b082 sub sp, #8 8007b36: af00 add r7, sp, #0 8007b38: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8007b3a: 6878 ldr r0, [r7, #4] 8007b3c: f7ff ff4c bl 80079d8 <__NVIC_SetPriorityGrouping> } 8007b40: bf00 nop 8007b42: 3708 adds r7, #8 8007b44: 46bd mov sp, r7 8007b46: bd80 pop {r7, pc} 08007b48 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8007b48: b580 push {r7, lr} 8007b4a: b086 sub sp, #24 8007b4c: af00 add r7, sp, #0 8007b4e: 4603 mov r3, r0 8007b50: 60b9 str r1, [r7, #8] 8007b52: 607a str r2, [r7, #4] 8007b54: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8007b56: f7ff ff63 bl 8007a20 <__NVIC_GetPriorityGrouping> 8007b5a: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8007b5c: 687a ldr r2, [r7, #4] 8007b5e: 68b9 ldr r1, [r7, #8] 8007b60: 6978 ldr r0, [r7, #20] 8007b62: f7ff ffb3 bl 8007acc 8007b66: 4602 mov r2, r0 8007b68: f9b7 300e ldrsh.w r3, [r7, #14] 8007b6c: 4611 mov r1, r2 8007b6e: 4618 mov r0, r3 8007b70: f7ff ff82 bl 8007a78 <__NVIC_SetPriority> } 8007b74: bf00 nop 8007b76: 3718 adds r7, #24 8007b78: 46bd mov sp, r7 8007b7a: bd80 pop {r7, pc} 08007b7c : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8007b7c: b580 push {r7, lr} 8007b7e: b082 sub sp, #8 8007b80: af00 add r7, sp, #0 8007b82: 4603 mov r3, r0 8007b84: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8007b86: f9b7 3006 ldrsh.w r3, [r7, #6] 8007b8a: 4618 mov r0, r3 8007b8c: f7ff ff56 bl 8007a3c <__NVIC_EnableIRQ> } 8007b90: bf00 nop 8007b92: 3708 adds r7, #8 8007b94: 46bd mov sp, r7 8007b96: bd80 pop {r7, pc} 08007b98 : /** * @brief Disables the MPU * @retval None */ void HAL_MPU_Disable(void) { 8007b98: b480 push {r7} 8007b9a: af00 add r7, sp, #0 __ASM volatile ("dmb 0xF":::"memory"); 8007b9c: f3bf 8f5f dmb sy } 8007ba0: bf00 nop /* Make sure outstanding transfers are done */ __DMB(); /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 8007ba2: 4b07 ldr r3, [pc, #28] @ (8007bc0 ) 8007ba4: 6a5b ldr r3, [r3, #36] @ 0x24 8007ba6: 4a06 ldr r2, [pc, #24] @ (8007bc0 ) 8007ba8: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8007bac: 6253 str r3, [r2, #36] @ 0x24 /* Disable the MPU and clear the control register*/ MPU->CTRL = 0; 8007bae: 4b05 ldr r3, [pc, #20] @ (8007bc4 ) 8007bb0: 2200 movs r2, #0 8007bb2: 605a str r2, [r3, #4] } 8007bb4: bf00 nop 8007bb6: 46bd mov sp, r7 8007bb8: f85d 7b04 ldr.w r7, [sp], #4 8007bbc: 4770 bx lr 8007bbe: bf00 nop 8007bc0: e000ed00 .word 0xe000ed00 8007bc4: e000ed90 .word 0xe000ed90 08007bc8 : * @arg MPU_PRIVILEGED_DEFAULT * @arg MPU_HFNMI_PRIVDEF * @retval None */ void HAL_MPU_Enable(uint32_t MPU_Control) { 8007bc8: b480 push {r7} 8007bca: b083 sub sp, #12 8007bcc: af00 add r7, sp, #0 8007bce: 6078 str r0, [r7, #4] /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 8007bd0: 4a0b ldr r2, [pc, #44] @ (8007c00 ) 8007bd2: 687b ldr r3, [r7, #4] 8007bd4: f043 0301 orr.w r3, r3, #1 8007bd8: 6053 str r3, [r2, #4] /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 8007bda: 4b0a ldr r3, [pc, #40] @ (8007c04 ) 8007bdc: 6a5b ldr r3, [r3, #36] @ 0x24 8007bde: 4a09 ldr r2, [pc, #36] @ (8007c04 ) 8007be0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8007be4: 6253 str r3, [r2, #36] @ 0x24 __ASM volatile ("dsb 0xF":::"memory"); 8007be6: f3bf 8f4f dsb sy } 8007bea: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8007bec: f3bf 8f6f isb sy } 8007bf0: bf00 nop /* Ensure MPU setting take effects */ __DSB(); __ISB(); } 8007bf2: bf00 nop 8007bf4: 370c adds r7, #12 8007bf6: 46bd mov sp, r7 8007bf8: f85d 7b04 ldr.w r7, [sp], #4 8007bfc: 4770 bx lr 8007bfe: bf00 nop 8007c00: e000ed90 .word 0xe000ed90 8007c04: e000ed00 .word 0xe000ed00 08007c08 : * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) { 8007c08: b480 push {r7} 8007c0a: b083 sub sp, #12 8007c0c: af00 add r7, sp, #0 8007c0e: 6078 str r0, [r7, #4] assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; 8007c10: 687b ldr r3, [r7, #4] 8007c12: 785a ldrb r2, [r3, #1] 8007c14: 4b1b ldr r3, [pc, #108] @ (8007c84 ) 8007c16: 609a str r2, [r3, #8] /* Disable the Region */ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 8007c18: 4b1a ldr r3, [pc, #104] @ (8007c84 ) 8007c1a: 691b ldr r3, [r3, #16] 8007c1c: 4a19 ldr r2, [pc, #100] @ (8007c84 ) 8007c1e: f023 0301 bic.w r3, r3, #1 8007c22: 6113 str r3, [r2, #16] /* Apply configuration */ MPU->RBAR = MPU_Init->BaseAddress; 8007c24: 4a17 ldr r2, [pc, #92] @ (8007c84 ) 8007c26: 687b ldr r3, [r7, #4] 8007c28: 685b ldr r3, [r3, #4] 8007c2a: 60d3 str r3, [r2, #12] MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007c2c: 687b ldr r3, [r7, #4] 8007c2e: 7b1b ldrb r3, [r3, #12] 8007c30: 071a lsls r2, r3, #28 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 8007c32: 687b ldr r3, [r7, #4] 8007c34: 7adb ldrb r3, [r3, #11] 8007c36: 061b lsls r3, r3, #24 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007c38: 431a orrs r2, r3 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 8007c3a: 687b ldr r3, [r7, #4] 8007c3c: 7a9b ldrb r3, [r3, #10] 8007c3e: 04db lsls r3, r3, #19 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 8007c40: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8007c42: 687b ldr r3, [r7, #4] 8007c44: 7b5b ldrb r3, [r3, #13] 8007c46: 049b lsls r3, r3, #18 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 8007c48: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 8007c4a: 687b ldr r3, [r7, #4] 8007c4c: 7b9b ldrb r3, [r3, #14] 8007c4e: 045b lsls r3, r3, #17 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8007c50: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8007c52: 687b ldr r3, [r7, #4] 8007c54: 7bdb ldrb r3, [r3, #15] 8007c56: 041b lsls r3, r3, #16 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 8007c58: 431a orrs r2, r3 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 8007c5a: 687b ldr r3, [r7, #4] 8007c5c: 7a5b ldrb r3, [r3, #9] 8007c5e: 021b lsls r3, r3, #8 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8007c60: 431a orrs r2, r3 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8007c62: 687b ldr r3, [r7, #4] 8007c64: 7a1b ldrb r3, [r3, #8] 8007c66: 005b lsls r3, r3, #1 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 8007c68: 4313 orrs r3, r2 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); 8007c6a: 687a ldr r2, [r7, #4] 8007c6c: 7812 ldrb r2, [r2, #0] 8007c6e: 4611 mov r1, r2 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007c70: 4a04 ldr r2, [pc, #16] @ (8007c84 ) ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8007c72: 430b orrs r3, r1 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007c74: 6113 str r3, [r2, #16] } 8007c76: bf00 nop 8007c78: 370c adds r7, #12 8007c7a: 46bd mov sp, r7 8007c7c: f85d 7b04 ldr.w r7, [sp], #4 8007c80: 4770 bx lr 8007c82: bf00 nop 8007c84: e000ed90 .word 0xe000ed90 08007c88 : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 8007c88: b580 push {r7, lr} 8007c8a: b082 sub sp, #8 8007c8c: af00 add r7, sp, #0 8007c8e: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 8007c90: 687b ldr r3, [r7, #4] 8007c92: 2b00 cmp r3, #0 8007c94: d101 bne.n 8007c9a { return HAL_ERROR; 8007c96: 2301 movs r3, #1 8007c98: e054 b.n 8007d44 } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 8007c9a: 687b ldr r3, [r7, #4] 8007c9c: 7f5b ldrb r3, [r3, #29] 8007c9e: b2db uxtb r3, r3 8007ca0: 2b00 cmp r3, #0 8007ca2: d105 bne.n 8007cb0 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 8007ca4: 687b ldr r3, [r7, #4] 8007ca6: 2200 movs r2, #0 8007ca8: 771a strb r2, [r3, #28] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 8007caa: 6878 ldr r0, [r7, #4] 8007cac: f7fc fa1a bl 80040e4 } hcrc->State = HAL_CRC_STATE_BUSY; 8007cb0: 687b ldr r3, [r7, #4] 8007cb2: 2202 movs r2, #2 8007cb4: 775a strb r2, [r3, #29] /* check whether or not non-default generating polynomial has been * picked up by user */ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) 8007cb6: 687b ldr r3, [r7, #4] 8007cb8: 791b ldrb r3, [r3, #4] 8007cba: 2b00 cmp r3, #0 8007cbc: d10c bne.n 8007cd8 { /* initialize peripheral with default generating polynomial */ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); 8007cbe: 687b ldr r3, [r7, #4] 8007cc0: 681b ldr r3, [r3, #0] 8007cc2: 4a22 ldr r2, [pc, #136] @ (8007d4c ) 8007cc4: 615a str r2, [r3, #20] MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); 8007cc6: 687b ldr r3, [r7, #4] 8007cc8: 681b ldr r3, [r3, #0] 8007cca: 689a ldr r2, [r3, #8] 8007ccc: 687b ldr r3, [r7, #4] 8007cce: 681b ldr r3, [r3, #0] 8007cd0: f022 0218 bic.w r2, r2, #24 8007cd4: 609a str r2, [r3, #8] 8007cd6: e00c b.n 8007cf2 } else { /* initialize CRC peripheral with generating polynomial defined by user */ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) 8007cd8: 687b ldr r3, [r7, #4] 8007cda: 6899 ldr r1, [r3, #8] 8007cdc: 687b ldr r3, [r7, #4] 8007cde: 68db ldr r3, [r3, #12] 8007ce0: 461a mov r2, r3 8007ce2: 6878 ldr r0, [r7, #4] 8007ce4: f000 f948 bl 8007f78 8007ce8: 4603 mov r3, r0 8007cea: 2b00 cmp r3, #0 8007cec: d001 beq.n 8007cf2 { return HAL_ERROR; 8007cee: 2301 movs r3, #1 8007cf0: e028 b.n 8007d44 } /* check whether or not non-default CRC initial value has been * picked up by user */ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) 8007cf2: 687b ldr r3, [r7, #4] 8007cf4: 795b ldrb r3, [r3, #5] 8007cf6: 2b00 cmp r3, #0 8007cf8: d105 bne.n 8007d06 { WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); 8007cfa: 687b ldr r3, [r7, #4] 8007cfc: 681b ldr r3, [r3, #0] 8007cfe: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007d02: 611a str r2, [r3, #16] 8007d04: e004 b.n 8007d10 } else { WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); 8007d06: 687b ldr r3, [r7, #4] 8007d08: 681b ldr r3, [r3, #0] 8007d0a: 687a ldr r2, [r7, #4] 8007d0c: 6912 ldr r2, [r2, #16] 8007d0e: 611a str r2, [r3, #16] } /* set input data inversion mode */ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); 8007d10: 687b ldr r3, [r7, #4] 8007d12: 681b ldr r3, [r3, #0] 8007d14: 689b ldr r3, [r3, #8] 8007d16: f023 0160 bic.w r1, r3, #96 @ 0x60 8007d1a: 687b ldr r3, [r7, #4] 8007d1c: 695a ldr r2, [r3, #20] 8007d1e: 687b ldr r3, [r7, #4] 8007d20: 681b ldr r3, [r3, #0] 8007d22: 430a orrs r2, r1 8007d24: 609a str r2, [r3, #8] /* set output data inversion mode */ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); 8007d26: 687b ldr r3, [r7, #4] 8007d28: 681b ldr r3, [r3, #0] 8007d2a: 689b ldr r3, [r3, #8] 8007d2c: f023 0180 bic.w r1, r3, #128 @ 0x80 8007d30: 687b ldr r3, [r7, #4] 8007d32: 699a ldr r2, [r3, #24] 8007d34: 687b ldr r3, [r7, #4] 8007d36: 681b ldr r3, [r3, #0] 8007d38: 430a orrs r2, r1 8007d3a: 609a str r2, [r3, #8] /* makes sure the input data format (bytes, halfwords or words stream) * is properly specified by user */ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 8007d3c: 687b ldr r3, [r7, #4] 8007d3e: 2201 movs r2, #1 8007d40: 775a strb r2, [r3, #29] /* Return function status */ return HAL_OK; 8007d42: 2300 movs r3, #0 } 8007d44: 4618 mov r0, r3 8007d46: 3708 adds r7, #8 8007d48: 46bd mov sp, r7 8007d4a: bd80 pop {r7, pc} 8007d4c: 04c11db7 .word 0x04c11db7 08007d50 : * and the API will internally adjust its input data processing based on the * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { 8007d50: b580 push {r7, lr} 8007d52: b086 sub sp, #24 8007d54: af00 add r7, sp, #0 8007d56: 60f8 str r0, [r7, #12] 8007d58: 60b9 str r1, [r7, #8] 8007d5a: 607a str r2, [r7, #4] uint32_t index; /* CRC input data buffer index */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ 8007d5c: 2300 movs r3, #0 8007d5e: 613b str r3, [r7, #16] /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; 8007d60: 68fb ldr r3, [r7, #12] 8007d62: 2202 movs r2, #2 8007d64: 775a strb r2, [r3, #29] /* Reset CRC Calculation Unit (hcrc->Instance->INIT is * written in hcrc->Instance->DR) */ __HAL_CRC_DR_RESET(hcrc); 8007d66: 68fb ldr r3, [r7, #12] 8007d68: 681b ldr r3, [r3, #0] 8007d6a: 689a ldr r2, [r3, #8] 8007d6c: 68fb ldr r3, [r7, #12] 8007d6e: 681b ldr r3, [r3, #0] 8007d70: f042 0201 orr.w r2, r2, #1 8007d74: 609a str r2, [r3, #8] switch (hcrc->InputDataFormat) 8007d76: 68fb ldr r3, [r7, #12] 8007d78: 6a1b ldr r3, [r3, #32] 8007d7a: 2b03 cmp r3, #3 8007d7c: d006 beq.n 8007d8c 8007d7e: 2b03 cmp r3, #3 8007d80: d829 bhi.n 8007dd6 8007d82: 2b01 cmp r3, #1 8007d84: d019 beq.n 8007dba 8007d86: 2b02 cmp r3, #2 8007d88: d01e beq.n 8007dc8 /* Specific 16-bit input data handling */ temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: break; 8007d8a: e024 b.n 8007dd6 for (index = 0U; index < BufferLength; index++) 8007d8c: 2300 movs r3, #0 8007d8e: 617b str r3, [r7, #20] 8007d90: e00a b.n 8007da8 hcrc->Instance->DR = pBuffer[index]; 8007d92: 697b ldr r3, [r7, #20] 8007d94: 009b lsls r3, r3, #2 8007d96: 68ba ldr r2, [r7, #8] 8007d98: 441a add r2, r3 8007d9a: 68fb ldr r3, [r7, #12] 8007d9c: 681b ldr r3, [r3, #0] 8007d9e: 6812 ldr r2, [r2, #0] 8007da0: 601a str r2, [r3, #0] for (index = 0U; index < BufferLength; index++) 8007da2: 697b ldr r3, [r7, #20] 8007da4: 3301 adds r3, #1 8007da6: 617b str r3, [r7, #20] 8007da8: 697a ldr r2, [r7, #20] 8007daa: 687b ldr r3, [r7, #4] 8007dac: 429a cmp r2, r3 8007dae: d3f0 bcc.n 8007d92 temp = hcrc->Instance->DR; 8007db0: 68fb ldr r3, [r7, #12] 8007db2: 681b ldr r3, [r3, #0] 8007db4: 681b ldr r3, [r3, #0] 8007db6: 613b str r3, [r7, #16] break; 8007db8: e00e b.n 8007dd8 temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); 8007dba: 687a ldr r2, [r7, #4] 8007dbc: 68b9 ldr r1, [r7, #8] 8007dbe: 68f8 ldr r0, [r7, #12] 8007dc0: f000 f812 bl 8007de8 8007dc4: 6138 str r0, [r7, #16] break; 8007dc6: e007 b.n 8007dd8 temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ 8007dc8: 687a ldr r2, [r7, #4] 8007dca: 68b9 ldr r1, [r7, #8] 8007dcc: 68f8 ldr r0, [r7, #12] 8007dce: f000 f899 bl 8007f04 8007dd2: 6138 str r0, [r7, #16] break; 8007dd4: e000 b.n 8007dd8 break; 8007dd6: bf00 nop } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 8007dd8: 68fb ldr r3, [r7, #12] 8007dda: 2201 movs r2, #1 8007ddc: 775a strb r2, [r3, #29] /* Return the CRC computed value */ return temp; 8007dde: 693b ldr r3, [r7, #16] } 8007de0: 4618 mov r0, r3 8007de2: 3718 adds r7, #24 8007de4: 46bd mov sp, r7 8007de6: bd80 pop {r7, pc} 08007de8 : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { 8007de8: b480 push {r7} 8007dea: b089 sub sp, #36 @ 0x24 8007dec: af00 add r7, sp, #0 8007dee: 60f8 str r0, [r7, #12] 8007df0: 60b9 str r1, [r7, #8] 8007df2: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 4 bytes are entered in a row with a single word write, * last bytes must be carefully fed to the CRC calculator to ensure a correct type * handling by the peripheral */ for (i = 0U; i < (BufferLength / 4U); i++) 8007df4: 2300 movs r3, #0 8007df6: 61fb str r3, [r7, #28] 8007df8: e023 b.n 8007e42 { hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007dfa: 69fb ldr r3, [r7, #28] 8007dfc: 009b lsls r3, r3, #2 8007dfe: 68ba ldr r2, [r7, #8] 8007e00: 4413 add r3, r2 8007e02: 781b ldrb r3, [r3, #0] 8007e04: 061a lsls r2, r3, #24 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8007e06: 69fb ldr r3, [r7, #28] 8007e08: 009b lsls r3, r3, #2 8007e0a: 3301 adds r3, #1 8007e0c: 68b9 ldr r1, [r7, #8] 8007e0e: 440b add r3, r1 8007e10: 781b ldrb r3, [r3, #0] 8007e12: 041b lsls r3, r3, #16 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007e14: 431a orrs r2, r3 ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 8007e16: 69fb ldr r3, [r7, #28] 8007e18: 009b lsls r3, r3, #2 8007e1a: 3302 adds r3, #2 8007e1c: 68b9 ldr r1, [r7, #8] 8007e1e: 440b add r3, r1 8007e20: 781b ldrb r3, [r3, #0] 8007e22: 021b lsls r3, r3, #8 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8007e24: 431a orrs r2, r3 (uint32_t)pBuffer[(4U * i) + 3U]; 8007e26: 69fb ldr r3, [r7, #28] 8007e28: 009b lsls r3, r3, #2 8007e2a: 3303 adds r3, #3 8007e2c: 68b9 ldr r1, [r7, #8] 8007e2e: 440b add r3, r1 8007e30: 781b ldrb r3, [r3, #0] 8007e32: 4619 mov r1, r3 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007e34: 68fb ldr r3, [r7, #12] 8007e36: 681b ldr r3, [r3, #0] ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 8007e38: 430a orrs r2, r1 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007e3a: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 4U); i++) 8007e3c: 69fb ldr r3, [r7, #28] 8007e3e: 3301 adds r3, #1 8007e40: 61fb str r3, [r7, #28] 8007e42: 687b ldr r3, [r7, #4] 8007e44: 089b lsrs r3, r3, #2 8007e46: 69fa ldr r2, [r7, #28] 8007e48: 429a cmp r2, r3 8007e4a: d3d6 bcc.n 8007dfa } /* last bytes specific handling */ if ((BufferLength % 4U) != 0U) 8007e4c: 687b ldr r3, [r7, #4] 8007e4e: f003 0303 and.w r3, r3, #3 8007e52: 2b00 cmp r3, #0 8007e54: d04d beq.n 8007ef2 { if ((BufferLength % 4U) == 1U) 8007e56: 687b ldr r3, [r7, #4] 8007e58: f003 0303 and.w r3, r3, #3 8007e5c: 2b01 cmp r3, #1 8007e5e: d107 bne.n 8007e70 { *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ 8007e60: 69fb ldr r3, [r7, #28] 8007e62: 009b lsls r3, r3, #2 8007e64: 68ba ldr r2, [r7, #8] 8007e66: 4413 add r3, r2 8007e68: 68fa ldr r2, [r7, #12] 8007e6a: 6812 ldr r2, [r2, #0] 8007e6c: 781b ldrb r3, [r3, #0] 8007e6e: 7013 strb r3, [r2, #0] } if ((BufferLength % 4U) == 2U) 8007e70: 687b ldr r3, [r7, #4] 8007e72: f003 0303 and.w r3, r3, #3 8007e76: 2b02 cmp r3, #2 8007e78: d116 bne.n 8007ea8 { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 8007e7a: 69fb ldr r3, [r7, #28] 8007e7c: 009b lsls r3, r3, #2 8007e7e: 68ba ldr r2, [r7, #8] 8007e80: 4413 add r3, r2 8007e82: 781b ldrb r3, [r3, #0] 8007e84: 021b lsls r3, r3, #8 8007e86: b21a sxth r2, r3 8007e88: 69fb ldr r3, [r7, #28] 8007e8a: 009b lsls r3, r3, #2 8007e8c: 3301 adds r3, #1 8007e8e: 68b9 ldr r1, [r7, #8] 8007e90: 440b add r3, r1 8007e92: 781b ldrb r3, [r3, #0] 8007e94: b21b sxth r3, r3 8007e96: 4313 orrs r3, r2 8007e98: b21b sxth r3, r3 8007e9a: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007e9c: 68fb ldr r3, [r7, #12] 8007e9e: 681b ldr r3, [r3, #0] 8007ea0: 617b str r3, [r7, #20] *pReg = data; 8007ea2: 697b ldr r3, [r7, #20] 8007ea4: 8b7a ldrh r2, [r7, #26] 8007ea6: 801a strh r2, [r3, #0] } if ((BufferLength % 4U) == 3U) 8007ea8: 687b ldr r3, [r7, #4] 8007eaa: f003 0303 and.w r3, r3, #3 8007eae: 2b03 cmp r3, #3 8007eb0: d11f bne.n 8007ef2 { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 8007eb2: 69fb ldr r3, [r7, #28] 8007eb4: 009b lsls r3, r3, #2 8007eb6: 68ba ldr r2, [r7, #8] 8007eb8: 4413 add r3, r2 8007eba: 781b ldrb r3, [r3, #0] 8007ebc: 021b lsls r3, r3, #8 8007ebe: b21a sxth r2, r3 8007ec0: 69fb ldr r3, [r7, #28] 8007ec2: 009b lsls r3, r3, #2 8007ec4: 3301 adds r3, #1 8007ec6: 68b9 ldr r1, [r7, #8] 8007ec8: 440b add r3, r1 8007eca: 781b ldrb r3, [r3, #0] 8007ecc: b21b sxth r3, r3 8007ece: 4313 orrs r3, r2 8007ed0: b21b sxth r3, r3 8007ed2: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007ed4: 68fb ldr r3, [r7, #12] 8007ed6: 681b ldr r3, [r3, #0] 8007ed8: 617b str r3, [r7, #20] *pReg = data; 8007eda: 697b ldr r3, [r7, #20] 8007edc: 8b7a ldrh r2, [r7, #26] 8007ede: 801a strh r2, [r3, #0] *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ 8007ee0: 69fb ldr r3, [r7, #28] 8007ee2: 009b lsls r3, r3, #2 8007ee4: 3302 adds r3, #2 8007ee6: 68ba ldr r2, [r7, #8] 8007ee8: 4413 add r3, r2 8007eea: 68fa ldr r2, [r7, #12] 8007eec: 6812 ldr r2, [r2, #0] 8007eee: 781b ldrb r3, [r3, #0] 8007ef0: 7013 strb r3, [r2, #0] } } /* Return the CRC computed value */ return hcrc->Instance->DR; 8007ef2: 68fb ldr r3, [r7, #12] 8007ef4: 681b ldr r3, [r3, #0] 8007ef6: 681b ldr r3, [r3, #0] } 8007ef8: 4618 mov r0, r3 8007efa: 3724 adds r7, #36 @ 0x24 8007efc: 46bd mov sp, r7 8007efe: f85d 7b04 ldr.w r7, [sp], #4 8007f02: 4770 bx lr 08007f04 : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { 8007f04: b480 push {r7} 8007f06: b087 sub sp, #28 8007f08: af00 add r7, sp, #0 8007f0a: 60f8 str r0, [r7, #12] 8007f0c: 60b9 str r1, [r7, #8] 8007f0e: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the peripheral */ for (i = 0U; i < (BufferLength / 2U); i++) 8007f10: 2300 movs r3, #0 8007f12: 617b str r3, [r7, #20] 8007f14: e013 b.n 8007f3e { hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; 8007f16: 697b ldr r3, [r7, #20] 8007f18: 009b lsls r3, r3, #2 8007f1a: 68ba ldr r2, [r7, #8] 8007f1c: 4413 add r3, r2 8007f1e: 881b ldrh r3, [r3, #0] 8007f20: 041a lsls r2, r3, #16 8007f22: 697b ldr r3, [r7, #20] 8007f24: 009b lsls r3, r3, #2 8007f26: 3302 adds r3, #2 8007f28: 68b9 ldr r1, [r7, #8] 8007f2a: 440b add r3, r1 8007f2c: 881b ldrh r3, [r3, #0] 8007f2e: 4619 mov r1, r3 8007f30: 68fb ldr r3, [r7, #12] 8007f32: 681b ldr r3, [r3, #0] 8007f34: 430a orrs r2, r1 8007f36: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 2U); i++) 8007f38: 697b ldr r3, [r7, #20] 8007f3a: 3301 adds r3, #1 8007f3c: 617b str r3, [r7, #20] 8007f3e: 687b ldr r3, [r7, #4] 8007f40: 085b lsrs r3, r3, #1 8007f42: 697a ldr r2, [r7, #20] 8007f44: 429a cmp r2, r3 8007f46: d3e6 bcc.n 8007f16 } if ((BufferLength % 2U) != 0U) 8007f48: 687b ldr r3, [r7, #4] 8007f4a: f003 0301 and.w r3, r3, #1 8007f4e: 2b00 cmp r3, #0 8007f50: d009 beq.n 8007f66 { pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007f52: 68fb ldr r3, [r7, #12] 8007f54: 681b ldr r3, [r3, #0] 8007f56: 613b str r3, [r7, #16] *pReg = pBuffer[2U * i]; 8007f58: 697b ldr r3, [r7, #20] 8007f5a: 009b lsls r3, r3, #2 8007f5c: 68ba ldr r2, [r7, #8] 8007f5e: 4413 add r3, r2 8007f60: 881a ldrh r2, [r3, #0] 8007f62: 693b ldr r3, [r7, #16] 8007f64: 801a strh r2, [r3, #0] } /* Return the CRC computed value */ return hcrc->Instance->DR; 8007f66: 68fb ldr r3, [r7, #12] 8007f68: 681b ldr r3, [r3, #0] 8007f6a: 681b ldr r3, [r3, #0] } 8007f6c: 4618 mov r0, r3 8007f6e: 371c adds r7, #28 8007f70: 46bd mov sp, r7 8007f72: f85d 7b04 ldr.w r7, [sp], #4 8007f76: 4770 bx lr 08007f78 : * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) { 8007f78: b480 push {r7} 8007f7a: b087 sub sp, #28 8007f7c: af00 add r7, sp, #0 8007f7e: 60f8 str r0, [r7, #12] 8007f80: 60b9 str r1, [r7, #8] 8007f82: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8007f84: 2300 movs r3, #0 8007f86: 75fb strb r3, [r7, #23] uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ 8007f88: 231f movs r3, #31 8007f8a: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); /* Ensure that the generating polynomial is odd */ if ((Pol & (uint32_t)(0x1U)) == 0U) 8007f8c: 68bb ldr r3, [r7, #8] 8007f8e: f003 0301 and.w r3, r3, #1 8007f92: 2b00 cmp r3, #0 8007f94: d102 bne.n 8007f9c { status = HAL_ERROR; 8007f96: 2301 movs r3, #1 8007f98: 75fb strb r3, [r7, #23] 8007f9a: e063 b.n 8008064 * definition. HAL_ERROR is reported if Pol degree is * larger than that indicated by PolyLength. * Look for MSB position: msb will contain the degree of * the second to the largest polynomial member. E.g., for * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) 8007f9c: bf00 nop 8007f9e: 693b ldr r3, [r7, #16] 8007fa0: 1e5a subs r2, r3, #1 8007fa2: 613a str r2, [r7, #16] 8007fa4: 2b00 cmp r3, #0 8007fa6: d009 beq.n 8007fbc 8007fa8: 693b ldr r3, [r7, #16] 8007faa: f003 031f and.w r3, r3, #31 8007fae: 68ba ldr r2, [r7, #8] 8007fb0: fa22 f303 lsr.w r3, r2, r3 8007fb4: f003 0301 and.w r3, r3, #1 8007fb8: 2b00 cmp r3, #0 8007fba: d0f0 beq.n 8007f9e { } switch (PolyLength) 8007fbc: 687b ldr r3, [r7, #4] 8007fbe: 2b18 cmp r3, #24 8007fc0: d846 bhi.n 8008050 8007fc2: a201 add r2, pc, #4 @ (adr r2, 8007fc8 ) 8007fc4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007fc8: 08008057 .word 0x08008057 8007fcc: 08008051 .word 0x08008051 8007fd0: 08008051 .word 0x08008051 8007fd4: 08008051 .word 0x08008051 8007fd8: 08008051 .word 0x08008051 8007fdc: 08008051 .word 0x08008051 8007fe0: 08008051 .word 0x08008051 8007fe4: 08008051 .word 0x08008051 8007fe8: 08008045 .word 0x08008045 8007fec: 08008051 .word 0x08008051 8007ff0: 08008051 .word 0x08008051 8007ff4: 08008051 .word 0x08008051 8007ff8: 08008051 .word 0x08008051 8007ffc: 08008051 .word 0x08008051 8008000: 08008051 .word 0x08008051 8008004: 08008051 .word 0x08008051 8008008: 08008039 .word 0x08008039 800800c: 08008051 .word 0x08008051 8008010: 08008051 .word 0x08008051 8008014: 08008051 .word 0x08008051 8008018: 08008051 .word 0x08008051 800801c: 08008051 .word 0x08008051 8008020: 08008051 .word 0x08008051 8008024: 08008051 .word 0x08008051 8008028: 0800802d .word 0x0800802d { case CRC_POLYLENGTH_7B: if (msb >= HAL_CRC_LENGTH_7B) 800802c: 693b ldr r3, [r7, #16] 800802e: 2b06 cmp r3, #6 8008030: d913 bls.n 800805a { status = HAL_ERROR; 8008032: 2301 movs r3, #1 8008034: 75fb strb r3, [r7, #23] } break; 8008036: e010 b.n 800805a case CRC_POLYLENGTH_8B: if (msb >= HAL_CRC_LENGTH_8B) 8008038: 693b ldr r3, [r7, #16] 800803a: 2b07 cmp r3, #7 800803c: d90f bls.n 800805e { status = HAL_ERROR; 800803e: 2301 movs r3, #1 8008040: 75fb strb r3, [r7, #23] } break; 8008042: e00c b.n 800805e case CRC_POLYLENGTH_16B: if (msb >= HAL_CRC_LENGTH_16B) 8008044: 693b ldr r3, [r7, #16] 8008046: 2b0f cmp r3, #15 8008048: d90b bls.n 8008062 { status = HAL_ERROR; 800804a: 2301 movs r3, #1 800804c: 75fb strb r3, [r7, #23] } break; 800804e: e008 b.n 8008062 case CRC_POLYLENGTH_32B: /* no polynomial definition vs. polynomial length issue possible */ break; default: status = HAL_ERROR; 8008050: 2301 movs r3, #1 8008052: 75fb strb r3, [r7, #23] break; 8008054: e006 b.n 8008064 break; 8008056: bf00 nop 8008058: e004 b.n 8008064 break; 800805a: bf00 nop 800805c: e002 b.n 8008064 break; 800805e: bf00 nop 8008060: e000 b.n 8008064 break; 8008062: bf00 nop } } if (status == HAL_OK) 8008064: 7dfb ldrb r3, [r7, #23] 8008066: 2b00 cmp r3, #0 8008068: d10d bne.n 8008086 { /* set generating polynomial */ WRITE_REG(hcrc->Instance->POL, Pol); 800806a: 68fb ldr r3, [r7, #12] 800806c: 681b ldr r3, [r3, #0] 800806e: 68ba ldr r2, [r7, #8] 8008070: 615a str r2, [r3, #20] /* set generating polynomial size */ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); 8008072: 68fb ldr r3, [r7, #12] 8008074: 681b ldr r3, [r3, #0] 8008076: 689b ldr r3, [r3, #8] 8008078: f023 0118 bic.w r1, r3, #24 800807c: 68fb ldr r3, [r7, #12] 800807e: 681b ldr r3, [r3, #0] 8008080: 687a ldr r2, [r7, #4] 8008082: 430a orrs r2, r1 8008084: 609a str r2, [r3, #8] } /* Return function status */ return status; 8008086: 7dfb ldrb r3, [r7, #23] } 8008088: 4618 mov r0, r3 800808a: 371c adds r7, #28 800808c: 46bd mov sp, r7 800808e: f85d 7b04 ldr.w r7, [sp], #4 8008092: 4770 bx lr 08008094 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { 8008094: b580 push {r7, lr} 8008096: b082 sub sp, #8 8008098: af00 add r7, sp, #0 800809a: 6078 str r0, [r7, #4] /* Check the DAC peripheral handle */ if (hdac == NULL) 800809c: 687b ldr r3, [r7, #4] 800809e: 2b00 cmp r3, #0 80080a0: d101 bne.n 80080a6 { return HAL_ERROR; 80080a2: 2301 movs r3, #1 80080a4: e014 b.n 80080d0 } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); if (hdac->State == HAL_DAC_STATE_RESET) 80080a6: 687b ldr r3, [r7, #4] 80080a8: 791b ldrb r3, [r3, #4] 80080aa: b2db uxtb r3, r3 80080ac: 2b00 cmp r3, #0 80080ae: d105 bne.n 80080bc hdac->MspInitCallback = HAL_DAC_MspInit; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /* Allocate lock resource and initialize it */ hdac->Lock = HAL_UNLOCKED; 80080b0: 687b ldr r3, [r7, #4] 80080b2: 2200 movs r2, #0 80080b4: 715a strb r2, [r3, #5] #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* Init the low level hardware */ hdac->MspInitCallback(hdac); #else /* Init the low level hardware */ HAL_DAC_MspInit(hdac); 80080b6: 6878 ldr r0, [r7, #4] 80080b8: f7fc f836 bl 8004128 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; 80080bc: 687b ldr r3, [r7, #4] 80080be: 2202 movs r2, #2 80080c0: 711a strb r2, [r3, #4] /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; 80080c2: 687b ldr r3, [r7, #4] 80080c4: 2200 movs r2, #0 80080c6: 611a str r2, [r3, #16] /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; 80080c8: 687b ldr r3, [r7, #4] 80080ca: 2201 movs r2, #1 80080cc: 711a strb r2, [r3, #4] /* Return function status */ return HAL_OK; 80080ce: 2300 movs r3, #0 } 80080d0: 4618 mov r0, r3 80080d2: 3708 adds r7, #8 80080d4: 46bd mov sp, r7 80080d6: bd80 pop {r7, pc} 080080d8 : * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { 80080d8: b480 push {r7} 80080da: b083 sub sp, #12 80080dc: af00 add r7, sp, #0 80080de: 6078 str r0, [r7, #4] 80080e0: 6039 str r1, [r7, #0] /* Check the DAC peripheral handle */ if (hdac == NULL) 80080e2: 687b ldr r3, [r7, #4] 80080e4: 2b00 cmp r3, #0 80080e6: d101 bne.n 80080ec { return HAL_ERROR; 80080e8: 2301 movs r3, #1 80080ea: e046 b.n 800817a /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 80080ec: 687b ldr r3, [r7, #4] 80080ee: 795b ldrb r3, [r3, #5] 80080f0: 2b01 cmp r3, #1 80080f2: d101 bne.n 80080f8 80080f4: 2302 movs r3, #2 80080f6: e040 b.n 800817a 80080f8: 687b ldr r3, [r7, #4] 80080fa: 2201 movs r2, #1 80080fc: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 80080fe: 687b ldr r3, [r7, #4] 8008100: 2202 movs r2, #2 8008102: 711a strb r2, [r3, #4] /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); 8008104: 687b ldr r3, [r7, #4] 8008106: 681b ldr r3, [r3, #0] 8008108: 6819 ldr r1, [r3, #0] 800810a: 683b ldr r3, [r7, #0] 800810c: f003 0310 and.w r3, r3, #16 8008110: 2201 movs r2, #1 8008112: 409a lsls r2, r3 8008114: 687b ldr r3, [r7, #4] 8008116: 681b ldr r3, [r3, #0] 8008118: 430a orrs r2, r1 800811a: 601a str r2, [r3, #0] if (Channel == DAC_CHANNEL_1) 800811c: 683b ldr r3, [r7, #0] 800811e: 2b00 cmp r3, #0 8008120: d10f bne.n 8008142 { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) 8008122: 687b ldr r3, [r7, #4] 8008124: 681b ldr r3, [r3, #0] 8008126: 681b ldr r3, [r3, #0] 8008128: f003 033e and.w r3, r3, #62 @ 0x3e 800812c: 2b02 cmp r3, #2 800812e: d11d bne.n 800816c { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); 8008130: 687b ldr r3, [r7, #4] 8008132: 681b ldr r3, [r3, #0] 8008134: 685a ldr r2, [r3, #4] 8008136: 687b ldr r3, [r7, #4] 8008138: 681b ldr r3, [r3, #0] 800813a: f042 0201 orr.w r2, r2, #1 800813e: 605a str r2, [r3, #4] 8008140: e014 b.n 800816c } else { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) 8008142: 687b ldr r3, [r7, #4] 8008144: 681b ldr r3, [r3, #0] 8008146: 681b ldr r3, [r3, #0] 8008148: f403 1278 and.w r2, r3, #4063232 @ 0x3e0000 800814c: 683b ldr r3, [r7, #0] 800814e: f003 0310 and.w r3, r3, #16 8008152: 2102 movs r1, #2 8008154: fa01 f303 lsl.w r3, r1, r3 8008158: 429a cmp r2, r3 800815a: d107 bne.n 800816c { /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); 800815c: 687b ldr r3, [r7, #4] 800815e: 681b ldr r3, [r3, #0] 8008160: 685a ldr r2, [r3, #4] 8008162: 687b ldr r3, [r7, #4] 8008164: 681b ldr r3, [r3, #0] 8008166: f042 0202 orr.w r2, r2, #2 800816a: 605a str r2, [r3, #4] } } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 800816c: 687b ldr r3, [r7, #4] 800816e: 2201 movs r2, #1 8008170: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 8008172: 687b ldr r3, [r7, #4] 8008174: 2200 movs r2, #0 8008176: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 8008178: 2300 movs r3, #0 } 800817a: 4618 mov r0, r3 800817c: 370c adds r7, #12 800817e: 46bd mov sp, r7 8008180: f85d 7b04 ldr.w r7, [sp], #4 8008184: 4770 bx lr 08008186 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { 8008186: b580 push {r7, lr} 8008188: b084 sub sp, #16 800818a: af00 add r7, sp, #0 800818c: 6078 str r0, [r7, #4] uint32_t itsource = hdac->Instance->CR; 800818e: 687b ldr r3, [r7, #4] 8008190: 681b ldr r3, [r3, #0] 8008192: 681b ldr r3, [r3, #0] 8008194: 60fb str r3, [r7, #12] uint32_t itflag = hdac->Instance->SR; 8008196: 687b ldr r3, [r7, #4] 8008198: 681b ldr r3, [r3, #0] 800819a: 6b5b ldr r3, [r3, #52] @ 0x34 800819c: 60bb str r3, [r7, #8] if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1) 800819e: 68fb ldr r3, [r7, #12] 80081a0: f403 5300 and.w r3, r3, #8192 @ 0x2000 80081a4: 2b00 cmp r3, #0 80081a6: d01d beq.n 80081e4 { /* Check underrun flag of DAC channel 1 */ if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1) 80081a8: 68bb ldr r3, [r7, #8] 80081aa: f403 5300 and.w r3, r3, #8192 @ 0x2000 80081ae: 2b00 cmp r3, #0 80081b0: d018 beq.n 80081e4 { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; 80081b2: 687b ldr r3, [r7, #4] 80081b4: 2204 movs r2, #4 80081b6: 711a strb r2, [r3, #4] /* Set DAC error code to channel1 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); 80081b8: 687b ldr r3, [r7, #4] 80081ba: 691b ldr r3, [r3, #16] 80081bc: f043 0201 orr.w r2, r3, #1 80081c0: 687b ldr r3, [r7, #4] 80081c2: 611a str r2, [r3, #16] /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); 80081c4: 687b ldr r3, [r7, #4] 80081c6: 681b ldr r3, [r3, #0] 80081c8: f44f 5200 mov.w r2, #8192 @ 0x2000 80081cc: 635a str r2, [r3, #52] @ 0x34 /* Disable the selected DAC channel1 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1); 80081ce: 687b ldr r3, [r7, #4] 80081d0: 681b ldr r3, [r3, #0] 80081d2: 681a ldr r2, [r3, #0] 80081d4: 687b ldr r3, [r7, #4] 80081d6: 681b ldr r3, [r3, #0] 80081d8: f422 5280 bic.w r2, r2, #4096 @ 0x1000 80081dc: 601a str r2, [r3, #0] /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh1(hdac); #else HAL_DAC_DMAUnderrunCallbackCh1(hdac); 80081de: 6878 ldr r0, [r7, #4] 80081e0: f000 f851 bl 8008286 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2) 80081e4: 68fb ldr r3, [r7, #12] 80081e6: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80081ea: 2b00 cmp r3, #0 80081ec: d01d beq.n 800822a { /* Check underrun flag of DAC channel 2 */ if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2) 80081ee: 68bb ldr r3, [r7, #8] 80081f0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80081f4: 2b00 cmp r3, #0 80081f6: d018 beq.n 800822a { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; 80081f8: 687b ldr r3, [r7, #4] 80081fa: 2204 movs r2, #4 80081fc: 711a strb r2, [r3, #4] /* Set DAC error code to channel2 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); 80081fe: 687b ldr r3, [r7, #4] 8008200: 691b ldr r3, [r3, #16] 8008202: f043 0202 orr.w r2, r3, #2 8008206: 687b ldr r3, [r7, #4] 8008208: 611a str r2, [r3, #16] /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); 800820a: 687b ldr r3, [r7, #4] 800820c: 681b ldr r3, [r3, #0] 800820e: f04f 5200 mov.w r2, #536870912 @ 0x20000000 8008212: 635a str r2, [r3, #52] @ 0x34 /* Disable the selected DAC channel2 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2); 8008214: 687b ldr r3, [r7, #4] 8008216: 681b ldr r3, [r3, #0] 8008218: 681a ldr r2, [r3, #0] 800821a: 687b ldr r3, [r7, #4] 800821c: 681b ldr r3, [r3, #0] 800821e: f022 5280 bic.w r2, r2, #268435456 @ 0x10000000 8008222: 601a str r2, [r3, #0] /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh2(hdac); #else HAL_DACEx_DMAUnderrunCallbackCh2(hdac); 8008224: 6878 ldr r0, [r7, #4] 8008226: f000 f97b bl 8008520 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } } 800822a: bf00 nop 800822c: 3710 adds r7, #16 800822e: 46bd mov sp, r7 8008230: bd80 pop {r7, pc} 08008232 : * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { 8008232: b480 push {r7} 8008234: b087 sub sp, #28 8008236: af00 add r7, sp, #0 8008238: 60f8 str r0, [r7, #12] 800823a: 60b9 str r1, [r7, #8] 800823c: 607a str r2, [r7, #4] 800823e: 603b str r3, [r7, #0] __IO uint32_t tmp = 0UL; 8008240: 2300 movs r3, #0 8008242: 617b str r3, [r7, #20] /* Check the DAC peripheral handle */ if (hdac == NULL) 8008244: 68fb ldr r3, [r7, #12] 8008246: 2b00 cmp r3, #0 8008248: d101 bne.n 800824e { return HAL_ERROR; 800824a: 2301 movs r3, #1 800824c: e015 b.n 800827a /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)hdac->Instance; 800824e: 68fb ldr r3, [r7, #12] 8008250: 681b ldr r3, [r3, #0] 8008252: 617b str r3, [r7, #20] if (Channel == DAC_CHANNEL_1) 8008254: 68bb ldr r3, [r7, #8] 8008256: 2b00 cmp r3, #0 8008258: d105 bne.n 8008266 { tmp += DAC_DHR12R1_ALIGNMENT(Alignment); 800825a: 697a ldr r2, [r7, #20] 800825c: 687b ldr r3, [r7, #4] 800825e: 4413 add r3, r2 8008260: 3308 adds r3, #8 8008262: 617b str r3, [r7, #20] 8008264: e004 b.n 8008270 } else { tmp += DAC_DHR12R2_ALIGNMENT(Alignment); 8008266: 697a ldr r2, [r7, #20] 8008268: 687b ldr r3, [r7, #4] 800826a: 4413 add r3, r2 800826c: 3314 adds r3, #20 800826e: 617b str r3, [r7, #20] } /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; 8008270: 697b ldr r3, [r7, #20] 8008272: 461a mov r2, r3 8008274: 683b ldr r3, [r7, #0] 8008276: 6013 str r3, [r2, #0] /* Return function status */ return HAL_OK; 8008278: 2300 movs r3, #0 } 800827a: 4618 mov r0, r3 800827c: 371c adds r7, #28 800827e: 46bd mov sp, r7 8008280: f85d 7b04 ldr.w r7, [sp], #4 8008284: 4770 bx lr 08008286 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) { 8008286: b480 push {r7} 8008288: b083 sub sp, #12 800828a: af00 add r7, sp, #0 800828c: 6078 str r0, [r7, #4] UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file */ } 800828e: bf00 nop 8008290: 370c adds r7, #12 8008292: 46bd mov sp, r7 8008294: f85d 7b04 ldr.w r7, [sp], #4 8008298: 4770 bx lr ... 0800829c : * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { 800829c: b580 push {r7, lr} 800829e: b08a sub sp, #40 @ 0x28 80082a0: af00 add r7, sp, #0 80082a2: 60f8 str r0, [r7, #12] 80082a4: 60b9 str r1, [r7, #8] 80082a6: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80082a8: 2300 movs r3, #0 80082aa: f887 3023 strb.w r3, [r7, #35] @ 0x23 uint32_t tmpreg2; uint32_t tickstart; uint32_t connectOnChip; /* Check the DAC peripheral handle and channel configuration struct */ if ((hdac == NULL) || (sConfig == NULL)) 80082ae: 68fb ldr r3, [r7, #12] 80082b0: 2b00 cmp r3, #0 80082b2: d002 beq.n 80082ba 80082b4: 68bb ldr r3, [r7, #8] 80082b6: 2b00 cmp r3, #0 80082b8: d101 bne.n 80082be { return HAL_ERROR; 80082ba: 2301 movs r3, #1 80082bc: e12a b.n 8008514 assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 80082be: 68fb ldr r3, [r7, #12] 80082c0: 795b ldrb r3, [r3, #5] 80082c2: 2b01 cmp r3, #1 80082c4: d101 bne.n 80082ca 80082c6: 2302 movs r3, #2 80082c8: e124 b.n 8008514 80082ca: 68fb ldr r3, [r7, #12] 80082cc: 2201 movs r2, #1 80082ce: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 80082d0: 68fb ldr r3, [r7, #12] 80082d2: 2202 movs r2, #2 80082d4: 711a strb r2, [r3, #4] /* Sample and hold configuration */ if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) 80082d6: 68bb ldr r3, [r7, #8] 80082d8: 681b ldr r3, [r3, #0] 80082da: 2b04 cmp r3, #4 80082dc: d17a bne.n 80083d4 { /* Get timeout */ tickstart = HAL_GetTick(); 80082de: f7fd fd8d bl 8005dfc 80082e2: 61f8 str r0, [r7, #28] if (Channel == DAC_CHANNEL_1) 80082e4: 687b ldr r3, [r7, #4] 80082e6: 2b00 cmp r3, #0 80082e8: d13d bne.n 8008366 { /* SHSR1 can be written when BWST1 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 80082ea: e018 b.n 800831e { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 80082ec: f7fd fd86 bl 8005dfc 80082f0: 4602 mov r2, r0 80082f2: 69fb ldr r3, [r7, #28] 80082f4: 1ad3 subs r3, r2, r3 80082f6: 2b01 cmp r3, #1 80082f8: d911 bls.n 800831e { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 80082fa: 68fb ldr r3, [r7, #12] 80082fc: 681b ldr r3, [r3, #0] 80082fe: 6b5a ldr r2, [r3, #52] @ 0x34 8008300: 4b86 ldr r3, [pc, #536] @ (800851c ) 8008302: 4013 ands r3, r2 8008304: 2b00 cmp r3, #0 8008306: d00a beq.n 800831e { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 8008308: 68fb ldr r3, [r7, #12] 800830a: 691b ldr r3, [r3, #16] 800830c: f043 0208 orr.w r2, r3, #8 8008310: 68fb ldr r3, [r7, #12] 8008312: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 8008314: 68fb ldr r3, [r7, #12] 8008316: 2203 movs r2, #3 8008318: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 800831a: 2303 movs r3, #3 800831c: e0fa b.n 8008514 while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 800831e: 68fb ldr r3, [r7, #12] 8008320: 681b ldr r3, [r3, #0] 8008322: 6b5a ldr r2, [r3, #52] @ 0x34 8008324: 4b7d ldr r3, [pc, #500] @ (800851c ) 8008326: 4013 ands r3, r2 8008328: 2b00 cmp r3, #0 800832a: d1df bne.n 80082ec } } } hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 800832c: 68fb ldr r3, [r7, #12] 800832e: 681b ldr r3, [r3, #0] 8008330: 68ba ldr r2, [r7, #8] 8008332: 6992 ldr r2, [r2, #24] 8008334: 641a str r2, [r3, #64] @ 0x40 8008336: e020 b.n 800837a { /* SHSR2 can be written when BWST2 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8008338: f7fd fd60 bl 8005dfc 800833c: 4602 mov r2, r0 800833e: 69fb ldr r3, [r7, #28] 8008340: 1ad3 subs r3, r2, r3 8008342: 2b01 cmp r3, #1 8008344: d90f bls.n 8008366 { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 8008346: 68fb ldr r3, [r7, #12] 8008348: 681b ldr r3, [r3, #0] 800834a: 6b5b ldr r3, [r3, #52] @ 0x34 800834c: 2b00 cmp r3, #0 800834e: da0a bge.n 8008366 { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 8008350: 68fb ldr r3, [r7, #12] 8008352: 691b ldr r3, [r3, #16] 8008354: f043 0208 orr.w r2, r3, #8 8008358: 68fb ldr r3, [r7, #12] 800835a: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 800835c: 68fb ldr r3, [r7, #12] 800835e: 2203 movs r2, #3 8008360: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 8008362: 2303 movs r3, #3 8008364: e0d6 b.n 8008514 while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 8008366: 68fb ldr r3, [r7, #12] 8008368: 681b ldr r3, [r3, #0] 800836a: 6b5b ldr r3, [r3, #52] @ 0x34 800836c: 2b00 cmp r3, #0 800836e: dbe3 blt.n 8008338 } } } hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 8008370: 68fb ldr r3, [r7, #12] 8008372: 681b ldr r3, [r3, #0] 8008374: 68ba ldr r2, [r7, #8] 8008376: 6992 ldr r2, [r2, #24] 8008378: 645a str r2, [r3, #68] @ 0x44 } /* HoldTime */ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), 800837a: 68fb ldr r3, [r7, #12] 800837c: 681b ldr r3, [r3, #0] 800837e: 6c9a ldr r2, [r3, #72] @ 0x48 8008380: 687b ldr r3, [r7, #4] 8008382: f003 0310 and.w r3, r3, #16 8008386: f240 31ff movw r1, #1023 @ 0x3ff 800838a: fa01 f303 lsl.w r3, r1, r3 800838e: 43db mvns r3, r3 8008390: ea02 0103 and.w r1, r2, r3 8008394: 68bb ldr r3, [r7, #8] 8008396: 69da ldr r2, [r3, #28] 8008398: 687b ldr r3, [r7, #4] 800839a: f003 0310 and.w r3, r3, #16 800839e: 409a lsls r2, r3 80083a0: 68fb ldr r3, [r7, #12] 80083a2: 681b ldr r3, [r3, #0] 80083a4: 430a orrs r2, r1 80083a6: 649a str r2, [r3, #72] @ 0x48 (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); /* RefreshTime */ MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), 80083a8: 68fb ldr r3, [r7, #12] 80083aa: 681b ldr r3, [r3, #0] 80083ac: 6cda ldr r2, [r3, #76] @ 0x4c 80083ae: 687b ldr r3, [r7, #4] 80083b0: f003 0310 and.w r3, r3, #16 80083b4: 21ff movs r1, #255 @ 0xff 80083b6: fa01 f303 lsl.w r3, r1, r3 80083ba: 43db mvns r3, r3 80083bc: ea02 0103 and.w r1, r2, r3 80083c0: 68bb ldr r3, [r7, #8] 80083c2: 6a1a ldr r2, [r3, #32] 80083c4: 687b ldr r3, [r7, #4] 80083c6: f003 0310 and.w r3, r3, #16 80083ca: 409a lsls r2, r3 80083cc: 68fb ldr r3, [r7, #12] 80083ce: 681b ldr r3, [r3, #0] 80083d0: 430a orrs r2, r1 80083d2: 64da str r2, [r3, #76] @ 0x4c (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); } if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) 80083d4: 68bb ldr r3, [r7, #8] 80083d6: 691b ldr r3, [r3, #16] 80083d8: 2b01 cmp r3, #1 80083da: d11d bne.n 8008418 /* USER TRIMMING */ { /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; 80083dc: 68fb ldr r3, [r7, #12] 80083de: 681b ldr r3, [r3, #0] 80083e0: 6b9b ldr r3, [r3, #56] @ 0x38 80083e2: 61bb str r3, [r7, #24] /* Clear trimming value */ tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); 80083e4: 687b ldr r3, [r7, #4] 80083e6: f003 0310 and.w r3, r3, #16 80083ea: 221f movs r2, #31 80083ec: fa02 f303 lsl.w r3, r2, r3 80083f0: 43db mvns r3, r3 80083f2: 69ba ldr r2, [r7, #24] 80083f4: 4013 ands r3, r2 80083f6: 61bb str r3, [r7, #24] /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; 80083f8: 68bb ldr r3, [r7, #8] 80083fa: 695b ldr r3, [r3, #20] 80083fc: 617b str r3, [r7, #20] /* Calculate CCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 80083fe: 687b ldr r3, [r7, #4] 8008400: f003 0310 and.w r3, r3, #16 8008404: 697a ldr r2, [r7, #20] 8008406: fa02 f303 lsl.w r3, r2, r3 800840a: 69ba ldr r2, [r7, #24] 800840c: 4313 orrs r3, r2 800840e: 61bb str r3, [r7, #24] /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; 8008410: 68fb ldr r3, [r7, #12] 8008412: 681b ldr r3, [r3, #0] 8008414: 69ba ldr r2, [r7, #24] 8008416: 639a str r2, [r3, #56] @ 0x38 } /* else factory trimming is used (factory setting are available at reset)*/ /* SW Nothing has nothing to do */ /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; 8008418: 68fb ldr r3, [r7, #12] 800841a: 681b ldr r3, [r3, #0] 800841c: 6bdb ldr r3, [r3, #60] @ 0x3c 800841e: 61bb str r3, [r7, #24] /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); 8008420: 687b ldr r3, [r7, #4] 8008422: f003 0310 and.w r3, r3, #16 8008426: 2207 movs r2, #7 8008428: fa02 f303 lsl.w r3, r2, r3 800842c: 43db mvns r3, r3 800842e: 69ba ldr r2, [r7, #24] 8008430: 4013 ands r3, r2 8008432: 61bb str r3, [r7, #24] /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) 8008434: 68bb ldr r3, [r7, #8] 8008436: 68db ldr r3, [r3, #12] 8008438: 2b01 cmp r3, #1 800843a: d102 bne.n 8008442 { connectOnChip = 0x00000000UL; 800843c: 2300 movs r3, #0 800843e: 627b str r3, [r7, #36] @ 0x24 8008440: e00f b.n 8008462 } else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL) 8008442: 68bb ldr r3, [r7, #8] 8008444: 68db ldr r3, [r3, #12] 8008446: 2b02 cmp r3, #2 8008448: d102 bne.n 8008450 { connectOnChip = DAC_MCR_MODE1_0; 800844a: 2301 movs r3, #1 800844c: 627b str r3, [r7, #36] @ 0x24 800844e: e008 b.n 8008462 } else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */ { if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) 8008450: 68bb ldr r3, [r7, #8] 8008452: 689b ldr r3, [r3, #8] 8008454: 2b00 cmp r3, #0 8008456: d102 bne.n 800845e { connectOnChip = DAC_MCR_MODE1_0; 8008458: 2301 movs r3, #1 800845a: 627b str r3, [r7, #36] @ 0x24 800845c: e001 b.n 8008462 } else { connectOnChip = 0x00000000UL; 800845e: 2300 movs r3, #0 8008460: 627b str r3, [r7, #36] @ 0x24 } } tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); 8008462: 68bb ldr r3, [r7, #8] 8008464: 681a ldr r2, [r3, #0] 8008466: 68bb ldr r3, [r7, #8] 8008468: 689b ldr r3, [r3, #8] 800846a: 4313 orrs r3, r2 800846c: 6a7a ldr r2, [r7, #36] @ 0x24 800846e: 4313 orrs r3, r2 8008470: 617b str r3, [r7, #20] /* Calculate MCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8008472: 687b ldr r3, [r7, #4] 8008474: f003 0310 and.w r3, r3, #16 8008478: 697a ldr r2, [r7, #20] 800847a: fa02 f303 lsl.w r3, r2, r3 800847e: 69ba ldr r2, [r7, #24] 8008480: 4313 orrs r3, r2 8008482: 61bb str r3, [r7, #24] /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; 8008484: 68fb ldr r3, [r7, #12] 8008486: 681b ldr r3, [r3, #0] 8008488: 69ba ldr r2, [r7, #24] 800848a: 63da str r2, [r3, #60] @ 0x3c /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); 800848c: 68fb ldr r3, [r7, #12] 800848e: 681b ldr r3, [r3, #0] 8008490: 6819 ldr r1, [r3, #0] 8008492: 687b ldr r3, [r7, #4] 8008494: f003 0310 and.w r3, r3, #16 8008498: f44f 4280 mov.w r2, #16384 @ 0x4000 800849c: fa02 f303 lsl.w r3, r2, r3 80084a0: 43da mvns r2, r3 80084a2: 68fb ldr r3, [r7, #12] 80084a4: 681b ldr r3, [r3, #0] 80084a6: 400a ands r2, r1 80084a8: 601a str r2, [r3, #0] /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; 80084aa: 68fb ldr r3, [r7, #12] 80084ac: 681b ldr r3, [r3, #0] 80084ae: 681b ldr r3, [r3, #0] 80084b0: 61bb str r3, [r7, #24] /* Clear TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); 80084b2: 687b ldr r3, [r7, #4] 80084b4: f003 0310 and.w r3, r3, #16 80084b8: f640 72fe movw r2, #4094 @ 0xffe 80084bc: fa02 f303 lsl.w r3, r2, r3 80084c0: 43db mvns r3, r3 80084c2: 69ba ldr r2, [r7, #24] 80084c4: 4013 ands r3, r2 80084c6: 61bb str r3, [r7, #24] /* Configure for the selected DAC channel: trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ tmpreg2 = sConfig->DAC_Trigger; 80084c8: 68bb ldr r3, [r7, #8] 80084ca: 685b ldr r3, [r3, #4] 80084cc: 617b str r3, [r7, #20] /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 80084ce: 687b ldr r3, [r7, #4] 80084d0: f003 0310 and.w r3, r3, #16 80084d4: 697a ldr r2, [r7, #20] 80084d6: fa02 f303 lsl.w r3, r2, r3 80084da: 69ba ldr r2, [r7, #24] 80084dc: 4313 orrs r3, r2 80084de: 61bb str r3, [r7, #24] /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; 80084e0: 68fb ldr r3, [r7, #12] 80084e2: 681b ldr r3, [r3, #0] 80084e4: 69ba ldr r2, [r7, #24] 80084e6: 601a str r2, [r3, #0] /* Disable wave generation */ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); 80084e8: 68fb ldr r3, [r7, #12] 80084ea: 681b ldr r3, [r3, #0] 80084ec: 6819 ldr r1, [r3, #0] 80084ee: 687b ldr r3, [r7, #4] 80084f0: f003 0310 and.w r3, r3, #16 80084f4: 22c0 movs r2, #192 @ 0xc0 80084f6: fa02 f303 lsl.w r3, r2, r3 80084fa: 43da mvns r2, r3 80084fc: 68fb ldr r3, [r7, #12] 80084fe: 681b ldr r3, [r3, #0] 8008500: 400a ands r2, r1 8008502: 601a str r2, [r3, #0] /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 8008504: 68fb ldr r3, [r7, #12] 8008506: 2201 movs r2, #1 8008508: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 800850a: 68fb ldr r3, [r7, #12] 800850c: 2200 movs r2, #0 800850e: 715a strb r2, [r3, #5] /* Return function status */ return status; 8008510: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 } 8008514: 4618 mov r0, r3 8008516: 3728 adds r7, #40 @ 0x28 8008518: 46bd mov sp, r7 800851a: bd80 pop {r7, pc} 800851c: 20008000 .word 0x20008000 08008520 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) { 8008520: b480 push {r7} 8008522: b083 sub sp, #12 8008524: af00 add r7, sp, #0 8008526: 6078 str r0, [r7, #4] UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file */ } 8008528: bf00 nop 800852a: 370c adds r7, #12 800852c: 46bd mov sp, r7 800852e: f85d 7b04 ldr.w r7, [sp], #4 8008532: 4770 bx lr 08008534 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8008534: b580 push {r7, lr} 8008536: b086 sub sp, #24 8008538: af00 add r7, sp, #0 800853a: 6078 str r0, [r7, #4] uint32_t registerValue; uint32_t tickstart = HAL_GetTick(); 800853c: f7fd fc5e bl 8005dfc 8008540: 6138 str r0, [r7, #16] DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 8008542: 687b ldr r3, [r7, #4] 8008544: 2b00 cmp r3, #0 8008546: d101 bne.n 800854c { return HAL_ERROR; 8008548: 2301 movs r3, #1 800854a: e316 b.n 8008b7a assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800854c: 687b ldr r3, [r7, #4] 800854e: 681b ldr r3, [r3, #0] 8008550: 4a66 ldr r2, [pc, #408] @ (80086ec ) 8008552: 4293 cmp r3, r2 8008554: d04a beq.n 80085ec 8008556: 687b ldr r3, [r7, #4] 8008558: 681b ldr r3, [r3, #0] 800855a: 4a65 ldr r2, [pc, #404] @ (80086f0 ) 800855c: 4293 cmp r3, r2 800855e: d045 beq.n 80085ec 8008560: 687b ldr r3, [r7, #4] 8008562: 681b ldr r3, [r3, #0] 8008564: 4a63 ldr r2, [pc, #396] @ (80086f4 ) 8008566: 4293 cmp r3, r2 8008568: d040 beq.n 80085ec 800856a: 687b ldr r3, [r7, #4] 800856c: 681b ldr r3, [r3, #0] 800856e: 4a62 ldr r2, [pc, #392] @ (80086f8 ) 8008570: 4293 cmp r3, r2 8008572: d03b beq.n 80085ec 8008574: 687b ldr r3, [r7, #4] 8008576: 681b ldr r3, [r3, #0] 8008578: 4a60 ldr r2, [pc, #384] @ (80086fc ) 800857a: 4293 cmp r3, r2 800857c: d036 beq.n 80085ec 800857e: 687b ldr r3, [r7, #4] 8008580: 681b ldr r3, [r3, #0] 8008582: 4a5f ldr r2, [pc, #380] @ (8008700 ) 8008584: 4293 cmp r3, r2 8008586: d031 beq.n 80085ec 8008588: 687b ldr r3, [r7, #4] 800858a: 681b ldr r3, [r3, #0] 800858c: 4a5d ldr r2, [pc, #372] @ (8008704 ) 800858e: 4293 cmp r3, r2 8008590: d02c beq.n 80085ec 8008592: 687b ldr r3, [r7, #4] 8008594: 681b ldr r3, [r3, #0] 8008596: 4a5c ldr r2, [pc, #368] @ (8008708 ) 8008598: 4293 cmp r3, r2 800859a: d027 beq.n 80085ec 800859c: 687b ldr r3, [r7, #4] 800859e: 681b ldr r3, [r3, #0] 80085a0: 4a5a ldr r2, [pc, #360] @ (800870c ) 80085a2: 4293 cmp r3, r2 80085a4: d022 beq.n 80085ec 80085a6: 687b ldr r3, [r7, #4] 80085a8: 681b ldr r3, [r3, #0] 80085aa: 4a59 ldr r2, [pc, #356] @ (8008710 ) 80085ac: 4293 cmp r3, r2 80085ae: d01d beq.n 80085ec 80085b0: 687b ldr r3, [r7, #4] 80085b2: 681b ldr r3, [r3, #0] 80085b4: 4a57 ldr r2, [pc, #348] @ (8008714 ) 80085b6: 4293 cmp r3, r2 80085b8: d018 beq.n 80085ec 80085ba: 687b ldr r3, [r7, #4] 80085bc: 681b ldr r3, [r3, #0] 80085be: 4a56 ldr r2, [pc, #344] @ (8008718 ) 80085c0: 4293 cmp r3, r2 80085c2: d013 beq.n 80085ec 80085c4: 687b ldr r3, [r7, #4] 80085c6: 681b ldr r3, [r3, #0] 80085c8: 4a54 ldr r2, [pc, #336] @ (800871c ) 80085ca: 4293 cmp r3, r2 80085cc: d00e beq.n 80085ec 80085ce: 687b ldr r3, [r7, #4] 80085d0: 681b ldr r3, [r3, #0] 80085d2: 4a53 ldr r2, [pc, #332] @ (8008720 ) 80085d4: 4293 cmp r3, r2 80085d6: d009 beq.n 80085ec 80085d8: 687b ldr r3, [r7, #4] 80085da: 681b ldr r3, [r3, #0] 80085dc: 4a51 ldr r2, [pc, #324] @ (8008724 ) 80085de: 4293 cmp r3, r2 80085e0: d004 beq.n 80085ec 80085e2: 687b ldr r3, [r7, #4] 80085e4: 681b ldr r3, [r3, #0] 80085e6: 4a50 ldr r2, [pc, #320] @ (8008728 ) 80085e8: 4293 cmp r3, r2 80085ea: d101 bne.n 80085f0 80085ec: 2301 movs r3, #1 80085ee: e000 b.n 80085f2 80085f0: 2300 movs r3, #0 80085f2: 2b00 cmp r3, #0 80085f4: f000 813b beq.w 800886e assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80085f8: 687b ldr r3, [r7, #4] 80085fa: 2202 movs r2, #2 80085fc: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8008600: 687b ldr r3, [r7, #4] 8008602: 2200 movs r2, #0 8008604: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8008608: 687b ldr r3, [r7, #4] 800860a: 681b ldr r3, [r3, #0] 800860c: 4a37 ldr r2, [pc, #220] @ (80086ec ) 800860e: 4293 cmp r3, r2 8008610: d04a beq.n 80086a8 8008612: 687b ldr r3, [r7, #4] 8008614: 681b ldr r3, [r3, #0] 8008616: 4a36 ldr r2, [pc, #216] @ (80086f0 ) 8008618: 4293 cmp r3, r2 800861a: d045 beq.n 80086a8 800861c: 687b ldr r3, [r7, #4] 800861e: 681b ldr r3, [r3, #0] 8008620: 4a34 ldr r2, [pc, #208] @ (80086f4 ) 8008622: 4293 cmp r3, r2 8008624: d040 beq.n 80086a8 8008626: 687b ldr r3, [r7, #4] 8008628: 681b ldr r3, [r3, #0] 800862a: 4a33 ldr r2, [pc, #204] @ (80086f8 ) 800862c: 4293 cmp r3, r2 800862e: d03b beq.n 80086a8 8008630: 687b ldr r3, [r7, #4] 8008632: 681b ldr r3, [r3, #0] 8008634: 4a31 ldr r2, [pc, #196] @ (80086fc ) 8008636: 4293 cmp r3, r2 8008638: d036 beq.n 80086a8 800863a: 687b ldr r3, [r7, #4] 800863c: 681b ldr r3, [r3, #0] 800863e: 4a30 ldr r2, [pc, #192] @ (8008700 ) 8008640: 4293 cmp r3, r2 8008642: d031 beq.n 80086a8 8008644: 687b ldr r3, [r7, #4] 8008646: 681b ldr r3, [r3, #0] 8008648: 4a2e ldr r2, [pc, #184] @ (8008704 ) 800864a: 4293 cmp r3, r2 800864c: d02c beq.n 80086a8 800864e: 687b ldr r3, [r7, #4] 8008650: 681b ldr r3, [r3, #0] 8008652: 4a2d ldr r2, [pc, #180] @ (8008708 ) 8008654: 4293 cmp r3, r2 8008656: d027 beq.n 80086a8 8008658: 687b ldr r3, [r7, #4] 800865a: 681b ldr r3, [r3, #0] 800865c: 4a2b ldr r2, [pc, #172] @ (800870c ) 800865e: 4293 cmp r3, r2 8008660: d022 beq.n 80086a8 8008662: 687b ldr r3, [r7, #4] 8008664: 681b ldr r3, [r3, #0] 8008666: 4a2a ldr r2, [pc, #168] @ (8008710 ) 8008668: 4293 cmp r3, r2 800866a: d01d beq.n 80086a8 800866c: 687b ldr r3, [r7, #4] 800866e: 681b ldr r3, [r3, #0] 8008670: 4a28 ldr r2, [pc, #160] @ (8008714 ) 8008672: 4293 cmp r3, r2 8008674: d018 beq.n 80086a8 8008676: 687b ldr r3, [r7, #4] 8008678: 681b ldr r3, [r3, #0] 800867a: 4a27 ldr r2, [pc, #156] @ (8008718 ) 800867c: 4293 cmp r3, r2 800867e: d013 beq.n 80086a8 8008680: 687b ldr r3, [r7, #4] 8008682: 681b ldr r3, [r3, #0] 8008684: 4a25 ldr r2, [pc, #148] @ (800871c ) 8008686: 4293 cmp r3, r2 8008688: d00e beq.n 80086a8 800868a: 687b ldr r3, [r7, #4] 800868c: 681b ldr r3, [r3, #0] 800868e: 4a24 ldr r2, [pc, #144] @ (8008720 ) 8008690: 4293 cmp r3, r2 8008692: d009 beq.n 80086a8 8008694: 687b ldr r3, [r7, #4] 8008696: 681b ldr r3, [r3, #0] 8008698: 4a22 ldr r2, [pc, #136] @ (8008724 ) 800869a: 4293 cmp r3, r2 800869c: d004 beq.n 80086a8 800869e: 687b ldr r3, [r7, #4] 80086a0: 681b ldr r3, [r3, #0] 80086a2: 4a21 ldr r2, [pc, #132] @ (8008728 ) 80086a4: 4293 cmp r3, r2 80086a6: d108 bne.n 80086ba 80086a8: 687b ldr r3, [r7, #4] 80086aa: 681b ldr r3, [r3, #0] 80086ac: 681a ldr r2, [r3, #0] 80086ae: 687b ldr r3, [r7, #4] 80086b0: 681b ldr r3, [r3, #0] 80086b2: f022 0201 bic.w r2, r2, #1 80086b6: 601a str r2, [r3, #0] 80086b8: e007 b.n 80086ca 80086ba: 687b ldr r3, [r7, #4] 80086bc: 681b ldr r3, [r3, #0] 80086be: 681a ldr r2, [r3, #0] 80086c0: 687b ldr r3, [r7, #4] 80086c2: 681b ldr r3, [r3, #0] 80086c4: f022 0201 bic.w r2, r2, #1 80086c8: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 80086ca: e02f b.n 800872c { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 80086cc: f7fd fb96 bl 8005dfc 80086d0: 4602 mov r2, r0 80086d2: 693b ldr r3, [r7, #16] 80086d4: 1ad3 subs r3, r2, r3 80086d6: 2b05 cmp r3, #5 80086d8: d928 bls.n 800872c { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 80086da: 687b ldr r3, [r7, #4] 80086dc: 2220 movs r2, #32 80086de: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 80086e0: 687b ldr r3, [r7, #4] 80086e2: 2203 movs r2, #3 80086e4: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 80086e8: 2301 movs r3, #1 80086ea: e246 b.n 8008b7a 80086ec: 40020010 .word 0x40020010 80086f0: 40020028 .word 0x40020028 80086f4: 40020040 .word 0x40020040 80086f8: 40020058 .word 0x40020058 80086fc: 40020070 .word 0x40020070 8008700: 40020088 .word 0x40020088 8008704: 400200a0 .word 0x400200a0 8008708: 400200b8 .word 0x400200b8 800870c: 40020410 .word 0x40020410 8008710: 40020428 .word 0x40020428 8008714: 40020440 .word 0x40020440 8008718: 40020458 .word 0x40020458 800871c: 40020470 .word 0x40020470 8008720: 40020488 .word 0x40020488 8008724: 400204a0 .word 0x400204a0 8008728: 400204b8 .word 0x400204b8 while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 800872c: 687b ldr r3, [r7, #4] 800872e: 681b ldr r3, [r3, #0] 8008730: 681b ldr r3, [r3, #0] 8008732: f003 0301 and.w r3, r3, #1 8008736: 2b00 cmp r3, #0 8008738: d1c8 bne.n 80086cc } } /* Get the CR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; 800873a: 687b ldr r3, [r7, #4] 800873c: 681b ldr r3, [r3, #0] 800873e: 681b ldr r3, [r3, #0] 8008740: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 8008742: 697a ldr r2, [r7, #20] 8008744: 4b83 ldr r3, [pc, #524] @ (8008954 ) 8008746: 4013 ands r3, r2 8008748: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ registerValue |= hdma->Init.Direction | 800874a: 687b ldr r3, [r7, #4] 800874c: 689a ldr r2, [r3, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 800874e: 687b ldr r3, [r7, #4] 8008750: 68db ldr r3, [r3, #12] registerValue |= hdma->Init.Direction | 8008752: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8008754: 687b ldr r3, [r7, #4] 8008756: 691b ldr r3, [r3, #16] 8008758: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800875a: 687b ldr r3, [r7, #4] 800875c: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 800875e: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8008760: 687b ldr r3, [r7, #4] 8008762: 699b ldr r3, [r3, #24] 8008764: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8008766: 687b ldr r3, [r7, #4] 8008768: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800876a: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800876c: 687b ldr r3, [r7, #4] 800876e: 6a1b ldr r3, [r3, #32] 8008770: 4313 orrs r3, r2 registerValue |= hdma->Init.Direction | 8008772: 697a ldr r2, [r7, #20] 8008774: 4313 orrs r3, r2 8008776: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8008778: 687b ldr r3, [r7, #4] 800877a: 6a5b ldr r3, [r3, #36] @ 0x24 800877c: 2b04 cmp r3, #4 800877e: d107 bne.n 8008790 { /* Get memory burst and peripheral burst */ registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 8008780: 687b ldr r3, [r7, #4] 8008782: 6ada ldr r2, [r3, #44] @ 0x2c 8008784: 687b ldr r3, [r7, #4] 8008786: 6b1b ldr r3, [r3, #48] @ 0x30 8008788: 4313 orrs r3, r2 800878a: 697a ldr r2, [r7, #20] 800878c: 4313 orrs r3, r2 800878e: 617b str r3, [r7, #20] } /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be lock when transferring data to/from USART/UART */ #if (STM32H7_DEV_ID == 0x450UL) if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) 8008790: 4b71 ldr r3, [pc, #452] @ (8008958 ) 8008792: 681a ldr r2, [r3, #0] 8008794: 4b71 ldr r3, [pc, #452] @ (800895c ) 8008796: 4013 ands r3, r2 8008798: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800879c: d328 bcc.n 80087f0 { #endif /* STM32H7_DEV_ID == 0x450UL */ if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) 800879e: 687b ldr r3, [r7, #4] 80087a0: 685b ldr r3, [r3, #4] 80087a2: 2b28 cmp r3, #40 @ 0x28 80087a4: d903 bls.n 80087ae 80087a6: 687b ldr r3, [r7, #4] 80087a8: 685b ldr r3, [r3, #4] 80087aa: 2b2e cmp r3, #46 @ 0x2e 80087ac: d917 bls.n 80087de 80087ae: 687b ldr r3, [r7, #4] 80087b0: 685b ldr r3, [r3, #4] 80087b2: 2b3e cmp r3, #62 @ 0x3e 80087b4: d903 bls.n 80087be 80087b6: 687b ldr r3, [r7, #4] 80087b8: 685b ldr r3, [r3, #4] 80087ba: 2b42 cmp r3, #66 @ 0x42 80087bc: d90f bls.n 80087de 80087be: 687b ldr r3, [r7, #4] 80087c0: 685b ldr r3, [r3, #4] 80087c2: 2b46 cmp r3, #70 @ 0x46 80087c4: d903 bls.n 80087ce 80087c6: 687b ldr r3, [r7, #4] 80087c8: 685b ldr r3, [r3, #4] 80087ca: 2b48 cmp r3, #72 @ 0x48 80087cc: d907 bls.n 80087de 80087ce: 687b ldr r3, [r7, #4] 80087d0: 685b ldr r3, [r3, #4] 80087d2: 2b4e cmp r3, #78 @ 0x4e 80087d4: d905 bls.n 80087e2 80087d6: 687b ldr r3, [r7, #4] 80087d8: 685b ldr r3, [r3, #4] 80087da: 2b52 cmp r3, #82 @ 0x52 80087dc: d801 bhi.n 80087e2 80087de: 2301 movs r3, #1 80087e0: e000 b.n 80087e4 80087e2: 2300 movs r3, #0 80087e4: 2b00 cmp r3, #0 80087e6: d003 beq.n 80087f0 { registerValue |= DMA_SxCR_TRBUFF; 80087e8: 697b ldr r3, [r7, #20] 80087ea: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80087ee: 617b str r3, [r7, #20] #if (STM32H7_DEV_ID == 0x450UL) } #endif /* STM32H7_DEV_ID == 0x450UL */ /* Write to DMA Stream CR register */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; 80087f0: 687b ldr r3, [r7, #4] 80087f2: 681b ldr r3, [r3, #0] 80087f4: 697a ldr r2, [r7, #20] 80087f6: 601a str r2, [r3, #0] /* Get the FCR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; 80087f8: 687b ldr r3, [r7, #4] 80087fa: 681b ldr r3, [r3, #0] 80087fc: 695b ldr r3, [r3, #20] 80087fe: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8008800: 697b ldr r3, [r7, #20] 8008802: f023 0307 bic.w r3, r3, #7 8008806: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ registerValue |= hdma->Init.FIFOMode; 8008808: 687b ldr r3, [r7, #4] 800880a: 6a5b ldr r3, [r3, #36] @ 0x24 800880c: 697a ldr r2, [r7, #20] 800880e: 4313 orrs r3, r2 8008810: 617b str r3, [r7, #20] /* the FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8008812: 687b ldr r3, [r7, #4] 8008814: 6a5b ldr r3, [r3, #36] @ 0x24 8008816: 2b04 cmp r3, #4 8008818: d117 bne.n 800884a { /* Get the FIFO threshold */ registerValue |= hdma->Init.FIFOThreshold; 800881a: 687b ldr r3, [r7, #4] 800881c: 6a9b ldr r3, [r3, #40] @ 0x28 800881e: 697a ldr r2, [r7, #20] 8008820: 4313 orrs r3, r2 8008822: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 */ if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) 8008824: 687b ldr r3, [r7, #4] 8008826: 6adb ldr r3, [r3, #44] @ 0x2c 8008828: 2b00 cmp r3, #0 800882a: d00e beq.n 800884a { if (DMA_CheckFifoParam(hdma) != HAL_OK) 800882c: 6878 ldr r0, [r7, #4] 800882e: f002 fb33 bl 800ae98 8008832: 4603 mov r3, r0 8008834: 2b00 cmp r3, #0 8008836: d008 beq.n 800884a { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8008838: 687b ldr r3, [r7, #4] 800883a: 2240 movs r2, #64 @ 0x40 800883c: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800883e: 687b ldr r3, [r7, #4] 8008840: 2201 movs r2, #1 8008842: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8008846: 2301 movs r3, #1 8008848: e197 b.n 8008b7a } } } /* Write to DMA Stream FCR */ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; 800884a: 687b ldr r3, [r7, #4] 800884c: 681b ldr r3, [r3, #0] 800884e: 697a ldr r2, [r7, #20] 8008850: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8008852: 6878 ldr r0, [r7, #4] 8008854: f002 fa6e bl 800ad34 8008858: 4603 mov r3, r0 800885a: 60bb str r3, [r7, #8] /* Clear all interrupt flags */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800885c: 687b ldr r3, [r7, #4] 800885e: 6ddb ldr r3, [r3, #92] @ 0x5c 8008860: f003 031f and.w r3, r3, #31 8008864: 223f movs r2, #63 @ 0x3f 8008866: 409a lsls r2, r3 8008868: 68bb ldr r3, [r7, #8] 800886a: 609a str r2, [r3, #8] 800886c: e0cd b.n 8008a0a } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 800886e: 687b ldr r3, [r7, #4] 8008870: 681b ldr r3, [r3, #0] 8008872: 4a3b ldr r2, [pc, #236] @ (8008960 ) 8008874: 4293 cmp r3, r2 8008876: d022 beq.n 80088be 8008878: 687b ldr r3, [r7, #4] 800887a: 681b ldr r3, [r3, #0] 800887c: 4a39 ldr r2, [pc, #228] @ (8008964 ) 800887e: 4293 cmp r3, r2 8008880: d01d beq.n 80088be 8008882: 687b ldr r3, [r7, #4] 8008884: 681b ldr r3, [r3, #0] 8008886: 4a38 ldr r2, [pc, #224] @ (8008968 ) 8008888: 4293 cmp r3, r2 800888a: d018 beq.n 80088be 800888c: 687b ldr r3, [r7, #4] 800888e: 681b ldr r3, [r3, #0] 8008890: 4a36 ldr r2, [pc, #216] @ (800896c ) 8008892: 4293 cmp r3, r2 8008894: d013 beq.n 80088be 8008896: 687b ldr r3, [r7, #4] 8008898: 681b ldr r3, [r3, #0] 800889a: 4a35 ldr r2, [pc, #212] @ (8008970 ) 800889c: 4293 cmp r3, r2 800889e: d00e beq.n 80088be 80088a0: 687b ldr r3, [r7, #4] 80088a2: 681b ldr r3, [r3, #0] 80088a4: 4a33 ldr r2, [pc, #204] @ (8008974 ) 80088a6: 4293 cmp r3, r2 80088a8: d009 beq.n 80088be 80088aa: 687b ldr r3, [r7, #4] 80088ac: 681b ldr r3, [r3, #0] 80088ae: 4a32 ldr r2, [pc, #200] @ (8008978 ) 80088b0: 4293 cmp r3, r2 80088b2: d004 beq.n 80088be 80088b4: 687b ldr r3, [r7, #4] 80088b6: 681b ldr r3, [r3, #0] 80088b8: 4a30 ldr r2, [pc, #192] @ (800897c ) 80088ba: 4293 cmp r3, r2 80088bc: d101 bne.n 80088c2 80088be: 2301 movs r3, #1 80088c0: e000 b.n 80088c4 80088c2: 2300 movs r3, #0 80088c4: 2b00 cmp r3, #0 80088c6: f000 8097 beq.w 80089f8 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 80088ca: 687b ldr r3, [r7, #4] 80088cc: 681b ldr r3, [r3, #0] 80088ce: 4a24 ldr r2, [pc, #144] @ (8008960 ) 80088d0: 4293 cmp r3, r2 80088d2: d021 beq.n 8008918 80088d4: 687b ldr r3, [r7, #4] 80088d6: 681b ldr r3, [r3, #0] 80088d8: 4a22 ldr r2, [pc, #136] @ (8008964 ) 80088da: 4293 cmp r3, r2 80088dc: d01c beq.n 8008918 80088de: 687b ldr r3, [r7, #4] 80088e0: 681b ldr r3, [r3, #0] 80088e2: 4a21 ldr r2, [pc, #132] @ (8008968 ) 80088e4: 4293 cmp r3, r2 80088e6: d017 beq.n 8008918 80088e8: 687b ldr r3, [r7, #4] 80088ea: 681b ldr r3, [r3, #0] 80088ec: 4a1f ldr r2, [pc, #124] @ (800896c ) 80088ee: 4293 cmp r3, r2 80088f0: d012 beq.n 8008918 80088f2: 687b ldr r3, [r7, #4] 80088f4: 681b ldr r3, [r3, #0] 80088f6: 4a1e ldr r2, [pc, #120] @ (8008970 ) 80088f8: 4293 cmp r3, r2 80088fa: d00d beq.n 8008918 80088fc: 687b ldr r3, [r7, #4] 80088fe: 681b ldr r3, [r3, #0] 8008900: 4a1c ldr r2, [pc, #112] @ (8008974 ) 8008902: 4293 cmp r3, r2 8008904: d008 beq.n 8008918 8008906: 687b ldr r3, [r7, #4] 8008908: 681b ldr r3, [r3, #0] 800890a: 4a1b ldr r2, [pc, #108] @ (8008978 ) 800890c: 4293 cmp r3, r2 800890e: d003 beq.n 8008918 8008910: 687b ldr r3, [r7, #4] 8008912: 681b ldr r3, [r3, #0] 8008914: 4a19 ldr r2, [pc, #100] @ (800897c ) 8008916: 4293 cmp r3, r2 /* Check the request parameter */ assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8008918: 687b ldr r3, [r7, #4] 800891a: 2202 movs r2, #2 800891c: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8008920: 687b ldr r3, [r7, #4] 8008922: 2200 movs r2, #0 8008924: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Get the CR register value */ registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; 8008928: 687b ldr r3, [r7, #4] 800892a: 681b ldr r3, [r3, #0] 800892c: 681b ldr r3, [r3, #0] 800892e: 617b str r3, [r7, #20] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */ registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ 8008930: 697a ldr r2, [r7, #20] 8008932: 4b13 ldr r3, [pc, #76] @ (8008980 ) 8008934: 4013 ands r3, r2 8008936: 617b str r3, [r7, #20] BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \ BDMA_CCR_CT)); /* Prepare the DMA Channel configuration */ registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8008938: 687b ldr r3, [r7, #4] 800893a: 689b ldr r3, [r3, #8] 800893c: 2b40 cmp r3, #64 @ 0x40 800893e: d021 beq.n 8008984 8008940: 687b ldr r3, [r7, #4] 8008942: 689b ldr r3, [r3, #8] 8008944: 2b80 cmp r3, #128 @ 0x80 8008946: d102 bne.n 800894e 8008948: f44f 4380 mov.w r3, #16384 @ 0x4000 800894c: e01b b.n 8008986 800894e: 2300 movs r3, #0 8008950: e019 b.n 8008986 8008952: bf00 nop 8008954: fe10803f .word 0xfe10803f 8008958: 5c001000 .word 0x5c001000 800895c: ffff0000 .word 0xffff0000 8008960: 58025408 .word 0x58025408 8008964: 5802541c .word 0x5802541c 8008968: 58025430 .word 0x58025430 800896c: 58025444 .word 0x58025444 8008970: 58025458 .word 0x58025458 8008974: 5802546c .word 0x5802546c 8008978: 58025480 .word 0x58025480 800897c: 58025494 .word 0x58025494 8008980: fffe000f .word 0xfffe000f 8008984: 2310 movs r3, #16 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 8008986: 687a ldr r2, [r7, #4] 8008988: 68d2 ldr r2, [r2, #12] 800898a: 08d2 lsrs r2, r2, #3 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 800898c: 431a orrs r2, r3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 800898e: 687b ldr r3, [r7, #4] 8008990: 691b ldr r3, [r3, #16] 8008992: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 8008994: 431a orrs r2, r3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 8008996: 687b ldr r3, [r7, #4] 8008998: 695b ldr r3, [r3, #20] 800899a: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 800899c: 431a orrs r2, r3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 800899e: 687b ldr r3, [r7, #4] 80089a0: 699b ldr r3, [r3, #24] 80089a2: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 80089a4: 431a orrs r2, r3 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 80089a6: 687b ldr r3, [r7, #4] 80089a8: 69db ldr r3, [r3, #28] 80089aa: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 80089ac: 431a orrs r2, r3 DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); 80089ae: 687b ldr r3, [r7, #4] 80089b0: 6a1b ldr r3, [r3, #32] 80089b2: 091b lsrs r3, r3, #4 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 80089b4: 4313 orrs r3, r2 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 80089b6: 697a ldr r2, [r7, #20] 80089b8: 4313 orrs r3, r2 80089ba: 617b str r3, [r7, #20] /* Write to DMA Channel CR register */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; 80089bc: 687b ldr r3, [r7, #4] 80089be: 681b ldr r3, [r3, #0] 80089c0: 697a ldr r2, [r7, #20] 80089c2: 601a str r2, [r3, #0] /* calculation of the channel index */ hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; 80089c4: 687b ldr r3, [r7, #4] 80089c6: 681b ldr r3, [r3, #0] 80089c8: 461a mov r2, r3 80089ca: 4b6e ldr r3, [pc, #440] @ (8008b84 ) 80089cc: 4413 add r3, r2 80089ce: 4a6e ldr r2, [pc, #440] @ (8008b88 ) 80089d0: fba2 2303 umull r2, r3, r2, r3 80089d4: 091b lsrs r3, r3, #4 80089d6: 009a lsls r2, r3, #2 80089d8: 687b ldr r3, [r7, #4] 80089da: 65da str r2, [r3, #92] @ 0x5c /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 80089dc: 6878 ldr r0, [r7, #4] 80089de: f002 f9a9 bl 800ad34 80089e2: 4603 mov r3, r0 80089e4: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 80089e6: 687b ldr r3, [r7, #4] 80089e8: 6ddb ldr r3, [r3, #92] @ 0x5c 80089ea: f003 031f and.w r3, r3, #31 80089ee: 2201 movs r2, #1 80089f0: 409a lsls r2, r3 80089f2: 68fb ldr r3, [r7, #12] 80089f4: 605a str r2, [r3, #4] 80089f6: e008 b.n 8008a0a } else { hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 80089f8: 687b ldr r3, [r7, #4] 80089fa: 2240 movs r2, #64 @ 0x40 80089fc: 655a str r2, [r3, #84] @ 0x54 hdma->State = HAL_DMA_STATE_ERROR; 80089fe: 687b ldr r3, [r7, #4] 8008a00: 2203 movs r2, #3 8008a02: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8008a06: 2301 movs r3, #1 8008a08: e0b7 b.n 8008b7a } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8008a0a: 687b ldr r3, [r7, #4] 8008a0c: 681b ldr r3, [r3, #0] 8008a0e: 4a5f ldr r2, [pc, #380] @ (8008b8c ) 8008a10: 4293 cmp r3, r2 8008a12: d072 beq.n 8008afa 8008a14: 687b ldr r3, [r7, #4] 8008a16: 681b ldr r3, [r3, #0] 8008a18: 4a5d ldr r2, [pc, #372] @ (8008b90 ) 8008a1a: 4293 cmp r3, r2 8008a1c: d06d beq.n 8008afa 8008a1e: 687b ldr r3, [r7, #4] 8008a20: 681b ldr r3, [r3, #0] 8008a22: 4a5c ldr r2, [pc, #368] @ (8008b94 ) 8008a24: 4293 cmp r3, r2 8008a26: d068 beq.n 8008afa 8008a28: 687b ldr r3, [r7, #4] 8008a2a: 681b ldr r3, [r3, #0] 8008a2c: 4a5a ldr r2, [pc, #360] @ (8008b98 ) 8008a2e: 4293 cmp r3, r2 8008a30: d063 beq.n 8008afa 8008a32: 687b ldr r3, [r7, #4] 8008a34: 681b ldr r3, [r3, #0] 8008a36: 4a59 ldr r2, [pc, #356] @ (8008b9c ) 8008a38: 4293 cmp r3, r2 8008a3a: d05e beq.n 8008afa 8008a3c: 687b ldr r3, [r7, #4] 8008a3e: 681b ldr r3, [r3, #0] 8008a40: 4a57 ldr r2, [pc, #348] @ (8008ba0 ) 8008a42: 4293 cmp r3, r2 8008a44: d059 beq.n 8008afa 8008a46: 687b ldr r3, [r7, #4] 8008a48: 681b ldr r3, [r3, #0] 8008a4a: 4a56 ldr r2, [pc, #344] @ (8008ba4 ) 8008a4c: 4293 cmp r3, r2 8008a4e: d054 beq.n 8008afa 8008a50: 687b ldr r3, [r7, #4] 8008a52: 681b ldr r3, [r3, #0] 8008a54: 4a54 ldr r2, [pc, #336] @ (8008ba8 ) 8008a56: 4293 cmp r3, r2 8008a58: d04f beq.n 8008afa 8008a5a: 687b ldr r3, [r7, #4] 8008a5c: 681b ldr r3, [r3, #0] 8008a5e: 4a53 ldr r2, [pc, #332] @ (8008bac ) 8008a60: 4293 cmp r3, r2 8008a62: d04a beq.n 8008afa 8008a64: 687b ldr r3, [r7, #4] 8008a66: 681b ldr r3, [r3, #0] 8008a68: 4a51 ldr r2, [pc, #324] @ (8008bb0 ) 8008a6a: 4293 cmp r3, r2 8008a6c: d045 beq.n 8008afa 8008a6e: 687b ldr r3, [r7, #4] 8008a70: 681b ldr r3, [r3, #0] 8008a72: 4a50 ldr r2, [pc, #320] @ (8008bb4 ) 8008a74: 4293 cmp r3, r2 8008a76: d040 beq.n 8008afa 8008a78: 687b ldr r3, [r7, #4] 8008a7a: 681b ldr r3, [r3, #0] 8008a7c: 4a4e ldr r2, [pc, #312] @ (8008bb8 ) 8008a7e: 4293 cmp r3, r2 8008a80: d03b beq.n 8008afa 8008a82: 687b ldr r3, [r7, #4] 8008a84: 681b ldr r3, [r3, #0] 8008a86: 4a4d ldr r2, [pc, #308] @ (8008bbc ) 8008a88: 4293 cmp r3, r2 8008a8a: d036 beq.n 8008afa 8008a8c: 687b ldr r3, [r7, #4] 8008a8e: 681b ldr r3, [r3, #0] 8008a90: 4a4b ldr r2, [pc, #300] @ (8008bc0 ) 8008a92: 4293 cmp r3, r2 8008a94: d031 beq.n 8008afa 8008a96: 687b ldr r3, [r7, #4] 8008a98: 681b ldr r3, [r3, #0] 8008a9a: 4a4a ldr r2, [pc, #296] @ (8008bc4 ) 8008a9c: 4293 cmp r3, r2 8008a9e: d02c beq.n 8008afa 8008aa0: 687b ldr r3, [r7, #4] 8008aa2: 681b ldr r3, [r3, #0] 8008aa4: 4a48 ldr r2, [pc, #288] @ (8008bc8 ) 8008aa6: 4293 cmp r3, r2 8008aa8: d027 beq.n 8008afa 8008aaa: 687b ldr r3, [r7, #4] 8008aac: 681b ldr r3, [r3, #0] 8008aae: 4a47 ldr r2, [pc, #284] @ (8008bcc ) 8008ab0: 4293 cmp r3, r2 8008ab2: d022 beq.n 8008afa 8008ab4: 687b ldr r3, [r7, #4] 8008ab6: 681b ldr r3, [r3, #0] 8008ab8: 4a45 ldr r2, [pc, #276] @ (8008bd0 ) 8008aba: 4293 cmp r3, r2 8008abc: d01d beq.n 8008afa 8008abe: 687b ldr r3, [r7, #4] 8008ac0: 681b ldr r3, [r3, #0] 8008ac2: 4a44 ldr r2, [pc, #272] @ (8008bd4 ) 8008ac4: 4293 cmp r3, r2 8008ac6: d018 beq.n 8008afa 8008ac8: 687b ldr r3, [r7, #4] 8008aca: 681b ldr r3, [r3, #0] 8008acc: 4a42 ldr r2, [pc, #264] @ (8008bd8 ) 8008ace: 4293 cmp r3, r2 8008ad0: d013 beq.n 8008afa 8008ad2: 687b ldr r3, [r7, #4] 8008ad4: 681b ldr r3, [r3, #0] 8008ad6: 4a41 ldr r2, [pc, #260] @ (8008bdc ) 8008ad8: 4293 cmp r3, r2 8008ada: d00e beq.n 8008afa 8008adc: 687b ldr r3, [r7, #4] 8008ade: 681b ldr r3, [r3, #0] 8008ae0: 4a3f ldr r2, [pc, #252] @ (8008be0 ) 8008ae2: 4293 cmp r3, r2 8008ae4: d009 beq.n 8008afa 8008ae6: 687b ldr r3, [r7, #4] 8008ae8: 681b ldr r3, [r3, #0] 8008aea: 4a3e ldr r2, [pc, #248] @ (8008be4 ) 8008aec: 4293 cmp r3, r2 8008aee: d004 beq.n 8008afa 8008af0: 687b ldr r3, [r7, #4] 8008af2: 681b ldr r3, [r3, #0] 8008af4: 4a3c ldr r2, [pc, #240] @ (8008be8 ) 8008af6: 4293 cmp r3, r2 8008af8: d101 bne.n 8008afe 8008afa: 2301 movs r3, #1 8008afc: e000 b.n 8008b00 8008afe: 2300 movs r3, #0 8008b00: 2b00 cmp r3, #0 8008b02: d032 beq.n 8008b6a { /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 8008b04: 6878 ldr r0, [r7, #4] 8008b06: f002 fa43 bl 800af90 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 8008b0a: 687b ldr r3, [r7, #4] 8008b0c: 689b ldr r3, [r3, #8] 8008b0e: 2b80 cmp r3, #128 @ 0x80 8008b10: d102 bne.n 8008b18 { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 8008b12: 687b ldr r3, [r7, #4] 8008b14: 2200 movs r2, #0 8008b16: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8008b18: 687b ldr r3, [r7, #4] 8008b1a: 685a ldr r2, [r3, #4] 8008b1c: 687b ldr r3, [r7, #4] 8008b1e: 6e1b ldr r3, [r3, #96] @ 0x60 8008b20: b2d2 uxtb r2, r2 8008b22: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8008b24: 687b ldr r3, [r7, #4] 8008b26: 6e5b ldr r3, [r3, #100] @ 0x64 8008b28: 687a ldr r2, [r7, #4] 8008b2a: 6e92 ldr r2, [r2, #104] @ 0x68 8008b2c: 605a str r2, [r3, #4] /* Initialize parameters for DMAMUX request generator : if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 */ if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) 8008b2e: 687b ldr r3, [r7, #4] 8008b30: 685b ldr r3, [r3, #4] 8008b32: 2b00 cmp r3, #0 8008b34: d010 beq.n 8008b58 8008b36: 687b ldr r3, [r7, #4] 8008b38: 685b ldr r3, [r3, #4] 8008b3a: 2b08 cmp r3, #8 8008b3c: d80c bhi.n 8008b58 { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 8008b3e: 6878 ldr r0, [r7, #4] 8008b40: f002 fac0 bl 800b0c4 /* Reset the DMAMUX request generator register */ hdma->DMAmuxRequestGen->RGCR = 0U; 8008b44: 687b ldr r3, [r7, #4] 8008b46: 6edb ldr r3, [r3, #108] @ 0x6c 8008b48: 2200 movs r2, #0 8008b4a: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8008b4c: 687b ldr r3, [r7, #4] 8008b4e: 6f1b ldr r3, [r3, #112] @ 0x70 8008b50: 687a ldr r2, [r7, #4] 8008b52: 6f52 ldr r2, [r2, #116] @ 0x74 8008b54: 605a str r2, [r3, #4] 8008b56: e008 b.n 8008b6a } else { hdma->DMAmuxRequestGen = 0U; 8008b58: 687b ldr r3, [r7, #4] 8008b5a: 2200 movs r2, #0 8008b5c: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = 0U; 8008b5e: 687b ldr r3, [r7, #4] 8008b60: 2200 movs r2, #0 8008b62: 671a str r2, [r3, #112] @ 0x70 hdma->DMAmuxRequestGenStatusMask = 0U; 8008b64: 687b ldr r3, [r7, #4] 8008b66: 2200 movs r2, #0 8008b68: 675a str r2, [r3, #116] @ 0x74 } } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8008b6a: 687b ldr r3, [r7, #4] 8008b6c: 2200 movs r2, #0 8008b6e: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8008b70: 687b ldr r3, [r7, #4] 8008b72: 2201 movs r2, #1 8008b74: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 8008b78: 2300 movs r3, #0 } 8008b7a: 4618 mov r0, r3 8008b7c: 3718 adds r7, #24 8008b7e: 46bd mov sp, r7 8008b80: bd80 pop {r7, pc} 8008b82: bf00 nop 8008b84: a7fdabf8 .word 0xa7fdabf8 8008b88: cccccccd .word 0xcccccccd 8008b8c: 40020010 .word 0x40020010 8008b90: 40020028 .word 0x40020028 8008b94: 40020040 .word 0x40020040 8008b98: 40020058 .word 0x40020058 8008b9c: 40020070 .word 0x40020070 8008ba0: 40020088 .word 0x40020088 8008ba4: 400200a0 .word 0x400200a0 8008ba8: 400200b8 .word 0x400200b8 8008bac: 40020410 .word 0x40020410 8008bb0: 40020428 .word 0x40020428 8008bb4: 40020440 .word 0x40020440 8008bb8: 40020458 .word 0x40020458 8008bbc: 40020470 .word 0x40020470 8008bc0: 40020488 .word 0x40020488 8008bc4: 400204a0 .word 0x400204a0 8008bc8: 400204b8 .word 0x400204b8 8008bcc: 58025408 .word 0x58025408 8008bd0: 5802541c .word 0x5802541c 8008bd4: 58025430 .word 0x58025430 8008bd8: 58025444 .word 0x58025444 8008bdc: 58025458 .word 0x58025458 8008be0: 5802546c .word 0x5802546c 8008be4: 58025480 .word 0x58025480 8008be8: 58025494 .word 0x58025494 08008bec : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8008bec: b580 push {r7, lr} 8008bee: b086 sub sp, #24 8008bf0: af00 add r7, sp, #0 8008bf2: 60f8 str r0, [r7, #12] 8008bf4: 60b9 str r1, [r7, #8] 8008bf6: 607a str r2, [r7, #4] 8008bf8: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8008bfa: 2300 movs r3, #0 8008bfc: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Check the DMA peripheral handle */ if(hdma == NULL) 8008bfe: 68fb ldr r3, [r7, #12] 8008c00: 2b00 cmp r3, #0 8008c02: d101 bne.n 8008c08 { return HAL_ERROR; 8008c04: 2301 movs r3, #1 8008c06: e226 b.n 8009056 } /* Process locked */ __HAL_LOCK(hdma); 8008c08: 68fb ldr r3, [r7, #12] 8008c0a: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8008c0e: 2b01 cmp r3, #1 8008c10: d101 bne.n 8008c16 8008c12: 2302 movs r3, #2 8008c14: e21f b.n 8009056 8008c16: 68fb ldr r3, [r7, #12] 8008c18: 2201 movs r2, #1 8008c1a: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 8008c1e: 68fb ldr r3, [r7, #12] 8008c20: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8008c24: b2db uxtb r3, r3 8008c26: 2b01 cmp r3, #1 8008c28: f040 820a bne.w 8009040 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8008c2c: 68fb ldr r3, [r7, #12] 8008c2e: 2202 movs r2, #2 8008c30: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8008c34: 68fb ldr r3, [r7, #12] 8008c36: 2200 movs r2, #0 8008c38: 655a str r2, [r3, #84] @ 0x54 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8008c3a: 68fb ldr r3, [r7, #12] 8008c3c: 681b ldr r3, [r3, #0] 8008c3e: 4a68 ldr r2, [pc, #416] @ (8008de0 ) 8008c40: 4293 cmp r3, r2 8008c42: d04a beq.n 8008cda 8008c44: 68fb ldr r3, [r7, #12] 8008c46: 681b ldr r3, [r3, #0] 8008c48: 4a66 ldr r2, [pc, #408] @ (8008de4 ) 8008c4a: 4293 cmp r3, r2 8008c4c: d045 beq.n 8008cda 8008c4e: 68fb ldr r3, [r7, #12] 8008c50: 681b ldr r3, [r3, #0] 8008c52: 4a65 ldr r2, [pc, #404] @ (8008de8 ) 8008c54: 4293 cmp r3, r2 8008c56: d040 beq.n 8008cda 8008c58: 68fb ldr r3, [r7, #12] 8008c5a: 681b ldr r3, [r3, #0] 8008c5c: 4a63 ldr r2, [pc, #396] @ (8008dec ) 8008c5e: 4293 cmp r3, r2 8008c60: d03b beq.n 8008cda 8008c62: 68fb ldr r3, [r7, #12] 8008c64: 681b ldr r3, [r3, #0] 8008c66: 4a62 ldr r2, [pc, #392] @ (8008df0 ) 8008c68: 4293 cmp r3, r2 8008c6a: d036 beq.n 8008cda 8008c6c: 68fb ldr r3, [r7, #12] 8008c6e: 681b ldr r3, [r3, #0] 8008c70: 4a60 ldr r2, [pc, #384] @ (8008df4 ) 8008c72: 4293 cmp r3, r2 8008c74: d031 beq.n 8008cda 8008c76: 68fb ldr r3, [r7, #12] 8008c78: 681b ldr r3, [r3, #0] 8008c7a: 4a5f ldr r2, [pc, #380] @ (8008df8 ) 8008c7c: 4293 cmp r3, r2 8008c7e: d02c beq.n 8008cda 8008c80: 68fb ldr r3, [r7, #12] 8008c82: 681b ldr r3, [r3, #0] 8008c84: 4a5d ldr r2, [pc, #372] @ (8008dfc ) 8008c86: 4293 cmp r3, r2 8008c88: d027 beq.n 8008cda 8008c8a: 68fb ldr r3, [r7, #12] 8008c8c: 681b ldr r3, [r3, #0] 8008c8e: 4a5c ldr r2, [pc, #368] @ (8008e00 ) 8008c90: 4293 cmp r3, r2 8008c92: d022 beq.n 8008cda 8008c94: 68fb ldr r3, [r7, #12] 8008c96: 681b ldr r3, [r3, #0] 8008c98: 4a5a ldr r2, [pc, #360] @ (8008e04 ) 8008c9a: 4293 cmp r3, r2 8008c9c: d01d beq.n 8008cda 8008c9e: 68fb ldr r3, [r7, #12] 8008ca0: 681b ldr r3, [r3, #0] 8008ca2: 4a59 ldr r2, [pc, #356] @ (8008e08 ) 8008ca4: 4293 cmp r3, r2 8008ca6: d018 beq.n 8008cda 8008ca8: 68fb ldr r3, [r7, #12] 8008caa: 681b ldr r3, [r3, #0] 8008cac: 4a57 ldr r2, [pc, #348] @ (8008e0c ) 8008cae: 4293 cmp r3, r2 8008cb0: d013 beq.n 8008cda 8008cb2: 68fb ldr r3, [r7, #12] 8008cb4: 681b ldr r3, [r3, #0] 8008cb6: 4a56 ldr r2, [pc, #344] @ (8008e10 ) 8008cb8: 4293 cmp r3, r2 8008cba: d00e beq.n 8008cda 8008cbc: 68fb ldr r3, [r7, #12] 8008cbe: 681b ldr r3, [r3, #0] 8008cc0: 4a54 ldr r2, [pc, #336] @ (8008e14 ) 8008cc2: 4293 cmp r3, r2 8008cc4: d009 beq.n 8008cda 8008cc6: 68fb ldr r3, [r7, #12] 8008cc8: 681b ldr r3, [r3, #0] 8008cca: 4a53 ldr r2, [pc, #332] @ (8008e18 ) 8008ccc: 4293 cmp r3, r2 8008cce: d004 beq.n 8008cda 8008cd0: 68fb ldr r3, [r7, #12] 8008cd2: 681b ldr r3, [r3, #0] 8008cd4: 4a51 ldr r2, [pc, #324] @ (8008e1c ) 8008cd6: 4293 cmp r3, r2 8008cd8: d108 bne.n 8008cec 8008cda: 68fb ldr r3, [r7, #12] 8008cdc: 681b ldr r3, [r3, #0] 8008cde: 681a ldr r2, [r3, #0] 8008ce0: 68fb ldr r3, [r7, #12] 8008ce2: 681b ldr r3, [r3, #0] 8008ce4: f022 0201 bic.w r2, r2, #1 8008ce8: 601a str r2, [r3, #0] 8008cea: e007 b.n 8008cfc 8008cec: 68fb ldr r3, [r7, #12] 8008cee: 681b ldr r3, [r3, #0] 8008cf0: 681a ldr r2, [r3, #0] 8008cf2: 68fb ldr r3, [r7, #12] 8008cf4: 681b ldr r3, [r3, #0] 8008cf6: f022 0201 bic.w r2, r2, #1 8008cfa: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8008cfc: 683b ldr r3, [r7, #0] 8008cfe: 687a ldr r2, [r7, #4] 8008d00: 68b9 ldr r1, [r7, #8] 8008d02: 68f8 ldr r0, [r7, #12] 8008d04: f001 fe6a bl 800a9dc if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8008d08: 68fb ldr r3, [r7, #12] 8008d0a: 681b ldr r3, [r3, #0] 8008d0c: 4a34 ldr r2, [pc, #208] @ (8008de0 ) 8008d0e: 4293 cmp r3, r2 8008d10: d04a beq.n 8008da8 8008d12: 68fb ldr r3, [r7, #12] 8008d14: 681b ldr r3, [r3, #0] 8008d16: 4a33 ldr r2, [pc, #204] @ (8008de4 ) 8008d18: 4293 cmp r3, r2 8008d1a: d045 beq.n 8008da8 8008d1c: 68fb ldr r3, [r7, #12] 8008d1e: 681b ldr r3, [r3, #0] 8008d20: 4a31 ldr r2, [pc, #196] @ (8008de8 ) 8008d22: 4293 cmp r3, r2 8008d24: d040 beq.n 8008da8 8008d26: 68fb ldr r3, [r7, #12] 8008d28: 681b ldr r3, [r3, #0] 8008d2a: 4a30 ldr r2, [pc, #192] @ (8008dec ) 8008d2c: 4293 cmp r3, r2 8008d2e: d03b beq.n 8008da8 8008d30: 68fb ldr r3, [r7, #12] 8008d32: 681b ldr r3, [r3, #0] 8008d34: 4a2e ldr r2, [pc, #184] @ (8008df0 ) 8008d36: 4293 cmp r3, r2 8008d38: d036 beq.n 8008da8 8008d3a: 68fb ldr r3, [r7, #12] 8008d3c: 681b ldr r3, [r3, #0] 8008d3e: 4a2d ldr r2, [pc, #180] @ (8008df4 ) 8008d40: 4293 cmp r3, r2 8008d42: d031 beq.n 8008da8 8008d44: 68fb ldr r3, [r7, #12] 8008d46: 681b ldr r3, [r3, #0] 8008d48: 4a2b ldr r2, [pc, #172] @ (8008df8 ) 8008d4a: 4293 cmp r3, r2 8008d4c: d02c beq.n 8008da8 8008d4e: 68fb ldr r3, [r7, #12] 8008d50: 681b ldr r3, [r3, #0] 8008d52: 4a2a ldr r2, [pc, #168] @ (8008dfc ) 8008d54: 4293 cmp r3, r2 8008d56: d027 beq.n 8008da8 8008d58: 68fb ldr r3, [r7, #12] 8008d5a: 681b ldr r3, [r3, #0] 8008d5c: 4a28 ldr r2, [pc, #160] @ (8008e00 ) 8008d5e: 4293 cmp r3, r2 8008d60: d022 beq.n 8008da8 8008d62: 68fb ldr r3, [r7, #12] 8008d64: 681b ldr r3, [r3, #0] 8008d66: 4a27 ldr r2, [pc, #156] @ (8008e04 ) 8008d68: 4293 cmp r3, r2 8008d6a: d01d beq.n 8008da8 8008d6c: 68fb ldr r3, [r7, #12] 8008d6e: 681b ldr r3, [r3, #0] 8008d70: 4a25 ldr r2, [pc, #148] @ (8008e08 ) 8008d72: 4293 cmp r3, r2 8008d74: d018 beq.n 8008da8 8008d76: 68fb ldr r3, [r7, #12] 8008d78: 681b ldr r3, [r3, #0] 8008d7a: 4a24 ldr r2, [pc, #144] @ (8008e0c ) 8008d7c: 4293 cmp r3, r2 8008d7e: d013 beq.n 8008da8 8008d80: 68fb ldr r3, [r7, #12] 8008d82: 681b ldr r3, [r3, #0] 8008d84: 4a22 ldr r2, [pc, #136] @ (8008e10 ) 8008d86: 4293 cmp r3, r2 8008d88: d00e beq.n 8008da8 8008d8a: 68fb ldr r3, [r7, #12] 8008d8c: 681b ldr r3, [r3, #0] 8008d8e: 4a21 ldr r2, [pc, #132] @ (8008e14 ) 8008d90: 4293 cmp r3, r2 8008d92: d009 beq.n 8008da8 8008d94: 68fb ldr r3, [r7, #12] 8008d96: 681b ldr r3, [r3, #0] 8008d98: 4a1f ldr r2, [pc, #124] @ (8008e18 ) 8008d9a: 4293 cmp r3, r2 8008d9c: d004 beq.n 8008da8 8008d9e: 68fb ldr r3, [r7, #12] 8008da0: 681b ldr r3, [r3, #0] 8008da2: 4a1e ldr r2, [pc, #120] @ (8008e1c ) 8008da4: 4293 cmp r3, r2 8008da6: d101 bne.n 8008dac 8008da8: 2301 movs r3, #1 8008daa: e000 b.n 8008dae 8008dac: 2300 movs r3, #0 8008dae: 2b00 cmp r3, #0 8008db0: d036 beq.n 8008e20 { /* Enable Common interrupts*/ MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 8008db2: 68fb ldr r3, [r7, #12] 8008db4: 681b ldr r3, [r3, #0] 8008db6: 681b ldr r3, [r3, #0] 8008db8: f023 021e bic.w r2, r3, #30 8008dbc: 68fb ldr r3, [r7, #12] 8008dbe: 681b ldr r3, [r3, #0] 8008dc0: f042 0216 orr.w r2, r2, #22 8008dc4: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8008dc6: 68fb ldr r3, [r7, #12] 8008dc8: 6c1b ldr r3, [r3, #64] @ 0x40 8008dca: 2b00 cmp r3, #0 8008dcc: d03e beq.n 8008e4c { /* Enable Half Transfer IT if corresponding Callback is set */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; 8008dce: 68fb ldr r3, [r7, #12] 8008dd0: 681b ldr r3, [r3, #0] 8008dd2: 681a ldr r2, [r3, #0] 8008dd4: 68fb ldr r3, [r7, #12] 8008dd6: 681b ldr r3, [r3, #0] 8008dd8: f042 0208 orr.w r2, r2, #8 8008ddc: 601a str r2, [r3, #0] 8008dde: e035 b.n 8008e4c 8008de0: 40020010 .word 0x40020010 8008de4: 40020028 .word 0x40020028 8008de8: 40020040 .word 0x40020040 8008dec: 40020058 .word 0x40020058 8008df0: 40020070 .word 0x40020070 8008df4: 40020088 .word 0x40020088 8008df8: 400200a0 .word 0x400200a0 8008dfc: 400200b8 .word 0x400200b8 8008e00: 40020410 .word 0x40020410 8008e04: 40020428 .word 0x40020428 8008e08: 40020440 .word 0x40020440 8008e0c: 40020458 .word 0x40020458 8008e10: 40020470 .word 0x40020470 8008e14: 40020488 .word 0x40020488 8008e18: 400204a0 .word 0x400204a0 8008e1c: 400204b8 .word 0x400204b8 } } else /* BDMA channel */ { /* Enable Common interrupts */ MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE)); 8008e20: 68fb ldr r3, [r7, #12] 8008e22: 681b ldr r3, [r3, #0] 8008e24: 681b ldr r3, [r3, #0] 8008e26: f023 020e bic.w r2, r3, #14 8008e2a: 68fb ldr r3, [r7, #12] 8008e2c: 681b ldr r3, [r3, #0] 8008e2e: f042 020a orr.w r2, r2, #10 8008e32: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8008e34: 68fb ldr r3, [r7, #12] 8008e36: 6c1b ldr r3, [r3, #64] @ 0x40 8008e38: 2b00 cmp r3, #0 8008e3a: d007 beq.n 8008e4c { /*Enable Half Transfer IT if corresponding Callback is set */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; 8008e3c: 68fb ldr r3, [r7, #12] 8008e3e: 681b ldr r3, [r3, #0] 8008e40: 681a ldr r2, [r3, #0] 8008e42: 68fb ldr r3, [r7, #12] 8008e44: 681b ldr r3, [r3, #0] 8008e46: f042 0204 orr.w r2, r2, #4 8008e4a: 601a str r2, [r3, #0] } } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8008e4c: 68fb ldr r3, [r7, #12] 8008e4e: 681b ldr r3, [r3, #0] 8008e50: 4a83 ldr r2, [pc, #524] @ (8009060 ) 8008e52: 4293 cmp r3, r2 8008e54: d072 beq.n 8008f3c 8008e56: 68fb ldr r3, [r7, #12] 8008e58: 681b ldr r3, [r3, #0] 8008e5a: 4a82 ldr r2, [pc, #520] @ (8009064 ) 8008e5c: 4293 cmp r3, r2 8008e5e: d06d beq.n 8008f3c 8008e60: 68fb ldr r3, [r7, #12] 8008e62: 681b ldr r3, [r3, #0] 8008e64: 4a80 ldr r2, [pc, #512] @ (8009068 ) 8008e66: 4293 cmp r3, r2 8008e68: d068 beq.n 8008f3c 8008e6a: 68fb ldr r3, [r7, #12] 8008e6c: 681b ldr r3, [r3, #0] 8008e6e: 4a7f ldr r2, [pc, #508] @ (800906c ) 8008e70: 4293 cmp r3, r2 8008e72: d063 beq.n 8008f3c 8008e74: 68fb ldr r3, [r7, #12] 8008e76: 681b ldr r3, [r3, #0] 8008e78: 4a7d ldr r2, [pc, #500] @ (8009070 ) 8008e7a: 4293 cmp r3, r2 8008e7c: d05e beq.n 8008f3c 8008e7e: 68fb ldr r3, [r7, #12] 8008e80: 681b ldr r3, [r3, #0] 8008e82: 4a7c ldr r2, [pc, #496] @ (8009074 ) 8008e84: 4293 cmp r3, r2 8008e86: d059 beq.n 8008f3c 8008e88: 68fb ldr r3, [r7, #12] 8008e8a: 681b ldr r3, [r3, #0] 8008e8c: 4a7a ldr r2, [pc, #488] @ (8009078 ) 8008e8e: 4293 cmp r3, r2 8008e90: d054 beq.n 8008f3c 8008e92: 68fb ldr r3, [r7, #12] 8008e94: 681b ldr r3, [r3, #0] 8008e96: 4a79 ldr r2, [pc, #484] @ (800907c ) 8008e98: 4293 cmp r3, r2 8008e9a: d04f beq.n 8008f3c 8008e9c: 68fb ldr r3, [r7, #12] 8008e9e: 681b ldr r3, [r3, #0] 8008ea0: 4a77 ldr r2, [pc, #476] @ (8009080 ) 8008ea2: 4293 cmp r3, r2 8008ea4: d04a beq.n 8008f3c 8008ea6: 68fb ldr r3, [r7, #12] 8008ea8: 681b ldr r3, [r3, #0] 8008eaa: 4a76 ldr r2, [pc, #472] @ (8009084 ) 8008eac: 4293 cmp r3, r2 8008eae: d045 beq.n 8008f3c 8008eb0: 68fb ldr r3, [r7, #12] 8008eb2: 681b ldr r3, [r3, #0] 8008eb4: 4a74 ldr r2, [pc, #464] @ (8009088 ) 8008eb6: 4293 cmp r3, r2 8008eb8: d040 beq.n 8008f3c 8008eba: 68fb ldr r3, [r7, #12] 8008ebc: 681b ldr r3, [r3, #0] 8008ebe: 4a73 ldr r2, [pc, #460] @ (800908c ) 8008ec0: 4293 cmp r3, r2 8008ec2: d03b beq.n 8008f3c 8008ec4: 68fb ldr r3, [r7, #12] 8008ec6: 681b ldr r3, [r3, #0] 8008ec8: 4a71 ldr r2, [pc, #452] @ (8009090 ) 8008eca: 4293 cmp r3, r2 8008ecc: d036 beq.n 8008f3c 8008ece: 68fb ldr r3, [r7, #12] 8008ed0: 681b ldr r3, [r3, #0] 8008ed2: 4a70 ldr r2, [pc, #448] @ (8009094 ) 8008ed4: 4293 cmp r3, r2 8008ed6: d031 beq.n 8008f3c 8008ed8: 68fb ldr r3, [r7, #12] 8008eda: 681b ldr r3, [r3, #0] 8008edc: 4a6e ldr r2, [pc, #440] @ (8009098 ) 8008ede: 4293 cmp r3, r2 8008ee0: d02c beq.n 8008f3c 8008ee2: 68fb ldr r3, [r7, #12] 8008ee4: 681b ldr r3, [r3, #0] 8008ee6: 4a6d ldr r2, [pc, #436] @ (800909c ) 8008ee8: 4293 cmp r3, r2 8008eea: d027 beq.n 8008f3c 8008eec: 68fb ldr r3, [r7, #12] 8008eee: 681b ldr r3, [r3, #0] 8008ef0: 4a6b ldr r2, [pc, #428] @ (80090a0 ) 8008ef2: 4293 cmp r3, r2 8008ef4: d022 beq.n 8008f3c 8008ef6: 68fb ldr r3, [r7, #12] 8008ef8: 681b ldr r3, [r3, #0] 8008efa: 4a6a ldr r2, [pc, #424] @ (80090a4 ) 8008efc: 4293 cmp r3, r2 8008efe: d01d beq.n 8008f3c 8008f00: 68fb ldr r3, [r7, #12] 8008f02: 681b ldr r3, [r3, #0] 8008f04: 4a68 ldr r2, [pc, #416] @ (80090a8 ) 8008f06: 4293 cmp r3, r2 8008f08: d018 beq.n 8008f3c 8008f0a: 68fb ldr r3, [r7, #12] 8008f0c: 681b ldr r3, [r3, #0] 8008f0e: 4a67 ldr r2, [pc, #412] @ (80090ac ) 8008f10: 4293 cmp r3, r2 8008f12: d013 beq.n 8008f3c 8008f14: 68fb ldr r3, [r7, #12] 8008f16: 681b ldr r3, [r3, #0] 8008f18: 4a65 ldr r2, [pc, #404] @ (80090b0 ) 8008f1a: 4293 cmp r3, r2 8008f1c: d00e beq.n 8008f3c 8008f1e: 68fb ldr r3, [r7, #12] 8008f20: 681b ldr r3, [r3, #0] 8008f22: 4a64 ldr r2, [pc, #400] @ (80090b4 ) 8008f24: 4293 cmp r3, r2 8008f26: d009 beq.n 8008f3c 8008f28: 68fb ldr r3, [r7, #12] 8008f2a: 681b ldr r3, [r3, #0] 8008f2c: 4a62 ldr r2, [pc, #392] @ (80090b8 ) 8008f2e: 4293 cmp r3, r2 8008f30: d004 beq.n 8008f3c 8008f32: 68fb ldr r3, [r7, #12] 8008f34: 681b ldr r3, [r3, #0] 8008f36: 4a61 ldr r2, [pc, #388] @ (80090bc ) 8008f38: 4293 cmp r3, r2 8008f3a: d101 bne.n 8008f40 8008f3c: 2301 movs r3, #1 8008f3e: e000 b.n 8008f42 8008f40: 2300 movs r3, #0 8008f42: 2b00 cmp r3, #0 8008f44: d01a beq.n 8008f7c { /* Check if DMAMUX Synchronization is enabled */ if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) 8008f46: 68fb ldr r3, [r7, #12] 8008f48: 6e1b ldr r3, [r3, #96] @ 0x60 8008f4a: 681b ldr r3, [r3, #0] 8008f4c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8008f50: 2b00 cmp r3, #0 8008f52: d007 beq.n 8008f64 { /* Enable DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; 8008f54: 68fb ldr r3, [r7, #12] 8008f56: 6e1b ldr r3, [r3, #96] @ 0x60 8008f58: 681a ldr r2, [r3, #0] 8008f5a: 68fb ldr r3, [r7, #12] 8008f5c: 6e1b ldr r3, [r3, #96] @ 0x60 8008f5e: f442 7280 orr.w r2, r2, #256 @ 0x100 8008f62: 601a str r2, [r3, #0] } if(hdma->DMAmuxRequestGen != 0U) 8008f64: 68fb ldr r3, [r7, #12] 8008f66: 6edb ldr r3, [r3, #108] @ 0x6c 8008f68: 2b00 cmp r3, #0 8008f6a: d007 beq.n 8008f7c { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 8008f6c: 68fb ldr r3, [r7, #12] 8008f6e: 6edb ldr r3, [r3, #108] @ 0x6c 8008f70: 681a ldr r2, [r3, #0] 8008f72: 68fb ldr r3, [r7, #12] 8008f74: 6edb ldr r3, [r3, #108] @ 0x6c 8008f76: f442 7280 orr.w r2, r2, #256 @ 0x100 8008f7a: 601a str r2, [r3, #0] } } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8008f7c: 68fb ldr r3, [r7, #12] 8008f7e: 681b ldr r3, [r3, #0] 8008f80: 4a37 ldr r2, [pc, #220] @ (8009060 ) 8008f82: 4293 cmp r3, r2 8008f84: d04a beq.n 800901c 8008f86: 68fb ldr r3, [r7, #12] 8008f88: 681b ldr r3, [r3, #0] 8008f8a: 4a36 ldr r2, [pc, #216] @ (8009064 ) 8008f8c: 4293 cmp r3, r2 8008f8e: d045 beq.n 800901c 8008f90: 68fb ldr r3, [r7, #12] 8008f92: 681b ldr r3, [r3, #0] 8008f94: 4a34 ldr r2, [pc, #208] @ (8009068 ) 8008f96: 4293 cmp r3, r2 8008f98: d040 beq.n 800901c 8008f9a: 68fb ldr r3, [r7, #12] 8008f9c: 681b ldr r3, [r3, #0] 8008f9e: 4a33 ldr r2, [pc, #204] @ (800906c ) 8008fa0: 4293 cmp r3, r2 8008fa2: d03b beq.n 800901c 8008fa4: 68fb ldr r3, [r7, #12] 8008fa6: 681b ldr r3, [r3, #0] 8008fa8: 4a31 ldr r2, [pc, #196] @ (8009070 ) 8008faa: 4293 cmp r3, r2 8008fac: d036 beq.n 800901c 8008fae: 68fb ldr r3, [r7, #12] 8008fb0: 681b ldr r3, [r3, #0] 8008fb2: 4a30 ldr r2, [pc, #192] @ (8009074 ) 8008fb4: 4293 cmp r3, r2 8008fb6: d031 beq.n 800901c 8008fb8: 68fb ldr r3, [r7, #12] 8008fba: 681b ldr r3, [r3, #0] 8008fbc: 4a2e ldr r2, [pc, #184] @ (8009078 ) 8008fbe: 4293 cmp r3, r2 8008fc0: d02c beq.n 800901c 8008fc2: 68fb ldr r3, [r7, #12] 8008fc4: 681b ldr r3, [r3, #0] 8008fc6: 4a2d ldr r2, [pc, #180] @ (800907c ) 8008fc8: 4293 cmp r3, r2 8008fca: d027 beq.n 800901c 8008fcc: 68fb ldr r3, [r7, #12] 8008fce: 681b ldr r3, [r3, #0] 8008fd0: 4a2b ldr r2, [pc, #172] @ (8009080 ) 8008fd2: 4293 cmp r3, r2 8008fd4: d022 beq.n 800901c 8008fd6: 68fb ldr r3, [r7, #12] 8008fd8: 681b ldr r3, [r3, #0] 8008fda: 4a2a ldr r2, [pc, #168] @ (8009084 ) 8008fdc: 4293 cmp r3, r2 8008fde: d01d beq.n 800901c 8008fe0: 68fb ldr r3, [r7, #12] 8008fe2: 681b ldr r3, [r3, #0] 8008fe4: 4a28 ldr r2, [pc, #160] @ (8009088 ) 8008fe6: 4293 cmp r3, r2 8008fe8: d018 beq.n 800901c 8008fea: 68fb ldr r3, [r7, #12] 8008fec: 681b ldr r3, [r3, #0] 8008fee: 4a27 ldr r2, [pc, #156] @ (800908c ) 8008ff0: 4293 cmp r3, r2 8008ff2: d013 beq.n 800901c 8008ff4: 68fb ldr r3, [r7, #12] 8008ff6: 681b ldr r3, [r3, #0] 8008ff8: 4a25 ldr r2, [pc, #148] @ (8009090 ) 8008ffa: 4293 cmp r3, r2 8008ffc: d00e beq.n 800901c 8008ffe: 68fb ldr r3, [r7, #12] 8009000: 681b ldr r3, [r3, #0] 8009002: 4a24 ldr r2, [pc, #144] @ (8009094 ) 8009004: 4293 cmp r3, r2 8009006: d009 beq.n 800901c 8009008: 68fb ldr r3, [r7, #12] 800900a: 681b ldr r3, [r3, #0] 800900c: 4a22 ldr r2, [pc, #136] @ (8009098 ) 800900e: 4293 cmp r3, r2 8009010: d004 beq.n 800901c 8009012: 68fb ldr r3, [r7, #12] 8009014: 681b ldr r3, [r3, #0] 8009016: 4a21 ldr r2, [pc, #132] @ (800909c ) 8009018: 4293 cmp r3, r2 800901a: d108 bne.n 800902e 800901c: 68fb ldr r3, [r7, #12] 800901e: 681b ldr r3, [r3, #0] 8009020: 681a ldr r2, [r3, #0] 8009022: 68fb ldr r3, [r7, #12] 8009024: 681b ldr r3, [r3, #0] 8009026: f042 0201 orr.w r2, r2, #1 800902a: 601a str r2, [r3, #0] 800902c: e012 b.n 8009054 800902e: 68fb ldr r3, [r7, #12] 8009030: 681b ldr r3, [r3, #0] 8009032: 681a ldr r2, [r3, #0] 8009034: 68fb ldr r3, [r7, #12] 8009036: 681b ldr r3, [r3, #0] 8009038: f042 0201 orr.w r2, r2, #1 800903c: 601a str r2, [r3, #0] 800903e: e009 b.n 8009054 } else { /* Set the error code to busy */ hdma->ErrorCode = HAL_DMA_ERROR_BUSY; 8009040: 68fb ldr r3, [r7, #12] 8009042: f44f 6200 mov.w r2, #2048 @ 0x800 8009046: 655a str r2, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hdma); 8009048: 68fb ldr r3, [r7, #12] 800904a: 2200 movs r2, #0 800904c: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Return error status */ status = HAL_ERROR; 8009050: 2301 movs r3, #1 8009052: 75fb strb r3, [r7, #23] } return status; 8009054: 7dfb ldrb r3, [r7, #23] } 8009056: 4618 mov r0, r3 8009058: 3718 adds r7, #24 800905a: 46bd mov sp, r7 800905c: bd80 pop {r7, pc} 800905e: bf00 nop 8009060: 40020010 .word 0x40020010 8009064: 40020028 .word 0x40020028 8009068: 40020040 .word 0x40020040 800906c: 40020058 .word 0x40020058 8009070: 40020070 .word 0x40020070 8009074: 40020088 .word 0x40020088 8009078: 400200a0 .word 0x400200a0 800907c: 400200b8 .word 0x400200b8 8009080: 40020410 .word 0x40020410 8009084: 40020428 .word 0x40020428 8009088: 40020440 .word 0x40020440 800908c: 40020458 .word 0x40020458 8009090: 40020470 .word 0x40020470 8009094: 40020488 .word 0x40020488 8009098: 400204a0 .word 0x400204a0 800909c: 400204b8 .word 0x400204b8 80090a0: 58025408 .word 0x58025408 80090a4: 5802541c .word 0x5802541c 80090a8: 58025430 .word 0x58025430 80090ac: 58025444 .word 0x58025444 80090b0: 58025458 .word 0x58025458 80090b4: 5802546c .word 0x5802546c 80090b8: 58025480 .word 0x58025480 80090bc: 58025494 .word 0x58025494 080090c0 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 80090c0: b580 push {r7, lr} 80090c2: b086 sub sp, #24 80090c4: af00 add r7, sp, #0 80090c6: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; const __IO uint32_t *enableRegister; uint32_t tickstart = HAL_GetTick(); 80090c8: f7fc fe98 bl 8005dfc 80090cc: 6138 str r0, [r7, #16] /* Check the DMA peripheral handle */ if(hdma == NULL) 80090ce: 687b ldr r3, [r7, #4] 80090d0: 2b00 cmp r3, #0 80090d2: d101 bne.n 80090d8 { return HAL_ERROR; 80090d4: 2301 movs r3, #1 80090d6: e2dc b.n 8009692 } /* Check the DMA peripheral state */ if(hdma->State != HAL_DMA_STATE_BUSY) 80090d8: 687b ldr r3, [r7, #4] 80090da: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 80090de: b2db uxtb r3, r3 80090e0: 2b02 cmp r3, #2 80090e2: d008 beq.n 80090f6 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80090e4: 687b ldr r3, [r7, #4] 80090e6: 2280 movs r2, #128 @ 0x80 80090e8: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80090ea: 687b ldr r3, [r7, #4] 80090ec: 2200 movs r2, #0 80090ee: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 80090f2: 2301 movs r3, #1 80090f4: e2cd b.n 8009692 } else { /* Disable all the transfer interrupts */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80090f6: 687b ldr r3, [r7, #4] 80090f8: 681b ldr r3, [r3, #0] 80090fa: 4a76 ldr r2, [pc, #472] @ (80092d4 ) 80090fc: 4293 cmp r3, r2 80090fe: d04a beq.n 8009196 8009100: 687b ldr r3, [r7, #4] 8009102: 681b ldr r3, [r3, #0] 8009104: 4a74 ldr r2, [pc, #464] @ (80092d8 ) 8009106: 4293 cmp r3, r2 8009108: d045 beq.n 8009196 800910a: 687b ldr r3, [r7, #4] 800910c: 681b ldr r3, [r3, #0] 800910e: 4a73 ldr r2, [pc, #460] @ (80092dc ) 8009110: 4293 cmp r3, r2 8009112: d040 beq.n 8009196 8009114: 687b ldr r3, [r7, #4] 8009116: 681b ldr r3, [r3, #0] 8009118: 4a71 ldr r2, [pc, #452] @ (80092e0 ) 800911a: 4293 cmp r3, r2 800911c: d03b beq.n 8009196 800911e: 687b ldr r3, [r7, #4] 8009120: 681b ldr r3, [r3, #0] 8009122: 4a70 ldr r2, [pc, #448] @ (80092e4 ) 8009124: 4293 cmp r3, r2 8009126: d036 beq.n 8009196 8009128: 687b ldr r3, [r7, #4] 800912a: 681b ldr r3, [r3, #0] 800912c: 4a6e ldr r2, [pc, #440] @ (80092e8 ) 800912e: 4293 cmp r3, r2 8009130: d031 beq.n 8009196 8009132: 687b ldr r3, [r7, #4] 8009134: 681b ldr r3, [r3, #0] 8009136: 4a6d ldr r2, [pc, #436] @ (80092ec ) 8009138: 4293 cmp r3, r2 800913a: d02c beq.n 8009196 800913c: 687b ldr r3, [r7, #4] 800913e: 681b ldr r3, [r3, #0] 8009140: 4a6b ldr r2, [pc, #428] @ (80092f0 ) 8009142: 4293 cmp r3, r2 8009144: d027 beq.n 8009196 8009146: 687b ldr r3, [r7, #4] 8009148: 681b ldr r3, [r3, #0] 800914a: 4a6a ldr r2, [pc, #424] @ (80092f4 ) 800914c: 4293 cmp r3, r2 800914e: d022 beq.n 8009196 8009150: 687b ldr r3, [r7, #4] 8009152: 681b ldr r3, [r3, #0] 8009154: 4a68 ldr r2, [pc, #416] @ (80092f8 ) 8009156: 4293 cmp r3, r2 8009158: d01d beq.n 8009196 800915a: 687b ldr r3, [r7, #4] 800915c: 681b ldr r3, [r3, #0] 800915e: 4a67 ldr r2, [pc, #412] @ (80092fc ) 8009160: 4293 cmp r3, r2 8009162: d018 beq.n 8009196 8009164: 687b ldr r3, [r7, #4] 8009166: 681b ldr r3, [r3, #0] 8009168: 4a65 ldr r2, [pc, #404] @ (8009300 ) 800916a: 4293 cmp r3, r2 800916c: d013 beq.n 8009196 800916e: 687b ldr r3, [r7, #4] 8009170: 681b ldr r3, [r3, #0] 8009172: 4a64 ldr r2, [pc, #400] @ (8009304 ) 8009174: 4293 cmp r3, r2 8009176: d00e beq.n 8009196 8009178: 687b ldr r3, [r7, #4] 800917a: 681b ldr r3, [r3, #0] 800917c: 4a62 ldr r2, [pc, #392] @ (8009308 ) 800917e: 4293 cmp r3, r2 8009180: d009 beq.n 8009196 8009182: 687b ldr r3, [r7, #4] 8009184: 681b ldr r3, [r3, #0] 8009186: 4a61 ldr r2, [pc, #388] @ (800930c ) 8009188: 4293 cmp r3, r2 800918a: d004 beq.n 8009196 800918c: 687b ldr r3, [r7, #4] 800918e: 681b ldr r3, [r3, #0] 8009190: 4a5f ldr r2, [pc, #380] @ (8009310 ) 8009192: 4293 cmp r3, r2 8009194: d101 bne.n 800919a 8009196: 2301 movs r3, #1 8009198: e000 b.n 800919c 800919a: 2300 movs r3, #0 800919c: 2b00 cmp r3, #0 800919e: d013 beq.n 80091c8 { /* Disable DMA All Interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 80091a0: 687b ldr r3, [r7, #4] 80091a2: 681b ldr r3, [r3, #0] 80091a4: 681a ldr r2, [r3, #0] 80091a6: 687b ldr r3, [r7, #4] 80091a8: 681b ldr r3, [r3, #0] 80091aa: f022 021e bic.w r2, r2, #30 80091ae: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 80091b0: 687b ldr r3, [r7, #4] 80091b2: 681b ldr r3, [r3, #0] 80091b4: 695a ldr r2, [r3, #20] 80091b6: 687b ldr r3, [r7, #4] 80091b8: 681b ldr r3, [r3, #0] 80091ba: f022 0280 bic.w r2, r2, #128 @ 0x80 80091be: 615a str r2, [r3, #20] enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); 80091c0: 687b ldr r3, [r7, #4] 80091c2: 681b ldr r3, [r3, #0] 80091c4: 617b str r3, [r7, #20] 80091c6: e00a b.n 80091de } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 80091c8: 687b ldr r3, [r7, #4] 80091ca: 681b ldr r3, [r3, #0] 80091cc: 681a ldr r2, [r3, #0] 80091ce: 687b ldr r3, [r7, #4] 80091d0: 681b ldr r3, [r3, #0] 80091d2: f022 020e bic.w r2, r2, #14 80091d6: 601a str r2, [r3, #0] enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); 80091d8: 687b ldr r3, [r7, #4] 80091da: 681b ldr r3, [r3, #0] 80091dc: 617b str r3, [r7, #20] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80091de: 687b ldr r3, [r7, #4] 80091e0: 681b ldr r3, [r3, #0] 80091e2: 4a3c ldr r2, [pc, #240] @ (80092d4 ) 80091e4: 4293 cmp r3, r2 80091e6: d072 beq.n 80092ce 80091e8: 687b ldr r3, [r7, #4] 80091ea: 681b ldr r3, [r3, #0] 80091ec: 4a3a ldr r2, [pc, #232] @ (80092d8 ) 80091ee: 4293 cmp r3, r2 80091f0: d06d beq.n 80092ce 80091f2: 687b ldr r3, [r7, #4] 80091f4: 681b ldr r3, [r3, #0] 80091f6: 4a39 ldr r2, [pc, #228] @ (80092dc ) 80091f8: 4293 cmp r3, r2 80091fa: d068 beq.n 80092ce 80091fc: 687b ldr r3, [r7, #4] 80091fe: 681b ldr r3, [r3, #0] 8009200: 4a37 ldr r2, [pc, #220] @ (80092e0 ) 8009202: 4293 cmp r3, r2 8009204: d063 beq.n 80092ce 8009206: 687b ldr r3, [r7, #4] 8009208: 681b ldr r3, [r3, #0] 800920a: 4a36 ldr r2, [pc, #216] @ (80092e4 ) 800920c: 4293 cmp r3, r2 800920e: d05e beq.n 80092ce 8009210: 687b ldr r3, [r7, #4] 8009212: 681b ldr r3, [r3, #0] 8009214: 4a34 ldr r2, [pc, #208] @ (80092e8 ) 8009216: 4293 cmp r3, r2 8009218: d059 beq.n 80092ce 800921a: 687b ldr r3, [r7, #4] 800921c: 681b ldr r3, [r3, #0] 800921e: 4a33 ldr r2, [pc, #204] @ (80092ec ) 8009220: 4293 cmp r3, r2 8009222: d054 beq.n 80092ce 8009224: 687b ldr r3, [r7, #4] 8009226: 681b ldr r3, [r3, #0] 8009228: 4a31 ldr r2, [pc, #196] @ (80092f0 ) 800922a: 4293 cmp r3, r2 800922c: d04f beq.n 80092ce 800922e: 687b ldr r3, [r7, #4] 8009230: 681b ldr r3, [r3, #0] 8009232: 4a30 ldr r2, [pc, #192] @ (80092f4 ) 8009234: 4293 cmp r3, r2 8009236: d04a beq.n 80092ce 8009238: 687b ldr r3, [r7, #4] 800923a: 681b ldr r3, [r3, #0] 800923c: 4a2e ldr r2, [pc, #184] @ (80092f8 ) 800923e: 4293 cmp r3, r2 8009240: d045 beq.n 80092ce 8009242: 687b ldr r3, [r7, #4] 8009244: 681b ldr r3, [r3, #0] 8009246: 4a2d ldr r2, [pc, #180] @ (80092fc ) 8009248: 4293 cmp r3, r2 800924a: d040 beq.n 80092ce 800924c: 687b ldr r3, [r7, #4] 800924e: 681b ldr r3, [r3, #0] 8009250: 4a2b ldr r2, [pc, #172] @ (8009300 ) 8009252: 4293 cmp r3, r2 8009254: d03b beq.n 80092ce 8009256: 687b ldr r3, [r7, #4] 8009258: 681b ldr r3, [r3, #0] 800925a: 4a2a ldr r2, [pc, #168] @ (8009304 ) 800925c: 4293 cmp r3, r2 800925e: d036 beq.n 80092ce 8009260: 687b ldr r3, [r7, #4] 8009262: 681b ldr r3, [r3, #0] 8009264: 4a28 ldr r2, [pc, #160] @ (8009308 ) 8009266: 4293 cmp r3, r2 8009268: d031 beq.n 80092ce 800926a: 687b ldr r3, [r7, #4] 800926c: 681b ldr r3, [r3, #0] 800926e: 4a27 ldr r2, [pc, #156] @ (800930c ) 8009270: 4293 cmp r3, r2 8009272: d02c beq.n 80092ce 8009274: 687b ldr r3, [r7, #4] 8009276: 681b ldr r3, [r3, #0] 8009278: 4a25 ldr r2, [pc, #148] @ (8009310 ) 800927a: 4293 cmp r3, r2 800927c: d027 beq.n 80092ce 800927e: 687b ldr r3, [r7, #4] 8009280: 681b ldr r3, [r3, #0] 8009282: 4a24 ldr r2, [pc, #144] @ (8009314 ) 8009284: 4293 cmp r3, r2 8009286: d022 beq.n 80092ce 8009288: 687b ldr r3, [r7, #4] 800928a: 681b ldr r3, [r3, #0] 800928c: 4a22 ldr r2, [pc, #136] @ (8009318 ) 800928e: 4293 cmp r3, r2 8009290: d01d beq.n 80092ce 8009292: 687b ldr r3, [r7, #4] 8009294: 681b ldr r3, [r3, #0] 8009296: 4a21 ldr r2, [pc, #132] @ (800931c ) 8009298: 4293 cmp r3, r2 800929a: d018 beq.n 80092ce 800929c: 687b ldr r3, [r7, #4] 800929e: 681b ldr r3, [r3, #0] 80092a0: 4a1f ldr r2, [pc, #124] @ (8009320 ) 80092a2: 4293 cmp r3, r2 80092a4: d013 beq.n 80092ce 80092a6: 687b ldr r3, [r7, #4] 80092a8: 681b ldr r3, [r3, #0] 80092aa: 4a1e ldr r2, [pc, #120] @ (8009324 ) 80092ac: 4293 cmp r3, r2 80092ae: d00e beq.n 80092ce 80092b0: 687b ldr r3, [r7, #4] 80092b2: 681b ldr r3, [r3, #0] 80092b4: 4a1c ldr r2, [pc, #112] @ (8009328 ) 80092b6: 4293 cmp r3, r2 80092b8: d009 beq.n 80092ce 80092ba: 687b ldr r3, [r7, #4] 80092bc: 681b ldr r3, [r3, #0] 80092be: 4a1b ldr r2, [pc, #108] @ (800932c ) 80092c0: 4293 cmp r3, r2 80092c2: d004 beq.n 80092ce 80092c4: 687b ldr r3, [r7, #4] 80092c6: 681b ldr r3, [r3, #0] 80092c8: 4a19 ldr r2, [pc, #100] @ (8009330 ) 80092ca: 4293 cmp r3, r2 80092cc: d132 bne.n 8009334 80092ce: 2301 movs r3, #1 80092d0: e031 b.n 8009336 80092d2: bf00 nop 80092d4: 40020010 .word 0x40020010 80092d8: 40020028 .word 0x40020028 80092dc: 40020040 .word 0x40020040 80092e0: 40020058 .word 0x40020058 80092e4: 40020070 .word 0x40020070 80092e8: 40020088 .word 0x40020088 80092ec: 400200a0 .word 0x400200a0 80092f0: 400200b8 .word 0x400200b8 80092f4: 40020410 .word 0x40020410 80092f8: 40020428 .word 0x40020428 80092fc: 40020440 .word 0x40020440 8009300: 40020458 .word 0x40020458 8009304: 40020470 .word 0x40020470 8009308: 40020488 .word 0x40020488 800930c: 400204a0 .word 0x400204a0 8009310: 400204b8 .word 0x400204b8 8009314: 58025408 .word 0x58025408 8009318: 5802541c .word 0x5802541c 800931c: 58025430 .word 0x58025430 8009320: 58025444 .word 0x58025444 8009324: 58025458 .word 0x58025458 8009328: 5802546c .word 0x5802546c 800932c: 58025480 .word 0x58025480 8009330: 58025494 .word 0x58025494 8009334: 2300 movs r3, #0 8009336: 2b00 cmp r3, #0 8009338: d007 beq.n 800934a { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 800933a: 687b ldr r3, [r7, #4] 800933c: 6e1b ldr r3, [r3, #96] @ 0x60 800933e: 681a ldr r2, [r3, #0] 8009340: 687b ldr r3, [r7, #4] 8009342: 6e1b ldr r3, [r3, #96] @ 0x60 8009344: f422 7280 bic.w r2, r2, #256 @ 0x100 8009348: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800934a: 687b ldr r3, [r7, #4] 800934c: 681b ldr r3, [r3, #0] 800934e: 4a6d ldr r2, [pc, #436] @ (8009504 ) 8009350: 4293 cmp r3, r2 8009352: d04a beq.n 80093ea 8009354: 687b ldr r3, [r7, #4] 8009356: 681b ldr r3, [r3, #0] 8009358: 4a6b ldr r2, [pc, #428] @ (8009508 ) 800935a: 4293 cmp r3, r2 800935c: d045 beq.n 80093ea 800935e: 687b ldr r3, [r7, #4] 8009360: 681b ldr r3, [r3, #0] 8009362: 4a6a ldr r2, [pc, #424] @ (800950c ) 8009364: 4293 cmp r3, r2 8009366: d040 beq.n 80093ea 8009368: 687b ldr r3, [r7, #4] 800936a: 681b ldr r3, [r3, #0] 800936c: 4a68 ldr r2, [pc, #416] @ (8009510 ) 800936e: 4293 cmp r3, r2 8009370: d03b beq.n 80093ea 8009372: 687b ldr r3, [r7, #4] 8009374: 681b ldr r3, [r3, #0] 8009376: 4a67 ldr r2, [pc, #412] @ (8009514 ) 8009378: 4293 cmp r3, r2 800937a: d036 beq.n 80093ea 800937c: 687b ldr r3, [r7, #4] 800937e: 681b ldr r3, [r3, #0] 8009380: 4a65 ldr r2, [pc, #404] @ (8009518 ) 8009382: 4293 cmp r3, r2 8009384: d031 beq.n 80093ea 8009386: 687b ldr r3, [r7, #4] 8009388: 681b ldr r3, [r3, #0] 800938a: 4a64 ldr r2, [pc, #400] @ (800951c ) 800938c: 4293 cmp r3, r2 800938e: d02c beq.n 80093ea 8009390: 687b ldr r3, [r7, #4] 8009392: 681b ldr r3, [r3, #0] 8009394: 4a62 ldr r2, [pc, #392] @ (8009520 ) 8009396: 4293 cmp r3, r2 8009398: d027 beq.n 80093ea 800939a: 687b ldr r3, [r7, #4] 800939c: 681b ldr r3, [r3, #0] 800939e: 4a61 ldr r2, [pc, #388] @ (8009524 ) 80093a0: 4293 cmp r3, r2 80093a2: d022 beq.n 80093ea 80093a4: 687b ldr r3, [r7, #4] 80093a6: 681b ldr r3, [r3, #0] 80093a8: 4a5f ldr r2, [pc, #380] @ (8009528 ) 80093aa: 4293 cmp r3, r2 80093ac: d01d beq.n 80093ea 80093ae: 687b ldr r3, [r7, #4] 80093b0: 681b ldr r3, [r3, #0] 80093b2: 4a5e ldr r2, [pc, #376] @ (800952c ) 80093b4: 4293 cmp r3, r2 80093b6: d018 beq.n 80093ea 80093b8: 687b ldr r3, [r7, #4] 80093ba: 681b ldr r3, [r3, #0] 80093bc: 4a5c ldr r2, [pc, #368] @ (8009530 ) 80093be: 4293 cmp r3, r2 80093c0: d013 beq.n 80093ea 80093c2: 687b ldr r3, [r7, #4] 80093c4: 681b ldr r3, [r3, #0] 80093c6: 4a5b ldr r2, [pc, #364] @ (8009534 ) 80093c8: 4293 cmp r3, r2 80093ca: d00e beq.n 80093ea 80093cc: 687b ldr r3, [r7, #4] 80093ce: 681b ldr r3, [r3, #0] 80093d0: 4a59 ldr r2, [pc, #356] @ (8009538 ) 80093d2: 4293 cmp r3, r2 80093d4: d009 beq.n 80093ea 80093d6: 687b ldr r3, [r7, #4] 80093d8: 681b ldr r3, [r3, #0] 80093da: 4a58 ldr r2, [pc, #352] @ (800953c ) 80093dc: 4293 cmp r3, r2 80093de: d004 beq.n 80093ea 80093e0: 687b ldr r3, [r7, #4] 80093e2: 681b ldr r3, [r3, #0] 80093e4: 4a56 ldr r2, [pc, #344] @ (8009540 ) 80093e6: 4293 cmp r3, r2 80093e8: d108 bne.n 80093fc 80093ea: 687b ldr r3, [r7, #4] 80093ec: 681b ldr r3, [r3, #0] 80093ee: 681a ldr r2, [r3, #0] 80093f0: 687b ldr r3, [r7, #4] 80093f2: 681b ldr r3, [r3, #0] 80093f4: f022 0201 bic.w r2, r2, #1 80093f8: 601a str r2, [r3, #0] 80093fa: e007 b.n 800940c 80093fc: 687b ldr r3, [r7, #4] 80093fe: 681b ldr r3, [r3, #0] 8009400: 681a ldr r2, [r3, #0] 8009402: 687b ldr r3, [r7, #4] 8009404: 681b ldr r3, [r3, #0] 8009406: f022 0201 bic.w r2, r2, #1 800940a: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while(((*enableRegister) & DMA_SxCR_EN) != 0U) 800940c: e013 b.n 8009436 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 800940e: f7fc fcf5 bl 8005dfc 8009412: 4602 mov r2, r0 8009414: 693b ldr r3, [r7, #16] 8009416: 1ad3 subs r3, r2, r3 8009418: 2b05 cmp r3, #5 800941a: d90c bls.n 8009436 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 800941c: 687b ldr r3, [r7, #4] 800941e: 2220 movs r2, #32 8009420: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 8009422: 687b ldr r3, [r7, #4] 8009424: 2203 movs r2, #3 8009426: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800942a: 687b ldr r3, [r7, #4] 800942c: 2200 movs r2, #0 800942e: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8009432: 2301 movs r3, #1 8009434: e12d b.n 8009692 while(((*enableRegister) & DMA_SxCR_EN) != 0U) 8009436: 697b ldr r3, [r7, #20] 8009438: 681b ldr r3, [r3, #0] 800943a: f003 0301 and.w r3, r3, #1 800943e: 2b00 cmp r3, #0 8009440: d1e5 bne.n 800940e } } /* Clear all interrupt flags at correct offset within the register */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8009442: 687b ldr r3, [r7, #4] 8009444: 681b ldr r3, [r3, #0] 8009446: 4a2f ldr r2, [pc, #188] @ (8009504 ) 8009448: 4293 cmp r3, r2 800944a: d04a beq.n 80094e2 800944c: 687b ldr r3, [r7, #4] 800944e: 681b ldr r3, [r3, #0] 8009450: 4a2d ldr r2, [pc, #180] @ (8009508 ) 8009452: 4293 cmp r3, r2 8009454: d045 beq.n 80094e2 8009456: 687b ldr r3, [r7, #4] 8009458: 681b ldr r3, [r3, #0] 800945a: 4a2c ldr r2, [pc, #176] @ (800950c ) 800945c: 4293 cmp r3, r2 800945e: d040 beq.n 80094e2 8009460: 687b ldr r3, [r7, #4] 8009462: 681b ldr r3, [r3, #0] 8009464: 4a2a ldr r2, [pc, #168] @ (8009510 ) 8009466: 4293 cmp r3, r2 8009468: d03b beq.n 80094e2 800946a: 687b ldr r3, [r7, #4] 800946c: 681b ldr r3, [r3, #0] 800946e: 4a29 ldr r2, [pc, #164] @ (8009514 ) 8009470: 4293 cmp r3, r2 8009472: d036 beq.n 80094e2 8009474: 687b ldr r3, [r7, #4] 8009476: 681b ldr r3, [r3, #0] 8009478: 4a27 ldr r2, [pc, #156] @ (8009518 ) 800947a: 4293 cmp r3, r2 800947c: d031 beq.n 80094e2 800947e: 687b ldr r3, [r7, #4] 8009480: 681b ldr r3, [r3, #0] 8009482: 4a26 ldr r2, [pc, #152] @ (800951c ) 8009484: 4293 cmp r3, r2 8009486: d02c beq.n 80094e2 8009488: 687b ldr r3, [r7, #4] 800948a: 681b ldr r3, [r3, #0] 800948c: 4a24 ldr r2, [pc, #144] @ (8009520 ) 800948e: 4293 cmp r3, r2 8009490: d027 beq.n 80094e2 8009492: 687b ldr r3, [r7, #4] 8009494: 681b ldr r3, [r3, #0] 8009496: 4a23 ldr r2, [pc, #140] @ (8009524 ) 8009498: 4293 cmp r3, r2 800949a: d022 beq.n 80094e2 800949c: 687b ldr r3, [r7, #4] 800949e: 681b ldr r3, [r3, #0] 80094a0: 4a21 ldr r2, [pc, #132] @ (8009528 ) 80094a2: 4293 cmp r3, r2 80094a4: d01d beq.n 80094e2 80094a6: 687b ldr r3, [r7, #4] 80094a8: 681b ldr r3, [r3, #0] 80094aa: 4a20 ldr r2, [pc, #128] @ (800952c ) 80094ac: 4293 cmp r3, r2 80094ae: d018 beq.n 80094e2 80094b0: 687b ldr r3, [r7, #4] 80094b2: 681b ldr r3, [r3, #0] 80094b4: 4a1e ldr r2, [pc, #120] @ (8009530 ) 80094b6: 4293 cmp r3, r2 80094b8: d013 beq.n 80094e2 80094ba: 687b ldr r3, [r7, #4] 80094bc: 681b ldr r3, [r3, #0] 80094be: 4a1d ldr r2, [pc, #116] @ (8009534 ) 80094c0: 4293 cmp r3, r2 80094c2: d00e beq.n 80094e2 80094c4: 687b ldr r3, [r7, #4] 80094c6: 681b ldr r3, [r3, #0] 80094c8: 4a1b ldr r2, [pc, #108] @ (8009538 ) 80094ca: 4293 cmp r3, r2 80094cc: d009 beq.n 80094e2 80094ce: 687b ldr r3, [r7, #4] 80094d0: 681b ldr r3, [r3, #0] 80094d2: 4a1a ldr r2, [pc, #104] @ (800953c ) 80094d4: 4293 cmp r3, r2 80094d6: d004 beq.n 80094e2 80094d8: 687b ldr r3, [r7, #4] 80094da: 681b ldr r3, [r3, #0] 80094dc: 4a18 ldr r2, [pc, #96] @ (8009540 ) 80094de: 4293 cmp r3, r2 80094e0: d101 bne.n 80094e6 80094e2: 2301 movs r3, #1 80094e4: e000 b.n 80094e8 80094e6: 2300 movs r3, #0 80094e8: 2b00 cmp r3, #0 80094ea: d02b beq.n 8009544 { regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 80094ec: 687b ldr r3, [r7, #4] 80094ee: 6d9b ldr r3, [r3, #88] @ 0x58 80094f0: 60bb str r3, [r7, #8] regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 80094f2: 687b ldr r3, [r7, #4] 80094f4: 6ddb ldr r3, [r3, #92] @ 0x5c 80094f6: f003 031f and.w r3, r3, #31 80094fa: 223f movs r2, #63 @ 0x3f 80094fc: 409a lsls r2, r3 80094fe: 68bb ldr r3, [r7, #8] 8009500: 609a str r2, [r3, #8] 8009502: e02a b.n 800955a 8009504: 40020010 .word 0x40020010 8009508: 40020028 .word 0x40020028 800950c: 40020040 .word 0x40020040 8009510: 40020058 .word 0x40020058 8009514: 40020070 .word 0x40020070 8009518: 40020088 .word 0x40020088 800951c: 400200a0 .word 0x400200a0 8009520: 400200b8 .word 0x400200b8 8009524: 40020410 .word 0x40020410 8009528: 40020428 .word 0x40020428 800952c: 40020440 .word 0x40020440 8009530: 40020458 .word 0x40020458 8009534: 40020470 .word 0x40020470 8009538: 40020488 .word 0x40020488 800953c: 400204a0 .word 0x400204a0 8009540: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8009544: 687b ldr r3, [r7, #4] 8009546: 6d9b ldr r3, [r3, #88] @ 0x58 8009548: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 800954a: 687b ldr r3, [r7, #4] 800954c: 6ddb ldr r3, [r3, #92] @ 0x5c 800954e: f003 031f and.w r3, r3, #31 8009552: 2201 movs r2, #1 8009554: 409a lsls r2, r3 8009556: 68fb ldr r3, [r7, #12] 8009558: 605a str r2, [r3, #4] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800955a: 687b ldr r3, [r7, #4] 800955c: 681b ldr r3, [r3, #0] 800955e: 4a4f ldr r2, [pc, #316] @ (800969c ) 8009560: 4293 cmp r3, r2 8009562: d072 beq.n 800964a 8009564: 687b ldr r3, [r7, #4] 8009566: 681b ldr r3, [r3, #0] 8009568: 4a4d ldr r2, [pc, #308] @ (80096a0 ) 800956a: 4293 cmp r3, r2 800956c: d06d beq.n 800964a 800956e: 687b ldr r3, [r7, #4] 8009570: 681b ldr r3, [r3, #0] 8009572: 4a4c ldr r2, [pc, #304] @ (80096a4 ) 8009574: 4293 cmp r3, r2 8009576: d068 beq.n 800964a 8009578: 687b ldr r3, [r7, #4] 800957a: 681b ldr r3, [r3, #0] 800957c: 4a4a ldr r2, [pc, #296] @ (80096a8 ) 800957e: 4293 cmp r3, r2 8009580: d063 beq.n 800964a 8009582: 687b ldr r3, [r7, #4] 8009584: 681b ldr r3, [r3, #0] 8009586: 4a49 ldr r2, [pc, #292] @ (80096ac ) 8009588: 4293 cmp r3, r2 800958a: d05e beq.n 800964a 800958c: 687b ldr r3, [r7, #4] 800958e: 681b ldr r3, [r3, #0] 8009590: 4a47 ldr r2, [pc, #284] @ (80096b0 ) 8009592: 4293 cmp r3, r2 8009594: d059 beq.n 800964a 8009596: 687b ldr r3, [r7, #4] 8009598: 681b ldr r3, [r3, #0] 800959a: 4a46 ldr r2, [pc, #280] @ (80096b4 ) 800959c: 4293 cmp r3, r2 800959e: d054 beq.n 800964a 80095a0: 687b ldr r3, [r7, #4] 80095a2: 681b ldr r3, [r3, #0] 80095a4: 4a44 ldr r2, [pc, #272] @ (80096b8 ) 80095a6: 4293 cmp r3, r2 80095a8: d04f beq.n 800964a 80095aa: 687b ldr r3, [r7, #4] 80095ac: 681b ldr r3, [r3, #0] 80095ae: 4a43 ldr r2, [pc, #268] @ (80096bc ) 80095b0: 4293 cmp r3, r2 80095b2: d04a beq.n 800964a 80095b4: 687b ldr r3, [r7, #4] 80095b6: 681b ldr r3, [r3, #0] 80095b8: 4a41 ldr r2, [pc, #260] @ (80096c0 ) 80095ba: 4293 cmp r3, r2 80095bc: d045 beq.n 800964a 80095be: 687b ldr r3, [r7, #4] 80095c0: 681b ldr r3, [r3, #0] 80095c2: 4a40 ldr r2, [pc, #256] @ (80096c4 ) 80095c4: 4293 cmp r3, r2 80095c6: d040 beq.n 800964a 80095c8: 687b ldr r3, [r7, #4] 80095ca: 681b ldr r3, [r3, #0] 80095cc: 4a3e ldr r2, [pc, #248] @ (80096c8 ) 80095ce: 4293 cmp r3, r2 80095d0: d03b beq.n 800964a 80095d2: 687b ldr r3, [r7, #4] 80095d4: 681b ldr r3, [r3, #0] 80095d6: 4a3d ldr r2, [pc, #244] @ (80096cc ) 80095d8: 4293 cmp r3, r2 80095da: d036 beq.n 800964a 80095dc: 687b ldr r3, [r7, #4] 80095de: 681b ldr r3, [r3, #0] 80095e0: 4a3b ldr r2, [pc, #236] @ (80096d0 ) 80095e2: 4293 cmp r3, r2 80095e4: d031 beq.n 800964a 80095e6: 687b ldr r3, [r7, #4] 80095e8: 681b ldr r3, [r3, #0] 80095ea: 4a3a ldr r2, [pc, #232] @ (80096d4 ) 80095ec: 4293 cmp r3, r2 80095ee: d02c beq.n 800964a 80095f0: 687b ldr r3, [r7, #4] 80095f2: 681b ldr r3, [r3, #0] 80095f4: 4a38 ldr r2, [pc, #224] @ (80096d8 ) 80095f6: 4293 cmp r3, r2 80095f8: d027 beq.n 800964a 80095fa: 687b ldr r3, [r7, #4] 80095fc: 681b ldr r3, [r3, #0] 80095fe: 4a37 ldr r2, [pc, #220] @ (80096dc ) 8009600: 4293 cmp r3, r2 8009602: d022 beq.n 800964a 8009604: 687b ldr r3, [r7, #4] 8009606: 681b ldr r3, [r3, #0] 8009608: 4a35 ldr r2, [pc, #212] @ (80096e0 ) 800960a: 4293 cmp r3, r2 800960c: d01d beq.n 800964a 800960e: 687b ldr r3, [r7, #4] 8009610: 681b ldr r3, [r3, #0] 8009612: 4a34 ldr r2, [pc, #208] @ (80096e4 ) 8009614: 4293 cmp r3, r2 8009616: d018 beq.n 800964a 8009618: 687b ldr r3, [r7, #4] 800961a: 681b ldr r3, [r3, #0] 800961c: 4a32 ldr r2, [pc, #200] @ (80096e8 ) 800961e: 4293 cmp r3, r2 8009620: d013 beq.n 800964a 8009622: 687b ldr r3, [r7, #4] 8009624: 681b ldr r3, [r3, #0] 8009626: 4a31 ldr r2, [pc, #196] @ (80096ec ) 8009628: 4293 cmp r3, r2 800962a: d00e beq.n 800964a 800962c: 687b ldr r3, [r7, #4] 800962e: 681b ldr r3, [r3, #0] 8009630: 4a2f ldr r2, [pc, #188] @ (80096f0 ) 8009632: 4293 cmp r3, r2 8009634: d009 beq.n 800964a 8009636: 687b ldr r3, [r7, #4] 8009638: 681b ldr r3, [r3, #0] 800963a: 4a2e ldr r2, [pc, #184] @ (80096f4 ) 800963c: 4293 cmp r3, r2 800963e: d004 beq.n 800964a 8009640: 687b ldr r3, [r7, #4] 8009642: 681b ldr r3, [r3, #0] 8009644: 4a2c ldr r2, [pc, #176] @ (80096f8 ) 8009646: 4293 cmp r3, r2 8009648: d101 bne.n 800964e 800964a: 2301 movs r3, #1 800964c: e000 b.n 8009650 800964e: 2300 movs r3, #0 8009650: 2b00 cmp r3, #0 8009652: d015 beq.n 8009680 { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8009654: 687b ldr r3, [r7, #4] 8009656: 6e5b ldr r3, [r3, #100] @ 0x64 8009658: 687a ldr r2, [r7, #4] 800965a: 6e92 ldr r2, [r2, #104] @ 0x68 800965c: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 800965e: 687b ldr r3, [r7, #4] 8009660: 6edb ldr r3, [r3, #108] @ 0x6c 8009662: 2b00 cmp r3, #0 8009664: d00c beq.n 8009680 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8009666: 687b ldr r3, [r7, #4] 8009668: 6edb ldr r3, [r3, #108] @ 0x6c 800966a: 681a ldr r2, [r3, #0] 800966c: 687b ldr r3, [r7, #4] 800966e: 6edb ldr r3, [r3, #108] @ 0x6c 8009670: f422 7280 bic.w r2, r2, #256 @ 0x100 8009674: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8009676: 687b ldr r3, [r7, #4] 8009678: 6f1b ldr r3, [r3, #112] @ 0x70 800967a: 687a ldr r2, [r7, #4] 800967c: 6f52 ldr r2, [r2, #116] @ 0x74 800967e: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8009680: 687b ldr r3, [r7, #4] 8009682: 2201 movs r2, #1 8009684: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009688: 687b ldr r3, [r7, #4] 800968a: 2200 movs r2, #0 800968c: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 8009690: 2300 movs r3, #0 } 8009692: 4618 mov r0, r3 8009694: 3718 adds r7, #24 8009696: 46bd mov sp, r7 8009698: bd80 pop {r7, pc} 800969a: bf00 nop 800969c: 40020010 .word 0x40020010 80096a0: 40020028 .word 0x40020028 80096a4: 40020040 .word 0x40020040 80096a8: 40020058 .word 0x40020058 80096ac: 40020070 .word 0x40020070 80096b0: 40020088 .word 0x40020088 80096b4: 400200a0 .word 0x400200a0 80096b8: 400200b8 .word 0x400200b8 80096bc: 40020410 .word 0x40020410 80096c0: 40020428 .word 0x40020428 80096c4: 40020440 .word 0x40020440 80096c8: 40020458 .word 0x40020458 80096cc: 40020470 .word 0x40020470 80096d0: 40020488 .word 0x40020488 80096d4: 400204a0 .word 0x400204a0 80096d8: 400204b8 .word 0x400204b8 80096dc: 58025408 .word 0x58025408 80096e0: 5802541c .word 0x5802541c 80096e4: 58025430 .word 0x58025430 80096e8: 58025444 .word 0x58025444 80096ec: 58025458 .word 0x58025458 80096f0: 5802546c .word 0x5802546c 80096f4: 58025480 .word 0x58025480 80096f8: 58025494 .word 0x58025494 080096fc : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 80096fc: b580 push {r7, lr} 80096fe: b084 sub sp, #16 8009700: af00 add r7, sp, #0 8009702: 6078 str r0, [r7, #4] BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 8009704: 687b ldr r3, [r7, #4] 8009706: 2b00 cmp r3, #0 8009708: d101 bne.n 800970e { return HAL_ERROR; 800970a: 2301 movs r3, #1 800970c: e237 b.n 8009b7e } if(hdma->State != HAL_DMA_STATE_BUSY) 800970e: 687b ldr r3, [r7, #4] 8009710: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8009714: b2db uxtb r3, r3 8009716: 2b02 cmp r3, #2 8009718: d004 beq.n 8009724 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800971a: 687b ldr r3, [r7, #4] 800971c: 2280 movs r2, #128 @ 0x80 800971e: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 8009720: 2301 movs r3, #1 8009722: e22c b.n 8009b7e } else { if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8009724: 687b ldr r3, [r7, #4] 8009726: 681b ldr r3, [r3, #0] 8009728: 4a5c ldr r2, [pc, #368] @ (800989c ) 800972a: 4293 cmp r3, r2 800972c: d04a beq.n 80097c4 800972e: 687b ldr r3, [r7, #4] 8009730: 681b ldr r3, [r3, #0] 8009732: 4a5b ldr r2, [pc, #364] @ (80098a0 ) 8009734: 4293 cmp r3, r2 8009736: d045 beq.n 80097c4 8009738: 687b ldr r3, [r7, #4] 800973a: 681b ldr r3, [r3, #0] 800973c: 4a59 ldr r2, [pc, #356] @ (80098a4 ) 800973e: 4293 cmp r3, r2 8009740: d040 beq.n 80097c4 8009742: 687b ldr r3, [r7, #4] 8009744: 681b ldr r3, [r3, #0] 8009746: 4a58 ldr r2, [pc, #352] @ (80098a8 ) 8009748: 4293 cmp r3, r2 800974a: d03b beq.n 80097c4 800974c: 687b ldr r3, [r7, #4] 800974e: 681b ldr r3, [r3, #0] 8009750: 4a56 ldr r2, [pc, #344] @ (80098ac ) 8009752: 4293 cmp r3, r2 8009754: d036 beq.n 80097c4 8009756: 687b ldr r3, [r7, #4] 8009758: 681b ldr r3, [r3, #0] 800975a: 4a55 ldr r2, [pc, #340] @ (80098b0 ) 800975c: 4293 cmp r3, r2 800975e: d031 beq.n 80097c4 8009760: 687b ldr r3, [r7, #4] 8009762: 681b ldr r3, [r3, #0] 8009764: 4a53 ldr r2, [pc, #332] @ (80098b4 ) 8009766: 4293 cmp r3, r2 8009768: d02c beq.n 80097c4 800976a: 687b ldr r3, [r7, #4] 800976c: 681b ldr r3, [r3, #0] 800976e: 4a52 ldr r2, [pc, #328] @ (80098b8 ) 8009770: 4293 cmp r3, r2 8009772: d027 beq.n 80097c4 8009774: 687b ldr r3, [r7, #4] 8009776: 681b ldr r3, [r3, #0] 8009778: 4a50 ldr r2, [pc, #320] @ (80098bc ) 800977a: 4293 cmp r3, r2 800977c: d022 beq.n 80097c4 800977e: 687b ldr r3, [r7, #4] 8009780: 681b ldr r3, [r3, #0] 8009782: 4a4f ldr r2, [pc, #316] @ (80098c0 ) 8009784: 4293 cmp r3, r2 8009786: d01d beq.n 80097c4 8009788: 687b ldr r3, [r7, #4] 800978a: 681b ldr r3, [r3, #0] 800978c: 4a4d ldr r2, [pc, #308] @ (80098c4 ) 800978e: 4293 cmp r3, r2 8009790: d018 beq.n 80097c4 8009792: 687b ldr r3, [r7, #4] 8009794: 681b ldr r3, [r3, #0] 8009796: 4a4c ldr r2, [pc, #304] @ (80098c8 ) 8009798: 4293 cmp r3, r2 800979a: d013 beq.n 80097c4 800979c: 687b ldr r3, [r7, #4] 800979e: 681b ldr r3, [r3, #0] 80097a0: 4a4a ldr r2, [pc, #296] @ (80098cc ) 80097a2: 4293 cmp r3, r2 80097a4: d00e beq.n 80097c4 80097a6: 687b ldr r3, [r7, #4] 80097a8: 681b ldr r3, [r3, #0] 80097aa: 4a49 ldr r2, [pc, #292] @ (80098d0 ) 80097ac: 4293 cmp r3, r2 80097ae: d009 beq.n 80097c4 80097b0: 687b ldr r3, [r7, #4] 80097b2: 681b ldr r3, [r3, #0] 80097b4: 4a47 ldr r2, [pc, #284] @ (80098d4 ) 80097b6: 4293 cmp r3, r2 80097b8: d004 beq.n 80097c4 80097ba: 687b ldr r3, [r7, #4] 80097bc: 681b ldr r3, [r3, #0] 80097be: 4a46 ldr r2, [pc, #280] @ (80098d8 ) 80097c0: 4293 cmp r3, r2 80097c2: d101 bne.n 80097c8 80097c4: 2301 movs r3, #1 80097c6: e000 b.n 80097ca 80097c8: 2300 movs r3, #0 80097ca: 2b00 cmp r3, #0 80097cc: f000 8086 beq.w 80098dc { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 80097d0: 687b ldr r3, [r7, #4] 80097d2: 2204 movs r2, #4 80097d4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80097d8: 687b ldr r3, [r7, #4] 80097da: 681b ldr r3, [r3, #0] 80097dc: 4a2f ldr r2, [pc, #188] @ (800989c ) 80097de: 4293 cmp r3, r2 80097e0: d04a beq.n 8009878 80097e2: 687b ldr r3, [r7, #4] 80097e4: 681b ldr r3, [r3, #0] 80097e6: 4a2e ldr r2, [pc, #184] @ (80098a0 ) 80097e8: 4293 cmp r3, r2 80097ea: d045 beq.n 8009878 80097ec: 687b ldr r3, [r7, #4] 80097ee: 681b ldr r3, [r3, #0] 80097f0: 4a2c ldr r2, [pc, #176] @ (80098a4 ) 80097f2: 4293 cmp r3, r2 80097f4: d040 beq.n 8009878 80097f6: 687b ldr r3, [r7, #4] 80097f8: 681b ldr r3, [r3, #0] 80097fa: 4a2b ldr r2, [pc, #172] @ (80098a8 ) 80097fc: 4293 cmp r3, r2 80097fe: d03b beq.n 8009878 8009800: 687b ldr r3, [r7, #4] 8009802: 681b ldr r3, [r3, #0] 8009804: 4a29 ldr r2, [pc, #164] @ (80098ac ) 8009806: 4293 cmp r3, r2 8009808: d036 beq.n 8009878 800980a: 687b ldr r3, [r7, #4] 800980c: 681b ldr r3, [r3, #0] 800980e: 4a28 ldr r2, [pc, #160] @ (80098b0 ) 8009810: 4293 cmp r3, r2 8009812: d031 beq.n 8009878 8009814: 687b ldr r3, [r7, #4] 8009816: 681b ldr r3, [r3, #0] 8009818: 4a26 ldr r2, [pc, #152] @ (80098b4 ) 800981a: 4293 cmp r3, r2 800981c: d02c beq.n 8009878 800981e: 687b ldr r3, [r7, #4] 8009820: 681b ldr r3, [r3, #0] 8009822: 4a25 ldr r2, [pc, #148] @ (80098b8 ) 8009824: 4293 cmp r3, r2 8009826: d027 beq.n 8009878 8009828: 687b ldr r3, [r7, #4] 800982a: 681b ldr r3, [r3, #0] 800982c: 4a23 ldr r2, [pc, #140] @ (80098bc ) 800982e: 4293 cmp r3, r2 8009830: d022 beq.n 8009878 8009832: 687b ldr r3, [r7, #4] 8009834: 681b ldr r3, [r3, #0] 8009836: 4a22 ldr r2, [pc, #136] @ (80098c0 ) 8009838: 4293 cmp r3, r2 800983a: d01d beq.n 8009878 800983c: 687b ldr r3, [r7, #4] 800983e: 681b ldr r3, [r3, #0] 8009840: 4a20 ldr r2, [pc, #128] @ (80098c4 ) 8009842: 4293 cmp r3, r2 8009844: d018 beq.n 8009878 8009846: 687b ldr r3, [r7, #4] 8009848: 681b ldr r3, [r3, #0] 800984a: 4a1f ldr r2, [pc, #124] @ (80098c8 ) 800984c: 4293 cmp r3, r2 800984e: d013 beq.n 8009878 8009850: 687b ldr r3, [r7, #4] 8009852: 681b ldr r3, [r3, #0] 8009854: 4a1d ldr r2, [pc, #116] @ (80098cc ) 8009856: 4293 cmp r3, r2 8009858: d00e beq.n 8009878 800985a: 687b ldr r3, [r7, #4] 800985c: 681b ldr r3, [r3, #0] 800985e: 4a1c ldr r2, [pc, #112] @ (80098d0 ) 8009860: 4293 cmp r3, r2 8009862: d009 beq.n 8009878 8009864: 687b ldr r3, [r7, #4] 8009866: 681b ldr r3, [r3, #0] 8009868: 4a1a ldr r2, [pc, #104] @ (80098d4 ) 800986a: 4293 cmp r3, r2 800986c: d004 beq.n 8009878 800986e: 687b ldr r3, [r7, #4] 8009870: 681b ldr r3, [r3, #0] 8009872: 4a19 ldr r2, [pc, #100] @ (80098d8 ) 8009874: 4293 cmp r3, r2 8009876: d108 bne.n 800988a 8009878: 687b ldr r3, [r7, #4] 800987a: 681b ldr r3, [r3, #0] 800987c: 681a ldr r2, [r3, #0] 800987e: 687b ldr r3, [r7, #4] 8009880: 681b ldr r3, [r3, #0] 8009882: f022 0201 bic.w r2, r2, #1 8009886: 601a str r2, [r3, #0] 8009888: e178 b.n 8009b7c 800988a: 687b ldr r3, [r7, #4] 800988c: 681b ldr r3, [r3, #0] 800988e: 681a ldr r2, [r3, #0] 8009890: 687b ldr r3, [r7, #4] 8009892: 681b ldr r3, [r3, #0] 8009894: f022 0201 bic.w r2, r2, #1 8009898: 601a str r2, [r3, #0] 800989a: e16f b.n 8009b7c 800989c: 40020010 .word 0x40020010 80098a0: 40020028 .word 0x40020028 80098a4: 40020040 .word 0x40020040 80098a8: 40020058 .word 0x40020058 80098ac: 40020070 .word 0x40020070 80098b0: 40020088 .word 0x40020088 80098b4: 400200a0 .word 0x400200a0 80098b8: 400200b8 .word 0x400200b8 80098bc: 40020410 .word 0x40020410 80098c0: 40020428 .word 0x40020428 80098c4: 40020440 .word 0x40020440 80098c8: 40020458 .word 0x40020458 80098cc: 40020470 .word 0x40020470 80098d0: 40020488 .word 0x40020488 80098d4: 400204a0 .word 0x400204a0 80098d8: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 80098dc: 687b ldr r3, [r7, #4] 80098de: 681b ldr r3, [r3, #0] 80098e0: 681a ldr r2, [r3, #0] 80098e2: 687b ldr r3, [r7, #4] 80098e4: 681b ldr r3, [r3, #0] 80098e6: f022 020e bic.w r2, r2, #14 80098ea: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 80098ec: 687b ldr r3, [r7, #4] 80098ee: 681b ldr r3, [r3, #0] 80098f0: 4a6c ldr r2, [pc, #432] @ (8009aa4 ) 80098f2: 4293 cmp r3, r2 80098f4: d04a beq.n 800998c 80098f6: 687b ldr r3, [r7, #4] 80098f8: 681b ldr r3, [r3, #0] 80098fa: 4a6b ldr r2, [pc, #428] @ (8009aa8 ) 80098fc: 4293 cmp r3, r2 80098fe: d045 beq.n 800998c 8009900: 687b ldr r3, [r7, #4] 8009902: 681b ldr r3, [r3, #0] 8009904: 4a69 ldr r2, [pc, #420] @ (8009aac ) 8009906: 4293 cmp r3, r2 8009908: d040 beq.n 800998c 800990a: 687b ldr r3, [r7, #4] 800990c: 681b ldr r3, [r3, #0] 800990e: 4a68 ldr r2, [pc, #416] @ (8009ab0 ) 8009910: 4293 cmp r3, r2 8009912: d03b beq.n 800998c 8009914: 687b ldr r3, [r7, #4] 8009916: 681b ldr r3, [r3, #0] 8009918: 4a66 ldr r2, [pc, #408] @ (8009ab4 ) 800991a: 4293 cmp r3, r2 800991c: d036 beq.n 800998c 800991e: 687b ldr r3, [r7, #4] 8009920: 681b ldr r3, [r3, #0] 8009922: 4a65 ldr r2, [pc, #404] @ (8009ab8 ) 8009924: 4293 cmp r3, r2 8009926: d031 beq.n 800998c 8009928: 687b ldr r3, [r7, #4] 800992a: 681b ldr r3, [r3, #0] 800992c: 4a63 ldr r2, [pc, #396] @ (8009abc ) 800992e: 4293 cmp r3, r2 8009930: d02c beq.n 800998c 8009932: 687b ldr r3, [r7, #4] 8009934: 681b ldr r3, [r3, #0] 8009936: 4a62 ldr r2, [pc, #392] @ (8009ac0 ) 8009938: 4293 cmp r3, r2 800993a: d027 beq.n 800998c 800993c: 687b ldr r3, [r7, #4] 800993e: 681b ldr r3, [r3, #0] 8009940: 4a60 ldr r2, [pc, #384] @ (8009ac4 ) 8009942: 4293 cmp r3, r2 8009944: d022 beq.n 800998c 8009946: 687b ldr r3, [r7, #4] 8009948: 681b ldr r3, [r3, #0] 800994a: 4a5f ldr r2, [pc, #380] @ (8009ac8 ) 800994c: 4293 cmp r3, r2 800994e: d01d beq.n 800998c 8009950: 687b ldr r3, [r7, #4] 8009952: 681b ldr r3, [r3, #0] 8009954: 4a5d ldr r2, [pc, #372] @ (8009acc ) 8009956: 4293 cmp r3, r2 8009958: d018 beq.n 800998c 800995a: 687b ldr r3, [r7, #4] 800995c: 681b ldr r3, [r3, #0] 800995e: 4a5c ldr r2, [pc, #368] @ (8009ad0 ) 8009960: 4293 cmp r3, r2 8009962: d013 beq.n 800998c 8009964: 687b ldr r3, [r7, #4] 8009966: 681b ldr r3, [r3, #0] 8009968: 4a5a ldr r2, [pc, #360] @ (8009ad4 ) 800996a: 4293 cmp r3, r2 800996c: d00e beq.n 800998c 800996e: 687b ldr r3, [r7, #4] 8009970: 681b ldr r3, [r3, #0] 8009972: 4a59 ldr r2, [pc, #356] @ (8009ad8 ) 8009974: 4293 cmp r3, r2 8009976: d009 beq.n 800998c 8009978: 687b ldr r3, [r7, #4] 800997a: 681b ldr r3, [r3, #0] 800997c: 4a57 ldr r2, [pc, #348] @ (8009adc ) 800997e: 4293 cmp r3, r2 8009980: d004 beq.n 800998c 8009982: 687b ldr r3, [r7, #4] 8009984: 681b ldr r3, [r3, #0] 8009986: 4a56 ldr r2, [pc, #344] @ (8009ae0 ) 8009988: 4293 cmp r3, r2 800998a: d108 bne.n 800999e 800998c: 687b ldr r3, [r7, #4] 800998e: 681b ldr r3, [r3, #0] 8009990: 681a ldr r2, [r3, #0] 8009992: 687b ldr r3, [r7, #4] 8009994: 681b ldr r3, [r3, #0] 8009996: f022 0201 bic.w r2, r2, #1 800999a: 601a str r2, [r3, #0] 800999c: e007 b.n 80099ae 800999e: 687b ldr r3, [r7, #4] 80099a0: 681b ldr r3, [r3, #0] 80099a2: 681a ldr r2, [r3, #0] 80099a4: 687b ldr r3, [r7, #4] 80099a6: 681b ldr r3, [r3, #0] 80099a8: f022 0201 bic.w r2, r2, #1 80099ac: 601a str r2, [r3, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80099ae: 687b ldr r3, [r7, #4] 80099b0: 681b ldr r3, [r3, #0] 80099b2: 4a3c ldr r2, [pc, #240] @ (8009aa4 ) 80099b4: 4293 cmp r3, r2 80099b6: d072 beq.n 8009a9e 80099b8: 687b ldr r3, [r7, #4] 80099ba: 681b ldr r3, [r3, #0] 80099bc: 4a3a ldr r2, [pc, #232] @ (8009aa8 ) 80099be: 4293 cmp r3, r2 80099c0: d06d beq.n 8009a9e 80099c2: 687b ldr r3, [r7, #4] 80099c4: 681b ldr r3, [r3, #0] 80099c6: 4a39 ldr r2, [pc, #228] @ (8009aac ) 80099c8: 4293 cmp r3, r2 80099ca: d068 beq.n 8009a9e 80099cc: 687b ldr r3, [r7, #4] 80099ce: 681b ldr r3, [r3, #0] 80099d0: 4a37 ldr r2, [pc, #220] @ (8009ab0 ) 80099d2: 4293 cmp r3, r2 80099d4: d063 beq.n 8009a9e 80099d6: 687b ldr r3, [r7, #4] 80099d8: 681b ldr r3, [r3, #0] 80099da: 4a36 ldr r2, [pc, #216] @ (8009ab4 ) 80099dc: 4293 cmp r3, r2 80099de: d05e beq.n 8009a9e 80099e0: 687b ldr r3, [r7, #4] 80099e2: 681b ldr r3, [r3, #0] 80099e4: 4a34 ldr r2, [pc, #208] @ (8009ab8 ) 80099e6: 4293 cmp r3, r2 80099e8: d059 beq.n 8009a9e 80099ea: 687b ldr r3, [r7, #4] 80099ec: 681b ldr r3, [r3, #0] 80099ee: 4a33 ldr r2, [pc, #204] @ (8009abc ) 80099f0: 4293 cmp r3, r2 80099f2: d054 beq.n 8009a9e 80099f4: 687b ldr r3, [r7, #4] 80099f6: 681b ldr r3, [r3, #0] 80099f8: 4a31 ldr r2, [pc, #196] @ (8009ac0 ) 80099fa: 4293 cmp r3, r2 80099fc: d04f beq.n 8009a9e 80099fe: 687b ldr r3, [r7, #4] 8009a00: 681b ldr r3, [r3, #0] 8009a02: 4a30 ldr r2, [pc, #192] @ (8009ac4 ) 8009a04: 4293 cmp r3, r2 8009a06: d04a beq.n 8009a9e 8009a08: 687b ldr r3, [r7, #4] 8009a0a: 681b ldr r3, [r3, #0] 8009a0c: 4a2e ldr r2, [pc, #184] @ (8009ac8 ) 8009a0e: 4293 cmp r3, r2 8009a10: d045 beq.n 8009a9e 8009a12: 687b ldr r3, [r7, #4] 8009a14: 681b ldr r3, [r3, #0] 8009a16: 4a2d ldr r2, [pc, #180] @ (8009acc ) 8009a18: 4293 cmp r3, r2 8009a1a: d040 beq.n 8009a9e 8009a1c: 687b ldr r3, [r7, #4] 8009a1e: 681b ldr r3, [r3, #0] 8009a20: 4a2b ldr r2, [pc, #172] @ (8009ad0 ) 8009a22: 4293 cmp r3, r2 8009a24: d03b beq.n 8009a9e 8009a26: 687b ldr r3, [r7, #4] 8009a28: 681b ldr r3, [r3, #0] 8009a2a: 4a2a ldr r2, [pc, #168] @ (8009ad4 ) 8009a2c: 4293 cmp r3, r2 8009a2e: d036 beq.n 8009a9e 8009a30: 687b ldr r3, [r7, #4] 8009a32: 681b ldr r3, [r3, #0] 8009a34: 4a28 ldr r2, [pc, #160] @ (8009ad8 ) 8009a36: 4293 cmp r3, r2 8009a38: d031 beq.n 8009a9e 8009a3a: 687b ldr r3, [r7, #4] 8009a3c: 681b ldr r3, [r3, #0] 8009a3e: 4a27 ldr r2, [pc, #156] @ (8009adc ) 8009a40: 4293 cmp r3, r2 8009a42: d02c beq.n 8009a9e 8009a44: 687b ldr r3, [r7, #4] 8009a46: 681b ldr r3, [r3, #0] 8009a48: 4a25 ldr r2, [pc, #148] @ (8009ae0 ) 8009a4a: 4293 cmp r3, r2 8009a4c: d027 beq.n 8009a9e 8009a4e: 687b ldr r3, [r7, #4] 8009a50: 681b ldr r3, [r3, #0] 8009a52: 4a24 ldr r2, [pc, #144] @ (8009ae4 ) 8009a54: 4293 cmp r3, r2 8009a56: d022 beq.n 8009a9e 8009a58: 687b ldr r3, [r7, #4] 8009a5a: 681b ldr r3, [r3, #0] 8009a5c: 4a22 ldr r2, [pc, #136] @ (8009ae8 ) 8009a5e: 4293 cmp r3, r2 8009a60: d01d beq.n 8009a9e 8009a62: 687b ldr r3, [r7, #4] 8009a64: 681b ldr r3, [r3, #0] 8009a66: 4a21 ldr r2, [pc, #132] @ (8009aec ) 8009a68: 4293 cmp r3, r2 8009a6a: d018 beq.n 8009a9e 8009a6c: 687b ldr r3, [r7, #4] 8009a6e: 681b ldr r3, [r3, #0] 8009a70: 4a1f ldr r2, [pc, #124] @ (8009af0 ) 8009a72: 4293 cmp r3, r2 8009a74: d013 beq.n 8009a9e 8009a76: 687b ldr r3, [r7, #4] 8009a78: 681b ldr r3, [r3, #0] 8009a7a: 4a1e ldr r2, [pc, #120] @ (8009af4 ) 8009a7c: 4293 cmp r3, r2 8009a7e: d00e beq.n 8009a9e 8009a80: 687b ldr r3, [r7, #4] 8009a82: 681b ldr r3, [r3, #0] 8009a84: 4a1c ldr r2, [pc, #112] @ (8009af8 ) 8009a86: 4293 cmp r3, r2 8009a88: d009 beq.n 8009a9e 8009a8a: 687b ldr r3, [r7, #4] 8009a8c: 681b ldr r3, [r3, #0] 8009a8e: 4a1b ldr r2, [pc, #108] @ (8009afc ) 8009a90: 4293 cmp r3, r2 8009a92: d004 beq.n 8009a9e 8009a94: 687b ldr r3, [r7, #4] 8009a96: 681b ldr r3, [r3, #0] 8009a98: 4a19 ldr r2, [pc, #100] @ (8009b00 ) 8009a9a: 4293 cmp r3, r2 8009a9c: d132 bne.n 8009b04 8009a9e: 2301 movs r3, #1 8009aa0: e031 b.n 8009b06 8009aa2: bf00 nop 8009aa4: 40020010 .word 0x40020010 8009aa8: 40020028 .word 0x40020028 8009aac: 40020040 .word 0x40020040 8009ab0: 40020058 .word 0x40020058 8009ab4: 40020070 .word 0x40020070 8009ab8: 40020088 .word 0x40020088 8009abc: 400200a0 .word 0x400200a0 8009ac0: 400200b8 .word 0x400200b8 8009ac4: 40020410 .word 0x40020410 8009ac8: 40020428 .word 0x40020428 8009acc: 40020440 .word 0x40020440 8009ad0: 40020458 .word 0x40020458 8009ad4: 40020470 .word 0x40020470 8009ad8: 40020488 .word 0x40020488 8009adc: 400204a0 .word 0x400204a0 8009ae0: 400204b8 .word 0x400204b8 8009ae4: 58025408 .word 0x58025408 8009ae8: 5802541c .word 0x5802541c 8009aec: 58025430 .word 0x58025430 8009af0: 58025444 .word 0x58025444 8009af4: 58025458 .word 0x58025458 8009af8: 5802546c .word 0x5802546c 8009afc: 58025480 .word 0x58025480 8009b00: 58025494 .word 0x58025494 8009b04: 2300 movs r3, #0 8009b06: 2b00 cmp r3, #0 8009b08: d028 beq.n 8009b5c { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8009b0a: 687b ldr r3, [r7, #4] 8009b0c: 6e1b ldr r3, [r3, #96] @ 0x60 8009b0e: 681a ldr r2, [r3, #0] 8009b10: 687b ldr r3, [r7, #4] 8009b12: 6e1b ldr r3, [r3, #96] @ 0x60 8009b14: f422 7280 bic.w r2, r2, #256 @ 0x100 8009b18: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8009b1a: 687b ldr r3, [r7, #4] 8009b1c: 6d9b ldr r3, [r3, #88] @ 0x58 8009b1e: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8009b20: 687b ldr r3, [r7, #4] 8009b22: 6ddb ldr r3, [r3, #92] @ 0x5c 8009b24: f003 031f and.w r3, r3, #31 8009b28: 2201 movs r2, #1 8009b2a: 409a lsls r2, r3 8009b2c: 68fb ldr r3, [r7, #12] 8009b2e: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8009b30: 687b ldr r3, [r7, #4] 8009b32: 6e5b ldr r3, [r3, #100] @ 0x64 8009b34: 687a ldr r2, [r7, #4] 8009b36: 6e92 ldr r2, [r2, #104] @ 0x68 8009b38: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 8009b3a: 687b ldr r3, [r7, #4] 8009b3c: 6edb ldr r3, [r3, #108] @ 0x6c 8009b3e: 2b00 cmp r3, #0 8009b40: d00c beq.n 8009b5c { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8009b42: 687b ldr r3, [r7, #4] 8009b44: 6edb ldr r3, [r3, #108] @ 0x6c 8009b46: 681a ldr r2, [r3, #0] 8009b48: 687b ldr r3, [r7, #4] 8009b4a: 6edb ldr r3, [r3, #108] @ 0x6c 8009b4c: f422 7280 bic.w r2, r2, #256 @ 0x100 8009b50: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8009b52: 687b ldr r3, [r7, #4] 8009b54: 6f1b ldr r3, [r3, #112] @ 0x70 8009b56: 687a ldr r2, [r7, #4] 8009b58: 6f52 ldr r2, [r2, #116] @ 0x74 8009b5a: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8009b5c: 687b ldr r3, [r7, #4] 8009b5e: 2201 movs r2, #1 8009b60: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009b64: 687b ldr r3, [r7, #4] 8009b66: 2200 movs r2, #0 8009b68: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8009b6c: 687b ldr r3, [r7, #4] 8009b6e: 6d1b ldr r3, [r3, #80] @ 0x50 8009b70: 2b00 cmp r3, #0 8009b72: d003 beq.n 8009b7c { hdma->XferAbortCallback(hdma); 8009b74: 687b ldr r3, [r7, #4] 8009b76: 6d1b ldr r3, [r3, #80] @ 0x50 8009b78: 6878 ldr r0, [r7, #4] 8009b7a: 4798 blx r3 } } } return HAL_OK; 8009b7c: 2300 movs r3, #0 } 8009b7e: 4618 mov r0, r3 8009b80: 3710 adds r7, #16 8009b82: 46bd mov sp, r7 8009b84: bd80 pop {r7, pc} 8009b86: bf00 nop 08009b88 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8009b88: b580 push {r7, lr} 8009b8a: b08a sub sp, #40 @ 0x28 8009b8c: af00 add r7, sp, #0 8009b8e: 6078 str r0, [r7, #4] uint32_t tmpisr_dma, tmpisr_bdma; uint32_t ccr_reg; __IO uint32_t count = 0U; 8009b90: 2300 movs r3, #0 8009b92: 60fb str r3, [r7, #12] uint32_t timeout = SystemCoreClock / 9600U; 8009b94: 4b67 ldr r3, [pc, #412] @ (8009d34 ) 8009b96: 681b ldr r3, [r3, #0] 8009b98: 4a67 ldr r2, [pc, #412] @ (8009d38 ) 8009b9a: fba2 2303 umull r2, r3, r2, r3 8009b9e: 0a9b lsrs r3, r3, #10 8009ba0: 627b str r3, [r7, #36] @ 0x24 /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8009ba2: 687b ldr r3, [r7, #4] 8009ba4: 6d9b ldr r3, [r3, #88] @ 0x58 8009ba6: 623b str r3, [r7, #32] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8009ba8: 687b ldr r3, [r7, #4] 8009baa: 6d9b ldr r3, [r3, #88] @ 0x58 8009bac: 61fb str r3, [r7, #28] tmpisr_dma = regs_dma->ISR; 8009bae: 6a3b ldr r3, [r7, #32] 8009bb0: 681b ldr r3, [r3, #0] 8009bb2: 61bb str r3, [r7, #24] tmpisr_bdma = regs_bdma->ISR; 8009bb4: 69fb ldr r3, [r7, #28] 8009bb6: 681b ldr r3, [r3, #0] 8009bb8: 617b str r3, [r7, #20] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8009bba: 687b ldr r3, [r7, #4] 8009bbc: 681b ldr r3, [r3, #0] 8009bbe: 4a5f ldr r2, [pc, #380] @ (8009d3c ) 8009bc0: 4293 cmp r3, r2 8009bc2: d04a beq.n 8009c5a 8009bc4: 687b ldr r3, [r7, #4] 8009bc6: 681b ldr r3, [r3, #0] 8009bc8: 4a5d ldr r2, [pc, #372] @ (8009d40 ) 8009bca: 4293 cmp r3, r2 8009bcc: d045 beq.n 8009c5a 8009bce: 687b ldr r3, [r7, #4] 8009bd0: 681b ldr r3, [r3, #0] 8009bd2: 4a5c ldr r2, [pc, #368] @ (8009d44 ) 8009bd4: 4293 cmp r3, r2 8009bd6: d040 beq.n 8009c5a 8009bd8: 687b ldr r3, [r7, #4] 8009bda: 681b ldr r3, [r3, #0] 8009bdc: 4a5a ldr r2, [pc, #360] @ (8009d48 ) 8009bde: 4293 cmp r3, r2 8009be0: d03b beq.n 8009c5a 8009be2: 687b ldr r3, [r7, #4] 8009be4: 681b ldr r3, [r3, #0] 8009be6: 4a59 ldr r2, [pc, #356] @ (8009d4c ) 8009be8: 4293 cmp r3, r2 8009bea: d036 beq.n 8009c5a 8009bec: 687b ldr r3, [r7, #4] 8009bee: 681b ldr r3, [r3, #0] 8009bf0: 4a57 ldr r2, [pc, #348] @ (8009d50 ) 8009bf2: 4293 cmp r3, r2 8009bf4: d031 beq.n 8009c5a 8009bf6: 687b ldr r3, [r7, #4] 8009bf8: 681b ldr r3, [r3, #0] 8009bfa: 4a56 ldr r2, [pc, #344] @ (8009d54 ) 8009bfc: 4293 cmp r3, r2 8009bfe: d02c beq.n 8009c5a 8009c00: 687b ldr r3, [r7, #4] 8009c02: 681b ldr r3, [r3, #0] 8009c04: 4a54 ldr r2, [pc, #336] @ (8009d58 ) 8009c06: 4293 cmp r3, r2 8009c08: d027 beq.n 8009c5a 8009c0a: 687b ldr r3, [r7, #4] 8009c0c: 681b ldr r3, [r3, #0] 8009c0e: 4a53 ldr r2, [pc, #332] @ (8009d5c ) 8009c10: 4293 cmp r3, r2 8009c12: d022 beq.n 8009c5a 8009c14: 687b ldr r3, [r7, #4] 8009c16: 681b ldr r3, [r3, #0] 8009c18: 4a51 ldr r2, [pc, #324] @ (8009d60 ) 8009c1a: 4293 cmp r3, r2 8009c1c: d01d beq.n 8009c5a 8009c1e: 687b ldr r3, [r7, #4] 8009c20: 681b ldr r3, [r3, #0] 8009c22: 4a50 ldr r2, [pc, #320] @ (8009d64 ) 8009c24: 4293 cmp r3, r2 8009c26: d018 beq.n 8009c5a 8009c28: 687b ldr r3, [r7, #4] 8009c2a: 681b ldr r3, [r3, #0] 8009c2c: 4a4e ldr r2, [pc, #312] @ (8009d68 ) 8009c2e: 4293 cmp r3, r2 8009c30: d013 beq.n 8009c5a 8009c32: 687b ldr r3, [r7, #4] 8009c34: 681b ldr r3, [r3, #0] 8009c36: 4a4d ldr r2, [pc, #308] @ (8009d6c ) 8009c38: 4293 cmp r3, r2 8009c3a: d00e beq.n 8009c5a 8009c3c: 687b ldr r3, [r7, #4] 8009c3e: 681b ldr r3, [r3, #0] 8009c40: 4a4b ldr r2, [pc, #300] @ (8009d70 ) 8009c42: 4293 cmp r3, r2 8009c44: d009 beq.n 8009c5a 8009c46: 687b ldr r3, [r7, #4] 8009c48: 681b ldr r3, [r3, #0] 8009c4a: 4a4a ldr r2, [pc, #296] @ (8009d74 ) 8009c4c: 4293 cmp r3, r2 8009c4e: d004 beq.n 8009c5a 8009c50: 687b ldr r3, [r7, #4] 8009c52: 681b ldr r3, [r3, #0] 8009c54: 4a48 ldr r2, [pc, #288] @ (8009d78 ) 8009c56: 4293 cmp r3, r2 8009c58: d101 bne.n 8009c5e 8009c5a: 2301 movs r3, #1 8009c5c: e000 b.n 8009c60 8009c5e: 2300 movs r3, #0 8009c60: 2b00 cmp r3, #0 8009c62: f000 842b beq.w 800a4bc { /* Transfer Error Interrupt management ***************************************/ if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009c66: 687b ldr r3, [r7, #4] 8009c68: 6ddb ldr r3, [r3, #92] @ 0x5c 8009c6a: f003 031f and.w r3, r3, #31 8009c6e: 2208 movs r2, #8 8009c70: 409a lsls r2, r3 8009c72: 69bb ldr r3, [r7, #24] 8009c74: 4013 ands r3, r2 8009c76: 2b00 cmp r3, #0 8009c78: f000 80a2 beq.w 8009dc0 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) 8009c7c: 687b ldr r3, [r7, #4] 8009c7e: 681b ldr r3, [r3, #0] 8009c80: 4a2e ldr r2, [pc, #184] @ (8009d3c ) 8009c82: 4293 cmp r3, r2 8009c84: d04a beq.n 8009d1c 8009c86: 687b ldr r3, [r7, #4] 8009c88: 681b ldr r3, [r3, #0] 8009c8a: 4a2d ldr r2, [pc, #180] @ (8009d40 ) 8009c8c: 4293 cmp r3, r2 8009c8e: d045 beq.n 8009d1c 8009c90: 687b ldr r3, [r7, #4] 8009c92: 681b ldr r3, [r3, #0] 8009c94: 4a2b ldr r2, [pc, #172] @ (8009d44 ) 8009c96: 4293 cmp r3, r2 8009c98: d040 beq.n 8009d1c 8009c9a: 687b ldr r3, [r7, #4] 8009c9c: 681b ldr r3, [r3, #0] 8009c9e: 4a2a ldr r2, [pc, #168] @ (8009d48 ) 8009ca0: 4293 cmp r3, r2 8009ca2: d03b beq.n 8009d1c 8009ca4: 687b ldr r3, [r7, #4] 8009ca6: 681b ldr r3, [r3, #0] 8009ca8: 4a28 ldr r2, [pc, #160] @ (8009d4c ) 8009caa: 4293 cmp r3, r2 8009cac: d036 beq.n 8009d1c 8009cae: 687b ldr r3, [r7, #4] 8009cb0: 681b ldr r3, [r3, #0] 8009cb2: 4a27 ldr r2, [pc, #156] @ (8009d50 ) 8009cb4: 4293 cmp r3, r2 8009cb6: d031 beq.n 8009d1c 8009cb8: 687b ldr r3, [r7, #4] 8009cba: 681b ldr r3, [r3, #0] 8009cbc: 4a25 ldr r2, [pc, #148] @ (8009d54 ) 8009cbe: 4293 cmp r3, r2 8009cc0: d02c beq.n 8009d1c 8009cc2: 687b ldr r3, [r7, #4] 8009cc4: 681b ldr r3, [r3, #0] 8009cc6: 4a24 ldr r2, [pc, #144] @ (8009d58 ) 8009cc8: 4293 cmp r3, r2 8009cca: d027 beq.n 8009d1c 8009ccc: 687b ldr r3, [r7, #4] 8009cce: 681b ldr r3, [r3, #0] 8009cd0: 4a22 ldr r2, [pc, #136] @ (8009d5c ) 8009cd2: 4293 cmp r3, r2 8009cd4: d022 beq.n 8009d1c 8009cd6: 687b ldr r3, [r7, #4] 8009cd8: 681b ldr r3, [r3, #0] 8009cda: 4a21 ldr r2, [pc, #132] @ (8009d60 ) 8009cdc: 4293 cmp r3, r2 8009cde: d01d beq.n 8009d1c 8009ce0: 687b ldr r3, [r7, #4] 8009ce2: 681b ldr r3, [r3, #0] 8009ce4: 4a1f ldr r2, [pc, #124] @ (8009d64 ) 8009ce6: 4293 cmp r3, r2 8009ce8: d018 beq.n 8009d1c 8009cea: 687b ldr r3, [r7, #4] 8009cec: 681b ldr r3, [r3, #0] 8009cee: 4a1e ldr r2, [pc, #120] @ (8009d68 ) 8009cf0: 4293 cmp r3, r2 8009cf2: d013 beq.n 8009d1c 8009cf4: 687b ldr r3, [r7, #4] 8009cf6: 681b ldr r3, [r3, #0] 8009cf8: 4a1c ldr r2, [pc, #112] @ (8009d6c ) 8009cfa: 4293 cmp r3, r2 8009cfc: d00e beq.n 8009d1c 8009cfe: 687b ldr r3, [r7, #4] 8009d00: 681b ldr r3, [r3, #0] 8009d02: 4a1b ldr r2, [pc, #108] @ (8009d70 ) 8009d04: 4293 cmp r3, r2 8009d06: d009 beq.n 8009d1c 8009d08: 687b ldr r3, [r7, #4] 8009d0a: 681b ldr r3, [r3, #0] 8009d0c: 4a19 ldr r2, [pc, #100] @ (8009d74 ) 8009d0e: 4293 cmp r3, r2 8009d10: d004 beq.n 8009d1c 8009d12: 687b ldr r3, [r7, #4] 8009d14: 681b ldr r3, [r3, #0] 8009d16: 4a18 ldr r2, [pc, #96] @ (8009d78 ) 8009d18: 4293 cmp r3, r2 8009d1a: d12f bne.n 8009d7c 8009d1c: 687b ldr r3, [r7, #4] 8009d1e: 681b ldr r3, [r3, #0] 8009d20: 681b ldr r3, [r3, #0] 8009d22: f003 0304 and.w r3, r3, #4 8009d26: 2b00 cmp r3, #0 8009d28: bf14 ite ne 8009d2a: 2301 movne r3, #1 8009d2c: 2300 moveq r3, #0 8009d2e: b2db uxtb r3, r3 8009d30: e02e b.n 8009d90 8009d32: bf00 nop 8009d34: 24000034 .word 0x24000034 8009d38: 1b4e81b5 .word 0x1b4e81b5 8009d3c: 40020010 .word 0x40020010 8009d40: 40020028 .word 0x40020028 8009d44: 40020040 .word 0x40020040 8009d48: 40020058 .word 0x40020058 8009d4c: 40020070 .word 0x40020070 8009d50: 40020088 .word 0x40020088 8009d54: 400200a0 .word 0x400200a0 8009d58: 400200b8 .word 0x400200b8 8009d5c: 40020410 .word 0x40020410 8009d60: 40020428 .word 0x40020428 8009d64: 40020440 .word 0x40020440 8009d68: 40020458 .word 0x40020458 8009d6c: 40020470 .word 0x40020470 8009d70: 40020488 .word 0x40020488 8009d74: 400204a0 .word 0x400204a0 8009d78: 400204b8 .word 0x400204b8 8009d7c: 687b ldr r3, [r7, #4] 8009d7e: 681b ldr r3, [r3, #0] 8009d80: 681b ldr r3, [r3, #0] 8009d82: f003 0308 and.w r3, r3, #8 8009d86: 2b00 cmp r3, #0 8009d88: bf14 ite ne 8009d8a: 2301 movne r3, #1 8009d8c: 2300 moveq r3, #0 8009d8e: b2db uxtb r3, r3 8009d90: 2b00 cmp r3, #0 8009d92: d015 beq.n 8009dc0 { /* Disable the transfer error interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); 8009d94: 687b ldr r3, [r7, #4] 8009d96: 681b ldr r3, [r3, #0] 8009d98: 681a ldr r2, [r3, #0] 8009d9a: 687b ldr r3, [r7, #4] 8009d9c: 681b ldr r3, [r3, #0] 8009d9e: f022 0204 bic.w r2, r2, #4 8009da2: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009da4: 687b ldr r3, [r7, #4] 8009da6: 6ddb ldr r3, [r3, #92] @ 0x5c 8009da8: f003 031f and.w r3, r3, #31 8009dac: 2208 movs r2, #8 8009dae: 409a lsls r2, r3 8009db0: 6a3b ldr r3, [r7, #32] 8009db2: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 8009db4: 687b ldr r3, [r7, #4] 8009db6: 6d5b ldr r3, [r3, #84] @ 0x54 8009db8: f043 0201 orr.w r2, r3, #1 8009dbc: 687b ldr r3, [r7, #4] 8009dbe: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009dc0: 687b ldr r3, [r7, #4] 8009dc2: 6ddb ldr r3, [r3, #92] @ 0x5c 8009dc4: f003 031f and.w r3, r3, #31 8009dc8: 69ba ldr r2, [r7, #24] 8009dca: fa22 f303 lsr.w r3, r2, r3 8009dce: f003 0301 and.w r3, r3, #1 8009dd2: 2b00 cmp r3, #0 8009dd4: d06e beq.n 8009eb4 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) 8009dd6: 687b ldr r3, [r7, #4] 8009dd8: 681b ldr r3, [r3, #0] 8009dda: 4a69 ldr r2, [pc, #420] @ (8009f80 ) 8009ddc: 4293 cmp r3, r2 8009dde: d04a beq.n 8009e76 8009de0: 687b ldr r3, [r7, #4] 8009de2: 681b ldr r3, [r3, #0] 8009de4: 4a67 ldr r2, [pc, #412] @ (8009f84 ) 8009de6: 4293 cmp r3, r2 8009de8: d045 beq.n 8009e76 8009dea: 687b ldr r3, [r7, #4] 8009dec: 681b ldr r3, [r3, #0] 8009dee: 4a66 ldr r2, [pc, #408] @ (8009f88 ) 8009df0: 4293 cmp r3, r2 8009df2: d040 beq.n 8009e76 8009df4: 687b ldr r3, [r7, #4] 8009df6: 681b ldr r3, [r3, #0] 8009df8: 4a64 ldr r2, [pc, #400] @ (8009f8c ) 8009dfa: 4293 cmp r3, r2 8009dfc: d03b beq.n 8009e76 8009dfe: 687b ldr r3, [r7, #4] 8009e00: 681b ldr r3, [r3, #0] 8009e02: 4a63 ldr r2, [pc, #396] @ (8009f90 ) 8009e04: 4293 cmp r3, r2 8009e06: d036 beq.n 8009e76 8009e08: 687b ldr r3, [r7, #4] 8009e0a: 681b ldr r3, [r3, #0] 8009e0c: 4a61 ldr r2, [pc, #388] @ (8009f94 ) 8009e0e: 4293 cmp r3, r2 8009e10: d031 beq.n 8009e76 8009e12: 687b ldr r3, [r7, #4] 8009e14: 681b ldr r3, [r3, #0] 8009e16: 4a60 ldr r2, [pc, #384] @ (8009f98 ) 8009e18: 4293 cmp r3, r2 8009e1a: d02c beq.n 8009e76 8009e1c: 687b ldr r3, [r7, #4] 8009e1e: 681b ldr r3, [r3, #0] 8009e20: 4a5e ldr r2, [pc, #376] @ (8009f9c ) 8009e22: 4293 cmp r3, r2 8009e24: d027 beq.n 8009e76 8009e26: 687b ldr r3, [r7, #4] 8009e28: 681b ldr r3, [r3, #0] 8009e2a: 4a5d ldr r2, [pc, #372] @ (8009fa0 ) 8009e2c: 4293 cmp r3, r2 8009e2e: d022 beq.n 8009e76 8009e30: 687b ldr r3, [r7, #4] 8009e32: 681b ldr r3, [r3, #0] 8009e34: 4a5b ldr r2, [pc, #364] @ (8009fa4 ) 8009e36: 4293 cmp r3, r2 8009e38: d01d beq.n 8009e76 8009e3a: 687b ldr r3, [r7, #4] 8009e3c: 681b ldr r3, [r3, #0] 8009e3e: 4a5a ldr r2, [pc, #360] @ (8009fa8 ) 8009e40: 4293 cmp r3, r2 8009e42: d018 beq.n 8009e76 8009e44: 687b ldr r3, [r7, #4] 8009e46: 681b ldr r3, [r3, #0] 8009e48: 4a58 ldr r2, [pc, #352] @ (8009fac ) 8009e4a: 4293 cmp r3, r2 8009e4c: d013 beq.n 8009e76 8009e4e: 687b ldr r3, [r7, #4] 8009e50: 681b ldr r3, [r3, #0] 8009e52: 4a57 ldr r2, [pc, #348] @ (8009fb0 ) 8009e54: 4293 cmp r3, r2 8009e56: d00e beq.n 8009e76 8009e58: 687b ldr r3, [r7, #4] 8009e5a: 681b ldr r3, [r3, #0] 8009e5c: 4a55 ldr r2, [pc, #340] @ (8009fb4 ) 8009e5e: 4293 cmp r3, r2 8009e60: d009 beq.n 8009e76 8009e62: 687b ldr r3, [r7, #4] 8009e64: 681b ldr r3, [r3, #0] 8009e66: 4a54 ldr r2, [pc, #336] @ (8009fb8 ) 8009e68: 4293 cmp r3, r2 8009e6a: d004 beq.n 8009e76 8009e6c: 687b ldr r3, [r7, #4] 8009e6e: 681b ldr r3, [r3, #0] 8009e70: 4a52 ldr r2, [pc, #328] @ (8009fbc ) 8009e72: 4293 cmp r3, r2 8009e74: d10a bne.n 8009e8c 8009e76: 687b ldr r3, [r7, #4] 8009e78: 681b ldr r3, [r3, #0] 8009e7a: 695b ldr r3, [r3, #20] 8009e7c: f003 0380 and.w r3, r3, #128 @ 0x80 8009e80: 2b00 cmp r3, #0 8009e82: bf14 ite ne 8009e84: 2301 movne r3, #1 8009e86: 2300 moveq r3, #0 8009e88: b2db uxtb r3, r3 8009e8a: e003 b.n 8009e94 8009e8c: 687b ldr r3, [r7, #4] 8009e8e: 681b ldr r3, [r3, #0] 8009e90: 681b ldr r3, [r3, #0] 8009e92: 2300 movs r3, #0 8009e94: 2b00 cmp r3, #0 8009e96: d00d beq.n 8009eb4 { /* Clear the FIFO error flag */ regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009e98: 687b ldr r3, [r7, #4] 8009e9a: 6ddb ldr r3, [r3, #92] @ 0x5c 8009e9c: f003 031f and.w r3, r3, #31 8009ea0: 2201 movs r2, #1 8009ea2: 409a lsls r2, r3 8009ea4: 6a3b ldr r3, [r7, #32] 8009ea6: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 8009ea8: 687b ldr r3, [r7, #4] 8009eaa: 6d5b ldr r3, [r3, #84] @ 0x54 8009eac: f043 0202 orr.w r2, r3, #2 8009eb0: 687b ldr r3, [r7, #4] 8009eb2: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009eb4: 687b ldr r3, [r7, #4] 8009eb6: 6ddb ldr r3, [r3, #92] @ 0x5c 8009eb8: f003 031f and.w r3, r3, #31 8009ebc: 2204 movs r2, #4 8009ebe: 409a lsls r2, r3 8009ec0: 69bb ldr r3, [r7, #24] 8009ec2: 4013 ands r3, r2 8009ec4: 2b00 cmp r3, #0 8009ec6: f000 808f beq.w 8009fe8 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) 8009eca: 687b ldr r3, [r7, #4] 8009ecc: 681b ldr r3, [r3, #0] 8009ece: 4a2c ldr r2, [pc, #176] @ (8009f80 ) 8009ed0: 4293 cmp r3, r2 8009ed2: d04a beq.n 8009f6a 8009ed4: 687b ldr r3, [r7, #4] 8009ed6: 681b ldr r3, [r3, #0] 8009ed8: 4a2a ldr r2, [pc, #168] @ (8009f84 ) 8009eda: 4293 cmp r3, r2 8009edc: d045 beq.n 8009f6a 8009ede: 687b ldr r3, [r7, #4] 8009ee0: 681b ldr r3, [r3, #0] 8009ee2: 4a29 ldr r2, [pc, #164] @ (8009f88 ) 8009ee4: 4293 cmp r3, r2 8009ee6: d040 beq.n 8009f6a 8009ee8: 687b ldr r3, [r7, #4] 8009eea: 681b ldr r3, [r3, #0] 8009eec: 4a27 ldr r2, [pc, #156] @ (8009f8c ) 8009eee: 4293 cmp r3, r2 8009ef0: d03b beq.n 8009f6a 8009ef2: 687b ldr r3, [r7, #4] 8009ef4: 681b ldr r3, [r3, #0] 8009ef6: 4a26 ldr r2, [pc, #152] @ (8009f90 ) 8009ef8: 4293 cmp r3, r2 8009efa: d036 beq.n 8009f6a 8009efc: 687b ldr r3, [r7, #4] 8009efe: 681b ldr r3, [r3, #0] 8009f00: 4a24 ldr r2, [pc, #144] @ (8009f94 ) 8009f02: 4293 cmp r3, r2 8009f04: d031 beq.n 8009f6a 8009f06: 687b ldr r3, [r7, #4] 8009f08: 681b ldr r3, [r3, #0] 8009f0a: 4a23 ldr r2, [pc, #140] @ (8009f98 ) 8009f0c: 4293 cmp r3, r2 8009f0e: d02c beq.n 8009f6a 8009f10: 687b ldr r3, [r7, #4] 8009f12: 681b ldr r3, [r3, #0] 8009f14: 4a21 ldr r2, [pc, #132] @ (8009f9c ) 8009f16: 4293 cmp r3, r2 8009f18: d027 beq.n 8009f6a 8009f1a: 687b ldr r3, [r7, #4] 8009f1c: 681b ldr r3, [r3, #0] 8009f1e: 4a20 ldr r2, [pc, #128] @ (8009fa0 ) 8009f20: 4293 cmp r3, r2 8009f22: d022 beq.n 8009f6a 8009f24: 687b ldr r3, [r7, #4] 8009f26: 681b ldr r3, [r3, #0] 8009f28: 4a1e ldr r2, [pc, #120] @ (8009fa4 ) 8009f2a: 4293 cmp r3, r2 8009f2c: d01d beq.n 8009f6a 8009f2e: 687b ldr r3, [r7, #4] 8009f30: 681b ldr r3, [r3, #0] 8009f32: 4a1d ldr r2, [pc, #116] @ (8009fa8 ) 8009f34: 4293 cmp r3, r2 8009f36: d018 beq.n 8009f6a 8009f38: 687b ldr r3, [r7, #4] 8009f3a: 681b ldr r3, [r3, #0] 8009f3c: 4a1b ldr r2, [pc, #108] @ (8009fac ) 8009f3e: 4293 cmp r3, r2 8009f40: d013 beq.n 8009f6a 8009f42: 687b ldr r3, [r7, #4] 8009f44: 681b ldr r3, [r3, #0] 8009f46: 4a1a ldr r2, [pc, #104] @ (8009fb0 ) 8009f48: 4293 cmp r3, r2 8009f4a: d00e beq.n 8009f6a 8009f4c: 687b ldr r3, [r7, #4] 8009f4e: 681b ldr r3, [r3, #0] 8009f50: 4a18 ldr r2, [pc, #96] @ (8009fb4 ) 8009f52: 4293 cmp r3, r2 8009f54: d009 beq.n 8009f6a 8009f56: 687b ldr r3, [r7, #4] 8009f58: 681b ldr r3, [r3, #0] 8009f5a: 4a17 ldr r2, [pc, #92] @ (8009fb8 ) 8009f5c: 4293 cmp r3, r2 8009f5e: d004 beq.n 8009f6a 8009f60: 687b ldr r3, [r7, #4] 8009f62: 681b ldr r3, [r3, #0] 8009f64: 4a15 ldr r2, [pc, #84] @ (8009fbc ) 8009f66: 4293 cmp r3, r2 8009f68: d12a bne.n 8009fc0 8009f6a: 687b ldr r3, [r7, #4] 8009f6c: 681b ldr r3, [r3, #0] 8009f6e: 681b ldr r3, [r3, #0] 8009f70: f003 0302 and.w r3, r3, #2 8009f74: 2b00 cmp r3, #0 8009f76: bf14 ite ne 8009f78: 2301 movne r3, #1 8009f7a: 2300 moveq r3, #0 8009f7c: b2db uxtb r3, r3 8009f7e: e023 b.n 8009fc8 8009f80: 40020010 .word 0x40020010 8009f84: 40020028 .word 0x40020028 8009f88: 40020040 .word 0x40020040 8009f8c: 40020058 .word 0x40020058 8009f90: 40020070 .word 0x40020070 8009f94: 40020088 .word 0x40020088 8009f98: 400200a0 .word 0x400200a0 8009f9c: 400200b8 .word 0x400200b8 8009fa0: 40020410 .word 0x40020410 8009fa4: 40020428 .word 0x40020428 8009fa8: 40020440 .word 0x40020440 8009fac: 40020458 .word 0x40020458 8009fb0: 40020470 .word 0x40020470 8009fb4: 40020488 .word 0x40020488 8009fb8: 400204a0 .word 0x400204a0 8009fbc: 400204b8 .word 0x400204b8 8009fc0: 687b ldr r3, [r7, #4] 8009fc2: 681b ldr r3, [r3, #0] 8009fc4: 681b ldr r3, [r3, #0] 8009fc6: 2300 movs r3, #0 8009fc8: 2b00 cmp r3, #0 8009fca: d00d beq.n 8009fe8 { /* Clear the direct mode error flag */ regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009fcc: 687b ldr r3, [r7, #4] 8009fce: 6ddb ldr r3, [r3, #92] @ 0x5c 8009fd0: f003 031f and.w r3, r3, #31 8009fd4: 2204 movs r2, #4 8009fd6: 409a lsls r2, r3 8009fd8: 6a3b ldr r3, [r7, #32] 8009fda: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 8009fdc: 687b ldr r3, [r7, #4] 8009fde: 6d5b ldr r3, [r3, #84] @ 0x54 8009fe0: f043 0204 orr.w r2, r3, #4 8009fe4: 687b ldr r3, [r7, #4] 8009fe6: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009fe8: 687b ldr r3, [r7, #4] 8009fea: 6ddb ldr r3, [r3, #92] @ 0x5c 8009fec: f003 031f and.w r3, r3, #31 8009ff0: 2210 movs r2, #16 8009ff2: 409a lsls r2, r3 8009ff4: 69bb ldr r3, [r7, #24] 8009ff6: 4013 ands r3, r2 8009ff8: 2b00 cmp r3, #0 8009ffa: f000 80a6 beq.w 800a14a { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) 8009ffe: 687b ldr r3, [r7, #4] 800a000: 681b ldr r3, [r3, #0] 800a002: 4a85 ldr r2, [pc, #532] @ (800a218 ) 800a004: 4293 cmp r3, r2 800a006: d04a beq.n 800a09e 800a008: 687b ldr r3, [r7, #4] 800a00a: 681b ldr r3, [r3, #0] 800a00c: 4a83 ldr r2, [pc, #524] @ (800a21c ) 800a00e: 4293 cmp r3, r2 800a010: d045 beq.n 800a09e 800a012: 687b ldr r3, [r7, #4] 800a014: 681b ldr r3, [r3, #0] 800a016: 4a82 ldr r2, [pc, #520] @ (800a220 ) 800a018: 4293 cmp r3, r2 800a01a: d040 beq.n 800a09e 800a01c: 687b ldr r3, [r7, #4] 800a01e: 681b ldr r3, [r3, #0] 800a020: 4a80 ldr r2, [pc, #512] @ (800a224 ) 800a022: 4293 cmp r3, r2 800a024: d03b beq.n 800a09e 800a026: 687b ldr r3, [r7, #4] 800a028: 681b ldr r3, [r3, #0] 800a02a: 4a7f ldr r2, [pc, #508] @ (800a228 ) 800a02c: 4293 cmp r3, r2 800a02e: d036 beq.n 800a09e 800a030: 687b ldr r3, [r7, #4] 800a032: 681b ldr r3, [r3, #0] 800a034: 4a7d ldr r2, [pc, #500] @ (800a22c ) 800a036: 4293 cmp r3, r2 800a038: d031 beq.n 800a09e 800a03a: 687b ldr r3, [r7, #4] 800a03c: 681b ldr r3, [r3, #0] 800a03e: 4a7c ldr r2, [pc, #496] @ (800a230 ) 800a040: 4293 cmp r3, r2 800a042: d02c beq.n 800a09e 800a044: 687b ldr r3, [r7, #4] 800a046: 681b ldr r3, [r3, #0] 800a048: 4a7a ldr r2, [pc, #488] @ (800a234 ) 800a04a: 4293 cmp r3, r2 800a04c: d027 beq.n 800a09e 800a04e: 687b ldr r3, [r7, #4] 800a050: 681b ldr r3, [r3, #0] 800a052: 4a79 ldr r2, [pc, #484] @ (800a238 ) 800a054: 4293 cmp r3, r2 800a056: d022 beq.n 800a09e 800a058: 687b ldr r3, [r7, #4] 800a05a: 681b ldr r3, [r3, #0] 800a05c: 4a77 ldr r2, [pc, #476] @ (800a23c ) 800a05e: 4293 cmp r3, r2 800a060: d01d beq.n 800a09e 800a062: 687b ldr r3, [r7, #4] 800a064: 681b ldr r3, [r3, #0] 800a066: 4a76 ldr r2, [pc, #472] @ (800a240 ) 800a068: 4293 cmp r3, r2 800a06a: d018 beq.n 800a09e 800a06c: 687b ldr r3, [r7, #4] 800a06e: 681b ldr r3, [r3, #0] 800a070: 4a74 ldr r2, [pc, #464] @ (800a244 ) 800a072: 4293 cmp r3, r2 800a074: d013 beq.n 800a09e 800a076: 687b ldr r3, [r7, #4] 800a078: 681b ldr r3, [r3, #0] 800a07a: 4a73 ldr r2, [pc, #460] @ (800a248 ) 800a07c: 4293 cmp r3, r2 800a07e: d00e beq.n 800a09e 800a080: 687b ldr r3, [r7, #4] 800a082: 681b ldr r3, [r3, #0] 800a084: 4a71 ldr r2, [pc, #452] @ (800a24c ) 800a086: 4293 cmp r3, r2 800a088: d009 beq.n 800a09e 800a08a: 687b ldr r3, [r7, #4] 800a08c: 681b ldr r3, [r3, #0] 800a08e: 4a70 ldr r2, [pc, #448] @ (800a250 ) 800a090: 4293 cmp r3, r2 800a092: d004 beq.n 800a09e 800a094: 687b ldr r3, [r7, #4] 800a096: 681b ldr r3, [r3, #0] 800a098: 4a6e ldr r2, [pc, #440] @ (800a254 ) 800a09a: 4293 cmp r3, r2 800a09c: d10a bne.n 800a0b4 800a09e: 687b ldr r3, [r7, #4] 800a0a0: 681b ldr r3, [r3, #0] 800a0a2: 681b ldr r3, [r3, #0] 800a0a4: f003 0308 and.w r3, r3, #8 800a0a8: 2b00 cmp r3, #0 800a0aa: bf14 ite ne 800a0ac: 2301 movne r3, #1 800a0ae: 2300 moveq r3, #0 800a0b0: b2db uxtb r3, r3 800a0b2: e009 b.n 800a0c8 800a0b4: 687b ldr r3, [r7, #4] 800a0b6: 681b ldr r3, [r3, #0] 800a0b8: 681b ldr r3, [r3, #0] 800a0ba: f003 0304 and.w r3, r3, #4 800a0be: 2b00 cmp r3, #0 800a0c0: bf14 ite ne 800a0c2: 2301 movne r3, #1 800a0c4: 2300 moveq r3, #0 800a0c6: b2db uxtb r3, r3 800a0c8: 2b00 cmp r3, #0 800a0ca: d03e beq.n 800a14a { /* Clear the half transfer complete flag */ regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); 800a0cc: 687b ldr r3, [r7, #4] 800a0ce: 6ddb ldr r3, [r3, #92] @ 0x5c 800a0d0: f003 031f and.w r3, r3, #31 800a0d4: 2210 movs r2, #16 800a0d6: 409a lsls r2, r3 800a0d8: 6a3b ldr r3, [r7, #32] 800a0da: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 800a0dc: 687b ldr r3, [r7, #4] 800a0de: 681b ldr r3, [r3, #0] 800a0e0: 681b ldr r3, [r3, #0] 800a0e2: f403 2380 and.w r3, r3, #262144 @ 0x40000 800a0e6: 2b00 cmp r3, #0 800a0e8: d018 beq.n 800a11c { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 800a0ea: 687b ldr r3, [r7, #4] 800a0ec: 681b ldr r3, [r3, #0] 800a0ee: 681b ldr r3, [r3, #0] 800a0f0: f403 2300 and.w r3, r3, #524288 @ 0x80000 800a0f4: 2b00 cmp r3, #0 800a0f6: d108 bne.n 800a10a { if(hdma->XferHalfCpltCallback != NULL) 800a0f8: 687b ldr r3, [r7, #4] 800a0fa: 6c1b ldr r3, [r3, #64] @ 0x40 800a0fc: 2b00 cmp r3, #0 800a0fe: d024 beq.n 800a14a { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800a100: 687b ldr r3, [r7, #4] 800a102: 6c1b ldr r3, [r3, #64] @ 0x40 800a104: 6878 ldr r0, [r7, #4] 800a106: 4798 blx r3 800a108: e01f b.n 800a14a } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 800a10a: 687b ldr r3, [r7, #4] 800a10c: 6c9b ldr r3, [r3, #72] @ 0x48 800a10e: 2b00 cmp r3, #0 800a110: d01b beq.n 800a14a { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 800a112: 687b ldr r3, [r7, #4] 800a114: 6c9b ldr r3, [r3, #72] @ 0x48 800a116: 6878 ldr r0, [r7, #4] 800a118: 4798 blx r3 800a11a: e016 b.n 800a14a } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 800a11c: 687b ldr r3, [r7, #4] 800a11e: 681b ldr r3, [r3, #0] 800a120: 681b ldr r3, [r3, #0] 800a122: f403 7380 and.w r3, r3, #256 @ 0x100 800a126: 2b00 cmp r3, #0 800a128: d107 bne.n 800a13a { /* Disable the half transfer interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 800a12a: 687b ldr r3, [r7, #4] 800a12c: 681b ldr r3, [r3, #0] 800a12e: 681a ldr r2, [r3, #0] 800a130: 687b ldr r3, [r7, #4] 800a132: 681b ldr r3, [r3, #0] 800a134: f022 0208 bic.w r2, r2, #8 800a138: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 800a13a: 687b ldr r3, [r7, #4] 800a13c: 6c1b ldr r3, [r3, #64] @ 0x40 800a13e: 2b00 cmp r3, #0 800a140: d003 beq.n 800a14a { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800a142: 687b ldr r3, [r7, #4] 800a144: 6c1b ldr r3, [r3, #64] @ 0x40 800a146: 6878 ldr r0, [r7, #4] 800a148: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 800a14a: 687b ldr r3, [r7, #4] 800a14c: 6ddb ldr r3, [r3, #92] @ 0x5c 800a14e: f003 031f and.w r3, r3, #31 800a152: 2220 movs r2, #32 800a154: 409a lsls r2, r3 800a156: 69bb ldr r3, [r7, #24] 800a158: 4013 ands r3, r2 800a15a: 2b00 cmp r3, #0 800a15c: f000 8110 beq.w 800a380 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) 800a160: 687b ldr r3, [r7, #4] 800a162: 681b ldr r3, [r3, #0] 800a164: 4a2c ldr r2, [pc, #176] @ (800a218 ) 800a166: 4293 cmp r3, r2 800a168: d04a beq.n 800a200 800a16a: 687b ldr r3, [r7, #4] 800a16c: 681b ldr r3, [r3, #0] 800a16e: 4a2b ldr r2, [pc, #172] @ (800a21c ) 800a170: 4293 cmp r3, r2 800a172: d045 beq.n 800a200 800a174: 687b ldr r3, [r7, #4] 800a176: 681b ldr r3, [r3, #0] 800a178: 4a29 ldr r2, [pc, #164] @ (800a220 ) 800a17a: 4293 cmp r3, r2 800a17c: d040 beq.n 800a200 800a17e: 687b ldr r3, [r7, #4] 800a180: 681b ldr r3, [r3, #0] 800a182: 4a28 ldr r2, [pc, #160] @ (800a224 ) 800a184: 4293 cmp r3, r2 800a186: d03b beq.n 800a200 800a188: 687b ldr r3, [r7, #4] 800a18a: 681b ldr r3, [r3, #0] 800a18c: 4a26 ldr r2, [pc, #152] @ (800a228 ) 800a18e: 4293 cmp r3, r2 800a190: d036 beq.n 800a200 800a192: 687b ldr r3, [r7, #4] 800a194: 681b ldr r3, [r3, #0] 800a196: 4a25 ldr r2, [pc, #148] @ (800a22c ) 800a198: 4293 cmp r3, r2 800a19a: d031 beq.n 800a200 800a19c: 687b ldr r3, [r7, #4] 800a19e: 681b ldr r3, [r3, #0] 800a1a0: 4a23 ldr r2, [pc, #140] @ (800a230 ) 800a1a2: 4293 cmp r3, r2 800a1a4: d02c beq.n 800a200 800a1a6: 687b ldr r3, [r7, #4] 800a1a8: 681b ldr r3, [r3, #0] 800a1aa: 4a22 ldr r2, [pc, #136] @ (800a234 ) 800a1ac: 4293 cmp r3, r2 800a1ae: d027 beq.n 800a200 800a1b0: 687b ldr r3, [r7, #4] 800a1b2: 681b ldr r3, [r3, #0] 800a1b4: 4a20 ldr r2, [pc, #128] @ (800a238 ) 800a1b6: 4293 cmp r3, r2 800a1b8: d022 beq.n 800a200 800a1ba: 687b ldr r3, [r7, #4] 800a1bc: 681b ldr r3, [r3, #0] 800a1be: 4a1f ldr r2, [pc, #124] @ (800a23c ) 800a1c0: 4293 cmp r3, r2 800a1c2: d01d beq.n 800a200 800a1c4: 687b ldr r3, [r7, #4] 800a1c6: 681b ldr r3, [r3, #0] 800a1c8: 4a1d ldr r2, [pc, #116] @ (800a240 ) 800a1ca: 4293 cmp r3, r2 800a1cc: d018 beq.n 800a200 800a1ce: 687b ldr r3, [r7, #4] 800a1d0: 681b ldr r3, [r3, #0] 800a1d2: 4a1c ldr r2, [pc, #112] @ (800a244 ) 800a1d4: 4293 cmp r3, r2 800a1d6: d013 beq.n 800a200 800a1d8: 687b ldr r3, [r7, #4] 800a1da: 681b ldr r3, [r3, #0] 800a1dc: 4a1a ldr r2, [pc, #104] @ (800a248 ) 800a1de: 4293 cmp r3, r2 800a1e0: d00e beq.n 800a200 800a1e2: 687b ldr r3, [r7, #4] 800a1e4: 681b ldr r3, [r3, #0] 800a1e6: 4a19 ldr r2, [pc, #100] @ (800a24c ) 800a1e8: 4293 cmp r3, r2 800a1ea: d009 beq.n 800a200 800a1ec: 687b ldr r3, [r7, #4] 800a1ee: 681b ldr r3, [r3, #0] 800a1f0: 4a17 ldr r2, [pc, #92] @ (800a250 ) 800a1f2: 4293 cmp r3, r2 800a1f4: d004 beq.n 800a200 800a1f6: 687b ldr r3, [r7, #4] 800a1f8: 681b ldr r3, [r3, #0] 800a1fa: 4a16 ldr r2, [pc, #88] @ (800a254 ) 800a1fc: 4293 cmp r3, r2 800a1fe: d12b bne.n 800a258 800a200: 687b ldr r3, [r7, #4] 800a202: 681b ldr r3, [r3, #0] 800a204: 681b ldr r3, [r3, #0] 800a206: f003 0310 and.w r3, r3, #16 800a20a: 2b00 cmp r3, #0 800a20c: bf14 ite ne 800a20e: 2301 movne r3, #1 800a210: 2300 moveq r3, #0 800a212: b2db uxtb r3, r3 800a214: e02a b.n 800a26c 800a216: bf00 nop 800a218: 40020010 .word 0x40020010 800a21c: 40020028 .word 0x40020028 800a220: 40020040 .word 0x40020040 800a224: 40020058 .word 0x40020058 800a228: 40020070 .word 0x40020070 800a22c: 40020088 .word 0x40020088 800a230: 400200a0 .word 0x400200a0 800a234: 400200b8 .word 0x400200b8 800a238: 40020410 .word 0x40020410 800a23c: 40020428 .word 0x40020428 800a240: 40020440 .word 0x40020440 800a244: 40020458 .word 0x40020458 800a248: 40020470 .word 0x40020470 800a24c: 40020488 .word 0x40020488 800a250: 400204a0 .word 0x400204a0 800a254: 400204b8 .word 0x400204b8 800a258: 687b ldr r3, [r7, #4] 800a25a: 681b ldr r3, [r3, #0] 800a25c: 681b ldr r3, [r3, #0] 800a25e: f003 0302 and.w r3, r3, #2 800a262: 2b00 cmp r3, #0 800a264: bf14 ite ne 800a266: 2301 movne r3, #1 800a268: 2300 moveq r3, #0 800a26a: b2db uxtb r3, r3 800a26c: 2b00 cmp r3, #0 800a26e: f000 8087 beq.w 800a380 { /* Clear the transfer complete flag */ regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); 800a272: 687b ldr r3, [r7, #4] 800a274: 6ddb ldr r3, [r3, #92] @ 0x5c 800a276: f003 031f and.w r3, r3, #31 800a27a: 2220 movs r2, #32 800a27c: 409a lsls r2, r3 800a27e: 6a3b ldr r3, [r7, #32] 800a280: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 800a282: 687b ldr r3, [r7, #4] 800a284: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 800a288: b2db uxtb r3, r3 800a28a: 2b04 cmp r3, #4 800a28c: d139 bne.n 800a302 { /* Disable all the transfer interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 800a28e: 687b ldr r3, [r7, #4] 800a290: 681b ldr r3, [r3, #0] 800a292: 681a ldr r2, [r3, #0] 800a294: 687b ldr r3, [r7, #4] 800a296: 681b ldr r3, [r3, #0] 800a298: f022 0216 bic.w r2, r2, #22 800a29c: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 800a29e: 687b ldr r3, [r7, #4] 800a2a0: 681b ldr r3, [r3, #0] 800a2a2: 695a ldr r2, [r3, #20] 800a2a4: 687b ldr r3, [r7, #4] 800a2a6: 681b ldr r3, [r3, #0] 800a2a8: f022 0280 bic.w r2, r2, #128 @ 0x80 800a2ac: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 800a2ae: 687b ldr r3, [r7, #4] 800a2b0: 6c1b ldr r3, [r3, #64] @ 0x40 800a2b2: 2b00 cmp r3, #0 800a2b4: d103 bne.n 800a2be 800a2b6: 687b ldr r3, [r7, #4] 800a2b8: 6c9b ldr r3, [r3, #72] @ 0x48 800a2ba: 2b00 cmp r3, #0 800a2bc: d007 beq.n 800a2ce { ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 800a2be: 687b ldr r3, [r7, #4] 800a2c0: 681b ldr r3, [r3, #0] 800a2c2: 681a ldr r2, [r3, #0] 800a2c4: 687b ldr r3, [r7, #4] 800a2c6: 681b ldr r3, [r3, #0] 800a2c8: f022 0208 bic.w r2, r2, #8 800a2cc: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800a2ce: 687b ldr r3, [r7, #4] 800a2d0: 6ddb ldr r3, [r3, #92] @ 0x5c 800a2d2: f003 031f and.w r3, r3, #31 800a2d6: 223f movs r2, #63 @ 0x3f 800a2d8: 409a lsls r2, r3 800a2da: 6a3b ldr r3, [r7, #32] 800a2dc: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a2de: 687b ldr r3, [r7, #4] 800a2e0: 2201 movs r2, #1 800a2e2: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a2e6: 687b ldr r3, [r7, #4] 800a2e8: 2200 movs r2, #0 800a2ea: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 800a2ee: 687b ldr r3, [r7, #4] 800a2f0: 6d1b ldr r3, [r3, #80] @ 0x50 800a2f2: 2b00 cmp r3, #0 800a2f4: f000 834a beq.w 800a98c { hdma->XferAbortCallback(hdma); 800a2f8: 687b ldr r3, [r7, #4] 800a2fa: 6d1b ldr r3, [r3, #80] @ 0x50 800a2fc: 6878 ldr r0, [r7, #4] 800a2fe: 4798 blx r3 } return; 800a300: e344 b.n 800a98c } if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 800a302: 687b ldr r3, [r7, #4] 800a304: 681b ldr r3, [r3, #0] 800a306: 681b ldr r3, [r3, #0] 800a308: f403 2380 and.w r3, r3, #262144 @ 0x40000 800a30c: 2b00 cmp r3, #0 800a30e: d018 beq.n 800a342 { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 800a310: 687b ldr r3, [r7, #4] 800a312: 681b ldr r3, [r3, #0] 800a314: 681b ldr r3, [r3, #0] 800a316: f403 2300 and.w r3, r3, #524288 @ 0x80000 800a31a: 2b00 cmp r3, #0 800a31c: d108 bne.n 800a330 { if(hdma->XferM1CpltCallback != NULL) 800a31e: 687b ldr r3, [r7, #4] 800a320: 6c5b ldr r3, [r3, #68] @ 0x44 800a322: 2b00 cmp r3, #0 800a324: d02c beq.n 800a380 { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 800a326: 687b ldr r3, [r7, #4] 800a328: 6c5b ldr r3, [r3, #68] @ 0x44 800a32a: 6878 ldr r0, [r7, #4] 800a32c: 4798 blx r3 800a32e: e027 b.n 800a380 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800a330: 687b ldr r3, [r7, #4] 800a332: 6bdb ldr r3, [r3, #60] @ 0x3c 800a334: 2b00 cmp r3, #0 800a336: d023 beq.n 800a380 { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 800a338: 687b ldr r3, [r7, #4] 800a33a: 6bdb ldr r3, [r3, #60] @ 0x3c 800a33c: 6878 ldr r0, [r7, #4] 800a33e: 4798 blx r3 800a340: e01e b.n 800a380 } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 800a342: 687b ldr r3, [r7, #4] 800a344: 681b ldr r3, [r3, #0] 800a346: 681b ldr r3, [r3, #0] 800a348: f403 7380 and.w r3, r3, #256 @ 0x100 800a34c: 2b00 cmp r3, #0 800a34e: d10f bne.n 800a370 { /* Disable the transfer complete interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); 800a350: 687b ldr r3, [r7, #4] 800a352: 681b ldr r3, [r3, #0] 800a354: 681a ldr r2, [r3, #0] 800a356: 687b ldr r3, [r7, #4] 800a358: 681b ldr r3, [r3, #0] 800a35a: f022 0210 bic.w r2, r2, #16 800a35e: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a360: 687b ldr r3, [r7, #4] 800a362: 2201 movs r2, #1 800a364: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a368: 687b ldr r3, [r7, #4] 800a36a: 2200 movs r2, #0 800a36c: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 800a370: 687b ldr r3, [r7, #4] 800a372: 6bdb ldr r3, [r3, #60] @ 0x3c 800a374: 2b00 cmp r3, #0 800a376: d003 beq.n 800a380 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 800a378: 687b ldr r3, [r7, #4] 800a37a: 6bdb ldr r3, [r3, #60] @ 0x3c 800a37c: 6878 ldr r0, [r7, #4] 800a37e: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 800a380: 687b ldr r3, [r7, #4] 800a382: 6d5b ldr r3, [r3, #84] @ 0x54 800a384: 2b00 cmp r3, #0 800a386: f000 8306 beq.w 800a996 { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) 800a38a: 687b ldr r3, [r7, #4] 800a38c: 6d5b ldr r3, [r3, #84] @ 0x54 800a38e: f003 0301 and.w r3, r3, #1 800a392: 2b00 cmp r3, #0 800a394: f000 8088 beq.w 800a4a8 { hdma->State = HAL_DMA_STATE_ABORT; 800a398: 687b ldr r3, [r7, #4] 800a39a: 2204 movs r2, #4 800a39c: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800a3a0: 687b ldr r3, [r7, #4] 800a3a2: 681b ldr r3, [r3, #0] 800a3a4: 4a7a ldr r2, [pc, #488] @ (800a590 ) 800a3a6: 4293 cmp r3, r2 800a3a8: d04a beq.n 800a440 800a3aa: 687b ldr r3, [r7, #4] 800a3ac: 681b ldr r3, [r3, #0] 800a3ae: 4a79 ldr r2, [pc, #484] @ (800a594 ) 800a3b0: 4293 cmp r3, r2 800a3b2: d045 beq.n 800a440 800a3b4: 687b ldr r3, [r7, #4] 800a3b6: 681b ldr r3, [r3, #0] 800a3b8: 4a77 ldr r2, [pc, #476] @ (800a598 ) 800a3ba: 4293 cmp r3, r2 800a3bc: d040 beq.n 800a440 800a3be: 687b ldr r3, [r7, #4] 800a3c0: 681b ldr r3, [r3, #0] 800a3c2: 4a76 ldr r2, [pc, #472] @ (800a59c ) 800a3c4: 4293 cmp r3, r2 800a3c6: d03b beq.n 800a440 800a3c8: 687b ldr r3, [r7, #4] 800a3ca: 681b ldr r3, [r3, #0] 800a3cc: 4a74 ldr r2, [pc, #464] @ (800a5a0 ) 800a3ce: 4293 cmp r3, r2 800a3d0: d036 beq.n 800a440 800a3d2: 687b ldr r3, [r7, #4] 800a3d4: 681b ldr r3, [r3, #0] 800a3d6: 4a73 ldr r2, [pc, #460] @ (800a5a4 ) 800a3d8: 4293 cmp r3, r2 800a3da: d031 beq.n 800a440 800a3dc: 687b ldr r3, [r7, #4] 800a3de: 681b ldr r3, [r3, #0] 800a3e0: 4a71 ldr r2, [pc, #452] @ (800a5a8 ) 800a3e2: 4293 cmp r3, r2 800a3e4: d02c beq.n 800a440 800a3e6: 687b ldr r3, [r7, #4] 800a3e8: 681b ldr r3, [r3, #0] 800a3ea: 4a70 ldr r2, [pc, #448] @ (800a5ac ) 800a3ec: 4293 cmp r3, r2 800a3ee: d027 beq.n 800a440 800a3f0: 687b ldr r3, [r7, #4] 800a3f2: 681b ldr r3, [r3, #0] 800a3f4: 4a6e ldr r2, [pc, #440] @ (800a5b0 ) 800a3f6: 4293 cmp r3, r2 800a3f8: d022 beq.n 800a440 800a3fa: 687b ldr r3, [r7, #4] 800a3fc: 681b ldr r3, [r3, #0] 800a3fe: 4a6d ldr r2, [pc, #436] @ (800a5b4 ) 800a400: 4293 cmp r3, r2 800a402: d01d beq.n 800a440 800a404: 687b ldr r3, [r7, #4] 800a406: 681b ldr r3, [r3, #0] 800a408: 4a6b ldr r2, [pc, #428] @ (800a5b8 ) 800a40a: 4293 cmp r3, r2 800a40c: d018 beq.n 800a440 800a40e: 687b ldr r3, [r7, #4] 800a410: 681b ldr r3, [r3, #0] 800a412: 4a6a ldr r2, [pc, #424] @ (800a5bc ) 800a414: 4293 cmp r3, r2 800a416: d013 beq.n 800a440 800a418: 687b ldr r3, [r7, #4] 800a41a: 681b ldr r3, [r3, #0] 800a41c: 4a68 ldr r2, [pc, #416] @ (800a5c0 ) 800a41e: 4293 cmp r3, r2 800a420: d00e beq.n 800a440 800a422: 687b ldr r3, [r7, #4] 800a424: 681b ldr r3, [r3, #0] 800a426: 4a67 ldr r2, [pc, #412] @ (800a5c4 ) 800a428: 4293 cmp r3, r2 800a42a: d009 beq.n 800a440 800a42c: 687b ldr r3, [r7, #4] 800a42e: 681b ldr r3, [r3, #0] 800a430: 4a65 ldr r2, [pc, #404] @ (800a5c8 ) 800a432: 4293 cmp r3, r2 800a434: d004 beq.n 800a440 800a436: 687b ldr r3, [r7, #4] 800a438: 681b ldr r3, [r3, #0] 800a43a: 4a64 ldr r2, [pc, #400] @ (800a5cc ) 800a43c: 4293 cmp r3, r2 800a43e: d108 bne.n 800a452 800a440: 687b ldr r3, [r7, #4] 800a442: 681b ldr r3, [r3, #0] 800a444: 681a ldr r2, [r3, #0] 800a446: 687b ldr r3, [r7, #4] 800a448: 681b ldr r3, [r3, #0] 800a44a: f022 0201 bic.w r2, r2, #1 800a44e: 601a str r2, [r3, #0] 800a450: e007 b.n 800a462 800a452: 687b ldr r3, [r7, #4] 800a454: 681b ldr r3, [r3, #0] 800a456: 681a ldr r2, [r3, #0] 800a458: 687b ldr r3, [r7, #4] 800a45a: 681b ldr r3, [r3, #0] 800a45c: f022 0201 bic.w r2, r2, #1 800a460: 601a str r2, [r3, #0] do { if (++count > timeout) 800a462: 68fb ldr r3, [r7, #12] 800a464: 3301 adds r3, #1 800a466: 60fb str r3, [r7, #12] 800a468: 6a7a ldr r2, [r7, #36] @ 0x24 800a46a: 429a cmp r2, r3 800a46c: d307 bcc.n 800a47e { break; } } while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); 800a46e: 687b ldr r3, [r7, #4] 800a470: 681b ldr r3, [r3, #0] 800a472: 681b ldr r3, [r3, #0] 800a474: f003 0301 and.w r3, r3, #1 800a478: 2b00 cmp r3, #0 800a47a: d1f2 bne.n 800a462 800a47c: e000 b.n 800a480 break; 800a47e: bf00 nop if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 800a480: 687b ldr r3, [r7, #4] 800a482: 681b ldr r3, [r3, #0] 800a484: 681b ldr r3, [r3, #0] 800a486: f003 0301 and.w r3, r3, #1 800a48a: 2b00 cmp r3, #0 800a48c: d004 beq.n 800a498 { /* Change the DMA state to error if DMA disable fails */ hdma->State = HAL_DMA_STATE_ERROR; 800a48e: 687b ldr r3, [r7, #4] 800a490: 2203 movs r2, #3 800a492: f883 2035 strb.w r2, [r3, #53] @ 0x35 800a496: e003 b.n 800a4a0 } else { /* Change the DMA state to Ready if DMA disable success */ hdma->State = HAL_DMA_STATE_READY; 800a498: 687b ldr r3, [r7, #4] 800a49a: 2201 movs r2, #1 800a49c: f883 2035 strb.w r2, [r3, #53] @ 0x35 } /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a4a0: 687b ldr r3, [r7, #4] 800a4a2: 2200 movs r2, #0 800a4a4: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 800a4a8: 687b ldr r3, [r7, #4] 800a4aa: 6cdb ldr r3, [r3, #76] @ 0x4c 800a4ac: 2b00 cmp r3, #0 800a4ae: f000 8272 beq.w 800a996 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800a4b2: 687b ldr r3, [r7, #4] 800a4b4: 6cdb ldr r3, [r3, #76] @ 0x4c 800a4b6: 6878 ldr r0, [r7, #4] 800a4b8: 4798 blx r3 800a4ba: e26c b.n 800a996 } } } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 800a4bc: 687b ldr r3, [r7, #4] 800a4be: 681b ldr r3, [r3, #0] 800a4c0: 4a43 ldr r2, [pc, #268] @ (800a5d0 ) 800a4c2: 4293 cmp r3, r2 800a4c4: d022 beq.n 800a50c 800a4c6: 687b ldr r3, [r7, #4] 800a4c8: 681b ldr r3, [r3, #0] 800a4ca: 4a42 ldr r2, [pc, #264] @ (800a5d4 ) 800a4cc: 4293 cmp r3, r2 800a4ce: d01d beq.n 800a50c 800a4d0: 687b ldr r3, [r7, #4] 800a4d2: 681b ldr r3, [r3, #0] 800a4d4: 4a40 ldr r2, [pc, #256] @ (800a5d8 ) 800a4d6: 4293 cmp r3, r2 800a4d8: d018 beq.n 800a50c 800a4da: 687b ldr r3, [r7, #4] 800a4dc: 681b ldr r3, [r3, #0] 800a4de: 4a3f ldr r2, [pc, #252] @ (800a5dc ) 800a4e0: 4293 cmp r3, r2 800a4e2: d013 beq.n 800a50c 800a4e4: 687b ldr r3, [r7, #4] 800a4e6: 681b ldr r3, [r3, #0] 800a4e8: 4a3d ldr r2, [pc, #244] @ (800a5e0 ) 800a4ea: 4293 cmp r3, r2 800a4ec: d00e beq.n 800a50c 800a4ee: 687b ldr r3, [r7, #4] 800a4f0: 681b ldr r3, [r3, #0] 800a4f2: 4a3c ldr r2, [pc, #240] @ (800a5e4 ) 800a4f4: 4293 cmp r3, r2 800a4f6: d009 beq.n 800a50c 800a4f8: 687b ldr r3, [r7, #4] 800a4fa: 681b ldr r3, [r3, #0] 800a4fc: 4a3a ldr r2, [pc, #232] @ (800a5e8 ) 800a4fe: 4293 cmp r3, r2 800a500: d004 beq.n 800a50c 800a502: 687b ldr r3, [r7, #4] 800a504: 681b ldr r3, [r3, #0] 800a506: 4a39 ldr r2, [pc, #228] @ (800a5ec ) 800a508: 4293 cmp r3, r2 800a50a: d101 bne.n 800a510 800a50c: 2301 movs r3, #1 800a50e: e000 b.n 800a512 800a510: 2300 movs r3, #0 800a512: 2b00 cmp r3, #0 800a514: f000 823f beq.w 800a996 { ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); 800a518: 687b ldr r3, [r7, #4] 800a51a: 681b ldr r3, [r3, #0] 800a51c: 681b ldr r3, [r3, #0] 800a51e: 613b str r3, [r7, #16] /* Half Transfer Complete Interrupt management ******************************/ if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) 800a520: 687b ldr r3, [r7, #4] 800a522: 6ddb ldr r3, [r3, #92] @ 0x5c 800a524: f003 031f and.w r3, r3, #31 800a528: 2204 movs r2, #4 800a52a: 409a lsls r2, r3 800a52c: 697b ldr r3, [r7, #20] 800a52e: 4013 ands r3, r2 800a530: 2b00 cmp r3, #0 800a532: f000 80cd beq.w 800a6d0 800a536: 693b ldr r3, [r7, #16] 800a538: f003 0304 and.w r3, r3, #4 800a53c: 2b00 cmp r3, #0 800a53e: f000 80c7 beq.w 800a6d0 { /* Clear the half transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); 800a542: 687b ldr r3, [r7, #4] 800a544: 6ddb ldr r3, [r3, #92] @ 0x5c 800a546: f003 031f and.w r3, r3, #31 800a54a: 2204 movs r2, #4 800a54c: 409a lsls r2, r3 800a54e: 69fb ldr r3, [r7, #28] 800a550: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a552: 693b ldr r3, [r7, #16] 800a554: f403 4300 and.w r3, r3, #32768 @ 0x8000 800a558: 2b00 cmp r3, #0 800a55a: d049 beq.n 800a5f0 { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 800a55c: 693b ldr r3, [r7, #16] 800a55e: f403 3380 and.w r3, r3, #65536 @ 0x10000 800a562: 2b00 cmp r3, #0 800a564: d109 bne.n 800a57a { if(hdma->XferM1HalfCpltCallback != NULL) 800a566: 687b ldr r3, [r7, #4] 800a568: 6c9b ldr r3, [r3, #72] @ 0x48 800a56a: 2b00 cmp r3, #0 800a56c: f000 8210 beq.w 800a990 { /* Half transfer Callback for Memory 1 */ hdma->XferM1HalfCpltCallback(hdma); 800a570: 687b ldr r3, [r7, #4] 800a572: 6c9b ldr r3, [r3, #72] @ 0x48 800a574: 6878 ldr r0, [r7, #4] 800a576: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a578: e20a b.n 800a990 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferHalfCpltCallback != NULL) 800a57a: 687b ldr r3, [r7, #4] 800a57c: 6c1b ldr r3, [r3, #64] @ 0x40 800a57e: 2b00 cmp r3, #0 800a580: f000 8206 beq.w 800a990 { /* Half transfer Callback for Memory 0 */ hdma->XferHalfCpltCallback(hdma); 800a584: 687b ldr r3, [r7, #4] 800a586: 6c1b ldr r3, [r3, #64] @ 0x40 800a588: 6878 ldr r0, [r7, #4] 800a58a: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a58c: e200 b.n 800a990 800a58e: bf00 nop 800a590: 40020010 .word 0x40020010 800a594: 40020028 .word 0x40020028 800a598: 40020040 .word 0x40020040 800a59c: 40020058 .word 0x40020058 800a5a0: 40020070 .word 0x40020070 800a5a4: 40020088 .word 0x40020088 800a5a8: 400200a0 .word 0x400200a0 800a5ac: 400200b8 .word 0x400200b8 800a5b0: 40020410 .word 0x40020410 800a5b4: 40020428 .word 0x40020428 800a5b8: 40020440 .word 0x40020440 800a5bc: 40020458 .word 0x40020458 800a5c0: 40020470 .word 0x40020470 800a5c4: 40020488 .word 0x40020488 800a5c8: 400204a0 .word 0x400204a0 800a5cc: 400204b8 .word 0x400204b8 800a5d0: 58025408 .word 0x58025408 800a5d4: 5802541c .word 0x5802541c 800a5d8: 58025430 .word 0x58025430 800a5dc: 58025444 .word 0x58025444 800a5e0: 58025458 .word 0x58025458 800a5e4: 5802546c .word 0x5802546c 800a5e8: 58025480 .word 0x58025480 800a5ec: 58025494 .word 0x58025494 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 800a5f0: 693b ldr r3, [r7, #16] 800a5f2: f003 0320 and.w r3, r3, #32 800a5f6: 2b00 cmp r3, #0 800a5f8: d160 bne.n 800a6bc { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800a5fa: 687b ldr r3, [r7, #4] 800a5fc: 681b ldr r3, [r3, #0] 800a5fe: 4a7f ldr r2, [pc, #508] @ (800a7fc ) 800a600: 4293 cmp r3, r2 800a602: d04a beq.n 800a69a 800a604: 687b ldr r3, [r7, #4] 800a606: 681b ldr r3, [r3, #0] 800a608: 4a7d ldr r2, [pc, #500] @ (800a800 ) 800a60a: 4293 cmp r3, r2 800a60c: d045 beq.n 800a69a 800a60e: 687b ldr r3, [r7, #4] 800a610: 681b ldr r3, [r3, #0] 800a612: 4a7c ldr r2, [pc, #496] @ (800a804 ) 800a614: 4293 cmp r3, r2 800a616: d040 beq.n 800a69a 800a618: 687b ldr r3, [r7, #4] 800a61a: 681b ldr r3, [r3, #0] 800a61c: 4a7a ldr r2, [pc, #488] @ (800a808 ) 800a61e: 4293 cmp r3, r2 800a620: d03b beq.n 800a69a 800a622: 687b ldr r3, [r7, #4] 800a624: 681b ldr r3, [r3, #0] 800a626: 4a79 ldr r2, [pc, #484] @ (800a80c ) 800a628: 4293 cmp r3, r2 800a62a: d036 beq.n 800a69a 800a62c: 687b ldr r3, [r7, #4] 800a62e: 681b ldr r3, [r3, #0] 800a630: 4a77 ldr r2, [pc, #476] @ (800a810 ) 800a632: 4293 cmp r3, r2 800a634: d031 beq.n 800a69a 800a636: 687b ldr r3, [r7, #4] 800a638: 681b ldr r3, [r3, #0] 800a63a: 4a76 ldr r2, [pc, #472] @ (800a814 ) 800a63c: 4293 cmp r3, r2 800a63e: d02c beq.n 800a69a 800a640: 687b ldr r3, [r7, #4] 800a642: 681b ldr r3, [r3, #0] 800a644: 4a74 ldr r2, [pc, #464] @ (800a818 ) 800a646: 4293 cmp r3, r2 800a648: d027 beq.n 800a69a 800a64a: 687b ldr r3, [r7, #4] 800a64c: 681b ldr r3, [r3, #0] 800a64e: 4a73 ldr r2, [pc, #460] @ (800a81c ) 800a650: 4293 cmp r3, r2 800a652: d022 beq.n 800a69a 800a654: 687b ldr r3, [r7, #4] 800a656: 681b ldr r3, [r3, #0] 800a658: 4a71 ldr r2, [pc, #452] @ (800a820 ) 800a65a: 4293 cmp r3, r2 800a65c: d01d beq.n 800a69a 800a65e: 687b ldr r3, [r7, #4] 800a660: 681b ldr r3, [r3, #0] 800a662: 4a70 ldr r2, [pc, #448] @ (800a824 ) 800a664: 4293 cmp r3, r2 800a666: d018 beq.n 800a69a 800a668: 687b ldr r3, [r7, #4] 800a66a: 681b ldr r3, [r3, #0] 800a66c: 4a6e ldr r2, [pc, #440] @ (800a828 ) 800a66e: 4293 cmp r3, r2 800a670: d013 beq.n 800a69a 800a672: 687b ldr r3, [r7, #4] 800a674: 681b ldr r3, [r3, #0] 800a676: 4a6d ldr r2, [pc, #436] @ (800a82c ) 800a678: 4293 cmp r3, r2 800a67a: d00e beq.n 800a69a 800a67c: 687b ldr r3, [r7, #4] 800a67e: 681b ldr r3, [r3, #0] 800a680: 4a6b ldr r2, [pc, #428] @ (800a830 ) 800a682: 4293 cmp r3, r2 800a684: d009 beq.n 800a69a 800a686: 687b ldr r3, [r7, #4] 800a688: 681b ldr r3, [r3, #0] 800a68a: 4a6a ldr r2, [pc, #424] @ (800a834 ) 800a68c: 4293 cmp r3, r2 800a68e: d004 beq.n 800a69a 800a690: 687b ldr r3, [r7, #4] 800a692: 681b ldr r3, [r3, #0] 800a694: 4a68 ldr r2, [pc, #416] @ (800a838 ) 800a696: 4293 cmp r3, r2 800a698: d108 bne.n 800a6ac 800a69a: 687b ldr r3, [r7, #4] 800a69c: 681b ldr r3, [r3, #0] 800a69e: 681a ldr r2, [r3, #0] 800a6a0: 687b ldr r3, [r7, #4] 800a6a2: 681b ldr r3, [r3, #0] 800a6a4: f022 0208 bic.w r2, r2, #8 800a6a8: 601a str r2, [r3, #0] 800a6aa: e007 b.n 800a6bc 800a6ac: 687b ldr r3, [r7, #4] 800a6ae: 681b ldr r3, [r3, #0] 800a6b0: 681a ldr r2, [r3, #0] 800a6b2: 687b ldr r3, [r7, #4] 800a6b4: 681b ldr r3, [r3, #0] 800a6b6: f022 0204 bic.w r2, r2, #4 800a6ba: 601a str r2, [r3, #0] } /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 800a6bc: 687b ldr r3, [r7, #4] 800a6be: 6c1b ldr r3, [r3, #64] @ 0x40 800a6c0: 2b00 cmp r3, #0 800a6c2: f000 8165 beq.w 800a990 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800a6c6: 687b ldr r3, [r7, #4] 800a6c8: 6c1b ldr r3, [r3, #64] @ 0x40 800a6ca: 6878 ldr r0, [r7, #4] 800a6cc: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a6ce: e15f b.n 800a990 } } } /* Transfer Complete Interrupt management ***********************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) 800a6d0: 687b ldr r3, [r7, #4] 800a6d2: 6ddb ldr r3, [r3, #92] @ 0x5c 800a6d4: f003 031f and.w r3, r3, #31 800a6d8: 2202 movs r2, #2 800a6da: 409a lsls r2, r3 800a6dc: 697b ldr r3, [r7, #20] 800a6de: 4013 ands r3, r2 800a6e0: 2b00 cmp r3, #0 800a6e2: f000 80c5 beq.w 800a870 800a6e6: 693b ldr r3, [r7, #16] 800a6e8: f003 0302 and.w r3, r3, #2 800a6ec: 2b00 cmp r3, #0 800a6ee: f000 80bf beq.w 800a870 { /* Clear the transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); 800a6f2: 687b ldr r3, [r7, #4] 800a6f4: 6ddb ldr r3, [r3, #92] @ 0x5c 800a6f6: f003 031f and.w r3, r3, #31 800a6fa: 2202 movs r2, #2 800a6fc: 409a lsls r2, r3 800a6fe: 69fb ldr r3, [r7, #28] 800a700: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a702: 693b ldr r3, [r7, #16] 800a704: f403 4300 and.w r3, r3, #32768 @ 0x8000 800a708: 2b00 cmp r3, #0 800a70a: d018 beq.n 800a73e { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 800a70c: 693b ldr r3, [r7, #16] 800a70e: f403 3380 and.w r3, r3, #65536 @ 0x10000 800a712: 2b00 cmp r3, #0 800a714: d109 bne.n 800a72a { if(hdma->XferM1CpltCallback != NULL) 800a716: 687b ldr r3, [r7, #4] 800a718: 6c5b ldr r3, [r3, #68] @ 0x44 800a71a: 2b00 cmp r3, #0 800a71c: f000 813a beq.w 800a994 { /* Transfer complete Callback for Memory 1 */ hdma->XferM1CpltCallback(hdma); 800a720: 687b ldr r3, [r7, #4] 800a722: 6c5b ldr r3, [r3, #68] @ 0x44 800a724: 6878 ldr r0, [r7, #4] 800a726: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a728: e134 b.n 800a994 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800a72a: 687b ldr r3, [r7, #4] 800a72c: 6bdb ldr r3, [r3, #60] @ 0x3c 800a72e: 2b00 cmp r3, #0 800a730: f000 8130 beq.w 800a994 { /* Transfer complete Callback for Memory 0 */ hdma->XferCpltCallback(hdma); 800a734: 687b ldr r3, [r7, #4] 800a736: 6bdb ldr r3, [r3, #60] @ 0x3c 800a738: 6878 ldr r0, [r7, #4] 800a73a: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a73c: e12a b.n 800a994 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 800a73e: 693b ldr r3, [r7, #16] 800a740: f003 0320 and.w r3, r3, #32 800a744: 2b00 cmp r3, #0 800a746: f040 8089 bne.w 800a85c { /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 800a74a: 687b ldr r3, [r7, #4] 800a74c: 681b ldr r3, [r3, #0] 800a74e: 4a2b ldr r2, [pc, #172] @ (800a7fc ) 800a750: 4293 cmp r3, r2 800a752: d04a beq.n 800a7ea 800a754: 687b ldr r3, [r7, #4] 800a756: 681b ldr r3, [r3, #0] 800a758: 4a29 ldr r2, [pc, #164] @ (800a800 ) 800a75a: 4293 cmp r3, r2 800a75c: d045 beq.n 800a7ea 800a75e: 687b ldr r3, [r7, #4] 800a760: 681b ldr r3, [r3, #0] 800a762: 4a28 ldr r2, [pc, #160] @ (800a804 ) 800a764: 4293 cmp r3, r2 800a766: d040 beq.n 800a7ea 800a768: 687b ldr r3, [r7, #4] 800a76a: 681b ldr r3, [r3, #0] 800a76c: 4a26 ldr r2, [pc, #152] @ (800a808 ) 800a76e: 4293 cmp r3, r2 800a770: d03b beq.n 800a7ea 800a772: 687b ldr r3, [r7, #4] 800a774: 681b ldr r3, [r3, #0] 800a776: 4a25 ldr r2, [pc, #148] @ (800a80c ) 800a778: 4293 cmp r3, r2 800a77a: d036 beq.n 800a7ea 800a77c: 687b ldr r3, [r7, #4] 800a77e: 681b ldr r3, [r3, #0] 800a780: 4a23 ldr r2, [pc, #140] @ (800a810 ) 800a782: 4293 cmp r3, r2 800a784: d031 beq.n 800a7ea 800a786: 687b ldr r3, [r7, #4] 800a788: 681b ldr r3, [r3, #0] 800a78a: 4a22 ldr r2, [pc, #136] @ (800a814 ) 800a78c: 4293 cmp r3, r2 800a78e: d02c beq.n 800a7ea 800a790: 687b ldr r3, [r7, #4] 800a792: 681b ldr r3, [r3, #0] 800a794: 4a20 ldr r2, [pc, #128] @ (800a818 ) 800a796: 4293 cmp r3, r2 800a798: d027 beq.n 800a7ea 800a79a: 687b ldr r3, [r7, #4] 800a79c: 681b ldr r3, [r3, #0] 800a79e: 4a1f ldr r2, [pc, #124] @ (800a81c ) 800a7a0: 4293 cmp r3, r2 800a7a2: d022 beq.n 800a7ea 800a7a4: 687b ldr r3, [r7, #4] 800a7a6: 681b ldr r3, [r3, #0] 800a7a8: 4a1d ldr r2, [pc, #116] @ (800a820 ) 800a7aa: 4293 cmp r3, r2 800a7ac: d01d beq.n 800a7ea 800a7ae: 687b ldr r3, [r7, #4] 800a7b0: 681b ldr r3, [r3, #0] 800a7b2: 4a1c ldr r2, [pc, #112] @ (800a824 ) 800a7b4: 4293 cmp r3, r2 800a7b6: d018 beq.n 800a7ea 800a7b8: 687b ldr r3, [r7, #4] 800a7ba: 681b ldr r3, [r3, #0] 800a7bc: 4a1a ldr r2, [pc, #104] @ (800a828 ) 800a7be: 4293 cmp r3, r2 800a7c0: d013 beq.n 800a7ea 800a7c2: 687b ldr r3, [r7, #4] 800a7c4: 681b ldr r3, [r3, #0] 800a7c6: 4a19 ldr r2, [pc, #100] @ (800a82c ) 800a7c8: 4293 cmp r3, r2 800a7ca: d00e beq.n 800a7ea 800a7cc: 687b ldr r3, [r7, #4] 800a7ce: 681b ldr r3, [r3, #0] 800a7d0: 4a17 ldr r2, [pc, #92] @ (800a830 ) 800a7d2: 4293 cmp r3, r2 800a7d4: d009 beq.n 800a7ea 800a7d6: 687b ldr r3, [r7, #4] 800a7d8: 681b ldr r3, [r3, #0] 800a7da: 4a16 ldr r2, [pc, #88] @ (800a834 ) 800a7dc: 4293 cmp r3, r2 800a7de: d004 beq.n 800a7ea 800a7e0: 687b ldr r3, [r7, #4] 800a7e2: 681b ldr r3, [r3, #0] 800a7e4: 4a14 ldr r2, [pc, #80] @ (800a838 ) 800a7e6: 4293 cmp r3, r2 800a7e8: d128 bne.n 800a83c 800a7ea: 687b ldr r3, [r7, #4] 800a7ec: 681b ldr r3, [r3, #0] 800a7ee: 681a ldr r2, [r3, #0] 800a7f0: 687b ldr r3, [r7, #4] 800a7f2: 681b ldr r3, [r3, #0] 800a7f4: f022 0214 bic.w r2, r2, #20 800a7f8: 601a str r2, [r3, #0] 800a7fa: e027 b.n 800a84c 800a7fc: 40020010 .word 0x40020010 800a800: 40020028 .word 0x40020028 800a804: 40020040 .word 0x40020040 800a808: 40020058 .word 0x40020058 800a80c: 40020070 .word 0x40020070 800a810: 40020088 .word 0x40020088 800a814: 400200a0 .word 0x400200a0 800a818: 400200b8 .word 0x400200b8 800a81c: 40020410 .word 0x40020410 800a820: 40020428 .word 0x40020428 800a824: 40020440 .word 0x40020440 800a828: 40020458 .word 0x40020458 800a82c: 40020470 .word 0x40020470 800a830: 40020488 .word 0x40020488 800a834: 400204a0 .word 0x400204a0 800a838: 400204b8 .word 0x400204b8 800a83c: 687b ldr r3, [r7, #4] 800a83e: 681b ldr r3, [r3, #0] 800a840: 681a ldr r2, [r3, #0] 800a842: 687b ldr r3, [r7, #4] 800a844: 681b ldr r3, [r3, #0] 800a846: f022 020a bic.w r2, r2, #10 800a84a: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a84c: 687b ldr r3, [r7, #4] 800a84e: 2201 movs r2, #1 800a850: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a854: 687b ldr r3, [r7, #4] 800a856: 2200 movs r2, #0 800a858: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 800a85c: 687b ldr r3, [r7, #4] 800a85e: 6bdb ldr r3, [r3, #60] @ 0x3c 800a860: 2b00 cmp r3, #0 800a862: f000 8097 beq.w 800a994 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 800a866: 687b ldr r3, [r7, #4] 800a868: 6bdb ldr r3, [r3, #60] @ 0x3c 800a86a: 6878 ldr r0, [r7, #4] 800a86c: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a86e: e091 b.n 800a994 } } } /* Transfer Error Interrupt management **************************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) 800a870: 687b ldr r3, [r7, #4] 800a872: 6ddb ldr r3, [r3, #92] @ 0x5c 800a874: f003 031f and.w r3, r3, #31 800a878: 2208 movs r2, #8 800a87a: 409a lsls r2, r3 800a87c: 697b ldr r3, [r7, #20] 800a87e: 4013 ands r3, r2 800a880: 2b00 cmp r3, #0 800a882: f000 8088 beq.w 800a996 800a886: 693b ldr r3, [r7, #16] 800a888: f003 0308 and.w r3, r3, #8 800a88c: 2b00 cmp r3, #0 800a88e: f000 8082 beq.w 800a996 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800a892: 687b ldr r3, [r7, #4] 800a894: 681b ldr r3, [r3, #0] 800a896: 4a41 ldr r2, [pc, #260] @ (800a99c ) 800a898: 4293 cmp r3, r2 800a89a: d04a beq.n 800a932 800a89c: 687b ldr r3, [r7, #4] 800a89e: 681b ldr r3, [r3, #0] 800a8a0: 4a3f ldr r2, [pc, #252] @ (800a9a0 ) 800a8a2: 4293 cmp r3, r2 800a8a4: d045 beq.n 800a932 800a8a6: 687b ldr r3, [r7, #4] 800a8a8: 681b ldr r3, [r3, #0] 800a8aa: 4a3e ldr r2, [pc, #248] @ (800a9a4 ) 800a8ac: 4293 cmp r3, r2 800a8ae: d040 beq.n 800a932 800a8b0: 687b ldr r3, [r7, #4] 800a8b2: 681b ldr r3, [r3, #0] 800a8b4: 4a3c ldr r2, [pc, #240] @ (800a9a8 ) 800a8b6: 4293 cmp r3, r2 800a8b8: d03b beq.n 800a932 800a8ba: 687b ldr r3, [r7, #4] 800a8bc: 681b ldr r3, [r3, #0] 800a8be: 4a3b ldr r2, [pc, #236] @ (800a9ac ) 800a8c0: 4293 cmp r3, r2 800a8c2: d036 beq.n 800a932 800a8c4: 687b ldr r3, [r7, #4] 800a8c6: 681b ldr r3, [r3, #0] 800a8c8: 4a39 ldr r2, [pc, #228] @ (800a9b0 ) 800a8ca: 4293 cmp r3, r2 800a8cc: d031 beq.n 800a932 800a8ce: 687b ldr r3, [r7, #4] 800a8d0: 681b ldr r3, [r3, #0] 800a8d2: 4a38 ldr r2, [pc, #224] @ (800a9b4 ) 800a8d4: 4293 cmp r3, r2 800a8d6: d02c beq.n 800a932 800a8d8: 687b ldr r3, [r7, #4] 800a8da: 681b ldr r3, [r3, #0] 800a8dc: 4a36 ldr r2, [pc, #216] @ (800a9b8 ) 800a8de: 4293 cmp r3, r2 800a8e0: d027 beq.n 800a932 800a8e2: 687b ldr r3, [r7, #4] 800a8e4: 681b ldr r3, [r3, #0] 800a8e6: 4a35 ldr r2, [pc, #212] @ (800a9bc ) 800a8e8: 4293 cmp r3, r2 800a8ea: d022 beq.n 800a932 800a8ec: 687b ldr r3, [r7, #4] 800a8ee: 681b ldr r3, [r3, #0] 800a8f0: 4a33 ldr r2, [pc, #204] @ (800a9c0 ) 800a8f2: 4293 cmp r3, r2 800a8f4: d01d beq.n 800a932 800a8f6: 687b ldr r3, [r7, #4] 800a8f8: 681b ldr r3, [r3, #0] 800a8fa: 4a32 ldr r2, [pc, #200] @ (800a9c4 ) 800a8fc: 4293 cmp r3, r2 800a8fe: d018 beq.n 800a932 800a900: 687b ldr r3, [r7, #4] 800a902: 681b ldr r3, [r3, #0] 800a904: 4a30 ldr r2, [pc, #192] @ (800a9c8 ) 800a906: 4293 cmp r3, r2 800a908: d013 beq.n 800a932 800a90a: 687b ldr r3, [r7, #4] 800a90c: 681b ldr r3, [r3, #0] 800a90e: 4a2f ldr r2, [pc, #188] @ (800a9cc ) 800a910: 4293 cmp r3, r2 800a912: d00e beq.n 800a932 800a914: 687b ldr r3, [r7, #4] 800a916: 681b ldr r3, [r3, #0] 800a918: 4a2d ldr r2, [pc, #180] @ (800a9d0 ) 800a91a: 4293 cmp r3, r2 800a91c: d009 beq.n 800a932 800a91e: 687b ldr r3, [r7, #4] 800a920: 681b ldr r3, [r3, #0] 800a922: 4a2c ldr r2, [pc, #176] @ (800a9d4 ) 800a924: 4293 cmp r3, r2 800a926: d004 beq.n 800a932 800a928: 687b ldr r3, [r7, #4] 800a92a: 681b ldr r3, [r3, #0] 800a92c: 4a2a ldr r2, [pc, #168] @ (800a9d8 ) 800a92e: 4293 cmp r3, r2 800a930: d108 bne.n 800a944 800a932: 687b ldr r3, [r7, #4] 800a934: 681b ldr r3, [r3, #0] 800a936: 681a ldr r2, [r3, #0] 800a938: 687b ldr r3, [r7, #4] 800a93a: 681b ldr r3, [r3, #0] 800a93c: f022 021c bic.w r2, r2, #28 800a940: 601a str r2, [r3, #0] 800a942: e007 b.n 800a954 800a944: 687b ldr r3, [r7, #4] 800a946: 681b ldr r3, [r3, #0] 800a948: 681a ldr r2, [r3, #0] 800a94a: 687b ldr r3, [r7, #4] 800a94c: 681b ldr r3, [r3, #0] 800a94e: f022 020e bic.w r2, r2, #14 800a952: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 800a954: 687b ldr r3, [r7, #4] 800a956: 6ddb ldr r3, [r3, #92] @ 0x5c 800a958: f003 031f and.w r3, r3, #31 800a95c: 2201 movs r2, #1 800a95e: 409a lsls r2, r3 800a960: 69fb ldr r3, [r7, #28] 800a962: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 800a964: 687b ldr r3, [r7, #4] 800a966: 2201 movs r2, #1 800a968: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a96a: 687b ldr r3, [r7, #4] 800a96c: 2201 movs r2, #1 800a96e: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a972: 687b ldr r3, [r7, #4] 800a974: 2200 movs r2, #0 800a976: f883 2034 strb.w r2, [r3, #52] @ 0x34 if (hdma->XferErrorCallback != NULL) 800a97a: 687b ldr r3, [r7, #4] 800a97c: 6cdb ldr r3, [r3, #76] @ 0x4c 800a97e: 2b00 cmp r3, #0 800a980: d009 beq.n 800a996 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800a982: 687b ldr r3, [r7, #4] 800a984: 6cdb ldr r3, [r3, #76] @ 0x4c 800a986: 6878 ldr r0, [r7, #4] 800a988: 4798 blx r3 800a98a: e004 b.n 800a996 return; 800a98c: bf00 nop 800a98e: e002 b.n 800a996 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a990: bf00 nop 800a992: e000 b.n 800a996 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a994: bf00 nop } else { /* Nothing To Do */ } } 800a996: 3728 adds r7, #40 @ 0x28 800a998: 46bd mov sp, r7 800a99a: bd80 pop {r7, pc} 800a99c: 40020010 .word 0x40020010 800a9a0: 40020028 .word 0x40020028 800a9a4: 40020040 .word 0x40020040 800a9a8: 40020058 .word 0x40020058 800a9ac: 40020070 .word 0x40020070 800a9b0: 40020088 .word 0x40020088 800a9b4: 400200a0 .word 0x400200a0 800a9b8: 400200b8 .word 0x400200b8 800a9bc: 40020410 .word 0x40020410 800a9c0: 40020428 .word 0x40020428 800a9c4: 40020440 .word 0x40020440 800a9c8: 40020458 .word 0x40020458 800a9cc: 40020470 .word 0x40020470 800a9d0: 40020488 .word 0x40020488 800a9d4: 400204a0 .word 0x400204a0 800a9d8: 400204b8 .word 0x400204b8 0800a9dc : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval None */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 800a9dc: b480 push {r7} 800a9de: b087 sub sp, #28 800a9e0: af00 add r7, sp, #0 800a9e2: 60f8 str r0, [r7, #12] 800a9e4: 60b9 str r1, [r7, #8] 800a9e6: 607a str r2, [r7, #4] 800a9e8: 603b str r3, [r7, #0] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 800a9ea: 68fb ldr r3, [r7, #12] 800a9ec: 6d9b ldr r3, [r3, #88] @ 0x58 800a9ee: 617b str r3, [r7, #20] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 800a9f0: 68fb ldr r3, [r7, #12] 800a9f2: 6d9b ldr r3, [r3, #88] @ 0x58 800a9f4: 613b str r3, [r7, #16] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800a9f6: 68fb ldr r3, [r7, #12] 800a9f8: 681b ldr r3, [r3, #0] 800a9fa: 4a7f ldr r2, [pc, #508] @ (800abf8 ) 800a9fc: 4293 cmp r3, r2 800a9fe: d072 beq.n 800aae6 800aa00: 68fb ldr r3, [r7, #12] 800aa02: 681b ldr r3, [r3, #0] 800aa04: 4a7d ldr r2, [pc, #500] @ (800abfc ) 800aa06: 4293 cmp r3, r2 800aa08: d06d beq.n 800aae6 800aa0a: 68fb ldr r3, [r7, #12] 800aa0c: 681b ldr r3, [r3, #0] 800aa0e: 4a7c ldr r2, [pc, #496] @ (800ac00 ) 800aa10: 4293 cmp r3, r2 800aa12: d068 beq.n 800aae6 800aa14: 68fb ldr r3, [r7, #12] 800aa16: 681b ldr r3, [r3, #0] 800aa18: 4a7a ldr r2, [pc, #488] @ (800ac04 ) 800aa1a: 4293 cmp r3, r2 800aa1c: d063 beq.n 800aae6 800aa1e: 68fb ldr r3, [r7, #12] 800aa20: 681b ldr r3, [r3, #0] 800aa22: 4a79 ldr r2, [pc, #484] @ (800ac08 ) 800aa24: 4293 cmp r3, r2 800aa26: d05e beq.n 800aae6 800aa28: 68fb ldr r3, [r7, #12] 800aa2a: 681b ldr r3, [r3, #0] 800aa2c: 4a77 ldr r2, [pc, #476] @ (800ac0c ) 800aa2e: 4293 cmp r3, r2 800aa30: d059 beq.n 800aae6 800aa32: 68fb ldr r3, [r7, #12] 800aa34: 681b ldr r3, [r3, #0] 800aa36: 4a76 ldr r2, [pc, #472] @ (800ac10 ) 800aa38: 4293 cmp r3, r2 800aa3a: d054 beq.n 800aae6 800aa3c: 68fb ldr r3, [r7, #12] 800aa3e: 681b ldr r3, [r3, #0] 800aa40: 4a74 ldr r2, [pc, #464] @ (800ac14 ) 800aa42: 4293 cmp r3, r2 800aa44: d04f beq.n 800aae6 800aa46: 68fb ldr r3, [r7, #12] 800aa48: 681b ldr r3, [r3, #0] 800aa4a: 4a73 ldr r2, [pc, #460] @ (800ac18 ) 800aa4c: 4293 cmp r3, r2 800aa4e: d04a beq.n 800aae6 800aa50: 68fb ldr r3, [r7, #12] 800aa52: 681b ldr r3, [r3, #0] 800aa54: 4a71 ldr r2, [pc, #452] @ (800ac1c ) 800aa56: 4293 cmp r3, r2 800aa58: d045 beq.n 800aae6 800aa5a: 68fb ldr r3, [r7, #12] 800aa5c: 681b ldr r3, [r3, #0] 800aa5e: 4a70 ldr r2, [pc, #448] @ (800ac20 ) 800aa60: 4293 cmp r3, r2 800aa62: d040 beq.n 800aae6 800aa64: 68fb ldr r3, [r7, #12] 800aa66: 681b ldr r3, [r3, #0] 800aa68: 4a6e ldr r2, [pc, #440] @ (800ac24 ) 800aa6a: 4293 cmp r3, r2 800aa6c: d03b beq.n 800aae6 800aa6e: 68fb ldr r3, [r7, #12] 800aa70: 681b ldr r3, [r3, #0] 800aa72: 4a6d ldr r2, [pc, #436] @ (800ac28 ) 800aa74: 4293 cmp r3, r2 800aa76: d036 beq.n 800aae6 800aa78: 68fb ldr r3, [r7, #12] 800aa7a: 681b ldr r3, [r3, #0] 800aa7c: 4a6b ldr r2, [pc, #428] @ (800ac2c ) 800aa7e: 4293 cmp r3, r2 800aa80: d031 beq.n 800aae6 800aa82: 68fb ldr r3, [r7, #12] 800aa84: 681b ldr r3, [r3, #0] 800aa86: 4a6a ldr r2, [pc, #424] @ (800ac30 ) 800aa88: 4293 cmp r3, r2 800aa8a: d02c beq.n 800aae6 800aa8c: 68fb ldr r3, [r7, #12] 800aa8e: 681b ldr r3, [r3, #0] 800aa90: 4a68 ldr r2, [pc, #416] @ (800ac34 ) 800aa92: 4293 cmp r3, r2 800aa94: d027 beq.n 800aae6 800aa96: 68fb ldr r3, [r7, #12] 800aa98: 681b ldr r3, [r3, #0] 800aa9a: 4a67 ldr r2, [pc, #412] @ (800ac38 ) 800aa9c: 4293 cmp r3, r2 800aa9e: d022 beq.n 800aae6 800aaa0: 68fb ldr r3, [r7, #12] 800aaa2: 681b ldr r3, [r3, #0] 800aaa4: 4a65 ldr r2, [pc, #404] @ (800ac3c ) 800aaa6: 4293 cmp r3, r2 800aaa8: d01d beq.n 800aae6 800aaaa: 68fb ldr r3, [r7, #12] 800aaac: 681b ldr r3, [r3, #0] 800aaae: 4a64 ldr r2, [pc, #400] @ (800ac40 ) 800aab0: 4293 cmp r3, r2 800aab2: d018 beq.n 800aae6 800aab4: 68fb ldr r3, [r7, #12] 800aab6: 681b ldr r3, [r3, #0] 800aab8: 4a62 ldr r2, [pc, #392] @ (800ac44 ) 800aaba: 4293 cmp r3, r2 800aabc: d013 beq.n 800aae6 800aabe: 68fb ldr r3, [r7, #12] 800aac0: 681b ldr r3, [r3, #0] 800aac2: 4a61 ldr r2, [pc, #388] @ (800ac48 ) 800aac4: 4293 cmp r3, r2 800aac6: d00e beq.n 800aae6 800aac8: 68fb ldr r3, [r7, #12] 800aaca: 681b ldr r3, [r3, #0] 800aacc: 4a5f ldr r2, [pc, #380] @ (800ac4c ) 800aace: 4293 cmp r3, r2 800aad0: d009 beq.n 800aae6 800aad2: 68fb ldr r3, [r7, #12] 800aad4: 681b ldr r3, [r3, #0] 800aad6: 4a5e ldr r2, [pc, #376] @ (800ac50 ) 800aad8: 4293 cmp r3, r2 800aada: d004 beq.n 800aae6 800aadc: 68fb ldr r3, [r7, #12] 800aade: 681b ldr r3, [r3, #0] 800aae0: 4a5c ldr r2, [pc, #368] @ (800ac54 ) 800aae2: 4293 cmp r3, r2 800aae4: d101 bne.n 800aaea 800aae6: 2301 movs r3, #1 800aae8: e000 b.n 800aaec 800aaea: 2300 movs r3, #0 800aaec: 2b00 cmp r3, #0 800aaee: d00d beq.n 800ab0c { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 800aaf0: 68fb ldr r3, [r7, #12] 800aaf2: 6e5b ldr r3, [r3, #100] @ 0x64 800aaf4: 68fa ldr r2, [r7, #12] 800aaf6: 6e92 ldr r2, [r2, #104] @ 0x68 800aaf8: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 800aafa: 68fb ldr r3, [r7, #12] 800aafc: 6edb ldr r3, [r3, #108] @ 0x6c 800aafe: 2b00 cmp r3, #0 800ab00: d004 beq.n 800ab0c { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 800ab02: 68fb ldr r3, [r7, #12] 800ab04: 6f1b ldr r3, [r3, #112] @ 0x70 800ab06: 68fa ldr r2, [r7, #12] 800ab08: 6f52 ldr r2, [r2, #116] @ 0x74 800ab0a: 605a str r2, [r3, #4] } } if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800ab0c: 68fb ldr r3, [r7, #12] 800ab0e: 681b ldr r3, [r3, #0] 800ab10: 4a39 ldr r2, [pc, #228] @ (800abf8 ) 800ab12: 4293 cmp r3, r2 800ab14: d04a beq.n 800abac 800ab16: 68fb ldr r3, [r7, #12] 800ab18: 681b ldr r3, [r3, #0] 800ab1a: 4a38 ldr r2, [pc, #224] @ (800abfc ) 800ab1c: 4293 cmp r3, r2 800ab1e: d045 beq.n 800abac 800ab20: 68fb ldr r3, [r7, #12] 800ab22: 681b ldr r3, [r3, #0] 800ab24: 4a36 ldr r2, [pc, #216] @ (800ac00 ) 800ab26: 4293 cmp r3, r2 800ab28: d040 beq.n 800abac 800ab2a: 68fb ldr r3, [r7, #12] 800ab2c: 681b ldr r3, [r3, #0] 800ab2e: 4a35 ldr r2, [pc, #212] @ (800ac04 ) 800ab30: 4293 cmp r3, r2 800ab32: d03b beq.n 800abac 800ab34: 68fb ldr r3, [r7, #12] 800ab36: 681b ldr r3, [r3, #0] 800ab38: 4a33 ldr r2, [pc, #204] @ (800ac08 ) 800ab3a: 4293 cmp r3, r2 800ab3c: d036 beq.n 800abac 800ab3e: 68fb ldr r3, [r7, #12] 800ab40: 681b ldr r3, [r3, #0] 800ab42: 4a32 ldr r2, [pc, #200] @ (800ac0c ) 800ab44: 4293 cmp r3, r2 800ab46: d031 beq.n 800abac 800ab48: 68fb ldr r3, [r7, #12] 800ab4a: 681b ldr r3, [r3, #0] 800ab4c: 4a30 ldr r2, [pc, #192] @ (800ac10 ) 800ab4e: 4293 cmp r3, r2 800ab50: d02c beq.n 800abac 800ab52: 68fb ldr r3, [r7, #12] 800ab54: 681b ldr r3, [r3, #0] 800ab56: 4a2f ldr r2, [pc, #188] @ (800ac14 ) 800ab58: 4293 cmp r3, r2 800ab5a: d027 beq.n 800abac 800ab5c: 68fb ldr r3, [r7, #12] 800ab5e: 681b ldr r3, [r3, #0] 800ab60: 4a2d ldr r2, [pc, #180] @ (800ac18 ) 800ab62: 4293 cmp r3, r2 800ab64: d022 beq.n 800abac 800ab66: 68fb ldr r3, [r7, #12] 800ab68: 681b ldr r3, [r3, #0] 800ab6a: 4a2c ldr r2, [pc, #176] @ (800ac1c ) 800ab6c: 4293 cmp r3, r2 800ab6e: d01d beq.n 800abac 800ab70: 68fb ldr r3, [r7, #12] 800ab72: 681b ldr r3, [r3, #0] 800ab74: 4a2a ldr r2, [pc, #168] @ (800ac20 ) 800ab76: 4293 cmp r3, r2 800ab78: d018 beq.n 800abac 800ab7a: 68fb ldr r3, [r7, #12] 800ab7c: 681b ldr r3, [r3, #0] 800ab7e: 4a29 ldr r2, [pc, #164] @ (800ac24 ) 800ab80: 4293 cmp r3, r2 800ab82: d013 beq.n 800abac 800ab84: 68fb ldr r3, [r7, #12] 800ab86: 681b ldr r3, [r3, #0] 800ab88: 4a27 ldr r2, [pc, #156] @ (800ac28 ) 800ab8a: 4293 cmp r3, r2 800ab8c: d00e beq.n 800abac 800ab8e: 68fb ldr r3, [r7, #12] 800ab90: 681b ldr r3, [r3, #0] 800ab92: 4a26 ldr r2, [pc, #152] @ (800ac2c ) 800ab94: 4293 cmp r3, r2 800ab96: d009 beq.n 800abac 800ab98: 68fb ldr r3, [r7, #12] 800ab9a: 681b ldr r3, [r3, #0] 800ab9c: 4a24 ldr r2, [pc, #144] @ (800ac30 ) 800ab9e: 4293 cmp r3, r2 800aba0: d004 beq.n 800abac 800aba2: 68fb ldr r3, [r7, #12] 800aba4: 681b ldr r3, [r3, #0] 800aba6: 4a23 ldr r2, [pc, #140] @ (800ac34 ) 800aba8: 4293 cmp r3, r2 800abaa: d101 bne.n 800abb0 800abac: 2301 movs r3, #1 800abae: e000 b.n 800abb2 800abb0: 2300 movs r3, #0 800abb2: 2b00 cmp r3, #0 800abb4: d059 beq.n 800ac6a { /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800abb6: 68fb ldr r3, [r7, #12] 800abb8: 6ddb ldr r3, [r3, #92] @ 0x5c 800abba: f003 031f and.w r3, r3, #31 800abbe: 223f movs r2, #63 @ 0x3f 800abc0: 409a lsls r2, r3 800abc2: 697b ldr r3, [r7, #20] 800abc4: 609a str r2, [r3, #8] /* Clear DBM bit */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM); 800abc6: 68fb ldr r3, [r7, #12] 800abc8: 681b ldr r3, [r3, #0] 800abca: 681a ldr r2, [r3, #0] 800abcc: 68fb ldr r3, [r7, #12] 800abce: 681b ldr r3, [r3, #0] 800abd0: f422 2280 bic.w r2, r2, #262144 @ 0x40000 800abd4: 601a str r2, [r3, #0] /* Configure DMA Stream data length */ ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; 800abd6: 68fb ldr r3, [r7, #12] 800abd8: 681b ldr r3, [r3, #0] 800abda: 683a ldr r2, [r7, #0] 800abdc: 605a str r2, [r3, #4] /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800abde: 68fb ldr r3, [r7, #12] 800abe0: 689b ldr r3, [r3, #8] 800abe2: 2b40 cmp r3, #64 @ 0x40 800abe4: d138 bne.n 800ac58 { /* Configure DMA Stream destination address */ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; 800abe6: 68fb ldr r3, [r7, #12] 800abe8: 681b ldr r3, [r3, #0] 800abea: 687a ldr r2, [r7, #4] 800abec: 609a str r2, [r3, #8] /* Configure DMA Stream source address */ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; 800abee: 68fb ldr r3, [r7, #12] 800abf0: 681b ldr r3, [r3, #0] 800abf2: 68ba ldr r2, [r7, #8] 800abf4: 60da str r2, [r3, #12] } else { /* Nothing To Do */ } } 800abf6: e086 b.n 800ad06 800abf8: 40020010 .word 0x40020010 800abfc: 40020028 .word 0x40020028 800ac00: 40020040 .word 0x40020040 800ac04: 40020058 .word 0x40020058 800ac08: 40020070 .word 0x40020070 800ac0c: 40020088 .word 0x40020088 800ac10: 400200a0 .word 0x400200a0 800ac14: 400200b8 .word 0x400200b8 800ac18: 40020410 .word 0x40020410 800ac1c: 40020428 .word 0x40020428 800ac20: 40020440 .word 0x40020440 800ac24: 40020458 .word 0x40020458 800ac28: 40020470 .word 0x40020470 800ac2c: 40020488 .word 0x40020488 800ac30: 400204a0 .word 0x400204a0 800ac34: 400204b8 .word 0x400204b8 800ac38: 58025408 .word 0x58025408 800ac3c: 5802541c .word 0x5802541c 800ac40: 58025430 .word 0x58025430 800ac44: 58025444 .word 0x58025444 800ac48: 58025458 .word 0x58025458 800ac4c: 5802546c .word 0x5802546c 800ac50: 58025480 .word 0x58025480 800ac54: 58025494 .word 0x58025494 ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; 800ac58: 68fb ldr r3, [r7, #12] 800ac5a: 681b ldr r3, [r3, #0] 800ac5c: 68ba ldr r2, [r7, #8] 800ac5e: 609a str r2, [r3, #8] ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; 800ac60: 68fb ldr r3, [r7, #12] 800ac62: 681b ldr r3, [r3, #0] 800ac64: 687a ldr r2, [r7, #4] 800ac66: 60da str r2, [r3, #12] } 800ac68: e04d b.n 800ad06 else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 800ac6a: 68fb ldr r3, [r7, #12] 800ac6c: 681b ldr r3, [r3, #0] 800ac6e: 4a29 ldr r2, [pc, #164] @ (800ad14 ) 800ac70: 4293 cmp r3, r2 800ac72: d022 beq.n 800acba 800ac74: 68fb ldr r3, [r7, #12] 800ac76: 681b ldr r3, [r3, #0] 800ac78: 4a27 ldr r2, [pc, #156] @ (800ad18 ) 800ac7a: 4293 cmp r3, r2 800ac7c: d01d beq.n 800acba 800ac7e: 68fb ldr r3, [r7, #12] 800ac80: 681b ldr r3, [r3, #0] 800ac82: 4a26 ldr r2, [pc, #152] @ (800ad1c ) 800ac84: 4293 cmp r3, r2 800ac86: d018 beq.n 800acba 800ac88: 68fb ldr r3, [r7, #12] 800ac8a: 681b ldr r3, [r3, #0] 800ac8c: 4a24 ldr r2, [pc, #144] @ (800ad20 ) 800ac8e: 4293 cmp r3, r2 800ac90: d013 beq.n 800acba 800ac92: 68fb ldr r3, [r7, #12] 800ac94: 681b ldr r3, [r3, #0] 800ac96: 4a23 ldr r2, [pc, #140] @ (800ad24 ) 800ac98: 4293 cmp r3, r2 800ac9a: d00e beq.n 800acba 800ac9c: 68fb ldr r3, [r7, #12] 800ac9e: 681b ldr r3, [r3, #0] 800aca0: 4a21 ldr r2, [pc, #132] @ (800ad28 ) 800aca2: 4293 cmp r3, r2 800aca4: d009 beq.n 800acba 800aca6: 68fb ldr r3, [r7, #12] 800aca8: 681b ldr r3, [r3, #0] 800acaa: 4a20 ldr r2, [pc, #128] @ (800ad2c ) 800acac: 4293 cmp r3, r2 800acae: d004 beq.n 800acba 800acb0: 68fb ldr r3, [r7, #12] 800acb2: 681b ldr r3, [r3, #0] 800acb4: 4a1e ldr r2, [pc, #120] @ (800ad30 ) 800acb6: 4293 cmp r3, r2 800acb8: d101 bne.n 800acbe 800acba: 2301 movs r3, #1 800acbc: e000 b.n 800acc0 800acbe: 2300 movs r3, #0 800acc0: 2b00 cmp r3, #0 800acc2: d020 beq.n 800ad06 regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 800acc4: 68fb ldr r3, [r7, #12] 800acc6: 6ddb ldr r3, [r3, #92] @ 0x5c 800acc8: f003 031f and.w r3, r3, #31 800accc: 2201 movs r2, #1 800acce: 409a lsls r2, r3 800acd0: 693b ldr r3, [r7, #16] 800acd2: 605a str r2, [r3, #4] ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; 800acd4: 68fb ldr r3, [r7, #12] 800acd6: 681b ldr r3, [r3, #0] 800acd8: 683a ldr r2, [r7, #0] 800acda: 605a str r2, [r3, #4] if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800acdc: 68fb ldr r3, [r7, #12] 800acde: 689b ldr r3, [r3, #8] 800ace0: 2b40 cmp r3, #64 @ 0x40 800ace2: d108 bne.n 800acf6 ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; 800ace4: 68fb ldr r3, [r7, #12] 800ace6: 681b ldr r3, [r3, #0] 800ace8: 687a ldr r2, [r7, #4] 800acea: 609a str r2, [r3, #8] ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; 800acec: 68fb ldr r3, [r7, #12] 800acee: 681b ldr r3, [r3, #0] 800acf0: 68ba ldr r2, [r7, #8] 800acf2: 60da str r2, [r3, #12] } 800acf4: e007 b.n 800ad06 ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; 800acf6: 68fb ldr r3, [r7, #12] 800acf8: 681b ldr r3, [r3, #0] 800acfa: 68ba ldr r2, [r7, #8] 800acfc: 609a str r2, [r3, #8] ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; 800acfe: 68fb ldr r3, [r7, #12] 800ad00: 681b ldr r3, [r3, #0] 800ad02: 687a ldr r2, [r7, #4] 800ad04: 60da str r2, [r3, #12] } 800ad06: bf00 nop 800ad08: 371c adds r7, #28 800ad0a: 46bd mov sp, r7 800ad0c: f85d 7b04 ldr.w r7, [sp], #4 800ad10: 4770 bx lr 800ad12: bf00 nop 800ad14: 58025408 .word 0x58025408 800ad18: 5802541c .word 0x5802541c 800ad1c: 58025430 .word 0x58025430 800ad20: 58025444 .word 0x58025444 800ad24: 58025458 .word 0x58025458 800ad28: 5802546c .word 0x5802546c 800ad2c: 58025480 .word 0x58025480 800ad30: 58025494 .word 0x58025494 0800ad34 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 800ad34: b480 push {r7} 800ad36: b085 sub sp, #20 800ad38: af00 add r7, sp, #0 800ad3a: 6078 str r0, [r7, #4] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800ad3c: 687b ldr r3, [r7, #4] 800ad3e: 681b ldr r3, [r3, #0] 800ad40: 4a42 ldr r2, [pc, #264] @ (800ae4c ) 800ad42: 4293 cmp r3, r2 800ad44: d04a beq.n 800addc 800ad46: 687b ldr r3, [r7, #4] 800ad48: 681b ldr r3, [r3, #0] 800ad4a: 4a41 ldr r2, [pc, #260] @ (800ae50 ) 800ad4c: 4293 cmp r3, r2 800ad4e: d045 beq.n 800addc 800ad50: 687b ldr r3, [r7, #4] 800ad52: 681b ldr r3, [r3, #0] 800ad54: 4a3f ldr r2, [pc, #252] @ (800ae54 ) 800ad56: 4293 cmp r3, r2 800ad58: d040 beq.n 800addc 800ad5a: 687b ldr r3, [r7, #4] 800ad5c: 681b ldr r3, [r3, #0] 800ad5e: 4a3e ldr r2, [pc, #248] @ (800ae58 ) 800ad60: 4293 cmp r3, r2 800ad62: d03b beq.n 800addc 800ad64: 687b ldr r3, [r7, #4] 800ad66: 681b ldr r3, [r3, #0] 800ad68: 4a3c ldr r2, [pc, #240] @ (800ae5c ) 800ad6a: 4293 cmp r3, r2 800ad6c: d036 beq.n 800addc 800ad6e: 687b ldr r3, [r7, #4] 800ad70: 681b ldr r3, [r3, #0] 800ad72: 4a3b ldr r2, [pc, #236] @ (800ae60 ) 800ad74: 4293 cmp r3, r2 800ad76: d031 beq.n 800addc 800ad78: 687b ldr r3, [r7, #4] 800ad7a: 681b ldr r3, [r3, #0] 800ad7c: 4a39 ldr r2, [pc, #228] @ (800ae64 ) 800ad7e: 4293 cmp r3, r2 800ad80: d02c beq.n 800addc 800ad82: 687b ldr r3, [r7, #4] 800ad84: 681b ldr r3, [r3, #0] 800ad86: 4a38 ldr r2, [pc, #224] @ (800ae68 ) 800ad88: 4293 cmp r3, r2 800ad8a: d027 beq.n 800addc 800ad8c: 687b ldr r3, [r7, #4] 800ad8e: 681b ldr r3, [r3, #0] 800ad90: 4a36 ldr r2, [pc, #216] @ (800ae6c ) 800ad92: 4293 cmp r3, r2 800ad94: d022 beq.n 800addc 800ad96: 687b ldr r3, [r7, #4] 800ad98: 681b ldr r3, [r3, #0] 800ad9a: 4a35 ldr r2, [pc, #212] @ (800ae70 ) 800ad9c: 4293 cmp r3, r2 800ad9e: d01d beq.n 800addc 800ada0: 687b ldr r3, [r7, #4] 800ada2: 681b ldr r3, [r3, #0] 800ada4: 4a33 ldr r2, [pc, #204] @ (800ae74 ) 800ada6: 4293 cmp r3, r2 800ada8: d018 beq.n 800addc 800adaa: 687b ldr r3, [r7, #4] 800adac: 681b ldr r3, [r3, #0] 800adae: 4a32 ldr r2, [pc, #200] @ (800ae78 ) 800adb0: 4293 cmp r3, r2 800adb2: d013 beq.n 800addc 800adb4: 687b ldr r3, [r7, #4] 800adb6: 681b ldr r3, [r3, #0] 800adb8: 4a30 ldr r2, [pc, #192] @ (800ae7c ) 800adba: 4293 cmp r3, r2 800adbc: d00e beq.n 800addc 800adbe: 687b ldr r3, [r7, #4] 800adc0: 681b ldr r3, [r3, #0] 800adc2: 4a2f ldr r2, [pc, #188] @ (800ae80 ) 800adc4: 4293 cmp r3, r2 800adc6: d009 beq.n 800addc 800adc8: 687b ldr r3, [r7, #4] 800adca: 681b ldr r3, [r3, #0] 800adcc: 4a2d ldr r2, [pc, #180] @ (800ae84 ) 800adce: 4293 cmp r3, r2 800add0: d004 beq.n 800addc 800add2: 687b ldr r3, [r7, #4] 800add4: 681b ldr r3, [r3, #0] 800add6: 4a2c ldr r2, [pc, #176] @ (800ae88 ) 800add8: 4293 cmp r3, r2 800adda: d101 bne.n 800ade0 800addc: 2301 movs r3, #1 800adde: e000 b.n 800ade2 800ade0: 2300 movs r3, #0 800ade2: 2b00 cmp r3, #0 800ade4: d024 beq.n 800ae30 { uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800ade6: 687b ldr r3, [r7, #4] 800ade8: 681b ldr r3, [r3, #0] 800adea: b2db uxtb r3, r3 800adec: 3b10 subs r3, #16 800adee: 4a27 ldr r2, [pc, #156] @ (800ae8c ) 800adf0: fba2 2303 umull r2, r3, r2, r3 800adf4: 091b lsrs r3, r3, #4 800adf6: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; 800adf8: 68fb ldr r3, [r7, #12] 800adfa: f003 0307 and.w r3, r3, #7 800adfe: 4a24 ldr r2, [pc, #144] @ (800ae90 ) 800ae00: 5cd3 ldrb r3, [r2, r3] 800ae02: 461a mov r2, r3 800ae04: 687b ldr r3, [r7, #4] 800ae06: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 800ae08: 68fb ldr r3, [r7, #12] 800ae0a: 2b03 cmp r3, #3 800ae0c: d908 bls.n 800ae20 { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); 800ae0e: 687b ldr r3, [r7, #4] 800ae10: 681b ldr r3, [r3, #0] 800ae12: 461a mov r2, r3 800ae14: 4b1f ldr r3, [pc, #124] @ (800ae94 ) 800ae16: 4013 ands r3, r2 800ae18: 1d1a adds r2, r3, #4 800ae1a: 687b ldr r3, [r7, #4] 800ae1c: 659a str r2, [r3, #88] @ 0x58 800ae1e: e00d b.n 800ae3c } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); 800ae20: 687b ldr r3, [r7, #4] 800ae22: 681b ldr r3, [r3, #0] 800ae24: 461a mov r2, r3 800ae26: 4b1b ldr r3, [pc, #108] @ (800ae94 ) 800ae28: 4013 ands r3, r2 800ae2a: 687a ldr r2, [r7, #4] 800ae2c: 6593 str r3, [r2, #88] @ 0x58 800ae2e: e005 b.n 800ae3c } } else /* BDMA instance(s) */ { /* return pointer to ISR and IFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); 800ae30: 687b ldr r3, [r7, #4] 800ae32: 681b ldr r3, [r3, #0] 800ae34: f023 02ff bic.w r2, r3, #255 @ 0xff 800ae38: 687b ldr r3, [r7, #4] 800ae3a: 659a str r2, [r3, #88] @ 0x58 } return hdma->StreamBaseAddress; 800ae3c: 687b ldr r3, [r7, #4] 800ae3e: 6d9b ldr r3, [r3, #88] @ 0x58 } 800ae40: 4618 mov r0, r3 800ae42: 3714 adds r7, #20 800ae44: 46bd mov sp, r7 800ae46: f85d 7b04 ldr.w r7, [sp], #4 800ae4a: 4770 bx lr 800ae4c: 40020010 .word 0x40020010 800ae50: 40020028 .word 0x40020028 800ae54: 40020040 .word 0x40020040 800ae58: 40020058 .word 0x40020058 800ae5c: 40020070 .word 0x40020070 800ae60: 40020088 .word 0x40020088 800ae64: 400200a0 .word 0x400200a0 800ae68: 400200b8 .word 0x400200b8 800ae6c: 40020410 .word 0x40020410 800ae70: 40020428 .word 0x40020428 800ae74: 40020440 .word 0x40020440 800ae78: 40020458 .word 0x40020458 800ae7c: 40020470 .word 0x40020470 800ae80: 40020488 .word 0x40020488 800ae84: 400204a0 .word 0x400204a0 800ae88: 400204b8 .word 0x400204b8 800ae8c: aaaaaaab .word 0xaaaaaaab 800ae90: 080186ec .word 0x080186ec 800ae94: fffffc00 .word 0xfffffc00 0800ae98 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 800ae98: b480 push {r7} 800ae9a: b085 sub sp, #20 800ae9c: af00 add r7, sp, #0 800ae9e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800aea0: 2300 movs r3, #0 800aea2: 73fb strb r3, [r7, #15] /* Memory Data size equal to Byte */ if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 800aea4: 687b ldr r3, [r7, #4] 800aea6: 699b ldr r3, [r3, #24] 800aea8: 2b00 cmp r3, #0 800aeaa: d120 bne.n 800aeee { switch (hdma->Init.FIFOThreshold) 800aeac: 687b ldr r3, [r7, #4] 800aeae: 6a9b ldr r3, [r3, #40] @ 0x28 800aeb0: 2b03 cmp r3, #3 800aeb2: d858 bhi.n 800af66 800aeb4: a201 add r2, pc, #4 @ (adr r2, 800aebc ) 800aeb6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800aeba: bf00 nop 800aebc: 0800aecd .word 0x0800aecd 800aec0: 0800aedf .word 0x0800aedf 800aec4: 0800aecd .word 0x0800aecd 800aec8: 0800af67 .word 0x0800af67 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800aecc: 687b ldr r3, [r7, #4] 800aece: 6adb ldr r3, [r3, #44] @ 0x2c 800aed0: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800aed4: 2b00 cmp r3, #0 800aed6: d048 beq.n 800af6a { status = HAL_ERROR; 800aed8: 2301 movs r3, #1 800aeda: 73fb strb r3, [r7, #15] } break; 800aedc: e045 b.n 800af6a case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 800aede: 687b ldr r3, [r7, #4] 800aee0: 6adb ldr r3, [r3, #44] @ 0x2c 800aee2: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800aee6: d142 bne.n 800af6e { status = HAL_ERROR; 800aee8: 2301 movs r3, #1 800aeea: 73fb strb r3, [r7, #15] } break; 800aeec: e03f b.n 800af6e break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 800aeee: 687b ldr r3, [r7, #4] 800aef0: 699b ldr r3, [r3, #24] 800aef2: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800aef6: d123 bne.n 800af40 { switch (hdma->Init.FIFOThreshold) 800aef8: 687b ldr r3, [r7, #4] 800aefa: 6a9b ldr r3, [r3, #40] @ 0x28 800aefc: 2b03 cmp r3, #3 800aefe: d838 bhi.n 800af72 800af00: a201 add r2, pc, #4 @ (adr r2, 800af08 ) 800af02: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800af06: bf00 nop 800af08: 0800af19 .word 0x0800af19 800af0c: 0800af1f .word 0x0800af1f 800af10: 0800af19 .word 0x0800af19 800af14: 0800af31 .word 0x0800af31 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 800af18: 2301 movs r3, #1 800af1a: 73fb strb r3, [r7, #15] break; 800af1c: e030 b.n 800af80 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800af1e: 687b ldr r3, [r7, #4] 800af20: 6adb ldr r3, [r3, #44] @ 0x2c 800af22: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800af26: 2b00 cmp r3, #0 800af28: d025 beq.n 800af76 { status = HAL_ERROR; 800af2a: 2301 movs r3, #1 800af2c: 73fb strb r3, [r7, #15] } break; 800af2e: e022 b.n 800af76 case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 800af30: 687b ldr r3, [r7, #4] 800af32: 6adb ldr r3, [r3, #44] @ 0x2c 800af34: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800af38: d11f bne.n 800af7a { status = HAL_ERROR; 800af3a: 2301 movs r3, #1 800af3c: 73fb strb r3, [r7, #15] } break; 800af3e: e01c b.n 800af7a } /* Memory Data size equal to Word */ else { switch (hdma->Init.FIFOThreshold) 800af40: 687b ldr r3, [r7, #4] 800af42: 6a9b ldr r3, [r3, #40] @ 0x28 800af44: 2b02 cmp r3, #2 800af46: d902 bls.n 800af4e 800af48: 2b03 cmp r3, #3 800af4a: d003 beq.n 800af54 status = HAL_ERROR; } break; default: break; 800af4c: e018 b.n 800af80 status = HAL_ERROR; 800af4e: 2301 movs r3, #1 800af50: 73fb strb r3, [r7, #15] break; 800af52: e015 b.n 800af80 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800af54: 687b ldr r3, [r7, #4] 800af56: 6adb ldr r3, [r3, #44] @ 0x2c 800af58: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800af5c: 2b00 cmp r3, #0 800af5e: d00e beq.n 800af7e status = HAL_ERROR; 800af60: 2301 movs r3, #1 800af62: 73fb strb r3, [r7, #15] break; 800af64: e00b b.n 800af7e break; 800af66: bf00 nop 800af68: e00a b.n 800af80 break; 800af6a: bf00 nop 800af6c: e008 b.n 800af80 break; 800af6e: bf00 nop 800af70: e006 b.n 800af80 break; 800af72: bf00 nop 800af74: e004 b.n 800af80 break; 800af76: bf00 nop 800af78: e002 b.n 800af80 break; 800af7a: bf00 nop 800af7c: e000 b.n 800af80 break; 800af7e: bf00 nop } } return status; 800af80: 7bfb ldrb r3, [r7, #15] } 800af82: 4618 mov r0, r3 800af84: 3714 adds r7, #20 800af86: 46bd mov sp, r7 800af88: f85d 7b04 ldr.w r7, [sp], #4 800af8c: 4770 bx lr 800af8e: bf00 nop 0800af90 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 800af90: b480 push {r7} 800af92: b085 sub sp, #20 800af94: af00 add r7, sp, #0 800af96: 6078 str r0, [r7, #4] uint32_t stream_number; uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); 800af98: 687b ldr r3, [r7, #4] 800af9a: 681b ldr r3, [r3, #0] 800af9c: 60bb str r3, [r7, #8] if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 800af9e: 687b ldr r3, [r7, #4] 800afa0: 681b ldr r3, [r3, #0] 800afa2: 4a38 ldr r2, [pc, #224] @ (800b084 ) 800afa4: 4293 cmp r3, r2 800afa6: d022 beq.n 800afee 800afa8: 687b ldr r3, [r7, #4] 800afaa: 681b ldr r3, [r3, #0] 800afac: 4a36 ldr r2, [pc, #216] @ (800b088 ) 800afae: 4293 cmp r3, r2 800afb0: d01d beq.n 800afee 800afb2: 687b ldr r3, [r7, #4] 800afb4: 681b ldr r3, [r3, #0] 800afb6: 4a35 ldr r2, [pc, #212] @ (800b08c ) 800afb8: 4293 cmp r3, r2 800afba: d018 beq.n 800afee 800afbc: 687b ldr r3, [r7, #4] 800afbe: 681b ldr r3, [r3, #0] 800afc0: 4a33 ldr r2, [pc, #204] @ (800b090 ) 800afc2: 4293 cmp r3, r2 800afc4: d013 beq.n 800afee 800afc6: 687b ldr r3, [r7, #4] 800afc8: 681b ldr r3, [r3, #0] 800afca: 4a32 ldr r2, [pc, #200] @ (800b094 ) 800afcc: 4293 cmp r3, r2 800afce: d00e beq.n 800afee 800afd0: 687b ldr r3, [r7, #4] 800afd2: 681b ldr r3, [r3, #0] 800afd4: 4a30 ldr r2, [pc, #192] @ (800b098 ) 800afd6: 4293 cmp r3, r2 800afd8: d009 beq.n 800afee 800afda: 687b ldr r3, [r7, #4] 800afdc: 681b ldr r3, [r3, #0] 800afde: 4a2f ldr r2, [pc, #188] @ (800b09c ) 800afe0: 4293 cmp r3, r2 800afe2: d004 beq.n 800afee 800afe4: 687b ldr r3, [r7, #4] 800afe6: 681b ldr r3, [r3, #0] 800afe8: 4a2d ldr r2, [pc, #180] @ (800b0a0 ) 800afea: 4293 cmp r3, r2 800afec: d101 bne.n 800aff2 800afee: 2301 movs r3, #1 800aff0: e000 b.n 800aff4 800aff2: 2300 movs r3, #0 800aff4: 2b00 cmp r3, #0 800aff6: d01a beq.n 800b02e { /* BDMA Channels are connected to DMAMUX2 channels */ stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; 800aff8: 687b ldr r3, [r7, #4] 800affa: 681b ldr r3, [r3, #0] 800affc: b2db uxtb r3, r3 800affe: 3b08 subs r3, #8 800b000: 4a28 ldr r2, [pc, #160] @ (800b0a4 ) 800b002: fba2 2303 umull r2, r3, r2, r3 800b006: 091b lsrs r3, r3, #4 800b008: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); 800b00a: 68fa ldr r2, [r7, #12] 800b00c: 4b26 ldr r3, [pc, #152] @ (800b0a8 ) 800b00e: 4413 add r3, r2 800b010: 009b lsls r3, r3, #2 800b012: 461a mov r2, r3 800b014: 687b ldr r3, [r7, #4] 800b016: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; 800b018: 687b ldr r3, [r7, #4] 800b01a: 4a24 ldr r2, [pc, #144] @ (800b0ac ) 800b01c: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800b01e: 68fb ldr r3, [r7, #12] 800b020: f003 031f and.w r3, r3, #31 800b024: 2201 movs r2, #1 800b026: 409a lsls r2, r3 800b028: 687b ldr r3, [r7, #4] 800b02a: 669a str r2, [r3, #104] @ 0x68 } hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); } } 800b02c: e024 b.n 800b078 stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800b02e: 687b ldr r3, [r7, #4] 800b030: 681b ldr r3, [r3, #0] 800b032: b2db uxtb r3, r3 800b034: 3b10 subs r3, #16 800b036: 4a1e ldr r2, [pc, #120] @ (800b0b0 ) 800b038: fba2 2303 umull r2, r3, r2, r3 800b03c: 091b lsrs r3, r3, #4 800b03e: 60fb str r3, [r7, #12] if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ 800b040: 68bb ldr r3, [r7, #8] 800b042: 4a1c ldr r2, [pc, #112] @ (800b0b4 ) 800b044: 4293 cmp r3, r2 800b046: d806 bhi.n 800b056 800b048: 68bb ldr r3, [r7, #8] 800b04a: 4a1b ldr r2, [pc, #108] @ (800b0b8 ) 800b04c: 4293 cmp r3, r2 800b04e: d902 bls.n 800b056 stream_number += 8U; 800b050: 68fb ldr r3, [r7, #12] 800b052: 3308 adds r3, #8 800b054: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); 800b056: 68fa ldr r2, [r7, #12] 800b058: 4b18 ldr r3, [pc, #96] @ (800b0bc ) 800b05a: 4413 add r3, r2 800b05c: 009b lsls r3, r3, #2 800b05e: 461a mov r2, r3 800b060: 687b ldr r3, [r7, #4] 800b062: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 800b064: 687b ldr r3, [r7, #4] 800b066: 4a16 ldr r2, [pc, #88] @ (800b0c0 ) 800b068: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800b06a: 68fb ldr r3, [r7, #12] 800b06c: f003 031f and.w r3, r3, #31 800b070: 2201 movs r2, #1 800b072: 409a lsls r2, r3 800b074: 687b ldr r3, [r7, #4] 800b076: 669a str r2, [r3, #104] @ 0x68 } 800b078: bf00 nop 800b07a: 3714 adds r7, #20 800b07c: 46bd mov sp, r7 800b07e: f85d 7b04 ldr.w r7, [sp], #4 800b082: 4770 bx lr 800b084: 58025408 .word 0x58025408 800b088: 5802541c .word 0x5802541c 800b08c: 58025430 .word 0x58025430 800b090: 58025444 .word 0x58025444 800b094: 58025458 .word 0x58025458 800b098: 5802546c .word 0x5802546c 800b09c: 58025480 .word 0x58025480 800b0a0: 58025494 .word 0x58025494 800b0a4: cccccccd .word 0xcccccccd 800b0a8: 16009600 .word 0x16009600 800b0ac: 58025880 .word 0x58025880 800b0b0: aaaaaaab .word 0xaaaaaaab 800b0b4: 400204b8 .word 0x400204b8 800b0b8: 4002040f .word 0x4002040f 800b0bc: 10008200 .word 0x10008200 800b0c0: 40020880 .word 0x40020880 0800b0c4 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 800b0c4: b480 push {r7} 800b0c6: b085 sub sp, #20 800b0c8: af00 add r7, sp, #0 800b0ca: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 800b0cc: 687b ldr r3, [r7, #4] 800b0ce: 685b ldr r3, [r3, #4] 800b0d0: b2db uxtb r3, r3 800b0d2: 60fb str r3, [r7, #12] if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) 800b0d4: 68fb ldr r3, [r7, #12] 800b0d6: 2b00 cmp r3, #0 800b0d8: d04a beq.n 800b170 800b0da: 68fb ldr r3, [r7, #12] 800b0dc: 2b08 cmp r3, #8 800b0de: d847 bhi.n 800b170 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 800b0e0: 687b ldr r3, [r7, #4] 800b0e2: 681b ldr r3, [r3, #0] 800b0e4: 4a25 ldr r2, [pc, #148] @ (800b17c ) 800b0e6: 4293 cmp r3, r2 800b0e8: d022 beq.n 800b130 800b0ea: 687b ldr r3, [r7, #4] 800b0ec: 681b ldr r3, [r3, #0] 800b0ee: 4a24 ldr r2, [pc, #144] @ (800b180 ) 800b0f0: 4293 cmp r3, r2 800b0f2: d01d beq.n 800b130 800b0f4: 687b ldr r3, [r7, #4] 800b0f6: 681b ldr r3, [r3, #0] 800b0f8: 4a22 ldr r2, [pc, #136] @ (800b184 ) 800b0fa: 4293 cmp r3, r2 800b0fc: d018 beq.n 800b130 800b0fe: 687b ldr r3, [r7, #4] 800b100: 681b ldr r3, [r3, #0] 800b102: 4a21 ldr r2, [pc, #132] @ (800b188 ) 800b104: 4293 cmp r3, r2 800b106: d013 beq.n 800b130 800b108: 687b ldr r3, [r7, #4] 800b10a: 681b ldr r3, [r3, #0] 800b10c: 4a1f ldr r2, [pc, #124] @ (800b18c ) 800b10e: 4293 cmp r3, r2 800b110: d00e beq.n 800b130 800b112: 687b ldr r3, [r7, #4] 800b114: 681b ldr r3, [r3, #0] 800b116: 4a1e ldr r2, [pc, #120] @ (800b190 ) 800b118: 4293 cmp r3, r2 800b11a: d009 beq.n 800b130 800b11c: 687b ldr r3, [r7, #4] 800b11e: 681b ldr r3, [r3, #0] 800b120: 4a1c ldr r2, [pc, #112] @ (800b194 ) 800b122: 4293 cmp r3, r2 800b124: d004 beq.n 800b130 800b126: 687b ldr r3, [r7, #4] 800b128: 681b ldr r3, [r3, #0] 800b12a: 4a1b ldr r2, [pc, #108] @ (800b198 ) 800b12c: 4293 cmp r3, r2 800b12e: d101 bne.n 800b134 800b130: 2301 movs r3, #1 800b132: e000 b.n 800b136 800b134: 2300 movs r3, #0 800b136: 2b00 cmp r3, #0 800b138: d00a beq.n 800b150 { /* BDMA Channels are connected to DMAMUX2 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); 800b13a: 68fa ldr r2, [r7, #12] 800b13c: 4b17 ldr r3, [pc, #92] @ (800b19c ) 800b13e: 4413 add r3, r2 800b140: 009b lsls r3, r3, #2 800b142: 461a mov r2, r3 800b144: 687b ldr r3, [r7, #4] 800b146: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; 800b148: 687b ldr r3, [r7, #4] 800b14a: 4a15 ldr r2, [pc, #84] @ (800b1a0 ) 800b14c: 671a str r2, [r3, #112] @ 0x70 800b14e: e009 b.n 800b164 } else { /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 800b150: 68fa ldr r2, [r7, #12] 800b152: 4b14 ldr r3, [pc, #80] @ (800b1a4 ) 800b154: 4413 add r3, r2 800b156: 009b lsls r3, r3, #2 800b158: 461a mov r2, r3 800b15a: 687b ldr r3, [r7, #4] 800b15c: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 800b15e: 687b ldr r3, [r7, #4] 800b160: 4a11 ldr r2, [pc, #68] @ (800b1a8 ) 800b162: 671a str r2, [r3, #112] @ 0x70 } hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); 800b164: 68fb ldr r3, [r7, #12] 800b166: 3b01 subs r3, #1 800b168: 2201 movs r2, #1 800b16a: 409a lsls r2, r3 800b16c: 687b ldr r3, [r7, #4] 800b16e: 675a str r2, [r3, #116] @ 0x74 } } 800b170: bf00 nop 800b172: 3714 adds r7, #20 800b174: 46bd mov sp, r7 800b176: f85d 7b04 ldr.w r7, [sp], #4 800b17a: 4770 bx lr 800b17c: 58025408 .word 0x58025408 800b180: 5802541c .word 0x5802541c 800b184: 58025430 .word 0x58025430 800b188: 58025444 .word 0x58025444 800b18c: 58025458 .word 0x58025458 800b190: 5802546c .word 0x5802546c 800b194: 58025480 .word 0x58025480 800b198: 58025494 .word 0x58025494 800b19c: 1600963f .word 0x1600963f 800b1a0: 58025940 .word 0x58025940 800b1a4: 1000823f .word 0x1000823f 800b1a8: 40020940 .word 0x40020940 0800b1ac : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800b1ac: b480 push {r7} 800b1ae: b089 sub sp, #36 @ 0x24 800b1b0: af00 add r7, sp, #0 800b1b2: 6078 str r0, [r7, #4] 800b1b4: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 800b1b6: 2300 movs r3, #0 800b1b8: 61fb str r3, [r7, #28] EXTI_Core_TypeDef *EXTI_CurrentCPU; #if defined(DUAL_CORE) && defined(CORE_CM4) EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ #else EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ 800b1ba: 4b89 ldr r3, [pc, #548] @ (800b3e0 ) 800b1bc: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 800b1be: e194 b.n 800b4ea { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 800b1c0: 683b ldr r3, [r7, #0] 800b1c2: 681a ldr r2, [r3, #0] 800b1c4: 2101 movs r1, #1 800b1c6: 69fb ldr r3, [r7, #28] 800b1c8: fa01 f303 lsl.w r3, r1, r3 800b1cc: 4013 ands r3, r2 800b1ce: 613b str r3, [r7, #16] if (iocurrent != 0x00U) 800b1d0: 693b ldr r3, [r7, #16] 800b1d2: 2b00 cmp r3, #0 800b1d4: f000 8186 beq.w 800b4e4 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 800b1d8: 683b ldr r3, [r7, #0] 800b1da: 685b ldr r3, [r3, #4] 800b1dc: f003 0303 and.w r3, r3, #3 800b1e0: 2b01 cmp r3, #1 800b1e2: d005 beq.n 800b1f0 800b1e4: 683b ldr r3, [r7, #0] 800b1e6: 685b ldr r3, [r3, #4] 800b1e8: f003 0303 and.w r3, r3, #3 800b1ec: 2b02 cmp r3, #2 800b1ee: d130 bne.n 800b252 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 800b1f0: 687b ldr r3, [r7, #4] 800b1f2: 689b ldr r3, [r3, #8] 800b1f4: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 800b1f6: 69fb ldr r3, [r7, #28] 800b1f8: 005b lsls r3, r3, #1 800b1fa: 2203 movs r2, #3 800b1fc: fa02 f303 lsl.w r3, r2, r3 800b200: 43db mvns r3, r3 800b202: 69ba ldr r2, [r7, #24] 800b204: 4013 ands r3, r2 800b206: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 800b208: 683b ldr r3, [r7, #0] 800b20a: 68da ldr r2, [r3, #12] 800b20c: 69fb ldr r3, [r7, #28] 800b20e: 005b lsls r3, r3, #1 800b210: fa02 f303 lsl.w r3, r2, r3 800b214: 69ba ldr r2, [r7, #24] 800b216: 4313 orrs r3, r2 800b218: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 800b21a: 687b ldr r3, [r7, #4] 800b21c: 69ba ldr r2, [r7, #24] 800b21e: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 800b220: 687b ldr r3, [r7, #4] 800b222: 685b ldr r3, [r3, #4] 800b224: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT0 << position) ; 800b226: 2201 movs r2, #1 800b228: 69fb ldr r3, [r7, #28] 800b22a: fa02 f303 lsl.w r3, r2, r3 800b22e: 43db mvns r3, r3 800b230: 69ba ldr r2, [r7, #24] 800b232: 4013 ands r3, r2 800b234: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 800b236: 683b ldr r3, [r7, #0] 800b238: 685b ldr r3, [r3, #4] 800b23a: 091b lsrs r3, r3, #4 800b23c: f003 0201 and.w r2, r3, #1 800b240: 69fb ldr r3, [r7, #28] 800b242: fa02 f303 lsl.w r3, r2, r3 800b246: 69ba ldr r2, [r7, #24] 800b248: 4313 orrs r3, r2 800b24a: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 800b24c: 687b ldr r3, [r7, #4] 800b24e: 69ba ldr r2, [r7, #24] 800b250: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 800b252: 683b ldr r3, [r7, #0] 800b254: 685b ldr r3, [r3, #4] 800b256: f003 0303 and.w r3, r3, #3 800b25a: 2b03 cmp r3, #3 800b25c: d017 beq.n 800b28e { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 800b25e: 687b ldr r3, [r7, #4] 800b260: 68db ldr r3, [r3, #12] 800b262: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 800b264: 69fb ldr r3, [r7, #28] 800b266: 005b lsls r3, r3, #1 800b268: 2203 movs r2, #3 800b26a: fa02 f303 lsl.w r3, r2, r3 800b26e: 43db mvns r3, r3 800b270: 69ba ldr r2, [r7, #24] 800b272: 4013 ands r3, r2 800b274: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 800b276: 683b ldr r3, [r7, #0] 800b278: 689a ldr r2, [r3, #8] 800b27a: 69fb ldr r3, [r7, #28] 800b27c: 005b lsls r3, r3, #1 800b27e: fa02 f303 lsl.w r3, r2, r3 800b282: 69ba ldr r2, [r7, #24] 800b284: 4313 orrs r3, r2 800b286: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 800b288: 687b ldr r3, [r7, #4] 800b28a: 69ba ldr r2, [r7, #24] 800b28c: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 800b28e: 683b ldr r3, [r7, #0] 800b290: 685b ldr r3, [r3, #4] 800b292: f003 0303 and.w r3, r3, #3 800b296: 2b02 cmp r3, #2 800b298: d123 bne.n 800b2e2 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 800b29a: 69fb ldr r3, [r7, #28] 800b29c: 08da lsrs r2, r3, #3 800b29e: 687b ldr r3, [r7, #4] 800b2a0: 3208 adds r2, #8 800b2a2: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800b2a6: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 800b2a8: 69fb ldr r3, [r7, #28] 800b2aa: f003 0307 and.w r3, r3, #7 800b2ae: 009b lsls r3, r3, #2 800b2b0: 220f movs r2, #15 800b2b2: fa02 f303 lsl.w r3, r2, r3 800b2b6: 43db mvns r3, r3 800b2b8: 69ba ldr r2, [r7, #24] 800b2ba: 4013 ands r3, r2 800b2bc: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 800b2be: 683b ldr r3, [r7, #0] 800b2c0: 691a ldr r2, [r3, #16] 800b2c2: 69fb ldr r3, [r7, #28] 800b2c4: f003 0307 and.w r3, r3, #7 800b2c8: 009b lsls r3, r3, #2 800b2ca: fa02 f303 lsl.w r3, r2, r3 800b2ce: 69ba ldr r2, [r7, #24] 800b2d0: 4313 orrs r3, r2 800b2d2: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 800b2d4: 69fb ldr r3, [r7, #28] 800b2d6: 08da lsrs r2, r3, #3 800b2d8: 687b ldr r3, [r7, #4] 800b2da: 3208 adds r2, #8 800b2dc: 69b9 ldr r1, [r7, #24] 800b2de: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 800b2e2: 687b ldr r3, [r7, #4] 800b2e4: 681b ldr r3, [r3, #0] 800b2e6: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 800b2e8: 69fb ldr r3, [r7, #28] 800b2ea: 005b lsls r3, r3, #1 800b2ec: 2203 movs r2, #3 800b2ee: fa02 f303 lsl.w r3, r2, r3 800b2f2: 43db mvns r3, r3 800b2f4: 69ba ldr r2, [r7, #24] 800b2f6: 4013 ands r3, r2 800b2f8: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 800b2fa: 683b ldr r3, [r7, #0] 800b2fc: 685b ldr r3, [r3, #4] 800b2fe: f003 0203 and.w r2, r3, #3 800b302: 69fb ldr r3, [r7, #28] 800b304: 005b lsls r3, r3, #1 800b306: fa02 f303 lsl.w r3, r2, r3 800b30a: 69ba ldr r2, [r7, #24] 800b30c: 4313 orrs r3, r2 800b30e: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 800b310: 687b ldr r3, [r7, #4] 800b312: 69ba ldr r2, [r7, #24] 800b314: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 800b316: 683b ldr r3, [r7, #0] 800b318: 685b ldr r3, [r3, #4] 800b31a: f403 3340 and.w r3, r3, #196608 @ 0x30000 800b31e: 2b00 cmp r3, #0 800b320: f000 80e0 beq.w 800b4e4 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800b324: 4b2f ldr r3, [pc, #188] @ (800b3e4 ) 800b326: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 800b32a: 4a2e ldr r2, [pc, #184] @ (800b3e4 ) 800b32c: f043 0302 orr.w r3, r3, #2 800b330: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 800b334: 4b2b ldr r3, [pc, #172] @ (800b3e4 ) 800b336: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 800b33a: f003 0302 and.w r3, r3, #2 800b33e: 60fb str r3, [r7, #12] 800b340: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 800b342: 4a29 ldr r2, [pc, #164] @ (800b3e8 ) 800b344: 69fb ldr r3, [r7, #28] 800b346: 089b lsrs r3, r3, #2 800b348: 3302 adds r3, #2 800b34a: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800b34e: 61bb str r3, [r7, #24] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 800b350: 69fb ldr r3, [r7, #28] 800b352: f003 0303 and.w r3, r3, #3 800b356: 009b lsls r3, r3, #2 800b358: 220f movs r2, #15 800b35a: fa02 f303 lsl.w r3, r2, r3 800b35e: 43db mvns r3, r3 800b360: 69ba ldr r2, [r7, #24] 800b362: 4013 ands r3, r2 800b364: 61bb str r3, [r7, #24] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 800b366: 687b ldr r3, [r7, #4] 800b368: 4a20 ldr r2, [pc, #128] @ (800b3ec ) 800b36a: 4293 cmp r3, r2 800b36c: d052 beq.n 800b414 800b36e: 687b ldr r3, [r7, #4] 800b370: 4a1f ldr r2, [pc, #124] @ (800b3f0 ) 800b372: 4293 cmp r3, r2 800b374: d031 beq.n 800b3da 800b376: 687b ldr r3, [r7, #4] 800b378: 4a1e ldr r2, [pc, #120] @ (800b3f4 ) 800b37a: 4293 cmp r3, r2 800b37c: d02b beq.n 800b3d6 800b37e: 687b ldr r3, [r7, #4] 800b380: 4a1d ldr r2, [pc, #116] @ (800b3f8 ) 800b382: 4293 cmp r3, r2 800b384: d025 beq.n 800b3d2 800b386: 687b ldr r3, [r7, #4] 800b388: 4a1c ldr r2, [pc, #112] @ (800b3fc ) 800b38a: 4293 cmp r3, r2 800b38c: d01f beq.n 800b3ce 800b38e: 687b ldr r3, [r7, #4] 800b390: 4a1b ldr r2, [pc, #108] @ (800b400 ) 800b392: 4293 cmp r3, r2 800b394: d019 beq.n 800b3ca 800b396: 687b ldr r3, [r7, #4] 800b398: 4a1a ldr r2, [pc, #104] @ (800b404 ) 800b39a: 4293 cmp r3, r2 800b39c: d013 beq.n 800b3c6 800b39e: 687b ldr r3, [r7, #4] 800b3a0: 4a19 ldr r2, [pc, #100] @ (800b408 ) 800b3a2: 4293 cmp r3, r2 800b3a4: d00d beq.n 800b3c2 800b3a6: 687b ldr r3, [r7, #4] 800b3a8: 4a18 ldr r2, [pc, #96] @ (800b40c ) 800b3aa: 4293 cmp r3, r2 800b3ac: d007 beq.n 800b3be 800b3ae: 687b ldr r3, [r7, #4] 800b3b0: 4a17 ldr r2, [pc, #92] @ (800b410 ) 800b3b2: 4293 cmp r3, r2 800b3b4: d101 bne.n 800b3ba 800b3b6: 2309 movs r3, #9 800b3b8: e02d b.n 800b416 800b3ba: 230a movs r3, #10 800b3bc: e02b b.n 800b416 800b3be: 2308 movs r3, #8 800b3c0: e029 b.n 800b416 800b3c2: 2307 movs r3, #7 800b3c4: e027 b.n 800b416 800b3c6: 2306 movs r3, #6 800b3c8: e025 b.n 800b416 800b3ca: 2305 movs r3, #5 800b3cc: e023 b.n 800b416 800b3ce: 2304 movs r3, #4 800b3d0: e021 b.n 800b416 800b3d2: 2303 movs r3, #3 800b3d4: e01f b.n 800b416 800b3d6: 2302 movs r3, #2 800b3d8: e01d b.n 800b416 800b3da: 2301 movs r3, #1 800b3dc: e01b b.n 800b416 800b3de: bf00 nop 800b3e0: 58000080 .word 0x58000080 800b3e4: 58024400 .word 0x58024400 800b3e8: 58000400 .word 0x58000400 800b3ec: 58020000 .word 0x58020000 800b3f0: 58020400 .word 0x58020400 800b3f4: 58020800 .word 0x58020800 800b3f8: 58020c00 .word 0x58020c00 800b3fc: 58021000 .word 0x58021000 800b400: 58021400 .word 0x58021400 800b404: 58021800 .word 0x58021800 800b408: 58021c00 .word 0x58021c00 800b40c: 58022000 .word 0x58022000 800b410: 58022400 .word 0x58022400 800b414: 2300 movs r3, #0 800b416: 69fa ldr r2, [r7, #28] 800b418: f002 0203 and.w r2, r2, #3 800b41c: 0092 lsls r2, r2, #2 800b41e: 4093 lsls r3, r2 800b420: 69ba ldr r2, [r7, #24] 800b422: 4313 orrs r3, r2 800b424: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 800b426: 4938 ldr r1, [pc, #224] @ (800b508 ) 800b428: 69fb ldr r3, [r7, #28] 800b42a: 089b lsrs r3, r3, #2 800b42c: 3302 adds r3, #2 800b42e: 69ba ldr r2, [r7, #24] 800b430: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 800b434: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b438: 681b ldr r3, [r3, #0] 800b43a: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b43c: 693b ldr r3, [r7, #16] 800b43e: 43db mvns r3, r3 800b440: 69ba ldr r2, [r7, #24] 800b442: 4013 ands r3, r2 800b444: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 800b446: 683b ldr r3, [r7, #0] 800b448: 685b ldr r3, [r3, #4] 800b44a: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800b44e: 2b00 cmp r3, #0 800b450: d003 beq.n 800b45a { temp |= iocurrent; 800b452: 69ba ldr r2, [r7, #24] 800b454: 693b ldr r3, [r7, #16] 800b456: 4313 orrs r3, r2 800b458: 61bb str r3, [r7, #24] } EXTI->RTSR1 = temp; 800b45a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b45e: 69bb ldr r3, [r7, #24] 800b460: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 800b462: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b466: 685b ldr r3, [r3, #4] 800b468: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b46a: 693b ldr r3, [r7, #16] 800b46c: 43db mvns r3, r3 800b46e: 69ba ldr r2, [r7, #24] 800b470: 4013 ands r3, r2 800b472: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 800b474: 683b ldr r3, [r7, #0] 800b476: 685b ldr r3, [r3, #4] 800b478: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800b47c: 2b00 cmp r3, #0 800b47e: d003 beq.n 800b488 { temp |= iocurrent; 800b480: 69ba ldr r2, [r7, #24] 800b482: 693b ldr r3, [r7, #16] 800b484: 4313 orrs r3, r2 800b486: 61bb str r3, [r7, #24] } EXTI->FTSR1 = temp; 800b488: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b48c: 69bb ldr r3, [r7, #24] 800b48e: 6053 str r3, [r2, #4] temp = EXTI_CurrentCPU->EMR1; 800b490: 697b ldr r3, [r7, #20] 800b492: 685b ldr r3, [r3, #4] 800b494: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b496: 693b ldr r3, [r7, #16] 800b498: 43db mvns r3, r3 800b49a: 69ba ldr r2, [r7, #24] 800b49c: 4013 ands r3, r2 800b49e: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 800b4a0: 683b ldr r3, [r7, #0] 800b4a2: 685b ldr r3, [r3, #4] 800b4a4: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b4a8: 2b00 cmp r3, #0 800b4aa: d003 beq.n 800b4b4 { temp |= iocurrent; 800b4ac: 69ba ldr r2, [r7, #24] 800b4ae: 693b ldr r3, [r7, #16] 800b4b0: 4313 orrs r3, r2 800b4b2: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->EMR1 = temp; 800b4b4: 697b ldr r3, [r7, #20] 800b4b6: 69ba ldr r2, [r7, #24] 800b4b8: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 800b4ba: 697b ldr r3, [r7, #20] 800b4bc: 681b ldr r3, [r3, #0] 800b4be: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b4c0: 693b ldr r3, [r7, #16] 800b4c2: 43db mvns r3, r3 800b4c4: 69ba ldr r2, [r7, #24] 800b4c6: 4013 ands r3, r2 800b4c8: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 800b4ca: 683b ldr r3, [r7, #0] 800b4cc: 685b ldr r3, [r3, #4] 800b4ce: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b4d2: 2b00 cmp r3, #0 800b4d4: d003 beq.n 800b4de { temp |= iocurrent; 800b4d6: 69ba ldr r2, [r7, #24] 800b4d8: 693b ldr r3, [r7, #16] 800b4da: 4313 orrs r3, r2 800b4dc: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->IMR1 = temp; 800b4de: 697b ldr r3, [r7, #20] 800b4e0: 69ba ldr r2, [r7, #24] 800b4e2: 601a str r2, [r3, #0] } } position++; 800b4e4: 69fb ldr r3, [r7, #28] 800b4e6: 3301 adds r3, #1 800b4e8: 61fb str r3, [r7, #28] while (((GPIO_Init->Pin) >> position) != 0x00U) 800b4ea: 683b ldr r3, [r7, #0] 800b4ec: 681a ldr r2, [r3, #0] 800b4ee: 69fb ldr r3, [r7, #28] 800b4f0: fa22 f303 lsr.w r3, r2, r3 800b4f4: 2b00 cmp r3, #0 800b4f6: f47f ae63 bne.w 800b1c0 } } 800b4fa: bf00 nop 800b4fc: bf00 nop 800b4fe: 3724 adds r7, #36 @ 0x24 800b500: 46bd mov sp, r7 800b502: f85d 7b04 ldr.w r7, [sp], #4 800b506: 4770 bx lr 800b508: 58000400 .word 0x58000400 0800b50c : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800b50c: b480 push {r7} 800b50e: b085 sub sp, #20 800b510: af00 add r7, sp, #0 800b512: 6078 str r0, [r7, #4] 800b514: 460b mov r3, r1 800b516: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0x00U) 800b518: 687b ldr r3, [r7, #4] 800b51a: 691a ldr r2, [r3, #16] 800b51c: 887b ldrh r3, [r7, #2] 800b51e: 4013 ands r3, r2 800b520: 2b00 cmp r3, #0 800b522: d002 beq.n 800b52a { bitstatus = GPIO_PIN_SET; 800b524: 2301 movs r3, #1 800b526: 73fb strb r3, [r7, #15] 800b528: e001 b.n 800b52e } else { bitstatus = GPIO_PIN_RESET; 800b52a: 2300 movs r3, #0 800b52c: 73fb strb r3, [r7, #15] } return bitstatus; 800b52e: 7bfb ldrb r3, [r7, #15] } 800b530: 4618 mov r0, r3 800b532: 3714 adds r7, #20 800b534: 46bd mov sp, r7 800b536: f85d 7b04 ldr.w r7, [sp], #4 800b53a: 4770 bx lr 0800b53c : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800b53c: b480 push {r7} 800b53e: b083 sub sp, #12 800b540: af00 add r7, sp, #0 800b542: 6078 str r0, [r7, #4] 800b544: 460b mov r3, r1 800b546: 807b strh r3, [r7, #2] 800b548: 4613 mov r3, r2 800b54a: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800b54c: 787b ldrb r3, [r7, #1] 800b54e: 2b00 cmp r3, #0 800b550: d003 beq.n 800b55a { GPIOx->BSRR = GPIO_Pin; 800b552: 887a ldrh r2, [r7, #2] 800b554: 687b ldr r3, [r7, #4] 800b556: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; } } 800b558: e003 b.n 800b562 GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 800b55a: 887b ldrh r3, [r7, #2] 800b55c: 041a lsls r2, r3, #16 800b55e: 687b ldr r3, [r7, #4] 800b560: 619a str r2, [r3, #24] } 800b562: bf00 nop 800b564: 370c adds r7, #12 800b566: 46bd mov sp, r7 800b568: f85d 7b04 ldr.w r7, [sp], #4 800b56c: 4770 bx lr 0800b56e : * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral. * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800b56e: b480 push {r7} 800b570: b085 sub sp, #20 800b572: af00 add r7, sp, #0 800b574: 6078 str r0, [r7, #4] 800b576: 460b mov r3, r1 800b578: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; 800b57a: 687b ldr r3, [r7, #4] 800b57c: 695b ldr r3, [r3, #20] 800b57e: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 800b580: 887a ldrh r2, [r7, #2] 800b582: 68fb ldr r3, [r7, #12] 800b584: 4013 ands r3, r2 800b586: 041a lsls r2, r3, #16 800b588: 68fb ldr r3, [r7, #12] 800b58a: 43d9 mvns r1, r3 800b58c: 887b ldrh r3, [r7, #2] 800b58e: 400b ands r3, r1 800b590: 431a orrs r2, r3 800b592: 687b ldr r3, [r7, #4] 800b594: 619a str r2, [r3, #24] } 800b596: bf00 nop 800b598: 3714 adds r7, #20 800b59a: 46bd mov sp, r7 800b59c: f85d 7b04 ldr.w r7, [sp], #4 800b5a0: 4770 bx lr 0800b5a2 : * @brief Handle EXTI interrupt request. * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 800b5a2: b580 push {r7, lr} 800b5a4: b082 sub sp, #8 800b5a6: af00 add r7, sp, #0 800b5a8: 4603 mov r3, r0 800b5aa: 80fb strh r3, [r7, #6] __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); } #else /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U) 800b5ac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b5b0: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 800b5b4: 88fb ldrh r3, [r7, #6] 800b5b6: 4013 ands r3, r2 800b5b8: 2b00 cmp r3, #0 800b5ba: d008 beq.n 800b5ce { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 800b5bc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b5c0: 88fb ldrh r3, [r7, #6] 800b5c2: f8c2 3088 str.w r3, [r2, #136] @ 0x88 HAL_GPIO_EXTI_Callback(GPIO_Pin); 800b5c6: 88fb ldrh r3, [r7, #6] 800b5c8: 4618 mov r0, r3 800b5ca: f7f5 f823 bl 8000614 } #endif } 800b5ce: bf00 nop 800b5d0: 3708 adds r7, #8 800b5d2: 46bd mov sp, r7 800b5d4: bd80 pop {r7, pc} 0800b5d6 : * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { 800b5d6: b580 push {r7, lr} 800b5d8: b084 sub sp, #16 800b5da: af00 add r7, sp, #0 800b5dc: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the IWDG handle allocation */ if (hiwdg == NULL) 800b5de: 687b ldr r3, [r7, #4] 800b5e0: 2b00 cmp r3, #0 800b5e2: d101 bne.n 800b5e8 { return HAL_ERROR; 800b5e4: 2301 movs r3, #1 800b5e6: e041 b.n 800b66c assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); /* Enable IWDG. LSI is turned on automatically */ __HAL_IWDG_START(hiwdg); 800b5e8: 687b ldr r3, [r7, #4] 800b5ea: 681b ldr r3, [r3, #0] 800b5ec: f64c 42cc movw r2, #52428 @ 0xcccc 800b5f0: 601a str r2, [r3, #0] /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing 0x5555 in KR */ IWDG_ENABLE_WRITE_ACCESS(hiwdg); 800b5f2: 687b ldr r3, [r7, #4] 800b5f4: 681b ldr r3, [r3, #0] 800b5f6: f245 5255 movw r2, #21845 @ 0x5555 800b5fa: 601a str r2, [r3, #0] /* Write to IWDG registers the Prescaler & Reload values to work with */ hiwdg->Instance->PR = hiwdg->Init.Prescaler; 800b5fc: 687b ldr r3, [r7, #4] 800b5fe: 681b ldr r3, [r3, #0] 800b600: 687a ldr r2, [r7, #4] 800b602: 6852 ldr r2, [r2, #4] 800b604: 605a str r2, [r3, #4] hiwdg->Instance->RLR = hiwdg->Init.Reload; 800b606: 687b ldr r3, [r7, #4] 800b608: 681b ldr r3, [r3, #0] 800b60a: 687a ldr r2, [r7, #4] 800b60c: 6892 ldr r2, [r2, #8] 800b60e: 609a str r2, [r3, #8] /* Check pending flag, if previous update not done, return timeout */ tickstart = HAL_GetTick(); 800b610: f7fa fbf4 bl 8005dfc 800b614: 60f8 str r0, [r7, #12] /* Wait for register to be updated */ while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 800b616: e00f b.n 800b638 { if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) 800b618: f7fa fbf0 bl 8005dfc 800b61c: 4602 mov r2, r0 800b61e: 68fb ldr r3, [r7, #12] 800b620: 1ad3 subs r3, r2, r3 800b622: 2b31 cmp r3, #49 @ 0x31 800b624: d908 bls.n 800b638 { if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 800b626: 687b ldr r3, [r7, #4] 800b628: 681b ldr r3, [r3, #0] 800b62a: 68db ldr r3, [r3, #12] 800b62c: f003 0307 and.w r3, r3, #7 800b630: 2b00 cmp r3, #0 800b632: d001 beq.n 800b638 { return HAL_TIMEOUT; 800b634: 2303 movs r3, #3 800b636: e019 b.n 800b66c while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 800b638: 687b ldr r3, [r7, #4] 800b63a: 681b ldr r3, [r3, #0] 800b63c: 68db ldr r3, [r3, #12] 800b63e: f003 0307 and.w r3, r3, #7 800b642: 2b00 cmp r3, #0 800b644: d1e8 bne.n 800b618 } } /* If window parameter is different than current value, modify window register */ if (hiwdg->Instance->WINR != hiwdg->Init.Window) 800b646: 687b ldr r3, [r7, #4] 800b648: 681b ldr r3, [r3, #0] 800b64a: 691a ldr r2, [r3, #16] 800b64c: 687b ldr r3, [r7, #4] 800b64e: 68db ldr r3, [r3, #12] 800b650: 429a cmp r2, r3 800b652: d005 beq.n 800b660 { /* Write to IWDG WINR the IWDG_Window value to compare with. In any case, even if window feature is disabled, Watchdog will be reloaded by writing windows register */ hiwdg->Instance->WINR = hiwdg->Init.Window; 800b654: 687b ldr r3, [r7, #4] 800b656: 681b ldr r3, [r3, #0] 800b658: 687a ldr r2, [r7, #4] 800b65a: 68d2 ldr r2, [r2, #12] 800b65c: 611a str r2, [r3, #16] 800b65e: e004 b.n 800b66a } else { /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); 800b660: 687b ldr r3, [r7, #4] 800b662: 681b ldr r3, [r3, #0] 800b664: f64a 22aa movw r2, #43690 @ 0xaaaa 800b668: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 800b66a: 2300 movs r3, #0 } 800b66c: 4618 mov r0, r3 800b66e: 3710 adds r7, #16 800b670: 46bd mov sp, r7 800b672: bd80 pop {r7, pc} 0800b674 : * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) { 800b674: b480 push {r7} 800b676: b083 sub sp, #12 800b678: af00 add r7, sp, #0 800b67a: 6078 str r0, [r7, #4] /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); 800b67c: 687b ldr r3, [r7, #4] 800b67e: 681b ldr r3, [r3, #0] 800b680: f64a 22aa movw r2, #43690 @ 0xaaaa 800b684: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800b686: 2300 movs r3, #0 } 800b688: 4618 mov r0, r3 800b68a: 370c adds r7, #12 800b68c: 46bd mov sp, r7 800b68e: f85d 7b04 ldr.w r7, [sp], #4 800b692: 4770 bx lr 0800b694 : * driver. All combination are allowed: wake up only Cortex-M7, wake up * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4. * @retval None. */ void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD) { 800b694: b480 push {r7} 800b696: b083 sub sp, #12 800b698: af00 add r7, sp, #0 800b69a: 6078 str r0, [r7, #4] /* Check the PVD configuration parameter */ if (sConfigPVD == NULL) 800b69c: 687b ldr r3, [r7, #4] 800b69e: 2b00 cmp r3, #0 800b6a0: d069 beq.n 800b776 /* Check the parameters */ assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel)); assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode)); /* Set PLS[7:5] bits according to PVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); 800b6a2: 4b38 ldr r3, [pc, #224] @ (800b784 ) 800b6a4: 681b ldr r3, [r3, #0] 800b6a6: f023 02e0 bic.w r2, r3, #224 @ 0xe0 800b6aa: 687b ldr r3, [r7, #4] 800b6ac: 681b ldr r3, [r3, #0] 800b6ae: 4935 ldr r1, [pc, #212] @ (800b784 ) 800b6b0: 4313 orrs r3, r2 800b6b2: 600b str r3, [r1, #0] /* Clear previous config */ #if !defined (DUAL_CORE) __HAL_PWR_PVD_EXTI_DISABLE_EVENT (); 800b6b4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b6b8: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b6bc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b6c0: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b6c4: f8c2 3084 str.w r3, [r2, #132] @ 0x84 __HAL_PWR_PVD_EXTI_DISABLE_IT (); 800b6c8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b6cc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b6d0: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b6d4: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b6d8: f8c2 3080 str.w r3, [r2, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE (); 800b6dc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b6e0: 681b ldr r3, [r3, #0] 800b6e2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b6e6: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b6ea: 6013 str r3, [r2, #0] __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE (); 800b6ec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b6f0: 685b ldr r3, [r3, #4] 800b6f2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b6f6: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b6fa: 6053 str r3, [r2, #4] #if !defined (DUAL_CORE) /* Interrupt mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 800b6fc: 687b ldr r3, [r7, #4] 800b6fe: 685b ldr r3, [r3, #4] 800b700: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b704: 2b00 cmp r3, #0 800b706: d009 beq.n 800b71c { __HAL_PWR_PVD_EXTI_ENABLE_IT (); 800b708: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b70c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b710: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b714: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b718: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } /* Event mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 800b71c: 687b ldr r3, [r7, #4] 800b71e: 685b ldr r3, [r3, #4] 800b720: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b724: 2b00 cmp r3, #0 800b726: d009 beq.n 800b73c { __HAL_PWR_PVD_EXTI_ENABLE_EVENT (); 800b728: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b72c: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b730: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b734: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b738: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 800b73c: 687b ldr r3, [r7, #4] 800b73e: 685b ldr r3, [r3, #4] 800b740: f003 0301 and.w r3, r3, #1 800b744: 2b00 cmp r3, #0 800b746: d007 beq.n 800b758 { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE (); 800b748: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b74c: 681b ldr r3, [r3, #0] 800b74e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b752: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b756: 6013 str r3, [r2, #0] } /* Falling edge configuration */ if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 800b758: 687b ldr r3, [r7, #4] 800b75a: 685b ldr r3, [r3, #4] 800b75c: f003 0302 and.w r3, r3, #2 800b760: 2b00 cmp r3, #0 800b762: d009 beq.n 800b778 { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE (); 800b764: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b768: 685b ldr r3, [r3, #4] 800b76a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b76e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b772: 6053 str r3, [r2, #4] 800b774: e000 b.n 800b778 return; 800b776: bf00 nop } } 800b778: 370c adds r7, #12 800b77a: 46bd mov sp, r7 800b77c: f85d 7b04 ldr.w r7, [sp], #4 800b780: 4770 bx lr 800b782: bf00 nop 800b784: 58024800 .word 0x58024800 0800b788 : /** * @brief Enable the Programmable Voltage Detector (PVD). * @retval None. */ void HAL_PWR_EnablePVD (void) { 800b788: b480 push {r7} 800b78a: af00 add r7, sp, #0 /* Enable the power voltage detector */ SET_BIT (PWR->CR1, PWR_CR1_PVDEN); 800b78c: 4b05 ldr r3, [pc, #20] @ (800b7a4 ) 800b78e: 681b ldr r3, [r3, #0] 800b790: 4a04 ldr r2, [pc, #16] @ (800b7a4 ) 800b792: f043 0310 orr.w r3, r3, #16 800b796: 6013 str r3, [r2, #0] } 800b798: bf00 nop 800b79a: 46bd mov sp, r7 800b79c: f85d 7b04 ldr.w r7, [sp], #4 800b7a0: 4770 bx lr 800b7a2: bf00 nop 800b7a4: 58024800 .word 0x58024800 0800b7a8 : * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { 800b7a8: b580 push {r7, lr} 800b7aa: b084 sub sp, #16 800b7ac: af00 add r7, sp, #0 800b7ae: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_SUPPLY (SupplySource)); /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) 800b7b0: 4b19 ldr r3, [pc, #100] @ (800b818 ) 800b7b2: 68db ldr r3, [r3, #12] 800b7b4: f003 0304 and.w r3, r3, #4 800b7b8: 2b04 cmp r3, #4 800b7ba: d00a beq.n 800b7d2 #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 800b7bc: 4b16 ldr r3, [pc, #88] @ (800b818 ) 800b7be: 68db ldr r3, [r3, #12] 800b7c0: f003 0307 and.w r3, r3, #7 800b7c4: 687a ldr r2, [r7, #4] 800b7c6: 429a cmp r2, r3 800b7c8: d001 beq.n 800b7ce { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 800b7ca: 2301 movs r3, #1 800b7cc: e01f b.n 800b80e else { /* Supply configuration update locked, but new supply configuration matches with old supply configuration : nothing to do */ return HAL_OK; 800b7ce: 2300 movs r3, #0 800b7d0: e01d b.n 800b80e } } /* Set the power supply configuration */ MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 800b7d2: 4b11 ldr r3, [pc, #68] @ (800b818 ) 800b7d4: 68db ldr r3, [r3, #12] 800b7d6: f023 0207 bic.w r2, r3, #7 800b7da: 490f ldr r1, [pc, #60] @ (800b818 ) 800b7dc: 687b ldr r3, [r7, #4] 800b7de: 4313 orrs r3, r2 800b7e0: 60cb str r3, [r1, #12] /* Get tick */ tickstart = HAL_GetTick (); 800b7e2: f7fa fb0b bl 8005dfc 800b7e6: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800b7e8: e009 b.n 800b7fe { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 800b7ea: f7fa fb07 bl 8005dfc 800b7ee: 4602 mov r2, r0 800b7f0: 68fb ldr r3, [r7, #12] 800b7f2: 1ad3 subs r3, r2, r3 800b7f4: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b7f8: d901 bls.n 800b7fe { return HAL_ERROR; 800b7fa: 2301 movs r3, #1 800b7fc: e007 b.n 800b80e while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800b7fe: 4b06 ldr r3, [pc, #24] @ (800b818 ) 800b800: 685b ldr r3, [r3, #4] 800b802: f403 5300 and.w r3, r3, #8192 @ 0x2000 800b806: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800b80a: d1ee bne.n 800b7ea } } } #endif /* defined (SMPS) */ return HAL_OK; 800b80c: 2300 movs r3, #0 } 800b80e: 4618 mov r0, r3 800b810: 3710 adds r7, #16 800b812: 46bd mov sp, r7 800b814: bd80 pop {r7, pc} 800b816: bf00 nop 800b818: 58024800 .word 0x58024800 0800b81c : * driver. All combination are allowed: wake up only Cortex-M7, wake up * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4. * @retval None. */ void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD) { 800b81c: b480 push {r7} 800b81e: b083 sub sp, #12 800b820: af00 add r7, sp, #0 800b822: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode)); /* Set the ALS[18:17] bits according to AVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); 800b824: 4b37 ldr r3, [pc, #220] @ (800b904 ) 800b826: 681b ldr r3, [r3, #0] 800b828: f423 22c0 bic.w r2, r3, #393216 @ 0x60000 800b82c: 687b ldr r3, [r7, #4] 800b82e: 681b ldr r3, [r3, #0] 800b830: 4934 ldr r1, [pc, #208] @ (800b904 ) 800b832: 4313 orrs r3, r2 800b834: 600b str r3, [r1, #0] /* Clear any previous config */ #if !defined (DUAL_CORE) __HAL_PWR_AVD_EXTI_DISABLE_EVENT (); 800b836: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b83a: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b83e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b842: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b846: f8c2 3084 str.w r3, [r2, #132] @ 0x84 __HAL_PWR_AVD_EXTI_DISABLE_IT (); 800b84a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b84e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b852: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b856: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b85a: f8c2 3080 str.w r3, [r2, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE (); 800b85e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b862: 681b ldr r3, [r3, #0] 800b864: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b868: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b86c: 6013 str r3, [r2, #0] __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE (); 800b86e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b872: 685b ldr r3, [r3, #4] 800b874: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b878: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b87c: 6053 str r3, [r2, #4] #if !defined (DUAL_CORE) /* Configure the interrupt mode */ if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT) 800b87e: 687b ldr r3, [r7, #4] 800b880: 685b ldr r3, [r3, #4] 800b882: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b886: 2b00 cmp r3, #0 800b888: d009 beq.n 800b89e { __HAL_PWR_AVD_EXTI_ENABLE_IT (); 800b88a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b88e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b892: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b896: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b89a: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } /* Configure the event mode */ if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT) 800b89e: 687b ldr r3, [r7, #4] 800b8a0: 685b ldr r3, [r3, #4] 800b8a2: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b8a6: 2b00 cmp r3, #0 800b8a8: d009 beq.n 800b8be { __HAL_PWR_AVD_EXTI_ENABLE_EVENT (); 800b8aa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b8ae: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b8b2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b8b6: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b8ba: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE) 800b8be: 687b ldr r3, [r7, #4] 800b8c0: 685b ldr r3, [r3, #4] 800b8c2: f003 0301 and.w r3, r3, #1 800b8c6: 2b00 cmp r3, #0 800b8c8: d007 beq.n 800b8da { __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE (); 800b8ca: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b8ce: 681b ldr r3, [r3, #0] 800b8d0: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b8d4: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b8d8: 6013 str r3, [r2, #0] } /* Falling edge configuration */ if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE) 800b8da: 687b ldr r3, [r7, #4] 800b8dc: 685b ldr r3, [r3, #4] 800b8de: f003 0302 and.w r3, r3, #2 800b8e2: 2b00 cmp r3, #0 800b8e4: d007 beq.n 800b8f6 { __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE (); 800b8e6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b8ea: 685b ldr r3, [r3, #4] 800b8ec: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b8f0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b8f4: 6053 str r3, [r2, #4] } } 800b8f6: bf00 nop 800b8f8: 370c adds r7, #12 800b8fa: 46bd mov sp, r7 800b8fc: f85d 7b04 ldr.w r7, [sp], #4 800b900: 4770 bx lr 800b902: bf00 nop 800b904: 58024800 .word 0x58024800 0800b908 : /** * @brief Enable the Analog Voltage Detector (AVD). * @retval None. */ void HAL_PWREx_EnableAVD (void) { 800b908: b480 push {r7} 800b90a: af00 add r7, sp, #0 /* Enable the Analog Voltage Detector */ SET_BIT (PWR->CR1, PWR_CR1_AVDEN); 800b90c: 4b05 ldr r3, [pc, #20] @ (800b924 ) 800b90e: 681b ldr r3, [r3, #0] 800b910: 4a04 ldr r2, [pc, #16] @ (800b924 ) 800b912: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b916: 6013 str r3, [r2, #0] } 800b918: bf00 nop 800b91a: 46bd mov sp, r7 800b91c: f85d 7b04 ldr.w r7, [sp], #4 800b920: 4770 bx lr 800b922: bf00 nop 800b924: 58024800 .word 0x58024800 0800b928 : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800b928: b580 push {r7, lr} 800b92a: b08c sub sp, #48 @ 0x30 800b92c: af00 add r7, sp, #0 800b92e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 800b930: 687b ldr r3, [r7, #4] 800b932: 2b00 cmp r3, #0 800b934: d102 bne.n 800b93c { return HAL_ERROR; 800b936: 2301 movs r3, #1 800b938: f000 bc48 b.w 800c1cc } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800b93c: 687b ldr r3, [r7, #4] 800b93e: 681b ldr r3, [r3, #0] 800b940: f003 0301 and.w r3, r3, #1 800b944: 2b00 cmp r3, #0 800b946: f000 8088 beq.w 800ba5a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b94a: 4b99 ldr r3, [pc, #612] @ (800bbb0 ) 800b94c: 691b ldr r3, [r3, #16] 800b94e: f003 0338 and.w r3, r3, #56 @ 0x38 800b952: 62fb str r3, [r7, #44] @ 0x2c const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800b954: 4b96 ldr r3, [pc, #600] @ (800bbb0 ) 800b956: 6a9b ldr r3, [r3, #40] @ 0x28 800b958: 62bb str r3, [r7, #40] @ 0x28 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 800b95a: 6afb ldr r3, [r7, #44] @ 0x2c 800b95c: 2b10 cmp r3, #16 800b95e: d007 beq.n 800b970 800b960: 6afb ldr r3, [r7, #44] @ 0x2c 800b962: 2b18 cmp r3, #24 800b964: d111 bne.n 800b98a 800b966: 6abb ldr r3, [r7, #40] @ 0x28 800b968: f003 0303 and.w r3, r3, #3 800b96c: 2b02 cmp r3, #2 800b96e: d10c bne.n 800b98a { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800b970: 4b8f ldr r3, [pc, #572] @ (800bbb0 ) 800b972: 681b ldr r3, [r3, #0] 800b974: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b978: 2b00 cmp r3, #0 800b97a: d06d beq.n 800ba58 800b97c: 687b ldr r3, [r7, #4] 800b97e: 685b ldr r3, [r3, #4] 800b980: 2b00 cmp r3, #0 800b982: d169 bne.n 800ba58 { return HAL_ERROR; 800b984: 2301 movs r3, #1 800b986: f000 bc21 b.w 800c1cc } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800b98a: 687b ldr r3, [r7, #4] 800b98c: 685b ldr r3, [r3, #4] 800b98e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800b992: d106 bne.n 800b9a2 800b994: 4b86 ldr r3, [pc, #536] @ (800bbb0 ) 800b996: 681b ldr r3, [r3, #0] 800b998: 4a85 ldr r2, [pc, #532] @ (800bbb0 ) 800b99a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b99e: 6013 str r3, [r2, #0] 800b9a0: e02e b.n 800ba00 800b9a2: 687b ldr r3, [r7, #4] 800b9a4: 685b ldr r3, [r3, #4] 800b9a6: 2b00 cmp r3, #0 800b9a8: d10c bne.n 800b9c4 800b9aa: 4b81 ldr r3, [pc, #516] @ (800bbb0 ) 800b9ac: 681b ldr r3, [r3, #0] 800b9ae: 4a80 ldr r2, [pc, #512] @ (800bbb0 ) 800b9b0: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b9b4: 6013 str r3, [r2, #0] 800b9b6: 4b7e ldr r3, [pc, #504] @ (800bbb0 ) 800b9b8: 681b ldr r3, [r3, #0] 800b9ba: 4a7d ldr r2, [pc, #500] @ (800bbb0 ) 800b9bc: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800b9c0: 6013 str r3, [r2, #0] 800b9c2: e01d b.n 800ba00 800b9c4: 687b ldr r3, [r7, #4] 800b9c6: 685b ldr r3, [r3, #4] 800b9c8: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800b9cc: d10c bne.n 800b9e8 800b9ce: 4b78 ldr r3, [pc, #480] @ (800bbb0 ) 800b9d0: 681b ldr r3, [r3, #0] 800b9d2: 4a77 ldr r2, [pc, #476] @ (800bbb0 ) 800b9d4: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800b9d8: 6013 str r3, [r2, #0] 800b9da: 4b75 ldr r3, [pc, #468] @ (800bbb0 ) 800b9dc: 681b ldr r3, [r3, #0] 800b9de: 4a74 ldr r2, [pc, #464] @ (800bbb0 ) 800b9e0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b9e4: 6013 str r3, [r2, #0] 800b9e6: e00b b.n 800ba00 800b9e8: 4b71 ldr r3, [pc, #452] @ (800bbb0 ) 800b9ea: 681b ldr r3, [r3, #0] 800b9ec: 4a70 ldr r2, [pc, #448] @ (800bbb0 ) 800b9ee: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b9f2: 6013 str r3, [r2, #0] 800b9f4: 4b6e ldr r3, [pc, #440] @ (800bbb0 ) 800b9f6: 681b ldr r3, [r3, #0] 800b9f8: 4a6d ldr r2, [pc, #436] @ (800bbb0 ) 800b9fa: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800b9fe: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 800ba00: 687b ldr r3, [r7, #4] 800ba02: 685b ldr r3, [r3, #4] 800ba04: 2b00 cmp r3, #0 800ba06: d013 beq.n 800ba30 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ba08: f7fa f9f8 bl 8005dfc 800ba0c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800ba0e: e008 b.n 800ba22 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800ba10: f7fa f9f4 bl 8005dfc 800ba14: 4602 mov r2, r0 800ba16: 6a7b ldr r3, [r7, #36] @ 0x24 800ba18: 1ad3 subs r3, r2, r3 800ba1a: 2b64 cmp r3, #100 @ 0x64 800ba1c: d901 bls.n 800ba22 { return HAL_TIMEOUT; 800ba1e: 2303 movs r3, #3 800ba20: e3d4 b.n 800c1cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800ba22: 4b63 ldr r3, [pc, #396] @ (800bbb0 ) 800ba24: 681b ldr r3, [r3, #0] 800ba26: f403 3300 and.w r3, r3, #131072 @ 0x20000 800ba2a: 2b00 cmp r3, #0 800ba2c: d0f0 beq.n 800ba10 800ba2e: e014 b.n 800ba5a } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ba30: f7fa f9e4 bl 8005dfc 800ba34: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800ba36: e008 b.n 800ba4a { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800ba38: f7fa f9e0 bl 8005dfc 800ba3c: 4602 mov r2, r0 800ba3e: 6a7b ldr r3, [r7, #36] @ 0x24 800ba40: 1ad3 subs r3, r2, r3 800ba42: 2b64 cmp r3, #100 @ 0x64 800ba44: d901 bls.n 800ba4a { return HAL_TIMEOUT; 800ba46: 2303 movs r3, #3 800ba48: e3c0 b.n 800c1cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800ba4a: 4b59 ldr r3, [pc, #356] @ (800bbb0 ) 800ba4c: 681b ldr r3, [r3, #0] 800ba4e: f403 3300 and.w r3, r3, #131072 @ 0x20000 800ba52: 2b00 cmp r3, #0 800ba54: d1f0 bne.n 800ba38 800ba56: e000 b.n 800ba5a if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800ba58: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800ba5a: 687b ldr r3, [r7, #4] 800ba5c: 681b ldr r3, [r3, #0] 800ba5e: f003 0302 and.w r3, r3, #2 800ba62: 2b00 cmp r3, #0 800ba64: f000 80ca beq.w 800bbfc /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800ba68: 4b51 ldr r3, [pc, #324] @ (800bbb0 ) 800ba6a: 691b ldr r3, [r3, #16] 800ba6c: f003 0338 and.w r3, r3, #56 @ 0x38 800ba70: 623b str r3, [r7, #32] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800ba72: 4b4f ldr r3, [pc, #316] @ (800bbb0 ) 800ba74: 6a9b ldr r3, [r3, #40] @ 0x28 800ba76: 61fb str r3, [r7, #28] if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 800ba78: 6a3b ldr r3, [r7, #32] 800ba7a: 2b00 cmp r3, #0 800ba7c: d007 beq.n 800ba8e 800ba7e: 6a3b ldr r3, [r7, #32] 800ba80: 2b18 cmp r3, #24 800ba82: d156 bne.n 800bb32 800ba84: 69fb ldr r3, [r7, #28] 800ba86: f003 0303 and.w r3, r3, #3 800ba8a: 2b00 cmp r3, #0 800ba8c: d151 bne.n 800bb32 { /* When HSI is used as system clock it will not be disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800ba8e: 4b48 ldr r3, [pc, #288] @ (800bbb0 ) 800ba90: 681b ldr r3, [r3, #0] 800ba92: f003 0304 and.w r3, r3, #4 800ba96: 2b00 cmp r3, #0 800ba98: d005 beq.n 800baa6 800ba9a: 687b ldr r3, [r7, #4] 800ba9c: 68db ldr r3, [r3, #12] 800ba9e: 2b00 cmp r3, #0 800baa0: d101 bne.n 800baa6 { return HAL_ERROR; 800baa2: 2301 movs r3, #1 800baa4: e392 b.n 800c1cc } /* Otherwise, only HSI division and calibration are allowed */ else { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800baa6: 4b42 ldr r3, [pc, #264] @ (800bbb0 ) 800baa8: 681b ldr r3, [r3, #0] 800baaa: f023 0219 bic.w r2, r3, #25 800baae: 687b ldr r3, [r7, #4] 800bab0: 68db ldr r3, [r3, #12] 800bab2: 493f ldr r1, [pc, #252] @ (800bbb0 ) 800bab4: 4313 orrs r3, r2 800bab6: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bab8: f7fa f9a0 bl 8005dfc 800babc: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800babe: e008 b.n 800bad2 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800bac0: f7fa f99c bl 8005dfc 800bac4: 4602 mov r2, r0 800bac6: 6a7b ldr r3, [r7, #36] @ 0x24 800bac8: 1ad3 subs r3, r2, r3 800baca: 2b02 cmp r3, #2 800bacc: d901 bls.n 800bad2 { return HAL_TIMEOUT; 800bace: 2303 movs r3, #3 800bad0: e37c b.n 800c1cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800bad2: 4b37 ldr r3, [pc, #220] @ (800bbb0 ) 800bad4: 681b ldr r3, [r3, #0] 800bad6: f003 0304 and.w r3, r3, #4 800bada: 2b00 cmp r3, #0 800badc: d0f0 beq.n 800bac0 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800bade: f7fa f999 bl 8005e14 800bae2: 4603 mov r3, r0 800bae4: f241 0203 movw r2, #4099 @ 0x1003 800bae8: 4293 cmp r3, r2 800baea: d817 bhi.n 800bb1c 800baec: 687b ldr r3, [r7, #4] 800baee: 691b ldr r3, [r3, #16] 800baf0: 2b40 cmp r3, #64 @ 0x40 800baf2: d108 bne.n 800bb06 800baf4: 4b2e ldr r3, [pc, #184] @ (800bbb0 ) 800baf6: 685b ldr r3, [r3, #4] 800baf8: f423 337c bic.w r3, r3, #258048 @ 0x3f000 800bafc: 4a2c ldr r2, [pc, #176] @ (800bbb0 ) 800bafe: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800bb02: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800bb04: e07a b.n 800bbfc __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800bb06: 4b2a ldr r3, [pc, #168] @ (800bbb0 ) 800bb08: 685b ldr r3, [r3, #4] 800bb0a: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800bb0e: 687b ldr r3, [r7, #4] 800bb10: 691b ldr r3, [r3, #16] 800bb12: 031b lsls r3, r3, #12 800bb14: 4926 ldr r1, [pc, #152] @ (800bbb0 ) 800bb16: 4313 orrs r3, r2 800bb18: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800bb1a: e06f b.n 800bbfc __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800bb1c: 4b24 ldr r3, [pc, #144] @ (800bbb0 ) 800bb1e: 685b ldr r3, [r3, #4] 800bb20: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800bb24: 687b ldr r3, [r7, #4] 800bb26: 691b ldr r3, [r3, #16] 800bb28: 061b lsls r3, r3, #24 800bb2a: 4921 ldr r1, [pc, #132] @ (800bbb0 ) 800bb2c: 4313 orrs r3, r2 800bb2e: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800bb30: e064 b.n 800bbfc } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 800bb32: 687b ldr r3, [r7, #4] 800bb34: 68db ldr r3, [r3, #12] 800bb36: 2b00 cmp r3, #0 800bb38: d047 beq.n 800bbca { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800bb3a: 4b1d ldr r3, [pc, #116] @ (800bbb0 ) 800bb3c: 681b ldr r3, [r3, #0] 800bb3e: f023 0219 bic.w r2, r3, #25 800bb42: 687b ldr r3, [r7, #4] 800bb44: 68db ldr r3, [r3, #12] 800bb46: 491a ldr r1, [pc, #104] @ (800bbb0 ) 800bb48: 4313 orrs r3, r2 800bb4a: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bb4c: f7fa f956 bl 8005dfc 800bb50: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800bb52: e008 b.n 800bb66 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800bb54: f7fa f952 bl 8005dfc 800bb58: 4602 mov r2, r0 800bb5a: 6a7b ldr r3, [r7, #36] @ 0x24 800bb5c: 1ad3 subs r3, r2, r3 800bb5e: 2b02 cmp r3, #2 800bb60: d901 bls.n 800bb66 { return HAL_TIMEOUT; 800bb62: 2303 movs r3, #3 800bb64: e332 b.n 800c1cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800bb66: 4b12 ldr r3, [pc, #72] @ (800bbb0 ) 800bb68: 681b ldr r3, [r3, #0] 800bb6a: f003 0304 and.w r3, r3, #4 800bb6e: 2b00 cmp r3, #0 800bb70: d0f0 beq.n 800bb54 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800bb72: f7fa f94f bl 8005e14 800bb76: 4603 mov r3, r0 800bb78: f241 0203 movw r2, #4099 @ 0x1003 800bb7c: 4293 cmp r3, r2 800bb7e: d819 bhi.n 800bbb4 800bb80: 687b ldr r3, [r7, #4] 800bb82: 691b ldr r3, [r3, #16] 800bb84: 2b40 cmp r3, #64 @ 0x40 800bb86: d108 bne.n 800bb9a 800bb88: 4b09 ldr r3, [pc, #36] @ (800bbb0 ) 800bb8a: 685b ldr r3, [r3, #4] 800bb8c: f423 337c bic.w r3, r3, #258048 @ 0x3f000 800bb90: 4a07 ldr r2, [pc, #28] @ (800bbb0 ) 800bb92: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800bb96: 6053 str r3, [r2, #4] 800bb98: e030 b.n 800bbfc 800bb9a: 4b05 ldr r3, [pc, #20] @ (800bbb0 ) 800bb9c: 685b ldr r3, [r3, #4] 800bb9e: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800bba2: 687b ldr r3, [r7, #4] 800bba4: 691b ldr r3, [r3, #16] 800bba6: 031b lsls r3, r3, #12 800bba8: 4901 ldr r1, [pc, #4] @ (800bbb0 ) 800bbaa: 4313 orrs r3, r2 800bbac: 604b str r3, [r1, #4] 800bbae: e025 b.n 800bbfc 800bbb0: 58024400 .word 0x58024400 800bbb4: 4b9a ldr r3, [pc, #616] @ (800be20 ) 800bbb6: 685b ldr r3, [r3, #4] 800bbb8: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800bbbc: 687b ldr r3, [r7, #4] 800bbbe: 691b ldr r3, [r3, #16] 800bbc0: 061b lsls r3, r3, #24 800bbc2: 4997 ldr r1, [pc, #604] @ (800be20 ) 800bbc4: 4313 orrs r3, r2 800bbc6: 604b str r3, [r1, #4] 800bbc8: e018 b.n 800bbfc } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800bbca: 4b95 ldr r3, [pc, #596] @ (800be20 ) 800bbcc: 681b ldr r3, [r3, #0] 800bbce: 4a94 ldr r2, [pc, #592] @ (800be20 ) 800bbd0: f023 0301 bic.w r3, r3, #1 800bbd4: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bbd6: f7fa f911 bl 8005dfc 800bbda: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800bbdc: e008 b.n 800bbf0 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800bbde: f7fa f90d bl 8005dfc 800bbe2: 4602 mov r2, r0 800bbe4: 6a7b ldr r3, [r7, #36] @ 0x24 800bbe6: 1ad3 subs r3, r2, r3 800bbe8: 2b02 cmp r3, #2 800bbea: d901 bls.n 800bbf0 { return HAL_TIMEOUT; 800bbec: 2303 movs r3, #3 800bbee: e2ed b.n 800c1cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800bbf0: 4b8b ldr r3, [pc, #556] @ (800be20 ) 800bbf2: 681b ldr r3, [r3, #0] 800bbf4: f003 0304 and.w r3, r3, #4 800bbf8: 2b00 cmp r3, #0 800bbfa: d1f0 bne.n 800bbde } } } } /*----------------------------- CSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 800bbfc: 687b ldr r3, [r7, #4] 800bbfe: 681b ldr r3, [r3, #0] 800bc00: f003 0310 and.w r3, r3, #16 800bc04: 2b00 cmp r3, #0 800bc06: f000 80a9 beq.w 800bd5c /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800bc0a: 4b85 ldr r3, [pc, #532] @ (800be20 ) 800bc0c: 691b ldr r3, [r3, #16] 800bc0e: f003 0338 and.w r3, r3, #56 @ 0x38 800bc12: 61bb str r3, [r7, #24] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800bc14: 4b82 ldr r3, [pc, #520] @ (800be20 ) 800bc16: 6a9b ldr r3, [r3, #40] @ 0x28 800bc18: 617b str r3, [r7, #20] if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 800bc1a: 69bb ldr r3, [r7, #24] 800bc1c: 2b08 cmp r3, #8 800bc1e: d007 beq.n 800bc30 800bc20: 69bb ldr r3, [r7, #24] 800bc22: 2b18 cmp r3, #24 800bc24: d13a bne.n 800bc9c 800bc26: 697b ldr r3, [r7, #20] 800bc28: f003 0303 and.w r3, r3, #3 800bc2c: 2b01 cmp r3, #1 800bc2e: d135 bne.n 800bc9c { /* When CSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800bc30: 4b7b ldr r3, [pc, #492] @ (800be20 ) 800bc32: 681b ldr r3, [r3, #0] 800bc34: f403 7380 and.w r3, r3, #256 @ 0x100 800bc38: 2b00 cmp r3, #0 800bc3a: d005 beq.n 800bc48 800bc3c: 687b ldr r3, [r7, #4] 800bc3e: 69db ldr r3, [r3, #28] 800bc40: 2b80 cmp r3, #128 @ 0x80 800bc42: d001 beq.n 800bc48 { return HAL_ERROR; 800bc44: 2301 movs r3, #1 800bc46: e2c1 b.n 800c1cc } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800bc48: f7fa f8e4 bl 8005e14 800bc4c: 4603 mov r3, r0 800bc4e: f241 0203 movw r2, #4099 @ 0x1003 800bc52: 4293 cmp r3, r2 800bc54: d817 bhi.n 800bc86 800bc56: 687b ldr r3, [r7, #4] 800bc58: 6a1b ldr r3, [r3, #32] 800bc5a: 2b20 cmp r3, #32 800bc5c: d108 bne.n 800bc70 800bc5e: 4b70 ldr r3, [pc, #448] @ (800be20 ) 800bc60: 685b ldr r3, [r3, #4] 800bc62: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 800bc66: 4a6e ldr r2, [pc, #440] @ (800be20 ) 800bc68: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800bc6c: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800bc6e: e075 b.n 800bd5c __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800bc70: 4b6b ldr r3, [pc, #428] @ (800be20 ) 800bc72: 685b ldr r3, [r3, #4] 800bc74: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800bc78: 687b ldr r3, [r7, #4] 800bc7a: 6a1b ldr r3, [r3, #32] 800bc7c: 069b lsls r3, r3, #26 800bc7e: 4968 ldr r1, [pc, #416] @ (800be20 ) 800bc80: 4313 orrs r3, r2 800bc82: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800bc84: e06a b.n 800bd5c __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800bc86: 4b66 ldr r3, [pc, #408] @ (800be20 ) 800bc88: 68db ldr r3, [r3, #12] 800bc8a: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 800bc8e: 687b ldr r3, [r7, #4] 800bc90: 6a1b ldr r3, [r3, #32] 800bc92: 061b lsls r3, r3, #24 800bc94: 4962 ldr r1, [pc, #392] @ (800be20 ) 800bc96: 4313 orrs r3, r2 800bc98: 60cb str r3, [r1, #12] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800bc9a: e05f b.n 800bd5c } } else { /* Check the CSI State */ if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) 800bc9c: 687b ldr r3, [r7, #4] 800bc9e: 69db ldr r3, [r3, #28] 800bca0: 2b00 cmp r3, #0 800bca2: d042 beq.n 800bd2a { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 800bca4: 4b5e ldr r3, [pc, #376] @ (800be20 ) 800bca6: 681b ldr r3, [r3, #0] 800bca8: 4a5d ldr r2, [pc, #372] @ (800be20 ) 800bcaa: f043 0380 orr.w r3, r3, #128 @ 0x80 800bcae: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bcb0: f7fa f8a4 bl 8005dfc 800bcb4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800bcb6: e008 b.n 800bcca { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 800bcb8: f7fa f8a0 bl 8005dfc 800bcbc: 4602 mov r2, r0 800bcbe: 6a7b ldr r3, [r7, #36] @ 0x24 800bcc0: 1ad3 subs r3, r2, r3 800bcc2: 2b02 cmp r3, #2 800bcc4: d901 bls.n 800bcca { return HAL_TIMEOUT; 800bcc6: 2303 movs r3, #3 800bcc8: e280 b.n 800c1cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800bcca: 4b55 ldr r3, [pc, #340] @ (800be20 ) 800bccc: 681b ldr r3, [r3, #0] 800bcce: f403 7380 and.w r3, r3, #256 @ 0x100 800bcd2: 2b00 cmp r3, #0 800bcd4: d0f0 beq.n 800bcb8 } } /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800bcd6: f7fa f89d bl 8005e14 800bcda: 4603 mov r3, r0 800bcdc: f241 0203 movw r2, #4099 @ 0x1003 800bce0: 4293 cmp r3, r2 800bce2: d817 bhi.n 800bd14 800bce4: 687b ldr r3, [r7, #4] 800bce6: 6a1b ldr r3, [r3, #32] 800bce8: 2b20 cmp r3, #32 800bcea: d108 bne.n 800bcfe 800bcec: 4b4c ldr r3, [pc, #304] @ (800be20 ) 800bcee: 685b ldr r3, [r3, #4] 800bcf0: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 800bcf4: 4a4a ldr r2, [pc, #296] @ (800be20 ) 800bcf6: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800bcfa: 6053 str r3, [r2, #4] 800bcfc: e02e b.n 800bd5c 800bcfe: 4b48 ldr r3, [pc, #288] @ (800be20 ) 800bd00: 685b ldr r3, [r3, #4] 800bd02: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800bd06: 687b ldr r3, [r7, #4] 800bd08: 6a1b ldr r3, [r3, #32] 800bd0a: 069b lsls r3, r3, #26 800bd0c: 4944 ldr r1, [pc, #272] @ (800be20 ) 800bd0e: 4313 orrs r3, r2 800bd10: 604b str r3, [r1, #4] 800bd12: e023 b.n 800bd5c 800bd14: 4b42 ldr r3, [pc, #264] @ (800be20 ) 800bd16: 68db ldr r3, [r3, #12] 800bd18: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 800bd1c: 687b ldr r3, [r7, #4] 800bd1e: 6a1b ldr r3, [r3, #32] 800bd20: 061b lsls r3, r3, #24 800bd22: 493f ldr r1, [pc, #252] @ (800be20 ) 800bd24: 4313 orrs r3, r2 800bd26: 60cb str r3, [r1, #12] 800bd28: e018 b.n 800bd5c } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 800bd2a: 4b3d ldr r3, [pc, #244] @ (800be20 ) 800bd2c: 681b ldr r3, [r3, #0] 800bd2e: 4a3c ldr r2, [pc, #240] @ (800be20 ) 800bd30: f023 0380 bic.w r3, r3, #128 @ 0x80 800bd34: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bd36: f7fa f861 bl 8005dfc 800bd3a: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800bd3c: e008 b.n 800bd50 { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 800bd3e: f7fa f85d bl 8005dfc 800bd42: 4602 mov r2, r0 800bd44: 6a7b ldr r3, [r7, #36] @ 0x24 800bd46: 1ad3 subs r3, r2, r3 800bd48: 2b02 cmp r3, #2 800bd4a: d901 bls.n 800bd50 { return HAL_TIMEOUT; 800bd4c: 2303 movs r3, #3 800bd4e: e23d b.n 800c1cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800bd50: 4b33 ldr r3, [pc, #204] @ (800be20 ) 800bd52: 681b ldr r3, [r3, #0] 800bd54: f403 7380 and.w r3, r3, #256 @ 0x100 800bd58: 2b00 cmp r3, #0 800bd5a: d1f0 bne.n 800bd3e } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800bd5c: 687b ldr r3, [r7, #4] 800bd5e: 681b ldr r3, [r3, #0] 800bd60: f003 0308 and.w r3, r3, #8 800bd64: 2b00 cmp r3, #0 800bd66: d036 beq.n 800bdd6 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 800bd68: 687b ldr r3, [r7, #4] 800bd6a: 695b ldr r3, [r3, #20] 800bd6c: 2b00 cmp r3, #0 800bd6e: d019 beq.n 800bda4 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800bd70: 4b2b ldr r3, [pc, #172] @ (800be20 ) 800bd72: 6f5b ldr r3, [r3, #116] @ 0x74 800bd74: 4a2a ldr r2, [pc, #168] @ (800be20 ) 800bd76: f043 0301 orr.w r3, r3, #1 800bd7a: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bd7c: f7fa f83e bl 8005dfc 800bd80: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800bd82: e008 b.n 800bd96 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800bd84: f7fa f83a bl 8005dfc 800bd88: 4602 mov r2, r0 800bd8a: 6a7b ldr r3, [r7, #36] @ 0x24 800bd8c: 1ad3 subs r3, r2, r3 800bd8e: 2b02 cmp r3, #2 800bd90: d901 bls.n 800bd96 { return HAL_TIMEOUT; 800bd92: 2303 movs r3, #3 800bd94: e21a b.n 800c1cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800bd96: 4b22 ldr r3, [pc, #136] @ (800be20 ) 800bd98: 6f5b ldr r3, [r3, #116] @ 0x74 800bd9a: f003 0302 and.w r3, r3, #2 800bd9e: 2b00 cmp r3, #0 800bda0: d0f0 beq.n 800bd84 800bda2: e018 b.n 800bdd6 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800bda4: 4b1e ldr r3, [pc, #120] @ (800be20 ) 800bda6: 6f5b ldr r3, [r3, #116] @ 0x74 800bda8: 4a1d ldr r2, [pc, #116] @ (800be20 ) 800bdaa: f023 0301 bic.w r3, r3, #1 800bdae: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bdb0: f7fa f824 bl 8005dfc 800bdb4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800bdb6: e008 b.n 800bdca { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800bdb8: f7fa f820 bl 8005dfc 800bdbc: 4602 mov r2, r0 800bdbe: 6a7b ldr r3, [r7, #36] @ 0x24 800bdc0: 1ad3 subs r3, r2, r3 800bdc2: 2b02 cmp r3, #2 800bdc4: d901 bls.n 800bdca { return HAL_TIMEOUT; 800bdc6: 2303 movs r3, #3 800bdc8: e200 b.n 800c1cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800bdca: 4b15 ldr r3, [pc, #84] @ (800be20 ) 800bdcc: 6f5b ldr r3, [r3, #116] @ 0x74 800bdce: f003 0302 and.w r3, r3, #2 800bdd2: 2b00 cmp r3, #0 800bdd4: d1f0 bne.n 800bdb8 } } } /*------------------------------ HSI48 Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 800bdd6: 687b ldr r3, [r7, #4] 800bdd8: 681b ldr r3, [r3, #0] 800bdda: f003 0320 and.w r3, r3, #32 800bdde: 2b00 cmp r3, #0 800bde0: d039 beq.n 800be56 { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) 800bde2: 687b ldr r3, [r7, #4] 800bde4: 699b ldr r3, [r3, #24] 800bde6: 2b00 cmp r3, #0 800bde8: d01c beq.n 800be24 { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 800bdea: 4b0d ldr r3, [pc, #52] @ (800be20 ) 800bdec: 681b ldr r3, [r3, #0] 800bdee: 4a0c ldr r2, [pc, #48] @ (800be20 ) 800bdf0: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800bdf4: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800bdf6: f7fa f801 bl 8005dfc 800bdfa: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 800bdfc: e008 b.n 800be10 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800bdfe: f7f9 fffd bl 8005dfc 800be02: 4602 mov r2, r0 800be04: 6a7b ldr r3, [r7, #36] @ 0x24 800be06: 1ad3 subs r3, r2, r3 800be08: 2b02 cmp r3, #2 800be0a: d901 bls.n 800be10 { return HAL_TIMEOUT; 800be0c: 2303 movs r3, #3 800be0e: e1dd b.n 800c1cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 800be10: 4b03 ldr r3, [pc, #12] @ (800be20 ) 800be12: 681b ldr r3, [r3, #0] 800be14: f403 5300 and.w r3, r3, #8192 @ 0x2000 800be18: 2b00 cmp r3, #0 800be1a: d0f0 beq.n 800bdfe 800be1c: e01b b.n 800be56 800be1e: bf00 nop 800be20: 58024400 .word 0x58024400 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 800be24: 4b9b ldr r3, [pc, #620] @ (800c094 ) 800be26: 681b ldr r3, [r3, #0] 800be28: 4a9a ldr r2, [pc, #616] @ (800c094 ) 800be2a: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800be2e: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800be30: f7f9 ffe4 bl 8005dfc 800be34: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800be36: e008 b.n 800be4a { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800be38: f7f9 ffe0 bl 8005dfc 800be3c: 4602 mov r2, r0 800be3e: 6a7b ldr r3, [r7, #36] @ 0x24 800be40: 1ad3 subs r3, r2, r3 800be42: 2b02 cmp r3, #2 800be44: d901 bls.n 800be4a { return HAL_TIMEOUT; 800be46: 2303 movs r3, #3 800be48: e1c0 b.n 800c1cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800be4a: 4b92 ldr r3, [pc, #584] @ (800c094 ) 800be4c: 681b ldr r3, [r3, #0] 800be4e: f403 5300 and.w r3, r3, #8192 @ 0x2000 800be52: 2b00 cmp r3, #0 800be54: d1f0 bne.n 800be38 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800be56: 687b ldr r3, [r7, #4] 800be58: 681b ldr r3, [r3, #0] 800be5a: f003 0304 and.w r3, r3, #4 800be5e: 2b00 cmp r3, #0 800be60: f000 8081 beq.w 800bf66 { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 800be64: 4b8c ldr r3, [pc, #560] @ (800c098 ) 800be66: 681b ldr r3, [r3, #0] 800be68: 4a8b ldr r2, [pc, #556] @ (800c098 ) 800be6a: f443 7380 orr.w r3, r3, #256 @ 0x100 800be6e: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800be70: f7f9 ffc4 bl 8005dfc 800be74: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800be76: e008 b.n 800be8a { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800be78: f7f9 ffc0 bl 8005dfc 800be7c: 4602 mov r2, r0 800be7e: 6a7b ldr r3, [r7, #36] @ 0x24 800be80: 1ad3 subs r3, r2, r3 800be82: 2b64 cmp r3, #100 @ 0x64 800be84: d901 bls.n 800be8a { return HAL_TIMEOUT; 800be86: 2303 movs r3, #3 800be88: e1a0 b.n 800c1cc while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800be8a: 4b83 ldr r3, [pc, #524] @ (800c098 ) 800be8c: 681b ldr r3, [r3, #0] 800be8e: f403 7380 and.w r3, r3, #256 @ 0x100 800be92: 2b00 cmp r3, #0 800be94: d0f0 beq.n 800be78 } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800be96: 687b ldr r3, [r7, #4] 800be98: 689b ldr r3, [r3, #8] 800be9a: 2b01 cmp r3, #1 800be9c: d106 bne.n 800beac 800be9e: 4b7d ldr r3, [pc, #500] @ (800c094 ) 800bea0: 6f1b ldr r3, [r3, #112] @ 0x70 800bea2: 4a7c ldr r2, [pc, #496] @ (800c094 ) 800bea4: f043 0301 orr.w r3, r3, #1 800bea8: 6713 str r3, [r2, #112] @ 0x70 800beaa: e02d b.n 800bf08 800beac: 687b ldr r3, [r7, #4] 800beae: 689b ldr r3, [r3, #8] 800beb0: 2b00 cmp r3, #0 800beb2: d10c bne.n 800bece 800beb4: 4b77 ldr r3, [pc, #476] @ (800c094 ) 800beb6: 6f1b ldr r3, [r3, #112] @ 0x70 800beb8: 4a76 ldr r2, [pc, #472] @ (800c094 ) 800beba: f023 0301 bic.w r3, r3, #1 800bebe: 6713 str r3, [r2, #112] @ 0x70 800bec0: 4b74 ldr r3, [pc, #464] @ (800c094 ) 800bec2: 6f1b ldr r3, [r3, #112] @ 0x70 800bec4: 4a73 ldr r2, [pc, #460] @ (800c094 ) 800bec6: f023 0304 bic.w r3, r3, #4 800beca: 6713 str r3, [r2, #112] @ 0x70 800becc: e01c b.n 800bf08 800bece: 687b ldr r3, [r7, #4] 800bed0: 689b ldr r3, [r3, #8] 800bed2: 2b05 cmp r3, #5 800bed4: d10c bne.n 800bef0 800bed6: 4b6f ldr r3, [pc, #444] @ (800c094 ) 800bed8: 6f1b ldr r3, [r3, #112] @ 0x70 800beda: 4a6e ldr r2, [pc, #440] @ (800c094 ) 800bedc: f043 0304 orr.w r3, r3, #4 800bee0: 6713 str r3, [r2, #112] @ 0x70 800bee2: 4b6c ldr r3, [pc, #432] @ (800c094 ) 800bee4: 6f1b ldr r3, [r3, #112] @ 0x70 800bee6: 4a6b ldr r2, [pc, #428] @ (800c094 ) 800bee8: f043 0301 orr.w r3, r3, #1 800beec: 6713 str r3, [r2, #112] @ 0x70 800beee: e00b b.n 800bf08 800bef0: 4b68 ldr r3, [pc, #416] @ (800c094 ) 800bef2: 6f1b ldr r3, [r3, #112] @ 0x70 800bef4: 4a67 ldr r2, [pc, #412] @ (800c094 ) 800bef6: f023 0301 bic.w r3, r3, #1 800befa: 6713 str r3, [r2, #112] @ 0x70 800befc: 4b65 ldr r3, [pc, #404] @ (800c094 ) 800befe: 6f1b ldr r3, [r3, #112] @ 0x70 800bf00: 4a64 ldr r2, [pc, #400] @ (800c094 ) 800bf02: f023 0304 bic.w r3, r3, #4 800bf06: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 800bf08: 687b ldr r3, [r7, #4] 800bf0a: 689b ldr r3, [r3, #8] 800bf0c: 2b00 cmp r3, #0 800bf0e: d015 beq.n 800bf3c { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bf10: f7f9 ff74 bl 8005dfc 800bf14: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800bf16: e00a b.n 800bf2e { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800bf18: f7f9 ff70 bl 8005dfc 800bf1c: 4602 mov r2, r0 800bf1e: 6a7b ldr r3, [r7, #36] @ 0x24 800bf20: 1ad3 subs r3, r2, r3 800bf22: f241 3288 movw r2, #5000 @ 0x1388 800bf26: 4293 cmp r3, r2 800bf28: d901 bls.n 800bf2e { return HAL_TIMEOUT; 800bf2a: 2303 movs r3, #3 800bf2c: e14e b.n 800c1cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800bf2e: 4b59 ldr r3, [pc, #356] @ (800c094 ) 800bf30: 6f1b ldr r3, [r3, #112] @ 0x70 800bf32: f003 0302 and.w r3, r3, #2 800bf36: 2b00 cmp r3, #0 800bf38: d0ee beq.n 800bf18 800bf3a: e014 b.n 800bf66 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bf3c: f7f9 ff5e bl 8005dfc 800bf40: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800bf42: e00a b.n 800bf5a { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800bf44: f7f9 ff5a bl 8005dfc 800bf48: 4602 mov r2, r0 800bf4a: 6a7b ldr r3, [r7, #36] @ 0x24 800bf4c: 1ad3 subs r3, r2, r3 800bf4e: f241 3288 movw r2, #5000 @ 0x1388 800bf52: 4293 cmp r3, r2 800bf54: d901 bls.n 800bf5a { return HAL_TIMEOUT; 800bf56: 2303 movs r3, #3 800bf58: e138 b.n 800c1cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800bf5a: 4b4e ldr r3, [pc, #312] @ (800c094 ) 800bf5c: 6f1b ldr r3, [r3, #112] @ 0x70 800bf5e: f003 0302 and.w r3, r3, #2 800bf62: 2b00 cmp r3, #0 800bf64: d1ee bne.n 800bf44 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800bf66: 687b ldr r3, [r7, #4] 800bf68: 6a5b ldr r3, [r3, #36] @ 0x24 800bf6a: 2b00 cmp r3, #0 800bf6c: f000 812d beq.w 800c1ca { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 800bf70: 4b48 ldr r3, [pc, #288] @ (800c094 ) 800bf72: 691b ldr r3, [r3, #16] 800bf74: f003 0338 and.w r3, r3, #56 @ 0x38 800bf78: 2b18 cmp r3, #24 800bf7a: f000 80bd beq.w 800c0f8 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 800bf7e: 687b ldr r3, [r7, #4] 800bf80: 6a5b ldr r3, [r3, #36] @ 0x24 800bf82: 2b02 cmp r3, #2 800bf84: f040 809e bne.w 800c0c4 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800bf88: 4b42 ldr r3, [pc, #264] @ (800c094 ) 800bf8a: 681b ldr r3, [r3, #0] 800bf8c: 4a41 ldr r2, [pc, #260] @ (800c094 ) 800bf8e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800bf92: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bf94: f7f9 ff32 bl 8005dfc 800bf98: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800bf9a: e008 b.n 800bfae { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800bf9c: f7f9 ff2e bl 8005dfc 800bfa0: 4602 mov r2, r0 800bfa2: 6a7b ldr r3, [r7, #36] @ 0x24 800bfa4: 1ad3 subs r3, r2, r3 800bfa6: 2b02 cmp r3, #2 800bfa8: d901 bls.n 800bfae { return HAL_TIMEOUT; 800bfaa: 2303 movs r3, #3 800bfac: e10e b.n 800c1cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800bfae: 4b39 ldr r3, [pc, #228] @ (800c094 ) 800bfb0: 681b ldr r3, [r3, #0] 800bfb2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800bfb6: 2b00 cmp r3, #0 800bfb8: d1f0 bne.n 800bf9c } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 800bfba: 4b36 ldr r3, [pc, #216] @ (800c094 ) 800bfbc: 6a9a ldr r2, [r3, #40] @ 0x28 800bfbe: 4b37 ldr r3, [pc, #220] @ (800c09c ) 800bfc0: 4013 ands r3, r2 800bfc2: 687a ldr r2, [r7, #4] 800bfc4: 6a91 ldr r1, [r2, #40] @ 0x28 800bfc6: 687a ldr r2, [r7, #4] 800bfc8: 6ad2 ldr r2, [r2, #44] @ 0x2c 800bfca: 0112 lsls r2, r2, #4 800bfcc: 430a orrs r2, r1 800bfce: 4931 ldr r1, [pc, #196] @ (800c094 ) 800bfd0: 4313 orrs r3, r2 800bfd2: 628b str r3, [r1, #40] @ 0x28 800bfd4: 687b ldr r3, [r7, #4] 800bfd6: 6b1b ldr r3, [r3, #48] @ 0x30 800bfd8: 3b01 subs r3, #1 800bfda: f3c3 0208 ubfx r2, r3, #0, #9 800bfde: 687b ldr r3, [r7, #4] 800bfe0: 6b5b ldr r3, [r3, #52] @ 0x34 800bfe2: 3b01 subs r3, #1 800bfe4: 025b lsls r3, r3, #9 800bfe6: b29b uxth r3, r3 800bfe8: 431a orrs r2, r3 800bfea: 687b ldr r3, [r7, #4] 800bfec: 6b9b ldr r3, [r3, #56] @ 0x38 800bfee: 3b01 subs r3, #1 800bff0: 041b lsls r3, r3, #16 800bff2: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800bff6: 431a orrs r2, r3 800bff8: 687b ldr r3, [r7, #4] 800bffa: 6bdb ldr r3, [r3, #60] @ 0x3c 800bffc: 3b01 subs r3, #1 800bffe: 061b lsls r3, r3, #24 800c000: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800c004: 4923 ldr r1, [pc, #140] @ (800c094 ) 800c006: 4313 orrs r3, r2 800c008: 630b str r3, [r1, #48] @ 0x30 RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Disable PLLFRACN . */ __HAL_RCC_PLLFRACN_DISABLE(); 800c00a: 4b22 ldr r3, [pc, #136] @ (800c094 ) 800c00c: 6adb ldr r3, [r3, #44] @ 0x2c 800c00e: 4a21 ldr r2, [pc, #132] @ (800c094 ) 800c010: f023 0301 bic.w r3, r3, #1 800c014: 62d3 str r3, [r2, #44] @ 0x2c /* Configure PLL PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800c016: 4b1f ldr r3, [pc, #124] @ (800c094 ) 800c018: 6b5a ldr r2, [r3, #52] @ 0x34 800c01a: 4b21 ldr r3, [pc, #132] @ (800c0a0 ) 800c01c: 4013 ands r3, r2 800c01e: 687a ldr r2, [r7, #4] 800c020: 6c92 ldr r2, [r2, #72] @ 0x48 800c022: 00d2 lsls r2, r2, #3 800c024: 491b ldr r1, [pc, #108] @ (800c094 ) 800c026: 4313 orrs r3, r2 800c028: 634b str r3, [r1, #52] @ 0x34 /* Select PLL1 input reference frequency range: VCI */ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 800c02a: 4b1a ldr r3, [pc, #104] @ (800c094 ) 800c02c: 6adb ldr r3, [r3, #44] @ 0x2c 800c02e: f023 020c bic.w r2, r3, #12 800c032: 687b ldr r3, [r7, #4] 800c034: 6c1b ldr r3, [r3, #64] @ 0x40 800c036: 4917 ldr r1, [pc, #92] @ (800c094 ) 800c038: 4313 orrs r3, r2 800c03a: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL1 output frequency range : VCO */ __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 800c03c: 4b15 ldr r3, [pc, #84] @ (800c094 ) 800c03e: 6adb ldr r3, [r3, #44] @ 0x2c 800c040: f023 0202 bic.w r2, r3, #2 800c044: 687b ldr r3, [r7, #4] 800c046: 6c5b ldr r3, [r3, #68] @ 0x44 800c048: 4912 ldr r1, [pc, #72] @ (800c094 ) 800c04a: 4313 orrs r3, r2 800c04c: 62cb str r3, [r1, #44] @ 0x2c /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 800c04e: 4b11 ldr r3, [pc, #68] @ (800c094 ) 800c050: 6adb ldr r3, [r3, #44] @ 0x2c 800c052: 4a10 ldr r2, [pc, #64] @ (800c094 ) 800c054: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800c058: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1Q Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c05a: 4b0e ldr r3, [pc, #56] @ (800c094 ) 800c05c: 6adb ldr r3, [r3, #44] @ 0x2c 800c05e: 4a0d ldr r2, [pc, #52] @ (800c094 ) 800c060: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c064: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1R Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 800c066: 4b0b ldr r3, [pc, #44] @ (800c094 ) 800c068: 6adb ldr r3, [r3, #44] @ 0x2c 800c06a: 4a0a ldr r2, [pc, #40] @ (800c094 ) 800c06c: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800c070: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1FRACN . */ __HAL_RCC_PLLFRACN_ENABLE(); 800c072: 4b08 ldr r3, [pc, #32] @ (800c094 ) 800c074: 6adb ldr r3, [r3, #44] @ 0x2c 800c076: 4a07 ldr r2, [pc, #28] @ (800c094 ) 800c078: f043 0301 orr.w r3, r3, #1 800c07c: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800c07e: 4b05 ldr r3, [pc, #20] @ (800c094 ) 800c080: 681b ldr r3, [r3, #0] 800c082: 4a04 ldr r2, [pc, #16] @ (800c094 ) 800c084: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800c088: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c08a: f7f9 feb7 bl 8005dfc 800c08e: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800c090: e011 b.n 800c0b6 800c092: bf00 nop 800c094: 58024400 .word 0x58024400 800c098: 58024800 .word 0x58024800 800c09c: fffffc0c .word 0xfffffc0c 800c0a0: ffff0007 .word 0xffff0007 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800c0a4: f7f9 feaa bl 8005dfc 800c0a8: 4602 mov r2, r0 800c0aa: 6a7b ldr r3, [r7, #36] @ 0x24 800c0ac: 1ad3 subs r3, r2, r3 800c0ae: 2b02 cmp r3, #2 800c0b0: d901 bls.n 800c0b6 { return HAL_TIMEOUT; 800c0b2: 2303 movs r3, #3 800c0b4: e08a b.n 800c1cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800c0b6: 4b47 ldr r3, [pc, #284] @ (800c1d4 ) 800c0b8: 681b ldr r3, [r3, #0] 800c0ba: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800c0be: 2b00 cmp r3, #0 800c0c0: d0f0 beq.n 800c0a4 800c0c2: e082 b.n 800c1ca } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800c0c4: 4b43 ldr r3, [pc, #268] @ (800c1d4 ) 800c0c6: 681b ldr r3, [r3, #0] 800c0c8: 4a42 ldr r2, [pc, #264] @ (800c1d4 ) 800c0ca: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800c0ce: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c0d0: f7f9 fe94 bl 8005dfc 800c0d4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800c0d6: e008 b.n 800c0ea { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800c0d8: f7f9 fe90 bl 8005dfc 800c0dc: 4602 mov r2, r0 800c0de: 6a7b ldr r3, [r7, #36] @ 0x24 800c0e0: 1ad3 subs r3, r2, r3 800c0e2: 2b02 cmp r3, #2 800c0e4: d901 bls.n 800c0ea { return HAL_TIMEOUT; 800c0e6: 2303 movs r3, #3 800c0e8: e070 b.n 800c1cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800c0ea: 4b3a ldr r3, [pc, #232] @ (800c1d4 ) 800c0ec: 681b ldr r3, [r3, #0] 800c0ee: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800c0f2: 2b00 cmp r3, #0 800c0f4: d1f0 bne.n 800c0d8 800c0f6: e068 b.n 800c1ca } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp1_pllckcfg = RCC->PLLCKSELR; 800c0f8: 4b36 ldr r3, [pc, #216] @ (800c1d4 ) 800c0fa: 6a9b ldr r3, [r3, #40] @ 0x28 800c0fc: 613b str r3, [r7, #16] temp2_pllckcfg = RCC->PLL1DIVR; 800c0fe: 4b35 ldr r3, [pc, #212] @ (800c1d4 ) 800c100: 6b1b ldr r3, [r3, #48] @ 0x30 800c102: 60fb str r3, [r7, #12] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800c104: 687b ldr r3, [r7, #4] 800c106: 6a5b ldr r3, [r3, #36] @ 0x24 800c108: 2b01 cmp r3, #1 800c10a: d031 beq.n 800c170 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800c10c: 693b ldr r3, [r7, #16] 800c10e: f003 0203 and.w r2, r3, #3 800c112: 687b ldr r3, [r7, #4] 800c114: 6a9b ldr r3, [r3, #40] @ 0x28 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800c116: 429a cmp r2, r3 800c118: d12a bne.n 800c170 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800c11a: 693b ldr r3, [r7, #16] 800c11c: 091b lsrs r3, r3, #4 800c11e: f003 023f and.w r2, r3, #63 @ 0x3f 800c122: 687b ldr r3, [r7, #4] 800c124: 6adb ldr r3, [r3, #44] @ 0x2c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800c126: 429a cmp r2, r3 800c128: d122 bne.n 800c170 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800c12a: 68fb ldr r3, [r7, #12] 800c12c: f3c3 0208 ubfx r2, r3, #0, #9 800c130: 687b ldr r3, [r7, #4] 800c132: 6b1b ldr r3, [r3, #48] @ 0x30 800c134: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800c136: 429a cmp r2, r3 800c138: d11a bne.n 800c170 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800c13a: 68fb ldr r3, [r7, #12] 800c13c: 0a5b lsrs r3, r3, #9 800c13e: f003 027f and.w r2, r3, #127 @ 0x7f 800c142: 687b ldr r3, [r7, #4] 800c144: 6b5b ldr r3, [r3, #52] @ 0x34 800c146: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800c148: 429a cmp r2, r3 800c14a: d111 bne.n 800c170 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 800c14c: 68fb ldr r3, [r7, #12] 800c14e: 0c1b lsrs r3, r3, #16 800c150: f003 027f and.w r2, r3, #127 @ 0x7f 800c154: 687b ldr r3, [r7, #4] 800c156: 6b9b ldr r3, [r3, #56] @ 0x38 800c158: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800c15a: 429a cmp r2, r3 800c15c: d108 bne.n 800c170 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 800c15e: 68fb ldr r3, [r7, #12] 800c160: 0e1b lsrs r3, r3, #24 800c162: f003 027f and.w r2, r3, #127 @ 0x7f 800c166: 687b ldr r3, [r7, #4] 800c168: 6bdb ldr r3, [r3, #60] @ 0x3c 800c16a: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 800c16c: 429a cmp r2, r3 800c16e: d001 beq.n 800c174 { return HAL_ERROR; 800c170: 2301 movs r3, #1 800c172: e02b b.n 800c1cc } else { /* Check if only fractional part needs to be updated */ temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); 800c174: 4b17 ldr r3, [pc, #92] @ (800c1d4 ) 800c176: 6b5b ldr r3, [r3, #52] @ 0x34 800c178: 08db lsrs r3, r3, #3 800c17a: f3c3 030c ubfx r3, r3, #0, #13 800c17e: 613b str r3, [r7, #16] if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) 800c180: 687b ldr r3, [r7, #4] 800c182: 6c9b ldr r3, [r3, #72] @ 0x48 800c184: 693a ldr r2, [r7, #16] 800c186: 429a cmp r2, r3 800c188: d01f beq.n 800c1ca { assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable PLL1FRACEN */ __HAL_RCC_PLLFRACN_DISABLE(); 800c18a: 4b12 ldr r3, [pc, #72] @ (800c1d4 ) 800c18c: 6adb ldr r3, [r3, #44] @ 0x2c 800c18e: 4a11 ldr r2, [pc, #68] @ (800c1d4 ) 800c190: f023 0301 bic.w r3, r3, #1 800c194: 62d3 str r3, [r2, #44] @ 0x2c /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c196: f7f9 fe31 bl 8005dfc 800c19a: 6278 str r0, [r7, #36] @ 0x24 /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) 800c19c: bf00 nop 800c19e: f7f9 fe2d bl 8005dfc 800c1a2: 4602 mov r2, r0 800c1a4: 6a7b ldr r3, [r7, #36] @ 0x24 800c1a6: 4293 cmp r3, r2 800c1a8: d0f9 beq.n 800c19e { } /* Configure PLL1 PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800c1aa: 4b0a ldr r3, [pc, #40] @ (800c1d4 ) 800c1ac: 6b5a ldr r2, [r3, #52] @ 0x34 800c1ae: 4b0a ldr r3, [pc, #40] @ (800c1d8 ) 800c1b0: 4013 ands r3, r2 800c1b2: 687a ldr r2, [r7, #4] 800c1b4: 6c92 ldr r2, [r2, #72] @ 0x48 800c1b6: 00d2 lsls r2, r2, #3 800c1b8: 4906 ldr r1, [pc, #24] @ (800c1d4 ) 800c1ba: 4313 orrs r3, r2 800c1bc: 634b str r3, [r1, #52] @ 0x34 /* Enable PLL1FRACEN to latch new value. */ __HAL_RCC_PLLFRACN_ENABLE(); 800c1be: 4b05 ldr r3, [pc, #20] @ (800c1d4 ) 800c1c0: 6adb ldr r3, [r3, #44] @ 0x2c 800c1c2: 4a04 ldr r2, [pc, #16] @ (800c1d4 ) 800c1c4: f043 0301 orr.w r3, r3, #1 800c1c8: 62d3 str r3, [r2, #44] @ 0x2c } } } } return HAL_OK; 800c1ca: 2300 movs r3, #0 } 800c1cc: 4618 mov r0, r3 800c1ce: 3730 adds r7, #48 @ 0x30 800c1d0: 46bd mov sp, r7 800c1d2: bd80 pop {r7, pc} 800c1d4: 58024400 .word 0x58024400 800c1d8: ffff0007 .word 0xffff0007 0800c1dc : * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800c1dc: b580 push {r7, lr} 800c1de: b086 sub sp, #24 800c1e0: af00 add r7, sp, #0 800c1e2: 6078 str r0, [r7, #4] 800c1e4: 6039 str r1, [r7, #0] HAL_StatusTypeDef halstatus; uint32_t tickstart; uint32_t common_system_clock; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800c1e6: 687b ldr r3, [r7, #4] 800c1e8: 2b00 cmp r3, #0 800c1ea: d101 bne.n 800c1f0 { return HAL_ERROR; 800c1ec: 2301 movs r3, #1 800c1ee: e19c b.n 800c52a /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 800c1f0: 4b8a ldr r3, [pc, #552] @ (800c41c ) 800c1f2: 681b ldr r3, [r3, #0] 800c1f4: f003 030f and.w r3, r3, #15 800c1f8: 683a ldr r2, [r7, #0] 800c1fa: 429a cmp r2, r3 800c1fc: d910 bls.n 800c220 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800c1fe: 4b87 ldr r3, [pc, #540] @ (800c41c ) 800c200: 681b ldr r3, [r3, #0] 800c202: f023 020f bic.w r2, r3, #15 800c206: 4985 ldr r1, [pc, #532] @ (800c41c ) 800c208: 683b ldr r3, [r7, #0] 800c20a: 4313 orrs r3, r2 800c20c: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800c20e: 4b83 ldr r3, [pc, #524] @ (800c41c ) 800c210: 681b ldr r3, [r3, #0] 800c212: f003 030f and.w r3, r3, #15 800c216: 683a ldr r2, [r7, #0] 800c218: 429a cmp r2, r3 800c21a: d001 beq.n 800c220 { return HAL_ERROR; 800c21c: 2301 movs r3, #1 800c21e: e184 b.n 800c52a } /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 800c220: 687b ldr r3, [r7, #4] 800c222: 681b ldr r3, [r3, #0] 800c224: f003 0304 and.w r3, r3, #4 800c228: 2b00 cmp r3, #0 800c22a: d010 beq.n 800c24e { #if defined (RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 800c22c: 687b ldr r3, [r7, #4] 800c22e: 691a ldr r2, [r3, #16] 800c230: 4b7b ldr r3, [pc, #492] @ (800c420 ) 800c232: 699b ldr r3, [r3, #24] 800c234: f003 0370 and.w r3, r3, #112 @ 0x70 800c238: 429a cmp r2, r3 800c23a: d908 bls.n 800c24e { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 800c23c: 4b78 ldr r3, [pc, #480] @ (800c420 ) 800c23e: 699b ldr r3, [r3, #24] 800c240: f023 0270 bic.w r2, r3, #112 @ 0x70 800c244: 687b ldr r3, [r7, #4] 800c246: 691b ldr r3, [r3, #16] 800c248: 4975 ldr r1, [pc, #468] @ (800c420 ) 800c24a: 4313 orrs r3, r2 800c24c: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800c24e: 687b ldr r3, [r7, #4] 800c250: 681b ldr r3, [r3, #0] 800c252: f003 0308 and.w r3, r3, #8 800c256: 2b00 cmp r3, #0 800c258: d010 beq.n 800c27c { #if defined (RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800c25a: 687b ldr r3, [r7, #4] 800c25c: 695a ldr r2, [r3, #20] 800c25e: 4b70 ldr r3, [pc, #448] @ (800c420 ) 800c260: 69db ldr r3, [r3, #28] 800c262: f003 0370 and.w r3, r3, #112 @ 0x70 800c266: 429a cmp r2, r3 800c268: d908 bls.n 800c27c { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800c26a: 4b6d ldr r3, [pc, #436] @ (800c420 ) 800c26c: 69db ldr r3, [r3, #28] 800c26e: f023 0270 bic.w r2, r3, #112 @ 0x70 800c272: 687b ldr r3, [r7, #4] 800c274: 695b ldr r3, [r3, #20] 800c276: 496a ldr r1, [pc, #424] @ (800c420 ) 800c278: 4313 orrs r3, r2 800c27a: 61cb str r3, [r1, #28] MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800c27c: 687b ldr r3, [r7, #4] 800c27e: 681b ldr r3, [r3, #0] 800c280: f003 0310 and.w r3, r3, #16 800c284: 2b00 cmp r3, #0 800c286: d010 beq.n 800c2aa { #if defined(RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800c288: 687b ldr r3, [r7, #4] 800c28a: 699a ldr r2, [r3, #24] 800c28c: 4b64 ldr r3, [pc, #400] @ (800c420 ) 800c28e: 69db ldr r3, [r3, #28] 800c290: f403 63e0 and.w r3, r3, #1792 @ 0x700 800c294: 429a cmp r2, r3 800c296: d908 bls.n 800c2aa { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800c298: 4b61 ldr r3, [pc, #388] @ (800c420 ) 800c29a: 69db ldr r3, [r3, #28] 800c29c: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800c2a0: 687b ldr r3, [r7, #4] 800c2a2: 699b ldr r3, [r3, #24] 800c2a4: 495e ldr r1, [pc, #376] @ (800c420 ) 800c2a6: 4313 orrs r3, r2 800c2a8: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800c2aa: 687b ldr r3, [r7, #4] 800c2ac: 681b ldr r3, [r3, #0] 800c2ae: f003 0320 and.w r3, r3, #32 800c2b2: 2b00 cmp r3, #0 800c2b4: d010 beq.n 800c2d8 { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800c2b6: 687b ldr r3, [r7, #4] 800c2b8: 69da ldr r2, [r3, #28] 800c2ba: 4b59 ldr r3, [pc, #356] @ (800c420 ) 800c2bc: 6a1b ldr r3, [r3, #32] 800c2be: f003 0370 and.w r3, r3, #112 @ 0x70 800c2c2: 429a cmp r2, r3 800c2c4: d908 bls.n 800c2d8 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800c2c6: 4b56 ldr r3, [pc, #344] @ (800c420 ) 800c2c8: 6a1b ldr r3, [r3, #32] 800c2ca: f023 0270 bic.w r2, r3, #112 @ 0x70 800c2ce: 687b ldr r3, [r7, #4] 800c2d0: 69db ldr r3, [r3, #28] 800c2d2: 4953 ldr r1, [pc, #332] @ (800c420 ) 800c2d4: 4313 orrs r3, r2 800c2d6: 620b str r3, [r1, #32] } #endif } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800c2d8: 687b ldr r3, [r7, #4] 800c2da: 681b ldr r3, [r3, #0] 800c2dc: f003 0302 and.w r3, r3, #2 800c2e0: 2b00 cmp r3, #0 800c2e2: d010 beq.n 800c306 { #if defined (RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800c2e4: 687b ldr r3, [r7, #4] 800c2e6: 68da ldr r2, [r3, #12] 800c2e8: 4b4d ldr r3, [pc, #308] @ (800c420 ) 800c2ea: 699b ldr r3, [r3, #24] 800c2ec: f003 030f and.w r3, r3, #15 800c2f0: 429a cmp r2, r3 800c2f2: d908 bls.n 800c306 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800c2f4: 4b4a ldr r3, [pc, #296] @ (800c420 ) 800c2f6: 699b ldr r3, [r3, #24] 800c2f8: f023 020f bic.w r2, r3, #15 800c2fc: 687b ldr r3, [r7, #4] 800c2fe: 68db ldr r3, [r3, #12] 800c300: 4947 ldr r1, [pc, #284] @ (800c420 ) 800c302: 4313 orrs r3, r2 800c304: 618b str r3, [r1, #24] } #endif } /*------------------------- SYSCLK Configuration -------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800c306: 687b ldr r3, [r7, #4] 800c308: 681b ldr r3, [r3, #0] 800c30a: f003 0301 and.w r3, r3, #1 800c30e: 2b00 cmp r3, #0 800c310: d055 beq.n 800c3be { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_D1CFGR_D1CPRE) MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); 800c312: 4b43 ldr r3, [pc, #268] @ (800c420 ) 800c314: 699b ldr r3, [r3, #24] 800c316: f423 6270 bic.w r2, r3, #3840 @ 0xf00 800c31a: 687b ldr r3, [r7, #4] 800c31c: 689b ldr r3, [r3, #8] 800c31e: 4940 ldr r1, [pc, #256] @ (800c420 ) 800c320: 4313 orrs r3, r2 800c322: 618b str r3, [r1, #24] #else MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); #endif /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800c324: 687b ldr r3, [r7, #4] 800c326: 685b ldr r3, [r3, #4] 800c328: 2b02 cmp r3, #2 800c32a: d107 bne.n 800c33c { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800c32c: 4b3c ldr r3, [pc, #240] @ (800c420 ) 800c32e: 681b ldr r3, [r3, #0] 800c330: f403 3300 and.w r3, r3, #131072 @ 0x20000 800c334: 2b00 cmp r3, #0 800c336: d121 bne.n 800c37c { return HAL_ERROR; 800c338: 2301 movs r3, #1 800c33a: e0f6 b.n 800c52a } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800c33c: 687b ldr r3, [r7, #4] 800c33e: 685b ldr r3, [r3, #4] 800c340: 2b03 cmp r3, #3 800c342: d107 bne.n 800c354 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800c344: 4b36 ldr r3, [pc, #216] @ (800c420 ) 800c346: 681b ldr r3, [r3, #0] 800c348: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800c34c: 2b00 cmp r3, #0 800c34e: d115 bne.n 800c37c { return HAL_ERROR; 800c350: 2301 movs r3, #1 800c352: e0ea b.n 800c52a } } /* CSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 800c354: 687b ldr r3, [r7, #4] 800c356: 685b ldr r3, [r3, #4] 800c358: 2b01 cmp r3, #1 800c35a: d107 bne.n 800c36c { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800c35c: 4b30 ldr r3, [pc, #192] @ (800c420 ) 800c35e: 681b ldr r3, [r3, #0] 800c360: f403 7380 and.w r3, r3, #256 @ 0x100 800c364: 2b00 cmp r3, #0 800c366: d109 bne.n 800c37c { return HAL_ERROR; 800c368: 2301 movs r3, #1 800c36a: e0de b.n 800c52a } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800c36c: 4b2c ldr r3, [pc, #176] @ (800c420 ) 800c36e: 681b ldr r3, [r3, #0] 800c370: f003 0304 and.w r3, r3, #4 800c374: 2b00 cmp r3, #0 800c376: d101 bne.n 800c37c { return HAL_ERROR; 800c378: 2301 movs r3, #1 800c37a: e0d6 b.n 800c52a } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 800c37c: 4b28 ldr r3, [pc, #160] @ (800c420 ) 800c37e: 691b ldr r3, [r3, #16] 800c380: f023 0207 bic.w r2, r3, #7 800c384: 687b ldr r3, [r7, #4] 800c386: 685b ldr r3, [r3, #4] 800c388: 4925 ldr r1, [pc, #148] @ (800c420 ) 800c38a: 4313 orrs r3, r2 800c38c: 610b str r3, [r1, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c38e: f7f9 fd35 bl 8005dfc 800c392: 6178 str r0, [r7, #20] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800c394: e00a b.n 800c3ac { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800c396: f7f9 fd31 bl 8005dfc 800c39a: 4602 mov r2, r0 800c39c: 697b ldr r3, [r7, #20] 800c39e: 1ad3 subs r3, r2, r3 800c3a0: f241 3288 movw r2, #5000 @ 0x1388 800c3a4: 4293 cmp r3, r2 800c3a6: d901 bls.n 800c3ac { return HAL_TIMEOUT; 800c3a8: 2303 movs r3, #3 800c3aa: e0be b.n 800c52a while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800c3ac: 4b1c ldr r3, [pc, #112] @ (800c420 ) 800c3ae: 691b ldr r3, [r3, #16] 800c3b0: f003 0238 and.w r2, r3, #56 @ 0x38 800c3b4: 687b ldr r3, [r7, #4] 800c3b6: 685b ldr r3, [r3, #4] 800c3b8: 00db lsls r3, r3, #3 800c3ba: 429a cmp r2, r3 800c3bc: d1eb bne.n 800c396 } /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800c3be: 687b ldr r3, [r7, #4] 800c3c0: 681b ldr r3, [r3, #0] 800c3c2: f003 0302 and.w r3, r3, #2 800c3c6: 2b00 cmp r3, #0 800c3c8: d010 beq.n 800c3ec { #if defined(RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800c3ca: 687b ldr r3, [r7, #4] 800c3cc: 68da ldr r2, [r3, #12] 800c3ce: 4b14 ldr r3, [pc, #80] @ (800c420 ) 800c3d0: 699b ldr r3, [r3, #24] 800c3d2: f003 030f and.w r3, r3, #15 800c3d6: 429a cmp r2, r3 800c3d8: d208 bcs.n 800c3ec { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800c3da: 4b11 ldr r3, [pc, #68] @ (800c420 ) 800c3dc: 699b ldr r3, [r3, #24] 800c3de: f023 020f bic.w r2, r3, #15 800c3e2: 687b ldr r3, [r7, #4] 800c3e4: 68db ldr r3, [r3, #12] 800c3e6: 490e ldr r1, [pc, #56] @ (800c420 ) 800c3e8: 4313 orrs r3, r2 800c3ea: 618b str r3, [r1, #24] } #endif } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 800c3ec: 4b0b ldr r3, [pc, #44] @ (800c41c ) 800c3ee: 681b ldr r3, [r3, #0] 800c3f0: f003 030f and.w r3, r3, #15 800c3f4: 683a ldr r2, [r7, #0] 800c3f6: 429a cmp r2, r3 800c3f8: d214 bcs.n 800c424 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800c3fa: 4b08 ldr r3, [pc, #32] @ (800c41c ) 800c3fc: 681b ldr r3, [r3, #0] 800c3fe: f023 020f bic.w r2, r3, #15 800c402: 4906 ldr r1, [pc, #24] @ (800c41c ) 800c404: 683b ldr r3, [r7, #0] 800c406: 4313 orrs r3, r2 800c408: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800c40a: 4b04 ldr r3, [pc, #16] @ (800c41c ) 800c40c: 681b ldr r3, [r3, #0] 800c40e: f003 030f and.w r3, r3, #15 800c412: 683a ldr r2, [r7, #0] 800c414: 429a cmp r2, r3 800c416: d005 beq.n 800c424 { return HAL_ERROR; 800c418: 2301 movs r3, #1 800c41a: e086 b.n 800c52a 800c41c: 52002000 .word 0x52002000 800c420: 58024400 .word 0x58024400 } } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 800c424: 687b ldr r3, [r7, #4] 800c426: 681b ldr r3, [r3, #0] 800c428: f003 0304 and.w r3, r3, #4 800c42c: 2b00 cmp r3, #0 800c42e: d010 beq.n 800c452 { #if defined(RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 800c430: 687b ldr r3, [r7, #4] 800c432: 691a ldr r2, [r3, #16] 800c434: 4b3f ldr r3, [pc, #252] @ (800c534 ) 800c436: 699b ldr r3, [r3, #24] 800c438: f003 0370 and.w r3, r3, #112 @ 0x70 800c43c: 429a cmp r2, r3 800c43e: d208 bcs.n 800c452 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 800c440: 4b3c ldr r3, [pc, #240] @ (800c534 ) 800c442: 699b ldr r3, [r3, #24] 800c444: f023 0270 bic.w r2, r3, #112 @ 0x70 800c448: 687b ldr r3, [r7, #4] 800c44a: 691b ldr r3, [r3, #16] 800c44c: 4939 ldr r1, [pc, #228] @ (800c534 ) 800c44e: 4313 orrs r3, r2 800c450: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800c452: 687b ldr r3, [r7, #4] 800c454: 681b ldr r3, [r3, #0] 800c456: f003 0308 and.w r3, r3, #8 800c45a: 2b00 cmp r3, #0 800c45c: d010 beq.n 800c480 { #if defined(RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800c45e: 687b ldr r3, [r7, #4] 800c460: 695a ldr r2, [r3, #20] 800c462: 4b34 ldr r3, [pc, #208] @ (800c534 ) 800c464: 69db ldr r3, [r3, #28] 800c466: f003 0370 and.w r3, r3, #112 @ 0x70 800c46a: 429a cmp r2, r3 800c46c: d208 bcs.n 800c480 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800c46e: 4b31 ldr r3, [pc, #196] @ (800c534 ) 800c470: 69db ldr r3, [r3, #28] 800c472: f023 0270 bic.w r2, r3, #112 @ 0x70 800c476: 687b ldr r3, [r7, #4] 800c478: 695b ldr r3, [r3, #20] 800c47a: 492e ldr r1, [pc, #184] @ (800c534 ) 800c47c: 4313 orrs r3, r2 800c47e: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800c480: 687b ldr r3, [r7, #4] 800c482: 681b ldr r3, [r3, #0] 800c484: f003 0310 and.w r3, r3, #16 800c488: 2b00 cmp r3, #0 800c48a: d010 beq.n 800c4ae { #if defined (RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800c48c: 687b ldr r3, [r7, #4] 800c48e: 699a ldr r2, [r3, #24] 800c490: 4b28 ldr r3, [pc, #160] @ (800c534 ) 800c492: 69db ldr r3, [r3, #28] 800c494: f403 63e0 and.w r3, r3, #1792 @ 0x700 800c498: 429a cmp r2, r3 800c49a: d208 bcs.n 800c4ae { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800c49c: 4b25 ldr r3, [pc, #148] @ (800c534 ) 800c49e: 69db ldr r3, [r3, #28] 800c4a0: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800c4a4: 687b ldr r3, [r7, #4] 800c4a6: 699b ldr r3, [r3, #24] 800c4a8: 4922 ldr r1, [pc, #136] @ (800c534 ) 800c4aa: 4313 orrs r3, r2 800c4ac: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800c4ae: 687b ldr r3, [r7, #4] 800c4b0: 681b ldr r3, [r3, #0] 800c4b2: f003 0320 and.w r3, r3, #32 800c4b6: 2b00 cmp r3, #0 800c4b8: d010 beq.n 800c4dc { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800c4ba: 687b ldr r3, [r7, #4] 800c4bc: 69da ldr r2, [r3, #28] 800c4be: 4b1d ldr r3, [pc, #116] @ (800c534 ) 800c4c0: 6a1b ldr r3, [r3, #32] 800c4c2: f003 0370 and.w r3, r3, #112 @ 0x70 800c4c6: 429a cmp r2, r3 800c4c8: d208 bcs.n 800c4dc { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800c4ca: 4b1a ldr r3, [pc, #104] @ (800c534 ) 800c4cc: 6a1b ldr r3, [r3, #32] 800c4ce: f023 0270 bic.w r2, r3, #112 @ 0x70 800c4d2: 687b ldr r3, [r7, #4] 800c4d4: 69db ldr r3, [r3, #28] 800c4d6: 4917 ldr r1, [pc, #92] @ (800c534 ) 800c4d8: 4313 orrs r3, r2 800c4da: 620b str r3, [r1, #32] #endif } /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 800c4dc: f000 f834 bl 800c548 800c4e0: 4602 mov r2, r0 800c4e2: 4b14 ldr r3, [pc, #80] @ (800c534 ) 800c4e4: 699b ldr r3, [r3, #24] 800c4e6: 0a1b lsrs r3, r3, #8 800c4e8: f003 030f and.w r3, r3, #15 800c4ec: 4912 ldr r1, [pc, #72] @ (800c538 ) 800c4ee: 5ccb ldrb r3, [r1, r3] 800c4f0: f003 031f and.w r3, r3, #31 800c4f4: fa22 f303 lsr.w r3, r2, r3 800c4f8: 613b str r3, [r7, #16] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800c4fa: 4b0e ldr r3, [pc, #56] @ (800c534 ) 800c4fc: 699b ldr r3, [r3, #24] 800c4fe: f003 030f and.w r3, r3, #15 800c502: 4a0d ldr r2, [pc, #52] @ (800c538 ) 800c504: 5cd3 ldrb r3, [r2, r3] 800c506: f003 031f and.w r3, r3, #31 800c50a: 693a ldr r2, [r7, #16] 800c50c: fa22 f303 lsr.w r3, r2, r3 800c510: 4a0a ldr r2, [pc, #40] @ (800c53c ) 800c512: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 800c514: 4a0a ldr r2, [pc, #40] @ (800c540 ) 800c516: 693b ldr r3, [r7, #16] 800c518: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick(uwTickPrio); 800c51a: 4b0a ldr r3, [pc, #40] @ (800c544 ) 800c51c: 681b ldr r3, [r3, #0] 800c51e: 4618 mov r0, r3 800c520: f7f8 f89c bl 800465c 800c524: 4603 mov r3, r0 800c526: 73fb strb r3, [r7, #15] return halstatus; 800c528: 7bfb ldrb r3, [r7, #15] } 800c52a: 4618 mov r0, r3 800c52c: 3718 adds r7, #24 800c52e: 46bd mov sp, r7 800c530: bd80 pop {r7, pc} 800c532: bf00 nop 800c534: 58024400 .word 0x58024400 800c538: 080186dc .word 0x080186dc 800c53c: 24000038 .word 0x24000038 800c540: 24000034 .word 0x24000034 800c544: 2400003c .word 0x2400003c 0800c548 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800c548: b480 push {r7} 800c54a: b089 sub sp, #36 @ 0x24 800c54c: af00 add r7, sp, #0 float_t fracn1, pllvco; uint32_t sysclockfreq; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 800c54e: 4bb3 ldr r3, [pc, #716] @ (800c81c ) 800c550: 691b ldr r3, [r3, #16] 800c552: f003 0338 and.w r3, r3, #56 @ 0x38 800c556: 2b18 cmp r3, #24 800c558: f200 8155 bhi.w 800c806 800c55c: a201 add r2, pc, #4 @ (adr r2, 800c564 ) 800c55e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c562: bf00 nop 800c564: 0800c5c9 .word 0x0800c5c9 800c568: 0800c807 .word 0x0800c807 800c56c: 0800c807 .word 0x0800c807 800c570: 0800c807 .word 0x0800c807 800c574: 0800c807 .word 0x0800c807 800c578: 0800c807 .word 0x0800c807 800c57c: 0800c807 .word 0x0800c807 800c580: 0800c807 .word 0x0800c807 800c584: 0800c5ef .word 0x0800c5ef 800c588: 0800c807 .word 0x0800c807 800c58c: 0800c807 .word 0x0800c807 800c590: 0800c807 .word 0x0800c807 800c594: 0800c807 .word 0x0800c807 800c598: 0800c807 .word 0x0800c807 800c59c: 0800c807 .word 0x0800c807 800c5a0: 0800c807 .word 0x0800c807 800c5a4: 0800c5f5 .word 0x0800c5f5 800c5a8: 0800c807 .word 0x0800c807 800c5ac: 0800c807 .word 0x0800c807 800c5b0: 0800c807 .word 0x0800c807 800c5b4: 0800c807 .word 0x0800c807 800c5b8: 0800c807 .word 0x0800c807 800c5bc: 0800c807 .word 0x0800c807 800c5c0: 0800c807 .word 0x0800c807 800c5c4: 0800c5fb .word 0x0800c5fb { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800c5c8: 4b94 ldr r3, [pc, #592] @ (800c81c ) 800c5ca: 681b ldr r3, [r3, #0] 800c5cc: f003 0320 and.w r3, r3, #32 800c5d0: 2b00 cmp r3, #0 800c5d2: d009 beq.n 800c5e8 { sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800c5d4: 4b91 ldr r3, [pc, #580] @ (800c81c ) 800c5d6: 681b ldr r3, [r3, #0] 800c5d8: 08db lsrs r3, r3, #3 800c5da: f003 0303 and.w r3, r3, #3 800c5de: 4a90 ldr r2, [pc, #576] @ (800c820 ) 800c5e0: fa22 f303 lsr.w r3, r2, r3 800c5e4: 61bb str r3, [r7, #24] else { sysclockfreq = (uint32_t) HSI_VALUE; } break; 800c5e6: e111 b.n 800c80c sysclockfreq = (uint32_t) HSI_VALUE; 800c5e8: 4b8d ldr r3, [pc, #564] @ (800c820 ) 800c5ea: 61bb str r3, [r7, #24] break; 800c5ec: e10e b.n 800c80c case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ sysclockfreq = CSI_VALUE; 800c5ee: 4b8d ldr r3, [pc, #564] @ (800c824 ) 800c5f0: 61bb str r3, [r7, #24] break; 800c5f2: e10b b.n 800c80c case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 800c5f4: 4b8c ldr r3, [pc, #560] @ (800c828 ) 800c5f6: 61bb str r3, [r7, #24] break; 800c5f8: e108 b.n 800c80c case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800c5fa: 4b88 ldr r3, [pc, #544] @ (800c81c ) 800c5fc: 6a9b ldr r3, [r3, #40] @ 0x28 800c5fe: f003 0303 and.w r3, r3, #3 800c602: 617b str r3, [r7, #20] pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; 800c604: 4b85 ldr r3, [pc, #532] @ (800c81c ) 800c606: 6a9b ldr r3, [r3, #40] @ 0x28 800c608: 091b lsrs r3, r3, #4 800c60a: f003 033f and.w r3, r3, #63 @ 0x3f 800c60e: 613b str r3, [r7, #16] pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); 800c610: 4b82 ldr r3, [pc, #520] @ (800c81c ) 800c612: 6adb ldr r3, [r3, #44] @ 0x2c 800c614: f003 0301 and.w r3, r3, #1 800c618: 60fb str r3, [r7, #12] fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800c61a: 4b80 ldr r3, [pc, #512] @ (800c81c ) 800c61c: 6b5b ldr r3, [r3, #52] @ 0x34 800c61e: 08db lsrs r3, r3, #3 800c620: f3c3 030c ubfx r3, r3, #0, #13 800c624: 68fa ldr r2, [r7, #12] 800c626: fb02 f303 mul.w r3, r2, r3 800c62a: ee07 3a90 vmov s15, r3 800c62e: eef8 7a67 vcvt.f32.u32 s15, s15 800c632: edc7 7a02 vstr s15, [r7, #8] if (pllm != 0U) 800c636: 693b ldr r3, [r7, #16] 800c638: 2b00 cmp r3, #0 800c63a: f000 80e1 beq.w 800c800 800c63e: 697b ldr r3, [r7, #20] 800c640: 2b02 cmp r3, #2 800c642: f000 8083 beq.w 800c74c 800c646: 697b ldr r3, [r7, #20] 800c648: 2b02 cmp r3, #2 800c64a: f200 80a1 bhi.w 800c790 800c64e: 697b ldr r3, [r7, #20] 800c650: 2b00 cmp r3, #0 800c652: d003 beq.n 800c65c 800c654: 697b ldr r3, [r7, #20] 800c656: 2b01 cmp r3, #1 800c658: d056 beq.n 800c708 800c65a: e099 b.n 800c790 { switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800c65c: 4b6f ldr r3, [pc, #444] @ (800c81c ) 800c65e: 681b ldr r3, [r3, #0] 800c660: f003 0320 and.w r3, r3, #32 800c664: 2b00 cmp r3, #0 800c666: d02d beq.n 800c6c4 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800c668: 4b6c ldr r3, [pc, #432] @ (800c81c ) 800c66a: 681b ldr r3, [r3, #0] 800c66c: 08db lsrs r3, r3, #3 800c66e: f003 0303 and.w r3, r3, #3 800c672: 4a6b ldr r2, [pc, #428] @ (800c820 ) 800c674: fa22 f303 lsr.w r3, r2, r3 800c678: 607b str r3, [r7, #4] pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c67a: 687b ldr r3, [r7, #4] 800c67c: ee07 3a90 vmov s15, r3 800c680: eef8 6a67 vcvt.f32.u32 s13, s15 800c684: 693b ldr r3, [r7, #16] 800c686: ee07 3a90 vmov s15, r3 800c68a: eef8 7a67 vcvt.f32.u32 s15, s15 800c68e: ee86 7aa7 vdiv.f32 s14, s13, s15 800c692: 4b62 ldr r3, [pc, #392] @ (800c81c ) 800c694: 6b1b ldr r3, [r3, #48] @ 0x30 800c696: f3c3 0308 ubfx r3, r3, #0, #9 800c69a: ee07 3a90 vmov s15, r3 800c69e: eef8 6a67 vcvt.f32.u32 s13, s15 800c6a2: ed97 6a02 vldr s12, [r7, #8] 800c6a6: eddf 5a61 vldr s11, [pc, #388] @ 800c82c 800c6aa: eec6 7a25 vdiv.f32 s15, s12, s11 800c6ae: ee76 7aa7 vadd.f32 s15, s13, s15 800c6b2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c6b6: ee77 7aa6 vadd.f32 s15, s15, s13 800c6ba: ee67 7a27 vmul.f32 s15, s14, s15 800c6be: edc7 7a07 vstr s15, [r7, #28] } else { pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 800c6c2: e087 b.n 800c7d4 pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c6c4: 693b ldr r3, [r7, #16] 800c6c6: ee07 3a90 vmov s15, r3 800c6ca: eef8 7a67 vcvt.f32.u32 s15, s15 800c6ce: eddf 6a58 vldr s13, [pc, #352] @ 800c830 800c6d2: ee86 7aa7 vdiv.f32 s14, s13, s15 800c6d6: 4b51 ldr r3, [pc, #324] @ (800c81c ) 800c6d8: 6b1b ldr r3, [r3, #48] @ 0x30 800c6da: f3c3 0308 ubfx r3, r3, #0, #9 800c6de: ee07 3a90 vmov s15, r3 800c6e2: eef8 6a67 vcvt.f32.u32 s13, s15 800c6e6: ed97 6a02 vldr s12, [r7, #8] 800c6ea: eddf 5a50 vldr s11, [pc, #320] @ 800c82c 800c6ee: eec6 7a25 vdiv.f32 s15, s12, s11 800c6f2: ee76 7aa7 vadd.f32 s15, s13, s15 800c6f6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c6fa: ee77 7aa6 vadd.f32 s15, s15, s13 800c6fe: ee67 7a27 vmul.f32 s15, s14, s15 800c702: edc7 7a07 vstr s15, [r7, #28] break; 800c706: e065 b.n 800c7d4 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c708: 693b ldr r3, [r7, #16] 800c70a: ee07 3a90 vmov s15, r3 800c70e: eef8 7a67 vcvt.f32.u32 s15, s15 800c712: eddf 6a48 vldr s13, [pc, #288] @ 800c834 800c716: ee86 7aa7 vdiv.f32 s14, s13, s15 800c71a: 4b40 ldr r3, [pc, #256] @ (800c81c ) 800c71c: 6b1b ldr r3, [r3, #48] @ 0x30 800c71e: f3c3 0308 ubfx r3, r3, #0, #9 800c722: ee07 3a90 vmov s15, r3 800c726: eef8 6a67 vcvt.f32.u32 s13, s15 800c72a: ed97 6a02 vldr s12, [r7, #8] 800c72e: eddf 5a3f vldr s11, [pc, #252] @ 800c82c 800c732: eec6 7a25 vdiv.f32 s15, s12, s11 800c736: ee76 7aa7 vadd.f32 s15, s13, s15 800c73a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c73e: ee77 7aa6 vadd.f32 s15, s15, s13 800c742: ee67 7a27 vmul.f32 s15, s14, s15 800c746: edc7 7a07 vstr s15, [r7, #28] break; 800c74a: e043 b.n 800c7d4 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c74c: 693b ldr r3, [r7, #16] 800c74e: ee07 3a90 vmov s15, r3 800c752: eef8 7a67 vcvt.f32.u32 s15, s15 800c756: eddf 6a38 vldr s13, [pc, #224] @ 800c838 800c75a: ee86 7aa7 vdiv.f32 s14, s13, s15 800c75e: 4b2f ldr r3, [pc, #188] @ (800c81c ) 800c760: 6b1b ldr r3, [r3, #48] @ 0x30 800c762: f3c3 0308 ubfx r3, r3, #0, #9 800c766: ee07 3a90 vmov s15, r3 800c76a: eef8 6a67 vcvt.f32.u32 s13, s15 800c76e: ed97 6a02 vldr s12, [r7, #8] 800c772: eddf 5a2e vldr s11, [pc, #184] @ 800c82c 800c776: eec6 7a25 vdiv.f32 s15, s12, s11 800c77a: ee76 7aa7 vadd.f32 s15, s13, s15 800c77e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c782: ee77 7aa6 vadd.f32 s15, s15, s13 800c786: ee67 7a27 vmul.f32 s15, s14, s15 800c78a: edc7 7a07 vstr s15, [r7, #28] break; 800c78e: e021 b.n 800c7d4 default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c790: 693b ldr r3, [r7, #16] 800c792: ee07 3a90 vmov s15, r3 800c796: eef8 7a67 vcvt.f32.u32 s15, s15 800c79a: eddf 6a26 vldr s13, [pc, #152] @ 800c834 800c79e: ee86 7aa7 vdiv.f32 s14, s13, s15 800c7a2: 4b1e ldr r3, [pc, #120] @ (800c81c ) 800c7a4: 6b1b ldr r3, [r3, #48] @ 0x30 800c7a6: f3c3 0308 ubfx r3, r3, #0, #9 800c7aa: ee07 3a90 vmov s15, r3 800c7ae: eef8 6a67 vcvt.f32.u32 s13, s15 800c7b2: ed97 6a02 vldr s12, [r7, #8] 800c7b6: eddf 5a1d vldr s11, [pc, #116] @ 800c82c 800c7ba: eec6 7a25 vdiv.f32 s15, s12, s11 800c7be: ee76 7aa7 vadd.f32 s15, s13, s15 800c7c2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c7c6: ee77 7aa6 vadd.f32 s15, s15, s13 800c7ca: ee67 7a27 vmul.f32 s15, s14, s15 800c7ce: edc7 7a07 vstr s15, [r7, #28] break; 800c7d2: bf00 nop } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; 800c7d4: 4b11 ldr r3, [pc, #68] @ (800c81c ) 800c7d6: 6b1b ldr r3, [r3, #48] @ 0x30 800c7d8: 0a5b lsrs r3, r3, #9 800c7da: f003 037f and.w r3, r3, #127 @ 0x7f 800c7de: 3301 adds r3, #1 800c7e0: 603b str r3, [r7, #0] sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); 800c7e2: 683b ldr r3, [r7, #0] 800c7e4: ee07 3a90 vmov s15, r3 800c7e8: eeb8 7a67 vcvt.f32.u32 s14, s15 800c7ec: edd7 6a07 vldr s13, [r7, #28] 800c7f0: eec6 7a87 vdiv.f32 s15, s13, s14 800c7f4: eefc 7ae7 vcvt.u32.f32 s15, s15 800c7f8: ee17 3a90 vmov r3, s15 800c7fc: 61bb str r3, [r7, #24] } else { sysclockfreq = 0U; } break; 800c7fe: e005 b.n 800c80c sysclockfreq = 0U; 800c800: 2300 movs r3, #0 800c802: 61bb str r3, [r7, #24] break; 800c804: e002 b.n 800c80c default: sysclockfreq = CSI_VALUE; 800c806: 4b07 ldr r3, [pc, #28] @ (800c824 ) 800c808: 61bb str r3, [r7, #24] break; 800c80a: bf00 nop } return sysclockfreq; 800c80c: 69bb ldr r3, [r7, #24] } 800c80e: 4618 mov r0, r3 800c810: 3724 adds r7, #36 @ 0x24 800c812: 46bd mov sp, r7 800c814: f85d 7b04 ldr.w r7, [sp], #4 800c818: 4770 bx lr 800c81a: bf00 nop 800c81c: 58024400 .word 0x58024400 800c820: 03d09000 .word 0x03d09000 800c824: 003d0900 .word 0x003d0900 800c828: 017d7840 .word 0x017d7840 800c82c: 46000000 .word 0x46000000 800c830: 4c742400 .word 0x4c742400 800c834: 4a742400 .word 0x4a742400 800c838: 4bbebc20 .word 0x4bbebc20 0800c83c : * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 800c83c: b580 push {r7, lr} 800c83e: b082 sub sp, #8 800c840: af00 add r7, sp, #0 uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 800c842: f7ff fe81 bl 800c548 800c846: 4602 mov r2, r0 800c848: 4b10 ldr r3, [pc, #64] @ (800c88c ) 800c84a: 699b ldr r3, [r3, #24] 800c84c: 0a1b lsrs r3, r3, #8 800c84e: f003 030f and.w r3, r3, #15 800c852: 490f ldr r1, [pc, #60] @ (800c890 ) 800c854: 5ccb ldrb r3, [r1, r3] 800c856: f003 031f and.w r3, r3, #31 800c85a: fa22 f303 lsr.w r3, r2, r3 800c85e: 607b str r3, [r7, #4] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800c860: 4b0a ldr r3, [pc, #40] @ (800c88c ) 800c862: 699b ldr r3, [r3, #24] 800c864: f003 030f and.w r3, r3, #15 800c868: 4a09 ldr r2, [pc, #36] @ (800c890 ) 800c86a: 5cd3 ldrb r3, [r2, r3] 800c86c: f003 031f and.w r3, r3, #31 800c870: 687a ldr r2, [r7, #4] 800c872: fa22 f303 lsr.w r3, r2, r3 800c876: 4a07 ldr r2, [pc, #28] @ (800c894 ) 800c878: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 800c87a: 4a07 ldr r2, [pc, #28] @ (800c898 ) 800c87c: 687b ldr r3, [r7, #4] 800c87e: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ return SystemD2Clock; 800c880: 4b04 ldr r3, [pc, #16] @ (800c894 ) 800c882: 681b ldr r3, [r3, #0] } 800c884: 4618 mov r0, r3 800c886: 3708 adds r7, #8 800c888: 46bd mov sp, r7 800c88a: bd80 pop {r7, pc} 800c88c: 58024400 .word 0x58024400 800c890: 080186dc .word 0x080186dc 800c894: 24000038 .word 0x24000038 800c898: 24000034 .word 0x24000034 0800c89c : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 800c89c: b580 push {r7, lr} 800c89e: af00 add r7, sp, #0 #if defined (RCC_D2CFGR_D2PPRE1) /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); 800c8a0: f7ff ffcc bl 800c83c 800c8a4: 4602 mov r2, r0 800c8a6: 4b06 ldr r3, [pc, #24] @ (800c8c0 ) 800c8a8: 69db ldr r3, [r3, #28] 800c8aa: 091b lsrs r3, r3, #4 800c8ac: f003 0307 and.w r3, r3, #7 800c8b0: 4904 ldr r1, [pc, #16] @ (800c8c4 ) 800c8b2: 5ccb ldrb r3, [r1, r3] 800c8b4: f003 031f and.w r3, r3, #31 800c8b8: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); #endif } 800c8bc: 4618 mov r0, r3 800c8be: bd80 pop {r7, pc} 800c8c0: 58024400 .word 0x58024400 800c8c4: 080186dc .word 0x080186dc 0800c8c8 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 800c8c8: b580 push {r7, lr} 800c8ca: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ #if defined(RCC_D2CFGR_D2PPRE2) return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); 800c8cc: f7ff ffb6 bl 800c83c 800c8d0: 4602 mov r2, r0 800c8d2: 4b06 ldr r3, [pc, #24] @ (800c8ec ) 800c8d4: 69db ldr r3, [r3, #28] 800c8d6: 0a1b lsrs r3, r3, #8 800c8d8: f003 0307 and.w r3, r3, #7 800c8dc: 4904 ldr r1, [pc, #16] @ (800c8f0 ) 800c8de: 5ccb ldrb r3, [r1, r3] 800c8e0: f003 031f and.w r3, r3, #31 800c8e4: fa22 f303 lsr.w r3, r2, r3 #else return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); #endif } 800c8e8: 4618 mov r0, r3 800c8ea: bd80 pop {r7, pc} 800c8ec: 58024400 .word 0x58024400 800c8f0: 080186dc .word 0x080186dc 0800c8f4 : * will be configured. * @param pFLatency: Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 800c8f4: b480 push {r7} 800c8f6: b083 sub sp, #12 800c8f8: af00 add r7, sp, #0 800c8fa: 6078 str r0, [r7, #4] 800c8fc: 6039 str r1, [r7, #0] /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | 800c8fe: 687b ldr r3, [r7, #4] 800c900: 223f movs r2, #63 @ 0x3f 800c902: 601a str r2, [r3, #0] RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ; /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 800c904: 4b1a ldr r3, [pc, #104] @ (800c970 ) 800c906: 691b ldr r3, [r3, #16] 800c908: f003 0207 and.w r2, r3, #7 800c90c: 687b ldr r3, [r7, #4] 800c90e: 605a str r2, [r3, #4] #if defined(RCC_D1CFGR_D1CPRE) /* Get the SYSCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE); 800c910: 4b17 ldr r3, [pc, #92] @ (800c970 ) 800c912: 699b ldr r3, [r3, #24] 800c914: f403 6270 and.w r2, r3, #3840 @ 0xf00 800c918: 687b ldr r3, [r7, #4] 800c91a: 609a str r2, [r3, #8] /* Get the D1HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE); 800c91c: 4b14 ldr r3, [pc, #80] @ (800c970 ) 800c91e: 699b ldr r3, [r3, #24] 800c920: f003 020f and.w r2, r3, #15 800c924: 687b ldr r3, [r7, #4] 800c926: 60da str r2, [r3, #12] /* Get the APB3 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE); 800c928: 4b11 ldr r3, [pc, #68] @ (800c970 ) 800c92a: 699b ldr r3, [r3, #24] 800c92c: f003 0270 and.w r2, r3, #112 @ 0x70 800c930: 687b ldr r3, [r7, #4] 800c932: 611a str r2, [r3, #16] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1); 800c934: 4b0e ldr r3, [pc, #56] @ (800c970 ) 800c936: 69db ldr r3, [r3, #28] 800c938: f003 0270 and.w r2, r3, #112 @ 0x70 800c93c: 687b ldr r3, [r7, #4] 800c93e: 615a str r2, [r3, #20] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2); 800c940: 4b0b ldr r3, [pc, #44] @ (800c970 ) 800c942: 69db ldr r3, [r3, #28] 800c944: f403 62e0 and.w r2, r3, #1792 @ 0x700 800c948: 687b ldr r3, [r7, #4] 800c94a: 619a str r2, [r3, #24] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); 800c94c: 4b08 ldr r3, [pc, #32] @ (800c970 ) 800c94e: 6a1b ldr r3, [r3, #32] 800c950: f003 0270 and.w r2, r3, #112 @ 0x70 800c954: 687b ldr r3, [r7, #4] 800c956: 61da str r2, [r3, #28] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE); #endif /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 800c958: 4b06 ldr r3, [pc, #24] @ (800c974 ) 800c95a: 681b ldr r3, [r3, #0] 800c95c: f003 020f and.w r2, r3, #15 800c960: 683b ldr r3, [r7, #0] 800c962: 601a str r2, [r3, #0] } 800c964: bf00 nop 800c966: 370c adds r7, #12 800c968: 46bd mov sp, r7 800c96a: f85d 7b04 ldr.w r7, [sp], #4 800c96e: 4770 bx lr 800c970: 58024400 .word 0x58024400 800c974: 52002000 .word 0x52002000 0800c978 : * (*) : Available on some STM32H7 lines only. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 800c978: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 800c97c: b0c8 sub sp, #288 @ 0x120 800c97e: af00 add r7, sp, #0 800c980: f8c7 010c str.w r0, [r7, #268] @ 0x10c uint32_t tmpreg; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 800c984: 2300 movs r3, #0 800c986: f887 311f strb.w r3, [r7, #287] @ 0x11f HAL_StatusTypeDef status = HAL_OK; /* Final status */ 800c98a: 2300 movs r3, #0 800c98c: f887 311e strb.w r3, [r7, #286] @ 0x11e /*---------------------------- SPDIFRX configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 800c990: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c994: e9d3 2300 ldrd r2, r3, [r3] 800c998: f002 6400 and.w r4, r2, #134217728 @ 0x8000000 800c99c: 2500 movs r5, #0 800c99e: ea54 0305 orrs.w r3, r4, r5 800c9a2: d049 beq.n 800ca38 { switch (PeriphClkInit->SpdifrxClockSelection) 800c9a4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c9a8: 6e9b ldr r3, [r3, #104] @ 0x68 800c9aa: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800c9ae: d02f beq.n 800ca10 800c9b0: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800c9b4: d828 bhi.n 800ca08 800c9b6: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800c9ba: d01a beq.n 800c9f2 800c9bc: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800c9c0: d822 bhi.n 800ca08 800c9c2: 2b00 cmp r3, #0 800c9c4: d003 beq.n 800c9ce 800c9c6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800c9ca: d007 beq.n 800c9dc 800c9cc: e01c b.n 800ca08 { case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c9ce: 4bb8 ldr r3, [pc, #736] @ (800ccb0 ) 800c9d0: 6adb ldr r3, [r3, #44] @ 0x2c 800c9d2: 4ab7 ldr r2, [pc, #732] @ (800ccb0 ) 800c9d4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c9d8: 62d3 str r3, [r2, #44] @ 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 800c9da: e01a b.n 800ca12 case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800c9dc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c9e0: 3308 adds r3, #8 800c9e2: 2102 movs r1, #2 800c9e4: 4618 mov r0, r3 800c9e6: f002 fb45 bl 800f074 800c9ea: 4603 mov r3, r0 800c9ec: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 800c9f0: e00f b.n 800ca12 case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800c9f2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c9f6: 3328 adds r3, #40 @ 0x28 800c9f8: 2102 movs r1, #2 800c9fa: 4618 mov r0, r3 800c9fc: f002 fbec bl 800f1d8 800ca00: 4603 mov r3, r0 800ca02: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 800ca06: e004 b.n 800ca12 /* Internal OSC clock is used as source of SPDIFRX clock*/ /* SPDIFRX clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800ca08: 2301 movs r3, #1 800ca0a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ca0e: e000 b.n 800ca12 break; 800ca10: bf00 nop } if (ret == HAL_OK) 800ca12: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ca16: 2b00 cmp r3, #0 800ca18: d10a bne.n 800ca30 { /* Set the source of SPDIFRX clock*/ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 800ca1a: 4ba5 ldr r3, [pc, #660] @ (800ccb0 ) 800ca1c: 6d1b ldr r3, [r3, #80] @ 0x50 800ca1e: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800ca22: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca26: 6e9b ldr r3, [r3, #104] @ 0x68 800ca28: 4aa1 ldr r2, [pc, #644] @ (800ccb0 ) 800ca2a: 430b orrs r3, r1 800ca2c: 6513 str r3, [r2, #80] @ 0x50 800ca2e: e003 b.n 800ca38 } else { /* set overall return value */ status = ret; 800ca30: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ca34: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 800ca38: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca3c: e9d3 2300 ldrd r2, r3, [r3] 800ca40: f402 7880 and.w r8, r2, #256 @ 0x100 800ca44: f04f 0900 mov.w r9, #0 800ca48: ea58 0309 orrs.w r3, r8, r9 800ca4c: d047 beq.n 800cade { switch (PeriphClkInit->Sai1ClockSelection) 800ca4e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca52: 6d9b ldr r3, [r3, #88] @ 0x58 800ca54: 2b04 cmp r3, #4 800ca56: d82a bhi.n 800caae 800ca58: a201 add r2, pc, #4 @ (adr r2, 800ca60 ) 800ca5a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ca5e: bf00 nop 800ca60: 0800ca75 .word 0x0800ca75 800ca64: 0800ca83 .word 0x0800ca83 800ca68: 0800ca99 .word 0x0800ca99 800ca6c: 0800cab7 .word 0x0800cab7 800ca70: 0800cab7 .word 0x0800cab7 { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800ca74: 4b8e ldr r3, [pc, #568] @ (800ccb0 ) 800ca76: 6adb ldr r3, [r3, #44] @ 0x2c 800ca78: 4a8d ldr r2, [pc, #564] @ (800ccb0 ) 800ca7a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800ca7e: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800ca80: e01a b.n 800cab8 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800ca82: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca86: 3308 adds r3, #8 800ca88: 2100 movs r1, #0 800ca8a: 4618 mov r0, r3 800ca8c: f002 faf2 bl 800f074 800ca90: 4603 mov r3, r0 800ca92: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800ca96: e00f b.n 800cab8 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800ca98: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca9c: 3328 adds r3, #40 @ 0x28 800ca9e: 2100 movs r1, #0 800caa0: 4618 mov r0, r3 800caa2: f002 fb99 bl 800f1d8 800caa6: 4603 mov r3, r0 800caa8: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800caac: e004 b.n 800cab8 /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800caae: 2301 movs r3, #1 800cab0: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cab4: e000 b.n 800cab8 break; 800cab6: bf00 nop } if (ret == HAL_OK) 800cab8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cabc: 2b00 cmp r3, #0 800cabe: d10a bne.n 800cad6 { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 800cac0: 4b7b ldr r3, [pc, #492] @ (800ccb0 ) 800cac2: 6d1b ldr r3, [r3, #80] @ 0x50 800cac4: f023 0107 bic.w r1, r3, #7 800cac8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cacc: 6d9b ldr r3, [r3, #88] @ 0x58 800cace: 4a78 ldr r2, [pc, #480] @ (800ccb0 ) 800cad0: 430b orrs r3, r1 800cad2: 6513 str r3, [r2, #80] @ 0x50 800cad4: e003 b.n 800cade } else { /* set overall return value */ status = ret; 800cad6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cada: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #if defined(SAI3) /*---------------------------- SAI2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) 800cade: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cae2: e9d3 2300 ldrd r2, r3, [r3] 800cae6: f402 7a00 and.w sl, r2, #512 @ 0x200 800caea: f04f 0b00 mov.w fp, #0 800caee: ea5a 030b orrs.w r3, sl, fp 800caf2: d04c beq.n 800cb8e { switch (PeriphClkInit->Sai23ClockSelection) 800caf4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800caf8: 6ddb ldr r3, [r3, #92] @ 0x5c 800cafa: f5b3 7f80 cmp.w r3, #256 @ 0x100 800cafe: d030 beq.n 800cb62 800cb00: f5b3 7f80 cmp.w r3, #256 @ 0x100 800cb04: d829 bhi.n 800cb5a 800cb06: 2bc0 cmp r3, #192 @ 0xc0 800cb08: d02d beq.n 800cb66 800cb0a: 2bc0 cmp r3, #192 @ 0xc0 800cb0c: d825 bhi.n 800cb5a 800cb0e: 2b80 cmp r3, #128 @ 0x80 800cb10: d018 beq.n 800cb44 800cb12: 2b80 cmp r3, #128 @ 0x80 800cb14: d821 bhi.n 800cb5a 800cb16: 2b00 cmp r3, #0 800cb18: d002 beq.n 800cb20 800cb1a: 2b40 cmp r3, #64 @ 0x40 800cb1c: d007 beq.n 800cb2e 800cb1e: e01c b.n 800cb5a { case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cb20: 4b63 ldr r3, [pc, #396] @ (800ccb0 ) 800cb22: 6adb ldr r3, [r3, #44] @ 0x2c 800cb24: 4a62 ldr r2, [pc, #392] @ (800ccb0 ) 800cb26: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cb2a: 62d3 str r3, [r2, #44] @ 0x2c /* SAI2/3 clock source configuration done later after clock selection check */ break; 800cb2c: e01c b.n 800cb68 case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800cb2e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb32: 3308 adds r3, #8 800cb34: 2100 movs r1, #0 800cb36: 4618 mov r0, r3 800cb38: f002 fa9c bl 800f074 800cb3c: 4603 mov r3, r0 800cb3e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 800cb42: e011 b.n 800cb68 case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800cb44: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb48: 3328 adds r3, #40 @ 0x28 800cb4a: 2100 movs r1, #0 800cb4c: 4618 mov r0, r3 800cb4e: f002 fb43 bl 800f1d8 800cb52: 4603 mov r3, r0 800cb54: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 800cb58: e006 b.n 800cb68 /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ /* SAI2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cb5a: 2301 movs r3, #1 800cb5c: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cb60: e002 b.n 800cb68 break; 800cb62: bf00 nop 800cb64: e000 b.n 800cb68 break; 800cb66: bf00 nop } if (ret == HAL_OK) 800cb68: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cb6c: 2b00 cmp r3, #0 800cb6e: d10a bne.n 800cb86 { /* Set the source of SAI2/3 clock*/ __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); 800cb70: 4b4f ldr r3, [pc, #316] @ (800ccb0 ) 800cb72: 6d1b ldr r3, [r3, #80] @ 0x50 800cb74: f423 71e0 bic.w r1, r3, #448 @ 0x1c0 800cb78: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb7c: 6ddb ldr r3, [r3, #92] @ 0x5c 800cb7e: 4a4c ldr r2, [pc, #304] @ (800ccb0 ) 800cb80: 430b orrs r3, r1 800cb82: 6513 str r3, [r2, #80] @ 0x50 800cb84: e003 b.n 800cb8e } else { /* set overall return value */ status = ret; 800cb86: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cb8a: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI2B*/ #if defined(SAI4) /*---------------------------- SAI4A configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 800cb8e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb92: e9d3 2300 ldrd r2, r3, [r3] 800cb96: f402 6380 and.w r3, r2, #1024 @ 0x400 800cb9a: f8c7 3100 str.w r3, [r7, #256] @ 0x100 800cb9e: 2300 movs r3, #0 800cba0: f8c7 3104 str.w r3, [r7, #260] @ 0x104 800cba4: e9d7 1240 ldrd r1, r2, [r7, #256] @ 0x100 800cba8: 460b mov r3, r1 800cbaa: 4313 orrs r3, r2 800cbac: d053 beq.n 800cc56 { switch (PeriphClkInit->Sai4AClockSelection) 800cbae: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cbb2: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 800cbb6: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800cbba: d035 beq.n 800cc28 800cbbc: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800cbc0: d82e bhi.n 800cc20 800cbc2: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800cbc6: d031 beq.n 800cc2c 800cbc8: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800cbcc: d828 bhi.n 800cc20 800cbce: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800cbd2: d01a beq.n 800cc0a 800cbd4: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800cbd8: d822 bhi.n 800cc20 800cbda: 2b00 cmp r3, #0 800cbdc: d003 beq.n 800cbe6 800cbde: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800cbe2: d007 beq.n 800cbf4 800cbe4: e01c b.n 800cc20 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cbe6: 4b32 ldr r3, [pc, #200] @ (800ccb0 ) 800cbe8: 6adb ldr r3, [r3, #44] @ 0x2c 800cbea: 4a31 ldr r2, [pc, #196] @ (800ccb0 ) 800cbec: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cbf0: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800cbf2: e01c b.n 800cc2e case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800cbf4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cbf8: 3308 adds r3, #8 800cbfa: 2100 movs r1, #0 800cbfc: 4618 mov r0, r3 800cbfe: f002 fa39 bl 800f074 800cc02: 4603 mov r3, r0 800cc04: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800cc08: e011 b.n 800cc2e case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800cc0a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc0e: 3328 adds r3, #40 @ 0x28 800cc10: 2100 movs r1, #0 800cc12: 4618 mov r0, r3 800cc14: f002 fae0 bl 800f1d8 800cc18: 4603 mov r3, r0 800cc1a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800cc1e: e006 b.n 800cc2e /* SAI4A clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800cc20: 2301 movs r3, #1 800cc22: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cc26: e002 b.n 800cc2e break; 800cc28: bf00 nop 800cc2a: e000 b.n 800cc2e break; 800cc2c: bf00 nop } if (ret == HAL_OK) 800cc2e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cc32: 2b00 cmp r3, #0 800cc34: d10b bne.n 800cc4e { /* Set the source of SAI4A clock*/ __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); 800cc36: 4b1e ldr r3, [pc, #120] @ (800ccb0 ) 800cc38: 6d9b ldr r3, [r3, #88] @ 0x58 800cc3a: f423 0160 bic.w r1, r3, #14680064 @ 0xe00000 800cc3e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc42: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 800cc46: 4a1a ldr r2, [pc, #104] @ (800ccb0 ) 800cc48: 430b orrs r3, r1 800cc4a: 6593 str r3, [r2, #88] @ 0x58 800cc4c: e003 b.n 800cc56 } else { /* set overall return value */ status = ret; 800cc4e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cc52: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI4B configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 800cc56: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc5a: e9d3 2300 ldrd r2, r3, [r3] 800cc5e: f402 6300 and.w r3, r2, #2048 @ 0x800 800cc62: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 800cc66: 2300 movs r3, #0 800cc68: f8c7 30fc str.w r3, [r7, #252] @ 0xfc 800cc6c: e9d7 123e ldrd r1, r2, [r7, #248] @ 0xf8 800cc70: 460b mov r3, r1 800cc72: 4313 orrs r3, r2 800cc74: d056 beq.n 800cd24 { switch (PeriphClkInit->Sai4BClockSelection) 800cc76: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc7a: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 800cc7e: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800cc82: d038 beq.n 800ccf6 800cc84: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800cc88: d831 bhi.n 800ccee 800cc8a: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800cc8e: d034 beq.n 800ccfa 800cc90: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800cc94: d82b bhi.n 800ccee 800cc96: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800cc9a: d01d beq.n 800ccd8 800cc9c: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800cca0: d825 bhi.n 800ccee 800cca2: 2b00 cmp r3, #0 800cca4: d006 beq.n 800ccb4 800cca6: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800ccaa: d00a beq.n 800ccc2 800ccac: e01f b.n 800ccee 800ccae: bf00 nop 800ccb0: 58024400 .word 0x58024400 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800ccb4: 4ba2 ldr r3, [pc, #648] @ (800cf40 ) 800ccb6: 6adb ldr r3, [r3, #44] @ 0x2c 800ccb8: 4aa1 ldr r2, [pc, #644] @ (800cf40 ) 800ccba: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800ccbe: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800ccc0: e01c b.n 800ccfc case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800ccc2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ccc6: 3308 adds r3, #8 800ccc8: 2100 movs r1, #0 800ccca: 4618 mov r0, r3 800cccc: f002 f9d2 bl 800f074 800ccd0: 4603 mov r3, r0 800ccd2: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800ccd6: e011 b.n 800ccfc case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800ccd8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ccdc: 3328 adds r3, #40 @ 0x28 800ccde: 2100 movs r1, #0 800cce0: 4618 mov r0, r3 800cce2: f002 fa79 bl 800f1d8 800cce6: 4603 mov r3, r0 800cce8: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800ccec: e006 b.n 800ccfc /* SAI4B clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800ccee: 2301 movs r3, #1 800ccf0: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ccf4: e002 b.n 800ccfc break; 800ccf6: bf00 nop 800ccf8: e000 b.n 800ccfc break; 800ccfa: bf00 nop } if (ret == HAL_OK) 800ccfc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cd00: 2b00 cmp r3, #0 800cd02: d10b bne.n 800cd1c { /* Set the source of SAI4B clock*/ __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); 800cd04: 4b8e ldr r3, [pc, #568] @ (800cf40 ) 800cd06: 6d9b ldr r3, [r3, #88] @ 0x58 800cd08: f023 61e0 bic.w r1, r3, #117440512 @ 0x7000000 800cd0c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd10: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 800cd14: 4a8a ldr r2, [pc, #552] @ (800cf40 ) 800cd16: 430b orrs r3, r1 800cd18: 6593 str r3, [r2, #88] @ 0x58 800cd1a: e003 b.n 800cd24 } else { /* set overall return value */ status = ret; 800cd1c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cd20: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI4*/ #if defined(QUADSPI) /*---------------------------- QSPI configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) 800cd24: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd28: e9d3 2300 ldrd r2, r3, [r3] 800cd2c: f002 7300 and.w r3, r2, #33554432 @ 0x2000000 800cd30: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0 800cd34: 2300 movs r3, #0 800cd36: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4 800cd3a: e9d7 123c ldrd r1, r2, [r7, #240] @ 0xf0 800cd3e: 460b mov r3, r1 800cd40: 4313 orrs r3, r2 800cd42: d03a beq.n 800cdba { switch (PeriphClkInit->QspiClockSelection) 800cd44: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd48: 6cdb ldr r3, [r3, #76] @ 0x4c 800cd4a: 2b30 cmp r3, #48 @ 0x30 800cd4c: d01f beq.n 800cd8e 800cd4e: 2b30 cmp r3, #48 @ 0x30 800cd50: d819 bhi.n 800cd86 800cd52: 2b20 cmp r3, #32 800cd54: d00c beq.n 800cd70 800cd56: 2b20 cmp r3, #32 800cd58: d815 bhi.n 800cd86 800cd5a: 2b00 cmp r3, #0 800cd5c: d019 beq.n 800cd92 800cd5e: 2b10 cmp r3, #16 800cd60: d111 bne.n 800cd86 { case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ /* Enable QSPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cd62: 4b77 ldr r3, [pc, #476] @ (800cf40 ) 800cd64: 6adb ldr r3, [r3, #44] @ 0x2c 800cd66: 4a76 ldr r2, [pc, #472] @ (800cf40 ) 800cd68: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cd6c: 62d3 str r3, [r2, #44] @ 0x2c /* QSPI clock source configuration done later after clock selection check */ break; 800cd6e: e011 b.n 800cd94 case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800cd70: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd74: 3308 adds r3, #8 800cd76: 2102 movs r1, #2 800cd78: 4618 mov r0, r3 800cd7a: f002 f97b bl 800f074 800cd7e: 4603 mov r3, r0 800cd80: f887 311f strb.w r3, [r7, #287] @ 0x11f /* QSPI clock source configuration done later after clock selection check */ break; 800cd84: e006 b.n 800cd94 case RCC_QSPICLKSOURCE_D1HCLK: /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ break; default: ret = HAL_ERROR; 800cd86: 2301 movs r3, #1 800cd88: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cd8c: e002 b.n 800cd94 break; 800cd8e: bf00 nop 800cd90: e000 b.n 800cd94 break; 800cd92: bf00 nop } if (ret == HAL_OK) 800cd94: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cd98: 2b00 cmp r3, #0 800cd9a: d10a bne.n 800cdb2 { /* Set the source of QSPI clock*/ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); 800cd9c: 4b68 ldr r3, [pc, #416] @ (800cf40 ) 800cd9e: 6cdb ldr r3, [r3, #76] @ 0x4c 800cda0: f023 0130 bic.w r1, r3, #48 @ 0x30 800cda4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cda8: 6cdb ldr r3, [r3, #76] @ 0x4c 800cdaa: 4a65 ldr r2, [pc, #404] @ (800cf40 ) 800cdac: 430b orrs r3, r1 800cdae: 64d3 str r3, [r2, #76] @ 0x4c 800cdb0: e003 b.n 800cdba } else { /* set overall return value */ status = ret; 800cdb2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cdb6: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 800cdba: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cdbe: e9d3 2300 ldrd r2, r3, [r3] 800cdc2: f402 5380 and.w r3, r2, #4096 @ 0x1000 800cdc6: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 800cdca: 2300 movs r3, #0 800cdcc: f8c7 30ec str.w r3, [r7, #236] @ 0xec 800cdd0: e9d7 123a ldrd r1, r2, [r7, #232] @ 0xe8 800cdd4: 460b mov r3, r1 800cdd6: 4313 orrs r3, r2 800cdd8: d051 beq.n 800ce7e { switch (PeriphClkInit->Spi123ClockSelection) 800cdda: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cdde: 6e1b ldr r3, [r3, #96] @ 0x60 800cde0: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800cde4: d035 beq.n 800ce52 800cde6: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800cdea: d82e bhi.n 800ce4a 800cdec: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800cdf0: d031 beq.n 800ce56 800cdf2: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800cdf6: d828 bhi.n 800ce4a 800cdf8: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800cdfc: d01a beq.n 800ce34 800cdfe: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800ce02: d822 bhi.n 800ce4a 800ce04: 2b00 cmp r3, #0 800ce06: d003 beq.n 800ce10 800ce08: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800ce0c: d007 beq.n 800ce1e 800ce0e: e01c b.n 800ce4a { case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800ce10: 4b4b ldr r3, [pc, #300] @ (800cf40 ) 800ce12: 6adb ldr r3, [r3, #44] @ 0x2c 800ce14: 4a4a ldr r2, [pc, #296] @ (800cf40 ) 800ce16: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800ce1a: 62d3 str r3, [r2, #44] @ 0x2c /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800ce1c: e01c b.n 800ce58 case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800ce1e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce22: 3308 adds r3, #8 800ce24: 2100 movs r1, #0 800ce26: 4618 mov r0, r3 800ce28: f002 f924 bl 800f074 800ce2c: 4603 mov r3, r0 800ce2e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800ce32: e011 b.n 800ce58 case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800ce34: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce38: 3328 adds r3, #40 @ 0x28 800ce3a: 2100 movs r1, #0 800ce3c: 4618 mov r0, r3 800ce3e: f002 f9cb bl 800f1d8 800ce42: 4603 mov r3, r0 800ce44: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800ce48: e006 b.n 800ce58 /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ /* SPI1/2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800ce4a: 2301 movs r3, #1 800ce4c: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ce50: e002 b.n 800ce58 break; 800ce52: bf00 nop 800ce54: e000 b.n 800ce58 break; 800ce56: bf00 nop } if (ret == HAL_OK) 800ce58: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ce5c: 2b00 cmp r3, #0 800ce5e: d10a bne.n 800ce76 { /* Set the source of SPI1/2/3 clock*/ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 800ce60: 4b37 ldr r3, [pc, #220] @ (800cf40 ) 800ce62: 6d1b ldr r3, [r3, #80] @ 0x50 800ce64: f423 41e0 bic.w r1, r3, #28672 @ 0x7000 800ce68: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce6c: 6e1b ldr r3, [r3, #96] @ 0x60 800ce6e: 4a34 ldr r2, [pc, #208] @ (800cf40 ) 800ce70: 430b orrs r3, r1 800ce72: 6513 str r3, [r2, #80] @ 0x50 800ce74: e003 b.n 800ce7e } else { /* set overall return value */ status = ret; 800ce76: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ce7a: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI4/5 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 800ce7e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce82: e9d3 2300 ldrd r2, r3, [r3] 800ce86: f402 5300 and.w r3, r2, #8192 @ 0x2000 800ce8a: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 800ce8e: 2300 movs r3, #0 800ce90: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 800ce94: e9d7 1238 ldrd r1, r2, [r7, #224] @ 0xe0 800ce98: 460b mov r3, r1 800ce9a: 4313 orrs r3, r2 800ce9c: d056 beq.n 800cf4c { switch (PeriphClkInit->Spi45ClockSelection) 800ce9e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cea2: 6e5b ldr r3, [r3, #100] @ 0x64 800cea4: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800cea8: d033 beq.n 800cf12 800ceaa: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800ceae: d82c bhi.n 800cf0a 800ceb0: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800ceb4: d02f beq.n 800cf16 800ceb6: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800ceba: d826 bhi.n 800cf0a 800cebc: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800cec0: d02b beq.n 800cf1a 800cec2: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800cec6: d820 bhi.n 800cf0a 800cec8: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800cecc: d012 beq.n 800cef4 800cece: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800ced2: d81a bhi.n 800cf0a 800ced4: 2b00 cmp r3, #0 800ced6: d022 beq.n 800cf1e 800ced8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800cedc: d115 bne.n 800cf0a /* SPI4/5 clock source configuration done later after clock selection check */ break; case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800cede: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cee2: 3308 adds r3, #8 800cee4: 2101 movs r1, #1 800cee6: 4618 mov r0, r3 800cee8: f002 f8c4 bl 800f074 800ceec: 4603 mov r3, r0 800ceee: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 800cef2: e015 b.n 800cf20 case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800cef4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cef8: 3328 adds r3, #40 @ 0x28 800cefa: 2101 movs r1, #1 800cefc: 4618 mov r0, r3 800cefe: f002 f96b bl 800f1d8 800cf02: 4603 mov r3, r0 800cf04: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 800cf08: e00a b.n 800cf20 /* HSE, oscillator is used as source of SPI4/5 clock */ /* SPI4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cf0a: 2301 movs r3, #1 800cf0c: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cf10: e006 b.n 800cf20 break; 800cf12: bf00 nop 800cf14: e004 b.n 800cf20 break; 800cf16: bf00 nop 800cf18: e002 b.n 800cf20 break; 800cf1a: bf00 nop 800cf1c: e000 b.n 800cf20 break; 800cf1e: bf00 nop } if (ret == HAL_OK) 800cf20: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cf24: 2b00 cmp r3, #0 800cf26: d10d bne.n 800cf44 { /* Set the source of SPI4/5 clock*/ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 800cf28: 4b05 ldr r3, [pc, #20] @ (800cf40 ) 800cf2a: 6d1b ldr r3, [r3, #80] @ 0x50 800cf2c: f423 21e0 bic.w r1, r3, #458752 @ 0x70000 800cf30: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf34: 6e5b ldr r3, [r3, #100] @ 0x64 800cf36: 4a02 ldr r2, [pc, #8] @ (800cf40 ) 800cf38: 430b orrs r3, r1 800cf3a: 6513 str r3, [r2, #80] @ 0x50 800cf3c: e006 b.n 800cf4c 800cf3e: bf00 nop 800cf40: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800cf44: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cf48: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI6 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 800cf4c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf50: e9d3 2300 ldrd r2, r3, [r3] 800cf54: f402 4380 and.w r3, r2, #16384 @ 0x4000 800cf58: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 800cf5c: 2300 movs r3, #0 800cf5e: f8c7 30dc str.w r3, [r7, #220] @ 0xdc 800cf62: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 800cf66: 460b mov r3, r1 800cf68: 4313 orrs r3, r2 800cf6a: d055 beq.n 800d018 { switch (PeriphClkInit->Spi6ClockSelection) 800cf6c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf70: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 800cf74: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800cf78: d033 beq.n 800cfe2 800cf7a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800cf7e: d82c bhi.n 800cfda 800cf80: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800cf84: d02f beq.n 800cfe6 800cf86: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800cf8a: d826 bhi.n 800cfda 800cf8c: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800cf90: d02b beq.n 800cfea 800cf92: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800cf96: d820 bhi.n 800cfda 800cf98: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cf9c: d012 beq.n 800cfc4 800cf9e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cfa2: d81a bhi.n 800cfda 800cfa4: 2b00 cmp r3, #0 800cfa6: d022 beq.n 800cfee 800cfa8: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800cfac: d115 bne.n 800cfda /* SPI6 clock source configuration done later after clock selection check */ break; case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800cfae: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cfb2: 3308 adds r3, #8 800cfb4: 2101 movs r1, #1 800cfb6: 4618 mov r0, r3 800cfb8: f002 f85c bl 800f074 800cfbc: 4603 mov r3, r0 800cfbe: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 800cfc2: e015 b.n 800cff0 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800cfc4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cfc8: 3328 adds r3, #40 @ 0x28 800cfca: 2101 movs r1, #1 800cfcc: 4618 mov r0, r3 800cfce: f002 f903 bl 800f1d8 800cfd2: 4603 mov r3, r0 800cfd4: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 800cfd8: e00a b.n 800cff0 /* SPI6 clock source configuration done later after clock selection check */ break; #endif default: ret = HAL_ERROR; 800cfda: 2301 movs r3, #1 800cfdc: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cfe0: e006 b.n 800cff0 break; 800cfe2: bf00 nop 800cfe4: e004 b.n 800cff0 break; 800cfe6: bf00 nop 800cfe8: e002 b.n 800cff0 break; 800cfea: bf00 nop 800cfec: e000 b.n 800cff0 break; 800cfee: bf00 nop } if (ret == HAL_OK) 800cff0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cff4: 2b00 cmp r3, #0 800cff6: d10b bne.n 800d010 { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 800cff8: 4ba3 ldr r3, [pc, #652] @ (800d288 ) 800cffa: 6d9b ldr r3, [r3, #88] @ 0x58 800cffc: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 800d000: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d004: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 800d008: 4a9f ldr r2, [pc, #636] @ (800d288 ) 800d00a: 430b orrs r3, r1 800d00c: 6593 str r3, [r2, #88] @ 0x58 800d00e: e003 b.n 800d018 } else { /* set overall return value */ status = ret; 800d010: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d014: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*DSI*/ #if defined(FDCAN1) || defined(FDCAN2) /*---------------------------- FDCAN configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 800d018: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d01c: e9d3 2300 ldrd r2, r3, [r3] 800d020: f402 4300 and.w r3, r2, #32768 @ 0x8000 800d024: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 800d028: 2300 movs r3, #0 800d02a: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 800d02e: e9d7 1234 ldrd r1, r2, [r7, #208] @ 0xd0 800d032: 460b mov r3, r1 800d034: 4313 orrs r3, r2 800d036: d037 beq.n 800d0a8 { switch (PeriphClkInit->FdcanClockSelection) 800d038: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d03c: 6f1b ldr r3, [r3, #112] @ 0x70 800d03e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d042: d00e beq.n 800d062 800d044: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d048: d816 bhi.n 800d078 800d04a: 2b00 cmp r3, #0 800d04c: d018 beq.n 800d080 800d04e: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800d052: d111 bne.n 800d078 { case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ /* Enable FDCAN Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d054: 4b8c ldr r3, [pc, #560] @ (800d288 ) 800d056: 6adb ldr r3, [r3, #44] @ 0x2c 800d058: 4a8b ldr r2, [pc, #556] @ (800d288 ) 800d05a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d05e: 62d3 str r3, [r2, #44] @ 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 800d060: e00f b.n 800d082 case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d062: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d066: 3308 adds r3, #8 800d068: 2101 movs r1, #1 800d06a: 4618 mov r0, r3 800d06c: f002 f802 bl 800f074 800d070: 4603 mov r3, r0 800d072: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FDCAN clock source configuration done later after clock selection check */ break; 800d076: e004 b.n 800d082 /* HSE is used as clock source for FDCAN*/ /* FDCAN clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d078: 2301 movs r3, #1 800d07a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d07e: e000 b.n 800d082 break; 800d080: bf00 nop } if (ret == HAL_OK) 800d082: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d086: 2b00 cmp r3, #0 800d088: d10a bne.n 800d0a0 { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 800d08a: 4b7f ldr r3, [pc, #508] @ (800d288 ) 800d08c: 6d1b ldr r3, [r3, #80] @ 0x50 800d08e: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 800d092: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d096: 6f1b ldr r3, [r3, #112] @ 0x70 800d098: 4a7b ldr r2, [pc, #492] @ (800d288 ) 800d09a: 430b orrs r3, r1 800d09c: 6513 str r3, [r2, #80] @ 0x50 800d09e: e003 b.n 800d0a8 } else { /* set overall return value */ status = ret; 800d0a0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d0a4: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*FDCAN1 || FDCAN2*/ /*---------------------------- FMC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 800d0a8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0ac: e9d3 2300 ldrd r2, r3, [r3] 800d0b0: f002 7380 and.w r3, r2, #16777216 @ 0x1000000 800d0b4: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 800d0b8: 2300 movs r3, #0 800d0ba: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 800d0be: e9d7 1232 ldrd r1, r2, [r7, #200] @ 0xc8 800d0c2: 460b mov r3, r1 800d0c4: 4313 orrs r3, r2 800d0c6: d039 beq.n 800d13c { switch (PeriphClkInit->FmcClockSelection) 800d0c8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0cc: 6c9b ldr r3, [r3, #72] @ 0x48 800d0ce: 2b03 cmp r3, #3 800d0d0: d81c bhi.n 800d10c 800d0d2: a201 add r2, pc, #4 @ (adr r2, 800d0d8 ) 800d0d4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d0d8: 0800d115 .word 0x0800d115 800d0dc: 0800d0e9 .word 0x0800d0e9 800d0e0: 0800d0f7 .word 0x0800d0f7 800d0e4: 0800d115 .word 0x0800d115 { case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ /* Enable FMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d0e8: 4b67 ldr r3, [pc, #412] @ (800d288 ) 800d0ea: 6adb ldr r3, [r3, #44] @ 0x2c 800d0ec: 4a66 ldr r2, [pc, #408] @ (800d288 ) 800d0ee: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d0f2: 62d3 str r3, [r2, #44] @ 0x2c /* FMC clock source configuration done later after clock selection check */ break; 800d0f4: e00f b.n 800d116 case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800d0f6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0fa: 3308 adds r3, #8 800d0fc: 2102 movs r1, #2 800d0fe: 4618 mov r0, r3 800d100: f001 ffb8 bl 800f074 800d104: 4603 mov r3, r0 800d106: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FMC clock source configuration done later after clock selection check */ break; 800d10a: e004 b.n 800d116 case RCC_FMCCLKSOURCE_HCLK: /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ break; default: ret = HAL_ERROR; 800d10c: 2301 movs r3, #1 800d10e: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d112: e000 b.n 800d116 break; 800d114: bf00 nop } if (ret == HAL_OK) 800d116: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d11a: 2b00 cmp r3, #0 800d11c: d10a bne.n 800d134 { /* Set the source of FMC clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 800d11e: 4b5a ldr r3, [pc, #360] @ (800d288 ) 800d120: 6cdb ldr r3, [r3, #76] @ 0x4c 800d122: f023 0103 bic.w r1, r3, #3 800d126: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d12a: 6c9b ldr r3, [r3, #72] @ 0x48 800d12c: 4a56 ldr r2, [pc, #344] @ (800d288 ) 800d12e: 430b orrs r3, r1 800d130: 64d3 str r3, [r2, #76] @ 0x4c 800d132: e003 b.n 800d13c } else { /* set overall return value */ status = ret; 800d134: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d138: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- RTC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 800d13c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d140: e9d3 2300 ldrd r2, r3, [r3] 800d144: f402 0380 and.w r3, r2, #4194304 @ 0x400000 800d148: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 800d14c: 2300 movs r3, #0 800d14e: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 800d152: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 800d156: 460b mov r3, r1 800d158: 4313 orrs r3, r2 800d15a: f000 809f beq.w 800d29c { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 800d15e: 4b4b ldr r3, [pc, #300] @ (800d28c ) 800d160: 681b ldr r3, [r3, #0] 800d162: 4a4a ldr r2, [pc, #296] @ (800d28c ) 800d164: f443 7380 orr.w r3, r3, #256 @ 0x100 800d168: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800d16a: f7f8 fe47 bl 8005dfc 800d16e: f8c7 0118 str.w r0, [r7, #280] @ 0x118 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800d172: e00b b.n 800d18c { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800d174: f7f8 fe42 bl 8005dfc 800d178: 4602 mov r2, r0 800d17a: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 800d17e: 1ad3 subs r3, r2, r3 800d180: 2b64 cmp r3, #100 @ 0x64 800d182: d903 bls.n 800d18c { ret = HAL_TIMEOUT; 800d184: 2303 movs r3, #3 800d186: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d18a: e005 b.n 800d198 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800d18c: 4b3f ldr r3, [pc, #252] @ (800d28c ) 800d18e: 681b ldr r3, [r3, #0] 800d190: f403 7380 and.w r3, r3, #256 @ 0x100 800d194: 2b00 cmp r3, #0 800d196: d0ed beq.n 800d174 } } if (ret == HAL_OK) 800d198: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d19c: 2b00 cmp r3, #0 800d19e: d179 bne.n 800d294 { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 800d1a0: 4b39 ldr r3, [pc, #228] @ (800d288 ) 800d1a2: 6f1a ldr r2, [r3, #112] @ 0x70 800d1a4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d1a8: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d1ac: 4053 eors r3, r2 800d1ae: f403 7340 and.w r3, r3, #768 @ 0x300 800d1b2: 2b00 cmp r3, #0 800d1b4: d015 beq.n 800d1e2 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800d1b6: 4b34 ldr r3, [pc, #208] @ (800d288 ) 800d1b8: 6f1b ldr r3, [r3, #112] @ 0x70 800d1ba: f423 7340 bic.w r3, r3, #768 @ 0x300 800d1be: f8c7 3114 str.w r3, [r7, #276] @ 0x114 /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 800d1c2: 4b31 ldr r3, [pc, #196] @ (800d288 ) 800d1c4: 6f1b ldr r3, [r3, #112] @ 0x70 800d1c6: 4a30 ldr r2, [pc, #192] @ (800d288 ) 800d1c8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800d1cc: 6713 str r3, [r2, #112] @ 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 800d1ce: 4b2e ldr r3, [pc, #184] @ (800d288 ) 800d1d0: 6f1b ldr r3, [r3, #112] @ 0x70 800d1d2: 4a2d ldr r2, [pc, #180] @ (800d288 ) 800d1d4: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800d1d8: 6713 str r3, [r2, #112] @ 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg; 800d1da: 4a2b ldr r2, [pc, #172] @ (800d288 ) 800d1dc: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800d1e0: 6713 str r3, [r2, #112] @ 0x70 } /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 800d1e2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d1e6: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d1ea: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d1ee: d118 bne.n 800d222 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800d1f0: f7f8 fe04 bl 8005dfc 800d1f4: f8c7 0118 str.w r0, [r7, #280] @ 0x118 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800d1f8: e00d b.n 800d216 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800d1fa: f7f8 fdff bl 8005dfc 800d1fe: 4602 mov r2, r0 800d200: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 800d204: 1ad2 subs r2, r2, r3 800d206: f241 3388 movw r3, #5000 @ 0x1388 800d20a: 429a cmp r2, r3 800d20c: d903 bls.n 800d216 { ret = HAL_TIMEOUT; 800d20e: 2303 movs r3, #3 800d210: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d214: e005 b.n 800d222 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800d216: 4b1c ldr r3, [pc, #112] @ (800d288 ) 800d218: 6f1b ldr r3, [r3, #112] @ 0x70 800d21a: f003 0302 and.w r3, r3, #2 800d21e: 2b00 cmp r3, #0 800d220: d0eb beq.n 800d1fa } } } if (ret == HAL_OK) 800d222: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d226: 2b00 cmp r3, #0 800d228: d129 bne.n 800d27e { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 800d22a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d22e: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d232: f403 7340 and.w r3, r3, #768 @ 0x300 800d236: f5b3 7f40 cmp.w r3, #768 @ 0x300 800d23a: d10e bne.n 800d25a 800d23c: 4b12 ldr r3, [pc, #72] @ (800d288 ) 800d23e: 691b ldr r3, [r3, #16] 800d240: f423 517c bic.w r1, r3, #16128 @ 0x3f00 800d244: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d248: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d24c: 091a lsrs r2, r3, #4 800d24e: 4b10 ldr r3, [pc, #64] @ (800d290 ) 800d250: 4013 ands r3, r2 800d252: 4a0d ldr r2, [pc, #52] @ (800d288 ) 800d254: 430b orrs r3, r1 800d256: 6113 str r3, [r2, #16] 800d258: e005 b.n 800d266 800d25a: 4b0b ldr r3, [pc, #44] @ (800d288 ) 800d25c: 691b ldr r3, [r3, #16] 800d25e: 4a0a ldr r2, [pc, #40] @ (800d288 ) 800d260: f423 537c bic.w r3, r3, #16128 @ 0x3f00 800d264: 6113 str r3, [r2, #16] 800d266: 4b08 ldr r3, [pc, #32] @ (800d288 ) 800d268: 6f19 ldr r1, [r3, #112] @ 0x70 800d26a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d26e: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d272: f3c3 030b ubfx r3, r3, #0, #12 800d276: 4a04 ldr r2, [pc, #16] @ (800d288 ) 800d278: 430b orrs r3, r1 800d27a: 6713 str r3, [r2, #112] @ 0x70 800d27c: e00e b.n 800d29c } else { /* set overall return value */ status = ret; 800d27e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d282: f887 311e strb.w r3, [r7, #286] @ 0x11e 800d286: e009 b.n 800d29c 800d288: 58024400 .word 0x58024400 800d28c: 58024800 .word 0x58024800 800d290: 00ffffcf .word 0x00ffffcf } } else { /* set overall return value */ status = ret; 800d294: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d298: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART1/6 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 800d29c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d2a0: e9d3 2300 ldrd r2, r3, [r3] 800d2a4: f002 0301 and.w r3, r2, #1 800d2a8: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 800d2ac: 2300 movs r3, #0 800d2ae: f8c7 30bc str.w r3, [r7, #188] @ 0xbc 800d2b2: e9d7 122e ldrd r1, r2, [r7, #184] @ 0xb8 800d2b6: 460b mov r3, r1 800d2b8: 4313 orrs r3, r2 800d2ba: f000 8089 beq.w 800d3d0 { switch (PeriphClkInit->Usart16ClockSelection) 800d2be: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d2c2: 6fdb ldr r3, [r3, #124] @ 0x7c 800d2c4: 2b28 cmp r3, #40 @ 0x28 800d2c6: d86b bhi.n 800d3a0 800d2c8: a201 add r2, pc, #4 @ (adr r2, 800d2d0 ) 800d2ca: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d2ce: bf00 nop 800d2d0: 0800d3a9 .word 0x0800d3a9 800d2d4: 0800d3a1 .word 0x0800d3a1 800d2d8: 0800d3a1 .word 0x0800d3a1 800d2dc: 0800d3a1 .word 0x0800d3a1 800d2e0: 0800d3a1 .word 0x0800d3a1 800d2e4: 0800d3a1 .word 0x0800d3a1 800d2e8: 0800d3a1 .word 0x0800d3a1 800d2ec: 0800d3a1 .word 0x0800d3a1 800d2f0: 0800d375 .word 0x0800d375 800d2f4: 0800d3a1 .word 0x0800d3a1 800d2f8: 0800d3a1 .word 0x0800d3a1 800d2fc: 0800d3a1 .word 0x0800d3a1 800d300: 0800d3a1 .word 0x0800d3a1 800d304: 0800d3a1 .word 0x0800d3a1 800d308: 0800d3a1 .word 0x0800d3a1 800d30c: 0800d3a1 .word 0x0800d3a1 800d310: 0800d38b .word 0x0800d38b 800d314: 0800d3a1 .word 0x0800d3a1 800d318: 0800d3a1 .word 0x0800d3a1 800d31c: 0800d3a1 .word 0x0800d3a1 800d320: 0800d3a1 .word 0x0800d3a1 800d324: 0800d3a1 .word 0x0800d3a1 800d328: 0800d3a1 .word 0x0800d3a1 800d32c: 0800d3a1 .word 0x0800d3a1 800d330: 0800d3a9 .word 0x0800d3a9 800d334: 0800d3a1 .word 0x0800d3a1 800d338: 0800d3a1 .word 0x0800d3a1 800d33c: 0800d3a1 .word 0x0800d3a1 800d340: 0800d3a1 .word 0x0800d3a1 800d344: 0800d3a1 .word 0x0800d3a1 800d348: 0800d3a1 .word 0x0800d3a1 800d34c: 0800d3a1 .word 0x0800d3a1 800d350: 0800d3a9 .word 0x0800d3a9 800d354: 0800d3a1 .word 0x0800d3a1 800d358: 0800d3a1 .word 0x0800d3a1 800d35c: 0800d3a1 .word 0x0800d3a1 800d360: 0800d3a1 .word 0x0800d3a1 800d364: 0800d3a1 .word 0x0800d3a1 800d368: 0800d3a1 .word 0x0800d3a1 800d36c: 0800d3a1 .word 0x0800d3a1 800d370: 0800d3a9 .word 0x0800d3a9 case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ /* USART1/6 clock source configuration done later after clock selection check */ break; case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d374: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d378: 3308 adds r3, #8 800d37a: 2101 movs r1, #1 800d37c: 4618 mov r0, r3 800d37e: f001 fe79 bl 800f074 800d382: 4603 mov r3, r0 800d384: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 800d388: e00f b.n 800d3aa case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d38a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d38e: 3328 adds r3, #40 @ 0x28 800d390: 2101 movs r1, #1 800d392: 4618 mov r0, r3 800d394: f001 ff20 bl 800f1d8 800d398: 4603 mov r3, r0 800d39a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 800d39e: e004 b.n 800d3aa /* LSE, oscillator is used as source of USART1/6 clock */ /* USART1/6 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d3a0: 2301 movs r3, #1 800d3a2: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d3a6: e000 b.n 800d3aa break; 800d3a8: bf00 nop } if (ret == HAL_OK) 800d3aa: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d3ae: 2b00 cmp r3, #0 800d3b0: d10a bne.n 800d3c8 { /* Set the source of USART1/6 clock */ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 800d3b2: 4bbf ldr r3, [pc, #764] @ (800d6b0 ) 800d3b4: 6d5b ldr r3, [r3, #84] @ 0x54 800d3b6: f023 0138 bic.w r1, r3, #56 @ 0x38 800d3ba: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d3be: 6fdb ldr r3, [r3, #124] @ 0x7c 800d3c0: 4abb ldr r2, [pc, #748] @ (800d6b0 ) 800d3c2: 430b orrs r3, r1 800d3c4: 6553 str r3, [r2, #84] @ 0x54 800d3c6: e003 b.n 800d3d0 } else { /* set overall return value */ status = ret; 800d3c8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d3cc: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 800d3d0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d3d4: e9d3 2300 ldrd r2, r3, [r3] 800d3d8: f002 0302 and.w r3, r2, #2 800d3dc: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 800d3e0: 2300 movs r3, #0 800d3e2: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 800d3e6: e9d7 122c ldrd r1, r2, [r7, #176] @ 0xb0 800d3ea: 460b mov r3, r1 800d3ec: 4313 orrs r3, r2 800d3ee: d041 beq.n 800d474 { switch (PeriphClkInit->Usart234578ClockSelection) 800d3f0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d3f4: 6f9b ldr r3, [r3, #120] @ 0x78 800d3f6: 2b05 cmp r3, #5 800d3f8: d824 bhi.n 800d444 800d3fa: a201 add r2, pc, #4 @ (adr r2, 800d400 ) 800d3fc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d400: 0800d44d .word 0x0800d44d 800d404: 0800d419 .word 0x0800d419 800d408: 0800d42f .word 0x0800d42f 800d40c: 0800d44d .word 0x0800d44d 800d410: 0800d44d .word 0x0800d44d 800d414: 0800d44d .word 0x0800d44d case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d418: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d41c: 3308 adds r3, #8 800d41e: 2101 movs r1, #1 800d420: 4618 mov r0, r3 800d422: f001 fe27 bl 800f074 800d426: 4603 mov r3, r0 800d428: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 800d42c: e00f b.n 800d44e case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d42e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d432: 3328 adds r3, #40 @ 0x28 800d434: 2101 movs r1, #1 800d436: 4618 mov r0, r3 800d438: f001 fece bl 800f1d8 800d43c: 4603 mov r3, r0 800d43e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 800d442: e004 b.n 800d44e /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d444: 2301 movs r3, #1 800d446: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d44a: e000 b.n 800d44e break; 800d44c: bf00 nop } if (ret == HAL_OK) 800d44e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d452: 2b00 cmp r3, #0 800d454: d10a bne.n 800d46c { /* Set the source of USART2/3/4/5/7/8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 800d456: 4b96 ldr r3, [pc, #600] @ (800d6b0 ) 800d458: 6d5b ldr r3, [r3, #84] @ 0x54 800d45a: f023 0107 bic.w r1, r3, #7 800d45e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d462: 6f9b ldr r3, [r3, #120] @ 0x78 800d464: 4a92 ldr r2, [pc, #584] @ (800d6b0 ) 800d466: 430b orrs r3, r1 800d468: 6553 str r3, [r2, #84] @ 0x54 800d46a: e003 b.n 800d474 } else { /* set overall return value */ status = ret; 800d46c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d470: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- LPUART1 Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 800d474: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d478: e9d3 2300 ldrd r2, r3, [r3] 800d47c: f002 0304 and.w r3, r2, #4 800d480: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 800d484: 2300 movs r3, #0 800d486: f8c7 30ac str.w r3, [r7, #172] @ 0xac 800d48a: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 800d48e: 460b mov r3, r1 800d490: 4313 orrs r3, r2 800d492: d044 beq.n 800d51e { switch (PeriphClkInit->Lpuart1ClockSelection) 800d494: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d498: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800d49c: 2b05 cmp r3, #5 800d49e: d825 bhi.n 800d4ec 800d4a0: a201 add r2, pc, #4 @ (adr r2, 800d4a8 ) 800d4a2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d4a6: bf00 nop 800d4a8: 0800d4f5 .word 0x0800d4f5 800d4ac: 0800d4c1 .word 0x0800d4c1 800d4b0: 0800d4d7 .word 0x0800d4d7 800d4b4: 0800d4f5 .word 0x0800d4f5 800d4b8: 0800d4f5 .word 0x0800d4f5 800d4bc: 0800d4f5 .word 0x0800d4f5 case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d4c0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d4c4: 3308 adds r3, #8 800d4c6: 2101 movs r1, #1 800d4c8: 4618 mov r0, r3 800d4ca: f001 fdd3 bl 800f074 800d4ce: 4603 mov r3, r0 800d4d0: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 800d4d4: e00f b.n 800d4f6 case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d4d6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d4da: 3328 adds r3, #40 @ 0x28 800d4dc: 2101 movs r1, #1 800d4de: 4618 mov r0, r3 800d4e0: f001 fe7a bl 800f1d8 800d4e4: 4603 mov r3, r0 800d4e6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 800d4ea: e004 b.n 800d4f6 /* LSE, oscillator is used as source of LPUART1 clock */ /* LPUART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d4ec: 2301 movs r3, #1 800d4ee: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d4f2: e000 b.n 800d4f6 break; 800d4f4: bf00 nop } if (ret == HAL_OK) 800d4f6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d4fa: 2b00 cmp r3, #0 800d4fc: d10b bne.n 800d516 { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 800d4fe: 4b6c ldr r3, [pc, #432] @ (800d6b0 ) 800d500: 6d9b ldr r3, [r3, #88] @ 0x58 800d502: f023 0107 bic.w r1, r3, #7 800d506: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d50a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800d50e: 4a68 ldr r2, [pc, #416] @ (800d6b0 ) 800d510: 430b orrs r3, r1 800d512: 6593 str r3, [r2, #88] @ 0x58 800d514: e003 b.n 800d51e } else { /* set overall return value */ status = ret; 800d516: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d51a: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 800d51e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d522: e9d3 2300 ldrd r2, r3, [r3] 800d526: f002 0320 and.w r3, r2, #32 800d52a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 800d52e: 2300 movs r3, #0 800d530: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 800d534: e9d7 1228 ldrd r1, r2, [r7, #160] @ 0xa0 800d538: 460b mov r3, r1 800d53a: 4313 orrs r3, r2 800d53c: d055 beq.n 800d5ea { switch (PeriphClkInit->Lptim1ClockSelection) 800d53e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d542: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800d546: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800d54a: d033 beq.n 800d5b4 800d54c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800d550: d82c bhi.n 800d5ac 800d552: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800d556: d02f beq.n 800d5b8 800d558: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800d55c: d826 bhi.n 800d5ac 800d55e: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800d562: d02b beq.n 800d5bc 800d564: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800d568: d820 bhi.n 800d5ac 800d56a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d56e: d012 beq.n 800d596 800d570: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d574: d81a bhi.n 800d5ac 800d576: 2b00 cmp r3, #0 800d578: d022 beq.n 800d5c0 800d57a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800d57e: d115 bne.n 800d5ac /* LPTIM1 clock source configuration done later after clock selection check */ break; case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d580: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d584: 3308 adds r3, #8 800d586: 2100 movs r1, #0 800d588: 4618 mov r0, r3 800d58a: f001 fd73 bl 800f074 800d58e: 4603 mov r3, r0 800d590: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 800d594: e015 b.n 800d5c2 case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d596: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d59a: 3328 adds r3, #40 @ 0x28 800d59c: 2102 movs r1, #2 800d59e: 4618 mov r0, r3 800d5a0: f001 fe1a bl 800f1d8 800d5a4: 4603 mov r3, r0 800d5a6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 800d5aa: e00a b.n 800d5c2 /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ /* LPTIM1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d5ac: 2301 movs r3, #1 800d5ae: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d5b2: e006 b.n 800d5c2 break; 800d5b4: bf00 nop 800d5b6: e004 b.n 800d5c2 break; 800d5b8: bf00 nop 800d5ba: e002 b.n 800d5c2 break; 800d5bc: bf00 nop 800d5be: e000 b.n 800d5c2 break; 800d5c0: bf00 nop } if (ret == HAL_OK) 800d5c2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d5c6: 2b00 cmp r3, #0 800d5c8: d10b bne.n 800d5e2 { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 800d5ca: 4b39 ldr r3, [pc, #228] @ (800d6b0 ) 800d5cc: 6d5b ldr r3, [r3, #84] @ 0x54 800d5ce: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 800d5d2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d5d6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800d5da: 4a35 ldr r2, [pc, #212] @ (800d6b0 ) 800d5dc: 430b orrs r3, r1 800d5de: 6553 str r3, [r2, #84] @ 0x54 800d5e0: e003 b.n 800d5ea } else { /* set overall return value */ status = ret; 800d5e2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d5e6: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 800d5ea: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d5ee: e9d3 2300 ldrd r2, r3, [r3] 800d5f2: f002 0340 and.w r3, r2, #64 @ 0x40 800d5f6: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800d5fa: 2300 movs r3, #0 800d5fc: f8c7 309c str.w r3, [r7, #156] @ 0x9c 800d600: e9d7 1226 ldrd r1, r2, [r7, #152] @ 0x98 800d604: 460b mov r3, r1 800d606: 4313 orrs r3, r2 800d608: d058 beq.n 800d6bc { switch (PeriphClkInit->Lptim2ClockSelection) 800d60a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d60e: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800d612: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800d616: d033 beq.n 800d680 800d618: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800d61c: d82c bhi.n 800d678 800d61e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d622: d02f beq.n 800d684 800d624: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d628: d826 bhi.n 800d678 800d62a: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 800d62e: d02b beq.n 800d688 800d630: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 800d634: d820 bhi.n 800d678 800d636: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800d63a: d012 beq.n 800d662 800d63c: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800d640: d81a bhi.n 800d678 800d642: 2b00 cmp r3, #0 800d644: d022 beq.n 800d68c 800d646: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800d64a: d115 bne.n 800d678 /* LPTIM2 clock source configuration done later after clock selection check */ break; case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d64c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d650: 3308 adds r3, #8 800d652: 2100 movs r1, #0 800d654: 4618 mov r0, r3 800d656: f001 fd0d bl 800f074 800d65a: 4603 mov r3, r0 800d65c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 800d660: e015 b.n 800d68e case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d662: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d666: 3328 adds r3, #40 @ 0x28 800d668: 2102 movs r1, #2 800d66a: 4618 mov r0, r3 800d66c: f001 fdb4 bl 800f1d8 800d670: 4603 mov r3, r0 800d672: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 800d676: e00a b.n 800d68e /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ /* LPTIM2 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d678: 2301 movs r3, #1 800d67a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d67e: e006 b.n 800d68e break; 800d680: bf00 nop 800d682: e004 b.n 800d68e break; 800d684: bf00 nop 800d686: e002 b.n 800d68e break; 800d688: bf00 nop 800d68a: e000 b.n 800d68e break; 800d68c: bf00 nop } if (ret == HAL_OK) 800d68e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d692: 2b00 cmp r3, #0 800d694: d10e bne.n 800d6b4 { /* Set the source of LPTIM2 clock*/ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 800d696: 4b06 ldr r3, [pc, #24] @ (800d6b0 ) 800d698: 6d9b ldr r3, [r3, #88] @ 0x58 800d69a: f423 51e0 bic.w r1, r3, #7168 @ 0x1c00 800d69e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d6a2: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800d6a6: 4a02 ldr r2, [pc, #8] @ (800d6b0 ) 800d6a8: 430b orrs r3, r1 800d6aa: 6593 str r3, [r2, #88] @ 0x58 800d6ac: e006 b.n 800d6bc 800d6ae: bf00 nop 800d6b0: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800d6b4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d6b8: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM345 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 800d6bc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d6c0: e9d3 2300 ldrd r2, r3, [r3] 800d6c4: f002 0380 and.w r3, r2, #128 @ 0x80 800d6c8: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800d6cc: 2300 movs r3, #0 800d6ce: f8c7 3094 str.w r3, [r7, #148] @ 0x94 800d6d2: e9d7 1224 ldrd r1, r2, [r7, #144] @ 0x90 800d6d6: 460b mov r3, r1 800d6d8: 4313 orrs r3, r2 800d6da: d055 beq.n 800d788 { switch (PeriphClkInit->Lptim345ClockSelection) 800d6dc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d6e0: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800d6e4: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 800d6e8: d033 beq.n 800d752 800d6ea: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 800d6ee: d82c bhi.n 800d74a 800d6f0: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800d6f4: d02f beq.n 800d756 800d6f6: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800d6fa: d826 bhi.n 800d74a 800d6fc: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800d700: d02b beq.n 800d75a 800d702: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800d706: d820 bhi.n 800d74a 800d708: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800d70c: d012 beq.n 800d734 800d70e: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800d712: d81a bhi.n 800d74a 800d714: 2b00 cmp r3, #0 800d716: d022 beq.n 800d75e 800d718: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800d71c: d115 bne.n 800d74a case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d71e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d722: 3308 adds r3, #8 800d724: 2100 movs r1, #0 800d726: 4618 mov r0, r3 800d728: f001 fca4 bl 800f074 800d72c: 4603 mov r3, r0 800d72e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800d732: e015 b.n 800d760 case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d734: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d738: 3328 adds r3, #40 @ 0x28 800d73a: 2102 movs r1, #2 800d73c: 4618 mov r0, r3 800d73e: f001 fd4b bl 800f1d8 800d742: 4603 mov r3, r0 800d744: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800d748: e00a b.n 800d760 /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d74a: 2301 movs r3, #1 800d74c: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d750: e006 b.n 800d760 break; 800d752: bf00 nop 800d754: e004 b.n 800d760 break; 800d756: bf00 nop 800d758: e002 b.n 800d760 break; 800d75a: bf00 nop 800d75c: e000 b.n 800d760 break; 800d75e: bf00 nop } if (ret == HAL_OK) 800d760: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d764: 2b00 cmp r3, #0 800d766: d10b bne.n 800d780 { /* Set the source of LPTIM3/4/5 clock */ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 800d768: 4bbb ldr r3, [pc, #748] @ (800da58 ) 800d76a: 6d9b ldr r3, [r3, #88] @ 0x58 800d76c: f423 4160 bic.w r1, r3, #57344 @ 0xe000 800d770: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d774: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800d778: 4ab7 ldr r2, [pc, #732] @ (800da58 ) 800d77a: 430b orrs r3, r1 800d77c: 6593 str r3, [r2, #88] @ 0x58 800d77e: e003 b.n 800d788 } else { /* set overall return value */ status = ret; 800d780: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d784: f887 311e strb.w r3, [r7, #286] @ 0x11e __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); } #else if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 800d788: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d78c: e9d3 2300 ldrd r2, r3, [r3] 800d790: f002 0308 and.w r3, r2, #8 800d794: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800d798: 2300 movs r3, #0 800d79a: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800d79e: e9d7 1222 ldrd r1, r2, [r7, #136] @ 0x88 800d7a2: 460b mov r3, r1 800d7a4: 4313 orrs r3, r2 800d7a6: d01e beq.n 800d7e6 { /* Check the parameters */ assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3) 800d7a8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7ac: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800d7b0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d7b4: d10c bne.n 800d7d0 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800d7b6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7ba: 3328 adds r3, #40 @ 0x28 800d7bc: 2102 movs r1, #2 800d7be: 4618 mov r0, r3 800d7c0: f001 fd0a bl 800f1d8 800d7c4: 4603 mov r3, r0 800d7c6: 2b00 cmp r3, #0 800d7c8: d002 beq.n 800d7d0 { status = HAL_ERROR; 800d7ca: 2301 movs r3, #1 800d7cc: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 800d7d0: 4ba1 ldr r3, [pc, #644] @ (800da58 ) 800d7d2: 6d5b ldr r3, [r3, #84] @ 0x54 800d7d4: f423 5140 bic.w r1, r3, #12288 @ 0x3000 800d7d8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7dc: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800d7e0: 4a9d ldr r2, [pc, #628] @ (800da58 ) 800d7e2: 430b orrs r3, r1 800d7e4: 6553 str r3, [r2, #84] @ 0x54 } #endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 800d7e6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7ea: e9d3 2300 ldrd r2, r3, [r3] 800d7ee: f002 0310 and.w r3, r2, #16 800d7f2: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800d7f6: 2300 movs r3, #0 800d7f8: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800d7fc: e9d7 1220 ldrd r1, r2, [r7, #128] @ 0x80 800d800: 460b mov r3, r1 800d802: 4313 orrs r3, r2 800d804: d01e beq.n 800d844 { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) 800d806: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d80a: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800d80e: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d812: d10c bne.n 800d82e { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800d814: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d818: 3328 adds r3, #40 @ 0x28 800d81a: 2102 movs r1, #2 800d81c: 4618 mov r0, r3 800d81e: f001 fcdb bl 800f1d8 800d822: 4603 mov r3, r0 800d824: 2b00 cmp r3, #0 800d826: d002 beq.n 800d82e { status = HAL_ERROR; 800d828: 2301 movs r3, #1 800d82a: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 800d82e: 4b8a ldr r3, [pc, #552] @ (800da58 ) 800d830: 6d9b ldr r3, [r3, #88] @ 0x58 800d832: f423 7140 bic.w r1, r3, #768 @ 0x300 800d836: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d83a: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800d83e: 4a86 ldr r2, [pc, #536] @ (800da58 ) 800d840: 430b orrs r3, r1 800d842: 6593 str r3, [r2, #88] @ 0x58 } /*---------------------------- ADC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 800d844: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d848: e9d3 2300 ldrd r2, r3, [r3] 800d84c: f402 2300 and.w r3, r2, #524288 @ 0x80000 800d850: 67bb str r3, [r7, #120] @ 0x78 800d852: 2300 movs r3, #0 800d854: 67fb str r3, [r7, #124] @ 0x7c 800d856: e9d7 121e ldrd r1, r2, [r7, #120] @ 0x78 800d85a: 460b mov r3, r1 800d85c: 4313 orrs r3, r2 800d85e: d03e beq.n 800d8de { switch (PeriphClkInit->AdcClockSelection) 800d860: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d864: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 800d868: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d86c: d022 beq.n 800d8b4 800d86e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d872: d81b bhi.n 800d8ac 800d874: 2b00 cmp r3, #0 800d876: d003 beq.n 800d880 800d878: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800d87c: d00b beq.n 800d896 800d87e: e015 b.n 800d8ac { case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d880: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d884: 3308 adds r3, #8 800d886: 2100 movs r1, #0 800d888: 4618 mov r0, r3 800d88a: f001 fbf3 bl 800f074 800d88e: 4603 mov r3, r0 800d890: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 800d894: e00f b.n 800d8b6 case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d896: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d89a: 3328 adds r3, #40 @ 0x28 800d89c: 2102 movs r1, #2 800d89e: 4618 mov r0, r3 800d8a0: f001 fc9a bl 800f1d8 800d8a4: 4603 mov r3, r0 800d8a6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 800d8aa: e004 b.n 800d8b6 /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ /* ADC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d8ac: 2301 movs r3, #1 800d8ae: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d8b2: e000 b.n 800d8b6 break; 800d8b4: bf00 nop } if (ret == HAL_OK) 800d8b6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d8ba: 2b00 cmp r3, #0 800d8bc: d10b bne.n 800d8d6 { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 800d8be: 4b66 ldr r3, [pc, #408] @ (800da58 ) 800d8c0: 6d9b ldr r3, [r3, #88] @ 0x58 800d8c2: f423 3140 bic.w r1, r3, #196608 @ 0x30000 800d8c6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8ca: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 800d8ce: 4a62 ldr r2, [pc, #392] @ (800da58 ) 800d8d0: 430b orrs r3, r1 800d8d2: 6593 str r3, [r2, #88] @ 0x58 800d8d4: e003 b.n 800d8de } else { /* set overall return value */ status = ret; 800d8d6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d8da: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ USB Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 800d8de: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8e2: e9d3 2300 ldrd r2, r3, [r3] 800d8e6: f402 2380 and.w r3, r2, #262144 @ 0x40000 800d8ea: 673b str r3, [r7, #112] @ 0x70 800d8ec: 2300 movs r3, #0 800d8ee: 677b str r3, [r7, #116] @ 0x74 800d8f0: e9d7 121c ldrd r1, r2, [r7, #112] @ 0x70 800d8f4: 460b mov r3, r1 800d8f6: 4313 orrs r3, r2 800d8f8: d03b beq.n 800d972 { switch (PeriphClkInit->UsbClockSelection) 800d8fa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8fe: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800d902: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800d906: d01f beq.n 800d948 800d908: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800d90c: d818 bhi.n 800d940 800d90e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800d912: d003 beq.n 800d91c 800d914: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800d918: d007 beq.n 800d92a 800d91a: e011 b.n 800d940 { case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ /* Enable USB Clock output generated form System USB . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d91c: 4b4e ldr r3, [pc, #312] @ (800da58 ) 800d91e: 6adb ldr r3, [r3, #44] @ 0x2c 800d920: 4a4d ldr r2, [pc, #308] @ (800da58 ) 800d922: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d926: 62d3 str r3, [r2, #44] @ 0x2c /* USB clock source configuration done later after clock selection check */ break; 800d928: e00f b.n 800d94a case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d92a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d92e: 3328 adds r3, #40 @ 0x28 800d930: 2101 movs r1, #1 800d932: 4618 mov r0, r3 800d934: f001 fc50 bl 800f1d8 800d938: 4603 mov r3, r0 800d93a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USB clock source configuration done later after clock selection check */ break; 800d93e: e004 b.n 800d94a /* HSI48 oscillator is used as source of USB clock */ /* USB clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d940: 2301 movs r3, #1 800d942: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d946: e000 b.n 800d94a break; 800d948: bf00 nop } if (ret == HAL_OK) 800d94a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d94e: 2b00 cmp r3, #0 800d950: d10b bne.n 800d96a { /* Set the source of USB clock*/ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 800d952: 4b41 ldr r3, [pc, #260] @ (800da58 ) 800d954: 6d5b ldr r3, [r3, #84] @ 0x54 800d956: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800d95a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d95e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800d962: 4a3d ldr r2, [pc, #244] @ (800da58 ) 800d964: 430b orrs r3, r1 800d966: 6553 str r3, [r2, #84] @ 0x54 800d968: e003 b.n 800d972 } else { /* set overall return value */ status = ret; 800d96a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d96e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------------- SDMMC Configuration ------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 800d972: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d976: e9d3 2300 ldrd r2, r3, [r3] 800d97a: f402 3380 and.w r3, r2, #65536 @ 0x10000 800d97e: 66bb str r3, [r7, #104] @ 0x68 800d980: 2300 movs r3, #0 800d982: 66fb str r3, [r7, #108] @ 0x6c 800d984: e9d7 121a ldrd r1, r2, [r7, #104] @ 0x68 800d988: 460b mov r3, r1 800d98a: 4313 orrs r3, r2 800d98c: d031 beq.n 800d9f2 { /* Check the parameters */ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); switch (PeriphClkInit->SdmmcClockSelection) 800d98e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d992: 6d1b ldr r3, [r3, #80] @ 0x50 800d994: 2b00 cmp r3, #0 800d996: d003 beq.n 800d9a0 800d998: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800d99c: d007 beq.n 800d9ae 800d99e: e011 b.n 800d9c4 { case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ /* Enable SDMMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d9a0: 4b2d ldr r3, [pc, #180] @ (800da58 ) 800d9a2: 6adb ldr r3, [r3, #44] @ 0x2c 800d9a4: 4a2c ldr r2, [pc, #176] @ (800da58 ) 800d9a6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d9aa: 62d3 str r3, [r2, #44] @ 0x2c /* SDMMC clock source configuration done later after clock selection check */ break; 800d9ac: e00e b.n 800d9cc case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800d9ae: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d9b2: 3308 adds r3, #8 800d9b4: 2102 movs r1, #2 800d9b6: 4618 mov r0, r3 800d9b8: f001 fb5c bl 800f074 800d9bc: 4603 mov r3, r0 800d9be: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SDMMC clock source configuration done later after clock selection check */ break; 800d9c2: e003 b.n 800d9cc default: ret = HAL_ERROR; 800d9c4: 2301 movs r3, #1 800d9c6: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d9ca: bf00 nop } if (ret == HAL_OK) 800d9cc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d9d0: 2b00 cmp r3, #0 800d9d2: d10a bne.n 800d9ea { /* Set the source of SDMMC clock*/ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 800d9d4: 4b20 ldr r3, [pc, #128] @ (800da58 ) 800d9d6: 6cdb ldr r3, [r3, #76] @ 0x4c 800d9d8: f423 3180 bic.w r1, r3, #65536 @ 0x10000 800d9dc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d9e0: 6d1b ldr r3, [r3, #80] @ 0x50 800d9e2: 4a1d ldr r2, [pc, #116] @ (800da58 ) 800d9e4: 430b orrs r3, r1 800d9e6: 64d3 str r3, [r2, #76] @ 0x4c 800d9e8: e003 b.n 800d9f2 } else { /* set overall return value */ status = ret; 800d9ea: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d9ee: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /* LTDC */ /*------------------------------ RNG Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 800d9f2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d9f6: e9d3 2300 ldrd r2, r3, [r3] 800d9fa: f402 3300 and.w r3, r2, #131072 @ 0x20000 800d9fe: 663b str r3, [r7, #96] @ 0x60 800da00: 2300 movs r3, #0 800da02: 667b str r3, [r7, #100] @ 0x64 800da04: e9d7 1218 ldrd r1, r2, [r7, #96] @ 0x60 800da08: 460b mov r3, r1 800da0a: 4313 orrs r3, r2 800da0c: d03b beq.n 800da86 { switch (PeriphClkInit->RngClockSelection) 800da0e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da12: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800da16: f5b3 7f40 cmp.w r3, #768 @ 0x300 800da1a: d018 beq.n 800da4e 800da1c: f5b3 7f40 cmp.w r3, #768 @ 0x300 800da20: d811 bhi.n 800da46 800da22: f5b3 7f00 cmp.w r3, #512 @ 0x200 800da26: d014 beq.n 800da52 800da28: f5b3 7f00 cmp.w r3, #512 @ 0x200 800da2c: d80b bhi.n 800da46 800da2e: 2b00 cmp r3, #0 800da30: d014 beq.n 800da5c 800da32: f5b3 7f80 cmp.w r3, #256 @ 0x100 800da36: d106 bne.n 800da46 { case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ /* Enable RNG Clock output generated form System RNG . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800da38: 4b07 ldr r3, [pc, #28] @ (800da58 ) 800da3a: 6adb ldr r3, [r3, #44] @ 0x2c 800da3c: 4a06 ldr r2, [pc, #24] @ (800da58 ) 800da3e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800da42: 62d3 str r3, [r2, #44] @ 0x2c /* RNG clock source configuration done later after clock selection check */ break; 800da44: e00b b.n 800da5e /* HSI48 oscillator is used as source of RNG clock */ /* RNG clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800da46: 2301 movs r3, #1 800da48: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800da4c: e007 b.n 800da5e break; 800da4e: bf00 nop 800da50: e005 b.n 800da5e break; 800da52: bf00 nop 800da54: e003 b.n 800da5e 800da56: bf00 nop 800da58: 58024400 .word 0x58024400 break; 800da5c: bf00 nop } if (ret == HAL_OK) 800da5e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800da62: 2b00 cmp r3, #0 800da64: d10b bne.n 800da7e { /* Set the source of RNG clock*/ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 800da66: 4bba ldr r3, [pc, #744] @ (800dd50 ) 800da68: 6d5b ldr r3, [r3, #84] @ 0x54 800da6a: f423 7140 bic.w r1, r3, #768 @ 0x300 800da6e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da72: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800da76: 4ab6 ldr r2, [pc, #728] @ (800dd50 ) 800da78: 430b orrs r3, r1 800da7a: 6553 str r3, [r2, #84] @ 0x54 800da7c: e003 b.n 800da86 } else { /* set overall return value */ status = ret; 800da7e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800da82: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ SWPMI1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 800da86: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da8a: e9d3 2300 ldrd r2, r3, [r3] 800da8e: f402 1380 and.w r3, r2, #1048576 @ 0x100000 800da92: 65bb str r3, [r7, #88] @ 0x58 800da94: 2300 movs r3, #0 800da96: 65fb str r3, [r7, #92] @ 0x5c 800da98: e9d7 1216 ldrd r1, r2, [r7, #88] @ 0x58 800da9c: 460b mov r3, r1 800da9e: 4313 orrs r3, r2 800daa0: d009 beq.n 800dab6 { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 800daa2: 4bab ldr r3, [pc, #684] @ (800dd50 ) 800daa4: 6d1b ldr r3, [r3, #80] @ 0x50 800daa6: f023 4100 bic.w r1, r3, #2147483648 @ 0x80000000 800daaa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800daae: 6f5b ldr r3, [r3, #116] @ 0x74 800dab0: 4aa7 ldr r2, [pc, #668] @ (800dd50 ) 800dab2: 430b orrs r3, r1 800dab4: 6513 str r3, [r2, #80] @ 0x50 } #if defined(HRTIM1) /*------------------------------ HRTIM1 clock Configuration ----------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) 800dab6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800daba: e9d3 2300 ldrd r2, r3, [r3] 800dabe: f002 5380 and.w r3, r2, #268435456 @ 0x10000000 800dac2: 653b str r3, [r7, #80] @ 0x50 800dac4: 2300 movs r3, #0 800dac6: 657b str r3, [r7, #84] @ 0x54 800dac8: e9d7 1214 ldrd r1, r2, [r7, #80] @ 0x50 800dacc: 460b mov r3, r1 800dace: 4313 orrs r3, r2 800dad0: d00a beq.n 800dae8 { /* Check the parameters */ assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); 800dad2: 4b9f ldr r3, [pc, #636] @ (800dd50 ) 800dad4: 691b ldr r3, [r3, #16] 800dad6: f423 4180 bic.w r1, r3, #16384 @ 0x4000 800dada: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dade: f8d3 30b8 ldr.w r3, [r3, #184] @ 0xb8 800dae2: 4a9b ldr r2, [pc, #620] @ (800dd50 ) 800dae4: 430b orrs r3, r1 800dae6: 6113 str r3, [r2, #16] } #endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 800dae8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800daec: e9d3 2300 ldrd r2, r3, [r3] 800daf0: f402 1300 and.w r3, r2, #2097152 @ 0x200000 800daf4: 64bb str r3, [r7, #72] @ 0x48 800daf6: 2300 movs r3, #0 800daf8: 64fb str r3, [r7, #76] @ 0x4c 800dafa: e9d7 1212 ldrd r1, r2, [r7, #72] @ 0x48 800dafe: 460b mov r3, r1 800db00: 4313 orrs r3, r2 800db02: d009 beq.n 800db18 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 800db04: 4b92 ldr r3, [pc, #584] @ (800dd50 ) 800db06: 6d1b ldr r3, [r3, #80] @ 0x50 800db08: f023 7180 bic.w r1, r3, #16777216 @ 0x1000000 800db0c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db10: 6edb ldr r3, [r3, #108] @ 0x6c 800db12: 4a8f ldr r2, [pc, #572] @ (800dd50 ) 800db14: 430b orrs r3, r1 800db16: 6513 str r3, [r2, #80] @ 0x50 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); } #endif /* DFSDM2 */ /*------------------------------------ TIM configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 800db18: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db1c: e9d3 2300 ldrd r2, r3, [r3] 800db20: f002 4380 and.w r3, r2, #1073741824 @ 0x40000000 800db24: 643b str r3, [r7, #64] @ 0x40 800db26: 2300 movs r3, #0 800db28: 647b str r3, [r7, #68] @ 0x44 800db2a: e9d7 1210 ldrd r1, r2, [r7, #64] @ 0x40 800db2e: 460b mov r3, r1 800db30: 4313 orrs r3, r2 800db32: d00e beq.n 800db52 { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 800db34: 4b86 ldr r3, [pc, #536] @ (800dd50 ) 800db36: 691b ldr r3, [r3, #16] 800db38: 4a85 ldr r2, [pc, #532] @ (800dd50 ) 800db3a: f423 4300 bic.w r3, r3, #32768 @ 0x8000 800db3e: 6113 str r3, [r2, #16] 800db40: 4b83 ldr r3, [pc, #524] @ (800dd50 ) 800db42: 6919 ldr r1, [r3, #16] 800db44: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db48: f8d3 30bc ldr.w r3, [r3, #188] @ 0xbc 800db4c: 4a80 ldr r2, [pc, #512] @ (800dd50 ) 800db4e: 430b orrs r3, r1 800db50: 6113 str r3, [r2, #16] } /*------------------------------------ CKPER configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 800db52: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db56: e9d3 2300 ldrd r2, r3, [r3] 800db5a: f002 4300 and.w r3, r2, #2147483648 @ 0x80000000 800db5e: 63bb str r3, [r7, #56] @ 0x38 800db60: 2300 movs r3, #0 800db62: 63fb str r3, [r7, #60] @ 0x3c 800db64: e9d7 120e ldrd r1, r2, [r7, #56] @ 0x38 800db68: 460b mov r3, r1 800db6a: 4313 orrs r3, r2 800db6c: d009 beq.n 800db82 { /* Check the parameters */ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); /* Configure the CKPER clock source */ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 800db6e: 4b78 ldr r3, [pc, #480] @ (800dd50 ) 800db70: 6cdb ldr r3, [r3, #76] @ 0x4c 800db72: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 800db76: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db7a: 6d5b ldr r3, [r3, #84] @ 0x54 800db7c: 4a74 ldr r2, [pc, #464] @ (800dd50 ) 800db7e: 430b orrs r3, r1 800db80: 64d3 str r3, [r2, #76] @ 0x4c } /*------------------------------ CEC Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 800db82: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db86: e9d3 2300 ldrd r2, r3, [r3] 800db8a: f402 0300 and.w r3, r2, #8388608 @ 0x800000 800db8e: 633b str r3, [r7, #48] @ 0x30 800db90: 2300 movs r3, #0 800db92: 637b str r3, [r7, #52] @ 0x34 800db94: e9d7 120c ldrd r1, r2, [r7, #48] @ 0x30 800db98: 460b mov r3, r1 800db9a: 4313 orrs r3, r2 800db9c: d00a beq.n 800dbb4 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC interface clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 800db9e: 4b6c ldr r3, [pc, #432] @ (800dd50 ) 800dba0: 6d5b ldr r3, [r3, #84] @ 0x54 800dba2: f423 0140 bic.w r1, r3, #12582912 @ 0xc00000 800dba6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dbaa: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800dbae: 4a68 ldr r2, [pc, #416] @ (800dd50 ) 800dbb0: 430b orrs r3, r1 800dbb2: 6553 str r3, [r2, #84] @ 0x54 } /*---------------------------- PLL2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) 800dbb4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dbb8: e9d3 2300 ldrd r2, r3, [r3] 800dbbc: 2100 movs r1, #0 800dbbe: 62b9 str r1, [r7, #40] @ 0x28 800dbc0: f003 0301 and.w r3, r3, #1 800dbc4: 62fb str r3, [r7, #44] @ 0x2c 800dbc6: e9d7 120a ldrd r1, r2, [r7, #40] @ 0x28 800dbca: 460b mov r3, r1 800dbcc: 4313 orrs r3, r2 800dbce: d011 beq.n 800dbf4 { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800dbd0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dbd4: 3308 adds r3, #8 800dbd6: 2100 movs r1, #0 800dbd8: 4618 mov r0, r3 800dbda: f001 fa4b bl 800f074 800dbde: 4603 mov r3, r0 800dbe0: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dbe4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dbe8: 2b00 cmp r3, #0 800dbea: d003 beq.n 800dbf4 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dbec: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dbf0: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) 800dbf4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dbf8: e9d3 2300 ldrd r2, r3, [r3] 800dbfc: 2100 movs r1, #0 800dbfe: 6239 str r1, [r7, #32] 800dc00: f003 0302 and.w r3, r3, #2 800dc04: 627b str r3, [r7, #36] @ 0x24 800dc06: e9d7 1208 ldrd r1, r2, [r7, #32] 800dc0a: 460b mov r3, r1 800dc0c: 4313 orrs r3, r2 800dc0e: d011 beq.n 800dc34 { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800dc10: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc14: 3308 adds r3, #8 800dc16: 2101 movs r1, #1 800dc18: 4618 mov r0, r3 800dc1a: f001 fa2b bl 800f074 800dc1e: 4603 mov r3, r0 800dc20: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dc24: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc28: 2b00 cmp r3, #0 800dc2a: d003 beq.n 800dc34 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dc2c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc30: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) 800dc34: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc38: e9d3 2300 ldrd r2, r3, [r3] 800dc3c: 2100 movs r1, #0 800dc3e: 61b9 str r1, [r7, #24] 800dc40: f003 0304 and.w r3, r3, #4 800dc44: 61fb str r3, [r7, #28] 800dc46: e9d7 1206 ldrd r1, r2, [r7, #24] 800dc4a: 460b mov r3, r1 800dc4c: 4313 orrs r3, r2 800dc4e: d011 beq.n 800dc74 { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800dc50: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc54: 3308 adds r3, #8 800dc56: 2102 movs r1, #2 800dc58: 4618 mov r0, r3 800dc5a: f001 fa0b bl 800f074 800dc5e: 4603 mov r3, r0 800dc60: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dc64: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc68: 2b00 cmp r3, #0 800dc6a: d003 beq.n 800dc74 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dc6c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc70: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- PLL3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) 800dc74: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc78: e9d3 2300 ldrd r2, r3, [r3] 800dc7c: 2100 movs r1, #0 800dc7e: 6139 str r1, [r7, #16] 800dc80: f003 0308 and.w r3, r3, #8 800dc84: 617b str r3, [r7, #20] 800dc86: e9d7 1204 ldrd r1, r2, [r7, #16] 800dc8a: 460b mov r3, r1 800dc8c: 4313 orrs r3, r2 800dc8e: d011 beq.n 800dcb4 { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800dc90: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc94: 3328 adds r3, #40 @ 0x28 800dc96: 2100 movs r1, #0 800dc98: 4618 mov r0, r3 800dc9a: f001 fa9d bl 800f1d8 800dc9e: 4603 mov r3, r0 800dca0: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dca4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dca8: 2b00 cmp r3, #0 800dcaa: d003 beq.n 800dcb4 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dcac: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dcb0: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) 800dcb4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dcb8: e9d3 2300 ldrd r2, r3, [r3] 800dcbc: 2100 movs r1, #0 800dcbe: 60b9 str r1, [r7, #8] 800dcc0: f003 0310 and.w r3, r3, #16 800dcc4: 60fb str r3, [r7, #12] 800dcc6: e9d7 1202 ldrd r1, r2, [r7, #8] 800dcca: 460b mov r3, r1 800dccc: 4313 orrs r3, r2 800dcce: d011 beq.n 800dcf4 { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800dcd0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dcd4: 3328 adds r3, #40 @ 0x28 800dcd6: 2101 movs r1, #1 800dcd8: 4618 mov r0, r3 800dcda: f001 fa7d bl 800f1d8 800dcde: 4603 mov r3, r0 800dce0: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dce4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dce8: 2b00 cmp r3, #0 800dcea: d003 beq.n 800dcf4 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dcec: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dcf0: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) 800dcf4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dcf8: e9d3 2300 ldrd r2, r3, [r3] 800dcfc: 2100 movs r1, #0 800dcfe: 6039 str r1, [r7, #0] 800dd00: f003 0320 and.w r3, r3, #32 800dd04: 607b str r3, [r7, #4] 800dd06: e9d7 1200 ldrd r1, r2, [r7] 800dd0a: 460b mov r3, r1 800dd0c: 4313 orrs r3, r2 800dd0e: d011 beq.n 800dd34 { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800dd10: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dd14: 3328 adds r3, #40 @ 0x28 800dd16: 2102 movs r1, #2 800dd18: 4618 mov r0, r3 800dd1a: f001 fa5d bl 800f1d8 800dd1e: 4603 mov r3, r0 800dd20: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dd24: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dd28: 2b00 cmp r3, #0 800dd2a: d003 beq.n 800dd34 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dd2c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dd30: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (status == HAL_OK) 800dd34: f897 311e ldrb.w r3, [r7, #286] @ 0x11e 800dd38: 2b00 cmp r3, #0 800dd3a: d101 bne.n 800dd40 { return HAL_OK; 800dd3c: 2300 movs r3, #0 800dd3e: e000 b.n 800dd42 } return HAL_ERROR; 800dd40: 2301 movs r3, #1 } 800dd42: 4618 mov r0, r3 800dd44: f507 7790 add.w r7, r7, #288 @ 0x120 800dd48: 46bd mov sp, r7 800dd4a: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 800dd4e: bf00 nop 800dd50: 58024400 .word 0x58024400 0800dd54 : * @retval Frequency in KHz * * (*) : Available on some STM32H7 lines only. */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) { 800dd54: b580 push {r7, lr} 800dd56: b090 sub sp, #64 @ 0x40 800dd58: af00 add r7, sp, #0 800dd5a: e9c7 0100 strd r0, r1, [r7] /* This variable is used to store the SAI and CKP clock source */ uint32_t saiclocksource; uint32_t ckpclocksource; uint32_t srcclk; if (PeriphClk == RCC_PERIPHCLK_SAI1) 800dd5e: e9d7 2300 ldrd r2, r3, [r7] 800dd62: f5a2 7180 sub.w r1, r2, #256 @ 0x100 800dd66: 430b orrs r3, r1 800dd68: f040 8094 bne.w 800de94 { saiclocksource = __HAL_RCC_GET_SAI1_SOURCE(); 800dd6c: 4b9e ldr r3, [pc, #632] @ (800dfe8 ) 800dd6e: 6d1b ldr r3, [r3, #80] @ 0x50 800dd70: f003 0307 and.w r3, r3, #7 800dd74: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800dd76: 6b3b ldr r3, [r7, #48] @ 0x30 800dd78: 2b04 cmp r3, #4 800dd7a: f200 8087 bhi.w 800de8c 800dd7e: a201 add r2, pc, #4 @ (adr r2, 800dd84 ) 800dd80: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800dd84: 0800dd99 .word 0x0800dd99 800dd88: 0800ddc1 .word 0x0800ddc1 800dd8c: 0800dde9 .word 0x0800dde9 800dd90: 0800de85 .word 0x0800de85 800dd94: 0800de11 .word 0x0800de11 { case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800dd98: 4b93 ldr r3, [pc, #588] @ (800dfe8 ) 800dd9a: 681b ldr r3, [r3, #0] 800dd9c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800dda0: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800dda4: d108 bne.n 800ddb8 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800dda6: f107 0324 add.w r3, r7, #36 @ 0x24 800ddaa: 4618 mov r0, r3 800ddac: f001 f810 bl 800edd0 frequency = pll1_clocks.PLL1_Q_Frequency; 800ddb0: 6abb ldr r3, [r7, #40] @ 0x28 800ddb2: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800ddb4: f000 bd45 b.w 800e842 frequency = 0; 800ddb8: 2300 movs r3, #0 800ddba: 63fb str r3, [r7, #60] @ 0x3c break; 800ddbc: f000 bd41 b.w 800e842 } case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800ddc0: 4b89 ldr r3, [pc, #548] @ (800dfe8 ) 800ddc2: 681b ldr r3, [r3, #0] 800ddc4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800ddc8: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800ddcc: d108 bne.n 800dde0 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800ddce: f107 0318 add.w r3, r7, #24 800ddd2: 4618 mov r0, r3 800ddd4: f000 fd54 bl 800e880 frequency = pll2_clocks.PLL2_P_Frequency; 800ddd8: 69bb ldr r3, [r7, #24] 800ddda: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dddc: f000 bd31 b.w 800e842 frequency = 0; 800dde0: 2300 movs r3, #0 800dde2: 63fb str r3, [r7, #60] @ 0x3c break; 800dde4: f000 bd2d b.w 800e842 } case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800dde8: 4b7f ldr r3, [pc, #508] @ (800dfe8 ) 800ddea: 681b ldr r3, [r3, #0] 800ddec: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800ddf0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800ddf4: d108 bne.n 800de08 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800ddf6: f107 030c add.w r3, r7, #12 800ddfa: 4618 mov r0, r3 800ddfc: f000 fe94 bl 800eb28 frequency = pll3_clocks.PLL3_P_Frequency; 800de00: 68fb ldr r3, [r7, #12] 800de02: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800de04: f000 bd1d b.w 800e842 frequency = 0; 800de08: 2300 movs r3, #0 800de0a: 63fb str r3, [r7, #60] @ 0x3c break; 800de0c: f000 bd19 b.w 800e842 } case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800de10: 4b75 ldr r3, [pc, #468] @ (800dfe8 ) 800de12: 6cdb ldr r3, [r3, #76] @ 0x4c 800de14: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800de18: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800de1a: 4b73 ldr r3, [pc, #460] @ (800dfe8 ) 800de1c: 681b ldr r3, [r3, #0] 800de1e: f003 0304 and.w r3, r3, #4 800de22: 2b04 cmp r3, #4 800de24: d10c bne.n 800de40 800de26: 6b7b ldr r3, [r7, #52] @ 0x34 800de28: 2b00 cmp r3, #0 800de2a: d109 bne.n 800de40 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800de2c: 4b6e ldr r3, [pc, #440] @ (800dfe8 ) 800de2e: 681b ldr r3, [r3, #0] 800de30: 08db lsrs r3, r3, #3 800de32: f003 0303 and.w r3, r3, #3 800de36: 4a6d ldr r2, [pc, #436] @ (800dfec ) 800de38: fa22 f303 lsr.w r3, r2, r3 800de3c: 63fb str r3, [r7, #60] @ 0x3c 800de3e: e01f b.n 800de80 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800de40: 4b69 ldr r3, [pc, #420] @ (800dfe8 ) 800de42: 681b ldr r3, [r3, #0] 800de44: f403 7380 and.w r3, r3, #256 @ 0x100 800de48: f5b3 7f80 cmp.w r3, #256 @ 0x100 800de4c: d106 bne.n 800de5c 800de4e: 6b7b ldr r3, [r7, #52] @ 0x34 800de50: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800de54: d102 bne.n 800de5c { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800de56: 4b66 ldr r3, [pc, #408] @ (800dff0 ) 800de58: 63fb str r3, [r7, #60] @ 0x3c 800de5a: e011 b.n 800de80 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800de5c: 4b62 ldr r3, [pc, #392] @ (800dfe8 ) 800de5e: 681b ldr r3, [r3, #0] 800de60: f403 3300 and.w r3, r3, #131072 @ 0x20000 800de64: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800de68: d106 bne.n 800de78 800de6a: 6b7b ldr r3, [r7, #52] @ 0x34 800de6c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800de70: d102 bne.n 800de78 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800de72: 4b60 ldr r3, [pc, #384] @ (800dff4 ) 800de74: 63fb str r3, [r7, #60] @ 0x3c 800de76: e003 b.n 800de80 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800de78: 2300 movs r3, #0 800de7a: 63fb str r3, [r7, #60] @ 0x3c } break; 800de7c: f000 bce1 b.w 800e842 800de80: f000 bcdf b.w 800e842 } case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ { frequency = EXTERNAL_CLOCK_VALUE; 800de84: 4b5c ldr r3, [pc, #368] @ (800dff8 ) 800de86: 63fb str r3, [r7, #60] @ 0x3c break; 800de88: f000 bcdb b.w 800e842 } default : { frequency = 0; 800de8c: 2300 movs r3, #0 800de8e: 63fb str r3, [r7, #60] @ 0x3c break; 800de90: f000 bcd7 b.w 800e842 } } } #if defined(SAI3) else if (PeriphClk == RCC_PERIPHCLK_SAI23) 800de94: e9d7 2300 ldrd r2, r3, [r7] 800de98: f5a2 7100 sub.w r1, r2, #512 @ 0x200 800de9c: 430b orrs r3, r1 800de9e: f040 80ad bne.w 800dffc { saiclocksource = __HAL_RCC_GET_SAI23_SOURCE(); 800dea2: 4b51 ldr r3, [pc, #324] @ (800dfe8 ) 800dea4: 6d1b ldr r3, [r3, #80] @ 0x50 800dea6: f403 73e0 and.w r3, r3, #448 @ 0x1c0 800deaa: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800deac: 6b3b ldr r3, [r7, #48] @ 0x30 800deae: f5b3 7f80 cmp.w r3, #256 @ 0x100 800deb2: d056 beq.n 800df62 800deb4: 6b3b ldr r3, [r7, #48] @ 0x30 800deb6: f5b3 7f80 cmp.w r3, #256 @ 0x100 800deba: f200 8090 bhi.w 800dfde 800debe: 6b3b ldr r3, [r7, #48] @ 0x30 800dec0: 2bc0 cmp r3, #192 @ 0xc0 800dec2: f000 8088 beq.w 800dfd6 800dec6: 6b3b ldr r3, [r7, #48] @ 0x30 800dec8: 2bc0 cmp r3, #192 @ 0xc0 800deca: f200 8088 bhi.w 800dfde 800dece: 6b3b ldr r3, [r7, #48] @ 0x30 800ded0: 2b80 cmp r3, #128 @ 0x80 800ded2: d032 beq.n 800df3a 800ded4: 6b3b ldr r3, [r7, #48] @ 0x30 800ded6: 2b80 cmp r3, #128 @ 0x80 800ded8: f200 8081 bhi.w 800dfde 800dedc: 6b3b ldr r3, [r7, #48] @ 0x30 800dede: 2b00 cmp r3, #0 800dee0: d003 beq.n 800deea 800dee2: 6b3b ldr r3, [r7, #48] @ 0x30 800dee4: 2b40 cmp r3, #64 @ 0x40 800dee6: d014 beq.n 800df12 800dee8: e079 b.n 800dfde { case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800deea: 4b3f ldr r3, [pc, #252] @ (800dfe8 ) 800deec: 681b ldr r3, [r3, #0] 800deee: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800def2: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800def6: d108 bne.n 800df0a { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800def8: f107 0324 add.w r3, r7, #36 @ 0x24 800defc: 4618 mov r0, r3 800defe: f000 ff67 bl 800edd0 frequency = pll1_clocks.PLL1_Q_Frequency; 800df02: 6abb ldr r3, [r7, #40] @ 0x28 800df04: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800df06: f000 bc9c b.w 800e842 frequency = 0; 800df0a: 2300 movs r3, #0 800df0c: 63fb str r3, [r7, #60] @ 0x3c break; 800df0e: f000 bc98 b.w 800e842 } case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800df12: 4b35 ldr r3, [pc, #212] @ (800dfe8 ) 800df14: 681b ldr r3, [r3, #0] 800df16: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800df1a: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800df1e: d108 bne.n 800df32 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800df20: f107 0318 add.w r3, r7, #24 800df24: 4618 mov r0, r3 800df26: f000 fcab bl 800e880 frequency = pll2_clocks.PLL2_P_Frequency; 800df2a: 69bb ldr r3, [r7, #24] 800df2c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800df2e: f000 bc88 b.w 800e842 frequency = 0; 800df32: 2300 movs r3, #0 800df34: 63fb str r3, [r7, #60] @ 0x3c break; 800df36: f000 bc84 b.w 800e842 } case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800df3a: 4b2b ldr r3, [pc, #172] @ (800dfe8 ) 800df3c: 681b ldr r3, [r3, #0] 800df3e: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800df42: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800df46: d108 bne.n 800df5a { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800df48: f107 030c add.w r3, r7, #12 800df4c: 4618 mov r0, r3 800df4e: f000 fdeb bl 800eb28 frequency = pll3_clocks.PLL3_P_Frequency; 800df52: 68fb ldr r3, [r7, #12] 800df54: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800df56: f000 bc74 b.w 800e842 frequency = 0; 800df5a: 2300 movs r3, #0 800df5c: 63fb str r3, [r7, #60] @ 0x3c break; 800df5e: f000 bc70 b.w 800e842 } case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800df62: 4b21 ldr r3, [pc, #132] @ (800dfe8 ) 800df64: 6cdb ldr r3, [r3, #76] @ 0x4c 800df66: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800df6a: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800df6c: 4b1e ldr r3, [pc, #120] @ (800dfe8 ) 800df6e: 681b ldr r3, [r3, #0] 800df70: f003 0304 and.w r3, r3, #4 800df74: 2b04 cmp r3, #4 800df76: d10c bne.n 800df92 800df78: 6b7b ldr r3, [r7, #52] @ 0x34 800df7a: 2b00 cmp r3, #0 800df7c: d109 bne.n 800df92 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800df7e: 4b1a ldr r3, [pc, #104] @ (800dfe8 ) 800df80: 681b ldr r3, [r3, #0] 800df82: 08db lsrs r3, r3, #3 800df84: f003 0303 and.w r3, r3, #3 800df88: 4a18 ldr r2, [pc, #96] @ (800dfec ) 800df8a: fa22 f303 lsr.w r3, r2, r3 800df8e: 63fb str r3, [r7, #60] @ 0x3c 800df90: e01f b.n 800dfd2 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800df92: 4b15 ldr r3, [pc, #84] @ (800dfe8 ) 800df94: 681b ldr r3, [r3, #0] 800df96: f403 7380 and.w r3, r3, #256 @ 0x100 800df9a: f5b3 7f80 cmp.w r3, #256 @ 0x100 800df9e: d106 bne.n 800dfae 800dfa0: 6b7b ldr r3, [r7, #52] @ 0x34 800dfa2: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800dfa6: d102 bne.n 800dfae { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800dfa8: 4b11 ldr r3, [pc, #68] @ (800dff0 ) 800dfaa: 63fb str r3, [r7, #60] @ 0x3c 800dfac: e011 b.n 800dfd2 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800dfae: 4b0e ldr r3, [pc, #56] @ (800dfe8 ) 800dfb0: 681b ldr r3, [r3, #0] 800dfb2: f403 3300 and.w r3, r3, #131072 @ 0x20000 800dfb6: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800dfba: d106 bne.n 800dfca 800dfbc: 6b7b ldr r3, [r7, #52] @ 0x34 800dfbe: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800dfc2: d102 bne.n 800dfca { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800dfc4: 4b0b ldr r3, [pc, #44] @ (800dff4 ) 800dfc6: 63fb str r3, [r7, #60] @ 0x3c 800dfc8: e003 b.n 800dfd2 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800dfca: 2300 movs r3, #0 800dfcc: 63fb str r3, [r7, #60] @ 0x3c } break; 800dfce: f000 bc38 b.w 800e842 800dfd2: f000 bc36 b.w 800e842 } case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ { frequency = EXTERNAL_CLOCK_VALUE; 800dfd6: 4b08 ldr r3, [pc, #32] @ (800dff8 ) 800dfd8: 63fb str r3, [r7, #60] @ 0x3c break; 800dfda: f000 bc32 b.w 800e842 } default : { frequency = 0; 800dfde: 2300 movs r3, #0 800dfe0: 63fb str r3, [r7, #60] @ 0x3c break; 800dfe2: f000 bc2e b.w 800e842 800dfe6: bf00 nop 800dfe8: 58024400 .word 0x58024400 800dfec: 03d09000 .word 0x03d09000 800dff0: 003d0900 .word 0x003d0900 800dff4: 017d7840 .word 0x017d7840 800dff8: 00bb8000 .word 0x00bb8000 } } #endif #if defined(SAI4) else if (PeriphClk == RCC_PERIPHCLK_SAI4A) 800dffc: e9d7 2300 ldrd r2, r3, [r7] 800e000: f5a2 6180 sub.w r1, r2, #1024 @ 0x400 800e004: 430b orrs r3, r1 800e006: f040 809c bne.w 800e142 { saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE(); 800e00a: 4b9e ldr r3, [pc, #632] @ (800e284 ) 800e00c: 6d9b ldr r3, [r3, #88] @ 0x58 800e00e: f403 0360 and.w r3, r3, #14680064 @ 0xe00000 800e012: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800e014: 6b3b ldr r3, [r7, #48] @ 0x30 800e016: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800e01a: d054 beq.n 800e0c6 800e01c: 6b3b ldr r3, [r7, #48] @ 0x30 800e01e: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800e022: f200 808b bhi.w 800e13c 800e026: 6b3b ldr r3, [r7, #48] @ 0x30 800e028: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800e02c: f000 8083 beq.w 800e136 800e030: 6b3b ldr r3, [r7, #48] @ 0x30 800e032: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800e036: f200 8081 bhi.w 800e13c 800e03a: 6b3b ldr r3, [r7, #48] @ 0x30 800e03c: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800e040: d02f beq.n 800e0a2 800e042: 6b3b ldr r3, [r7, #48] @ 0x30 800e044: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800e048: d878 bhi.n 800e13c 800e04a: 6b3b ldr r3, [r7, #48] @ 0x30 800e04c: 2b00 cmp r3, #0 800e04e: d004 beq.n 800e05a 800e050: 6b3b ldr r3, [r7, #48] @ 0x30 800e052: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800e056: d012 beq.n 800e07e 800e058: e070 b.n 800e13c { case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e05a: 4b8a ldr r3, [pc, #552] @ (800e284 ) 800e05c: 681b ldr r3, [r3, #0] 800e05e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e062: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e066: d107 bne.n 800e078 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e068: f107 0324 add.w r3, r7, #36 @ 0x24 800e06c: 4618 mov r0, r3 800e06e: f000 feaf bl 800edd0 frequency = pll1_clocks.PLL1_Q_Frequency; 800e072: 6abb ldr r3, [r7, #40] @ 0x28 800e074: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e076: e3e4 b.n 800e842 frequency = 0; 800e078: 2300 movs r3, #0 800e07a: 63fb str r3, [r7, #60] @ 0x3c break; 800e07c: e3e1 b.n 800e842 } case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e07e: 4b81 ldr r3, [pc, #516] @ (800e284 ) 800e080: 681b ldr r3, [r3, #0] 800e082: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e086: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e08a: d107 bne.n 800e09c { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e08c: f107 0318 add.w r3, r7, #24 800e090: 4618 mov r0, r3 800e092: f000 fbf5 bl 800e880 frequency = pll2_clocks.PLL2_P_Frequency; 800e096: 69bb ldr r3, [r7, #24] 800e098: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e09a: e3d2 b.n 800e842 frequency = 0; 800e09c: 2300 movs r3, #0 800e09e: 63fb str r3, [r7, #60] @ 0x3c break; 800e0a0: e3cf b.n 800e842 } case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e0a2: 4b78 ldr r3, [pc, #480] @ (800e284 ) 800e0a4: 681b ldr r3, [r3, #0] 800e0a6: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e0aa: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e0ae: d107 bne.n 800e0c0 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e0b0: f107 030c add.w r3, r7, #12 800e0b4: 4618 mov r0, r3 800e0b6: f000 fd37 bl 800eb28 frequency = pll3_clocks.PLL3_P_Frequency; 800e0ba: 68fb ldr r3, [r7, #12] 800e0bc: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e0be: e3c0 b.n 800e842 frequency = 0; 800e0c0: 2300 movs r3, #0 800e0c2: 63fb str r3, [r7, #60] @ 0x3c break; 800e0c4: e3bd b.n 800e842 } case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e0c6: 4b6f ldr r3, [pc, #444] @ (800e284 ) 800e0c8: 6cdb ldr r3, [r3, #76] @ 0x4c 800e0ca: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e0ce: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e0d0: 4b6c ldr r3, [pc, #432] @ (800e284 ) 800e0d2: 681b ldr r3, [r3, #0] 800e0d4: f003 0304 and.w r3, r3, #4 800e0d8: 2b04 cmp r3, #4 800e0da: d10c bne.n 800e0f6 800e0dc: 6b7b ldr r3, [r7, #52] @ 0x34 800e0de: 2b00 cmp r3, #0 800e0e0: d109 bne.n 800e0f6 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e0e2: 4b68 ldr r3, [pc, #416] @ (800e284 ) 800e0e4: 681b ldr r3, [r3, #0] 800e0e6: 08db lsrs r3, r3, #3 800e0e8: f003 0303 and.w r3, r3, #3 800e0ec: 4a66 ldr r2, [pc, #408] @ (800e288 ) 800e0ee: fa22 f303 lsr.w r3, r2, r3 800e0f2: 63fb str r3, [r7, #60] @ 0x3c 800e0f4: e01e b.n 800e134 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e0f6: 4b63 ldr r3, [pc, #396] @ (800e284 ) 800e0f8: 681b ldr r3, [r3, #0] 800e0fa: f403 7380 and.w r3, r3, #256 @ 0x100 800e0fe: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e102: d106 bne.n 800e112 800e104: 6b7b ldr r3, [r7, #52] @ 0x34 800e106: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e10a: d102 bne.n 800e112 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e10c: 4b5f ldr r3, [pc, #380] @ (800e28c ) 800e10e: 63fb str r3, [r7, #60] @ 0x3c 800e110: e010 b.n 800e134 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e112: 4b5c ldr r3, [pc, #368] @ (800e284 ) 800e114: 681b ldr r3, [r3, #0] 800e116: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e11a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e11e: d106 bne.n 800e12e 800e120: 6b7b ldr r3, [r7, #52] @ 0x34 800e122: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e126: d102 bne.n 800e12e { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e128: 4b59 ldr r3, [pc, #356] @ (800e290 ) 800e12a: 63fb str r3, [r7, #60] @ 0x3c 800e12c: e002 b.n 800e134 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e12e: 2300 movs r3, #0 800e130: 63fb str r3, [r7, #60] @ 0x3c } break; 800e132: e386 b.n 800e842 800e134: e385 b.n 800e842 } case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ { frequency = EXTERNAL_CLOCK_VALUE; 800e136: 4b57 ldr r3, [pc, #348] @ (800e294 ) 800e138: 63fb str r3, [r7, #60] @ 0x3c break; 800e13a: e382 b.n 800e842 } default : { frequency = 0; 800e13c: 2300 movs r3, #0 800e13e: 63fb str r3, [r7, #60] @ 0x3c break; 800e140: e37f b.n 800e842 } } } else if (PeriphClk == RCC_PERIPHCLK_SAI4B) 800e142: e9d7 2300 ldrd r2, r3, [r7] 800e146: f5a2 6100 sub.w r1, r2, #2048 @ 0x800 800e14a: 430b orrs r3, r1 800e14c: f040 80a7 bne.w 800e29e { saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE(); 800e150: 4b4c ldr r3, [pc, #304] @ (800e284 ) 800e152: 6d9b ldr r3, [r3, #88] @ 0x58 800e154: f003 63e0 and.w r3, r3, #117440512 @ 0x7000000 800e158: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800e15a: 6b3b ldr r3, [r7, #48] @ 0x30 800e15c: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800e160: d055 beq.n 800e20e 800e162: 6b3b ldr r3, [r7, #48] @ 0x30 800e164: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800e168: f200 8096 bhi.w 800e298 800e16c: 6b3b ldr r3, [r7, #48] @ 0x30 800e16e: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800e172: f000 8084 beq.w 800e27e 800e176: 6b3b ldr r3, [r7, #48] @ 0x30 800e178: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800e17c: f200 808c bhi.w 800e298 800e180: 6b3b ldr r3, [r7, #48] @ 0x30 800e182: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e186: d030 beq.n 800e1ea 800e188: 6b3b ldr r3, [r7, #48] @ 0x30 800e18a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e18e: f200 8083 bhi.w 800e298 800e192: 6b3b ldr r3, [r7, #48] @ 0x30 800e194: 2b00 cmp r3, #0 800e196: d004 beq.n 800e1a2 800e198: 6b3b ldr r3, [r7, #48] @ 0x30 800e19a: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800e19e: d012 beq.n 800e1c6 800e1a0: e07a b.n 800e298 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e1a2: 4b38 ldr r3, [pc, #224] @ (800e284 ) 800e1a4: 681b ldr r3, [r3, #0] 800e1a6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e1aa: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e1ae: d107 bne.n 800e1c0 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e1b0: f107 0324 add.w r3, r7, #36 @ 0x24 800e1b4: 4618 mov r0, r3 800e1b6: f000 fe0b bl 800edd0 frequency = pll1_clocks.PLL1_Q_Frequency; 800e1ba: 6abb ldr r3, [r7, #40] @ 0x28 800e1bc: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e1be: e340 b.n 800e842 frequency = 0; 800e1c0: 2300 movs r3, #0 800e1c2: 63fb str r3, [r7, #60] @ 0x3c break; 800e1c4: e33d b.n 800e842 } case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e1c6: 4b2f ldr r3, [pc, #188] @ (800e284 ) 800e1c8: 681b ldr r3, [r3, #0] 800e1ca: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e1ce: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e1d2: d107 bne.n 800e1e4 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e1d4: f107 0318 add.w r3, r7, #24 800e1d8: 4618 mov r0, r3 800e1da: f000 fb51 bl 800e880 frequency = pll2_clocks.PLL2_P_Frequency; 800e1de: 69bb ldr r3, [r7, #24] 800e1e0: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e1e2: e32e b.n 800e842 frequency = 0; 800e1e4: 2300 movs r3, #0 800e1e6: 63fb str r3, [r7, #60] @ 0x3c break; 800e1e8: e32b b.n 800e842 } case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e1ea: 4b26 ldr r3, [pc, #152] @ (800e284 ) 800e1ec: 681b ldr r3, [r3, #0] 800e1ee: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e1f2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e1f6: d107 bne.n 800e208 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e1f8: f107 030c add.w r3, r7, #12 800e1fc: 4618 mov r0, r3 800e1fe: f000 fc93 bl 800eb28 frequency = pll3_clocks.PLL3_P_Frequency; 800e202: 68fb ldr r3, [r7, #12] 800e204: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e206: e31c b.n 800e842 frequency = 0; 800e208: 2300 movs r3, #0 800e20a: 63fb str r3, [r7, #60] @ 0x3c break; 800e20c: e319 b.n 800e842 } case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e20e: 4b1d ldr r3, [pc, #116] @ (800e284 ) 800e210: 6cdb ldr r3, [r3, #76] @ 0x4c 800e212: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e216: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e218: 4b1a ldr r3, [pc, #104] @ (800e284 ) 800e21a: 681b ldr r3, [r3, #0] 800e21c: f003 0304 and.w r3, r3, #4 800e220: 2b04 cmp r3, #4 800e222: d10c bne.n 800e23e 800e224: 6b7b ldr r3, [r7, #52] @ 0x34 800e226: 2b00 cmp r3, #0 800e228: d109 bne.n 800e23e { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e22a: 4b16 ldr r3, [pc, #88] @ (800e284 ) 800e22c: 681b ldr r3, [r3, #0] 800e22e: 08db lsrs r3, r3, #3 800e230: f003 0303 and.w r3, r3, #3 800e234: 4a14 ldr r2, [pc, #80] @ (800e288 ) 800e236: fa22 f303 lsr.w r3, r2, r3 800e23a: 63fb str r3, [r7, #60] @ 0x3c 800e23c: e01e b.n 800e27c } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e23e: 4b11 ldr r3, [pc, #68] @ (800e284 ) 800e240: 681b ldr r3, [r3, #0] 800e242: f403 7380 and.w r3, r3, #256 @ 0x100 800e246: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e24a: d106 bne.n 800e25a 800e24c: 6b7b ldr r3, [r7, #52] @ 0x34 800e24e: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e252: d102 bne.n 800e25a { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e254: 4b0d ldr r3, [pc, #52] @ (800e28c ) 800e256: 63fb str r3, [r7, #60] @ 0x3c 800e258: e010 b.n 800e27c } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e25a: 4b0a ldr r3, [pc, #40] @ (800e284 ) 800e25c: 681b ldr r3, [r3, #0] 800e25e: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e262: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e266: d106 bne.n 800e276 800e268: 6b7b ldr r3, [r7, #52] @ 0x34 800e26a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e26e: d102 bne.n 800e276 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e270: 4b07 ldr r3, [pc, #28] @ (800e290 ) 800e272: 63fb str r3, [r7, #60] @ 0x3c 800e274: e002 b.n 800e27c } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e276: 2300 movs r3, #0 800e278: 63fb str r3, [r7, #60] @ 0x3c } break; 800e27a: e2e2 b.n 800e842 800e27c: e2e1 b.n 800e842 } case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ { frequency = EXTERNAL_CLOCK_VALUE; 800e27e: 4b05 ldr r3, [pc, #20] @ (800e294 ) 800e280: 63fb str r3, [r7, #60] @ 0x3c break; 800e282: e2de b.n 800e842 800e284: 58024400 .word 0x58024400 800e288: 03d09000 .word 0x03d09000 800e28c: 003d0900 .word 0x003d0900 800e290: 017d7840 .word 0x017d7840 800e294: 00bb8000 .word 0x00bb8000 } default : { frequency = 0; 800e298: 2300 movs r3, #0 800e29a: 63fb str r3, [r7, #60] @ 0x3c break; 800e29c: e2d1 b.n 800e842 } } } #endif /*SAI4*/ else if (PeriphClk == RCC_PERIPHCLK_SPI123) 800e29e: e9d7 2300 ldrd r2, r3, [r7] 800e2a2: f5a2 5180 sub.w r1, r2, #4096 @ 0x1000 800e2a6: 430b orrs r3, r1 800e2a8: f040 809c bne.w 800e3e4 { /* Get SPI1/2/3 clock source */ srcclk = __HAL_RCC_GET_SPI123_SOURCE(); 800e2ac: 4b93 ldr r3, [pc, #588] @ (800e4fc ) 800e2ae: 6d1b ldr r3, [r3, #80] @ 0x50 800e2b0: f403 43e0 and.w r3, r3, #28672 @ 0x7000 800e2b4: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e2b6: 6bbb ldr r3, [r7, #56] @ 0x38 800e2b8: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800e2bc: d054 beq.n 800e368 800e2be: 6bbb ldr r3, [r7, #56] @ 0x38 800e2c0: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800e2c4: f200 808b bhi.w 800e3de 800e2c8: 6bbb ldr r3, [r7, #56] @ 0x38 800e2ca: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800e2ce: f000 8083 beq.w 800e3d8 800e2d2: 6bbb ldr r3, [r7, #56] @ 0x38 800e2d4: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800e2d8: f200 8081 bhi.w 800e3de 800e2dc: 6bbb ldr r3, [r7, #56] @ 0x38 800e2de: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800e2e2: d02f beq.n 800e344 800e2e4: 6bbb ldr r3, [r7, #56] @ 0x38 800e2e6: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800e2ea: d878 bhi.n 800e3de 800e2ec: 6bbb ldr r3, [r7, #56] @ 0x38 800e2ee: 2b00 cmp r3, #0 800e2f0: d004 beq.n 800e2fc 800e2f2: 6bbb ldr r3, [r7, #56] @ 0x38 800e2f4: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800e2f8: d012 beq.n 800e320 800e2fa: e070 b.n 800e3de { case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e2fc: 4b7f ldr r3, [pc, #508] @ (800e4fc ) 800e2fe: 681b ldr r3, [r3, #0] 800e300: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e304: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e308: d107 bne.n 800e31a { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e30a: f107 0324 add.w r3, r7, #36 @ 0x24 800e30e: 4618 mov r0, r3 800e310: f000 fd5e bl 800edd0 frequency = pll1_clocks.PLL1_Q_Frequency; 800e314: 6abb ldr r3, [r7, #40] @ 0x28 800e316: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e318: e293 b.n 800e842 frequency = 0; 800e31a: 2300 movs r3, #0 800e31c: 63fb str r3, [r7, #60] @ 0x3c break; 800e31e: e290 b.n 800e842 } case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e320: 4b76 ldr r3, [pc, #472] @ (800e4fc ) 800e322: 681b ldr r3, [r3, #0] 800e324: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e328: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e32c: d107 bne.n 800e33e { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e32e: f107 0318 add.w r3, r7, #24 800e332: 4618 mov r0, r3 800e334: f000 faa4 bl 800e880 frequency = pll2_clocks.PLL2_P_Frequency; 800e338: 69bb ldr r3, [r7, #24] 800e33a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e33c: e281 b.n 800e842 frequency = 0; 800e33e: 2300 movs r3, #0 800e340: 63fb str r3, [r7, #60] @ 0x3c break; 800e342: e27e b.n 800e842 } case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e344: 4b6d ldr r3, [pc, #436] @ (800e4fc ) 800e346: 681b ldr r3, [r3, #0] 800e348: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e34c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e350: d107 bne.n 800e362 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e352: f107 030c add.w r3, r7, #12 800e356: 4618 mov r0, r3 800e358: f000 fbe6 bl 800eb28 frequency = pll3_clocks.PLL3_P_Frequency; 800e35c: 68fb ldr r3, [r7, #12] 800e35e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e360: e26f b.n 800e842 frequency = 0; 800e362: 2300 movs r3, #0 800e364: 63fb str r3, [r7, #60] @ 0x3c break; 800e366: e26c b.n 800e842 } case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e368: 4b64 ldr r3, [pc, #400] @ (800e4fc ) 800e36a: 6cdb ldr r3, [r3, #76] @ 0x4c 800e36c: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e370: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e372: 4b62 ldr r3, [pc, #392] @ (800e4fc ) 800e374: 681b ldr r3, [r3, #0] 800e376: f003 0304 and.w r3, r3, #4 800e37a: 2b04 cmp r3, #4 800e37c: d10c bne.n 800e398 800e37e: 6b7b ldr r3, [r7, #52] @ 0x34 800e380: 2b00 cmp r3, #0 800e382: d109 bne.n 800e398 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e384: 4b5d ldr r3, [pc, #372] @ (800e4fc ) 800e386: 681b ldr r3, [r3, #0] 800e388: 08db lsrs r3, r3, #3 800e38a: f003 0303 and.w r3, r3, #3 800e38e: 4a5c ldr r2, [pc, #368] @ (800e500 ) 800e390: fa22 f303 lsr.w r3, r2, r3 800e394: 63fb str r3, [r7, #60] @ 0x3c 800e396: e01e b.n 800e3d6 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e398: 4b58 ldr r3, [pc, #352] @ (800e4fc ) 800e39a: 681b ldr r3, [r3, #0] 800e39c: f403 7380 and.w r3, r3, #256 @ 0x100 800e3a0: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e3a4: d106 bne.n 800e3b4 800e3a6: 6b7b ldr r3, [r7, #52] @ 0x34 800e3a8: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e3ac: d102 bne.n 800e3b4 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e3ae: 4b55 ldr r3, [pc, #340] @ (800e504 ) 800e3b0: 63fb str r3, [r7, #60] @ 0x3c 800e3b2: e010 b.n 800e3d6 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e3b4: 4b51 ldr r3, [pc, #324] @ (800e4fc ) 800e3b6: 681b ldr r3, [r3, #0] 800e3b8: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e3bc: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e3c0: d106 bne.n 800e3d0 800e3c2: 6b7b ldr r3, [r7, #52] @ 0x34 800e3c4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e3c8: d102 bne.n 800e3d0 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e3ca: 4b4f ldr r3, [pc, #316] @ (800e508 ) 800e3cc: 63fb str r3, [r7, #60] @ 0x3c 800e3ce: e002 b.n 800e3d6 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e3d0: 2300 movs r3, #0 800e3d2: 63fb str r3, [r7, #60] @ 0x3c } break; 800e3d4: e235 b.n 800e842 800e3d6: e234 b.n 800e842 } case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ { frequency = EXTERNAL_CLOCK_VALUE; 800e3d8: 4b4c ldr r3, [pc, #304] @ (800e50c ) 800e3da: 63fb str r3, [r7, #60] @ 0x3c break; 800e3dc: e231 b.n 800e842 } default : { frequency = 0; 800e3de: 2300 movs r3, #0 800e3e0: 63fb str r3, [r7, #60] @ 0x3c break; 800e3e2: e22e b.n 800e842 } } } else if (PeriphClk == RCC_PERIPHCLK_SPI45) 800e3e4: e9d7 2300 ldrd r2, r3, [r7] 800e3e8: f5a2 5100 sub.w r1, r2, #8192 @ 0x2000 800e3ec: 430b orrs r3, r1 800e3ee: f040 808f bne.w 800e510 { /* Get SPI45 clock source */ srcclk = __HAL_RCC_GET_SPI45_SOURCE(); 800e3f2: 4b42 ldr r3, [pc, #264] @ (800e4fc ) 800e3f4: 6d1b ldr r3, [r3, #80] @ 0x50 800e3f6: f403 23e0 and.w r3, r3, #458752 @ 0x70000 800e3fa: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e3fc: 6bbb ldr r3, [r7, #56] @ 0x38 800e3fe: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800e402: d06b beq.n 800e4dc 800e404: 6bbb ldr r3, [r7, #56] @ 0x38 800e406: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800e40a: d874 bhi.n 800e4f6 800e40c: 6bbb ldr r3, [r7, #56] @ 0x38 800e40e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800e412: d056 beq.n 800e4c2 800e414: 6bbb ldr r3, [r7, #56] @ 0x38 800e416: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800e41a: d86c bhi.n 800e4f6 800e41c: 6bbb ldr r3, [r7, #56] @ 0x38 800e41e: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800e422: d03b beq.n 800e49c 800e424: 6bbb ldr r3, [r7, #56] @ 0x38 800e426: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800e42a: d864 bhi.n 800e4f6 800e42c: 6bbb ldr r3, [r7, #56] @ 0x38 800e42e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e432: d021 beq.n 800e478 800e434: 6bbb ldr r3, [r7, #56] @ 0x38 800e436: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e43a: d85c bhi.n 800e4f6 800e43c: 6bbb ldr r3, [r7, #56] @ 0x38 800e43e: 2b00 cmp r3, #0 800e440: d004 beq.n 800e44c 800e442: 6bbb ldr r3, [r7, #56] @ 0x38 800e444: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e448: d004 beq.n 800e454 800e44a: e054 b.n 800e4f6 { case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */ { frequency = HAL_RCC_GetPCLK1Freq(); 800e44c: f7fe fa26 bl 800c89c 800e450: 63f8 str r0, [r7, #60] @ 0x3c break; 800e452: e1f6 b.n 800e842 } case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e454: 4b29 ldr r3, [pc, #164] @ (800e4fc ) 800e456: 681b ldr r3, [r3, #0] 800e458: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e45c: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e460: d107 bne.n 800e472 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e462: f107 0318 add.w r3, r7, #24 800e466: 4618 mov r0, r3 800e468: f000 fa0a bl 800e880 frequency = pll2_clocks.PLL2_Q_Frequency; 800e46c: 69fb ldr r3, [r7, #28] 800e46e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e470: e1e7 b.n 800e842 frequency = 0; 800e472: 2300 movs r3, #0 800e474: 63fb str r3, [r7, #60] @ 0x3c break; 800e476: e1e4 b.n 800e842 } case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e478: 4b20 ldr r3, [pc, #128] @ (800e4fc ) 800e47a: 681b ldr r3, [r3, #0] 800e47c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e480: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e484: d107 bne.n 800e496 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e486: f107 030c add.w r3, r7, #12 800e48a: 4618 mov r0, r3 800e48c: f000 fb4c bl 800eb28 frequency = pll3_clocks.PLL3_Q_Frequency; 800e490: 693b ldr r3, [r7, #16] 800e492: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e494: e1d5 b.n 800e842 frequency = 0; 800e496: 2300 movs r3, #0 800e498: 63fb str r3, [r7, #60] @ 0x3c break; 800e49a: e1d2 b.n 800e842 } case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800e49c: 4b17 ldr r3, [pc, #92] @ (800e4fc ) 800e49e: 681b ldr r3, [r3, #0] 800e4a0: f003 0304 and.w r3, r3, #4 800e4a4: 2b04 cmp r3, #4 800e4a6: d109 bne.n 800e4bc { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e4a8: 4b14 ldr r3, [pc, #80] @ (800e4fc ) 800e4aa: 681b ldr r3, [r3, #0] 800e4ac: 08db lsrs r3, r3, #3 800e4ae: f003 0303 and.w r3, r3, #3 800e4b2: 4a13 ldr r2, [pc, #76] @ (800e500 ) 800e4b4: fa22 f303 lsr.w r3, r2, r3 800e4b8: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e4ba: e1c2 b.n 800e842 frequency = 0; 800e4bc: 2300 movs r3, #0 800e4be: 63fb str r3, [r7, #60] @ 0x3c break; 800e4c0: e1bf b.n 800e842 } case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 800e4c2: 4b0e ldr r3, [pc, #56] @ (800e4fc ) 800e4c4: 681b ldr r3, [r3, #0] 800e4c6: f403 7380 and.w r3, r3, #256 @ 0x100 800e4ca: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e4ce: d102 bne.n 800e4d6 { frequency = CSI_VALUE; 800e4d0: 4b0c ldr r3, [pc, #48] @ (800e504 ) 800e4d2: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e4d4: e1b5 b.n 800e842 frequency = 0; 800e4d6: 2300 movs r3, #0 800e4d8: 63fb str r3, [r7, #60] @ 0x3c break; 800e4da: e1b2 b.n 800e842 } case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e4dc: 4b07 ldr r3, [pc, #28] @ (800e4fc ) 800e4de: 681b ldr r3, [r3, #0] 800e4e0: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e4e4: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e4e8: d102 bne.n 800e4f0 { frequency = HSE_VALUE; 800e4ea: 4b07 ldr r3, [pc, #28] @ (800e508 ) 800e4ec: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e4ee: e1a8 b.n 800e842 frequency = 0; 800e4f0: 2300 movs r3, #0 800e4f2: 63fb str r3, [r7, #60] @ 0x3c break; 800e4f4: e1a5 b.n 800e842 } default : { frequency = 0; 800e4f6: 2300 movs r3, #0 800e4f8: 63fb str r3, [r7, #60] @ 0x3c break; 800e4fa: e1a2 b.n 800e842 800e4fc: 58024400 .word 0x58024400 800e500: 03d09000 .word 0x03d09000 800e504: 003d0900 .word 0x003d0900 800e508: 017d7840 .word 0x017d7840 800e50c: 00bb8000 .word 0x00bb8000 } } } else if (PeriphClk == RCC_PERIPHCLK_ADC) 800e510: e9d7 2300 ldrd r2, r3, [r7] 800e514: f5a2 2100 sub.w r1, r2, #524288 @ 0x80000 800e518: 430b orrs r3, r1 800e51a: d173 bne.n 800e604 { /* Get ADC clock source */ srcclk = __HAL_RCC_GET_ADC_SOURCE(); 800e51c: 4b9c ldr r3, [pc, #624] @ (800e790 ) 800e51e: 6d9b ldr r3, [r3, #88] @ 0x58 800e520: f403 3340 and.w r3, r3, #196608 @ 0x30000 800e524: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e526: 6bbb ldr r3, [r7, #56] @ 0x38 800e528: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e52c: d02f beq.n 800e58e 800e52e: 6bbb ldr r3, [r7, #56] @ 0x38 800e530: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e534: d863 bhi.n 800e5fe 800e536: 6bbb ldr r3, [r7, #56] @ 0x38 800e538: 2b00 cmp r3, #0 800e53a: d004 beq.n 800e546 800e53c: 6bbb ldr r3, [r7, #56] @ 0x38 800e53e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e542: d012 beq.n 800e56a 800e544: e05b b.n 800e5fe { case RCC_ADCCLKSOURCE_PLL2: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e546: 4b92 ldr r3, [pc, #584] @ (800e790 ) 800e548: 681b ldr r3, [r3, #0] 800e54a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e54e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e552: d107 bne.n 800e564 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e554: f107 0318 add.w r3, r7, #24 800e558: 4618 mov r0, r3 800e55a: f000 f991 bl 800e880 frequency = pll2_clocks.PLL2_P_Frequency; 800e55e: 69bb ldr r3, [r7, #24] 800e560: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e562: e16e b.n 800e842 frequency = 0; 800e564: 2300 movs r3, #0 800e566: 63fb str r3, [r7, #60] @ 0x3c break; 800e568: e16b b.n 800e842 } case RCC_ADCCLKSOURCE_PLL3: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e56a: 4b89 ldr r3, [pc, #548] @ (800e790 ) 800e56c: 681b ldr r3, [r3, #0] 800e56e: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e572: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e576: d107 bne.n 800e588 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e578: f107 030c add.w r3, r7, #12 800e57c: 4618 mov r0, r3 800e57e: f000 fad3 bl 800eb28 frequency = pll3_clocks.PLL3_R_Frequency; 800e582: 697b ldr r3, [r7, #20] 800e584: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e586: e15c b.n 800e842 frequency = 0; 800e588: 2300 movs r3, #0 800e58a: 63fb str r3, [r7, #60] @ 0x3c break; 800e58c: e159 b.n 800e842 } case RCC_ADCCLKSOURCE_CLKP: { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e58e: 4b80 ldr r3, [pc, #512] @ (800e790 ) 800e590: 6cdb ldr r3, [r3, #76] @ 0x4c 800e592: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e596: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e598: 4b7d ldr r3, [pc, #500] @ (800e790 ) 800e59a: 681b ldr r3, [r3, #0] 800e59c: f003 0304 and.w r3, r3, #4 800e5a0: 2b04 cmp r3, #4 800e5a2: d10c bne.n 800e5be 800e5a4: 6b7b ldr r3, [r7, #52] @ 0x34 800e5a6: 2b00 cmp r3, #0 800e5a8: d109 bne.n 800e5be { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e5aa: 4b79 ldr r3, [pc, #484] @ (800e790 ) 800e5ac: 681b ldr r3, [r3, #0] 800e5ae: 08db lsrs r3, r3, #3 800e5b0: f003 0303 and.w r3, r3, #3 800e5b4: 4a77 ldr r2, [pc, #476] @ (800e794 ) 800e5b6: fa22 f303 lsr.w r3, r2, r3 800e5ba: 63fb str r3, [r7, #60] @ 0x3c 800e5bc: e01e b.n 800e5fc } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e5be: 4b74 ldr r3, [pc, #464] @ (800e790 ) 800e5c0: 681b ldr r3, [r3, #0] 800e5c2: f403 7380 and.w r3, r3, #256 @ 0x100 800e5c6: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e5ca: d106 bne.n 800e5da 800e5cc: 6b7b ldr r3, [r7, #52] @ 0x34 800e5ce: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e5d2: d102 bne.n 800e5da { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e5d4: 4b70 ldr r3, [pc, #448] @ (800e798 ) 800e5d6: 63fb str r3, [r7, #60] @ 0x3c 800e5d8: e010 b.n 800e5fc } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e5da: 4b6d ldr r3, [pc, #436] @ (800e790 ) 800e5dc: 681b ldr r3, [r3, #0] 800e5de: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e5e2: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e5e6: d106 bne.n 800e5f6 800e5e8: 6b7b ldr r3, [r7, #52] @ 0x34 800e5ea: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e5ee: d102 bne.n 800e5f6 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e5f0: 4b6a ldr r3, [pc, #424] @ (800e79c ) 800e5f2: 63fb str r3, [r7, #60] @ 0x3c 800e5f4: e002 b.n 800e5fc } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e5f6: 2300 movs r3, #0 800e5f8: 63fb str r3, [r7, #60] @ 0x3c } break; 800e5fa: e122 b.n 800e842 800e5fc: e121 b.n 800e842 } default : { frequency = 0; 800e5fe: 2300 movs r3, #0 800e600: 63fb str r3, [r7, #60] @ 0x3c break; 800e602: e11e b.n 800e842 } } } else if (PeriphClk == RCC_PERIPHCLK_SDMMC) 800e604: e9d7 2300 ldrd r2, r3, [r7] 800e608: f5a2 3180 sub.w r1, r2, #65536 @ 0x10000 800e60c: 430b orrs r3, r1 800e60e: d133 bne.n 800e678 { /* Get SDMMC clock source */ srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); 800e610: 4b5f ldr r3, [pc, #380] @ (800e790 ) 800e612: 6cdb ldr r3, [r3, #76] @ 0x4c 800e614: f403 3380 and.w r3, r3, #65536 @ 0x10000 800e618: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e61a: 6bbb ldr r3, [r7, #56] @ 0x38 800e61c: 2b00 cmp r3, #0 800e61e: d004 beq.n 800e62a 800e620: 6bbb ldr r3, [r7, #56] @ 0x38 800e622: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e626: d012 beq.n 800e64e 800e628: e023 b.n 800e672 { case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e62a: 4b59 ldr r3, [pc, #356] @ (800e790 ) 800e62c: 681b ldr r3, [r3, #0] 800e62e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e632: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e636: d107 bne.n 800e648 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e638: f107 0324 add.w r3, r7, #36 @ 0x24 800e63c: 4618 mov r0, r3 800e63e: f000 fbc7 bl 800edd0 frequency = pll1_clocks.PLL1_Q_Frequency; 800e642: 6abb ldr r3, [r7, #40] @ 0x28 800e644: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e646: e0fc b.n 800e842 frequency = 0; 800e648: 2300 movs r3, #0 800e64a: 63fb str r3, [r7, #60] @ 0x3c break; 800e64c: e0f9 b.n 800e842 } case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e64e: 4b50 ldr r3, [pc, #320] @ (800e790 ) 800e650: 681b ldr r3, [r3, #0] 800e652: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e656: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e65a: d107 bne.n 800e66c { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e65c: f107 0318 add.w r3, r7, #24 800e660: 4618 mov r0, r3 800e662: f000 f90d bl 800e880 frequency = pll2_clocks.PLL2_R_Frequency; 800e666: 6a3b ldr r3, [r7, #32] 800e668: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e66a: e0ea b.n 800e842 frequency = 0; 800e66c: 2300 movs r3, #0 800e66e: 63fb str r3, [r7, #60] @ 0x3c break; 800e670: e0e7 b.n 800e842 } default : { frequency = 0; 800e672: 2300 movs r3, #0 800e674: 63fb str r3, [r7, #60] @ 0x3c break; 800e676: e0e4 b.n 800e842 } } } else if (PeriphClk == RCC_PERIPHCLK_SPI6) 800e678: e9d7 2300 ldrd r2, r3, [r7] 800e67c: f5a2 4180 sub.w r1, r2, #16384 @ 0x4000 800e680: 430b orrs r3, r1 800e682: f040 808d bne.w 800e7a0 { /* Get SPI6 clock source */ srcclk = __HAL_RCC_GET_SPI6_SOURCE(); 800e686: 4b42 ldr r3, [pc, #264] @ (800e790 ) 800e688: 6d9b ldr r3, [r3, #88] @ 0x58 800e68a: f003 43e0 and.w r3, r3, #1879048192 @ 0x70000000 800e68e: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e690: 6bbb ldr r3, [r7, #56] @ 0x38 800e692: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800e696: d06b beq.n 800e770 800e698: 6bbb ldr r3, [r7, #56] @ 0x38 800e69a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800e69e: d874 bhi.n 800e78a 800e6a0: 6bbb ldr r3, [r7, #56] @ 0x38 800e6a2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800e6a6: d056 beq.n 800e756 800e6a8: 6bbb ldr r3, [r7, #56] @ 0x38 800e6aa: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800e6ae: d86c bhi.n 800e78a 800e6b0: 6bbb ldr r3, [r7, #56] @ 0x38 800e6b2: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800e6b6: d03b beq.n 800e730 800e6b8: 6bbb ldr r3, [r7, #56] @ 0x38 800e6ba: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800e6be: d864 bhi.n 800e78a 800e6c0: 6bbb ldr r3, [r7, #56] @ 0x38 800e6c2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e6c6: d021 beq.n 800e70c 800e6c8: 6bbb ldr r3, [r7, #56] @ 0x38 800e6ca: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e6ce: d85c bhi.n 800e78a 800e6d0: 6bbb ldr r3, [r7, #56] @ 0x38 800e6d2: 2b00 cmp r3, #0 800e6d4: d004 beq.n 800e6e0 800e6d6: 6bbb ldr r3, [r7, #56] @ 0x38 800e6d8: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e6dc: d004 beq.n 800e6e8 800e6de: e054 b.n 800e78a { case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ { frequency = HAL_RCCEx_GetD3PCLK1Freq(); 800e6e0: f000 f8b8 bl 800e854 800e6e4: 63f8 str r0, [r7, #60] @ 0x3c break; 800e6e6: e0ac b.n 800e842 } case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e6e8: 4b29 ldr r3, [pc, #164] @ (800e790 ) 800e6ea: 681b ldr r3, [r3, #0] 800e6ec: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e6f0: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e6f4: d107 bne.n 800e706 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e6f6: f107 0318 add.w r3, r7, #24 800e6fa: 4618 mov r0, r3 800e6fc: f000 f8c0 bl 800e880 frequency = pll2_clocks.PLL2_Q_Frequency; 800e700: 69fb ldr r3, [r7, #28] 800e702: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e704: e09d b.n 800e842 frequency = 0; 800e706: 2300 movs r3, #0 800e708: 63fb str r3, [r7, #60] @ 0x3c break; 800e70a: e09a b.n 800e842 } case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e70c: 4b20 ldr r3, [pc, #128] @ (800e790 ) 800e70e: 681b ldr r3, [r3, #0] 800e710: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e714: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e718: d107 bne.n 800e72a { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e71a: f107 030c add.w r3, r7, #12 800e71e: 4618 mov r0, r3 800e720: f000 fa02 bl 800eb28 frequency = pll3_clocks.PLL3_Q_Frequency; 800e724: 693b ldr r3, [r7, #16] 800e726: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e728: e08b b.n 800e842 frequency = 0; 800e72a: 2300 movs r3, #0 800e72c: 63fb str r3, [r7, #60] @ 0x3c break; 800e72e: e088 b.n 800e842 } case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800e730: 4b17 ldr r3, [pc, #92] @ (800e790 ) 800e732: 681b ldr r3, [r3, #0] 800e734: f003 0304 and.w r3, r3, #4 800e738: 2b04 cmp r3, #4 800e73a: d109 bne.n 800e750 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e73c: 4b14 ldr r3, [pc, #80] @ (800e790 ) 800e73e: 681b ldr r3, [r3, #0] 800e740: 08db lsrs r3, r3, #3 800e742: f003 0303 and.w r3, r3, #3 800e746: 4a13 ldr r2, [pc, #76] @ (800e794 ) 800e748: fa22 f303 lsr.w r3, r2, r3 800e74c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e74e: e078 b.n 800e842 frequency = 0; 800e750: 2300 movs r3, #0 800e752: 63fb str r3, [r7, #60] @ 0x3c break; 800e754: e075 b.n 800e842 } case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 800e756: 4b0e ldr r3, [pc, #56] @ (800e790 ) 800e758: 681b ldr r3, [r3, #0] 800e75a: f403 7380 and.w r3, r3, #256 @ 0x100 800e75e: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e762: d102 bne.n 800e76a { frequency = CSI_VALUE; 800e764: 4b0c ldr r3, [pc, #48] @ (800e798 ) 800e766: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e768: e06b b.n 800e842 frequency = 0; 800e76a: 2300 movs r3, #0 800e76c: 63fb str r3, [r7, #60] @ 0x3c break; 800e76e: e068 b.n 800e842 } case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e770: 4b07 ldr r3, [pc, #28] @ (800e790 ) 800e772: 681b ldr r3, [r3, #0] 800e774: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e778: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e77c: d102 bne.n 800e784 { frequency = HSE_VALUE; 800e77e: 4b07 ldr r3, [pc, #28] @ (800e79c ) 800e780: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e782: e05e b.n 800e842 frequency = 0; 800e784: 2300 movs r3, #0 800e786: 63fb str r3, [r7, #60] @ 0x3c break; 800e788: e05b b.n 800e842 break; } #endif /* RCC_SPI6CLKSOURCE_PIN */ default : { frequency = 0; 800e78a: 2300 movs r3, #0 800e78c: 63fb str r3, [r7, #60] @ 0x3c break; 800e78e: e058 b.n 800e842 800e790: 58024400 .word 0x58024400 800e794: 03d09000 .word 0x03d09000 800e798: 003d0900 .word 0x003d0900 800e79c: 017d7840 .word 0x017d7840 } } } else if (PeriphClk == RCC_PERIPHCLK_FDCAN) 800e7a0: e9d7 2300 ldrd r2, r3, [r7] 800e7a4: f5a2 4100 sub.w r1, r2, #32768 @ 0x8000 800e7a8: 430b orrs r3, r1 800e7aa: d148 bne.n 800e83e { /* Get FDCAN clock source */ srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); 800e7ac: 4b27 ldr r3, [pc, #156] @ (800e84c ) 800e7ae: 6d1b ldr r3, [r3, #80] @ 0x50 800e7b0: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e7b4: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e7b6: 6bbb ldr r3, [r7, #56] @ 0x38 800e7b8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e7bc: d02a beq.n 800e814 800e7be: 6bbb ldr r3, [r7, #56] @ 0x38 800e7c0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e7c4: d838 bhi.n 800e838 800e7c6: 6bbb ldr r3, [r7, #56] @ 0x38 800e7c8: 2b00 cmp r3, #0 800e7ca: d004 beq.n 800e7d6 800e7cc: 6bbb ldr r3, [r7, #56] @ 0x38 800e7ce: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e7d2: d00d beq.n 800e7f0 800e7d4: e030 b.n 800e838 { case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e7d6: 4b1d ldr r3, [pc, #116] @ (800e84c ) 800e7d8: 681b ldr r3, [r3, #0] 800e7da: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e7de: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e7e2: d102 bne.n 800e7ea { frequency = HSE_VALUE; 800e7e4: 4b1a ldr r3, [pc, #104] @ (800e850 ) 800e7e6: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e7e8: e02b b.n 800e842 frequency = 0; 800e7ea: 2300 movs r3, #0 800e7ec: 63fb str r3, [r7, #60] @ 0x3c break; 800e7ee: e028 b.n 800e842 } case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e7f0: 4b16 ldr r3, [pc, #88] @ (800e84c ) 800e7f2: 681b ldr r3, [r3, #0] 800e7f4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e7f8: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e7fc: d107 bne.n 800e80e { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e7fe: f107 0324 add.w r3, r7, #36 @ 0x24 800e802: 4618 mov r0, r3 800e804: f000 fae4 bl 800edd0 frequency = pll1_clocks.PLL1_Q_Frequency; 800e808: 6abb ldr r3, [r7, #40] @ 0x28 800e80a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e80c: e019 b.n 800e842 frequency = 0; 800e80e: 2300 movs r3, #0 800e810: 63fb str r3, [r7, #60] @ 0x3c break; 800e812: e016 b.n 800e842 } case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e814: 4b0d ldr r3, [pc, #52] @ (800e84c ) 800e816: 681b ldr r3, [r3, #0] 800e818: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e81c: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e820: d107 bne.n 800e832 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e822: f107 0318 add.w r3, r7, #24 800e826: 4618 mov r0, r3 800e828: f000 f82a bl 800e880 frequency = pll2_clocks.PLL2_Q_Frequency; 800e82c: 69fb ldr r3, [r7, #28] 800e82e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e830: e007 b.n 800e842 frequency = 0; 800e832: 2300 movs r3, #0 800e834: 63fb str r3, [r7, #60] @ 0x3c break; 800e836: e004 b.n 800e842 } default : { frequency = 0; 800e838: 2300 movs r3, #0 800e83a: 63fb str r3, [r7, #60] @ 0x3c break; 800e83c: e001 b.n 800e842 } } } else { frequency = 0; 800e83e: 2300 movs r3, #0 800e840: 63fb str r3, [r7, #60] @ 0x3c } return frequency; 800e842: 6bfb ldr r3, [r7, #60] @ 0x3c } 800e844: 4618 mov r0, r3 800e846: 3740 adds r7, #64 @ 0x40 800e848: 46bd mov sp, r7 800e84a: bd80 pop {r7, pc} 800e84c: 58024400 .word 0x58024400 800e850: 017d7840 .word 0x017d7840 0800e854 : * @note Each time D3PCLK1 changes, this function must be called to update the * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval D3PCLK1 frequency */ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) { 800e854: b580 push {r7, lr} 800e856: af00 add r7, sp, #0 #if defined(RCC_D3CFGR_D3PPRE) /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); 800e858: f7fd fff0 bl 800c83c 800e85c: 4602 mov r2, r0 800e85e: 4b06 ldr r3, [pc, #24] @ (800e878 ) 800e860: 6a1b ldr r3, [r3, #32] 800e862: 091b lsrs r3, r3, #4 800e864: f003 0307 and.w r3, r3, #7 800e868: 4904 ldr r1, [pc, #16] @ (800e87c ) 800e86a: 5ccb ldrb r3, [r1, r3] 800e86c: f003 031f and.w r3, r3, #31 800e870: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); #endif } 800e874: 4618 mov r0, r3 800e876: bd80 pop {r7, pc} 800e878: 58024400 .word 0x58024400 800e87c: 080186dc .word 0x080186dc 0800e880 : * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL2_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) { 800e880: b480 push {r7} 800e882: b089 sub sp, #36 @ 0x24 800e884: af00 add r7, sp, #0 800e886: 6078 str r0, [r7, #4] float_t fracn2, pll2vco; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N PLL2xCLK = PLL2_VCO / PLL2x */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800e888: 4ba1 ldr r3, [pc, #644] @ (800eb10 ) 800e88a: 6a9b ldr r3, [r3, #40] @ 0x28 800e88c: f003 0303 and.w r3, r3, #3 800e890: 61bb str r3, [r7, #24] pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); 800e892: 4b9f ldr r3, [pc, #636] @ (800eb10 ) 800e894: 6a9b ldr r3, [r3, #40] @ 0x28 800e896: 0b1b lsrs r3, r3, #12 800e898: f003 033f and.w r3, r3, #63 @ 0x3f 800e89c: 617b str r3, [r7, #20] pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; 800e89e: 4b9c ldr r3, [pc, #624] @ (800eb10 ) 800e8a0: 6adb ldr r3, [r3, #44] @ 0x2c 800e8a2: 091b lsrs r3, r3, #4 800e8a4: f003 0301 and.w r3, r3, #1 800e8a8: 613b str r3, [r7, #16] fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); 800e8aa: 4b99 ldr r3, [pc, #612] @ (800eb10 ) 800e8ac: 6bdb ldr r3, [r3, #60] @ 0x3c 800e8ae: 08db lsrs r3, r3, #3 800e8b0: f3c3 030c ubfx r3, r3, #0, #13 800e8b4: 693a ldr r2, [r7, #16] 800e8b6: fb02 f303 mul.w r3, r2, r3 800e8ba: ee07 3a90 vmov s15, r3 800e8be: eef8 7a67 vcvt.f32.u32 s15, s15 800e8c2: edc7 7a03 vstr s15, [r7, #12] if (pll2m != 0U) 800e8c6: 697b ldr r3, [r7, #20] 800e8c8: 2b00 cmp r3, #0 800e8ca: f000 8111 beq.w 800eaf0 { switch (pllsource) 800e8ce: 69bb ldr r3, [r7, #24] 800e8d0: 2b02 cmp r3, #2 800e8d2: f000 8083 beq.w 800e9dc 800e8d6: 69bb ldr r3, [r7, #24] 800e8d8: 2b02 cmp r3, #2 800e8da: f200 80a1 bhi.w 800ea20 800e8de: 69bb ldr r3, [r7, #24] 800e8e0: 2b00 cmp r3, #0 800e8e2: d003 beq.n 800e8ec 800e8e4: 69bb ldr r3, [r7, #24] 800e8e6: 2b01 cmp r3, #1 800e8e8: d056 beq.n 800e998 800e8ea: e099 b.n 800ea20 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800e8ec: 4b88 ldr r3, [pc, #544] @ (800eb10 ) 800e8ee: 681b ldr r3, [r3, #0] 800e8f0: f003 0320 and.w r3, r3, #32 800e8f4: 2b00 cmp r3, #0 800e8f6: d02d beq.n 800e954 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e8f8: 4b85 ldr r3, [pc, #532] @ (800eb10 ) 800e8fa: 681b ldr r3, [r3, #0] 800e8fc: 08db lsrs r3, r3, #3 800e8fe: f003 0303 and.w r3, r3, #3 800e902: 4a84 ldr r2, [pc, #528] @ (800eb14 ) 800e904: fa22 f303 lsr.w r3, r2, r3 800e908: 60bb str r3, [r7, #8] pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e90a: 68bb ldr r3, [r7, #8] 800e90c: ee07 3a90 vmov s15, r3 800e910: eef8 6a67 vcvt.f32.u32 s13, s15 800e914: 697b ldr r3, [r7, #20] 800e916: ee07 3a90 vmov s15, r3 800e91a: eef8 7a67 vcvt.f32.u32 s15, s15 800e91e: ee86 7aa7 vdiv.f32 s14, s13, s15 800e922: 4b7b ldr r3, [pc, #492] @ (800eb10 ) 800e924: 6b9b ldr r3, [r3, #56] @ 0x38 800e926: f3c3 0308 ubfx r3, r3, #0, #9 800e92a: ee07 3a90 vmov s15, r3 800e92e: eef8 6a67 vcvt.f32.u32 s13, s15 800e932: ed97 6a03 vldr s12, [r7, #12] 800e936: eddf 5a78 vldr s11, [pc, #480] @ 800eb18 800e93a: eec6 7a25 vdiv.f32 s15, s12, s11 800e93e: ee76 7aa7 vadd.f32 s15, s13, s15 800e942: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e946: ee77 7aa6 vadd.f32 s15, s15, s13 800e94a: ee67 7a27 vmul.f32 s15, s14, s15 800e94e: edc7 7a07 vstr s15, [r7, #28] } else { pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); } break; 800e952: e087 b.n 800ea64 pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e954: 697b ldr r3, [r7, #20] 800e956: ee07 3a90 vmov s15, r3 800e95a: eef8 7a67 vcvt.f32.u32 s15, s15 800e95e: eddf 6a6f vldr s13, [pc, #444] @ 800eb1c 800e962: ee86 7aa7 vdiv.f32 s14, s13, s15 800e966: 4b6a ldr r3, [pc, #424] @ (800eb10 ) 800e968: 6b9b ldr r3, [r3, #56] @ 0x38 800e96a: f3c3 0308 ubfx r3, r3, #0, #9 800e96e: ee07 3a90 vmov s15, r3 800e972: eef8 6a67 vcvt.f32.u32 s13, s15 800e976: ed97 6a03 vldr s12, [r7, #12] 800e97a: eddf 5a67 vldr s11, [pc, #412] @ 800eb18 800e97e: eec6 7a25 vdiv.f32 s15, s12, s11 800e982: ee76 7aa7 vadd.f32 s15, s13, s15 800e986: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e98a: ee77 7aa6 vadd.f32 s15, s15, s13 800e98e: ee67 7a27 vmul.f32 s15, s14, s15 800e992: edc7 7a07 vstr s15, [r7, #28] break; 800e996: e065 b.n 800ea64 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e998: 697b ldr r3, [r7, #20] 800e99a: ee07 3a90 vmov s15, r3 800e99e: eef8 7a67 vcvt.f32.u32 s15, s15 800e9a2: eddf 6a5f vldr s13, [pc, #380] @ 800eb20 800e9a6: ee86 7aa7 vdiv.f32 s14, s13, s15 800e9aa: 4b59 ldr r3, [pc, #356] @ (800eb10 ) 800e9ac: 6b9b ldr r3, [r3, #56] @ 0x38 800e9ae: f3c3 0308 ubfx r3, r3, #0, #9 800e9b2: ee07 3a90 vmov s15, r3 800e9b6: eef8 6a67 vcvt.f32.u32 s13, s15 800e9ba: ed97 6a03 vldr s12, [r7, #12] 800e9be: eddf 5a56 vldr s11, [pc, #344] @ 800eb18 800e9c2: eec6 7a25 vdiv.f32 s15, s12, s11 800e9c6: ee76 7aa7 vadd.f32 s15, s13, s15 800e9ca: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e9ce: ee77 7aa6 vadd.f32 s15, s15, s13 800e9d2: ee67 7a27 vmul.f32 s15, s14, s15 800e9d6: edc7 7a07 vstr s15, [r7, #28] break; 800e9da: e043 b.n 800ea64 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e9dc: 697b ldr r3, [r7, #20] 800e9de: ee07 3a90 vmov s15, r3 800e9e2: eef8 7a67 vcvt.f32.u32 s15, s15 800e9e6: eddf 6a4f vldr s13, [pc, #316] @ 800eb24 800e9ea: ee86 7aa7 vdiv.f32 s14, s13, s15 800e9ee: 4b48 ldr r3, [pc, #288] @ (800eb10 ) 800e9f0: 6b9b ldr r3, [r3, #56] @ 0x38 800e9f2: f3c3 0308 ubfx r3, r3, #0, #9 800e9f6: ee07 3a90 vmov s15, r3 800e9fa: eef8 6a67 vcvt.f32.u32 s13, s15 800e9fe: ed97 6a03 vldr s12, [r7, #12] 800ea02: eddf 5a45 vldr s11, [pc, #276] @ 800eb18 800ea06: eec6 7a25 vdiv.f32 s15, s12, s11 800ea0a: ee76 7aa7 vadd.f32 s15, s13, s15 800ea0e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ea12: ee77 7aa6 vadd.f32 s15, s15, s13 800ea16: ee67 7a27 vmul.f32 s15, s14, s15 800ea1a: edc7 7a07 vstr s15, [r7, #28] break; 800ea1e: e021 b.n 800ea64 default: pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800ea20: 697b ldr r3, [r7, #20] 800ea22: ee07 3a90 vmov s15, r3 800ea26: eef8 7a67 vcvt.f32.u32 s15, s15 800ea2a: eddf 6a3d vldr s13, [pc, #244] @ 800eb20 800ea2e: ee86 7aa7 vdiv.f32 s14, s13, s15 800ea32: 4b37 ldr r3, [pc, #220] @ (800eb10 ) 800ea34: 6b9b ldr r3, [r3, #56] @ 0x38 800ea36: f3c3 0308 ubfx r3, r3, #0, #9 800ea3a: ee07 3a90 vmov s15, r3 800ea3e: eef8 6a67 vcvt.f32.u32 s13, s15 800ea42: ed97 6a03 vldr s12, [r7, #12] 800ea46: eddf 5a34 vldr s11, [pc, #208] @ 800eb18 800ea4a: eec6 7a25 vdiv.f32 s15, s12, s11 800ea4e: ee76 7aa7 vadd.f32 s15, s13, s15 800ea52: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ea56: ee77 7aa6 vadd.f32 s15, s15, s13 800ea5a: ee67 7a27 vmul.f32 s15, s14, s15 800ea5e: edc7 7a07 vstr s15, [r7, #28] break; 800ea62: bf00 nop } PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; 800ea64: 4b2a ldr r3, [pc, #168] @ (800eb10 ) 800ea66: 6b9b ldr r3, [r3, #56] @ 0x38 800ea68: 0a5b lsrs r3, r3, #9 800ea6a: f003 037f and.w r3, r3, #127 @ 0x7f 800ea6e: ee07 3a90 vmov s15, r3 800ea72: eef8 7a67 vcvt.f32.u32 s15, s15 800ea76: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ea7a: ee37 7a87 vadd.f32 s14, s15, s14 800ea7e: edd7 6a07 vldr s13, [r7, #28] 800ea82: eec6 7a87 vdiv.f32 s15, s13, s14 800ea86: eefc 7ae7 vcvt.u32.f32 s15, s15 800ea8a: ee17 2a90 vmov r2, s15 800ea8e: 687b ldr r3, [r7, #4] 800ea90: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; 800ea92: 4b1f ldr r3, [pc, #124] @ (800eb10 ) 800ea94: 6b9b ldr r3, [r3, #56] @ 0x38 800ea96: 0c1b lsrs r3, r3, #16 800ea98: f003 037f and.w r3, r3, #127 @ 0x7f 800ea9c: ee07 3a90 vmov s15, r3 800eaa0: eef8 7a67 vcvt.f32.u32 s15, s15 800eaa4: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800eaa8: ee37 7a87 vadd.f32 s14, s15, s14 800eaac: edd7 6a07 vldr s13, [r7, #28] 800eab0: eec6 7a87 vdiv.f32 s15, s13, s14 800eab4: eefc 7ae7 vcvt.u32.f32 s15, s15 800eab8: ee17 2a90 vmov r2, s15 800eabc: 687b ldr r3, [r7, #4] 800eabe: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; 800eac0: 4b13 ldr r3, [pc, #76] @ (800eb10 ) 800eac2: 6b9b ldr r3, [r3, #56] @ 0x38 800eac4: 0e1b lsrs r3, r3, #24 800eac6: f003 037f and.w r3, r3, #127 @ 0x7f 800eaca: ee07 3a90 vmov s15, r3 800eace: eef8 7a67 vcvt.f32.u32 s15, s15 800ead2: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ead6: ee37 7a87 vadd.f32 s14, s15, s14 800eada: edd7 6a07 vldr s13, [r7, #28] 800eade: eec6 7a87 vdiv.f32 s15, s13, s14 800eae2: eefc 7ae7 vcvt.u32.f32 s15, s15 800eae6: ee17 2a90 vmov r2, s15 800eaea: 687b ldr r3, [r7, #4] 800eaec: 609a str r2, [r3, #8] { PLL2_Clocks->PLL2_P_Frequency = 0U; PLL2_Clocks->PLL2_Q_Frequency = 0U; PLL2_Clocks->PLL2_R_Frequency = 0U; } } 800eaee: e008 b.n 800eb02 PLL2_Clocks->PLL2_P_Frequency = 0U; 800eaf0: 687b ldr r3, [r7, #4] 800eaf2: 2200 movs r2, #0 800eaf4: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = 0U; 800eaf6: 687b ldr r3, [r7, #4] 800eaf8: 2200 movs r2, #0 800eafa: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = 0U; 800eafc: 687b ldr r3, [r7, #4] 800eafe: 2200 movs r2, #0 800eb00: 609a str r2, [r3, #8] } 800eb02: bf00 nop 800eb04: 3724 adds r7, #36 @ 0x24 800eb06: 46bd mov sp, r7 800eb08: f85d 7b04 ldr.w r7, [sp], #4 800eb0c: 4770 bx lr 800eb0e: bf00 nop 800eb10: 58024400 .word 0x58024400 800eb14: 03d09000 .word 0x03d09000 800eb18: 46000000 .word 0x46000000 800eb1c: 4c742400 .word 0x4c742400 800eb20: 4a742400 .word 0x4a742400 800eb24: 4bbebc20 .word 0x4bbebc20 0800eb28 : * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL3_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) { 800eb28: b480 push {r7} 800eb2a: b089 sub sp, #36 @ 0x24 800eb2c: af00 add r7, sp, #0 800eb2e: 6078 str r0, [r7, #4] float_t fracn3, pll3vco; /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N PLL3xCLK = PLL3_VCO / PLLxR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800eb30: 4ba1 ldr r3, [pc, #644] @ (800edb8 ) 800eb32: 6a9b ldr r3, [r3, #40] @ 0x28 800eb34: f003 0303 and.w r3, r3, #3 800eb38: 61bb str r3, [r7, #24] pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; 800eb3a: 4b9f ldr r3, [pc, #636] @ (800edb8 ) 800eb3c: 6a9b ldr r3, [r3, #40] @ 0x28 800eb3e: 0d1b lsrs r3, r3, #20 800eb40: f003 033f and.w r3, r3, #63 @ 0x3f 800eb44: 617b str r3, [r7, #20] pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; 800eb46: 4b9c ldr r3, [pc, #624] @ (800edb8 ) 800eb48: 6adb ldr r3, [r3, #44] @ 0x2c 800eb4a: 0a1b lsrs r3, r3, #8 800eb4c: f003 0301 and.w r3, r3, #1 800eb50: 613b str r3, [r7, #16] fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); 800eb52: 4b99 ldr r3, [pc, #612] @ (800edb8 ) 800eb54: 6c5b ldr r3, [r3, #68] @ 0x44 800eb56: 08db lsrs r3, r3, #3 800eb58: f3c3 030c ubfx r3, r3, #0, #13 800eb5c: 693a ldr r2, [r7, #16] 800eb5e: fb02 f303 mul.w r3, r2, r3 800eb62: ee07 3a90 vmov s15, r3 800eb66: eef8 7a67 vcvt.f32.u32 s15, s15 800eb6a: edc7 7a03 vstr s15, [r7, #12] if (pll3m != 0U) 800eb6e: 697b ldr r3, [r7, #20] 800eb70: 2b00 cmp r3, #0 800eb72: f000 8111 beq.w 800ed98 { switch (pllsource) 800eb76: 69bb ldr r3, [r7, #24] 800eb78: 2b02 cmp r3, #2 800eb7a: f000 8083 beq.w 800ec84 800eb7e: 69bb ldr r3, [r7, #24] 800eb80: 2b02 cmp r3, #2 800eb82: f200 80a1 bhi.w 800ecc8 800eb86: 69bb ldr r3, [r7, #24] 800eb88: 2b00 cmp r3, #0 800eb8a: d003 beq.n 800eb94 800eb8c: 69bb ldr r3, [r7, #24] 800eb8e: 2b01 cmp r3, #1 800eb90: d056 beq.n 800ec40 800eb92: e099 b.n 800ecc8 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800eb94: 4b88 ldr r3, [pc, #544] @ (800edb8 ) 800eb96: 681b ldr r3, [r3, #0] 800eb98: f003 0320 and.w r3, r3, #32 800eb9c: 2b00 cmp r3, #0 800eb9e: d02d beq.n 800ebfc { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800eba0: 4b85 ldr r3, [pc, #532] @ (800edb8 ) 800eba2: 681b ldr r3, [r3, #0] 800eba4: 08db lsrs r3, r3, #3 800eba6: f003 0303 and.w r3, r3, #3 800ebaa: 4a84 ldr r2, [pc, #528] @ (800edbc ) 800ebac: fa22 f303 lsr.w r3, r2, r3 800ebb0: 60bb str r3, [r7, #8] pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ebb2: 68bb ldr r3, [r7, #8] 800ebb4: ee07 3a90 vmov s15, r3 800ebb8: eef8 6a67 vcvt.f32.u32 s13, s15 800ebbc: 697b ldr r3, [r7, #20] 800ebbe: ee07 3a90 vmov s15, r3 800ebc2: eef8 7a67 vcvt.f32.u32 s15, s15 800ebc6: ee86 7aa7 vdiv.f32 s14, s13, s15 800ebca: 4b7b ldr r3, [pc, #492] @ (800edb8 ) 800ebcc: 6c1b ldr r3, [r3, #64] @ 0x40 800ebce: f3c3 0308 ubfx r3, r3, #0, #9 800ebd2: ee07 3a90 vmov s15, r3 800ebd6: eef8 6a67 vcvt.f32.u32 s13, s15 800ebda: ed97 6a03 vldr s12, [r7, #12] 800ebde: eddf 5a78 vldr s11, [pc, #480] @ 800edc0 800ebe2: eec6 7a25 vdiv.f32 s15, s12, s11 800ebe6: ee76 7aa7 vadd.f32 s15, s13, s15 800ebea: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ebee: ee77 7aa6 vadd.f32 s15, s15, s13 800ebf2: ee67 7a27 vmul.f32 s15, s14, s15 800ebf6: edc7 7a07 vstr s15, [r7, #28] } else { pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); } break; 800ebfa: e087 b.n 800ed0c pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ebfc: 697b ldr r3, [r7, #20] 800ebfe: ee07 3a90 vmov s15, r3 800ec02: eef8 7a67 vcvt.f32.u32 s15, s15 800ec06: eddf 6a6f vldr s13, [pc, #444] @ 800edc4 800ec0a: ee86 7aa7 vdiv.f32 s14, s13, s15 800ec0e: 4b6a ldr r3, [pc, #424] @ (800edb8 ) 800ec10: 6c1b ldr r3, [r3, #64] @ 0x40 800ec12: f3c3 0308 ubfx r3, r3, #0, #9 800ec16: ee07 3a90 vmov s15, r3 800ec1a: eef8 6a67 vcvt.f32.u32 s13, s15 800ec1e: ed97 6a03 vldr s12, [r7, #12] 800ec22: eddf 5a67 vldr s11, [pc, #412] @ 800edc0 800ec26: eec6 7a25 vdiv.f32 s15, s12, s11 800ec2a: ee76 7aa7 vadd.f32 s15, s13, s15 800ec2e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ec32: ee77 7aa6 vadd.f32 s15, s15, s13 800ec36: ee67 7a27 vmul.f32 s15, s14, s15 800ec3a: edc7 7a07 vstr s15, [r7, #28] break; 800ec3e: e065 b.n 800ed0c case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ec40: 697b ldr r3, [r7, #20] 800ec42: ee07 3a90 vmov s15, r3 800ec46: eef8 7a67 vcvt.f32.u32 s15, s15 800ec4a: eddf 6a5f vldr s13, [pc, #380] @ 800edc8 800ec4e: ee86 7aa7 vdiv.f32 s14, s13, s15 800ec52: 4b59 ldr r3, [pc, #356] @ (800edb8 ) 800ec54: 6c1b ldr r3, [r3, #64] @ 0x40 800ec56: f3c3 0308 ubfx r3, r3, #0, #9 800ec5a: ee07 3a90 vmov s15, r3 800ec5e: eef8 6a67 vcvt.f32.u32 s13, s15 800ec62: ed97 6a03 vldr s12, [r7, #12] 800ec66: eddf 5a56 vldr s11, [pc, #344] @ 800edc0 800ec6a: eec6 7a25 vdiv.f32 s15, s12, s11 800ec6e: ee76 7aa7 vadd.f32 s15, s13, s15 800ec72: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ec76: ee77 7aa6 vadd.f32 s15, s15, s13 800ec7a: ee67 7a27 vmul.f32 s15, s14, s15 800ec7e: edc7 7a07 vstr s15, [r7, #28] break; 800ec82: e043 b.n 800ed0c case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ec84: 697b ldr r3, [r7, #20] 800ec86: ee07 3a90 vmov s15, r3 800ec8a: eef8 7a67 vcvt.f32.u32 s15, s15 800ec8e: eddf 6a4f vldr s13, [pc, #316] @ 800edcc 800ec92: ee86 7aa7 vdiv.f32 s14, s13, s15 800ec96: 4b48 ldr r3, [pc, #288] @ (800edb8 ) 800ec98: 6c1b ldr r3, [r3, #64] @ 0x40 800ec9a: f3c3 0308 ubfx r3, r3, #0, #9 800ec9e: ee07 3a90 vmov s15, r3 800eca2: eef8 6a67 vcvt.f32.u32 s13, s15 800eca6: ed97 6a03 vldr s12, [r7, #12] 800ecaa: eddf 5a45 vldr s11, [pc, #276] @ 800edc0 800ecae: eec6 7a25 vdiv.f32 s15, s12, s11 800ecb2: ee76 7aa7 vadd.f32 s15, s13, s15 800ecb6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ecba: ee77 7aa6 vadd.f32 s15, s15, s13 800ecbe: ee67 7a27 vmul.f32 s15, s14, s15 800ecc2: edc7 7a07 vstr s15, [r7, #28] break; 800ecc6: e021 b.n 800ed0c default: pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ecc8: 697b ldr r3, [r7, #20] 800ecca: ee07 3a90 vmov s15, r3 800ecce: eef8 7a67 vcvt.f32.u32 s15, s15 800ecd2: eddf 6a3d vldr s13, [pc, #244] @ 800edc8 800ecd6: ee86 7aa7 vdiv.f32 s14, s13, s15 800ecda: 4b37 ldr r3, [pc, #220] @ (800edb8 ) 800ecdc: 6c1b ldr r3, [r3, #64] @ 0x40 800ecde: f3c3 0308 ubfx r3, r3, #0, #9 800ece2: ee07 3a90 vmov s15, r3 800ece6: eef8 6a67 vcvt.f32.u32 s13, s15 800ecea: ed97 6a03 vldr s12, [r7, #12] 800ecee: eddf 5a34 vldr s11, [pc, #208] @ 800edc0 800ecf2: eec6 7a25 vdiv.f32 s15, s12, s11 800ecf6: ee76 7aa7 vadd.f32 s15, s13, s15 800ecfa: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ecfe: ee77 7aa6 vadd.f32 s15, s15, s13 800ed02: ee67 7a27 vmul.f32 s15, s14, s15 800ed06: edc7 7a07 vstr s15, [r7, #28] break; 800ed0a: bf00 nop } PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; 800ed0c: 4b2a ldr r3, [pc, #168] @ (800edb8 ) 800ed0e: 6c1b ldr r3, [r3, #64] @ 0x40 800ed10: 0a5b lsrs r3, r3, #9 800ed12: f003 037f and.w r3, r3, #127 @ 0x7f 800ed16: ee07 3a90 vmov s15, r3 800ed1a: eef8 7a67 vcvt.f32.u32 s15, s15 800ed1e: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ed22: ee37 7a87 vadd.f32 s14, s15, s14 800ed26: edd7 6a07 vldr s13, [r7, #28] 800ed2a: eec6 7a87 vdiv.f32 s15, s13, s14 800ed2e: eefc 7ae7 vcvt.u32.f32 s15, s15 800ed32: ee17 2a90 vmov r2, s15 800ed36: 687b ldr r3, [r7, #4] 800ed38: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; 800ed3a: 4b1f ldr r3, [pc, #124] @ (800edb8 ) 800ed3c: 6c1b ldr r3, [r3, #64] @ 0x40 800ed3e: 0c1b lsrs r3, r3, #16 800ed40: f003 037f and.w r3, r3, #127 @ 0x7f 800ed44: ee07 3a90 vmov s15, r3 800ed48: eef8 7a67 vcvt.f32.u32 s15, s15 800ed4c: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ed50: ee37 7a87 vadd.f32 s14, s15, s14 800ed54: edd7 6a07 vldr s13, [r7, #28] 800ed58: eec6 7a87 vdiv.f32 s15, s13, s14 800ed5c: eefc 7ae7 vcvt.u32.f32 s15, s15 800ed60: ee17 2a90 vmov r2, s15 800ed64: 687b ldr r3, [r7, #4] 800ed66: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; 800ed68: 4b13 ldr r3, [pc, #76] @ (800edb8 ) 800ed6a: 6c1b ldr r3, [r3, #64] @ 0x40 800ed6c: 0e1b lsrs r3, r3, #24 800ed6e: f003 037f and.w r3, r3, #127 @ 0x7f 800ed72: ee07 3a90 vmov s15, r3 800ed76: eef8 7a67 vcvt.f32.u32 s15, s15 800ed7a: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ed7e: ee37 7a87 vadd.f32 s14, s15, s14 800ed82: edd7 6a07 vldr s13, [r7, #28] 800ed86: eec6 7a87 vdiv.f32 s15, s13, s14 800ed8a: eefc 7ae7 vcvt.u32.f32 s15, s15 800ed8e: ee17 2a90 vmov r2, s15 800ed92: 687b ldr r3, [r7, #4] 800ed94: 609a str r2, [r3, #8] PLL3_Clocks->PLL3_P_Frequency = 0U; PLL3_Clocks->PLL3_Q_Frequency = 0U; PLL3_Clocks->PLL3_R_Frequency = 0U; } } 800ed96: e008 b.n 800edaa PLL3_Clocks->PLL3_P_Frequency = 0U; 800ed98: 687b ldr r3, [r7, #4] 800ed9a: 2200 movs r2, #0 800ed9c: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = 0U; 800ed9e: 687b ldr r3, [r7, #4] 800eda0: 2200 movs r2, #0 800eda2: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = 0U; 800eda4: 687b ldr r3, [r7, #4] 800eda6: 2200 movs r2, #0 800eda8: 609a str r2, [r3, #8] } 800edaa: bf00 nop 800edac: 3724 adds r7, #36 @ 0x24 800edae: 46bd mov sp, r7 800edb0: f85d 7b04 ldr.w r7, [sp], #4 800edb4: 4770 bx lr 800edb6: bf00 nop 800edb8: 58024400 .word 0x58024400 800edbc: 03d09000 .word 0x03d09000 800edc0: 46000000 .word 0x46000000 800edc4: 4c742400 .word 0x4c742400 800edc8: 4a742400 .word 0x4a742400 800edcc: 4bbebc20 .word 0x4bbebc20 0800edd0 : * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL1_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) { 800edd0: b480 push {r7} 800edd2: b089 sub sp, #36 @ 0x24 800edd4: af00 add r7, sp, #0 800edd6: 6078 str r0, [r7, #4] uint32_t pllsource, pll1m, pll1fracen, hsivalue; float_t fracn1, pll1vco; pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800edd8: 4ba0 ldr r3, [pc, #640] @ (800f05c ) 800edda: 6a9b ldr r3, [r3, #40] @ 0x28 800eddc: f003 0303 and.w r3, r3, #3 800ede0: 61bb str r3, [r7, #24] pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); 800ede2: 4b9e ldr r3, [pc, #632] @ (800f05c ) 800ede4: 6a9b ldr r3, [r3, #40] @ 0x28 800ede6: 091b lsrs r3, r3, #4 800ede8: f003 033f and.w r3, r3, #63 @ 0x3f 800edec: 617b str r3, [r7, #20] pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; 800edee: 4b9b ldr r3, [pc, #620] @ (800f05c ) 800edf0: 6adb ldr r3, [r3, #44] @ 0x2c 800edf2: f003 0301 and.w r3, r3, #1 800edf6: 613b str r3, [r7, #16] fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800edf8: 4b98 ldr r3, [pc, #608] @ (800f05c ) 800edfa: 6b5b ldr r3, [r3, #52] @ 0x34 800edfc: 08db lsrs r3, r3, #3 800edfe: f3c3 030c ubfx r3, r3, #0, #13 800ee02: 693a ldr r2, [r7, #16] 800ee04: fb02 f303 mul.w r3, r2, r3 800ee08: ee07 3a90 vmov s15, r3 800ee0c: eef8 7a67 vcvt.f32.u32 s15, s15 800ee10: edc7 7a03 vstr s15, [r7, #12] if (pll1m != 0U) 800ee14: 697b ldr r3, [r7, #20] 800ee16: 2b00 cmp r3, #0 800ee18: f000 8111 beq.w 800f03e { switch (pllsource) 800ee1c: 69bb ldr r3, [r7, #24] 800ee1e: 2b02 cmp r3, #2 800ee20: f000 8083 beq.w 800ef2a 800ee24: 69bb ldr r3, [r7, #24] 800ee26: 2b02 cmp r3, #2 800ee28: f200 80a1 bhi.w 800ef6e 800ee2c: 69bb ldr r3, [r7, #24] 800ee2e: 2b00 cmp r3, #0 800ee30: d003 beq.n 800ee3a 800ee32: 69bb ldr r3, [r7, #24] 800ee34: 2b01 cmp r3, #1 800ee36: d056 beq.n 800eee6 800ee38: e099 b.n 800ef6e { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800ee3a: 4b88 ldr r3, [pc, #544] @ (800f05c ) 800ee3c: 681b ldr r3, [r3, #0] 800ee3e: f003 0320 and.w r3, r3, #32 800ee42: 2b00 cmp r3, #0 800ee44: d02d beq.n 800eea2 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800ee46: 4b85 ldr r3, [pc, #532] @ (800f05c ) 800ee48: 681b ldr r3, [r3, #0] 800ee4a: 08db lsrs r3, r3, #3 800ee4c: f003 0303 and.w r3, r3, #3 800ee50: 4a83 ldr r2, [pc, #524] @ (800f060 ) 800ee52: fa22 f303 lsr.w r3, r2, r3 800ee56: 60bb str r3, [r7, #8] pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ee58: 68bb ldr r3, [r7, #8] 800ee5a: ee07 3a90 vmov s15, r3 800ee5e: eef8 6a67 vcvt.f32.u32 s13, s15 800ee62: 697b ldr r3, [r7, #20] 800ee64: ee07 3a90 vmov s15, r3 800ee68: eef8 7a67 vcvt.f32.u32 s15, s15 800ee6c: ee86 7aa7 vdiv.f32 s14, s13, s15 800ee70: 4b7a ldr r3, [pc, #488] @ (800f05c ) 800ee72: 6b1b ldr r3, [r3, #48] @ 0x30 800ee74: f3c3 0308 ubfx r3, r3, #0, #9 800ee78: ee07 3a90 vmov s15, r3 800ee7c: eef8 6a67 vcvt.f32.u32 s13, s15 800ee80: ed97 6a03 vldr s12, [r7, #12] 800ee84: eddf 5a77 vldr s11, [pc, #476] @ 800f064 800ee88: eec6 7a25 vdiv.f32 s15, s12, s11 800ee8c: ee76 7aa7 vadd.f32 s15, s13, s15 800ee90: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ee94: ee77 7aa6 vadd.f32 s15, s15, s13 800ee98: ee67 7a27 vmul.f32 s15, s14, s15 800ee9c: edc7 7a07 vstr s15, [r7, #28] } else { pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 800eea0: e087 b.n 800efb2 pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800eea2: 697b ldr r3, [r7, #20] 800eea4: ee07 3a90 vmov s15, r3 800eea8: eef8 7a67 vcvt.f32.u32 s15, s15 800eeac: eddf 6a6e vldr s13, [pc, #440] @ 800f068 800eeb0: ee86 7aa7 vdiv.f32 s14, s13, s15 800eeb4: 4b69 ldr r3, [pc, #420] @ (800f05c ) 800eeb6: 6b1b ldr r3, [r3, #48] @ 0x30 800eeb8: f3c3 0308 ubfx r3, r3, #0, #9 800eebc: ee07 3a90 vmov s15, r3 800eec0: eef8 6a67 vcvt.f32.u32 s13, s15 800eec4: ed97 6a03 vldr s12, [r7, #12] 800eec8: eddf 5a66 vldr s11, [pc, #408] @ 800f064 800eecc: eec6 7a25 vdiv.f32 s15, s12, s11 800eed0: ee76 7aa7 vadd.f32 s15, s13, s15 800eed4: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800eed8: ee77 7aa6 vadd.f32 s15, s15, s13 800eedc: ee67 7a27 vmul.f32 s15, s14, s15 800eee0: edc7 7a07 vstr s15, [r7, #28] break; 800eee4: e065 b.n 800efb2 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800eee6: 697b ldr r3, [r7, #20] 800eee8: ee07 3a90 vmov s15, r3 800eeec: eef8 7a67 vcvt.f32.u32 s15, s15 800eef0: eddf 6a5e vldr s13, [pc, #376] @ 800f06c 800eef4: ee86 7aa7 vdiv.f32 s14, s13, s15 800eef8: 4b58 ldr r3, [pc, #352] @ (800f05c ) 800eefa: 6b1b ldr r3, [r3, #48] @ 0x30 800eefc: f3c3 0308 ubfx r3, r3, #0, #9 800ef00: ee07 3a90 vmov s15, r3 800ef04: eef8 6a67 vcvt.f32.u32 s13, s15 800ef08: ed97 6a03 vldr s12, [r7, #12] 800ef0c: eddf 5a55 vldr s11, [pc, #340] @ 800f064 800ef10: eec6 7a25 vdiv.f32 s15, s12, s11 800ef14: ee76 7aa7 vadd.f32 s15, s13, s15 800ef18: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ef1c: ee77 7aa6 vadd.f32 s15, s15, s13 800ef20: ee67 7a27 vmul.f32 s15, s14, s15 800ef24: edc7 7a07 vstr s15, [r7, #28] break; 800ef28: e043 b.n 800efb2 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ef2a: 697b ldr r3, [r7, #20] 800ef2c: ee07 3a90 vmov s15, r3 800ef30: eef8 7a67 vcvt.f32.u32 s15, s15 800ef34: eddf 6a4e vldr s13, [pc, #312] @ 800f070 800ef38: ee86 7aa7 vdiv.f32 s14, s13, s15 800ef3c: 4b47 ldr r3, [pc, #284] @ (800f05c ) 800ef3e: 6b1b ldr r3, [r3, #48] @ 0x30 800ef40: f3c3 0308 ubfx r3, r3, #0, #9 800ef44: ee07 3a90 vmov s15, r3 800ef48: eef8 6a67 vcvt.f32.u32 s13, s15 800ef4c: ed97 6a03 vldr s12, [r7, #12] 800ef50: eddf 5a44 vldr s11, [pc, #272] @ 800f064 800ef54: eec6 7a25 vdiv.f32 s15, s12, s11 800ef58: ee76 7aa7 vadd.f32 s15, s13, s15 800ef5c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ef60: ee77 7aa6 vadd.f32 s15, s15, s13 800ef64: ee67 7a27 vmul.f32 s15, s14, s15 800ef68: edc7 7a07 vstr s15, [r7, #28] break; 800ef6c: e021 b.n 800efb2 default: pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ef6e: 697b ldr r3, [r7, #20] 800ef70: ee07 3a90 vmov s15, r3 800ef74: eef8 7a67 vcvt.f32.u32 s15, s15 800ef78: eddf 6a3b vldr s13, [pc, #236] @ 800f068 800ef7c: ee86 7aa7 vdiv.f32 s14, s13, s15 800ef80: 4b36 ldr r3, [pc, #216] @ (800f05c ) 800ef82: 6b1b ldr r3, [r3, #48] @ 0x30 800ef84: f3c3 0308 ubfx r3, r3, #0, #9 800ef88: ee07 3a90 vmov s15, r3 800ef8c: eef8 6a67 vcvt.f32.u32 s13, s15 800ef90: ed97 6a03 vldr s12, [r7, #12] 800ef94: eddf 5a33 vldr s11, [pc, #204] @ 800f064 800ef98: eec6 7a25 vdiv.f32 s15, s12, s11 800ef9c: ee76 7aa7 vadd.f32 s15, s13, s15 800efa0: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800efa4: ee77 7aa6 vadd.f32 s15, s15, s13 800efa8: ee67 7a27 vmul.f32 s15, s14, s15 800efac: edc7 7a07 vstr s15, [r7, #28] break; 800efb0: bf00 nop } PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; 800efb2: 4b2a ldr r3, [pc, #168] @ (800f05c ) 800efb4: 6b1b ldr r3, [r3, #48] @ 0x30 800efb6: 0a5b lsrs r3, r3, #9 800efb8: f003 037f and.w r3, r3, #127 @ 0x7f 800efbc: ee07 3a90 vmov s15, r3 800efc0: eef8 7a67 vcvt.f32.u32 s15, s15 800efc4: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800efc8: ee37 7a87 vadd.f32 s14, s15, s14 800efcc: edd7 6a07 vldr s13, [r7, #28] 800efd0: eec6 7a87 vdiv.f32 s15, s13, s14 800efd4: eefc 7ae7 vcvt.u32.f32 s15, s15 800efd8: ee17 2a90 vmov r2, s15 800efdc: 687b ldr r3, [r7, #4] 800efde: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ; 800efe0: 4b1e ldr r3, [pc, #120] @ (800f05c ) 800efe2: 6b1b ldr r3, [r3, #48] @ 0x30 800efe4: 0c1b lsrs r3, r3, #16 800efe6: f003 037f and.w r3, r3, #127 @ 0x7f 800efea: ee07 3a90 vmov s15, r3 800efee: eef8 7a67 vcvt.f32.u32 s15, s15 800eff2: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800eff6: ee37 7a87 vadd.f32 s14, s15, s14 800effa: edd7 6a07 vldr s13, [r7, #28] 800effe: eec6 7a87 vdiv.f32 s15, s13, s14 800f002: eefc 7ae7 vcvt.u32.f32 s15, s15 800f006: ee17 2a90 vmov r2, s15 800f00a: 687b ldr r3, [r7, #4] 800f00c: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; 800f00e: 4b13 ldr r3, [pc, #76] @ (800f05c ) 800f010: 6b1b ldr r3, [r3, #48] @ 0x30 800f012: 0e1b lsrs r3, r3, #24 800f014: f003 037f and.w r3, r3, #127 @ 0x7f 800f018: ee07 3a90 vmov s15, r3 800f01c: eef8 7a67 vcvt.f32.u32 s15, s15 800f020: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800f024: ee37 7a87 vadd.f32 s14, s15, s14 800f028: edd7 6a07 vldr s13, [r7, #28] 800f02c: eec6 7a87 vdiv.f32 s15, s13, s14 800f030: eefc 7ae7 vcvt.u32.f32 s15, s15 800f034: ee17 2a90 vmov r2, s15 800f038: 687b ldr r3, [r7, #4] 800f03a: 609a str r2, [r3, #8] PLL1_Clocks->PLL1_P_Frequency = 0U; PLL1_Clocks->PLL1_Q_Frequency = 0U; PLL1_Clocks->PLL1_R_Frequency = 0U; } } 800f03c: e008 b.n 800f050 PLL1_Clocks->PLL1_P_Frequency = 0U; 800f03e: 687b ldr r3, [r7, #4] 800f040: 2200 movs r2, #0 800f042: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = 0U; 800f044: 687b ldr r3, [r7, #4] 800f046: 2200 movs r2, #0 800f048: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = 0U; 800f04a: 687b ldr r3, [r7, #4] 800f04c: 2200 movs r2, #0 800f04e: 609a str r2, [r3, #8] } 800f050: bf00 nop 800f052: 3724 adds r7, #36 @ 0x24 800f054: 46bd mov sp, r7 800f056: f85d 7b04 ldr.w r7, [sp], #4 800f05a: 4770 bx lr 800f05c: 58024400 .word 0x58024400 800f060: 03d09000 .word 0x03d09000 800f064: 46000000 .word 0x46000000 800f068: 4c742400 .word 0x4c742400 800f06c: 4a742400 .word 0x4a742400 800f070: 4bbebc20 .word 0x4bbebc20 0800f074 : * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { 800f074: b580 push {r7, lr} 800f076: b084 sub sp, #16 800f078: af00 add r7, sp, #0 800f07a: 6078 str r0, [r7, #4] 800f07c: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800f07e: 2300 movs r3, #0 800f080: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800f082: 4b53 ldr r3, [pc, #332] @ (800f1d0 ) 800f084: 6a9b ldr r3, [r3, #40] @ 0x28 800f086: f003 0303 and.w r3, r3, #3 800f08a: 2b03 cmp r3, #3 800f08c: d101 bne.n 800f092 { return HAL_ERROR; 800f08e: 2301 movs r3, #1 800f090: e099 b.n 800f1c6 else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 800f092: 4b4f ldr r3, [pc, #316] @ (800f1d0 ) 800f094: 681b ldr r3, [r3, #0] 800f096: 4a4e ldr r2, [pc, #312] @ (800f1d0 ) 800f098: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800f09c: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800f09e: f7f6 fead bl 8005dfc 800f0a2: 60b8 str r0, [r7, #8] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800f0a4: e008 b.n 800f0b8 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800f0a6: f7f6 fea9 bl 8005dfc 800f0aa: 4602 mov r2, r0 800f0ac: 68bb ldr r3, [r7, #8] 800f0ae: 1ad3 subs r3, r2, r3 800f0b0: 2b02 cmp r3, #2 800f0b2: d901 bls.n 800f0b8 { return HAL_TIMEOUT; 800f0b4: 2303 movs r3, #3 800f0b6: e086 b.n 800f1c6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800f0b8: 4b45 ldr r3, [pc, #276] @ (800f1d0 ) 800f0ba: 681b ldr r3, [r3, #0] 800f0bc: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800f0c0: 2b00 cmp r3, #0 800f0c2: d1f0 bne.n 800f0a6 } } /* Configure PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 800f0c4: 4b42 ldr r3, [pc, #264] @ (800f1d0 ) 800f0c6: 6a9b ldr r3, [r3, #40] @ 0x28 800f0c8: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800f0cc: 687b ldr r3, [r7, #4] 800f0ce: 681b ldr r3, [r3, #0] 800f0d0: 031b lsls r3, r3, #12 800f0d2: 493f ldr r1, [pc, #252] @ (800f1d0 ) 800f0d4: 4313 orrs r3, r2 800f0d6: 628b str r3, [r1, #40] @ 0x28 800f0d8: 687b ldr r3, [r7, #4] 800f0da: 685b ldr r3, [r3, #4] 800f0dc: 3b01 subs r3, #1 800f0de: f3c3 0208 ubfx r2, r3, #0, #9 800f0e2: 687b ldr r3, [r7, #4] 800f0e4: 689b ldr r3, [r3, #8] 800f0e6: 3b01 subs r3, #1 800f0e8: 025b lsls r3, r3, #9 800f0ea: b29b uxth r3, r3 800f0ec: 431a orrs r2, r3 800f0ee: 687b ldr r3, [r7, #4] 800f0f0: 68db ldr r3, [r3, #12] 800f0f2: 3b01 subs r3, #1 800f0f4: 041b lsls r3, r3, #16 800f0f6: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800f0fa: 431a orrs r2, r3 800f0fc: 687b ldr r3, [r7, #4] 800f0fe: 691b ldr r3, [r3, #16] 800f100: 3b01 subs r3, #1 800f102: 061b lsls r3, r3, #24 800f104: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800f108: 4931 ldr r1, [pc, #196] @ (800f1d0 ) 800f10a: 4313 orrs r3, r2 800f10c: 638b str r3, [r1, #56] @ 0x38 pll2->PLL2P, pll2->PLL2Q, pll2->PLL2R); /* Select PLL2 input reference frequency range: VCI */ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 800f10e: 4b30 ldr r3, [pc, #192] @ (800f1d0 ) 800f110: 6adb ldr r3, [r3, #44] @ 0x2c 800f112: f023 02c0 bic.w r2, r3, #192 @ 0xc0 800f116: 687b ldr r3, [r7, #4] 800f118: 695b ldr r3, [r3, #20] 800f11a: 492d ldr r1, [pc, #180] @ (800f1d0 ) 800f11c: 4313 orrs r3, r2 800f11e: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL2 output frequency range : VCO */ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 800f120: 4b2b ldr r3, [pc, #172] @ (800f1d0 ) 800f122: 6adb ldr r3, [r3, #44] @ 0x2c 800f124: f023 0220 bic.w r2, r3, #32 800f128: 687b ldr r3, [r7, #4] 800f12a: 699b ldr r3, [r3, #24] 800f12c: 4928 ldr r1, [pc, #160] @ (800f1d0 ) 800f12e: 4313 orrs r3, r2 800f130: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_DISABLE(); 800f132: 4b27 ldr r3, [pc, #156] @ (800f1d0 ) 800f134: 6adb ldr r3, [r3, #44] @ 0x2c 800f136: 4a26 ldr r2, [pc, #152] @ (800f1d0 ) 800f138: f023 0310 bic.w r3, r3, #16 800f13c: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 800f13e: 4b24 ldr r3, [pc, #144] @ (800f1d0 ) 800f140: 6bda ldr r2, [r3, #60] @ 0x3c 800f142: 4b24 ldr r3, [pc, #144] @ (800f1d4 ) 800f144: 4013 ands r3, r2 800f146: 687a ldr r2, [r7, #4] 800f148: 69d2 ldr r2, [r2, #28] 800f14a: 00d2 lsls r2, r2, #3 800f14c: 4920 ldr r1, [pc, #128] @ (800f1d0 ) 800f14e: 4313 orrs r3, r2 800f150: 63cb str r3, [r1, #60] @ 0x3c /* Enable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_ENABLE(); 800f152: 4b1f ldr r3, [pc, #124] @ (800f1d0 ) 800f154: 6adb ldr r3, [r3, #44] @ 0x2c 800f156: 4a1e ldr r2, [pc, #120] @ (800f1d0 ) 800f158: f043 0310 orr.w r3, r3, #16 800f15c: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL2 clock output */ if (Divider == DIVIDER_P_UPDATE) 800f15e: 683b ldr r3, [r7, #0] 800f160: 2b00 cmp r3, #0 800f162: d106 bne.n 800f172 { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 800f164: 4b1a ldr r3, [pc, #104] @ (800f1d0 ) 800f166: 6adb ldr r3, [r3, #44] @ 0x2c 800f168: 4a19 ldr r2, [pc, #100] @ (800f1d0 ) 800f16a: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800f16e: 62d3 str r3, [r2, #44] @ 0x2c 800f170: e00f b.n 800f192 } else if (Divider == DIVIDER_Q_UPDATE) 800f172: 683b ldr r3, [r7, #0] 800f174: 2b01 cmp r3, #1 800f176: d106 bne.n 800f186 { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 800f178: 4b15 ldr r3, [pc, #84] @ (800f1d0 ) 800f17a: 6adb ldr r3, [r3, #44] @ 0x2c 800f17c: 4a14 ldr r2, [pc, #80] @ (800f1d0 ) 800f17e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800f182: 62d3 str r3, [r2, #44] @ 0x2c 800f184: e005 b.n 800f192 } else { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 800f186: 4b12 ldr r3, [pc, #72] @ (800f1d0 ) 800f188: 6adb ldr r3, [r3, #44] @ 0x2c 800f18a: 4a11 ldr r2, [pc, #68] @ (800f1d0 ) 800f18c: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 800f190: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL2. */ __HAL_RCC_PLL2_ENABLE(); 800f192: 4b0f ldr r3, [pc, #60] @ (800f1d0 ) 800f194: 681b ldr r3, [r3, #0] 800f196: 4a0e ldr r2, [pc, #56] @ (800f1d0 ) 800f198: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 800f19c: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800f19e: f7f6 fe2d bl 8005dfc 800f1a2: 60b8 str r0, [r7, #8] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800f1a4: e008 b.n 800f1b8 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800f1a6: f7f6 fe29 bl 8005dfc 800f1aa: 4602 mov r2, r0 800f1ac: 68bb ldr r3, [r7, #8] 800f1ae: 1ad3 subs r3, r2, r3 800f1b0: 2b02 cmp r3, #2 800f1b2: d901 bls.n 800f1b8 { return HAL_TIMEOUT; 800f1b4: 2303 movs r3, #3 800f1b6: e006 b.n 800f1c6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800f1b8: 4b05 ldr r3, [pc, #20] @ (800f1d0 ) 800f1ba: 681b ldr r3, [r3, #0] 800f1bc: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800f1c0: 2b00 cmp r3, #0 800f1c2: d0f0 beq.n 800f1a6 } } return status; 800f1c4: 7bfb ldrb r3, [r7, #15] } 800f1c6: 4618 mov r0, r3 800f1c8: 3710 adds r7, #16 800f1ca: 46bd mov sp, r7 800f1cc: bd80 pop {r7, pc} 800f1ce: bf00 nop 800f1d0: 58024400 .word 0x58024400 800f1d4: ffff0007 .word 0xffff0007 0800f1d8 : * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { 800f1d8: b580 push {r7, lr} 800f1da: b084 sub sp, #16 800f1dc: af00 add r7, sp, #0 800f1de: 6078 str r0, [r7, #4] 800f1e0: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800f1e2: 2300 movs r3, #0 800f1e4: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800f1e6: 4b53 ldr r3, [pc, #332] @ (800f334 ) 800f1e8: 6a9b ldr r3, [r3, #40] @ 0x28 800f1ea: f003 0303 and.w r3, r3, #3 800f1ee: 2b03 cmp r3, #3 800f1f0: d101 bne.n 800f1f6 { return HAL_ERROR; 800f1f2: 2301 movs r3, #1 800f1f4: e099 b.n 800f32a else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 800f1f6: 4b4f ldr r3, [pc, #316] @ (800f334 ) 800f1f8: 681b ldr r3, [r3, #0] 800f1fa: 4a4e ldr r2, [pc, #312] @ (800f334 ) 800f1fc: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800f200: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800f202: f7f6 fdfb bl 8005dfc 800f206: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800f208: e008 b.n 800f21c { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800f20a: f7f6 fdf7 bl 8005dfc 800f20e: 4602 mov r2, r0 800f210: 68bb ldr r3, [r7, #8] 800f212: 1ad3 subs r3, r2, r3 800f214: 2b02 cmp r3, #2 800f216: d901 bls.n 800f21c { return HAL_TIMEOUT; 800f218: 2303 movs r3, #3 800f21a: e086 b.n 800f32a while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800f21c: 4b45 ldr r3, [pc, #276] @ (800f334 ) 800f21e: 681b ldr r3, [r3, #0] 800f220: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800f224: 2b00 cmp r3, #0 800f226: d1f0 bne.n 800f20a } } /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 800f228: 4b42 ldr r3, [pc, #264] @ (800f334 ) 800f22a: 6a9b ldr r3, [r3, #40] @ 0x28 800f22c: f023 727c bic.w r2, r3, #66060288 @ 0x3f00000 800f230: 687b ldr r3, [r7, #4] 800f232: 681b ldr r3, [r3, #0] 800f234: 051b lsls r3, r3, #20 800f236: 493f ldr r1, [pc, #252] @ (800f334 ) 800f238: 4313 orrs r3, r2 800f23a: 628b str r3, [r1, #40] @ 0x28 800f23c: 687b ldr r3, [r7, #4] 800f23e: 685b ldr r3, [r3, #4] 800f240: 3b01 subs r3, #1 800f242: f3c3 0208 ubfx r2, r3, #0, #9 800f246: 687b ldr r3, [r7, #4] 800f248: 689b ldr r3, [r3, #8] 800f24a: 3b01 subs r3, #1 800f24c: 025b lsls r3, r3, #9 800f24e: b29b uxth r3, r3 800f250: 431a orrs r2, r3 800f252: 687b ldr r3, [r7, #4] 800f254: 68db ldr r3, [r3, #12] 800f256: 3b01 subs r3, #1 800f258: 041b lsls r3, r3, #16 800f25a: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800f25e: 431a orrs r2, r3 800f260: 687b ldr r3, [r7, #4] 800f262: 691b ldr r3, [r3, #16] 800f264: 3b01 subs r3, #1 800f266: 061b lsls r3, r3, #24 800f268: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800f26c: 4931 ldr r1, [pc, #196] @ (800f334 ) 800f26e: 4313 orrs r3, r2 800f270: 640b str r3, [r1, #64] @ 0x40 pll3->PLL3P, pll3->PLL3Q, pll3->PLL3R); /* Select PLL3 input reference frequency range: VCI */ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 800f272: 4b30 ldr r3, [pc, #192] @ (800f334 ) 800f274: 6adb ldr r3, [r3, #44] @ 0x2c 800f276: f423 6240 bic.w r2, r3, #3072 @ 0xc00 800f27a: 687b ldr r3, [r7, #4] 800f27c: 695b ldr r3, [r3, #20] 800f27e: 492d ldr r1, [pc, #180] @ (800f334 ) 800f280: 4313 orrs r3, r2 800f282: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL3 output frequency range : VCO */ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 800f284: 4b2b ldr r3, [pc, #172] @ (800f334 ) 800f286: 6adb ldr r3, [r3, #44] @ 0x2c 800f288: f423 7200 bic.w r2, r3, #512 @ 0x200 800f28c: 687b ldr r3, [r7, #4] 800f28e: 699b ldr r3, [r3, #24] 800f290: 4928 ldr r1, [pc, #160] @ (800f334 ) 800f292: 4313 orrs r3, r2 800f294: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_DISABLE(); 800f296: 4b27 ldr r3, [pc, #156] @ (800f334 ) 800f298: 6adb ldr r3, [r3, #44] @ 0x2c 800f29a: 4a26 ldr r2, [pc, #152] @ (800f334 ) 800f29c: f423 7380 bic.w r3, r3, #256 @ 0x100 800f2a0: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 800f2a2: 4b24 ldr r3, [pc, #144] @ (800f334 ) 800f2a4: 6c5a ldr r2, [r3, #68] @ 0x44 800f2a6: 4b24 ldr r3, [pc, #144] @ (800f338 ) 800f2a8: 4013 ands r3, r2 800f2aa: 687a ldr r2, [r7, #4] 800f2ac: 69d2 ldr r2, [r2, #28] 800f2ae: 00d2 lsls r2, r2, #3 800f2b0: 4920 ldr r1, [pc, #128] @ (800f334 ) 800f2b2: 4313 orrs r3, r2 800f2b4: 644b str r3, [r1, #68] @ 0x44 /* Enable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_ENABLE(); 800f2b6: 4b1f ldr r3, [pc, #124] @ (800f334 ) 800f2b8: 6adb ldr r3, [r3, #44] @ 0x2c 800f2ba: 4a1e ldr r2, [pc, #120] @ (800f334 ) 800f2bc: f443 7380 orr.w r3, r3, #256 @ 0x100 800f2c0: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL3 clock output */ if (Divider == DIVIDER_P_UPDATE) 800f2c2: 683b ldr r3, [r7, #0] 800f2c4: 2b00 cmp r3, #0 800f2c6: d106 bne.n 800f2d6 { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 800f2c8: 4b1a ldr r3, [pc, #104] @ (800f334 ) 800f2ca: 6adb ldr r3, [r3, #44] @ 0x2c 800f2cc: 4a19 ldr r2, [pc, #100] @ (800f334 ) 800f2ce: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 800f2d2: 62d3 str r3, [r2, #44] @ 0x2c 800f2d4: e00f b.n 800f2f6 } else if (Divider == DIVIDER_Q_UPDATE) 800f2d6: 683b ldr r3, [r7, #0] 800f2d8: 2b01 cmp r3, #1 800f2da: d106 bne.n 800f2ea { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 800f2dc: 4b15 ldr r3, [pc, #84] @ (800f334 ) 800f2de: 6adb ldr r3, [r3, #44] @ 0x2c 800f2e0: 4a14 ldr r2, [pc, #80] @ (800f334 ) 800f2e2: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 800f2e6: 62d3 str r3, [r2, #44] @ 0x2c 800f2e8: e005 b.n 800f2f6 } else { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 800f2ea: 4b12 ldr r3, [pc, #72] @ (800f334 ) 800f2ec: 6adb ldr r3, [r3, #44] @ 0x2c 800f2ee: 4a11 ldr r2, [pc, #68] @ (800f334 ) 800f2f0: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800f2f4: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL3. */ __HAL_RCC_PLL3_ENABLE(); 800f2f6: 4b0f ldr r3, [pc, #60] @ (800f334 ) 800f2f8: 681b ldr r3, [r3, #0] 800f2fa: 4a0e ldr r2, [pc, #56] @ (800f334 ) 800f2fc: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800f300: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800f302: f7f6 fd7b bl 8005dfc 800f306: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800f308: e008 b.n 800f31c { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800f30a: f7f6 fd77 bl 8005dfc 800f30e: 4602 mov r2, r0 800f310: 68bb ldr r3, [r7, #8] 800f312: 1ad3 subs r3, r2, r3 800f314: 2b02 cmp r3, #2 800f316: d901 bls.n 800f31c { return HAL_TIMEOUT; 800f318: 2303 movs r3, #3 800f31a: e006 b.n 800f32a while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800f31c: 4b05 ldr r3, [pc, #20] @ (800f334 ) 800f31e: 681b ldr r3, [r3, #0] 800f320: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800f324: 2b00 cmp r3, #0 800f326: d0f0 beq.n 800f30a } } return status; 800f328: 7bfb ldrb r3, [r7, #15] } 800f32a: 4618 mov r0, r3 800f32c: 3710 adds r7, #16 800f32e: 46bd mov sp, r7 800f330: bd80 pop {r7, pc} 800f332: bf00 nop 800f334: 58024400 .word 0x58024400 800f338: ffff0007 .word 0xffff0007 0800f33c : * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL status */ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { 800f33c: b580 push {r7, lr} 800f33e: b084 sub sp, #16 800f340: af00 add r7, sp, #0 800f342: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the RNG handle allocation */ if (hrng == NULL) 800f344: 687b ldr r3, [r7, #4] 800f346: 2b00 cmp r3, #0 800f348: d101 bne.n 800f34e { return HAL_ERROR; 800f34a: 2301 movs r3, #1 800f34c: e054 b.n 800f3f8 /* Init the low level hardware */ hrng->MspInitCallback(hrng); } #else if (hrng->State == HAL_RNG_STATE_RESET) 800f34e: 687b ldr r3, [r7, #4] 800f350: 7a5b ldrb r3, [r3, #9] 800f352: b2db uxtb r3, r3 800f354: 2b00 cmp r3, #0 800f356: d105 bne.n 800f364 { /* Allocate lock resource and initialize it */ hrng->Lock = HAL_UNLOCKED; 800f358: 687b ldr r3, [r7, #4] 800f35a: 2200 movs r2, #0 800f35c: 721a strb r2, [r3, #8] /* Init the low level hardware */ HAL_RNG_MspInit(hrng); 800f35e: 6878 ldr r0, [r7, #4] 800f360: f7f4 ff30 bl 80041c4 } #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; 800f364: 687b ldr r3, [r7, #4] 800f366: 2202 movs r2, #2 800f368: 725a strb r2, [r3, #9] } } } #else /* Clock Error Detection Configuration */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection); 800f36a: 687b ldr r3, [r7, #4] 800f36c: 681b ldr r3, [r3, #0] 800f36e: 681b ldr r3, [r3, #0] 800f370: f023 0120 bic.w r1, r3, #32 800f374: 687b ldr r3, [r7, #4] 800f376: 685a ldr r2, [r3, #4] 800f378: 687b ldr r3, [r7, #4] 800f37a: 681b ldr r3, [r3, #0] 800f37c: 430a orrs r2, r1 800f37e: 601a str r2, [r3, #0] #endif /* RNG_CR_CONDRST */ /* Enable the RNG Peripheral */ __HAL_RNG_ENABLE(hrng); 800f380: 687b ldr r3, [r7, #4] 800f382: 681b ldr r3, [r3, #0] 800f384: 681a ldr r2, [r3, #0] 800f386: 687b ldr r3, [r7, #4] 800f388: 681b ldr r3, [r3, #0] 800f38a: f042 0204 orr.w r2, r2, #4 800f38e: 601a str r2, [r3, #0] /* verify that no seed error */ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) 800f390: 687b ldr r3, [r7, #4] 800f392: 681b ldr r3, [r3, #0] 800f394: 685b ldr r3, [r3, #4] 800f396: f003 0340 and.w r3, r3, #64 @ 0x40 800f39a: 2b40 cmp r3, #64 @ 0x40 800f39c: d104 bne.n 800f3a8 { hrng->State = HAL_RNG_STATE_ERROR; 800f39e: 687b ldr r3, [r7, #4] 800f3a0: 2204 movs r2, #4 800f3a2: 725a strb r2, [r3, #9] return HAL_ERROR; 800f3a4: 2301 movs r3, #1 800f3a6: e027 b.n 800f3f8 } /* Get tick */ tickstart = HAL_GetTick(); 800f3a8: f7f6 fd28 bl 8005dfc 800f3ac: 60f8 str r0, [r7, #12] /* Check if data register contains valid random data */ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f3ae: e015 b.n 800f3dc { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) 800f3b0: f7f6 fd24 bl 8005dfc 800f3b4: 4602 mov r2, r0 800f3b6: 68fb ldr r3, [r7, #12] 800f3b8: 1ad3 subs r3, r2, r3 800f3ba: 2b02 cmp r3, #2 800f3bc: d90e bls.n 800f3dc { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f3be: 687b ldr r3, [r7, #4] 800f3c0: 681b ldr r3, [r3, #0] 800f3c2: 685b ldr r3, [r3, #4] 800f3c4: f003 0304 and.w r3, r3, #4 800f3c8: 2b04 cmp r3, #4 800f3ca: d107 bne.n 800f3dc { hrng->State = HAL_RNG_STATE_ERROR; 800f3cc: 687b ldr r3, [r7, #4] 800f3ce: 2204 movs r2, #4 800f3d0: 725a strb r2, [r3, #9] hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; 800f3d2: 687b ldr r3, [r7, #4] 800f3d4: 2202 movs r2, #2 800f3d6: 60da str r2, [r3, #12] return HAL_ERROR; 800f3d8: 2301 movs r3, #1 800f3da: e00d b.n 800f3f8 while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f3dc: 687b ldr r3, [r7, #4] 800f3de: 681b ldr r3, [r3, #0] 800f3e0: 685b ldr r3, [r3, #4] 800f3e2: f003 0304 and.w r3, r3, #4 800f3e6: 2b04 cmp r3, #4 800f3e8: d0e2 beq.n 800f3b0 } } } /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; 800f3ea: 687b ldr r3, [r7, #4] 800f3ec: 2201 movs r2, #1 800f3ee: 725a strb r2, [r3, #9] /* Initialise the error code */ hrng->ErrorCode = HAL_RNG_ERROR_NONE; 800f3f0: 687b ldr r3, [r7, #4] 800f3f2: 2200 movs r2, #0 800f3f4: 60da str r2, [r3, #12] /* Return function status */ return HAL_OK; 800f3f6: 2300 movs r3, #0 } 800f3f8: 4618 mov r0, r3 800f3fa: 3710 adds r7, #16 800f3fc: 46bd mov sp, r7 800f3fe: bd80 pop {r7, pc} 0800f400 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 800f400: b580 push {r7, lr} 800f402: b082 sub sp, #8 800f404: af00 add r7, sp, #0 800f406: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800f408: 687b ldr r3, [r7, #4] 800f40a: 2b00 cmp r3, #0 800f40c: d101 bne.n 800f412 { return HAL_ERROR; 800f40e: 2301 movs r3, #1 800f410: e049 b.n 800f4a6 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800f412: 687b ldr r3, [r7, #4] 800f414: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f418: b2db uxtb r3, r3 800f41a: 2b00 cmp r3, #0 800f41c: d106 bne.n 800f42c { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800f41e: 687b ldr r3, [r7, #4] 800f420: 2200 movs r2, #0 800f422: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800f426: 6878 ldr r0, [r7, #4] 800f428: f7f4 ff40 bl 80042ac #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f42c: 687b ldr r3, [r7, #4] 800f42e: 2202 movs r2, #2 800f430: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800f434: 687b ldr r3, [r7, #4] 800f436: 681a ldr r2, [r3, #0] 800f438: 687b ldr r3, [r7, #4] 800f43a: 3304 adds r3, #4 800f43c: 4619 mov r1, r3 800f43e: 4610 mov r0, r2 800f440: f001 f918 bl 8010674 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800f444: 687b ldr r3, [r7, #4] 800f446: 2201 movs r2, #1 800f448: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f44c: 687b ldr r3, [r7, #4] 800f44e: 2201 movs r2, #1 800f450: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f454: 687b ldr r3, [r7, #4] 800f456: 2201 movs r2, #1 800f458: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f45c: 687b ldr r3, [r7, #4] 800f45e: 2201 movs r2, #1 800f460: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f464: 687b ldr r3, [r7, #4] 800f466: 2201 movs r2, #1 800f468: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f46c: 687b ldr r3, [r7, #4] 800f46e: 2201 movs r2, #1 800f470: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f474: 687b ldr r3, [r7, #4] 800f476: 2201 movs r2, #1 800f478: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f47c: 687b ldr r3, [r7, #4] 800f47e: 2201 movs r2, #1 800f480: f883 2044 strb.w r2, [r3, #68] @ 0x44 800f484: 687b ldr r3, [r7, #4] 800f486: 2201 movs r2, #1 800f488: f883 2045 strb.w r2, [r3, #69] @ 0x45 800f48c: 687b ldr r3, [r7, #4] 800f48e: 2201 movs r2, #1 800f490: f883 2046 strb.w r2, [r3, #70] @ 0x46 800f494: 687b ldr r3, [r7, #4] 800f496: 2201 movs r2, #1 800f498: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800f49c: 687b ldr r3, [r7, #4] 800f49e: 2201 movs r2, #1 800f4a0: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800f4a4: 2300 movs r3, #0 } 800f4a6: 4618 mov r0, r3 800f4a8: 3708 adds r7, #8 800f4aa: 46bd mov sp, r7 800f4ac: bd80 pop {r7, pc} ... 0800f4b0 : * @brief Starts the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { 800f4b0: b480 push {r7} 800f4b2: b085 sub sp, #20 800f4b4: af00 add r7, sp, #0 800f4b6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800f4b8: 687b ldr r3, [r7, #4] 800f4ba: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f4be: b2db uxtb r3, r3 800f4c0: 2b01 cmp r3, #1 800f4c2: d001 beq.n 800f4c8 { return HAL_ERROR; 800f4c4: 2301 movs r3, #1 800f4c6: e04c b.n 800f562 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f4c8: 687b ldr r3, [r7, #4] 800f4ca: 2202 movs r2, #2 800f4cc: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f4d0: 687b ldr r3, [r7, #4] 800f4d2: 681b ldr r3, [r3, #0] 800f4d4: 4a26 ldr r2, [pc, #152] @ (800f570 ) 800f4d6: 4293 cmp r3, r2 800f4d8: d022 beq.n 800f520 800f4da: 687b ldr r3, [r7, #4] 800f4dc: 681b ldr r3, [r3, #0] 800f4de: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f4e2: d01d beq.n 800f520 800f4e4: 687b ldr r3, [r7, #4] 800f4e6: 681b ldr r3, [r3, #0] 800f4e8: 4a22 ldr r2, [pc, #136] @ (800f574 ) 800f4ea: 4293 cmp r3, r2 800f4ec: d018 beq.n 800f520 800f4ee: 687b ldr r3, [r7, #4] 800f4f0: 681b ldr r3, [r3, #0] 800f4f2: 4a21 ldr r2, [pc, #132] @ (800f578 ) 800f4f4: 4293 cmp r3, r2 800f4f6: d013 beq.n 800f520 800f4f8: 687b ldr r3, [r7, #4] 800f4fa: 681b ldr r3, [r3, #0] 800f4fc: 4a1f ldr r2, [pc, #124] @ (800f57c ) 800f4fe: 4293 cmp r3, r2 800f500: d00e beq.n 800f520 800f502: 687b ldr r3, [r7, #4] 800f504: 681b ldr r3, [r3, #0] 800f506: 4a1e ldr r2, [pc, #120] @ (800f580 ) 800f508: 4293 cmp r3, r2 800f50a: d009 beq.n 800f520 800f50c: 687b ldr r3, [r7, #4] 800f50e: 681b ldr r3, [r3, #0] 800f510: 4a1c ldr r2, [pc, #112] @ (800f584 ) 800f512: 4293 cmp r3, r2 800f514: d004 beq.n 800f520 800f516: 687b ldr r3, [r7, #4] 800f518: 681b ldr r3, [r3, #0] 800f51a: 4a1b ldr r2, [pc, #108] @ (800f588 ) 800f51c: 4293 cmp r3, r2 800f51e: d115 bne.n 800f54c { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f520: 687b ldr r3, [r7, #4] 800f522: 681b ldr r3, [r3, #0] 800f524: 689a ldr r2, [r3, #8] 800f526: 4b19 ldr r3, [pc, #100] @ (800f58c ) 800f528: 4013 ands r3, r2 800f52a: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f52c: 68fb ldr r3, [r7, #12] 800f52e: 2b06 cmp r3, #6 800f530: d015 beq.n 800f55e 800f532: 68fb ldr r3, [r7, #12] 800f534: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f538: d011 beq.n 800f55e { __HAL_TIM_ENABLE(htim); 800f53a: 687b ldr r3, [r7, #4] 800f53c: 681b ldr r3, [r3, #0] 800f53e: 681a ldr r2, [r3, #0] 800f540: 687b ldr r3, [r7, #4] 800f542: 681b ldr r3, [r3, #0] 800f544: f042 0201 orr.w r2, r2, #1 800f548: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f54a: e008 b.n 800f55e } } else { __HAL_TIM_ENABLE(htim); 800f54c: 687b ldr r3, [r7, #4] 800f54e: 681b ldr r3, [r3, #0] 800f550: 681a ldr r2, [r3, #0] 800f552: 687b ldr r3, [r7, #4] 800f554: 681b ldr r3, [r3, #0] 800f556: f042 0201 orr.w r2, r2, #1 800f55a: 601a str r2, [r3, #0] 800f55c: e000 b.n 800f560 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f55e: bf00 nop } /* Return function status */ return HAL_OK; 800f560: 2300 movs r3, #0 } 800f562: 4618 mov r0, r3 800f564: 3714 adds r7, #20 800f566: 46bd mov sp, r7 800f568: f85d 7b04 ldr.w r7, [sp], #4 800f56c: 4770 bx lr 800f56e: bf00 nop 800f570: 40010000 .word 0x40010000 800f574: 40000400 .word 0x40000400 800f578: 40000800 .word 0x40000800 800f57c: 40000c00 .word 0x40000c00 800f580: 40010400 .word 0x40010400 800f584: 40001800 .word 0x40001800 800f588: 40014000 .word 0x40014000 800f58c: 00010007 .word 0x00010007 0800f590 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 800f590: b480 push {r7} 800f592: b085 sub sp, #20 800f594: af00 add r7, sp, #0 800f596: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800f598: 687b ldr r3, [r7, #4] 800f59a: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f59e: b2db uxtb r3, r3 800f5a0: 2b01 cmp r3, #1 800f5a2: d001 beq.n 800f5a8 { return HAL_ERROR; 800f5a4: 2301 movs r3, #1 800f5a6: e054 b.n 800f652 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f5a8: 687b ldr r3, [r7, #4] 800f5aa: 2202 movs r2, #2 800f5ac: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 800f5b0: 687b ldr r3, [r7, #4] 800f5b2: 681b ldr r3, [r3, #0] 800f5b4: 68da ldr r2, [r3, #12] 800f5b6: 687b ldr r3, [r7, #4] 800f5b8: 681b ldr r3, [r3, #0] 800f5ba: f042 0201 orr.w r2, r2, #1 800f5be: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f5c0: 687b ldr r3, [r7, #4] 800f5c2: 681b ldr r3, [r3, #0] 800f5c4: 4a26 ldr r2, [pc, #152] @ (800f660 ) 800f5c6: 4293 cmp r3, r2 800f5c8: d022 beq.n 800f610 800f5ca: 687b ldr r3, [r7, #4] 800f5cc: 681b ldr r3, [r3, #0] 800f5ce: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f5d2: d01d beq.n 800f610 800f5d4: 687b ldr r3, [r7, #4] 800f5d6: 681b ldr r3, [r3, #0] 800f5d8: 4a22 ldr r2, [pc, #136] @ (800f664 ) 800f5da: 4293 cmp r3, r2 800f5dc: d018 beq.n 800f610 800f5de: 687b ldr r3, [r7, #4] 800f5e0: 681b ldr r3, [r3, #0] 800f5e2: 4a21 ldr r2, [pc, #132] @ (800f668 ) 800f5e4: 4293 cmp r3, r2 800f5e6: d013 beq.n 800f610 800f5e8: 687b ldr r3, [r7, #4] 800f5ea: 681b ldr r3, [r3, #0] 800f5ec: 4a1f ldr r2, [pc, #124] @ (800f66c ) 800f5ee: 4293 cmp r3, r2 800f5f0: d00e beq.n 800f610 800f5f2: 687b ldr r3, [r7, #4] 800f5f4: 681b ldr r3, [r3, #0] 800f5f6: 4a1e ldr r2, [pc, #120] @ (800f670 ) 800f5f8: 4293 cmp r3, r2 800f5fa: d009 beq.n 800f610 800f5fc: 687b ldr r3, [r7, #4] 800f5fe: 681b ldr r3, [r3, #0] 800f600: 4a1c ldr r2, [pc, #112] @ (800f674 ) 800f602: 4293 cmp r3, r2 800f604: d004 beq.n 800f610 800f606: 687b ldr r3, [r7, #4] 800f608: 681b ldr r3, [r3, #0] 800f60a: 4a1b ldr r2, [pc, #108] @ (800f678 ) 800f60c: 4293 cmp r3, r2 800f60e: d115 bne.n 800f63c { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f610: 687b ldr r3, [r7, #4] 800f612: 681b ldr r3, [r3, #0] 800f614: 689a ldr r2, [r3, #8] 800f616: 4b19 ldr r3, [pc, #100] @ (800f67c ) 800f618: 4013 ands r3, r2 800f61a: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f61c: 68fb ldr r3, [r7, #12] 800f61e: 2b06 cmp r3, #6 800f620: d015 beq.n 800f64e 800f622: 68fb ldr r3, [r7, #12] 800f624: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f628: d011 beq.n 800f64e { __HAL_TIM_ENABLE(htim); 800f62a: 687b ldr r3, [r7, #4] 800f62c: 681b ldr r3, [r3, #0] 800f62e: 681a ldr r2, [r3, #0] 800f630: 687b ldr r3, [r7, #4] 800f632: 681b ldr r3, [r3, #0] 800f634: f042 0201 orr.w r2, r2, #1 800f638: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f63a: e008 b.n 800f64e } } else { __HAL_TIM_ENABLE(htim); 800f63c: 687b ldr r3, [r7, #4] 800f63e: 681b ldr r3, [r3, #0] 800f640: 681a ldr r2, [r3, #0] 800f642: 687b ldr r3, [r7, #4] 800f644: 681b ldr r3, [r3, #0] 800f646: f042 0201 orr.w r2, r2, #1 800f64a: 601a str r2, [r3, #0] 800f64c: e000 b.n 800f650 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f64e: bf00 nop } /* Return function status */ return HAL_OK; 800f650: 2300 movs r3, #0 } 800f652: 4618 mov r0, r3 800f654: 3714 adds r7, #20 800f656: 46bd mov sp, r7 800f658: f85d 7b04 ldr.w r7, [sp], #4 800f65c: 4770 bx lr 800f65e: bf00 nop 800f660: 40010000 .word 0x40010000 800f664: 40000400 .word 0x40000400 800f668: 40000800 .word 0x40000800 800f66c: 40000c00 .word 0x40000c00 800f670: 40010400 .word 0x40010400 800f674: 40001800 .word 0x40001800 800f678: 40014000 .word 0x40014000 800f67c: 00010007 .word 0x00010007 0800f680 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 800f680: b580 push {r7, lr} 800f682: b082 sub sp, #8 800f684: af00 add r7, sp, #0 800f686: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800f688: 687b ldr r3, [r7, #4] 800f68a: 2b00 cmp r3, #0 800f68c: d101 bne.n 800f692 { return HAL_ERROR; 800f68e: 2301 movs r3, #1 800f690: e049 b.n 800f726 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800f692: 687b ldr r3, [r7, #4] 800f694: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f698: b2db uxtb r3, r3 800f69a: 2b00 cmp r3, #0 800f69c: d106 bne.n 800f6ac { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800f69e: 687b ldr r3, [r7, #4] 800f6a0: 2200 movs r2, #0 800f6a2: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 800f6a6: 6878 ldr r0, [r7, #4] 800f6a8: f7f4 fdc6 bl 8004238 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f6ac: 687b ldr r3, [r7, #4] 800f6ae: 2202 movs r2, #2 800f6b0: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800f6b4: 687b ldr r3, [r7, #4] 800f6b6: 681a ldr r2, [r3, #0] 800f6b8: 687b ldr r3, [r7, #4] 800f6ba: 3304 adds r3, #4 800f6bc: 4619 mov r1, r3 800f6be: 4610 mov r0, r2 800f6c0: f000 ffd8 bl 8010674 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800f6c4: 687b ldr r3, [r7, #4] 800f6c6: 2201 movs r2, #1 800f6c8: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f6cc: 687b ldr r3, [r7, #4] 800f6ce: 2201 movs r2, #1 800f6d0: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f6d4: 687b ldr r3, [r7, #4] 800f6d6: 2201 movs r2, #1 800f6d8: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f6dc: 687b ldr r3, [r7, #4] 800f6de: 2201 movs r2, #1 800f6e0: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f6e4: 687b ldr r3, [r7, #4] 800f6e6: 2201 movs r2, #1 800f6e8: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f6ec: 687b ldr r3, [r7, #4] 800f6ee: 2201 movs r2, #1 800f6f0: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f6f4: 687b ldr r3, [r7, #4] 800f6f6: 2201 movs r2, #1 800f6f8: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f6fc: 687b ldr r3, [r7, #4] 800f6fe: 2201 movs r2, #1 800f700: f883 2044 strb.w r2, [r3, #68] @ 0x44 800f704: 687b ldr r3, [r7, #4] 800f706: 2201 movs r2, #1 800f708: f883 2045 strb.w r2, [r3, #69] @ 0x45 800f70c: 687b ldr r3, [r7, #4] 800f70e: 2201 movs r2, #1 800f710: f883 2046 strb.w r2, [r3, #70] @ 0x46 800f714: 687b ldr r3, [r7, #4] 800f716: 2201 movs r2, #1 800f718: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800f71c: 687b ldr r3, [r7, #4] 800f71e: 2201 movs r2, #1 800f720: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800f724: 2300 movs r3, #0 } 800f726: 4618 mov r0, r3 800f728: 3708 adds r7, #8 800f72a: 46bd mov sp, r7 800f72c: bd80 pop {r7, pc} ... 0800f730 : * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 800f730: b580 push {r7, lr} 800f732: b084 sub sp, #16 800f734: af00 add r7, sp, #0 800f736: 6078 str r0, [r7, #4] 800f738: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 800f73a: 683b ldr r3, [r7, #0] 800f73c: 2b00 cmp r3, #0 800f73e: d109 bne.n 800f754 800f740: 687b ldr r3, [r7, #4] 800f742: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800f746: b2db uxtb r3, r3 800f748: 2b01 cmp r3, #1 800f74a: bf14 ite ne 800f74c: 2301 movne r3, #1 800f74e: 2300 moveq r3, #0 800f750: b2db uxtb r3, r3 800f752: e03c b.n 800f7ce 800f754: 683b ldr r3, [r7, #0] 800f756: 2b04 cmp r3, #4 800f758: d109 bne.n 800f76e 800f75a: 687b ldr r3, [r7, #4] 800f75c: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800f760: b2db uxtb r3, r3 800f762: 2b01 cmp r3, #1 800f764: bf14 ite ne 800f766: 2301 movne r3, #1 800f768: 2300 moveq r3, #0 800f76a: b2db uxtb r3, r3 800f76c: e02f b.n 800f7ce 800f76e: 683b ldr r3, [r7, #0] 800f770: 2b08 cmp r3, #8 800f772: d109 bne.n 800f788 800f774: 687b ldr r3, [r7, #4] 800f776: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800f77a: b2db uxtb r3, r3 800f77c: 2b01 cmp r3, #1 800f77e: bf14 ite ne 800f780: 2301 movne r3, #1 800f782: 2300 moveq r3, #0 800f784: b2db uxtb r3, r3 800f786: e022 b.n 800f7ce 800f788: 683b ldr r3, [r7, #0] 800f78a: 2b0c cmp r3, #12 800f78c: d109 bne.n 800f7a2 800f78e: 687b ldr r3, [r7, #4] 800f790: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800f794: b2db uxtb r3, r3 800f796: 2b01 cmp r3, #1 800f798: bf14 ite ne 800f79a: 2301 movne r3, #1 800f79c: 2300 moveq r3, #0 800f79e: b2db uxtb r3, r3 800f7a0: e015 b.n 800f7ce 800f7a2: 683b ldr r3, [r7, #0] 800f7a4: 2b10 cmp r3, #16 800f7a6: d109 bne.n 800f7bc 800f7a8: 687b ldr r3, [r7, #4] 800f7aa: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800f7ae: b2db uxtb r3, r3 800f7b0: 2b01 cmp r3, #1 800f7b2: bf14 ite ne 800f7b4: 2301 movne r3, #1 800f7b6: 2300 moveq r3, #0 800f7b8: b2db uxtb r3, r3 800f7ba: e008 b.n 800f7ce 800f7bc: 687b ldr r3, [r7, #4] 800f7be: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800f7c2: b2db uxtb r3, r3 800f7c4: 2b01 cmp r3, #1 800f7c6: bf14 ite ne 800f7c8: 2301 movne r3, #1 800f7ca: 2300 moveq r3, #0 800f7cc: b2db uxtb r3, r3 800f7ce: 2b00 cmp r3, #0 800f7d0: d001 beq.n 800f7d6 { return HAL_ERROR; 800f7d2: 2301 movs r3, #1 800f7d4: e0a1 b.n 800f91a } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800f7d6: 683b ldr r3, [r7, #0] 800f7d8: 2b00 cmp r3, #0 800f7da: d104 bne.n 800f7e6 800f7dc: 687b ldr r3, [r7, #4] 800f7de: 2202 movs r2, #2 800f7e0: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f7e4: e023 b.n 800f82e 800f7e6: 683b ldr r3, [r7, #0] 800f7e8: 2b04 cmp r3, #4 800f7ea: d104 bne.n 800f7f6 800f7ec: 687b ldr r3, [r7, #4] 800f7ee: 2202 movs r2, #2 800f7f0: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f7f4: e01b b.n 800f82e 800f7f6: 683b ldr r3, [r7, #0] 800f7f8: 2b08 cmp r3, #8 800f7fa: d104 bne.n 800f806 800f7fc: 687b ldr r3, [r7, #4] 800f7fe: 2202 movs r2, #2 800f800: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f804: e013 b.n 800f82e 800f806: 683b ldr r3, [r7, #0] 800f808: 2b0c cmp r3, #12 800f80a: d104 bne.n 800f816 800f80c: 687b ldr r3, [r7, #4] 800f80e: 2202 movs r2, #2 800f810: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f814: e00b b.n 800f82e 800f816: 683b ldr r3, [r7, #0] 800f818: 2b10 cmp r3, #16 800f81a: d104 bne.n 800f826 800f81c: 687b ldr r3, [r7, #4] 800f81e: 2202 movs r2, #2 800f820: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f824: e003 b.n 800f82e 800f826: 687b ldr r3, [r7, #4] 800f828: 2202 movs r2, #2 800f82a: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 800f82e: 687b ldr r3, [r7, #4] 800f830: 681b ldr r3, [r3, #0] 800f832: 2201 movs r2, #1 800f834: 6839 ldr r1, [r7, #0] 800f836: 4618 mov r0, r3 800f838: f001 fc60 bl 80110fc if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800f83c: 687b ldr r3, [r7, #4] 800f83e: 681b ldr r3, [r3, #0] 800f840: 4a38 ldr r2, [pc, #224] @ (800f924 ) 800f842: 4293 cmp r3, r2 800f844: d013 beq.n 800f86e 800f846: 687b ldr r3, [r7, #4] 800f848: 681b ldr r3, [r3, #0] 800f84a: 4a37 ldr r2, [pc, #220] @ (800f928 ) 800f84c: 4293 cmp r3, r2 800f84e: d00e beq.n 800f86e 800f850: 687b ldr r3, [r7, #4] 800f852: 681b ldr r3, [r3, #0] 800f854: 4a35 ldr r2, [pc, #212] @ (800f92c ) 800f856: 4293 cmp r3, r2 800f858: d009 beq.n 800f86e 800f85a: 687b ldr r3, [r7, #4] 800f85c: 681b ldr r3, [r3, #0] 800f85e: 4a34 ldr r2, [pc, #208] @ (800f930 ) 800f860: 4293 cmp r3, r2 800f862: d004 beq.n 800f86e 800f864: 687b ldr r3, [r7, #4] 800f866: 681b ldr r3, [r3, #0] 800f868: 4a32 ldr r2, [pc, #200] @ (800f934 ) 800f86a: 4293 cmp r3, r2 800f86c: d101 bne.n 800f872 800f86e: 2301 movs r3, #1 800f870: e000 b.n 800f874 800f872: 2300 movs r3, #0 800f874: 2b00 cmp r3, #0 800f876: d007 beq.n 800f888 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 800f878: 687b ldr r3, [r7, #4] 800f87a: 681b ldr r3, [r3, #0] 800f87c: 6c5a ldr r2, [r3, #68] @ 0x44 800f87e: 687b ldr r3, [r7, #4] 800f880: 681b ldr r3, [r3, #0] 800f882: f442 4200 orr.w r2, r2, #32768 @ 0x8000 800f886: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f888: 687b ldr r3, [r7, #4] 800f88a: 681b ldr r3, [r3, #0] 800f88c: 4a25 ldr r2, [pc, #148] @ (800f924 ) 800f88e: 4293 cmp r3, r2 800f890: d022 beq.n 800f8d8 800f892: 687b ldr r3, [r7, #4] 800f894: 681b ldr r3, [r3, #0] 800f896: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f89a: d01d beq.n 800f8d8 800f89c: 687b ldr r3, [r7, #4] 800f89e: 681b ldr r3, [r3, #0] 800f8a0: 4a25 ldr r2, [pc, #148] @ (800f938 ) 800f8a2: 4293 cmp r3, r2 800f8a4: d018 beq.n 800f8d8 800f8a6: 687b ldr r3, [r7, #4] 800f8a8: 681b ldr r3, [r3, #0] 800f8aa: 4a24 ldr r2, [pc, #144] @ (800f93c ) 800f8ac: 4293 cmp r3, r2 800f8ae: d013 beq.n 800f8d8 800f8b0: 687b ldr r3, [r7, #4] 800f8b2: 681b ldr r3, [r3, #0] 800f8b4: 4a22 ldr r2, [pc, #136] @ (800f940 ) 800f8b6: 4293 cmp r3, r2 800f8b8: d00e beq.n 800f8d8 800f8ba: 687b ldr r3, [r7, #4] 800f8bc: 681b ldr r3, [r3, #0] 800f8be: 4a1a ldr r2, [pc, #104] @ (800f928 ) 800f8c0: 4293 cmp r3, r2 800f8c2: d009 beq.n 800f8d8 800f8c4: 687b ldr r3, [r7, #4] 800f8c6: 681b ldr r3, [r3, #0] 800f8c8: 4a1e ldr r2, [pc, #120] @ (800f944 ) 800f8ca: 4293 cmp r3, r2 800f8cc: d004 beq.n 800f8d8 800f8ce: 687b ldr r3, [r7, #4] 800f8d0: 681b ldr r3, [r3, #0] 800f8d2: 4a16 ldr r2, [pc, #88] @ (800f92c ) 800f8d4: 4293 cmp r3, r2 800f8d6: d115 bne.n 800f904 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f8d8: 687b ldr r3, [r7, #4] 800f8da: 681b ldr r3, [r3, #0] 800f8dc: 689a ldr r2, [r3, #8] 800f8de: 4b1a ldr r3, [pc, #104] @ (800f948 ) 800f8e0: 4013 ands r3, r2 800f8e2: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f8e4: 68fb ldr r3, [r7, #12] 800f8e6: 2b06 cmp r3, #6 800f8e8: d015 beq.n 800f916 800f8ea: 68fb ldr r3, [r7, #12] 800f8ec: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f8f0: d011 beq.n 800f916 { __HAL_TIM_ENABLE(htim); 800f8f2: 687b ldr r3, [r7, #4] 800f8f4: 681b ldr r3, [r3, #0] 800f8f6: 681a ldr r2, [r3, #0] 800f8f8: 687b ldr r3, [r7, #4] 800f8fa: 681b ldr r3, [r3, #0] 800f8fc: f042 0201 orr.w r2, r2, #1 800f900: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f902: e008 b.n 800f916 } } else { __HAL_TIM_ENABLE(htim); 800f904: 687b ldr r3, [r7, #4] 800f906: 681b ldr r3, [r3, #0] 800f908: 681a ldr r2, [r3, #0] 800f90a: 687b ldr r3, [r7, #4] 800f90c: 681b ldr r3, [r3, #0] 800f90e: f042 0201 orr.w r2, r2, #1 800f912: 601a str r2, [r3, #0] 800f914: e000 b.n 800f918 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f916: bf00 nop } /* Return function status */ return HAL_OK; 800f918: 2300 movs r3, #0 } 800f91a: 4618 mov r0, r3 800f91c: 3710 adds r7, #16 800f91e: 46bd mov sp, r7 800f920: bd80 pop {r7, pc} 800f922: bf00 nop 800f924: 40010000 .word 0x40010000 800f928: 40010400 .word 0x40010400 800f92c: 40014000 .word 0x40014000 800f930: 40014400 .word 0x40014400 800f934: 40014800 .word 0x40014800 800f938: 40000400 .word 0x40000400 800f93c: 40000800 .word 0x40000800 800f940: 40000c00 .word 0x40000c00 800f944: 40001800 .word 0x40001800 800f948: 00010007 .word 0x00010007 0800f94c : * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { 800f94c: b580 push {r7, lr} 800f94e: b082 sub sp, #8 800f950: af00 add r7, sp, #0 800f952: 6078 str r0, [r7, #4] 800f954: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 800f956: 687b ldr r3, [r7, #4] 800f958: 681b ldr r3, [r3, #0] 800f95a: 2200 movs r2, #0 800f95c: 6839 ldr r1, [r7, #0] 800f95e: 4618 mov r0, r3 800f960: f001 fbcc bl 80110fc if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800f964: 687b ldr r3, [r7, #4] 800f966: 681b ldr r3, [r3, #0] 800f968: 4a3e ldr r2, [pc, #248] @ (800fa64 ) 800f96a: 4293 cmp r3, r2 800f96c: d013 beq.n 800f996 800f96e: 687b ldr r3, [r7, #4] 800f970: 681b ldr r3, [r3, #0] 800f972: 4a3d ldr r2, [pc, #244] @ (800fa68 ) 800f974: 4293 cmp r3, r2 800f976: d00e beq.n 800f996 800f978: 687b ldr r3, [r7, #4] 800f97a: 681b ldr r3, [r3, #0] 800f97c: 4a3b ldr r2, [pc, #236] @ (800fa6c ) 800f97e: 4293 cmp r3, r2 800f980: d009 beq.n 800f996 800f982: 687b ldr r3, [r7, #4] 800f984: 681b ldr r3, [r3, #0] 800f986: 4a3a ldr r2, [pc, #232] @ (800fa70 ) 800f988: 4293 cmp r3, r2 800f98a: d004 beq.n 800f996 800f98c: 687b ldr r3, [r7, #4] 800f98e: 681b ldr r3, [r3, #0] 800f990: 4a38 ldr r2, [pc, #224] @ (800fa74 ) 800f992: 4293 cmp r3, r2 800f994: d101 bne.n 800f99a 800f996: 2301 movs r3, #1 800f998: e000 b.n 800f99c 800f99a: 2300 movs r3, #0 800f99c: 2b00 cmp r3, #0 800f99e: d017 beq.n 800f9d0 { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); 800f9a0: 687b ldr r3, [r7, #4] 800f9a2: 681b ldr r3, [r3, #0] 800f9a4: 6a1a ldr r2, [r3, #32] 800f9a6: f241 1311 movw r3, #4369 @ 0x1111 800f9aa: 4013 ands r3, r2 800f9ac: 2b00 cmp r3, #0 800f9ae: d10f bne.n 800f9d0 800f9b0: 687b ldr r3, [r7, #4] 800f9b2: 681b ldr r3, [r3, #0] 800f9b4: 6a1a ldr r2, [r3, #32] 800f9b6: f240 4344 movw r3, #1092 @ 0x444 800f9ba: 4013 ands r3, r2 800f9bc: 2b00 cmp r3, #0 800f9be: d107 bne.n 800f9d0 800f9c0: 687b ldr r3, [r7, #4] 800f9c2: 681b ldr r3, [r3, #0] 800f9c4: 6c5a ldr r2, [r3, #68] @ 0x44 800f9c6: 687b ldr r3, [r7, #4] 800f9c8: 681b ldr r3, [r3, #0] 800f9ca: f422 4200 bic.w r2, r2, #32768 @ 0x8000 800f9ce: 645a str r2, [r3, #68] @ 0x44 } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); 800f9d0: 687b ldr r3, [r7, #4] 800f9d2: 681b ldr r3, [r3, #0] 800f9d4: 6a1a ldr r2, [r3, #32] 800f9d6: f241 1311 movw r3, #4369 @ 0x1111 800f9da: 4013 ands r3, r2 800f9dc: 2b00 cmp r3, #0 800f9de: d10f bne.n 800fa00 800f9e0: 687b ldr r3, [r7, #4] 800f9e2: 681b ldr r3, [r3, #0] 800f9e4: 6a1a ldr r2, [r3, #32] 800f9e6: f240 4344 movw r3, #1092 @ 0x444 800f9ea: 4013 ands r3, r2 800f9ec: 2b00 cmp r3, #0 800f9ee: d107 bne.n 800fa00 800f9f0: 687b ldr r3, [r7, #4] 800f9f2: 681b ldr r3, [r3, #0] 800f9f4: 681a ldr r2, [r3, #0] 800f9f6: 687b ldr r3, [r7, #4] 800f9f8: 681b ldr r3, [r3, #0] 800f9fa: f022 0201 bic.w r2, r2, #1 800f9fe: 601a str r2, [r3, #0] /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); 800fa00: 683b ldr r3, [r7, #0] 800fa02: 2b00 cmp r3, #0 800fa04: d104 bne.n 800fa10 800fa06: 687b ldr r3, [r7, #4] 800fa08: 2201 movs r2, #1 800fa0a: f883 203e strb.w r2, [r3, #62] @ 0x3e 800fa0e: e023 b.n 800fa58 800fa10: 683b ldr r3, [r7, #0] 800fa12: 2b04 cmp r3, #4 800fa14: d104 bne.n 800fa20 800fa16: 687b ldr r3, [r7, #4] 800fa18: 2201 movs r2, #1 800fa1a: f883 203f strb.w r2, [r3, #63] @ 0x3f 800fa1e: e01b b.n 800fa58 800fa20: 683b ldr r3, [r7, #0] 800fa22: 2b08 cmp r3, #8 800fa24: d104 bne.n 800fa30 800fa26: 687b ldr r3, [r7, #4] 800fa28: 2201 movs r2, #1 800fa2a: f883 2040 strb.w r2, [r3, #64] @ 0x40 800fa2e: e013 b.n 800fa58 800fa30: 683b ldr r3, [r7, #0] 800fa32: 2b0c cmp r3, #12 800fa34: d104 bne.n 800fa40 800fa36: 687b ldr r3, [r7, #4] 800fa38: 2201 movs r2, #1 800fa3a: f883 2041 strb.w r2, [r3, #65] @ 0x41 800fa3e: e00b b.n 800fa58 800fa40: 683b ldr r3, [r7, #0] 800fa42: 2b10 cmp r3, #16 800fa44: d104 bne.n 800fa50 800fa46: 687b ldr r3, [r7, #4] 800fa48: 2201 movs r2, #1 800fa4a: f883 2042 strb.w r2, [r3, #66] @ 0x42 800fa4e: e003 b.n 800fa58 800fa50: 687b ldr r3, [r7, #4] 800fa52: 2201 movs r2, #1 800fa54: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Return function status */ return HAL_OK; 800fa58: 2300 movs r3, #0 } 800fa5a: 4618 mov r0, r3 800fa5c: 3708 adds r7, #8 800fa5e: 46bd mov sp, r7 800fa60: bd80 pop {r7, pc} 800fa62: bf00 nop 800fa64: 40010000 .word 0x40010000 800fa68: 40010400 .word 0x40010400 800fa6c: 40014000 .word 0x40014000 800fa70: 40014400 .word 0x40014400 800fa74: 40014800 .word 0x40014800 0800fa78 : * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) { 800fa78: b580 push {r7, lr} 800fa7a: b082 sub sp, #8 800fa7c: af00 add r7, sp, #0 800fa7e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800fa80: 687b ldr r3, [r7, #4] 800fa82: 2b00 cmp r3, #0 800fa84: d101 bne.n 800fa8a { return HAL_ERROR; 800fa86: 2301 movs r3, #1 800fa88: e049 b.n 800fb1e assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800fa8a: 687b ldr r3, [r7, #4] 800fa8c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800fa90: b2db uxtb r3, r3 800fa92: 2b00 cmp r3, #0 800fa94: d106 bne.n 800faa4 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800fa96: 687b ldr r3, [r7, #4] 800fa98: 2200 movs r2, #0 800fa9a: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->IC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); 800fa9e: 6878 ldr r0, [r7, #4] 800faa0: f000 f841 bl 800fb26 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800faa4: 687b ldr r3, [r7, #4] 800faa6: 2202 movs r2, #2 800faa8: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800faac: 687b ldr r3, [r7, #4] 800faae: 681a ldr r2, [r3, #0] 800fab0: 687b ldr r3, [r7, #4] 800fab2: 3304 adds r3, #4 800fab4: 4619 mov r1, r3 800fab6: 4610 mov r0, r2 800fab8: f000 fddc bl 8010674 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800fabc: 687b ldr r3, [r7, #4] 800fabe: 2201 movs r2, #1 800fac0: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800fac4: 687b ldr r3, [r7, #4] 800fac6: 2201 movs r2, #1 800fac8: f883 203e strb.w r2, [r3, #62] @ 0x3e 800facc: 687b ldr r3, [r7, #4] 800face: 2201 movs r2, #1 800fad0: f883 203f strb.w r2, [r3, #63] @ 0x3f 800fad4: 687b ldr r3, [r7, #4] 800fad6: 2201 movs r2, #1 800fad8: f883 2040 strb.w r2, [r3, #64] @ 0x40 800fadc: 687b ldr r3, [r7, #4] 800fade: 2201 movs r2, #1 800fae0: f883 2041 strb.w r2, [r3, #65] @ 0x41 800fae4: 687b ldr r3, [r7, #4] 800fae6: 2201 movs r2, #1 800fae8: f883 2042 strb.w r2, [r3, #66] @ 0x42 800faec: 687b ldr r3, [r7, #4] 800faee: 2201 movs r2, #1 800faf0: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800faf4: 687b ldr r3, [r7, #4] 800faf6: 2201 movs r2, #1 800faf8: f883 2044 strb.w r2, [r3, #68] @ 0x44 800fafc: 687b ldr r3, [r7, #4] 800fafe: 2201 movs r2, #1 800fb00: f883 2045 strb.w r2, [r3, #69] @ 0x45 800fb04: 687b ldr r3, [r7, #4] 800fb06: 2201 movs r2, #1 800fb08: f883 2046 strb.w r2, [r3, #70] @ 0x46 800fb0c: 687b ldr r3, [r7, #4] 800fb0e: 2201 movs r2, #1 800fb10: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800fb14: 687b ldr r3, [r7, #4] 800fb16: 2201 movs r2, #1 800fb18: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800fb1c: 2300 movs r3, #0 } 800fb1e: 4618 mov r0, r3 800fb20: 3708 adds r7, #8 800fb22: 46bd mov sp, r7 800fb24: bd80 pop {r7, pc} 0800fb26 : * @brief Initializes the TIM Input Capture MSP. * @param htim TIM Input Capture handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) { 800fb26: b480 push {r7} 800fb28: b083 sub sp, #12 800fb2a: af00 add r7, sp, #0 800fb2c: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_MspInit could be implemented in the user file */ } 800fb2e: bf00 nop 800fb30: 370c adds r7, #12 800fb32: 46bd mov sp, r7 800fb34: f85d 7b04 ldr.w r7, [sp], #4 800fb38: 4770 bx lr ... 0800fb3c : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { 800fb3c: b580 push {r7, lr} 800fb3e: b084 sub sp, #16 800fb40: af00 add r7, sp, #0 800fb42: 6078 str r0, [r7, #4] 800fb44: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800fb46: 2300 movs r3, #0 800fb48: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); 800fb4a: 683b ldr r3, [r7, #0] 800fb4c: 2b00 cmp r3, #0 800fb4e: d104 bne.n 800fb5a 800fb50: 687b ldr r3, [r7, #4] 800fb52: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800fb56: b2db uxtb r3, r3 800fb58: e023 b.n 800fba2 800fb5a: 683b ldr r3, [r7, #0] 800fb5c: 2b04 cmp r3, #4 800fb5e: d104 bne.n 800fb6a 800fb60: 687b ldr r3, [r7, #4] 800fb62: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800fb66: b2db uxtb r3, r3 800fb68: e01b b.n 800fba2 800fb6a: 683b ldr r3, [r7, #0] 800fb6c: 2b08 cmp r3, #8 800fb6e: d104 bne.n 800fb7a 800fb70: 687b ldr r3, [r7, #4] 800fb72: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800fb76: b2db uxtb r3, r3 800fb78: e013 b.n 800fba2 800fb7a: 683b ldr r3, [r7, #0] 800fb7c: 2b0c cmp r3, #12 800fb7e: d104 bne.n 800fb8a 800fb80: 687b ldr r3, [r7, #4] 800fb82: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800fb86: b2db uxtb r3, r3 800fb88: e00b b.n 800fba2 800fb8a: 683b ldr r3, [r7, #0] 800fb8c: 2b10 cmp r3, #16 800fb8e: d104 bne.n 800fb9a 800fb90: 687b ldr r3, [r7, #4] 800fb92: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800fb96: b2db uxtb r3, r3 800fb98: e003 b.n 800fba2 800fb9a: 687b ldr r3, [r7, #4] 800fb9c: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800fba0: b2db uxtb r3, r3 800fba2: 73bb strb r3, [r7, #14] HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); 800fba4: 683b ldr r3, [r7, #0] 800fba6: 2b00 cmp r3, #0 800fba8: d104 bne.n 800fbb4 800fbaa: 687b ldr r3, [r7, #4] 800fbac: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 800fbb0: b2db uxtb r3, r3 800fbb2: e013 b.n 800fbdc 800fbb4: 683b ldr r3, [r7, #0] 800fbb6: 2b04 cmp r3, #4 800fbb8: d104 bne.n 800fbc4 800fbba: 687b ldr r3, [r7, #4] 800fbbc: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 800fbc0: b2db uxtb r3, r3 800fbc2: e00b b.n 800fbdc 800fbc4: 683b ldr r3, [r7, #0] 800fbc6: 2b08 cmp r3, #8 800fbc8: d104 bne.n 800fbd4 800fbca: 687b ldr r3, [r7, #4] 800fbcc: f893 3046 ldrb.w r3, [r3, #70] @ 0x46 800fbd0: b2db uxtb r3, r3 800fbd2: e003 b.n 800fbdc 800fbd4: 687b ldr r3, [r7, #4] 800fbd6: f893 3047 ldrb.w r3, [r3, #71] @ 0x47 800fbda: b2db uxtb r3, r3 800fbdc: 737b strb r3, [r7, #13] /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) 800fbde: 7bbb ldrb r3, [r7, #14] 800fbe0: 2b01 cmp r3, #1 800fbe2: d102 bne.n 800fbea || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) 800fbe4: 7b7b ldrb r3, [r7, #13] 800fbe6: 2b01 cmp r3, #1 800fbe8: d001 beq.n 800fbee { return HAL_ERROR; 800fbea: 2301 movs r3, #1 800fbec: e0e2 b.n 800fdb4 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800fbee: 683b ldr r3, [r7, #0] 800fbf0: 2b00 cmp r3, #0 800fbf2: d104 bne.n 800fbfe 800fbf4: 687b ldr r3, [r7, #4] 800fbf6: 2202 movs r2, #2 800fbf8: f883 203e strb.w r2, [r3, #62] @ 0x3e 800fbfc: e023 b.n 800fc46 800fbfe: 683b ldr r3, [r7, #0] 800fc00: 2b04 cmp r3, #4 800fc02: d104 bne.n 800fc0e 800fc04: 687b ldr r3, [r7, #4] 800fc06: 2202 movs r2, #2 800fc08: f883 203f strb.w r2, [r3, #63] @ 0x3f 800fc0c: e01b b.n 800fc46 800fc0e: 683b ldr r3, [r7, #0] 800fc10: 2b08 cmp r3, #8 800fc12: d104 bne.n 800fc1e 800fc14: 687b ldr r3, [r7, #4] 800fc16: 2202 movs r2, #2 800fc18: f883 2040 strb.w r2, [r3, #64] @ 0x40 800fc1c: e013 b.n 800fc46 800fc1e: 683b ldr r3, [r7, #0] 800fc20: 2b0c cmp r3, #12 800fc22: d104 bne.n 800fc2e 800fc24: 687b ldr r3, [r7, #4] 800fc26: 2202 movs r2, #2 800fc28: f883 2041 strb.w r2, [r3, #65] @ 0x41 800fc2c: e00b b.n 800fc46 800fc2e: 683b ldr r3, [r7, #0] 800fc30: 2b10 cmp r3, #16 800fc32: d104 bne.n 800fc3e 800fc34: 687b ldr r3, [r7, #4] 800fc36: 2202 movs r2, #2 800fc38: f883 2042 strb.w r2, [r3, #66] @ 0x42 800fc3c: e003 b.n 800fc46 800fc3e: 687b ldr r3, [r7, #4] 800fc40: 2202 movs r2, #2 800fc42: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800fc46: 683b ldr r3, [r7, #0] 800fc48: 2b00 cmp r3, #0 800fc4a: d104 bne.n 800fc56 800fc4c: 687b ldr r3, [r7, #4] 800fc4e: 2202 movs r2, #2 800fc50: f883 2044 strb.w r2, [r3, #68] @ 0x44 800fc54: e013 b.n 800fc7e 800fc56: 683b ldr r3, [r7, #0] 800fc58: 2b04 cmp r3, #4 800fc5a: d104 bne.n 800fc66 800fc5c: 687b ldr r3, [r7, #4] 800fc5e: 2202 movs r2, #2 800fc60: f883 2045 strb.w r2, [r3, #69] @ 0x45 800fc64: e00b b.n 800fc7e 800fc66: 683b ldr r3, [r7, #0] 800fc68: 2b08 cmp r3, #8 800fc6a: d104 bne.n 800fc76 800fc6c: 687b ldr r3, [r7, #4] 800fc6e: 2202 movs r2, #2 800fc70: f883 2046 strb.w r2, [r3, #70] @ 0x46 800fc74: e003 b.n 800fc7e 800fc76: 687b ldr r3, [r7, #4] 800fc78: 2202 movs r2, #2 800fc7a: f883 2047 strb.w r2, [r3, #71] @ 0x47 switch (Channel) 800fc7e: 683b ldr r3, [r7, #0] 800fc80: 2b0c cmp r3, #12 800fc82: d841 bhi.n 800fd08 800fc84: a201 add r2, pc, #4 @ (adr r2, 800fc8c ) 800fc86: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800fc8a: bf00 nop 800fc8c: 0800fcc1 .word 0x0800fcc1 800fc90: 0800fd09 .word 0x0800fd09 800fc94: 0800fd09 .word 0x0800fd09 800fc98: 0800fd09 .word 0x0800fd09 800fc9c: 0800fcd3 .word 0x0800fcd3 800fca0: 0800fd09 .word 0x0800fd09 800fca4: 0800fd09 .word 0x0800fd09 800fca8: 0800fd09 .word 0x0800fd09 800fcac: 0800fce5 .word 0x0800fce5 800fcb0: 0800fd09 .word 0x0800fd09 800fcb4: 0800fd09 .word 0x0800fd09 800fcb8: 0800fd09 .word 0x0800fd09 800fcbc: 0800fcf7 .word 0x0800fcf7 { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 800fcc0: 687b ldr r3, [r7, #4] 800fcc2: 681b ldr r3, [r3, #0] 800fcc4: 68da ldr r2, [r3, #12] 800fcc6: 687b ldr r3, [r7, #4] 800fcc8: 681b ldr r3, [r3, #0] 800fcca: f042 0202 orr.w r2, r2, #2 800fcce: 60da str r2, [r3, #12] break; 800fcd0: e01d b.n 800fd0e } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 800fcd2: 687b ldr r3, [r7, #4] 800fcd4: 681b ldr r3, [r3, #0] 800fcd6: 68da ldr r2, [r3, #12] 800fcd8: 687b ldr r3, [r7, #4] 800fcda: 681b ldr r3, [r3, #0] 800fcdc: f042 0204 orr.w r2, r2, #4 800fce0: 60da str r2, [r3, #12] break; 800fce2: e014 b.n 800fd0e } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 800fce4: 687b ldr r3, [r7, #4] 800fce6: 681b ldr r3, [r3, #0] 800fce8: 68da ldr r2, [r3, #12] 800fcea: 687b ldr r3, [r7, #4] 800fcec: 681b ldr r3, [r3, #0] 800fcee: f042 0208 orr.w r2, r2, #8 800fcf2: 60da str r2, [r3, #12] break; 800fcf4: e00b b.n 800fd0e } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 800fcf6: 687b ldr r3, [r7, #4] 800fcf8: 681b ldr r3, [r3, #0] 800fcfa: 68da ldr r2, [r3, #12] 800fcfc: 687b ldr r3, [r7, #4] 800fcfe: 681b ldr r3, [r3, #0] 800fd00: f042 0210 orr.w r2, r2, #16 800fd04: 60da str r2, [r3, #12] break; 800fd06: e002 b.n 800fd0e } default: status = HAL_ERROR; 800fd08: 2301 movs r3, #1 800fd0a: 73fb strb r3, [r7, #15] break; 800fd0c: bf00 nop } if (status == HAL_OK) 800fd0e: 7bfb ldrb r3, [r7, #15] 800fd10: 2b00 cmp r3, #0 800fd12: d14e bne.n 800fdb2 { /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 800fd14: 687b ldr r3, [r7, #4] 800fd16: 681b ldr r3, [r3, #0] 800fd18: 2201 movs r2, #1 800fd1a: 6839 ldr r1, [r7, #0] 800fd1c: 4618 mov r0, r3 800fd1e: f001 f9ed bl 80110fc /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800fd22: 687b ldr r3, [r7, #4] 800fd24: 681b ldr r3, [r3, #0] 800fd26: 4a25 ldr r2, [pc, #148] @ (800fdbc ) 800fd28: 4293 cmp r3, r2 800fd2a: d022 beq.n 800fd72 800fd2c: 687b ldr r3, [r7, #4] 800fd2e: 681b ldr r3, [r3, #0] 800fd30: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800fd34: d01d beq.n 800fd72 800fd36: 687b ldr r3, [r7, #4] 800fd38: 681b ldr r3, [r3, #0] 800fd3a: 4a21 ldr r2, [pc, #132] @ (800fdc0 ) 800fd3c: 4293 cmp r3, r2 800fd3e: d018 beq.n 800fd72 800fd40: 687b ldr r3, [r7, #4] 800fd42: 681b ldr r3, [r3, #0] 800fd44: 4a1f ldr r2, [pc, #124] @ (800fdc4 ) 800fd46: 4293 cmp r3, r2 800fd48: d013 beq.n 800fd72 800fd4a: 687b ldr r3, [r7, #4] 800fd4c: 681b ldr r3, [r3, #0] 800fd4e: 4a1e ldr r2, [pc, #120] @ (800fdc8 ) 800fd50: 4293 cmp r3, r2 800fd52: d00e beq.n 800fd72 800fd54: 687b ldr r3, [r7, #4] 800fd56: 681b ldr r3, [r3, #0] 800fd58: 4a1c ldr r2, [pc, #112] @ (800fdcc ) 800fd5a: 4293 cmp r3, r2 800fd5c: d009 beq.n 800fd72 800fd5e: 687b ldr r3, [r7, #4] 800fd60: 681b ldr r3, [r3, #0] 800fd62: 4a1b ldr r2, [pc, #108] @ (800fdd0 ) 800fd64: 4293 cmp r3, r2 800fd66: d004 beq.n 800fd72 800fd68: 687b ldr r3, [r7, #4] 800fd6a: 681b ldr r3, [r3, #0] 800fd6c: 4a19 ldr r2, [pc, #100] @ (800fdd4 ) 800fd6e: 4293 cmp r3, r2 800fd70: d115 bne.n 800fd9e { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800fd72: 687b ldr r3, [r7, #4] 800fd74: 681b ldr r3, [r3, #0] 800fd76: 689a ldr r2, [r3, #8] 800fd78: 4b17 ldr r3, [pc, #92] @ (800fdd8 ) 800fd7a: 4013 ands r3, r2 800fd7c: 60bb str r3, [r7, #8] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800fd7e: 68bb ldr r3, [r7, #8] 800fd80: 2b06 cmp r3, #6 800fd82: d015 beq.n 800fdb0 800fd84: 68bb ldr r3, [r7, #8] 800fd86: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800fd8a: d011 beq.n 800fdb0 { __HAL_TIM_ENABLE(htim); 800fd8c: 687b ldr r3, [r7, #4] 800fd8e: 681b ldr r3, [r3, #0] 800fd90: 681a ldr r2, [r3, #0] 800fd92: 687b ldr r3, [r7, #4] 800fd94: 681b ldr r3, [r3, #0] 800fd96: f042 0201 orr.w r2, r2, #1 800fd9a: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800fd9c: e008 b.n 800fdb0 } } else { __HAL_TIM_ENABLE(htim); 800fd9e: 687b ldr r3, [r7, #4] 800fda0: 681b ldr r3, [r3, #0] 800fda2: 681a ldr r2, [r3, #0] 800fda4: 687b ldr r3, [r7, #4] 800fda6: 681b ldr r3, [r3, #0] 800fda8: f042 0201 orr.w r2, r2, #1 800fdac: 601a str r2, [r3, #0] 800fdae: e000 b.n 800fdb2 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800fdb0: bf00 nop } } /* Return function status */ return status; 800fdb2: 7bfb ldrb r3, [r7, #15] } 800fdb4: 4618 mov r0, r3 800fdb6: 3710 adds r7, #16 800fdb8: 46bd mov sp, r7 800fdba: bd80 pop {r7, pc} 800fdbc: 40010000 .word 0x40010000 800fdc0: 40000400 .word 0x40000400 800fdc4: 40000800 .word 0x40000800 800fdc8: 40000c00 .word 0x40000c00 800fdcc: 40010400 .word 0x40010400 800fdd0: 40001800 .word 0x40001800 800fdd4: 40014000 .word 0x40014000 800fdd8: 00010007 .word 0x00010007 0800fddc : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 800fddc: b580 push {r7, lr} 800fdde: b084 sub sp, #16 800fde0: af00 add r7, sp, #0 800fde2: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 800fde4: 687b ldr r3, [r7, #4] 800fde6: 681b ldr r3, [r3, #0] 800fde8: 68db ldr r3, [r3, #12] 800fdea: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 800fdec: 687b ldr r3, [r7, #4] 800fdee: 681b ldr r3, [r3, #0] 800fdf0: 691b ldr r3, [r3, #16] 800fdf2: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 800fdf4: 68bb ldr r3, [r7, #8] 800fdf6: f003 0302 and.w r3, r3, #2 800fdfa: 2b00 cmp r3, #0 800fdfc: d020 beq.n 800fe40 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 800fdfe: 68fb ldr r3, [r7, #12] 800fe00: f003 0302 and.w r3, r3, #2 800fe04: 2b00 cmp r3, #0 800fe06: d01b beq.n 800fe40 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 800fe08: 687b ldr r3, [r7, #4] 800fe0a: 681b ldr r3, [r3, #0] 800fe0c: f06f 0202 mvn.w r2, #2 800fe10: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800fe12: 687b ldr r3, [r7, #4] 800fe14: 2201 movs r2, #1 800fe16: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 800fe18: 687b ldr r3, [r7, #4] 800fe1a: 681b ldr r3, [r3, #0] 800fe1c: 699b ldr r3, [r3, #24] 800fe1e: f003 0303 and.w r3, r3, #3 800fe22: 2b00 cmp r3, #0 800fe24: d003 beq.n 800fe2e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800fe26: 6878 ldr r0, [r7, #4] 800fe28: f7f1 fdc0 bl 80019ac 800fe2c: e005 b.n 800fe3a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800fe2e: 6878 ldr r0, [r7, #4] 800fe30: f000 fbc8 bl 80105c4 HAL_TIM_PWM_PulseFinishedCallback(htim); 800fe34: 6878 ldr r0, [r7, #4] 800fe36: f000 fbcf bl 80105d8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800fe3a: 687b ldr r3, [r7, #4] 800fe3c: 2200 movs r2, #0 800fe3e: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 800fe40: 68bb ldr r3, [r7, #8] 800fe42: f003 0304 and.w r3, r3, #4 800fe46: 2b00 cmp r3, #0 800fe48: d020 beq.n 800fe8c { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 800fe4a: 68fb ldr r3, [r7, #12] 800fe4c: f003 0304 and.w r3, r3, #4 800fe50: 2b00 cmp r3, #0 800fe52: d01b beq.n 800fe8c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 800fe54: 687b ldr r3, [r7, #4] 800fe56: 681b ldr r3, [r3, #0] 800fe58: f06f 0204 mvn.w r2, #4 800fe5c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800fe5e: 687b ldr r3, [r7, #4] 800fe60: 2202 movs r2, #2 800fe62: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 800fe64: 687b ldr r3, [r7, #4] 800fe66: 681b ldr r3, [r3, #0] 800fe68: 699b ldr r3, [r3, #24] 800fe6a: f403 7340 and.w r3, r3, #768 @ 0x300 800fe6e: 2b00 cmp r3, #0 800fe70: d003 beq.n 800fe7a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800fe72: 6878 ldr r0, [r7, #4] 800fe74: f7f1 fd9a bl 80019ac 800fe78: e005 b.n 800fe86 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800fe7a: 6878 ldr r0, [r7, #4] 800fe7c: f000 fba2 bl 80105c4 HAL_TIM_PWM_PulseFinishedCallback(htim); 800fe80: 6878 ldr r0, [r7, #4] 800fe82: f000 fba9 bl 80105d8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800fe86: 687b ldr r3, [r7, #4] 800fe88: 2200 movs r2, #0 800fe8a: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 800fe8c: 68bb ldr r3, [r7, #8] 800fe8e: f003 0308 and.w r3, r3, #8 800fe92: 2b00 cmp r3, #0 800fe94: d020 beq.n 800fed8 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 800fe96: 68fb ldr r3, [r7, #12] 800fe98: f003 0308 and.w r3, r3, #8 800fe9c: 2b00 cmp r3, #0 800fe9e: d01b beq.n 800fed8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 800fea0: 687b ldr r3, [r7, #4] 800fea2: 681b ldr r3, [r3, #0] 800fea4: f06f 0208 mvn.w r2, #8 800fea8: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800feaa: 687b ldr r3, [r7, #4] 800feac: 2204 movs r2, #4 800feae: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800feb0: 687b ldr r3, [r7, #4] 800feb2: 681b ldr r3, [r3, #0] 800feb4: 69db ldr r3, [r3, #28] 800feb6: f003 0303 and.w r3, r3, #3 800feba: 2b00 cmp r3, #0 800febc: d003 beq.n 800fec6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800febe: 6878 ldr r0, [r7, #4] 800fec0: f7f1 fd74 bl 80019ac 800fec4: e005 b.n 800fed2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800fec6: 6878 ldr r0, [r7, #4] 800fec8: f000 fb7c bl 80105c4 HAL_TIM_PWM_PulseFinishedCallback(htim); 800fecc: 6878 ldr r0, [r7, #4] 800fece: f000 fb83 bl 80105d8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800fed2: 687b ldr r3, [r7, #4] 800fed4: 2200 movs r2, #0 800fed6: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 800fed8: 68bb ldr r3, [r7, #8] 800feda: f003 0310 and.w r3, r3, #16 800fede: 2b00 cmp r3, #0 800fee0: d020 beq.n 800ff24 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 800fee2: 68fb ldr r3, [r7, #12] 800fee4: f003 0310 and.w r3, r3, #16 800fee8: 2b00 cmp r3, #0 800feea: d01b beq.n 800ff24 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 800feec: 687b ldr r3, [r7, #4] 800feee: 681b ldr r3, [r3, #0] 800fef0: f06f 0210 mvn.w r2, #16 800fef4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800fef6: 687b ldr r3, [r7, #4] 800fef8: 2208 movs r2, #8 800fefa: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 800fefc: 687b ldr r3, [r7, #4] 800fefe: 681b ldr r3, [r3, #0] 800ff00: 69db ldr r3, [r3, #28] 800ff02: f403 7340 and.w r3, r3, #768 @ 0x300 800ff06: 2b00 cmp r3, #0 800ff08: d003 beq.n 800ff12 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800ff0a: 6878 ldr r0, [r7, #4] 800ff0c: f7f1 fd4e bl 80019ac 800ff10: e005 b.n 800ff1e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800ff12: 6878 ldr r0, [r7, #4] 800ff14: f000 fb56 bl 80105c4 HAL_TIM_PWM_PulseFinishedCallback(htim); 800ff18: 6878 ldr r0, [r7, #4] 800ff1a: f000 fb5d bl 80105d8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800ff1e: 687b ldr r3, [r7, #4] 800ff20: 2200 movs r2, #0 800ff22: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 800ff24: 68bb ldr r3, [r7, #8] 800ff26: f003 0301 and.w r3, r3, #1 800ff2a: 2b00 cmp r3, #0 800ff2c: d00c beq.n 800ff48 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 800ff2e: 68fb ldr r3, [r7, #12] 800ff30: f003 0301 and.w r3, r3, #1 800ff34: 2b00 cmp r3, #0 800ff36: d007 beq.n 800ff48 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 800ff38: 687b ldr r3, [r7, #4] 800ff3a: 681b ldr r3, [r3, #0] 800ff3c: f06f 0201 mvn.w r2, #1 800ff40: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 800ff42: 6878 ldr r0, [r7, #4] 800ff44: f7f1 ff8e bl 8001e64 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800ff48: 68bb ldr r3, [r7, #8] 800ff4a: f003 0380 and.w r3, r3, #128 @ 0x80 800ff4e: 2b00 cmp r3, #0 800ff50: d104 bne.n 800ff5c ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) 800ff52: 68bb ldr r3, [r7, #8] 800ff54: f403 5300 and.w r3, r3, #8192 @ 0x2000 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800ff58: 2b00 cmp r3, #0 800ff5a: d00c beq.n 800ff76 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800ff5c: 68fb ldr r3, [r7, #12] 800ff5e: f003 0380 and.w r3, r3, #128 @ 0x80 800ff62: 2b00 cmp r3, #0 800ff64: d007 beq.n 800ff76 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 800ff66: 687b ldr r3, [r7, #4] 800ff68: 681b ldr r3, [r3, #0] 800ff6a: f46f 5202 mvn.w r2, #8320 @ 0x2080 800ff6e: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 800ff70: 6878 ldr r0, [r7, #4] 800ff72: f001 f9ff bl 8011374 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 800ff76: 68bb ldr r3, [r7, #8] 800ff78: f403 7380 and.w r3, r3, #256 @ 0x100 800ff7c: 2b00 cmp r3, #0 800ff7e: d00c beq.n 800ff9a { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800ff80: 68fb ldr r3, [r7, #12] 800ff82: f003 0380 and.w r3, r3, #128 @ 0x80 800ff86: 2b00 cmp r3, #0 800ff88: d007 beq.n 800ff9a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 800ff8a: 687b ldr r3, [r7, #4] 800ff8c: 681b ldr r3, [r3, #0] 800ff8e: f46f 7280 mvn.w r2, #256 @ 0x100 800ff92: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 800ff94: 6878 ldr r0, [r7, #4] 800ff96: f001 f9f7 bl 8011388 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 800ff9a: 68bb ldr r3, [r7, #8] 800ff9c: f003 0340 and.w r3, r3, #64 @ 0x40 800ffa0: 2b00 cmp r3, #0 800ffa2: d00c beq.n 800ffbe { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 800ffa4: 68fb ldr r3, [r7, #12] 800ffa6: f003 0340 and.w r3, r3, #64 @ 0x40 800ffaa: 2b00 cmp r3, #0 800ffac: d007 beq.n 800ffbe { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 800ffae: 687b ldr r3, [r7, #4] 800ffb0: 681b ldr r3, [r3, #0] 800ffb2: f06f 0240 mvn.w r2, #64 @ 0x40 800ffb6: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 800ffb8: 6878 ldr r0, [r7, #4] 800ffba: f000 fb17 bl 80105ec #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 800ffbe: 68bb ldr r3, [r7, #8] 800ffc0: f003 0320 and.w r3, r3, #32 800ffc4: 2b00 cmp r3, #0 800ffc6: d00c beq.n 800ffe2 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 800ffc8: 68fb ldr r3, [r7, #12] 800ffca: f003 0320 and.w r3, r3, #32 800ffce: 2b00 cmp r3, #0 800ffd0: d007 beq.n 800ffe2 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 800ffd2: 687b ldr r3, [r7, #4] 800ffd4: 681b ldr r3, [r3, #0] 800ffd6: f06f 0220 mvn.w r2, #32 800ffda: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 800ffdc: 6878 ldr r0, [r7, #4] 800ffde: f001 f9bf bl 8011360 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 800ffe2: bf00 nop 800ffe4: 3710 adds r7, #16 800ffe6: 46bd mov sp, r7 800ffe8: bd80 pop {r7, pc} 0800ffea : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { 800ffea: b580 push {r7, lr} 800ffec: b086 sub sp, #24 800ffee: af00 add r7, sp, #0 800fff0: 60f8 str r0, [r7, #12] 800fff2: 60b9 str r1, [r7, #8] 800fff4: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800fff6: 2300 movs r3, #0 800fff8: 75fb strb r3, [r7, #23] assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); /* Process Locked */ __HAL_LOCK(htim); 800fffa: 68fb ldr r3, [r7, #12] 800fffc: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8010000: 2b01 cmp r3, #1 8010002: d101 bne.n 8010008 8010004: 2302 movs r3, #2 8010006: e088 b.n 801011a 8010008: 68fb ldr r3, [r7, #12] 801000a: 2201 movs r2, #1 801000c: f883 203c strb.w r2, [r3, #60] @ 0x3c if (Channel == TIM_CHANNEL_1) 8010010: 687b ldr r3, [r7, #4] 8010012: 2b00 cmp r3, #0 8010014: d11b bne.n 801004e { /* TI1 Configuration */ TIM_TI1_SetConfig(htim->Instance, 8010016: 68fb ldr r3, [r7, #12] 8010018: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 801001a: 68bb ldr r3, [r7, #8] 801001c: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 801001e: 68bb ldr r3, [r7, #8] 8010020: 685a ldr r2, [r3, #4] sConfig->ICFilter); 8010022: 68bb ldr r3, [r7, #8] 8010024: 68db ldr r3, [r3, #12] TIM_TI1_SetConfig(htim->Instance, 8010026: f000 fea1 bl 8010d6c /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; 801002a: 68fb ldr r3, [r7, #12] 801002c: 681b ldr r3, [r3, #0] 801002e: 699a ldr r2, [r3, #24] 8010030: 68fb ldr r3, [r7, #12] 8010032: 681b ldr r3, [r3, #0] 8010034: f022 020c bic.w r2, r2, #12 8010038: 619a str r2, [r3, #24] /* Set the IC1PSC value */ htim->Instance->CCMR1 |= sConfig->ICPrescaler; 801003a: 68fb ldr r3, [r7, #12] 801003c: 681b ldr r3, [r3, #0] 801003e: 6999 ldr r1, [r3, #24] 8010040: 68bb ldr r3, [r7, #8] 8010042: 689a ldr r2, [r3, #8] 8010044: 68fb ldr r3, [r7, #12] 8010046: 681b ldr r3, [r3, #0] 8010048: 430a orrs r2, r1 801004a: 619a str r2, [r3, #24] 801004c: e060 b.n 8010110 } else if (Channel == TIM_CHANNEL_2) 801004e: 687b ldr r3, [r7, #4] 8010050: 2b04 cmp r3, #4 8010052: d11c bne.n 801008e { /* TI2 Configuration */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_TI2_SetConfig(htim->Instance, 8010054: 68fb ldr r3, [r7, #12] 8010056: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 8010058: 68bb ldr r3, [r7, #8] 801005a: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 801005c: 68bb ldr r3, [r7, #8] 801005e: 685a ldr r2, [r3, #4] sConfig->ICFilter); 8010060: 68bb ldr r3, [r7, #8] 8010062: 68db ldr r3, [r3, #12] TIM_TI2_SetConfig(htim->Instance, 8010064: f000 ff25 bl 8010eb2 /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; 8010068: 68fb ldr r3, [r7, #12] 801006a: 681b ldr r3, [r3, #0] 801006c: 699a ldr r2, [r3, #24] 801006e: 68fb ldr r3, [r7, #12] 8010070: 681b ldr r3, [r3, #0] 8010072: f422 6240 bic.w r2, r2, #3072 @ 0xc00 8010076: 619a str r2, [r3, #24] /* Set the IC2PSC value */ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); 8010078: 68fb ldr r3, [r7, #12] 801007a: 681b ldr r3, [r3, #0] 801007c: 6999 ldr r1, [r3, #24] 801007e: 68bb ldr r3, [r7, #8] 8010080: 689b ldr r3, [r3, #8] 8010082: 021a lsls r2, r3, #8 8010084: 68fb ldr r3, [r7, #12] 8010086: 681b ldr r3, [r3, #0] 8010088: 430a orrs r2, r1 801008a: 619a str r2, [r3, #24] 801008c: e040 b.n 8010110 } else if (Channel == TIM_CHANNEL_3) 801008e: 687b ldr r3, [r7, #4] 8010090: 2b08 cmp r3, #8 8010092: d11b bne.n 80100cc { /* TI3 Configuration */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); TIM_TI3_SetConfig(htim->Instance, 8010094: 68fb ldr r3, [r7, #12] 8010096: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 8010098: 68bb ldr r3, [r7, #8] 801009a: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 801009c: 68bb ldr r3, [r7, #8] 801009e: 685a ldr r2, [r3, #4] sConfig->ICFilter); 80100a0: 68bb ldr r3, [r7, #8] 80100a2: 68db ldr r3, [r3, #12] TIM_TI3_SetConfig(htim->Instance, 80100a4: f000 ff72 bl 8010f8c /* Reset the IC3PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; 80100a8: 68fb ldr r3, [r7, #12] 80100aa: 681b ldr r3, [r3, #0] 80100ac: 69da ldr r2, [r3, #28] 80100ae: 68fb ldr r3, [r7, #12] 80100b0: 681b ldr r3, [r3, #0] 80100b2: f022 020c bic.w r2, r2, #12 80100b6: 61da str r2, [r3, #28] /* Set the IC3PSC value */ htim->Instance->CCMR2 |= sConfig->ICPrescaler; 80100b8: 68fb ldr r3, [r7, #12] 80100ba: 681b ldr r3, [r3, #0] 80100bc: 69d9 ldr r1, [r3, #28] 80100be: 68bb ldr r3, [r7, #8] 80100c0: 689a ldr r2, [r3, #8] 80100c2: 68fb ldr r3, [r7, #12] 80100c4: 681b ldr r3, [r3, #0] 80100c6: 430a orrs r2, r1 80100c8: 61da str r2, [r3, #28] 80100ca: e021 b.n 8010110 } else if (Channel == TIM_CHANNEL_4) 80100cc: 687b ldr r3, [r7, #4] 80100ce: 2b0c cmp r3, #12 80100d0: d11c bne.n 801010c { /* TI4 Configuration */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); TIM_TI4_SetConfig(htim->Instance, 80100d2: 68fb ldr r3, [r7, #12] 80100d4: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 80100d6: 68bb ldr r3, [r7, #8] 80100d8: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 80100da: 68bb ldr r3, [r7, #8] 80100dc: 685a ldr r2, [r3, #4] sConfig->ICFilter); 80100de: 68bb ldr r3, [r7, #8] 80100e0: 68db ldr r3, [r3, #12] TIM_TI4_SetConfig(htim->Instance, 80100e2: f000 ff8f bl 8011004 /* Reset the IC4PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; 80100e6: 68fb ldr r3, [r7, #12] 80100e8: 681b ldr r3, [r3, #0] 80100ea: 69da ldr r2, [r3, #28] 80100ec: 68fb ldr r3, [r7, #12] 80100ee: 681b ldr r3, [r3, #0] 80100f0: f422 6240 bic.w r2, r2, #3072 @ 0xc00 80100f4: 61da str r2, [r3, #28] /* Set the IC4PSC value */ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); 80100f6: 68fb ldr r3, [r7, #12] 80100f8: 681b ldr r3, [r3, #0] 80100fa: 69d9 ldr r1, [r3, #28] 80100fc: 68bb ldr r3, [r7, #8] 80100fe: 689b ldr r3, [r3, #8] 8010100: 021a lsls r2, r3, #8 8010102: 68fb ldr r3, [r7, #12] 8010104: 681b ldr r3, [r3, #0] 8010106: 430a orrs r2, r1 8010108: 61da str r2, [r3, #28] 801010a: e001 b.n 8010110 } else { status = HAL_ERROR; 801010c: 2301 movs r3, #1 801010e: 75fb strb r3, [r7, #23] } __HAL_UNLOCK(htim); 8010110: 68fb ldr r3, [r7, #12] 8010112: 2200 movs r2, #0 8010114: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8010118: 7dfb ldrb r3, [r7, #23] } 801011a: 4618 mov r0, r3 801011c: 3718 adds r7, #24 801011e: 46bd mov sp, r7 8010120: bd80 pop {r7, pc} ... 08010124 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8010124: b580 push {r7, lr} 8010126: b086 sub sp, #24 8010128: af00 add r7, sp, #0 801012a: 60f8 str r0, [r7, #12] 801012c: 60b9 str r1, [r7, #8] 801012e: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8010130: 2300 movs r3, #0 8010132: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 8010134: 68fb ldr r3, [r7, #12] 8010136: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 801013a: 2b01 cmp r3, #1 801013c: d101 bne.n 8010142 801013e: 2302 movs r3, #2 8010140: e0ff b.n 8010342 8010142: 68fb ldr r3, [r7, #12] 8010144: 2201 movs r2, #1 8010146: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 801014a: 687b ldr r3, [r7, #4] 801014c: 2b14 cmp r3, #20 801014e: f200 80f0 bhi.w 8010332 8010152: a201 add r2, pc, #4 @ (adr r2, 8010158 ) 8010154: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8010158: 080101ad .word 0x080101ad 801015c: 08010333 .word 0x08010333 8010160: 08010333 .word 0x08010333 8010164: 08010333 .word 0x08010333 8010168: 080101ed .word 0x080101ed 801016c: 08010333 .word 0x08010333 8010170: 08010333 .word 0x08010333 8010174: 08010333 .word 0x08010333 8010178: 0801022f .word 0x0801022f 801017c: 08010333 .word 0x08010333 8010180: 08010333 .word 0x08010333 8010184: 08010333 .word 0x08010333 8010188: 0801026f .word 0x0801026f 801018c: 08010333 .word 0x08010333 8010190: 08010333 .word 0x08010333 8010194: 08010333 .word 0x08010333 8010198: 080102b1 .word 0x080102b1 801019c: 08010333 .word 0x08010333 80101a0: 08010333 .word 0x08010333 80101a4: 08010333 .word 0x08010333 80101a8: 080102f1 .word 0x080102f1 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 80101ac: 68fb ldr r3, [r7, #12] 80101ae: 681b ldr r3, [r3, #0] 80101b0: 68b9 ldr r1, [r7, #8] 80101b2: 4618 mov r0, r3 80101b4: f000 fb04 bl 80107c0 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 80101b8: 68fb ldr r3, [r7, #12] 80101ba: 681b ldr r3, [r3, #0] 80101bc: 699a ldr r2, [r3, #24] 80101be: 68fb ldr r3, [r7, #12] 80101c0: 681b ldr r3, [r3, #0] 80101c2: f042 0208 orr.w r2, r2, #8 80101c6: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 80101c8: 68fb ldr r3, [r7, #12] 80101ca: 681b ldr r3, [r3, #0] 80101cc: 699a ldr r2, [r3, #24] 80101ce: 68fb ldr r3, [r7, #12] 80101d0: 681b ldr r3, [r3, #0] 80101d2: f022 0204 bic.w r2, r2, #4 80101d6: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 80101d8: 68fb ldr r3, [r7, #12] 80101da: 681b ldr r3, [r3, #0] 80101dc: 6999 ldr r1, [r3, #24] 80101de: 68bb ldr r3, [r7, #8] 80101e0: 691a ldr r2, [r3, #16] 80101e2: 68fb ldr r3, [r7, #12] 80101e4: 681b ldr r3, [r3, #0] 80101e6: 430a orrs r2, r1 80101e8: 619a str r2, [r3, #24] break; 80101ea: e0a5 b.n 8010338 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 80101ec: 68fb ldr r3, [r7, #12] 80101ee: 681b ldr r3, [r3, #0] 80101f0: 68b9 ldr r1, [r7, #8] 80101f2: 4618 mov r0, r3 80101f4: f000 fb74 bl 80108e0 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 80101f8: 68fb ldr r3, [r7, #12] 80101fa: 681b ldr r3, [r3, #0] 80101fc: 699a ldr r2, [r3, #24] 80101fe: 68fb ldr r3, [r7, #12] 8010200: 681b ldr r3, [r3, #0] 8010202: f442 6200 orr.w r2, r2, #2048 @ 0x800 8010206: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8010208: 68fb ldr r3, [r7, #12] 801020a: 681b ldr r3, [r3, #0] 801020c: 699a ldr r2, [r3, #24] 801020e: 68fb ldr r3, [r7, #12] 8010210: 681b ldr r3, [r3, #0] 8010212: f422 6280 bic.w r2, r2, #1024 @ 0x400 8010216: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8010218: 68fb ldr r3, [r7, #12] 801021a: 681b ldr r3, [r3, #0] 801021c: 6999 ldr r1, [r3, #24] 801021e: 68bb ldr r3, [r7, #8] 8010220: 691b ldr r3, [r3, #16] 8010222: 021a lsls r2, r3, #8 8010224: 68fb ldr r3, [r7, #12] 8010226: 681b ldr r3, [r3, #0] 8010228: 430a orrs r2, r1 801022a: 619a str r2, [r3, #24] break; 801022c: e084 b.n 8010338 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 801022e: 68fb ldr r3, [r7, #12] 8010230: 681b ldr r3, [r3, #0] 8010232: 68b9 ldr r1, [r7, #8] 8010234: 4618 mov r0, r3 8010236: f000 fbdd bl 80109f4 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 801023a: 68fb ldr r3, [r7, #12] 801023c: 681b ldr r3, [r3, #0] 801023e: 69da ldr r2, [r3, #28] 8010240: 68fb ldr r3, [r7, #12] 8010242: 681b ldr r3, [r3, #0] 8010244: f042 0208 orr.w r2, r2, #8 8010248: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 801024a: 68fb ldr r3, [r7, #12] 801024c: 681b ldr r3, [r3, #0] 801024e: 69da ldr r2, [r3, #28] 8010250: 68fb ldr r3, [r7, #12] 8010252: 681b ldr r3, [r3, #0] 8010254: f022 0204 bic.w r2, r2, #4 8010258: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 801025a: 68fb ldr r3, [r7, #12] 801025c: 681b ldr r3, [r3, #0] 801025e: 69d9 ldr r1, [r3, #28] 8010260: 68bb ldr r3, [r7, #8] 8010262: 691a ldr r2, [r3, #16] 8010264: 68fb ldr r3, [r7, #12] 8010266: 681b ldr r3, [r3, #0] 8010268: 430a orrs r2, r1 801026a: 61da str r2, [r3, #28] break; 801026c: e064 b.n 8010338 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 801026e: 68fb ldr r3, [r7, #12] 8010270: 681b ldr r3, [r3, #0] 8010272: 68b9 ldr r1, [r7, #8] 8010274: 4618 mov r0, r3 8010276: f000 fc45 bl 8010b04 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 801027a: 68fb ldr r3, [r7, #12] 801027c: 681b ldr r3, [r3, #0] 801027e: 69da ldr r2, [r3, #28] 8010280: 68fb ldr r3, [r7, #12] 8010282: 681b ldr r3, [r3, #0] 8010284: f442 6200 orr.w r2, r2, #2048 @ 0x800 8010288: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 801028a: 68fb ldr r3, [r7, #12] 801028c: 681b ldr r3, [r3, #0] 801028e: 69da ldr r2, [r3, #28] 8010290: 68fb ldr r3, [r7, #12] 8010292: 681b ldr r3, [r3, #0] 8010294: f422 6280 bic.w r2, r2, #1024 @ 0x400 8010298: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 801029a: 68fb ldr r3, [r7, #12] 801029c: 681b ldr r3, [r3, #0] 801029e: 69d9 ldr r1, [r3, #28] 80102a0: 68bb ldr r3, [r7, #8] 80102a2: 691b ldr r3, [r3, #16] 80102a4: 021a lsls r2, r3, #8 80102a6: 68fb ldr r3, [r7, #12] 80102a8: 681b ldr r3, [r3, #0] 80102aa: 430a orrs r2, r1 80102ac: 61da str r2, [r3, #28] break; 80102ae: e043 b.n 8010338 { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); 80102b0: 68fb ldr r3, [r7, #12] 80102b2: 681b ldr r3, [r3, #0] 80102b4: 68b9 ldr r1, [r7, #8] 80102b6: 4618 mov r0, r3 80102b8: f000 fc8e bl 8010bd8 /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 80102bc: 68fb ldr r3, [r7, #12] 80102be: 681b ldr r3, [r3, #0] 80102c0: 6d5a ldr r2, [r3, #84] @ 0x54 80102c2: 68fb ldr r3, [r7, #12] 80102c4: 681b ldr r3, [r3, #0] 80102c6: f042 0208 orr.w r2, r2, #8 80102ca: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 80102cc: 68fb ldr r3, [r7, #12] 80102ce: 681b ldr r3, [r3, #0] 80102d0: 6d5a ldr r2, [r3, #84] @ 0x54 80102d2: 68fb ldr r3, [r7, #12] 80102d4: 681b ldr r3, [r3, #0] 80102d6: f022 0204 bic.w r2, r2, #4 80102da: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; 80102dc: 68fb ldr r3, [r7, #12] 80102de: 681b ldr r3, [r3, #0] 80102e0: 6d59 ldr r1, [r3, #84] @ 0x54 80102e2: 68bb ldr r3, [r7, #8] 80102e4: 691a ldr r2, [r3, #16] 80102e6: 68fb ldr r3, [r7, #12] 80102e8: 681b ldr r3, [r3, #0] 80102ea: 430a orrs r2, r1 80102ec: 655a str r2, [r3, #84] @ 0x54 break; 80102ee: e023 b.n 8010338 { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); 80102f0: 68fb ldr r3, [r7, #12] 80102f2: 681b ldr r3, [r3, #0] 80102f4: 68b9 ldr r1, [r7, #8] 80102f6: 4618 mov r0, r3 80102f8: f000 fcd2 bl 8010ca0 /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 80102fc: 68fb ldr r3, [r7, #12] 80102fe: 681b ldr r3, [r3, #0] 8010300: 6d5a ldr r2, [r3, #84] @ 0x54 8010302: 68fb ldr r3, [r7, #12] 8010304: 681b ldr r3, [r3, #0] 8010306: f442 6200 orr.w r2, r2, #2048 @ 0x800 801030a: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 801030c: 68fb ldr r3, [r7, #12] 801030e: 681b ldr r3, [r3, #0] 8010310: 6d5a ldr r2, [r3, #84] @ 0x54 8010312: 68fb ldr r3, [r7, #12] 8010314: 681b ldr r3, [r3, #0] 8010316: f422 6280 bic.w r2, r2, #1024 @ 0x400 801031a: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 801031c: 68fb ldr r3, [r7, #12] 801031e: 681b ldr r3, [r3, #0] 8010320: 6d59 ldr r1, [r3, #84] @ 0x54 8010322: 68bb ldr r3, [r7, #8] 8010324: 691b ldr r3, [r3, #16] 8010326: 021a lsls r2, r3, #8 8010328: 68fb ldr r3, [r7, #12] 801032a: 681b ldr r3, [r3, #0] 801032c: 430a orrs r2, r1 801032e: 655a str r2, [r3, #84] @ 0x54 break; 8010330: e002 b.n 8010338 } default: status = HAL_ERROR; 8010332: 2301 movs r3, #1 8010334: 75fb strb r3, [r7, #23] break; 8010336: bf00 nop } __HAL_UNLOCK(htim); 8010338: 68fb ldr r3, [r7, #12] 801033a: 2200 movs r2, #0 801033c: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8010340: 7dfb ldrb r3, [r7, #23] } 8010342: 4618 mov r0, r3 8010344: 3718 adds r7, #24 8010346: 46bd mov sp, r7 8010348: bd80 pop {r7, pc} 801034a: bf00 nop 0801034c : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 801034c: b580 push {r7, lr} 801034e: b084 sub sp, #16 8010350: af00 add r7, sp, #0 8010352: 6078 str r0, [r7, #4] 8010354: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8010356: 2300 movs r3, #0 8010358: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 801035a: 687b ldr r3, [r7, #4] 801035c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8010360: 2b01 cmp r3, #1 8010362: d101 bne.n 8010368 8010364: 2302 movs r3, #2 8010366: e0dc b.n 8010522 8010368: 687b ldr r3, [r7, #4] 801036a: 2201 movs r2, #1 801036c: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 8010370: 687b ldr r3, [r7, #4] 8010372: 2202 movs r2, #2 8010374: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 8010378: 687b ldr r3, [r7, #4] 801037a: 681b ldr r3, [r3, #0] 801037c: 689b ldr r3, [r3, #8] 801037e: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 8010380: 68ba ldr r2, [r7, #8] 8010382: 4b6a ldr r3, [pc, #424] @ (801052c ) 8010384: 4013 ands r3, r2 8010386: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8010388: 68bb ldr r3, [r7, #8] 801038a: f423 437f bic.w r3, r3, #65280 @ 0xff00 801038e: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 8010390: 687b ldr r3, [r7, #4] 8010392: 681b ldr r3, [r3, #0] 8010394: 68ba ldr r2, [r7, #8] 8010396: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 8010398: 683b ldr r3, [r7, #0] 801039a: 681b ldr r3, [r3, #0] 801039c: 4a64 ldr r2, [pc, #400] @ (8010530 ) 801039e: 4293 cmp r3, r2 80103a0: f000 80a9 beq.w 80104f6 80103a4: 4a62 ldr r2, [pc, #392] @ (8010530 ) 80103a6: 4293 cmp r3, r2 80103a8: f200 80ae bhi.w 8010508 80103ac: 4a61 ldr r2, [pc, #388] @ (8010534 ) 80103ae: 4293 cmp r3, r2 80103b0: f000 80a1 beq.w 80104f6 80103b4: 4a5f ldr r2, [pc, #380] @ (8010534 ) 80103b6: 4293 cmp r3, r2 80103b8: f200 80a6 bhi.w 8010508 80103bc: 4a5e ldr r2, [pc, #376] @ (8010538 ) 80103be: 4293 cmp r3, r2 80103c0: f000 8099 beq.w 80104f6 80103c4: 4a5c ldr r2, [pc, #368] @ (8010538 ) 80103c6: 4293 cmp r3, r2 80103c8: f200 809e bhi.w 8010508 80103cc: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 80103d0: f000 8091 beq.w 80104f6 80103d4: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 80103d8: f200 8096 bhi.w 8010508 80103dc: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80103e0: f000 8089 beq.w 80104f6 80103e4: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80103e8: f200 808e bhi.w 8010508 80103ec: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80103f0: d03e beq.n 8010470 80103f2: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80103f6: f200 8087 bhi.w 8010508 80103fa: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80103fe: f000 8086 beq.w 801050e 8010402: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8010406: d87f bhi.n 8010508 8010408: 2b70 cmp r3, #112 @ 0x70 801040a: d01a beq.n 8010442 801040c: 2b70 cmp r3, #112 @ 0x70 801040e: d87b bhi.n 8010508 8010410: 2b60 cmp r3, #96 @ 0x60 8010412: d050 beq.n 80104b6 8010414: 2b60 cmp r3, #96 @ 0x60 8010416: d877 bhi.n 8010508 8010418: 2b50 cmp r3, #80 @ 0x50 801041a: d03c beq.n 8010496 801041c: 2b50 cmp r3, #80 @ 0x50 801041e: d873 bhi.n 8010508 8010420: 2b40 cmp r3, #64 @ 0x40 8010422: d058 beq.n 80104d6 8010424: 2b40 cmp r3, #64 @ 0x40 8010426: d86f bhi.n 8010508 8010428: 2b30 cmp r3, #48 @ 0x30 801042a: d064 beq.n 80104f6 801042c: 2b30 cmp r3, #48 @ 0x30 801042e: d86b bhi.n 8010508 8010430: 2b20 cmp r3, #32 8010432: d060 beq.n 80104f6 8010434: 2b20 cmp r3, #32 8010436: d867 bhi.n 8010508 8010438: 2b00 cmp r3, #0 801043a: d05c beq.n 80104f6 801043c: 2b10 cmp r3, #16 801043e: d05a beq.n 80104f6 8010440: e062 b.n 8010508 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8010442: 687b ldr r3, [r7, #4] 8010444: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8010446: 683b ldr r3, [r7, #0] 8010448: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 801044a: 683b ldr r3, [r7, #0] 801044c: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 801044e: 683b ldr r3, [r7, #0] 8010450: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8010452: f000 fe33 bl 80110bc /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 8010456: 687b ldr r3, [r7, #4] 8010458: 681b ldr r3, [r3, #0] 801045a: 689b ldr r3, [r3, #8] 801045c: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 801045e: 68bb ldr r3, [r7, #8] 8010460: f043 0377 orr.w r3, r3, #119 @ 0x77 8010464: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8010466: 687b ldr r3, [r7, #4] 8010468: 681b ldr r3, [r3, #0] 801046a: 68ba ldr r2, [r7, #8] 801046c: 609a str r2, [r3, #8] break; 801046e: e04f b.n 8010510 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8010470: 687b ldr r3, [r7, #4] 8010472: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8010474: 683b ldr r3, [r7, #0] 8010476: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 8010478: 683b ldr r3, [r7, #0] 801047a: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 801047c: 683b ldr r3, [r7, #0] 801047e: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8010480: f000 fe1c bl 80110bc /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 8010484: 687b ldr r3, [r7, #4] 8010486: 681b ldr r3, [r3, #0] 8010488: 689a ldr r2, [r3, #8] 801048a: 687b ldr r3, [r7, #4] 801048c: 681b ldr r3, [r3, #0] 801048e: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8010492: 609a str r2, [r3, #8] break; 8010494: e03c b.n 8010510 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8010496: 687b ldr r3, [r7, #4] 8010498: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 801049a: 683b ldr r3, [r7, #0] 801049c: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 801049e: 683b ldr r3, [r7, #0] 80104a0: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 80104a2: 461a mov r2, r3 80104a4: f000 fcd6 bl 8010e54 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 80104a8: 687b ldr r3, [r7, #4] 80104aa: 681b ldr r3, [r3, #0] 80104ac: 2150 movs r1, #80 @ 0x50 80104ae: 4618 mov r0, r3 80104b0: f000 fde6 bl 8011080 break; 80104b4: e02c b.n 8010510 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 80104b6: 687b ldr r3, [r7, #4] 80104b8: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80104ba: 683b ldr r3, [r7, #0] 80104bc: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80104be: 683b ldr r3, [r7, #0] 80104c0: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 80104c2: 461a mov r2, r3 80104c4: f000 fd32 bl 8010f2c TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 80104c8: 687b ldr r3, [r7, #4] 80104ca: 681b ldr r3, [r3, #0] 80104cc: 2160 movs r1, #96 @ 0x60 80104ce: 4618 mov r0, r3 80104d0: f000 fdd6 bl 8011080 break; 80104d4: e01c b.n 8010510 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 80104d6: 687b ldr r3, [r7, #4] 80104d8: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80104da: 683b ldr r3, [r7, #0] 80104dc: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80104de: 683b ldr r3, [r7, #0] 80104e0: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 80104e2: 461a mov r2, r3 80104e4: f000 fcb6 bl 8010e54 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 80104e8: 687b ldr r3, [r7, #4] 80104ea: 681b ldr r3, [r3, #0] 80104ec: 2140 movs r1, #64 @ 0x40 80104ee: 4618 mov r0, r3 80104f0: f000 fdc6 bl 8011080 break; 80104f4: e00c b.n 8010510 case TIM_CLOCKSOURCE_ITR8: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 80104f6: 687b ldr r3, [r7, #4] 80104f8: 681a ldr r2, [r3, #0] 80104fa: 683b ldr r3, [r7, #0] 80104fc: 681b ldr r3, [r3, #0] 80104fe: 4619 mov r1, r3 8010500: 4610 mov r0, r2 8010502: f000 fdbd bl 8011080 break; 8010506: e003 b.n 8010510 } default: status = HAL_ERROR; 8010508: 2301 movs r3, #1 801050a: 73fb strb r3, [r7, #15] break; 801050c: e000 b.n 8010510 break; 801050e: bf00 nop } htim->State = HAL_TIM_STATE_READY; 8010510: 687b ldr r3, [r7, #4] 8010512: 2201 movs r2, #1 8010514: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8010518: 687b ldr r3, [r7, #4] 801051a: 2200 movs r2, #0 801051c: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8010520: 7bfb ldrb r3, [r7, #15] } 8010522: 4618 mov r0, r3 8010524: 3710 adds r7, #16 8010526: 46bd mov sp, r7 8010528: bd80 pop {r7, pc} 801052a: bf00 nop 801052c: ffceff88 .word 0xffceff88 8010530: 00100040 .word 0x00100040 8010534: 00100030 .word 0x00100030 8010538: 00100020 .word 0x00100020 0801053c : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval Captured value */ uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) { 801053c: b480 push {r7} 801053e: b085 sub sp, #20 8010540: af00 add r7, sp, #0 8010542: 6078 str r0, [r7, #4] 8010544: 6039 str r1, [r7, #0] uint32_t tmpreg = 0U; 8010546: 2300 movs r3, #0 8010548: 60fb str r3, [r7, #12] switch (Channel) 801054a: 683b ldr r3, [r7, #0] 801054c: 2b0c cmp r3, #12 801054e: d831 bhi.n 80105b4 8010550: a201 add r2, pc, #4 @ (adr r2, 8010558 ) 8010552: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8010556: bf00 nop 8010558: 0801058d .word 0x0801058d 801055c: 080105b5 .word 0x080105b5 8010560: 080105b5 .word 0x080105b5 8010564: 080105b5 .word 0x080105b5 8010568: 08010597 .word 0x08010597 801056c: 080105b5 .word 0x080105b5 8010570: 080105b5 .word 0x080105b5 8010574: 080105b5 .word 0x080105b5 8010578: 080105a1 .word 0x080105a1 801057c: 080105b5 .word 0x080105b5 8010580: 080105b5 .word 0x080105b5 8010584: 080105b5 .word 0x080105b5 8010588: 080105ab .word 0x080105ab { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Return the capture 1 value */ tmpreg = htim->Instance->CCR1; 801058c: 687b ldr r3, [r7, #4] 801058e: 681b ldr r3, [r3, #0] 8010590: 6b5b ldr r3, [r3, #52] @ 0x34 8010592: 60fb str r3, [r7, #12] break; 8010594: e00f b.n 80105b6 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Return the capture 2 value */ tmpreg = htim->Instance->CCR2; 8010596: 687b ldr r3, [r7, #4] 8010598: 681b ldr r3, [r3, #0] 801059a: 6b9b ldr r3, [r3, #56] @ 0x38 801059c: 60fb str r3, [r7, #12] break; 801059e: e00a b.n 80105b6 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Return the capture 3 value */ tmpreg = htim->Instance->CCR3; 80105a0: 687b ldr r3, [r7, #4] 80105a2: 681b ldr r3, [r3, #0] 80105a4: 6bdb ldr r3, [r3, #60] @ 0x3c 80105a6: 60fb str r3, [r7, #12] break; 80105a8: e005 b.n 80105b6 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Return the capture 4 value */ tmpreg = htim->Instance->CCR4; 80105aa: 687b ldr r3, [r7, #4] 80105ac: 681b ldr r3, [r3, #0] 80105ae: 6c1b ldr r3, [r3, #64] @ 0x40 80105b0: 60fb str r3, [r7, #12] break; 80105b2: e000 b.n 80105b6 } default: break; 80105b4: bf00 nop } return tmpreg; 80105b6: 68fb ldr r3, [r7, #12] } 80105b8: 4618 mov r0, r3 80105ba: 3714 adds r7, #20 80105bc: 46bd mov sp, r7 80105be: f85d 7b04 ldr.w r7, [sp], #4 80105c2: 4770 bx lr 080105c4 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 80105c4: b480 push {r7} 80105c6: b083 sub sp, #12 80105c8: af00 add r7, sp, #0 80105ca: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 80105cc: bf00 nop 80105ce: 370c adds r7, #12 80105d0: 46bd mov sp, r7 80105d2: f85d 7b04 ldr.w r7, [sp], #4 80105d6: 4770 bx lr 080105d8 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 80105d8: b480 push {r7} 80105da: b083 sub sp, #12 80105dc: af00 add r7, sp, #0 80105de: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 80105e0: bf00 nop 80105e2: 370c adds r7, #12 80105e4: 46bd mov sp, r7 80105e6: f85d 7b04 ldr.w r7, [sp], #4 80105ea: 4770 bx lr 080105ec : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 80105ec: b480 push {r7} 80105ee: b083 sub sp, #12 80105f0: af00 add r7, sp, #0 80105f2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 80105f4: bf00 nop 80105f6: 370c adds r7, #12 80105f8: 46bd mov sp, r7 80105fa: f85d 7b04 ldr.w r7, [sp], #4 80105fe: 4770 bx lr 08010600 : * @arg TIM_CHANNEL_5: TIM Channel 5 * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) { 8010600: b480 push {r7} 8010602: b085 sub sp, #20 8010604: af00 add r7, sp, #0 8010606: 6078 str r0, [r7, #4] 8010608: 6039 str r1, [r7, #0] HAL_TIM_ChannelStateTypeDef channel_state; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); 801060a: 683b ldr r3, [r7, #0] 801060c: 2b00 cmp r3, #0 801060e: d104 bne.n 801061a 8010610: 687b ldr r3, [r7, #4] 8010612: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8010616: b2db uxtb r3, r3 8010618: e023 b.n 8010662 801061a: 683b ldr r3, [r7, #0] 801061c: 2b04 cmp r3, #4 801061e: d104 bne.n 801062a 8010620: 687b ldr r3, [r7, #4] 8010622: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8010626: b2db uxtb r3, r3 8010628: e01b b.n 8010662 801062a: 683b ldr r3, [r7, #0] 801062c: 2b08 cmp r3, #8 801062e: d104 bne.n 801063a 8010630: 687b ldr r3, [r7, #4] 8010632: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8010636: b2db uxtb r3, r3 8010638: e013 b.n 8010662 801063a: 683b ldr r3, [r7, #0] 801063c: 2b0c cmp r3, #12 801063e: d104 bne.n 801064a 8010640: 687b ldr r3, [r7, #4] 8010642: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8010646: b2db uxtb r3, r3 8010648: e00b b.n 8010662 801064a: 683b ldr r3, [r7, #0] 801064c: 2b10 cmp r3, #16 801064e: d104 bne.n 801065a 8010650: 687b ldr r3, [r7, #4] 8010652: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8010656: b2db uxtb r3, r3 8010658: e003 b.n 8010662 801065a: 687b ldr r3, [r7, #4] 801065c: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 8010660: b2db uxtb r3, r3 8010662: 73fb strb r3, [r7, #15] return channel_state; 8010664: 7bfb ldrb r3, [r7, #15] } 8010666: 4618 mov r0, r3 8010668: 3714 adds r7, #20 801066a: 46bd mov sp, r7 801066c: f85d 7b04 ldr.w r7, [sp], #4 8010670: 4770 bx lr ... 08010674 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8010674: b480 push {r7} 8010676: b085 sub sp, #20 8010678: af00 add r7, sp, #0 801067a: 6078 str r0, [r7, #4] 801067c: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 801067e: 687b ldr r3, [r7, #4] 8010680: 681b ldr r3, [r3, #0] 8010682: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8010684: 687b ldr r3, [r7, #4] 8010686: 4a46 ldr r2, [pc, #280] @ (80107a0 ) 8010688: 4293 cmp r3, r2 801068a: d013 beq.n 80106b4 801068c: 687b ldr r3, [r7, #4] 801068e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8010692: d00f beq.n 80106b4 8010694: 687b ldr r3, [r7, #4] 8010696: 4a43 ldr r2, [pc, #268] @ (80107a4 ) 8010698: 4293 cmp r3, r2 801069a: d00b beq.n 80106b4 801069c: 687b ldr r3, [r7, #4] 801069e: 4a42 ldr r2, [pc, #264] @ (80107a8 ) 80106a0: 4293 cmp r3, r2 80106a2: d007 beq.n 80106b4 80106a4: 687b ldr r3, [r7, #4] 80106a6: 4a41 ldr r2, [pc, #260] @ (80107ac ) 80106a8: 4293 cmp r3, r2 80106aa: d003 beq.n 80106b4 80106ac: 687b ldr r3, [r7, #4] 80106ae: 4a40 ldr r2, [pc, #256] @ (80107b0 ) 80106b0: 4293 cmp r3, r2 80106b2: d108 bne.n 80106c6 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80106b4: 68fb ldr r3, [r7, #12] 80106b6: f023 0370 bic.w r3, r3, #112 @ 0x70 80106ba: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80106bc: 683b ldr r3, [r7, #0] 80106be: 685b ldr r3, [r3, #4] 80106c0: 68fa ldr r2, [r7, #12] 80106c2: 4313 orrs r3, r2 80106c4: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80106c6: 687b ldr r3, [r7, #4] 80106c8: 4a35 ldr r2, [pc, #212] @ (80107a0 ) 80106ca: 4293 cmp r3, r2 80106cc: d01f beq.n 801070e 80106ce: 687b ldr r3, [r7, #4] 80106d0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80106d4: d01b beq.n 801070e 80106d6: 687b ldr r3, [r7, #4] 80106d8: 4a32 ldr r2, [pc, #200] @ (80107a4 ) 80106da: 4293 cmp r3, r2 80106dc: d017 beq.n 801070e 80106de: 687b ldr r3, [r7, #4] 80106e0: 4a31 ldr r2, [pc, #196] @ (80107a8 ) 80106e2: 4293 cmp r3, r2 80106e4: d013 beq.n 801070e 80106e6: 687b ldr r3, [r7, #4] 80106e8: 4a30 ldr r2, [pc, #192] @ (80107ac ) 80106ea: 4293 cmp r3, r2 80106ec: d00f beq.n 801070e 80106ee: 687b ldr r3, [r7, #4] 80106f0: 4a2f ldr r2, [pc, #188] @ (80107b0 ) 80106f2: 4293 cmp r3, r2 80106f4: d00b beq.n 801070e 80106f6: 687b ldr r3, [r7, #4] 80106f8: 4a2e ldr r2, [pc, #184] @ (80107b4 ) 80106fa: 4293 cmp r3, r2 80106fc: d007 beq.n 801070e 80106fe: 687b ldr r3, [r7, #4] 8010700: 4a2d ldr r2, [pc, #180] @ (80107b8 ) 8010702: 4293 cmp r3, r2 8010704: d003 beq.n 801070e 8010706: 687b ldr r3, [r7, #4] 8010708: 4a2c ldr r2, [pc, #176] @ (80107bc ) 801070a: 4293 cmp r3, r2 801070c: d108 bne.n 8010720 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 801070e: 68fb ldr r3, [r7, #12] 8010710: f423 7340 bic.w r3, r3, #768 @ 0x300 8010714: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8010716: 683b ldr r3, [r7, #0] 8010718: 68db ldr r3, [r3, #12] 801071a: 68fa ldr r2, [r7, #12] 801071c: 4313 orrs r3, r2 801071e: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8010720: 68fb ldr r3, [r7, #12] 8010722: f023 0280 bic.w r2, r3, #128 @ 0x80 8010726: 683b ldr r3, [r7, #0] 8010728: 695b ldr r3, [r3, #20] 801072a: 4313 orrs r3, r2 801072c: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 801072e: 687b ldr r3, [r7, #4] 8010730: 68fa ldr r2, [r7, #12] 8010732: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8010734: 683b ldr r3, [r7, #0] 8010736: 689a ldr r2, [r3, #8] 8010738: 687b ldr r3, [r7, #4] 801073a: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 801073c: 683b ldr r3, [r7, #0] 801073e: 681a ldr r2, [r3, #0] 8010740: 687b ldr r3, [r7, #4] 8010742: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8010744: 687b ldr r3, [r7, #4] 8010746: 4a16 ldr r2, [pc, #88] @ (80107a0 ) 8010748: 4293 cmp r3, r2 801074a: d00f beq.n 801076c 801074c: 687b ldr r3, [r7, #4] 801074e: 4a18 ldr r2, [pc, #96] @ (80107b0 ) 8010750: 4293 cmp r3, r2 8010752: d00b beq.n 801076c 8010754: 687b ldr r3, [r7, #4] 8010756: 4a17 ldr r2, [pc, #92] @ (80107b4 ) 8010758: 4293 cmp r3, r2 801075a: d007 beq.n 801076c 801075c: 687b ldr r3, [r7, #4] 801075e: 4a16 ldr r2, [pc, #88] @ (80107b8 ) 8010760: 4293 cmp r3, r2 8010762: d003 beq.n 801076c 8010764: 687b ldr r3, [r7, #4] 8010766: 4a15 ldr r2, [pc, #84] @ (80107bc ) 8010768: 4293 cmp r3, r2 801076a: d103 bne.n 8010774 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 801076c: 683b ldr r3, [r7, #0] 801076e: 691a ldr r2, [r3, #16] 8010770: 687b ldr r3, [r7, #4] 8010772: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8010774: 687b ldr r3, [r7, #4] 8010776: 2201 movs r2, #1 8010778: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 801077a: 687b ldr r3, [r7, #4] 801077c: 691b ldr r3, [r3, #16] 801077e: f003 0301 and.w r3, r3, #1 8010782: 2b01 cmp r3, #1 8010784: d105 bne.n 8010792 { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 8010786: 687b ldr r3, [r7, #4] 8010788: 691b ldr r3, [r3, #16] 801078a: f023 0201 bic.w r2, r3, #1 801078e: 687b ldr r3, [r7, #4] 8010790: 611a str r2, [r3, #16] } } 8010792: bf00 nop 8010794: 3714 adds r7, #20 8010796: 46bd mov sp, r7 8010798: f85d 7b04 ldr.w r7, [sp], #4 801079c: 4770 bx lr 801079e: bf00 nop 80107a0: 40010000 .word 0x40010000 80107a4: 40000400 .word 0x40000400 80107a8: 40000800 .word 0x40000800 80107ac: 40000c00 .word 0x40000c00 80107b0: 40010400 .word 0x40010400 80107b4: 40014000 .word 0x40014000 80107b8: 40014400 .word 0x40014400 80107bc: 40014800 .word 0x40014800 080107c0 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80107c0: b480 push {r7} 80107c2: b087 sub sp, #28 80107c4: af00 add r7, sp, #0 80107c6: 6078 str r0, [r7, #4] 80107c8: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80107ca: 687b ldr r3, [r7, #4] 80107cc: 6a1b ldr r3, [r3, #32] 80107ce: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 80107d0: 687b ldr r3, [r7, #4] 80107d2: 6a1b ldr r3, [r3, #32] 80107d4: f023 0201 bic.w r2, r3, #1 80107d8: 687b ldr r3, [r7, #4] 80107da: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80107dc: 687b ldr r3, [r7, #4] 80107de: 685b ldr r3, [r3, #4] 80107e0: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80107e2: 687b ldr r3, [r7, #4] 80107e4: 699b ldr r3, [r3, #24] 80107e6: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 80107e8: 68fa ldr r2, [r7, #12] 80107ea: 4b37 ldr r3, [pc, #220] @ (80108c8 ) 80107ec: 4013 ands r3, r2 80107ee: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 80107f0: 68fb ldr r3, [r7, #12] 80107f2: f023 0303 bic.w r3, r3, #3 80107f6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80107f8: 683b ldr r3, [r7, #0] 80107fa: 681b ldr r3, [r3, #0] 80107fc: 68fa ldr r2, [r7, #12] 80107fe: 4313 orrs r3, r2 8010800: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 8010802: 697b ldr r3, [r7, #20] 8010804: f023 0302 bic.w r3, r3, #2 8010808: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 801080a: 683b ldr r3, [r7, #0] 801080c: 689b ldr r3, [r3, #8] 801080e: 697a ldr r2, [r7, #20] 8010810: 4313 orrs r3, r2 8010812: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8010814: 687b ldr r3, [r7, #4] 8010816: 4a2d ldr r2, [pc, #180] @ (80108cc ) 8010818: 4293 cmp r3, r2 801081a: d00f beq.n 801083c 801081c: 687b ldr r3, [r7, #4] 801081e: 4a2c ldr r2, [pc, #176] @ (80108d0 ) 8010820: 4293 cmp r3, r2 8010822: d00b beq.n 801083c 8010824: 687b ldr r3, [r7, #4] 8010826: 4a2b ldr r2, [pc, #172] @ (80108d4 ) 8010828: 4293 cmp r3, r2 801082a: d007 beq.n 801083c 801082c: 687b ldr r3, [r7, #4] 801082e: 4a2a ldr r2, [pc, #168] @ (80108d8 ) 8010830: 4293 cmp r3, r2 8010832: d003 beq.n 801083c 8010834: 687b ldr r3, [r7, #4] 8010836: 4a29 ldr r2, [pc, #164] @ (80108dc ) 8010838: 4293 cmp r3, r2 801083a: d10c bne.n 8010856 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 801083c: 697b ldr r3, [r7, #20] 801083e: f023 0308 bic.w r3, r3, #8 8010842: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8010844: 683b ldr r3, [r7, #0] 8010846: 68db ldr r3, [r3, #12] 8010848: 697a ldr r2, [r7, #20] 801084a: 4313 orrs r3, r2 801084c: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 801084e: 697b ldr r3, [r7, #20] 8010850: f023 0304 bic.w r3, r3, #4 8010854: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010856: 687b ldr r3, [r7, #4] 8010858: 4a1c ldr r2, [pc, #112] @ (80108cc ) 801085a: 4293 cmp r3, r2 801085c: d00f beq.n 801087e 801085e: 687b ldr r3, [r7, #4] 8010860: 4a1b ldr r2, [pc, #108] @ (80108d0 ) 8010862: 4293 cmp r3, r2 8010864: d00b beq.n 801087e 8010866: 687b ldr r3, [r7, #4] 8010868: 4a1a ldr r2, [pc, #104] @ (80108d4 ) 801086a: 4293 cmp r3, r2 801086c: d007 beq.n 801087e 801086e: 687b ldr r3, [r7, #4] 8010870: 4a19 ldr r2, [pc, #100] @ (80108d8 ) 8010872: 4293 cmp r3, r2 8010874: d003 beq.n 801087e 8010876: 687b ldr r3, [r7, #4] 8010878: 4a18 ldr r2, [pc, #96] @ (80108dc ) 801087a: 4293 cmp r3, r2 801087c: d111 bne.n 80108a2 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 801087e: 693b ldr r3, [r7, #16] 8010880: f423 7380 bic.w r3, r3, #256 @ 0x100 8010884: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 8010886: 693b ldr r3, [r7, #16] 8010888: f423 7300 bic.w r3, r3, #512 @ 0x200 801088c: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 801088e: 683b ldr r3, [r7, #0] 8010890: 695b ldr r3, [r3, #20] 8010892: 693a ldr r2, [r7, #16] 8010894: 4313 orrs r3, r2 8010896: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8010898: 683b ldr r3, [r7, #0] 801089a: 699b ldr r3, [r3, #24] 801089c: 693a ldr r2, [r7, #16] 801089e: 4313 orrs r3, r2 80108a0: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80108a2: 687b ldr r3, [r7, #4] 80108a4: 693a ldr r2, [r7, #16] 80108a6: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80108a8: 687b ldr r3, [r7, #4] 80108aa: 68fa ldr r2, [r7, #12] 80108ac: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 80108ae: 683b ldr r3, [r7, #0] 80108b0: 685a ldr r2, [r3, #4] 80108b2: 687b ldr r3, [r7, #4] 80108b4: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80108b6: 687b ldr r3, [r7, #4] 80108b8: 697a ldr r2, [r7, #20] 80108ba: 621a str r2, [r3, #32] } 80108bc: bf00 nop 80108be: 371c adds r7, #28 80108c0: 46bd mov sp, r7 80108c2: f85d 7b04 ldr.w r7, [sp], #4 80108c6: 4770 bx lr 80108c8: fffeff8f .word 0xfffeff8f 80108cc: 40010000 .word 0x40010000 80108d0: 40010400 .word 0x40010400 80108d4: 40014000 .word 0x40014000 80108d8: 40014400 .word 0x40014400 80108dc: 40014800 .word 0x40014800 080108e0 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80108e0: b480 push {r7} 80108e2: b087 sub sp, #28 80108e4: af00 add r7, sp, #0 80108e6: 6078 str r0, [r7, #4] 80108e8: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80108ea: 687b ldr r3, [r7, #4] 80108ec: 6a1b ldr r3, [r3, #32] 80108ee: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 80108f0: 687b ldr r3, [r7, #4] 80108f2: 6a1b ldr r3, [r3, #32] 80108f4: f023 0210 bic.w r2, r3, #16 80108f8: 687b ldr r3, [r7, #4] 80108fa: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80108fc: 687b ldr r3, [r7, #4] 80108fe: 685b ldr r3, [r3, #4] 8010900: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8010902: 687b ldr r3, [r7, #4] 8010904: 699b ldr r3, [r3, #24] 8010906: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 8010908: 68fa ldr r2, [r7, #12] 801090a: 4b34 ldr r3, [pc, #208] @ (80109dc ) 801090c: 4013 ands r3, r2 801090e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8010910: 68fb ldr r3, [r7, #12] 8010912: f423 7340 bic.w r3, r3, #768 @ 0x300 8010916: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8010918: 683b ldr r3, [r7, #0] 801091a: 681b ldr r3, [r3, #0] 801091c: 021b lsls r3, r3, #8 801091e: 68fa ldr r2, [r7, #12] 8010920: 4313 orrs r3, r2 8010922: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 8010924: 697b ldr r3, [r7, #20] 8010926: f023 0320 bic.w r3, r3, #32 801092a: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 801092c: 683b ldr r3, [r7, #0] 801092e: 689b ldr r3, [r3, #8] 8010930: 011b lsls r3, r3, #4 8010932: 697a ldr r2, [r7, #20] 8010934: 4313 orrs r3, r2 8010936: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 8010938: 687b ldr r3, [r7, #4] 801093a: 4a29 ldr r2, [pc, #164] @ (80109e0 ) 801093c: 4293 cmp r3, r2 801093e: d003 beq.n 8010948 8010940: 687b ldr r3, [r7, #4] 8010942: 4a28 ldr r2, [pc, #160] @ (80109e4 ) 8010944: 4293 cmp r3, r2 8010946: d10d bne.n 8010964 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 8010948: 697b ldr r3, [r7, #20] 801094a: f023 0380 bic.w r3, r3, #128 @ 0x80 801094e: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8010950: 683b ldr r3, [r7, #0] 8010952: 68db ldr r3, [r3, #12] 8010954: 011b lsls r3, r3, #4 8010956: 697a ldr r2, [r7, #20] 8010958: 4313 orrs r3, r2 801095a: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 801095c: 697b ldr r3, [r7, #20] 801095e: f023 0340 bic.w r3, r3, #64 @ 0x40 8010962: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010964: 687b ldr r3, [r7, #4] 8010966: 4a1e ldr r2, [pc, #120] @ (80109e0 ) 8010968: 4293 cmp r3, r2 801096a: d00f beq.n 801098c 801096c: 687b ldr r3, [r7, #4] 801096e: 4a1d ldr r2, [pc, #116] @ (80109e4 ) 8010970: 4293 cmp r3, r2 8010972: d00b beq.n 801098c 8010974: 687b ldr r3, [r7, #4] 8010976: 4a1c ldr r2, [pc, #112] @ (80109e8 ) 8010978: 4293 cmp r3, r2 801097a: d007 beq.n 801098c 801097c: 687b ldr r3, [r7, #4] 801097e: 4a1b ldr r2, [pc, #108] @ (80109ec ) 8010980: 4293 cmp r3, r2 8010982: d003 beq.n 801098c 8010984: 687b ldr r3, [r7, #4] 8010986: 4a1a ldr r2, [pc, #104] @ (80109f0 ) 8010988: 4293 cmp r3, r2 801098a: d113 bne.n 80109b4 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 801098c: 693b ldr r3, [r7, #16] 801098e: f423 6380 bic.w r3, r3, #1024 @ 0x400 8010992: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8010994: 693b ldr r3, [r7, #16] 8010996: f423 6300 bic.w r3, r3, #2048 @ 0x800 801099a: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 801099c: 683b ldr r3, [r7, #0] 801099e: 695b ldr r3, [r3, #20] 80109a0: 009b lsls r3, r3, #2 80109a2: 693a ldr r2, [r7, #16] 80109a4: 4313 orrs r3, r2 80109a6: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 80109a8: 683b ldr r3, [r7, #0] 80109aa: 699b ldr r3, [r3, #24] 80109ac: 009b lsls r3, r3, #2 80109ae: 693a ldr r2, [r7, #16] 80109b0: 4313 orrs r3, r2 80109b2: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80109b4: 687b ldr r3, [r7, #4] 80109b6: 693a ldr r2, [r7, #16] 80109b8: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80109ba: 687b ldr r3, [r7, #4] 80109bc: 68fa ldr r2, [r7, #12] 80109be: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 80109c0: 683b ldr r3, [r7, #0] 80109c2: 685a ldr r2, [r3, #4] 80109c4: 687b ldr r3, [r7, #4] 80109c6: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80109c8: 687b ldr r3, [r7, #4] 80109ca: 697a ldr r2, [r7, #20] 80109cc: 621a str r2, [r3, #32] } 80109ce: bf00 nop 80109d0: 371c adds r7, #28 80109d2: 46bd mov sp, r7 80109d4: f85d 7b04 ldr.w r7, [sp], #4 80109d8: 4770 bx lr 80109da: bf00 nop 80109dc: feff8fff .word 0xfeff8fff 80109e0: 40010000 .word 0x40010000 80109e4: 40010400 .word 0x40010400 80109e8: 40014000 .word 0x40014000 80109ec: 40014400 .word 0x40014400 80109f0: 40014800 .word 0x40014800 080109f4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80109f4: b480 push {r7} 80109f6: b087 sub sp, #28 80109f8: af00 add r7, sp, #0 80109fa: 6078 str r0, [r7, #4] 80109fc: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80109fe: 687b ldr r3, [r7, #4] 8010a00: 6a1b ldr r3, [r3, #32] 8010a02: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8010a04: 687b ldr r3, [r7, #4] 8010a06: 6a1b ldr r3, [r3, #32] 8010a08: f423 7280 bic.w r2, r3, #256 @ 0x100 8010a0c: 687b ldr r3, [r7, #4] 8010a0e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010a10: 687b ldr r3, [r7, #4] 8010a12: 685b ldr r3, [r3, #4] 8010a14: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8010a16: 687b ldr r3, [r7, #4] 8010a18: 69db ldr r3, [r3, #28] 8010a1a: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8010a1c: 68fa ldr r2, [r7, #12] 8010a1e: 4b33 ldr r3, [pc, #204] @ (8010aec ) 8010a20: 4013 ands r3, r2 8010a22: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8010a24: 68fb ldr r3, [r7, #12] 8010a26: f023 0303 bic.w r3, r3, #3 8010a2a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8010a2c: 683b ldr r3, [r7, #0] 8010a2e: 681b ldr r3, [r3, #0] 8010a30: 68fa ldr r2, [r7, #12] 8010a32: 4313 orrs r3, r2 8010a34: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8010a36: 697b ldr r3, [r7, #20] 8010a38: f423 7300 bic.w r3, r3, #512 @ 0x200 8010a3c: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 8010a3e: 683b ldr r3, [r7, #0] 8010a40: 689b ldr r3, [r3, #8] 8010a42: 021b lsls r3, r3, #8 8010a44: 697a ldr r2, [r7, #20] 8010a46: 4313 orrs r3, r2 8010a48: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8010a4a: 687b ldr r3, [r7, #4] 8010a4c: 4a28 ldr r2, [pc, #160] @ (8010af0 ) 8010a4e: 4293 cmp r3, r2 8010a50: d003 beq.n 8010a5a 8010a52: 687b ldr r3, [r7, #4] 8010a54: 4a27 ldr r2, [pc, #156] @ (8010af4 ) 8010a56: 4293 cmp r3, r2 8010a58: d10d bne.n 8010a76 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8010a5a: 697b ldr r3, [r7, #20] 8010a5c: f423 6300 bic.w r3, r3, #2048 @ 0x800 8010a60: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 8010a62: 683b ldr r3, [r7, #0] 8010a64: 68db ldr r3, [r3, #12] 8010a66: 021b lsls r3, r3, #8 8010a68: 697a ldr r2, [r7, #20] 8010a6a: 4313 orrs r3, r2 8010a6c: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8010a6e: 697b ldr r3, [r7, #20] 8010a70: f423 6380 bic.w r3, r3, #1024 @ 0x400 8010a74: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010a76: 687b ldr r3, [r7, #4] 8010a78: 4a1d ldr r2, [pc, #116] @ (8010af0 ) 8010a7a: 4293 cmp r3, r2 8010a7c: d00f beq.n 8010a9e 8010a7e: 687b ldr r3, [r7, #4] 8010a80: 4a1c ldr r2, [pc, #112] @ (8010af4 ) 8010a82: 4293 cmp r3, r2 8010a84: d00b beq.n 8010a9e 8010a86: 687b ldr r3, [r7, #4] 8010a88: 4a1b ldr r2, [pc, #108] @ (8010af8 ) 8010a8a: 4293 cmp r3, r2 8010a8c: d007 beq.n 8010a9e 8010a8e: 687b ldr r3, [r7, #4] 8010a90: 4a1a ldr r2, [pc, #104] @ (8010afc ) 8010a92: 4293 cmp r3, r2 8010a94: d003 beq.n 8010a9e 8010a96: 687b ldr r3, [r7, #4] 8010a98: 4a19 ldr r2, [pc, #100] @ (8010b00 ) 8010a9a: 4293 cmp r3, r2 8010a9c: d113 bne.n 8010ac6 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8010a9e: 693b ldr r3, [r7, #16] 8010aa0: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8010aa4: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8010aa6: 693b ldr r3, [r7, #16] 8010aa8: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8010aac: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8010aae: 683b ldr r3, [r7, #0] 8010ab0: 695b ldr r3, [r3, #20] 8010ab2: 011b lsls r3, r3, #4 8010ab4: 693a ldr r2, [r7, #16] 8010ab6: 4313 orrs r3, r2 8010ab8: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 8010aba: 683b ldr r3, [r7, #0] 8010abc: 699b ldr r3, [r3, #24] 8010abe: 011b lsls r3, r3, #4 8010ac0: 693a ldr r2, [r7, #16] 8010ac2: 4313 orrs r3, r2 8010ac4: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010ac6: 687b ldr r3, [r7, #4] 8010ac8: 693a ldr r2, [r7, #16] 8010aca: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8010acc: 687b ldr r3, [r7, #4] 8010ace: 68fa ldr r2, [r7, #12] 8010ad0: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8010ad2: 683b ldr r3, [r7, #0] 8010ad4: 685a ldr r2, [r3, #4] 8010ad6: 687b ldr r3, [r7, #4] 8010ad8: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010ada: 687b ldr r3, [r7, #4] 8010adc: 697a ldr r2, [r7, #20] 8010ade: 621a str r2, [r3, #32] } 8010ae0: bf00 nop 8010ae2: 371c adds r7, #28 8010ae4: 46bd mov sp, r7 8010ae6: f85d 7b04 ldr.w r7, [sp], #4 8010aea: 4770 bx lr 8010aec: fffeff8f .word 0xfffeff8f 8010af0: 40010000 .word 0x40010000 8010af4: 40010400 .word 0x40010400 8010af8: 40014000 .word 0x40014000 8010afc: 40014400 .word 0x40014400 8010b00: 40014800 .word 0x40014800 08010b04 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010b04: b480 push {r7} 8010b06: b087 sub sp, #28 8010b08: af00 add r7, sp, #0 8010b0a: 6078 str r0, [r7, #4] 8010b0c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010b0e: 687b ldr r3, [r7, #4] 8010b10: 6a1b ldr r3, [r3, #32] 8010b12: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8010b14: 687b ldr r3, [r7, #4] 8010b16: 6a1b ldr r3, [r3, #32] 8010b18: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8010b1c: 687b ldr r3, [r7, #4] 8010b1e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010b20: 687b ldr r3, [r7, #4] 8010b22: 685b ldr r3, [r3, #4] 8010b24: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8010b26: 687b ldr r3, [r7, #4] 8010b28: 69db ldr r3, [r3, #28] 8010b2a: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8010b2c: 68fa ldr r2, [r7, #12] 8010b2e: 4b24 ldr r3, [pc, #144] @ (8010bc0 ) 8010b30: 4013 ands r3, r2 8010b32: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8010b34: 68fb ldr r3, [r7, #12] 8010b36: f423 7340 bic.w r3, r3, #768 @ 0x300 8010b3a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8010b3c: 683b ldr r3, [r7, #0] 8010b3e: 681b ldr r3, [r3, #0] 8010b40: 021b lsls r3, r3, #8 8010b42: 68fa ldr r2, [r7, #12] 8010b44: 4313 orrs r3, r2 8010b46: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8010b48: 693b ldr r3, [r7, #16] 8010b4a: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8010b4e: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8010b50: 683b ldr r3, [r7, #0] 8010b52: 689b ldr r3, [r3, #8] 8010b54: 031b lsls r3, r3, #12 8010b56: 693a ldr r2, [r7, #16] 8010b58: 4313 orrs r3, r2 8010b5a: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010b5c: 687b ldr r3, [r7, #4] 8010b5e: 4a19 ldr r2, [pc, #100] @ (8010bc4 ) 8010b60: 4293 cmp r3, r2 8010b62: d00f beq.n 8010b84 8010b64: 687b ldr r3, [r7, #4] 8010b66: 4a18 ldr r2, [pc, #96] @ (8010bc8 ) 8010b68: 4293 cmp r3, r2 8010b6a: d00b beq.n 8010b84 8010b6c: 687b ldr r3, [r7, #4] 8010b6e: 4a17 ldr r2, [pc, #92] @ (8010bcc ) 8010b70: 4293 cmp r3, r2 8010b72: d007 beq.n 8010b84 8010b74: 687b ldr r3, [r7, #4] 8010b76: 4a16 ldr r2, [pc, #88] @ (8010bd0 ) 8010b78: 4293 cmp r3, r2 8010b7a: d003 beq.n 8010b84 8010b7c: 687b ldr r3, [r7, #4] 8010b7e: 4a15 ldr r2, [pc, #84] @ (8010bd4 ) 8010b80: 4293 cmp r3, r2 8010b82: d109 bne.n 8010b98 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8010b84: 697b ldr r3, [r7, #20] 8010b86: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8010b8a: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8010b8c: 683b ldr r3, [r7, #0] 8010b8e: 695b ldr r3, [r3, #20] 8010b90: 019b lsls r3, r3, #6 8010b92: 697a ldr r2, [r7, #20] 8010b94: 4313 orrs r3, r2 8010b96: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010b98: 687b ldr r3, [r7, #4] 8010b9a: 697a ldr r2, [r7, #20] 8010b9c: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8010b9e: 687b ldr r3, [r7, #4] 8010ba0: 68fa ldr r2, [r7, #12] 8010ba2: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8010ba4: 683b ldr r3, [r7, #0] 8010ba6: 685a ldr r2, [r3, #4] 8010ba8: 687b ldr r3, [r7, #4] 8010baa: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010bac: 687b ldr r3, [r7, #4] 8010bae: 693a ldr r2, [r7, #16] 8010bb0: 621a str r2, [r3, #32] } 8010bb2: bf00 nop 8010bb4: 371c adds r7, #28 8010bb6: 46bd mov sp, r7 8010bb8: f85d 7b04 ldr.w r7, [sp], #4 8010bbc: 4770 bx lr 8010bbe: bf00 nop 8010bc0: feff8fff .word 0xfeff8fff 8010bc4: 40010000 .word 0x40010000 8010bc8: 40010400 .word 0x40010400 8010bcc: 40014000 .word 0x40014000 8010bd0: 40014400 .word 0x40014400 8010bd4: 40014800 .word 0x40014800 08010bd8 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010bd8: b480 push {r7} 8010bda: b087 sub sp, #28 8010bdc: af00 add r7, sp, #0 8010bde: 6078 str r0, [r7, #4] 8010be0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010be2: 687b ldr r3, [r7, #4] 8010be4: 6a1b ldr r3, [r3, #32] 8010be6: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; 8010be8: 687b ldr r3, [r7, #4] 8010bea: 6a1b ldr r3, [r3, #32] 8010bec: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8010bf0: 687b ldr r3, [r7, #4] 8010bf2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010bf4: 687b ldr r3, [r7, #4] 8010bf6: 685b ldr r3, [r3, #4] 8010bf8: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 8010bfa: 687b ldr r3, [r7, #4] 8010bfc: 6d5b ldr r3, [r3, #84] @ 0x54 8010bfe: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); 8010c00: 68fa ldr r2, [r7, #12] 8010c02: 4b21 ldr r3, [pc, #132] @ (8010c88 ) 8010c04: 4013 ands r3, r2 8010c06: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8010c08: 683b ldr r3, [r7, #0] 8010c0a: 681b ldr r3, [r3, #0] 8010c0c: 68fa ldr r2, [r7, #12] 8010c0e: 4313 orrs r3, r2 8010c10: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; 8010c12: 693b ldr r3, [r7, #16] 8010c14: f423 3300 bic.w r3, r3, #131072 @ 0x20000 8010c18: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); 8010c1a: 683b ldr r3, [r7, #0] 8010c1c: 689b ldr r3, [r3, #8] 8010c1e: 041b lsls r3, r3, #16 8010c20: 693a ldr r2, [r7, #16] 8010c22: 4313 orrs r3, r2 8010c24: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010c26: 687b ldr r3, [r7, #4] 8010c28: 4a18 ldr r2, [pc, #96] @ (8010c8c ) 8010c2a: 4293 cmp r3, r2 8010c2c: d00f beq.n 8010c4e 8010c2e: 687b ldr r3, [r7, #4] 8010c30: 4a17 ldr r2, [pc, #92] @ (8010c90 ) 8010c32: 4293 cmp r3, r2 8010c34: d00b beq.n 8010c4e 8010c36: 687b ldr r3, [r7, #4] 8010c38: 4a16 ldr r2, [pc, #88] @ (8010c94 ) 8010c3a: 4293 cmp r3, r2 8010c3c: d007 beq.n 8010c4e 8010c3e: 687b ldr r3, [r7, #4] 8010c40: 4a15 ldr r2, [pc, #84] @ (8010c98 ) 8010c42: 4293 cmp r3, r2 8010c44: d003 beq.n 8010c4e 8010c46: 687b ldr r3, [r7, #4] 8010c48: 4a14 ldr r2, [pc, #80] @ (8010c9c ) 8010c4a: 4293 cmp r3, r2 8010c4c: d109 bne.n 8010c62 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; 8010c4e: 697b ldr r3, [r7, #20] 8010c50: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8010c54: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); 8010c56: 683b ldr r3, [r7, #0] 8010c58: 695b ldr r3, [r3, #20] 8010c5a: 021b lsls r3, r3, #8 8010c5c: 697a ldr r2, [r7, #20] 8010c5e: 4313 orrs r3, r2 8010c60: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010c62: 687b ldr r3, [r7, #4] 8010c64: 697a ldr r2, [r7, #20] 8010c66: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 8010c68: 687b ldr r3, [r7, #4] 8010c6a: 68fa ldr r2, [r7, #12] 8010c6c: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; 8010c6e: 683b ldr r3, [r7, #0] 8010c70: 685a ldr r2, [r3, #4] 8010c72: 687b ldr r3, [r7, #4] 8010c74: 659a str r2, [r3, #88] @ 0x58 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010c76: 687b ldr r3, [r7, #4] 8010c78: 693a ldr r2, [r7, #16] 8010c7a: 621a str r2, [r3, #32] } 8010c7c: bf00 nop 8010c7e: 371c adds r7, #28 8010c80: 46bd mov sp, r7 8010c82: f85d 7b04 ldr.w r7, [sp], #4 8010c86: 4770 bx lr 8010c88: fffeff8f .word 0xfffeff8f 8010c8c: 40010000 .word 0x40010000 8010c90: 40010400 .word 0x40010400 8010c94: 40014000 .word 0x40014000 8010c98: 40014400 .word 0x40014400 8010c9c: 40014800 .word 0x40014800 08010ca0 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010ca0: b480 push {r7} 8010ca2: b087 sub sp, #28 8010ca4: af00 add r7, sp, #0 8010ca6: 6078 str r0, [r7, #4] 8010ca8: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010caa: 687b ldr r3, [r7, #4] 8010cac: 6a1b ldr r3, [r3, #32] 8010cae: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; 8010cb0: 687b ldr r3, [r7, #4] 8010cb2: 6a1b ldr r3, [r3, #32] 8010cb4: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 8010cb8: 687b ldr r3, [r7, #4] 8010cba: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010cbc: 687b ldr r3, [r7, #4] 8010cbe: 685b ldr r3, [r3, #4] 8010cc0: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 8010cc2: 687b ldr r3, [r7, #4] 8010cc4: 6d5b ldr r3, [r3, #84] @ 0x54 8010cc6: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); 8010cc8: 68fa ldr r2, [r7, #12] 8010cca: 4b22 ldr r3, [pc, #136] @ (8010d54 ) 8010ccc: 4013 ands r3, r2 8010cce: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8010cd0: 683b ldr r3, [r7, #0] 8010cd2: 681b ldr r3, [r3, #0] 8010cd4: 021b lsls r3, r3, #8 8010cd6: 68fa ldr r2, [r7, #12] 8010cd8: 4313 orrs r3, r2 8010cda: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; 8010cdc: 693b ldr r3, [r7, #16] 8010cde: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8010ce2: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); 8010ce4: 683b ldr r3, [r7, #0] 8010ce6: 689b ldr r3, [r3, #8] 8010ce8: 051b lsls r3, r3, #20 8010cea: 693a ldr r2, [r7, #16] 8010cec: 4313 orrs r3, r2 8010cee: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010cf0: 687b ldr r3, [r7, #4] 8010cf2: 4a19 ldr r2, [pc, #100] @ (8010d58 ) 8010cf4: 4293 cmp r3, r2 8010cf6: d00f beq.n 8010d18 8010cf8: 687b ldr r3, [r7, #4] 8010cfa: 4a18 ldr r2, [pc, #96] @ (8010d5c ) 8010cfc: 4293 cmp r3, r2 8010cfe: d00b beq.n 8010d18 8010d00: 687b ldr r3, [r7, #4] 8010d02: 4a17 ldr r2, [pc, #92] @ (8010d60 ) 8010d04: 4293 cmp r3, r2 8010d06: d007 beq.n 8010d18 8010d08: 687b ldr r3, [r7, #4] 8010d0a: 4a16 ldr r2, [pc, #88] @ (8010d64 ) 8010d0c: 4293 cmp r3, r2 8010d0e: d003 beq.n 8010d18 8010d10: 687b ldr r3, [r7, #4] 8010d12: 4a15 ldr r2, [pc, #84] @ (8010d68 ) 8010d14: 4293 cmp r3, r2 8010d16: d109 bne.n 8010d2c { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; 8010d18: 697b ldr r3, [r7, #20] 8010d1a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010d1e: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); 8010d20: 683b ldr r3, [r7, #0] 8010d22: 695b ldr r3, [r3, #20] 8010d24: 029b lsls r3, r3, #10 8010d26: 697a ldr r2, [r7, #20] 8010d28: 4313 orrs r3, r2 8010d2a: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010d2c: 687b ldr r3, [r7, #4] 8010d2e: 697a ldr r2, [r7, #20] 8010d30: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 8010d32: 687b ldr r3, [r7, #4] 8010d34: 68fa ldr r2, [r7, #12] 8010d36: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; 8010d38: 683b ldr r3, [r7, #0] 8010d3a: 685a ldr r2, [r3, #4] 8010d3c: 687b ldr r3, [r7, #4] 8010d3e: 65da str r2, [r3, #92] @ 0x5c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010d40: 687b ldr r3, [r7, #4] 8010d42: 693a ldr r2, [r7, #16] 8010d44: 621a str r2, [r3, #32] } 8010d46: bf00 nop 8010d48: 371c adds r7, #28 8010d4a: 46bd mov sp, r7 8010d4c: f85d 7b04 ldr.w r7, [sp], #4 8010d50: 4770 bx lr 8010d52: bf00 nop 8010d54: feff8fff .word 0xfeff8fff 8010d58: 40010000 .word 0x40010000 8010d5c: 40010400 .word 0x40010400 8010d60: 40014000 .word 0x40014000 8010d64: 40014400 .word 0x40014400 8010d68: 40014800 .word 0x40014800 08010d6c : * (on channel2 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 8010d6c: b480 push {r7} 8010d6e: b087 sub sp, #28 8010d70: af00 add r7, sp, #0 8010d72: 60f8 str r0, [r7, #12] 8010d74: 60b9 str r1, [r7, #8] 8010d76: 607a str r2, [r7, #4] 8010d78: 603b str r3, [r7, #0] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8010d7a: 68fb ldr r3, [r7, #12] 8010d7c: 6a1b ldr r3, [r3, #32] 8010d7e: 613b str r3, [r7, #16] TIMx->CCER &= ~TIM_CCER_CC1E; 8010d80: 68fb ldr r3, [r7, #12] 8010d82: 6a1b ldr r3, [r3, #32] 8010d84: f023 0201 bic.w r2, r3, #1 8010d88: 68fb ldr r3, [r7, #12] 8010d8a: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010d8c: 68fb ldr r3, [r7, #12] 8010d8e: 699b ldr r3, [r3, #24] 8010d90: 617b str r3, [r7, #20] /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) 8010d92: 68fb ldr r3, [r7, #12] 8010d94: 4a28 ldr r2, [pc, #160] @ (8010e38 ) 8010d96: 4293 cmp r3, r2 8010d98: d01b beq.n 8010dd2 8010d9a: 68fb ldr r3, [r7, #12] 8010d9c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8010da0: d017 beq.n 8010dd2 8010da2: 68fb ldr r3, [r7, #12] 8010da4: 4a25 ldr r2, [pc, #148] @ (8010e3c ) 8010da6: 4293 cmp r3, r2 8010da8: d013 beq.n 8010dd2 8010daa: 68fb ldr r3, [r7, #12] 8010dac: 4a24 ldr r2, [pc, #144] @ (8010e40 ) 8010dae: 4293 cmp r3, r2 8010db0: d00f beq.n 8010dd2 8010db2: 68fb ldr r3, [r7, #12] 8010db4: 4a23 ldr r2, [pc, #140] @ (8010e44 ) 8010db6: 4293 cmp r3, r2 8010db8: d00b beq.n 8010dd2 8010dba: 68fb ldr r3, [r7, #12] 8010dbc: 4a22 ldr r2, [pc, #136] @ (8010e48 ) 8010dbe: 4293 cmp r3, r2 8010dc0: d007 beq.n 8010dd2 8010dc2: 68fb ldr r3, [r7, #12] 8010dc4: 4a21 ldr r2, [pc, #132] @ (8010e4c ) 8010dc6: 4293 cmp r3, r2 8010dc8: d003 beq.n 8010dd2 8010dca: 68fb ldr r3, [r7, #12] 8010dcc: 4a20 ldr r2, [pc, #128] @ (8010e50 ) 8010dce: 4293 cmp r3, r2 8010dd0: d101 bne.n 8010dd6 8010dd2: 2301 movs r3, #1 8010dd4: e000 b.n 8010dd8 8010dd6: 2300 movs r3, #0 8010dd8: 2b00 cmp r3, #0 8010dda: d008 beq.n 8010dee { tmpccmr1 &= ~TIM_CCMR1_CC1S; 8010ddc: 697b ldr r3, [r7, #20] 8010dde: f023 0303 bic.w r3, r3, #3 8010de2: 617b str r3, [r7, #20] tmpccmr1 |= TIM_ICSelection; 8010de4: 697a ldr r2, [r7, #20] 8010de6: 687b ldr r3, [r7, #4] 8010de8: 4313 orrs r3, r2 8010dea: 617b str r3, [r7, #20] 8010dec: e003 b.n 8010df6 } else { tmpccmr1 |= TIM_CCMR1_CC1S_0; 8010dee: 697b ldr r3, [r7, #20] 8010df0: f043 0301 orr.w r3, r3, #1 8010df4: 617b str r3, [r7, #20] } /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8010df6: 697b ldr r3, [r7, #20] 8010df8: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8010dfc: 617b str r3, [r7, #20] tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); 8010dfe: 683b ldr r3, [r7, #0] 8010e00: 011b lsls r3, r3, #4 8010e02: b2db uxtb r3, r3 8010e04: 697a ldr r2, [r7, #20] 8010e06: 4313 orrs r3, r2 8010e08: 617b str r3, [r7, #20] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8010e0a: 693b ldr r3, [r7, #16] 8010e0c: f023 030a bic.w r3, r3, #10 8010e10: 613b str r3, [r7, #16] tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); 8010e12: 68bb ldr r3, [r7, #8] 8010e14: f003 030a and.w r3, r3, #10 8010e18: 693a ldr r2, [r7, #16] 8010e1a: 4313 orrs r3, r2 8010e1c: 613b str r3, [r7, #16] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8010e1e: 68fb ldr r3, [r7, #12] 8010e20: 697a ldr r2, [r7, #20] 8010e22: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8010e24: 68fb ldr r3, [r7, #12] 8010e26: 693a ldr r2, [r7, #16] 8010e28: 621a str r2, [r3, #32] } 8010e2a: bf00 nop 8010e2c: 371c adds r7, #28 8010e2e: 46bd mov sp, r7 8010e30: f85d 7b04 ldr.w r7, [sp], #4 8010e34: 4770 bx lr 8010e36: bf00 nop 8010e38: 40010000 .word 0x40010000 8010e3c: 40000400 .word 0x40000400 8010e40: 40000800 .word 0x40000800 8010e44: 40000c00 .word 0x40000c00 8010e48: 40010400 .word 0x40010400 8010e4c: 40001800 .word 0x40001800 8010e50: 40014000 .word 0x40014000 08010e54 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8010e54: b480 push {r7} 8010e56: b087 sub sp, #28 8010e58: af00 add r7, sp, #0 8010e5a: 60f8 str r0, [r7, #12] 8010e5c: 60b9 str r1, [r7, #8] 8010e5e: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8010e60: 68fb ldr r3, [r7, #12] 8010e62: 6a1b ldr r3, [r3, #32] 8010e64: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8010e66: 68fb ldr r3, [r7, #12] 8010e68: 6a1b ldr r3, [r3, #32] 8010e6a: f023 0201 bic.w r2, r3, #1 8010e6e: 68fb ldr r3, [r7, #12] 8010e70: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010e72: 68fb ldr r3, [r7, #12] 8010e74: 699b ldr r3, [r3, #24] 8010e76: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8010e78: 693b ldr r3, [r7, #16] 8010e7a: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8010e7e: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8010e80: 687b ldr r3, [r7, #4] 8010e82: 011b lsls r3, r3, #4 8010e84: 693a ldr r2, [r7, #16] 8010e86: 4313 orrs r3, r2 8010e88: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8010e8a: 697b ldr r3, [r7, #20] 8010e8c: f023 030a bic.w r3, r3, #10 8010e90: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8010e92: 697a ldr r2, [r7, #20] 8010e94: 68bb ldr r3, [r7, #8] 8010e96: 4313 orrs r3, r2 8010e98: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8010e9a: 68fb ldr r3, [r7, #12] 8010e9c: 693a ldr r2, [r7, #16] 8010e9e: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8010ea0: 68fb ldr r3, [r7, #12] 8010ea2: 697a ldr r2, [r7, #20] 8010ea4: 621a str r2, [r3, #32] } 8010ea6: bf00 nop 8010ea8: 371c adds r7, #28 8010eaa: 46bd mov sp, r7 8010eac: f85d 7b04 ldr.w r7, [sp], #4 8010eb0: 4770 bx lr 08010eb2 : * (on channel1 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 8010eb2: b480 push {r7} 8010eb4: b087 sub sp, #28 8010eb6: af00 add r7, sp, #0 8010eb8: 60f8 str r0, [r7, #12] 8010eba: 60b9 str r1, [r7, #8] 8010ebc: 607a str r2, [r7, #4] 8010ebe: 603b str r3, [r7, #0] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8010ec0: 68fb ldr r3, [r7, #12] 8010ec2: 6a1b ldr r3, [r3, #32] 8010ec4: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8010ec6: 68fb ldr r3, [r7, #12] 8010ec8: 6a1b ldr r3, [r3, #32] 8010eca: f023 0210 bic.w r2, r3, #16 8010ece: 68fb ldr r3, [r7, #12] 8010ed0: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010ed2: 68fb ldr r3, [r7, #12] 8010ed4: 699b ldr r3, [r3, #24] 8010ed6: 613b str r3, [r7, #16] /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; 8010ed8: 693b ldr r3, [r7, #16] 8010eda: f423 7340 bic.w r3, r3, #768 @ 0x300 8010ede: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICSelection << 8U); 8010ee0: 687b ldr r3, [r7, #4] 8010ee2: 021b lsls r3, r3, #8 8010ee4: 693a ldr r2, [r7, #16] 8010ee6: 4313 orrs r3, r2 8010ee8: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8010eea: 693b ldr r3, [r7, #16] 8010eec: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8010ef0: 613b str r3, [r7, #16] tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); 8010ef2: 683b ldr r3, [r7, #0] 8010ef4: 031b lsls r3, r3, #12 8010ef6: b29b uxth r3, r3 8010ef8: 693a ldr r2, [r7, #16] 8010efa: 4313 orrs r3, r2 8010efc: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8010efe: 697b ldr r3, [r7, #20] 8010f00: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8010f04: 617b str r3, [r7, #20] tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); 8010f06: 68bb ldr r3, [r7, #8] 8010f08: 011b lsls r3, r3, #4 8010f0a: f003 03a0 and.w r3, r3, #160 @ 0xa0 8010f0e: 697a ldr r2, [r7, #20] 8010f10: 4313 orrs r3, r2 8010f12: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8010f14: 68fb ldr r3, [r7, #12] 8010f16: 693a ldr r2, [r7, #16] 8010f18: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8010f1a: 68fb ldr r3, [r7, #12] 8010f1c: 697a ldr r2, [r7, #20] 8010f1e: 621a str r2, [r3, #32] } 8010f20: bf00 nop 8010f22: 371c adds r7, #28 8010f24: 46bd mov sp, r7 8010f26: f85d 7b04 ldr.w r7, [sp], #4 8010f2a: 4770 bx lr 08010f2c : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8010f2c: b480 push {r7} 8010f2e: b087 sub sp, #28 8010f30: af00 add r7, sp, #0 8010f32: 60f8 str r0, [r7, #12] 8010f34: 60b9 str r1, [r7, #8] 8010f36: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8010f38: 68fb ldr r3, [r7, #12] 8010f3a: 6a1b ldr r3, [r3, #32] 8010f3c: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8010f3e: 68fb ldr r3, [r7, #12] 8010f40: 6a1b ldr r3, [r3, #32] 8010f42: f023 0210 bic.w r2, r3, #16 8010f46: 68fb ldr r3, [r7, #12] 8010f48: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010f4a: 68fb ldr r3, [r7, #12] 8010f4c: 699b ldr r3, [r3, #24] 8010f4e: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8010f50: 693b ldr r3, [r7, #16] 8010f52: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8010f56: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8010f58: 687b ldr r3, [r7, #4] 8010f5a: 031b lsls r3, r3, #12 8010f5c: 693a ldr r2, [r7, #16] 8010f5e: 4313 orrs r3, r2 8010f60: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8010f62: 697b ldr r3, [r7, #20] 8010f64: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8010f68: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8010f6a: 68bb ldr r3, [r7, #8] 8010f6c: 011b lsls r3, r3, #4 8010f6e: 697a ldr r2, [r7, #20] 8010f70: 4313 orrs r3, r2 8010f72: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8010f74: 68fb ldr r3, [r7, #12] 8010f76: 693a ldr r2, [r7, #16] 8010f78: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8010f7a: 68fb ldr r3, [r7, #12] 8010f7c: 697a ldr r2, [r7, #20] 8010f7e: 621a str r2, [r3, #32] } 8010f80: bf00 nop 8010f82: 371c adds r7, #28 8010f84: 46bd mov sp, r7 8010f86: f85d 7b04 ldr.w r7, [sp], #4 8010f8a: 4770 bx lr 08010f8c : * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 8010f8c: b480 push {r7} 8010f8e: b087 sub sp, #28 8010f90: af00 add r7, sp, #0 8010f92: 60f8 str r0, [r7, #12] 8010f94: 60b9 str r1, [r7, #8] 8010f96: 607a str r2, [r7, #4] 8010f98: 603b str r3, [r7, #0] uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ tmpccer = TIMx->CCER; 8010f9a: 68fb ldr r3, [r7, #12] 8010f9c: 6a1b ldr r3, [r3, #32] 8010f9e: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC3E; 8010fa0: 68fb ldr r3, [r7, #12] 8010fa2: 6a1b ldr r3, [r3, #32] 8010fa4: f423 7280 bic.w r2, r3, #256 @ 0x100 8010fa8: 68fb ldr r3, [r7, #12] 8010faa: 621a str r2, [r3, #32] tmpccmr2 = TIMx->CCMR2; 8010fac: 68fb ldr r3, [r7, #12] 8010fae: 69db ldr r3, [r3, #28] 8010fb0: 613b str r3, [r7, #16] /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; 8010fb2: 693b ldr r3, [r7, #16] 8010fb4: f023 0303 bic.w r3, r3, #3 8010fb8: 613b str r3, [r7, #16] tmpccmr2 |= TIM_ICSelection; 8010fba: 693a ldr r2, [r7, #16] 8010fbc: 687b ldr r3, [r7, #4] 8010fbe: 4313 orrs r3, r2 8010fc0: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; 8010fc2: 693b ldr r3, [r7, #16] 8010fc4: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8010fc8: 613b str r3, [r7, #16] tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); 8010fca: 683b ldr r3, [r7, #0] 8010fcc: 011b lsls r3, r3, #4 8010fce: b2db uxtb r3, r3 8010fd0: 693a ldr r2, [r7, #16] 8010fd2: 4313 orrs r3, r2 8010fd4: 613b str r3, [r7, #16] /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); 8010fd6: 697b ldr r3, [r7, #20] 8010fd8: f423 6320 bic.w r3, r3, #2560 @ 0xa00 8010fdc: 617b str r3, [r7, #20] tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); 8010fde: 68bb ldr r3, [r7, #8] 8010fe0: 021b lsls r3, r3, #8 8010fe2: f403 6320 and.w r3, r3, #2560 @ 0xa00 8010fe6: 697a ldr r2, [r7, #20] 8010fe8: 4313 orrs r3, r2 8010fea: 617b str r3, [r7, #20] /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; 8010fec: 68fb ldr r3, [r7, #12] 8010fee: 693a ldr r2, [r7, #16] 8010ff0: 61da str r2, [r3, #28] TIMx->CCER = tmpccer; 8010ff2: 68fb ldr r3, [r7, #12] 8010ff4: 697a ldr r2, [r7, #20] 8010ff6: 621a str r2, [r3, #32] } 8010ff8: bf00 nop 8010ffa: 371c adds r7, #28 8010ffc: 46bd mov sp, r7 8010ffe: f85d 7b04 ldr.w r7, [sp], #4 8011002: 4770 bx lr 08011004 : * protected against un-initialized filter and polarity values. * @retval None */ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 8011004: b480 push {r7} 8011006: b087 sub sp, #28 8011008: af00 add r7, sp, #0 801100a: 60f8 str r0, [r7, #12] 801100c: 60b9 str r1, [r7, #8] 801100e: 607a str r2, [r7, #4] 8011010: 603b str r3, [r7, #0] uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ tmpccer = TIMx->CCER; 8011012: 68fb ldr r3, [r7, #12] 8011014: 6a1b ldr r3, [r3, #32] 8011016: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC4E; 8011018: 68fb ldr r3, [r7, #12] 801101a: 6a1b ldr r3, [r3, #32] 801101c: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8011020: 68fb ldr r3, [r7, #12] 8011022: 621a str r2, [r3, #32] tmpccmr2 = TIMx->CCMR2; 8011024: 68fb ldr r3, [r7, #12] 8011026: 69db ldr r3, [r3, #28] 8011028: 613b str r3, [r7, #16] /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; 801102a: 693b ldr r3, [r7, #16] 801102c: f423 7340 bic.w r3, r3, #768 @ 0x300 8011030: 613b str r3, [r7, #16] tmpccmr2 |= (TIM_ICSelection << 8U); 8011032: 687b ldr r3, [r7, #4] 8011034: 021b lsls r3, r3, #8 8011036: 693a ldr r2, [r7, #16] 8011038: 4313 orrs r3, r2 801103a: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; 801103c: 693b ldr r3, [r7, #16] 801103e: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8011042: 613b str r3, [r7, #16] tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); 8011044: 683b ldr r3, [r7, #0] 8011046: 031b lsls r3, r3, #12 8011048: b29b uxth r3, r3 801104a: 693a ldr r2, [r7, #16] 801104c: 4313 orrs r3, r2 801104e: 613b str r3, [r7, #16] /* Select the Polarity and set the CC4E Bit */ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); 8011050: 697b ldr r3, [r7, #20] 8011052: f423 4320 bic.w r3, r3, #40960 @ 0xa000 8011056: 617b str r3, [r7, #20] tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); 8011058: 68bb ldr r3, [r7, #8] 801105a: 031b lsls r3, r3, #12 801105c: f403 4320 and.w r3, r3, #40960 @ 0xa000 8011060: 697a ldr r2, [r7, #20] 8011062: 4313 orrs r3, r2 8011064: 617b str r3, [r7, #20] /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; 8011066: 68fb ldr r3, [r7, #12] 8011068: 693a ldr r2, [r7, #16] 801106a: 61da str r2, [r3, #28] TIMx->CCER = tmpccer ; 801106c: 68fb ldr r3, [r7, #12] 801106e: 697a ldr r2, [r7, #20] 8011070: 621a str r2, [r3, #32] } 8011072: bf00 nop 8011074: 371c adds r7, #28 8011076: 46bd mov sp, r7 8011078: f85d 7b04 ldr.w r7, [sp], #4 801107c: 4770 bx lr ... 08011080 : * (*) Value not defined in all devices. * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8011080: b480 push {r7} 8011082: b085 sub sp, #20 8011084: af00 add r7, sp, #0 8011086: 6078 str r0, [r7, #4] 8011088: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 801108a: 687b ldr r3, [r7, #4] 801108c: 689b ldr r3, [r3, #8] 801108e: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8011090: 68fa ldr r2, [r7, #12] 8011092: 4b09 ldr r3, [pc, #36] @ (80110b8 ) 8011094: 4013 ands r3, r2 8011096: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8011098: 683a ldr r2, [r7, #0] 801109a: 68fb ldr r3, [r7, #12] 801109c: 4313 orrs r3, r2 801109e: f043 0307 orr.w r3, r3, #7 80110a2: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 80110a4: 687b ldr r3, [r7, #4] 80110a6: 68fa ldr r2, [r7, #12] 80110a8: 609a str r2, [r3, #8] } 80110aa: bf00 nop 80110ac: 3714 adds r7, #20 80110ae: 46bd mov sp, r7 80110b0: f85d 7b04 ldr.w r7, [sp], #4 80110b4: 4770 bx lr 80110b6: bf00 nop 80110b8: ffcfff8f .word 0xffcfff8f 080110bc : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 80110bc: b480 push {r7} 80110be: b087 sub sp, #28 80110c0: af00 add r7, sp, #0 80110c2: 60f8 str r0, [r7, #12] 80110c4: 60b9 str r1, [r7, #8] 80110c6: 607a str r2, [r7, #4] 80110c8: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 80110ca: 68fb ldr r3, [r7, #12] 80110cc: 689b ldr r3, [r3, #8] 80110ce: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80110d0: 697b ldr r3, [r7, #20] 80110d2: f423 437f bic.w r3, r3, #65280 @ 0xff00 80110d6: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 80110d8: 683b ldr r3, [r7, #0] 80110da: 021a lsls r2, r3, #8 80110dc: 687b ldr r3, [r7, #4] 80110de: 431a orrs r2, r3 80110e0: 68bb ldr r3, [r7, #8] 80110e2: 4313 orrs r3, r2 80110e4: 697a ldr r2, [r7, #20] 80110e6: 4313 orrs r3, r2 80110e8: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 80110ea: 68fb ldr r3, [r7, #12] 80110ec: 697a ldr r2, [r7, #20] 80110ee: 609a str r2, [r3, #8] } 80110f0: bf00 nop 80110f2: 371c adds r7, #28 80110f4: 46bd mov sp, r7 80110f6: f85d 7b04 ldr.w r7, [sp], #4 80110fa: 4770 bx lr 080110fc : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 80110fc: b480 push {r7} 80110fe: b087 sub sp, #28 8011100: af00 add r7, sp, #0 8011102: 60f8 str r0, [r7, #12] 8011104: 60b9 str r1, [r7, #8] 8011106: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8011108: 68bb ldr r3, [r7, #8] 801110a: f003 031f and.w r3, r3, #31 801110e: 2201 movs r2, #1 8011110: fa02 f303 lsl.w r3, r2, r3 8011114: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 8011116: 68fb ldr r3, [r7, #12] 8011118: 6a1a ldr r2, [r3, #32] 801111a: 697b ldr r3, [r7, #20] 801111c: 43db mvns r3, r3 801111e: 401a ands r2, r3 8011120: 68fb ldr r3, [r7, #12] 8011122: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8011124: 68fb ldr r3, [r7, #12] 8011126: 6a1a ldr r2, [r3, #32] 8011128: 68bb ldr r3, [r7, #8] 801112a: f003 031f and.w r3, r3, #31 801112e: 6879 ldr r1, [r7, #4] 8011130: fa01 f303 lsl.w r3, r1, r3 8011134: 431a orrs r2, r3 8011136: 68fb ldr r3, [r7, #12] 8011138: 621a str r2, [r3, #32] } 801113a: bf00 nop 801113c: 371c adds r7, #28 801113e: 46bd mov sp, r7 8011140: f85d 7b04 ldr.w r7, [sp], #4 8011144: 4770 bx lr ... 08011148 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8011148: b480 push {r7} 801114a: b085 sub sp, #20 801114c: af00 add r7, sp, #0 801114e: 6078 str r0, [r7, #4] 8011150: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8011152: 687b ldr r3, [r7, #4] 8011154: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8011158: 2b01 cmp r3, #1 801115a: d101 bne.n 8011160 801115c: 2302 movs r3, #2 801115e: e06d b.n 801123c 8011160: 687b ldr r3, [r7, #4] 8011162: 2201 movs r2, #1 8011164: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8011168: 687b ldr r3, [r7, #4] 801116a: 2202 movs r2, #2 801116c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8011170: 687b ldr r3, [r7, #4] 8011172: 681b ldr r3, [r3, #0] 8011174: 685b ldr r3, [r3, #4] 8011176: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8011178: 687b ldr r3, [r7, #4] 801117a: 681b ldr r3, [r3, #0] 801117c: 689b ldr r3, [r3, #8] 801117e: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 8011180: 687b ldr r3, [r7, #4] 8011182: 681b ldr r3, [r3, #0] 8011184: 4a30 ldr r2, [pc, #192] @ (8011248 ) 8011186: 4293 cmp r3, r2 8011188: d004 beq.n 8011194 801118a: 687b ldr r3, [r7, #4] 801118c: 681b ldr r3, [r3, #0] 801118e: 4a2f ldr r2, [pc, #188] @ (801124c ) 8011190: 4293 cmp r3, r2 8011192: d108 bne.n 80111a6 { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 8011194: 68fb ldr r3, [r7, #12] 8011196: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 801119a: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 801119c: 683b ldr r3, [r7, #0] 801119e: 685b ldr r3, [r3, #4] 80111a0: 68fa ldr r2, [r7, #12] 80111a2: 4313 orrs r3, r2 80111a4: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 80111a6: 68fb ldr r3, [r7, #12] 80111a8: f023 0370 bic.w r3, r3, #112 @ 0x70 80111ac: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 80111ae: 683b ldr r3, [r7, #0] 80111b0: 681b ldr r3, [r3, #0] 80111b2: 68fa ldr r2, [r7, #12] 80111b4: 4313 orrs r3, r2 80111b6: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 80111b8: 687b ldr r3, [r7, #4] 80111ba: 681b ldr r3, [r3, #0] 80111bc: 68fa ldr r2, [r7, #12] 80111be: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80111c0: 687b ldr r3, [r7, #4] 80111c2: 681b ldr r3, [r3, #0] 80111c4: 4a20 ldr r2, [pc, #128] @ (8011248 ) 80111c6: 4293 cmp r3, r2 80111c8: d022 beq.n 8011210 80111ca: 687b ldr r3, [r7, #4] 80111cc: 681b ldr r3, [r3, #0] 80111ce: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80111d2: d01d beq.n 8011210 80111d4: 687b ldr r3, [r7, #4] 80111d6: 681b ldr r3, [r3, #0] 80111d8: 4a1d ldr r2, [pc, #116] @ (8011250 ) 80111da: 4293 cmp r3, r2 80111dc: d018 beq.n 8011210 80111de: 687b ldr r3, [r7, #4] 80111e0: 681b ldr r3, [r3, #0] 80111e2: 4a1c ldr r2, [pc, #112] @ (8011254 ) 80111e4: 4293 cmp r3, r2 80111e6: d013 beq.n 8011210 80111e8: 687b ldr r3, [r7, #4] 80111ea: 681b ldr r3, [r3, #0] 80111ec: 4a1a ldr r2, [pc, #104] @ (8011258 ) 80111ee: 4293 cmp r3, r2 80111f0: d00e beq.n 8011210 80111f2: 687b ldr r3, [r7, #4] 80111f4: 681b ldr r3, [r3, #0] 80111f6: 4a15 ldr r2, [pc, #84] @ (801124c ) 80111f8: 4293 cmp r3, r2 80111fa: d009 beq.n 8011210 80111fc: 687b ldr r3, [r7, #4] 80111fe: 681b ldr r3, [r3, #0] 8011200: 4a16 ldr r2, [pc, #88] @ (801125c ) 8011202: 4293 cmp r3, r2 8011204: d004 beq.n 8011210 8011206: 687b ldr r3, [r7, #4] 8011208: 681b ldr r3, [r3, #0] 801120a: 4a15 ldr r2, [pc, #84] @ (8011260 ) 801120c: 4293 cmp r3, r2 801120e: d10c bne.n 801122a { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8011210: 68bb ldr r3, [r7, #8] 8011212: f023 0380 bic.w r3, r3, #128 @ 0x80 8011216: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8011218: 683b ldr r3, [r7, #0] 801121a: 689b ldr r3, [r3, #8] 801121c: 68ba ldr r2, [r7, #8] 801121e: 4313 orrs r3, r2 8011220: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8011222: 687b ldr r3, [r7, #4] 8011224: 681b ldr r3, [r3, #0] 8011226: 68ba ldr r2, [r7, #8] 8011228: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 801122a: 687b ldr r3, [r7, #4] 801122c: 2201 movs r2, #1 801122e: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8011232: 687b ldr r3, [r7, #4] 8011234: 2200 movs r2, #0 8011236: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 801123a: 2300 movs r3, #0 } 801123c: 4618 mov r0, r3 801123e: 3714 adds r7, #20 8011240: 46bd mov sp, r7 8011242: f85d 7b04 ldr.w r7, [sp], #4 8011246: 4770 bx lr 8011248: 40010000 .word 0x40010000 801124c: 40010400 .word 0x40010400 8011250: 40000400 .word 0x40000400 8011254: 40000800 .word 0x40000800 8011258: 40000c00 .word 0x40000c00 801125c: 40001800 .word 0x40001800 8011260: 40014000 .word 0x40014000 08011264 : * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { 8011264: b480 push {r7} 8011266: b085 sub sp, #20 8011268: af00 add r7, sp, #0 801126a: 6078 str r0, [r7, #4] 801126c: 6039 str r1, [r7, #0] /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; 801126e: 2300 movs r3, #0 8011270: 60fb str r3, [r7, #12] #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); #endif /* TIM_BDTR_BKBID */ /* Check input state */ __HAL_LOCK(htim); 8011272: 687b ldr r3, [r7, #4] 8011274: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8011278: 2b01 cmp r3, #1 801127a: d101 bne.n 8011280 801127c: 2302 movs r3, #2 801127e: e065 b.n 801134c 8011280: 687b ldr r3, [r7, #4] 8011282: 2201 movs r2, #1 8011284: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); 8011288: 68fb ldr r3, [r7, #12] 801128a: f023 02ff bic.w r2, r3, #255 @ 0xff 801128e: 683b ldr r3, [r7, #0] 8011290: 68db ldr r3, [r3, #12] 8011292: 4313 orrs r3, r2 8011294: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); 8011296: 68fb ldr r3, [r7, #12] 8011298: f423 7240 bic.w r2, r3, #768 @ 0x300 801129c: 683b ldr r3, [r7, #0] 801129e: 689b ldr r3, [r3, #8] 80112a0: 4313 orrs r3, r2 80112a2: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 80112a4: 68fb ldr r3, [r7, #12] 80112a6: f423 6280 bic.w r2, r3, #1024 @ 0x400 80112aa: 683b ldr r3, [r7, #0] 80112ac: 685b ldr r3, [r3, #4] 80112ae: 4313 orrs r3, r2 80112b0: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 80112b2: 68fb ldr r3, [r7, #12] 80112b4: f423 6200 bic.w r2, r3, #2048 @ 0x800 80112b8: 683b ldr r3, [r7, #0] 80112ba: 681b ldr r3, [r3, #0] 80112bc: 4313 orrs r3, r2 80112be: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 80112c0: 68fb ldr r3, [r7, #12] 80112c2: f423 5280 bic.w r2, r3, #4096 @ 0x1000 80112c6: 683b ldr r3, [r7, #0] 80112c8: 691b ldr r3, [r3, #16] 80112ca: 4313 orrs r3, r2 80112cc: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 80112ce: 68fb ldr r3, [r7, #12] 80112d0: f423 5200 bic.w r2, r3, #8192 @ 0x2000 80112d4: 683b ldr r3, [r7, #0] 80112d6: 695b ldr r3, [r3, #20] 80112d8: 4313 orrs r3, r2 80112da: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 80112dc: 68fb ldr r3, [r7, #12] 80112de: f423 4280 bic.w r2, r3, #16384 @ 0x4000 80112e2: 683b ldr r3, [r7, #0] 80112e4: 6a9b ldr r3, [r3, #40] @ 0x28 80112e6: 4313 orrs r3, r2 80112e8: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 80112ea: 68fb ldr r3, [r7, #12] 80112ec: f423 2270 bic.w r2, r3, #983040 @ 0xf0000 80112f0: 683b ldr r3, [r7, #0] 80112f2: 699b ldr r3, [r3, #24] 80112f4: 041b lsls r3, r3, #16 80112f6: 4313 orrs r3, r2 80112f8: 60fb str r3, [r7, #12] #if defined(TIM_BDTR_BKBID) MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); #endif /* TIM_BDTR_BKBID */ if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) 80112fa: 687b ldr r3, [r7, #4] 80112fc: 681b ldr r3, [r3, #0] 80112fe: 4a16 ldr r2, [pc, #88] @ (8011358 ) 8011300: 4293 cmp r3, r2 8011302: d004 beq.n 801130e 8011304: 687b ldr r3, [r7, #4] 8011306: 681b ldr r3, [r3, #0] 8011308: 4a14 ldr r2, [pc, #80] @ (801135c ) 801130a: 4293 cmp r3, r2 801130c: d115 bne.n 801133a #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); #endif /* TIM_BDTR_BKBID */ /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); 801130e: 68fb ldr r3, [r7, #12] 8011310: f423 0270 bic.w r2, r3, #15728640 @ 0xf00000 8011314: 683b ldr r3, [r7, #0] 8011316: 6a5b ldr r3, [r3, #36] @ 0x24 8011318: 051b lsls r3, r3, #20 801131a: 4313 orrs r3, r2 801131c: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); 801131e: 68fb ldr r3, [r7, #12] 8011320: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000 8011324: 683b ldr r3, [r7, #0] 8011326: 69db ldr r3, [r3, #28] 8011328: 4313 orrs r3, r2 801132a: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); 801132c: 68fb ldr r3, [r7, #12] 801132e: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000 8011332: 683b ldr r3, [r7, #0] 8011334: 6a1b ldr r3, [r3, #32] 8011336: 4313 orrs r3, r2 8011338: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); #endif /* TIM_BDTR_BKBID */ } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; 801133a: 687b ldr r3, [r7, #4] 801133c: 681b ldr r3, [r3, #0] 801133e: 68fa ldr r2, [r7, #12] 8011340: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(htim); 8011342: 687b ldr r3, [r7, #4] 8011344: 2200 movs r2, #0 8011346: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 801134a: 2300 movs r3, #0 } 801134c: 4618 mov r0, r3 801134e: 3714 adds r7, #20 8011350: 46bd mov sp, r7 8011352: f85d 7b04 ldr.w r7, [sp], #4 8011356: 4770 bx lr 8011358: 40010000 .word 0x40010000 801135c: 40010400 .word 0x40010400 08011360 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8011360: b480 push {r7} 8011362: b083 sub sp, #12 8011364: af00 add r7, sp, #0 8011366: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8011368: bf00 nop 801136a: 370c adds r7, #12 801136c: 46bd mov sp, r7 801136e: f85d 7b04 ldr.w r7, [sp], #4 8011372: 4770 bx lr 08011374 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8011374: b480 push {r7} 8011376: b083 sub sp, #12 8011378: af00 add r7, sp, #0 801137a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 801137c: bf00 nop 801137e: 370c adds r7, #12 8011380: 46bd mov sp, r7 8011382: f85d 7b04 ldr.w r7, [sp], #4 8011386: 4770 bx lr 08011388 : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 8011388: b480 push {r7} 801138a: b083 sub sp, #12 801138c: af00 add r7, sp, #0 801138e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 8011390: bf00 nop 8011392: 370c adds r7, #12 8011394: 46bd mov sp, r7 8011396: f85d 7b04 ldr.w r7, [sp], #4 801139a: 4770 bx lr 0801139c : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 801139c: b580 push {r7, lr} 801139e: b082 sub sp, #8 80113a0: af00 add r7, sp, #0 80113a2: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 80113a4: 687b ldr r3, [r7, #4] 80113a6: 2b00 cmp r3, #0 80113a8: d101 bne.n 80113ae { return HAL_ERROR; 80113aa: 2301 movs r3, #1 80113ac: e042 b.n 8011434 { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 80113ae: 687b ldr r3, [r7, #4] 80113b0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80113b4: 2b00 cmp r3, #0 80113b6: d106 bne.n 80113c6 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 80113b8: 687b ldr r3, [r7, #4] 80113ba: 2200 movs r2, #0 80113bc: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 80113c0: 6878 ldr r0, [r7, #4] 80113c2: f7f3 f881 bl 80044c8 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 80113c6: 687b ldr r3, [r7, #4] 80113c8: 2224 movs r2, #36 @ 0x24 80113ca: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UART_DISABLE(huart); 80113ce: 687b ldr r3, [r7, #4] 80113d0: 681b ldr r3, [r3, #0] 80113d2: 681a ldr r2, [r3, #0] 80113d4: 687b ldr r3, [r7, #4] 80113d6: 681b ldr r3, [r3, #0] 80113d8: f022 0201 bic.w r2, r2, #1 80113dc: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 80113de: 687b ldr r3, [r7, #4] 80113e0: 6a9b ldr r3, [r3, #40] @ 0x28 80113e2: 2b00 cmp r3, #0 80113e4: d002 beq.n 80113ec { UART_AdvFeatureConfig(huart); 80113e6: 6878 ldr r0, [r7, #4] 80113e8: f001 f9e8 bl 80127bc } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 80113ec: 6878 ldr r0, [r7, #4] 80113ee: f000 fc7d bl 8011cec 80113f2: 4603 mov r3, r0 80113f4: 2b01 cmp r3, #1 80113f6: d101 bne.n 80113fc { return HAL_ERROR; 80113f8: 2301 movs r3, #1 80113fa: e01b b.n 8011434 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 80113fc: 687b ldr r3, [r7, #4] 80113fe: 681b ldr r3, [r3, #0] 8011400: 685a ldr r2, [r3, #4] 8011402: 687b ldr r3, [r7, #4] 8011404: 681b ldr r3, [r3, #0] 8011406: f422 4290 bic.w r2, r2, #18432 @ 0x4800 801140a: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 801140c: 687b ldr r3, [r7, #4] 801140e: 681b ldr r3, [r3, #0] 8011410: 689a ldr r2, [r3, #8] 8011412: 687b ldr r3, [r7, #4] 8011414: 681b ldr r3, [r3, #0] 8011416: f022 022a bic.w r2, r2, #42 @ 0x2a 801141a: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 801141c: 687b ldr r3, [r7, #4] 801141e: 681b ldr r3, [r3, #0] 8011420: 681a ldr r2, [r3, #0] 8011422: 687b ldr r3, [r7, #4] 8011424: 681b ldr r3, [r3, #0] 8011426: f042 0201 orr.w r2, r2, #1 801142a: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 801142c: 6878 ldr r0, [r7, #4] 801142e: f001 fa67 bl 8012900 8011432: 4603 mov r3, r0 } 8011434: 4618 mov r0, r3 8011436: 3708 adds r7, #8 8011438: 46bd mov sp, r7 801143a: bd80 pop {r7, pc} 0801143c : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 801143c: b480 push {r7} 801143e: b091 sub sp, #68 @ 0x44 8011440: af00 add r7, sp, #0 8011442: 60f8 str r0, [r7, #12] 8011444: 60b9 str r1, [r7, #8] 8011446: 4613 mov r3, r2 8011448: 80fb strh r3, [r7, #6] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 801144a: 68fb ldr r3, [r7, #12] 801144c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8011450: 2b20 cmp r3, #32 8011452: d178 bne.n 8011546 { if ((pData == NULL) || (Size == 0U)) 8011454: 68bb ldr r3, [r7, #8] 8011456: 2b00 cmp r3, #0 8011458: d002 beq.n 8011460 801145a: 88fb ldrh r3, [r7, #6] 801145c: 2b00 cmp r3, #0 801145e: d101 bne.n 8011464 { return HAL_ERROR; 8011460: 2301 movs r3, #1 8011462: e071 b.n 8011548 } huart->pTxBuffPtr = pData; 8011464: 68fb ldr r3, [r7, #12] 8011466: 68ba ldr r2, [r7, #8] 8011468: 651a str r2, [r3, #80] @ 0x50 huart->TxXferSize = Size; 801146a: 68fb ldr r3, [r7, #12] 801146c: 88fa ldrh r2, [r7, #6] 801146e: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 huart->TxXferCount = Size; 8011472: 68fb ldr r3, [r7, #12] 8011474: 88fa ldrh r2, [r7, #6] 8011476: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 huart->TxISR = NULL; 801147a: 68fb ldr r3, [r7, #12] 801147c: 2200 movs r2, #0 801147e: 679a str r2, [r3, #120] @ 0x78 huart->ErrorCode = HAL_UART_ERROR_NONE; 8011480: 68fb ldr r3, [r7, #12] 8011482: 2200 movs r2, #0 8011484: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->gState = HAL_UART_STATE_BUSY_TX; 8011488: 68fb ldr r3, [r7, #12] 801148a: 2221 movs r2, #33 @ 0x21 801148c: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Configure Tx interrupt processing */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) 8011490: 68fb ldr r3, [r7, #12] 8011492: 6e5b ldr r3, [r3, #100] @ 0x64 8011494: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8011498: d12a bne.n 80114f0 { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 801149a: 68fb ldr r3, [r7, #12] 801149c: 689b ldr r3, [r3, #8] 801149e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80114a2: d107 bne.n 80114b4 80114a4: 68fb ldr r3, [r7, #12] 80114a6: 691b ldr r3, [r3, #16] 80114a8: 2b00 cmp r3, #0 80114aa: d103 bne.n 80114b4 { huart->TxISR = UART_TxISR_16BIT_FIFOEN; 80114ac: 68fb ldr r3, [r7, #12] 80114ae: 4a29 ldr r2, [pc, #164] @ (8011554 ) 80114b0: 679a str r2, [r3, #120] @ 0x78 80114b2: e002 b.n 80114ba } else { huart->TxISR = UART_TxISR_8BIT_FIFOEN; 80114b4: 68fb ldr r3, [r7, #12] 80114b6: 4a28 ldr r2, [pc, #160] @ (8011558 ) 80114b8: 679a str r2, [r3, #120] @ 0x78 } /* Enable the TX FIFO threshold interrupt */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 80114ba: 68fb ldr r3, [r7, #12] 80114bc: 681b ldr r3, [r3, #0] 80114be: 3308 adds r3, #8 80114c0: 62bb str r3, [r7, #40] @ 0x28 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80114c2: 6abb ldr r3, [r7, #40] @ 0x28 80114c4: e853 3f00 ldrex r3, [r3] 80114c8: 627b str r3, [r7, #36] @ 0x24 return(result); 80114ca: 6a7b ldr r3, [r7, #36] @ 0x24 80114cc: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 80114d0: 63bb str r3, [r7, #56] @ 0x38 80114d2: 68fb ldr r3, [r7, #12] 80114d4: 681b ldr r3, [r3, #0] 80114d6: 3308 adds r3, #8 80114d8: 6bba ldr r2, [r7, #56] @ 0x38 80114da: 637a str r2, [r7, #52] @ 0x34 80114dc: 633b str r3, [r7, #48] @ 0x30 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80114de: 6b39 ldr r1, [r7, #48] @ 0x30 80114e0: 6b7a ldr r2, [r7, #52] @ 0x34 80114e2: e841 2300 strex r3, r2, [r1] 80114e6: 62fb str r3, [r7, #44] @ 0x2c return(result); 80114e8: 6afb ldr r3, [r7, #44] @ 0x2c 80114ea: 2b00 cmp r3, #0 80114ec: d1e5 bne.n 80114ba 80114ee: e028 b.n 8011542 } else { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80114f0: 68fb ldr r3, [r7, #12] 80114f2: 689b ldr r3, [r3, #8] 80114f4: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80114f8: d107 bne.n 801150a 80114fa: 68fb ldr r3, [r7, #12] 80114fc: 691b ldr r3, [r3, #16] 80114fe: 2b00 cmp r3, #0 8011500: d103 bne.n 801150a { huart->TxISR = UART_TxISR_16BIT; 8011502: 68fb ldr r3, [r7, #12] 8011504: 4a15 ldr r2, [pc, #84] @ (801155c ) 8011506: 679a str r2, [r3, #120] @ 0x78 8011508: e002 b.n 8011510 } else { huart->TxISR = UART_TxISR_8BIT; 801150a: 68fb ldr r3, [r7, #12] 801150c: 4a14 ldr r2, [pc, #80] @ (8011560 ) 801150e: 679a str r2, [r3, #120] @ 0x78 } /* Enable the Transmit Data Register Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8011510: 68fb ldr r3, [r7, #12] 8011512: 681b ldr r3, [r3, #0] 8011514: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011516: 697b ldr r3, [r7, #20] 8011518: e853 3f00 ldrex r3, [r3] 801151c: 613b str r3, [r7, #16] return(result); 801151e: 693b ldr r3, [r7, #16] 8011520: f043 0380 orr.w r3, r3, #128 @ 0x80 8011524: 63fb str r3, [r7, #60] @ 0x3c 8011526: 68fb ldr r3, [r7, #12] 8011528: 681b ldr r3, [r3, #0] 801152a: 461a mov r2, r3 801152c: 6bfb ldr r3, [r7, #60] @ 0x3c 801152e: 623b str r3, [r7, #32] 8011530: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011532: 69f9 ldr r1, [r7, #28] 8011534: 6a3a ldr r2, [r7, #32] 8011536: e841 2300 strex r3, r2, [r1] 801153a: 61bb str r3, [r7, #24] return(result); 801153c: 69bb ldr r3, [r7, #24] 801153e: 2b00 cmp r3, #0 8011540: d1e6 bne.n 8011510 } return HAL_OK; 8011542: 2300 movs r3, #0 8011544: e000 b.n 8011548 } else { return HAL_BUSY; 8011546: 2302 movs r3, #2 } } 8011548: 4618 mov r0, r3 801154a: 3744 adds r7, #68 @ 0x44 801154c: 46bd mov sp, r7 801154e: f85d 7b04 ldr.w r7, [sp], #4 8011552: 4770 bx lr 8011554: 080130c7 .word 0x080130c7 8011558: 08012fe7 .word 0x08012fe7 801155c: 08012f25 .word 0x08012f25 8011560: 08012e6d .word 0x08012e6d 08011564 : * @brief Handle UART interrupt request. * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8011564: b580 push {r7, lr} 8011566: b0ba sub sp, #232 @ 0xe8 8011568: af00 add r7, sp, #0 801156a: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->ISR); 801156c: 687b ldr r3, [r7, #4] 801156e: 681b ldr r3, [r3, #0] 8011570: 69db ldr r3, [r3, #28] 8011572: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8011576: 687b ldr r3, [r7, #4] 8011578: 681b ldr r3, [r3, #0] 801157a: 681b ldr r3, [r3, #0] 801157c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8011580: 687b ldr r3, [r7, #4] 8011582: 681b ldr r3, [r3, #0] 8011584: 689b ldr r3, [r3, #8] 8011586: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags; uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); 801158a: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4 801158e: f640 030f movw r3, #2063 @ 0x80f 8011592: 4013 ands r3, r2 8011594: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == 0U) 8011598: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 801159c: 2b00 cmp r3, #0 801159e: d11b bne.n 80115d8 { /* UART in mode Receiver ---------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 80115a0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80115a4: f003 0320 and.w r3, r3, #32 80115a8: 2b00 cmp r3, #0 80115aa: d015 beq.n 80115d8 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 80115ac: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80115b0: f003 0320 and.w r3, r3, #32 80115b4: 2b00 cmp r3, #0 80115b6: d105 bne.n 80115c4 || ((cr3its & USART_CR3_RXFTIE) != 0U))) 80115b8: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80115bc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80115c0: 2b00 cmp r3, #0 80115c2: d009 beq.n 80115d8 { if (huart->RxISR != NULL) 80115c4: 687b ldr r3, [r7, #4] 80115c6: 6f5b ldr r3, [r3, #116] @ 0x74 80115c8: 2b00 cmp r3, #0 80115ca: f000 8377 beq.w 8011cbc { huart->RxISR(huart); 80115ce: 687b ldr r3, [r7, #4] 80115d0: 6f5b ldr r3, [r3, #116] @ 0x74 80115d2: 6878 ldr r0, [r7, #4] 80115d4: 4798 blx r3 } return; 80115d6: e371 b.n 8011cbc } } /* If some errors occur */ if ((errorflags != 0U) 80115d8: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80115dc: 2b00 cmp r3, #0 80115de: f000 8123 beq.w 8011828 && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) 80115e2: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 80115e6: 4b8d ldr r3, [pc, #564] @ (801181c ) 80115e8: 4013 ands r3, r2 80115ea: 2b00 cmp r3, #0 80115ec: d106 bne.n 80115fc || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) 80115ee: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0 80115f2: 4b8b ldr r3, [pc, #556] @ (8011820 ) 80115f4: 4013 ands r3, r2 80115f6: 2b00 cmp r3, #0 80115f8: f000 8116 beq.w 8011828 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 80115fc: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011600: f003 0301 and.w r3, r3, #1 8011604: 2b00 cmp r3, #0 8011606: d011 beq.n 801162c 8011608: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801160c: f403 7380 and.w r3, r3, #256 @ 0x100 8011610: 2b00 cmp r3, #0 8011612: d00b beq.n 801162c { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8011614: 687b ldr r3, [r7, #4] 8011616: 681b ldr r3, [r3, #0] 8011618: 2201 movs r2, #1 801161a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 801161c: 687b ldr r3, [r7, #4] 801161e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011622: f043 0201 orr.w r2, r3, #1 8011626: 687b ldr r3, [r7, #4] 8011628: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 801162c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011630: f003 0302 and.w r3, r3, #2 8011634: 2b00 cmp r3, #0 8011636: d011 beq.n 801165c 8011638: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 801163c: f003 0301 and.w r3, r3, #1 8011640: 2b00 cmp r3, #0 8011642: d00b beq.n 801165c { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8011644: 687b ldr r3, [r7, #4] 8011646: 681b ldr r3, [r3, #0] 8011648: 2202 movs r2, #2 801164a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 801164c: 687b ldr r3, [r7, #4] 801164e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011652: f043 0204 orr.w r2, r3, #4 8011656: 687b ldr r3, [r7, #4] 8011658: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 801165c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011660: f003 0304 and.w r3, r3, #4 8011664: 2b00 cmp r3, #0 8011666: d011 beq.n 801168c 8011668: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 801166c: f003 0301 and.w r3, r3, #1 8011670: 2b00 cmp r3, #0 8011672: d00b beq.n 801168c { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8011674: 687b ldr r3, [r7, #4] 8011676: 681b ldr r3, [r3, #0] 8011678: 2204 movs r2, #4 801167a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 801167c: 687b ldr r3, [r7, #4] 801167e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011682: f043 0202 orr.w r2, r3, #2 8011686: 687b ldr r3, [r7, #4] 8011688: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Over-Run interrupt occurred -----------------------------------------*/ if (((isrflags & USART_ISR_ORE) != 0U) 801168c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011690: f003 0308 and.w r3, r3, #8 8011694: 2b00 cmp r3, #0 8011696: d017 beq.n 80116c8 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 8011698: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801169c: f003 0320 and.w r3, r3, #32 80116a0: 2b00 cmp r3, #0 80116a2: d105 bne.n 80116b0 ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) 80116a4: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 80116a8: 4b5c ldr r3, [pc, #368] @ (801181c ) 80116aa: 4013 ands r3, r2 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 80116ac: 2b00 cmp r3, #0 80116ae: d00b beq.n 80116c8 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 80116b0: 687b ldr r3, [r7, #4] 80116b2: 681b ldr r3, [r3, #0] 80116b4: 2208 movs r2, #8 80116b6: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_ORE; 80116b8: 687b ldr r3, [r7, #4] 80116ba: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80116be: f043 0208 orr.w r2, r3, #8 80116c2: 687b ldr r3, [r7, #4] 80116c4: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Receiver Timeout interrupt occurred ---------------------------------*/ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) 80116c8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80116cc: f403 6300 and.w r3, r3, #2048 @ 0x800 80116d0: 2b00 cmp r3, #0 80116d2: d012 beq.n 80116fa 80116d4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80116d8: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 80116dc: 2b00 cmp r3, #0 80116de: d00c beq.n 80116fa { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 80116e0: 687b ldr r3, [r7, #4] 80116e2: 681b ldr r3, [r3, #0] 80116e4: f44f 6200 mov.w r2, #2048 @ 0x800 80116e8: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_RTO; 80116ea: 687b ldr r3, [r7, #4] 80116ec: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80116f0: f043 0220 orr.w r2, r3, #32 80116f4: 687b ldr r3, [r7, #4] 80116f6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 80116fa: 687b ldr r3, [r7, #4] 80116fc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011700: 2b00 cmp r3, #0 8011702: f000 82dd beq.w 8011cc0 { /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 8011706: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801170a: f003 0320 and.w r3, r3, #32 801170e: 2b00 cmp r3, #0 8011710: d013 beq.n 801173a && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 8011712: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011716: f003 0320 and.w r3, r3, #32 801171a: 2b00 cmp r3, #0 801171c: d105 bne.n 801172a || ((cr3its & USART_CR3_RXFTIE) != 0U))) 801171e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011722: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011726: 2b00 cmp r3, #0 8011728: d007 beq.n 801173a { if (huart->RxISR != NULL) 801172a: 687b ldr r3, [r7, #4] 801172c: 6f5b ldr r3, [r3, #116] @ 0x74 801172e: 2b00 cmp r3, #0 8011730: d003 beq.n 801173a { huart->RxISR(huart); 8011732: 687b ldr r3, [r7, #4] 8011734: 6f5b ldr r3, [r3, #116] @ 0x74 8011736: 6878 ldr r0, [r7, #4] 8011738: 4798 blx r3 /* If Error is to be considered as blocking : - Receiver Timeout error in Reception - Overrun error in Reception - any error occurs in DMA mode reception */ errorcode = huart->ErrorCode; 801173a: 687b ldr r3, [r7, #4] 801173c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011740: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8011744: 687b ldr r3, [r7, #4] 8011746: 681b ldr r3, [r3, #0] 8011748: 689b ldr r3, [r3, #8] 801174a: f003 0340 and.w r3, r3, #64 @ 0x40 801174e: 2b40 cmp r3, #64 @ 0x40 8011750: d005 beq.n 801175e ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) 8011752: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8011756: f003 0328 and.w r3, r3, #40 @ 0x28 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 801175a: 2b00 cmp r3, #0 801175c: d054 beq.n 8011808 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 801175e: 6878 ldr r0, [r7, #4] 8011760: f001 fb08 bl 8012d74 /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8011764: 687b ldr r3, [r7, #4] 8011766: 681b ldr r3, [r3, #0] 8011768: 689b ldr r3, [r3, #8] 801176a: f003 0340 and.w r3, r3, #64 @ 0x40 801176e: 2b40 cmp r3, #64 @ 0x40 8011770: d146 bne.n 8011800 { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8011772: 687b ldr r3, [r7, #4] 8011774: 681b ldr r3, [r3, #0] 8011776: 3308 adds r3, #8 8011778: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801177c: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8011780: e853 3f00 ldrex r3, [r3] 8011784: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8011788: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 801178c: f023 0340 bic.w r3, r3, #64 @ 0x40 8011790: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8011794: 687b ldr r3, [r7, #4] 8011796: 681b ldr r3, [r3, #0] 8011798: 3308 adds r3, #8 801179a: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 801179e: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 80117a2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80117a6: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 80117aa: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 80117ae: e841 2300 strex r3, r2, [r1] 80117b2: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 80117b6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80117ba: 2b00 cmp r3, #0 80117bc: d1d9 bne.n 8011772 /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 80117be: 687b ldr r3, [r7, #4] 80117c0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80117c4: 2b00 cmp r3, #0 80117c6: d017 beq.n 80117f8 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 80117c8: 687b ldr r3, [r7, #4] 80117ca: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80117ce: 4a15 ldr r2, [pc, #84] @ (8011824 ) 80117d0: 651a str r2, [r3, #80] @ 0x50 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 80117d2: 687b ldr r3, [r7, #4] 80117d4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80117d8: 4618 mov r0, r3 80117da: f7f7 ff8f bl 80096fc 80117de: 4603 mov r3, r0 80117e0: 2b00 cmp r3, #0 80117e2: d019 beq.n 8011818 { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 80117e4: 687b ldr r3, [r7, #4] 80117e6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80117ea: 6d1b ldr r3, [r3, #80] @ 0x50 80117ec: 687a ldr r2, [r7, #4] 80117ee: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80 80117f2: 4610 mov r0, r2 80117f4: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80117f6: e00f b.n 8011818 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80117f8: 6878 ldr r0, [r7, #4] 80117fa: f000 fa6d bl 8011cd8 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80117fe: e00b b.n 8011818 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8011800: 6878 ldr r0, [r7, #4] 8011802: f000 fa69 bl 8011cd8 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8011806: e007 b.n 8011818 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8011808: 6878 ldr r0, [r7, #4] 801180a: f000 fa65 bl 8011cd8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 801180e: 687b ldr r3, [r7, #4] 8011810: 2200 movs r2, #0 8011812: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } return; 8011816: e253 b.n 8011cc0 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8011818: bf00 nop return; 801181a: e251 b.n 8011cc0 801181c: 10000001 .word 0x10000001 8011820: 04000120 .word 0x04000120 8011824: 08012e41 .word 0x08012e41 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8011828: 687b ldr r3, [r7, #4] 801182a: 6edb ldr r3, [r3, #108] @ 0x6c 801182c: 2b01 cmp r3, #1 801182e: f040 81e7 bne.w 8011c00 && ((isrflags & USART_ISR_IDLE) != 0U) 8011832: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011836: f003 0310 and.w r3, r3, #16 801183a: 2b00 cmp r3, #0 801183c: f000 81e0 beq.w 8011c00 && ((cr1its & USART_ISR_IDLE) != 0U)) 8011840: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011844: f003 0310 and.w r3, r3, #16 8011848: 2b00 cmp r3, #0 801184a: f000 81d9 beq.w 8011c00 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 801184e: 687b ldr r3, [r7, #4] 8011850: 681b ldr r3, [r3, #0] 8011852: 2210 movs r2, #16 8011854: 621a str r2, [r3, #32] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8011856: 687b ldr r3, [r7, #4] 8011858: 681b ldr r3, [r3, #0] 801185a: 689b ldr r3, [r3, #8] 801185c: f003 0340 and.w r3, r3, #64 @ 0x40 8011860: 2b40 cmp r3, #64 @ 0x40 8011862: f040 8151 bne.w 8011b08 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8011866: 687b ldr r3, [r7, #4] 8011868: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801186c: 681b ldr r3, [r3, #0] 801186e: 4a96 ldr r2, [pc, #600] @ (8011ac8 ) 8011870: 4293 cmp r3, r2 8011872: d068 beq.n 8011946 8011874: 687b ldr r3, [r7, #4] 8011876: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801187a: 681b ldr r3, [r3, #0] 801187c: 4a93 ldr r2, [pc, #588] @ (8011acc ) 801187e: 4293 cmp r3, r2 8011880: d061 beq.n 8011946 8011882: 687b ldr r3, [r7, #4] 8011884: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011888: 681b ldr r3, [r3, #0] 801188a: 4a91 ldr r2, [pc, #580] @ (8011ad0 ) 801188c: 4293 cmp r3, r2 801188e: d05a beq.n 8011946 8011890: 687b ldr r3, [r7, #4] 8011892: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011896: 681b ldr r3, [r3, #0] 8011898: 4a8e ldr r2, [pc, #568] @ (8011ad4 ) 801189a: 4293 cmp r3, r2 801189c: d053 beq.n 8011946 801189e: 687b ldr r3, [r7, #4] 80118a0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118a4: 681b ldr r3, [r3, #0] 80118a6: 4a8c ldr r2, [pc, #560] @ (8011ad8 ) 80118a8: 4293 cmp r3, r2 80118aa: d04c beq.n 8011946 80118ac: 687b ldr r3, [r7, #4] 80118ae: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118b2: 681b ldr r3, [r3, #0] 80118b4: 4a89 ldr r2, [pc, #548] @ (8011adc ) 80118b6: 4293 cmp r3, r2 80118b8: d045 beq.n 8011946 80118ba: 687b ldr r3, [r7, #4] 80118bc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118c0: 681b ldr r3, [r3, #0] 80118c2: 4a87 ldr r2, [pc, #540] @ (8011ae0 ) 80118c4: 4293 cmp r3, r2 80118c6: d03e beq.n 8011946 80118c8: 687b ldr r3, [r7, #4] 80118ca: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118ce: 681b ldr r3, [r3, #0] 80118d0: 4a84 ldr r2, [pc, #528] @ (8011ae4 ) 80118d2: 4293 cmp r3, r2 80118d4: d037 beq.n 8011946 80118d6: 687b ldr r3, [r7, #4] 80118d8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118dc: 681b ldr r3, [r3, #0] 80118de: 4a82 ldr r2, [pc, #520] @ (8011ae8 ) 80118e0: 4293 cmp r3, r2 80118e2: d030 beq.n 8011946 80118e4: 687b ldr r3, [r7, #4] 80118e6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118ea: 681b ldr r3, [r3, #0] 80118ec: 4a7f ldr r2, [pc, #508] @ (8011aec ) 80118ee: 4293 cmp r3, r2 80118f0: d029 beq.n 8011946 80118f2: 687b ldr r3, [r7, #4] 80118f4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118f8: 681b ldr r3, [r3, #0] 80118fa: 4a7d ldr r2, [pc, #500] @ (8011af0 ) 80118fc: 4293 cmp r3, r2 80118fe: d022 beq.n 8011946 8011900: 687b ldr r3, [r7, #4] 8011902: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011906: 681b ldr r3, [r3, #0] 8011908: 4a7a ldr r2, [pc, #488] @ (8011af4 ) 801190a: 4293 cmp r3, r2 801190c: d01b beq.n 8011946 801190e: 687b ldr r3, [r7, #4] 8011910: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011914: 681b ldr r3, [r3, #0] 8011916: 4a78 ldr r2, [pc, #480] @ (8011af8 ) 8011918: 4293 cmp r3, r2 801191a: d014 beq.n 8011946 801191c: 687b ldr r3, [r7, #4] 801191e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011922: 681b ldr r3, [r3, #0] 8011924: 4a75 ldr r2, [pc, #468] @ (8011afc ) 8011926: 4293 cmp r3, r2 8011928: d00d beq.n 8011946 801192a: 687b ldr r3, [r7, #4] 801192c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011930: 681b ldr r3, [r3, #0] 8011932: 4a73 ldr r2, [pc, #460] @ (8011b00 ) 8011934: 4293 cmp r3, r2 8011936: d006 beq.n 8011946 8011938: 687b ldr r3, [r7, #4] 801193a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801193e: 681b ldr r3, [r3, #0] 8011940: 4a70 ldr r2, [pc, #448] @ (8011b04 ) 8011942: 4293 cmp r3, r2 8011944: d106 bne.n 8011954 8011946: 687b ldr r3, [r7, #4] 8011948: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801194c: 681b ldr r3, [r3, #0] 801194e: 685b ldr r3, [r3, #4] 8011950: b29b uxth r3, r3 8011952: e005 b.n 8011960 8011954: 687b ldr r3, [r7, #4] 8011956: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801195a: 681b ldr r3, [r3, #0] 801195c: 685b ldr r3, [r3, #4] 801195e: b29b uxth r3, r3 8011960: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8011964: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8011968: 2b00 cmp r3, #0 801196a: f000 81ab beq.w 8011cc4 && (nb_remaining_rx_data < huart->RxXferSize)) 801196e: 687b ldr r3, [r7, #4] 8011970: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8011974: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8011978: 429a cmp r2, r3 801197a: f080 81a3 bcs.w 8011cc4 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 801197e: 687b ldr r3, [r7, #4] 8011980: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8011984: f8a3 205e strh.w r2, [r3, #94] @ 0x5e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8011988: 687b ldr r3, [r7, #4] 801198a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801198e: 69db ldr r3, [r3, #28] 8011990: f5b3 7f80 cmp.w r3, #256 @ 0x100 8011994: f000 8087 beq.w 8011aa6 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8011998: 687b ldr r3, [r7, #4] 801199a: 681b ldr r3, [r3, #0] 801199c: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80119a0: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 80119a4: e853 3f00 ldrex r3, [r3] 80119a8: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 80119ac: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 80119b0: f423 7380 bic.w r3, r3, #256 @ 0x100 80119b4: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 80119b8: 687b ldr r3, [r7, #4] 80119ba: 681b ldr r3, [r3, #0] 80119bc: 461a mov r2, r3 80119be: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 80119c2: f8c7 3094 str.w r3, [r7, #148] @ 0x94 80119c6: f8c7 2090 str.w r2, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80119ca: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 80119ce: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 80119d2: e841 2300 strex r3, r2, [r1] 80119d6: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 80119da: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 80119de: 2b00 cmp r3, #0 80119e0: d1da bne.n 8011998 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80119e2: 687b ldr r3, [r7, #4] 80119e4: 681b ldr r3, [r3, #0] 80119e6: 3308 adds r3, #8 80119e8: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80119ea: 6f7b ldr r3, [r7, #116] @ 0x74 80119ec: e853 3f00 ldrex r3, [r3] 80119f0: 673b str r3, [r7, #112] @ 0x70 return(result); 80119f2: 6f3b ldr r3, [r7, #112] @ 0x70 80119f4: f023 0301 bic.w r3, r3, #1 80119f8: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 80119fc: 687b ldr r3, [r7, #4] 80119fe: 681b ldr r3, [r3, #0] 8011a00: 3308 adds r3, #8 8011a02: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8011a06: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8011a0a: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011a0c: 6ff9 ldr r1, [r7, #124] @ 0x7c 8011a0e: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8011a12: e841 2300 strex r3, r2, [r1] 8011a16: 67bb str r3, [r7, #120] @ 0x78 return(result); 8011a18: 6fbb ldr r3, [r7, #120] @ 0x78 8011a1a: 2b00 cmp r3, #0 8011a1c: d1e1 bne.n 80119e2 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8011a1e: 687b ldr r3, [r7, #4] 8011a20: 681b ldr r3, [r3, #0] 8011a22: 3308 adds r3, #8 8011a24: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011a26: 6e3b ldr r3, [r7, #96] @ 0x60 8011a28: e853 3f00 ldrex r3, [r3] 8011a2c: 65fb str r3, [r7, #92] @ 0x5c return(result); 8011a2e: 6dfb ldr r3, [r7, #92] @ 0x5c 8011a30: f023 0340 bic.w r3, r3, #64 @ 0x40 8011a34: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8011a38: 687b ldr r3, [r7, #4] 8011a3a: 681b ldr r3, [r3, #0] 8011a3c: 3308 adds r3, #8 8011a3e: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8011a42: 66fa str r2, [r7, #108] @ 0x6c 8011a44: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011a46: 6eb9 ldr r1, [r7, #104] @ 0x68 8011a48: 6efa ldr r2, [r7, #108] @ 0x6c 8011a4a: e841 2300 strex r3, r2, [r1] 8011a4e: 667b str r3, [r7, #100] @ 0x64 return(result); 8011a50: 6e7b ldr r3, [r7, #100] @ 0x64 8011a52: 2b00 cmp r3, #0 8011a54: d1e3 bne.n 8011a1e /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8011a56: 687b ldr r3, [r7, #4] 8011a58: 2220 movs r2, #32 8011a5a: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8011a5e: 687b ldr r3, [r7, #4] 8011a60: 2200 movs r2, #0 8011a62: 66da str r2, [r3, #108] @ 0x6c ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8011a64: 687b ldr r3, [r7, #4] 8011a66: 681b ldr r3, [r3, #0] 8011a68: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011a6a: 6cfb ldr r3, [r7, #76] @ 0x4c 8011a6c: e853 3f00 ldrex r3, [r3] 8011a70: 64bb str r3, [r7, #72] @ 0x48 return(result); 8011a72: 6cbb ldr r3, [r7, #72] @ 0x48 8011a74: f023 0310 bic.w r3, r3, #16 8011a78: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8011a7c: 687b ldr r3, [r7, #4] 8011a7e: 681b ldr r3, [r3, #0] 8011a80: 461a mov r2, r3 8011a82: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8011a86: 65bb str r3, [r7, #88] @ 0x58 8011a88: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011a8a: 6d79 ldr r1, [r7, #84] @ 0x54 8011a8c: 6dba ldr r2, [r7, #88] @ 0x58 8011a8e: e841 2300 strex r3, r2, [r1] 8011a92: 653b str r3, [r7, #80] @ 0x50 return(result); 8011a94: 6d3b ldr r3, [r7, #80] @ 0x50 8011a96: 2b00 cmp r3, #0 8011a98: d1e4 bne.n 8011a64 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8011a9a: 687b ldr r3, [r7, #4] 8011a9c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011aa0: 4618 mov r0, r3 8011aa2: f7f7 fb0d bl 80090c0 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8011aa6: 687b ldr r3, [r7, #4] 8011aa8: 2202 movs r2, #2 8011aaa: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8011aac: 687b ldr r3, [r7, #4] 8011aae: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 8011ab2: 687b ldr r3, [r7, #4] 8011ab4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011ab8: b29b uxth r3, r3 8011aba: 1ad3 subs r3, r2, r3 8011abc: b29b uxth r3, r3 8011abe: 4619 mov r1, r3 8011ac0: 6878 ldr r0, [r7, #4] 8011ac2: f7f2 ffff bl 8004ac4 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 8011ac6: e0fd b.n 8011cc4 8011ac8: 40020010 .word 0x40020010 8011acc: 40020028 .word 0x40020028 8011ad0: 40020040 .word 0x40020040 8011ad4: 40020058 .word 0x40020058 8011ad8: 40020070 .word 0x40020070 8011adc: 40020088 .word 0x40020088 8011ae0: 400200a0 .word 0x400200a0 8011ae4: 400200b8 .word 0x400200b8 8011ae8: 40020410 .word 0x40020410 8011aec: 40020428 .word 0x40020428 8011af0: 40020440 .word 0x40020440 8011af4: 40020458 .word 0x40020458 8011af8: 40020470 .word 0x40020470 8011afc: 40020488 .word 0x40020488 8011b00: 400204a0 .word 0x400204a0 8011b04: 400204b8 .word 0x400204b8 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8011b08: 687b ldr r3, [r7, #4] 8011b0a: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 8011b0e: 687b ldr r3, [r7, #4] 8011b10: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011b14: b29b uxth r3, r3 8011b16: 1ad3 subs r3, r2, r3 8011b18: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8011b1c: 687b ldr r3, [r7, #4] 8011b1e: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011b22: b29b uxth r3, r3 8011b24: 2b00 cmp r3, #0 8011b26: f000 80cf beq.w 8011cc8 && (nb_rx_data > 0U)) 8011b2a: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8011b2e: 2b00 cmp r3, #0 8011b30: f000 80ca beq.w 8011cc8 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8011b34: 687b ldr r3, [r7, #4] 8011b36: 681b ldr r3, [r3, #0] 8011b38: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011b3a: 6bbb ldr r3, [r7, #56] @ 0x38 8011b3c: e853 3f00 ldrex r3, [r3] 8011b40: 637b str r3, [r7, #52] @ 0x34 return(result); 8011b42: 6b7b ldr r3, [r7, #52] @ 0x34 8011b44: f423 7390 bic.w r3, r3, #288 @ 0x120 8011b48: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8011b4c: 687b ldr r3, [r7, #4] 8011b4e: 681b ldr r3, [r3, #0] 8011b50: 461a mov r2, r3 8011b52: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 8011b56: 647b str r3, [r7, #68] @ 0x44 8011b58: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011b5a: 6c39 ldr r1, [r7, #64] @ 0x40 8011b5c: 6c7a ldr r2, [r7, #68] @ 0x44 8011b5e: e841 2300 strex r3, r2, [r1] 8011b62: 63fb str r3, [r7, #60] @ 0x3c return(result); 8011b64: 6bfb ldr r3, [r7, #60] @ 0x3c 8011b66: 2b00 cmp r3, #0 8011b68: d1e4 bne.n 8011b34 /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8011b6a: 687b ldr r3, [r7, #4] 8011b6c: 681b ldr r3, [r3, #0] 8011b6e: 3308 adds r3, #8 8011b70: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011b72: 6a7b ldr r3, [r7, #36] @ 0x24 8011b74: e853 3f00 ldrex r3, [r3] 8011b78: 623b str r3, [r7, #32] return(result); 8011b7a: 6a3a ldr r2, [r7, #32] 8011b7c: 4b55 ldr r3, [pc, #340] @ (8011cd4 ) 8011b7e: 4013 ands r3, r2 8011b80: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8011b84: 687b ldr r3, [r7, #4] 8011b86: 681b ldr r3, [r3, #0] 8011b88: 3308 adds r3, #8 8011b8a: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8011b8e: 633a str r2, [r7, #48] @ 0x30 8011b90: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011b92: 6af9 ldr r1, [r7, #44] @ 0x2c 8011b94: 6b3a ldr r2, [r7, #48] @ 0x30 8011b96: e841 2300 strex r3, r2, [r1] 8011b9a: 62bb str r3, [r7, #40] @ 0x28 return(result); 8011b9c: 6abb ldr r3, [r7, #40] @ 0x28 8011b9e: 2b00 cmp r3, #0 8011ba0: d1e3 bne.n 8011b6a /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8011ba2: 687b ldr r3, [r7, #4] 8011ba4: 2220 movs r2, #32 8011ba6: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8011baa: 687b ldr r3, [r7, #4] 8011bac: 2200 movs r2, #0 8011bae: 66da str r2, [r3, #108] @ 0x6c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8011bb0: 687b ldr r3, [r7, #4] 8011bb2: 2200 movs r2, #0 8011bb4: 675a str r2, [r3, #116] @ 0x74 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8011bb6: 687b ldr r3, [r7, #4] 8011bb8: 681b ldr r3, [r3, #0] 8011bba: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011bbc: 693b ldr r3, [r7, #16] 8011bbe: e853 3f00 ldrex r3, [r3] 8011bc2: 60fb str r3, [r7, #12] return(result); 8011bc4: 68fb ldr r3, [r7, #12] 8011bc6: f023 0310 bic.w r3, r3, #16 8011bca: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8011bce: 687b ldr r3, [r7, #4] 8011bd0: 681b ldr r3, [r3, #0] 8011bd2: 461a mov r2, r3 8011bd4: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 8011bd8: 61fb str r3, [r7, #28] 8011bda: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011bdc: 69b9 ldr r1, [r7, #24] 8011bde: 69fa ldr r2, [r7, #28] 8011be0: e841 2300 strex r3, r2, [r1] 8011be4: 617b str r3, [r7, #20] return(result); 8011be6: 697b ldr r3, [r7, #20] 8011be8: 2b00 cmp r3, #0 8011bea: d1e4 bne.n 8011bb6 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8011bec: 687b ldr r3, [r7, #4] 8011bee: 2202 movs r2, #2 8011bf0: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8011bf2: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8011bf6: 4619 mov r1, r3 8011bf8: 6878 ldr r0, [r7, #4] 8011bfa: f7f2 ff63 bl 8004ac4 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 8011bfe: e063 b.n 8011cc8 } } /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) 8011c00: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011c04: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8011c08: 2b00 cmp r3, #0 8011c0a: d00e beq.n 8011c2a 8011c0c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011c10: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8011c14: 2b00 cmp r3, #0 8011c16: d008 beq.n 8011c2a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); 8011c18: 687b ldr r3, [r7, #4] 8011c1a: 681b ldr r3, [r3, #0] 8011c1c: f44f 1280 mov.w r2, #1048576 @ 0x100000 8011c20: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Wakeup Callback */ huart->WakeupCallback(huart); #else /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); 8011c22: 6878 ldr r0, [r7, #4] 8011c24: f002 f80c bl 8013c40 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8011c28: e051 b.n 8011cce } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) 8011c2a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011c2e: f003 0380 and.w r3, r3, #128 @ 0x80 8011c32: 2b00 cmp r3, #0 8011c34: d014 beq.n 8011c60 && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) 8011c36: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011c3a: f003 0380 and.w r3, r3, #128 @ 0x80 8011c3e: 2b00 cmp r3, #0 8011c40: d105 bne.n 8011c4e || ((cr3its & USART_CR3_TXFTIE) != 0U))) 8011c42: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011c46: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8011c4a: 2b00 cmp r3, #0 8011c4c: d008 beq.n 8011c60 { if (huart->TxISR != NULL) 8011c4e: 687b ldr r3, [r7, #4] 8011c50: 6f9b ldr r3, [r3, #120] @ 0x78 8011c52: 2b00 cmp r3, #0 8011c54: d03a beq.n 8011ccc { huart->TxISR(huart); 8011c56: 687b ldr r3, [r7, #4] 8011c58: 6f9b ldr r3, [r3, #120] @ 0x78 8011c5a: 6878 ldr r0, [r7, #4] 8011c5c: 4798 blx r3 } return; 8011c5e: e035 b.n 8011ccc } /* UART in mode Transmitter (transmission end) -----------------------------*/ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) 8011c60: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011c64: f003 0340 and.w r3, r3, #64 @ 0x40 8011c68: 2b00 cmp r3, #0 8011c6a: d009 beq.n 8011c80 8011c6c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011c70: f003 0340 and.w r3, r3, #64 @ 0x40 8011c74: 2b00 cmp r3, #0 8011c76: d003 beq.n 8011c80 { UART_EndTransmit_IT(huart); 8011c78: 6878 ldr r0, [r7, #4] 8011c7a: f001 fa99 bl 80131b0 return; 8011c7e: e026 b.n 8011cce } /* UART TX Fifo Empty occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) 8011c80: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011c84: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8011c88: 2b00 cmp r3, #0 8011c8a: d009 beq.n 8011ca0 8011c8c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011c90: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 8011c94: 2b00 cmp r3, #0 8011c96: d003 beq.n 8011ca0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ huart->TxFifoEmptyCallback(huart); #else /* Call legacy weak Tx Fifo Empty Callback */ HAL_UARTEx_TxFifoEmptyCallback(huart); 8011c98: 6878 ldr r0, [r7, #4] 8011c9a: f001 ffe5 bl 8013c68 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8011c9e: e016 b.n 8011cce } /* UART RX Fifo Full occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) 8011ca0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011ca4: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8011ca8: 2b00 cmp r3, #0 8011caa: d010 beq.n 8011cce 8011cac: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011cb0: 2b00 cmp r3, #0 8011cb2: da0c bge.n 8011cce #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ huart->RxFifoFullCallback(huart); #else /* Call legacy weak Rx Fifo Full Callback */ HAL_UARTEx_RxFifoFullCallback(huart); 8011cb4: 6878 ldr r0, [r7, #4] 8011cb6: f001 ffcd bl 8013c54 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8011cba: e008 b.n 8011cce return; 8011cbc: bf00 nop 8011cbe: e006 b.n 8011cce return; 8011cc0: bf00 nop 8011cc2: e004 b.n 8011cce return; 8011cc4: bf00 nop 8011cc6: e002 b.n 8011cce return; 8011cc8: bf00 nop 8011cca: e000 b.n 8011cce return; 8011ccc: bf00 nop } } 8011cce: 37e8 adds r7, #232 @ 0xe8 8011cd0: 46bd mov sp, r7 8011cd2: bd80 pop {r7, pc} 8011cd4: effffffe .word 0xeffffffe 08011cd8 : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8011cd8: b480 push {r7} 8011cda: b083 sub sp, #12 8011cdc: af00 add r7, sp, #0 8011cde: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } 8011ce0: bf00 nop 8011ce2: 370c adds r7, #12 8011ce4: 46bd mov sp, r7 8011ce6: f85d 7b04 ldr.w r7, [sp], #4 8011cea: 4770 bx lr 08011cec : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 8011cec: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8011cf0: b092 sub sp, #72 @ 0x48 8011cf2: af00 add r7, sp, #0 8011cf4: 6178 str r0, [r7, #20] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 8011cf6: 2300 movs r3, #0 8011cf8: f887 3042 strb.w r3, [r7, #66] @ 0x42 * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 8011cfc: 697b ldr r3, [r7, #20] 8011cfe: 689a ldr r2, [r3, #8] 8011d00: 697b ldr r3, [r7, #20] 8011d02: 691b ldr r3, [r3, #16] 8011d04: 431a orrs r2, r3 8011d06: 697b ldr r3, [r7, #20] 8011d08: 695b ldr r3, [r3, #20] 8011d0a: 431a orrs r2, r3 8011d0c: 697b ldr r3, [r7, #20] 8011d0e: 69db ldr r3, [r3, #28] 8011d10: 4313 orrs r3, r2 8011d12: 647b str r3, [r7, #68] @ 0x44 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 8011d14: 697b ldr r3, [r7, #20] 8011d16: 681b ldr r3, [r3, #0] 8011d18: 681a ldr r2, [r3, #0] 8011d1a: 4bbe ldr r3, [pc, #760] @ (8012014 ) 8011d1c: 4013 ands r3, r2 8011d1e: 697a ldr r2, [r7, #20] 8011d20: 6812 ldr r2, [r2, #0] 8011d22: 6c79 ldr r1, [r7, #68] @ 0x44 8011d24: 430b orrs r3, r1 8011d26: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8011d28: 697b ldr r3, [r7, #20] 8011d2a: 681b ldr r3, [r3, #0] 8011d2c: 685b ldr r3, [r3, #4] 8011d2e: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8011d32: 697b ldr r3, [r7, #20] 8011d34: 68da ldr r2, [r3, #12] 8011d36: 697b ldr r3, [r7, #20] 8011d38: 681b ldr r3, [r3, #0] 8011d3a: 430a orrs r2, r1 8011d3c: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 8011d3e: 697b ldr r3, [r7, #20] 8011d40: 699b ldr r3, [r3, #24] 8011d42: 647b str r3, [r7, #68] @ 0x44 if (!(UART_INSTANCE_LOWPOWER(huart))) 8011d44: 697b ldr r3, [r7, #20] 8011d46: 681b ldr r3, [r3, #0] 8011d48: 4ab3 ldr r2, [pc, #716] @ (8012018 ) 8011d4a: 4293 cmp r3, r2 8011d4c: d004 beq.n 8011d58 { tmpreg |= huart->Init.OneBitSampling; 8011d4e: 697b ldr r3, [r7, #20] 8011d50: 6a1b ldr r3, [r3, #32] 8011d52: 6c7a ldr r2, [r7, #68] @ 0x44 8011d54: 4313 orrs r3, r2 8011d56: 647b str r3, [r7, #68] @ 0x44 } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 8011d58: 697b ldr r3, [r7, #20] 8011d5a: 681b ldr r3, [r3, #0] 8011d5c: 689a ldr r2, [r3, #8] 8011d5e: 4baf ldr r3, [pc, #700] @ (801201c ) 8011d60: 4013 ands r3, r2 8011d62: 697a ldr r2, [r7, #20] 8011d64: 6812 ldr r2, [r2, #0] 8011d66: 6c79 ldr r1, [r7, #68] @ 0x44 8011d68: 430b orrs r3, r1 8011d6a: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 8011d6c: 697b ldr r3, [r7, #20] 8011d6e: 681b ldr r3, [r3, #0] 8011d70: 6adb ldr r3, [r3, #44] @ 0x2c 8011d72: f023 010f bic.w r1, r3, #15 8011d76: 697b ldr r3, [r7, #20] 8011d78: 6a5a ldr r2, [r3, #36] @ 0x24 8011d7a: 697b ldr r3, [r7, #20] 8011d7c: 681b ldr r3, [r3, #0] 8011d7e: 430a orrs r2, r1 8011d80: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 8011d82: 697b ldr r3, [r7, #20] 8011d84: 681b ldr r3, [r3, #0] 8011d86: 4aa6 ldr r2, [pc, #664] @ (8012020 ) 8011d88: 4293 cmp r3, r2 8011d8a: d177 bne.n 8011e7c 8011d8c: 4ba5 ldr r3, [pc, #660] @ (8012024 ) 8011d8e: 6d5b ldr r3, [r3, #84] @ 0x54 8011d90: f003 0338 and.w r3, r3, #56 @ 0x38 8011d94: 2b28 cmp r3, #40 @ 0x28 8011d96: d86d bhi.n 8011e74 8011d98: a201 add r2, pc, #4 @ (adr r2, 8011da0 ) 8011d9a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011d9e: bf00 nop 8011da0: 08011e45 .word 0x08011e45 8011da4: 08011e75 .word 0x08011e75 8011da8: 08011e75 .word 0x08011e75 8011dac: 08011e75 .word 0x08011e75 8011db0: 08011e75 .word 0x08011e75 8011db4: 08011e75 .word 0x08011e75 8011db8: 08011e75 .word 0x08011e75 8011dbc: 08011e75 .word 0x08011e75 8011dc0: 08011e4d .word 0x08011e4d 8011dc4: 08011e75 .word 0x08011e75 8011dc8: 08011e75 .word 0x08011e75 8011dcc: 08011e75 .word 0x08011e75 8011dd0: 08011e75 .word 0x08011e75 8011dd4: 08011e75 .word 0x08011e75 8011dd8: 08011e75 .word 0x08011e75 8011ddc: 08011e75 .word 0x08011e75 8011de0: 08011e55 .word 0x08011e55 8011de4: 08011e75 .word 0x08011e75 8011de8: 08011e75 .word 0x08011e75 8011dec: 08011e75 .word 0x08011e75 8011df0: 08011e75 .word 0x08011e75 8011df4: 08011e75 .word 0x08011e75 8011df8: 08011e75 .word 0x08011e75 8011dfc: 08011e75 .word 0x08011e75 8011e00: 08011e5d .word 0x08011e5d 8011e04: 08011e75 .word 0x08011e75 8011e08: 08011e75 .word 0x08011e75 8011e0c: 08011e75 .word 0x08011e75 8011e10: 08011e75 .word 0x08011e75 8011e14: 08011e75 .word 0x08011e75 8011e18: 08011e75 .word 0x08011e75 8011e1c: 08011e75 .word 0x08011e75 8011e20: 08011e65 .word 0x08011e65 8011e24: 08011e75 .word 0x08011e75 8011e28: 08011e75 .word 0x08011e75 8011e2c: 08011e75 .word 0x08011e75 8011e30: 08011e75 .word 0x08011e75 8011e34: 08011e75 .word 0x08011e75 8011e38: 08011e75 .word 0x08011e75 8011e3c: 08011e75 .word 0x08011e75 8011e40: 08011e6d .word 0x08011e6d 8011e44: 2301 movs r3, #1 8011e46: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e4a: e222 b.n 8012292 8011e4c: 2304 movs r3, #4 8011e4e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e52: e21e b.n 8012292 8011e54: 2308 movs r3, #8 8011e56: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e5a: e21a b.n 8012292 8011e5c: 2310 movs r3, #16 8011e5e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e62: e216 b.n 8012292 8011e64: 2320 movs r3, #32 8011e66: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e6a: e212 b.n 8012292 8011e6c: 2340 movs r3, #64 @ 0x40 8011e6e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e72: e20e b.n 8012292 8011e74: 2380 movs r3, #128 @ 0x80 8011e76: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e7a: e20a b.n 8012292 8011e7c: 697b ldr r3, [r7, #20] 8011e7e: 681b ldr r3, [r3, #0] 8011e80: 4a69 ldr r2, [pc, #420] @ (8012028 ) 8011e82: 4293 cmp r3, r2 8011e84: d130 bne.n 8011ee8 8011e86: 4b67 ldr r3, [pc, #412] @ (8012024 ) 8011e88: 6d5b ldr r3, [r3, #84] @ 0x54 8011e8a: f003 0307 and.w r3, r3, #7 8011e8e: 2b05 cmp r3, #5 8011e90: d826 bhi.n 8011ee0 8011e92: a201 add r2, pc, #4 @ (adr r2, 8011e98 ) 8011e94: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011e98: 08011eb1 .word 0x08011eb1 8011e9c: 08011eb9 .word 0x08011eb9 8011ea0: 08011ec1 .word 0x08011ec1 8011ea4: 08011ec9 .word 0x08011ec9 8011ea8: 08011ed1 .word 0x08011ed1 8011eac: 08011ed9 .word 0x08011ed9 8011eb0: 2300 movs r3, #0 8011eb2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011eb6: e1ec b.n 8012292 8011eb8: 2304 movs r3, #4 8011eba: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ebe: e1e8 b.n 8012292 8011ec0: 2308 movs r3, #8 8011ec2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ec6: e1e4 b.n 8012292 8011ec8: 2310 movs r3, #16 8011eca: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ece: e1e0 b.n 8012292 8011ed0: 2320 movs r3, #32 8011ed2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ed6: e1dc b.n 8012292 8011ed8: 2340 movs r3, #64 @ 0x40 8011eda: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ede: e1d8 b.n 8012292 8011ee0: 2380 movs r3, #128 @ 0x80 8011ee2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ee6: e1d4 b.n 8012292 8011ee8: 697b ldr r3, [r7, #20] 8011eea: 681b ldr r3, [r3, #0] 8011eec: 4a4f ldr r2, [pc, #316] @ (801202c ) 8011eee: 4293 cmp r3, r2 8011ef0: d130 bne.n 8011f54 8011ef2: 4b4c ldr r3, [pc, #304] @ (8012024 ) 8011ef4: 6d5b ldr r3, [r3, #84] @ 0x54 8011ef6: f003 0307 and.w r3, r3, #7 8011efa: 2b05 cmp r3, #5 8011efc: d826 bhi.n 8011f4c 8011efe: a201 add r2, pc, #4 @ (adr r2, 8011f04 ) 8011f00: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011f04: 08011f1d .word 0x08011f1d 8011f08: 08011f25 .word 0x08011f25 8011f0c: 08011f2d .word 0x08011f2d 8011f10: 08011f35 .word 0x08011f35 8011f14: 08011f3d .word 0x08011f3d 8011f18: 08011f45 .word 0x08011f45 8011f1c: 2300 movs r3, #0 8011f1e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f22: e1b6 b.n 8012292 8011f24: 2304 movs r3, #4 8011f26: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f2a: e1b2 b.n 8012292 8011f2c: 2308 movs r3, #8 8011f2e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f32: e1ae b.n 8012292 8011f34: 2310 movs r3, #16 8011f36: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f3a: e1aa b.n 8012292 8011f3c: 2320 movs r3, #32 8011f3e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f42: e1a6 b.n 8012292 8011f44: 2340 movs r3, #64 @ 0x40 8011f46: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f4a: e1a2 b.n 8012292 8011f4c: 2380 movs r3, #128 @ 0x80 8011f4e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f52: e19e b.n 8012292 8011f54: 697b ldr r3, [r7, #20] 8011f56: 681b ldr r3, [r3, #0] 8011f58: 4a35 ldr r2, [pc, #212] @ (8012030 ) 8011f5a: 4293 cmp r3, r2 8011f5c: d130 bne.n 8011fc0 8011f5e: 4b31 ldr r3, [pc, #196] @ (8012024 ) 8011f60: 6d5b ldr r3, [r3, #84] @ 0x54 8011f62: f003 0307 and.w r3, r3, #7 8011f66: 2b05 cmp r3, #5 8011f68: d826 bhi.n 8011fb8 8011f6a: a201 add r2, pc, #4 @ (adr r2, 8011f70 ) 8011f6c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011f70: 08011f89 .word 0x08011f89 8011f74: 08011f91 .word 0x08011f91 8011f78: 08011f99 .word 0x08011f99 8011f7c: 08011fa1 .word 0x08011fa1 8011f80: 08011fa9 .word 0x08011fa9 8011f84: 08011fb1 .word 0x08011fb1 8011f88: 2300 movs r3, #0 8011f8a: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f8e: e180 b.n 8012292 8011f90: 2304 movs r3, #4 8011f92: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f96: e17c b.n 8012292 8011f98: 2308 movs r3, #8 8011f9a: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f9e: e178 b.n 8012292 8011fa0: 2310 movs r3, #16 8011fa2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fa6: e174 b.n 8012292 8011fa8: 2320 movs r3, #32 8011faa: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fae: e170 b.n 8012292 8011fb0: 2340 movs r3, #64 @ 0x40 8011fb2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fb6: e16c b.n 8012292 8011fb8: 2380 movs r3, #128 @ 0x80 8011fba: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fbe: e168 b.n 8012292 8011fc0: 697b ldr r3, [r7, #20] 8011fc2: 681b ldr r3, [r3, #0] 8011fc4: 4a1b ldr r2, [pc, #108] @ (8012034 ) 8011fc6: 4293 cmp r3, r2 8011fc8: d142 bne.n 8012050 8011fca: 4b16 ldr r3, [pc, #88] @ (8012024 ) 8011fcc: 6d5b ldr r3, [r3, #84] @ 0x54 8011fce: f003 0307 and.w r3, r3, #7 8011fd2: 2b05 cmp r3, #5 8011fd4: d838 bhi.n 8012048 8011fd6: a201 add r2, pc, #4 @ (adr r2, 8011fdc ) 8011fd8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011fdc: 08011ff5 .word 0x08011ff5 8011fe0: 08011ffd .word 0x08011ffd 8011fe4: 08012005 .word 0x08012005 8011fe8: 0801200d .word 0x0801200d 8011fec: 08012039 .word 0x08012039 8011ff0: 08012041 .word 0x08012041 8011ff4: 2300 movs r3, #0 8011ff6: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ffa: e14a b.n 8012292 8011ffc: 2304 movs r3, #4 8011ffe: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012002: e146 b.n 8012292 8012004: 2308 movs r3, #8 8012006: f887 3043 strb.w r3, [r7, #67] @ 0x43 801200a: e142 b.n 8012292 801200c: 2310 movs r3, #16 801200e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012012: e13e b.n 8012292 8012014: cfff69f3 .word 0xcfff69f3 8012018: 58000c00 .word 0x58000c00 801201c: 11fff4ff .word 0x11fff4ff 8012020: 40011000 .word 0x40011000 8012024: 58024400 .word 0x58024400 8012028: 40004400 .word 0x40004400 801202c: 40004800 .word 0x40004800 8012030: 40004c00 .word 0x40004c00 8012034: 40005000 .word 0x40005000 8012038: 2320 movs r3, #32 801203a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801203e: e128 b.n 8012292 8012040: 2340 movs r3, #64 @ 0x40 8012042: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012046: e124 b.n 8012292 8012048: 2380 movs r3, #128 @ 0x80 801204a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801204e: e120 b.n 8012292 8012050: 697b ldr r3, [r7, #20] 8012052: 681b ldr r3, [r3, #0] 8012054: 4acb ldr r2, [pc, #812] @ (8012384 ) 8012056: 4293 cmp r3, r2 8012058: d176 bne.n 8012148 801205a: 4bcb ldr r3, [pc, #812] @ (8012388 ) 801205c: 6d5b ldr r3, [r3, #84] @ 0x54 801205e: f003 0338 and.w r3, r3, #56 @ 0x38 8012062: 2b28 cmp r3, #40 @ 0x28 8012064: d86c bhi.n 8012140 8012066: a201 add r2, pc, #4 @ (adr r2, 801206c ) 8012068: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801206c: 08012111 .word 0x08012111 8012070: 08012141 .word 0x08012141 8012074: 08012141 .word 0x08012141 8012078: 08012141 .word 0x08012141 801207c: 08012141 .word 0x08012141 8012080: 08012141 .word 0x08012141 8012084: 08012141 .word 0x08012141 8012088: 08012141 .word 0x08012141 801208c: 08012119 .word 0x08012119 8012090: 08012141 .word 0x08012141 8012094: 08012141 .word 0x08012141 8012098: 08012141 .word 0x08012141 801209c: 08012141 .word 0x08012141 80120a0: 08012141 .word 0x08012141 80120a4: 08012141 .word 0x08012141 80120a8: 08012141 .word 0x08012141 80120ac: 08012121 .word 0x08012121 80120b0: 08012141 .word 0x08012141 80120b4: 08012141 .word 0x08012141 80120b8: 08012141 .word 0x08012141 80120bc: 08012141 .word 0x08012141 80120c0: 08012141 .word 0x08012141 80120c4: 08012141 .word 0x08012141 80120c8: 08012141 .word 0x08012141 80120cc: 08012129 .word 0x08012129 80120d0: 08012141 .word 0x08012141 80120d4: 08012141 .word 0x08012141 80120d8: 08012141 .word 0x08012141 80120dc: 08012141 .word 0x08012141 80120e0: 08012141 .word 0x08012141 80120e4: 08012141 .word 0x08012141 80120e8: 08012141 .word 0x08012141 80120ec: 08012131 .word 0x08012131 80120f0: 08012141 .word 0x08012141 80120f4: 08012141 .word 0x08012141 80120f8: 08012141 .word 0x08012141 80120fc: 08012141 .word 0x08012141 8012100: 08012141 .word 0x08012141 8012104: 08012141 .word 0x08012141 8012108: 08012141 .word 0x08012141 801210c: 08012139 .word 0x08012139 8012110: 2301 movs r3, #1 8012112: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012116: e0bc b.n 8012292 8012118: 2304 movs r3, #4 801211a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801211e: e0b8 b.n 8012292 8012120: 2308 movs r3, #8 8012122: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012126: e0b4 b.n 8012292 8012128: 2310 movs r3, #16 801212a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801212e: e0b0 b.n 8012292 8012130: 2320 movs r3, #32 8012132: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012136: e0ac b.n 8012292 8012138: 2340 movs r3, #64 @ 0x40 801213a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801213e: e0a8 b.n 8012292 8012140: 2380 movs r3, #128 @ 0x80 8012142: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012146: e0a4 b.n 8012292 8012148: 697b ldr r3, [r7, #20] 801214a: 681b ldr r3, [r3, #0] 801214c: 4a8f ldr r2, [pc, #572] @ (801238c ) 801214e: 4293 cmp r3, r2 8012150: d130 bne.n 80121b4 8012152: 4b8d ldr r3, [pc, #564] @ (8012388 ) 8012154: 6d5b ldr r3, [r3, #84] @ 0x54 8012156: f003 0307 and.w r3, r3, #7 801215a: 2b05 cmp r3, #5 801215c: d826 bhi.n 80121ac 801215e: a201 add r2, pc, #4 @ (adr r2, 8012164 ) 8012160: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012164: 0801217d .word 0x0801217d 8012168: 08012185 .word 0x08012185 801216c: 0801218d .word 0x0801218d 8012170: 08012195 .word 0x08012195 8012174: 0801219d .word 0x0801219d 8012178: 080121a5 .word 0x080121a5 801217c: 2300 movs r3, #0 801217e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012182: e086 b.n 8012292 8012184: 2304 movs r3, #4 8012186: f887 3043 strb.w r3, [r7, #67] @ 0x43 801218a: e082 b.n 8012292 801218c: 2308 movs r3, #8 801218e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012192: e07e b.n 8012292 8012194: 2310 movs r3, #16 8012196: f887 3043 strb.w r3, [r7, #67] @ 0x43 801219a: e07a b.n 8012292 801219c: 2320 movs r3, #32 801219e: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121a2: e076 b.n 8012292 80121a4: 2340 movs r3, #64 @ 0x40 80121a6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121aa: e072 b.n 8012292 80121ac: 2380 movs r3, #128 @ 0x80 80121ae: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121b2: e06e b.n 8012292 80121b4: 697b ldr r3, [r7, #20] 80121b6: 681b ldr r3, [r3, #0] 80121b8: 4a75 ldr r2, [pc, #468] @ (8012390 ) 80121ba: 4293 cmp r3, r2 80121bc: d130 bne.n 8012220 80121be: 4b72 ldr r3, [pc, #456] @ (8012388 ) 80121c0: 6d5b ldr r3, [r3, #84] @ 0x54 80121c2: f003 0307 and.w r3, r3, #7 80121c6: 2b05 cmp r3, #5 80121c8: d826 bhi.n 8012218 80121ca: a201 add r2, pc, #4 @ (adr r2, 80121d0 ) 80121cc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80121d0: 080121e9 .word 0x080121e9 80121d4: 080121f1 .word 0x080121f1 80121d8: 080121f9 .word 0x080121f9 80121dc: 08012201 .word 0x08012201 80121e0: 08012209 .word 0x08012209 80121e4: 08012211 .word 0x08012211 80121e8: 2300 movs r3, #0 80121ea: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121ee: e050 b.n 8012292 80121f0: 2304 movs r3, #4 80121f2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121f6: e04c b.n 8012292 80121f8: 2308 movs r3, #8 80121fa: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121fe: e048 b.n 8012292 8012200: 2310 movs r3, #16 8012202: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012206: e044 b.n 8012292 8012208: 2320 movs r3, #32 801220a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801220e: e040 b.n 8012292 8012210: 2340 movs r3, #64 @ 0x40 8012212: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012216: e03c b.n 8012292 8012218: 2380 movs r3, #128 @ 0x80 801221a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801221e: e038 b.n 8012292 8012220: 697b ldr r3, [r7, #20] 8012222: 681b ldr r3, [r3, #0] 8012224: 4a5b ldr r2, [pc, #364] @ (8012394 ) 8012226: 4293 cmp r3, r2 8012228: d130 bne.n 801228c 801222a: 4b57 ldr r3, [pc, #348] @ (8012388 ) 801222c: 6d9b ldr r3, [r3, #88] @ 0x58 801222e: f003 0307 and.w r3, r3, #7 8012232: 2b05 cmp r3, #5 8012234: d826 bhi.n 8012284 8012236: a201 add r2, pc, #4 @ (adr r2, 801223c ) 8012238: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801223c: 08012255 .word 0x08012255 8012240: 0801225d .word 0x0801225d 8012244: 08012265 .word 0x08012265 8012248: 0801226d .word 0x0801226d 801224c: 08012275 .word 0x08012275 8012250: 0801227d .word 0x0801227d 8012254: 2302 movs r3, #2 8012256: f887 3043 strb.w r3, [r7, #67] @ 0x43 801225a: e01a b.n 8012292 801225c: 2304 movs r3, #4 801225e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012262: e016 b.n 8012292 8012264: 2308 movs r3, #8 8012266: f887 3043 strb.w r3, [r7, #67] @ 0x43 801226a: e012 b.n 8012292 801226c: 2310 movs r3, #16 801226e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012272: e00e b.n 8012292 8012274: 2320 movs r3, #32 8012276: f887 3043 strb.w r3, [r7, #67] @ 0x43 801227a: e00a b.n 8012292 801227c: 2340 movs r3, #64 @ 0x40 801227e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012282: e006 b.n 8012292 8012284: 2380 movs r3, #128 @ 0x80 8012286: f887 3043 strb.w r3, [r7, #67] @ 0x43 801228a: e002 b.n 8012292 801228c: 2380 movs r3, #128 @ 0x80 801228e: f887 3043 strb.w r3, [r7, #67] @ 0x43 /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 8012292: 697b ldr r3, [r7, #20] 8012294: 681b ldr r3, [r3, #0] 8012296: 4a3f ldr r2, [pc, #252] @ (8012394 ) 8012298: 4293 cmp r3, r2 801229a: f040 80f8 bne.w 801248e { /* Retrieve frequency clock */ switch (clocksource) 801229e: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 80122a2: 2b20 cmp r3, #32 80122a4: dc46 bgt.n 8012334 80122a6: 2b02 cmp r3, #2 80122a8: f2c0 8082 blt.w 80123b0 80122ac: 3b02 subs r3, #2 80122ae: 2b1e cmp r3, #30 80122b0: d87e bhi.n 80123b0 80122b2: a201 add r2, pc, #4 @ (adr r2, 80122b8 ) 80122b4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80122b8: 0801233b .word 0x0801233b 80122bc: 080123b1 .word 0x080123b1 80122c0: 08012343 .word 0x08012343 80122c4: 080123b1 .word 0x080123b1 80122c8: 080123b1 .word 0x080123b1 80122cc: 080123b1 .word 0x080123b1 80122d0: 08012353 .word 0x08012353 80122d4: 080123b1 .word 0x080123b1 80122d8: 080123b1 .word 0x080123b1 80122dc: 080123b1 .word 0x080123b1 80122e0: 080123b1 .word 0x080123b1 80122e4: 080123b1 .word 0x080123b1 80122e8: 080123b1 .word 0x080123b1 80122ec: 080123b1 .word 0x080123b1 80122f0: 08012363 .word 0x08012363 80122f4: 080123b1 .word 0x080123b1 80122f8: 080123b1 .word 0x080123b1 80122fc: 080123b1 .word 0x080123b1 8012300: 080123b1 .word 0x080123b1 8012304: 080123b1 .word 0x080123b1 8012308: 080123b1 .word 0x080123b1 801230c: 080123b1 .word 0x080123b1 8012310: 080123b1 .word 0x080123b1 8012314: 080123b1 .word 0x080123b1 8012318: 080123b1 .word 0x080123b1 801231c: 080123b1 .word 0x080123b1 8012320: 080123b1 .word 0x080123b1 8012324: 080123b1 .word 0x080123b1 8012328: 080123b1 .word 0x080123b1 801232c: 080123b1 .word 0x080123b1 8012330: 080123a3 .word 0x080123a3 8012334: 2b40 cmp r3, #64 @ 0x40 8012336: d037 beq.n 80123a8 8012338: e03a b.n 80123b0 { case UART_CLOCKSOURCE_D3PCLK1: pclk = HAL_RCCEx_GetD3PCLK1Freq(); 801233a: f7fc fa8b bl 800e854 801233e: 63f8 str r0, [r7, #60] @ 0x3c break; 8012340: e03c b.n 80123bc case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8012342: f107 0324 add.w r3, r7, #36 @ 0x24 8012346: 4618 mov r0, r3 8012348: f7fc fa9a bl 800e880 pclk = pll2_clocks.PLL2_Q_Frequency; 801234c: 6abb ldr r3, [r7, #40] @ 0x28 801234e: 63fb str r3, [r7, #60] @ 0x3c break; 8012350: e034 b.n 80123bc case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8012352: f107 0318 add.w r3, r7, #24 8012356: 4618 mov r0, r3 8012358: f7fc fbe6 bl 800eb28 pclk = pll3_clocks.PLL3_Q_Frequency; 801235c: 69fb ldr r3, [r7, #28] 801235e: 63fb str r3, [r7, #60] @ 0x3c break; 8012360: e02c b.n 80123bc case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8012362: 4b09 ldr r3, [pc, #36] @ (8012388 ) 8012364: 681b ldr r3, [r3, #0] 8012366: f003 0320 and.w r3, r3, #32 801236a: 2b00 cmp r3, #0 801236c: d016 beq.n 801239c { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 801236e: 4b06 ldr r3, [pc, #24] @ (8012388 ) 8012370: 681b ldr r3, [r3, #0] 8012372: 08db lsrs r3, r3, #3 8012374: f003 0303 and.w r3, r3, #3 8012378: 4a07 ldr r2, [pc, #28] @ (8012398 ) 801237a: fa22 f303 lsr.w r3, r2, r3 801237e: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8012380: e01c b.n 80123bc 8012382: bf00 nop 8012384: 40011400 .word 0x40011400 8012388: 58024400 .word 0x58024400 801238c: 40007800 .word 0x40007800 8012390: 40007c00 .word 0x40007c00 8012394: 58000c00 .word 0x58000c00 8012398: 03d09000 .word 0x03d09000 pclk = (uint32_t) HSI_VALUE; 801239c: 4b9d ldr r3, [pc, #628] @ (8012614 ) 801239e: 63fb str r3, [r7, #60] @ 0x3c break; 80123a0: e00c b.n 80123bc case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 80123a2: 4b9d ldr r3, [pc, #628] @ (8012618 ) 80123a4: 63fb str r3, [r7, #60] @ 0x3c break; 80123a6: e009 b.n 80123bc case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 80123a8: f44f 4300 mov.w r3, #32768 @ 0x8000 80123ac: 63fb str r3, [r7, #60] @ 0x3c break; 80123ae: e005 b.n 80123bc default: pclk = 0U; 80123b0: 2300 movs r3, #0 80123b2: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 80123b4: 2301 movs r3, #1 80123b6: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 80123ba: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 80123bc: 6bfb ldr r3, [r7, #60] @ 0x3c 80123be: 2b00 cmp r3, #0 80123c0: f000 81de beq.w 8012780 { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 80123c4: 697b ldr r3, [r7, #20] 80123c6: 6a5b ldr r3, [r3, #36] @ 0x24 80123c8: 4a94 ldr r2, [pc, #592] @ (801261c ) 80123ca: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80123ce: 461a mov r2, r3 80123d0: 6bfb ldr r3, [r7, #60] @ 0x3c 80123d2: fbb3 f3f2 udiv r3, r3, r2 80123d6: 633b str r3, [r7, #48] @ 0x30 /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 80123d8: 697b ldr r3, [r7, #20] 80123da: 685a ldr r2, [r3, #4] 80123dc: 4613 mov r3, r2 80123de: 005b lsls r3, r3, #1 80123e0: 4413 add r3, r2 80123e2: 6b3a ldr r2, [r7, #48] @ 0x30 80123e4: 429a cmp r2, r3 80123e6: d305 bcc.n 80123f4 (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) 80123e8: 697b ldr r3, [r7, #20] 80123ea: 685b ldr r3, [r3, #4] 80123ec: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 80123ee: 6b3a ldr r2, [r7, #48] @ 0x30 80123f0: 429a cmp r2, r3 80123f2: d903 bls.n 80123fc { ret = HAL_ERROR; 80123f4: 2301 movs r3, #1 80123f6: f887 3042 strb.w r3, [r7, #66] @ 0x42 80123fa: e1c1 b.n 8012780 } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 80123fc: 6bfb ldr r3, [r7, #60] @ 0x3c 80123fe: 2200 movs r2, #0 8012400: 60bb str r3, [r7, #8] 8012402: 60fa str r2, [r7, #12] 8012404: 697b ldr r3, [r7, #20] 8012406: 6a5b ldr r3, [r3, #36] @ 0x24 8012408: 4a84 ldr r2, [pc, #528] @ (801261c ) 801240a: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 801240e: b29b uxth r3, r3 8012410: 2200 movs r2, #0 8012412: 603b str r3, [r7, #0] 8012414: 607a str r2, [r7, #4] 8012416: e9d7 2300 ldrd r2, r3, [r7] 801241a: e9d7 0102 ldrd r0, r1, [r7, #8] 801241e: f7ed ff5f bl 80002e0 <__aeabi_uldivmod> 8012422: 4602 mov r2, r0 8012424: 460b mov r3, r1 8012426: 4610 mov r0, r2 8012428: 4619 mov r1, r3 801242a: f04f 0200 mov.w r2, #0 801242e: f04f 0300 mov.w r3, #0 8012432: 020b lsls r3, r1, #8 8012434: ea43 6310 orr.w r3, r3, r0, lsr #24 8012438: 0202 lsls r2, r0, #8 801243a: 6979 ldr r1, [r7, #20] 801243c: 6849 ldr r1, [r1, #4] 801243e: 0849 lsrs r1, r1, #1 8012440: 2000 movs r0, #0 8012442: 460c mov r4, r1 8012444: 4605 mov r5, r0 8012446: eb12 0804 adds.w r8, r2, r4 801244a: eb43 0905 adc.w r9, r3, r5 801244e: 697b ldr r3, [r7, #20] 8012450: 685b ldr r3, [r3, #4] 8012452: 2200 movs r2, #0 8012454: 469a mov sl, r3 8012456: 4693 mov fp, r2 8012458: 4652 mov r2, sl 801245a: 465b mov r3, fp 801245c: 4640 mov r0, r8 801245e: 4649 mov r1, r9 8012460: f7ed ff3e bl 80002e0 <__aeabi_uldivmod> 8012464: 4602 mov r2, r0 8012466: 460b mov r3, r1 8012468: 4613 mov r3, r2 801246a: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 801246c: 6bbb ldr r3, [r7, #56] @ 0x38 801246e: f5b3 7f40 cmp.w r3, #768 @ 0x300 8012472: d308 bcc.n 8012486 8012474: 6bbb ldr r3, [r7, #56] @ 0x38 8012476: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 801247a: d204 bcs.n 8012486 { huart->Instance->BRR = usartdiv; 801247c: 697b ldr r3, [r7, #20] 801247e: 681b ldr r3, [r3, #0] 8012480: 6bba ldr r2, [r7, #56] @ 0x38 8012482: 60da str r2, [r3, #12] 8012484: e17c b.n 8012780 } else { ret = HAL_ERROR; 8012486: 2301 movs r3, #1 8012488: f887 3042 strb.w r3, [r7, #66] @ 0x42 801248c: e178 b.n 8012780 } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 801248e: 697b ldr r3, [r7, #20] 8012490: 69db ldr r3, [r3, #28] 8012492: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8012496: f040 80c5 bne.w 8012624 { switch (clocksource) 801249a: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 801249e: 2b20 cmp r3, #32 80124a0: dc48 bgt.n 8012534 80124a2: 2b00 cmp r3, #0 80124a4: db7b blt.n 801259e 80124a6: 2b20 cmp r3, #32 80124a8: d879 bhi.n 801259e 80124aa: a201 add r2, pc, #4 @ (adr r2, 80124b0 ) 80124ac: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80124b0: 0801253b .word 0x0801253b 80124b4: 08012543 .word 0x08012543 80124b8: 0801259f .word 0x0801259f 80124bc: 0801259f .word 0x0801259f 80124c0: 0801254b .word 0x0801254b 80124c4: 0801259f .word 0x0801259f 80124c8: 0801259f .word 0x0801259f 80124cc: 0801259f .word 0x0801259f 80124d0: 0801255b .word 0x0801255b 80124d4: 0801259f .word 0x0801259f 80124d8: 0801259f .word 0x0801259f 80124dc: 0801259f .word 0x0801259f 80124e0: 0801259f .word 0x0801259f 80124e4: 0801259f .word 0x0801259f 80124e8: 0801259f .word 0x0801259f 80124ec: 0801259f .word 0x0801259f 80124f0: 0801256b .word 0x0801256b 80124f4: 0801259f .word 0x0801259f 80124f8: 0801259f .word 0x0801259f 80124fc: 0801259f .word 0x0801259f 8012500: 0801259f .word 0x0801259f 8012504: 0801259f .word 0x0801259f 8012508: 0801259f .word 0x0801259f 801250c: 0801259f .word 0x0801259f 8012510: 0801259f .word 0x0801259f 8012514: 0801259f .word 0x0801259f 8012518: 0801259f .word 0x0801259f 801251c: 0801259f .word 0x0801259f 8012520: 0801259f .word 0x0801259f 8012524: 0801259f .word 0x0801259f 8012528: 0801259f .word 0x0801259f 801252c: 0801259f .word 0x0801259f 8012530: 08012591 .word 0x08012591 8012534: 2b40 cmp r3, #64 @ 0x40 8012536: d02e beq.n 8012596 8012538: e031 b.n 801259e { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 801253a: f7fa f9af bl 800c89c 801253e: 63f8 str r0, [r7, #60] @ 0x3c break; 8012540: e033 b.n 80125aa case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8012542: f7fa f9c1 bl 800c8c8 8012546: 63f8 str r0, [r7, #60] @ 0x3c break; 8012548: e02f b.n 80125aa case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 801254a: f107 0324 add.w r3, r7, #36 @ 0x24 801254e: 4618 mov r0, r3 8012550: f7fc f996 bl 800e880 pclk = pll2_clocks.PLL2_Q_Frequency; 8012554: 6abb ldr r3, [r7, #40] @ 0x28 8012556: 63fb str r3, [r7, #60] @ 0x3c break; 8012558: e027 b.n 80125aa case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 801255a: f107 0318 add.w r3, r7, #24 801255e: 4618 mov r0, r3 8012560: f7fc fae2 bl 800eb28 pclk = pll3_clocks.PLL3_Q_Frequency; 8012564: 69fb ldr r3, [r7, #28] 8012566: 63fb str r3, [r7, #60] @ 0x3c break; 8012568: e01f b.n 80125aa case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 801256a: 4b2d ldr r3, [pc, #180] @ (8012620 ) 801256c: 681b ldr r3, [r3, #0] 801256e: f003 0320 and.w r3, r3, #32 8012572: 2b00 cmp r3, #0 8012574: d009 beq.n 801258a { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8012576: 4b2a ldr r3, [pc, #168] @ (8012620 ) 8012578: 681b ldr r3, [r3, #0] 801257a: 08db lsrs r3, r3, #3 801257c: f003 0303 and.w r3, r3, #3 8012580: 4a24 ldr r2, [pc, #144] @ (8012614 ) 8012582: fa22 f303 lsr.w r3, r2, r3 8012586: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8012588: e00f b.n 80125aa pclk = (uint32_t) HSI_VALUE; 801258a: 4b22 ldr r3, [pc, #136] @ (8012614 ) 801258c: 63fb str r3, [r7, #60] @ 0x3c break; 801258e: e00c b.n 80125aa case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 8012590: 4b21 ldr r3, [pc, #132] @ (8012618 ) 8012592: 63fb str r3, [r7, #60] @ 0x3c break; 8012594: e009 b.n 80125aa case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8012596: f44f 4300 mov.w r3, #32768 @ 0x8000 801259a: 63fb str r3, [r7, #60] @ 0x3c break; 801259c: e005 b.n 80125aa default: pclk = 0U; 801259e: 2300 movs r3, #0 80125a0: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 80125a2: 2301 movs r3, #1 80125a4: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 80125a8: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 80125aa: 6bfb ldr r3, [r7, #60] @ 0x3c 80125ac: 2b00 cmp r3, #0 80125ae: f000 80e7 beq.w 8012780 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 80125b2: 697b ldr r3, [r7, #20] 80125b4: 6a5b ldr r3, [r3, #36] @ 0x24 80125b6: 4a19 ldr r2, [pc, #100] @ (801261c ) 80125b8: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80125bc: 461a mov r2, r3 80125be: 6bfb ldr r3, [r7, #60] @ 0x3c 80125c0: fbb3 f3f2 udiv r3, r3, r2 80125c4: 005a lsls r2, r3, #1 80125c6: 697b ldr r3, [r7, #20] 80125c8: 685b ldr r3, [r3, #4] 80125ca: 085b lsrs r3, r3, #1 80125cc: 441a add r2, r3 80125ce: 697b ldr r3, [r7, #20] 80125d0: 685b ldr r3, [r3, #4] 80125d2: fbb2 f3f3 udiv r3, r2, r3 80125d6: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 80125d8: 6bbb ldr r3, [r7, #56] @ 0x38 80125da: 2b0f cmp r3, #15 80125dc: d916 bls.n 801260c 80125de: 6bbb ldr r3, [r7, #56] @ 0x38 80125e0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80125e4: d212 bcs.n 801260c { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 80125e6: 6bbb ldr r3, [r7, #56] @ 0x38 80125e8: b29b uxth r3, r3 80125ea: f023 030f bic.w r3, r3, #15 80125ee: 86fb strh r3, [r7, #54] @ 0x36 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 80125f0: 6bbb ldr r3, [r7, #56] @ 0x38 80125f2: 085b lsrs r3, r3, #1 80125f4: b29b uxth r3, r3 80125f6: f003 0307 and.w r3, r3, #7 80125fa: b29a uxth r2, r3 80125fc: 8efb ldrh r3, [r7, #54] @ 0x36 80125fe: 4313 orrs r3, r2 8012600: 86fb strh r3, [r7, #54] @ 0x36 huart->Instance->BRR = brrtemp; 8012602: 697b ldr r3, [r7, #20] 8012604: 681b ldr r3, [r3, #0] 8012606: 8efa ldrh r2, [r7, #54] @ 0x36 8012608: 60da str r2, [r3, #12] 801260a: e0b9 b.n 8012780 } else { ret = HAL_ERROR; 801260c: 2301 movs r3, #1 801260e: f887 3042 strb.w r3, [r7, #66] @ 0x42 8012612: e0b5 b.n 8012780 8012614: 03d09000 .word 0x03d09000 8012618: 003d0900 .word 0x003d0900 801261c: 080186f4 .word 0x080186f4 8012620: 58024400 .word 0x58024400 } } } else { switch (clocksource) 8012624: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 8012628: 2b20 cmp r3, #32 801262a: dc49 bgt.n 80126c0 801262c: 2b00 cmp r3, #0 801262e: db7c blt.n 801272a 8012630: 2b20 cmp r3, #32 8012632: d87a bhi.n 801272a 8012634: a201 add r2, pc, #4 @ (adr r2, 801263c ) 8012636: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801263a: bf00 nop 801263c: 080126c7 .word 0x080126c7 8012640: 080126cf .word 0x080126cf 8012644: 0801272b .word 0x0801272b 8012648: 0801272b .word 0x0801272b 801264c: 080126d7 .word 0x080126d7 8012650: 0801272b .word 0x0801272b 8012654: 0801272b .word 0x0801272b 8012658: 0801272b .word 0x0801272b 801265c: 080126e7 .word 0x080126e7 8012660: 0801272b .word 0x0801272b 8012664: 0801272b .word 0x0801272b 8012668: 0801272b .word 0x0801272b 801266c: 0801272b .word 0x0801272b 8012670: 0801272b .word 0x0801272b 8012674: 0801272b .word 0x0801272b 8012678: 0801272b .word 0x0801272b 801267c: 080126f7 .word 0x080126f7 8012680: 0801272b .word 0x0801272b 8012684: 0801272b .word 0x0801272b 8012688: 0801272b .word 0x0801272b 801268c: 0801272b .word 0x0801272b 8012690: 0801272b .word 0x0801272b 8012694: 0801272b .word 0x0801272b 8012698: 0801272b .word 0x0801272b 801269c: 0801272b .word 0x0801272b 80126a0: 0801272b .word 0x0801272b 80126a4: 0801272b .word 0x0801272b 80126a8: 0801272b .word 0x0801272b 80126ac: 0801272b .word 0x0801272b 80126b0: 0801272b .word 0x0801272b 80126b4: 0801272b .word 0x0801272b 80126b8: 0801272b .word 0x0801272b 80126bc: 0801271d .word 0x0801271d 80126c0: 2b40 cmp r3, #64 @ 0x40 80126c2: d02e beq.n 8012722 80126c4: e031 b.n 801272a { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 80126c6: f7fa f8e9 bl 800c89c 80126ca: 63f8 str r0, [r7, #60] @ 0x3c break; 80126cc: e033 b.n 8012736 case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 80126ce: f7fa f8fb bl 800c8c8 80126d2: 63f8 str r0, [r7, #60] @ 0x3c break; 80126d4: e02f b.n 8012736 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80126d6: f107 0324 add.w r3, r7, #36 @ 0x24 80126da: 4618 mov r0, r3 80126dc: f7fc f8d0 bl 800e880 pclk = pll2_clocks.PLL2_Q_Frequency; 80126e0: 6abb ldr r3, [r7, #40] @ 0x28 80126e2: 63fb str r3, [r7, #60] @ 0x3c break; 80126e4: e027 b.n 8012736 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 80126e6: f107 0318 add.w r3, r7, #24 80126ea: 4618 mov r0, r3 80126ec: f7fc fa1c bl 800eb28 pclk = pll3_clocks.PLL3_Q_Frequency; 80126f0: 69fb ldr r3, [r7, #28] 80126f2: 63fb str r3, [r7, #60] @ 0x3c break; 80126f4: e01f b.n 8012736 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 80126f6: 4b2d ldr r3, [pc, #180] @ (80127ac ) 80126f8: 681b ldr r3, [r3, #0] 80126fa: f003 0320 and.w r3, r3, #32 80126fe: 2b00 cmp r3, #0 8012700: d009 beq.n 8012716 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8012702: 4b2a ldr r3, [pc, #168] @ (80127ac ) 8012704: 681b ldr r3, [r3, #0] 8012706: 08db lsrs r3, r3, #3 8012708: f003 0303 and.w r3, r3, #3 801270c: 4a28 ldr r2, [pc, #160] @ (80127b0 ) 801270e: fa22 f303 lsr.w r3, r2, r3 8012712: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8012714: e00f b.n 8012736 pclk = (uint32_t) HSI_VALUE; 8012716: 4b26 ldr r3, [pc, #152] @ (80127b0 ) 8012718: 63fb str r3, [r7, #60] @ 0x3c break; 801271a: e00c b.n 8012736 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 801271c: 4b25 ldr r3, [pc, #148] @ (80127b4 ) 801271e: 63fb str r3, [r7, #60] @ 0x3c break; 8012720: e009 b.n 8012736 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8012722: f44f 4300 mov.w r3, #32768 @ 0x8000 8012726: 63fb str r3, [r7, #60] @ 0x3c break; 8012728: e005 b.n 8012736 default: pclk = 0U; 801272a: 2300 movs r3, #0 801272c: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 801272e: 2301 movs r3, #1 8012730: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 8012734: bf00 nop } if (pclk != 0U) 8012736: 6bfb ldr r3, [r7, #60] @ 0x3c 8012738: 2b00 cmp r3, #0 801273a: d021 beq.n 8012780 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 801273c: 697b ldr r3, [r7, #20] 801273e: 6a5b ldr r3, [r3, #36] @ 0x24 8012740: 4a1d ldr r2, [pc, #116] @ (80127b8 ) 8012742: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8012746: 461a mov r2, r3 8012748: 6bfb ldr r3, [r7, #60] @ 0x3c 801274a: fbb3 f2f2 udiv r2, r3, r2 801274e: 697b ldr r3, [r7, #20] 8012750: 685b ldr r3, [r3, #4] 8012752: 085b lsrs r3, r3, #1 8012754: 441a add r2, r3 8012756: 697b ldr r3, [r7, #20] 8012758: 685b ldr r3, [r3, #4] 801275a: fbb2 f3f3 udiv r3, r2, r3 801275e: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8012760: 6bbb ldr r3, [r7, #56] @ 0x38 8012762: 2b0f cmp r3, #15 8012764: d909 bls.n 801277a 8012766: 6bbb ldr r3, [r7, #56] @ 0x38 8012768: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 801276c: d205 bcs.n 801277a { huart->Instance->BRR = (uint16_t)usartdiv; 801276e: 6bbb ldr r3, [r7, #56] @ 0x38 8012770: b29a uxth r2, r3 8012772: 697b ldr r3, [r7, #20] 8012774: 681b ldr r3, [r3, #0] 8012776: 60da str r2, [r3, #12] 8012778: e002 b.n 8012780 } else { ret = HAL_ERROR; 801277a: 2301 movs r3, #1 801277c: f887 3042 strb.w r3, [r7, #66] @ 0x42 } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 8012780: 697b ldr r3, [r7, #20] 8012782: 2201 movs r2, #1 8012784: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1; 8012788: 697b ldr r3, [r7, #20] 801278a: 2201 movs r2, #1 801278c: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; 8012790: 697b ldr r3, [r7, #20] 8012792: 2200 movs r2, #0 8012794: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 8012796: 697b ldr r3, [r7, #20] 8012798: 2200 movs r2, #0 801279a: 679a str r2, [r3, #120] @ 0x78 return ret; 801279c: f897 3042 ldrb.w r3, [r7, #66] @ 0x42 } 80127a0: 4618 mov r0, r3 80127a2: 3748 adds r7, #72 @ 0x48 80127a4: 46bd mov sp, r7 80127a6: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 80127aa: bf00 nop 80127ac: 58024400 .word 0x58024400 80127b0: 03d09000 .word 0x03d09000 80127b4: 003d0900 .word 0x003d0900 80127b8: 080186f4 .word 0x080186f4 080127bc : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 80127bc: b480 push {r7} 80127be: b083 sub sp, #12 80127c0: af00 add r7, sp, #0 80127c2: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 80127c4: 687b ldr r3, [r7, #4] 80127c6: 6a9b ldr r3, [r3, #40] @ 0x28 80127c8: f003 0308 and.w r3, r3, #8 80127cc: 2b00 cmp r3, #0 80127ce: d00a beq.n 80127e6 { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 80127d0: 687b ldr r3, [r7, #4] 80127d2: 681b ldr r3, [r3, #0] 80127d4: 685b ldr r3, [r3, #4] 80127d6: f423 4100 bic.w r1, r3, #32768 @ 0x8000 80127da: 687b ldr r3, [r7, #4] 80127dc: 6b9a ldr r2, [r3, #56] @ 0x38 80127de: 687b ldr r3, [r7, #4] 80127e0: 681b ldr r3, [r3, #0] 80127e2: 430a orrs r2, r1 80127e4: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 80127e6: 687b ldr r3, [r7, #4] 80127e8: 6a9b ldr r3, [r3, #40] @ 0x28 80127ea: f003 0301 and.w r3, r3, #1 80127ee: 2b00 cmp r3, #0 80127f0: d00a beq.n 8012808 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 80127f2: 687b ldr r3, [r7, #4] 80127f4: 681b ldr r3, [r3, #0] 80127f6: 685b ldr r3, [r3, #4] 80127f8: f423 3100 bic.w r1, r3, #131072 @ 0x20000 80127fc: 687b ldr r3, [r7, #4] 80127fe: 6ada ldr r2, [r3, #44] @ 0x2c 8012800: 687b ldr r3, [r7, #4] 8012802: 681b ldr r3, [r3, #0] 8012804: 430a orrs r2, r1 8012806: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 8012808: 687b ldr r3, [r7, #4] 801280a: 6a9b ldr r3, [r3, #40] @ 0x28 801280c: f003 0302 and.w r3, r3, #2 8012810: 2b00 cmp r3, #0 8012812: d00a beq.n 801282a { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 8012814: 687b ldr r3, [r7, #4] 8012816: 681b ldr r3, [r3, #0] 8012818: 685b ldr r3, [r3, #4] 801281a: f423 3180 bic.w r1, r3, #65536 @ 0x10000 801281e: 687b ldr r3, [r7, #4] 8012820: 6b1a ldr r2, [r3, #48] @ 0x30 8012822: 687b ldr r3, [r7, #4] 8012824: 681b ldr r3, [r3, #0] 8012826: 430a orrs r2, r1 8012828: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 801282a: 687b ldr r3, [r7, #4] 801282c: 6a9b ldr r3, [r3, #40] @ 0x28 801282e: f003 0304 and.w r3, r3, #4 8012832: 2b00 cmp r3, #0 8012834: d00a beq.n 801284c { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 8012836: 687b ldr r3, [r7, #4] 8012838: 681b ldr r3, [r3, #0] 801283a: 685b ldr r3, [r3, #4] 801283c: f423 2180 bic.w r1, r3, #262144 @ 0x40000 8012840: 687b ldr r3, [r7, #4] 8012842: 6b5a ldr r2, [r3, #52] @ 0x34 8012844: 687b ldr r3, [r7, #4] 8012846: 681b ldr r3, [r3, #0] 8012848: 430a orrs r2, r1 801284a: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 801284c: 687b ldr r3, [r7, #4] 801284e: 6a9b ldr r3, [r3, #40] @ 0x28 8012850: f003 0310 and.w r3, r3, #16 8012854: 2b00 cmp r3, #0 8012856: d00a beq.n 801286e { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 8012858: 687b ldr r3, [r7, #4] 801285a: 681b ldr r3, [r3, #0] 801285c: 689b ldr r3, [r3, #8] 801285e: f423 5180 bic.w r1, r3, #4096 @ 0x1000 8012862: 687b ldr r3, [r7, #4] 8012864: 6bda ldr r2, [r3, #60] @ 0x3c 8012866: 687b ldr r3, [r7, #4] 8012868: 681b ldr r3, [r3, #0] 801286a: 430a orrs r2, r1 801286c: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 801286e: 687b ldr r3, [r7, #4] 8012870: 6a9b ldr r3, [r3, #40] @ 0x28 8012872: f003 0320 and.w r3, r3, #32 8012876: 2b00 cmp r3, #0 8012878: d00a beq.n 8012890 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 801287a: 687b ldr r3, [r7, #4] 801287c: 681b ldr r3, [r3, #0] 801287e: 689b ldr r3, [r3, #8] 8012880: f423 5100 bic.w r1, r3, #8192 @ 0x2000 8012884: 687b ldr r3, [r7, #4] 8012886: 6c1a ldr r2, [r3, #64] @ 0x40 8012888: 687b ldr r3, [r7, #4] 801288a: 681b ldr r3, [r3, #0] 801288c: 430a orrs r2, r1 801288e: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 8012890: 687b ldr r3, [r7, #4] 8012892: 6a9b ldr r3, [r3, #40] @ 0x28 8012894: f003 0340 and.w r3, r3, #64 @ 0x40 8012898: 2b00 cmp r3, #0 801289a: d01a beq.n 80128d2 { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 801289c: 687b ldr r3, [r7, #4] 801289e: 681b ldr r3, [r3, #0] 80128a0: 685b ldr r3, [r3, #4] 80128a2: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 80128a6: 687b ldr r3, [r7, #4] 80128a8: 6c5a ldr r2, [r3, #68] @ 0x44 80128aa: 687b ldr r3, [r7, #4] 80128ac: 681b ldr r3, [r3, #0] 80128ae: 430a orrs r2, r1 80128b0: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 80128b2: 687b ldr r3, [r7, #4] 80128b4: 6c5b ldr r3, [r3, #68] @ 0x44 80128b6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80128ba: d10a bne.n 80128d2 { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 80128bc: 687b ldr r3, [r7, #4] 80128be: 681b ldr r3, [r3, #0] 80128c0: 685b ldr r3, [r3, #4] 80128c2: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 80128c6: 687b ldr r3, [r7, #4] 80128c8: 6c9a ldr r2, [r3, #72] @ 0x48 80128ca: 687b ldr r3, [r7, #4] 80128cc: 681b ldr r3, [r3, #0] 80128ce: 430a orrs r2, r1 80128d0: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 80128d2: 687b ldr r3, [r7, #4] 80128d4: 6a9b ldr r3, [r3, #40] @ 0x28 80128d6: f003 0380 and.w r3, r3, #128 @ 0x80 80128da: 2b00 cmp r3, #0 80128dc: d00a beq.n 80128f4 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 80128de: 687b ldr r3, [r7, #4] 80128e0: 681b ldr r3, [r3, #0] 80128e2: 685b ldr r3, [r3, #4] 80128e4: f423 2100 bic.w r1, r3, #524288 @ 0x80000 80128e8: 687b ldr r3, [r7, #4] 80128ea: 6cda ldr r2, [r3, #76] @ 0x4c 80128ec: 687b ldr r3, [r7, #4] 80128ee: 681b ldr r3, [r3, #0] 80128f0: 430a orrs r2, r1 80128f2: 605a str r2, [r3, #4] } } 80128f4: bf00 nop 80128f6: 370c adds r7, #12 80128f8: 46bd mov sp, r7 80128fa: f85d 7b04 ldr.w r7, [sp], #4 80128fe: 4770 bx lr 08012900 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 8012900: b580 push {r7, lr} 8012902: b098 sub sp, #96 @ 0x60 8012904: af02 add r7, sp, #8 8012906: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012908: 687b ldr r3, [r7, #4] 801290a: 2200 movs r2, #0 801290c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8012910: f7f3 fa74 bl 8005dfc 8012914: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 8012916: 687b ldr r3, [r7, #4] 8012918: 681b ldr r3, [r3, #0] 801291a: 681b ldr r3, [r3, #0] 801291c: f003 0308 and.w r3, r3, #8 8012920: 2b08 cmp r3, #8 8012922: d12f bne.n 8012984 { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8012924: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8012928: 9300 str r3, [sp, #0] 801292a: 6d7b ldr r3, [r7, #84] @ 0x54 801292c: 2200 movs r2, #0 801292e: f44f 1100 mov.w r1, #2097152 @ 0x200000 8012932: 6878 ldr r0, [r7, #4] 8012934: f000 f88e bl 8012a54 8012938: 4603 mov r3, r0 801293a: 2b00 cmp r3, #0 801293c: d022 beq.n 8012984 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 801293e: 687b ldr r3, [r7, #4] 8012940: 681b ldr r3, [r3, #0] 8012942: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012944: 6bbb ldr r3, [r7, #56] @ 0x38 8012946: e853 3f00 ldrex r3, [r3] 801294a: 637b str r3, [r7, #52] @ 0x34 return(result); 801294c: 6b7b ldr r3, [r7, #52] @ 0x34 801294e: f023 0380 bic.w r3, r3, #128 @ 0x80 8012952: 653b str r3, [r7, #80] @ 0x50 8012954: 687b ldr r3, [r7, #4] 8012956: 681b ldr r3, [r3, #0] 8012958: 461a mov r2, r3 801295a: 6d3b ldr r3, [r7, #80] @ 0x50 801295c: 647b str r3, [r7, #68] @ 0x44 801295e: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012960: 6c39 ldr r1, [r7, #64] @ 0x40 8012962: 6c7a ldr r2, [r7, #68] @ 0x44 8012964: e841 2300 strex r3, r2, [r1] 8012968: 63fb str r3, [r7, #60] @ 0x3c return(result); 801296a: 6bfb ldr r3, [r7, #60] @ 0x3c 801296c: 2b00 cmp r3, #0 801296e: d1e6 bne.n 801293e huart->gState = HAL_UART_STATE_READY; 8012970: 687b ldr r3, [r7, #4] 8012972: 2220 movs r2, #32 8012974: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); 8012978: 687b ldr r3, [r7, #4] 801297a: 2200 movs r2, #0 801297c: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8012980: 2303 movs r3, #3 8012982: e063 b.n 8012a4c } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 8012984: 687b ldr r3, [r7, #4] 8012986: 681b ldr r3, [r3, #0] 8012988: 681b ldr r3, [r3, #0] 801298a: f003 0304 and.w r3, r3, #4 801298e: 2b04 cmp r3, #4 8012990: d149 bne.n 8012a26 { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8012992: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8012996: 9300 str r3, [sp, #0] 8012998: 6d7b ldr r3, [r7, #84] @ 0x54 801299a: 2200 movs r2, #0 801299c: f44f 0180 mov.w r1, #4194304 @ 0x400000 80129a0: 6878 ldr r0, [r7, #4] 80129a2: f000 f857 bl 8012a54 80129a6: 4603 mov r3, r0 80129a8: 2b00 cmp r3, #0 80129aa: d03c beq.n 8012a26 { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 80129ac: 687b ldr r3, [r7, #4] 80129ae: 681b ldr r3, [r3, #0] 80129b0: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80129b2: 6a7b ldr r3, [r7, #36] @ 0x24 80129b4: e853 3f00 ldrex r3, [r3] 80129b8: 623b str r3, [r7, #32] return(result); 80129ba: 6a3b ldr r3, [r7, #32] 80129bc: f423 7390 bic.w r3, r3, #288 @ 0x120 80129c0: 64fb str r3, [r7, #76] @ 0x4c 80129c2: 687b ldr r3, [r7, #4] 80129c4: 681b ldr r3, [r3, #0] 80129c6: 461a mov r2, r3 80129c8: 6cfb ldr r3, [r7, #76] @ 0x4c 80129ca: 633b str r3, [r7, #48] @ 0x30 80129cc: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80129ce: 6af9 ldr r1, [r7, #44] @ 0x2c 80129d0: 6b3a ldr r2, [r7, #48] @ 0x30 80129d2: e841 2300 strex r3, r2, [r1] 80129d6: 62bb str r3, [r7, #40] @ 0x28 return(result); 80129d8: 6abb ldr r3, [r7, #40] @ 0x28 80129da: 2b00 cmp r3, #0 80129dc: d1e6 bne.n 80129ac ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80129de: 687b ldr r3, [r7, #4] 80129e0: 681b ldr r3, [r3, #0] 80129e2: 3308 adds r3, #8 80129e4: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80129e6: 693b ldr r3, [r7, #16] 80129e8: e853 3f00 ldrex r3, [r3] 80129ec: 60fb str r3, [r7, #12] return(result); 80129ee: 68fb ldr r3, [r7, #12] 80129f0: f023 0301 bic.w r3, r3, #1 80129f4: 64bb str r3, [r7, #72] @ 0x48 80129f6: 687b ldr r3, [r7, #4] 80129f8: 681b ldr r3, [r3, #0] 80129fa: 3308 adds r3, #8 80129fc: 6cba ldr r2, [r7, #72] @ 0x48 80129fe: 61fa str r2, [r7, #28] 8012a00: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012a02: 69b9 ldr r1, [r7, #24] 8012a04: 69fa ldr r2, [r7, #28] 8012a06: e841 2300 strex r3, r2, [r1] 8012a0a: 617b str r3, [r7, #20] return(result); 8012a0c: 697b ldr r3, [r7, #20] 8012a0e: 2b00 cmp r3, #0 8012a10: d1e5 bne.n 80129de huart->RxState = HAL_UART_STATE_READY; 8012a12: 687b ldr r3, [r7, #4] 8012a14: 2220 movs r2, #32 8012a16: f8c3 208c str.w r2, [r3, #140] @ 0x8c __HAL_UNLOCK(huart); 8012a1a: 687b ldr r3, [r7, #4] 8012a1c: 2200 movs r2, #0 8012a1e: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8012a22: 2303 movs r3, #3 8012a24: e012 b.n 8012a4c } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 8012a26: 687b ldr r3, [r7, #4] 8012a28: 2220 movs r2, #32 8012a2a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 huart->RxState = HAL_UART_STATE_READY; 8012a2e: 687b ldr r3, [r7, #4] 8012a30: 2220 movs r2, #32 8012a32: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012a36: 687b ldr r3, [r7, #4] 8012a38: 2200 movs r2, #0 8012a3a: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8012a3c: 687b ldr r3, [r7, #4] 8012a3e: 2200 movs r2, #0 8012a40: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 8012a42: 687b ldr r3, [r7, #4] 8012a44: 2200 movs r2, #0 8012a46: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8012a4a: 2300 movs r3, #0 } 8012a4c: 4618 mov r0, r3 8012a4e: 3758 adds r7, #88 @ 0x58 8012a50: 46bd mov sp, r7 8012a52: bd80 pop {r7, pc} 08012a54 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8012a54: b580 push {r7, lr} 8012a56: b084 sub sp, #16 8012a58: af00 add r7, sp, #0 8012a5a: 60f8 str r0, [r7, #12] 8012a5c: 60b9 str r1, [r7, #8] 8012a5e: 603b str r3, [r7, #0] 8012a60: 4613 mov r3, r2 8012a62: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8012a64: e04f b.n 8012b06 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8012a66: 69bb ldr r3, [r7, #24] 8012a68: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8012a6c: d04b beq.n 8012b06 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8012a6e: f7f3 f9c5 bl 8005dfc 8012a72: 4602 mov r2, r0 8012a74: 683b ldr r3, [r7, #0] 8012a76: 1ad3 subs r3, r2, r3 8012a78: 69ba ldr r2, [r7, #24] 8012a7a: 429a cmp r2, r3 8012a7c: d302 bcc.n 8012a84 8012a7e: 69bb ldr r3, [r7, #24] 8012a80: 2b00 cmp r3, #0 8012a82: d101 bne.n 8012a88 { return HAL_TIMEOUT; 8012a84: 2303 movs r3, #3 8012a86: e04e b.n 8012b26 } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 8012a88: 68fb ldr r3, [r7, #12] 8012a8a: 681b ldr r3, [r3, #0] 8012a8c: 681b ldr r3, [r3, #0] 8012a8e: f003 0304 and.w r3, r3, #4 8012a92: 2b00 cmp r3, #0 8012a94: d037 beq.n 8012b06 8012a96: 68bb ldr r3, [r7, #8] 8012a98: 2b80 cmp r3, #128 @ 0x80 8012a9a: d034 beq.n 8012b06 8012a9c: 68bb ldr r3, [r7, #8] 8012a9e: 2b40 cmp r3, #64 @ 0x40 8012aa0: d031 beq.n 8012b06 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8012aa2: 68fb ldr r3, [r7, #12] 8012aa4: 681b ldr r3, [r3, #0] 8012aa6: 69db ldr r3, [r3, #28] 8012aa8: f003 0308 and.w r3, r3, #8 8012aac: 2b08 cmp r3, #8 8012aae: d110 bne.n 8012ad2 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8012ab0: 68fb ldr r3, [r7, #12] 8012ab2: 681b ldr r3, [r3, #0] 8012ab4: 2208 movs r2, #8 8012ab6: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8012ab8: 68f8 ldr r0, [r7, #12] 8012aba: f000 f95b bl 8012d74 huart->ErrorCode = HAL_UART_ERROR_ORE; 8012abe: 68fb ldr r3, [r7, #12] 8012ac0: 2208 movs r2, #8 8012ac2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8012ac6: 68fb ldr r3, [r7, #12] 8012ac8: 2200 movs r2, #0 8012aca: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_ERROR; 8012ace: 2301 movs r3, #1 8012ad0: e029 b.n 8012b26 } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8012ad2: 68fb ldr r3, [r7, #12] 8012ad4: 681b ldr r3, [r3, #0] 8012ad6: 69db ldr r3, [r3, #28] 8012ad8: f403 6300 and.w r3, r3, #2048 @ 0x800 8012adc: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8012ae0: d111 bne.n 8012b06 { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8012ae2: 68fb ldr r3, [r7, #12] 8012ae4: 681b ldr r3, [r3, #0] 8012ae6: f44f 6200 mov.w r2, #2048 @ 0x800 8012aea: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8012aec: 68f8 ldr r0, [r7, #12] 8012aee: f000 f941 bl 8012d74 huart->ErrorCode = HAL_UART_ERROR_RTO; 8012af2: 68fb ldr r3, [r7, #12] 8012af4: 2220 movs r2, #32 8012af6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8012afa: 68fb ldr r3, [r7, #12] 8012afc: 2200 movs r2, #0 8012afe: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_TIMEOUT; 8012b02: 2303 movs r3, #3 8012b04: e00f b.n 8012b26 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8012b06: 68fb ldr r3, [r7, #12] 8012b08: 681b ldr r3, [r3, #0] 8012b0a: 69da ldr r2, [r3, #28] 8012b0c: 68bb ldr r3, [r7, #8] 8012b0e: 4013 ands r3, r2 8012b10: 68ba ldr r2, [r7, #8] 8012b12: 429a cmp r2, r3 8012b14: bf0c ite eq 8012b16: 2301 moveq r3, #1 8012b18: 2300 movne r3, #0 8012b1a: b2db uxtb r3, r3 8012b1c: 461a mov r2, r3 8012b1e: 79fb ldrb r3, [r7, #7] 8012b20: 429a cmp r2, r3 8012b22: d0a0 beq.n 8012a66 } } } } return HAL_OK; 8012b24: 2300 movs r3, #0 } 8012b26: 4618 mov r0, r3 8012b28: 3710 adds r7, #16 8012b2a: 46bd mov sp, r7 8012b2c: bd80 pop {r7, pc} ... 08012b30 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8012b30: b480 push {r7} 8012b32: b0a3 sub sp, #140 @ 0x8c 8012b34: af00 add r7, sp, #0 8012b36: 60f8 str r0, [r7, #12] 8012b38: 60b9 str r1, [r7, #8] 8012b3a: 4613 mov r3, r2 8012b3c: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 8012b3e: 68fb ldr r3, [r7, #12] 8012b40: 68ba ldr r2, [r7, #8] 8012b42: 659a str r2, [r3, #88] @ 0x58 huart->RxXferSize = Size; 8012b44: 68fb ldr r3, [r7, #12] 8012b46: 88fa ldrh r2, [r7, #6] 8012b48: f8a3 205c strh.w r2, [r3, #92] @ 0x5c huart->RxXferCount = Size; 8012b4c: 68fb ldr r3, [r7, #12] 8012b4e: 88fa ldrh r2, [r7, #6] 8012b50: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->RxISR = NULL; 8012b54: 68fb ldr r3, [r7, #12] 8012b56: 2200 movs r2, #0 8012b58: 675a str r2, [r3, #116] @ 0x74 /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); 8012b5a: 68fb ldr r3, [r7, #12] 8012b5c: 689b ldr r3, [r3, #8] 8012b5e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012b62: d10e bne.n 8012b82 8012b64: 68fb ldr r3, [r7, #12] 8012b66: 691b ldr r3, [r3, #16] 8012b68: 2b00 cmp r3, #0 8012b6a: d105 bne.n 8012b78 8012b6c: 68fb ldr r3, [r7, #12] 8012b6e: f240 12ff movw r2, #511 @ 0x1ff 8012b72: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012b76: e02d b.n 8012bd4 8012b78: 68fb ldr r3, [r7, #12] 8012b7a: 22ff movs r2, #255 @ 0xff 8012b7c: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012b80: e028 b.n 8012bd4 8012b82: 68fb ldr r3, [r7, #12] 8012b84: 689b ldr r3, [r3, #8] 8012b86: 2b00 cmp r3, #0 8012b88: d10d bne.n 8012ba6 8012b8a: 68fb ldr r3, [r7, #12] 8012b8c: 691b ldr r3, [r3, #16] 8012b8e: 2b00 cmp r3, #0 8012b90: d104 bne.n 8012b9c 8012b92: 68fb ldr r3, [r7, #12] 8012b94: 22ff movs r2, #255 @ 0xff 8012b96: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012b9a: e01b b.n 8012bd4 8012b9c: 68fb ldr r3, [r7, #12] 8012b9e: 227f movs r2, #127 @ 0x7f 8012ba0: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012ba4: e016 b.n 8012bd4 8012ba6: 68fb ldr r3, [r7, #12] 8012ba8: 689b ldr r3, [r3, #8] 8012baa: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8012bae: d10d bne.n 8012bcc 8012bb0: 68fb ldr r3, [r7, #12] 8012bb2: 691b ldr r3, [r3, #16] 8012bb4: 2b00 cmp r3, #0 8012bb6: d104 bne.n 8012bc2 8012bb8: 68fb ldr r3, [r7, #12] 8012bba: 227f movs r2, #127 @ 0x7f 8012bbc: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012bc0: e008 b.n 8012bd4 8012bc2: 68fb ldr r3, [r7, #12] 8012bc4: 223f movs r2, #63 @ 0x3f 8012bc6: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012bca: e003 b.n 8012bd4 8012bcc: 68fb ldr r3, [r7, #12] 8012bce: 2200 movs r2, #0 8012bd0: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 huart->ErrorCode = HAL_UART_ERROR_NONE; 8012bd4: 68fb ldr r3, [r7, #12] 8012bd6: 2200 movs r2, #0 8012bd8: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->RxState = HAL_UART_STATE_BUSY_RX; 8012bdc: 68fb ldr r3, [r7, #12] 8012bde: 2222 movs r2, #34 @ 0x22 8012be0: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012be4: 68fb ldr r3, [r7, #12] 8012be6: 681b ldr r3, [r3, #0] 8012be8: 3308 adds r3, #8 8012bea: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012bec: 6e7b ldr r3, [r7, #100] @ 0x64 8012bee: e853 3f00 ldrex r3, [r3] 8012bf2: 663b str r3, [r7, #96] @ 0x60 return(result); 8012bf4: 6e3b ldr r3, [r7, #96] @ 0x60 8012bf6: f043 0301 orr.w r3, r3, #1 8012bfa: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8012bfe: 68fb ldr r3, [r7, #12] 8012c00: 681b ldr r3, [r3, #0] 8012c02: 3308 adds r3, #8 8012c04: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 8012c08: 673a str r2, [r7, #112] @ 0x70 8012c0a: 66fb str r3, [r7, #108] @ 0x6c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012c0c: 6ef9 ldr r1, [r7, #108] @ 0x6c 8012c0e: 6f3a ldr r2, [r7, #112] @ 0x70 8012c10: e841 2300 strex r3, r2, [r1] 8012c14: 66bb str r3, [r7, #104] @ 0x68 return(result); 8012c16: 6ebb ldr r3, [r7, #104] @ 0x68 8012c18: 2b00 cmp r3, #0 8012c1a: d1e3 bne.n 8012be4 /* Configure Rx interrupt processing */ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) 8012c1c: 68fb ldr r3, [r7, #12] 8012c1e: 6e5b ldr r3, [r3, #100] @ 0x64 8012c20: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8012c24: d14f bne.n 8012cc6 8012c26: 68fb ldr r3, [r7, #12] 8012c28: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8012c2c: 88fa ldrh r2, [r7, #6] 8012c2e: 429a cmp r2, r3 8012c30: d349 bcc.n 8012cc6 { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012c32: 68fb ldr r3, [r7, #12] 8012c34: 689b ldr r3, [r3, #8] 8012c36: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012c3a: d107 bne.n 8012c4c 8012c3c: 68fb ldr r3, [r7, #12] 8012c3e: 691b ldr r3, [r3, #16] 8012c40: 2b00 cmp r3, #0 8012c42: d103 bne.n 8012c4c { huart->RxISR = UART_RxISR_16BIT_FIFOEN; 8012c44: 68fb ldr r3, [r7, #12] 8012c46: 4a47 ldr r2, [pc, #284] @ (8012d64 ) 8012c48: 675a str r2, [r3, #116] @ 0x74 8012c4a: e002 b.n 8012c52 } else { huart->RxISR = UART_RxISR_8BIT_FIFOEN; 8012c4c: 68fb ldr r3, [r7, #12] 8012c4e: 4a46 ldr r2, [pc, #280] @ (8012d68 ) 8012c50: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8012c52: 68fb ldr r3, [r7, #12] 8012c54: 691b ldr r3, [r3, #16] 8012c56: 2b00 cmp r3, #0 8012c58: d01a beq.n 8012c90 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8012c5a: 68fb ldr r3, [r7, #12] 8012c5c: 681b ldr r3, [r3, #0] 8012c5e: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012c60: 6d3b ldr r3, [r7, #80] @ 0x50 8012c62: e853 3f00 ldrex r3, [r3] 8012c66: 64fb str r3, [r7, #76] @ 0x4c return(result); 8012c68: 6cfb ldr r3, [r7, #76] @ 0x4c 8012c6a: f443 7380 orr.w r3, r3, #256 @ 0x100 8012c6e: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8012c72: 68fb ldr r3, [r7, #12] 8012c74: 681b ldr r3, [r3, #0] 8012c76: 461a mov r2, r3 8012c78: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8012c7c: 65fb str r3, [r7, #92] @ 0x5c 8012c7e: 65ba str r2, [r7, #88] @ 0x58 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012c80: 6db9 ldr r1, [r7, #88] @ 0x58 8012c82: 6dfa ldr r2, [r7, #92] @ 0x5c 8012c84: e841 2300 strex r3, r2, [r1] 8012c88: 657b str r3, [r7, #84] @ 0x54 return(result); 8012c8a: 6d7b ldr r3, [r7, #84] @ 0x54 8012c8c: 2b00 cmp r3, #0 8012c8e: d1e4 bne.n 8012c5a } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8012c90: 68fb ldr r3, [r7, #12] 8012c92: 681b ldr r3, [r3, #0] 8012c94: 3308 adds r3, #8 8012c96: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012c98: 6bfb ldr r3, [r7, #60] @ 0x3c 8012c9a: e853 3f00 ldrex r3, [r3] 8012c9e: 63bb str r3, [r7, #56] @ 0x38 return(result); 8012ca0: 6bbb ldr r3, [r7, #56] @ 0x38 8012ca2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8012ca6: 67fb str r3, [r7, #124] @ 0x7c 8012ca8: 68fb ldr r3, [r7, #12] 8012caa: 681b ldr r3, [r3, #0] 8012cac: 3308 adds r3, #8 8012cae: 6ffa ldr r2, [r7, #124] @ 0x7c 8012cb0: 64ba str r2, [r7, #72] @ 0x48 8012cb2: 647b str r3, [r7, #68] @ 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012cb4: 6c79 ldr r1, [r7, #68] @ 0x44 8012cb6: 6cba ldr r2, [r7, #72] @ 0x48 8012cb8: e841 2300 strex r3, r2, [r1] 8012cbc: 643b str r3, [r7, #64] @ 0x40 return(result); 8012cbe: 6c3b ldr r3, [r7, #64] @ 0x40 8012cc0: 2b00 cmp r3, #0 8012cc2: d1e5 bne.n 8012c90 8012cc4: e046 b.n 8012d54 } else { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012cc6: 68fb ldr r3, [r7, #12] 8012cc8: 689b ldr r3, [r3, #8] 8012cca: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012cce: d107 bne.n 8012ce0 8012cd0: 68fb ldr r3, [r7, #12] 8012cd2: 691b ldr r3, [r3, #16] 8012cd4: 2b00 cmp r3, #0 8012cd6: d103 bne.n 8012ce0 { huart->RxISR = UART_RxISR_16BIT; 8012cd8: 68fb ldr r3, [r7, #12] 8012cda: 4a24 ldr r2, [pc, #144] @ (8012d6c ) 8012cdc: 675a str r2, [r3, #116] @ 0x74 8012cde: e002 b.n 8012ce6 } else { huart->RxISR = UART_RxISR_8BIT; 8012ce0: 68fb ldr r3, [r7, #12] 8012ce2: 4a23 ldr r2, [pc, #140] @ (8012d70 ) 8012ce4: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8012ce6: 68fb ldr r3, [r7, #12] 8012ce8: 691b ldr r3, [r3, #16] 8012cea: 2b00 cmp r3, #0 8012cec: d019 beq.n 8012d22 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); 8012cee: 68fb ldr r3, [r7, #12] 8012cf0: 681b ldr r3, [r3, #0] 8012cf2: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012cf4: 6abb ldr r3, [r7, #40] @ 0x28 8012cf6: e853 3f00 ldrex r3, [r3] 8012cfa: 627b str r3, [r7, #36] @ 0x24 return(result); 8012cfc: 6a7b ldr r3, [r7, #36] @ 0x24 8012cfe: f443 7390 orr.w r3, r3, #288 @ 0x120 8012d02: 677b str r3, [r7, #116] @ 0x74 8012d04: 68fb ldr r3, [r7, #12] 8012d06: 681b ldr r3, [r3, #0] 8012d08: 461a mov r2, r3 8012d0a: 6f7b ldr r3, [r7, #116] @ 0x74 8012d0c: 637b str r3, [r7, #52] @ 0x34 8012d0e: 633a str r2, [r7, #48] @ 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d10: 6b39 ldr r1, [r7, #48] @ 0x30 8012d12: 6b7a ldr r2, [r7, #52] @ 0x34 8012d14: e841 2300 strex r3, r2, [r1] 8012d18: 62fb str r3, [r7, #44] @ 0x2c return(result); 8012d1a: 6afb ldr r3, [r7, #44] @ 0x2c 8012d1c: 2b00 cmp r3, #0 8012d1e: d1e6 bne.n 8012cee 8012d20: e018 b.n 8012d54 } else { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8012d22: 68fb ldr r3, [r7, #12] 8012d24: 681b ldr r3, [r3, #0] 8012d26: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012d28: 697b ldr r3, [r7, #20] 8012d2a: e853 3f00 ldrex r3, [r3] 8012d2e: 613b str r3, [r7, #16] return(result); 8012d30: 693b ldr r3, [r7, #16] 8012d32: f043 0320 orr.w r3, r3, #32 8012d36: 67bb str r3, [r7, #120] @ 0x78 8012d38: 68fb ldr r3, [r7, #12] 8012d3a: 681b ldr r3, [r3, #0] 8012d3c: 461a mov r2, r3 8012d3e: 6fbb ldr r3, [r7, #120] @ 0x78 8012d40: 623b str r3, [r7, #32] 8012d42: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d44: 69f9 ldr r1, [r7, #28] 8012d46: 6a3a ldr r2, [r7, #32] 8012d48: e841 2300 strex r3, r2, [r1] 8012d4c: 61bb str r3, [r7, #24] return(result); 8012d4e: 69bb ldr r3, [r7, #24] 8012d50: 2b00 cmp r3, #0 8012d52: d1e6 bne.n 8012d22 } } return HAL_OK; 8012d54: 2300 movs r3, #0 } 8012d56: 4618 mov r0, r3 8012d58: 378c adds r7, #140 @ 0x8c 8012d5a: 46bd mov sp, r7 8012d5c: f85d 7b04 ldr.w r7, [sp], #4 8012d60: 4770 bx lr 8012d62: bf00 nop 8012d64: 080138d9 .word 0x080138d9 8012d68: 08013579 .word 0x08013579 8012d6c: 080133c1 .word 0x080133c1 8012d70: 08013209 .word 0x08013209 08012d74 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8012d74: b480 push {r7} 8012d76: b095 sub sp, #84 @ 0x54 8012d78: af00 add r7, sp, #0 8012d7a: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8012d7c: 687b ldr r3, [r7, #4] 8012d7e: 681b ldr r3, [r3, #0] 8012d80: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012d82: 6b7b ldr r3, [r7, #52] @ 0x34 8012d84: e853 3f00 ldrex r3, [r3] 8012d88: 633b str r3, [r7, #48] @ 0x30 return(result); 8012d8a: 6b3b ldr r3, [r7, #48] @ 0x30 8012d8c: f423 7390 bic.w r3, r3, #288 @ 0x120 8012d90: 64fb str r3, [r7, #76] @ 0x4c 8012d92: 687b ldr r3, [r7, #4] 8012d94: 681b ldr r3, [r3, #0] 8012d96: 461a mov r2, r3 8012d98: 6cfb ldr r3, [r7, #76] @ 0x4c 8012d9a: 643b str r3, [r7, #64] @ 0x40 8012d9c: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d9e: 6bf9 ldr r1, [r7, #60] @ 0x3c 8012da0: 6c3a ldr r2, [r7, #64] @ 0x40 8012da2: e841 2300 strex r3, r2, [r1] 8012da6: 63bb str r3, [r7, #56] @ 0x38 return(result); 8012da8: 6bbb ldr r3, [r7, #56] @ 0x38 8012daa: 2b00 cmp r3, #0 8012dac: d1e6 bne.n 8012d7c ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8012dae: 687b ldr r3, [r7, #4] 8012db0: 681b ldr r3, [r3, #0] 8012db2: 3308 adds r3, #8 8012db4: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012db6: 6a3b ldr r3, [r7, #32] 8012db8: e853 3f00 ldrex r3, [r3] 8012dbc: 61fb str r3, [r7, #28] return(result); 8012dbe: 69fa ldr r2, [r7, #28] 8012dc0: 4b1e ldr r3, [pc, #120] @ (8012e3c ) 8012dc2: 4013 ands r3, r2 8012dc4: 64bb str r3, [r7, #72] @ 0x48 8012dc6: 687b ldr r3, [r7, #4] 8012dc8: 681b ldr r3, [r3, #0] 8012dca: 3308 adds r3, #8 8012dcc: 6cba ldr r2, [r7, #72] @ 0x48 8012dce: 62fa str r2, [r7, #44] @ 0x2c 8012dd0: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012dd2: 6ab9 ldr r1, [r7, #40] @ 0x28 8012dd4: 6afa ldr r2, [r7, #44] @ 0x2c 8012dd6: e841 2300 strex r3, r2, [r1] 8012dda: 627b str r3, [r7, #36] @ 0x24 return(result); 8012ddc: 6a7b ldr r3, [r7, #36] @ 0x24 8012dde: 2b00 cmp r3, #0 8012de0: d1e5 bne.n 8012dae /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012de2: 687b ldr r3, [r7, #4] 8012de4: 6edb ldr r3, [r3, #108] @ 0x6c 8012de6: 2b01 cmp r3, #1 8012de8: d118 bne.n 8012e1c { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012dea: 687b ldr r3, [r7, #4] 8012dec: 681b ldr r3, [r3, #0] 8012dee: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012df0: 68fb ldr r3, [r7, #12] 8012df2: e853 3f00 ldrex r3, [r3] 8012df6: 60bb str r3, [r7, #8] return(result); 8012df8: 68bb ldr r3, [r7, #8] 8012dfa: f023 0310 bic.w r3, r3, #16 8012dfe: 647b str r3, [r7, #68] @ 0x44 8012e00: 687b ldr r3, [r7, #4] 8012e02: 681b ldr r3, [r3, #0] 8012e04: 461a mov r2, r3 8012e06: 6c7b ldr r3, [r7, #68] @ 0x44 8012e08: 61bb str r3, [r7, #24] 8012e0a: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012e0c: 6979 ldr r1, [r7, #20] 8012e0e: 69ba ldr r2, [r7, #24] 8012e10: e841 2300 strex r3, r2, [r1] 8012e14: 613b str r3, [r7, #16] return(result); 8012e16: 693b ldr r3, [r7, #16] 8012e18: 2b00 cmp r3, #0 8012e1a: d1e6 bne.n 8012dea } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012e1c: 687b ldr r3, [r7, #4] 8012e1e: 2220 movs r2, #32 8012e20: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012e24: 687b ldr r3, [r7, #4] 8012e26: 2200 movs r2, #0 8012e28: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 8012e2a: 687b ldr r3, [r7, #4] 8012e2c: 2200 movs r2, #0 8012e2e: 675a str r2, [r3, #116] @ 0x74 } 8012e30: bf00 nop 8012e32: 3754 adds r7, #84 @ 0x54 8012e34: 46bd mov sp, r7 8012e36: f85d 7b04 ldr.w r7, [sp], #4 8012e3a: 4770 bx lr 8012e3c: effffffe .word 0xeffffffe 08012e40 : * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8012e40: b580 push {r7, lr} 8012e42: b084 sub sp, #16 8012e44: af00 add r7, sp, #0 8012e46: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8012e48: 687b ldr r3, [r7, #4] 8012e4a: 6b9b ldr r3, [r3, #56] @ 0x38 8012e4c: 60fb str r3, [r7, #12] huart->RxXferCount = 0U; 8012e4e: 68fb ldr r3, [r7, #12] 8012e50: 2200 movs r2, #0 8012e52: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->TxXferCount = 0U; 8012e56: 68fb ldr r3, [r7, #12] 8012e58: 2200 movs r2, #0 8012e5a: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8012e5e: 68f8 ldr r0, [r7, #12] 8012e60: f7fe ff3a bl 8011cd8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8012e64: bf00 nop 8012e66: 3710 adds r7, #16 8012e68: 46bd mov sp, r7 8012e6a: bd80 pop {r7, pc} 08012e6c : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) { 8012e6c: b480 push {r7} 8012e6e: b08f sub sp, #60 @ 0x3c 8012e70: af00 add r7, sp, #0 8012e72: 6078 str r0, [r7, #4] /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8012e74: 687b ldr r3, [r7, #4] 8012e76: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8012e7a: 2b21 cmp r3, #33 @ 0x21 8012e7c: d14c bne.n 8012f18 { if (huart->TxXferCount == 0U) 8012e7e: 687b ldr r3, [r7, #4] 8012e80: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012e84: b29b uxth r3, r3 8012e86: 2b00 cmp r3, #0 8012e88: d132 bne.n 8012ef0 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8012e8a: 687b ldr r3, [r7, #4] 8012e8c: 681b ldr r3, [r3, #0] 8012e8e: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012e90: 6a3b ldr r3, [r7, #32] 8012e92: e853 3f00 ldrex r3, [r3] 8012e96: 61fb str r3, [r7, #28] return(result); 8012e98: 69fb ldr r3, [r7, #28] 8012e9a: f023 0380 bic.w r3, r3, #128 @ 0x80 8012e9e: 637b str r3, [r7, #52] @ 0x34 8012ea0: 687b ldr r3, [r7, #4] 8012ea2: 681b ldr r3, [r3, #0] 8012ea4: 461a mov r2, r3 8012ea6: 6b7b ldr r3, [r7, #52] @ 0x34 8012ea8: 62fb str r3, [r7, #44] @ 0x2c 8012eaa: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012eac: 6ab9 ldr r1, [r7, #40] @ 0x28 8012eae: 6afa ldr r2, [r7, #44] @ 0x2c 8012eb0: e841 2300 strex r3, r2, [r1] 8012eb4: 627b str r3, [r7, #36] @ 0x24 return(result); 8012eb6: 6a7b ldr r3, [r7, #36] @ 0x24 8012eb8: 2b00 cmp r3, #0 8012eba: d1e6 bne.n 8012e8a /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8012ebc: 687b ldr r3, [r7, #4] 8012ebe: 681b ldr r3, [r3, #0] 8012ec0: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012ec2: 68fb ldr r3, [r7, #12] 8012ec4: e853 3f00 ldrex r3, [r3] 8012ec8: 60bb str r3, [r7, #8] return(result); 8012eca: 68bb ldr r3, [r7, #8] 8012ecc: f043 0340 orr.w r3, r3, #64 @ 0x40 8012ed0: 633b str r3, [r7, #48] @ 0x30 8012ed2: 687b ldr r3, [r7, #4] 8012ed4: 681b ldr r3, [r3, #0] 8012ed6: 461a mov r2, r3 8012ed8: 6b3b ldr r3, [r7, #48] @ 0x30 8012eda: 61bb str r3, [r7, #24] 8012edc: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012ede: 6979 ldr r1, [r7, #20] 8012ee0: 69ba ldr r2, [r7, #24] 8012ee2: e841 2300 strex r3, r2, [r1] 8012ee6: 613b str r3, [r7, #16] return(result); 8012ee8: 693b ldr r3, [r7, #16] 8012eea: 2b00 cmp r3, #0 8012eec: d1e6 bne.n 8012ebc huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); huart->pTxBuffPtr++; huart->TxXferCount--; } } } 8012eee: e013 b.n 8012f18 huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 8012ef0: 687b ldr r3, [r7, #4] 8012ef2: 6d1b ldr r3, [r3, #80] @ 0x50 8012ef4: 781a ldrb r2, [r3, #0] 8012ef6: 687b ldr r3, [r7, #4] 8012ef8: 681b ldr r3, [r3, #0] 8012efa: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 8012efc: 687b ldr r3, [r7, #4] 8012efe: 6d1b ldr r3, [r3, #80] @ 0x50 8012f00: 1c5a adds r2, r3, #1 8012f02: 687b ldr r3, [r7, #4] 8012f04: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 8012f06: 687b ldr r3, [r7, #4] 8012f08: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012f0c: b29b uxth r3, r3 8012f0e: 3b01 subs r3, #1 8012f10: b29a uxth r2, r3 8012f12: 687b ldr r3, [r7, #4] 8012f14: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 8012f18: bf00 nop 8012f1a: 373c adds r7, #60 @ 0x3c 8012f1c: 46bd mov sp, r7 8012f1e: f85d 7b04 ldr.w r7, [sp], #4 8012f22: 4770 bx lr 08012f24 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { 8012f24: b480 push {r7} 8012f26: b091 sub sp, #68 @ 0x44 8012f28: af00 add r7, sp, #0 8012f2a: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8012f2c: 687b ldr r3, [r7, #4] 8012f2e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8012f32: 2b21 cmp r3, #33 @ 0x21 8012f34: d151 bne.n 8012fda { if (huart->TxXferCount == 0U) 8012f36: 687b ldr r3, [r7, #4] 8012f38: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012f3c: b29b uxth r3, r3 8012f3e: 2b00 cmp r3, #0 8012f40: d132 bne.n 8012fa8 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8012f42: 687b ldr r3, [r7, #4] 8012f44: 681b ldr r3, [r3, #0] 8012f46: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012f48: 6a7b ldr r3, [r7, #36] @ 0x24 8012f4a: e853 3f00 ldrex r3, [r3] 8012f4e: 623b str r3, [r7, #32] return(result); 8012f50: 6a3b ldr r3, [r7, #32] 8012f52: f023 0380 bic.w r3, r3, #128 @ 0x80 8012f56: 63bb str r3, [r7, #56] @ 0x38 8012f58: 687b ldr r3, [r7, #4] 8012f5a: 681b ldr r3, [r3, #0] 8012f5c: 461a mov r2, r3 8012f5e: 6bbb ldr r3, [r7, #56] @ 0x38 8012f60: 633b str r3, [r7, #48] @ 0x30 8012f62: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012f64: 6af9 ldr r1, [r7, #44] @ 0x2c 8012f66: 6b3a ldr r2, [r7, #48] @ 0x30 8012f68: e841 2300 strex r3, r2, [r1] 8012f6c: 62bb str r3, [r7, #40] @ 0x28 return(result); 8012f6e: 6abb ldr r3, [r7, #40] @ 0x28 8012f70: 2b00 cmp r3, #0 8012f72: d1e6 bne.n 8012f42 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8012f74: 687b ldr r3, [r7, #4] 8012f76: 681b ldr r3, [r3, #0] 8012f78: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012f7a: 693b ldr r3, [r7, #16] 8012f7c: e853 3f00 ldrex r3, [r3] 8012f80: 60fb str r3, [r7, #12] return(result); 8012f82: 68fb ldr r3, [r7, #12] 8012f84: f043 0340 orr.w r3, r3, #64 @ 0x40 8012f88: 637b str r3, [r7, #52] @ 0x34 8012f8a: 687b ldr r3, [r7, #4] 8012f8c: 681b ldr r3, [r3, #0] 8012f8e: 461a mov r2, r3 8012f90: 6b7b ldr r3, [r7, #52] @ 0x34 8012f92: 61fb str r3, [r7, #28] 8012f94: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012f96: 69b9 ldr r1, [r7, #24] 8012f98: 69fa ldr r2, [r7, #28] 8012f9a: e841 2300 strex r3, r2, [r1] 8012f9e: 617b str r3, [r7, #20] return(result); 8012fa0: 697b ldr r3, [r7, #20] 8012fa2: 2b00 cmp r3, #0 8012fa4: d1e6 bne.n 8012f74 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; } } } 8012fa6: e018 b.n 8012fda tmp = (const uint16_t *) huart->pTxBuffPtr; 8012fa8: 687b ldr r3, [r7, #4] 8012faa: 6d1b ldr r3, [r3, #80] @ 0x50 8012fac: 63fb str r3, [r7, #60] @ 0x3c huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 8012fae: 6bfb ldr r3, [r7, #60] @ 0x3c 8012fb0: 881b ldrh r3, [r3, #0] 8012fb2: 461a mov r2, r3 8012fb4: 687b ldr r3, [r7, #4] 8012fb6: 681b ldr r3, [r3, #0] 8012fb8: f3c2 0208 ubfx r2, r2, #0, #9 8012fbc: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 8012fbe: 687b ldr r3, [r7, #4] 8012fc0: 6d1b ldr r3, [r3, #80] @ 0x50 8012fc2: 1c9a adds r2, r3, #2 8012fc4: 687b ldr r3, [r7, #4] 8012fc6: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 8012fc8: 687b ldr r3, [r7, #4] 8012fca: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012fce: b29b uxth r3, r3 8012fd0: 3b01 subs r3, #1 8012fd2: b29a uxth r2, r3 8012fd4: 687b ldr r3, [r7, #4] 8012fd6: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 8012fda: bf00 nop 8012fdc: 3744 adds r7, #68 @ 0x44 8012fde: 46bd mov sp, r7 8012fe0: f85d 7b04 ldr.w r7, [sp], #4 8012fe4: 4770 bx lr 08012fe6 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 8012fe6: b480 push {r7} 8012fe8: b091 sub sp, #68 @ 0x44 8012fea: af00 add r7, sp, #0 8012fec: 6078 str r0, [r7, #4] uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8012fee: 687b ldr r3, [r7, #4] 8012ff0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8012ff4: 2b21 cmp r3, #33 @ 0x21 8012ff6: d160 bne.n 80130ba { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 8012ff8: 687b ldr r3, [r7, #4] 8012ffa: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 8012ffe: 87fb strh r3, [r7, #62] @ 0x3e 8013000: e057 b.n 80130b2 { if (huart->TxXferCount == 0U) 8013002: 687b ldr r3, [r7, #4] 8013004: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8013008: b29b uxth r3, r3 801300a: 2b00 cmp r3, #0 801300c: d133 bne.n 8013076 { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 801300e: 687b ldr r3, [r7, #4] 8013010: 681b ldr r3, [r3, #0] 8013012: 3308 adds r3, #8 8013014: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013016: 6a7b ldr r3, [r7, #36] @ 0x24 8013018: e853 3f00 ldrex r3, [r3] 801301c: 623b str r3, [r7, #32] return(result); 801301e: 6a3b ldr r3, [r7, #32] 8013020: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 8013024: 63bb str r3, [r7, #56] @ 0x38 8013026: 687b ldr r3, [r7, #4] 8013028: 681b ldr r3, [r3, #0] 801302a: 3308 adds r3, #8 801302c: 6bba ldr r2, [r7, #56] @ 0x38 801302e: 633a str r2, [r7, #48] @ 0x30 8013030: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013032: 6af9 ldr r1, [r7, #44] @ 0x2c 8013034: 6b3a ldr r2, [r7, #48] @ 0x30 8013036: e841 2300 strex r3, r2, [r1] 801303a: 62bb str r3, [r7, #40] @ 0x28 return(result); 801303c: 6abb ldr r3, [r7, #40] @ 0x28 801303e: 2b00 cmp r3, #0 8013040: d1e5 bne.n 801300e /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8013042: 687b ldr r3, [r7, #4] 8013044: 681b ldr r3, [r3, #0] 8013046: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013048: 693b ldr r3, [r7, #16] 801304a: e853 3f00 ldrex r3, [r3] 801304e: 60fb str r3, [r7, #12] return(result); 8013050: 68fb ldr r3, [r7, #12] 8013052: f043 0340 orr.w r3, r3, #64 @ 0x40 8013056: 637b str r3, [r7, #52] @ 0x34 8013058: 687b ldr r3, [r7, #4] 801305a: 681b ldr r3, [r3, #0] 801305c: 461a mov r2, r3 801305e: 6b7b ldr r3, [r7, #52] @ 0x34 8013060: 61fb str r3, [r7, #28] 8013062: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013064: 69b9 ldr r1, [r7, #24] 8013066: 69fa ldr r2, [r7, #28] 8013068: e841 2300 strex r3, r2, [r1] 801306c: 617b str r3, [r7, #20] return(result); 801306e: 697b ldr r3, [r7, #20] 8013070: 2b00 cmp r3, #0 8013072: d1e6 bne.n 8013042 break; /* force exit loop */ 8013074: e021 b.n 80130ba } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 8013076: 687b ldr r3, [r7, #4] 8013078: 681b ldr r3, [r3, #0] 801307a: 69db ldr r3, [r3, #28] 801307c: f003 0380 and.w r3, r3, #128 @ 0x80 8013080: 2b00 cmp r3, #0 8013082: d013 beq.n 80130ac { huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 8013084: 687b ldr r3, [r7, #4] 8013086: 6d1b ldr r3, [r3, #80] @ 0x50 8013088: 781a ldrb r2, [r3, #0] 801308a: 687b ldr r3, [r7, #4] 801308c: 681b ldr r3, [r3, #0] 801308e: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 8013090: 687b ldr r3, [r7, #4] 8013092: 6d1b ldr r3, [r3, #80] @ 0x50 8013094: 1c5a adds r2, r3, #1 8013096: 687b ldr r3, [r7, #4] 8013098: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 801309a: 687b ldr r3, [r7, #4] 801309c: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80130a0: b29b uxth r3, r3 80130a2: 3b01 subs r3, #1 80130a4: b29a uxth r2, r3 80130a6: 687b ldr r3, [r7, #4] 80130a8: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80130ac: 8ffb ldrh r3, [r7, #62] @ 0x3e 80130ae: 3b01 subs r3, #1 80130b0: 87fb strh r3, [r7, #62] @ 0x3e 80130b2: 8ffb ldrh r3, [r7, #62] @ 0x3e 80130b4: 2b00 cmp r3, #0 80130b6: d1a4 bne.n 8013002 { /* Nothing to do */ } } } } 80130b8: e7ff b.n 80130ba 80130ba: bf00 nop 80130bc: 3744 adds r7, #68 @ 0x44 80130be: 46bd mov sp, r7 80130c0: f85d 7b04 ldr.w r7, [sp], #4 80130c4: 4770 bx lr 080130c6 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 80130c6: b480 push {r7} 80130c8: b091 sub sp, #68 @ 0x44 80130ca: af00 add r7, sp, #0 80130cc: 6078 str r0, [r7, #4] const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 80130ce: 687b ldr r3, [r7, #4] 80130d0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80130d4: 2b21 cmp r3, #33 @ 0x21 80130d6: d165 bne.n 80131a4 { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80130d8: 687b ldr r3, [r7, #4] 80130da: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 80130de: 87fb strh r3, [r7, #62] @ 0x3e 80130e0: e05c b.n 801319c { if (huart->TxXferCount == 0U) 80130e2: 687b ldr r3, [r7, #4] 80130e4: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80130e8: b29b uxth r3, r3 80130ea: 2b00 cmp r3, #0 80130ec: d133 bne.n 8013156 { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 80130ee: 687b ldr r3, [r7, #4] 80130f0: 681b ldr r3, [r3, #0] 80130f2: 3308 adds r3, #8 80130f4: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80130f6: 6a3b ldr r3, [r7, #32] 80130f8: e853 3f00 ldrex r3, [r3] 80130fc: 61fb str r3, [r7, #28] return(result); 80130fe: 69fb ldr r3, [r7, #28] 8013100: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 8013104: 637b str r3, [r7, #52] @ 0x34 8013106: 687b ldr r3, [r7, #4] 8013108: 681b ldr r3, [r3, #0] 801310a: 3308 adds r3, #8 801310c: 6b7a ldr r2, [r7, #52] @ 0x34 801310e: 62fa str r2, [r7, #44] @ 0x2c 8013110: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013112: 6ab9 ldr r1, [r7, #40] @ 0x28 8013114: 6afa ldr r2, [r7, #44] @ 0x2c 8013116: e841 2300 strex r3, r2, [r1] 801311a: 627b str r3, [r7, #36] @ 0x24 return(result); 801311c: 6a7b ldr r3, [r7, #36] @ 0x24 801311e: 2b00 cmp r3, #0 8013120: d1e5 bne.n 80130ee /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8013122: 687b ldr r3, [r7, #4] 8013124: 681b ldr r3, [r3, #0] 8013126: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013128: 68fb ldr r3, [r7, #12] 801312a: e853 3f00 ldrex r3, [r3] 801312e: 60bb str r3, [r7, #8] return(result); 8013130: 68bb ldr r3, [r7, #8] 8013132: f043 0340 orr.w r3, r3, #64 @ 0x40 8013136: 633b str r3, [r7, #48] @ 0x30 8013138: 687b ldr r3, [r7, #4] 801313a: 681b ldr r3, [r3, #0] 801313c: 461a mov r2, r3 801313e: 6b3b ldr r3, [r7, #48] @ 0x30 8013140: 61bb str r3, [r7, #24] 8013142: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013144: 6979 ldr r1, [r7, #20] 8013146: 69ba ldr r2, [r7, #24] 8013148: e841 2300 strex r3, r2, [r1] 801314c: 613b str r3, [r7, #16] return(result); 801314e: 693b ldr r3, [r7, #16] 8013150: 2b00 cmp r3, #0 8013152: d1e6 bne.n 8013122 break; /* force exit loop */ 8013154: e026 b.n 80131a4 } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 8013156: 687b ldr r3, [r7, #4] 8013158: 681b ldr r3, [r3, #0] 801315a: 69db ldr r3, [r3, #28] 801315c: f003 0380 and.w r3, r3, #128 @ 0x80 8013160: 2b00 cmp r3, #0 8013162: d018 beq.n 8013196 { tmp = (const uint16_t *) huart->pTxBuffPtr; 8013164: 687b ldr r3, [r7, #4] 8013166: 6d1b ldr r3, [r3, #80] @ 0x50 8013168: 63bb str r3, [r7, #56] @ 0x38 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 801316a: 6bbb ldr r3, [r7, #56] @ 0x38 801316c: 881b ldrh r3, [r3, #0] 801316e: 461a mov r2, r3 8013170: 687b ldr r3, [r7, #4] 8013172: 681b ldr r3, [r3, #0] 8013174: f3c2 0208 ubfx r2, r2, #0, #9 8013178: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 801317a: 687b ldr r3, [r7, #4] 801317c: 6d1b ldr r3, [r3, #80] @ 0x50 801317e: 1c9a adds r2, r3, #2 8013180: 687b ldr r3, [r7, #4] 8013182: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 8013184: 687b ldr r3, [r7, #4] 8013186: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 801318a: b29b uxth r3, r3 801318c: 3b01 subs r3, #1 801318e: b29a uxth r2, r3 8013190: 687b ldr r3, [r7, #4] 8013192: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 8013196: 8ffb ldrh r3, [r7, #62] @ 0x3e 8013198: 3b01 subs r3, #1 801319a: 87fb strh r3, [r7, #62] @ 0x3e 801319c: 8ffb ldrh r3, [r7, #62] @ 0x3e 801319e: 2b00 cmp r3, #0 80131a0: d19f bne.n 80130e2 { /* Nothing to do */ } } } } 80131a2: e7ff b.n 80131a4 80131a4: bf00 nop 80131a6: 3744 adds r7, #68 @ 0x44 80131a8: 46bd mov sp, r7 80131aa: f85d 7b04 ldr.w r7, [sp], #4 80131ae: 4770 bx lr 080131b0 : * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 80131b0: b580 push {r7, lr} 80131b2: b088 sub sp, #32 80131b4: af00 add r7, sp, #0 80131b6: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80131b8: 687b ldr r3, [r7, #4] 80131ba: 681b ldr r3, [r3, #0] 80131bc: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80131be: 68fb ldr r3, [r7, #12] 80131c0: e853 3f00 ldrex r3, [r3] 80131c4: 60bb str r3, [r7, #8] return(result); 80131c6: 68bb ldr r3, [r7, #8] 80131c8: f023 0340 bic.w r3, r3, #64 @ 0x40 80131cc: 61fb str r3, [r7, #28] 80131ce: 687b ldr r3, [r7, #4] 80131d0: 681b ldr r3, [r3, #0] 80131d2: 461a mov r2, r3 80131d4: 69fb ldr r3, [r7, #28] 80131d6: 61bb str r3, [r7, #24] 80131d8: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80131da: 6979 ldr r1, [r7, #20] 80131dc: 69ba ldr r2, [r7, #24] 80131de: e841 2300 strex r3, r2, [r1] 80131e2: 613b str r3, [r7, #16] return(result); 80131e4: 693b ldr r3, [r7, #16] 80131e6: 2b00 cmp r3, #0 80131e8: d1e6 bne.n 80131b8 /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80131ea: 687b ldr r3, [r7, #4] 80131ec: 2220 movs r2, #32 80131ee: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Cleat TxISR function pointer */ huart->TxISR = NULL; 80131f2: 687b ldr r3, [r7, #4] 80131f4: 2200 movs r2, #0 80131f6: 679a str r2, [r3, #120] @ 0x78 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 80131f8: 6878 ldr r0, [r7, #4] 80131fa: f7f1 fc8d bl 8004b18 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80131fe: bf00 nop 8013200: 3720 adds r7, #32 8013202: 46bd mov sp, r7 8013204: bd80 pop {r7, pc} ... 08013208 : * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) { 8013208: b580 push {r7, lr} 801320a: b09c sub sp, #112 @ 0x70 801320c: af00 add r7, sp, #0 801320e: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 8013210: 687b ldr r3, [r7, #4] 8013212: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8013216: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 801321a: 687b ldr r3, [r7, #4] 801321c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8013220: 2b22 cmp r3, #34 @ 0x22 8013222: f040 80be bne.w 80133a2 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8013226: 687b ldr r3, [r7, #4] 8013228: 681b ldr r3, [r3, #0] 801322a: 6a5b ldr r3, [r3, #36] @ 0x24 801322c: f8a7 306c strh.w r3, [r7, #108] @ 0x6c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 8013230: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 8013234: b2d9 uxtb r1, r3 8013236: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 801323a: b2da uxtb r2, r3 801323c: 687b ldr r3, [r7, #4] 801323e: 6d9b ldr r3, [r3, #88] @ 0x58 8013240: 400a ands r2, r1 8013242: b2d2 uxtb r2, r2 8013244: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8013246: 687b ldr r3, [r7, #4] 8013248: 6d9b ldr r3, [r3, #88] @ 0x58 801324a: 1c5a adds r2, r3, #1 801324c: 687b ldr r3, [r7, #4] 801324e: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8013250: 687b ldr r3, [r7, #4] 8013252: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013256: b29b uxth r3, r3 8013258: 3b01 subs r3, #1 801325a: b29a uxth r2, r3 801325c: 687b ldr r3, [r7, #4] 801325e: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 8013262: 687b ldr r3, [r7, #4] 8013264: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013268: b29b uxth r3, r3 801326a: 2b00 cmp r3, #0 801326c: f040 80a1 bne.w 80133b2 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8013270: 687b ldr r3, [r7, #4] 8013272: 681b ldr r3, [r3, #0] 8013274: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013276: 6cfb ldr r3, [r7, #76] @ 0x4c 8013278: e853 3f00 ldrex r3, [r3] 801327c: 64bb str r3, [r7, #72] @ 0x48 return(result); 801327e: 6cbb ldr r3, [r7, #72] @ 0x48 8013280: f423 7390 bic.w r3, r3, #288 @ 0x120 8013284: 66bb str r3, [r7, #104] @ 0x68 8013286: 687b ldr r3, [r7, #4] 8013288: 681b ldr r3, [r3, #0] 801328a: 461a mov r2, r3 801328c: 6ebb ldr r3, [r7, #104] @ 0x68 801328e: 65bb str r3, [r7, #88] @ 0x58 8013290: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013292: 6d79 ldr r1, [r7, #84] @ 0x54 8013294: 6dba ldr r2, [r7, #88] @ 0x58 8013296: e841 2300 strex r3, r2, [r1] 801329a: 653b str r3, [r7, #80] @ 0x50 return(result); 801329c: 6d3b ldr r3, [r7, #80] @ 0x50 801329e: 2b00 cmp r3, #0 80132a0: d1e6 bne.n 8013270 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80132a2: 687b ldr r3, [r7, #4] 80132a4: 681b ldr r3, [r3, #0] 80132a6: 3308 adds r3, #8 80132a8: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80132aa: 6bbb ldr r3, [r7, #56] @ 0x38 80132ac: e853 3f00 ldrex r3, [r3] 80132b0: 637b str r3, [r7, #52] @ 0x34 return(result); 80132b2: 6b7b ldr r3, [r7, #52] @ 0x34 80132b4: f023 0301 bic.w r3, r3, #1 80132b8: 667b str r3, [r7, #100] @ 0x64 80132ba: 687b ldr r3, [r7, #4] 80132bc: 681b ldr r3, [r3, #0] 80132be: 3308 adds r3, #8 80132c0: 6e7a ldr r2, [r7, #100] @ 0x64 80132c2: 647a str r2, [r7, #68] @ 0x44 80132c4: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80132c6: 6c39 ldr r1, [r7, #64] @ 0x40 80132c8: 6c7a ldr r2, [r7, #68] @ 0x44 80132ca: e841 2300 strex r3, r2, [r1] 80132ce: 63fb str r3, [r7, #60] @ 0x3c return(result); 80132d0: 6bfb ldr r3, [r7, #60] @ 0x3c 80132d2: 2b00 cmp r3, #0 80132d4: d1e5 bne.n 80132a2 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80132d6: 687b ldr r3, [r7, #4] 80132d8: 2220 movs r2, #32 80132da: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 80132de: 687b ldr r3, [r7, #4] 80132e0: 2200 movs r2, #0 80132e2: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80132e4: 687b ldr r3, [r7, #4] 80132e6: 2200 movs r2, #0 80132e8: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 80132ea: 687b ldr r3, [r7, #4] 80132ec: 681b ldr r3, [r3, #0] 80132ee: 4a33 ldr r2, [pc, #204] @ (80133bc ) 80132f0: 4293 cmp r3, r2 80132f2: d01f beq.n 8013334 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 80132f4: 687b ldr r3, [r7, #4] 80132f6: 681b ldr r3, [r3, #0] 80132f8: 685b ldr r3, [r3, #4] 80132fa: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80132fe: 2b00 cmp r3, #0 8013300: d018 beq.n 8013334 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8013302: 687b ldr r3, [r7, #4] 8013304: 681b ldr r3, [r3, #0] 8013306: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013308: 6a7b ldr r3, [r7, #36] @ 0x24 801330a: e853 3f00 ldrex r3, [r3] 801330e: 623b str r3, [r7, #32] return(result); 8013310: 6a3b ldr r3, [r7, #32] 8013312: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8013316: 663b str r3, [r7, #96] @ 0x60 8013318: 687b ldr r3, [r7, #4] 801331a: 681b ldr r3, [r3, #0] 801331c: 461a mov r2, r3 801331e: 6e3b ldr r3, [r7, #96] @ 0x60 8013320: 633b str r3, [r7, #48] @ 0x30 8013322: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013324: 6af9 ldr r1, [r7, #44] @ 0x2c 8013326: 6b3a ldr r2, [r7, #48] @ 0x30 8013328: e841 2300 strex r3, r2, [r1] 801332c: 62bb str r3, [r7, #40] @ 0x28 return(result); 801332e: 6abb ldr r3, [r7, #40] @ 0x28 8013330: 2b00 cmp r3, #0 8013332: d1e6 bne.n 8013302 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013334: 687b ldr r3, [r7, #4] 8013336: 6edb ldr r3, [r3, #108] @ 0x6c 8013338: 2b01 cmp r3, #1 801333a: d12e bne.n 801339a { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801333c: 687b ldr r3, [r7, #4] 801333e: 2200 movs r2, #0 8013340: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013342: 687b ldr r3, [r7, #4] 8013344: 681b ldr r3, [r3, #0] 8013346: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013348: 693b ldr r3, [r7, #16] 801334a: e853 3f00 ldrex r3, [r3] 801334e: 60fb str r3, [r7, #12] return(result); 8013350: 68fb ldr r3, [r7, #12] 8013352: f023 0310 bic.w r3, r3, #16 8013356: 65fb str r3, [r7, #92] @ 0x5c 8013358: 687b ldr r3, [r7, #4] 801335a: 681b ldr r3, [r3, #0] 801335c: 461a mov r2, r3 801335e: 6dfb ldr r3, [r7, #92] @ 0x5c 8013360: 61fb str r3, [r7, #28] 8013362: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013364: 69b9 ldr r1, [r7, #24] 8013366: 69fa ldr r2, [r7, #28] 8013368: e841 2300 strex r3, r2, [r1] 801336c: 617b str r3, [r7, #20] return(result); 801336e: 697b ldr r3, [r7, #20] 8013370: 2b00 cmp r3, #0 8013372: d1e6 bne.n 8013342 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8013374: 687b ldr r3, [r7, #4] 8013376: 681b ldr r3, [r3, #0] 8013378: 69db ldr r3, [r3, #28] 801337a: f003 0310 and.w r3, r3, #16 801337e: 2b10 cmp r3, #16 8013380: d103 bne.n 801338a { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8013382: 687b ldr r3, [r7, #4] 8013384: 681b ldr r3, [r3, #0] 8013386: 2210 movs r2, #16 8013388: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 801338a: 687b ldr r3, [r7, #4] 801338c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8013390: 4619 mov r1, r3 8013392: 6878 ldr r0, [r7, #4] 8013394: f7f1 fb96 bl 8004ac4 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8013398: e00b b.n 80133b2 HAL_UART_RxCpltCallback(huart); 801339a: 6878 ldr r0, [r7, #4] 801339c: f7f1 fb88 bl 8004ab0 } 80133a0: e007 b.n 80133b2 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 80133a2: 687b ldr r3, [r7, #4] 80133a4: 681b ldr r3, [r3, #0] 80133a6: 699a ldr r2, [r3, #24] 80133a8: 687b ldr r3, [r7, #4] 80133aa: 681b ldr r3, [r3, #0] 80133ac: f042 0208 orr.w r2, r2, #8 80133b0: 619a str r2, [r3, #24] } 80133b2: bf00 nop 80133b4: 3770 adds r7, #112 @ 0x70 80133b6: 46bd mov sp, r7 80133b8: bd80 pop {r7, pc} 80133ba: bf00 nop 80133bc: 58000c00 .word 0x58000c00 080133c0 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { 80133c0: b580 push {r7, lr} 80133c2: b09c sub sp, #112 @ 0x70 80133c4: af00 add r7, sp, #0 80133c6: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 80133c8: 687b ldr r3, [r7, #4] 80133ca: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 80133ce: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80133d2: 687b ldr r3, [r7, #4] 80133d4: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80133d8: 2b22 cmp r3, #34 @ 0x22 80133da: f040 80be bne.w 801355a { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 80133de: 687b ldr r3, [r7, #4] 80133e0: 681b ldr r3, [r3, #0] 80133e2: 6a5b ldr r3, [r3, #36] @ 0x24 80133e4: f8a7 306c strh.w r3, [r7, #108] @ 0x6c tmp = (uint16_t *) huart->pRxBuffPtr ; 80133e8: 687b ldr r3, [r7, #4] 80133ea: 6d9b ldr r3, [r3, #88] @ 0x58 80133ec: 66bb str r3, [r7, #104] @ 0x68 *tmp = (uint16_t)(uhdata & uhMask); 80133ee: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c 80133f2: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 80133f6: 4013 ands r3, r2 80133f8: b29a uxth r2, r3 80133fa: 6ebb ldr r3, [r7, #104] @ 0x68 80133fc: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 80133fe: 687b ldr r3, [r7, #4] 8013400: 6d9b ldr r3, [r3, #88] @ 0x58 8013402: 1c9a adds r2, r3, #2 8013404: 687b ldr r3, [r7, #4] 8013406: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8013408: 687b ldr r3, [r7, #4] 801340a: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 801340e: b29b uxth r3, r3 8013410: 3b01 subs r3, #1 8013412: b29a uxth r2, r3 8013414: 687b ldr r3, [r7, #4] 8013416: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 801341a: 687b ldr r3, [r7, #4] 801341c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013420: b29b uxth r3, r3 8013422: 2b00 cmp r3, #0 8013424: f040 80a1 bne.w 801356a { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8013428: 687b ldr r3, [r7, #4] 801342a: 681b ldr r3, [r3, #0] 801342c: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801342e: 6cbb ldr r3, [r7, #72] @ 0x48 8013430: e853 3f00 ldrex r3, [r3] 8013434: 647b str r3, [r7, #68] @ 0x44 return(result); 8013436: 6c7b ldr r3, [r7, #68] @ 0x44 8013438: f423 7390 bic.w r3, r3, #288 @ 0x120 801343c: 667b str r3, [r7, #100] @ 0x64 801343e: 687b ldr r3, [r7, #4] 8013440: 681b ldr r3, [r3, #0] 8013442: 461a mov r2, r3 8013444: 6e7b ldr r3, [r7, #100] @ 0x64 8013446: 657b str r3, [r7, #84] @ 0x54 8013448: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801344a: 6d39 ldr r1, [r7, #80] @ 0x50 801344c: 6d7a ldr r2, [r7, #84] @ 0x54 801344e: e841 2300 strex r3, r2, [r1] 8013452: 64fb str r3, [r7, #76] @ 0x4c return(result); 8013454: 6cfb ldr r3, [r7, #76] @ 0x4c 8013456: 2b00 cmp r3, #0 8013458: d1e6 bne.n 8013428 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 801345a: 687b ldr r3, [r7, #4] 801345c: 681b ldr r3, [r3, #0] 801345e: 3308 adds r3, #8 8013460: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013462: 6b7b ldr r3, [r7, #52] @ 0x34 8013464: e853 3f00 ldrex r3, [r3] 8013468: 633b str r3, [r7, #48] @ 0x30 return(result); 801346a: 6b3b ldr r3, [r7, #48] @ 0x30 801346c: f023 0301 bic.w r3, r3, #1 8013470: 663b str r3, [r7, #96] @ 0x60 8013472: 687b ldr r3, [r7, #4] 8013474: 681b ldr r3, [r3, #0] 8013476: 3308 adds r3, #8 8013478: 6e3a ldr r2, [r7, #96] @ 0x60 801347a: 643a str r2, [r7, #64] @ 0x40 801347c: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801347e: 6bf9 ldr r1, [r7, #60] @ 0x3c 8013480: 6c3a ldr r2, [r7, #64] @ 0x40 8013482: e841 2300 strex r3, r2, [r1] 8013486: 63bb str r3, [r7, #56] @ 0x38 return(result); 8013488: 6bbb ldr r3, [r7, #56] @ 0x38 801348a: 2b00 cmp r3, #0 801348c: d1e5 bne.n 801345a /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 801348e: 687b ldr r3, [r7, #4] 8013490: 2220 movs r2, #32 8013492: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8013496: 687b ldr r3, [r7, #4] 8013498: 2200 movs r2, #0 801349a: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 801349c: 687b ldr r3, [r7, #4] 801349e: 2200 movs r2, #0 80134a0: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 80134a2: 687b ldr r3, [r7, #4] 80134a4: 681b ldr r3, [r3, #0] 80134a6: 4a33 ldr r2, [pc, #204] @ (8013574 ) 80134a8: 4293 cmp r3, r2 80134aa: d01f beq.n 80134ec { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 80134ac: 687b ldr r3, [r7, #4] 80134ae: 681b ldr r3, [r3, #0] 80134b0: 685b ldr r3, [r3, #4] 80134b2: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80134b6: 2b00 cmp r3, #0 80134b8: d018 beq.n 80134ec { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 80134ba: 687b ldr r3, [r7, #4] 80134bc: 681b ldr r3, [r3, #0] 80134be: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80134c0: 6a3b ldr r3, [r7, #32] 80134c2: e853 3f00 ldrex r3, [r3] 80134c6: 61fb str r3, [r7, #28] return(result); 80134c8: 69fb ldr r3, [r7, #28] 80134ca: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 80134ce: 65fb str r3, [r7, #92] @ 0x5c 80134d0: 687b ldr r3, [r7, #4] 80134d2: 681b ldr r3, [r3, #0] 80134d4: 461a mov r2, r3 80134d6: 6dfb ldr r3, [r7, #92] @ 0x5c 80134d8: 62fb str r3, [r7, #44] @ 0x2c 80134da: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80134dc: 6ab9 ldr r1, [r7, #40] @ 0x28 80134de: 6afa ldr r2, [r7, #44] @ 0x2c 80134e0: e841 2300 strex r3, r2, [r1] 80134e4: 627b str r3, [r7, #36] @ 0x24 return(result); 80134e6: 6a7b ldr r3, [r7, #36] @ 0x24 80134e8: 2b00 cmp r3, #0 80134ea: d1e6 bne.n 80134ba } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80134ec: 687b ldr r3, [r7, #4] 80134ee: 6edb ldr r3, [r3, #108] @ 0x6c 80134f0: 2b01 cmp r3, #1 80134f2: d12e bne.n 8013552 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80134f4: 687b ldr r3, [r7, #4] 80134f6: 2200 movs r2, #0 80134f8: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80134fa: 687b ldr r3, [r7, #4] 80134fc: 681b ldr r3, [r3, #0] 80134fe: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013500: 68fb ldr r3, [r7, #12] 8013502: e853 3f00 ldrex r3, [r3] 8013506: 60bb str r3, [r7, #8] return(result); 8013508: 68bb ldr r3, [r7, #8] 801350a: f023 0310 bic.w r3, r3, #16 801350e: 65bb str r3, [r7, #88] @ 0x58 8013510: 687b ldr r3, [r7, #4] 8013512: 681b ldr r3, [r3, #0] 8013514: 461a mov r2, r3 8013516: 6dbb ldr r3, [r7, #88] @ 0x58 8013518: 61bb str r3, [r7, #24] 801351a: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801351c: 6979 ldr r1, [r7, #20] 801351e: 69ba ldr r2, [r7, #24] 8013520: e841 2300 strex r3, r2, [r1] 8013524: 613b str r3, [r7, #16] return(result); 8013526: 693b ldr r3, [r7, #16] 8013528: 2b00 cmp r3, #0 801352a: d1e6 bne.n 80134fa if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 801352c: 687b ldr r3, [r7, #4] 801352e: 681b ldr r3, [r3, #0] 8013530: 69db ldr r3, [r3, #28] 8013532: f003 0310 and.w r3, r3, #16 8013536: 2b10 cmp r3, #16 8013538: d103 bne.n 8013542 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 801353a: 687b ldr r3, [r7, #4] 801353c: 681b ldr r3, [r3, #0] 801353e: 2210 movs r2, #16 8013540: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8013542: 687b ldr r3, [r7, #4] 8013544: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8013548: 4619 mov r1, r3 801354a: 6878 ldr r0, [r7, #4] 801354c: f7f1 faba bl 8004ac4 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8013550: e00b b.n 801356a HAL_UART_RxCpltCallback(huart); 8013552: 6878 ldr r0, [r7, #4] 8013554: f7f1 faac bl 8004ab0 } 8013558: e007 b.n 801356a __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 801355a: 687b ldr r3, [r7, #4] 801355c: 681b ldr r3, [r3, #0] 801355e: 699a ldr r2, [r3, #24] 8013560: 687b ldr r3, [r7, #4] 8013562: 681b ldr r3, [r3, #0] 8013564: f042 0208 orr.w r2, r2, #8 8013568: 619a str r2, [r3, #24] } 801356a: bf00 nop 801356c: 3770 adds r7, #112 @ 0x70 801356e: 46bd mov sp, r7 8013570: bd80 pop {r7, pc} 8013572: bf00 nop 8013574: 58000c00 .word 0x58000c00 08013578 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 8013578: b580 push {r7, lr} 801357a: b0ac sub sp, #176 @ 0xb0 801357c: af00 add r7, sp, #0 801357e: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 8013580: 687b ldr r3, [r7, #4] 8013582: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8013586: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 801358a: 687b ldr r3, [r7, #4] 801358c: 681b ldr r3, [r3, #0] 801358e: 69db ldr r3, [r3, #28] 8013590: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr1its = READ_REG(huart->Instance->CR1); 8013594: 687b ldr r3, [r7, #4] 8013596: 681b ldr r3, [r3, #0] 8013598: 681b ldr r3, [r3, #0] 801359a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t cr3its = READ_REG(huart->Instance->CR3); 801359e: 687b ldr r3, [r7, #4] 80135a0: 681b ldr r3, [r3, #0] 80135a2: 689b ldr r3, [r3, #8] 80135a4: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80135a8: 687b ldr r3, [r7, #4] 80135aa: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80135ae: 2b22 cmp r3, #34 @ 0x22 80135b0: f040 8180 bne.w 80138b4 { nb_rx_data = huart->NbRxDataToProcess; 80135b4: 687b ldr r3, [r7, #4] 80135b6: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 80135ba: f8a7 309e strh.w r3, [r7, #158] @ 0x9e while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 80135be: e123 b.n 8013808 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 80135c0: 687b ldr r3, [r7, #4] 80135c2: 681b ldr r3, [r3, #0] 80135c4: 6a5b ldr r3, [r3, #36] @ 0x24 80135c6: f8a7 309c strh.w r3, [r7, #156] @ 0x9c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 80135ca: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c 80135ce: b2d9 uxtb r1, r3 80135d0: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa 80135d4: b2da uxtb r2, r3 80135d6: 687b ldr r3, [r7, #4] 80135d8: 6d9b ldr r3, [r3, #88] @ 0x58 80135da: 400a ands r2, r1 80135dc: b2d2 uxtb r2, r2 80135de: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 80135e0: 687b ldr r3, [r7, #4] 80135e2: 6d9b ldr r3, [r3, #88] @ 0x58 80135e4: 1c5a adds r2, r3, #1 80135e6: 687b ldr r3, [r7, #4] 80135e8: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 80135ea: 687b ldr r3, [r7, #4] 80135ec: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80135f0: b29b uxth r3, r3 80135f2: 3b01 subs r3, #1 80135f4: b29a uxth r2, r3 80135f6: 687b ldr r3, [r7, #4] 80135f8: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 80135fc: 687b ldr r3, [r7, #4] 80135fe: 681b ldr r3, [r3, #0] 8013600: 69db ldr r3, [r3, #28] 8013602: f8c7 30ac str.w r3, [r7, #172] @ 0xac /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8013606: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801360a: f003 0307 and.w r3, r3, #7 801360e: 2b00 cmp r3, #0 8013610: d053 beq.n 80136ba { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8013612: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8013616: f003 0301 and.w r3, r3, #1 801361a: 2b00 cmp r3, #0 801361c: d011 beq.n 8013642 801361e: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 8013622: f403 7380 and.w r3, r3, #256 @ 0x100 8013626: 2b00 cmp r3, #0 8013628: d00b beq.n 8013642 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 801362a: 687b ldr r3, [r7, #4] 801362c: 681b ldr r3, [r3, #0] 801362e: 2201 movs r2, #1 8013630: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8013632: 687b ldr r3, [r7, #4] 8013634: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013638: f043 0201 orr.w r2, r3, #1 801363c: 687b ldr r3, [r7, #4] 801363e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8013642: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8013646: f003 0302 and.w r3, r3, #2 801364a: 2b00 cmp r3, #0 801364c: d011 beq.n 8013672 801364e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8013652: f003 0301 and.w r3, r3, #1 8013656: 2b00 cmp r3, #0 8013658: d00b beq.n 8013672 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 801365a: 687b ldr r3, [r7, #4] 801365c: 681b ldr r3, [r3, #0] 801365e: 2202 movs r2, #2 8013660: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8013662: 687b ldr r3, [r7, #4] 8013664: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013668: f043 0204 orr.w r2, r3, #4 801366c: 687b ldr r3, [r7, #4] 801366e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8013672: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8013676: f003 0304 and.w r3, r3, #4 801367a: 2b00 cmp r3, #0 801367c: d011 beq.n 80136a2 801367e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8013682: f003 0301 and.w r3, r3, #1 8013686: 2b00 cmp r3, #0 8013688: d00b beq.n 80136a2 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 801368a: 687b ldr r3, [r7, #4] 801368c: 681b ldr r3, [r3, #0] 801368e: 2204 movs r2, #4 8013690: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8013692: 687b ldr r3, [r7, #4] 8013694: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013698: f043 0202 orr.w r2, r3, #2 801369c: 687b ldr r3, [r7, #4] 801369e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 80136a2: 687b ldr r3, [r7, #4] 80136a4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80136a8: 2b00 cmp r3, #0 80136aa: d006 beq.n 80136ba #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80136ac: 6878 ldr r0, [r7, #4] 80136ae: f7fe fb13 bl 8011cd8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80136b2: 687b ldr r3, [r7, #4] 80136b4: 2200 movs r2, #0 80136b6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 80136ba: 687b ldr r3, [r7, #4] 80136bc: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80136c0: b29b uxth r3, r3 80136c2: 2b00 cmp r3, #0 80136c4: f040 80a0 bne.w 8013808 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80136c8: 687b ldr r3, [r7, #4] 80136ca: 681b ldr r3, [r3, #0] 80136cc: 673b str r3, [r7, #112] @ 0x70 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80136ce: 6f3b ldr r3, [r7, #112] @ 0x70 80136d0: e853 3f00 ldrex r3, [r3] 80136d4: 66fb str r3, [r7, #108] @ 0x6c return(result); 80136d6: 6efb ldr r3, [r7, #108] @ 0x6c 80136d8: f423 7380 bic.w r3, r3, #256 @ 0x100 80136dc: f8c7 3098 str.w r3, [r7, #152] @ 0x98 80136e0: 687b ldr r3, [r7, #4] 80136e2: 681b ldr r3, [r3, #0] 80136e4: 461a mov r2, r3 80136e6: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 80136ea: 67fb str r3, [r7, #124] @ 0x7c 80136ec: 67ba str r2, [r7, #120] @ 0x78 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80136ee: 6fb9 ldr r1, [r7, #120] @ 0x78 80136f0: 6ffa ldr r2, [r7, #124] @ 0x7c 80136f2: e841 2300 strex r3, r2, [r1] 80136f6: 677b str r3, [r7, #116] @ 0x74 return(result); 80136f8: 6f7b ldr r3, [r7, #116] @ 0x74 80136fa: 2b00 cmp r3, #0 80136fc: d1e4 bne.n 80136c8 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 80136fe: 687b ldr r3, [r7, #4] 8013700: 681b ldr r3, [r3, #0] 8013702: 3308 adds r3, #8 8013704: 65fb str r3, [r7, #92] @ 0x5c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013706: 6dfb ldr r3, [r7, #92] @ 0x5c 8013708: e853 3f00 ldrex r3, [r3] 801370c: 65bb str r3, [r7, #88] @ 0x58 return(result); 801370e: 6dba ldr r2, [r7, #88] @ 0x58 8013710: 4b6e ldr r3, [pc, #440] @ (80138cc ) 8013712: 4013 ands r3, r2 8013714: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8013718: 687b ldr r3, [r7, #4] 801371a: 681b ldr r3, [r3, #0] 801371c: 3308 adds r3, #8 801371e: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8013722: 66ba str r2, [r7, #104] @ 0x68 8013724: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013726: 6e79 ldr r1, [r7, #100] @ 0x64 8013728: 6eba ldr r2, [r7, #104] @ 0x68 801372a: e841 2300 strex r3, r2, [r1] 801372e: 663b str r3, [r7, #96] @ 0x60 return(result); 8013730: 6e3b ldr r3, [r7, #96] @ 0x60 8013732: 2b00 cmp r3, #0 8013734: d1e3 bne.n 80136fe /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013736: 687b ldr r3, [r7, #4] 8013738: 2220 movs r2, #32 801373a: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 801373e: 687b ldr r3, [r7, #4] 8013740: 2200 movs r2, #0 8013742: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8013744: 687b ldr r3, [r7, #4] 8013746: 2200 movs r2, #0 8013748: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 801374a: 687b ldr r3, [r7, #4] 801374c: 681b ldr r3, [r3, #0] 801374e: 4a60 ldr r2, [pc, #384] @ (80138d0 ) 8013750: 4293 cmp r3, r2 8013752: d021 beq.n 8013798 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8013754: 687b ldr r3, [r7, #4] 8013756: 681b ldr r3, [r3, #0] 8013758: 685b ldr r3, [r3, #4] 801375a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 801375e: 2b00 cmp r3, #0 8013760: d01a beq.n 8013798 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8013762: 687b ldr r3, [r7, #4] 8013764: 681b ldr r3, [r3, #0] 8013766: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013768: 6cbb ldr r3, [r7, #72] @ 0x48 801376a: e853 3f00 ldrex r3, [r3] 801376e: 647b str r3, [r7, #68] @ 0x44 return(result); 8013770: 6c7b ldr r3, [r7, #68] @ 0x44 8013772: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8013776: f8c7 3090 str.w r3, [r7, #144] @ 0x90 801377a: 687b ldr r3, [r7, #4] 801377c: 681b ldr r3, [r3, #0] 801377e: 461a mov r2, r3 8013780: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8013784: 657b str r3, [r7, #84] @ 0x54 8013786: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013788: 6d39 ldr r1, [r7, #80] @ 0x50 801378a: 6d7a ldr r2, [r7, #84] @ 0x54 801378c: e841 2300 strex r3, r2, [r1] 8013790: 64fb str r3, [r7, #76] @ 0x4c return(result); 8013792: 6cfb ldr r3, [r7, #76] @ 0x4c 8013794: 2b00 cmp r3, #0 8013796: d1e4 bne.n 8013762 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013798: 687b ldr r3, [r7, #4] 801379a: 6edb ldr r3, [r3, #108] @ 0x6c 801379c: 2b01 cmp r3, #1 801379e: d130 bne.n 8013802 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80137a0: 687b ldr r3, [r7, #4] 80137a2: 2200 movs r2, #0 80137a4: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80137a6: 687b ldr r3, [r7, #4] 80137a8: 681b ldr r3, [r3, #0] 80137aa: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80137ac: 6b7b ldr r3, [r7, #52] @ 0x34 80137ae: e853 3f00 ldrex r3, [r3] 80137b2: 633b str r3, [r7, #48] @ 0x30 return(result); 80137b4: 6b3b ldr r3, [r7, #48] @ 0x30 80137b6: f023 0310 bic.w r3, r3, #16 80137ba: f8c7 308c str.w r3, [r7, #140] @ 0x8c 80137be: 687b ldr r3, [r7, #4] 80137c0: 681b ldr r3, [r3, #0] 80137c2: 461a mov r2, r3 80137c4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 80137c8: 643b str r3, [r7, #64] @ 0x40 80137ca: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80137cc: 6bf9 ldr r1, [r7, #60] @ 0x3c 80137ce: 6c3a ldr r2, [r7, #64] @ 0x40 80137d0: e841 2300 strex r3, r2, [r1] 80137d4: 63bb str r3, [r7, #56] @ 0x38 return(result); 80137d6: 6bbb ldr r3, [r7, #56] @ 0x38 80137d8: 2b00 cmp r3, #0 80137da: d1e4 bne.n 80137a6 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 80137dc: 687b ldr r3, [r7, #4] 80137de: 681b ldr r3, [r3, #0] 80137e0: 69db ldr r3, [r3, #28] 80137e2: f003 0310 and.w r3, r3, #16 80137e6: 2b10 cmp r3, #16 80137e8: d103 bne.n 80137f2 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 80137ea: 687b ldr r3, [r7, #4] 80137ec: 681b ldr r3, [r3, #0] 80137ee: 2210 movs r2, #16 80137f0: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 80137f2: 687b ldr r3, [r7, #4] 80137f4: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 80137f8: 4619 mov r1, r3 80137fa: 6878 ldr r0, [r7, #4] 80137fc: f7f1 f962 bl 8004ac4 8013800: e002 b.n 8013808 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8013802: 6878 ldr r0, [r7, #4] 8013804: f7f1 f954 bl 8004ab0 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8013808: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e 801380c: 2b00 cmp r3, #0 801380e: d006 beq.n 801381e 8013810: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8013814: f003 0320 and.w r3, r3, #32 8013818: 2b00 cmp r3, #0 801381a: f47f aed1 bne.w 80135c0 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 801381e: 687b ldr r3, [r7, #4] 8013820: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013824: f8a7 308a strh.w r3, [r7, #138] @ 0x8a if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 8013828: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 801382c: 2b00 cmp r3, #0 801382e: d049 beq.n 80138c4 8013830: 687b ldr r3, [r7, #4] 8013832: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8013836: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a 801383a: 429a cmp r2, r3 801383c: d242 bcs.n 80138c4 { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 801383e: 687b ldr r3, [r7, #4] 8013840: 681b ldr r3, [r3, #0] 8013842: 3308 adds r3, #8 8013844: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013846: 6a3b ldr r3, [r7, #32] 8013848: e853 3f00 ldrex r3, [r3] 801384c: 61fb str r3, [r7, #28] return(result); 801384e: 69fb ldr r3, [r7, #28] 8013850: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8013854: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8013858: 687b ldr r3, [r7, #4] 801385a: 681b ldr r3, [r3, #0] 801385c: 3308 adds r3, #8 801385e: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 8013862: 62fa str r2, [r7, #44] @ 0x2c 8013864: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013866: 6ab9 ldr r1, [r7, #40] @ 0x28 8013868: 6afa ldr r2, [r7, #44] @ 0x2c 801386a: e841 2300 strex r3, r2, [r1] 801386e: 627b str r3, [r7, #36] @ 0x24 return(result); 8013870: 6a7b ldr r3, [r7, #36] @ 0x24 8013872: 2b00 cmp r3, #0 8013874: d1e3 bne.n 801383e /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; 8013876: 687b ldr r3, [r7, #4] 8013878: 4a16 ldr r2, [pc, #88] @ (80138d4 ) 801387a: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 801387c: 687b ldr r3, [r7, #4] 801387e: 681b ldr r3, [r3, #0] 8013880: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013882: 68fb ldr r3, [r7, #12] 8013884: e853 3f00 ldrex r3, [r3] 8013888: 60bb str r3, [r7, #8] return(result); 801388a: 68bb ldr r3, [r7, #8] 801388c: f043 0320 orr.w r3, r3, #32 8013890: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8013894: 687b ldr r3, [r7, #4] 8013896: 681b ldr r3, [r3, #0] 8013898: 461a mov r2, r3 801389a: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 801389e: 61bb str r3, [r7, #24] 80138a0: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80138a2: 6979 ldr r1, [r7, #20] 80138a4: 69ba ldr r2, [r7, #24] 80138a6: e841 2300 strex r3, r2, [r1] 80138aa: 613b str r3, [r7, #16] return(result); 80138ac: 693b ldr r3, [r7, #16] 80138ae: 2b00 cmp r3, #0 80138b0: d1e4 bne.n 801387c else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 80138b2: e007 b.n 80138c4 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 80138b4: 687b ldr r3, [r7, #4] 80138b6: 681b ldr r3, [r3, #0] 80138b8: 699a ldr r2, [r3, #24] 80138ba: 687b ldr r3, [r7, #4] 80138bc: 681b ldr r3, [r3, #0] 80138be: f042 0208 orr.w r2, r2, #8 80138c2: 619a str r2, [r3, #24] } 80138c4: bf00 nop 80138c6: 37b0 adds r7, #176 @ 0xb0 80138c8: 46bd mov sp, r7 80138ca: bd80 pop {r7, pc} 80138cc: effffffe .word 0xeffffffe 80138d0: 58000c00 .word 0x58000c00 80138d4: 08013209 .word 0x08013209 080138d8 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 80138d8: b580 push {r7, lr} 80138da: b0ae sub sp, #184 @ 0xb8 80138dc: af00 add r7, sp, #0 80138de: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 80138e0: 687b ldr r3, [r7, #4] 80138e2: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 80138e6: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2 uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 80138ea: 687b ldr r3, [r7, #4] 80138ec: 681b ldr r3, [r3, #0] 80138ee: 69db ldr r3, [r3, #28] 80138f0: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 80138f4: 687b ldr r3, [r7, #4] 80138f6: 681b ldr r3, [r3, #0] 80138f8: 681b ldr r3, [r3, #0] 80138fa: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr3its = READ_REG(huart->Instance->CR3); 80138fe: 687b ldr r3, [r7, #4] 8013900: 681b ldr r3, [r3, #0] 8013902: 689b ldr r3, [r3, #8] 8013904: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8013908: 687b ldr r3, [r7, #4] 801390a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 801390e: 2b22 cmp r3, #34 @ 0x22 8013910: f040 8184 bne.w 8013c1c { nb_rx_data = huart->NbRxDataToProcess; 8013914: 687b ldr r3, [r7, #4] 8013916: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 801391a: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 801391e: e127 b.n 8013b70 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8013920: 687b ldr r3, [r7, #4] 8013922: 681b ldr r3, [r3, #0] 8013924: 6a5b ldr r3, [r3, #36] @ 0x24 8013926: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4 tmp = (uint16_t *) huart->pRxBuffPtr ; 801392a: 687b ldr r3, [r7, #4] 801392c: 6d9b ldr r3, [r3, #88] @ 0x58 801392e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 *tmp = (uint16_t)(uhdata & uhMask); 8013932: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4 8013936: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2 801393a: 4013 ands r3, r2 801393c: b29a uxth r2, r3 801393e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8013942: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8013944: 687b ldr r3, [r7, #4] 8013946: 6d9b ldr r3, [r3, #88] @ 0x58 8013948: 1c9a adds r2, r3, #2 801394a: 687b ldr r3, [r7, #4] 801394c: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 801394e: 687b ldr r3, [r7, #4] 8013950: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013954: b29b uxth r3, r3 8013956: 3b01 subs r3, #1 8013958: b29a uxth r2, r3 801395a: 687b ldr r3, [r7, #4] 801395c: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 8013960: 687b ldr r3, [r7, #4] 8013962: 681b ldr r3, [r3, #0] 8013964: 69db ldr r3, [r3, #28] 8013966: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 801396a: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 801396e: f003 0307 and.w r3, r3, #7 8013972: 2b00 cmp r3, #0 8013974: d053 beq.n 8013a1e { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8013976: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 801397a: f003 0301 and.w r3, r3, #1 801397e: 2b00 cmp r3, #0 8013980: d011 beq.n 80139a6 8013982: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8013986: f403 7380 and.w r3, r3, #256 @ 0x100 801398a: 2b00 cmp r3, #0 801398c: d00b beq.n 80139a6 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 801398e: 687b ldr r3, [r7, #4] 8013990: 681b ldr r3, [r3, #0] 8013992: 2201 movs r2, #1 8013994: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8013996: 687b ldr r3, [r7, #4] 8013998: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 801399c: f043 0201 orr.w r2, r3, #1 80139a0: 687b ldr r3, [r7, #4] 80139a2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 80139a6: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 80139aa: f003 0302 and.w r3, r3, #2 80139ae: 2b00 cmp r3, #0 80139b0: d011 beq.n 80139d6 80139b2: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 80139b6: f003 0301 and.w r3, r3, #1 80139ba: 2b00 cmp r3, #0 80139bc: d00b beq.n 80139d6 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 80139be: 687b ldr r3, [r7, #4] 80139c0: 681b ldr r3, [r3, #0] 80139c2: 2202 movs r2, #2 80139c4: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 80139c6: 687b ldr r3, [r7, #4] 80139c8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80139cc: f043 0204 orr.w r2, r3, #4 80139d0: 687b ldr r3, [r7, #4] 80139d2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 80139d6: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 80139da: f003 0304 and.w r3, r3, #4 80139de: 2b00 cmp r3, #0 80139e0: d011 beq.n 8013a06 80139e2: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 80139e6: f003 0301 and.w r3, r3, #1 80139ea: 2b00 cmp r3, #0 80139ec: d00b beq.n 8013a06 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 80139ee: 687b ldr r3, [r7, #4] 80139f0: 681b ldr r3, [r3, #0] 80139f2: 2204 movs r2, #4 80139f4: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 80139f6: 687b ldr r3, [r7, #4] 80139f8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80139fc: f043 0202 orr.w r2, r3, #2 8013a00: 687b ldr r3, [r7, #4] 8013a02: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8013a06: 687b ldr r3, [r7, #4] 8013a08: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013a0c: 2b00 cmp r3, #0 8013a0e: d006 beq.n 8013a1e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013a10: 6878 ldr r0, [r7, #4] 8013a12: f7fe f961 bl 8011cd8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8013a16: 687b ldr r3, [r7, #4] 8013a18: 2200 movs r2, #0 8013a1a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 8013a1e: 687b ldr r3, [r7, #4] 8013a20: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013a24: b29b uxth r3, r3 8013a26: 2b00 cmp r3, #0 8013a28: f040 80a2 bne.w 8013b70 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8013a2c: 687b ldr r3, [r7, #4] 8013a2e: 681b ldr r3, [r3, #0] 8013a30: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013a32: 6f7b ldr r3, [r7, #116] @ 0x74 8013a34: e853 3f00 ldrex r3, [r3] 8013a38: 673b str r3, [r7, #112] @ 0x70 return(result); 8013a3a: 6f3b ldr r3, [r7, #112] @ 0x70 8013a3c: f423 7380 bic.w r3, r3, #256 @ 0x100 8013a40: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8013a44: 687b ldr r3, [r7, #4] 8013a46: 681b ldr r3, [r3, #0] 8013a48: 461a mov r2, r3 8013a4a: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8013a4e: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8013a52: 67fa str r2, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013a54: 6ff9 ldr r1, [r7, #124] @ 0x7c 8013a56: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8013a5a: e841 2300 strex r3, r2, [r1] 8013a5e: 67bb str r3, [r7, #120] @ 0x78 return(result); 8013a60: 6fbb ldr r3, [r7, #120] @ 0x78 8013a62: 2b00 cmp r3, #0 8013a64: d1e2 bne.n 8013a2c /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8013a66: 687b ldr r3, [r7, #4] 8013a68: 681b ldr r3, [r3, #0] 8013a6a: 3308 adds r3, #8 8013a6c: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013a6e: 6e3b ldr r3, [r7, #96] @ 0x60 8013a70: e853 3f00 ldrex r3, [r3] 8013a74: 65fb str r3, [r7, #92] @ 0x5c return(result); 8013a76: 6dfa ldr r2, [r7, #92] @ 0x5c 8013a78: 4b6e ldr r3, [pc, #440] @ (8013c34 ) 8013a7a: 4013 ands r3, r2 8013a7c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8013a80: 687b ldr r3, [r7, #4] 8013a82: 681b ldr r3, [r3, #0] 8013a84: 3308 adds r3, #8 8013a86: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98 8013a8a: 66fa str r2, [r7, #108] @ 0x6c 8013a8c: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013a8e: 6eb9 ldr r1, [r7, #104] @ 0x68 8013a90: 6efa ldr r2, [r7, #108] @ 0x6c 8013a92: e841 2300 strex r3, r2, [r1] 8013a96: 667b str r3, [r7, #100] @ 0x64 return(result); 8013a98: 6e7b ldr r3, [r7, #100] @ 0x64 8013a9a: 2b00 cmp r3, #0 8013a9c: d1e3 bne.n 8013a66 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013a9e: 687b ldr r3, [r7, #4] 8013aa0: 2220 movs r2, #32 8013aa2: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8013aa6: 687b ldr r3, [r7, #4] 8013aa8: 2200 movs r2, #0 8013aaa: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8013aac: 687b ldr r3, [r7, #4] 8013aae: 2200 movs r2, #0 8013ab0: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8013ab2: 687b ldr r3, [r7, #4] 8013ab4: 681b ldr r3, [r3, #0] 8013ab6: 4a60 ldr r2, [pc, #384] @ (8013c38 ) 8013ab8: 4293 cmp r3, r2 8013aba: d021 beq.n 8013b00 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8013abc: 687b ldr r3, [r7, #4] 8013abe: 681b ldr r3, [r3, #0] 8013ac0: 685b ldr r3, [r3, #4] 8013ac2: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8013ac6: 2b00 cmp r3, #0 8013ac8: d01a beq.n 8013b00 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8013aca: 687b ldr r3, [r7, #4] 8013acc: 681b ldr r3, [r3, #0] 8013ace: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013ad0: 6cfb ldr r3, [r7, #76] @ 0x4c 8013ad2: e853 3f00 ldrex r3, [r3] 8013ad6: 64bb str r3, [r7, #72] @ 0x48 return(result); 8013ad8: 6cbb ldr r3, [r7, #72] @ 0x48 8013ada: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8013ade: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8013ae2: 687b ldr r3, [r7, #4] 8013ae4: 681b ldr r3, [r3, #0] 8013ae6: 461a mov r2, r3 8013ae8: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 8013aec: 65bb str r3, [r7, #88] @ 0x58 8013aee: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013af0: 6d79 ldr r1, [r7, #84] @ 0x54 8013af2: 6dba ldr r2, [r7, #88] @ 0x58 8013af4: e841 2300 strex r3, r2, [r1] 8013af8: 653b str r3, [r7, #80] @ 0x50 return(result); 8013afa: 6d3b ldr r3, [r7, #80] @ 0x50 8013afc: 2b00 cmp r3, #0 8013afe: d1e4 bne.n 8013aca } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013b00: 687b ldr r3, [r7, #4] 8013b02: 6edb ldr r3, [r3, #108] @ 0x6c 8013b04: 2b01 cmp r3, #1 8013b06: d130 bne.n 8013b6a { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013b08: 687b ldr r3, [r7, #4] 8013b0a: 2200 movs r2, #0 8013b0c: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013b0e: 687b ldr r3, [r7, #4] 8013b10: 681b ldr r3, [r3, #0] 8013b12: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013b14: 6bbb ldr r3, [r7, #56] @ 0x38 8013b16: e853 3f00 ldrex r3, [r3] 8013b1a: 637b str r3, [r7, #52] @ 0x34 return(result); 8013b1c: 6b7b ldr r3, [r7, #52] @ 0x34 8013b1e: f023 0310 bic.w r3, r3, #16 8013b22: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8013b26: 687b ldr r3, [r7, #4] 8013b28: 681b ldr r3, [r3, #0] 8013b2a: 461a mov r2, r3 8013b2c: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8013b30: 647b str r3, [r7, #68] @ 0x44 8013b32: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013b34: 6c39 ldr r1, [r7, #64] @ 0x40 8013b36: 6c7a ldr r2, [r7, #68] @ 0x44 8013b38: e841 2300 strex r3, r2, [r1] 8013b3c: 63fb str r3, [r7, #60] @ 0x3c return(result); 8013b3e: 6bfb ldr r3, [r7, #60] @ 0x3c 8013b40: 2b00 cmp r3, #0 8013b42: d1e4 bne.n 8013b0e if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8013b44: 687b ldr r3, [r7, #4] 8013b46: 681b ldr r3, [r3, #0] 8013b48: 69db ldr r3, [r3, #28] 8013b4a: f003 0310 and.w r3, r3, #16 8013b4e: 2b10 cmp r3, #16 8013b50: d103 bne.n 8013b5a { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8013b52: 687b ldr r3, [r7, #4] 8013b54: 681b ldr r3, [r3, #0] 8013b56: 2210 movs r2, #16 8013b58: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8013b5a: 687b ldr r3, [r7, #4] 8013b5c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8013b60: 4619 mov r1, r3 8013b62: 6878 ldr r0, [r7, #4] 8013b64: f7f0 ffae bl 8004ac4 8013b68: e002 b.n 8013b70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8013b6a: 6878 ldr r0, [r7, #4] 8013b6c: f7f0 ffa0 bl 8004ab0 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8013b70: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6 8013b74: 2b00 cmp r3, #0 8013b76: d006 beq.n 8013b86 8013b78: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8013b7c: f003 0320 and.w r3, r3, #32 8013b80: 2b00 cmp r3, #0 8013b82: f47f aecd bne.w 8013920 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 8013b86: 687b ldr r3, [r7, #4] 8013b88: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013b8c: f8a7 308e strh.w r3, [r7, #142] @ 0x8e if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 8013b90: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e 8013b94: 2b00 cmp r3, #0 8013b96: d049 beq.n 8013c2c 8013b98: 687b ldr r3, [r7, #4] 8013b9a: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8013b9e: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e 8013ba2: 429a cmp r2, r3 8013ba4: d242 bcs.n 8013c2c { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8013ba6: 687b ldr r3, [r7, #4] 8013ba8: 681b ldr r3, [r3, #0] 8013baa: 3308 adds r3, #8 8013bac: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013bae: 6a7b ldr r3, [r7, #36] @ 0x24 8013bb0: e853 3f00 ldrex r3, [r3] 8013bb4: 623b str r3, [r7, #32] return(result); 8013bb6: 6a3b ldr r3, [r7, #32] 8013bb8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8013bbc: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8013bc0: 687b ldr r3, [r7, #4] 8013bc2: 681b ldr r3, [r3, #0] 8013bc4: 3308 adds r3, #8 8013bc6: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88 8013bca: 633a str r2, [r7, #48] @ 0x30 8013bcc: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013bce: 6af9 ldr r1, [r7, #44] @ 0x2c 8013bd0: 6b3a ldr r2, [r7, #48] @ 0x30 8013bd2: e841 2300 strex r3, r2, [r1] 8013bd6: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013bd8: 6abb ldr r3, [r7, #40] @ 0x28 8013bda: 2b00 cmp r3, #0 8013bdc: d1e3 bne.n 8013ba6 /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; 8013bde: 687b ldr r3, [r7, #4] 8013be0: 4a16 ldr r2, [pc, #88] @ (8013c3c ) 8013be2: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8013be4: 687b ldr r3, [r7, #4] 8013be6: 681b ldr r3, [r3, #0] 8013be8: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013bea: 693b ldr r3, [r7, #16] 8013bec: e853 3f00 ldrex r3, [r3] 8013bf0: 60fb str r3, [r7, #12] return(result); 8013bf2: 68fb ldr r3, [r7, #12] 8013bf4: f043 0320 orr.w r3, r3, #32 8013bf8: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8013bfc: 687b ldr r3, [r7, #4] 8013bfe: 681b ldr r3, [r3, #0] 8013c00: 461a mov r2, r3 8013c02: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8013c06: 61fb str r3, [r7, #28] 8013c08: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013c0a: 69b9 ldr r1, [r7, #24] 8013c0c: 69fa ldr r2, [r7, #28] 8013c0e: e841 2300 strex r3, r2, [r1] 8013c12: 617b str r3, [r7, #20] return(result); 8013c14: 697b ldr r3, [r7, #20] 8013c16: 2b00 cmp r3, #0 8013c18: d1e4 bne.n 8013be4 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8013c1a: e007 b.n 8013c2c __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8013c1c: 687b ldr r3, [r7, #4] 8013c1e: 681b ldr r3, [r3, #0] 8013c20: 699a ldr r2, [r3, #24] 8013c22: 687b ldr r3, [r7, #4] 8013c24: 681b ldr r3, [r3, #0] 8013c26: f042 0208 orr.w r2, r2, #8 8013c2a: 619a str r2, [r3, #24] } 8013c2c: bf00 nop 8013c2e: 37b8 adds r7, #184 @ 0xb8 8013c30: 46bd mov sp, r7 8013c32: bd80 pop {r7, pc} 8013c34: effffffe .word 0xeffffffe 8013c38: 58000c00 .word 0x58000c00 8013c3c: 080133c1 .word 0x080133c1 08013c40 : * @brief UART wakeup from Stop mode callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { 8013c40: b480 push {r7} 8013c42: b083 sub sp, #12 8013c44: af00 add r7, sp, #0 8013c46: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } 8013c48: bf00 nop 8013c4a: 370c adds r7, #12 8013c4c: 46bd mov sp, r7 8013c4e: f85d 7b04 ldr.w r7, [sp], #4 8013c52: 4770 bx lr 08013c54 : * @brief UART RX Fifo full callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { 8013c54: b480 push {r7} 8013c56: b083 sub sp, #12 8013c58: af00 add r7, sp, #0 8013c5a: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. */ } 8013c5c: bf00 nop 8013c5e: 370c adds r7, #12 8013c60: 46bd mov sp, r7 8013c62: f85d 7b04 ldr.w r7, [sp], #4 8013c66: 4770 bx lr 08013c68 : * @brief UART TX Fifo empty callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { 8013c68: b480 push {r7} 8013c6a: b083 sub sp, #12 8013c6c: af00 add r7, sp, #0 8013c6e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } 8013c70: bf00 nop 8013c72: 370c adds r7, #12 8013c74: 46bd mov sp, r7 8013c76: f85d 7b04 ldr.w r7, [sp], #4 8013c7a: 4770 bx lr 08013c7c : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 8013c7c: b480 push {r7} 8013c7e: b085 sub sp, #20 8013c80: af00 add r7, sp, #0 8013c82: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 8013c84: 687b ldr r3, [r7, #4] 8013c86: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8013c8a: 2b01 cmp r3, #1 8013c8c: d101 bne.n 8013c92 8013c8e: 2302 movs r3, #2 8013c90: e027 b.n 8013ce2 8013c92: 687b ldr r3, [r7, #4] 8013c94: 2201 movs r2, #1 8013c96: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8013c9a: 687b ldr r3, [r7, #4] 8013c9c: 2224 movs r2, #36 @ 0x24 8013c9e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8013ca2: 687b ldr r3, [r7, #4] 8013ca4: 681b ldr r3, [r3, #0] 8013ca6: 681b ldr r3, [r3, #0] 8013ca8: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8013caa: 687b ldr r3, [r7, #4] 8013cac: 681b ldr r3, [r3, #0] 8013cae: 681a ldr r2, [r3, #0] 8013cb0: 687b ldr r3, [r7, #4] 8013cb2: 681b ldr r3, [r3, #0] 8013cb4: f022 0201 bic.w r2, r2, #1 8013cb8: 601a str r2, [r3, #0] /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 8013cba: 68fb ldr r3, [r7, #12] 8013cbc: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000 8013cc0: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 8013cc2: 687b ldr r3, [r7, #4] 8013cc4: 2200 movs r2, #0 8013cc6: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8013cc8: 687b ldr r3, [r7, #4] 8013cca: 681b ldr r3, [r3, #0] 8013ccc: 68fa ldr r2, [r7, #12] 8013cce: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8013cd0: 687b ldr r3, [r7, #4] 8013cd2: 2220 movs r2, #32 8013cd4: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8013cd8: 687b ldr r3, [r7, #4] 8013cda: 2200 movs r2, #0 8013cdc: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8013ce0: 2300 movs r3, #0 } 8013ce2: 4618 mov r0, r3 8013ce4: 3714 adds r7, #20 8013ce6: 46bd mov sp, r7 8013ce8: f85d 7b04 ldr.w r7, [sp], #4 8013cec: 4770 bx lr 08013cee : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8013cee: b580 push {r7, lr} 8013cf0: b084 sub sp, #16 8013cf2: af00 add r7, sp, #0 8013cf4: 6078 str r0, [r7, #4] 8013cf6: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8013cf8: 687b ldr r3, [r7, #4] 8013cfa: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8013cfe: 2b01 cmp r3, #1 8013d00: d101 bne.n 8013d06 8013d02: 2302 movs r3, #2 8013d04: e02d b.n 8013d62 8013d06: 687b ldr r3, [r7, #4] 8013d08: 2201 movs r2, #1 8013d0a: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8013d0e: 687b ldr r3, [r7, #4] 8013d10: 2224 movs r2, #36 @ 0x24 8013d12: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8013d16: 687b ldr r3, [r7, #4] 8013d18: 681b ldr r3, [r3, #0] 8013d1a: 681b ldr r3, [r3, #0] 8013d1c: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8013d1e: 687b ldr r3, [r7, #4] 8013d20: 681b ldr r3, [r3, #0] 8013d22: 681a ldr r2, [r3, #0] 8013d24: 687b ldr r3, [r7, #4] 8013d26: 681b ldr r3, [r3, #0] 8013d28: f022 0201 bic.w r2, r2, #1 8013d2c: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 8013d2e: 687b ldr r3, [r7, #4] 8013d30: 681b ldr r3, [r3, #0] 8013d32: 689b ldr r3, [r3, #8] 8013d34: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 8013d38: 687b ldr r3, [r7, #4] 8013d3a: 681b ldr r3, [r3, #0] 8013d3c: 683a ldr r2, [r7, #0] 8013d3e: 430a orrs r2, r1 8013d40: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8013d42: 6878 ldr r0, [r7, #4] 8013d44: f000 f8a0 bl 8013e88 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8013d48: 687b ldr r3, [r7, #4] 8013d4a: 681b ldr r3, [r3, #0] 8013d4c: 68fa ldr r2, [r7, #12] 8013d4e: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8013d50: 687b ldr r3, [r7, #4] 8013d52: 2220 movs r2, #32 8013d54: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8013d58: 687b ldr r3, [r7, #4] 8013d5a: 2200 movs r2, #0 8013d5c: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8013d60: 2300 movs r3, #0 } 8013d62: 4618 mov r0, r3 8013d64: 3710 adds r7, #16 8013d66: 46bd mov sp, r7 8013d68: bd80 pop {r7, pc} 08013d6a : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8013d6a: b580 push {r7, lr} 8013d6c: b084 sub sp, #16 8013d6e: af00 add r7, sp, #0 8013d70: 6078 str r0, [r7, #4] 8013d72: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8013d74: 687b ldr r3, [r7, #4] 8013d76: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8013d7a: 2b01 cmp r3, #1 8013d7c: d101 bne.n 8013d82 8013d7e: 2302 movs r3, #2 8013d80: e02d b.n 8013dde 8013d82: 687b ldr r3, [r7, #4] 8013d84: 2201 movs r2, #1 8013d86: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8013d8a: 687b ldr r3, [r7, #4] 8013d8c: 2224 movs r2, #36 @ 0x24 8013d8e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8013d92: 687b ldr r3, [r7, #4] 8013d94: 681b ldr r3, [r3, #0] 8013d96: 681b ldr r3, [r3, #0] 8013d98: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8013d9a: 687b ldr r3, [r7, #4] 8013d9c: 681b ldr r3, [r3, #0] 8013d9e: 681a ldr r2, [r3, #0] 8013da0: 687b ldr r3, [r7, #4] 8013da2: 681b ldr r3, [r3, #0] 8013da4: f022 0201 bic.w r2, r2, #1 8013da8: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 8013daa: 687b ldr r3, [r7, #4] 8013dac: 681b ldr r3, [r3, #0] 8013dae: 689b ldr r3, [r3, #8] 8013db0: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 8013db4: 687b ldr r3, [r7, #4] 8013db6: 681b ldr r3, [r3, #0] 8013db8: 683a ldr r2, [r7, #0] 8013dba: 430a orrs r2, r1 8013dbc: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8013dbe: 6878 ldr r0, [r7, #4] 8013dc0: f000 f862 bl 8013e88 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8013dc4: 687b ldr r3, [r7, #4] 8013dc6: 681b ldr r3, [r3, #0] 8013dc8: 68fa ldr r2, [r7, #12] 8013dca: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8013dcc: 687b ldr r3, [r7, #4] 8013dce: 2220 movs r2, #32 8013dd0: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8013dd4: 687b ldr r3, [r7, #4] 8013dd6: 2200 movs r2, #0 8013dd8: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8013ddc: 2300 movs r3, #0 } 8013dde: 4618 mov r0, r3 8013de0: 3710 adds r7, #16 8013de2: 46bd mov sp, r7 8013de4: bd80 pop {r7, pc} 08013de6 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8013de6: b580 push {r7, lr} 8013de8: b08c sub sp, #48 @ 0x30 8013dea: af00 add r7, sp, #0 8013dec: 60f8 str r0, [r7, #12] 8013dee: 60b9 str r1, [r7, #8] 8013df0: 4613 mov r3, r2 8013df2: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status = HAL_OK; 8013df4: 2300 movs r3, #0 8013df6: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8013dfa: 68fb ldr r3, [r7, #12] 8013dfc: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8013e00: 2b20 cmp r3, #32 8013e02: d13b bne.n 8013e7c { if ((pData == NULL) || (Size == 0U)) 8013e04: 68bb ldr r3, [r7, #8] 8013e06: 2b00 cmp r3, #0 8013e08: d002 beq.n 8013e10 8013e0a: 88fb ldrh r3, [r7, #6] 8013e0c: 2b00 cmp r3, #0 8013e0e: d101 bne.n 8013e14 { return HAL_ERROR; 8013e10: 2301 movs r3, #1 8013e12: e034 b.n 8013e7e } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8013e14: 68fb ldr r3, [r7, #12] 8013e16: 2201 movs r2, #1 8013e18: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8013e1a: 68fb ldr r3, [r7, #12] 8013e1c: 2200 movs r2, #0 8013e1e: 671a str r2, [r3, #112] @ 0x70 (void)UART_Start_Receive_IT(huart, pData, Size); 8013e20: 88fb ldrh r3, [r7, #6] 8013e22: 461a mov r2, r3 8013e24: 68b9 ldr r1, [r7, #8] 8013e26: 68f8 ldr r0, [r7, #12] 8013e28: f7fe fe82 bl 8012b30 if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013e2c: 68fb ldr r3, [r7, #12] 8013e2e: 6edb ldr r3, [r3, #108] @ 0x6c 8013e30: 2b01 cmp r3, #1 8013e32: d11d bne.n 8013e70 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8013e34: 68fb ldr r3, [r7, #12] 8013e36: 681b ldr r3, [r3, #0] 8013e38: 2210 movs r2, #16 8013e3a: 621a str r2, [r3, #32] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013e3c: 68fb ldr r3, [r7, #12] 8013e3e: 681b ldr r3, [r3, #0] 8013e40: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013e42: 69bb ldr r3, [r7, #24] 8013e44: e853 3f00 ldrex r3, [r3] 8013e48: 617b str r3, [r7, #20] return(result); 8013e4a: 697b ldr r3, [r7, #20] 8013e4c: f043 0310 orr.w r3, r3, #16 8013e50: 62bb str r3, [r7, #40] @ 0x28 8013e52: 68fb ldr r3, [r7, #12] 8013e54: 681b ldr r3, [r3, #0] 8013e56: 461a mov r2, r3 8013e58: 6abb ldr r3, [r7, #40] @ 0x28 8013e5a: 627b str r3, [r7, #36] @ 0x24 8013e5c: 623a str r2, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013e5e: 6a39 ldr r1, [r7, #32] 8013e60: 6a7a ldr r2, [r7, #36] @ 0x24 8013e62: e841 2300 strex r3, r2, [r1] 8013e66: 61fb str r3, [r7, #28] return(result); 8013e68: 69fb ldr r3, [r7, #28] 8013e6a: 2b00 cmp r3, #0 8013e6c: d1e6 bne.n 8013e3c 8013e6e: e002 b.n 8013e76 { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8013e70: 2301 movs r3, #1 8013e72: f887 302f strb.w r3, [r7, #47] @ 0x2f } return status; 8013e76: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8013e7a: e000 b.n 8013e7e } else { return HAL_BUSY; 8013e7c: 2302 movs r3, #2 } } 8013e7e: 4618 mov r0, r3 8013e80: 3730 adds r7, #48 @ 0x30 8013e82: 46bd mov sp, r7 8013e84: bd80 pop {r7, pc} ... 08013e88 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 8013e88: b480 push {r7} 8013e8a: b085 sub sp, #20 8013e8c: af00 add r7, sp, #0 8013e8e: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 8013e90: 687b ldr r3, [r7, #4] 8013e92: 6e5b ldr r3, [r3, #100] @ 0x64 8013e94: 2b00 cmp r3, #0 8013e96: d108 bne.n 8013eaa { huart->NbTxDataToProcess = 1U; 8013e98: 687b ldr r3, [r7, #4] 8013e9a: 2201 movs r2, #1 8013e9c: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1U; 8013ea0: 687b ldr r3, [r7, #4] 8013ea2: 2201 movs r2, #1 8013ea4: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 8013ea8: e031 b.n 8013f0e rx_fifo_depth = RX_FIFO_DEPTH; 8013eaa: 2310 movs r3, #16 8013eac: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 8013eae: 2310 movs r3, #16 8013eb0: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 8013eb2: 687b ldr r3, [r7, #4] 8013eb4: 681b ldr r3, [r3, #0] 8013eb6: 689b ldr r3, [r3, #8] 8013eb8: 0e5b lsrs r3, r3, #25 8013eba: b2db uxtb r3, r3 8013ebc: f003 0307 and.w r3, r3, #7 8013ec0: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 8013ec2: 687b ldr r3, [r7, #4] 8013ec4: 681b ldr r3, [r3, #0] 8013ec6: 689b ldr r3, [r3, #8] 8013ec8: 0f5b lsrs r3, r3, #29 8013eca: b2db uxtb r3, r3 8013ecc: f003 0307 and.w r3, r3, #7 8013ed0: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8013ed2: 7bbb ldrb r3, [r7, #14] 8013ed4: 7b3a ldrb r2, [r7, #12] 8013ed6: 4911 ldr r1, [pc, #68] @ (8013f1c ) 8013ed8: 5c8a ldrb r2, [r1, r2] 8013eda: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 8013ede: 7b3a ldrb r2, [r7, #12] 8013ee0: 490f ldr r1, [pc, #60] @ (8013f20 ) 8013ee2: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8013ee4: fb93 f3f2 sdiv r3, r3, r2 8013ee8: b29a uxth r2, r3 8013eea: 687b ldr r3, [r7, #4] 8013eec: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8013ef0: 7bfb ldrb r3, [r7, #15] 8013ef2: 7b7a ldrb r2, [r7, #13] 8013ef4: 4909 ldr r1, [pc, #36] @ (8013f1c ) 8013ef6: 5c8a ldrb r2, [r1, r2] 8013ef8: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 8013efc: 7b7a ldrb r2, [r7, #13] 8013efe: 4908 ldr r1, [pc, #32] @ (8013f20 ) 8013f00: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8013f02: fb93 f3f2 sdiv r3, r3, r2 8013f06: b29a uxth r2, r3 8013f08: 687b ldr r3, [r7, #4] 8013f0a: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 } 8013f0e: bf00 nop 8013f10: 3714 adds r7, #20 8013f12: 46bd mov sp, r7 8013f14: f85d 7b04 ldr.w r7, [sp], #4 8013f18: 4770 bx lr 8013f1a: bf00 nop 8013f1c: 0801870c .word 0x0801870c 8013f20: 08018714 .word 0x08018714 08013f24 <__NVIC_SetPriority>: { 8013f24: b480 push {r7} 8013f26: b083 sub sp, #12 8013f28: af00 add r7, sp, #0 8013f2a: 4603 mov r3, r0 8013f2c: 6039 str r1, [r7, #0] 8013f2e: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8013f30: f9b7 3006 ldrsh.w r3, [r7, #6] 8013f34: 2b00 cmp r3, #0 8013f36: db0a blt.n 8013f4e <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8013f38: 683b ldr r3, [r7, #0] 8013f3a: b2da uxtb r2, r3 8013f3c: 490c ldr r1, [pc, #48] @ (8013f70 <__NVIC_SetPriority+0x4c>) 8013f3e: f9b7 3006 ldrsh.w r3, [r7, #6] 8013f42: 0112 lsls r2, r2, #4 8013f44: b2d2 uxtb r2, r2 8013f46: 440b add r3, r1 8013f48: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 8013f4c: e00a b.n 8013f64 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8013f4e: 683b ldr r3, [r7, #0] 8013f50: b2da uxtb r2, r3 8013f52: 4908 ldr r1, [pc, #32] @ (8013f74 <__NVIC_SetPriority+0x50>) 8013f54: 88fb ldrh r3, [r7, #6] 8013f56: f003 030f and.w r3, r3, #15 8013f5a: 3b04 subs r3, #4 8013f5c: 0112 lsls r2, r2, #4 8013f5e: b2d2 uxtb r2, r2 8013f60: 440b add r3, r1 8013f62: 761a strb r2, [r3, #24] } 8013f64: bf00 nop 8013f66: 370c adds r7, #12 8013f68: 46bd mov sp, r7 8013f6a: f85d 7b04 ldr.w r7, [sp], #4 8013f6e: 4770 bx lr 8013f70: e000e100 .word 0xe000e100 8013f74: e000ed00 .word 0xe000ed00 08013f78 : /* SysTick handler implementation that also clears overflow flag. */ #if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) void SysTick_Handler (void) { 8013f78: b580 push {r7, lr} 8013f7a: af00 add r7, sp, #0 /* Clear overflow flag */ SysTick->CTRL; 8013f7c: 4b05 ldr r3, [pc, #20] @ (8013f94 ) 8013f7e: 681b ldr r3, [r3, #0] if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { 8013f80: f002 fd1e bl 80169c0 8013f84: 4603 mov r3, r0 8013f86: 2b01 cmp r3, #1 8013f88: d001 beq.n 8013f8e /* Call tick handler */ xPortSysTickHandler(); 8013f8a: f003 ff2d bl 8017de8 } } 8013f8e: bf00 nop 8013f90: bd80 pop {r7, pc} 8013f92: bf00 nop 8013f94: e000e010 .word 0xe000e010 08013f98 : #endif /* SysTick */ /* Setup SVC to reset value. */ __STATIC_INLINE void SVC_Setup (void) { 8013f98: b580 push {r7, lr} 8013f9a: af00 add r7, sp, #0 #if (__ARM_ARCH_7A__ == 0U) /* Service Call interrupt might be configured before kernel start */ /* and when its priority is lower or equal to BASEPRI, svc intruction */ /* causes a Hard Fault. */ NVIC_SetPriority (SVCall_IRQ_NBR, 0U); 8013f9c: 2100 movs r1, #0 8013f9e: f06f 0004 mvn.w r0, #4 8013fa2: f7ff ffbf bl 8013f24 <__NVIC_SetPriority> #endif } 8013fa6: bf00 nop 8013fa8: bd80 pop {r7, pc} ... 08013fac : static uint32_t OS_Tick_GetOverflow (void); /* Get OS Tick interval */ static uint32_t OS_Tick_GetInterval (void); /*---------------------------------------------------------------------------*/ osStatus_t osKernelInitialize (void) { 8013fac: b480 push {r7} 8013fae: b083 sub sp, #12 8013fb0: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013fb2: f3ef 8305 mrs r3, IPSR 8013fb6: 603b str r3, [r7, #0] return(result); 8013fb8: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 8013fba: 2b00 cmp r3, #0 8013fbc: d003 beq.n 8013fc6 stat = osErrorISR; 8013fbe: f06f 0305 mvn.w r3, #5 8013fc2: 607b str r3, [r7, #4] 8013fc4: e00c b.n 8013fe0 } else { if (KernelState == osKernelInactive) { 8013fc6: 4b0a ldr r3, [pc, #40] @ (8013ff0 ) 8013fc8: 681b ldr r3, [r3, #0] 8013fca: 2b00 cmp r3, #0 8013fcc: d105 bne.n 8013fda EvrFreeRTOSSetup(0U); #endif #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) vPortDefineHeapRegions (configHEAP_5_REGIONS); #endif KernelState = osKernelReady; 8013fce: 4b08 ldr r3, [pc, #32] @ (8013ff0 ) 8013fd0: 2201 movs r2, #1 8013fd2: 601a str r2, [r3, #0] stat = osOK; 8013fd4: 2300 movs r3, #0 8013fd6: 607b str r3, [r7, #4] 8013fd8: e002 b.n 8013fe0 } else { stat = osError; 8013fda: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8013fde: 607b str r3, [r7, #4] } } return (stat); 8013fe0: 687b ldr r3, [r7, #4] } 8013fe2: 4618 mov r0, r3 8013fe4: 370c adds r7, #12 8013fe6: 46bd mov sp, r7 8013fe8: f85d 7b04 ldr.w r7, [sp], #4 8013fec: 4770 bx lr 8013fee: bf00 nop 8013ff0: 24001064 .word 0x24001064 08013ff4 : } return (state); } osStatus_t osKernelStart (void) { 8013ff4: b580 push {r7, lr} 8013ff6: b082 sub sp, #8 8013ff8: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013ffa: f3ef 8305 mrs r3, IPSR 8013ffe: 603b str r3, [r7, #0] return(result); 8014000: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 8014002: 2b00 cmp r3, #0 8014004: d003 beq.n 801400e stat = osErrorISR; 8014006: f06f 0305 mvn.w r3, #5 801400a: 607b str r3, [r7, #4] 801400c: e010 b.n 8014030 } else { if (KernelState == osKernelReady) { 801400e: 4b0b ldr r3, [pc, #44] @ (801403c ) 8014010: 681b ldr r3, [r3, #0] 8014012: 2b01 cmp r3, #1 8014014: d109 bne.n 801402a /* Ensure SVC priority is at the reset value */ SVC_Setup(); 8014016: f7ff ffbf bl 8013f98 /* Change state to enable IRQ masking check */ KernelState = osKernelRunning; 801401a: 4b08 ldr r3, [pc, #32] @ (801403c ) 801401c: 2202 movs r2, #2 801401e: 601a str r2, [r3, #0] /* Start the kernel scheduler */ vTaskStartScheduler(); 8014020: f002 f824 bl 801606c stat = osOK; 8014024: 2300 movs r3, #0 8014026: 607b str r3, [r7, #4] 8014028: e002 b.n 8014030 } else { stat = osError; 801402a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801402e: 607b str r3, [r7, #4] } } return (stat); 8014030: 687b ldr r3, [r7, #4] } 8014032: 4618 mov r0, r3 8014034: 3708 adds r7, #8 8014036: 46bd mov sp, r7 8014038: bd80 pop {r7, pc} 801403a: bf00 nop 801403c: 24001064 .word 0x24001064 08014040 : return (configCPU_CLOCK_HZ); } /*---------------------------------------------------------------------------*/ osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { 8014040: b580 push {r7, lr} 8014042: b08e sub sp, #56 @ 0x38 8014044: af04 add r7, sp, #16 8014046: 60f8 str r0, [r7, #12] 8014048: 60b9 str r1, [r7, #8] 801404a: 607a str r2, [r7, #4] uint32_t stack; TaskHandle_t hTask; UBaseType_t prio; int32_t mem; hTask = NULL; 801404c: 2300 movs r3, #0 801404e: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014050: f3ef 8305 mrs r3, IPSR 8014054: 617b str r3, [r7, #20] return(result); 8014056: 697b ldr r3, [r7, #20] if (!IS_IRQ() && (func != NULL)) { 8014058: 2b00 cmp r3, #0 801405a: d17f bne.n 801415c 801405c: 68fb ldr r3, [r7, #12] 801405e: 2b00 cmp r3, #0 8014060: d07c beq.n 801415c stack = configMINIMAL_STACK_SIZE; 8014062: f44f 7300 mov.w r3, #512 @ 0x200 8014066: 623b str r3, [r7, #32] prio = (UBaseType_t)osPriorityNormal; 8014068: 2318 movs r3, #24 801406a: 61fb str r3, [r7, #28] name = NULL; 801406c: 2300 movs r3, #0 801406e: 627b str r3, [r7, #36] @ 0x24 mem = -1; 8014070: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8014074: 61bb str r3, [r7, #24] if (attr != NULL) { 8014076: 687b ldr r3, [r7, #4] 8014078: 2b00 cmp r3, #0 801407a: d045 beq.n 8014108 if (attr->name != NULL) { 801407c: 687b ldr r3, [r7, #4] 801407e: 681b ldr r3, [r3, #0] 8014080: 2b00 cmp r3, #0 8014082: d002 beq.n 801408a name = attr->name; 8014084: 687b ldr r3, [r7, #4] 8014086: 681b ldr r3, [r3, #0] 8014088: 627b str r3, [r7, #36] @ 0x24 } if (attr->priority != osPriorityNone) { 801408a: 687b ldr r3, [r7, #4] 801408c: 699b ldr r3, [r3, #24] 801408e: 2b00 cmp r3, #0 8014090: d002 beq.n 8014098 prio = (UBaseType_t)attr->priority; 8014092: 687b ldr r3, [r7, #4] 8014094: 699b ldr r3, [r3, #24] 8014096: 61fb str r3, [r7, #28] } if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { 8014098: 69fb ldr r3, [r7, #28] 801409a: 2b00 cmp r3, #0 801409c: d008 beq.n 80140b0 801409e: 69fb ldr r3, [r7, #28] 80140a0: 2b38 cmp r3, #56 @ 0x38 80140a2: d805 bhi.n 80140b0 80140a4: 687b ldr r3, [r7, #4] 80140a6: 685b ldr r3, [r3, #4] 80140a8: f003 0301 and.w r3, r3, #1 80140ac: 2b00 cmp r3, #0 80140ae: d001 beq.n 80140b4 return (NULL); 80140b0: 2300 movs r3, #0 80140b2: e054 b.n 801415e } if (attr->stack_size > 0U) { 80140b4: 687b ldr r3, [r7, #4] 80140b6: 695b ldr r3, [r3, #20] 80140b8: 2b00 cmp r3, #0 80140ba: d003 beq.n 80140c4 /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ stack = attr->stack_size / sizeof(StackType_t); 80140bc: 687b ldr r3, [r7, #4] 80140be: 695b ldr r3, [r3, #20] 80140c0: 089b lsrs r3, r3, #2 80140c2: 623b str r3, [r7, #32] } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 80140c4: 687b ldr r3, [r7, #4] 80140c6: 689b ldr r3, [r3, #8] 80140c8: 2b00 cmp r3, #0 80140ca: d00e beq.n 80140ea 80140cc: 687b ldr r3, [r7, #4] 80140ce: 68db ldr r3, [r3, #12] 80140d0: 2ba7 cmp r3, #167 @ 0xa7 80140d2: d90a bls.n 80140ea (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 80140d4: 687b ldr r3, [r7, #4] 80140d6: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 80140d8: 2b00 cmp r3, #0 80140da: d006 beq.n 80140ea (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 80140dc: 687b ldr r3, [r7, #4] 80140de: 695b ldr r3, [r3, #20] 80140e0: 2b00 cmp r3, #0 80140e2: d002 beq.n 80140ea mem = 1; 80140e4: 2301 movs r3, #1 80140e6: 61bb str r3, [r7, #24] 80140e8: e010 b.n 801410c } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { 80140ea: 687b ldr r3, [r7, #4] 80140ec: 689b ldr r3, [r3, #8] 80140ee: 2b00 cmp r3, #0 80140f0: d10c bne.n 801410c 80140f2: 687b ldr r3, [r7, #4] 80140f4: 68db ldr r3, [r3, #12] 80140f6: 2b00 cmp r3, #0 80140f8: d108 bne.n 801410c 80140fa: 687b ldr r3, [r7, #4] 80140fc: 691b ldr r3, [r3, #16] 80140fe: 2b00 cmp r3, #0 8014100: d104 bne.n 801410c mem = 0; 8014102: 2300 movs r3, #0 8014104: 61bb str r3, [r7, #24] 8014106: e001 b.n 801410c } } } else { mem = 0; 8014108: 2300 movs r3, #0 801410a: 61bb str r3, [r7, #24] } if (mem == 1) { 801410c: 69bb ldr r3, [r7, #24] 801410e: 2b01 cmp r3, #1 8014110: d110 bne.n 8014134 #if (configSUPPORT_STATIC_ALLOCATION == 1) hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 8014112: 687b ldr r3, [r7, #4] 8014114: 691b ldr r3, [r3, #16] (StaticTask_t *)attr->cb_mem); 8014116: 687a ldr r2, [r7, #4] 8014118: 6892 ldr r2, [r2, #8] hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 801411a: 9202 str r2, [sp, #8] 801411c: 9301 str r3, [sp, #4] 801411e: 69fb ldr r3, [r7, #28] 8014120: 9300 str r3, [sp, #0] 8014122: 68bb ldr r3, [r7, #8] 8014124: 6a3a ldr r2, [r7, #32] 8014126: 6a79 ldr r1, [r7, #36] @ 0x24 8014128: 68f8 ldr r0, [r7, #12] 801412a: f001 fdac bl 8015c86 801412e: 4603 mov r3, r0 8014130: 613b str r3, [r7, #16] 8014132: e013 b.n 801415c #endif } else { if (mem == 0) { 8014134: 69bb ldr r3, [r7, #24] 8014136: 2b00 cmp r3, #0 8014138: d110 bne.n 801415c #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { 801413a: 6a3b ldr r3, [r7, #32] 801413c: b29a uxth r2, r3 801413e: f107 0310 add.w r3, r7, #16 8014142: 9301 str r3, [sp, #4] 8014144: 69fb ldr r3, [r7, #28] 8014146: 9300 str r3, [sp, #0] 8014148: 68bb ldr r3, [r7, #8] 801414a: 6a79 ldr r1, [r7, #36] @ 0x24 801414c: 68f8 ldr r0, [r7, #12] 801414e: f001 fdfa bl 8015d46 8014152: 4603 mov r3, r0 8014154: 2b01 cmp r3, #1 8014156: d001 beq.n 801415c hTask = NULL; 8014158: 2300 movs r3, #0 801415a: 613b str r3, [r7, #16] #endif } } } return ((osThreadId_t)hTask); 801415c: 693b ldr r3, [r7, #16] } 801415e: 4618 mov r0, r3 8014160: 3728 adds r7, #40 @ 0x28 8014162: 46bd mov sp, r7 8014164: bd80 pop {r7, pc} 08014166 : /* Return flags before clearing */ return (rflags); } #endif /* (configUSE_OS2_THREAD_FLAGS == 1) */ osStatus_t osDelay (uint32_t ticks) { 8014166: b580 push {r7, lr} 8014168: b084 sub sp, #16 801416a: af00 add r7, sp, #0 801416c: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801416e: f3ef 8305 mrs r3, IPSR 8014172: 60bb str r3, [r7, #8] return(result); 8014174: 68bb ldr r3, [r7, #8] osStatus_t stat; if (IS_IRQ()) { 8014176: 2b00 cmp r3, #0 8014178: d003 beq.n 8014182 stat = osErrorISR; 801417a: f06f 0305 mvn.w r3, #5 801417e: 60fb str r3, [r7, #12] 8014180: e007 b.n 8014192 } else { stat = osOK; 8014182: 2300 movs r3, #0 8014184: 60fb str r3, [r7, #12] if (ticks != 0U) { 8014186: 687b ldr r3, [r7, #4] 8014188: 2b00 cmp r3, #0 801418a: d002 beq.n 8014192 vTaskDelay(ticks); 801418c: 6878 ldr r0, [r7, #4] 801418e: f001 ff37 bl 8016000 } } return (stat); 8014192: 68fb ldr r3, [r7, #12] } 8014194: 4618 mov r0, r3 8014196: 3710 adds r7, #16 8014198: 46bd mov sp, r7 801419a: bd80 pop {r7, pc} 0801419c : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_TIMER == 1) static void TimerCallback (TimerHandle_t hTimer) { 801419c: b580 push {r7, lr} 801419e: b084 sub sp, #16 80141a0: af00 add r7, sp, #0 80141a2: 6078 str r0, [r7, #4] TimerCallback_t *callb; callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); 80141a4: 6878 ldr r0, [r7, #4] 80141a6: f003 fc3d bl 8017a24 80141aa: 60f8 str r0, [r7, #12] if (callb != NULL) { 80141ac: 68fb ldr r3, [r7, #12] 80141ae: 2b00 cmp r3, #0 80141b0: d005 beq.n 80141be callb->func (callb->arg); 80141b2: 68fb ldr r3, [r7, #12] 80141b4: 681b ldr r3, [r3, #0] 80141b6: 68fa ldr r2, [r7, #12] 80141b8: 6852 ldr r2, [r2, #4] 80141ba: 4610 mov r0, r2 80141bc: 4798 blx r3 } } 80141be: bf00 nop 80141c0: 3710 adds r7, #16 80141c2: 46bd mov sp, r7 80141c4: bd80 pop {r7, pc} ... 080141c8 : osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { 80141c8: b580 push {r7, lr} 80141ca: b08c sub sp, #48 @ 0x30 80141cc: af02 add r7, sp, #8 80141ce: 60f8 str r0, [r7, #12] 80141d0: 607a str r2, [r7, #4] 80141d2: 603b str r3, [r7, #0] 80141d4: 460b mov r3, r1 80141d6: 72fb strb r3, [r7, #11] TimerHandle_t hTimer; TimerCallback_t *callb; UBaseType_t reload; int32_t mem; hTimer = NULL; 80141d8: 2300 movs r3, #0 80141da: 623b str r3, [r7, #32] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80141dc: f3ef 8305 mrs r3, IPSR 80141e0: 613b str r3, [r7, #16] return(result); 80141e2: 693b ldr r3, [r7, #16] if (!IS_IRQ() && (func != NULL)) { 80141e4: 2b00 cmp r3, #0 80141e6: d163 bne.n 80142b0 80141e8: 68fb ldr r3, [r7, #12] 80141ea: 2b00 cmp r3, #0 80141ec: d060 beq.n 80142b0 /* Allocate memory to store callback function and argument */ callb = pvPortMalloc (sizeof(TimerCallback_t)); 80141ee: 2008 movs r0, #8 80141f0: f003 fe8c bl 8017f0c 80141f4: 6178 str r0, [r7, #20] if (callb != NULL) { 80141f6: 697b ldr r3, [r7, #20] 80141f8: 2b00 cmp r3, #0 80141fa: d059 beq.n 80142b0 callb->func = func; 80141fc: 697b ldr r3, [r7, #20] 80141fe: 68fa ldr r2, [r7, #12] 8014200: 601a str r2, [r3, #0] callb->arg = argument; 8014202: 697b ldr r3, [r7, #20] 8014204: 687a ldr r2, [r7, #4] 8014206: 605a str r2, [r3, #4] if (type == osTimerOnce) { 8014208: 7afb ldrb r3, [r7, #11] 801420a: 2b00 cmp r3, #0 801420c: d102 bne.n 8014214 reload = pdFALSE; 801420e: 2300 movs r3, #0 8014210: 61fb str r3, [r7, #28] 8014212: e001 b.n 8014218 } else { reload = pdTRUE; 8014214: 2301 movs r3, #1 8014216: 61fb str r3, [r7, #28] } mem = -1; 8014218: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801421c: 61bb str r3, [r7, #24] name = NULL; 801421e: 2300 movs r3, #0 8014220: 627b str r3, [r7, #36] @ 0x24 if (attr != NULL) { 8014222: 683b ldr r3, [r7, #0] 8014224: 2b00 cmp r3, #0 8014226: d01c beq.n 8014262 if (attr->name != NULL) { 8014228: 683b ldr r3, [r7, #0] 801422a: 681b ldr r3, [r3, #0] 801422c: 2b00 cmp r3, #0 801422e: d002 beq.n 8014236 name = attr->name; 8014230: 683b ldr r3, [r7, #0] 8014232: 681b ldr r3, [r3, #0] 8014234: 627b str r3, [r7, #36] @ 0x24 } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) { 8014236: 683b ldr r3, [r7, #0] 8014238: 689b ldr r3, [r3, #8] 801423a: 2b00 cmp r3, #0 801423c: d006 beq.n 801424c 801423e: 683b ldr r3, [r7, #0] 8014240: 68db ldr r3, [r3, #12] 8014242: 2b2b cmp r3, #43 @ 0x2b 8014244: d902 bls.n 801424c mem = 1; 8014246: 2301 movs r3, #1 8014248: 61bb str r3, [r7, #24] 801424a: e00c b.n 8014266 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 801424c: 683b ldr r3, [r7, #0] 801424e: 689b ldr r3, [r3, #8] 8014250: 2b00 cmp r3, #0 8014252: d108 bne.n 8014266 8014254: 683b ldr r3, [r7, #0] 8014256: 68db ldr r3, [r3, #12] 8014258: 2b00 cmp r3, #0 801425a: d104 bne.n 8014266 mem = 0; 801425c: 2300 movs r3, #0 801425e: 61bb str r3, [r7, #24] 8014260: e001 b.n 8014266 } } } else { mem = 0; 8014262: 2300 movs r3, #0 8014264: 61bb str r3, [r7, #24] } if (mem == 1) { 8014266: 69bb ldr r3, [r7, #24] 8014268: 2b01 cmp r3, #1 801426a: d10c bne.n 8014286 #if (configSUPPORT_STATIC_ALLOCATION == 1) hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem); 801426c: 683b ldr r3, [r7, #0] 801426e: 689b ldr r3, [r3, #8] 8014270: 9301 str r3, [sp, #4] 8014272: 4b12 ldr r3, [pc, #72] @ (80142bc ) 8014274: 9300 str r3, [sp, #0] 8014276: 697b ldr r3, [r7, #20] 8014278: 69fa ldr r2, [r7, #28] 801427a: 2101 movs r1, #1 801427c: 6a78 ldr r0, [r7, #36] @ 0x24 801427e: f003 f81a bl 80172b6 8014282: 6238 str r0, [r7, #32] 8014284: e00b b.n 801429e #endif } else { if (mem == 0) { 8014286: 69bb ldr r3, [r7, #24] 8014288: 2b00 cmp r3, #0 801428a: d108 bne.n 801429e #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback); 801428c: 4b0b ldr r3, [pc, #44] @ (80142bc ) 801428e: 9300 str r3, [sp, #0] 8014290: 697b ldr r3, [r7, #20] 8014292: 69fa ldr r2, [r7, #28] 8014294: 2101 movs r1, #1 8014296: 6a78 ldr r0, [r7, #36] @ 0x24 8014298: f002 ffec bl 8017274 801429c: 6238 str r0, [r7, #32] #endif } } if ((hTimer == NULL) && (callb != NULL)) { 801429e: 6a3b ldr r3, [r7, #32] 80142a0: 2b00 cmp r3, #0 80142a2: d105 bne.n 80142b0 80142a4: 697b ldr r3, [r7, #20] 80142a6: 2b00 cmp r3, #0 80142a8: d002 beq.n 80142b0 vPortFree (callb); 80142aa: 6978 ldr r0, [r7, #20] 80142ac: f003 fefc bl 80180a8 } } } return ((osTimerId_t)hTimer); 80142b0: 6a3b ldr r3, [r7, #32] } 80142b2: 4618 mov r0, r3 80142b4: 3728 adds r7, #40 @ 0x28 80142b6: 46bd mov sp, r7 80142b8: bd80 pop {r7, pc} 80142ba: bf00 nop 80142bc: 0801419d .word 0x0801419d 080142c0 : } return (p); } osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) { 80142c0: b580 push {r7, lr} 80142c2: b088 sub sp, #32 80142c4: af02 add r7, sp, #8 80142c6: 6078 str r0, [r7, #4] 80142c8: 6039 str r1, [r7, #0] TimerHandle_t hTimer = (TimerHandle_t)timer_id; 80142ca: 687b ldr r3, [r7, #4] 80142cc: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80142ce: f3ef 8305 mrs r3, IPSR 80142d2: 60fb str r3, [r7, #12] return(result); 80142d4: 68fb ldr r3, [r7, #12] osStatus_t stat; if (IS_IRQ()) { 80142d6: 2b00 cmp r3, #0 80142d8: d003 beq.n 80142e2 stat = osErrorISR; 80142da: f06f 0305 mvn.w r3, #5 80142de: 617b str r3, [r7, #20] 80142e0: e017 b.n 8014312 } else if (hTimer == NULL) { 80142e2: 693b ldr r3, [r7, #16] 80142e4: 2b00 cmp r3, #0 80142e6: d103 bne.n 80142f0 stat = osErrorParameter; 80142e8: f06f 0303 mvn.w r3, #3 80142ec: 617b str r3, [r7, #20] 80142ee: e010 b.n 8014312 } else { if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) { 80142f0: 2300 movs r3, #0 80142f2: 9300 str r3, [sp, #0] 80142f4: 2300 movs r3, #0 80142f6: 683a ldr r2, [r7, #0] 80142f8: 2104 movs r1, #4 80142fa: 6938 ldr r0, [r7, #16] 80142fc: f003 f858 bl 80173b0 8014300: 4603 mov r3, r0 8014302: 2b01 cmp r3, #1 8014304: d102 bne.n 801430c stat = osOK; 8014306: 2300 movs r3, #0 8014308: 617b str r3, [r7, #20] 801430a: e002 b.n 8014312 } else { stat = osErrorResource; 801430c: f06f 0302 mvn.w r3, #2 8014310: 617b str r3, [r7, #20] } } return (stat); 8014312: 697b ldr r3, [r7, #20] } 8014314: 4618 mov r0, r3 8014316: 3718 adds r7, #24 8014318: 46bd mov sp, r7 801431a: bd80 pop {r7, pc} 0801431c : osStatus_t osTimerStop (osTimerId_t timer_id) { 801431c: b580 push {r7, lr} 801431e: b088 sub sp, #32 8014320: af02 add r7, sp, #8 8014322: 6078 str r0, [r7, #4] TimerHandle_t hTimer = (TimerHandle_t)timer_id; 8014324: 687b ldr r3, [r7, #4] 8014326: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014328: f3ef 8305 mrs r3, IPSR 801432c: 60fb str r3, [r7, #12] return(result); 801432e: 68fb ldr r3, [r7, #12] osStatus_t stat; if (IS_IRQ()) { 8014330: 2b00 cmp r3, #0 8014332: d003 beq.n 801433c stat = osErrorISR; 8014334: f06f 0305 mvn.w r3, #5 8014338: 617b str r3, [r7, #20] 801433a: e021 b.n 8014380 } else if (hTimer == NULL) { 801433c: 693b ldr r3, [r7, #16] 801433e: 2b00 cmp r3, #0 8014340: d103 bne.n 801434a stat = osErrorParameter; 8014342: f06f 0303 mvn.w r3, #3 8014346: 617b str r3, [r7, #20] 8014348: e01a b.n 8014380 } else { if (xTimerIsTimerActive (hTimer) == pdFALSE) { 801434a: 6938 ldr r0, [r7, #16] 801434c: f003 fb40 bl 80179d0 8014350: 4603 mov r3, r0 8014352: 2b00 cmp r3, #0 8014354: d103 bne.n 801435e stat = osErrorResource; 8014356: f06f 0302 mvn.w r3, #2 801435a: 617b str r3, [r7, #20] 801435c: e010 b.n 8014380 } else { if (xTimerStop (hTimer, 0) == pdPASS) { 801435e: 2300 movs r3, #0 8014360: 9300 str r3, [sp, #0] 8014362: 2300 movs r3, #0 8014364: 2200 movs r2, #0 8014366: 2103 movs r1, #3 8014368: 6938 ldr r0, [r7, #16] 801436a: f003 f821 bl 80173b0 801436e: 4603 mov r3, r0 8014370: 2b01 cmp r3, #1 8014372: d102 bne.n 801437a stat = osOK; 8014374: 2300 movs r3, #0 8014376: 617b str r3, [r7, #20] 8014378: e002 b.n 8014380 } else { stat = osError; 801437a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801437e: 617b str r3, [r7, #20] } } } return (stat); 8014380: 697b ldr r3, [r7, #20] } 8014382: 4618 mov r0, r3 8014384: 3718 adds r7, #24 8014386: 46bd mov sp, r7 8014388: bd80 pop {r7, pc} 0801438a : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_MUTEX == 1) osMutexId_t osMutexNew (const osMutexAttr_t *attr) { 801438a: b580 push {r7, lr} 801438c: b088 sub sp, #32 801438e: af00 add r7, sp, #0 8014390: 6078 str r0, [r7, #4] int32_t mem; #if (configQUEUE_REGISTRY_SIZE > 0) const char *name; #endif hMutex = NULL; 8014392: 2300 movs r3, #0 8014394: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014396: f3ef 8305 mrs r3, IPSR 801439a: 60bb str r3, [r7, #8] return(result); 801439c: 68bb ldr r3, [r7, #8] if (!IS_IRQ()) { 801439e: 2b00 cmp r3, #0 80143a0: d174 bne.n 801448c if (attr != NULL) { 80143a2: 687b ldr r3, [r7, #4] 80143a4: 2b00 cmp r3, #0 80143a6: d003 beq.n 80143b0 type = attr->attr_bits; 80143a8: 687b ldr r3, [r7, #4] 80143aa: 685b ldr r3, [r3, #4] 80143ac: 61bb str r3, [r7, #24] 80143ae: e001 b.n 80143b4 } else { type = 0U; 80143b0: 2300 movs r3, #0 80143b2: 61bb str r3, [r7, #24] } if ((type & osMutexRecursive) == osMutexRecursive) { 80143b4: 69bb ldr r3, [r7, #24] 80143b6: f003 0301 and.w r3, r3, #1 80143ba: 2b00 cmp r3, #0 80143bc: d002 beq.n 80143c4 rmtx = 1U; 80143be: 2301 movs r3, #1 80143c0: 617b str r3, [r7, #20] 80143c2: e001 b.n 80143c8 } else { rmtx = 0U; 80143c4: 2300 movs r3, #0 80143c6: 617b str r3, [r7, #20] } if ((type & osMutexRobust) != osMutexRobust) { 80143c8: 69bb ldr r3, [r7, #24] 80143ca: f003 0308 and.w r3, r3, #8 80143ce: 2b00 cmp r3, #0 80143d0: d15c bne.n 801448c mem = -1; 80143d2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80143d6: 613b str r3, [r7, #16] if (attr != NULL) { 80143d8: 687b ldr r3, [r7, #4] 80143da: 2b00 cmp r3, #0 80143dc: d015 beq.n 801440a if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { 80143de: 687b ldr r3, [r7, #4] 80143e0: 689b ldr r3, [r3, #8] 80143e2: 2b00 cmp r3, #0 80143e4: d006 beq.n 80143f4 80143e6: 687b ldr r3, [r7, #4] 80143e8: 68db ldr r3, [r3, #12] 80143ea: 2b4f cmp r3, #79 @ 0x4f 80143ec: d902 bls.n 80143f4 mem = 1; 80143ee: 2301 movs r3, #1 80143f0: 613b str r3, [r7, #16] 80143f2: e00c b.n 801440e } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 80143f4: 687b ldr r3, [r7, #4] 80143f6: 689b ldr r3, [r3, #8] 80143f8: 2b00 cmp r3, #0 80143fa: d108 bne.n 801440e 80143fc: 687b ldr r3, [r7, #4] 80143fe: 68db ldr r3, [r3, #12] 8014400: 2b00 cmp r3, #0 8014402: d104 bne.n 801440e mem = 0; 8014404: 2300 movs r3, #0 8014406: 613b str r3, [r7, #16] 8014408: e001 b.n 801440e } } } else { mem = 0; 801440a: 2300 movs r3, #0 801440c: 613b str r3, [r7, #16] } if (mem == 1) { 801440e: 693b ldr r3, [r7, #16] 8014410: 2b01 cmp r3, #1 8014412: d112 bne.n 801443a #if (configSUPPORT_STATIC_ALLOCATION == 1) if (rmtx != 0U) { 8014414: 697b ldr r3, [r7, #20] 8014416: 2b00 cmp r3, #0 8014418: d007 beq.n 801442a #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem); 801441a: 687b ldr r3, [r7, #4] 801441c: 689b ldr r3, [r3, #8] 801441e: 4619 mov r1, r3 8014420: 2004 movs r0, #4 8014422: f000 fc50 bl 8014cc6 8014426: 61f8 str r0, [r7, #28] 8014428: e016 b.n 8014458 #endif } else { hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem); 801442a: 687b ldr r3, [r7, #4] 801442c: 689b ldr r3, [r3, #8] 801442e: 4619 mov r1, r3 8014430: 2001 movs r0, #1 8014432: f000 fc48 bl 8014cc6 8014436: 61f8 str r0, [r7, #28] 8014438: e00e b.n 8014458 } #endif } else { if (mem == 0) { 801443a: 693b ldr r3, [r7, #16] 801443c: 2b00 cmp r3, #0 801443e: d10b bne.n 8014458 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (rmtx != 0U) { 8014440: 697b ldr r3, [r7, #20] 8014442: 2b00 cmp r3, #0 8014444: d004 beq.n 8014450 #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutex (); 8014446: 2004 movs r0, #4 8014448: f000 fc25 bl 8014c96 801444c: 61f8 str r0, [r7, #28] 801444e: e003 b.n 8014458 #endif } else { hMutex = xSemaphoreCreateMutex (); 8014450: 2001 movs r0, #1 8014452: f000 fc20 bl 8014c96 8014456: 61f8 str r0, [r7, #28] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hMutex != NULL) { 8014458: 69fb ldr r3, [r7, #28] 801445a: 2b00 cmp r3, #0 801445c: d00c beq.n 8014478 if (attr != NULL) { 801445e: 687b ldr r3, [r7, #4] 8014460: 2b00 cmp r3, #0 8014462: d003 beq.n 801446c name = attr->name; 8014464: 687b ldr r3, [r7, #4] 8014466: 681b ldr r3, [r3, #0] 8014468: 60fb str r3, [r7, #12] 801446a: e001 b.n 8014470 } else { name = NULL; 801446c: 2300 movs r3, #0 801446e: 60fb str r3, [r7, #12] } vQueueAddToRegistry (hMutex, name); 8014470: 68f9 ldr r1, [r7, #12] 8014472: 69f8 ldr r0, [r7, #28] 8014474: f001 f9ea bl 801584c } #endif if ((hMutex != NULL) && (rmtx != 0U)) { 8014478: 69fb ldr r3, [r7, #28] 801447a: 2b00 cmp r3, #0 801447c: d006 beq.n 801448c 801447e: 697b ldr r3, [r7, #20] 8014480: 2b00 cmp r3, #0 8014482: d003 beq.n 801448c hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U); 8014484: 69fb ldr r3, [r7, #28] 8014486: f043 0301 orr.w r3, r3, #1 801448a: 61fb str r3, [r7, #28] } } } return ((osMutexId_t)hMutex); 801448c: 69fb ldr r3, [r7, #28] } 801448e: 4618 mov r0, r3 8014490: 3720 adds r7, #32 8014492: 46bd mov sp, r7 8014494: bd80 pop {r7, pc} 08014496 : osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { 8014496: b580 push {r7, lr} 8014498: b086 sub sp, #24 801449a: af00 add r7, sp, #0 801449c: 6078 str r0, [r7, #4] 801449e: 6039 str r1, [r7, #0] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 80144a0: 687b ldr r3, [r7, #4] 80144a2: f023 0301 bic.w r3, r3, #1 80144a6: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 80144a8: 687b ldr r3, [r7, #4] 80144aa: f003 0301 and.w r3, r3, #1 80144ae: 60fb str r3, [r7, #12] stat = osOK; 80144b0: 2300 movs r3, #0 80144b2: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80144b4: f3ef 8305 mrs r3, IPSR 80144b8: 60bb str r3, [r7, #8] return(result); 80144ba: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 80144bc: 2b00 cmp r3, #0 80144be: d003 beq.n 80144c8 stat = osErrorISR; 80144c0: f06f 0305 mvn.w r3, #5 80144c4: 617b str r3, [r7, #20] 80144c6: e02c b.n 8014522 } else if (hMutex == NULL) { 80144c8: 693b ldr r3, [r7, #16] 80144ca: 2b00 cmp r3, #0 80144cc: d103 bne.n 80144d6 stat = osErrorParameter; 80144ce: f06f 0303 mvn.w r3, #3 80144d2: 617b str r3, [r7, #20] 80144d4: e025 b.n 8014522 } else { if (rmtx != 0U) { 80144d6: 68fb ldr r3, [r7, #12] 80144d8: 2b00 cmp r3, #0 80144da: d011 beq.n 8014500 #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) { 80144dc: 6839 ldr r1, [r7, #0] 80144de: 6938 ldr r0, [r7, #16] 80144e0: f000 fc41 bl 8014d66 80144e4: 4603 mov r3, r0 80144e6: 2b01 cmp r3, #1 80144e8: d01b beq.n 8014522 if (timeout != 0U) { 80144ea: 683b ldr r3, [r7, #0] 80144ec: 2b00 cmp r3, #0 80144ee: d003 beq.n 80144f8 stat = osErrorTimeout; 80144f0: f06f 0301 mvn.w r3, #1 80144f4: 617b str r3, [r7, #20] 80144f6: e014 b.n 8014522 } else { stat = osErrorResource; 80144f8: f06f 0302 mvn.w r3, #2 80144fc: 617b str r3, [r7, #20] 80144fe: e010 b.n 8014522 } } #endif } else { if (xSemaphoreTake (hMutex, timeout) != pdPASS) { 8014500: 6839 ldr r1, [r7, #0] 8014502: 6938 ldr r0, [r7, #16] 8014504: f000 fee8 bl 80152d8 8014508: 4603 mov r3, r0 801450a: 2b01 cmp r3, #1 801450c: d009 beq.n 8014522 if (timeout != 0U) { 801450e: 683b ldr r3, [r7, #0] 8014510: 2b00 cmp r3, #0 8014512: d003 beq.n 801451c stat = osErrorTimeout; 8014514: f06f 0301 mvn.w r3, #1 8014518: 617b str r3, [r7, #20] 801451a: e002 b.n 8014522 } else { stat = osErrorResource; 801451c: f06f 0302 mvn.w r3, #2 8014520: 617b str r3, [r7, #20] } } } } return (stat); 8014522: 697b ldr r3, [r7, #20] } 8014524: 4618 mov r0, r3 8014526: 3718 adds r7, #24 8014528: 46bd mov sp, r7 801452a: bd80 pop {r7, pc} 0801452c : osStatus_t osMutexRelease (osMutexId_t mutex_id) { 801452c: b580 push {r7, lr} 801452e: b086 sub sp, #24 8014530: af00 add r7, sp, #0 8014532: 6078 str r0, [r7, #4] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 8014534: 687b ldr r3, [r7, #4] 8014536: f023 0301 bic.w r3, r3, #1 801453a: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 801453c: 687b ldr r3, [r7, #4] 801453e: f003 0301 and.w r3, r3, #1 8014542: 60fb str r3, [r7, #12] stat = osOK; 8014544: 2300 movs r3, #0 8014546: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014548: f3ef 8305 mrs r3, IPSR 801454c: 60bb str r3, [r7, #8] return(result); 801454e: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 8014550: 2b00 cmp r3, #0 8014552: d003 beq.n 801455c stat = osErrorISR; 8014554: f06f 0305 mvn.w r3, #5 8014558: 617b str r3, [r7, #20] 801455a: e01f b.n 801459c } else if (hMutex == NULL) { 801455c: 693b ldr r3, [r7, #16] 801455e: 2b00 cmp r3, #0 8014560: d103 bne.n 801456a stat = osErrorParameter; 8014562: f06f 0303 mvn.w r3, #3 8014566: 617b str r3, [r7, #20] 8014568: e018 b.n 801459c } else { if (rmtx != 0U) { 801456a: 68fb ldr r3, [r7, #12] 801456c: 2b00 cmp r3, #0 801456e: d009 beq.n 8014584 #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreGiveRecursive (hMutex) != pdPASS) { 8014570: 6938 ldr r0, [r7, #16] 8014572: f000 fbc3 bl 8014cfc 8014576: 4603 mov r3, r0 8014578: 2b01 cmp r3, #1 801457a: d00f beq.n 801459c stat = osErrorResource; 801457c: f06f 0302 mvn.w r3, #2 8014580: 617b str r3, [r7, #20] 8014582: e00b b.n 801459c } #endif } else { if (xSemaphoreGive (hMutex) != pdPASS) { 8014584: 2300 movs r3, #0 8014586: 2200 movs r2, #0 8014588: 2100 movs r1, #0 801458a: 6938 ldr r0, [r7, #16] 801458c: f000 fc22 bl 8014dd4 8014590: 4603 mov r3, r0 8014592: 2b01 cmp r3, #1 8014594: d002 beq.n 801459c stat = osErrorResource; 8014596: f06f 0302 mvn.w r3, #2 801459a: 617b str r3, [r7, #20] } } } return (stat); 801459c: 697b ldr r3, [r7, #20] } 801459e: 4618 mov r0, r3 80145a0: 3718 adds r7, #24 80145a2: 46bd mov sp, r7 80145a4: bd80 pop {r7, pc} 080145a6 : return (stat); } /*---------------------------------------------------------------------------*/ osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { 80145a6: b580 push {r7, lr} 80145a8: b08a sub sp, #40 @ 0x28 80145aa: af02 add r7, sp, #8 80145ac: 60f8 str r0, [r7, #12] 80145ae: 60b9 str r1, [r7, #8] 80145b0: 607a str r2, [r7, #4] int32_t mem; #if (configQUEUE_REGISTRY_SIZE > 0) const char *name; #endif hQueue = NULL; 80145b2: 2300 movs r3, #0 80145b4: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80145b6: f3ef 8305 mrs r3, IPSR 80145ba: 613b str r3, [r7, #16] return(result); 80145bc: 693b ldr r3, [r7, #16] if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) { 80145be: 2b00 cmp r3, #0 80145c0: d15f bne.n 8014682 80145c2: 68fb ldr r3, [r7, #12] 80145c4: 2b00 cmp r3, #0 80145c6: d05c beq.n 8014682 80145c8: 68bb ldr r3, [r7, #8] 80145ca: 2b00 cmp r3, #0 80145cc: d059 beq.n 8014682 mem = -1; 80145ce: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80145d2: 61bb str r3, [r7, #24] if (attr != NULL) { 80145d4: 687b ldr r3, [r7, #4] 80145d6: 2b00 cmp r3, #0 80145d8: d029 beq.n 801462e if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 80145da: 687b ldr r3, [r7, #4] 80145dc: 689b ldr r3, [r3, #8] 80145de: 2b00 cmp r3, #0 80145e0: d012 beq.n 8014608 80145e2: 687b ldr r3, [r7, #4] 80145e4: 68db ldr r3, [r3, #12] 80145e6: 2b4f cmp r3, #79 @ 0x4f 80145e8: d90e bls.n 8014608 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 80145ea: 687b ldr r3, [r7, #4] 80145ec: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 80145ee: 2b00 cmp r3, #0 80145f0: d00a beq.n 8014608 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 80145f2: 687b ldr r3, [r7, #4] 80145f4: 695a ldr r2, [r3, #20] 80145f6: 68fb ldr r3, [r7, #12] 80145f8: 68b9 ldr r1, [r7, #8] 80145fa: fb01 f303 mul.w r3, r1, r3 80145fe: 429a cmp r2, r3 8014600: d302 bcc.n 8014608 mem = 1; 8014602: 2301 movs r3, #1 8014604: 61bb str r3, [r7, #24] 8014606: e014 b.n 8014632 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 8014608: 687b ldr r3, [r7, #4] 801460a: 689b ldr r3, [r3, #8] 801460c: 2b00 cmp r3, #0 801460e: d110 bne.n 8014632 8014610: 687b ldr r3, [r7, #4] 8014612: 68db ldr r3, [r3, #12] 8014614: 2b00 cmp r3, #0 8014616: d10c bne.n 8014632 (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 8014618: 687b ldr r3, [r7, #4] 801461a: 691b ldr r3, [r3, #16] if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 801461c: 2b00 cmp r3, #0 801461e: d108 bne.n 8014632 (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 8014620: 687b ldr r3, [r7, #4] 8014622: 695b ldr r3, [r3, #20] 8014624: 2b00 cmp r3, #0 8014626: d104 bne.n 8014632 mem = 0; 8014628: 2300 movs r3, #0 801462a: 61bb str r3, [r7, #24] 801462c: e001 b.n 8014632 } } } else { mem = 0; 801462e: 2300 movs r3, #0 8014630: 61bb str r3, [r7, #24] } if (mem == 1) { 8014632: 69bb ldr r3, [r7, #24] 8014634: 2b01 cmp r3, #1 8014636: d10b bne.n 8014650 #if (configSUPPORT_STATIC_ALLOCATION == 1) hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem); 8014638: 687b ldr r3, [r7, #4] 801463a: 691a ldr r2, [r3, #16] 801463c: 687b ldr r3, [r7, #4] 801463e: 689b ldr r3, [r3, #8] 8014640: 2100 movs r1, #0 8014642: 9100 str r1, [sp, #0] 8014644: 68b9 ldr r1, [r7, #8] 8014646: 68f8 ldr r0, [r7, #12] 8014648: f000 fa30 bl 8014aac 801464c: 61f8 str r0, [r7, #28] 801464e: e008 b.n 8014662 #endif } else { if (mem == 0) { 8014650: 69bb ldr r3, [r7, #24] 8014652: 2b00 cmp r3, #0 8014654: d105 bne.n 8014662 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hQueue = xQueueCreate (msg_count, msg_size); 8014656: 2200 movs r2, #0 8014658: 68b9 ldr r1, [r7, #8] 801465a: 68f8 ldr r0, [r7, #12] 801465c: f000 faa3 bl 8014ba6 8014660: 61f8 str r0, [r7, #28] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hQueue != NULL) { 8014662: 69fb ldr r3, [r7, #28] 8014664: 2b00 cmp r3, #0 8014666: d00c beq.n 8014682 if (attr != NULL) { 8014668: 687b ldr r3, [r7, #4] 801466a: 2b00 cmp r3, #0 801466c: d003 beq.n 8014676 name = attr->name; 801466e: 687b ldr r3, [r7, #4] 8014670: 681b ldr r3, [r3, #0] 8014672: 617b str r3, [r7, #20] 8014674: e001 b.n 801467a } else { name = NULL; 8014676: 2300 movs r3, #0 8014678: 617b str r3, [r7, #20] } vQueueAddToRegistry (hQueue, name); 801467a: 6979 ldr r1, [r7, #20] 801467c: 69f8 ldr r0, [r7, #28] 801467e: f001 f8e5 bl 801584c } #endif } return ((osMessageQueueId_t)hQueue); 8014682: 69fb ldr r3, [r7, #28] } 8014684: 4618 mov r0, r3 8014686: 3720 adds r7, #32 8014688: 46bd mov sp, r7 801468a: bd80 pop {r7, pc} 0801468c : osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { 801468c: b580 push {r7, lr} 801468e: b088 sub sp, #32 8014690: af00 add r7, sp, #0 8014692: 60f8 str r0, [r7, #12] 8014694: 60b9 str r1, [r7, #8] 8014696: 603b str r3, [r7, #0] 8014698: 4613 mov r3, r2 801469a: 71fb strb r3, [r7, #7] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 801469c: 68fb ldr r3, [r7, #12] 801469e: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 80146a0: 2300 movs r3, #0 80146a2: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80146a4: f3ef 8305 mrs r3, IPSR 80146a8: 617b str r3, [r7, #20] return(result); 80146aa: 697b ldr r3, [r7, #20] if (IS_IRQ()) { 80146ac: 2b00 cmp r3, #0 80146ae: d028 beq.n 8014702 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 80146b0: 69bb ldr r3, [r7, #24] 80146b2: 2b00 cmp r3, #0 80146b4: d005 beq.n 80146c2 80146b6: 68bb ldr r3, [r7, #8] 80146b8: 2b00 cmp r3, #0 80146ba: d002 beq.n 80146c2 80146bc: 683b ldr r3, [r7, #0] 80146be: 2b00 cmp r3, #0 80146c0: d003 beq.n 80146ca stat = osErrorParameter; 80146c2: f06f 0303 mvn.w r3, #3 80146c6: 61fb str r3, [r7, #28] 80146c8: e038 b.n 801473c } else { yield = pdFALSE; 80146ca: 2300 movs r3, #0 80146cc: 613b str r3, [r7, #16] if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { 80146ce: f107 0210 add.w r2, r7, #16 80146d2: 2300 movs r3, #0 80146d4: 68b9 ldr r1, [r7, #8] 80146d6: 69b8 ldr r0, [r7, #24] 80146d8: f000 fc7e bl 8014fd8 80146dc: 4603 mov r3, r0 80146de: 2b01 cmp r3, #1 80146e0: d003 beq.n 80146ea stat = osErrorResource; 80146e2: f06f 0302 mvn.w r3, #2 80146e6: 61fb str r3, [r7, #28] 80146e8: e028 b.n 801473c } else { portYIELD_FROM_ISR (yield); 80146ea: 693b ldr r3, [r7, #16] 80146ec: 2b00 cmp r3, #0 80146ee: d025 beq.n 801473c 80146f0: 4b15 ldr r3, [pc, #84] @ (8014748 ) 80146f2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80146f6: 601a str r2, [r3, #0] 80146f8: f3bf 8f4f dsb sy 80146fc: f3bf 8f6f isb sy 8014700: e01c b.n 801473c } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 8014702: 69bb ldr r3, [r7, #24] 8014704: 2b00 cmp r3, #0 8014706: d002 beq.n 801470e 8014708: 68bb ldr r3, [r7, #8] 801470a: 2b00 cmp r3, #0 801470c: d103 bne.n 8014716 stat = osErrorParameter; 801470e: f06f 0303 mvn.w r3, #3 8014712: 61fb str r3, [r7, #28] 8014714: e012 b.n 801473c } else { if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 8014716: 2300 movs r3, #0 8014718: 683a ldr r2, [r7, #0] 801471a: 68b9 ldr r1, [r7, #8] 801471c: 69b8 ldr r0, [r7, #24] 801471e: f000 fb59 bl 8014dd4 8014722: 4603 mov r3, r0 8014724: 2b01 cmp r3, #1 8014726: d009 beq.n 801473c if (timeout != 0U) { 8014728: 683b ldr r3, [r7, #0] 801472a: 2b00 cmp r3, #0 801472c: d003 beq.n 8014736 stat = osErrorTimeout; 801472e: f06f 0301 mvn.w r3, #1 8014732: 61fb str r3, [r7, #28] 8014734: e002 b.n 801473c } else { stat = osErrorResource; 8014736: f06f 0302 mvn.w r3, #2 801473a: 61fb str r3, [r7, #28] } } } } return (stat); 801473c: 69fb ldr r3, [r7, #28] } 801473e: 4618 mov r0, r3 8014740: 3720 adds r7, #32 8014742: 46bd mov sp, r7 8014744: bd80 pop {r7, pc} 8014746: bf00 nop 8014748: e000ed04 .word 0xe000ed04 0801474c : osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { 801474c: b580 push {r7, lr} 801474e: b088 sub sp, #32 8014750: af00 add r7, sp, #0 8014752: 60f8 str r0, [r7, #12] 8014754: 60b9 str r1, [r7, #8] 8014756: 607a str r2, [r7, #4] 8014758: 603b str r3, [r7, #0] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 801475a: 68fb ldr r3, [r7, #12] 801475c: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 801475e: 2300 movs r3, #0 8014760: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014762: f3ef 8305 mrs r3, IPSR 8014766: 617b str r3, [r7, #20] return(result); 8014768: 697b ldr r3, [r7, #20] if (IS_IRQ()) { 801476a: 2b00 cmp r3, #0 801476c: d028 beq.n 80147c0 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 801476e: 69bb ldr r3, [r7, #24] 8014770: 2b00 cmp r3, #0 8014772: d005 beq.n 8014780 8014774: 68bb ldr r3, [r7, #8] 8014776: 2b00 cmp r3, #0 8014778: d002 beq.n 8014780 801477a: 683b ldr r3, [r7, #0] 801477c: 2b00 cmp r3, #0 801477e: d003 beq.n 8014788 stat = osErrorParameter; 8014780: f06f 0303 mvn.w r3, #3 8014784: 61fb str r3, [r7, #28] 8014786: e037 b.n 80147f8 } else { yield = pdFALSE; 8014788: 2300 movs r3, #0 801478a: 613b str r3, [r7, #16] if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) { 801478c: f107 0310 add.w r3, r7, #16 8014790: 461a mov r2, r3 8014792: 68b9 ldr r1, [r7, #8] 8014794: 69b8 ldr r0, [r7, #24] 8014796: f000 feaf bl 80154f8 801479a: 4603 mov r3, r0 801479c: 2b01 cmp r3, #1 801479e: d003 beq.n 80147a8 stat = osErrorResource; 80147a0: f06f 0302 mvn.w r3, #2 80147a4: 61fb str r3, [r7, #28] 80147a6: e027 b.n 80147f8 } else { portYIELD_FROM_ISR (yield); 80147a8: 693b ldr r3, [r7, #16] 80147aa: 2b00 cmp r3, #0 80147ac: d024 beq.n 80147f8 80147ae: 4b15 ldr r3, [pc, #84] @ (8014804 ) 80147b0: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80147b4: 601a str r2, [r3, #0] 80147b6: f3bf 8f4f dsb sy 80147ba: f3bf 8f6f isb sy 80147be: e01b b.n 80147f8 } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 80147c0: 69bb ldr r3, [r7, #24] 80147c2: 2b00 cmp r3, #0 80147c4: d002 beq.n 80147cc 80147c6: 68bb ldr r3, [r7, #8] 80147c8: 2b00 cmp r3, #0 80147ca: d103 bne.n 80147d4 stat = osErrorParameter; 80147cc: f06f 0303 mvn.w r3, #3 80147d0: 61fb str r3, [r7, #28] 80147d2: e011 b.n 80147f8 } else { if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 80147d4: 683a ldr r2, [r7, #0] 80147d6: 68b9 ldr r1, [r7, #8] 80147d8: 69b8 ldr r0, [r7, #24] 80147da: f000 fc9b bl 8015114 80147de: 4603 mov r3, r0 80147e0: 2b01 cmp r3, #1 80147e2: d009 beq.n 80147f8 if (timeout != 0U) { 80147e4: 683b ldr r3, [r7, #0] 80147e6: 2b00 cmp r3, #0 80147e8: d003 beq.n 80147f2 stat = osErrorTimeout; 80147ea: f06f 0301 mvn.w r3, #1 80147ee: 61fb str r3, [r7, #28] 80147f0: e002 b.n 80147f8 } else { stat = osErrorResource; 80147f2: f06f 0302 mvn.w r3, #2 80147f6: 61fb str r3, [r7, #28] } } } } return (stat); 80147f8: 69fb ldr r3, [r7, #28] } 80147fa: 4618 mov r0, r3 80147fc: 3720 adds r7, #32 80147fe: 46bd mov sp, r7 8014800: bd80 pop {r7, pc} 8014802: bf00 nop 8014804: e000ed04 .word 0xe000ed04 08014808 : /* vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { 8014808: b480 push {r7} 801480a: b085 sub sp, #20 801480c: af00 add r7, sp, #0 801480e: 60f8 str r0, [r7, #12] 8014810: 60b9 str r1, [r7, #8] 8014812: 607a str r2, [r7, #4] /* Idle task control block and stack */ static StaticTask_t Idle_TCB; static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; *ppxIdleTaskTCBBuffer = &Idle_TCB; 8014814: 68fb ldr r3, [r7, #12] 8014816: 4a07 ldr r2, [pc, #28] @ (8014834 ) 8014818: 601a str r2, [r3, #0] *ppxIdleTaskStackBuffer = &Idle_Stack[0]; 801481a: 68bb ldr r3, [r7, #8] 801481c: 4a06 ldr r2, [pc, #24] @ (8014838 ) 801481e: 601a str r2, [r3, #0] *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; 8014820: 687b ldr r3, [r7, #4] 8014822: f44f 7200 mov.w r2, #512 @ 0x200 8014826: 601a str r2, [r3, #0] } 8014828: bf00 nop 801482a: 3714 adds r7, #20 801482c: 46bd mov sp, r7 801482e: f85d 7b04 ldr.w r7, [sp], #4 8014832: 4770 bx lr 8014834: 24001068 .word 0x24001068 8014838: 24001110 .word 0x24001110 0801483c : /* vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { 801483c: b480 push {r7} 801483e: b085 sub sp, #20 8014840: af00 add r7, sp, #0 8014842: 60f8 str r0, [r7, #12] 8014844: 60b9 str r1, [r7, #8] 8014846: 607a str r2, [r7, #4] /* Timer task control block and stack */ static StaticTask_t Timer_TCB; static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; *ppxTimerTaskTCBBuffer = &Timer_TCB; 8014848: 68fb ldr r3, [r7, #12] 801484a: 4a07 ldr r2, [pc, #28] @ (8014868 ) 801484c: 601a str r2, [r3, #0] *ppxTimerTaskStackBuffer = &Timer_Stack[0]; 801484e: 68bb ldr r3, [r7, #8] 8014850: 4a06 ldr r2, [pc, #24] @ (801486c ) 8014852: 601a str r2, [r3, #0] *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; 8014854: 687b ldr r3, [r7, #4] 8014856: f44f 6280 mov.w r2, #1024 @ 0x400 801485a: 601a str r2, [r3, #0] } 801485c: bf00 nop 801485e: 3714 adds r7, #20 8014860: 46bd mov sp, r7 8014862: f85d 7b04 ldr.w r7, [sp], #4 8014866: 4770 bx lr 8014868: 24001910 .word 0x24001910 801486c: 240019b8 .word 0x240019b8 08014870 : /*----------------------------------------------------------- * PUBLIC LIST API documented in list.h *----------------------------------------------------------*/ void vListInitialise( List_t * const pxList ) { 8014870: b480 push {r7} 8014872: b083 sub sp, #12 8014874: af00 add r7, sp, #0 8014876: 6078 str r0, [r7, #4] /* The list structure contains a list item which is used to mark the end of the list. To initialise the list the list end is inserted as the only list entry. */ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8014878: 687b ldr r3, [r7, #4] 801487a: f103 0208 add.w r2, r3, #8 801487e: 687b ldr r3, [r7, #4] 8014880: 605a str r2, [r3, #4] /* The list end value is the highest possible value in the list to ensure it remains at the end of the list. */ pxList->xListEnd.xItemValue = portMAX_DELAY; 8014882: 687b ldr r3, [r7, #4] 8014884: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8014888: 609a str r2, [r3, #8] /* The list end next and previous pointers point to itself so we know when the list is empty. */ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 801488a: 687b ldr r3, [r7, #4] 801488c: f103 0208 add.w r2, r3, #8 8014890: 687b ldr r3, [r7, #4] 8014892: 60da str r2, [r3, #12] pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8014894: 687b ldr r3, [r7, #4] 8014896: f103 0208 add.w r2, r3, #8 801489a: 687b ldr r3, [r7, #4] 801489c: 611a str r2, [r3, #16] pxList->uxNumberOfItems = ( UBaseType_t ) 0U; 801489e: 687b ldr r3, [r7, #4] 80148a0: 2200 movs r2, #0 80148a2: 601a str r2, [r3, #0] /* Write known values into the list if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); } 80148a4: bf00 nop 80148a6: 370c adds r7, #12 80148a8: 46bd mov sp, r7 80148aa: f85d 7b04 ldr.w r7, [sp], #4 80148ae: 4770 bx lr 080148b0 : /*-----------------------------------------------------------*/ void vListInitialiseItem( ListItem_t * const pxItem ) { 80148b0: b480 push {r7} 80148b2: b083 sub sp, #12 80148b4: af00 add r7, sp, #0 80148b6: 6078 str r0, [r7, #4] /* Make sure the list item is not recorded as being on a list. */ pxItem->pxContainer = NULL; 80148b8: 687b ldr r3, [r7, #4] 80148ba: 2200 movs r2, #0 80148bc: 611a str r2, [r3, #16] /* Write known values into the list item if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } 80148be: bf00 nop 80148c0: 370c adds r7, #12 80148c2: 46bd mov sp, r7 80148c4: f85d 7b04 ldr.w r7, [sp], #4 80148c8: 4770 bx lr 080148ca : /*-----------------------------------------------------------*/ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) { 80148ca: b480 push {r7} 80148cc: b085 sub sp, #20 80148ce: af00 add r7, sp, #0 80148d0: 6078 str r0, [r7, #4] 80148d2: 6039 str r1, [r7, #0] ListItem_t * const pxIndex = pxList->pxIndex; 80148d4: 687b ldr r3, [r7, #4] 80148d6: 685b ldr r3, [r3, #4] 80148d8: 60fb str r3, [r7, #12] listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); /* Insert a new list item into pxList, but rather than sort the list, makes the new list item the last item to be removed by a call to listGET_OWNER_OF_NEXT_ENTRY(). */ pxNewListItem->pxNext = pxIndex; 80148da: 683b ldr r3, [r7, #0] 80148dc: 68fa ldr r2, [r7, #12] 80148de: 605a str r2, [r3, #4] pxNewListItem->pxPrevious = pxIndex->pxPrevious; 80148e0: 68fb ldr r3, [r7, #12] 80148e2: 689a ldr r2, [r3, #8] 80148e4: 683b ldr r3, [r7, #0] 80148e6: 609a str r2, [r3, #8] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); pxIndex->pxPrevious->pxNext = pxNewListItem; 80148e8: 68fb ldr r3, [r7, #12] 80148ea: 689b ldr r3, [r3, #8] 80148ec: 683a ldr r2, [r7, #0] 80148ee: 605a str r2, [r3, #4] pxIndex->pxPrevious = pxNewListItem; 80148f0: 68fb ldr r3, [r7, #12] 80148f2: 683a ldr r2, [r7, #0] 80148f4: 609a str r2, [r3, #8] /* Remember which list the item is in. */ pxNewListItem->pxContainer = pxList; 80148f6: 683b ldr r3, [r7, #0] 80148f8: 687a ldr r2, [r7, #4] 80148fa: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 80148fc: 687b ldr r3, [r7, #4] 80148fe: 681b ldr r3, [r3, #0] 8014900: 1c5a adds r2, r3, #1 8014902: 687b ldr r3, [r7, #4] 8014904: 601a str r2, [r3, #0] } 8014906: bf00 nop 8014908: 3714 adds r7, #20 801490a: 46bd mov sp, r7 801490c: f85d 7b04 ldr.w r7, [sp], #4 8014910: 4770 bx lr 08014912 : /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8014912: b480 push {r7} 8014914: b085 sub sp, #20 8014916: af00 add r7, sp, #0 8014918: 6078 str r0, [r7, #4] 801491a: 6039 str r1, [r7, #0] ListItem_t *pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; 801491c: 683b ldr r3, [r7, #0] 801491e: 681b ldr r3, [r3, #0] 8014920: 60bb str r3, [r7, #8] new list item should be placed after it. This ensures that TCBs which are stored in ready lists (all of which have the same xItemValue value) get a share of the CPU. However, if the xItemValue is the same as the back marker the iteration loop below will not end. Therefore the value is checked first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) 8014922: 68bb ldr r3, [r7, #8] 8014924: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014928: d103 bne.n 8014932 { pxIterator = pxList->xListEnd.pxPrevious; 801492a: 687b ldr r3, [r7, #4] 801492c: 691b ldr r3, [r3, #16] 801492e: 60fb str r3, [r7, #12] 8014930: e00c b.n 801494c 4) Using a queue or semaphore before it has been initialised or before the scheduler has been started (are interrupts firing before vTaskStartScheduler() has been called?). **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ 8014932: 687b ldr r3, [r7, #4] 8014934: 3308 adds r3, #8 8014936: 60fb str r3, [r7, #12] 8014938: e002 b.n 8014940 801493a: 68fb ldr r3, [r7, #12] 801493c: 685b ldr r3, [r3, #4] 801493e: 60fb str r3, [r7, #12] 8014940: 68fb ldr r3, [r7, #12] 8014942: 685b ldr r3, [r3, #4] 8014944: 681b ldr r3, [r3, #0] 8014946: 68ba ldr r2, [r7, #8] 8014948: 429a cmp r2, r3 801494a: d2f6 bcs.n 801493a /* There is nothing to do here, just iterating to the wanted insertion position. */ } } pxNewListItem->pxNext = pxIterator->pxNext; 801494c: 68fb ldr r3, [r7, #12] 801494e: 685a ldr r2, [r3, #4] 8014950: 683b ldr r3, [r7, #0] 8014952: 605a str r2, [r3, #4] pxNewListItem->pxNext->pxPrevious = pxNewListItem; 8014954: 683b ldr r3, [r7, #0] 8014956: 685b ldr r3, [r3, #4] 8014958: 683a ldr r2, [r7, #0] 801495a: 609a str r2, [r3, #8] pxNewListItem->pxPrevious = pxIterator; 801495c: 683b ldr r3, [r7, #0] 801495e: 68fa ldr r2, [r7, #12] 8014960: 609a str r2, [r3, #8] pxIterator->pxNext = pxNewListItem; 8014962: 68fb ldr r3, [r7, #12] 8014964: 683a ldr r2, [r7, #0] 8014966: 605a str r2, [r3, #4] /* Remember which list the item is in. This allows fast removal of the item later. */ pxNewListItem->pxContainer = pxList; 8014968: 683b ldr r3, [r7, #0] 801496a: 687a ldr r2, [r7, #4] 801496c: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 801496e: 687b ldr r3, [r7, #4] 8014970: 681b ldr r3, [r3, #0] 8014972: 1c5a adds r2, r3, #1 8014974: 687b ldr r3, [r7, #4] 8014976: 601a str r2, [r3, #0] } 8014978: bf00 nop 801497a: 3714 adds r7, #20 801497c: 46bd mov sp, r7 801497e: f85d 7b04 ldr.w r7, [sp], #4 8014982: 4770 bx lr 08014984 : /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { 8014984: b480 push {r7} 8014986: b085 sub sp, #20 8014988: af00 add r7, sp, #0 801498a: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list item. */ List_t * const pxList = pxItemToRemove->pxContainer; 801498c: 687b ldr r3, [r7, #4] 801498e: 691b ldr r3, [r3, #16] 8014990: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 8014992: 687b ldr r3, [r7, #4] 8014994: 685b ldr r3, [r3, #4] 8014996: 687a ldr r2, [r7, #4] 8014998: 6892 ldr r2, [r2, #8] 801499a: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; 801499c: 687b ldr r3, [r7, #4] 801499e: 689b ldr r3, [r3, #8] 80149a0: 687a ldr r2, [r7, #4] 80149a2: 6852 ldr r2, [r2, #4] 80149a4: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) 80149a6: 68fb ldr r3, [r7, #12] 80149a8: 685b ldr r3, [r3, #4] 80149aa: 687a ldr r2, [r7, #4] 80149ac: 429a cmp r2, r3 80149ae: d103 bne.n 80149b8 { pxList->pxIndex = pxItemToRemove->pxPrevious; 80149b0: 687b ldr r3, [r7, #4] 80149b2: 689a ldr r2, [r3, #8] 80149b4: 68fb ldr r3, [r7, #12] 80149b6: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; 80149b8: 687b ldr r3, [r7, #4] 80149ba: 2200 movs r2, #0 80149bc: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; 80149be: 68fb ldr r3, [r7, #12] 80149c0: 681b ldr r3, [r3, #0] 80149c2: 1e5a subs r2, r3, #1 80149c4: 68fb ldr r3, [r7, #12] 80149c6: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; 80149c8: 68fb ldr r3, [r7, #12] 80149ca: 681b ldr r3, [r3, #0] } 80149cc: 4618 mov r0, r3 80149ce: 3714 adds r7, #20 80149d0: 46bd mov sp, r7 80149d2: f85d 7b04 ldr.w r7, [sp], #4 80149d6: 4770 bx lr 080149d8 : } \ taskEXIT_CRITICAL() /*-----------------------------------------------------------*/ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) { 80149d8: b580 push {r7, lr} 80149da: b084 sub sp, #16 80149dc: af00 add r7, sp, #0 80149de: 6078 str r0, [r7, #4] 80149e0: 6039 str r1, [r7, #0] Queue_t * const pxQueue = xQueue; 80149e2: 687b ldr r3, [r7, #4] 80149e4: 60fb str r3, [r7, #12] configASSERT( pxQueue ); 80149e6: 68fb ldr r3, [r7, #12] 80149e8: 2b00 cmp r3, #0 80149ea: d10b bne.n 8014a04 portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile 80149ec: f04f 0350 mov.w r3, #80 @ 0x50 80149f0: f383 8811 msr BASEPRI, r3 80149f4: f3bf 8f6f isb sy 80149f8: f3bf 8f4f dsb sy 80149fc: 60bb str r3, [r7, #8] " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } 80149fe: bf00 nop 8014a00: bf00 nop 8014a02: e7fd b.n 8014a00 taskENTER_CRITICAL(); 8014a04: f003 f960 bl 8017cc8 { pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8014a08: 68fb ldr r3, [r7, #12] 8014a0a: 681a ldr r2, [r3, #0] 8014a0c: 68fb ldr r3, [r7, #12] 8014a0e: 6bdb ldr r3, [r3, #60] @ 0x3c 8014a10: 68f9 ldr r1, [r7, #12] 8014a12: 6c09 ldr r1, [r1, #64] @ 0x40 8014a14: fb01 f303 mul.w r3, r1, r3 8014a18: 441a add r2, r3 8014a1a: 68fb ldr r3, [r7, #12] 8014a1c: 609a str r2, [r3, #8] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 8014a1e: 68fb ldr r3, [r7, #12] 8014a20: 2200 movs r2, #0 8014a22: 639a str r2, [r3, #56] @ 0x38 pxQueue->pcWriteTo = pxQueue->pcHead; 8014a24: 68fb ldr r3, [r7, #12] 8014a26: 681a ldr r2, [r3, #0] 8014a28: 68fb ldr r3, [r7, #12] 8014a2a: 605a str r2, [r3, #4] pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8014a2c: 68fb ldr r3, [r7, #12] 8014a2e: 681a ldr r2, [r3, #0] 8014a30: 68fb ldr r3, [r7, #12] 8014a32: 6bdb ldr r3, [r3, #60] @ 0x3c 8014a34: 3b01 subs r3, #1 8014a36: 68f9 ldr r1, [r7, #12] 8014a38: 6c09 ldr r1, [r1, #64] @ 0x40 8014a3a: fb01 f303 mul.w r3, r1, r3 8014a3e: 441a add r2, r3 8014a40: 68fb ldr r3, [r7, #12] 8014a42: 60da str r2, [r3, #12] pxQueue->cRxLock = queueUNLOCKED; 8014a44: 68fb ldr r3, [r7, #12] 8014a46: 22ff movs r2, #255 @ 0xff 8014a48: f883 2044 strb.w r2, [r3, #68] @ 0x44 pxQueue->cTxLock = queueUNLOCKED; 8014a4c: 68fb ldr r3, [r7, #12] 8014a4e: 22ff movs r2, #255 @ 0xff 8014a50: f883 2045 strb.w r2, [r3, #69] @ 0x45 if( xNewQueue == pdFALSE ) 8014a54: 683b ldr r3, [r7, #0] 8014a56: 2b00 cmp r3, #0 8014a58: d114 bne.n 8014a84 /* If there are tasks blocked waiting to read from the queue, then the tasks will remain blocked as after this function exits the queue will still be empty. If there are tasks blocked waiting to write to the queue, then one should be unblocked as after this function exits it will be possible to write to it. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8014a5a: 68fb ldr r3, [r7, #12] 8014a5c: 691b ldr r3, [r3, #16] 8014a5e: 2b00 cmp r3, #0 8014a60: d01a beq.n 8014a98 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014a62: 68fb ldr r3, [r7, #12] 8014a64: 3310 adds r3, #16 8014a66: 4618 mov r0, r3 8014a68: f001 fdac bl 80165c4 8014a6c: 4603 mov r3, r0 8014a6e: 2b00 cmp r3, #0 8014a70: d012 beq.n 8014a98 { queueYIELD_IF_USING_PREEMPTION(); 8014a72: 4b0d ldr r3, [pc, #52] @ (8014aa8 ) 8014a74: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014a78: 601a str r2, [r3, #0] 8014a7a: f3bf 8f4f dsb sy 8014a7e: f3bf 8f6f isb sy 8014a82: e009 b.n 8014a98 } } else { /* Ensure the event queues start in the correct state. */ vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 8014a84: 68fb ldr r3, [r7, #12] 8014a86: 3310 adds r3, #16 8014a88: 4618 mov r0, r3 8014a8a: f7ff fef1 bl 8014870 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); 8014a8e: 68fb ldr r3, [r7, #12] 8014a90: 3324 adds r3, #36 @ 0x24 8014a92: 4618 mov r0, r3 8014a94: f7ff feec bl 8014870 } } taskEXIT_CRITICAL(); 8014a98: f003 f948 bl 8017d2c /* A value is returned for calling semantic consistency with previous versions. */ return pdPASS; 8014a9c: 2301 movs r3, #1 } 8014a9e: 4618 mov r0, r3 8014aa0: 3710 adds r7, #16 8014aa2: 46bd mov sp, r7 8014aa4: bd80 pop {r7, pc} 8014aa6: bf00 nop 8014aa8: e000ed04 .word 0xe000ed04 08014aac : /*-----------------------------------------------------------*/ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) { 8014aac: b580 push {r7, lr} 8014aae: b08e sub sp, #56 @ 0x38 8014ab0: af02 add r7, sp, #8 8014ab2: 60f8 str r0, [r7, #12] 8014ab4: 60b9 str r1, [r7, #8] 8014ab6: 607a str r2, [r7, #4] 8014ab8: 603b str r3, [r7, #0] Queue_t *pxNewQueue; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 8014aba: 68fb ldr r3, [r7, #12] 8014abc: 2b00 cmp r3, #0 8014abe: d10b bne.n 8014ad8 __asm volatile 8014ac0: f04f 0350 mov.w r3, #80 @ 0x50 8014ac4: f383 8811 msr BASEPRI, r3 8014ac8: f3bf 8f6f isb sy 8014acc: f3bf 8f4f dsb sy 8014ad0: 62bb str r3, [r7, #40] @ 0x28 } 8014ad2: bf00 nop 8014ad4: bf00 nop 8014ad6: e7fd b.n 8014ad4 /* The StaticQueue_t structure and the queue storage area must be supplied. */ configASSERT( pxStaticQueue != NULL ); 8014ad8: 683b ldr r3, [r7, #0] 8014ada: 2b00 cmp r3, #0 8014adc: d10b bne.n 8014af6 __asm volatile 8014ade: f04f 0350 mov.w r3, #80 @ 0x50 8014ae2: f383 8811 msr BASEPRI, r3 8014ae6: f3bf 8f6f isb sy 8014aea: f3bf 8f4f dsb sy 8014aee: 627b str r3, [r7, #36] @ 0x24 } 8014af0: bf00 nop 8014af2: bf00 nop 8014af4: e7fd b.n 8014af2 /* A queue storage area should be provided if the item size is not 0, and should not be provided if the item size is 0. */ configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); 8014af6: 687b ldr r3, [r7, #4] 8014af8: 2b00 cmp r3, #0 8014afa: d002 beq.n 8014b02 8014afc: 68bb ldr r3, [r7, #8] 8014afe: 2b00 cmp r3, #0 8014b00: d001 beq.n 8014b06 8014b02: 2301 movs r3, #1 8014b04: e000 b.n 8014b08 8014b06: 2300 movs r3, #0 8014b08: 2b00 cmp r3, #0 8014b0a: d10b bne.n 8014b24 __asm volatile 8014b0c: f04f 0350 mov.w r3, #80 @ 0x50 8014b10: f383 8811 msr BASEPRI, r3 8014b14: f3bf 8f6f isb sy 8014b18: f3bf 8f4f dsb sy 8014b1c: 623b str r3, [r7, #32] } 8014b1e: bf00 nop 8014b20: bf00 nop 8014b22: e7fd b.n 8014b20 configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); 8014b24: 687b ldr r3, [r7, #4] 8014b26: 2b00 cmp r3, #0 8014b28: d102 bne.n 8014b30 8014b2a: 68bb ldr r3, [r7, #8] 8014b2c: 2b00 cmp r3, #0 8014b2e: d101 bne.n 8014b34 8014b30: 2301 movs r3, #1 8014b32: e000 b.n 8014b36 8014b34: 2300 movs r3, #0 8014b36: 2b00 cmp r3, #0 8014b38: d10b bne.n 8014b52 __asm volatile 8014b3a: f04f 0350 mov.w r3, #80 @ 0x50 8014b3e: f383 8811 msr BASEPRI, r3 8014b42: f3bf 8f6f isb sy 8014b46: f3bf 8f4f dsb sy 8014b4a: 61fb str r3, [r7, #28] } 8014b4c: bf00 nop 8014b4e: bf00 nop 8014b50: e7fd b.n 8014b4e #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticQueue_t or StaticSemaphore_t equals the size of the real queue and semaphore structures. */ volatile size_t xSize = sizeof( StaticQueue_t ); 8014b52: 2350 movs r3, #80 @ 0x50 8014b54: 617b str r3, [r7, #20] configASSERT( xSize == sizeof( Queue_t ) ); 8014b56: 697b ldr r3, [r7, #20] 8014b58: 2b50 cmp r3, #80 @ 0x50 8014b5a: d00b beq.n 8014b74 __asm volatile 8014b5c: f04f 0350 mov.w r3, #80 @ 0x50 8014b60: f383 8811 msr BASEPRI, r3 8014b64: f3bf 8f6f isb sy 8014b68: f3bf 8f4f dsb sy 8014b6c: 61bb str r3, [r7, #24] } 8014b6e: bf00 nop 8014b70: bf00 nop 8014b72: e7fd b.n 8014b70 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 8014b74: 697b ldr r3, [r7, #20] #endif /* configASSERT_DEFINED */ /* The address of a statically allocated queue was passed in, use it. The address of a statically allocated storage area was also passed in but is already set. */ pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8014b76: 683b ldr r3, [r7, #0] 8014b78: 62fb str r3, [r7, #44] @ 0x2c if( pxNewQueue != NULL ) 8014b7a: 6afb ldr r3, [r7, #44] @ 0x2c 8014b7c: 2b00 cmp r3, #0 8014b7e: d00d beq.n 8014b9c #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* Queues can be allocated wither statically or dynamically, so note this queue was allocated statically in case the queue is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdTRUE; 8014b80: 6afb ldr r3, [r7, #44] @ 0x2c 8014b82: 2201 movs r2, #1 8014b84: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8014b88: f897 2038 ldrb.w r2, [r7, #56] @ 0x38 8014b8c: 6afb ldr r3, [r7, #44] @ 0x2c 8014b8e: 9300 str r3, [sp, #0] 8014b90: 4613 mov r3, r2 8014b92: 687a ldr r2, [r7, #4] 8014b94: 68b9 ldr r1, [r7, #8] 8014b96: 68f8 ldr r0, [r7, #12] 8014b98: f000 f840 bl 8014c1c { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 8014b9c: 6afb ldr r3, [r7, #44] @ 0x2c } 8014b9e: 4618 mov r0, r3 8014ba0: 3730 adds r7, #48 @ 0x30 8014ba2: 46bd mov sp, r7 8014ba4: bd80 pop {r7, pc} 08014ba6 : /*-----------------------------------------------------------*/ #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) { 8014ba6: b580 push {r7, lr} 8014ba8: b08a sub sp, #40 @ 0x28 8014baa: af02 add r7, sp, #8 8014bac: 60f8 str r0, [r7, #12] 8014bae: 60b9 str r1, [r7, #8] 8014bb0: 4613 mov r3, r2 8014bb2: 71fb strb r3, [r7, #7] Queue_t *pxNewQueue; size_t xQueueSizeInBytes; uint8_t *pucQueueStorage; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 8014bb4: 68fb ldr r3, [r7, #12] 8014bb6: 2b00 cmp r3, #0 8014bb8: d10b bne.n 8014bd2 __asm volatile 8014bba: f04f 0350 mov.w r3, #80 @ 0x50 8014bbe: f383 8811 msr BASEPRI, r3 8014bc2: f3bf 8f6f isb sy 8014bc6: f3bf 8f4f dsb sy 8014bca: 613b str r3, [r7, #16] } 8014bcc: bf00 nop 8014bce: bf00 nop 8014bd0: e7fd b.n 8014bce /* Allocate enough space to hold the maximum number of items that can be in the queue at any time. It is valid for uxItemSize to be zero in the case the queue is used as a semaphore. */ xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8014bd2: 68fb ldr r3, [r7, #12] 8014bd4: 68ba ldr r2, [r7, #8] 8014bd6: fb02 f303 mul.w r3, r2, r3 8014bda: 61fb str r3, [r7, #28] alignment requirements of the Queue_t structure - which in this case is an int8_t *. Therefore, whenever the stack alignment requirements are greater than or equal to the pointer to char requirements the cast is safe. In other cases alignment requirements are not strict (one or two bytes). */ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ 8014bdc: 69fb ldr r3, [r7, #28] 8014bde: 3350 adds r3, #80 @ 0x50 8014be0: 4618 mov r0, r3 8014be2: f003 f993 bl 8017f0c 8014be6: 61b8 str r0, [r7, #24] if( pxNewQueue != NULL ) 8014be8: 69bb ldr r3, [r7, #24] 8014bea: 2b00 cmp r3, #0 8014bec: d011 beq.n 8014c12 { /* Jump past the queue structure to find the location of the queue storage area. */ pucQueueStorage = ( uint8_t * ) pxNewQueue; 8014bee: 69bb ldr r3, [r7, #24] 8014bf0: 617b str r3, [r7, #20] pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8014bf2: 697b ldr r3, [r7, #20] 8014bf4: 3350 adds r3, #80 @ 0x50 8014bf6: 617b str r3, [r7, #20] #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { /* Queues can be created either statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdFALSE; 8014bf8: 69bb ldr r3, [r7, #24] 8014bfa: 2200 movs r2, #0 8014bfc: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_STATIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8014c00: 79fa ldrb r2, [r7, #7] 8014c02: 69bb ldr r3, [r7, #24] 8014c04: 9300 str r3, [sp, #0] 8014c06: 4613 mov r3, r2 8014c08: 697a ldr r2, [r7, #20] 8014c0a: 68b9 ldr r1, [r7, #8] 8014c0c: 68f8 ldr r0, [r7, #12] 8014c0e: f000 f805 bl 8014c1c { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 8014c12: 69bb ldr r3, [r7, #24] } 8014c14: 4618 mov r0, r3 8014c16: 3720 adds r7, #32 8014c18: 46bd mov sp, r7 8014c1a: bd80 pop {r7, pc} 08014c1c : #endif /* configSUPPORT_STATIC_ALLOCATION */ /*-----------------------------------------------------------*/ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) { 8014c1c: b580 push {r7, lr} 8014c1e: b084 sub sp, #16 8014c20: af00 add r7, sp, #0 8014c22: 60f8 str r0, [r7, #12] 8014c24: 60b9 str r1, [r7, #8] 8014c26: 607a str r2, [r7, #4] 8014c28: 70fb strb r3, [r7, #3] /* Remove compiler warnings about unused parameters should configUSE_TRACE_FACILITY not be set to 1. */ ( void ) ucQueueType; if( uxItemSize == ( UBaseType_t ) 0 ) 8014c2a: 68bb ldr r3, [r7, #8] 8014c2c: 2b00 cmp r3, #0 8014c2e: d103 bne.n 8014c38 { /* No RAM was allocated for the queue storage area, but PC head cannot be set to NULL because NULL is used as a key to say the queue is used as a mutex. Therefore just set pcHead to point to the queue as a benign value that is known to be within the memory map. */ pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; 8014c30: 69bb ldr r3, [r7, #24] 8014c32: 69ba ldr r2, [r7, #24] 8014c34: 601a str r2, [r3, #0] 8014c36: e002 b.n 8014c3e } else { /* Set the head to the start of the queue storage area. */ pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; 8014c38: 69bb ldr r3, [r7, #24] 8014c3a: 687a ldr r2, [r7, #4] 8014c3c: 601a str r2, [r3, #0] } /* Initialise the queue members as described where the queue type is defined. */ pxNewQueue->uxLength = uxQueueLength; 8014c3e: 69bb ldr r3, [r7, #24] 8014c40: 68fa ldr r2, [r7, #12] 8014c42: 63da str r2, [r3, #60] @ 0x3c pxNewQueue->uxItemSize = uxItemSize; 8014c44: 69bb ldr r3, [r7, #24] 8014c46: 68ba ldr r2, [r7, #8] 8014c48: 641a str r2, [r3, #64] @ 0x40 ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); 8014c4a: 2101 movs r1, #1 8014c4c: 69b8 ldr r0, [r7, #24] 8014c4e: f7ff fec3 bl 80149d8 #if ( configUSE_TRACE_FACILITY == 1 ) { pxNewQueue->ucQueueType = ucQueueType; 8014c52: 69bb ldr r3, [r7, #24] 8014c54: 78fa ldrb r2, [r7, #3] 8014c56: f883 204c strb.w r2, [r3, #76] @ 0x4c pxNewQueue->pxQueueSetContainer = NULL; } #endif /* configUSE_QUEUE_SETS */ traceQUEUE_CREATE( pxNewQueue ); } 8014c5a: bf00 nop 8014c5c: 3710 adds r7, #16 8014c5e: 46bd mov sp, r7 8014c60: bd80 pop {r7, pc} 08014c62 : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static void prvInitialiseMutex( Queue_t *pxNewQueue ) { 8014c62: b580 push {r7, lr} 8014c64: b082 sub sp, #8 8014c66: af00 add r7, sp, #0 8014c68: 6078 str r0, [r7, #4] if( pxNewQueue != NULL ) 8014c6a: 687b ldr r3, [r7, #4] 8014c6c: 2b00 cmp r3, #0 8014c6e: d00e beq.n 8014c8e { /* The queue create function will set all the queue structure members correctly for a generic queue, but this function is creating a mutex. Overwrite those members that need to be set differently - in particular the information required for priority inheritance. */ pxNewQueue->u.xSemaphore.xMutexHolder = NULL; 8014c70: 687b ldr r3, [r7, #4] 8014c72: 2200 movs r2, #0 8014c74: 609a str r2, [r3, #8] pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; 8014c76: 687b ldr r3, [r7, #4] 8014c78: 2200 movs r2, #0 8014c7a: 601a str r2, [r3, #0] /* In case this is a recursive mutex. */ pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; 8014c7c: 687b ldr r3, [r7, #4] 8014c7e: 2200 movs r2, #0 8014c80: 60da str r2, [r3, #12] traceCREATE_MUTEX( pxNewQueue ); /* Start with the semaphore in the expected state. */ ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); 8014c82: 2300 movs r3, #0 8014c84: 2200 movs r2, #0 8014c86: 2100 movs r1, #0 8014c88: 6878 ldr r0, [r7, #4] 8014c8a: f000 f8a3 bl 8014dd4 } else { traceCREATE_MUTEX_FAILED(); } } 8014c8e: bf00 nop 8014c90: 3708 adds r7, #8 8014c92: 46bd mov sp, r7 8014c94: bd80 pop {r7, pc} 08014c96 : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) { 8014c96: b580 push {r7, lr} 8014c98: b086 sub sp, #24 8014c9a: af00 add r7, sp, #0 8014c9c: 4603 mov r3, r0 8014c9e: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8014ca0: 2301 movs r3, #1 8014ca2: 617b str r3, [r7, #20] 8014ca4: 2300 movs r3, #0 8014ca6: 613b str r3, [r7, #16] xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); 8014ca8: 79fb ldrb r3, [r7, #7] 8014caa: 461a mov r2, r3 8014cac: 6939 ldr r1, [r7, #16] 8014cae: 6978 ldr r0, [r7, #20] 8014cb0: f7ff ff79 bl 8014ba6 8014cb4: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 8014cb6: 68f8 ldr r0, [r7, #12] 8014cb8: f7ff ffd3 bl 8014c62 return xNewQueue; 8014cbc: 68fb ldr r3, [r7, #12] } 8014cbe: 4618 mov r0, r3 8014cc0: 3718 adds r7, #24 8014cc2: 46bd mov sp, r7 8014cc4: bd80 pop {r7, pc} 08014cc6 : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) { 8014cc6: b580 push {r7, lr} 8014cc8: b088 sub sp, #32 8014cca: af02 add r7, sp, #8 8014ccc: 4603 mov r3, r0 8014cce: 6039 str r1, [r7, #0] 8014cd0: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8014cd2: 2301 movs r3, #1 8014cd4: 617b str r3, [r7, #20] 8014cd6: 2300 movs r3, #0 8014cd8: 613b str r3, [r7, #16] /* Prevent compiler warnings about unused parameters if configUSE_TRACE_FACILITY does not equal 1. */ ( void ) ucQueueType; xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); 8014cda: 79fb ldrb r3, [r7, #7] 8014cdc: 9300 str r3, [sp, #0] 8014cde: 683b ldr r3, [r7, #0] 8014ce0: 2200 movs r2, #0 8014ce2: 6939 ldr r1, [r7, #16] 8014ce4: 6978 ldr r0, [r7, #20] 8014ce6: f7ff fee1 bl 8014aac 8014cea: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 8014cec: 68f8 ldr r0, [r7, #12] 8014cee: f7ff ffb8 bl 8014c62 return xNewQueue; 8014cf2: 68fb ldr r3, [r7, #12] } 8014cf4: 4618 mov r0, r3 8014cf6: 3718 adds r7, #24 8014cf8: 46bd mov sp, r7 8014cfa: bd80 pop {r7, pc} 08014cfc : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) { 8014cfc: b590 push {r4, r7, lr} 8014cfe: b087 sub sp, #28 8014d00: af00 add r7, sp, #0 8014d02: 6078 str r0, [r7, #4] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8014d04: 687b ldr r3, [r7, #4] 8014d06: 613b str r3, [r7, #16] configASSERT( pxMutex ); 8014d08: 693b ldr r3, [r7, #16] 8014d0a: 2b00 cmp r3, #0 8014d0c: d10b bne.n 8014d26 __asm volatile 8014d0e: f04f 0350 mov.w r3, #80 @ 0x50 8014d12: f383 8811 msr BASEPRI, r3 8014d16: f3bf 8f6f isb sy 8014d1a: f3bf 8f4f dsb sy 8014d1e: 60fb str r3, [r7, #12] } 8014d20: bf00 nop 8014d22: bf00 nop 8014d24: e7fd b.n 8014d22 change outside of this task. If this task does not hold the mutex then pxMutexHolder can never coincidentally equal the tasks handle, and as this is the only condition we are interested in it does not matter if pxMutexHolder is accessed simultaneously by another task. Therefore no mutual exclusion is required to test the pxMutexHolder variable. */ if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 8014d26: 693b ldr r3, [r7, #16] 8014d28: 689c ldr r4, [r3, #8] 8014d2a: f001 fe39 bl 80169a0 8014d2e: 4603 mov r3, r0 8014d30: 429c cmp r4, r3 8014d32: d111 bne.n 8014d58 /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to the task handle, therefore no underflow check is required. Also, uxRecursiveCallCount is only modified by the mutex holder, and as there can only be one, no mutual exclusion is required to modify the uxRecursiveCallCount member. */ ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; 8014d34: 693b ldr r3, [r7, #16] 8014d36: 68db ldr r3, [r3, #12] 8014d38: 1e5a subs r2, r3, #1 8014d3a: 693b ldr r3, [r7, #16] 8014d3c: 60da str r2, [r3, #12] /* Has the recursive call count unwound to 0? */ if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) 8014d3e: 693b ldr r3, [r7, #16] 8014d40: 68db ldr r3, [r3, #12] 8014d42: 2b00 cmp r3, #0 8014d44: d105 bne.n 8014d52 { /* Return the mutex. This will automatically unblock any other task that might be waiting to access the mutex. */ ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); 8014d46: 2300 movs r3, #0 8014d48: 2200 movs r2, #0 8014d4a: 2100 movs r1, #0 8014d4c: 6938 ldr r0, [r7, #16] 8014d4e: f000 f841 bl 8014dd4 else { mtCOVERAGE_TEST_MARKER(); } xReturn = pdPASS; 8014d52: 2301 movs r3, #1 8014d54: 617b str r3, [r7, #20] 8014d56: e001 b.n 8014d5c } else { /* The mutex cannot be given because the calling task is not the holder. */ xReturn = pdFAIL; 8014d58: 2300 movs r3, #0 8014d5a: 617b str r3, [r7, #20] traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); } return xReturn; 8014d5c: 697b ldr r3, [r7, #20] } 8014d5e: 4618 mov r0, r3 8014d60: 371c adds r7, #28 8014d62: 46bd mov sp, r7 8014d64: bd90 pop {r4, r7, pc} 08014d66 : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) { 8014d66: b590 push {r4, r7, lr} 8014d68: b087 sub sp, #28 8014d6a: af00 add r7, sp, #0 8014d6c: 6078 str r0, [r7, #4] 8014d6e: 6039 str r1, [r7, #0] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8014d70: 687b ldr r3, [r7, #4] 8014d72: 613b str r3, [r7, #16] configASSERT( pxMutex ); 8014d74: 693b ldr r3, [r7, #16] 8014d76: 2b00 cmp r3, #0 8014d78: d10b bne.n 8014d92 __asm volatile 8014d7a: f04f 0350 mov.w r3, #80 @ 0x50 8014d7e: f383 8811 msr BASEPRI, r3 8014d82: f3bf 8f6f isb sy 8014d86: f3bf 8f4f dsb sy 8014d8a: 60fb str r3, [r7, #12] } 8014d8c: bf00 nop 8014d8e: bf00 nop 8014d90: e7fd b.n 8014d8e /* Comments regarding mutual exclusion as per those within xQueueGiveMutexRecursive(). */ traceTAKE_MUTEX_RECURSIVE( pxMutex ); if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 8014d92: 693b ldr r3, [r7, #16] 8014d94: 689c ldr r4, [r3, #8] 8014d96: f001 fe03 bl 80169a0 8014d9a: 4603 mov r3, r0 8014d9c: 429c cmp r4, r3 8014d9e: d107 bne.n 8014db0 { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 8014da0: 693b ldr r3, [r7, #16] 8014da2: 68db ldr r3, [r3, #12] 8014da4: 1c5a adds r2, r3, #1 8014da6: 693b ldr r3, [r7, #16] 8014da8: 60da str r2, [r3, #12] xReturn = pdPASS; 8014daa: 2301 movs r3, #1 8014dac: 617b str r3, [r7, #20] 8014dae: e00c b.n 8014dca } else { xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait ); 8014db0: 6839 ldr r1, [r7, #0] 8014db2: 6938 ldr r0, [r7, #16] 8014db4: f000 fa90 bl 80152d8 8014db8: 6178 str r0, [r7, #20] /* pdPASS will only be returned if the mutex was successfully obtained. The calling task may have entered the Blocked state before reaching here. */ if( xReturn != pdFAIL ) 8014dba: 697b ldr r3, [r7, #20] 8014dbc: 2b00 cmp r3, #0 8014dbe: d004 beq.n 8014dca { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 8014dc0: 693b ldr r3, [r7, #16] 8014dc2: 68db ldr r3, [r3, #12] 8014dc4: 1c5a adds r2, r3, #1 8014dc6: 693b ldr r3, [r7, #16] 8014dc8: 60da str r2, [r3, #12] { traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ); } } return xReturn; 8014dca: 697b ldr r3, [r7, #20] } 8014dcc: 4618 mov r0, r3 8014dce: 371c adds r7, #28 8014dd0: 46bd mov sp, r7 8014dd2: bd90 pop {r4, r7, pc} 08014dd4 : #endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) { 8014dd4: b580 push {r7, lr} 8014dd6: b08e sub sp, #56 @ 0x38 8014dd8: af00 add r7, sp, #0 8014dda: 60f8 str r0, [r7, #12] 8014ddc: 60b9 str r1, [r7, #8] 8014dde: 607a str r2, [r7, #4] 8014de0: 603b str r3, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; 8014de2: 2300 movs r3, #0 8014de4: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8014de6: 68fb ldr r3, [r7, #12] 8014de8: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 8014dea: 6b3b ldr r3, [r7, #48] @ 0x30 8014dec: 2b00 cmp r3, #0 8014dee: d10b bne.n 8014e08 __asm volatile 8014df0: f04f 0350 mov.w r3, #80 @ 0x50 8014df4: f383 8811 msr BASEPRI, r3 8014df8: f3bf 8f6f isb sy 8014dfc: f3bf 8f4f dsb sy 8014e00: 62bb str r3, [r7, #40] @ 0x28 } 8014e02: bf00 nop 8014e04: bf00 nop 8014e06: e7fd b.n 8014e04 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8014e08: 68bb ldr r3, [r7, #8] 8014e0a: 2b00 cmp r3, #0 8014e0c: d103 bne.n 8014e16 8014e0e: 6b3b ldr r3, [r7, #48] @ 0x30 8014e10: 6c1b ldr r3, [r3, #64] @ 0x40 8014e12: 2b00 cmp r3, #0 8014e14: d101 bne.n 8014e1a 8014e16: 2301 movs r3, #1 8014e18: e000 b.n 8014e1c 8014e1a: 2300 movs r3, #0 8014e1c: 2b00 cmp r3, #0 8014e1e: d10b bne.n 8014e38 __asm volatile 8014e20: f04f 0350 mov.w r3, #80 @ 0x50 8014e24: f383 8811 msr BASEPRI, r3 8014e28: f3bf 8f6f isb sy 8014e2c: f3bf 8f4f dsb sy 8014e30: 627b str r3, [r7, #36] @ 0x24 } 8014e32: bf00 nop 8014e34: bf00 nop 8014e36: e7fd b.n 8014e34 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8014e38: 683b ldr r3, [r7, #0] 8014e3a: 2b02 cmp r3, #2 8014e3c: d103 bne.n 8014e46 8014e3e: 6b3b ldr r3, [r7, #48] @ 0x30 8014e40: 6bdb ldr r3, [r3, #60] @ 0x3c 8014e42: 2b01 cmp r3, #1 8014e44: d101 bne.n 8014e4a 8014e46: 2301 movs r3, #1 8014e48: e000 b.n 8014e4c 8014e4a: 2300 movs r3, #0 8014e4c: 2b00 cmp r3, #0 8014e4e: d10b bne.n 8014e68 __asm volatile 8014e50: f04f 0350 mov.w r3, #80 @ 0x50 8014e54: f383 8811 msr BASEPRI, r3 8014e58: f3bf 8f6f isb sy 8014e5c: f3bf 8f4f dsb sy 8014e60: 623b str r3, [r7, #32] } 8014e62: bf00 nop 8014e64: bf00 nop 8014e66: e7fd b.n 8014e64 #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8014e68: f001 fdaa bl 80169c0 8014e6c: 4603 mov r3, r0 8014e6e: 2b00 cmp r3, #0 8014e70: d102 bne.n 8014e78 8014e72: 687b ldr r3, [r7, #4] 8014e74: 2b00 cmp r3, #0 8014e76: d101 bne.n 8014e7c 8014e78: 2301 movs r3, #1 8014e7a: e000 b.n 8014e7e 8014e7c: 2300 movs r3, #0 8014e7e: 2b00 cmp r3, #0 8014e80: d10b bne.n 8014e9a __asm volatile 8014e82: f04f 0350 mov.w r3, #80 @ 0x50 8014e86: f383 8811 msr BASEPRI, r3 8014e8a: f3bf 8f6f isb sy 8014e8e: f3bf 8f4f dsb sy 8014e92: 61fb str r3, [r7, #28] } 8014e94: bf00 nop 8014e96: bf00 nop 8014e98: e7fd b.n 8014e96 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 8014e9a: f002 ff15 bl 8017cc8 { /* Is there room on the queue now? The running task must be the highest priority task wanting to access the queue. If the head item in the queue is to be overwritten then it does not matter if the queue is full. */ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 8014e9e: 6b3b ldr r3, [r7, #48] @ 0x30 8014ea0: 6b9a ldr r2, [r3, #56] @ 0x38 8014ea2: 6b3b ldr r3, [r7, #48] @ 0x30 8014ea4: 6bdb ldr r3, [r3, #60] @ 0x3c 8014ea6: 429a cmp r2, r3 8014ea8: d302 bcc.n 8014eb0 8014eaa: 683b ldr r3, [r7, #0] 8014eac: 2b02 cmp r3, #2 8014eae: d129 bne.n 8014f04 } } } #else /* configUSE_QUEUE_SETS */ { xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 8014eb0: 683a ldr r2, [r7, #0] 8014eb2: 68b9 ldr r1, [r7, #8] 8014eb4: 6b38 ldr r0, [r7, #48] @ 0x30 8014eb6: f000 fbb9 bl 801562c 8014eba: 62f8 str r0, [r7, #44] @ 0x2c /* If there was a task waiting for data to arrive on the queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8014ebc: 6b3b ldr r3, [r7, #48] @ 0x30 8014ebe: 6a5b ldr r3, [r3, #36] @ 0x24 8014ec0: 2b00 cmp r3, #0 8014ec2: d010 beq.n 8014ee6 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8014ec4: 6b3b ldr r3, [r7, #48] @ 0x30 8014ec6: 3324 adds r3, #36 @ 0x24 8014ec8: 4618 mov r0, r3 8014eca: f001 fb7b bl 80165c4 8014ece: 4603 mov r3, r0 8014ed0: 2b00 cmp r3, #0 8014ed2: d013 beq.n 8014efc { /* The unblocked task has a priority higher than our own so yield immediately. Yes it is ok to do this from within the critical section - the kernel takes care of that. */ queueYIELD_IF_USING_PREEMPTION(); 8014ed4: 4b3f ldr r3, [pc, #252] @ (8014fd4 ) 8014ed6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014eda: 601a str r2, [r3, #0] 8014edc: f3bf 8f4f dsb sy 8014ee0: f3bf 8f6f isb sy 8014ee4: e00a b.n 8014efc else { mtCOVERAGE_TEST_MARKER(); } } else if( xYieldRequired != pdFALSE ) 8014ee6: 6afb ldr r3, [r7, #44] @ 0x2c 8014ee8: 2b00 cmp r3, #0 8014eea: d007 beq.n 8014efc { /* This path is a special case that will only get executed if the task was holding multiple mutexes and the mutexes were given back in an order that is different to that in which they were taken. */ queueYIELD_IF_USING_PREEMPTION(); 8014eec: 4b39 ldr r3, [pc, #228] @ (8014fd4 ) 8014eee: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014ef2: 601a str r2, [r3, #0] 8014ef4: f3bf 8f4f dsb sy 8014ef8: f3bf 8f6f isb sy mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); 8014efc: f002 ff16 bl 8017d2c return pdPASS; 8014f00: 2301 movs r3, #1 8014f02: e063 b.n 8014fcc } else { if( xTicksToWait == ( TickType_t ) 0 ) 8014f04: 687b ldr r3, [r7, #4] 8014f06: 2b00 cmp r3, #0 8014f08: d103 bne.n 8014f12 { /* The queue was full and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 8014f0a: f002 ff0f bl 8017d2c /* Return to the original privilege level before exiting the function. */ traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 8014f0e: 2300 movs r3, #0 8014f10: e05c b.n 8014fcc } else if( xEntryTimeSet == pdFALSE ) 8014f12: 6b7b ldr r3, [r7, #52] @ 0x34 8014f14: 2b00 cmp r3, #0 8014f16: d106 bne.n 8014f26 { /* The queue was full and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8014f18: f107 0314 add.w r3, r7, #20 8014f1c: 4618 mov r0, r3 8014f1e: f001 fbdd bl 80166dc xEntryTimeSet = pdTRUE; 8014f22: 2301 movs r3, #1 8014f24: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8014f26: f002 ff01 bl 8017d2c /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 8014f2a: f001 f90f bl 801614c prvLockQueue( pxQueue ); 8014f2e: f002 fecb bl 8017cc8 8014f32: 6b3b ldr r3, [r7, #48] @ 0x30 8014f34: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014f38: b25b sxtb r3, r3 8014f3a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014f3e: d103 bne.n 8014f48 8014f40: 6b3b ldr r3, [r7, #48] @ 0x30 8014f42: 2200 movs r2, #0 8014f44: f883 2044 strb.w r2, [r3, #68] @ 0x44 8014f48: 6b3b ldr r3, [r7, #48] @ 0x30 8014f4a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014f4e: b25b sxtb r3, r3 8014f50: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014f54: d103 bne.n 8014f5e 8014f56: 6b3b ldr r3, [r7, #48] @ 0x30 8014f58: 2200 movs r2, #0 8014f5a: f883 2045 strb.w r2, [r3, #69] @ 0x45 8014f5e: f002 fee5 bl 8017d2c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8014f62: 1d3a adds r2, r7, #4 8014f64: f107 0314 add.w r3, r7, #20 8014f68: 4611 mov r1, r2 8014f6a: 4618 mov r0, r3 8014f6c: f001 fbcc bl 8016708 8014f70: 4603 mov r3, r0 8014f72: 2b00 cmp r3, #0 8014f74: d124 bne.n 8014fc0 { if( prvIsQueueFull( pxQueue ) != pdFALSE ) 8014f76: 6b38 ldr r0, [r7, #48] @ 0x30 8014f78: f000 fc50 bl 801581c 8014f7c: 4603 mov r3, r0 8014f7e: 2b00 cmp r3, #0 8014f80: d018 beq.n 8014fb4 { traceBLOCKING_ON_QUEUE_SEND( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); 8014f82: 6b3b ldr r3, [r7, #48] @ 0x30 8014f84: 3310 adds r3, #16 8014f86: 687a ldr r2, [r7, #4] 8014f88: 4611 mov r1, r2 8014f8a: 4618 mov r0, r3 8014f8c: f001 fac8 bl 8016520 /* Unlocking the queue means queue events can effect the event list. It is possible that interrupts occurring now remove this task from the event list again - but as the scheduler is suspended the task will go onto the pending ready last instead of the actual ready list. */ prvUnlockQueue( pxQueue ); 8014f90: 6b38 ldr r0, [r7, #48] @ 0x30 8014f92: f000 fbdb bl 801574c /* Resuming the scheduler will move tasks from the pending ready list into the ready list - so it is feasible that this task is already in a ready list before it yields - in which case the yield will not cause a context switch unless there is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) 8014f96: f001 f8e7 bl 8016168 8014f9a: 4603 mov r3, r0 8014f9c: 2b00 cmp r3, #0 8014f9e: f47f af7c bne.w 8014e9a { portYIELD_WITHIN_API(); 8014fa2: 4b0c ldr r3, [pc, #48] @ (8014fd4 ) 8014fa4: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014fa8: 601a str r2, [r3, #0] 8014faa: f3bf 8f4f dsb sy 8014fae: f3bf 8f6f isb sy 8014fb2: e772 b.n 8014e9a } } else { /* Try again. */ prvUnlockQueue( pxQueue ); 8014fb4: 6b38 ldr r0, [r7, #48] @ 0x30 8014fb6: f000 fbc9 bl 801574c ( void ) xTaskResumeAll(); 8014fba: f001 f8d5 bl 8016168 8014fbe: e76c b.n 8014e9a } } else { /* The timeout has expired. */ prvUnlockQueue( pxQueue ); 8014fc0: 6b38 ldr r0, [r7, #48] @ 0x30 8014fc2: f000 fbc3 bl 801574c ( void ) xTaskResumeAll(); 8014fc6: f001 f8cf bl 8016168 traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 8014fca: 2300 movs r3, #0 } } /*lint -restore */ } 8014fcc: 4618 mov r0, r3 8014fce: 3738 adds r7, #56 @ 0x38 8014fd0: 46bd mov sp, r7 8014fd2: bd80 pop {r7, pc} 8014fd4: e000ed04 .word 0xe000ed04 08014fd8 : /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) { 8014fd8: b580 push {r7, lr} 8014fda: b090 sub sp, #64 @ 0x40 8014fdc: af00 add r7, sp, #0 8014fde: 60f8 str r0, [r7, #12] 8014fe0: 60b9 str r1, [r7, #8] 8014fe2: 607a str r2, [r7, #4] 8014fe4: 603b str r3, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8014fe6: 68fb ldr r3, [r7, #12] 8014fe8: 63bb str r3, [r7, #56] @ 0x38 configASSERT( pxQueue ); 8014fea: 6bbb ldr r3, [r7, #56] @ 0x38 8014fec: 2b00 cmp r3, #0 8014fee: d10b bne.n 8015008 __asm volatile 8014ff0: f04f 0350 mov.w r3, #80 @ 0x50 8014ff4: f383 8811 msr BASEPRI, r3 8014ff8: f3bf 8f6f isb sy 8014ffc: f3bf 8f4f dsb sy 8015000: 62bb str r3, [r7, #40] @ 0x28 } 8015002: bf00 nop 8015004: bf00 nop 8015006: e7fd b.n 8015004 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8015008: 68bb ldr r3, [r7, #8] 801500a: 2b00 cmp r3, #0 801500c: d103 bne.n 8015016 801500e: 6bbb ldr r3, [r7, #56] @ 0x38 8015010: 6c1b ldr r3, [r3, #64] @ 0x40 8015012: 2b00 cmp r3, #0 8015014: d101 bne.n 801501a 8015016: 2301 movs r3, #1 8015018: e000 b.n 801501c 801501a: 2300 movs r3, #0 801501c: 2b00 cmp r3, #0 801501e: d10b bne.n 8015038 __asm volatile 8015020: f04f 0350 mov.w r3, #80 @ 0x50 8015024: f383 8811 msr BASEPRI, r3 8015028: f3bf 8f6f isb sy 801502c: f3bf 8f4f dsb sy 8015030: 627b str r3, [r7, #36] @ 0x24 } 8015032: bf00 nop 8015034: bf00 nop 8015036: e7fd b.n 8015034 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8015038: 683b ldr r3, [r7, #0] 801503a: 2b02 cmp r3, #2 801503c: d103 bne.n 8015046 801503e: 6bbb ldr r3, [r7, #56] @ 0x38 8015040: 6bdb ldr r3, [r3, #60] @ 0x3c 8015042: 2b01 cmp r3, #1 8015044: d101 bne.n 801504a 8015046: 2301 movs r3, #1 8015048: e000 b.n 801504c 801504a: 2300 movs r3, #0 801504c: 2b00 cmp r3, #0 801504e: d10b bne.n 8015068 __asm volatile 8015050: f04f 0350 mov.w r3, #80 @ 0x50 8015054: f383 8811 msr BASEPRI, r3 8015058: f3bf 8f6f isb sy 801505c: f3bf 8f4f dsb sy 8015060: 623b str r3, [r7, #32] } 8015062: bf00 nop 8015064: bf00 nop 8015066: e7fd b.n 8015064 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8015068: f002 ff0e bl 8017e88 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile 801506c: f3ef 8211 mrs r2, BASEPRI 8015070: f04f 0350 mov.w r3, #80 @ 0x50 8015074: f383 8811 msr BASEPRI, r3 8015078: f3bf 8f6f isb sy 801507c: f3bf 8f4f dsb sy 8015080: 61fa str r2, [r7, #28] 8015082: 61bb str r3, [r7, #24] :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; 8015084: 69fb ldr r3, [r7, #28] /* Similar to xQueueGenericSend, except without blocking if there is no room in the queue. Also don't directly wake a task that was blocked on a queue read, instead return a flag to say whether a context switch is required or not (i.e. has a task with a higher priority than us been woken by this post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8015086: 637b str r3, [r7, #52] @ 0x34 { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 8015088: 6bbb ldr r3, [r7, #56] @ 0x38 801508a: 6b9a ldr r2, [r3, #56] @ 0x38 801508c: 6bbb ldr r3, [r7, #56] @ 0x38 801508e: 6bdb ldr r3, [r3, #60] @ 0x3c 8015090: 429a cmp r2, r3 8015092: d302 bcc.n 801509a 8015094: 683b ldr r3, [r7, #0] 8015096: 2b02 cmp r3, #2 8015098: d12f bne.n 80150fa { const int8_t cTxLock = pxQueue->cTxLock; 801509a: 6bbb ldr r3, [r7, #56] @ 0x38 801509c: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80150a0: f887 3033 strb.w r3, [r7, #51] @ 0x33 const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; 80150a4: 6bbb ldr r3, [r7, #56] @ 0x38 80150a6: 6b9b ldr r3, [r3, #56] @ 0x38 80150a8: 62fb str r3, [r7, #44] @ 0x2c /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a semaphore or mutex. That means prvCopyDataToQueue() cannot result in a task disinheriting a priority and prvCopyDataToQueue() can be called here even though the disinherit function does not check if the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 80150aa: 683a ldr r2, [r7, #0] 80150ac: 68b9 ldr r1, [r7, #8] 80150ae: 6bb8 ldr r0, [r7, #56] @ 0x38 80150b0: f000 fabc bl 801562c /* The event list is not altered if the queue is locked. This will be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 80150b4: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33 80150b8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80150bc: d112 bne.n 80150e4 } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 80150be: 6bbb ldr r3, [r7, #56] @ 0x38 80150c0: 6a5b ldr r3, [r3, #36] @ 0x24 80150c2: 2b00 cmp r3, #0 80150c4: d016 beq.n 80150f4 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 80150c6: 6bbb ldr r3, [r7, #56] @ 0x38 80150c8: 3324 adds r3, #36 @ 0x24 80150ca: 4618 mov r0, r3 80150cc: f001 fa7a bl 80165c4 80150d0: 4603 mov r3, r0 80150d2: 2b00 cmp r3, #0 80150d4: d00e beq.n 80150f4 { /* The task waiting has a higher priority so record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 80150d6: 687b ldr r3, [r7, #4] 80150d8: 2b00 cmp r3, #0 80150da: d00b beq.n 80150f4 { *pxHigherPriorityTaskWoken = pdTRUE; 80150dc: 687b ldr r3, [r7, #4] 80150de: 2201 movs r2, #1 80150e0: 601a str r2, [r3, #0] 80150e2: e007 b.n 80150f4 } else { /* Increment the lock count so the task that unlocks the queue knows that data was posted while it was locked. */ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); 80150e4: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 80150e8: 3301 adds r3, #1 80150ea: b2db uxtb r3, r3 80150ec: b25a sxtb r2, r3 80150ee: 6bbb ldr r3, [r7, #56] @ 0x38 80150f0: f883 2045 strb.w r2, [r3, #69] @ 0x45 } xReturn = pdPASS; 80150f4: 2301 movs r3, #1 80150f6: 63fb str r3, [r7, #60] @ 0x3c { 80150f8: e001 b.n 80150fe } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 80150fa: 2300 movs r3, #0 80150fc: 63fb str r3, [r7, #60] @ 0x3c 80150fe: 6b7b ldr r3, [r7, #52] @ 0x34 8015100: 617b str r3, [r7, #20] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile 8015102: 697b ldr r3, [r7, #20] 8015104: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } 8015108: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 801510a: 6bfb ldr r3, [r7, #60] @ 0x3c } 801510c: 4618 mov r0, r3 801510e: 3740 adds r7, #64 @ 0x40 8015110: 46bd mov sp, r7 8015112: bd80 pop {r7, pc} 08015114 : return xReturn; } /*-----------------------------------------------------------*/ BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) { 8015114: b580 push {r7, lr} 8015116: b08c sub sp, #48 @ 0x30 8015118: af00 add r7, sp, #0 801511a: 60f8 str r0, [r7, #12] 801511c: 60b9 str r1, [r7, #8] 801511e: 607a str r2, [r7, #4] BaseType_t xEntryTimeSet = pdFALSE; 8015120: 2300 movs r3, #0 8015122: 62fb str r3, [r7, #44] @ 0x2c TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8015124: 68fb ldr r3, [r7, #12] 8015126: 62bb str r3, [r7, #40] @ 0x28 /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); 8015128: 6abb ldr r3, [r7, #40] @ 0x28 801512a: 2b00 cmp r3, #0 801512c: d10b bne.n 8015146 __asm volatile 801512e: f04f 0350 mov.w r3, #80 @ 0x50 8015132: f383 8811 msr BASEPRI, r3 8015136: f3bf 8f6f isb sy 801513a: f3bf 8f4f dsb sy 801513e: 623b str r3, [r7, #32] } 8015140: bf00 nop 8015142: bf00 nop 8015144: e7fd b.n 8015142 /* The buffer into which data is received can only be NULL if the data size is zero (so no data is copied into the buffer. */ configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8015146: 68bb ldr r3, [r7, #8] 8015148: 2b00 cmp r3, #0 801514a: d103 bne.n 8015154 801514c: 6abb ldr r3, [r7, #40] @ 0x28 801514e: 6c1b ldr r3, [r3, #64] @ 0x40 8015150: 2b00 cmp r3, #0 8015152: d101 bne.n 8015158 8015154: 2301 movs r3, #1 8015156: e000 b.n 801515a 8015158: 2300 movs r3, #0 801515a: 2b00 cmp r3, #0 801515c: d10b bne.n 8015176 __asm volatile 801515e: f04f 0350 mov.w r3, #80 @ 0x50 8015162: f383 8811 msr BASEPRI, r3 8015166: f3bf 8f6f isb sy 801516a: f3bf 8f4f dsb sy 801516e: 61fb str r3, [r7, #28] } 8015170: bf00 nop 8015172: bf00 nop 8015174: e7fd b.n 8015172 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8015176: f001 fc23 bl 80169c0 801517a: 4603 mov r3, r0 801517c: 2b00 cmp r3, #0 801517e: d102 bne.n 8015186 8015180: 687b ldr r3, [r7, #4] 8015182: 2b00 cmp r3, #0 8015184: d101 bne.n 801518a 8015186: 2301 movs r3, #1 8015188: e000 b.n 801518c 801518a: 2300 movs r3, #0 801518c: 2b00 cmp r3, #0 801518e: d10b bne.n 80151a8 __asm volatile 8015190: f04f 0350 mov.w r3, #80 @ 0x50 8015194: f383 8811 msr BASEPRI, r3 8015198: f3bf 8f6f isb sy 801519c: f3bf 8f4f dsb sy 80151a0: 61bb str r3, [r7, #24] } 80151a2: bf00 nop 80151a4: bf00 nop 80151a6: e7fd b.n 80151a4 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 80151a8: f002 fd8e bl 8017cc8 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 80151ac: 6abb ldr r3, [r7, #40] @ 0x28 80151ae: 6b9b ldr r3, [r3, #56] @ 0x38 80151b0: 627b str r3, [r7, #36] @ 0x24 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 80151b2: 6a7b ldr r3, [r7, #36] @ 0x24 80151b4: 2b00 cmp r3, #0 80151b6: d01f beq.n 80151f8 { /* Data available, remove one item. */ prvCopyDataFromQueue( pxQueue, pvBuffer ); 80151b8: 68b9 ldr r1, [r7, #8] 80151ba: 6ab8 ldr r0, [r7, #40] @ 0x28 80151bc: f000 faa0 bl 8015700 traceQUEUE_RECEIVE( pxQueue ); pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 80151c0: 6a7b ldr r3, [r7, #36] @ 0x24 80151c2: 1e5a subs r2, r3, #1 80151c4: 6abb ldr r3, [r7, #40] @ 0x28 80151c6: 639a str r2, [r3, #56] @ 0x38 /* There is now space in the queue, were any tasks waiting to post to the queue? If so, unblock the highest priority waiting task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80151c8: 6abb ldr r3, [r7, #40] @ 0x28 80151ca: 691b ldr r3, [r3, #16] 80151cc: 2b00 cmp r3, #0 80151ce: d00f beq.n 80151f0 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80151d0: 6abb ldr r3, [r7, #40] @ 0x28 80151d2: 3310 adds r3, #16 80151d4: 4618 mov r0, r3 80151d6: f001 f9f5 bl 80165c4 80151da: 4603 mov r3, r0 80151dc: 2b00 cmp r3, #0 80151de: d007 beq.n 80151f0 { queueYIELD_IF_USING_PREEMPTION(); 80151e0: 4b3c ldr r3, [pc, #240] @ (80152d4 ) 80151e2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80151e6: 601a str r2, [r3, #0] 80151e8: f3bf 8f4f dsb sy 80151ec: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 80151f0: f002 fd9c bl 8017d2c return pdPASS; 80151f4: 2301 movs r3, #1 80151f6: e069 b.n 80152cc } else { if( xTicksToWait == ( TickType_t ) 0 ) 80151f8: 687b ldr r3, [r7, #4] 80151fa: 2b00 cmp r3, #0 80151fc: d103 bne.n 8015206 { /* The queue was empty and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 80151fe: f002 fd95 bl 8017d2c traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8015202: 2300 movs r3, #0 8015204: e062 b.n 80152cc } else if( xEntryTimeSet == pdFALSE ) 8015206: 6afb ldr r3, [r7, #44] @ 0x2c 8015208: 2b00 cmp r3, #0 801520a: d106 bne.n 801521a { /* The queue was empty and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 801520c: f107 0310 add.w r3, r7, #16 8015210: 4618 mov r0, r3 8015212: f001 fa63 bl 80166dc xEntryTimeSet = pdTRUE; 8015216: 2301 movs r3, #1 8015218: 62fb str r3, [r7, #44] @ 0x2c /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 801521a: f002 fd87 bl 8017d2c /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 801521e: f000 ff95 bl 801614c prvLockQueue( pxQueue ); 8015222: f002 fd51 bl 8017cc8 8015226: 6abb ldr r3, [r7, #40] @ 0x28 8015228: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 801522c: b25b sxtb r3, r3 801522e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015232: d103 bne.n 801523c 8015234: 6abb ldr r3, [r7, #40] @ 0x28 8015236: 2200 movs r2, #0 8015238: f883 2044 strb.w r2, [r3, #68] @ 0x44 801523c: 6abb ldr r3, [r7, #40] @ 0x28 801523e: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8015242: b25b sxtb r3, r3 8015244: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015248: d103 bne.n 8015252 801524a: 6abb ldr r3, [r7, #40] @ 0x28 801524c: 2200 movs r2, #0 801524e: f883 2045 strb.w r2, [r3, #69] @ 0x45 8015252: f002 fd6b bl 8017d2c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8015256: 1d3a adds r2, r7, #4 8015258: f107 0310 add.w r3, r7, #16 801525c: 4611 mov r1, r2 801525e: 4618 mov r0, r3 8015260: f001 fa52 bl 8016708 8015264: 4603 mov r3, r0 8015266: 2b00 cmp r3, #0 8015268: d123 bne.n 80152b2 { /* The timeout has not expired. If the queue is still empty place the task on the list of tasks waiting to receive from the queue. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 801526a: 6ab8 ldr r0, [r7, #40] @ 0x28 801526c: f000 fac0 bl 80157f0 8015270: 4603 mov r3, r0 8015272: 2b00 cmp r3, #0 8015274: d017 beq.n 80152a6 { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 8015276: 6abb ldr r3, [r7, #40] @ 0x28 8015278: 3324 adds r3, #36 @ 0x24 801527a: 687a ldr r2, [r7, #4] 801527c: 4611 mov r1, r2 801527e: 4618 mov r0, r3 8015280: f001 f94e bl 8016520 prvUnlockQueue( pxQueue ); 8015284: 6ab8 ldr r0, [r7, #40] @ 0x28 8015286: f000 fa61 bl 801574c if( xTaskResumeAll() == pdFALSE ) 801528a: f000 ff6d bl 8016168 801528e: 4603 mov r3, r0 8015290: 2b00 cmp r3, #0 8015292: d189 bne.n 80151a8 { portYIELD_WITHIN_API(); 8015294: 4b0f ldr r3, [pc, #60] @ (80152d4 ) 8015296: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801529a: 601a str r2, [r3, #0] 801529c: f3bf 8f4f dsb sy 80152a0: f3bf 8f6f isb sy 80152a4: e780 b.n 80151a8 } else { /* The queue contains data again. Loop back to try and read the data. */ prvUnlockQueue( pxQueue ); 80152a6: 6ab8 ldr r0, [r7, #40] @ 0x28 80152a8: f000 fa50 bl 801574c ( void ) xTaskResumeAll(); 80152ac: f000 ff5c bl 8016168 80152b0: e77a b.n 80151a8 } else { /* Timed out. If there is no data in the queue exit, otherwise loop back and attempt to read the data. */ prvUnlockQueue( pxQueue ); 80152b2: 6ab8 ldr r0, [r7, #40] @ 0x28 80152b4: f000 fa4a bl 801574c ( void ) xTaskResumeAll(); 80152b8: f000 ff56 bl 8016168 if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80152bc: 6ab8 ldr r0, [r7, #40] @ 0x28 80152be: f000 fa97 bl 80157f0 80152c2: 4603 mov r3, r0 80152c4: 2b00 cmp r3, #0 80152c6: f43f af6f beq.w 80151a8 { traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 80152ca: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 80152cc: 4618 mov r0, r3 80152ce: 3730 adds r7, #48 @ 0x30 80152d0: 46bd mov sp, r7 80152d2: bd80 pop {r7, pc} 80152d4: e000ed04 .word 0xe000ed04 080152d8 : /*-----------------------------------------------------------*/ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) { 80152d8: b580 push {r7, lr} 80152da: b08e sub sp, #56 @ 0x38 80152dc: af00 add r7, sp, #0 80152de: 6078 str r0, [r7, #4] 80152e0: 6039 str r1, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE; 80152e2: 2300 movs r3, #0 80152e4: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 80152e6: 687b ldr r3, [r7, #4] 80152e8: 62fb str r3, [r7, #44] @ 0x2c #if( configUSE_MUTEXES == 1 ) BaseType_t xInheritanceOccurred = pdFALSE; 80152ea: 2300 movs r3, #0 80152ec: 633b str r3, [r7, #48] @ 0x30 #endif /* Check the queue pointer is not NULL. */ configASSERT( ( pxQueue ) ); 80152ee: 6afb ldr r3, [r7, #44] @ 0x2c 80152f0: 2b00 cmp r3, #0 80152f2: d10b bne.n 801530c __asm volatile 80152f4: f04f 0350 mov.w r3, #80 @ 0x50 80152f8: f383 8811 msr BASEPRI, r3 80152fc: f3bf 8f6f isb sy 8015300: f3bf 8f4f dsb sy 8015304: 623b str r3, [r7, #32] } 8015306: bf00 nop 8015308: bf00 nop 801530a: e7fd b.n 8015308 /* Check this really is a semaphore, in which case the item size will be 0. */ configASSERT( pxQueue->uxItemSize == 0 ); 801530c: 6afb ldr r3, [r7, #44] @ 0x2c 801530e: 6c1b ldr r3, [r3, #64] @ 0x40 8015310: 2b00 cmp r3, #0 8015312: d00b beq.n 801532c __asm volatile 8015314: f04f 0350 mov.w r3, #80 @ 0x50 8015318: f383 8811 msr BASEPRI, r3 801531c: f3bf 8f6f isb sy 8015320: f3bf 8f4f dsb sy 8015324: 61fb str r3, [r7, #28] } 8015326: bf00 nop 8015328: bf00 nop 801532a: e7fd b.n 8015328 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 801532c: f001 fb48 bl 80169c0 8015330: 4603 mov r3, r0 8015332: 2b00 cmp r3, #0 8015334: d102 bne.n 801533c 8015336: 683b ldr r3, [r7, #0] 8015338: 2b00 cmp r3, #0 801533a: d101 bne.n 8015340 801533c: 2301 movs r3, #1 801533e: e000 b.n 8015342 8015340: 2300 movs r3, #0 8015342: 2b00 cmp r3, #0 8015344: d10b bne.n 801535e __asm volatile 8015346: f04f 0350 mov.w r3, #80 @ 0x50 801534a: f383 8811 msr BASEPRI, r3 801534e: f3bf 8f6f isb sy 8015352: f3bf 8f4f dsb sy 8015356: 61bb str r3, [r7, #24] } 8015358: bf00 nop 801535a: bf00 nop 801535c: e7fd b.n 801535a /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 801535e: f002 fcb3 bl 8017cc8 { /* Semaphores are queues with an item size of 0, and where the number of messages in the queue is the semaphore's count value. */ const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; 8015362: 6afb ldr r3, [r7, #44] @ 0x2c 8015364: 6b9b ldr r3, [r3, #56] @ 0x38 8015366: 62bb str r3, [r7, #40] @ 0x28 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxSemaphoreCount > ( UBaseType_t ) 0 ) 8015368: 6abb ldr r3, [r7, #40] @ 0x28 801536a: 2b00 cmp r3, #0 801536c: d024 beq.n 80153b8 { traceQUEUE_RECEIVE( pxQueue ); /* Semaphores are queues with a data size of zero and where the messages waiting is the semaphore's count. Reduce the count. */ pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; 801536e: 6abb ldr r3, [r7, #40] @ 0x28 8015370: 1e5a subs r2, r3, #1 8015372: 6afb ldr r3, [r7, #44] @ 0x2c 8015374: 639a str r2, [r3, #56] @ 0x38 #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8015376: 6afb ldr r3, [r7, #44] @ 0x2c 8015378: 681b ldr r3, [r3, #0] 801537a: 2b00 cmp r3, #0 801537c: d104 bne.n 8015388 { /* Record the information required to implement priority inheritance should it become necessary. */ pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); 801537e: f001 fc99 bl 8016cb4 8015382: 4602 mov r2, r0 8015384: 6afb ldr r3, [r7, #44] @ 0x2c 8015386: 609a str r2, [r3, #8] } #endif /* configUSE_MUTEXES */ /* Check to see if other tasks are blocked waiting to give the semaphore, and if so, unblock the highest priority such task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8015388: 6afb ldr r3, [r7, #44] @ 0x2c 801538a: 691b ldr r3, [r3, #16] 801538c: 2b00 cmp r3, #0 801538e: d00f beq.n 80153b0 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8015390: 6afb ldr r3, [r7, #44] @ 0x2c 8015392: 3310 adds r3, #16 8015394: 4618 mov r0, r3 8015396: f001 f915 bl 80165c4 801539a: 4603 mov r3, r0 801539c: 2b00 cmp r3, #0 801539e: d007 beq.n 80153b0 { queueYIELD_IF_USING_PREEMPTION(); 80153a0: 4b54 ldr r3, [pc, #336] @ (80154f4 ) 80153a2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80153a6: 601a str r2, [r3, #0] 80153a8: f3bf 8f4f dsb sy 80153ac: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 80153b0: f002 fcbc bl 8017d2c return pdPASS; 80153b4: 2301 movs r3, #1 80153b6: e098 b.n 80154ea } else { if( xTicksToWait == ( TickType_t ) 0 ) 80153b8: 683b ldr r3, [r7, #0] 80153ba: 2b00 cmp r3, #0 80153bc: d112 bne.n 80153e4 /* For inheritance to have occurred there must have been an initial timeout, and an adjusted timeout cannot become 0, as if it were 0 the function would have exited. */ #if( configUSE_MUTEXES == 1 ) { configASSERT( xInheritanceOccurred == pdFALSE ); 80153be: 6b3b ldr r3, [r7, #48] @ 0x30 80153c0: 2b00 cmp r3, #0 80153c2: d00b beq.n 80153dc __asm volatile 80153c4: f04f 0350 mov.w r3, #80 @ 0x50 80153c8: f383 8811 msr BASEPRI, r3 80153cc: f3bf 8f6f isb sy 80153d0: f3bf 8f4f dsb sy 80153d4: 617b str r3, [r7, #20] } 80153d6: bf00 nop 80153d8: bf00 nop 80153da: e7fd b.n 80153d8 } #endif /* configUSE_MUTEXES */ /* The semaphore count was 0 and no block time is specified (or the block time has expired) so exit now. */ taskEXIT_CRITICAL(); 80153dc: f002 fca6 bl 8017d2c traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 80153e0: 2300 movs r3, #0 80153e2: e082 b.n 80154ea } else if( xEntryTimeSet == pdFALSE ) 80153e4: 6b7b ldr r3, [r7, #52] @ 0x34 80153e6: 2b00 cmp r3, #0 80153e8: d106 bne.n 80153f8 { /* The semaphore count was 0 and a block time was specified so configure the timeout structure ready to block. */ vTaskInternalSetTimeOutState( &xTimeOut ); 80153ea: f107 030c add.w r3, r7, #12 80153ee: 4618 mov r0, r3 80153f0: f001 f974 bl 80166dc xEntryTimeSet = pdTRUE; 80153f4: 2301 movs r3, #1 80153f6: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 80153f8: f002 fc98 bl 8017d2c /* Interrupts and other tasks can give to and take from the semaphore now the critical section has been exited. */ vTaskSuspendAll(); 80153fc: f000 fea6 bl 801614c prvLockQueue( pxQueue ); 8015400: f002 fc62 bl 8017cc8 8015404: 6afb ldr r3, [r7, #44] @ 0x2c 8015406: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 801540a: b25b sxtb r3, r3 801540c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015410: d103 bne.n 801541a 8015412: 6afb ldr r3, [r7, #44] @ 0x2c 8015414: 2200 movs r2, #0 8015416: f883 2044 strb.w r2, [r3, #68] @ 0x44 801541a: 6afb ldr r3, [r7, #44] @ 0x2c 801541c: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8015420: b25b sxtb r3, r3 8015422: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015426: d103 bne.n 8015430 8015428: 6afb ldr r3, [r7, #44] @ 0x2c 801542a: 2200 movs r2, #0 801542c: f883 2045 strb.w r2, [r3, #69] @ 0x45 8015430: f002 fc7c bl 8017d2c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8015434: 463a mov r2, r7 8015436: f107 030c add.w r3, r7, #12 801543a: 4611 mov r1, r2 801543c: 4618 mov r0, r3 801543e: f001 f963 bl 8016708 8015442: 4603 mov r3, r0 8015444: 2b00 cmp r3, #0 8015446: d132 bne.n 80154ae { /* A block time is specified and not expired. If the semaphore count is 0 then enter the Blocked state to wait for a semaphore to become available. As semaphores are implemented with queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8015448: 6af8 ldr r0, [r7, #44] @ 0x2c 801544a: f000 f9d1 bl 80157f0 801544e: 4603 mov r3, r0 8015450: 2b00 cmp r3, #0 8015452: d026 beq.n 80154a2 { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8015454: 6afb ldr r3, [r7, #44] @ 0x2c 8015456: 681b ldr r3, [r3, #0] 8015458: 2b00 cmp r3, #0 801545a: d109 bne.n 8015470 { taskENTER_CRITICAL(); 801545c: f002 fc34 bl 8017cc8 { xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); 8015460: 6afb ldr r3, [r7, #44] @ 0x2c 8015462: 689b ldr r3, [r3, #8] 8015464: 4618 mov r0, r3 8015466: f001 fac9 bl 80169fc 801546a: 6338 str r0, [r7, #48] @ 0x30 } taskEXIT_CRITICAL(); 801546c: f002 fc5e bl 8017d2c mtCOVERAGE_TEST_MARKER(); } } #endif vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 8015470: 6afb ldr r3, [r7, #44] @ 0x2c 8015472: 3324 adds r3, #36 @ 0x24 8015474: 683a ldr r2, [r7, #0] 8015476: 4611 mov r1, r2 8015478: 4618 mov r0, r3 801547a: f001 f851 bl 8016520 prvUnlockQueue( pxQueue ); 801547e: 6af8 ldr r0, [r7, #44] @ 0x2c 8015480: f000 f964 bl 801574c if( xTaskResumeAll() == pdFALSE ) 8015484: f000 fe70 bl 8016168 8015488: 4603 mov r3, r0 801548a: 2b00 cmp r3, #0 801548c: f47f af67 bne.w 801535e { portYIELD_WITHIN_API(); 8015490: 4b18 ldr r3, [pc, #96] @ (80154f4 ) 8015492: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015496: 601a str r2, [r3, #0] 8015498: f3bf 8f4f dsb sy 801549c: f3bf 8f6f isb sy 80154a0: e75d b.n 801535e } else { /* There was no timeout and the semaphore count was not 0, so attempt to take the semaphore again. */ prvUnlockQueue( pxQueue ); 80154a2: 6af8 ldr r0, [r7, #44] @ 0x2c 80154a4: f000 f952 bl 801574c ( void ) xTaskResumeAll(); 80154a8: f000 fe5e bl 8016168 80154ac: e757 b.n 801535e } } else { /* Timed out. */ prvUnlockQueue( pxQueue ); 80154ae: 6af8 ldr r0, [r7, #44] @ 0x2c 80154b0: f000 f94c bl 801574c ( void ) xTaskResumeAll(); 80154b4: f000 fe58 bl 8016168 /* If the semaphore count is 0 exit now as the timeout has expired. Otherwise return to attempt to take the semaphore that is known to be available. As semaphores are implemented by queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80154b8: 6af8 ldr r0, [r7, #44] @ 0x2c 80154ba: f000 f999 bl 80157f0 80154be: 4603 mov r3, r0 80154c0: 2b00 cmp r3, #0 80154c2: f43f af4c beq.w 801535e #if ( configUSE_MUTEXES == 1 ) { /* xInheritanceOccurred could only have be set if pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to test the mutex type again to check it is actually a mutex. */ if( xInheritanceOccurred != pdFALSE ) 80154c6: 6b3b ldr r3, [r7, #48] @ 0x30 80154c8: 2b00 cmp r3, #0 80154ca: d00d beq.n 80154e8 { taskENTER_CRITICAL(); 80154cc: f002 fbfc bl 8017cc8 /* This task blocking on the mutex caused another task to inherit this task's priority. Now this task has timed out the priority should be disinherited again, but only as low as the next highest priority task that is waiting for the same mutex. */ uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); 80154d0: 6af8 ldr r0, [r7, #44] @ 0x2c 80154d2: f000 f893 bl 80155fc 80154d6: 6278 str r0, [r7, #36] @ 0x24 vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); 80154d8: 6afb ldr r3, [r7, #44] @ 0x2c 80154da: 689b ldr r3, [r3, #8] 80154dc: 6a79 ldr r1, [r7, #36] @ 0x24 80154de: 4618 mov r0, r3 80154e0: f001 fb64 bl 8016bac } taskEXIT_CRITICAL(); 80154e4: f002 fc22 bl 8017d2c } } #endif /* configUSE_MUTEXES */ traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 80154e8: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 80154ea: 4618 mov r0, r3 80154ec: 3738 adds r7, #56 @ 0x38 80154ee: 46bd mov sp, r7 80154f0: bd80 pop {r7, pc} 80154f2: bf00 nop 80154f4: e000ed04 .word 0xe000ed04 080154f8 : } /*lint -restore */ } /*-----------------------------------------------------------*/ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) { 80154f8: b580 push {r7, lr} 80154fa: b08e sub sp, #56 @ 0x38 80154fc: af00 add r7, sp, #0 80154fe: 60f8 str r0, [r7, #12] 8015500: 60b9 str r1, [r7, #8] 8015502: 607a str r2, [r7, #4] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8015504: 68fb ldr r3, [r7, #12] 8015506: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 8015508: 6b3b ldr r3, [r7, #48] @ 0x30 801550a: 2b00 cmp r3, #0 801550c: d10b bne.n 8015526 __asm volatile 801550e: f04f 0350 mov.w r3, #80 @ 0x50 8015512: f383 8811 msr BASEPRI, r3 8015516: f3bf 8f6f isb sy 801551a: f3bf 8f4f dsb sy 801551e: 623b str r3, [r7, #32] } 8015520: bf00 nop 8015522: bf00 nop 8015524: e7fd b.n 8015522 configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8015526: 68bb ldr r3, [r7, #8] 8015528: 2b00 cmp r3, #0 801552a: d103 bne.n 8015534 801552c: 6b3b ldr r3, [r7, #48] @ 0x30 801552e: 6c1b ldr r3, [r3, #64] @ 0x40 8015530: 2b00 cmp r3, #0 8015532: d101 bne.n 8015538 8015534: 2301 movs r3, #1 8015536: e000 b.n 801553a 8015538: 2300 movs r3, #0 801553a: 2b00 cmp r3, #0 801553c: d10b bne.n 8015556 __asm volatile 801553e: f04f 0350 mov.w r3, #80 @ 0x50 8015542: f383 8811 msr BASEPRI, r3 8015546: f3bf 8f6f isb sy 801554a: f3bf 8f4f dsb sy 801554e: 61fb str r3, [r7, #28] } 8015550: bf00 nop 8015552: bf00 nop 8015554: e7fd b.n 8015552 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8015556: f002 fc97 bl 8017e88 __asm volatile 801555a: f3ef 8211 mrs r2, BASEPRI 801555e: f04f 0350 mov.w r3, #80 @ 0x50 8015562: f383 8811 msr BASEPRI, r3 8015566: f3bf 8f6f isb sy 801556a: f3bf 8f4f dsb sy 801556e: 61ba str r2, [r7, #24] 8015570: 617b str r3, [r7, #20] return ulOriginalBASEPRI; 8015572: 69bb ldr r3, [r7, #24] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8015574: 62fb str r3, [r7, #44] @ 0x2c { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8015576: 6b3b ldr r3, [r7, #48] @ 0x30 8015578: 6b9b ldr r3, [r3, #56] @ 0x38 801557a: 62bb str r3, [r7, #40] @ 0x28 /* Cannot block in an ISR, so check there is data available. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 801557c: 6abb ldr r3, [r7, #40] @ 0x28 801557e: 2b00 cmp r3, #0 8015580: d02f beq.n 80155e2 { const int8_t cRxLock = pxQueue->cRxLock; 8015582: 6b3b ldr r3, [r7, #48] @ 0x30 8015584: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8015588: f887 3027 strb.w r3, [r7, #39] @ 0x27 traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); prvCopyDataFromQueue( pxQueue, pvBuffer ); 801558c: 68b9 ldr r1, [r7, #8] 801558e: 6b38 ldr r0, [r7, #48] @ 0x30 8015590: f000 f8b6 bl 8015700 pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 8015594: 6abb ldr r3, [r7, #40] @ 0x28 8015596: 1e5a subs r2, r3, #1 8015598: 6b3b ldr r3, [r7, #48] @ 0x30 801559a: 639a str r2, [r3, #56] @ 0x38 /* If the queue is locked the event list will not be modified. Instead update the lock count so the task that unlocks the queue will know that an ISR has removed data while the queue was locked. */ if( cRxLock == queueUNLOCKED ) 801559c: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27 80155a0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80155a4: d112 bne.n 80155cc { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80155a6: 6b3b ldr r3, [r7, #48] @ 0x30 80155a8: 691b ldr r3, [r3, #16] 80155aa: 2b00 cmp r3, #0 80155ac: d016 beq.n 80155dc { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80155ae: 6b3b ldr r3, [r7, #48] @ 0x30 80155b0: 3310 adds r3, #16 80155b2: 4618 mov r0, r3 80155b4: f001 f806 bl 80165c4 80155b8: 4603 mov r3, r0 80155ba: 2b00 cmp r3, #0 80155bc: d00e beq.n 80155dc { /* The task waiting has a higher priority than us so force a context switch. */ if( pxHigherPriorityTaskWoken != NULL ) 80155be: 687b ldr r3, [r7, #4] 80155c0: 2b00 cmp r3, #0 80155c2: d00b beq.n 80155dc { *pxHigherPriorityTaskWoken = pdTRUE; 80155c4: 687b ldr r3, [r7, #4] 80155c6: 2201 movs r2, #1 80155c8: 601a str r2, [r3, #0] 80155ca: e007 b.n 80155dc } else { /* Increment the lock count so the task that unlocks the queue knows that data was removed while it was locked. */ pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 ); 80155cc: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 80155d0: 3301 adds r3, #1 80155d2: b2db uxtb r3, r3 80155d4: b25a sxtb r2, r3 80155d6: 6b3b ldr r3, [r7, #48] @ 0x30 80155d8: f883 2044 strb.w r2, [r3, #68] @ 0x44 } xReturn = pdPASS; 80155dc: 2301 movs r3, #1 80155de: 637b str r3, [r7, #52] @ 0x34 80155e0: e001 b.n 80155e6 } else { xReturn = pdFAIL; 80155e2: 2300 movs r3, #0 80155e4: 637b str r3, [r7, #52] @ 0x34 80155e6: 6afb ldr r3, [r7, #44] @ 0x2c 80155e8: 613b str r3, [r7, #16] __asm volatile 80155ea: 693b ldr r3, [r7, #16] 80155ec: f383 8811 msr BASEPRI, r3 } 80155f0: bf00 nop traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 80155f2: 6b7b ldr r3, [r7, #52] @ 0x34 } 80155f4: 4618 mov r0, r3 80155f6: 3738 adds r7, #56 @ 0x38 80155f8: 46bd mov sp, r7 80155fa: bd80 pop {r7, pc} 080155fc : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) { 80155fc: b480 push {r7} 80155fe: b085 sub sp, #20 8015600: af00 add r7, sp, #0 8015602: 6078 str r0, [r7, #4] priority, but the waiting task times out, then the holder should disinherit the priority - but only down to the highest priority of any other tasks that are waiting for the same mutex. For this purpose, return the priority of the highest priority task that is waiting for the mutex. */ if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) 8015604: 687b ldr r3, [r7, #4] 8015606: 6a5b ldr r3, [r3, #36] @ 0x24 8015608: 2b00 cmp r3, #0 801560a: d006 beq.n 801561a { uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); 801560c: 687b ldr r3, [r7, #4] 801560e: 6b1b ldr r3, [r3, #48] @ 0x30 8015610: 681b ldr r3, [r3, #0] 8015612: f1c3 0338 rsb r3, r3, #56 @ 0x38 8015616: 60fb str r3, [r7, #12] 8015618: e001 b.n 801561e } else { uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; 801561a: 2300 movs r3, #0 801561c: 60fb str r3, [r7, #12] } return uxHighestPriorityOfWaitingTasks; 801561e: 68fb ldr r3, [r7, #12] } 8015620: 4618 mov r0, r3 8015622: 3714 adds r7, #20 8015624: 46bd mov sp, r7 8015626: f85d 7b04 ldr.w r7, [sp], #4 801562a: 4770 bx lr 0801562c : #endif /* configUSE_MUTEXES */ /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) { 801562c: b580 push {r7, lr} 801562e: b086 sub sp, #24 8015630: af00 add r7, sp, #0 8015632: 60f8 str r0, [r7, #12] 8015634: 60b9 str r1, [r7, #8] 8015636: 607a str r2, [r7, #4] BaseType_t xReturn = pdFALSE; 8015638: 2300 movs r3, #0 801563a: 617b str r3, [r7, #20] UBaseType_t uxMessagesWaiting; /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; 801563c: 68fb ldr r3, [r7, #12] 801563e: 6b9b ldr r3, [r3, #56] @ 0x38 8015640: 613b str r3, [r7, #16] if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) 8015642: 68fb ldr r3, [r7, #12] 8015644: 6c1b ldr r3, [r3, #64] @ 0x40 8015646: 2b00 cmp r3, #0 8015648: d10d bne.n 8015666 { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 801564a: 68fb ldr r3, [r7, #12] 801564c: 681b ldr r3, [r3, #0] 801564e: 2b00 cmp r3, #0 8015650: d14d bne.n 80156ee { /* The mutex is no longer being held. */ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); 8015652: 68fb ldr r3, [r7, #12] 8015654: 689b ldr r3, [r3, #8] 8015656: 4618 mov r0, r3 8015658: f001 fa38 bl 8016acc 801565c: 6178 str r0, [r7, #20] pxQueue->u.xSemaphore.xMutexHolder = NULL; 801565e: 68fb ldr r3, [r7, #12] 8015660: 2200 movs r2, #0 8015662: 609a str r2, [r3, #8] 8015664: e043 b.n 80156ee mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_MUTEXES */ } else if( xPosition == queueSEND_TO_BACK ) 8015666: 687b ldr r3, [r7, #4] 8015668: 2b00 cmp r3, #0 801566a: d119 bne.n 80156a0 { ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 801566c: 68fb ldr r3, [r7, #12] 801566e: 6858 ldr r0, [r3, #4] 8015670: 68fb ldr r3, [r7, #12] 8015672: 6c1b ldr r3, [r3, #64] @ 0x40 8015674: 461a mov r2, r3 8015676: 68b9 ldr r1, [r7, #8] 8015678: f002 fec0 bl 80183fc pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 801567c: 68fb ldr r3, [r7, #12] 801567e: 685a ldr r2, [r3, #4] 8015680: 68fb ldr r3, [r7, #12] 8015682: 6c1b ldr r3, [r3, #64] @ 0x40 8015684: 441a add r2, r3 8015686: 68fb ldr r3, [r7, #12] 8015688: 605a str r2, [r3, #4] if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 801568a: 68fb ldr r3, [r7, #12] 801568c: 685a ldr r2, [r3, #4] 801568e: 68fb ldr r3, [r7, #12] 8015690: 689b ldr r3, [r3, #8] 8015692: 429a cmp r2, r3 8015694: d32b bcc.n 80156ee { pxQueue->pcWriteTo = pxQueue->pcHead; 8015696: 68fb ldr r3, [r7, #12] 8015698: 681a ldr r2, [r3, #0] 801569a: 68fb ldr r3, [r7, #12] 801569c: 605a str r2, [r3, #4] 801569e: e026 b.n 80156ee mtCOVERAGE_TEST_MARKER(); } } else { ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ 80156a0: 68fb ldr r3, [r7, #12] 80156a2: 68d8 ldr r0, [r3, #12] 80156a4: 68fb ldr r3, [r7, #12] 80156a6: 6c1b ldr r3, [r3, #64] @ 0x40 80156a8: 461a mov r2, r3 80156aa: 68b9 ldr r1, [r7, #8] 80156ac: f002 fea6 bl 80183fc pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; 80156b0: 68fb ldr r3, [r7, #12] 80156b2: 68da ldr r2, [r3, #12] 80156b4: 68fb ldr r3, [r7, #12] 80156b6: 6c1b ldr r3, [r3, #64] @ 0x40 80156b8: 425b negs r3, r3 80156ba: 441a add r2, r3 80156bc: 68fb ldr r3, [r7, #12] 80156be: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 80156c0: 68fb ldr r3, [r7, #12] 80156c2: 68da ldr r2, [r3, #12] 80156c4: 68fb ldr r3, [r7, #12] 80156c6: 681b ldr r3, [r3, #0] 80156c8: 429a cmp r2, r3 80156ca: d207 bcs.n 80156dc { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); 80156cc: 68fb ldr r3, [r7, #12] 80156ce: 689a ldr r2, [r3, #8] 80156d0: 68fb ldr r3, [r7, #12] 80156d2: 6c1b ldr r3, [r3, #64] @ 0x40 80156d4: 425b negs r3, r3 80156d6: 441a add r2, r3 80156d8: 68fb ldr r3, [r7, #12] 80156da: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } if( xPosition == queueOVERWRITE ) 80156dc: 687b ldr r3, [r7, #4] 80156de: 2b02 cmp r3, #2 80156e0: d105 bne.n 80156ee { if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 80156e2: 693b ldr r3, [r7, #16] 80156e4: 2b00 cmp r3, #0 80156e6: d002 beq.n 80156ee { /* An item is not being added but overwritten, so subtract one from the recorded number of items in the queue so when one is added again below the number of recorded items remains correct. */ --uxMessagesWaiting; 80156e8: 693b ldr r3, [r7, #16] 80156ea: 3b01 subs r3, #1 80156ec: 613b str r3, [r7, #16] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 80156ee: 693b ldr r3, [r7, #16] 80156f0: 1c5a adds r2, r3, #1 80156f2: 68fb ldr r3, [r7, #12] 80156f4: 639a str r2, [r3, #56] @ 0x38 return xReturn; 80156f6: 697b ldr r3, [r7, #20] } 80156f8: 4618 mov r0, r3 80156fa: 3718 adds r7, #24 80156fc: 46bd mov sp, r7 80156fe: bd80 pop {r7, pc} 08015700 : /*-----------------------------------------------------------*/ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) { 8015700: b580 push {r7, lr} 8015702: b082 sub sp, #8 8015704: af00 add r7, sp, #0 8015706: 6078 str r0, [r7, #4] 8015708: 6039 str r1, [r7, #0] if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) 801570a: 687b ldr r3, [r7, #4] 801570c: 6c1b ldr r3, [r3, #64] @ 0x40 801570e: 2b00 cmp r3, #0 8015710: d018 beq.n 8015744 { pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 8015712: 687b ldr r3, [r7, #4] 8015714: 68da ldr r2, [r3, #12] 8015716: 687b ldr r3, [r7, #4] 8015718: 6c1b ldr r3, [r3, #64] @ 0x40 801571a: 441a add r2, r3 801571c: 687b ldr r3, [r7, #4] 801571e: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 8015720: 687b ldr r3, [r7, #4] 8015722: 68da ldr r2, [r3, #12] 8015724: 687b ldr r3, [r7, #4] 8015726: 689b ldr r3, [r3, #8] 8015728: 429a cmp r2, r3 801572a: d303 bcc.n 8015734 { pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; 801572c: 687b ldr r3, [r7, #4] 801572e: 681a ldr r2, [r3, #0] 8015730: 687b ldr r3, [r7, #4] 8015732: 60da str r2, [r3, #12] } else { mtCOVERAGE_TEST_MARKER(); } ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 8015734: 687b ldr r3, [r7, #4] 8015736: 68d9 ldr r1, [r3, #12] 8015738: 687b ldr r3, [r7, #4] 801573a: 6c1b ldr r3, [r3, #64] @ 0x40 801573c: 461a mov r2, r3 801573e: 6838 ldr r0, [r7, #0] 8015740: f002 fe5c bl 80183fc } } 8015744: bf00 nop 8015746: 3708 adds r7, #8 8015748: 46bd mov sp, r7 801574a: bd80 pop {r7, pc} 0801574c : /*-----------------------------------------------------------*/ static void prvUnlockQueue( Queue_t * const pxQueue ) { 801574c: b580 push {r7, lr} 801574e: b084 sub sp, #16 8015750: af00 add r7, sp, #0 8015752: 6078 str r0, [r7, #4] /* The lock counts contains the number of extra data items placed or removed from the queue while the queue was locked. When a queue is locked items can be added or removed, but the event lists cannot be updated. */ taskENTER_CRITICAL(); 8015754: f002 fab8 bl 8017cc8 { int8_t cTxLock = pxQueue->cTxLock; 8015758: 687b ldr r3, [r7, #4] 801575a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 801575e: 73fb strb r3, [r7, #15] /* See if data was added to the queue while it was locked. */ while( cTxLock > queueLOCKED_UNMODIFIED ) 8015760: e011 b.n 8015786 } #else /* configUSE_QUEUE_SETS */ { /* Tasks that are removed from the event list will get added to the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8015762: 687b ldr r3, [r7, #4] 8015764: 6a5b ldr r3, [r3, #36] @ 0x24 8015766: 2b00 cmp r3, #0 8015768: d012 beq.n 8015790 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 801576a: 687b ldr r3, [r7, #4] 801576c: 3324 adds r3, #36 @ 0x24 801576e: 4618 mov r0, r3 8015770: f000 ff28 bl 80165c4 8015774: 4603 mov r3, r0 8015776: 2b00 cmp r3, #0 8015778: d001 beq.n 801577e { /* The task waiting has a higher priority so record that a context switch is required. */ vTaskMissedYield(); 801577a: f001 f829 bl 80167d0 break; } } #endif /* configUSE_QUEUE_SETS */ --cTxLock; 801577e: 7bfb ldrb r3, [r7, #15] 8015780: 3b01 subs r3, #1 8015782: b2db uxtb r3, r3 8015784: 73fb strb r3, [r7, #15] while( cTxLock > queueLOCKED_UNMODIFIED ) 8015786: f997 300f ldrsb.w r3, [r7, #15] 801578a: 2b00 cmp r3, #0 801578c: dce9 bgt.n 8015762 801578e: e000 b.n 8015792 break; 8015790: bf00 nop } pxQueue->cTxLock = queueUNLOCKED; 8015792: 687b ldr r3, [r7, #4] 8015794: 22ff movs r2, #255 @ 0xff 8015796: f883 2045 strb.w r2, [r3, #69] @ 0x45 } taskEXIT_CRITICAL(); 801579a: f002 fac7 bl 8017d2c /* Do the same for the Rx lock. */ taskENTER_CRITICAL(); 801579e: f002 fa93 bl 8017cc8 { int8_t cRxLock = pxQueue->cRxLock; 80157a2: 687b ldr r3, [r7, #4] 80157a4: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80157a8: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 80157aa: e011 b.n 80157d0 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80157ac: 687b ldr r3, [r7, #4] 80157ae: 691b ldr r3, [r3, #16] 80157b0: 2b00 cmp r3, #0 80157b2: d012 beq.n 80157da { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80157b4: 687b ldr r3, [r7, #4] 80157b6: 3310 adds r3, #16 80157b8: 4618 mov r0, r3 80157ba: f000 ff03 bl 80165c4 80157be: 4603 mov r3, r0 80157c0: 2b00 cmp r3, #0 80157c2: d001 beq.n 80157c8 { vTaskMissedYield(); 80157c4: f001 f804 bl 80167d0 else { mtCOVERAGE_TEST_MARKER(); } --cRxLock; 80157c8: 7bbb ldrb r3, [r7, #14] 80157ca: 3b01 subs r3, #1 80157cc: b2db uxtb r3, r3 80157ce: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 80157d0: f997 300e ldrsb.w r3, [r7, #14] 80157d4: 2b00 cmp r3, #0 80157d6: dce9 bgt.n 80157ac 80157d8: e000 b.n 80157dc } else { break; 80157da: bf00 nop } } pxQueue->cRxLock = queueUNLOCKED; 80157dc: 687b ldr r3, [r7, #4] 80157de: 22ff movs r2, #255 @ 0xff 80157e0: f883 2044 strb.w r2, [r3, #68] @ 0x44 } taskEXIT_CRITICAL(); 80157e4: f002 faa2 bl 8017d2c } 80157e8: bf00 nop 80157ea: 3710 adds r7, #16 80157ec: 46bd mov sp, r7 80157ee: bd80 pop {r7, pc} 080157f0 : /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) { 80157f0: b580 push {r7, lr} 80157f2: b084 sub sp, #16 80157f4: af00 add r7, sp, #0 80157f6: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 80157f8: f002 fa66 bl 8017cc8 { if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) 80157fc: 687b ldr r3, [r7, #4] 80157fe: 6b9b ldr r3, [r3, #56] @ 0x38 8015800: 2b00 cmp r3, #0 8015802: d102 bne.n 801580a { xReturn = pdTRUE; 8015804: 2301 movs r3, #1 8015806: 60fb str r3, [r7, #12] 8015808: e001 b.n 801580e } else { xReturn = pdFALSE; 801580a: 2300 movs r3, #0 801580c: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 801580e: f002 fa8d bl 8017d2c return xReturn; 8015812: 68fb ldr r3, [r7, #12] } 8015814: 4618 mov r0, r3 8015816: 3710 adds r7, #16 8015818: 46bd mov sp, r7 801581a: bd80 pop {r7, pc} 0801581c : return xReturn; } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) { 801581c: b580 push {r7, lr} 801581e: b084 sub sp, #16 8015820: af00 add r7, sp, #0 8015822: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8015824: f002 fa50 bl 8017cc8 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) 8015828: 687b ldr r3, [r7, #4] 801582a: 6b9a ldr r2, [r3, #56] @ 0x38 801582c: 687b ldr r3, [r7, #4] 801582e: 6bdb ldr r3, [r3, #60] @ 0x3c 8015830: 429a cmp r2, r3 8015832: d102 bne.n 801583a { xReturn = pdTRUE; 8015834: 2301 movs r3, #1 8015836: 60fb str r3, [r7, #12] 8015838: e001 b.n 801583e } else { xReturn = pdFALSE; 801583a: 2300 movs r3, #0 801583c: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 801583e: f002 fa75 bl 8017d2c return xReturn; 8015842: 68fb ldr r3, [r7, #12] } 8015844: 4618 mov r0, r3 8015846: 3710 adds r7, #16 8015848: 46bd mov sp, r7 801584a: bd80 pop {r7, pc} 0801584c : /*-----------------------------------------------------------*/ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ { 801584c: b480 push {r7} 801584e: b085 sub sp, #20 8015850: af00 add r7, sp, #0 8015852: 6078 str r0, [r7, #4] 8015854: 6039 str r1, [r7, #0] UBaseType_t ux; /* See if there is an empty space in the registry. A NULL name denotes a free slot. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8015856: 2300 movs r3, #0 8015858: 60fb str r3, [r7, #12] 801585a: e014 b.n 8015886 { if( xQueueRegistry[ ux ].pcQueueName == NULL ) 801585c: 4a0f ldr r2, [pc, #60] @ (801589c ) 801585e: 68fb ldr r3, [r7, #12] 8015860: f852 3033 ldr.w r3, [r2, r3, lsl #3] 8015864: 2b00 cmp r3, #0 8015866: d10b bne.n 8015880 { /* Store the information on this queue. */ xQueueRegistry[ ux ].pcQueueName = pcQueueName; 8015868: 490c ldr r1, [pc, #48] @ (801589c ) 801586a: 68fb ldr r3, [r7, #12] 801586c: 683a ldr r2, [r7, #0] 801586e: f841 2033 str.w r2, [r1, r3, lsl #3] xQueueRegistry[ ux ].xHandle = xQueue; 8015872: 4a0a ldr r2, [pc, #40] @ (801589c ) 8015874: 68fb ldr r3, [r7, #12] 8015876: 00db lsls r3, r3, #3 8015878: 4413 add r3, r2 801587a: 687a ldr r2, [r7, #4] 801587c: 605a str r2, [r3, #4] traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); break; 801587e: e006 b.n 801588e for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8015880: 68fb ldr r3, [r7, #12] 8015882: 3301 adds r3, #1 8015884: 60fb str r3, [r7, #12] 8015886: 68fb ldr r3, [r7, #12] 8015888: 2b07 cmp r3, #7 801588a: d9e7 bls.n 801585c else { mtCOVERAGE_TEST_MARKER(); } } } 801588c: bf00 nop 801588e: bf00 nop 8015890: 3714 adds r7, #20 8015892: 46bd mov sp, r7 8015894: f85d 7b04 ldr.w r7, [sp], #4 8015898: 4770 bx lr 801589a: bf00 nop 801589c: 240029b8 .word 0x240029b8 080158a0 : /*-----------------------------------------------------------*/ #if ( configUSE_TIMERS == 1 ) void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 80158a0: b580 push {r7, lr} 80158a2: b086 sub sp, #24 80158a4: af00 add r7, sp, #0 80158a6: 60f8 str r0, [r7, #12] 80158a8: 60b9 str r1, [r7, #8] 80158aa: 607a str r2, [r7, #4] Queue_t * const pxQueue = xQueue; 80158ac: 68fb ldr r3, [r7, #12] 80158ae: 617b str r3, [r7, #20] will not actually cause the task to block, just place it on a blocked list. It will not block until the scheduler is unlocked - at which time a yield will be performed. If an item is added to the queue while the queue is locked, and the calling task blocks on the queue, then the calling task will be immediately unblocked when the queue is unlocked. */ prvLockQueue( pxQueue ); 80158b0: f002 fa0a bl 8017cc8 80158b4: 697b ldr r3, [r7, #20] 80158b6: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80158ba: b25b sxtb r3, r3 80158bc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80158c0: d103 bne.n 80158ca 80158c2: 697b ldr r3, [r7, #20] 80158c4: 2200 movs r2, #0 80158c6: f883 2044 strb.w r2, [r3, #68] @ 0x44 80158ca: 697b ldr r3, [r7, #20] 80158cc: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80158d0: b25b sxtb r3, r3 80158d2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80158d6: d103 bne.n 80158e0 80158d8: 697b ldr r3, [r7, #20] 80158da: 2200 movs r2, #0 80158dc: f883 2045 strb.w r2, [r3, #69] @ 0x45 80158e0: f002 fa24 bl 8017d2c if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) 80158e4: 697b ldr r3, [r7, #20] 80158e6: 6b9b ldr r3, [r3, #56] @ 0x38 80158e8: 2b00 cmp r3, #0 80158ea: d106 bne.n 80158fa { /* There is nothing in the queue, block for the specified period. */ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); 80158ec: 697b ldr r3, [r7, #20] 80158ee: 3324 adds r3, #36 @ 0x24 80158f0: 687a ldr r2, [r7, #4] 80158f2: 68b9 ldr r1, [r7, #8] 80158f4: 4618 mov r0, r3 80158f6: f000 fe39 bl 801656c } else { mtCOVERAGE_TEST_MARKER(); } prvUnlockQueue( pxQueue ); 80158fa: 6978 ldr r0, [r7, #20] 80158fc: f7ff ff26 bl 801574c } 8015900: bf00 nop 8015902: 3718 adds r7, #24 8015904: 46bd mov sp, r7 8015906: bd80 pop {r7, pc} 08015908 : return xReturn; } /*-----------------------------------------------------------*/ size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) { 8015908: b480 push {r7} 801590a: b087 sub sp, #28 801590c: af00 add r7, sp, #0 801590e: 6078 str r0, [r7, #4] const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 8015910: 687b ldr r3, [r7, #4] 8015912: 613b str r3, [r7, #16] size_t xSpace; configASSERT( pxStreamBuffer ); 8015914: 693b ldr r3, [r7, #16] 8015916: 2b00 cmp r3, #0 8015918: d10b bne.n 8015932 __asm volatile 801591a: f04f 0350 mov.w r3, #80 @ 0x50 801591e: f383 8811 msr BASEPRI, r3 8015922: f3bf 8f6f isb sy 8015926: f3bf 8f4f dsb sy 801592a: 60fb str r3, [r7, #12] } 801592c: bf00 nop 801592e: bf00 nop 8015930: e7fd b.n 801592e xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; 8015932: 693b ldr r3, [r7, #16] 8015934: 689a ldr r2, [r3, #8] 8015936: 693b ldr r3, [r7, #16] 8015938: 681b ldr r3, [r3, #0] 801593a: 4413 add r3, r2 801593c: 617b str r3, [r7, #20] xSpace -= pxStreamBuffer->xHead; 801593e: 693b ldr r3, [r7, #16] 8015940: 685b ldr r3, [r3, #4] 8015942: 697a ldr r2, [r7, #20] 8015944: 1ad3 subs r3, r2, r3 8015946: 617b str r3, [r7, #20] xSpace -= ( size_t ) 1; 8015948: 697b ldr r3, [r7, #20] 801594a: 3b01 subs r3, #1 801594c: 617b str r3, [r7, #20] if( xSpace >= pxStreamBuffer->xLength ) 801594e: 693b ldr r3, [r7, #16] 8015950: 689b ldr r3, [r3, #8] 8015952: 697a ldr r2, [r7, #20] 8015954: 429a cmp r2, r3 8015956: d304 bcc.n 8015962 { xSpace -= pxStreamBuffer->xLength; 8015958: 693b ldr r3, [r7, #16] 801595a: 689b ldr r3, [r3, #8] 801595c: 697a ldr r2, [r7, #20] 801595e: 1ad3 subs r3, r2, r3 8015960: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xSpace; 8015962: 697b ldr r3, [r7, #20] } 8015964: 4618 mov r0, r3 8015966: 371c adds r7, #28 8015968: 46bd mov sp, r7 801596a: f85d 7b04 ldr.w r7, [sp], #4 801596e: 4770 bx lr 08015970 : size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) { 8015970: b580 push {r7, lr} 8015972: b090 sub sp, #64 @ 0x40 8015974: af02 add r7, sp, #8 8015976: 60f8 str r0, [r7, #12] 8015978: 60b9 str r1, [r7, #8] 801597a: 607a str r2, [r7, #4] 801597c: 603b str r3, [r7, #0] StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 801597e: 68fb ldr r3, [r7, #12] 8015980: 62fb str r3, [r7, #44] @ 0x2c size_t xReturn, xSpace = 0; 8015982: 2300 movs r3, #0 8015984: 637b str r3, [r7, #52] @ 0x34 size_t xRequiredSpace = xDataLengthBytes; 8015986: 687b ldr r3, [r7, #4] 8015988: 633b str r3, [r7, #48] @ 0x30 TimeOut_t xTimeOut; configASSERT( pvTxData ); 801598a: 68bb ldr r3, [r7, #8] 801598c: 2b00 cmp r3, #0 801598e: d10b bne.n 80159a8 __asm volatile 8015990: f04f 0350 mov.w r3, #80 @ 0x50 8015994: f383 8811 msr BASEPRI, r3 8015998: f3bf 8f6f isb sy 801599c: f3bf 8f4f dsb sy 80159a0: 627b str r3, [r7, #36] @ 0x24 } 80159a2: bf00 nop 80159a4: bf00 nop 80159a6: e7fd b.n 80159a4 configASSERT( pxStreamBuffer ); 80159a8: 6afb ldr r3, [r7, #44] @ 0x2c 80159aa: 2b00 cmp r3, #0 80159ac: d10b bne.n 80159c6 __asm volatile 80159ae: f04f 0350 mov.w r3, #80 @ 0x50 80159b2: f383 8811 msr BASEPRI, r3 80159b6: f3bf 8f6f isb sy 80159ba: f3bf 8f4f dsb sy 80159be: 623b str r3, [r7, #32] } 80159c0: bf00 nop 80159c2: bf00 nop 80159c4: e7fd b.n 80159c2 /* This send function is used to write to both message buffers and stream buffers. If this is a message buffer then the space needed must be increased by the amount of bytes needed to store the length of the message. */ if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) 80159c6: 6afb ldr r3, [r7, #44] @ 0x2c 80159c8: 7f1b ldrb r3, [r3, #28] 80159ca: f003 0301 and.w r3, r3, #1 80159ce: 2b00 cmp r3, #0 80159d0: d012 beq.n 80159f8 { xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; 80159d2: 6b3b ldr r3, [r7, #48] @ 0x30 80159d4: 3304 adds r3, #4 80159d6: 633b str r3, [r7, #48] @ 0x30 /* Overflow? */ configASSERT( xRequiredSpace > xDataLengthBytes ); 80159d8: 6b3a ldr r2, [r7, #48] @ 0x30 80159da: 687b ldr r3, [r7, #4] 80159dc: 429a cmp r2, r3 80159de: d80b bhi.n 80159f8 __asm volatile 80159e0: f04f 0350 mov.w r3, #80 @ 0x50 80159e4: f383 8811 msr BASEPRI, r3 80159e8: f3bf 8f6f isb sy 80159ec: f3bf 8f4f dsb sy 80159f0: 61fb str r3, [r7, #28] } 80159f2: bf00 nop 80159f4: bf00 nop 80159f6: e7fd b.n 80159f4 else { mtCOVERAGE_TEST_MARKER(); } if( xTicksToWait != ( TickType_t ) 0 ) 80159f8: 683b ldr r3, [r7, #0] 80159fa: 2b00 cmp r3, #0 80159fc: d03f beq.n 8015a7e { vTaskSetTimeOutState( &xTimeOut ); 80159fe: f107 0310 add.w r3, r7, #16 8015a02: 4618 mov r0, r3 8015a04: f000 fe42 bl 801668c do { /* Wait until the required number of bytes are free in the message buffer. */ taskENTER_CRITICAL(); 8015a08: f002 f95e bl 8017cc8 { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 8015a0c: 6af8 ldr r0, [r7, #44] @ 0x2c 8015a0e: f7ff ff7b bl 8015908 8015a12: 6378 str r0, [r7, #52] @ 0x34 if( xSpace < xRequiredSpace ) 8015a14: 6b7a ldr r2, [r7, #52] @ 0x34 8015a16: 6b3b ldr r3, [r7, #48] @ 0x30 8015a18: 429a cmp r2, r3 8015a1a: d218 bcs.n 8015a4e { /* Clear notification state as going to wait for space. */ ( void ) xTaskNotifyStateClear( NULL ); 8015a1c: 2000 movs r0, #0 8015a1e: f001 fb65 bl 80170ec /* Should only be one writer. */ configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL ); 8015a22: 6afb ldr r3, [r7, #44] @ 0x2c 8015a24: 695b ldr r3, [r3, #20] 8015a26: 2b00 cmp r3, #0 8015a28: d00b beq.n 8015a42 __asm volatile 8015a2a: f04f 0350 mov.w r3, #80 @ 0x50 8015a2e: f383 8811 msr BASEPRI, r3 8015a32: f3bf 8f6f isb sy 8015a36: f3bf 8f4f dsb sy 8015a3a: 61bb str r3, [r7, #24] } 8015a3c: bf00 nop 8015a3e: bf00 nop 8015a40: e7fd b.n 8015a3e pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle(); 8015a42: f000 ffad bl 80169a0 8015a46: 4602 mov r2, r0 8015a48: 6afb ldr r3, [r7, #44] @ 0x2c 8015a4a: 615a str r2, [r3, #20] 8015a4c: e002 b.n 8015a54 } else { taskEXIT_CRITICAL(); 8015a4e: f002 f96d bl 8017d2c break; 8015a52: e014 b.n 8015a7e } } taskEXIT_CRITICAL(); 8015a54: f002 f96a bl 8017d2c traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ); ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); 8015a58: 683b ldr r3, [r7, #0] 8015a5a: 2200 movs r2, #0 8015a5c: 2100 movs r1, #0 8015a5e: 2000 movs r0, #0 8015a60: f001 f93c bl 8016cdc pxStreamBuffer->xTaskWaitingToSend = NULL; 8015a64: 6afb ldr r3, [r7, #44] @ 0x2c 8015a66: 2200 movs r2, #0 8015a68: 615a str r2, [r3, #20] } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); 8015a6a: 463a mov r2, r7 8015a6c: f107 0310 add.w r3, r7, #16 8015a70: 4611 mov r1, r2 8015a72: 4618 mov r0, r3 8015a74: f000 fe48 bl 8016708 8015a78: 4603 mov r3, r0 8015a7a: 2b00 cmp r3, #0 8015a7c: d0c4 beq.n 8015a08 else { mtCOVERAGE_TEST_MARKER(); } if( xSpace == ( size_t ) 0 ) 8015a7e: 6b7b ldr r3, [r7, #52] @ 0x34 8015a80: 2b00 cmp r3, #0 8015a82: d103 bne.n 8015a8c { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 8015a84: 6af8 ldr r0, [r7, #44] @ 0x2c 8015a86: f7ff ff3f bl 8015908 8015a8a: 6378 str r0, [r7, #52] @ 0x34 else { mtCOVERAGE_TEST_MARKER(); } xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); 8015a8c: 6b3b ldr r3, [r7, #48] @ 0x30 8015a8e: 9300 str r3, [sp, #0] 8015a90: 6b7b ldr r3, [r7, #52] @ 0x34 8015a92: 687a ldr r2, [r7, #4] 8015a94: 68b9 ldr r1, [r7, #8] 8015a96: 6af8 ldr r0, [r7, #44] @ 0x2c 8015a98: f000 f823 bl 8015ae2 8015a9c: 62b8 str r0, [r7, #40] @ 0x28 if( xReturn > ( size_t ) 0 ) 8015a9e: 6abb ldr r3, [r7, #40] @ 0x28 8015aa0: 2b00 cmp r3, #0 8015aa2: d019 beq.n 8015ad8 { traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn ); /* Was a task waiting for the data? */ if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) 8015aa4: 6af8 ldr r0, [r7, #44] @ 0x2c 8015aa6: f000 f8ce bl 8015c46 8015aaa: 4602 mov r2, r0 8015aac: 6afb ldr r3, [r7, #44] @ 0x2c 8015aae: 68db ldr r3, [r3, #12] 8015ab0: 429a cmp r2, r3 8015ab2: d311 bcc.n 8015ad8 { sbSEND_COMPLETED( pxStreamBuffer ); 8015ab4: f000 fb4a bl 801614c 8015ab8: 6afb ldr r3, [r7, #44] @ 0x2c 8015aba: 691b ldr r3, [r3, #16] 8015abc: 2b00 cmp r3, #0 8015abe: d009 beq.n 8015ad4 8015ac0: 6afb ldr r3, [r7, #44] @ 0x2c 8015ac2: 6918 ldr r0, [r3, #16] 8015ac4: 2300 movs r3, #0 8015ac6: 2200 movs r2, #0 8015ac8: 2100 movs r1, #0 8015aca: f001 f967 bl 8016d9c 8015ace: 6afb ldr r3, [r7, #44] @ 0x2c 8015ad0: 2200 movs r2, #0 8015ad2: 611a str r2, [r3, #16] 8015ad4: f000 fb48 bl 8016168 { mtCOVERAGE_TEST_MARKER(); traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ); } return xReturn; 8015ad8: 6abb ldr r3, [r7, #40] @ 0x28 } 8015ada: 4618 mov r0, r3 8015adc: 3738 adds r7, #56 @ 0x38 8015ade: 46bd mov sp, r7 8015ae0: bd80 pop {r7, pc} 08015ae2 : static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, const void * pvTxData, size_t xDataLengthBytes, size_t xSpace, size_t xRequiredSpace ) { 8015ae2: b580 push {r7, lr} 8015ae4: b086 sub sp, #24 8015ae6: af00 add r7, sp, #0 8015ae8: 60f8 str r0, [r7, #12] 8015aea: 60b9 str r1, [r7, #8] 8015aec: 607a str r2, [r7, #4] 8015aee: 603b str r3, [r7, #0] BaseType_t xShouldWrite; size_t xReturn; if( xSpace == ( size_t ) 0 ) 8015af0: 683b ldr r3, [r7, #0] 8015af2: 2b00 cmp r3, #0 8015af4: d102 bne.n 8015afc { /* Doesn't matter if this is a stream buffer or a message buffer, there is no space to write. */ xShouldWrite = pdFALSE; 8015af6: 2300 movs r3, #0 8015af8: 617b str r3, [r7, #20] 8015afa: e01d b.n 8015b38 } else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 ) 8015afc: 68fb ldr r3, [r7, #12] 8015afe: 7f1b ldrb r3, [r3, #28] 8015b00: f003 0301 and.w r3, r3, #1 8015b04: 2b00 cmp r3, #0 8015b06: d108 bne.n 8015b1a { /* This is a stream buffer, as opposed to a message buffer, so writing a stream of bytes rather than discrete messages. Write as many bytes as possible. */ xShouldWrite = pdTRUE; 8015b08: 2301 movs r3, #1 8015b0a: 617b str r3, [r7, #20] xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); 8015b0c: 687a ldr r2, [r7, #4] 8015b0e: 683b ldr r3, [r7, #0] 8015b10: 4293 cmp r3, r2 8015b12: bf28 it cs 8015b14: 4613 movcs r3, r2 8015b16: 607b str r3, [r7, #4] 8015b18: e00e b.n 8015b38 } else if( xSpace >= xRequiredSpace ) 8015b1a: 683a ldr r2, [r7, #0] 8015b1c: 6a3b ldr r3, [r7, #32] 8015b1e: 429a cmp r2, r3 8015b20: d308 bcc.n 8015b34 { /* This is a message buffer, as opposed to a stream buffer, and there is enough space to write both the message length and the message itself into the buffer. Start by writing the length of the data, the data itself will be written later in this function. */ xShouldWrite = pdTRUE; 8015b22: 2301 movs r3, #1 8015b24: 617b str r3, [r7, #20] ( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH ); 8015b26: 1d3b adds r3, r7, #4 8015b28: 2204 movs r2, #4 8015b2a: 4619 mov r1, r3 8015b2c: 68f8 ldr r0, [r7, #12] 8015b2e: f000 f815 bl 8015b5c 8015b32: e001 b.n 8015b38 } else { /* There is space available, but not enough space. */ xShouldWrite = pdFALSE; 8015b34: 2300 movs r3, #0 8015b36: 617b str r3, [r7, #20] } if( xShouldWrite != pdFALSE ) 8015b38: 697b ldr r3, [r7, #20] 8015b3a: 2b00 cmp r3, #0 8015b3c: d007 beq.n 8015b4e { /* Writes the data itself. */ xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */ 8015b3e: 687b ldr r3, [r7, #4] 8015b40: 461a mov r2, r3 8015b42: 68b9 ldr r1, [r7, #8] 8015b44: 68f8 ldr r0, [r7, #12] 8015b46: f000 f809 bl 8015b5c 8015b4a: 6138 str r0, [r7, #16] 8015b4c: e001 b.n 8015b52 } else { xReturn = 0; 8015b4e: 2300 movs r3, #0 8015b50: 613b str r3, [r7, #16] } return xReturn; 8015b52: 693b ldr r3, [r7, #16] } 8015b54: 4618 mov r0, r3 8015b56: 3718 adds r7, #24 8015b58: 46bd mov sp, r7 8015b5a: bd80 pop {r7, pc} 08015b5c : return xReturn; } /*-----------------------------------------------------------*/ static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) { 8015b5c: b580 push {r7, lr} 8015b5e: b08a sub sp, #40 @ 0x28 8015b60: af00 add r7, sp, #0 8015b62: 60f8 str r0, [r7, #12] 8015b64: 60b9 str r1, [r7, #8] 8015b66: 607a str r2, [r7, #4] size_t xNextHead, xFirstLength; configASSERT( xCount > ( size_t ) 0 ); 8015b68: 687b ldr r3, [r7, #4] 8015b6a: 2b00 cmp r3, #0 8015b6c: d10b bne.n 8015b86 __asm volatile 8015b6e: f04f 0350 mov.w r3, #80 @ 0x50 8015b72: f383 8811 msr BASEPRI, r3 8015b76: f3bf 8f6f isb sy 8015b7a: f3bf 8f4f dsb sy 8015b7e: 61fb str r3, [r7, #28] } 8015b80: bf00 nop 8015b82: bf00 nop 8015b84: e7fd b.n 8015b82 xNextHead = pxStreamBuffer->xHead; 8015b86: 68fb ldr r3, [r7, #12] 8015b88: 685b ldr r3, [r3, #4] 8015b8a: 627b str r3, [r7, #36] @ 0x24 /* Calculate the number of bytes that can be added in the first write - which may be less than the total number of bytes that need to be added if the buffer will wrap back to the beginning. */ xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount ); 8015b8c: 68fb ldr r3, [r7, #12] 8015b8e: 689a ldr r2, [r3, #8] 8015b90: 6a7b ldr r3, [r7, #36] @ 0x24 8015b92: 1ad3 subs r3, r2, r3 8015b94: 687a ldr r2, [r7, #4] 8015b96: 4293 cmp r3, r2 8015b98: bf28 it cs 8015b9a: 4613 movcs r3, r2 8015b9c: 623b str r3, [r7, #32] /* Write as many bytes as can be written in the first write. */ configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength ); 8015b9e: 6a7a ldr r2, [r7, #36] @ 0x24 8015ba0: 6a3b ldr r3, [r7, #32] 8015ba2: 441a add r2, r3 8015ba4: 68fb ldr r3, [r7, #12] 8015ba6: 689b ldr r3, [r3, #8] 8015ba8: 429a cmp r2, r3 8015baa: d90b bls.n 8015bc4 __asm volatile 8015bac: f04f 0350 mov.w r3, #80 @ 0x50 8015bb0: f383 8811 msr BASEPRI, r3 8015bb4: f3bf 8f6f isb sy 8015bb8: f3bf 8f4f dsb sy 8015bbc: 61bb str r3, [r7, #24] } 8015bbe: bf00 nop 8015bc0: bf00 nop 8015bc2: e7fd b.n 8015bc0 ( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 8015bc4: 68fb ldr r3, [r7, #12] 8015bc6: 699a ldr r2, [r3, #24] 8015bc8: 6a7b ldr r3, [r7, #36] @ 0x24 8015bca: 4413 add r3, r2 8015bcc: 6a3a ldr r2, [r7, #32] 8015bce: 68b9 ldr r1, [r7, #8] 8015bd0: 4618 mov r0, r3 8015bd2: f002 fc13 bl 80183fc /* If the number of bytes written was less than the number that could be written in the first write... */ if( xCount > xFirstLength ) 8015bd6: 687a ldr r2, [r7, #4] 8015bd8: 6a3b ldr r3, [r7, #32] 8015bda: 429a cmp r2, r3 8015bdc: d91d bls.n 8015c1a { /* ...then write the remaining bytes to the start of the buffer. */ configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength ); 8015bde: 687a ldr r2, [r7, #4] 8015be0: 6a3b ldr r3, [r7, #32] 8015be2: 1ad2 subs r2, r2, r3 8015be4: 68fb ldr r3, [r7, #12] 8015be6: 689b ldr r3, [r3, #8] 8015be8: 429a cmp r2, r3 8015bea: d90b bls.n 8015c04 __asm volatile 8015bec: f04f 0350 mov.w r3, #80 @ 0x50 8015bf0: f383 8811 msr BASEPRI, r3 8015bf4: f3bf 8f6f isb sy 8015bf8: f3bf 8f4f dsb sy 8015bfc: 617b str r3, [r7, #20] } 8015bfe: bf00 nop 8015c00: bf00 nop 8015c02: e7fd b.n 8015c00 ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 8015c04: 68fb ldr r3, [r7, #12] 8015c06: 6998 ldr r0, [r3, #24] 8015c08: 68ba ldr r2, [r7, #8] 8015c0a: 6a3b ldr r3, [r7, #32] 8015c0c: 18d1 adds r1, r2, r3 8015c0e: 687a ldr r2, [r7, #4] 8015c10: 6a3b ldr r3, [r7, #32] 8015c12: 1ad3 subs r3, r2, r3 8015c14: 461a mov r2, r3 8015c16: f002 fbf1 bl 80183fc else { mtCOVERAGE_TEST_MARKER(); } xNextHead += xCount; 8015c1a: 6a7a ldr r2, [r7, #36] @ 0x24 8015c1c: 687b ldr r3, [r7, #4] 8015c1e: 4413 add r3, r2 8015c20: 627b str r3, [r7, #36] @ 0x24 if( xNextHead >= pxStreamBuffer->xLength ) 8015c22: 68fb ldr r3, [r7, #12] 8015c24: 689b ldr r3, [r3, #8] 8015c26: 6a7a ldr r2, [r7, #36] @ 0x24 8015c28: 429a cmp r2, r3 8015c2a: d304 bcc.n 8015c36 { xNextHead -= pxStreamBuffer->xLength; 8015c2c: 68fb ldr r3, [r7, #12] 8015c2e: 689b ldr r3, [r3, #8] 8015c30: 6a7a ldr r2, [r7, #36] @ 0x24 8015c32: 1ad3 subs r3, r2, r3 8015c34: 627b str r3, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } pxStreamBuffer->xHead = xNextHead; 8015c36: 68fb ldr r3, [r7, #12] 8015c38: 6a7a ldr r2, [r7, #36] @ 0x24 8015c3a: 605a str r2, [r3, #4] return xCount; 8015c3c: 687b ldr r3, [r7, #4] } 8015c3e: 4618 mov r0, r3 8015c40: 3728 adds r7, #40 @ 0x28 8015c42: 46bd mov sp, r7 8015c44: bd80 pop {r7, pc} 08015c46 : return xCount; } /*-----------------------------------------------------------*/ static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) { 8015c46: b480 push {r7} 8015c48: b085 sub sp, #20 8015c4a: af00 add r7, sp, #0 8015c4c: 6078 str r0, [r7, #4] /* Returns the distance between xTail and xHead. */ size_t xCount; xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead; 8015c4e: 687b ldr r3, [r7, #4] 8015c50: 689a ldr r2, [r3, #8] 8015c52: 687b ldr r3, [r7, #4] 8015c54: 685b ldr r3, [r3, #4] 8015c56: 4413 add r3, r2 8015c58: 60fb str r3, [r7, #12] xCount -= pxStreamBuffer->xTail; 8015c5a: 687b ldr r3, [r7, #4] 8015c5c: 681b ldr r3, [r3, #0] 8015c5e: 68fa ldr r2, [r7, #12] 8015c60: 1ad3 subs r3, r2, r3 8015c62: 60fb str r3, [r7, #12] if ( xCount >= pxStreamBuffer->xLength ) 8015c64: 687b ldr r3, [r7, #4] 8015c66: 689b ldr r3, [r3, #8] 8015c68: 68fa ldr r2, [r7, #12] 8015c6a: 429a cmp r2, r3 8015c6c: d304 bcc.n 8015c78 { xCount -= pxStreamBuffer->xLength; 8015c6e: 687b ldr r3, [r7, #4] 8015c70: 689b ldr r3, [r3, #8] 8015c72: 68fa ldr r2, [r7, #12] 8015c74: 1ad3 subs r3, r2, r3 8015c76: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xCount; 8015c78: 68fb ldr r3, [r7, #12] } 8015c7a: 4618 mov r0, r3 8015c7c: 3714 adds r7, #20 8015c7e: 46bd mov sp, r7 8015c80: f85d 7b04 ldr.w r7, [sp], #4 8015c84: 4770 bx lr 08015c86 : const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) { 8015c86: b580 push {r7, lr} 8015c88: b08e sub sp, #56 @ 0x38 8015c8a: af04 add r7, sp, #16 8015c8c: 60f8 str r0, [r7, #12] 8015c8e: 60b9 str r1, [r7, #8] 8015c90: 607a str r2, [r7, #4] 8015c92: 603b str r3, [r7, #0] TCB_t *pxNewTCB; TaskHandle_t xReturn; configASSERT( puxStackBuffer != NULL ); 8015c94: 6b7b ldr r3, [r7, #52] @ 0x34 8015c96: 2b00 cmp r3, #0 8015c98: d10b bne.n 8015cb2 __asm volatile 8015c9a: f04f 0350 mov.w r3, #80 @ 0x50 8015c9e: f383 8811 msr BASEPRI, r3 8015ca2: f3bf 8f6f isb sy 8015ca6: f3bf 8f4f dsb sy 8015caa: 623b str r3, [r7, #32] } 8015cac: bf00 nop 8015cae: bf00 nop 8015cb0: e7fd b.n 8015cae configASSERT( pxTaskBuffer != NULL ); 8015cb2: 6bbb ldr r3, [r7, #56] @ 0x38 8015cb4: 2b00 cmp r3, #0 8015cb6: d10b bne.n 8015cd0 __asm volatile 8015cb8: f04f 0350 mov.w r3, #80 @ 0x50 8015cbc: f383 8811 msr BASEPRI, r3 8015cc0: f3bf 8f6f isb sy 8015cc4: f3bf 8f4f dsb sy 8015cc8: 61fb str r3, [r7, #28] } 8015cca: bf00 nop 8015ccc: bf00 nop 8015cce: e7fd b.n 8015ccc #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTask_t equals the size of the real task structure. */ volatile size_t xSize = sizeof( StaticTask_t ); 8015cd0: 23a8 movs r3, #168 @ 0xa8 8015cd2: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( TCB_t ) ); 8015cd4: 693b ldr r3, [r7, #16] 8015cd6: 2ba8 cmp r3, #168 @ 0xa8 8015cd8: d00b beq.n 8015cf2 __asm volatile 8015cda: f04f 0350 mov.w r3, #80 @ 0x50 8015cde: f383 8811 msr BASEPRI, r3 8015ce2: f3bf 8f6f isb sy 8015ce6: f3bf 8f4f dsb sy 8015cea: 61bb str r3, [r7, #24] } 8015cec: bf00 nop 8015cee: bf00 nop 8015cf0: e7fd b.n 8015cee ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ 8015cf2: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) 8015cf4: 6bbb ldr r3, [r7, #56] @ 0x38 8015cf6: 2b00 cmp r3, #0 8015cf8: d01e beq.n 8015d38 8015cfa: 6b7b ldr r3, [r7, #52] @ 0x34 8015cfc: 2b00 cmp r3, #0 8015cfe: d01b beq.n 8015d38 { /* The memory used for the task's TCB and stack are passed into this function - use them. */ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8015d00: 6bbb ldr r3, [r7, #56] @ 0x38 8015d02: 627b str r3, [r7, #36] @ 0x24 pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; 8015d04: 6a7b ldr r3, [r7, #36] @ 0x24 8015d06: 6b7a ldr r2, [r7, #52] @ 0x34 8015d08: 631a str r2, [r3, #48] @ 0x30 #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created statically in case the task is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; 8015d0a: 6a7b ldr r3, [r7, #36] @ 0x24 8015d0c: 2202 movs r2, #2 8015d0e: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 8015d12: 2300 movs r3, #0 8015d14: 9303 str r3, [sp, #12] 8015d16: 6a7b ldr r3, [r7, #36] @ 0x24 8015d18: 9302 str r3, [sp, #8] 8015d1a: f107 0314 add.w r3, r7, #20 8015d1e: 9301 str r3, [sp, #4] 8015d20: 6b3b ldr r3, [r7, #48] @ 0x30 8015d22: 9300 str r3, [sp, #0] 8015d24: 683b ldr r3, [r7, #0] 8015d26: 687a ldr r2, [r7, #4] 8015d28: 68b9 ldr r1, [r7, #8] 8015d2a: 68f8 ldr r0, [r7, #12] 8015d2c: f000 f850 bl 8015dd0 prvAddNewTaskToReadyList( pxNewTCB ); 8015d30: 6a78 ldr r0, [r7, #36] @ 0x24 8015d32: f000 f8f5 bl 8015f20 8015d36: e001 b.n 8015d3c } else { xReturn = NULL; 8015d38: 2300 movs r3, #0 8015d3a: 617b str r3, [r7, #20] } return xReturn; 8015d3c: 697b ldr r3, [r7, #20] } 8015d3e: 4618 mov r0, r3 8015d40: 3728 adds r7, #40 @ 0x28 8015d42: 46bd mov sp, r7 8015d44: bd80 pop {r7, pc} 08015d46 : const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const configSTACK_DEPTH_TYPE usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) { 8015d46: b580 push {r7, lr} 8015d48: b08c sub sp, #48 @ 0x30 8015d4a: af04 add r7, sp, #16 8015d4c: 60f8 str r0, [r7, #12] 8015d4e: 60b9 str r1, [r7, #8] 8015d50: 603b str r3, [r7, #0] 8015d52: 4613 mov r3, r2 8015d54: 80fb strh r3, [r7, #6] #else /* portSTACK_GROWTH */ { StackType_t *pxStack; /* Allocate space for the stack used by the task being created. */ pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ 8015d56: 88fb ldrh r3, [r7, #6] 8015d58: 009b lsls r3, r3, #2 8015d5a: 4618 mov r0, r3 8015d5c: f002 f8d6 bl 8017f0c 8015d60: 6178 str r0, [r7, #20] if( pxStack != NULL ) 8015d62: 697b ldr r3, [r7, #20] 8015d64: 2b00 cmp r3, #0 8015d66: d00e beq.n 8015d86 { /* Allocate space for the TCB. */ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ 8015d68: 20a8 movs r0, #168 @ 0xa8 8015d6a: f002 f8cf bl 8017f0c 8015d6e: 61f8 str r0, [r7, #28] if( pxNewTCB != NULL ) 8015d70: 69fb ldr r3, [r7, #28] 8015d72: 2b00 cmp r3, #0 8015d74: d003 beq.n 8015d7e { /* Store the stack location in the TCB. */ pxNewTCB->pxStack = pxStack; 8015d76: 69fb ldr r3, [r7, #28] 8015d78: 697a ldr r2, [r7, #20] 8015d7a: 631a str r2, [r3, #48] @ 0x30 8015d7c: e005 b.n 8015d8a } else { /* The stack cannot be used as the TCB was not created. Free it again. */ vPortFree( pxStack ); 8015d7e: 6978 ldr r0, [r7, #20] 8015d80: f002 f992 bl 80180a8 8015d84: e001 b.n 8015d8a } } else { pxNewTCB = NULL; 8015d86: 2300 movs r3, #0 8015d88: 61fb str r3, [r7, #28] } } #endif /* portSTACK_GROWTH */ if( pxNewTCB != NULL ) 8015d8a: 69fb ldr r3, [r7, #28] 8015d8c: 2b00 cmp r3, #0 8015d8e: d017 beq.n 8015dc0 { #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; 8015d90: 69fb ldr r3, [r7, #28] 8015d92: 2200 movs r2, #0 8015d94: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); 8015d98: 88fa ldrh r2, [r7, #6] 8015d9a: 2300 movs r3, #0 8015d9c: 9303 str r3, [sp, #12] 8015d9e: 69fb ldr r3, [r7, #28] 8015da0: 9302 str r3, [sp, #8] 8015da2: 6afb ldr r3, [r7, #44] @ 0x2c 8015da4: 9301 str r3, [sp, #4] 8015da6: 6abb ldr r3, [r7, #40] @ 0x28 8015da8: 9300 str r3, [sp, #0] 8015daa: 683b ldr r3, [r7, #0] 8015dac: 68b9 ldr r1, [r7, #8] 8015dae: 68f8 ldr r0, [r7, #12] 8015db0: f000 f80e bl 8015dd0 prvAddNewTaskToReadyList( pxNewTCB ); 8015db4: 69f8 ldr r0, [r7, #28] 8015db6: f000 f8b3 bl 8015f20 xReturn = pdPASS; 8015dba: 2301 movs r3, #1 8015dbc: 61bb str r3, [r7, #24] 8015dbe: e002 b.n 8015dc6 } else { xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; 8015dc0: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8015dc4: 61bb str r3, [r7, #24] } return xReturn; 8015dc6: 69bb ldr r3, [r7, #24] } 8015dc8: 4618 mov r0, r3 8015dca: 3720 adds r7, #32 8015dcc: 46bd mov sp, r7 8015dce: bd80 pop {r7, pc} 08015dd0 : void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, TCB_t *pxNewTCB, const MemoryRegion_t * const xRegions ) { 8015dd0: b580 push {r7, lr} 8015dd2: b088 sub sp, #32 8015dd4: af00 add r7, sp, #0 8015dd6: 60f8 str r0, [r7, #12] 8015dd8: 60b9 str r1, [r7, #8] 8015dda: 607a str r2, [r7, #4] 8015ddc: 603b str r3, [r7, #0] /* Avoid dependency on memset() if it is not required. */ #if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) { /* Fill the stack with a known value to assist debugging. */ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); 8015dde: 6b3b ldr r3, [r7, #48] @ 0x30 8015de0: 6b18 ldr r0, [r3, #48] @ 0x30 8015de2: 687b ldr r3, [r7, #4] 8015de4: 009b lsls r3, r3, #2 8015de6: 461a mov r2, r3 8015de8: 21a5 movs r1, #165 @ 0xa5 8015dea: f002 fa7d bl 80182e8 grows from high memory to low (as per the 80x86) or vice versa. portSTACK_GROWTH is used to make the result positive or negative as required by the port. */ #if( portSTACK_GROWTH < 0 ) { pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); 8015dee: 6b3b ldr r3, [r7, #48] @ 0x30 8015df0: 6b1a ldr r2, [r3, #48] @ 0x30 8015df2: 6879 ldr r1, [r7, #4] 8015df4: f06f 4340 mvn.w r3, #3221225472 @ 0xc0000000 8015df8: 440b add r3, r1 8015dfa: 009b lsls r3, r3, #2 8015dfc: 4413 add r3, r2 8015dfe: 61bb str r3, [r7, #24] pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ 8015e00: 69bb ldr r3, [r7, #24] 8015e02: f023 0307 bic.w r3, r3, #7 8015e06: 61bb str r3, [r7, #24] /* Check the alignment of the calculated top of stack is correct. */ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); 8015e08: 69bb ldr r3, [r7, #24] 8015e0a: f003 0307 and.w r3, r3, #7 8015e0e: 2b00 cmp r3, #0 8015e10: d00b beq.n 8015e2a __asm volatile 8015e12: f04f 0350 mov.w r3, #80 @ 0x50 8015e16: f383 8811 msr BASEPRI, r3 8015e1a: f3bf 8f6f isb sy 8015e1e: f3bf 8f4f dsb sy 8015e22: 617b str r3, [r7, #20] } 8015e24: bf00 nop 8015e26: bf00 nop 8015e28: e7fd b.n 8015e26 pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); } #endif /* portSTACK_GROWTH */ /* Store the task name in the TCB. */ if( pcName != NULL ) 8015e2a: 68bb ldr r3, [r7, #8] 8015e2c: 2b00 cmp r3, #0 8015e2e: d01f beq.n 8015e70 { for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8015e30: 2300 movs r3, #0 8015e32: 61fb str r3, [r7, #28] 8015e34: e012 b.n 8015e5c { pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 8015e36: 68ba ldr r2, [r7, #8] 8015e38: 69fb ldr r3, [r7, #28] 8015e3a: 4413 add r3, r2 8015e3c: 7819 ldrb r1, [r3, #0] 8015e3e: 6b3a ldr r2, [r7, #48] @ 0x30 8015e40: 69fb ldr r3, [r7, #28] 8015e42: 4413 add r3, r2 8015e44: 3334 adds r3, #52 @ 0x34 8015e46: 460a mov r2, r1 8015e48: 701a strb r2, [r3, #0] /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than configMAX_TASK_NAME_LEN characters just in case the memory after the string is not accessible (extremely unlikely). */ if( pcName[ x ] == ( char ) 0x00 ) 8015e4a: 68ba ldr r2, [r7, #8] 8015e4c: 69fb ldr r3, [r7, #28] 8015e4e: 4413 add r3, r2 8015e50: 781b ldrb r3, [r3, #0] 8015e52: 2b00 cmp r3, #0 8015e54: d006 beq.n 8015e64 for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8015e56: 69fb ldr r3, [r7, #28] 8015e58: 3301 adds r3, #1 8015e5a: 61fb str r3, [r7, #28] 8015e5c: 69fb ldr r3, [r7, #28] 8015e5e: 2b0f cmp r3, #15 8015e60: d9e9 bls.n 8015e36 8015e62: e000 b.n 8015e66 { break; 8015e64: bf00 nop } } /* Ensure the name string is terminated in the case that the string length was greater or equal to configMAX_TASK_NAME_LEN. */ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; 8015e66: 6b3b ldr r3, [r7, #48] @ 0x30 8015e68: 2200 movs r2, #0 8015e6a: f883 2043 strb.w r2, [r3, #67] @ 0x43 8015e6e: e003 b.n 8015e78 } else { /* The task has not been given a name, so just ensure there is a NULL terminator when it is read out. */ pxNewTCB->pcTaskName[ 0 ] = 0x00; 8015e70: 6b3b ldr r3, [r7, #48] @ 0x30 8015e72: 2200 movs r2, #0 8015e74: f883 2034 strb.w r2, [r3, #52] @ 0x34 } /* This is used as an array index so must ensure it's not too large. First remove the privilege bit if one is present. */ if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) 8015e78: 6abb ldr r3, [r7, #40] @ 0x28 8015e7a: 2b37 cmp r3, #55 @ 0x37 8015e7c: d901 bls.n 8015e82 { uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; 8015e7e: 2337 movs r3, #55 @ 0x37 8015e80: 62bb str r3, [r7, #40] @ 0x28 else { mtCOVERAGE_TEST_MARKER(); } pxNewTCB->uxPriority = uxPriority; 8015e82: 6b3b ldr r3, [r7, #48] @ 0x30 8015e84: 6aba ldr r2, [r7, #40] @ 0x28 8015e86: 62da str r2, [r3, #44] @ 0x2c #if ( configUSE_MUTEXES == 1 ) { pxNewTCB->uxBasePriority = uxPriority; 8015e88: 6b3b ldr r3, [r7, #48] @ 0x30 8015e8a: 6aba ldr r2, [r7, #40] @ 0x28 8015e8c: 64da str r2, [r3, #76] @ 0x4c pxNewTCB->uxMutexesHeld = 0; 8015e8e: 6b3b ldr r3, [r7, #48] @ 0x30 8015e90: 2200 movs r2, #0 8015e92: 651a str r2, [r3, #80] @ 0x50 } #endif /* configUSE_MUTEXES */ vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); 8015e94: 6b3b ldr r3, [r7, #48] @ 0x30 8015e96: 3304 adds r3, #4 8015e98: 4618 mov r0, r3 8015e9a: f7fe fd09 bl 80148b0 vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); 8015e9e: 6b3b ldr r3, [r7, #48] @ 0x30 8015ea0: 3318 adds r3, #24 8015ea2: 4618 mov r0, r3 8015ea4: f7fe fd04 bl 80148b0 /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get back to the containing TCB from a generic item in a list. */ listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); 8015ea8: 6b3b ldr r3, [r7, #48] @ 0x30 8015eaa: 6b3a ldr r2, [r7, #48] @ 0x30 8015eac: 611a str r2, [r3, #16] /* Event lists are always in priority order. */ listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8015eae: 6abb ldr r3, [r7, #40] @ 0x28 8015eb0: f1c3 0238 rsb r2, r3, #56 @ 0x38 8015eb4: 6b3b ldr r3, [r7, #48] @ 0x30 8015eb6: 619a str r2, [r3, #24] listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); 8015eb8: 6b3b ldr r3, [r7, #48] @ 0x30 8015eba: 6b3a ldr r2, [r7, #48] @ 0x30 8015ebc: 625a str r2, [r3, #36] @ 0x24 } #endif #if ( configUSE_TASK_NOTIFICATIONS == 1 ) { pxNewTCB->ulNotifiedValue = 0; 8015ebe: 6b3b ldr r3, [r7, #48] @ 0x30 8015ec0: 2200 movs r2, #0 8015ec2: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8015ec6: 6b3b ldr r3, [r7, #48] @ 0x30 8015ec8: 2200 movs r2, #0 8015eca: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 #if ( configUSE_NEWLIB_REENTRANT == 1 ) { /* Initialise this task's Newlib reent structure. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); 8015ece: 6b3b ldr r3, [r7, #48] @ 0x30 8015ed0: 3354 adds r3, #84 @ 0x54 8015ed2: 224c movs r2, #76 @ 0x4c 8015ed4: 2100 movs r1, #0 8015ed6: 4618 mov r0, r3 8015ed8: f002 fa06 bl 80182e8 8015edc: 6b3b ldr r3, [r7, #48] @ 0x30 8015ede: 4a0d ldr r2, [pc, #52] @ (8015f14 ) 8015ee0: 659a str r2, [r3, #88] @ 0x58 8015ee2: 6b3b ldr r3, [r7, #48] @ 0x30 8015ee4: 4a0c ldr r2, [pc, #48] @ (8015f18 ) 8015ee6: 65da str r2, [r3, #92] @ 0x5c 8015ee8: 6b3b ldr r3, [r7, #48] @ 0x30 8015eea: 4a0c ldr r2, [pc, #48] @ (8015f1c ) 8015eec: 661a str r2, [r3, #96] @ 0x60 } #endif /* portSTACK_GROWTH */ } #else /* portHAS_STACK_OVERFLOW_CHECKING */ { pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); 8015eee: 683a ldr r2, [r7, #0] 8015ef0: 68f9 ldr r1, [r7, #12] 8015ef2: 69b8 ldr r0, [r7, #24] 8015ef4: f001 fdb8 bl 8017a68 8015ef8: 4602 mov r2, r0 8015efa: 6b3b ldr r3, [r7, #48] @ 0x30 8015efc: 601a str r2, [r3, #0] } #endif /* portHAS_STACK_OVERFLOW_CHECKING */ } #endif /* portUSING_MPU_WRAPPERS */ if( pxCreatedTask != NULL ) 8015efe: 6afb ldr r3, [r7, #44] @ 0x2c 8015f00: 2b00 cmp r3, #0 8015f02: d002 beq.n 8015f0a { /* Pass the handle out in an anonymous way. The handle can be used to change the created task's priority, delete the created task, etc.*/ *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; 8015f04: 6afb ldr r3, [r7, #44] @ 0x2c 8015f06: 6b3a ldr r2, [r7, #48] @ 0x30 8015f08: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 8015f0a: bf00 nop 8015f0c: 3720 adds r7, #32 8015f0e: 46bd mov sp, r7 8015f10: bd80 pop {r7, pc} 8015f12: bf00 nop 8015f14: 2401304c .word 0x2401304c 8015f18: 240130b4 .word 0x240130b4 8015f1c: 2401311c .word 0x2401311c 08015f20 : /*-----------------------------------------------------------*/ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) { 8015f20: b580 push {r7, lr} 8015f22: b082 sub sp, #8 8015f24: af00 add r7, sp, #0 8015f26: 6078 str r0, [r7, #4] /* Ensure interrupts don't access the task lists while the lists are being updated. */ taskENTER_CRITICAL(); 8015f28: f001 fece bl 8017cc8 { uxCurrentNumberOfTasks++; 8015f2c: 4b2d ldr r3, [pc, #180] @ (8015fe4 ) 8015f2e: 681b ldr r3, [r3, #0] 8015f30: 3301 adds r3, #1 8015f32: 4a2c ldr r2, [pc, #176] @ (8015fe4 ) 8015f34: 6013 str r3, [r2, #0] if( pxCurrentTCB == NULL ) 8015f36: 4b2c ldr r3, [pc, #176] @ (8015fe8 ) 8015f38: 681b ldr r3, [r3, #0] 8015f3a: 2b00 cmp r3, #0 8015f3c: d109 bne.n 8015f52 { /* There are no other tasks, or all the other tasks are in the suspended state - make this the current task. */ pxCurrentTCB = pxNewTCB; 8015f3e: 4a2a ldr r2, [pc, #168] @ (8015fe8 ) 8015f40: 687b ldr r3, [r7, #4] 8015f42: 6013 str r3, [r2, #0] if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) 8015f44: 4b27 ldr r3, [pc, #156] @ (8015fe4 ) 8015f46: 681b ldr r3, [r3, #0] 8015f48: 2b01 cmp r3, #1 8015f4a: d110 bne.n 8015f6e { /* This is the first task to be created so do the preliminary initialisation required. We will not recover if this call fails, but we will report the failure. */ prvInitialiseTaskLists(); 8015f4c: f000 fc64 bl 8016818 8015f50: e00d b.n 8015f6e else { /* If the scheduler is not already running, make this task the current task if it is the highest priority task to be created so far. */ if( xSchedulerRunning == pdFALSE ) 8015f52: 4b26 ldr r3, [pc, #152] @ (8015fec ) 8015f54: 681b ldr r3, [r3, #0] 8015f56: 2b00 cmp r3, #0 8015f58: d109 bne.n 8015f6e { if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) 8015f5a: 4b23 ldr r3, [pc, #140] @ (8015fe8 ) 8015f5c: 681b ldr r3, [r3, #0] 8015f5e: 6ada ldr r2, [r3, #44] @ 0x2c 8015f60: 687b ldr r3, [r7, #4] 8015f62: 6adb ldr r3, [r3, #44] @ 0x2c 8015f64: 429a cmp r2, r3 8015f66: d802 bhi.n 8015f6e { pxCurrentTCB = pxNewTCB; 8015f68: 4a1f ldr r2, [pc, #124] @ (8015fe8 ) 8015f6a: 687b ldr r3, [r7, #4] 8015f6c: 6013 str r3, [r2, #0] { mtCOVERAGE_TEST_MARKER(); } } uxTaskNumber++; 8015f6e: 4b20 ldr r3, [pc, #128] @ (8015ff0 ) 8015f70: 681b ldr r3, [r3, #0] 8015f72: 3301 adds r3, #1 8015f74: 4a1e ldr r2, [pc, #120] @ (8015ff0 ) 8015f76: 6013 str r3, [r2, #0] #if ( configUSE_TRACE_FACILITY == 1 ) { /* Add a counter into the TCB for tracing only. */ pxNewTCB->uxTCBNumber = uxTaskNumber; 8015f78: 4b1d ldr r3, [pc, #116] @ (8015ff0 ) 8015f7a: 681a ldr r2, [r3, #0] 8015f7c: 687b ldr r3, [r7, #4] 8015f7e: 645a str r2, [r3, #68] @ 0x44 } #endif /* configUSE_TRACE_FACILITY */ traceTASK_CREATE( pxNewTCB ); prvAddTaskToReadyList( pxNewTCB ); 8015f80: 687b ldr r3, [r7, #4] 8015f82: 6ada ldr r2, [r3, #44] @ 0x2c 8015f84: 4b1b ldr r3, [pc, #108] @ (8015ff4 ) 8015f86: 681b ldr r3, [r3, #0] 8015f88: 429a cmp r2, r3 8015f8a: d903 bls.n 8015f94 8015f8c: 687b ldr r3, [r7, #4] 8015f8e: 6adb ldr r3, [r3, #44] @ 0x2c 8015f90: 4a18 ldr r2, [pc, #96] @ (8015ff4 ) 8015f92: 6013 str r3, [r2, #0] 8015f94: 687b ldr r3, [r7, #4] 8015f96: 6ada ldr r2, [r3, #44] @ 0x2c 8015f98: 4613 mov r3, r2 8015f9a: 009b lsls r3, r3, #2 8015f9c: 4413 add r3, r2 8015f9e: 009b lsls r3, r3, #2 8015fa0: 4a15 ldr r2, [pc, #84] @ (8015ff8 ) 8015fa2: 441a add r2, r3 8015fa4: 687b ldr r3, [r7, #4] 8015fa6: 3304 adds r3, #4 8015fa8: 4619 mov r1, r3 8015faa: 4610 mov r0, r2 8015fac: f7fe fc8d bl 80148ca portSETUP_TCB( pxNewTCB ); } taskEXIT_CRITICAL(); 8015fb0: f001 febc bl 8017d2c if( xSchedulerRunning != pdFALSE ) 8015fb4: 4b0d ldr r3, [pc, #52] @ (8015fec ) 8015fb6: 681b ldr r3, [r3, #0] 8015fb8: 2b00 cmp r3, #0 8015fba: d00e beq.n 8015fda { /* If the created task is of a higher priority than the current task then it should run now. */ if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) 8015fbc: 4b0a ldr r3, [pc, #40] @ (8015fe8 ) 8015fbe: 681b ldr r3, [r3, #0] 8015fc0: 6ada ldr r2, [r3, #44] @ 0x2c 8015fc2: 687b ldr r3, [r7, #4] 8015fc4: 6adb ldr r3, [r3, #44] @ 0x2c 8015fc6: 429a cmp r2, r3 8015fc8: d207 bcs.n 8015fda { taskYIELD_IF_USING_PREEMPTION(); 8015fca: 4b0c ldr r3, [pc, #48] @ (8015ffc ) 8015fcc: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015fd0: 601a str r2, [r3, #0] 8015fd2: f3bf 8f4f dsb sy 8015fd6: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 8015fda: bf00 nop 8015fdc: 3708 adds r7, #8 8015fde: 46bd mov sp, r7 8015fe0: bd80 pop {r7, pc} 8015fe2: bf00 nop 8015fe4: 24002ecc .word 0x24002ecc 8015fe8: 240029f8 .word 0x240029f8 8015fec: 24002ed8 .word 0x24002ed8 8015ff0: 24002ee8 .word 0x24002ee8 8015ff4: 24002ed4 .word 0x24002ed4 8015ff8: 240029fc .word 0x240029fc 8015ffc: e000ed04 .word 0xe000ed04 08016000 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelay == 1 ) void vTaskDelay( const TickType_t xTicksToDelay ) { 8016000: b580 push {r7, lr} 8016002: b084 sub sp, #16 8016004: af00 add r7, sp, #0 8016006: 6078 str r0, [r7, #4] BaseType_t xAlreadyYielded = pdFALSE; 8016008: 2300 movs r3, #0 801600a: 60fb str r3, [r7, #12] /* A delay time of zero just forces a reschedule. */ if( xTicksToDelay > ( TickType_t ) 0U ) 801600c: 687b ldr r3, [r7, #4] 801600e: 2b00 cmp r3, #0 8016010: d018 beq.n 8016044 { configASSERT( uxSchedulerSuspended == 0 ); 8016012: 4b14 ldr r3, [pc, #80] @ (8016064 ) 8016014: 681b ldr r3, [r3, #0] 8016016: 2b00 cmp r3, #0 8016018: d00b beq.n 8016032 __asm volatile 801601a: f04f 0350 mov.w r3, #80 @ 0x50 801601e: f383 8811 msr BASEPRI, r3 8016022: f3bf 8f6f isb sy 8016026: f3bf 8f4f dsb sy 801602a: 60bb str r3, [r7, #8] } 801602c: bf00 nop 801602e: bf00 nop 8016030: e7fd b.n 801602e vTaskSuspendAll(); 8016032: f000 f88b bl 801614c list or removed from the blocked list until the scheduler is resumed. This task cannot be in an event list as it is the currently executing task. */ prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); 8016036: 2100 movs r1, #0 8016038: 6878 ldr r0, [r7, #4] 801603a: f001 f87d bl 8017138 } xAlreadyYielded = xTaskResumeAll(); 801603e: f000 f893 bl 8016168 8016042: 60f8 str r0, [r7, #12] mtCOVERAGE_TEST_MARKER(); } /* Force a reschedule if xTaskResumeAll has not already done so, we may have put ourselves to sleep. */ if( xAlreadyYielded == pdFALSE ) 8016044: 68fb ldr r3, [r7, #12] 8016046: 2b00 cmp r3, #0 8016048: d107 bne.n 801605a { portYIELD_WITHIN_API(); 801604a: 4b07 ldr r3, [pc, #28] @ (8016068 ) 801604c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016050: 601a str r2, [r3, #0] 8016052: f3bf 8f4f dsb sy 8016056: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 801605a: bf00 nop 801605c: 3710 adds r7, #16 801605e: 46bd mov sp, r7 8016060: bd80 pop {r7, pc} 8016062: bf00 nop 8016064: 24002ef4 .word 0x24002ef4 8016068: e000ed04 .word 0xe000ed04 0801606c : #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ /*-----------------------------------------------------------*/ void vTaskStartScheduler( void ) { 801606c: b580 push {r7, lr} 801606e: b08a sub sp, #40 @ 0x28 8016070: af04 add r7, sp, #16 BaseType_t xReturn; /* Add the idle task at the lowest priority. */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxIdleTaskTCBBuffer = NULL; 8016072: 2300 movs r3, #0 8016074: 60bb str r3, [r7, #8] StackType_t *pxIdleTaskStackBuffer = NULL; 8016076: 2300 movs r3, #0 8016078: 607b str r3, [r7, #4] uint32_t ulIdleTaskStackSize; /* The Idle task is created using user provided RAM - obtain the address of the RAM then create the idle task. */ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); 801607a: 463a mov r2, r7 801607c: 1d39 adds r1, r7, #4 801607e: f107 0308 add.w r3, r7, #8 8016082: 4618 mov r0, r3 8016084: f7fe fbc0 bl 8014808 xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, 8016088: 6839 ldr r1, [r7, #0] 801608a: 687b ldr r3, [r7, #4] 801608c: 68ba ldr r2, [r7, #8] 801608e: 9202 str r2, [sp, #8] 8016090: 9301 str r3, [sp, #4] 8016092: 2300 movs r3, #0 8016094: 9300 str r3, [sp, #0] 8016096: 2300 movs r3, #0 8016098: 460a mov r2, r1 801609a: 4924 ldr r1, [pc, #144] @ (801612c ) 801609c: 4824 ldr r0, [pc, #144] @ (8016130 ) 801609e: f7ff fdf2 bl 8015c86 80160a2: 4603 mov r3, r0 80160a4: 4a23 ldr r2, [pc, #140] @ (8016134 ) 80160a6: 6013 str r3, [r2, #0] ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ pxIdleTaskStackBuffer, pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ if( xIdleTaskHandle != NULL ) 80160a8: 4b22 ldr r3, [pc, #136] @ (8016134 ) 80160aa: 681b ldr r3, [r3, #0] 80160ac: 2b00 cmp r3, #0 80160ae: d002 beq.n 80160b6 { xReturn = pdPASS; 80160b0: 2301 movs r3, #1 80160b2: 617b str r3, [r7, #20] 80160b4: e001 b.n 80160ba } else { xReturn = pdFAIL; 80160b6: 2300 movs r3, #0 80160b8: 617b str r3, [r7, #20] } #endif /* configSUPPORT_STATIC_ALLOCATION */ #if ( configUSE_TIMERS == 1 ) { if( xReturn == pdPASS ) 80160ba: 697b ldr r3, [r7, #20] 80160bc: 2b01 cmp r3, #1 80160be: d102 bne.n 80160c6 { xReturn = xTimerCreateTimerTask(); 80160c0: f001 f88e bl 80171e0 80160c4: 6178 str r0, [r7, #20] mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_TIMERS */ if( xReturn == pdPASS ) 80160c6: 697b ldr r3, [r7, #20] 80160c8: 2b01 cmp r3, #1 80160ca: d11b bne.n 8016104 __asm volatile 80160cc: f04f 0350 mov.w r3, #80 @ 0x50 80160d0: f383 8811 msr BASEPRI, r3 80160d4: f3bf 8f6f isb sy 80160d8: f3bf 8f4f dsb sy 80160dc: 613b str r3, [r7, #16] } 80160de: bf00 nop { /* Switch Newlib's _impure_ptr variable to point to the _reent structure specific to the task that will run first. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 80160e0: 4b15 ldr r3, [pc, #84] @ (8016138 ) 80160e2: 681b ldr r3, [r3, #0] 80160e4: 3354 adds r3, #84 @ 0x54 80160e6: 4a15 ldr r2, [pc, #84] @ (801613c ) 80160e8: 6013 str r3, [r2, #0] } #endif /* configUSE_NEWLIB_REENTRANT */ xNextTaskUnblockTime = portMAX_DELAY; 80160ea: 4b15 ldr r3, [pc, #84] @ (8016140 ) 80160ec: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80160f0: 601a str r2, [r3, #0] xSchedulerRunning = pdTRUE; 80160f2: 4b14 ldr r3, [pc, #80] @ (8016144 ) 80160f4: 2201 movs r2, #1 80160f6: 601a str r2, [r3, #0] xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; 80160f8: 4b13 ldr r3, [pc, #76] @ (8016148 ) 80160fa: 2200 movs r2, #0 80160fc: 601a str r2, [r3, #0] traceTASK_SWITCHED_IN(); /* Setting up the timer tick is hardware specific and thus in the portable interface. */ if( xPortStartScheduler() != pdFALSE ) 80160fe: f001 fd3f bl 8017b80 } /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, meaning xIdleTaskHandle is not used anywhere else. */ ( void ) xIdleTaskHandle; } 8016102: e00f b.n 8016124 configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); 8016104: 697b ldr r3, [r7, #20] 8016106: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801610a: d10b bne.n 8016124 __asm volatile 801610c: f04f 0350 mov.w r3, #80 @ 0x50 8016110: f383 8811 msr BASEPRI, r3 8016114: f3bf 8f6f isb sy 8016118: f3bf 8f4f dsb sy 801611c: 60fb str r3, [r7, #12] } 801611e: bf00 nop 8016120: bf00 nop 8016122: e7fd b.n 8016120 } 8016124: bf00 nop 8016126: 3718 adds r7, #24 8016128: 46bd mov sp, r7 801612a: bd80 pop {r7, pc} 801612c: 08018660 .word 0x08018660 8016130: 080167e9 .word 0x080167e9 8016134: 24002ef0 .word 0x24002ef0 8016138: 240029f8 .word 0x240029f8 801613c: 24000048 .word 0x24000048 8016140: 24002eec .word 0x24002eec 8016144: 24002ed8 .word 0x24002ed8 8016148: 24002ed0 .word 0x24002ed0 0801614c : vPortEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { 801614c: b480 push {r7} 801614e: af00 add r7, sp, #0 do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER(); /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; 8016150: 4b04 ldr r3, [pc, #16] @ (8016164 ) 8016152: 681b ldr r3, [r3, #0] 8016154: 3301 adds r3, #1 8016156: 4a03 ldr r2, [pc, #12] @ (8016164 ) 8016158: 6013 str r3, [r2, #0] /* Enforces ordering for ports and optimised compilers that may otherwise place the above increment elsewhere. */ portMEMORY_BARRIER(); } 801615a: bf00 nop 801615c: 46bd mov sp, r7 801615e: f85d 7b04 ldr.w r7, [sp], #4 8016162: 4770 bx lr 8016164: 24002ef4 .word 0x24002ef4 08016168 : #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ BaseType_t xTaskResumeAll( void ) { 8016168: b580 push {r7, lr} 801616a: b084 sub sp, #16 801616c: af00 add r7, sp, #0 TCB_t *pxTCB = NULL; 801616e: 2300 movs r3, #0 8016170: 60fb str r3, [r7, #12] BaseType_t xAlreadyYielded = pdFALSE; 8016172: 2300 movs r3, #0 8016174: 60bb str r3, [r7, #8] /* If uxSchedulerSuspended is zero then this function does not match a previous call to vTaskSuspendAll(). */ configASSERT( uxSchedulerSuspended ); 8016176: 4b42 ldr r3, [pc, #264] @ (8016280 ) 8016178: 681b ldr r3, [r3, #0] 801617a: 2b00 cmp r3, #0 801617c: d10b bne.n 8016196 __asm volatile 801617e: f04f 0350 mov.w r3, #80 @ 0x50 8016182: f383 8811 msr BASEPRI, r3 8016186: f3bf 8f6f isb sy 801618a: f3bf 8f4f dsb sy 801618e: 603b str r3, [r7, #0] } 8016190: bf00 nop 8016192: bf00 nop 8016194: e7fd b.n 8016192 /* It is possible that an ISR caused a task to be removed from an event list while the scheduler was suspended. If this was the case then the removed task will have been added to the xPendingReadyList. Once the scheduler has been resumed it is safe to move all the pending ready tasks from this list into their appropriate ready list. */ taskENTER_CRITICAL(); 8016196: f001 fd97 bl 8017cc8 { --uxSchedulerSuspended; 801619a: 4b39 ldr r3, [pc, #228] @ (8016280 ) 801619c: 681b ldr r3, [r3, #0] 801619e: 3b01 subs r3, #1 80161a0: 4a37 ldr r2, [pc, #220] @ (8016280 ) 80161a2: 6013 str r3, [r2, #0] if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80161a4: 4b36 ldr r3, [pc, #216] @ (8016280 ) 80161a6: 681b ldr r3, [r3, #0] 80161a8: 2b00 cmp r3, #0 80161aa: d162 bne.n 8016272 { if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) 80161ac: 4b35 ldr r3, [pc, #212] @ (8016284 ) 80161ae: 681b ldr r3, [r3, #0] 80161b0: 2b00 cmp r3, #0 80161b2: d05e beq.n 8016272 { /* Move any readied tasks from the pending list into the appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 80161b4: e02f b.n 8016216 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80161b6: 4b34 ldr r3, [pc, #208] @ (8016288 ) 80161b8: 68db ldr r3, [r3, #12] 80161ba: 68db ldr r3, [r3, #12] 80161bc: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 80161be: 68fb ldr r3, [r7, #12] 80161c0: 3318 adds r3, #24 80161c2: 4618 mov r0, r3 80161c4: f7fe fbde bl 8014984 ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80161c8: 68fb ldr r3, [r7, #12] 80161ca: 3304 adds r3, #4 80161cc: 4618 mov r0, r3 80161ce: f7fe fbd9 bl 8014984 prvAddTaskToReadyList( pxTCB ); 80161d2: 68fb ldr r3, [r7, #12] 80161d4: 6ada ldr r2, [r3, #44] @ 0x2c 80161d6: 4b2d ldr r3, [pc, #180] @ (801628c ) 80161d8: 681b ldr r3, [r3, #0] 80161da: 429a cmp r2, r3 80161dc: d903 bls.n 80161e6 80161de: 68fb ldr r3, [r7, #12] 80161e0: 6adb ldr r3, [r3, #44] @ 0x2c 80161e2: 4a2a ldr r2, [pc, #168] @ (801628c ) 80161e4: 6013 str r3, [r2, #0] 80161e6: 68fb ldr r3, [r7, #12] 80161e8: 6ada ldr r2, [r3, #44] @ 0x2c 80161ea: 4613 mov r3, r2 80161ec: 009b lsls r3, r3, #2 80161ee: 4413 add r3, r2 80161f0: 009b lsls r3, r3, #2 80161f2: 4a27 ldr r2, [pc, #156] @ (8016290 ) 80161f4: 441a add r2, r3 80161f6: 68fb ldr r3, [r7, #12] 80161f8: 3304 adds r3, #4 80161fa: 4619 mov r1, r3 80161fc: 4610 mov r0, r2 80161fe: f7fe fb64 bl 80148ca /* If the moved task has a priority higher than the current task then a yield must be performed. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 8016202: 68fb ldr r3, [r7, #12] 8016204: 6ada ldr r2, [r3, #44] @ 0x2c 8016206: 4b23 ldr r3, [pc, #140] @ (8016294 ) 8016208: 681b ldr r3, [r3, #0] 801620a: 6adb ldr r3, [r3, #44] @ 0x2c 801620c: 429a cmp r2, r3 801620e: d302 bcc.n 8016216 { xYieldPending = pdTRUE; 8016210: 4b21 ldr r3, [pc, #132] @ (8016298 ) 8016212: 2201 movs r2, #1 8016214: 601a str r2, [r3, #0] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 8016216: 4b1c ldr r3, [pc, #112] @ (8016288 ) 8016218: 681b ldr r3, [r3, #0] 801621a: 2b00 cmp r3, #0 801621c: d1cb bne.n 80161b6 { mtCOVERAGE_TEST_MARKER(); } } if( pxTCB != NULL ) 801621e: 68fb ldr r3, [r7, #12] 8016220: 2b00 cmp r3, #0 8016222: d001 beq.n 8016228 which may have prevented the next unblock time from being re-calculated, in which case re-calculate it now. Mainly important for low power tickless implementations, where this can prevent an unnecessary exit from low power state. */ prvResetNextTaskUnblockTime(); 8016224: f000 fb9c bl 8016960 /* If any ticks occurred while the scheduler was suspended then they should be processed now. This ensures the tick count does not slip, and that any delayed tasks are resumed at the correct time. */ { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ 8016228: 4b1c ldr r3, [pc, #112] @ (801629c ) 801622a: 681b ldr r3, [r3, #0] 801622c: 607b str r3, [r7, #4] if( xPendedCounts > ( TickType_t ) 0U ) 801622e: 687b ldr r3, [r7, #4] 8016230: 2b00 cmp r3, #0 8016232: d010 beq.n 8016256 { do { if( xTaskIncrementTick() != pdFALSE ) 8016234: f000 f846 bl 80162c4 8016238: 4603 mov r3, r0 801623a: 2b00 cmp r3, #0 801623c: d002 beq.n 8016244 { xYieldPending = pdTRUE; 801623e: 4b16 ldr r3, [pc, #88] @ (8016298 ) 8016240: 2201 movs r2, #1 8016242: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } --xPendedCounts; 8016244: 687b ldr r3, [r7, #4] 8016246: 3b01 subs r3, #1 8016248: 607b str r3, [r7, #4] } while( xPendedCounts > ( TickType_t ) 0U ); 801624a: 687b ldr r3, [r7, #4] 801624c: 2b00 cmp r3, #0 801624e: d1f1 bne.n 8016234 xPendedTicks = 0; 8016250: 4b12 ldr r3, [pc, #72] @ (801629c ) 8016252: 2200 movs r2, #0 8016254: 601a str r2, [r3, #0] { mtCOVERAGE_TEST_MARKER(); } } if( xYieldPending != pdFALSE ) 8016256: 4b10 ldr r3, [pc, #64] @ (8016298 ) 8016258: 681b ldr r3, [r3, #0] 801625a: 2b00 cmp r3, #0 801625c: d009 beq.n 8016272 { #if( configUSE_PREEMPTION != 0 ) { xAlreadyYielded = pdTRUE; 801625e: 2301 movs r3, #1 8016260: 60bb str r3, [r7, #8] } #endif taskYIELD_IF_USING_PREEMPTION(); 8016262: 4b0f ldr r3, [pc, #60] @ (80162a0 ) 8016264: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016268: 601a str r2, [r3, #0] 801626a: f3bf 8f4f dsb sy 801626e: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016272: f001 fd5b bl 8017d2c return xAlreadyYielded; 8016276: 68bb ldr r3, [r7, #8] } 8016278: 4618 mov r0, r3 801627a: 3710 adds r7, #16 801627c: 46bd mov sp, r7 801627e: bd80 pop {r7, pc} 8016280: 24002ef4 .word 0x24002ef4 8016284: 24002ecc .word 0x24002ecc 8016288: 24002e8c .word 0x24002e8c 801628c: 24002ed4 .word 0x24002ed4 8016290: 240029fc .word 0x240029fc 8016294: 240029f8 .word 0x240029f8 8016298: 24002ee0 .word 0x24002ee0 801629c: 24002edc .word 0x24002edc 80162a0: e000ed04 .word 0xe000ed04 080162a4 : /*-----------------------------------------------------------*/ TickType_t xTaskGetTickCount( void ) { 80162a4: b480 push {r7} 80162a6: b083 sub sp, #12 80162a8: af00 add r7, sp, #0 TickType_t xTicks; /* Critical section required if running on a 16 bit processor. */ portTICK_TYPE_ENTER_CRITICAL(); { xTicks = xTickCount; 80162aa: 4b05 ldr r3, [pc, #20] @ (80162c0 ) 80162ac: 681b ldr r3, [r3, #0] 80162ae: 607b str r3, [r7, #4] } portTICK_TYPE_EXIT_CRITICAL(); return xTicks; 80162b0: 687b ldr r3, [r7, #4] } 80162b2: 4618 mov r0, r3 80162b4: 370c adds r7, #12 80162b6: 46bd mov sp, r7 80162b8: f85d 7b04 ldr.w r7, [sp], #4 80162bc: 4770 bx lr 80162be: bf00 nop 80162c0: 24002ed0 .word 0x24002ed0 080162c4 : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { 80162c4: b580 push {r7, lr} 80162c6: b086 sub sp, #24 80162c8: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; 80162ca: 2300 movs r3, #0 80162cc: 617b str r3, [r7, #20] /* Called by the portable layer each time a tick interrupt occurs. Increments the tick then checks to see if the new tick value will cause any tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80162ce: 4b4f ldr r3, [pc, #316] @ (801640c ) 80162d0: 681b ldr r3, [r3, #0] 80162d2: 2b00 cmp r3, #0 80162d4: f040 8090 bne.w 80163f8 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 80162d8: 4b4d ldr r3, [pc, #308] @ (8016410 ) 80162da: 681b ldr r3, [r3, #0] 80162dc: 3301 adds r3, #1 80162de: 613b str r3, [r7, #16] /* Increment the RTOS tick, switching the delayed and overflowed delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; 80162e0: 4a4b ldr r2, [pc, #300] @ (8016410 ) 80162e2: 693b ldr r3, [r7, #16] 80162e4: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ 80162e6: 693b ldr r3, [r7, #16] 80162e8: 2b00 cmp r3, #0 80162ea: d121 bne.n 8016330 { taskSWITCH_DELAYED_LISTS(); 80162ec: 4b49 ldr r3, [pc, #292] @ (8016414 ) 80162ee: 681b ldr r3, [r3, #0] 80162f0: 681b ldr r3, [r3, #0] 80162f2: 2b00 cmp r3, #0 80162f4: d00b beq.n 801630e __asm volatile 80162f6: f04f 0350 mov.w r3, #80 @ 0x50 80162fa: f383 8811 msr BASEPRI, r3 80162fe: f3bf 8f6f isb sy 8016302: f3bf 8f4f dsb sy 8016306: 603b str r3, [r7, #0] } 8016308: bf00 nop 801630a: bf00 nop 801630c: e7fd b.n 801630a 801630e: 4b41 ldr r3, [pc, #260] @ (8016414 ) 8016310: 681b ldr r3, [r3, #0] 8016312: 60fb str r3, [r7, #12] 8016314: 4b40 ldr r3, [pc, #256] @ (8016418 ) 8016316: 681b ldr r3, [r3, #0] 8016318: 4a3e ldr r2, [pc, #248] @ (8016414 ) 801631a: 6013 str r3, [r2, #0] 801631c: 4a3e ldr r2, [pc, #248] @ (8016418 ) 801631e: 68fb ldr r3, [r7, #12] 8016320: 6013 str r3, [r2, #0] 8016322: 4b3e ldr r3, [pc, #248] @ (801641c ) 8016324: 681b ldr r3, [r3, #0] 8016326: 3301 adds r3, #1 8016328: 4a3c ldr r2, [pc, #240] @ (801641c ) 801632a: 6013 str r3, [r2, #0] 801632c: f000 fb18 bl 8016960 /* See if this tick has made a timeout expire. Tasks are stored in the queue in the order of their wake time - meaning once one task has been found whose block time has not expired there is no need to look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) 8016330: 4b3b ldr r3, [pc, #236] @ (8016420 ) 8016332: 681b ldr r3, [r3, #0] 8016334: 693a ldr r2, [r7, #16] 8016336: 429a cmp r2, r3 8016338: d349 bcc.n 80163ce { for( ;; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 801633a: 4b36 ldr r3, [pc, #216] @ (8016414 ) 801633c: 681b ldr r3, [r3, #0] 801633e: 681b ldr r3, [r3, #0] 8016340: 2b00 cmp r3, #0 8016342: d104 bne.n 801634e /* The delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016344: 4b36 ldr r3, [pc, #216] @ (8016420 ) 8016346: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801634a: 601a str r2, [r3, #0] break; 801634c: e03f b.n 80163ce { /* The delayed list is not empty, get the value of the item at the head of the delayed list. This is the time at which the task at the head of the delayed list must be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 801634e: 4b31 ldr r3, [pc, #196] @ (8016414 ) 8016350: 681b ldr r3, [r3, #0] 8016352: 68db ldr r3, [r3, #12] 8016354: 68db ldr r3, [r3, #12] 8016356: 60bb str r3, [r7, #8] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); 8016358: 68bb ldr r3, [r7, #8] 801635a: 685b ldr r3, [r3, #4] 801635c: 607b str r3, [r7, #4] if( xConstTickCount < xItemValue ) 801635e: 693a ldr r2, [r7, #16] 8016360: 687b ldr r3, [r7, #4] 8016362: 429a cmp r2, r3 8016364: d203 bcs.n 801636e /* It is not time to unblock this item yet, but the item value is the time at which the task at the head of the blocked list must be removed from the Blocked state - so record the item value in xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; 8016366: 4a2e ldr r2, [pc, #184] @ (8016420 ) 8016368: 687b ldr r3, [r7, #4] 801636a: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ 801636c: e02f b.n 80163ce { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 801636e: 68bb ldr r3, [r7, #8] 8016370: 3304 adds r3, #4 8016372: 4618 mov r0, r3 8016374: f7fe fb06 bl 8014984 /* Is the task waiting on an event also? If so remove it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 8016378: 68bb ldr r3, [r7, #8] 801637a: 6a9b ldr r3, [r3, #40] @ 0x28 801637c: 2b00 cmp r3, #0 801637e: d004 beq.n 801638a { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 8016380: 68bb ldr r3, [r7, #8] 8016382: 3318 adds r3, #24 8016384: 4618 mov r0, r3 8016386: f7fe fafd bl 8014984 mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready list. */ prvAddTaskToReadyList( pxTCB ); 801638a: 68bb ldr r3, [r7, #8] 801638c: 6ada ldr r2, [r3, #44] @ 0x2c 801638e: 4b25 ldr r3, [pc, #148] @ (8016424 ) 8016390: 681b ldr r3, [r3, #0] 8016392: 429a cmp r2, r3 8016394: d903 bls.n 801639e 8016396: 68bb ldr r3, [r7, #8] 8016398: 6adb ldr r3, [r3, #44] @ 0x2c 801639a: 4a22 ldr r2, [pc, #136] @ (8016424 ) 801639c: 6013 str r3, [r2, #0] 801639e: 68bb ldr r3, [r7, #8] 80163a0: 6ada ldr r2, [r3, #44] @ 0x2c 80163a2: 4613 mov r3, r2 80163a4: 009b lsls r3, r3, #2 80163a6: 4413 add r3, r2 80163a8: 009b lsls r3, r3, #2 80163aa: 4a1f ldr r2, [pc, #124] @ (8016428 ) 80163ac: 441a add r2, r3 80163ae: 68bb ldr r3, [r7, #8] 80163b0: 3304 adds r3, #4 80163b2: 4619 mov r1, r3 80163b4: 4610 mov r0, r2 80163b6: f7fe fa88 bl 80148ca { /* Preemption is on, but a context switch should only be performed if the unblocked task has a priority that is equal to or higher than the currently executing task. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 80163ba: 68bb ldr r3, [r7, #8] 80163bc: 6ada ldr r2, [r3, #44] @ 0x2c 80163be: 4b1b ldr r3, [pc, #108] @ (801642c ) 80163c0: 681b ldr r3, [r3, #0] 80163c2: 6adb ldr r3, [r3, #44] @ 0x2c 80163c4: 429a cmp r2, r3 80163c6: d3b8 bcc.n 801633a { xSwitchRequired = pdTRUE; 80163c8: 2301 movs r3, #1 80163ca: 617b str r3, [r7, #20] if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 80163cc: e7b5 b.n 801633a /* Tasks of equal priority to the currently running task will share processing time (time slice) if preemption is on, and the application writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 80163ce: 4b17 ldr r3, [pc, #92] @ (801642c ) 80163d0: 681b ldr r3, [r3, #0] 80163d2: 6ada ldr r2, [r3, #44] @ 0x2c 80163d4: 4914 ldr r1, [pc, #80] @ (8016428 ) 80163d6: 4613 mov r3, r2 80163d8: 009b lsls r3, r3, #2 80163da: 4413 add r3, r2 80163dc: 009b lsls r3, r3, #2 80163de: 440b add r3, r1 80163e0: 681b ldr r3, [r3, #0] 80163e2: 2b01 cmp r3, #1 80163e4: d901 bls.n 80163ea { xSwitchRequired = pdTRUE; 80163e6: 2301 movs r3, #1 80163e8: 617b str r3, [r7, #20] } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) 80163ea: 4b11 ldr r3, [pc, #68] @ (8016430 ) 80163ec: 681b ldr r3, [r3, #0] 80163ee: 2b00 cmp r3, #0 80163f0: d007 beq.n 8016402 { xSwitchRequired = pdTRUE; 80163f2: 2301 movs r3, #1 80163f4: 617b str r3, [r7, #20] 80163f6: e004 b.n 8016402 } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; 80163f8: 4b0e ldr r3, [pc, #56] @ (8016434 ) 80163fa: 681b ldr r3, [r3, #0] 80163fc: 3301 adds r3, #1 80163fe: 4a0d ldr r2, [pc, #52] @ (8016434 ) 8016400: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; 8016402: 697b ldr r3, [r7, #20] } 8016404: 4618 mov r0, r3 8016406: 3718 adds r7, #24 8016408: 46bd mov sp, r7 801640a: bd80 pop {r7, pc} 801640c: 24002ef4 .word 0x24002ef4 8016410: 24002ed0 .word 0x24002ed0 8016414: 24002e84 .word 0x24002e84 8016418: 24002e88 .word 0x24002e88 801641c: 24002ee4 .word 0x24002ee4 8016420: 24002eec .word 0x24002eec 8016424: 24002ed4 .word 0x24002ed4 8016428: 240029fc .word 0x240029fc 801642c: 240029f8 .word 0x240029f8 8016430: 24002ee0 .word 0x24002ee0 8016434: 24002edc .word 0x24002edc 08016438 : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { 8016438: b580 push {r7, lr} 801643a: b084 sub sp, #16 801643c: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) 801643e: 4b32 ldr r3, [pc, #200] @ (8016508 ) 8016440: 681b ldr r3, [r3, #0] 8016442: 2b00 cmp r3, #0 8016444: d003 beq.n 801644e { /* The scheduler is currently suspended - do not allow a context switch. */ xYieldPending = pdTRUE; 8016446: 4b31 ldr r3, [pc, #196] @ (801650c ) 8016448: 2201 movs r2, #1 801644a: 601a str r2, [r3, #0] for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ } } 801644c: e058 b.n 8016500 xYieldPending = pdFALSE; 801644e: 4b2f ldr r3, [pc, #188] @ (801650c ) 8016450: 2200 movs r2, #0 8016452: 601a str r2, [r3, #0] taskCHECK_FOR_STACK_OVERFLOW(); 8016454: 4b2e ldr r3, [pc, #184] @ (8016510 ) 8016456: 681b ldr r3, [r3, #0] 8016458: 681a ldr r2, [r3, #0] 801645a: 4b2d ldr r3, [pc, #180] @ (8016510 ) 801645c: 681b ldr r3, [r3, #0] 801645e: 6b1b ldr r3, [r3, #48] @ 0x30 8016460: 429a cmp r2, r3 8016462: d808 bhi.n 8016476 8016464: 4b2a ldr r3, [pc, #168] @ (8016510 ) 8016466: 681a ldr r2, [r3, #0] 8016468: 4b29 ldr r3, [pc, #164] @ (8016510 ) 801646a: 681b ldr r3, [r3, #0] 801646c: 3334 adds r3, #52 @ 0x34 801646e: 4619 mov r1, r3 8016470: 4610 mov r0, r2 8016472: f7ea f8ad bl 80005d0 taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8016476: 4b27 ldr r3, [pc, #156] @ (8016514 ) 8016478: 681b ldr r3, [r3, #0] 801647a: 60fb str r3, [r7, #12] 801647c: e011 b.n 80164a2 801647e: 68fb ldr r3, [r7, #12] 8016480: 2b00 cmp r3, #0 8016482: d10b bne.n 801649c __asm volatile 8016484: f04f 0350 mov.w r3, #80 @ 0x50 8016488: f383 8811 msr BASEPRI, r3 801648c: f3bf 8f6f isb sy 8016490: f3bf 8f4f dsb sy 8016494: 607b str r3, [r7, #4] } 8016496: bf00 nop 8016498: bf00 nop 801649a: e7fd b.n 8016498 801649c: 68fb ldr r3, [r7, #12] 801649e: 3b01 subs r3, #1 80164a0: 60fb str r3, [r7, #12] 80164a2: 491d ldr r1, [pc, #116] @ (8016518 ) 80164a4: 68fa ldr r2, [r7, #12] 80164a6: 4613 mov r3, r2 80164a8: 009b lsls r3, r3, #2 80164aa: 4413 add r3, r2 80164ac: 009b lsls r3, r3, #2 80164ae: 440b add r3, r1 80164b0: 681b ldr r3, [r3, #0] 80164b2: 2b00 cmp r3, #0 80164b4: d0e3 beq.n 801647e 80164b6: 68fa ldr r2, [r7, #12] 80164b8: 4613 mov r3, r2 80164ba: 009b lsls r3, r3, #2 80164bc: 4413 add r3, r2 80164be: 009b lsls r3, r3, #2 80164c0: 4a15 ldr r2, [pc, #84] @ (8016518 ) 80164c2: 4413 add r3, r2 80164c4: 60bb str r3, [r7, #8] 80164c6: 68bb ldr r3, [r7, #8] 80164c8: 685b ldr r3, [r3, #4] 80164ca: 685a ldr r2, [r3, #4] 80164cc: 68bb ldr r3, [r7, #8] 80164ce: 605a str r2, [r3, #4] 80164d0: 68bb ldr r3, [r7, #8] 80164d2: 685a ldr r2, [r3, #4] 80164d4: 68bb ldr r3, [r7, #8] 80164d6: 3308 adds r3, #8 80164d8: 429a cmp r2, r3 80164da: d104 bne.n 80164e6 80164dc: 68bb ldr r3, [r7, #8] 80164de: 685b ldr r3, [r3, #4] 80164e0: 685a ldr r2, [r3, #4] 80164e2: 68bb ldr r3, [r7, #8] 80164e4: 605a str r2, [r3, #4] 80164e6: 68bb ldr r3, [r7, #8] 80164e8: 685b ldr r3, [r3, #4] 80164ea: 68db ldr r3, [r3, #12] 80164ec: 4a08 ldr r2, [pc, #32] @ (8016510 ) 80164ee: 6013 str r3, [r2, #0] 80164f0: 4a08 ldr r2, [pc, #32] @ (8016514 ) 80164f2: 68fb ldr r3, [r7, #12] 80164f4: 6013 str r3, [r2, #0] _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 80164f6: 4b06 ldr r3, [pc, #24] @ (8016510 ) 80164f8: 681b ldr r3, [r3, #0] 80164fa: 3354 adds r3, #84 @ 0x54 80164fc: 4a07 ldr r2, [pc, #28] @ (801651c ) 80164fe: 6013 str r3, [r2, #0] } 8016500: bf00 nop 8016502: 3710 adds r7, #16 8016504: 46bd mov sp, r7 8016506: bd80 pop {r7, pc} 8016508: 24002ef4 .word 0x24002ef4 801650c: 24002ee0 .word 0x24002ee0 8016510: 240029f8 .word 0x240029f8 8016514: 24002ed4 .word 0x24002ed4 8016518: 240029fc .word 0x240029fc 801651c: 24000048 .word 0x24000048 08016520 : /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { 8016520: b580 push {r7, lr} 8016522: b084 sub sp, #16 8016524: af00 add r7, sp, #0 8016526: 6078 str r0, [r7, #4] 8016528: 6039 str r1, [r7, #0] configASSERT( pxEventList ); 801652a: 687b ldr r3, [r7, #4] 801652c: 2b00 cmp r3, #0 801652e: d10b bne.n 8016548 __asm volatile 8016530: f04f 0350 mov.w r3, #80 @ 0x50 8016534: f383 8811 msr BASEPRI, r3 8016538: f3bf 8f6f isb sy 801653c: f3bf 8f4f dsb sy 8016540: 60fb str r3, [r7, #12] } 8016542: bf00 nop 8016544: bf00 nop 8016546: e7fd b.n 8016544 /* Place the event list item of the TCB in the appropriate event list. This is placed in the list in priority order so the highest priority task is the first to be woken by the event. The queue that contains the event list is locked, preventing simultaneous access from interrupts. */ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 8016548: 4b07 ldr r3, [pc, #28] @ (8016568 ) 801654a: 681b ldr r3, [r3, #0] 801654c: 3318 adds r3, #24 801654e: 4619 mov r1, r3 8016550: 6878 ldr r0, [r7, #4] 8016552: f7fe f9de bl 8014912 prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 8016556: 2101 movs r1, #1 8016558: 6838 ldr r0, [r7, #0] 801655a: f000 fded bl 8017138 } 801655e: bf00 nop 8016560: 3710 adds r7, #16 8016562: 46bd mov sp, r7 8016564: bd80 pop {r7, pc} 8016566: bf00 nop 8016568: 240029f8 .word 0x240029f8 0801656c : /*-----------------------------------------------------------*/ #if( configUSE_TIMERS == 1 ) void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 801656c: b580 push {r7, lr} 801656e: b086 sub sp, #24 8016570: af00 add r7, sp, #0 8016572: 60f8 str r0, [r7, #12] 8016574: 60b9 str r1, [r7, #8] 8016576: 607a str r2, [r7, #4] configASSERT( pxEventList ); 8016578: 68fb ldr r3, [r7, #12] 801657a: 2b00 cmp r3, #0 801657c: d10b bne.n 8016596 __asm volatile 801657e: f04f 0350 mov.w r3, #80 @ 0x50 8016582: f383 8811 msr BASEPRI, r3 8016586: f3bf 8f6f isb sy 801658a: f3bf 8f4f dsb sy 801658e: 617b str r3, [r7, #20] } 8016590: bf00 nop 8016592: bf00 nop 8016594: e7fd b.n 8016592 /* Place the event list item of the TCB in the appropriate event list. In this case it is assume that this is the only task that is going to be waiting on this event list, so the faster vListInsertEnd() function can be used in place of vListInsert. */ vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 8016596: 4b0a ldr r3, [pc, #40] @ (80165c0 ) 8016598: 681b ldr r3, [r3, #0] 801659a: 3318 adds r3, #24 801659c: 4619 mov r1, r3 801659e: 68f8 ldr r0, [r7, #12] 80165a0: f7fe f993 bl 80148ca /* If the task should block indefinitely then set the block time to a value that will be recognised as an indefinite delay inside the prvAddCurrentTaskToDelayedList() function. */ if( xWaitIndefinitely != pdFALSE ) 80165a4: 687b ldr r3, [r7, #4] 80165a6: 2b00 cmp r3, #0 80165a8: d002 beq.n 80165b0 { xTicksToWait = portMAX_DELAY; 80165aa: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80165ae: 60bb str r3, [r7, #8] } traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); 80165b0: 6879 ldr r1, [r7, #4] 80165b2: 68b8 ldr r0, [r7, #8] 80165b4: f000 fdc0 bl 8017138 } 80165b8: bf00 nop 80165ba: 3718 adds r7, #24 80165bc: 46bd mov sp, r7 80165be: bd80 pop {r7, pc} 80165c0: 240029f8 .word 0x240029f8 080165c4 : #endif /* configUSE_TIMERS */ /*-----------------------------------------------------------*/ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { 80165c4: b580 push {r7, lr} 80165c6: b086 sub sp, #24 80165c8: af00 add r7, sp, #0 80165ca: 6078 str r0, [r7, #4] get called - the lock count on the queue will get modified instead. This means exclusive access to the event list is guaranteed here. This function assumes that a check has already been made to ensure that pxEventList is not empty. */ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80165cc: 687b ldr r3, [r7, #4] 80165ce: 68db ldr r3, [r3, #12] 80165d0: 68db ldr r3, [r3, #12] 80165d2: 613b str r3, [r7, #16] configASSERT( pxUnblockedTCB ); 80165d4: 693b ldr r3, [r7, #16] 80165d6: 2b00 cmp r3, #0 80165d8: d10b bne.n 80165f2 __asm volatile 80165da: f04f 0350 mov.w r3, #80 @ 0x50 80165de: f383 8811 msr BASEPRI, r3 80165e2: f3bf 8f6f isb sy 80165e6: f3bf 8f4f dsb sy 80165ea: 60fb str r3, [r7, #12] } 80165ec: bf00 nop 80165ee: bf00 nop 80165f0: e7fd b.n 80165ee ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); 80165f2: 693b ldr r3, [r7, #16] 80165f4: 3318 adds r3, #24 80165f6: 4618 mov r0, r3 80165f8: f7fe f9c4 bl 8014984 if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80165fc: 4b1d ldr r3, [pc, #116] @ (8016674 ) 80165fe: 681b ldr r3, [r3, #0] 8016600: 2b00 cmp r3, #0 8016602: d11d bne.n 8016640 { ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); 8016604: 693b ldr r3, [r7, #16] 8016606: 3304 adds r3, #4 8016608: 4618 mov r0, r3 801660a: f7fe f9bb bl 8014984 prvAddTaskToReadyList( pxUnblockedTCB ); 801660e: 693b ldr r3, [r7, #16] 8016610: 6ada ldr r2, [r3, #44] @ 0x2c 8016612: 4b19 ldr r3, [pc, #100] @ (8016678 ) 8016614: 681b ldr r3, [r3, #0] 8016616: 429a cmp r2, r3 8016618: d903 bls.n 8016622 801661a: 693b ldr r3, [r7, #16] 801661c: 6adb ldr r3, [r3, #44] @ 0x2c 801661e: 4a16 ldr r2, [pc, #88] @ (8016678 ) 8016620: 6013 str r3, [r2, #0] 8016622: 693b ldr r3, [r7, #16] 8016624: 6ada ldr r2, [r3, #44] @ 0x2c 8016626: 4613 mov r3, r2 8016628: 009b lsls r3, r3, #2 801662a: 4413 add r3, r2 801662c: 009b lsls r3, r3, #2 801662e: 4a13 ldr r2, [pc, #76] @ (801667c ) 8016630: 441a add r2, r3 8016632: 693b ldr r3, [r7, #16] 8016634: 3304 adds r3, #4 8016636: 4619 mov r1, r3 8016638: 4610 mov r0, r2 801663a: f7fe f946 bl 80148ca 801663e: e005 b.n 801664c } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); 8016640: 693b ldr r3, [r7, #16] 8016642: 3318 adds r3, #24 8016644: 4619 mov r1, r3 8016646: 480e ldr r0, [pc, #56] @ (8016680 ) 8016648: f7fe f93f bl 80148ca } if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) 801664c: 693b ldr r3, [r7, #16] 801664e: 6ada ldr r2, [r3, #44] @ 0x2c 8016650: 4b0c ldr r3, [pc, #48] @ (8016684 ) 8016652: 681b ldr r3, [r3, #0] 8016654: 6adb ldr r3, [r3, #44] @ 0x2c 8016656: 429a cmp r2, r3 8016658: d905 bls.n 8016666 { /* Return true if the task removed from the event list has a higher priority than the calling task. This allows the calling task to know if it should force a context switch now. */ xReturn = pdTRUE; 801665a: 2301 movs r3, #1 801665c: 617b str r3, [r7, #20] /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 801665e: 4b0a ldr r3, [pc, #40] @ (8016688 ) 8016660: 2201 movs r2, #1 8016662: 601a str r2, [r3, #0] 8016664: e001 b.n 801666a } else { xReturn = pdFALSE; 8016666: 2300 movs r3, #0 8016668: 617b str r3, [r7, #20] } return xReturn; 801666a: 697b ldr r3, [r7, #20] } 801666c: 4618 mov r0, r3 801666e: 3718 adds r7, #24 8016670: 46bd mov sp, r7 8016672: bd80 pop {r7, pc} 8016674: 24002ef4 .word 0x24002ef4 8016678: 24002ed4 .word 0x24002ed4 801667c: 240029fc .word 0x240029fc 8016680: 24002e8c .word 0x24002e8c 8016684: 240029f8 .word 0x240029f8 8016688: 24002ee0 .word 0x24002ee0 0801668c : } } /*-----------------------------------------------------------*/ void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) { 801668c: b580 push {r7, lr} 801668e: b084 sub sp, #16 8016690: af00 add r7, sp, #0 8016692: 6078 str r0, [r7, #4] configASSERT( pxTimeOut ); 8016694: 687b ldr r3, [r7, #4] 8016696: 2b00 cmp r3, #0 8016698: d10b bne.n 80166b2 __asm volatile 801669a: f04f 0350 mov.w r3, #80 @ 0x50 801669e: f383 8811 msr BASEPRI, r3 80166a2: f3bf 8f6f isb sy 80166a6: f3bf 8f4f dsb sy 80166aa: 60fb str r3, [r7, #12] } 80166ac: bf00 nop 80166ae: bf00 nop 80166b0: e7fd b.n 80166ae taskENTER_CRITICAL(); 80166b2: f001 fb09 bl 8017cc8 { pxTimeOut->xOverflowCount = xNumOfOverflows; 80166b6: 4b07 ldr r3, [pc, #28] @ (80166d4 ) 80166b8: 681a ldr r2, [r3, #0] 80166ba: 687b ldr r3, [r7, #4] 80166bc: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 80166be: 4b06 ldr r3, [pc, #24] @ (80166d8 ) 80166c0: 681a ldr r2, [r3, #0] 80166c2: 687b ldr r3, [r7, #4] 80166c4: 605a str r2, [r3, #4] } taskEXIT_CRITICAL(); 80166c6: f001 fb31 bl 8017d2c } 80166ca: bf00 nop 80166cc: 3710 adds r7, #16 80166ce: 46bd mov sp, r7 80166d0: bd80 pop {r7, pc} 80166d2: bf00 nop 80166d4: 24002ee4 .word 0x24002ee4 80166d8: 24002ed0 .word 0x24002ed0 080166dc : /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { 80166dc: b480 push {r7} 80166de: b083 sub sp, #12 80166e0: af00 add r7, sp, #0 80166e2: 6078 str r0, [r7, #4] /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; 80166e4: 4b06 ldr r3, [pc, #24] @ (8016700 ) 80166e6: 681a ldr r2, [r3, #0] 80166e8: 687b ldr r3, [r7, #4] 80166ea: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 80166ec: 4b05 ldr r3, [pc, #20] @ (8016704 ) 80166ee: 681a ldr r2, [r3, #0] 80166f0: 687b ldr r3, [r7, #4] 80166f2: 605a str r2, [r3, #4] } 80166f4: bf00 nop 80166f6: 370c adds r7, #12 80166f8: 46bd mov sp, r7 80166fa: f85d 7b04 ldr.w r7, [sp], #4 80166fe: 4770 bx lr 8016700: 24002ee4 .word 0x24002ee4 8016704: 24002ed0 .word 0x24002ed0 08016708 : /*-----------------------------------------------------------*/ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) { 8016708: b580 push {r7, lr} 801670a: b088 sub sp, #32 801670c: af00 add r7, sp, #0 801670e: 6078 str r0, [r7, #4] 8016710: 6039 str r1, [r7, #0] BaseType_t xReturn; configASSERT( pxTimeOut ); 8016712: 687b ldr r3, [r7, #4] 8016714: 2b00 cmp r3, #0 8016716: d10b bne.n 8016730 __asm volatile 8016718: f04f 0350 mov.w r3, #80 @ 0x50 801671c: f383 8811 msr BASEPRI, r3 8016720: f3bf 8f6f isb sy 8016724: f3bf 8f4f dsb sy 8016728: 613b str r3, [r7, #16] } 801672a: bf00 nop 801672c: bf00 nop 801672e: e7fd b.n 801672c configASSERT( pxTicksToWait ); 8016730: 683b ldr r3, [r7, #0] 8016732: 2b00 cmp r3, #0 8016734: d10b bne.n 801674e __asm volatile 8016736: f04f 0350 mov.w r3, #80 @ 0x50 801673a: f383 8811 msr BASEPRI, r3 801673e: f3bf 8f6f isb sy 8016742: f3bf 8f4f dsb sy 8016746: 60fb str r3, [r7, #12] } 8016748: bf00 nop 801674a: bf00 nop 801674c: e7fd b.n 801674a taskENTER_CRITICAL(); 801674e: f001 fabb bl 8017cc8 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; 8016752: 4b1d ldr r3, [pc, #116] @ (80167c8 ) 8016754: 681b ldr r3, [r3, #0] 8016756: 61bb str r3, [r7, #24] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; 8016758: 687b ldr r3, [r7, #4] 801675a: 685b ldr r3, [r3, #4] 801675c: 69ba ldr r2, [r7, #24] 801675e: 1ad3 subs r3, r2, r3 8016760: 617b str r3, [r7, #20] } else #endif #if ( INCLUDE_vTaskSuspend == 1 ) if( *pxTicksToWait == portMAX_DELAY ) 8016762: 683b ldr r3, [r7, #0] 8016764: 681b ldr r3, [r3, #0] 8016766: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801676a: d102 bne.n 8016772 { /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is the maximum block time then the task should block indefinitely, and therefore never time out. */ xReturn = pdFALSE; 801676c: 2300 movs r3, #0 801676e: 61fb str r3, [r7, #28] 8016770: e023 b.n 80167ba } else #endif if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ 8016772: 687b ldr r3, [r7, #4] 8016774: 681a ldr r2, [r3, #0] 8016776: 4b15 ldr r3, [pc, #84] @ (80167cc ) 8016778: 681b ldr r3, [r3, #0] 801677a: 429a cmp r2, r3 801677c: d007 beq.n 801678e 801677e: 687b ldr r3, [r7, #4] 8016780: 685b ldr r3, [r3, #4] 8016782: 69ba ldr r2, [r7, #24] 8016784: 429a cmp r2, r3 8016786: d302 bcc.n 801678e /* The tick count is greater than the time at which vTaskSetTimeout() was called, but has also overflowed since vTaskSetTimeOut() was called. It must have wrapped all the way around and gone past again. This passed since vTaskSetTimeout() was called. */ xReturn = pdTRUE; 8016788: 2301 movs r3, #1 801678a: 61fb str r3, [r7, #28] 801678c: e015 b.n 80167ba } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ 801678e: 683b ldr r3, [r7, #0] 8016790: 681b ldr r3, [r3, #0] 8016792: 697a ldr r2, [r7, #20] 8016794: 429a cmp r2, r3 8016796: d20b bcs.n 80167b0 { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; 8016798: 683b ldr r3, [r7, #0] 801679a: 681a ldr r2, [r3, #0] 801679c: 697b ldr r3, [r7, #20] 801679e: 1ad2 subs r2, r2, r3 80167a0: 683b ldr r3, [r7, #0] 80167a2: 601a str r2, [r3, #0] vTaskInternalSetTimeOutState( pxTimeOut ); 80167a4: 6878 ldr r0, [r7, #4] 80167a6: f7ff ff99 bl 80166dc xReturn = pdFALSE; 80167aa: 2300 movs r3, #0 80167ac: 61fb str r3, [r7, #28] 80167ae: e004 b.n 80167ba } else { *pxTicksToWait = 0; 80167b0: 683b ldr r3, [r7, #0] 80167b2: 2200 movs r2, #0 80167b4: 601a str r2, [r3, #0] xReturn = pdTRUE; 80167b6: 2301 movs r3, #1 80167b8: 61fb str r3, [r7, #28] } } taskEXIT_CRITICAL(); 80167ba: f001 fab7 bl 8017d2c return xReturn; 80167be: 69fb ldr r3, [r7, #28] } 80167c0: 4618 mov r0, r3 80167c2: 3720 adds r7, #32 80167c4: 46bd mov sp, r7 80167c6: bd80 pop {r7, pc} 80167c8: 24002ed0 .word 0x24002ed0 80167cc: 24002ee4 .word 0x24002ee4 080167d0 : /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { 80167d0: b480 push {r7} 80167d2: af00 add r7, sp, #0 xYieldPending = pdTRUE; 80167d4: 4b03 ldr r3, [pc, #12] @ (80167e4 ) 80167d6: 2201 movs r2, #1 80167d8: 601a str r2, [r3, #0] } 80167da: bf00 nop 80167dc: 46bd mov sp, r7 80167de: f85d 7b04 ldr.w r7, [sp], #4 80167e2: 4770 bx lr 80167e4: 24002ee0 .word 0x24002ee0 080167e8 : * * void prvIdleTask( void *pvParameters ); * */ static portTASK_FUNCTION( prvIdleTask, pvParameters ) { 80167e8: b580 push {r7, lr} 80167ea: b082 sub sp, #8 80167ec: af00 add r7, sp, #0 80167ee: 6078 str r0, [r7, #4] for( ;; ) { /* See if any tasks have deleted themselves - if so then the idle task is responsible for freeing the deleted task's TCB and stack. */ prvCheckTasksWaitingTermination(); 80167f0: f000 f852 bl 8016898 A critical region is not required here as we are just reading from the list, and an occasional incorrect value will not matter. If the ready list at the idle priority contains more than one task then a task other than the idle task is ready to execute. */ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) 80167f4: 4b06 ldr r3, [pc, #24] @ (8016810 ) 80167f6: 681b ldr r3, [r3, #0] 80167f8: 2b01 cmp r3, #1 80167fa: d9f9 bls.n 80167f0 { taskYIELD(); 80167fc: 4b05 ldr r3, [pc, #20] @ (8016814 ) 80167fe: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016802: 601a str r2, [r3, #0] 8016804: f3bf 8f4f dsb sy 8016808: f3bf 8f6f isb sy prvCheckTasksWaitingTermination(); 801680c: e7f0 b.n 80167f0 801680e: bf00 nop 8016810: 240029fc .word 0x240029fc 8016814: e000ed04 .word 0xe000ed04 08016818 : #endif /* portUSING_MPU_WRAPPERS */ /*-----------------------------------------------------------*/ static void prvInitialiseTaskLists( void ) { 8016818: b580 push {r7, lr} 801681a: b082 sub sp, #8 801681c: af00 add r7, sp, #0 UBaseType_t uxPriority; for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 801681e: 2300 movs r3, #0 8016820: 607b str r3, [r7, #4] 8016822: e00c b.n 801683e { vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); 8016824: 687a ldr r2, [r7, #4] 8016826: 4613 mov r3, r2 8016828: 009b lsls r3, r3, #2 801682a: 4413 add r3, r2 801682c: 009b lsls r3, r3, #2 801682e: 4a12 ldr r2, [pc, #72] @ (8016878 ) 8016830: 4413 add r3, r2 8016832: 4618 mov r0, r3 8016834: f7fe f81c bl 8014870 for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 8016838: 687b ldr r3, [r7, #4] 801683a: 3301 adds r3, #1 801683c: 607b str r3, [r7, #4] 801683e: 687b ldr r3, [r7, #4] 8016840: 2b37 cmp r3, #55 @ 0x37 8016842: d9ef bls.n 8016824 } vListInitialise( &xDelayedTaskList1 ); 8016844: 480d ldr r0, [pc, #52] @ (801687c ) 8016846: f7fe f813 bl 8014870 vListInitialise( &xDelayedTaskList2 ); 801684a: 480d ldr r0, [pc, #52] @ (8016880 ) 801684c: f7fe f810 bl 8014870 vListInitialise( &xPendingReadyList ); 8016850: 480c ldr r0, [pc, #48] @ (8016884 ) 8016852: f7fe f80d bl 8014870 #if ( INCLUDE_vTaskDelete == 1 ) { vListInitialise( &xTasksWaitingTermination ); 8016856: 480c ldr r0, [pc, #48] @ (8016888 ) 8016858: f7fe f80a bl 8014870 } #endif /* INCLUDE_vTaskDelete */ #if ( INCLUDE_vTaskSuspend == 1 ) { vListInitialise( &xSuspendedTaskList ); 801685c: 480b ldr r0, [pc, #44] @ (801688c ) 801685e: f7fe f807 bl 8014870 } #endif /* INCLUDE_vTaskSuspend */ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList using list2. */ pxDelayedTaskList = &xDelayedTaskList1; 8016862: 4b0b ldr r3, [pc, #44] @ (8016890 ) 8016864: 4a05 ldr r2, [pc, #20] @ (801687c ) 8016866: 601a str r2, [r3, #0] pxOverflowDelayedTaskList = &xDelayedTaskList2; 8016868: 4b0a ldr r3, [pc, #40] @ (8016894 ) 801686a: 4a05 ldr r2, [pc, #20] @ (8016880 ) 801686c: 601a str r2, [r3, #0] } 801686e: bf00 nop 8016870: 3708 adds r7, #8 8016872: 46bd mov sp, r7 8016874: bd80 pop {r7, pc} 8016876: bf00 nop 8016878: 240029fc .word 0x240029fc 801687c: 24002e5c .word 0x24002e5c 8016880: 24002e70 .word 0x24002e70 8016884: 24002e8c .word 0x24002e8c 8016888: 24002ea0 .word 0x24002ea0 801688c: 24002eb8 .word 0x24002eb8 8016890: 24002e84 .word 0x24002e84 8016894: 24002e88 .word 0x24002e88 08016898 : /*-----------------------------------------------------------*/ static void prvCheckTasksWaitingTermination( void ) { 8016898: b580 push {r7, lr} 801689a: b082 sub sp, #8 801689c: af00 add r7, sp, #0 { TCB_t *pxTCB; /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 801689e: e019 b.n 80168d4 { taskENTER_CRITICAL(); 80168a0: f001 fa12 bl 8017cc8 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80168a4: 4b10 ldr r3, [pc, #64] @ (80168e8 ) 80168a6: 68db ldr r3, [r3, #12] 80168a8: 68db ldr r3, [r3, #12] 80168aa: 607b str r3, [r7, #4] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80168ac: 687b ldr r3, [r7, #4] 80168ae: 3304 adds r3, #4 80168b0: 4618 mov r0, r3 80168b2: f7fe f867 bl 8014984 --uxCurrentNumberOfTasks; 80168b6: 4b0d ldr r3, [pc, #52] @ (80168ec ) 80168b8: 681b ldr r3, [r3, #0] 80168ba: 3b01 subs r3, #1 80168bc: 4a0b ldr r2, [pc, #44] @ (80168ec ) 80168be: 6013 str r3, [r2, #0] --uxDeletedTasksWaitingCleanUp; 80168c0: 4b0b ldr r3, [pc, #44] @ (80168f0 ) 80168c2: 681b ldr r3, [r3, #0] 80168c4: 3b01 subs r3, #1 80168c6: 4a0a ldr r2, [pc, #40] @ (80168f0 ) 80168c8: 6013 str r3, [r2, #0] } taskEXIT_CRITICAL(); 80168ca: f001 fa2f bl 8017d2c prvDeleteTCB( pxTCB ); 80168ce: 6878 ldr r0, [r7, #4] 80168d0: f000 f810 bl 80168f4 while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 80168d4: 4b06 ldr r3, [pc, #24] @ (80168f0 ) 80168d6: 681b ldr r3, [r3, #0] 80168d8: 2b00 cmp r3, #0 80168da: d1e1 bne.n 80168a0 } } #endif /* INCLUDE_vTaskDelete */ } 80168dc: bf00 nop 80168de: bf00 nop 80168e0: 3708 adds r7, #8 80168e2: 46bd mov sp, r7 80168e4: bd80 pop {r7, pc} 80168e6: bf00 nop 80168e8: 24002ea0 .word 0x24002ea0 80168ec: 24002ecc .word 0x24002ecc 80168f0: 24002eb4 .word 0x24002eb4 080168f4 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelete == 1 ) static void prvDeleteTCB( TCB_t *pxTCB ) { 80168f4: b580 push {r7, lr} 80168f6: b084 sub sp, #16 80168f8: af00 add r7, sp, #0 80168fa: 6078 str r0, [r7, #4] to the task to free any memory allocated at the application level. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ #if ( configUSE_NEWLIB_REENTRANT == 1 ) { _reclaim_reent( &( pxTCB->xNewLib_reent ) ); 80168fc: 687b ldr r3, [r7, #4] 80168fe: 3354 adds r3, #84 @ 0x54 8016900: 4618 mov r0, r3 8016902: f001 fcf9 bl 80182f8 <_reclaim_reent> #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* The task could have been allocated statically or dynamically, so check what was statically allocated before trying to free the memory. */ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) 8016906: 687b ldr r3, [r7, #4] 8016908: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 801690c: 2b00 cmp r3, #0 801690e: d108 bne.n 8016922 { /* Both the stack and TCB were allocated dynamically, so both must be freed. */ vPortFree( pxTCB->pxStack ); 8016910: 687b ldr r3, [r7, #4] 8016912: 6b1b ldr r3, [r3, #48] @ 0x30 8016914: 4618 mov r0, r3 8016916: f001 fbc7 bl 80180a8 vPortFree( pxTCB ); 801691a: 6878 ldr r0, [r7, #4] 801691c: f001 fbc4 bl 80180a8 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); mtCOVERAGE_TEST_MARKER(); } } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } 8016920: e019 b.n 8016956 else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) 8016922: 687b ldr r3, [r7, #4] 8016924: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8016928: 2b01 cmp r3, #1 801692a: d103 bne.n 8016934 vPortFree( pxTCB ); 801692c: 6878 ldr r0, [r7, #4] 801692e: f001 fbbb bl 80180a8 } 8016932: e010 b.n 8016956 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); 8016934: 687b ldr r3, [r7, #4] 8016936: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 801693a: 2b02 cmp r3, #2 801693c: d00b beq.n 8016956 __asm volatile 801693e: f04f 0350 mov.w r3, #80 @ 0x50 8016942: f383 8811 msr BASEPRI, r3 8016946: f3bf 8f6f isb sy 801694a: f3bf 8f4f dsb sy 801694e: 60fb str r3, [r7, #12] } 8016950: bf00 nop 8016952: bf00 nop 8016954: e7fd b.n 8016952 } 8016956: bf00 nop 8016958: 3710 adds r7, #16 801695a: 46bd mov sp, r7 801695c: bd80 pop {r7, pc} ... 08016960 : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { 8016960: b480 push {r7} 8016962: b083 sub sp, #12 8016964: af00 add r7, sp, #0 TCB_t *pxTCB; if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8016966: 4b0c ldr r3, [pc, #48] @ (8016998 ) 8016968: 681b ldr r3, [r3, #0] 801696a: 681b ldr r3, [r3, #0] 801696c: 2b00 cmp r3, #0 801696e: d104 bne.n 801697a { /* The new current delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass until there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; 8016970: 4b0a ldr r3, [pc, #40] @ (801699c ) 8016972: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8016976: 601a str r2, [r3, #0] which the task at the head of the delayed list should be removed from the Blocked state. */ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); } } 8016978: e008 b.n 801698c ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 801697a: 4b07 ldr r3, [pc, #28] @ (8016998 ) 801697c: 681b ldr r3, [r3, #0] 801697e: 68db ldr r3, [r3, #12] 8016980: 68db ldr r3, [r3, #12] 8016982: 607b str r3, [r7, #4] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 8016984: 687b ldr r3, [r7, #4] 8016986: 685b ldr r3, [r3, #4] 8016988: 4a04 ldr r2, [pc, #16] @ (801699c ) 801698a: 6013 str r3, [r2, #0] } 801698c: bf00 nop 801698e: 370c adds r7, #12 8016990: 46bd mov sp, r7 8016992: f85d 7b04 ldr.w r7, [sp], #4 8016996: 4770 bx lr 8016998: 24002e84 .word 0x24002e84 801699c: 24002eec .word 0x24002eec 080169a0 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) TaskHandle_t xTaskGetCurrentTaskHandle( void ) { 80169a0: b480 push {r7} 80169a2: b083 sub sp, #12 80169a4: af00 add r7, sp, #0 TaskHandle_t xReturn; /* A critical section is not required as this is not called from an interrupt and the current TCB will always be the same for any individual execution thread. */ xReturn = pxCurrentTCB; 80169a6: 4b05 ldr r3, [pc, #20] @ (80169bc ) 80169a8: 681b ldr r3, [r3, #0] 80169aa: 607b str r3, [r7, #4] return xReturn; 80169ac: 687b ldr r3, [r7, #4] } 80169ae: 4618 mov r0, r3 80169b0: 370c adds r7, #12 80169b2: 46bd mov sp, r7 80169b4: f85d 7b04 ldr.w r7, [sp], #4 80169b8: 4770 bx lr 80169ba: bf00 nop 80169bc: 240029f8 .word 0x240029f8 080169c0 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) BaseType_t xTaskGetSchedulerState( void ) { 80169c0: b480 push {r7} 80169c2: b083 sub sp, #12 80169c4: af00 add r7, sp, #0 BaseType_t xReturn; if( xSchedulerRunning == pdFALSE ) 80169c6: 4b0b ldr r3, [pc, #44] @ (80169f4 ) 80169c8: 681b ldr r3, [r3, #0] 80169ca: 2b00 cmp r3, #0 80169cc: d102 bne.n 80169d4 { xReturn = taskSCHEDULER_NOT_STARTED; 80169ce: 2301 movs r3, #1 80169d0: 607b str r3, [r7, #4] 80169d2: e008 b.n 80169e6 } else { if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80169d4: 4b08 ldr r3, [pc, #32] @ (80169f8 ) 80169d6: 681b ldr r3, [r3, #0] 80169d8: 2b00 cmp r3, #0 80169da: d102 bne.n 80169e2 { xReturn = taskSCHEDULER_RUNNING; 80169dc: 2302 movs r3, #2 80169de: 607b str r3, [r7, #4] 80169e0: e001 b.n 80169e6 } else { xReturn = taskSCHEDULER_SUSPENDED; 80169e2: 2300 movs r3, #0 80169e4: 607b str r3, [r7, #4] } } return xReturn; 80169e6: 687b ldr r3, [r7, #4] } 80169e8: 4618 mov r0, r3 80169ea: 370c adds r7, #12 80169ec: 46bd mov sp, r7 80169ee: f85d 7b04 ldr.w r7, [sp], #4 80169f2: 4770 bx lr 80169f4: 24002ed8 .word 0x24002ed8 80169f8: 24002ef4 .word 0x24002ef4 080169fc : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) { 80169fc: b580 push {r7, lr} 80169fe: b084 sub sp, #16 8016a00: af00 add r7, sp, #0 8016a02: 6078 str r0, [r7, #4] TCB_t * const pxMutexHolderTCB = pxMutexHolder; 8016a04: 687b ldr r3, [r7, #4] 8016a06: 60bb str r3, [r7, #8] BaseType_t xReturn = pdFALSE; 8016a08: 2300 movs r3, #0 8016a0a: 60fb str r3, [r7, #12] /* If the mutex was given back by an interrupt while the queue was locked then the mutex holder might now be NULL. _RB_ Is this still needed as interrupts can no longer use mutexes? */ if( pxMutexHolder != NULL ) 8016a0c: 687b ldr r3, [r7, #4] 8016a0e: 2b00 cmp r3, #0 8016a10: d051 beq.n 8016ab6 { /* If the holder of the mutex has a priority below the priority of the task attempting to obtain the mutex then it will temporarily inherit the priority of the task attempting to obtain the mutex. */ if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) 8016a12: 68bb ldr r3, [r7, #8] 8016a14: 6ada ldr r2, [r3, #44] @ 0x2c 8016a16: 4b2a ldr r3, [pc, #168] @ (8016ac0 ) 8016a18: 681b ldr r3, [r3, #0] 8016a1a: 6adb ldr r3, [r3, #44] @ 0x2c 8016a1c: 429a cmp r2, r3 8016a1e: d241 bcs.n 8016aa4 { /* Adjust the mutex holder state to account for its new priority. Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 8016a20: 68bb ldr r3, [r7, #8] 8016a22: 699b ldr r3, [r3, #24] 8016a24: 2b00 cmp r3, #0 8016a26: db06 blt.n 8016a36 { listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016a28: 4b25 ldr r3, [pc, #148] @ (8016ac0 ) 8016a2a: 681b ldr r3, [r3, #0] 8016a2c: 6adb ldr r3, [r3, #44] @ 0x2c 8016a2e: f1c3 0238 rsb r2, r3, #56 @ 0x38 8016a32: 68bb ldr r3, [r7, #8] 8016a34: 619a str r2, [r3, #24] mtCOVERAGE_TEST_MARKER(); } /* If the task being modified is in the ready state it will need to be moved into a new list. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) 8016a36: 68bb ldr r3, [r7, #8] 8016a38: 6959 ldr r1, [r3, #20] 8016a3a: 68bb ldr r3, [r7, #8] 8016a3c: 6ada ldr r2, [r3, #44] @ 0x2c 8016a3e: 4613 mov r3, r2 8016a40: 009b lsls r3, r3, #2 8016a42: 4413 add r3, r2 8016a44: 009b lsls r3, r3, #2 8016a46: 4a1f ldr r2, [pc, #124] @ (8016ac4 ) 8016a48: 4413 add r3, r2 8016a4a: 4299 cmp r1, r3 8016a4c: d122 bne.n 8016a94 { if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016a4e: 68bb ldr r3, [r7, #8] 8016a50: 3304 adds r3, #4 8016a52: 4618 mov r0, r3 8016a54: f7fd ff96 bl 8014984 { mtCOVERAGE_TEST_MARKER(); } /* Inherit the priority before being moved into the new list. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8016a58: 4b19 ldr r3, [pc, #100] @ (8016ac0 ) 8016a5a: 681b ldr r3, [r3, #0] 8016a5c: 6ada ldr r2, [r3, #44] @ 0x2c 8016a5e: 68bb ldr r3, [r7, #8] 8016a60: 62da str r2, [r3, #44] @ 0x2c prvAddTaskToReadyList( pxMutexHolderTCB ); 8016a62: 68bb ldr r3, [r7, #8] 8016a64: 6ada ldr r2, [r3, #44] @ 0x2c 8016a66: 4b18 ldr r3, [pc, #96] @ (8016ac8 ) 8016a68: 681b ldr r3, [r3, #0] 8016a6a: 429a cmp r2, r3 8016a6c: d903 bls.n 8016a76 8016a6e: 68bb ldr r3, [r7, #8] 8016a70: 6adb ldr r3, [r3, #44] @ 0x2c 8016a72: 4a15 ldr r2, [pc, #84] @ (8016ac8 ) 8016a74: 6013 str r3, [r2, #0] 8016a76: 68bb ldr r3, [r7, #8] 8016a78: 6ada ldr r2, [r3, #44] @ 0x2c 8016a7a: 4613 mov r3, r2 8016a7c: 009b lsls r3, r3, #2 8016a7e: 4413 add r3, r2 8016a80: 009b lsls r3, r3, #2 8016a82: 4a10 ldr r2, [pc, #64] @ (8016ac4 ) 8016a84: 441a add r2, r3 8016a86: 68bb ldr r3, [r7, #8] 8016a88: 3304 adds r3, #4 8016a8a: 4619 mov r1, r3 8016a8c: 4610 mov r0, r2 8016a8e: f7fd ff1c bl 80148ca 8016a92: e004 b.n 8016a9e } else { /* Just inherit the priority. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8016a94: 4b0a ldr r3, [pc, #40] @ (8016ac0 ) 8016a96: 681b ldr r3, [r3, #0] 8016a98: 6ada ldr r2, [r3, #44] @ 0x2c 8016a9a: 68bb ldr r3, [r7, #8] 8016a9c: 62da str r2, [r3, #44] @ 0x2c } traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); /* Inheritance occurred. */ xReturn = pdTRUE; 8016a9e: 2301 movs r3, #1 8016aa0: 60fb str r3, [r7, #12] 8016aa2: e008 b.n 8016ab6 } else { if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) 8016aa4: 68bb ldr r3, [r7, #8] 8016aa6: 6cda ldr r2, [r3, #76] @ 0x4c 8016aa8: 4b05 ldr r3, [pc, #20] @ (8016ac0 ) 8016aaa: 681b ldr r3, [r3, #0] 8016aac: 6adb ldr r3, [r3, #44] @ 0x2c 8016aae: 429a cmp r2, r3 8016ab0: d201 bcs.n 8016ab6 current priority of the mutex holder is not lower than the priority of the task attempting to take the mutex. Therefore the mutex holder must have already inherited a priority, but inheritance would have occurred if that had not been the case. */ xReturn = pdTRUE; 8016ab2: 2301 movs r3, #1 8016ab4: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8016ab6: 68fb ldr r3, [r7, #12] } 8016ab8: 4618 mov r0, r3 8016aba: 3710 adds r7, #16 8016abc: 46bd mov sp, r7 8016abe: bd80 pop {r7, pc} 8016ac0: 240029f8 .word 0x240029f8 8016ac4: 240029fc .word 0x240029fc 8016ac8: 24002ed4 .word 0x24002ed4 08016acc : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { 8016acc: b580 push {r7, lr} 8016ace: b086 sub sp, #24 8016ad0: af00 add r7, sp, #0 8016ad2: 6078 str r0, [r7, #4] TCB_t * const pxTCB = pxMutexHolder; 8016ad4: 687b ldr r3, [r7, #4] 8016ad6: 613b str r3, [r7, #16] BaseType_t xReturn = pdFALSE; 8016ad8: 2300 movs r3, #0 8016ada: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 8016adc: 687b ldr r3, [r7, #4] 8016ade: 2b00 cmp r3, #0 8016ae0: d058 beq.n 8016b94 { /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. */ configASSERT( pxTCB == pxCurrentTCB ); 8016ae2: 4b2f ldr r3, [pc, #188] @ (8016ba0 ) 8016ae4: 681b ldr r3, [r3, #0] 8016ae6: 693a ldr r2, [r7, #16] 8016ae8: 429a cmp r2, r3 8016aea: d00b beq.n 8016b04 __asm volatile 8016aec: f04f 0350 mov.w r3, #80 @ 0x50 8016af0: f383 8811 msr BASEPRI, r3 8016af4: f3bf 8f6f isb sy 8016af8: f3bf 8f4f dsb sy 8016afc: 60fb str r3, [r7, #12] } 8016afe: bf00 nop 8016b00: bf00 nop 8016b02: e7fd b.n 8016b00 configASSERT( pxTCB->uxMutexesHeld ); 8016b04: 693b ldr r3, [r7, #16] 8016b06: 6d1b ldr r3, [r3, #80] @ 0x50 8016b08: 2b00 cmp r3, #0 8016b0a: d10b bne.n 8016b24 __asm volatile 8016b0c: f04f 0350 mov.w r3, #80 @ 0x50 8016b10: f383 8811 msr BASEPRI, r3 8016b14: f3bf 8f6f isb sy 8016b18: f3bf 8f4f dsb sy 8016b1c: 60bb str r3, [r7, #8] } 8016b1e: bf00 nop 8016b20: bf00 nop 8016b22: e7fd b.n 8016b20 ( pxTCB->uxMutexesHeld )--; 8016b24: 693b ldr r3, [r7, #16] 8016b26: 6d1b ldr r3, [r3, #80] @ 0x50 8016b28: 1e5a subs r2, r3, #1 8016b2a: 693b ldr r3, [r7, #16] 8016b2c: 651a str r2, [r3, #80] @ 0x50 /* Has the holder of the mutex inherited the priority of another task? */ if( pxTCB->uxPriority != pxTCB->uxBasePriority ) 8016b2e: 693b ldr r3, [r7, #16] 8016b30: 6ada ldr r2, [r3, #44] @ 0x2c 8016b32: 693b ldr r3, [r7, #16] 8016b34: 6cdb ldr r3, [r3, #76] @ 0x4c 8016b36: 429a cmp r2, r3 8016b38: d02c beq.n 8016b94 { /* Only disinherit if no other mutexes are held. */ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) 8016b3a: 693b ldr r3, [r7, #16] 8016b3c: 6d1b ldr r3, [r3, #80] @ 0x50 8016b3e: 2b00 cmp r3, #0 8016b40: d128 bne.n 8016b94 /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. Remove the holding task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016b42: 693b ldr r3, [r7, #16] 8016b44: 3304 adds r3, #4 8016b46: 4618 mov r0, r3 8016b48: f7fd ff1c bl 8014984 } /* Disinherit the priority before adding the task into the new ready list. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); pxTCB->uxPriority = pxTCB->uxBasePriority; 8016b4c: 693b ldr r3, [r7, #16] 8016b4e: 6cda ldr r2, [r3, #76] @ 0x4c 8016b50: 693b ldr r3, [r7, #16] 8016b52: 62da str r2, [r3, #44] @ 0x2c /* Reset the event list item value. It cannot be in use for any other purpose if this task is running, and it must be running to give back the mutex. */ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016b54: 693b ldr r3, [r7, #16] 8016b56: 6adb ldr r3, [r3, #44] @ 0x2c 8016b58: f1c3 0238 rsb r2, r3, #56 @ 0x38 8016b5c: 693b ldr r3, [r7, #16] 8016b5e: 619a str r2, [r3, #24] prvAddTaskToReadyList( pxTCB ); 8016b60: 693b ldr r3, [r7, #16] 8016b62: 6ada ldr r2, [r3, #44] @ 0x2c 8016b64: 4b0f ldr r3, [pc, #60] @ (8016ba4 ) 8016b66: 681b ldr r3, [r3, #0] 8016b68: 429a cmp r2, r3 8016b6a: d903 bls.n 8016b74 8016b6c: 693b ldr r3, [r7, #16] 8016b6e: 6adb ldr r3, [r3, #44] @ 0x2c 8016b70: 4a0c ldr r2, [pc, #48] @ (8016ba4 ) 8016b72: 6013 str r3, [r2, #0] 8016b74: 693b ldr r3, [r7, #16] 8016b76: 6ada ldr r2, [r3, #44] @ 0x2c 8016b78: 4613 mov r3, r2 8016b7a: 009b lsls r3, r3, #2 8016b7c: 4413 add r3, r2 8016b7e: 009b lsls r3, r3, #2 8016b80: 4a09 ldr r2, [pc, #36] @ (8016ba8 ) 8016b82: 441a add r2, r3 8016b84: 693b ldr r3, [r7, #16] 8016b86: 3304 adds r3, #4 8016b88: 4619 mov r1, r3 8016b8a: 4610 mov r0, r2 8016b8c: f7fd fe9d bl 80148ca in an order different to that in which they were taken. If a context switch did not occur when the first mutex was returned, even if a task was waiting on it, then a context switch should occur when the last mutex is returned whether a task is waiting on it or not. */ xReturn = pdTRUE; 8016b90: 2301 movs r3, #1 8016b92: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8016b94: 697b ldr r3, [r7, #20] } 8016b96: 4618 mov r0, r3 8016b98: 3718 adds r7, #24 8016b9a: 46bd mov sp, r7 8016b9c: bd80 pop {r7, pc} 8016b9e: bf00 nop 8016ba0: 240029f8 .word 0x240029f8 8016ba4: 24002ed4 .word 0x24002ed4 8016ba8: 240029fc .word 0x240029fc 08016bac : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) { 8016bac: b580 push {r7, lr} 8016bae: b088 sub sp, #32 8016bb0: af00 add r7, sp, #0 8016bb2: 6078 str r0, [r7, #4] 8016bb4: 6039 str r1, [r7, #0] TCB_t * const pxTCB = pxMutexHolder; 8016bb6: 687b ldr r3, [r7, #4] 8016bb8: 61bb str r3, [r7, #24] UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; 8016bba: 2301 movs r3, #1 8016bbc: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 8016bbe: 687b ldr r3, [r7, #4] 8016bc0: 2b00 cmp r3, #0 8016bc2: d06c beq.n 8016c9e { /* If pxMutexHolder is not NULL then the holder must hold at least one mutex. */ configASSERT( pxTCB->uxMutexesHeld ); 8016bc4: 69bb ldr r3, [r7, #24] 8016bc6: 6d1b ldr r3, [r3, #80] @ 0x50 8016bc8: 2b00 cmp r3, #0 8016bca: d10b bne.n 8016be4 __asm volatile 8016bcc: f04f 0350 mov.w r3, #80 @ 0x50 8016bd0: f383 8811 msr BASEPRI, r3 8016bd4: f3bf 8f6f isb sy 8016bd8: f3bf 8f4f dsb sy 8016bdc: 60fb str r3, [r7, #12] } 8016bde: bf00 nop 8016be0: bf00 nop 8016be2: e7fd b.n 8016be0 /* Determine the priority to which the priority of the task that holds the mutex should be set. This will be the greater of the holding task's base priority and the priority of the highest priority task that is waiting to obtain the mutex. */ if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) 8016be4: 69bb ldr r3, [r7, #24] 8016be6: 6cdb ldr r3, [r3, #76] @ 0x4c 8016be8: 683a ldr r2, [r7, #0] 8016bea: 429a cmp r2, r3 8016bec: d902 bls.n 8016bf4 { uxPriorityToUse = uxHighestPriorityWaitingTask; 8016bee: 683b ldr r3, [r7, #0] 8016bf0: 61fb str r3, [r7, #28] 8016bf2: e002 b.n 8016bfa } else { uxPriorityToUse = pxTCB->uxBasePriority; 8016bf4: 69bb ldr r3, [r7, #24] 8016bf6: 6cdb ldr r3, [r3, #76] @ 0x4c 8016bf8: 61fb str r3, [r7, #28] } /* Does the priority need to change? */ if( pxTCB->uxPriority != uxPriorityToUse ) 8016bfa: 69bb ldr r3, [r7, #24] 8016bfc: 6adb ldr r3, [r3, #44] @ 0x2c 8016bfe: 69fa ldr r2, [r7, #28] 8016c00: 429a cmp r2, r3 8016c02: d04c beq.n 8016c9e { /* Only disinherit if no other mutexes are held. This is a simplification in the priority inheritance implementation. If the task that holds the mutex is also holding other mutexes then the other mutexes may have caused the priority inheritance. */ if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) 8016c04: 69bb ldr r3, [r7, #24] 8016c06: 6d1b ldr r3, [r3, #80] @ 0x50 8016c08: 697a ldr r2, [r7, #20] 8016c0a: 429a cmp r2, r3 8016c0c: d147 bne.n 8016c9e { /* If a task has timed out because it already holds the mutex it was trying to obtain then it cannot of inherited its own priority. */ configASSERT( pxTCB != pxCurrentTCB ); 8016c0e: 4b26 ldr r3, [pc, #152] @ (8016ca8 ) 8016c10: 681b ldr r3, [r3, #0] 8016c12: 69ba ldr r2, [r7, #24] 8016c14: 429a cmp r2, r3 8016c16: d10b bne.n 8016c30 __asm volatile 8016c18: f04f 0350 mov.w r3, #80 @ 0x50 8016c1c: f383 8811 msr BASEPRI, r3 8016c20: f3bf 8f6f isb sy 8016c24: f3bf 8f4f dsb sy 8016c28: 60bb str r3, [r7, #8] } 8016c2a: bf00 nop 8016c2c: bf00 nop 8016c2e: e7fd b.n 8016c2c /* Disinherit the priority, remembering the previous priority to facilitate determining the subject task's state. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); uxPriorityUsedOnEntry = pxTCB->uxPriority; 8016c30: 69bb ldr r3, [r7, #24] 8016c32: 6adb ldr r3, [r3, #44] @ 0x2c 8016c34: 613b str r3, [r7, #16] pxTCB->uxPriority = uxPriorityToUse; 8016c36: 69bb ldr r3, [r7, #24] 8016c38: 69fa ldr r2, [r7, #28] 8016c3a: 62da str r2, [r3, #44] @ 0x2c /* Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 8016c3c: 69bb ldr r3, [r7, #24] 8016c3e: 699b ldr r3, [r3, #24] 8016c40: 2b00 cmp r3, #0 8016c42: db04 blt.n 8016c4e { listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016c44: 69fb ldr r3, [r7, #28] 8016c46: f1c3 0238 rsb r2, r3, #56 @ 0x38 8016c4a: 69bb ldr r3, [r7, #24] 8016c4c: 619a str r2, [r3, #24] then the task that holds the mutex could be in either the Ready, Blocked or Suspended states. Only remove the task from its current state list if it is in the Ready state as the task's priority is going to change and there is one Ready list per priority. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) 8016c4e: 69bb ldr r3, [r7, #24] 8016c50: 6959 ldr r1, [r3, #20] 8016c52: 693a ldr r2, [r7, #16] 8016c54: 4613 mov r3, r2 8016c56: 009b lsls r3, r3, #2 8016c58: 4413 add r3, r2 8016c5a: 009b lsls r3, r3, #2 8016c5c: 4a13 ldr r2, [pc, #76] @ (8016cac ) 8016c5e: 4413 add r3, r2 8016c60: 4299 cmp r1, r3 8016c62: d11c bne.n 8016c9e { if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016c64: 69bb ldr r3, [r7, #24] 8016c66: 3304 adds r3, #4 8016c68: 4618 mov r0, r3 8016c6a: f7fd fe8b bl 8014984 else { mtCOVERAGE_TEST_MARKER(); } prvAddTaskToReadyList( pxTCB ); 8016c6e: 69bb ldr r3, [r7, #24] 8016c70: 6ada ldr r2, [r3, #44] @ 0x2c 8016c72: 4b0f ldr r3, [pc, #60] @ (8016cb0 ) 8016c74: 681b ldr r3, [r3, #0] 8016c76: 429a cmp r2, r3 8016c78: d903 bls.n 8016c82 8016c7a: 69bb ldr r3, [r7, #24] 8016c7c: 6adb ldr r3, [r3, #44] @ 0x2c 8016c7e: 4a0c ldr r2, [pc, #48] @ (8016cb0 ) 8016c80: 6013 str r3, [r2, #0] 8016c82: 69bb ldr r3, [r7, #24] 8016c84: 6ada ldr r2, [r3, #44] @ 0x2c 8016c86: 4613 mov r3, r2 8016c88: 009b lsls r3, r3, #2 8016c8a: 4413 add r3, r2 8016c8c: 009b lsls r3, r3, #2 8016c8e: 4a07 ldr r2, [pc, #28] @ (8016cac ) 8016c90: 441a add r2, r3 8016c92: 69bb ldr r3, [r7, #24] 8016c94: 3304 adds r3, #4 8016c96: 4619 mov r1, r3 8016c98: 4610 mov r0, r2 8016c9a: f7fd fe16 bl 80148ca } else { mtCOVERAGE_TEST_MARKER(); } } 8016c9e: bf00 nop 8016ca0: 3720 adds r7, #32 8016ca2: 46bd mov sp, r7 8016ca4: bd80 pop {r7, pc} 8016ca6: bf00 nop 8016ca8: 240029f8 .word 0x240029f8 8016cac: 240029fc .word 0x240029fc 8016cb0: 24002ed4 .word 0x24002ed4 08016cb4 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) TaskHandle_t pvTaskIncrementMutexHeldCount( void ) { 8016cb4: b480 push {r7} 8016cb6: af00 add r7, sp, #0 /* If xSemaphoreCreateMutex() is called before any tasks have been created then pxCurrentTCB will be NULL. */ if( pxCurrentTCB != NULL ) 8016cb8: 4b07 ldr r3, [pc, #28] @ (8016cd8 ) 8016cba: 681b ldr r3, [r3, #0] 8016cbc: 2b00 cmp r3, #0 8016cbe: d004 beq.n 8016cca { ( pxCurrentTCB->uxMutexesHeld )++; 8016cc0: 4b05 ldr r3, [pc, #20] @ (8016cd8 ) 8016cc2: 681b ldr r3, [r3, #0] 8016cc4: 6d1a ldr r2, [r3, #80] @ 0x50 8016cc6: 3201 adds r2, #1 8016cc8: 651a str r2, [r3, #80] @ 0x50 } return pxCurrentTCB; 8016cca: 4b03 ldr r3, [pc, #12] @ (8016cd8 ) 8016ccc: 681b ldr r3, [r3, #0] } 8016cce: 4618 mov r0, r3 8016cd0: 46bd mov sp, r7 8016cd2: f85d 7b04 ldr.w r7, [sp], #4 8016cd6: 4770 bx lr 8016cd8: 240029f8 .word 0x240029f8 08016cdc : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) { 8016cdc: b580 push {r7, lr} 8016cde: b086 sub sp, #24 8016ce0: af00 add r7, sp, #0 8016ce2: 60f8 str r0, [r7, #12] 8016ce4: 60b9 str r1, [r7, #8] 8016ce6: 607a str r2, [r7, #4] 8016ce8: 603b str r3, [r7, #0] BaseType_t xReturn; taskENTER_CRITICAL(); 8016cea: f000 ffed bl 8017cc8 { /* Only block if a notification is not already pending. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 8016cee: 4b29 ldr r3, [pc, #164] @ (8016d94 ) 8016cf0: 681b ldr r3, [r3, #0] 8016cf2: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016cf6: b2db uxtb r3, r3 8016cf8: 2b02 cmp r3, #2 8016cfa: d01c beq.n 8016d36 { /* Clear bits in the task's notification value as bits may get set by the notifying task or interrupt. This can be used to clear the value to zero. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry; 8016cfc: 4b25 ldr r3, [pc, #148] @ (8016d94 ) 8016cfe: 681b ldr r3, [r3, #0] 8016d00: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 8016d04: 68fa ldr r2, [r7, #12] 8016d06: 43d2 mvns r2, r2 8016d08: 400a ands r2, r1 8016d0a: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 /* Mark this task as waiting for a notification. */ pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION; 8016d0e: 4b21 ldr r3, [pc, #132] @ (8016d94 ) 8016d10: 681b ldr r3, [r3, #0] 8016d12: 2201 movs r2, #1 8016d14: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 if( xTicksToWait > ( TickType_t ) 0 ) 8016d18: 683b ldr r3, [r7, #0] 8016d1a: 2b00 cmp r3, #0 8016d1c: d00b beq.n 8016d36 { prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 8016d1e: 2101 movs r1, #1 8016d20: 6838 ldr r0, [r7, #0] 8016d22: f000 fa09 bl 8017138 /* All ports are written to allow a yield in a critical section (some will yield immediately, others wait until the critical section exits) - but it is not something that application code should ever do. */ portYIELD_WITHIN_API(); 8016d26: 4b1c ldr r3, [pc, #112] @ (8016d98 ) 8016d28: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016d2c: 601a str r2, [r3, #0] 8016d2e: f3bf 8f4f dsb sy 8016d32: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016d36: f000 fff9 bl 8017d2c taskENTER_CRITICAL(); 8016d3a: f000 ffc5 bl 8017cc8 { traceTASK_NOTIFY_WAIT(); if( pulNotificationValue != NULL ) 8016d3e: 687b ldr r3, [r7, #4] 8016d40: 2b00 cmp r3, #0 8016d42: d005 beq.n 8016d50 { /* Output the current notification value, which may or may not have changed. */ *pulNotificationValue = pxCurrentTCB->ulNotifiedValue; 8016d44: 4b13 ldr r3, [pc, #76] @ (8016d94 ) 8016d46: 681b ldr r3, [r3, #0] 8016d48: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016d4c: 687b ldr r3, [r7, #4] 8016d4e: 601a str r2, [r3, #0] /* If ucNotifyValue is set then either the task never entered the blocked state (because a notification was already pending) or the task unblocked because of a notification. Otherwise the task unblocked because of a timeout. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 8016d50: 4b10 ldr r3, [pc, #64] @ (8016d94 ) 8016d52: 681b ldr r3, [r3, #0] 8016d54: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016d58: b2db uxtb r3, r3 8016d5a: 2b02 cmp r3, #2 8016d5c: d002 beq.n 8016d64 { /* A notification was not received. */ xReturn = pdFALSE; 8016d5e: 2300 movs r3, #0 8016d60: 617b str r3, [r7, #20] 8016d62: e00a b.n 8016d7a } else { /* A notification was already pending or a notification was received while the task was waiting. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit; 8016d64: 4b0b ldr r3, [pc, #44] @ (8016d94 ) 8016d66: 681b ldr r3, [r3, #0] 8016d68: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 8016d6c: 68ba ldr r2, [r7, #8] 8016d6e: 43d2 mvns r2, r2 8016d70: 400a ands r2, r1 8016d72: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 xReturn = pdTRUE; 8016d76: 2301 movs r3, #1 8016d78: 617b str r3, [r7, #20] } pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8016d7a: 4b06 ldr r3, [pc, #24] @ (8016d94 ) 8016d7c: 681b ldr r3, [r3, #0] 8016d7e: 2200 movs r2, #0 8016d80: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 } taskEXIT_CRITICAL(); 8016d84: f000 ffd2 bl 8017d2c return xReturn; 8016d88: 697b ldr r3, [r7, #20] } 8016d8a: 4618 mov r0, r3 8016d8c: 3718 adds r7, #24 8016d8e: 46bd mov sp, r7 8016d90: bd80 pop {r7, pc} 8016d92: bf00 nop 8016d94: 240029f8 .word 0x240029f8 8016d98: e000ed04 .word 0xe000ed04 08016d9c : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) { 8016d9c: b580 push {r7, lr} 8016d9e: b08a sub sp, #40 @ 0x28 8016da0: af00 add r7, sp, #0 8016da2: 60f8 str r0, [r7, #12] 8016da4: 60b9 str r1, [r7, #8] 8016da6: 603b str r3, [r7, #0] 8016da8: 4613 mov r3, r2 8016daa: 71fb strb r3, [r7, #7] TCB_t * pxTCB; BaseType_t xReturn = pdPASS; 8016dac: 2301 movs r3, #1 8016dae: 627b str r3, [r7, #36] @ 0x24 uint8_t ucOriginalNotifyState; configASSERT( xTaskToNotify ); 8016db0: 68fb ldr r3, [r7, #12] 8016db2: 2b00 cmp r3, #0 8016db4: d10b bne.n 8016dce __asm volatile 8016db6: f04f 0350 mov.w r3, #80 @ 0x50 8016dba: f383 8811 msr BASEPRI, r3 8016dbe: f3bf 8f6f isb sy 8016dc2: f3bf 8f4f dsb sy 8016dc6: 61bb str r3, [r7, #24] } 8016dc8: bf00 nop 8016dca: bf00 nop 8016dcc: e7fd b.n 8016dca pxTCB = xTaskToNotify; 8016dce: 68fb ldr r3, [r7, #12] 8016dd0: 623b str r3, [r7, #32] taskENTER_CRITICAL(); 8016dd2: f000 ff79 bl 8017cc8 { if( pulPreviousNotificationValue != NULL ) 8016dd6: 683b ldr r3, [r7, #0] 8016dd8: 2b00 cmp r3, #0 8016dda: d004 beq.n 8016de6 { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 8016ddc: 6a3b ldr r3, [r7, #32] 8016dde: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016de2: 683b ldr r3, [r7, #0] 8016de4: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 8016de6: 6a3b ldr r3, [r7, #32] 8016de8: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016dec: 77fb strb r3, [r7, #31] pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 8016dee: 6a3b ldr r3, [r7, #32] 8016df0: 2202 movs r2, #2 8016df2: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 8016df6: 79fb ldrb r3, [r7, #7] 8016df8: 2b04 cmp r3, #4 8016dfa: d82e bhi.n 8016e5a 8016dfc: a201 add r2, pc, #4 @ (adr r2, 8016e04 ) 8016dfe: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016e02: bf00 nop 8016e04: 08016e7f .word 0x08016e7f 8016e08: 08016e19 .word 0x08016e19 8016e0c: 08016e2b .word 0x08016e2b 8016e10: 08016e3b .word 0x08016e3b 8016e14: 08016e45 .word 0x08016e45 { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 8016e18: 6a3b ldr r3, [r7, #32] 8016e1a: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016e1e: 68bb ldr r3, [r7, #8] 8016e20: 431a orrs r2, r3 8016e22: 6a3b ldr r3, [r7, #32] 8016e24: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016e28: e02c b.n 8016e84 case eIncrement : ( pxTCB->ulNotifiedValue )++; 8016e2a: 6a3b ldr r3, [r7, #32] 8016e2c: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016e30: 1c5a adds r2, r3, #1 8016e32: 6a3b ldr r3, [r7, #32] 8016e34: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016e38: e024 b.n 8016e84 case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 8016e3a: 6a3b ldr r3, [r7, #32] 8016e3c: 68ba ldr r2, [r7, #8] 8016e3e: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016e42: e01f b.n 8016e84 case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 8016e44: 7ffb ldrb r3, [r7, #31] 8016e46: 2b02 cmp r3, #2 8016e48: d004 beq.n 8016e54 { pxTCB->ulNotifiedValue = ulValue; 8016e4a: 6a3b ldr r3, [r7, #32] 8016e4c: 68ba ldr r2, [r7, #8] 8016e4e: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 8016e52: e017 b.n 8016e84 xReturn = pdFAIL; 8016e54: 2300 movs r3, #0 8016e56: 627b str r3, [r7, #36] @ 0x24 break; 8016e58: e014 b.n 8016e84 default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 8016e5a: 6a3b ldr r3, [r7, #32] 8016e5c: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016e60: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8016e64: d00d beq.n 8016e82 __asm volatile 8016e66: f04f 0350 mov.w r3, #80 @ 0x50 8016e6a: f383 8811 msr BASEPRI, r3 8016e6e: f3bf 8f6f isb sy 8016e72: f3bf 8f4f dsb sy 8016e76: 617b str r3, [r7, #20] } 8016e78: bf00 nop 8016e7a: bf00 nop 8016e7c: e7fd b.n 8016e7a break; 8016e7e: bf00 nop 8016e80: e000 b.n 8016e84 break; 8016e82: bf00 nop traceTASK_NOTIFY(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 8016e84: 7ffb ldrb r3, [r7, #31] 8016e86: 2b01 cmp r3, #1 8016e88: d13b bne.n 8016f02 { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8016e8a: 6a3b ldr r3, [r7, #32] 8016e8c: 3304 adds r3, #4 8016e8e: 4618 mov r0, r3 8016e90: f7fd fd78 bl 8014984 prvAddTaskToReadyList( pxTCB ); 8016e94: 6a3b ldr r3, [r7, #32] 8016e96: 6ada ldr r2, [r3, #44] @ 0x2c 8016e98: 4b1d ldr r3, [pc, #116] @ (8016f10 ) 8016e9a: 681b ldr r3, [r3, #0] 8016e9c: 429a cmp r2, r3 8016e9e: d903 bls.n 8016ea8 8016ea0: 6a3b ldr r3, [r7, #32] 8016ea2: 6adb ldr r3, [r3, #44] @ 0x2c 8016ea4: 4a1a ldr r2, [pc, #104] @ (8016f10 ) 8016ea6: 6013 str r3, [r2, #0] 8016ea8: 6a3b ldr r3, [r7, #32] 8016eaa: 6ada ldr r2, [r3, #44] @ 0x2c 8016eac: 4613 mov r3, r2 8016eae: 009b lsls r3, r3, #2 8016eb0: 4413 add r3, r2 8016eb2: 009b lsls r3, r3, #2 8016eb4: 4a17 ldr r2, [pc, #92] @ (8016f14 ) 8016eb6: 441a add r2, r3 8016eb8: 6a3b ldr r3, [r7, #32] 8016eba: 3304 adds r3, #4 8016ebc: 4619 mov r1, r3 8016ebe: 4610 mov r0, r2 8016ec0: f7fd fd03 bl 80148ca /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 8016ec4: 6a3b ldr r3, [r7, #32] 8016ec6: 6a9b ldr r3, [r3, #40] @ 0x28 8016ec8: 2b00 cmp r3, #0 8016eca: d00b beq.n 8016ee4 __asm volatile 8016ecc: f04f 0350 mov.w r3, #80 @ 0x50 8016ed0: f383 8811 msr BASEPRI, r3 8016ed4: f3bf 8f6f isb sy 8016ed8: f3bf 8f4f dsb sy 8016edc: 613b str r3, [r7, #16] } 8016ede: bf00 nop 8016ee0: bf00 nop 8016ee2: e7fd b.n 8016ee0 earliest possible time. */ prvResetNextTaskUnblockTime(); } #endif if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 8016ee4: 6a3b ldr r3, [r7, #32] 8016ee6: 6ada ldr r2, [r3, #44] @ 0x2c 8016ee8: 4b0b ldr r3, [pc, #44] @ (8016f18 ) 8016eea: 681b ldr r3, [r3, #0] 8016eec: 6adb ldr r3, [r3, #44] @ 0x2c 8016eee: 429a cmp r2, r3 8016ef0: d907 bls.n 8016f02 { /* The notified task has a priority above the currently executing task so a yield is required. */ taskYIELD_IF_USING_PREEMPTION(); 8016ef2: 4b0a ldr r3, [pc, #40] @ (8016f1c ) 8016ef4: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016ef8: 601a str r2, [r3, #0] 8016efa: f3bf 8f4f dsb sy 8016efe: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016f02: f000 ff13 bl 8017d2c return xReturn; 8016f06: 6a7b ldr r3, [r7, #36] @ 0x24 } 8016f08: 4618 mov r0, r3 8016f0a: 3728 adds r7, #40 @ 0x28 8016f0c: 46bd mov sp, r7 8016f0e: bd80 pop {r7, pc} 8016f10: 24002ed4 .word 0x24002ed4 8016f14: 240029fc .word 0x240029fc 8016f18: 240029f8 .word 0x240029f8 8016f1c: e000ed04 .word 0xe000ed04 08016f20 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) { 8016f20: b580 push {r7, lr} 8016f22: b08e sub sp, #56 @ 0x38 8016f24: af00 add r7, sp, #0 8016f26: 60f8 str r0, [r7, #12] 8016f28: 60b9 str r1, [r7, #8] 8016f2a: 603b str r3, [r7, #0] 8016f2c: 4613 mov r3, r2 8016f2e: 71fb strb r3, [r7, #7] TCB_t * pxTCB; uint8_t ucOriginalNotifyState; BaseType_t xReturn = pdPASS; 8016f30: 2301 movs r3, #1 8016f32: 637b str r3, [r7, #52] @ 0x34 UBaseType_t uxSavedInterruptStatus; configASSERT( xTaskToNotify ); 8016f34: 68fb ldr r3, [r7, #12] 8016f36: 2b00 cmp r3, #0 8016f38: d10b bne.n 8016f52 __asm volatile 8016f3a: f04f 0350 mov.w r3, #80 @ 0x50 8016f3e: f383 8811 msr BASEPRI, r3 8016f42: f3bf 8f6f isb sy 8016f46: f3bf 8f4f dsb sy 8016f4a: 627b str r3, [r7, #36] @ 0x24 } 8016f4c: bf00 nop 8016f4e: bf00 nop 8016f50: e7fd b.n 8016f4e below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8016f52: f000 ff99 bl 8017e88 pxTCB = xTaskToNotify; 8016f56: 68fb ldr r3, [r7, #12] 8016f58: 633b str r3, [r7, #48] @ 0x30 __asm volatile 8016f5a: f3ef 8211 mrs r2, BASEPRI 8016f5e: f04f 0350 mov.w r3, #80 @ 0x50 8016f62: f383 8811 msr BASEPRI, r3 8016f66: f3bf 8f6f isb sy 8016f6a: f3bf 8f4f dsb sy 8016f6e: 623a str r2, [r7, #32] 8016f70: 61fb str r3, [r7, #28] return ulOriginalBASEPRI; 8016f72: 6a3b ldr r3, [r7, #32] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8016f74: 62fb str r3, [r7, #44] @ 0x2c { if( pulPreviousNotificationValue != NULL ) 8016f76: 683b ldr r3, [r7, #0] 8016f78: 2b00 cmp r3, #0 8016f7a: d004 beq.n 8016f86 { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 8016f7c: 6b3b ldr r3, [r7, #48] @ 0x30 8016f7e: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016f82: 683b ldr r3, [r7, #0] 8016f84: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 8016f86: 6b3b ldr r3, [r7, #48] @ 0x30 8016f88: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016f8c: f887 302b strb.w r3, [r7, #43] @ 0x2b pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 8016f90: 6b3b ldr r3, [r7, #48] @ 0x30 8016f92: 2202 movs r2, #2 8016f94: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 8016f98: 79fb ldrb r3, [r7, #7] 8016f9a: 2b04 cmp r3, #4 8016f9c: d82e bhi.n 8016ffc 8016f9e: a201 add r2, pc, #4 @ (adr r2, 8016fa4 ) 8016fa0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016fa4: 08017021 .word 0x08017021 8016fa8: 08016fb9 .word 0x08016fb9 8016fac: 08016fcb .word 0x08016fcb 8016fb0: 08016fdb .word 0x08016fdb 8016fb4: 08016fe5 .word 0x08016fe5 { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 8016fb8: 6b3b ldr r3, [r7, #48] @ 0x30 8016fba: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016fbe: 68bb ldr r3, [r7, #8] 8016fc0: 431a orrs r2, r3 8016fc2: 6b3b ldr r3, [r7, #48] @ 0x30 8016fc4: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016fc8: e02d b.n 8017026 case eIncrement : ( pxTCB->ulNotifiedValue )++; 8016fca: 6b3b ldr r3, [r7, #48] @ 0x30 8016fcc: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016fd0: 1c5a adds r2, r3, #1 8016fd2: 6b3b ldr r3, [r7, #48] @ 0x30 8016fd4: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016fd8: e025 b.n 8017026 case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 8016fda: 6b3b ldr r3, [r7, #48] @ 0x30 8016fdc: 68ba ldr r2, [r7, #8] 8016fde: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016fe2: e020 b.n 8017026 case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 8016fe4: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8016fe8: 2b02 cmp r3, #2 8016fea: d004 beq.n 8016ff6 { pxTCB->ulNotifiedValue = ulValue; 8016fec: 6b3b ldr r3, [r7, #48] @ 0x30 8016fee: 68ba ldr r2, [r7, #8] 8016ff0: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 8016ff4: e017 b.n 8017026 xReturn = pdFAIL; 8016ff6: 2300 movs r3, #0 8016ff8: 637b str r3, [r7, #52] @ 0x34 break; 8016ffa: e014 b.n 8017026 default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 8016ffc: 6b3b ldr r3, [r7, #48] @ 0x30 8016ffe: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8017002: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8017006: d00d beq.n 8017024 __asm volatile 8017008: f04f 0350 mov.w r3, #80 @ 0x50 801700c: f383 8811 msr BASEPRI, r3 8017010: f3bf 8f6f isb sy 8017014: f3bf 8f4f dsb sy 8017018: 61bb str r3, [r7, #24] } 801701a: bf00 nop 801701c: bf00 nop 801701e: e7fd b.n 801701c break; 8017020: bf00 nop 8017022: e000 b.n 8017026 break; 8017024: bf00 nop traceTASK_NOTIFY_FROM_ISR(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 8017026: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 801702a: 2b01 cmp r3, #1 801702c: d147 bne.n 80170be { /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 801702e: 6b3b ldr r3, [r7, #48] @ 0x30 8017030: 6a9b ldr r3, [r3, #40] @ 0x28 8017032: 2b00 cmp r3, #0 8017034: d00b beq.n 801704e __asm volatile 8017036: f04f 0350 mov.w r3, #80 @ 0x50 801703a: f383 8811 msr BASEPRI, r3 801703e: f3bf 8f6f isb sy 8017042: f3bf 8f4f dsb sy 8017046: 617b str r3, [r7, #20] } 8017048: bf00 nop 801704a: bf00 nop 801704c: e7fd b.n 801704a if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 801704e: 4b21 ldr r3, [pc, #132] @ (80170d4 ) 8017050: 681b ldr r3, [r3, #0] 8017052: 2b00 cmp r3, #0 8017054: d11d bne.n 8017092 { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8017056: 6b3b ldr r3, [r7, #48] @ 0x30 8017058: 3304 adds r3, #4 801705a: 4618 mov r0, r3 801705c: f7fd fc92 bl 8014984 prvAddTaskToReadyList( pxTCB ); 8017060: 6b3b ldr r3, [r7, #48] @ 0x30 8017062: 6ada ldr r2, [r3, #44] @ 0x2c 8017064: 4b1c ldr r3, [pc, #112] @ (80170d8 ) 8017066: 681b ldr r3, [r3, #0] 8017068: 429a cmp r2, r3 801706a: d903 bls.n 8017074 801706c: 6b3b ldr r3, [r7, #48] @ 0x30 801706e: 6adb ldr r3, [r3, #44] @ 0x2c 8017070: 4a19 ldr r2, [pc, #100] @ (80170d8 ) 8017072: 6013 str r3, [r2, #0] 8017074: 6b3b ldr r3, [r7, #48] @ 0x30 8017076: 6ada ldr r2, [r3, #44] @ 0x2c 8017078: 4613 mov r3, r2 801707a: 009b lsls r3, r3, #2 801707c: 4413 add r3, r2 801707e: 009b lsls r3, r3, #2 8017080: 4a16 ldr r2, [pc, #88] @ (80170dc ) 8017082: 441a add r2, r3 8017084: 6b3b ldr r3, [r7, #48] @ 0x30 8017086: 3304 adds r3, #4 8017088: 4619 mov r1, r3 801708a: 4610 mov r0, r2 801708c: f7fd fc1d bl 80148ca 8017090: e005 b.n 801709e } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); 8017092: 6b3b ldr r3, [r7, #48] @ 0x30 8017094: 3318 adds r3, #24 8017096: 4619 mov r1, r3 8017098: 4811 ldr r0, [pc, #68] @ (80170e0 ) 801709a: f7fd fc16 bl 80148ca } if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 801709e: 6b3b ldr r3, [r7, #48] @ 0x30 80170a0: 6ada ldr r2, [r3, #44] @ 0x2c 80170a2: 4b10 ldr r3, [pc, #64] @ (80170e4 ) 80170a4: 681b ldr r3, [r3, #0] 80170a6: 6adb ldr r3, [r3, #44] @ 0x2c 80170a8: 429a cmp r2, r3 80170aa: d908 bls.n 80170be { /* The notified task has a priority above the currently executing task so a yield is required. */ if( pxHigherPriorityTaskWoken != NULL ) 80170ac: 6c3b ldr r3, [r7, #64] @ 0x40 80170ae: 2b00 cmp r3, #0 80170b0: d002 beq.n 80170b8 { *pxHigherPriorityTaskWoken = pdTRUE; 80170b2: 6c3b ldr r3, [r7, #64] @ 0x40 80170b4: 2201 movs r2, #1 80170b6: 601a str r2, [r3, #0] } /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 80170b8: 4b0b ldr r3, [pc, #44] @ (80170e8 ) 80170ba: 2201 movs r2, #1 80170bc: 601a str r2, [r3, #0] 80170be: 6afb ldr r3, [r7, #44] @ 0x2c 80170c0: 613b str r3, [r7, #16] __asm volatile 80170c2: 693b ldr r3, [r7, #16] 80170c4: f383 8811 msr BASEPRI, r3 } 80170c8: bf00 nop } } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 80170ca: 6b7b ldr r3, [r7, #52] @ 0x34 } 80170cc: 4618 mov r0, r3 80170ce: 3738 adds r7, #56 @ 0x38 80170d0: 46bd mov sp, r7 80170d2: bd80 pop {r7, pc} 80170d4: 24002ef4 .word 0x24002ef4 80170d8: 24002ed4 .word 0x24002ed4 80170dc: 240029fc .word 0x240029fc 80170e0: 24002e8c .word 0x24002e8c 80170e4: 240029f8 .word 0x240029f8 80170e8: 24002ee0 .word 0x24002ee0 080170ec : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask ) { 80170ec: b580 push {r7, lr} 80170ee: b084 sub sp, #16 80170f0: af00 add r7, sp, #0 80170f2: 6078 str r0, [r7, #4] TCB_t *pxTCB; BaseType_t xReturn; /* If null is passed in here then it is the calling task that is having its notification state cleared. */ pxTCB = prvGetTCBFromHandle( xTask ); 80170f4: 687b ldr r3, [r7, #4] 80170f6: 2b00 cmp r3, #0 80170f8: d102 bne.n 8017100 80170fa: 4b0e ldr r3, [pc, #56] @ (8017134 ) 80170fc: 681b ldr r3, [r3, #0] 80170fe: e000 b.n 8017102 8017100: 687b ldr r3, [r7, #4] 8017102: 60bb str r3, [r7, #8] taskENTER_CRITICAL(); 8017104: f000 fde0 bl 8017cc8 { if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED ) 8017108: 68bb ldr r3, [r7, #8] 801710a: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 801710e: b2db uxtb r3, r3 8017110: 2b02 cmp r3, #2 8017112: d106 bne.n 8017122 { pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8017114: 68bb ldr r3, [r7, #8] 8017116: 2200 movs r2, #0 8017118: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 xReturn = pdPASS; 801711c: 2301 movs r3, #1 801711e: 60fb str r3, [r7, #12] 8017120: e001 b.n 8017126 } else { xReturn = pdFAIL; 8017122: 2300 movs r3, #0 8017124: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8017126: f000 fe01 bl 8017d2c return xReturn; 801712a: 68fb ldr r3, [r7, #12] } 801712c: 4618 mov r0, r3 801712e: 3710 adds r7, #16 8017130: 46bd mov sp, r7 8017132: bd80 pop {r7, pc} 8017134: 240029f8 .word 0x240029f8 08017138 : #endif /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { 8017138: b580 push {r7, lr} 801713a: b084 sub sp, #16 801713c: af00 add r7, sp, #0 801713e: 6078 str r0, [r7, #4] 8017140: 6039 str r1, [r7, #0] TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; 8017142: 4b21 ldr r3, [pc, #132] @ (80171c8 ) 8017144: 681b ldr r3, [r3, #0] 8017146: 60fb str r3, [r7, #12] } #endif /* Remove the task from the ready list before adding it to the blocked list as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8017148: 4b20 ldr r3, [pc, #128] @ (80171cc ) 801714a: 681b ldr r3, [r3, #0] 801714c: 3304 adds r3, #4 801714e: 4618 mov r0, r3 8017150: f7fd fc18 bl 8014984 mtCOVERAGE_TEST_MARKER(); } #if ( INCLUDE_vTaskSuspend == 1 ) { if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) 8017154: 687b ldr r3, [r7, #4] 8017156: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801715a: d10a bne.n 8017172 801715c: 683b ldr r3, [r7, #0] 801715e: 2b00 cmp r3, #0 8017160: d007 beq.n 8017172 { /* Add the task to the suspended task list instead of a delayed task list to ensure it is not woken by a timing event. It will block indefinitely. */ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8017162: 4b1a ldr r3, [pc, #104] @ (80171cc ) 8017164: 681b ldr r3, [r3, #0] 8017166: 3304 adds r3, #4 8017168: 4619 mov r1, r3 801716a: 4819 ldr r0, [pc, #100] @ (80171d0 ) 801716c: f7fd fbad bl 80148ca /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } 8017170: e026 b.n 80171c0 xTimeToWake = xConstTickCount + xTicksToWait; 8017172: 68fa ldr r2, [r7, #12] 8017174: 687b ldr r3, [r7, #4] 8017176: 4413 add r3, r2 8017178: 60bb str r3, [r7, #8] listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 801717a: 4b14 ldr r3, [pc, #80] @ (80171cc ) 801717c: 681b ldr r3, [r3, #0] 801717e: 68ba ldr r2, [r7, #8] 8017180: 605a str r2, [r3, #4] if( xTimeToWake < xConstTickCount ) 8017182: 68ba ldr r2, [r7, #8] 8017184: 68fb ldr r3, [r7, #12] 8017186: 429a cmp r2, r3 8017188: d209 bcs.n 801719e vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 801718a: 4b12 ldr r3, [pc, #72] @ (80171d4 ) 801718c: 681a ldr r2, [r3, #0] 801718e: 4b0f ldr r3, [pc, #60] @ (80171cc ) 8017190: 681b ldr r3, [r3, #0] 8017192: 3304 adds r3, #4 8017194: 4619 mov r1, r3 8017196: 4610 mov r0, r2 8017198: f7fd fbbb bl 8014912 } 801719c: e010 b.n 80171c0 vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 801719e: 4b0e ldr r3, [pc, #56] @ (80171d8 ) 80171a0: 681a ldr r2, [r3, #0] 80171a2: 4b0a ldr r3, [pc, #40] @ (80171cc ) 80171a4: 681b ldr r3, [r3, #0] 80171a6: 3304 adds r3, #4 80171a8: 4619 mov r1, r3 80171aa: 4610 mov r0, r2 80171ac: f7fd fbb1 bl 8014912 if( xTimeToWake < xNextTaskUnblockTime ) 80171b0: 4b0a ldr r3, [pc, #40] @ (80171dc ) 80171b2: 681b ldr r3, [r3, #0] 80171b4: 68ba ldr r2, [r7, #8] 80171b6: 429a cmp r2, r3 80171b8: d202 bcs.n 80171c0 xNextTaskUnblockTime = xTimeToWake; 80171ba: 4a08 ldr r2, [pc, #32] @ (80171dc ) 80171bc: 68bb ldr r3, [r7, #8] 80171be: 6013 str r3, [r2, #0] } 80171c0: bf00 nop 80171c2: 3710 adds r7, #16 80171c4: 46bd mov sp, r7 80171c6: bd80 pop {r7, pc} 80171c8: 24002ed0 .word 0x24002ed0 80171cc: 240029f8 .word 0x240029f8 80171d0: 24002eb8 .word 0x24002eb8 80171d4: 24002e88 .word 0x24002e88 80171d8: 24002e84 .word 0x24002e84 80171dc: 24002eec .word 0x24002eec 080171e0 : TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ BaseType_t xTimerCreateTimerTask( void ) { 80171e0: b580 push {r7, lr} 80171e2: b08a sub sp, #40 @ 0x28 80171e4: af04 add r7, sp, #16 BaseType_t xReturn = pdFAIL; 80171e6: 2300 movs r3, #0 80171e8: 617b str r3, [r7, #20] /* This function is called when the scheduler is started if configUSE_TIMERS is set to 1. Check that the infrastructure used by the timer service task has been created/initialised. If timers have already been created then the initialisation will already have been performed. */ prvCheckForValidListAndQueue(); 80171ea: f000 fbb1 bl 8017950 if( xTimerQueue != NULL ) 80171ee: 4b1d ldr r3, [pc, #116] @ (8017264 ) 80171f0: 681b ldr r3, [r3, #0] 80171f2: 2b00 cmp r3, #0 80171f4: d021 beq.n 801723a { #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxTimerTaskTCBBuffer = NULL; 80171f6: 2300 movs r3, #0 80171f8: 60fb str r3, [r7, #12] StackType_t *pxTimerTaskStackBuffer = NULL; 80171fa: 2300 movs r3, #0 80171fc: 60bb str r3, [r7, #8] uint32_t ulTimerTaskStackSize; vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); 80171fe: 1d3a adds r2, r7, #4 8017200: f107 0108 add.w r1, r7, #8 8017204: f107 030c add.w r3, r7, #12 8017208: 4618 mov r0, r3 801720a: f7fd fb17 bl 801483c xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, 801720e: 6879 ldr r1, [r7, #4] 8017210: 68bb ldr r3, [r7, #8] 8017212: 68fa ldr r2, [r7, #12] 8017214: 9202 str r2, [sp, #8] 8017216: 9301 str r3, [sp, #4] 8017218: 2302 movs r3, #2 801721a: 9300 str r3, [sp, #0] 801721c: 2300 movs r3, #0 801721e: 460a mov r2, r1 8017220: 4911 ldr r1, [pc, #68] @ (8017268 ) 8017222: 4812 ldr r0, [pc, #72] @ (801726c ) 8017224: f7fe fd2f bl 8015c86 8017228: 4603 mov r3, r0 801722a: 4a11 ldr r2, [pc, #68] @ (8017270 ) 801722c: 6013 str r3, [r2, #0] NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, pxTimerTaskStackBuffer, pxTimerTaskTCBBuffer ); if( xTimerTaskHandle != NULL ) 801722e: 4b10 ldr r3, [pc, #64] @ (8017270 ) 8017230: 681b ldr r3, [r3, #0] 8017232: 2b00 cmp r3, #0 8017234: d001 beq.n 801723a { xReturn = pdPASS; 8017236: 2301 movs r3, #1 8017238: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } configASSERT( xReturn ); 801723a: 697b ldr r3, [r7, #20] 801723c: 2b00 cmp r3, #0 801723e: d10b bne.n 8017258 __asm volatile 8017240: f04f 0350 mov.w r3, #80 @ 0x50 8017244: f383 8811 msr BASEPRI, r3 8017248: f3bf 8f6f isb sy 801724c: f3bf 8f4f dsb sy 8017250: 613b str r3, [r7, #16] } 8017252: bf00 nop 8017254: bf00 nop 8017256: e7fd b.n 8017254 return xReturn; 8017258: 697b ldr r3, [r7, #20] } 801725a: 4618 mov r0, r3 801725c: 3718 adds r7, #24 801725e: 46bd mov sp, r7 8017260: bd80 pop {r7, pc} 8017262: bf00 nop 8017264: 24002f28 .word 0x24002f28 8017268: 08018668 .word 0x08018668 801726c: 080174e9 .word 0x080174e9 8017270: 24002f2c .word 0x24002f2c 08017274 : TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) { 8017274: b580 push {r7, lr} 8017276: b088 sub sp, #32 8017278: af02 add r7, sp, #8 801727a: 60f8 str r0, [r7, #12] 801727c: 60b9 str r1, [r7, #8] 801727e: 607a str r2, [r7, #4] 8017280: 603b str r3, [r7, #0] Timer_t *pxNewTimer; pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */ 8017282: 202c movs r0, #44 @ 0x2c 8017284: f000 fe42 bl 8017f0c 8017288: 6178 str r0, [r7, #20] if( pxNewTimer != NULL ) 801728a: 697b ldr r3, [r7, #20] 801728c: 2b00 cmp r3, #0 801728e: d00d beq.n 80172ac { /* Status is thus far zero as the timer is not created statically and has not been started. The auto-reload bit may get set in prvInitialiseNewTimer. */ pxNewTimer->ucStatus = 0x00; 8017290: 697b ldr r3, [r7, #20] 8017292: 2200 movs r2, #0 8017294: f883 2028 strb.w r2, [r3, #40] @ 0x28 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); 8017298: 697b ldr r3, [r7, #20] 801729a: 9301 str r3, [sp, #4] 801729c: 6a3b ldr r3, [r7, #32] 801729e: 9300 str r3, [sp, #0] 80172a0: 683b ldr r3, [r7, #0] 80172a2: 687a ldr r2, [r7, #4] 80172a4: 68b9 ldr r1, [r7, #8] 80172a6: 68f8 ldr r0, [r7, #12] 80172a8: f000 f845 bl 8017336 } return pxNewTimer; 80172ac: 697b ldr r3, [r7, #20] } 80172ae: 4618 mov r0, r3 80172b0: 3718 adds r7, #24 80172b2: 46bd mov sp, r7 80172b4: bd80 pop {r7, pc} 080172b6 : const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) { 80172b6: b580 push {r7, lr} 80172b8: b08a sub sp, #40 @ 0x28 80172ba: af02 add r7, sp, #8 80172bc: 60f8 str r0, [r7, #12] 80172be: 60b9 str r1, [r7, #8] 80172c0: 607a str r2, [r7, #4] 80172c2: 603b str r3, [r7, #0] #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTimer_t equals the size of the real timer structure. */ volatile size_t xSize = sizeof( StaticTimer_t ); 80172c4: 232c movs r3, #44 @ 0x2c 80172c6: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( Timer_t ) ); 80172c8: 693b ldr r3, [r7, #16] 80172ca: 2b2c cmp r3, #44 @ 0x2c 80172cc: d00b beq.n 80172e6 __asm volatile 80172ce: f04f 0350 mov.w r3, #80 @ 0x50 80172d2: f383 8811 msr BASEPRI, r3 80172d6: f3bf 8f6f isb sy 80172da: f3bf 8f4f dsb sy 80172de: 61bb str r3, [r7, #24] } 80172e0: bf00 nop 80172e2: bf00 nop 80172e4: e7fd b.n 80172e2 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 80172e6: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ /* A pointer to a StaticTimer_t structure MUST be provided, use it. */ configASSERT( pxTimerBuffer ); 80172e8: 6afb ldr r3, [r7, #44] @ 0x2c 80172ea: 2b00 cmp r3, #0 80172ec: d10b bne.n 8017306 __asm volatile 80172ee: f04f 0350 mov.w r3, #80 @ 0x50 80172f2: f383 8811 msr BASEPRI, r3 80172f6: f3bf 8f6f isb sy 80172fa: f3bf 8f4f dsb sy 80172fe: 617b str r3, [r7, #20] } 8017300: bf00 nop 8017302: bf00 nop 8017304: e7fd b.n 8017302 pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */ 8017306: 6afb ldr r3, [r7, #44] @ 0x2c 8017308: 61fb str r3, [r7, #28] if( pxNewTimer != NULL ) 801730a: 69fb ldr r3, [r7, #28] 801730c: 2b00 cmp r3, #0 801730e: d00d beq.n 801732c { /* Timers can be created statically or dynamically so note this timer was created statically in case it is later deleted. The auto-reload bit may get set in prvInitialiseNewTimer(). */ pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED; 8017310: 69fb ldr r3, [r7, #28] 8017312: 2202 movs r2, #2 8017314: f883 2028 strb.w r2, [r3, #40] @ 0x28 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); 8017318: 69fb ldr r3, [r7, #28] 801731a: 9301 str r3, [sp, #4] 801731c: 6abb ldr r3, [r7, #40] @ 0x28 801731e: 9300 str r3, [sp, #0] 8017320: 683b ldr r3, [r7, #0] 8017322: 687a ldr r2, [r7, #4] 8017324: 68b9 ldr r1, [r7, #8] 8017326: 68f8 ldr r0, [r7, #12] 8017328: f000 f805 bl 8017336 } return pxNewTimer; 801732c: 69fb ldr r3, [r7, #28] } 801732e: 4618 mov r0, r3 8017330: 3720 adds r7, #32 8017332: 46bd mov sp, r7 8017334: bd80 pop {r7, pc} 08017336 : const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) { 8017336: b580 push {r7, lr} 8017338: b086 sub sp, #24 801733a: af00 add r7, sp, #0 801733c: 60f8 str r0, [r7, #12] 801733e: 60b9 str r1, [r7, #8] 8017340: 607a str r2, [r7, #4] 8017342: 603b str r3, [r7, #0] /* 0 is not a valid value for xTimerPeriodInTicks. */ configASSERT( ( xTimerPeriodInTicks > 0 ) ); 8017344: 68bb ldr r3, [r7, #8] 8017346: 2b00 cmp r3, #0 8017348: d10b bne.n 8017362 __asm volatile 801734a: f04f 0350 mov.w r3, #80 @ 0x50 801734e: f383 8811 msr BASEPRI, r3 8017352: f3bf 8f6f isb sy 8017356: f3bf 8f4f dsb sy 801735a: 617b str r3, [r7, #20] } 801735c: bf00 nop 801735e: bf00 nop 8017360: e7fd b.n 801735e if( pxNewTimer != NULL ) 8017362: 6a7b ldr r3, [r7, #36] @ 0x24 8017364: 2b00 cmp r3, #0 8017366: d01e beq.n 80173a6 { /* Ensure the infrastructure used by the timer service task has been created/initialised. */ prvCheckForValidListAndQueue(); 8017368: f000 faf2 bl 8017950 /* Initialise the timer structure members using the function parameters. */ pxNewTimer->pcTimerName = pcTimerName; 801736c: 6a7b ldr r3, [r7, #36] @ 0x24 801736e: 68fa ldr r2, [r7, #12] 8017370: 601a str r2, [r3, #0] pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks; 8017372: 6a7b ldr r3, [r7, #36] @ 0x24 8017374: 68ba ldr r2, [r7, #8] 8017376: 619a str r2, [r3, #24] pxNewTimer->pvTimerID = pvTimerID; 8017378: 6a7b ldr r3, [r7, #36] @ 0x24 801737a: 683a ldr r2, [r7, #0] 801737c: 61da str r2, [r3, #28] pxNewTimer->pxCallbackFunction = pxCallbackFunction; 801737e: 6a7b ldr r3, [r7, #36] @ 0x24 8017380: 6a3a ldr r2, [r7, #32] 8017382: 621a str r2, [r3, #32] vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); 8017384: 6a7b ldr r3, [r7, #36] @ 0x24 8017386: 3304 adds r3, #4 8017388: 4618 mov r0, r3 801738a: f7fd fa91 bl 80148b0 if( uxAutoReload != pdFALSE ) 801738e: 687b ldr r3, [r7, #4] 8017390: 2b00 cmp r3, #0 8017392: d008 beq.n 80173a6 { pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; 8017394: 6a7b ldr r3, [r7, #36] @ 0x24 8017396: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 801739a: f043 0304 orr.w r3, r3, #4 801739e: b2da uxtb r2, r3 80173a0: 6a7b ldr r3, [r7, #36] @ 0x24 80173a2: f883 2028 strb.w r2, [r3, #40] @ 0x28 } traceTIMER_CREATE( pxNewTimer ); } } 80173a6: bf00 nop 80173a8: 3718 adds r7, #24 80173aa: 46bd mov sp, r7 80173ac: bd80 pop {r7, pc} ... 080173b0 : /*-----------------------------------------------------------*/ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) { 80173b0: b580 push {r7, lr} 80173b2: b08a sub sp, #40 @ 0x28 80173b4: af00 add r7, sp, #0 80173b6: 60f8 str r0, [r7, #12] 80173b8: 60b9 str r1, [r7, #8] 80173ba: 607a str r2, [r7, #4] 80173bc: 603b str r3, [r7, #0] BaseType_t xReturn = pdFAIL; 80173be: 2300 movs r3, #0 80173c0: 627b str r3, [r7, #36] @ 0x24 DaemonTaskMessage_t xMessage; configASSERT( xTimer ); 80173c2: 68fb ldr r3, [r7, #12] 80173c4: 2b00 cmp r3, #0 80173c6: d10b bne.n 80173e0 __asm volatile 80173c8: f04f 0350 mov.w r3, #80 @ 0x50 80173cc: f383 8811 msr BASEPRI, r3 80173d0: f3bf 8f6f isb sy 80173d4: f3bf 8f4f dsb sy 80173d8: 623b str r3, [r7, #32] } 80173da: bf00 nop 80173dc: bf00 nop 80173de: e7fd b.n 80173dc /* Send a message to the timer service task to perform a particular action on a particular timer definition. */ if( xTimerQueue != NULL ) 80173e0: 4b19 ldr r3, [pc, #100] @ (8017448 ) 80173e2: 681b ldr r3, [r3, #0] 80173e4: 2b00 cmp r3, #0 80173e6: d02a beq.n 801743e { /* Send a command to the timer service task to start the xTimer timer. */ xMessage.xMessageID = xCommandID; 80173e8: 68bb ldr r3, [r7, #8] 80173ea: 613b str r3, [r7, #16] xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; 80173ec: 687b ldr r3, [r7, #4] 80173ee: 617b str r3, [r7, #20] xMessage.u.xTimerParameters.pxTimer = xTimer; 80173f0: 68fb ldr r3, [r7, #12] 80173f2: 61bb str r3, [r7, #24] if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) 80173f4: 68bb ldr r3, [r7, #8] 80173f6: 2b05 cmp r3, #5 80173f8: dc18 bgt.n 801742c { if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) 80173fa: f7ff fae1 bl 80169c0 80173fe: 4603 mov r3, r0 8017400: 2b02 cmp r3, #2 8017402: d109 bne.n 8017418 { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); 8017404: 4b10 ldr r3, [pc, #64] @ (8017448 ) 8017406: 6818 ldr r0, [r3, #0] 8017408: f107 0110 add.w r1, r7, #16 801740c: 2300 movs r3, #0 801740e: 6b3a ldr r2, [r7, #48] @ 0x30 8017410: f7fd fce0 bl 8014dd4 8017414: 6278 str r0, [r7, #36] @ 0x24 8017416: e012 b.n 801743e } else { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); 8017418: 4b0b ldr r3, [pc, #44] @ (8017448 ) 801741a: 6818 ldr r0, [r3, #0] 801741c: f107 0110 add.w r1, r7, #16 8017420: 2300 movs r3, #0 8017422: 2200 movs r2, #0 8017424: f7fd fcd6 bl 8014dd4 8017428: 6278 str r0, [r7, #36] @ 0x24 801742a: e008 b.n 801743e } } else { xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); 801742c: 4b06 ldr r3, [pc, #24] @ (8017448 ) 801742e: 6818 ldr r0, [r3, #0] 8017430: f107 0110 add.w r1, r7, #16 8017434: 2300 movs r3, #0 8017436: 683a ldr r2, [r7, #0] 8017438: f7fd fdce bl 8014fd8 801743c: 6278 str r0, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 801743e: 6a7b ldr r3, [r7, #36] @ 0x24 } 8017440: 4618 mov r0, r3 8017442: 3728 adds r7, #40 @ 0x28 8017444: 46bd mov sp, r7 8017446: bd80 pop {r7, pc} 8017448: 24002f28 .word 0x24002f28 0801744c : return pxTimer->pcTimerName; } /*-----------------------------------------------------------*/ static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) { 801744c: b580 push {r7, lr} 801744e: b088 sub sp, #32 8017450: af02 add r7, sp, #8 8017452: 6078 str r0, [r7, #4] 8017454: 6039 str r1, [r7, #0] BaseType_t xResult; Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8017456: 4b23 ldr r3, [pc, #140] @ (80174e4 ) 8017458: 681b ldr r3, [r3, #0] 801745a: 68db ldr r3, [r3, #12] 801745c: 68db ldr r3, [r3, #12] 801745e: 617b str r3, [r7, #20] /* Remove the timer from the list of active timers. A check has already been performed to ensure the list is not empty. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8017460: 697b ldr r3, [r7, #20] 8017462: 3304 adds r3, #4 8017464: 4618 mov r0, r3 8017466: f7fd fa8d bl 8014984 traceTIMER_EXPIRED( pxTimer ); /* If the timer is an auto-reload timer then calculate the next expiry time and re-insert the timer in the list of active timers. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 801746a: 697b ldr r3, [r7, #20] 801746c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017470: f003 0304 and.w r3, r3, #4 8017474: 2b00 cmp r3, #0 8017476: d023 beq.n 80174c0 { /* The timer is inserted into a list using a time relative to anything other than the current time. It will therefore be inserted into the correct list relative to the time this task thinks it is now. */ if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) 8017478: 697b ldr r3, [r7, #20] 801747a: 699a ldr r2, [r3, #24] 801747c: 687b ldr r3, [r7, #4] 801747e: 18d1 adds r1, r2, r3 8017480: 687b ldr r3, [r7, #4] 8017482: 683a ldr r2, [r7, #0] 8017484: 6978 ldr r0, [r7, #20] 8017486: f000 f8d5 bl 8017634 801748a: 4603 mov r3, r0 801748c: 2b00 cmp r3, #0 801748e: d020 beq.n 80174d2 { /* The timer expired before it was added to the active timer list. Reload it now. */ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 8017490: 2300 movs r3, #0 8017492: 9300 str r3, [sp, #0] 8017494: 2300 movs r3, #0 8017496: 687a ldr r2, [r7, #4] 8017498: 2100 movs r1, #0 801749a: 6978 ldr r0, [r7, #20] 801749c: f7ff ff88 bl 80173b0 80174a0: 6138 str r0, [r7, #16] configASSERT( xResult ); 80174a2: 693b ldr r3, [r7, #16] 80174a4: 2b00 cmp r3, #0 80174a6: d114 bne.n 80174d2 __asm volatile 80174a8: f04f 0350 mov.w r3, #80 @ 0x50 80174ac: f383 8811 msr BASEPRI, r3 80174b0: f3bf 8f6f isb sy 80174b4: f3bf 8f4f dsb sy 80174b8: 60fb str r3, [r7, #12] } 80174ba: bf00 nop 80174bc: bf00 nop 80174be: e7fd b.n 80174bc mtCOVERAGE_TEST_MARKER(); } } else { pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 80174c0: 697b ldr r3, [r7, #20] 80174c2: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80174c6: f023 0301 bic.w r3, r3, #1 80174ca: b2da uxtb r2, r3 80174cc: 697b ldr r3, [r7, #20] 80174ce: f883 2028 strb.w r2, [r3, #40] @ 0x28 mtCOVERAGE_TEST_MARKER(); } /* Call the timer callback. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 80174d2: 697b ldr r3, [r7, #20] 80174d4: 6a1b ldr r3, [r3, #32] 80174d6: 6978 ldr r0, [r7, #20] 80174d8: 4798 blx r3 } 80174da: bf00 nop 80174dc: 3718 adds r7, #24 80174de: 46bd mov sp, r7 80174e0: bd80 pop {r7, pc} 80174e2: bf00 nop 80174e4: 24002f20 .word 0x24002f20 080174e8 : /*-----------------------------------------------------------*/ static portTASK_FUNCTION( prvTimerTask, pvParameters ) { 80174e8: b580 push {r7, lr} 80174ea: b084 sub sp, #16 80174ec: af00 add r7, sp, #0 80174ee: 6078 str r0, [r7, #4] for( ;; ) { /* Query the timers list to see if it contains any timers, and if so, obtain the time at which the next timer will expire. */ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 80174f0: f107 0308 add.w r3, r7, #8 80174f4: 4618 mov r0, r3 80174f6: f000 f859 bl 80175ac 80174fa: 60f8 str r0, [r7, #12] /* If a timer has expired, process it. Otherwise, block this task until either a timer does expire, or a command is received. */ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); 80174fc: 68bb ldr r3, [r7, #8] 80174fe: 4619 mov r1, r3 8017500: 68f8 ldr r0, [r7, #12] 8017502: f000 f805 bl 8017510 /* Empty the command queue. */ prvProcessReceivedCommands(); 8017506: f000 f8d7 bl 80176b8 xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 801750a: bf00 nop 801750c: e7f0 b.n 80174f0 ... 08017510 : } } /*-----------------------------------------------------------*/ static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) { 8017510: b580 push {r7, lr} 8017512: b084 sub sp, #16 8017514: af00 add r7, sp, #0 8017516: 6078 str r0, [r7, #4] 8017518: 6039 str r1, [r7, #0] TickType_t xTimeNow; BaseType_t xTimerListsWereSwitched; vTaskSuspendAll(); 801751a: f7fe fe17 bl 801614c /* Obtain the time now to make an assessment as to whether the timer has expired or not. If obtaining the time causes the lists to switch then don't process this timer as any timers that remained in the list when the lists were switched will have been processed within the prvSampleTimeNow() function. */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 801751e: f107 0308 add.w r3, r7, #8 8017522: 4618 mov r0, r3 8017524: f000 f866 bl 80175f4 8017528: 60f8 str r0, [r7, #12] if( xTimerListsWereSwitched == pdFALSE ) 801752a: 68bb ldr r3, [r7, #8] 801752c: 2b00 cmp r3, #0 801752e: d130 bne.n 8017592 { /* The tick count has not overflowed, has the timer expired? */ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) 8017530: 683b ldr r3, [r7, #0] 8017532: 2b00 cmp r3, #0 8017534: d10a bne.n 801754c 8017536: 687a ldr r2, [r7, #4] 8017538: 68fb ldr r3, [r7, #12] 801753a: 429a cmp r2, r3 801753c: d806 bhi.n 801754c { ( void ) xTaskResumeAll(); 801753e: f7fe fe13 bl 8016168 prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); 8017542: 68f9 ldr r1, [r7, #12] 8017544: 6878 ldr r0, [r7, #4] 8017546: f7ff ff81 bl 801744c else { ( void ) xTaskResumeAll(); } } } 801754a: e024 b.n 8017596 if( xListWasEmpty != pdFALSE ) 801754c: 683b ldr r3, [r7, #0] 801754e: 2b00 cmp r3, #0 8017550: d008 beq.n 8017564 xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); 8017552: 4b13 ldr r3, [pc, #76] @ (80175a0 ) 8017554: 681b ldr r3, [r3, #0] 8017556: 681b ldr r3, [r3, #0] 8017558: 2b00 cmp r3, #0 801755a: d101 bne.n 8017560 801755c: 2301 movs r3, #1 801755e: e000 b.n 8017562 8017560: 2300 movs r3, #0 8017562: 603b str r3, [r7, #0] vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); 8017564: 4b0f ldr r3, [pc, #60] @ (80175a4 ) 8017566: 6818 ldr r0, [r3, #0] 8017568: 687a ldr r2, [r7, #4] 801756a: 68fb ldr r3, [r7, #12] 801756c: 1ad3 subs r3, r2, r3 801756e: 683a ldr r2, [r7, #0] 8017570: 4619 mov r1, r3 8017572: f7fe f995 bl 80158a0 if( xTaskResumeAll() == pdFALSE ) 8017576: f7fe fdf7 bl 8016168 801757a: 4603 mov r3, r0 801757c: 2b00 cmp r3, #0 801757e: d10a bne.n 8017596 portYIELD_WITHIN_API(); 8017580: 4b09 ldr r3, [pc, #36] @ (80175a8 ) 8017582: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8017586: 601a str r2, [r3, #0] 8017588: f3bf 8f4f dsb sy 801758c: f3bf 8f6f isb sy } 8017590: e001 b.n 8017596 ( void ) xTaskResumeAll(); 8017592: f7fe fde9 bl 8016168 } 8017596: bf00 nop 8017598: 3710 adds r7, #16 801759a: 46bd mov sp, r7 801759c: bd80 pop {r7, pc} 801759e: bf00 nop 80175a0: 24002f24 .word 0x24002f24 80175a4: 24002f28 .word 0x24002f28 80175a8: e000ed04 .word 0xe000ed04 080175ac : /*-----------------------------------------------------------*/ static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) { 80175ac: b480 push {r7} 80175ae: b085 sub sp, #20 80175b0: af00 add r7, sp, #0 80175b2: 6078 str r0, [r7, #4] the timer with the nearest expiry time will expire. If there are no active timers then just set the next expire time to 0. That will cause this task to unblock when the tick count overflows, at which point the timer lists will be switched and the next expiry time can be re-assessed. */ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); 80175b4: 4b0e ldr r3, [pc, #56] @ (80175f0 ) 80175b6: 681b ldr r3, [r3, #0] 80175b8: 681b ldr r3, [r3, #0] 80175ba: 2b00 cmp r3, #0 80175bc: d101 bne.n 80175c2 80175be: 2201 movs r2, #1 80175c0: e000 b.n 80175c4 80175c2: 2200 movs r2, #0 80175c4: 687b ldr r3, [r7, #4] 80175c6: 601a str r2, [r3, #0] if( *pxListWasEmpty == pdFALSE ) 80175c8: 687b ldr r3, [r7, #4] 80175ca: 681b ldr r3, [r3, #0] 80175cc: 2b00 cmp r3, #0 80175ce: d105 bne.n 80175dc { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 80175d0: 4b07 ldr r3, [pc, #28] @ (80175f0 ) 80175d2: 681b ldr r3, [r3, #0] 80175d4: 68db ldr r3, [r3, #12] 80175d6: 681b ldr r3, [r3, #0] 80175d8: 60fb str r3, [r7, #12] 80175da: e001 b.n 80175e0 } else { /* Ensure the task unblocks when the tick count rolls over. */ xNextExpireTime = ( TickType_t ) 0U; 80175dc: 2300 movs r3, #0 80175de: 60fb str r3, [r7, #12] } return xNextExpireTime; 80175e0: 68fb ldr r3, [r7, #12] } 80175e2: 4618 mov r0, r3 80175e4: 3714 adds r7, #20 80175e6: 46bd mov sp, r7 80175e8: f85d 7b04 ldr.w r7, [sp], #4 80175ec: 4770 bx lr 80175ee: bf00 nop 80175f0: 24002f20 .word 0x24002f20 080175f4 : /*-----------------------------------------------------------*/ static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) { 80175f4: b580 push {r7, lr} 80175f6: b084 sub sp, #16 80175f8: af00 add r7, sp, #0 80175fa: 6078 str r0, [r7, #4] TickType_t xTimeNow; PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ xTimeNow = xTaskGetTickCount(); 80175fc: f7fe fe52 bl 80162a4 8017600: 60f8 str r0, [r7, #12] if( xTimeNow < xLastTime ) 8017602: 4b0b ldr r3, [pc, #44] @ (8017630 ) 8017604: 681b ldr r3, [r3, #0] 8017606: 68fa ldr r2, [r7, #12] 8017608: 429a cmp r2, r3 801760a: d205 bcs.n 8017618 { prvSwitchTimerLists(); 801760c: f000 f93a bl 8017884 *pxTimerListsWereSwitched = pdTRUE; 8017610: 687b ldr r3, [r7, #4] 8017612: 2201 movs r2, #1 8017614: 601a str r2, [r3, #0] 8017616: e002 b.n 801761e } else { *pxTimerListsWereSwitched = pdFALSE; 8017618: 687b ldr r3, [r7, #4] 801761a: 2200 movs r2, #0 801761c: 601a str r2, [r3, #0] } xLastTime = xTimeNow; 801761e: 4a04 ldr r2, [pc, #16] @ (8017630 ) 8017620: 68fb ldr r3, [r7, #12] 8017622: 6013 str r3, [r2, #0] return xTimeNow; 8017624: 68fb ldr r3, [r7, #12] } 8017626: 4618 mov r0, r3 8017628: 3710 adds r7, #16 801762a: 46bd mov sp, r7 801762c: bd80 pop {r7, pc} 801762e: bf00 nop 8017630: 24002f30 .word 0x24002f30 08017634 : /*-----------------------------------------------------------*/ static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) { 8017634: b580 push {r7, lr} 8017636: b086 sub sp, #24 8017638: af00 add r7, sp, #0 801763a: 60f8 str r0, [r7, #12] 801763c: 60b9 str r1, [r7, #8] 801763e: 607a str r2, [r7, #4] 8017640: 603b str r3, [r7, #0] BaseType_t xProcessTimerNow = pdFALSE; 8017642: 2300 movs r3, #0 8017644: 617b str r3, [r7, #20] listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); 8017646: 68fb ldr r3, [r7, #12] 8017648: 68ba ldr r2, [r7, #8] 801764a: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 801764c: 68fb ldr r3, [r7, #12] 801764e: 68fa ldr r2, [r7, #12] 8017650: 611a str r2, [r3, #16] if( xNextExpiryTime <= xTimeNow ) 8017652: 68ba ldr r2, [r7, #8] 8017654: 687b ldr r3, [r7, #4] 8017656: 429a cmp r2, r3 8017658: d812 bhi.n 8017680 { /* Has the expiry time elapsed between the command to start/reset a timer was issued, and the time the command was processed? */ if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 801765a: 687a ldr r2, [r7, #4] 801765c: 683b ldr r3, [r7, #0] 801765e: 1ad2 subs r2, r2, r3 8017660: 68fb ldr r3, [r7, #12] 8017662: 699b ldr r3, [r3, #24] 8017664: 429a cmp r2, r3 8017666: d302 bcc.n 801766e { /* The time between a command being issued and the command being processed actually exceeds the timers period. */ xProcessTimerNow = pdTRUE; 8017668: 2301 movs r3, #1 801766a: 617b str r3, [r7, #20] 801766c: e01b b.n 80176a6 } else { vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); 801766e: 4b10 ldr r3, [pc, #64] @ (80176b0 ) 8017670: 681a ldr r2, [r3, #0] 8017672: 68fb ldr r3, [r7, #12] 8017674: 3304 adds r3, #4 8017676: 4619 mov r1, r3 8017678: 4610 mov r0, r2 801767a: f7fd f94a bl 8014912 801767e: e012 b.n 80176a6 } } else { if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) 8017680: 687a ldr r2, [r7, #4] 8017682: 683b ldr r3, [r7, #0] 8017684: 429a cmp r2, r3 8017686: d206 bcs.n 8017696 8017688: 68ba ldr r2, [r7, #8] 801768a: 683b ldr r3, [r7, #0] 801768c: 429a cmp r2, r3 801768e: d302 bcc.n 8017696 { /* If, since the command was issued, the tick count has overflowed but the expiry time has not, then the timer must have already passed its expiry time and should be processed immediately. */ xProcessTimerNow = pdTRUE; 8017690: 2301 movs r3, #1 8017692: 617b str r3, [r7, #20] 8017694: e007 b.n 80176a6 } else { vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 8017696: 4b07 ldr r3, [pc, #28] @ (80176b4 ) 8017698: 681a ldr r2, [r3, #0] 801769a: 68fb ldr r3, [r7, #12] 801769c: 3304 adds r3, #4 801769e: 4619 mov r1, r3 80176a0: 4610 mov r0, r2 80176a2: f7fd f936 bl 8014912 } } return xProcessTimerNow; 80176a6: 697b ldr r3, [r7, #20] } 80176a8: 4618 mov r0, r3 80176aa: 3718 adds r7, #24 80176ac: 46bd mov sp, r7 80176ae: bd80 pop {r7, pc} 80176b0: 24002f24 .word 0x24002f24 80176b4: 24002f20 .word 0x24002f20 080176b8 : /*-----------------------------------------------------------*/ static void prvProcessReceivedCommands( void ) { 80176b8: b580 push {r7, lr} 80176ba: b08e sub sp, #56 @ 0x38 80176bc: af02 add r7, sp, #8 DaemonTaskMessage_t xMessage; Timer_t *pxTimer; BaseType_t xTimerListsWereSwitched, xResult; TickType_t xTimeNow; while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 80176be: e0ce b.n 801785e { #if ( INCLUDE_xTimerPendFunctionCall == 1 ) { /* Negative commands are pended function calls rather than timer commands. */ if( xMessage.xMessageID < ( BaseType_t ) 0 ) 80176c0: 687b ldr r3, [r7, #4] 80176c2: 2b00 cmp r3, #0 80176c4: da19 bge.n 80176fa { const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); 80176c6: 1d3b adds r3, r7, #4 80176c8: 3304 adds r3, #4 80176ca: 62fb str r3, [r7, #44] @ 0x2c /* The timer uses the xCallbackParameters member to request a callback be executed. Check the callback is not NULL. */ configASSERT( pxCallback ); 80176cc: 6afb ldr r3, [r7, #44] @ 0x2c 80176ce: 2b00 cmp r3, #0 80176d0: d10b bne.n 80176ea __asm volatile 80176d2: f04f 0350 mov.w r3, #80 @ 0x50 80176d6: f383 8811 msr BASEPRI, r3 80176da: f3bf 8f6f isb sy 80176de: f3bf 8f4f dsb sy 80176e2: 61fb str r3, [r7, #28] } 80176e4: bf00 nop 80176e6: bf00 nop 80176e8: e7fd b.n 80176e6 /* Call the function. */ pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); 80176ea: 6afb ldr r3, [r7, #44] @ 0x2c 80176ec: 681b ldr r3, [r3, #0] 80176ee: 6afa ldr r2, [r7, #44] @ 0x2c 80176f0: 6850 ldr r0, [r2, #4] 80176f2: 6afa ldr r2, [r7, #44] @ 0x2c 80176f4: 6892 ldr r2, [r2, #8] 80176f6: 4611 mov r1, r2 80176f8: 4798 blx r3 } #endif /* INCLUDE_xTimerPendFunctionCall */ /* Commands that are positive are timer commands rather than pended function calls. */ if( xMessage.xMessageID >= ( BaseType_t ) 0 ) 80176fa: 687b ldr r3, [r7, #4] 80176fc: 2b00 cmp r3, #0 80176fe: f2c0 80ae blt.w 801785e { /* The messages uses the xTimerParameters member to work on a software timer. */ pxTimer = xMessage.u.xTimerParameters.pxTimer; 8017702: 68fb ldr r3, [r7, #12] 8017704: 62bb str r3, [r7, #40] @ 0x28 if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ 8017706: 6abb ldr r3, [r7, #40] @ 0x28 8017708: 695b ldr r3, [r3, #20] 801770a: 2b00 cmp r3, #0 801770c: d004 beq.n 8017718 { /* The timer is in a list, remove it. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 801770e: 6abb ldr r3, [r7, #40] @ 0x28 8017710: 3304 adds r3, #4 8017712: 4618 mov r0, r3 8017714: f7fd f936 bl 8014984 it must be present in the function call. prvSampleTimeNow() must be called after the message is received from xTimerQueue so there is no possibility of a higher priority task adding a message to the message queue with a time that is ahead of the timer daemon task (because it pre-empted the timer daemon task after the xTimeNow value was set). */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8017718: 463b mov r3, r7 801771a: 4618 mov r0, r3 801771c: f7ff ff6a bl 80175f4 8017720: 6278 str r0, [r7, #36] @ 0x24 switch( xMessage.xMessageID ) 8017722: 687b ldr r3, [r7, #4] 8017724: 2b09 cmp r3, #9 8017726: f200 8097 bhi.w 8017858 801772a: a201 add r2, pc, #4 @ (adr r2, 8017730 ) 801772c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8017730: 08017759 .word 0x08017759 8017734: 08017759 .word 0x08017759 8017738: 08017759 .word 0x08017759 801773c: 080177cf .word 0x080177cf 8017740: 080177e3 .word 0x080177e3 8017744: 0801782f .word 0x0801782f 8017748: 08017759 .word 0x08017759 801774c: 08017759 .word 0x08017759 8017750: 080177cf .word 0x080177cf 8017754: 080177e3 .word 0x080177e3 case tmrCOMMAND_START_FROM_ISR : case tmrCOMMAND_RESET : case tmrCOMMAND_RESET_FROM_ISR : case tmrCOMMAND_START_DONT_TRACE : /* Start or restart a timer. */ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8017758: 6abb ldr r3, [r7, #40] @ 0x28 801775a: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 801775e: f043 0301 orr.w r3, r3, #1 8017762: b2da uxtb r2, r3 8017764: 6abb ldr r3, [r7, #40] @ 0x28 8017766: f883 2028 strb.w r2, [r3, #40] @ 0x28 if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) 801776a: 68ba ldr r2, [r7, #8] 801776c: 6abb ldr r3, [r7, #40] @ 0x28 801776e: 699b ldr r3, [r3, #24] 8017770: 18d1 adds r1, r2, r3 8017772: 68bb ldr r3, [r7, #8] 8017774: 6a7a ldr r2, [r7, #36] @ 0x24 8017776: 6ab8 ldr r0, [r7, #40] @ 0x28 8017778: f7ff ff5c bl 8017634 801777c: 4603 mov r3, r0 801777e: 2b00 cmp r3, #0 8017780: d06c beq.n 801785c { /* The timer expired before it was added to the active timer list. Process it now. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8017782: 6abb ldr r3, [r7, #40] @ 0x28 8017784: 6a1b ldr r3, [r3, #32] 8017786: 6ab8 ldr r0, [r7, #40] @ 0x28 8017788: 4798 blx r3 traceTIMER_EXPIRED( pxTimer ); if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 801778a: 6abb ldr r3, [r7, #40] @ 0x28 801778c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017790: f003 0304 and.w r3, r3, #4 8017794: 2b00 cmp r3, #0 8017796: d061 beq.n 801785c { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); 8017798: 68ba ldr r2, [r7, #8] 801779a: 6abb ldr r3, [r7, #40] @ 0x28 801779c: 699b ldr r3, [r3, #24] 801779e: 441a add r2, r3 80177a0: 2300 movs r3, #0 80177a2: 9300 str r3, [sp, #0] 80177a4: 2300 movs r3, #0 80177a6: 2100 movs r1, #0 80177a8: 6ab8 ldr r0, [r7, #40] @ 0x28 80177aa: f7ff fe01 bl 80173b0 80177ae: 6238 str r0, [r7, #32] configASSERT( xResult ); 80177b0: 6a3b ldr r3, [r7, #32] 80177b2: 2b00 cmp r3, #0 80177b4: d152 bne.n 801785c __asm volatile 80177b6: f04f 0350 mov.w r3, #80 @ 0x50 80177ba: f383 8811 msr BASEPRI, r3 80177be: f3bf 8f6f isb sy 80177c2: f3bf 8f4f dsb sy 80177c6: 61bb str r3, [r7, #24] } 80177c8: bf00 nop 80177ca: bf00 nop 80177cc: e7fd b.n 80177ca break; case tmrCOMMAND_STOP : case tmrCOMMAND_STOP_FROM_ISR : /* The timer has already been removed from the active list. */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 80177ce: 6abb ldr r3, [r7, #40] @ 0x28 80177d0: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80177d4: f023 0301 bic.w r3, r3, #1 80177d8: b2da uxtb r2, r3 80177da: 6abb ldr r3, [r7, #40] @ 0x28 80177dc: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 80177e0: e03d b.n 801785e case tmrCOMMAND_CHANGE_PERIOD : case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR : pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 80177e2: 6abb ldr r3, [r7, #40] @ 0x28 80177e4: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80177e8: f043 0301 orr.w r3, r3, #1 80177ec: b2da uxtb r2, r3 80177ee: 6abb ldr r3, [r7, #40] @ 0x28 80177f0: f883 2028 strb.w r2, [r3, #40] @ 0x28 pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; 80177f4: 68ba ldr r2, [r7, #8] 80177f6: 6abb ldr r3, [r7, #40] @ 0x28 80177f8: 619a str r2, [r3, #24] configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); 80177fa: 6abb ldr r3, [r7, #40] @ 0x28 80177fc: 699b ldr r3, [r3, #24] 80177fe: 2b00 cmp r3, #0 8017800: d10b bne.n 801781a __asm volatile 8017802: f04f 0350 mov.w r3, #80 @ 0x50 8017806: f383 8811 msr BASEPRI, r3 801780a: f3bf 8f6f isb sy 801780e: f3bf 8f4f dsb sy 8017812: 617b str r3, [r7, #20] } 8017814: bf00 nop 8017816: bf00 nop 8017818: e7fd b.n 8017816 be longer or shorter than the old one. The command time is therefore set to the current time, and as the period cannot be zero the next expiry time can only be in the future, meaning (unlike for the xTimerStart() case above) there is no fail case that needs to be handled here. */ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); 801781a: 6abb ldr r3, [r7, #40] @ 0x28 801781c: 699a ldr r2, [r3, #24] 801781e: 6a7b ldr r3, [r7, #36] @ 0x24 8017820: 18d1 adds r1, r2, r3 8017822: 6a7b ldr r3, [r7, #36] @ 0x24 8017824: 6a7a ldr r2, [r7, #36] @ 0x24 8017826: 6ab8 ldr r0, [r7, #40] @ 0x28 8017828: f7ff ff04 bl 8017634 break; 801782c: e017 b.n 801785e #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* The timer has already been removed from the active list, just free up the memory if the memory was dynamically allocated. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) 801782e: 6abb ldr r3, [r7, #40] @ 0x28 8017830: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017834: f003 0302 and.w r3, r3, #2 8017838: 2b00 cmp r3, #0 801783a: d103 bne.n 8017844 { vPortFree( pxTimer ); 801783c: 6ab8 ldr r0, [r7, #40] @ 0x28 801783e: f000 fc33 bl 80180a8 no need to free the memory - just mark the timer as "not active". */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ break; 8017842: e00c b.n 801785e pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8017844: 6abb ldr r3, [r7, #40] @ 0x28 8017846: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 801784a: f023 0301 bic.w r3, r3, #1 801784e: b2da uxtb r2, r3 8017850: 6abb ldr r3, [r7, #40] @ 0x28 8017852: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8017856: e002 b.n 801785e default : /* Don't expect to get here. */ break; 8017858: bf00 nop 801785a: e000 b.n 801785e break; 801785c: bf00 nop while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 801785e: 4b08 ldr r3, [pc, #32] @ (8017880 ) 8017860: 681b ldr r3, [r3, #0] 8017862: 1d39 adds r1, r7, #4 8017864: 2200 movs r2, #0 8017866: 4618 mov r0, r3 8017868: f7fd fc54 bl 8015114 801786c: 4603 mov r3, r0 801786e: 2b00 cmp r3, #0 8017870: f47f af26 bne.w 80176c0 } } } } 8017874: bf00 nop 8017876: bf00 nop 8017878: 3730 adds r7, #48 @ 0x30 801787a: 46bd mov sp, r7 801787c: bd80 pop {r7, pc} 801787e: bf00 nop 8017880: 24002f28 .word 0x24002f28 08017884 : /*-----------------------------------------------------------*/ static void prvSwitchTimerLists( void ) { 8017884: b580 push {r7, lr} 8017886: b088 sub sp, #32 8017888: af02 add r7, sp, #8 /* The tick count has overflowed. The timer lists must be switched. If there are any timers still referenced from the current timer list then they must have expired and should be processed before the lists are switched. */ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 801788a: e049 b.n 8017920 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 801788c: 4b2e ldr r3, [pc, #184] @ (8017948 ) 801788e: 681b ldr r3, [r3, #0] 8017890: 68db ldr r3, [r3, #12] 8017892: 681b ldr r3, [r3, #0] 8017894: 613b str r3, [r7, #16] /* Remove the timer from the list. */ pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8017896: 4b2c ldr r3, [pc, #176] @ (8017948 ) 8017898: 681b ldr r3, [r3, #0] 801789a: 68db ldr r3, [r3, #12] 801789c: 68db ldr r3, [r3, #12] 801789e: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 80178a0: 68fb ldr r3, [r7, #12] 80178a2: 3304 adds r3, #4 80178a4: 4618 mov r0, r3 80178a6: f7fd f86d bl 8014984 traceTIMER_EXPIRED( pxTimer ); /* Execute its callback, then send a command to restart the timer if it is an auto-reload timer. It cannot be restarted here as the lists have not yet been switched. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 80178aa: 68fb ldr r3, [r7, #12] 80178ac: 6a1b ldr r3, [r3, #32] 80178ae: 68f8 ldr r0, [r7, #12] 80178b0: 4798 blx r3 if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 80178b2: 68fb ldr r3, [r7, #12] 80178b4: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80178b8: f003 0304 and.w r3, r3, #4 80178bc: 2b00 cmp r3, #0 80178be: d02f beq.n 8017920 the timer going into the same timer list then it has already expired and the timer should be re-inserted into the current list so it is processed again within this loop. Otherwise a command should be sent to restart the timer to ensure it is only inserted into a list after the lists have been swapped. */ xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); 80178c0: 68fb ldr r3, [r7, #12] 80178c2: 699b ldr r3, [r3, #24] 80178c4: 693a ldr r2, [r7, #16] 80178c6: 4413 add r3, r2 80178c8: 60bb str r3, [r7, #8] if( xReloadTime > xNextExpireTime ) 80178ca: 68ba ldr r2, [r7, #8] 80178cc: 693b ldr r3, [r7, #16] 80178ce: 429a cmp r2, r3 80178d0: d90e bls.n 80178f0 { listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); 80178d2: 68fb ldr r3, [r7, #12] 80178d4: 68ba ldr r2, [r7, #8] 80178d6: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 80178d8: 68fb ldr r3, [r7, #12] 80178da: 68fa ldr r2, [r7, #12] 80178dc: 611a str r2, [r3, #16] vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 80178de: 4b1a ldr r3, [pc, #104] @ (8017948 ) 80178e0: 681a ldr r2, [r3, #0] 80178e2: 68fb ldr r3, [r7, #12] 80178e4: 3304 adds r3, #4 80178e6: 4619 mov r1, r3 80178e8: 4610 mov r0, r2 80178ea: f7fd f812 bl 8014912 80178ee: e017 b.n 8017920 } else { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 80178f0: 2300 movs r3, #0 80178f2: 9300 str r3, [sp, #0] 80178f4: 2300 movs r3, #0 80178f6: 693a ldr r2, [r7, #16] 80178f8: 2100 movs r1, #0 80178fa: 68f8 ldr r0, [r7, #12] 80178fc: f7ff fd58 bl 80173b0 8017900: 6078 str r0, [r7, #4] configASSERT( xResult ); 8017902: 687b ldr r3, [r7, #4] 8017904: 2b00 cmp r3, #0 8017906: d10b bne.n 8017920 __asm volatile 8017908: f04f 0350 mov.w r3, #80 @ 0x50 801790c: f383 8811 msr BASEPRI, r3 8017910: f3bf 8f6f isb sy 8017914: f3bf 8f4f dsb sy 8017918: 603b str r3, [r7, #0] } 801791a: bf00 nop 801791c: bf00 nop 801791e: e7fd b.n 801791c while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 8017920: 4b09 ldr r3, [pc, #36] @ (8017948 ) 8017922: 681b ldr r3, [r3, #0] 8017924: 681b ldr r3, [r3, #0] 8017926: 2b00 cmp r3, #0 8017928: d1b0 bne.n 801788c { mtCOVERAGE_TEST_MARKER(); } } pxTemp = pxCurrentTimerList; 801792a: 4b07 ldr r3, [pc, #28] @ (8017948 ) 801792c: 681b ldr r3, [r3, #0] 801792e: 617b str r3, [r7, #20] pxCurrentTimerList = pxOverflowTimerList; 8017930: 4b06 ldr r3, [pc, #24] @ (801794c ) 8017932: 681b ldr r3, [r3, #0] 8017934: 4a04 ldr r2, [pc, #16] @ (8017948 ) 8017936: 6013 str r3, [r2, #0] pxOverflowTimerList = pxTemp; 8017938: 4a04 ldr r2, [pc, #16] @ (801794c ) 801793a: 697b ldr r3, [r7, #20] 801793c: 6013 str r3, [r2, #0] } 801793e: bf00 nop 8017940: 3718 adds r7, #24 8017942: 46bd mov sp, r7 8017944: bd80 pop {r7, pc} 8017946: bf00 nop 8017948: 24002f20 .word 0x24002f20 801794c: 24002f24 .word 0x24002f24 08017950 : /*-----------------------------------------------------------*/ static void prvCheckForValidListAndQueue( void ) { 8017950: b580 push {r7, lr} 8017952: b082 sub sp, #8 8017954: af02 add r7, sp, #8 /* Check that the list from which active timers are referenced, and the queue used to communicate with the timer service, have been initialised. */ taskENTER_CRITICAL(); 8017956: f000 f9b7 bl 8017cc8 { if( xTimerQueue == NULL ) 801795a: 4b15 ldr r3, [pc, #84] @ (80179b0 ) 801795c: 681b ldr r3, [r3, #0] 801795e: 2b00 cmp r3, #0 8017960: d120 bne.n 80179a4 { vListInitialise( &xActiveTimerList1 ); 8017962: 4814 ldr r0, [pc, #80] @ (80179b4 ) 8017964: f7fc ff84 bl 8014870 vListInitialise( &xActiveTimerList2 ); 8017968: 4813 ldr r0, [pc, #76] @ (80179b8 ) 801796a: f7fc ff81 bl 8014870 pxCurrentTimerList = &xActiveTimerList1; 801796e: 4b13 ldr r3, [pc, #76] @ (80179bc ) 8017970: 4a10 ldr r2, [pc, #64] @ (80179b4 ) 8017972: 601a str r2, [r3, #0] pxOverflowTimerList = &xActiveTimerList2; 8017974: 4b12 ldr r3, [pc, #72] @ (80179c0 ) 8017976: 4a10 ldr r2, [pc, #64] @ (80179b8 ) 8017978: 601a str r2, [r3, #0] /* The timer queue is allocated statically in case configSUPPORT_DYNAMIC_ALLOCATION is 0. */ static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 801797a: 2300 movs r3, #0 801797c: 9300 str r3, [sp, #0] 801797e: 4b11 ldr r3, [pc, #68] @ (80179c4 ) 8017980: 4a11 ldr r2, [pc, #68] @ (80179c8 ) 8017982: 2110 movs r1, #16 8017984: 200a movs r0, #10 8017986: f7fd f891 bl 8014aac 801798a: 4603 mov r3, r0 801798c: 4a08 ldr r2, [pc, #32] @ (80179b0 ) 801798e: 6013 str r3, [r2, #0] } #endif #if ( configQUEUE_REGISTRY_SIZE > 0 ) { if( xTimerQueue != NULL ) 8017990: 4b07 ldr r3, [pc, #28] @ (80179b0 ) 8017992: 681b ldr r3, [r3, #0] 8017994: 2b00 cmp r3, #0 8017996: d005 beq.n 80179a4 { vQueueAddToRegistry( xTimerQueue, "TmrQ" ); 8017998: 4b05 ldr r3, [pc, #20] @ (80179b0 ) 801799a: 681b ldr r3, [r3, #0] 801799c: 490b ldr r1, [pc, #44] @ (80179cc ) 801799e: 4618 mov r0, r3 80179a0: f7fd ff54 bl 801584c else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 80179a4: f000 f9c2 bl 8017d2c } 80179a8: bf00 nop 80179aa: 46bd mov sp, r7 80179ac: bd80 pop {r7, pc} 80179ae: bf00 nop 80179b0: 24002f28 .word 0x24002f28 80179b4: 24002ef8 .word 0x24002ef8 80179b8: 24002f0c .word 0x24002f0c 80179bc: 24002f20 .word 0x24002f20 80179c0: 24002f24 .word 0x24002f24 80179c4: 24002fd4 .word 0x24002fd4 80179c8: 24002f34 .word 0x24002f34 80179cc: 08018670 .word 0x08018670 080179d0 : /*-----------------------------------------------------------*/ BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) { 80179d0: b580 push {r7, lr} 80179d2: b086 sub sp, #24 80179d4: af00 add r7, sp, #0 80179d6: 6078 str r0, [r7, #4] BaseType_t xReturn; Timer_t *pxTimer = xTimer; 80179d8: 687b ldr r3, [r7, #4] 80179da: 613b str r3, [r7, #16] configASSERT( xTimer ); 80179dc: 687b ldr r3, [r7, #4] 80179de: 2b00 cmp r3, #0 80179e0: d10b bne.n 80179fa __asm volatile 80179e2: f04f 0350 mov.w r3, #80 @ 0x50 80179e6: f383 8811 msr BASEPRI, r3 80179ea: f3bf 8f6f isb sy 80179ee: f3bf 8f4f dsb sy 80179f2: 60fb str r3, [r7, #12] } 80179f4: bf00 nop 80179f6: bf00 nop 80179f8: e7fd b.n 80179f6 /* Is the timer in the list of active timers? */ taskENTER_CRITICAL(); 80179fa: f000 f965 bl 8017cc8 { if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 ) 80179fe: 693b ldr r3, [r7, #16] 8017a00: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017a04: f003 0301 and.w r3, r3, #1 8017a08: 2b00 cmp r3, #0 8017a0a: d102 bne.n 8017a12 { xReturn = pdFALSE; 8017a0c: 2300 movs r3, #0 8017a0e: 617b str r3, [r7, #20] 8017a10: e001 b.n 8017a16 } else { xReturn = pdTRUE; 8017a12: 2301 movs r3, #1 8017a14: 617b str r3, [r7, #20] } } taskEXIT_CRITICAL(); 8017a16: f000 f989 bl 8017d2c return xReturn; 8017a1a: 697b ldr r3, [r7, #20] } /*lint !e818 Can't be pointer to const due to the typedef. */ 8017a1c: 4618 mov r0, r3 8017a1e: 3718 adds r7, #24 8017a20: 46bd mov sp, r7 8017a22: bd80 pop {r7, pc} 08017a24 : /*-----------------------------------------------------------*/ void *pvTimerGetTimerID( const TimerHandle_t xTimer ) { 8017a24: b580 push {r7, lr} 8017a26: b086 sub sp, #24 8017a28: af00 add r7, sp, #0 8017a2a: 6078 str r0, [r7, #4] Timer_t * const pxTimer = xTimer; 8017a2c: 687b ldr r3, [r7, #4] 8017a2e: 617b str r3, [r7, #20] void *pvReturn; configASSERT( xTimer ); 8017a30: 687b ldr r3, [r7, #4] 8017a32: 2b00 cmp r3, #0 8017a34: d10b bne.n 8017a4e __asm volatile 8017a36: f04f 0350 mov.w r3, #80 @ 0x50 8017a3a: f383 8811 msr BASEPRI, r3 8017a3e: f3bf 8f6f isb sy 8017a42: f3bf 8f4f dsb sy 8017a46: 60fb str r3, [r7, #12] } 8017a48: bf00 nop 8017a4a: bf00 nop 8017a4c: e7fd b.n 8017a4a taskENTER_CRITICAL(); 8017a4e: f000 f93b bl 8017cc8 { pvReturn = pxTimer->pvTimerID; 8017a52: 697b ldr r3, [r7, #20] 8017a54: 69db ldr r3, [r3, #28] 8017a56: 613b str r3, [r7, #16] } taskEXIT_CRITICAL(); 8017a58: f000 f968 bl 8017d2c return pvReturn; 8017a5c: 693b ldr r3, [r7, #16] } 8017a5e: 4618 mov r0, r3 8017a60: 3718 adds r7, #24 8017a62: 46bd mov sp, r7 8017a64: bd80 pop {r7, pc} ... 08017a68 : /* * See header file for description. */ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) { 8017a68: b480 push {r7} 8017a6a: b085 sub sp, #20 8017a6c: af00 add r7, sp, #0 8017a6e: 60f8 str r0, [r7, #12] 8017a70: 60b9 str r1, [r7, #8] 8017a72: 607a str r2, [r7, #4] /* Simulate the stack frame as it would be created by a context switch interrupt. */ /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts, and to ensure alignment. */ pxTopOfStack--; 8017a74: 68fb ldr r3, [r7, #12] 8017a76: 3b04 subs r3, #4 8017a78: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ 8017a7a: 68fb ldr r3, [r7, #12] 8017a7c: f04f 7280 mov.w r2, #16777216 @ 0x1000000 8017a80: 601a str r2, [r3, #0] pxTopOfStack--; 8017a82: 68fb ldr r3, [r7, #12] 8017a84: 3b04 subs r3, #4 8017a86: 60fb str r3, [r7, #12] *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ 8017a88: 68bb ldr r3, [r7, #8] 8017a8a: f023 0201 bic.w r2, r3, #1 8017a8e: 68fb ldr r3, [r7, #12] 8017a90: 601a str r2, [r3, #0] pxTopOfStack--; 8017a92: 68fb ldr r3, [r7, #12] 8017a94: 3b04 subs r3, #4 8017a96: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ 8017a98: 4a0c ldr r2, [pc, #48] @ (8017acc ) 8017a9a: 68fb ldr r3, [r7, #12] 8017a9c: 601a str r2, [r3, #0] /* Save code space by skipping register initialisation. */ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ 8017a9e: 68fb ldr r3, [r7, #12] 8017aa0: 3b14 subs r3, #20 8017aa2: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ 8017aa4: 687a ldr r2, [r7, #4] 8017aa6: 68fb ldr r3, [r7, #12] 8017aa8: 601a str r2, [r3, #0] /* A save method is being used that requires each task to maintain its own exec return value. */ pxTopOfStack--; 8017aaa: 68fb ldr r3, [r7, #12] 8017aac: 3b04 subs r3, #4 8017aae: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_EXC_RETURN; 8017ab0: 68fb ldr r3, [r7, #12] 8017ab2: f06f 0202 mvn.w r2, #2 8017ab6: 601a str r2, [r3, #0] pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ 8017ab8: 68fb ldr r3, [r7, #12] 8017aba: 3b20 subs r3, #32 8017abc: 60fb str r3, [r7, #12] return pxTopOfStack; 8017abe: 68fb ldr r3, [r7, #12] } 8017ac0: 4618 mov r0, r3 8017ac2: 3714 adds r7, #20 8017ac4: 46bd mov sp, r7 8017ac6: f85d 7b04 ldr.w r7, [sp], #4 8017aca: 4770 bx lr 8017acc: 08017ad1 .word 0x08017ad1 08017ad0 : /*-----------------------------------------------------------*/ static void prvTaskExitError( void ) { 8017ad0: b480 push {r7} 8017ad2: b085 sub sp, #20 8017ad4: af00 add r7, sp, #0 volatile uint32_t ulDummy = 0; 8017ad6: 2300 movs r3, #0 8017ad8: 607b str r3, [r7, #4] its caller as there is nothing to return to. If a task wants to exit it should instead call vTaskDelete( NULL ). Artificially force an assert() to be triggered if configASSERT() is defined, then stop here so application writers can catch the error. */ configASSERT( uxCriticalNesting == ~0UL ); 8017ada: 4b13 ldr r3, [pc, #76] @ (8017b28 ) 8017adc: 681b ldr r3, [r3, #0] 8017ade: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8017ae2: d00b beq.n 8017afc __asm volatile 8017ae4: f04f 0350 mov.w r3, #80 @ 0x50 8017ae8: f383 8811 msr BASEPRI, r3 8017aec: f3bf 8f6f isb sy 8017af0: f3bf 8f4f dsb sy 8017af4: 60fb str r3, [r7, #12] } 8017af6: bf00 nop 8017af8: bf00 nop 8017afa: e7fd b.n 8017af8 __asm volatile 8017afc: f04f 0350 mov.w r3, #80 @ 0x50 8017b00: f383 8811 msr BASEPRI, r3 8017b04: f3bf 8f6f isb sy 8017b08: f3bf 8f4f dsb sy 8017b0c: 60bb str r3, [r7, #8] } 8017b0e: bf00 nop portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) 8017b10: bf00 nop 8017b12: 687b ldr r3, [r7, #4] 8017b14: 2b00 cmp r3, #0 8017b16: d0fc beq.n 8017b12 about code appearing after this function is called - making ulDummy volatile makes the compiler think the function could return and therefore not output an 'unreachable code' warning for code that appears after it. */ } } 8017b18: bf00 nop 8017b1a: bf00 nop 8017b1c: 3714 adds r7, #20 8017b1e: 46bd mov sp, r7 8017b20: f85d 7b04 ldr.w r7, [sp], #4 8017b24: 4770 bx lr 8017b26: bf00 nop 8017b28: 24000044 .word 0x24000044 8017b2c: 00000000 .word 0x00000000 08017b30 : /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( 8017b30: 4b07 ldr r3, [pc, #28] @ (8017b50 ) 8017b32: 6819 ldr r1, [r3, #0] 8017b34: 6808 ldr r0, [r1, #0] 8017b36: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017b3a: f380 8809 msr PSP, r0 8017b3e: f3bf 8f6f isb sy 8017b42: f04f 0000 mov.w r0, #0 8017b46: f380 8811 msr BASEPRI, r0 8017b4a: 4770 bx lr 8017b4c: f3af 8000 nop.w 08017b50 : 8017b50: 240029f8 .word 0x240029f8 " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } 8017b54: bf00 nop 8017b56: bf00 nop 08017b58 : { /* Start the first task. This also clears the bit that indicates the FPU is in use in case the FPU was used before the scheduler was started - which would otherwise result in the unnecessary leaving of space in the SVC stack for lazy saving of FPU registers. */ __asm volatile( 8017b58: 4808 ldr r0, [pc, #32] @ (8017b7c ) 8017b5a: 6800 ldr r0, [r0, #0] 8017b5c: 6800 ldr r0, [r0, #0] 8017b5e: f380 8808 msr MSP, r0 8017b62: f04f 0000 mov.w r0, #0 8017b66: f380 8814 msr CONTROL, r0 8017b6a: b662 cpsie i 8017b6c: b661 cpsie f 8017b6e: f3bf 8f4f dsb sy 8017b72: f3bf 8f6f isb sy 8017b76: df00 svc 0 8017b78: bf00 nop " dsb \n" " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n" ); } 8017b7a: bf00 nop 8017b7c: e000ed08 .word 0xe000ed08 08017b80 : /* * See header file for description. */ BaseType_t xPortStartScheduler( void ) { 8017b80: b580 push {r7, lr} 8017b82: b086 sub sp, #24 8017b84: af00 add r7, sp, #0 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); /* This port can be used on all revisions of the Cortex-M7 core other than the r0p1 parts. r0p1 parts should use the port from the /source/portable/GCC/ARM_CM7/r0p1 directory. */ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); 8017b86: 4b47 ldr r3, [pc, #284] @ (8017ca4 ) 8017b88: 681b ldr r3, [r3, #0] 8017b8a: 4a47 ldr r2, [pc, #284] @ (8017ca8 ) 8017b8c: 4293 cmp r3, r2 8017b8e: d10b bne.n 8017ba8 __asm volatile 8017b90: f04f 0350 mov.w r3, #80 @ 0x50 8017b94: f383 8811 msr BASEPRI, r3 8017b98: f3bf 8f6f isb sy 8017b9c: f3bf 8f4f dsb sy 8017ba0: 613b str r3, [r7, #16] } 8017ba2: bf00 nop 8017ba4: bf00 nop 8017ba6: e7fd b.n 8017ba4 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); 8017ba8: 4b3e ldr r3, [pc, #248] @ (8017ca4 ) 8017baa: 681b ldr r3, [r3, #0] 8017bac: 4a3f ldr r2, [pc, #252] @ (8017cac ) 8017bae: 4293 cmp r3, r2 8017bb0: d10b bne.n 8017bca __asm volatile 8017bb2: f04f 0350 mov.w r3, #80 @ 0x50 8017bb6: f383 8811 msr BASEPRI, r3 8017bba: f3bf 8f6f isb sy 8017bbe: f3bf 8f4f dsb sy 8017bc2: 60fb str r3, [r7, #12] } 8017bc4: bf00 nop 8017bc6: bf00 nop 8017bc8: e7fd b.n 8017bc6 #if( configASSERT_DEFINED == 1 ) { volatile uint32_t ulOriginalPriority; volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); 8017bca: 4b39 ldr r3, [pc, #228] @ (8017cb0 ) 8017bcc: 617b str r3, [r7, #20] functions can be called. ISR safe functions are those that end in "FromISR". FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. Save the interrupt priority value that is about to be clobbered. */ ulOriginalPriority = *pucFirstUserPriorityRegister; 8017bce: 697b ldr r3, [r7, #20] 8017bd0: 781b ldrb r3, [r3, #0] 8017bd2: b2db uxtb r3, r3 8017bd4: 607b str r3, [r7, #4] /* Determine the number of priority bits available. First write to all possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; 8017bd6: 697b ldr r3, [r7, #20] 8017bd8: 22ff movs r2, #255 @ 0xff 8017bda: 701a strb r2, [r3, #0] /* Read the value back to see how many bits stuck. */ ucMaxPriorityValue = *pucFirstUserPriorityRegister; 8017bdc: 697b ldr r3, [r7, #20] 8017bde: 781b ldrb r3, [r3, #0] 8017be0: b2db uxtb r3, r3 8017be2: 70fb strb r3, [r7, #3] /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; 8017be4: 78fb ldrb r3, [r7, #3] 8017be6: b2db uxtb r3, r3 8017be8: f003 0350 and.w r3, r3, #80 @ 0x50 8017bec: b2da uxtb r2, r3 8017bee: 4b31 ldr r3, [pc, #196] @ (8017cb4 ) 8017bf0: 701a strb r2, [r3, #0] /* Calculate the maximum acceptable priority group value for the number of bits read back. */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; 8017bf2: 4b31 ldr r3, [pc, #196] @ (8017cb8 ) 8017bf4: 2207 movs r2, #7 8017bf6: 601a str r2, [r3, #0] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 8017bf8: e009 b.n 8017c0e { ulMaxPRIGROUPValue--; 8017bfa: 4b2f ldr r3, [pc, #188] @ (8017cb8 ) 8017bfc: 681b ldr r3, [r3, #0] 8017bfe: 3b01 subs r3, #1 8017c00: 4a2d ldr r2, [pc, #180] @ (8017cb8 ) 8017c02: 6013 str r3, [r2, #0] ucMaxPriorityValue <<= ( uint8_t ) 0x01; 8017c04: 78fb ldrb r3, [r7, #3] 8017c06: b2db uxtb r3, r3 8017c08: 005b lsls r3, r3, #1 8017c0a: b2db uxtb r3, r3 8017c0c: 70fb strb r3, [r7, #3] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 8017c0e: 78fb ldrb r3, [r7, #3] 8017c10: b2db uxtb r3, r3 8017c12: f003 0380 and.w r3, r3, #128 @ 0x80 8017c16: 2b80 cmp r3, #128 @ 0x80 8017c18: d0ef beq.n 8017bfa #ifdef configPRIO_BITS { /* Check the FreeRTOS configuration that defines the number of priority bits matches the number of priority bits actually queried from the hardware. */ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); 8017c1a: 4b27 ldr r3, [pc, #156] @ (8017cb8 ) 8017c1c: 681b ldr r3, [r3, #0] 8017c1e: f1c3 0307 rsb r3, r3, #7 8017c22: 2b04 cmp r3, #4 8017c24: d00b beq.n 8017c3e __asm volatile 8017c26: f04f 0350 mov.w r3, #80 @ 0x50 8017c2a: f383 8811 msr BASEPRI, r3 8017c2e: f3bf 8f6f isb sy 8017c32: f3bf 8f4f dsb sy 8017c36: 60bb str r3, [r7, #8] } 8017c38: bf00 nop 8017c3a: bf00 nop 8017c3c: e7fd b.n 8017c3a } #endif /* Shift the priority group value back to its position within the AIRCR register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; 8017c3e: 4b1e ldr r3, [pc, #120] @ (8017cb8 ) 8017c40: 681b ldr r3, [r3, #0] 8017c42: 021b lsls r3, r3, #8 8017c44: 4a1c ldr r2, [pc, #112] @ (8017cb8 ) 8017c46: 6013 str r3, [r2, #0] ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; 8017c48: 4b1b ldr r3, [pc, #108] @ (8017cb8 ) 8017c4a: 681b ldr r3, [r3, #0] 8017c4c: f403 63e0 and.w r3, r3, #1792 @ 0x700 8017c50: 4a19 ldr r2, [pc, #100] @ (8017cb8 ) 8017c52: 6013 str r3, [r2, #0] /* Restore the clobbered interrupt priority register to its original value. */ *pucFirstUserPriorityRegister = ulOriginalPriority; 8017c54: 687b ldr r3, [r7, #4] 8017c56: b2da uxtb r2, r3 8017c58: 697b ldr r3, [r7, #20] 8017c5a: 701a strb r2, [r3, #0] } #endif /* conifgASSERT_DEFINED */ /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; 8017c5c: 4b17 ldr r3, [pc, #92] @ (8017cbc ) 8017c5e: 681b ldr r3, [r3, #0] 8017c60: 4a16 ldr r2, [pc, #88] @ (8017cbc ) 8017c62: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8017c66: 6013 str r3, [r2, #0] portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; 8017c68: 4b14 ldr r3, [pc, #80] @ (8017cbc ) 8017c6a: 681b ldr r3, [r3, #0] 8017c6c: 4a13 ldr r2, [pc, #76] @ (8017cbc ) 8017c6e: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000 8017c72: 6013 str r3, [r2, #0] /* Start the timer that generates the tick ISR. Interrupts are disabled here already. */ vPortSetupTimerInterrupt(); 8017c74: f000 f8da bl 8017e2c /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; 8017c78: 4b11 ldr r3, [pc, #68] @ (8017cc0 ) 8017c7a: 2200 movs r2, #0 8017c7c: 601a str r2, [r3, #0] /* Ensure the VFP is enabled - it should be anyway. */ vPortEnableVFP(); 8017c7e: f000 f8f9 bl 8017e74 /* Lazy save always. */ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; 8017c82: 4b10 ldr r3, [pc, #64] @ (8017cc4 ) 8017c84: 681b ldr r3, [r3, #0] 8017c86: 4a0f ldr r2, [pc, #60] @ (8017cc4 ) 8017c88: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000 8017c8c: 6013 str r3, [r2, #0] /* Start the first task. */ prvPortStartFirstTask(); 8017c8e: f7ff ff63 bl 8017b58 exit error function to prevent compiler warnings about a static function not being called in the case that the application writer overrides this functionality by defining configTASK_RETURN_ADDRESS. Call vTaskSwitchContext() so link time optimisation does not remove the symbol. */ vTaskSwitchContext(); 8017c92: f7fe fbd1 bl 8016438 prvTaskExitError(); 8017c96: f7ff ff1b bl 8017ad0 /* Should not get here! */ return 0; 8017c9a: 2300 movs r3, #0 } 8017c9c: 4618 mov r0, r3 8017c9e: 3718 adds r7, #24 8017ca0: 46bd mov sp, r7 8017ca2: bd80 pop {r7, pc} 8017ca4: e000ed00 .word 0xe000ed00 8017ca8: 410fc271 .word 0x410fc271 8017cac: 410fc270 .word 0x410fc270 8017cb0: e000e400 .word 0xe000e400 8017cb4: 24003024 .word 0x24003024 8017cb8: 24003028 .word 0x24003028 8017cbc: e000ed20 .word 0xe000ed20 8017cc0: 24000044 .word 0x24000044 8017cc4: e000ef34 .word 0xe000ef34 08017cc8 : configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) { 8017cc8: b480 push {r7} 8017cca: b083 sub sp, #12 8017ccc: af00 add r7, sp, #0 __asm volatile 8017cce: f04f 0350 mov.w r3, #80 @ 0x50 8017cd2: f383 8811 msr BASEPRI, r3 8017cd6: f3bf 8f6f isb sy 8017cda: f3bf 8f4f dsb sy 8017cde: 607b str r3, [r7, #4] } 8017ce0: bf00 nop portDISABLE_INTERRUPTS(); uxCriticalNesting++; 8017ce2: 4b10 ldr r3, [pc, #64] @ (8017d24 ) 8017ce4: 681b ldr r3, [r3, #0] 8017ce6: 3301 adds r3, #1 8017ce8: 4a0e ldr r2, [pc, #56] @ (8017d24 ) 8017cea: 6013 str r3, [r2, #0] /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if( uxCriticalNesting == 1 ) 8017cec: 4b0d ldr r3, [pc, #52] @ (8017d24 ) 8017cee: 681b ldr r3, [r3, #0] 8017cf0: 2b01 cmp r3, #1 8017cf2: d110 bne.n 8017d16 { configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); 8017cf4: 4b0c ldr r3, [pc, #48] @ (8017d28 ) 8017cf6: 681b ldr r3, [r3, #0] 8017cf8: b2db uxtb r3, r3 8017cfa: 2b00 cmp r3, #0 8017cfc: d00b beq.n 8017d16 __asm volatile 8017cfe: f04f 0350 mov.w r3, #80 @ 0x50 8017d02: f383 8811 msr BASEPRI, r3 8017d06: f3bf 8f6f isb sy 8017d0a: f3bf 8f4f dsb sy 8017d0e: 603b str r3, [r7, #0] } 8017d10: bf00 nop 8017d12: bf00 nop 8017d14: e7fd b.n 8017d12 } } 8017d16: bf00 nop 8017d18: 370c adds r7, #12 8017d1a: 46bd mov sp, r7 8017d1c: f85d 7b04 ldr.w r7, [sp], #4 8017d20: 4770 bx lr 8017d22: bf00 nop 8017d24: 24000044 .word 0x24000044 8017d28: e000ed04 .word 0xe000ed04 08017d2c : /*-----------------------------------------------------------*/ void vPortExitCritical( void ) { 8017d2c: b480 push {r7} 8017d2e: b083 sub sp, #12 8017d30: af00 add r7, sp, #0 configASSERT( uxCriticalNesting ); 8017d32: 4b12 ldr r3, [pc, #72] @ (8017d7c ) 8017d34: 681b ldr r3, [r3, #0] 8017d36: 2b00 cmp r3, #0 8017d38: d10b bne.n 8017d52 __asm volatile 8017d3a: f04f 0350 mov.w r3, #80 @ 0x50 8017d3e: f383 8811 msr BASEPRI, r3 8017d42: f3bf 8f6f isb sy 8017d46: f3bf 8f4f dsb sy 8017d4a: 607b str r3, [r7, #4] } 8017d4c: bf00 nop 8017d4e: bf00 nop 8017d50: e7fd b.n 8017d4e uxCriticalNesting--; 8017d52: 4b0a ldr r3, [pc, #40] @ (8017d7c ) 8017d54: 681b ldr r3, [r3, #0] 8017d56: 3b01 subs r3, #1 8017d58: 4a08 ldr r2, [pc, #32] @ (8017d7c ) 8017d5a: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) 8017d5c: 4b07 ldr r3, [pc, #28] @ (8017d7c ) 8017d5e: 681b ldr r3, [r3, #0] 8017d60: 2b00 cmp r3, #0 8017d62: d105 bne.n 8017d70 8017d64: 2300 movs r3, #0 8017d66: 603b str r3, [r7, #0] __asm volatile 8017d68: 683b ldr r3, [r7, #0] 8017d6a: f383 8811 msr BASEPRI, r3 } 8017d6e: bf00 nop { portENABLE_INTERRUPTS(); } } 8017d70: bf00 nop 8017d72: 370c adds r7, #12 8017d74: 46bd mov sp, r7 8017d76: f85d 7b04 ldr.w r7, [sp], #4 8017d7a: 4770 bx lr 8017d7c: 24000044 .word 0x24000044 08017d80 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile 8017d80: f3ef 8009 mrs r0, PSP 8017d84: f3bf 8f6f isb sy 8017d88: 4b15 ldr r3, [pc, #84] @ (8017de0 ) 8017d8a: 681a ldr r2, [r3, #0] 8017d8c: f01e 0f10 tst.w lr, #16 8017d90: bf08 it eq 8017d92: ed20 8a10 vstmdbeq r0!, {s16-s31} 8017d96: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017d9a: 6010 str r0, [r2, #0] 8017d9c: e92d 0009 stmdb sp!, {r0, r3} 8017da0: f04f 0050 mov.w r0, #80 @ 0x50 8017da4: f380 8811 msr BASEPRI, r0 8017da8: f3bf 8f4f dsb sy 8017dac: f3bf 8f6f isb sy 8017db0: f7fe fb42 bl 8016438 8017db4: f04f 0000 mov.w r0, #0 8017db8: f380 8811 msr BASEPRI, r0 8017dbc: bc09 pop {r0, r3} 8017dbe: 6819 ldr r1, [r3, #0] 8017dc0: 6808 ldr r0, [r1, #0] 8017dc2: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017dc6: f01e 0f10 tst.w lr, #16 8017dca: bf08 it eq 8017dcc: ecb0 8a10 vldmiaeq r0!, {s16-s31} 8017dd0: f380 8809 msr PSP, r0 8017dd4: f3bf 8f6f isb sy 8017dd8: 4770 bx lr 8017dda: bf00 nop 8017ddc: f3af 8000 nop.w 08017de0 : 8017de0: 240029f8 .word 0x240029f8 " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ); } 8017de4: bf00 nop 8017de6: bf00 nop 08017de8 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { 8017de8: b580 push {r7, lr} 8017dea: b082 sub sp, #8 8017dec: af00 add r7, sp, #0 __asm volatile 8017dee: f04f 0350 mov.w r3, #80 @ 0x50 8017df2: f383 8811 msr BASEPRI, r3 8017df6: f3bf 8f6f isb sy 8017dfa: f3bf 8f4f dsb sy 8017dfe: 607b str r3, [r7, #4] } 8017e00: bf00 nop save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) 8017e02: f7fe fa5f bl 80162c4 8017e06: 4603 mov r3, r0 8017e08: 2b00 cmp r3, #0 8017e0a: d003 beq.n 8017e14 { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; 8017e0c: 4b06 ldr r3, [pc, #24] @ (8017e28 ) 8017e0e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8017e12: 601a str r2, [r3, #0] 8017e14: 2300 movs r3, #0 8017e16: 603b str r3, [r7, #0] __asm volatile 8017e18: 683b ldr r3, [r7, #0] 8017e1a: f383 8811 msr BASEPRI, r3 } 8017e1e: bf00 nop } } portENABLE_INTERRUPTS(); } 8017e20: bf00 nop 8017e22: 3708 adds r7, #8 8017e24: 46bd mov sp, r7 8017e26: bd80 pop {r7, pc} 8017e28: e000ed04 .word 0xe000ed04 08017e2c : /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) { 8017e2c: b480 push {r7} 8017e2e: af00 add r7, sp, #0 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and clear the SysTick. */ portNVIC_SYSTICK_CTRL_REG = 0UL; 8017e30: 4b0b ldr r3, [pc, #44] @ (8017e60 ) 8017e32: 2200 movs r2, #0 8017e34: 601a str r2, [r3, #0] portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; 8017e36: 4b0b ldr r3, [pc, #44] @ (8017e64 ) 8017e38: 2200 movs r2, #0 8017e3a: 601a str r2, [r3, #0] /* Configure SysTick to interrupt at the requested rate. */ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; 8017e3c: 4b0a ldr r3, [pc, #40] @ (8017e68 ) 8017e3e: 681b ldr r3, [r3, #0] 8017e40: 4a0a ldr r2, [pc, #40] @ (8017e6c ) 8017e42: fba2 2303 umull r2, r3, r2, r3 8017e46: 099b lsrs r3, r3, #6 8017e48: 4a09 ldr r2, [pc, #36] @ (8017e70 ) 8017e4a: 3b01 subs r3, #1 8017e4c: 6013 str r3, [r2, #0] portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); 8017e4e: 4b04 ldr r3, [pc, #16] @ (8017e60 ) 8017e50: 2207 movs r2, #7 8017e52: 601a str r2, [r3, #0] } 8017e54: bf00 nop 8017e56: 46bd mov sp, r7 8017e58: f85d 7b04 ldr.w r7, [sp], #4 8017e5c: 4770 bx lr 8017e5e: bf00 nop 8017e60: e000e010 .word 0xe000e010 8017e64: e000e018 .word 0xe000e018 8017e68: 24000034 .word 0x24000034 8017e6c: 10624dd3 .word 0x10624dd3 8017e70: e000e014 .word 0xe000e014 08017e74 : /*-----------------------------------------------------------*/ /* This is a naked function. */ static void vPortEnableVFP( void ) { __asm volatile 8017e74: f8df 000c ldr.w r0, [pc, #12] @ 8017e84 8017e78: 6801 ldr r1, [r0, #0] 8017e7a: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 8017e7e: 6001 str r1, [r0, #0] 8017e80: 4770 bx lr " \n" " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ " str r1, [r0] \n" " bx r14 " ); } 8017e82: bf00 nop 8017e84: e000ed88 .word 0xe000ed88 08017e88 : /*-----------------------------------------------------------*/ #if( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { 8017e88: b480 push {r7} 8017e8a: b085 sub sp, #20 8017e8c: af00 add r7, sp, #0 uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); 8017e8e: f3ef 8305 mrs r3, IPSR 8017e92: 60fb str r3, [r7, #12] /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) 8017e94: 68fb ldr r3, [r7, #12] 8017e96: 2b0f cmp r3, #15 8017e98: d915 bls.n 8017ec6 { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; 8017e9a: 4a18 ldr r2, [pc, #96] @ (8017efc ) 8017e9c: 68fb ldr r3, [r7, #12] 8017e9e: 4413 add r3, r2 8017ea0: 781b ldrb r3, [r3, #0] 8017ea2: 72fb strb r3, [r7, #11] interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); 8017ea4: 4b16 ldr r3, [pc, #88] @ (8017f00 ) 8017ea6: 781b ldrb r3, [r3, #0] 8017ea8: 7afa ldrb r2, [r7, #11] 8017eaa: 429a cmp r2, r3 8017eac: d20b bcs.n 8017ec6 __asm volatile 8017eae: f04f 0350 mov.w r3, #80 @ 0x50 8017eb2: f383 8811 msr BASEPRI, r3 8017eb6: f3bf 8f6f isb sy 8017eba: f3bf 8f4f dsb sy 8017ebe: 607b str r3, [r7, #4] } 8017ec0: bf00 nop 8017ec2: bf00 nop 8017ec4: e7fd b.n 8017ec2 configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); 8017ec6: 4b0f ldr r3, [pc, #60] @ (8017f04 ) 8017ec8: 681b ldr r3, [r3, #0] 8017eca: f403 62e0 and.w r2, r3, #1792 @ 0x700 8017ece: 4b0e ldr r3, [pc, #56] @ (8017f08 ) 8017ed0: 681b ldr r3, [r3, #0] 8017ed2: 429a cmp r2, r3 8017ed4: d90b bls.n 8017eee __asm volatile 8017ed6: f04f 0350 mov.w r3, #80 @ 0x50 8017eda: f383 8811 msr BASEPRI, r3 8017ede: f3bf 8f6f isb sy 8017ee2: f3bf 8f4f dsb sy 8017ee6: 603b str r3, [r7, #0] } 8017ee8: bf00 nop 8017eea: bf00 nop 8017eec: e7fd b.n 8017eea } 8017eee: bf00 nop 8017ef0: 3714 adds r7, #20 8017ef2: 46bd mov sp, r7 8017ef4: f85d 7b04 ldr.w r7, [sp], #4 8017ef8: 4770 bx lr 8017efa: bf00 nop 8017efc: e000e3f0 .word 0xe000e3f0 8017f00: 24003024 .word 0x24003024 8017f04: e000ed0c .word 0xe000ed0c 8017f08: 24003028 .word 0x24003028 08017f0c : static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ void *pvPortMalloc( size_t xWantedSize ) { 8017f0c: b580 push {r7, lr} 8017f0e: b08a sub sp, #40 @ 0x28 8017f10: af00 add r7, sp, #0 8017f12: 6078 str r0, [r7, #4] BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; void *pvReturn = NULL; 8017f14: 2300 movs r3, #0 8017f16: 61fb str r3, [r7, #28] vTaskSuspendAll(); 8017f18: f7fe f918 bl 801614c { /* If this is the first call to malloc then the heap will require initialisation to setup the list of free blocks. */ if( pxEnd == NULL ) 8017f1c: 4b5c ldr r3, [pc, #368] @ (8018090 ) 8017f1e: 681b ldr r3, [r3, #0] 8017f20: 2b00 cmp r3, #0 8017f22: d101 bne.n 8017f28 { prvHeapInit(); 8017f24: f000 f924 bl 8018170 /* Check the requested block size is not so large that the top bit is set. The top bit of the block size member of the BlockLink_t structure is used to determine who owns the block - the application or the kernel, so it must be free. */ if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) 8017f28: 4b5a ldr r3, [pc, #360] @ (8018094 ) 8017f2a: 681a ldr r2, [r3, #0] 8017f2c: 687b ldr r3, [r7, #4] 8017f2e: 4013 ands r3, r2 8017f30: 2b00 cmp r3, #0 8017f32: f040 8095 bne.w 8018060 { /* The wanted size is increased so it can contain a BlockLink_t structure in addition to the requested amount of bytes. */ if( xWantedSize > 0 ) 8017f36: 687b ldr r3, [r7, #4] 8017f38: 2b00 cmp r3, #0 8017f3a: d01e beq.n 8017f7a { xWantedSize += xHeapStructSize; 8017f3c: 2208 movs r2, #8 8017f3e: 687b ldr r3, [r7, #4] 8017f40: 4413 add r3, r2 8017f42: 607b str r3, [r7, #4] /* Ensure that blocks are always aligned to the required number of bytes. */ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) 8017f44: 687b ldr r3, [r7, #4] 8017f46: f003 0307 and.w r3, r3, #7 8017f4a: 2b00 cmp r3, #0 8017f4c: d015 beq.n 8017f7a { /* Byte alignment required. */ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); 8017f4e: 687b ldr r3, [r7, #4] 8017f50: f023 0307 bic.w r3, r3, #7 8017f54: 3308 adds r3, #8 8017f56: 607b str r3, [r7, #4] configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); 8017f58: 687b ldr r3, [r7, #4] 8017f5a: f003 0307 and.w r3, r3, #7 8017f5e: 2b00 cmp r3, #0 8017f60: d00b beq.n 8017f7a __asm volatile 8017f62: f04f 0350 mov.w r3, #80 @ 0x50 8017f66: f383 8811 msr BASEPRI, r3 8017f6a: f3bf 8f6f isb sy 8017f6e: f3bf 8f4f dsb sy 8017f72: 617b str r3, [r7, #20] } 8017f74: bf00 nop 8017f76: bf00 nop 8017f78: e7fd b.n 8017f76 else { mtCOVERAGE_TEST_MARKER(); } if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) 8017f7a: 687b ldr r3, [r7, #4] 8017f7c: 2b00 cmp r3, #0 8017f7e: d06f beq.n 8018060 8017f80: 4b45 ldr r3, [pc, #276] @ (8018098 ) 8017f82: 681b ldr r3, [r3, #0] 8017f84: 687a ldr r2, [r7, #4] 8017f86: 429a cmp r2, r3 8017f88: d86a bhi.n 8018060 { /* Traverse the list from the start (lowest address) block until one of adequate size is found. */ pxPreviousBlock = &xStart; 8017f8a: 4b44 ldr r3, [pc, #272] @ (801809c ) 8017f8c: 623b str r3, [r7, #32] pxBlock = xStart.pxNextFreeBlock; 8017f8e: 4b43 ldr r3, [pc, #268] @ (801809c ) 8017f90: 681b ldr r3, [r3, #0] 8017f92: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 8017f94: e004 b.n 8017fa0 { pxPreviousBlock = pxBlock; 8017f96: 6a7b ldr r3, [r7, #36] @ 0x24 8017f98: 623b str r3, [r7, #32] pxBlock = pxBlock->pxNextFreeBlock; 8017f9a: 6a7b ldr r3, [r7, #36] @ 0x24 8017f9c: 681b ldr r3, [r3, #0] 8017f9e: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 8017fa0: 6a7b ldr r3, [r7, #36] @ 0x24 8017fa2: 685b ldr r3, [r3, #4] 8017fa4: 687a ldr r2, [r7, #4] 8017fa6: 429a cmp r2, r3 8017fa8: d903 bls.n 8017fb2 8017faa: 6a7b ldr r3, [r7, #36] @ 0x24 8017fac: 681b ldr r3, [r3, #0] 8017fae: 2b00 cmp r3, #0 8017fb0: d1f1 bne.n 8017f96 } /* If the end marker was reached then a block of adequate size was not found. */ if( pxBlock != pxEnd ) 8017fb2: 4b37 ldr r3, [pc, #220] @ (8018090 ) 8017fb4: 681b ldr r3, [r3, #0] 8017fb6: 6a7a ldr r2, [r7, #36] @ 0x24 8017fb8: 429a cmp r2, r3 8017fba: d051 beq.n 8018060 { /* Return the memory space pointed to - jumping over the BlockLink_t structure at its start. */ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); 8017fbc: 6a3b ldr r3, [r7, #32] 8017fbe: 681b ldr r3, [r3, #0] 8017fc0: 2208 movs r2, #8 8017fc2: 4413 add r3, r2 8017fc4: 61fb str r3, [r7, #28] /* This block is being returned for use so must be taken out of the list of free blocks. */ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; 8017fc6: 6a7b ldr r3, [r7, #36] @ 0x24 8017fc8: 681a ldr r2, [r3, #0] 8017fca: 6a3b ldr r3, [r7, #32] 8017fcc: 601a str r2, [r3, #0] /* If the block is larger than required it can be split into two. */ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) 8017fce: 6a7b ldr r3, [r7, #36] @ 0x24 8017fd0: 685a ldr r2, [r3, #4] 8017fd2: 687b ldr r3, [r7, #4] 8017fd4: 1ad2 subs r2, r2, r3 8017fd6: 2308 movs r3, #8 8017fd8: 005b lsls r3, r3, #1 8017fda: 429a cmp r2, r3 8017fdc: d920 bls.n 8018020 { /* This block is to be split into two. Create a new block following the number of bytes requested. The void cast is used to prevent byte alignment warnings from the compiler. */ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); 8017fde: 6a7a ldr r2, [r7, #36] @ 0x24 8017fe0: 687b ldr r3, [r7, #4] 8017fe2: 4413 add r3, r2 8017fe4: 61bb str r3, [r7, #24] configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); 8017fe6: 69bb ldr r3, [r7, #24] 8017fe8: f003 0307 and.w r3, r3, #7 8017fec: 2b00 cmp r3, #0 8017fee: d00b beq.n 8018008 __asm volatile 8017ff0: f04f 0350 mov.w r3, #80 @ 0x50 8017ff4: f383 8811 msr BASEPRI, r3 8017ff8: f3bf 8f6f isb sy 8017ffc: f3bf 8f4f dsb sy 8018000: 613b str r3, [r7, #16] } 8018002: bf00 nop 8018004: bf00 nop 8018006: e7fd b.n 8018004 /* Calculate the sizes of two blocks split from the single block. */ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; 8018008: 6a7b ldr r3, [r7, #36] @ 0x24 801800a: 685a ldr r2, [r3, #4] 801800c: 687b ldr r3, [r7, #4] 801800e: 1ad2 subs r2, r2, r3 8018010: 69bb ldr r3, [r7, #24] 8018012: 605a str r2, [r3, #4] pxBlock->xBlockSize = xWantedSize; 8018014: 6a7b ldr r3, [r7, #36] @ 0x24 8018016: 687a ldr r2, [r7, #4] 8018018: 605a str r2, [r3, #4] /* Insert the new block into the list of free blocks. */ prvInsertBlockIntoFreeList( pxNewBlockLink ); 801801a: 69b8 ldr r0, [r7, #24] 801801c: f000 f90a bl 8018234 else { mtCOVERAGE_TEST_MARKER(); } xFreeBytesRemaining -= pxBlock->xBlockSize; 8018020: 4b1d ldr r3, [pc, #116] @ (8018098 ) 8018022: 681a ldr r2, [r3, #0] 8018024: 6a7b ldr r3, [r7, #36] @ 0x24 8018026: 685b ldr r3, [r3, #4] 8018028: 1ad3 subs r3, r2, r3 801802a: 4a1b ldr r2, [pc, #108] @ (8018098 ) 801802c: 6013 str r3, [r2, #0] if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) 801802e: 4b1a ldr r3, [pc, #104] @ (8018098 ) 8018030: 681a ldr r2, [r3, #0] 8018032: 4b1b ldr r3, [pc, #108] @ (80180a0 ) 8018034: 681b ldr r3, [r3, #0] 8018036: 429a cmp r2, r3 8018038: d203 bcs.n 8018042 { xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; 801803a: 4b17 ldr r3, [pc, #92] @ (8018098 ) 801803c: 681b ldr r3, [r3, #0] 801803e: 4a18 ldr r2, [pc, #96] @ (80180a0 ) 8018040: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } /* The block is being returned - it is allocated and owned by the application and has no "next" block. */ pxBlock->xBlockSize |= xBlockAllocatedBit; 8018042: 6a7b ldr r3, [r7, #36] @ 0x24 8018044: 685a ldr r2, [r3, #4] 8018046: 4b13 ldr r3, [pc, #76] @ (8018094 ) 8018048: 681b ldr r3, [r3, #0] 801804a: 431a orrs r2, r3 801804c: 6a7b ldr r3, [r7, #36] @ 0x24 801804e: 605a str r2, [r3, #4] pxBlock->pxNextFreeBlock = NULL; 8018050: 6a7b ldr r3, [r7, #36] @ 0x24 8018052: 2200 movs r2, #0 8018054: 601a str r2, [r3, #0] xNumberOfSuccessfulAllocations++; 8018056: 4b13 ldr r3, [pc, #76] @ (80180a4 ) 8018058: 681b ldr r3, [r3, #0] 801805a: 3301 adds r3, #1 801805c: 4a11 ldr r2, [pc, #68] @ (80180a4 ) 801805e: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } traceMALLOC( pvReturn, xWantedSize ); } ( void ) xTaskResumeAll(); 8018060: f7fe f882 bl 8016168 mtCOVERAGE_TEST_MARKER(); } } #endif configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); 8018064: 69fb ldr r3, [r7, #28] 8018066: f003 0307 and.w r3, r3, #7 801806a: 2b00 cmp r3, #0 801806c: d00b beq.n 8018086 __asm volatile 801806e: f04f 0350 mov.w r3, #80 @ 0x50 8018072: f383 8811 msr BASEPRI, r3 8018076: f3bf 8f6f isb sy 801807a: f3bf 8f4f dsb sy 801807e: 60fb str r3, [r7, #12] } 8018080: bf00 nop 8018082: bf00 nop 8018084: e7fd b.n 8018082 return pvReturn; 8018086: 69fb ldr r3, [r7, #28] } 8018088: 4618 mov r0, r3 801808a: 3728 adds r7, #40 @ 0x28 801808c: 46bd mov sp, r7 801808e: bd80 pop {r7, pc} 8018090: 24013034 .word 0x24013034 8018094: 24013048 .word 0x24013048 8018098: 24013038 .word 0x24013038 801809c: 2401302c .word 0x2401302c 80180a0: 2401303c .word 0x2401303c 80180a4: 24013040 .word 0x24013040 080180a8 : /*-----------------------------------------------------------*/ void vPortFree( void *pv ) { 80180a8: b580 push {r7, lr} 80180aa: b086 sub sp, #24 80180ac: af00 add r7, sp, #0 80180ae: 6078 str r0, [r7, #4] uint8_t *puc = ( uint8_t * ) pv; 80180b0: 687b ldr r3, [r7, #4] 80180b2: 617b str r3, [r7, #20] BlockLink_t *pxLink; if( pv != NULL ) 80180b4: 687b ldr r3, [r7, #4] 80180b6: 2b00 cmp r3, #0 80180b8: d04f beq.n 801815a { /* The memory being freed will have an BlockLink_t structure immediately before it. */ puc -= xHeapStructSize; 80180ba: 2308 movs r3, #8 80180bc: 425b negs r3, r3 80180be: 697a ldr r2, [r7, #20] 80180c0: 4413 add r3, r2 80180c2: 617b str r3, [r7, #20] /* This casting is to keep the compiler from issuing warnings. */ pxLink = ( void * ) puc; 80180c4: 697b ldr r3, [r7, #20] 80180c6: 613b str r3, [r7, #16] /* Check the block is actually allocated. */ configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); 80180c8: 693b ldr r3, [r7, #16] 80180ca: 685a ldr r2, [r3, #4] 80180cc: 4b25 ldr r3, [pc, #148] @ (8018164 ) 80180ce: 681b ldr r3, [r3, #0] 80180d0: 4013 ands r3, r2 80180d2: 2b00 cmp r3, #0 80180d4: d10b bne.n 80180ee __asm volatile 80180d6: f04f 0350 mov.w r3, #80 @ 0x50 80180da: f383 8811 msr BASEPRI, r3 80180de: f3bf 8f6f isb sy 80180e2: f3bf 8f4f dsb sy 80180e6: 60fb str r3, [r7, #12] } 80180e8: bf00 nop 80180ea: bf00 nop 80180ec: e7fd b.n 80180ea configASSERT( pxLink->pxNextFreeBlock == NULL ); 80180ee: 693b ldr r3, [r7, #16] 80180f0: 681b ldr r3, [r3, #0] 80180f2: 2b00 cmp r3, #0 80180f4: d00b beq.n 801810e __asm volatile 80180f6: f04f 0350 mov.w r3, #80 @ 0x50 80180fa: f383 8811 msr BASEPRI, r3 80180fe: f3bf 8f6f isb sy 8018102: f3bf 8f4f dsb sy 8018106: 60bb str r3, [r7, #8] } 8018108: bf00 nop 801810a: bf00 nop 801810c: e7fd b.n 801810a if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) 801810e: 693b ldr r3, [r7, #16] 8018110: 685a ldr r2, [r3, #4] 8018112: 4b14 ldr r3, [pc, #80] @ (8018164 ) 8018114: 681b ldr r3, [r3, #0] 8018116: 4013 ands r3, r2 8018118: 2b00 cmp r3, #0 801811a: d01e beq.n 801815a { if( pxLink->pxNextFreeBlock == NULL ) 801811c: 693b ldr r3, [r7, #16] 801811e: 681b ldr r3, [r3, #0] 8018120: 2b00 cmp r3, #0 8018122: d11a bne.n 801815a { /* The block is being returned to the heap - it is no longer allocated. */ pxLink->xBlockSize &= ~xBlockAllocatedBit; 8018124: 693b ldr r3, [r7, #16] 8018126: 685a ldr r2, [r3, #4] 8018128: 4b0e ldr r3, [pc, #56] @ (8018164 ) 801812a: 681b ldr r3, [r3, #0] 801812c: 43db mvns r3, r3 801812e: 401a ands r2, r3 8018130: 693b ldr r3, [r7, #16] 8018132: 605a str r2, [r3, #4] vTaskSuspendAll(); 8018134: f7fe f80a bl 801614c { /* Add this block to the list of free blocks. */ xFreeBytesRemaining += pxLink->xBlockSize; 8018138: 693b ldr r3, [r7, #16] 801813a: 685a ldr r2, [r3, #4] 801813c: 4b0a ldr r3, [pc, #40] @ (8018168 ) 801813e: 681b ldr r3, [r3, #0] 8018140: 4413 add r3, r2 8018142: 4a09 ldr r2, [pc, #36] @ (8018168 ) 8018144: 6013 str r3, [r2, #0] traceFREE( pv, pxLink->xBlockSize ); prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); 8018146: 6938 ldr r0, [r7, #16] 8018148: f000 f874 bl 8018234 xNumberOfSuccessfulFrees++; 801814c: 4b07 ldr r3, [pc, #28] @ (801816c ) 801814e: 681b ldr r3, [r3, #0] 8018150: 3301 adds r3, #1 8018152: 4a06 ldr r2, [pc, #24] @ (801816c ) 8018154: 6013 str r3, [r2, #0] } ( void ) xTaskResumeAll(); 8018156: f7fe f807 bl 8016168 else { mtCOVERAGE_TEST_MARKER(); } } } 801815a: bf00 nop 801815c: 3718 adds r7, #24 801815e: 46bd mov sp, r7 8018160: bd80 pop {r7, pc} 8018162: bf00 nop 8018164: 24013048 .word 0x24013048 8018168: 24013038 .word 0x24013038 801816c: 24013044 .word 0x24013044 08018170 : /* This just exists to keep the linker quiet. */ } /*-----------------------------------------------------------*/ static void prvHeapInit( void ) { 8018170: b480 push {r7} 8018172: b085 sub sp, #20 8018174: af00 add r7, sp, #0 BlockLink_t *pxFirstFreeBlock; uint8_t *pucAlignedHeap; size_t uxAddress; size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; 8018176: f44f 3380 mov.w r3, #65536 @ 0x10000 801817a: 60bb str r3, [r7, #8] /* Ensure the heap starts on a correctly aligned boundary. */ uxAddress = ( size_t ) ucHeap; 801817c: 4b27 ldr r3, [pc, #156] @ (801821c ) 801817e: 60fb str r3, [r7, #12] if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) 8018180: 68fb ldr r3, [r7, #12] 8018182: f003 0307 and.w r3, r3, #7 8018186: 2b00 cmp r3, #0 8018188: d00c beq.n 80181a4 { uxAddress += ( portBYTE_ALIGNMENT - 1 ); 801818a: 68fb ldr r3, [r7, #12] 801818c: 3307 adds r3, #7 801818e: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 8018190: 68fb ldr r3, [r7, #12] 8018192: f023 0307 bic.w r3, r3, #7 8018196: 60fb str r3, [r7, #12] xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; 8018198: 68ba ldr r2, [r7, #8] 801819a: 68fb ldr r3, [r7, #12] 801819c: 1ad3 subs r3, r2, r3 801819e: 4a1f ldr r2, [pc, #124] @ (801821c ) 80181a0: 4413 add r3, r2 80181a2: 60bb str r3, [r7, #8] } pucAlignedHeap = ( uint8_t * ) uxAddress; 80181a4: 68fb ldr r3, [r7, #12] 80181a6: 607b str r3, [r7, #4] /* xStart is used to hold a pointer to the first item in the list of free blocks. The void cast is used to prevent compiler warnings. */ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; 80181a8: 4a1d ldr r2, [pc, #116] @ (8018220 ) 80181aa: 687b ldr r3, [r7, #4] 80181ac: 6013 str r3, [r2, #0] xStart.xBlockSize = ( size_t ) 0; 80181ae: 4b1c ldr r3, [pc, #112] @ (8018220 ) 80181b0: 2200 movs r2, #0 80181b2: 605a str r2, [r3, #4] /* pxEnd is used to mark the end of the list of free blocks and is inserted at the end of the heap space. */ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; 80181b4: 687b ldr r3, [r7, #4] 80181b6: 68ba ldr r2, [r7, #8] 80181b8: 4413 add r3, r2 80181ba: 60fb str r3, [r7, #12] uxAddress -= xHeapStructSize; 80181bc: 2208 movs r2, #8 80181be: 68fb ldr r3, [r7, #12] 80181c0: 1a9b subs r3, r3, r2 80181c2: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 80181c4: 68fb ldr r3, [r7, #12] 80181c6: f023 0307 bic.w r3, r3, #7 80181ca: 60fb str r3, [r7, #12] pxEnd = ( void * ) uxAddress; 80181cc: 68fb ldr r3, [r7, #12] 80181ce: 4a15 ldr r2, [pc, #84] @ (8018224 ) 80181d0: 6013 str r3, [r2, #0] pxEnd->xBlockSize = 0; 80181d2: 4b14 ldr r3, [pc, #80] @ (8018224 ) 80181d4: 681b ldr r3, [r3, #0] 80181d6: 2200 movs r2, #0 80181d8: 605a str r2, [r3, #4] pxEnd->pxNextFreeBlock = NULL; 80181da: 4b12 ldr r3, [pc, #72] @ (8018224 ) 80181dc: 681b ldr r3, [r3, #0] 80181de: 2200 movs r2, #0 80181e0: 601a str r2, [r3, #0] /* To start with there is a single free block that is sized to take up the entire heap space, minus the space taken by pxEnd. */ pxFirstFreeBlock = ( void * ) pucAlignedHeap; 80181e2: 687b ldr r3, [r7, #4] 80181e4: 603b str r3, [r7, #0] pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; 80181e6: 683b ldr r3, [r7, #0] 80181e8: 68fa ldr r2, [r7, #12] 80181ea: 1ad2 subs r2, r2, r3 80181ec: 683b ldr r3, [r7, #0] 80181ee: 605a str r2, [r3, #4] pxFirstFreeBlock->pxNextFreeBlock = pxEnd; 80181f0: 4b0c ldr r3, [pc, #48] @ (8018224 ) 80181f2: 681a ldr r2, [r3, #0] 80181f4: 683b ldr r3, [r7, #0] 80181f6: 601a str r2, [r3, #0] /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 80181f8: 683b ldr r3, [r7, #0] 80181fa: 685b ldr r3, [r3, #4] 80181fc: 4a0a ldr r2, [pc, #40] @ (8018228 ) 80181fe: 6013 str r3, [r2, #0] xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8018200: 683b ldr r3, [r7, #0] 8018202: 685b ldr r3, [r3, #4] 8018204: 4a09 ldr r2, [pc, #36] @ (801822c ) 8018206: 6013 str r3, [r2, #0] /* Work out the position of the top bit in a size_t variable. */ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); 8018208: 4b09 ldr r3, [pc, #36] @ (8018230 ) 801820a: f04f 4200 mov.w r2, #2147483648 @ 0x80000000 801820e: 601a str r2, [r3, #0] } 8018210: bf00 nop 8018212: 3714 adds r7, #20 8018214: 46bd mov sp, r7 8018216: f85d 7b04 ldr.w r7, [sp], #4 801821a: 4770 bx lr 801821c: 2400302c .word 0x2400302c 8018220: 2401302c .word 0x2401302c 8018224: 24013034 .word 0x24013034 8018228: 2401303c .word 0x2401303c 801822c: 24013038 .word 0x24013038 8018230: 24013048 .word 0x24013048 08018234 : /*-----------------------------------------------------------*/ static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) { 8018234: b480 push {r7} 8018236: b085 sub sp, #20 8018238: af00 add r7, sp, #0 801823a: 6078 str r0, [r7, #4] BlockLink_t *pxIterator; uint8_t *puc; /* Iterate through the list until a block is found that has a higher address than the block being inserted. */ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) 801823c: 4b28 ldr r3, [pc, #160] @ (80182e0 ) 801823e: 60fb str r3, [r7, #12] 8018240: e002 b.n 8018248 8018242: 68fb ldr r3, [r7, #12] 8018244: 681b ldr r3, [r3, #0] 8018246: 60fb str r3, [r7, #12] 8018248: 68fb ldr r3, [r7, #12] 801824a: 681b ldr r3, [r3, #0] 801824c: 687a ldr r2, [r7, #4] 801824e: 429a cmp r2, r3 8018250: d8f7 bhi.n 8018242 /* Nothing to do here, just iterate to the right position. */ } /* Do the block being inserted, and the block it is being inserted after make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; 8018252: 68fb ldr r3, [r7, #12] 8018254: 60bb str r3, [r7, #8] if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) 8018256: 68fb ldr r3, [r7, #12] 8018258: 685b ldr r3, [r3, #4] 801825a: 68ba ldr r2, [r7, #8] 801825c: 4413 add r3, r2 801825e: 687a ldr r2, [r7, #4] 8018260: 429a cmp r2, r3 8018262: d108 bne.n 8018276 { pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 8018264: 68fb ldr r3, [r7, #12] 8018266: 685a ldr r2, [r3, #4] 8018268: 687b ldr r3, [r7, #4] 801826a: 685b ldr r3, [r3, #4] 801826c: 441a add r2, r3 801826e: 68fb ldr r3, [r7, #12] 8018270: 605a str r2, [r3, #4] pxBlockToInsert = pxIterator; 8018272: 68fb ldr r3, [r7, #12] 8018274: 607b str r3, [r7, #4] mtCOVERAGE_TEST_MARKER(); } /* Do the block being inserted, and the block it is being inserted before make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; 8018276: 687b ldr r3, [r7, #4] 8018278: 60bb str r3, [r7, #8] if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 801827a: 687b ldr r3, [r7, #4] 801827c: 685b ldr r3, [r3, #4] 801827e: 68ba ldr r2, [r7, #8] 8018280: 441a add r2, r3 8018282: 68fb ldr r3, [r7, #12] 8018284: 681b ldr r3, [r3, #0] 8018286: 429a cmp r2, r3 8018288: d118 bne.n 80182bc { if( pxIterator->pxNextFreeBlock != pxEnd ) 801828a: 68fb ldr r3, [r7, #12] 801828c: 681a ldr r2, [r3, #0] 801828e: 4b15 ldr r3, [pc, #84] @ (80182e4 ) 8018290: 681b ldr r3, [r3, #0] 8018292: 429a cmp r2, r3 8018294: d00d beq.n 80182b2 { /* Form one big block from the two blocks. */ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; 8018296: 687b ldr r3, [r7, #4] 8018298: 685a ldr r2, [r3, #4] 801829a: 68fb ldr r3, [r7, #12] 801829c: 681b ldr r3, [r3, #0] 801829e: 685b ldr r3, [r3, #4] 80182a0: 441a add r2, r3 80182a2: 687b ldr r3, [r7, #4] 80182a4: 605a str r2, [r3, #4] pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; 80182a6: 68fb ldr r3, [r7, #12] 80182a8: 681b ldr r3, [r3, #0] 80182aa: 681a ldr r2, [r3, #0] 80182ac: 687b ldr r3, [r7, #4] 80182ae: 601a str r2, [r3, #0] 80182b0: e008 b.n 80182c4 } else { pxBlockToInsert->pxNextFreeBlock = pxEnd; 80182b2: 4b0c ldr r3, [pc, #48] @ (80182e4 ) 80182b4: 681a ldr r2, [r3, #0] 80182b6: 687b ldr r3, [r7, #4] 80182b8: 601a str r2, [r3, #0] 80182ba: e003 b.n 80182c4 } } else { pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; 80182bc: 68fb ldr r3, [r7, #12] 80182be: 681a ldr r2, [r3, #0] 80182c0: 687b ldr r3, [r7, #4] 80182c2: 601a str r2, [r3, #0] /* If the block being inserted plugged a gab, so was merged with the block before and the block after, then it's pxNextFreeBlock pointer will have already been set, and should not be set here as that would make it point to itself. */ if( pxIterator != pxBlockToInsert ) 80182c4: 68fa ldr r2, [r7, #12] 80182c6: 687b ldr r3, [r7, #4] 80182c8: 429a cmp r2, r3 80182ca: d002 beq.n 80182d2 { pxIterator->pxNextFreeBlock = pxBlockToInsert; 80182cc: 68fb ldr r3, [r7, #12] 80182ce: 687a ldr r2, [r7, #4] 80182d0: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 80182d2: bf00 nop 80182d4: 3714 adds r7, #20 80182d6: 46bd mov sp, r7 80182d8: f85d 7b04 ldr.w r7, [sp], #4 80182dc: 4770 bx lr 80182de: bf00 nop 80182e0: 2401302c .word 0x2401302c 80182e4: 24013034 .word 0x24013034 080182e8 : 80182e8: 4402 add r2, r0 80182ea: 4603 mov r3, r0 80182ec: 4293 cmp r3, r2 80182ee: d100 bne.n 80182f2 80182f0: 4770 bx lr 80182f2: f803 1b01 strb.w r1, [r3], #1 80182f6: e7f9 b.n 80182ec 080182f8 <_reclaim_reent>: 80182f8: 4b29 ldr r3, [pc, #164] @ (80183a0 <_reclaim_reent+0xa8>) 80182fa: 681b ldr r3, [r3, #0] 80182fc: 4283 cmp r3, r0 80182fe: b570 push {r4, r5, r6, lr} 8018300: 4604 mov r4, r0 8018302: d04b beq.n 801839c <_reclaim_reent+0xa4> 8018304: 69c3 ldr r3, [r0, #28] 8018306: b1ab cbz r3, 8018334 <_reclaim_reent+0x3c> 8018308: 68db ldr r3, [r3, #12] 801830a: b16b cbz r3, 8018328 <_reclaim_reent+0x30> 801830c: 2500 movs r5, #0 801830e: 69e3 ldr r3, [r4, #28] 8018310: 68db ldr r3, [r3, #12] 8018312: 5959 ldr r1, [r3, r5] 8018314: 2900 cmp r1, #0 8018316: d13b bne.n 8018390 <_reclaim_reent+0x98> 8018318: 3504 adds r5, #4 801831a: 2d80 cmp r5, #128 @ 0x80 801831c: d1f7 bne.n 801830e <_reclaim_reent+0x16> 801831e: 69e3 ldr r3, [r4, #28] 8018320: 4620 mov r0, r4 8018322: 68d9 ldr r1, [r3, #12] 8018324: f000 f878 bl 8018418 <_free_r> 8018328: 69e3 ldr r3, [r4, #28] 801832a: 6819 ldr r1, [r3, #0] 801832c: b111 cbz r1, 8018334 <_reclaim_reent+0x3c> 801832e: 4620 mov r0, r4 8018330: f000 f872 bl 8018418 <_free_r> 8018334: 6961 ldr r1, [r4, #20] 8018336: b111 cbz r1, 801833e <_reclaim_reent+0x46> 8018338: 4620 mov r0, r4 801833a: f000 f86d bl 8018418 <_free_r> 801833e: 69e1 ldr r1, [r4, #28] 8018340: b111 cbz r1, 8018348 <_reclaim_reent+0x50> 8018342: 4620 mov r0, r4 8018344: f000 f868 bl 8018418 <_free_r> 8018348: 6b21 ldr r1, [r4, #48] @ 0x30 801834a: b111 cbz r1, 8018352 <_reclaim_reent+0x5a> 801834c: 4620 mov r0, r4 801834e: f000 f863 bl 8018418 <_free_r> 8018352: 6b61 ldr r1, [r4, #52] @ 0x34 8018354: b111 cbz r1, 801835c <_reclaim_reent+0x64> 8018356: 4620 mov r0, r4 8018358: f000 f85e bl 8018418 <_free_r> 801835c: 6ba1 ldr r1, [r4, #56] @ 0x38 801835e: b111 cbz r1, 8018366 <_reclaim_reent+0x6e> 8018360: 4620 mov r0, r4 8018362: f000 f859 bl 8018418 <_free_r> 8018366: 6ca1 ldr r1, [r4, #72] @ 0x48 8018368: b111 cbz r1, 8018370 <_reclaim_reent+0x78> 801836a: 4620 mov r0, r4 801836c: f000 f854 bl 8018418 <_free_r> 8018370: 6c61 ldr r1, [r4, #68] @ 0x44 8018372: b111 cbz r1, 801837a <_reclaim_reent+0x82> 8018374: 4620 mov r0, r4 8018376: f000 f84f bl 8018418 <_free_r> 801837a: 6ae1 ldr r1, [r4, #44] @ 0x2c 801837c: b111 cbz r1, 8018384 <_reclaim_reent+0x8c> 801837e: 4620 mov r0, r4 8018380: f000 f84a bl 8018418 <_free_r> 8018384: 6a23 ldr r3, [r4, #32] 8018386: b14b cbz r3, 801839c <_reclaim_reent+0xa4> 8018388: 4620 mov r0, r4 801838a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} 801838e: 4718 bx r3 8018390: 680e ldr r6, [r1, #0] 8018392: 4620 mov r0, r4 8018394: f000 f840 bl 8018418 <_free_r> 8018398: 4631 mov r1, r6 801839a: e7bb b.n 8018314 <_reclaim_reent+0x1c> 801839c: bd70 pop {r4, r5, r6, pc} 801839e: bf00 nop 80183a0: 24000048 .word 0x24000048 080183a4 <__errno>: 80183a4: 4b01 ldr r3, [pc, #4] @ (80183ac <__errno+0x8>) 80183a6: 6818 ldr r0, [r3, #0] 80183a8: 4770 bx lr 80183aa: bf00 nop 80183ac: 24000048 .word 0x24000048 080183b0 <__libc_init_array>: 80183b0: b570 push {r4, r5, r6, lr} 80183b2: 4d0d ldr r5, [pc, #52] @ (80183e8 <__libc_init_array+0x38>) 80183b4: 4c0d ldr r4, [pc, #52] @ (80183ec <__libc_init_array+0x3c>) 80183b6: 1b64 subs r4, r4, r5 80183b8: 10a4 asrs r4, r4, #2 80183ba: 2600 movs r6, #0 80183bc: 42a6 cmp r6, r4 80183be: d109 bne.n 80183d4 <__libc_init_array+0x24> 80183c0: 4d0b ldr r5, [pc, #44] @ (80183f0 <__libc_init_array+0x40>) 80183c2: 4c0c ldr r4, [pc, #48] @ (80183f4 <__libc_init_array+0x44>) 80183c4: f000 f920 bl 8018608 <_init> 80183c8: 1b64 subs r4, r4, r5 80183ca: 10a4 asrs r4, r4, #2 80183cc: 2600 movs r6, #0 80183ce: 42a6 cmp r6, r4 80183d0: d105 bne.n 80183de <__libc_init_array+0x2e> 80183d2: bd70 pop {r4, r5, r6, pc} 80183d4: f855 3b04 ldr.w r3, [r5], #4 80183d8: 4798 blx r3 80183da: 3601 adds r6, #1 80183dc: e7ee b.n 80183bc <__libc_init_array+0xc> 80183de: f855 3b04 ldr.w r3, [r5], #4 80183e2: 4798 blx r3 80183e4: 3601 adds r6, #1 80183e6: e7f2 b.n 80183ce <__libc_init_array+0x1e> 80183e8: 0801872c .word 0x0801872c 80183ec: 0801872c .word 0x0801872c 80183f0: 0801872c .word 0x0801872c 80183f4: 08018730 .word 0x08018730 080183f8 <__retarget_lock_acquire_recursive>: 80183f8: 4770 bx lr 080183fa <__retarget_lock_release_recursive>: 80183fa: 4770 bx lr 080183fc : 80183fc: 440a add r2, r1 80183fe: 4291 cmp r1, r2 8018400: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8018404: d100 bne.n 8018408 8018406: 4770 bx lr 8018408: b510 push {r4, lr} 801840a: f811 4b01 ldrb.w r4, [r1], #1 801840e: f803 4f01 strb.w r4, [r3, #1]! 8018412: 4291 cmp r1, r2 8018414: d1f9 bne.n 801840a 8018416: bd10 pop {r4, pc} 08018418 <_free_r>: 8018418: b538 push {r3, r4, r5, lr} 801841a: 4605 mov r5, r0 801841c: 2900 cmp r1, #0 801841e: d041 beq.n 80184a4 <_free_r+0x8c> 8018420: f851 3c04 ldr.w r3, [r1, #-4] 8018424: 1f0c subs r4, r1, #4 8018426: 2b00 cmp r3, #0 8018428: bfb8 it lt 801842a: 18e4 addlt r4, r4, r3 801842c: f000 f83e bl 80184ac <__malloc_lock> 8018430: 4a1d ldr r2, [pc, #116] @ (80184a8 <_free_r+0x90>) 8018432: 6813 ldr r3, [r2, #0] 8018434: b933 cbnz r3, 8018444 <_free_r+0x2c> 8018436: 6063 str r3, [r4, #4] 8018438: 6014 str r4, [r2, #0] 801843a: 4628 mov r0, r5 801843c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8018440: f000 b83a b.w 80184b8 <__malloc_unlock> 8018444: 42a3 cmp r3, r4 8018446: d908 bls.n 801845a <_free_r+0x42> 8018448: 6820 ldr r0, [r4, #0] 801844a: 1821 adds r1, r4, r0 801844c: 428b cmp r3, r1 801844e: bf01 itttt eq 8018450: 6819 ldreq r1, [r3, #0] 8018452: 685b ldreq r3, [r3, #4] 8018454: 1809 addeq r1, r1, r0 8018456: 6021 streq r1, [r4, #0] 8018458: e7ed b.n 8018436 <_free_r+0x1e> 801845a: 461a mov r2, r3 801845c: 685b ldr r3, [r3, #4] 801845e: b10b cbz r3, 8018464 <_free_r+0x4c> 8018460: 42a3 cmp r3, r4 8018462: d9fa bls.n 801845a <_free_r+0x42> 8018464: 6811 ldr r1, [r2, #0] 8018466: 1850 adds r0, r2, r1 8018468: 42a0 cmp r0, r4 801846a: d10b bne.n 8018484 <_free_r+0x6c> 801846c: 6820 ldr r0, [r4, #0] 801846e: 4401 add r1, r0 8018470: 1850 adds r0, r2, r1 8018472: 4283 cmp r3, r0 8018474: 6011 str r1, [r2, #0] 8018476: d1e0 bne.n 801843a <_free_r+0x22> 8018478: 6818 ldr r0, [r3, #0] 801847a: 685b ldr r3, [r3, #4] 801847c: 6053 str r3, [r2, #4] 801847e: 4408 add r0, r1 8018480: 6010 str r0, [r2, #0] 8018482: e7da b.n 801843a <_free_r+0x22> 8018484: d902 bls.n 801848c <_free_r+0x74> 8018486: 230c movs r3, #12 8018488: 602b str r3, [r5, #0] 801848a: e7d6 b.n 801843a <_free_r+0x22> 801848c: 6820 ldr r0, [r4, #0] 801848e: 1821 adds r1, r4, r0 8018490: 428b cmp r3, r1 8018492: bf04 itt eq 8018494: 6819 ldreq r1, [r3, #0] 8018496: 685b ldreq r3, [r3, #4] 8018498: 6063 str r3, [r4, #4] 801849a: bf04 itt eq 801849c: 1809 addeq r1, r1, r0 801849e: 6021 streq r1, [r4, #0] 80184a0: 6054 str r4, [r2, #4] 80184a2: e7ca b.n 801843a <_free_r+0x22> 80184a4: bd38 pop {r3, r4, r5, pc} 80184a6: bf00 nop 80184a8: 24013188 .word 0x24013188 080184ac <__malloc_lock>: 80184ac: 4801 ldr r0, [pc, #4] @ (80184b4 <__malloc_lock+0x8>) 80184ae: f7ff bfa3 b.w 80183f8 <__retarget_lock_acquire_recursive> 80184b2: bf00 nop 80184b4: 24013184 .word 0x24013184 080184b8 <__malloc_unlock>: 80184b8: 4801 ldr r0, [pc, #4] @ (80184c0 <__malloc_unlock+0x8>) 80184ba: f7ff bf9e b.w 80183fa <__retarget_lock_release_recursive> 80184be: bf00 nop 80184c0: 24013184 .word 0x24013184 080184c4 : 80184c4: b508 push {r3, lr} 80184c6: ed2d 8b02 vpush {d8} 80184ca: eef0 8a40 vmov.f32 s17, s0 80184ce: eeb0 8a60 vmov.f32 s16, s1 80184d2: f000 f817 bl 8018504 <__ieee754_fmodf> 80184d6: eef4 8a48 vcmp.f32 s17, s16 80184da: eef1 fa10 vmrs APSR_nzcv, fpscr 80184de: d60c bvs.n 80184fa 80184e0: eddf 8a07 vldr s17, [pc, #28] @ 8018500 80184e4: eeb4 8a68 vcmp.f32 s16, s17 80184e8: eef1 fa10 vmrs APSR_nzcv, fpscr 80184ec: d105 bne.n 80184fa 80184ee: f7ff ff59 bl 80183a4 <__errno> 80184f2: ee88 0aa8 vdiv.f32 s0, s17, s17 80184f6: 2321 movs r3, #33 @ 0x21 80184f8: 6003 str r3, [r0, #0] 80184fa: ecbd 8b02 vpop {d8} 80184fe: bd08 pop {r3, pc} 8018500: 00000000 .word 0x00000000 08018504 <__ieee754_fmodf>: 8018504: b5f0 push {r4, r5, r6, r7, lr} 8018506: ee10 5a90 vmov r5, s1 801850a: f025 4000 bic.w r0, r5, #2147483648 @ 0x80000000 801850e: 1e43 subs r3, r0, #1 8018510: f1b3 4fff cmp.w r3, #2139095040 @ 0x7f800000 8018514: d206 bcs.n 8018524 <__ieee754_fmodf+0x20> 8018516: ee10 3a10 vmov r3, s0 801851a: f023 4600 bic.w r6, r3, #2147483648 @ 0x80000000 801851e: f1b6 4fff cmp.w r6, #2139095040 @ 0x7f800000 8018522: d304 bcc.n 801852e <__ieee754_fmodf+0x2a> 8018524: ee60 0a20 vmul.f32 s1, s0, s1 8018528: ee80 0aa0 vdiv.f32 s0, s1, s1 801852c: bdf0 pop {r4, r5, r6, r7, pc} 801852e: 4286 cmp r6, r0 8018530: dbfc blt.n 801852c <__ieee754_fmodf+0x28> 8018532: f003 4400 and.w r4, r3, #2147483648 @ 0x80000000 8018536: d105 bne.n 8018544 <__ieee754_fmodf+0x40> 8018538: 4b32 ldr r3, [pc, #200] @ (8018604 <__ieee754_fmodf+0x100>) 801853a: eb03 7354 add.w r3, r3, r4, lsr #29 801853e: ed93 0a00 vldr s0, [r3] 8018542: e7f3 b.n 801852c <__ieee754_fmodf+0x28> 8018544: f013 4fff tst.w r3, #2139095040 @ 0x7f800000 8018548: d140 bne.n 80185cc <__ieee754_fmodf+0xc8> 801854a: 0232 lsls r2, r6, #8 801854c: f06f 017d mvn.w r1, #125 @ 0x7d 8018550: 2a00 cmp r2, #0 8018552: dc38 bgt.n 80185c6 <__ieee754_fmodf+0xc2> 8018554: f015 4fff tst.w r5, #2139095040 @ 0x7f800000 8018558: d13e bne.n 80185d8 <__ieee754_fmodf+0xd4> 801855a: 0207 lsls r7, r0, #8 801855c: f06f 027d mvn.w r2, #125 @ 0x7d 8018560: 2f00 cmp r7, #0 8018562: da36 bge.n 80185d2 <__ieee754_fmodf+0xce> 8018564: f111 0f7e cmn.w r1, #126 @ 0x7e 8018568: bfb9 ittee lt 801856a: f06f 037d mvnlt.w r3, #125 @ 0x7d 801856e: 1a5b sublt r3, r3, r1 8018570: f3c3 0316 ubfxge r3, r3, #0, #23 8018574: f443 0300 orrge.w r3, r3, #8388608 @ 0x800000 8018578: bfb8 it lt 801857a: fa06 f303 lsllt.w r3, r6, r3 801857e: f112 0f7e cmn.w r2, #126 @ 0x7e 8018582: bfb5 itete lt 8018584: f06f 057d mvnlt.w r5, #125 @ 0x7d 8018588: f3c5 0516 ubfxge r5, r5, #0, #23 801858c: 1aad sublt r5, r5, r2 801858e: f445 0000 orrge.w r0, r5, #8388608 @ 0x800000 8018592: bfb8 it lt 8018594: 40a8 lsllt r0, r5 8018596: 1a89 subs r1, r1, r2 8018598: 1a1d subs r5, r3, r0 801859a: bb01 cbnz r1, 80185de <__ieee754_fmodf+0xda> 801859c: ea13 0325 ands.w r3, r3, r5, asr #32 80185a0: bf38 it cc 80185a2: 462b movcc r3, r5 80185a4: 2b00 cmp r3, #0 80185a6: d0c7 beq.n 8018538 <__ieee754_fmodf+0x34> 80185a8: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 80185ac: db1f blt.n 80185ee <__ieee754_fmodf+0xea> 80185ae: f112 0f7e cmn.w r2, #126 @ 0x7e 80185b2: db1f blt.n 80185f4 <__ieee754_fmodf+0xf0> 80185b4: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 80185b8: 327f adds r2, #127 @ 0x7f 80185ba: 4323 orrs r3, r4 80185bc: ea43 53c2 orr.w r3, r3, r2, lsl #23 80185c0: ee00 3a10 vmov s0, r3 80185c4: e7b2 b.n 801852c <__ieee754_fmodf+0x28> 80185c6: 3901 subs r1, #1 80185c8: 0052 lsls r2, r2, #1 80185ca: e7c1 b.n 8018550 <__ieee754_fmodf+0x4c> 80185cc: 15f1 asrs r1, r6, #23 80185ce: 397f subs r1, #127 @ 0x7f 80185d0: e7c0 b.n 8018554 <__ieee754_fmodf+0x50> 80185d2: 3a01 subs r2, #1 80185d4: 007f lsls r7, r7, #1 80185d6: e7c3 b.n 8018560 <__ieee754_fmodf+0x5c> 80185d8: 15c2 asrs r2, r0, #23 80185da: 3a7f subs r2, #127 @ 0x7f 80185dc: e7c2 b.n 8018564 <__ieee754_fmodf+0x60> 80185de: 2d00 cmp r5, #0 80185e0: da02 bge.n 80185e8 <__ieee754_fmodf+0xe4> 80185e2: 005b lsls r3, r3, #1 80185e4: 3901 subs r1, #1 80185e6: e7d7 b.n 8018598 <__ieee754_fmodf+0x94> 80185e8: d0a6 beq.n 8018538 <__ieee754_fmodf+0x34> 80185ea: 006b lsls r3, r5, #1 80185ec: e7fa b.n 80185e4 <__ieee754_fmodf+0xe0> 80185ee: 005b lsls r3, r3, #1 80185f0: 3a01 subs r2, #1 80185f2: e7d9 b.n 80185a8 <__ieee754_fmodf+0xa4> 80185f4: f1c2 22ff rsb r2, r2, #4278255360 @ 0xff00ff00 80185f8: f502 027f add.w r2, r2, #16711680 @ 0xff0000 80185fc: 3282 adds r2, #130 @ 0x82 80185fe: 4113 asrs r3, r2 8018600: 4323 orrs r3, r4 8018602: e7dd b.n 80185c0 <__ieee754_fmodf+0xbc> 8018604: 0801871c .word 0x0801871c 08018608 <_init>: 8018608: b5f8 push {r3, r4, r5, r6, r7, lr} 801860a: bf00 nop 801860c: bcf8 pop {r3, r4, r5, r6, r7} 801860e: bc08 pop {r3} 8018610: 469e mov lr, r3 8018612: 4770 bx lr 08018614 <_fini>: 8018614: b5f8 push {r3, r4, r5, r6, r7, lr} 8018616: bf00 nop 8018618: bcf8 pop {r3, r4, r5, r6, r7} 801861a: bc08 pop {r3} 801861c: 469e mov lr, r3 801861e: 4770 bx lr